From 76b6bb36f8d31a383c99b4a09b078e2086ea1427 Mon Sep 17 00:00:00 2001 From: Theodor Chikin Date: Thu, 18 Sep 2025 16:54:16 +0300 Subject: [PATCH] added build folder. Now compilde binary becomes available in git --- build/File_Handling.d | 108 + build/File_Handling.lst | 3501 +++ build/File_Handling.o | Bin 0 -> 34784 bytes build/For_stm32.bin | Bin 0 -> 44412 bytes build/For_stm32.elf | Bin 0 -> 730904 bytes build/For_stm32.hex | 2782 +++ build/For_stm32.map | 5297 +++++ build/bsp_driver_sd.d | 70 + build/bsp_driver_sd.lst | 1072 + build/bsp_driver_sd.o | Bin 0 -> 19808 bytes build/diskio.d | 104 + build/diskio.lst | 473 + build/diskio.o | Bin 0 -> 9212 bytes build/fatfs.d | 107 + build/fatfs.lst | 193 + build/fatfs.o | Bin 0 -> 6788 bytes build/fatfs_platform.d | 68 + build/fatfs_platform.lst | 119 + build/fatfs_platform.o | Bin 0 -> 4024 bytes build/ff.d | 101 + build/ff.lst | 22719 +++++++++++++++++++ build/ff.o | Bin 0 -> 130972 bytes build/ff_gen_drv.d | 104 + build/ff_gen_drv.lst | 474 + build/ff_gen_drv.o | Bin 0 -> 9024 bytes build/main.d | 112 + build/main.lst | 34295 +++++++++++++++++++++++++++++ build/main.o | Bin 0 -> 134592 bytes build/sd_diskio.d | 105 + build/sd_diskio.lst | 742 + build/sd_diskio.o | Bin 0 -> 11816 bytes build/startup_stm32f767xx.d | 1 + build/startup_stm32f767xx.o | Bin 0 -> 8360 bytes build/stm32f7xx_hal.d | 67 + build/stm32f7xx_hal.lst | 1817 ++ build/stm32f7xx_hal.o | Bin 0 -> 22260 bytes build/stm32f7xx_hal_adc.d | 68 + build/stm32f7xx_hal_adc.lst | 6376 ++++++ build/stm32f7xx_hal_adc.o | Bin 0 -> 32704 bytes build/stm32f7xx_hal_adc_ex.d | 68 + build/stm32f7xx_hal_adc_ex.lst | 4040 ++++ build/stm32f7xx_hal_adc_ex.o | Bin 0 -> 25984 bytes build/stm32f7xx_hal_cortex.d | 68 + build/stm32f7xx_hal_cortex.lst | 5769 +++++ build/stm32f7xx_hal_cortex.o | Bin 0 -> 28472 bytes build/stm32f7xx_hal_dma.d | 68 + build/stm32f7xx_hal_dma.lst | 4646 ++++ build/stm32f7xx_hal_dma.o | Bin 0 -> 26424 bytes build/stm32f7xx_hal_dma_ex.d | 68 + build/stm32f7xx_hal_dma_ex.lst | 3762 ++++ build/stm32f7xx_hal_dma_ex.o | Bin 0 -> 17248 bytes build/stm32f7xx_hal_exti.d | 68 + build/stm32f7xx_hal_exti.lst | 1554 ++ build/stm32f7xx_hal_exti.o | Bin 0 -> 12992 bytes build/stm32f7xx_hal_flash.d | 68 + build/stm32f7xx_hal_flash.lst | 3466 +++ build/stm32f7xx_hal_flash.o | Bin 0 -> 17536 bytes build/stm32f7xx_hal_flash_ex.d | 68 + build/stm32f7xx_hal_flash_ex.lst | 3759 ++++ build/stm32f7xx_hal_flash_ex.o | Bin 0 -> 20680 bytes build/stm32f7xx_hal_gpio.d | 68 + build/stm32f7xx_hal_gpio.lst | 1814 ++ build/stm32f7xx_hal_gpio.o | Bin 0 -> 14484 bytes build/stm32f7xx_hal_i2c.d | 68 + build/stm32f7xx_hal_i2c.lst | 28773 ++++++++++++++++++++++++ build/stm32f7xx_hal_i2c.o | Bin 0 -> 148608 bytes build/stm32f7xx_hal_i2c_ex.d | 68 + build/stm32f7xx_hal_i2c_ex.lst | 634 + build/stm32f7xx_hal_i2c_ex.o | Bin 0 -> 11256 bytes build/stm32f7xx_hal_msp.d | 92 + build/stm32f7xx_hal_msp.lst | 2263 ++ build/stm32f7xx_hal_msp.o | Bin 0 -> 32220 bytes build/stm32f7xx_hal_pwr.d | 68 + build/stm32f7xx_hal_pwr.lst | 2379 ++ build/stm32f7xx_hal_pwr.o | Bin 0 -> 13612 bytes build/stm32f7xx_hal_pwr_ex.d | 68 + build/stm32f7xx_hal_pwr_ex.lst | 1648 ++ build/stm32f7xx_hal_pwr_ex.o | Bin 0 -> 16236 bytes build/stm32f7xx_hal_rcc.d | 68 + build/stm32f7xx_hal_rcc.lst | 5244 +++++ build/stm32f7xx_hal_rcc.o | Bin 0 -> 24432 bytes build/stm32f7xx_hal_rcc_ex.d | 68 + build/stm32f7xx_hal_rcc_ex.lst | 4544 ++++ build/stm32f7xx_hal_rcc_ex.o | Bin 0 -> 20860 bytes build/stm32f7xx_hal_sd.d | 68 + build/stm32f7xx_hal_sd.lst | 12948 +++++++++++ build/stm32f7xx_hal_sd.o | Bin 0 -> 75156 bytes build/stm32f7xx_hal_tim.d | 68 + build/stm32f7xx_hal_tim.lst | 29972 +++++++++++++++++++++++++ build/stm32f7xx_hal_tim.o | Bin 0 -> 160408 bytes build/stm32f7xx_hal_tim_ex.d | 68 + build/stm32f7xx_hal_tim_ex.lst | 10691 +++++++++ build/stm32f7xx_hal_tim_ex.o | Bin 0 -> 67256 bytes build/stm32f7xx_hal_uart.d | 68 + build/stm32f7xx_hal_uart.lst | 20279 +++++++++++++++++ build/stm32f7xx_hal_uart.o | Bin 0 -> 129304 bytes build/stm32f7xx_hal_uart_ex.d | 68 + build/stm32f7xx_hal_uart_ex.lst | 3980 ++++ build/stm32f7xx_hal_uart_ex.o | Bin 0 -> 26092 bytes build/stm32f7xx_it.d | 93 + build/stm32f7xx_it.lst | 13989 ++++++++++++ build/stm32f7xx_it.o | Bin 0 -> 28160 bytes build/stm32f7xx_ll_dma.d | 72 + build/stm32f7xx_ll_dma.lst | 3506 +++ build/stm32f7xx_ll_dma.o | Bin 0 -> 14784 bytes build/stm32f7xx_ll_exti.d | 70 + build/stm32f7xx_ll_exti.lst | 1533 ++ build/stm32f7xx_ll_exti.o | Bin 0 -> 8940 bytes build/stm32f7xx_ll_gpio.d | 72 + build/stm32f7xx_ll_gpio.lst | 3966 ++++ build/stm32f7xx_ll_gpio.o | Bin 0 -> 19376 bytes build/stm32f7xx_ll_rcc.d | 70 + build/stm32f7xx_ll_rcc.lst | 11469 ++++++++++ build/stm32f7xx_ll_rcc.o | Bin 0 -> 48784 bytes build/stm32f7xx_ll_sdmmc.d | 68 + build/stm32f7xx_ll_sdmmc.lst | 6063 +++++ build/stm32f7xx_ll_sdmmc.o | Bin 0 -> 47424 bytes build/stm32f7xx_ll_spi.d | 74 + build/stm32f7xx_ll_spi.lst | 5233 +++++ build/stm32f7xx_ll_spi.o | Bin 0 -> 15748 bytes build/stm32f7xx_ll_tim.d | 72 + build/stm32f7xx_ll_tim.lst | 11811 ++++++++++ build/stm32f7xx_ll_tim.o | Bin 0 -> 41128 bytes build/stm32f7xx_ll_usart.d | 74 + build/stm32f7xx_ll_usart.lst | 5295 +++++ build/stm32f7xx_ll_usart.o | Bin 0 -> 17516 bytes build/stm32f7xx_ll_utils.d | 76 + build/stm32f7xx_ll_utils.lst | 8356 +++++++ build/stm32f7xx_ll_utils.o | Bin 0 -> 20452 bytes build/syscall.d | 100 + build/syscall.lst | 33 + build/syscall.o | Bin 0 -> 2620 bytes build/syscalls.d | 1 + build/syscalls.lst | 871 + build/syscalls.o | Bin 0 -> 14908 bytes build/sysmem.d | 1 + build/sysmem.lst | 231 + build/sysmem.o | Bin 0 -> 4132 bytes build/system_stm32f7xx.d | 67 + build/system_stm32f7xx.lst | 569 + build/system_stm32f7xx.o | Bin 0 -> 8312 bytes 141 files changed, 308259 insertions(+) create mode 100644 build/File_Handling.d create mode 100644 build/File_Handling.lst create mode 100644 build/File_Handling.o create mode 100755 build/For_stm32.bin create mode 100755 build/For_stm32.elf create mode 100644 build/For_stm32.hex create mode 100644 build/For_stm32.map create mode 100644 build/bsp_driver_sd.d create mode 100644 build/bsp_driver_sd.lst create mode 100644 build/bsp_driver_sd.o create mode 100644 build/diskio.d create mode 100644 build/diskio.lst create mode 100644 build/diskio.o create mode 100644 build/fatfs.d create mode 100644 build/fatfs.lst create mode 100644 build/fatfs.o create mode 100644 build/fatfs_platform.d create mode 100644 build/fatfs_platform.lst create mode 100644 build/fatfs_platform.o create mode 100644 build/ff.d create mode 100644 build/ff.lst create mode 100644 build/ff.o create mode 100644 build/ff_gen_drv.d create mode 100644 build/ff_gen_drv.lst create mode 100644 build/ff_gen_drv.o create mode 100644 build/main.d create mode 100644 build/main.lst create mode 100644 build/main.o create mode 100644 build/sd_diskio.d create mode 100644 build/sd_diskio.lst create mode 100644 build/sd_diskio.o create mode 100644 build/startup_stm32f767xx.d create mode 100644 build/startup_stm32f767xx.o create mode 100644 build/stm32f7xx_hal.d create mode 100644 build/stm32f7xx_hal.lst create mode 100644 build/stm32f7xx_hal.o create mode 100644 build/stm32f7xx_hal_adc.d create mode 100644 build/stm32f7xx_hal_adc.lst create mode 100644 build/stm32f7xx_hal_adc.o create mode 100644 build/stm32f7xx_hal_adc_ex.d create mode 100644 build/stm32f7xx_hal_adc_ex.lst create mode 100644 build/stm32f7xx_hal_adc_ex.o create mode 100644 build/stm32f7xx_hal_cortex.d create mode 100644 build/stm32f7xx_hal_cortex.lst create mode 100644 build/stm32f7xx_hal_cortex.o create mode 100644 build/stm32f7xx_hal_dma.d create mode 100644 build/stm32f7xx_hal_dma.lst create mode 100644 build/stm32f7xx_hal_dma.o create mode 100644 build/stm32f7xx_hal_dma_ex.d create mode 100644 build/stm32f7xx_hal_dma_ex.lst create mode 100644 build/stm32f7xx_hal_dma_ex.o create mode 100644 build/stm32f7xx_hal_exti.d create mode 100644 build/stm32f7xx_hal_exti.lst create mode 100644 build/stm32f7xx_hal_exti.o create mode 100644 build/stm32f7xx_hal_flash.d create mode 100644 build/stm32f7xx_hal_flash.lst create mode 100644 build/stm32f7xx_hal_flash.o create mode 100644 build/stm32f7xx_hal_flash_ex.d create mode 100644 build/stm32f7xx_hal_flash_ex.lst create mode 100644 build/stm32f7xx_hal_flash_ex.o create mode 100644 build/stm32f7xx_hal_gpio.d create mode 100644 build/stm32f7xx_hal_gpio.lst create mode 100644 build/stm32f7xx_hal_gpio.o create mode 100644 build/stm32f7xx_hal_i2c.d create mode 100644 build/stm32f7xx_hal_i2c.lst create mode 100644 build/stm32f7xx_hal_i2c.o create mode 100644 build/stm32f7xx_hal_i2c_ex.d create mode 100644 build/stm32f7xx_hal_i2c_ex.lst create mode 100644 build/stm32f7xx_hal_i2c_ex.o create mode 100644 build/stm32f7xx_hal_msp.d create mode 100644 build/stm32f7xx_hal_msp.lst create mode 100644 build/stm32f7xx_hal_msp.o create mode 100644 build/stm32f7xx_hal_pwr.d create mode 100644 build/stm32f7xx_hal_pwr.lst create mode 100644 build/stm32f7xx_hal_pwr.o create mode 100644 build/stm32f7xx_hal_pwr_ex.d create mode 100644 build/stm32f7xx_hal_pwr_ex.lst create mode 100644 build/stm32f7xx_hal_pwr_ex.o create mode 100644 build/stm32f7xx_hal_rcc.d create mode 100644 build/stm32f7xx_hal_rcc.lst create mode 100644 build/stm32f7xx_hal_rcc.o create mode 100644 build/stm32f7xx_hal_rcc_ex.d create mode 100644 build/stm32f7xx_hal_rcc_ex.lst create mode 100644 build/stm32f7xx_hal_rcc_ex.o create mode 100644 build/stm32f7xx_hal_sd.d create mode 100644 build/stm32f7xx_hal_sd.lst create mode 100644 build/stm32f7xx_hal_sd.o create mode 100644 build/stm32f7xx_hal_tim.d create mode 100644 build/stm32f7xx_hal_tim.lst create mode 100644 build/stm32f7xx_hal_tim.o create mode 100644 build/stm32f7xx_hal_tim_ex.d create mode 100644 build/stm32f7xx_hal_tim_ex.lst create mode 100644 build/stm32f7xx_hal_tim_ex.o create mode 100644 build/stm32f7xx_hal_uart.d create mode 100644 build/stm32f7xx_hal_uart.lst create mode 100644 build/stm32f7xx_hal_uart.o create mode 100644 build/stm32f7xx_hal_uart_ex.d create mode 100644 build/stm32f7xx_hal_uart_ex.lst create mode 100644 build/stm32f7xx_hal_uart_ex.o create mode 100644 build/stm32f7xx_it.d create mode 100644 build/stm32f7xx_it.lst create mode 100644 build/stm32f7xx_it.o create mode 100644 build/stm32f7xx_ll_dma.d create mode 100644 build/stm32f7xx_ll_dma.lst create mode 100644 build/stm32f7xx_ll_dma.o create mode 100644 build/stm32f7xx_ll_exti.d create mode 100644 build/stm32f7xx_ll_exti.lst create mode 100644 build/stm32f7xx_ll_exti.o create mode 100644 build/stm32f7xx_ll_gpio.d create mode 100644 build/stm32f7xx_ll_gpio.lst create mode 100644 build/stm32f7xx_ll_gpio.o create mode 100644 build/stm32f7xx_ll_rcc.d create mode 100644 build/stm32f7xx_ll_rcc.lst create mode 100644 build/stm32f7xx_ll_rcc.o create mode 100644 build/stm32f7xx_ll_sdmmc.d create mode 100644 build/stm32f7xx_ll_sdmmc.lst create mode 100644 build/stm32f7xx_ll_sdmmc.o create mode 100644 build/stm32f7xx_ll_spi.d create mode 100644 build/stm32f7xx_ll_spi.lst create mode 100644 build/stm32f7xx_ll_spi.o create mode 100644 build/stm32f7xx_ll_tim.d create mode 100644 build/stm32f7xx_ll_tim.lst create mode 100644 build/stm32f7xx_ll_tim.o create mode 100644 build/stm32f7xx_ll_usart.d create mode 100644 build/stm32f7xx_ll_usart.lst create mode 100644 build/stm32f7xx_ll_usart.o create mode 100644 build/stm32f7xx_ll_utils.d create mode 100644 build/stm32f7xx_ll_utils.lst create mode 100644 build/stm32f7xx_ll_utils.o create mode 100644 build/syscall.d create mode 100644 build/syscall.lst create mode 100644 build/syscall.o create mode 100644 build/syscalls.d create mode 100644 build/syscalls.lst create mode 100644 build/syscalls.o create mode 100644 build/sysmem.d create mode 100644 build/sysmem.lst create mode 100644 build/sysmem.o create mode 100644 build/system_stm32f7xx.d create mode 100644 build/system_stm32f7xx.lst create mode 100644 build/system_stm32f7xx.o diff --git a/build/File_Handling.d b/build/File_Handling.d new file mode 100644 index 0000000..08e22b9 --- /dev/null +++ b/build/File_Handling.d @@ -0,0 +1,108 @@ +build/File_Handling.o: Src/File_Handling.c Inc/File_Handling.h \ + Inc/fatfs.h Middlewares/Third_Party/FatFs/src/ff.h \ + Middlewares/Third_Party/FatFs/src/integer.h Inc/ffconf.h Inc/main.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h Inc/bsp_driver_sd.h \ + Inc/fatfs_platform.h Middlewares/Third_Party/FatFs/src/ff_gen_drv.h \ + Middlewares/Third_Party/FatFs/src/diskio.h \ + Middlewares/Third_Party/FatFs/src/ff.h Inc/sd_diskio.h +Inc/File_Handling.h: +Inc/fatfs.h: +Middlewares/Third_Party/FatFs/src/ff.h: +Middlewares/Third_Party/FatFs/src/integer.h: +Inc/ffconf.h: +Inc/main.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h: +Inc/bsp_driver_sd.h: +Inc/fatfs_platform.h: +Middlewares/Third_Party/FatFs/src/ff_gen_drv.h: +Middlewares/Third_Party/FatFs/src/diskio.h: +Middlewares/Third_Party/FatFs/src/ff.h: +Inc/sd_diskio.h: diff --git a/build/File_Handling.lst b/build/File_Handling.lst new file mode 100644 index 0000000..b614855 --- /dev/null +++ b/build/File_Handling.lst @@ -0,0 +1,3501 @@ +ARM GAS /tmp/cccCjqCZ.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "File_Handling.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Src/File_Handling.c" + 19 .section .text.Send_Uart,"ax",%progbits + 20 .align 1 + 21 .global Send_Uart + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 Send_Uart: + 27 .LVL0: + 28 .LFB1186: + 1:Src/File_Handling.c **** /* + 2:Src/File_Handling.c **** * File_Handling_RTOS.c + 3:Src/File_Handling.c **** * + 4:Src/File_Handling.c **** * Created on: 14-May-2020 + 5:Src/File_Handling.c **** * Author: Controllerstech + 6:Src/File_Handling.c **** */ + 7:Src/File_Handling.c **** + 8:Src/File_Handling.c **** #include + 9:Src/File_Handling.c **** #include "stm32f7xx_hal.h" + 10:Src/File_Handling.c **** + 11:Src/File_Handling.c **** #define UART USART1 + 12:Src/File_Handling.c **** + 13:Src/File_Handling.c **** + 14:Src/File_Handling.c **** + 15:Src/File_Handling.c **** /* =============================>>>>>>>> NO CHANGES AFTER THIS LINE =============================== + 16:Src/File_Handling.c **** + 17:Src/File_Handling.c **** FATFS fs; // file system + 18:Src/File_Handling.c **** FIL fil; // File + 19:Src/File_Handling.c **** FILINFO fno; + 20:Src/File_Handling.c **** extern FRESULT fresult; // result + 21:Src/File_Handling.c **** extern unsigned long sizeoffile; + 22:Src/File_Handling.c **** UINT br, bw; // File read/write count + 23:Src/File_Handling.c **** + 24:Src/File_Handling.c **** /**** capacity related *****/ + 25:Src/File_Handling.c **** FATFS *pfs; + 26:Src/File_Handling.c **** DWORD fre_clust; + 27:Src/File_Handling.c **** uint32_t total, free_space; + 28:Src/File_Handling.c **** + 29:Src/File_Handling.c **** + 30:Src/File_Handling.c **** void Send_Uart (char *string) + ARM GAS /tmp/cccCjqCZ.s page 2 + + + 31:Src/File_Handling.c **** { + 29 .loc 1 31 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 32:Src/File_Handling.c **** //HAL_UART_Transmit(UART, (uint8_t *)string, strlen (string), HAL_MAX_DELAY); + 33:Src/File_Handling.c **** } + 34 .loc 1 33 1 view .LVU1 + 35 0000 7047 bx lr + 36 .cfi_endproc + 37 .LFE1186: + 39 .section .text.Mount_SD,"ax",%progbits + 40 .align 1 + 41 .global Mount_SD + 42 .syntax unified + 43 .thumb + 44 .thumb_func + 46 Mount_SD: + 47 .LVL1: + 48 .LFB1187: + 34:Src/File_Handling.c **** + 35:Src/File_Handling.c **** + 36:Src/File_Handling.c **** + 37:Src/File_Handling.c **** int Mount_SD (const TCHAR* path) + 38:Src/File_Handling.c **** { + 49 .loc 1 38 1 view -0 + 50 .cfi_startproc + 51 @ args = 0, pretend = 0, frame = 0 + 52 @ frame_needed = 0, uses_anonymous_args = 0 + 53 .loc 1 38 1 is_stmt 0 view .LVU3 + 54 0000 08B5 push {r3, lr} + 55 .LCFI0: + 56 .cfi_def_cfa_offset 8 + 57 .cfi_offset 3, -8 + 58 .cfi_offset 14, -4 + 59 0002 0146 mov r1, r0 + 39:Src/File_Handling.c **** fresult = f_mount(&fs, path, 1); + 60 .loc 1 39 2 is_stmt 1 view .LVU4 + 61 .loc 1 39 12 is_stmt 0 view .LVU5 + 62 0004 0122 movs r2, #1 + 63 0006 0548 ldr r0, .L6 + 64 .LVL2: + 65 .loc 1 39 12 view .LVU6 + 66 0008 FFF7FEFF bl f_mount + 67 .LVL3: + 68 .loc 1 39 10 discriminator 1 view .LVU7 + 69 000c 044B ldr r3, .L6+4 + 70 000e 1870 strb r0, [r3] + 40:Src/File_Handling.c **** if (fresult != FR_OK) return 1; + 71 .loc 1 40 2 is_stmt 1 view .LVU8 + 72 .loc 1 40 5 is_stmt 0 view .LVU9 + 73 0010 08B1 cbz r0, .L4 + 74 .loc 1 40 31 discriminator 1 view .LVU10 + 75 0012 0120 movs r0, #1 + 76 .L2: + 41:Src/File_Handling.c **** else return 0; + ARM GAS /tmp/cccCjqCZ.s page 3 + + + 42:Src/File_Handling.c **** } + 77 .loc 1 42 1 view .LVU11 + 78 0014 08BD pop {r3, pc} + 79 .L4: + 41:Src/File_Handling.c **** else return 0; + 80 .loc 1 41 14 view .LVU12 + 81 0016 0020 movs r0, #0 + 82 0018 FCE7 b .L2 + 83 .L7: + 84 001a 00BF .align 2 + 85 .L6: + 86 001c 00000000 .word fs + 87 0020 00000000 .word fresult + 88 .cfi_endproc + 89 .LFE1187: + 91 .section .text.Unmount_SD,"ax",%progbits + 92 .align 1 + 93 .global Unmount_SD + 94 .syntax unified + 95 .thumb + 96 .thumb_func + 98 Unmount_SD: + 99 .LVL4: + 100 .LFB1188: + 43:Src/File_Handling.c **** + 44:Src/File_Handling.c **** int Unmount_SD (const TCHAR* path) + 45:Src/File_Handling.c **** { + 101 .loc 1 45 1 is_stmt 1 view -0 + 102 .cfi_startproc + 103 @ args = 0, pretend = 0, frame = 0 + 104 @ frame_needed = 0, uses_anonymous_args = 0 + 105 .loc 1 45 1 is_stmt 0 view .LVU14 + 106 0000 08B5 push {r3, lr} + 107 .LCFI1: + 108 .cfi_def_cfa_offset 8 + 109 .cfi_offset 3, -8 + 110 .cfi_offset 14, -4 + 111 0002 0146 mov r1, r0 + 46:Src/File_Handling.c **** fresult = f_mount(NULL, path, 1); + 112 .loc 1 46 2 is_stmt 1 view .LVU15 + 113 .loc 1 46 12 is_stmt 0 view .LVU16 + 114 0004 0122 movs r2, #1 + 115 0006 0020 movs r0, #0 + 116 .LVL5: + 117 .loc 1 46 12 view .LVU17 + 118 0008 FFF7FEFF bl f_mount + 119 .LVL6: + 120 .loc 1 46 10 discriminator 1 view .LVU18 + 121 000c 034B ldr r3, .L12 + 122 000e 1870 strb r0, [r3] + 47:Src/File_Handling.c **** if (fresult == FR_OK) return 0;//Send_Uart ("SD CARD UNMOUNTED successfully...\n\n\n"); + 123 .loc 1 47 2 is_stmt 1 view .LVU19 + 124 .loc 1 47 5 is_stmt 0 view .LVU20 + 125 0010 08B1 cbz r0, .L10 + 48:Src/File_Handling.c **** return 1;//else Send_Uart("ERROR!!! in UNMOUNTING SD CARD\n\n\n"); + 126 .loc 1 48 9 view .LVU21 + 127 0012 0120 movs r0, #1 + ARM GAS /tmp/cccCjqCZ.s page 4 + + + 128 .L8: + 49:Src/File_Handling.c **** } + 129 .loc 1 49 1 view .LVU22 + 130 0014 08BD pop {r3, pc} + 131 .L10: + 47:Src/File_Handling.c **** if (fresult == FR_OK) return 0;//Send_Uart ("SD CARD UNMOUNTED successfully...\n\n\n"); + 132 .loc 1 47 31 discriminator 1 view .LVU23 + 133 0016 0020 movs r0, #0 + 134 0018 FCE7 b .L8 + 135 .L13: + 136 001a 00BF .align 2 + 137 .L12: + 138 001c 00000000 .word fresult + 139 .cfi_endproc + 140 .LFE1188: + 142 .section .rodata.Scan_SD.str1.4,"aMS",%progbits,1 + 143 .align 2 + 144 .LC0: + 145 0000 53595354 .ascii "SYSTEM~1\000" + 145 454D7E31 + 145 00 + 146 0009 000000 .align 2 + 147 .LC1: + 148 000c 4469723A .ascii "Dir: %s\015\012\000" + 148 2025730D + 148 0A00 + 149 0016 0000 .align 2 + 150 .LC2: + 151 0018 2F257300 .ascii "/%s\000" + 152 .align 2 + 153 .LC3: + 154 001c 46696C65 .ascii "File: %s/%s\012\000" + 154 3A202573 + 154 2F25730A + 154 00 + 155 .section .text.Scan_SD,"ax",%progbits + 156 .align 1 + 157 .global Scan_SD + 158 .syntax unified + 159 .thumb + 160 .thumb_func + 162 Scan_SD: + 163 .LVL7: + 164 .LFB1189: + 50:Src/File_Handling.c **** + 51:Src/File_Handling.c **** /* Start node to be scanned (***also used as work area***) */ + 52:Src/File_Handling.c **** FRESULT Scan_SD (char* pat) + 53:Src/File_Handling.c **** { + 165 .loc 1 53 1 is_stmt 1 view -0 + 166 .cfi_startproc + 167 @ args = 0, pretend = 0, frame = 48 + 168 @ frame_needed = 0, uses_anonymous_args = 0 + 169 .loc 1 53 1 is_stmt 0 view .LVU25 + 170 0000 70B5 push {r4, r5, r6, lr} + 171 .LCFI2: + 172 .cfi_def_cfa_offset 16 + 173 .cfi_offset 4, -16 + ARM GAS /tmp/cccCjqCZ.s page 5 + + + 174 .cfi_offset 5, -12 + 175 .cfi_offset 6, -8 + 176 .cfi_offset 14, -4 + 177 0002 8CB0 sub sp, sp, #48 + 178 .LCFI3: + 179 .cfi_def_cfa_offset 64 + 180 0004 0546 mov r5, r0 + 54:Src/File_Handling.c **** DIR dir; + 181 .loc 1 54 5 is_stmt 1 view .LVU26 + 55:Src/File_Handling.c **** UINT i; + 182 .loc 1 55 5 view .LVU27 + 56:Src/File_Handling.c **** char *path = malloc(20*sizeof (char)); + 183 .loc 1 56 5 view .LVU28 + 184 .loc 1 56 18 is_stmt 0 view .LVU29 + 185 0006 1420 movs r0, #20 + 186 .LVL8: + 187 .loc 1 56 18 view .LVU30 + 188 0008 FFF7FEFF bl malloc + 189 .LVL9: + 190 000c 0446 mov r4, r0 + 191 .LVL10: + 57:Src/File_Handling.c **** sprintf (path, "%s",pat); + 192 .loc 1 57 5 is_stmt 1 view .LVU31 + 193 000e 2946 mov r1, r5 + 194 0010 FFF7FEFF bl strcpy + 195 .LVL11: + 58:Src/File_Handling.c **** + 59:Src/File_Handling.c **** fresult = f_opendir(&dir, path); /* Open the directory */ + 196 .loc 1 59 5 view .LVU32 + 197 .loc 1 59 15 is_stmt 0 view .LVU33 + 198 0014 2146 mov r1, r4 + 199 0016 6846 mov r0, sp + 200 0018 FFF7FEFF bl f_opendir + 201 .LVL12: + 202 .loc 1 59 13 discriminator 1 view .LVU34 + 203 001c 264B ldr r3, .L21 + 204 001e 1870 strb r0, [r3] + 60:Src/File_Handling.c **** if (fresult == FR_OK) + 205 .loc 1 60 5 is_stmt 1 view .LVU35 + 206 .loc 1 60 8 is_stmt 0 view .LVU36 + 207 0020 0028 cmp r0, #0 + 208 0022 42D1 bne .L16 + 209 0024 0BE0 b .L15 + 210 .LVL13: + 211 .L18: + 212 .LBB2: + 61:Src/File_Handling.c **** { + 62:Src/File_Handling.c **** for (;;) + 63:Src/File_Handling.c **** { + 64:Src/File_Handling.c **** fresult = f_readdir(&dir, &fno); /* Read a directory item */ + 65:Src/File_Handling.c **** if (fresult != FR_OK || fno.fname[0] == 0) break; /* Break on error or end of dir */ + 66:Src/File_Handling.c **** if (fno.fattrib & AM_DIR) /* It is a directory */ + 67:Src/File_Handling.c **** { + 68:Src/File_Handling.c **** if (!(strcmp ("SYSTEM~1", fno.fname))) continue; + 69:Src/File_Handling.c **** char *buf = malloc(30*sizeof(char)); + 70:Src/File_Handling.c **** sprintf (buf, "Dir: %s\r\n", fno.fname); + 71:Src/File_Handling.c **** Send_Uart(buf); + ARM GAS /tmp/cccCjqCZ.s page 6 + + + 72:Src/File_Handling.c **** free(buf); + 73:Src/File_Handling.c **** i = strlen(path); + 74:Src/File_Handling.c **** sprintf(&path[i], "/%s", fno.fname); + 75:Src/File_Handling.c **** fresult = Scan_SD(path); /* Enter the directory */ + 76:Src/File_Handling.c **** if (fresult != FR_OK) break; + 77:Src/File_Handling.c **** path[i] = 0; + 78:Src/File_Handling.c **** } + 79:Src/File_Handling.c **** else + 80:Src/File_Handling.c **** { /* It is a file. */ + 81:Src/File_Handling.c **** char *buf = malloc(30*sizeof(char)); + 213 .loc 1 81 16 is_stmt 1 view .LVU37 + 214 .loc 1 81 28 is_stmt 0 view .LVU38 + 215 0026 1E20 movs r0, #30 + 216 0028 FFF7FEFF bl malloc + 217 .LVL14: + 218 002c 0546 mov r5, r0 + 219 .LVL15: + 82:Src/File_Handling.c **** sprintf(buf,"File: %s/%s\n", path, fno.fname); + 220 .loc 1 82 16 is_stmt 1 view .LVU39 + 221 002e 234B ldr r3, .L21+4 + 222 0030 2246 mov r2, r4 + 223 0032 2349 ldr r1, .L21+8 + 224 0034 FFF7FEFF bl sprintf + 225 .LVL16: + 83:Src/File_Handling.c **** Send_Uart(buf); + 226 .loc 1 83 16 view .LVU40 + 84:Src/File_Handling.c **** free(buf); + 227 .loc 1 84 16 view .LVU41 + 228 0038 2846 mov r0, r5 + 229 003a FFF7FEFF bl free + 230 .LVL17: + 231 .L15: + 232 .loc 1 84 16 is_stmt 0 view .LVU42 + 233 .LBE2: + 62:Src/File_Handling.c **** { + 234 .loc 1 62 9 is_stmt 1 view .LVU43 + 64:Src/File_Handling.c **** if (fresult != FR_OK || fno.fname[0] == 0) break; /* Break on error or end of dir */ + 235 .loc 1 64 13 view .LVU44 + 64:Src/File_Handling.c **** if (fresult != FR_OK || fno.fname[0] == 0) break; /* Break on error or end of dir */ + 236 .loc 1 64 23 is_stmt 0 view .LVU45 + 237 003e 2149 ldr r1, .L21+12 + 238 0040 6846 mov r0, sp + 239 0042 FFF7FEFF bl f_readdir + 240 .LVL18: + 64:Src/File_Handling.c **** if (fresult != FR_OK || fno.fname[0] == 0) break; /* Break on error or end of dir */ + 241 .loc 1 64 21 discriminator 1 view .LVU46 + 242 0046 1C4B ldr r3, .L21 + 243 0048 1870 strb r0, [r3] + 65:Src/File_Handling.c **** if (fno.fattrib & AM_DIR) /* It is a directory */ + 244 .loc 1 65 13 is_stmt 1 view .LVU47 + 65:Src/File_Handling.c **** if (fno.fattrib & AM_DIR) /* It is a directory */ + 245 .loc 1 65 16 is_stmt 0 view .LVU48 + 246 004a 58BB cbnz r0, .L17 + 65:Src/File_Handling.c **** if (fno.fattrib & AM_DIR) /* It is a directory */ + 247 .loc 1 65 46 discriminator 1 view .LVU49 + 248 004c 1D4B ldr r3, .L21+12 + 249 004e 5B7A ldrb r3, [r3, #9] @ zero_extendqisi2 + ARM GAS /tmp/cccCjqCZ.s page 7 + + + 65:Src/File_Handling.c **** if (fno.fattrib & AM_DIR) /* It is a directory */ + 250 .loc 1 65 34 discriminator 1 view .LVU50 + 251 0050 43B3 cbz r3, .L17 + 66:Src/File_Handling.c **** { + 252 .loc 1 66 13 is_stmt 1 view .LVU51 + 66:Src/File_Handling.c **** { + 253 .loc 1 66 20 is_stmt 0 view .LVU52 + 254 0052 1C4B ldr r3, .L21+12 + 255 0054 1B7A ldrb r3, [r3, #8] @ zero_extendqisi2 + 66:Src/File_Handling.c **** { + 256 .loc 1 66 16 view .LVU53 + 257 0056 13F0100F tst r3, #16 + 258 005a E4D0 beq .L18 + 259 .LBB3: + 68:Src/File_Handling.c **** char *buf = malloc(30*sizeof(char)); + 260 .loc 1 68 14 is_stmt 1 view .LVU54 + 68:Src/File_Handling.c **** char *buf = malloc(30*sizeof(char)); + 261 .loc 1 68 20 is_stmt 0 view .LVU55 + 262 005c 1749 ldr r1, .L21+4 + 263 005e 1A48 ldr r0, .L21+16 + 264 0060 FFF7FEFF bl strcmp + 265 .LVL19: + 68:Src/File_Handling.c **** char *buf = malloc(30*sizeof(char)); + 266 .loc 1 68 17 discriminator 1 view .LVU56 + 267 0064 0028 cmp r0, #0 + 268 0066 EAD0 beq .L15 + 69:Src/File_Handling.c **** sprintf (buf, "Dir: %s\r\n", fno.fname); + 269 .loc 1 69 14 is_stmt 1 view .LVU57 + 69:Src/File_Handling.c **** sprintf (buf, "Dir: %s\r\n", fno.fname); + 270 .loc 1 69 26 is_stmt 0 view .LVU58 + 271 0068 1E20 movs r0, #30 + 272 006a FFF7FEFF bl malloc + 273 .LVL20: + 274 006e 0546 mov r5, r0 + 275 .LVL21: + 70:Src/File_Handling.c **** Send_Uart(buf); + 276 .loc 1 70 14 is_stmt 1 view .LVU59 + 277 0070 124E ldr r6, .L21+4 + 278 0072 3246 mov r2, r6 + 279 0074 1549 ldr r1, .L21+20 + 280 0076 FFF7FEFF bl sprintf + 281 .LVL22: + 71:Src/File_Handling.c **** free(buf); + 282 .loc 1 71 14 view .LVU60 + 72:Src/File_Handling.c **** i = strlen(path); + 283 .loc 1 72 14 view .LVU61 + 284 007a 2846 mov r0, r5 + 285 007c FFF7FEFF bl free + 286 .LVL23: + 73:Src/File_Handling.c **** sprintf(&path[i], "/%s", fno.fname); + 287 .loc 1 73 17 view .LVU62 + 73:Src/File_Handling.c **** sprintf(&path[i], "/%s", fno.fname); + 288 .loc 1 73 21 is_stmt 0 view .LVU63 + 289 0080 2046 mov r0, r4 + 290 0082 FFF7FEFF bl strlen + 291 .LVL24: + 292 0086 0546 mov r5, r0 + ARM GAS /tmp/cccCjqCZ.s page 8 + + + 293 .LVL25: + 74:Src/File_Handling.c **** fresult = Scan_SD(path); /* Enter the directory */ + 294 .loc 1 74 17 is_stmt 1 view .LVU64 + 295 0088 3246 mov r2, r6 + 296 008a 1149 ldr r1, .L21+24 + 297 008c 2018 adds r0, r4, r0 + 298 .LVL26: + 74:Src/File_Handling.c **** fresult = Scan_SD(path); /* Enter the directory */ + 299 .loc 1 74 17 is_stmt 0 view .LVU65 + 300 008e FFF7FEFF bl sprintf + 301 .LVL27: + 75:Src/File_Handling.c **** if (fresult != FR_OK) break; + 302 .loc 1 75 17 is_stmt 1 view .LVU66 + 75:Src/File_Handling.c **** if (fresult != FR_OK) break; + 303 .loc 1 75 27 is_stmt 0 view .LVU67 + 304 0092 2046 mov r0, r4 + 305 0094 FFF7FEFF bl Scan_SD + 306 .LVL28: + 75:Src/File_Handling.c **** if (fresult != FR_OK) break; + 307 .loc 1 75 25 discriminator 1 view .LVU68 + 308 0098 074B ldr r3, .L21 + 309 009a 1870 strb r0, [r3] + 76:Src/File_Handling.c **** path[i] = 0; + 310 .loc 1 76 17 is_stmt 1 view .LVU69 + 76:Src/File_Handling.c **** path[i] = 0; + 311 .loc 1 76 20 is_stmt 0 view .LVU70 + 312 009c 10B9 cbnz r0, .L17 + 77:Src/File_Handling.c **** } + 313 .loc 1 77 17 is_stmt 1 view .LVU71 + 77:Src/File_Handling.c **** } + 314 .loc 1 77 25 is_stmt 0 view .LVU72 + 315 009e 0023 movs r3, #0 + 316 00a0 6355 strb r3, [r4, r5] + 317 .LBE3: + 318 00a2 CCE7 b .L15 + 319 .LVL29: + 320 .L17: + 85:Src/File_Handling.c **** } + 86:Src/File_Handling.c **** } + 87:Src/File_Handling.c **** f_closedir(&dir); + 321 .loc 1 87 9 is_stmt 1 view .LVU73 + 322 00a4 6846 mov r0, sp + 323 00a6 FFF7FEFF bl f_closedir + 324 .LVL30: + 325 .L16: + 88:Src/File_Handling.c **** } + 89:Src/File_Handling.c **** free(path); + 326 .loc 1 89 5 view .LVU74 + 327 00aa 2046 mov r0, r4 + 328 00ac FFF7FEFF bl free + 329 .LVL31: + 90:Src/File_Handling.c **** return fresult; + 330 .loc 1 90 5 view .LVU75 + 91:Src/File_Handling.c **** } + 331 .loc 1 91 1 is_stmt 0 view .LVU76 + 332 00b0 014B ldr r3, .L21 + 333 00b2 1878 ldrb r0, [r3] @ zero_extendqisi2 + ARM GAS /tmp/cccCjqCZ.s page 9 + + + 334 00b4 0CB0 add sp, sp, #48 + 335 .LCFI4: + 336 .cfi_def_cfa_offset 16 + 337 @ sp needed + 338 00b6 70BD pop {r4, r5, r6, pc} + 339 .LVL32: + 340 .L22: + 341 .loc 1 91 1 view .LVU77 + 342 .align 2 + 343 .L21: + 344 00b8 00000000 .word fresult + 345 00bc 09000000 .word fno+9 + 346 00c0 1C000000 .word .LC3 + 347 00c4 00000000 .word fno + 348 00c8 00000000 .word .LC0 + 349 00cc 0C000000 .word .LC1 + 350 00d0 18000000 .word .LC2 + 351 .cfi_endproc + 352 .LFE1189: + 354 .section .rodata.Format_SD.str1.4,"aMS",%progbits,1 + 355 .align 2 + 356 .LC4: + 357 0000 2F00 .ascii "/\000" + 358 .section .text.Format_SD,"ax",%progbits + 359 .align 1 + 360 .global Format_SD + 361 .syntax unified + 362 .thumb + 363 .thumb_func + 365 Format_SD: + 366 .LFB1190: + 92:Src/File_Handling.c **** + 93:Src/File_Handling.c **** /* Only supports removing files from home directory */ + 94:Src/File_Handling.c **** FRESULT Format_SD (void) + 95:Src/File_Handling.c **** { + 367 .loc 1 95 1 is_stmt 1 view -0 + 368 .cfi_startproc + 369 @ args = 0, pretend = 0, frame = 48 + 370 @ frame_needed = 0, uses_anonymous_args = 0 + 371 0000 10B5 push {r4, lr} + 372 .LCFI5: + 373 .cfi_def_cfa_offset 8 + 374 .cfi_offset 4, -8 + 375 .cfi_offset 14, -4 + 376 0002 8CB0 sub sp, sp, #48 + 377 .LCFI6: + 378 .cfi_def_cfa_offset 56 + 96:Src/File_Handling.c **** DIR dir; + 379 .loc 1 96 5 view .LVU79 + 97:Src/File_Handling.c **** char *path = malloc(20*sizeof (char)); + 380 .loc 1 97 5 view .LVU80 + 381 .loc 1 97 18 is_stmt 0 view .LVU81 + 382 0004 1420 movs r0, #20 + 383 0006 FFF7FEFF bl malloc + 384 .LVL33: + 385 000a 0446 mov r4, r0 + 386 .LVL34: + ARM GAS /tmp/cccCjqCZ.s page 10 + + + 98:Src/File_Handling.c **** sprintf (path, "%s","/"); + 387 .loc 1 98 5 is_stmt 1 view .LVU82 + 388 000c 1A4B ldr r3, .L30 + 389 000e 1B88 ldrh r3, [r3] @ unaligned + 390 0010 0380 strh r3, [r0] @ unaligned + 99:Src/File_Handling.c **** + 100:Src/File_Handling.c **** fresult = f_opendir(&dir, path); /* Open the directory */ + 391 .loc 1 100 5 view .LVU83 + 392 .loc 1 100 15 is_stmt 0 view .LVU84 + 393 0012 0146 mov r1, r0 + 394 0014 6846 mov r0, sp + 395 .LVL35: + 396 .loc 1 100 15 view .LVU85 + 397 0016 FFF7FEFF bl f_opendir + 398 .LVL36: + 399 .loc 1 100 13 discriminator 1 view .LVU86 + 400 001a 184B ldr r3, .L30+4 + 401 001c 1870 strb r0, [r3] + 101:Src/File_Handling.c **** if (fresult == FR_OK) + 402 .loc 1 101 5 is_stmt 1 view .LVU87 + 403 .loc 1 101 8 is_stmt 0 view .LVU88 + 404 001e 18BB cbnz r0, .L25 + 405 0020 04E0 b .L24 + 406 .L27: + 102:Src/File_Handling.c **** { + 103:Src/File_Handling.c **** for (;;) + 104:Src/File_Handling.c **** { + 105:Src/File_Handling.c **** fresult = f_readdir(&dir, &fno); /* Read a directory item */ + 106:Src/File_Handling.c **** if (fresult != FR_OK || fno.fname[0] == 0) break; /* Break on error or end of dir */ + 107:Src/File_Handling.c **** if (fno.fattrib & AM_DIR) /* It is a directory */ + 108:Src/File_Handling.c **** { + 109:Src/File_Handling.c **** if (!(strcmp ("SYSTEM~1", fno.fname))) continue; + 110:Src/File_Handling.c **** fresult = f_unlink(fno.fname); + 111:Src/File_Handling.c **** if (fresult == FR_DENIED) continue; + 112:Src/File_Handling.c **** } + 113:Src/File_Handling.c **** else + 114:Src/File_Handling.c **** { /* It is a file. */ + 115:Src/File_Handling.c **** fresult = f_unlink(fno.fname); + 407 .loc 1 115 16 is_stmt 1 view .LVU89 + 408 .loc 1 115 26 is_stmt 0 view .LVU90 + 409 0022 1748 ldr r0, .L30+8 + 410 0024 FFF7FEFF bl f_unlink + 411 .LVL37: + 412 .loc 1 115 24 discriminator 1 view .LVU91 + 413 0028 144B ldr r3, .L30+4 + 414 002a 1870 strb r0, [r3] + 415 .L24: + 103:Src/File_Handling.c **** { + 416 .loc 1 103 9 is_stmt 1 view .LVU92 + 105:Src/File_Handling.c **** if (fresult != FR_OK || fno.fname[0] == 0) break; /* Break on error or end of dir */ + 417 .loc 1 105 13 view .LVU93 + 105:Src/File_Handling.c **** if (fresult != FR_OK || fno.fname[0] == 0) break; /* Break on error or end of dir */ + 418 .loc 1 105 23 is_stmt 0 view .LVU94 + 419 002c 1549 ldr r1, .L30+12 + 420 002e 6846 mov r0, sp + 421 0030 FFF7FEFF bl f_readdir + 422 .LVL38: + ARM GAS /tmp/cccCjqCZ.s page 11 + + + 105:Src/File_Handling.c **** if (fresult != FR_OK || fno.fname[0] == 0) break; /* Break on error or end of dir */ + 423 .loc 1 105 21 discriminator 1 view .LVU95 + 424 0034 114B ldr r3, .L30+4 + 425 0036 1870 strb r0, [r3] + 106:Src/File_Handling.c **** if (fno.fattrib & AM_DIR) /* It is a directory */ + 426 .loc 1 106 13 is_stmt 1 view .LVU96 + 106:Src/File_Handling.c **** if (fno.fattrib & AM_DIR) /* It is a directory */ + 427 .loc 1 106 16 is_stmt 0 view .LVU97 + 428 0038 98B9 cbnz r0, .L26 + 106:Src/File_Handling.c **** if (fno.fattrib & AM_DIR) /* It is a directory */ + 429 .loc 1 106 46 discriminator 1 view .LVU98 + 430 003a 124B ldr r3, .L30+12 + 431 003c 5B7A ldrb r3, [r3, #9] @ zero_extendqisi2 + 106:Src/File_Handling.c **** if (fno.fattrib & AM_DIR) /* It is a directory */ + 432 .loc 1 106 34 discriminator 1 view .LVU99 + 433 003e 83B1 cbz r3, .L26 + 107:Src/File_Handling.c **** { + 434 .loc 1 107 13 is_stmt 1 view .LVU100 + 107:Src/File_Handling.c **** { + 435 .loc 1 107 20 is_stmt 0 view .LVU101 + 436 0040 104B ldr r3, .L30+12 + 437 0042 1B7A ldrb r3, [r3, #8] @ zero_extendqisi2 + 107:Src/File_Handling.c **** { + 438 .loc 1 107 16 view .LVU102 + 439 0044 13F0100F tst r3, #16 + 440 0048 EBD0 beq .L27 + 109:Src/File_Handling.c **** fresult = f_unlink(fno.fname); + 441 .loc 1 109 14 is_stmt 1 view .LVU103 + 109:Src/File_Handling.c **** fresult = f_unlink(fno.fname); + 442 .loc 1 109 20 is_stmt 0 view .LVU104 + 443 004a 0D49 ldr r1, .L30+8 + 444 004c 0E48 ldr r0, .L30+16 + 445 004e FFF7FEFF bl strcmp + 446 .LVL39: + 109:Src/File_Handling.c **** fresult = f_unlink(fno.fname); + 447 .loc 1 109 17 discriminator 1 view .LVU105 + 448 0052 0028 cmp r0, #0 + 449 0054 EAD0 beq .L24 + 110:Src/File_Handling.c **** if (fresult == FR_DENIED) continue; + 450 .loc 1 110 14 is_stmt 1 view .LVU106 + 110:Src/File_Handling.c **** if (fresult == FR_DENIED) continue; + 451 .loc 1 110 24 is_stmt 0 view .LVU107 + 452 0056 0A48 ldr r0, .L30+8 + 453 0058 FFF7FEFF bl f_unlink + 454 .LVL40: + 110:Src/File_Handling.c **** if (fresult == FR_DENIED) continue; + 455 .loc 1 110 22 discriminator 1 view .LVU108 + 456 005c 074B ldr r3, .L30+4 + 457 005e 1870 strb r0, [r3] + 111:Src/File_Handling.c **** } + 458 .loc 1 111 14 is_stmt 1 view .LVU109 + 111:Src/File_Handling.c **** } + 459 .loc 1 111 40 discriminator 1 view .LVU110 + 460 0060 E4E7 b .L24 + 461 .L26: + 116:Src/File_Handling.c **** } + 117:Src/File_Handling.c **** } + ARM GAS /tmp/cccCjqCZ.s page 12 + + + 118:Src/File_Handling.c **** f_closedir(&dir); + 462 .loc 1 118 9 view .LVU111 + 463 0062 6846 mov r0, sp + 464 0064 FFF7FEFF bl f_closedir + 465 .LVL41: + 466 .L25: + 119:Src/File_Handling.c **** } + 120:Src/File_Handling.c **** free(path); + 467 .loc 1 120 5 view .LVU112 + 468 0068 2046 mov r0, r4 + 469 006a FFF7FEFF bl free + 470 .LVL42: + 121:Src/File_Handling.c **** return fresult; + 471 .loc 1 121 5 view .LVU113 + 122:Src/File_Handling.c **** } + 472 .loc 1 122 1 is_stmt 0 view .LVU114 + 473 006e 034B ldr r3, .L30+4 + 474 0070 1878 ldrb r0, [r3] @ zero_extendqisi2 + 475 0072 0CB0 add sp, sp, #48 + 476 .LCFI7: + 477 .cfi_def_cfa_offset 8 + 478 @ sp needed + 479 0074 10BD pop {r4, pc} + 480 .LVL43: + 481 .L31: + 482 .loc 1 122 1 view .LVU115 + 483 0076 00BF .align 2 + 484 .L30: + 485 0078 00000000 .word .LC4 + 486 007c 00000000 .word fresult + 487 0080 09000000 .word fno+9 + 488 0084 00000000 .word fno + 489 0088 00000000 .word .LC0 + 490 .cfi_endproc + 491 .LFE1190: + 493 .section .text.Write_File,"ax",%progbits + 494 .align 1 + 495 .global Write_File + 496 .syntax unified + 497 .thumb + 498 .thumb_func + 500 Write_File: + 501 .LVL44: + 502 .LFB1191: + 123:Src/File_Handling.c **** + 124:Src/File_Handling.c **** + 125:Src/File_Handling.c **** + 126:Src/File_Handling.c **** + 127:Src/File_Handling.c **** FRESULT Write_File (char *name, char *data) + 128:Src/File_Handling.c **** { + 503 .loc 1 128 1 is_stmt 1 view -0 + 504 .cfi_startproc + 505 @ args = 0, pretend = 0, frame = 0 + 506 @ frame_needed = 0, uses_anonymous_args = 0 + 507 .loc 1 128 1 is_stmt 0 view .LVU117 + 508 0000 70B5 push {r4, r5, r6, lr} + 509 .LCFI8: + ARM GAS /tmp/cccCjqCZ.s page 13 + + + 510 .cfi_def_cfa_offset 16 + 511 .cfi_offset 4, -16 + 512 .cfi_offset 5, -12 + 513 .cfi_offset 6, -8 + 514 .cfi_offset 14, -4 + 515 0002 0446 mov r4, r0 + 516 0004 0D46 mov r5, r1 + 129:Src/File_Handling.c **** + 130:Src/File_Handling.c **** /**** check whether the file exists or not ****/ + 131:Src/File_Handling.c **** fresult = f_stat (name, &fno); + 517 .loc 1 131 2 is_stmt 1 view .LVU118 + 518 .loc 1 131 12 is_stmt 0 view .LVU119 + 519 0006 1249 ldr r1, .L37 + 520 .LVL45: + 521 .loc 1 131 12 view .LVU120 + 522 0008 FFF7FEFF bl f_stat + 523 .LVL46: + 524 .loc 1 131 10 discriminator 1 view .LVU121 + 525 000c 114B ldr r3, .L37+4 + 526 000e 1870 strb r0, [r3] + 132:Src/File_Handling.c **** if (fresult != FR_OK) + 527 .loc 1 132 2 is_stmt 1 view .LVU122 + 528 .loc 1 132 5 is_stmt 0 view .LVU123 + 529 0010 08B1 cbz r0, .L33 + 530 .LBB4: + 133:Src/File_Handling.c **** { + 134:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 531 .loc 1 134 3 is_stmt 1 view .LVU124 + 135:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! *%s* does not exists\n\n", name); + 136:Src/File_Handling.c **** //Send_Uart (buf); + 137:Src/File_Handling.c **** free(buf); + 532 .loc 1 137 6 view .LVU125 + 138:Src/File_Handling.c **** return fresult; + 533 .loc 1 138 6 view .LVU126 + 534 .loc 1 138 13 is_stmt 0 view .LVU127 + 535 0012 C0B2 uxtb r0, r0 + 536 .LVL47: + 537 .L34: + 538 .loc 1 138 13 view .LVU128 + 539 .LBE4: + 139:Src/File_Handling.c **** } + 140:Src/File_Handling.c **** + 141:Src/File_Handling.c **** else + 142:Src/File_Handling.c **** { + 143:Src/File_Handling.c **** /* Create a file with read write access and open it */ + 144:Src/File_Handling.c **** fresult = f_open(&fil, name, FA_OPEN_EXISTING | FA_WRITE); + 145:Src/File_Handling.c **** if (fresult != FR_OK) + 146:Src/File_Handling.c **** { + 147:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 148:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name); + 149:Src/File_Handling.c **** //Send_Uart(buf); + 150:Src/File_Handling.c **** free(buf); + 151:Src/File_Handling.c **** return fresult; + 152:Src/File_Handling.c **** } + 153:Src/File_Handling.c **** + 154:Src/File_Handling.c **** else + 155:Src/File_Handling.c **** { + ARM GAS /tmp/cccCjqCZ.s page 14 + + + 156:Src/File_Handling.c **** fresult = f_write(&fil, data, strlen(data), &bw); + 157:Src/File_Handling.c **** if (fresult != FR_OK) + 158:Src/File_Handling.c **** { + 159:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 160:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d while writing to the FILE *%s*\n\n", fresult, name); + 161:Src/File_Handling.c **** //Send_Uart(buf); + 162:Src/File_Handling.c **** free(buf); + 163:Src/File_Handling.c **** } + 164:Src/File_Handling.c **** + 165:Src/File_Handling.c **** /* Close file */ + 166:Src/File_Handling.c **** fresult = f_close(&fil); + 167:Src/File_Handling.c **** if (fresult != FR_OK) + 168:Src/File_Handling.c **** { + 169:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 170:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in closing file *%s* after writing it\n\n", fresult, name); + 171:Src/File_Handling.c **** //Send_Uart(buf); + 172:Src/File_Handling.c **** free(buf); + 173:Src/File_Handling.c **** } + 174:Src/File_Handling.c **** else + 175:Src/File_Handling.c **** { + 176:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 177:Src/File_Handling.c **** //sprintf (buf, "File *%s* is WRITTEN and CLOSED successfully\n", name); + 178:Src/File_Handling.c **** //Send_Uart(buf); + 179:Src/File_Handling.c **** free(buf); + 180:Src/File_Handling.c **** } + 181:Src/File_Handling.c **** } + 182:Src/File_Handling.c **** return fresult; + 183:Src/File_Handling.c **** } + 184:Src/File_Handling.c **** } + 540 .loc 1 184 1 view .LVU129 + 541 0014 70BD pop {r4, r5, r6, pc} + 542 .LVL48: + 543 .L33: + 144:Src/File_Handling.c **** if (fresult != FR_OK) + 544 .loc 1 144 6 is_stmt 1 view .LVU130 + 144:Src/File_Handling.c **** if (fresult != FR_OK) + 545 .loc 1 144 16 is_stmt 0 view .LVU131 + 546 0016 0222 movs r2, #2 + 547 0018 2146 mov r1, r4 + 548 001a 0F48 ldr r0, .L37+8 + 549 001c FFF7FEFF bl f_open + 550 .LVL49: + 144:Src/File_Handling.c **** if (fresult != FR_OK) + 551 .loc 1 144 14 discriminator 1 view .LVU132 + 552 0020 0C4B ldr r3, .L37+4 + 553 0022 1870 strb r0, [r3] + 145:Src/File_Handling.c **** { + 554 .loc 1 145 6 is_stmt 1 view .LVU133 + 145:Src/File_Handling.c **** { + 555 .loc 1 145 9 is_stmt 0 view .LVU134 + 556 0024 08B1 cbz r0, .L35 + 557 .LBB5: + 147:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name); + 558 .loc 1 147 7 is_stmt 1 view .LVU135 + 150:Src/File_Handling.c **** return fresult; + 559 .loc 1 150 10 view .LVU136 + 151:Src/File_Handling.c **** } + ARM GAS /tmp/cccCjqCZ.s page 15 + + + 560 .loc 1 151 10 view .LVU137 + 151:Src/File_Handling.c **** } + 561 .loc 1 151 17 is_stmt 0 view .LVU138 + 562 0026 C0B2 uxtb r0, r0 + 563 0028 F4E7 b .L34 + 564 .L35: + 565 .LBE5: + 156:Src/File_Handling.c **** if (fresult != FR_OK) + 566 .loc 1 156 7 is_stmt 1 view .LVU139 + 156:Src/File_Handling.c **** if (fresult != FR_OK) + 567 .loc 1 156 17 is_stmt 0 view .LVU140 + 568 002a 2846 mov r0, r5 + 569 002c FFF7FEFF bl strlen + 570 .LVL50: + 571 0030 0246 mov r2, r0 + 156:Src/File_Handling.c **** if (fresult != FR_OK) + 572 .loc 1 156 17 discriminator 1 view .LVU141 + 573 0032 094E ldr r6, .L37+8 + 574 0034 094B ldr r3, .L37+12 + 575 0036 2946 mov r1, r5 + 576 0038 3046 mov r0, r6 + 577 003a FFF7FEFF bl f_write + 578 .LVL51: + 156:Src/File_Handling.c **** if (fresult != FR_OK) + 579 .loc 1 156 15 discriminator 2 view .LVU142 + 580 003e 054C ldr r4, .L37+4 + 581 .LVL52: + 156:Src/File_Handling.c **** if (fresult != FR_OK) + 582 .loc 1 156 15 discriminator 2 view .LVU143 + 583 0040 2070 strb r0, [r4] + 157:Src/File_Handling.c **** { + 584 .loc 1 157 7 is_stmt 1 view .LVU144 + 159:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d while writing to the FILE *%s*\n\n", fresult, name); + 585 .loc 1 159 8 view .LVU145 + 162:Src/File_Handling.c **** } + 586 .loc 1 162 8 view .LVU146 + 166:Src/File_Handling.c **** if (fresult != FR_OK) + 587 .loc 1 166 7 view .LVU147 + 166:Src/File_Handling.c **** if (fresult != FR_OK) + 588 .loc 1 166 17 is_stmt 0 view .LVU148 + 589 0042 3046 mov r0, r6 + 590 0044 FFF7FEFF bl f_close + 591 .LVL53: + 166:Src/File_Handling.c **** if (fresult != FR_OK) + 592 .loc 1 166 15 discriminator 1 view .LVU149 + 593 0048 2070 strb r0, [r4] + 167:Src/File_Handling.c **** { + 594 .loc 1 167 7 is_stmt 1 view .LVU150 + 176:Src/File_Handling.c **** //sprintf (buf, "File *%s* is WRITTEN and CLOSED successfully\n", name); + 595 .loc 1 176 8 view .LVU151 + 179:Src/File_Handling.c **** } + 596 .loc 1 179 8 view .LVU152 + 182:Src/File_Handling.c **** } + 597 .loc 1 182 6 view .LVU153 + 182:Src/File_Handling.c **** } + 598 .loc 1 182 13 is_stmt 0 view .LVU154 + 599 004a C0B2 uxtb r0, r0 + ARM GAS /tmp/cccCjqCZ.s page 16 + + + 600 004c E2E7 b .L34 + 601 .L38: + 602 004e 00BF .align 2 + 603 .L37: + 604 0050 00000000 .word fno + 605 0054 00000000 .word fresult + 606 0058 00000000 .word fil + 607 005c 00000000 .word bw + 608 .cfi_endproc + 609 .LFE1191: + 611 .section .text.Write_File_byte,"ax",%progbits + 612 .align 1 + 613 .global Write_File_byte + 614 .syntax unified + 615 .thumb + 616 .thumb_func + 618 Write_File_byte: + 619 .LVL54: + 620 .LFB1192: + 185:Src/File_Handling.c **** + 186:Src/File_Handling.c **** FRESULT Write_File_byte (char *name, uint8_t *data, unsigned int bytesize) + 187:Src/File_Handling.c **** { + 621 .loc 1 187 1 is_stmt 1 view -0 + 622 .cfi_startproc + 623 @ args = 0, pretend = 0, frame = 0 + 624 @ frame_needed = 0, uses_anonymous_args = 0 + 625 .loc 1 187 1 is_stmt 0 view .LVU156 + 626 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 627 .LCFI9: + 628 .cfi_def_cfa_offset 24 + 629 .cfi_offset 3, -24 + 630 .cfi_offset 4, -20 + 631 .cfi_offset 5, -16 + 632 .cfi_offset 6, -12 + 633 .cfi_offset 7, -8 + 634 .cfi_offset 14, -4 + 635 0002 0446 mov r4, r0 + 636 0004 0D46 mov r5, r1 + 637 0006 1646 mov r6, r2 + 188:Src/File_Handling.c **** + 189:Src/File_Handling.c **** /**** check whether the file exists or not ****/ + 190:Src/File_Handling.c **** fresult = f_stat (name, &fno); + 638 .loc 1 190 2 is_stmt 1 view .LVU157 + 639 .loc 1 190 12 is_stmt 0 view .LVU158 + 640 0008 1049 ldr r1, .L44 + 641 .LVL55: + 642 .loc 1 190 12 view .LVU159 + 643 000a FFF7FEFF bl f_stat + 644 .LVL56: + 645 .loc 1 190 10 discriminator 1 view .LVU160 + 646 000e 104B ldr r3, .L44+4 + 647 0010 1870 strb r0, [r3] + 191:Src/File_Handling.c **** if (fresult != FR_OK) + 648 .loc 1 191 2 is_stmt 1 view .LVU161 + 649 .loc 1 191 5 is_stmt 0 view .LVU162 + 650 0012 08B1 cbz r0, .L40 + 651 .LBB6: + ARM GAS /tmp/cccCjqCZ.s page 17 + + + 192:Src/File_Handling.c **** { + 193:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 652 .loc 1 193 3 is_stmt 1 view .LVU163 + 194:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! *%s* does not exists\n\n", name); + 195:Src/File_Handling.c **** //Send_Uart (buf); + 196:Src/File_Handling.c **** free(buf); + 653 .loc 1 196 6 view .LVU164 + 197:Src/File_Handling.c **** return fresult; + 654 .loc 1 197 6 view .LVU165 + 655 .loc 1 197 13 is_stmt 0 view .LVU166 + 656 0014 C0B2 uxtb r0, r0 + 657 .LVL57: + 658 .L41: + 659 .loc 1 197 13 view .LVU167 + 660 .LBE6: + 198:Src/File_Handling.c **** } + 199:Src/File_Handling.c **** + 200:Src/File_Handling.c **** else + 201:Src/File_Handling.c **** { + 202:Src/File_Handling.c **** /* Create a file with read write access and open it */ + 203:Src/File_Handling.c **** fresult = f_open(&fil, name, FA_OPEN_EXISTING | FA_WRITE); + 204:Src/File_Handling.c **** if (fresult != FR_OK) + 205:Src/File_Handling.c **** { + 206:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 207:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name); + 208:Src/File_Handling.c **** //Send_Uart(buf); + 209:Src/File_Handling.c **** free(buf); + 210:Src/File_Handling.c **** return fresult; + 211:Src/File_Handling.c **** } + 212:Src/File_Handling.c **** + 213:Src/File_Handling.c **** else + 214:Src/File_Handling.c **** { + 215:Src/File_Handling.c **** fresult = f_write(&fil, data, bytesize, &bw); + 216:Src/File_Handling.c **** if (fresult != FR_OK) + 217:Src/File_Handling.c **** { + 218:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 219:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d while writing to the FILE *%s*\n\n", fresult, name); + 220:Src/File_Handling.c **** //Send_Uart(buf); + 221:Src/File_Handling.c **** free(buf); + 222:Src/File_Handling.c **** } + 223:Src/File_Handling.c **** + 224:Src/File_Handling.c **** /* Close file */ + 225:Src/File_Handling.c **** fresult = f_close(&fil); + 226:Src/File_Handling.c **** if (fresult != FR_OK) + 227:Src/File_Handling.c **** { + 228:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 229:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in closing file *%s* after writing it\n\n", fresult, name); + 230:Src/File_Handling.c **** //Send_Uart(buf); + 231:Src/File_Handling.c **** free(buf); + 232:Src/File_Handling.c **** } + 233:Src/File_Handling.c **** else + 234:Src/File_Handling.c **** { + 235:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 236:Src/File_Handling.c **** //sprintf (buf, "File *%s* is WRITTEN and CLOSED successfully\n", name); + 237:Src/File_Handling.c **** //Send_Uart(buf); + 238:Src/File_Handling.c **** free(buf); + 239:Src/File_Handling.c **** } + ARM GAS /tmp/cccCjqCZ.s page 18 + + + 240:Src/File_Handling.c **** } + 241:Src/File_Handling.c **** return fresult; + 242:Src/File_Handling.c **** } + 243:Src/File_Handling.c **** } + 661 .loc 1 243 1 view .LVU168 + 662 0016 F8BD pop {r3, r4, r5, r6, r7, pc} + 663 .LVL58: + 664 .L40: + 203:Src/File_Handling.c **** if (fresult != FR_OK) + 665 .loc 1 203 6 is_stmt 1 view .LVU169 + 203:Src/File_Handling.c **** if (fresult != FR_OK) + 666 .loc 1 203 16 is_stmt 0 view .LVU170 + 667 0018 0222 movs r2, #2 + 668 001a 2146 mov r1, r4 + 669 001c 0D48 ldr r0, .L44+8 + 670 001e FFF7FEFF bl f_open + 671 .LVL59: + 203:Src/File_Handling.c **** if (fresult != FR_OK) + 672 .loc 1 203 14 discriminator 1 view .LVU171 + 673 0022 0B4B ldr r3, .L44+4 + 674 0024 1870 strb r0, [r3] + 204:Src/File_Handling.c **** { + 675 .loc 1 204 6 is_stmt 1 view .LVU172 + 204:Src/File_Handling.c **** { + 676 .loc 1 204 9 is_stmt 0 view .LVU173 + 677 0026 08B1 cbz r0, .L42 + 678 .LBB7: + 206:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name); + 679 .loc 1 206 7 is_stmt 1 view .LVU174 + 209:Src/File_Handling.c **** return fresult; + 680 .loc 1 209 10 view .LVU175 + 210:Src/File_Handling.c **** } + 681 .loc 1 210 10 view .LVU176 + 210:Src/File_Handling.c **** } + 682 .loc 1 210 17 is_stmt 0 view .LVU177 + 683 0028 C0B2 uxtb r0, r0 + 684 002a F4E7 b .L41 + 685 .L42: + 686 .LBE7: + 215:Src/File_Handling.c **** if (fresult != FR_OK) + 687 .loc 1 215 7 is_stmt 1 view .LVU178 + 215:Src/File_Handling.c **** if (fresult != FR_OK) + 688 .loc 1 215 17 is_stmt 0 view .LVU179 + 689 002c 094F ldr r7, .L44+8 + 690 002e 0A4B ldr r3, .L44+12 + 691 0030 3246 mov r2, r6 + 692 0032 2946 mov r1, r5 + 693 0034 3846 mov r0, r7 + 694 0036 FFF7FEFF bl f_write + 695 .LVL60: + 215:Src/File_Handling.c **** if (fresult != FR_OK) + 696 .loc 1 215 15 discriminator 1 view .LVU180 + 697 003a 054C ldr r4, .L44+4 + 698 .LVL61: + 215:Src/File_Handling.c **** if (fresult != FR_OK) + 699 .loc 1 215 15 discriminator 1 view .LVU181 + 700 003c 2070 strb r0, [r4] + ARM GAS /tmp/cccCjqCZ.s page 19 + + + 216:Src/File_Handling.c **** { + 701 .loc 1 216 7 is_stmt 1 view .LVU182 + 218:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d while writing to the FILE *%s*\n\n", fresult, name); + 702 .loc 1 218 8 view .LVU183 + 221:Src/File_Handling.c **** } + 703 .loc 1 221 8 view .LVU184 + 225:Src/File_Handling.c **** if (fresult != FR_OK) + 704 .loc 1 225 7 view .LVU185 + 225:Src/File_Handling.c **** if (fresult != FR_OK) + 705 .loc 1 225 17 is_stmt 0 view .LVU186 + 706 003e 3846 mov r0, r7 + 707 0040 FFF7FEFF bl f_close + 708 .LVL62: + 225:Src/File_Handling.c **** if (fresult != FR_OK) + 709 .loc 1 225 15 discriminator 1 view .LVU187 + 710 0044 2070 strb r0, [r4] + 226:Src/File_Handling.c **** { + 711 .loc 1 226 7 is_stmt 1 view .LVU188 + 235:Src/File_Handling.c **** //sprintf (buf, "File *%s* is WRITTEN and CLOSED successfully\n", name); + 712 .loc 1 235 8 view .LVU189 + 238:Src/File_Handling.c **** } + 713 .loc 1 238 8 view .LVU190 + 241:Src/File_Handling.c **** } + 714 .loc 1 241 6 view .LVU191 + 241:Src/File_Handling.c **** } + 715 .loc 1 241 13 is_stmt 0 view .LVU192 + 716 0046 C0B2 uxtb r0, r0 + 717 0048 E5E7 b .L41 + 718 .L45: + 719 004a 00BF .align 2 + 720 .L44: + 721 004c 00000000 .word fno + 722 0050 00000000 .word fresult + 723 0054 00000000 .word fil + 724 0058 00000000 .word bw + 725 .cfi_endproc + 726 .LFE1192: + 728 .section .rodata.Read_File.str1.4,"aMS",%progbits,1 + 729 .align 2 + 730 .LC5: + 731 0000 45525252 .ascii "ERRROR!!! *%s* does not exists\012\012\000" + 731 4F522121 + 731 21202A25 + 731 732A2064 + 731 6F657320 + 732 0021 000000 .align 2 + 733 .LC6: + 734 0024 4552524F .ascii "ERROR!!! No. %d in opening file *%s*\012\012\000" + 734 52212121 + 734 204E6F2E + 734 20256420 + 734 696E206F + 735 004b 00 .align 2 + 736 .LC7: + 737 004c 4552524F .ascii "ERROR!!! No. %d in reading file *%s*\012\012\000" + 737 52212121 + 737 204E6F2E + ARM GAS /tmp/cccCjqCZ.s page 20 + + + 737 20256420 + 737 696E2072 + 738 0073 00 .align 2 + 739 .LC8: + 740 0074 4552524F .ascii "ERROR!!! No. %d in closing file *%s*\012\012\000" + 740 52212121 + 740 204E6F2E + 740 20256420 + 740 696E2063 + 741 009b 00 .align 2 + 742 .LC9: + 743 009c 46696C65 .ascii "File *%s* CLOSED successfully\012\000" + 743 202A2573 + 743 2A20434C + 743 4F534544 + 743 20737563 + 744 .section .text.Read_File,"ax",%progbits + 745 .align 1 + 746 .global Read_File + 747 .syntax unified + 748 .thumb + 749 .thumb_func + 751 Read_File: + 752 .LVL63: + 753 .LFB1193: + 244:Src/File_Handling.c **** + 245:Src/File_Handling.c **** FRESULT Read_File (char *name) + 246:Src/File_Handling.c **** { + 754 .loc 1 246 1 is_stmt 1 view -0 + 755 .cfi_startproc + 756 @ args = 0, pretend = 0, frame = 0 + 757 @ frame_needed = 0, uses_anonymous_args = 0 + 758 .loc 1 246 1 is_stmt 0 view .LVU194 + 759 0000 70B5 push {r4, r5, r6, lr} + 760 .LCFI10: + 761 .cfi_def_cfa_offset 16 + 762 .cfi_offset 4, -16 + 763 .cfi_offset 5, -12 + 764 .cfi_offset 6, -8 + 765 .cfi_offset 14, -4 + 766 0002 0446 mov r4, r0 + 247:Src/File_Handling.c **** /**** check whether the file exists or not ****/ + 248:Src/File_Handling.c **** fresult = f_stat (name, &fno); + 767 .loc 1 248 2 is_stmt 1 view .LVU195 + 768 .loc 1 248 12 is_stmt 0 view .LVU196 + 769 0004 3749 ldr r1, .L55 + 770 0006 FFF7FEFF bl f_stat + 771 .LVL64: + 772 .loc 1 248 10 discriminator 1 view .LVU197 + 773 000a 374B ldr r3, .L55+4 + 774 000c 1870 strb r0, [r3] + 249:Src/File_Handling.c **** if (fresult != FR_OK) + 775 .loc 1 249 2 is_stmt 1 view .LVU198 + 776 .loc 1 249 5 is_stmt 0 view .LVU199 + 777 000e B8B9 cbnz r0, .L54 + 778 .LBB8: + 250:Src/File_Handling.c **** { + ARM GAS /tmp/cccCjqCZ.s page 21 + + + 251:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 252:Src/File_Handling.c **** sprintf (buf, "ERRROR!!! *%s* does not exists\n\n", name); + 253:Src/File_Handling.c **** Send_Uart (buf); + 254:Src/File_Handling.c **** free(buf); + 255:Src/File_Handling.c **** return fresult; + 256:Src/File_Handling.c **** } + 257:Src/File_Handling.c **** + 258:Src/File_Handling.c **** else + 259:Src/File_Handling.c **** { + 260:Src/File_Handling.c **** /* Open file to read */ + 261:Src/File_Handling.c **** fresult = f_open(&fil, name, FA_READ); + 779 .loc 1 261 3 is_stmt 1 view .LVU200 + 780 .loc 1 261 13 is_stmt 0 view .LVU201 + 781 0010 0122 movs r2, #1 + 782 0012 2146 mov r1, r4 + 783 0014 3548 ldr r0, .L55+8 + 784 0016 FFF7FEFF bl f_open + 785 .LVL65: + 786 001a 0546 mov r5, r0 + 787 .loc 1 261 11 discriminator 1 view .LVU202 + 788 001c 324B ldr r3, .L55+4 + 789 001e 1870 strb r0, [r3] + 262:Src/File_Handling.c **** + 263:Src/File_Handling.c **** if (fresult != FR_OK) + 790 .loc 1 263 3 is_stmt 1 view .LVU203 + 791 .loc 1 263 6 is_stmt 0 view .LVU204 + 792 0020 E0B1 cbz r0, .L49 + 793 .LBB9: + 264:Src/File_Handling.c **** { + 265:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 794 .loc 1 265 4 is_stmt 1 view .LVU205 + 795 .loc 1 265 16 is_stmt 0 view .LVU206 + 796 0022 6420 movs r0, #100 + 797 0024 FFF7FEFF bl malloc + 798 .LVL66: + 799 0028 0646 mov r6, r0 + 800 .LVL67: + 266:Src/File_Handling.c **** sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name); + 801 .loc 1 266 4 is_stmt 1 view .LVU207 + 802 002a 2346 mov r3, r4 + 803 002c 2A46 mov r2, r5 + 804 002e 3049 ldr r1, .L55+12 + 805 0030 FFF7FEFF bl sprintf + 806 .LVL68: + 267:Src/File_Handling.c **** Send_Uart(buf); + 807 .loc 1 267 7 view .LVU208 + 268:Src/File_Handling.c **** free(buf); + 808 .loc 1 268 7 view .LVU209 + 809 0034 3046 mov r0, r6 + 810 0036 FFF7FEFF bl free + 811 .LVL69: + 269:Src/File_Handling.c **** return fresult; + 812 .loc 1 269 7 view .LVU210 + 813 .loc 1 269 14 is_stmt 0 view .LVU211 + 814 003a 2B4B ldr r3, .L55+4 + 815 003c 1878 ldrb r0, [r3] @ zero_extendqisi2 + 816 003e 0CE0 b .L48 + ARM GAS /tmp/cccCjqCZ.s page 22 + + + 817 .LVL70: + 818 .L54: + 819 .loc 1 269 14 view .LVU212 + 820 .LBE9: + 821 .LBE8: + 822 .LBB13: + 251:Src/File_Handling.c **** sprintf (buf, "ERRROR!!! *%s* does not exists\n\n", name); + 823 .loc 1 251 3 is_stmt 1 view .LVU213 + 251:Src/File_Handling.c **** sprintf (buf, "ERRROR!!! *%s* does not exists\n\n", name); + 824 .loc 1 251 15 is_stmt 0 view .LVU214 + 825 0040 6420 movs r0, #100 + 826 0042 FFF7FEFF bl malloc + 827 .LVL71: + 828 0046 0546 mov r5, r0 + 829 .LVL72: + 252:Src/File_Handling.c **** Send_Uart (buf); + 830 .loc 1 252 3 is_stmt 1 view .LVU215 + 831 0048 2246 mov r2, r4 + 832 004a 2A49 ldr r1, .L55+16 + 833 004c FFF7FEFF bl sprintf + 834 .LVL73: + 253:Src/File_Handling.c **** free(buf); + 835 .loc 1 253 3 view .LVU216 + 254:Src/File_Handling.c **** return fresult; + 836 .loc 1 254 3 view .LVU217 + 837 0050 2846 mov r0, r5 + 838 0052 FFF7FEFF bl free + 839 .LVL74: + 255:Src/File_Handling.c **** } + 840 .loc 1 255 6 view .LVU218 + 255:Src/File_Handling.c **** } + 841 .loc 1 255 13 is_stmt 0 view .LVU219 + 842 0056 244B ldr r3, .L55+4 + 843 0058 1878 ldrb r0, [r3] @ zero_extendqisi2 + 844 .LVL75: + 845 .L48: + 255:Src/File_Handling.c **** } + 846 .loc 1 255 13 view .LVU220 + 847 .LBE13: + 270:Src/File_Handling.c **** } + 271:Src/File_Handling.c **** + 272:Src/File_Handling.c **** /* Read data from the file + 273:Src/File_Handling.c **** * see the function details for the arguments */ + 274:Src/File_Handling.c **** + 275:Src/File_Handling.c **** char *buffer = malloc(sizeof(f_size(&fil))); + 276:Src/File_Handling.c **** fresult = f_read (&fil, buffer, f_size(&fil), &br); + 277:Src/File_Handling.c **** if (fresult != FR_OK) + 278:Src/File_Handling.c **** { + 279:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 280:Src/File_Handling.c **** free(buffer); + 281:Src/File_Handling.c **** sprintf (buf, "ERROR!!! No. %d in reading file *%s*\n\n", fresult, name); + 282:Src/File_Handling.c **** Send_Uart(buffer); + 283:Src/File_Handling.c **** free(buf); + 284:Src/File_Handling.c **** } + 285:Src/File_Handling.c **** + 286:Src/File_Handling.c **** else + 287:Src/File_Handling.c **** { + ARM GAS /tmp/cccCjqCZ.s page 23 + + + 288:Src/File_Handling.c **** Send_Uart(buffer); + 289:Src/File_Handling.c **** free(buffer); + 290:Src/File_Handling.c **** + 291:Src/File_Handling.c **** /* Close file */ + 292:Src/File_Handling.c **** fresult = f_close(&fil); + 293:Src/File_Handling.c **** if (fresult != FR_OK) + 294:Src/File_Handling.c **** { + 295:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 296:Src/File_Handling.c **** sprintf (buf, "ERROR!!! No. %d in closing file *%s*\n\n", fresult, name); + 297:Src/File_Handling.c **** Send_Uart(buf); + 298:Src/File_Handling.c **** free(buf); + 299:Src/File_Handling.c **** } + 300:Src/File_Handling.c **** else + 301:Src/File_Handling.c **** { + 302:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 303:Src/File_Handling.c **** sprintf (buf, "File *%s* CLOSED successfully\n", name); + 304:Src/File_Handling.c **** Send_Uart(buf); + 305:Src/File_Handling.c **** free(buf); + 306:Src/File_Handling.c **** } + 307:Src/File_Handling.c **** } + 308:Src/File_Handling.c **** return fresult; + 309:Src/File_Handling.c **** } + 310:Src/File_Handling.c **** } + 848 .loc 1 310 1 view .LVU221 + 849 005a 70BD pop {r4, r5, r6, pc} + 850 .LVL76: + 851 .L49: + 852 .LBB14: + 275:Src/File_Handling.c **** fresult = f_read (&fil, buffer, f_size(&fil), &br); + 853 .loc 1 275 3 is_stmt 1 view .LVU222 + 275:Src/File_Handling.c **** fresult = f_read (&fil, buffer, f_size(&fil), &br); + 854 .loc 1 275 18 is_stmt 0 view .LVU223 + 855 005c 0420 movs r0, #4 + 856 005e FFF7FEFF bl malloc + 857 .LVL77: + 858 0062 0546 mov r5, r0 + 859 .LVL78: + 276:Src/File_Handling.c **** if (fresult != FR_OK) + 860 .loc 1 276 3 is_stmt 1 view .LVU224 + 276:Src/File_Handling.c **** if (fresult != FR_OK) + 861 .loc 1 276 35 is_stmt 0 view .LVU225 + 862 0064 2148 ldr r0, .L55+8 + 863 .LVL79: + 276:Src/File_Handling.c **** if (fresult != FR_OK) + 864 .loc 1 276 13 view .LVU226 + 865 0066 244B ldr r3, .L55+20 + 866 0068 C268 ldr r2, [r0, #12] + 867 006a 2946 mov r1, r5 + 868 006c FFF7FEFF bl f_read + 869 .LVL80: + 276:Src/File_Handling.c **** if (fresult != FR_OK) + 870 .loc 1 276 11 discriminator 1 view .LVU227 + 871 0070 1D4B ldr r3, .L55+4 + 872 0072 1870 strb r0, [r3] + 277:Src/File_Handling.c **** { + 873 .loc 1 277 3 is_stmt 1 view .LVU228 + 277:Src/File_Handling.c **** { + ARM GAS /tmp/cccCjqCZ.s page 24 + + + 874 .loc 1 277 6 is_stmt 0 view .LVU229 + 875 0074 98B1 cbz r0, .L50 + 876 .LBB10: + 279:Src/File_Handling.c **** free(buffer); + 877 .loc 1 279 4 is_stmt 1 view .LVU230 + 279:Src/File_Handling.c **** free(buffer); + 878 .loc 1 279 16 is_stmt 0 view .LVU231 + 879 0076 6420 movs r0, #100 + 880 0078 FFF7FEFF bl malloc + 881 .LVL81: + 882 007c 0646 mov r6, r0 + 883 .LVL82: + 280:Src/File_Handling.c **** sprintf (buf, "ERROR!!! No. %d in reading file *%s*\n\n", fresult, name); + 884 .loc 1 280 4 is_stmt 1 view .LVU232 + 885 007e 2846 mov r0, r5 + 886 .LVL83: + 280:Src/File_Handling.c **** sprintf (buf, "ERROR!!! No. %d in reading file *%s*\n\n", fresult, name); + 887 .loc 1 280 4 is_stmt 0 view .LVU233 + 888 0080 FFF7FEFF bl free + 889 .LVL84: + 281:Src/File_Handling.c **** Send_Uart(buffer); + 890 .loc 1 281 5 is_stmt 1 view .LVU234 + 891 0084 2346 mov r3, r4 + 892 0086 184A ldr r2, .L55+4 + 893 0088 1278 ldrb r2, [r2] @ zero_extendqisi2 + 894 008a 1C49 ldr r1, .L55+24 + 895 008c 3046 mov r0, r6 + 896 008e FFF7FEFF bl sprintf + 897 .LVL85: + 282:Src/File_Handling.c **** free(buf); + 898 .loc 1 282 6 view .LVU235 + 283:Src/File_Handling.c **** } + 899 .loc 1 283 6 view .LVU236 + 900 0092 3046 mov r0, r6 + 901 0094 FFF7FEFF bl free + 902 .LVL86: + 903 .L51: + 283:Src/File_Handling.c **** } + 904 .loc 1 283 6 is_stmt 0 view .LVU237 + 905 .LBE10: + 308:Src/File_Handling.c **** } + 906 .loc 1 308 6 is_stmt 1 view .LVU238 + 308:Src/File_Handling.c **** } + 907 .loc 1 308 13 is_stmt 0 view .LVU239 + 908 0098 134B ldr r3, .L55+4 + 909 009a 1878 ldrb r0, [r3] @ zero_extendqisi2 + 910 009c DDE7 b .L48 + 911 .LVL87: + 912 .L50: + 288:Src/File_Handling.c **** free(buffer); + 913 .loc 1 288 4 is_stmt 1 view .LVU240 + 289:Src/File_Handling.c **** + 914 .loc 1 289 4 view .LVU241 + 915 009e 2846 mov r0, r5 + 916 00a0 FFF7FEFF bl free + 917 .LVL88: + 292:Src/File_Handling.c **** if (fresult != FR_OK) + ARM GAS /tmp/cccCjqCZ.s page 25 + + + 918 .loc 1 292 4 view .LVU242 + 292:Src/File_Handling.c **** if (fresult != FR_OK) + 919 .loc 1 292 14 is_stmt 0 view .LVU243 + 920 00a4 1148 ldr r0, .L55+8 + 921 00a6 FFF7FEFF bl f_close + 922 .LVL89: + 923 00aa 0546 mov r5, r0 + 924 .LVL90: + 292:Src/File_Handling.c **** if (fresult != FR_OK) + 925 .loc 1 292 12 discriminator 1 view .LVU244 + 926 00ac 0E4B ldr r3, .L55+4 + 927 00ae 1870 strb r0, [r3] + 293:Src/File_Handling.c **** { + 928 .loc 1 293 4 is_stmt 1 view .LVU245 + 293:Src/File_Handling.c **** { + 929 .loc 1 293 7 is_stmt 0 view .LVU246 + 930 00b0 60B1 cbz r0, .L52 + 931 .LBB11: + 295:Src/File_Handling.c **** sprintf (buf, "ERROR!!! No. %d in closing file *%s*\n\n", fresult, name); + 932 .loc 1 295 5 is_stmt 1 view .LVU247 + 295:Src/File_Handling.c **** sprintf (buf, "ERROR!!! No. %d in closing file *%s*\n\n", fresult, name); + 933 .loc 1 295 17 is_stmt 0 view .LVU248 + 934 00b2 6420 movs r0, #100 + 935 00b4 FFF7FEFF bl malloc + 936 .LVL91: + 937 00b8 0646 mov r6, r0 + 938 .LVL92: + 296:Src/File_Handling.c **** Send_Uart(buf); + 939 .loc 1 296 5 is_stmt 1 view .LVU249 + 940 00ba 2346 mov r3, r4 + 941 00bc 2A46 mov r2, r5 + 942 00be 1049 ldr r1, .L55+28 + 943 00c0 FFF7FEFF bl sprintf + 944 .LVL93: + 297:Src/File_Handling.c **** free(buf); + 945 .loc 1 297 5 view .LVU250 + 298:Src/File_Handling.c **** } + 946 .loc 1 298 5 view .LVU251 + 947 00c4 3046 mov r0, r6 + 948 00c6 FFF7FEFF bl free + 949 .LVL94: + 950 .LBE11: + 951 00ca E5E7 b .L51 + 952 .LVL95: + 953 .L52: + 954 .LBB12: + 302:Src/File_Handling.c **** sprintf (buf, "File *%s* CLOSED successfully\n", name); + 955 .loc 1 302 5 view .LVU252 + 302:Src/File_Handling.c **** sprintf (buf, "File *%s* CLOSED successfully\n", name); + 956 .loc 1 302 17 is_stmt 0 view .LVU253 + 957 00cc 6420 movs r0, #100 + 958 00ce FFF7FEFF bl malloc + 959 .LVL96: + 960 00d2 0546 mov r5, r0 + 961 .LVL97: + 303:Src/File_Handling.c **** Send_Uart(buf); + 962 .loc 1 303 5 is_stmt 1 view .LVU254 + ARM GAS /tmp/cccCjqCZ.s page 26 + + + 963 00d4 2246 mov r2, r4 + 964 00d6 0B49 ldr r1, .L55+32 + 965 00d8 FFF7FEFF bl sprintf + 966 .LVL98: + 304:Src/File_Handling.c **** free(buf); + 967 .loc 1 304 5 view .LVU255 + 305:Src/File_Handling.c **** } + 968 .loc 1 305 5 view .LVU256 + 969 00dc 2846 mov r0, r5 + 970 00de FFF7FEFF bl free + 971 .LVL99: + 972 00e2 D9E7 b .L51 + 973 .L56: + 974 .align 2 + 975 .L55: + 976 00e4 00000000 .word fno + 977 00e8 00000000 .word fresult + 978 00ec 00000000 .word fil + 979 00f0 24000000 .word .LC6 + 980 00f4 00000000 .word .LC5 + 981 00f8 00000000 .word br + 982 00fc 4C000000 .word .LC7 + 983 0100 74000000 .word .LC8 + 984 0104 9C000000 .word .LC9 + 985 .LBE12: + 986 .LBE14: + 987 .cfi_endproc + 988 .LFE1193: + 990 .section .rodata.Seek_Read_File.str1.4,"aMS",%progbits,1 + 991 .align 2 + 992 .LC10: + 993 0000 4552524F .ascii "ERROR!!! Can't seek the file: *%s*\012\012\000" + 993 52212121 + 993 2043616E + 993 27742073 + 993 65656B20 + 994 .section .text.Seek_Read_File,"ax",%progbits + 995 .align 1 + 996 .global Seek_Read_File + 997 .syntax unified + 998 .thumb + 999 .thumb_func + 1001 Seek_Read_File: + 1002 .LVL100: + 1003 .LFB1194: + 311:Src/File_Handling.c **** + 312:Src/File_Handling.c **** FRESULT Seek_Read_File (char *name, uint8_t *data, unsigned int bytesize, unsigned long goto_label) + 313:Src/File_Handling.c **** { + 1004 .loc 1 313 1 view -0 + 1005 .cfi_startproc + 1006 @ args = 0, pretend = 0, frame = 0 + 1007 @ frame_needed = 0, uses_anonymous_args = 0 + 1008 .loc 1 313 1 is_stmt 0 view .LVU258 + 1009 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 1010 .LCFI11: + 1011 .cfi_def_cfa_offset 24 + 1012 .cfi_offset 4, -24 + ARM GAS /tmp/cccCjqCZ.s page 27 + + + 1013 .cfi_offset 5, -20 + 1014 .cfi_offset 6, -16 + 1015 .cfi_offset 7, -12 + 1016 .cfi_offset 8, -8 + 1017 .cfi_offset 14, -4 + 1018 0004 0446 mov r4, r0 + 1019 0006 0F46 mov r7, r1 + 1020 0008 9046 mov r8, r2 + 1021 000a 1D46 mov r5, r3 + 314:Src/File_Handling.c **** /**** check whether the file exists or not ****/ + 315:Src/File_Handling.c **** fresult = f_stat (name, &fno); + 1022 .loc 1 315 2 is_stmt 1 view .LVU259 + 1023 .loc 1 315 12 is_stmt 0 view .LVU260 + 1024 000c 4349 ldr r1, .L70 + 1025 .LVL101: + 1026 .loc 1 315 12 view .LVU261 + 1027 000e FFF7FEFF bl f_stat + 1028 .LVL102: + 1029 .loc 1 315 10 discriminator 1 view .LVU262 + 1030 0012 434B ldr r3, .L70+4 + 1031 0014 1870 strb r0, [r3] + 316:Src/File_Handling.c **** if (fresult != FR_OK) + 1032 .loc 1 316 2 is_stmt 1 view .LVU263 + 1033 .loc 1 316 5 is_stmt 0 view .LVU264 + 1034 0016 E8B9 cbnz r0, .L67 + 317:Src/File_Handling.c **** { + 318:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 319:Src/File_Handling.c **** sprintf (buf, "ERRROR!!! *%s* does not exists\n\n", name); + 320:Src/File_Handling.c **** //Send_Uart (buf); + 321:Src/File_Handling.c **** free(buf); + 322:Src/File_Handling.c **** return fresult; + 323:Src/File_Handling.c **** } + 324:Src/File_Handling.c **** + 325:Src/File_Handling.c **** else + 326:Src/File_Handling.c **** { + 327:Src/File_Handling.c **** /* Open file to read */ + 328:Src/File_Handling.c **** fresult = f_open(&fil, name, FA_READ); + 1035 .loc 1 328 3 is_stmt 1 view .LVU265 + 1036 .loc 1 328 13 is_stmt 0 view .LVU266 + 1037 0018 0122 movs r2, #1 + 1038 001a 2146 mov r1, r4 + 1039 001c 4148 ldr r0, .L70+8 + 1040 001e FFF7FEFF bl f_open + 1041 .LVL103: + 1042 0022 0646 mov r6, r0 + 1043 .loc 1 328 11 discriminator 1 view .LVU267 + 1044 0024 3E4B ldr r3, .L70+4 + 1045 0026 1870 strb r0, [r3] + 329:Src/File_Handling.c **** + 330:Src/File_Handling.c **** if (fresult != FR_OK) + 1046 .loc 1 330 3 is_stmt 1 view .LVU268 + 1047 .loc 1 330 6 is_stmt 0 view .LVU269 + 1048 0028 18BB cbnz r0, .L68 + 331:Src/File_Handling.c **** { + 332:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 333:Src/File_Handling.c **** sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name); + 334:Src/File_Handling.c **** //Send_Uart(buf); + ARM GAS /tmp/cccCjqCZ.s page 28 + + + 335:Src/File_Handling.c **** free(buf); + 336:Src/File_Handling.c **** return fresult; + 337:Src/File_Handling.c **** } + 338:Src/File_Handling.c **** + 339:Src/File_Handling.c **** /* Read data from the file + 340:Src/File_Handling.c **** * see the function details for the arguments */ + 341:Src/File_Handling.c **** + 342:Src/File_Handling.c **** //char *buffer = malloc(sizeof(f_size(&fil))); + 343:Src/File_Handling.c **** fresult = f_lseek (&fil, goto_label); /* Move file pointer of the file object */ + 1049 .loc 1 343 3 is_stmt 1 view .LVU270 + 1050 .loc 1 343 14 is_stmt 0 view .LVU271 + 1051 002a 2946 mov r1, r5 + 1052 002c 3D48 ldr r0, .L70+8 + 1053 002e FFF7FEFF bl f_lseek + 1054 .LVL104: + 1055 .loc 1 343 11 discriminator 1 view .LVU272 + 1056 0032 3B4B ldr r3, .L70+4 + 1057 0034 1870 strb r0, [r3] + 344:Src/File_Handling.c **** if (fresult != FR_OK) + 1058 .loc 1 344 3 is_stmt 1 view .LVU273 + 1059 .loc 1 344 6 is_stmt 0 view .LVU274 + 1060 0036 58B3 cbz r0, .L61 + 1061 .LBB15: + 345:Src/File_Handling.c **** { + 346:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 1062 .loc 1 346 4 is_stmt 1 view .LVU275 + 1063 .loc 1 346 16 is_stmt 0 view .LVU276 + 1064 0038 6420 movs r0, #100 + 1065 003a FFF7FEFF bl malloc + 1066 .LVL105: + 1067 003e 0546 mov r5, r0 + 1068 .LVL106: + 347:Src/File_Handling.c **** //free(buffer); + 348:Src/File_Handling.c **** sprintf (buf, "ERROR!!! Can't seek the file: *%s*\n\n", name); + 1069 .loc 1 348 5 is_stmt 1 view .LVU277 + 1070 0040 2246 mov r2, r4 + 1071 0042 3949 ldr r1, .L70+12 + 1072 0044 FFF7FEFF bl sprintf + 1073 .LVL107: + 349:Src/File_Handling.c **** //Send_Uart(buffer); + 350:Src/File_Handling.c **** free(buf); + 1074 .loc 1 350 5 view .LVU278 + 1075 0048 2846 mov r0, r5 + 1076 004a FFF7FEFF bl free + 1077 .LVL108: + 351:Src/File_Handling.c **** return fresult; + 1078 .loc 1 351 4 view .LVU279 + 1079 .loc 1 351 11 is_stmt 0 view .LVU280 + 1080 004e 344B ldr r3, .L70+4 + 1081 0050 1878 ldrb r0, [r3] @ zero_extendqisi2 + 1082 0052 0CE0 b .L59 + 1083 .LVL109: + 1084 .L67: + 1085 .loc 1 351 11 view .LVU281 + 1086 .LBE15: + 1087 .LBB16: + 318:Src/File_Handling.c **** sprintf (buf, "ERRROR!!! *%s* does not exists\n\n", name); + ARM GAS /tmp/cccCjqCZ.s page 29 + + + 1088 .loc 1 318 3 is_stmt 1 view .LVU282 + 318:Src/File_Handling.c **** sprintf (buf, "ERRROR!!! *%s* does not exists\n\n", name); + 1089 .loc 1 318 15 is_stmt 0 view .LVU283 + 1090 0054 6420 movs r0, #100 + 1091 0056 FFF7FEFF bl malloc + 1092 .LVL110: + 1093 005a 0546 mov r5, r0 + 1094 .LVL111: + 319:Src/File_Handling.c **** //Send_Uart (buf); + 1095 .loc 1 319 3 is_stmt 1 view .LVU284 + 1096 005c 2246 mov r2, r4 + 1097 005e 3349 ldr r1, .L70+16 + 1098 0060 FFF7FEFF bl sprintf + 1099 .LVL112: + 321:Src/File_Handling.c **** return fresult; + 1100 .loc 1 321 3 view .LVU285 + 1101 0064 2846 mov r0, r5 + 1102 0066 FFF7FEFF bl free + 1103 .LVL113: + 322:Src/File_Handling.c **** } + 1104 .loc 1 322 6 view .LVU286 + 322:Src/File_Handling.c **** } + 1105 .loc 1 322 13 is_stmt 0 view .LVU287 + 1106 006a 2D4B ldr r3, .L70+4 + 1107 006c 1878 ldrb r0, [r3] @ zero_extendqisi2 + 1108 .LVL114: + 1109 .L59: + 322:Src/File_Handling.c **** } + 1110 .loc 1 322 13 view .LVU288 + 1111 .LBE16: + 352:Src/File_Handling.c **** } + 353:Src/File_Handling.c **** fresult = f_read (&fil, data, bytesize, &br); + 354:Src/File_Handling.c **** if (fresult != FR_OK) + 355:Src/File_Handling.c **** { + 356:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 357:Src/File_Handling.c **** //free(buffer); + 358:Src/File_Handling.c **** sprintf (buf, "ERROR!!! No. %d in reading file *%s*\n\n", fresult, name); + 359:Src/File_Handling.c **** //Send_Uart(buffer); + 360:Src/File_Handling.c **** free(buf); + 361:Src/File_Handling.c **** + 362:Src/File_Handling.c **** } + 363:Src/File_Handling.c **** + 364:Src/File_Handling.c **** else + 365:Src/File_Handling.c **** { + 366:Src/File_Handling.c **** //Send_Uart(buffer); + 367:Src/File_Handling.c **** //free(buffer); + 368:Src/File_Handling.c **** if (goto_label==0)//Set size of file in first 4 bytes + 369:Src/File_Handling.c **** { + 370:Src/File_Handling.c **** sizeoffile = f_size(&fil); + 371:Src/File_Handling.c **** data[0] = (uint8_t) (sizeoffile&0xff); + 372:Src/File_Handling.c **** data[1] = (uint8_t) ((sizeoffile>>8)&0xff); + 373:Src/File_Handling.c **** data[2] = (uint8_t) ((sizeoffile>>16)&0xff); + 374:Src/File_Handling.c **** data[3] = (uint8_t) ((sizeoffile>>24)&0xff); + 375:Src/File_Handling.c **** } + 376:Src/File_Handling.c **** + 377:Src/File_Handling.c **** /* Close file */ + 378:Src/File_Handling.c **** fresult = f_close(&fil); + ARM GAS /tmp/cccCjqCZ.s page 30 + + + 379:Src/File_Handling.c **** if (fresult != FR_OK) + 380:Src/File_Handling.c **** { + 381:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 382:Src/File_Handling.c **** sprintf (buf, "ERROR!!! No. %d in closing file *%s*\n\n", fresult, name); + 383:Src/File_Handling.c **** //Send_Uart(buf); + 384:Src/File_Handling.c **** free(buf); + 385:Src/File_Handling.c **** } + 386:Src/File_Handling.c **** else + 387:Src/File_Handling.c **** { + 388:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 389:Src/File_Handling.c **** sprintf (buf, "File *%s* CLOSED successfully\n", name); + 390:Src/File_Handling.c **** //Send_Uart(buf); + 391:Src/File_Handling.c **** free(buf); + 392:Src/File_Handling.c **** } + 393:Src/File_Handling.c **** } + 394:Src/File_Handling.c **** return fresult; + 395:Src/File_Handling.c **** } + 396:Src/File_Handling.c **** } + 1112 .loc 1 396 1 view .LVU289 + 1113 006e BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 1114 .LVL115: + 1115 .L68: + 1116 .LBB17: + 332:Src/File_Handling.c **** sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name); + 1117 .loc 1 332 4 is_stmt 1 view .LVU290 + 332:Src/File_Handling.c **** sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name); + 1118 .loc 1 332 16 is_stmt 0 view .LVU291 + 1119 0072 6420 movs r0, #100 + 1120 0074 FFF7FEFF bl malloc + 1121 .LVL116: + 1122 0078 0546 mov r5, r0 + 1123 .LVL117: + 333:Src/File_Handling.c **** //Send_Uart(buf); + 1124 .loc 1 333 4 is_stmt 1 view .LVU292 + 1125 007a 2346 mov r3, r4 + 1126 007c 3246 mov r2, r6 + 1127 007e 2C49 ldr r1, .L70+20 + 1128 0080 FFF7FEFF bl sprintf + 1129 .LVL118: + 335:Src/File_Handling.c **** return fresult; + 1130 .loc 1 335 7 view .LVU293 + 1131 0084 2846 mov r0, r5 + 1132 0086 FFF7FEFF bl free + 1133 .LVL119: + 336:Src/File_Handling.c **** } + 1134 .loc 1 336 7 view .LVU294 + 336:Src/File_Handling.c **** } + 1135 .loc 1 336 14 is_stmt 0 view .LVU295 + 1136 008a 254B ldr r3, .L70+4 + 1137 008c 1878 ldrb r0, [r3] @ zero_extendqisi2 + 1138 008e EEE7 b .L59 + 1139 .LVL120: + 1140 .L61: + 336:Src/File_Handling.c **** } + 1141 .loc 1 336 14 view .LVU296 + 1142 .LBE17: + 353:Src/File_Handling.c **** if (fresult != FR_OK) + ARM GAS /tmp/cccCjqCZ.s page 31 + + + 1143 .loc 1 353 3 is_stmt 1 view .LVU297 + 353:Src/File_Handling.c **** if (fresult != FR_OK) + 1144 .loc 1 353 13 is_stmt 0 view .LVU298 + 1145 0090 284B ldr r3, .L70+24 + 1146 0092 4246 mov r2, r8 + 1147 0094 3946 mov r1, r7 + 1148 0096 2348 ldr r0, .L70+8 + 1149 0098 FFF7FEFF bl f_read + 1150 .LVL121: + 1151 009c 0646 mov r6, r0 + 353:Src/File_Handling.c **** if (fresult != FR_OK) + 1152 .loc 1 353 11 discriminator 1 view .LVU299 + 1153 009e 204B ldr r3, .L70+4 + 1154 00a0 1870 strb r0, [r3] + 354:Src/File_Handling.c **** { + 1155 .loc 1 354 3 is_stmt 1 view .LVU300 + 354:Src/File_Handling.c **** { + 1156 .loc 1 354 6 is_stmt 0 view .LVU301 + 1157 00a2 08BB cbnz r0, .L69 + 368:Src/File_Handling.c **** { + 1158 .loc 1 368 4 is_stmt 1 view .LVU302 + 368:Src/File_Handling.c **** { + 1159 .loc 1 368 7 is_stmt 0 view .LVU303 + 1160 00a4 55B9 cbnz r5, .L64 + 370:Src/File_Handling.c **** data[0] = (uint8_t) (sizeoffile&0xff); + 1161 .loc 1 370 5 is_stmt 1 view .LVU304 + 370:Src/File_Handling.c **** data[0] = (uint8_t) (sizeoffile&0xff); + 1162 .loc 1 370 18 is_stmt 0 view .LVU305 + 1163 00a6 1F4B ldr r3, .L70+8 + 1164 00a8 DA68 ldr r2, [r3, #12] + 370:Src/File_Handling.c **** data[0] = (uint8_t) (sizeoffile&0xff); + 1165 .loc 1 370 16 view .LVU306 + 1166 00aa 234B ldr r3, .L70+28 + 1167 00ac 1A60 str r2, [r3] + 371:Src/File_Handling.c **** data[1] = (uint8_t) ((sizeoffile>>8)&0xff); + 1168 .loc 1 371 5 is_stmt 1 view .LVU307 + 371:Src/File_Handling.c **** data[1] = (uint8_t) ((sizeoffile>>8)&0xff); + 1169 .loc 1 371 13 is_stmt 0 view .LVU308 + 1170 00ae 3A70 strb r2, [r7] + 372:Src/File_Handling.c **** data[2] = (uint8_t) ((sizeoffile>>16)&0xff); + 1171 .loc 1 372 5 is_stmt 1 view .LVU309 + 372:Src/File_Handling.c **** data[2] = (uint8_t) ((sizeoffile>>16)&0xff); + 1172 .loc 1 372 15 is_stmt 0 view .LVU310 + 1173 00b0 5A78 ldrb r2, [r3, #1] @ zero_extendqisi2 + 372:Src/File_Handling.c **** data[2] = (uint8_t) ((sizeoffile>>16)&0xff); + 1174 .loc 1 372 13 view .LVU311 + 1175 00b2 7A70 strb r2, [r7, #1] + 373:Src/File_Handling.c **** data[3] = (uint8_t) ((sizeoffile>>24)&0xff); + 1176 .loc 1 373 5 is_stmt 1 view .LVU312 + 373:Src/File_Handling.c **** data[3] = (uint8_t) ((sizeoffile>>24)&0xff); + 1177 .loc 1 373 15 is_stmt 0 view .LVU313 + 1178 00b4 9A78 ldrb r2, [r3, #2] @ zero_extendqisi2 + 373:Src/File_Handling.c **** data[3] = (uint8_t) ((sizeoffile>>24)&0xff); + 1179 .loc 1 373 13 view .LVU314 + 1180 00b6 BA70 strb r2, [r7, #2] + 374:Src/File_Handling.c **** } + 1181 .loc 1 374 5 is_stmt 1 view .LVU315 + ARM GAS /tmp/cccCjqCZ.s page 32 + + + 374:Src/File_Handling.c **** } + 1182 .loc 1 374 15 is_stmt 0 view .LVU316 + 1183 00b8 DB78 ldrb r3, [r3, #3] @ zero_extendqisi2 + 374:Src/File_Handling.c **** } + 1184 .loc 1 374 13 view .LVU317 + 1185 00ba FB70 strb r3, [r7, #3] + 1186 .L64: + 378:Src/File_Handling.c **** if (fresult != FR_OK) + 1187 .loc 1 378 4 is_stmt 1 view .LVU318 + 378:Src/File_Handling.c **** if (fresult != FR_OK) + 1188 .loc 1 378 14 is_stmt 0 view .LVU319 + 1189 00bc 1948 ldr r0, .L70+8 + 1190 00be FFF7FEFF bl f_close + 1191 .LVL122: + 1192 00c2 0546 mov r5, r0 + 1193 .LVL123: + 378:Src/File_Handling.c **** if (fresult != FR_OK) + 1194 .loc 1 378 12 discriminator 1 view .LVU320 + 1195 00c4 164B ldr r3, .L70+4 + 1196 00c6 1870 strb r0, [r3] + 379:Src/File_Handling.c **** { + 1197 .loc 1 379 4 is_stmt 1 view .LVU321 + 379:Src/File_Handling.c **** { + 1198 .loc 1 379 7 is_stmt 0 view .LVU322 + 1199 00c8 D8B1 cbz r0, .L65 + 1200 .LBB18: + 381:Src/File_Handling.c **** sprintf (buf, "ERROR!!! No. %d in closing file *%s*\n\n", fresult, name); + 1201 .loc 1 381 5 is_stmt 1 view .LVU323 + 381:Src/File_Handling.c **** sprintf (buf, "ERROR!!! No. %d in closing file *%s*\n\n", fresult, name); + 1202 .loc 1 381 17 is_stmt 0 view .LVU324 + 1203 00ca 6420 movs r0, #100 + 1204 00cc FFF7FEFF bl malloc + 1205 .LVL124: + 1206 00d0 0646 mov r6, r0 + 1207 .LVL125: + 382:Src/File_Handling.c **** //Send_Uart(buf); + 1208 .loc 1 382 5 is_stmt 1 view .LVU325 + 1209 00d2 2346 mov r3, r4 + 1210 00d4 2A46 mov r2, r5 + 1211 00d6 1949 ldr r1, .L70+32 + 1212 00d8 FFF7FEFF bl sprintf + 1213 .LVL126: + 384:Src/File_Handling.c **** } + 1214 .loc 1 384 5 view .LVU326 + 1215 00dc 3046 mov r0, r6 + 1216 00de FFF7FEFF bl free + 1217 .LVL127: + 1218 .L63: + 384:Src/File_Handling.c **** } + 1219 .loc 1 384 5 is_stmt 0 view .LVU327 + 1220 .LBE18: + 394:Src/File_Handling.c **** } + 1221 .loc 1 394 6 is_stmt 1 view .LVU328 + 394:Src/File_Handling.c **** } + 1222 .loc 1 394 13 is_stmt 0 view .LVU329 + 1223 00e2 0F4B ldr r3, .L70+4 + 1224 00e4 1878 ldrb r0, [r3] @ zero_extendqisi2 + ARM GAS /tmp/cccCjqCZ.s page 33 + + + 1225 00e6 C2E7 b .L59 + 1226 .LVL128: + 1227 .L69: + 1228 .LBB19: + 356:Src/File_Handling.c **** //free(buffer); + 1229 .loc 1 356 4 is_stmt 1 view .LVU330 + 356:Src/File_Handling.c **** //free(buffer); + 1230 .loc 1 356 16 is_stmt 0 view .LVU331 + 1231 00e8 6420 movs r0, #100 + 1232 00ea FFF7FEFF bl malloc + 1233 .LVL129: + 1234 00ee 0546 mov r5, r0 + 1235 .LVL130: + 358:Src/File_Handling.c **** //Send_Uart(buffer); + 1236 .loc 1 358 5 is_stmt 1 view .LVU332 + 1237 00f0 2346 mov r3, r4 + 1238 00f2 3246 mov r2, r6 + 1239 00f4 1249 ldr r1, .L70+36 + 1240 00f6 FFF7FEFF bl sprintf + 1241 .LVL131: + 360:Src/File_Handling.c **** + 1242 .loc 1 360 5 view .LVU333 + 1243 00fa 2846 mov r0, r5 + 1244 00fc FFF7FEFF bl free + 1245 .LVL132: + 1246 .LBE19: + 1247 0100 EFE7 b .L63 + 1248 .LVL133: + 1249 .L65: + 1250 .LBB20: + 388:Src/File_Handling.c **** sprintf (buf, "File *%s* CLOSED successfully\n", name); + 1251 .loc 1 388 5 view .LVU334 + 388:Src/File_Handling.c **** sprintf (buf, "File *%s* CLOSED successfully\n", name); + 1252 .loc 1 388 17 is_stmt 0 view .LVU335 + 1253 0102 6420 movs r0, #100 + 1254 0104 FFF7FEFF bl malloc + 1255 .LVL134: + 1256 0108 0546 mov r5, r0 + 1257 .LVL135: + 389:Src/File_Handling.c **** //Send_Uart(buf); + 1258 .loc 1 389 5 is_stmt 1 view .LVU336 + 1259 010a 2246 mov r2, r4 + 1260 010c 0D49 ldr r1, .L70+40 + 1261 010e FFF7FEFF bl sprintf + 1262 .LVL136: + 391:Src/File_Handling.c **** } + 1263 .loc 1 391 5 view .LVU337 + 1264 0112 2846 mov r0, r5 + 1265 0114 FFF7FEFF bl free + 1266 .LVL137: + 1267 0118 E3E7 b .L63 + 1268 .L71: + 1269 011a 00BF .align 2 + 1270 .L70: + 1271 011c 00000000 .word fno + 1272 0120 00000000 .word fresult + 1273 0124 00000000 .word fil + ARM GAS /tmp/cccCjqCZ.s page 34 + + + 1274 0128 00000000 .word .LC10 + 1275 012c 00000000 .word .LC5 + 1276 0130 24000000 .word .LC6 + 1277 0134 00000000 .word br + 1278 0138 00000000 .word sizeoffile + 1279 013c 74000000 .word .LC8 + 1280 0140 4C000000 .word .LC7 + 1281 0144 9C000000 .word .LC9 + 1282 .LBE20: + 1283 .cfi_endproc + 1284 .LFE1194: + 1286 .section .text.Create_File,"ax",%progbits + 1287 .align 1 + 1288 .global Create_File + 1289 .syntax unified + 1290 .thumb + 1291 .thumb_func + 1293 Create_File: + 1294 .LVL138: + 1295 .LFB1195: + 397:Src/File_Handling.c **** + 398:Src/File_Handling.c **** FRESULT Create_File (char *name) + 399:Src/File_Handling.c **** { + 1296 .loc 1 399 1 view -0 + 1297 .cfi_startproc + 1298 @ args = 0, pretend = 0, frame = 0 + 1299 @ frame_needed = 0, uses_anonymous_args = 0 + 1300 .loc 1 399 1 is_stmt 0 view .LVU339 + 1301 0000 10B5 push {r4, lr} + 1302 .LCFI12: + 1303 .cfi_def_cfa_offset 8 + 1304 .cfi_offset 4, -8 + 1305 .cfi_offset 14, -4 + 1306 0002 0446 mov r4, r0 + 400:Src/File_Handling.c **** fresult = f_stat (name, &fno); + 1307 .loc 1 400 2 is_stmt 1 view .LVU340 + 1308 .loc 1 400 12 is_stmt 0 view .LVU341 + 1309 0004 0C49 ldr r1, .L77 + 1310 0006 FFF7FEFF bl f_stat + 1311 .LVL139: + 1312 .loc 1 400 10 discriminator 1 view .LVU342 + 1313 000a 0C4B ldr r3, .L77+4 + 1314 000c 1870 strb r0, [r3] + 401:Src/File_Handling.c **** if (fresult == FR_OK) + 1315 .loc 1 401 2 is_stmt 1 view .LVU343 + 1316 .loc 1 401 5 is_stmt 0 view .LVU344 + 1317 000e 08B9 cbnz r0, .L73 + 1318 .LBB21: + 402:Src/File_Handling.c **** { + 403:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 1319 .loc 1 403 3 is_stmt 1 view .LVU345 + 404:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! *%s* already exists!!!!\n use Update_File \n\n",name); + 405:Src/File_Handling.c **** //Send_Uart(buf); + 406:Src/File_Handling.c **** free(buf); + 1320 .loc 1 406 3 view .LVU346 + 407:Src/File_Handling.c **** return fresult; + 1321 .loc 1 407 6 view .LVU347 + ARM GAS /tmp/cccCjqCZ.s page 35 + + + 1322 .loc 1 407 13 is_stmt 0 view .LVU348 + 1323 0010 C0B2 uxtb r0, r0 + 1324 .L74: + 1325 .LBE21: + 408:Src/File_Handling.c **** } + 409:Src/File_Handling.c **** else + 410:Src/File_Handling.c **** { + 411:Src/File_Handling.c **** fresult = f_open(&fil, name, FA_CREATE_ALWAYS|FA_READ|FA_WRITE); + 412:Src/File_Handling.c **** if (fresult != FR_OK) + 413:Src/File_Handling.c **** { + 414:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 415:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in creating file *%s*\n\n", fresult, name); + 416:Src/File_Handling.c **** //Send_Uart(buf); + 417:Src/File_Handling.c **** free(buf); + 418:Src/File_Handling.c **** return fresult; + 419:Src/File_Handling.c **** } + 420:Src/File_Handling.c **** else + 421:Src/File_Handling.c **** { + 422:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 423:Src/File_Handling.c **** //sprintf (buf, "*%s* created successfully\n Now use Write_File to write data\n",name); + 424:Src/File_Handling.c **** //Send_Uart(buf); + 425:Src/File_Handling.c **** free(buf); + 426:Src/File_Handling.c **** } + 427:Src/File_Handling.c **** + 428:Src/File_Handling.c **** fresult = f_close(&fil); + 429:Src/File_Handling.c **** if (fresult != FR_OK) + 430:Src/File_Handling.c **** { + 431:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 432:Src/File_Handling.c **** //sprintf (buf, "ERROR No. %d in closing file *%s*\n\n", fresult, name); + 433:Src/File_Handling.c **** //Send_Uart(buf); + 434:Src/File_Handling.c **** free(buf); + 435:Src/File_Handling.c **** } + 436:Src/File_Handling.c **** else + 437:Src/File_Handling.c **** { + 438:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 439:Src/File_Handling.c **** //sprintf (buf, "File *%s* CLOSED successfully\n", name); + 440:Src/File_Handling.c **** //Send_Uart(buf); + 441:Src/File_Handling.c **** free(buf); + 442:Src/File_Handling.c **** } + 443:Src/File_Handling.c **** } + 444:Src/File_Handling.c **** return fresult; + 445:Src/File_Handling.c **** } + 1326 .loc 1 445 1 view .LVU349 + 1327 0012 10BD pop {r4, pc} + 1328 .LVL140: + 1329 .L73: + 411:Src/File_Handling.c **** if (fresult != FR_OK) + 1330 .loc 1 411 3 is_stmt 1 view .LVU350 + 411:Src/File_Handling.c **** if (fresult != FR_OK) + 1331 .loc 1 411 13 is_stmt 0 view .LVU351 + 1332 0014 0B22 movs r2, #11 + 1333 0016 2146 mov r1, r4 + 1334 0018 0948 ldr r0, .L77+8 + 1335 001a FFF7FEFF bl f_open + 1336 .LVL141: + 411:Src/File_Handling.c **** if (fresult != FR_OK) + 1337 .loc 1 411 11 discriminator 1 view .LVU352 + ARM GAS /tmp/cccCjqCZ.s page 36 + + + 1338 001e 074B ldr r3, .L77+4 + 1339 0020 1870 strb r0, [r3] + 412:Src/File_Handling.c **** { + 1340 .loc 1 412 3 is_stmt 1 view .LVU353 + 412:Src/File_Handling.c **** { + 1341 .loc 1 412 6 is_stmt 0 view .LVU354 + 1342 0022 08B1 cbz r0, .L75 + 1343 .LBB22: + 414:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in creating file *%s*\n\n", fresult, name); + 1344 .loc 1 414 4 is_stmt 1 view .LVU355 + 417:Src/File_Handling.c **** return fresult; + 1345 .loc 1 417 4 view .LVU356 + 418:Src/File_Handling.c **** } + 1346 .loc 1 418 7 view .LVU357 + 418:Src/File_Handling.c **** } + 1347 .loc 1 418 14 is_stmt 0 view .LVU358 + 1348 0024 C0B2 uxtb r0, r0 + 1349 0026 F4E7 b .L74 + 1350 .L75: + 1351 .LBE22: + 422:Src/File_Handling.c **** //sprintf (buf, "*%s* created successfully\n Now use Write_File to write data\n",name); + 1352 .loc 1 422 4 is_stmt 1 view .LVU359 + 425:Src/File_Handling.c **** } + 1353 .loc 1 425 4 view .LVU360 + 428:Src/File_Handling.c **** if (fresult != FR_OK) + 1354 .loc 1 428 3 view .LVU361 + 428:Src/File_Handling.c **** if (fresult != FR_OK) + 1355 .loc 1 428 13 is_stmt 0 view .LVU362 + 1356 0028 0548 ldr r0, .L77+8 + 1357 002a FFF7FEFF bl f_close + 1358 .LVL142: + 428:Src/File_Handling.c **** if (fresult != FR_OK) + 1359 .loc 1 428 11 discriminator 1 view .LVU363 + 1360 002e 034B ldr r3, .L77+4 + 1361 0030 1870 strb r0, [r3] + 429:Src/File_Handling.c **** { + 1362 .loc 1 429 3 is_stmt 1 view .LVU364 + 438:Src/File_Handling.c **** //sprintf (buf, "File *%s* CLOSED successfully\n", name); + 1363 .loc 1 438 4 view .LVU365 + 441:Src/File_Handling.c **** } + 1364 .loc 1 441 4 view .LVU366 + 444:Src/File_Handling.c **** } + 1365 .loc 1 444 5 view .LVU367 + 444:Src/File_Handling.c **** } + 1366 .loc 1 444 12 is_stmt 0 view .LVU368 + 1367 0032 C0B2 uxtb r0, r0 + 1368 0034 EDE7 b .L74 + 1369 .L78: + 1370 0036 00BF .align 2 + 1371 .L77: + 1372 0038 00000000 .word fno + 1373 003c 00000000 .word fresult + 1374 0040 00000000 .word fil + 1375 .cfi_endproc + 1376 .LFE1195: + 1378 .section .text.Update_File,"ax",%progbits + 1379 .align 1 + ARM GAS /tmp/cccCjqCZ.s page 37 + + + 1380 .global Update_File + 1381 .syntax unified + 1382 .thumb + 1383 .thumb_func + 1385 Update_File: + 1386 .LVL143: + 1387 .LFB1196: + 446:Src/File_Handling.c **** + 447:Src/File_Handling.c **** FRESULT Update_File (char *name, char *data) + 448:Src/File_Handling.c **** { + 1388 .loc 1 448 1 is_stmt 1 view -0 + 1389 .cfi_startproc + 1390 @ args = 0, pretend = 0, frame = 0 + 1391 @ frame_needed = 0, uses_anonymous_args = 0 + 1392 .loc 1 448 1 is_stmt 0 view .LVU370 + 1393 0000 70B5 push {r4, r5, r6, lr} + 1394 .LCFI13: + 1395 .cfi_def_cfa_offset 16 + 1396 .cfi_offset 4, -16 + 1397 .cfi_offset 5, -12 + 1398 .cfi_offset 6, -8 + 1399 .cfi_offset 14, -4 + 1400 0002 0446 mov r4, r0 + 1401 0004 0D46 mov r5, r1 + 449:Src/File_Handling.c **** /**** check whether the file exists or not ****/ + 450:Src/File_Handling.c **** fresult = f_stat (name, &fno); + 1402 .loc 1 450 2 is_stmt 1 view .LVU371 + 1403 .loc 1 450 12 is_stmt 0 view .LVU372 + 1404 0006 1249 ldr r1, .L84 + 1405 .LVL144: + 1406 .loc 1 450 12 view .LVU373 + 1407 0008 FFF7FEFF bl f_stat + 1408 .LVL145: + 1409 .loc 1 450 10 discriminator 1 view .LVU374 + 1410 000c 114B ldr r3, .L84+4 + 1411 000e 1870 strb r0, [r3] + 451:Src/File_Handling.c **** if (fresult != FR_OK) + 1412 .loc 1 451 2 is_stmt 1 view .LVU375 + 1413 .loc 1 451 5 is_stmt 0 view .LVU376 + 1414 0010 08B1 cbz r0, .L80 + 1415 .LBB23: + 452:Src/File_Handling.c **** { + 453:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 1416 .loc 1 453 3 is_stmt 1 view .LVU377 + 454:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! *%s* does not exists\n\n", name); + 455:Src/File_Handling.c **** //Send_Uart (buf); + 456:Src/File_Handling.c **** free(buf); + 1417 .loc 1 456 3 view .LVU378 + 457:Src/File_Handling.c **** return fresult; + 1418 .loc 1 457 6 view .LVU379 + 1419 .loc 1 457 13 is_stmt 0 view .LVU380 + 1420 0012 C0B2 uxtb r0, r0 + 1421 .LVL146: + 1422 .L81: + 1423 .loc 1 457 13 view .LVU381 + 1424 .LBE23: + 458:Src/File_Handling.c **** } + ARM GAS /tmp/cccCjqCZ.s page 38 + + + 459:Src/File_Handling.c **** + 460:Src/File_Handling.c **** else + 461:Src/File_Handling.c **** { + 462:Src/File_Handling.c **** /* Create a file with read write access and open it */ + 463:Src/File_Handling.c **** fresult = f_open(&fil, name, FA_OPEN_APPEND | FA_WRITE); + 464:Src/File_Handling.c **** if (fresult != FR_OK) + 465:Src/File_Handling.c **** { + 466:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 467:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name); + 468:Src/File_Handling.c **** //Send_Uart(buf); + 469:Src/File_Handling.c **** free(buf); + 470:Src/File_Handling.c **** return fresult; + 471:Src/File_Handling.c **** } + 472:Src/File_Handling.c **** + 473:Src/File_Handling.c **** /* Writing text */ + 474:Src/File_Handling.c **** fresult = f_write(&fil, data, strlen (data), &bw); + 475:Src/File_Handling.c **** if (fresult != FR_OK) + 476:Src/File_Handling.c **** { + 477:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 478:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in writing file *%s*\n\n", fresult, name); + 479:Src/File_Handling.c **** //Send_Uart(buf); + 480:Src/File_Handling.c **** free(buf); + 481:Src/File_Handling.c **** } + 482:Src/File_Handling.c **** + 483:Src/File_Handling.c **** else + 484:Src/File_Handling.c **** { + 485:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 486:Src/File_Handling.c **** //sprintf (buf, "*%s* UPDATED successfully\n", name); + 487:Src/File_Handling.c **** //Send_Uart(buf); + 488:Src/File_Handling.c **** free(buf); + 489:Src/File_Handling.c **** } + 490:Src/File_Handling.c **** + 491:Src/File_Handling.c **** /* Close file */ + 492:Src/File_Handling.c **** fresult = f_close(&fil); + 493:Src/File_Handling.c **** if (fresult != FR_OK) + 494:Src/File_Handling.c **** { + 495:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 496:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in closing file *%s*\n\n", fresult, name); + 497:Src/File_Handling.c **** //Send_Uart(buf); + 498:Src/File_Handling.c **** free(buf); + 499:Src/File_Handling.c **** } + 500:Src/File_Handling.c **** else + 501:Src/File_Handling.c **** { + 502:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 503:Src/File_Handling.c **** //sprintf (buf, "File *%s* CLOSED successfully\n", name); + 504:Src/File_Handling.c **** //Send_Uart(buf); + 505:Src/File_Handling.c **** free(buf); + 506:Src/File_Handling.c **** } + 507:Src/File_Handling.c **** } + 508:Src/File_Handling.c **** return fresult; + 509:Src/File_Handling.c **** } + 1425 .loc 1 509 1 view .LVU382 + 1426 0014 70BD pop {r4, r5, r6, pc} + 1427 .LVL147: + 1428 .L80: + 463:Src/File_Handling.c **** if (fresult != FR_OK) + 1429 .loc 1 463 6 is_stmt 1 view .LVU383 + ARM GAS /tmp/cccCjqCZ.s page 39 + + + 463:Src/File_Handling.c **** if (fresult != FR_OK) + 1430 .loc 1 463 16 is_stmt 0 view .LVU384 + 1431 0016 3222 movs r2, #50 + 1432 0018 2146 mov r1, r4 + 1433 001a 0F48 ldr r0, .L84+8 + 1434 001c FFF7FEFF bl f_open + 1435 .LVL148: + 463:Src/File_Handling.c **** if (fresult != FR_OK) + 1436 .loc 1 463 14 discriminator 1 view .LVU385 + 1437 0020 0C4B ldr r3, .L84+4 + 1438 0022 1870 strb r0, [r3] + 464:Src/File_Handling.c **** { + 1439 .loc 1 464 6 is_stmt 1 view .LVU386 + 464:Src/File_Handling.c **** { + 1440 .loc 1 464 9 is_stmt 0 view .LVU387 + 1441 0024 08B1 cbz r0, .L82 + 1442 .LBB24: + 466:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name); + 1443 .loc 1 466 7 is_stmt 1 view .LVU388 + 469:Src/File_Handling.c **** return fresult; + 1444 .loc 1 469 10 view .LVU389 + 470:Src/File_Handling.c **** } + 1445 .loc 1 470 10 view .LVU390 + 470:Src/File_Handling.c **** } + 1446 .loc 1 470 17 is_stmt 0 view .LVU391 + 1447 0026 C0B2 uxtb r0, r0 + 1448 0028 F4E7 b .L81 + 1449 .L82: + 1450 .LBE24: + 474:Src/File_Handling.c **** if (fresult != FR_OK) + 1451 .loc 1 474 6 is_stmt 1 view .LVU392 + 474:Src/File_Handling.c **** if (fresult != FR_OK) + 1452 .loc 1 474 16 is_stmt 0 view .LVU393 + 1453 002a 2846 mov r0, r5 + 1454 002c FFF7FEFF bl strlen + 1455 .LVL149: + 1456 0030 0246 mov r2, r0 + 474:Src/File_Handling.c **** if (fresult != FR_OK) + 1457 .loc 1 474 16 discriminator 1 view .LVU394 + 1458 0032 094E ldr r6, .L84+8 + 1459 0034 094B ldr r3, .L84+12 + 1460 0036 2946 mov r1, r5 + 1461 0038 3046 mov r0, r6 + 1462 003a FFF7FEFF bl f_write + 1463 .LVL150: + 474:Src/File_Handling.c **** if (fresult != FR_OK) + 1464 .loc 1 474 14 discriminator 2 view .LVU395 + 1465 003e 054C ldr r4, .L84+4 + 1466 .LVL151: + 474:Src/File_Handling.c **** if (fresult != FR_OK) + 1467 .loc 1 474 14 discriminator 2 view .LVU396 + 1468 0040 2070 strb r0, [r4] + 475:Src/File_Handling.c **** { + 1469 .loc 1 475 6 is_stmt 1 view .LVU397 + 485:Src/File_Handling.c **** //sprintf (buf, "*%s* UPDATED successfully\n", name); + 1470 .loc 1 485 7 view .LVU398 + 488:Src/File_Handling.c **** } + ARM GAS /tmp/cccCjqCZ.s page 40 + + + 1471 .loc 1 488 7 view .LVU399 + 492:Src/File_Handling.c **** if (fresult != FR_OK) + 1472 .loc 1 492 6 view .LVU400 + 492:Src/File_Handling.c **** if (fresult != FR_OK) + 1473 .loc 1 492 16 is_stmt 0 view .LVU401 + 1474 0042 3046 mov r0, r6 + 1475 0044 FFF7FEFF bl f_close + 1476 .LVL152: + 492:Src/File_Handling.c **** if (fresult != FR_OK) + 1477 .loc 1 492 14 discriminator 1 view .LVU402 + 1478 0048 2070 strb r0, [r4] + 493:Src/File_Handling.c **** { + 1479 .loc 1 493 6 is_stmt 1 view .LVU403 + 502:Src/File_Handling.c **** //sprintf (buf, "File *%s* CLOSED successfully\n", name); + 1480 .loc 1 502 7 view .LVU404 + 505:Src/File_Handling.c **** } + 1481 .loc 1 505 7 view .LVU405 + 508:Src/File_Handling.c **** } + 1482 .loc 1 508 5 view .LVU406 + 508:Src/File_Handling.c **** } + 1483 .loc 1 508 12 is_stmt 0 view .LVU407 + 1484 004a C0B2 uxtb r0, r0 + 1485 004c E2E7 b .L81 + 1486 .L85: + 1487 004e 00BF .align 2 + 1488 .L84: + 1489 0050 00000000 .word fno + 1490 0054 00000000 .word fresult + 1491 0058 00000000 .word fil + 1492 005c 00000000 .word bw + 1493 .cfi_endproc + 1494 .LFE1196: + 1496 .section .rodata.Remove_File.str1.4,"aMS",%progbits,1 + 1497 .align 2 + 1498 .LC11: + 1499 0000 4552524F .ascii "ERROR!!! *%s* does not exists\012\012\000" + 1499 52212121 + 1499 202A2573 + 1499 2A20646F + 1499 6573206E + 1500 .align 2 + 1501 .LC12: + 1502 0020 2A25732A .ascii "*%s* has been removed successfully\012\000" + 1502 20686173 + 1502 20626565 + 1502 6E207265 + 1502 6D6F7665 + 1503 .align 2 + 1504 .LC13: + 1505 0044 4552524F .ascii "ERROR No. %d in removing *%s*\012\012\000" + 1505 52204E6F + 1505 2E202564 + 1505 20696E20 + 1505 72656D6F + 1506 .section .text.Remove_File,"ax",%progbits + 1507 .align 1 + 1508 .global Remove_File + ARM GAS /tmp/cccCjqCZ.s page 41 + + + 1509 .syntax unified + 1510 .thumb + 1511 .thumb_func + 1513 Remove_File: + 1514 .LVL153: + 1515 .LFB1197: + 510:Src/File_Handling.c **** + 511:Src/File_Handling.c **** FRESULT Remove_File (char *name) + 512:Src/File_Handling.c **** { + 1516 .loc 1 512 1 is_stmt 1 view -0 + 1517 .cfi_startproc + 1518 @ args = 0, pretend = 0, frame = 0 + 1519 @ frame_needed = 0, uses_anonymous_args = 0 + 1520 .loc 1 512 1 is_stmt 0 view .LVU409 + 1521 0000 70B5 push {r4, r5, r6, lr} + 1522 .LCFI14: + 1523 .cfi_def_cfa_offset 16 + 1524 .cfi_offset 4, -16 + 1525 .cfi_offset 5, -12 + 1526 .cfi_offset 6, -8 + 1527 .cfi_offset 14, -4 + 1528 0002 0446 mov r4, r0 + 513:Src/File_Handling.c **** /**** check whether the file exists or not ****/ + 514:Src/File_Handling.c **** fresult = f_stat (name, &fno); + 1529 .loc 1 514 2 is_stmt 1 view .LVU410 + 1530 .loc 1 514 12 is_stmt 0 view .LVU411 + 1531 0004 1A49 ldr r1, .L93 + 1532 0006 FFF7FEFF bl f_stat + 1533 .LVL154: + 1534 .loc 1 514 10 discriminator 1 view .LVU412 + 1535 000a 1A4B ldr r3, .L93+4 + 1536 000c 1870 strb r0, [r3] + 515:Src/File_Handling.c **** if (fresult != FR_OK) + 1537 .loc 1 515 2 is_stmt 1 view .LVU413 + 1538 .loc 1 515 5 is_stmt 0 view .LVU414 + 1539 000e A0B9 cbnz r0, .L92 + 516:Src/File_Handling.c **** { + 517:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 518:Src/File_Handling.c **** sprintf (buf, "ERROR!!! *%s* does not exists\n\n", name); + 519:Src/File_Handling.c **** Send_Uart (buf); + 520:Src/File_Handling.c **** free(buf); + 521:Src/File_Handling.c **** return fresult; + 522:Src/File_Handling.c **** } + 523:Src/File_Handling.c **** + 524:Src/File_Handling.c **** else + 525:Src/File_Handling.c **** { + 526:Src/File_Handling.c **** fresult = f_unlink (name); + 1540 .loc 1 526 3 is_stmt 1 view .LVU415 + 1541 .loc 1 526 13 is_stmt 0 view .LVU416 + 1542 0010 2046 mov r0, r4 + 1543 0012 FFF7FEFF bl f_unlink + 1544 .LVL155: + 1545 0016 0546 mov r5, r0 + 1546 .loc 1 526 11 discriminator 1 view .LVU417 + 1547 0018 164B ldr r3, .L93+4 + 1548 001a 1870 strb r0, [r3] + 527:Src/File_Handling.c **** if (fresult == FR_OK) + ARM GAS /tmp/cccCjqCZ.s page 42 + + + 1549 .loc 1 527 3 is_stmt 1 view .LVU418 + 1550 .loc 1 527 6 is_stmt 0 view .LVU419 + 1551 001c D8B9 cbnz r0, .L89 + 1552 .LBB25: + 528:Src/File_Handling.c **** { + 529:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 1553 .loc 1 529 4 is_stmt 1 view .LVU420 + 1554 .loc 1 529 16 is_stmt 0 view .LVU421 + 1555 001e 6420 movs r0, #100 + 1556 0020 FFF7FEFF bl malloc + 1557 .LVL156: + 1558 0024 0546 mov r5, r0 + 1559 .LVL157: + 530:Src/File_Handling.c **** sprintf (buf, "*%s* has been removed successfully\n", name); + 1560 .loc 1 530 4 is_stmt 1 view .LVU422 + 1561 0026 2246 mov r2, r4 + 1562 0028 1349 ldr r1, .L93+8 + 1563 002a FFF7FEFF bl sprintf + 1564 .LVL158: + 531:Src/File_Handling.c **** Send_Uart (buf); + 1565 .loc 1 531 4 view .LVU423 + 532:Src/File_Handling.c **** free(buf); + 1566 .loc 1 532 4 view .LVU424 + 1567 002e 2846 mov r0, r5 + 1568 0030 FFF7FEFF bl free + 1569 .LVL159: + 1570 .L90: + 1571 .loc 1 532 4 is_stmt 0 view .LVU425 + 1572 .LBE25: + 533:Src/File_Handling.c **** } + 534:Src/File_Handling.c **** + 535:Src/File_Handling.c **** else + 536:Src/File_Handling.c **** { + 537:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 538:Src/File_Handling.c **** sprintf (buf, "ERROR No. %d in removing *%s*\n\n",fresult, name); + 539:Src/File_Handling.c **** Send_Uart (buf); + 540:Src/File_Handling.c **** free(buf); + 541:Src/File_Handling.c **** } + 542:Src/File_Handling.c **** } + 543:Src/File_Handling.c **** return fresult; + 1573 .loc 1 543 2 is_stmt 1 view .LVU426 + 1574 .loc 1 543 9 is_stmt 0 view .LVU427 + 1575 0034 0F4B ldr r3, .L93+4 + 1576 0036 1878 ldrb r0, [r3] @ zero_extendqisi2 + 1577 .L88: + 544:Src/File_Handling.c **** } + 1578 .loc 1 544 1 view .LVU428 + 1579 0038 70BD pop {r4, r5, r6, pc} + 1580 .LVL160: + 1581 .L92: + 1582 .LBB26: + 517:Src/File_Handling.c **** sprintf (buf, "ERROR!!! *%s* does not exists\n\n", name); + 1583 .loc 1 517 3 is_stmt 1 view .LVU429 + 517:Src/File_Handling.c **** sprintf (buf, "ERROR!!! *%s* does not exists\n\n", name); + 1584 .loc 1 517 15 is_stmt 0 view .LVU430 + 1585 003a 6420 movs r0, #100 + 1586 003c FFF7FEFF bl malloc + ARM GAS /tmp/cccCjqCZ.s page 43 + + + 1587 .LVL161: + 1588 0040 0546 mov r5, r0 + 1589 .LVL162: + 518:Src/File_Handling.c **** Send_Uart (buf); + 1590 .loc 1 518 3 is_stmt 1 view .LVU431 + 1591 0042 2246 mov r2, r4 + 1592 0044 0D49 ldr r1, .L93+12 + 1593 0046 FFF7FEFF bl sprintf + 1594 .LVL163: + 519:Src/File_Handling.c **** free(buf); + 1595 .loc 1 519 3 view .LVU432 + 520:Src/File_Handling.c **** return fresult; + 1596 .loc 1 520 3 view .LVU433 + 1597 004a 2846 mov r0, r5 + 1598 004c FFF7FEFF bl free + 1599 .LVL164: + 521:Src/File_Handling.c **** } + 1600 .loc 1 521 3 view .LVU434 + 521:Src/File_Handling.c **** } + 1601 .loc 1 521 10 is_stmt 0 view .LVU435 + 1602 0050 084B ldr r3, .L93+4 + 1603 0052 1878 ldrb r0, [r3] @ zero_extendqisi2 + 1604 0054 F0E7 b .L88 + 1605 .LVL165: + 1606 .L89: + 521:Src/File_Handling.c **** } + 1607 .loc 1 521 10 view .LVU436 + 1608 .LBE26: + 1609 .LBB27: + 537:Src/File_Handling.c **** sprintf (buf, "ERROR No. %d in removing *%s*\n\n",fresult, name); + 1610 .loc 1 537 4 is_stmt 1 view .LVU437 + 537:Src/File_Handling.c **** sprintf (buf, "ERROR No. %d in removing *%s*\n\n",fresult, name); + 1611 .loc 1 537 16 is_stmt 0 view .LVU438 + 1612 0056 6420 movs r0, #100 + 1613 0058 FFF7FEFF bl malloc + 1614 .LVL166: + 1615 005c 0646 mov r6, r0 + 1616 .LVL167: + 538:Src/File_Handling.c **** Send_Uart (buf); + 1617 .loc 1 538 4 is_stmt 1 view .LVU439 + 1618 005e 2346 mov r3, r4 + 1619 0060 2A46 mov r2, r5 + 1620 0062 0749 ldr r1, .L93+16 + 1621 0064 FFF7FEFF bl sprintf + 1622 .LVL168: + 539:Src/File_Handling.c **** free(buf); + 1623 .loc 1 539 4 view .LVU440 + 540:Src/File_Handling.c **** } + 1624 .loc 1 540 4 view .LVU441 + 1625 0068 3046 mov r0, r6 + 1626 006a FFF7FEFF bl free + 1627 .LVL169: + 1628 006e E1E7 b .L90 + 1629 .L94: + 1630 .align 2 + 1631 .L93: + 1632 0070 00000000 .word fno + ARM GAS /tmp/cccCjqCZ.s page 44 + + + 1633 0074 00000000 .word fresult + 1634 0078 20000000 .word .LC12 + 1635 007c 00000000 .word .LC11 + 1636 0080 44000000 .word .LC13 + 1637 .LBE27: + 1638 .cfi_endproc + 1639 .LFE1197: + 1641 .section .rodata.Create_Dir.str1.4,"aMS",%progbits,1 + 1642 .align 2 + 1643 .LC14: + 1644 0000 2A25732A .ascii "*%s* has been created successfully\012\000" + 1644 20686173 + 1644 20626565 + 1644 6E206372 + 1644 65617465 + 1645 .align 2 + 1646 .LC15: + 1647 0024 4552524F .ascii "ERROR No. %d in creating directory *%s*\012\012\000" + 1647 52204E6F + 1647 2E202564 + 1647 20696E20 + 1647 63726561 + 1648 .section .text.Create_Dir,"ax",%progbits + 1649 .align 1 + 1650 .global Create_Dir + 1651 .syntax unified + 1652 .thumb + 1653 .thumb_func + 1655 Create_Dir: + 1656 .LVL170: + 1657 .LFB1198: + 545:Src/File_Handling.c **** + 546:Src/File_Handling.c **** FRESULT Create_Dir (char *name) + 547:Src/File_Handling.c **** { + 1658 .loc 1 547 1 view -0 + 1659 .cfi_startproc + 1660 @ args = 0, pretend = 0, frame = 0 + 1661 @ frame_needed = 0, uses_anonymous_args = 0 + 1662 .loc 1 547 1 is_stmt 0 view .LVU443 + 1663 0000 70B5 push {r4, r5, r6, lr} + 1664 .LCFI15: + 1665 .cfi_def_cfa_offset 16 + 1666 .cfi_offset 4, -16 + 1667 .cfi_offset 5, -12 + 1668 .cfi_offset 6, -8 + 1669 .cfi_offset 14, -4 + 1670 0002 0546 mov r5, r0 + 548:Src/File_Handling.c **** fresult = f_mkdir(name); + 1671 .loc 1 548 5 is_stmt 1 view .LVU444 + 1672 .loc 1 548 15 is_stmt 0 view .LVU445 + 1673 0004 FFF7FEFF bl f_mkdir + 1674 .LVL171: + 1675 .loc 1 548 13 discriminator 1 view .LVU446 + 1676 0008 0F4B ldr r3, .L99 + 1677 000a 1870 strb r0, [r3] + 549:Src/File_Handling.c **** if (fresult == FR_OK) + 1678 .loc 1 549 5 is_stmt 1 view .LVU447 + ARM GAS /tmp/cccCjqCZ.s page 45 + + + 1679 .loc 1 549 8 is_stmt 0 view .LVU448 + 1680 000c 68B9 cbnz r0, .L96 + 1681 .LBB28: + 550:Src/File_Handling.c **** { + 551:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 1682 .loc 1 551 6 is_stmt 1 view .LVU449 + 1683 .loc 1 551 18 is_stmt 0 view .LVU450 + 1684 000e 6420 movs r0, #100 + 1685 0010 FFF7FEFF bl malloc + 1686 .LVL172: + 1687 0014 0446 mov r4, r0 + 1688 .LVL173: + 552:Src/File_Handling.c **** sprintf (buf, "*%s* has been created successfully\n", name); + 1689 .loc 1 552 6 is_stmt 1 view .LVU451 + 1690 0016 2A46 mov r2, r5 + 1691 0018 0C49 ldr r1, .L99+4 + 1692 001a FFF7FEFF bl sprintf + 1693 .LVL174: + 553:Src/File_Handling.c **** Send_Uart (buf); + 1694 .loc 1 553 6 view .LVU452 + 554:Src/File_Handling.c **** free(buf); + 1695 .loc 1 554 6 view .LVU453 + 1696 001e 2046 mov r0, r4 + 1697 0020 FFF7FEFF bl free + 1698 .LVL175: + 1699 .L97: + 1700 .loc 1 554 6 is_stmt 0 view .LVU454 + 1701 .LBE28: + 555:Src/File_Handling.c **** } + 556:Src/File_Handling.c **** else + 557:Src/File_Handling.c **** { + 558:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 559:Src/File_Handling.c **** sprintf (buf, "ERROR No. %d in creating directory *%s*\n\n", fresult,name); + 560:Src/File_Handling.c **** Send_Uart(buf); + 561:Src/File_Handling.c **** free(buf); + 562:Src/File_Handling.c **** } + 563:Src/File_Handling.c **** return fresult; + 1702 .loc 1 563 5 is_stmt 1 view .LVU455 + 564:Src/File_Handling.c **** } + 1703 .loc 1 564 1 is_stmt 0 view .LVU456 + 1704 0024 084B ldr r3, .L99 + 1705 0026 1878 ldrb r0, [r3] @ zero_extendqisi2 + 1706 0028 70BD pop {r4, r5, r6, pc} + 1707 .LVL176: + 1708 .L96: + 1709 .loc 1 564 1 view .LVU457 + 1710 002a 0446 mov r4, r0 + 1711 .LBB29: + 558:Src/File_Handling.c **** sprintf (buf, "ERROR No. %d in creating directory *%s*\n\n", fresult,name); + 1712 .loc 1 558 6 is_stmt 1 view .LVU458 + 558:Src/File_Handling.c **** sprintf (buf, "ERROR No. %d in creating directory *%s*\n\n", fresult,name); + 1713 .loc 1 558 18 is_stmt 0 view .LVU459 + 1714 002c 6420 movs r0, #100 + 1715 002e FFF7FEFF bl malloc + 1716 .LVL177: + 1717 0032 0646 mov r6, r0 + 1718 .LVL178: + ARM GAS /tmp/cccCjqCZ.s page 46 + + + 559:Src/File_Handling.c **** Send_Uart(buf); + 1719 .loc 1 559 6 is_stmt 1 view .LVU460 + 1720 0034 2B46 mov r3, r5 + 1721 0036 2246 mov r2, r4 + 1722 0038 0549 ldr r1, .L99+8 + 1723 003a FFF7FEFF bl sprintf + 1724 .LVL179: + 560:Src/File_Handling.c **** free(buf); + 1725 .loc 1 560 6 view .LVU461 + 561:Src/File_Handling.c **** } + 1726 .loc 1 561 6 view .LVU462 + 1727 003e 3046 mov r0, r6 + 1728 0040 FFF7FEFF bl free + 1729 .LVL180: + 1730 0044 EEE7 b .L97 + 1731 .L100: + 1732 0046 00BF .align 2 + 1733 .L99: + 1734 0048 00000000 .word fresult + 1735 004c 00000000 .word .LC14 + 1736 0050 24000000 .word .LC15 + 1737 .LBE29: + 1738 .cfi_endproc + 1739 .LFE1198: + 1741 .section .rodata.Check_SD_Space.str1.4,"aMS",%progbits,1 + 1742 .align 2 + 1743 .LC16: + 1744 0000 00 .ascii "\000" + 1745 0001 000000 .align 2 + 1746 .LC17: + 1747 0004 53442043 .ascii "SD CARD Total Size: \011%lu\012\000" + 1747 41524420 + 1747 546F7461 + 1747 6C205369 + 1747 7A653A20 + 1748 001e 0000 .align 2 + 1749 .LC18: + 1750 0020 53442043 .ascii "SD CARD Free Space: \011%lu\012\000" + 1750 41524420 + 1750 46726565 + 1750 20537061 + 1750 63653A20 + 1751 .section .text.Check_SD_Space,"ax",%progbits + 1752 .align 1 + 1753 .global Check_SD_Space + 1754 .syntax unified + 1755 .thumb + 1756 .thumb_func + 1758 Check_SD_Space: + 1759 .LFB1199: + 565:Src/File_Handling.c **** + 566:Src/File_Handling.c **** void Check_SD_Space (void) + 567:Src/File_Handling.c **** { + 1760 .loc 1 567 1 view -0 + 1761 .cfi_startproc + 1762 @ args = 0, pretend = 0, frame = 0 + 1763 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/cccCjqCZ.s page 47 + + + 1764 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 1765 .LCFI16: + 1766 .cfi_def_cfa_offset 24 + 1767 .cfi_offset 3, -24 + 1768 .cfi_offset 4, -20 + 1769 .cfi_offset 5, -16 + 1770 .cfi_offset 6, -12 + 1771 .cfi_offset 7, -8 + 1772 .cfi_offset 14, -4 + 1773 0002 2DED028B vpush.64 {d8} + 1774 .LCFI17: + 1775 .cfi_def_cfa_offset 32 + 1776 .cfi_offset 80, -32 + 1777 .cfi_offset 81, -28 + 568:Src/File_Handling.c **** /* Check free space */ + 569:Src/File_Handling.c **** f_getfree("", &fre_clust, &pfs); + 1778 .loc 1 569 5 view .LVU464 + 1779 0006 234D ldr r5, .L103 + 1780 0008 234F ldr r7, .L103+4 + 1781 000a 2A46 mov r2, r5 + 1782 000c 3946 mov r1, r7 + 1783 000e 2348 ldr r0, .L103+8 + 1784 0010 FFF7FEFF bl f_getfree + 1785 .LVL181: + 570:Src/File_Handling.c **** + 571:Src/File_Handling.c **** total = (uint32_t)((pfs->n_fatent - 2) * pfs->csize * 0.5); + 1786 .loc 1 571 5 view .LVU465 + 1787 .loc 1 571 28 is_stmt 0 view .LVU466 + 1788 0014 2A68 ldr r2, [r5] + 1789 0016 9369 ldr r3, [r2, #24] + 1790 .loc 1 571 39 view .LVU467 + 1791 0018 023B subs r3, r3, #2 + 1792 .loc 1 571 49 view .LVU468 + 1793 001a 5289 ldrh r2, [r2, #10] + 1794 .loc 1 571 44 view .LVU469 + 1795 001c 02FB03F3 mul r3, r2, r3 + 1796 .loc 1 571 57 view .LVU470 + 1797 0020 07EE903A vmov s15, r3 @ int + 1798 0024 B8EE677B vcvt.f64.u32 d7, s15 + 1799 0028 B6EE008B vmov.f64 d8, #5.0e-1 + 1800 002c 27EE087B vmul.f64 d7, d7, d8 + 1801 .loc 1 571 13 view .LVU471 + 1802 0030 FCEEC77B vcvt.u32.f64 s15, d7 + 1803 0034 17EE904A vmov r4, s15 @ int + 1804 .loc 1 571 11 view .LVU472 + 1805 0038 194B ldr r3, .L103+12 + 1806 003a C3ED007A vstr.32 s15, [r3] @ int + 572:Src/File_Handling.c **** char *buf = malloc(30*sizeof(char)); + 1807 .loc 1 572 5 is_stmt 1 view .LVU473 + 1808 .loc 1 572 17 is_stmt 0 view .LVU474 + 1809 003e 1E20 movs r0, #30 + 1810 0040 FFF7FEFF bl malloc + 1811 .LVL182: + 1812 0044 0646 mov r6, r0 + 1813 .LVL183: + 573:Src/File_Handling.c **** sprintf (buf, "SD CARD Total Size: \t%lu\n",total); + 1814 .loc 1 573 5 is_stmt 1 view .LVU475 + ARM GAS /tmp/cccCjqCZ.s page 48 + + + 1815 0046 2246 mov r2, r4 + 1816 0048 1649 ldr r1, .L103+16 + 1817 004a FFF7FEFF bl sprintf + 1818 .LVL184: + 574:Src/File_Handling.c **** Send_Uart(buf); + 1819 .loc 1 574 5 view .LVU476 + 575:Src/File_Handling.c **** free(buf); + 1820 .loc 1 575 5 view .LVU477 + 1821 004e 3046 mov r0, r6 + 1822 0050 FFF7FEFF bl free + 1823 .LVL185: + 576:Src/File_Handling.c **** free_space = (uint32_t)(fre_clust * pfs->csize * 0.5); + 1824 .loc 1 576 5 view .LVU478 + 1825 .loc 1 576 44 is_stmt 0 view .LVU479 + 1826 0054 2B68 ldr r3, [r5] + 1827 0056 5B89 ldrh r3, [r3, #10] + 1828 .loc 1 576 39 view .LVU480 + 1829 0058 3A68 ldr r2, [r7] + 1830 005a 02FB03F3 mul r3, r2, r3 + 1831 005e 07EE103A vmov s14, r3 @ int + 1832 .loc 1 576 52 view .LVU481 + 1833 0062 B8EE477B vcvt.f64.u32 d7, s14 + 1834 0066 27EE087B vmul.f64 d7, d7, d8 + 1835 .loc 1 576 18 view .LVU482 + 1836 006a FCEEC77B vcvt.u32.f64 s15, d7 + 1837 006e 17EE904A vmov r4, s15 @ int + 1838 .loc 1 576 16 view .LVU483 + 1839 0072 0D4B ldr r3, .L103+20 + 1840 0074 C3ED007A vstr.32 s15, [r3] @ int + 577:Src/File_Handling.c **** buf = malloc(30*sizeof(char)); + 1841 .loc 1 577 5 is_stmt 1 view .LVU484 + 1842 .loc 1 577 11 is_stmt 0 view .LVU485 + 1843 0078 1E20 movs r0, #30 + 1844 007a FFF7FEFF bl malloc + 1845 .LVL186: + 1846 007e 0546 mov r5, r0 + 1847 .LVL187: + 578:Src/File_Handling.c **** sprintf (buf, "SD CARD Free Space: \t%lu\n",free_space); + 1848 .loc 1 578 5 is_stmt 1 view .LVU486 + 1849 0080 2246 mov r2, r4 + 1850 0082 0A49 ldr r1, .L103+24 + 1851 0084 FFF7FEFF bl sprintf + 1852 .LVL188: + 579:Src/File_Handling.c **** Send_Uart(buf); + 1853 .loc 1 579 5 view .LVU487 + 580:Src/File_Handling.c **** free(buf); + 1854 .loc 1 580 5 view .LVU488 + 1855 0088 2846 mov r0, r5 + 1856 008a FFF7FEFF bl free + 1857 .LVL189: + 581:Src/File_Handling.c **** } + 1858 .loc 1 581 1 is_stmt 0 view .LVU489 + 1859 008e BDEC028B vldm sp!, {d8} + 1860 .LCFI18: + 1861 .cfi_restore 80 + 1862 .cfi_restore 81 + 1863 .cfi_def_cfa_offset 24 + ARM GAS /tmp/cccCjqCZ.s page 49 + + + 1864 0092 F8BD pop {r3, r4, r5, r6, r7, pc} + 1865 .LVL190: + 1866 .L104: + 1867 .loc 1 581 1 view .LVU490 + 1868 .align 2 + 1869 .L103: + 1870 0094 00000000 .word pfs + 1871 0098 00000000 .word fre_clust + 1872 009c 00000000 .word .LC16 + 1873 00a0 00000000 .word total + 1874 00a4 04000000 .word .LC17 + 1875 00a8 00000000 .word free_space + 1876 00ac 20000000 .word .LC18 + 1877 .cfi_endproc + 1878 .LFE1199: + 1880 .section .text.Update_File_float,"ax",%progbits + 1881 .align 1 + 1882 .global Update_File_float + 1883 .syntax unified + 1884 .thumb + 1885 .thumb_func + 1887 Update_File_float: + 1888 .LVL191: + 1889 .LFB1200: + 582:Src/File_Handling.c **** + 583:Src/File_Handling.c **** FRESULT Update_File_float (char *name, float *data, unsigned int bytesize) + 584:Src/File_Handling.c **** { + 1890 .loc 1 584 1 is_stmt 1 view -0 + 1891 .cfi_startproc + 1892 @ args = 0, pretend = 0, frame = 0 + 1893 @ frame_needed = 0, uses_anonymous_args = 0 + 1894 .loc 1 584 1 is_stmt 0 view .LVU492 + 1895 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 1896 .LCFI19: + 1897 .cfi_def_cfa_offset 24 + 1898 .cfi_offset 3, -24 + 1899 .cfi_offset 4, -20 + 1900 .cfi_offset 5, -16 + 1901 .cfi_offset 6, -12 + 1902 .cfi_offset 7, -8 + 1903 .cfi_offset 14, -4 + 1904 0002 0446 mov r4, r0 + 1905 0004 0D46 mov r5, r1 + 1906 0006 1646 mov r6, r2 + 585:Src/File_Handling.c **** /**** check whether the file exists or not ****/ + 586:Src/File_Handling.c **** fresult = f_stat (name, &fno); + 1907 .loc 1 586 2 is_stmt 1 view .LVU493 + 1908 .loc 1 586 12 is_stmt 0 view .LVU494 + 1909 0008 1049 ldr r1, .L110 + 1910 .LVL192: + 1911 .loc 1 586 12 view .LVU495 + 1912 000a FFF7FEFF bl f_stat + 1913 .LVL193: + 1914 .loc 1 586 10 discriminator 1 view .LVU496 + 1915 000e 104B ldr r3, .L110+4 + 1916 0010 1870 strb r0, [r3] + 587:Src/File_Handling.c **** if (fresult != FR_OK) + ARM GAS /tmp/cccCjqCZ.s page 50 + + + 1917 .loc 1 587 2 is_stmt 1 view .LVU497 + 1918 .loc 1 587 5 is_stmt 0 view .LVU498 + 1919 0012 08B1 cbz r0, .L106 + 1920 .LBB30: + 588:Src/File_Handling.c **** { + 589:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 1921 .loc 1 589 3 is_stmt 1 view .LVU499 + 590:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! *%s* does not exists\n\n", name); + 591:Src/File_Handling.c **** //Send_Uart (buf); + 592:Src/File_Handling.c **** free(buf); + 1922 .loc 1 592 3 view .LVU500 + 593:Src/File_Handling.c **** return fresult; + 1923 .loc 1 593 6 view .LVU501 + 1924 .loc 1 593 13 is_stmt 0 view .LVU502 + 1925 0014 C0B2 uxtb r0, r0 + 1926 .LVL194: + 1927 .L107: + 1928 .loc 1 593 13 view .LVU503 + 1929 .LBE30: + 594:Src/File_Handling.c **** } + 595:Src/File_Handling.c **** + 596:Src/File_Handling.c **** else + 597:Src/File_Handling.c **** { + 598:Src/File_Handling.c **** /* Create a file with read write access and open it */ + 599:Src/File_Handling.c **** fresult = f_open(&fil, name, FA_OPEN_APPEND | FA_WRITE); + 600:Src/File_Handling.c **** if (fresult != FR_OK) + 601:Src/File_Handling.c **** { + 602:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 603:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name); + 604:Src/File_Handling.c **** //Send_Uart(buf); + 605:Src/File_Handling.c **** free(buf); + 606:Src/File_Handling.c **** return fresult; + 607:Src/File_Handling.c **** } + 608:Src/File_Handling.c **** + 609:Src/File_Handling.c **** /* Writing text */ + 610:Src/File_Handling.c **** fresult = f_write(&fil, data, bytesize, &bw); + 611:Src/File_Handling.c **** if (fresult != FR_OK) + 612:Src/File_Handling.c **** { + 613:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 614:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in writing file *%s*\n\n", fresult, name); + 615:Src/File_Handling.c **** //Send_Uart(buf); + 616:Src/File_Handling.c **** free(buf); + 617:Src/File_Handling.c **** } + 618:Src/File_Handling.c **** + 619:Src/File_Handling.c **** else + 620:Src/File_Handling.c **** { + 621:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 622:Src/File_Handling.c **** //sprintf (buf, "*%s* UPDATED successfully\n", name); + 623:Src/File_Handling.c **** //Send_Uart(buf); + 624:Src/File_Handling.c **** free(buf); + 625:Src/File_Handling.c **** } + 626:Src/File_Handling.c **** + 627:Src/File_Handling.c **** /* Close file */ + 628:Src/File_Handling.c **** fresult = f_close(&fil); + 629:Src/File_Handling.c **** if (fresult != FR_OK) + 630:Src/File_Handling.c **** { + 631:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + ARM GAS /tmp/cccCjqCZ.s page 51 + + + 632:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in closing file *%s*\n\n", fresult, name); + 633:Src/File_Handling.c **** //Send_Uart(buf); + 634:Src/File_Handling.c **** free(buf); + 635:Src/File_Handling.c **** } + 636:Src/File_Handling.c **** else + 637:Src/File_Handling.c **** { + 638:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 639:Src/File_Handling.c **** //sprintf (buf, "File *%s* CLOSED successfully\n", name); + 640:Src/File_Handling.c **** //Send_Uart(buf); + 641:Src/File_Handling.c **** free(buf); + 642:Src/File_Handling.c **** } + 643:Src/File_Handling.c **** } + 644:Src/File_Handling.c **** return fresult; + 645:Src/File_Handling.c **** } + 1930 .loc 1 645 1 view .LVU504 + 1931 0016 F8BD pop {r3, r4, r5, r6, r7, pc} + 1932 .LVL195: + 1933 .L106: + 599:Src/File_Handling.c **** if (fresult != FR_OK) + 1934 .loc 1 599 6 is_stmt 1 view .LVU505 + 599:Src/File_Handling.c **** if (fresult != FR_OK) + 1935 .loc 1 599 16 is_stmt 0 view .LVU506 + 1936 0018 3222 movs r2, #50 + 1937 001a 2146 mov r1, r4 + 1938 001c 0D48 ldr r0, .L110+8 + 1939 001e FFF7FEFF bl f_open + 1940 .LVL196: + 599:Src/File_Handling.c **** if (fresult != FR_OK) + 1941 .loc 1 599 14 discriminator 1 view .LVU507 + 1942 0022 0B4B ldr r3, .L110+4 + 1943 0024 1870 strb r0, [r3] + 600:Src/File_Handling.c **** { + 1944 .loc 1 600 6 is_stmt 1 view .LVU508 + 600:Src/File_Handling.c **** { + 1945 .loc 1 600 9 is_stmt 0 view .LVU509 + 1946 0026 08B1 cbz r0, .L108 + 1947 .LBB31: + 602:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name); + 1948 .loc 1 602 7 is_stmt 1 view .LVU510 + 605:Src/File_Handling.c **** return fresult; + 1949 .loc 1 605 10 view .LVU511 + 606:Src/File_Handling.c **** } + 1950 .loc 1 606 10 view .LVU512 + 606:Src/File_Handling.c **** } + 1951 .loc 1 606 17 is_stmt 0 view .LVU513 + 1952 0028 C0B2 uxtb r0, r0 + 1953 002a F4E7 b .L107 + 1954 .L108: + 1955 .LBE31: + 610:Src/File_Handling.c **** if (fresult != FR_OK) + 1956 .loc 1 610 6 is_stmt 1 view .LVU514 + 610:Src/File_Handling.c **** if (fresult != FR_OK) + 1957 .loc 1 610 16 is_stmt 0 view .LVU515 + 1958 002c 094F ldr r7, .L110+8 + 1959 002e 0A4B ldr r3, .L110+12 + 1960 0030 3246 mov r2, r6 + 1961 0032 2946 mov r1, r5 + ARM GAS /tmp/cccCjqCZ.s page 52 + + + 1962 0034 3846 mov r0, r7 + 1963 0036 FFF7FEFF bl f_write + 1964 .LVL197: + 610:Src/File_Handling.c **** if (fresult != FR_OK) + 1965 .loc 1 610 14 discriminator 1 view .LVU516 + 1966 003a 054C ldr r4, .L110+4 + 1967 .LVL198: + 610:Src/File_Handling.c **** if (fresult != FR_OK) + 1968 .loc 1 610 14 discriminator 1 view .LVU517 + 1969 003c 2070 strb r0, [r4] + 611:Src/File_Handling.c **** { + 1970 .loc 1 611 6 is_stmt 1 view .LVU518 + 621:Src/File_Handling.c **** //sprintf (buf, "*%s* UPDATED successfully\n", name); + 1971 .loc 1 621 7 view .LVU519 + 624:Src/File_Handling.c **** } + 1972 .loc 1 624 7 view .LVU520 + 628:Src/File_Handling.c **** if (fresult != FR_OK) + 1973 .loc 1 628 6 view .LVU521 + 628:Src/File_Handling.c **** if (fresult != FR_OK) + 1974 .loc 1 628 16 is_stmt 0 view .LVU522 + 1975 003e 3846 mov r0, r7 + 1976 0040 FFF7FEFF bl f_close + 1977 .LVL199: + 628:Src/File_Handling.c **** if (fresult != FR_OK) + 1978 .loc 1 628 14 discriminator 1 view .LVU523 + 1979 0044 2070 strb r0, [r4] + 629:Src/File_Handling.c **** { + 1980 .loc 1 629 6 is_stmt 1 view .LVU524 + 638:Src/File_Handling.c **** //sprintf (buf, "File *%s* CLOSED successfully\n", name); + 1981 .loc 1 638 7 view .LVU525 + 641:Src/File_Handling.c **** } + 1982 .loc 1 641 7 view .LVU526 + 644:Src/File_Handling.c **** } + 1983 .loc 1 644 5 view .LVU527 + 644:Src/File_Handling.c **** } + 1984 .loc 1 644 12 is_stmt 0 view .LVU528 + 1985 0046 C0B2 uxtb r0, r0 + 1986 0048 E5E7 b .L107 + 1987 .L111: + 1988 004a 00BF .align 2 + 1989 .L110: + 1990 004c 00000000 .word fno + 1991 0050 00000000 .word fresult + 1992 0054 00000000 .word fil + 1993 0058 00000000 .word bw + 1994 .cfi_endproc + 1995 .LFE1200: + 1997 .section .text.Update_File_byte,"ax",%progbits + 1998 .align 1 + 1999 .global Update_File_byte + 2000 .syntax unified + 2001 .thumb + 2002 .thumb_func + 2004 Update_File_byte: + 2005 .LVL200: + 2006 .LFB1201: + 646:Src/File_Handling.c **** + ARM GAS /tmp/cccCjqCZ.s page 53 + + + 647:Src/File_Handling.c **** FRESULT Update_File_byte (char *name, uint8_t *data, unsigned int bytesize) + 648:Src/File_Handling.c **** { + 2007 .loc 1 648 1 is_stmt 1 view -0 + 2008 .cfi_startproc + 2009 @ args = 0, pretend = 0, frame = 0 + 2010 @ frame_needed = 0, uses_anonymous_args = 0 + 2011 .loc 1 648 1 is_stmt 0 view .LVU530 + 2012 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 2013 .LCFI20: + 2014 .cfi_def_cfa_offset 24 + 2015 .cfi_offset 3, -24 + 2016 .cfi_offset 4, -20 + 2017 .cfi_offset 5, -16 + 2018 .cfi_offset 6, -12 + 2019 .cfi_offset 7, -8 + 2020 .cfi_offset 14, -4 + 2021 0002 0446 mov r4, r0 + 2022 0004 0D46 mov r5, r1 + 2023 0006 1646 mov r6, r2 + 649:Src/File_Handling.c **** /**** check whether the file exists or not ****/ + 650:Src/File_Handling.c **** fresult = f_stat (name, &fno); + 2024 .loc 1 650 2 is_stmt 1 view .LVU531 + 2025 .loc 1 650 12 is_stmt 0 view .LVU532 + 2026 0008 1049 ldr r1, .L117 + 2027 .LVL201: + 2028 .loc 1 650 12 view .LVU533 + 2029 000a FFF7FEFF bl f_stat + 2030 .LVL202: + 2031 .loc 1 650 10 discriminator 1 view .LVU534 + 2032 000e 104B ldr r3, .L117+4 + 2033 0010 1870 strb r0, [r3] + 651:Src/File_Handling.c **** if (fresult != FR_OK) + 2034 .loc 1 651 2 is_stmt 1 view .LVU535 + 2035 .loc 1 651 5 is_stmt 0 view .LVU536 + 2036 0012 08B1 cbz r0, .L113 + 2037 .LBB32: + 652:Src/File_Handling.c **** { + 653:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 2038 .loc 1 653 3 is_stmt 1 view .LVU537 + 654:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! *%s* does not exists\n\n", name); + 655:Src/File_Handling.c **** //Send_Uart (buf); + 656:Src/File_Handling.c **** free(buf); + 2039 .loc 1 656 3 view .LVU538 + 657:Src/File_Handling.c **** return fresult; + 2040 .loc 1 657 6 view .LVU539 + 2041 .loc 1 657 13 is_stmt 0 view .LVU540 + 2042 0014 C0B2 uxtb r0, r0 + 2043 .LVL203: + 2044 .L114: + 2045 .loc 1 657 13 view .LVU541 + 2046 .LBE32: + 658:Src/File_Handling.c **** } + 659:Src/File_Handling.c **** + 660:Src/File_Handling.c **** else + 661:Src/File_Handling.c **** { + 662:Src/File_Handling.c **** /* Create a file with read write access and open it */ + 663:Src/File_Handling.c **** fresult = f_open(&fil, name, FA_OPEN_APPEND | FA_WRITE); + ARM GAS /tmp/cccCjqCZ.s page 54 + + + 664:Src/File_Handling.c **** if (fresult != FR_OK) + 665:Src/File_Handling.c **** { + 666:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 667:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name); + 668:Src/File_Handling.c **** //Send_Uart(buf); + 669:Src/File_Handling.c **** free(buf); + 670:Src/File_Handling.c **** return fresult; + 671:Src/File_Handling.c **** } + 672:Src/File_Handling.c **** + 673:Src/File_Handling.c **** /* Writing text */ + 674:Src/File_Handling.c **** fresult = f_write(&fil, data, bytesize, &bw); + 675:Src/File_Handling.c **** if (fresult != FR_OK) + 676:Src/File_Handling.c **** { + 677:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 678:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in writing file *%s*\n\n", fresult, name); + 679:Src/File_Handling.c **** //Send_Uart(buf); + 680:Src/File_Handling.c **** free(buf); + 681:Src/File_Handling.c **** } + 682:Src/File_Handling.c **** + 683:Src/File_Handling.c **** else + 684:Src/File_Handling.c **** { + 685:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 686:Src/File_Handling.c **** //sprintf (buf, "*%s* UPDATED successfully\n", name); + 687:Src/File_Handling.c **** //Send_Uart(buf); + 688:Src/File_Handling.c **** free(buf); + 689:Src/File_Handling.c **** } + 690:Src/File_Handling.c **** + 691:Src/File_Handling.c **** /* Close file */ + 692:Src/File_Handling.c **** fresult = f_close(&fil); + 693:Src/File_Handling.c **** if (fresult != FR_OK) + 694:Src/File_Handling.c **** { + 695:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 696:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in closing file *%s*\n\n", fresult, name); + 697:Src/File_Handling.c **** //Send_Uart(buf); + 698:Src/File_Handling.c **** free(buf); + 699:Src/File_Handling.c **** } + 700:Src/File_Handling.c **** else + 701:Src/File_Handling.c **** { + 702:Src/File_Handling.c **** char *buf = malloc(100*sizeof(char)); + 703:Src/File_Handling.c **** //sprintf (buf, "File *%s* CLOSED successfully\n", name); + 704:Src/File_Handling.c **** //Send_Uart(buf); + 705:Src/File_Handling.c **** free(buf); + 706:Src/File_Handling.c **** } + 707:Src/File_Handling.c **** } + 708:Src/File_Handling.c **** return fresult; + 709:Src/File_Handling.c **** } + 2047 .loc 1 709 1 view .LVU542 + 2048 0016 F8BD pop {r3, r4, r5, r6, r7, pc} + 2049 .LVL204: + 2050 .L113: + 663:Src/File_Handling.c **** if (fresult != FR_OK) + 2051 .loc 1 663 6 is_stmt 1 view .LVU543 + 663:Src/File_Handling.c **** if (fresult != FR_OK) + 2052 .loc 1 663 16 is_stmt 0 view .LVU544 + 2053 0018 3222 movs r2, #50 + 2054 001a 2146 mov r1, r4 + 2055 001c 0D48 ldr r0, .L117+8 + ARM GAS /tmp/cccCjqCZ.s page 55 + + + 2056 001e FFF7FEFF bl f_open + 2057 .LVL205: + 663:Src/File_Handling.c **** if (fresult != FR_OK) + 2058 .loc 1 663 14 discriminator 1 view .LVU545 + 2059 0022 0B4B ldr r3, .L117+4 + 2060 0024 1870 strb r0, [r3] + 664:Src/File_Handling.c **** { + 2061 .loc 1 664 6 is_stmt 1 view .LVU546 + 664:Src/File_Handling.c **** { + 2062 .loc 1 664 9 is_stmt 0 view .LVU547 + 2063 0026 08B1 cbz r0, .L115 + 2064 .LBB33: + 666:Src/File_Handling.c **** //sprintf (buf, "ERROR!!! No. %d in opening file *%s*\n\n", fresult, name); + 2065 .loc 1 666 7 is_stmt 1 view .LVU548 + 669:Src/File_Handling.c **** return fresult; + 2066 .loc 1 669 10 view .LVU549 + 670:Src/File_Handling.c **** } + 2067 .loc 1 670 10 view .LVU550 + 670:Src/File_Handling.c **** } + 2068 .loc 1 670 17 is_stmt 0 view .LVU551 + 2069 0028 C0B2 uxtb r0, r0 + 2070 002a F4E7 b .L114 + 2071 .L115: + 2072 .LBE33: + 674:Src/File_Handling.c **** if (fresult != FR_OK) + 2073 .loc 1 674 6 is_stmt 1 view .LVU552 + 674:Src/File_Handling.c **** if (fresult != FR_OK) + 2074 .loc 1 674 16 is_stmt 0 view .LVU553 + 2075 002c 094F ldr r7, .L117+8 + 2076 002e 0A4B ldr r3, .L117+12 + 2077 0030 3246 mov r2, r6 + 2078 0032 2946 mov r1, r5 + 2079 0034 3846 mov r0, r7 + 2080 0036 FFF7FEFF bl f_write + 2081 .LVL206: + 674:Src/File_Handling.c **** if (fresult != FR_OK) + 2082 .loc 1 674 14 discriminator 1 view .LVU554 + 2083 003a 054C ldr r4, .L117+4 + 2084 .LVL207: + 674:Src/File_Handling.c **** if (fresult != FR_OK) + 2085 .loc 1 674 14 discriminator 1 view .LVU555 + 2086 003c 2070 strb r0, [r4] + 675:Src/File_Handling.c **** { + 2087 .loc 1 675 6 is_stmt 1 view .LVU556 + 685:Src/File_Handling.c **** //sprintf (buf, "*%s* UPDATED successfully\n", name); + 2088 .loc 1 685 7 view .LVU557 + 688:Src/File_Handling.c **** } + 2089 .loc 1 688 7 view .LVU558 + 692:Src/File_Handling.c **** if (fresult != FR_OK) + 2090 .loc 1 692 6 view .LVU559 + 692:Src/File_Handling.c **** if (fresult != FR_OK) + 2091 .loc 1 692 16 is_stmt 0 view .LVU560 + 2092 003e 3846 mov r0, r7 + 2093 0040 FFF7FEFF bl f_close + 2094 .LVL208: + 692:Src/File_Handling.c **** if (fresult != FR_OK) + 2095 .loc 1 692 14 discriminator 1 view .LVU561 + ARM GAS /tmp/cccCjqCZ.s page 56 + + + 2096 0044 2070 strb r0, [r4] + 693:Src/File_Handling.c **** { + 2097 .loc 1 693 6 is_stmt 1 view .LVU562 + 702:Src/File_Handling.c **** //sprintf (buf, "File *%s* CLOSED successfully\n", name); + 2098 .loc 1 702 7 view .LVU563 + 705:Src/File_Handling.c **** } + 2099 .loc 1 705 7 view .LVU564 + 708:Src/File_Handling.c **** } + 2100 .loc 1 708 5 view .LVU565 + 708:Src/File_Handling.c **** } + 2101 .loc 1 708 12 is_stmt 0 view .LVU566 + 2102 0046 C0B2 uxtb r0, r0 + 2103 0048 E5E7 b .L114 + 2104 .L118: + 2105 004a 00BF .align 2 + 2106 .L117: + 2107 004c 00000000 .word fno + 2108 0050 00000000 .word fresult + 2109 0054 00000000 .word fil + 2110 0058 00000000 .word bw + 2111 .cfi_endproc + 2112 .LFE1201: + 2114 .global free_space + 2115 .section .bss.free_space,"aw",%nobits + 2116 .align 2 + 2119 free_space: + 2120 0000 00000000 .space 4 + 2121 .global total + 2122 .section .bss.total,"aw",%nobits + 2123 .align 2 + 2126 total: + 2127 0000 00000000 .space 4 + 2128 .global fre_clust + 2129 .section .bss.fre_clust,"aw",%nobits + 2130 .align 2 + 2133 fre_clust: + 2134 0000 00000000 .space 4 + 2135 .global pfs + 2136 .section .bss.pfs,"aw",%nobits + 2137 .align 2 + 2140 pfs: + 2141 0000 00000000 .space 4 + 2142 .global bw + 2143 .section .bss.bw,"aw",%nobits + 2144 .align 2 + 2147 bw: + 2148 0000 00000000 .space 4 + 2149 .global br + 2150 .section .bss.br,"aw",%nobits + 2151 .align 2 + 2154 br: + 2155 0000 00000000 .space 4 + 2156 .global fno + 2157 .section .bss.fno,"aw",%nobits + 2158 .align 2 + 2161 fno: + 2162 0000 00000000 .space 24 + ARM GAS /tmp/cccCjqCZ.s page 57 + + + 2162 00000000 + 2162 00000000 + 2162 00000000 + 2162 00000000 + 2163 .global fil + 2164 .section .bss.fil,"aw",%nobits + 2165 .align 2 + 2168 fil: + 2169 0000 00000000 .space 4144 + 2169 00000000 + 2169 00000000 + 2169 00000000 + 2169 00000000 + 2170 .global fs + 2171 .section .bss.fs,"aw",%nobits + 2172 .align 2 + 2175 fs: + 2176 0000 00000000 .space 4148 + 2176 00000000 + 2176 00000000 + 2176 00000000 + 2176 00000000 + 2177 .text + 2178 .Letext0: + 2179 .file 2 "Middlewares/Third_Party/FatFs/src/integer.h" + 2180 .file 3 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 2181 .file 4 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stddef.h" + 2182 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h" + 2183 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h" + 2184 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h" + 2185 .file 8 "Middlewares/Third_Party/FatFs/src/ff.h" + 2186 .file 9 "/usr/include/newlib/string.h" + 2187 .file 10 "/usr/include/newlib/stdio.h" + 2188 .file 11 "/usr/include/newlib/stdlib.h" + 2189 .file 12 "" + ARM GAS /tmp/cccCjqCZ.s page 58 + + +DEFINED SYMBOLS + *ABS*:00000000 File_Handling.c + /tmp/cccCjqCZ.s:20 .text.Send_Uart:00000000 $t + /tmp/cccCjqCZ.s:26 .text.Send_Uart:00000000 Send_Uart + /tmp/cccCjqCZ.s:40 .text.Mount_SD:00000000 $t + /tmp/cccCjqCZ.s:46 .text.Mount_SD:00000000 Mount_SD + /tmp/cccCjqCZ.s:86 .text.Mount_SD:0000001c $d + /tmp/cccCjqCZ.s:2175 .bss.fs:00000000 fs + /tmp/cccCjqCZ.s:92 .text.Unmount_SD:00000000 $t + /tmp/cccCjqCZ.s:98 .text.Unmount_SD:00000000 Unmount_SD + /tmp/cccCjqCZ.s:138 .text.Unmount_SD:0000001c $d + /tmp/cccCjqCZ.s:143 .rodata.Scan_SD.str1.4:00000000 $d + /tmp/cccCjqCZ.s:156 .text.Scan_SD:00000000 $t + /tmp/cccCjqCZ.s:162 .text.Scan_SD:00000000 Scan_SD + /tmp/cccCjqCZ.s:344 .text.Scan_SD:000000b8 $d + /tmp/cccCjqCZ.s:2161 .bss.fno:00000000 fno + /tmp/cccCjqCZ.s:355 .rodata.Format_SD.str1.4:00000000 $d + /tmp/cccCjqCZ.s:359 .text.Format_SD:00000000 $t + /tmp/cccCjqCZ.s:365 .text.Format_SD:00000000 Format_SD + /tmp/cccCjqCZ.s:485 .text.Format_SD:00000078 $d + /tmp/cccCjqCZ.s:494 .text.Write_File:00000000 $t + /tmp/cccCjqCZ.s:500 .text.Write_File:00000000 Write_File + /tmp/cccCjqCZ.s:604 .text.Write_File:00000050 $d + /tmp/cccCjqCZ.s:2168 .bss.fil:00000000 fil + /tmp/cccCjqCZ.s:2147 .bss.bw:00000000 bw + /tmp/cccCjqCZ.s:612 .text.Write_File_byte:00000000 $t + /tmp/cccCjqCZ.s:618 .text.Write_File_byte:00000000 Write_File_byte + /tmp/cccCjqCZ.s:721 .text.Write_File_byte:0000004c $d + /tmp/cccCjqCZ.s:729 .rodata.Read_File.str1.4:00000000 $d + /tmp/cccCjqCZ.s:745 .text.Read_File:00000000 $t + /tmp/cccCjqCZ.s:751 .text.Read_File:00000000 Read_File + /tmp/cccCjqCZ.s:976 .text.Read_File:000000e4 $d + /tmp/cccCjqCZ.s:2154 .bss.br:00000000 br + /tmp/cccCjqCZ.s:991 .rodata.Seek_Read_File.str1.4:00000000 $d + /tmp/cccCjqCZ.s:995 .text.Seek_Read_File:00000000 $t + /tmp/cccCjqCZ.s:1001 .text.Seek_Read_File:00000000 Seek_Read_File + /tmp/cccCjqCZ.s:1271 .text.Seek_Read_File:0000011c $d + /tmp/cccCjqCZ.s:1287 .text.Create_File:00000000 $t + /tmp/cccCjqCZ.s:1293 .text.Create_File:00000000 Create_File + /tmp/cccCjqCZ.s:1372 .text.Create_File:00000038 $d + /tmp/cccCjqCZ.s:1379 .text.Update_File:00000000 $t + /tmp/cccCjqCZ.s:1385 .text.Update_File:00000000 Update_File + /tmp/cccCjqCZ.s:1489 .text.Update_File:00000050 $d + /tmp/cccCjqCZ.s:1497 .rodata.Remove_File.str1.4:00000000 $d + /tmp/cccCjqCZ.s:1507 .text.Remove_File:00000000 $t + /tmp/cccCjqCZ.s:1513 .text.Remove_File:00000000 Remove_File + /tmp/cccCjqCZ.s:1632 .text.Remove_File:00000070 $d + /tmp/cccCjqCZ.s:1642 .rodata.Create_Dir.str1.4:00000000 $d + /tmp/cccCjqCZ.s:1649 .text.Create_Dir:00000000 $t + /tmp/cccCjqCZ.s:1655 .text.Create_Dir:00000000 Create_Dir + /tmp/cccCjqCZ.s:1734 .text.Create_Dir:00000048 $d + /tmp/cccCjqCZ.s:1742 .rodata.Check_SD_Space.str1.4:00000000 $d + /tmp/cccCjqCZ.s:1752 .text.Check_SD_Space:00000000 $t + /tmp/cccCjqCZ.s:1758 .text.Check_SD_Space:00000000 Check_SD_Space + /tmp/cccCjqCZ.s:1870 .text.Check_SD_Space:00000094 $d + /tmp/cccCjqCZ.s:2140 .bss.pfs:00000000 pfs + /tmp/cccCjqCZ.s:2133 .bss.fre_clust:00000000 fre_clust + ARM GAS /tmp/cccCjqCZ.s page 59 + + + /tmp/cccCjqCZ.s:2126 .bss.total:00000000 total + /tmp/cccCjqCZ.s:2119 .bss.free_space:00000000 free_space + /tmp/cccCjqCZ.s:1881 .text.Update_File_float:00000000 $t + /tmp/cccCjqCZ.s:1887 .text.Update_File_float:00000000 Update_File_float + /tmp/cccCjqCZ.s:1990 .text.Update_File_float:0000004c $d + /tmp/cccCjqCZ.s:1998 .text.Update_File_byte:00000000 $t + /tmp/cccCjqCZ.s:2004 .text.Update_File_byte:00000000 Update_File_byte + /tmp/cccCjqCZ.s:2107 .text.Update_File_byte:0000004c $d + /tmp/cccCjqCZ.s:2116 .bss.free_space:00000000 $d + /tmp/cccCjqCZ.s:2123 .bss.total:00000000 $d + /tmp/cccCjqCZ.s:2130 .bss.fre_clust:00000000 $d + /tmp/cccCjqCZ.s:2137 .bss.pfs:00000000 $d + /tmp/cccCjqCZ.s:2144 .bss.bw:00000000 $d + /tmp/cccCjqCZ.s:2151 .bss.br:00000000 $d + /tmp/cccCjqCZ.s:2158 .bss.fno:00000000 $d + /tmp/cccCjqCZ.s:2165 .bss.fil:00000000 $d + /tmp/cccCjqCZ.s:2172 .bss.fs:00000000 $d + +UNDEFINED SYMBOLS +f_mount +fresult +malloc +strcpy +f_opendir +sprintf +free +f_readdir +strcmp +strlen +f_closedir +f_unlink +f_stat +f_open +f_write +f_close +f_read +f_lseek +sizeoffile +f_mkdir +f_getfree diff --git a/build/File_Handling.o b/build/File_Handling.o new file mode 100644 index 0000000000000000000000000000000000000000..b19da18efca02fe99af47ec9b4bef9f9495c1f81 GIT binary patch literal 34784 zcmdsg34B!Lx%WAAgg_FKpn#Sk%Y;Njk|qNL6y;M? zv}(0#FSS;!wQ8+aw61tvYOPhTTJ&14w%V&+tXkLWervz-{r~U#oHJ*JaO-!M-*ES)-sfG;l5-Ac)vXGfrfFE4X_Odo$}m1ULrJ`q3QCNyQD+P;Hw^#XX4stK zU2*t}zaI89UX&oa(9rq|Yt?OIc>QLkmMwhl2r> z%cl+-;oiO|87Pxw4Bmawes4He+46*EglV%d+@o+BY#SxZo=bbJK*_z~qJ}BqqI&9- zXw7=9nGel%4@_=2d1uYf^BX4Z%=svD%%Owh>nEyq7$tu?Xj#Z^oEskNunI;t?D;InmJZCrUXDEz?Xp@mv0>6) z_ij^Kl?Tgt4|rZ1uVTvuHC9@Yh4Q}pv(buk?#Pr@yn8TMpJBHmph}GGP(oDb1w@tk zV7!kQo3#zz?Fk3N*{ap_;lJaNI|m_vu?YtFCZrV`{^UaD~pzs?eY= zg$5tF^9{#1uA%LQ}g!z5Stq!DxSP|K?CPhMTHM z%~AA*qU~K@N3XMQVE70y4uk2*3Qo8@NoCmzP=ss$Gp!|Ihlv{-*>-> zj31}+f$;{;Yji_y!loDo$T`2{?HV%m^=5^a-HW{X8Dq0!M6>NjW^$AuEOK!M8v9UslZ`%>UUA`Bcb1 zc&nsgS$ILXNIZw&%m2XI`;Te(T~ATN#7zqaH;n8YylUjY;O|Gi8k`_`90#qJ67o1f z+0}U*1G|sfxujP;D|KIeXiKJqgN|taWt4frR6Fy{Tr=m)cP7SNx~i{c_Wh6CnfYKE z#$Kw5k*fz+fKT7jt2|fmNA7$-$;aqx#@zq1HNzegN14`&-P1lC>WD`BLqpLm1KXlq zNfS)j2*oG8(&8*-WlVUsVWP^zM6~g``>nNJ_0j!S-%knWIC9M%8hkJ=bM}KDvX7*X z^qfsmHFe*ht(=H+ut(b9 z!EDw2ty{=Au|kA(D}3QuSV6pwNI!7&wKaxXYeO~FEw!PxfmnNAsI_+|j?$@9`?hj{ zwPfL;Xf)J1*xu=oeR+53`>t;ltuAVsY0s6JJ(u^oPH4Hn^_BaRln*Xlc;5$`Prv5_ z<6F}|@Spyd4}N|6_zx~!IicZ~?;AVyQQ3$1#yR4f)pPO%3ww0!Ow?X}y0d1`QIl(9 zz|ngTzUTVZm+IKe{9Btx3L)Upj#V7l|Jh^Jf2Zw_3k<`h+Tk&qy@ruq2kJ|-j3*q< z&E-$I612;c;(>fP>Hm=%;PO5W1#qtaHrx3$^8G)H8iwkn(%q0eJodWp`N~je4&o<6bfN{P;@8k+05pJRZ-YMS*tI_bs%zews1-fnh}LTb{@@0@aZE+Jx)!`22zN%-p~a zXrW!WrVD9=K!tDxT&WP;hIbFjfzx3irEDDe9+$_T>GF7bk<(Pqz2G3h3)vW!Q#}u< z-{0Uj%~K5>|B?&}ya(~)xf?(J#xZBYTzX}ue{E_mG=kF^{D~0)85B{E(z9D2FIDyiL zkmU^MWNLw+opc{3q5O5i%6KiP9ZH76+$Ox>LxK zU?)R9UC7zN4OBiu$cl{Zz5RxNR|*s3DylSm%*s>{V>pNok1;%7vHF?r_fah~*S{zA zdI&SRhYkO^s>lp73+GA0Ji)_saK5C-7yLb&y;sPTU^#=kK-~L-10*jDaNxR%(t|xz zzC2|K07*gjG8E4t_Q93zIVh)BWct6Kx)zL#fsRuR|JDAR!9@_kf2O4$h@aey=+Kbi zzedQh!7-FxD}M5V)jp8dNfi0PJLvX@LWY75ko=L5#lbJwpd0*j>MAM;e#~fYNB#O8GCu=HFT;PYgc8c=M&I3+LaVN#V%>MIflzZP&B&^)Z!!E2ySIRqndkpiYBd%) zJ(M1oOc=pby8pG^c_H@p6GHlePob*+Ny(x=_#&mx`f0~ilxp}m$<}~S4$}?KKQdDX z-S44Rc8bY`%l~4=At>ZLf|^Fo5Akc}d<(y>oSEnXch2!}@5xC;*_*Qx)qFXhfs>MR z4K3xYz;9~K>(CG690ETrry0NLIXl4*=6Il=k&_S3n4AKXGjqNLepb$7aFw0oMmfju zybJICcirCriA8o`Oi~FiCID*?6wK!9rSlt?EI^x1HmzL@MjSO za1_hq59)E+OfdVeWtmDOg10dpHjQnXU+pb1 zDrhq-`o9uaJ1JHERGbscODO#}k?ymlYzo7~Z{W{fZTVhG?_jDJ%p`~d5U2H}n2f_b zNHGIOa<;SG=~i++rG$e(XGkS5-~0|3=J_t|n$=F>4>q$2b|=qAqaZG%!f@{Rh|!a`7_`dp}Mcj^Wa1UhGPxEu)|WKeMr4V2iGD z1(hgtwaxmm#k$>Q-Da^KwORLCtl!$KhlEv_0T&!PA44?7Y<9))yGBoUqi_m@9Difc zR0uU2a;4Sc^3OF27ea+&cZpVUZD)PgR{XZOw&Ax`Y!%f)u?dQFvK{4olQ*f%c1 zn9N(!tkf=dO<|kg0r#J=>(nlHl~ZF01Pih2)Gl`|V`?{naSC=jwND~2o!ZsOsXb(i zHdq<@!e&J+RsgQFfh`tmvd!9Vu_|oVnZmMDyBeaSrgl&Z|Gm_HPwIc|)TVlFK?aJ= z2k~nj@A3f*gRA11WL%kU7*o|)TjWY(a(Pa85B5Ti#=9`3JkUt!ZhCG(ry7OqMb5DC zTE%QM3LC-Vlw7D;s@E}sFk@9M+!iQoLz(MCqpe~TaxJH&_PC|JVrh@4aTLK)2yFU? zrJ_qvrX}VR@n96)3P0F6jrGn8J(4a4Wmr+;%k_{~qo@1&=dT>?|4-erQ1+($PfNroom1$2K;N?VmnhPmC zo$Bz!;{!ciE<8>oB!bp;A~3Jmd^M@8bZmpPh#?1AlO zZqo$q$%Tdauk^%~ot{2*cFUV zv=~L>Abd#{L)6AF9>A~pu%nwcff3>{V}GXAO%LmCS_y6ycD)!rY?d%z*MjkV>;>7V zmy7)u@T-@tUzu`9nFjVu?626O=S?}Jd}y;?wOB6r)dt?QSYvJ0hZd{EW_>QKLd;&( z@;Zo^GiS>SLlE+i(xZi=t$P(v$wbc2kosJAI3swNxmI|pAJk#SKESMiigkct59FKw zfP9#jIC9EvdyveVaE_{v-IwT`z7FoIOdsqUOrZe{-TKR|^l>DXV4q}*t})eEH9}=J z>qd)JZL@B-SZy}z9%0#|FeYAZ?c8ESmiZPrT_{De|C|*!57FZ0A!L%W3p90x3N`;PA8uJbF5m=&2ZNPGfbVqNXuhmEdna7;If6$71{9!^vQ2*PhHy6&*9~Edinqg^mL`e)1Sek zr-u?ftpYo-Wi*}O?(TlVJikZp_d!bUMbNNX`xtoiv`TnKogFlt;O}WLI23+u`zzD_vN6~)uopfr z{w{a;dqw=+BfL>&#~Th$NQO~35kH&&@8~-5;mv8%VqyYxK!Yv&i`FnJjlx0JM5QSh z9!YZ|KHv*)fEHVIyw*~usJDQZGzp3V;PIl9X>(3aW17jyY#vCw+^&GCc|C3j>*;YI z#ObjC%x3Jrtd5RxM@6@rih^*dTPN~S8H!864hr8+0Ob*A{F@YEFi z_s*zD z4t+Gltkv_3H?rzA%e4yv-Z|0hB+vdgX^Gd3doN&fspNgJUCs)+)ka|pguI*f1FH_J zsH;L<`4o_}d6y;E>>jXrNAC&SX5ys^!oj2);-ssLH~$52KY=qd3#XuEgY7X$)jhSj zusWN&O3Cq(lB$wk!J(boT?OKU9hYb?L(QPLJwE8Y8n_EbbIYqtr^EwJ&P7S#a7LR zkWn{iyNr51Sd4nRW?4}q80Cj+BF-XE8HX3zwhk3)0cYE2@B3m8V=Wh~x6xO3i#@fd za``Q!Nshwbh$KD=!;o;ez2}rz!;Pyp$BhA_Z0RlpvLB=sh#oiR^P*z5zVQm75yJi+ zqBgrxZMvE#vkQ2WHXAE`I`$&Q&RejYBNfPP>L>2cj2T~4e8G0(*n`3N8dS`waihhc zYf;yH*fu&fpGHpwvn$D{J!FnBT#hb*kpg`;%!M)Qz`EX0@z&#q!4Eo}*y_?wIr(I(G0!=14(?S!-iY4tc8_f9hi zxC>sNW1^5!2)Z2i^88~^8~4Hq)Cg2M>gA(BY10r;dXAaq)z(-$7<4Gjhf)R@e#;vf zW0ZZIM`xmDTD)c!!m<_76&`a*8XdaOMqK~ ziEa~|PIX!pr_*eGX;(sx=@OTK66X9cXgPLhc)l{!v? zWpHfwqBt&33{?dhkbG7o1PY^b$_)1O`BfQuJflarsX1fpQh17@cd@fZ*>Kwumz&K5 zoN}YsMxb)QuqXVrq!(#1fhL_|kO>7kdR=w6B(0Wpw)4(d# z8UzNFq_GjK&02$?y&N^pO;8yvPO!0Isb#c;Tvco%FjvkAK)MP$8bjEG-6;l{u;B;< z)is1os(93{tc4iCQ8Qt4B#|mfN%Vk)S_YB#aZo;Dpy5U(8%Cf?k_B)L95NXtL2H~u zu5;5iTH-d=Ii;hQb)8m16?SwTfn!N!%&pEat|cu?2Vp2lOq!>Ys7<&uNlf}NEhfC3 zBqsfl78BSwr*E+Ajm|rEdqYA9$irq|L(~>k8#lL9{0&l-1 zX*>`1@3jWu4OL7S(g9S;QWcvCy2p+>uKZ9LZO}W$6;+Z(#R|A>(oqmLsA7T-oaTYq zt#t_dw9YkvTXhk?_BIoxW3eN>gep}`Xx5ov?N;n&f;N|+aRBUJY7N5Es+geh0$7gZ z>4qhQ?Scj;43S+v+JpfcTM#>zR|a=5~xUkNvCs+cgUxN_oTk#-69sbWIVgJA8@8U&h5n)qd4&C?o$B}ZyF8yKq z>iNkcr!lt`g0-5o_4WvDC49fooZs9mWH}Ri6?XD0yC|yde?ojiIF)uA4QQ#${0f(o zcv+9F#%{I_bsDRCySnQxcVEwAqvQ=(noAKebChI&&kvZB4es}HXtlyx#PJW3wj933j_VGj?-@a9wuWw$DK zMZ2x?mSg93(@S4pq-#q%xE^XaxUt?Xqi}~hJ2khPmXwDfy6!P>Sxs*Pb`b&U@}iEd zy?wFL-hR#^T=koVS9Pwtz|6%l*EHjtsix2Lx_sr{be~z~4dBss0BJAy$B+zp@#bU3 zF|L$^db9t%dZ~q8vryMAaCsBzRkEJfw>T%qo9%;b6qk6%fET2%m7vSLevp|y_t-_= zd{t^#pW|EPP4&4?g<7t6JeXs(b`aW`Aj@>1QwU|=ps&!I%bI204Brw}%+mT9(4PoN zh7UHqS&O}6L1g(Fe2XBMgz^OHEdr}tSA(SqV8eG{k=MIqvDftFtaN20H0cipT2!vu zgYX+va}b1%#nGOOGUYo@yMW0UwEol0$wPSKv`MzEghd2AJsxdZLbQhs-E&LXL=u@I_ay#1IddI>gog4I!%N%oyYN4@UQyL|4J+bp96EGsf+6 zr-#@iZyH^6d)>YYWX$w>kS&f>kFUX-vOZ@qh9D9F^?p+gf48rpAqSIzb<2?Xd3dJS z=l({Bvjn9EZxJvU(q`9zQ=V+r$H@flR!kP3djhnTJ9poroTc>UO=mJtpv^*N1Ju_4DbE@8afhgVv-Li8M^Gmg?;1dnLxRwZKP5fOWRt5$hEi@j-*hlrhr zRgN?~g}LSNxvR?J$=eXmU6yX7@(^=)aA&Y@brYFCECfsq6XL~yRLc#sHCoZ*EB+hV z+JMCfvm#(;c*7zU9a^-(oxjq`D7|S%!P#G_W`E1yoc%uE zTqZydFRl{S?DrwVDM%EWHcq8TEg{Sv`JDd}Wa9ikEI}S^hNU?YbL7Cn3~S)=!sT

vNLU_3J(CFb*91_@u`Xk54|#9u6&^c=P(u z9v&Uk*x0G(ErhU|*tmN~V3C*&4^XOH z=gnT}&D3H{7^rczFnx;`CB^(}6|>8?>c63Xy{h+Q>HH6N?fD3rtI7YY_*$d=U6Hjo zlQg!p_w@~Q8r?X-+}am2hKKRWr!hQ;Gp<;-(LEfA?HG(2YX`gVzG{Rox<|VE2HImr z>x%ktTcoXeS)`_Bq#37WJVi6QBYctG=#LBy4B$j<$bjk7@TQfczR})NQxj=kwW_tc zzPA3vmS#BaY-{i6i$WRix~iY8{lmSR`|*M-Us{Cgc4HVXz%t0F0kaWBgTP0e+U5xlun*NRXO-s*v^{jo@Et-~fwiPg@Y_8|k+>l;t3UR7TkX|8UmUR~E# z*J7MB)N8e~V@E8C1TY=_k!~~}^_#-s);g=%t6N5#Mw*tbtgC4=@NSxlPPKzRRpnu$ zwX?mS0l{r!lMYpV9z!$QB6W>TYnQKx)HJo!kyW>@zO~JO+m7~OoVlOW)Pkz5^&9FU zF{7p@+IbpmMbtaENV;k=T3_E7ZZbM`4zTud$Y<*ju%H3dW$Y_t@Cn3o# z=r`5B#@hNuIL4{DbV!0)e>>RSusDFIaD7s)hJ@qlpgXcT8q@uRZd1WyZ1hF@9V4c` zW@Ln!#ZYSBtW${gx3r*pc18!f@qSa3+}irq2E}esZ++|NV61a+2gOYd#&FNTP)v=H z7++U5x>a~OS1pl~TI$>CBF!yLZRnS}T8`1qErUk5x-Hy_Hf%YK1GJk1+vsLex+B}! z`?TFwzq+nzZ5#8Yn}7=_?{v^Jo^t4M z)~#}6=C<+{eD-6Yxd+YZ@9m7VZtWP34t3+j_Q+6sSNl-;@@Ri_s2y+K zN1AJvB`Jdw86N14@!H&2-nceYGiP2%UvY=#R?IziPDRCnQ0bP=!L5rsF-)T)rCa8K zj`eKa(gExSzk6`oaiv{zjwi`gwGnR=S*j0qz4sEJ~v*e=cufV|ZNn|qXe{zwLIn&mmp6fZ!eLmxI z*5z#_hyR4SyoI$aBX5uIT<>|F^WA%s+f=J;tGE(uCdcFSweQOtKeL`Xjaq|Gp95+{TzB{V__v*;c_jDUQtz?ZozHDg9NpPNLL}+vJJy z@_u=Ib3>X~BUkAkvQ-jmyYXj(L=OLc5Z~O!_#}Jdm43cGY{tixQF7yN4~hOKDE;}i z7XK&_-`seaHBo<((vRnBQd}7&H~#RR7%%?6gTnQF7zmsl$`==O)SLCdv8N*7)W&j*Am0xsBtK==eydz-=r{ zk}pc4^&NJL={BmYqC&T^G>Kk@8L9rBp;qc_tj8RIoQ@nh*;s#_J(vkz7lqg=L1YLPW z`ck3ufLZAOD}Z!y5%z5S+4&lvwb9>A*eTzHJsa!uoj_}&{C^kc}+G(+gqTmjs89mLf0=h{uMOq^IRvJy-h+k z>eG(3kyzZ2 zLhE=-jm-)4Y~z~=^ekh00zK0>8#GxuKhq3;;wMgHeM-IvE{+++T{z*k?y=Z+Bkb!x zx!dBn{hJ1Z0XI+gSac9H2nZU1+ z;I4vP^U2jd?``Po6^9GCKjq}8%W3qVAA4YvzAkXJ8%7AUt0ReT(O48XwgTPq$mC}I z+Gzm%O7eU3Iuz)|`90}V^?VJShDV}FLvNetok4`&*~C8mXaVbU9SC&c#R(!7nOjBg zJ|N@zdt$$y-!7cCJtp)MM9@zQ9u)Ke>6d3j0mNHO9K@s5LKjt`1Jz=LpqOvVLT5@8tvk`9Ej<89oUK&gQ$=CoVT<`zj(`2 z%_Dw&B0zoE;TaC?98X03DkAEy0MJ{_uiA_Hs=cVM+Kcw9_9DN^p4C6# z(;oBQLIi&!5qyMh1a|87lin@zONh|FLg?!RRevGAyGTR-5hC;+7x}Zoe@Xa%5dI+` z+w(RN?Rk%g_IyOdY2l}WUlLEpn_oh6v7y`}m;t^sZ)K!+N&XQ}EosEFl8APmNCbbA z@VkW{6aH@DpC|l%MC9WkBHH;h5%rVX^C#hdPJ}yaetR z+5-%nBkL6GtM` zsPYFp-xvBi!8-(>7ko|deZlb@|EO0gSR=^uAMytTuM)gX@POcRf^P_ZDabFhu>Mp* zev5_l8o^D11A=D?UM$Ejm{9+xg8Wtq=_dtW5`0VWbHQnDt#^`Ox8PR6J%X1D{zULu z!S@8e5)5F1(C-96eio7RJi+q>uN1sN@N+@0SL^2r775N3Y!U1e91Kh&aw}C!UA(hX}n3iJ0f#7WxN7%=7Do-cQ6lzengl3LX|LO3`-K2%akV9l^T= ze<%2fV76b^n&yh`{t3Vn;hj^UGR@Y=>JL3 z#EA-Nui#q2J|f~868an>;<`fU9}4{wBI3A*Sd5o!1s@_JjweL^g3vDszAF58gnnP} zW8wc*XkJ6oP6`oza)cf)m`{Y?kl=B`Um&*yWa|H8zf$lj;r~qVS46buIicSm;ynFbBK&_rgukx@jd7r1AFqZhoIr$pvfvcqA1}C? z2>TJC2L)q-7Z6Xxho=O;Bm5f$4+uU-gq>G~{y^|!!IbgZPMTmQ5pfm^o=4{eJP}_u72GZSD+GT^ME!e(enRkN;x?=&LjP~Uj6BVsOho?{5fRTk!CH|w2)&Vr z@zYI2-iL@2aoApAz~N;s)GDB4UodC-@N&@up7F@?0Y5 zJi*CC=vN4?6g-)TINF6C5&BG_zfHus!#?3(BmCQizFX)g1%FROd~XqP?0i@7Ln7kw zMK|~x+ z5^*j0jNtEt|E}PNg1Akgu46ocI89bGPGc0}6iH#3;BkTr1givV1=|GI2}T4v12o{t`j{J&Sa`;A+85f?b0AS01RR?&|>0B#mV8?^DDJ1@U;2qQ5Js?*Bl3z0fxb zJ|y_4AU|zRJI@HdAo!BtKMVegp!x?yDh=av(!jq8x_Cbaw7QQ3oG5gmpt`RFK0mWZ zy+wjGg3AT@bzaIh3PuHc1xJYGhH-}A9>KkW>OK_Y*9m=-pt>&wKEI>O`i}~#`%|Ew z5&AX3LxS%LekjOq*0R1&FesQM7$Rbj7Yoi7tPtcUWGQbHTr0RFXefl8xxwCCOAg0 zNN~C!|1B5l%@yP)O-a`aHVd{1ZWcUEa7b{QAU|}<`qv8HD0qwD9fEfY{z~vk!GnS? z2p$rATku1{PXyh(UsjCk7{Ls|Y{4ml(*#Qe=Lqt%tE|69aGl^Of&+rXf;$D(eM8i{ zOz0~G)qO(nuM?V|B&Gd(1s@W8RFIz#rTk^V*97^GFp&R+;8%kDmkh}F3G#!OJpY>@ zSSUDEkl)6ne6e7y;0i&08k6#fV7K6@g8Zl@<>v^h`--415&BBO?+Nk~m(*AH7lHQ* z{eU1pNlE$hf-eicD#(vUQvRvnSAy!kB>4QuBjw`+CkyhEi{$eQh&;cn6kH@&CCHB< zQod0zD%dMHC>RsmBe+-a+k%%1@6dyVwf zf;R}>EVy6rE((}!F)k} zXODb!-xs)8=xV_gf~y4i**)s_399?OptlRnPw-KGiQtuj-xK5)_$c2mc(33Cg8Y^p z<Kjt1b30(rNpKBIS1kfp2wlxeMGeT1|r(~ z3K8wRo##Jj-#2(ZfOavFY|k}B#Lo|MGwv6;z9R0EVT1AV5ATfgd?Mm|m58`b;P^y5 zzbC>!OdGC~D>@|01AXS+1^SS7qi5;MxwD{*BV!^1`y8D;TD&C2i&hUVE1 zoyA#>$IZ%y256*A9y_C_Ic1ebT-SOY%~G@rC;dn~zNc#?QhIs@|@e~GWEn8$48lZ0Z>0Ar)d4?oF$Uy=@iLF>{Ov+yWo&UK2E4B;JH9ufF@(= zigs+>9O>=vhJr4)cXSLzw>hPJxzwTDKGfd7Ihs)aNDf|fi&_>jFpaX#fh}A3{-wiE z_Yhx2EURu=U8dgv+lp85Fk!#uHVJx|Zt58_R>3q)*s#Q@tq{M|!&0ZVWIf8bVOdbm z75yze9y5~tTE1wwFjvqmd+r{7aR zhp=0lWv>Ygr@dm>%LI@1u=LvYx=^OQx!Ad#fqjN5=^xso{47Bp`?=kW{RLIhKbGIq zK|1|b!Y|in`o$7&`@I57p%?l%V+qUe(!>S$4hIY9ydPo=k)u+N&5IpzjCUf{H{r|_ZJNIT4h21 zSoU}?&1vt@I(>dgdlRrzkL}|U>{)ra z4)(e%W1>fY`$W$gR~}5VJxO{buSoKH3jFQ{pY6cyR@*QC%`w`w{PNne5wx{2KFXgE zJy zJ-(k}ZI&MI;U?#g?*&<#rFS#*I1a3hdH$ReLpDox1N5BZApc~{b1bAB2ghQkJ^H&V z$=>7W)D)`|A-C-D-^;ejU>ncO!u<>$uw=7jyvOYHdj>AvGNDJm$78qr{x->8FNFIn zV?fK^b4m6t+NQ5>X>Y#6-rGs`%z3zf2)VUc_IQum8DH*pLp`TWdz{Bse1A@|_e0p* zHcET>OsCUc<%nVIh8@~lMdd~RnLVR>k1E|7owRaZu@c$rKY8zY`Ut7trOcT*$d%FR8k6<9x ng0m4j?Qz)BC+yi<7f#H6Y#9O9D)QLw)Vpg3u9F=MOYi>xxYG{X literal 0 HcmV?d00001 diff --git a/build/For_stm32.bin b/build/For_stm32.bin new file mode 100755 index 0000000000000000000000000000000000000000..c0caf94316e640bef33b2fbd45d86c40d7416346 GIT binary patch literal 44412 zcmc${4SZC^^*=oK-rejb*uOT$4Fq!Yw)=d~+)W6Gzo*ah ze?FfFKC?6T%$YN1X3orYp31*)e!I;@c6P zM%n)_!rlK1t(C}oK9+y#f5GeHW6-p3=joGgDL?ksE6a?>^Wv*uef0mE_~QSwVI{qh2b$C!0<(m## zntriw_+D{q+}0Heo2J`p*lL_PPt_IZx3ZDq9-%&~fhm?wac8zKd*7iiEe>&?Zw5PT z6r<7PgM}zdrAF+fatXYgxP^_3+hUw;^a}Oj9{qMIuc&?H3mpe>CM zy?slSOYuv)YxJRU^7~bi&|Fp>>)_{H_GQqf54e-!1Y6IYC~azxksSxfJzeb_rWp-YtO%a!xf< zj&(o#sIb%4zNONs_{C>yo*MdMYh2t5;4s~9udsSvl&_a3$akaM-@8t$M$2xm&AYqR zC`~AtnYG(v^SlSx%mW{P#hQ#aJtbRYHdYP%(m7n-f1FC54GX-^Nj;Lx@&dt}YU1GT z{+7Pm-%@5{cF?lEr|JqN$bs@WWEGIUC+df6dDElA;(obrgIpum%hE@Q)vSOiZGL8t zuXmldN-wLU3wNrl@F%mS2H`qZusU#BmO`1TFqIWN5Xdd)4E~`tQMWp{1GTdJMFD0< zFHiX3E4@9TO-Rty8|oiZ=M`qw>qEL7ab41dOqXukv+^CX-j=QkS$Vtguyl!|kPysd<(-8&h8FVtI=Lx4ButodM}3wr#fCDeLx> z$}|TJ^4jdUK>W_hCGqvtT2`F;e0duBKicu*h*0=% zl%bZ}QEpxMnYKbPK7YgE6LRB8!%h|wCg!Y>TI(dS)g@_p7f)S3+EBk+-W}Wt{_{tV z3Q9Y7s-h*+tKX(8V)=<}B9rQ0JB&Uos*_(ktgruhSlVeQvMUD3SR~cI9G>ZPDWYW9 zs;mD=m|Bq)YXws-bsOZJoCl0uzP_INVCtn6uc8-5T+M~PzB25{Vagv>%nSC8YGE0T z4*NT5dZ8FL*&#uNG*@cF>~P+1nXwRIA_C?=i&b0>87ck$0-P z$-=~^X1w6+Jei<0cgD|-cYi-?ud}@6g}AuDmHECy880(qU&uzf&QRDiBXGxXmVayD zz5S9bgoG(KpO93c;FpHZpfqO8sSoz+TlKl-G5DQ+!>Q-mETT;@o1`{N@)srLEvea= z^3ku@okzbC@3c%BwbNjiBr`rsCRY;O^T!& z)A;WG>=M+KwHuJaLyP1znT=@=c7`Q6T|N@dl%JDB=m)`_;iWZ{)<9pA<+dWP9;?NH z#vGYs_~9N`wkhyd_DE3N<64WP`KHdq-fN#}qQzi#*JF=u5S3v|I?;d?o72*2zNydQTy09NVL7OJw$8R>i=M zW@aDG%G^DNa4Uv3ICDMehi~`1qv|YGw^w=Ho-e|v(Kq726nUMOjq48Dy*GoRu2qU> zN@7pV^ud6f%hYOlC@K^t2kc(rv7p56ndhx*-0hSCneqbfFVLIJz7Nt=#Cd4#ekF`r z3V%nxz5~4dZ1kK!antRpZi;CHD|qejKQr{;_QUQ`Woh05P%@p$@p>}qoMQr2o;*1n zJ4msEDQ~~N+i5;Ybug?xDc(65>zzXaV@_0g?f{mCbMSS7?{cOGtS2=Z{|RPz7kG^& zZ+*q2J3K96yEm~U4XxFnR?i1vt5+zQgW6I&XM!ibVmhG&GL`;O*f+yuFX*TIv)9?- zA7kt`IFnCp0(Rml)+(A<{{4YUIZYKl5D}hsb_RVj%=zY%k}S4Gr?C8m0Z61tn7p|p z1yT)Z8&@%%a2zcHruXf^XWJ~2uSsaLn(T^MFF>wYn??8AlC1detCsJTAbejnAvPg4 zA~qt{A=Z5_ndZQB9k9O&3Pq`qd7)KG5f!tJwMuDu0o@eHWL$YmgK2n4_K2U$D7OIR z79IqT;7KPck|?#VmxR{!0`Xebcuh_Z`DReAB<~2@a*hqqv-7~EpmK0pi;#mb&88T1>l9{ScI8X)JH{!GvLbj`T9yX$8c zf7&(U((_$EyY%zsuY<}PL|0S{;)F(xW*vGdtx*kP=FJd_F$>4W9lk-9iVeks6v1o= z3WbB({p-ZT6d#!?6oLX_9bPX_Yhh9vX8nCZ$E0Z|AZe2w2>*Y@j!B1(7fwj|zvaU+ z>D+PC1bsiAZc^uQ-2`LcxFP#6(QjB zwqnFZ9GIa>&5N=Y??PTrua*XUS_+%!C#N+E6X@CI-5R&>qtn>0#3DQw+PtYsoH<1v7Ch^H+IjMDik$HYv^%4&ZD^uC z^e-=Ap39s*-SmlIpD)wO_Rb8U(AXvzl_2eSSQQ`7@iw3qHaX+4VBZ**@X^_f`Pqfm z8r8*YB@OCyOReg%h()?Km)KYSEY?6!o|988DRGjn;KQ#(YgS;R)5`0fo4KVVb0W(X zLer-YIW5?2{q^eG1but(Xqb3T3TQPR4?D6@vL&?Uv%j-E1X|S}Kg&7STJ*%ifRk~aEQ z>nceTb#d!0!bkGcK$)Guv( zJanXa{j7BQYlll^ExlfKS_P}F%^A<^){6BQsl(xXuicw6EF*5TNBr<^aJJoV@e0t5 zE4@d~*Zc1%Emsnf2ZgNO01x> ztmpPKcCTH5*5F~I-9eWBQ1Gn$$2Oz+JAvPVXM06mxWJp~)fE+Zh#QTsgMd|fhYlO< zIia#GEQj>O<-IJgDu8w}kLNk;J1)fvnrm$1O4qB?t@++G@H7`ZNx?M5Va@1S7N0nZC^$zDVe=oEncS?L)^yZ!6q5k3F{hiEWl)d4x(B7Z*pzTaN zqqRCAS6@2Q`HKA4u(SrPE2LIF9QJsf;VIAs=OED9L!r3IFq_$QvQf_W#4DAZu51=4 zK2(7HxjSI@6d!s+U{>1YGqB6QaX9g=BN@IK^P0<=*=XZomX}T1?s%GgOj+9ea+}d~ z-&eZ7G9^y^MAd~p`AW3waQY;9H~unN*2!j^*~)?q^5*ILyK2vSPB|Nowppbo9afw! zOkHBn2v>unye0d#5nY=v{k}WWW;Z2wr~J^>VsHuFamrK9gj3nAk|eZ6Z}KaHYMydB z&ZpLhH&>NpWj?q6KzBq*?zR+_v`8haJMPj899ySjZP6mX!fIXscCUX?iCB!C+woi$ z%Nf@Ap@Z4~^c8cFq;7KRPbD?tNnklf`C|A$S6v$$Ee8)c#S^tocK)J&edfKbk|ZWeiAI$>&Di^pG>&d&eNpCLcjnyhoQ#5tZ1zu9IrY;xGT3_Y`2 zBvV|M5V3X{+OO*}TqtQt*0C-@1s~|c^qB{`l?e4C>mFV-vqd64I-i~{b_wSbIWNg= z(Mf*g5&zTE9p`KPue6EDRVBMye6|iJQi{lP~?;sp}Hksb)dI7#5E`{&Q!+DY3Ys zdF&T=@c4*$n#U|Pb0yDDozG)`>JAXU@e$i;97`Ub6PsIbrS50Z-yu@zKk9(po2;Ecvf}J>#KYpUYeD zv#<5bdcJ=9p$|~%mpF@LK2Ss0nHr_IwQml1GOQIgUd}VFowo5*ZB0Mq*XJ_UF8TUr zs6S!toBdD?62Dg1)K^l2nAT3a3X-_i=-%BePB?BfxHCOubtCHnfVB!YdhODe0_?9mHe#*4-_y6Fz=@}=toDpPtKJD}+8hH+1crs0)2J=`~;y?N84QUV0Pa-mk-JRfHd+^^_j+^_GNv7uT+f zJ2U%IXx>v!-6x3W2qEWrk5$YU1OEMmZ;-Z_=|%8#gfq|{3j(YOPR6=qgtyV`8J4E_ zyfkPbOwp(1jJw5s_u`d5nKnzXmACsVtg=qAcCr3+W|!sAB%a53UMkPi(xxsYT%?t| zoyzI7ay%XB{46|1E61NNbrMa+(@N)u;asiUG%EKc&-3&2XPs|{him2d^J%RdPk-3? zS~vrFmK-Ye0dlm|JDtA`rvh%}@HYY1Qg3wb3Y!3TaCj5oT54ZsLpTm_KZoxDTuVLI zxgpFlLRk zAkyouz^NK872J&emK1T)iWlxf&9qif8OS*21G#)HP^8U8&coE9qP6@>l3k*Dq8(uWJExduD-Lq$5le9Bhu@ zztrJ%?Cg5Q`YMEsjHs zF^Ew#Y%_3(0}$*%kSk-oap$M%mKvK}-u_O71G1Q_eyXl-w8>L)?!wb>b^dKO*_{JB zlais*oTF5ldS^M6a8wlI$pkq1eHx|XPRx0=A z%2GTlQA$5N%~dKXEzt~EwG$eI+{EqidmP9;839LCfNiIK(_nv%OeCxrp&{Qrf4Q@r&7Hq!{&Ep?!pLvy6MJvR?UjcNI=X7OBcZu@P}9 zwX-JHPHH3O&y{U@ujk4(jdo|EO@3$QqD-{O@9b+6Nj$YljJ1h)zPe3Wu{IS@n_Smw z)9@}M_#fCF0rI1@$TFZs@v#=weOrrY+-Qu7*;VbS{6>3djQpwE82MBC+CwV=wa3ca z$gRkK0F3wjf___&vF|^)s{>dV( z&#LTFeNv34{C=Kjh#LYRr6QvST*0b!a=G~nb>BO=6%Vg(ha|Hg7Zr@o{hc`Tm?Ob?{B+HV>+ayywKgJ%Sg(uSlSAl9kDdk+JLl!(|=rp-cHa*k+yK? z`feeIxc*VMqmg#KJhb~Q>u9w5h_yBh-d7U8OS@U#e}ehY9zTfYyE8l)jicRyEz|d} z@Nj#kJZffMX`EtF?X#?&9FAkf3BU-sii0eD6)uEsN$0wBgfR#s5l%tp{19P1f*;`| z!p8{v5Hb+vAUF`lAovhG2+YEub3m6}Bs%_%=RBk_tF74x{rU&PdWAjVApBc4P#NTH zLHrt?NjI@Hv61?`G5jPc8B>R3UpJ^!R4%Dj*>Wg#)*_s)L}gDW{TjOb``g1w$gRQi zf5IlDJ_BA$I6j8Ao#S2T^zRRab;!LB&u79``4n{T*Yw~Up}5H;3&m2No!2N%Uhre> zgyx1u^)}9)W$vA@+=@6S?Z?>+=cEZ2!_(crsKF%x&!H34<(#SRGu~TfYoku%@_g6i zerfo1m!`cE{Ar}=oQd)8Dn7&@0pn5M&rx6DHR>zi_2plqzFgGzc9?T~`v_3D4-|%9 zgThcwVaPQoq=LfppkT>KLHXGzZ@EVKL|#7r8s&8;{|KFBVtNbLJF!2~owpt~+`)3T z{3_O@OplQB3ThYx?+m6K_ZMuSUDEC=*l_HEL#pC2ync9mMEab^EX}@>=ciTi*q^qW z$4AmW=P|R}SMhv%6_5S)-8?>G|D4CH$iABA7geoZwqde=?}j4(vPVC!*-LgJSY4K^ z{q?y`+z#|-SW8;_p=9;>Gi);jWEtXk1bG`c%dUcmYhT*&Dk>3N{_6saiu` zHQW7y&6x8bTKjzGZVuT7h%RR(AiwDRoI@T5gl2CwVB0$FKcaG*0khN`u(TE?u?5ihY$O~bdh>V>rPc6oTaK*9vn?Xx_f*e+!nCFmZ*L)x{Yl74 zLfN^zZ1JH)U>%H=jh|iMrSe3ts|RV^cu7eAu7~>p#OTm|K(s7PLQWzmjg4^;56s77 zlnk@z-1e(p`u$Na(P-#7M{C3YUN*xLW(pNG8{B8AaWf`$1_XOYxaND3`{_zy!nXaD z)7wsPdph=zBzG3(4E%Vwp3tXRoKWAeuDDd!KIx?OC)Jt@>Rg z%$gqA2a8cX{2uG2`hwDeG7V}jFD=fP-K)K&OZYvHlV>t@ze9`opP-o$fZp|e6z zHsfAzd@!EM+J$-p&KT8lR;i$PqmI{&fQo=t%Yy+~7&X2w0wQrpDj?s92AUH9(Q!x; zAhV-SH75e1=a6_nN}`@-J-5wAJ6?)LJ6=S10pU4>XAyQqX|IAjI0VMbSGFU)G<`rj zr2bY|%4*RH!FII26{CB-&1Telxea>M9T&Cs*S#EdEsfHih?RubMQ65y`&iD{t=DfI zx3zHV_^lJR7Hu81HE-+at@&FEwvO4l#U{Pj+mY7mfc`7JC@LeNhd7j9`R9-g0s0(2 zpCazFLR~)3(R~GG=IT-P<%$UV!7jfvYV?zAWPU?IgWk}Fwl^C44bi^kSp-!QJBu)$;>Uq7Lts6p4} zFVS7xFmWumXZ(Opm+f0z+IcBo+U=pcV(f*UiQKLc?f6Y3cCKS0*QNT-cg7}TsnIQY zes6a{f2;Gv+m3o@%ymj_gf$xvMLRY|$X>`w$d;H`nh0FtN5eh_T$9ZS{9_eTrK{4Q zJlw05T7mi|l8*Lc=xC|RR8kaH`X37Fyql?#B8hNT2JH$L)y>3q; zESt4aZ!?2b)BF-(k4eJ%dqGa+JNEj#%wg z&|U**81`6bjZ=?+Ggdzs+%a&ct2f%J<#=GaBi?2Mcyo1`W4-aa-e|``g#8Hn5MJrs zMSWtV{@=cDA}n(T%&R516QthMcpJ%2%di{p6RLk6o#L&ymw|jcGd)>esomkCStWoc z@LOcW%9KPYF?riin|WJ#`)jK#+fu+)>bA6c!;6B_-Mg<@R4RL4#L56m5#}(Be0lq> zd3q{0FRnf=N5rhYM=fj~6yyAEaQj_^J9}d?>f`5ESKU5Q8G_#abu`kkw&tGipQt>sR47_t6egdjIuyU3NjXv73tp|FkugZ51&Q{+Co&XHTdi3YY1vrCj?-BC$2Id1EUvTE6@a$aG zuB1)Cdlm>%5i{P5P>t{-gzX5O2(xcs#(IR=vyylXA9T-xu0VBt*zIdBDN9@9g8xdI zuf#2a%Ud|Fw{Xs13OoC6E5wUGpU`*zbF2H-vZ*tPLP6K9kRb$*!9Ecjk3|TD$HrRv zyY5KGzUX++u=9H(jfR$H_B`O`AlP_aKM0R4#dvnt?jPgM^bem2k26=I&)J;imcSLW z4*_O2f+swf<6jJ?bAD6YnQI2)R``xEwa0?iNUk(r630nEo*8*^IG#Vp;W-h{w}xr1 z(0P=fH*uF8MfwQtT_cEl5a|5MnCR#`Uy}Yrc2zpB(plAqK<8dM@9snTuLx^nt)ATd zBX^efM`fwrdgr=J@vlAz%Zy-+bd2bFpuD(-Qkh-FH6r4{T`O-Z5XW`VuhdoO|5Ods2)3Ky4;Sg^Pz8C>>^wi|s)upMad4|>8xL(c($RvPJd})f z98f1e`n_3I{-Q^B`{AK(5dhnxHX}uM`_I8AF4|G8=J^S}7;y-EMLRr5S!*e^04Wbo zeFv#sJas$a)l&IcNKx&jh^e*`#MU}JQd5zdiq=m>n?Ltwnd~)_H&oRWZP;Bi#eHTi zd|CsO-3E;3PreW*YSQ@AE=j(r%;MiQysj?V@hYD3{1ay;tbupF@5}H6$V5$-uNgOV zF)1C#M}0Jx(y@G0zxze5yP#~$%u%JiSSM&r%ZEJ1+eboLMj*68QfMCC5uiDDQ%wr^ zOW~u#&Kqm3$RiJ=NXNpi1oxSZQUQEcKqK3I+Jkp>ev(!8Y`0`TW6VU0OzwE_KH>{@ zm}I5T=3&CvvzQE!ERbB}k!&DMaz(O3GPMPP_p~lepS-N{$CbIV53Sa%rJDOZ6mI(H0X{x$fy;eCGsqQP9K)5k zFTydDW22V2M|i5;BYdB#?_jn-KZM0jRK%`HWO?K1p3Z~amoCJ0r@40S&uSDVKDYm^ za3uWY{@#v1Mui(*-hVOt-Ley0pE}`*bbP1NJ?lf9+us89E9;k{pF>hir^?C#-rHsx zVedAt40?pgi)>=IbOCqQo)Yw>O?~H!$ybdeasSTSRJGN}T2R3;B7&ol&t4>$a`S_FQ zn%8N>hhYy{+ey}WVRCPfMt&$DD?3Mk%8pe-fcZ}JWOMR2#$n1wX|ZuIKr*P$N5T6A zeQr;td4XB>PxNCXO!J~|KKLNlv@VjY)7g#dmZV2v?d`jh=5i0&ZzrD@9oAdub)?^s z&c$__4AHS1TzR9*`z1CL_6JR32X!t%-tVJJuo}#-jC4G#F22Ti(cCGBXybJ^#_OJM zjMsd$VIC-zMU{Wug|uMp?I?|Y2WvB>Tv1x1dpo8^=VAS()TC%}P0^!su)gl{V?KAh z)q5L_8B&LPwY4xQkV54ENCM%zhy}1bk#;&D@!}s9@ct*Y-l6 z!7iPNUD}1)&qQCkTgVye8-l$R`wZTF;A4$3@6**uF8aor?8JRCLhB{TNZ*>dA8A@I z$^J|09l3u`hVL4yPs3Yvf-GUg9#t7E7n*Mx_iwu@|CgOt<{O)+RG>#!48Luw z@eq|UHVLu-=-eLdnf&7f`(vsBo~AFW7HH{|{-tVQT0O;0(T;ObAx{j5x#Z2FlMN`H z(Sx^A@-79j(o|3#xAwrM9>|r?g|#{ie6NaPov}9SNJ~*7(7Euw&>AD|;pQ;SHq(do zLDbTyL!RXjX<4Bt@O+nG10g&k>i;+j-;O4uoPzfu;TKpG?N}8p#2cfJM4ly*S8R+*M z3Fn%EsIi&G0;A0BO|*_^|9yCSmhePnkV@^9N|`bqwkf7uA2A;4v%#Z{&@hFfG>?Jr z>QaFG8UE61Jf!D+-T{70kRu}nj5n=4#-@1e@lFM|njQl@ZYY)DIgPtfx}nmc{9csD z86~z}(Ru`X60^BsAkMu49AsALV=WSMbm*bqptaz|!W=YD zXf1_i!b=zex>yPL`|v&hMchwvKf8lZy5}!FzW)i#$|qnw98ti|C)SXszm<(+@xuR` z|JzaSf7tq&MlXVA{Y;FTuWn|7Un+SR_d)Owb^B(ln~8T$T1ETL{fYjP^CixD=S>0g zN#}W+t=?%3xXu?%sCVWDG+U-4=%fA1e>N@Z8+dT3vGr`KKu2)xmJ_wv2(7$DyV!~;kLKP~(L5UlC`?*Vd;TZdAOfZPelcLBM} z9S6vZ;oEu5&mpHAIkzKc9@jEO%*%34`HAqXnMSg@rfhJg255xx19uyRo6BZRR8tt< z=(3GeQ>;P}v|Yc<*UO)T2`eQ)=S)XwA>FV7%Zl}QGM7b0rzHQ4sLLBBoSSCmAWsPs z)rqB6Q2RJM4t2u9yYk99$6i&Z4Rkau*fpR|`xSK#cN@`Ces=N?MV;64Ix`2o~2ch1^za zH5&rgV>f{mn#Dl0x2x{LnfBn z?$%MQ4JHN8;Axw5_vL|yt6}mTJ2&5#XL_sO$HF zBwt1H9x_U>Zo%5D&Kp%Pj>>zIT{rp(DK~$+X=Fjes67eb{GBeHeN=tklcS%=-%hYN z!2Z~EI2`FX+l~9xF$4I=+D$fi$vYaOmKeyxZyNu#2Sy=X6wqw>xm+^96SvkubAq+5 zEo|j>aS?WLNC)&Tve!|cjX|GTd+2v;&p%)vAsJ#5G#O$=#64jRMSfBb{bu(3C7h&< zkS!)@WP#^cnaJ7>eH^0nL62O%Q#0 zS*A35y&s-HcuxnmQwcUtK^fB(1|L^qYJJUOm=a0I9#4kNnNyo}tlyjOvWFt^AYnvBTi!Ni8@(;R-e@nV zAI14N-uV&6^M8f53;Z47MK|ZVKkZ&uW@C!8P9_dgsAT?_WKSr-W*}J!03= zSfygn8gHVDVD-RcRrNgeCSdiR+NC#v`|k#Lp5lw;)hwkv4d$2^!yf<>B@I@C+NL4B z1$R=cU@EB0^SV&OJkE=~-Gf>MuiNWfDok>rNy3*G zaE}mz^?Nd(Q+Q*%uf*JduzVss=&&lU5*N+)rsC@(`hd6`qdga}x#A*mIbaKi2As=n zN}T9igwv@y#kxYVLASh)?*${wNilkkg*R~y{LUR7cw~o|&AI4{u;d+vxs!msjP?+V z8Q**0b1EUgtXU!A+_6yUFV`B@AcOlM&}T#FM|iDCi(H5W$+d`CY2Og7-B?3A5ugQI zFNW{J`JwI~S+0m0g`YU)b8LOpdTU6mx3p0dqx6^CyTWTFkC*&1wWi%#tbG~sQa*|)B^CXOQn>xIFS7G-bu1hbe75=z z&8L^9w)@Pn+E=82HqAg_EeAIX6M0<%)n#QN=-%3i!;13??!G1O$>rL41HUAf-r?SR zynnjjNKI||jyMJ*o{Eu?&<|K!AqmF0yXf%QxM^^*+02R}cp zEq}UjBrUDw3F(G_HV-%+R;*a-+8rZuf;*O_B9;PL4MR}_)iekaK(dhnF4i_vt>jn8 zYo*fE>U9HaWy*+7s?~%Z{L=-0+HhzO+DOm{1G0Ef%XbEug1$r4zy2a^wmrx>#i_(| zE?kAt5~V8i`wGRXALgN!EJ6M-&p*S32Ql+(!Zyf~RmjIzYy9{|2cHWG-u-Q?JmYYD zzU`C_@Az)pPha;LKB-(WnDB<)d25R(e&$K=R+ZLb77X)#>D}Cq)8MeWzVu{=GQ39t zb++g#k9r1$bY5$ zpEP15-Xi2}$*&@)M%6yaw1MEFE5GW)Fxs}1>Y6qHyQPw#8uqk)?3T(yVXfZ|1xJ)R zX?GEwp5FtOn*Ulbvuuvn+RoS<&m6C#-H-ScyONmljpYJM^h&8x8X#Ho%fG4J9j$$IeYeS`;@PJ_R3!2yOhK=iUVR_D7x ze8(#4$Xdj4e|7f2#a-j#1D*Kt=$2pyw^`_&Dru; z3ttG%ig6}^cL5$%-kMVIWLH!v2m9xnXaTj@XqE$2)pZA^mCaj0?V7iQDbIrbE$#&? zXvMq+7iwG1I~WZU$WqA9%``1YFG)pk+B-$ zfLGm*H{>jFr8EB|knPUGKJ8yPJg9j)U%pGGJyXaX#CyQM&Jx&-_T^&CCkJu+wt{Rb znM){!KD%Uih~<72PS8eUHSt&!jgw)|;5)`yw5}lPkB!8s5Z5<-%(1F0jrT^{lHJ}S zjNVX`xzC-&dt@BSq@c{S^Banua$dk_9}4LU;scAnQFkbeFYsx*wnVI-#{9c+n=~{qi}$skx8r{zI=PgOF^!aXXq75}`nMW@2B7GTu1GEEV^JULc|`u*id-^eZqeO_%_n&zrp>T0P? zdv@tuBiG4XpW#`ovMs~!>ak_>JS6=Zt;bP+ULP&=$jvX%D{&#xy#y;(5x%cN?>Hnt?+~DO2+%tO=pBOf0zw-Ce9E9R z8=J1{UooZyj0Mwh%Ab#(ohoYUK`Ku8cYEKwupwnwDYHKVFPZL+&gf9grDGQa7w+-d zzU~W(@ld+^F7J^G8!Y85j_fyDnd$!4}pQpK6eoCC#ojIw&HIU(r4+RWAkoE+kD z)q5OB*%d{4hU@#3FPO(;?Gp-M0LSbp#yU+p)1tr)GdE&qm&7#JCd`&!^v22KV|`cY zJ#d<&PK&KOg{PZBxbfs1@5NUOhQ-=Z(BF=| z&apvl#>WMQ5Rc&hY(I}iSZ`7|)Z@}tt$I(iBO_`8N5?KmX^CYgzIW1*2p>-bFWzPE zB|S@%k1mY9ia>U3HbvxTNk8ntw71-W(D&^udL|op2flttRBQ1*BT?lxP>jtQl%f1^ zEZDT9jpj(Nr5K!4(vEg+<~`WrY%cw?eMsk(H^s;hFzEI9n{WpQv$y& zJFadnw6{Cb&Mr%I9Yy-{W!Sq$Fy%WngnMTV%SFGm`$w1q&-CF+Im9Li+Ams!jv?2RYX&F}^D!*^^m{LMC7p8-FV=CsR=fsLTOh4?6{ zxSwbvP5UBp>iTl*&kV@%Pc;U9(wCEVc0dk8&Vzk9QqGEgYWRMLG2qj3aDuAfZQ%9b z8zaU*bu7muJ##q+nxrvM70W4<&JM_7$oXC@=ZKVZUw=K&P>q4_XgTeU)fEGB7;?({ za;lygkmFxy49x7ynRj+T4nvN!FUOTLpryq16fH;bS3PsNrR{7)Qs9PI4y!sF%lUl8 zfi|{+DIf9qYBXb{axt>wjDh?ZF1Q^?#T*|P*++lghpOMw-$up1B0eyzuLk6;ACL!Y zU|=xvAXf@o{h_*n=i!OuV_|&29Lw`peW-4Z4!iQdJx~S z9>li*e@HYjx^dVs?(aSl+j-v$`Dj1Hs0|9(mSHbgwZmx%ETbJ2>7gs8wfn~pT{3h< z4v#aJ(B3JSQ-gMVO~SEi|3$~TVS$Bwolw*2J@?E^Twz;w^g<%mu*4;6zF^ADsQJ6G z9rvH8c|2;qynk;B%_*(Lj8#+T%pB@SaMgM~2@AP-_>v9Pk`}01wyC)keYd_4!Qvs` zwIWxGKTS}46^X8Ays)*bK8jpEbH+)5&z9}SOpXiC>>Z9%7R}Yn;7!+{5JFj2B`Be3 zG{Qum#%_dEu~fL3AhEGqmjas|>Sk2`z4&HMmd@4k(=?{|Jd*2jX>BBv0+lh0+O*F= zU#xnTepe4EqZ$U&ctC1tj9L#p?eiJ*0NJo&eSnz-J(ka-@i;@0-a0gpL-Z^}^D;ecOwNKTjY%IpN6}f>t%z2- z)_&fa>$`NaCDxjuX#aIxEY_M@XpEqX{@!3&Ty0-U{r$*Q{k@?O_deG9w07Igxb14k z&Rx6j-q0i7@)lRJg!5T)dv1$P|Gt+}V_fS!CEk%OqOQz)^a4xW;jp=!o_j)nHyS6- zQAb)O#h`zgl`H1tIILGPILFVCXO(5V{kZL=18MtW_I+1Q!< z8cduy%jOY^s7)LEf^CPxRr zFFB}v8@(@~ZAU#?u9*K=K&SNx=U(dpDo1UxxkTW>+A#I)z}T`omY1~qOYT@SxBtE8 zUl^ay&Mlj(=FY*p6{Kq=n>m%-7Ey1*33+P!1Fwn~{gqpswtyBxpW)BLV{vvY&Wyzw zv3PJSPLIV?+i!a{!FF3%u+0jKwz9BfD-G*xa#(LG3CG!-VS~*PHrj3tlfKFCVTxhT zni8{7GtnVc55*k-w+li)O=zsaH*n&0^y{h?S|l;2MH2A!oM{BHKu)r*v0B3GFm`HW zcmqTyr)j6TsYXcW$12OBZ=bYd?G<5Vh8GNQSrN_4cY$l3};|L5*_h^z1|^~IbmJq{SN<0 zp?F`Le;xEHj63$#Zn@yz&v6Ife?(@ogtUMc1 z#crltd9v}%kV;$nWCZ6BI*%Be3^Bc5SD?e0Nf)Gc8xM)4Jz=pFR!s2LcWy!7ngo{zp2hKCZT zcQ`Py^iX(wjNWUUUK8lmgO(fN&gd)Q(F5q^gI+xNGmT3MJc|`XKX(8pb7GtvL0>syePu@9&+PB}ndp1@8-3pk4w?`SNB$PRbpX9vV|^uQeTBEf zXf(fw91GtNqxeVk{u}+h|9jq72hpw%L2Wa_6Oot0`2#2x#3&YO6yb|O6c0sq^!NVu zfVH$fJS@iJ&pE|Sptu**su1prtp7&u(|8^kmrUaczYyyGhRDhR{l6UjUp=7z7xDi0 zfT|x9ixHfWyJPdh&yMi^$9e{D19UzCn(Dk;yPoNJqib_ddCM#lzAl2@+tg!kF-d^8 zHFnjs&14(#?e97d|DIXXvHuePSPWlUdYS%a&?oKSO8Sp-`ckDv-?cP8;lC^4ij|Q5 zOO7PYk=kUCljS7u_O9nIHg!F6acF42H%BhU>h`1P1aF)7A+Nm!H^trJ`83xc~B-!~(@&~X=0 zaaFp#b(NdEeYjCACF#{CO4m0eY{LpuDH zh5lsUT}5>FMqlJQ%(M{W?{2&R-@Qqt8IE@ju!7<)f}Jk5XELZqS9-$?VC2_YJ@Vtk>T`MSdnSoZv| z?4cKY?f7NBHcETGrnIM((sRC~^qhZD+VL5s9iP%~;ok{jJw<8j-zaT4L1{~X((D8J zEqssPQ<7{LL($&Crk|njg{_ucaXY;!sJ&&>*Z&DolC{xXS8+rQ@Pg^XPq`-k`N(Db zyesfiuZe$p0KVl4{ETbjA02?NMh5aT^qTlD4Zsf#z$aNVQ3<@IMsHR1wRc-YD$`o~ zF2}}vID1haYx6e4HS1V2ppI7t)FEuW>6-YS0r*c`fgg8G{L%sV4-denHWXc>4TS^n z?;U_IY)!f*{fq(lw{d(y#ycI}^lPj(e`qYjYBL?H4eXyQE(YDPSys9X{;dqRoc2vs zz8N~}2K);Ax16s=>~Pi^?-FB$tUpYIx`ur(gyTz|I>9I=;k?rU; z`!%@OcwqUmblz*}yw{e+dW~XjZF;dP2W!)dRl`GhX#c|AeSBRSf|Y7-6~nhiq8)ej zO0uQh<1mt)r96>Vp7KPj9{xGHP?l-3Ut2>|^2V9d&F8t=KhJ%9eZ`l;Au-Z*;uBX( z{gB>#{Jj|J`5kB#EXwj=v}Eu#TJqUd{i%(AB9{X}N(fT_I#^=BVcS?m9t_`>W%MuL4{mA9lj(G7#q-H%akF6Gy=eDxp&&7E zJ^mgcR15dKGCe< z43C7GQ)d!(2X3#9#Gp^~95eqbFkJpT+*cy`B)(?t5(5IfX?~CI9aJtFCLajv<;F14 ze}#S@*c*n7ys5wsoW7e3{kby^BSG)B8aY3=_G)d3hxIAvzIYwg`VYWZUORn%8y;px zNPi(byF|Ml>vJ656F1;51QFhx9?m1M?`ovegRN(_n#+V6q8&GN)@2>Q>1%4h>UBZR z^6`y+#ITOEYVpEtcBF|?`#OniYAFdq`#M$MFsd_3b;&*%4ir;PM12+BfFxddepO9@8wlZ+8bX#DDO$%0Y zx${N+&B9JdHni8iKKNd5VYA44Xhkoi8+#ww0nnqKu5VC#_X=t=`>0L5Ozj3x)5f;+ z8`OMFHH|nq%L00zcw2)0G(x)I!@}#|(Ou}leyp&??fmZ+{cIoo-I2laPWcnnu?zZ% z%EsInsFAm;6MfPB!Z?Sbt6`YAajl6`%YF6E>rYDdN7RXh_!_tEbmcP0C<{C&(%7>4 z@)kE_dJASi-#fknM!8zf10NOLueS;2^i!g}plUpa+|{$I`4d&=FAnWp=2BSI-YQ|# zaV@=iZ`B7Op&zrL=PP^%eR0{2s=do37w|X-4EcWu5$&XItMAAKgT0D=UAuiOIpot# ze6dYu6mB$Jf9_PYW3Wo!OP@2{eEbh>47V$JUU}Kz_U#W2(&VT7T;MgpTLNL!p1Jn}n)UxGLL2Fpp#vGP;1%z6&1A z&0XKdXQbm#QH?{9a~J~M(bwc-S}58f@xRpcW+2~dow>E@rDbVXa9SA3jFmJ>1N&-Z zC_M%juYhNSl4Ee|6>w81Hg~k%9;MU9W*&`Gv22Ka12U?2FnqtEeA56qnzJj?aZi+u zxd|T>zbr>*{R8D_+_%aRbQs8y9&!|i6@t8&1$#W+{il(>wTt?G@F{D*Y%J~;wg@}- zLXy(AI0i`4EB%tRCuHfzz7g0o#&da#u_|2Aa}6Q;8mYc=4OR)PQqNNClIlOBxC&mZ z6Zf>~;w8?<$DJfu;Zu>0uOhozjo*;0$6}J@hh#PPOV-3|)+&v<>l%`k(JxseW0Ez7 z#}@O%fGsv&mMg~V21v#wycNsx&O$PVUPCf2OTd+qaajVclngEbb9eO3x2q%|kxKxL zza%^F-)2tmIqyGup{}ybw?$oIB`fhpr0%u8hu_84gq2&=Mb@&FwfCncz31PjE(L~J zOjuQmGDjwq@z_6MBaa;u-s3TwkgytG##-%M&hqKILjL<5mwHx-Eq?Lj{mzyxs}d?s zqx8|rga_)?6`*Gj%N`(zbM8hS*E-+h@zDth4<=L#6Xq{AK8%}YCKlE@<}co=8jqOp zx10nk!?)6(TI@(*IDwsBjMaHn=DkG6KcVbFir-G%h*(tCiSIp_x#GAv;fI+kj$W9y zs*K0Al^c0nH}^drJLcA?Rx86__{d=g)K%b15NlMMmC78MP@~#;%8%4Yo^l|S%To-g z>v*chR-=yMDFLZGYu1Wm7i6ghe>+XE*QoihrV9BfLG-0gZ2xiUKJ|Vkx)Lg=joZZe zi?ufFSe$w9PI%PnAqlncvG&ictrFmqHW8;@c9_P^*R+MsOZJ!5)I!=T9>5#D%L7$d z*QN*Q_a6Q`EO1Cowd5?;cJm#$M`C#k@J18u)~i*|y*i${U)^=DrUO)~p?ggnwn()u z(Q+56EGe`|kMEL1JHCX@a%<3bU#bp&aRW4d*QuAEdfhJ1Q!UHtzcjGN5Ofn8aLT8@ zJf&B2LxeSx>U~|SwOIAU=oYEFmT0wJuZEUrwT@Qb!kPb9;iR@yfl7YCIet1oTBUz+ zo@{}hh18v$;lid(w2wm@(Y``rtbY(IO~T%^uVP&6P5z738|gR}&1l4}qMV2`qh7Xo z=fOfw{@RrHag?52{F&b43Uf^_xw{Z0)~gfe?8c6@yDEgQ!9_b}M6ZN?MCaL+#N)H* z`M=_JOgHoCDy@W8`mHdH(~FH{4c~%Yx2jQs_v^$$qP8n~SM#naD`qD_EQh2Y_H=BF zejO$YI{8kxmM41Zmb*R2mT&S%_x;7=x-YS!?mlSfkxL z1nZR6j=pwYuNDHHGN6?j_gddpd3E)>z54pkz4#`~_Nr=Q{qE{(jYoHc<$eU)9`#L3 z7lYnGHWq)kr7_ljPaV17;yt>{udr)a4vOAkr4~nmcb3=YdLO}5ZF9{+*o^Q# zf@!JEWpQPA?!uW-bZqc8s)LU>T5uHtPyLPF{pb_v_*i=uoTY=4FP67T@A01 z%F`9vdueWW_oUEoOa4s(sfTa=r; zc9(gU<+gp!jKjN}ro+NWe4{W(Z^ZxAJKS|0yr0K3(yjWe>U7se@aptD0-sf9l~n12 zk10F6IU0$=0^^`}qkRXZrQ%W>`J$tqKUJsC8skXzUgxsI8+tQtm38)%St+w$98gnS z5P4M}AWv_Hd{<4Oy5`QRh9_<6X8!B+yp8&f{_pk86)Q_nUs72<+U0D~+dy^RV??zm z{d$P$lpahbPvabLeYeyx5QB1R1#8kVI0I#pw3U1%U+m3x$77eT2Hw#!3?8+{jN`$n_cy;jh@}Z;) zf1|O^1B<11=u&zIGR0{O4qfWNdy*+mDG1M4@=Ejwn76kSYIAuDQfKxH1(SjzhvHq0 z*cS@uErA1Vet1^bJBPuh{$tqGhw|Igdgq{6oPu}_;7N#mu;Rx9uVDhcuLBQOUKiE! zv^O4B);M?%!&73a;fg$3c{EN0hk*%<>L*D*;rVad(C=4I@AG2Klf3`%4yzsnz1k8O zjNhcd3VK(lLa<9e#2W{A?@xl?8@)5f?DiiHf|WECcsjhHNPg$=BCQYsw-aW&W8Izj z+le?s$8e1t*BHaaJ6shyj!SP7O7N{ET>NblPS?V5EiqiY|5IV?!v)=&IPP;XT$~NS zgJ3QS4r&({Qrd660cre2Ii9{LI0$PIr5)y*k*2pB2jh1#yy>xmaVzn<=o5U$_z{0v z6MddPt>RBBqX+rZ|5e)ez%_N9{ok7#Ap9#RYAI5@5D+v9QM4**4N16)+F_;c=d5iL zP@7;|Bh-y`>kMjJY5VrYYBwwEW~JTMx>f^rHA7$R?6&r8*WSqX4s?BuvwE%6nt+f< zApE}1NkF@GpWplY{or$Q&pr1!=bk^$J44q)`2DE|Tmkl3h_t3Xv@b84$K^FzsWod$SK&%tt$BMrVXSNmN zPSi@@0v^2Sp0^yH5Kq7=b?#hz&&l#Scf|78wpk3RpM}e5NK0Kl=4*5a)B%0@33@d)4cb})qYhO>9d@XQI_ywIsL{44 zb+~mNpZiWkYltkC(y0f{Sqt>zrjm@xxyveF;?qw*JqckJ!V-iB5H@oh_#)e2j%~Ny z1PZv@N-^>z7Ku%{q!%LkO>>W{VC5k7$PQcX^{vZ|SA?7dlM(Vl+vqG0)FjfQ-<63ojP&Qo zoZn=dvrI7Twj|mty5+LA(*S!$V>(4xR7&VfbfxNIJaqB_oWUpS=hcl%d z?+RUl=Ra-bHhTKf;EHUz9tG5RK&5#h3-?fo+y;(kob1re@qA=kYHMV$zoy;?rTHH8 zz#u)rzK9Y1yqi!jN1(1dA=Au>-O9+D>IN)U*2l^(& z=j`O*p~E+c$IJx%9DWe|6uxz#N~odpT2TGP*ri0jq)u7D>{GC9KGwn zooV#$V}<64yY+ky_35k7gPK}S=jQ1ro&zmkLz-g7HPDsH8>P}SqEvc%lsZp|Uh|?< zIy*|GiJB9YzT*~3oa3dpEzuegW29~0^mK%aNu53ky&vO?&&tZW4Ph+8 z1cVHZu<33+m=HgRb)az8@O4 zLI0ZTgMl7nO7xnDYdzAj0_bzB*alC<`}_9jw-I;ibE+F{*`{3<9yb0KiVu+p*&*E6TMx*L3 zRkenCdn@{VwHby}y+#3N?s!6H=>n7Yt@1>4OJ^+2Ff6luXiGHF4EzQ{hDl{PXk)r@ zD@j6Nqn)IN4YefQk-u!Oae_P!-?0Q?Il>AA*p=Ywas44@5SV1H2^!fX zGmGAU>>RUGlta4kSp%>Q^4bZU_&jV%L|`ym`;rEj)ty^l=y?$HXEM$O zQp3!6~ZWj9%+D@ED8I90kEDe3J~q=mTu&d_|^ zt!`T<1_OT$VFyNP8XH?0_5$r(p2dVlv^LxqfY-8N9wH?|Ik;@ALKMLY+zp}JJ{$qC;HHgv`mCY5QxSlq5m?&kV|uD+$UR8k0+uJ z$=dV1H(=*GIzEI62L@@BPqvbM>|4i!R#_P+V_+x)&-c4UjNAn1nz8n|sRdcAo@uCO zJga9GYn|gbJxd*JLuiObBQ*qxxOyLJpDNlfame}Q5cLZmIS8upNv;V33ZS};@nbi@Vv#kbR7SA0=aE^@H^13wCNxS^D)hg7W-y_~qpKG2wZ>i5^)JG%V zaHX@f7aNz7_2k++y*O9b#h{F_Xjg)ZFAgZAe|g(InS2ad7HccKcZcmhi^1Mxfu+rc z|5h~7{A3M2rkuRpKijZ6lkKQQZ6Z+p__=(+_|9aEEf;OOAe&tL{N`2;Z;V43+}Pa> z#cqLz?!{7hMU>KGWVsWp{aV2r=_zXC7}PJm{Mpspi~;OPWu8mHOxtug9)_cq!kA0C>)0frqGpnTp-EEx$aB)h_M{7l0zZ|3c z%5zcsrSfWep|}JPSCkwxr>(5j)tr4oTU$_*3EA!MhDA$3%>=|YhrLcNX}@zW^V!}Y zJu7+O3!L-kCMLpX!fNbSY{%ZOPSWI0@$z@22V?a`x&e8uE+|W8_-nUt)6MeB!Cd`C z-E3K$Hm6gqZ44HHdz|eZhh3O_Pc|&- zndw2nAWr*h*V<|6CyJ*1NiM|oknvn+;R4tJ%uOuPoG@dbZ=G9{mzaM^aW2p-%Y2|i ziNSkv^}mOOusbhZ|RWrZbE?naGS=Zk_3Ev!+LzbGt=rt9p6;~3nC>t ze6bi$K}rkqiTb(m1$$5I16Nw$=4U2Y9E&44BENH)hUs1xcE4O1^#@!HJJ0Og1NKOA^!h$NWeJ-N0%B_8^;nNmEyM1r`=ey`BUf9db*$GZz8qK>djxRLYE z((u|6sZ=tcgeFK0?1w$W3y$iVP{!ZwyNzF*{zbh8n#PmN5hx3wo*d%u<_oWPo`ud; z7cfZJ_?%JY;U?=LZ9v=u)|k+~CR>NRcB-WI&*CZ9w}(<){A9Fdc3$-tz$iL_Ipx58 zu~0o6_}j3)Jw{UZ%oJg7cxY+=D(zn5B+nk4O?;t?ldCrhzTvcFtT=esR2=73`)h#1 z-yRZuTMhBx&Jty{|7oP$GZc$EHDFX;bspyxnEl0Wu8EUM@1symXV%XgCJqM{F)hP^ zqT#r#lRXbN{KvA&V7`Hy#`!ihOtZxL!m--=Iv3UZ%piI-2KpR@obSE{$X-EzRs@7NKot29E@joQ5)kPm7eL zNbwBDNw5{^UyZnoxMJNCG>Zoum07eK%=L_EhzqHDx!rq$rA@B|6PoBmn)9VLz-xQ) z9ajX@G6^M>A@{Ebw@G3{#g)|)4~Ig%iJ>$B^BdO3VW--^7|(w?$T!iO?nAs8akbxw z*seifH|lxS$u*x!|7|D~y5G$2+h;uKyW~8b(HgqpTUvI~_jhMSe_w5raaN~+U2D4F zks-0j3%&4zLif{xDVUnX-z5~@)(K4Eig}^$TwS_ZfY+I;vIcWQHTegb4ByrH3Eqf= z*ZDB~#q>XRh@T@AE$Xj1MCCjq;2iN0uJEcy00n|ncOvIk#lIg+Z<<{7>>X8A#pVlD z?S3JpP$o$b&i4xHoMAqIG*!xMIljAG6%QIFbgvXlW`2HKDA?O>Cm160L73iNO1aq()NS4MoTcC<%Fe_*$W3pNExm z-ZdpT?b4q31cL0NeHDuzzWh$%@5OPQLqIO=->c#-mup-2ok%OVCi~3hJm` z2^v2i-$GA%gwWWX$VQG~2 zT5cd!wul-n$#4_+NeXRyt;z-op*a1-on{{Y)G zfISogtzm;~4a>u764jby&W81n0mrYO(H|L<9cRpw%1@JC!WiGAl*OJ>>keCH`(F44 zRDm{j1`7w(7;-gnD|?%pt1=V-UTkF|a0@=T~uJ zmiK5dVFl9lLMW#1ZDUGDM4!PltdH6))v0dMtcvZ=U)qL0t3k9v% zuLBkLHIP*-Rn$6#3f3u9pr$HVry%+n1FHck(!K8gf=^nK9vdsS*-d3*I`RE$Zu1TY zQXqlP7cB3hcYRB4wQn;n>pUuv6aud?OG(~rNOlef2E&3>?;;rR7X>A$je4}8Njvn7&;C=aWo!vjvAA)W&-0!d~z} z)Iry^lyGh))ify_2RT)(_kc0GD<9rQsWz{`l8D#E7i7xRf{8K*&jSS8KNKf9+#Bt0 z+IM9=XS{ftFWzX?v0CXi|F@#b$JYQEvfyzpAN`w;J-z$@;{;-C@7XDTS4ebgYc9ej zDX;BzFmBKkYctzV!Me)hkbg~)#92pxJC4&XV5+}|4~;dJxcTB!)&~2l?&8L_?)xSs zbvVM!m z^@IRhE-jl+JwY>=RAK?)Olxc21s@>_+7vUT9v^bKt_Gh)En~J zsR4}g0n5btNxJMV^3*yUm;$M@^mdB9JG>`YBnnc{Jr>;09iEo&la;zjGG+?C+WuxE zG&y~$P-^iVY?f@ju^;;SPVCBlhH*D(e{DA?!|mba;&^UNF-vFOIA58^E+;-Aj8M3w!;ql{@0i*!PKt#OhDC8DlJEwPw-uuO z1?ZDvOMx_oWDU0q&FbC!%W6D33~aZ!U%9aeRx4MY9p}3{W!woqo6A$_%k_p9tis^T(-YzmgU0EHs_ozo43rU za$(NYYp|2Dl03+K9KPKrrp%MC+ej+>h*fBQsIj?G2*m|lm={!epHDny#QT8754bB` zG}FM(Eap!?n?J94cyO0~E7f-5A>rrm29uhOgl_c4!>h&*Tys(Wi|7qiUXp^;9+i1! z6|XIo>VfCxaDkhfzUaE@Q23HMZxD7$1}?=T(5mez%u6ZQso0B^8+?%H1;~9p9t55i z7<_JL^^?%50JnL>seO`q3=$B|OSTq!f5zL!hdT>2N#8{>d=>a#-gD~$=@EM|JOH7(uoLSdKv-%^YbV;QGgHgIJCQ3~B)@7G_PvDNpT6FhP+A(N z>+~SrR|%SSrvag3es2tu1co&xoJ;hH(uCb`I0HF7-r4Rr1i7sxYQsI$P}BSYQ6e z`I)H=Bg*L(Kn5p_og|t|I-PvMJVv1xqP;CP!M)!S8G!|7Z?^tE*7_x~i?tqH|G+`x zL!Gf-Ykln3S|2lXvhCKkjI=z0MSTM&(YBjdbnR;`y^Qn8oSK_se{S$*4;}d$B(xlF zDdl5j1iRE7Li5jnak2e6FX0(*Y%|Kks9YNy>FcY2UREZ^2kaMY`;5kp2yXq1;Z}c7 zEO4to;~n5uA>kG`6XTk04hKF({%ST>bAV&Tz_Gu>Bh}m!Y0?D?VOuf7wznoe&_=lS zW8fO|j00SgfouK!glk!bt=I24#7)_HeeR+CHuBrL@DP1lH3PHJ@(9*PaO2xp6SqQV z=_XFBQM6B*AXB2FFgu;Jeb2c8K#fJtePl}f-2=uCisgb_r*>^Q#(9k~8BZ~5in%*Z&ptrrX2W;3kfXr^=(0N-dn*o;$PLX2$6VQjI zLE_rRB33d8O)AXoJm&8b^bAS6Xt#U>e(S@it`59U4P!448a%}RgafmIbpelP4+p*^ z{Vb1Y@iB}h4hlQ3XhkkGuj<_!o_x$rxXSrnaFTu71X-~iGIAY7(l4!C(IO8#a|t=`cyA zpymf3U>4ge@y*RxS;lugE1koNbHkQT6du1H5q`yAs5uqnn!3uko{%##kDgGT%p!eJ z%nR7hp?N~>G~n*!AV;e$J-(1Wtf)l3WV|89JhHmvidy8Hnm3L6qjOv`<~Z8x)ANzB zcqp{romaJsz5fMZ0zKKw=8^}A$B)htpR=0%i2eRRxnMhJRG-dylJsdf&z(|>9UQ0i zqKn_x8cc8!=4*m=u9~dYP_T#X(fFS=#&&$*=TvEi7VEW)i*~hlzimaE*IFcj8c#3t zwAcxw)m;}XIZu+$&YUg$-fhH<(t5ENmangu9->w(0@g-miUJPOYQn)w36=#OCWYr~cgE{&P|hf8{Rs^pt!Ctn4gD;#(n z+zaU>++?WHZ7kieQc1_NfRDit^x}wD9T~>VWyn-@RImESv z1C>KUbLwt2N)e?yp#{jloQhI9!EsS3s_az2w8MH6SMU|e+=Mb0oP8xIt-y{Cq#=c$ zr@u_p?sc3Uj>pO&&BIMQSm6PW%4(?J`G^_BlsG zQ1D__z+QgjjFHP34xEPN6_Q61q@<F3@Dzx)A$%0?b1;n#K4M@ji1!QZr!rZo?KTzUB#mUx0D-q@Y`Y-;o?%L` zMD!gD%(i2t^ATH7-u0VLCJiTpHvE77UE%6_-XI}nHU zN#}NUJ>X1*AF76k6%ilgMsyP){{v426Aq^HTCe>uBtT#{$*IBa^<3tOW*nc-kLB;e z2F6|Ne>$($UQsmK%Sx*DlCmjUQj(B_^Cv1PE;%_l9$_a!BFAa}tf;l80WSmo6Qw!| zuNOpJogCB2>1yRvU9Cs0J*nt*4v$8AOj#3!IVm`Gb_QdU4LTcO-d0ZPHUQ>Lc!ptC za$x-qa&cQ9lw(oS1CWt(Ze0tweM%ebyL<!d zuT=<@2=|f?8}z_E2+MF^j{C)kmm!#NUyA!hh%ZE#kNbI;N#-Cv8=)BYGw{3!@#zRU z+)u%MKH_-@T1BI~pY?sltdccz)~s2R#c?P8Co(K#k7yu}0V=u>7Vs)HLbpL6n@=tN zRKBABTJ0`lap%6)9O#Qhq<$c`iL+b1cOZ}&{#+RdTpc{G+`i-C<7YNw|8o7&el%kOaoN!P&abQgUtGb;S#93hE5`|Z;5>|5&L3H4u{jW zY`Cx?mE@IRzsFQV`z5imifI6Grc&7dth7)ne>1h1d@n>&RimlS;`c^VVaX#}f>XF>f#(NpVKz5r}W*E z&eBPtl-+lOI|-U1dj2m%?^kr{Y=5)g1sib@os(n663K*f8#f(Xr1pYJSTHgKalQNmo`^Mi zb;@LqsJ-woG`?`kD{ioC*b%JfX#Z%F??)zhNC#y@J;o5lehOY)F33628PGX815$pH zR;8Mqht~kgr(^k?Jms?^-^U~QZkcy;{>8j2YFTZfB_365Oj`WZCZR1CZ_2TyF`bAs zOLff!NZY_()DT}V2IbQTHDN4CmR9SVD(prqjp=WsG3)vDu&?GsEpNczUl-E=csC5K zf6$t9!C5lo$Oe;^fW9n+FK6$cSHHhPUHpFf^Trz;2}=`}V}{>#GfM^THiE9zWw>S-5iN?T-Jr{h3I}tplIrcMHKDaergbb#Nd+sUymbvi0)i_Hn zUtTtY#W=2P<;s;6E3>n+#i@C9Q^j?g*4K%TZF*c>UvIB_ye=UDSqUZr@~usUV%|E@ z{+PJQvHmgpV-JfP?2oKxISKL`;A+=f*Zoi6svp@@_fK%rNa3Psc|~QJS*+VqUA?}p zZo`&G9{K*Q?=x8+%YR&~Tfcsz__%F7t5k_7{&T(lMH5-F%~~f`tzZ9`SiAnwP2XL= z?jK&p+9uxY00u=hrp#!3&Q#sBlKBf3-o5Dl2Y$E}#A~`r{2=am{w<}!);_GX&3s(Rh}4U{%-0jIGd*b)8>!G%ESyh>2hmHsFm8>fjk zttur3Zyx;hTW=pa z>}qX0f(%F9zimHu{69{deD8Os-v51R=?5SF=SLs^>61@Ao=8dMU1!ez?X&W873Wc0 z#ih%aSE0=Be09y|@9DkX*B=Pp7zho*U>Wz|@Kzr6v8y;uDFP}eQvIB`UPf5KNA4-@ P|K*QI;i;4nbNT-U=$gq; literal 0 HcmV?d00001 diff --git a/build/For_stm32.elf b/build/For_stm32.elf new file mode 100755 index 0000000000000000000000000000000000000000..f81c4669109ce98351617e99bee4fcc697157268 GIT binary patch literal 730904 zcmeFae|%KM^*=oK-u;zilimCPLK0xJOC%&9fuJIwEW6szT*suDifLTwjhfO|&NH82vw6)2`{?`}I$~(jxUw5H zv()^9Ul{EF6Q(-csEhKA2h2@B-#dJdxJ9>Rxx%Jvw&=GQX3dLe3bk9FYeZEqw-3m zuY8eR;^o1Dg=mcZQknU$vN%52fZx$2TfpyTdA*z{FVNoj zVX9n;da}BN%`E?>zyvwBhABt8pM6x=VQt@B2+vsffY6%VYKIYBfj`N@iv6a$DW+0yb;^M_;lg!wpZ#W|@tR1b*QdF7G== zCC`KfUgzWBCkiX`ZP@;G!AkiI99Lyo-h(P6q@ z>|HO{%6?h;FsX(WGNsMOYzcnnIg9jCWOUJv2rK&WY^g!Gh83;~oRXzbRz#S_3hxi( z6?O*y(3+%K72J+mS;4{pvq8!e-v3f-OKcMoHGaMSvB)GnWw1+jX0!aSf|?yCbR~x@R+O*|)q|qB$hx=2bZ1hVkfiZvqlQ~cAB*IhbylXl(8cl> z1#WS%!rKGVi)`y`mqXUg6>#x!?^6I zo$UdeJYSv;`NujQiV8*lMj2|k4dvE`pJ^)+6AIQJIxaV!(C=U&VPfuTskL4bTb+`c zcj4r@~+?x@Lw=`R8ZQnBO;o!Jld_AVpfpUCNjzY>LJLmxL$tskkkiZJo1na?{qPb4bMoe8rOT;I>$mN^Rzp&r2#=(sHuoBVV%Hk9;ZKZl17mMkHu#6T}R~Xp&mRGz~D*1HWz4NH#^1 zG{xy9j)-P~-_ad3Dw1YQ<2(CuN>Eq!E`EWQ(eohWS4uUJw zLvtw2f!-$bEyW%!W{drexiabS!#&O%W8lr4k)XKKp$+6_5p-3LP$UE_viBgQIg#R_ zfO>k0+@FP4gU;A5BhL48@)SvHxXw6s(jj9W8>^EuPw#dNKJiK9?>?s7(sLrBu{_(D zfiYL@vC0oN=EyeBg6zl#NrfX$G&rg~w*}_8jUl70*v%{lzlhY2mW!a9FUOoY8hL0y z>n=i#V|z4hNz69PqUhO?teivHS-a*CZspJhN1i+5(5>#bBN}t{t<@fv`|~hr^p4m+ zRbK01V=y3Rv(#E1j0r_40h@<-EG)6P=XvTIcR8d$mb}38 zb4Zif_ClMAIS;MfFNaY}(eLQjyPvn8jh+*j)O2e^Gu1eP6~21tpP5>4`$6}pvUE=& zC>c-Ydfb`yjxm91cfOo~6=af~DQ~^D%V9b}bui36sh&BR>l{M@V~$t5Zv&Q!bKo_C z?{s7YEGJYN{|RP#7I+LLZ+^+7+uSW-nYZZ;G;J!eWoE{P07ZILzbOyaMO$DYC zk}S5xrm}*&1JFpLFlAFoDzqBfHm-68;n-UQ4DVZm&$gK*Zw6ykNA(#t!}JV!`u@cIIyo7mHN9({LobUb4z$iOrJu;m zC(mho-C>nS%lU^UV?LT3Q)dia)Q%CV)V?6A@lNFR^r~sVr>Eli2L~}PR&13=$cZ%@ zJs(H%H*a^mdMHbN7whbnh_lEj>*VxCVFEo{JzI2le|QS(l~|1DBC97&(V0@^VZk$= zryVB_rOKHf!@4tQ+J+`+L;vy+=Gm+nGmIY#w)ry6Y;VsLiVSUnK?%}|hgtFQTu%dP zVN)^>3APQo#1GG8&d({b)JB}lTG9}iVXlif&0?{p%_;VkKZ7|Cl;`BuNQzF<6n^lf zXvq$2a9DWVbF(&=WKCpwLTJW}A*TeJwZC3%o1kqE9tjiA$pN*-V_|zXO16YnfBJWp zk3h5f<7YVMYKxxu`^y-AWP=Zp*X>Pw*!T;Q$WyY==EOX7UEtZaJEW8QETd~qSPB=P z_~eUp<#Tq=RsR2$dHbQ4Qn{?2y~W|b!*4xL{hJlSLanUH9G34k>#{xK2Xl3-E#w>O zX0|i3t@8Z{^G%VZ7uDXkU{$aLY&B)PorfXcp^#4qJ!#y$L!bF!>5Rc2vpn=jq9zpb z>}*Yt_BfK!A9MThNiJ=?KQv@{{j_w(tA|QuHN7t4um~1SnDj0=CLWT8r*EOE655S44#qy*k&+&C-7VFY^$sf7kaWh zn&Lt?aij8e0I(|0&|#z9$0KYr%OyK;Sue}44xpXP?S2mHj#IIK=4$J>(shv;mI6;Y zc$y2Iq+q&YH)VpW0{1C>$srYQXfts^B`Oqi%FE$9Y$#PUqSWR&16rrU_seJG#_kK} zwcY7iiSmmMb0pE65D|tAmCqj|ZePH9{jvVnA69v6HQOD}{JqGA+^Gp|u^V@Uhx&$x z_jNL}LH2~l!g_z!jkYuKwA$*#JZ{~pT1;H($tL(?aAauJP9nGMwJrjIKh1~t!9T)Z8gNtlN zXA5(taLx^!b6s0(l6dSXPz(5ES>?Jz(Z{(?>1NUAXAq{!wRr6L8SLEee3|ldttlFN zi_ZS*@EdIw{YJaBOW#x8A{ljELe$cwZ@;EXf4-z8MZ>y;2>5^uGiL4YR-z=Mo;ab8l|Vv~K!Bfh6+*w5AZUTzaps!MjYCL}z!uen<}&$`o}E@??9 zk+>vPo}{)|k>}X+j(bjuQx=vuTT&p!o!#Q+2OO*9MtSb>iojisuR=l#TN5;zE`5i! zOE^Em`JNq;`T@%=52LRI3t-gK*K`SOPuPo{eNt=e=5iQ3)HuCGH=T8-T>P0s(&m4s(#YvSVk7n=K2Yixosbg_fo_1W4aK^Ex9cd@Uo2yF}WXUaT z`t{)(<+Gn>%3@fV@zSwBwu;g{twx1MXC;Qi6L^krFYW}WZe?mp$NXlIo}E9X~cShrVtXZ~A*z4sWw&YJ4?CcCnh zI@*0=R(1ALsof_Deql#~>x73{Q{}_wMN6#X4>2Yj-luidM`X!v-R_q5@>(W|c6OG9 z*cle8+bgaY6+z7MitCS@w~O<6>=U>1_^^12$1E*t1aX>tLj!ya%Fkz*6Y98ToCzc@tUJ&g*8V8Jc(<>M=#|` zYaDno7rgq_%m;sUHh;lSztS%4`Rc6)-$$umU@ww&e=T8Wsg!hU-Wc$tUn6X|lxJ8o zeZ$GR+J4Bd&StJz{MAoUf8v@q`k^W$VU4h{ucQhwu9PUp>Dja8_9ItFzWM z?O*+QP1{%Iu7tn;>gD+(TX2WFBhy8?Y>HjtWhjotUsOAWj;8W z=P{m_#`Dy)u}cXTtL1K`avHT9Pe(gH4UbXF@#l-3M3eEf()mF+Pc1i{%6-A}d_4VW z=Ud_7YB~OVN-f9JA9TJN&P1L$mrA{l95wZJ=WoMlfLl2H4ZzjZ>zzBpM!@YH-UPUs z+S}O>)&cJ0@ZEr`spmS^hgqg*XByEysYxSqDNL^|)hJH_2i&h%i}aRGW`iH8c>jg2 zwcW?L)TXZn{E<#dvlR~@z4kJk>fuu1jgYsbh?AE;e=lmLxq{lTl+#tEzUZURIlHKy9U0sm*!S+U&VgP*+0d6kgZc;p+#~6pe6+@m5A610^3L8594k6c#QpaFHIU8Sz%Z>Y;xsX<*ok7#*a z3t-zbGxQ<@VWMDXa|Aoi14^|@QH09%uvOSj5Ly=q;uFQKB8O<=5RE8pl{f_RKF1M6%~lPEh;fK0 zYPV`R#2km1Mcq~%hZy1zgQ(xC=MXy}Sc9Nf2ESp)Cy~vyR=J}6?MgdzF)#8-WL=|G zo|=0Ho`y%}-(rUO^@7m6Pyf1RQdoPH7!Vmp@~bOD-zY=g5*0 zjq$u&DIJM@5}CM#%Du6o6wgYG(hpB}mP$%XEE8Vs#0DWRXJ91A%!BI6}+emII z?61*@gcXO}0jxho4RMHMGx`&D6YRCSR%*!xV7{^HQfX?9k4h7a*Fm-ZFq*JUeWH9X@*j>U*Ll z?!Sg!(HhSXNWWc1-NWSyF@4plQ%H=o<751+Mwa z9PMoG{Dt$EiHQ4jigbbc8MD8i?EruCM8B9PZL3fu!}}4lPdiHgWX>((ZtBx*T^L)) zm$va7qWh$pvmQCVYJn|zMGHj&0to5XmV zi03QYlpSwVA+^bQwKfg!GJyYq?Gd0qYKzPRT9goPQT;cyi29BCXcD`kJyl<85A~5R zP3r;CZP6Mczb-dZ*I+-oupw`Yt8Q|=fCQqzV>AQZ|x!7!`yax|8#X<**{$8 z;_YGm?V&k}+9UAxSgvS~0UDQmOLD7TAe~##N$nk|aeXs4-LF~o z5`5)iL#j*iYZ`>zfZKJ-(FkH^7S>|SelyU*% zQK$SMLY@jAJQdG+5?$%`U3^@6rE2#s4&SA6Hh?c?WcI7^mBsmj&T_s~ogI7`Uw3f6 z(!kdZ;ESR4_H$1bt1_#$N&e(GPX+xvQO|iLC!a6Ak)I6qwf<9i!5qhVQRleJc}eT% z<$974cyXP3CC*EFKQCJ4pRqpq{8zk~)v?ZOzr=cfmEZ-;Hvmr0UTx?XWh~bkNjD3{ zJNBg%cAR|LHT_&_T9)rA7qgzKJ>|_>kyV$qYW}MEE4HsVwer-8td;XuZeKayyWN}R z-8{R%x4GQvW7Z|^D))=-XWc)$<>&J2UznKbt-r%_TI}0+%Qigy1mV%y4fuToVZG~= zhcx_@JB!CzZs~%r`s=Wa;^UE5EmmM2MO>k^kmh~CrqKz%VS?ie zHlB?>A6(_45)Q@8OQ>nh*GexfLr#&T9G2{b4+idW9gQ5eEG|15dDFs1-s8$~^8ic2 zkV`A=7u{A_!&9Gie-e3)+a$gfWDA@|j+y8Dt$P9N5%gsxt+4;oeaCDnosaZ8z!7-r zO{7GgI)oH-kmEKZZQ(Qybn7p$#oR8bqgA)|Z(2s9-G?o8Ver0!_+8S?^8XVofc5x( ztiYA&&TJg*60BL?e}#wJvgA>-@=JA!IbtifxN|v<1v>x(^hyU^`Z8Pu+miNm8302ch5o zV3@D4CLF;1mi1Hyd7BZxif6J-%uQ^hHh&D?NlJ#aAvxC!DixKB5sPd-m{z_JyDL%I z-ATXtF5kZPa58dh@%*2#5vfms*Ah;M<89-3=R1A-LSYSZ@5S@!uth!z+xt~5_(qu2 zWR!(TQofDXC{9`Mkh(*2!J>K#d(Sf04tQ=w?34CkZ-#x+gbU#ruAkT9kbvjV4(d|Q zG}md*O|#Wrr+)c$*OY#3_*Iu`y%PLsq-mdt{_mP}kU;~+qrRV^zM`wtSIFxtxJrF_ zsPC;X=lIqUpl~lJ48ID6p`5~yt58S-g=S`Gl*K*P#3(w3mt7 zE!^(J`bcNqTKI4W%Q^BZn3J;HLhj3`VGwR-Fy)x9a6PS(HgDnjqv!2XHIH%YhsTGd z&v?wzZ7XAQG*IQ=soGn;KC&$m_c*k{|tjvb3&gwPUjh_K(S86ev3%LsbRrmj_ z^1Dbc>f8kk+Zw|72{6Rmxq!~cj@^=b3sSdt+8)eqzQy&R`xe)0?rNl6u2pWAYd_B5 zBlX0e46G@gLjKzJYhIBtcl@GvD&`l4=i#q>5;1Nmg@wL5O1Bv3h6z3SqLdnL9gW*F zTIDyr1E2oJ^Cp7MMh@@(oS`j+sKeY@11;3#<|CchxlGmR6;?b+oy)m?Qo1*?Qq8F( zZNC_~A5VtdVMr^H)!~^JV=E+hJ_kknQsyX0nN?;0;}h&GQ{^ZIAWnzY z1EOVa5^|G3X>6Q}1YkZMr=%~ZecLa4>GwyyM5CeSEX@%Ec-aI`m@!n`taqKR!O57^ z84zq8;o9#>uBWSn30wD7&1gH${pnakl3m#tGq}gY?Swwd;&|kB%kuLk(d;}Ld7Y_N zgKBdKeC_kjq&17yqLsgkhFQ}id*Lzi{E2(ah){uFVa7wXb}j?ODEGFOfAS12O<2RnVzsL@Zdkp&Hf4f<=w zJYk<-RoT zYOcJLX8mdGr7x9lKRovm&S8g|eh+lXCVkJ6Ghl}j?a+7At}YWhlsw5|oe!NlQ#{sx zZNs>Rq6VXFynjMNaf7DKSE9MFe&Sf}&-elDF55Rd)%{X|w98Fr#aIj76S-d_*72KY zd|$^zZcFv;?+i_bQiDr!|K8?={Z{WzupV(!pKFx5C~GzxjCE{?lE09ZkS{T*GzqxG zkBWU1xJIi3_(vmk+Oi- z=;U>lMxScN3NcUP*X&M$XR|KmX=c!B8ealDQd%Xcv#2>CuGu$5V;xfvZbV(T5swXAAOPfif zw{-Q@s6lNa0*k&*Z7Zev;61g$-{d#?lhHbZKf&KOBdGNcFCC8BsikB4W&1&I(QDMs zM1SJ$!Kf)E#$L-n9O+fiUOi~&cbjRBiyQ`L%s&|1F>t5x8>}^Q0x(@sPqQApIlD}8 zY5cA?)^Pw~AHrUQmwR`TObjIdZF?ueGpEP6T8uM6lBUYrNWNQ!-+=E>ee-A+Z^5|? z^xKi;&h|*{b|;N00X%`U{w-13X0-!_@N??K|gbsoXrBUzaOlRNoaTY918l{7!KDU4+|v<2vf)`&VcEUQrnW zY5yt~?by>3?Rcp(+VPiOrhMER?Wh5)3A4*hDEBKokB&w=9!IzU{P*$v2yokwe_bTj z@fcvwAiRd~AA~%>mq*r>U1vL9b$p3Xyuct#IbMBy$pR)6ix+lIxCEV7T^@RnuM`!* zHDz;YmkAG-y2rd2ykCXDGu8)LF<>_;4A_k>gSCp$Y@^Y4XMP>%?UEoYsC-->lYVM4H~T!cj*>)6@@yVP6ly$gG*?*mT&hJ796xncqKAlrI` z{5^sBfF~55J|R3iH)2!LC*VB`1gV%AZbYa-_z}W3gieIn*D-@1VRm^kui^dfa@Yz~ z*9YC+=904X)lS@BN%xkxL~wZ%=k+Ge`HNvk|7nGI;b#;2&VO!p-CQclv8CwG?z(+rTv@*1 zvvA|gndEgeXS*bD#cV@>nS}Yf`O zTZ(upwX3LB0wlSMeiOSU`80@iUGyt;75P4i1ZoBAjkpgN?dXUI^1|8qKC)F0;f&+J z7STE$)^fC?1v&XB8SB^|neyoO%By|FkM8o}hPqh*YsmHAhnaHZY8`rDqoHi)n1C2YAZo(sn;Sk4XJ5p{WP@sGhepR zRy$>Vb#3wbUA0qPr`O<4Yha2?kN*7e=i)?F8-LOz$v2dleLIKO*T*_u!Bf6(;;h8g zxSj9)B0K>)QQPHh#tB_qOULnEAI-INEbrCtexBzlEE_XxRB12f37XRippOZ*kKfRB%<((MmMo)x(J0s7RTeyz2<0b>@rce8PM=CSou3OF&Nps+M^!wgY|zANPi=!k%4C-PiRbRvYZM^6w8m=JI0) zd;F|s%?;S+9zQGL4#72R_I;({`(5HIev88WN#wSzbc0Q!eB6WcwmJj+O&aB+o<}OC zVALC=Deijg3@BCTW+NY}T2_?{UDYUAJu2qlp4KH9Qa7h+4f}F8Maa@VtML3FbY}8WM2zQNZg!hxk+ZZjd58<&B6|rkFdER)sr}IGf z#q+xEbmxwJ*^R=)=k~oBj)uS3*W2;Om~h=o`!0mPTXvk=Q^(!Wj_-83%0Ixq{Y_B6 zynZS688pRsvaBrNxn-6C{%+HXpj()-&?|=_K#GFr_z0JwFtX6`dnMW&6q@zenKw7Z$c9h1xgSnYf&KS+ny&cnH^Duu? zYI1B+ZSkXXFu(5fVLW%d*?SB18B&LO)wwj<@du=6E`{xa6wRer3z4F^6gCdwVJ?k! zJdYGxgI&85+fr;)l5bJdODNS#ZIF_%ukT>9L&2tTTA`f%i4~yw6rAz3A&} z@)P&z2+fzIBYkt`KBQ^BB>ykXlOuske&qf&8F$y1KOJw?39^J9do;q}xlr$>@%wF8 zJN@w=qt(5$WLCiFjRL9Ld@Tmv#& zlqhU2yf3ucfOEJxO!dw5VZ9$SH)@b)K1fzpCo zG#lmgkOv&x8`JG5bSLxl;+TF%p-<1#l}Im0#LOO&Mq1>Ay+sE#BfI+flx9gdIau5+ zfqS%4$1DqRA6SDJ7Sv40Jy*iMrZ8q`roKQgbAJ=fBkF%I-kv2qQ5h7W_DZEp84uqS zQ?88~4)*!r(MDL9LUFoV&sTLRK=&E`(rY-V+0@iqkf>TYm z9ye|%mFPZ&vr#&s(xChvl*b+=K3~y%1b-4UH>J9EtPu-S0#adSkmb?{?(H^~Gi&8~ zw?|Oki;D0fCx!IoxsOube{d3`<{XMj$Pq#L;a>AWn(t_A5KZDG8(u8IloZgpmV<+= zN^QJFVy*@f`VCqOUd+r+Jc zyoVzS*}0@zy6JCW<5+_5|K|TTl=~mHZkEA=;9fTi{pPKomFSa79>#ePZiu?PGuO_- zJ14E8ZO6VOU&*-=hu?8Sz;wcK&T92LECJ`a;t767UO@F_+JjzNzkFxH^0|Ae{Eou7 zZ?h;coe<0)Jh z8SRpM*P|{^m~d{Gm5V$jOjIY9T0rfi@Ho^75ATZ0>l}MUomS9MtzhSXI&GKLIoxGH zOZnc(HxzYV%j?V9V36oEme9Luvu|I{MlYBC`SA>{tW!vc{i_bBC;eutjm(4vg{H=W4 zhbU@#4E`t8??hfG$up_U@6ZHpz^@!g#@u^7zkB6d8Nb)FvhQBcrQ3T0J*jlVPw2nT zcj+z@JaRjvk@^NhgMPOav(KH~8mhH{?;ZijoNmgcryM-Z>Mp<=Txk|T`9}}^ zw)VUlPFFdpigQxccO&r94I_Amc341HvKin3O9Gv|Zn}L=6#l^J{JEzgOnz(fC-ZwM zbZ){B$WFu=u+sF>UfhVyz2s3Qe{xSpYp2y?b!~SDfw6m)gB9%-iM-29xe#Od*9C{E z_tWB>u_}^z)=~$&v+8|DP5&)Ox~oXHhYS+DTktkV=8f`;qw=3**NlEb$}8Ar99h^f zYIho7MA|aI)G%*0`pT2cBbPA-}7ee)Z@_?o-r&{}KdR3!#Uq-?h)L zh#vH0fpcwOD1L_oRR1X~LCExyPO1KSA8rESJstQ?CHOoAWlUEXd|ZyH%9_P7CDM@H zOHNhHxDigL_V}$>ym#a6ZajOXIR-4t3PA{@Z+) zZYUBD5_(j$=5J-z(OV1r23w(j6zAhu=ZEOm3tgwf+}};|z#YOe_P{$CDh>U5u2LEEER{=dXk(3^8=Gr`+4dO!2IsIB{zWk?*@3D;*ICk zE}=XXW}g?w9{>|26;_MdrX#%>XHu+i8mP?kI8nnq&Wo+xjamhd%i~xgOm?<7id}#o zUt(+bO2?}N&tH}tsUf&H?=Mwx-d3q}H%E%hplnm0(7I|hH68WU0*agd)RumJ(Nb`^ zH>}En>VKE|(59XbZ)mVldL zw9~LHBzw3t#w_lIwq^9DK0o_d_-R-mTk25nSFuR9-BSn>?R*h$1%Mr(-Kgzr7@F_jo#mh2F5ZogaUFV`AYA%puNuxCS%BW|rp z3!R7s$+?hOXx$Jk-Izl=5nu&dE`;yE{-ORK+0JMrhI`@|&+++HmDZ5BwA5Y{B)?no z>;OlCNgEWGX?Y(AsDp8tX3~4Wka`p{_o640WiB(wM+%@6-nAYY#Q9{G4&NfkLK{Sr zCD_y!o7NF%!rO}3pevf%f;RArwmZ|#<{E}XJhI{Vv{OP895A;+6VyH!dRe`Iq4lO9 z<^tTNpARkv)-UzfPdfZA?)j;0`P2Es>FF&`NY@3_alr8~W5rw7ZXb~w+`cpou@q2i z7>XLGra{mE(v4Jbv8I`7rF(_ERw_-cUOTW>ri|#MT8)t4pU(Tzhr@bMdxClxkVS)9 zzB9-e^d2Pn`ij-j_5kM;yAt==a5Z{Ml&T^3<%&f+%uOv>jQnBle};<=VB}eatq!mX@!h(QzV0)8a)qKd;tjoXmKIU`)Sc+5F0I2T z80PuHv#B4a!ESMW;m!$VdX50{${fHG*Aw-}JX%l|oz}`S zkFH?!i5!o6sn}X4YEkQm{#vW530~$=a~dP;F!3WgtEw|S_Oi{6n*y1hn-Mz^Peojg z5m_IZ%EZ0&UX!t4@QGobd`{OkdBjM(MabJyP)$&ks%^4yJ;6n1LG=e=v~3C1HGKef zOBF#??CJg3Ema4@s@x6+N0d5fbrBuz-vgFb@Mvm$&e$CH9FM)-hxldWq?e`^ zWFD$>{5F`z^9fG*gqPq+D%;}tRWKQQtD3_cbX zEkDCNordi$pC2$!^vxTzU!@yZx;k%D9adh6&kmyl+iwG7O?^wm`*$X-DFVF11uyb5O!2LCT&x99{*MRfRW3=TX zd}HbuXx$#CwJX4scl&9rK2s5I;q$@rIA;=g7jUD>Q(Fq2Y)VAR#rpXMT0ku}nB+ip zP5u7qW%HI(yXGxs%Cn$k4DO zcu$-RaeLFt>?_OCxir!j@A4F*_lBa(y{>F7k#Q)KiZavBtuKDcaUQ*WFr+O^2rT+q z-Jvl0bUC;6!HTTY|zjw98HwSNQiI_hP1$W{! zX=tFF%i71=@jp?GT*~{Htt|zWKSx=-m+lYY92M4zZ(jPslVNxZ(CccMrl?k)5-&q? ze<|A6vkO9>)mWFLJFAvBTk6uET{73eZ8GPlcowUzOYysEY}q_FX}?PAanzsRM+-9f zX@C9KVYMqp7$35f%|+jg3yAGL=}gT=$C#j~Op|h#Y;=qcRxX)&@$jm2`~KG25hH_Q zyM6qwCFG-MY?Ug81J7H1X373mVR;tPA%|`0zE)}NV0>*w7b4qBuwWM9>niMyg97Xh z0d|J~yF-B8Az02Mv?1V58Ej@l(>47w#`J)pa5{GR^C8)3qBVTXUG=Z*90Q-_r@ z+cUT&)7{Y-8;Y@X^t|B2IX>IleO@sf%y8Y|IedP-xuV6M^Li^Y-q)IvQql6WbZ5)Y zt1DVIr8c%2h3eK6=`?e;+`8%=mI@qa8YZGWAGTE4^2{%GaWskLhZ_9K6TC-0$-8F zqzTL{^JC5l!3I`GwkF`<5VzCswj*Uz6zLgm?^C{D8jrb8D1-wXqh}K4X|kCX2Ckd6 z0V}&CraL!cwEVnRCy$TIuFA8&wazpcdb6dsPh%D6|BO&RmBwru3JR8+LwTGQTYC~u zH-vEF$vNJGuNDl8x1+GX9eW&OgX)Oa1%?oh;QvfNj|O;eQaRM^RA()}JJyjIGlHX| z=cV+dvg6-7VNb#xPXrI%W$z_BOVy7q^nL_^{Mc-&$oG;y_=9O}xecN3+gbEXKJE^D z{g9~E;eAG;%6*{do7E^o`QdoJqxkFj3j9qPS?3w72)g7zlWRLx942nZ+b`3XCOWsf zol9wrSzODm$@2_qXL+fC-!PV`m?22yGAhOJGF#+do9a@T-tpj zOo3p;Z7m-unmt%WoK#p&kA@JkAob)pTau{+R=*y9E zm-kb{_d^T;ubP7$R3&c%uLs{4F$8MjIY#N3OF6J44T0)-PLXtGKn_FB_u@H+rQCb_ z>w$%82z*D)X}7Pc9FW71Q_+`G{mg(I-`$45tiGIiX9naja};0o zGnZQ0&PF5$u8Zfe>ND}2&zA3RW6PQHAs?>>6M8BSJv+`2D2U^N+ksR}34xJ)^yhsL z@tOPEsQ8vA1cvq1fV_1B^56{&3`QRGN@1%$h^*&%cq09{J0W0-=lQBXh-`}IU4y+* zy294N#;Vn;D@8S}k~_O~vZT)L%hv?NkUCE>ya7V1WgAAl5)!U?@^j&u-+V6Q?MB@E z`PzQ}BE41Sn@8*PgP;jJh_6@=;9Gz{B%0`59afC{x(~-!-giS@S`X1{g96s2SPNEe zcbEf9X+=eP=<@09zVSmB4_%(iu&>;A!M=7_;BG!oMAH54yJjUV zw=O+$J_&PJ(&E*hGv!9q{N4D9`%lz79yMQDzc+^Fl-6OyM$+cY8fs5;*110p3winY zk`2|89;jZrvAGnoTUUf&cGKOpVrPplT~NH0NzP|H@U^Tuf?Pgw#z}!sm+r$z)&*$v z4#zHw#%fmZhO1Brp)9Kwl+bkQVWLlcH$tjhBHT!jc;Br}h0hLkGphd{d^0Co<81j! zI#axE$$6=?+LOtFsyIen`lp~TRzFL>tA>fycV+@e*J1b(X<)iuJ@ysw4zR!rDku7zQbv zZl;m39&KE2cGvXDa3^fhOA?@5v>Cq7XCMLcVZ~*Dkp(-JkE8L}Lz3M(G>}X5%tZ4N zJ+)8HfGYJ#A3b~V8ThS;R)*Ss-kNK>G_pC~nxSa_HC-&;nmSmFpbL4gH!rHOEg^Y7 za)rFt7vbE;a@-Ut$%CDJ7*#OW#^aNvwI%?!Y%!?8v< z--ul)=L($SMEC3&fZko!;91^c6i2ogwYPW%L()Q^95voq{%iL?Jt9&BWpU_j<^OUo zyab)5;@(oe$UV|ywa>=NbCn-!7 z#%wr=T_h|8sURWnrspmuSzokM`!;x9MB9$I)m*XQv4BRE2UooZJ82^Un>x&dDpA8_Ao4cPq%&N-=RNc`c&WiXHN__WNHEFZil9 zJFEdUhCRcdhsWcbc$^iFGvo2#c$^WBr?ubmN}~0auwX3@i`KHRWGxMAta4auEeY$a zjRK22<_#W!#gH1zAN5n3cMw?z{0 z^_=MhF+)$XuQFTW)?s|t$nXY;Mow3EbJGma&W|E2o4$S0j=5Kaml?NUfXj+$T)qQb z1IK04^uT>%0PYvi($C{|CXG*)uQ{C{yt7Z^8hRVrp_p*S`p!O4eflR0WzhS%|EJ#t zn)Mg5$!#)79_)yhXRg;N969HFL9qGlVwnTpWiEHzpA;tTZS$>#U95y`ci{9|$*qgn;5~S%61V*zU)~F#L3O0y z7AC#ByubV0d1IN`LzaB3;~%*HZ5kt-6fB7tRk?Jlp(uv?d|JGlN&Y&4-e);T9N?ZDL1p5%$j~JTtal2nrsKK5|6Qp(< z4vM8cVX+imOz_sXZ-H#`4FO~RwSm1C?91l`it^WB^)MW~753-mBFRo)3#)+7*$~*@ zCXFx#gvowKD(Jl*`**k$mb+OISvXKy`Y*h#n7N#uLIIqj*gwWC+t+ZXdKJQ>vA>0H z8bI%+I6WiiY2x&L9eXp38%mtsp}@q_gW>UUdarVNO`zuoEf>P=v6sW62hb}3y#(-Q z9G4t;7Bh&-;X|<JJZ#^Y}APaU&@10kvv`d!y^VCVlG9!{bt@KXEUF zH@?Xg1?*>&LC{99fMDL7`3m-eo<&XIcw+$eC0yNcowsbwy^Lp2& zo{E-oBfc(z)!W!(YcWcIw>5Uvw#{N2@a^w@Ko^4&fzR=Y5$c3SyeV$x-5@xp_#U^;# zJP&$oEjTIe7SE+SA9N26t*lXV_r+Gm@i5b0H_T2)lPC&Ev;sSDDxCO>WZ|H+_-9lH_!!v_0LaLC_-T5T<)1 zoW7+yomd6v3y;|M)W%|gh>v+^CV37=d__c2vPsBCE_@CWC2JR3ae&UX+VE-951vxD7Ks#Q3`#&*Sdi%myO_Q^>-Z4oyH;jmsRjI|7CY04Xgfo z8rMt+QJ+o17s{EpJ8Xw%&j-&Qq~LAGFY~rh+Wi%!-K~_K^97~n{EO1|PbqExgnorVl^$s`%%km+^{;2`@=F9LiuZn+U0DdGoke{Jf#eZ=CerNzb z>6(#B;4L+JtE#WPTcc8$+S+$GHpau53)*;_x9YE2$LaxfygZ-|Vap9y#diEEXw>}mG2!Di z|4E&b@C|meFVdvNDltU1L29tfDPXs5sHPhXU)O}owBiJrSiAFnk&PbKD0vH|EQ< zJGJ2XL~K&CVB58D*D|3nDR3?R9z;fn;hFLRxGR1xpq0a6%<_0Hin9E(_9 z$yzb|cH1j1Mptcjq@Q@AS;ZM14K=6DBJ2*FULB4@pXfPi`d47M{8_lKM9K+#&Dtpj z1l*?iJ-&BPwQ!icKdhA-!$kjO`n`Wo7&`KXf_vcf-DKF$ojUXcz1wQw{M_8Dwj}}H zr`&rJG*s(90Au;>^!;tzFf%~=i*U0`v}rLv>+qhq9)BT-@aFVz9)W#FBkdlnJ+mWu zOt>!AaYJW)_I~WXrUfh>C-kfU-{?mS??|f}-~Dfju?FSwSTv0c&R9AK_YQ19`?<;U z>Z^tA>7vxWRwAETYNF7-7G67NOIr05H~WU12i-fuhP+3rp9+ik-4?dscPnJTW;`Ay z9{}AaWLtzS44f<7X82*#gEd_5yfI(1umhS6>$Oh?-|H=E7P*9$_d>g|_K_a|5_NZd zjoLexQJd9AZQ3Pj*MXYax20dB=54BN#Lih3AbsL(G3050cHs^SuYY@YksIr=!WOmj zzgzUvz4UiS2Fp9-k0bV-uumdv%=LjvvpxLb5#) znOKCcaa&JSErpJM`kp*>5T3aj2zEsQ#*rdRE$em^AiV;1&&iSM8q4Y+zO~u_wM0C*beU8*DOl*4k5$BADhX07 zn#y@>G2Ir-CtZb(F5tB9zzyc+u5aQq+VQ8D%Av?P41w+!%_F9aY++G-}_>qkfts>*L>m zjA`u*-*2ecI6#l)?2LBY6=P#=zz4-I>CqYAKs_4wjd}zd270809_cVc&@E=cmVkHv zsi$x5BH0fCHc1DpDIE^jerh07$@5VEb7 z{8g(lOJJ6ImSU&m|CHit++v-$yG@fIaXvokB+Uw+jCOn(-PvmRnr1x~*DN12tGQpZ zCSJ8xY1AE8(X7mV%^DfktT8+`nGl-p#e!;1E~Kc*>T@iQ=->#-;wk6Rb}4Ik;NAB5^q529?QG|beS0HIfMF67SJt7-;R$6t_D$HpWBY`6dCVpxuELkGRymfj0{X6y z?>_s*o|R&YPdss-qh<5T#L81BeWWV!et%>+=;_6>`w8NhyMf1bj(2%{WJ2Nti8aE6 z`HKt>4QO zEGlcocOS@Fe$15k!>r{;&QD)i#^buG4Lq)&`!0{|b890O3&UUd$YuK@E5Vl_)<&!r zDsy;3ZN$b?KBPwSlpU!&o?=K{!&9}^+Q=xL5|GNbWG_E@UY2U{x6=e$ZKMF+RG}a> z2w7^x_J`8;M($&xGqIA|xK*6LNNvORMOpXkz>QihG@%Z6tbKFqss-Fhn}}U6J4F5F zZQ4xxCEH7pv?5w7?#COw%L3Jy*JcFi_b&cBEO0QAX3kxtuIAfuj>Pg8;Eg6)tye|d z_h@+PzR1pdR2!fs61vC8VGARc#cJ-|5tbZUsKs|lVjW+=X1O_Ny*EvRzqkP!zw6Y> zPrYW7=S9p*{a@(WV+fjw4cO(=U!KxN@7{fRp~Sk##5udL zV(qF9;cIZQj+wE`p&!zIb_MbHEF}L|oQ`Q`JzcGqP)olVrha;%k-XuXvFcVgO1S+x zv52VcjNQ?^v)Y2uNf7fv>4!ZX8)9FD$%9UJC!EWY-1W;`?xV{#x}|&n;&$GfR9Szo ztMcf*8!M&z{!+=kAWW43Zsg*o?!+P|dOau5c!AE=8!xcsiGd$A*7Mc5zB(gBDIcsU z6K0wpcdL9RApOgDTI$Exwe)DC%`*h^l-iEIc3vAP0z7p1Q*;acr{#_oe|1%H1 z3A3%b#^B#obG82HjAnMdM$x|B(-;|i*xrJp5Zu(?;MoV6 zNXO>W&Az$w-HA)^e78QpET?L4YozK_rTSjmhD}+JZaaFS501ag#bU8;1^1s1XqHGz z=r)~HhYSs-s$}^5TvuJG3bljllzBr+1^h2c#w95-Z(BM?HV4$tWLV zPw`yiwBa`NCY&m3Y^mj`vtJlclP-w7>i3bSwL!nDr&3*W%WH6xHf(8s<=>XMGTGj zS{o)1O~<{-vj?H)3aAamoT4-Fa*7j)qIP77+p(z3Q@5y3E{|VLE@?z_#=V#Ena-)s zyMoV=oX)r5JdWJ5ccOX+8hTza8cDyH<>X3rC8B4bk z-2%q#O-1Th-i*}geL~^npva+kS0ny~0(whef13|CtNo5)@TorppZZXKdg^x!ipQyl zR|B4m*b6Uy0`M9p(EB>L!OH8RTAubKz{{$`?P1)Mn5Mrhk7gc~6Tz-$0;Bp#(~rCV z+cxyytEcyQG3QC1e|Uz~41!&44h+U`a$q^VD^w}iq#xpq1HAVq;ocj)GskSU9}a?- zG!1wfyrD?<&T)&hQUu&anCB$M<6h7e$qNgyOF+1LU? zHiob$kwpFj-Cb2Z8Q)ICJ+$Pt3tqeA#U8FQi{Pc* zgeun75-+}OBILRSuUqnB|4*6SkRmmG9kWtJA28s5w(J!Ac_;(%k8OWPz}Rmm_}^&Rj&V`Nxh$)2 zIw0;7@f|B3g?F~&Jv-+IE`uGsQZr;6zJ$0Fr&1>mMt_bB&8#s_9$S`U;7fbRmBy+9<@B;F%8T%p(`@GYg6^T8YiNaliF<9QyD?7;E}I@L_!m$~ zRA;rbT*dfVSf--QIrf97<-#+UW#9=t{3z`qvmnr(HZOjC1oOO7u^)+go4!@S=zB>< zVgTQxa<(^3Z>RCBIAcZgaD)*Ec?kIk1qg)*MF=Ai0tllJsPDSpp`AyqO}5srF=kYZ z`k&=z{cp&}6P7kZz8o9qygV@m(by0fgy&50ASI_U0kF~1pyFglDVOM~933_~18;T|;zYDZTX|pEWGQlSXS)zB{5cIPbdat{wVc^5~CHXLZnS8Vs zi8v<+&IORTPe|MciTi{^BSsSUfp56rd(7a2M9BwS6k#w9mi(;gs z5hIBcXE9%#;CtWTgG9*(i6$ROBu-krVC-)i{EmWC4&2*T1d~tQF|OceH7TO70PBU8 z(Yrj1CPs}e4$;ies87@9uL=$ttLCjPbp}h*$A$cLc{tA~rp|{Gl_Kh#)$Vkywo8EK zoO@bv`VjK#S)Y-98t;^n>PyliYX21+9VF@_ttE-{`xdz3z@^t?E!=gvp{0WtF@4Lc!Z-!GZ-d5Uxjz9@6P)$mQSUfVg*yN zS1P4rl+Ki+bYD3-_m;mYa+FS#qcn}?G)i~5Xe3Umr`$$l{8Qwbm$6&?=HttTgfGb0 zE`AF${t-6L{QtAjT&|-L=faxv92(P&_m(V)p&XZ>9Lb|oWH}-+JNe^0Wh(YR8fE)4 zsyT~s_w9k&*BTt%yLXR5h(+jx5YNb(hG$?M4o)edGGV6xe)BR;i{JbV>=Y1XIwpP# zGq9Qw?=j%7;irxLWg|oIcXEH3f?Z~p_>^Eta80oLW!*1*1ud`zE#Ny@fI;-T86#K>rdaBw+#EQ*=ZcmQxGkGo%pQ;9(MqzD@vB(OU3I?ugO?O zv)hI$%gSJ4;X|byXZ&5_GxmbfEL~WzIY$?#mN49dsllOQT>A6zc0k8?oAdu^yzSL7 zHun5~9d9olTg~zI!q{qz%QW70>X7;S@fP3yQ{^~&&$8)}e;8*A;dQa!6n+zQD zPOmlgmS&EL&l?;3BZ z(3#Cx?b)<$)rOSuxlX$B%92oER-hoR1Uv+*cpeb8t`kI@*Zow0nz>v{R zP4Bm*1_;Kgu}W7x(LNEhY|yp|+9xf2L8Gr35cO?P{ei4NAJCr@^qQ6w(0>i5;+ywF z0)FK51=dw#%~*wf`{bG)_zs01=L6sc1fvc{X|EtU% z!Wr17=p1a+TNUcC2)G1<8xUxWbD{nc+ORII!d|m$i~AiX>X1%*zWglC`IhZNmaw6f zT6xzNIv@Mu_Mp40c*r<+J|6V-H9oXlC+sy7<*T6*bQgN+(9@G@I@ea}49c5@a zPp#o@!HT%b22nmm){6}(e>qR}!dt!%n|Xf;{kI`BQ@F_1-aLQ7*0Q9n9c}(|Tl?{x zX=~Z7|C6oZTW4d{qgBd;;Dn%Bg$}RW{Dp_UT&*c4gS1zlh z`COrR&p=oeSYF|X$giN^_wXjGkgkQxD;!bp0k;?IZ^oD2IpRFG z1+f)@Cz~0gudF-4vnw9^b3=IF8p4x<0DMU{&JC-+r{Eko-Pw~O>S0)6bEv(;XKdwAs-Iz4%Q zw|cx+PuCzL7Uhbl=GjeQ+J6~!X#&?!GHbBkqc zyT5nolmziaO`eHB`tiX$HLflaZOdfY)lgwIAG&S}Lyk7cV6m&0X4j}3doRX>O5{k7 zmSsCd`Tc6WQBzdL80hC1eeaZI1xd<81SmZpA4I6l_AT^m7(_)SoRmL z+%<={s0XB5uE?%;Oyk{+j6g(sRGkW2>^*1CG++9eke2>y?N9z+!q0m9 z`HI2ub2zDp`6td#pL1}De}3wm1gza&+~zAyozn@io7?KEm}`C2VDZiNrGa|`wfGh| zYfN@J@y&!OcwVs_&wkSb_Flc~`9N>8HKTv}xzM!q=1`yr-)k>reTzbmHz#NOls+Kj z>ocg%;$PX^AG5~+^&UKh=~bJE6ZP@dqOEfKbB$%{!7W|Vd7W?Ak6WD0S{@&e9k@2Z z+pOmK`h2~AS|9Ju{(U|R^~3L`g75134Z}Hr$fX~ifbg>fA$c9^cM#?!Cr_{t5{OYb>w&qJ7b zI(#g-PwC)yrc|~!-Fco?Fga?IgQvp|?59l#IM5S`4;x0F_3jWqFKALp2*-K&WsuVK_uOQTCs5=la%IQcQJVZ_o6 zD>s~G3)XGfdb;!`c4ElViQVIAl~hWv@0nP=xv*VHWexXKv7Q$ErZ45G>_i$QjX>EB zv~Fv5RppJ$Yw!az2AJAbTL5Q8Hcml2gm}1YO>>cNL&e1I^fZ{Ah*@fDQBJbeYnt;{ zJ=Ywuirz@G2KQ2YwLQDb&nmQZLDER1eyw#`z_)b#&r`Z?ZfQB`Y|&NtH{2h$RaqKG zf&OGGUqv}hLVO+Kmc|0a9%_YkL(gMXY~60}+bu0ER~PXoo+#MWaJXu3{Faup4P!>` zYWSgQ{F&49R~6*c<%!=p`|(8vXa9Qa3x8ETdY4+*>~`^iYQLyDSPIML>gn$mc#Bkg zb>>*e4&N|?z7Nt9->&WzQE#m9`o0a{i#aoI6Cb4ZA8}^RCX#cviuZ^&uztsCRg6Gb z)$L@BisOT3@2Z~D@9i>udUnyF>DwFC=zbwu3Bnqlg3j?p8-P=y2ZS6)M=K7DVd~Kd zYGDx{y0xYGX0}m-E}@dW2^In zu%+=@)Qkn|wXUzFoMzWr8cTs;t?Q?c|9PeQMR@$rqt#ErHxt-~7M}W5?ac}FME2@7 zmKv&sP2Fttf*)FpUhokl#4owb(JR#;qJOB|rL0NDW5wv?7xPTLXtw8dBU z_plRoZ>-dCrJN0`DNW&sl+);~*khl9JLi<+;mDL@2uBhA8{UR-ZZpD!31#{7=jWG2 zrhEtdw+IIj_9J|a@Na~D2(<`bAbdvNWEAh6cj5u@bgy$@InE2nJ8@r?inHrSY4Nb(Xq-$`xU6Q;|QUkm8+$1Xi!WFT&g2t@Jz>R(dvvvC=Zg zd(YYL3cQN?3hqxwZ4E$ejYe(Fs6|~_%jdkh@=c*5$r%s7Nn^l-`oAOyJZU+*U(ut@ zIi=-u{?WlV^gK%)S^MfrV2I-{{fi!h_Y7c`>49&;NaM(?-*wW-`qh*CtL@u5Qg%OI zx?Mvp%w(^w1eQ`4`A`SXp7RRcbr9i*k*AL%W-NFX-#X+ z+B2{Q9M?uM{)8~H;~jI4(R*oMLQF%C=ux%#Wh;US+t=dTfC|ROy5`ipA8X!1yKg;u zMUPy9Gg``al(m!}+KRL4eQ&m$IH4D{l-bb+5~emNa~2Jq&V1eL-)fF10X{=*(N4c! z5WUaX&rsNI32eq{LQjaNdLYxAvAiI5|KhI4!ihLFA7_TOG?(Fd9Y*nnrF1HmB2TAK za5{y8(Nw|d6f}NnI5i+TaCyyF_$Do_9*YfaEiW7yQ-}Ubv2||+XcYpt7X@7PiCEd$-qhNr1}dwG2lI>6+)&ZTK_Q;AwR~g2uXS%>ty91K zN-~}vG_+?W253FR=r$#=`CL^)o`Yd7f>}e&hMJtR`Q=+NL&Qmjbv$=|S@vJ)NlW(4 z{y=O!?v+KlzDW1qFi*oMKY{R-x;G=KGqc|bG1QAak}Z@(4i1-}X%()W)c zo690iU2Qh3Q}x$xC`jDj3tt;0ZJxqOBK6fgH6cVL=o(`9@&NIkId2P8)XXh^rTn4p z_Z9rKmuJr{OBY(D-~6Aj(hI!-Ysi}4VZBhlz3@!0SCg0tXuiW)`q$`yFJ~KUr($n4EVc0jZ;36)t>M|b%a)cuTa&$V>(NO) zT>Eb*v%)gAfJ5}nB7adj?1H{Hh8ahh1??(mCl;*aLt}qd?T4|;D5q^HS}h=2Z6sQB zImW98t6vscS=yJvUk!uZ3=`!Y8lpP5swEZAPWEB$cN8+efJ~N%eBr74o*gY}smHmD z84Fgf9qHW5{U<9Z&4`xf8hAW=_FSHwJp*5&pS$rWKFcxVLyS{K8tvSXvZuoq--`&( z!{#=Ix$oJq&G!uAPa(bz;c?8l=-%!bFBA9a^yNn1 z9JTV6>fK9JoaM6d=G{wZ&FtY?XOg8cnPX;wRVd%peiOE&9Kbt3Iv0aK1bd*nGMonx zU)ewHY-n0q6IyvgY1hgg>52R4OReoqy|L=dyPabHXkXLZ-=_weYhp3`=~BD#uXIXX zj}SZspHcqGO6=rpP+HvCU4)n1a&|rT>sR6VZU2lIv3B+(R)%{6DxD6Ev#Ci&Q?2Gd zjrsLS_)A*XY7?dX?z{s3%Tla3BZ!L`)331aikk1sX+P83=afJm?1#SB;NAIC`Y*M7 zz#9cW*IHoxZdjcysYTWtN6qa+O&Kd>jk;PV)(hdz6JN*i&1r8M(`?ia#dDjf1&>Hw zw4kMzCimN5w?yCw^52g(z>cbOw!mg+5MTLl^+8$NKjEEuzqD{DI{l{*y=Swh;u@?-#9c0(%2`_3M(?i0N+g`S_E(;Ml15JJ z2H0B$zUgtM9rJ`lnlrRv4SCdP!qv4$j;47+8%kMLPIH8|rqA0G5wj!qNqf>9o|S|* zpqWDYBlHIQ=8wbX_+RnHip_i#d#F=DeMo%?z5T4EyYFBOX2{7UDWaTf@WuM{3ck)+ z&8V-gi@;vra z=w9jxSn&;p5w_fb`Z7mu{ZRf?)Jb+}Y9NNz8ZKAYSyuDMEud|NwU^dBb#??!t(<^+}YdDj$6eUxjJkTxxGj zVEFPtTSF;JY@D7`dgz|5Rf87YyeM;eHGF1<9Zymw&=+JrZR_0Niyjg>6{J<++sf2+ z*R5Q)Qf;v{Rl_eRDL;1IQGonl#n;qKtR_!`@65t~HVXfFyq05j*;q!}cHN{t^N(iN zs%dJVM|IY&M7%} z*nvQIZFj;iMdL}uTHLwe8zdPj)_pB(hMlJ7HPlqixDC51Fx%W#<-d(;3@ae24hJ`u zpNW6H;QD?20<-E5&FNZA^-$Wrp#J-E@>;nq^DrVR5i6SG)_>M)S^o$i-T^)E8`|CV zYtDLLb(Vwbx~En~U}lk3@1L{rs6(AN^7LNyiHBEO8Z$U{G@^g`+kOcr%^5Q?GGwH= z@gVn)!F_NBSJ&pDl(m?t{iXJUX5T83wXu9_%jpwZOKkQr=*spE5S)0fTtqc>{(S$U zjpgY@8_ViY=JX;e`Qomu--yt&tn=Y;&zE%?}f$=p;l+56(IFIrBHhfD|^)Fh1*~^964F3kI z58JSE?^~Kr{YksFHQm!r?K-B`Xw^V1wW)$O{iSMS`BB_ozFGBc;a0RLOCN?cIBj^6 zM82f1il+_{BlIOG@5Z27v%b`5fnf(Plzx&ZeQ~H-lpeGGbFUU$S7-fA>8-yhy>@=r z){DzxmfWzS)8}@fY!|HP_-{&j1n(!4=3Hp|?^-X^(6--jVwdAZQa%lv)@9kJu6r65 zXFZc%Pj&_yyBYG(D#u&Rx;_T(u_M*chVnzfCkhJo8MgJbu&pyEtgx*!@o&Jk`jKt1 zEVQe)sIBP>q@N+$Y7lHJ8#eX>zDPBArye*|O4gPwtnKezuh~kr_9$#kd>IF}7J{vv zIYYMAJ@1ZFmu_Oc?>IGh)A}HNxAl@u)VJoG8-S7pb8<-`#@mzgHw5wA0Bd$vp8q~*6&|p-wRgbU*a>x5*h;guSj2K$ zv6BkEox^|UqGo8di+|A`%(p&~dv);jsdhZe!ww#r|Fks?fYmkC`pVmyexdzYwZ75@ zVbL^$!jo5&A{jfcDr;unHm`8(9|A<mhhqAs|A+5Nw?8{8dlpau(2F7&a$7X z`4d~3BdW;q?ad3S=XBrF(tJWZqiMXiz`F0_MyBX_8_SNz|5R?NUmq;lT3^;bfYG?` z$l8tNWYL!Whf0%fqi=R5E#hmJ(QK6N7qfBl^{M<#REiO>TEkOZ^Sg4i;Cs^3Yg4B8 zp`CZI>$YaR%Md=s5?WvSi6~!pp?}w~vFkP(XN*!S_YLvB{q|E^yjqa9|EIE1Bi;L7 zJZiUXEH6Y)Gd$W)AtTK`q+zLtYHcX1bse1zffbNyv#Xw9_2~VsPn#`y)0QL@CC#6@WKzP9Tc*v=$cm`Q z^^dLS@4v5NX|q}nuYhOy#yduq)ZVlgC$G?YBsJg~6FEAvm<98yUAU@66XI7FSnF^~ zSE>6QTd{qdrSwGjOw)<8E}e~h36>5G&2u4~5^CzYVm zh_z>g#a+KW%lNLv$y#+DPq&7AesS`FU!A>tHoY+tsd4_d`SlAtPZevWmIoEAlPsX~ z3=nwG9()Mv-{T7-N{#&vdE#uxiKQEGrdE7mVi0T9Pi4%YlP3MayJ-bbh_1PzyKo&Z zuGfa{MEpi^y(6>&ahyI`wOssesB+^wR7;IhL>jPeB)u!v|KLjnonG~Fe|`C8tN_8e zNmX_{y&f#SMC0MTcq|`?2N(mze_w9#{~WgakA&U+!{M8xB$w*K`zMlQi;RqPAl!rC zWX%6%*y7&{{t);-56_VN8LBURK}f4(>GMPG^!c?G|E_RGdPS|>zau33KccgM9MDu1Ihe66bXV;H)6d>qdZcF3xC?G7G^u zeh_rrz7>2pmBHelMttM5!FMHAdrd}|h;TW5!v-~QDZ*I5qXCaXd?Z34;C#R%5WfUr zDBvORB!dtifRGJ16ZHOw_eDqt+#7HVLbVSD=3qVD5!a;FZOI(2Gy#&-U%tYM+^ zh|V>|V-&pvC*V!At4H%xI`e5`qnnREbA0|o1=)2^Y)Qg?F=N#a)@|b5ZASgMCU@J9 z;d4#LTE7o>F8)5;saOH-%z3tTMvxtyC{BJ|-{@8#13RKS*ZG50Tk4Qf2iM8-N0Bnr zDo&rsJB-oYPH!Uc+!D{le0VM<*5NS!#@UBvyJ@`=&hIIlL(faBAw}!}VukrQ|8rs~ zVfh7YHhp`+z$zWss_geVusF#>N~rSl4he37T}?ZSCN2ebwUF!Uz_N+&bzo^OWav<( zbDXa^u~em#3VS$1q)SzYeCA&&sMPOi&(bb6U%*E(J83R7_W3`KeZRh{^x!w;193*2 zvFBt*L2m6^7`aY{TJR);_NC^H%)!%07M&eR7bo;vuy_2;#yo}Y^Q-!O7h-AOh7Od| zKG>LA{NiMQf759o)8nVp(~#%S`}`l`1Ve_Mq?PD$u6lcNf}pHD4}6}1=csYx>70tE zt}33+8PA{?JlKkimL{A#6G#fuS+`iTUu&F3Z;9?%>+>JF9y`A9me)7CboPqoN=DC* zZfdx_5MM~g$Ob)PXvDq~Uv)VYN|GM1s>1_PdRnbYnthM222i?mk*0u3J1k%@!dD6Ta%GfQcxFrBJ|Q3a}Hs(4bF=?&r@R{pIT@Y+LG4N z`Ww>J)rje0|AsD3&#%P!YE{tkEWY=*U+e(*M;mtiW32hEIVXg5WUa1Zj4xyGE$8|# zr+iRi$^O85f5F*(5o038;SRlCFSTTCC}`Ptx@lBfGoD&v4FQcUjQOS^`2No9^h;w5 zzGBas-(WkNci4A4jgt>9j`v4`!ts}0ntxeQze!W@E_L*{k(naK*vJVJCXAnun3(8G zOIeWSn|af$1-^MVE%eQ*EMKs2K|}qiFAav7Of**OCS4jMcpzo4*a zWPs}S0bW-mi1NBA2;H3H$eqFU&e{wQv>*&T(GN9NbYYj=G_a8X;&9|e!8~;7TjX!+k$YjX8>eu59 zjVDf?I(??8`RuutRvcKyu5G`AL!WYm+4B*Ea{u@8e{10X&>BDo^ik2O@OuQIgc~s7 z{{Q@ObRIV)#9Sr6FMi8rl}#_l5_&|nK_mNK%B+#LOC3stJ=WskalEtYrjUFruD?#ln!|QT{!bjk zTIApUDRx^#GI+T?0w*3S7Mq74#a7>mF;(OE#wK1uiyzBJNsP_6tN>x5C78z8BFhau z7+Y*PZ)NNj%X!GX)p8_-vD+=k#c{ls8wa=Zp>2M&UY4D?~{z(e@$7 z;aWTDVTAS=(&lMaT=TWpkV}D93~Hek2YV>e)_`ZEHV9X|NJcA<((K5+ShMwHY_wK~ z_!w;k+GVUZ3-ZTlqrrKpHVLJ>OgjL4i8cOTT4Kgze<~na!u9dqV=!VzC|gfY0IJcHQJA`rE4`GBwVLuLx)l=7OBd# z+anm8p}p#0Y^K(V+MA_KK~2uqPNDX$*A79Gpf(I?%e7aKc8<0SZ8}#Q3H}?jc;tQ~ zY}@JroAm_R#PO0k5|yARS`am2%^@>O^=6^`ibcBt*(!GJdi+>FMk7S@^JakAmItz( zF4jFzI3lylaKc_eh-?y&)8#hAZPydq0$k9GqS1>S7Oi~VLKb0(Ql96In^9utFt95x z^4O&S6hCtwK+%<#czi9SUnnj|e(nEOg}4rLp++z0N6*A(TS+>r=Na5_?e|Afa@0#CJh7#&mjm!T9s zN$AW0ld{Kz?amo60OeB?cDW`NPGHJsChT?<68yOddz>Gkn<`)M*i4e+_c|Xy7f?bb zJ=wV$2B*}TaH{h~n47ZKg!?!@fDtPDOgO{ofXOLensAPDCme(FZxbHuyxj-*D-#~( ze4O~d=CNZ%{&~*9WDIp?d5fKgiGRNdk8{S6yaPOTmf$aOUQYFLkjLI3;8MfdzTvSe z1ia9>03A&E)=XdNDx8G!|Hp)HbuOny{?34fH7R}?(+ljy@|Mo8@BcX zk6nW-RR8_lFqA_kN0qd-A9?I^f@6in`7_n>Pi8K=EY1c(95xXjSe$1F5jGJYTMTnN zViZL6e`;~QNEY&6GnbIX*@+bU+2r`r;+#))dDP^nvp8R(&i;#u_{QQqNQh%5qTb?6 zh2K+tH4#5roTp)r%5f8M#Nr$RC!sW$h+izuL<})Xqlsv+IKL#5IAJ1AS)4vn>?Duf zCW?=p$PuLaDU)NB=G;T2J#8Y^XwLUBE-GhC#9Gbiqp~!ah$l7YB6wn@*+i_@oN1KH zS+n@hY0j@5K%6r;nk4Xu>vT zCt6I2<0D5J28`H=6PV-U7~zclEVgh$CUbluK?}ev=J=Nc?RsyBckGd%OYcwMrxJAQ z{ozg>pGnZ84I9IW39*XQ_Jg2VI&39OS~p1y{_{SqwFA1CmD1dC&f zpv6H6jbqj?VLXm+)HA3*kJs@mcdSPRy5I^O8@c3S&bi58dd`F`u9AGvpEqHMF#4o3 zf@Ci-7-_CmL4~=+ge|W838R?fRuhJ?Tw25&x0$fZ`8V7mIc`^DjJcZIIUSAaxWj}! z&LF{6ChT>-MaHqzgcF=qL|IxH1b>5!}_)Zh<<18a%y~|9W z;hH!ppE>R};T+d!a!~h}{DYlys2Wz9@G!%8?=>qw&v_$x&HK#s#fGuouf|YiDgJTJ z$1Vr`Z$^4*9Ak9b0IG0C=#*7d^$)0O0Nuuu>{z2ZieaEeXMfbpm|%47$4uDbBBNMq zf_4|VoX1VjLzIJ2|C_Z9c}Q6hL$@_KB?t9CTwv&K*`=UVY{=L`pQld#?%{X?=nHRYvd@v@0qa2 z`98JY`zGvleoXLg6HaixK*jvPgnh2U%O)|$hbEltDw$Zw93Po*Dy$Ro|7pT~Tob6Z zKQ`eE=O*&>pO|ota~r|`GU36_8iMzj@G$4Q1b=G6dCuF(T0S%3B3BW~|J;O&of=j1 z7bc8P7=Roy!4l`^RJ>Xfp5)w3;`f^H6z9hT?=#_P7&tH>d}+d^fU_`HFyWcZJ&#=B z*Qz=h7Uk*VIHo#2f^#)m?YPM&Tdl!_X&}jl$2VcStAMKQgbBNxg{0?66Lvej)T*aU z*yEaTIrvYTu-7%3n)!?gCm5Zq$%K8b31q#^CYsuSAVsR&|D zc?1#Bi&UoCcm`(W&JFl9DxN2O0P|+r2@G=__vRQsoX@MoZL+=0(}=AG*2%P+;BUdU z40PvfYBUIn-SRocXvyvB#b*+CwGjF`achxqONurbonK|v1-Son^-(VYlbIxo-$zNF zKyP8%VE7zl(1P@?0cr&ZF$s}<9T8|8{S|b~$o?*4EM)pbG*o1k1TFeuD(V0U+V!IZ z4wj%xZy<1}1l{^+0*6b`qn{%%UxHp{Jp#oeM=Fm|_U_0rj%k$rP8ek5ILXBHUAXs& zERmo^$BGCRIZ1+c9UF~Uj^CHkoXdT zH+4u{OW?u_5+A48+Fz6)Nn90qtK(i&uzsAfxxGW;iCln7yO8?0xz`U8xS|W?t@u59 zD%w2qZpoaikB5VZyibCu`cwiRlwcqIRy;3?d{}}R`XVadBNEKfXJM#{Tr0uBdIFj+ za-9T+=}%e!J}tpK{Ynz`tOSenNmQ`sBv`DMz|bOJl;Ai$5A(3dS0q@XM^nrEU4oPJ zIM{3CW(iKwr(uMR+$zCodK!E{b~7bco4`%5pd`QtQ8fD=J5DVK$);z>|omK@zm+Z=waFawTZj zi!ou0x@`@S9&C(HW?Zp8h! z?o?UiRnDNZyC3XMPF(Tl=-18x_)vG7U>=|kp|q=eoDkq({aIAM`;kOzJTVW`S5T=Q zlVF~{6(Ze_ORz{^Ox3qeg2nn1B@c0H2Xyi5@!z;IrM0=NFUo_uxj{8@n5W z#T5NUSfKlP2~K03EOf`-+2Z94nslKHa4sm>$#M!;YdXsBeo-MzOh(LL$5-Ice}T*x zvyU>*QaO0QOB5#?bE-3E-}~2w8?rFoL^F<(gL zJkhW*wGu2s1JTneG!{f#3uuHssL(r!P8NFI5aW%_aP)?Fy$r1rd!ZXoL;c5I=*Fe! z6|on(akLGf*_1B59<395!Cjt0fnz(|C9^IfIG}upT%~u>v-m<}s=eo<&K3y;x%LFq zQM3vmRBb!TZ_!#{O`0|f1FKb=jW&&DR*oNis4@VFZ6qPar(f-`!L{pmVZ_m|>1d)~ zkePm6M-wf9wd-XaO%#JZsLwE)NMD1p>*mD5t?w-Xc)g^0^oNLQ&NEbEEE6wT|ycdP(b z`HZfZtcNko=*uKERrkX)=_@3)kKTllO25lzSW1Sl1^pf$-j*Pv9AOLky^=au{|>gU z-=ApM(J=i}s)Yw6n5T~;aFvg0Q}GwY7EUZ;`oq3D%=Hxi%-F)w0M|%xA(4ApwgDBKcU7?~=NtLMVVbO=t%b75qfN1*8>TzVu7z++mLTmLuO z+f!^d1+#WSrk*jX8`;Dpc*Z+UQhtL`e;(60F#Vqk0GiIhqF;&X^js-L*!8R620c?H z=+eKy2;?!HgIk}9I`Ei=;nDwwy7!otfRVnEw40+=Ay+$P9pmM(MdhWC1}T}MnyfNUQKc+dAxD!;_1tIEkNxI3d^+Z@C4{?Jb6092fl#$Znw?@9KF9_XY= zi)T9TN!ihZLJzeUK4p5EPw8WwG)jAB^Pc}fF%|zM&X1-6zMl7-DENmv z?LRu&lxGKmnd#%x3rNRlJ(KW$SG zcmI_-!b+|_j1)1xxPFdSVD;A*V(xLFr@a9?iZf?d7X61Bd8yRJB~Xp!5hSw5ZBnv7!xYQ zm=JeTf(yk|BkpuJqZ?G}2dVf?iS$-O@!zTsB*`rT6gO@(r;KY8QxAG~3#+FGDxEC! zBF)Q(g1ZY{fC)oFCrf_-?w%ym!&O3c{lS7J=+}wfy4l^S_{`!x>)(n=wG433i+DZk zhc7Vi;fz}z%LQ}KfWNSqPbKWa1>;0KV;IFP4=mO)R)X%>%O*}_7Sp~xq9a+%+Xb&a z0BTsw8DxU~5vt5$8n#cL1D|Ix4I2g)hQZ++|8kT@yfaLJuA=kWnLQ5iuA5P2t#2p7 zqaT6UVi`89YcZs1xh57R#u`U^*U|9H+Nj@RS=T3FS=uCtRV-F4rE+_^7Q^thGKr;i zn;Hl)9&L}~7_t)Mu=bhDFgT{uIIJ1B)nu$G8o>RsLhL$?!`crW)kWj5cEqeMX3ayF z(@v{vA=ggAV-jou$IU>BsQ=`GOd1{2yam=c6W@o^9Y9vMkel< zJDUb#m`~@T4o&G6xwBagyT1K0fMz*d;(ogGM9J(HH_)BU8+H$~Zh#4No~F_p|Cm_s zyAiP%o%AA9sdtx?=Go*d5}G=O^~=+w($ zhTcyl=+awZVcyRq7^yEt)qB5?78Rx63tRPuB#6fd11P7xsuu-~aeKdvm`Sy8D~5jW zR~=UPvJK$ZP9l*N-bcFDNzkry%3!}_#&mY-L{Bh06a4yxUeD8}XeHsW;>tf7;7 zzv~eEq#aqan)7-H!h1ZIqy0Uko?s zJt0Atz7Aub_oM{fu`?Gk@2M!mOgym*%N8;3=_sSucG5qzg7=K%_395s0Bn+Ag8ndN z+blt!zK|U4SqUcV|)xQClUL!K}Zcc;53`BTD3Pc^P*Of@wHK zIXQRBf;u%jxD*~~=%+YWQ7foiCuW*iy+KkeCf)A*@fyHbh;tsBT zgKF$#DWSyNuA{Q8J7F(fhDQ;~ekCsQma)rMQO5ykXW=rK)(xDP!-5sJjOaP47DSC( zv^!uwnsy6@R;xydZQ2r;yImUy-{;WmXwwMoF?3R=_AfMvOB)4UBDFzik0|YB#G|!^ z5ztQig-lrM3jSDaCn{BERy_M)U5=`>EVWx1GUk2tt(eYnO?^vazHZkOs-KCfAk?qO zh-buF&?~_8iv_3=XaXGecOxbYK&>a#NJ3?ss7Zv{0o{0xiLw(a3muUUFi|^Hptcce zkY^N%4_P@tb)PhTAmh0aH0A-7L0oC57oHm}QGEzij;_FSyGm55;6g3&+!TpQCRA5U zb$M=oiSiN3g?R?g9V}4^gnAd|$#V-N3QfbH#2}!?NR*ej;;0I8$4iulP?4x%o_n=K zxd}BK9+BtHlqjqV_H}z1mCkeLNR*vWX*NPtN|c3Acf$txPzRY9ip>f2Ak2^t)g_7% zYB9;e)^vlbT>9u-EKzlYiWVB(B2ixx3RM8EJ0&lN}#C~geoJh{3MAgCDfgiV}6!Il@RJ2hFG4TFHw1f@?cKK3v?Q6A*&Ce zx}y{Gf*um(B~&%lUtuhb8Q^jeYB;`WX`)=E*2aK|l zyGO!ZK=t5n1BklWqKo%-T<;H`ATDH%aAfr8-^a&8`-Bf9PY)bph%^;ungU8g7qHWd ziXJ?GlEvJpNdDN zN#1UfaUzTpRUY5l!9|lEBElFHybIlZbQy%K#d2ftjliu$e4NHbJGT-aU7*W3o!)!) z;MrtS_n4M(fat>RCVhYlSx)nqznGJ*05wAZeSl{$3ELUMZ2(uHD3eiox} z51vc6MHQN48cs~&Qe-gEQWW$6!Fmr8ciyf_)^cK{`9v3rfr)1CN&Gm5n&|IroUiPl zQw(%^AJ&7ffx4arW|h56Ou_(q@B^qHPlZX@eGz3iQJyp@KbRD=13^0TJY|x3wiIcS z2cj-L^G$MBlMG$oL&E5vVTZYd6lEbd+=bq$!LV~2ApbX7ykg^1e#3&znO8?+6zzq? zK7K3`vyB?rjLCc%QuB8rtUQ#?>|Y`%w=w=a(x)t5$`~OPaovj;e=kC1JrhwtzBwY2 zSH?5@S_DX7{7WS1RR!ollsJ`_Xev!Iu;+w7LSFVoKU}EC!lf?tTNUEQFZLfFn;kUWB;aVA5XK^s zLdP#rB7U{hu`Z3-NzW(+$ZgOutL92U?koUc`ym*LUt=gf6$p&&Eb~XCCB?5tvfnG- z02(QNyQE3QEy#*SwDl(X1C$44MF~>*1b!Lo<^H3}@V=<8{`?D?0S}XkKZy)T`E}5Q z-#Exrd{~4~d?&Em5e&tL8;Xa4pq)jTFCiT%?nAQQE4~dhQhbo4NyR?^S^@eh6a5Fp z{{@cU)pa(XNFB3NL8_>(IDUL{F+}%<&l}^{np=v*uBffs}$@-Vb~K zyb+Eb045-eLFhMQ0pndFoWwvoUsfWZcGBU0IFE2}nuSs}R6|cA&a(%bwZkJ4DX))! zeHS6)1Gs3e8XY9cf?F$uUW<{AD%5Be+&uFna2<3Qg(&I7>^Ys8JrS(Do+PKn3UVd^ z*8qDJ!hq*H3*@B3K=R9b&s%gOi6|%C?gxDZLI%g6$G>%m-f#ejy@Z^IL5%;$VW)fY zP8c*j2pRO0fPZHo=}}c0AzQsb)*H!Z0x=B%!wO9`J6ULw*q?unc^}^(HK!g*e~*KY zKQYAAe1l^kY5s3uYY`01H#n}kSn~~zd8D}oV_7SB49(v#vYr6s7z9J}Hw`5p0OEc^ z3eEpvAYTGv10jXxZyCwI0pd#pmg6Hgai=3j*vhRb%>D~P42DO(HW!{;RNU>7JQo{!7ZP=#W6xL$a}L1DcPNZCR; zA%Nw)MWz@lOFzZS>@@UUgW~WdBh1prI($_6JAu883R}Xs$0+-!0BMIv#ycrU5$ABy z)G!s!m>%7xExwhpI*8=r`UAyM9BQ|raNu`>jF7eo(!5N~_p`c;96b~_sSO%RN9okp=i4%cB~B>kQM(^_H_`pp)M=p>8}cBsx_ zQon6r*dnBnek%kMUGJsXFo!LN7)ig+!StzMB>lDsM!N2x*hq(Z4Kb2_N5FJgFjD=! zD;VkeF~vqXTz3&8>8D@<$|wl^_6kP$RK|-P>Z`;=^_Kt!+ULO1NWT+;iLT8Q8|Scn zNsOf5KrrP9M$!-88AChUjbeUiz{qRT;jC9SR*p&`f&r76!bHEfN zMxozu!B|ZCO>wAWiHY=E0fuEl8tHefV4^G8E1%}DEhI+L?`beSNsO66SPIQE9|MVO z9*ew{JaiB>g5hTZ&tRDgCCl3#EFP0Zku3L1mTx;)ek%pjg|(7}4L39TtrW2Ak}N)h z#qa`91f%c-nsIz8>3P4STcj3b%2bxpKcgdkhNM^h5A<9~f97JkVmIr7ERn>&`zK^b ze?pS~b1@m(3++IELDJiPM;E0-HIpHc`0ns29X{})(qqY%pkHz^U1|sM*sCqb*IZ0C zv(I3?$PP&S#iFHZY!LqieT46~TRA!QqF&7YCai;}7MkvDzr8cLw{L*`3L)!hpWsiS zfj-HF2b>6ogF9#!4(?4L9z{qC!Q5Ou$*$?ziDEz6U2V`Z{SZi%xF1=Jz|!Ue@(D(| zCR6MuyCpvlj1PeHFql>$q%Q^VA|lTt3|>55mm5_6<6t@_7^$XWi7c+2C}wk5T1}-K(Rj#!Ae8EkNCLtTYChK_o@Xe8 z*E~p0*CdKL9IliCsnB3>4@6*@5m1BdxELhEVObRP(2E_`ILQ(;Sd>Lz?4YBoOp)}v zC7mYtm=QpVa5FO{`NiKQcT4&_N&oQTC9g-uW@DC*rS)jAF zN*1Glh5#c6j7dFD_C)7<7M+zQyEGpuLCx?zBhfF56+w!p&bk)Z3WUrnz(!S8X=K>p zS540}UDDV786BQ!zNEkPJG$wYZo2h0=S7eG(nL3bhpP#vc%*2 zTkON>M#mb1&VrC79^l_%FC}Cq5PbB|}>WLq{g&{O1SB(xcd{4Vg)nl<|vX$nRh2yk2e@N>IGvx<=ZSN z<$s_k@C8)s_jL$0Dx|}&_Hs!ML#vAoF%ynuxetEiQaF~1Bxa|_A!pIm`Ti1|Z?pjz ztOKY?{qYbL2!1p4B6;v{#nEKly2*LsuWgmfMu5v6$%8fHW0MQv~B=%#DbQ zcZs;B65|S+GKd&wg0v7!^E)IGSz&a=J_kF$)25V~5+4B5{T&jCtT4I`BgVUI%1Tq> zOJI6IFz&nqlUKn=*Kx%7H=DYX80jhe`(WCIAfCe4A@Y?-6>%G$Fo;xioj|D`u&GBV zRTq%xD5D0!cnmX4A}iuLg%}^ip7L>EYz4^`heZ_#EbSTeMItNWT0xAfZ0f&=@pX`T zf+-nc=yu6R9D{cN$OCpbLR#@sLxN36m=3z_aHP7DBwP*BWbjNx7#svZ8+C3(V0~aqBdV@@r-V5jzU|5Eb9uMGYMCde!!8ri7B2tY&imyg7NEv)e6W7~G)I&CvUSFhd z0_kJ0eT0y{0RWwF_6?;=+YN|#6>+_nQax-_2U4oB%vQ^p<2py?;vvakp_ny(mdO^&2vIFOk|S z$@+Msa7Jnx@&q|ql5-^4%$?k$VCW|qCP@ZSIffq-bi9ugmACL>`b9(g7)f6(>A$-d zxqkMQxmUTQil!&6w@Jc^i<6N}u*`QsqDjI!gJh1=bwJb0p$|>;Td#1TQ<^jo6!354~|# z9xBRx1sv}p_%8?XQVqoIR+Tp6s1H4N2g@Z=2%(^Zyu&2F1TvAZEzDllL4L<1zXmdq zP9aovkl!`Qn?WX$wJWnf(?Q;8lDC0OBrn3d9pqgm`7Mx%l!owa2l+jdyaQw+;V3zK zO9%OVgRDH1$1=x(LVY}8f?)@;m*!bbJD(~UhDnB7U@o|4A7;{LOZqfP7nY*f$C~sC zNndg?y~9#&m(+EVDtZwN!eu7ES2Aq>9fN7dPe}SVlD>r0QzIJ2nF3yr46VOqV5TL% zDe2uN8Wr$YL%=d_3V2^KO445b1H~sPyCub_Y)X?QDc}AfpMaz^Ns8g9D9toUi9vtp@b5zF z3Q0+q6j7`H4|{JOUPY1ji+A;Mx;v*&=bR8i0wH801PCz+AOS)Mdq9-MfC$JAf-LeP zC?X;%BCdeozM-PH&bW_`j^l!g;)1(^`=F!aGA^i$>+kcasy+#f_xHZ{KKFU11-$6`JXr6+jdx(WJ_@i87P;c1%N`)gn(~Pb7?wQ5tZ~%( z2Uzi3OfSJ0o#=EcP*7Av6$%Qz#*DJ2_K3w0M9b@jMI4prheB5DJ{on-%e0M*<#Ii| zxpAbbppJ;O;gT6^D^xV)^I1A^Qp~!JPTU37+Ys7KEmX6{ zx3GLoa4CSFhoMUtqf2s?VNlVO&)4b1$uVm$o#+i#351GZx>f-6g{3z^2Y@lKjDj(` zl)ynMn)3M}oj4_Cbvg=yBf**vp?TEm4{$mxrxDZuTnfv@Fh-Zp;UE=F`TUYjoEo!^ zqZ6$mco&5JNG%V52Ms()@Dr5Yfn^Vj(d9lMDw^{7Bb_)cX5B$2-UaIi2z^JbmjE)` zVvHN6>vn*Su#~_UT~+~6(Ui{^%8)ocW_?8`wt>|jLj9<91;991jwHAMU_LBdFl=-g z21G?uKC|e=nK7&T1PCq$>nsTIILEFt0j`AQa)R*ycfs;U7^BN_WHA*@`7EFlXT_{} zbYe4DJ0bK8way0k0G9WtCErBKng*Z6)LN(C#7Y2sx#3x>$@kMSzKK6U_g{33Z(_0? z`rt5zd=n{a8hqAK>m1Yr)Z&}i2|^vE;NlgSnj%|17t?l0%<_(g;AvphLx^Xs8eJ{` zBHNVDr)0DzGL%Xgme0Ymok{@#!%JEYw|m8>83U^fnmPb>LrFjn}W4kI`5V zN1$3iT@m%@INoebwrkc^|IT8Hv_f?5mn^*~M)oinB`zo2rIl0R~gXCmV851=}z2LP;p<+^jD{+qP!9c>}H53ByL48VI6W&?G% zL%goAJ#0TYIovsGZk$|w3AmHt)`Z9{E^9Zcuc0EUz2grg-w*O1K;GDrjP!#`s-CQV z1QJ{fdUHz&qkad-j92}0k!6>*;6il>1KI+~K-MSL=0L2|nTW;nxH_okNi4uQs+Hq4ZV_ptvx;+-cG8MV( z->9wyxedt2wfXTI}=l>gXvQa-COc}?Ck!6au7-bBEI33}{MpADtOl>|0 z-H$;ykBh;!&dK49E_36oF7Gc#0{{sjpDSrQ&#~;uD9Zl?YY7z5$Q%8B1~4~HQ?Dk) zOoPwWRJhPljpX?N2rZtMX!01k!&mbhxN$a&d^N9um6&wWC-%r zybnV6NWt1uu=>uCIfYgJPTwV^lM8e9Q8|Vm8U8XMD>#F?3uo zi_Dc&l+syvvAP!`y(c3pm<=3_s)Re@kttDD%senF_R(vDPi$WG#2m+351(XKaJ$PK zm;Wd+FF<<_V^lM8%!+Mb9hemi-S1>YNfA=MC$i$vLd?n` ziA&&)IBi;#6?F$@#V$w*gU`LR^>?hcQxOQh6~{nv63l^FK{3DQn7SEwx5D zR!1b5%s`_9W}d0VcPR%T8%DiLltpukX9Km+XdFQ;W?&VBDk)gaBw+^51?#{JWNdyX z1LtKTzkak6f{o0|D$D@D9dY^esQSfm0|!*UX1e-S4UrW!L=DwRXtO&0K>CgFabuQI zT?jI(<6m2nqw2UEOtw<3;i0U;l};_ltfgyOlBLdMqk1fuY{HrjW}XTs#)?{_dLks) zgw1a$Vbsq8Syu0JBg=xwvN*CV)fS^{QxXaB3R0#NY5FM4g-n@AGozxt+diPe?*R#6 z@YzV)JGS*5e3wOg2Na)zIk0F`46iYsBdPGdtt$Kp0BFqdoT14BXTTj6Z62HOHjFIV z-@@`Wj4IlcH4Q%JQtJcTnolhjZNCsbc^IP$i}o30%jbo(eP&ymDafMT0YdGiAd5EH zrhHyP!Ov~$Sqidf_kvJQ7+JIrhvhJ-#iC7FG(31-L#;1ti!0V;(Vh*Vnbcy@J_VMO zr55WZ%9`?d6Scmyt1m(UsHe~Ke#awff0S@M2SB6phTZ?P@-QCHDU0Hs@41Uc2HxcZ7rq-6a5ZI-$soC6TJq(5(b}rXgk}sZlVSgeLJKdhmncC8JA4b^{-IF4b*tz1`kgZ+tw}cTPF3e zV#62$b5K%K4qu&kmQthCw)RkiNj(+P$57+Iq~1U|gU`!oYvi%Z&|p$8gEY6%%cMRJ zmUCcKQd8D6_}oIR;kMO>T1@I2A#?);tG`0Pnbb#v^*c#D7@92KOEtSiQcuyW_5a4| z#E||@QeVJk@(paQVluO2{{=x1sd-USziS;>mAr2?S0(%$co}L!K0l`IZ4JLK61fStB2PO3kmVSfJ<7mSP*DI;Pq%MPW zDU3{NOm7-}U{q35)-?EBLahwjx{+E;>hTb2qG0uQ1c6Dt9jxC;>Rf0tso&G=7D-*B zSwH?8s}n=|?@8VN+}220?qXYsK|GE?a(hPE7i~d38`P^R(2vI_`yvEPT+R&mDuC@m zt1Y+N;WM!sn~c5p(czc}CIXA?v5rw_RDTZgLm;nhNoHGdDn4rWgDJZPKWmFo_8y1) z4uOxaVh0R;y_-JXa9rf$q0K%f!KIITBB#{?|8kJ&w!~B~ZB)<~IaL&FvVLp4;K%4Ox%C z6wom_^&=uSCU2_G1&al*AK0?s4Q_73dSDy{Y>WaJW72G+{wvV(K&#F|K=)Om0#Hnb zhRTN;^#$O_bSRE2W!hpii0>{&3|6ZhV~p$Mz8I@11&u?#15Usuw>8<^{K^9p=EC$D zd?=#O+wi(BMo;`*3zA!fT>tO~aJRx#Iq0W}8x?Us2w#!-iU9E@MXc_K7rvRP+Q#}!Wa^cDF1u|VkjZr-fByLQZtV!LCYMjp{Nyj&n z7HiTOnuJ6=QIjriCanR9yOjQoGp*JyrXk&3LI@RNMZ@S{%#0j@tU(gMpk-Ub>sr&fOq3q9$EI1Ajp8;c?Vyufm93cANjg=Tr<|S$$jK5ix4B0kD_Az;*<+n1~!( z@^`@IiokjuKFGyHeIe5uMlL2A2g{K#YBAAs^u*wEm)4StiH?K7To}2SXbmhpZ%QsE zx*QfBE5neMAPfxU$8_W+`!R;Jh9T|Wf>GN5@CRtz4kMR6QN@vpyXoiqacea+Wk{cZ z%wsSzr0>AOd!$rI-=!x8pC4*18Pabc@D+>OP>!3v4uwpQv>dsn!DkueevQqI zLBwa`g{rTIg}u1?fv|A-V*OB9xGtrB1T6egtv>=59w<gT}1(S`csVBtVf{UTU6Z(hFy7Je<%W75du@wLQO)GH&~NaHsY;Wecq>TUEImk*(7fEON#mOpAJ(LK&7`L^X=O8MmnN-mChgXw>zhe?HR(Q0 zLLffZq#c@sq}``Udo&3V`c;#@)TEy1bM#cj&P8vhxwN9#)q{b~o>8C}>J%kp1;{Lo zJtHz#o*C7vK<3t;V_TB{f6L^bp&{Rw9cWlt!p>BxEMYHe(k0EL-I{cZCLzvyHR<7I z(ms%w7cXiO^5R!b`mot84=pmKzH26BX_ALe3SG?eHK|=QsZ5h9n@LrgG(eLOu3AlM z(j??XgC-rTNyv*4nzTZbkQa+UVimASk#x<0yto1ko^5iImc;_Ur!0%12^62Ata|z@`)@7>v(|AP=BrjBOA~&G8#t&KwZMN^3W&i^0ai9 zaF_(VX94^P{J0u6Ar4Rx%Ht`qo#qudJLKf{pzTe-E4K5>tG$VOdNq8+iPIMtTv|V_k(^0a&#rw37MK3FI7kxMPUCQ#T6eas^ zTt-)i0sR~$+julalH55NI>KCiq2%Xe3}=LmAsj??lRg~diVMX|`Z7YskW+jxt4uJt zVqY<<%$^LDG33Nd99Q&XCYT(vAA0Xd3H$KKB4fyXNJ!@f#+}muig`mYKruTd!5l~? zXBHH5V9=M$p;I#?Pabq<47mkK=wwrplNCxbJLoMXc{n(DjWVV~9)Pm*z5_|_8Bmh% zJ9Wy#qv=c$ncShNm_<&lV$N@a71zg*c?+4BqKE+Y=BY|UtAqrN>{kzK;{r@`vM7e~ zz%zy$??7k5ZgASlLm@0~6jcs1ICXTuXx!#OV6&w&fE(PEz-Ftz60lLM>~kUkj^-&fHK4<{UD)YF{zuh-$^WxgENE)fr&^g-jeoKzOJGqq|6;{K&EQBlm_pMEUlV z=W2T;-@c`M`wShX4oI9>KNdbN;8&9U{93w`_6+QC*W9c-l>M7d8v z(qj$ABbSudo?YMUwPznLJ>YTZ5S*es_$%YOli8SD6{+pCWORngRNQF|lWM#0UO`aS zLB^0XF`yQ^ifUXbrhL1~8qn<9Rn};!c0KwV5S*cW3laBNf2whfno{fE(zpKFw|DV+ zLhxv%_DpM_B-QRqt0h~iC0nW`BemjusC~$Kg6r~>Zy%a{n*;fwDPQQJUFiOYraYk1 z7*dGR61$ITToI_$?rW)bUrV+7A~lP?t)&__X(+X|W=*qiYs~>NNq87L1jov_HNM6C zUTEq!kt-pU>Oyl^v+6=~yh@3;nO)=Q2{!^M$?@i(X36o&-J!A=jW^{1o5ql9P&daM zs_`%_rRJC|a@jFuE*nDz@y+>~uUxCuk>uB+SF;CSi=i?oJ$fT3W*bihye=DEOPINM z0mNO;Q*s@_fAJla)HDC9aL|HT*1mPYMuT?~O@Fx$X{S2n68{RcD&y%fOXEeDb zFjaS0C|w9 zF(ic-$DB*a{b|X$ZZ##1!`dS`%*n3KoyPTOx4fx#2h~syJROd0K1-6SW!COGM}ou1 z8Fn2i9B;ZUuWUfY%$)*_9Cz?4A_sVo+fb=fVfSs;skB3x#3P^aA$@*3Vd1ib%TVv| zd>|xiPsR=TiONw-MMV-6Rj9p6kD^_Oen+9tWO{A}8bw?npUppYalO8*{=f_BEnZM> zR_4xvx_u-broge|_%q%2bI{@Gj<}dT^45{P1P=!<6y4>;^f7fYy-WH{FkTfN0&AQt z-2R(HkTM31H7wlzD|K)|18@Jewno^_;O)N_ZvRz$b^EV{+kX{SxBptW{a4{+25XK0lmyDhXXU!6I$*6@(Mio|iR+o%gxMWmeb;+o;Hqx)k;3cCLE*Vws^~m5Qqt?1eUR^S3;gV6MuPzz2 zaLMQ;GW_b2Q45!hDt&dysD(>LnOM;!qZTe1rM|pmRA%YP;L0q;_~q&naB#_Jd*rHQ zUJ@}a6gGL=VZs%%5OosU!3*VWhoQXfFifEMn&CK>C&S_jD7(VC8bXmujrfczSD+{w zp}OtR`Y8dip4KifGOL^_|2_)?E^NY_nt%n)EHRR->ztk%+Q}19R-N7&dP!bG=G18z zBzX;)(_h16awoY1HOx-3Zgz%fn44tl<&4lUKgnyzoWnINOm3YBI99{bB(EWJ#%Wld zMJi`S4j)65^5Bkar(`#=okHDsZ@hAdoG#59uEkcHD>w?pn!a185Xb`}?! zk3qqvR!Uw&=A4uK2!TrSt_tV84zx2x@F8S47ZfnDa87rUH=H=@3z)jNDJVJRIKYhs zh7|6Z zfac&Y%l-mSi`S4j+e}4qpqwQuuFTw6m47;5ayolN&81{=31D+6;VoCO=2F62u44Uk zZUsr+ausXPFqzy34`YKg%r-3EaupkDwud*m@VYhPIiT>dLWDDvw_Jr+F!{s9AXuTi z303-Q1 zinu#fLp!+w3F}VR5Vs&8yWN=@2FcAx2Y0rH$s}*Qa*x$8JGqhEc^c*>_an^id=2vr zs|cmRU1)xakY%oMm-#c0PO`MQ%Zq4_N}Ic)kcl3ZHg{#ADsA~m-gxD%DrzISg-PCc z<*qJNxn7$5J3b@aGc>n6S%T)xU8A`b$sbS^xN8eliK&tW*IifmrgW-@EKlyanp>NE z56z-`eo;zt>yo_j%Dqs-h9qyiayJw*HF4ur4sX12FDhIsUx`^cgN6fc)^I6`5^Ft+ zH(t5dnkPZ0jXdDJQ{G&}S%_TG6HTty&KGPeMV^@5m42IfveFZGLa4QT+z%UEqgIwp zzw-nRN;KSc5Pb&$6|YC4;G6_E-5EH8mo=yOG2*mlTFD1wFcogNb0e7&6bt1MllK6@ z2kFhRk>JSxwcuC=eR?Fg;(s9+`JbTlv`G5q|3l^F!uzU4l6_@v-fYHz6XO!kb%OZ zP~1b+ADT5YkPqTj@QS474^pub#4a#Wu|_FAL&Yze6~|GL6^T;(q8oiY8N_9g;&7$7 znS$>n#GOb4Ce;?=rVN~TwPrjywJd~Bf%qs)$)6#y5rk4P26r!iXLSCd>IVe8qqveO z^qNZXs~|+@_S30T;Z*)spogIbK`i^g!Nf`s1o_Kl;D3Q&@wrs_OBr*x9>iLh;@imm zOCQosgmp1Y+4rRVHO}|vc35wQK?RLjmxIGrD#kLPA|24>)ZBKU|2s+J(Rs!9(En}K zw0{laXE4R<@etbv(ErW|d|yhsM~4B%BTGMKCl{>Q=WC|;s>D^vhiB72$X*TF5}C87YX=*9rP2jW{WDjiq! zV_@1;q6-3}0=QxfX`_ILlXk?>bop4)&IUdmMg@AM4D=(we}*Z!5I(YI`X2_m6t6N< z+DaFN%bBq=RTQ`ahS7KjE{mP%D9o&26xtnv>Jdhz@yt2~?MUFmNs~ok<|xw613rs1 z8HJg%NqYkLFEAG+gbGNF49EZwdc)-7I8To?X#Rd!SksnxkY@#rpkX!*7Go&Nv1x3>Q-3&~fL!Gv z7ma9eqThGuJ0ASuD8B`9<y&066|<6#{|DY2wj~7J6_II4ebOwUe0t4y#za6&P)x11Up{NYz>nMcD$Tp zHOx-1ZrXHBjcy;4L70kg z${<*VGYanM1m~lS|+0gaHL!`IBign}ck>%zqaWiE8AYU!M39cBU`uH@~xn zc491HmjuUR%n~ng0bxa=Ucw-88Q~#`DH0})q+sEpODXyRujoTkun^G&NlkI&Qhoua zhA5$ZX`$M*khGl%ek62^bT1DA%02q2+@n{iPDpR~HyBj=MTV-zJO|D?vp~o?6NGq4 z(PG$zXoUryI9WIEdMG#+NbDlB67vcfXQ+&W>mc<-dV`mKU z1q-wIm~8oA;Y_6;kfuFHuyV{8tfjM2gnn1LjcoWchHJStvf9bOJs;AOT=4-yFLwDd z74Jli;`KAUlkm=nPvK(Tf@L^%d{-ML!e2pr2qtglLiCV!6_K_d_+yy1e?E$?R4|<` zuSTl?({9OZoJjt1oY~X921Nm;mF%&+(u&bFH;&GK9Uk6*cy5PZ?XheCBis2OYTBF4 zw1O`+P0Qc{!pRKw-747UgUg_w1s}v+=qRgT-z|g9WmGr9s36{5&aB6p4`UZ;wsfV( znFwOo9mN`^?fGZX|IO%dJye-th{s+QmrW`jb3tZYZh`aI-5$kbQx22*c@Uq0QSsPR#B%;4 z@IKOHJT`S>JZgGikq(TC$EH4v$8o^3U{pLVmhreA_$rwEelKIN1S_sj( z+@7FOT4nA0d^&~MdZQMm!%#?+AUzA3n%(5GNu%&S25X|KIoQ6^y~T7(xihhp?ra8O z1KlYESLTZ`9-%gkb*N)?OS-aBwWO<&?9uP<{UD?oO-nbLb>P`*IM&i_XA?-yAkx*4 zt8F@SJEKX{P3R(WOxc9mwzHrN9NmPjQ*Lnx)>Z?(wi@BJRr@E$bgjx<>A_YA$L_@A zNf?*GK$~|T{%kdD=h;468M`uv0_j#ps_c(c(8_!QyH9s;$0g~_t&FelxYShL%J^($ zaL45VRKwSITqNg#fci`27U47x+iIvAG}B5J;ec#lN zLN-<<-7Eb(l+?uWGmbOdtGopW4+0V3vmXw}xYufba)ZlG z2Hc`UksmBP3Gg}%3xi2?>IMxG96EfY;ogq<2t~>T%NqbzMbnX)~JX7w0c zdp_yvgG_(@IjZT>vxhOfBgV}z?nXR>VPA$nuN=4f`Hcv&|7bBXafz9t7~V&J7gE|f zA;Pv_oC01NVbA}m2zXh9gN)&WF`0E@gp(Pgh);@ewm%PTgS9-uxqcSD#H^DeoS!jZ zDCAd|DF)FjDKz3=wSmAXrgaAis*wv^!4$Cvi<1!K#PLWGBhj-Jqho!5%(RDDyvQk( zcXrvhvx{QlIy^GvV*=!jq|NxIEGN22>o~Y9jnZp1bLhOI()Ru`B-({ zB9hGJoR9U$TTA(6q#uy;dPZ00yo*sp<8B!5N<7eQxE_E0X!j}qGejuk$gzgIBXv4x z$aYNiRvYd!8rpz0hWo6BUc563g}YP3Abtqpa~dY&ha>=>*DyQYlkf!%bK`vpU(_%^ zUYrHEOT)s9#wG;gB@Ih6MiRcPVR^ha3Xl7Wh86L8!dEq{iVq@uO~W4X-67!X8rH_o z?FjgWhIR4vgl}rt5XY@KhWnO=gX5PI?$)p|17+CVqtQsidNl{!x2-=Rt%6(^v*Xi| z#|g~hx|ki;DHzT#g%D=P6}A(c9d|K1uCN#OalpsyxWYlWIRhB8;|eDeoE>*DJFalH zk;&O{7qjC(2zZ-xZxjB5@HTt`qa*Gek(?2>XM+AA!glyjA@Cm~?1el{)x9&qfsuI> zlkF~HErM$9Tc`h)($Re2Zg69dM= z{ih>bkr>Oo-x1-e@Q+N^XCmAqyqEad2-k)W67P&~UHAy`a}jO`S0Q!W=Oa8gF_`YZ z5aGtqLFMJX7~zqLQDE2XyN`xmPmyr6eMtB-<4PML$ z&oVL>F`M78u!sUx95XDaaKEtpf2FhTpOLW6y00Q^BP+Wb?$;6a5(Alb-$XbF2QjeU zMmQPfGHdrmI6EMSPNmdT~X3nt66}gyVB?CO0DtPmPpZT#=HCD^hZCMQVBx zn!Z$v#TD^|<`^j0)XI{JE8^!QmwE7qi!0*ib)X$hT%3z5;ujP!v3LnO7gxmB7cdj> z1r_JwiulHY4U*e4&czk+O&v~=y0!7^@Iu8eE?O^PU7U+6;+JaJ5a;5G_~jZ7j&pHE z{7MZQ<6K-3zgokQaW1ZiU#sEhI2TvMuPaa$UQ?WlE8;g4s9c;7=i-X^jT%nIvI@35 z*>-Dj4nmT{2WS@~%&qKG0p#L}_%@RizbdHpr=ntte-1Z;K048j`15#sgMJ#?@edKa zAj*3$z7nly5aoRk?}1_zM46q8HN2H5~zGXjmTKOn+xk2TPyQBc)m#Gcb&}d;6*LmAhRKONyEWNPWF+I zv`o~2=xGLf%=vK0&rMYN6IqBK9EN76N(bMF^BSQ7ZFA|5X2LU z0izs9#$Q7^B^tFbR;lEmg-?vIzK4HpRMnE`CItHnsqgWk8mWhnk|K2lo@Qzjl&#bZ zyxz8vc^=AiqPwto*_=&aw9VGFZSUJ^4!r|%^$4EcH|W{WbN-yz@c#2is}oz(9aJ~bKmSW%XP=E5wg56>rm zt|;U3BrG%u`_2NMC(8ImXO=XgEU?{jS(;)Hk$vhIS~)mJCnRLU9RWak z+IC%CE=TUnJ`oi~mGeWn9Jw=x9Y{5DIdW$Oso<%;7wB5M&x6 zeg$k{V`or>NK%(M?I0qVrbx_SoJ-7b15zo|60IoAoWHLS*pB#KxEGT=nT`mCNcjvT zF1xOo-yxwgec|+nTHB^khZ>?Hi`A+SK)rz4DAcYCA|@*GHL6GLC@RV{x&^g>sHo5= zfX|{^76T?kyH`NZ9%0fD%&x@ zKX!{SO3DB`b10pm8b%Ge!wu(-Rb`RroLJW#f4a$cYtWmx=y$TUmY7TyAIL!lroDKp z+AxA;SZ5@blg9^mj6{K02EF7YH5H6gE1R~Mo<8v6% z(X@)@fm(^`qXGs?21Kh@zwRgJT{VcN}SfRA>uCw#mndl)G3sMV&z{ z2EULpNQJ)i=VbU(1qr&?2Mlp>pZG%8buQJET?=_%G%!_Nf>L@@=a6+F z+z}-x>*e2&f|Pn6-oQOkL$|7o@?Sw`G5=Q5dB}Hp2t|s>@g6;Qn->M+Mtewgvm!S3>GWKPJ*jN z)4|yXy>DQQk|%QDFxh-mD7lJjDfc=!VJ+Sm7^CEPXw{I-M;$E%!h4!>XMj@;riAemDa@)Zf2pOEw0rxflk!|uZnsVhL(FT=M(GB2Ch76A7fE;dqGsrgi zm`J&9BGI36AAxfsWR^;~Za`$4e9WR;50P;!05~7SXoBhbF~EFS=D{#kSr0L=CLia+h$0bQOiyK91gTY&lyY0h=3^@@ zWg`4bBzFa5E=$YZOEw=5(9%_eA4PKaLgwzY+zzt&c#f7T5hhT6rN1vg<~hohR)NJD z7jNKQd;?vS`8V+b?S|nSSRr2EtAO>DTR|b`W9SK96jZtcNWL!>;wB1x6cdXzak$p$D(W!~~EiSVp0nC^QXd20~FfM_Y^v@y;ROJ{A+BL88V`O7Eofc%W4b zb2q^?5V%c5903vq8RTwa6jisy#7I!cQPk^6y&@(?fI^O*ngSPa z!z^Df#k?Ts%PwDa4fiLr?9+AZ=jwovTC=#1n6I{yofVg|M&&tlXc9IK%b>8XQv#DR z8dXplsXaOpVCAI*MrVvr0?QbgK9K-xBPGx$Lxr`{u7SWIkpQbTC2&aO#UB`k(nx^y zloBY71d1t;7YVR&R04UC0GGR%S75)lj0NtIG!D6Uq$D*GAl-XANQn{z)m+aF4y0;Q4&lZ&fWye?ejPt7u^EmW zgpc3WJ-8Xp=4LqQfRe{XxMq25gp=~dhv?|y;Mh#as~vAR|3glaOh6Ak`du{~LI>=4 zvmEg&62h#OfA&)d@Dh6sisw>$ZWk=1wik3jQ)2&ubUMZU1@5f0Kk0}n&>jiN)104N zkeoBwJ$L4#k7_zwlE_(SehT4mX7HoS8320Bc@YKKb^eZw@tpmLsqbvUGsD3Ix)FC? zDneuG;5=m`;WQMYadj5))5IAJ_mj?x@IB@9M>w;bxA6A0avp;(*-jpwt)0sdk{st4 z*xNX_wno$LEJRx5IlB&P7O2LS%H+Pa<;(7YUgUCNsaRpHg$D(;)rz*Mowrc>55+De!|3Jg zMw-+*1Muwa`~&gr>K2Xd9&3EiSWCdIAdJ! ziUmKtkQ#0o9(n>W#;IScI&Tz6o?JX>y4=+n<9b-DM;@0@c;l(W!vpkGps!|sGe|!d zCSC<^g^^JMJ2y5->|*f-?7?XBDgPCu2=iV?$WR@!O1}LB@IgxoD4Ky z*04O}WT5$qh7}}! zCpj5tVlq%+FU83~6O(}o2Pux#nV1YzIGN;Rpoz&qg|m$;P6nEo415o%ok8jxxS;da z8xMPCxrs?Tw)-hg+L@TNQ_4n)lXfO1?G(0CoU}7BX{WH4`l$#QlXeORNlx0Cn6y(k zndGFMiAg(!vs0Y3GcjqWaBhl|b|xn66wXg_($2)B9fQb8yR5HJ6_}W`o6m4=Hoq|a z8oW?4&Hfpw8L1QTf|_4N*iKzUt*;~OB?k?Mv)@EGNZDP$|2D$OR5xb%z6fWhHsW

(s$6Ox?r6xIe zNMLMN`ae45^4&2b+?2WsRgh^#ctQ$eXQ%`$9lyz`9~plq;!jK6(-Alp;aRDG@^0kc z+|=J#47`ZHI5~)wf*;|fsT|5@MDoj1YneZB#pkx;R1$p|Gl&RlMCyD>BqG8(k-Csh zgc0FAfR^N>!d47!ay;VLnV)M7>kd%_jAliU+- zVo$ijC@k0$ZemZk!a?c+w3H_HgmZ&FmZ+s>pa7cK6RvP}YA*5W2kmz($wjU>Y50br+9RNi9O+pUy+*5!n!unuS#-HxQRXC%Do;* z&O(~l6RzZIQ^zqGuqRyMI#qbFCtMYdhSWmVLf8|o^cz)S#h!2`7WRavE**n^>=b9xP0XY#@!S+=(oM{yE1aL=OuC7gbcG9( zoJlt^ldf=Sk~8V%QxPslzQcXYq$_?!k~8ThX3`a|N^vIL#7w%vJyM)WH!+j0aBYe+ z=_Y2<6|PHhCf&qLy21@9&ZL`|NmqDqk~8ThX3`aIOmQaN#7w%vBa@g(H!+j0;OG=* z(oM{yE8LXgOuC7gbcH9RIFoK-CSBpls5+7Qm`PW78gLC-wFu8LvN)4&VkZ4&q*G>v ziAnT4WPr*wOrk42ookpxSJ(!>JL=L1dr3~Bo0vpb{2;|ibQ6>43MW&XL^m;su5fme zljtTU(G|{3auVIdB)Y=+s`z3OUE#tcC(%tzqAOgQc6YD{?tDGEglCR>hP7 zj@Hl)A0TYf&^cp2f+ zW*09?Tr{UnRi4ohXVPiNNbxUlUh9koUe80qQ)o^r}iS{XWhlWjIYm|i8of=LE zC!;}#-J{{;unS(S*!>z#3putIdr-q!;UCZx#~#*jZdl9o{HulwLL7)=#2(jhad@}~ z_@stQ!(l87J2YG#b|>7a;mWXyVSYhER=eRq2Kp6^*NE^5l)~7X8m|-KLVPvE_Go;* zFk;unKzP@j!Mx3OEB#H#+r((D_O6mroFU_a47a<6cKH1ffQM@6g@=s-?5$xC{(^Gn z)@hhDVmBhc+6u zA9)aR@rXB2!)zH=Z-|DuAs3H$BQ(qpxp>4oT*JbUi$}b%8kUA!JmQVhusr1A5pR-) z6-JCFb9mFtYY`LuMtgI_RS1o9JQB!oI7i;*l6n=I|Dp^B8<; zwUUcRymOKlpzO%`XYafYv@^*${p?*(z{KL~#MxzUeF3WvEFO`Q%ihKU&iI%mJwq-Y z@iukXBz0>;E*|kNF4`txUC6~F-lZBggj_u0U9REakc&sWD>ZBkxp>68TEmec7ms+? zYB)ON;t}t<0#&Ovg^%I=@op$k)zpNLi$}a0HJprPBm7cnjibh{LrB{20ool1bGFS{ znwXrj-e!^#RQa_&XCFc?9`XC=L^nb%9`XBWXop-p;zxP!gu zU6c$i9`TPe*|-Od{^S1lj0sm1_)iwo9_6V2bP*%T9OdE>|Cu6{ls!T&9`Sb;|17z+ zGQa)ji&TEs$^7(I$b(KCbyUgE>tg0X~@G(;%8`XdC0>};%hXwBIMyF@wJ7jq*TeW5MNjLqI9Z< zEDP~-HMch8;U@9(i&QzP3!h^uT&Q6~IFfKfAyX4;P7*xaBz{q0nS2FiC3v_=e6xm2 zQGD2akMVGm__gK?=mfbzrT+vY&(%mla|6NENI`Q0!PQ7Xa|6NENLUZ1VjF~9jfC}J z3MNCYMhY6EtT19+jTDTqrox+C)iDdO8tE56N3KS4jjg$$#N1;dutC40?N3KS4A=iitR;! z)kwMmNpUq&fYnGDQodh`tC0e%MmkN(*QdA|DZpx^%@PkzaWzta)ksUEd?U&NKh`o> ztTW4|J~2(}7$KLkB%&(A4qss4=4!4N-j9|s5!Dev_&I8j zMAU;$hDlUai6vS%JIuk$lUSAx%?{*NV!4L-p+oK|8Wx6mXbKXiX;^B+29yAwZuLMA zV8_F8+|qe?6B zMn3a`mDWx=_ErHC!z?M4l~!U;`*Biuq^z_O@8rvY;gZqe15BRx@<$*jX31Dthb2B} zuWGm^S%)S5riCYjZ{Vd)e58dZhWl0n{#|n?hn-NDB|h!&i}ZI|_!maYBtqHC!Moyu{b-RfV@$R(OeTHC(Dz<$c#)y#~v}JxGhh4@I9# zk5-0<(&e8dl$~dGZxX-CcGW7uvCP>vKX$Wij%DYFV-bKhe1OslVav8B0c4fY&1{^5 z2~r+c*oBojZ0OQ^W93lzjS!VDgoiDPu;<+gcQU)>kdCs6ZX#FM<#B~wW}k?PLc|qz zd0b(aIqX2Hk;fHwnN6A+t+31E3cJkdni{RJlR@B(Qu>{Ab79Zp3cF-w4(Tmd*k#Mv z+_qw14Jsl|tc&T8Xd}0_wG(F`Oj$!f%oiT|1hJcgR`NqwtfdeiOfY13d$Ao3xbM3{ z+(gz8K3H&ZY}0r;9i!6^lPaBVD_$klA@%KuDixGgd+|?vs<`jLz3UK$h3P1ab=?LSBDr0 z+*fCGsAV!dB&rA&fQkcj47@m)F@x%<%3af|Xr|%TIr=4rt0blv;RvSe<*0EB1eeH& zv*FwOgArzg;w!i*CgNMQL!1FQTXdsu4Rx3xgi$GbPC8{vuy@VNg>j&vQfj@B35koe zjgm@m2Evr2xmzRdG^4Zv9HvMExGF_#vjGXo6e*mbnFlivW?cVZh{F-)LWG&&z7Zi4 z7oo4FQs{6|$uR#5)K6hb218^5%q{6qjEh1s*C?3?&LWtn)7)thcY#r|8l25AAEmjA zBJN_N75kMDcd1dj92~w?Mc^VD$eE~=U`bi&DscHa_Dpk8aJ0r)MH9nY zDs0sXvm>Tax?Rhkp-CfJ$QM4V<#mo1h)-F3I=3iUr}hKkN9dNxlg>Je&IC7tdNqtJ zS$r!$P_E;q4^QR~&L-+`@H-nw4(?V$$>Q3cPGTc{!-~``g2k^doB*a*;d4U6tD9cVDWX{2{sbT+PM9|*ZB(Y`8vPf%r{E+fyl!9iz22I$K2Rt zlzNCSnQakWRe)9ckl8T=Q@-n+#5|_a*5+6JawLU#3`$+tmiaL;t(sq z=QYgsx!A#aLBm|1iyf>NHO%+9*umPRVWG#x4%SN=mU>+5V7;tixzEK8)+-uT_+0E@ zy{ciA&&3YbYZ~_Ox!A#aUBgtG_3Qv*ui>J!v=pd;aeIG_PN->+O1)uhj|)n zk4Aduv-P%h6Vl2JtattPCen`+!`Ay+2oO_Z)(09Q0qMkt8hVEHU&sV&uk|rfK0_WY zz6ox`se|Bj-ijskJV`y_#BCk_17@zb0j`CP{VAWALy|m8s_>O ziI0uYFyH4$eC%)y3w@5n$Hr<{>T@JMHcrEGpCj?HNgC>HoUv)~kbOcBO`mK1bqXS8F)Z=SY0)S`A10{8WuyS8$dr&rSYgrGPgS zsC=5>b0j`?qlP>qo9_V6$Q}YlYd%05gD_{w6{K<-XKb5Eid*H@`t9(g<#Qz7?V}Uj z@HrCi_R|ojKp}W;l=q&`k$5-C`@rW&yc=b9(&tFLJ4Wkf`y7dPn>5VzITG(4)k^KT z&-XbJ??#zj=yN3AouY+HeU8MtGc+vsITG*A*1CEdr+b{qb70)0dxF1^F<}{ZmuVft zKeHC_Bn@r<1#(wt==pzU;Lg-AFsv*l${Mp19CCBrbNqMcVu(t{JumIz8o~?GF190F zpLS7tzcF&r=c#4xW*y|D--JGwd#UDPHzu$3b1yTwDA#RtANMD_x=gxH7SkS;N%!d@ zW)sUK=Mvm!iq4XSp@+}!M|WrO3@KbIORW2Rkt(ruvc$SCYT*W1kldFv9E<|NCJTiF zPRfm_?jG|~c#|V8La<}2usMo#k+=|!x26x^Jc1C%PK`K!ia4!V8k-+R8}S(g{r&j9 ze~vPIz$c!0jpGC1dd4dmf;uAaT?mR&ulaE1L<0y_9{RQ%=>)4A{jLVJ8%#UdZ!Pn3 z=;TBYCcq#O@Y#!s!^j)Z6FRM0IJXddaa!8BR$dP}w-M9}V3c#Mm2(e+@BoZ-ZjE&A zF@#mT;5LVD5BTECv~w@GRdmiDfHPgv&b{Qy(47wA$uQD6HX7{>{Pse(K%M=k4_a;x zeTTonEpaNm;}AsoFtsK>7lTHHGTNuQof&O08vVE{nQk*(m5g+lKQ7@v9O7-I_)NEw z;(taM?uUWWG)CvB-%&avt#p)9`UnaiP^nmSW|BItDh>37zhEGUPp7pUx1L^21{J+J zqp(`(OrZo0*vYc_Diw?F91K_+Q%>z4flla1Tmng_%8@=Q)N5mPbSiTY4jTif?N=C= zgU&=soCo6RFeQHwAg+t4MtUPpXXo2rDsG~`(_#tn=y1b(9EK@!G&EHLPKzC?6R=cl zVOksp(MKRgaf&k6mFQuy0cp{xbhQqmD()(snWIXyF4iwCx{{*ZAo?&|q|0=bdzqDJ zw^(m2S|lbiF^Xa;2k(a{RVbc`T2ZA%QB3CG`-t+}Fi63R>HeqAftleB261Lu>rcbIl#7}L+3)_j|{fN&9vEObjD1vhVJQJQ*?oBx84_($5!sZK5396kh})G%%3 znc7pGMoRn%gd0hG9%UO2P2ih7VJKE%!>Fv9?&z#q(2;4#Dy87SL%eamJ{VRfh zq9ofkq9%fASIe|{L=me&=myiN9Nsc}&w;OaS9vaEr)xlCeRp*W+RLD^aNX5R>-Y_5 ztctWAUb>g)#b*1!EMq?ZkdD-5Tb9eC;Q1&R7u*WV2Xk=;?{${SW+CTQLW)YC9+|JqvWj9}XJ1)&#-^6cw3 zlAh=2gV_&1;v9#X?X>lmpbQO$M zRs)0a3aC3_l#i>dQ4B`rVaRM4<>PAQ<0udY!C-}$;YlCIYYWnxgSFyF?c=@hk-jp` z=che9(&|nRZ-5h5!XTJ$WkU&9Ps?U+HELffehQwrE3LKL>_M#oBT=2gs5F1uOs9FN z8glvMp!);fh6Abw_(asu0o388YUtywgGAlTNc1gHrA3Ryi_FO_;=r67a5#ufkXK2# zMf9Zn$)GNTDVOj4^+LY)DnA$xqqBIA0T`$qV>83ZK1autLj#3O8v6+BO$1d{AcK`d z$AEYgOnxJD7_E-8U}1|Gm3Tug%s1{rYU+>nGIYCme%U%3-s|5kd^i2S_-Ob4^U;nf z_&*=*D4hTKX#dYgJ3eRr^U?nQ=%byVyjR4UKY3~YAAj<0k;4BMK6&NWexcXPAB0xX zpMs_e>rvV3U{FrM_yN|VDroypk=r~HayP~gyhhCp{CvWZ8Yca(C_F}g{Ac^e(Wwa< zw)QuXJ53Ac`lHF6t06Ag+C#S%ns+0XZs0BP*D`P%X7iS6A&g8==0pu`|9y1FyyY5V zbaW4WSYeKW=E0xzw}aN2DTpt1ezCYK%|M99N#z5dQ#XOxM)1SOJ(aw7)4VqFBMVnJ zfx0hEJ$PuKJvs!^hvrcMY5TYD|G9{S$hDilt=6G)A$T~N`u@+g4`o1a2lZwc^}*iO z&Sf}X1K|}I+1F$Ujl5eBX%TPX+$Z3RXVcEb?S6DF7=^TfQO+flbG<<54kMl0LFd|k zjRX*{Tg{;x55CCbcds0sc-`tv=T?DwB8+nGEh~qidlrQ4Fw!}uIC@AtY(xCC@4S&c%Nwu>00KUy;>F&~84Fvua6hyqcCawA$Dc95G_LrDCVcJnY(2K)<9KY&pmu!osPQsSs1@ns96 zK41?sXYzf24TPs*ise|t;ZYZVK?y_5f?tXwngg#yG#qgC6H}7v1)?>xCikG^!PEc- zDB@B26xIO3e%SL4RnUlg$F^n52oYNg^STMj{>j~pEr*&5qBT-HNcFzHSO|l z(Lk3!g#&NFs5E?A_2I{iLwsQn$P4Mxrh{Bs2cF1Jf1Pd;Bk0uapxz9lKFv0XqZ!B- zKzJ5LeVSb?WcBk62%p2qJYr3dwjk{57{y}_@{wVmllJf!(T^ThjE5$S3j0(Q_RS!i z4}+nC<%hzheFuIL?F37_1eZF=^0#jQ9cptFdb}{@GAqB2KGr(Rv4bCEke>pZH29XZ1p}>e@Ehcu z9uc;KpNV@$*o$Kl(K$4N0Vf2VUJ*YX=*x6%GP!w05x3TH$2Cjn)n}S}U9# zaHF+@jn)e12Ha@vV52q59~MIg+-U7!qqX7}2KQtEW23dgr2#iuJJ@J_iFf%Yj2NX7ONHTy5 zm=Hlg5fMc&pdg^AU_>!TOo)nziW$79n6qNM-s}H7wX4pVr1!n+|JJwGx7Isr?K8cf zy=&L5(A5>XtMH+<@KtesXdS|b*1~s-^F!+pKD3tjddB&obqF6?i@bN7A6kd-p|$Y+ z#g=ZDrId}uAeLKWwS)**aoEx=+GzlH!lv=#s#T4(Y@ z>kvM)=6>~9v}M~9Ua7uCeW|fR?rp-27GCY`gdn{PPVJ1Asuh~Nzh4H=XzRI9N)`w0 zBI|LHeH$uIuwPvA&dDB$vciXF!ur{tplaa5Ghu`5FUfW@Y&`orvilo0k^K|d0}Pv+ z{X5w{hAnWs&ydZ*L2hS8Ulr*X;TR(OD?9=sRYu9l?u_N0NLR!9*$?0uh>x9Y^aDMx zy$l=A{-^=i-iA$NKaWy~^fPR3&alCQoydTECekfM^xvaVi41h_WAwR^A(4fQekUy+ zX2Lkxo120iVOT%=d`b^DY>>Sf^)52Tu<`6WU}dvm;l(`Wxk|zm1WfdHSamS5Cgq1~=cQFAddH26{Y4R}}eFKxjg{ija3E);@^s+0B~6XDMtsB5f-b))Vivg76Wr&(D>RWTGEk> z8rFEYC?3WS2e90g@3Tbmefm(WPNA@0Eh`<+D{A})5(G&l88xg4yDc^U)FuA#rh5TD z3ilocm3$B8bzHm(Vic@-&D1R9hU(%=s>hFXg886NprVe4=|)q)U5X26UfTm;Yopm8 zIJLuL0aBsSp;oiGs-k97quC8OwV46U)Mt$Db5Ekfd04?VPzxGqhxV{^7sX$Cy0nJ^ z9RMo*K)`(F$zlNW2|mx#`O<4n@C5+R5bQ%0QP|z9fcVFMA{qOXD)D7@S#-P z;-w3b-W96GgdeX37pY?iUtA6DdNhFUQFP=7GN~7P&FIEFpyz?g8VFcL@C^Vj5X=@M zg9+|`43?!q<@(jqOT1jxOuUfS0y6!_4Smb?ONq<85L-vSotculh*_jJTj?05B?Ee> zMNJ{C&@ZbyZtn`dvV1gOlo6o_f|LN|`Ur&TH4K5+Zn8L7V)NjgdYmcL_4PHkC+q9$ zKpzE_jbI92bH^|-(~iZaL!eT$a4T51hx2ZD2~ek9fom_WM-zTyKL^#Q=CS#h8VXO+l%$~ z;vsvn&t71)L((|PUW~UFOYFrB_TmA1vBh3=Jj?{|YcD3)3(O3N<@@XfrUeA~-Cjh8 z8Kk|vIKW<g*_*?vVVnVL+Ss|i=Wj;K5kVZUGh)GPpy|d39SU_Q^*uP_wmrJ{uDq&zu}2)^*IcL zvu@a}_Ry^s-iN#+-cYoB5M{U8L$_MwaVN%ZwTEss%?HapbgOwTDZ)7(y4BV!yVV}L z)y8a;-D(frYT<(jyVV}L)y8a;-D(frYT*-6cB?&ftA)>vvRjSA(+pn_Ww+Wxw_2yY zv^dIcwTEuC=$AycuZ*%=?V(#Od{va)Y7gCN z;k!lIt@hBZmiT%`*{$}_trmIjD7)1jy4Aw>kFr~h%{xqd1EcI#d+1h+d{~s-Y7gCN z;YUT;t@hBZ7Jf{W-D(frYKiaYD7)1jy44~d7iG8FL$_M^@lkfGJ#?!jeUqZ>R(t4H zi+ox{zov?AweZuU>{ff|R*U}GQFg06bgL<6w>rvhwTEuC0P|Ip-D(frY5^9iD7)1j zy43N~0jnYj0MrmfvH%j|LsR4H-c@!53vnz?@my_6xrxtc45!O$bT}gxu5@uHtVeuNB z*_DKc*uvt85x#txxB}i{R}yP+4cW;li|ffwHEfW$mh5!H!r}@%!>}vK^R&oaNj^s- zkTAQFSc_&?61tBUB+RZPqFk0RyOIc7kubZG2-`Mcb|n$EGGTTl z5wqnNODCSd~;!%&a0D~U)4C(N!S!VXI` zK&`{BB*KnLm|aPP9g{G-k_dZr!t6>S?6`#4l|B@yYYgxQsZENgnAFP(l}YxBd(gxQru`Ed$b|vx5 zt|UB7Fsa`S%s}s*VwJ59L8Gs>;(akzVf**t2>=J9h04*-xfjDavhay0Xb@T&$N35M zBX!|qtCvt2)S_B;%Al4wrOQ?q)A^~j zBE1n-R0RDcv46VQ-vadMdhNr`hxD#vEjxQ@=WN)?JD$;W4EH4yj7O6I65~~3ygh&x zpuh1sC4%$3ff_1){ih~|q$F(4vwxj|-do;kk+x?sT?Er7FizdmogC7oG5aKB7$^rX z*5Rca0V^h8IslXtF!-qg?gg-w;BQRkQ~}pa#2^8L@!SULuBi5FxN|Li%y5eb^+TCD!!k3r)lg2%+!ts6>q1Wv~G`pzYElO(P$^Q z0rW3K+(c*HBOx~R{5COn3+1zxEe$yVqd9Wn&{opQ4xf@Ru+$hWY(A6b_lrz9Q<&tXb0&)hJr(6o}M>zw` zQ!a%MqMQNdDVM^>Bb))|DVM@0BKDL^;d7&$0p=-}!WTsCDVM?*N9-w=bdfW_sZ%bi z=x3QX*Nq(P!cUxK?RfL79h}xUq@Ux>x4a*1MEL?Yc?6VkL~L{?`HO5HtRT{_FZ{gN z>K8}%qkN&|OC+BdSmzUtreUlxocHZ`m$=?8I-~oydKtx_>Ktx_>M2rTe!cPxo(yPxo&nzI6XqN-P2^l2YdWLC|ezf+d}&?$q5aoQ!XT?vdo$dh*!{M-F zsrrdZ&vJ!N0q{0-^R(_Ks)D-hfwlmlNye7ukm4c!D{VcC2^r>){hQ9BQ*o}t>)CVizkp=LLvv8;~yyYC8<>oqfHA!_doCD0_Hr%p*D;Ghj zW;a6x(Kx{Wbks4v=w+Y6KMFs!rgat)KLbD2SGDa*_8qSGyo$V!PHzw?M{D+i%0^d* zPx9cCEbuR?Y)%VdNEuWiN8ae*`F`*PbNOQ%%Vt0Lj=(1t zc-9YoCh(~Rw)%md?)gj-;+1am1Ma8jeQsmf;Rkwx=L@T`(+|#IUVdpc-u8p_EdYFF zfn9#^9)Yhdu*VN7&~SR+SYWRo{DgYteQSZw{GfXS0N+{QD?ez)dA08?@SPv*WR>{A z0{i@+ggN%3%068u|5rbV()E2-xw=1(t_`r(*zqw!pQapoD4p#R4ls!3;b^ zyk9M_CKR-0EWg?0uL}ilMF9M6HLx%loq)u!V(V>(Vvf%{DmsrTgl8I5Sm_7o6VQ^z zR)TW?Ib`+;Xh~Nq@$r18gg}(HFe`$#W_T96=8qOR^Fi}j!q2sQ$ccZ-Ik$f*?`qi5 z#%{1etXU^~%;|m(0DaRAj*mHAx$W^bXayX=oUUmGAn)k-n9~(L2so$fV@_B2xD)4` zu8%ogn$KMBV@@|OL;Acv=5(!D_IZ8ud5zhCbGkm}bd6a(r|V-**O(1Br|V-*SNKH0 zIb9!fy29rMoYVC&rz?DczB_%)=`z>wszks!T_1D0A}H3({6?tXAIb9!fy24iloYVC&rz?E7fOEP&=5!^#o&o1{eaz{Kym!DkT_1D0 z!uQv=HV$qy@eK^xmO+j=U6Bt9IH&7lPFMI*0q1mm%;^e0M&I~8=5!^#qXW+A`k2!d z`M7{{x<2M~g&(hPavyWLlD55$Xyguf1g`ci(c^`ASqJMV4Ib9!fx|HkI zi*vd@=5z%>>%}=;A9K0_p!MRMu8%og0nmDJPS?krt^nxs#yO|!V@~&HHnh)M7)PJK@_fum)-Tsqj9Pl%;tf}e_gzSI34UQO!Z4|kd~<;%dYskhs2|c}7Zz2aI)`=av)U+5M|0Hs zwb6%&?yQae%6xpWHd;X4%{9>?)s^T?HS7BkNT6OBm-kk0);0TlfMC-0!lYd1D{x|DKJ8+5T<497^@|e{pUVx6boB z$iM$Rx9We-tr~^C;Q!0#R{85avz37V-wJ6 zaqmoNcrktQ&Rr=DFLp^8H11Am_%RM(+>I)G4x&dae*BPOj(d;FUZeRr;TT6J?!7Ae zW(|Co5#t!h-K4UaTsT_nWb%s1%Bn<$;sh?HHSP`SIU~{XZ=DRv zbf5=t(SVlbxlZB;j3?atl+V@N=pC+$!Ey|byBG({E(XhbM=#_i2g@!7%eo9o{TK(! z?n{;rVjL{H7%YoC9_L`$#b8^KL@E(XiO&x&!d>|(G?Ue`trmR$^%=^zKoF%Fhp43-60sHCo8usj=4 zaIh>D1%qYLm}BZ12Fpvd#(Y1B9#wSe96J_%RNaT@02*W2YbEVA=iBYP{{oI9PTuSe78W{1^wzE(Xg2?D1n9 zEV~#i3$WLZ{e=4HVz4a0XMT)>Wfy~G0lxBM94xySEDP|RALC%z#b8;0eSVCCWfz0x z8?@`c`Y{fcT@02*gJl)Vz4a9Ul)pTusyZ%Ti<#yCxdrXCUcnk-e?eS8I|BVgMgMCY9$^{ zzovwMmW;O&-w8%hLO|chtO(kg;aTjOKU(C>2hC>*f0yM$PJ)AF7lY+z&=@2WIAf@Hioy1GM0X*+{k0P#Q zTX%UV!v1CKZ9EFxt3yW5#B)t3Wp~6-+#c6jK8Q{43;h+AkH;=P5d3wPPsC1RG}l`` zH@1j=th9VVY$oNaEMFYElJXlYUlN;5`D)9T#jc}#jpZwxL?;4kLtYLGH}JRP;gX#Q z?-yB$Y0jM6O7M8sNZX?NaU$^kxcb{wW;o3(7n|g+MwDy&MKr93k~fU_#f4@*v}8))+u^SGv>^Gda}WgNmrGhrIk=ruI`{7VH;JMneU$3O=_+!sV2 zzNe>;*YaUg%IM>&6^)(_?Ne#=$2vxzQC=~(BwY#dwc2Q*I)(|mvmS5bn2iu`?^JDQ z_<4kQhKAe01pm_BZi2VHf&KvTH`;JRby05^zP^^X$ES>5uXGkPJ`2<5phk&0M%TjI zra%Wm+#iGin>vVjySSRssSv0L`Xu7&VpUF8mjS&TRMeh@vshKJD4qcD2*K~f$PfnG z17H`y8w8w8&^;R~IRNnh!?C%@#;@RZdP}RWzhHrYqE2XBo8Zmm>GC~4~4kd^CsCY?ePzbF;SHDs@}L9R4t*bKr;}cU?OY5Ak~Qs>RXA= z`>~RM3WM1XZhVVockwrc_(0vXp9=&KK0O+8!ODqTRGw zpqfy%4Ea?8YF2h;o@rgD zZ=eX8@ertVwZ?`rr>nqMf?7t|j@%L_c0Bm8pbA#*#}I?hpUoh3M^59d`2QwuoFRx2 zH&5h8Ox?HorScarBgnX#ahmRc9t+2Ay3<1Cv)(QVtL2c;c~)B%aH+n_m$YTvS0mml zL1k|uZYp~GxeKJ0d&M6Ed{!wbWp5C_fp75rU>sfAzMF0 z$5&g^y!S<6HIAR7>5hx3uo$7i=s%{4cetc#aYje#?M8~;0o7B%mS%+Nw!Q9^86l@b z5*5syM9+ASO2m^gI_QWyHO4xOd$jee!{bciA=G8F+=e$B*dENFs=d9z49d`Tt4de2 z!NNG5KSwa{Y_E~>I!{1Kyi@h%DZD&^mt9yuoTO!yV$yUw8_dQOAV{~sU2&nmqQDLz zh{qX%Zl#%8{Ib7HEe^vJyZ!5X4V3<7YSI1Qsm0JfOlmX_{qNM`|LaqWZjGtMn$wBZ zXAiO40S`6GsKQUs8$Y#9x=;8R_ud3tk9&QLd$p1o_xc$33NPbcALCx(W!&py+{;Ne zj(amX?)5S59RnbX@ofg_SvKV)xP3xK_atF#e2{Q2RFMK7v2Nk>52sz5SmT@{TVPo~ zc33}%FS2|PdyxFamPe#Gb_7R1E1W8f$-6QauYz)tFUD6vUAziv&GJ=H7q5Z}@5dTZ zj#oiBJBU|7V|*3V#jBw74|8#Gz6$E%RZ!6{j`3Ac7q5Z}U*cr(f`N7VJTtY(S3zC8 z3R(_9R3Fv;Y8bD~F-=$&m#|K3W(l;gEH1nsvq!ZHAH?lZ?ZU@nTo&h1?ZPKw_NaE@ zb7Nc<=TYs#7sxyumc=D4#W606^Qd-_m&CX%&ZF9eFN<+moJX~9)M>AXaao*4wTrwm z#$|CH)h>KhjLYIYs$KYQGDVDKafz>I%pTP)^4>8ni}R><;rq)Z9+t%=zJW0=i}R>< zkq?V;S=`04xbUN5To&h1?ZS_d>0~U6OMFMixGc`2+C@Gt#$|CH)h_&ana;zqxWqRp zW{+wY`Lwt_s$KZ$GP#FkanV0J#$|CH)lRvdr{uCYk7^eH^ORf`=TYqfV4jl8;ykKd z0L)WzS)50;3xH*Dy@LRcYQL8?P-a(n*d(51c;7RQr`mr!jQL}fs|gbBs19V12K^jo zd}uU&qoIrOt3p5V*9ph^VmzNL*6Ki_L39H4bBUB!@*_iK}DdCyV5TSvLlhh0@6R2eBsC~h+q^< zP`!h|BFWah`oPC1P<@+1^VFqi7u4ulA4TM;sRsc*xDNa_+*V!dz$2;Mx(>V^nV}lj zfs3h~T?cMT?Tk9`yL9m1wFa+wY7w=6ssrQv8+`Fy2d*UiQ5|>~jl5e6&Q~up%2!Pu zqN3@Hz~;w}H+_e^2$nbVk8e5tT6Zn}DtY6&~Ih;xkm7;5z``Aox4I zIa9#j0Q>?fx&y}cz)sN<<^ub}ZKug`Do@`j)l<|+JwO`=;@tt>clIxS0l??z%=#W$ z+?97l7ocrHg^|Mn_EC8ZvJAkb1m9;IeN{thz69U}5Lzb;budc@AGqDO>QYbEM5+IY6Q;Ia!OS5eh9fEy&)W9E0I%ho~wx# zt0~l7Uo+#nAUgFVrzIWy(HVR>|22oEi$sx*&IXO9V)JRZVtep46yXm}Vro7Ukj^o* z{DdlFn~(iW+qz;;wR?!7w<<5c^%XeE?t4F$rS(KKtZH9Jh+R!peW zvxQXkw`|dong{ElGw@^jQ1%5|LTf>010}sV)IFBR=1`Q`&7p{!&7pQ$6>JXmELF_r zP{h$k(mN1^QG7AQXxpp`xR&lHP$x`1B4$!l!p25nBI=y1wEwrarh%@cc}-eLiu%hNG9n21V||W%liZAR3}y|G|P-_ICrp4mGTwoiiBh zVTKK|uRj>1+QZN1IL=2P@$k!#_ONI!08l+1eiy3GLshSbM9;3{Ay9ajgA7$K)Z^g; zA)ALUiHC>6k^Xc@=iy7@;duaN)bHVrdOh3|sxJ?TUR}pSqLb@G;dk+&@Owi&exHVZ ztd#xj;`i-v@8*=>w~ODq0K8eh-y7@odoz3)RL2*h?dnD4aaFCRDColP(^1{kCH457 zz(Y&?zEu28=*_}vRYS5Q4Q;);6xUQ@5%M4Qy{8z?;doH;wC9uK(}j(B*A zcz7xtnV9nM6!Gu|0N2*<;pz2yIJaI8iT14HA<+i)q43+~{obw~zo+0yE`IMPes70+ zTT_1TCw~74;J5nyuBzAX{_y3yI=&Entv(bUUcmM$%XpZ3EOs{rvAv38Oe-EH#KZmO zVG#i&WuFia#{oDBq|2VcJ^mDfRG#s$gbaTwcu{UVYzxNWPe+S>01vwmL8eK|LzhOHpYVUJfHOdajq5np(~mWSjiO3O?uE)mkfXDo6-{5T^6CrT zvMCYVdYJciqLy3F!GJ!sCcl!8*@WMkZhZ~(V^A*6FTxaoxYg@oyZ`_y@uT+=9CE!2Lp_0|`BK;ouq#yjCF>`6zL>>qFS zt1^*|T?c5X_ID-XTMo)?M}NQZ^xg3VfDb{1bBrIXp!!ek^J0@=qi7it=YmT2=zB0OkHU5a3zj@DczsL4`hA8~&xET2$^?z06d9ER7Z-sblL@ z?_w{zo@|N2Lfu=T3$XQ9yP2tqr7u#AJ$pY$&tl%=x712c z_GJJcV|um^(qdiJ4glH_l=}+vV7;X0P5?K73XiLE?{0K6SHeco8Ib%8m3^T4s@f*w z<0EX(8mgmcy<;tpB1-^Xj%Ahn(}rlV_NW)oR-oJ>W_y)*6uun&C4hw!>*R1xH?uw8 z4mcN*@1XV#$f>82_H#4q2|dEiJjI3%U4f?=sJ_rg)*E_~o2lPSVBAFrS@0L3r`8*K zuG`=<8~1()+3qhwFLWFHO?lT8)$IVVPW&I&L6NTF4RA9ib=jW%ahwy(IvzV+A_?jd zybqSYnWN%%9%8ctFYRaVQ!74CTe+DpT8>M20`pd9h7p9&T;!fxY)rHkVM$pDTIs zy0N*E41d<};$36&5iI$Do^2oEL`~n?1?!XCN<*Rhc`j%^k3}J!SI*iup5v7bh8;)5!2=IxkK!HkXj$ z&vm>wUp1&e{^_)T40|7?Y~D*Te;(k)d?i)oX)^rT!i!5)gMufJTwSss+KW$cp^Nwn zTJ4M|;r)7h0zWE_5{*XGQbv#X_sI7#G^kMk{*TUhJ|udvHNJcZKOT=XvjgdLEKfz6+0J|#d@kaY4#!R87GxLc_SP%ipKOp~A4C`3-JP`3 z-DF=*u`iN+G{r6L`q~&Cay^P8aWLoL@WLKrw5o9kaTlc6V^CV|@VE(EHjV6{m|;1T zFCQ(C{w~}p>q4%VRbanH6ne$_@%iPHEu{VSR)K@X^1}tvU(7pYpEBW1tpZ2C<+so% z_S+E)dE^pSf#bRI7tj#{WE55~`L0#qxTt(Gjk;FhQd-!D*KcXi;{dCir^W&@shGsv z{=_P<%U%8^>%k{hVHoYbW);{SEw7-$Yf{mjJmg31wNb0 z*V4jm*223imqk{At!MdFbZb$xm*m4}x;)7$aN4c>nQRS7DoUTBdO^gN`|V^SDRv@b z`yKDy>P#rzL4P)-Svq?~itWj`rdYPcdo&f`wPKHVYI$UmX7|^AmG)-PZ}5JnHr#R^ zb>HRtou!BKa;ud%Ycs(*<*iantwV;&Qfu!htBU;Hz6nbI-BK$)bv+J&U9<6#o57D= z^?e2sbSZ zW79&aVbvntSNy^6=Mg3y&xd^s$f-UmCvm&3y8eXt{ZIV_ys z2Rp*=hr{W8up@jqES%m4JJL1+KD`figkKYf@p9N=ooxdnd^rr8G8lh`Mfh@9IK2;c zgfEAM)B9jYP}EL1y$^PTFNcNG`(Q`-a#%RM4|XI@{q#QA5xyK2PVa*q<;!8=^gh@T ze)$>3%VFZ**%7`R7Ou7rc7!j7g{$p@9pTGi;cEL}NBDABxY|D05xyK2uCotz7>m0{ zq9&VNt}`~MHJ;;S>c!p6YKyxWcX$gRu=}SJxCcfWqOLdK27qp#xD>RL;0Azhf5Z9- z?)c{(V%Q+@C~j=5>56hZ!R-Ovk%mnqxF4W9#<01LcO#lI_h@euqD?BC4}dk2S}!XN zg$LRC)QBwAo(#TJ%JJz}u3CsJR?lbZk8#fuA!^p#es^4Jt2!bfh2P;vWoCv+V2`D3Wu#`WAzTRb)pmwywZOz=9o`F z{8Ba(TeED+uEUfE{La_!K}~MJx_Qg>@DbGT0x0tj7UfT!9y%5cO~DcfUWdl3Ag2j! z^3Uyt3w1_lE>%v)_2&?ON|lr)S1aO2%?z!#mi~mwziL_Xz7N~#nw`D zh)bwaPuZ;t@k?%PsXJ7<*0l61E!`Y?)mj=3@nL^q>GsgC*3x9COsr`sfg45L5o!d3 zI(2g)zTht`-5cslHP(U^P`QR`O;dHef|fRgw3T}xx|?FBq!djSb}c~Xi#JWPADd{l z`>9%ZA#O&07hdo5c>9ZRmuxiZG#}0u{2YXgF2m(2w93%;m=->+urr~4yg8|*=m#pNW0zz7gZo}{Z|I!&mSg` z4lo4rLu`PVxR}lWPV>*``d$>t9nhxxmjG96x5f3ns%v%E_o{>G<(*L404mcD*1hU* zf^P%Z3DT}_geiwV_kplIg?BwnYERS}OqfGWyPgjw7bLE4Wgz}+Gl6t~c96FM=>Vf~ zF$x6Nd$Gc-g6p%OP4_1QSA5oq>#J0^>aMR+1L@^uP`U(Erh5#ll+N{s0Ne-CuFruf zhd=W{?rPD$`x2q!iY*0G5Mviu=Np!=C{loJi#j%rq%}3Mx;6bOPSQ#ZHi<_$UVA&#@+u zPVv`}e{KWh--yx$;d5FZE9CK5A*RG@#v_Hm?nkbILv9a83h6{Te0RllUTcGjQy9aMF(2^pUD= z%_CLMf%svNc~4d!sT%ICyY_hBbv`~8jO5@!ABz^k__?0hE8U4rD+hm`<^6b{5eGZo zEX(7AnIZih?|jS0W0w^}f3_Ug=$0m8C!m4%F0g!VY!dl7mM@4sgl>R0*Yd@&Ih147 zbP z55btvTWIyW#ik(9-X)grsXyTH7TF^#d&f@Y==f3_exUwf$6M?rnOSb>;Mg_8A;&r` z*y{S1q- z#SHQTT;@q4H#9i19|svYn9m6fHA+tM8L}e{>nGQt1qh8cY>>PR^*?l^VdKe8BfuVG zSZro~5XIx%cO^j+BC8p}jkIVFr+1Pspaz7dq$1ePAg81v7(|OxQxTj%_DmZ=awSS5 zWY4Tef~Jx`$K@eL***&;=LVQl8R4X2F>&-$c_Nw-bh3YkPA=!MAnkZNm<~6hDF@{( zM%k)ZSVwXmfU`jOo*<5>)k}E$iN9$Flu1o4G{=FMSsZamW*sGoc@OqqXT;i@ zqb1_x&A3fK;>~daRsbjip)B5{`S!LfCSt<_5Y2xavgX^1`4I>(03_xs#nKG`Rua^S z?Ihs+0PX>yES{zLTk*OQi~0{#m|-V5!RwHzJJEcJ`?vbKti4;X0tbnd#jUT`i#$OZyuN9OG!KSvyU3JOnxP!(|V72?&&4C@#i;YpKtXyTo&P<3<$oE+gr z7v?a#|KOcDL3Z_)$W`j~rL?Shu_|HZ9DJw`L<53lE&hemSFsZmdmlSCusd=veeF-Fa)ktdIj{v>~ ziJOgUx!FYAthf!`Jy5|Y7-!AnNSn=(z6Es68wbhX)VvJdAlPU`-{`ER{M#QU)r_ch z)Ajdb#+?Q9Oi=NNetj6GH+zID09*wUH~m^}hQ!UMp|Ba0%1w?NYr4s3|HjR3yg_(E zuCDEPF7Wa52283(7`aGpe(trUo5|ZTZwZpez~|lp`Y`}tKajZjrC0Ml#^JcMI}!@R zK?S2>oVoe$I&O}GgipJ)^D}uL^KpP$_$9sEVZ8hT8P9fq0xYWgW7f+ZUTb=JBhVW_ zQsz6n{pr9K0GmPLnQ`K-cnv3TlU73V zH`VHD7T7}L(as6jI|%w;!K6Af(|WYf(~r4|JMruV;`+*APn|k#}O*c`biy*1l?jFTfZj|wC9n!~4><=sI zzAWq6C{I6M=K!4r63<3?`uVyJzzrbrY_#>vl=Bg$oT2a*sNh+XfmdhM&cGdz{7pIk z!J60ExXE7Y&!DehQgPQysd=4EIp2+P28l;qtw$!Wx`{^vp)dec@ReyPDjL-A2zm7b zB9=9<4Ruon(Plwae;MONS5(50&FQdTR5LKIBn{0$ZYS2w z-9X;~iJJ$x{h6EUe#iMIKymZnT5b*$H@iTo3RK`2H;;hrnzTu|O%{kDetKY++D73MN}6H~*z{yZHvtS3$Y2 zF=_u&y50N@z>gqt^G{Xtk%QfOXt(`?j?)%YFwM9*7`AH``mDcmGhgkao9|+y5YCy} zKhE*omGbgk)r(d0AjH!L)OhW19b~Akn!_;W$n@MVQ8y}@?Y*TvNG!5ZT0U=Nm z-V{&Q6Q}^~fn?9ql0DZWz%>$R7BgtI@pdCR9y>ww_ViSs)k@z;TM*!BP~)R=bdV9$ zP{Z@|nKx_YIKCet|C)xgeNLHT@{v9*GCth~(~N@VIV&eVEmFFt-ti%1Jg6~eY7s>D z)Yb4N`m{gnZos^m0{H|G3@@kFIVz$!hqw+#X`F_62Z-Twl)kf8Bf#|%=pAP3Sd-ZK z2*7|0bZjcnSXITMc@Y7&fEs@!K}Jx+CiWQd<`>Anr{Qd$^Go^ae)=@jBz6`|GYXnt zkupD2>0Wi!!;Vu4LZFGvpf#xE>`4Z?p21=MfQxJdw8R+0tpoG#-pgRy?J*e>!OnpN2r-mAigr1{)zKoW9 zlhE<7LTj{iVak%PbeHNaSa}_UEn3c|tyjclPG&RQzadg3dN%tNoiXhn!8$Rh*_IyE zKA0;B?$YVabtQXMSAww+9}Yr~wl#!UPEM_A?HePjS`J2(_V1*Zpj2yB>p$%Bfso!kFE7iEAg#B2t`onT z3LCJMJz|gOg|v&1xv7OT8?RkR6W)*7g*4%Vs9i`CKE05(oawH%kS2V3Ax-%7LYnaD zg*4&Q3u$6My^tn+dLd2t^g^11uZ-G-G~uhFb|Fpl(+g?Brx(&TY5&s;X%arYkjBia zzL3W7vXI6iy&6)pkQTQKX+2P?85C}^LeI&}P`YZZRIJ%q=i^cBG#Gi%C`Z{fH=}_K z-u|G5KHMzpu4cF!vNADq?q(gHkBA-b%qFO8ZM`?3WP@~6r5=J@*8oPdy5Z)))-M0V zbU>)H7eJ7x3|B_J#zk^M7rac^F;3sOH1};O*v^LalQXe&jDvnf8YHu^Qi_9qg^ec< zOn^Pmu!-bLl=d}jt{fqJkYNjw+@3gms9}qfd^s;X#IPmFbw`06Vc4>y(+ce2hOJ2c zg!&pDYuL7qcee+AoXe)xBse@lwS~p3sm#T!ubVQDW+12BtOW(gqpag`?PopL5INv@ zpA;hasqSwG?lV+2=f1{;FG)1Ujgag9CYf&QMtD1GyY|rF;rs^8Q_D*hsXWGkP0V7H~8A8P+V|W(;r-M>L3ULZlUHwq9S&m}Hb>eKli> zVf`f6S2IpAEKZ}w(fj{6+qGj%8EsHP**tfxwl zFIkzWYbxtH4+WYv4S<*RC{+Edf1=WavQEPEd^l?YCTtrxp2ELif44IN`?TPFj2kWJ zr;p1`lmufVIar@bUWC<;;27h8ll%&|RB)VO{p7hQ$l!Rx2FWCDQ>!8zLB;~{(`0_ zxTr*GXr;bUf`uh>;0*5@*56=}k#G+2I4gtH|u+vd>*#LVDaIXcc-KGeWXdA4L3`emh&pQ&}ZOP+M ztW5k8I&r&URdPGoI}Gb4pBe@BPQ!Z1;YWbI%dmd36WO~B8%j!eb}&h$u2bYh+*@Sk5c-mVH+l&q4Y7s79>|OqQ?zen7p0JPZ+i+`3d8F(y)z^ z|7H?48@4#Pfu^1^Y~y42hNgZrY$Vx&>^{Rr zlXo*EKN(Z;ScE zFR;FhrNsEcdE<V(62%@uq22&B^13lmpvTS`585z=c%E19}qZ84YaGIm*UW&>O9#%nH@WxQv_Ev*>IFr@xVid0qNZ{Rs zNoS6ys12FVfbIb`)^8D=9M^rDmUuU{9Mt5nvk>Owcn*DWmyU1z3R)KMdf(OlQ0M__ zs^^SOiO1Q8Sq9(|PzeG!ys4V;<(}~@#{}AzMjxW7Qhlp=^){5%Ybme###_@X=P|s7 z2Z?yqU%WaHU@uT(?NxvAY7~GG1hs4Z#kJD`OazH*2Z?K&0XzU|PS<#kIi+vWn-5}1 zeUm&i1&{fYF{%4Fz`aSEPankE)1x6k4*`|^h6e${^y2M56~M`$CRcR__))Bo_l>)B zSmRy8Xd|XGa|IMG12xv0C4Vg7rvN@8*qbhVB4F|f^nXE3-e=i;8jEj&lkU=iP0u{> z3`czy%VeA)za0XS%ll=vPwZ{6*NJd*7zrdm9kli@7@yxIGjTy@ZLZvhhn)H&D%IFAf3G2kdMelE${*2AjJD`0v@D>q zFmv*cXkSL#7eF_VRO5d~YgXewqq-Vj4~1nQsm6}@_Bw!927$@{mC4~>@zw$xiyIjF^E{iw zS4DM0@d?lmK}~d)ToaWJ-_lbWcc+bOB{Q?0!FU$b_}_Ht+Gry-utx$ojNq-v z=4@U#%PE-+yn20FM^C$()Xq5r)%Z*&=&>{m> zIpuE~XqADwIprT3XrqC8I^|y(h|6lMU`Vi{_no(6(@V+?edfqFV6lK`ocXZ3=9e=rl&(W~Z^g@ooCyaOKHrz8w#{ zYI33V?a4@6=Gy|Gb3x+UQ{vlQ0PX;ZZ%>PF&jWahV1lWBCZgNFUjghRIDpYT6VZL3 zqUTW;K-yytKDr`Sq=KjBIdW>A7BMdei71u%ERf^USSo=|qh_oKS5-?;H$pfJZ^vm+RomTlK_Sr_fto#&%#~H9xrMR9S=< zoOFF$80kbe)G%>ikvOmu@$3LOtyB+YUx$c{oLHs!_akKL6&R6jXorY?T9NT%lC(Sl-~o`%FAgqK7dmy!)%#)HRHam|mN0JCDO;smsbaeKJr2L+ z$k_h<0Mm*_#J%r>j=a5^ynrcekhu3_psVm{045RC?(GY7HCYSbdQi%lzOYr@8NTJJ zy-Hp1jzezEi)L4J2zBtHZ z2|Nnm9#Hcq5G#9|&0oX?JL2X0aKV1TL{T4Xm~1_?-G|rM^EBY^Pdvq5^@`ay&MqPIL-- z(9{_~PXm?pVeRY`97&Dq09*lT(w+8kn&Wiv3ko4muM`qIZ(D)K0>F+A(Z~ij6 zXCPg3*k8O5L0LRAm}d5iOAu7|k8B>mZO%hw&?X;idQGeWG9-_&Kb0X>d+Rhj!SUc@ zhU|luqyk4GG8GdL;}}rc18mlw${0zFtpJ_{!9Jhot<_#K1#0`u4Y(cki>Hq}>$ z+tS}A+fjBPWYq%Jpi9GfdcmW5prcZOE)DCfKLh~|VxV@aCCh7DD1CnIG~nvG5*y97 zkRBG_0rU!xRHp4AU71F_;y6P=(hR*K;28j>fpleJp1pwBt2aaa;dQEU)LJZrZ_`>D zV-|Yw!h}p=4bxa%BUSYXwN|RNW;asX;-tliY4wyJXQi>4A=w*(taej=R$FA(giy_< zd;!w0&TnS(a6(8o<#z(T8B}%wOLs!3Hw*Vy0ACP%i}&(`&=`W}?m+tvlH8so85_I` z38?WGtlyIb>IXfR_p0$6EWNe=5PDuRG2GAQ=w+UM|P%}Lt-Cp4R>bON^H?ifD=n?VrTpN zGqF>E9t)Dh&h`&sVxItTA3>ei+5VACSF<;;qzID4&h}3s_#l8=L6X=xHn9Vx(C13J z_Ind00FuOBDBuYI#(+{uYY*3$sB@SojdHl!SEIW9));4MM;mOWsmz?$W#Yjj@vRR> zI-Au>{944Mx|P|)HzSmo5XhD+rW|H_F0G=hNOS+jP{*bq^!!<|} zUuqL?=C8^mo!>#>E0838iUF3YUT;LD=k^A)f{C2q;xN|VAI}PYH~u7c|R03fMgaYDPV*5G4BYHS)6PEhXEK0k~!dPPtO5+ zOCP&HW?Hj7Jph^tjT1qVmpKyj830d$8b82-&-L`o@RtBS05yLfIin|ls;0`^U3PIh z(A9-95x|KA^%VGlt}d7r02Y9xV0ugNrXO+&9-6vf`nbAa4g=5&)ck7XjxLyQaKWbQ zUoETM0;gi(9#|5&W^RG<*1&iRl&7)ghXT_Rai`!y7sd}3$ub4syaz6H@w8E&cSK1f z-J0FO*{~;lyrf&nRzY{%mQvNNrMe-d>biRR4XUlwccY>D4&J@2KC;__G%Bx^E%bMk zo)G;V=no)$k8`^82b~x_M^fV8kJZFU90EOT0{0wayC9|3$dWqFy>z0C`N zo(Gcq?<%E>`X&IY2^2+oASkKtgwd>>Hu_Ouuceyb;PX{T49{ z-Uyvp0t49gQFvdU2^_+LeH32K1P)=_N8#m6;1ITb6kg5*4q@9z;pI%= z5Vn2PK95r9KyDb z!poV!A#D37@yVIMA#D37ayb(?gl!*%motI!BA^)bS+HejM<;ZR<^3qOs0>|e*&vFIN<%9w8;^Y(fzj(M zk8OD|I0#*D`P|q@+$f=ymM@6q6oOx6`Qq3~=$eFXuzZOVKcB#A&wB^n+P5_~D868q zr8lR{sQy*`Ew5`W^c z>kTk$Jn^rFU5v|7*n&i7#O94PY;j@>67P*OY)N7YntSgg z!cz43(NP)LB6nPfGW84SITNW~EPVCfd@Yh=2j}1hV>vw1pWM*Do?zUv2x9DTG! zMrLlNVjij_ax9luPM+EgYpS%?fyLvXkk3sjA!$uU4Qn`26uUFr)qAm#B`7}*XQ4Av zn;qd4_^g6?>MZJJ)-t-3MlTUbTQYba7WmAwLiI4=8*zRCD~A1h95JXBVSFj6UAa-U zpex@3-3@A}P2H$^)6~q5@$n0&=w2FHr*!VW2;d2Vedy)Q0+xS*_&`Oysd`OGBp!)Ldnb6bLS}9bTX|=l6wuL^o*8V^C z-ULdDVrd($?CzSbp6;HWeV<{58HNGbK|nUy7ugpP71?D`Ktwi`O$Arvs;JE+2DBubzR}m0VQBhGuMG^J-KTl+3O;3aOzTbQP^M2<$=bdw+r{c-T$cV_Lva+(O zT0`U%iq$^ewr#f9H4w@DDPmO?qE+}x`6_cNt;4rzf|UWzs{9%K(RUyTi42-fJdo64 zuH-zQInS_>$iVBwGi*2KYs?vAB8LN=7_)WGx(kuhe@Rll48(pm<2vkJfLgL^Ta~v` zAjyy1>=-&R$={lZb>sw;u9xP8n{SMsWlS_CK>SD^^t?cGWD9r~P^CXn!osfAFO7oGBc@j$Vsg8LP zO7odkvUw8fMidYn?|;r8dK?`M#WuG5FPPVelW$`AUo?Cmv=}3{|0Tmap`)z94Tg_6 zm}2=~Hf*ZXr5pH-hR+PWQVH=_44)g?N`8~!3q$v#Is0EVe2LSk&mhbHn&HcxegivM z{>_H3bUF-x{w;>D=L}%jwi>=s=&>~Dd)@HOLQj%^!|*Lb&ys)B@NGgbk$=nZ?L%`B z6aU+W@9cD@{&x)DJ;Vns{o4%R%jt{c?S}0adWY`4YxqH-O;rD$;fI8{|I7cr;fFdM zx+3~J3_k*V6AN#%bX&m~D|s@mDDg&1zk{(e98_rBR^U#>31&ndql)Uss7%sI^)r)R zWpj@F80G-(&M;jGJYiK6XYq(UVHJ@ltRnJ+Riye8R=-1y$148DpLIks|H9& z;S*LFIJL&yC#W~-jCIvt+44&w={0dOZG zPgq6d39E=aVHJ@ltRf>zQ3;XiPgvDJh5&P=nkTF}VHAtGPgwC7ojT?|VZ~tK8I+j& zgcYNUCq-hz&Vyw)77vrulVk1^R=l_GD{C3M2Q`8xtj-a(P0W45O0(@_?h{s;?HqHT zu+nVznEQm4W_!ilC#*EvFXldBrALZEv5n;@=-y%-pdm5$2`kMGwbB9{t>D}=!0Ld%x8B+L6ZSeWN&`(r*76bi&D+#sZ!LIhyUN`~lBc9qzhJjsc z)W*J|olm%IYHR@ASnsl#v9_bYKI^i%u^uD9zTmQjv3AV6!DZp|?Q~$He-tgGVQ_qN z=rjiw*6fLtt*#{cY6V#RjRbbigXjjqx7<`G7OMsJ9hZgUgP{r=`vXv9Q(H=A@SmZz zRC|oReCVldO5;Cr*+6XOIbe5tYTq0S_G6MCb6LESHHVo$^PkO9s2rvI9?HWx zGxmBJQvUR6Et!IUxojYG8bhR%%R8YpO!gZ-61s`S+J;ZHlK;gFj`DA0Nh}~spKOBl zl{yn_n^1$ZsX@V()6J{O25vn#B&crxq2S=(34l8IFA)e)eqf`Zp^Wj4=+=LYzt!h6nd`XC-dhlFT zp@;Q0Ar9-ov8rM$it&}T4Q*xv9j7XImFFvK7h1&h@v7nn;X8*~j{!eHRq)-5zOwEZ zS2t~pp`g-h&GKw9~l9(CD9&4`2(A@o)y&7nrY{HX}PL$0?<}OFZIy8 zs;7=P0a3RwMas=n-ZMaw@{&o(ec;)QJ`W~2pA_L7uZ ztTffHkaYyXX4Ek0Tij0q6*BMuyAoUm;AT*ftb(j6mM*suzy=ULGFOU9P?w{mnsY6u z4QK~&#c%59qAo9Xiz;}ZS})f{ss4rA$AP_~xRiwi4&nz?aA1Uh?Fg!YH3pMisLO1O z^phx8vUWVsF~w1pJb#h$(SQaeeJvK?-dfQ`|24@Ge2IChD5_JuD%WE~hnni=yiLnU=$7*95HQdDiSLYU+ks zVzalX<0NE5L@F2)4eTz|DkAlI- z-;011caiHbtS_ooDeH?Q4BtWMYmg4Z`l4!Kc)Ca`CHD}z3P@Y?tS-0w#*8)BRS&~;)x&U|4#UgH^8!d0e7!E?I{;r1l!6y) zF!u)xP$2ZK&)G?a7FF%DItjQcNHrx7EixThDqv`lbmX%kbOxwU8t2fW-mHcz0bEW{ z>gJpx>39zUSOwBX4cFy=1YjFMF=~Vciw|Sq16eieGa4Th=F9aF0Qu{NB()cdzx zKyp_Oe|G>K2P*uO4e7(e{*>tc6JDkasv+xx9~EYCFxw5_LxR%fcNIz_iT;eenFOWf z?AG9A0Ox?Tb$c|p62J-&&h=O>iMR)BFM_cDU?}FQR_WIq8t*QQs%fZ5R_Ig6rv|2( zkltPBHm!oOG|E1iNo<3YOkNg8|*!2JZJ_{kc45y0~x ztMpl%fmA&d{MHQ1Vd2{WtDd+Kp}SPQ>IK&;>=o~K1FbIb3pNt43~3q-HP{JY2aqnf zkp_nV7!0yX=i(%%J}roJ|KHLA8K?T2QUv&kLj}+>Ja-LAv1m8r%b5 z7eVp(3k@Cta0rCnlY}Xxx}_jV&6;gF2SDXmu~O|ajLWwam~)d<^(_Tm;$2><^$kIu zejr`)G7a7e;AVnS@@*P?48TJmt90rJl+yz)bIF`;?**)$_6qJ%-Q^zDUGAyXr60wV z1f&b@rNPqy^d=|;_txMN0M~%v@;w|d(&6&5OYqRorIxc3xC&+(m(vR>+!6aCwukhB z?o31LzKZ9lOs&uQ4Lb~}FD>we4R=oGnOngfK=RiN0%|BS7IIF9q!yf@3;{X_R6~XU ze?c~ffGYsZ14%!upNH(F%c$;PewDhFNLLSg>JH{NrMk^PUjb=#-{*_ELjb-5iMk!P}1eG)DAHmyN@?0O)&f^#}GEQw<$f;jFwIlQEQSE4;=YX`@(OT_N0JnfdZ2)Fg zslA`pwu)1`8gi;nw(-7|uAA*Z-vDW~ZM53JADD-OMC}!E)|Ot#D*7w0s>X95rdD}c z|H^AlW7`640n%EP)_Ng;3qYdv(KxNe>QBaCM_yHE7eG$^?y238S3$L_fvy5+wIAe3 zL)r^q4@lJd;?!2CremPx`MhGewqoS@$2n%B9E3p{_w#wZ$sB=#!yt4NAKH3_dVVOf zuFflxOF7BsX8nhkb#-1JW^MK-bb$(F2EICPn4US+c!eE!Ou={GOa;=Jz6)Cw7z>r4&LL8b*K z$kZU$c)viGbS^TC)S0fKd6%3Z(`YZ#C3&4#(hbP4NM{6Ccykah{UbnVFtP zhNpEVyvh?Bo==eJZ76J%n=>yn1%bzwzhwe~LeL7$zl#{Pe&PQH3R(1!L(+6l*kS@o{ zK9}X(2;e%w+G-&@})Sfy(Bi6fQNC-Gu|r_ABpqk+%z*>Tcui25 ziUTV6-H4B{%8G$eS9yh-D0R%uLy)z6d)+YWRMsPJ_9 zUO%%hl{^E^rf0}tu?px4 zP+@%zL(?-(r+IGyc!i+YJR?JvfeJ&)$^;eG84bx98AGURCV(>u;@f(bnwim-*~cX- zYc#0vbp#xsEGAqB;3|-I`Qi+zrN;m~45~yfi_3MVL1!&B(0^kfsR|r^B5>M?z-vwf z-gP4Ii8xUDJxezwqpi@7+A4*UlGX`<+y;Zy<0U4Ltutg~35W6NH;@iw>x_QX&>TP$ zf)dC!87&Bo1aJ;P31pj$fehp#09S(wB#><~&ZDI7MmJpTbhw^^z!M-bm@N$hV%1Ki zYU5%pHGnBT86@Es8NX)G*72ZWE#I5~HxR?i1|#6*w)E=FWh=^2{Ys6O+tS6$NJLo& zkfI&hmM&iY0&o{dSM9s$Qnh#DG`S4)-)qEPE|}Mkr?Q*`^Im{zwWOvoFDJbldn~qG zS$jab5^~Z9Gm1$m%K8^Usf65gX`{UXb^_^2$W0$cT~7eGg`iYIUb-x%-WyZa-5}kX z^R&(_05*ZN%LUryZvlJ-@>+8)becBhf%Q)Wc03Vy#)-g*Cju{v15ebN=Sn@_$q{IG zTJ?Gkry`K^5N|!1+npx!oo+xofpj2ur}bwbrvjKvPy)FpttG+b0B$2Ft$9z{nGEDs z0Iz~{YyLRx6iRxn`I9thA%`Jw2qXrxrTzcYnos8N)IPz>KpMOph?2CI?bEujxl98( z0#x_|PGrb4mJ--6XZ=L*2DZBnX|g^#2H;>&;qDOv%8<4Pzz&dZ1f8^3n1)!`A!^mR zbR;A@r)Bdtt?$M`QvX~)sfRLnUc7OTZYW&NX}$)>i+(tW>Rm zaxVLEQHD1TI-o2SsAW7`lPYJOD}as!Y0n->?Z)MqS((Zj0@7#CM^l@#R?f&$)+r$E z#M)G;njYDxeo$HY9DLpwMwj)%0WB??fdejmmEDB{F20p*#le|8_yGsJ;RaLpvZ-}* zO$8!<)1Xl;_e|}UDku6!f!++#rglpmPKgV0lywG3o7ye)LYkVNtE>P>o7zL0`VN4t zpyT5v$gC&~W9huhfk>Vcq^Sb0Is}@L`_eHELBUzrW zENnV+&HFMY^NR^(Y#7H&oXSER@M0?)MjFNCZeraytgb89 zE)Hwr$_uUgG*VYzDBtz}|?%t^~$Q z(Y;kz`K`cs=hF2HZE4_G#P*St>TT&=1X#UwW1hI!taPejumljoRn&?R`sjk73^aP&zGg{r9 z<*-i;s%zZY8I?h1BhVK?+MS(IncDsY;1hyF*${U|M{#y@X|b{kcp z)E4|iIZkzRNNqRPCqrtA(}G%=!CG0GP%GEMC-u8mD@&ttO}`%KYLKp#rBS(s6)95~ z2jd#q`uJkw8reH8?lv+B56$_qx;)NTco-nwObk=CRS#B0(*!dIqg?gNNv82MjY?m* z1n3NqHnV9|`ojGHmVtEbpRB9TU#_g*2}M`v80Z z@?3cwrg;6!ts}a^_f^D2-IM>cy8Q93H>T?g*|L9)RPQ&Xwcz^lddBr%BeLw%8)yfR zcKz1~9;C#3-vBHHdBqMvHqXqs8k*wbi8XX}b@}7Xlp5;ES;=h)W`2iq)w24=%-bSz z`I}autSCsEd0Rv-f7=3R2+}olM@0JP?Er2fC^dAa20sAs4ngUk%Qcu=8+{(6Yv?Ww z&IB+CtN~v z()Y%8X>b;RDIlo<-fVjpI#C0@X#s65!(^<*bTr5oKaxSZD#7N*p+yaEXgt3vES>#B zpznh8ocgM;boOXnWraXqwV#G;UbQzm!B8kI_;UuldqT0zphwk3x<21_56cN^2+%CKeuh>QL#r|ysZykYR z_a|3xY@b1onuv~~Be*|Vnru=%?Cu8XV)rNanuMXM5ry-1IJdMUE%KD|A;YMp)k zD2Q%M5PiiH-I#oe+x@Y;HyoljCj=;39|3Zjm;l|JEN9!sKF0-jI`pb}vaovD+0_lI4Aig51lOkX*i81K=u=v4Y?qt<(q^#N?_aafdF%H0Rf`e(tX(1UNR|2?;pxij@6_RGW9l%zCPqJn8 z)?i9wTzG=KC>%jVr6wc_ar3+wyg^_vv*gThX59R;&flhVN=%Wqq}Lx=ws}$f%aL|`G0;gM9mT(#?yTZ%05*YiY?O{oK@(-=fuvM-N{59(UA-tY zYcvYIH=)pm$e`w&Y^v^FN7~hJpnXBQ(0d(eSK9z=0O>;SbEI9J(NtLjLApZjccen* z0GLToD&#>&D&z$Kj}nv$c}Rm<&6Je}inDouLT{+89%ctxm|$&Fh^mi0YZp3l|M3i< z13}u_g-#cS=wblVL2;V<%RHZr9r~|gH2Np#Uy2NBMspL5{!R-HC7Xag4buAiJF+P> z?_^A>K-%$v+VKSd<`NXg2WcN)1n?9=ar|@*9szI|6lb0|p0DO`v}xl+6`YVij)eEX zCOs0iaZdJTHxtK0w0?rQp*p2R`Zm*8$jbGVz{!no^mWH!_SXj71w#$Z$p zO<#?Hmd$vlTztDdomwV(S~drzQmzMj8OR&-&W1$%phuUgG&{V^8=jzfA2o+s8vBL^ zWn9T_fzW_-bqo*6xUwF=3XpD`BZJa7JGN9-dyqGzdHw!7*O>pp=!dpa&MJ8!sk+;P zp;&$48TUexoB$RBodMFuy^tg)fZ|iIb_CLc-U~@%xU_l}fHnkW(0ehd2?xEg_#{?W zkalB3lDKhRYh{fE>8AE_lJv0~09*?a-#Es2zP%2c;>R>k;`jsjcF$<|c0qz~8=+X8 zb&3i61xYe090K|&Nc(m{l8g#xw^3Gakhb_jZSnH}o(09VZcIU8mD~AxamJaRQ0O*f zPX)03pO{cW+hj1*mHdXm)kH2^OL=|VGgp=s^VBSAV$SvpKD05k^0S>g^b>|5#( z-ap5-{N#MRqvbNo84pp_u9b28kSzniBA{1;v<-)B82}yyuo_hU3i6ua*0d)CwjGL8 zPrLeu;yxRwMvT^;H%K!<=T zn?ZzgrJEpOhK;Gf=u(yDQ9QYC!UJaU_B~C_?b{gpHU*^heh2hJkPh;ufVAH0JK#(O z(hcdgfb_S#j>^gbNq^zOoY%F=p_Im$YW5_KKR^rEfgY`DBp6p8idA7-V_c1ZwDNO- z_6BL=Y6PT}9|3Tfpv;wO1V(e%XxvFz86Z7ulmr@c*l62XSw$f2MosNThc3!$3(^g! zEFcYN9DtD^F}T{WVZo;V`miyPr|0+Z;1?Bc4hLx) z2KZ%OvJk*!pg7G{?Fo(M*D=tapP>IVa7xNV`+0 z-MIn4wV=2{-C?5+>(TG8K5WEJHDiI_Up3oU%)a(>!ppo`d7?l2s%9Ip@eq9-Z*Yrm z9UEbQnh$wBY`pH1vF{6@pBmHXVpZpEKLJ{{+LSF~;QIOZeQAfEP71I*3Z)f&(UiLJfTz4M> z`U6P!;WXbs_TkfdVrU2HKAh$o%|3iPfEz%%;xc^F4i5wP79!;=akfXVQ*#Sf>3UsJV74y?{ z0QlP-XY2ocMa9L41Ru!!-&a)pzwnBRU-~ugp=cm^z4uUb6xMqWg=W3?P-xbB4~1sE_fTlodk=+X|J(1OXah?!`GXxK z-C=WDpb;4J9tw?g2O{sGcnJsp1Mi_Y3&q$hOWs4#F$snKkH3dv8*O0GDUsmUp=)VF zC!9lq-@0!Fuwvb6f&I>91F=nIU=O*hWBDILFoVDN2O_7Mt^UZfFQjg25Vw zFAV*~^iso@gz_%{UuO97&=u5Q%kY&}^5ra`w({RWXXt`?ZvftJa4XpV>iZ4GLpHz+ zCO_V9@CNh$oA(<$$UGD>dGLONe=*O$dB4FP=An?ugZCToH531x_Zy@lpMJl=k2vz) zZ$Kvg{RV8V@$WZaaq;grI4XSA`wjGPQT2X@R|I&IPQoL6xNXlfBk_ngMU#XBQ51R$gq~Zle2uASfzTnwJ zZ;wOya9;2%qHE*O-$w!+N_0C>Hmj;)po@>I1_v?yTQ8kQ@VF0pBMKV_fq@jr#==a3 z0#OAaJ^>mWK%vH-5Rahc4Fn^}1(C{|Tn$yFrC~ z2M2P?t?%T%xCsx^uZ9RFOGP#X&=_PDi#&bPe4rdiWsf;hgwkUM?l{PX{`@xtf3dCxhO%Xd z7u~M<`JVcLq25$~J+fWHthE&1X`-5-Dgu||aT*Zqc^ESKlCw$Z6jmiJIcv#_PE;90 zeGsEKMHwnBS{7>Qi9R<0c{1ZFn4*k=7R?NG@I)UO0nsFiQlqQ2o+p~*8Bn2yPJ-wT z+yY`ZH-AsU4|O5rbpUrb?Wpwvj;EbA)X{tZ zE`~t`f3V)3cH~Y7bX2H6&IiySLC0)}swFXFNCQWFTm$q$P+^3%)6kLUE_MKTgW&B1 z8#x1+t>Hjy?*-|#y(Uf;y}S~@e1c0T*;L=8dkw(j1mB_^%`|w%AlyR))yN}=k3hk3 z>tX=Y3GQPU@F6IIcK}#QupT8_Xz)b<&w|jJ_QLlHRmlRs!!##8*t;R2e)D|%F4&oY zik*%JPC$hnsPOyX8I%|RpckmdB7%p5QuHeT7JyL7Xf)vpwWJ)0tK3p}|AMVx@L4Ej zTB?cUs$egcaxKuyL4~ynkmtVO5K6oaU<*h;O8KZ~*o90nnYG==TTZ$%rcf%m+dLdg@Hy$WP;D4swFqO12VJFdSFMB) zPqqBg13y0|x7sSyV8-#%1Um*nhYDkPNyqWhq)zm6HqdDxZO5fa;^zwh)`GMhbF>|W z!?An^(i?~7Cdr7}9zZLCvT;bcGS{#3>}Hv zVjvyx3LUZe04^aY0k5sW#{fJ;Py$}5!My->5|n_~(O`5GS{TUlZ7l3V>*12JekS+d z2YebE=2qO*i*MmAp-`n}8ArF;ay}UkbO=b_sn}}E`Q!rtTS0one#4d#yWwbModl8- zKc}yrb$@E>yteI0cn4?%7qPXsOR%Xg^rGf1Hb*ULb9K2W@@xv3N`nq=(Lq`kw7j0E0o|3FqCf zBRp=L^<#ZiPJX77Tqm1V<@xitJkk%SuDU7=&~ss4h4L{J{PG?a&c-Urf_EDuOS*$rR|NLzBZwq(k9WlaR>P_NLI+zQ|ZP`o9H z%^9I7V#}SAV9*xiQ@45s%?Y$(Xubvd6-XO2N8dG$PQZp&P<%07yM+E{I7#Z6p#LOf zQ0ckG;hurk)ZZ6qPmtE%Q{VWV17H$J`_^0g_AdZOLGgv2z_&-vL)nLM|1iGV8=i-< z@At|+?3ZdE4zw>wmwnhT)&4es4ImxtpZrqo73bq_5yF;`Ny(XUOrJ-BS5-Wj`uek zX<@=QNm)}t+WPaf_4Oy?DL#-6=lS}U=s*CyL0+#M4pXXkCC|xOI_dacx#YM!QadN; zl@%(;iYZJ8!U9;JPR=($DD=zJc`eXYARUB4zf7G27bxo(KTK<(!@dP%ekzz!fi_4roF zT<-z^=M$7!#z76<0^oX(Xa8d;$g{t(j+E{j+zyNHE~1inMZuFug=))4ZAozHb?8&s zMaHEqN@l9x0sR^zv3DoECQ8tBGf#bs6EuaVLDTD=ro~EP-Vo?XAno!E+U0=&dJ~jq z*KX9_T?=3VL78pcq`_waJV8+6utb9g0DMMJW?MIFFlRb;x`K{3S!S=}>HO3LlRH9Q zWfU9drz)8>js-gEgqj*LjAPiD+9YUNKuw!HO>LB1T|WqP6-YbZPCNe=fXxKO`BSy^ z{u#>plb|@?UV}{l)&pthJ7{nufU^mT^BpyK1AuEmCv?7+I+NE*^%L&KABMGhy`#R8 z37f2<6w$ll1kpk)v1-v`CBqg(E7e^SAbPlZ4|yI&s1XpaBQG#IEZ1M30Nib?W01^B zTcujZmULZp9e+}X53Xn(*GZ+EITK9=R7ajbzivF!*MnaJsw=P7yFQ!uSMapBbPujx zz5zRU?!>b>f*nSe|5&gAs;P#!N_yB8!*k{mKL*BFh^ui-BCLZr5BaQfPeB*f-*3aW zqpiJ|GPcL0+5G*1Yx;zZ04gaGK~A4Nz7GBc?1>fl=h)-$&%YI`5dZuAHtT=C-)25q z_J8I3ZR2fxeB^T6T*UX<@clM?eB@fRXWXCB-*3amM>HP@b7zN*kB?~H3G?G4HaJm;=Ep~De0)UnCCU8wi2a)3 z%ai%>5gQ*L(dm`R{P>8CkB?}+UNS#EV&mf@nr{^5$46{@d_?oj!u(ap@$nJO4+?LhdVG9D^FzY?_=t^ptxUy)lVn22WGIoZq-pM^-i4jeS=)o7f5oFBdM9G-C?qCq>Cz_ zKVTyvEz|dAXa(*|r1J|DzPBSd1F*fN^9vNd_ubFe1=4Fl#P^ZQI_dlZh3_+$jimDn z6utv4i+A(4=fHZz&yQXNs64I2cP!Kj=Yw?K>i7NON?PG3F>w2Q`kQLF!5Ut9A$Z5| zPPiWxrx-pG<~J#PnTAgdpQ*s-8$L74&rtYq^Lws%ksIcBD15aIUuZ?9Q(-;jf1IY# zqEM=@i3%;nQJ5c$@SSXgt?<~3z_&JhAiQoQ_zs45!u*7Uubbf`R^%DXQhmLYzZbLx zs4`UU8=yj+gHX>++zgzxrQ$c^V<);1%@xNBI6nAYnA^Y8cP!qiGQfjJv3H~yU7S! z+L&dA4`^dn7~Tm#OkM8x@_c28L=$@ZsFF`X1gJ7p>3c$jCZpYkr!Y!Snaoyr8f9NH zd?3sX622{lcf#Bt;d@(!2TGkr!rUO?`%t+pH6_dq625&#J~hk@627kupBd%`3Ez)~ z&kb{fgztC57lye(!WZzlZKfp54HCYn;mfVaIjov2pZ^K?5ughh*8x$j?M%hKZvKv7 z?xS8sa;Cg-zqNhRD@d(1OIf9$tX#whdHPTS_l07CRS0~>P86>46EyXLyh=gm*P8OR zrrAJed7AP)O&QCm`L{rIYwo3v0iKTE0%FbkK(~21ehV0DGTxybI}>yqqYlovv>iLO zj=C4){s2gOw6jXbFxqivf{y->R3|4J9d~LSmjRta9S<{-cLw@ULiNvnjAq;wkh*vj z=?{XkW%2E94SoXPBT&x87=fz&sjUHj?kzx*FTrMZQ0~=WYT%#-vamolymQKrY?f1 z8-QkC3hkiWbzn}yK^+i`97H1v6O3$!G<7p3(%Q&EZRBL2=Ye!23%y9n7YK^ACCib1 z3rL$+LxXz(>?9~JcP!Chcs3TvK{hy9N&c*h^4sepiF_=inL~ zl=JIxHb-D{24)6BkUSWan*?SO4$cR`=F=GGxd}GUN1FP>vw5zzc`eX2AZ_zp&t`c? z!F+AW$4LJWq;0-TgV}TOkzSCt`Em`O4d8T8PALqk_NQL-`*Yg@y%Na_K)H>;+<}AJ zK(P4|#<^jF&5t5Y@k@QWZ8X$2?*+OGq-}0k-R8#HlJGpdc?P6yZlb|X08Sw&ac-)? zs{vdN%ISHW&68pCIG|4;`EgM0Szxx}U^9rjao)w*Ngcw&6!8P*ZX~K?%rmsnhkVjF z!t>DtL0K=bat`_WQ36AQzB8S0dy!R^A;9T(>ItB z*8#W+q&+Uzemn}x|toa00$Pp!BB>_IG>#5cFT(5XIzpl)slRUJBa70?SnnetZd zgQ_K`j%Q!3tRA4u#ahuYp0tkv_y&}H57sHw_bNu^i?6{W&>%pV_2X3eJPIg`f4ya) zzQyR?`ohfIvgSjZ9Ps=s2X6pjEwY9EQzg-P`Qug-Um6^h*~33o6Efl`rqrr#*6Sw6-Yb!xOOyrJzg&e zP#opxxC)m1Cr3GV5dU}zkOQ8-eIcSXoxE^AAyeYx;Kk2%dc9UvCMqKB#Jx{$3 zO=_6yx`T}%xmQ@ua#*QKGE5y0Qx&Y^jX+-nWu1qd$kUY)=)qTEj;-7|_xDIY04ly4 zL)QmTCqFxJpe|Pa8`H5H?|G!;Ek;8In(`Cy3otbV#$|T5~&rA!zT#keJ%#_mvJ%qA8{`|sB zS1NyQ2cS!lehX#LZ`R=QCSMI_bLyE8)Bf;X2coB{M@C}GtF#*GGiKOXz1y$}K7;#& zB{Hks*?`AiqL|g7Qt1l2q$j*~1MZ}OYVL*r|GY-5KDA#(Il12;;YUdP0J6$na>aZ< zz+?59{S`&t2I$;~kq%_l%z{_^!!@@4Q(xLCxT4D~M?x_~3Mp20)M#?(%~y6~iUc9j z49QLYM$at*?!GvT7=|l z|3=d>`=HUZ5+Wab)c1UmYH@dQwU4R>-qH7Rj22|Izmb!A3eJW+BYa-Im`x{+F${uHQ zEr87B)pc#9u3}|hXLQ|(^xOYNSGlsEFuIz6V!EL{MaGMRJHb1xx zR)03Tf*;)W%LliqO(&WUZddSw+kW}rHbbQo%?GzD_`z+zd~lm%q)s#++^+az3Wkwi z)9{sS&O&N)ECYKg&kj~azl*@tiXf3!l{&FjmUWw2k?x!pSQXtcK>BuL*Q}ox zby{+FsI^GSTGj55{w#MzLrT6)NnT26$+zPr-!_stl-xi`UchL{4e^p2jO1SzLh?~c z^0GloJ{m9isFD1NlFKQ{$-0(Y9xu7vNN%I#B1-afq$L-{OD-~!eui)!KZVXyq?VkQ zBq6LV3xM;I`sgTKL7k&1$@8L?9G%osqIA7Z>n4(w2dJ|-vx{8$L z$Lzs}2br+^qVM-~nWpde?8G=>{%T^g2)-bmSq@qE6XpNI_j~HV6zr6_+5XNKdJAJ7 z*6c0&kk4H-w!$+?ux9*&;RE5D(7^4(hIf)X^?>}3hL3~;b&>v);Zwu)aS3DpZ1~LZ zjadA(j~G5TysIYoUwml{8lFxGkHl=p{?(+HgrC5P);?|uF7lP(m58Q& z%%nF8e+7r^-wod^To=9C{=@Js!{0OipQgMv;WSKr?SGl{_ThS%{n>vRzH|5}~q|*>CRm95TkZ_j`UYd;o2!DH@C6 zo#c+Z;qs&5BjHY!aPB9=r-pMGyq^u9nLMCBHqb@_^3Z zj~c!_c@X*E3}0zQS~L2`+&dt2q3RCEMsO#*19CqSygMMwlUnHO8tRR4HtkV#XD ziIhfU#64DEkvbJ+;r+_uU3Xjtc3yx_;X$Q(56c0?;@zIQbk27R7Cn(rEQ@)+e_jm0T*9HUY1*$QZ@%%(;c?0;{KqYkdG?WtN&tMRqe0T~5iMRJHRn|QqD}N=# zrXW>*E}v7y|rb6Ouo5jok$cDh11t@DL;( z09myzbj5rYTi+skJVoXM+<@d4DN?f46ET`@wEsb|50UUsh`cYF9yVgR)O54Gjv~(i z{0_0F46uC8eWHLbC4Fq-Bd`BKqjBJOj;gzw7OPg9H$zXc*o zM3WcsS=98Ty^A7@_!=ay7EQ-T{8?K;LcH4qk&U9si_;C%^nzVZ5qh^9$shfVrj2$_ zqvr|Cgzdes&!kvs4*FA#^IdoWDYuDV2_tCiI*QEFFRqEMMmG?yr~t1eOK znocyAD7C9DQP>%DqPaw=vyx}P@t6y9A*(Bh9f9LPHU}`IwBiV+`sLo;TG*aEP1J$a zWuRO+%Z*POPH;GYvkA&cbwW}zg4Y7L5|r15<(!`+W7<;y9w)e;XRnDGRCi+c8$he} z+eCNSn4WVms}wtS*==Y?rJQAV*}dgtRXc@B8wViCL0(HX4zw3ZIe9k@^w*MGD49t~ zj-y&KQ%hQPFJ)p6+|j43UnlnPbvz%@!m1NS6rc4~I}F+SGQdAwUk0S&650Iq$4*_} zf13FF8suUIVFkM2$L5buVUGm<`GWhP%ipvB$IbHQQDy>VP!KOJV&(X!FD{Y-_JqmP z%oRs)jnBVDg+51MoKP)jcwMDm!aQY`^ChP3{x?**=qL*~&CtjFZyMflMrVS5%kYuV zK+MGaZyP=})QS8%hR<|1;~ePUrqX{xVZO3lXE9obf4fO9ca{``f7kGp&I33(`rk8r zJ?B;QLjU`QZ{&pPfZt*GX3mD%;Qwj(md@M~@E;hyjdL62KUC>ajNrbq_D)NT0{)%G z-|o(rl>f-^y__uS+ojTLi+n$)KkWAJR_PstAK~z_#lJ_TcNKn`a}kz>{U4kBvqGH) z!T-I6pY2?MiKqV)&HKydE9Y`tclh^d1N~(Sl=FTWfKLr@wQ_jn;r~pf4@MFGvPH`I zkUBm$67vHNuPyxhRr*+wSP*c&VU)ixrMw()ejxCr0bUI_zYzG!09ykNuQ&V$v?Knq zw*t-sX#l=9rECv4*_8OkNbCqWQyI%|jl|A?^I!#lg9g|WaCQ^;&H(!YP9-{~|9b=M z4>(8A&iscAa3J8E5(Dsq0S*S7(kuXn4e&$2*}*39qXB*nI3+afCzU=!+&>z?#vlMc z8;Kii=S_Nh!~i$j&MWA>{$C8R%yvrX%dZBw({`q_D;+h!3frm6Qhqb;udfxj&p?!w%n!gRm7~k4k1wa$uQ&xLwJYvjhl8N==jEx9oHr2M9Dj#*I9>Fph}prHBA(yh6mpv&v- z)GNnOjRggr-p?@$3Ys4z-+knQg64-vr{{u#E^nw~78G>)2*)faXnu@za4sn5^2R%6 zK|!Za37G{2%}J1m3~9E5;_NW=CxQ5X>NBo5{^dv;FheSWfI~a&y7W0+*`3 z!zov7t$xe#eKfYTX_KZ{>Wv74a}s6*H9+Z~qV1|TvWQ&{eg?5EXsqguQer#7Zzq=1 zhuBHPa+c$E04RNrlQ$VJW0&}8lmO&aND{ z`UP=WzwiYD-z6btP`zA_8gZ@j-F0-xXVVO8_AyU&^BLLYBZnhM3>Es9;OvDTsAk_ z`UM<*cQK7bx`X-c38(OdkDaU5xs>f8}J z9gR8Vf>Gz;BfHLnKw(5Qi9*ZWaxzoSojTQW?sD0zX!0zi-tCr?8(nrW*cGl7h0#ef z!QSJtCDF5~>Ry*EkB%X`%3+~6-$Xl-eIRtUu=P?#O&@DHtK9%Lg2{|vNS+r?>)NB2 z<*e~P2@_KrIqO2(J-eUq?9QA4bx*p5WopZwa@kyM*?N~POc^r)UOnxaQj#(jb@xn= zT76~Zy6*OYk-ikR(mG?Q-`U`w1SmDvc`eid6EfYDHoK9qqVKbMws@7dknC2MO^Obu zaj&~kbfPaY^&N+Ld{`YwVkhelMhc8rfjLay?mvhE(}Riwm-9i&eh6gzRt6@c2>n)N z+>UPQ%a~G*!7O7uhKfMOyjtk78J9*eKxCXz7y2?T!CczOXr6*lW;nSR5;B%ziW<&% z1D7F@jBc0}Ml)KV^puQ;a2(5+mJA;=4&ovpEu#SP=@}ak^bGkTqUC(+KLKYh@C*QAy zLrP_inuy#hjg3>C2TLw#VGPVA1&YATpr<%ga-5QvP4A_@71`2|qI7 z7dN2*=i*%XVOKI zBwWk_j=2fRIE&@-2l?1-^3>zV7pfCd?*dbGn7oP6$XD6dq45pFyRX_2r2CM5mD1%& zss*Ko8fl#+PvxjsGV48$4>tL1p z6pV~WE@gpl0DT!$)EDC;z(!x9lp1$o%@9=dDGCGFi6@E<0NR3z3!$tSG#OKe8XOwc z^}Y~wS;dV2Hv?VcCEf0eN>a(49(1399`m3_4D^ZzJ#C0qi0uq3!1D z$k1AM0%6Lpoj3?|tD>@BB1NOh_4$5Ty-9$&9!U-gBZ?+iogS)kHak;?d#K*Gf59bjw-om|YVz9%2X z$EDGH5RbAQ5Q(q8;*|iN0lnmvl;%sOE%Q;zY?kyOQd!cqaV4z-#*!YXUeb=ZlBl#= zN%V)VH-OjLr#xNKN|bUJOWNm_^mANE2i=m2kc)o0HF4A}i7pNl&wh+6k2O)c7yx^J zPdBIAS~x?p%5F#EP9#z#+ex7si0V`u+-d?Me=oxow(`QjFR?UebHYJ*6D-ppOmYL%CYP7Y54mphE_#^q^l{sFcOf z^Daoz4oW`}&n1!L-guq(cjF%40Xy5xkH|23yT0pc_ECDYaA$IA!?)z^4S|yxLNAXaq3061PV|MP(dsTdFg! z1=t!uEl_cUtKj| zjDkqDZhRhqt3iA-n=YxBj%Dm#?1li9PC+V5dOohC*}z!R{^}+D?3TpVq`UFu5Uf^S zBLMVnc!nwOEL~n>lvSVQHAgDTI|&lTv-ZGPULO~8JzEqvKy`&kwUYJ$I11Y4l{7|| zG!UiqWl3Kml_lL0SJIEbSkg0aEySowPj-m5XV4zDfO6G!sdH$MXS zPmnjFe~Kb2W#aa`4Cucj@mG)xj*QzQ+NNrgmF+Heg1*I~q?Bf}_ z2iI7IJJBG|j0+&8dtOMl&t6FF4)W|c84{+wun^YYFc)*%i|KhZOZU8ZYfyYudEa^E z<>>Mzqpb7d%j3)B;>)8`&$`%j_vAqv_PCg9gYF~$q4aZdjJLIQYrO#_FN!an`@G{z zXGy(W>~DL=-+H^nE3bhrZym~dG`_qgCn#^di=Ci%#FvC%=vrb2_*&uF@CxMFBLeo0X zM=Z=MSO#Wmfe-YLamY<583Y`bv)!-jg+p2F1pthDTywY zzJx@X0O`cU@Z*yD14wYL!v~I-{co@P_Ce6hcxJ-53U%@fL~ma8YoUL@d9@379`xWc zPcDU?1^5_9M{izjI+t=kHr#-`p6*8`?fsPrGsq$@Wr-W9h8}Xa8*7v^|;kTDAY%| zhg6Tt$ZAB0i(bAPyVnoQg78Q=Rh|c#F(7IA>@p1@4@XpI4RIl>hlX$u4bx!G_C=Vp z{}DRH_7^2tB^u_s*qrzbW+{fQay4za$wNTq)m53P^GTCl1#?AjtEaR2MI+2Xvl))S zsbpXz38-sL^T1t@Wg0BF1 z?J5VW*!o1)C6f)W7ZSUJBrtUH@%MzvE}S@F;guZypv!a>d>BMVK}XJi4ScucCl6H<{EdNy4v%qe>T0E43Ew;UeW5F zT5r77Gc}ZGHOEBEBE;!x*ZAH5PJMT{`rNj50P%gw)hB~0hhK4?t#F&0QoR+jxgCs8 ziEnOfH>@;zI>+_g%olXKIW-IIrk-ASosGeW1NI`gti~c+ZRscVin&O;4&WM4+0~HX z5-j^jBgB?(E41qT+UQpx@;Sf?m4)RlRZA=7&1Wj!Po*0?rL_vFH2FcaHBi}@Dy8~H z#fcO*RQYV>#Yw0d{l~l73|gZul90nn!~W&QN<~r8eh}87e!>d5&&utDRWW_n`!3+T z>%BGG=)v;jrHOaF-P_v#=H_<`WVid{$GrN?C)?Z-Zg*cn0e!nWaBh9x0!m??q@XNz z`?FIvfeV%(#R@)*Ulpv4UtchbvcXsJ8?XZRk}34xN?pg_Gsg?oXp8ePer*1PzQ>Or z!AO=1KRm$z-n~H{4n*8r;}r02jZ2p1CJSzjSKv6Z7Wr^%oH$mOVG3WG6mf5jyC~WM zZ;eOXTjSMGE8^Z7*QmKQ9&vAtYt-Bt7ZaW}Cg9fiLo~s?HBLPK*0_69JQ`pyQ!<^3 z5I4-l8Y56nWwbkvagQ|Cm24fC4a5eJts9*rsZQ*Avh||NgpI_Ok!=`#M%Yv-;oiWfRZ^j+kMvP`XyMWw}{6y@Co zG_Z|UHSv88$bJa`z6sMJl;wx7ucIA1rxfrQzNX7<{Z@s%+lO~PrB9rWd!?=2RJ>XW z_wAfE1z$rk?_`G9OeiWX1hsoIj!7;b4ZOj^7qf_VzHK*nAK8yFq#D{|{|0 zQ0#uHX-Im`Y~-fhPePSi=h@s$Y~BNK2dI#{B~*(ryISSLc+4GyCr{XKRk_x~+jZ16 z5J^h=T}yP#1aJ{Z>!=hRE5P3c!uv(Kp`}}&bw(@J!~T62>tWx@L8|+=Vh)D=gr^&2 z%W}f7UkCECquFeHYC&Kye%!I&YZW8fH#Co79V_b$ zbg|4rmAE^em=XzWlHVQpjmnOvV7nA1*#E?j?05?HiCvGZDa}%Yr-$+|KE=4>DL6PN z6;x)Wa%c>m;j${m9Z$g_F6)bN$5Zf3m-WYdWY2QhKq~h71kVmm7Sobq-0>6~>atFZ zJD!5)xNLHaJD!5WT{aTqj;G-H4sFAZrx}W{f+Yf-_t;H^v=L!I>^w7~_to z;4GIdiE+nM@M4!Ok8#IS@Di7;jB&?P@KTqp7vqkn;B1#|l*%1X!8t(&Ms_?gDs{o6 zv1OSZPrICC|v0}7Km}jQ}8M`L`gCB;o#LS8;o(s zQ}7zMcqhgkPr+-Gzl3(|c#3hyQ*en4J_rh`m!`;$r{FFA<~UAilp4GvbQT(TDt9~u z?{ppk%Ck9lJO!7#{~w+OqX7TbRmA)!@^vDJ7}c@f3U}NUgHti6wslM!I;| z%HWQt;0FIxKUWyy}GEZOmtB|Dz7WXDt1yjtk7 zS+e6POLjbE$&RNi+3}PmJD#$ZR$w5=k{wT3vg0XBc06Utj;Acy@suSyp0Z@eQ&!xL zr{K5#Q7}Sg*iJ?Y!{nOhWT!O1rAC&_u(M=_oh38uESX_v#m%stLcfA&cB=YAg%;o_ zhx?fRRHhf?jGj2%QvXtJT?KM3VESK%cXCEg!!iTr?vqhGU)Y%Y5*HdUIP%>(N$ghl z;6Or&T`zAlG0PXb5t!|Nvcf9Kdw@{3FG>Zre=VRS+VP>ug_H6CiWK=$w@9uVC^8Dt z$Bf84OP+?zTSK}2z6>VV{u{65&dvuS`xZHGHA!hedSvjF;ILaA| zy~)`*K^~*S^Iig5W7yLjooh+0|kyFc+ z{=<`I$1SRoE|fW_Q`?oRf%BWzDyn&!fhxIFC=010Xg8{*5kZ1nG+^=}3H`lPK{K-lUTTO(oRSK!*3l&rr$v4s57AuAF`IE}SoS>f$ zt$*nkB@)V`PjQW08Ao!|2}P+DU|o$jO+P%DuWrA_2GItj&jXFN`8L`w;qK}1T{e3dejH#J~PwhY1k2a(m8pr?}TQe+a)4zcX z)Nz&?uZ)cZWZabwlFEatSa=<*jr4K8v~adocYNvY z=wknC?vp-!E-S^z0>%4xIY%{7LFGO$+Xe|2;^Kw?2T=OtZWD8+7+8l4y z9y68Wy^@vH2uAjDd9AM`Vm8H#3iUkls%7;IZ9W1Dr(S`>Ud@WgSBe+P_W1o3re) zrsC|f^TqNl)*U{6eDa%AJUU&4(Hp6FCc<8z)*B3KDzyl%G<(Q+fP0}7{4;xYUkS-P*0sJ*-UDG(Wg9W*OC!^-x;W>Xpj~F()xV@Ox!(lM{+t zYVp~X#iyN6%*dj4KU@4$PgXE)vCJfVP{O*q0S>g71{JxoqP zzUkpgnS8B4W$7}SaUI=jwPV%Z^;D`?Ry*j)a->?Qb7e`8hl8}i+FJ6DE%^e1`Cdt` zl+1JwC9mDkLy1a9Po+U+gXem(Y^nt-UYfncXA8yXnOF}izY^*dY*ov!@h z!H?UbhdHb~+ay%ApLA*-04=66Zr>{<@%Lxm5h%dlv>vEJtsRarW~EB#JNebZ)F7ESPq4oOkG3l_S^OVHt~-J%l= zNsco_tbI3;l8I9i-ru-NOt=~;QZZcPe+7cKn3Z@ccC}6zztUu<_yS+bZX zg_O7cV6f`PYCtO->nUHLdlmja1f`>9whq`6~{|u1pRjQQD zF1FGWJ$P?(OcodJ!|9f3UTeS5+5pqjR*@3<1g4B^ER(pY=t8-?8cB)BaaL6-SmAxG z9p{zUf$T)pxT{M&(1wp%Rjnb%k++9Q4^K-|bB-zxcLsj1Emt(~UMvFScDfSS+l9ws zVkK5~W;Y(eu9WGis5dRxW#ze)Xt>lQQsftACQ>C*4&r+AV{LC)nP!8c^{d8d0c=oY z*r1qc#u^-fl%E-(j^JyS$ur?OP8 zVZ&enf>|mY!y2PTW}2);wj43cYy9#Mt~VJSZXG*3kB1h)MFerEij6PiqCnt?ncV|P1GMs)()fb@A_!}95< z&Q-?{d<--!*G6@!@>i^%U2m$y>Dp+jovRkjF3Y34%rjA)cGhlXh65VB&qmz|Z2s(` z-7t_TM_y*F5p>*6IrF^;I)s8u1xrO05XzkMPNh(yfEg+mYh+08vn4Xg7d1sD z6Nh{SQ;$ItO?xBMnPUiv?j5++hxuB%NIF5>e*q;6Pv$YlswE|}D3OkHTayluv!#9q zy{?(ULCs9p#W-F6rEbH;E%I1o%4YbgsBVT&Mc55k56`w9o`PU3P+!flzVcN}D4Zyx za<28~+mycs>_k<@%HMKySBe!AY>99@5?2z7Dp?IgAS2AnS&79Kl&^PooB}P-U#ye} zch^$6oxlgbz5wco#-1YvmAyBEicPE|3U=@gL{OGb5Fyl!+fW33MX3A3Cea!) zX>CLBvIunt)g)R+gk~r2Y(^;Cud=Alm+cU>26E}4X;f#`VPuDZdUC7DG>h7MHWgiB z^WShx&{%j$2XMupxB)C4ong!M45!ZqYE3zrEY_0B@w%-h9iH_XZ+{0m zwv+AHhI7#p+Ll4ulZx?Xc5%&om~t7T=h||rI3=5q{n^SAmlM01&1E#XO;lHZ25cV7 zIB^+u5r;M-3K$||@%`f&$&!8=;S<2JUzMTk-$U>=u`jOpBN9A!xW!B_N?&Gitt(z#A1kyyr0&k=3?L24 za$Y8E+$}eO>*{a#&HdGEbbWT86OsWk0xo7ku{!}jP)#S`M-V;;^7SU&gVpqQ=(h;A z0c-NZ)ik>H?m`IE20^hc|u%M{c5ZRU7juS-2z zt-1)WL2#J}Q)DiC%pUhBf}cU5O!TX4lLhZ^4GP#b*{W(0seK`W5hB!6!m4U|IqiM~ z_lU6ER@bXlTM=v$p)USbRntlD0D`YUS>AjOzN(sDh$?)SYoVa*0b#VNT75ZCUj$u1 zVfkpKR327A>db4?6Vvf0aB+ z$=)uGbFW(hjiUX?-se>HvdZkKN`9d1ov`kALUJbC9apSpvL`8!dcVdM#MRqKu`EE- ziG~<)Ipgo4KzNtN7wEXpB7&q!w||wir9^n2ttIlCc&Fq7WI{{=-8;P!m+~eE^G&*q z%e8nml(SY>QRI%fxSJFm!8gq;Jk%k zJIEi+twB>aT~`{_-sh)`Ab&Kn{Pd8t)Pj5&u#PUYjvj;HOrVY~@*M5XJ;m132Pyvw z*fmday3ReVKj6j!C@YelF0qH5fuI}|j$uDolCF1s?f}iPdi-*e1fx zx_rYD{9ki7Ckaqgj1y$^%SWc;I*-vmh!Pp&<6|XG(Hzlclw9S?X5#m?$fQf}R+(Je z<&>bipMkocd53Ztb8F(-`P;4Ynp?*kT}6HGbwaXL``lAzIA8C|j-7A-36TAiNYi0l zZprfn4P-KDc!SoZ!Zk`xEaH#4`r;R}F3k?$mUr>0FX*(!8>VR^HwxCL=>WbO;T6C} z!3$}61L#2ncLAb+TjU$kGztzN*rP&ZFQ#b}lzqrO3SgsPW10^C5eQBL8U?SUop=V? zl&0ftFXf*D8wH!vGzzjm;!Sm+>|5#FSJU()cP@g#BAhFsvDtE&i{NUYp|LqlL*o(h z_lcs0#^y8)jc*WqD#Dwk_Lejq*JU5W8Wi=zGZGq;8hYN<$%oLGLy3gOHL((U37Jf~ zOXFl;Ba_}-r7{`qPLc0!+dr?zWU+9O>&Q(hmMZ()W^6Rc_?}0J#NKaiiNxNsZeuz0 zn~0U$L62Kg=CRBii{x zJ~d8%pzDXD5nU?WN`A4(bV+hFqPM4BLGUuLibfu8@8E>@# zg}OXC7SYIQg`hboD!_hO*bQ&2-E1%WaP>!?9~huJ?~Z85+HR_+v4+k25QMUMUlb>7 zdL=@=fR96siQr@rl4$=Sg|3jmr?FSut0?UtWdB0X6~gsLD>;oz3z<|KN-PD z5$c7W4dMDCY_rce1)!{@EFU(6%S5;h!K@-kx6V8_S__CSyz5dqBKDpF%4MoyDMemc4yWz*J zj?PX$Ba@pyHP|}JOrSTq%OhMwyoosoVokNcz5OZ^L0bys3XS~YSeFf*oua<3>>Mle zm%q;8&PFH$dV(kX2;mY}bFL@chVWTec!ww4fpC*seU&GCAK~k+<|a?L8DaCA?SVeC z!qn+bt73i?So81-&>s@E4~!nVf!Dz?r^rKTa^|%2#<_OhXbhhQps<_?l274^ z&1aJDqcSFgVc{&1%^`oK$QUf=+rjb-*;OLahf0Rq`62i%9~(gEl>Q}-`YY8=UU%QY z>ywu9#t@3l?~u?7RDY-H^|%`lUIQ$#e^Qmi4g{|NJ4gD$x`e6u9Z#i#!ifxHzn!{< zkw05xI_n0)I_utqV1Wo_ya#Q6Y$d-L6uk}^;qW4exn55J?^E&;C*HSXC7g_*EvMMM zu1rn~S;+o%Wv;ZPc)h)AaV}mL&wt1fja>Lsi#u40|3r8USc^NR>J*;$UmgJhg)Eky zPu02lEV3OybDoKPK2@K>Eu6}e`DD^%ir!1vS5jpn-LfuK=di!Y9~IeDm4#)S(e(h| z6#>$F>r$(U=zg+GMMS@^Pfg!RmwiKaFDPmQZ&@dN1#NMVJRc&D#L9A~gHv)P#Wg9W zDCo~w?Z|z2y^`Fpn#}5pQz$Bz;5V8xa-&48zcEGoyY4}rMgsQw>rE+o{q<}F z{ee)dNKs2}A-hOKTp_PW(Wi^wBD+;Y_~_OYeXg(8A;YJh5Xs%d+fwx0Gno89&@>ee zGG3Zyxe2HAAhVSjmSW>F{dRtr3C5#rWXYvG&$m1mBU}WU>xyDziiV&@)Tk6agRG|T zaZr*=6EahYvxpC;^bZMzUqbGgn`qepUP0AJc2x6?gU{Y7qyl5gO>L#2p0p(`(ev_J%T4iD8ud%%lmio z$3#Y#JsQ%m&iH}dBPcq9)@2;^pz%smI4cgPK(2|OU$tNY1!Ci6ZUKBtZbdd!3o znKDgcaiD98xIc%rTyu_UWF@br46>#SLf9YV>qIsCLD9W5CD*1l zcntKRHJR4dxFyOfi^vE}bGnoe7Pm_{kL0K0ayGmGEuplZ#*74_(ivsxr2fcS4p=&) zlk@^l69lC|cah^PodM+gf}(PolJi`5T9N}#tL>C5aAlg$g1`?mAkaF=jwd;hTm=?T z-H0!>GutHTczPV+!=OWBwolSQ_6vdoB4j@8VD(!6#5@VKe>+-> z`jYPriaK&g3D%!nqI%OumT+fKAT&}zWtX;aN`_M4bt#?cl#UQihlAD(nRjG}oloON z8dfuY45}HoA-oziIw-FHDX1~o@@M1J2X^oLOHli@0>QPw?!12q>T?&)5v~As{9t!lGy=GI_Y*8&@Xt%GbzbUisUT zwIW=^83!nk{bCLVi8J((FMaaixZ6yVScy|o7yCu~1Wl*(Y6<;~uAlz6mFe>~UaSRC zBUgIVPp?=%wfKb>%K>}0Ws`NuMg(g>;h3pcaw*9QYyQerMqvH4#ro+q1g(MkX{+_q zTjbvaMKd_4IAyO(SRWme6J5!jlz6oD84NxBHTzg-uL#;<(uEk7p(4vJ@u*(Vy+5c| za=xMYuYhI!Ku|A&WE^Ey1UgC{vZULQKUrjYTjrslUVs^Zpq~i!7Rp1xOu2KlBfb6I$MWclpc}xW z{5HhOt|vcBWXi3d<@Pm#_eD5Wrk;L5y^qxOH{-MecKDqh)ZsS^!E_M{;WI4ZXUVSx zP4~F2FG_-^^udMD)Y*W)_6klLO77|8I1Akp8))_c6&@EXndp{RhL*h`NB^-nmGj)O zfE|e93t0&4;K)XrwEp-lp#Jy?>9@f8BgBG725jOahCa5IAEfi?55fSOtV z4{m~i!ih6jP5*5*$08UeLb3gyfDX^) zVFmK1kD_}!T49UhT+#!DqdDJo4%iu&{3emHyzCOtlTyFGjMD>H_jI-Hc@n`AP~?M$ z%$0qiAy(5(MW?#5;c>F-UD=d4*~7@>j8BYc$>!4qwWY|Ag3<@vD zF+cd#G1YiEfFG!{e(>w^{4(+vicGzF*jC+l1k;w`71uILQ=E&}z&GJT9c~_-!$!=ugCwvl9bedf#QS_nf zm{KM=ne1euYuwchqK_=$63FHO>z0qLWs?wG0-VyG(#{&c9fq<#ldFa|Qe?z9jmD>K zLr)`o0@&br)~{phLj-Swq5`VP8EPSi_kyPtGPx9UpUUjYS58pe zAW`(bEsza25oDj9A4{2p#!vB;g6?zO6WzjUFyQF^@;jxX_gwc3x3t(R zvwcufW^(aP$!53s-$hQthvmQ{{7L4}b-bE~09{9eM($HLkRdhF@-+Qr$2rDw`3H?Z zfzxb;c)ho4=xQ2}MkK=J5_~>2`q&yx0zRiMkVRELzg}y6oa_T4QiD#n27QfS4{%C< zlS!o%TEw6ep;c-9SBi{W``5KiL%*&8+XZnS$R8!QRU7$r4Y(4)y+Bx(Sq`6&-3^>( zAz@wD?_T#=#LJOf)^c-1Y81G3qW!znD6K6{^1F6Urp6)AI0-hg!&f!|%jR-~V?YCC z6SQp1S<-6Awpy6%b83Ua(fsHuBqj> zavfq8`d5MmW5#nu_hVlXXE=UR?lc=L=Dq1QaVpiN8EHbsbN*QQLED?Y+HcXs3aZ}? z@~6s=`QG$37U3HRc8G8cUzI}GT6*9&1V01$+3_x)ZdV$H2s}_ol=?PjP8xVo;o-C>WWoQAXp_r zrL@^sDwK92*aU>q7N4FwGgEv{25{<+5H~)@!Ad!h98eA>Q{m)?p z_Mea7ToLNQp7S-AgDpldAIQO;w+Gu!cC(1Ef1P#70kZpnQ-6WT^SINWC|{aqZX%ZbhJP ze5>QfR`-o>lEzl=jc<)L8++rMElvE!H&ON8_|}26Aoj+$cjVyi8{a-4ZQuBo6YYu; zUt?NdpD#O^nX>XIPcffkkM~aoX$`YfN-jRJz6lTwne+ty$ z!h>T5ghlof`ENn)lyRJP2CA%En$Kwuc-`6^+%Yyi?BVwCBY*?o3X06*9Iv*#LCW+v zN&IyW!ezj6=+Q|y>?FSx)clTGQlY9zdPm8%Pk&30XGRJ&UQr_47E?_QdYCqhJy?U* za#H%YCfkK;Fd0J_?&Hh zVv}UrOgl-I)}qw?_vz-UlcYC0z6Nh!MeUPO^w|$Ly00bk-c0Fz^jW_L>3;j!eJQ5< z?z3RP9n9V*A4kww(hdCaKKTeEC+TkfB<~eB)s4PFI_Td@42A-tm|~7l5U8GJ-X~{5 z0pXKs{uJ%j$z~q8LpZe6N+&c4tIeet9j;Lzr8VV@zYO8cAo7FMI5|_=G$!)69DBPYiao}Mu9|_AVV*-zO`Ha+4rM*YJe3lb=N)#S5emQ!|lEC-A zl+%fSJ?vp$?6A`d(E8EK2g34g-oQ^@K9nlo<_-Mp`HXN`I{9C`d{$V# z%^UdD%jbmUtJwj*&8w~{$_}+B`Qq?C(f{2SeMH?-8h(JaM&J*x zym|Or9!v}T>E&C6<=ec0<6gdP_y?)~mv_95Vfi+1;BT+IOIW_m8~De|_Xx`;w*!vf zJznpye497Gw|Q;1^baSek@tD|LE*b2v)N)-?eX8_z$r^=#`HQ%eQ$0 zNnUcNU(VMNVt0`%^vac8Q~mp-Y;H0 zD|NtG=>O{Fb5i?=@khOUZfYNi>0@5LAay_w^1pfc;?zNs|J}=%I*|_I{XhKvp?;>6 zWPPnv@NRPowxnN8AUV|r_8i10^gq*<(R!c1kOFtEb+wZkn9D``X}aA>f0E8I>1l+l zFMV(}4tM-h>oSiv@%Kl`tJ2ckD^-?PlPYZ)9~|IM>L<1KUqeAg^W^3!;~Blt3)(RK zwq!N0BR+bVZb)wJW&_dbb;!1Jv!Q5aF4>N5HWKYj94B{nvl-Dhq_mrx&5E|ixa6L0 zHYfT37ypv`y4l?58L&t`-OUz6R}LjRz|9s%9Y$30U^iPD{gr7W`8+q<#PL6cE0ah1 z~2r*9(+`RMh2!ZZ0&UpWx#2@J6iN8PE5YJu6URCEJlZ4Otzx#Gg{g@ z+D_`;mVd9-Z5zFx5Kg|m-dfFejLsLUmb%$4(PvYkP4>^it>~KjdbIIn@I)xn~7xnAI@J zmOseWqf|Yxf{ed0_9s8$vy$~ls_WS$qaf5YWk51Md9qy27H$VP(dUqbyf_F%ci@bW z7YCtejq}KQaS+is2=#I6W<+b^lTbf5n-zVSxi-|_&E`axG8Kjfx!GLD--jLxo$G%G zP8p@4;VFL$n{(;@&`4LwiLRhaLgU@+u<6Wv*#>-g)Ibh>kSA#`kV7BlN`Fcqzafo% zTvr^*ODCh*Lip3XEvnov+FiQz^ITa?_=@^R*Ncn4%$=p#0nu;85ntuKPOnJx6*1gG zdtK!r(GQt)Lf^Q`L!-aUA^WXcIxO0tI@$l`UjkiU(a7k_a@>Q(S7~-^^iKjg^nL25 zN@INVAZPN>VK+M=`lV!l%G;{Pog95rSRHY*TFe z|EXCyN9hO({atSfCi#ozbGtGirThlD~Zma-lb&DCNT)`6t#E6-pqfN*L9ZHC6r$T z67fPMgue2ckIpQhyq+QPG)TycTFUEn6t)B9b%?|Ppu9|`&-sT;9IrhwUUybY(Jnn_H zLY3DUoDwMtu8>HIz&Lv876Dj)M7&Tr;_FxrjeKml-Knn7J)ckV~7dsuRfO7eU#q=67fQXw_RIa&!V#yD6iK@>;MUQ zQA>G!fx>4%c^x6~6Hs2EY@d?^;zE5E$N68OUV9Mh2;+|n?>baA<5~LH@b*`0E#ci6 zX$KGs+Wu%*W0R`+Wxg3t=>;H>v8ZIAubpr;Ix~S9dn<`sKtf}wrN%yj!b3ofeTl>d zpvJyS;%&gK3*Zc8@SbR>)1b{f?Ax1OdHRw|hVNxMPN|-~_NMFE%k;PBt#8t+OWAj{ zxevsw?S#-;`+d5ejZ#^ghCm`~QTf}mHXoflpw_k`(Gn!ImRf3U9~624wRSj(VL+{& zO5!rWJ4D4=`DZ!(XgMvSYyn8b36)#1L3`jHbnXJmX)TF0AR#AeDW@GMYy-;aGZLQw z<@6JY!+?L)1K04k!J`sT+p9RdS(fMU?ddvQn*K50E@zcz?Rd-Dk(A?e0w9qcs0>A4 z?WluJEueNZC(#rnw1Zk|M^6;G1GQr)i6KDkm_*`I@GsxKYdOuQY#vC&36&o_PRr0) z3Y626BvyljoT#OowxIATP);9_*bS7^_aqJi{?!h#wl@#OdDW@KFr9^4>tqr86m^uP zVKLGIkf*`@NP0~fyQd>K4d@B3tW28Ao<*JO;+h*tx!DzK?mFAte57-LZSDr!+!F{^ z0c~!GHaA6@8ywf%Cdy4N>vhX+aC%!|w-4zaV4FL~HkVeLlNiwEuF>WiNC*|hHCI5n zxg^$Hk!`LA(k{R@S7MvH6u~7RuDQGAI&CDbxjB@Z4YB4T>8*v`N~9}*Z7$t5w+q1= zK%09~*`3Rt%j`?5oKf~rZbox`#TvUWt*JB@szc8K+uZ&%?TY>g&Jf`Xb7|zewEQ|D zo}oi9Mua(Y5dPN+7b3V8=z>KKd4sPn0Auz+=z4ouskLuy2S5kfArc2b+_}6N7hEi_#g-SZ*mwRxClN1H4tu<6qn8Dg zS056+Ktf*BQeGob7zUKrJQ8z&@>)vbb`ZyFM~v4kme*>^9|wtep|TKt_189ZUIEJM z7ZN{%guJMwyux*TPBKtlWh5E{<<*Tu7ZArwUJGaab!VEMAkU$EFi6A;m3;J-*93Gf z2FhzLiP<0_FKQ{TJ5X2xl-DW}j{)ViiNr?WhO4aQb^P!oDe}m_fbpT*Aj)MK;1Wp!~me~ zyNJYvAg){6V2BY(TOwbY>gD4YS*pm8L| z05#}J5;Fjf7EZ&#eKB4qTV6L)ej`v`z0q*^A~Tmifk9;i`pWB3bRGc8>q8PB0LyET z=sNOus9Q^U{eZ#&pu92)eNH-1UL_=o0E?h0)DW-Q&hKbDzddDbfpRLRls6vocLp%1 z$m{2n)0ya;4wTba5~G3Tbd~5j@^_9~OF3PE!sS3Y-9%zBP)-k$xF1NL7tN#3i{plz z^!abGJ}x8L6t>v1MAmal)M2F1u!b>XiaVS8l62rZ8%2aSCBA(siihVirA?F zwV@t~e4sY8A<+u(uaWt$OhX4F_M)DMKR;{NhR#4xd8(T?n>;*o1PJlg`i3guBjaFbp%*PfJZ!|!m2&gyukmv=}8^cKq1982yEynA^h^`i=Qhpgo z#0!;c(N|uJ&{+VK*F7Ze0ttChOL?tDVGU4TJ4kE;%Ih-{pMZaD6+g9{exmF!NW=-1 zT7@pBq*AuIKsnVRQ41vGL@nji9EGMpIrSvb9Vn-vB!&R~H8SVVAw;ITA#&xTPN?89 zCv+*LCdzKYo*$=2x=V~yAiWXP`OjdjGjI_tJcHmV5x&e_1{xYGH=sX6@U95A&qR26 zq^)SCHS{?tpw1cRs<593n;~cnN*?CWa+{&(00~(b$!12jC({V<0Gzz-3VCSvlrwrW zm$p#e56+|^a~;brOS@U5gV0`z^fr(;xHWZJMD)hm%LtwWb<3%@036|Pc1(AP=$iBh zr9T1fndxXaj{Ln67*w7?U!x_|h-+v-dnS)W9bkKAmgqY2cb;2Id!{7{&4KnzFA_b0 z_RKI6Ljh5|ni?Cy4cuO`yaribmr*_mD6c2ca2)x&78q1cLtl9INfglL)U3ydd(q*zTwRgYaSsM z2vwO)pXE^Y3gI{5<`QzIKOuU9s16R>bN3<^FjD1C*qVFmdm%bF+(z^_B3%#iP7hM& zoUn%IF9?1V;l8N|hlKThSauVilL_*Uw?}wxxQ^WM9e|*f2s@S|9BQja%Y04{*hl-$ z3)hfmJuX5p0_5E%<7b%FdWsmX9wd01kWQKhD(UXEaj2y1YPH91yz9fE~`=J(7&{9Wpa>nCac(pdA~rM8nU zSV@JuZKXMLsq{{QN^g~VoZd<8DV2Vv!T}IF7q&ygj*8u>dM<3=j8!m5G{2+rJ2Z5( zo{7%sKu5(`5~G0~72*}+xyCWn(ot~*3YP;N6*rMs40KdHNaB9*uXE1FmeYF5o(G9I zp>iWOD5qWMyaANc*Ch6Ugq*0QoQ|RJD^O06<}7i6a;irnAMmfSnI!S@LIMXjYveij zh1A~S;Eq&j1!4|f&O+Tf_!Vo+d`jnmM8=>p6n!;j89GaW8uKKH)gYlU)KX)%pztbC zV?H9W8>lhglQ;1YhldlD3AQ2~2e(*TeM5hK&PEANO0tq=$OF4B#p)*iUXOkEN zl+z_7E&}{(V&0L{?o+8rv9OVlABuDBEcH~Xo)~qOx=<#9yQ=iXEE+PM8+)B`S88AB zjE9ll3u2wo01ew24_L#0p!5((WH>6{!azI2-;(x$8lFQU8zeNGT55P13XOpp-i<^T zpoX7AVlZ&m!Ln*$Dv!HW%T(M$W|@UmjJ%jirkJagcA8n3+DDAM73uXLW@H2nYvfJV z$WJK!2qZERl{ayU8hIFheUCs&GX&9qoxHZk4iqIx{#L{+&V zVO5W(baW4*TifF){bX~Z2Wc(Qf3QkTx%Xge9!$~IEYaV@JUa{3&#I`(eFdxfSxOIk z5L9bRtGlYG%C&Z@y36B(D&G;{VtN%-xiD^3H>R|Wwc1?>JXJ+iu0>kar&4rxrd+E@ zSFNa`Dwh|n>WUOSkE!Z8!nLA`s$2@Qsugjq-Xg8etD<^sOm$wY)iN_xTJ0aIoK@Pk zVgwy;<&B{Jp{8QjFr-63-tW@c1LPN7JUoWrN)e8i;|;XJ?-6`1!Vkp@gRJoU)|?4J z-XV$Sv#szA1TTwllSIWiR(M7m)`cK8RM$20hU&UdSdKc8(g`5ZP(|f(^mV8%L}xD0 zq53?DXF-Q!gsonoN8I*@1w67r&!^6HPm89;fBBQXXjuPaH+04&>q zBM>;(o#ffnIz=BATS@5yAdyX|?7|1? z>le^j2h^swNW2LW+C(k2X)g+20k!Ej5=VjBl-8b0av+ZRLor@$Ew4h#3qT@XsEk8j zd38XiHBep`lNb*Y@}idVnv25KKzTh#;(nmK){}T1#PK=>kJ=dMYI*IV{0)$Z7b<^w zyuLZt*P*X5atNIRK>NaU zmCw!frPxMrM#X+VGU4TyGgtcl-EHL{{?Zpevk1wo~+kQol|_y-{>Ubg~|&auNvr8 z2g<7viBgb|7qygEXB18W%4-mb0YG_OMB+ja$E$*#w*BZ2DX&?SUj-8JLgg&<)n7}| zsQ}7rJBh6zAunnvug_8V7$~oQNc;tqS5_yky#RM!jSUA`ls?G;-H_D~7FlHoADv4G z-&-Yw8_<*)(9R3tdy~6L2oFZu3&cWraa+&y`)#N^N9i*lk?E-PLtjmQ9i5#(P5+X_ z=OCf!)Kb%bLE&ehrl)k~jy_P+>ypR?aa~djbK514*ibo%@)jTwFI4te3yvK>yk#MmUKzDN|$^_Q)XR9 zuS>$ox};9(;&YBulJ~Z(>(i2TK|2KD86ehAt+*g({gGk&>26AwgGBy7MTQAunnvuPacP29(!bB$ff?wT8r#Adc7A4xYcVZTxJbd<#g#3zcH@mDeZe zd<2x&VG`eiguJMwyaL@=k^|*ci$qPJyqc0|0^)cbkMZhgdG(~cD@eo(m6tqT7ojr- zD6cz7+yN5uqL%V{3WZfbdA&>GZJ@mNlh_C1c**PMY33*XVc@0J3Y@ocZB5@^9UKJ#6265vpwlvUrPxj80gX|{R^Xy1E@zlMN z`esCDZ;y{Pm+U+t}lP7R>;HX+dnB(#@W zYHwE*Is>)$Y!ZWj+ItC!i$GjI@KKRp2;`G)kaXJ8f^I;b+PH#=p$1J8J zodRNU+5`=2-|aRY?x1uDNMs)>hdldMq4O9}`!zi*B4y36`Ks~5``kcby5^U+tom!Z=DD6e58hJu8=sHME7qA&?4uiHu729($1 zBpwC-!|#{P#qTYu`2A({O~W3Z-&-W3V%4MkxHQ2Qp4xD=>;^GVDDaenXE&EwVD@>)juQjmxjD#txu zYtdN^l-E}zz61$*QA>IKhQcpEdDZU2X&or9W+ci$9Iy9dyxQA%=s|fmkcby5OVC$; zor}&nKzU6hF##mxMJ?rZ4GMFC^17469YA?KL1Gn%<0UVJv*V|$<+YjeO&}33RGOf# zygo(e1E9Q8`|=YDkdPO(lvh0z@__Q{PNFMNUPDNn4dQqOh(OEhJj?4+$}a(lc%ib@ ztIY4+K^JSsuKk@Jrxq(fCpF1-AiK#O}d@6M%5c2wzGxq)&=Z?9{21ohU-Zyf$-5bLma z>3kc^Z`uxPaysiGkjOEpRG_bp>4{EfppGdgF$E-a47JoTH=wW(sAHZWu?nbTHj~%{ z;yUc2ULLRAL4E4xL&`q@iFl#X5Pju!2%Q5!d6_d<8j(rJi(1Mn8>K9uyc&~e2$WYB z5}iOCFM~&|zdo}58cg{>kcby5uX?;DqB9;SuX{+`1rqY2mhyTQg*8BV?I!U)P+kW~ z{1^P|HuI;JlXE85W++d@36;UvpuVbwUUi_HdXqR6B;-UbKzT(6aNh&` zD|TP9oa$3n3=(ldB})7#r_SiK1IlS4i3uPfCu%9DYf+dBl+z<59sJTwl$wG4yx3h7)O*Z-B0UW3v$2bU{p8u$iwF9gk-$D1yC^tJ?(1zs@FIxC zZXepR^T;wgzvT?#E*D5-H!3OUtKDVjGzMySHxgYyLc6J@cAta7V4!wSAaOBJyXTUa z4ct?WJOhsd2F}9)-KscX32J8a>7E0+1$A%!5z;q-bwIb^KzW zQIZ(TMk?08$+D$FB zdl(8sf!ci;iAg~1UO-|#;9n!tau((;tzzynN=?81p1n&0x={Wc>AS$%yEM>S`n%&$ zhyiQw(!db0_W=ZViclYMUK+Si9zr;V;0Vb3LJqkskS5jZoX15fkk@M-!sP*d14=&x zr;70BISB6x=o6na5nL`peSG=ufL?vR2f;F+Ye#wPwLS-Oh8B9OOL>*H{nV2_@ye^V z=}A80A(kge<6Wy*{vwT;^Uv}u?;6mv_CH9E0Bd>Iz?st1qla;?23X6x21bbG-y-;2 zglc)$z(ldU9qinJ3@&e92D+cYXPGRNc!YV9hm zTqCVKG{Ebu+P==x%8N*!0(JhXu652BMGHA2xcCd|II=OU?c-(Jjx!3uIY9j>4=+!k zEq7a@GI@w@P8FFrWJ#q=xyrNlZauiRpTi;6nGW)+#xYFsHxKx?H~KA{S&XE~197^5}8=*)fy>7IB7*H*S1 zbIh_TGGXvUr7Qu1XTvb4=Q7yO^X9!D=e=g5U?49VvX39uGy3X`%aL9JibAMJ*CeCi z`Jg#6{Z&SstUWSe(5zBczZIW5zckkgsom^3O!I<&tYv)IuEJ@}286bDET# zbU!;#->5*El<=JP68^Rth*iEOUISLYNuWcee$zm@>O0)tcX)1t(|EvS`}u4Etz9(F zzOHmO|C>3!8~Cpe6z2lx@{qhb&jhM-rpsAPN#5J@nc%@9uIS96wd-glXy3RU3?ye2 zJ5H@Y@FL#+9<(oz4Tb`5agd;WziH6E?KEg#a~kv|@5!djzU`Fi)u^7ag4TT(nwn*_ zp1hNcziIk7Nw3B!{&G#%4)`DPuSXbNj>036sgewne6+eqofOUz&Q6djt@xcfA^!s@ zhe-Oamqu15w<7KMZk5bq!8=I@oa7dgd)zP8aszptu0R-aqK3u$Ju`UCxYTfxKSL={ zv(^MjCzB3F(xk2A_pd=-Tqh6p@HeD$THip@H$c=+t}baOX~ZQ?TRn2Xca_N7hNWuA zcWj|#vLqAn9oLdNlF3NoYgX;TycW~Ra{R6NFGc9A0BRS9O2X#iQ|kFR)J4LebBa`S ze9uZNT{IK$&5)9=nhE*FE+ErQGZEh_R1b95Oos0%$@I`nmd}VzB`2SJt^m)5%JBqnasVKNlzLv`U2-Z`Khmy;cF{eE3`_E?~KdI zJeYZXfbR1xl#)kMrPB(0`w9ENV|iOBDfSH~A_A-Oek4=sTP}t@nN~f>gR{QHOzMHB zQksxyo-|_GXlJb+rWNVQ&NE84Bk3v5vwFlXzA18$bv1iao#_&!!+eiOSG=Y^9_vIt zps3#rBbJ$8u5_HMjJC$B+h}^O2@mI(0h39cxh6|8A@jMG)Rj!cjHCWFCZr){?w{v4 z*P4_kXe`TIOvw!Lv-bEnCW^;9c!BXyQpwYH{^lDkdh6G}Roc{H%n+R(+k zfZ9W*<~~Y#n7L#gwsm?teu*0$YQj7qz6eO~1~jWd?_Y;7Q}RqR)g$m0f&XUyXvO^` z;woy^R@_KQrsVxQMR_spN=U>hizr}~e-#x;N}yD#IQ|^+I`K#h=m6y>brSh!d3j>C z(X~`cH?`#wq+bdm%jl4tmS!bsGoR9vOs1syVltUlHj`v>849gU=5Puk=5$Khn&SFo zGMp5VJxdMukdd45XvQ$UNkP)g~rKTU5$u`s6JV)j-n`vuu$V{=BE~WvQsW#KwNs)ein1%xcFt{^vwE2BCiiMpc)PbGz|NDS2D|{6TTy3K;Tg;+hgz$*(h&B$d|r1IH$J zVUQ*_%{hu@@OR*c)X?MvX=`2}ttRYd&E;%ldq+N1|)Jg8j zpG_bnt@xc9vgFuD(pz%WB^_IG+(J6wq_|6tP2{ozDWB0ftS!zbm*TE1q*98zw)mTL zs$E-5Aeg~~aYS$JQ_`S7-D%!P$s@b)LBx7rf-eh8H3(0tE3$Zx1wvZ~ZwZ$cjh1lBS zM@kC3wZ(mu#MTx&$i&tb2gtsugLU&n_BWeF+{%D=e zqFz}?v$oE1(OW5c^Jzi?Ax=+30ju|>s7O-6qf*83AErR(73p~$mRv-YcrW$xM6I`? zC?g`0rJ$!*=yTF!b(LwVwMOKZvaq|_SW4PkZAdz{+K^0awZV11%GJhLG8s;?$mI3u zE}gKu+W1ZybXOZXBYCS0u`9OPkdoMHL#nXa5Lwt=ZCpp^c&iO@er&a|Pg`+U8`HE9zUV1PecVlet08bLqO zg6Ls$&o#AlHHys+3k6f-JU1e?Rk>jo+tTqd(QVmCe){b-JWO3xzg`$&r{`G z8EBe5iw09yV^g49(?x;6L;iOW*0kqJSv}XZ=Sq<}p^NzQ6-c(*^Wsq8fs`OFGqODo zxZ86h+w;I+TE}l*{}!KMF&!+ zhmj3?aD8+PnO-TfVGq8j4fHm$V-LDJb|X9X;47)iFm8~M9eZ$lq!&bom>$=X*_keJ zJIu(AJ?QP&tA9WdJ9e?oAHQSwyF2zd95mo}ckGf0`Q076WFr3f9lPJ%v42csS^kS@ znH_r{R>wJ|a#jtpV?TpjuHW6U%a;fW{P8<>fBcT!@9x;8xh8&h$3BKS&He6!!Y4iK)2!@h zoZuG-nRH~c-cZuP7x|-g(r7)dj%ID0Z$wYdjA;+igakvJo``fq!URBxHYFiasp16X z`$akfN!RNLWm_VFKh?|Q=tkFa6!z(p2;HC*RCmvu+e!Q9Q_4PF(vIKVr%NWu@9xuy zZo2Vw)MESekjQqUumzQ>P$*{65|9?$f0tgW3R(SWy4_q%6KQ7iSk`*g`P z_q+Ra$+Y#m`*g{4@w@wU$@J!Xz7W|-!)kG|(@4&o6HM}RAqiizXAvdq!pSMHH47J# zSs(5~W{>G6nGNAf$?P-hCG%3MbpChdJgM_?SS&nbzF0tJW9DWW`>{rUN;XZQMyaXM ziYl+pBi+csG(tQo16*58TgIY35G$@#{Nd~V)7?dfymIS#QLRU-4rSd12im7s0 zAXHi>2dz}OERfPPXCZ~Da#YNnCNx{gdc%``S&NlAOnG%@!{ z(;YNZW?G6`N6j=fGezwb%``KgOQw@%nwz_%PG`-uFqcb77tORZD8_d9Hk|TO=yP4b=-+%h#5*9hLtMP->qV^iMCJsaPv(zQ(y3s4Oixoft8}PT zmU^5_>1Byr2^u|!vH4rQe7+O83Cf{J&I^c49)?9~rAwzfri)~1r%0m#CvvgmBDvp- zT7609MJ4T+qU*@iwU@`ur8E}F*E%65D2HKL_8wR6k^+GPw^7yyg^_8Sws0%iEM*L( zZFVmJUrn27TQn0eS4n28Wcwb90Oz zQfaSgrj}_ct-Y?9+9{)_UErj>5fTD*%)9Otd-kNUw7kh~j#RDGB)uCujA%HuFT=WqM$$i?P~tY5LPwh-mHBPrHXtCp0>RY~9bMs0g1;Dp-BdhhPK>Ga!~%wF%CJW;+I z4og7p1(Tf*Of_-Rt7KmQb?(BX-6l(Xc7XgBqQ*tN4^4*nPM6xS$&kyGADc`WZVSnu zDYA*qCniIBY%)h3D{H<>kyIDSgXHcK$(YH`r?%P`WM2o_wK(EurkWg4zKdA~@@~b# z&rP=Uty~<;`;+_^CM*>E6~D}CdOLM|Uzrq%gSziv^tHYpf=;OJIP|X3WOxX9>E1Ka z7>at!KEQ(rt)1|_Zo!3aK{>?(%t=molUs0&EeQHst>z<-l(lifpHOxttv%;fx`Il2 z-I8)XnI13$gZ>nDV*wuJ5Qa`TBZ-Sw)p*P%zJ{s}@XeG8^8WAe3bZ8d)94~$`TyB& z^nGebRB(J>s0&^4s`%np?ed*4;3aKz`6P~G7lK(%~(1Ly8Yc|Dm0Fgp%(;=0%gHJAc-Zc`QQjr-IDM&hZ@S zzZ^1IpvAZ;QygD^Bj2M7<(CowLufxku6I{A)nzwv5?T#G_64xdvNxxOksl(m-t=Ow zl}#lt+vIRAEs5DVG-Ms+gc~7~0VJO{LFTU*lqB6T9rar%l2O;IQavhUWSF|uo#-G0 zGOopy(j{8;|FHKa@OD%-rIb&pMM^29lp;l>)DOSsS!=KT?)N?C z<|YVM`#1URyY^ap?Ro9B*PhqgQU9Vj0#|>SA%+d^%`s zts^|`bg414!eU5704Jj=Wkqx@hCeIAA-t~9f=CQ zYz&U4+HiqFcNG%dRY-JKAt_XN=%47WLZZ70iS9-ux`k2Fy$gi#K0yPwFbWU%9fef! zW3aqUfE2l8C|?c|9rBdlVr?wE55?$)I&g*0!Pg_cv?4m0jrL148fxzD?ku>@*Yc33)ed=B3%ghH9{Ra)g?lCRciFv?wyRMVy;stv z8&}&9?5YRh&jWCcOr_|$^Y=<-fgBEbu7W>%ucW7B7f2}0c7cSE>;ehD-{cQ@Hot2tK7`0PokcdqBb=&+|aS zAx|?@hFu_GHg?Fv;@Tk(a}0+(9f%MPd4_=4ArE7RLmoy6hdi5sghQS#^k+Eac?Kcj zkcV;7Lmt-54tW?74te%Pp5c&(NI2vn5)OG7CmixziNwMo&n0Cv;3PZb`4eE_kY^0Y zkX;~Q3gM84NI2wSa^aBYdc+BbJYN734tdBH4tf3@A>ojRB@Kr>e~FNA$ip}|^DYF0 zYa<(hbhs*M9|M!m(hhPSVuF4c925^+fnS&^O3OBxZ?WcAcuq^+o7G3 zDjnmBA184Yh(+qkb_$yB#&0m>7XJA^2=2FQBNV3r{%n1@yY*iYYSUP5deSJ za$ls0-#I=384min^BW{RHOT2o45^Zy1vUH?%38X7kgOFoswS5@IYpNI*-it`b{gil zQE4`Cifq^<{wbw~&ljHtu}i1O&(o_@B&qn~75;FRY1S!nYPI3IMov9)52E4v3bWKH zvf&F255iw^4LsXv_+pXK8Xkqe+&4h+Y^cCrX=!DY2AQE;y+G*ky_= z?^|7tu_u#cdA~+R)k(6vLJ*xK%PR%ZNwU035S=8;ZxTc&$@2b!=pf2w)|6kb&(N@1t#cqi6}Cl)t}qk1;0&{^oNO(NSG)& z?}mwT7LX3tMB2B(R@qGSVy ziIUu5?NsrC6NR1i_s_u@773-D{e?8 zN)n1}hi*!$bc`#0hs4uCEK*~3Q_y@j^1@{CN&e}?pN9P~4^`jMa}-M0a1Z^XleiLW z*aQB;*&XM>-|`jG3+Hsaoh!$GX24ZVoPJzk?fLlg>B$U$mKy<=z`&l zlD_#-*qfrcP6GNtl75QpU+89T9|d|L+%5;B0#_l?krR*lfGboJnM`SpTnpzKH=+Ej z?#*B+W1|SG`bPMxtj+y_R>lSyHhvoKM93B3{!s{VjfF;RbAa|jpppAjaCaeu>9oOV z+CH6`%MrqKe2#9`gD8062hyTq5TR(vR%y*2OlE6#HKB9h(3(G(&-yI{G8+!9`8UmM zmcxOpgX{RzCC>egbpEM8Pljupf?~6XpY#Pe85ytP_G{xJAM<%1|hgxk44MwPft z@x4EQB#G5F1Kq%F3iL_!ZWOYuFaP{y$6vbmTdTclsa2wzI{wj2UrBDJ7URb-xNXBB zA)6MsZ9{)QZ`<4tkH49E4!vrTk?N|{kq^U(-CJ}6ylq2MODruiww7IZh+r! zTHv+~qsf*9?$gjBlPwF}r(qP?vcP>BEiwyT^7*#DY+@~R;78&l- z5K)T^_i2czMTYw{MARa~eHtQak>LoCh+1U0PeVj4GTf&jGUT@{8a7o|u?YS`4gG47 z;X)1hyhWxP7Y(1Po{O1Pw=RTLw=RTHw=U>aiwxIkRsm6q4A*Ih*wzJWtrl6swbFNL zk>NJYg%}5Fk>NHC_xjW#!)+Sgt5Ay!w`u+nh;CirHVwC^)gr@fn(07n>w?+X)&+}e zTNf;(T4cCNGlB?ek>M)MVj#A4!Psh%;U*2Es6~dGG?xKUiwrkuIN_*8hMP2$Nwvsu zlZJ89tqa!7EHZ`!i;O$x!6G9PEHWa&B4eCjk$n+~1&d7Xrw-apn(^b8@sU(gzNaiHibu-girmT&?ZTe-`v`*XZ#blu z78!5S@VQr!0k(C)0}Zpt=nobdk?mPzvO97kn0%JDb@3Dv^jjCAd(0v`igmFUFAND5 z8Kb}=Bh9uh;yb8p;9!waJcC6>Bv@obf<>0OgUXzPMMkz@kr4?N8IfR-5m{jt8Ic2B zm0kKNNQTt7;-=KQgUUX3(H&H3Oud83Qn+IF4r;|)UKoBuA%Vz=>lD*zG~m;CB3@b4YV&8Z^)Sq_T{N3IS^m#r zy1p2$YceL$wQDMWD@A zTKa&+_1x@(R@DT}EH`N^q!Pt&v)=g;l;>-G(r~kRPFwieLRNRq`&{8JsT0+Jnjig# zqs_$pxD>HyezYLfSHS&)fr85(EmhT;X#91KmWo_Q_>;M&QUQ6|`BIVo!WI1US^Q~k z;RT4|P$P;I%9L!~7v*j}9jwV-V%X!v>BGSGZsWa!|7^zb4_xVh!<^ekPMr?LGIA+g z!-kVKxiyWD5cl^$zfICfC%(^(wto_&rLE{sxbl%mYi%Pl`8?3il5`wM>)Ka=^Z?M? z;aq{0;JGLI8;)k&kI|0Fy_4~MpJrFRCbj-uV3}?oUhH&B|LlILCiz4QeyR@%@@J;AucLb+YY&H-yEE5U`BJ*>i56>Z zCtCDR;)&LM@c0ug%9uaVBGpwUqHaH2&doM;gVCt5_jad_m$Z)inG~Jc;(tmX@&q{zQv@H4MX(=n~uApJ?G=-kXKOxcw*5??b$BqD92a zLe@B(XtB!SMCS0!x>Og>993m;>G-YgWYV`d@C9?U|9 z1hbG)T3m@VGYii_2iQg(8#tJS6whE55(#D@kzf`we%PpE&cQ4sTQCcW1hbGxFbj#S zFtd;d%tChQ+(A~{RPKM3=e1GTx-kc85O*2ev|h}Y<=tCfzy#O|YYx^HSF|ExCWhTuA10S9-iyOK4rVKjXN`%LATk~U{iO{C)wk-&8w%;L?6ydM*I z7NIOyE&*)t>8$)DE_CRo&1rsCF15Pq1|)IpwEV36YBz1<29JMU6*g@;ILFFan(f?F zd6wpPZmKu4fuo(9Z-d*PrJ=R$ER9qr*3pmQk%#Vn=jK+alq2?4m!wvg$6vB+pu zo~8Mnn<~%J{LW34XKC2E>7#u6mrzx1xY*7O{eE&jimA%?N_KST=2Aq)gTtC1K~LL}Al!mSE@RLa5rBua-#D z?99#$Yh8cmhO71ZJ2&?rB<$R9B_4KexcUw|HzPo7ie@%8MYCo$MYFtN=VmSL;3|5$bF&M2HSF9_CUZMC_SF*B%%*4-AWYGRAkQ#G6A4o^kuXIwPMD&( z3=UH?_iFmX&dp80!W7M2m@q{%g)l`E2~#wa3sW@DH^LOnbGk4^lPyfqTt$Z|nk5ZW zG!Ns#6wNr8qA54BSxQ{?WQx=dvRzYTSzPIMgxJmv{UzQil{nm|i{c2Xak!mV`WE@d zkOT!G;v>nY{cn~O#Uo{LC0;oa?ZTe-9}W?mMu#7)a+b!O8-A;#BzBWOOWO)2o1*Ct zQ#6qezKTOdK2~#wqV2UQqzEyG=I>4rA zws)AKDV|}9CK9G-B4LVV{4hl`=P*T+Elklw!W2y;OwmNb6io!*Dq)v$k5L-c@7$C~ zD6t*7DXG#i_>v8Ye+XiU8naurYgh_bk^?s$7MGq!a5dVwX||mkZobsrxnV%bmHrK} ztA6K({t`bD($3{mq_4p5 zrn|3#a3fp~PX-q=o#%i(0XO^s9&HU2TF5p97ruE%e8&GmfeV9$)>+7Vmm`TxE_5^6 zLWItSYwLwQa0o)*1dE{}XI~XP=W3gW5LV~inUGD0vkW1-BII%(avEatY^;)u_MYlC z;s1)ajm$Vz{?40|xZZBpwm;&q&AyaL4R+4Rp+02hF+M{iMr)`bUq(S~{svna++ukC z2wdrrEruVWCfv1PjGLfcjvUHA{hnOA#n8>C--TcE>34U%8?w`~aSD zo_;sJA7MX*t8(k3=%#YNfluV*>9>8EO`d*Zzu_z3N%tEVZCYu%y!vj%+dc?L`s&** z)}9ZhdfO1ZH`FS&PHC?jncpZl@o6^tT@$VimEu?5_H8zK^=;o~lULuRCHm^S3HOFd zZ)oNlOc*=7IMm1z-3=#ILvCX1l=kK26nXV+UuTn7-?kMYufFZ;Z1U>66uPA8`cC&E*e9*azH^(xblm#y8qH87*ky&7sn5 zlFwowDDzjP%*%kF(DAEpe5Q?yAAR+W&$RKwXm4ra<)PADl7PPYw(qpbt8aX#?Ng|a zzWT;@+PJ-_ufDMtqhiy}Wk7%b9PDBvC)Ak2Ih6?ek@4_H5vhTDN z{Ht#!w_D-u&<6NU8{fb#DC`Ra-)Z9$@WloH>YHp!3jWpiNeEe1@UOmE(iH{&>ibND z>|Zzs`QSTkj01~@@*`ixB3@)$6xqW?LAmaAB|aMSufAu{U*bWOehU$)M{%k|HO^z? zdzyToM-mis-C$1ep)QWTMt#g+B~F3N{pFC!FRXQSXBXE^5EdFLY+SUkr#b3$%jEcJn1SU z4R7&?3M#~}z6<`Z%S(Nr_KBM=FcZj*a@@yE6PysL{9e zv-c}|(7(11p{~_G1ZVZ_A-Hs$Jp?Bb9)c4I55b9qhu}oQLvSMDAvlrn5S&PO2u@_k z9)c4I55YMI!$WW);UPGY@DQ9xcnD4;JOn2a9)c4I55b9qhu}oQLvSMDAvlrn5S&PO z2u>tC1ShhW6A9ZDEhrLJmcP^es0UR?Ju6sz3!1!m5NOa#>`+D$?Qlxq6Q3v=F8Dn& z548@@{3IGNML7MSE4;acWmxNO{uq21X1YloYJHYp!bch%k>;>!@XJxyOXXkU69zB$JnbsE;U$vQl{7~pH=UvyrJQt+W$2i`-s zQdZ}8VWh#$T>>VyZ39*$AHv@?$pUOAei!_!z~A-_j3%=@Y<9mw|7$z1jW?rQ5k&nE@4w7nbbug+uJ}KSb%*z)6=c z>SLE*3iJ$;*mrwYZ$X|91N|W!rC@O*b9)ll<7A=~?A6Gkya@DpICP)d@q^tc1)Q|^ zF`Zl*p4;l%Z;gEa@>GO=5U%TClr3N5KeqPk`~+g&Z847)ss1ElUCx*XLzwe1*|O5| zUA?uT#Z7<7HsTFNF6&NtAG%hSb?-rSxvcBx#C11td~-H_4^S6!{=3?*_L$h8Kg(%x zF?W>^TjaWW!-h2d-MmV;4W1o*|JcK;gwKHAHl%04ucyVhN_Z9g=~co9fKAfVVr)qt z1t1gvEkZ^7Sex`>m&@!uoca7COs|2B|@Gyg{|oC0SQ~t>H9}qBII_YZADM~{t=f5 zxfvO@qKAOkR&@IQ5tj&A$Z&~pGmvnJFn#}sON5lhuocZX>1i=*W?Rt=30u*x&HKk* zyF~au;r(MDAItrAy?^9Z^zYw4Qoh4hG?B0sO(bkZ6Io%W#YAvg%q~5@45M~;;1&GL zIE>RG39tJ7u$#(*%OYK$_3%Z?KRq1yEP6MB9XEM@`->M>axK%|Y+^QlHZdDQS^Q7LY zO0V2+|5g0$FEL&7}C zJ+*LTOC%iG5(!7Pj1!J*c~>SJ*~+b|@STA1Z&fjcaAZp)9N99taAf;>+^QZb6d;T_%Ha& z4M`)V>KEY9AEX%M`@_oBa`DL~x@7BQ&ZEh00~Eu*z>4!OxG9r{kl60>@u;5w{}J3& z?h_?@G*U=k0RBAOG-i}6kbK^YNmcWiJ_obtW5{+$Z=@%7)X4Aka83I7(HOn5CcWR! zyUP%x15NY!dHH#Fr|(Vq$+^yBx2{s%6)M*(@nbhxq23RopLx%rxA{C=FY6|?=CPZs zP+vxXtx%65m;Cb6?;pD*7of|3|JV&b^z{Fy$8IwJ^0U$Z6CS(uhKp6d4UgUAR`c&4 zyYc6psB^>oOC-#{M8f<_B+S1=Y9G7l{L9yG@`DTQ@`DQ(Vxr4Gc5DA@@c1{2a(gQL z;KFP2*i9a|_46K7<=A#!_Op30**d_hONFBfvstXB9?b7>gK~T6sKTDydrsC&#>=ih zDzpw`njJytG`J~W!wg$ErXY`9-vYv$;P9yd+-c%WeA+QM!;qQyUoX?$VTO)iy*zn0 z+^E-&1y%K9L34DkSbp!pzbmTh3b?AD_o?dFgsS>Ap{jmOs9KP(3E|P$##xv<^=m@Y z;(I>w6A$*SGY907vq4@$t#*aAgCQmcBqOXLL8gNC3 zijI`_?MM3;;~!fr-p*wFk2nK;W7`A`j>fbMq=SIPXa~Izq?)LDFX|ad3u5Dz-1mL7cTQm zMx1b&X9!5R%tN+tnP&k)!et(oG+gFcijZ)bhjH)|4wM^NXAn==7714^iJ*(op00uC zcu*?*6wrM78!p2iiNlp_6h}~v!)0*8z2v(JNmNmah>s*WGIR~R?;}Z3JW>|dz?)&B zVc7FBJ`0K;U^o=)yz|jR*fV}B#I~6M@3TPsejKke;fImdg4F(%KS3fr$>-pg2N1nU zC;hH4hJZf*gNcRr1L;qirK?@T2f@(5M7zHR`s8F133glPW%%v35dGn{5Rq_O=vV}_ zWN!;Klh#xYb+X$+Zv)A03yFTKds~Ph;kFQ?;5Q;jv)e-4aJAb)>_KO@g}Ckww}ptb z*li&qJ$74&@$26fBHJ9hEktC2-4-IU#BK`_Sz)(@h#cseDKo!hSvgNs+#cMNZXlt7 z?J&flAU*FIn&EBubF^Rswek=p*~`gZ44KJ4s}ZOBxC>C|VlRca`$o*17Z%&8wB>gi z%BwoqYs1uzOB3GPDfgoTU3p*pP0DBCZ=t*!{uawu<8Nuf{_kAp8p``1nR5ANP%7mj z{MGUg;BVA)-jX!nW^eftP+a*-_?wh}&WXMJPv9(;kHOzk`FzkD${X;vTwaU6mGTYv zTP?o;&c^b$;cqHW#oy-gkHO#K`rgL+6t^XAsE>l%P~414_x-7Ok&$crAhA;y0+%ao4&&UcdOOTv`ka6cW@ zky7d3g6ztl)t{;4k2fe6eXfDk>OTdkls;0F=Z9|!4C0fa+i)O=qB;%_p&Yrc^D0P4 zpPK;>KBb*3z}LbXAX>ym)x$s(XxAv( z(>oMx(f1H7nW3H2-Gl>j+Ke-jX;ihm?=U0TQ)<2E4EAZiGA8>PXMZxqIQx@@!nw;b zB-xqlayLM8vbc{K{9Fn)gd!(f{{(RdPI5mVV8r*KX77dDs~zf_|B@A8O$teIZ(>cY z{5$etr12zuE8vo?FERy|^U3K<<3hy$W4J+buuC6AIKMf*DWd%(rGZuXz!Sgx+h;n9 zdP^d;0L%4c+sc9sY;d>qF{^tJcN^Sfw9KuIWc(?xzbEB5_Z7Jm^9qpXNcbbH>M06K zC*jKja7*6Bx9!-n98)7KQ6a8(=^RB$@2f>hYl0s$&EU5g^b z^x~#R$&WV$2u_w@x}M3Bk0r^-7vSNQWY-UuY-Kr7RTIr1jQhTu5iXVqEjbQMtsC6M zA}FoLxr=vMj2O%R$R!^cWSDEd{@oyWdHhHn?PYl00q!%Uc*QlULyOW1cgqmsZe+3t^B4{zIptB5d}`Ops1R^PL2@ zf}i(F*0@>LQQsH7Guki#u{ivf{1g6suHj>h`vuTGig+J^>t)IKuSkYtij}_u{%Hh! z3a;|kKt2!8=ZM@3F7-(Nd)Vtt9u4OWus=0m# z0T04Su73y5-x6W2kHhmATsGJHppBxAcfBY1T&ukhlFv6(&IJB5MEiHRkYf`AH*1cr z7caIEC^&wr_1jl`8TX zT5^XISR&yBmPj~(CDKum&(KCUm72I2!mkfY1;8%L&wY6%=D+8=7Wxs|O}w3C-?d0@ zDurcdk?pRZp#2oTxLrxV)LuzfofY{2tu~2Yb-qiQ#IHJuv{m#2w5)Oc?^>icm9Xl3 z2~qT>5}uLpP%eDe;(I{CcP-MJN_a*hH-0a|9W7=C_$R=(5@KR-arLWUFA^rjM4 zokI;+byoBPw2WQsX0 zG5Jz^+oedN-j~{ykGF9pDT+s$y?&`(^a^`kh9y2gOL^yW6hBP6Y}FZVD%l5UKMW>& zG)sSYG)p8rn&mCb+@skh()fjPpQU|(_8}(dpOA>wu}8D4MmT|GNH~FI6#u1m`v5J! zv~G`P*}&n^>@$*ze?meeJenmE9?dd-cr?qL!wD?e!VWNzumema>;My4k-e$ZWH*(h z#`d|ha8s#g+%L8F{5eXa=bXjtm)fV=cP%)yrpa;apxgp(DB}Ic(Da8dKqugrx_-q3 z$Rj@v;D(;WY*)It2&&F@$<|>SNXhgeGVO~Abq}}>2G4-wC!uEG=VErNvMGej3HKb3 z+kcLv_ULDSd$hvINT-2MRH`vYsDwSUqg^YVSc!WEzuQ|nZg#t zzSI(3F_Wav0R42mL@}vrE>9y3pHrZ{Qis-s&^#aQ#yo9l9ooTlXh+teol=K(NlM#= zWk!DSn!yc`2J_^&;~={)Pc$657)g=p4y!|9j3e#X`W&$-}f`}yTCcE53jhMxiE zyP>%sL&TD9r?=}qdP#THOS*+#(k=9o?wyx(Cmk3!y*i#lVwL0|6r|8sE+VyL&c}fy z{~I|a$pa`xA-N4a#pEeaO3A#Bu^NlOQ%(+szmj|({%Z0U_}iGgh`&uq=@S_3Nf-XM zBsYSmHQ9`~ZOIn=ZBNbsr6Wne*_lke5++@8F(}>104P1l#rQiZnF~7hvGBJqISiEk zWGZ+Dl8yK~m@Ec;a&i>tQWCb{flU3lEk*os$F3BCB zk0kfu@64nG%BYuK2|`&J=UNzk9L|{?1Phz~4QR z_4vCW`6b$9VX^`KMafC{yJvDP{w_`~$KSn@AL8%c$s=gJeUhi}cS-UR{=OmkJYp?P zs>th&Nk9HBOXlG3zRB&#Yk9H+{{51lf@ekY7oe<6uEyV0uK78DLgCUvbv`<%+Dz>7 zLJt+ItKN%9g)0=p3m#C%OEe&5roi?}A9&NY<-gA1Hc*8Kf z=gCilH4MRfe(x+$OZv-?rE2kUloj&FpMxxQ6xX8&%^hgnYVl`D(|@5LJsUrGssl23 z5fE3s3Sq#e6Dzq%)#6J@<7C)jEho8`lkV?>+Olz@`>&+w8nX93OZHzTMW!TteP@7@ z{9`fs0w^{JrVVZe@pJm{NdUN}6OVWE$@q^z{sFFxQTb2B z&N;}wykUcT(tGjKaQ|FvW}%837PzO1O&>!d?O4+O2jUbrECi{Iq;o*}AYAb{a&?jP zuRy;kBy#nVbn}37=fV|_TLjV|Nz1VUUj|n^VS)P>O@0*U0YX{`k|h68pl6eGq-X!eD0(MAx@dFF-`+e;!T?zbB(pUjcyBGMKq_J5&?Vo}F z18J;)r?m}X{K82EJZ(SV`@rF=FDO;v>kzfil&TzpM}m4dL!jtOB)BDTob;agAcph0 zHx%5G9xOjsUl~t~h0Q>hzJURS%YwJ)lFnpiTX%D@ZF1ZCawj&SI@kasuDN+Rh$vGj zS>D{-d{Fn&<~KIKp*iVBQRlc~+Z1fYG>8WqU*%pePWp1o4S+c z2Jkg#Ld~rj4d_ALORyKw0zy^8mC%|b2jNE~A&J9CYY$}AE*{8!htE?YL-3Gvb6UnO zpAw3!DRuk20-?u8@MW3QofO;R6nfjy2CPOOJ!tDm$?O&uWuQT-H5fIFPXmX`X){bg zeWsLtPB-UFBr=;ogll@vGH6%W}<)H3mlKIel=gHtzGG^|;8;C6E zj4W9b*d?35GFUYuflspPOuCX4O`lvP`OTc_7Iu#&+g3G@d}#9@G`tIKF>5~RrTsL! zMfl5}fA+=aCJ?EG$bQZx_|kHr>GD;m;M|6&V+-Z4t%8uvn+mpE(k%9_4am~->{f>d z7DgsDBtPG`AIg7_McpG?tAn~TAYr_J&P`lp}`mo}rZyAsBIV>6nQ2$RvLZ01LK(a;WlFI!mQ>$Kt5_Fup(4%i5*6_#_92d#LoKtxZ;qR4 zNMhiiE^Q&~wZv7xc1s-Lpl*$F5I;EgR$n0LNK9UFt;h&X?MYG{65hcfu&m|66>X9u zC=+YJtb!}4f@@F(S56gN#q?Fx^i^Y4%{1jTT&)hw>NR{wF|R<{OzpO3bzVna#X%=# zby}C{v~JaDJ*LwpsZPU3l2ScHh1}=60d03sHyaIlFsneQn4lAb(1;2#Z8exDXJpCL zrH(=5HYJtLsUa6hP~xe4PRpj5NfFn+~iAUY}A zFglO*W{D|VR;D{@;Hi;lOtS#2u~Vsr zELu(3EI}40>R^~o#cZ#ZQVY#G*m|#Gy;s%VYmA$hz0+j9(~N$lIfhnY`DuLxD~_X| z9UW>+f?8oPzVey}g$s{um53gdh)HqzR3flgjs>8veqYyUqDV`m3Q4*= zYU#nWXC_A-_G+hqbljC|J0Pq38-4qVzGHLNP6k=sk2B-E?r*hrY^&cU?b@at*2SH9 zwx}gCL(vO#ciK8VuR-hV#02Su(Aos38tyhh27+lLG$WYEyf z$Z<9%Wj4dKtm32E%Pk?o=pg%$S!T^7n_Z9jFqq!y>Opb|a>LlW)QL^{NUG{)rh+sp z5~OqjOjGsKpG9CobA20v3D!5-a9(QN?iv}wyM?Aeqve(&yJuS@R3FQQde-C~Ugb-c z*t3jz)ZSc3dvlTRH_x_bTu^LH#Ie-;oLI3$B7|D7`V+6PbzoI>Qjb^Iri7Yp7O>&s zleXa^LMA#ruk}s0qlPRCtxD>4sW2mS=Eql8c6@c`$B+yij-g39hI(xb;ngF_{ZRw> zOb2|kN+~&pa+ajZ{N!v8Q|8kFgOt)`b2?;@Vmf5ZED+v|gwvArE8MXB8!`#SiaQeN z8Li?3PU=8#4WwxJbA%9tt69M3Q9;rVThD2-#pmpNwIRm+0C zdA8MSvgnCsyttQCVO6rGV$}IwGty>8iL?|`Xw6C+-caV} z$ad4_9q?4AV12jq3!$J_L^M+CGSfvWg*9e~Ul5u6_6&FS#clmW|ZyJ=ykANwvKxThi?4YEad%ZI_GQ3tF$npvd&^ z zce8-geUPk)K@%hlc1j(WoS{G@;4W=Sz`jVWiIFbD&BQRP8DosHQM(r#`V$;#nBrhD zG;rL>CIYrEhOl6R_N1bTagmnNw|{zQRX1g`5BjsA8L8%WSZEFE!qoKkB@bf-_ewmo zXck|FDRtyxYASd<>tgyE1?f+`K$>ty|E=lrj5f1{lGK!PmFwN3fw z+x4krq#ClGSaE+M$Ui%Hz%;AvNyGv-IV&n&2bdsPU&k?WYpozH92V0u@`AjlXQV;Z z7PJNY1?UO))#D{UXOZ+hU7hS<>WO*=0)%tHdqygwr+==5|$Jm1q~ue&HUYbLWr zI3==XrlKricO$bhwE!$dO}Px)O@d5v>C!V63{x+=WYmQ>bn?Z*kuxqSW(7>z!kR2+ z%xBtZc1Fc$4s-G)l^kHt2Qv`7E^2G<1&rfxYQ z2qNf5m|wn(JIs5tAyMZ+M`shuh)8y9tIXPlDY6c>B2T*feq;Sv+y+Rx$cYD`h1xPl zTE$Cbe7qU09dfsmf_%jrQ28vd{bbsL^1Rd5;BW6TIF=^bS#_?c1w)tu+nw$6NFLZQ zb!Yj!rjpxPIGQqb5o94JPd;ty;{H@p2J-3^N%|Qgs6VccgWjJK^?#TUcphatD7ACg zbej`$cQbOOs+loF56{RK&|f*i#Wt(8>SVdtmL;(wGvn6DU1d`pi8HD+8ui>x%jBzD zlxDP-orB7NrgZGgqBLuHwCA^3>MTxcJIkgj{K$^AhHn3+N1~yN^JALrY-^NQZI~$< z)B48gPiVOyaL{hSAI|TYNqmAI?qXnPrf$isMq!(#S?=C>`I#QdVN@6|@ocHW!7D?d zqh#yc(A+*hZI^VJ0Q8Cb?Df7j7y{kjJESAlJe?>wRVkU^J99K zE!Jq`?jwfQ*`Z0e)*?ucZ?a-syPP&P0>znjLSAjwX>z-95>J-teIn6Uxl|@rpFtlE zMEWquYPu@YJTabONY}`RO|^l^E(XUXP4~z1!!AAei3gZTtkRIP9azRpuU5tFh}2|P z#dMg2liWSY>zMIQsnaQbm$)FgIk)aMay;GhR%4na%8=1W!Q!KG z=Am^^1~h=iKi4CBy4zfD1nwGCx`bvj!cWg<%Y^0CxJQq;{1Jym^?wz*b0>_?*K-tP zg}-)s&&zV=<`=J5)R>+svUWo++hm!x&l;OZ3YR*fUe|dKztO61DeCV+m>J6b$5dc6 zs@=MbHQNA)Lc?X`+NE6{e+L;8s`zuoi*gr=-o zZ?2vBTkPTnk5}a4Mq5_0Y00wA()7#(YCn6!z0)L3uDV08O|6?KN4cV8?DSroC0&sfP8S4w8d#Il)X%L!q+B`hME zsa}2YwJfq{;~|rJGlps5cruvhN2t;;?04F@{w*;pOqXW%MQJYVz)n^w1UcOTMQmYV zcgpq(f)cQef>>5+HVS03E3-`yx=MOHm+^Krb*z%|J6c{7rrQP-rF5ZQe?4aNxn0GJ z1tfc}>CKEf^S-F!K(}oPQd4`w>WQ^;+i!YYWEG|@%dU? zzuOhT9p1SQot_mnXystwrbe)dzD;Rj>FpT~ukpo!SQ>Rx&8%K% zF%D~dq&0pG)sb!DOx1B*CB|gjoted+H#)n+(UWvjNMlD@D!oZN&PzkHr_&2qy2a9H z^GQ=&We&jRS;&|V6{6Q@wXY2GtJw5Y0J#B=g$6BZX#||ZMeG+8;I>c@i!8nhilUs4&2J6qv3R5QU>4m|O9!QYB8tCr)agEl7{pz|C$8`Xxeo z!6UN^ggwA!c@MsGqg5u%Os2d%m|vHqW|Oa1CdPQzVnYLa;hWo>tS_@0%utGFdEP1v z5paqgqip!yK?qAgpWu82e)x0IY3%%=$L9ir9?H)V`BW!pcJ zm~VRS0Oh;GE}g}E13I64Y!xav7)>YXVKunJ9AcNp?aEo4QvLHD#&~@dTE3fbtJ=0B z*gNuck*^pRqZ}>Pg{@R}?8ivi)oyI$d#zJ8C-C$(f2}C1?0RaYZjwn|uUC_PTIusy z$mru{N`H2PCVQoTedL8LM996r(!KAR%LJ$nyO}= z&qx$6)v;${O;z`Dr0>C)Zyb##yI@&69(Db7dR9#{{PZ|SXT{5&?;75(<1ZK7PHZ-7;0$j zjD*E3^n37!3qBFQZb^qT_PlcUYI0UON_XZ|(yp72zw^xE<_;hu)ymNHA-Z%!Mi10I zjr339sN_*CCXrgKz9%ISGkX@$Xs%K3x-!mus|p|2^g~GcW863C9p&|9e)SDsf5QY+ z;GHLCNNpnX{BX%X`Nn)z@H4**swE&4p*Ds~R177Z*BkuYf$Q33u`3Wga96TpvU-p! z^q+-kz0L<`ya6S#hpTKBEDOb^lJY326-MrW|1O-!<8b0F10;$sU_e3xrSEI2@TJN8 z$Ktex#jr%&N7Nq=iw2k{_b7cD!_%=#iDW0y4B(I+A^sipYUeLEbof`(sL>vozU1Y=7K^j>c6V3WmF&juv>SV}-H7i7#<%?C z0T#9g@?F)hT{U1`XWloG{RLUaGHvU>9A*|GS3opu2Nnv z2Bsp&Ybz4zZ7z54120xMwiMnV_>6LqF?D%P1dwy_flf86OVatJpzWKmecNq-7i*i> zK9R+*if2_y{H3PY#+~G5LuEF>qKfK9E!vzdu~zmB1Z3=4-_z7TsoAeXp>4d1$ZR4F zguR&fM6Je@izxIVoVh)f8`_w(keizMrgmc1l(RV3NfmK$9$^X{T%74_V*yU4N#d zwUB)2mLbO~6Q2yy$z#MT4-p)%5@y;witTq)UTlV}SvEUWFPs#X%ACq6bH^kp)vexk z_g%y2dE4EjrZGQGrC98ZV4bBCdu*MVoYptV{Hg&KyA4-VIZy{Qz~_nxy-Fp!l3?uBNgV6sZV6q5p56pM_j zD0A;Kl7P7X?HD%h_VgHbeP4RpKtIu@v&sxgja*2?;#o-}=>Qk8kvgZ_o+u3^hmTrp zztaywz9I-JpDHO8ibAkEi&{yn`D!O2&P+AaRT;#Z>8euO{MEGi@grs?2GO`sb;%9Th-eGf?Tw*)3>#o+cSftK+6i{z?u^xkolIb5sXCdS4jw9*Ar{$|yu-eE zrN`O4GgQ^=B5|T6?+C>(-PH1Ppb8>yG}IMDW|#dq0H%~V+2!e69jmy=kPg~i>HTm5 z=5&$mb4+F2rkCyNqcE?GyTuyoqnt3B4Az)wVs@)7KY^i^l@>p}1pSgOr&5_2p2Qiu zv$os2(r)k0&LZ|J9DWwDFNEg1wokjZ-)0dzo0g%)Ee6};@y0QGkJkvIuGOt_%r){` z1+v*`FGj>z(9sYnf!Y~j;vU(~ruX>@M!VKAM9?TA}vU5umbb1h}E8$0pT>=K<~b&%O+ zJ+-)QfO|WhgnIkmcBQ2vXNa1Ots$`Sp8&fPsE(L)Rf^4S%U@avTOD?4+KkoTaKax}!A1u+L%6o# z0dJkLraxtnGZzNa$w_-B7am2QVGO!mfY69h%zzWHqI$E4>@{AnUqDg+JzbB`vTc{)Mq&%DE~2 z=8iwM#4ib+ckSMdl7K6W!{YE*A*Fm++e+xsj0k;kI&F(?zth!v*{(j8zr-c$R;e8~QVTBA- zNbbt{IO(^lr7N?Yn|DpO$JV&?PdwzSsodxH6m0a@Y<)_6op{X{mm#a9+~#M^#zu$S zB#^7E>DgCy!01=N(gDL?;1Sz-g7sKdQv0)#Dj)FE`*~sIM5Q<0o|LE67V>6Crj8cO2b5h92C)}!= zZ@4s(-!o}XH4J`hqV@;iaNR>MFLc@DV^?w|Y2Nqc+APzRw)p}M7N$2VRlJQJ^-gy9 zhsW3BZhmFAzD^r-)zje$?o3B`mHKgvrvIQq+?HKk^;WpVttR+BT$B5c;?LdOUo8KH z8%tTQLdXqp1-DNfY8gLJy`iuogcKZkZ;w*jCrT|1jZ;ghwW%?sdvduKoKf@qEcFI( z9}AbbH3Y0@;to&iqrRg(SHUe9Bip&cHcD_FT+y9)_82`Hebk~C+(r;jhhx?qNm_CI z{3@uM;gGShr^Gz_2pDI~yx#0bbzw=mZt;AS`$<`%%)y`OL!9OB;zaF2Q) z1kj{HVVK!6kXI-N!8-BQhzo=Ehby>+V}x%PwzUKY!xi00XOGdN(bqCz{gBYGCtJb)92|;8K$iOXY9z9^fG2UI1WZ-f3v++50JR|AtHA^zH6I*j zO#h)s?PbY)EkOxUO74umI%bT%s-&})faz#Jn!+`R@CaPNZFxsZrSEW1zo8-Tyay1! z0!^-W5^58ifFBUf{$t$>lHqCs=FcdEZA!KVL_=kx;%pf0ZvW!0ACGRlgi&(aYj=x+ zb~kU_?nav+*w_pvF35JadB+W~n5=ZZ-7Sm_SKnXT?#352LmWLKN8U4Ly6RbQY+u4> z)E~61C0Y+M?iM&CM{pIKwL1lv_%#|#aC0u0_$?Yta7Qkf_%;nDxF;7({C*84cqkW4 z{9z3y_(?99_+uJOz)Hs@&sO$Igt9KE<`)52Zg_tPz+9rXJhb0c4})V{64Ka!zayI* zhAP4~z#%HZ?c!ZWfS&}X#!SZOVf67!h2`pitImK+-1-VK057X|0}@~&V6Y-^ zzB0#OSEj!n+{FChIDrs;1P+3H6~I9yc%HClLh{7hZNeE+{k3xd=6N#VyOo@_ z$|EQqi%VlG()l8swi0ygvFx*_;g`|5#pL*4@_ zg*KlW$LF(f99V?=&lZ1fV3F&2I1DQSJo~^{IzAbrhcUJ{mP`_yV=8!9fmGHI94y{- z1joZk8i_6hh;NeMH3YYccOAhUN+oz+sRS=7m4L;`8g2!Q!UUs{kfSmKn-HZ1j#5pC zLmxyRC79*Ogv*tDI=~s8O!#pn6I|)Zgj(LwyW#zYClfvlhqMVE@nk}+$LKHNeZ`Xr zd!-_y1pRO5Rf*>=JB%i-#-m<20CHb1sfs>fBIhNFHY zTqIWdnF6`WAU*y^{+lPUP-_UtVv22_XitJs$odQ%R02U@#VVv8>w6^CwFH5+m}M;_ z+xaKOKTHx?O>hJplz3r`p5qiLjnQ+4BIPl9E>Wa9M$Z=&X&R$vn<6b^^xUsV+Za6$ zDbg`U&m)R-jnVV0B0XdDI5ZAQ&^tyCehrdH{}??ZiVTj?!`dQbO4#n93Oo>wZBNM6 zH2gzxKal4zI0y#;St47Foa8uEIMxs-$Gh@rtP_q=0_8X)&oL?-YYCJi9rfB9g+j5I z?-wMp0TCXOxa$cXfh)R`3uE*=sz_;!9*>k`q$dBCFMJEe2ycOd;Y)BUoNQ;%bBEG35@+n*T`;=gs5?8N8Lr?+ol`f2 z)WtreCliO%WpzVHeLGxso6xAtJ-g{h-cg@YHiXne>xCqw9`8dkJ9){`J|tSyR)qaX zWv^!0Nu`U}6G>xZ9riRNVs{By>7va;3^WkVf{R-rrPj6rc`wQF7o1UR`N_Klt~P|! zE9-x8)4x5&2UxYK< zx`%S4Gk1hMF<2L#@N zBkAEhxw<1rPR1IMy*YSDRkAOl2YSTj9QxtQ@{_SqkUt3qvrYf!{AsS!DYqeKH}*nR2+U+`#cDlC(;XfFwa+fIHB`t5gzQ*A{_N}LY50@%&|NU9fqX_$8r)L zu6}_(RR0j+6P|AI5_b$JXTYI_he8WGcPU7h!DV`b#4D9I?o*Ps=E;e>9i+SA*c(~v zfz$`!3K^TisI~m${eGR4Seqv$oiiQbQ|cG^9vDDqjUhrBS8KC|58(@f#B9X21_rdvua4!iJaqb0BUWCh3n#5P&Q0Ya1x8O)BA>9la+aVy$fnz0F zGL=O*V3a9R4g>5wouHVxrn>hCA)0k;@c z^so)V6c#dxI}t1wz#+kvaV1E*3XUhW)&q$vAbyjikyb6GvftyKu7V?P7hFE%ylFT~ zg=2vUFHwI#;r_@~3QP}cmM!pgV7UVh1zr&sn6wArGO9Cii;%!lNhB_@QCY6l(I#KP zk#`kbK7{7z6Kaw=!Y9?=Pk7x_Ut)T0hs&1u6|i)HN_!&J>IFyIh;XNBFL7Hyxk{*U zfsM*yEzT5}yw}3zLs*V&lFpfq@J{vj6K;}rf}u?h`yyN5AA;pcI2Jf9TEUU_5?sNh zYAA6>BL1X2Fs7M7Vs&*4;1=;3yM>*Q&on_?-It319GZLR#Q)*&o79 ziHG5s2H_*>FA;9?X%L>~(;#HNaT-)SXQ?7`gqzi0BJ5o#J^hHIXAlk%ON0w7z{Uy* ziTPiFUbzJA0tfFs0Hbfns4VRM`+xT# z=2AqVb|<`9qOT*k1+M5eojpbmlg4oZQ~$1dEd|@w$fu++)-%SP5@Y?{0BusH^%j}% zSrkE;4@oW2u-+xO2~PG_==rMBtr%8^ zO-s?sa7>)=GB`vh*a9cf>G_n>ExN+%LA+A~2=0cH2=shQ>1l-Tphq8qix%Uh;is(~yYWC1j@BSAW>TVCl)T3JzL;fGoDTpWj+n<_*HUhTs%q##tnpi8FzyxwL_p$#D`e zN)Y1t{rfatIIPonEYT4XZ#4n=TKpwQm!`j^dW|KJZxJ);q#Sq-&j<*gK>8T{=^>Q+?vHm$THWJA?f zkX(1bp^5~5F5Wc+=Wka*j^o}* z=RlSzwn9RuTGGEQMYi%-Rl|UaqOsl<_W7W&({jnu(VaQ0-;LyFlWN5@@`&nRvP0PUD>? z@zxSB0>wBJ5yz(a5y3{dLU$Dvk z;Y8tGFh{9B2*hTu^+iRjG- z;y=}3f~Ru9#Q#l$30}+v6MspA30U|zajQ(E{o|skpEc70j#>e66rPrA)XD{FTAWcU z4yb7JCB1`?xTV5@@_N znRs=FAmd#n@zxS(ywOa&IwR0IW^xl88-ws>ILwX&ENI+D#{fT8XgC-EWS03hBF{!R zv=ISW#&07sA1BOf2u>C6YJw22ZW}S)@xnYxpz+pZ;?-><#@i(E))HvE(M-I$ZNyB@ zgJWY5UId3WB49z|HaY_MkwQDu5i-ks8-7--hTZ*G0==X27vlgs-T-MCkTYI$;mu zf+rX$iEwWL7gLNk5ncf2i^}Z?=d8-MQzF!t5t1(pss-K>Ty01bs9kkJ3T^|+aGWnk z_Uwq%Q|g2)0BsQ*>rBWL;-195EGWz1q;8pAMpE~$6Y?lp{U>ltlW;fi#A&kqdVQ-9 z_N%`{xK;ffgx7jHA^Qwzgo(T0$UOrt-{$zJ3aGo)2|-;zT~;Tg;7C27ZV0KX>xPhe zSltj(H~5gAXcHJWuRuMnPDsI#y2*#cGE{J+UQ{QyzX-LHG60*`o(|*CRbeGmk!?EwKuN!hZsN3p>JOJu<>V#YmS-Qc?72zZ5531sL z;3xWULh{FQcPQ|~d^jQb zND3TtBRpRH0=K}Alb3A?Jy-Yu!WS&SGA3k7=fa^p1muZssT=2x*2?&Qz1sbHu^-zX zW<4CsO!$QQON0*91APu*N&O{4wt~>D0uf|-ufU;H1Z0nUjQAWl1QX291ruMV!34}G zj&1o2A>|oxEHvSW`b&f>)Zb6Izo!$jVBinOfR>g)rnwvrB_m*zIBVjYG?-v>E|~b$ z8cc9QE|~Z|8cgt5F4)RokoB^E@V`#O;+QwVf`nskgd5f0LwG41hQ$L3J(u|a!XXr0 z0<3&7WQu3Op$!Qx5$`$zMva@3_|qCp(3EQs;>_vS99$@e6)(=*Xun?Yp|BecgJbg% z9SkXL`^H} zr4l@$R05_Mmy`It$OH8xxKF&R37B)tnJadBUT zTr>Fj8-nr={$M+dM>pOW)~|EDHjg;#2Zt7m)6e>&-k$IPDST=q78^@0O6XMtTPn3M zDpfT0C5zlH(d!y~FXa9{IQBLn$2t6AQOtsqX9RTg3jtYTSuU0IIgr%xe(-)r(pxY_ zxB$!z?i9CZaE#s?Ji2&rjNWY?T{t*K?|pD(Fjt2L$LN1F4W^eFTd*}~($G+le<0M$ zyX;PubG^zCyFV8|hcTzv6(AG=F2T44r!r)zUTyw_6y<+A;-fFk9K-O`~Of z6Uz8@4K_=Qy=MR5ud9_}y75i~f4$QE?#8xu$+c_HcNR_<)pDGEj#NkDGO}XnWR$?W zQmULacyt_1p14De|AhmwB?!k-6LM;UKQo5OOTKo5q2vTB#Ji4QwNeQfIU3z@9vXK| z8h1V8j!J|z1R6KUygxIMBwj||_`*8MwP1{p4&@-wavWl5kz*9(n}p+#F9K+~H7$5M z(tH{Y=@2{v7ta^OpVeRj);?B=_e@D%k6WH*gh6vkTw zhfE3f7wiJ^c5rzw?y$<`~18gWc`860JuP*Yw_pyf&Lu~;4AGRDnl;e=7+ z)XO_%jTnvi8l?X^EIp%w)~nG3!B#hgksTFz<2ADJ=h~v~I?s3wMn%bJ^&rIc%5RYs zM)QR*=S~@;V2hV4XwXeNLbo(xn5jfq<4;JPxN6KKD*pu4n;>|c5^t{*uStW1Wk;q# z>QUMx9Q_Ny9b4^%d+>$R! zA~G2)1?32f{m5vK4b^dPk&a`+XHyT_{&%1WcTx)Die{R60-5}82+kIjSS(RhcamE$ zxB9E}lONg86Sor@b7sXl%`@hyy6vS_btmj#UbX4e#T#s>mT^*(kd4lN+q~LsRY+3m4I2I{scYZT}{Bu;~pX2ufYU^;$25DMX3ZV zZPb)jL>6v=WVnVvGh9!g$*dvJxM72h@~UHmv5!PFN-QBA#D+ktc?iL^aO7aB)8Od0 z{2#*+*;8;F$%Id>lEuA2{0ulWHo?|hFmYB0!2~aecQpa47AHjfB@HIP zr|G2w0a)3X(<&eLuU#9T2x?z~>nv1@4*f@Rm1lm*U3DmoqV5=~MB{l`=T9BR;@+g~oiu6WMAEj_&OMI=o$w{`FB~Hrl5(ym7=a@Tp%#CATF~{Bj#uE~(Za;}kE6x@!5`Flcr1|bb*zWOB_Cxx^Xj3J*w&|smRJZJrU>QgQ8-}UlaJ+=okEf6;5 zV%1}@>vR4#Q0tf0%3UAEV=ne*445$Zca|eW%&gYyQENBv^5xCu9Y*(SLeBJFNV+~1 z2I-2^&P=y^iur=p!Q(>4{^&PfUI%it6ElG~Y{2hS*`t1(&>MzSMiS~#V@b$1N~i=E zQ5T4Lb*3Y{Nc}y8?>SUVqang0)ZasR-XAEvP7OVYsrIas`I6xDL+D*c@FnrCCO8~P zfl9zs;~__UIdVZT!69&QF!3`qn1JPpgRNXJH#wyRV5$_?#1JHp=@Vt1}v$k6C z)mCw|0qc7t9Ly!FFQ`_{xR;Ga7*~$fco2@&Ap9;|1$#^Qow>m=B9FpBo*oDIrFchY zp!74P2BRARPJv^L6*Ko79J>X`wwUk?kXM9oygP8_euHDTqCR)Rg(wc??}DpfA4xb4 z2XdScd=x8tRtvBe$0KEyobW8k#iwx_ko!I1?KAQHhUb8kB-<055N-$ZKujnh%O=Uz z*X0Nxn}pz_SUKX6%u?I}Ct?6d3Gvc#7Q7@AZdUTS02itE5&+6Vv?JSK8TdZ>kx!RU zrEWdJ1#nE4@K8x%JrmMVvz{YF#V55-e7fV>7*W3TLh_7aqbGiDJ3+8T9WS@>=oZgl zoosgEl?YS0?hoHTAM6gq^>OZc9~$XR#=jEeYv2%{fXUU5PiE&XLiiS8 zUrlg@vEzr-Sa9MW*I)uBZmk>F3(rP<}lmf z*B(!D>37PAo}Hr6_DC)yPA(oXmYu?wD;f%AY&oCc(#`Fv6e3SKdnBez5IxHr=d0sR z_aN$(Dk#)Qw?e;LMdGA5<6H(uAt&6T{tm(u(XXKQ6K+y}2O;GqJ1CrEIu}S>jB`Np zOwfUha)pmVcsm?=hv2Zocz;p4k=`Rbif-Hh?-_7lBp5|Do{`>laO?^8KmEt2!Su55 zzSGlsqyqQ<*n1ynE352I@OzI}ub%qayco)Pi!kODK5fcoEHs1=Lkvx5npniX_x%GY zVu&F$Z5$gYiXsG%ShOL=7&WHCIL7DLv~4>sLpzMiF~(+WmSJ4PaoM!PauLJWrrKp# zrpB-+W3zOAzq7x+&pzKh_ucn+pjhFu4!`~F^E-R*v(KOJyWjoZy*lXCz~~+qWw!#@ z3}UXe-wZX=W25);AbR~|NWd`Rg&+0GSL!di!90hJcAs&hIXmRojClCqc(i>i6y&?{{n8-uPYX4 zgA1`wUUcejr)?^}Y+HR!hl|1T+LkR-H@W1h{YvWW#!4k!S-l(Z(p+o5Ns4Xf-G?dt zEDEC`J|}X(lOp#JKP>gc*((Fz1~o>*)<**q-*!>T@Jq1^jWF>DBGw2r<)&k++?1Zi z-RDo+p86xYeCwL^7f1e5p#}B4Rn0(U&Dadodg6qV>2?%b5~(q}TyuL)%CHTj$5xReoe*lRe9iuQEMW>K&DQ`o^YI$jsmiS^`)}XW(KWn>N)J`cb z_{7xO+e-3nV;XNgd6``JMM26DbpLJ11cBYt&U-4?PlbBC3H3SXpGRQ_h-?PA(gCve zqaZ}W>p>hMke>^I(X!Q_1!|pO)XE2?DRm&BHhkJi@(VD=Fu1Q151@46^mM`B^Rs8k{Y9B_yh4Q0-Cq#S-z;^DPN+-x_ z`3r~^_Xji({nkeW0&Ots{%bY2gqoQ>zF)4|nfBKWAsd;Y@pMj7+ZOQExLYmQ&;@Dj zy3mYWwQ1jE`ITZ0eg$0Y^!?;CFE997|BP;2-tV|-CVmO%N6fRk)f&w@$3qx~5frA8 z_<+dzMj^BzX9WtfL?9(MImAB6TLZaHxL3(#?s!ZCE`-?bu23;Ruy*AfkL_$*m3EA1 zb7)s1ke5!F*wW4TwV+8DmR$T8bJ^a#s}mpczndi5eZQ?tkjm?qg($E}VA{sAO8VSD zuM@6UdYM)pFOq74Su3kGwmsOl9}j!?wt{#_dknf0)^9sI12@{Xfa@U zsn&TI8%!^2h%-=NRU0@5YgXV(f_2m|4F50-?u|c|g z;~hq4MC~@)v$US*ntkfN$K~Iy9a@K%Cdc*6=gg_&`+29-M@h8Nq6IrAMP<{Lwa^<9xQ%_;*uS97WMJQt8W*H1~;A=@j1%*XVsmMP8%wpeV6mk zKpnSP7e`d$7mAXfXw+FT4zg0moAEO-iN;(gu~!;eiaz^Zc6~kL>gowJb)fON2x2Fk zQh5_ewYG6)PGj>qtF6oBVqNyh;qN--cQY4~we%-^?f68JX-1@HwxDaaqBM!IeSe% zo-xRA=;P8=;cW(?7sanL9{-e76XsW{dAvZX2{%-#d3>W(6IN8JdHjn~O;}s0=JD@H zHR0Y$HIE;VYQn>nY92o-)r6-i)ja-VsU|#Mspj!tNHyVDrJBd@NHyX8N;Qu^kZQum zm1-WhVJtEC3Ee0@=RE$ZR1>bPRP%VQR1+3fs(HLvstH4tY923>Y67Q}_pMVT&Ro^x zkdu4++VPjRvNMEih8BlL( zlW*bg3UBH0gfEcG5X=0GE^YdF2nAgsJdEOpn#X@C)r9?(Y91euYQn3PY97BX)r7Yy z)ja-xrJ8WOQqALkfG#66LJx`$jmJ}^ns8aAn#VJwns9Zcn#b2jHDP|Gn#aE+)r4Cr z)jVD!)r57GY94QtYQm06HIKh7)r5O1)ja-VsU|#Aspj#sQcZZNQqAL+rJ8WKQqAN4 zN2&>&Qa-71=BhLna#C{EaBXp>yjaRaP7RD4;k{B#OJ*Gn~#nUJMT=~!7qWKz&Td)`*CZ%;_zQOPcR zSXDC8CDrB(=%G}pX2x@sn}jm%PfNVzxKX#e-$A(j7R+1}GKn9GY|mRUMsjwbAO->{ z?!n5GQI8D!5;c0>h(_B{IMzflVh=y-^)+d9n((8( z8>{?c6mF%&>qU-tZZRpyxda8zIuJ++>$LKrJf{z-a|3mNVARSJK1CZ1T^fjS|7xQ` zl{UeZ)wGW%5t_jouf>9g#w-B|91JU)53Q;EgTLHE6PciGijWs1v`=`i@ zr@midA8LddD8WYgH%vUfQmP5FE7fX+*p0gBfjY=mq*gu-_w3dG0(VMK;Fs`p5bK1! zq9yDTE#XJTvD`XCMw7KoOxNVJ3-L`!%>w1hWBOQ1vd z5SnI<^}I?|arz3PaV6?)i^qF7;Dxql0(Im$hVml#$%pVK()_9Ei% zbA2(r>WDum`E>o5gC#u|g~LajCvrFO7LjKXxzYIP$8@mmAPUS8NNJd6d0RnzU*v$7;B!aA2Q0B>aq>*^lEhXJ4~QJ_U6K2U^jD3O zZT}JlaS}*L;{2{D&0PmnohUF>5W7U~CSEJ@Od@A2IJVJp(AoBK6u2XhlDL~~N^^I3 z4NeLubVocQa(6(`p`Y0fr0J?Vw*6ZaxFe8~xMN79 z7q^5V#LpN5SBo6*9+CTq50-jqrT??_w^3k_aBmQY2;_$#%4>CPL1e2Pfm$aRwc+N# z-DRzdcMm%Hc<3x1;|D$=ayRjHk!KQ_pK4y&_CKP)9D$UEyppp&RMZLNF|W$c=k+zP z#G2)mSNyM_aQumfL=JdDXAaeiP*b9WfmE^naF9r1|B0Y4PE zkN8ok_wLyCZ&2WlKuY57q$$naMs#>nNX@o_xLM?G;$tGuBr==TQDEEOM}a#6DTzDW zLoXSf#lY`(4E}zH(mMIfar;-?e*CBzu+SDjwGf4wATAQQn|PbZGl_Ik4Xr5H`j=1; z9O3pL4iU)DPv~3ATD0+LrOY7o<()yE^wry^?2g@V=SMCIedQO0)}D{EGQBl1e}D4X zgB5ZK3YPt2M>qVYP%qZDX5=a?;(+=)M@USG^G{tw{@*ASAc8JACWmlF8iEf{

&BhXgP zlMXe}4R>-M3Kv#ry+w=>XuFxQTT!<`s06lbMqQ1%wL&GZWsW)<`fE|JfC}PDk$Z?V zLA`&GzXAo_A&`HqvYxvYANHVdx)Waz zc`EU!$n%JAm3rcHzZUrOthW$o=RcyL;{;ONAd(pw^~kU(=WQK^fg@sz?%olR@NN)? z3Eja%jc{oYhY8a~>#e;E@@t`8jUbUF4@oJTO#0=jrDGbSOuRW59)1+?n23)9o)GaF zz_TK%EzIUHqYsrf@#Gdw?hLGD1e%&se5+%Wf<$H6=)4Vggitst#0y0ZxK!jG;*F)A zI8^F20wV29MZu^LNU4kpSyw_mS6J5p7KpeAuvkQz9}tmzz8LWHC}G|JUl2Lq$0GL- z3p4{KAftiYBNpU;+IblT5fVtrM0f;M?+WWU-~$m)0zMRxZaP9+yE zcZq?_TTl=K;npAy5pGBEdjgNQNHu{b(a85FTD&<_)(K*9B(YfDU5XY*qD8yyE7sPS zi5lq}g5erLVu|~5840_rFUbDvFuRpr>xr&!e)sp3AiFo>Zd(tDtK39uQC+p11YjRm zCE85(D}mdpiq_o}!$lDnsyqF-7;*ZFUmY_Jy?Uq&Kyp)CIj$FeifQ$SxU2RN3QZAD ziQGf%37gcmUg9Mp_Yk?of}fn}Xr}{uxFe9_dLK`^?WpKR;f60edK9as9gO(hmP1wjD(r77a+wqPZ`R70$zT@6N~mr@`C@VZ#?A}A-#^L&;n}PxiXkX(MsfMtxesAa;kQ zmgFgRm*5^$zK6n#m4M=-9ngWo2mOh3kJDPrYy1-eI=&eecA&s9;ZBsXb|4O;z98F2 z^5L}KvO)<&H%G>QU2U76Pq12bW1Fj1nqcDIvg@=+G-8Y|rdf}iCntJ_G6fH=!+o~( zA<2YU;re5cFdxO|o5xE-b&aq(h=YWUq9yQ($!+fRK@V$#x=tXYRSsNVeFSOba&+dY zm3h>Y^V&@3qH)2%vuwK4+XWgpS-o;SCc&N7 zeDl^sPG*p;sWUW#)P>n~1C^xCHn03dn@n|Mmo+Mz6v=`zZGI-%-9R@{TQJiIl0mc? z=CtW#W8-|PnrSUr>bEitPh+!l(Vf99O}b{=l5^5tZ0ytMTTDgQD$leO=c?6-N0-;o zq~WA#v-vcty`!q!az?e7nrE@vhw3u!#B|oW9OgweIMKNY{%mcVLl;rYnVRS3tg0@* zS>g`SOl4r^nw*<(c?&I=xoUM-#U$Of6||VCZd=YX$23$8L66;h{sG-#58jR^%TPFr ziLZ*>Pu!2UmEo;D1-{1wsb5ng$mV~6f{92t021EX5XcWB(e&Cdwym@61OJk3hX~JT z+wuyK$1k9unqa0Y7l_S58=(11g831`0E(X^JYFl+1oK{Qo6-A7;=Qt~RueK96Y}*W zA(bmXwqq*DX)o?Cl@;tu|PUD6PPy<9zmH> z{Q4cE6dsp@?V}X-$-%Z!3Uu0r9|SF5d<({yX$hGgEu{j%`ECVAp;C_2P*HPIoS ztD(ca!6BZjp}?_ln=n7^-igAYA>Ji&Kk-F4z+%~7P~dnrE*3Wb0~92m@DfN^EClk$ zUM#U~ooyHWk0CI^UTs^h1|C0;g18B0dd$TV%@5H0Dq$Z~i-oPo;bKv4X0aeR#)@QL1(1Z*u0y-!Avtc^>U{bR48Iq8 zUL#2Bn_`D++F{JW*iUDOPSysWHUnw<2B=m9b?pN{dxL*nA&NyOXySf3Z7vOsmlFn1 zrWBj+7^SdW4z`a{xJ3@OjZ!#)f>lcRNc4A%QYhdX&GAGUgbU?h+b9Kg2rV=hTwBbC z))+&*IfR5YMnOUyilL%K43$s2A+pX8Dq2wB zpu1HWLr(5a+eccNxuH$cH_N&Aqq$Yd547(@p<&`qk-Le{h&+$DuhbJ~;?_F&_NJK; z(9Xjsn4$zy8oG5974Hk@13*{c)VcveceAf3o&@7*A=BqeB5G&ZU=|9)CXR?4a7C#n z@#D0x8bw=4+B>e$+n!%rC5 zl97Y$Txo1=#dE0JkHYWJ>TwfE^)8t9g8q)8;IBRGolMj^s@nJHQtgZX&?e{5-KJqv8jQ#uN9A4&B(EAW@x7`5E@u%-Hx-|U;%qCVyK*{n$8 ziF(gpu%JK7_xgnYkDKtFp4pjy2cE)1!46JXfs)(nl{yrt0|cWsTtqJ^YuzvF&Df4F z0!HE9LA*}n4&wY$uY*M-|7sL$=>$?jSPi~Nz7n-p1@aJKP7qfT*v_35NbcQ?cM2$2 zD>DFBipU!OYPQFDz300VV6*foy}C# z522pMT4&oH0jh?kvtmNa)jpPR`V#V;wj`37Z(4j-WV3vtvX8(m?Dk?q<}JKCJ8#6svZ+926vz zFfWM1gquZ6ScOuFsUIrZOk%nk3OaK!9omEsa8T%*cnPW@cM}xrs_9%EPNDko` z$_2$Yiy!`E^y6<$8|7hla56x+I2c)Hk9!owYaq~c655+k(x(e;B~&+~Fa+WYB6kxR zb}qErpl3m7gmoxg4DI(m`Hg9#JlYs4hX}OeHfnsQ5fn7+1DnFz54S@3Xs8$<>_Pcr zv7xx=lfRiZ%7bU6PN&4?t@v04g#i-Z6uF!DZmCzU{teYG=vg@70QaD{obvF2P&-7R zArQ?*u@wqhZixIYC|?W}1B91QB=Y};FQ&)AVX0F~d?$V~yw}}U5SOB3=tVb?!;wpQ z2lOlmh|tAiDd$mls2n8FP7=5{{t&LFhN>aL)j=F2TpPp@0{u7ikL}x0F(*_G5ayvs zA3vTp%7gh*M_3TVA;MzOYR`9X!A~Bbu!qFwenWb$^@8Q%_r0%>k&6eP2okm9C=4Ed9(|{X~S~Ne0t7BhWkWo3I%s30JlK2Bk^@*e0qMM&( zb-epo4cfmma1owywfb$gXL`MI6s&|KW;qJ{5lBTx33Gy2Be3z0fn=?*OK;FL-h~qx1+qqvXbV%WMN}2c&iZuGo&C^Div6sqP;>$_xt2koFm@5qTT@;!m9!H60n7RU;XDzV< zCDt-?mzK4}X-O>;Co>LhD=$CuAopms*9RRxIm^7<&%xiZ?(?=AK28FmsLlE-hMU7%jw;Pc-kDtbn>53*{x+vIn#UpZkpvbv6O17 zEH}MUs@+r1&772Kch_?>AyQqWsvOTcQf@PJX5EDTylI>D&g+x)Z#&Alp^b6+3GQWO zjAzV~(X*ba1;wQ2wjbuEw%b^>aYVOQxe1h;_IYNsG?tX?o#{Gk*gHS3)xQ6Jzw~m2 zbAInE6LQA(POPulnqlKpxX;tY!xl4tKO51!gjU17Vmo88y~;hx^eMpeoXfs3O8XQAExt@q#BGnF5e>3 zLLa{36b=ZBgE&N3B3i;a(GoU@matp2goi{+cuBN`1EM9oCtAXB(GsR2T+9u^r9rF_ zri+$v8H%4GUw+&qPa*P7f3QMzjR!^l2!JXhn;3m-EwHwJJHAP4QTiLq>cR?(0=;r z*x>=~u&<6iAJCrr>X?E7O@XhDxfsw~`0ALH0Vc(UzkH_?Ghu5P*X39;ocnCRwGp#f zQ@&p^nmR5SeYIFJmAff!ExL{EY-vM!ns2SSYVDT8qzi5$xhtfzr411_e-g3-&Ggkx&lWT4^IM(i zc1Cr^rtMi>6O%LUE`yK(zjWNh^Xkif9ajb@TscHOf|J|U$@>}#%n&XC4XcIlr6AS_ zZ0yz${_dc(n7r|vX-d0d)zR|nHy4HSh^|A<=R~yLn#yjuoaP>{mMVR*J6Kvz%tz}P zRXK^z{^ss%X{+Aj@j0@XVnCCXl6Mw1F~e$XxG{0Qn$K?kz@)`b9eeo5(G-(SS0o$RxPABkr-NXQ`0|R6IW|ZMwP{s@bVbOMCmO^~C&iR7S;uU0iy-ay{m)w$z5p zpvuh@Z&u~}_7z$;zmt)lXKIq@Qs_brjLH{1kn1)?HwdQvBEDDRqQCvyY3`5Cax{F? zfMvD%jF)>m(^+gPF8B*?%-yRtyV@B)Jdm>k-)!hxje*O3F5wdi!6n(fwNeYjaXOPG zj+__0<;rMV3f&y2(p#K(s&tzPQ;Ki+6N%}y!THgO&)vF#)AR_samkBS`e!*>V^8eL zc-uv+*QdSF6u3T(|H`4&f>z`9F?fEX%xg7HA3J30lhzZ*&WbSdL8ujfM=9!(d$e&g zRYC@nNZi$j%kLS~W&#K*H`m?vH+gMye{Pq{oj%<8CRt-GxT(M7#AtVp!X(5y`JeoL z;ZBHYOFz19guL3zzOf7U0{mof_ZKnQ;>pr8DJLP?cAVE%+a~9vWUSoO&53GgJS#=H zE(^)>8~;32OCFP`-9F-?ZmCs!xdEy4u*ubjT4=T}Bz<@BxW2d0Mh~gv`k%XkIm^{C z7N0vWM+T*_r?#t2o9U4wOkPx@#Icu4We%Lt^MOWD@iFE+J3F)KtWFi}rl1?V%ns*j z(`L#1ajd-P+fHbFv$@abTzxbfJ+D`;$Gp{++Oe*Jyi3U0$?8K8xuwhGq(1&_D{ptK z_#0!R#!b%T1Cb$a=COp_%yZJuZBF^DakXM%gHjdAqcr_ z`0IhsYjyM9r!{WF2?=PpTC^**AGGS22ft3d92u0{tQp_AU}8&c@(U~s&^YenRW>PG zJjvG8LK}QF-1XCh<&s#*M)usL?G=-pxQN`Qa|X5QwTdn;`EI9sL_=04R~@7AS@m*c zP#X6%-M0f@tAoOUA+Gw(#)m`5c@YHzK_JDQU+IpF|1&V^1Yy|uVI}^Q^kx+LAd(F^ zJNV?DM1e2DiePkzaAy!}ghxb6cvQ3mnytje*!ZH=zYA9D1e)`M7|qw!yswUa>gvZ= ziwpgK7i>QmA{ijCt=lLb!=c1!_XD)yc$P+fDfHqI&*><%K-?&DKz>J(x2)cXY}bzh ztAtyFI7C=4S^|wBtAtIWCD3fhL6e=vyM)~1-8Pr=-8);_vEt9i==Ol~mv!7^Y>6jh zbXr=U@g&c-w|ho&+3kGJOc?9)mvz;ffafpk%8BG=joYntmbqG0O>Bdk{PGz8X60tR zI~z_!8+RR5}>*)!oQ+iQe_Z0|c6O8yiireWlm@xq_uZT_fCx(%eJpk4J7|<(i$< z>NFbHFV}13xLQ@6{`%whtiFIk3&g2-1IHCiC9y8s~^P{w$5s`#*j?}D_eNi_LZEuFMfzu$;wr1VY)@NT2X94Z&9sQD*c$6 z)2oi?%(^q8XNcTl(T~46XL`&{!fmNxXKJ`3V6FX^8jb6(?7{=2@~A5RPaaxzzmfJu zd}TMjls!Hm<9hqWVtdiIK3{hRO!#cM>m(M_MB46aKF}LqB1Je z%Qj`NSFU0*#oS=kl+fyg!?0VtDYNSIFD=!>MA5&SbISq`AKSNFIrT+QcV6_#scGwq zFWb{v-Kt#Q)fu&})sJ|>MW6h)r1jKl<@%1il^@L!FZ$&BiM8p?Nb8Hd)yv0fz_0fA zJ?(ErUf+}V@{h*T@S;!tGVwNRyp7gR&3pavi5R%(lmC!-pEJ?M>u2Vp_}SAj^uwQg z@^jPH_jWGm&(5eDCTSDq|HI~K8;eEG{MXKi&Gr4A-l$szLub%F;{W7Zh(9LhU-J(l z<*wM}vP9!CmL*qRRA7a1;h2Jle-jTc$1LV#wED|2!8kvn0%IM9C~Cr3NnWEeB%?7{ zmlePN@PoNqroW9<8$ZT4%OR1Jw$jXh_++v-t12ykh51{&Gc%6=$yNZdd5V~C)IX# z{%Ub8qV3N2ika|P(996e>9J~ZpDT$ucMsfm@bsoy=JL*G5OR~)DjCg1mwEH+19t1# zT|)YmuWZL`QLQbAu4_*8j7lHuD$(V=O1DMn-YYnk_YvhJpEiD{t&N8LO!cxdDpO<3jf-t2pMbmt zjVFhvorcp&WG;fd&dou0G7nRGtdCFZ6q|3K*XFI7seJYM)4mRzpZZ?bdO?@^^QV1F zjaz=ItLz%*Py1(O=Cs}^-O#wVGiPs<5`T6wciPi9ue)C6T5D$nC!6Qfn5mVyo;^dl zJ~X*N)9~GeseLfqGJnQQlaX9)y76~O(({6U=*}B))Xa{TGVNsJPIjI_IZ1?@AURRn zRuVk9P!$GVbu+mxW6?KsW!O39*|T5dCIsSR6AlRtWke%xM{JSF3njqP@hs|G6l&VGEU zT%wD5toY8GMXoAIuPb0U|B$-LJ*rych4ttYMcJ~wWV&rD`2RHJ{^c{hGCOhb+ z>Ub_;16Mvrnm3|LXLcbaPxX;*@4fk4A0OMYXSQ6Q+lzJ6y_YEG$J}Wn zmEK%JO^giZ(JSq|s!HE^$Y(YwE+w5v$puM9GC^xluFn$@wYi|nKwgY=SMQadS+X+o z=X|!RPtn?H`$3#qlRe9~U3g)f$)_dxTSi@YmhQo}u21}iW|!Q2NHtV$aL>o_A=RK9 z>mgMm@Nqfcnh&Wam18}m+Cb#9cHSBvQq7XadPuct13tRvt$$@K>m;wg_`&uIKlx-@ ze0b39X|u=OnokINzt>EtWwR$`=S|oOA58Rd{M2b#z;m0~d@MX|YvK9GW{>9bVbd{3 z)CP%ZX0q5#25DyHSxevZrDw|M`o4TJhR>t}c`Ve&KXT^H;}PQQu<8!=8y zXiK9Tpxhg~vs&FOKsQrDObs74TJ&e5Iv-VgagBR}XN&KQsMX`?PEl=t4$sB28k+XM zIi4dEesZg+dH1B|vt2fmTa#n=?ToClGh(ERf9+EKxeT%Q+u=`V>`n^%LC%LLnDYcu za%T?dayJ;u19@;I;8hV{2fQm{%*-2590^KyZj4IXlZxU^u#Q%lQR$e+!FoS1?J}k) zqSBb{1z9Hp)08o^)0fWb#&F(vk(+sEH7)6%&iWe*&TXpJ+2dDeG;=1j*V?(;+s$j| zWVw0myev1bU6AGGv{Ue_tr>C?b$gNTM^4*OESTS)F+GO923X&+5^oCJAVw z-jN9&Msn&7%>A|uJ=Mp#7r&ta*I_Mh$!R+`sb#6n{{C0ocau!6TAc{GiRV;DQ&LH7w1lIgCA=+K!gobWI4)Yk_e4uLDO$ouq9qjQB0rk}bOfb%IzNjuz{Q#d0DeVRnuD0@S{QcaYhsuA8R z)kGPq8sS8#Cdy#d2p^YfqKsCJ&{g)H*n@%q2|p6Vdd$h}Q6}OtVQ613g1}ymprE0$ zAu5Bo4z-&DW00@~rM>v3yX`;%wUu^Tq1qYLgM_Dg4Na|3md zVALs%RMsy*;qOoK^Pf>3u)!7hVXSNV@vRNg=$b2LeE%zU^!=~===X*0Bb<+B3sLZX zo*;d&w`b`@m3Ha8G^)E`aCaW^Vte|vN5QT)>t$zQ9O|m&^m;X3rMlY}38fO4_vqy> zBGHSlxF&vT=_{)-@L{0n*~=~pCwfNLZ(+uu@H&UMTI9@6;F0+y6zr*l%YryW=tGg+ z_bcD$SK0A+kyI0C(pUT0L8F%hYMnr;d-8(J=yrf^g<%h!sjbS*#!UFibf*M&v673g zMYS3vCUeuSS5k)E=5QaqD5F{U(Dyk`({3f5vg9P%hNvn&vsbobTVP}fBlCGrg<-Mn zybI@j6h=YhFhfqFAm?{c;DbPl8xwke8R|b52I0*hCOv%;s(&vG!gGy`x1suLVGzWN z#Yr!GjVD{e%xC1ROt1xrcOeRcBQjx--DO!(kn{5>2#Y|9OX7#P7(9hS3q-OZCligF z3;tEGKp@3gV5iCG42(KK81}o3$`Bg^(Z+H~ShN45-$AyS7aR-|mZF4&;?I`3;qZ7! zstLDNs(HLYstLO))jWPdstLy`)jWPzstN3z_wA#n^REYLjj$$&$#kUu-w+0Yt}FW; z`}ecLAh2r{2BY}@ghBYIk?{&t|4A5xH-nf=>2~zuf-sOZf{a)aDf`7)p)bhE;#7Tp zx@#>lVKn#}#!@_1X3$Wif#w!Ru~OQ8qdgz-z3?#!RO+0n?kPIcVq1HWhFS< z&Y+*CRv?>Rb(w(eCXx$I=@mCNyQdV}_A7@=z$#1`gd{OGKU(*^re-Pw7uAko3D;U; z-g9flR?LU(DC{_qQ>8JFWbH(O7s77^u}&aA*T3b^uRx()A}uu9C2JK5>=J$@h;;(_ zIlG5(!hb`q3ku?Kk&|&J=N%MSC6J<~s((dA>R$zFonTaaGeL9eKtip2c3%|VEe*LL zc>$^yQJ4)P-9k=g5jlrY(2PJzv#3e^^FXZ=j9U3V1&)5C4kXlus6BNsp_V7qIG0{6 zeYy_rf$DJ-c92N7)ee%g4+YH#q%`XwssDSR)(J+C<&^ zD^%N2*g+y~K~Cl!Geq8ZP|%d{5Q^_4j~|w50e}CnqkMW zP38EIPO6V@_T78QMC3^#zS@iH>^783xxcCB)YdYI(?{U`q||+%b6z{8*xK%#+q(ku zVqrFF(%dAj?26_LYj4tU+6sGn(pKcPE(UEyOfzL?a5wWj+ufIOqGzb=R>*0KYHKV^ zjJLS`)=_MDsc^$<^rjVVeO*v&#xH|xC@!0xvw&|FtmX7=#R`qyiK^nnw}De7HX{{z zL1!B|cCRDZ3R6NzR)&pc%CO7Kuys{F%2evP9R;GZOBA1@O4P>DUPa6&%4u`^dS+EL z^9X&fdV_3{c)ivuI`7U?UaM^slXYNwdtR$;6x}RO_GPzan5bxoJ4 zmiro&lRh-WAvWCY%Iuza~vC*H<-P7wv(J(4G z?N>ck{xOxgCFCoN0l{SzkH-5NCnt%uwCSc$eV5@H1_v(Xme1tMB&YR8T$bIe^9)=f z*`b%|zk2?4yQ>rZXXs9y7tI&#$9*{wBge&@h>_7zYgeZEZ6Y=6wPUZ$s)7Xd2PC=?VRB@pVo}L<%wyN4wMI&-_N=EZM$kSy?aB@j8g7( z4Lcq^x_~=zefrJ9U!1zkm`K)^mMmvBFXp;l)w%5{5#4Fl&VX*!BwRNW+;z0mI%7`j z?B<%Kk+v0IS4Cdb+7#X9l^2uoOb#4B(R&AOJ8&XLT#Dz4?7r=NihoqZ>C<)Lerm|( zX)+((qp;41qcjGgp}28rAtD1WxD}IQClsF1axZuFds_EDOKH|L(Q7w}ZYDX=Gn#QS^vcz$-EqU!>TbI_11VqOojT(P{rGlY zC$hU#ZLAzi<4h-_+aYYQlAXu2?L~a1+?i;ic8t8aJi$NY(u^_Jt|fej-C3_mk`jCN z-d}B0M$x~ucvm^q_Z+dp7!aJF{Cf_Y6uwoEUDIY+%MDn%x^j%fnj<*T20G!Iwi;{x ze3)p>c-l63mtgN>oi?Q>2~9@XZPs?qtG4BFl2vz8(E8@iLwRm$)!p%PB35jCt5R*? zT)7jmi7!8fhm=t`35l$1W-qovnT&=10YM#)b?-$>;* zz}O_fG-1?GO=G85+tCJr4WZiOAvn}>clT6O-*Hcu)Q4mUdJ)L z>WD6Ax3*Z(xDzB?o7Fxdw*;D~9m9uF3B-0l=ThmF-ulh(pmM64VXQC)1ZTY2JapT& z+djMzk=cx`|HM(V%@$Ii+5*O$lD6yT_SfAA4b7e zc(9=GNLfMTt`{m|1Vuqh_n}~T3BQk0or0v?8z^-G%`{EqgQ(mc2sHxTVkiiYiI(uV zXbCTfmhh5j3F5*ssqt18T#wWH?Io*ME-{(PmeZ8s7QSsTo}qGL%Z4z~T0h*`+Y!`K zrFUIU?|YQhE0^d@HyNgcVbQ6LN*uOXL*M5(S-sXrOng};^BKatUCnh`oSUMSLA_ zSVV@rIK(+}17N9$HNb#~BY=$}ZU$@-k$u`B;#eJ!x)tytDIC5TqNK1EQ#i~NK97Pq zLikgZ_F`k#i$KY2jqo-K283`jh&9605XCTIdJt=b>qN^@U|(RE{a7yAG~)R%B15^H zam);y<*}vRj!YL2ja*eW8*d7rQ=D`fr#D&3RjX<+tsC67n>wMO9duH@=6 zsJXszr&QNqa?@1plgCJSkw=t3Z_=btty>4KJ)^0c)IfRpSYAN(!o)Nb+$Sc`I)BKHuNh}=uOq0|!@0QkL{ zKO*g1fdYpFQW}C<1m$AktO0BiaSz~W5xv2pm=EOwsUS$pVYU>y&DNq=Yf8I_y6}&% zi=wb%6Ri3dcUM?6^SiR=XU^L!k%b2$n+Mj)l3V?{w$UtrYMK=S{jq9N>rUko$1hHY0%ZIFTKWJBn7B#}0APy4tqu>H)DLegEDIWtKFXi`v zmp&q#USNMIUkU6ANxFaOg}~lYCQ9-)eo4JY9D=nKC`jRJfY(KQ6Sm$)ftK)BD7X&m z`Y!NYQAZ0Z?LgCA(wx9<-_6zXdi^hGy zb(lz%nR4y_Ty)Jv;iM+c6S<%G%ELiFkNB#{{Y1{J>ZGQfuc07g1X41Snye*(RVQo; z;xa-98u&>aj)Re8QcE_YvjIBW7|aaQ%*zN5Z)+GOEkKNhlDSV43q!j>g2X%K++PaX z^3bA2SQW%U!fq7K{fB^$m+}+9eWm;?kb#lI$WD~=qv9Y6&brfJbYZZcWSz_y#fk^Ocrmb6(DiW0SJIu~ zRiNL3!Y_H|QlKn-8jgLkNIGF|0U9p}cEU`Q@sCsOf5QAh;i@2Ziaeb-3kA0=jujMU zmlZ@#sZbH4H3`+zQ7{OEnL!*Ouwj_@g*=4KV2hMSBFmo?)^Ori8Azf$xB#Hz;k7;6*C!UKZ3t%z(^1 zyW{ZaZrmqB;W8lZ5xIwWT;x9D`=y>(pl9IsS?CaG=V=rKNBH+B*z@dWi4dr5xK+ZI zQZYcF1MKPQCoCM?My@{X_X23|1?n)VAByNBqWlch`$JWYAgm$6N1`RLJIRUcq){!A zbMC>ELt&bTTSV@uI?Nxl^^GV<4xtvrA;J)f-y3*55~^#2TY@-5SdHSDJYEy3YlO8y z93tE%TEgupz7dbtNi|_Z5QhjGQ9P5!o28n-{`%@_Kj)x+aiG@;3=XFV0u5oz2{hu~ zu3>V9cTe-6W-i)`pBfzkt}10BE%3c0QF8uMc0StryG7Ry6pjh;PLcbGYwrsi_5Omw zZ73l16Ax;I?*T3SE(*qnK+ag5m8P*#osIT|_QQl*w0-&LI*(VQFe3nl5zLp>JicA3 z3Ff`YgYPl$7{LG|=)adPMhMsbUeWar_$A2l0ZiA&(?+S9g8~MDF;y5EW{9m^a*S;q zir4XY2MR0^7;nW=3^9JmRMbsJfOA5uweJBwL}@R6e3aOU$oSTq!OjiA))oSmhgrh-y?I@A`z1KGQUCZ1Ek|egRj9;r7!f*Grar?f@cR{ zG4`V#`%z~fm}8t|VzhM*x(swJ##)czx$CB)cnC{Kruz^VpllU(i6qf*W^uV=9n1xA zu|Om+7Wd3y2aI*1aK;k3OGB<)DvxI4teFcY6w!W`qUiUt%@E;k6uf8a8>Mic=ywC27Lo7_3Mf~PQg{jF3wUDv z8^sKY2T(BFgo7v@#l{_NqmKpZ$v4_( z9&y>L=?s6$O%E@MKE`Wvp(tjePC8-lwV$~gyEzIc2$4e#xw5B{^)d>k2w|G|Aduf| zPsO`LYgdo$hLU!f4VIlJ{c!NOl5jMLgM^c!C43}WO;*^%!bZl{heG85;dPWL1$I*k z$3;&#p?V4*ir$QsLJVZ^7#Qyb)*yiv`2BZViy7BU=Yd2PH}+yGlG7V(1hHyy;h7{;+EwmC>{E+Sm;)j=?dqH(=NC{AEP<44us5P& zKzJj7n}aw^SS#Aw02@UlJQPG1-x4Uqy2ZytY=U|R3U3DPE-C)G6!!B46!wAGi#r>T zdt(xdf}EF8xN1sDr4Nx&j|__=-C*{Y*4m3Xqa?o~mI<#0aT(!t(Gre|mTCC6y%FQ3U)MAeqSs%-__DI($SAPy0vt?dpxd(TE;e8jCHC$oy2pGHA^ z1X3!qii~+dT_*@5$)m(LAC)%*UXAbzK^(XdFe2I&fOR4gwgl0Jv?vx?z3cs4D8;3n zDY=7Pjlymbxws+sX{z$bR;y6ZQNpGm4imPZ_>&HgcZBL1;m#lq6aGN7gc)#(6DFZQ zh&95MDBcv0XG%4Jk-8geK2V0YIGC>!B)nxwc;&f`;feQUgsXzhIzh}^p1k>M(dc@V zaM46z9SR1TKqvfq>S%a~h8cUHQxMb1+VJM9@@|-XI(VoNo(bYjgae`_yeeA4VbK!k z8W)W0&#WNU2v>`iFk7^QYeh?#BU-{-(Guo~mT;YD3G+oukbb$3*k&UHQQ8!jjq`0( z97o|D7~&YDWZ6|8U1yuQ;9+(WRt0ex;Wp6{9u_U( z5z!JJL-BKt$9trj@OTiH5uOk&fiWffHb$^~M5ZWWF!dPBNDQVPgBgjz)am%iV7E>X z7nVg%k=SmSjAsMcE%x*jC6nq>kR%;LY`!J586w;l#2P^|GsI3x1Vek&Hs2b7`?wzm319vvb!nj12}W(WTpcKD-7Nq- zwTssfDwYQewH1I{L?qByJKotOuPIZC#n7`APO{oKJnBR%Vrh`T=0WebqlTSvK$wa+~!ii42@4?JO2bsLTM8V`HoDAYH;Um!!*f_H{#Otet^!;uBH<^3IJg6_Q?$DPcZ;aK#W2_k!5V?xk3;m!34MV(M4)Zn z8z*iS^%ek)W5cC=8Yd$GvhrmO-#J%fkmyIKae{B-p4Eo(pl;}tCU zYXfWv;t=7tMN4=}w1htqE#ZC9622!|!bucAGkDA};Gofas$ncAQLtkYE(@)O35+Kg z)e9#aZw=LT!h=B^CNM_Nt6f#EdSB z86AijT^2Jsz>FRU(Jdn!)9A{n$>XMp=8SkO}Nob25GU*EF!{q7$Fu zY%XSusyiP4I*!%2)~g4tS6g~FRF5Nu$qx_QliPs{Q84oei-R~qVARkO?nWV*_<*Ph z92o3ngcnfAARYn5RjPUXyi^m8R;qdYmQ)jtRjPUXwp0_|sZ{g$yHZVHk9=s>g(d=f zHX}5z6W9}M@`O7@OL$1M1nXP5CVBjHsIC)U4&o5Ox>+(~H|t3^%W8J>-O##DU_TH@ zF6tXlwJubT5H<&~M%aSVg^Ra&{hP2pd9+q>uMQrJbMSGM$c!zED{wTqiuj znjkJC(B6gkx$0}K;78_dqtT*WIz@{YgZv~)_+W+t^M=_(cvJNhm?h{rsvoI7CZWAl zXD;n#;;M3PxX7##=A-y|z~k$sn!rnFUmacGPBiMS3e-A*RCfW*+fmcPEv9V+kqhMLn@kqlCX% zqHtLBv`Irr57auMR#V;JT#UkO5FZh_oA_v{C$huf*k6fidm?QtLV;Pr2#TK>Jl-zV z1X}aeJbp~733TMEy(4k;U?A5CW~=G2tCL(>f#K@F8z6tz&VkHBWW|2%$EstHFc z)jWPnstLy`)jWP%stNB@s(JifsU|R7?^^@a&q&$TEhtP8@dXs*ks-bzA`Q}t%Pt#N z8w$m~4U>LWq1EcpvPNK5oRI=gNGyhGi7*IkkP9}Y))Q(uO|)NfZ-913g53eaauj@0 zc*iIOI>G%EZO|4T)SyWhNG)(y5=h6lNc-A*Yu!x80O@mrla+*dC?UlZq?_* z$>ge2hi+bk=qkSy;;P%_-n47Z?OYGto_hh_;!Jt&%Azm+l~NPt6nBr6hWs}T`X*lQ zI)4n`M)WocM}hdB$jK;>^IuWWj6h1WQHa!fLaqEt$2~CdAPT(_kBA(QCj6Yx>=4=R zArwSHcs__jgjZ17i>)0*TJr(&_)QeFBG7@a_6}60qy3@D0O2JR{t-X%APRr+as%EH zh6B3fih`nR=JX^0{Nf1zzJmeKtJ~n)%VDFVH&8e{L{br_hD^1_47G+QS51 zqeR9ACj?r+skCO!{bV?f%J)&2XX2baK~6?pe35w)116zDN0@2NM3%DU(Fq1b1iiX8LIEd{e42F^|?xpRV_ zgf>lm%r-P$X-prpF}>25zIkT0C&P$kawrC7l1resW`4cW{Q6*w>6OOx%`*|6_bvlr zlj}2{bN_^J8Zt*KKf8)CGza0`MASMa^qS}#976L?QCPu*-ER13Cwykg{6sl$P^RuN}$VfB(3Su6!&DUwKoTO=P!8psgYH=_ByX$!; zMuuNc)LLgg;~D+gE`9UfR`5>AUDf*`*F&*5DBaF67mDkG()O65jS5j3v#pKI7p6?F zG-lC8mN4CJGz8_U&^$83*e!u_DM}bS3N>L7SduX<+Enf40EWMf=0}uGVFij?j%|S< z${0W!6{2*ZZiP~^=a?Iz+??7h+NcnvG27bMd`HUkN@EsnWC_!}+f>f2M9y^ATo;7v zW?Tx6=}#Iq%3hhZX(6eb37)Q-Tqm#(W*To)4y*Yh>i{VuB&K!#Hw9ygPHO! zsnwg{h(1@A7O%9l_*@y&D~;)!TQAKyY9o_c8|`G0J658PbjRT2R|g5(rRoPfRLP`m zf4Q@ZJNam`A~u_l7lr3O!skMl+cRa&$kCiiZUBdh{1Mb`Rs=~LTm)NO_(vmw$y z<+)>Fx^(1&$uTE8b8|M&hW9N`;Gq~4?vcd4e;4FF8$NV|oV!sl7YU^JC-M?TJu>W3 zDtWviS{WdxH&|Ilph4aIu6MtU$ab;SV6^Q15#LzG!_$sNYr)`$g_1 zt`NDGxU$p}zgz0n29b8Yih?W3Da%z&qDcPXzrL#L-9;dI`347(wJ>+Z2o-8 z^h#qEZDa}4c|Qc@k3l}|iqj0GZ_x{@;SKj@T^#}^43E@eQFii;L=eBru_90S3tHEahuLLnB z9*k?zdR{O#Kv)pO7%=vR_>UI-tM}jFX;>7bhOiKYf4WUv9OQYU#2bRVVDxt2h9J)w zC2k7xyiwwoATJnw?eU`Pha?7u@^d0C2K>B;O99J7+ydAp;ts&KMZ61epNP8w4~yu- zR=E#VbETR(4j z&H?W3shM>r%se;uPAGbD$&RT$JDJGN;y7U$lZ{0(HC&8|KGGfIj7*spp<0;d6BTEY zNatsF%!r$nL21(_nZ=Hk=s(5TT^Y2V*oCT;-(vFG+{VMz*`|Lu8H}fY{bF~az1qwE zR=)-3Qs}d0rwFgK4ac81jOmre^vzrB3=HX<9cG4>?UZ#t#_pItC&u*3tj$cK693LY z7)O`2^-ccB!RhmXCb@TPcd^tmZtJ1Vt|V*c^Z-}ZannnS{Cdr6^J%crI)4U?2~x>V z?emF}thgnpX&TRLJwGQkTW+DX+`}67-tnZGj`HcwYc;TBSNHpJ+)3Rcuycj)gfYF+ znBHbX&r<$a5ke?7p~9A-^WCq(_>m$SWT~- z^GhhN^$W`e+$-%O*(+`G2Bpoe%Jel>qR-E}Phk--)^j*i3D0h|WvQ7yPFqTDOPauR zw<+k2C3hz6)@5Y4*&US4=C@7d^Q%OX_c=)vgFRQ>6goyTSL<|Dy*%UPBy*j zJi6`9O`4Y4@eC5(xZJzXZ`^Mw2164&&-w60cKL2A>@R|X>4}}^ylFSG_$pyn6Gso- zvojNZZ7_bRqSK>c(!l;^B>AaYml5X)_N_NgOc`!|x^EH|PGy(v)t1orIob58^Vo7O zVnA zxgIAHwBzO`4F9<9JrssQT=Zm+11=HSdp4QvzJ~(yglj>?EG7I@5NiY)gO;#Zv;>;X zg;ES*zmR7y2WBk-LP*Ui9pR^n0R ztykb1uAx5;Tn>MW{vmzGpKemD&5CbyKhk^5fM}WM}>;Fgib1dL$;4I*M zaa1V~R&c=_c0cT$W z{)G_A*Mq?J;@;mZ3VM+jrIkM|dD>bcYZyOY9v?>iROt2sbyF+5jqml8*I38W)>*aVhki6AE_H7sN9uTMgW0|k-067jPfIgqAp=&R8Jg4!` zT!=5shHg2q2lI%pwJbkZbb%CJoS%J*@RhZ|W59cY7HbH2+dskI*_OwguljliLVL01 zsQNhp-kj1t`!n;O#_{1XU)Q1RfS$a4OJp6K0KODzi(-3;i%L67%i|s8G2?mm=lRn_ z7$>0GRpfMkvDEJ`@g?Bgvi+r{y$!$*Z@|9c?6OKmJR)_>MSJn1$GukV=<>RSM7&N3 z6dk2qjs;)O2o$%KxS+(@6<#;=N0-KaX$O~=e8NtY_G0Mod_3HTj-lP6vIDzIzOGYZ ze;q$a2|NV64g7h7*w1jh2-pW)T_VKd82`hI^MWtUZ(lf)|CR>*FLkz+S=)*BMfsD$ zyUKo5^Q-feR3oML7?y1#%tj0Mh?%Ajg$2Me_OL@gCG`|2Pl$Qq(xK zo%TzQtEly73mMx9l=k8ef6nJ)H!JX(jdG~$_d6w?Dsk$~SjVVe4xB|YUVSJ#al9Eh zKJ`oZ6KEh`eI?!|hlS>6L3vy&aY=~}mZi z{+04P3FJDs707*gBT(lBacgC~w|3dt%2Cl~OL7?uhI4o9&aoG0TIu6uv9exPjejeb({PV@} z;Y;TYP8P*;w_@8O{u+Mr7ImGs2@U~uzUzLW$Z^?$`Xx{tydCY!ibFJx*8zb-uRrv> z`eCWpanx~DyH(UURlgkV53a*?65`#lLE_%=4LOg_+=%On(*9Gxn{muIcLMhV7kv}o zp#tPoNg54=@hC^t{+3 zhvEODc<<6){2wo>y%Vs*xK?hG_Ya4FT)TbW65LqgK_KTnU+nMuIG!1fwsyleqE?d>!+9XmjSm_ z;#NDl9`%^}0$-g1<3?RSH@J4Yw_rbo-{*b<-}zVSiM?CXV^*o(y^uGfUi-5J$M53! zx-$L;Nyh7t0PkNFGq&Sb1iK#>z`lxh0LSz1z>m|GdR`y%rR(EBd93ZH zmw$qci^O6j+L6C+2Yzf!niXU5N#T76z8(@No+^*uE04Eo;!C~GryXVe?h>`%2g~E{ zmUyB>egC$!v^TS~$7-HC+l!U>yA>U!xIZi^+jBqTOT#%Lhjy&kpT>w8T>- z>O9aqZYuTj%D4`c$FoX@FO|m=<#T@UwLze`uf)4bRKJSM>k z30dt^&0J$%{!_KHXs6sqV%?+suY7UL@I!I`OnFpu9F~Jm8(V>WK)wzOg!kqYSD`$N z`jtGus|)dch~p)|1$W8yH1(@ccH(#^5Af1_?Ulo@KXv_9v_rMzVgBtJ*J{+WzgvMk zkL@XsUnuc#iEP`!|H>EN%eEIkzESP)H?l579e>t}=ZEfHa=pqQ{+fzo{$d!BzmrDZ zVj#zfKQ_nlT?gC>JPzyw@|PSR1@Z?H7XXg~=L7j$n2eV{(t0IuO^NrE_zdt?=%@dV z+*djdT!Lf1=y%RNxNi&OZ-_Eq{0+~!zz+Nz>E{2Ry)OZ*tEl?Vdy{*!G)-HQw534% zUeZmL_mVDvlB5fjPtpYhKS^n&0^I^_scp(8QYat@g2<-q>j$!mh>D1cD2sxq2#AP) zf*T+%z+Xj#|L=Fs%-!C7SxSre|9^#>`|j*>=FFKh=bSl%_i=d71O4QU+LW{Kx?ti3 z@20&Q?>o=M4MlkKg7@R`=4I&HBhet>U!ZM@c|yU)Hy0>9`(k>Av{9Ad-Q*f-}3|G9CQrk}xn{89To z)4sou_~s{ZKU=YSl(E!`ikW>8_IbQrznM<)?$RLLX<5i27-9br*4c{DIaiJg*L*FL zTsZvARYwV<#(!nEAihfLkLSO8cNgD{_^Vtb-kSfl_qzBu5bwr;$u$1AGhIA{0vD3x%lBj;DN3r{Zq~DwApb-w5KL zuM5|?F#dy!UHO$mbzknP(EMYUx%icc{{ryJ{nPl@*17oMBUJ7Yj~{WYiyw`6M-Q1s z^MC3@7vGL}u0QUd#y5P*#WQ?-1aUO}^3O%%9bPi6#&=%f;^(3KRz}!=8h=O-e;ndL zJcEB4f53Gv|L%=(y#4!Vd~d5yCEhOMa{OLvpLLP&NAUY8`#c>9@1!2lK3#aba;|8B zheJGMZ$CXUT^;OFq4|SG&sI%lloh2XYEcsAp$%i^g2S?XFhEYe! z=Mp?FJo#oEb(DOlb4o@e6Fz%b&PzT z#6vwJb&Pxpc&KNjj*$;_jC>kr=|deOpI7ZeU7~9*e^aN(hq^=uSN_h;3BURKS^H3z z=+f~wb%yTSmCG>d4qZ5ZQ)lSD-J4<5A@ZRPkq>o)F227v(^7}XhdRS#dWKPl$mbsW zP-mD-$1v*blHu;#^~-&4tvB27bV@st^;1tsU0}I(FpfGxKGYHNp^lIbb%cCQ##1i8 z3wQN0?a2%KPw(=%caR@>srz%`{7oGoAL;=4P$%c&lW$i}GJLS#tb;nc{_-X3V;<`E zTt5CjC-UvWspq4Pj}LWxe5liN@$Stq>d@TxJM~WXD_JkwM4cX=h6;1 z-8bW?3v=J^)_1x7v+dO3@u3cn4|RBasKet!-JR*xQk;T$9C zF8NS*$%nd2KGa?Eq0Z8cAAeIf>AoG@7)D(spQZLW3~xTY_Mwi_<>T*@?Q;#@d~UE0 zb(MS`#pBW^-;8@55A~JQRq~;(k`Hy2e5kABLtP~w>L8Qll>25{>MHqASILLEN<>zneB;9xN%{b~R`A}EMhq_8W)K&7Kj?(4hZ|W-fh^`WE>MHsCA3P53E= z)IGZIa&M-gZjujmlYFR~KNU3e{Ywcd8m`*L!Bfa>LmG4 zC&`C8Nj}s?x^nrOI!O2J-VCG8(S4VDGtB}#)Jsw)$%neea_N)dOiP_#GW^~4%{Ef^ zSgu`+qfU|!b&uuJF^;;&a`B9#PLdCGgyqt0t#H;!og^RXB3(WFP2HpWPQDpOU8D== zZ|WZ1ck<0R>LOh@e^dA9zLRgp9oR>FGQInzUh?)6^r3Fcg}+ zssHg}8tNL$wTp3;_VH8Fm4o;HhO2yQOTnSs_-t-C^|;inZf^c^`Lu~kW_v~8 zMtwAO%l*NFX{b|n=?2YiOVe^Up|hq`AM&fnBEyYJ+ianv=t z_VG7$&U~nI=0lw`AL^X>P^aw5arqcV9Wx*5nE8l~8E@*C`B2BqhdO3H)G_m+j+qa2 z%zUV0=0hDbpO@@I9Wx*5nE6o0%!fK=KGZSup^ljkbX`XZ$IOR1WM-l;_gFgf!FXWHU=0jaFAL@>io+Fp7 zTVLFB{{DOKU)+1mp{q75T^5Ay|DpL)r|h-c(MK=&z^r*oG%XVa2{hZBWk>cLx~#bW zhw#765END1uzp=}RnH;C6^9;LJb2yeUDh12X4x*w4nCx(*fzB=rO;OFv6Zsi`8`XQ zu3C1~!RwZ-FMeoc&$^{c_C0uA?=i)_4({D+eQ`Y+T(SD#o;8I-sY5&Th;_@B9J+e9 z!b(~ytnXbtb;@$Kb=9gRhiq7nP;@#Lx_)g>N@#D->Xgu>s}D{I-LM|b(eOi8ukTsE z1iiv%SpBYO00Jsm^U|I*OzTBj;i6nqS021-$@>UbA#n&zcnoLR46yZ9o|)tvza8dW<$<`N6%*i6bbn{g4ekt9p0o zS<@+#rZVegD!eQe%I0&!Gk(T1e%`B-cd?<-8;4(`3J6^2?TnwRa~0Xj48NPbv3^6B zw_m{hA^;~IGahofLqO>WM#v5rqvjIOF8xEAV*0!_Rey%d(n?KcN(5W%zHZ;RDdSm=d zC4R8k=Aq*Yh#KjeZ)KM=&TI7A{7lX(=GvLYH{bpQ^Nuv%)Vzq_$1m#=iz$N<3w}6n>#CwuWY{uQ9AI zjEkmhZtyq+4Y`~*+0S{|25$#^Hnn>V1#hB{+=B?1Q1E~n1;5wklEw_SoQ53gjW)!U z8f^>13aDuiVU2=%!@9goF+1E1C=DjeFB*vd7{G=GU_KFZR?e$N6M*bPC8pJD#JiIC zKUbzkvEc2}<;^R2GrPUcF7JSXSKo#7t%B}+dq`j9ALZ5JJ#0f^2SiRKPD&zj7PqY}uHF`BIx8zNhrhFy^WQIEYGc9= z%QOI@BfOm?Q64GAm|yoYg%FTAOeT?8bIFj5*NJ4tZ};|;cZPpiKl6<=KhTo9S@2he zWe|oR53S9B{MbgB+lOVm(sr$oYR@}bs^x5}Eig~kH@8)T#`q1W!hB<6VZ*|Kb@5Bl zESLjZcFdiL;dyZqDa4f zHk0~WO_!Mog<~AtTVf>=2%q4LHUj!e@ z#)RD?--7Rbg$*;lV>vr4tJ&e@YzCXq_NK$zPQr`!o%b9o%HsCpMRMJkR0@aZ9UQLp(&6y4V-*hnqj`0cZQ<|~2t_&^0t%#XI9K5yWcVcuhx^Eb2pRUx z*Vic=UWtT#+J^l!fDIl_?t-)>F>vz5SyYs$gl=N1kR%j}Bb!>z|ze0Z`l z9S&DxU8Jz#=bASLhc6sg4h~p`hzAeI!l8KnHLMj3yI%V$xbe8{>!+f9eI0!bmL}Tp zo2N?0{QKqldb{oGE2Vus!}ay8GJSp1j`^D@eLbnazWy=N*K=%NACC0(OSZ4KMEm+! zw68p;V19_`Y|-;U&a&VN^j)+&`|yp8HR6l1W9NIg{jRoel>`*I0he_8Zu79nXAwln z7_*F%o#O}OF9bt)%T{-aS5Jvk)}JBb7B-|o3c~idpEpGhlrFjVHi>T+o-D_O$KTDu zX|jV{2>Ir`3*Rc4V|^OlVgYrM6>TiE?~e%T{cX5RJ#2|lggNa9MaWBoWuKwH#=xNs5ZCD;A!#aKnm)3s;!h?vqyF-@+A( zH7lV2!Iv4ELnWSXzWMQjlts=JTiNUI;_l98x^76K+N8)DezxPYD6y5ksml?KQP7Zf z7PBg+JU!DbM?f+BWW1ubhX!KqWcPN&mWPJSDOToIZ1B9JAmd>rSpyjtr6DMKO%76+ z8U%9pDFP!lB=336HnG##JVtV}coZr>}h>q}f zWOqd5GsfI1(q`$_Y!MYPGHV_N`P>7)C@PvMZ!0Q76NUBoI|U(4EKkJ90Np87kVLWg zs3hvDu=uDXiqyH?7C$Rdyk`ig@tF-6z=f3aEd*T5qMTpwXOy=8ny`Xs`=9Ku{V$cY z|FdcBzaT6=+Wz17)Beh4zdfzB7ly?}Tl<^-TKlV#)?Sj<+B3r9qpf|V|JJ6$_N=hD zXlwu6Uuz#PY3+4stvw+uKHAzh`)+Nx&hspud2*OaWLJ(NA%KjZgdI~IzdRroB+Zx| z!`lBJQDkt%8Y6vdkk!lnhA@Fzr%^U$Dt_nMy*;48qU0SEC=x<|3^0W2@Nkxi^yxJ> z3P<2kg52q4m-O*vYL>@hO-*;~dv)wKVwwNQ2{1nO4x`7mqJ^3s}_w=+F#VeX99MC7kkCl?diyBr69OlDXlhE+ny7 zWu}6}kxv$BrnCbrrgpg*(#yX!y@$)%wtV5jh1ne(HK#VyTxC}ivrXl_1#!c z$CHbQETsl2DvHAj?OtXs6t!z}xhy;%>8_Bcbj@A1K|pR$j)Ef>wPpm?=w=Sj5jjBt zO4`U%4>2{MDp-q-&9MvNa91ja5(0Cee1my~8a|q=p;l`+Mrt5_6$MJR z27C)I6w*MRFE*Q+z$F2$Y@`sqF0U4dVtcWsOdUr{9R;a_NLz_1tZ%I&fELd#n@gHF zd;oX@c!d#O4OHnIpJuPk4wHP6NKy>asq9wPG-Y3@ zqn$2$DrO@&3$rU9D_m|Df+v+E3z*=o9G#iWL7mrbY73?&{68`UcLoSgtwQ4m3c^rq zP3)D(?f3#cHXGD{xTh=S9bxv79uIvMU2|=#x4axj9svPgNDh<0M683-%doB`o zsSW##$~dLGzhE26^6rX+eb0uSrE*V6_lgzXJSuXtn4szgXBG2o8LOB}tyRo3npXu? zBuF65S3y$h=CV`7SRe&@l!+D*C(AoP(351J{yNJUJy#`JCqN{|&HIH4MOCQ008Id9 z$u~B(hXPAFelU+wP>0pVPG3h%oC3$`D2ld$LB%1q6+A`VVG(YQj_~!^xI3YjQAA7{usPP<5b5rTYqVt%@I2>9o)SaaKS$9VTjgUZhB@n4BjG zrBiOXcQCU^5XWQN%w(#>4G7?PZ-N~n*Gxx-gWQlB2(4PvK6QGyg4552c{M68J+;hW z|w$HCfR zTXoE!!5h@uCs>12+8GDs6zC4BuiXI6BrN~Z*F)N;PMH?zEq$Gse^B(~Ccr}5%fp;n z9?JPq!OE!^+F>!nEf*cZ3hUw>ChObL(g;SgkCUQvi=Vn~wvo52MQ4}|h&G-> z*wa4U)E7cjqw5xP0y&x)pcm7p7fb(n*;X?I7FfXLEMUV$U~JCI=e+SbZx}ad<0Xt= z+}O!Q59T6enkKtt= z#aJog(?|j-Vlk57QcWNw`esR_P+{4mWLOiGmi)z7$#0dG{6@VLW=nn+X2awG!#`5= zOGntEqoU8xz}sWk=*zX}Xs@1PF!z*ca}&9av|E=46))Yso6KfmW(~(>Tiq z4v~sda9M?&kqGqOQe6ZE-N<|bv=P)WzNw+)nh|>9#>@(-w922KDACllNBUVTO77Rf zG69j(ZJDozWg_&9jSwyE|?HbDMW+w@v=**N;IgCOjQ_9ZJ16V>0(RR@yJgd^;%Ad>4E^&{`)2G zHiX1-%rWJ#_~v{WrU0tO)Z`S!Od_69ClSsvFlkKM?=0)hxtTLJIdhZ)JLg zd;p!)gw#xH_xyRSGORUhcdPJe>@(Nk(Ca? zNSm2xeUI5&<nT!4OS`u{Kj$j6P#sxVM4zm~ak7cpiH~T}-0QHjDG1tKm(6;R;dawg& zYTHG61i>R)TRcg~P%U%nf{)=2k)=cE3>I40lyihQ4CA-X2y_ZJOi+?dWM%qR8!?8H zi6PD5R)z6O_jNNFj@tyNCxGipc`0MX`sX$C&D9bbK>n41SZHhLl)-Z)a`43Sa(TC!63{F|7h}*bS~hH;G(DA(5a`9`bbGuEZnS zy(WIC_8%IFiGV)L`sHuV+n!^AQSu;BQO1ZOO@E3^p#kTuiR1-?)LqbW&5i}Hi4{OY<(xV@_y!@$wn4yn5e`n73OdG3JytjHQ*ZGDczvCub18!}cF99|JU~}* z$ojQQmdc?%9@&y}a=}Tol4EMI(_cJJrDxIP^jhqQnjD6U1xL<`#ll&NoE1apa-OkT zvUU|-N37!^I~;|p5bG*YP5g-LT$9M?gA-DV_rRX!xrz)Rk1c#7reda$1D%zPIW{sB zueV5+;20D=RGQZZl|`yQJ7a5UVlC;F7$-}X9M=sx2Tn~zdXn0YKwM2vn&vSIl=QS2 zB+P+gp58SLgiTTy)%&nEkGJj9*-T?7XO`yv(WcJ>Ud2S*1*OUV)<^OyN|T?M)z&0R zr$0|~6HPjth&i&8g{}m%or}5Cl12ML7oet<{g-ifV_w$^t;evO>}Yz`%7RKmAEkIu zs)3tt_e9xN@P@bM1S~HD(@n)*z6KB+Oz&}9MF^*iG!ibRxDeG z8G(k{2>BgM)smU%=2Uq65i?MacE;u(LiJE)GE@&=a#k*1vSQg95Q!tT{y4?Z^Qu8} zBXgD>SZ&(8}NYV@x2{b|#PCp09i=5OP?hRq7C_Om1 zIhzCpTDoVCk# zVlUq?Uaj(>g|lB|$aWI;mI0pBq9IUt=9Dcq2Vd~5J;$8Cz`Tv zbe?U5eH#_mZ_}H$d76CP$dO)6eMp+=UfYP(aw3BMw#^$UIp~DjoI!Rdk%Jz&%|)5a zwqfaX&TYV*MS|$3+uR-tqRVdc9hNvAxH~1xP9NUpaf#?a%*;@;Pp{tQH;BoOm*pyp zttqwt9*H-P9?!&^W*rbag{nCE0XJZ$ylk^f94lL=>I0H=irG1x#E_#?>I*C;=r!D& znvHgZ4#dp^V5qVaM7ELThQ!o&&0P^Fx+<|=E?nq7=~^Jx3A!FPFU1O_7jp9ta%mGF zk{)9&9)q8{E~&vDX83QGskr(qiK8}>^ZqZ(#M}Zu=b@Gbp>mrJ&CQv#+Z`oEo|;nR zKWve&Z_Dajk*6%zA~XAhfTvq@^JR*=^H6sn@W)-^%Ilu4VDB>8*2Q0`>dL!QsBr^nG5aH zs`1UX7y7O^tSGHwvQaFULYAEOgcO4>1(lKvhotUAt`IwYLv$NZ|O&$I2oAWpe zS{s06W6T}f1k+$X?7znN=20QdQLjaXH1aPU-gi+CD>>+@s15Fr{{1{2B`pzY|Q4_ExwDugRz&K^ER|0^+ zp<#qD-R3b+kBn*VWx7M#CD}D8$(}^AD*sf8zdR-WnMnLaDe=!Qi=1HMjSA*!G{H2; zVT-#({U*dGW4^sE6Yf%Y?}E94B&-=J$C%Tp#+MTZVrxdInOAWDquQS(@xP44%Vxz~ ziFnWNl$y?so-X?f^_RZckP{iY(9Is7Jkxeqb5ohfI7`%*XlU?kQa{_(z?Txaj@9ee z##kiF!w3Um8Js8!q>Mt0cPJ-U3Va-e3=%l42&YpLp0eX*a^-Ylsln1XXGXDbCNJGg zGc;x2%wX%xC{{?ojEd3a7QHaGT#1SzC$i)qO(|l zBLS>v+lJW7n?cMIP7WqS(fBK5Qw=dIgy@sob%$-Xl_M(eFGx|1B|Ztp2u0_zO3KYm zCr(hPL_88`Ba8EF>by(s-t!llAzhIwMkb0ave>qT=)~;MYl{f3u8HmNweiia@!Lt` z_s+opn$4PLnz|3iUK)n6g>1c}?7S7lyl9JYJ{ZKvj*OeCfKhG+hSZ#tAEv_`VG^L0 zqI%dGZ+rfd*aVPtu#puOkQHqs-x+^D(!@o% z>=4%n0mb!!l#R`jCPT%6Ca=ojC=--1WI{g}n)T-9pyNNZne>Q|!VkJaic5e7^~qn5 zu1S&mwo7NBWYJDj)e{V1$%l+v(AZ~L@2Q4j6~dP*avb>@-S~}^x)y0&4ky%#44?!2 zscr^HFt{)ckd~BBRpiJ|54$fg`-W{sUX*VG?|u%}^gYlj;Rsjw@-oxHWB9y8$NbY4 zpMqAhH6U7zmrgDX(JGErI*E1WjY>|71U5MwDLNcknF|{v{k>77S+sNu>Ti(x*XIsW z_|Tm0yTiEH^rmgl-9nSPD9}sb;MbS_x8Z$On%JY0SdzpKLZX3HD7q*`cGV?hxZgG9 znDxEORxb%ww6vnpI`uY}EFFmvq}yiRwPgN9%OE|s2!7oi5x{vIoFL?$lDkA4B!B|U z871NiI%Wx&ksdw4MwiJA^DfCfT{Z?V5D}?473SNLOmzry;tQH+321WxY0=p4iXlWw zE71w5r&H?zb#984RHoV;P%R;WBRZ~o(Ah_NzdameF+rK$v)X>5F(*4nH5YTo0@Y)( z=h9Kr)D^}i=9oQ^p7BS9Vgp{4W$xkjp`i(dgR|Y9y{IkVppE?}4)rkFB)uR+h=utb zM;I!cMgy7%Bgag;=)l;#?%Wi6&d8s0_>4AeJIuE?_JW@Ls6wS|q4MnaWK$`Rj5J87 zf$*=11~o0Pr(FfiquO1SXwS!h0jQLF<~nl_*U=qwVHZze7oS8eB`o2FLOq&E2P^UR(q^)L9dRtc=(OOEzW-eKX_ z49LX6IJA$PA!3p$oG=tZjxnks>T=r%l&Li>?V_~r%8{X=xff)TRsI~6;xZRI1&aY3 zX+g?eg?&F18$tfy5tbQ3dB^3v-5IiOmO ziZw7Q>G0mm4C9DQL#5vw)D{nH3CTZimRHvcKq%1b{~hLX3h(Tt`j|iArGKb zJ1*k(Qt%Qkf21o5n}D1ctwFb1Y}(8QI0lR~QxJL^u6B^_)D`A&m}as8=;P`Fzc7TM zR!3TLVRbq_cca{`iqDG%hS2|&Gq8erhY|Y15TSotA^4n2aOL7jryN4hFU9D?h|!~R zp-fMJ|4gmLXwFU|S&OA6%eOA{btRh2*{sXk&f(AZ@aL}c7YQP}wPA+08>dPR$Fchv zHf&A6x_@P3!4xCIwr46GvSbLHVHq;?!7^ls2z?A)6Yz9tgbe~f}` z6S?4Uy@K7PXvmnUItWp5M z9M`Y`!;Odxt5BdNSQny_un@E&Cmg|lR>90B!)nY?aQzVC1aA&CpB!pOIN)VsZO{h<~TB%KW4DdXtY6n`l?k1Jn0QL5SRLDF#Q%Vm3fP?-~At#cAZDDPZle(ce=+;s_pwh^5mTNzfFQ&gy1I z+Lo4rR(P42o>)xC(8;htnI#bm!iY8(!AdwK>MdIlNu$dkGDp%7yj=0Ba#+40eD-!+ z?m;R+gI@N!20SD!yPL>EvMs*3ek1wMOfGa)C1`pIw^ySZ8X%?-ns2K47YIJO4c83!g(X3@GPzZyuLxo?CN zb1Q)%*aiH%;BaFIherhtfwMn>!!Mo48C)YNrf&1c2pxtD1H&a7&|LuIS@SJMg4lx> zT(Ml1zI<+;6#$EDgUn)+`7oABp@9=Y11BVDAY5?@%sU3NHSClrGQ@Aqz)KJJwPGV~ zjxMO5Ds>B@8`)uzjVyN1^kvSCtny}^COZ(66w*Mp`vsU?V2BypY~(LSU*?@LWc0t5V5r zdGyr44gg%#a%|r?$$c|M*`p?zRKTYQmspmAg~SCg6iINp#CDd8-X0>{I{|=z!NL$o zfS#u-FO$YLUG}8`hb&)#$Qo8C2moLq_u>Xa8Xiq+u*E1F!A%}+G2qnU<^fAK7-B9+ z_6r6s62P;!m`iE=_nr|(?{gb@j7&B|1X+yJCezO&Fec9fPGv>V;kH5g8QDhQ8|Vt- zp1xb!@;2kWsiciK7as8X0ZTuPF^-StZz74V0AS{YxSP*zq%+08Rpb&nxi3}`F-b3o zbqPU4i8e$w-ZMnqp&MIlCmO<|*>wx~&?j8e9?GHHt%2835vIa63F-t5P79S$iO)pA*

5;@zv zoi*pqWpmC$x~VSxfNFYM=?mJPLfQ7T#@jQ%^xSrkv{Hx{zT4*GUl1lrC&H`CtLqFo z-)FgMJT5vcOir0`8FQ>GRdrBM&;Uf&f<^&+b(dEU>j|FHg`O*54=cHLRCap@umay4 z+3oGaUtApY_$M@m5`xpdjF6$)kp_0Ic+|~-#R6Ur+AigT$LG-p5tsoB)LwH2wi2?< znugnftVl)_1IVZ)H$ot#&A3DO+}iFYIr}Q*w6GWw>6U?(1B$(#y{o1#vT8CqRr<%P zF^%1WDo&t74-5ftX2_CK0-PGGS;iDLMc|`0s!Q&J#4*<~=_DFXV!U985 zL_8WSSmIt8Q2mp1PcEKJ()nQM) zZ@zYXH&N?OjFDyH*iGU!F$uzunggZBCEfJcVSg3=)^<0Fb&bMm;Gn`$9OOpJdS$rf zPjtAeOhfmeN&`&D-NEHcgB-4o@Kl&aJY&o*VthIP?7?8SZ?KaE`qeKdKi3E`{vdMK z_|wd=YHW=Mk*C%aL9#F|hv^o=wY{$BEhxCn6prc5D|iQv^X9jD`;YVLR(ksuyaRIH zK{;y0ln7cV%e%U^}_UEEl99A3MN()0dAaK2>S65 zTlI+UX>>W*9ViSbbHlc>TLj#&N3rU9t`mEPRBEP5129v)MM86B4&rNZgHJWllrU+h zt}RFa4J~+g?q?-^a*j_jo_D&pG}go0Ba=rfN6EC~u2 z-pQ1cTzULNKd=v>q@bi1(<4p8onuGGKR+p8p2La?-eP^t&{t7k;tGZ}w9S)g4dktZ z*BeON%v<10>dgfkv8Nvn?B>Vz5!uu3`vc&Y^J*6&PD6OuaSkJHV1yn_69a}|@euEs zm?V)~ryLEoXq+52WxQM!L_)lNeBg{8BMtFO~2r|02)b@y8m$2FhO@sD*k1rR(fF&Q-MXsm$2H8Y0%E;(6H5oA z7>i`VrOa!p+EHOmt@4i)g2h`axoO}Fq@vB+#@zUc0vP$+1Q?w&I|L1mg$M+CVtz)F z(&CMWM<`T^3C^X9v@%g7FGZay%q6u)n6Q?s%6a=~rKDU4gx@4~Onmp@H+&ya0!)#o zteVo4Vaizhw5O@WvRh+%H!+j$deA#I1-;|$i9dJHqQ!X=j1rX%&P+uoFV37TB|cV> zQ{D>5x|*rmbq(bD+M@D8%FHNbtMaG#?c@*+6J`tR4VoHVajE06$p7&(>5T?Sr4QNEQ7&r~{ zOogzT7{seLf)OV`i3XDt4JMTxvo<6_9&6bjG0!-4)tJS6^=dD#ZEm1h3 zHN)E-1UkVU#z6oeb@@G>cj}?e;p!Vo_ZItihrX(OTU zL4rwISo+V&NH9?oM1DrnMnWS$BMGEs$r{CfzmC7P_J86ZO7(HK6lTz#+{@2fuQ=Q~U48)A;k337rkH{!VG5b+g9 zEVls-a65y=*wo`M8V6Gr^qoKTfD7MS8VF>f0fkZ+NDzj(48XTG0DxGu5aw1fxGqhQ z=(f5H07h-OiXyP2=zN7EpBlupDp$>);<^&_R7qStSW#FOvfwqjC+AxsY=<|1d^J-N z%&FRiOEZLh0S|GS`?u^RxrdfKkI`@mP zHv`C5(whf(KsDN%0TdGH&9y$Y9ozrMGWMb;*g9-|)Wb;z9!^eP2oC-#>KlZ6rv#kq zKX-@pH3tz&FDaNA1FJC#Xh^MS6^vakY)nYAc;XLUc(5a59O(>Y%Py_H)u-arocCYI z#(A6<0*G=O3QgkfSwcI6O3%fTit=bZsDu;wBwF22lUr+m@YJK{Q3%PXlbehbd}$lF zlJO)w>ejm0BWa)BK{f=A8@P{!e@h|dd?(vWMd#+Eqo9`bJzk!67u3TE>{%s~QlbIP zGt}z}a?rjR(l&CzT(aPznm?=YldeBW;-Qa)!%&FBz|BBIz>NW9IuID4UX`K|z9ixk z?69aKc&v>U_R30)k7PwrIIqG^)84QZZ!BaGd(a&wRTLPI0s_biI{%`YU8Qn*T2h=O zNELHs*A5)PGGftW8xe6>~WaBG@C?IYXeIud2-1;y^akVH4M)!?8EEOb zQ%(1prRTq*}f23Ji{l-$sr3mrzCwg`0PuX-}9QSySC3~SBdt|16B zW0w+Lz@+ENVXjc1Eik5YOL9&yFpZk*UBwJHG6TmHdqtF~rgONq3;R0gmrBe?zvs-9 zq+qBBT}Isk(mI=4K{ig`N)oVrW7+IG+7A(aW};WObL4oKteLO5lW3z7_Cmk4wT2?7 zshG|?P&C~tn~llP1)GYFcXXwKB7N0{rOPUuwtdSVR9$=2x>O5Soc3R~;O(Q2)`&FHP(yGqMyMv-RCwp+{PPMQO?FmEmQeWCwEw z<|uH>DFclg$we{0bxOaRrQ2-?P`D$ZLHR-7(U0~W{dC{azwbNxuVtfe=VaW(iC)BM zZd@V}@StE4RoO2G@={qw%qL#91qOIM1P?ko1Ikw07LpnnnOn=Yz&lXJI>CCgW)L>i zye?jIx#YD|5;eYVjYQ`*;5eW5oR)UN_!9BtJfe4GdgZjCpumcBN8hSD5INm3E#*krh*9uH@{M3TZ8 z(d-pf^i$+2lqxDR`mosI4HM&=yl=6K&C(%qcWaTSV6vv)Gm?dhup~Us(Jj`98!N zKNp4h%QT7x;8j!zt*$E2i;I7;qZU~mIM*%(+C7RS94Shmhxyn3FS zmJLb{3c-xI2mYT3UBQw&Se|n}1Azt_2QN^!N}=2c6p#fp^T+FOl?{1r40EO)5-i0+Cyj5WSAgW{ke{*e=5Sqpl{G$(z{&<`>t*U8 zjNJ#v#uItmdC--@Nb{83&E|QdU;LpccBCF`w%#gvhNV%dS`R#9JG+xC?U*TP4B8 z!h9?Ce^!sRred4k8~4)sR($)m|cf~M5wy~(oTOqsOAu|;x&g@N=^39+W zT>O(LB}!$r6>pWa;^83wn3DYETJg`4Ql61g>}{s7z9MaeBb*EjP{aeEekVrbbyK1@ z{|n2>2eWUE>{1Tc0xR#9b>SAbNOo)d09Rgj057_#CTxcz`<3YSq~HC>`cj)?DLHCW z99yHqIel-YWH8`1J89SO1tEfSTl3BGUkhy-8bT_*{YO9(e`l#^t1P5d%R!$=u&F$m zsJtchfA3i#;wA(3lD2qt=3|&)xM4T4m0!uyPG^mff6stTG3yHUMJF)!Do$v*(B8|e z2q*C88FzCeE^=5y=I&QDE@t#25#M$vuo|G3Apyt4Z+Z_YHVg=mocO#JI$4VGs9y%T zC)3~rWl&H@ExM%0XH)9Bh7J64;42KmORkl$ye28<){t}@k~ON_ClY$0yK}3*mQXaQ zEwTtob*IZz6rkd64y*<7Lyi}P(GX>pL|?;bwT6nXA*5E7de$p?^hKc=i;J`U-wq3m zM?6q2;wR-IaNy00J@S={ zz9EdJ7%{o^{#xJB_iJ>i(c|Osh#f|82Q%tz(b2NhZSY%^{slkIXSX{44vt%dl9|A> zV}f#~P{5FamX-Kagmh3;5_w(Kzsw`xWU?Oq7;dM5DKTf_2w@+-CsEu&1JV+1?gRyc z*hhIVQ4qJxZ$sjd=3z;!*Xw@yV=|8-MV&W_wZw{gVI@6H&(aGAw8C%U;-?^$*rb@d zmzJbDYg|dHKYvu4HG_u|=s3C|;a}^eD&&DcQ~GtI_6xFoGRbR51tF{|aSyH_hk`YQes?g>1PufKRM2`G9LanXSFZEwD{0 zaD;UytV}413V&gZ9fyl$5LRcdf`%$%{#C(U9PXV|(0)(%TGGuf_EUDK=FZg=ubwL# z9q8~{WQ4z~8$pY)ayr9&V;v5nQZP7GlH3tYW|pN%?gP?GlG!YdW5;bL6g6TlF;Vha zr_jk}{4A{**QPY%iFh+EPHDz-18BzS>CkvpnsH?u8lOsO#%u9ryqS{Z1eYWY8dZ}8 z8ZV9rXN3%kSR0sg*HET+t{f;D;s)gf-7ncesh6p7-g+qN=&45s<(XJBG|A;?29j`& z=_!>V{&p-lGCZgv^hNu|5@6i_I1NlH#yLkVQH%rDCNb_8$<8UpU5(BW(27pFAixp*_qPHD!=18ByT z>CO0MS~KjXG&cWEfT!*VG+s$*=^3u2Y0$73w<*~S#ke;F!ynrjD9&H1I({2^J*J?YilHHd27l2w~v40`jHRwLSSp+VOtt5J-24AsEI z3_y$1ats}TMoW?aQGOe(Mv>t2@O+5107w9x5f{n8*|iM!55!#4j&v_V7<1BTq3Wfsf=e^oBvQ9UD$&(uM zX>wIC#sOEA3lCyR?_Y?t?7Wng@#gY)%g#<|*~_kFSJ92G;~AydS@YBi%kSM8LJgiAfsf$XH9VZu)W zW?A!3*RpR0kwL4!194?~%U**fkt1qpq7T;}g4Fj%kV?p$2#d_ufK;`RPLoG}BuK(N z3683M@nf3zCIz@sgb{)XkF0^MDdZ>MPbrtdG?XHK7ZedArk_JCFfoxNe+`nb7F=BN z8C%Ok(OTsCadR7L8HQS*hvE4-)~H(k?uK zOhFf_k%`O&Z!R{YWcOxbQt12bq0GFUq`GINg;ltLdl21p8@RW0ywOU|Fx{EGwZ?AX zu(06BB4#T03)-uHjK-)Xc5(8s~*4v zlWk>6t8Ptc)x-U^>iWp+cr0ah+*mR@VkF5Do15L_c#b;1#FV~xrJd4emQIepxQX*b zGOp5G%Zam6w|9YOf0@!3SjU){ID)5N4a5Z;K%FfQtOTfLLwLBos7|P6<1!V;lip^XB0;?uS8~qbZf;GD+A5z061O}6O;Wt%RuY}130o<-QEFQaq7quR>^hA;Cb9w%~9 z?)&T>J(q)p(JDMmFOAO3Hr03`q$(s)a;4`nl4M{w}?vpD*p`Z?&UX`*BMfRRg2U`$3a1>It^% zkpzu-E``QitTe`vGAvQP8N0EtKy#XBan6r>5JiHsnan#JD4nyh4f`N zTkcPpEnn+A~sT?pR*o)nM^sA%Oj- zv1BwtpKN^H+`kfqfh7fJthF=xhLp}d>N@w+AkwZk#@x6{XZvnRp6l8YPI}v%Ssvx2 z-wdG4hUyeM;Rw!consHhsH0Bp+ejUG_X@TEKy{hnqb8zj6NE}qEzu(;KAl@fK<@N| zajoIj7n?_|`JDz3a&v2m55alV&?mHuRGIrB8`i@bGAdm!k)ua#B9S&?^K;z6kh@&! z zYD-+r#$_<_o^8L?AA7YwxOW{q@j#$%m9AgG`d$fL%8S&dHd2>DR^U9qhM^ZyZKt&oB1<+*Zhjj{EJxT zYi#CE^_}^3oB7dL<{NG1O?_uR(I&%+@+g*?qChU$>#J_MQ1N zHW_s3k(%$ep?~Z<^94599kI;!+fX}z<(hq|P4=Z&=7(+QGkw?W2IYoW=ErR2C(2~b zj&|FzHJotwyNl0YoZHYal7=u!-%g}aSd{+h<|}JnJO)q#!wwBG_)}OhtM2h7oQ(!X z!_!TXNQ|ZH>W$bhE%sn1%vrXJZ~j{)S1_XFsp;JjXbll~LPxJIeII!deBm_7fwGU3 zV>4|{LJpqcY8!77kD_PIna8RY1oQ|lUTJ=@oYS!2dMbR#SppETeWZ~aZ6Imw7k}#w zTC{OvxIG-P_i$>XTQ+O4-5RT=Tc68nxZ~Prz1naPr{p4LJK-9tt8Da|#8TTGtjVgG z{yS0YRPt+0;-MYmAs5)w+7gaT$tO<`tibTXrVnmZo5|YX+!d}T1|@_cTwrP0dML{J zkwsJ72xHCfcy^BIgD{1#J@0+#@BrUdQ7e zio``mM)HXzO=Hu6i2-?(t-Q<%>N;S{OD!)awZ8LZ-s%yS)~B?JG7tSQb2GJCc`0)q=yy035rr|Y>o|gD|(4dUZc(qdn(^Bm#D*^O|ag?ApEegQ^9Gwfk zDB#XDwUHM=G8O{UNqTkEBm2e|N5zO@dE;ekS&cYuF{}NV|JFCoch#G7MGN!_=zg8~ z>c-s6DN|-f|IG;nBl|7`NdINI-wq&Ce0kal>iL!<-D0KQ z%2IFM(xpDjQt#c;r4CwB;STQ^xTAm_kT%m(oU z;qtrklJCCDoyNvq9F#j~z@~#hT6c4_g-DtTc zxh5vx0cNEGU@5_Ri}QR_hLgnw5Gi~B&svky1s}kLAJ&yv`{C)v=%E>W91$`CD56!8 z)zjBz2JZDk%kaC|hOfPCJdCqAFR;)bmlQf^aK%e)T!~Vj+$?a36*+EG#vKgGSCYvA zkdDkbz(667bEuJR!ADu!pCiPiopT9$Q0(2}Y+%2muH6WkaKWYr18myt=@bXgd2H~e zA-Vw01z(A)t1Mp$M`{tiG7X;;K!f2cQ`kzqx|Mt-j>*C$I*vC)nMp8p1bMrlvtVqq z#ma>Q{&ezrN9N{)7MIg{(4#+CG{WiLe&FuLrDWFW;^Q{!OIhlJ7EU-}z#G0w_K)ea zE`X8>?qqX`S*J!#^rQ&vs%>E}599TS+C2}OMfbZN{)N!hd<4%PU~|3_;MumelO6qZ zHc15oT-akGg$W1#M+y_@;(z^8cOJ+dstph9L{HpW`F+fRfjxAqmjuKl3vzeB>VuQ+ z3?TfE3LIiLa-kh^U3O?(w!bE!pbJU33=|>W zf>j6)hSP^JLTUIB4c$&JnVAeURX?(m#d4Xx66G46FujK<94&z5i{mpUY2(gS8p1#9 z&;*&!Xr_T5Q681=6!8ELA5-lH$58dS*LgbTd3}2*fDv-|Ckv)#%Kb1$k~{Q!Mq9Nv zcH!!1#9a~AEW&nP?}`Y{FP=E16G$$MaMjYFch;%PoYW6y%nPaFn<5JyCc=oo_G3Hk zo97(-@M<;c|1)5#hT+znQ1Bt$_=9aGPeJ$DOjsSF6!DYI7SiHQKH$5x+()d1Y$?S9 zuBBarZRr~p;B!%-J8lKkM5C>`pEx<&a>R3GH1$vy4lff3gf1Pv?v3~G91{yV+mm03 zL=^5&D5~#bzi;3GOLS}#?@NcH7OW^x!iLq;enEX`i*=ED!J5pW8>SwPkaRlnDdFx7 z`8Mbj!0isfSv6v<8P+A(1QezSgiJ5k^)bq`Tz zZWRC9k7K6So5fg`XHS_DqRt(Mfl&Nvlv}zZ17g99yU0Kp0w9BCJghY14$zD)G$k?u ztknYe?ExIPz|KMh=UMmWv|&^^)1;IR1FUdS#udMYKg5RE6v`4@t5QhJxU>OaB zSTT7PR#d%C?ZcpV?OvhiE#AYMh6&1R-kKXkJXjiKwbw{u4vDe8!QvZXgIDDum$BY) zIG}%`g}#yv;Hu1DAQ0z&$y5N0C!(ed+)d3zf42etI}+(va_i@>6w3`L@loub~Q1mpG*dG87A&z)9^^jRfh z%m>$xLEkv_;ZUVhXgVi4DJC2-0x3Nl%Epw!TknP)!yt792RFXz3x-S}*DZP)-3jk8 z9Ob+X3a@g|B;hxx1{2D4t+sBM_1QM?dS)&RKvS^5JbpyPvD=Y3q&1erx%G>~!RV1( zr8?~5W^(ES)t1X5Cv=3#iULF?=VHcL%lQY|g(ZgI9fBAxVnbwgqz6=7_fYPGzVg)H z8Q-MfJKEJTaFthOa8{FqA?iySPI`6jpxz!(Jl3ZkW`snjD>m#W0V7QLDg zDtyz_pO)A_So4 zGi4W8Kguijq3i;EBsq40myne0KJ01x?HyonCl(0TVPFt5v1PzZSmH|zM~&d;H%F1= zIj6W|kwZh{qYlj2B545Q@j1PBnzUV)fhkFR%`|s~^x=Uun4)K*FPzZtf+-qK-F~Jh zFaFUf3U`F^>upa_7Rh~Jzhj}Zlx#nAggPgwDwYp2hh;vboo<2>L#Tmt6Sd1ZJKVw( zmDFWxOjNjb>=#a$G7ua5yJie#Lw&AkK+_@6jLLF(Zy*&5)~SO4LttAwhzI~mYSyd^ z6$nk)g^J{xi%}kLx!$=MKF{U}7No9Ux=4jHAh~F{Z_EsoJD(Fk+k;<;waahmcc}q* z2ELX}NUUXbG<3yvD0T1vp4cT`83@e+=;?LwZx?zkn3{TTYYch;6iD-1;!F6zz%XyX zOFF#C%JAEYxHF*uKnKQMBvozz!*EO5WI-AaFt&&ESP<|{3qtJs9HX>vUkC^+NU$Gh z*M^c_v9Ua+LF|cgRC>cST=$S6;tD-J@v}uj^9;?OA~*2hqONMJzGNPjgG*{Z&@S_6 z30L(haAn++kiF5jdetSHQ|?>y&1XMRiV}@Bd2%ooOncoAn4~5v9$R>JNe~G6pYL?xkoQSpGlN?2?$8B z%99d&nX;N@HTlv6M=z$=Q6?V~3U)cD9jv|r1+`MeLxx0%6jyk1pnP+y!ZB4+&HL=j zqckTe25V)mEG8osSNsCbWP)+AfKl9hFDelDqttV$5436Y*PBbj_EJqBjNmB z-3o?c)iZc>p+Tm5i6roXNL)U#=e$CXJd|!mzgRBfTje6oZ?H%p)Q9Kv6b>T9z`;oh zF|ba7T)-|zk%vU0w%BH@EH0 z>h3b1;T^Kup^=|3Q#CQ8qf6m zF#y7Rl`)LP7sQcG?UFDY>GvQUM8$%E@Fj?}bFKIS6M+DBHJ*~yg{2UCfVg&;r{D_< zm)vcm5)hiKktVx4ZdzjihfyTrAcw`Kp9n#u!6?bFCBLGrXccA^UKYidZmXh~9h$IS zihJM{0N0CfrjTo}V}u*YaBm7aAAv3|=oEP71+mEwQ;<#yMF8R=E1|?>J49?O(^KIO z;uIdyJYgM>`0I^|#N1?&bXjvdBv&y8FP2rj;mDxx;RhU(S&V9v)rTyQlFGS4D)%H; z0OZwzNVCZ$$R|ZNeSK1_$xZ)W%nJvnvNECpEiBmcHIz*w{(v4CIICCD-ZauH__;U! zA`43MEyx(OT}r~IZ+^Qx9B|j77D`L%%yPP(|31Xha9tN+I!{;+*q$5M=0U|kCXE6< zee1eRt$O-*8wZ2E*dYC?gR!gGCC31B0PfdDAKB@)Mb6k#bp=XPhzP;ptLU043(y

!DOr=IY>O2}qQ&xwNP$FjaxXgjBQ^8oD5!i>O^Pim!8wCtjlz8p#e!jEMWSuP zyTz^}dVPnrAVqcD@>1}GUn6qRHrAPsQZ5P#CX(6sR`bi&hpuq?u|8wzj(|m?NRy0# zPc3|fT}DE3Tbx*7DmsIOb0o9@_b#*{nnXv5C5KR?q|M%J{3KQAMnWanhv4$pb`LxI zo;|$1@?MVOe7#wVG)(6;S29a#IqmaW?4I~}0K9+7Y#*)kk}Fxf)+PWWvZNlwvG@~@ z$2AB^7rL0=l0U5hcp&yZnKhm^LdgiA4*O@aLmWO!9+Z2mg=&curq){TkaLc(gyx8@ zkV{x#nditZY-TbDBLS_79Z}*GCIytmkSSAgZMS*YezD;sxArIJ8vr&6)JkTb>4CNguu>w4<%Ro7@(FyC2f@%(fuZ9F zI*EFXzdIKi%sSHFf;U>Ia%fZ~8|@d9?Q5FHxvP{%@xrl-Md1%TMoo2tHv#SAu%fNl zFUaK{)modZ8#4dkVh){1@WAKTbu1q+uJ25}4_T9%qFX+7iSi0w2ir{qodtoWXjCCV z?p!SR2a|tU!EtIDdkQ*)lFiAm_Ia|rIEdSA2ukqGLJpm|6>!In`&YOP4x`JRlH5*> zA_!ZQIRy7V%7OJ!P)aV42}hNItzak>4;ecVG3vl@dT=1MtMO-w+(*lM+RETa)*i2jskctD2q7YTs9^Q(>E<*E&y&^%uD`Oag%XE0z5q}Pm z7NZ@Wnbid#fdJt$MK0$dyrsz<*cEqoQw(Ku26Fd8{90zi<&WILsKr95r45$ zKE#m4^A6NGi#Bq)J8aOeTJRX$tYZq$w9!#hx6-?dVpKUNvj>f4dJt2HzVhtXK|)y3 zb(uT1|5$#j{C!DeOCwO(2s`+eU#p8~>ZKoF+D1uy*pEehcf%>9aJ41iBJJ8&3I0Ux z?m?j9O%XW)76)>`*`!{rZfA zo+V-fIj)Pee}#t!Oj@oFlO$R_l)6l39i^G>5JwX((*wBOfHU3mr%RsSiEj&+=OUX& zU3<7Zk0$cm9&6kWZR6Cjq04gtyvIfB`9dtu&uyNkHI#>1(V?pnc`nh|oQ?jC&Gbkt z(=D1QJKV7hE6H;_8;*_g*HnV9SbfSBUYWeS{%vX zWFgiNWEp8r6)OhUu{V#y{u%&8g1T84EFI)W)Rr)a0#G{u*qTBrt}1FuLO2j3 zA-TueK!ZqbF|ZcSXs38)Xo2n7lLtd#n?;kpTQ*`75tj#_i9P{4(!rkuvkp)6tfQVcDjCfR?&*|6?t6dwW(pTD$d4b!oxN3QKKr8O%%0Bt{AGtDNlL-_;5w zd6g!y#|cd!f#N2Kiz|bOw|G0QwN1y7pgjL zbjh#Ka8Y(5D78t;rEL+pC6vol_9ulAnxRFu^{kSUL|UkLoykXh!Yn=#{rc5zTdrSh zhxAL?NJtbs|H!ak)ICbSRP$D*U)GS7U9>-W#B?zIdWikHY4^?Qm(mUyFL!g7g4*^= z2ckzWXQ4Q8aBU3SKj)4@8($bu8`bVV#I0cHqbL;ty=|gh86!}XDDN5&>yf7XwsB0Eiqny*9LD9adK@ z;0coEswb&cYH7sxt-FQRMmrue1l+a8|YOwMl0T0h2S4;Jj1%-<0f|Yd0B(7qQ7|VYWtVzSC4@Kz>{<;yiomXTYr~7K?5jN+)6eM?KG$ zLgW`^6#S)D?+zi0f9Fyc7~pTQNNqU9)Lnkb*me)wsA zSaFk-4vOF^vZb?5sI6INyrSV#AUFL2ZudZT=+c>PaJj4e>F;1J15mJySXNvQXKJ?? z3Tuj#9?nFdwo!ng10V(H0K7LnmpN}^A=~Jvy%6qSw&;lCm`*!}tBzM`euPU@oRs}& zf=vecUiA=ZG;5%ya{@#LxFDHqukjZ!Cj#f@K-U5O(Pu}KLTYV3tP#)!Masy5%=2JM zBnS%BDrl6VLGU2n@zv0MYf=zZcn93V!|P2@_!=)3HQ1EcqF7`?a@ zqi>%4ABxc@zK3fSF6agl3M-p!4|z-O|6raJ?yFieh!v%X-l>3-xEYuYCT7XAJE2U7 zSoHcqh!$CZ%5~Ha2EUanPwMK0iu`nE=Eth=r6y69Lhb@bffMxZRsEP)_5+oHEcm7k zO@pc{umWf#*K*x1>@6aa+l>3C>-econgS(~%N?N{P{|O#cq|Wg%3+bx*sqo=@+nv3 zD3k%Wut7^kvL*MXWE;(hM^hrCqF+r*Hjz|PmQw>uC#w5FOrQcS^8vUFEubxSRn5?P z#$bCwrMf#~CxY}=X!>Wp{ov62Mw#eEf!3~4z5Zq-x(3HB8rtIgMqK0(}ZqM5%1=@oN4Q)6C z)F&3oVELWpQ78?*bUSDJ`8GklJwbhTO0&i?;`JRA)J1p1o_jbe|FsfZJ+&-n_DDG3 zMq9M0+l!=Rh(8NjacCWsrc90HfnsQ`P!XO6^IHC5`@i=%`W5#xMm>u*%ABS`;FtvDU!Utq*W=M|& zXI?6qg(P`94S)b%o-(Y8hECF-B!CioOSx>1mY;Z29XeJ+Z57PG;3w3iLbgE&cIJgY5_9RPDL@Z(RZ*gR`)wa_f9@mh^*-WGo?5=Xv-*hp zyvD_)K?3L-BnH<$HIUErAK+h}v#kvNRPmSmspT*EGnBvNPd$HGlknJzDy4serQ;4_ zD*K`U`uwq&*ylJ5(5sKR?31PNA5ifb-J4|3#^Up!m0+s}3ajMdvBU4W%@nc*8eBas zPu&KC^KzyTq6zTWE}he}utW%Ta6-*0bvSz+@qk6L`zeidJBb-(V0Jr<>(v0u&8x)( z+OI1jH@F{7q&|Q16u1%1rPE2p6rDow-dP21pxBd%@>|}uOn1%@K0;)26fU?Y-Q}@B zzTqaV>JLp=Ad47Dvzj81hMYe!2sxA?J48bkGGtOTWFLmKMMK`tkUgRy-=JG~b8iKP z&%7V|v+q{qGN@Z5JZMM8+<}40fW$|z`S%=`Tk@6>rxa25slBe@e`7Nh>`Ow#25kB5^MIJv+RMKo>27wSYnlfjkfSj=}QH1?Gk#8DFC91s%k(syE4 z@&}~kj=mGSlIej;<~hUxKBryDWCKhy$pQLKv#cCV5WdKwW{#FRhjeFrAr|@Nq~#&|;}HXbHx7M6oNjml@ZFGz&xk%j9S;^eEZxQ?k?svuw>-QB=L zf*f@)SGqY+=`gJMc#yM`IxL3i0?f5ck+jX@c^bGulEt(w-GbrmQ^tIldeqaSDB4c=-M6En zC;{+(+kLto3cEj}Nf1iFn1{{?z2aFhWg_&ftr2~~3l(<)qkt@+>6?V6y$PCDPeb|7 zK;ctw{z7kV@*7awt$=9(oWz1dfdX1eI{pZAfJ+b44cWxC*3N#iGT33zmYm~283dus zZxpc~TV_rHs7nXwhK;$PoT<_YtZ9&U@F)PXeoJb<2Sgm3j(Ec^lPEAaSjA&4K1(A0 ziWVD#>ziE%NeIw?g8P#IcYv-!5PudLE&)R#Y@mX*Ri?dV|5Ab+=O&vVHvSka;*EYg zQ3<_Rj8Ww3fd*Z_F?Si1^8j>X4&;X!fQwY$MPSIE76vpl#lcD%nv%Vv`iN9Tg4#qu zPav~Nl0o1-n$t6HF%*?!HEM{!MQJh)DkLxfQ(-L*;iCCCIlx&ci=zw`G*lT3 zdP0D6{X1W8`$o*it2#Izxnl5SARK)ebyK6(lDeUI51@udC!L30gp)opH>n0>*RaO# z%(vQTG;*IXTVg7GbF9Wy0!5Ids!LK<=@%?*m=8iQ#tqdk93|pcy?#N`Cn}45#SMhD ztKh7!nBdISh{rsNeoDUKOz9BU6D))Zvv`?6vU)sWx7yI5?)~A0!Dt5RR_ymP9~BW~tIIPy~L}>K7;i zztDRY2a3S2di?@L5N!V_sLUK7qY&FZRodM^P%L$|CM5G%7szpVKySr}S(7+8wLhi-sV@c>N4NHH+As)C2>SQs}g zaGM_u8{jPM!YqAXa+WUUQu{S`lsBBDIzRuvTrY1w0U-I41<5dsTtA&`?*gSzArt9A1zjYy5HYuCwo< z_HBIPiJUvxug{(53bIc$ff<+Z0&$A<0wF7Dn=nEtd&~a%7;HWL_YA1L32D>Sfh&r} zcf*izee?b6`|F9_bXu7z42xw$D_13ROEB;)EI9YMx`l<48kNw>CQoiopuCn$IktQn z2c~**IZk;lH>NnYjyw=iMO2+KG2XIZc2hjqg#$rLMjkbObO2k=8VFJWF3=AAHG9iP zYyuFL2lNL@CgN6ge=xyn!I^W?b7}eg*2l*}$eYsUG+V%(M2l5^SHpgqGC&XB)>H~} zkelg;4S1&ObeB2LKh|7Ewl5hF&}hF?CO%q&^GPB&{=e*<34GjFb?;~N_l#s)-XeL4 zlh~5&*v?{YcASLBab(#}WLvf(DT$r59TaP1i^#I8#c_C)urGzOQ)pRB*p~tUTFP2p z*$S`hOWKB|g#u-1fl{Eaw7l={ocsUJe?}uEc7T>opCOw6a{qTZ_w4uFb8+ZsfP^c) z>%jnGALn8F;>et~;Pol9R2v?;k8FHkE3NXQD}IF^2_kROy5apG=-KeYhy{eHkETxVc6G9Yc0SWGJd6V2_+PF@m~ zzKqEwKDjo(OCPmrHT9UMq^r#r^e9^G6;R)@tmj(GHd7uKqgBi*WYh~0E#ki=TJ)$` zb@)jbMcWE>W}kP41G@amdL%%;XI9Af%?9}k!qfr!d1p&Q4e(n{yOygNF|3d z3WpS85(peBM*Ri(I|73iOHvT{Zv|5L0PD21QRm?YEB44d=ZeD8>p*EJC3+0YpMiA9 zUg@Mm{&`qJ{){!+cH2I!Vb$hOTiaUBW6#!nX1Rk*6?mfJZPENUfGE{hnu#WbN@uJz-xrj<()O-ok5RIFAhoA}!_O)=N|m+@ z*e)V1>n3{#Dva1y&)%4hVo3Haq;61%XKogPnatdq^$@lNz0{-EXKsG8G;6_N%3cZs zW=S=K3C|KGypah|VEHJl2Zvcm2k%i0+@Vlen67&}cu*eeY;n7m>RO-LU3uVf_fD1NYc3pa)AxrdH)X!?wdE40~LYc!1?~ko;;;og|ro!lcyZl4y zjeyeOi{^M?XUOv%ZV8ql!w zv^+S6r=Z3zggxRw4++lsYx4@Rh}NWnf0ha^INFBN!9OI#WXq@J2JxWG@?f3=@|o_0 zkjp3F#UVawM}w9n?@(++aPi8WF9~f?Ud^WY*J9V^4tlh7)*`Rs;H+6DikUqqBNZZ! z4p$B90Y(jS?x(QIqDSN=z436RLH?~$Z*3x-%gZQ^NyX{D-h+9z(tX9m*p5I-*ddD>gPlqga3vMj9fh=}9MB*5qH9AILMa1z0JbCWjWr#w5 zVybjWW^pw{B&m2sM3T{GlZ~zBH+T)UY0T!pFspjE& zZMBLs0}<}gn$A4S@1oW5BI4OVC>?bJ=H8nuNw%I#ZJRvmMyEqbQK%BT_J{G};NNFt zsXd?emPQu_XK71KeHrupK{}KT8bFw6Z1O|l0%cNXp!bXizzD{a#`oVW3y-ll|EeJ~ zP=LkbRil8LW>CP#LoD0>FgfubVc5T1Iq{MZOm)_B!dT`*krR8%$p2jAaWy$%@t{x} zD{M)SDC=r-NQquaiEC#_iPE`&zYbF3{oyD*WZM6i5|XBP6aK%Hc*s)Xqahm4)|LNz zONo2pD85{;tyrV`gr&0Nf(Nlx9ebohyvQZJ2tSpRRgIlVU`H!zjhxcGAX80*by)9_ zs%(y{CpNTFP5WH6=GSW>vh_iT(%5zkt&O(SBzbPlPxkMXwQDDZtplFJ;PSo3w#x^2 zYcfFGH}xD^SvkOaLxfyw8oujM{?2WPM=OW;_zH3fq)U_3X>d|HJfj*`A@VI zl>{Jo{tzKk#ojHC20H$;i+b)q>D@uL zaV@_i{s_2ii1$0j`#!x>w%$Esk^3znP>z#z`KQi7K#jSG#a#_z6t1CekpNSMsK`s3 z7}-R*S{t1%T$fwDCAVq~w!ma3hb@orc8Eu7bF0?Mh9k6JClT4|8QCDTP3&?k4xB0U z(iigD8|)YdoK{O^_HD3z#bJ}=+t`SQarN!e7G~-!`su~zTIWk_bKlo6d>kxq!}!TY zU(8ez^`9=&Y{6n;)DRAeb+EfxnaX_P$%@ygfyA}lsmc~q*7Z5B%V#{<7q~G1)N3kt zgO}gM`CjAJaxBz)?@x)EmZsZ#9Mtrr^VD~I3zfOD0SX?hoBQ)%iIe@tesTdXy^mFKi(w|iprba7&`^}q03rPNs;sS}j^K#m%%;-#LZ zPFo6Vdk^AVrA+Arr8fu95==rIVtKFmp~Zont0tLYmgC!Hw|Kst|JnjuKCUmgcc-ks zWO}Y!zg|aG>Tsic^inZvc39&kh`u(-K6<7O8Bv~~;Xlu&7wUnvIBPfbmVR`k`|(w6 zXAb@Nqp4Z?@mIki@}Qw{_WgK8svln|^&^p)Mky~2X8(ig$4q!ICzaFieaY1@{AW)m z!!K|4D@n61%2L=6vUmg}s2KM0Ty$4z%0Cd=vN`|rxUq^Ue{t|RG#lQPVP2`NnL}ei zGdh!M>$$0M{nIQ>-4~i#2fFgTI6WeU6^ge$$*{4MJko&wZ?hJEUbW(X7_9D@wO1|v z?z1a?pAO5CkJ`g1x{N&Q*g&mtia0pv+<$Kj^_2hC_X8cJDYgUAUdn-Jb_f@lltG~p z4p(C7@TVLFrl;@sr#c{PN%W`oFdKcW-j3R$*#8d2Ugw9Lg%hj3z#(V)`1}6UKYpw| z%tnuyAAkIuQ0$(v6VmPvPrp6)$A1utK})G_e=R)y+T0(%JQRC=*~i}wPw$`mP`{EkrUuPt4FJXNora%ew$?y34=n5xf|ef*~I z@$b(4@xO(SKVJ6n+r!6?pZnv-gkm2o`}p1A>CgP>Y#8?BQ0(iq>3M$986Wc-<_6e( z0bpM$`}h^%<5$l8@mIpfUnu+db>ZWe%<^%~nlc~!$34uT`gv#N$IYeBSE-Yx_2sbq z-VD1oT@|to=Ff~|j3yHNs4TOKq%Kv>zi8`09qV<{yi4$J6EGKxju)IJ{4{>?e^M{r z&I>WtyysxNA};fvsWMMIZ8b(eV8;;^GNJkCnFVFk;INbA@Id3i&xusTtP0tmvM%K7 zIGf)zw5-lIhgEoze%HP^NiPybmeWHS>5nO%4Kw7tkqO|pSWd`ZT*tZ&U-$Gw^L&17Ux zF0YL*O9flwN3C{Xw0)Dh^t^Av8KMbt(zO^ua#=djZA(z0YIoB1# zrUWi8l~iL#$Qx7=P^{-)?&=sEf6KCWOzf|kaN4X~JO6|yE8P@;;lIsxmZYHlQ0`{{ z@t@%ihET4NHZ-hiP2A&(j?8^MOEH5jOsHIFz_TLvT;z^ck z#Ytx8Gy(@Ej%Ma8&@+BC^UFVdcY1PYVk(a7Oj(5f{CMUUVkwr{niEHl`We0%1Vfgi z;a5E#A@q-u?UFyf13;%X5e&(BCHODMnnn;cY4PMn$q@psa3%R|#hLIRDS;ee%N369 zpJ!BKqVsy_a2!JXV1MiF80(T2``)0%e#KRhpv7|Dttq0PnYT8EpjnwAlCClNHgA%RYWu`1sv(fBcc~@jsP) z{M_*I+vfiGli}lUlzsf7@bMew{`iaG<3B9}*vA6EzL(bMW&-T_q1YG7T7E-l`9*WL z{LRpEP<8{f-xfZ8?kpcC9)%l(mG{S|4<~|X1xUL(y5H3;vBjSF{M$LgCNfMZjJB?lZ2^NMh*SThV-cd%$&u-V4a4BQ$@oze}Qb+>LJ?iA@|I z-Y*eK)ZDVlD!r&#+ZC2XuhGUgim(S?MF?QSojS`^OY(NsD^|iA(DN2=q3Tx=5KGN} zpJBu+&E{JYy^!W=8p`z4PdeaS8;G@pSbM0{4$7a;VCw&b06cXMX3xQH_|Iw2Z#lq1OSHiC44y-Jn zKG(N&__})qcRvB@d4ZSZ|G>zVbxaDw?MAM z)u%Ou`4^Obp-(o&4YbxQ1eqrmXa=jE0j(MA9UUGXE8aOYQJicYJU%)xT-qpHy zXln0d>*P7j@!VeIQJ?$P@#39hqqk==dq>BLg&T&(hsQ?8kNK>Qj!zYj6(?NoCi^$c z$2&Y+90?Pg_6QH37~<)?3O{j`O>q)`CaryUXYL zZho`YNbKu170YmT5DMx=Lxau{u@&NLZ8c|++EV1BXYE^>kCt~DhAz$TKO#;@Laaxi zk$8qmOS!iXCf;g#iY#R+Tc@8Ep88G&aB?xxMOp(}=Cv=Ty!I|ER-L(JO6aK=zy0`3 z{S1`zRZd&QTKzL>(jEueCZk#I+8yFl`zrEWeHmRSN2EOCq5J!7ICR4Mk{S=0*3|YY zZ-Od0&+?%UM_V*jc$FI6W?jS7f=%ma=(p$blh$}OO%_O$6Vdwx}bytn*>9MVSib&WW5S6Df{0=!}d zbqE32mmRKcq;Fk(v2g2MrWn+a&hi)EMeAKwv9Ao?`f(P$6EQ{q8hY1eyw%{>X%r-i zL7c((q+2MG*JAvA31lA7l14ob4ZHS8!wygoKu~-fr>uRre}9A2Zobvh@0C^;M^gx^ zv@=tF6%0SCR${Z&l=)P(s6#@w{4~UpX9d}ML1LA$&W4?8&4Ox~o_Q3K8%XCiYVJVU zBMk@R%l!>CD`I^4sV3u{=D@1SAD?A1W*ILdqql0-ddxa|MUUBtd>}W^b`}~Oa54or z97uuTW6&03xXw2O8Sri`!H$L91k_|NPFheDVLU{^4@Mx+sI1HxwL|BsU(Q2on;TlU z!i=B_j^a>-^zK%7_%NbdqYLAt+WQaGTo42Dx+eih-%}G=oL4n)#aT!z?gd;w+GfaVpLp0-QuHB!sp@Dom&5j-(NRERQr)@by=ib4Z9|2&3US9?6u* zLp?&Rd}s}W0HX)#V7T!}r(0f9Yce=vAAch4`P$Pa+BUUlW6)MV~)neXe0M#4mn+9R&jGJo~Awdook| zWI8SB^WUp~4X9O7CaUIU`ju*&nc>mNJ4R1ds+IIByf{9~7U45z3aE;%R+fSb{Hd#z zl}}x*4;r zbqR0oI@|pqe3kmOngp=+t@-wH3pwnysk9O5m8#(rrk7Z2B7l`j0#K#3_o(dGA6(hb zsqDW!xUxo@Pd1~;hNrmBFYOXqEc>rV3sisG9A2_C=u={8m`#xKE}kPA`1DsG+R%h7 z4O*yXQhZnN{RjA2O<3Bh0XH<=`UOW?O18$2RrH^$6wNi6?xe3$moqD!(LTllC&!oc;=f}1w*)IUa z{;Ihe3%;U;c8Bq1YIwM6xG%23+FV0XGSubtVWi6V)m|XmC>Y=-f zz9(7O4^1yOt%z;(6s_H8rWO*G6Ryk@Lt$|-iQtujiF-N6rmaP-ITRu@%hu)=wTY@X ztfi%G2GJU zzN`Mfl=_99(gW!E5}h24ly`Qr~ygjlZ*QB$Jw5Z+)-HUtKXDAR}oNlx99lJ(_GuG@rX` zW|ZwL4R-VI(#qe|YOqFx;zxqw1y~JEDboGec2A7ELH3%2`nBkCoj$(@?Gsoz=Hb|s z(~LP)Rq{Hpripyhe>w$G;9JaFiN2crh0LlqteJGs`fm-(jb@#cn1>o1QG;Kz%?CAk zEuPDWl&K+Al^$oeYPK%a7+QSyxn5hM#1g$fU6uSeRI)$c#FmKU`*uEG!%W;-Dt@nu zKhvU78B;^U`3501DjK2Dx~LOopoaZmSncY-AD&x+J8&TfNkKFU2Zy@}kz!QVuTe(8 zL&uHaP2!zVu5GIoENxvKzq_uiZe6;Mhn<(^gArLbn+5|z0y<_poDZxwQrm`dI9~WP z#`In`HfR>2pJvF$u^fITOAj7wPiApX7_~* z&RnB4i+uCu^|#61%Wj$v{OQ9{X2!iY45D%dv^iSs$l~U}7e)y|?vur=BU$Ewu_6a> zBs8JqM#evQD)O({pSxJCMwYyePde;wGKh<9rLErI70Ca_Qq36}$&6CVbZQ|uADwQ= z_3$kN#shbiYJuwXLz!?Jvys|p4N`am-NS|Lk{Sr(b`xaWAF$sr8so*zbzw(#bg~6- z@CDh$P$o*~Z3^KxaDWAcBc@wUMoeoP+n!GMpKHn3m`Y=e&RBvom0iGe7Re)==0_R> z@%u_}%FiYKv*0ol7d2#UGU~J`Hx)_~eHZdtQ;?@H*hgv z1)k{^BOEPZIL7W!=h@BRJ)6HSSHBjZwF_fQwa@!KM*Kp{F(?wmTBdI;HZ1W7!$7Y< zl$qS_qwxdAL10^!lA$GM>J9$sZuJI*NT3r(z!?&tBhDxMvs(^<)Va>kWW%_B# z9ponxm+Nr7xCR!Zp4UB$XTmlgmJbJrZj-+lyqD@$l3wKHut^KrQ!FQ)@g=;-KN0xF z_@s77;=mD9UYAU{-byyBMxAYC2V%H9YFCf<8H=k?!2>2^Y%M_!IcF-YWa?A1MAV)< zQZO!R((VVTaVD~2wMJ#VxmaoHHLAE2hT;9vr($WMBW#-zYu&pe?&;Ab`T5EXEW;fR@?Z5t5qF#h16jTtqLMqs0a$FMlmnX2~+mF->d~b z6q{aw6I7A|Q(%YJFBxXgZ}S+H%U~aB$Fd&b3K1$Nq{`un^dW&g;erxhN`rMKn~&*yT{GDLBfb8>c z{5sdzk~_a82g5KYzrbxe6DX@{HN1I;trkseWo@diGs2VSu>`hRxZYH!9Box8RX#B zKZL1DoN)-AVlTi}Yb&aOh!40AO_ti@oh#|hEjdPeF#xv~eXr+iA4uh2*OJ?eGH)N$ zS+mq7WQazAnojhojrPLTBI>MNgGs`yZ#SKxr2qWi=K#kK*d}`6br5y!CW;1C=V89` z1CAvLT@W|h>tMwj@;mPn{fh_U`q4CqJz3I2z4fpuBM=)EC{B%afD5RMU!!oNZMxF@#6Hlv4ouOdM-fynC+!OrK&(q z0Z3horJIlyo-Z(>BS_XqqIuYsf`W`o$6_`9M9@_Ck+85~`y{$c<)e#%2`}d5uP|T* zMi9`V1RhF~Jr%I#!qi5u51={yL^pK0xQ{j(gWt;hENkkF zJ#^1{9uWR_+Y4pv*m_Wt-)s#TM1x;Rh~wBC`pNW`z!+d zWlE)Y1TDZx9nd)u!FBvjqhY< zO&UU94?0T;wqv>FDRiq|hLkvqUWn~s+2(`KAPrZcfo)bSsKXQ>YY1z^ z#&JNit!{0%=~i{>oS8(1Fewi7DD~vWl?W4kC}S*$I=Vs~f|zOn5CnHI@Diq=Jt@lU z5fWLY<%M^t<}X+l2+2sBY8a7V5)sf`w@FoXnA@dP6`^Cjo;BUfLl-=Pv|Eme12)D; zkC}opbLjx8)R9M!$F@Uwiymi$J8Ogmt z6~z%IUKQquF}VK{tYtWu-)h^OA%|mjA_uM@XOta{w|MlRcw?Ju)-3?<*#09&ZZ!=F zQ`Q7&^ARzjQaY2Ds~3MB+;MW81RB^7&vxuJaq<<1ciFKH#e1tUB1uXCGLW=*loqO7 zo*Xcqr&z#!4m?!M4ZOcRj2CYyKxEV0apzQ}na=zHJ^Oy>8D!nqureTxXG#^UfEj{0 zhMGe>dOb*FCMzAmd;@@=d$b}SQ4@vh2}6qAU%>#CMUyybH0n7DRgt4gVbKbw`97qVb@`2Q4gAgp#bIiNPd>`jov9 zz>Hn^RBL8nE;&v?Hb2tE=y0g*YFK@DUx)!%hRu4%YOq^9RYPIhosz7d?_FNltod@E+;UjA-+^JJVkdyk!UQA0GO{t13sySunEIdg3mN9JXQ242<_=~xbS+id9#!_rX(zgm^!OlU&%6* z)$KtwO8k57d_!fBRRpWLaW!bdtRx;~_fRk!23XhfF4J5HK_6v3Hi;IFw)T27S!NAC zE_cWpqOb=F#`-I&<~rn;E4Cs8Q^h4^E_Tt~!rsYfm(JRd)uXjf)<`xZ_NC{ti0kd4 z%Aw?75s7Z(;la0oz!KU*AVNLI3So|z2htx9N;+%~{lX`rTY183Sh3~SNn)LqpO-(T ziVPZhja*lURKJRuL(>(OnCw@{pv?WPL9lBy5 z+fZ~UUaY!x>KedBkIzNduxj^M-n211{s*S%q#3P$L$cD995JF-*x{(z6k6MA>C0Oj ztvQ_61|joX9|!iS>hNW$ad0(uNT`sAPK8t$&B5b!Z{`587OZNPPI=6s7su?=3xp(= zamxOLh@g`BWIg$!t=sw;8jwl$vfQfcaLT~kM5QbaARJKw;-#6Ez-v*k0Ol5TV16nc z{OXrMv%hc0<(MO@!I#}*OEI`qef@LG*58rWBogZHZ2-%Pq)u9ExI23zH~y)W@P zx^!-)M8kts)Qc+{=NASo-U(cAq^4Pogxm-Z-%5jo-?YxJp9!B-(?TtACy4m|++nWt;z?CQm zBp9_xV%O)Jd;^M*F6M|7(QPb(&TBCH9g>Rmomj6W#g+*5n>7Oe*zsm2yA8I22YvA?Tq5>!5_>`_0xctw9+(nhpJPzVsHvp>a30g59|V z$!xB0)A!t&j&wKAh)1|FKY4(pk)rSC(KhT--Hx>cN;FEY+E79)SgPAfvLX64U&B=H zW{Qc$0zP3oh<%-X=n~Soxq6qDkfo$x$^IQahH%`rm%v)O7#6**~dKH%0@P33P;&9}Utt?8w~eK-~ z#a7BAWK!lsP0j#W+gL$^;%+-lwPGaYj4(neHUo`9Zo?0nSg0`J-685&?-I5b zLJJi7qH)=@JS?n64^(CZ{@vyn46%rbV>f(xi7D0^j`Mm?SE&eK$sRZ$elq&dSs}pR z80y>)WPwEqo-rF}pvIXlzF1r}?+?t<3~dRf$GB|6!%(41-=9nmcAzst*<9 zjgdz_Jxx&TKT8&ugd*a@a2c0eh)y|c;Pbdrd114UT;USjSrFYWion<4u89Ri)-K2K zsVGPc?_B;85uxNRJC=-SDpwH9Zvhtwk#`!Ej5r-=4o%Ca;}EZ-VN7hlAs zYtak!U1t!9VY{w+81Qf@-GQI#QxBI74;aQeJ!XUxCTs+gTIy7fnUp$INL_~N#VmAW ziiJQp!^Cve!{{~>x|b>bRKW9T1K(q&j<#Eqzs^w8qHLl=<_M`&bpInv8-!nu^5#zn zHk(hQx{9(R&9S(RK^CP5%g(J z97`4^j~J04uMT!9&YILaaKRWM#YaXl?7kP^p0 zpsnE|SBgmzx@~eHElp69nsR4){la&ll|ktmAuCE51TX?D`=G&8*oM*mGd9GmM#OLI zrYg`rSOzrN!YQB`TEHgEiNK&u5DO%}1p{x*M)YMpAmUYGS#R`fZfdi%#Tz|PF!m3t zj3j4#A0UWp2E=nEs#VqqOyh{@1>zdg58xUYC{l?qACDN^E`n(^+bdV&O!347w}MkyWN~dG14)%?xWFJTXgL-i z!y1P>x8??^QCd3?G-&vGA$JlBF~PVok|r3v5&Rh-W)r}GEYfo#?}3mWGRYriWYU+B zD0=LR!#hj{Ar6cIYuV2-OxYwIHX_pJ>=T-g#Dt)wv-!d@3broQT9{H3J`&=@;PZxg zNLjl^Q}4dSY0AC6CREv%z#tNt>KAI0z*JWteH)N}=){39V!04K`HI={AXWXsi6I4{ zREuL$Q|@7oOMCd4*OVI*oI7*3=%*<+$xkg*@JRdB#HZqkN4WL%{M=z*e`B){1wl*+ zBJqDS0Nqo;jwrRntVzaEcd1(>au;RBF6`Jhp{S)uyiqhCR@|gjU>{QhNGp9x*hXcs zwh=Fi*|#tzNglm(1*aMVF`VjkG$wAhv~vWN<11NkW#M|s7)~YENuGD#K zVbc`yaG?!GOWfR`u&8Ch(?_^p8oqj#!)GfJT%oPEDqviy2Y%-s05N JYAA-iorW z*KF~Oj6)icH)x4Mxc7q%m`^ilJ#`8eavPKE0!PK;sNUG+91qPnHM$}&HlXxm5NXf+4Sw;nlWDiWCM(uWJGt;vsQ0>u~tK1+N>zhUA? zWsyvd!D#>L2F!fFt6eH6rfwe`H_?@li&jsav%;Deb&`oj!3-AfKPw%om7HGDvc@Fs6U*GZmeHH< z*0gjK;?6UoBR1RWw{#SKqeWBGS|vYnWcsOL{<>6$t$55ck*ByVg7;k=P{Kd;Dj3O3 z+c6V%(!3X`mlCWssNGhHeGg~DXL96-b>p;gtE^O=`FaqYXRt-Xx`5FsG9y|QpwW7a zlsl&03-w}n3k73TEIkiT)f82^()m&5Q3i&~B{qI;V1;=qJyCVq>G2#5gR`0Txv1yZR zlMATXeqGif`V5u8vl>@7D=YfLP|@Q}z^lc!byA8=s{3Fxh?2}|m6EbJH*W*a)}_k% zV8szd?+c0bS}S8pPB1oa3N=we=$@>3R`rFmuxxWvhhQSe*pzF7+5*BrU^p@H>$jfQ zVn-#I6Xave#jQl0^J3i3%E)h0w}$o&i`c-Z-LyDUAF4Ecgev_$(NAQB5%i`` zt6-oqIVxd38UiL7A4#AK9J;xbD_e9H-`sBo0lBGTTRi?1=!CXZFoi7h3J__Ep)i_O z?NKz$Olb$^VYNt%5kG9vx}G2Q4Ory!!}Uo0%IRZw2jhQdiWj4cGuwz~a8EJ67m10R z9dj6o&W1z&izT9uKg7HlVW4Cv4X_5bnCj(wFh0S(x#~PM5lR@MTJJSnk>au(iP8kd znzc3sLRfuRgMw!t(yHGl%fNQ4=9=kYG6|3OcCkOL`Opn_6l%@fA1i3N-8W5VcUW4s zn`@NdqV~T-f{P>x$;?C-6)7o5g5fDClH`iN;M^xqzXylLCU8poTg-n$h`@!+SDz`U z>ko73(IG?{B$uXR8P8Y=4M-uA9|z=;aVzhX9##I5yGd@)h0#f4)-0fKTZ$R`s(SLl zIDv`vg_%ndG#FR?RHm$_nDT*dsXeXd*Y4vPlxYb}Z7YJD$<4-BFo`kMD729ED7p<@ zLIUc;yg07U8u|9zefW{}!5Ce()js_ZpGBFc@b@8R;5@j#E5=adb#fkpdnWc1_vg`R;UmTW4W@7*GG8OHFJ1;sd_ z%<-YI!gP|x`sj(t(aFNGILmYbY#R<-uCGSZ}q$+*BEQMvdCC^;=0G(b?0@FfWDGA%73S`loi9k!!S zB2WAUozT>6Wf8Y7l>S&}z8`nSTd}gy)5>~sPkN+Y;J#(4C~2F-4`0OGG@7|fr`QK$ z1~9QO(y!|9_1e%(p{|6-mmg6EY%3YPWO*7G&%Pry!(QOqcKV!$qq^WWO|7!>zpYmJ z%gZW%#>~pU=aqMo7_Wu?Z$>q0%3bK3S#W2eK%Qn@o=@0(Zwa{!7+(`GO!2oV(gsj* zr&A9G8t<>x;rEnv_=k^}0gb16ffVXhg~ofTRsR06%Kv$01tc9n zMgBw-C4pjYs3_}G)sy#LIopeGh~PahewK3-^V=KEc7oyGY6c3^AYDx+rd>9dE^!;T zn@OMoGPtCaNoUl(w!G?IW;r%Tw#79GXr(^-O=0i)N(<^cmNPv@@7ODwV;idKk`m#+ zUblq1-;-a+-n&ICOC>mfYV*6Sdrq9T7*>h8uY7bFT{z`^ks}tQ#5(8uB3Zr@&gTVQ zi9f2o4Q)ZnH3@@KTY}oG#d`LLfQVAbwNg|{YhbARzvI)j;<08gXLub3*x8304>LGR zVMj*x!iV)b&cZK*BdqS#%3k9Vs;am=%+rNS4^ zE}Z4;xwC~tYw3|x5cBZ0m|G%vpylrXeXG6LF3%E53#(n$wp5pD!}-6Dsy>{@k`A#n zoHtb+&L@1xZYi22R|%{i#kHrI|C7tAevMb1F7P?8H^pnJin)J@E3cS|rZ)D; z{EQ~5va|2c(!|rsnz*NG6Zh3rim;F1RlrXn)J)_mJ34|;^NGT1hF>YnT|9Lss!rWk zXX)IF$~yPls-62*n7aJRokp`bfn0!^zq@i8zYw?Nv*hyeRb|aQH9d`9;D==}_OVpe zz&;mOUonxdDQn@$RR{8;vPOimRVVV(vo!JgvL>ETwTYk1n8dfGp11w`oO1i ztvVtLB2qNE<~w;t5{HB&2ZiD@ILx2S($^1__4OYgRgJ@NDi>9nTADCO52Oz)4=n+) zIzQr!XIZ1>#ZfF$yTvswWJysnEU=9Fs{MQEEdBdZS^qv=wSNxp2khSh7&6=3Smc+i?@S4xlb0&lefHtpb-JGu=lRT1pjaT^J4 z`>4NN*31XJnF_V%PfIOTpVBe}i|6#ZSQR(l3oyfwe9$oa$OFOb@7Y&1!|LY%8-sxB zzR#ZtGwcPU1peSK*JV}B z0s3hKk1CI3|EtwTS}564{}rYxOHRreg3t^s!-uMdz~^GeMl#9X$=8(mHlAGJW$`jU zn&HT)uC>HXq@ncsvihGe(|7WdP&w8YXQt)y7s+1|5(Q^7Ih>^U#2&w<#8j&4e6KFI z^OXB%&o(dr9M6kFRI_d9cA2JA)11KvgZ`eRuBAtMvC{5T?ofAIjkOm+ATOKHTdC6z!_xEL?9>nhssnM@LLk z`d~)B5VJ$(0L6W?fa0DqP&_RGMY^BguL6qHZXr2a5>P0x&%)9;|HIu_E;{7CGV=p^ z^k3F^={3($?6m$a$5;F-&y6;H*5{)qC@eM~eThiQu)a*765fxNisPp~UqNub_lIZ< zd9xE#T4#+~T*RhI1v99T?TOIygr_B^-{vZO?w(&*v)9d{-d1b%{@FOiOP7>*e^o2# zX)zx71Ur#_zYGc9M|zS9M)6)N@L(0nC&q15kll~Vnt7);lkf{i`M)T&l#pF)BiKQ@ zi9#t4pNc5igeYK}`TJ@yFNH;N9?D(H(RC*Cy8|}v4A|%UW^(qH1bU89QJE}ys%@|= zv2e#71xC707#lTTDZjom+r<3K15M1IoT;LSMblp9Wu>Oi3K^UaMq^c3 z@mt~!rCHp^%X;&*G@!jJFZ2S&idT~;#ZYUfR^NqcunaLX1xG7ULT!F?1=2|cAppsj z6%;}lI2^?i?9;&{aN3~7y=oTho2ipmV-P( zndvKI#QhSYA~L`j62{aqpl1XIcGk@%j@i_c9+ZX}8RzuP!(rX%CaV-i3b% zhs;-1IQ}W_f#a43PX6ACG!g$%dU#&oZ_0+Jyjjw#7r@sLU5btLsJW^D{aUpaUs%@S z@6T-UAL7y4PE}i>TqwWXcA{`u{mNHvi~3QFH16WAz?zSOHR$pOz=7zUDXfuBCu9+# zF`5`}$fI!9c=PJ=VfvhXzHFF(J(}Wm8;DPYwp1AUaJNoDMmDT?RufGCsUS(yB zJ3a)wd0yOuG~Rr(toe_mhv#_n_Ojuf9o{^(T8lp{Ywt~|jU|NL*u>i?|QpJ0xcd99a8HDNK2m6pScXKCUqWlemtY7=j?GKQS+GLfC< z@()Ww7W%Pj_9-zc$VWp}-8|2W`{gL>6!XopPJJW|S1<5(FCcLdk#%ohh57$`jk9=j zK4ppYq>4)tIqOrBb2;B_W8O!ZMD$ zjwXYnzt3nFRLJjdh7}1u^`O=Yle1Vimq@4)wb7>m{D}2p`3ElZhcw0%b0`6iEPn91 z^0(_e=cv6p_&~4dyzzS}9P3jbdY!frR3D@w??=P$WGhTlM3|}{+iK<-VMYA;V)v_i&QMHLTSs9xqv{WHZt3k}c zRn@9|e%xFdT;C{b>!UNl^|n$&=24ta-V&+L^YOd2^Sg&x(=^@&49?H7Q9MU>Z<|;T z%VDp-P<-}T{K<4c*0flC!h$rWzCPV87ptH4ey3)!sJ@Uzknk~8b>4m_ZZ)(_~{> z&;*p*w7V@awP0twU$;>xSmABqBqc>rBe{=Nu<*aMHzoPrZZyA7gx}d{F}FyeTjPr? z&)}EZHRDo|I5$GxDnqEg^~S>-R8S^1Z(a;Vti-Xt*B3D{U`T#IC)Nr8HC zC8$4j)`R~-wf?=Ttbb3P*}oq?xWRw6TIH`TtNckbEC1JX9Q?O5_(luh^c{LYOmYby z;;rGLtpbXWBb($Zq4@k2MjyU)SGtO9p%83dSr!vQc({ZT#Mme6Ax}}LF(!_EXd&$= zILa>D(4dpFntA>(az!`g4mIU=HRW!{F=lEJ#C(YV9&U!YaxKXX>#rUGrHc^l?|cP! zE!Cfu`m;uVF4mvRMXX!%`s?MdewUvU>+Iq({IR^sMFU^Z54o`TsrA2p!)7KPan!SZ z>g;cQovsPt&=1Gq>95}`up1%=^^7f){B6j;OV{e^a{XCh{atNOSLnfo`a}K!{x;{; zi;Hx*UY*}yPdD4s4SIU1o?d28TkYv(dfKk19rkp4{-e6q)2sB<9xl>tqyAVomg(vO zLB!f$rQ3D7wT9Q~_7dG%iyL*@rdw-ji*B#ft+laDj+TSD`E?&RD_@)+lq1fWSyE7j zc1m+3hZMApnmB1L;dCOG6H<(bke&}xiBq%Dng#S@eo#5J`T1?Cb}`2Sk_k^mJ)Ya! zYKYt7Y(=#t30u~d)vB+e(Wj(>86I7y4dmd$k)=ppR96{ zdqVCSoL)evqa}BZb_V%^p-c){4Yo1Vb1lTXK&5%_GReoR4Kv|b3b*M8#WkEQrT{H0 zA2&QqDc{+3ttmbDU&L9YtS{sUzm~1>T4X-@rh8`&xoK_8IG3D@02LtW9z2S*oS)X~!T{7&eQwHAKgnNYRUW!rx>c z^Ary@2i?K5l`(~M&prJfIb5&&HraJa78_d=e}NsPVE~F_>oxf55DK=kCo&M|5CK&| zm8b}|`LI@mo)w|n0VngcU$IWN#!78#`l3#EpvB14u-nugP-04~XQ67S-{;}iFo~D{s_S9jWw%{Q4|AWxGnc0Iu$P@m>0w^r z{v|e%Qk6g?a}s1bec4y)v9<1vzce&nHRk@lYK`Ah*7(zAHvWBUJiQmCs?GStxbno> z@V>vYtp4Bi`V*Vc%lx1;zTl%oiLvpOf@!{?>HH&t*wcF^uE^z4}VbB z!}reY;rq_5hwmbhEh@iEeHjP-8?(Onw`4g#c=6I0_^=;yXh5p&;QIP_n2>~@I7DCI z5oTddUU0J9kLP8+Zal{vMA}0OdFaR=QHs_w1I3s*pRek|_9yD;4Fe|1^IPw|G+ z1^&f3okU~}yU8r*ufc6u1mUnSA(o$egcWe^eV$`O{cE#+d8de=Q2~<*{>Nf;K3%O_ zuP^J?6J~bnCreX@l$fsZ;__`!(j0t;kG2;3y04wjtt{lmpsUZ&&*R-l4g_cAKl5IP z>A5$(h06>4r5A80A-U~j0J7C_*t#|)ooK2gmhafXB}z~rB}&-nzqa8^N_{M$-3e`z zy*_ub>_dRYq}tBCM)^nYtvBN{^0CZ0P>6W=Op;=@&&cn4{%7ZA_h zj9}Gahtm2K*&;?E0|XPTW`1n77}7l@>|62W2V2cQ7o>Y`HKYqWiUQJoc;h59lusHLGht6UTDfJOywyx0Q!T{O3W>VtsgxS{ci=?wh8oaCJ7Cy%tg8E1-W_- zS!&MBzc?4I%`Li6OolIF-x%r3lmrIHvzQMmf1XMFpz2;!UUhE8ZuF5eC zF<%Y2#ap-}Ij%a)g>{=9)zK93P5Cxyu8SjfbFJ3NhKr+S!rRCu$ABVO*8=}Oj1JHM zw~q>L3!EnzgWt|b@2S|0d@)5XnP`YB*_s8-r1UP{E>wclJ|fMUrMh8Kqi5SzxC!D}wJ@8z?k zo;X*b240(Qbcc)*`mbg&bul^9n`v_OMqSF~;of9CbTHB`yUj5CUibNb3o`?Ibeu&K}Gca}hZ0q!8S5YayS z`nfXDUnbDwnz+mmOQyui=&g67Fh-xmFh&_|!1+kNM3zdT&kzz0viuMv49!Ux?`MocQjshPrj?=c3N$-MXrpyY~rV10Wz=858V$zWHYz60UEGLGT zh{;QM;Asy8cUS5_9}gyNGX)%K(W+y!TxMX;HY%^lE9^tr+!k9?I0i$LoHrFpEX%E7 zBK24#)^2#h+K;ll;gfB&qbC>KX!i?&bK_-{>a{M;W5j(OL9r-f$hm7Vdh*?!K(aI!03J{IzkvnOO3{?*p!iT|Djz+bT+4hf3^x0M z^mCdZj8-LpQ;!#}%PqS+3@N(OEW-TbaF8^IXUlS{$yMSR9|65TWuWBkFgR!uFAkk2 z^`NcaXh(P(+Bz+mvsOoWn{i;C)rHM#cn@Y_`mf3_%`L+lesyk{&drH9^dwrIUn-Kf z46{+UN8he&-ok6pfF46z53^kmBjN1#=(kXRwpemMM!f>C>hKwATfnSXHajqujGH!X z%Y=FxIfdB35WWJS(TnaL5%j_t9U*I>NXuh;HA+W}>#Y|db79S5RHxNw6H(^$*{e<` zMkkM+h31qQ9Uq;Vsr0xWT2~9HuQ9$X7Q8sOc7vyJZOyHfSRzESM)lI7fT~jN?{=^$m6}hsUICw?-13EiZ5GA|ILIX zNDZ9+=Go7h<)r(SO`7M*^E`N#S@Eot(i!>lex`X{qIm_LfUDU8es*C6MwvGQk+U?7 zTnl}O`grS!p`*t~$5HF2Cnsbtx00T&b!g(mmhqG0#Vy65+ecg5x3+Y&w6_L3`k^-X zi!j4a42_|hPdK+SmA&kV^5YFnk4+_ZgWKG0Pe5kLb3h*(>s(T$jCHQ?k_>yMOm4ht z*Y@Mm7y*f@U&pL|8rGK!sy=EUYvJT;uT#XepTm_y1CaER4-Z{Ll;e4^w6x2rovjCo ztod*Qbi%nlmKNI2)sT*NsR?9trGe1B)r%L|7gq+9Nxx-O1850f#~9h+XW<0#?6qA4il?_V!AH6 zI4hPB-HJ=a;S1U5xdw~qk9aZP zkMyeV%`Li!66=l25t!N;CygXV_k8*|Um33~DW~^R1EOv;jE97!>pA?CPa+4F;DtsT`;2eqNMARuA&pKiZCJx*le-bkN2As?qTQ7MSh*g ze*`j|mH5w!M<=umoyP>-Hy?s}IqQ^AlxGLaUJ4DojC5~{F3Hth>{*u$W4?(mZe{c= zmI!hyR>pEw+IT+tR+e)xWdPebsHSgnqcDI=`6brC!&K@!QDhtNr-6xlbp=H*?LA0a zK^D0@d9~5Um6u$R+p;opTg{$fVFo_KQTHH&7XG0D&TN!{qspXyi%d9EF~{Dr=r*)u z9#wv{0P9$xB@iiV2I5Al;6gIpu5ISlgMg{|xW%-qL_0(>)MRl@o11eN;ccYU{OAH- z;atf^V6M^xtmqf)=Pk`jJYnHWs>X&(f9JD>&{6n%rWAbm?3IH53RUjJ$13AoKIFib-p27GQV3)XSQY{ugsK@uWm=rS+}`NWHQ8zc7Z0OW zj~ZFr(jq0z84bI9ytr9oQL)n#>`Rmk?1QUCSG>`-x-G#$p)GHzUwDx`Elu#t^Y^qw z3l8sNms-mRMb;TRBIalby*qyiKPMFS=9>o=x4@jW=|OxhX+DB?Wnt72vO~Xg7ax_1 z%#Uttp`{I;kN+`Dbq;acVpGm?#iG)3g|61Z(~!mXc5Tg)nx}G=wLdr?mM#Rae_WGo zYhKs7p|!cWxwU!2##a8VZ*AspTPrU%wsz>Qc|-HX&BzA|HFM8{=C<`4J>%>yHf7J^wR6JyD!nw>~TJn()K48l4ig^A<4~FHk-Zsg-4R-#N|uuX?Tn<(h8eRc1P@xlnh62 z1F89|KnyKC)Dwwo*E;rE&lJO&v-6iCzm$;|*(-~aXXREUo|4Q0p%&;a4yyr zqOd1ZE!t*E=s-#wVT9*5?U1kd{1#iLp(G#aU=xv$+_Z2yt>WO-ynuzMimuH=ks!y!Y$Wm3j6DTUFO08NTE1oV_O|kuCD-o_CxLpGmiO(#9q&i(Nr2 z*v-l&qmpzY)f`@a`11MyyJIaEs&(|$dcKX}2{j{@pT3w0m9tX&IK<1P+TeRq>>pmV z`F+&fx;#%z9**G8W@p~jpL#-dmu?9k>x9sfqn9W4?t2@Z3C^adT_|}-Dm?CrdYz_LOX3#U_eJZX5QCmo%)1oZY1LCoS1o+65`Gtnc|U3$YKZhXJ`pACglW;%G#eh$Es_5Hy$SMbWha@eQ^(yB))?(F`zKB)N@4g0(2( z$A0#oVdBoz*F+=5xJh&=#9$&Pk%6(CR4kI@(Ne3ZhX9!N*=`_cYZPxzrMKk5gyJwZWDw zDY@qCr-V)#mj61rc48m{h<=V$msa+$f*ypjCJin&%9q!ts26nQXGxO0ysstgrxn?j$n z+WtdMR-MVPB)6Ikqr3@YIVO8VG@cl>a`&;xC zU%wBHH1#>%TCp7wivuupp-o+gS{aZjUG3XZ7N*soQk_)uF^(Ur<3J1gfFn68b;~9$ zT8yJtQX9ClNnJM0gd8Dyj%tPWB?)gjlPRJo38qEpkDsiGLRa?M)SB(QuUW=?H26yk z08qq>QdZjXvhU_1166E&6CP27)hvyRtK-ZK=td>}>uJd8@j@g^VXU1Y%;fAD3A^$H1ma-S3SN%Gr~*me4RtF32L<+d5hHxt-ha+ z*}ykeWeZABgW}Tct)gq!`)Uupiw`-|h|=i4P4B|tI9mLU2?6t&yV@#LDw@}|sVMdKD}dne=)Wj38X@B1}W0$jqM zy;m^J&%J9INN)m}{L6p(u?|k4%Dv7KoWVTFlZU2B8v!H0RE{3JZXFpWn_^*8YI%2PED9Bb$BCfmY8Iata4clsV294{w0c46cBS4pOLLmKe8Y}A^EiKs= zPJ2af5r@^Ez;|_R`<=}O2Rpe3kM!66=!0-?Ul0;$PvkkUoSJpIud}EAcYz+%%c8Hh zdP2GgD-oxT;3e4Qe{peefn2-<%2?@Rgk>psR6Z?Xp?>AG1sZ>oAvO+vB^;5QHjuF3 z?Fk9$EdEt&Tl;SkuIOyai8&Gz1H@GZ=;7Uga{#v+4v)8|^tezhH>+ zv+&tHcXuw2VXlMg9muk06^5+#mgEO=^Hu_F0ep67t2-P;%io6xXd9PR6yU1S+5x)( zxEf0IflQV-FB>mHonPUJ8}-X@*RcGya7!z0?l#us7M|n_l9e?2Ao#1kdWTiHV@(=g z^fU~^F3$m9RK1;NQ-&{s&*Fe0y3A)App=F5xNZ#|79t*fj%@BU(2dK(oUQYd$7!GbzKPM3Y{9te`iYa% zrv^`0;f_L2|Bd6BLxa~B_73>*$s-KTsSi9-SIJIiBh3X)pBe&ZxbC-Gza{ zuE9NpT{jIJ$?Tb!I5|VBJ8)p2tLI?&?F+v*hTs0op}l(t_6!yVyLJ`2 zyL?SZ2=(N2m4Nr4GCNZoErvGo$BtpiO{v7sbb;e*l^~+fx=A# zUHyz|VrYEw#ORcoxGHmWdSZeNYK2on6GJC5gNJNdrpKp%k_z;UpDs>JWe$%NC%SGw zIWg7Edf@FtNAJk60p{4T;sgy8Po+Dy)jLLOU46US3)lDewHNk`58Xaiw5iJUcXt;C z*&VmLIFh;H&b?zN@9dr$izlpmXkxf$eB@+Ypl5es_ul>tpz&HyPEQrat?*46N&lHW zr|G*&$6xez4eZa@O!f5~ECAj;gPC2s2m3XAz*iV33e5mujAaLkr;B4YzV1_FrQyXG z+toeTbMu};_YGYK5AHco*qWIp60m)HVJg!+fY~-nwp}31{(08 z$)hO*FLkB2c;e*5T?05uGLw$UC#NTl7Q0W5kBlC(afYwsCj&hLn$Qe@>0vT6UBjpM z7Kf(Tpr-mWHo@B+R-=$taiq|m>AGQ8_ksPpM^BFqGpRJL&hAF*VNPPeJEefUdk)<+ zs6iM(#y|xRdk)^*b%0j;y863%_YCgo&scv|0xv=F6pcC3^d46Ipr`tC;N-DgMxYwu zf!&4foBI0;gL``WY)ZS24~>r($27LMrGehQ{`QRic4T&qP92(1mwUQtZt#q7&_K1f zXYZljlf%W#q3#6v1t+5|=sEy?V0UjX59vo-yN*6C+&(>$nH)Vf&cVs2KKaF4$i>!MeaklK+x`oxHC9~&LNgFX%n_V4NHEtD9C!w0Bmriv#{wQtYR zv3BnwAc`TJ>D}FPC@{3HX&6Lt?Bvj}QQj@1!&ApIy=}}gbLOOLK%F{qYNB`yUeOEN z6wdVzb{D!}0w)3l48MEEhl^)22XCJ^G}7%P&RC%3N!Von(D)tVx&c$zduI$cbHm;N zP^xcNM+#rcSZQDXq3fCd-kyWki&ymw++qkMcvTQe`)n^d?1k~JhbJa@PHN%I-i?FkSp%bUz zV#hMw;pOlV3P5kT4|e1jk)YANlYMtf;dtj?q&Lv^v|A-0h?Ik+z`mo65EzO zc<@kRZ_j}}14jlBqnTmQv4Air3=P9b$^g5kzaRQhmtERp@~YqDRbLQWdkzoA!gtTXu3ZQAWNtb|7mJ0xqhrOw?RTNL zOpl8V6o;F%`x?nbA8B)U&%piyJqEu7`|=(ariLc(u%$e-t^}P`4z;96TIYopa>O?j9(rYYatVTv{7Vb$C<2P27mCOaG{3X8R89MGMm34*R<` zqZR}54h-wd%-~_D3`?cE2aCqVPLHT=u&cLEh7W&jj6gTm-43F;B_gy86$h(v^h5iD z($y_QWh?_WrN@U)3{AL2q&e7i6LL3LTCiEvZ6S^!$N@|xXvj+tWRm8MvWmubX9uy3d@E3KR3x-5mu{b)X~badE^zfIS1q2zGzCEtMR7W9MkV>K?lfHsh44>}f#iMuFpULSHQnJvo zjwA54+25gx3er~{5^w(oBDQR537s=P9GSR9}J8# z<_WR2dlo?A#8&?;CP9)KD za_lZQ0R@sEBDx0#_8c&Nc%{>YLkjc}6r@3yjCrI^r9}|>8G3)HdoR|3Ayfh~w`Izx zDt?y+W6xlBFJv3AD@;xQjhRCOeS7xoh6iDyTvZ|RWRz#z9&vyK=(u(y#BpO|&+xHg zX77Qnfg5~?fKwC-ID@5C@{`1d8B#_vA^@+ayQk~GftyeSU_bon(4VdPgYwkfe}(>R z&-523PmWC+3EXtW&4!Kr*s-Ub&1VMg96DukH5k1yV$&PYu2802^&dV6M-pa<*=+;4 z&!owi-pBrqFl%xE;o~sQ#te#>f_faPXRyq{I8md+nc?CX;?cD#^Z#gerYGSdBGgpn zL5Y`EnkYk3!;A}w_<+9|U}sze52Egf7w&fajk!M3yH|K=ekF4%nSN$i-cg84Ne#e~ z-jnV?fPa7SXc6W1y4$a8@~xRomiMTw?dqm2 zCyt()-fq;SL2d4&;;xeYqS%~I4 zQ51tS2p#ISpPR-{#JZyKYx%xx`r}brwS6b=6#kxer;cEgW<0xr3d)FjFTV%|5-ubg zLeE|RhiYOBnNsbsBlBvfvy_)@hN5o%nAYPbPZV26io-*#y*+({t^Groo_)u$bjL@J z77&1w#fg!jqs79+5OmpkeQ~^ql)xF<*S)KvFi#4TCr75hG9QNKGFYfUSSIRTyqZS; zfxVitdVFa3XnRI~w`SxX>OKg`+^}nak>R8*!LEQ6}{vLetIFc}t z-mZg33Wrd`-MmSw41x9EatQZ2qbO)kHEO&k~j1qDMoid;4~@9jre z^S9mpc4W>J@LEfY0k?qupmIvfTcskr}}QjHTT(+StzRY1!z<@iN!^g=3w`E6ap^6nnY9Ejb|F~Yi^Bu35zLDE*P9;U4Q z?may>%X>&GR}}{PuP<~Tf?30Kf=(rJ^P> zu@OI|5-Ka$p{O4fQUOKP0}2`IQNL7)`gy8XKp|rpVY#IsqSlO@C zani$ZI9U&8LN08^h$7(_49YqVn!DF|bGPsJ>fR$$%r}=Owc`Bj`1ZPiiJja(FoOAx z!`bO3x6Uk~xo;U*7HHWfGNi#9Q?Rw&tJ_AfoT9}LEqfxm0_5FU)D&*8MFZbSTk{xfs~Iwk2{5l#As@i?C`k9o?-m$~sD44~UnXh_F^JG9wcS zagBfGbPaEs@Q!}0ciP9J-JLCK+AtV6XH#;$aD6j2;8qm+28XZ_5VULY9eFr-aZ1t| z{FE2=B;azhN&{!=7l?vp#F(;PW4#Mx#Y~sZ5OVsUGwxE&&C{I$`XhXC3&t<5>TUAn zx;UGg4cKw&9q%8+HXW=OM2P>Dh`Wp4I%$rwoYFN-ZK_5=e{)2iUw^As73mF8I##G; zQi1j79mzh7C;d4*iLrNX?rNR(JBtk5TPCq$%W8R}7QZ9$z822$J8p_*E?si@&-V+R zCvv4b8lzbSKm52=^_2Vd(-E#IVJvaF%6H59n(KU+Y;>;imZLkS{eGv6i|mMN;Y(Uu z@APwNiKleEKsLbL+Iv@z?_JJ|KqjhRw!qU-1`@Xqw#f@m#AYzJO-T(iwMK!JflkcA z&|>s+9210j%OF?XW$`V*awC?%y4`4i?6i3wGPjKkO-PS!ZZ#VVB+%%S!wwbc?M=)A zi{n^!?{{mKB(_19@xngL28FKZ$L@qPwDSFBkk%uzrKw`rk|DNAD|wh6n{e!Vi%s2^d?c*;rsEvZIv z4GSHyVNHE~Z|@!$8!KCt=zt@3GeF8mH97&E`%k8cQmvPxw{m9S1Z*l{0bN>>8669d zu!_E^o4UGmrPm1Pd;IDa#M*v2opsP&*NIgp1U%3UikX_67{yRm$a8;5tan994fKDU zcm-{KD%m^gd@#>jNULHZl^^Nf;ee&3@TZOfWXtZS)1FT3Px*SBC0UN)?nq{^)4)V@)*D}?mhVf z0s5;xO1nAw)e!x73Uj1s?TU138s7yc-J_Uay6)cD#L1O2 zJIp>fDCW6#p4j|?`mv0RMF6~6YGfQ|E+ux5e-g7L?yNh3WhUwu$){b@(;g{_J3U0> z5YtKT3}NR4wO_}>9x@K%e28o=v0JOM)-EQT4w+{zgY~V8t7O>S#9vJ?85*N)yeGKWaW;@z8 z!Q&Pf%4OQ-LV~0zTE9{#bhJnxZYfP^o5aTDX5juzO|<{bk}MCHiSCWGbm5o}I)qz= zaT6X{!h==GDjvR}QL}{QM+#)Y3O&3x%*=c5;nKkJfboDI@x4jtIW5LL@P`~O)?&E8 z8md@Q!39joMLtZ07~ONgNH1f_h>#xqc@9So{rDgC0pg^{`q6BS>KXhv${1Nz-grhq z4tDu*U!3sT&S9*c1gqOHbL}6+h&>R<0XVavx83#8C??jv*Sc=~#@pL5z3Xbl*jvJy zY`Hc|ZpCmABXu{-75~%+x98EhIfS?k8(K;8xEPC&k`==O3XcJDO?<5^imyf25tlrS zjVyHHcFcLWWF^Ph+%Sj04$Exyu5e5m+&=KywNxcyzGO2udtb^`xbl#Oa|joVL_49; zNL$}+4ce_kiSdgi<0RplwLTzbOP9@sc%ln7=$8aVQL-o$jfwPcE=q=1^KGS5fU*&t z`{@c>JZVj5b zrFs2ExK|vkF_ABGqX;nOoYdJV{+$$mfu&;XlSWvcItxEL*VAij)xuHiB(Y9`Jy|{HS$@0nS_->)C^=|h@V~J;Xu(P;_8Xv4Gyv)FU}rze zl_~P1W8<>8VkY`=0vCg+97U!KF8D_dSzBR+yttk4saPp*5vFLYU25a3s<0U^4E19D zSiU%N4VC2N2EIpd;u(j%C$T}-A_rIc*noU_U!i{#D?k%{_i%SU=$C&BZ7mogaROsv z0#Bw+V)U8n8x3~5^WrU?y*QMHBN`wF5{oN1HqIYK?7X0S;oR1}=B`$(pHUG=8!Ack z*}nsENU48xCrWht<{db|=`|w>WF!oFr@*bdg=bfSQSA3RF}LG*57=Q-5UUL>ZM{=% z-NCL244tUV?vZg3B`UH|^!AIgIWhI8if(mhu;GxKCvf%(mK}$IiHQv6g9Nn+6=1L_%VE!HO5a9BID(cDCd3!sBAA4sO3dDmWkgOEg_o@FnSg~5x<3kgmF^X$4Y#no>|0%JmaWztXXT|B1Dd_p^`{Z*|SPQ#yYQt*GLFq z6SV@^)RYX$#;0%Yo$4PRnAnb>r4Jz}TcHVu+9$T-z%3&UbJJF}qV ze2}Uxxp)vru9sj5euPzYt-+l6-4l9nre$!ncaO*$(SahZILiilb6eLRUSoy9X(%l+ zv|)LkBp9QBV|+lwSJ4=wlNl{$7g&S=MJ$s$p>QontD0vFK!rs$Ra;X^III5hDJ%5R z)ZdRIF=8i5>mJpB5Pkt9mOWyhZmD#=lER=E*CqY#k``1!D;1VseCJ(1G*lXlEG$tV zR_vfh*57f)v;;a#`yJcTL}QcGH&a|el`OJ^a#S*F#m18*GOo}lJLK6F8HYUcQqGqu z6@|zo7bhgN$Mf(%eF-98o_bu-fKakHI$8{hyC?fccl4tY+c6u#CWKihUf-F=x|=(K zr?!B!J6pH#$Y0lL=u1fOqyl!H);6!lDTSzXH;Un)B9}l7)6yQqtC)QwRK7PN_QN2l zSt-xXX-QHzu0^2_(NJzD)?4b^$ObjRN|8Ke_91)SWIz4X&fVnAVUMiF_|LBXiAWTb z1y}BtITKR5G1*J&_mfn9WRe`F5?=0h$Sq>~jMG7}tpjd;ynheW+RJMR3Oh#!Ms}go zTN!WyF~y9Ln29G%(bUayDFhA=N9vccP9ycDoh7s~)&sFA5QPd517_{o%b~PXn~W91 zpwv4eZC7$zXVB5exSR!%Vc-J~4p6#tbzWc;;|;(U?-ndm0}qE-dnG!>ET>{nFHsElF!?ZA#6d)GCl~R^3JVmVgKOeQ7?~(elrSa63dY*jwOx1+ zkmnH4XZRHj)y-@9tU({1w2Oy#VIx#=7tLcyHY!4Jrfo4F^=Bivd)an-#JzhnPvv(p z^M|zk?M0bNQVnt~#C9xwzv8f^@Q{BtqSyu@cI>F)K zMl0DViiPy0cdc&fDl}n?m2d3A%JHrw6f) z=2ttYCs1_{W7%JbCh-{7E_v*M4Ecc8n&vxc7<`ml>rqy4`XQ63wW$RuL&ftd@$zY^ zvn8L%JmP>=NMCw09^GCYbgakIiZlVyjeJ8l@_qA%^@Q$Bxu39TU5)dlcv7`=A1HcL z-_DmiNQ-Fh$gL;Tr>9PQO@yc0p{m?z;$~&5O93!Tgz=k9SnXBmPMYy~g(7r#i_hMz*=TPPX zi*?}r4;ygewEZqg!V-a5HSk=$tYkYnI9L>>JXF}`@>n*?$1`y;nn><`rpvw4ms>9X zL{v__FUMDSnbw81ck^;DAU4{P`b?G9(%RO&!na7mJODyh%9L19S76}C7Z<9`P0EYuM3j7&@vmm6hH z>d-~ztal`2oMeSTYmh3E$M<6DMv5y1qf-O@bnJo^@;PL5}NvSg?wC&~dM(q_- zVc5ZB(&!Ww8nZ2jtZLUI^=U-VKWLL;>-7cVXj+9bd0@>bL{|``>BJVaK;MWm-Hn?B zr)@B!F{=bIYGwg#+USvkI@)VLX3$K#PZC5}6aoWzUy&)8J#Xoh*5&9^Z+jI{w& zA!Ztv2CY>}R^ONG9cV+^3#U28kdVR#joDyXz^Fv}ks*%_fm-mM4r1Uauz03&jlio4 zbI)WKwj6NI(9}KEPduG-*-A#)Q-%w{g~l?EH6y*qqUdh@QD1Ak#etC_zOO2B5mdYv zA?6krByI0o)jKt-2&V+`J9sNb#B|0CV4+o{lSx(4w-}%H;XxcP4^n-}(px<5lq*2s zsq|2kdMK@!*sj5A8%gbaF?b#(l1FS`)v}ZCCNml<6ASAPZa}P{AXo~ASrx<$Y|>68 z4QXPvt9g5B)B?|;qcbOSqkh^w459zYlU@~NrNdEmW5K7K25d3YzybQQ(qKx~vRGM1 ztj|D-8o7`ZohkP;no|fSalUydG7&`SSUviX;fG(dfyUy)RXAzbKj>zYNSBo*P6lg{sjfsliJU{>?YAs+J)8O&ql2M!_T03Uy z#azvpqwwGjo=-B=qb*p!8TBb~a}?IEvsB{)SOaaw=^B@lm9?sZj5wi$*DZ=dSSda! z8?nQ5k0wj^)YDBUyLk zx(FAq_^v&?C@#pXIVbQtRwm(q}YVrJSihz8@a!P1FN8IjhnE0!;!3z6+HBN)E-w zy6x=6`FftuhZEC%1m{+0(k0*DaSvkEpImi_Z&T>(#Gcc~dS^KO*j^dL z8+F!o!yY$J3Zu1Hu;OcRoSD<@i9RRB2AZ+kRKh8GO0}+cY;bw>3-1kLyGnlAkk>qA zimi^Ddw5&skV-f04$HuA4NmSF9JtvP=!bjHL5g0}qS`OgHX_B|KIvAa@KB7i4n3oR z>cIAUOqyI^C({rpduxVE_t5(`?cY5#$W>BomK3YniUG(_If{F0#^3 zPry&}DY{6vf%gcJHK6NE_V>~|_(xk~t+7Ufu1EOFwRCr_!AVqD#W)_8A4T-e!|*s) z7M+K08C2&-*MM;W+wa)85`Tx-Yjh-7--@R&_^Ygid?D6Ex+4=oD9cHZjZ~1tCotBO zoVg4HMZ9qs7el(2QThzNbGZpbKUe$s)(W>;g)_Z);U}YHvUc^CC_qc{D)9v|x|n8M z5T6gj6d&gal!N32F_**&@=D|66oPEs4n-t_1oY7ps)jtGfG6NPSuS7friKR@i1D#Yq(yGsh+WWU=jZcix8ESew&G`_v zj1^zJ*3_?S^Ee~AvpoAE<3n`ZrUC{XM|w6<>v1|J+6`ILT<;&2!wW0j`+4X%JPW>e z0WYGKlUh2KdlqtDila9<`m6~Jst_7!riu@lF2zx@HGc6g;-@q;jUE8;9iM386SvL1fP+NsAcnQ z4cD-v_as|7Z!wyL8aMYA`7Y^b)HW#5CE7CRmm}+pM0+Rq6nG8_?{F?GH;;Nq#W^dA z_~7J7fB)E|+b(lz@cqRe1|x#J<)HCQ31Yd~S*O;+qO%}7ViINdL< z@RgJC1HtGMQJa2<-Z_ks1{*2po{*QPheb(!2=Z zsRO)O$UWGq*`ki;%}ov<`#LEN+cNI&ni_cyH__oqJyu(tJWmIg#{4@3ShVLN&YJLg zzU3?1O*$=mFNAtJ zPusl0D48U9v540YW|5Js@+`UQJ^rz4+moRcZ!l={*zVOj^3b-d!!1va=ywaX%Ab)sDYN&45I*L4A>k*q$$y6q)AmouDgggvhRcvGtgJA8Y zI_~62%tniM0%}#r6)MNf1@E0|9qldRpkm~9JTi7=e%Q(*~nZN z=c9usJQ(_A!t}e`i)-;b!3+a)y&ss#l|#skR<4S6D=0}9B_`mzqhnNWRjRYK%Flcu4aI~Gkd7?!FktKERuWqH zFo}*GVQSRxk;saZ#&neZ_g)PbGq0#blO4-H8+>2l$1e681|bE!y`q=cS7?0OEO zY(2v~h8H5odW7$f>)yA6_dfVOrI6ZvI7_=W+oA4GZs`taI{Ep|VMz7)q)G{lj!+*xfrgU{4!a5o{ zW+at15!z%Q(h9I{XtFq7UT1@hScgf4r{$rWh(+ka4gojN^eQiu0Y*tv3Y==n!VuGE zXV!q~&A4E=Z9aavzPr22nLXyfUIdH){ue8Y(UHA5UI#Ua8ZzI^l|YlO%EI8{IjxC! zdP?@8qD1CTwoz zQ!$ewY3iEh2BQW)?i*FGzPMDQOgCs(96?;yy*?obRN*F=ZUW$oL?z?k(5EFP5PB7Z zQ?4m&ee*3|I-kuHOR@m#hn@goY4mGFGLveIIkeufX!L|w80I}=m|90X{D5eT$=MQR zWXl*SJuft{gcQ;i&F#z8TvF-vGo(l6m7Q4aU|KZ$4R#ZE9`m3;Tlo0VVyJL81E)UNw%7*8OWrU6vTObvql;H zGY@b6j6I=I`^|#Ut-{{KyvTn5h6^;{p&oq zR~YT>!!alBIb$_hrZeuAprOJ9pZx%tzbJ^Oe;_F8vJ)@z8RDyYM*2_~$=o}IN?rw0 zTjq58W>gbeZ-;$((b|y#+@Zwxx0ROWhesv{_y+Q+Jxkm0a-Y)D5)?I{Z&4a4nYS|G zh7qI(MZ5<|-aa&hvk>wFX9IW|rF5TMHt8S+bJ)N|SSMTRc%9I0+^-k(5AP_*-X-Hb z)PtEQZRx%~Lc8UCLc3iSyq~o&R0{eEP<<~s0Yv?WgR#M}0#z#7sFy55c=;gSpvpD^ zJM1oxP)o=?E-zau;sr`_D=dal=nriQR6qALoHUSPva}0r?lp`@3}IQIDHOJk@9f8e zZiP`C+Ci2vB@uZ>I7YEfxQdNcVI79>ZpVq;c!M2I?u-nv)nR3YA=ussU%Dm$$VTz9 zDp85ZHa@tUDUvYGQ%^$$-!Z17el%UaW=d+q8jkZ=M8DvucQ`wyVl`&~6&KSK0sDpk zBUwzkD7oh3@bL3g+X z1Z`IkF$kL|DCtml3Cj`)fM6 ze-I3807$=5Bq<_*Cv~z(@Z#37G%^xOtF(>l@GRq+b**?kT^~G&KL*Aty~Qu1*(WBs z1nm|sQzA=*5NRj%MnowJP2mqJm8(Xp#fhd6rY+e@dBpd5vr0}W8O_UzPOx)W9`G0`c~>ApSiQ>wcqt=`>@ZE}HY&&i8uIsXB~&Er z)jO0KuM}h2)*Y+UCUYurrZ2soZp}Nh?XG>qr}4Z2>LpGt>KxE(mpq~DRyvCoeLk$W$ z5#u2!0XU3ZcZMeb`zI!Lj38FwOM5`$Mkz4DlQIEgW>;4KF3wR{5T$`kS`E^R4r3OEH2l^pJqOdQnchE$pK``4081BPPkc+dqalB&#n>5qA2QYKPe4KA| zk?UvhjQ|{1v@#VfGcs1hR=K=Cw=jeaCn=YereTcn&K! z;uf1^e;wPx{eiR;CaTv#v~#QQC=%usMwaTWM9A@>S*j!dx6VJb_jMt6njL+;Wzsz+A=P2s&c zcp^g7Jv278ObGF&%@Ww-t@kJ&Jz@aU_5OR<;B4GN$+ak|ORhtcz5Q6H*v^>8m0~lG z4{pa!8!m)p(Ug-jTG-(zjFbA}q+C@zf_H-La_@Mh;1uk>!O4k$N|%?!aLtP(^b%+~ zaZ&Jhs4OkptBI=$18@Ws6l~~pw6p>7brcd=uoALotPhiC)uZZYu!#G~VYOU08=Nk} z*aN5xyA)9^AP>SfEGv!=z#$HzV^JrV{h~%(XW2e6IReG85RM~S5N445cwQ#xgC2K? zE&xy(3{tjGUwO{cJvM5#f~+|edM77)!B!?<1EIkK!doa8WA|=tR@BQy1iMJO|EC!=iAS)2U5WSn*8ikQy8vYK$ z%+7mv!hOA;78wGFw~t0UJ`;ghrQlZ13ghrDaE>gzbRTXZm8(14R1y$xvWZ+|KMqtd z_)vp_kKTz(a^RV8a2wABzOO9OD`?m6+n#PbqyI$VvDE;}9vZ`5%XUUH-MFZWShp!r7~0)CiheIB9}YS8o@rW<$jR6Z=XT&$@n8dX z1=x?H@_YO5-8q62g;EReDb_aO>K|SU7i`93Z|(1|Bp3!4mvN_de{ff87aqV~kC&iF ziV08!+{i*f#+??RM$G6;nWDQ*O=xr3kffoco+6nskxUJ=1GyB%;DT=z$0g?S*t6u1R0@99mfg~GrxGzG4nLf2wI zKRSZ(U`Qs*Dz`Y=!Lf)h>k$DZIzPnvQ39!NVedqQ2)!fH^VN6a>>3>%u&j2)^7muV zzsf}VL(iLe^L*V+oIUH`kjxhmVcg`J#?7lS#P{#Gspy_coS1ZpBiw)-#P7lB{z1G( z%w1K_+oAhLM)3sR=ZCTXhu~6chn}}90>%(vmm9D*M)y?@yVbl@*@_(k4q*d_$Bz{? zvU_X{TU5PRCy&y`Com&cg1#Zs7*55G-F*>>C@zBfC;PGKq}g3-#k>&?^7w3wx7A|9 z%dCaDF(T2bW75%LZ_HYCtcRUa9nn=#SqoC&(;`J?>EJ^-0pHY32s zF`p=1D(31kK7q^;Vqjtl&55Z@!t~G+dhzH_ac7iX>Wh9l)%B0vjBP6Huoens>r;?zVij5`59a4$Q~y>a*T${#EhmfzY?zwC335pT>7`lc{t@zPAo>}u%oihIES`WdLjhxs0-BnV zmFbxT<32CMw?+ktz2WUcNoklGtANnwq8#WSST&iz?w<-P)P?1ki*vubP?)50@zkB- zM;gaso99xMBKij7La?o=$>bMThtRDv_ee85pmQ$g47Y?KLSGU-0!yGc?v>$uWB9Tl z25Kd7n8lHc5~hX-;G5T|*juLI8U{5sPY`?8K8y&ZX0*DgHpkq2rXob`?BgH_)Q zAIkkpP&L(V%hhITSs(uK^V))-=2d*JuAP6N`hltk!*ApcI?C+bwGc$(zoNTD4^ariWS)@0Dm!_+1SCDSXUbNkp zt@z=k+O8t|qI**Ki@+ZjzJgzsU6ric-ep0}b1}Xrd#A(KA&sA9%OUS<)@?!30-9aF5k5}E;=?btJK?RrsXjntn0p6&k>d7Nz)>g4hjglwe`@+sl)=1dKBtgA*Q8td zVfNByDhK7v8v={4XQM25H@r1j4_F06*!E8SS2@@je`(rL3u7yqs4 z+mLSSr|H8p@Hv!9uk+=eLVAzzpW{Y>rrKo#vuo!x!Tu}B`U+&N`Fv1ATUJ>~$Ml6r zrwvugS2HUJ76ETJ;3Pg4?O+TJW*ZN#Uy4ouFUIN_d@=F^l-Qq7K>6QVuWh1|X zfDfSn#1RKF_sy1gfbB)xye2m`YK)Ox?R6~3V4+d)UuQd5tSLUy432M$rx*H?>5Fuj(@vi}YD8?^RyyZJBc<1-)@SFKYTZ5W| zF5SfqrzuelyG%l+#g0bC4C>eFjqn2a=(oYE0s2uG$pLMHZAtv1+g<-$?fU;O;tE+#>*8jU}f*QD;NOvy) zrtZ@EVS8$Mtb*E^(!H3?;wOTiYt({Sx1I&a^T24*3IVwPmJZ)RB?sEl$ zu|#B!MSL5(F|R>h<=Xow3@nEu_u?B~h{KgAx@R!L{|&bB=GORyJ|7r!L&c$p0lsswq7lB_p8t%Xr#8;?zYr;0N{{TC1tpPgLm9+eHK;~9k z*X-j$_irz_x{>bS7lRs_B+DfH7-0TZ_({Om0A@Xu?-KlmuDi7_DlL*_>|(npE&bU{ z?LxY`kK-SF*uJ2PV%$pUEJxE>#eZ&?vXcLEsPo=f9yD`7hIhpS6;#64AzkG=g5Qb0 zIDc={7nO!}usqL59^=P)YUi+y)|Lt9*&z6^trcFj)y04c6JLiv>X`I-;O!cerUMF^VsF17)i&avCt2IYJk`DyRU4?jgm7OqR- zX`2?GhI>+Y>YX&INB%Z#mEgs?Sl(7AK$Xds#@D6ttKZVHt!`LOx~*4HVfZi~@fIdZ z;l=o^ZK3H4zNG6galaz{Fw$)-pnUfsU3EvgBY=rhJbub=5p*M#bj{{$LB)7ATT+*Ysuht?+r% z*2KS_g0H0Dd3Pf&L4GZ#2k>H7PP8Vb<jZQ*b+Al?OkANAZ`Ilj#i~Al;VJ1A5Ds{XzL!I?7|| z7R*p@`j$%h)AG+$j%`1%lKQ9~DNov-UI3%Ly*jVQ92zu~lj$dCNWU~g`kcO?rXG29 z4@CKV0qL|$O{W~>&(B^INdHTC9CQ!iH-h1>SI4UX(ymHR^H0}<@PSWa-i7>)_|0+& zFYDKJjkz1u-!L6_q(^f~!uJ5?{7CuW`8HV_QWz*1-xS`P!XE%!XYwBhtaDcKe>w%9 z0<2>Q@%)7NQ~rc)e!`TWdLsR+$bTb#!%p1VL|v!sNl>N4UjaTZ_7%@PG;imiwnY?! zEZSH*C*r;DeekE=2mjjp;O7oqy?j(5aJEuezW=ZBs~~>^glMXb<;xrW;c0Ad>oMNy z_xStZUwt2Zxc%z zodK`><_){}NBM07?Ak~9cRL-{0jKhwtwguAcAl0C zbilRV3j2SJ+25XBy8xS;b)ZpxZv8CPcE3|Q&)Ug5pikS0wMiY5lxGNfi?5{fG~U{) zvpZ@3tMchF<(w;GzX0`Co$i}ddyDL#skSqFpL7o7tHU4V-B;3eugEVpZuWZ=O0#GR zYrvrQc7d4TEEeOOd`bg!a1wvU|97JKqP;YhbvO7>zB>F7J^=U(ew#dv*=CnX_205H zsJTICv_Gs9zh(6`9OEU%(ROJ00O{8D&q057o@UE>#UJZL zco=m$gx_u4qq^6vZ)3i4mid()>XEuATm#tpFim$lPx@rb2g?d#LrSmy*vd({PC~A? zA(zvo*usOE9WQffUgRcz>n`29_xOn<{ygw`k<;V*lK8saDSU4dKb6M&{A?qZe-3yT z-$8F1+&Z)3KoZbKWh{9hvxR~y?q|riNN~v4^}+L1;z`|7mTRZoUZKLI)qYOA!n7fU zhw$5vbSzG|JL@Qttft;Z$H~!u1@i~f###$EuD>_l;5=}dzfE=|32`kWbOACpw3pu=QQuB4gTWn zUtYl307G*Mznhb5BiXe=_%gS9qCPwgIh_6Y@u}#>A6tj}K=1cTciH;AiM+R^;)4Z7 zhDY(+`-TTI+10|>@;xv3*f%toyqp&_+kGvbLc;!Lwi6P_#^zx#C|(#1;TXSu$vS*a}YTl;@O_`9(~%SBSqg+HH_8(U?Zt*6jnA^FJx&#=5dHos~8y&%?UdG0@7pAU88^ekz}qwH5MKlJB{FLCt>& z^06KKnP^#Sw)K7dD*8J)gZ_S+%42PNFPwFH{$tBa>t1z88QqxZ+RLWzlk&>bkIaz% zs7beFpOf_1RxIv~tKi0g~8y~Cul zjg-$7Nss2J;(rv!ajH@o&fa1lp!B;Ouf&;t#WkkvUenK}@>tmxOIycwU~w;{@>w1H zmnff=onu_uSE@cHuYx;#72Ja<9Q%y&WV^^*cf!qen_-S02LGt$pDxe8?Q3pbvem6S zW9)5-#$GL-a?5!2K<3Mw7cMli9T(na{U>{ebQV1)qC6yz$;bGzmGk$_ZtRWv*8ce1 zs^*;wTG(-P7E;sGeXtT;*7H;TVG0K8Xir4>eg5DK@jnkoy(!N( z;WI3J4RBhI8ni>=Y%g$@mi~Z$$}5lG)&?}4ZEopS&Oj&q#qita=%~X{>d=-P#X?>y*?yohfH{tA9uUt?)W zr?mJfXK~iDPpyy3B_Dp6kAG=723Fu~-U0W#1o4FVc>;fx=pXfX?R$iKke~fq+lTGJ z^u0*0GwJ-T`CpavXxwV5U6tL!%?|2aX$}dEj8jdujnmOyq~f`SqTH>5ORnot zSDLrR#Tn7OK+AmxdE0?YpHbF2t$NU%Wzcce@=VL4xC6*@ASJ8fkR0SwxW#}~&QpR* z)MIsRT~%jI)rMKww(8F64Yl)Cc8~^@>aF;iZ&cPxx}90qy^XL1&{Iy^u1w#HbjD4Z zP8y~kkLZ(QK5;Kpz-c+JMmQIfP#)&tC&XV`KEew=7X)u1-)xU3{0qR>8hFmZc)y+a zd4O4_=3kV8R|2;D+5od}EB!XW^f#<8`4s{0#c%2Bqi$?f+P8qK1CD>Bo%2oI|MPw% z+df-72@cb1o|B+iW%9fQcqQP~?9;2!r|}@wflLR+*I1@S55?!MSk5ZIHzJS9IOJjY zkjT~*cjzj(XMwv1e5~(bA7>d0{-r)6x#;V&%b(_q>hl)p+L1@=ho1rUtK~Nw3ToN_ z+cIdYEaN`l*e}xkQ1e~@p021;y~5wdd7%{F#h&k8;5sm$opB$ol$l+-aP>#)JpH-D z?)*MF-GQ11W<6N_jjDs;H**g~&ow~S_r9fmI?+$XAF(d)KH~Oi(sj|gKL72Y=7%V6 zCj8+?gPQw+uQZ1w|JvWxXR6|Ur}BRWIL^@_f7vsgs>{`n1vPgG|JX(}|54x`5u9Jo zf)HQv`%)_ZlHb!k)nxsZ|6br3@7cD}yw3x7x8N%0oqt51mnoO+3E;LR`QkZTxAsH- zMBN0xkM({GRu%R$x8V>nw=?A&B5CXYtDxqh=&Ir~%8l9YiD^Xiv;P(Rf$*Mz{w_yf zr?TMN%@d=#K${z6iW$iZ8pdKRdIo1M_Um{=`vPaCw7S@*Tz5>LF}D0R3P08Fv!MA5 z^7!!zP0%X);o2WA0sqv@by&8=RUz_YU==(p{33g(Tc5HA($H7LW#S=IJmOS`G-(rj zm+QejZ=f{$pVVWIt482b_?w|Gw`cM2EV^>k4@rL#e|8Td+g&?H{o2bY z6Rs6_GoNXyJ(%fm`{=gZzM1W0800KAp|cx7Z^}KA@ei_Do`GplPCANc44 zvmgA(H);;f`eyY*RS$iWFpIRKhE{Ar#?@!PK- zf0>>^&k|5prFjUyB`(Rwaf#yY1J2T(6xw*~pq`XA$i#ZG>BEx8#cMYG8Ix}7zYx!kEj|qsXYuUwSA&BnTQ1Ti zX&UgS_GsCb|m<7YHxBFf`SY&cRL%xuC7LN3@LQf$nYTZg-d$1+cI4m4cLs2Bq^*DlNMlCYtbFV|sx$oG{H=h@NED&}daJ(9`(j$}&f zgZh3Hoe1w^@b4Um;?A-OZY9&UI8tCr}5-9XAR1&(Q!L2 zx6b1_f#XWVNlq-dHk}xp5*s7^1nVOJ{v{&Z3A07q5oKT2i8bF=FSDD zV!^QsE*2}(C-ZGZzG39ML3CDm9#0!1-Jx2nUx~ex+2Lwf7#`QITm4ZS?8U!jWwB1@ zz+>*mVjvNg-|IB3#yb}IwXFh&DK)9uS?Ig%Zz^s3#%{G8s?U1;Y1onJdbf(-q{lZs96p&Ww2dO=kN*<(AE6-5 zeln11e~5DThYyCCyYSCLVeY=K9>W)ZWccF<5l@F__;n_HDa=hF`K9nc72pF^2djka zVAWGqVDnVfiK^U}k^cmK06tN55-{jbR=q*^7gbk45B!np6V=FnqWbA-;rCqiOYX-@ z)n}_S`S2{izKE|MS4;jMSO2UUZSb?|D@?vpeQ*|XADnfRIy*Y+=~+Vb^sHwIKRfGr zz+XM)mE!6fUe3K*mDwD=T6M7sj4oDPCiIJ{$7kW|aWd)zBeeHs$wobe4~LJ0)%OKo z4i+54FX$nU4DVKH(z{hhAZmbM&y|Ec{LK$a`!3b`T__5SUkNYq>#?e%Ec+;Q^O0hZ zTXqs|_E>nj>H<@LtQrE-FS?3$qK1z`Ff^oXxA3{}P*rtq5wah{uQ%|UtfM%w)R4 ziGNguU8LU>-nJ5=tpq*fCViKqH{u6#P}@1zXEu7ta^8d7 z2DVhAwfC_4df4^#D?of(3x2f>W~XYx{balujK7f~_+;idz@$J!_o8O^LJV}T%pq3u z5UK78k7rI0I>AbyMdcH=fROwi<=1hdlwH`-gDUg@zr|H#OVEovNmm=rnOn6hsK4=8 zIQM$gd&w%amRLIMUBAOQ*U%iUnGZ$Izb-cg=W*Tj_`Rf_$@Pu+*?5~IL*x12MdV8r z5ByM;^3kq*($xVjGVcN%T3Nb7OvX_v7m~suvp|j zQ$jkm7r&*5E)}*~IEQG2YLVrbw8Y0S0=kxfc&x*diVg}8Khc7aDs0~Y)$MqMz2gzq z0M0aX4t-phQ*KghAO-uZwy}_I5K@!u@WjoV$Ayq|7^2K;a)B0ZP+5z~Hzx-t}__=;2Z zaJqA#fH}9(W&IX@{Z@NI45BxLbFM?RuM@|tjSR=RAzayRJZm`bM&!ToH*zI7i_a{^ z@5M`UMFa%U!S(eZ+*al!A}OLDVekoL{6qu9X}A@?Zf&%qL1Pcnd%lSDFK)HzTc2X@ zdP;revxJ__{0W=(Pckp0Vp&%f3)&EV;;Dq?3Wp7_5tql;HE^AY`NDY(&_u(n*~uVm z?848j-*HBTB00vW4*+GOj4Z35|5aav32ns~(1i!@A!!#1fNWg5PJYO;JKQ>neT$EKPS~UqTo(qPmT3rbC8pkbOh= zoy_Hg4lZZjW%9e3_iVDd)}+7@6b7}ZR_(mpB-(!74RfMMdpS(=hQ+`wZh+%%Xw2;e zLEA7Ao?=DvsK|Gv*M#5AoX%8D2EPTrbdjBNYsk(i^gqx1f?E3pCEF^JLD{jYRSF8x z2_Zl;?}m>RgGdO3dp9fsYSA)iuJKix#jA|Cx)DsF2#yIqM|II*bLvCXljt}4$!ut4 z_B>>oH(yMA{tftjgQ#_7?q2X%>Gk=lRUAr!i`f7d^F~If-hjRV|9l2DqcTv=;&b<~Yy7rS0^OJR^pLs=x0Vf639|8I!b1j;yEJ;o-M;Lq@ z89u%a!^paB{OZ2THaAP|V&*(E zcOf%=p};O*pq~y(mheV#IBhPtR7GEV1Ejm*Gw}YOS#|AHaLuYa7v8WtxON`DZ(5WI zuKi`$^BthMV;!QfJ29kJ(twr8{>A|FIK$}2b4NpH=VuiJBt64n?-?e!&=N@q-!aHB$wl8tdODZ=Rsg9_%))p2qZ)jf z@^1()hmTj`YkxJQ+5iEb;n%6^GyFPJ{c<(Rd%5}op|`8wc3+2Ph4%)(ia2G~Vb1ao zV-khv6XobIAHEwtQ3XpT)9fnDcggkc@V)B8v$D4xlMI==MXvBn?jr^$qkO6b-+#Yzrv(=XfU#fn?!EaQ*N%+lbOpd{jljAKeP%t4PcgeJNAzv8CtM`wM9 z^I<9b$GM;8I0g7=4oep{U&TUh8S-ffZUgi-_2p`Eli3y}+xBrB}5;W?P zUFea!?q~1UK7BvDQyzZvG6sgBV_7YsP4Apl%>ReEd*`6?-Uy7_=Ml?&BPD9>+9H28iSG1I>0k^T))$oVg(6 zKcGAB!Ps;~z$@aj!w0jFIi943Ej?u2vkR2>?<4&Y=!CXR`$HK015DgWagp3MVy=8h zu-F|)xf2dUo#E^{D5P#-+GU2pFF~WfBXYIzhh7PyWHCqRxu=d5H9#E zC_anmF>JpRzwYcXRS7%9UE2W96hVXRm&sfx-wYo!r#xn0vIFsE7^;LFJ^!2;0JTR$JLE2{=?k} z59hKwgYdcB>0EY-oWqB6&*riXP>K8L9BL*!k~>bRjsvR>HK5Sh(9{xBz;M@@Om%Kw z5Mc6{6Nnb!e}S$0r4(T`7HNKj3~x$?Y6oVQ9}D#7=c1oVR8x)M|DkMkt~0|zW;-xj zAOBn({Zt}Me-efg=^i1_eAHq-Vu_82CH^!6;7>EpOR(ctio@qQ6@r(|oF~zF#uUbhm8VVi{O7({n%cFF6uA^EkB%v63X34et_dv)ix!wugK!}g~#)$kty zRy3ZCb0>p4If9XAg#&elR={YWj)r z*(yzc7LH%j>HU3rQe=^Oes$Nk!){1D-$|VnsV`(S`GS{%>F2YDbDDlQ=SpMxvsK@% z()928(vU8tg~3x9db_7GFH}_+l@k($)$`%w=0C}>`YAXx0GCiap!3s%HsNGC&k6vsIcnQD6{O*P(+wgwF3!yzCk%NOFgd$w+wF&X#Mh;;ckRnqJwu*4-purFE1$%}0uiDrRBS_GgU zz!(704gg)w9OYQ^{VbG_hkQS0zda032ABPI?m&pD(E^ZoB7Cq4BqD8((@frJrpIXp zOAXXa4^)Df0L4-zZoEng$`L89RQxNPvl!ld@hXI#Ph~K_+<+-9B;N$dpC|Nu<_CnN z0-I3*sB}a42B#I&?0Xz}59biSpmMo=Ttz<^9%3MND14mpuE`4IU7K>v2aEB~fCHMV#j( z`piBnHn)*S^Rg<0IYlCmpCU8iE8)H>JnFn^;jZAGg9YvI9fT&; zHFfuLS>zBm5H{eS{Z&YsWRf%)Dh^}TB(Z2LrNW{$N$Rf4s#->Pgq7`r>R~h+pk>5B z8yv$8uJN&WK&7Fr*b$tRVf_(KxAs?|FS%%x{K6Hx& z9;(tbEtvGT<-s<;4Heu5eu$(=zFEkPI>LMQvpM#2iL@I_q>mCJOIg9B+W84rtg7CP zx4(btSlHePy3YLU-O%q;ugx6IEq0d69K-tMEUcz@X=UN)PXh z+8yN_&YhuDXOL6dM!Z4& z2@lVh7wcHuGw*h^opKz3EFsWiOnyA~48NX1$O`=kr$j3eQN0I2K5Y98b{)|!=Q-H< zam^2C`2eS<&Xd(xP&qg&d*2)=Liw{9#K*5>!XF~2N0j~(pwA*~4qwUqkT4Q| zg3z5ao>STIS#(oO`(Mmr%JX6_2!E8j#1em!gNeVL3-;M!mpqn%e|iY@KZP+FgVaGb z#L+5gE@>=}`C0Z*4lN2!2M`-r^d+=!_>sSUXK6W?W_gfh5P~TS#>Nb-0$ZQOHo=s zF8Gcvo%WZ@LwFQ?#nDfm}X@U^N@Ne_d6_{UG+SG(6I z<8r#0Z3ey`@LdM}EZ|84^Hmt*2L4UJM+{8<7RGVHV4uPJqhd&f6NfwuK#zKS2J$dJ zzI@1$4ekM$@i1o*#z1p`YX)l zKia-LKkSm6zRnn!^6|W|#l!F-nD0i_kMiTWU`x*vLJrP}Ja1PkjP|RPALnds{&oXj zUxA)yc$NOs74ST_t9a@oZ@YIi-?e+Y~zXRuX z1w;le`>ro#*?1+{t7uL7J_~Q;MXO$>rV?l5#veEdw`Xm z&kfuHc%k9{1%oGjyMbB1&iQeE;(33t@@oOVEr9Frt@1u&@T7m%z~nc4U7VkI-Z`xN z?gXDbfa{Q;{03J8i(r*I&?*nc(<)2v)<4OOTf%`%CzX0Yqq5MyLDoM{fiIsm5 z^nU{Q6+=ILeT*l6-c79ZUjh9CfGvIduf}-N^NwPrN5CFz1Z?T&*Ts0!FEsG)f&SM4 zA4R&#f70Mdf5yPaLI3A~j~M!vUrX}mUB*BQ#lHdl7QlxDa`yD9!IMAlHYPPCcoFpf zYl?o`4KbeWt??!!GUn&q$IQ+Ae}(+_0_I)FTA#}cV?6137qXCp;(rGHR{$3!x0COn z!IS=B1GD_s4NN@mP{tQNF8{j*CjLDGGk?RUV|wCw&oaL7$p(K5d0GMU-er}4?q^~= z>3OHJkb{CS?^ITp{12z#vrjAD>5F$QTl(_`CO_V}Z1M9x8^gr&-ersLF);DGf7#*> z8JKw9$87QE3`{)lXI4C6-p{P?{|3GMPk_%MLG^QZaf~ND?`u|i>hWIzX56XtR}7x? zyuVrLt6(=D0esl_vjaHOMqoIG>;7QLr zpYerHHn;`!{}*5@|2Ev|ta#G%4rql}gMP%{39a(HV(_HDXy8uJ|25#_NLTu)Wida} z^NwicPy1T5Jcfzq9nltFtdC*hj~JNwkKdfczhhwHU%w@ZZ&?w;#9wKQVe;?%TnrN* z{$>(BgS|&2<>2L@(;J7QqsdEdItf6~Cj^WJrff5E`S z^B#1?6XxCL3bVYqD`R-9g8aPyTP8`B~mp z0~62t(iKmb_oQ2x_oG{w_o6FIe&-C#{O1i!eE9h!{lH0ubHQ&{s4wqOxBTZDnEZK{ zy2WD|q|U+4ABG10-3t79*SgKW(!ftupy!?IO3(6n=emV?=emV?=emV?=emV?=emV? z=emV?=emV?=emV?*Sf;g@34U>AMaeZ_(u&)Jnvq&`11xPo_DY-o-prVSD583{6Y*9 z&%4+aPndVHD@^(x0~60X*)4vbfr;lG?H2!}frsH77{-lC^@P2oY;p6;E-oWI?d)@`@@g2=EOg!&$xA?g&F-$z~YPb0F z1}2_&wOjnw))*$9cd}djn+E<~h5GQ`b*29gSR($9fE(aYG@h!vJ;swi?_pPZ>T9oo ziRb<57JsxohKc7L>lT06z{K;;b;T3r-R2hN-R2hNo#hrjlY(DL!Mt}|=_&uYju`%% z3i{za*h-JRqUfXJ4ezN|Jo$C3k73H6H?Y{(h9rKWfr&q3VCLtY)A+*2+1tWs%iPVM zc*nHGuQD+6^Ui6D-)dmudH1x%?=>*S?&zcSmAj)Q)yXrwDb7!RqXuSu4)!GRj~bZx zeOqGuuU0D0;7LFI#h9Mu@!n>9;p6nddz&rHdz%$*sKB3h94nsu7j2DUo=4Y@)}Qwa zyR>Z32mErt3z4AxrNiJUAMYDh`Zv(8HUhTmX}nKZ@htz8ftjE83tRlF1}2{O3|stV z0~61Cge`vlmtuHlh5GTXTuZ;zz~sj}a}`gRcjYQf`41bIc;20B@lP0-c;1O?@#j)7 z4ms30{47}?$EA@Tt_dEfAV2SOwfrs_nC0<)SBrn!z{K;uSBsx>cMKEH`(G`-!@$Jz zK3I#NHZbwL|JCAOFT}8vZ(! zdrB4m?}7iD6rT5$D*jF2KL)rS3Cf@MmMZ=|;C~CSEuZ(5D*oec3spevPrQ#*@izkh zp8(tSg+=`_p7r5^VV2LkMioz(cZ*t>cZphRc*4AE)55%4 z)55$<)55$P)55%~Qel>N+Q8(`yDJq>n0HlLn0Heu%=|qDCOz+}wD`jYCZ2auTKwXX z7$%-~Q7WD=@10bb<()Aw@w|sp@r{-2)!^@>y#hXi4C?=%yC=?1esb5NFw6#w%2 z`}j)mJ7W4?;sLMo{D|irkCGiFlz^WF*y4G|qv9U~ej{LA&trbx)u?#Z_w0BK6EAl& z3V|EX&lXd712g~L$s~TCf!jYB1YaX;>bI{H(=$I#Nk;OpeBLK0#e09ndjT!XdjS<@ z{#83;nE81ppyD4z{q>{%h4Bc$UXI z>=b5uTr@E8ucct#GpF>#^WHKG^WHHF^WHHF^WHEE^WHBDU!Q_`=au3q-_b9}Fw5t? zSBfXh`>ZU?d!-a+{!0cXJ@1aP_?oZ8F!8+0N%4f`ZYD`^{j>3_DSQg%T}7Io@E-%r3_9NMUIWelQ{aCE@H~U(JqL>a-+}*)6rT4UDE|Kh{_}vXe7pxi z@i`pXyd5ylDQfw=7eVnK1-=)s9nW}Ag5rM}_gtf5K{o39 zErY)S_`e5Cyv7$b-;DW_o_8(a3!iN8SL_Bvtkr02a0_`)X}G=Tn(0k0Cs zx39sAJO=(e}vH{N81-}7!zCf=1d1r&5f$s*s3Gj^u&pR9x ze>d>kQ}{y$za9ABPT_f%gXS*+|K9?>$MdKD=No@Vd3nEs(tic?p91`fp?}@rzX|+d zKcqfF?zYO}X0PcX_QTsZ4IL7|~_~&4sn6`_3 zUIcs!FpeEW_WFdOCx6}{q5S^_^xp%#;{R^!T%aVY%6or!IXy^V1|f+kFyasc!Z_XY zB!Y{cs_L1N?&+THnpXlIs=H2ims2n5G1H@tf&xMkALOMjf-w>l3WwcFjbbjBsPTHQUX~j4dVl}@sI$+R$y%wky6gP+6uF>l~?{UwVIp&;K6z&w!5y`FekZ&wrZykAlA($rKL1p%?gGCy$k+QLeEvCH zodbS;kgs=0`1}jFdNKHy1OD~?2%rB#t_om1KjQhs3HJ6yi>;q5`b#!K&&@a2{N z(*P@9@09TQ!g_B+i1l8G5bHe+A=Wz?LacW%gjnxB2(jKv;Ia78e6!fb1G1ME+xvUc z#}G?jJ-*S^6!!k1+`^FI{OYo3JOzvs%Y|C6--Vaoq4_5J)& ze}palk?8i5(9`ek`}XhVY71C?*6Wvki`(am-nsXsSp5HDfR%qmfR+EU04x9c9RBKi zQhLh&9|2bVv)-G{e=xwx*KdOJ#mCxv{U&&b^?ThR{+|I>d-Z@H(R*cpmH$MJpKk^D z&m3jZ_v7u)_j`Wse_z`E2TxM|T|vIue=xw0=E{p7KI_bX;^j}AB>(1N{z&xSPLls< za9+pKvH!*YmnpyQ{hr@vMNfhKd4HY%|BnnlBYO7g@O-vJkb{`@qTe-@7jh5cC%J|9A&r~Yi#BShEo$7c=t zRRr&Wp2kD@m0bO0@Y}fmb(YJ2RWAQd@GqQcfB#$c@5<%B7kn}MC$Dnj^AYgxFWdN3 z<^KWf^;`UW5quT$@a_E@csl6skHDwAKGnZ96dVuopAUW<`O2S*{!76Ay!#p~!b`!S ze5P~wM({e$C&^w*{>$J?_e3N2J9;;Rbv|j*<=+ne*{YP^H-n!XPv^sf;A7~om+x_K z*#5tOKg9g^?fnq^u7Lhez?U(9HoErD;1RE|{`0{%(f`dZe+&3eX^&-%>Hki!&ZBvK zng!p>cxt{$K6gN0_Q$uMknhhQuOYtyz8;ZK9DNyyy5L(H_WZc&-wM9-Wt@Me0pYiU zzYagx6oVfIe~|WGc5NylFdon=^ug}$gM-IOq{N!2b{CET`e`D?Gs_0|jpTTd%jn@~z z2X9U7|386s-qFkZ8{jhXlYUEHKLG1|;H`$gk?2R@u)k+AkRiSZJW6|h{#=&J9|tGM zSNbaYQ{ei*p7$3%2=?Qt`LP7P6Mbh`O!*ZspLP1ThWOxh;IRF-fIp@CElwZb4L-*B zJu1xjJp|TyRrOE9`WX1RT&xGH{ZD{@@^YSMaq{|S@GoI+RbJ!u40x3J>HBw%9`S@8 z)85d7R&*!vBxgDey4sRl^@7s9vt@P)j9lIVBL@R zV;iH9M;!h8a^*h^*8Z6<|0wutw11J~_mkkKvG2d?>OT&?3VY%4Q(&Dx_4U6CzHDb| zPks#c&#%cJJPSh@@_!My{06%oRsXL5V{=DpuDxyG)vHqbRt6_8w)fLieij_kn+LxM z{?@zthrr*v*X|Ff{7t#?cYy!y-S)j~%D*d@e=qnR7mq6cfn5G$;D@n)47(Zs&x3WI z*pJ`ix$@ry>pZZR*Z0Bxd1UGH)8I1gZFlre;}PI@aQ{OD)&4IElkfHI@*I9Ccn|T^ zTV4P6fX@o_?>BPgd*Ht*+x-I3za3m*{#gE2MR$RpfZmv+_a1N^`=tFtm466)Gv&9# zpXSRW;8(N$c#q5fJa{$ngO5kQ27VLcK^vz2_rafqo}cfhpNGFoQvYxvIPCA0V4XMK zMSZom3HN&s|K|1a0Qq{p!TW=G@IB0ThRw|P!(f($L-`&9e|8Vg*Esrjfqx(Sx!(2X&%g=# z=;eJJtmi2_{l5c;{C^{dzpwiE7f!BC3lN zf0ccwmH7WQxI}+^d(VJxq(9!ioyqx*(NWrCU8?fufW!X12z(jmHMTl_Hi4`7M;RcM zzXtp~=J(qjE`o3ArR%Q>IHb1(e(q~heOLis7w~s0_z{i+h>%fxdzku~TjMty1z`FnE@pr%>f6su|2J4ISxRIpii4d*`7QbE1c&tZfgcFsf$PC~{!99z`LhIm{PNTuw!zJk-47PM zo55d4-g+ml@Ezdi1@d?w_!Fn5^80h}#{&KON3fnx^8NoNSkL?1;o5%+To2-(?}PPx zmGA$L!55<6vY(Rg8PCi1?>umw`0Em&UIN}yPyOi*@Ga0oEe*Zh;80%6 z;4|?5etz5n4%b_6$(8@39DWFV8~S@3`jXdY!9Rgz?dAwL&^ z-$1tNR6L;2nWu5!NNU5?+kfxi^!;{)J_ z1Aada{&=A8{|FBG{SNpj^R46P{SM#Ed{Oo&(FWmh3-{2cwmyXY=F#ZDi zf85dkC2)!L<0THi7#zy?YOwA%`1v~y9%sC~eD~+d*TMG%<9Q7H#3cH}gp_>V0zTy( z_MPCue~_#He(+=T$IJ6W;2VPR|1_A7i4WH@K3@UH=>K}h|98N*v0q2bVcI+WV(q*8 zcxY9$7993(Jvd>$)?EFq;I{_j`!aB7Z+3z|MfnY`{6TO??v`L74xhdqTI z!_VE|(7!(bzJ~Epwpll-wLi0-~0LShv2WH?}*FT`;X%o5s_WIcbe*u0p z9^&uSV7AqU;~Dk()oy>#iF^I#rm@9sTeq#OY-sC<>}0#$DYQFBi`9O$+^XAziF%{) z>q)mg-|I!?)?%IXBv#32eJxt(_Iv%o;^KydD2_|J;)&VusZzY7w6nZBj-y)AO_u7t ze$tKm&3K{FZY4d+)!Ok=qdi}3#I=6A+l#A%m1v>e>@<>oQrj?k@)EIHj;q~n^=O>5 z`rV_^Vz=5%;@Y6uJc>PjWwOxUu#vh!ax7*ub$Xp{z10`H`X#$7dxsZ?2`WoEKS0+@ zbdhwst+o=XjYfN+%T;f_dnm3p>PxMpM(atUM9MeYhZC;!qjquiO8tV}auFjXzD;bSDczEjPeziHNd14r^fAdF;U^TU+o== zX3E95&_>MdMuX9-B+X7Vy|)tgyY;1|q#I4mEEnTSG}mu;;!1gHbfYNkoGDKa$1Y1I|bqJu876YWk0NcW1u8#T;cd95tFWQ;(Fr z_RfvZRz~B!{2!*7z6_DFwhs|`88DjCCChbozSoIs-TGmK)~jh4YjLgKJ5-k@A@ss> zvT$gwU+oWi2(Q|Y7OVZm9(m?F?lgeyZc`QQ0^6ze^oG?!4`>Ov|W zvCxqrNR!lDzb>Uf&*EuKU)XA6i zHV!kPSNx7@Gl@zog~R%@YY`1Cp2ny9c63M^#>jfE*c(E7Z4r}q@ zc4GjciE4kM7ftl)wTN+xu_cD8zH4?IP%NDb#vz0<8x6s+bA4&YJoO#b zUJ}diN7loqCAvv}t{Ap8nzp6d0T-i&0hq<$WICsEC-{zB4$W!+$4R(qbXRVc z0l*`eIZ>J285gFfOz=tQm9~zZ>DTIQG2M^R{~GaYq$W2ThWvypPC$Azo|q&83~C#d z+&g1q+Aw3th~(aG^-uvZ6Pp<*(VCI2w3n6|W~gJBb8aSb%)fcXARx# zN}$?RE!xdBEa$(F>Pr!%WPb4FZ3Hx+RKdfv7I5X zQ3O&b7o#0>D4<&s;Dwzg8E2f1+pw3$Vg)oB#iWOok&sykOcqDu+R%X6VkStk0wYvf zTx$1O4w+y2HnNc=oWavfw7b|fde^JBTWCmyu`lf|vXUf_pBS%9%-LW(9-bluZ=739IX%+=O_V35rIg+*WCVx)kD~vX<|bzLhD}LI#iUU^ zs-Vw|Qdic37^cwfCPtdkbY*9}YcAe@9its6pD`kHg;JPi-3iZA%G{V~J=8?TPs%tN zO|=KDKI6x)ejxw7J;JuE)m!e>Mx)6JQqJm$na;TeEqODa&l`)cTcEs_(E^=%2&33AEiN6TOs~s&UP6qV$|1`=_@#C z)_YP@VyBx134x#0F*EIq71=R+op`w_9L-_@TN{kH9agU&G7ZjiN6yk_G;Q9xWjat9 zw>IVAT%}yN&euVT3SFFzSEjcPrDTTF8*(#1q20|Gn_&=c>)=zh{ei^e*lcL11sg#{ z#y-TA1JT@gHoAe4Bl3B6v;r%XX=yPYw20sjSvsuf10$|hBm+6sj0~Km(z*=i&VE!o zQtTMdbK=hMlWC$dy)B9pnP6rLakh8Y(h(cT3>Q)~rm3A#O~n}5fWqmQ3xd>exneAy z*@Os%n&Db{DI*tj(GI=V$7YmLjdmA* zV3W@3yeVvr(Puw?8^X{7;%@@ zHzq_h28}%dRsr)znG4R&`2b{5`=Nvp#QK>CHE-TGMdQ1|wZUAH95RuFAw8VoMjWmQ zH#rJ;1fw@*(%4<{TS)^N@hXS9eEixR6*MW;tf%Ln~CyX`>-y-XuO=kCTLTxn-?Yp5@54WrzZ=bR@~Sw;U_4uzn%-B6v@Fd>7RL7nJ=U_cy{JtI zzfnN!mPCa?m)!!h@GMn!oj?VT;`vdZ7+wV>IP_w90@E4FZ@7Lkt0$F~`7`@yLuc%w zOcxxfpp9>4vd+W>OQjiR`0lU`FIN`=h`?NX&|OFrTGESXDrrttTSP-cyDy8ikan`E z&5*!`oS@@4GBbpH<27Z`SeUcT;U}{)<%i^|M)8CvV^7A)64_T6GNQiEV7QT?I$dmw zm3Z#p+;9WIhB(qB_VEkVj$jyFi;&c!J=h#f4kZ@ zW@!+2ZP%nP;@l{$^gEakvGWVuhH7f*VfUHhPG9}d64dy${%q11uhk4c<<^2B6sV_e zkOVZHezI)a0V9XThTLlTlJ2zZ-(SoK68n|$e!+pDvy9W0PG!8C7CGs-DCns8jan0ZXV@Q(-*|`H%GPbF6)Eg= zZ@~@8V%+W|nBn1uOvVbERn-x*m~g``WpL}nrMR=$+J_2o7uj@*dE)ptD+AXUGf=*_ zv#b!<-Zt?Q+=$d}7|ezvXIU35yU5-avDq{=zPlLtJ`N=#>fol1U5Y27)6$R{wT8K(?p z&c146z&$SAIvs{RLoJA+4ZWkyes!Mje%F34`>T4d8y_~aI@(}%Q8#qkW}hz;pIpJ;;lMi#Ev7bK{6wx(mX-2^$IS zx;j7KO%8iRSm`f0XV6+wWm_kUh6y((KEl~XM_dJT zrbwSH{86s+dcO7S)0)TZfj(cPI6j_x@bDb-%VM()nNiku3Cil)sR_&c0RA zTcvF7kB6#??E{jJ~Ra-0tJY z?SFy8cF%junb8~9`BG`#|I3xT`=K+VF9sF;<=I^5+Vj`uA^MWfbTkC@m-dc1^ygZXI(Z4lZujVfuO`dQ4`I*semyqZ_o-~gRX3Bm01<#Hy@|ooM%l{A40crmL literal 0 HcmV?d00001 diff --git a/build/For_stm32.hex b/build/For_stm32.hex new file mode 100644 index 0000000..287c1fd --- /dev/null +++ b/build/For_stm32.hex @@ -0,0 +1,2782 @@ +:020000040800F2 +:100000000000082049AA0008413D0008433D0008BF +:10001000453D0008473D0008493D0008000000003C +:100020000000000000000000000000004B3D000840 +:100030004D3D0008000000004F3D0008513D000804 +:1000400099AA000899AA000899AA000899AA000884 +:1000500099AA000899AA000899AA000899AA000874 +:1000600099AA000899AA000899AA000899AA000864 +:1000700099AA000899AA000899AA000899AA000854 +:1000800099AA000899AA0008593D000899AA0008F1 +:1000900099AA000899AA000899AA000899AA000834 +:1000A00099AA0008713D0008A53D000899AA00081A +:1000B000D93D000899AA000899AA000899AA000841 +:1000C00099AA000899AA000899AA000899AA000804 +:1000D00099AA00081541000899AA000899AA0008E1 +:1000E00099AA000899AA000899AA000899AA0008E4 +:1000F000DD3D000899AA000899AA000899AA0008FD +:1001000099AA000899AA00082D3E000899AA00089B +:1001100099AA000899AA0008313E0008653E000827 +:1001200099AA000899AA000899AA000899AA0008A3 +:1001300099AA000899AA000899AA000899AA000893 +:1001400099AA000899AA000899AA000899AA000883 +:1001500099AA000899AA0008F541000899AA000880 +:1001600099AA000899AA000899AA000899AA000863 +:1001700099AA000899AA000899AA0008000000009E +:1001800099AA000899AA000899AA000899AA000843 +:1001900099AA000899AA000899AA000899AA000833 +:1001A00099AA000899AA000899AA000899AA000823 +:1001B00099AA000899AA000899AA000899AA000813 +:1001C00099AA000899AA00080000000099AA00084E +:1001D00099AA000899AA000899AA000899AA0008F3 +:1001E00099AA000899AA000899AA000899AA0008E3 +:0801F00099AA000899AA000871 +:100200000348044B834202D0034B03B118477047A5 +:100210005C0000205C000020000000000548064B48 +:100220001B1AD90F01EBA301491002D0034B03B1F4 +:10023000184770475C0000205C00002000000000B0 +:1002400010B5064C237843B9FFF7DAFF044B13B11E +:100250000448AFF300800123237010BD5C00002030 +:10026000000000009CAA000808B5044B1BB104491B +:100270000448AFF30080BDE80840CFE7000000006D +:10028000600000209CAA00080CB410B59CB01EAB06 +:10029000029106916FF0004104910791084953F8CB +:1002A000042B0591002402A901931B9400F010F97E +:1002B000029B1C701CB0BDE8104002B0704700BF2C +:1002C0000802FFFF0EB430B59CB06FF000411FABC9 +:1002D000049107910A4953F8042B029000240690D8 +:1002E000084D0868019302A905951B9400F0F0F8E9 +:1002F000029B1C701CB0BDE8304003B0704700BFCB +:10030000000000200802FFFF2DE9F0478F681D461E +:10031000AF420B680C46164636D8B1F90CC01CF437 +:10032000906F0ED13D46184631462A4600F06EFBCE +:10033000A368DF1B2368A7602B4400202360BDE86F +:10034000F0874A69096902EB42025F1A02EBD27236 +:100350006B1C52103B44934292BF914699461A46F9 +:100360001CF4806F804611D0114600F071FA82466D +:1003700000B321693A4600F01BFCA38923F4906383 +:1003800043F08003A38105E02F46CCE700F0BAFCE0 +:10039000824658B10AEB0703A9EB0707A760C4F828 +:1003A00010A0C4F8149023602F46BCE72169404692 +:1003B00000F0CEFAA3890C2243F04003C8F80020D5 +:1003C0004FF0FF30A381BAE72DE9F04F936817682B +:1003D00083B09246002B74D04FF0000B8B680A68F4 +:1003E00081460C465D4645E0B4F90C3013F4906F3D +:1003F0002CD0D4E90401161A01EB410202EBD272AF +:10040000711C52102944914292BF904688460A4678 +:100410005B0539D51146484600F01AFA01900028CC +:100420003DD03246216900F0C3FBA289019B22F432 +:10043000906242F08002A2819819A8EB0606A6609D +:10044000C4F8148023612060A8462E4632465946DF +:1004500000F0DCFADAF80810A3682268A3EB0803BE +:100460003244491BA3602260CAF8081049B3D7E997 +:1004700000B5083798461046002DF8D09D421E461C +:10048000B2D2A8462E46E1E70146484600F03AFCC3 +:1004900003460028D0D12169484600F059FAA389C3 +:1004A0000C2243F04003C9F800204FF0FF30A38135 +:1004B00000220023CAF80820CAF8043003B0BDE8BF +:1004C000F08F00200023CAF8043003B0BDE8F08F9D +:1004D0002DE9F04F1C468B891D069DB0884681464C +:1004E000934603D50B69002B00F0F180002309939C +:1004F00043F22003ADF829309BF800307D4D039482 +:100500000126002B73D0DA4603E01AF8013F002BD6 +:1005100075D0252BF9D1BAEB0B0473D19AF80020D2 +:10052000002A64D000234FF0FF32CDE905230AF101 +:10053000010A049307938DF853301A9305E0049A47 +:1005400006FA03F31A430492A2465446052214F80D +:10055000011B284600F0DCFAA346431B0028EED11D +:10056000049BD80644BF20228DF8532019079AF81F +:10057000001044BF2B228DF853202A2950D1039A12 +:1005800011680432002903927CDB07919AF801106C +:100590002E295BD0584C0322204600F0B9FA38B11E +:1005A000049B001B4022824013430BF1010B049378 +:1005B0001BF8011B51488DF82810062200F0A8FAFC +:1005C000002865D04E4B002B55D003AA00924D4B0E +:1005D000424604A94846AFF3008007467A1C06D07D +:1005E000099B3B4409939BF80030002B8BD1B8F852 +:1005F0000C305B067AD409981DB0BDE8F08FBAEBD9 +:100600000B04F4D023465A4641464846FFF77CFE89 +:100610000130ECD0099B9AF80020234409937FE72E +:10062000A1F13002092A88BFD346B1D8079B00E068 +:100630000134217803EB830302EB4303A1F1300281 +:10064000092AF5D92E290793A346A3D19BF80110B7 +:100650002A2927D1039B9BF802101A6805920433BC +:10066000002A0BF102000393B8BF4FF0FF3383461B +:10067000B8BF05938EE7039B073323F007030833C6 +:100680000393ADE7494243F00203079104937DE7EA +:1006900003AA00921B4B424604A9484600F0F6FB11 +:1006A00007469BE7A1F130020023092A05930BF1CD +:1006B000010B3FF66FAF1BF8011F03EB830302EB47 +:1006C0004303A1F13002092AF5D9059362E74021DD +:1006D00000F0BEF8C8F80000C8F8100018B14023B8 +:1006E000C8F8143002E70C23C9F800304FF0FF308F +:1006F00082E700BF28AC000830AC000834AC00082A +:10070000000000000903000870B50F4B0F4DAB420D +:10071000A3EB050607D0B610002455F8043B0134BE +:100720009847A642F9D80AF0B9F9094D094B5E1B62 +:10073000AB424FEAA60606D0002455F8043B01342C +:100740009847A642F9D870BD18AD000818AD00084A +:1007500018AD00081CAD0008830730B547D0541E03 +:10076000002A3ED0CAB2034601E0013C39D303F867 +:10077000012B9D07F9D1032C2CD9CDB205EB052512 +:100780000F2C05EB054535D9A4F1100222F00F0C12 +:1007900003F1100EE6444FEA121C1A46C2E9005556 +:1007A000C2E9025510327245F8D10CF1010214F081 +:1007B0000C0F03EB021204F00F0C13D0ACF1040386 +:1007C00023F003030433134442F8045B9342FBD148 +:1007D0000CF003042CB1C9B21C4403F8011BA34262 +:1007E000FBD130BD64461346002CF4D1F9E7034633 +:1007F0001446C0E71A46A446E0E700BF014B18685C +:10080000704700BF0000002070B5104E33680546E9 +:100810000C46B3B12146284600F07EFC431C0CD0A8 +:10082000C41C24F00304A04205D0211A284600F07D +:1008300073FC013001D0204670BD4FF0FF342046DC +:1008400070BD194600F068FC3060E3E778000020D6 +:100850002DE9F843CD1C25F0030508350C2D38BFD4 +:100860000C25002D064618DBA94216D8DFF8DC80DF +:1008700000F04EFCD8F80420A2B1144603E06368EF +:1008800022467BB11C4623685B1BF8D40B2B1FD878 +:100890009442636854D053600CE00C233360002012 +:1008A000BDE8F88329463046FFF7AEFF431C0446F7 +:1008B00019D00560304600F02DFC04F10B00231D1B +:1008C00020F00700C21A1CBF1B1AA350BDE8F88312 +:1008D00061199442256014BF5160C8F80410635137 +:1008E00063684B60E6E7D8F804701FB33C467F6846 +:1008F000002FFBD123683946304604EB030900F092 +:100900000BFC814516D12368ED1A29463046FFF7C6 +:100910007BFF01300ED02368D8F804202B442360DD +:10092000536883B1A34203D01A465B689C42FBD153 +:100930000023B0E70C233360304600F0EBFBAEE75A +:10094000C8F80430B6E7C8F80470B3E778000020B0 +:10095000002950D038B551F8043C0C1F002BB8BF0B +:10096000E418054600F0D4FB274A13682BB1A342D4 +:100970000CD92168601883422CD06360284614602B +:10098000BDE8384000F0C6BBA3420FD81A465B68EA +:10099000002BF9D111685018844217D02CD3636012 +:1009A00054602846BDE8384000F0B4BB11685018C8 +:1009B000A04214D020D8216860188342EFD1186873 +:1009C0005B680844C4E900035460EAE723680B4409 +:1009D0001360E6E718685B6808442060CDE720688C +:1009E0000144501883421160DBD1D3E90004014473 +:1009F000C2E90014D5E770470C232B602846BDE8F8 +:100A0000384000F087BB00BF7C00002088420ED930 +:100A10008B1883420BD900EB020C002A6ED0624681 +:100A200013F801CD02F801CD9942F9D170470F2A90 +:100A30000FD8034602F1FF3C002A5FD00CF1010CF5 +:100A4000013B8C4411F8012B03F8012F6145F9D1CA +:100A5000704740EA01039B0751D1A2F1100370B522 +:100A600001F1200C23F00F0501F1100E00F110042C +:100A7000AC441B095EF8105C44F8105C5EF80C5C3A +:100A800044F80C5C5EF8085C44F8085C5EF8045CB2 +:100A900044F8045C0EF1100EE64504F11004E9D1AF +:100AA000013312F00C0F01EB031102F00F0400EB05 +:100AB000031328D0043C24F003064FEA940C1E4490 +:100AC0001C1F8E465EF8045B44F8045FB442F9D103 +:100AD0000CF1010402F0030203EB840301EB840137 +:100AE00002F1FF3C4AB10CF1010C013B8C4411F8BE +:100AF000012B03F8012F6145F9D170BD704702F158 +:100B0000FF3C03469AE72246EAE700BF00000000E8 +:100B100001F0FF01102A2BDB10F0070F08D010F8AE +:100B2000013B013A8B422DD010F0070F42B3F6D1B2 +:100B3000F0B441EA012141EA014122F007047FF0CB +:100B400000070023F0E80256083C85EA010586EA22 +:100B5000010685FA47F5A3FA87F586FA47F6A5FA5E +:100B600087F68EB9EED1F0BC01F0FF0102F007026A +:100B700032B110F8013B013A83EA010313B1F8D115 +:100B80000020704701387047002D06BF35460338F6 +:100B9000073815F0010F07D1013015F4807F02BF2F +:100BA000013015F4C03F0130F0BC0138704700BF80 +:100BB000844641EA000313F003036DD1403A41D368 +:100BC00051F8043B40F8043B51F8043B40F8043B27 +:100BD00051F8043B40F8043B51F8043B40F8043B17 +:100BE00051F8043B40F8043B51F8043B40F8043B07 +:100BF00051F8043B40F8043B51F8043B40F8043BF7 +:100C000051F8043B40F8043B51F8043B40F8043BE6 +:100C100051F8043B40F8043B51F8043B40F8043BD6 +:100C200051F8043B40F8043B51F8043B40F8043BC6 +:100C300051F8043B40F8043B51F8043B40F8043BB6 +:100C4000403ABDD2303211D351F8043B40F8043B56 +:100C500051F8043B40F8043B51F8043B40F8043B96 +:100C600051F8043B40F8043B103AEDD20C3205D366 +:100C700051F8043B40F8043B043AF9D2043208D05E +:100C8000D2071CBF11F8013B00F8013B01D30B88D0 +:100C900003806046704700BF082A13D38B078DD0AE +:100CA00010F003038AD0C3F10403D21ADB071CBF80 +:100CB00011F8013B00F8013B80D331F8023B20F8EA +:100CC000023B7BE7043AD9D3013A11F8013B00F823 +:100CD000013BF9D20B7803704B7843708B788370AB +:100CE00060467047024B01461868FFF7B1BD00BF70 +:100CF00000000020024B01461868FFF729BE00BF24 +:100D0000000000202DE9F041144641B30AB3064625 +:100D10000D4600F013FA8442074602D8B4EB500F98 +:100D200013D821463046FFF793FD804650B1BC42B0 +:100D30002246294628BF3A46FFF73AFF2946304661 +:100D4000FFF706FE4046BDE8F081A8464046BDE8F4 +:100D5000F081A046FFF7FCFD4046BDE8F081BDE80C +:100D6000F0411146FFF774BD2DE9F84F92461F463A +:100D70000A698B68DDF828909A42B8BF1A46CAF80B +:100D8000002091F843300C46064613B10132CAF8F0 +:100D90000020226891065FD5DAF800300233CAF8E5 +:100DA0000030226812F0060F11461DD1E168994209 +:100DB000D8BF114618DD4FF0000804F1190B05E00B +:100DC000E568DAF80030ED1A45450CDD01235A4696 +:100DD00039463046C847013008F10108F0D14FF0DC +:100DE000FF30BDE8F88F216894F84330003B18BF0E +:100DF00001238A060AD5E1185A1C302081F84300E5 +:100E0000224494F8451082F84310023304F143025F +:100E100039463046C8470130E1D02368DAF800503F +:100E2000216903F00603042BD4E902201BD08A4277 +:100E300020DD4FF00008521A90441A34002501E0DA +:100E4000454517DA0123224639463046C847013066 +:100E500005F10105F4D1C2E712F0060F0DD0003BF9 +:100E600018BF0123D2E7401B8A4220EAE078E2DC87 +:100E70000028E2DC0020BDE8F88FE168DAF80030F5 +:100E80009942D8BF114696DCAEE700BF2DE9F04786 +:100E9000174684B00A7E0C9D0C460646984601F122 +:100EA000430C002A35D0A2F15803D9B2202969D8C1 +:100EB000202B67D8DFE813F0E600660066006600C6 +:100EC0006600660066006600660066006600AC00AC +:100ED00070006600660066006600700066006600CE +:100EE0006600660021008300C60066006600B6004A +:100EF0006600830066006600EC002B68226861696A +:100F0000181D286010061B6802D4520600F1E0800C +:100F100019600023E1462361CDF800803B4603AA17 +:100F200021463046FFF720FF013020D023694A4692 +:100F300039463046C047013019D02368E068DDF8F3 +:100F40000C909B0718D5484516DD002504F1190AB9 +:100F500004E0E068A0EB0903AB420DDD012352463B +:100F600039463046C047013005F10105F1D14FF057 +:100F7000FF3004B0BDE8F0874845B8BF484604B02C +:100F8000BDE8F08784F84220012004F142090023E3 +:100F9000206184F84330BFE72A682368111D1806D2 +:100FA000296002D4590600F1958010680146002896 +:100FB0006268C0F2938054484FF00A0E15E0206832 +:100FC0002B6810F0800F53F8041B02D1400648BF75 +:100FD00089B26F2A4C482B6014BF4FF00A0E4FF0B5 +:100FE000080E0023626884F84330002AA26051DBB7 +:100FF000236823F00403236000294BD1002A7BD10E +:10100000E146BEF1080F56D0ACEB0903236183E73C +:101010002B681A6804332B6004F1420984F84220DB +:101020000120B4E72B686268191D2960D3F800908D +:1010300000214846FFF76CFD002863D0A0EB0900B3 +:101040006060A4E7236843F02003236078222F48E0 +:1010500084F845202A6813F0800F52F8041B03D14E +:1010600013F0400F18BF89B22A60DA0744BF43F07B +:101070002003236019B9236823F0200323604FF075 +:10108000100EAEE7582384F845301F482368E1E787 +:101090002368DBE77546E146B1FBF5F305FB131A60 +:1010A0000A46AA4210F80A1009F8011D1946F3D29F +:1010B000BEF1080FA8D12368DD07A5D562682369B2 +:1010C0009A42A1DC302309F8013C09F1FF399BE782 +:1010D00019801EE7B2F90010084668E72D20002AA3 +:1010E000A26084F8430002DB23F0040323600A2596 +:1010F00005484942AE46CEE7037884F8423004F111 +:1011000042097EE7606842E73CAC000850AC00084A +:10111000704700BF704700BF38B5074D0022044636 +:1011200008462A6009F062F9431C00D038BD2B68DC +:10113000002BFBD0236038BDBC01002051F8043CDB +:10114000181F002BBCBF0B58C018704753B94AB9C1 +:10115000002908BF00281CBF4FF0FF314FF0FF30BF +:1011600000F06AB9ADF1080C6DE904CE00F006F8A4 +:10117000DDF804E0DDE9022304B070472DE9F04713 +:10118000089D0E4604460F46002B4AD194468C45D6 +:10119000B2FA82F260D942B1C2F12003974020FA3C +:1011A00003F30CFA02FC1F4394404FEA1C4E1FFA53 +:1011B0008CF6B7FBFEF1230C0EFB117743EA0743D5 +:1011C00001FB06F098420AD91CEB030301F1FF373B +:1011D00080F01581984240F21281023963441B1A53 +:1011E000A4B2B3FBFEF00EFB103344EA034400FB51 +:1011F00006F6A6420AD91CEB040400F1FF3380F086 +:101200000081A64240F2FD806444023840EA014079 +:10121000A41B00211DB1D4400023C5E90043BDE853 +:10122000F0878B4205D90DB1C5E9000100210846C0 +:10123000F5E7B3FA83F1002946D1B34202D38242E3 +:1012400000F2F580841A66EB030201201746002D98 +:10125000E5D0C5E90047E2E7002A40F09380A1EB22 +:101260000C034FEA1C471FFA8CFE0121B3FBF7F673 +:1012700007FB1630230C43EA00430EFB06F09842AE +:1012800008D91CEB030306F1FF3802D2984200F2A2 +:10129000D08046461B1AA4B2B3FBF7F007FB10330D +:1012A00044EA03440EFB00FEA64508D91CEB0404E7 +:1012B00000F1FF3302D2A64500F2B6801846A4EB37 +:1012C0000E0440EA0640A5E7C1F120078B4022FA50 +:1012D00007FC4CEA030C06FA01FE20FA07F426FA92 +:1012E00007F344EA0E0400FA01F84FEA1C404FEA03 +:1012F0001449B3FBF0FE1FFA8CF600FB1E3349EADB +:1013000003430EFB06F9994502FA01F20BD91CEBD7 +:1013100003030EF1FF3A80F08580994540F2828008 +:10132000AEF1020E6344A3EB0909A4B2B9FBF0F3DA +:1013300000FB139944EA094403FB06F6A64208D9C8 +:101340001CEB040403F1FF3068D2A64266D9023BCD +:10135000644443EA0E40A41BA0FB02E6B442734679 +:10136000B14652D34FD05DB1B8EB030264EB090430 +:1013700004FA07F722FA01F31F43CC40C5E90074D1 +:1013800000214CE7C2F1200120FA01F30CFA02FC23 +:1013900026FA01F1964033434FEA1C471FFA8CFEB0 +:1013A000B1FBF7F007FB1016190C41EA064100FBF0 +:1013B0000EF68E4204FA02F408D91CEB010100F18A +:1013C000FF382DD28E422BD902386144891B9BB243 +:1013D000B1FBF7F607FB161143EA014306FB0EF1DA +:1013E000994208D91CEB030306F1FF3814D2994245 +:1013F00012D9023E63445B1A46EA004136E7394699 +:10140000EDE6184602E7F045ADD2BEEB020366EB0F +:101410000C060138B146A6E74646ECE7034698E7D6 +:101420004046D3E7D6467EE76444023847E708469D +:101430000DE7023E63442DE7704700BF00B500F0A2 +:101440000700C0F1070CBCF1040F28BF4FF0040CDB +:10145000031D062B0FD9C31E4FF0FF3E0EFA0CF0F2 +:1014600021EA000199400EFA03FE22EA0E0241EA47 +:1014700002005DF804FB0023EEE70000064B074A7C +:101480001A6000225A609A60DA604FF400611961B4 +:101490005A6114229A617047EC040020002C01402C +:1014A00000B583B00D4B1A6B42F480021A631B6BBC +:1014B00003F480030193019B094BD8680022114675 +:1014C000C0F30220FFF7BAFF0001C0B2054B83F85A +:1014D000460340229A6003B05DF804FB00380240E6 +:1014E00000ED00E000E100E082B0028802F00102BD +:1014F0001A700288C2F340025A700288C2F3800256 +:101500009A700288C2F3C002DA700288C2F3001235 +:101510001A710288C2F340125A710288C2F3801213 +:101520009A710288C2F3C012DA710288C2F30022F3 +:101530001A720288C2F340225A720288C2F38022D1 +:101540009A720288C2F3C022DA720288C2F30032B1 +:101550001A730288C2F340325A738278384B1A7079 +:10156000828807EE902AF8EE677AC3ED017AC28886 +:1015700007EE902AF8EE677AC3ED027A028907EE49 +:10158000902AF8EE677AC3ED037A428907EE102AB3 +:10159000B8EE477B9FED285B87EE056BFCEEC67BC4 +:1015A000CDED017A9DF804201A75818907EE901A15 +:1015B000F8EE677AC3ED067AC18907EE901AF8EE65 +:1015C000677AC3ED077A018A07EE901AF8EE677A18 +:1015D000C3ED087A418AD982818A07EE901AF8EE23 +:1015E000677A9FED187A67EE877AC3ED0A7AC18A27 +:1015F00007EE901AF8EE677A67EE877AC3ED097AFC +:10160000018B07EE901AF8EE677A67EE877AC3EDE2 +:101610000C7A418B07EE901AF8EE677A67EE877ABC +:10162000C3ED0B7A084BA3FB0232D208074B1A60BA +:1016300002B07047AFF30080000000000000594086 +:10164000C001002000008043CDCCCCCC080300209A +:1016500030B40B8804881B1BD1ED017A03F6B73C2C +:1016600041F26E74A44518D890ED027A06EE903AD5 +:10167000F8EEE66A27EE267A284C2468284D2D6875 +:10168000641B06EE904AF8EE666A27EE267A9FED16 +:10169000256AC7EE066A77EEA67AD0ED016A9FED5D +:1016A000227AF4EEC77AF1EE10FA09DC9FED1F7A88 +:1016B000F4EEC77AF1EE10FA04D5DFED1C7A01E002 +:1016C000DFED197AC1ED017A07EE103AB8EEC77A6C +:1016D00027EE267ADFED166A37EE267AFDEEE77AF8 +:1016E000F8EEE77A77EE877AFDEEE77A17EE900A62 +:1016F000B0F57A7F06DB4DF6E053984204DD4DF6F7 +:10170000E05001E042F26020022A02D080B230BCF8 +:101710007047024B1A68024B1A60F7E71803002063 +:10172000100300200000C8420000FA460000FAC67C +:101730000000004710B5092813D8DFE800F00513B2 +:10174000212F3D4B5965717D414C01224FF4806141 +:10175000204604F020FA00224FF48061204604F075 +:101760001AFA10BD3A4C01224FF40061204604F0F1 +:1017700012FA00224FF40061204604F00CFAF0E760 +:10178000334C01224FF48051204604F004FA002229 +:101790004FF48051204604F0FEF9E2E72C4C012280 +:1017A0004FF40051204604F0F6F900224FF40051A6 +:1017B000204604F0F0F9D4E7254C01224FF4804193 +:1017C000204604F0E8F900224FF48041204604F05E +:1017D000E2F9C6E71E4C01224FF40041204604F016 +:1017E000DAF900224FF40041204604F0D4F9B8E7BA +:1017F000184C01221021204604F0CDF900221021BE +:10180000204604F0C8F9ACE7124C01222021204602 +:1018100004F0C1F900222021204604F0BCF9A0E721 +:101820000C4C01224021204604F0B5F90022402151 +:10183000204604F0B0F994E7064C012280212046AE +:1018400004F0A9F900228021204604F0A4F988E7D9 +:10185000001802400004024038B5044600224FF44C +:101860008041814804F097F900224FF400717F48CD +:1018700004F091F9002300E00133B3F5FA7FFBD3C4 +:1018800001224FF48041784804F085F901224FF499 +:101890000071764804F07FF9002300E00133B3F5CE +:1018A000FA7FFBD3631E032B39D8DFE803F0023A3B +:1018B0006FA66D4C01224FF40061204604F06BF9D5 +:1018C00000224FF48061204604F065F9002300E017 +:1018D0000133B3F5FA7FFBD3654A136843F0400345 +:1018E00013600023624A926812F0010F04D1B3F52D +:1018F0007A7F01D80133F5E75D490A6822F040029A +:101900000A6000E00133B3F5FA7FFBD301224FF404 +:101910008061554804F03FF9554BDD68ADB228466B +:1019200038BD524C01224FF48061204604F033F957 +:1019300000224021204604F02EF9002300E001336C +:10194000B3F5FA7FFBD34B4A136843F040031360AF +:101950000023484A926812F0010F04D1B3F57A7F50 +:1019600001D80133F5E743490A6822F040020A60D2 +:1019700000E00133B3F5FA7FFBD3012240213B485D +:1019800004F009F93B4BDD68ADB2C8E7364C0122E3 +:101990004FF48061204604F0FEF800224FF400610D +:1019A000204604F0F8F8002300E00133B3F5FA7F95 +:1019B000FBD32F4A136843F04003136000232C4AE3 +:1019C000926812F0010F04D1B3F57A7F01D8013388 +:1019D000F5E727490A6822F040020A6000E0013377 +:1019E000B3F5FA7FFBD301224FF400611E4804F0E7 +:1019F000D2F81F4BDD68ADB291E71C4C01224021AB +:101A0000204604F0C8F800224FF48061204604F01C +:101A1000C2F8002300E00133B3F5FA7FFBD3154A87 +:101A2000136843F0400313600023124A926812F0D7 +:101A3000010F04D1B3F57A7F01D80133F5E70D49E1 +:101A40000A6822F040020A6000E00133B3F5FA7F31 +:101A5000FBD301224FF48061044804F09CF8054B4D +:101A6000DD68ADB25BE700BF001002400014024029 +:101A7000003401400050014008B5044805F030FF33 +:101A80000023034A1370034A136008BD08040020B2 +:101A9000D60200200C0300202DE9F04F8FB0002467 +:101AA00009940A940B940C940D94854B1A6B42F094 +:101AB00020021A631A6B02F020020192019A1A6B3B +:101AC00042F080021A631A6B02F080020292029ABC +:101AD0001A6B42F004021A631A6B02F004020392BA +:101AE000039A1A6B42F001021A631A6B02F00102A8 +:101AF0000492049A1A6B42F002021A631A6B02F003 +:101B000002020592059A1A6B42F010021A631A6BD0 +:101B100002F010020692069A1A6B42F008021A634B +:101B20001A6B02F008020792079A1A6B42F0400201 +:101B30001A631B6B03F040030893089BDFF8908146 +:101B400022464FF4C861404604F025F8DFF884B11E +:101B500022463C21584604F01EF85A4E22464B219C +:101B6000304604F018F801221021304604F013F832 +:101B7000554F22464FF44061384604F00CF80122DC +:101B80004FF48041384604F006F8DFF84CA12246B5 +:101B900044F6F041504603F0FEFF01224FF480511D +:101BA000504603F0F8FFDFF8349122464FF4C1713C +:101BB000484603F0F0FF22464FF47E41434803F0CD +:101BC000EAFF182309930A9401250B9509A94046B9 +:101BD00003F0D8FE4FF4C86309930A950B940C9454 +:101BE00009A9404603F0CEFE342309930A950B94CD +:101BF0000C9409A9584603F0C5FE082309930A95D9 +:101C00000B9403230C9309A9584603F0BBFE5B23F6 +:101C100009930A950B940C9409A9304603F0B2FE7F +:101C20004FF4F04309930A940B9409A9404603F03A +:101C3000A9FE4FF4406309930A950B940C9409A9EB +:101C4000384603F09FFE4FF4804309930A950B94A6 +:101C500003230C9309A9384603F094FE45F6F0439C +:101C600009930A950B940C9409A9504603F08AFE37 +:101C70004FF4C17309930A950B940C9409A9484633 +:101C800003F080FE4FF4807309930A940B9409A922 +:101C9000304603F077FE09950A940B9409A948464B +:101CA00003F070FE4FF47E4309930A950B940C9455 +:101CB00009A9064803F066FE0FB0BDE8F08F00BF2B +:101CC00000380240000002400010024000180240AC +:101CD000001402400008024000040240000C0240D0 +:101CE0002DE9F04192B02822002108A8FEF734FD2A +:101CF00000240294039404940594069407942A4BB8 +:101D00005A6C42F400525A645A6C02F40052019226 +:101D1000019A1A6B42F010021A631B6B03F0100356 +:101D20000093009B4FF480530293022503954FF0DC +:101D30000308CDF81080052707971C4E02A93046EE +:101D400004F095FA4FF4005302930395CDF81080F8 +:101D500005940694079702A9304604F088FA4FF4D8 +:101D6000806308934FF4827309934FF470630A936E +:101D70000B950C944FF400730D9318230E930F944E +:101D80001094072311930A4C08A9204605F0ECFB98 +:101D9000636823F010036360636823F008036360E3 +:101DA00012B0BDE8F08100BF0038024000100240D0 +:101DB000003401402DE9F04192B02822002108A80A +:101DC000FEF7CAFC0024029403940494059406943C +:101DD0000794294B1A6C42F480421A641A6C02F47C +:101DE00080420192019A1A6B42F002021A631B6B45 +:101DF00003F002030093009B4FF40053029302256B +:101E000003954FF00308CDF81080052707971B4E68 +:101E100002A9304604F02BFA4FF4004302930395D5 +:101E2000CDF8108005940694079702A9304604F077 +:101E30001EFA08944FF4827309934FF470630A9367 +:101E40000B9501230C934FF400730D9310230E9305 +:101E50000F94109407231193094C08A9204605F00C +:101E600083FB636823F010036360636823F0080357 +:101E7000636012B0BDE8F081003802400004024007 +:101E8000003800402DE9F04192B02822002108A836 +:101E9000FEF762FC002402940394049405940694D3 +:101EA0000794294B5A6C42F480125A645A6C02F41B +:101EB00080120192019A1A6B42F020021A631B6B86 +:101EC00003F020030093009B8023029302250395D7 +:101ED0004FF00308CDF81080052707971B4E02A985 +:101EE000304604F0C4F94FF4807302930395CDF8A3 +:101EF000108005940694079702A9304604F0B7F9BC +:101F00004FF4806308934FF4827309934FF4706326 +:101F10000A930B950C944FF400730D9318230E93B2 +:101F20000F94109407231193094C08A9204605F03B +:101F30001BFB636823F010036360636823F00803EE +:101F4000636012B0BDE8F081003802400014024026 +:101F5000005001402DE9F04192B02822002108A84C +:101F6000FEF7FAFB0024029403940494059406946B +:101F70000794294B5A6C42F400125A645A6C02F4CA +:101F800000120192019A1A6B42F001021A631B6B54 +:101F900003F001030093009B202302930225039585 +:101FA0004FF00308CDF81080082707971B4E0DEB64 +:101FB0000701304604F05BF9802302930395CDF8C6 +:101FC00010800594069407970DEB0701304604F046 +:101FD0004EF908944FF4827309934FF470630A9397 +:101FE0000B9501230C934FF400730D9318230E935C +:101FF0000F94109407231193094C08A9204605F06B +:10200000B3FA636823F010036360636823F0080386 +:10201000636012B0BDE8F081003802400000024069 +:102020000054014010B586B000240194029403943A +:10203000049405941D4B1A6C42F001021A641B6C47 +:1020400003F001030093009B194BD86822462146F8 +:10205000C0F30220FFF7F2F90001C0B2154B83F87C +:102060001C034FF080521A604FF47A73ADF80430BD +:102070000294114B0393049401A94FF0804006F0A1 +:10208000C3F84FF080431A6822F080021A60996802 +:102090000A4A0A409A605A6822F070025A609A68A6 +:1020A00022F080029A6006B010BD00BF00380240E6 +:1020B00000ED00E000E100E040D10C00F8BFFEFFC1 +:1020C00010B586B0002401940294039404940594FE +:1020D0001C4B1A6C42F008021A641B6C03F00803D4 +:1020E0000093009B184BD86822462146C0F302207B +:1020F000FFF7A4F90001C0B2144B83F832034FF488 +:1021000080225A6042F21073ADF8043002944FF40A +:102110000C73039304940E4C01A9204606F074F846 +:10212000236823F080032360A2680A4B1340A36056 +:10213000636823F070036360A36823F08003A360E7 +:1021400006B010BD0038024000ED00E000E100E004 +:10215000000C0040F8BFFEFF10B586B000240194CB +:1021600002940394049405941A4B1A6C42F02002D2 +:102170001A641B6C03F020030093009B164BD86875 +:1021800022462146C0F30220FFF758F90001C0B2F1 +:10219000124B83F837034FF400025A6040F2973332 +:1021A000ADF804300294632303930D4C01A920463B +:1021B00006F02AF8236823F080032360636823F085 +:1021C000700343F010036360A36823F08003A360EF +:1021D00006B010BD0038024000ED00E000E100E074 +:1021E0000014004010B586B00024019402940394BA +:1021F000049405941A4B1A6C42F010021A641B6C7A +:1022000003F010030093009B164BD868224621462A +:10221000C0F30220FFF712F90001C0B2124B83F89D +:1022200036034FF480025A604BF2AF33ADF80430FE +:102230000294132303930D4C01A9204605F0E4FFFB +:10224000236823F080032360636823F0700343F066 +:1022500010036360A36823F08003A36006B010BD81 +:102260000038024000ED00E000E100E00010004016 +:102270002DE9F04100239E4A13609E4A13609E4A56 +:1022800013609E4A13609E4A13609E4A13709E4AD2 +:1022900013809E4A13609E4A13609E4A13709E4AA2 +:1022A000137005E09D4A002122F8131001339BB200 +:1022B0000E2BF7D9994B41F211121A80984B00223C +:1022C000DA81DA701A711A821A735A735A719A7112 +:1022D000DA72DA711A725A729A725A709A701A70A5 +:1022E000904D2A80904C228000226A606260AA6031 +:1022F000A2608E4E9C46BCE80F000FC6DCF8003092 +:1023000033808B4E95E80F0086E80F00894D94E8E6 +:102310000F0085E80F00884BDA6842F00102DA60AE +:102320001A6842F001021A6003F58063DA6842F02D +:102330000102DA601A6842F001021A6003F51433F0 +:10234000D3F8B82022F00102C3F8B8204FF00062A1 +:10235000DA604FF00072DA60784A02F1080353E85D +:10236000003F43F08003083242E800310029F3D1F6 +:10237000734BD3F8B82042F01002C3F8B820D3F85A +:10238000B82042F00402C3F8B8204FF00062DA60CF +:102390004FF00072DA606B4AD3F8B83003F0C00334 +:1023A000402B7BD0664BC3F8C020674AC3F8C420DB +:1023B0000024664B1C60664B1C60664F2246082159 +:1023C000384603F0E8FB22460421384603F0E3FBDD +:1023D000DFF8A48122464FF48071404603F0DBFB16 +:1023E00022461021384603F0D6FB5B4E22464FF4BE +:1023F0008061304603F0CFFB584D22460821284625 +:1024000003F0C9FB22460121284603F0C4FB224603 +:102410000221284603F0BFFB22464FF400613046FC +:1024200003F0B9FB22462021384603F0B4FB07F540 +:10243000006701224FF48061384603F0ACFB484C42 +:1024400001224021204603F0A6FB01224FF48041E7 +:10245000384603F0A0FB01224FF48041204603F0F0 +:102460009AFB01224FF48041304603F094FB012295 +:102470004021284603F08FFB01224FF48051304663 +:1024800003F089FB01221021284603F084FB01217F +:10249000404603F079FB40B1BDE8F081284BC3F81A +:1024A000C420294AC3F8C02082E74FF4807128462F +:1024B00003F06AFB0028EFD12A4805F0CDFF2A4B34 +:1024C000186018B1294B01221A70E5E71E231A463D +:1024D0002749284806F010F8234C2060214805F0D1 +:1024E000CDFF20600023084A1380064A1370E9E7F5 +:1024F0003003002018030020140300202C030020C8 +:1025000024030020D9020020D402002084020020ED +:1025100080020020D8020020D7020020B002002054 +:102520001802002050020020400200202C0200204F +:1025300070020020600200200010004000100140E6 +:1025400000640240DC02002028100140200300202B +:102550001C0300200008024000040240000002406A +:1025600000140240B4AA00088802002000030020E2 +:1025700090020020B8AA0008000C024010B5002408 +:1025800005282CD8DFE800F0030812171C26154890 +:1025900002F0F6F8204610BD124C6421204602F0ED +:1025A000A9F9204602F007FA80B2F4E70D4802F0DC +:1025B00081F92046EFE70C4802F0E2F82046EAE70E +:1025C000094C6421204602F095F9204602F0F3F907 +:1025D00080B2E0E7044802F06DF92046DBE72046D0 +:1025E000D9E700BFB80500207005002038B50C46BB +:1025F0000138032823D8DFE800F0023B5B7C00228F +:102600004FF480414B4803F0C6FA00224A4B9B68C6 +:1026100013F0020F04D1B2F5FA7F01D80132F5E7C9 +:10262000454B9C810022444B9B6813F0010F04D161 +:10263000B2F5FA7F01D80132F5E73F4BDB683D4D3B +:1026400001224FF48041284603F0A5FA3B4C0122B9 +:102650004021204603F09FFA01224FF48051284682 +:1026600003F099FA01221021204603F094FA38BDB4 +:1026700000224021314803F08EFA0022304B9B6843 +:1026800013F0020F04D1B2F5FA7F01D80132F5E759 +:102690002B4B9C8100222A4B9B6813F0010F04D125 +:1026A000B2F5FA7F01D80132F5E7254BDB68C6E7C2 +:1026B00000224FF480511F4803F06DFA00221E4B98 +:1026C0009B6813F0020F04D1B2F5FA7F01D80132F2 +:1026D000F5E7194B9C810022174B9B6813F0010F03 +:1026E00004D1B2F5FA7F01D80132F5E7124BDB686D +:1026F000A5E700221021114803F04DFA0022104BEB +:102700009B6813F0020F04D1B2F5FA7F01D80132B1 +:10271000F5E70B4B9C810022094B9B6813F0010FDE +:1027200004D1B2F5FA7F01D80132F5E7044BDB683A +:1027300085E700BF0004024000380040000002406E +:10274000005401402DE9F84305460F4616461C4645 +:10275000AF4B00221A600121AE4803F015FA0028A1 +:1027600000F0D2802B8803F0010323702B88C3F381 +:10277000400363702B88C3F38003A3702B88C3F3DB +:10278000C003E3702B88C3F3001323712B88C3F3BA +:10279000401363712B88C3F38013A3712B88C3F399 +:1027A000C013E3712B88C3F3002323722B88C3F378 +:1027B000402363722B88C3F38023A3722B88C3F357 +:1027C000C023E3722B88C3F3003323732B88C3F336 +:1027D000403363736B883B80AB8833806B89E381C4 +:1027E000AB8907EE903AF8EE677A9FED8B7A67EE49 +:1027F000877AC7ED017AEB8907EE903AF8EE677AAF +:1028000067EE877AC7ED027A2B8A07EE903AF8EEE8 +:10281000677A67EE877AC6ED017A6B8A07EE903A9F +:10282000F8EE677A67EE877AC6ED027AAA8A7B4B62 +:102830005A83EB8ABB812B8BB3816378002B00F02A +:10284000958001220821764803F0A5F9A378002B92 +:1028500000F0928001220421714803F09CF9E37892 +:10286000002B00F08F8001224FF48071694803F043 +:1028700092F92379002B00F08C8001221021684806 +:1028800003F089F96379002B00F0898001224FF46D +:102890008061644803F07FF9A379002B00F0868003 +:1028A00001220821604803F076F9637A1BB1E379CD +:1028B000002B40F08180002201215B4803F06BF97E +:1028C00000224FF40061574803F065F9A37A1BB169 +:1028D000237A002B40F0868000220221524803F028 +:1028E0005AF9002220214E4803F055F9237B1BB9E9 +:1028F0004E4B7B604E4BBB60637B1BB94B4B736095 +:102900004B4BB360BDE8F8834FF48071464803F049 +:102910003BF901287FF426AF464805F09DFD3C4B6E +:10292000186000287FF41EAFDFF80C91484605F0D0 +:10293000A9FEDFF8DC80C8F80000484605F080FEFC +:10294000C8F800001E222946484605F0A7FDC8F831 +:1029500000001E222946484605F0D6FEC8F80000B1 +:10296000344805F08BFDC8F80000FBE60022082182 +:102970002B4803F010F969E700220421284803F0EE +:102980000AF96CE700224FF48071224803F003F942 +:102990006FE700221021224803F0FDF872E70022C1 +:1029A0004FF480611F4803F0F6F875E70022082114 +:1029B0001D4803F0F0F878E747F6FF710320FFF7B2 +:1029C00015FE47F6FF710320FFF710FE01224FF4BA +:1029D0000061144803F0DFF801221146124803F0A9 +:1029E000DAF873E747F6FF710420FFF7FFFD47F6BB +:1029F000FF710420FFF7FAFD01222021084803F0AF +:102A0000CAF801220221084803F0C5F86EE700BFAA +:102A100088020020000C02400000803BB002002031 +:102A20000008024000040240000002400000204173 +:102A30000AD7233CB4AA0008B8AA00088446008834 +:102A4000012304E03CF81320504001331BB28B42B9 +:102A5000F8DB704710B50E4B1B8841F21112934200 +:102A600005D047F2777293420FD10E2400E00D2477 +:102A70002146FFF7E3FF074B1880074B33F814306C +:102A8000984214BF0020012010BD0020FCE700BFC9 +:102A9000D2020020D00200209002002010B504468F +:102AA00001210A4803F070F808B1012010BD084860 +:102AB00005F0D2FC08B10120F8E71E2221460548A6 +:102AC00005F022FE024805F0D9FCEFE7000C0240B9 +:102AD000B4AA0008C4AA000838B5044601210D486C +:102AE00003F052F808B1012038BD0B4805F0B4FCE2 +:102AF00008B10120F8E7094D2B681E22214608483D +:102B000005F0FAFC2B681E332B60034805F0B6FC79 +:102B1000EAE700BF000C0240B4AA000884020020CB +:102B2000C4AA000810B501210B4803F02DF808B124 +:102B3000012010BD094805F08FFC08B10120F8E71D +:102B4000074C204605F09EFD204605F079FD034820 +:102B500005F094FCEDE700BF000C0240B4AA0008A9 +:102B6000C4AA00088C4600220CE033B9074BDB698D +:102B700013F08003F9D00123F7E7815C034B9962DE +:102B8000013292B26245F1D3704700BF001001409C +:102B90000D4B1B78002BFBD10C4BD3F8B82022F047 +:102BA0000102C3F8B820D3F8BC206FF30F02104322 +:102BB000C3F8BC00D3F8B82042F00102C3F8B82033 +:102BC000014B01221A707047D802002000640240B5 +:102BD00072B6FEE700B585B000230093019302931F +:102BE00003932B482B4A02604FF4403242608360CB +:102BF00001220261836180F82030C362264981622C +:102C0000C3600521C16180F83030426101F08CFD64 +:102C1000002831D109230093012301930723029354 +:102C200069461B4801F068FF40BB0823009302235C +:102C300001936946164801F05FFF08BB0223009329 +:102C4000032301936946124801F056FFD0B90A23C5 +:102C500000930423019369460D4801F04DFF98B994 +:102C60000B230093052301936946094801F044FFB3 +:102C700060B905B05DF804FBFFF7AAFFFFF7A8FFF6 +:102C8000FFF7A6FFFFF7A4FFFFF7A2FFFFF7A0FFE4 +:102C9000B8050020002001400100000F00B585B0FC +:102CA000002300930193029303931448144A026093 +:102CB0004FF44032426083600361836180F82030CA +:102CC000C362104A8262C3600122C26180F8303060 +:102CD000426101F029FD68B90F230093012301939C +:102CE000072302936946054801F006FF20B905B0A5 +:102CF0005DF804FBFFF76CFFFFF76AFF700500202B +:102D0000002201400100000F2DE9F041B4B0002184 +:102D10002D912E912F9130913191329133912791B4 +:102D2000289129912A912B912C91902203A8FDF7AB +:102D300013FD4023039303A802F024FB002840F076 +:102D40009E80504B5A6C42F010025A645A6C02F04A +:102D500010020292029A1A6B42F001021A631B6B74 +:102D600003F001030193019B4FF4007327934FF08D +:102D70000208CDF8A0800327299700242A942B94D9 +:102D800007262C96404D27A9284603F070FA4FF4E9 +:102D900080632793CDF8A08029972A942B942C96B2 +:102DA00027A9284603F063FA384BD3F8B82022F05D +:102DB000F05242F00062C3F8B820D3F8B82022F0F5 +:102DC000C00242F04002C3F8B820D3F8B82042F461 +:102DD0004032C3F8B820D3F8B82022F49072C3F878 +:102DE000B820D3F8B82022F40072C3F8B820D3F882 +:102DF000B82042F48062C3F8B820D3F8B82022F497 +:102E0000C052C3F8B820D3F8B82022F4C042C3F8A7 +:102E1000B820D3F8CC2022F00402C3F8CC201C4BFD +:102E2000D86822462146C0F30220FEF707FB0001C6 +:102E3000C0B2184B83F8250320225A604FF4E133C7 +:102E40002D932E942F9430940C23319332943394F9 +:102E500004F1804404F588342DA9204605F074FA65 +:102E6000636823F490436360A36823F02A03A3609C +:102E7000236843F00103236034B0BDE8F081FFF71D +:102E8000A7FE00BF0038024000000240006402407C +:102E900000ED00E000E100E008B50848084B0360E1 +:102EA000B7234360002383600922C260036183610A +:102EB00004F082FE00B908BDFFF78AFE0804002076 +:102EC0000044014008B50B480B4B03604FF4E1335D +:102ED000436000238360C36003610C22426183610D +:102EE000C3610362436207F07EFD00B908BDFFF7CE +:102EF0006FFE00BF34030020007C004000B589B0A5 +:102F0000002304930593069307930193029303937D +:102F10001348144A0260436083605B22C26003610D +:102F20004361836104F048FE98B94FF480530493E1 +:102F300004A90B4804F082FF68B9002301930293AF +:102F4000039301A9064805F00BF930B909B05DF803 +:102F500004FBFFF73DFEFFF73BFEFFF739FE00BF26 +:102F6000540400200004014000B589B000230193FF +:102F70000293039304930593069307931448154A09 +:102F800002600122426083605B22C2600361802391 +:102F9000836104F011FEA8B90D4804F03DFE98B914 +:102FA000602301935B23029300220392059201A9FF +:102FB000074804F099FE48B9054801F091FA09B0B4 +:102FC0005DF804FBFFF704FEFFF702FEFFF700FECB +:102FD000BC0300200048014000B58FB000230A93D5 +:102FE0000B930C930D93079308930993009301930C +:102FF000029303930493059306931E481E4A0260AE +:10300000436083602D22C2600361836104F0D4FDBC +:1030100030BB4FF480530A930AA9164804F00EFF00 +:1030200000BB144804F0F8FDF0B90023079309939E +:1030300007A9104805F094F8C0B96023009316233F +:10304000019300230293049308226946094804F07F +:103050004BFE68B9074801F043FA0FB05DF804FB76 +:10306000FFF7B6FDFFF7B4FDFFF7B2FDFFF7B0FDC8 +:10307000FFF7AEFDA00400200008004000B595B0A9 +:103080003422002107A8FDF767FB00230293039376 +:10309000049305930693244B1A6C42F080521A64F1 +:1030A0001B6C03F080530093009B204B1A6842F482 +:1030B00040421A601B6803F440430193019B0123C3 +:1030C00007934FF48033089302230D934FF480024B +:1030D0000E9219220F924FF4B87210921193082297 +:1030E0001292139307A801F0FBFDB0B902F062FD44 +:1030F000A8B90F23029302230393002304934FF4F0 +:10310000A05305934FF480530693062102A802F0C2 +:103110005DF830B915B05DF804FBFFF759FDFFF716 +:1031200057FDFFF755FD00BF00380240007000401A +:103130002DE9F04383B002F017FEFFF79FFFFEF783 +:10314000ABFCFEF7ADF9FEF7CBFD00F0DDFDFEF7C1 +:1031500069FFFEF7B5FFFFF73DFDFFF79FFDFEF7A7 +:1031600029FEFEF78FFEFEF7F5FEFFF7CDFDFEF719 +:1031700085F9FEF7F1FFFFF735F8FFF78DFEFFF752 +:10318000A1FEFFF7BBFEFFF7EFFEFFF725FFFFF7FE +:103190006FF8844A3523D362D36A01335B08013B5D +:1031A000D363D36A5B00013302F5A032D362D36AE2 +:1031B00001335B08013B53634CE07B4B1B78002BD6 +:1031C0004FD17A4A52E8003F43F4807342E800311D +:1031D0000029F6D1754A52E8003F43F0200342E847 +:1031E00000310029F6D1714A02F1080353E8003F8B +:1031F00043F00103083242E800310029F3D16C4B5F +:10320000002283F8252320225A60674B01221A707E +:1032100027E0684B00221A70674B5A681A61FEF764 +:103220002BFC664B1B78022B00F01C84032B00F058 +:103230004F84012B09D1624C02212046FFF792FCFA +:103240000023237063705D4A13705E4B1B78012B63 +:1032500000F040844FF480715B4802F095FC012837 +:10326000ABD05A4B1B78092BDBD801A252F823F0C4 +:10327000133200089932000803330008393300087C +:10328000693300087933000895330008F9330008E2 +:103290004D350008933500084D4C0D212046FFF7B1 +:1032A000CDFB4C4B18802046FFF7D4FB70B9444A45 +:1032B000137843F004031370444B02221A703D4B01 +:1032C00000221A703D4B01221A70AAE7424A136885 +:1032D00043F04003136002F58E32136843F040035D +:1032E00013603E4B3E4A3F492046FFF72BFA3E4BC8 +:1032F0001A683E4B1A600723344A13702D4A137024 +:10330000E0E72D4B5A681A61FEF7B6FBFEF7B0FFF7 +:10331000314A136823F04003136002F58E321368BC +:1033200023F0400313600023284A1370214A1370CE +:10333000224B01221A7074E72D48FFF7CDFB82B2B1 +:103340002C4B1A801E490B7803430B7042B91B4B60 +:1033500003221A700023174A13701C4A137060E787 +:10336000164B01221A70F5E7144B02221A70114B0A +:103370001A78164B1A7054E7FFF7D4FB104A1378EB +:10338000034313700D4B01221A700A4B1A780F4B2E +:103390001A7046E7094B01221A70064B1A780B4B3C +:1033A0001A703EE700080040D702002000100140DC +:1033B00000E100E0FF020020C0010020FE0200202A +:1033C000FC020020D902002000000240000300207F +:1033D00090020020D0020020003800402C02002083 +:1033E0006002002070020020300300202C03002027 +:1033F000B0020020CE0200207A4B5A681A61FEF714 +:103400003BFB794B1B68794A126893427FF609AF00 +:10341000764A13600120FEF71FFA754F38810120AC +:10342000FEF71AFA38810220FEF716FA714E308143 +:103430000220FEF711FA30810320FEF70DFA032077 +:10344000FEF70AFA38800420FEF706FA0420FEF799 +:1034500003FA3080DFF8D081012239464046FEF77A +:10346000F7F80146644D28800320FFF7BFF8DFF826 +:10347000B491022231464846FEF7EAF80146288018 +:103480000420FFF7B3F83B895C4C63803389A38049 +:10349000B8F80C100120FFF7A9F8B9F80C100220B9 +:1034A000FFF7A4F80020FFF769F828800120FFF754 +:1034B00065F82880E0810120FFF760F828802082ED +:1034C0000120FFF75BF8288060820120FFF756F8A3 +:1034D0002880A0820120FFF751F82880E082022096 +:1034E000FFF74CF828800320FFF748F828800420D5 +:1034F000FFF744F8288020830520FFF73FF8288055 +:103500003F4B1B683F4A1360E3801B0C23813B88C1 +:1035100063813388A3813C4BDB7A012B03D03B4B87 +:1035200007221A707DE602340D212046FFF786FA45 +:103530000346374A1080A01E8383FFF7AFFA034685 +:10354000288034490A7813430B70E8E73248FFF7C4 +:1035500081FA70B92F4A137843F0040313702F4B8C +:1035600002221A70294B00221A702D4B01221A7068 +:1035700057E6254B2B4A2C492748FDF7B5FF204B32 +:103580001A682A4B1A600923244A13701F4A1370C1 +:10359000EBE7144B1B78012B54D0022B00F0378142 +:1035A000114B1B68114A1268934200F20882204BAB +:1035B0001B78002BFBD0FEF75FFA0A4BDB8A032B4C +:1035C0000BD91C4B1A681C4BDA60064B1B7D1B4A3F +:1035D000A2FB0323DB081A4A13600C4B09221A7062 +:1035E0001FE600BFC00100201803002014030020C4 +:1035F0000C02002000020020CE020020B0020020B9 +:1036000030030020280300202C020020FF020020AD +:10361000D0020020FC0200209002002000030020C5 +:10362000FE02002060020020700200202C03002017 +:10363000D60200200403002008040020CDCCCCCC0E +:1036400008030020AD4BD3ED077AFCEEE77A17EEC6 +:10365000903A99B20220FEF7C9FF0320FEF7FCF86A +:103660000320FEF7F9F8A64C20800420FEF7F4F8BA +:103670000420FEF7F1F8A34D288001222146A2483C +:10368000FDF7E6FF0146A14C20800320FEF7AEFFC8 +:10369000022229469E48FDF7DBFF014620800420D8 +:1036A000FEF7A4FF9B4C01228021204602F073FA12 +:1036B00000228021204602F06EFA974804F0C8F8F4 +:1036C000002875D18D4B93ED027AD3ED047A37EE55 +:1036D000677AD3ED036AC7EE267AB2EE047A67EE14 +:1036E000877AFCEEE77ACDED017A9DF80460DFF889 +:1036F00054920021484604F0DDFCDFF84C8208219A +:10370000404604F0D7FC854F3B6823F008033B603C +:10371000834D2B6823F008032B6000247C626C62CD +:103720002146484604F01AFC0821404604F016FCE5 +:10373000EB6A143B6B627C622546704BD3ED047AD6 +:1037400093ED027AF4EEC77AF1EE10FA37D5754BA5 +:103750001B78002BF1D0FCEEE77A17EE903A99B285 +:103760000120FEF743FF654BD3ED047A93ED037A16 +:1037700077EE877AC3ED047A00276B4B1F60694BA5 +:103780001F70DFF8C88101224FF40071404602F03B +:1037900002FA3A464FF40071404602F0FCF9B4FBDD +:1037A000F6F306FB13439BB21BB10134A4B2C4E78A +:1037B000FEE7E8B2FDF7BEFF0135ADB2F5E7574AC7 +:1037C000D36843F00103D360FEF756F94B4CD4EDB8 +:1037D000017AC4ED047AFCEEE77A17EE903A99B2DA +:1037E0000120FEF703FFE38A032B0CD94A4AD06875 +:1037F0004E49086042F20F71D160013B642202FB26 +:1038000003F34B4A1360444804F022F8C8E63B4BEC +:10381000D3ED077AFCEEE77A17EE903A99B20120E1 +:10382000FEF7E4FE0320FEF717F80320FEF714F876 +:10383000334C20800420FEF70FF80420FEF70CF82C +:10384000304D2880012221462F48FDF701FF014617 +:103850002E4C20800320FEF7C9FE022229462C4868 +:10386000FDF7F6FE014620800420FEF7BFFE314B37 +:1038700002221A7000229A721A814FF47A721A8107 +:103880002D4A5A6080225A802C4B42F21072DA6222 +:103890002B4803F0DDFF78BB012280211D4802F098 +:1038A0007AF942F21073013BFDD1002280211948C0 +:1038B00002F071F91F4B02229A72174803F0C8FFF9 +:1038C000D8B90E4BD3ED047A93ED027AF4EEC77AB1 +:1038D000F1EE10FA3CD5134B1B78002BF1D0074BBF +:1038E00093ED037A77EE277AC3ED047A00230E4A2C +:1038F00013600C4A1370E4E7FEE7FEE7C001002006 +:103900000C0200200002002070020020CE020020E5 +:1039100060020020000C0240080400200048014022 +:1039200000080040D60200200C0300200403002001 +:1039300008030020F40100200004024000040140BC +:1039400054040020BC030020A00400200018024002 +:103950006C4803F068FF6C4C01228021204602F085 +:103960001AF900228021204602F015F9674803F079 +:10397000B7FF674B00225A62FEF77EF8654CD4ED24 +:10398000017AC4ED047AFCEEE77A17EE903A99B228 +:103990000220FEF72BFEE38A032B0CD9594AD0688C +:1039A0005D49086042F20F71D160013B642202FB65 +:1039B00003F35A4A1360534803F04AFFF0E5584AAC +:1039C00013600120FDF748FF564E30810120FDF7BE +:1039D00043FF30810220FDF73FFF534F3881022023 +:1039E000FDF73AFF38813389504C6380A080002076 +:1039F000FEF7C4FD4E4D28800120FEF7BFFD288054 +:103A0000E0810120FEF7BAFD288020820120FEF728 +:103A1000B5FD288060820120FEF7B0FD2880A082DD +:103A20000120FEF7ABFD2880E0820220FEF7A6FD14 +:103A300028800320FEF7A2FD28800420FEF79EFDCB +:103A4000288020830520FEF799FD2880394B1B68CC +:103A5000394A1360E3801B0C2381338863813B88E0 +:103A6000A381A4E5354C0D212046FEF7E7FF344B3A +:103A70001880608300230BE02C4A32F81320590091 +:103A8000304800F813200131120A425401339BB22E +:103A90000E2BF1D91E20FFF77BF82B4B00221A705A +:103AA000FFF7D3BB214A32F813205900254800F80C +:103AB00013200131120A425401339BB20E2BF1D96B +:103AC0001E20FFF765F8204B00221A70FFF7BDBBE0 +:103AD0000023F3E7174B1B681C4A12689B1A642BE0 +:103AE0007FF6B8AB00221A4B1A801A490B7843F0C4 +:103AF00002030B70144B01211970174B1A70FFF75A +:103B0000A9BB00BF08040020000C024054040020A0 +:103B100000040140C001002004030020080300202D +:103B2000140300200C02002000020020B00200203C +:103B3000CE0200203003002028030020B202002023 +:103B4000D0020020DC020020FE020020240300201E +:103B5000D4020020FC020020D902002000B583B06E +:103B6000009313460A460146034803F089F800B162 +:103B7000012003B05DF804FBEC04002000B583B025 +:103B8000009313460A460146034803F09DF900B12D +:103B9000012003B05DF804FBEC04002008B50348E5 +:103BA00003F0D0FC043818BF012008BDEC0400204D +:103BB00008B50146014803F052FC08BDEC040020A2 +:103BC00000B583B001238DF8073000F0ADF810B9CF +:103BD00000238DF807309DF8070003B05DF804FB63 +:103BE00038B5FFF7EDFF012802D00225284638BD81 +:103BF0000446074803F018FC05460028F6D14FF4A8 +:103C00000061034803F03EFC0028EFD02546EDE7B5 +:103C1000EC04002008B5074B01221A70FFF7BEFF25 +:103C200020B9044A137803F0FE031370014B18788F +:103C300008BD00BF5000002010B50446074B01220C +:103C40001A70FFF7CDFF10B1044B187810BD204655 +:103C5000FFF7E0FF014B1870F6E700BF50000020AF +:103C600008B5FFF7D7FF08BD08B5084611461A4644 +:103C70004FF0FF33FFF772FF30B9FFF78FFF0346B6 +:103C80000028FAD1184608BD0123FBE708B508460D +:103C900011461A464FF0FF33FFF770FF30B9FFF7B8 +:103CA0007DFF03460028FAD1184608BD0123FBE733 +:103CB00030B589B0134B187810F001041BD11546AC +:103CC00003291CD8DFE801F002040A100C4613E0B7 +:103CD0006846FFF76DFF069B2B600DE06846FFF717 +:103CE00067FF079B2B8007E06846FFF761FF079B94 +:103CF0005B0A2B6000E00324204609B030BD042499 +:103D0000FAE700BF5000002008B50349034806F059 +:103D100067FB034B187008BD0006002064AC000868 +:103D2000040600200020704708B50121034801F077 +:103D30002BFF08B9012008BD0020FCE7000C024061 +:103D4000FEE7FEE7FEE7FEE7FEE7704770477047D5 +:103D500008B502F015F808BD08B5034800F031FEBB +:103D6000024800F02EFE08BDB805002070050020B6 +:103D700008B5084A136801331360074A1268934272 +:103D800003D0064803F0CBFD08BD054B01221A7095 +:103D9000F7E700BF0C030020080300200804002000 +:103DA000D602002008B5094B1A6842F008021A60D2 +:103DB00007490A6842F008020A60DA6822F0010244 +:103DC000DA60044803F0ABFD08BD00BF00480140C5 +:103DD00000080040BC0300207047000010B5114BE4 +:103DE0009B7A022B0ED0032B18D100210220FEF764 +:103DF000FDFB0C4C00226188606801F0CCFE0223C0 +:103E0000A3720BE0074C21890220FEF7EFFB012291 +:103E10006188606801F0BFFE0323A372024803F0CB +:103E20007EFD10BDF4010020540400207047000006 +:103E300008B5094B1B6913F0010F0BD0064B6FF04F +:103E400001021A61054A1368013313600221044814 +:103E500001F0A7FE08BD00BF0010004030030020A5 +:103E6000000C0240064B1B6913F0010F07D0044BF6 +:103E70006FF001021A61034A13680133136070473F +:103E8000001400401803002010B4974B5A6AD2B2B5 +:103E9000964B1A70964B1B881F2B00F20B81DFE8A4 +:103EA00013F020002F00090109010901090109018E +:103EB00009010901090109010901090109010901B2 +:103EC00009010901090109010901090109010901A2 +:103ED0000901090109010901090109019500090107 +:103EE000CF0084490868844908608449012008702B +:103EF00083490A8003447E4A13805DF8044B70476F +:103F00007F490B8803EB02239BB20B8044F24442AF +:103F1000934237D00FD842F22222934220D043F26C +:103F20003332934225D041F21112934240D1704B6B +:103F300002221A80E1E746F2666293422BD047F2F2 +:103F40007772934230D045F25552934230D10023DC +:103F5000674A1380694A13706A4B05221A70CCE7CE +:103F60000023634A1380654A1370664B02221A705D +:103F7000C3E700235E4A1380604A1370614B03223B +:103F80001A70BAE700235A4A13805C4A13705D4BDB +:103F900004221A70B1E70023554A1380574A137060 +:103FA000584B06221A70A8E7514B02221A80A4E748 +:103FB00000234F4A1380514A1370534A137843F039 +:103FC000020313704F4B02221A7096E74C4908887F +:103FD00041F21111884212D013F0010F2AD0590872 +:103FE00001394A4C34F8110000EB022224F8112068 +:103FF00001333F4A1380464B00221A707DE713F0CD +:10400000010F11D05B08013B404830F8131001EB61 +:10401000022220F813203B4B01221A700023344A5D +:104020001380364A137068E75B08013B374921F873 +:104030001320F0E759080139344820F81120D7E758 +:104040002F49088847F27771884212D013F0010F88 +:104050002AD0590801392D4C34F8110000EB022206 +:1040600024F811200133224A1380294B00221A70B0 +:1040700043E713F0010F11D05B08013B234830F8F0 +:10408000131001EB022220F813201E4B08221A7095 +:104090000023174A1380194A13702EE75B08013B6F +:1040A0001A4921F81320F0E759080139174820F878 +:1040B0001120D7E713F0010F0FD059080139134C25 +:1040C00034F8110000EB022224F811200133084AD1 +:1040D00013800F4B00221A700FE7590801390B4863 +:1040E00020F81120F2E700BF00100140010300207A +:1040F000D40200203003002024030020D902002035 +:10410000D202002000030020FC02002090020020C8 +:10411000FE02002000B583B0304BDB6913F0200FA6 +:1041200007D02E4B1B6813F0200F02D0FFF7ACFE18 +:1041300033E02A4BDB6913F0080F25D1274BDB69ED +:1041400013F0020F2CD1254BDB6913F0040F31D192 +:10415000224BDB6913F0010F36D1214BDB6913F0E1 +:10416000400F1AD01E4B1B6813F0400F15D01B4B8D +:1041700040221A62194A52E8003F23F0400342E805 +:1041800000310029F6D108E0144B5B6A9DF8072046 +:1041900052FA83F3DBB28DF8073003B05DF804FB0D +:1041A0000E4B5B6A9DF8072052FA83F3DBB28DF861 +:1041B0000730F2E7094B5B6A9DF8072052FA83F358 +:1041C000DBB28DF80730E8E7044B5B6A9DF8072007 +:1041D00052FA83F3DBB28DF80730DEE700100140BE +:1041E00000140140024B4FF00062DA60704700BFDC +:1041F0000064024008B50A4B5B6813F0006F09D1F8 +:10420000074B5B6813F0007F03D0054B4FF0007243 +:10421000DA6008BDFFF7E6FF024B00221A70F8E7EC +:1042200000640240D802002082B00A4B1A6C42F0AF +:1042300080521A641A6C02F080520092009A5A6CF2 +:1042400042F480425A645B6C03F480430193019B07 +:1042500002B070470038024030B58DB0002307939C +:10426000089309930A930B930368384A934204D046 +:10427000374A934246D00DB030BD364B5A6C42F4AB +:1042800080725A645A6C02F480720192019A1A6B1D +:1042900042F004021A631A6B02F004020292029ABC +:1042A0001A6B42F001021A631A6B02F001020392C8 +:1042B000039A1A6B42F002021A631B6B03F00203AB +:1042C0000493049B03240794089407A9224801F04F +:1042D00059FB0423079308940025099507A91F4853 +:1042E00001F050FB07940894099507A91C4801F0B8 +:1042F00049FB2A462946122001F0DEFC122001F07B +:10430000EBFCB8E7134B5A6C42F480625A645A6C67 +:1043100002F480620592059A1A6B42F020021A6339 +:104320001B6B03F020030693069B202307930323B4 +:10433000089307A90B4801F025FB00221146122023 +:1043400001F0BAFC122001F0C7FC94E70020014004 +:1043500000220140003802400008024000000240F4 +:104360000004024000140240F0B5ADB00446002144 +:104370002791289129912A912B91902203A8FCF74B +:10438000EBF92268224B9A4201D02DB0F0BD4FF4D8 +:104390002003039303A800F0F5FF002835D11D4B3F +:1043A0005A6C42F400625A645A6C02F40062009241 +:1043B000009A1A6B42F004021A631A6B02F00402AC +:1043C0000192019A1A6B42F008021A631B6B03F008 +:1043D00008030293029B4FF4F85327930227289770 +:1043E0000026299603252A950C242B9427A90A48F0 +:1043F00001F0C8FA04232793289729962A952B942D +:1044000027A9064801F0BEFABFE7FEF7E1FBC6E7C1 +:10441000002C01400038024000080240000C02401D +:1044200000B585B00368294A93420BD0284A9342CD +:1044300013D0284A934223D0274A934233D005B061 +:104440005DF804FB254B1A6C42F004021A641B6CE5 +:1044500003F004030093009BF1E7204B5A6C42F0F9 +:1044600002025A645B6C03F002030193019B002279 +:1044700011462C2001F020FC2C2001F02DFCDEE761 +:10448000164B5A6C42F400325A645B6C03F40033EE +:104490000293029B00221146192001F00DFC192005 +:1044A00001F01AFCCBE70D4B5A6C42F480225A649F +:1044B0005B6C03F480230393039B002211461A20B4 +:1044C00001F0FAFB1A2001F007FCB8E700080040F1 +:1044D000000401400044014000480140003802400F +:1044E00000B589B0002303930493059306930793C3 +:1044F00003681A4A934205D0194A934217D009B06B +:104500005DF804FB174B1A6B42F002021A631B6B37 +:1045100003F002030193019B4FF480730393022382 +:104520000493079303A9104801F02CFAE7E70D4B19 +:104530001A6B42F002021A631B6B03F00203029330 +:10454000029B4FF400730393022304930323079306 +:1045500003A9054801F016FAD1E700BF00080040A2 +:1045600000480140003802400004024010B5ACB0E1 +:10457000044600212791289129912A912B9190227C +:1045800003A8FCF7E9F82268174B9A4201D02CB037 +:1045900010BD4FF40053039303A800F0F3FE00BBDB +:1045A000124B1A6C42F000421A641A6C02F000427C +:1045B0000192019A1A6B42F010021A631B6B03F00E +:1045C00010030293029B03232793022228920022C6 +:1045D00029922A9308232B9327A9054801F0D2F9A1 +:1045E000D5E7FEF7F5FADBE7007C00400038024033 +:1045F000001002404A4B5A6822F440325A605A680E +:1046000041680A435A600268536823F48073536018 +:1046100002685368016943EA0123536002685368E2 +:1046200023F0407353600268536881680B43536002 +:104630000268936823F40063936002689368C1681A +:104640000B439360826A374B9A4257D00268936853 +:1046500023F07063936002689368816A0B439360F0 +:104660000268936823F04053936002689368C16ABC +:104670000B4393600268936823F00203936002681F +:104680009368816943EA4103936090F82030002BDE +:104690003FD00268536843F4006353600268536874 +:1046A00023F46043536001684B68426A013A43EA6D +:1046B00042334B600268D36A23F47003D36201680B +:1046C000CB6AC269013A43EA0253CB62026893683B +:1046D00023F4007393600268936890F8301043EA03 +:1046E000412393600268936823F4806393600268B7 +:1046F0009368416943EA8123936070470268936835 +:1047000023F0706393600268936823F040539360D2 +:10471000B0E70268536823F400635360CAE700BF40 +:10472000002301400100000F28B310B50446036CBC +:1047300043B1236C13F0100F0BD00120002384F839 +:104740003C3010BDFFF788FD0023636484F83C30E3 +:10475000EFE7226C094B134043F002032364204629 +:10476000FFF748FF00206064236C23F0030343F04D +:1047700001032364E2E70120704700BFFDEEFFFF65 +:1047800082B00023019390F83C30012B7ED00123AE +:1047900080F83C3003689A6812F0010F13D19A68D0 +:1047A00042F001029A603D4B1B683D4AA2FB032385 +:1047B0009B0C03EB4303019302E0019B013B01933C +:1047C000019B002BF9D103689A6812F0010F52D0B7 +:1047D000016C344A0A4042F4807202645A6812F44E +:1047E000806F05D0026C22F4405242F48052026481 +:1047F000026C12F4805F19D0426C22F0060242640F +:10480000002280F83C206FF022021A60264B5B6881 +:1048100013F01F0F0DD103689A6812F0405F37D173 +:104820009A6842F080429A6000202DE000224264A3 +:10483000E6E703681D4A93420AD01B4B5B6813F0FE +:10484000100F27D103681A4A93420AD000201BE0B8 +:104850009A6812F0405FF0D19A6842F080429A6004 +:10486000EBE79A6812F0405F16D19A6842F08042F6 +:104870009A60002008E0036C43F010030364436C6B +:1048800043F001034364002002B070470220FBE7BD +:104890000020F9E70020F7E70020F5E758000020A6 +:1048A00083DE1B43FEF8FFFF002301400020014090 +:1048B0000022014090F83C30012B17D0012380F8F2 +:1048C0003C300268936823F00103936003689B689F +:1048D00013F0010F05D1026C054B134043F00103A7 +:1048E0000364002380F83C3018467047022070476C +:1048F000FEEEFFFF70B504460D4603689A6812F499 +:10490000806F03D09B6813F4807F19D101F044FAC3 +:10491000064623681A6812F0020F20D1B5F1FF3F56 +:10492000F7D0B5B923681B6813F0020FF1D1236CDF +:1049300043F004032364002384F83C30032033E075 +:10494000036C43F020030364002380F83C30012013 +:104950002AE001F021FA801BA842DAD9E2E76FF0E1 +:1049600012021A60236C43F40073236423689A686C +:1049700012F0405F17D1A269BAB9DA6A12F4700F67 +:1049800003D09B6813F4806F11D1236C23F48073E0 +:104990002364236C13F4805F0BD1236C43F0010379 +:1049A0002364002000E0002070BD0020FCE7002010 +:1049B000FAE70020F8E70368D86C70477047704743 +:1049C000704770B5044603681E685D68C5F3401201 +:1049D00012EA56022CD0026C12F0100F03D1026CB6 +:1049E00042F4007202649A6812F0405F19D1A26921 +:1049F000BAB9DA6A12F4700F03D09A6812F4806FB1 +:104A00000FD15A6822F020025A60236C23F480737D +:104A10002364236C13F4805F03D1236C43F0010300 +:104A200023642046FFF7CAFF23686FF012021A6062 +:104A3000C5F3C01313EA960335D0236C13F0100F9F +:104A400003D1236C43F40053236423689A6812F45F +:104A5000401F21D19A6B12F4401F03D09A6812F4C0 +:104A6000806F19D15A6812F4806F15D19A6812F0CC +:104A7000405F11D1A2697AB95A6822F080025A6067 +:104A8000236C23F480532364236C13F4807F03D1BD +:104A9000236C43F001032364204600F01FF92368D0 +:104AA0006FF00C021A60C5F380131E4204D0236815 +:104AB0001B6813F0010F05D1C5F3806515EA561583 +:104AC0000CD170BD236C43F4803323642046FFF780 +:104AD00076FF23686FF001021A60EDE7636C43F024 +:104AE0000203636423686FF020051D602046FFF712 +:104AF00067FF23681D60E4E730B482B000220192B2 +:104B000090F83C20012A00F0DC800346012280F866 +:104B10003C200A68B2F1004F18BF092A22D9046864 +:104B2000E06892B202EB42021E3A4FF0070C0CFA18 +:104B300002F220EA0202E2600A68634882420AD076 +:104B40001D68E8688C6892B202EB42021E3A9440FB +:104B50002043E8601CE01868C2688C6842EA04627E +:104B6000C26015E00468206992B202EB42024FF085 +:104B7000070C0CFA02F220EA020222611C6820698A +:104B80000A8802EB42028D6805FA02F202432261B2 +:104B90004A68062A29D81C68606B02EB8202053A33 +:104BA0004FF01F0C0CFA02F220EA020262631C684A +:104BB000606B4A6802EB8202053AB1F800C00CFA59 +:104BC00002F2024362631868404A90423DD018687E +:104BD0003E4A904243D018683C4A90424CD0002054 +:104BE00083F83C0002B030BC70470C2A16D81D6810 +:104BF000286B02EB8202233A1F2404FA02F220EA15 +:104C000002022A631D68286B4A6802EB8202233A7B +:104C10000C8804FA02F202432A63D4E71D68E86AAA +:104C200002EB8202413A1F2404FA02F220EA020255 +:104C3000EA621D68E86A4A6802EB8202413A0C881F +:104C400004FA02F20243EA62BDE70A68B2F1004FD9 +:104C5000BDD11F48426822F440024260B7E70A68AB +:104C6000122AB8D11A4A506820F4000050605068E7 +:104C700040F480005060AEE70A681348112A18BF5C +:104C80008242ACD1124A506820F4800050605068D3 +:104C900040F40000506009680B4A91429FD10D4AD0 +:104CA00012680D49A1FB0212920C02EB8202520023 +:104CB000019202E0019A013A0192019A002AF9D187 +:104CC0008DE702208EE700BF120000100020014097 +:104CD000002301405800002083DE1B437047000082 +:104CE000002800F0068270B582B00446036813F015 +:104CF000010F29D0954B9B6803F00C03042B1AD0AD +:104D0000924B9B6803F00C03082B0FD06368B3F53C +:104D1000803F40D0002B54D18C4B1A6822F4803253 +:104D20001A601A6822F480221A6039E0874B5B68A7 +:104D300013F4800FEAD0854B1B6813F4003F03D0B7 +:104D40006368002B00F0D781236813F0020F74D042 +:104D50007E4B9B6813F00C0F5ED07C4B9B6803F07E +:104D60000C03082B53D0E368002B00F08980774AAE +:104D7000136843F00103136001F00EF80546734B0E +:104D80001B6813F0020F72D101F006F8401B0228D5 +:104D9000F5D90320B4E16D4A136843F480331360FE +:104DA00063682BB300F0F8FF0546684B1B6813F4EB +:104DB000003FC9D100F0F0FF401B6428F5D9032063 +:104DC0009EE1B3F5A02F09D0604B1A6822F480321F +:104DD0001A601A6822F480221A60E1E75B4B1A68B5 +:104DE00042F480221A601A6842F480321A60D7E7CF +:104DF00000F0D2FF0546554B1B6813F4003FA3D0CB +:104E000000F0CAFF401B6428F5D9032078E14F4B1E +:104E10005B6813F4800FA6D14C4B1B6813F0020F94 +:104E200003D0E368012B40F06881484A136823F0FF +:104E3000F803216943EAC1031360236813F0080FE4 +:104E400046D0636983B3414A536F43F0010353670C +:104E500000F0A2FF05463D4B5B6F13F0020F37D108 +:104E600000F09AFF401B0228F5D9032048E1374A99 +:104E7000136823F0F803216943EAC1031360DCE7F8 +:104E8000324A136823F00103136000F085FF0546E2 +:104E90002E4B1B6813F0020FCFD000F07DFF401B9C +:104EA0000228F5D903202BE1284A536F23F0010390 +:104EB000536700F071FF0546244B5B6F13F0020F40 +:104EC00006D000F069FF401B0228F5D9032017E146 +:104ED000236813F0040F7DD01C4B1B6C13F0805F14 +:104EE0001ED11A4B1A6C42F080521A641B6C03F0EC +:104EF00080530193019B0125154B1B6813F4807FA0 +:104F000010D0A368012B25D0002B3BD10F4B1A6F7B +:104F100022F001021A671A6F22F004021A671EE0DB +:104F20000025E9E70A4A136843F48073136000F030 +:104F300033FF0646064B1B6813F4807FE1D100F077 +:104F40002BFF801B6428F5D90320D9E000380240EC +:104F500000700040724A136F43F001031367A368A7 +:104F600033B300F019FF06466D4B1B6F13F0020FB1 +:104F70002FD100F011FF801B41F288339842F3D902 +:104F80000320BDE0052B09D0654B1A6F22F001020A +:104F90001A671A6F22F004021A67E0E7604B1A6F73 +:104FA00042F004021A671A6F42F001021A67D6E74C +:104FB00000F0F2FE06465A4B1B6F13F0020F08D0AA +:104FC00000F0EAFE801B41F288339842F3D90320B7 +:104FD00096E0FDB9A369002B00F09180504A9268D9 +:104FE00002F00C02082A59D0022B19D04C4A13683F +:104FF00023F08073136000F0CFFE0446484B1B681B +:1050000013F0007F48D000F0C7FE001B0228F5D93E +:10501000032075E0424A136C23F080531364D9E7F0 +:105020003F4A136823F08073136000F0B5FE054615 +:105030003B4B1B6813F0007F06D000F0ADFE401B19 +:105040000228F5D903205BE0E369226A1343626A10 +:1050500043EA8213A26A5208013A43EA0243E26A2F +:1050600043EA0263226B43EA02732D4A53601368DA +:1050700043F08073136000F08FFE0446284B1B68DA +:1050800013F0007F06D100F087FE001B0228F5D93F +:10509000032035E0002033E0002031E0204A526850 +:1050A000012B2FD002F48003E1698B422CD102F056 +:1050B0003F03216A8B4229D1616A47F6C0731340CE +:1050C000B3EB811F24D102F44031A36A5B08013B9A +:1050D000B1EB034F1ED102F07063E16AB3EB016FD5 +:1050E0001AD102F0E042236BB2EB037F16D100200D +:1050F00006E001207047012002E0012000E00020CE +:1051000002B070BD0120FBE70120F9E70120F7E7BD +:105110000120F5E70120F3E70120F1E70120EFE7A7 +:105120000038024008B5264B9B6803F00C03042BA3 +:1051300041D0082B41D1224B5A6802F03F025B68F4 +:1051400013F4800F12D01E4B5968C1F388111D480B +:105150000023A1FB0001FBF7F9FF194B5B68C3F3C8 +:10516000014301335B00B0FBF3F008BD144B5868FA +:10517000C0F388104FEA401CBCEB000C6EEB0E0E27 +:105180004FEA8E1343EA9C634FEA8C11B1EB0C019A +:1051900063EB0E03DB0043EA5173C90011EB000C13 +:1051A00043F10003990200234FEA8C2041EA9C510D +:1051B000FBF7CCFFD1E70348D7E70348D5E700BFAB +:1051C0000038024040787D010024F400002800F0FF +:1051D000A08070B50D460446524B1B6803F00F03C8 +:1051E0008B420BD24F4A136823F00F030B4313601B +:1051F000136803F00F038B4240F08D80236813F097 +:10520000020F17D013F0040F04D0474A936843F4F9 +:10521000E0539360236813F0080F04D0424A936868 +:1052200043F460439360404A936823F0F003A1681D +:105230000B439360236813F0010F31D06368012B97 +:1052400020D0022B25D0384A126812F0020F64D009 +:1052500035498A6822F0030213438B6000F09CFDFD +:105260000646314B9B6803F00C036268B3EB820F78 +:1052700016D000F091FD801B41F288339842F0D99E +:10528000032045E0284A126812F4003FE0D10120D3 +:105290003EE0254A126812F0007FD9D1012037E0A4 +:1052A000204B1B6803F00F03AB420AD91D4A136859 +:1052B00023F00F032B431360136803F00F03AB427B +:1052C0002DD1236813F0040F06D0174A936823F4F6 +:1052D000E053E1680B439360236813F0080F07D095 +:1052E000114A936823F46043216943EAC103936040 +:1052F000FFF718FF0C4B9B68C3F303130B4AD35CF7 +:10530000D8400B4B18600B4B186800F007FD0020CD +:1053100070BD012070470120FAE70120F8E7012065 +:10532000F6E700BF003C02400038024080AC0008B5 +:105330005800002054000020014B1868704700BF3F +:105340005800002008B5FFF7F7FF044B9B68C3F334 +:105350008223034AD35CD84008BD00BF0038024016 +:1053600078AC000808B5FFF7E7FF044B9B68C3F370 +:105370004233034AD35CD84008BD00BF0038024026 +:1053800078AC0008F0B583B00446066816F0010654 +:105390000DD0B54B9A6822F400029A609A68416B6E +:1053A0000A439A60436B002B00F067810026256852 +:1053B00015F4002511D0AC4AD2F88C3023F44013F8 +:1053C000E16B0B43C2F88C30E36BB3F5801F00F048 +:1053D0005681002B00F055810025236813F4801FAF +:1053E0000FD0A14AD2F88C3023F44003216C0B4338 +:1053F000C2F88C30236CB3F5800F00F0448103B900 +:105400000125236813F0807F00D0012613F0200FC0 +:1054100040F03B81236813F0100F0CD0924BD3F86F +:105420008C2022F08072C3F88C20D3F88C20A16BE2 +:105430000A43C3F88C20236813F4804F08D08A4AAB +:10544000D2F8903023F44033616E0B43C2F89030B1 +:10545000236813F4004F08D0834AD2F8903023F425 +:105460004023A16E0B43C2F89030236813F4803FB1 +:1054700008D07D4AD2F8903023F44013E16E0B43FC +:10548000C2F89030236813F4003F08D0764AD2F86F +:10549000903023F44003216F0B43C2F8903023680F +:1054A00013F0400F08D0704AD2F8903023F0030375 +:1054B000616C0B43C2F89030236813F0800F08D062 +:1054C000694AD2F8903023F00C03A16C0B43C2F868 +:1054D0009030236813F4807F08D0634AD2F890306C +:1054E00023F03003E16C0B43C2F89030236813F4CF +:1054F000007F08D05C4AD2F8903023F0C003216DC1 +:105500000B43C2F89030236813F4806F08D0564ADA +:10551000D2F8903023F44073616D0B43C2F89030A1 +:10552000236813F4006F08D04F4AD2F8903023F468 +:105530004063A16D0B43C2F89030236813F4805F81 +:1055400008D0494AD2F8903023F44053E16D0B4320 +:10555000C2F89030236813F4005F08D0424AD2F8B2 +:10556000903023F44043216E0B43C2F890302368FF +:1055700013F4800F08D03C4AD2F8903023F08063B7 +:10558000A16F0B43C2F89030236813F4001F0DD0B5 +:10559000354AD2F8903023F00063E16F0B43C2F834 +:1055A0009030E36FB3F1006F00F0D580236813F003 +:1055B000080F00D0012513F4802F08D02A4AD2F812 +:1055C000903023F04073616F0B43C2F89030236832 +:1055D00013F4000F09D0244AD2F8903023F08053FE +:1055E000D4F880100B43C2F89030236813F0806F1A +:1055F00009D01D4AD2F8903023F00053D4F884101B +:105600000B43C2F89030236813F0006F09D0164A9C +:10561000D2F88C3023F00073D4F888100B43C2F812 +:105620008C30236813F0805F09D00F4AD2F88C3099 +:1056300023F08063D4F88C100B43C2F88C3026B969 +:10564000236813F0007F00F00681074A136823F0F7 +:105650008063136000F0A0FB0646034B1B6813F049 +:10566000006F7AD002E000BF0038024000F094FBE7 +:10567000801B6428F1D90320F0E0012697E601267B +:10568000A7E60125A9E60126B9E67F4B1A6C42F090 +:1056900080521A641B6C03F080530193019B7B4A78 +:1056A000136843F48073136000F076FB0746774B72 +:1056B0001B6813F4807F06D100F06EFBC01B6428CA +:1056C000F5D90320CAE0704B1B6F13F4407315D05B +:1056D000226B02F440729A4210D06B4B1A6F22F484 +:1056E0004072196F41F480311967196F21F48031CC +:1056F00019671A671B6F13F0010F12D1236B03F4A4 +:105700004072B2F5407F1DD05F4A936823F4F813CE +:1057100093605D490B6F226BC2F30B0213430B675F +:1057200078E600F039FB0746574B1B6F13F0020F6A +:10573000E4D100F031FBC01B41F288339842F3D929 +:1057400003208BE05048826822F4F8125049194037 +:105750000A438260DDE7012528E7236813F0010F83 +:1057600013D0636B8BB9484AD2F88430D2F88410D6 +:10577000606803F4403343EA801301F070610B4327 +:10578000A16843EA0173C2F88430236813F4002F40 +:1057900003D0E26BB2F5801F06D013F4801F1ED039 +:1057A000236CB3F5800F1AD1374AD2F88430D2F87F +:1057B0008410606803F4403343EA8013E06843EAEE +:1057C000006301F0E0410B43C2F88430D2F88C3022 +:1057D00023F01F03616A01390B43C2F88C30236840 +:1057E00013F0807F11D0284AD2F88400D2F88410B8 +:1057F000666823691B0443EA861300F07060034364 +:1058000001F0E0410B43C2F88430236813F0007FBD +:105810000DD0626823691B0443EA8213E26843EAFD +:105820000263A26843EA0273174AC2F88430164A38 +:10583000136843F08063136000F0AEFA0646124B23 +:105840001B6813F0006F06D100F0A6FA801B6428D5 +:10585000F5D9032002E0012D02D0002003B0F0BDF5 +:10586000094A136823F08053136000F095FA054647 +:10587000054B1B6813F0005F0CD000F08DFA401B45 +:105880006428F5D90320E9E70038024000700040A1 +:10589000FFFCFF0F236813F4002F01D0E26B22B14D +:1058A00013F4801F1DD0236CDBB9354AD2F8883041 +:1058B000D2F88810606903F4403343EA8013A0698A +:1058C00043EA006301F0E0410B43C2F88830D2F8AC +:1058D0008C3023F4F853A16A013943EA0123C2F85A +:1058E0008C30236813F4001F03D0E36FB3F1006F13 +:1058F00031D0236813F0080F19D0214AD2F888104C +:10590000D2F88830606903F4403343EA801301F031 +:1059100070610B43E16943EA0173C2F88830D2F841 +:105920008C3023F44033E16A0B43C2F88C30144AC4 +:10593000136843F08053136000F02EFA0446104BB6 +:105940001B6813F0005F19D100F026FA001B6428D1 +:10595000F5D9032082E70A4AD2F88800D2F88810E5 +:105960006569236A1B0443EA851300F070600343F2 +:1059700001F0E0410B43C2F88830BAE700206DE740 +:105980000038024000230F2B00F2F48070B582B083 +:1059900066E085684FEA430E032404FA0EF425EA14 +:1059A0000405CC6804FA0EF42C438460446824EAAD +:1059B00002044A68C2F300129A40224342605DE04A +:1059C000DC08083450F8242003F00705AD004FF040 +:1059D0000F0E0EFA05FE22EA0E0E0A69AA4042EAEE +:1059E0000E0240F824205DE0092200E0002202FAC5 +:1059F0000EF22A430234604D45F824205F4A946831 +:105A00006FEA0C0224EA0C054E6816F4801F01D0E0 +:105A10004CEA0405594CA560E46802EA04054E68A6 +:105A200016F4001F01D04CEA0405544CE56064688C +:105A300002EA04054E6816F4003F01D04CEA040562 +:105A40004E4C6560246822404D6815F4803F01D0BB +:105A50004CEA0402494C226001330F2B00F288808B +:105A600001229A400C6804EA020C32EA0404F3D1E1 +:105A70004C6804F00304013C012C8AD94A6802F006 +:105A80000302032A09D0C4685D000322AA4024EA65 +:105A900002048A68AA402243C2604A6802F00302F4 +:105AA000022A8DD004684FEA430E032202FA0EF256 +:105AB00024EA02044A6802F0030202FA0EF22243C8 +:105AC00002604A6812F4403FC6D02D4A546C44F438 +:105AD00080445464526C02F480420192019A9C0802 +:105AE000A51C254A52F8255003F0030E4FEA8E0EEE +:105AF0000F2202FA0EF225EA0205224A90423FF4F2 +:105B000075AF02F58062904222D002F58062904229 +:105B100020D002F5806290421ED002F58062904251 +:105B20001CD002F5806290421AD002F58062904249 +:105B300018D002F58062904216D002F58062904241 +:105B400014D002F5806290423FF44EAF0A224EE735 +:105B500001224CE702224AE7032248E7042246E7F3 +:105B6000052244E7062242E7072240E708223EE7F3 +:105B700002B070BD704700BF00380140003C0140DA +:105B800000380240000002400369194201D00120A0 +:105B90007047002070470AB1816170470904816134 +:105BA0007047436901EA030221EA030141EA024125 +:105BB0008161704710B582B01B4B1A6C42F0805265 +:105BC0001A641B6C03F080530193019B174A1368FE +:105BD00043F48033136000F0DFF80446134B5B6836 +:105BE00013F4803F08D100F0D7F8001BB0F57A7F9E +:105BF000F4D9032002B010BD0C4A136843F40033FB +:105C0000136000F0C9F80446084B5B6813F4003FCA +:105C100007D100F0C1F8001BB0F57A7FF4D903205A +:105C2000E8E70020E6E700BF0038024000700040CF +:105C3000002804DB0901C9B2044B1954704700F075 +:105C40000F000901C9B2024B1954704700E400E08B +:105C500014ED00E000B500F00700C0F1070CBCF146 +:105C6000040F28BF4FF0040C031D062B0FD9C31ED1 +:105C70004FF0FF3E0EFA0CF021EA000199400EFAB7 +:105C800003FE22EA0E0241EA02005DF804FB002353 +:105C9000EEE700000649CB6823F4E0631B041B0C0D +:105CA000000200F4E0600343024A1A43CA607047EE +:105CB00000ED00E00000FA0510B50446054BD86879 +:105CC000C0F30220FFF7C6FF01462046FFF7B0FFF2 +:105CD00010BD00BF00ED00E0002807DB00F01F0250 +:105CE000400901239340024A42F82030704700BF28 +:105CF00000E100E00138B0F1807F0BD24FF0E023EB +:105D00005861054AF02182F823100020986107228B +:105D10001A6170470120704700ED00E010B504469D +:105D20000E4B1A784FF47A73B3FBF2F30C4A1068F7 +:105D3000B0FBF3F0FFF7DEFF68B90F2C01D90120AB +:105D40000AE0002221464FF0FF30FFF7B5FF054B78 +:105D50001C60002000E0012010BD00BF51000020A9 +:105D6000580000205400002008B50320FFF792FFE0 +:105D70000020FFF7D3FFFEF757FA002008BD000010 +:105D8000034A1168034B1B780B441360704700BF34 +:105D90000806002051000020014B1868704700BF22 +:105DA0000806002038B50446FFF7F6FF0546B4F1B3 +:105DB000FF3F02D0044B1B781C44FFF7EDFF401B54 +:105DC000A042FAD338BD00BF51000020034B9B68AE +:105DD000C3F30313024AD35CD84070470038024033 +:105DE00080AC0008034B9B68C3F38223024AD35C58 +:105DF000D84070470038024078AC0008034B9B68DD +:105E0000C3F34233024AD35CD840704700380240A3 +:105E100078AC00080D4B5B6803F480039BB90C4819 +:105E20000A4B5A6802F03F02B0FBF2F05A68C2F324 +:105E3000881202FB00F05B68C3F3014301335B008F +:105E4000B0FBF3F070470348EAE700BF00380240B8 +:105E50000024F40040787D0108B5074B9B6803F0EF +:105E60000C03042B04D0082B04D1FFF7D3FF08BD8B +:105E70000248FCE70248FAE70038024040787D011A +:105E80000024F40008B5032808D00C282ED0B0F563 +:105E9000406F53D030287AD0002008BD514BD3F842 +:105EA0009030034043EA00434F4A934208D0B3F195 +:105EB000031F0CD0013A934211D1FFF7CDFFECE75D +:105EC000484B186810F00200E7D04848E5E7454B1A +:105ED000186F10F00200E0D04FF40040DDE7FFF74C +:105EE000BBFFFFF773FFFFF789FFD6E73D4BD3F802 +:105EF0009030034043EA00433D4A934208D0B3F157 +:105F00000C1F0CD0043A934211D1FFF7A5FFC4E750 +:105F1000344B186810F00200BFD03448BDE7314B55 +:105F2000186F10F00200B8D04FF40040B5E7FFF74B +:105F300093FFFFF74BFFFFF755FFAEE7294BD3F871 +:105F40009030034043EA00432A4A934209D0B3F118 +:105F50000C2F0DD0A2F58062934211D1FFF77CFF88 +:105F60009BE7204B186810F0020096D01F4894E77A +:105F70001C4B186F10F002008FD04FF400408CE7DC +:105F8000FFF76AFFFFF722FFFFF738FF85E7154BA2 +:105F9000D3F89030034043EA0043174A934208D0B5 +:105FA000B3F1301F0DD0103A934213D1FFF754FFD5 +:105FB00073E70C4B186810F002003FF46EAF0B480B +:105FC0006BE7084B186F10F002003FF466AF4FF418 +:105FD000004062E7FFF740FFFFF7F8FEFFF702FF20 +:105FE0005BE700BF00380240020003000024F40019 +:105FF00008000C000008000C2000300008B5C02884 +:106000000AD0B0F5407F2FD0B0F5405F55D0B0F545 +:10601000404F7BD0002008BD524BD3F89030034056 +:1060200043EA0043504A934208D0B3F1C01F0CD05A +:10603000403A934211D1FFF70FFFECE7494B186844 +:1060400010F00200E7D04948E5E7464B186F10F022 +:106050000200E0D04FF40040DDE7FFF7FDFEFFF760 +:10606000B5FEFFF7BFFED6E73E4BD3F890300340B6 +:1060700043EA00433E4A934209D0B3F1032F0DD0C7 +:10608000A2F58072934211D1FFF7E6FEC3E7354BCC +:10609000186810F00200BED03448BCE7314B186FCE +:1060A00010F00200B7D04FF40040B4E7FFF7D4FE81 +:1060B000FFF78CFEFFF796FEADE72A4BD3F8903042 +:1060C000034043EA00432B4A934209D0B3F1302FF7 +:1060D0000DD0A2F58052934211D1FFF7BDFE9AE791 +:1060E000204B186810F0020095D0204893E71D4B14 +:1060F000186F10F002008ED04FF400408BE7FFF7CE +:10610000ABFEFFF763FEFFF76DFE84E7154BD3F898 +:106110009030034043EA0043174A934209D0B3F159 +:10612000C02F0ED0A2F58042934213D1FFF794FE08 +:1061300071E70C4B186810F002003FF46CAF0B488D +:1061400069E7084B186F10F002003FF464AF4FF49A +:10615000004060E7FFF780FEFFF738FEFFF742FEE2 +:1061600059E700BF003802408000C0000024F4005E +:106170000002000300200030008000C000B58368EA +:1061800091FAA1FCBCFA8CFC4FEA4C0C4FF0030EC8 +:106190000EFA0CFC23EA0C0391FAA1F1B1FA81F199 +:1061A00049008A40134383605DF804FB00B5C3686F +:1061B00091FAA1FCBCFA8CFC4FEA4C0C4FF0030E98 +:1061C0000EFA0CFC23EA0C0391FAA1F1B1FA81F169 +:1061D00049008A401343C3605DF804FB00B5036ABD +:1061E00091FAA1FCBCFA8CFC4FEA8C0C4FF00F0E1C +:1061F0000EFA0CFC23EA0C0391FAA1F1B1FA81F139 +:1062000089008A40134303625DF804FB00B5436ACA +:10621000090A91FAA1FCBCFA8CFC4FEA8C0C4FF0F5 +:106220000F0E0EFA0CFC23EA0C0391FAA1F1B1FA5D +:1062300081F189008A40134343625DF804FB00B595 +:10624000036891FAA1FCBCFA8CFC4FEA4C0C4FF0AD +:10625000030E0EFA0CFC23EA0C0391FAA1F1B1FA39 +:1062600081F149008A40134303605DF804FBF8B5EF +:1062700007460E460D6895FAA5F5B5FA85F519E0BD +:10628000B26821463846FFF779FF3268F1687B68CB +:1062900023EA020301FB02F213437B6016E07269FA +:1062A00021463846FFF7B2FF726821463846FFF7AD +:1062B000C6FF0135346834FA05F21BD00122AA402A +:1062C0001440F6D07368013B012BD9D932692146BD +:1062D0003846FFF76BFF7368022BE5D194FAA4F3FD +:1062E000B3FA83F3072BDAD8726921463846FFF7F1 +:1062F00075FFD9E70020F8BD0B4B1B680B4AA2FBCA +:1063000003235B0A41F2883202FB03F31A46013B86 +:106310003AB1426B12F0800FF8D0C523836300209E +:1063200070474FF00040704758000020D34D621076 +:1063300084B00DF1040C8CE80E000B461343039A55 +:106340001343049A1343059A1343069A134341686F +:10635000034A0A4013434360002004B0704700BF63 +:106360000081FFFFD0F8800070470B68C0F88030D4 +:10637000002070470323036000207047006800F08E +:10638000030070470B6883604B688A681343CA68D0 +:1063900013430A691343C2686FF30B021343C360CC +:1063A000002070470069C0B27047143040587047F1 +:1063B0000B6843624B6883628B68CA6813430A693F +:1063C00013434A691343C26A22F0F7021343C362BC +:1063D0000020704710B586B0044600230193029355 +:1063E000039304934FF48063059301A9FFF7CAFF59 +:1063F0002046FFF781FF06B010BD000038B5044607 +:106400000D46504B1B685049A1FB03135B0A03FB6D +:1064100002F21346013A002B5DD0636B13F0450F77 +:10642000F7D013F4006FF4D1636B13F0040F06D1AF +:10643000636B13F0010F05D00120A0634DE0042031 +:10644000A0634AE0C523A3632046FFF7ABFFA84241 +:1064500001D0012041E000212046FFF7A6FF0346BE +:106460003A481840C8B3002B38DB13F0804F38D1BE +:1064700013F0005F37D113F0805F36D113F0006F57 +:1064800036D113F0806F36D113F0807F36D113F4FC +:10649000000F36D113F4800F36D113F4001F36D11C +:1064A00013F4801F36D113F4802F36D113F4003F3C +:1064B00036D113F4803F36D113F4004F36D113F4A4 +:1064C000804F36D113F4005F36D113F0080F36D069 +:1064D0004FF4000001E04FF0004038BD4FF0007075 +:1064E000FBE74020F9E78020F7E74FF48070F4E7FE +:1064F0004FF40070F1E74FF48060EEE74FF4006076 +:10650000EBE74FF48050E8E74FF40050E5E74FF435 +:106510008040E2E74FF40040DFE74FF40030DCE773 +:106520004FF48020D9E74FF40020D6E74FF48010D5 +:10653000D3E74FF40010D0E74FF48000CDE74FF4DD +:106540008030CAE758000020D34D621008E0FFFDFC +:1065500030B587B00446019110250295402303937E +:10656000002304934FF48063059301A9FFF70AFF0A +:1065700041F2883229462046FFF740FF07B030BD80 +:1065800030B587B00446019111250295402303934D +:10659000002304934FF48063059301A9FFF7F2FEF3 +:1065A00041F2883229462046FFF728FF07B030BD68 +:1065B00030B587B00446019112250295402303931C +:1065C000002304934FF48063059301A9FFF7DAFEDB +:1065D00041F2883229462046FFF710FF07B030BD50 +:1065E00030B587B0044601911825029540230393E6 +:1065F000002304934FF48063059301A9FFF7C2FEC3 +:1066000041F2883229462046FFF7F8FE07B030BD38 +:1066100030B587B0044601911925029540230393B4 +:10662000002304934FF48063059301A9FFF7AAFEAA +:1066300041F2883229462046FFF7E0FE07B030BD20 +:1066400030B587B00446002301930C250295402203 +:10665000039204934FF48063059301A9FFF792FE20 +:10666000034A29462046FFF7C9FE07B030BD00BFE8 +:1066700000E1F50530B587B0044601920725029583 +:1066800040230393002304934FF48063059301A9EF +:10669000FFF778FE41F2883229462046FFF7AEFE2A +:1066A00007B030BD30B587B004460191372502955B +:1066B00040230393002304934FF48063059301A9BF +:1066C000FFF760FE41F2883229462046FFF796FE2A +:1066D00007B030BD30B587B004460191062502955C +:1066E00040230393002304934FF48063059301A98F +:1066F000FFF748FE41F2883229462046FFF77EFE2A +:1067000007B030BD30B587B0044600230193332570 +:1067100002954022039204934FF48063059301A9EC +:10672000FFF730FE41F2883229462046FFF766FE29 +:1067300007B030BD30B587B0044601910D250295F4 +:1067400040230393002304934FF48063059301A92E +:10675000FFF718FE41F2883229462046FFF74EFE29 +:1067600007B030BD0146144B1B68144AA2FB03233B +:106770005B0A41F2883202FB03F31A46013BBAB1CD +:106780004A6B12F0450FF8D012F4006FF5D14B6B45 +:1067900013F0040F06D1486B10F0010005D1C5239A +:1067A0008B637047042088637047012088637047BB +:1067B0004FF00040704700BF58000020D34D6210DA +:1067C00010B586B004460023019302220292C02233 +:1067D000039204934FF48063059301A9FFF7D2FD60 +:1067E0002046FFF7BFFF06B010BD10B586B00446C7 +:1067F000019109230293C0230393002304934FF4D0 +:106800008063059301A9FFF7BDFD2046FFF7AAFFAE +:1068100006B010BD0146104B1B68104AA2FB0323B3 +:106820005B0A41F2883202FB03F31A46013B82B154 +:106830004A6B12F0450FF8D012F4006FF5D1486B97 +:1068400010F0040002D1C5238B63704704208863D5 +:1068500070474FF00040704758000020D34D621041 +:1068600010B586B004460A4B0B43019329230293CB +:1068700040230393002304934FF48063059301A9FD +:10688000FFF780FD2046FFF7C5FF06B010BD00BF33 +:1068900000001080F8B505460E461746234B1B68CE +:1068A000234AA2FB03235B0A41F2883202FB03F373 +:1068B0001A46013B8AB36C6B14F0450FF8D014F400 +:1068C000006FF5D16B6B13F0040F06D16B6B13F0F7 +:1068D000010F05D00120A86321E00420A8631EE079 +:1068E0002846FFF75FFDB04201D0012017E0C52325 +:1068F000AB6300212846FFF758FD034610F46040C3 +:1069000008D013F4804F0BD113F4004F0BD04FF489 +:10691000805004E01B0C3B8001E04FF00040F8BDCC +:106920004FF40050FBE74FF48030F8E758000020A8 +:10693000D34D621070B586B004460D460023019316 +:10694000032602964022039204934FF4806305933A +:1069500001A9FFF717FD2A4631462046FFF79AFFA7 +:1069600006B070BD0146164B1B68164AA2FB0323F6 +:106970005B0A41F2883202FB03F31A46013BE2B1A3 +:106980004A6B12F0450FF8D012F4006FF5D14B6B43 +:1069900013F0040F0BD14B6B13F001030AD1486BBA +:1069A00010F040000BD040228A6318467047042044 +:1069B000886370470120886370474FF0004070473C +:1069C00058000020D34D621010B586B004464FF435 +:1069D000D573019308230293402303930023049368 +:1069E0004FF48063059301A9FFF7CCFC2046FFF725 +:1069F000B9FF06B010BD000070B582B00446002398 +:106A000001930068FFF7E6FC054610B1284602B086 +:106A100070BD2068FFF7D8FF38B90123A364A36CC9 +:106A2000012B0BD02E46284614E00023A3642068D7 +:106A3000FFF7D0FC0028F2D00546E7E700212068E8 +:106A4000FFF730FE0028EDD04FF08055DEE7019BC8 +:106A500001330193019A4FF6FE739A4213D896B907 +:106A600000212068FFF71EFEE0B912492068FFF7F9 +:106A7000F7FE0646C0B900212068FFF796FCC30F59 +:106A8000E5D01E46E3E7019A4FF6FE739A420ED810 +:106A900010F0804302D001236364B7E700226264F0 +:106AA0001D46B3E70546B1E74FF08055AEE74FF01E +:106AB0008075ABE7000010C1F0B589B004460F4601 +:106AC000FFF76AF906460023009301930821206826 +:106AD000FFF73EFD054610B1284609B0F0BD216D17 +:106AE00009042068FFF7DEFD05460028F4D14FF0C9 +:106AF000FF33029308230393302304930223059367 +:106B0000002306930123079302A92068FFF750FC96 +:106B10002068FFF7F7FD054658B1DDE7FFF722FCD7 +:106B20004DF825000135FFF737F9831BB3F1FF3F1F +:106B30003FD02068436B13F02A0F07D1436B13F447 +:106B4000001FEBD1436B13F4005FECD1436B13F0E8 +:106B5000080F25D1436B13F0020F24D1456B15F0BC +:106B6000200523D140F23A538363019A130203F4C0 +:106B70007F0343EA0263110A01F47F410B4343EAB6 +:106B800012633B60009A130203F47F0343EA02633B +:106B9000110A01F47F410B4343EA12637B609BE7D8 +:106BA0000825856398E70225856395E72025856399 +:106BB00092E74FF000458FE710B582B00446002100 +:106BC000009101910068FFF7F0FB10F0007F13D1F6 +:106BD00069462046FFF770FF80B9019B13F4802FB0 +:106BE0000ED0216D09042068FFF75CFD30B9022149 +:106BF0002068FFF76FFD01E04FF4006002B010BDA8 +:106C00004FF08060FAE710B582B004460021009191 +:106C100001910068FFF7C9FB10F0007F13D16946AE +:106C20002046FFF749FF80B9019B13F4803F0ED047 +:106C3000216D09042068FFF735FD30B90021206877 +:106C4000FFF748FD01E04FF4006002B010BD4FF0C7 +:106C50008060FAE770B581B104460E46016D090403 +:106C60000068FFF767FD054608B1284670BD0021A2 +:106C70002068FFF79AFB3060F7E74FF00065F4E714 +:106C80002DE9F04F87B005460C4616469B46DDF8C9 +:106C900040A0FFF781F8002C36D0814695F834707B +:106CA000FFB2012F40F004810023AB6306EB0B031E +:106CB000EA6D93422ED8032385F834302B680022E6 +:106CC000DA626B6C012B00D076024FF0FF33009339 +:106CD0004FEA4B2301939023029302230393002353 +:106CE00004930123059369462868FFF761FBBBF114 +:106CF000010F14D902232B6331462868FFF758FC93 +:106D0000A0B9DDF8048038E0AB6B43F00063AB63FF +:106D10000127D2E0AB6B43F00073AB63CDE00123FE +:106D20002B6331462868FFF72BFCE9E72B68654A9F +:106D30009A63AB6B0343AB63012385F834300023C4 +:106D40002B63BAE02868FFF70DFB2070C0F3072320 +:106D50006370C0F30743A370000EE0700434A8F121 +:106D600004080136072EEDD9FFF716F8A0EB09004D +:106D700050450FD2BAF1000F0CD02868466B16F4BC +:106D8000957615D1436B13F4004FEDD0B8F1000F99 +:106D9000EAD0E7E72B684B4A9A63AB6B43F00043BA +:106DA000AB63012385F8343000232B63032784E091 +:106DB000436B13F4807F05D0BBF1010F02D96B6CDC +:106DC000032B38D12B685A6B12F0080F44D15A6B41 +:106DD00012F0020F4CD15A6B12F0200F54D12868D8 +:106DE000436B13F4001F5BD0B8F1000F58D0FFF7CE +:106DF000B9FA2070C0F307236370C0F30743A37090 +:106E0000000EE0700434A8F10408FEF7C5FFA0EB03 +:106E10000900504502D2BAF1000FE0D12B68294A8F +:106E20009A63AB6B43F00043AB63012385F83430C6 +:106E300000232B6341E0FFF703FC03460028C1D089 +:106E40002A6820499163AA6B1343AB63012385F839 +:106E5000343000232B6330E01A4A9A63AB6B43F063 +:106E60000803AB63012385F8343000232B6324E04F +:106E7000144A9A63AB6B43F00203AB63012385F8BA +:106E8000343000232B6318E00E4A9A63AB6B43F057 +:106E90002003AB63012385F8343000232B630CE01F +:106EA00040F23A538363012385F83430002704E02D +:106EB000AB6B43F00053AB630127384607B0BDE826 +:106EC000F08F00BFFF0540002DE9F04F8BB0054665 +:106ED0000C4616469B46DDF850A0FEF75DFF002CE1 +:106EE00037D0804695F83470FFB2012F40F0E18032 +:106EF0000023AB6306EB0B03EA6D93422FD8032309 +:106F000085F834302B680022DA626B6C012B00D0DC +:106F100076024FF0FF3304934FEA4B2305939023FF +:106F200006930023079308930123099304A9286873 +:106F3000FFF73EFABBF1010F16D920232B63314630 +:106F40002868FFF765FB0190019BABB9DDF8149051 +:106F500040E0AB6B43F00063AB630127AEE0AB6B8B +:106F600043F00073AB63A9E010232B63314628681C +:106F7000FFF736FB0190E7E72B68524A9A63AB6B49 +:106F8000019A1343AB63012385F8343000232B634C +:106F900094E023780393627843EA02230393A27870 +:106FA00043EA02430393E27843EA0263039304341F +:106FB000A9F1040903A92868FFF7D7F90136072EBC +:106FC000E7D9FEF7E9FEA0EB080050450FD2BAF171 +:106FD000000F0CD02868466B16F48D7615D1436BE4 +:106FE00013F4804FEDD0B9F1000FEAD0E7E72B683A +:106FF000344A9A63AB6B019A1343AB63012385F860 +:10700000343000232B63032758E0436B13F4807F55 +:1070100005D0BBF1010F02D96B6C032B18D12B6883 +:107020005A6B12F0080F24D15A6B12F0020F2CD1B8 +:107030005A6B12F0100F34D0224A9A63AB6B43F0B4 +:107040001003AB63012385F8343000232B6335E054 +:10705000FFF7F6FA03460028E1D02A681949916340 +:10706000AA6B1343AB63012385F8343000232B63F1 +:1070700024E0144A9A63AB6B43F00803AB6301232B +:1070800085F8343000232B6318E00E4A9A63AB6B0B +:1070900043F00203AB63012385F8343000232B63F4 +:1070A0000CE040F23A529A63012385F8343000270D +:1070B00004E0AB6B43F00053AB63012738460BB0E1 +:1070C000BDE8F08FFF0540000346426E920F0A7044 +:1070D000426EC2F383624A7090F8672002F00302A6 +:1070E0008A7090F86620CA7090F865200A7190F84E +:1070F00064204A71826E120DCA80B0F86A2002F0D4 +:107100000F020A72826EC2F3C0324A72826EC2F3FA +:1071100080328A72826EC2F34032CA72826EC2F3C9 +:1071200000320A7300224A73426C002A40F08680C3 +:10713000806E40F6FC7202EA8002D86E42EA9072DB +:107140000A61DA6EC2F3C2620A7593F86F2002F028 +:1071500007024A75DA6EC2F342528A75DA6EC2F3DA +:107160008242CA75DA6EC2F3C2320A760A69013205 +:107170005A65087E00F00700023082405A6591F897 +:1071800008C00CF00F0C012000FA0CF09865400AC2 +:1071900000FB02F2DA654FF400721A66DA6EC2F38F +:1071A00080324A76DA6EC2F3C6128A76DA6E02F05E +:1071B0007F02CA761A6FD20F0A771A6FC2F3417232 +:1071C0004A771A6FC2F382628A771A6FC2F38352C8 +:1071D000CA771A6FC2F3405281F82020002081F84C +:1071E0002100B3F8722002F0010281F822201A6F08 +:1071F000C2F3C03281F823201A6FC2F3803281F8C3 +:1072000024201A6FC2F3403281F825201A6FC2F38E +:10721000003281F826201A6FC2F3812281F82720DC +:107220001A6FC2F3012281F828201B6FC3F34603B3 +:1072300081F82930012381F82A307047012A11D1C1 +:10724000826E120402F47C12B0F86E0002430A61EE +:107250000A69013292025A65DA654FF400729A6542 +:107260001A669BE7026805499163826B42F080527F +:107270008263012083F83400704700BFFF0540009F +:1072800070B590B004460123ADF812300068FFF7E6 +:1072900075F800286CD0636C032B45D1636C032B0D +:1072A0005DD1636C032B1DD0BDF81210216509045C +:1072B0002068FFF79AFA054600285BD10021206874 +:1072C000FFF773F8606604212068FFF76EF8A06688 +:1072D00008212068FFF769F8E0660C212068FFF7B5 +:1072E00064F8206704212068FFF75FF8000DE06470 +:1072F00005A92046FFF7E8FE00283ED1226D1204C2 +:1073000000232068FFF7B6F9054698BB234653F8DB +:10731000106B93E807008DE80700043494E80E0032 +:107320003046FFF705F825E02068FFF749FA0546E3 +:1073300000BB00212068FFF738F86067042120684F +:10734000FFF733F8A06708212068FFF72EF8E06701 +:107350000C212068FFF729F8C4F880009EE70DF1A2 +:1073600012012068FFF7E6FA0546002899D001E0EF +:107370004FF08065284610B070BD4FF08055F9E79A +:1073800030B58BB00446002304930593069307930E +:107390000893762309930AAB13E907008DE80700E9 +:1073A00004AB0ECB2068FEF7C3FF18B101252846B9 +:1073B0000BB030BD05462268536823F480735360D8 +:1073C0002068FEF7D7FF2268536843F48073536048 +:1073D0000220FEF7E7FC2046FFF70EFB30B1012547 +:1073E00084F83450A36B0343A363E0E72046FFF720 +:1073F00047FF30B1012584F83450A36B0343A363E6 +:10740000D5E74FF400712068FFF7A2F80028CED02E +:10741000236804499963A36B0343A363012584F89C +:107420003450C4E7FF054000A8B110B5044690F8F9 +:10743000343063B1032384F834302046FFF7A0FFD3 +:1074400058B9A0632063012384F8343010BD03775A +:10745000FCF78AFFEEE7012070470120F6E7436C56 +:107460000B60836C4B60C36C8B60036DCB60436DB2 +:107470000B61836D4B61C36D8B61036ECB6100202B +:107480007047000030B58BB004460D46032380F8EA +:107490003430436C032B1CD0B1F5805F08D0B1F5BC +:1074A000006F0AD079B1836B43F00063836314E00B +:1074B000836B43F0805383630FE0FFF77DFBA36B87 +:1074C0000343A36309E0FFF79EFBA36B0343A3639E +:1074D00003E0836B43F080538363A36BC3B12368E2 +:1074E000174A9A63012584F834504FF400712068DC +:1074F000FFF72EF830B1236811499963A36B03435A +:10750000A3630125012384F8343028460BB030BD35 +:1075100063680493A3680593E3680693079563691A +:107520000893A36909930AAB13E907008DE80700E4 +:1075300004AB0ECB2068FEF7FBFE0025D5E700BFAD +:10754000FF05400010B582B004460023019301A955 +:10755000FFF780FB10B1A36B0343A3630198C0F353 +:10756000432002B010BD00000346026812F0400F35 +:1075700036D110B402681D4810400A684C68224396 +:10758000CC6822430C6922434C6922438C69224314 +:10759000CC6922430C6A2243104318605868144A8D +:1075A00002408868B1F816C040EA0C0002435A60F5 +:1075B0008A68B2F5006F03D25A6842F480525A606A +:1075C0000A6AB2F5005F07D00020DA6922F400628F +:1075D000DA615DF8044B70478A8C1A610020F4E789 +:1075E0000120DA6922F40062DA6170474000FFFF8F +:1075F000FBF0FFFF70B4046A036A23F00103036227 +:1076000042688569124B2B400D681D4324F002042B +:107610008B6823430F4C104EB04218BFA0420CBFE2 +:107620000124002405D123F00803CE681E4326F070 +:1076300004032CB122F440724C6914438A6922433A +:10764000426085614A684263036270BC704700BF54 +:107650008CFFFEFF000001400004014070B4036A8B +:10766000026A22F4807202624268C569144C2C409E +:107670000E68264323F400738C6843EA0423114CFC +:10768000114DA84218BFA0420CBF0124002406D10E +:1076900023F40063CD6843EA052323F480633CB1FF +:1076A00022F440524C6942EA04128C6942EA041204 +:1076B0004260C6614A68C263036270BC704700BF23 +:1076C0008CFFFEFF000001400004014070B4036A1B +:1076D000026A22F4805202624468C5690D4A2A4057 +:1076E0000D6842EA052223F400538D6843EA05330E +:1076F000094E0A4DA84218BFB04204D124F4804478 +:107700004D6944EA85144460C2614A6802640362B8 +:1077100070BC7047FF8CFFFE000001400004014078 +:1077200070B4036A026A22F4803202624468426DD5 +:107730000D4D15400A682A4323F400338D6843EA4F +:1077400005430A4E0A4DA84218BFB04204D124F4A2 +:1077500080344D6944EA0524446042654A68826584 +:10776000036270BC704700BF8FFFFEFF0000014046 +:107770000004014070B4036A026A22F480120262BB +:107780004468456D0D4A2A400D6842EA052223F4FB +:1077900000138D6843EA0553094E0A4DA84218BFED +:1077A000B04204D124F480244D6944EA8524446025 +:1077B00042654A68C265036270BC7047FF8FFFFE76 +:1077C000000001400004014010B4036A046A24F080 +:1077D00001040462846924F0F00C4CEA021223F0E4 +:1077E0000A030B43826103625DF8044B704710B4D7 +:1077F000036A046A24F010040462846924F4704C5F +:107800004CEA023223F0A00343EA011382610362CF +:107810005DF8044B7047836823F070030B4343F01B +:107820000703836070470368196A41F2111211421D +:1078300008D1196A40F24442114203D11A6822F079 +:1078400001021A60012380F83D30002070470000DB +:1078500090F83D30DBB2012B3AD1022380F83D3065 +:107860000268D36843F00103D36003681A4AB3F196 +:10787000804F18BF93421DD0A2F57C42934219D08D +:1078800002F58062934215D002F58062934211D0D6 +:1078900002F5784293420DD002F57052934209D01E +:1078A000A2F59432934205D01A6842F001021A60A0 +:1078B000002070479968094A0A40062A18BFB2F5A5 +:1078C000803F07D01A6842F001021A60002070471A +:1078D00001207047002070470000014007000100B0 +:1078E0000268D36823F00103D3600368196A41F288 +:1078F0001112114208D1196A40F24442114203D1D7 +:107900001A6822F001021A60012380F83D3000203D +:10791000704770477047704770477047704770B541 +:1079200004460368DE681D6915F0020F10D016F0DA +:10793000020F0DD06FF002021A6101230377036872 +:107940009B6913F0030F64D0FFF7E6FF0023237752 +:1079500015F0040F12D016F0040F0FD023686FF04B +:1079600004021A610223237723689B6913F4407F82 +:1079700055D02046FFF7D0FF0023237715F0080FDE +:1079800012D016F0080F0FD023686FF008021A61AA +:10799000042323772368DB6913F0030F46D02046C6 +:1079A000FFF7BAFF0023237715F0100F12D016F05F +:1079B000100F0FD023686FF010021A61082323778D +:1079C0002368DB6913F4407F37D02046FFF7A4FF1C +:1079D0000023237715F0010F02D016F0010F33D1E9 +:1079E00015F4025F02D016F0800F35D115F4807FB8 +:1079F00002D016F0800F37D115F0400F02D016F0EC +:107A0000400F39D115F0200F02D016F0200F3BD1D6 +:107A100070BDFFF780FF2046FFF77FFF96E7204607 +:107A2000FFF779FF2046FFF778FFA5E72046FFF72D +:107A300072FF2046FFF771FFB4E72046FFF76BFFA8 +:107A40002046FFF76AFFC3E723686FF001021A615F +:107A50002046FFF75FFFC3E723686FF402521A6105 +:107A6000204600F0CEFBC1E723686FF480721A61F4 +:107A7000204600F0C7FBBFE723686FF040021A61A1 +:107A80002046FFF74BFFBDE723686FF020021A6125 +:107A9000204600F0B5FBBBE730B503683F4A904293 +:107AA00014BF4FF0000E4FF0010EB0F1804F14BF25 +:107AB00072464EF00102AAB9394CA04214BF00240C +:107AC0000124384DA8420DD064B904F1804404F576 +:107AD0008234A04214BF0024012405F50065A842A9 +:107AE00000D01CB123F070034C682343002A33D12B +:107AF0002B4A904214BF002201222A4CA0422BD0D4 +:107B000052BB02F1804202F58232904214BF002241 +:107B1000012204F50064A0421ED0EAB9224A904234 +:107B200014BF0022012204F59A34A04214D09AB95D +:107B30001E4A904214BF0022012204F50064A042B4 +:107B40000AD04AB91A4A904214BF00220122A4F571 +:107B50009634A04200D022B123F4407CCB6843EAA3 +:107B60000C0323F080034A69134303608A68C262EE +:107B70000A6882620F4A904214BF73464EF00103B6 +:107B80000BB10B69036301234361036913F0010F18 +:107B900003D0036923F00103036130BD00000140FD +:107BA000000800400004004000440140001800406C +:107BB000002000400004014060B310B5044690F876 +:107BC0003D3013B3022384F83D30214651F8040BB5 +:107BD000FFF762FF012384F8483084F83E3084F8D0 +:107BE0003F3084F8403084F8413084F8423084F8E3 +:107BF000433084F8443084F8453084F8463084F8C3 +:107C0000473084F83D30002010BD80F83C30FCF750 +:107C100007FCD7E70120704760B310B5044690F821 +:107C20003D3013B3022384F83D30214651F8040B54 +:107C3000FFF732FF012384F8483084F83E3084F89F +:107C40003F3084F8403084F8413084F8423084F882 +:107C5000433084F8443084F8453084F8463084F862 +:107C6000473084F83D30002010BD80F83C30FFF7ED +:107C700050FED7E70120704770B4036A026A22F011 +:107C80001002026242688569144C2C400D6844EA77 +:107C9000052523F020038C6843EA0413104C114E91 +:107CA000B04218BFA0420CBF0124002406D123F02B +:107CB0008003CE6843EA061323F040033CB122F46C +:107CC00040624C6942EA84028C6942EA8402426062 +:107CD00085614A688263036270BC7047FF8CFFFE57 +:107CE000000001400004014038B590F83C30012B01 +:107CF00000F0958004460D46012380F83C30142A9C +:107D000000F28880DFE802F00B8686861F86868672 +:107D100034868686488686865D86868671000068FB +:107D2000FFF768FC2268936943F0080393612268B7 +:107D3000936923F0040393612268936929690B43D3 +:107D40009361002067E00068FFF796FF226893695F +:107D500043F4006393612268936923F48063936121 +:107D600022689369296943EA01239361002052E064 +:107D70000068FFF773FC2268D36943F00803D361FE +:107D80002268D36923F00403D3612268D369296987 +:107D90000B43D36100203EE00068FFF797FC2268A8 +:107DA000D36943F40063D3612268D36923F4806309 +:107DB000D3612268D369296943EA0123D361002092 +:107DC00029E00068FFF7ACFC2268536D43F008031C +:107DD00053652268536D23F0040353652268536D85 +:107DE00029690B435365002015E00068FFF7C2FCCA +:107DF0002268536D43F4006353652268536D23F486 +:107E0000806353652268536D296943EA01235365F2 +:107E1000002000E00120002384F83C3038BD02201F +:107E2000FCE710B4846824F47F4C42EA03220A433E +:107E300042EA0C0282605DF8044B704790F83C30D7 +:107E4000012B76D010B50446012380F83C30022384 +:107E500080F83D3002689068374B034093600B68B0 +:107E6000602B4CD023D8402B54D011D8202B03D0DA +:107E70000AD80BB1102B05D119462068FFF7CBFCAF +:107E8000002028E0012026E0302BF5D0012022E060 +:107E9000502B0AD1CA6849682068FFF795FC502129 +:107EA0002068FFF7B8FC002015E0012013E0B3F5CF +:107EB000805F3AD0B3F5005F14D0702B37D1CB6818 +:107EC0004A6889682068FFF7ACFF2268936843F02E +:107ED000770393600020012384F83D30002384F869 +:107EE0003C3010BDCB684A6889682068FFF799FF6D +:107EF0002268936843F4804393600020EBE7CA68EC +:107F000049682068FFF773FC60212068FFF783FC55 +:107F10000020E0E7CA6849682068FFF755FC402167 +:107F20002068FFF778FC0020D5E70020D3E7012088 +:107F3000D1E70220704700BF8800FEFF01F01F015B +:107F40004FF0010C0CFA01FC036A23EA0C030362F4 +:107F5000036A8A40134303627047000010B5044669 +:107F600010293CD8DFE801F0093B3B3B1F3B3B3B82 +:107F7000263B3B3B2D3B3B3B340090F83E30DBB295 +:107F8000013B18BF0123002B40F08980102974D8D1 +:107F9000DFE801F02C737373637373736773737328 +:107FA0006B7373736F0090F83F30DBB2013B18BF07 +:107FB0000123E8E790F84030DBB2013B18BF012312 +:107FC000E1E790F84130DBB2013B18BF0123DAE76B +:107FD00090F84230DBB2013B18BF0123D3E790F8A1 +:107FE0004330DBB2013B18BF0123CCE7022384F806 +:107FF0003E3001222068FFF7A1FF23682A492B4A5F +:10800000934218BF8B4203D15A6C42F400425A6427 +:108010002368254AB3F1804F18BF934231D0A2F5AF +:108020007C4293422DD002F58062934229D002F522 +:108030008062934225D002F57842934221D002F526 +:10804000705293421DD0A2F59432934219D01A680F +:1080500042F001021A60002022E0022384F83F303F +:10806000C7E7022384F84030C3E7022384F8413095 +:10807000BFE7022384F84230BBE7022384F8433091 +:10808000B7E799680A4A0A40062A18BFB2F5803F46 +:1080900007D01A6842F001021A60002000E00120B7 +:1080A00010BD0020FCE700BF0000014000040140BB +:1080B0000700010038B504460D4600220068FFF7AE +:1080C0003DFF23682449254A934218BF8B420DD1B6 +:1080D000196A41F21112114208D1196A40F2444260 +:1080E000114203D15A6C22F400425A642368196A7F +:1080F00041F21112114208D1196A40F24442114270 +:1081000003D11A6822F001021A60102D1FD8DFE88F +:1081100005F0091E1E1E0E1E1E1E121E1E1E161EFF +:108120001E1E1A00012384F83E30002038BD0123B2 +:1081300084F83F30F9E7012384F84030F5E7012364 +:1081400084F84130F1E7012384F84230EDE7012360 +:1081500084F84330E9E700BF00000140000401401B +:1081600090F83C20012A45D070B40346012280F8E3 +:108170003C20022280F83D200268506894681E4E20 +:108180001E4DAA4218BFB24203D120F470004D68C0 +:10819000284320F070000D68284350601A68164884 +:1081A000B2F1804F18BF824217D0A0F57C408242C6 +:1081B00013D000F5806082420FD000F580608242CB +:1081C0000BD000F57840824207D000F57050824213 +:1081D00003D0A0F59430824204D124F08004896851 +:1081E00021439160012283F83D20002083F83C0068 +:1081F00070BC70470220704700000140000401403D +:10820000704770477047000030B503683B4A9042A2 +:1082100014BF4FF0000E4FF0010EB0F1804F14BFAD +:1082200072464EF00102AAB9354CA04214BF002498 +:108230000124344DA8420DD064B904F1804404F502 +:108240008234A04214BF0024012405F50065A84231 +:1082500000D01CB123F070034C682343002A33D1B3 +:10826000274A904214BF00220122264CA0422BD064 +:1082700052BB02F1804202F58232904214BF0022CA +:10828000012204F50064A0421ED0EAB91E4A9042C1 +:1082900014BF0022012204F59A34A04214D09AB9E6 +:1082A0001A4A904214BF0022012204F50064A04241 +:1082B0000AD04AB9164A904214BF00220122A4F5FE +:1082C0009634A04200D022B123F4407CCB684CEA23 +:1082D000030303608A68C2620A8882620D4A904280 +:1082E00014BF73464EF001030BB10B69036343697E +:1082F00043F001034361002030BD00BF0000014096 +:108300000008004000040040004401400018004004 +:108310000020004000040140B2F5004F06D001EB00 +:108320005301B1FBF3F189B2C16070475A0802EB07 +:108330004102B2FBF3F34FF6F0721A40C3F342036B +:108340001343C3607047000038B5036813F0010F92 +:1083500062D104460D460368314A1A404B68C96829 +:108360000B4329690B43A9690B431A430260AB68AD +:10837000426822F44052134343606B69826822F4DE +:10838000407213438360274B984216D0264B984285 +:108390001BD0264B98421CD0254B98421DD0254B14 +:1083A00098421ED0244B984220D0244B984222D091 +:1083B000234B984224D001202FE00320FDF762FDDB +:1083C00060B32B680BBB012027E00C20FDF75AFDA2 +:1083D000F6E73020FDF756FDF2E7C020FDF70EFE70 +:1083E000EEE74FF44070FDF709FEE9E74FF4406017 +:1083F000FDF748FDE4E74FF44050FDF7FFFDDFE7F0 +:108400004FF44040FDF7FAFDDAE7AA69014620463D +:10841000FFF782FF002000E0012038BD0120FCE7CB +:10842000F369FFEF001001400044004000480040A5 +:10843000004C004000500040001401400078004013 +:10844000007C0040034AD2F8883043F47003C2F83D +:108450008830704700ED00E008B50146012205486C +:1084600001F01EFA044B187008B1012008BD00206D +:10847000FCE700BF5C1600208C02002008B5014616 +:108480000122002001F00CFA034B187008B1012002 +:1084900008BD0020FCE700BF8C020020F8B50446B0 +:1084A0000D461646104901F0ECFE104B187008B14D +:1084B000C0B2F8BD022221460D4801F021FA0B4B53 +:1084C000187008B1C0B2F4E7094F0A4B324629468A +:1084D000384601F01AFC054C2070384601F069FD61 +:1084E0002070C0B2E5E700BF140600208C02002017 +:1084F0002C0600200C0600202DE9F04104460F4612 +:1085000090461D46434901F0BCFE434B1870E8B944 +:1085100001222146414801F0F3F906463E4B18700E +:1085200018BB29463D4801F059FD3B4B187058B324 +:108530006420F8F7D7FB054622463949F7F7C2FE13 +:108540002846F8F7D7FB344B18780CE06420F8F78E +:10855000C9FB054622463349F7F7B4FE2846F8F72B +:10856000C9FB2D4B1878BDE8F0816420F8F7BAFB01 +:108570000546234632462C49F7F7A4FE2846F8F76D +:10858000B9FB254B1878EEE7284B4246394623487D +:1085900001F0CFFA0646204B187008BB55B91F4BA7 +:1085A000DA68234B1A603A705A787A709A78BA70FF +:1085B000DB78FB70194801F0FCFC0546164B18707F +:1085C000D8B16420F8F78EFB064623462A4619499F +:1085D000F7F778FE3046F8F78DFB0F4B1878C2E7B7 +:1085E0006420F8F77FFB0546234632461249F7F729 +:1085F00069FE2846F8F77EFBEFE76420F8F772FB88 +:10860000054622460D49F7F75DFE2846F8F772FB4E +:10861000E3E700BF140600208C0200202C06002097 +:108620008CAB0008D0AA0008F4AA000810060020AD +:108630008002002044AB00081CAB00086CAB0008B3 +:1086400010B504460C4901F01CFE0C4B187008B91B +:10865000C0B210BD0B222146094801F051F9074B69 +:10866000187008B1C0B2F4E7054801F0A2FC034B52 +:108670001870C0B2EDE700BF140600208C02002085 +:108680002C06002070B504461A4901F0FAFD1A4B79 +:108690001870A0B9204601F016FE0546164B18705A +:1086A000D8B96420F8F71EFB054622461349F7F7B0 +:1086B00009FE2846F8F71EFB0F4B187870BD6420A2 +:1086C000F8F710FB054622460D49F7F7FBFD284653 +:1086D000F8F710FB084B1878F0E76420F8F702FB76 +:1086E000064623462A460749F7F7ECFD3046F8F7D9 +:1086F00001FBE1E7140600208C020020D4AB000847 +:10870000B4AB0008F8AB0008F8B504460D461646B1 +:10871000104901F0B6FD104B187008B1C0B2F8BD99 +:10872000322221460D4801F0EBF80B4B187008B1CE +:10873000C0B2F4E7094F0A4B32462946384601F0E9 +:10874000E4FA054C2070384601F033FC2070C0B2CA +:10875000E5E700BF140600208C0200202C06002054 +:108760000C06002008B5044B03EB800252685268E7 +:108770000344187A904708BDB826002008B5084B76 +:108780001B5C53B9064B01221A5403EB800252685A +:1087900012680344187A904708BD0020FCE700BF28 +:1087A000B826002038B5044C04EB80056D68AD6830 +:1087B0000444207AA84738BDB826002038B5044CB8 +:1087C00004EB80056D68ED680444207AA84738BD45 +:1087D000B826002010B5044B03EB800464682469BC +:1087E0000344187AA04710BDB826002042780078CC +:1087F00040EA02207047C378827842EA0322437835 +:1088000043EA0223007840EA032070470170090A16 +:10881000417070470170C1F307234370C1F30743F0 +:108820008370090EC1707047944632B10A780131E5 +:1088300002700130BCF1010CF8D1704701700130B9 +:10884000013AFBD1704784469CF800000CF1010C02 +:108850000B780131C01A013A01D00028F4D07047DA +:10886000034600E00133187808B18842FAD1704716 +:1088700010B44FF0000C634602E04FF0010C0133DE +:10888000012B15D81A01184CA258002AF5D00468FB +:10889000A242F4D1144A02EB031254688268944253 +:1088A000EDD1114A02EB0312946842699442E6D179 +:1088B000022B0BD0B1B90C4A02EB03139B89B3F521 +:1088C000807F0DD000205DF8044B7047022914BF53 +:1088D00063464CF001030BB10020F4E71220F2E7ED +:1088E0001020F0E71020EEE790260020002000E0A6 +:1088F0000130012804D80301034AD358002BF7D1D3 +:10890000023818BF012070479026002070B4002361 +:1089100000E00133012B13D81A01234CA45802683C +:108920009442F6D1204A02EB0312546882689442C2 +:10893000EFD11D4A02EB0312946842699442E8D1D8 +:10894000022B08D0F9B1184A02EB031292894ABBF4 +:108950004FF480721DE00023012B05D81A01124C40 +:10896000A2580AB10133F7E7022B19D00E4D1C01B2 +:1089700005EB031206682E518468546040699060CC +:1089800000209081DEE7084A02EB0312928901324F +:1089900092B2054901EB03118A81581C70BC7047E3 +:1089A0000020FBE70020F9E790260020013801288D +:1089B00015D80D4B03EB00139B89B3F5807F03D0D3 +:1089C00043B1013B9BB200E00023074A02EB0012D7 +:1089D000938133B903010020034AD050704702202D +:1089E00070470020704700BF90260020002303E05E +:1089F0005DF8044B70470133012B11D81A01094966 +:108A00008A588242F7D110B41A0100248C500133E5 +:108A1000012BEDD81A0103498A588242F7D1F3E7B6 +:108A2000704700BF9026002002398369023B8B42C9 +:108A300004D94389C06A01FB0300704700207047D6 +:108A40000268C36A04339089B1FBF0F15289B1FB2B +:108A5000F2F101E0091A0833186818B18142F9D21D +:108A600058680844704770B506460D4601F11A0073 +:108A7000FFF7BCFE3378032B00D070BD044605F130 +:108A80001400FFF7B3FE44EA0040F6E770B506466F +:108A90000C46154691B204F11A00FFF7B7FE337881 +:108AA000032B00D070BD290C04F11400FFF7AEFEBB +:108AB000F8E738B500234B72C36973B305460C461B +:108AC0000022134606E0BCF1090F0FD0A1184B722B +:108AD000013263460A2B0ED803F1010C296ACB5CE4 +:108AE000202BF6D0052BEED1E523ECE7A1182E20A4 +:108AF00048720132EAE72244002353722B6ADB7A80 +:108B00002372286A1C30FFF776FE2060286A163030 +:108B1000FFF771FEE080000CA08038BD2DE9F84F12 +:108B200081468A46D1F8008000F1240B0B222021D7 +:108B30005846FFF783FE00252B46082729E001361B +:108B400018F806302F2BFAD05C2BF8D04644CAF820 +:108B50000060002D44D099F82430E52B35D0202C2E +:108B600037D8042389F82F30002035E014F0800F27 +:108B700027D121461B48FFF773FE78BBA4F16103A0 +:108B8000DBB2192B01D8203CE4B20BF805400135CB +:108B900033465E1C18F80340202CD7D95C2C18BF34 +:108BA0002F2CCDD02E2C18BFAF42DFD82E3C18BFB3 +:108BB00001240B2F08BF44F0010464B908250B27DA +:108BC000E6E7803C084B1C5DD3E7052389F8243099 +:108BD000C5E70023C6E70620BDE8F88F0620FBE7BF +:108BE0000620F9E718AC000890AC000801460068C0 +:108BF00008B1024603E04FF0FF30704701321378AE +:108C0000202B01D93A2BF9D13A2B01D00020704703 +:108C1000034613F8010B3038092898BF9A4203D154 +:108C200028B901320A6070474FF0FF3070474FF0AB +:108C3000FF30704738B50D46044698B103689BB1C4 +:108C40001A78A2B18188DA88914203D009200024E1 +:108C50002C6038BD5878FFF785FD10F0010009D170 +:108C60002468F5E70920F3E71C460920F0E709200E +:108C70000024EDE709200024EAE72DE9F041C5785A +:108C800015B92846BDE8F0810446076B00F13408A9 +:108C900001233A4641464078FFF790FD0546A0B9CA +:108CA0000023E370636AFB1AE2699342E9D2A67873 +:108CB00008E0E3691F4401233A4641466078FFF724 +:108CC0007DFD013E012EF4D8DBE70125D9E770B523 +:108CD000036B8B4202D10026304670BD04460D4620 +:108CE000FFF7CBFF06460028F6D101232A4604F100 +:108CF00034016078FFF756FD10B101264FF0FF35C3 +:108D00002563E9E738B504460023C3704FF0FF330D +:108D10000363FFF7DCFF30BB054604F23220FFF7A8 +:108D200065FD4AF6552398421FD194F83430E92B5B +:108D300007D0636B03F0FF130D4A934201D0022565 +:108D400014E004F16A00FFF756FD20F07F40094B64 +:108D500098420BD004F18600FFF74DFD064B984278 +:108D600004D0022502E0042500E00325284638BD92 +:108D7000EB00900046415400464154332DE9F04F3A +:108D800087B00D46164600230B60FFF72FFF071E26 +:108D9000C0F26781BE4B53F82740002C00F066817B +:108DA0002C6006F0FE06237873B16078FFF7DAFCDA +:108DB00010F0010508D1002E00F0548110F0040FCE +:108DC00000F050810A254DE100232370F8B2607055 +:108DD000FFF7D4FC10F0010F40F04A811EB110F0F3 +:108DE000040F40F0478104F10C0202216078FFF784 +:108DF000F1FC0546002840F03F81A289A2F50073EE +:108E00009BB2B3F5606F00F23981531E1A4201D054 +:108E1000012527E100212046FFF774FF022800F01A +:108E200088800026042800F02B81012800F22A8186 +:108E300004F13F00FFF7DAFCB4F80C80404540F045 +:108E4000238104F14A00FFF7D1FC074620B904F161 +:108E50005800FFF7D0FC0746E76194F84420A27061 +:108E6000531EDBB2012B00F2118107FB02F30093CA +:108E700094F84190A4F80A90B9F1000F00F0108125 +:108E800009F1FF3319EA030F40F00C8104F14500AA +:108E9000FFF7ACFC824620814FEA581BB0FBFBF386 +:108EA0000BFB13039BB2002B40F0FE8004F1470044 +:108EB000FFF79CFC019020B904F15400FFF79BFCE4 +:108EC000019004F14200FFF791FC0146002800F0F8 +:108ED000ED80009BC318BAFBFBFB5B44019A9A42EE +:108EE000C0F0E680D21AB2FBF9F04A45C0F0E28049 +:108EF0004FF6F572904234D840F6F57290426AD936 +:108F00004FF0020B2FE0002006AB03EB860343F883 +:108F1000100C0136032E0ED804F13400330103F592 +:108F2000DF7318440379002BEDD00830FFF763FCA2 +:108F3000EAE70026EEE700270AE031462046FFF781 +:108F4000E1FE01287FF66EAF0137032F3FF66AAFCF +:108F500006AB03EB870353F8106C002EEDD1032012 +:108F6000F2E74FF0030B00F10209C4F818902662F3 +:108F70008A1962623344E362BBF1030F2ED0BAF167 +:108F8000000F00F09D80009B1A44A262BBF1020F0B +:108F900035D009EB490209F0010303EB52034344C6 +:108FA000013BB3FBF8F3BB4200F28C804FF0FF3380 +:108FB0006361236180232371BBF1030F22D084F806 +:108FC00000B0344A138801339BB21380E3802046FB +:108FD000FFF70CFD46E04FF0010BC4E704F15E0023 +:108FE000FFF704FC002867D1BAF1000F66D104F145 +:108FF0006000FFF700FCA0624FEA8903CFE74FEA69 +:109000004903CCE704F16400FFF7F0FB0128D6D157 +:10901000711C2046FFF75BFE0028D0D1002323718E +:1090200004F23220FFF7E2FB4AF655239842C6D1FC +:1090300004F13400FFF7DFFB174B9842BFD104F572 +:109040000670FFF7D8FB154B9842B8D104F50770AE +:10905000FFF7D1FB606104F50870FFF7CCFB2061DE +:10906000ADE70B25284607B0BDE8F08F0C25F9E7E2 +:109070000325F7E70A25F5E70125F3E70125F1E7E1 +:109080000125EFE70D25EDE70D25EBE70D25E9E7D8 +:10909000B4260020B0260020525261417272416114 +:1090A0000D25DFE70D25DDE70D25DBE70D25D9E7EC +:1090B0000D25D7E70D25D5E70D25D3E70D25D1E7FC +:1090C0000D25CFE70D25CDE72DE9F047012940F229 +:1090D0008E8004460D46174683698B4240F28B8092 +:1090E0000378022B49D0032B60D0012B40F0858000 +:1090F00001EB5108416A8389B8FBF3F31944FFF788 +:10910000E6FD0646002873D104F1340A08F101098E +:10911000A389B8FBF3F203FB128815F0010522D0F6 +:109120001AF8083003F00F0343EA0713DBB20AF81A +:1091300008300123E370616AA389B9FBF3F3194492 +:109140002046FFF7C4FD0646002851D1A389B9FB8C +:10915000F3F203FB129945B1C7F307130AF809307C +:109160000123E37044E0FBB2E1E71AF80930C7F3EA +:10917000032223F00F031343F0E7416A83895B085E +:10918000B5FBF3F31944FFF7A2FD064680BB04F1DB +:1091900034006D00A389B5FBF3F203FB1255B9B29D +:1091A0002844FFF733FB0123E37021E0416A838900 +:1091B0009B08B5FBF3F31944FFF789FD0646B8B9E0 +:1091C00027F0704704F13403AD00A289B5FBF2F13A +:1091D00002FB11551D442846FFF70DFB00F07041BE +:1091E00039432846FFF716FB0123E37000E002260F +:1091F0003046BDE8F0870226FAE70226F8E7F8B520 +:10920000056801296AD90C46AB698B4268D92B786D +:10921000022B35D0032B49D0012B63D101EB510632 +:10922000696AAB89B6FBF3F319442846FFF74FFD93 +:1092300010B14FF0FF3052E0771CAB89B6FBF3F270 +:1092400003FB12662E4496F83460696AB7FBF3F3A9 +:1092500019442846FFF73BFD002845D1AB89B7FBF1 +:10926000F3F203FB12772F4497F8343046EA0320D9 +:1092700014F0010F01D0000931E0C0F30B002EE023 +:10928000696AAB895B08B4FBF3F319442846FFF71E +:109290001EFD60BB05F134006400AB89B4FBF3F242 +:1092A00003FB12442044FFF7A1FA18E0696AAB8976 +:1092B0009B08B4FBF3F319442846FFF708FDC8B92F +:1092C00005F13400A400AB89B4FBF3F203FB1244B4 +:1092D0002044FFF790FA20F0704000E00120F8BD34 +:1092E0000120FCE70120FAE74FF0FF30F7E74FF0ED +:1092F000FF30F4E74FF0FF30F1E72DE9F041D0F80F +:109300000080B1F5001F49D207460E4611F01F0F2D +:1093100047D1416184681CBB98F80030022B01D909 +:10932000D8F82840E4B9B8F80830B3EB561F3AD95A +:10933000D8F82830FB61BC61FB69E3B3B8F80C20B6 +:10934000B6FBF2F21344FB6108F13403B8F80C20C9 +:10935000B6FBF2F102FB11610B443B6200201EE000 +:10936000B8F80A50B8F80C3003FB05F5AE420FD33D +:1093700021463846FFF743FF0446B0F1FF3F14D0C3 +:10938000012814D9D8F81830834212D9761BEDE79A +:1093900021464046FFF748FBF861CCE70220BDE8D4 +:1093A000F0810220FBE70220F9E70120F7E7022025 +:1093B000F5E70220F3E70220F1E72DE9F041054649 +:1093C00006680F4651B9D6F81080B8F1000F12D0D8 +:1093D000B369434511D84FF001080EE0FFF70FFFC6 +:1093E000034601284CD9B0F1FF3F4ED0B26982420A +:1093F0004BD8B84601E04FF0010844460CE0214646 +:109400002846FFF7FCFE034678B1B0F1FF3F18BFD6 +:1094100001283AD0444537D00134B369A342EED88D +:10942000B8F1010F2ED90224E9E74FF0FF322146AF +:109430003046FFF749FE0246B0FA80F04009002F9F +:1094400008BF002070B9A2B934617269B369023BE8 +:109450009A4201D8013A7261337943F001033371C2 +:10946000234612E0224639463046FFF72DFE0246DB +:10947000E9E7012A01D0012307E04FF0FF3304E0C0 +:10948000012302E0002300E000231846BDE8F0813C +:10949000F8B50C46056801292ED906461146AB6978 +:1094A000A3422BD94AB14FF0FF322846FFF70CFEFA +:1094B000074610B123E0A24221D927462146304673 +:1094C000FFF79DFE0446E0B101281CD0B0F1FF3F3C +:1094D0001BD0002239462846FFF7F6FD074670B933 +:1094E0006B69AA69911E8B42E5D201336B612B79BE +:1094F00043F001032B71DEE7022700E00227384624 +:10950000F8BD0027FBE70227F9E70127F7E738B5A1 +:1095100004460568C1692846FFF7D9FB20B9236ACC +:10952000E5221A700123EB7038BD2DE9F843066877 +:109530004469C369002B74D005460F462034B4F546 +:10954000001F70D2B189B4FBF1F201FB12423AB9AB +:109550000133C3618169A1B93389B3EB541F0CD9BD +:109560006C6106F13403B289B4FBF2F102FB1144E1 +:1095700023442B620020BDE8F8830023C36104204C +:10958000F9E7B289B4FBF2F27389013B12EA0308EE +:10959000E6D1FFF734FE8146012846D9B0F1FF3FFE +:1095A00045D0B369834234D88FB1A9692846FFF703 +:1095B00004FF814600283CD001283CD0B0F1FF3F99 +:1095C0003BD03046FFF759FB28B10120D3E70023F9 +:1095D000EB610420CFE7B289002106F13400FFF7E8 +:1095E0002DF949463046FFF71FFA306373899845D5 +:1095F0000BD20123F3703046FFF73FFBF8B908F1B7 +:109600000108336B01333363F0E7336BA3EB0803DB +:109610003363C5F8189049463046FFF705FAE8610C +:109620009EE70420A7E70420A5E70220A3E7012086 +:10963000A1E707209FE702209DE701209BE701208B +:1096400099E770B5044606680021FFF756FE054607 +:1096500040B1284670BD00212046FFF766FF054651 +:109660000028F6D1E1693046FFF731FB05460028B6 +:10967000EFD1206A03787BB1C37A03F03F03A37173 +:10968000C37A13F0080FE6D10B2204F12401FFF78F +:10969000DAF80028DFD1DCE70425DAE730B583B05B +:1096A00004460191056801E001330193019B1A789A +:1096B0002F2AF9D05C2AF7D00022A2601B781F2B3A +:1096C00021D901A92046FFF729FA034618BB2046F5 +:1096D000FFF7B7FF94F82F200346F8B912F0040FF4 +:1096E00019D1A37913F0100F1FD005F1340163696C +:1096F000AA89B3FBF2F002FB103319442846FFF7A6 +:10970000B2F9A060DDE7802384F82F3011462046AF +:10971000FFF7F3FD0346184603B030BD0428FAD125 +:1097200012F0040FF7D10523F5E70523F3E7F8B5A9 +:1097300004460E4607680021FFF7DFFD0246B8B970 +:10974000002506E0002501212046FFF7EEFE024637 +:1097500070B9E1693846FFF7BAFA024640B9236AA0 +:109760001B78002B18BFE52BECD10135B542EAD1AF +:10977000042A01D01046F8BD0722FBE770B5044665 +:1097800006680121FFF7D3FF054608B1284670BDE2 +:10979000E1693046FFF79BFA05460028F6D1202202 +:1097A0000021206AFFF74AF80B2204F12401206A05 +:1097B000FFF73AF80123F370E8E7F8B504460E46E0 +:1097C0000568042705E000212046FFF7AEFE0746A6 +:1097D000E8B9E169D9B12846FFF779FA0746B0B987 +:1097E000236A1A7892B1DB7A03F03F03A371E52A6A +:1097F00018BF2E2AE7D00F2BE5D023F02003082B2B +:1098000014BF00230123B342DDD100E004270FB1D0 +:109810000023E3613846F8BD70B50446FFF72DFA22 +:10982000054648B92378032B08D0002211466078FA +:10983000FEF7D0FF00B10125284670BD2379012B2A +:10984000F3D104F13406A28900213046FEF7F6FF79 +:109850004AF6552104F23220FEF7D8FF0E49304671 +:10986000FEF7D8FF0D4904F50670FEF7D3FF6169D6 +:1098700004F50770FEF7CEFF216904F50870FEF7C6 +:10988000C9FF226A01322263012331466078FEF764 +:1098900095FF00232371C8E7525261417272416102 +:1098A00070B584B0019000911646039103A8FFF7AC +:1098B0009DF9041E20DB114B53F8245025B1284696 +:1098C000FFF794F800232B70019B0BB100221A7054 +:1098D000019B0A4A42F82430721E18BF0122002B55 +:1098E00008BF42F0010212B1002004B070BD01A90E +:1098F0006846FFF743FAF8E70B20F6E7B4260020A6 +:109900002DE9F04391B00191002800F01081144638 +:10991000064602F03F073A4603A901A8FFF72EFAD0 +:10992000054628B100233360284611B0BDE8F08316 +:10993000039B0493019904A8FFF7B0FE054660B9A4 +:109940009DF93F30002B52DB14F03E0F14BF012174 +:10995000002104A8FEF78CFF054614F01C0F5CD014 +:10996000002D50D0042D44D047F00807002DD9D148 +:1099700017F0080F61D0FAF7D5F9044601460C98A4 +:109980000E30FEF747FF21460C981630FEF742FFD7 +:109990000C9B2022DA72DDF80C80DDF8309049460D +:1099A0004046FFF760F80446002249464046FFF76C +:1099B0006DF800210C981C30FEF72CFF039B012250 +:1099C000DA70002C39D0039BD3F830800022214676 +:1099D00004A8FFF75DFD05460028A3D14146039882 +:1099E000FFF775F90546013C039B1C6125E0062540 +:1099F000B3E7FEF77BFF08B91225B5E704A8FFF728 +:109A0000BDFE0546B0E79DF8163013F0110F13D1D7 +:109A100014F0040FAAD0082584E7002D82D19DF808 +:109A2000163013F0100F7ED114F0020F05D013F092 +:109A3000010F02D0072575E70725002D7FF472AFCF +:109A400017F0080F01D047F04007039B1B6B7362B0 +:109A50000C9BB362012F94BF0021012104A8FEF7E3 +:109A600055FF306108B902255CE7039CDDF83080C2 +:109A700041462046FEF7F7FFB06008F11C00FEF7F4 +:109A8000BAFEF0600021F1623460E388B38037757C +:109A900071753162B16106F130084FF48052404671 +:109AA000FEF7CCFE17F0200F39D0F468002C36D02A +:109AB000B461039B5F899B8903FB07F7B16801E0F1 +:109AC0000225E41BBC4294BF002301235DB953B1BE +:109AD0003046FFF794FB01460128F1D9B0F1FF3F72 +:109AE000EFD10125EDE7F161002D7FF41BAF039F5E +:109AF000B7F80C90B4FBF9F309FB13437BB138467C +:109B0000FEF792FF08B902250CE7B4FBF9F2024414 +:109B10003262012341467878FEF744FE28B9002DD1 +:109B20003FF402AFFEE60425FCE60125FAE609252E +:109B3000FAE62DE9F04F85B004460F4615469846E3 +:109B40000023C8F8003003A9FFF774F8019000283B +:109B500040F0B980637D0193002B40F0B480237DF9 +:109B600013F0010F00F0CE80E668A369F61AAE424A +:109B700067D32E4665E0E36A1BB12046FEF760FF1F +:109B800073E0E1692046FFF73AFB6EE04FF0020A0E +:109B900084F815A0CDF804A095E04FF0010A84F8F0 +:109BA00015A0CDF804A08EE04FF0020A84F815A0AD +:109BB000CDF804A087E094F91430002B04DB039B5C +:109BC0009D890AFB05F532E0236AA3EB090353459F +:109BD000F5D2039A928904F1300102FB0370FEF77B +:109BE00023FEECE7226A4A450DD094F91430002B8D +:109BF0006DDB01234A4604F1300103984078FEF7FB +:109C0000D1FD002877D1C4F82090039B9D89A369DA +:109C1000B3FBF5F205FB1233ED1AAE4200D2354626 +:109C200004F130012A4619443846FEF7FDFD2F4461 +:109C3000A3692B44A361D8F800302B44C8F8003046 +:109C4000761B002E3FD0A169039A9589B1FBF5F3ED +:109C500005FB1313002BD8D1B1FBF5F55389013B5C +:109C60001D4008D1002986D1A06801288ED9B0F105 +:109C7000FF3F92D0E061DDF80CB0E1695846FEF795 +:109C8000D3FE814600288FD0A944BBF80C30B6FB28 +:109C9000F3FAB342A6D805EB0A03BBF80A209342B5 +:109CA00001D9A2EB050A53464A4639469BF8010002 +:109CB000FEF778FD00283FF47EAF4FF0010A84F8EC +:109CC00015A0CDF804A0019805B0BDE8F08F0123E0 +:109CD00004F130019BF80100FEF770FD20B9237DEF +:109CE00003F07F03237584E74FF0010A84F815A081 +:109CF000CDF804A0E7E74FF0010A84F815A0CDF8ED +:109D000004A0E0E707230193DDE72DE9F04F85B0DC +:109D100004460F46154698460023C8F8003003A9AC +:109D2000FEF788FF019000284AD1637D0193002B44 +:109D300046D1237D13F0020F00F0EC80A369EB42C3 +:109D4000C0F0B680DD43B3E0E36A002B3CD0204690 +:109D5000FEF776FE002800F0D880012839D0B0F157 +:109D6000FF3F3DD0E061A36803B9A06094F91430CF +:109D7000002B3CDBDDF80CB0E1695846FEF754FEE1 +:109D80008146002848D0B144BBF80C30B5FBF3FA4B +:109D9000AB425FD806EB0A03BBF80A20934201D915 +:109DA000A2EB060A53464A4639469BF80100FEF7E5 +:109DB00005FDC0B34FF0010A84F815A0CDF804A04A +:109DC000019805B0BDE8F08FE1692046FFF7F5FA8C +:109DD000C0E74FF0020A84F815A0CDF804A0EFE721 +:109DE0004FF0010A84F815A0CDF804A0E8E701239C +:109DF000226A04F1300103984078FEF7DFFC20B9B5 +:109E0000237D03F07F032375B4E74FF0010A84F844 +:109E100015A0CDF804A0D3E74FF0020A84F815A0EE +:109E2000CDF804A0CCE7236AA3EB0903534504D380 +:109E3000039B9E890AFB06F62BE0039A928902FB9C +:109E4000037104F13000FEF7EFFC237D03F07F0384 +:109E50002375EDE7236A4B4503D0A269E3689A4274 +:109E600042D3C4F82090039B9E89A369B3FBF6F20A +:109E700006FB1233F61AB54200D22E4604F130002A +:109E8000324639461844FEF7CFFC237D63F07F034A +:109E900023753744A3693344A361E268934238BF12 +:109EA0001346E360D8F800303344C8F80030AD1BE7 +:109EB0005DB3A169039A9689B1FBF6F306FB131310 +:109EC000002BD0D1B1FBF6F65389013B1E407FF445 +:109ED0004DAF00297FF438AFA06800287FF43DAF74 +:109EE0002046FFF76AFA35E701234A4604F13001BC +:109EF0009BF80100FEF756FC0028B2D04FF0010A93 +:109F000084F815A0CDF804A05AE7237D43F0400360 +:109F1000237555E70723019352E770B582B00446D5 +:109F200001A9FEF787FE70B9237D13F0400F0AD018 +:109F300013F0800F09D1F9F7F5FE0546616A019823 +:109F4000FEF7C5FE78B102B070BD0123226A04F1AC +:109F5000300101984078FEF731FC40BB237D03F0CF +:109F60007F032375E7E7A66AF37A43F02003F372D1 +:109F7000A26831462068FEF789FDE16806F11C0001 +:109F8000FEF748FC294606F11600FEF743FC0021C7 +:109F900006F11200FEF73AFC019B0122DA700198EB +:109FA000FFF73AFC237D23F040032375CBE7012024 +:109FB000C9E710B582B00446FFF7AFFF08B102B0A1 +:109FC00010BD01A92046FEF735FE0028F7D1206913 +:109FD000FEF7ECFC0028F2D12060F0E72DE9F04F0D +:109FE00083B004460D4601A9FEF724FE064678B963 +:109FF000667D6EB9E36A002B00F08E80B5F1FF3FFD +:10A000000AD0E768AF4200D32F46A761002F3FD1A7 +:10A01000304603B0BDE8F08F984658F804BBD4F83A +:10A0200008A0BAF1000F27D04FF0020909F1020988 +:10A030005146002701370D462046FFF7E0F801465C +:10A04000012813D9B0F1FF3F13D001358542F1D07B +:10A05000CB4505D3434643F8087BC8F804A098468F +:10A06000019B9B698B4209D98A46DFE70226667508 +:10A07000CEE701266675CBE74FF00209E36AC3F825 +:10A080000090D94500F2FB800023C8F80030BFE7FC +:10A090007D1E29462046FEF7D3FC0146E061DDF82F +:10A0A00004804046FEF7C0FC00B3B8F80C30B5FBA6 +:10A0B000F3F5B8F80A20013A15400544B7FBF3F26E +:10A0C00003FB1277002FA3D0226AAA42A0D094F9F2 +:10A0D0001430002B0DDB01232A4604F130010198D6 +:10A0E0004078FEF75FFBA0B9256291E7022666750E +:10A0F0008EE7012304F1300198F80100FEF75EFBC2 +:10A1000020B9237D03F07F032375E4E701266675FC +:10A110007EE7012666757BE7E368AB4204D2227DC9 +:10A1200012F0020F00D11D46A3690022A261E5B121 +:10A13000019AB2F80A80928902FB08F873B16A1E8C +:10A14000B2FBF8F2013BB3FBF8F18A4206D3C8F147 +:10A1500000021340A361EF1AE56904E0A06850B360 +:10A16000E0612F460546002D45D1A369E268934280 +:10A1700004D9E360227D42F0400222750198828971 +:10A18000B3FBF2F102FB1133002B3FF441AF226A23 +:10A19000AA423FF43DAF94F91430002B5DDB01235C +:10A1A0002A4604F1300101984078FEF7FBFA0028B6 +:10A1B00062D125622CE700212046FFF7FEF8012836 +:10A1C00004D0B0F1FF3F04D0A060C9E70226667555 +:10A1D0001EE7012666751BE729462046FFF70FF8A4 +:10A1E0000546B5F1FF3F2DD0012D2ED9019B9B696E +:10A1F000AB422AD9E561474510D9A7EB0807A36907 +:10A200004344A361237D13F0020FE5D02946204685 +:10A21000FFF7D3F805460028E3D10746A3693B447E +:10A22000A3610198B0F80C80B7FBF8F308FB137337 +:10A230008BB12946FEF7F8FB054648B1B7FBF8F7A6 +:10A240003D4492E701266675E2E602266675DFE682 +:10A2500002266675DCE61D4687E7012304F130011E +:10A260004078FEF7ABFA20B9237D03F07F03237516 +:10A2700095E701266675CBE601266675C8E61126C8 +:10A28000C6E630B58FB001900C46002202A901A8A5 +:10A29000FEF774FD054610B128460FB030BD019998 +:10A2A00002A8FFF7FBF905460028F5D19DF93730E4 +:10A2B000002B06DB002CEFD0214602A8FEF7F9FBAD +:10A2C000EAE70625E8E7F0B59DB00190022203A970 +:10A2D00001A8FEF753FD039B1093044610B12046DE +:10A2E0001DB0F0BD019910A8FFF7D8F90446002869 +:10A2F000F5D1022110A8FEF7BBFA04460028EED1E2 +:10A300009DF96F30002B3CDB9DF8465015F0010F96 +:10A3100039D1039F18993846FEF7A5FB064615F07C +:10A32000100F13D1002CDAD110A8FFF7F0F8044673 +:10A33000B0FA80F04009002E08BF0020D0B9002CF0 +:10A34000CDD10398FFF768FA0446C8E70497069052 +:10A35000002104A8FEF7D1FF04460028BFD1002148 +:10A3600004A8FFF72AFA044610B10428DAD1DBE783 +:10A370000724D7E70022314610A8FFF789F80446E2 +:10A38000DDE70624ABE70724A9E70000134B5B7A5F +:10A3900013BB10B5044603F0FF00104B93F809C03F +:10A3A0005FFA8CFC4FF0000E03F80CE093F809C044 +:10A3B00003EB8C0CCCF804405C7A1C4422725A7A71 +:10A3C000541CE4B25C7230320A703A234B702F2373 +:10A3D0008B7081F803E010BD01207047B826002083 +:10A3E00008B50022FFF7D2FF08BD000010B50346F4 +:10A3F0000C4A0D490D48006840B10C480068034400 +:10A40000521A934206D8094A136010BD0748084CF7 +:10A410000460F2E7F6F7F2F90C2303604FF0FF3027 +:10A42000F3E700BF0000082000400000C426002021 +:10A43000C8260020026852E8003F23F4907342E8E7 +:10A4400000310029F6D1026802F1080353E8003F09 +:10A4500023F00103083242E800310029F3D1036EF2 +:10A46000012B06D02023C0F88030002303668366CA +:10A470007047026852E8003F23F0100342E80031C1 +:10A480000029F6D1EEE7000010B5044683680269A2 +:10A49000134342691343C269134301680868914A30 +:10A4A00002401A430A602268536823F44053E1686B +:10A4B0000B435360A269236A1A4321688B6823F413 +:10A4C000306313438B602368874A934218D0874ACE +:10A4D00093423AD0864A93424FD0864A93425ED006 +:10A4E000854A93426DD0854A93427FD0844A9342F5 +:10A4F00000F09180834A934200F0A28010230BE089 +:10A50000814BD3F8903003F00303032B1BD8DFE813 +:10A5100003F00216AB180123E069B0F5004F00F01C +:10A52000D780082B00F23881DFE813F014012701EF +:10A53000120136012A013601360136012D010423AC +:10A54000EAE70823E8E71023E6E76F4BD3F89030FB +:10A5500003F00C030C2B0ED8DFE803F0070D0D0DF4 +:10A56000090D0D0D880D0D0D0B000023D4E70423FC +:10A57000D2E70823D0E71023CEE7634BD3F890301F +:10A5800003F03003202B73D005D8002B72D0102B92 +:10A5900072D10423C0E7302B70D10823BCE75A4B9B +:10A5A000D3F8903003F0C003802B69D005D8002B7E +:10A5B00068D0402B68D10423AEE7C02B66D10823B6 +:10A5C000AAE7514BD3F8903003F44073B3F5007F02 +:10A5D0005ED006D8002B5DD0B3F5807F5CD104231C +:10A5E0009AE7B3F5407F59D1082395E7464BD3F856 +:10A5F000903003F44063B3F5006F51D006D8002BC0 +:10A6000050D0B3F5806F4FD1042385E7B3F5406F89 +:10A610004CD1082380E73C4BD3F8903003F44053EF +:10A62000B3F5005F44D006D8002B43D0B3F5805F6C +:10A6300042D1042370E7B3F5405F3FD108236BE7B5 +:10A64000314BD3F8903003F44043B3F5004F37D08B +:10A6500005D8BBB3B3F5804F36D104235CE7B3F51F +:10A66000404F33D1082357E7022355E7022353E72E +:10A67000022351E700234FE710234DE710234BE758 +:10A68000022349E7002347E7102345E7102343E768 +:10A69000022341E700233FE710233DE710233BE778 +:10A6A000022339E7012337E7102335E7102333E787 +:10A6B000022331E700232FE710232DE710232BE798 +:10A6C000022329E7002327E7102325E7102323E7A8 +:10A6D000082B5BD8DFE803F01A343A5A375A5A5A33 +:10A6E0001E0000BFF369FFEF00100140004400406E +:10A6F00000480040004C0040005000400014014061 +:10A7000000780040007C004000380240FAF71AFE52 +:10A7100000283DD06268530803EB4003B3FBF2F31B +:10A72000A3F110014FF6EF72914233D89AB222F0A2 +:10A730000F02C3F3420313432268D360002030E0CA +:10A74000FAF710FEE4E7FAF7EDFCE1E71748E1E776 +:10A75000164802E0FAF7F6FD00B3636800EB530019 +:10A76000B0FBF3F0A0F110024FF6EF739A4217D846 +:10A77000236880B2D860002013E0FAF7F3FDEBE71E +:10A78000FAF7D0FCE8E74FF40040E6E7012008E0E4 +:10A79000002006E0012004E0012002E0002000E0AB +:10A7A00001200023A366E36610BD00BF0024F4006F +:10A7B000436A13F0080F06D00268536823F400437D +:10A7C000416B0B435360436A13F0010F06D00268DC +:10A7D000536823F40033816A0B435360436A13F0D8 +:10A7E000020F06D00268536823F48033C16A0B431A +:10A7F0005360436A13F0040F06D00268536823F4D1 +:10A800008023016B0B435360436A13F0100F06D093 +:10A810000268936823F48053816B0B439360436A0F +:10A8200013F0200F06D00268936823F40053C16B25 +:10A830000B439360436A13F0400F0AD002685368D9 +:10A8400023F48013016C0B435360036CB3F5801F3A +:10A850000BD0436A13F0800F06D00268536823F4CC +:10A860000023816C0B43536070470268536823F4E4 +:10A87000C003416C0B435360EBE72DE9F8430546F9 +:10A880000E4617469946DDF820802B68DC6936EACB +:10A8900004040CBF01240024BC423AD1B8F1FF3FAC +:10A8A000F3D0FBF779FAA0EB0900404534D8B8F1B2 +:10A8B000000F33D02B681A6812F0040FE5D0B6F100 +:10A8C000400218BF0122802EDFD0002ADDD0DA69D5 +:10A8D00012F0080F11D1DA6912F4006FD5D04FF4DD +:10A8E00000621A622846FFF7A5FD2023C5F88430D0 +:10A8F000002385F8783003200CE008241C622846E9 +:10A90000FFF798FDC5F88440002385F878300120D2 +:10A9100000E00020BDE8F8830320FBE70320F9E70F +:10A9200030B583B004460023C0F88430FBF734FA16 +:10A9300005462268126812F0080F0FD123681B68C1 +:10A9400013F0040F26D12023E367C4F880300020E1 +:10A950002066606684F8780003B030BD6FF07E43F7 +:10A960000093034600224FF400112046FFF785FFB5 +:10A970000028E3D0226852E8003F23F0800342E839 +:10A9800000310029F6D12023E367002384F87830D2 +:10A990000320E1E76FF07E4300932B4600224FF443 +:10A9A00080012046FFF769FF0028CCD0226852E8DA +:10A9B000003F23F4907342E800310029F6D1226869 +:10A9C00002F1080353E8003F23F00103083242E894 +:10A9D00000310029F3D12023C4F88030002384F80B +:10A9E00078300320B8E768B310B50446C36F03B3EB +:10A9F0002423E3672268136823F001031360636A6A +:10AA0000E3B92046FFF740FD012811D022685368C2 +:10AA100023F4904353602268936823F02A039360E1 +:10AA20002268136843F0010313602046FFF778FFA4 +:10AA300010BD80F87830F9F799FDD9E72046FFF787 +:10AA4000B7FEDEE701207047DFF834D0FDF7FAFCEF +:10AA50000C480D490D4A002302E0D458C450043379 +:10AA6000C4188C42F9D30A4A0A4C002301E013604F +:10AA70000432A242FBD3F5F747FEF8F759FB7047C3 +:10AA800000000820000000205C00002020AD00082D +:10AA90005C000020C8260020FEE70000F8B500BFDB +:10AAA000F8BC08BC9E467047F8B500BFF8BC08BCAF +:04AAB0009E46704707 +:10AAB4002F000000434F4D4D414E442E5458540036 +:10AAC40046494C45312E54585400000045525252C8 +:10AAD4004F52212121202A25732A20646F65732077 +:10AAE4006E6F74206578697374730A0A000000003D +:10AAF4004552524F52212121204E6F2E2025642091 +:10AB0400696E206F70656E696E672066696C65207A +:10AB14002A25732A0A0A00004552524F5221212144 +:10AB2400204E6F2E20256420696E20726561646951 +:10AB34006E672066696C65202A25732A0A0A00005C +:10AB44004552524F52212121204E6F2E2025642040 +:10AB5400696E20636C6F73696E672066696C65202B +:10AB64002A25732A0A0A000046696C65202A25737F +:10AB74002A20434C4F5345442073756363657373B4 +:10AB840066756C6C790A00004552524F522121219E +:10AB94002043616E2774207365656B20746865209B +:10ABA40066696C653A2020202A25732A0A0A000067 +:10ABB4004552524F52212121202A25732A20646FA5 +:10ABC4006573206E6F74206578697374730A0A0064 +:10ABD4002A25732A20686173206265656E20726578 +:10ABE4006D6F766564207375636365737366756CE6 +:10ABF4006C790A004552524F52204E6F2E20256424 +:10AC040020696E2072656D6F76696E67202A2573E0 +:10AC14002A0A0A00222A2B2C3A3B3C3D3E3F5B5D2C +:10AC24007C7F0000232D302B20000000686C4C003A +:10AC34006566674546470000303132333435363770 +:10AC44003839414243444546000000003031323334 +:10AC54003435363738396162636465660000000054 +:10AC6400393C0008613C0008693C00088D3C000840 +:10AC7400B13C0008000000000102030400000000D1 +:10AC8400000000000102030406070809435545417A +:10AC94004141414345454549494941414592924FC6 +:10ACA4004F4F5555594F554F9C4F9E9F41494F55B6 +:10ACB400A5A5A6A7A8A9AAABACADAEAFB0B1B2B3D7 +:10ACC400B4414141B8B9BABBBCBDBEBFC0C1C2C327 +:10ACD400C4C54141C8C9CACBCCCDCECFD1D14545DD +:10ACE4004549494949D9DADBDCDD49DF4FE14F4FBA +:10ACF4004F4FE6E8E85555555959EEEFF0F1F2F3A8 +:0CAD0400F4F5F6F7F8F9FAFBFCFDFEFF91 +:08AD1000005EFF7F010000005E +:04AD180069020008C4 +:04AD1C0041020008E8 +:10AD2000040000200000000080000020E800002057 +:10AD300050010020000000000000000000000000A2 +:10AD40000000000000000000000000000000000003 +:10AD500000000000000000000000000000000000F3 +:10AD600000000000000000000000000000000000E3 +:0CAD700001010000100000000024F400AD +:040000050800AA49FC +:00000001FF diff --git a/build/For_stm32.map b/build/For_stm32.map new file mode 100644 index 0000000..ec8656f --- /dev/null +++ b/build/For_stm32.map @@ -0,0 +1,5297 @@ +Archive member included to satisfy reference by file (symbol) + +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) + build/File_Handling.o (sprintf) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcpy.o) + build/File_Handling.o (strcpy) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-impure.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) (_impure_ptr) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) (_svfprintf_r) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o (__libc_init_array) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strlen.o) + build/File_Handling.o (strlen) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o (memset) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-errno.o) + build/sysmem.o (__errno) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) (_malloc_r) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-freer.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) (_free_r) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memmove.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) (memmove) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memchr.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) (memchr) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) (memcpy) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-malloc.o) + build/File_Handling.o (malloc) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reallocr.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) (_realloc_r) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-vfprintf_i.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) (_printf_i) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mlock.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) (__malloc_lock) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcmp.o) + build/File_Handling.o (strcmp) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-exit.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o (exit) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-atexit.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o (atexit) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fini.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o (__libc_fini_array) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sbrkr.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) (_sbrk_r) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-msizer.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reallocr.o) (_malloc_usable_size_r) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-exit.o) (__stdio_exit_handler) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) (_fflush_r) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fwalk.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) (_fwalk_sglue) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-atexit.o) (__register_exitproc) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reent.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sbrkr.o) (errno) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) (__sread) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-closer.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) (_close_r) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__call_atexit.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) (__call_exitprocs) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-readr.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) (_read_r) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-lseekr.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) (_lseek_r) +/usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-writer.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) (_write_r) +/usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + build/stm32f7xx_hal_rcc.o (__aeabi_uldivmod) +/usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) (__udivmoddi4) +/usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) (__aeabi_ldiv0) + +Discarded input sections + + .text 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crti.o + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crti.o + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crti.o + .data 0x00000000 0x4 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o + .rodata 0x00000000 0x24 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o + .text 0x00000000 0x70 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o + .ARM.extab 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o + .ARM.exidx 0x00000000 0x10 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o + .debug_line 0x00000000 0x75 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o + .debug_line_str + 0x00000000 0x82 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o + .debug_info 0x00000000 0x24 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o + .debug_abbrev 0x00000000 0x14 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o + .debug_aranges + 0x00000000 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o + .debug_str 0x00000000 0x8e /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o + .ARM.attributes + 0x00000000 0x1e /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o + .text 0x00000000 0x0 build/main.o + .data 0x00000000 0x0 build/main.o + .bss 0x00000000 0x0 build/main.o + .text.Advanced_Controller_Temp + 0x00000000 0xe4 build/main.o + .bss.temp32 0x00000000 0x4 build/main.o + .text 0x00000000 0x0 build/bsp_driver_sd.o + .data 0x00000000 0x0 build/bsp_driver_sd.o + .bss 0x00000000 0x0 build/bsp_driver_sd.o + .text.BSP_SD_ITConfig + 0x00000000 0x4 build/bsp_driver_sd.o + .text.BSP_SD_ReadBlocks_DMA + 0x00000000 0x18 build/bsp_driver_sd.o + .text.BSP_SD_WriteBlocks_DMA + 0x00000000 0x18 build/bsp_driver_sd.o + .text.BSP_SD_Erase + 0x00000000 0x18 build/bsp_driver_sd.o + .text.BSP_SD_AbortCallback + 0x00000000 0x2 build/bsp_driver_sd.o + .text.HAL_SD_AbortCallback + 0x00000000 0x8 build/bsp_driver_sd.o + .text.BSP_SD_WriteCpltCallback + 0x00000000 0x2 build/bsp_driver_sd.o + .text.HAL_SD_TxCpltCallback + 0x00000000 0x8 build/bsp_driver_sd.o + .text.BSP_SD_ReadCpltCallback + 0x00000000 0x2 build/bsp_driver_sd.o + .text.HAL_SD_RxCpltCallback + 0x00000000 0x8 build/bsp_driver_sd.o + .text 0x00000000 0x0 build/sd_diskio.o + .data 0x00000000 0x0 build/sd_diskio.o + .bss 0x00000000 0x0 build/sd_diskio.o + .text 0x00000000 0x0 build/fatfs.o + .data 0x00000000 0x0 build/fatfs.o + .bss 0x00000000 0x0 build/fatfs.o + .bss.SDFile 0x00000000 0x1030 build/fatfs.o + .bss.SDFatFS 0x00000000 0x1034 build/fatfs.o + .text 0x00000000 0x0 build/fatfs_platform.o + .data 0x00000000 0x0 build/fatfs_platform.o + .bss 0x00000000 0x0 build/fatfs_platform.o + .text 0x00000000 0x0 build/stm32f7xx_it.o + .data 0x00000000 0x0 build/stm32f7xx_it.o + .bss 0x00000000 0x0 build/stm32f7xx_it.o + .text 0x00000000 0x0 build/stm32f7xx_hal_msp.o + .data 0x00000000 0x0 build/stm32f7xx_hal_msp.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_msp.o + .text.HAL_ADC_MspDeInit + 0x00000000 0x68 build/stm32f7xx_hal_msp.o + .text.HAL_SD_MspDeInit + 0x00000000 0x3c build/stm32f7xx_hal_msp.o + .text.HAL_TIM_Base_MspDeInit + 0x00000000 0x78 build/stm32f7xx_hal_msp.o + .text.HAL_UART_MspDeInit + 0x00000000 0x2c build/stm32f7xx_hal_msp.o + .text 0x00000000 0x0 build/stm32f7xx_hal_adc.o + .data 0x00000000 0x0 build/stm32f7xx_hal_adc.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_adc.o + .text.HAL_ADC_MspInit + 0x00000000 0x2 build/stm32f7xx_hal_adc.o + .text.HAL_ADC_MspDeInit + 0x00000000 0x2 build/stm32f7xx_hal_adc.o + .text.HAL_ADC_DeInit + 0x00000000 0x3a build/stm32f7xx_hal_adc.o + .text.HAL_ADC_PollForEvent + 0x00000000 0x7e build/stm32f7xx_hal_adc.o + .text.HAL_ADC_Start_IT + 0x00000000 0x144 build/stm32f7xx_hal_adc.o + .text.HAL_ADC_Stop_IT + 0x00000000 0x4c build/stm32f7xx_hal_adc.o + .text.HAL_ADC_Start_DMA + 0x00000000 0x180 build/stm32f7xx_hal_adc.o + .text.HAL_ADC_Stop_DMA + 0x00000000 0x78 build/stm32f7xx_hal_adc.o + .text.HAL_ADC_ConvHalfCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_adc.o + .text.ADC_DMAHalfConvCplt + 0x00000000 0xa build/stm32f7xx_hal_adc.o + .text.ADC_DMAError + 0x00000000 0x16 build/stm32f7xx_hal_adc.o + .text.ADC_DMAConvCplt + 0x00000000 0x72 build/stm32f7xx_hal_adc.o + .text.HAL_ADC_AnalogWDGConfig + 0x00000000 0x78 build/stm32f7xx_hal_adc.o + .text.HAL_ADC_GetState + 0x00000000 0x4 build/stm32f7xx_hal_adc.o + .text.HAL_ADC_GetError + 0x00000000 0x4 build/stm32f7xx_hal_adc.o + .text 0x00000000 0x0 build/stm32f7xx_hal_adc_ex.o + .data 0x00000000 0x0 build/stm32f7xx_hal_adc_ex.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_adc_ex.o + .text.ADC_MultiModeDMAError + 0x00000000 0x16 build/stm32f7xx_hal_adc_ex.o + .text.ADC_MultiModeDMAHalfConvCplt + 0x00000000 0xa build/stm32f7xx_hal_adc_ex.o + .text.ADC_MultiModeDMAConvCplt + 0x00000000 0x62 build/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_InjectedStart + 0x00000000 0xfc build/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_InjectedStart_IT + 0x00000000 0x104 build/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_InjectedStop + 0x00000000 0x64 build/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_InjectedPollForConversion + 0x00000000 0xb2 build/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_InjectedStop_IT + 0x00000000 0x6c build/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_InjectedGetValue + 0x00000000 0x40 build/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_MultiModeStart_DMA + 0x00000000 0x130 build/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_MultiModeStop_DMA + 0x00000000 0x64 build/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_MultiModeGetValue + 0x00000000 0xc build/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_InjectedConfigChannel + 0x00000000 0x208 build/stm32f7xx_hal_adc_ex.o + .text.HAL_ADCEx_MultiModeConfigChannel + 0x00000000 0x58 build/stm32f7xx_hal_adc_ex.o + .text 0x00000000 0x0 build/stm32f7xx_hal_rcc.o + .data 0x00000000 0x0 build/stm32f7xx_hal_rcc.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_rcc.o + .text.HAL_RCC_DeInit + 0x00000000 0x158 build/stm32f7xx_hal_rcc.o + .text.HAL_RCC_MCOConfig + 0x00000000 0x98 build/stm32f7xx_hal_rcc.o + .text.HAL_RCC_EnableCSS + 0x00000000 0x10 build/stm32f7xx_hal_rcc.o + .text.HAL_RCC_DisableCSS + 0x00000000 0x10 build/stm32f7xx_hal_rcc.o + .text.HAL_RCC_GetOscConfig + 0x00000000 0xe0 build/stm32f7xx_hal_rcc.o + .text.HAL_RCC_GetClockConfig + 0x00000000 0x3c build/stm32f7xx_hal_rcc.o + .text.HAL_RCC_CSSCallback + 0x00000000 0x2 build/stm32f7xx_hal_rcc.o + .text.HAL_RCC_NMI_IRQHandler + 0x00000000 0x20 build/stm32f7xx_hal_rcc.o + .text 0x00000000 0x0 build/stm32f7xx_hal_rcc_ex.o + .data 0x00000000 0x0 build/stm32f7xx_hal_rcc_ex.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_rcc_ex.o + .text.HAL_RCCEx_GetPeriphCLKConfig + 0x00000000 0x188 build/stm32f7xx_hal_rcc_ex.o + .text.HAL_RCCEx_GetPeriphCLKFreq + 0x00000000 0x1e4 build/stm32f7xx_hal_rcc_ex.o + .text.HAL_RCCEx_EnablePLLI2S + 0x00000000 0x78 build/stm32f7xx_hal_rcc_ex.o + .text.HAL_RCCEx_DisablePLLI2S + 0x00000000 0x34 build/stm32f7xx_hal_rcc_ex.o + .text.HAL_RCCEx_EnablePLLSAI + 0x00000000 0x78 build/stm32f7xx_hal_rcc_ex.o + .text.HAL_RCCEx_DisablePLLSAI + 0x00000000 0x34 build/stm32f7xx_hal_rcc_ex.o + .text 0x00000000 0x0 build/stm32f7xx_hal_flash.o + .data 0x00000000 0x0 build/stm32f7xx_hal_flash.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_flash.o + .text.FLASH_Program_DoubleWord + 0x00000000 0x34 build/stm32f7xx_hal_flash.o + .text.FLASH_Program_Word + 0x00000000 0x28 build/stm32f7xx_hal_flash.o + .text.FLASH_Program_HalfWord + 0x00000000 0x28 build/stm32f7xx_hal_flash.o + .text.FLASH_Program_Byte + 0x00000000 0x24 build/stm32f7xx_hal_flash.o + .text.FLASH_SetErrorCode + 0x00000000 0x74 build/stm32f7xx_hal_flash.o + .text.HAL_FLASH_Program_IT + 0x00000000 0x74 build/stm32f7xx_hal_flash.o + .text.HAL_FLASH_EndOfOperationCallback + 0x00000000 0x2 build/stm32f7xx_hal_flash.o + .text.HAL_FLASH_OperationErrorCallback + 0x00000000 0x2 build/stm32f7xx_hal_flash.o + .text.HAL_FLASH_IRQHandler + 0x00000000 0x108 build/stm32f7xx_hal_flash.o + .text.HAL_FLASH_Unlock + 0x00000000 0x30 build/stm32f7xx_hal_flash.o + .text.HAL_FLASH_Lock + 0x00000000 0x14 build/stm32f7xx_hal_flash.o + .text.HAL_FLASH_OB_Unlock + 0x00000000 0x28 build/stm32f7xx_hal_flash.o + .text.HAL_FLASH_OB_Lock + 0x00000000 0x14 build/stm32f7xx_hal_flash.o + .text.HAL_FLASH_GetError + 0x00000000 0xc build/stm32f7xx_hal_flash.o + .text.FLASH_WaitForLastOperation + 0x00000000 0x64 build/stm32f7xx_hal_flash.o + .text.HAL_FLASH_Program + 0x00000000 0x7c build/stm32f7xx_hal_flash.o + .text.HAL_FLASH_OB_Launch + 0x00000000 0x1c build/stm32f7xx_hal_flash.o + .bss.pFlash 0x00000000 0x1c build/stm32f7xx_hal_flash.o + .debug_info 0x00000000 0x7d4 build/stm32f7xx_hal_flash.o + .debug_abbrev 0x00000000 0x2cd build/stm32f7xx_hal_flash.o + .debug_loc 0x00000000 0x556 build/stm32f7xx_hal_flash.o + .debug_aranges + 0x00000000 0xa0 build/stm32f7xx_hal_flash.o + .debug_ranges 0x00000000 0x90 build/stm32f7xx_hal_flash.o + .debug_line 0x00000000 0x770 build/stm32f7xx_hal_flash.o + .debug_str 0x00000000 0x510 build/stm32f7xx_hal_flash.o + .comment 0x00000000 0x27 build/stm32f7xx_hal_flash.o + .debug_frame 0x00000000 0x168 build/stm32f7xx_hal_flash.o + .ARM.attributes + 0x00000000 0x32 build/stm32f7xx_hal_flash.o + .text 0x00000000 0x0 build/stm32f7xx_hal_flash_ex.o + .data 0x00000000 0x0 build/stm32f7xx_hal_flash_ex.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_flash_ex.o + .text.FLASH_MassErase + 0x00000000 0x50 build/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_GetWRP + 0x00000000 0x14 build/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_GetUser + 0x00000000 0x14 build/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_BOR_LevelConfig + 0x00000000 0x14 build/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_GetRDP + 0x00000000 0x1c build/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_GetBOR + 0x00000000 0x10 build/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_GetBootAddress + 0x00000000 0x18 build/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_EnableWRP + 0x00000000 0x20 build/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_DisableWRP + 0x00000000 0x1c build/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_RDP_LevelConfig + 0x00000000 0x18 build/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_UserConfig + 0x00000000 0x48 build/stm32f7xx_hal_flash_ex.o + .text.FLASH_OB_BootAddressConfig + 0x00000000 0x34 build/stm32f7xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBProgram + 0x00000000 0xc4 build/stm32f7xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBGetConfig + 0x00000000 0x32 build/stm32f7xx_hal_flash_ex.o + .text.FLASH_Erase_Sector + 0x00000000 0x58 build/stm32f7xx_hal_flash_ex.o + .text.HAL_FLASHEx_Erase + 0x00000000 0x98 build/stm32f7xx_hal_flash_ex.o + .text.HAL_FLASHEx_Erase_IT + 0x00000000 0x68 build/stm32f7xx_hal_flash_ex.o + .debug_info 0x00000000 0x9f6 build/stm32f7xx_hal_flash_ex.o + .debug_abbrev 0x00000000 0x28f build/stm32f7xx_hal_flash_ex.o + .debug_loc 0x00000000 0x97c build/stm32f7xx_hal_flash_ex.o + .debug_aranges + 0x00000000 0xa0 build/stm32f7xx_hal_flash_ex.o + .debug_ranges 0x00000000 0x90 build/stm32f7xx_hal_flash_ex.o + .debug_line 0x00000000 0x72c build/stm32f7xx_hal_flash_ex.o + .debug_str 0x00000000 0x5ef build/stm32f7xx_hal_flash_ex.o + .comment 0x00000000 0x27 build/stm32f7xx_hal_flash_ex.o + .debug_frame 0x00000000 0x190 build/stm32f7xx_hal_flash_ex.o + .ARM.attributes + 0x00000000 0x32 build/stm32f7xx_hal_flash_ex.o + .text 0x00000000 0x0 build/stm32f7xx_hal_gpio.o + .data 0x00000000 0x0 build/stm32f7xx_hal_gpio.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_gpio.o + .text.HAL_GPIO_DeInit + 0x00000000 0x14c build/stm32f7xx_hal_gpio.o + .text.HAL_GPIO_LockPin + 0x00000000 0x2e build/stm32f7xx_hal_gpio.o + .text.HAL_GPIO_EXTI_Callback + 0x00000000 0x2 build/stm32f7xx_hal_gpio.o + .text.HAL_GPIO_EXTI_IRQHandler + 0x00000000 0x1c build/stm32f7xx_hal_gpio.o + .text 0x00000000 0x0 build/stm32f7xx_hal_dma.o + .data 0x00000000 0x0 build/stm32f7xx_hal_dma.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_dma.o + .text.DMA_SetConfig + 0x00000000 0x2c build/stm32f7xx_hal_dma.o + .text.DMA_CalcBaseAndBitshift + 0x00000000 0x3c build/stm32f7xx_hal_dma.o + .text.DMA_CheckFifoParam + 0x00000000 0x8e build/stm32f7xx_hal_dma.o + .text.HAL_DMA_Init + 0x00000000 0xd0 build/stm32f7xx_hal_dma.o + .text.HAL_DMA_DeInit + 0x00000000 0x64 build/stm32f7xx_hal_dma.o + .text.HAL_DMA_Start + 0x00000000 0x48 build/stm32f7xx_hal_dma.o + .text.HAL_DMA_Start_IT + 0x00000000 0x74 build/stm32f7xx_hal_dma.o + .text.HAL_DMA_Abort + 0x00000000 0x94 build/stm32f7xx_hal_dma.o + .text.HAL_DMA_Abort_IT + 0x00000000 0x26 build/stm32f7xx_hal_dma.o + .text.HAL_DMA_PollForTransfer + 0x00000000 0x128 build/stm32f7xx_hal_dma.o + .text.HAL_DMA_IRQHandler + 0x00000000 0x1dc build/stm32f7xx_hal_dma.o + .text.HAL_DMA_RegisterCallback + 0x00000000 0x5a build/stm32f7xx_hal_dma.o + .text.HAL_DMA_UnRegisterCallback + 0x00000000 0x6e build/stm32f7xx_hal_dma.o + .text.HAL_DMA_GetState + 0x00000000 0x6 build/stm32f7xx_hal_dma.o + .text.HAL_DMA_GetError + 0x00000000 0x4 build/stm32f7xx_hal_dma.o + .rodata.flagBitshiftOffset.0 + 0x00000000 0x8 build/stm32f7xx_hal_dma.o + .debug_info 0x00000000 0xbb6 build/stm32f7xx_hal_dma.o + .debug_abbrev 0x00000000 0x2fe build/stm32f7xx_hal_dma.o + .debug_loc 0x00000000 0xe9a build/stm32f7xx_hal_dma.o + .debug_aranges + 0x00000000 0x90 build/stm32f7xx_hal_dma.o + .debug_ranges 0x00000000 0x80 build/stm32f7xx_hal_dma.o + .debug_line 0x00000000 0xdbe build/stm32f7xx_hal_dma.o + .debug_str 0x00000000 0x769 build/stm32f7xx_hal_dma.o + .comment 0x00000000 0x27 build/stm32f7xx_hal_dma.o + .debug_frame 0x00000000 0x188 build/stm32f7xx_hal_dma.o + .ARM.attributes + 0x00000000 0x32 build/stm32f7xx_hal_dma.o + .text 0x00000000 0x0 build/stm32f7xx_hal_dma_ex.o + .data 0x00000000 0x0 build/stm32f7xx_hal_dma_ex.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_dma_ex.o + .text.DMA_MultiBufferSetConfig + 0x00000000 0x24 build/stm32f7xx_hal_dma_ex.o + .text.HAL_DMAEx_MultiBufferStart + 0x00000000 0x5e build/stm32f7xx_hal_dma_ex.o + .text.HAL_DMAEx_MultiBufferStart_IT + 0x00000000 0xeec build/stm32f7xx_hal_dma_ex.o + .text.HAL_DMAEx_ChangeMemory + 0x00000000 0x10 build/stm32f7xx_hal_dma_ex.o + .debug_info 0x00000000 0x5ff build/stm32f7xx_hal_dma_ex.o + .debug_abbrev 0x00000000 0x1d6 build/stm32f7xx_hal_dma_ex.o + .debug_loc 0x00000000 0x4d5 build/stm32f7xx_hal_dma_ex.o + .debug_aranges + 0x00000000 0x38 build/stm32f7xx_hal_dma_ex.o + .debug_ranges 0x00000000 0x28 build/stm32f7xx_hal_dma_ex.o + .debug_line 0x00000000 0xe2e build/stm32f7xx_hal_dma_ex.o + .debug_str 0x00000000 0x546 build/stm32f7xx_hal_dma_ex.o + .comment 0x00000000 0x27 build/stm32f7xx_hal_dma_ex.o + .debug_frame 0x00000000 0x74 build/stm32f7xx_hal_dma_ex.o + .ARM.attributes + 0x00000000 0x32 build/stm32f7xx_hal_dma_ex.o + .text 0x00000000 0x0 build/stm32f7xx_hal_pwr.o + .data 0x00000000 0x0 build/stm32f7xx_hal_pwr.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_pwr.o + .text.HAL_PWR_DeInit + 0x00000000 0x18 build/stm32f7xx_hal_pwr.o + .text.HAL_PWR_EnableBkUpAccess + 0x00000000 0x10 build/stm32f7xx_hal_pwr.o + .text.HAL_PWR_DisableBkUpAccess + 0x00000000 0x10 build/stm32f7xx_hal_pwr.o + .text.HAL_PWR_ConfigPVD + 0x00000000 0x84 build/stm32f7xx_hal_pwr.o + .text.HAL_PWR_EnablePVD + 0x00000000 0x10 build/stm32f7xx_hal_pwr.o + .text.HAL_PWR_DisablePVD + 0x00000000 0x10 build/stm32f7xx_hal_pwr.o + .text.HAL_PWR_EnableWakeUpPin + 0x00000000 0x20 build/stm32f7xx_hal_pwr.o + .text.HAL_PWR_DisableWakeUpPin + 0x00000000 0x10 build/stm32f7xx_hal_pwr.o + .text.HAL_PWR_EnterSLEEPMode + 0x00000000 0x28 build/stm32f7xx_hal_pwr.o + .text.HAL_PWR_EnterSTOPMode + 0x00000000 0x40 build/stm32f7xx_hal_pwr.o + .text.HAL_PWR_EnterSTANDBYMode + 0x00000000 0x20 build/stm32f7xx_hal_pwr.o + .text.HAL_PWR_PVDCallback + 0x00000000 0x2 build/stm32f7xx_hal_pwr.o + .text.HAL_PWR_PVD_IRQHandler + 0x00000000 0x20 build/stm32f7xx_hal_pwr.o + .text.HAL_PWR_EnableSleepOnExit + 0x00000000 0x10 build/stm32f7xx_hal_pwr.o + .text.HAL_PWR_DisableSleepOnExit + 0x00000000 0x10 build/stm32f7xx_hal_pwr.o + .text.HAL_PWR_EnableSEVOnPend + 0x00000000 0x10 build/stm32f7xx_hal_pwr.o + .text.HAL_PWR_DisableSEVOnPend + 0x00000000 0x10 build/stm32f7xx_hal_pwr.o + .debug_info 0x00000000 0xa94 build/stm32f7xx_hal_pwr.o + .debug_abbrev 0x00000000 0x1cf build/stm32f7xx_hal_pwr.o + .debug_loc 0x00000000 0x7f build/stm32f7xx_hal_pwr.o + .debug_aranges + 0x00000000 0xa0 build/stm32f7xx_hal_pwr.o + .debug_ranges 0x00000000 0x90 build/stm32f7xx_hal_pwr.o + .debug_line 0x00000000 0x3dc build/stm32f7xx_hal_pwr.o + .debug_str 0x00000000 0x630 build/stm32f7xx_hal_pwr.o + .comment 0x00000000 0x27 build/stm32f7xx_hal_pwr.o + .debug_frame 0x00000000 0x128 build/stm32f7xx_hal_pwr.o + .ARM.attributes + 0x00000000 0x32 build/stm32f7xx_hal_pwr.o + .text 0x00000000 0x0 build/stm32f7xx_hal_pwr_ex.o + .data 0x00000000 0x0 build/stm32f7xx_hal_pwr_ex.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_EnableBkUpReg + 0x00000000 0x3c build/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableBkUpReg + 0x00000000 0x3c build/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_EnableFlashPowerDown + 0x00000000 0x10 build/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableFlashPowerDown + 0x00000000 0x10 build/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_EnableMainRegulatorLowVoltage + 0x00000000 0x10 build/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableMainRegulatorLowVoltage + 0x00000000 0x10 build/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_EnableLowRegulatorLowVoltage + 0x00000000 0x10 build/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableLowRegulatorLowVoltage + 0x00000000 0x10 build/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableOverDrive + 0x00000000 0x7c build/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_EnterUnderDriveSTOPMode + 0x00000000 0x98 build/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_GetVoltageRange + 0x00000000 0x10 build/stm32f7xx_hal_pwr_ex.o + .text.HAL_PWREx_ControlVoltageScaling + 0x00000000 0xc0 build/stm32f7xx_hal_pwr_ex.o + .text 0x00000000 0x0 build/stm32f7xx_hal_cortex.o + .data 0x00000000 0x0 build/stm32f7xx_hal_cortex.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_cortex.o + .text.__NVIC_DisableIRQ + 0x00000000 0x24 build/stm32f7xx_hal_cortex.o + .text.__NVIC_GetPriority + 0x00000000 0x20 build/stm32f7xx_hal_cortex.o + .text.NVIC_DecodePriority + 0x00000000 0x3e build/stm32f7xx_hal_cortex.o + .text.__NVIC_SystemReset + 0x00000000 0x24 build/stm32f7xx_hal_cortex.o + .text.HAL_NVIC_DisableIRQ + 0x00000000 0x8 build/stm32f7xx_hal_cortex.o + .text.HAL_NVIC_SystemReset + 0x00000000 0x6 build/stm32f7xx_hal_cortex.o + .text.HAL_MPU_Disable + 0x00000000 0x1c build/stm32f7xx_hal_cortex.o + .text.HAL_MPU_Enable + 0x00000000 0x20 build/stm32f7xx_hal_cortex.o + .text.HAL_MPU_EnableRegion + 0x00000000 0x18 build/stm32f7xx_hal_cortex.o + .text.HAL_MPU_DisableRegion + 0x00000000 0x18 build/stm32f7xx_hal_cortex.o + .text.HAL_MPU_ConfigRegion + 0x00000000 0x58 build/stm32f7xx_hal_cortex.o + .text.HAL_NVIC_GetPriorityGrouping + 0x00000000 0x10 build/stm32f7xx_hal_cortex.o + .text.HAL_NVIC_GetPriority + 0x00000000 0x18 build/stm32f7xx_hal_cortex.o + .text.HAL_NVIC_SetPendingIRQ + 0x00000000 0x1c build/stm32f7xx_hal_cortex.o + .text.HAL_NVIC_GetPendingIRQ + 0x00000000 0x24 build/stm32f7xx_hal_cortex.o + .text.HAL_NVIC_ClearPendingIRQ + 0x00000000 0x1c build/stm32f7xx_hal_cortex.o + .text.HAL_NVIC_GetActive + 0x00000000 0x24 build/stm32f7xx_hal_cortex.o + .text.HAL_SYSTICK_CLKSourceConfig + 0x00000000 0x20 build/stm32f7xx_hal_cortex.o + .text.HAL_SYSTICK_Callback + 0x00000000 0x2 build/stm32f7xx_hal_cortex.o + .text.HAL_SYSTICK_IRQHandler + 0x00000000 0x8 build/stm32f7xx_hal_cortex.o + .text 0x00000000 0x0 build/stm32f7xx_hal.o + .data 0x00000000 0x0 build/stm32f7xx_hal.o + .bss 0x00000000 0x0 build/stm32f7xx_hal.o + .text.HAL_MspInit + 0x00000000 0x2 build/stm32f7xx_hal.o + .text.HAL_MspDeInit + 0x00000000 0x2 build/stm32f7xx_hal.o + .text.HAL_DeInit + 0x00000000 0x2c build/stm32f7xx_hal.o + .text.HAL_GetTickPrio + 0x00000000 0xc build/stm32f7xx_hal.o + .text.HAL_SetTickFreq + 0x00000000 0x2c build/stm32f7xx_hal.o + .text.HAL_GetTickFreq + 0x00000000 0xc build/stm32f7xx_hal.o + .text.HAL_SuspendTick + 0x00000000 0xe build/stm32f7xx_hal.o + .text.HAL_ResumeTick + 0x00000000 0xe build/stm32f7xx_hal.o + .text.HAL_GetHalVersion + 0x00000000 0x8 build/stm32f7xx_hal.o + .text.HAL_GetREVID + 0x00000000 0xc build/stm32f7xx_hal.o + .text.HAL_GetDEVID + 0x00000000 0x10 build/stm32f7xx_hal.o + .text.HAL_GetUIDw0 + 0x00000000 0xc build/stm32f7xx_hal.o + .text.HAL_GetUIDw1 + 0x00000000 0xc build/stm32f7xx_hal.o + .text.HAL_GetUIDw2 + 0x00000000 0xc build/stm32f7xx_hal.o + .text.HAL_DBGMCU_EnableDBGSleepMode + 0x00000000 0x10 build/stm32f7xx_hal.o + .text.HAL_DBGMCU_DisableDBGSleepMode + 0x00000000 0x10 build/stm32f7xx_hal.o + .text.HAL_DBGMCU_EnableDBGStopMode + 0x00000000 0x10 build/stm32f7xx_hal.o + .text.HAL_DBGMCU_DisableDBGStopMode + 0x00000000 0x10 build/stm32f7xx_hal.o + .text.HAL_DBGMCU_EnableDBGStandbyMode + 0x00000000 0x10 build/stm32f7xx_hal.o + .text.HAL_DBGMCU_DisableDBGStandbyMode + 0x00000000 0x10 build/stm32f7xx_hal.o + .text.HAL_EnableCompensationCell + 0x00000000 0x10 build/stm32f7xx_hal.o + .text.HAL_DisableCompensationCell + 0x00000000 0x10 build/stm32f7xx_hal.o + .text.HAL_EnableFMCMemorySwapping + 0x00000000 0x10 build/stm32f7xx_hal.o + .text.HAL_DisableFMCMemorySwapping + 0x00000000 0x10 build/stm32f7xx_hal.o + .text.HAL_EnableMemorySwappingBank + 0x00000000 0x10 build/stm32f7xx_hal.o + .text.HAL_DisableMemorySwappingBank + 0x00000000 0x10 build/stm32f7xx_hal.o + .text 0x00000000 0x0 build/stm32f7xx_hal_i2c.o + .data 0x00000000 0x0 build/stm32f7xx_hal_i2c.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_i2c.o + .text.I2C_Flush_TXDR + 0x00000000 0x22 build/stm32f7xx_hal_i2c.o + .text.I2C_TransferConfig + 0x00000000 0x3c build/stm32f7xx_hal_i2c.o + .text.I2C_Enable_IRQ + 0x00000000 0x9c build/stm32f7xx_hal_i2c.o + .text.I2C_Disable_IRQ + 0x00000000 0x70 build/stm32f7xx_hal_i2c.o + .text.I2C_ConvertOtherXferOptions + 0x00000000 0x1e build/stm32f7xx_hal_i2c.o + .text.I2C_IsErrorOccurred + 0x00000000 0x118 build/stm32f7xx_hal_i2c.o + .text.I2C_WaitOnTXISFlagUntilTimeout + 0x00000000 0x60 build/stm32f7xx_hal_i2c.o + .text.I2C_WaitOnFlagUntilTimeout + 0x00000000 0x7c build/stm32f7xx_hal_i2c.o + .text.I2C_RequestMemoryWrite + 0x00000000 0x7c build/stm32f7xx_hal_i2c.o + .text.I2C_RequestMemoryRead + 0x00000000 0x78 build/stm32f7xx_hal_i2c.o + .text.I2C_WaitOnSTOPFlagUntilTimeout + 0x00000000 0x5e build/stm32f7xx_hal_i2c.o + .text.I2C_WaitOnRXNEFlagUntilTimeout + 0x00000000 0xaa build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_MspInit + 0x00000000 0x2 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Init + 0x00000000 0xc8 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_MspDeInit + 0x00000000 0x2 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_DeInit + 0x00000000 0x32 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit + 0x00000000 0x1a4 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Receive + 0x00000000 0x17c build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit + 0x00000000 0x1f4 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive + 0x00000000 0x184 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit_IT + 0x00000000 0xc8 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Receive_IT + 0x00000000 0x98 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit_IT + 0x00000000 0x8c build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive_IT + 0x00000000 0x64 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit_DMA + 0x00000000 0x174 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Receive_DMA + 0x00000000 0x150 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit_DMA + 0x00000000 0x140 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive_DMA + 0x00000000 0xf4 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Mem_Write + 0x00000000 0x1aa build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Mem_Read + 0x00000000 0x1b0 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Mem_Write_IT + 0x00000000 0xb8 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Mem_Read_IT + 0x00000000 0xb4 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Mem_Write_DMA + 0x00000000 0x134 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Mem_Read_DMA + 0x00000000 0x134 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_IsDeviceReady + 0x00000000 0x13c build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Transmit_IT + 0x00000000 0x10c build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Transmit_DMA + 0x00000000 0x1e4 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Receive_IT + 0x00000000 0xb4 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Receive_DMA + 0x00000000 0x174 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Transmit_IT + 0x00000000 0xe4 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Transmit_DMA + 0x00000000 0x1ac build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Receive_IT + 0x00000000 0xe4 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Receive_DMA + 0x00000000 0x1ac build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_EnableListen_IT + 0x00000000 0x2c build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_DisableListen_IT + 0x00000000 0x3a build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_Master_Abort_IT + 0x00000000 0x88 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_EV_IRQHandler + 0x00000000 0x10 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_MasterTxCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_MasterRxCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_i2c.o + .text.I2C_ITMasterSeqCplt + 0x00000000 0x54 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_SlaveTxCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_SlaveRxCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_i2c.o + .text.I2C_ITSlaveSeqCplt + 0x00000000 0x82 build/stm32f7xx_hal_i2c.o + .text.I2C_DMASlaveTransmitCplt + 0x00000000 0x22 build/stm32f7xx_hal_i2c.o + .text.I2C_DMASlaveReceiveCplt + 0x00000000 0x26 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_AddrCallback + 0x00000000 0x2 build/stm32f7xx_hal_i2c.o + .text.I2C_ITAddrCplt + 0x00000000 0xa0 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_ListenCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_i2c.o + .text.I2C_ITListenCplt + 0x00000000 0x68 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_MemTxCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_MemRxCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_ErrorCallback + 0x00000000 0x2 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_AbortCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_i2c.o + .text.I2C_TreatErrorCallback + 0x00000000 0x2e build/stm32f7xx_hal_i2c.o + .text.I2C_ITError + 0x00000000 0x130 build/stm32f7xx_hal_i2c.o + .text.I2C_ITSlaveCplt + 0x00000000 0x1f0 build/stm32f7xx_hal_i2c.o + .text.I2C_Slave_ISR_IT + 0x00000000 0x14a build/stm32f7xx_hal_i2c.o + .text.I2C_ITMasterCplt + 0x00000000 0x12e build/stm32f7xx_hal_i2c.o + .text.I2C_Master_ISR_IT + 0x00000000 0x1ac build/stm32f7xx_hal_i2c.o + .text.I2C_Mem_ISR_DMA + 0x00000000 0x1d0 build/stm32f7xx_hal_i2c.o + .text.I2C_Slave_ISR_DMA + 0x00000000 0x124 build/stm32f7xx_hal_i2c.o + .text.I2C_Master_ISR_DMA + 0x00000000 0x154 build/stm32f7xx_hal_i2c.o + .text.I2C_DMAError + 0x00000000 0x44 build/stm32f7xx_hal_i2c.o + .text.I2C_DMAMasterTransmitCplt + 0x00000000 0x5a build/stm32f7xx_hal_i2c.o + .text.I2C_DMAMasterReceiveCplt + 0x00000000 0x6a build/stm32f7xx_hal_i2c.o + .text.I2C_Mem_ISR_IT + 0x00000000 0x1c0 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_ER_IRQHandler + 0x00000000 0x6a build/stm32f7xx_hal_i2c.o + .text.I2C_DMAAbort + 0x00000000 0x1a build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_GetState + 0x00000000 0x6 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_GetMode + 0x00000000 0x6 build/stm32f7xx_hal_i2c.o + .text.HAL_I2C_GetError + 0x00000000 0x4 build/stm32f7xx_hal_i2c.o + .debug_info 0x00000000 0x471d build/stm32f7xx_hal_i2c.o + .debug_abbrev 0x00000000 0x2e4 build/stm32f7xx_hal_i2c.o + .debug_loc 0x00000000 0x655b build/stm32f7xx_hal_i2c.o + .debug_aranges + 0x00000000 0x2a0 build/stm32f7xx_hal_i2c.o + .debug_ranges 0x00000000 0x290 build/stm32f7xx_hal_i2c.o + .debug_line 0x00000000 0x4da9 build/stm32f7xx_hal_i2c.o + .debug_str 0x00000000 0x1055 build/stm32f7xx_hal_i2c.o + .comment 0x00000000 0x27 build/stm32f7xx_hal_i2c.o + .debug_frame 0x00000000 0x988 build/stm32f7xx_hal_i2c.o + .ARM.attributes + 0x00000000 0x32 build/stm32f7xx_hal_i2c.o + .text 0x00000000 0x0 build/stm32f7xx_hal_i2c_ex.o + .data 0x00000000 0x0 build/stm32f7xx_hal_i2c_ex.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_i2c_ex.o + .text.HAL_I2CEx_ConfigAnalogFilter + 0x00000000 0x5c build/stm32f7xx_hal_i2c_ex.o + .text.HAL_I2CEx_ConfigDigitalFilter + 0x00000000 0x58 build/stm32f7xx_hal_i2c_ex.o + .text.HAL_I2CEx_EnableFastModePlus + 0x00000000 0x2c build/stm32f7xx_hal_i2c_ex.o + .text.HAL_I2CEx_DisableFastModePlus + 0x00000000 0x2c build/stm32f7xx_hal_i2c_ex.o + .debug_info 0x00000000 0xab8 build/stm32f7xx_hal_i2c_ex.o + .debug_abbrev 0x00000000 0x1b5 build/stm32f7xx_hal_i2c_ex.o + .debug_loc 0x00000000 0x197 build/stm32f7xx_hal_i2c_ex.o + .debug_aranges + 0x00000000 0x38 build/stm32f7xx_hal_i2c_ex.o + .debug_ranges 0x00000000 0x28 build/stm32f7xx_hal_i2c_ex.o + .debug_line 0x00000000 0x274 build/stm32f7xx_hal_i2c_ex.o + .debug_str 0x00000000 0x8d5 build/stm32f7xx_hal_i2c_ex.o + .comment 0x00000000 0x27 build/stm32f7xx_hal_i2c_ex.o + .debug_frame 0x00000000 0x60 build/stm32f7xx_hal_i2c_ex.o + .ARM.attributes + 0x00000000 0x32 build/stm32f7xx_hal_i2c_ex.o + .text 0x00000000 0x0 build/stm32f7xx_hal_exti.o + .data 0x00000000 0x0 build/stm32f7xx_hal_exti.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_exti.o + .text.HAL_EXTI_SetConfigLine + 0x00000000 0xd4 build/stm32f7xx_hal_exti.o + .text.HAL_EXTI_GetConfigLine + 0x00000000 0xa8 build/stm32f7xx_hal_exti.o + .text.HAL_EXTI_ClearConfigLine + 0x00000000 0x84 build/stm32f7xx_hal_exti.o + .text.HAL_EXTI_RegisterCallback + 0x00000000 0xe build/stm32f7xx_hal_exti.o + .text.HAL_EXTI_GetHandle + 0x00000000 0xc build/stm32f7xx_hal_exti.o + .text.HAL_EXTI_IRQHandler + 0x00000000 0x24 build/stm32f7xx_hal_exti.o + .text.HAL_EXTI_GetPending + 0x00000000 0x18 build/stm32f7xx_hal_exti.o + .text.HAL_EXTI_ClearPending + 0x00000000 0x14 build/stm32f7xx_hal_exti.o + .text.HAL_EXTI_GenerateSWI + 0x00000000 0x14 build/stm32f7xx_hal_exti.o + .debug_info 0x00000000 0x613 build/stm32f7xx_hal_exti.o + .debug_abbrev 0x00000000 0x1ef build/stm32f7xx_hal_exti.o + .debug_loc 0x00000000 0x5f6 build/stm32f7xx_hal_exti.o + .debug_aranges + 0x00000000 0x60 build/stm32f7xx_hal_exti.o + .debug_ranges 0x00000000 0x50 build/stm32f7xx_hal_exti.o + .debug_line 0x00000000 0x55d build/stm32f7xx_hal_exti.o + .debug_str 0x00000000 0x3de build/stm32f7xx_hal_exti.o + .comment 0x00000000 0x27 build/stm32f7xx_hal_exti.o + .debug_frame 0x00000000 0xe8 build/stm32f7xx_hal_exti.o + .ARM.attributes + 0x00000000 0x32 build/stm32f7xx_hal_exti.o + .text 0x00000000 0x0 build/stm32f7xx_ll_rcc.o + .data 0x00000000 0x0 build/stm32f7xx_ll_rcc.o + .bss 0x00000000 0x0 build/stm32f7xx_ll_rcc.o + .text.LL_RCC_DeInit + 0x00000000 0x98 build/stm32f7xx_ll_rcc.o + .text.LL_RCC_GetCECClockFreq + 0x00000000 0x30 build/stm32f7xx_ll_rcc.o + .text.LL_RCC_GetSystemClocksFreq + 0x00000000 0x20 build/stm32f7xx_ll_rcc.o + .text.LL_RCC_GetI2CClockFreq + 0x00000000 0x120 build/stm32f7xx_ll_rcc.o + .text.LL_RCC_GetLPTIMClockFreq + 0x00000000 0x6c build/stm32f7xx_ll_rcc.o + .text.LL_RCC_GetDFSDMClockFreq + 0x00000000 0x28 build/stm32f7xx_ll_rcc.o + .text.RCC_PLL_GetFreqDomain_48M + 0x00000000 0x40 build/stm32f7xx_ll_rcc.o + .text.RCC_PLLSAI_GetFreqDomain_SAI + 0x00000000 0x50 build/stm32f7xx_ll_rcc.o + .text.RCC_PLLSAI_GetFreqDomain_48M + 0x00000000 0x48 build/stm32f7xx_ll_rcc.o + .text.LL_RCC_GetSDMMCClockFreq + 0x00000000 0x94 build/stm32f7xx_ll_rcc.o + .text.LL_RCC_GetRNGClockFreq + 0x00000000 0x34 build/stm32f7xx_ll_rcc.o + .text.LL_RCC_GetUSBClockFreq + 0x00000000 0x34 build/stm32f7xx_ll_rcc.o + .text.RCC_PLLSAI_GetFreqDomain_LTDC + 0x00000000 0x58 build/stm32f7xx_ll_rcc.o + .text.LL_RCC_GetLTDCClockFreq + 0x00000000 0x18 build/stm32f7xx_ll_rcc.o + .text.RCC_PLLI2S_GetFreqDomain_SAI + 0x00000000 0x50 build/stm32f7xx_ll_rcc.o + .text.LL_RCC_GetSAIClockFreq + 0x00000000 0x11c build/stm32f7xx_ll_rcc.o + .text.LL_RCC_GetDFSDMAudioClockFreq + 0x00000000 0x24 build/stm32f7xx_ll_rcc.o + .text.RCC_PLLI2S_GetFreqDomain_SPDIFRX + 0x00000000 0x48 build/stm32f7xx_ll_rcc.o + .text.LL_RCC_GetSPDIFRXClockFreq + 0x00000000 0x18 build/stm32f7xx_ll_rcc.o + .text.RCC_PLLI2S_GetFreqDomain_I2S + 0x00000000 0x44 build/stm32f7xx_ll_rcc.o + .text.LL_RCC_GetI2SClockFreq + 0x00000000 0x34 build/stm32f7xx_ll_rcc.o + .rodata.aRCC_PLLSAIDIVRPrescTable + 0x00000000 0x4 build/stm32f7xx_ll_rcc.o + .text 0x00000000 0x0 build/stm32f7xx_ll_utils.o + .data 0x00000000 0x0 build/stm32f7xx_ll_utils.o + .bss 0x00000000 0x0 build/stm32f7xx_ll_utils.o + .text.UTILS_GetPLLOutputFrequency + 0x00000000 0x20 build/stm32f7xx_ll_utils.o + .text.UTILS_PLL_IsBusy + 0x00000000 0x30 build/stm32f7xx_ll_utils.o + .text.LL_Init1msTick + 0x00000000 0x20 build/stm32f7xx_ll_utils.o + .text.LL_mDelay + 0x00000000 0x2a build/stm32f7xx_ll_utils.o + .text.LL_SetSystemCoreClock + 0x00000000 0xc build/stm32f7xx_ll_utils.o + .text.LL_SetFlashLatency + 0x00000000 0x160 build/stm32f7xx_ll_utils.o + .text.UTILS_EnablePLLAndSwitchSystem + 0x00000000 0xac build/stm32f7xx_ll_utils.o + .text.LL_PLL_ConfigSystemClock_HSI + 0x00000000 0x64 build/stm32f7xx_ll_utils.o + .text.LL_PLL_ConfigSystemClock_HSE + 0x00000000 0x84 build/stm32f7xx_ll_utils.o + .debug_info 0x00000000 0xdcd build/stm32f7xx_ll_utils.o + .debug_abbrev 0x00000000 0x2f3 build/stm32f7xx_ll_utils.o + .debug_loc 0x00000000 0x93f build/stm32f7xx_ll_utils.o + .debug_aranges + 0x00000000 0x60 build/stm32f7xx_ll_utils.o + .debug_ranges 0x00000000 0x50 build/stm32f7xx_ll_utils.o + .debug_line 0x00000000 0x7ae build/stm32f7xx_ll_utils.o + .debug_str 0x00000000 0x76e build/stm32f7xx_ll_utils.o + .comment 0x00000000 0x27 build/stm32f7xx_ll_utils.o + .debug_frame 0x00000000 0xec build/stm32f7xx_ll_utils.o + .ARM.attributes + 0x00000000 0x32 build/stm32f7xx_ll_utils.o + .text 0x00000000 0x0 build/stm32f7xx_ll_exti.o + .data 0x00000000 0x0 build/stm32f7xx_ll_exti.o + .bss 0x00000000 0x0 build/stm32f7xx_ll_exti.o + .text.LL_EXTI_DeInit + 0x00000000 0x1c build/stm32f7xx_ll_exti.o + .text.LL_EXTI_Init + 0x00000000 0xd8 build/stm32f7xx_ll_exti.o + .text.LL_EXTI_StructInit + 0x00000000 0xe build/stm32f7xx_ll_exti.o + .debug_info 0x00000000 0x52a build/stm32f7xx_ll_exti.o + .debug_abbrev 0x00000000 0x1d9 build/stm32f7xx_ll_exti.o + .debug_loc 0x00000000 0x322 build/stm32f7xx_ll_exti.o + .debug_aranges + 0x00000000 0x30 build/stm32f7xx_ll_exti.o + .debug_ranges 0x00000000 0x98 build/stm32f7xx_ll_exti.o + .debug_line 0x00000000 0x36c build/stm32f7xx_ll_exti.o + .debug_str 0x00000000 0x381 build/stm32f7xx_ll_exti.o + .comment 0x00000000 0x27 build/stm32f7xx_ll_exti.o + .debug_frame 0x00000000 0x50 build/stm32f7xx_ll_exti.o + .ARM.attributes + 0x00000000 0x32 build/stm32f7xx_ll_exti.o + .text 0x00000000 0x0 build/stm32f7xx_ll_gpio.o + .data 0x00000000 0x0 build/stm32f7xx_ll_gpio.o + .bss 0x00000000 0x0 build/stm32f7xx_ll_gpio.o + .text.LL_GPIO_DeInit + 0x00000000 0x17c build/stm32f7xx_ll_gpio.o + .text.LL_GPIO_StructInit + 0x00000000 0x16 build/stm32f7xx_ll_gpio.o + .text 0x00000000 0x0 build/stm32f7xx_ll_dma.o + .data 0x00000000 0x0 build/stm32f7xx_ll_dma.o + .bss 0x00000000 0x0 build/stm32f7xx_ll_dma.o + .text.LL_DMA_DeInit + 0x00000000 0x1f8 build/stm32f7xx_ll_dma.o + .text.LL_DMA_Init + 0x00000000 0x9c build/stm32f7xx_ll_dma.o + .text.LL_DMA_StructInit + 0x00000000 0x22 build/stm32f7xx_ll_dma.o + .rodata.STREAM_OFFSET_TAB + 0x00000000 0x8 build/stm32f7xx_ll_dma.o + .debug_info 0x00000000 0xb2f build/stm32f7xx_ll_dma.o + .debug_abbrev 0x00000000 0x26a build/stm32f7xx_ll_dma.o + .debug_loc 0x00000000 0x6ad build/stm32f7xx_ll_dma.o + .debug_aranges + 0x00000000 0x30 build/stm32f7xx_ll_dma.o + .debug_ranges 0x00000000 0x68 build/stm32f7xx_ll_dma.o + .debug_line 0x00000000 0x502 build/stm32f7xx_ll_dma.o + .debug_str 0x00000000 0x5e5 build/stm32f7xx_ll_dma.o + .comment 0x00000000 0x27 build/stm32f7xx_ll_dma.o + .debug_frame 0x00000000 0x60 build/stm32f7xx_ll_dma.o + .ARM.attributes + 0x00000000 0x32 build/stm32f7xx_ll_dma.o + .text 0x00000000 0x0 build/stm32f7xx_ll_sdmmc.o + .data 0x00000000 0x0 build/stm32f7xx_ll_sdmmc.o + .bss 0x00000000 0x0 build/stm32f7xx_ll_sdmmc.o + .text.SDMMC_PowerState_OFF + 0x00000000 0x8 build/stm32f7xx_ll_sdmmc.o + .text.SDMMC_GetDataCounter + 0x00000000 0x4 build/stm32f7xx_ll_sdmmc.o + .text.SDMMC_GetFIFOCount + 0x00000000 0x6 build/stm32f7xx_ll_sdmmc.o + .text.SDMMC_SetSDMMCReadWaitMode + 0x00000000 0xe build/stm32f7xx_ll_sdmmc.o + .text.SDMMC_CmdSDEraseStartAdd + 0x00000000 0x30 build/stm32f7xx_ll_sdmmc.o + .text.SDMMC_CmdSDEraseEndAdd + 0x00000000 0x30 build/stm32f7xx_ll_sdmmc.o + .text.SDMMC_CmdEraseStartAdd + 0x00000000 0x30 build/stm32f7xx_ll_sdmmc.o + .text.SDMMC_CmdEraseEndAdd + 0x00000000 0x30 build/stm32f7xx_ll_sdmmc.o + .text.SDMMC_CmdErase + 0x00000000 0x30 build/stm32f7xx_ll_sdmmc.o + .text.SDMMC_CmdSetRelAddMmc + 0x00000000 0x32 build/stm32f7xx_ll_sdmmc.o + .text.SDMMC_CmdStatusRegister + 0x00000000 0x30 build/stm32f7xx_ll_sdmmc.o + .text.SDMMC_CmdSwitch + 0x00000000 0x30 build/stm32f7xx_ll_sdmmc.o + .text.SDMMC_CmdSendEXTCSD + 0x00000000 0x30 build/stm32f7xx_ll_sdmmc.o + .text.SDMMC_CmdOpCondition + 0x00000000 0x2a build/stm32f7xx_ll_sdmmc.o + .text 0x00000000 0x0 build/stm32f7xx_hal_sd.o + .data 0x00000000 0x0 build/stm32f7xx_hal_sd.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_sd.o + .text.SD_DMATransmitCplt + 0x00000000 0xe build/stm32f7xx_hal_sd.o + .text.SD_PowerOFF + 0x00000000 0xa build/stm32f7xx_hal_sd.o + .text.SD_Read_IT + 0x00000000 0x38 build/stm32f7xx_hal_sd.o + .text.SD_Write_IT + 0x00000000 0x48 build/stm32f7xx_hal_sd.o + .text.SD_SendSDStatus + 0x00000000 0x106 build/stm32f7xx_hal_sd.o + .text.HAL_SD_MspInit + 0x00000000 0x2 build/stm32f7xx_hal_sd.o + .text.HAL_SD_MspDeInit + 0x00000000 0x2 build/stm32f7xx_hal_sd.o + .text.HAL_SD_DeInit + 0x00000000 0x24 build/stm32f7xx_hal_sd.o + .text.HAL_SD_ReadBlocks_IT + 0x00000000 0xcc build/stm32f7xx_hal_sd.o + .text.HAL_SD_WriteBlocks_IT + 0x00000000 0xc4 build/stm32f7xx_hal_sd.o + .text.HAL_SD_ReadBlocks_DMA + 0x00000000 0x134 build/stm32f7xx_hal_sd.o + .text.HAL_SD_WriteBlocks_DMA + 0x00000000 0x130 build/stm32f7xx_hal_sd.o + .text.HAL_SD_Erase + 0x00000000 0xf8 build/stm32f7xx_hal_sd.o + .text.HAL_SD_GetState + 0x00000000 0x6 build/stm32f7xx_hal_sd.o + .text.HAL_SD_GetError + 0x00000000 0x4 build/stm32f7xx_hal_sd.o + .text.HAL_SD_TxCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_sd.o + .text.HAL_SD_RxCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_sd.o + .text.HAL_SD_ErrorCallback + 0x00000000 0x2 build/stm32f7xx_hal_sd.o + .text.SD_DMAReceiveCplt + 0x00000000 0x48 build/stm32f7xx_hal_sd.o + .text.HAL_SD_AbortCallback + 0x00000000 0x2 build/stm32f7xx_hal_sd.o + .text.HAL_SD_GetCardCID + 0x00000000 0x58 build/stm32f7xx_hal_sd.o + .text.HAL_SD_GetCardStatus + 0x00000000 0xac build/stm32f7xx_hal_sd.o + .text.SD_DMAError + 0x00000000 0x68 build/stm32f7xx_hal_sd.o + .text.SD_DMATxAbort + 0x00000000 0x44 build/stm32f7xx_hal_sd.o + .text.SD_DMARxAbort + 0x00000000 0x44 build/stm32f7xx_hal_sd.o + .text.HAL_SD_IRQHandler + 0x00000000 0x1c8 build/stm32f7xx_hal_sd.o + .text.HAL_SD_Abort + 0x00000000 0x92 build/stm32f7xx_hal_sd.o + .text.HAL_SD_Abort_IT + 0x00000000 0xa8 build/stm32f7xx_hal_sd.o + .text 0x00000000 0x0 build/stm32f7xx_ll_spi.o + .data 0x00000000 0x0 build/stm32f7xx_ll_spi.o + .bss 0x00000000 0x0 build/stm32f7xx_ll_spi.o + .text.LL_SPI_DeInit + 0x00000000 0xd4 build/stm32f7xx_ll_spi.o + .text.LL_SPI_StructInit + 0x00000000 0x1e build/stm32f7xx_ll_spi.o + .text.LL_I2S_DeInit + 0x00000000 0x8 build/stm32f7xx_ll_spi.o + .text.LL_I2S_Init + 0x00000000 0xac build/stm32f7xx_ll_spi.o + .text.LL_I2S_StructInit + 0x00000000 0x12 build/stm32f7xx_ll_spi.o + .text.LL_I2S_ConfigPrescaler + 0x00000000 0x10 build/stm32f7xx_ll_spi.o + .text 0x00000000 0x0 build/stm32f7xx_hal_tim.o + .data 0x00000000 0x0 build/stm32f7xx_hal_tim.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_tim.o + .text.TIM_TI2_SetConfig + 0x00000000 0x36 build/stm32f7xx_hal_tim.o + .text.TIM_TI3_SetConfig + 0x00000000 0x36 build/stm32f7xx_hal_tim.o + .text.TIM_TI4_SetConfig + 0x00000000 0x36 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_Base_MspInit + 0x00000000 0x2 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_Base_MspDeInit + 0x00000000 0x2 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_Base_DeInit + 0x00000000 0x66 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_Base_Start + 0x00000000 0x88 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_Base_Start_DMA + 0x00000000 0xdc build/stm32f7xx_hal_tim.o + .text.HAL_TIM_Base_Stop_DMA + 0x00000000 0x3c build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_MspInit + 0x00000000 0x2 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_MspDeInit + 0x00000000 0x2 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_DeInit + 0x00000000 0x66 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_PWM_MspDeInit + 0x00000000 0x2 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_PWM_DeInit + 0x00000000 0x66 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_MspInit + 0x00000000 0x2 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_MspDeInit + 0x00000000 0x2 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_DeInit + 0x00000000 0x66 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_MspInit + 0x00000000 0x2 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_MspDeInit + 0x00000000 0x2 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_DeInit + 0x00000000 0x4e build/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_MspInit + 0x00000000 0x2 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_MspDeInit + 0x00000000 0x2 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_DeInit + 0x00000000 0x4e build/stm32f7xx_hal_tim.o + .text.HAL_TIM_DMABurst_MultiWriteStart + 0x00000000 0x1b4 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_DMABurst_WriteStart + 0x00000000 0x16 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_DMABurst_WriteStop + 0x00000000 0x84 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_DMABurst_MultiReadStart + 0x00000000 0x1b4 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_DMABurst_ReadStart + 0x00000000 0x16 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_DMABurst_ReadStop + 0x00000000 0x84 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_GenerateEvent + 0x00000000 0x2a build/stm32f7xx_hal_tim.o + .text.HAL_TIM_ConfigTI1Input + 0x00000000 0x10 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_ReadCapturedValue + 0x00000000 0x32 build/stm32f7xx_hal_tim.o + .text.TIM_DMAPeriodElapsedCplt + 0x00000000 0x16 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_PeriodElapsedHalfCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_tim.o + .text.TIM_DMAPeriodElapsedHalfCplt + 0x00000000 0xa build/stm32f7xx_hal_tim.o + .text.TIM_DMACaptureCplt + 0x00000000 0x80 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_CaptureHalfCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_tim.o + .text.TIM_DMACaptureHalfCplt + 0x00000000 0x3e build/stm32f7xx_hal_tim.o + .text.TIM_DMADelayPulseCplt + 0x00000000 0x70 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_tim.o + .text.TIM_DMADelayPulseHalfCplt + 0x00000000 0x3e build/stm32f7xx_hal_tim.o + .text.TIM_DMATriggerCplt + 0x00000000 0x16 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_TriggerHalfCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_tim.o + .text.TIM_DMATriggerHalfCplt + 0x00000000 0xa build/stm32f7xx_hal_tim.o + .text.HAL_TIM_ErrorCallback + 0x00000000 0x2 build/stm32f7xx_hal_tim.o + .text.TIM_DMAError + 0x00000000 0x5c build/stm32f7xx_hal_tim.o + .text.HAL_TIM_Base_GetState + 0x00000000 0x6 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_GetState + 0x00000000 0x6 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_PWM_GetState + 0x00000000 0x6 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_GetState + 0x00000000 0x6 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_GetState + 0x00000000 0x6 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_GetState + 0x00000000 0x6 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_GetActiveChannel + 0x00000000 0x4 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_GetChannelState + 0x00000000 0x4a build/stm32f7xx_hal_tim.o + .text.HAL_TIM_DMABurstState + 0x00000000 0x6 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_Init + 0x00000000 0x60 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_Init + 0x00000000 0x60 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_Init + 0x00000000 0x5c build/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_Init + 0x00000000 0xb0 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_ConfigChannel + 0x00000000 0x7a build/stm32f7xx_hal_tim.o + .text.TIM_TI1_SetConfig + 0x00000000 0x94 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_ConfigChannel + 0x00000000 0xcc build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_ConfigChannel + 0x00000000 0x100 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_ConfigOCrefClear + 0x00000000 0x144 build/stm32f7xx_hal_tim.o + .text.TIM_SlaveTimer_SetConfig + 0x00000000 0xbc build/stm32f7xx_hal_tim.o + .text.HAL_TIM_SlaveConfigSynchro + 0x00000000 0x52 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_SlaveConfigSynchro_IT + 0x00000000 0x52 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_Start + 0x00000000 0x158 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_Stop + 0x00000000 0xac build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_Start_IT + 0x00000000 0x1c4 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_Stop_IT + 0x00000000 0x100 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_Start_DMA + 0x00000000 0x31c build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OC_Stop_DMA + 0x00000000 0x118 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_PWM_Start_IT + 0x00000000 0x1c4 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_PWM_Stop_IT + 0x00000000 0x100 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_PWM_Start_DMA + 0x00000000 0x31c build/stm32f7xx_hal_tim.o + .text.HAL_TIM_PWM_Stop_DMA + 0x00000000 0x118 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_Start + 0x00000000 0x168 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_Stop + 0x00000000 0x9a build/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_Start_IT + 0x00000000 0x1ac build/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_Stop_IT + 0x00000000 0xea build/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_Start_DMA + 0x00000000 0x27c build/stm32f7xx_hal_tim.o + .text.HAL_TIM_IC_Stop_DMA + 0x00000000 0x100 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_Start + 0x00000000 0x84 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_Stop + 0x00000000 0x80 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_Start_IT + 0x00000000 0x98 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_OnePulse_Stop_IT + 0x00000000 0x94 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_Start + 0x00000000 0xc8 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_Stop + 0x00000000 0xe6 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_Start_IT + 0x00000000 0xf4 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_Stop_IT + 0x00000000 0x110 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_Start_DMA + 0x00000000 0x24c build/stm32f7xx_hal_tim.o + .text.HAL_TIM_Encoder_Stop_DMA + 0x00000000 0x128 build/stm32f7xx_hal_tim.o + .text 0x00000000 0x0 build/stm32f7xx_hal_tim_ex.o + .data 0x00000000 0x0 build/stm32f7xx_hal_tim_ex.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_tim_ex.o + .text.TIM_CCxNChannelCmd + 0x00000000 0x1e build/stm32f7xx_hal_tim_ex.o + .text.TIM_DMAErrorCCxN + 0x00000000 0x44 build/stm32f7xx_hal_tim_ex.o + .text.TIM_DMADelayPulseNCplt + 0x00000000 0x58 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_MspInit + 0x00000000 0x2 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Init + 0x00000000 0xd8 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_MspDeInit + 0x00000000 0x2 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_DeInit + 0x00000000 0x4e build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Start + 0x00000000 0xc8 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Stop + 0x00000000 0x42 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Start_IT + 0x00000000 0xd4 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Stop_IT + 0x00000000 0x4c build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Start_DMA + 0x00000000 0xfc build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Stop_DMA + 0x00000000 0x4a build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OCN_Start + 0x00000000 0x100 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OCN_Stop + 0x00000000 0x76 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OCN_Start_IT + 0x00000000 0x138 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OCN_Stop_IT + 0x00000000 0xc4 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OCN_Start_DMA + 0x00000000 0x22c build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OCN_Stop_DMA + 0x00000000 0xc2 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_PWMN_Start + 0x00000000 0x100 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_PWMN_Stop + 0x00000000 0x76 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_PWMN_Start_IT + 0x00000000 0x138 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_PWMN_Stop_IT + 0x00000000 0xc4 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_PWMN_Start_DMA + 0x00000000 0x22c build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_PWMN_Stop_DMA + 0x00000000 0xc2 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OnePulseN_Start + 0x00000000 0x7a build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OnePulseN_Stop + 0x00000000 0x72 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OnePulseN_Start_IT + 0x00000000 0x90 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_OnePulseN_Stop_IT + 0x00000000 0x86 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_ConfigCommutEvent + 0x00000000 0x76 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_ConfigCommutEvent_IT + 0x00000000 0x76 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_ConfigCommutEvent_DMA + 0x00000000 0x94 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_ConfigBreakDeadTime + 0x00000000 0x90 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_ConfigBreakInput + 0x00000000 0xa4 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_RemapConfig + 0x00000000 0x24 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_GroupChannel5 + 0x00000000 0x3e build/stm32f7xx_hal_tim_ex.o + .text.TIMEx_DMACommutationCplt + 0x00000000 0x10 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_CommutHalfCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_tim_ex.o + .text.TIMEx_DMACommutationHalfCplt + 0x00000000 0x10 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_GetState + 0x00000000 0x6 build/stm32f7xx_hal_tim_ex.o + .text.HAL_TIMEx_GetChannelNState + 0x00000000 0x2a build/stm32f7xx_hal_tim_ex.o + .text 0x00000000 0x0 build/stm32f7xx_ll_tim.o + .data 0x00000000 0x0 build/stm32f7xx_ll_tim.o + .bss 0x00000000 0x0 build/stm32f7xx_ll_tim.o + .text.OC1Config + 0x00000000 0x78 build/stm32f7xx_ll_tim.o + .text.OC2Config + 0x00000000 0x80 build/stm32f7xx_ll_tim.o + .text.OC3Config + 0x00000000 0x7c build/stm32f7xx_ll_tim.o + .text.OC4Config + 0x00000000 0x60 build/stm32f7xx_ll_tim.o + .text.OC5Config + 0x00000000 0x60 build/stm32f7xx_ll_tim.o + .text.OC6Config + 0x00000000 0x60 build/stm32f7xx_ll_tim.o + .text.IC1Config + 0x00000000 0x38 build/stm32f7xx_ll_tim.o + .text.IC2Config + 0x00000000 0x3a build/stm32f7xx_ll_tim.o + .text.IC3Config + 0x00000000 0x3a build/stm32f7xx_ll_tim.o + .text.IC4Config + 0x00000000 0x3a build/stm32f7xx_ll_tim.o + .text.LL_TIM_DeInit + 0x00000000 0x1e8 build/stm32f7xx_ll_tim.o + .text.LL_TIM_StructInit + 0x00000000 0x12 build/stm32f7xx_ll_tim.o + .text.LL_TIM_OC_StructInit + 0x00000000 0x14 build/stm32f7xx_ll_tim.o + .text.LL_TIM_OC_Init + 0x00000000 0x54 build/stm32f7xx_ll_tim.o + .text.LL_TIM_IC_StructInit + 0x00000000 0x10 build/stm32f7xx_ll_tim.o + .text.LL_TIM_IC_Init + 0x00000000 0x3c build/stm32f7xx_ll_tim.o + .text.LL_TIM_ENCODER_StructInit + 0x00000000 0x1c build/stm32f7xx_ll_tim.o + .text.LL_TIM_ENCODER_Init + 0x00000000 0x60 build/stm32f7xx_ll_tim.o + .text.LL_TIM_HALLSENSOR_StructInit + 0x00000000 0xc build/stm32f7xx_ll_tim.o + .text.LL_TIM_HALLSENSOR_Init + 0x00000000 0x60 build/stm32f7xx_ll_tim.o + .text.LL_TIM_BDTR_StructInit + 0x00000000 0x1a build/stm32f7xx_ll_tim.o + .text.LL_TIM_BDTR_Init + 0x00000000 0x70 build/stm32f7xx_ll_tim.o + .text 0x00000000 0x0 build/stm32f7xx_ll_usart.o + .data 0x00000000 0x0 build/stm32f7xx_ll_usart.o + .bss 0x00000000 0x0 build/stm32f7xx_ll_usart.o + .text.LL_USART_DeInit + 0x00000000 0x114 build/stm32f7xx_ll_usart.o + .text.LL_USART_StructInit + 0x00000000 0x18 build/stm32f7xx_ll_usart.o + .text.LL_USART_ClockInit + 0x00000000 0x3e build/stm32f7xx_ll_usart.o + .text.LL_USART_ClockStructInit + 0x00000000 0xc build/stm32f7xx_ll_usart.o + .text 0x00000000 0x0 build/system_stm32f7xx.o + .data 0x00000000 0x0 build/system_stm32f7xx.o + .bss 0x00000000 0x0 build/system_stm32f7xx.o + .text.SystemCoreClockUpdate + 0x00000000 0xa0 build/system_stm32f7xx.o + .text 0x00000000 0x0 build/File_Handling.o + .data 0x00000000 0x0 build/File_Handling.o + .bss 0x00000000 0x0 build/File_Handling.o + .text.Send_Uart + 0x00000000 0x2 build/File_Handling.o + .rodata.Scan_SD.str1.4 + 0x00000000 0x29 build/File_Handling.o + .text.Scan_SD 0x00000000 0xd4 build/File_Handling.o + .rodata.Format_SD.str1.4 + 0x00000000 0x2 build/File_Handling.o + .text.Format_SD + 0x00000000 0x8c build/File_Handling.o + .text.Write_File + 0x00000000 0x60 build/File_Handling.o + .text.Read_File + 0x00000000 0x108 build/File_Handling.o + .text.Update_File + 0x00000000 0x60 build/File_Handling.o + .rodata.Create_Dir.str1.4 + 0x00000000 0x4e build/File_Handling.o + .text.Create_Dir + 0x00000000 0x54 build/File_Handling.o + .rodata.Check_SD_Space.str1.4 + 0x00000000 0x3a build/File_Handling.o + .text.Check_SD_Space + 0x00000000 0xb0 build/File_Handling.o + .text.Update_File_float + 0x00000000 0x5c build/File_Handling.o + .bss.free_space + 0x00000000 0x4 build/File_Handling.o + .bss.total 0x00000000 0x4 build/File_Handling.o + .bss.fre_clust + 0x00000000 0x4 build/File_Handling.o + .bss.pfs 0x00000000 0x4 build/File_Handling.o + .text 0x00000000 0x0 build/diskio.o + .data 0x00000000 0x0 build/diskio.o + .bss 0x00000000 0x0 build/diskio.o + .text.get_fattime + 0x00000000 0x4 build/diskio.o + .text 0x00000000 0x0 build/ff.o + .data 0x00000000 0x0 build/ff.o + .bss 0x00000000 0x0 build/ff.o + .text.putc_init + 0x00000000 0xa build/ff.o + .text.putc_bfd + 0x00000000 0x4e build/ff.o + .text.putc_flush + 0x00000000 0x3a build/ff.o + .text.f_opendir + 0x00000000 0x8e build/ff.o + .text.f_closedir + 0x00000000 0x24 build/ff.o + .text.f_readdir + 0x00000000 0x4e build/ff.o + .text.f_getfree + 0x00000000 0xde build/ff.o + .text.f_truncate + 0x00000000 0xac build/ff.o + .text.f_mkdir 0x00000000 0x162 build/ff.o + .text.f_rename + 0x00000000 0x126 build/ff.o + .rodata.f_mkfs.str1.4 + 0x00000000 0x34 build/ff.o + .text.f_mkfs 0x00000000 0x690 build/ff.o + .text.f_gets 0x00000000 0x56 build/ff.o + .text.f_putc 0x00000000 0x1e build/ff.o + .text.f_puts 0x00000000 0x26 build/ff.o + .text.f_printf + 0x00000000 0x244 build/ff.o + .rodata.cst.0 0x00000000 0xe build/ff.o + .rodata.cst32.1 + 0x00000000 0xe build/ff.o + .text 0x00000000 0x0 build/ff_gen_drv.o + .data 0x00000000 0x0 build/ff_gen_drv.o + .bss 0x00000000 0x0 build/ff_gen_drv.o + .text.FATFS_UnLinkDriverEx + 0x00000000 0x3c build/ff_gen_drv.o + .text.FATFS_UnLinkDriver + 0x00000000 0xa build/ff_gen_drv.o + .text.FATFS_GetAttachedDriversNbr + 0x00000000 0xc build/ff_gen_drv.o + .text 0x00000000 0x0 build/syscall.o + .data 0x00000000 0x0 build/syscall.o + .bss 0x00000000 0x0 build/syscall.o + .debug_info 0x00000000 0x15d build/syscall.o + .debug_abbrev 0x00000000 0x5f build/syscall.o + .debug_aranges + 0x00000000 0x18 build/syscall.o + .debug_line 0x00000000 0xec build/syscall.o + .debug_str 0x00000000 0x242 build/syscall.o + .comment 0x00000000 0x27 build/syscall.o + .ARM.attributes + 0x00000000 0x32 build/syscall.o + .text 0x00000000 0x0 build/sysmem.o + .data 0x00000000 0x0 build/sysmem.o + .bss 0x00000000 0x0 build/sysmem.o + .text 0x00000000 0x0 build/syscalls.o + .data 0x00000000 0x0 build/syscalls.o + .bss 0x00000000 0x0 build/syscalls.o + .text.initialise_monitor_handles + 0x00000000 0x2 build/syscalls.o + .text._getpid 0x00000000 0x4 build/syscalls.o + .text._kill 0x00000000 0x10 build/syscalls.o + .text._exit 0x00000000 0xc build/syscalls.o + .text._read 0x00000000 0x20 build/syscalls.o + .text._write 0x00000000 0x1c build/syscalls.o + .text._close 0x00000000 0x6 build/syscalls.o + .text._fstat 0x00000000 0xa build/syscalls.o + .text._isatty 0x00000000 0x4 build/syscalls.o + .text._lseek 0x00000000 0x4 build/syscalls.o + .text._open 0x00000000 0xa build/syscalls.o + .text._wait 0x00000000 0x10 build/syscalls.o + .text._unlink 0x00000000 0x10 build/syscalls.o + .text._times 0x00000000 0x6 build/syscalls.o + .text._stat 0x00000000 0xa build/syscalls.o + .text._link 0x00000000 0x10 build/syscalls.o + .text._fork 0x00000000 0x10 build/syscalls.o + .text._execve 0x00000000 0x10 build/syscalls.o + .data.environ 0x00000000 0x4 build/syscalls.o + .bss.__env 0x00000000 0x4 build/syscalls.o + .debug_info 0x00000000 0x848 build/syscalls.o + .debug_abbrev 0x00000000 0x1e3 build/syscalls.o + .debug_loc 0x00000000 0x583 build/syscalls.o + .debug_aranges + 0x00000000 0xa8 build/syscalls.o + .debug_ranges 0x00000000 0x98 build/syscalls.o + .debug_line 0x00000000 0x36d build/syscalls.o + .debug_str 0x00000000 0x3fc build/syscalls.o + .comment 0x00000000 0x27 build/syscalls.o + .debug_frame 0x00000000 0x190 build/syscalls.o + .ARM.attributes + 0x00000000 0x32 build/syscalls.o + .text 0x00000000 0x0 build/stm32f7xx_hal_uart.o + .data 0x00000000 0x0 build/stm32f7xx_hal_uart.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_uart.o + .text.UART_EndTxTransfer + 0x00000000 0x18 build/stm32f7xx_hal_uart.o + .text.UART_TxISR_8BIT + 0x00000000 0x54 build/stm32f7xx_hal_uart.o + .text.UART_TxISR_16BIT + 0x00000000 0x58 build/stm32f7xx_hal_uart.o + .text.HAL_UART_MspInit + 0x00000000 0x2 build/stm32f7xx_hal_uart.o + .text.HAL_UART_MspDeInit + 0x00000000 0x2 build/stm32f7xx_hal_uart.o + .text.HAL_UART_DeInit + 0x00000000 0x40 build/stm32f7xx_hal_uart.o + .text.HAL_UART_Transmit_IT + 0x00000000 0x64 build/stm32f7xx_hal_uart.o + .text.HAL_UART_Transmit_DMA + 0x00000000 0x94 build/stm32f7xx_hal_uart.o + .text.HAL_UART_DMAPause + 0x00000000 0x8a build/stm32f7xx_hal_uart.o + .text.HAL_UART_DMAResume + 0x00000000 0x7a build/stm32f7xx_hal_uart.o + .text.HAL_UART_DMAStop + 0x00000000 0xac build/stm32f7xx_hal_uart.o + .text.HAL_UART_Abort + 0x00000000 0x100 build/stm32f7xx_hal_uart.o + .text.HAL_UART_AbortTransmit + 0x00000000 0x68 build/stm32f7xx_hal_uart.o + .text.HAL_UART_AbortReceive + 0x00000000 0xae build/stm32f7xx_hal_uart.o + .text.HAL_UART_TxCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_uart.o + .text.UART_DMATransmitCplt + 0x00000000 0x46 build/stm32f7xx_hal_uart.o + .text.UART_EndTransmit_IT + 0x00000000 0x22 build/stm32f7xx_hal_uart.o + .text.HAL_UART_TxHalfCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_uart.o + .text.UART_DMATxHalfCplt + 0x00000000 0xa build/stm32f7xx_hal_uart.o + .text.HAL_UART_RxCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_uart.o + .text.HAL_UART_RxHalfCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_uart.o + .text.HAL_UART_ErrorCallback + 0x00000000 0x2 build/stm32f7xx_hal_uart.o + .text.UART_DMAError + 0x00000000 0x56 build/stm32f7xx_hal_uart.o + .text.UART_DMAAbortOnError + 0x00000000 0x14 build/stm32f7xx_hal_uart.o + .text.HAL_UART_AbortCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_uart.o + .text.HAL_UART_Abort_IT + 0x00000000 0x130 build/stm32f7xx_hal_uart.o + .text.UART_DMARxAbortCallback + 0x00000000 0x40 build/stm32f7xx_hal_uart.o + .text.UART_DMATxAbortCallback + 0x00000000 0x36 build/stm32f7xx_hal_uart.o + .text.HAL_UART_AbortTransmitCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_uart.o + .text.HAL_UART_AbortTransmit_IT + 0x00000000 0x80 build/stm32f7xx_hal_uart.o + .text.UART_DMATxOnlyAbortCallback + 0x00000000 0x14 build/stm32f7xx_hal_uart.o + .text.HAL_UART_AbortReceiveCpltCallback + 0x00000000 0x2 build/stm32f7xx_hal_uart.o + .text.HAL_UART_AbortReceive_IT + 0x00000000 0xcc build/stm32f7xx_hal_uart.o + .text.UART_DMARxOnlyAbortCallback + 0x00000000 0x28 build/stm32f7xx_hal_uart.o + .text.HAL_UARTEx_RxEventCallback + 0x00000000 0x2 build/stm32f7xx_hal_uart.o + .text.UART_RxISR_8BIT + 0x00000000 0xd0 build/stm32f7xx_hal_uart.o + .text.UART_RxISR_16BIT + 0x00000000 0xce build/stm32f7xx_hal_uart.o + .text.UART_DMARxHalfCplt + 0x00000000 0x20 build/stm32f7xx_hal_uart.o + .text.UART_DMAReceiveCplt + 0x00000000 0x90 build/stm32f7xx_hal_uart.o + .text.HAL_UARTEx_WakeupCallback + 0x00000000 0x2 build/stm32f7xx_hal_uart.o + .text.HAL_UART_IRQHandler + 0x00000000 0x2e8 build/stm32f7xx_hal_uart.o + .text.HAL_UART_ReceiverTimeout_Config + 0x00000000 0xe build/stm32f7xx_hal_uart.o + .text.HAL_UART_EnableReceiverTimeout + 0x00000000 0x38 build/stm32f7xx_hal_uart.o + .text.HAL_UART_DisableReceiverTimeout + 0x00000000 0x38 build/stm32f7xx_hal_uart.o + .text.HAL_MultiProcessor_EnterMuteMode + 0x00000000 0xc build/stm32f7xx_hal_uart.o + .text.HAL_HalfDuplex_EnableTransmitter + 0x00000000 0x48 build/stm32f7xx_hal_uart.o + .text.HAL_HalfDuplex_EnableReceiver + 0x00000000 0x48 build/stm32f7xx_hal_uart.o + .text.HAL_LIN_SendBreak + 0x00000000 0x2e build/stm32f7xx_hal_uart.o + .text.HAL_UART_GetState + 0x00000000 0xa build/stm32f7xx_hal_uart.o + .text.HAL_UART_GetError + 0x00000000 0x6 build/stm32f7xx_hal_uart.o + .text.HAL_UART_Transmit + 0x00000000 0xc6 build/stm32f7xx_hal_uart.o + .text.HAL_UART_Receive + 0x00000000 0x116 build/stm32f7xx_hal_uart.o + .text.HAL_HalfDuplex_Init + 0x00000000 0x6e build/stm32f7xx_hal_uart.o + .text.HAL_LIN_Init + 0x00000000 0x92 build/stm32f7xx_hal_uart.o + .text.HAL_MultiProcessor_Init + 0x00000000 0x8a build/stm32f7xx_hal_uart.o + .text.HAL_MultiProcessor_EnableMuteMode + 0x00000000 0x34 build/stm32f7xx_hal_uart.o + .text.HAL_MultiProcessor_DisableMuteMode + 0x00000000 0x34 build/stm32f7xx_hal_uart.o + .text.UART_Start_Receive_IT + 0x00000000 0xd4 build/stm32f7xx_hal_uart.o + .text.HAL_UART_Receive_IT + 0x00000000 0x40 build/stm32f7xx_hal_uart.o + .text.UART_Start_Receive_DMA + 0x00000000 0xa8 build/stm32f7xx_hal_uart.o + .text.HAL_UART_Receive_DMA + 0x00000000 0x40 build/stm32f7xx_hal_uart.o + .text 0x00000000 0x0 build/stm32f7xx_hal_uart_ex.o + .data 0x00000000 0x0 build/stm32f7xx_hal_uart_ex.o + .bss 0x00000000 0x0 build/stm32f7xx_hal_uart_ex.o + .text.UARTEx_Wakeup_AddressConfig + 0x00000000 0x2e build/stm32f7xx_hal_uart_ex.o + .text.HAL_RS485Ex_Init + 0x00000000 0x7e build/stm32f7xx_hal_uart_ex.o + .text.HAL_UARTEx_EnableClockStopMode + 0x00000000 0x34 build/stm32f7xx_hal_uart_ex.o + .text.HAL_UARTEx_DisableClockStopMode + 0x00000000 0x34 build/stm32f7xx_hal_uart_ex.o + .text.HAL_MultiProcessorEx_AddressLength_Set + 0x00000000 0x36 build/stm32f7xx_hal_uart_ex.o + .text.HAL_UARTEx_StopModeWakeUpSourceConfig + 0x00000000 0x7e build/stm32f7xx_hal_uart_ex.o + .text.HAL_UARTEx_EnableStopMode + 0x00000000 0x2e build/stm32f7xx_hal_uart_ex.o + .text.HAL_UARTEx_DisableStopMode + 0x00000000 0x2e build/stm32f7xx_hal_uart_ex.o + .text.HAL_UARTEx_ReceiveToIdle + 0x00000000 0x15e build/stm32f7xx_hal_uart_ex.o + .text.HAL_UARTEx_ReceiveToIdle_IT + 0x00000000 0x4e build/stm32f7xx_hal_uart_ex.o + .text.HAL_UARTEx_ReceiveToIdle_DMA + 0x00000000 0x50 build/stm32f7xx_hal_uart_ex.o + .text.HAL_UARTEx_GetRxEventType + 0x00000000 0x4 build/stm32f7xx_hal_uart_ex.o + .debug_info 0x00000000 0x119b build/stm32f7xx_hal_uart_ex.o + .debug_abbrev 0x00000000 0x301 build/stm32f7xx_hal_uart_ex.o + .debug_loc 0x00000000 0xd8a build/stm32f7xx_hal_uart_ex.o + .debug_aranges + 0x00000000 0x78 build/stm32f7xx_hal_uart_ex.o + .debug_ranges 0x00000000 0x80 build/stm32f7xx_hal_uart_ex.o + .debug_line 0x00000000 0x8e1 build/stm32f7xx_hal_uart_ex.o + .debug_str 0x00000000 0x970 build/stm32f7xx_hal_uart_ex.o + .comment 0x00000000 0x27 build/stm32f7xx_hal_uart_ex.o + .debug_frame 0x00000000 0x138 build/stm32f7xx_hal_uart_ex.o + .ARM.attributes + 0x00000000 0x32 build/stm32f7xx_hal_uart_ex.o + .text 0x00000000 0x14 build/startup_stm32f767xx.o + .data 0x00000000 0x0 build/startup_stm32f767xx.o + .bss 0x00000000 0x0 build/startup_stm32f767xx.o + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) + .text 0x00000000 0xbc /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcpy.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcpy.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcpy.o) + .debug_info 0x00000000 0xc3 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcpy.o) + .debug_abbrev 0x00000000 0x7b /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcpy.o) + .debug_loclists + 0x00000000 0x2c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcpy.o) + .debug_aranges + 0x00000000 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcpy.o) + .debug_rnglists + 0x00000000 0x14 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcpy.o) + .debug_line 0x00000000 0xb9 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcpy.o) + .debug_str 0x00000000 0x19a /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcpy.o) + .comment 0x00000000 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcpy.o) + .debug_frame 0x00000000 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcpy.o) + .ARM.attributes + 0x00000000 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcpy.o) + .text 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-impure.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-impure.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + .text 0x00000000 0xd8 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strlen.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strlen.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strlen.o) + .ARM.extab 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strlen.o) + .ARM.exidx 0x00000000 0x8 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strlen.o) + .debug_line 0x00000000 0x86 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strlen.o) + .debug_line_str + 0x00000000 0x98 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strlen.o) + .debug_info 0x00000000 0x33 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strlen.o) + .debug_abbrev 0x00000000 0x28 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strlen.o) + .debug_aranges + 0x00000000 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strlen.o) + .debug_str 0x00000000 0xab /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strlen.o) + .eh_frame 0x00000000 0x34 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strlen.o) + .ARM.attributes + 0x00000000 0x1c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strlen.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-errno.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-errno.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-freer.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-freer.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memmove.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memmove.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memchr.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memchr.o) + .ARM.extab 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memchr.o) + .eh_frame 0x00000000 0x50 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memchr.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy.o) + .ARM.extab 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy.o) + .eh_frame 0x00000000 0x2c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-malloc.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-malloc.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reallocr.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reallocr.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-vfprintf_i.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-vfprintf_i.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mlock.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mlock.o) + .text 0x00000000 0x2e0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcmp.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcmp.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcmp.o) + .ARM.extab 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcmp.o) + .ARM.exidx 0x00000000 0x8 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcmp.o) + .debug_line 0x00000000 0x10e /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcmp.o) + .debug_line_str + 0x00000000 0x98 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcmp.o) + .debug_info 0x00000000 0x33 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcmp.o) + .debug_abbrev 0x00000000 0x28 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcmp.o) + .debug_aranges + 0x00000000 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcmp.o) + .debug_str 0x00000000 0xab /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcmp.o) + .debug_frame 0x00000000 0x7c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcmp.o) + .ARM.attributes + 0x00000000 0x1e /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcmp.o) + .text 0x00000000 0x24 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-exit.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-exit.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-exit.o) + .debug_info 0x00000000 0x11b /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-exit.o) + .debug_abbrev 0x00000000 0xd8 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-exit.o) + .debug_loclists + 0x00000000 0x1b /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-exit.o) + .debug_aranges + 0x00000000 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-exit.o) + .debug_line 0x00000000 0x12d /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-exit.o) + .debug_str 0x00000000 0x1c2 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-exit.o) + .comment 0x00000000 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-exit.o) + .debug_frame 0x00000000 0x28 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-exit.o) + .ARM.attributes + 0x00000000 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-exit.o) + .text 0x00000000 0xc /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-atexit.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-atexit.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-atexit.o) + .debug_info 0x00000000 0x11e /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-atexit.o) + .debug_abbrev 0x00000000 0xc1 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-atexit.o) + .debug_loclists + 0x00000000 0x2b /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-atexit.o) + .debug_aranges + 0x00000000 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-atexit.o) + .debug_line 0x00000000 0xc3 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-atexit.o) + .debug_str 0x00000000 0x1d9 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-atexit.o) + .comment 0x00000000 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-atexit.o) + .debug_frame 0x00000000 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-atexit.o) + .ARM.attributes + 0x00000000 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-atexit.o) + .text 0x00000000 0x28 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fini.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fini.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fini.o) + .debug_info 0x00000000 0xf7 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fini.o) + .debug_abbrev 0x00000000 0xcc /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fini.o) + .debug_loclists + 0x00000000 0x42 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fini.o) + .debug_aranges + 0x00000000 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fini.o) + .debug_line 0x00000000 0xd2 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fini.o) + .debug_str 0x00000000 0x1d3 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fini.o) + .comment 0x00000000 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fini.o) + .debug_frame 0x00000000 0x34 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fini.o) + .ARM.attributes + 0x00000000 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fini.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sbrkr.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sbrkr.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-msizer.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-msizer.o) + .text 0x00000000 0x224 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + .data 0x00000000 0xc /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + .text 0x00000000 0x1a8 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) + .debug_info 0x00000000 0xa33 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) + .debug_abbrev 0x00000000 0x2e4 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) + .debug_loclists + 0x00000000 0x2f3 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) + .debug_aranges + 0x00000000 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) + .debug_rnglists + 0x00000000 0x59 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) + .debug_line 0x00000000 0x446 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) + .debug_str 0x00000000 0x546 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) + .comment 0x00000000 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) + .debug_frame 0x00000000 0x8c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) + .ARM.attributes + 0x00000000 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) + .text 0x00000000 0x44 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fwalk.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fwalk.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fwalk.o) + .debug_info 0x00000000 0x7c8 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fwalk.o) + .debug_abbrev 0x00000000 0x19b /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fwalk.o) + .debug_loclists + 0x00000000 0x87 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fwalk.o) + .debug_aranges + 0x00000000 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fwalk.o) + .debug_line 0x00000000 0x1d1 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fwalk.o) + .debug_str 0x00000000 0x4cf /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fwalk.o) + .comment 0x00000000 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fwalk.o) + .debug_frame 0x00000000 0x34 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fwalk.o) + .ARM.attributes + 0x00000000 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fwalk.o) + .text 0x00000000 0xac /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) + .data 0x00000000 0x4 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) + .bss 0x00000000 0x8c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) + .debug_info 0x00000000 0x284 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) + .debug_abbrev 0x00000000 0x1d4 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) + .debug_loclists + 0x00000000 0x127 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) + .debug_aranges + 0x00000000 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) + .debug_line 0x00000000 0x230 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) + .debug_str 0x00000000 0x293 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) + .comment 0x00000000 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) + .debug_frame 0x00000000 0x38 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) + .ARM.attributes + 0x00000000 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) + .text 0x00000000 0xd4 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reent.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reent.o) + .text 0x00000000 0x94 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) + .debug_info 0x00000000 0xa80 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) + .debug_abbrev 0x00000000 0x224 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) + .debug_loclists + 0x00000000 0x23b /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) + .debug_aranges + 0x00000000 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) + .debug_line 0x00000000 0x22b /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) + .debug_str 0x00000000 0x52c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) + .comment 0x00000000 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) + .debug_frame 0x00000000 0x8c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) + .ARM.attributes + 0x00000000 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) + .text 0x00000000 0x24 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-closer.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-closer.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-closer.o) + .debug_info 0x00000000 0x752 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-closer.o) + .debug_abbrev 0x00000000 0x1b0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-closer.o) + .debug_loclists + 0x00000000 0x4b /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-closer.o) + .debug_aranges + 0x00000000 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-closer.o) + .debug_line 0x00000000 0x193 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-closer.o) + .debug_str 0x00000000 0x4b5 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-closer.o) + .comment 0x00000000 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-closer.o) + .debug_frame 0x00000000 0x2c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-closer.o) + .ARM.attributes + 0x00000000 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-closer.o) + .text 0x00000000 0xc4 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__call_atexit.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__call_atexit.o) + .bss 0x00000000 0x4 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__call_atexit.o) + .debug_info 0x00000000 0x235 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__call_atexit.o) + .debug_abbrev 0x00000000 0x179 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__call_atexit.o) + .debug_loclists + 0x00000000 0xff /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__call_atexit.o) + .debug_aranges + 0x00000000 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__call_atexit.o) + .debug_rnglists + 0x00000000 0x2c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__call_atexit.o) + .debug_line 0x00000000 0x246 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__call_atexit.o) + .debug_str 0x00000000 0x245 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__call_atexit.o) + .comment 0x00000000 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__call_atexit.o) + .debug_frame 0x00000000 0x40 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__call_atexit.o) + .ARM.attributes + 0x00000000 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__call_atexit.o) + .text 0x00000000 0x2c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-readr.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-readr.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-readr.o) + .debug_info 0x00000000 0x7b5 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-readr.o) + .debug_abbrev 0x00000000 0x1b0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-readr.o) + .debug_loclists + 0x00000000 0x9e /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-readr.o) + .debug_aranges + 0x00000000 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-readr.o) + .debug_line 0x00000000 0x198 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-readr.o) + .debug_str 0x00000000 0x4c3 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-readr.o) + .comment 0x00000000 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-readr.o) + .debug_frame 0x00000000 0x2c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-readr.o) + .ARM.attributes + 0x00000000 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-readr.o) + .text 0x00000000 0x2c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-lseekr.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-lseekr.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-lseekr.o) + .debug_info 0x00000000 0x79e /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-lseekr.o) + .debug_abbrev 0x00000000 0x1c4 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-lseekr.o) + .debug_loclists + 0x00000000 0x9e /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-lseekr.o) + .debug_aranges + 0x00000000 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-lseekr.o) + .debug_line 0x00000000 0x199 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-lseekr.o) + .debug_str 0x00000000 0x4c3 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-lseekr.o) + .comment 0x00000000 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-lseekr.o) + .debug_frame 0x00000000 0x2c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-lseekr.o) + .ARM.attributes + 0x00000000 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-lseekr.o) + .text 0x00000000 0x2c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-writer.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-writer.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-writer.o) + .debug_info 0x00000000 0x7bb /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-writer.o) + .debug_abbrev 0x00000000 0x1b5 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-writer.o) + .debug_loclists + 0x00000000 0x9e /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-writer.o) + .debug_aranges + 0x00000000 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-writer.o) + .debug_line 0x00000000 0x199 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-writer.o) + .debug_str 0x00000000 0x4c5 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-writer.o) + .comment 0x00000000 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-writer.o) + .debug_frame 0x00000000 0x2c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-writer.o) + .ARM.attributes + 0x00000000 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-writer.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + .ARM.extab 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) + .text 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtend.o + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtend.o + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtend.o + .rodata 0x00000000 0x24 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtend.o + .eh_frame 0x00000000 0x4 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtend.o + .text 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtn.o + .data 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtn.o + .bss 0x00000000 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtn.o + +Memory Configuration + +Name Origin Length Attributes +RAM 0x20000000 0x00080000 xrw +FLASH 0x08000000 0x00200000 xr +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crti.o +LOAD /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o +LOAD /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +LOAD build/main.o +LOAD build/bsp_driver_sd.o +LOAD build/sd_diskio.o +LOAD build/fatfs.o +LOAD build/fatfs_platform.o +LOAD build/stm32f7xx_it.o +LOAD build/stm32f7xx_hal_msp.o +LOAD build/stm32f7xx_hal_adc.o +LOAD build/stm32f7xx_hal_adc_ex.o +LOAD build/stm32f7xx_hal_rcc.o +LOAD build/stm32f7xx_hal_rcc_ex.o +LOAD build/stm32f7xx_hal_flash.o +LOAD build/stm32f7xx_hal_flash_ex.o +LOAD build/stm32f7xx_hal_gpio.o +LOAD build/stm32f7xx_hal_dma.o +LOAD build/stm32f7xx_hal_dma_ex.o +LOAD build/stm32f7xx_hal_pwr.o +LOAD build/stm32f7xx_hal_pwr_ex.o +LOAD build/stm32f7xx_hal_cortex.o +LOAD build/stm32f7xx_hal.o +LOAD build/stm32f7xx_hal_i2c.o +LOAD build/stm32f7xx_hal_i2c_ex.o +LOAD build/stm32f7xx_hal_exti.o +LOAD build/stm32f7xx_ll_rcc.o +LOAD build/stm32f7xx_ll_utils.o +LOAD build/stm32f7xx_ll_exti.o +LOAD build/stm32f7xx_ll_gpio.o +LOAD build/stm32f7xx_ll_dma.o +LOAD build/stm32f7xx_ll_sdmmc.o +LOAD build/stm32f7xx_hal_sd.o +LOAD build/stm32f7xx_ll_spi.o +LOAD build/stm32f7xx_hal_tim.o +LOAD build/stm32f7xx_hal_tim_ex.o +LOAD build/stm32f7xx_ll_tim.o +LOAD build/stm32f7xx_ll_usart.o +LOAD build/system_stm32f7xx.o +LOAD build/File_Handling.o +LOAD build/diskio.o +LOAD build/ff.o +LOAD build/ff_gen_drv.o +LOAD build/syscall.o +LOAD build/sysmem.o +LOAD build/syscalls.o +LOAD build/stm32f7xx_hal_uart.o +LOAD build/stm32f7xx_hal_uart_ex.o +LOAD build/startup_stm32f767xx.o +LOAD /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a +LOAD /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libm.a +LOAD /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libnosys.a +START GROUP +LOAD /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a +LOAD /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a +END GROUP +START GROUP +LOAD /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a +LOAD /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a +END GROUP +LOAD /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtend.o +LOAD /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtn.o + 0x20080000 _estack = (ORIGIN (RAM) + LENGTH (RAM)) + 0x00002000 _Min_Heap_Size = 0x2000 + 0x00004000 _Min_Stack_Size = 0x4000 + +.isr_vector 0x08000000 0x1f8 + 0x08000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x08000000 0x1f8 build/startup_stm32f767xx.o + 0x08000000 g_pfnVectors + 0x080001f8 . = ALIGN (0x4) + +.text 0x08000200 0xa8b4 + 0x08000200 . = ALIGN (0x4) + *(.text) + .text 0x08000200 0x88 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o + .text 0x08000288 0x80 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) + 0x08000288 _siprintf_r + 0x08000288 _sprintf_r + 0x080002c4 sprintf + 0x080002c4 siprintf + .text 0x08000308 0x400 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) + 0x08000308 __ssputs_r + 0x080003c8 __ssprint_r + 0x080004d0 _svfprintf_r + 0x080004d0 _svfiprintf_r + .text 0x08000708 0x50 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + 0x08000708 __libc_init_array + .text 0x08000758 0xa4 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + 0x08000758 memset + .text 0x080007fc 0xc /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-errno.o) + 0x080007fc __errno + .text 0x08000808 0x148 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) + 0x08000850 _malloc_r + .text 0x08000950 0xbc /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-freer.o) + 0x08000950 _free_r + .text 0x08000a0c 0x100 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memmove.o) + 0x08000a0c memmove + *fill* 0x08000b0c 0x4 + .text 0x08000b10 0xa0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memchr.o) + 0x08000b10 memchr + .text 0x08000bb0 0x134 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy.o) + 0x08000bb0 memcpy + .text 0x08000ce4 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-malloc.o) + 0x08000ce4 malloc + 0x08000cf4 free + .text 0x08000d04 0x64 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reallocr.o) + 0x08000d04 _realloc_r + .text 0x08000d68 0x3a8 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-vfprintf_i.o) + 0x08000d68 _printf_common + 0x08000e8c _printf_i + .text 0x08001110 0x8 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mlock.o) + 0x08001110 __malloc_lock + 0x08001114 __malloc_unlock + .text 0x08001118 0x24 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sbrkr.o) + 0x08001118 _sbrk_r + .text 0x0800113c 0x10 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-msizer.o) + 0x0800113c _malloc_usable_size_r + .text 0x0800114c 0x30 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + 0x0800114c __aeabi_uldivmod + .text 0x0800117c 0x2bc /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + 0x0800117c __udivmoddi4 + .text 0x08001438 0x4 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) + 0x08001438 __aeabi_ldiv0 + 0x08001438 __aeabi_idiv0 + *(.text*) + .text.NVIC_EncodePriority + 0x0800143c 0x3e build/main.o + *fill* 0x0800147a 0x2 + .text.MX_SDMMC1_SD_Init + 0x0800147c 0x24 build/main.o + .text.MX_DMA_Init + 0x080014a0 0x48 build/main.o + .text.Decode_task + 0x080014e8 0x168 build/main.o + .text.PID_Controller_Temp + 0x08001650 0xe4 build/main.o + .text.OUT_trigger + 0x08001734 0x124 build/main.o + .text.MPhD_T 0x08001858 0x220 build/main.o + .text.Stop_TIM10 + 0x08001a78 0x20 build/main.o + .text.MX_GPIO_Init + 0x08001a98 0x248 build/main.o + .text.MX_SPI4_Init + 0x08001ce0 0xd4 build/main.o + .text.MX_SPI2_Init + 0x08001db4 0xd0 build/main.o + .text.MX_SPI5_Init + 0x08001e84 0xd0 build/main.o + .text.MX_SPI6_Init + 0x08001f54 0xd0 build/main.o + .text.MX_TIM2_Init + 0x08002024 0x9c build/main.o + .text.MX_TIM5_Init + 0x080020c0 0x98 build/main.o + .text.MX_TIM7_Init + 0x08002158 0x8c build/main.o + .text.MX_TIM6_Init + 0x080021e4 0x8c build/main.o + .text.Init_params + 0x08002270 0x30c build/main.o + .text.Get_ADC 0x0800257c 0x70 build/main.o + .text.Set_LTEC + 0x080025ec 0x158 build/main.o + 0x080025ec Set_LTEC + .text.Decode_uart + 0x08002744 0x2f8 build/main.o + .text.CalculateChecksum + 0x08002a3c 0x18 build/main.o + 0x08002a3c CalculateChecksum + .text.CheckChecksum + 0x08002a54 0x48 build/main.o + 0x08002a54 CheckChecksum + .text.SD_SAVE 0x08002a9c 0x3c build/main.o + 0x08002a9c SD_SAVE + .text.SD_READ 0x08002ad8 0x4c build/main.o + 0x08002ad8 SD_READ + .text.SD_REMOVE + 0x08002b24 0x40 build/main.o + 0x08002b24 SD_REMOVE + .text.USART_TX + 0x08002b64 0x2c build/main.o + 0x08002b64 USART_TX + .text.USART_TX_DMA + 0x08002b90 0x40 build/main.o + 0x08002b90 USART_TX_DMA + .text.Error_Handler + 0x08002bd0 0x4 build/main.o + 0x08002bd0 Error_Handler + .text.MX_ADC1_Init + 0x08002bd4 0xc8 build/main.o + .text.MX_ADC3_Init + 0x08002c9c 0x6c build/main.o + .text.MX_USART1_UART_Init + 0x08002d08 0x190 build/main.o + .text.MX_TIM10_Init + 0x08002e98 0x2c build/main.o + .text.MX_UART8_Init + 0x08002ec4 0x38 build/main.o + .text.MX_TIM8_Init + 0x08002efc 0x6c build/main.o + .text.MX_TIM11_Init + 0x08002f68 0x70 build/main.o + .text.MX_TIM4_Init + 0x08002fd8 0xa4 build/main.o + .text.SystemClock_Config + 0x0800307c 0xb4 build/main.o + 0x0800307c SystemClock_Config + .text.main 0x08003130 0xa2c build/main.o + 0x08003130 main + .text.BSP_SD_ReadBlocks + 0x08003b5c 0x20 build/bsp_driver_sd.o + 0x08003b5c BSP_SD_ReadBlocks + .text.BSP_SD_WriteBlocks + 0x08003b7c 0x20 build/bsp_driver_sd.o + 0x08003b7c BSP_SD_WriteBlocks + .text.BSP_SD_GetCardState + 0x08003b9c 0x14 build/bsp_driver_sd.o + 0x08003b9c BSP_SD_GetCardState + .text.BSP_SD_GetCardInfo + 0x08003bb0 0x10 build/bsp_driver_sd.o + 0x08003bb0 BSP_SD_GetCardInfo + .text.BSP_SD_IsDetected + 0x08003bc0 0x20 build/bsp_driver_sd.o + 0x08003bc0 BSP_SD_IsDetected + .text.BSP_SD_Init + 0x08003be0 0x34 build/bsp_driver_sd.o + 0x08003be0 BSP_SD_Init + .text.SD_CheckStatus + 0x08003c14 0x24 build/sd_diskio.o + .text.SD_initialize + 0x08003c38 0x28 build/sd_diskio.o + 0x08003c38 SD_initialize + .text.SD_status + 0x08003c60 0x8 build/sd_diskio.o + 0x08003c60 SD_status + .text.SD_read 0x08003c68 0x24 build/sd_diskio.o + 0x08003c68 SD_read + .text.SD_write + 0x08003c8c 0x24 build/sd_diskio.o + 0x08003c8c SD_write + .text.SD_ioctl + 0x08003cb0 0x58 build/sd_diskio.o + 0x08003cb0 SD_ioctl + .text.MX_FATFS_Init + 0x08003d08 0x1c build/fatfs.o + 0x08003d08 MX_FATFS_Init + .text.get_fattime + 0x08003d24 0x4 build/fatfs.o + 0x08003d24 get_fattime + .text.BSP_PlatformIsDetected + 0x08003d28 0x18 build/fatfs_platform.o + 0x08003d28 BSP_PlatformIsDetected + .text.NMI_Handler + 0x08003d40 0x2 build/stm32f7xx_it.o + 0x08003d40 NMI_Handler + .text.HardFault_Handler + 0x08003d42 0x2 build/stm32f7xx_it.o + 0x08003d42 HardFault_Handler + .text.MemManage_Handler + 0x08003d44 0x2 build/stm32f7xx_it.o + 0x08003d44 MemManage_Handler + .text.BusFault_Handler + 0x08003d46 0x2 build/stm32f7xx_it.o + 0x08003d46 BusFault_Handler + .text.UsageFault_Handler + 0x08003d48 0x2 build/stm32f7xx_it.o + 0x08003d48 UsageFault_Handler + .text.SVC_Handler + 0x08003d4a 0x2 build/stm32f7xx_it.o + 0x08003d4a SVC_Handler + .text.DebugMon_Handler + 0x08003d4c 0x2 build/stm32f7xx_it.o + 0x08003d4c DebugMon_Handler + .text.PendSV_Handler + 0x08003d4e 0x2 build/stm32f7xx_it.o + 0x08003d4e PendSV_Handler + .text.SysTick_Handler + 0x08003d50 0x8 build/stm32f7xx_it.o + 0x08003d50 SysTick_Handler + .text.ADC_IRQHandler + 0x08003d58 0x18 build/stm32f7xx_it.o + 0x08003d58 ADC_IRQHandler + .text.TIM1_UP_TIM10_IRQHandler + 0x08003d70 0x34 build/stm32f7xx_it.o + 0x08003d70 TIM1_UP_TIM10_IRQHandler + .text.TIM1_TRG_COM_TIM11_IRQHandler + 0x08003da4 0x34 build/stm32f7xx_it.o + 0x08003da4 TIM1_TRG_COM_TIM11_IRQHandler + .text.TIM2_IRQHandler + 0x08003dd8 0x2 build/stm32f7xx_it.o + 0x08003dd8 TIM2_IRQHandler + *fill* 0x08003dda 0x2 + .text.TIM8_UP_TIM13_IRQHandler + 0x08003ddc 0x50 build/stm32f7xx_it.o + 0x08003ddc TIM8_UP_TIM13_IRQHandler + .text.TIM5_IRQHandler + 0x08003e2c 0x2 build/stm32f7xx_it.o + 0x08003e2c TIM5_IRQHandler + *fill* 0x08003e2e 0x2 + .text.TIM6_DAC_IRQHandler + 0x08003e30 0x34 build/stm32f7xx_it.o + 0x08003e30 TIM6_DAC_IRQHandler + .text.TIM7_IRQHandler + 0x08003e64 0x24 build/stm32f7xx_it.o + 0x08003e64 TIM7_IRQHandler + .text.UART_RxCpltCallback + 0x08003e88 0x28c build/stm32f7xx_it.o + 0x08003e88 UART_RxCpltCallback + .text.USART1_IRQHandler + 0x08004114 0xd0 build/stm32f7xx_it.o + 0x08004114 USART1_IRQHandler + .text.DMA2_Stream7_TransferComplete + 0x080041e4 0x10 build/stm32f7xx_it.o + 0x080041e4 DMA2_Stream7_TransferComplete + .text.DMA2_Stream7_IRQHandler + 0x080041f4 0x34 build/stm32f7xx_it.o + 0x080041f4 DMA2_Stream7_IRQHandler + .text.HAL_MspInit + 0x08004228 0x30 build/stm32f7xx_hal_msp.o + 0x08004228 HAL_MspInit + .text.HAL_ADC_MspInit + 0x08004258 0x110 build/stm32f7xx_hal_msp.o + 0x08004258 HAL_ADC_MspInit + .text.HAL_SD_MspInit + 0x08004368 0xb8 build/stm32f7xx_hal_msp.o + 0x08004368 HAL_SD_MspInit + .text.HAL_TIM_Base_MspInit + 0x08004420 0xc0 build/stm32f7xx_hal_msp.o + 0x08004420 HAL_TIM_Base_MspInit + .text.HAL_TIM_MspPostInit + 0x080044e0 0x8c build/stm32f7xx_hal_msp.o + 0x080044e0 HAL_TIM_MspPostInit + .text.HAL_UART_MspInit + 0x0800456c 0x88 build/stm32f7xx_hal_msp.o + 0x0800456c HAL_UART_MspInit + .text.ADC_Init + 0x080045f4 0x134 build/stm32f7xx_hal_adc.o + .text.HAL_ADC_Init + 0x08004728 0x58 build/stm32f7xx_hal_adc.o + 0x08004728 HAL_ADC_Init + .text.HAL_ADC_Start + 0x08004780 0x134 build/stm32f7xx_hal_adc.o + 0x08004780 HAL_ADC_Start + .text.HAL_ADC_Stop + 0x080048b4 0x40 build/stm32f7xx_hal_adc.o + 0x080048b4 HAL_ADC_Stop + .text.HAL_ADC_PollForConversion + 0x080048f4 0xc2 build/stm32f7xx_hal_adc.o + 0x080048f4 HAL_ADC_PollForConversion + .text.HAL_ADC_GetValue + 0x080049b6 0x6 build/stm32f7xx_hal_adc.o + 0x080049b6 HAL_ADC_GetValue + .text.HAL_ADC_ConvCpltCallback + 0x080049bc 0x2 build/stm32f7xx_hal_adc.o + 0x080049bc HAL_ADC_ConvCpltCallback + .text.HAL_ADC_LevelOutOfWindowCallback + 0x080049be 0x2 build/stm32f7xx_hal_adc.o + 0x080049be HAL_ADC_LevelOutOfWindowCallback + .text.HAL_ADC_ErrorCallback + 0x080049c0 0x2 build/stm32f7xx_hal_adc.o + 0x080049c0 HAL_ADC_ErrorCallback + .text.HAL_ADC_IRQHandler + 0x080049c2 0x136 build/stm32f7xx_hal_adc.o + 0x080049c2 HAL_ADC_IRQHandler + .text.HAL_ADC_ConfigChannel + 0x08004af8 0x1e4 build/stm32f7xx_hal_adc.o + 0x08004af8 HAL_ADC_ConfigChannel + .text.HAL_ADCEx_InjectedConvCpltCallback + 0x08004cdc 0x2 build/stm32f7xx_hal_adc_ex.o + 0x08004cdc HAL_ADCEx_InjectedConvCpltCallback + *fill* 0x08004cde 0x2 + .text.HAL_RCC_OscConfig + 0x08004ce0 0x444 build/stm32f7xx_hal_rcc.o + 0x08004ce0 HAL_RCC_OscConfig + .text.HAL_RCC_GetSysClockFreq + 0x08005124 0xa8 build/stm32f7xx_hal_rcc.o + 0x08005124 HAL_RCC_GetSysClockFreq + .text.HAL_RCC_ClockConfig + 0x080051cc 0x16c build/stm32f7xx_hal_rcc.o + 0x080051cc HAL_RCC_ClockConfig + .text.HAL_RCC_GetHCLKFreq + 0x08005338 0xc build/stm32f7xx_hal_rcc.o + 0x08005338 HAL_RCC_GetHCLKFreq + .text.HAL_RCC_GetPCLK1Freq + 0x08005344 0x20 build/stm32f7xx_hal_rcc.o + 0x08005344 HAL_RCC_GetPCLK1Freq + .text.HAL_RCC_GetPCLK2Freq + 0x08005364 0x20 build/stm32f7xx_hal_rcc.o + 0x08005364 HAL_RCC_GetPCLK2Freq + .text.HAL_RCCEx_PeriphCLKConfig + 0x08005384 0x600 build/stm32f7xx_hal_rcc_ex.o + 0x08005384 HAL_RCCEx_PeriphCLKConfig + .text.HAL_GPIO_Init + 0x08005984 0x204 build/stm32f7xx_hal_gpio.o + 0x08005984 HAL_GPIO_Init + .text.HAL_GPIO_ReadPin + 0x08005b88 0xe build/stm32f7xx_hal_gpio.o + 0x08005b88 HAL_GPIO_ReadPin + .text.HAL_GPIO_WritePin + 0x08005b96 0xc build/stm32f7xx_hal_gpio.o + 0x08005b96 HAL_GPIO_WritePin + .text.HAL_GPIO_TogglePin + 0x08005ba2 0x12 build/stm32f7xx_hal_gpio.o + 0x08005ba2 HAL_GPIO_TogglePin + .text.HAL_PWREx_EnableOverDrive + 0x08005bb4 0x7c build/stm32f7xx_hal_pwr_ex.o + 0x08005bb4 HAL_PWREx_EnableOverDrive + .text.__NVIC_SetPriority + 0x08005c30 0x24 build/stm32f7xx_hal_cortex.o + .text.NVIC_EncodePriority + 0x08005c54 0x3e build/stm32f7xx_hal_cortex.o + *fill* 0x08005c92 0x2 + .text.HAL_NVIC_SetPriorityGrouping + 0x08005c94 0x24 build/stm32f7xx_hal_cortex.o + 0x08005c94 HAL_NVIC_SetPriorityGrouping + .text.HAL_NVIC_SetPriority + 0x08005cb8 0x20 build/stm32f7xx_hal_cortex.o + 0x08005cb8 HAL_NVIC_SetPriority + .text.HAL_NVIC_EnableIRQ + 0x08005cd8 0x1c build/stm32f7xx_hal_cortex.o + 0x08005cd8 HAL_NVIC_EnableIRQ + .text.HAL_SYSTICK_Config + 0x08005cf4 0x28 build/stm32f7xx_hal_cortex.o + 0x08005cf4 HAL_SYSTICK_Config + .text.HAL_InitTick + 0x08005d1c 0x4c build/stm32f7xx_hal.o + 0x08005d1c HAL_InitTick + .text.HAL_Init + 0x08005d68 0x16 build/stm32f7xx_hal.o + 0x08005d68 HAL_Init + *fill* 0x08005d7e 0x2 + .text.HAL_IncTick + 0x08005d80 0x18 build/stm32f7xx_hal.o + 0x08005d80 HAL_IncTick + .text.HAL_GetTick + 0x08005d98 0xc build/stm32f7xx_hal.o + 0x08005d98 HAL_GetTick + .text.HAL_Delay + 0x08005da4 0x28 build/stm32f7xx_hal.o + 0x08005da4 HAL_Delay + .text.RCC_GetHCLKClockFreq + 0x08005dcc 0x18 build/stm32f7xx_ll_rcc.o + 0x08005dcc RCC_GetHCLKClockFreq + .text.RCC_GetPCLK1ClockFreq + 0x08005de4 0x18 build/stm32f7xx_ll_rcc.o + 0x08005de4 RCC_GetPCLK1ClockFreq + .text.RCC_GetPCLK2ClockFreq + 0x08005dfc 0x18 build/stm32f7xx_ll_rcc.o + 0x08005dfc RCC_GetPCLK2ClockFreq + .text.RCC_PLL_GetFreqDomain_SYS + 0x08005e14 0x44 build/stm32f7xx_ll_rcc.o + 0x08005e14 RCC_PLL_GetFreqDomain_SYS + .text.RCC_GetSystemClockFreq + 0x08005e58 0x2c build/stm32f7xx_ll_rcc.o + 0x08005e58 RCC_GetSystemClockFreq + .text.LL_RCC_GetUSARTClockFreq + 0x08005e84 0x178 build/stm32f7xx_ll_rcc.o + 0x08005e84 LL_RCC_GetUSARTClockFreq + .text.LL_RCC_GetUARTClockFreq + 0x08005ffc 0x180 build/stm32f7xx_ll_rcc.o + 0x08005ffc LL_RCC_GetUARTClockFreq + .text.LL_GPIO_SetPinSpeed + 0x0800617c 0x30 build/stm32f7xx_ll_gpio.o + .text.LL_GPIO_SetPinPull + 0x080061ac 0x30 build/stm32f7xx_ll_gpio.o + .text.LL_GPIO_SetAFPin_0_7 + 0x080061dc 0x30 build/stm32f7xx_ll_gpio.o + .text.LL_GPIO_SetAFPin_8_15 + 0x0800620c 0x32 build/stm32f7xx_ll_gpio.o + .text.LL_GPIO_SetPinMode + 0x0800623e 0x30 build/stm32f7xx_ll_gpio.o + .text.LL_GPIO_Init + 0x0800626e 0x8a build/stm32f7xx_ll_gpio.o + 0x0800626e LL_GPIO_Init + .text.SDMMC_GetCmdError + 0x080062f8 0x38 build/stm32f7xx_ll_sdmmc.o + .text.SDMMC_Init + 0x08006330 0x34 build/stm32f7xx_ll_sdmmc.o + 0x08006330 SDMMC_Init + .text.SDMMC_ReadFIFO + 0x08006364 0x6 build/stm32f7xx_ll_sdmmc.o + 0x08006364 SDMMC_ReadFIFO + .text.SDMMC_WriteFIFO + 0x0800636a 0xa build/stm32f7xx_ll_sdmmc.o + 0x0800636a SDMMC_WriteFIFO + .text.SDMMC_PowerState_ON + 0x08006374 0x8 build/stm32f7xx_ll_sdmmc.o + 0x08006374 SDMMC_PowerState_ON + .text.SDMMC_GetPowerState + 0x0800637c 0x8 build/stm32f7xx_ll_sdmmc.o + 0x0800637c SDMMC_GetPowerState + .text.SDMMC_SendCommand + 0x08006384 0x20 build/stm32f7xx_ll_sdmmc.o + 0x08006384 SDMMC_SendCommand + .text.SDMMC_GetCommandResponse + 0x080063a4 0x6 build/stm32f7xx_ll_sdmmc.o + 0x080063a4 SDMMC_GetCommandResponse + .text.SDMMC_GetResponse + 0x080063aa 0x6 build/stm32f7xx_ll_sdmmc.o + 0x080063aa SDMMC_GetResponse + .text.SDMMC_ConfigData + 0x080063b0 0x24 build/stm32f7xx_ll_sdmmc.o + 0x080063b0 SDMMC_ConfigData + .text.SDMMC_CmdGoIdleState + 0x080063d4 0x26 build/stm32f7xx_ll_sdmmc.o + 0x080063d4 SDMMC_CmdGoIdleState + *fill* 0x080063fa 0x2 + .text.SDMMC_GetCmdResp1 + 0x080063fc 0x154 build/stm32f7xx_ll_sdmmc.o + 0x080063fc SDMMC_GetCmdResp1 + .text.SDMMC_CmdBlockLength + 0x08006550 0x30 build/stm32f7xx_ll_sdmmc.o + 0x08006550 SDMMC_CmdBlockLength + .text.SDMMC_CmdReadSingleBlock + 0x08006580 0x30 build/stm32f7xx_ll_sdmmc.o + 0x08006580 SDMMC_CmdReadSingleBlock + .text.SDMMC_CmdReadMultiBlock + 0x080065b0 0x30 build/stm32f7xx_ll_sdmmc.o + 0x080065b0 SDMMC_CmdReadMultiBlock + .text.SDMMC_CmdWriteSingleBlock + 0x080065e0 0x30 build/stm32f7xx_ll_sdmmc.o + 0x080065e0 SDMMC_CmdWriteSingleBlock + .text.SDMMC_CmdWriteMultiBlock + 0x08006610 0x30 build/stm32f7xx_ll_sdmmc.o + 0x08006610 SDMMC_CmdWriteMultiBlock + .text.SDMMC_CmdStopTransfer + 0x08006640 0x34 build/stm32f7xx_ll_sdmmc.o + 0x08006640 SDMMC_CmdStopTransfer + .text.SDMMC_CmdSelDesel + 0x08006674 0x30 build/stm32f7xx_ll_sdmmc.o + 0x08006674 SDMMC_CmdSelDesel + .text.SDMMC_CmdAppCommand + 0x080066a4 0x30 build/stm32f7xx_ll_sdmmc.o + 0x080066a4 SDMMC_CmdAppCommand + .text.SDMMC_CmdBusWidth + 0x080066d4 0x30 build/stm32f7xx_ll_sdmmc.o + 0x080066d4 SDMMC_CmdBusWidth + .text.SDMMC_CmdSendSCR + 0x08006704 0x30 build/stm32f7xx_ll_sdmmc.o + 0x08006704 SDMMC_CmdSendSCR + .text.SDMMC_CmdSendStatus + 0x08006734 0x30 build/stm32f7xx_ll_sdmmc.o + 0x08006734 SDMMC_CmdSendStatus + .text.SDMMC_GetCmdResp2 + 0x08006764 0x5c build/stm32f7xx_ll_sdmmc.o + 0x08006764 SDMMC_GetCmdResp2 + .text.SDMMC_CmdSendCID + 0x080067c0 0x2a build/stm32f7xx_ll_sdmmc.o + 0x080067c0 SDMMC_CmdSendCID + .text.SDMMC_CmdSendCSD + 0x080067ea 0x2a build/stm32f7xx_ll_sdmmc.o + 0x080067ea SDMMC_CmdSendCSD + .text.SDMMC_GetCmdResp3 + 0x08006814 0x4c build/stm32f7xx_ll_sdmmc.o + 0x08006814 SDMMC_GetCmdResp3 + .text.SDMMC_CmdAppOperCommand + 0x08006860 0x34 build/stm32f7xx_ll_sdmmc.o + 0x08006860 SDMMC_CmdAppOperCommand + .text.SDMMC_GetCmdResp6 + 0x08006894 0xa0 build/stm32f7xx_ll_sdmmc.o + 0x08006894 SDMMC_GetCmdResp6 + .text.SDMMC_CmdSetRelAdd + 0x08006934 0x30 build/stm32f7xx_ll_sdmmc.o + 0x08006934 SDMMC_CmdSetRelAdd + .text.SDMMC_GetCmdResp7 + 0x08006964 0x64 build/stm32f7xx_ll_sdmmc.o + 0x08006964 SDMMC_GetCmdResp7 + .text.SDMMC_CmdOperCond + 0x080069c8 0x2e build/stm32f7xx_ll_sdmmc.o + 0x080069c8 SDMMC_CmdOperCond + *fill* 0x080069f6 0x2 + .text.SD_PowerON + 0x080069f8 0xc0 build/stm32f7xx_hal_sd.o + .text.SD_FindSCR + 0x08006ab8 0x100 build/stm32f7xx_hal_sd.o + .text.SD_WideBus_Enable + 0x08006bb8 0x4e build/stm32f7xx_hal_sd.o + .text.SD_WideBus_Disable + 0x08006c06 0x4e build/stm32f7xx_hal_sd.o + .text.SD_SendStatus + 0x08006c54 0x2c build/stm32f7xx_hal_sd.o + .text.HAL_SD_ReadBlocks + 0x08006c80 0x248 build/stm32f7xx_hal_sd.o + 0x08006c80 HAL_SD_ReadBlocks + .text.HAL_SD_WriteBlocks + 0x08006ec8 0x200 build/stm32f7xx_hal_sd.o + 0x08006ec8 HAL_SD_WriteBlocks + .text.HAL_SD_GetCardCSD + 0x080070c8 0x1b8 build/stm32f7xx_hal_sd.o + 0x080070c8 HAL_SD_GetCardCSD + .text.SD_InitCard + 0x08007280 0x100 build/stm32f7xx_hal_sd.o + .text.HAL_SD_InitCard + 0x08007380 0xa8 build/stm32f7xx_hal_sd.o + 0x08007380 HAL_SD_InitCard + .text.HAL_SD_Init + 0x08007428 0x36 build/stm32f7xx_hal_sd.o + 0x08007428 HAL_SD_Init + .text.HAL_SD_GetCardInfo + 0x0800745e 0x24 build/stm32f7xx_hal_sd.o + 0x0800745e HAL_SD_GetCardInfo + *fill* 0x08007482 0x2 + .text.HAL_SD_ConfigWideBusOperation + 0x08007484 0xc0 build/stm32f7xx_hal_sd.o + 0x08007484 HAL_SD_ConfigWideBusOperation + .text.HAL_SD_GetCardState + 0x08007544 0x22 build/stm32f7xx_hal_sd.o + 0x08007544 HAL_SD_GetCardState + *fill* 0x08007566 0x2 + .text.LL_SPI_Init + 0x08007568 0x8c build/stm32f7xx_ll_spi.o + 0x08007568 LL_SPI_Init + .text.TIM_OC1_SetConfig + 0x080075f4 0x68 build/stm32f7xx_hal_tim.o + .text.TIM_OC3_SetConfig + 0x0800765c 0x70 build/stm32f7xx_hal_tim.o + .text.TIM_OC4_SetConfig + 0x080076cc 0x54 build/stm32f7xx_hal_tim.o + .text.TIM_OC5_SetConfig + 0x08007720 0x54 build/stm32f7xx_hal_tim.o + .text.TIM_OC6_SetConfig + 0x08007774 0x54 build/stm32f7xx_hal_tim.o + .text.TIM_TI1_ConfigInputStage + 0x080077c8 0x26 build/stm32f7xx_hal_tim.o + .text.TIM_TI2_ConfigInputStage + 0x080077ee 0x28 build/stm32f7xx_hal_tim.o + .text.TIM_ITRx_SetConfig + 0x08007816 0x10 build/stm32f7xx_hal_tim.o + .text.HAL_TIM_Base_Stop + 0x08007826 0x28 build/stm32f7xx_hal_tim.o + 0x08007826 HAL_TIM_Base_Stop + *fill* 0x0800784e 0x2 + .text.HAL_TIM_Base_Start_IT + 0x08007850 0x90 build/stm32f7xx_hal_tim.o + 0x08007850 HAL_TIM_Base_Start_IT + .text.HAL_TIM_Base_Stop_IT + 0x080078e0 0x32 build/stm32f7xx_hal_tim.o + 0x080078e0 HAL_TIM_Base_Stop_IT + .text.HAL_TIM_PWM_MspInit + 0x08007912 0x2 build/stm32f7xx_hal_tim.o + 0x08007912 HAL_TIM_PWM_MspInit + .text.HAL_TIM_PeriodElapsedCallback + 0x08007914 0x2 build/stm32f7xx_hal_tim.o + 0x08007914 HAL_TIM_PeriodElapsedCallback + .text.HAL_TIM_OC_DelayElapsedCallback + 0x08007916 0x2 build/stm32f7xx_hal_tim.o + 0x08007916 HAL_TIM_OC_DelayElapsedCallback + .text.HAL_TIM_IC_CaptureCallback + 0x08007918 0x2 build/stm32f7xx_hal_tim.o + 0x08007918 HAL_TIM_IC_CaptureCallback + .text.HAL_TIM_PWM_PulseFinishedCallback + 0x0800791a 0x2 build/stm32f7xx_hal_tim.o + 0x0800791a HAL_TIM_PWM_PulseFinishedCallback + .text.HAL_TIM_TriggerCallback + 0x0800791c 0x2 build/stm32f7xx_hal_tim.o + 0x0800791c HAL_TIM_TriggerCallback + .text.HAL_TIM_IRQHandler + 0x0800791e 0x17a build/stm32f7xx_hal_tim.o + 0x0800791e HAL_TIM_IRQHandler + .text.TIM_Base_SetConfig + 0x08007a98 0x120 build/stm32f7xx_hal_tim.o + 0x08007a98 TIM_Base_SetConfig + .text.HAL_TIM_Base_Init + 0x08007bb8 0x60 build/stm32f7xx_hal_tim.o + 0x08007bb8 HAL_TIM_Base_Init + .text.HAL_TIM_PWM_Init + 0x08007c18 0x60 build/stm32f7xx_hal_tim.o + 0x08007c18 HAL_TIM_PWM_Init + .text.TIM_OC2_SetConfig + 0x08007c78 0x70 build/stm32f7xx_hal_tim.o + 0x08007c78 TIM_OC2_SetConfig + .text.HAL_TIM_PWM_ConfigChannel + 0x08007ce8 0x13a build/stm32f7xx_hal_tim.o + 0x08007ce8 HAL_TIM_PWM_ConfigChannel + .text.TIM_ETR_SetConfig + 0x08007e22 0x1a build/stm32f7xx_hal_tim.o + 0x08007e22 TIM_ETR_SetConfig + .text.HAL_TIM_ConfigClockSource + 0x08007e3c 0x100 build/stm32f7xx_hal_tim.o + 0x08007e3c HAL_TIM_ConfigClockSource + .text.TIM_CCxChannelCmd + 0x08007f3c 0x1e build/stm32f7xx_hal_tim.o + 0x08007f3c TIM_CCxChannelCmd + *fill* 0x08007f5a 0x2 + .text.HAL_TIM_PWM_Start + 0x08007f5c 0x158 build/stm32f7xx_hal_tim.o + 0x08007f5c HAL_TIM_PWM_Start + .text.HAL_TIM_PWM_Stop + 0x080080b4 0xac build/stm32f7xx_hal_tim.o + 0x080080b4 HAL_TIM_PWM_Stop + .text.HAL_TIMEx_MasterConfigSynchronization + 0x08008160 0xa0 build/stm32f7xx_hal_tim_ex.o + 0x08008160 HAL_TIMEx_MasterConfigSynchronization + .text.HAL_TIMEx_CommutCallback + 0x08008200 0x2 build/stm32f7xx_hal_tim_ex.o + 0x08008200 HAL_TIMEx_CommutCallback + .text.HAL_TIMEx_BreakCallback + 0x08008202 0x2 build/stm32f7xx_hal_tim_ex.o + 0x08008202 HAL_TIMEx_BreakCallback + .text.HAL_TIMEx_Break2Callback + 0x08008204 0x2 build/stm32f7xx_hal_tim_ex.o + 0x08008204 HAL_TIMEx_Break2Callback + *fill* 0x08008206 0x2 + .text.LL_TIM_Init + 0x08008208 0x110 build/stm32f7xx_ll_tim.o + 0x08008208 LL_TIM_Init + .text.LL_USART_SetBaudRate + 0x08008318 0x2e build/stm32f7xx_ll_usart.o + *fill* 0x08008346 0x2 + .text.LL_USART_Init + 0x08008348 0xfc build/stm32f7xx_ll_usart.o + 0x08008348 LL_USART_Init + .text.SystemInit + 0x08008444 0x14 build/system_stm32f7xx.o + 0x08008444 SystemInit + .text.Mount_SD + 0x08008458 0x24 build/File_Handling.o + 0x08008458 Mount_SD + .text.Unmount_SD + 0x0800847c 0x20 build/File_Handling.o + 0x0800847c Unmount_SD + .text.Write_File_byte + 0x0800849c 0x5c build/File_Handling.o + 0x0800849c Write_File_byte + .text.Seek_Read_File + 0x080084f8 0x148 build/File_Handling.o + 0x080084f8 Seek_Read_File + .text.Create_File + 0x08008640 0x44 build/File_Handling.o + 0x08008640 Create_File + .text.Remove_File + 0x08008684 0x84 build/File_Handling.o + 0x08008684 Remove_File + .text.Update_File_byte + 0x08008708 0x5c build/File_Handling.o + 0x08008708 Update_File_byte + .text.disk_status + 0x08008764 0x18 build/diskio.o + 0x08008764 disk_status + .text.disk_initialize + 0x0800877c 0x28 build/diskio.o + 0x0800877c disk_initialize + .text.disk_read + 0x080087a4 0x18 build/diskio.o + 0x080087a4 disk_read + .text.disk_write + 0x080087bc 0x18 build/diskio.o + 0x080087bc disk_write + .text.disk_ioctl + 0x080087d4 0x18 build/diskio.o + 0x080087d4 disk_ioctl + .text.ld_word 0x080087ec 0xa build/ff.o + .text.ld_dword + 0x080087f6 0x16 build/ff.o + .text.st_word 0x0800880c 0x8 build/ff.o + .text.st_dword + 0x08008814 0x14 build/ff.o + .text.mem_cpy 0x08008828 0x14 build/ff.o + .text.mem_set 0x0800883c 0xa build/ff.o + .text.mem_cmp 0x08008846 0x1a build/ff.o + .text.chk_chr 0x08008860 0x10 build/ff.o + .text.chk_lock + 0x08008870 0x7c build/ff.o + .text.enq_lock + 0x080088ec 0x20 build/ff.o + .text.inc_lock + 0x0800890c 0xa0 build/ff.o + .text.dec_lock + 0x080089ac 0x40 build/ff.o + .text.clear_lock + 0x080089ec 0x3c build/ff.o + .text.clust2sect + 0x08008a28 0x18 build/ff.o + .text.clmt_clust + 0x08008a40 0x26 build/ff.o + .text.ld_clust + 0x08008a66 0x26 build/ff.o + .text.st_clust + 0x08008a8c 0x26 build/ff.o + .text.get_fileinfo + 0x08008ab2 0x6a build/ff.o + .text.create_name + 0x08008b1c 0xd0 build/ff.o + .text.get_ldnumber + 0x08008bec 0x48 build/ff.o + .text.validate + 0x08008c34 0x46 build/ff.o + .text.sync_window + 0x08008c7a 0x54 build/ff.o + .text.move_window + 0x08008cce 0x36 build/ff.o + .text.check_fs + 0x08008d04 0x78 build/ff.o + .text.find_volume + 0x08008d7c 0x34c build/ff.o + .text.put_fat 0x080090c8 0x136 build/ff.o + .text.get_fat 0x080091fe 0xfc build/ff.o + .text.dir_sdi 0x080092fa 0xc0 build/ff.o + .text.create_chain + 0x080093ba 0xd6 build/ff.o + .text.remove_chain + 0x08009490 0x7e build/ff.o + .text.dir_remove + 0x0800950e 0x1c build/ff.o + .text.dir_next + 0x0800952a 0x118 build/ff.o + .text.dir_find + 0x08009642 0x5a build/ff.o + .text.follow_path + 0x0800969c 0x92 build/ff.o + .text.dir_alloc + 0x0800972e 0x4e build/ff.o + .text.dir_register + 0x0800977c 0x3e build/ff.o + .text.dir_read + 0x080097ba 0x5e build/ff.o + .text.sync_fs 0x08009818 0x88 build/ff.o + .text.f_mount 0x080098a0 0x60 build/ff.o + 0x080098a0 f_mount + .text.f_open 0x08009900 0x232 build/ff.o + 0x08009900 f_open + .text.f_read 0x08009b32 0x1d8 build/ff.o + 0x08009b32 f_read + .text.f_write 0x08009d0a 0x210 build/ff.o + 0x08009d0a f_write + .text.f_sync 0x08009f1a 0x98 build/ff.o + 0x08009f1a f_sync + .text.f_close 0x08009fb2 0x2a build/ff.o + 0x08009fb2 f_close + .text.f_lseek 0x08009fdc 0x2a6 build/ff.o + 0x08009fdc f_lseek + .text.f_stat 0x0800a282 0x44 build/ff.o + 0x0800a282 f_stat + .text.f_unlink + 0x0800a2c6 0xc4 build/ff.o + 0x0800a2c6 f_unlink + *fill* 0x0800a38a 0x2 + .text.FATFS_LinkDriverEx + 0x0800a38c 0x54 build/ff_gen_drv.o + 0x0800a38c FATFS_LinkDriverEx + .text.FATFS_LinkDriver + 0x0800a3e0 0xa build/ff_gen_drv.o + 0x0800a3e0 FATFS_LinkDriver + *fill* 0x0800a3ea 0x2 + .text._sbrk 0x0800a3ec 0x48 build/sysmem.o + 0x0800a3ec _sbrk + .text.UART_EndRxTransfer + 0x0800a434 0x52 build/stm32f7xx_hal_uart.o + *fill* 0x0800a486 0x2 + .text.UART_SetConfig + 0x0800a488 0x328 build/stm32f7xx_hal_uart.o + 0x0800a488 UART_SetConfig + .text.UART_AdvFeatureConfig + 0x0800a7b0 0xca build/stm32f7xx_hal_uart.o + 0x0800a7b0 UART_AdvFeatureConfig + .text.UART_WaitOnFlagUntilTimeout + 0x0800a87a 0xa6 build/stm32f7xx_hal_uart.o + 0x0800a87a UART_WaitOnFlagUntilTimeout + .text.UART_CheckIdleState + 0x0800a920 0xc6 build/stm32f7xx_hal_uart.o + 0x0800a920 UART_CheckIdleState + .text.HAL_UART_Init + 0x0800a9e6 0x62 build/stm32f7xx_hal_uart.o + 0x0800a9e6 HAL_UART_Init + .text.Reset_Handler + 0x0800aa48 0x50 build/startup_stm32f767xx.o + 0x0800aa48 Reset_Handler + .text.Default_Handler + 0x0800aa98 0x2 build/startup_stm32f767xx.o + 0x0800aa98 RTC_Alarm_IRQHandler + 0x0800aa98 EXTI2_IRQHandler + 0x0800aa98 TIM8_CC_IRQHandler + 0x0800aa98 UART8_IRQHandler + 0x0800aa98 SPI4_IRQHandler + 0x0800aa98 TIM1_CC_IRQHandler + 0x0800aa98 DMA2_Stream5_IRQHandler + 0x0800aa98 JPEG_IRQHandler + 0x0800aa98 DMA1_Stream5_IRQHandler + 0x0800aa98 CAN3_RX1_IRQHandler + 0x0800aa98 PVD_IRQHandler + 0x0800aa98 TAMP_STAMP_IRQHandler + 0x0800aa98 CAN2_RX1_IRQHandler + 0x0800aa98 EXTI3_IRQHandler + 0x0800aa98 TIM8_TRG_COM_TIM14_IRQHandler + 0x0800aa98 DFSDM1_FLT1_IRQHandler + 0x0800aa98 I2C3_ER_IRQHandler + 0x0800aa98 DFSDM1_FLT2_IRQHandler + 0x0800aa98 EXTI0_IRQHandler + 0x0800aa98 I2C2_EV_IRQHandler + 0x0800aa98 DMA1_Stream2_IRQHandler + 0x0800aa98 CAN1_RX0_IRQHandler + 0x0800aa98 FPU_IRQHandler + 0x0800aa98 OTG_HS_WKUP_IRQHandler + 0x0800aa98 CAN3_SCE_IRQHandler + 0x0800aa98 LTDC_ER_IRQHandler + 0x0800aa98 CAN2_SCE_IRQHandler + 0x0800aa98 DMA2_Stream2_IRQHandler + 0x0800aa98 SPI1_IRQHandler + 0x0800aa98 TIM1_BRK_TIM9_IRQHandler + 0x0800aa98 DCMI_IRQHandler + 0x0800aa98 CAN2_RX0_IRQHandler + 0x0800aa98 DMA2_Stream3_IRQHandler + 0x0800aa98 SAI2_IRQHandler + 0x0800aa98 DFSDM1_FLT3_IRQHandler + 0x0800aa98 USART6_IRQHandler + 0x0800aa98 CAN3_RX0_IRQHandler + 0x0800aa98 USART3_IRQHandler + 0x0800aa98 CAN1_RX1_IRQHandler + 0x0800aa98 UART5_IRQHandler + 0x0800aa98 DMA2_Stream0_IRQHandler + 0x0800aa98 TIM4_IRQHandler + 0x0800aa98 QUADSPI_IRQHandler + 0x0800aa98 I2C1_EV_IRQHandler + 0x0800aa98 DMA1_Stream6_IRQHandler + 0x0800aa98 DMA1_Stream1_IRQHandler + 0x0800aa98 UART4_IRQHandler + 0x0800aa98 TIM3_IRQHandler + 0x0800aa98 RCC_IRQHandler + 0x0800aa98 TIM8_BRK_TIM12_IRQHandler + 0x0800aa98 Default_Handler + 0x0800aa98 CEC_IRQHandler + 0x0800aa98 EXTI15_10_IRQHandler + 0x0800aa98 DMA1_Stream7_IRQHandler + 0x0800aa98 SPI5_IRQHandler + 0x0800aa98 SDMMC1_IRQHandler + 0x0800aa98 CAN2_TX_IRQHandler + 0x0800aa98 I2C3_EV_IRQHandler + 0x0800aa98 EXTI9_5_IRQHandler + 0x0800aa98 RTC_WKUP_IRQHandler + 0x0800aa98 LTDC_IRQHandler + 0x0800aa98 ETH_WKUP_IRQHandler + 0x0800aa98 SPDIF_RX_IRQHandler + 0x0800aa98 SPI2_IRQHandler + 0x0800aa98 OTG_HS_EP1_IN_IRQHandler + 0x0800aa98 DMA1_Stream0_IRQHandler + 0x0800aa98 CAN1_TX_IRQHandler + 0x0800aa98 EXTI4_IRQHandler + 0x0800aa98 RNG_IRQHandler + 0x0800aa98 ETH_IRQHandler + 0x0800aa98 OTG_HS_EP1_OUT_IRQHandler + 0x0800aa98 WWDG_IRQHandler + 0x0800aa98 SPI6_IRQHandler + 0x0800aa98 MDIOS_IRQHandler + 0x0800aa98 I2C4_EV_IRQHandler + 0x0800aa98 CAN3_TX_IRQHandler + 0x0800aa98 OTG_FS_WKUP_IRQHandler + 0x0800aa98 OTG_HS_IRQHandler + 0x0800aa98 DMA2D_IRQHandler + 0x0800aa98 EXTI1_IRQHandler + 0x0800aa98 SDMMC2_IRQHandler + 0x0800aa98 UART7_IRQHandler + 0x0800aa98 USART2_IRQHandler + 0x0800aa98 DFSDM1_FLT0_IRQHandler + 0x0800aa98 I2C2_ER_IRQHandler + 0x0800aa98 DMA2_Stream1_IRQHandler + 0x0800aa98 CAN1_SCE_IRQHandler + 0x0800aa98 FLASH_IRQHandler + 0x0800aa98 DMA2_Stream4_IRQHandler + 0x0800aa98 OTG_FS_IRQHandler + 0x0800aa98 SPI3_IRQHandler + 0x0800aa98 DMA1_Stream4_IRQHandler + 0x0800aa98 I2C1_ER_IRQHandler + 0x0800aa98 FMC_IRQHandler + 0x0800aa98 LPTIM1_IRQHandler + 0x0800aa98 I2C4_ER_IRQHandler + 0x0800aa98 DMA2_Stream6_IRQHandler + 0x0800aa98 SAI1_IRQHandler + 0x0800aa98 DMA1_Stream3_IRQHandler + *(.glue_7) + .glue_7 0x0800aa9a 0x0 linker stubs + *(.glue_7t) + .glue_7t 0x0800aa9a 0x0 linker stubs + *(.eh_frame) + *fill* 0x0800aa9a 0x2 + .eh_frame 0x0800aa9c 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o + *(.init) + .init 0x0800aa9c 0x4 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crti.o + 0x0800aa9c _init + .init 0x0800aaa0 0x8 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtn.o + *(.fini) + .fini 0x0800aaa8 0x4 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crti.o + 0x0800aaa8 _fini + .fini 0x0800aaac 0x8 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtn.o + 0x0800aab4 . = ALIGN (0x4) + 0x0800aab4 _etext = . + +.vfp11_veneer 0x0800aab4 0x0 + .vfp11_veneer 0x0800aab4 0x0 linker stubs + +.v4_bx 0x0800aab4 0x0 + .v4_bx 0x0800aab4 0x0 linker stubs + +.iplt 0x0800aab4 0x0 + .iplt 0x0800aab4 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o + +.rodata 0x0800aab4 0x25c + 0x0800aab4 . = ALIGN (0x4) + *(.rodata) + *(.rodata*) + .rodata.Init_params.str1.4 + 0x0800aab4 0x1ad build/main.o + 0x10 (size before relaxing) + .rodata.SD_SAVE.str1.4 + 0x0800ac61 0xa build/main.o + *fill* 0x0800ac61 0x3 + .rodata.SD_Driver + 0x0800ac64 0x14 build/sd_diskio.o + 0x0800ac64 SD_Driver + .rodata.APBPrescTable + 0x0800ac78 0x8 build/system_stm32f7xx.o + 0x0800ac78 APBPrescTable + .rodata.AHBPrescTable + 0x0800ac80 0x10 build/system_stm32f7xx.o + 0x0800ac80 AHBPrescTable + .rodata.Read_File.str1.4 + 0x0800ac90 0xbb build/File_Handling.o + .rodata.Seek_Read_File.str1.4 + 0x0800ac90 0x27 build/File_Handling.o + .rodata.Remove_File.str1.4 + 0x0800ac90 0x64 build/File_Handling.o + .rodata.create_name.str1.4 + 0x0800ac90 0xf build/ff.o + .rodata.ExCvt 0x0800ac90 0x80 build/ff.o + .rodata.str1.4 + 0x0800ad10 0x13 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) + .rodata.str1.4 + 0x0800ad10 0x25 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-vfprintf_i.o) + 0x0800ad4c . = ALIGN (0x4) + +.ARM.extab + *(.ARM.extab* .gnu.linkonce.armextab.*) + +.ARM 0x0800ad10 0x8 + 0x0800ad10 __exidx_start = . + *(.ARM.exidx*) + .ARM.exidx 0x0800ad10 0x8 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memchr.o) + .ARM.exidx 0x0800ad18 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy.o) + 0x8 (size before relaxing) + .ARM.exidx 0x0800ad18 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + 0x8 (size before relaxing) + 0x0800ad18 __exidx_end = . + +.rel.dyn 0x0800ad18 0x0 + .rel.iplt 0x0800ad18 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o + +.preinit_array 0x0800ad18 0x0 + 0x0800ad18 PROVIDE (__preinit_array_start = .) + *(.preinit_array*) + 0x0800ad18 PROVIDE (__preinit_array_end = .) + +.init_array 0x0800ad18 0x4 + 0x0800ad18 PROVIDE (__init_array_start = .) + *(SORT_BY_NAME(.init_array.*)) + *(.init_array*) + .init_array 0x0800ad18 0x4 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o + 0x0800ad1c PROVIDE (__init_array_end = .) + +.fini_array 0x0800ad1c 0x4 + 0x0800ad1c PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array*) + .fini_array 0x0800ad1c 0x4 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o + 0x0800ad20 PROVIDE (__fini_array_end = .) + 0x0800ad20 _sidata = LOADADDR (.data) + +.data 0x20000000 0x5c load address 0x0800ad20 + 0x20000000 . = ALIGN (0x4) + 0x20000000 _sdata = . + *(.data) + .data 0x20000000 0x50 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-impure.o) + 0x20000000 _impure_ptr + 0x20000004 _impure_data + *(.data*) + .data.Stat 0x20000050 0x1 build/sd_diskio.o + .data.uwTickFreq + 0x20000051 0x1 build/stm32f7xx_hal.o + 0x20000051 uwTickFreq + *fill* 0x20000052 0x2 + .data.uwTickPrio + 0x20000054 0x4 build/stm32f7xx_hal.o + 0x20000054 uwTickPrio + .data.SystemCoreClock + 0x20000058 0x4 build/system_stm32f7xx.o + 0x20000058 SystemCoreClock + 0x2000005c . = ALIGN (0x4) + 0x2000005c _edata = . + +.tm_clone_table + 0x2000005c 0x0 load address 0x0800ad7c + .tm_clone_table + 0x2000005c 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o + .tm_clone_table + 0x2000005c 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtend.o + +.igot.plt 0x2000005c 0x0 load address 0x0800ad7c + .igot.plt 0x2000005c 0x0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o + 0x2000005c . = ALIGN (0x4) + +.bss 0x2000005c 0x266c load address 0x0800ad7c + 0x2000005c _sbss = . + 0x2000005c __bss_start__ = _sbss + *(.bss) + .bss 0x2000005c 0x1c /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o + .bss 0x20000078 0x8 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) + 0x20000078 __malloc_sbrk_start + 0x2000007c __malloc_free_list + .bss 0x20000080 0x13c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + 0x20000080 __sf + 0x200001b8 __stdio_exit_handler + .bss 0x200001bc 0x4 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reent.o) + 0x200001bc errno + *(.bss*) + .bss.task 0x200001c0 0x34 build/main.o + 0x200001c0 task + .bss.LD_blinker + 0x200001f4 0xc build/main.o + 0x200001f4 LD_blinker + .bss.LD2_param + 0x20000200 0xc build/main.o + 0x20000200 LD2_param + .bss.LD1_param + 0x2000020c 0xc build/main.o + 0x2000020c LD1_param + .bss.Def_setup + 0x20000218 0x12 build/main.o + 0x20000218 Def_setup + *fill* 0x2000022a 0x2 + .bss.Curr_setup + 0x2000022c 0x12 build/main.o + 0x2000022c Curr_setup + *fill* 0x2000023e 0x2 + .bss.LD2_def_setup + 0x20000240 0x10 build/main.o + 0x20000240 LD2_def_setup + .bss.LD1_def_setup + 0x20000250 0x10 build/main.o + 0x20000250 LD1_def_setup + .bss.LD2_curr_setup + 0x20000260 0x10 build/main.o + 0x20000260 LD2_curr_setup + .bss.LD1_curr_setup + 0x20000270 0x10 build/main.o + 0x20000270 LD1_curr_setup + .bss.sizeoffile + 0x20000280 0x4 build/main.o + 0x20000280 sizeoffile + .bss.fgoto 0x20000284 0x4 build/main.o + 0x20000284 fgoto + .bss.test 0x20000288 0x4 build/main.o + 0x20000288 test + .bss.fresult 0x2000028c 0x1 build/main.o + 0x2000028c fresult + *fill* 0x2000028d 0x3 + .bss.COMMAND 0x20000290 0x1e build/main.o + 0x20000290 COMMAND + *fill* 0x200002ae 0x2 + .bss.Long_Data + 0x200002b0 0x1e build/main.o + 0x200002b0 Long_Data + .bss.temp16 0x200002ce 0x2 build/main.o + 0x200002ce temp16 + .bss.CS_result + 0x200002d0 0x2 build/main.o + 0x200002d0 CS_result + .bss.UART_header + 0x200002d2 0x2 build/main.o + 0x200002d2 UART_header + .bss.UART_rec_incr + 0x200002d4 0x2 build/main.o + 0x200002d4 UART_rec_incr + .bss.TIM10_coflag + 0x200002d6 0x1 build/main.o + 0x200002d6 TIM10_coflag + .bss.u_rx_flg 0x200002d7 0x1 build/main.o + 0x200002d7 u_rx_flg + .bss.u_tx_flg 0x200002d8 0x1 build/main.o + 0x200002d8 u_tx_flg + .bss.flg_tmt 0x200002d9 0x1 build/main.o + 0x200002d9 flg_tmt + *fill* 0x200002da 0x2 + .bss.UART_DATA + 0x200002dc 0x1e build/main.o + 0x200002dc UART_DATA + *fill* 0x200002fa 0x2 + .bss.State_Data + 0x200002fc 0x2 build/main.o + 0x200002fc State_Data + .bss.UART_transmission_request + 0x200002fe 0x1 build/main.o + 0x200002fe UART_transmission_request + .bss.CPU_state_old + 0x200002ff 0x1 build/main.o + 0x200002ff CPU_state_old + .bss.CPU_state + 0x20000300 0x1 build/main.o + 0x20000300 CPU_state + .bss.uart_buf 0x20000301 0x1 build/main.o + 0x20000301 uart_buf + *fill* 0x20000302 0x2 + .bss.TIM10_period + 0x20000304 0x4 build/main.o + 0x20000304 TIM10_period + .bss.TO10_counter + 0x20000308 0x4 build/main.o + 0x20000308 TO10_counter + .bss.TO10 0x2000030c 0x4 build/main.o + 0x2000030c TO10 + .bss.TO7_PID 0x20000310 0x4 build/main.o + 0x20000310 TO7_PID + .bss.TO7_before + 0x20000314 0x4 build/main.o + 0x20000314 TO7_before + .bss.TO7 0x20000318 0x4 build/main.o + 0x20000318 TO7 + .bss.SD_SLIDE 0x2000031c 0x4 build/main.o + 0x2000031c SD_SLIDE + .bss.SD_SEEK 0x20000320 0x4 build/main.o + 0x20000320 SD_SEEK + .bss.TO6_uart 0x20000324 0x4 build/main.o + 0x20000324 TO6_uart + .bss.TO6_stop 0x20000328 0x4 build/main.o + 0x20000328 TO6_stop + .bss.TO6_before + 0x2000032c 0x4 build/main.o + 0x2000032c TO6_before + .bss.TO6 0x20000330 0x4 build/main.o + 0x20000330 TO6 + .bss.huart8 0x20000334 0x88 build/main.o + 0x20000334 huart8 + .bss.htim11 0x200003bc 0x4c build/main.o + 0x200003bc htim11 + .bss.htim10 0x20000408 0x4c build/main.o + 0x20000408 htim10 + .bss.htim8 0x20000454 0x4c build/main.o + 0x20000454 htim8 + .bss.htim4 0x200004a0 0x4c build/main.o + 0x200004a0 htim4 + .bss.hsd1 0x200004ec 0x84 build/main.o + 0x200004ec hsd1 + .bss.hadc3 0x20000570 0x48 build/main.o + 0x20000570 hadc3 + .bss.hadc1 0x200005b8 0x48 build/main.o + 0x200005b8 hadc1 + .bss.SDPath 0x20000600 0x4 build/fatfs.o + 0x20000600 SDPath + .bss.retSD 0x20000604 0x1 build/fatfs.o + 0x20000604 retSD + *fill* 0x20000605 0x3 + .bss.uwTick 0x20000608 0x4 build/stm32f7xx_hal.o + 0x20000608 uwTick + .bss.bw 0x2000060c 0x4 build/File_Handling.o + 0x2000060c bw + .bss.br 0x20000610 0x4 build/File_Handling.o + 0x20000610 br + .bss.fno 0x20000614 0x18 build/File_Handling.o + 0x20000614 fno + .bss.fil 0x2000062c 0x1030 build/File_Handling.o + 0x2000062c fil + .bss.fs 0x2000165c 0x1034 build/File_Handling.o + 0x2000165c fs + .bss.Files 0x20002690 0x20 build/ff.o + .bss.Fsid 0x200026b0 0x2 build/ff.o + *fill* 0x200026b2 0x2 + .bss.FatFs 0x200026b4 0x4 build/ff.o + .bss.disk 0x200026b8 0xc build/ff_gen_drv.o + 0x200026b8 disk + .bss.__sbrk_heap_end + 0x200026c4 0x4 build/sysmem.o + *(COMMON) + 0x200026c8 . = ALIGN (0x4) + 0x200026c8 _ebss = . + 0x200026c8 __bss_end__ = _ebss + +._user_heap_stack + 0x200026c8 0x6000 load address 0x0800ad7c + 0x200026c8 . = ALIGN (0x8) + [!provide] PROVIDE (end = .) + 0x200026c8 PROVIDE (_end = .) + 0x200046c8 . = (. + _Min_Heap_Size) + *fill* 0x200026c8 0x2000 + 0x200086c8 . = (. + _Min_Stack_Size) + *fill* 0x200046c8 0x4000 + 0x200086c8 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) +OUTPUT(build/For_stm32.elf elf32-littlearm) +LOAD linker stubs +LOAD /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc.a +LOAD /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libm.a +LOAD /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a + +.ARM.attributes + 0x00000000 0x2e + .ARM.attributes + 0x00000000 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crti.o + .ARM.attributes + 0x00000020 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o + .ARM.attributes + 0x00000052 0x32 build/main.o + .ARM.attributes + 0x00000084 0x32 build/bsp_driver_sd.o + .ARM.attributes + 0x000000b6 0x32 build/sd_diskio.o + .ARM.attributes + 0x000000e8 0x32 build/fatfs.o + .ARM.attributes + 0x0000011a 0x32 build/fatfs_platform.o + .ARM.attributes + 0x0000014c 0x32 build/stm32f7xx_it.o + .ARM.attributes + 0x0000017e 0x32 build/stm32f7xx_hal_msp.o + .ARM.attributes + 0x000001b0 0x32 build/stm32f7xx_hal_adc.o + .ARM.attributes + 0x000001e2 0x32 build/stm32f7xx_hal_adc_ex.o + .ARM.attributes + 0x00000214 0x32 build/stm32f7xx_hal_rcc.o + .ARM.attributes + 0x00000246 0x32 build/stm32f7xx_hal_rcc_ex.o + .ARM.attributes + 0x00000278 0x32 build/stm32f7xx_hal_gpio.o + .ARM.attributes + 0x000002aa 0x32 build/stm32f7xx_hal_pwr_ex.o + .ARM.attributes + 0x000002dc 0x32 build/stm32f7xx_hal_cortex.o + .ARM.attributes + 0x0000030e 0x32 build/stm32f7xx_hal.o + .ARM.attributes + 0x00000340 0x32 build/stm32f7xx_ll_rcc.o + .ARM.attributes + 0x00000372 0x32 build/stm32f7xx_ll_gpio.o + .ARM.attributes + 0x000003a4 0x32 build/stm32f7xx_ll_sdmmc.o + .ARM.attributes + 0x000003d6 0x32 build/stm32f7xx_hal_sd.o + .ARM.attributes + 0x00000408 0x32 build/stm32f7xx_ll_spi.o + .ARM.attributes + 0x0000043a 0x32 build/stm32f7xx_hal_tim.o + .ARM.attributes + 0x0000046c 0x32 build/stm32f7xx_hal_tim_ex.o + .ARM.attributes + 0x0000049e 0x32 build/stm32f7xx_ll_tim.o + .ARM.attributes + 0x000004d0 0x32 build/stm32f7xx_ll_usart.o + .ARM.attributes + 0x00000502 0x32 build/system_stm32f7xx.o + .ARM.attributes + 0x00000534 0x32 build/File_Handling.o + .ARM.attributes + 0x00000566 0x32 build/diskio.o + .ARM.attributes + 0x00000598 0x32 build/ff.o + .ARM.attributes + 0x000005ca 0x32 build/ff_gen_drv.o + .ARM.attributes + 0x000005fc 0x32 build/sysmem.o + .ARM.attributes + 0x0000062e 0x32 build/stm32f7xx_hal_uart.o + .ARM.attributes + 0x00000660 0x21 build/startup_stm32f767xx.o + .ARM.attributes + 0x00000681 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) + .ARM.attributes + 0x000006b3 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-impure.o) + .ARM.attributes + 0x000006e5 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) + .ARM.attributes + 0x00000717 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + .ARM.attributes + 0x00000749 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + .ARM.attributes + 0x0000077b 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-errno.o) + .ARM.attributes + 0x000007ad 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) + .ARM.attributes + 0x000007df 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-freer.o) + .ARM.attributes + 0x00000811 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memmove.o) + .ARM.attributes + 0x00000843 0x1c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memchr.o) + .ARM.attributes + 0x0000085f 0x1e /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy.o) + .ARM.attributes + 0x0000087d 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-malloc.o) + .ARM.attributes + 0x000008af 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reallocr.o) + .ARM.attributes + 0x000008e1 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-vfprintf_i.o) + .ARM.attributes + 0x00000913 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mlock.o) + .ARM.attributes + 0x00000945 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sbrkr.o) + .ARM.attributes + 0x00000977 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-msizer.o) + .ARM.attributes + 0x000009a9 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + .ARM.attributes + 0x000009db 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reent.o) + .ARM.attributes + 0x00000a0d 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + .ARM.attributes + 0x00000a2d 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + .ARM.attributes + 0x00000a5f 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x00000a7f 0x32 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtend.o + .ARM.attributes + 0x00000ab1 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtn.o + +.comment 0x00000000 0x26 + .comment 0x00000000 0x26 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o + 0x27 (size before relaxing) + .comment 0x00000026 0x27 build/main.o + .comment 0x00000026 0x27 build/bsp_driver_sd.o + .comment 0x00000026 0x27 build/sd_diskio.o + .comment 0x00000026 0x27 build/fatfs.o + .comment 0x00000026 0x27 build/fatfs_platform.o + .comment 0x00000026 0x27 build/stm32f7xx_it.o + .comment 0x00000026 0x27 build/stm32f7xx_hal_msp.o + .comment 0x00000026 0x27 build/stm32f7xx_hal_adc.o + .comment 0x00000026 0x27 build/stm32f7xx_hal_adc_ex.o + .comment 0x00000026 0x27 build/stm32f7xx_hal_rcc.o + .comment 0x00000026 0x27 build/stm32f7xx_hal_rcc_ex.o + .comment 0x00000026 0x27 build/stm32f7xx_hal_gpio.o + .comment 0x00000026 0x27 build/stm32f7xx_hal_pwr_ex.o + .comment 0x00000026 0x27 build/stm32f7xx_hal_cortex.o + .comment 0x00000026 0x27 build/stm32f7xx_hal.o + .comment 0x00000026 0x27 build/stm32f7xx_ll_rcc.o + .comment 0x00000026 0x27 build/stm32f7xx_ll_gpio.o + .comment 0x00000026 0x27 build/stm32f7xx_ll_sdmmc.o + .comment 0x00000026 0x27 build/stm32f7xx_hal_sd.o + .comment 0x00000026 0x27 build/stm32f7xx_ll_spi.o + .comment 0x00000026 0x27 build/stm32f7xx_hal_tim.o + .comment 0x00000026 0x27 build/stm32f7xx_hal_tim_ex.o + .comment 0x00000026 0x27 build/stm32f7xx_ll_tim.o + .comment 0x00000026 0x27 build/stm32f7xx_ll_usart.o + .comment 0x00000026 0x27 build/system_stm32f7xx.o + .comment 0x00000026 0x27 build/File_Handling.o + .comment 0x00000026 0x27 build/diskio.o + .comment 0x00000026 0x27 build/ff.o + .comment 0x00000026 0x27 build/ff_gen_drv.o + .comment 0x00000026 0x27 build/sysmem.o + .comment 0x00000026 0x27 build/stm32f7xx_hal_uart.o + .comment 0x00000026 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) + .comment 0x00000026 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-impure.o) + .comment 0x00000026 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) + .comment 0x00000026 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + .comment 0x00000026 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + .comment 0x00000026 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-errno.o) + .comment 0x00000026 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) + .comment 0x00000026 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-freer.o) + .comment 0x00000026 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memmove.o) + .comment 0x00000026 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-malloc.o) + .comment 0x00000026 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reallocr.o) + .comment 0x00000026 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-vfprintf_i.o) + .comment 0x00000026 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mlock.o) + .comment 0x00000026 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sbrkr.o) + .comment 0x00000026 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-msizer.o) + .comment 0x00000026 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + .comment 0x00000026 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reent.o) + .comment 0x00000026 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + .comment 0x00000026 0x27 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtend.o + +.debug_info 0x00000000 0x3a793 + .debug_info 0x00000000 0x818e build/main.o + .debug_info 0x0000818e 0xe39 build/bsp_driver_sd.o + .debug_info 0x00008fc7 0x74a build/sd_diskio.o + .debug_info 0x00009711 0x65a build/fatfs.o + .debug_info 0x00009d6b 0x1f0 build/fatfs_platform.o + .debug_info 0x00009f5b 0x1925 build/stm32f7xx_it.o + .debug_info 0x0000b880 0x23e6 build/stm32f7xx_hal_msp.o + .debug_info 0x0000dc66 0xfb5 build/stm32f7xx_hal_adc.o + .debug_info 0x0000ec1b 0xd39 build/stm32f7xx_hal_adc_ex.o + .debug_info 0x0000f954 0xd0b build/stm32f7xx_hal_rcc.o + .debug_info 0x0001065f 0x96b build/stm32f7xx_hal_rcc_ex.o + .debug_info 0x00010fca 0x867 build/stm32f7xx_hal_gpio.o + .debug_info 0x00011831 0xb00 build/stm32f7xx_hal_pwr_ex.o + .debug_info 0x00012331 0x145b build/stm32f7xx_hal_cortex.o + .debug_info 0x0001378c 0xc0b build/stm32f7xx_hal.o + .debug_info 0x00014397 0x1d6b build/stm32f7xx_ll_rcc.o + .debug_info 0x00016102 0xda5 build/stm32f7xx_ll_gpio.o + .debug_info 0x00016ea7 0x1ad6 build/stm32f7xx_ll_sdmmc.o + .debug_info 0x0001897d 0x2a28 build/stm32f7xx_hal_sd.o + .debug_info 0x0001b3a5 0xb14 build/stm32f7xx_ll_spi.o + .debug_info 0x0001beb9 0x42a3 build/stm32f7xx_hal_tim.o + .debug_info 0x0002015c 0x2009 build/stm32f7xx_hal_tim_ex.o + .debug_info 0x00022165 0x19f0 build/stm32f7xx_ll_tim.o + .debug_info 0x00023b55 0xc07 build/stm32f7xx_ll_usart.o + .debug_info 0x0002475c 0x7ea build/system_stm32f7xx.o + .debug_info 0x00024f46 0x1ef6 build/File_Handling.o + .debug_info 0x00026e3c 0x5f7 build/diskio.o + .debug_info 0x00027433 0x47f5 build/ff.o + .debug_info 0x0002bc28 0x525 build/ff_gen_drv.o + .debug_info 0x0002c14d 0x174 build/sysmem.o + .debug_info 0x0002c2c1 0x54ac build/stm32f7xx_hal_uart.o + .debug_info 0x0003176d 0x30 build/startup_stm32f767xx.o + .debug_info 0x0003179d 0x87b /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) + .debug_info 0x00032018 0x70b /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-impure.o) + .debug_info 0x00032723 0x1092 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) + .debug_info 0x000337b5 0x10b /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + .debug_info 0x000338c0 0x135 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + .debug_info 0x000339f5 0x6f1 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-errno.o) + .debug_info 0x000340e6 0x9b6 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) + .debug_info 0x00034a9c 0x87f /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-freer.o) + .debug_info 0x0003531b 0x148 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memmove.o) + .debug_info 0x00035463 0x25 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memchr.o) + .debug_info 0x00035488 0x33 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy.o) + .debug_info 0x000354bb 0x796 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-malloc.o) + .debug_info 0x00035c51 0x8cd /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reallocr.o) + .debug_info 0x0003651e 0xdd7 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-vfprintf_i.o) + .debug_info 0x000372f5 0x71c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mlock.o) + .debug_info 0x00037a11 0x778 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sbrkr.o) + .debug_info 0x00038189 0x78a /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-msizer.o) + .debug_info 0x00038913 0xe8c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + .debug_info 0x0003979f 0x89f /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reent.o) + .debug_info 0x0003a03e 0x24 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + .debug_info 0x0003a062 0x6f5 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + .debug_info 0x0003a757 0x3c /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) + +.debug_abbrev 0x00000000 0x7012 + .debug_abbrev 0x00000000 0x506 build/main.o + .debug_abbrev 0x00000506 0x2a1 build/bsp_driver_sd.o + .debug_abbrev 0x000007a7 0x1e1 build/sd_diskio.o + .debug_abbrev 0x00000988 0x181 build/fatfs.o + .debug_abbrev 0x00000b09 0x11e build/fatfs_platform.o + .debug_abbrev 0x00000c27 0x33b build/stm32f7xx_it.o + .debug_abbrev 0x00000f62 0x299 build/stm32f7xx_hal_msp.o + .debug_abbrev 0x000011fb 0x2b6 build/stm32f7xx_hal_adc.o + .debug_abbrev 0x000014b1 0x2d9 build/stm32f7xx_hal_adc_ex.o + .debug_abbrev 0x0000178a 0x306 build/stm32f7xx_hal_rcc.o + .debug_abbrev 0x00001a90 0x1f3 build/stm32f7xx_hal_rcc_ex.o + .debug_abbrev 0x00001c83 0x22b build/stm32f7xx_hal_gpio.o + .debug_abbrev 0x00001eae 0x1d5 build/stm32f7xx_hal_pwr_ex.o + .debug_abbrev 0x00002083 0x3ca build/stm32f7xx_hal_cortex.o + .debug_abbrev 0x0000244d 0x244 build/stm32f7xx_hal.o + .debug_abbrev 0x00002691 0x294 build/stm32f7xx_ll_rcc.o + .debug_abbrev 0x00002925 0x2ad build/stm32f7xx_ll_gpio.o + .debug_abbrev 0x00002bd2 0x236 build/stm32f7xx_ll_sdmmc.o + .debug_abbrev 0x00002e08 0x306 build/stm32f7xx_hal_sd.o + .debug_abbrev 0x0000310e 0x2e3 build/stm32f7xx_ll_spi.o + .debug_abbrev 0x000033f1 0x2bd build/stm32f7xx_hal_tim.o + .debug_abbrev 0x000036ae 0x2b7 build/stm32f7xx_hal_tim_ex.o + .debug_abbrev 0x00003965 0x2af build/stm32f7xx_ll_tim.o + .debug_abbrev 0x00003c14 0x2d3 build/stm32f7xx_ll_usart.o + .debug_abbrev 0x00003ee7 0x12a build/system_stm32f7xx.o + .debug_abbrev 0x00004011 0x307 build/File_Handling.o + .debug_abbrev 0x00004318 0x1ca build/diskio.o + .debug_abbrev 0x000044e2 0x309 build/ff.o + .debug_abbrev 0x000047eb 0x1da build/ff_gen_drv.o + .debug_abbrev 0x000049c5 0xeb build/sysmem.o + .debug_abbrev 0x00004ab0 0x346 build/stm32f7xx_hal_uart.o + .debug_abbrev 0x00004df6 0x1d build/startup_stm32f767xx.o + .debug_abbrev 0x00004e13 0x21c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) + .debug_abbrev 0x0000502f 0x149 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-impure.o) + .debug_abbrev 0x00005178 0x32f /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) + .debug_abbrev 0x000054a7 0xc9 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + .debug_abbrev 0x00005570 0xb7 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + .debug_abbrev 0x00005627 0x15e /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-errno.o) + .debug_abbrev 0x00005785 0x24a /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) + .debug_abbrev 0x000059cf 0x249 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-freer.o) + .debug_abbrev 0x00005c18 0xc3 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memmove.o) + .debug_abbrev 0x00005cdb 0x14 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memchr.o) + .debug_abbrev 0x00005cef 0x28 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy.o) + .debug_abbrev 0x00005d17 0x1cf /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-malloc.o) + .debug_abbrev 0x00005ee6 0x20c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reallocr.o) + .debug_abbrev 0x000060f2 0x284 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-vfprintf_i.o) + .debug_abbrev 0x00006376 0x192 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mlock.o) + .debug_abbrev 0x00006508 0x1da /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sbrkr.o) + .debug_abbrev 0x000066e2 0x196 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-msizer.o) + .debug_abbrev 0x00006878 0x408 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + .debug_abbrev 0x00006c80 0x1ee /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reent.o) + .debug_abbrev 0x00006e6e 0x14 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + .debug_abbrev 0x00006e82 0x16a /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + .debug_abbrev 0x00006fec 0x26 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) + +.debug_loc 0x00000000 0x261ca + .debug_loc 0x00000000 0x2987 build/main.o + .debug_loc 0x00002987 0x6f0 build/bsp_driver_sd.o + .debug_loc 0x00003077 0x544 build/sd_diskio.o + .debug_loc 0x000035bb 0x20 build/fatfs.o + .debug_loc 0x000035db 0x51 build/fatfs_platform.o + .debug_loc 0x0000362c 0x43a build/stm32f7xx_it.o + .debug_loc 0x00003a66 0x5a7 build/stm32f7xx_hal_msp.o + .debug_loc 0x0000400d 0xe7b build/stm32f7xx_hal_adc.o + .debug_loc 0x00004e88 0xc11 build/stm32f7xx_hal_adc_ex.o + .debug_loc 0x00005a99 0x849 build/stm32f7xx_hal_rcc.o + .debug_loc 0x000062e2 0x924 build/stm32f7xx_hal_rcc_ex.o + .debug_loc 0x00006c06 0x60b build/stm32f7xx_hal_gpio.o + .debug_loc 0x00007211 0x3e6 build/stm32f7xx_hal_pwr_ex.o + .debug_loc 0x000075f7 0x886 build/stm32f7xx_hal_cortex.o + .debug_loc 0x00007e7d 0x1f9 build/stm32f7xx_hal.o + .debug_loc 0x00008076 0x1806 build/stm32f7xx_ll_rcc.o + .debug_loc 0x0000987c 0x9ad build/stm32f7xx_ll_gpio.o + .debug_loc 0x0000a229 0x1873 build/stm32f7xx_ll_sdmmc.o + .debug_loc 0x0000ba9c 0x29f6 build/stm32f7xx_hal_sd.o + .debug_loc 0x0000e492 0x6d7 build/stm32f7xx_ll_spi.o + .debug_loc 0x0000eb69 0x6372 build/stm32f7xx_hal_tim.o + .debug_loc 0x00014edb 0x291a build/stm32f7xx_hal_tim_ex.o + .debug_loc 0x000177f5 0x1b79 build/stm32f7xx_ll_tim.o + .debug_loc 0x0001936e 0x8b1 build/stm32f7xx_ll_usart.o + .debug_loc 0x00019c1f 0x181 build/system_stm32f7xx.o + .debug_loc 0x00019da0 0xa9c build/File_Handling.o + .debug_loc 0x0001a83c 0x377 build/diskio.o + .debug_loc 0x0001abb3 0x6040 build/ff.o + .debug_loc 0x00020bf3 0x37c build/ff_gen_drv.o + .debug_loc 0x00020f6f 0x90 build/sysmem.o + .debug_loc 0x00020fff 0x51cb build/stm32f7xx_hal_uart.o + +.debug_aranges 0x00000000 0x1c50 + .debug_aranges + 0x00000000 0x158 build/main.o + .debug_aranges + 0x00000158 0x98 build/bsp_driver_sd.o + .debug_aranges + 0x000001f0 0x48 build/sd_diskio.o + .debug_aranges + 0x00000238 0x28 build/fatfs.o + .debug_aranges + 0x00000260 0x20 build/fatfs_platform.o + .debug_aranges + 0x00000280 0xc0 build/stm32f7xx_it.o + .debug_aranges + 0x00000340 0x68 build/stm32f7xx_hal_msp.o + .debug_aranges + 0x000003a8 0xe8 build/stm32f7xx_hal_adc.o + .debug_aranges + 0x00000490 0x90 build/stm32f7xx_hal_adc_ex.o + .debug_aranges + 0x00000520 0x88 build/stm32f7xx_hal_rcc.o + .debug_aranges + 0x000005a8 0x50 build/stm32f7xx_hal_rcc_ex.o + .debug_aranges + 0x000005f8 0x58 build/stm32f7xx_hal_gpio.o + .debug_aranges + 0x00000650 0x80 build/stm32f7xx_hal_pwr_ex.o + .debug_aranges + 0x000006d0 0xe8 build/stm32f7xx_hal_cortex.o + .debug_aranges + 0x000007b8 0x110 build/stm32f7xx_hal.o + .debug_aranges + 0x000008c8 0xf8 build/stm32f7xx_ll_rcc.o + .debug_aranges + 0x000009c0 0x58 build/stm32f7xx_ll_gpio.o + .debug_aranges + 0x00000a18 0x188 build/stm32f7xx_ll_sdmmc.o + .debug_aranges + 0x00000ba0 0x168 build/stm32f7xx_hal_sd.o + .debug_aranges + 0x00000d08 0x50 build/stm32f7xx_ll_spi.o + .debug_aranges + 0x00000d58 0x3e0 build/stm32f7xx_hal_tim.o + .debug_aranges + 0x00001138 0x180 build/stm32f7xx_hal_tim_ex.o + .debug_aranges + 0x000012b8 0xd0 build/stm32f7xx_ll_tim.o + .debug_aranges + 0x00001388 0x48 build/stm32f7xx_ll_usart.o + .debug_aranges + 0x000013d0 0x28 build/system_stm32f7xx.o + .debug_aranges + 0x000013f8 0x98 build/File_Handling.o + .debug_aranges + 0x00001490 0x48 build/diskio.o + .debug_aranges + 0x000014d8 0x208 build/ff.o + .debug_aranges + 0x000016e0 0x40 build/ff_gen_drv.o + .debug_aranges + 0x00001720 0x20 build/sysmem.o + .debug_aranges + 0x00001740 0x230 build/stm32f7xx_hal_uart.o + .debug_aranges + 0x00001970 0x28 build/startup_stm32f767xx.o + .debug_aranges + 0x00001998 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) + .debug_aranges + 0x000019b8 0x18 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-impure.o) + .debug_aranges + 0x000019d0 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) + .debug_aranges + 0x000019f0 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + .debug_aranges + 0x00001a10 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + .debug_aranges + 0x00001a30 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-errno.o) + .debug_aranges + 0x00001a50 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) + .debug_aranges + 0x00001a70 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-freer.o) + .debug_aranges + 0x00001a90 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memmove.o) + .debug_aranges + 0x00001ab0 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memchr.o) + .debug_aranges + 0x00001ad0 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy.o) + .debug_aranges + 0x00001af0 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-malloc.o) + .debug_aranges + 0x00001b10 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reallocr.o) + .debug_aranges + 0x00001b30 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-vfprintf_i.o) + .debug_aranges + 0x00001b50 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mlock.o) + .debug_aranges + 0x00001b70 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sbrkr.o) + .debug_aranges + 0x00001b90 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-msizer.o) + .debug_aranges + 0x00001bb0 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + .debug_aranges + 0x00001bd0 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reent.o) + .debug_aranges + 0x00001bf0 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + .debug_aranges + 0x00001c10 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + .debug_aranges + 0x00001c30 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) + +.debug_ranges 0x00000000 0x1b90 + .debug_ranges 0x00000000 0x1c0 build/main.o + .debug_ranges 0x000001c0 0x88 build/bsp_driver_sd.o + .debug_ranges 0x00000248 0x38 build/sd_diskio.o + .debug_ranges 0x00000280 0x18 build/fatfs.o + .debug_ranges 0x00000298 0x10 build/fatfs_platform.o + .debug_ranges 0x000002a8 0xb0 build/stm32f7xx_it.o + .debug_ranges 0x00000358 0x58 build/stm32f7xx_hal_msp.o + .debug_ranges 0x000003b0 0xd8 build/stm32f7xx_hal_adc.o + .debug_ranges 0x00000488 0x80 build/stm32f7xx_hal_adc_ex.o + .debug_ranges 0x00000508 0x78 build/stm32f7xx_hal_rcc.o + .debug_ranges 0x00000580 0x40 build/stm32f7xx_hal_rcc_ex.o + .debug_ranges 0x000005c0 0x48 build/stm32f7xx_hal_gpio.o + .debug_ranges 0x00000608 0x70 build/stm32f7xx_hal_pwr_ex.o + .debug_ranges 0x00000678 0xd8 build/stm32f7xx_hal_cortex.o + .debug_ranges 0x00000750 0x100 build/stm32f7xx_hal.o + .debug_ranges 0x00000850 0xe8 build/stm32f7xx_ll_rcc.o + .debug_ranges 0x00000938 0x150 build/stm32f7xx_ll_gpio.o + .debug_ranges 0x00000a88 0x178 build/stm32f7xx_ll_sdmmc.o + .debug_ranges 0x00000c00 0x158 build/stm32f7xx_hal_sd.o + .debug_ranges 0x00000d58 0x58 build/stm32f7xx_ll_spi.o + .debug_ranges 0x00000db0 0x3d0 build/stm32f7xx_hal_tim.o + .debug_ranges 0x00001180 0x170 build/stm32f7xx_hal_tim_ex.o + .debug_ranges 0x000012f0 0x210 build/stm32f7xx_ll_tim.o + .debug_ranges 0x00001500 0x110 build/stm32f7xx_ll_usart.o + .debug_ranges 0x00001610 0x18 build/system_stm32f7xx.o + .debug_ranges 0x00001628 0xa0 build/File_Handling.o + .debug_ranges 0x000016c8 0x38 build/diskio.o + .debug_ranges 0x00001700 0x1f8 build/ff.o + .debug_ranges 0x000018f8 0x30 build/ff_gen_drv.o + .debug_ranges 0x00001928 0x10 build/sysmem.o + .debug_ranges 0x00001938 0x238 build/stm32f7xx_hal_uart.o + .debug_ranges 0x00001b70 0x20 build/startup_stm32f767xx.o + +.debug_line 0x00000000 0x2399e + .debug_line 0x00000000 0x3757 build/main.o + .debug_line 0x00003757 0x39e build/bsp_driver_sd.o + .debug_line 0x00003af5 0x2f2 build/sd_diskio.o + .debug_line 0x00003de7 0x170 build/fatfs.o + .debug_line 0x00003f57 0x111 build/fatfs_platform.o + .debug_line 0x00004068 0x934 build/stm32f7xx_it.o + .debug_line 0x0000499c 0x66d build/stm32f7xx_hal_msp.o + .debug_line 0x00005009 0xfc7 build/stm32f7xx_hal_adc.o + .debug_line 0x00005fd0 0xb34 build/stm32f7xx_hal_adc_ex.o + .debug_line 0x00006b04 0xd15 build/stm32f7xx_hal_rcc.o + .debug_line 0x00007819 0xbd9 build/stm32f7xx_hal_rcc_ex.o + .debug_line 0x000083f2 0x6aa build/stm32f7xx_hal_gpio.o + .debug_line 0x00008a9c 0x52c build/stm32f7xx_hal_pwr_ex.o + .debug_line 0x00008fc8 0x77a build/stm32f7xx_hal_cortex.o + .debug_line 0x00009742 0x548 build/stm32f7xx_hal.o + .debug_line 0x00009c8a 0x1721 build/stm32f7xx_ll_rcc.o + .debug_line 0x0000b3ab 0x76d build/stm32f7xx_ll_gpio.o + .debug_line 0x0000bb18 0x104d build/stm32f7xx_ll_sdmmc.o + .debug_line 0x0000cb65 0x263f build/stm32f7xx_hal_sd.o + .debug_line 0x0000f1a4 0x56b build/stm32f7xx_ll_spi.o + .debug_line 0x0000f70f 0x4839 build/stm32f7xx_hal_tim.o + .debug_line 0x00013f48 0x1bb4 build/stm32f7xx_hal_tim_ex.o + .debug_line 0x00015afc 0xe26 build/stm32f7xx_ll_tim.o + .debug_line 0x00016922 0x62f build/stm32f7xx_ll_usart.o + .debug_line 0x00016f51 0x1c2 build/system_stm32f7xx.o + .debug_line 0x00017113 0xa76 build/File_Handling.o + .debug_line 0x00017b89 0x217 build/diskio.o + .debug_line 0x00017da0 0x42e1 build/ff.o + .debug_line 0x0001c081 0x25a build/ff_gen_drv.o + .debug_line 0x0001c2db 0xf8 build/sysmem.o + .debug_line 0x0001c3d3 0x3f43 build/stm32f7xx_hal_uart.o + .debug_line 0x00020316 0x73 build/startup_stm32f767xx.o + .debug_line 0x00020389 0x224 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) + .debug_line 0x000205ad 0xe7 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-impure.o) + .debug_line 0x00020694 0x854 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) + .debug_line 0x00020ee8 0x11e /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + .debug_line 0x00021006 0x1b6 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + .debug_line 0x000211bc 0x10c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-errno.o) + .debug_line 0x000212c8 0x446 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) + .debug_line 0x0002170e 0x2c3 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-freer.o) + .debug_line 0x000219d1 0x1f1 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memmove.o) + .debug_line 0x00021bc2 0x84 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memchr.o) + .debug_line 0x00021c46 0xb9 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy.o) + .debug_line 0x00021cff 0x16b /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-malloc.o) + .debug_line 0x00021e6a 0x1f8 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reallocr.o) + .debug_line 0x00022062 0x75d /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-vfprintf_i.o) + .debug_line 0x000227bf 0x153 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mlock.o) + .debug_line 0x00022912 0x193 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sbrkr.o) + .debug_line 0x00022aa5 0x176 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-msizer.o) + .debug_line 0x00022c1b 0x4fc /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + .debug_line 0x00023117 0x27b /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reent.o) + .debug_line 0x00023392 0x4e /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + .debug_line 0x000233e0 0x574 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + .debug_line 0x00023954 0x4a /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) + +.debug_str 0x00000000 0x969c + .debug_str 0x00000000 0x969c build/main.o + 0x2d06 (size before relaxing) + .debug_str 0x0000969c 0x8f5 build/bsp_driver_sd.o + .debug_str 0x0000969c 0x3f8 build/sd_diskio.o + .debug_str 0x0000969c 0x3f0 build/fatfs.o + .debug_str 0x0000969c 0x23d build/fatfs_platform.o + .debug_str 0x0000969c 0xed1 build/stm32f7xx_it.o + .debug_str 0x0000969c 0x1975 build/stm32f7xx_hal_msp.o + .debug_str 0x0000969c 0x93c build/stm32f7xx_hal_adc.o + .debug_str 0x0000969c 0x990 build/stm32f7xx_hal_adc_ex.o + .debug_str 0x0000969c 0x714 build/stm32f7xx_hal_rcc.o + .debug_str 0x0000969c 0x72c build/stm32f7xx_hal_rcc_ex.o + .debug_str 0x0000969c 0x4e5 build/stm32f7xx_hal_gpio.o + .debug_str 0x0000969c 0x63f build/stm32f7xx_hal_pwr_ex.o + .debug_str 0x0000969c 0xe66 build/stm32f7xx_hal_cortex.o + .debug_str 0x0000969c 0xd38 build/stm32f7xx_hal.o + .debug_str 0x0000969c 0xbce build/stm32f7xx_ll_rcc.o + .debug_str 0x0000969c 0x499 build/stm32f7xx_ll_gpio.o + .debug_str 0x0000969c 0x7ec build/stm32f7xx_ll_sdmmc.o + .debug_str 0x0000969c 0x10c7 build/stm32f7xx_hal_sd.o + .debug_str 0x0000969c 0x5bf build/stm32f7xx_ll_spi.o + .debug_str 0x0000969c 0x1770 build/stm32f7xx_hal_tim.o + .debug_str 0x0000969c 0x1076 build/stm32f7xx_hal_tim_ex.o + .debug_str 0x0000969c 0x9cb build/stm32f7xx_ll_tim.o + .debug_str 0x0000969c 0x5be build/stm32f7xx_ll_usart.o + .debug_str 0x0000969c 0x449 build/system_stm32f7xx.o + .debug_str 0x0000969c 0x647 build/File_Handling.o + .debug_str 0x0000969c 0x325 build/diskio.o + .debug_str 0x0000969c 0x8bb build/ff.o + .debug_str 0x0000969c 0x376 build/ff_gen_drv.o + .debug_str 0x0000969c 0x213 build/sysmem.o + .debug_str 0x0000969c 0x1014 build/stm32f7xx_hal_uart.o + .debug_str 0x0000969c 0x88 build/startup_stm32f767xx.o + .debug_str 0x0000969c 0x4fe /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) + .debug_str 0x0000969c 0x4bf /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-impure.o) + .debug_str 0x0000969c 0x808 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) + .debug_str 0x0000969c 0x1fd /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + .debug_str 0x0000969c 0x1b0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + .debug_str 0x0000969c 0x4b9 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-errno.o) + .debug_str 0x0000969c 0x5a0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) + .debug_str 0x0000969c 0x53f /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-freer.o) + .debug_str 0x0000969c 0x1cf /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memmove.o) + .debug_str 0x0000969c 0x9e /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memchr.o) + .debug_str 0x0000969c 0xac /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy.o) + .debug_str 0x0000969c 0x4e4 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-malloc.o) + .debug_str 0x0000969c 0x535 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reallocr.o) + .debug_str 0x0000969c 0x79e /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-vfprintf_i.o) + .debug_str 0x0000969c 0x4dd /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mlock.o) + .debug_str 0x0000969c 0x4c8 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sbrkr.o) + .debug_str 0x0000969c 0x508 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-msizer.o) + .debug_str 0x0000969c 0x6c2 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + .debug_str 0x0000969c 0x4de /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reent.o) + .debug_str 0x0000969c 0xa3 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + .debug_str 0x0000969c 0x688 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + .debug_str 0x0000969c 0xc3 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) + +.debug_frame 0x00000000 0x4cd8 + .debug_frame 0x00000000 0x4a4 build/main.o + .debug_frame 0x000004a4 0x180 build/bsp_driver_sd.o + .debug_frame 0x00000624 0xac build/sd_diskio.o + .debug_frame 0x000006d0 0x38 build/fatfs.o + .debug_frame 0x00000708 0x28 build/fatfs_platform.o + .debug_frame 0x00000730 0x1b4 build/stm32f7xx_it.o + .debug_frame 0x000008e4 0x138 build/stm32f7xx_hal_msp.o + .debug_frame 0x00000a1c 0x268 build/stm32f7xx_hal_adc.o + .debug_frame 0x00000c84 0x18c build/stm32f7xx_hal_adc_ex.o + .debug_frame 0x00000e10 0x178 build/stm32f7xx_hal_rcc.o + .debug_frame 0x00000f88 0xc0 build/stm32f7xx_hal_rcc_ex.o + .debug_frame 0x00001048 0xd8 build/stm32f7xx_hal_gpio.o + .debug_frame 0x00001120 0x134 build/stm32f7xx_hal_pwr_ex.o + .debug_frame 0x00001254 0x1ec build/stm32f7xx_hal_cortex.o + .debug_frame 0x00001440 0x22c build/stm32f7xx_hal.o + .debug_frame 0x0000166c 0x250 build/stm32f7xx_ll_rcc.o + .debug_frame 0x000018bc 0xc8 build/stm32f7xx_ll_gpio.o + .debug_frame 0x00001984 0x4c8 build/stm32f7xx_ll_sdmmc.o + .debug_frame 0x00001e4c 0x4b8 build/stm32f7xx_hal_sd.o + .debug_frame 0x00002304 0xa8 build/stm32f7xx_ll_spi.o + .debug_frame 0x000023ac 0xb6c build/stm32f7xx_hal_tim.o + .debug_frame 0x00002f18 0x478 build/stm32f7xx_hal_tim_ex.o + .debug_frame 0x00003390 0x24c build/stm32f7xx_ll_tim.o + .debug_frame 0x000035dc 0x88 build/stm32f7xx_ll_usart.o + .debug_frame 0x00003664 0x30 build/system_stm32f7xx.o + .debug_frame 0x00003694 0x1e8 build/File_Handling.o + .debug_frame 0x0000387c 0xa0 build/diskio.o + .debug_frame 0x0000391c 0x7bc build/ff.o + .debug_frame 0x000040d8 0x7c build/ff_gen_drv.o + .debug_frame 0x00004154 0x28 build/sysmem.o + .debug_frame 0x0000417c 0x608 build/stm32f7xx_hal_uart.o + .debug_frame 0x00004784 0x78 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) + .debug_frame 0x000047fc 0x98 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) + .debug_frame 0x00004894 0x2c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + .debug_frame 0x000048c0 0x2c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + .debug_frame 0x000048ec 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-errno.o) + .debug_frame 0x0000490c 0x50 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) + .debug_frame 0x0000495c 0x58 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-freer.o) + .debug_frame 0x000049b4 0x40 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memmove.o) + .debug_frame 0x000049f4 0x30 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-malloc.o) + .debug_frame 0x00004a24 0x38 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reallocr.o) + .debug_frame 0x00004a5c 0x6c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-vfprintf_i.o) + .debug_frame 0x00004ac8 0x30 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mlock.o) + .debug_frame 0x00004af8 0x2c /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sbrkr.o) + .debug_frame 0x00004b24 0x20 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-msizer.o) + .debug_frame 0x00004b44 0xf4 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + .debug_frame 0x00004c38 0x40 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reent.o) + .debug_frame 0x00004c78 0x2c /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + .debug_frame 0x00004ca4 0x34 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + +.debug_loclists + 0x00000000 0x2087 + .debug_loclists + 0x00000000 0x88 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) + .debug_loclists + 0x00000088 0x56b /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) + .debug_loclists + 0x000005f3 0x65 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + .debug_loclists + 0x00000658 0x1c2 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + .debug_loclists + 0x0000081a 0x263 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) + .debug_loclists + 0x00000a7d 0x164 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-freer.o) + .debug_loclists + 0x00000be1 0x233 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memmove.o) + .debug_loclists + 0x00000e14 0x4a /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-malloc.o) + .debug_loclists + 0x00000e5e 0x102 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reallocr.o) + .debug_loclists + 0x00000f60 0x44f /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-vfprintf_i.o) + .debug_loclists + 0x000013af 0x4b /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sbrkr.o) + .debug_loclists + 0x000013fa 0x59 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-msizer.o) + .debug_loclists + 0x00001453 0x1d0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + .debug_loclists + 0x00001623 0x80 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reent.o) + .debug_loclists + 0x000016a3 0x9e4 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + +.debug_rnglists + 0x00000000 0x1d4 + .debug_rnglists + 0x00000000 0x42 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) + .debug_rnglists + 0x00000042 0x1e /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) + .debug_rnglists + 0x00000060 0x13 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-freer.o) + .debug_rnglists + 0x00000073 0x66 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-vfprintf_i.o) + .debug_rnglists + 0x000000d9 0x77 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + .debug_rnglists + 0x00000150 0x84 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + +.debug_line_str + 0x00000000 0x145 + .debug_line_str + 0x00000000 0x145 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memchr.o) + 0x92 (size before relaxing) + .debug_line_str + 0x00000145 0x99 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy.o) + .debug_line_str + 0x00000145 0x97 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + .debug_line_str + 0x00000145 0x9b /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) + +Cross Reference Table + +Symbol File +ADC_IRQHandler build/stm32f7xx_it.o +AHBPrescTable build/system_stm32f7xx.o + build/stm32f7xx_ll_utils.o + build/stm32f7xx_ll_rcc.o + build/stm32f7xx_hal_rcc.o +APBPrescTable build/system_stm32f7xx.o + build/stm32f7xx_ll_rcc.o + build/stm32f7xx_hal_rcc.o +Advanced_Controller_Temp build/main.o +BSP_PlatformIsDetected build/fatfs_platform.o + build/bsp_driver_sd.o +BSP_SD_AbortCallback build/bsp_driver_sd.o +BSP_SD_Erase build/bsp_driver_sd.o +BSP_SD_GetCardInfo build/bsp_driver_sd.o + build/sd_diskio.o +BSP_SD_GetCardState build/bsp_driver_sd.o + build/sd_diskio.o +BSP_SD_ITConfig build/bsp_driver_sd.o +BSP_SD_Init build/bsp_driver_sd.o + build/sd_diskio.o +BSP_SD_IsDetected build/bsp_driver_sd.o +BSP_SD_ReadBlocks build/bsp_driver_sd.o + build/sd_diskio.o +BSP_SD_ReadBlocks_DMA build/bsp_driver_sd.o +BSP_SD_ReadCpltCallback build/bsp_driver_sd.o +BSP_SD_WriteBlocks build/bsp_driver_sd.o + build/sd_diskio.o +BSP_SD_WriteBlocks_DMA build/bsp_driver_sd.o +BSP_SD_WriteCpltCallback build/bsp_driver_sd.o +BusFault_Handler build/stm32f7xx_it.o +CAN1_RX0_IRQHandler build/startup_stm32f767xx.o +CAN1_RX1_IRQHandler build/startup_stm32f767xx.o +CAN1_SCE_IRQHandler build/startup_stm32f767xx.o +CAN1_TX_IRQHandler build/startup_stm32f767xx.o +CAN2_RX0_IRQHandler build/startup_stm32f767xx.o +CAN2_RX1_IRQHandler build/startup_stm32f767xx.o +CAN2_SCE_IRQHandler build/startup_stm32f767xx.o +CAN2_TX_IRQHandler build/startup_stm32f767xx.o +CAN3_RX0_IRQHandler build/startup_stm32f767xx.o +CAN3_RX1_IRQHandler build/startup_stm32f767xx.o +CAN3_SCE_IRQHandler build/startup_stm32f767xx.o +CAN3_TX_IRQHandler build/startup_stm32f767xx.o +CEC_IRQHandler build/startup_stm32f767xx.o +COMMAND build/main.o + build/stm32f7xx_it.o +CPU_state build/main.o + build/stm32f7xx_it.o +CPU_state_old build/main.o +CS_result build/main.o +CalculateChecksum build/main.o +CheckChecksum build/main.o +Check_SD_Space build/File_Handling.o +Create_Dir build/File_Handling.o +Create_File build/File_Handling.o + build/main.o +Curr_setup build/main.o +DCMI_IRQHandler build/startup_stm32f767xx.o +DFSDM1_FLT0_IRQHandler build/startup_stm32f767xx.o +DFSDM1_FLT1_IRQHandler build/startup_stm32f767xx.o +DFSDM1_FLT2_IRQHandler build/startup_stm32f767xx.o +DFSDM1_FLT3_IRQHandler build/startup_stm32f767xx.o +DMA1_Stream0_IRQHandler build/startup_stm32f767xx.o +DMA1_Stream1_IRQHandler build/startup_stm32f767xx.o +DMA1_Stream2_IRQHandler build/startup_stm32f767xx.o +DMA1_Stream3_IRQHandler build/startup_stm32f767xx.o +DMA1_Stream4_IRQHandler build/startup_stm32f767xx.o +DMA1_Stream5_IRQHandler build/startup_stm32f767xx.o +DMA1_Stream6_IRQHandler build/startup_stm32f767xx.o +DMA1_Stream7_IRQHandler build/startup_stm32f767xx.o +DMA2D_IRQHandler build/startup_stm32f767xx.o +DMA2_Stream0_IRQHandler build/startup_stm32f767xx.o +DMA2_Stream1_IRQHandler build/startup_stm32f767xx.o +DMA2_Stream2_IRQHandler build/startup_stm32f767xx.o +DMA2_Stream3_IRQHandler build/startup_stm32f767xx.o +DMA2_Stream4_IRQHandler build/startup_stm32f767xx.o +DMA2_Stream5_IRQHandler build/startup_stm32f767xx.o +DMA2_Stream6_IRQHandler build/startup_stm32f767xx.o +DMA2_Stream7_IRQHandler build/stm32f7xx_it.o +DMA2_Stream7_TransferComplete build/stm32f7xx_it.o +DebugMon_Handler build/stm32f7xx_it.o +Def_setup build/main.o +Default_Handler build/startup_stm32f767xx.o +ETH_IRQHandler build/startup_stm32f767xx.o +ETH_WKUP_IRQHandler build/startup_stm32f767xx.o +EXTI0_IRQHandler build/startup_stm32f767xx.o +EXTI15_10_IRQHandler build/startup_stm32f767xx.o +EXTI1_IRQHandler build/startup_stm32f767xx.o +EXTI2_IRQHandler build/startup_stm32f767xx.o +EXTI3_IRQHandler build/startup_stm32f767xx.o +EXTI4_IRQHandler build/startup_stm32f767xx.o +EXTI9_5_IRQHandler build/startup_stm32f767xx.o +Error_Handler build/main.o + build/stm32f7xx_hal_msp.o +FATFS_GetAttachedDriversNbr build/ff_gen_drv.o +FATFS_LinkDriver build/ff_gen_drv.o + build/fatfs.o +FATFS_LinkDriverEx build/ff_gen_drv.o +FATFS_UnLinkDriver build/ff_gen_drv.o +FATFS_UnLinkDriverEx build/ff_gen_drv.o +FLASH_Erase_Sector build/stm32f7xx_hal_flash_ex.o + build/stm32f7xx_hal_flash.o +FLASH_IRQHandler build/startup_stm32f767xx.o +FLASH_WaitForLastOperation build/stm32f7xx_hal_flash.o + build/stm32f7xx_hal_flash_ex.o +FMC_IRQHandler build/startup_stm32f767xx.o +FPU_IRQHandler build/startup_stm32f767xx.o +Format_SD build/File_Handling.o +HAL_ADCEx_InjectedConfigChannel build/stm32f7xx_hal_adc_ex.o +HAL_ADCEx_InjectedConvCpltCallback build/stm32f7xx_hal_adc_ex.o + build/stm32f7xx_hal_adc.o +HAL_ADCEx_InjectedGetValue build/stm32f7xx_hal_adc_ex.o +HAL_ADCEx_InjectedPollForConversion build/stm32f7xx_hal_adc_ex.o +HAL_ADCEx_InjectedStart build/stm32f7xx_hal_adc_ex.o +HAL_ADCEx_InjectedStart_IT build/stm32f7xx_hal_adc_ex.o +HAL_ADCEx_InjectedStop build/stm32f7xx_hal_adc_ex.o +HAL_ADCEx_InjectedStop_IT build/stm32f7xx_hal_adc_ex.o +HAL_ADCEx_MultiModeConfigChannel build/stm32f7xx_hal_adc_ex.o +HAL_ADCEx_MultiModeGetValue build/stm32f7xx_hal_adc_ex.o +HAL_ADCEx_MultiModeStart_DMA build/stm32f7xx_hal_adc_ex.o +HAL_ADCEx_MultiModeStop_DMA build/stm32f7xx_hal_adc_ex.o +HAL_ADC_AnalogWDGConfig build/stm32f7xx_hal_adc.o +HAL_ADC_ConfigChannel build/stm32f7xx_hal_adc.o + build/main.o +HAL_ADC_ConvCpltCallback build/stm32f7xx_hal_adc.o + build/stm32f7xx_hal_adc_ex.o +HAL_ADC_ConvHalfCpltCallback build/stm32f7xx_hal_adc.o + build/stm32f7xx_hal_adc_ex.o +HAL_ADC_DeInit build/stm32f7xx_hal_adc.o +HAL_ADC_ErrorCallback build/stm32f7xx_hal_adc.o + build/stm32f7xx_hal_adc_ex.o +HAL_ADC_GetError build/stm32f7xx_hal_adc.o +HAL_ADC_GetState build/stm32f7xx_hal_adc.o +HAL_ADC_GetValue build/stm32f7xx_hal_adc.o + build/main.o +HAL_ADC_IRQHandler build/stm32f7xx_hal_adc.o + build/stm32f7xx_it.o +HAL_ADC_Init build/stm32f7xx_hal_adc.o + build/main.o +HAL_ADC_LevelOutOfWindowCallback build/stm32f7xx_hal_adc.o +HAL_ADC_MspDeInit build/stm32f7xx_hal_msp.o +HAL_ADC_MspInit build/stm32f7xx_hal_msp.o +HAL_ADC_PollForConversion build/stm32f7xx_hal_adc.o + build/main.o +HAL_ADC_PollForEvent build/stm32f7xx_hal_adc.o +HAL_ADC_Start build/stm32f7xx_hal_adc.o + build/main.o +HAL_ADC_Start_DMA build/stm32f7xx_hal_adc.o +HAL_ADC_Start_IT build/stm32f7xx_hal_adc.o +HAL_ADC_Stop build/stm32f7xx_hal_adc.o + build/main.o +HAL_ADC_Stop_DMA build/stm32f7xx_hal_adc.o +HAL_ADC_Stop_IT build/stm32f7xx_hal_adc.o +HAL_DBGMCU_DisableDBGSleepMode build/stm32f7xx_hal.o +HAL_DBGMCU_DisableDBGStandbyMode build/stm32f7xx_hal.o +HAL_DBGMCU_DisableDBGStopMode build/stm32f7xx_hal.o +HAL_DBGMCU_EnableDBGSleepMode build/stm32f7xx_hal.o +HAL_DBGMCU_EnableDBGStandbyMode build/stm32f7xx_hal.o +HAL_DBGMCU_EnableDBGStopMode build/stm32f7xx_hal.o +HAL_DMAEx_ChangeMemory build/stm32f7xx_hal_dma_ex.o +HAL_DMAEx_MultiBufferStart build/stm32f7xx_hal_dma_ex.o +HAL_DMAEx_MultiBufferStart_IT build/stm32f7xx_hal_dma_ex.o +HAL_DMA_Abort build/stm32f7xx_hal_dma.o + build/stm32f7xx_hal_uart.o + build/stm32f7xx_hal_sd.o + build/stm32f7xx_hal_adc_ex.o + build/stm32f7xx_hal_adc.o +HAL_DMA_Abort_IT build/stm32f7xx_hal_dma.o + build/stm32f7xx_hal_uart.o + build/stm32f7xx_hal_tim_ex.o + build/stm32f7xx_hal_tim.o + build/stm32f7xx_hal_sd.o + build/stm32f7xx_hal_i2c.o +HAL_DMA_DeInit build/stm32f7xx_hal_dma.o +HAL_DMA_GetError build/stm32f7xx_hal_dma.o + build/stm32f7xx_hal_uart.o + build/stm32f7xx_hal_sd.o + build/stm32f7xx_hal_i2c.o +HAL_DMA_GetState build/stm32f7xx_hal_dma.o + build/stm32f7xx_hal_i2c.o +HAL_DMA_IRQHandler build/stm32f7xx_hal_dma.o +HAL_DMA_Init build/stm32f7xx_hal_dma.o +HAL_DMA_PollForTransfer build/stm32f7xx_hal_dma.o +HAL_DMA_RegisterCallback build/stm32f7xx_hal_dma.o +HAL_DMA_Start build/stm32f7xx_hal_dma.o +HAL_DMA_Start_IT build/stm32f7xx_hal_dma.o + build/stm32f7xx_hal_uart.o + build/stm32f7xx_hal_tim_ex.o + build/stm32f7xx_hal_tim.o + build/stm32f7xx_hal_sd.o + build/stm32f7xx_hal_i2c.o + build/stm32f7xx_hal_adc_ex.o + build/stm32f7xx_hal_adc.o +HAL_DMA_UnRegisterCallback build/stm32f7xx_hal_dma.o +HAL_DeInit build/stm32f7xx_hal.o +HAL_Delay build/stm32f7xx_hal.o + build/stm32f7xx_hal_sd.o +HAL_DisableCompensationCell build/stm32f7xx_hal.o +HAL_DisableFMCMemorySwapping build/stm32f7xx_hal.o +HAL_DisableMemorySwappingBank build/stm32f7xx_hal.o +HAL_EXTI_ClearConfigLine build/stm32f7xx_hal_exti.o +HAL_EXTI_ClearPending build/stm32f7xx_hal_exti.o +HAL_EXTI_GenerateSWI build/stm32f7xx_hal_exti.o +HAL_EXTI_GetConfigLine build/stm32f7xx_hal_exti.o +HAL_EXTI_GetHandle build/stm32f7xx_hal_exti.o +HAL_EXTI_GetPending build/stm32f7xx_hal_exti.o +HAL_EXTI_IRQHandler build/stm32f7xx_hal_exti.o +HAL_EXTI_RegisterCallback build/stm32f7xx_hal_exti.o +HAL_EXTI_SetConfigLine build/stm32f7xx_hal_exti.o +HAL_EnableCompensationCell build/stm32f7xx_hal.o +HAL_EnableFMCMemorySwapping build/stm32f7xx_hal.o +HAL_EnableMemorySwappingBank build/stm32f7xx_hal.o +HAL_FLASHEx_Erase build/stm32f7xx_hal_flash_ex.o +HAL_FLASHEx_Erase_IT build/stm32f7xx_hal_flash_ex.o +HAL_FLASHEx_OBGetConfig build/stm32f7xx_hal_flash_ex.o +HAL_FLASHEx_OBProgram build/stm32f7xx_hal_flash_ex.o +HAL_FLASH_EndOfOperationCallback build/stm32f7xx_hal_flash.o +HAL_FLASH_GetError build/stm32f7xx_hal_flash.o +HAL_FLASH_IRQHandler build/stm32f7xx_hal_flash.o +HAL_FLASH_Lock build/stm32f7xx_hal_flash.o +HAL_FLASH_OB_Launch build/stm32f7xx_hal_flash.o +HAL_FLASH_OB_Lock build/stm32f7xx_hal_flash.o +HAL_FLASH_OB_Unlock build/stm32f7xx_hal_flash.o +HAL_FLASH_OperationErrorCallback build/stm32f7xx_hal_flash.o +HAL_FLASH_Program build/stm32f7xx_hal_flash.o +HAL_FLASH_Program_IT build/stm32f7xx_hal_flash.o +HAL_FLASH_Unlock build/stm32f7xx_hal_flash.o +HAL_GPIO_DeInit build/stm32f7xx_hal_gpio.o + build/stm32f7xx_hal_msp.o +HAL_GPIO_EXTI_Callback build/stm32f7xx_hal_gpio.o +HAL_GPIO_EXTI_IRQHandler build/stm32f7xx_hal_gpio.o +HAL_GPIO_Init build/stm32f7xx_hal_gpio.o + build/stm32f7xx_hal_rcc.o + build/stm32f7xx_hal_msp.o + build/main.o +HAL_GPIO_LockPin build/stm32f7xx_hal_gpio.o +HAL_GPIO_ReadPin build/stm32f7xx_hal_gpio.o + build/fatfs_platform.o + build/main.o +HAL_GPIO_TogglePin build/stm32f7xx_hal_gpio.o + build/stm32f7xx_it.o +HAL_GPIO_WritePin build/stm32f7xx_hal_gpio.o + build/stm32f7xx_it.o + build/main.o +HAL_GetDEVID build/stm32f7xx_hal.o +HAL_GetHalVersion build/stm32f7xx_hal.o +HAL_GetREVID build/stm32f7xx_hal.o +HAL_GetTick build/stm32f7xx_hal.o + build/stm32f7xx_hal_uart_ex.o + build/stm32f7xx_hal_uart.o + build/stm32f7xx_hal_sd.o + build/stm32f7xx_hal_i2c.o + build/stm32f7xx_hal_pwr_ex.o + build/stm32f7xx_hal_dma.o + build/stm32f7xx_hal_flash.o + build/stm32f7xx_hal_rcc_ex.o + build/stm32f7xx_hal_rcc.o + build/stm32f7xx_hal_adc_ex.o + build/stm32f7xx_hal_adc.o +HAL_GetTickFreq build/stm32f7xx_hal.o +HAL_GetTickPrio build/stm32f7xx_hal.o +HAL_GetUIDw0 build/stm32f7xx_hal.o +HAL_GetUIDw1 build/stm32f7xx_hal.o +HAL_GetUIDw2 build/stm32f7xx_hal.o +HAL_HalfDuplex_EnableReceiver build/stm32f7xx_hal_uart.o +HAL_HalfDuplex_EnableTransmitter build/stm32f7xx_hal_uart.o +HAL_HalfDuplex_Init build/stm32f7xx_hal_uart.o +HAL_I2CEx_ConfigAnalogFilter build/stm32f7xx_hal_i2c_ex.o +HAL_I2CEx_ConfigDigitalFilter build/stm32f7xx_hal_i2c_ex.o +HAL_I2CEx_DisableFastModePlus build/stm32f7xx_hal_i2c_ex.o +HAL_I2CEx_EnableFastModePlus build/stm32f7xx_hal_i2c_ex.o +HAL_I2C_AbortCpltCallback build/stm32f7xx_hal_i2c.o +HAL_I2C_AddrCallback build/stm32f7xx_hal_i2c.o +HAL_I2C_DeInit build/stm32f7xx_hal_i2c.o +HAL_I2C_DisableListen_IT build/stm32f7xx_hal_i2c.o +HAL_I2C_ER_IRQHandler build/stm32f7xx_hal_i2c.o +HAL_I2C_EV_IRQHandler build/stm32f7xx_hal_i2c.o +HAL_I2C_EnableListen_IT build/stm32f7xx_hal_i2c.o +HAL_I2C_ErrorCallback build/stm32f7xx_hal_i2c.o +HAL_I2C_GetError build/stm32f7xx_hal_i2c.o +HAL_I2C_GetMode build/stm32f7xx_hal_i2c.o +HAL_I2C_GetState build/stm32f7xx_hal_i2c.o +HAL_I2C_Init build/stm32f7xx_hal_i2c.o +HAL_I2C_IsDeviceReady build/stm32f7xx_hal_i2c.o +HAL_I2C_ListenCpltCallback build/stm32f7xx_hal_i2c.o +HAL_I2C_MasterRxCpltCallback build/stm32f7xx_hal_i2c.o +HAL_I2C_MasterTxCpltCallback build/stm32f7xx_hal_i2c.o +HAL_I2C_Master_Abort_IT build/stm32f7xx_hal_i2c.o +HAL_I2C_Master_Receive build/stm32f7xx_hal_i2c.o +HAL_I2C_Master_Receive_DMA build/stm32f7xx_hal_i2c.o +HAL_I2C_Master_Receive_IT build/stm32f7xx_hal_i2c.o +HAL_I2C_Master_Seq_Receive_DMA build/stm32f7xx_hal_i2c.o +HAL_I2C_Master_Seq_Receive_IT build/stm32f7xx_hal_i2c.o +HAL_I2C_Master_Seq_Transmit_DMA build/stm32f7xx_hal_i2c.o +HAL_I2C_Master_Seq_Transmit_IT build/stm32f7xx_hal_i2c.o +HAL_I2C_Master_Transmit build/stm32f7xx_hal_i2c.o +HAL_I2C_Master_Transmit_DMA build/stm32f7xx_hal_i2c.o +HAL_I2C_Master_Transmit_IT build/stm32f7xx_hal_i2c.o +HAL_I2C_MemRxCpltCallback build/stm32f7xx_hal_i2c.o +HAL_I2C_MemTxCpltCallback build/stm32f7xx_hal_i2c.o +HAL_I2C_Mem_Read build/stm32f7xx_hal_i2c.o +HAL_I2C_Mem_Read_DMA build/stm32f7xx_hal_i2c.o +HAL_I2C_Mem_Read_IT build/stm32f7xx_hal_i2c.o +HAL_I2C_Mem_Write build/stm32f7xx_hal_i2c.o +HAL_I2C_Mem_Write_DMA build/stm32f7xx_hal_i2c.o +HAL_I2C_Mem_Write_IT build/stm32f7xx_hal_i2c.o +HAL_I2C_MspDeInit build/stm32f7xx_hal_i2c.o +HAL_I2C_MspInit build/stm32f7xx_hal_i2c.o +HAL_I2C_SlaveRxCpltCallback build/stm32f7xx_hal_i2c.o +HAL_I2C_SlaveTxCpltCallback build/stm32f7xx_hal_i2c.o +HAL_I2C_Slave_Receive build/stm32f7xx_hal_i2c.o +HAL_I2C_Slave_Receive_DMA build/stm32f7xx_hal_i2c.o +HAL_I2C_Slave_Receive_IT build/stm32f7xx_hal_i2c.o +HAL_I2C_Slave_Seq_Receive_DMA build/stm32f7xx_hal_i2c.o +HAL_I2C_Slave_Seq_Receive_IT build/stm32f7xx_hal_i2c.o +HAL_I2C_Slave_Seq_Transmit_DMA build/stm32f7xx_hal_i2c.o +HAL_I2C_Slave_Seq_Transmit_IT build/stm32f7xx_hal_i2c.o +HAL_I2C_Slave_Transmit build/stm32f7xx_hal_i2c.o +HAL_I2C_Slave_Transmit_DMA build/stm32f7xx_hal_i2c.o +HAL_I2C_Slave_Transmit_IT build/stm32f7xx_hal_i2c.o +HAL_IncTick build/stm32f7xx_hal.o + build/stm32f7xx_it.o +HAL_Init build/stm32f7xx_hal.o + build/main.o +HAL_InitTick build/stm32f7xx_hal.o + build/stm32f7xx_hal_rcc.o +HAL_LIN_Init build/stm32f7xx_hal_uart.o +HAL_LIN_SendBreak build/stm32f7xx_hal_uart.o +HAL_MPU_ConfigRegion build/stm32f7xx_hal_cortex.o +HAL_MPU_Disable build/stm32f7xx_hal_cortex.o +HAL_MPU_DisableRegion build/stm32f7xx_hal_cortex.o +HAL_MPU_Enable build/stm32f7xx_hal_cortex.o +HAL_MPU_EnableRegion build/stm32f7xx_hal_cortex.o +HAL_MspDeInit build/stm32f7xx_hal.o +HAL_MspInit build/stm32f7xx_hal_msp.o +HAL_MultiProcessorEx_AddressLength_Set build/stm32f7xx_hal_uart_ex.o +HAL_MultiProcessor_DisableMuteMode build/stm32f7xx_hal_uart.o +HAL_MultiProcessor_EnableMuteMode build/stm32f7xx_hal_uart.o +HAL_MultiProcessor_EnterMuteMode build/stm32f7xx_hal_uart.o +HAL_MultiProcessor_Init build/stm32f7xx_hal_uart.o +HAL_NVIC_ClearPendingIRQ build/stm32f7xx_hal_cortex.o +HAL_NVIC_DisableIRQ build/stm32f7xx_hal_cortex.o + build/stm32f7xx_hal_msp.o +HAL_NVIC_EnableIRQ build/stm32f7xx_hal_cortex.o + build/stm32f7xx_hal_msp.o +HAL_NVIC_GetActive build/stm32f7xx_hal_cortex.o +HAL_NVIC_GetPendingIRQ build/stm32f7xx_hal_cortex.o +HAL_NVIC_GetPriority build/stm32f7xx_hal_cortex.o +HAL_NVIC_GetPriorityGrouping build/stm32f7xx_hal_cortex.o +HAL_NVIC_SetPendingIRQ build/stm32f7xx_hal_cortex.o +HAL_NVIC_SetPriority build/stm32f7xx_hal_cortex.o + build/stm32f7xx_hal.o + build/stm32f7xx_hal_msp.o +HAL_NVIC_SetPriorityGrouping build/stm32f7xx_hal_cortex.o + build/stm32f7xx_hal.o +HAL_NVIC_SystemReset build/stm32f7xx_hal_cortex.o +HAL_PWREx_ControlVoltageScaling build/stm32f7xx_hal_pwr_ex.o +HAL_PWREx_DisableBkUpReg build/stm32f7xx_hal_pwr_ex.o +HAL_PWREx_DisableFlashPowerDown build/stm32f7xx_hal_pwr_ex.o +HAL_PWREx_DisableLowRegulatorLowVoltage build/stm32f7xx_hal_pwr_ex.o +HAL_PWREx_DisableMainRegulatorLowVoltage build/stm32f7xx_hal_pwr_ex.o +HAL_PWREx_DisableOverDrive build/stm32f7xx_hal_pwr_ex.o +HAL_PWREx_EnableBkUpReg build/stm32f7xx_hal_pwr_ex.o +HAL_PWREx_EnableFlashPowerDown build/stm32f7xx_hal_pwr_ex.o +HAL_PWREx_EnableLowRegulatorLowVoltage build/stm32f7xx_hal_pwr_ex.o +HAL_PWREx_EnableMainRegulatorLowVoltage build/stm32f7xx_hal_pwr_ex.o +HAL_PWREx_EnableOverDrive build/stm32f7xx_hal_pwr_ex.o + build/main.o +HAL_PWREx_EnterUnderDriveSTOPMode build/stm32f7xx_hal_pwr_ex.o +HAL_PWREx_GetVoltageRange build/stm32f7xx_hal_pwr_ex.o +HAL_PWR_ConfigPVD build/stm32f7xx_hal_pwr.o +HAL_PWR_DeInit build/stm32f7xx_hal_pwr.o +HAL_PWR_DisableBkUpAccess build/stm32f7xx_hal_pwr.o +HAL_PWR_DisablePVD build/stm32f7xx_hal_pwr.o +HAL_PWR_DisableSEVOnPend build/stm32f7xx_hal_pwr.o +HAL_PWR_DisableSleepOnExit build/stm32f7xx_hal_pwr.o +HAL_PWR_DisableWakeUpPin build/stm32f7xx_hal_pwr.o +HAL_PWR_EnableBkUpAccess build/stm32f7xx_hal_pwr.o +HAL_PWR_EnablePVD build/stm32f7xx_hal_pwr.o +HAL_PWR_EnableSEVOnPend build/stm32f7xx_hal_pwr.o +HAL_PWR_EnableSleepOnExit build/stm32f7xx_hal_pwr.o +HAL_PWR_EnableWakeUpPin build/stm32f7xx_hal_pwr.o +HAL_PWR_EnterSLEEPMode build/stm32f7xx_hal_pwr.o +HAL_PWR_EnterSTANDBYMode build/stm32f7xx_hal_pwr.o +HAL_PWR_EnterSTOPMode build/stm32f7xx_hal_pwr.o +HAL_PWR_PVDCallback build/stm32f7xx_hal_pwr.o +HAL_PWR_PVD_IRQHandler build/stm32f7xx_hal_pwr.o +HAL_RCCEx_DisablePLLI2S build/stm32f7xx_hal_rcc_ex.o +HAL_RCCEx_DisablePLLSAI build/stm32f7xx_hal_rcc_ex.o +HAL_RCCEx_EnablePLLI2S build/stm32f7xx_hal_rcc_ex.o +HAL_RCCEx_EnablePLLSAI build/stm32f7xx_hal_rcc_ex.o +HAL_RCCEx_GetPeriphCLKConfig build/stm32f7xx_hal_rcc_ex.o +HAL_RCCEx_GetPeriphCLKFreq build/stm32f7xx_hal_rcc_ex.o +HAL_RCCEx_PeriphCLKConfig build/stm32f7xx_hal_rcc_ex.o + build/stm32f7xx_hal_msp.o + build/main.o +HAL_RCC_CSSCallback build/stm32f7xx_hal_rcc.o +HAL_RCC_ClockConfig build/stm32f7xx_hal_rcc.o + build/main.o +HAL_RCC_DeInit build/stm32f7xx_hal_rcc.o +HAL_RCC_DisableCSS build/stm32f7xx_hal_rcc.o +HAL_RCC_EnableCSS build/stm32f7xx_hal_rcc.o +HAL_RCC_GetClockConfig build/stm32f7xx_hal_rcc.o +HAL_RCC_GetHCLKFreq build/stm32f7xx_hal_rcc.o +HAL_RCC_GetOscConfig build/stm32f7xx_hal_rcc.o +HAL_RCC_GetPCLK1Freq build/stm32f7xx_hal_rcc.o + build/stm32f7xx_hal_uart.o +HAL_RCC_GetPCLK2Freq build/stm32f7xx_hal_rcc.o + build/stm32f7xx_hal_uart.o +HAL_RCC_GetSysClockFreq build/stm32f7xx_hal_rcc.o + build/stm32f7xx_hal_uart.o +HAL_RCC_MCOConfig build/stm32f7xx_hal_rcc.o +HAL_RCC_NMI_IRQHandler build/stm32f7xx_hal_rcc.o +HAL_RCC_OscConfig build/stm32f7xx_hal_rcc.o + build/main.o +HAL_RS485Ex_Init build/stm32f7xx_hal_uart_ex.o +HAL_ResumeTick build/stm32f7xx_hal.o +HAL_SD_Abort build/stm32f7xx_hal_sd.o +HAL_SD_AbortCallback build/bsp_driver_sd.o +HAL_SD_Abort_IT build/stm32f7xx_hal_sd.o +HAL_SD_ConfigWideBusOperation build/stm32f7xx_hal_sd.o + build/bsp_driver_sd.o +HAL_SD_DeInit build/stm32f7xx_hal_sd.o +HAL_SD_Erase build/stm32f7xx_hal_sd.o + build/bsp_driver_sd.o +HAL_SD_ErrorCallback build/stm32f7xx_hal_sd.o +HAL_SD_GetCardCID build/stm32f7xx_hal_sd.o +HAL_SD_GetCardCSD build/stm32f7xx_hal_sd.o +HAL_SD_GetCardInfo build/stm32f7xx_hal_sd.o + build/bsp_driver_sd.o +HAL_SD_GetCardState build/stm32f7xx_hal_sd.o + build/bsp_driver_sd.o +HAL_SD_GetCardStatus build/stm32f7xx_hal_sd.o +HAL_SD_GetError build/stm32f7xx_hal_sd.o +HAL_SD_GetState build/stm32f7xx_hal_sd.o +HAL_SD_IRQHandler build/stm32f7xx_hal_sd.o +HAL_SD_Init build/stm32f7xx_hal_sd.o + build/bsp_driver_sd.o +HAL_SD_InitCard build/stm32f7xx_hal_sd.o +HAL_SD_MspDeInit build/stm32f7xx_hal_msp.o +HAL_SD_MspInit build/stm32f7xx_hal_msp.o +HAL_SD_ReadBlocks build/stm32f7xx_hal_sd.o + build/bsp_driver_sd.o +HAL_SD_ReadBlocks_DMA build/stm32f7xx_hal_sd.o + build/bsp_driver_sd.o +HAL_SD_ReadBlocks_IT build/stm32f7xx_hal_sd.o +HAL_SD_RxCpltCallback build/bsp_driver_sd.o +HAL_SD_TxCpltCallback build/bsp_driver_sd.o +HAL_SD_WriteBlocks build/stm32f7xx_hal_sd.o + build/bsp_driver_sd.o +HAL_SD_WriteBlocks_DMA build/stm32f7xx_hal_sd.o + build/bsp_driver_sd.o +HAL_SD_WriteBlocks_IT build/stm32f7xx_hal_sd.o +HAL_SYSTICK_CLKSourceConfig build/stm32f7xx_hal_cortex.o +HAL_SYSTICK_Callback build/stm32f7xx_hal_cortex.o +HAL_SYSTICK_Config build/stm32f7xx_hal_cortex.o + build/stm32f7xx_hal.o +HAL_SYSTICK_IRQHandler build/stm32f7xx_hal_cortex.o +HAL_SetTickFreq build/stm32f7xx_hal.o +HAL_SuspendTick build/stm32f7xx_hal.o +HAL_TIMEx_Break2Callback build/stm32f7xx_hal_tim_ex.o + build/stm32f7xx_hal_tim.o +HAL_TIMEx_BreakCallback build/stm32f7xx_hal_tim_ex.o + build/stm32f7xx_hal_tim.o +HAL_TIMEx_CommutCallback build/stm32f7xx_hal_tim_ex.o + build/stm32f7xx_hal_tim.o +HAL_TIMEx_CommutHalfCpltCallback build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_ConfigBreakDeadTime build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_ConfigBreakInput build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_ConfigCommutEvent build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_ConfigCommutEvent_DMA build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_ConfigCommutEvent_IT build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_GetChannelNState build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_GroupChannel5 build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_DeInit build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_GetState build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_Init build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_MspDeInit build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_MspInit build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_Start build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_Start_DMA build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_Start_IT build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_Stop build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_Stop_DMA build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_Stop_IT build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_MasterConfigSynchronization build/stm32f7xx_hal_tim_ex.o + build/main.o +HAL_TIMEx_OCN_Start build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_OCN_Start_DMA build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_OCN_Start_IT build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_OCN_Stop build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_OCN_Stop_DMA build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_OCN_Stop_IT build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_OnePulseN_Start build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_OnePulseN_Start_IT build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_OnePulseN_Stop build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_OnePulseN_Stop_IT build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_PWMN_Start build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_PWMN_Start_DMA build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_PWMN_Start_IT build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_PWMN_Stop build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_PWMN_Stop_DMA build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_PWMN_Stop_IT build/stm32f7xx_hal_tim_ex.o +HAL_TIMEx_RemapConfig build/stm32f7xx_hal_tim_ex.o +HAL_TIM_Base_DeInit build/stm32f7xx_hal_tim.o +HAL_TIM_Base_GetState build/stm32f7xx_hal_tim.o +HAL_TIM_Base_Init build/stm32f7xx_hal_tim.o + build/main.o +HAL_TIM_Base_MspDeInit build/stm32f7xx_hal_msp.o +HAL_TIM_Base_MspInit build/stm32f7xx_hal_msp.o +HAL_TIM_Base_Start build/stm32f7xx_hal_tim.o +HAL_TIM_Base_Start_DMA build/stm32f7xx_hal_tim.o +HAL_TIM_Base_Start_IT build/stm32f7xx_hal_tim.o + build/main.o +HAL_TIM_Base_Stop build/stm32f7xx_hal_tim.o + build/main.o +HAL_TIM_Base_Stop_DMA build/stm32f7xx_hal_tim.o +HAL_TIM_Base_Stop_IT build/stm32f7xx_hal_tim.o + build/main.o +HAL_TIM_ConfigClockSource build/stm32f7xx_hal_tim.o + build/main.o +HAL_TIM_ConfigOCrefClear build/stm32f7xx_hal_tim.o +HAL_TIM_ConfigTI1Input build/stm32f7xx_hal_tim.o +HAL_TIM_DMABurstState build/stm32f7xx_hal_tim.o +HAL_TIM_DMABurst_MultiReadStart build/stm32f7xx_hal_tim.o +HAL_TIM_DMABurst_MultiWriteStart build/stm32f7xx_hal_tim.o +HAL_TIM_DMABurst_ReadStart build/stm32f7xx_hal_tim.o +HAL_TIM_DMABurst_ReadStop build/stm32f7xx_hal_tim.o +HAL_TIM_DMABurst_WriteStart build/stm32f7xx_hal_tim.o +HAL_TIM_DMABurst_WriteStop build/stm32f7xx_hal_tim.o +HAL_TIM_Encoder_DeInit build/stm32f7xx_hal_tim.o +HAL_TIM_Encoder_GetState build/stm32f7xx_hal_tim.o +HAL_TIM_Encoder_Init build/stm32f7xx_hal_tim.o +HAL_TIM_Encoder_MspDeInit build/stm32f7xx_hal_tim.o +HAL_TIM_Encoder_MspInit build/stm32f7xx_hal_tim.o +HAL_TIM_Encoder_Start build/stm32f7xx_hal_tim.o +HAL_TIM_Encoder_Start_DMA build/stm32f7xx_hal_tim.o +HAL_TIM_Encoder_Start_IT build/stm32f7xx_hal_tim.o +HAL_TIM_Encoder_Stop build/stm32f7xx_hal_tim.o +HAL_TIM_Encoder_Stop_DMA build/stm32f7xx_hal_tim.o +HAL_TIM_Encoder_Stop_IT build/stm32f7xx_hal_tim.o +HAL_TIM_ErrorCallback build/stm32f7xx_hal_tim.o + build/stm32f7xx_hal_tim_ex.o +HAL_TIM_GenerateEvent build/stm32f7xx_hal_tim.o +HAL_TIM_GetActiveChannel build/stm32f7xx_hal_tim.o +HAL_TIM_GetChannelState build/stm32f7xx_hal_tim.o +HAL_TIM_IC_CaptureCallback build/stm32f7xx_hal_tim.o +HAL_TIM_IC_CaptureHalfCpltCallback build/stm32f7xx_hal_tim.o +HAL_TIM_IC_ConfigChannel build/stm32f7xx_hal_tim.o +HAL_TIM_IC_DeInit build/stm32f7xx_hal_tim.o +HAL_TIM_IC_GetState build/stm32f7xx_hal_tim.o +HAL_TIM_IC_Init build/stm32f7xx_hal_tim.o +HAL_TIM_IC_MspDeInit build/stm32f7xx_hal_tim.o +HAL_TIM_IC_MspInit build/stm32f7xx_hal_tim.o +HAL_TIM_IC_Start build/stm32f7xx_hal_tim.o +HAL_TIM_IC_Start_DMA build/stm32f7xx_hal_tim.o +HAL_TIM_IC_Start_IT build/stm32f7xx_hal_tim.o +HAL_TIM_IC_Stop build/stm32f7xx_hal_tim.o +HAL_TIM_IC_Stop_DMA build/stm32f7xx_hal_tim.o +HAL_TIM_IC_Stop_IT build/stm32f7xx_hal_tim.o +HAL_TIM_IRQHandler build/stm32f7xx_hal_tim.o + build/stm32f7xx_it.o +HAL_TIM_MspPostInit build/stm32f7xx_hal_msp.o + build/main.o +HAL_TIM_OC_ConfigChannel build/stm32f7xx_hal_tim.o +HAL_TIM_OC_DeInit build/stm32f7xx_hal_tim.o +HAL_TIM_OC_DelayElapsedCallback build/stm32f7xx_hal_tim.o +HAL_TIM_OC_GetState build/stm32f7xx_hal_tim.o +HAL_TIM_OC_Init build/stm32f7xx_hal_tim.o +HAL_TIM_OC_MspDeInit build/stm32f7xx_hal_tim.o +HAL_TIM_OC_MspInit build/stm32f7xx_hal_tim.o +HAL_TIM_OC_Start build/stm32f7xx_hal_tim.o +HAL_TIM_OC_Start_DMA build/stm32f7xx_hal_tim.o +HAL_TIM_OC_Start_IT build/stm32f7xx_hal_tim.o +HAL_TIM_OC_Stop build/stm32f7xx_hal_tim.o +HAL_TIM_OC_Stop_DMA build/stm32f7xx_hal_tim.o +HAL_TIM_OC_Stop_IT build/stm32f7xx_hal_tim.o +HAL_TIM_OnePulse_ConfigChannel build/stm32f7xx_hal_tim.o +HAL_TIM_OnePulse_DeInit build/stm32f7xx_hal_tim.o +HAL_TIM_OnePulse_GetState build/stm32f7xx_hal_tim.o +HAL_TIM_OnePulse_Init build/stm32f7xx_hal_tim.o +HAL_TIM_OnePulse_MspDeInit build/stm32f7xx_hal_tim.o +HAL_TIM_OnePulse_MspInit build/stm32f7xx_hal_tim.o +HAL_TIM_OnePulse_Start build/stm32f7xx_hal_tim.o +HAL_TIM_OnePulse_Start_IT build/stm32f7xx_hal_tim.o +HAL_TIM_OnePulse_Stop build/stm32f7xx_hal_tim.o +HAL_TIM_OnePulse_Stop_IT build/stm32f7xx_hal_tim.o +HAL_TIM_PWM_ConfigChannel build/stm32f7xx_hal_tim.o + build/main.o +HAL_TIM_PWM_DeInit build/stm32f7xx_hal_tim.o +HAL_TIM_PWM_GetState build/stm32f7xx_hal_tim.o +HAL_TIM_PWM_Init build/stm32f7xx_hal_tim.o + build/main.o +HAL_TIM_PWM_MspDeInit build/stm32f7xx_hal_tim.o +HAL_TIM_PWM_MspInit build/stm32f7xx_hal_tim.o +HAL_TIM_PWM_PulseFinishedCallback build/stm32f7xx_hal_tim.o + build/stm32f7xx_hal_tim_ex.o +HAL_TIM_PWM_PulseFinishedHalfCpltCallback build/stm32f7xx_hal_tim.o +HAL_TIM_PWM_Start build/stm32f7xx_hal_tim.o + build/main.o +HAL_TIM_PWM_Start_DMA build/stm32f7xx_hal_tim.o +HAL_TIM_PWM_Start_IT build/stm32f7xx_hal_tim.o +HAL_TIM_PWM_Stop build/stm32f7xx_hal_tim.o + build/main.o +HAL_TIM_PWM_Stop_DMA build/stm32f7xx_hal_tim.o +HAL_TIM_PWM_Stop_IT build/stm32f7xx_hal_tim.o +HAL_TIM_PeriodElapsedCallback build/stm32f7xx_hal_tim.o +HAL_TIM_PeriodElapsedHalfCpltCallback build/stm32f7xx_hal_tim.o +HAL_TIM_ReadCapturedValue build/stm32f7xx_hal_tim.o +HAL_TIM_SlaveConfigSynchro build/stm32f7xx_hal_tim.o +HAL_TIM_SlaveConfigSynchro_IT build/stm32f7xx_hal_tim.o +HAL_TIM_TriggerCallback build/stm32f7xx_hal_tim.o +HAL_TIM_TriggerHalfCpltCallback build/stm32f7xx_hal_tim.o +HAL_UARTEx_DisableClockStopMode build/stm32f7xx_hal_uart_ex.o +HAL_UARTEx_DisableStopMode build/stm32f7xx_hal_uart_ex.o +HAL_UARTEx_EnableClockStopMode build/stm32f7xx_hal_uart_ex.o +HAL_UARTEx_EnableStopMode build/stm32f7xx_hal_uart_ex.o +HAL_UARTEx_GetRxEventType build/stm32f7xx_hal_uart_ex.o +HAL_UARTEx_ReceiveToIdle build/stm32f7xx_hal_uart_ex.o +HAL_UARTEx_ReceiveToIdle_DMA build/stm32f7xx_hal_uart_ex.o +HAL_UARTEx_ReceiveToIdle_IT build/stm32f7xx_hal_uart_ex.o +HAL_UARTEx_RxEventCallback build/stm32f7xx_hal_uart.o +HAL_UARTEx_StopModeWakeUpSourceConfig build/stm32f7xx_hal_uart_ex.o +HAL_UARTEx_WakeupCallback build/stm32f7xx_hal_uart.o +HAL_UART_Abort build/stm32f7xx_hal_uart.o +HAL_UART_AbortCpltCallback build/stm32f7xx_hal_uart.o +HAL_UART_AbortReceive build/stm32f7xx_hal_uart.o +HAL_UART_AbortReceiveCpltCallback build/stm32f7xx_hal_uart.o +HAL_UART_AbortReceive_IT build/stm32f7xx_hal_uart.o +HAL_UART_AbortTransmit build/stm32f7xx_hal_uart.o +HAL_UART_AbortTransmitCpltCallback build/stm32f7xx_hal_uart.o +HAL_UART_AbortTransmit_IT build/stm32f7xx_hal_uart.o +HAL_UART_Abort_IT build/stm32f7xx_hal_uart.o +HAL_UART_DMAPause build/stm32f7xx_hal_uart.o +HAL_UART_DMAResume build/stm32f7xx_hal_uart.o +HAL_UART_DMAStop build/stm32f7xx_hal_uart.o +HAL_UART_DeInit build/stm32f7xx_hal_uart.o +HAL_UART_DisableReceiverTimeout build/stm32f7xx_hal_uart.o +HAL_UART_EnableReceiverTimeout build/stm32f7xx_hal_uart.o +HAL_UART_ErrorCallback build/stm32f7xx_hal_uart.o +HAL_UART_GetError build/stm32f7xx_hal_uart.o +HAL_UART_GetState build/stm32f7xx_hal_uart.o +HAL_UART_IRQHandler build/stm32f7xx_hal_uart.o +HAL_UART_Init build/stm32f7xx_hal_uart.o + build/main.o +HAL_UART_MspDeInit build/stm32f7xx_hal_msp.o +HAL_UART_MspInit build/stm32f7xx_hal_msp.o + build/stm32f7xx_hal_uart_ex.o +HAL_UART_Receive build/stm32f7xx_hal_uart.o +HAL_UART_Receive_DMA build/stm32f7xx_hal_uart.o +HAL_UART_Receive_IT build/stm32f7xx_hal_uart.o +HAL_UART_ReceiverTimeout_Config build/stm32f7xx_hal_uart.o +HAL_UART_RxCpltCallback build/stm32f7xx_hal_uart.o +HAL_UART_RxHalfCpltCallback build/stm32f7xx_hal_uart.o +HAL_UART_Transmit build/stm32f7xx_hal_uart.o +HAL_UART_Transmit_DMA build/stm32f7xx_hal_uart.o +HAL_UART_Transmit_IT build/stm32f7xx_hal_uart.o +HAL_UART_TxCpltCallback build/stm32f7xx_hal_uart.o +HAL_UART_TxHalfCpltCallback build/stm32f7xx_hal_uart.o +HardFault_Handler build/stm32f7xx_it.o +I2C1_ER_IRQHandler build/startup_stm32f767xx.o +I2C1_EV_IRQHandler build/startup_stm32f767xx.o +I2C2_ER_IRQHandler build/startup_stm32f767xx.o +I2C2_EV_IRQHandler build/startup_stm32f767xx.o +I2C3_ER_IRQHandler build/startup_stm32f767xx.o +I2C3_EV_IRQHandler build/startup_stm32f767xx.o +I2C4_ER_IRQHandler build/startup_stm32f767xx.o +I2C4_EV_IRQHandler build/startup_stm32f767xx.o +JPEG_IRQHandler build/startup_stm32f767xx.o +LD1_curr_setup build/main.o +LD1_def_setup build/main.o +LD1_param build/main.o +LD2_curr_setup build/main.o +LD2_def_setup build/main.o +LD2_param build/main.o +LD_blinker build/main.o + build/stm32f7xx_it.o +LL_DMA_DeInit build/stm32f7xx_ll_dma.o +LL_DMA_Init build/stm32f7xx_ll_dma.o +LL_DMA_StructInit build/stm32f7xx_ll_dma.o +LL_EXTI_DeInit build/stm32f7xx_ll_exti.o +LL_EXTI_Init build/stm32f7xx_ll_exti.o +LL_EXTI_StructInit build/stm32f7xx_ll_exti.o +LL_GPIO_DeInit build/stm32f7xx_ll_gpio.o +LL_GPIO_Init build/stm32f7xx_ll_gpio.o + build/main.o +LL_GPIO_StructInit build/stm32f7xx_ll_gpio.o +LL_I2S_ConfigPrescaler build/stm32f7xx_ll_spi.o +LL_I2S_DeInit build/stm32f7xx_ll_spi.o +LL_I2S_Init build/stm32f7xx_ll_spi.o +LL_I2S_StructInit build/stm32f7xx_ll_spi.o +LL_Init1msTick build/stm32f7xx_ll_utils.o +LL_PLL_ConfigSystemClock_HSE build/stm32f7xx_ll_utils.o +LL_PLL_ConfigSystemClock_HSI build/stm32f7xx_ll_utils.o +LL_RCC_DeInit build/stm32f7xx_ll_rcc.o +LL_RCC_GetCECClockFreq build/stm32f7xx_ll_rcc.o +LL_RCC_GetDFSDMAudioClockFreq build/stm32f7xx_ll_rcc.o +LL_RCC_GetDFSDMClockFreq build/stm32f7xx_ll_rcc.o +LL_RCC_GetI2CClockFreq build/stm32f7xx_ll_rcc.o +LL_RCC_GetI2SClockFreq build/stm32f7xx_ll_rcc.o + build/stm32f7xx_ll_spi.o +LL_RCC_GetLPTIMClockFreq build/stm32f7xx_ll_rcc.o +LL_RCC_GetLTDCClockFreq build/stm32f7xx_ll_rcc.o +LL_RCC_GetRNGClockFreq build/stm32f7xx_ll_rcc.o +LL_RCC_GetSAIClockFreq build/stm32f7xx_ll_rcc.o +LL_RCC_GetSDMMCClockFreq build/stm32f7xx_ll_rcc.o +LL_RCC_GetSPDIFRXClockFreq build/stm32f7xx_ll_rcc.o +LL_RCC_GetSystemClocksFreq build/stm32f7xx_ll_rcc.o +LL_RCC_GetUARTClockFreq build/stm32f7xx_ll_rcc.o + build/stm32f7xx_ll_usart.o +LL_RCC_GetUSARTClockFreq build/stm32f7xx_ll_rcc.o + build/stm32f7xx_ll_usart.o +LL_RCC_GetUSBClockFreq build/stm32f7xx_ll_rcc.o +LL_SPI_DeInit build/stm32f7xx_ll_spi.o +LL_SPI_Init build/stm32f7xx_ll_spi.o + build/main.o +LL_SPI_StructInit build/stm32f7xx_ll_spi.o +LL_SetFlashLatency build/stm32f7xx_ll_utils.o +LL_SetSystemCoreClock build/stm32f7xx_ll_utils.o +LL_TIM_BDTR_Init build/stm32f7xx_ll_tim.o +LL_TIM_BDTR_StructInit build/stm32f7xx_ll_tim.o +LL_TIM_DeInit build/stm32f7xx_ll_tim.o +LL_TIM_ENCODER_Init build/stm32f7xx_ll_tim.o +LL_TIM_ENCODER_StructInit build/stm32f7xx_ll_tim.o +LL_TIM_HALLSENSOR_Init build/stm32f7xx_ll_tim.o +LL_TIM_HALLSENSOR_StructInit build/stm32f7xx_ll_tim.o +LL_TIM_IC_Init build/stm32f7xx_ll_tim.o +LL_TIM_IC_StructInit build/stm32f7xx_ll_tim.o +LL_TIM_Init build/stm32f7xx_ll_tim.o + build/main.o +LL_TIM_OC_Init build/stm32f7xx_ll_tim.o +LL_TIM_OC_StructInit build/stm32f7xx_ll_tim.o +LL_TIM_StructInit build/stm32f7xx_ll_tim.o +LL_USART_ClockInit build/stm32f7xx_ll_usart.o +LL_USART_ClockStructInit build/stm32f7xx_ll_usart.o +LL_USART_DeInit build/stm32f7xx_ll_usart.o +LL_USART_Init build/stm32f7xx_ll_usart.o + build/main.o +LL_USART_StructInit build/stm32f7xx_ll_usart.o +LL_mDelay build/stm32f7xx_ll_utils.o +LPTIM1_IRQHandler build/startup_stm32f767xx.o +LTDC_ER_IRQHandler build/startup_stm32f767xx.o +LTDC_IRQHandler build/startup_stm32f767xx.o +Long_Data build/main.o +MDIOS_IRQHandler build/startup_stm32f767xx.o +MX_FATFS_Init build/fatfs.o + build/main.o +MemManage_Handler build/stm32f7xx_it.o +Mount_SD build/File_Handling.o + build/main.o +NMI_Handler build/stm32f7xx_it.o +OTG_FS_IRQHandler build/startup_stm32f767xx.o +OTG_FS_WKUP_IRQHandler build/startup_stm32f767xx.o +OTG_HS_EP1_IN_IRQHandler build/startup_stm32f767xx.o +OTG_HS_EP1_OUT_IRQHandler build/startup_stm32f767xx.o +OTG_HS_IRQHandler build/startup_stm32f767xx.o +OTG_HS_WKUP_IRQHandler build/startup_stm32f767xx.o +PVD_IRQHandler build/startup_stm32f767xx.o +PendSV_Handler build/stm32f7xx_it.o +QUADSPI_IRQHandler build/startup_stm32f767xx.o +RCC_GetHCLKClockFreq build/stm32f7xx_ll_rcc.o +RCC_GetPCLK1ClockFreq build/stm32f7xx_ll_rcc.o +RCC_GetPCLK2ClockFreq build/stm32f7xx_ll_rcc.o +RCC_GetSystemClockFreq build/stm32f7xx_ll_rcc.o +RCC_IRQHandler build/startup_stm32f767xx.o +RCC_PLLI2S_GetFreqDomain_I2S build/stm32f7xx_ll_rcc.o +RCC_PLLI2S_GetFreqDomain_SAI build/stm32f7xx_ll_rcc.o +RCC_PLLI2S_GetFreqDomain_SPDIFRX build/stm32f7xx_ll_rcc.o +RCC_PLLSAI_GetFreqDomain_48M build/stm32f7xx_ll_rcc.o +RCC_PLLSAI_GetFreqDomain_LTDC build/stm32f7xx_ll_rcc.o +RCC_PLLSAI_GetFreqDomain_SAI build/stm32f7xx_ll_rcc.o +RCC_PLL_GetFreqDomain_48M build/stm32f7xx_ll_rcc.o +RCC_PLL_GetFreqDomain_SYS build/stm32f7xx_ll_rcc.o +RNG_IRQHandler build/startup_stm32f767xx.o +RTC_Alarm_IRQHandler build/startup_stm32f767xx.o +RTC_WKUP_IRQHandler build/startup_stm32f767xx.o +Read_File build/File_Handling.o +Remove_File build/File_Handling.o + build/main.o +Reset_Handler build/startup_stm32f767xx.o +SAI1_IRQHandler build/startup_stm32f767xx.o +SAI2_IRQHandler build/startup_stm32f767xx.o +SDFatFS build/fatfs.o +SDFile build/fatfs.o +SDMMC1_IRQHandler build/startup_stm32f767xx.o +SDMMC2_IRQHandler build/startup_stm32f767xx.o +SDMMC_CmdAppCommand build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdAppOperCommand build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdBlockLength build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdBusWidth build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdErase build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdEraseEndAdd build/stm32f7xx_ll_sdmmc.o +SDMMC_CmdEraseStartAdd build/stm32f7xx_ll_sdmmc.o +SDMMC_CmdGoIdleState build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdOpCondition build/stm32f7xx_ll_sdmmc.o +SDMMC_CmdOperCond build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdReadMultiBlock build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdReadSingleBlock build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdSDEraseEndAdd build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdSDEraseStartAdd build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdSelDesel build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdSendCID build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdSendCSD build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdSendEXTCSD build/stm32f7xx_ll_sdmmc.o +SDMMC_CmdSendSCR build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdSendStatus build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdSetRelAdd build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdSetRelAddMmc build/stm32f7xx_ll_sdmmc.o +SDMMC_CmdStatusRegister build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdStopTransfer build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdSwitch build/stm32f7xx_ll_sdmmc.o +SDMMC_CmdWriteMultiBlock build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_CmdWriteSingleBlock build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_ConfigData build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_GetCmdResp1 build/stm32f7xx_ll_sdmmc.o +SDMMC_GetCmdResp2 build/stm32f7xx_ll_sdmmc.o +SDMMC_GetCmdResp3 build/stm32f7xx_ll_sdmmc.o +SDMMC_GetCmdResp6 build/stm32f7xx_ll_sdmmc.o +SDMMC_GetCmdResp7 build/stm32f7xx_ll_sdmmc.o +SDMMC_GetCommandResponse build/stm32f7xx_ll_sdmmc.o +SDMMC_GetDataCounter build/stm32f7xx_ll_sdmmc.o +SDMMC_GetFIFOCount build/stm32f7xx_ll_sdmmc.o +SDMMC_GetPowerState build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_GetResponse build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_Init build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_PowerState_OFF build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_PowerState_ON build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_ReadFIFO build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDMMC_SendCommand build/stm32f7xx_ll_sdmmc.o +SDMMC_SetSDMMCReadWaitMode build/stm32f7xx_ll_sdmmc.o +SDMMC_WriteFIFO build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_hal_sd.o +SDPath build/fatfs.o +SD_Driver build/sd_diskio.o + build/fatfs.o +SD_READ build/main.o +SD_REMOVE build/main.o +SD_SAVE build/main.o +SD_SEEK build/main.o +SD_SLIDE build/main.o +SD_initialize build/sd_diskio.o +SD_ioctl build/sd_diskio.o +SD_read build/sd_diskio.o +SD_status build/sd_diskio.o +SD_write build/sd_diskio.o +SPDIF_RX_IRQHandler build/startup_stm32f767xx.o +SPI1_IRQHandler build/startup_stm32f767xx.o +SPI2_IRQHandler build/startup_stm32f767xx.o +SPI3_IRQHandler build/startup_stm32f767xx.o +SPI4_IRQHandler build/startup_stm32f767xx.o +SPI5_IRQHandler build/startup_stm32f767xx.o +SPI6_IRQHandler build/startup_stm32f767xx.o +SVC_Handler build/stm32f7xx_it.o +Scan_SD build/File_Handling.o +Seek_Read_File build/File_Handling.o + build/main.o +Send_Uart build/File_Handling.o +Set_LTEC build/main.o + build/stm32f7xx_it.o +State_Data build/main.o + build/stm32f7xx_it.o +SysTick_Handler build/stm32f7xx_it.o +SystemClock_Config build/main.o +SystemCoreClock build/system_stm32f7xx.o + build/stm32f7xx_ll_sdmmc.o + build/stm32f7xx_ll_utils.o + build/stm32f7xx_hal.o + build/stm32f7xx_hal_dma.o + build/stm32f7xx_hal_rcc.o + build/stm32f7xx_hal_adc_ex.o + build/stm32f7xx_hal_adc.o +SystemCoreClockUpdate build/system_stm32f7xx.o +SystemInit build/system_stm32f7xx.o + build/startup_stm32f767xx.o +TAMP_STAMP_IRQHandler build/startup_stm32f767xx.o +TIM10_coflag build/main.o + build/stm32f7xx_it.o +TIM10_period build/main.o +TIM1_BRK_TIM9_IRQHandler build/startup_stm32f767xx.o +TIM1_CC_IRQHandler build/startup_stm32f767xx.o +TIM1_TRG_COM_TIM11_IRQHandler build/stm32f7xx_it.o +TIM1_UP_TIM10_IRQHandler build/stm32f7xx_it.o +TIM2_IRQHandler build/stm32f7xx_it.o +TIM3_IRQHandler build/startup_stm32f767xx.o +TIM4_IRQHandler build/startup_stm32f767xx.o +TIM5_IRQHandler build/stm32f7xx_it.o +TIM6_DAC_IRQHandler build/stm32f7xx_it.o +TIM7_IRQHandler build/stm32f7xx_it.o +TIM8_BRK_TIM12_IRQHandler build/startup_stm32f767xx.o +TIM8_CC_IRQHandler build/startup_stm32f767xx.o +TIM8_TRG_COM_TIM14_IRQHandler build/startup_stm32f767xx.o +TIM8_UP_TIM13_IRQHandler build/stm32f7xx_it.o +TIMEx_DMACommutationCplt build/stm32f7xx_hal_tim_ex.o + build/stm32f7xx_hal_tim.o +TIMEx_DMACommutationHalfCplt build/stm32f7xx_hal_tim_ex.o + build/stm32f7xx_hal_tim.o +TIM_Base_SetConfig build/stm32f7xx_hal_tim.o + build/stm32f7xx_hal_tim_ex.o +TIM_CCxChannelCmd build/stm32f7xx_hal_tim.o + build/stm32f7xx_hal_tim_ex.o +TIM_DMACaptureCplt build/stm32f7xx_hal_tim.o + build/stm32f7xx_hal_tim_ex.o +TIM_DMACaptureHalfCplt build/stm32f7xx_hal_tim.o + build/stm32f7xx_hal_tim_ex.o +TIM_DMADelayPulseHalfCplt build/stm32f7xx_hal_tim.o + build/stm32f7xx_hal_tim_ex.o +TIM_DMAError build/stm32f7xx_hal_tim.o + build/stm32f7xx_hal_tim_ex.o +TIM_ETR_SetConfig build/stm32f7xx_hal_tim.o +TIM_OC2_SetConfig build/stm32f7xx_hal_tim.o + build/stm32f7xx_hal_tim_ex.o +TIM_TI1_SetConfig build/stm32f7xx_hal_tim.o + build/stm32f7xx_hal_tim_ex.o +TO10 build/main.o + build/stm32f7xx_it.o +TO10_counter build/main.o + build/stm32f7xx_it.o +TO6 build/main.o + build/stm32f7xx_it.o +TO6_before build/main.o +TO6_stop build/main.o +TO6_uart build/main.o + build/stm32f7xx_it.o +TO7 build/main.o + build/stm32f7xx_it.o +TO7_PID build/main.o +TO7_before build/main.o +UART4_IRQHandler build/startup_stm32f767xx.o +UART5_IRQHandler build/startup_stm32f767xx.o +UART7_IRQHandler build/startup_stm32f767xx.o +UART8_IRQHandler build/startup_stm32f767xx.o +UART_AdvFeatureConfig build/stm32f7xx_hal_uart.o + build/stm32f7xx_hal_uart_ex.o +UART_CheckIdleState build/stm32f7xx_hal_uart.o + build/stm32f7xx_hal_uart_ex.o +UART_DATA build/main.o +UART_RxCpltCallback build/stm32f7xx_it.o +UART_SetConfig build/stm32f7xx_hal_uart.o + build/stm32f7xx_hal_uart_ex.o +UART_Start_Receive_DMA build/stm32f7xx_hal_uart.o + build/stm32f7xx_hal_uart_ex.o +UART_Start_Receive_IT build/stm32f7xx_hal_uart.o + build/stm32f7xx_hal_uart_ex.o +UART_WaitOnFlagUntilTimeout build/stm32f7xx_hal_uart.o + build/stm32f7xx_hal_uart_ex.o +UART_header build/main.o + build/stm32f7xx_it.o +UART_rec_incr build/main.o + build/stm32f7xx_it.o +UART_transmission_request build/main.o + build/stm32f7xx_it.o +USART1_IRQHandler build/stm32f7xx_it.o +USART2_IRQHandler build/startup_stm32f767xx.o +USART3_IRQHandler build/startup_stm32f767xx.o +USART6_IRQHandler build/startup_stm32f767xx.o +USART_TX build/main.o +USART_TX_DMA build/main.o +Unmount_SD build/File_Handling.o + build/main.o +Update_File build/File_Handling.o +Update_File_byte build/File_Handling.o + build/main.o +Update_File_float build/File_Handling.o +UsageFault_Handler build/stm32f7xx_it.o +WWDG_IRQHandler build/startup_stm32f767xx.o +Write_File build/File_Handling.o +Write_File_byte build/File_Handling.o + build/main.o +_ITM_deregisterTMCloneTable /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o +_ITM_registerTMCloneTable /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o +_Min_Stack_Size build/sysmem.o +__TMC_END__ /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtend.o + /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o +__aeabi_idiv0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) +__aeabi_ldiv0 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) +__aeabi_uldivmod /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + build/stm32f7xx_hal_rcc.o +__atexit /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__call_atexit.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) +__atexit0 /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) +__atexit_dummy /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) +__bss_end__ /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +__bss_start__ /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +__call_exitprocs /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__call_atexit.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-exit.o) +__deregister_frame_info /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o +__dso_handle /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o +__env build/syscalls.o +__errno /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-errno.o) + build/syscalls.o + build/sysmem.o +__fini_array_end /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fini.o) +__fini_array_start /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fini.o) +__fp_lock_all /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) +__fp_unlock_all /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) +__init_array_end /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) +__init_array_start /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) +__io_getchar build/syscalls.o +__io_putchar build/syscalls.o +__libc_fini_array /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fini.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +__libc_init_array /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + build/startup_stm32f767xx.o + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +__malloc_free_list /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-freer.o) +__malloc_lock /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mlock.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-freer.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) +__malloc_sbrk_start /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) +__malloc_unlock /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mlock.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-freer.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) +__on_exit_args /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) +__preinit_array_end /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) +__preinit_array_start /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) +__register_exitproc /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-atexit.o) +__register_frame_info /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crtbegin.o +__sclose /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) +__seofread /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) +__sf /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-impure.o) +__sflush_r /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) +__sfp /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) +__sfp_lock_acquire /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) +__sfp_lock_release /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) +__sglue /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) +__sinit /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) +__sread /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) +__sseek /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) +__ssprint_r /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) +__ssputs_r /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) +__stack /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +__stdio_exit_handler /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-exit.o) +__swrite /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) +__udivmoddi4 /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) +_close build/syscalls.o + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-closer.o) +_close_r /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-closer.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) +_ebss build/startup_stm32f767xx.o +_edata build/startup_stm32f767xx.o +_end build/sysmem.o +_estack build/startup_stm32f767xx.o + build/sysmem.o +_execve build/syscalls.o +_exit build/syscalls.o + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-exit.o) +_fflush_r /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) +_fini /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crti.o + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fini.o) +_fork build/syscalls.o +_free_r /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-freer.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reent.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reallocr.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-malloc.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) +_fstat build/syscalls.o +_fwalk_sglue /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fwalk.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) +_getpid build/syscalls.o +_impure_data /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-impure.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) +_impure_ptr /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-impure.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reent.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-malloc.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-errno.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) +_init /usr/lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+dp/hard/crti.o + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) +_isatty build/syscalls.o +_kill build/syscalls.o +_link build/syscalls.o +_lseek build/syscalls.o + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-lseekr.o) +_lseek_r /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-lseekr.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) +_mainCRTStartup /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +_malloc_r /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reallocr.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-malloc.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) +_malloc_usable_size_r /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-msizer.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reallocr.o) +_open build/syscalls.o +_printf_common /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-vfprintf_i.o) +_printf_float /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) +_printf_i /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-vfprintf_i.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) +_read build/syscalls.o + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-readr.o) +_read_r /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-readr.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) +_realloc_r /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reallocr.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) +_reclaim_reent /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reent.o) +_sbrk build/sysmem.o + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sbrkr.o) +_sbrk_r /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sbrkr.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-mallocr.o) +_sbss build/startup_stm32f767xx.o +_sdata build/startup_stm32f767xx.o +_sidata build/startup_stm32f767xx.o +_siprintf_r /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) +_sprintf_r /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) +_stack_init /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +_start /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +_stat build/syscalls.o +_svfiprintf_r /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) +_svfprintf_r /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) +_times build/syscalls.o +_unlink build/syscalls.o +_wait build/syscalls.o +_write build/syscalls.o + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-writer.o) +_write_r /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-writer.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-stdio.o) +atexit /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-atexit.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +br build/File_Handling.o +bw build/File_Handling.o +disk build/ff_gen_drv.o + build/diskio.o +disk_initialize build/diskio.o + build/ff.o +disk_ioctl build/diskio.o + build/ff.o +disk_read build/diskio.o + build/ff.o +disk_status build/diskio.o + build/ff.o +disk_write build/diskio.o + build/ff.o +environ build/syscalls.o +errno /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reent.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-writer.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-lseekr.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-readr.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-closer.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sbrkr.o) +exit /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-exit.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +f_close build/ff.o + build/File_Handling.o +f_closedir build/ff.o + build/File_Handling.o +f_getfree build/ff.o + build/File_Handling.o +f_gets build/ff.o +f_lseek build/ff.o + build/File_Handling.o +f_mkdir build/ff.o + build/File_Handling.o +f_mkfs build/ff.o +f_mount build/ff.o + build/File_Handling.o +f_open build/ff.o + build/File_Handling.o +f_opendir build/ff.o + build/File_Handling.o +f_printf build/ff.o +f_putc build/ff.o +f_puts build/ff.o +f_read build/ff.o + build/File_Handling.o +f_readdir build/ff.o + build/File_Handling.o +f_rename build/ff.o +f_stat build/ff.o + build/File_Handling.o +f_sync build/ff.o +f_truncate build/ff.o +f_unlink build/ff.o + build/File_Handling.o +f_write build/ff.o + build/File_Handling.o +fflush /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-fflush.o) +fgoto build/main.o +fil build/File_Handling.o +flg_tmt build/main.o + build/stm32f7xx_it.o +fno build/File_Handling.o +fre_clust build/File_Handling.o +free /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-malloc.o) + build/File_Handling.o +free_space build/File_Handling.o +fresult build/main.o + build/File_Handling.o +fs build/File_Handling.o +g_pfnVectors build/startup_stm32f767xx.o +get_fattime build/fatfs.o + build/ff.o +hadc1 build/main.o + build/stm32f7xx_it.o +hadc3 build/main.o + build/stm32f7xx_it.o +hardware_init_hook /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +hsd1 build/main.o + build/bsp_driver_sd.o +htim10 build/main.o + build/stm32f7xx_it.o +htim11 build/main.o + build/stm32f7xx_it.o +htim4 build/main.o +htim8 build/main.o + build/stm32f7xx_it.o +huart8 build/main.o +initialise_monitor_handles build/syscalls.o +main build/main.o + build/startup_stm32f767xx.o + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +malloc /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-malloc.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-__atexit.o) + build/File_Handling.o +memchr /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memchr.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-vfprintf_i.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) +memcpy /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-reallocr.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) +memmove /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memmove.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-nano-svfprintf.o) +memset /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-findfp.o) + build/stm32f7xx_hal_msp.o + build/main.o + /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +pFlash build/stm32f7xx_hal_flash.o + build/stm32f7xx_hal_flash_ex.o +pfs build/File_Handling.o +retSD build/fatfs.o +siprintf /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) +sizeoffile build/main.o + build/File_Handling.o +software_init_hook /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +sprintf /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-sprintf.o) + build/File_Handling.o +strcmp /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcmp.o) + build/File_Handling.o +strcpy /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strcpy.o) + build/File_Handling.o +strlen /usr/lib/gcc/arm-none-eabi/13.2.1/../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-strlen.o) + build/File_Handling.o +task build/main.o +temp16 build/main.o +temp32 build/main.o +test build/main.o +total build/File_Handling.o +u_rx_flg build/main.o +u_tx_flg build/main.o + build/stm32f7xx_it.o +uart_buf build/main.o + build/stm32f7xx_it.o +uwTick build/stm32f7xx_hal.o +uwTickFreq build/stm32f7xx_hal.o +uwTickPrio build/stm32f7xx_hal.o + build/stm32f7xx_hal_rcc.o diff --git a/build/bsp_driver_sd.d b/build/bsp_driver_sd.d new file mode 100644 index 0000000..4a6ac82 --- /dev/null +++ b/build/bsp_driver_sd.d @@ -0,0 +1,70 @@ +build/bsp_driver_sd.o: Src/bsp_driver_sd.c Inc/bsp_driver_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + Inc/fatfs_platform.h +Inc/bsp_driver_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +Inc/fatfs_platform.h: diff --git a/build/bsp_driver_sd.lst b/build/bsp_driver_sd.lst new file mode 100644 index 0000000..fcd788c --- /dev/null +++ b/build/bsp_driver_sd.lst @@ -0,0 +1,1072 @@ +ARM GAS /tmp/ccwhiVas.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "bsp_driver_sd.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Src/bsp_driver_sd.c" + 19 .section .text.BSP_SD_ITConfig,"ax",%progbits + 20 .align 1 + 21 .weak BSP_SD_ITConfig + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 BSP_SD_ITConfig: + 27 .LFB142: + 1:Src/bsp_driver_sd.c **** /* USER CODE BEGIN Header */ + 2:Src/bsp_driver_sd.c **** /** + 3:Src/bsp_driver_sd.c **** ****************************************************************************** + 4:Src/bsp_driver_sd.c **** * @file bsp_driver_sd.c for F7 (based on stm32756g_eval_sd.c) + 5:Src/bsp_driver_sd.c **** * @brief This file includes a generic uSD card driver. + 6:Src/bsp_driver_sd.c **** * To be completed by the user according to the board used for the project. + 7:Src/bsp_driver_sd.c **** * @note Some functions generated as weak: they can be overridden by + 8:Src/bsp_driver_sd.c **** * - code in user files + 9:Src/bsp_driver_sd.c **** * - or BSP code from the FW pack files + 10:Src/bsp_driver_sd.c **** * if such files are added to the generated project (by the user). + 11:Src/bsp_driver_sd.c **** ****************************************************************************** + 12:Src/bsp_driver_sd.c **** * @attention + 13:Src/bsp_driver_sd.c **** * + 14:Src/bsp_driver_sd.c **** * Copyright (c) 2023 STMicroelectronics. + 15:Src/bsp_driver_sd.c **** * All rights reserved. + 16:Src/bsp_driver_sd.c **** * + 17:Src/bsp_driver_sd.c **** * This software is licensed under terms that can be found in the LICENSE file + 18:Src/bsp_driver_sd.c **** * in the root directory of this software component. + 19:Src/bsp_driver_sd.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 20:Src/bsp_driver_sd.c **** * + 21:Src/bsp_driver_sd.c **** ****************************************************************************** + 22:Src/bsp_driver_sd.c **** */ + 23:Src/bsp_driver_sd.c **** /* USER CODE END Header */ + 24:Src/bsp_driver_sd.c **** + 25:Src/bsp_driver_sd.c **** #ifdef OLD_API + 26:Src/bsp_driver_sd.c **** /* kept to avoid issue when migrating old projects. */ + 27:Src/bsp_driver_sd.c **** /* USER CODE BEGIN 0 */ + 28:Src/bsp_driver_sd.c **** + 29:Src/bsp_driver_sd.c **** /* USER CODE END 0 */ + 30:Src/bsp_driver_sd.c **** #else + 31:Src/bsp_driver_sd.c **** /* USER CODE BEGIN FirstSection */ + ARM GAS /tmp/ccwhiVas.s page 2 + + + 32:Src/bsp_driver_sd.c **** /* can be used to modify / undefine following code or add new definitions */ + 33:Src/bsp_driver_sd.c **** /* USER CODE END FirstSection */ + 34:Src/bsp_driver_sd.c **** /* Includes ------------------------------------------------------------------*/ + 35:Src/bsp_driver_sd.c **** #include "bsp_driver_sd.h" + 36:Src/bsp_driver_sd.c **** + 37:Src/bsp_driver_sd.c **** /* Extern variables ---------------------------------------------------------*/ + 38:Src/bsp_driver_sd.c **** + 39:Src/bsp_driver_sd.c **** extern SD_HandleTypeDef hsd1; + 40:Src/bsp_driver_sd.c **** + 41:Src/bsp_driver_sd.c **** /* USER CODE BEGIN BeforeInitSection */ + 42:Src/bsp_driver_sd.c **** /* can be used to modify / undefine following code or add code */ + 43:Src/bsp_driver_sd.c **** /* USER CODE END BeforeInitSection */ + 44:Src/bsp_driver_sd.c **** /** + 45:Src/bsp_driver_sd.c **** * @brief Initializes the SD card device. + 46:Src/bsp_driver_sd.c **** * @retval SD status + 47:Src/bsp_driver_sd.c **** */ + 48:Src/bsp_driver_sd.c **** __weak uint8_t BSP_SD_Init(void) + 49:Src/bsp_driver_sd.c **** { + 50:Src/bsp_driver_sd.c **** uint8_t sd_state = MSD_OK; + 51:Src/bsp_driver_sd.c **** /* Check if the SD card is plugged in the slot */ + 52:Src/bsp_driver_sd.c **** if (BSP_SD_IsDetected() != SD_PRESENT) + 53:Src/bsp_driver_sd.c **** { + 54:Src/bsp_driver_sd.c **** return MSD_ERROR_SD_NOT_PRESENT; + 55:Src/bsp_driver_sd.c **** } + 56:Src/bsp_driver_sd.c **** /* HAL SD initialization */ + 57:Src/bsp_driver_sd.c **** sd_state = HAL_SD_Init(&hsd1); + 58:Src/bsp_driver_sd.c **** /* Configure SD Bus width (4 bits mode selected) */ + 59:Src/bsp_driver_sd.c **** if (sd_state == MSD_OK) + 60:Src/bsp_driver_sd.c **** { + 61:Src/bsp_driver_sd.c **** /* Enable wide operation */ + 62:Src/bsp_driver_sd.c **** if (HAL_SD_ConfigWideBusOperation(&hsd1, SDMMC_BUS_WIDE_4B) != HAL_OK) + 63:Src/bsp_driver_sd.c **** { + 64:Src/bsp_driver_sd.c **** sd_state = MSD_ERROR; + 65:Src/bsp_driver_sd.c **** } + 66:Src/bsp_driver_sd.c **** } + 67:Src/bsp_driver_sd.c **** + 68:Src/bsp_driver_sd.c **** return sd_state; + 69:Src/bsp_driver_sd.c **** } + 70:Src/bsp_driver_sd.c **** /* USER CODE BEGIN AfterInitSection */ + 71:Src/bsp_driver_sd.c **** /* can be used to modify previous code / undefine following code / add code */ + 72:Src/bsp_driver_sd.c **** /* USER CODE END AfterInitSection */ + 73:Src/bsp_driver_sd.c **** + 74:Src/bsp_driver_sd.c **** /* USER CODE BEGIN InterruptMode */ + 75:Src/bsp_driver_sd.c **** /** + 76:Src/bsp_driver_sd.c **** * @brief Configures Interrupt mode for SD detection pin. + 77:Src/bsp_driver_sd.c **** * @retval Returns 0 + 78:Src/bsp_driver_sd.c **** */ + 79:Src/bsp_driver_sd.c **** __weak uint8_t BSP_SD_ITConfig(void) + 80:Src/bsp_driver_sd.c **** { + 28 .loc 1 80 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 81:Src/bsp_driver_sd.c **** /* Code to be updated by the user or replaced by one from the FW pack (in a stmxxxx_sd.c file) */ + 82:Src/bsp_driver_sd.c **** + 83:Src/bsp_driver_sd.c **** return (uint8_t)0; + ARM GAS /tmp/ccwhiVas.s page 3 + + + 33 .loc 1 83 3 view .LVU1 + 84:Src/bsp_driver_sd.c **** } + 34 .loc 1 84 1 is_stmt 0 view .LVU2 + 35 0000 0020 movs r0, #0 + 36 0002 7047 bx lr + 37 .cfi_endproc + 38 .LFE142: + 40 .section .text.BSP_SD_ReadBlocks,"ax",%progbits + 41 .align 1 + 42 .weak BSP_SD_ReadBlocks + 43 .syntax unified + 44 .thumb + 45 .thumb_func + 47 BSP_SD_ReadBlocks: + 48 .LVL0: + 49 .LFB143: + 85:Src/bsp_driver_sd.c **** + 86:Src/bsp_driver_sd.c **** /* USER CODE END InterruptMode */ + 87:Src/bsp_driver_sd.c **** + 88:Src/bsp_driver_sd.c **** /* USER CODE BEGIN BeforeReadBlocksSection */ + 89:Src/bsp_driver_sd.c **** /* can be used to modify previous code / undefine following code / add code */ + 90:Src/bsp_driver_sd.c **** /* USER CODE END BeforeReadBlocksSection */ + 91:Src/bsp_driver_sd.c **** /** + 92:Src/bsp_driver_sd.c **** * @brief Reads block(s) from a specified address in an SD card, in polling mode. + 93:Src/bsp_driver_sd.c **** * @param pData: Pointer to the buffer that will contain the data to transmit + 94:Src/bsp_driver_sd.c **** * @param ReadAddr: Address from where data is to be read + 95:Src/bsp_driver_sd.c **** * @param NumOfBlocks: Number of SD blocks to read + 96:Src/bsp_driver_sd.c **** * @param Timeout: Timeout for read operation + 97:Src/bsp_driver_sd.c **** * @retval SD status + 98:Src/bsp_driver_sd.c **** */ + 99:Src/bsp_driver_sd.c **** __weak uint8_t BSP_SD_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t + 100:Src/bsp_driver_sd.c **** { + 50 .loc 1 100 1 is_stmt 1 view -0 + 51 .cfi_startproc + 52 @ args = 0, pretend = 0, frame = 0 + 53 @ frame_needed = 0, uses_anonymous_args = 0 + 54 .loc 1 100 1 is_stmt 0 view .LVU4 + 55 0000 00B5 push {lr} + 56 .LCFI0: + 57 .cfi_def_cfa_offset 4 + 58 .cfi_offset 14, -4 + 59 0002 83B0 sub sp, sp, #12 + 60 .LCFI1: + 61 .cfi_def_cfa_offset 16 + 101:Src/bsp_driver_sd.c **** uint8_t sd_state = MSD_OK; + 62 .loc 1 101 3 is_stmt 1 view .LVU5 + 63 .LVL1: + 102:Src/bsp_driver_sd.c **** + 103:Src/bsp_driver_sd.c **** if (HAL_SD_ReadBlocks(&hsd1, (uint8_t *)pData, ReadAddr, NumOfBlocks, Timeout) != HAL_OK) + 64 .loc 1 103 3 view .LVU6 + 65 .loc 1 103 7 is_stmt 0 view .LVU7 + 66 0004 0093 str r3, [sp] + 67 0006 1346 mov r3, r2 + 68 .LVL2: + 69 .loc 1 103 7 view .LVU8 + 70 0008 0A46 mov r2, r1 + 71 .LVL3: + ARM GAS /tmp/ccwhiVas.s page 4 + + + 72 .loc 1 103 7 view .LVU9 + 73 000a 0146 mov r1, r0 + 74 .LVL4: + 75 .loc 1 103 7 view .LVU10 + 76 000c 0348 ldr r0, .L6 + 77 .LVL5: + 78 .loc 1 103 7 view .LVU11 + 79 000e FFF7FEFF bl HAL_SD_ReadBlocks + 80 .LVL6: + 81 .loc 1 103 6 discriminator 1 view .LVU12 + 82 0012 00B1 cbz r0, .L3 + 104:Src/bsp_driver_sd.c **** { + 105:Src/bsp_driver_sd.c **** sd_state = MSD_ERROR; + 83 .loc 1 105 14 view .LVU13 + 84 0014 0120 movs r0, #1 + 85 .L3: + 86 .LVL7: + 106:Src/bsp_driver_sd.c **** } + 107:Src/bsp_driver_sd.c **** + 108:Src/bsp_driver_sd.c **** return sd_state; + 87 .loc 1 108 3 is_stmt 1 view .LVU14 + 109:Src/bsp_driver_sd.c **** } + 88 .loc 1 109 1 is_stmt 0 view .LVU15 + 89 0016 03B0 add sp, sp, #12 + 90 .LCFI2: + 91 .cfi_def_cfa_offset 4 + 92 @ sp needed + 93 0018 5DF804FB ldr pc, [sp], #4 + 94 .L7: + 95 .align 2 + 96 .L6: + 97 001c 00000000 .word hsd1 + 98 .cfi_endproc + 99 .LFE143: + 101 .section .text.BSP_SD_WriteBlocks,"ax",%progbits + 102 .align 1 + 103 .weak BSP_SD_WriteBlocks + 104 .syntax unified + 105 .thumb + 106 .thumb_func + 108 BSP_SD_WriteBlocks: + 109 .LVL8: + 110 .LFB144: + 110:Src/bsp_driver_sd.c **** + 111:Src/bsp_driver_sd.c **** /* USER CODE BEGIN BeforeWriteBlocksSection */ + 112:Src/bsp_driver_sd.c **** /* can be used to modify previous code / undefine following code / add code */ + 113:Src/bsp_driver_sd.c **** /* USER CODE END BeforeWriteBlocksSection */ + 114:Src/bsp_driver_sd.c **** /** + 115:Src/bsp_driver_sd.c **** * @brief Writes block(s) to a specified address in an SD card, in polling mode. + 116:Src/bsp_driver_sd.c **** * @param pData: Pointer to the buffer that will contain the data to transmit + 117:Src/bsp_driver_sd.c **** * @param WriteAddr: Address from where data is to be written + 118:Src/bsp_driver_sd.c **** * @param NumOfBlocks: Number of SD blocks to write + 119:Src/bsp_driver_sd.c **** * @param Timeout: Timeout for write operation + 120:Src/bsp_driver_sd.c **** * @retval SD status + 121:Src/bsp_driver_sd.c **** */ + 122:Src/bsp_driver_sd.c **** __weak uint8_t BSP_SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32 + 123:Src/bsp_driver_sd.c **** { + ARM GAS /tmp/ccwhiVas.s page 5 + + + 111 .loc 1 123 1 is_stmt 1 view -0 + 112 .cfi_startproc + 113 @ args = 0, pretend = 0, frame = 0 + 114 @ frame_needed = 0, uses_anonymous_args = 0 + 115 .loc 1 123 1 is_stmt 0 view .LVU17 + 116 0000 00B5 push {lr} + 117 .LCFI3: + 118 .cfi_def_cfa_offset 4 + 119 .cfi_offset 14, -4 + 120 0002 83B0 sub sp, sp, #12 + 121 .LCFI4: + 122 .cfi_def_cfa_offset 16 + 124:Src/bsp_driver_sd.c **** uint8_t sd_state = MSD_OK; + 123 .loc 1 124 3 is_stmt 1 view .LVU18 + 124 .LVL9: + 125:Src/bsp_driver_sd.c **** + 126:Src/bsp_driver_sd.c **** if (HAL_SD_WriteBlocks(&hsd1, (uint8_t *)pData, WriteAddr, NumOfBlocks, Timeout) != HAL_OK) + 125 .loc 1 126 3 view .LVU19 + 126 .loc 1 126 7 is_stmt 0 view .LVU20 + 127 0004 0093 str r3, [sp] + 128 0006 1346 mov r3, r2 + 129 .LVL10: + 130 .loc 1 126 7 view .LVU21 + 131 0008 0A46 mov r2, r1 + 132 .LVL11: + 133 .loc 1 126 7 view .LVU22 + 134 000a 0146 mov r1, r0 + 135 .LVL12: + 136 .loc 1 126 7 view .LVU23 + 137 000c 0348 ldr r0, .L12 + 138 .LVL13: + 139 .loc 1 126 7 view .LVU24 + 140 000e FFF7FEFF bl HAL_SD_WriteBlocks + 141 .LVL14: + 142 .loc 1 126 6 discriminator 1 view .LVU25 + 143 0012 00B1 cbz r0, .L9 + 127:Src/bsp_driver_sd.c **** { + 128:Src/bsp_driver_sd.c **** sd_state = MSD_ERROR; + 144 .loc 1 128 14 view .LVU26 + 145 0014 0120 movs r0, #1 + 146 .L9: + 147 .LVL15: + 129:Src/bsp_driver_sd.c **** } + 130:Src/bsp_driver_sd.c **** + 131:Src/bsp_driver_sd.c **** return sd_state; + 148 .loc 1 131 3 is_stmt 1 view .LVU27 + 132:Src/bsp_driver_sd.c **** } + 149 .loc 1 132 1 is_stmt 0 view .LVU28 + 150 0016 03B0 add sp, sp, #12 + 151 .LCFI5: + 152 .cfi_def_cfa_offset 4 + 153 @ sp needed + 154 0018 5DF804FB ldr pc, [sp], #4 + 155 .L13: + 156 .align 2 + 157 .L12: + 158 001c 00000000 .word hsd1 + ARM GAS /tmp/ccwhiVas.s page 6 + + + 159 .cfi_endproc + 160 .LFE144: + 162 .section .text.BSP_SD_ReadBlocks_DMA,"ax",%progbits + 163 .align 1 + 164 .weak BSP_SD_ReadBlocks_DMA + 165 .syntax unified + 166 .thumb + 167 .thumb_func + 169 BSP_SD_ReadBlocks_DMA: + 170 .LVL16: + 171 .LFB145: + 133:Src/bsp_driver_sd.c **** + 134:Src/bsp_driver_sd.c **** /* USER CODE BEGIN BeforeReadDMABlocksSection */ + 135:Src/bsp_driver_sd.c **** /* can be used to modify previous code / undefine following code / add code */ + 136:Src/bsp_driver_sd.c **** /* USER CODE END BeforeReadDMABlocksSection */ + 137:Src/bsp_driver_sd.c **** /** + 138:Src/bsp_driver_sd.c **** * @brief Reads block(s) from a specified address in an SD card, in DMA mode. + 139:Src/bsp_driver_sd.c **** * @param pData: Pointer to the buffer that will contain the data to transmit + 140:Src/bsp_driver_sd.c **** * @param ReadAddr: Address from where data is to be read + 141:Src/bsp_driver_sd.c **** * @param NumOfBlocks: Number of SD blocks to read + 142:Src/bsp_driver_sd.c **** * @retval SD status + 143:Src/bsp_driver_sd.c **** */ + 144:Src/bsp_driver_sd.c **** __weak uint8_t BSP_SD_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks) + 145:Src/bsp_driver_sd.c **** { + 172 .loc 1 145 1 is_stmt 1 view -0 + 173 .cfi_startproc + 174 @ args = 0, pretend = 0, frame = 0 + 175 @ frame_needed = 0, uses_anonymous_args = 0 + 176 .loc 1 145 1 is_stmt 0 view .LVU30 + 177 0000 08B5 push {r3, lr} + 178 .LCFI6: + 179 .cfi_def_cfa_offset 8 + 180 .cfi_offset 3, -8 + 181 .cfi_offset 14, -4 + 182 0002 1346 mov r3, r2 + 146:Src/bsp_driver_sd.c **** uint8_t sd_state = MSD_OK; + 183 .loc 1 146 3 is_stmt 1 view .LVU31 + 184 .LVL17: + 147:Src/bsp_driver_sd.c **** + 148:Src/bsp_driver_sd.c **** /* Read block(s) in DMA transfer mode */ + 149:Src/bsp_driver_sd.c **** if (HAL_SD_ReadBlocks_DMA(&hsd1, (uint8_t *)pData, ReadAddr, NumOfBlocks) != HAL_OK) + 185 .loc 1 149 3 view .LVU32 + 186 .loc 1 149 7 is_stmt 0 view .LVU33 + 187 0004 0A46 mov r2, r1 + 188 .LVL18: + 189 .loc 1 149 7 view .LVU34 + 190 0006 0146 mov r1, r0 + 191 .LVL19: + 192 .loc 1 149 7 view .LVU35 + 193 0008 0248 ldr r0, .L18 + 194 .LVL20: + 195 .loc 1 149 7 view .LVU36 + 196 000a FFF7FEFF bl HAL_SD_ReadBlocks_DMA + 197 .LVL21: + 198 .loc 1 149 6 discriminator 1 view .LVU37 + 199 000e 00B1 cbz r0, .L15 + 150:Src/bsp_driver_sd.c **** { + ARM GAS /tmp/ccwhiVas.s page 7 + + + 151:Src/bsp_driver_sd.c **** sd_state = MSD_ERROR; + 200 .loc 1 151 14 view .LVU38 + 201 0010 0120 movs r0, #1 + 202 .L15: + 203 .LVL22: + 152:Src/bsp_driver_sd.c **** } + 153:Src/bsp_driver_sd.c **** + 154:Src/bsp_driver_sd.c **** return sd_state; + 204 .loc 1 154 3 is_stmt 1 view .LVU39 + 155:Src/bsp_driver_sd.c **** } + 205 .loc 1 155 1 is_stmt 0 view .LVU40 + 206 0012 08BD pop {r3, pc} + 207 .L19: + 208 .align 2 + 209 .L18: + 210 0014 00000000 .word hsd1 + 211 .cfi_endproc + 212 .LFE145: + 214 .section .text.BSP_SD_WriteBlocks_DMA,"ax",%progbits + 215 .align 1 + 216 .weak BSP_SD_WriteBlocks_DMA + 217 .syntax unified + 218 .thumb + 219 .thumb_func + 221 BSP_SD_WriteBlocks_DMA: + 222 .LVL23: + 223 .LFB146: + 156:Src/bsp_driver_sd.c **** + 157:Src/bsp_driver_sd.c **** /* USER CODE BEGIN BeforeWriteDMABlocksSection */ + 158:Src/bsp_driver_sd.c **** /* can be used to modify previous code / undefine following code / add code */ + 159:Src/bsp_driver_sd.c **** /* USER CODE END BeforeWriteDMABlocksSection */ + 160:Src/bsp_driver_sd.c **** /** + 161:Src/bsp_driver_sd.c **** * @brief Writes block(s) to a specified address in an SD card, in DMA mode. + 162:Src/bsp_driver_sd.c **** * @param pData: Pointer to the buffer that will contain the data to transmit + 163:Src/bsp_driver_sd.c **** * @param WriteAddr: Address from where data is to be written + 164:Src/bsp_driver_sd.c **** * @param NumOfBlocks: Number of SD blocks to write + 165:Src/bsp_driver_sd.c **** * @retval SD status + 166:Src/bsp_driver_sd.c **** */ + 167:Src/bsp_driver_sd.c **** __weak uint8_t BSP_SD_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks) + 168:Src/bsp_driver_sd.c **** { + 224 .loc 1 168 1 is_stmt 1 view -0 + 225 .cfi_startproc + 226 @ args = 0, pretend = 0, frame = 0 + 227 @ frame_needed = 0, uses_anonymous_args = 0 + 228 .loc 1 168 1 is_stmt 0 view .LVU42 + 229 0000 08B5 push {r3, lr} + 230 .LCFI7: + 231 .cfi_def_cfa_offset 8 + 232 .cfi_offset 3, -8 + 233 .cfi_offset 14, -4 + 234 0002 1346 mov r3, r2 + 169:Src/bsp_driver_sd.c **** uint8_t sd_state = MSD_OK; + 235 .loc 1 169 3 is_stmt 1 view .LVU43 + 236 .LVL24: + 170:Src/bsp_driver_sd.c **** + 171:Src/bsp_driver_sd.c **** /* Write block(s) in DMA transfer mode */ + 172:Src/bsp_driver_sd.c **** if (HAL_SD_WriteBlocks_DMA(&hsd1, (uint8_t *)pData, WriteAddr, NumOfBlocks) != HAL_OK) + ARM GAS /tmp/ccwhiVas.s page 8 + + + 237 .loc 1 172 3 view .LVU44 + 238 .loc 1 172 7 is_stmt 0 view .LVU45 + 239 0004 0A46 mov r2, r1 + 240 .LVL25: + 241 .loc 1 172 7 view .LVU46 + 242 0006 0146 mov r1, r0 + 243 .LVL26: + 244 .loc 1 172 7 view .LVU47 + 245 0008 0248 ldr r0, .L24 + 246 .LVL27: + 247 .loc 1 172 7 view .LVU48 + 248 000a FFF7FEFF bl HAL_SD_WriteBlocks_DMA + 249 .LVL28: + 250 .loc 1 172 6 discriminator 1 view .LVU49 + 251 000e 00B1 cbz r0, .L21 + 173:Src/bsp_driver_sd.c **** { + 174:Src/bsp_driver_sd.c **** sd_state = MSD_ERROR; + 252 .loc 1 174 14 view .LVU50 + 253 0010 0120 movs r0, #1 + 254 .L21: + 255 .LVL29: + 175:Src/bsp_driver_sd.c **** } + 176:Src/bsp_driver_sd.c **** + 177:Src/bsp_driver_sd.c **** return sd_state; + 256 .loc 1 177 3 is_stmt 1 view .LVU51 + 178:Src/bsp_driver_sd.c **** } + 257 .loc 1 178 1 is_stmt 0 view .LVU52 + 258 0012 08BD pop {r3, pc} + 259 .L25: + 260 .align 2 + 261 .L24: + 262 0014 00000000 .word hsd1 + 263 .cfi_endproc + 264 .LFE146: + 266 .section .text.BSP_SD_Erase,"ax",%progbits + 267 .align 1 + 268 .weak BSP_SD_Erase + 269 .syntax unified + 270 .thumb + 271 .thumb_func + 273 BSP_SD_Erase: + 274 .LVL30: + 275 .LFB147: + 179:Src/bsp_driver_sd.c **** + 180:Src/bsp_driver_sd.c **** /* USER CODE BEGIN BeforeEraseSection */ + 181:Src/bsp_driver_sd.c **** /* can be used to modify previous code / undefine following code / add code */ + 182:Src/bsp_driver_sd.c **** /* USER CODE END BeforeEraseSection */ + 183:Src/bsp_driver_sd.c **** /** + 184:Src/bsp_driver_sd.c **** * @brief Erases the specified memory area of the given SD card. + 185:Src/bsp_driver_sd.c **** * @param StartAddr: Start byte address + 186:Src/bsp_driver_sd.c **** * @param EndAddr: End byte address + 187:Src/bsp_driver_sd.c **** * @retval SD status + 188:Src/bsp_driver_sd.c **** */ + 189:Src/bsp_driver_sd.c **** __weak uint8_t BSP_SD_Erase(uint32_t StartAddr, uint32_t EndAddr) + 190:Src/bsp_driver_sd.c **** { + 276 .loc 1 190 1 is_stmt 1 view -0 + 277 .cfi_startproc + ARM GAS /tmp/ccwhiVas.s page 9 + + + 278 @ args = 0, pretend = 0, frame = 0 + 279 @ frame_needed = 0, uses_anonymous_args = 0 + 280 .loc 1 190 1 is_stmt 0 view .LVU54 + 281 0000 08B5 push {r3, lr} + 282 .LCFI8: + 283 .cfi_def_cfa_offset 8 + 284 .cfi_offset 3, -8 + 285 .cfi_offset 14, -4 + 286 0002 0A46 mov r2, r1 + 191:Src/bsp_driver_sd.c **** uint8_t sd_state = MSD_OK; + 287 .loc 1 191 3 is_stmt 1 view .LVU55 + 288 .LVL31: + 192:Src/bsp_driver_sd.c **** + 193:Src/bsp_driver_sd.c **** if (HAL_SD_Erase(&hsd1, StartAddr, EndAddr) != HAL_OK) + 289 .loc 1 193 3 view .LVU56 + 290 .loc 1 193 7 is_stmt 0 view .LVU57 + 291 0004 0146 mov r1, r0 + 292 .LVL32: + 293 .loc 1 193 7 view .LVU58 + 294 0006 0348 ldr r0, .L30 + 295 .LVL33: + 296 .loc 1 193 7 view .LVU59 + 297 0008 FFF7FEFF bl HAL_SD_Erase + 298 .LVL34: + 299 .loc 1 193 6 discriminator 1 view .LVU60 + 300 000c 00B1 cbz r0, .L27 + 194:Src/bsp_driver_sd.c **** { + 195:Src/bsp_driver_sd.c **** sd_state = MSD_ERROR; + 301 .loc 1 195 14 view .LVU61 + 302 000e 0120 movs r0, #1 + 303 .L27: + 304 .LVL35: + 196:Src/bsp_driver_sd.c **** } + 197:Src/bsp_driver_sd.c **** + 198:Src/bsp_driver_sd.c **** return sd_state; + 305 .loc 1 198 3 is_stmt 1 view .LVU62 + 199:Src/bsp_driver_sd.c **** } + 306 .loc 1 199 1 is_stmt 0 view .LVU63 + 307 0010 08BD pop {r3, pc} + 308 .L31: + 309 0012 00BF .align 2 + 310 .L30: + 311 0014 00000000 .word hsd1 + 312 .cfi_endproc + 313 .LFE147: + 315 .section .text.BSP_SD_GetCardState,"ax",%progbits + 316 .align 1 + 317 .weak BSP_SD_GetCardState + 318 .syntax unified + 319 .thumb + 320 .thumb_func + 322 BSP_SD_GetCardState: + 323 .LFB148: + 200:Src/bsp_driver_sd.c **** + 201:Src/bsp_driver_sd.c **** /* USER CODE BEGIN BeforeGetCardStateSection */ + 202:Src/bsp_driver_sd.c **** /* can be used to modify previous code / undefine following code / add code */ + 203:Src/bsp_driver_sd.c **** /* USER CODE END BeforeGetCardStateSection */ + ARM GAS /tmp/ccwhiVas.s page 10 + + + 204:Src/bsp_driver_sd.c **** + 205:Src/bsp_driver_sd.c **** /** + 206:Src/bsp_driver_sd.c **** * @brief Gets the current SD card data status. + 207:Src/bsp_driver_sd.c **** * @param None + 208:Src/bsp_driver_sd.c **** * @retval Data transfer state. + 209:Src/bsp_driver_sd.c **** * This value can be one of the following values: + 210:Src/bsp_driver_sd.c **** * @arg SD_TRANSFER_OK: No data transfer is acting + 211:Src/bsp_driver_sd.c **** * @arg SD_TRANSFER_BUSY: Data transfer is acting + 212:Src/bsp_driver_sd.c **** */ + 213:Src/bsp_driver_sd.c **** __weak uint8_t BSP_SD_GetCardState(void) + 214:Src/bsp_driver_sd.c **** { + 324 .loc 1 214 1 is_stmt 1 view -0 + 325 .cfi_startproc + 326 @ args = 0, pretend = 0, frame = 0 + 327 @ frame_needed = 0, uses_anonymous_args = 0 + 328 0000 08B5 push {r3, lr} + 329 .LCFI9: + 330 .cfi_def_cfa_offset 8 + 331 .cfi_offset 3, -8 + 332 .cfi_offset 14, -4 + 215:Src/bsp_driver_sd.c **** return ((HAL_SD_GetCardState(&hsd1) == HAL_SD_CARD_TRANSFER ) ? SD_TRANSFER_OK : SD_TRANSFER_BUSY + 333 .loc 1 215 3 view .LVU65 + 334 .loc 1 215 12 is_stmt 0 view .LVU66 + 335 0002 0348 ldr r0, .L34 + 336 0004 FFF7FEFF bl HAL_SD_GetCardState + 337 .LVL36: + 216:Src/bsp_driver_sd.c **** } + 338 .loc 1 216 1 view .LVU67 + 339 0008 0438 subs r0, r0, #4 + 340 000a 18BF it ne + 341 000c 0120 movne r0, #1 + 342 000e 08BD pop {r3, pc} + 343 .L35: + 344 .align 2 + 345 .L34: + 346 0010 00000000 .word hsd1 + 347 .cfi_endproc + 348 .LFE148: + 350 .section .text.BSP_SD_GetCardInfo,"ax",%progbits + 351 .align 1 + 352 .weak BSP_SD_GetCardInfo + 353 .syntax unified + 354 .thumb + 355 .thumb_func + 357 BSP_SD_GetCardInfo: + 358 .LVL37: + 359 .LFB149: + 217:Src/bsp_driver_sd.c **** + 218:Src/bsp_driver_sd.c **** /** + 219:Src/bsp_driver_sd.c **** * @brief Get SD information about specific SD card. + 220:Src/bsp_driver_sd.c **** * @param CardInfo: Pointer to HAL_SD_CardInfoTypedef structure + 221:Src/bsp_driver_sd.c **** * @retval None + 222:Src/bsp_driver_sd.c **** */ + 223:Src/bsp_driver_sd.c **** __weak void BSP_SD_GetCardInfo(HAL_SD_CardInfoTypeDef *CardInfo) + 224:Src/bsp_driver_sd.c **** { + 360 .loc 1 224 1 is_stmt 1 view -0 + 361 .cfi_startproc + ARM GAS /tmp/ccwhiVas.s page 11 + + + 362 @ args = 0, pretend = 0, frame = 0 + 363 @ frame_needed = 0, uses_anonymous_args = 0 + 364 .loc 1 224 1 is_stmt 0 view .LVU69 + 365 0000 08B5 push {r3, lr} + 366 .LCFI10: + 367 .cfi_def_cfa_offset 8 + 368 .cfi_offset 3, -8 + 369 .cfi_offset 14, -4 + 370 0002 0146 mov r1, r0 + 225:Src/bsp_driver_sd.c **** /* Get SD card Information */ + 226:Src/bsp_driver_sd.c **** HAL_SD_GetCardInfo(&hsd1, CardInfo); + 371 .loc 1 226 3 is_stmt 1 view .LVU70 + 372 0004 0148 ldr r0, .L38 + 373 .LVL38: + 374 .loc 1 226 3 is_stmt 0 view .LVU71 + 375 0006 FFF7FEFF bl HAL_SD_GetCardInfo + 376 .LVL39: + 227:Src/bsp_driver_sd.c **** } + 377 .loc 1 227 1 view .LVU72 + 378 000a 08BD pop {r3, pc} + 379 .L39: + 380 .align 2 + 381 .L38: + 382 000c 00000000 .word hsd1 + 383 .cfi_endproc + 384 .LFE149: + 386 .section .text.BSP_SD_AbortCallback,"ax",%progbits + 387 .align 1 + 388 .weak BSP_SD_AbortCallback + 389 .syntax unified + 390 .thumb + 391 .thumb_func + 393 BSP_SD_AbortCallback: + 394 .LFB153: + 228:Src/bsp_driver_sd.c **** + 229:Src/bsp_driver_sd.c **** /* USER CODE BEGIN BeforeCallBacksSection */ + 230:Src/bsp_driver_sd.c **** /* can be used to modify previous code / undefine following code / add code */ + 231:Src/bsp_driver_sd.c **** /* USER CODE END BeforeCallBacksSection */ + 232:Src/bsp_driver_sd.c **** /** + 233:Src/bsp_driver_sd.c **** * @brief SD Abort callbacks + 234:Src/bsp_driver_sd.c **** * @param hsd: SD handle + 235:Src/bsp_driver_sd.c **** * @retval None + 236:Src/bsp_driver_sd.c **** */ + 237:Src/bsp_driver_sd.c **** void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) + 238:Src/bsp_driver_sd.c **** { + 239:Src/bsp_driver_sd.c **** BSP_SD_AbortCallback(); + 240:Src/bsp_driver_sd.c **** } + 241:Src/bsp_driver_sd.c **** + 242:Src/bsp_driver_sd.c **** /** + 243:Src/bsp_driver_sd.c **** * @brief Tx Transfer completed callback + 244:Src/bsp_driver_sd.c **** * @param hsd: SD handle + 245:Src/bsp_driver_sd.c **** * @retval None + 246:Src/bsp_driver_sd.c **** */ + 247:Src/bsp_driver_sd.c **** void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) + 248:Src/bsp_driver_sd.c **** { + 249:Src/bsp_driver_sd.c **** BSP_SD_WriteCpltCallback(); + 250:Src/bsp_driver_sd.c **** } + ARM GAS /tmp/ccwhiVas.s page 12 + + + 251:Src/bsp_driver_sd.c **** + 252:Src/bsp_driver_sd.c **** /** + 253:Src/bsp_driver_sd.c **** * @brief Rx Transfer completed callback + 254:Src/bsp_driver_sd.c **** * @param hsd: SD handle + 255:Src/bsp_driver_sd.c **** * @retval None + 256:Src/bsp_driver_sd.c **** */ + 257:Src/bsp_driver_sd.c **** void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd) + 258:Src/bsp_driver_sd.c **** { + 259:Src/bsp_driver_sd.c **** BSP_SD_ReadCpltCallback(); + 260:Src/bsp_driver_sd.c **** } + 261:Src/bsp_driver_sd.c **** + 262:Src/bsp_driver_sd.c **** /* USER CODE BEGIN CallBacksSection_C */ + 263:Src/bsp_driver_sd.c **** /** + 264:Src/bsp_driver_sd.c **** * @brief BSP SD Abort callback + 265:Src/bsp_driver_sd.c **** * @retval None + 266:Src/bsp_driver_sd.c **** * @note empty (up to the user to fill it in or to remove it if useless) + 267:Src/bsp_driver_sd.c **** */ + 268:Src/bsp_driver_sd.c **** __weak void BSP_SD_AbortCallback(void) + 269:Src/bsp_driver_sd.c **** { + 395 .loc 1 269 1 is_stmt 1 view -0 + 396 .cfi_startproc + 397 @ args = 0, pretend = 0, frame = 0 + 398 @ frame_needed = 0, uses_anonymous_args = 0 + 399 @ link register save eliminated. + 270:Src/bsp_driver_sd.c **** + 271:Src/bsp_driver_sd.c **** } + 400 .loc 1 271 1 view .LVU74 + 401 0000 7047 bx lr + 402 .cfi_endproc + 403 .LFE153: + 405 .section .text.HAL_SD_AbortCallback,"ax",%progbits + 406 .align 1 + 407 .global HAL_SD_AbortCallback + 408 .syntax unified + 409 .thumb + 410 .thumb_func + 412 HAL_SD_AbortCallback: + 413 .LVL40: + 414 .LFB150: + 238:Src/bsp_driver_sd.c **** BSP_SD_AbortCallback(); + 415 .loc 1 238 1 view -0 + 416 .cfi_startproc + 417 @ args = 0, pretend = 0, frame = 0 + 418 @ frame_needed = 0, uses_anonymous_args = 0 + 238:Src/bsp_driver_sd.c **** BSP_SD_AbortCallback(); + 419 .loc 1 238 1 is_stmt 0 view .LVU76 + 420 0000 08B5 push {r3, lr} + 421 .LCFI11: + 422 .cfi_def_cfa_offset 8 + 423 .cfi_offset 3, -8 + 424 .cfi_offset 14, -4 + 239:Src/bsp_driver_sd.c **** } + 425 .loc 1 239 3 is_stmt 1 view .LVU77 + 426 0002 FFF7FEFF bl BSP_SD_AbortCallback + 427 .LVL41: + 240:Src/bsp_driver_sd.c **** + 428 .loc 1 240 1 is_stmt 0 view .LVU78 + ARM GAS /tmp/ccwhiVas.s page 13 + + + 429 0006 08BD pop {r3, pc} + 430 .cfi_endproc + 431 .LFE150: + 433 .section .text.BSP_SD_WriteCpltCallback,"ax",%progbits + 434 .align 1 + 435 .weak BSP_SD_WriteCpltCallback + 436 .syntax unified + 437 .thumb + 438 .thumb_func + 440 BSP_SD_WriteCpltCallback: + 441 .LFB154: + 272:Src/bsp_driver_sd.c **** + 273:Src/bsp_driver_sd.c **** /** + 274:Src/bsp_driver_sd.c **** * @brief BSP Tx Transfer completed callback + 275:Src/bsp_driver_sd.c **** * @retval None + 276:Src/bsp_driver_sd.c **** * @note empty (up to the user to fill it in or to remove it if useless) + 277:Src/bsp_driver_sd.c **** */ + 278:Src/bsp_driver_sd.c **** __weak void BSP_SD_WriteCpltCallback(void) + 279:Src/bsp_driver_sd.c **** { + 442 .loc 1 279 1 is_stmt 1 view -0 + 443 .cfi_startproc + 444 @ args = 0, pretend = 0, frame = 0 + 445 @ frame_needed = 0, uses_anonymous_args = 0 + 446 @ link register save eliminated. + 280:Src/bsp_driver_sd.c **** + 281:Src/bsp_driver_sd.c **** } + 447 .loc 1 281 1 view .LVU80 + 448 0000 7047 bx lr + 449 .cfi_endproc + 450 .LFE154: + 452 .section .text.HAL_SD_TxCpltCallback,"ax",%progbits + 453 .align 1 + 454 .global HAL_SD_TxCpltCallback + 455 .syntax unified + 456 .thumb + 457 .thumb_func + 459 HAL_SD_TxCpltCallback: + 460 .LVL42: + 461 .LFB151: + 248:Src/bsp_driver_sd.c **** BSP_SD_WriteCpltCallback(); + 462 .loc 1 248 1 view -0 + 463 .cfi_startproc + 464 @ args = 0, pretend = 0, frame = 0 + 465 @ frame_needed = 0, uses_anonymous_args = 0 + 248:Src/bsp_driver_sd.c **** BSP_SD_WriteCpltCallback(); + 466 .loc 1 248 1 is_stmt 0 view .LVU82 + 467 0000 08B5 push {r3, lr} + 468 .LCFI12: + 469 .cfi_def_cfa_offset 8 + 470 .cfi_offset 3, -8 + 471 .cfi_offset 14, -4 + 249:Src/bsp_driver_sd.c **** } + 472 .loc 1 249 3 is_stmt 1 view .LVU83 + 473 0002 FFF7FEFF bl BSP_SD_WriteCpltCallback + 474 .LVL43: + 250:Src/bsp_driver_sd.c **** + 475 .loc 1 250 1 is_stmt 0 view .LVU84 + ARM GAS /tmp/ccwhiVas.s page 14 + + + 476 0006 08BD pop {r3, pc} + 477 .cfi_endproc + 478 .LFE151: + 480 .section .text.BSP_SD_ReadCpltCallback,"ax",%progbits + 481 .align 1 + 482 .weak BSP_SD_ReadCpltCallback + 483 .syntax unified + 484 .thumb + 485 .thumb_func + 487 BSP_SD_ReadCpltCallback: + 488 .LFB155: + 282:Src/bsp_driver_sd.c **** + 283:Src/bsp_driver_sd.c **** /** + 284:Src/bsp_driver_sd.c **** * @brief BSP Rx Transfer completed callback + 285:Src/bsp_driver_sd.c **** * @retval None + 286:Src/bsp_driver_sd.c **** * @note empty (up to the user to fill it in or to remove it if useless) + 287:Src/bsp_driver_sd.c **** */ + 288:Src/bsp_driver_sd.c **** __weak void BSP_SD_ReadCpltCallback(void) + 289:Src/bsp_driver_sd.c **** { + 489 .loc 1 289 1 is_stmt 1 view -0 + 490 .cfi_startproc + 491 @ args = 0, pretend = 0, frame = 0 + 492 @ frame_needed = 0, uses_anonymous_args = 0 + 493 @ link register save eliminated. + 290:Src/bsp_driver_sd.c **** + 291:Src/bsp_driver_sd.c **** } + 494 .loc 1 291 1 view .LVU86 + 495 0000 7047 bx lr + 496 .cfi_endproc + 497 .LFE155: + 499 .section .text.HAL_SD_RxCpltCallback,"ax",%progbits + 500 .align 1 + 501 .global HAL_SD_RxCpltCallback + 502 .syntax unified + 503 .thumb + 504 .thumb_func + 506 HAL_SD_RxCpltCallback: + 507 .LVL44: + 508 .LFB152: + 258:Src/bsp_driver_sd.c **** BSP_SD_ReadCpltCallback(); + 509 .loc 1 258 1 view -0 + 510 .cfi_startproc + 511 @ args = 0, pretend = 0, frame = 0 + 512 @ frame_needed = 0, uses_anonymous_args = 0 + 258:Src/bsp_driver_sd.c **** BSP_SD_ReadCpltCallback(); + 513 .loc 1 258 1 is_stmt 0 view .LVU88 + 514 0000 08B5 push {r3, lr} + 515 .LCFI13: + 516 .cfi_def_cfa_offset 8 + 517 .cfi_offset 3, -8 + 518 .cfi_offset 14, -4 + 259:Src/bsp_driver_sd.c **** } + 519 .loc 1 259 3 is_stmt 1 view .LVU89 + 520 0002 FFF7FEFF bl BSP_SD_ReadCpltCallback + 521 .LVL45: + 260:Src/bsp_driver_sd.c **** + 522 .loc 1 260 1 is_stmt 0 view .LVU90 + ARM GAS /tmp/ccwhiVas.s page 15 + + + 523 0006 08BD pop {r3, pc} + 524 .cfi_endproc + 525 .LFE152: + 527 .section .text.BSP_SD_IsDetected,"ax",%progbits + 528 .align 1 + 529 .weak BSP_SD_IsDetected + 530 .syntax unified + 531 .thumb + 532 .thumb_func + 534 BSP_SD_IsDetected: + 535 .LFB156: + 292:Src/bsp_driver_sd.c **** /* USER CODE END CallBacksSection_C */ + 293:Src/bsp_driver_sd.c **** #endif + 294:Src/bsp_driver_sd.c **** + 295:Src/bsp_driver_sd.c **** /** + 296:Src/bsp_driver_sd.c **** * @brief Detects if SD card is correctly plugged in the memory slot or not. + 297:Src/bsp_driver_sd.c **** * @param None + 298:Src/bsp_driver_sd.c **** * @retval Returns if SD is detected or not + 299:Src/bsp_driver_sd.c **** */ + 300:Src/bsp_driver_sd.c **** __weak uint8_t BSP_SD_IsDetected(void) + 301:Src/bsp_driver_sd.c **** { + 536 .loc 1 301 1 is_stmt 1 view -0 + 537 .cfi_startproc + 538 @ args = 0, pretend = 0, frame = 8 + 539 @ frame_needed = 0, uses_anonymous_args = 0 + 540 0000 00B5 push {lr} + 541 .LCFI14: + 542 .cfi_def_cfa_offset 4 + 543 .cfi_offset 14, -4 + 544 0002 83B0 sub sp, sp, #12 + 545 .LCFI15: + 546 .cfi_def_cfa_offset 16 + 302:Src/bsp_driver_sd.c **** __IO uint8_t status = SD_PRESENT; + 547 .loc 1 302 3 view .LVU92 + 548 .loc 1 302 16 is_stmt 0 view .LVU93 + 549 0004 0123 movs r3, #1 + 550 0006 8DF80730 strb r3, [sp, #7] + 303:Src/bsp_driver_sd.c **** + 304:Src/bsp_driver_sd.c **** if (BSP_PlatformIsDetected() == 0x0) + 551 .loc 1 304 3 is_stmt 1 view .LVU94 + 552 .loc 1 304 7 is_stmt 0 view .LVU95 + 553 000a FFF7FEFF bl BSP_PlatformIsDetected + 554 .LVL46: + 555 .loc 1 304 6 discriminator 1 view .LVU96 + 556 000e 10B9 cbnz r0, .L50 + 305:Src/bsp_driver_sd.c **** { + 306:Src/bsp_driver_sd.c **** status = SD_NOT_PRESENT; + 557 .loc 1 306 5 is_stmt 1 view .LVU97 + 558 .loc 1 306 12 is_stmt 0 view .LVU98 + 559 0010 0023 movs r3, #0 + 560 0012 8DF80730 strb r3, [sp, #7] + 561 .L50: + 307:Src/bsp_driver_sd.c **** } + 308:Src/bsp_driver_sd.c **** + 309:Src/bsp_driver_sd.c **** return status; + 562 .loc 1 309 3 is_stmt 1 view .LVU99 + 563 .loc 1 309 10 is_stmt 0 view .LVU100 + ARM GAS /tmp/ccwhiVas.s page 16 + + + 564 0016 9DF80700 ldrb r0, [sp, #7] @ zero_extendqisi2 + 310:Src/bsp_driver_sd.c **** } + 565 .loc 1 310 1 view .LVU101 + 566 001a 03B0 add sp, sp, #12 + 567 .LCFI16: + 568 .cfi_def_cfa_offset 4 + 569 @ sp needed + 570 001c 5DF804FB ldr pc, [sp], #4 + 571 .cfi_endproc + 572 .LFE156: + 574 .section .text.BSP_SD_Init,"ax",%progbits + 575 .align 1 + 576 .weak BSP_SD_Init + 577 .syntax unified + 578 .thumb + 579 .thumb_func + 581 BSP_SD_Init: + 582 .LFB141: + 49:Src/bsp_driver_sd.c **** uint8_t sd_state = MSD_OK; + 583 .loc 1 49 1 is_stmt 1 view -0 + 584 .cfi_startproc + 585 @ args = 0, pretend = 0, frame = 0 + 586 @ frame_needed = 0, uses_anonymous_args = 0 + 587 0000 38B5 push {r3, r4, r5, lr} + 588 .LCFI17: + 589 .cfi_def_cfa_offset 16 + 590 .cfi_offset 3, -16 + 591 .cfi_offset 4, -12 + 592 .cfi_offset 5, -8 + 593 .cfi_offset 14, -4 + 50:Src/bsp_driver_sd.c **** /* Check if the SD card is plugged in the slot */ + 594 .loc 1 50 3 view .LVU103 + 595 .LVL47: + 52:Src/bsp_driver_sd.c **** { + 596 .loc 1 52 3 view .LVU104 + 52:Src/bsp_driver_sd.c **** { + 597 .loc 1 52 7 is_stmt 0 view .LVU105 + 598 0002 FFF7FEFF bl BSP_SD_IsDetected + 599 .LVL48: + 52:Src/bsp_driver_sd.c **** { + 600 .loc 1 52 6 discriminator 1 view .LVU106 + 601 0006 0128 cmp r0, #1 + 602 0008 02D0 beq .L57 + 54:Src/bsp_driver_sd.c **** } + 603 .loc 1 54 12 view .LVU107 + 604 000a 0225 movs r5, #2 + 605 .LVL49: + 606 .L53: + 69:Src/bsp_driver_sd.c **** /* USER CODE BEGIN AfterInitSection */ + 607 .loc 1 69 1 view .LVU108 + 608 000c 2846 mov r0, r5 + 609 000e 38BD pop {r3, r4, r5, pc} + 610 .LVL50: + 611 .L57: + 69:Src/bsp_driver_sd.c **** /* USER CODE BEGIN AfterInitSection */ + 612 .loc 1 69 1 view .LVU109 + 613 0010 0446 mov r4, r0 + ARM GAS /tmp/ccwhiVas.s page 17 + + + 57:Src/bsp_driver_sd.c **** /* Configure SD Bus width (4 bits mode selected) */ + 614 .loc 1 57 3 is_stmt 1 view .LVU110 + 57:Src/bsp_driver_sd.c **** /* Configure SD Bus width (4 bits mode selected) */ + 615 .loc 1 57 14 is_stmt 0 view .LVU111 + 616 0012 0748 ldr r0, .L58 + 617 0014 FFF7FEFF bl HAL_SD_Init + 618 .LVL51: + 59:Src/bsp_driver_sd.c **** { + 619 .loc 1 59 3 is_stmt 1 view .LVU112 + 59:Src/bsp_driver_sd.c **** { + 620 .loc 1 59 6 is_stmt 0 view .LVU113 + 621 0018 0546 mov r5, r0 + 622 001a 0028 cmp r0, #0 + 623 001c F6D1 bne .L53 + 62:Src/bsp_driver_sd.c **** { + 624 .loc 1 62 5 is_stmt 1 view .LVU114 + 62:Src/bsp_driver_sd.c **** { + 625 .loc 1 62 9 is_stmt 0 view .LVU115 + 626 001e 4FF40061 mov r1, #2048 + 627 0022 0348 ldr r0, .L58 + 628 .LVL52: + 62:Src/bsp_driver_sd.c **** { + 629 .loc 1 62 9 view .LVU116 + 630 0024 FFF7FEFF bl HAL_SD_ConfigWideBusOperation + 631 .LVL53: + 62:Src/bsp_driver_sd.c **** { + 632 .loc 1 62 8 discriminator 1 view .LVU117 + 633 0028 0028 cmp r0, #0 + 634 002a EFD0 beq .L53 + 64:Src/bsp_driver_sd.c **** } + 635 .loc 1 64 16 view .LVU118 + 636 002c 2546 mov r5, r4 + 637 .LVL54: + 64:Src/bsp_driver_sd.c **** } + 638 .loc 1 64 16 view .LVU119 + 639 002e EDE7 b .L53 + 640 .L59: + 641 .align 2 + 642 .L58: + 643 0030 00000000 .word hsd1 + 644 .cfi_endproc + 645 .LFE141: + 647 .text + 648 .Letext0: + 649 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 650 .file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 651 .file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 652 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h" + 653 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h" + 654 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h" + 655 .file 8 "Inc/fatfs_platform.h" + ARM GAS /tmp/ccwhiVas.s page 18 + + +DEFINED SYMBOLS + *ABS*:00000000 bsp_driver_sd.c + /tmp/ccwhiVas.s:20 .text.BSP_SD_ITConfig:00000000 $t + /tmp/ccwhiVas.s:26 .text.BSP_SD_ITConfig:00000000 BSP_SD_ITConfig + /tmp/ccwhiVas.s:41 .text.BSP_SD_ReadBlocks:00000000 $t + /tmp/ccwhiVas.s:47 .text.BSP_SD_ReadBlocks:00000000 BSP_SD_ReadBlocks + /tmp/ccwhiVas.s:97 .text.BSP_SD_ReadBlocks:0000001c $d + /tmp/ccwhiVas.s:102 .text.BSP_SD_WriteBlocks:00000000 $t + /tmp/ccwhiVas.s:108 .text.BSP_SD_WriteBlocks:00000000 BSP_SD_WriteBlocks + /tmp/ccwhiVas.s:158 .text.BSP_SD_WriteBlocks:0000001c $d + /tmp/ccwhiVas.s:163 .text.BSP_SD_ReadBlocks_DMA:00000000 $t + /tmp/ccwhiVas.s:169 .text.BSP_SD_ReadBlocks_DMA:00000000 BSP_SD_ReadBlocks_DMA + /tmp/ccwhiVas.s:210 .text.BSP_SD_ReadBlocks_DMA:00000014 $d + /tmp/ccwhiVas.s:215 .text.BSP_SD_WriteBlocks_DMA:00000000 $t + /tmp/ccwhiVas.s:221 .text.BSP_SD_WriteBlocks_DMA:00000000 BSP_SD_WriteBlocks_DMA + /tmp/ccwhiVas.s:262 .text.BSP_SD_WriteBlocks_DMA:00000014 $d + /tmp/ccwhiVas.s:267 .text.BSP_SD_Erase:00000000 $t + /tmp/ccwhiVas.s:273 .text.BSP_SD_Erase:00000000 BSP_SD_Erase + /tmp/ccwhiVas.s:311 .text.BSP_SD_Erase:00000014 $d + /tmp/ccwhiVas.s:316 .text.BSP_SD_GetCardState:00000000 $t + /tmp/ccwhiVas.s:322 .text.BSP_SD_GetCardState:00000000 BSP_SD_GetCardState + /tmp/ccwhiVas.s:346 .text.BSP_SD_GetCardState:00000010 $d + /tmp/ccwhiVas.s:351 .text.BSP_SD_GetCardInfo:00000000 $t + /tmp/ccwhiVas.s:357 .text.BSP_SD_GetCardInfo:00000000 BSP_SD_GetCardInfo + /tmp/ccwhiVas.s:382 .text.BSP_SD_GetCardInfo:0000000c $d + /tmp/ccwhiVas.s:387 .text.BSP_SD_AbortCallback:00000000 $t + /tmp/ccwhiVas.s:393 .text.BSP_SD_AbortCallback:00000000 BSP_SD_AbortCallback + /tmp/ccwhiVas.s:406 .text.HAL_SD_AbortCallback:00000000 $t + /tmp/ccwhiVas.s:412 .text.HAL_SD_AbortCallback:00000000 HAL_SD_AbortCallback + /tmp/ccwhiVas.s:434 .text.BSP_SD_WriteCpltCallback:00000000 $t + /tmp/ccwhiVas.s:440 .text.BSP_SD_WriteCpltCallback:00000000 BSP_SD_WriteCpltCallback + /tmp/ccwhiVas.s:453 .text.HAL_SD_TxCpltCallback:00000000 $t + /tmp/ccwhiVas.s:459 .text.HAL_SD_TxCpltCallback:00000000 HAL_SD_TxCpltCallback + /tmp/ccwhiVas.s:481 .text.BSP_SD_ReadCpltCallback:00000000 $t + /tmp/ccwhiVas.s:487 .text.BSP_SD_ReadCpltCallback:00000000 BSP_SD_ReadCpltCallback + /tmp/ccwhiVas.s:500 .text.HAL_SD_RxCpltCallback:00000000 $t + /tmp/ccwhiVas.s:506 .text.HAL_SD_RxCpltCallback:00000000 HAL_SD_RxCpltCallback + /tmp/ccwhiVas.s:528 .text.BSP_SD_IsDetected:00000000 $t + /tmp/ccwhiVas.s:534 .text.BSP_SD_IsDetected:00000000 BSP_SD_IsDetected + /tmp/ccwhiVas.s:575 .text.BSP_SD_Init:00000000 $t + /tmp/ccwhiVas.s:581 .text.BSP_SD_Init:00000000 BSP_SD_Init + /tmp/ccwhiVas.s:643 .text.BSP_SD_Init:00000030 $d + +UNDEFINED SYMBOLS +HAL_SD_ReadBlocks +hsd1 +HAL_SD_WriteBlocks +HAL_SD_ReadBlocks_DMA +HAL_SD_WriteBlocks_DMA +HAL_SD_Erase +HAL_SD_GetCardState +HAL_SD_GetCardInfo +BSP_PlatformIsDetected +HAL_SD_Init +HAL_SD_ConfigWideBusOperation diff --git a/build/bsp_driver_sd.o b/build/bsp_driver_sd.o new file mode 100644 index 0000000000000000000000000000000000000000..5c0d3ae71a9720cf4991b36f0917d596ef37c702 GIT binary patch literal 19808 zcmeI3dvsh?y~p>NGm}X(>EyI&>4Q?HN!kW%o^5FhE#%!snkFPElna_pGLt4YFDH{y zYJoy46e!q&0t#3Gd3n(VctL#dxGq4wzN#XkUP1BwKv5n=P`TglKEFM4=A;$8ce&R6 z!?SYoIlssL?cd&KpM9QlQSa}n+eVorKy?yg*VP#sgQkS;M1BU_&%Uf1H z9Bc{e=%E%>{_3~dUsiGHf$~2bTG;Z!FPYc!s8RuLsG#-fJf#YEhm?9ctTj3R0{P)< zpa=xRABTUy%6pAcAoP9s2ZEtK?2JHu=qbRy7sUgWvlDO#cG1hqe~?~*aGeeF0#p-N zHfJx*Df|mvNS|Q%3B=6{h6YE{Dop(ySo5p#&r(xn+qYO#90V_D>{Rw`)-+wFR7FBT zMEtmsg9RP+u-|Uv{0Ph2cNn=a@-F0N-)Us0poQ`7GV%;n_%UQ>-)-5feaaqtyFFzP zc|~@yo*j0k-c@Lj{XQcH3+g-9Dto7q^9vf=nv{KkkqaXaFpmrEX}iHdsS}w&`646F zh)h8x_AVpOj+D`Uv61IRPNaN^kzF+2$a&l`mzwg` z1zp|s%D&9V%L-cA4||RO%E-0M=W-*jj&!iSSJ>08)A`p$PGbBkP5E_^f1`b$J&m0e zC|w^pB_HxtZh5QMER2T;uU6cP{B7IMG^N|kd4jG^Ts2AvC0B(zGzeCPeBJG5HFLZ=slDRi2Mj`JzR z3pI#1!&$&k%_7crZld!$MV#lH$WUz}#+)-Kc8XZ$e1P?C6tUd-HJTARN5mz{ZbP=A z&4I(HK^h$Dw_Zl|(fgoM(LZ9-ivAQ$3q&vFh>zaDwnxX9p|T%mn}-Ac2`R`@)25>K z&7sSkpQEFkaR$Hgcy6;t)=|7_K07N=8g!c2st?R(?*>YjIRni5zo>|=};yULZ6bjue;(F)P40TY%4rdQr za?5;o8t8V4SnqA~-MzTU`3=R}MLbtc4|3`#4$iRtjG#054?0dA(}OSIzkMnGh3*Wv znh^4st|zXd*?HAdE{5nVK>57vD7h82=VeF926S;=c9fioXnAX7ZxuQ>P^=TtaeB~W zd5t2@P<9bRw*-zuHL@?mwbs`lMT<~SMHASxqFb>Yh`t;3+R?4(ieU6r=tI#TGLz_E z(cU5+O*oWJ30wtBkP+;A5IfvBo!wFt3!gJ(E9!Q5{tCZK5>U=8IEH&f3_2yKC>$3t z-w858pNNG{1+7UD9cL#)Z4q&Xb2r675obH^qPSJWdCIOpmf_*RuTf#qp76vJ9zJ@s zg|{!@wi#{V9Wi#g8ExU6F?Y1hbB37Bg$tN+pfu)mvAw%u?p`l*ZbyvpC1NdimeaaN ztV^6VXnXk5m^)&s^}r49jXk47Ez{#Ee1%w7IzM1L_br&Ft*af*Tj8rktaJ7sO+ovH^_+a2Xl$lkI=+@#n1IX91W?LiB zTBB)1}VZ;s>FSj`sWxc=ylyO?_1IPN%#qpAOScH?H_ zeb-xfpTpP}8SgJ;yxAf&<{>mO+-1x^F=jQ_dK?yOiRI}2rE`q`uvo`VQR>)>Xs)!J z9%upw&YOn|B6SIL>Nx9F?x&bFRrfQhSAh$Zb)0no!L4H^sb7YhRp?XCw@SHdEGth3 zK}od|t92u)K7L?4K~p7n@43)!!a5H-RxvRZvmR&thqEPjLu)+++X7wkur7Efl(%8k z1#8`cKViWavIW1vf>R4j!51o62xX8%kKut>hp) z4a!wmOQBZ>peVD>nDUbSiaOzN^p)Np?dF+HQpcowYp|#e- zS;yJX9-!l2S?63x*29aqhd%@5eOOC2v1t#VOx+(K{~GI}D7*O42#=qI*iAg~mKH+b z0g;ninbpZetxTd0<_PP~-1>QjvpyO@T~8v0b!QE?-vea=Yst5CiF($5E99G~yHxva zr0xfhpTg?qbhplll@wwv<ThZkkn0q#4b0)7)Rp zG&e%ojm4`bD7ayEF|X)d&$V0AmP z3C2*zT<)p-sV2c46-a;|%J)4Ec-HwW2ev9b2fwrHgtU zIydQ^I_VYAEyY?o9d^!4Z!_sK9LnrzJ2Mno5ZUU>ZNixxSYORFp>GMB@IffA#_INQ z-)g4Dv+a}A=_d5GQy0ur>TlHPCiEq#TMgYwSluQhbrZ%Rk7CtL;GFrtYyz&5aWGiz z*(RVxdde!d&O;tnb=Jb$3K6Esq@3luh# zHO*QWEsogHW1}1MrdgeqgOY(V6^Wb*B~Ez9;7aA>$SILkk=9~##&Si37HQ;(9|DCf ztF_pIDSrV>Rp{R-#a1MOlA%=*>I>`Pctf+S+lunYdrxjavRM##Z(~Hm|W?sw5RpNt;JN%skB6iv|S~`&h@LOS<|h$yz3iurN>He-O>Q( z(#tQg)HJIGC6CM0q66x31t_P~{M?v15s%01K&E#Cd7o*(UW{e@(W=FTIsOa8U$xza1(pdVWzI1P(dYOVIyl^}>Y3&6l^*Qm!+n zoO{~O>>W&&ylvI(38?CWY!~amPR0Ms^7c~3*k(ZjrwgV`ymiWMQ_mpWa-BKld?~|A z7PqOLgj=pFr<{8MF{!CMNwTTrznY4{hu&}p0k-wbz+S<&L&n_goS6YCEWD7z-X^B$ z%`=D?*1tbMF&T4c5N^57oN`Cq+wSP*h+yaZtM7ClxdZ7R=sRA7ajXG);e^D6W0FI}J1KFSW3mh@b_Y?ZH#g$H zUOtHbEa|49H}v$zt(Yrj$VgoLgvW{+tS*W72CI0wfa0WmY#L> z>wDbtbW&VZ@Az0xLdWbGPgM3Xqw#bCuR$sY*x}>p;ia|xD^5aSD9{K|Y~S895FhGE zB>SO82m92+ald+K2=Rx9`}}%FLB%>qe>~kk-ZM4?jHZU6(_%8avUJxooX4aZOUXJZK309pK3t3fx+}!pBtQi3- z$NvTKUx5Cq^4YGN?0)#~xPNT2`^9)`$L>2)^m_uZRD~Sva4Ngk?7&c7iEf;ocUq`` zjr6ypn(f!UWr`G5hb+4&R*AaobSxB=pm|^jQKsZst3&zj@NlYQx?6Z)bT##?O{N>; zsYF*go=&RH=B|z!h3!-FNyVBPHg=s2*YR|Gq%Wzmwha@*?fqIDS3{#CTVnd(#K`#I zmXTy4##fUj)`ng;A-?Ei%B)L`HO13$T?5+EnT#jgSUpI{BJ$BIc;cU1DX?Cl4?_bGSyboI5vc?8XD@2_ifcRu7}+;m@ez$L;X2Ux-D$NSoijZ ziT?hMbV@Zfwr||ftvZsa!Lb3(MqLS}pxTnd4HK#Hw2sW~#QVbT=AP!x&h}2zzRZp? zwaV^j?QR?$=^xzU=|R>idpO&E(jw4$uk{;ted;t22b+J4r@I^-KMpUB$95e?QSLT z^7gUxr6(Ufh}>~u8r->^J6ezG@d0#VET``7tX2Bntw0a{-1O@k+B>^db1F5OYGgkf ze;$UWGCcqr&L4|&XC#L?((8wCTnuOS2)rl8jl0fVAGRi#9zorm^&7fcn%zN^9ax>s z^-X814Ncvhs%d@mhD-vwjN7@5L#!DOzH8hAmIq)qFg@33(P zrkMb;dpt7=GXuY~xv{zR%+?KSRS(CyuR#+Cv9z`)t@pW}3|O5zA#ukfx2N6XFEKjN zJCxLJ-2<3921bVxN)O(q!EHR7pj+AO4!Ou_9dAmeF;yh>tj9S}I;A;<=|?qjgt#Na zJ#u@@2w%HlW2~`eMa;cCjMY}xF0HAqUKOht?i-s}(}&|RxxHd|1?2R=#BeXz4}JgG zw&fLxnv*CFjmFazxWZh6**^hAJk>X_2G^e3RwOHi-_bu-nHY;zY{4IgV1GqztfC!K ze*%YI#kf1WjYICA7|}CbM&~xSWAr>s4)JYC)mDR(r8~#x9=2u%#l<6!T|GjwyC`#P zqy|SZFP^W)Ix{B@?v9n%8**^#)2YeJ}VX7Cc4W87-WuWx0{kcX;NmiMklp`e^WKt3K+y zGaAg?;T_3l?y_iOjQVK)?!eWS`oHK|_DFGfM``rDw>1mzE4=mbQN=&Y?`ZwB-q%md zbPmq$;2!(^?2q~yDB`>oRMui_hE_CJw5hzQ;kGG(g8b?DtYoG&%btx__j9dz)_kjk z_m#fIs|u<=zUejNw!kam9?#royJ~#l|(31 z&p+(*=gZpcV&iErA0uU#DcV1~ANiO#yV!Udo9iF(`SUStcCqnDGuMBr&!5javx|*y zUvmA6w7+?Z!Ea-{iw*Bw|7qGkJ1%prwkr1deXh^W7w6f<#`})k{IVl~UbdR=v(MN4QJo1fKeOff$9!^$PcHSz z3w<(=qU>U;6S4xfZ1oPGT;Y?K_~a_|pnjC2=fe{GXAL~6VpvP?6k`==7LJS4jQ~>a zz?$_BD?FFUEVOUKN;~I}5{&HWWQJ*zNkoH44_NnSeKKpOP&XH4s@%lHP zeL8|OK4X<&Z!M%C3w0~S&Y7bG&ZpC{H+ysJ$Ef$^*k`#PUBK5ZKS$l2W1p)Y z6*;Ek&r{!mY!=r4E3tF#EWvo<$1rB0-8-de*?*;3mR4m6bLo}2g_N_f=Yn3&-X4v6 zOW-~V@Sb|b)2o^kPTy2b3hBLH_Z0U!`_&TJy&{o-t{|2pU4rE3a{ctJqQnt5trD-? z>kjeDRf?xhH0KILynVMR;y&qCM7(`>9pde|cBbYCm(<3QHy9F1Un|P?QEtlJH!KA> zX!V=glSN*gmH8^9;8ge8AppCU>#{P(eL+K3<{7e}$vuAP&lhI}E%KZlGRJ+vT4AdY zlZ1}DLF6_!UO|WZ9KPTTrK(ZR#0%hwJkKG4rSiH3oGCJA>_81(fRnXKaR#Fw{xp$- zX1#EouwB?K+#(zijtj38J|_IJ@I~P?9FMH8T*&!?@_=x=ke@bE&+moFyMzx3zbt%4 z_$%RTbfAteTq#^9+$7u~{IKvI;r+sggpUaMqX5QzPWW@-?}QdEjcDgLR^;)*O5qye zdf_?3_Xy7y?iF4yyhHe)@R0Cn;eQLC7ye54d*Lg>JPbVMRV?J^wUldwb;5SxyM@ET zox&@H9}(Uyd`S2u;nTuAT;j2w#ln+>&BAVBpD-o7M0k_%R^eSjelE|r{~`RG@G&7j zf};KF!e@mq3Gskj+ouU*!YbjZ!ZzW#!Xe?s!u`U7!cPew7Jg0mL*Z|Pe-`G4-8^Oq z7YUaO2Za;DJ;G~+j|iU;{zbSD6A#zbf{pNtAn*#AW33!e5Xm_lEFIVGt88{fbDGn?+*sJXUx-iE<~1 zeVNGoc#HZqB>c}5doPL0?SA2VNcg2izKBFUSCYj_eL#3E3BQ}gewWDi2=5d97eszc z_=M;WiTsrC`y}GODRzEK7Qls2k+7IVeaDf=r(EPE!Wz-97P(H?Ecyn=i2gB=9~XXwL_YZX zQ0I^D{8RwP_*~(968V*jeW}PRgsVlrR^-!#9il%+tg>ti8=O1!e5I1CGtdk*eiU4MBY{u#C|CxAv?mEB>d+K7YlJ2q30o-UNq4?nixu& zyf5NBrLWgOOi^0Krshf#^9?THG@FF$gy#x33%3Zj3U`y3cP?0+{G#w>p}szZeFm?~z1k)6<#GgAiP0%lkhg-okD()&-h;v>g!F&Pl?RmdC~rykRR()ep496fk`q5f%w&36B-75S}7z6s{HW%YM$E{M{^nrh zP{VcsDTd@qUox$wM+VWyc+A`g9j15vfkhtK7hm(CM;>GK>IqaIGELKC6& z{JBI}O(I`D7bA5$kheY$f_2m*Sd(xaiFT|Pc91cp^!-1m+lh9aOFg)mMCA$L0Eu=E z3CBnzl@{uLK)ZKR2K9Lh?cc=n0NQ&ciFQ6hqJ1xtXkSSHME`e@XvZjt{P&T_{~(FH zKTpP#`UY8|6n}}!{P+u1<~7F#kxw^?`gOmeb9BEV54frTWVq;j>O^iLk(X{a?3*bg zzqHtOyO8HTk@u6x_v0epMI!Gni2N9d{GSr}84~UInaIB)(VoAE%!jXRS0Rb|`GaD% zuT11}63H(Uc_oSVt{1t3M56{o<}X?G_^TX0e>ffQRh8rEl*<9LrQc~+@@=oG?8Uba zl~h!kCu-&^n@YSk%&~YLjZU(89$TtO#%w|Tq;rzpQ~1aZ?gP(B<#HZ#9?hzsZsxQj z_i<*noIE=8nZ128`I+aW(!QskITcTO20E#p)(j1fBuzw&B~{rsI;_9a@s#RM#fRZk z-`Q3fPp4CZy%TAKef!I?aK#YT&rw+lheXbT!(A^6@SlD--1Xx3qm9dAtoc~q%8&D^ zzuq8pW-;})K;iXU2{~q*KvSjx+j#V#>acQok@rGiHC9YV+K+klV)e$`1UZJ)EGFK& zq436IAQKPMYbM@B*!ITb{52b^Sxmh5LE(+(c;Zn{Kjz18_`UJ=Lq1Zx8=?2ci+SSV zmOT^iF>HI|-39qb@i?D)<5hd&VS3KQ`<^e}V~}THHH&HQccAdbtMkMwg3Yw|6>NL+ zdkV6H)hs67AEEHZ>+rivqZUVP-NVz8UVwD$>LyzQQNI8A5b{oEIi=VR|2!+N>=#20TD z;>Dl`@U}7=?+u9um0oyVv1E%B)5^5f%_dc`wPnIBjFhMzQk-(BS91(jZm-+O)e{RMuzXq1KZavApJ z_e?#M@MHW6tR}w;;fLmpL8X_Sdisk_status(disk.lun[pdrv]); + 40 .loc 1 42 3 view .LVU3 + 41 .loc 1 42 18 is_stmt 0 view .LVU4 + 42 0002 044B ldr r3, .L3 + 43 0004 03EB8002 add r2, r3, r0, lsl #2 + 44 0008 5268 ldr r2, [r2, #4] + 45 .loc 1 42 24 view .LVU5 + 46 000a 5268 ldr r2, [r2, #4] + 47 .loc 1 42 10 view .LVU6 + 48 000c 0344 add r3, r3, r0 + 49 000e 187A ldrb r0, [r3, #8] @ zero_extendqisi2 + 50 .LVL1: + 51 .loc 1 42 10 view .LVU7 + 52 0010 9047 blx r2 + 53 .LVL2: + 43:Middlewares/Third_Party/FatFs/src/diskio.c **** return stat; + 54 .loc 1 43 3 is_stmt 1 view .LVU8 + 44:Middlewares/Third_Party/FatFs/src/diskio.c **** } + 55 .loc 1 44 1 is_stmt 0 view .LVU9 + 56 0012 08BD pop {r3, pc} + 57 .L4: + 58 .align 2 + 59 .L3: + 60 0014 00000000 .word disk + 61 .cfi_endproc + 62 .LFE1183: + 64 .section .text.disk_initialize,"ax",%progbits + 65 .align 1 + 66 .global disk_initialize + 67 .syntax unified + 68 .thumb + 69 .thumb_func + 71 disk_initialize: + 72 .LVL3: + 73 .LFB1184: + ARM GAS /tmp/ccNpyRnY.s page 3 + + + 45:Middlewares/Third_Party/FatFs/src/diskio.c **** + 46:Middlewares/Third_Party/FatFs/src/diskio.c **** /** + 47:Middlewares/Third_Party/FatFs/src/diskio.c **** * @brief Initializes a Drive + 48:Middlewares/Third_Party/FatFs/src/diskio.c **** * @param pdrv: Physical drive number (0..) + 49:Middlewares/Third_Party/FatFs/src/diskio.c **** * @retval DSTATUS: Operation status + 50:Middlewares/Third_Party/FatFs/src/diskio.c **** */ + 51:Middlewares/Third_Party/FatFs/src/diskio.c **** DSTATUS disk_initialize ( + 52:Middlewares/Third_Party/FatFs/src/diskio.c **** BYTE pdrv /* Physical drive nmuber to identify the drive */ + 53:Middlewares/Third_Party/FatFs/src/diskio.c **** ) + 54:Middlewares/Third_Party/FatFs/src/diskio.c **** { + 74 .loc 1 54 1 is_stmt 1 view -0 + 75 .cfi_startproc + 76 @ args = 0, pretend = 0, frame = 0 + 77 @ frame_needed = 0, uses_anonymous_args = 0 + 78 .loc 1 54 1 is_stmt 0 view .LVU11 + 79 0000 08B5 push {r3, lr} + 80 .LCFI1: + 81 .cfi_def_cfa_offset 8 + 82 .cfi_offset 3, -8 + 83 .cfi_offset 14, -4 + 55:Middlewares/Third_Party/FatFs/src/diskio.c **** DSTATUS stat = RES_OK; + 84 .loc 1 55 3 is_stmt 1 view .LVU12 + 85 .LVL4: + 56:Middlewares/Third_Party/FatFs/src/diskio.c **** + 57:Middlewares/Third_Party/FatFs/src/diskio.c **** if(disk.is_initialized[pdrv] == 0) + 86 .loc 1 57 3 view .LVU13 + 87 .loc 1 57 25 is_stmt 0 view .LVU14 + 88 0002 084B ldr r3, .L9 + 89 0004 1B5C ldrb r3, [r3, r0] @ zero_extendqisi2 + 90 .loc 1 57 5 view .LVU15 + 91 0006 53B9 cbnz r3, .L7 + 58:Middlewares/Third_Party/FatFs/src/diskio.c **** { + 59:Middlewares/Third_Party/FatFs/src/diskio.c **** disk.is_initialized[pdrv] = 1; + 92 .loc 1 59 5 is_stmt 1 view .LVU16 + 93 .loc 1 59 31 is_stmt 0 view .LVU17 + 94 0008 064B ldr r3, .L9 + 95 000a 0122 movs r2, #1 + 96 000c 1A54 strb r2, [r3, r0] + 60:Middlewares/Third_Party/FatFs/src/diskio.c **** stat = disk.drv[pdrv]->disk_initialize(disk.lun[pdrv]); + 97 .loc 1 60 5 is_stmt 1 view .LVU18 + 98 .loc 1 60 20 is_stmt 0 view .LVU19 + 99 000e 03EB8002 add r2, r3, r0, lsl #2 + 100 0012 5268 ldr r2, [r2, #4] + 101 .loc 1 60 26 view .LVU20 + 102 0014 1268 ldr r2, [r2] + 103 .loc 1 60 12 view .LVU21 + 104 0016 0344 add r3, r3, r0 + 105 0018 187A ldrb r0, [r3, #8] @ zero_extendqisi2 + 106 .LVL5: + 107 .loc 1 60 12 view .LVU22 + 108 001a 9047 blx r2 + 109 .LVL6: + 110 .L6: + 61:Middlewares/Third_Party/FatFs/src/diskio.c **** } + 62:Middlewares/Third_Party/FatFs/src/diskio.c **** return stat; + 111 .loc 1 62 3 is_stmt 1 view .LVU23 + 63:Middlewares/Third_Party/FatFs/src/diskio.c **** } + ARM GAS /tmp/ccNpyRnY.s page 4 + + + 112 .loc 1 63 1 is_stmt 0 view .LVU24 + 113 001c 08BD pop {r3, pc} + 114 .LVL7: + 115 .L7: + 55:Middlewares/Third_Party/FatFs/src/diskio.c **** + 116 .loc 1 55 11 view .LVU25 + 117 001e 0020 movs r0, #0 + 118 .LVL8: + 55:Middlewares/Third_Party/FatFs/src/diskio.c **** + 119 .loc 1 55 11 view .LVU26 + 120 0020 FCE7 b .L6 + 121 .L10: + 122 0022 00BF .align 2 + 123 .L9: + 124 0024 00000000 .word disk + 125 .cfi_endproc + 126 .LFE1184: + 128 .section .text.disk_read,"ax",%progbits + 129 .align 1 + 130 .global disk_read + 131 .syntax unified + 132 .thumb + 133 .thumb_func + 135 disk_read: + 136 .LVL9: + 137 .LFB1185: + 64:Middlewares/Third_Party/FatFs/src/diskio.c **** + 65:Middlewares/Third_Party/FatFs/src/diskio.c **** /** + 66:Middlewares/Third_Party/FatFs/src/diskio.c **** * @brief Reads Sector(s) + 67:Middlewares/Third_Party/FatFs/src/diskio.c **** * @param pdrv: Physical drive number (0..) + 68:Middlewares/Third_Party/FatFs/src/diskio.c **** * @param *buff: Data buffer to store read data + 69:Middlewares/Third_Party/FatFs/src/diskio.c **** * @param sector: Sector address (LBA) + 70:Middlewares/Third_Party/FatFs/src/diskio.c **** * @param count: Number of sectors to read (1..128) + 71:Middlewares/Third_Party/FatFs/src/diskio.c **** * @retval DRESULT: Operation result + 72:Middlewares/Third_Party/FatFs/src/diskio.c **** */ + 73:Middlewares/Third_Party/FatFs/src/diskio.c **** DRESULT disk_read ( + 74:Middlewares/Third_Party/FatFs/src/diskio.c **** BYTE pdrv, /* Physical drive nmuber to identify the drive */ + 75:Middlewares/Third_Party/FatFs/src/diskio.c **** BYTE *buff, /* Data buffer to store read data */ + 76:Middlewares/Third_Party/FatFs/src/diskio.c **** DWORD sector, /* Sector address in LBA */ + 77:Middlewares/Third_Party/FatFs/src/diskio.c **** UINT count /* Number of sectors to read */ + 78:Middlewares/Third_Party/FatFs/src/diskio.c **** ) + 79:Middlewares/Third_Party/FatFs/src/diskio.c **** { + 138 .loc 1 79 1 is_stmt 1 view -0 + 139 .cfi_startproc + 140 @ args = 0, pretend = 0, frame = 0 + 141 @ frame_needed = 0, uses_anonymous_args = 0 + 142 .loc 1 79 1 is_stmt 0 view .LVU28 + 143 0000 38B5 push {r3, r4, r5, lr} + 144 .LCFI2: + 145 .cfi_def_cfa_offset 16 + 146 .cfi_offset 3, -16 + 147 .cfi_offset 4, -12 + 148 .cfi_offset 5, -8 + 149 .cfi_offset 14, -4 + 80:Middlewares/Third_Party/FatFs/src/diskio.c **** DRESULT res; + 150 .loc 1 80 3 is_stmt 1 view .LVU29 + 81:Middlewares/Third_Party/FatFs/src/diskio.c **** + ARM GAS /tmp/ccNpyRnY.s page 5 + + + 82:Middlewares/Third_Party/FatFs/src/diskio.c **** res = disk.drv[pdrv]->disk_read(disk.lun[pdrv], buff, sector, count); + 151 .loc 1 82 3 view .LVU30 + 152 .loc 1 82 17 is_stmt 0 view .LVU31 + 153 0002 044C ldr r4, .L13 + 154 0004 04EB8005 add r5, r4, r0, lsl #2 + 155 0008 6D68 ldr r5, [r5, #4] + 156 .loc 1 82 23 view .LVU32 + 157 000a AD68 ldr r5, [r5, #8] + 158 .loc 1 82 9 view .LVU33 + 159 000c 0444 add r4, r4, r0 + 160 000e 207A ldrb r0, [r4, #8] @ zero_extendqisi2 + 161 .LVL10: + 162 .loc 1 82 9 view .LVU34 + 163 0010 A847 blx r5 + 164 .LVL11: + 83:Middlewares/Third_Party/FatFs/src/diskio.c **** return res; + 165 .loc 1 83 3 is_stmt 1 view .LVU35 + 84:Middlewares/Third_Party/FatFs/src/diskio.c **** } + 166 .loc 1 84 1 is_stmt 0 view .LVU36 + 167 0012 38BD pop {r3, r4, r5, pc} + 168 .L14: + 169 .align 2 + 170 .L13: + 171 0014 00000000 .word disk + 172 .cfi_endproc + 173 .LFE1185: + 175 .section .text.disk_write,"ax",%progbits + 176 .align 1 + 177 .global disk_write + 178 .syntax unified + 179 .thumb + 180 .thumb_func + 182 disk_write: + 183 .LVL12: + 184 .LFB1186: + 85:Middlewares/Third_Party/FatFs/src/diskio.c **** + 86:Middlewares/Third_Party/FatFs/src/diskio.c **** /** + 87:Middlewares/Third_Party/FatFs/src/diskio.c **** * @brief Writes Sector(s) + 88:Middlewares/Third_Party/FatFs/src/diskio.c **** * @param pdrv: Physical drive number (0..) + 89:Middlewares/Third_Party/FatFs/src/diskio.c **** * @param *buff: Data to be written + 90:Middlewares/Third_Party/FatFs/src/diskio.c **** * @param sector: Sector address (LBA) + 91:Middlewares/Third_Party/FatFs/src/diskio.c **** * @param count: Number of sectors to write (1..128) + 92:Middlewares/Third_Party/FatFs/src/diskio.c **** * @retval DRESULT: Operation result + 93:Middlewares/Third_Party/FatFs/src/diskio.c **** */ + 94:Middlewares/Third_Party/FatFs/src/diskio.c **** #if _USE_WRITE == 1 + 95:Middlewares/Third_Party/FatFs/src/diskio.c **** DRESULT disk_write ( + 96:Middlewares/Third_Party/FatFs/src/diskio.c **** BYTE pdrv, /* Physical drive nmuber to identify the drive */ + 97:Middlewares/Third_Party/FatFs/src/diskio.c **** const BYTE *buff, /* Data to be written */ + 98:Middlewares/Third_Party/FatFs/src/diskio.c **** DWORD sector, /* Sector address in LBA */ + 99:Middlewares/Third_Party/FatFs/src/diskio.c **** UINT count /* Number of sectors to write */ + 100:Middlewares/Third_Party/FatFs/src/diskio.c **** ) + 101:Middlewares/Third_Party/FatFs/src/diskio.c **** { + 185 .loc 1 101 1 is_stmt 1 view -0 + 186 .cfi_startproc + 187 @ args = 0, pretend = 0, frame = 0 + 188 @ frame_needed = 0, uses_anonymous_args = 0 + 189 .loc 1 101 1 is_stmt 0 view .LVU38 + ARM GAS /tmp/ccNpyRnY.s page 6 + + + 190 0000 38B5 push {r3, r4, r5, lr} + 191 .LCFI3: + 192 .cfi_def_cfa_offset 16 + 193 .cfi_offset 3, -16 + 194 .cfi_offset 4, -12 + 195 .cfi_offset 5, -8 + 196 .cfi_offset 14, -4 + 102:Middlewares/Third_Party/FatFs/src/diskio.c **** DRESULT res; + 197 .loc 1 102 3 is_stmt 1 view .LVU39 + 103:Middlewares/Third_Party/FatFs/src/diskio.c **** + 104:Middlewares/Third_Party/FatFs/src/diskio.c **** res = disk.drv[pdrv]->disk_write(disk.lun[pdrv], buff, sector, count); + 198 .loc 1 104 3 view .LVU40 + 199 .loc 1 104 17 is_stmt 0 view .LVU41 + 200 0002 044C ldr r4, .L17 + 201 0004 04EB8005 add r5, r4, r0, lsl #2 + 202 0008 6D68 ldr r5, [r5, #4] + 203 .loc 1 104 23 view .LVU42 + 204 000a ED68 ldr r5, [r5, #12] + 205 .loc 1 104 9 view .LVU43 + 206 000c 0444 add r4, r4, r0 + 207 000e 207A ldrb r0, [r4, #8] @ zero_extendqisi2 + 208 .LVL13: + 209 .loc 1 104 9 view .LVU44 + 210 0010 A847 blx r5 + 211 .LVL14: + 105:Middlewares/Third_Party/FatFs/src/diskio.c **** return res; + 212 .loc 1 105 3 is_stmt 1 view .LVU45 + 106:Middlewares/Third_Party/FatFs/src/diskio.c **** } + 213 .loc 1 106 1 is_stmt 0 view .LVU46 + 214 0012 38BD pop {r3, r4, r5, pc} + 215 .L18: + 216 .align 2 + 217 .L17: + 218 0014 00000000 .word disk + 219 .cfi_endproc + 220 .LFE1186: + 222 .section .text.disk_ioctl,"ax",%progbits + 223 .align 1 + 224 .global disk_ioctl + 225 .syntax unified + 226 .thumb + 227 .thumb_func + 229 disk_ioctl: + 230 .LVL15: + 231 .LFB1187: + 107:Middlewares/Third_Party/FatFs/src/diskio.c **** #endif /* _USE_WRITE == 1 */ + 108:Middlewares/Third_Party/FatFs/src/diskio.c **** + 109:Middlewares/Third_Party/FatFs/src/diskio.c **** /** + 110:Middlewares/Third_Party/FatFs/src/diskio.c **** * @brief I/O control operation + 111:Middlewares/Third_Party/FatFs/src/diskio.c **** * @param pdrv: Physical drive number (0..) + 112:Middlewares/Third_Party/FatFs/src/diskio.c **** * @param cmd: Control code + 113:Middlewares/Third_Party/FatFs/src/diskio.c **** * @param *buff: Buffer to send/receive control data + 114:Middlewares/Third_Party/FatFs/src/diskio.c **** * @retval DRESULT: Operation result + 115:Middlewares/Third_Party/FatFs/src/diskio.c **** */ + 116:Middlewares/Third_Party/FatFs/src/diskio.c **** #if _USE_IOCTL == 1 + 117:Middlewares/Third_Party/FatFs/src/diskio.c **** DRESULT disk_ioctl ( + 118:Middlewares/Third_Party/FatFs/src/diskio.c **** BYTE pdrv, /* Physical drive nmuber (0..) */ + ARM GAS /tmp/ccNpyRnY.s page 7 + + + 119:Middlewares/Third_Party/FatFs/src/diskio.c **** BYTE cmd, /* Control code */ + 120:Middlewares/Third_Party/FatFs/src/diskio.c **** void *buff /* Buffer to send/receive control data */ + 121:Middlewares/Third_Party/FatFs/src/diskio.c **** ) + 122:Middlewares/Third_Party/FatFs/src/diskio.c **** { + 232 .loc 1 122 1 is_stmt 1 view -0 + 233 .cfi_startproc + 234 @ args = 0, pretend = 0, frame = 0 + 235 @ frame_needed = 0, uses_anonymous_args = 0 + 236 .loc 1 122 1 is_stmt 0 view .LVU48 + 237 0000 10B5 push {r4, lr} + 238 .LCFI4: + 239 .cfi_def_cfa_offset 8 + 240 .cfi_offset 4, -8 + 241 .cfi_offset 14, -4 + 123:Middlewares/Third_Party/FatFs/src/diskio.c **** DRESULT res; + 242 .loc 1 123 3 is_stmt 1 view .LVU49 + 124:Middlewares/Third_Party/FatFs/src/diskio.c **** + 125:Middlewares/Third_Party/FatFs/src/diskio.c **** res = disk.drv[pdrv]->disk_ioctl(disk.lun[pdrv], cmd, buff); + 243 .loc 1 125 3 view .LVU50 + 244 .loc 1 125 17 is_stmt 0 view .LVU51 + 245 0002 044B ldr r3, .L21 + 246 0004 03EB8004 add r4, r3, r0, lsl #2 + 247 0008 6468 ldr r4, [r4, #4] + 248 .loc 1 125 23 view .LVU52 + 249 000a 2469 ldr r4, [r4, #16] + 250 .loc 1 125 9 view .LVU53 + 251 000c 0344 add r3, r3, r0 + 252 000e 187A ldrb r0, [r3, #8] @ zero_extendqisi2 + 253 .LVL16: + 254 .loc 1 125 9 view .LVU54 + 255 0010 A047 blx r4 + 256 .LVL17: + 126:Middlewares/Third_Party/FatFs/src/diskio.c **** return res; + 257 .loc 1 126 3 is_stmt 1 view .LVU55 + 127:Middlewares/Third_Party/FatFs/src/diskio.c **** } + 258 .loc 1 127 1 is_stmt 0 view .LVU56 + 259 0012 10BD pop {r4, pc} + 260 .L22: + 261 .align 2 + 262 .L21: + 263 0014 00000000 .word disk + 264 .cfi_endproc + 265 .LFE1187: + 267 .section .text.get_fattime,"ax",%progbits + 268 .align 1 + 269 .weak get_fattime + 270 .syntax unified + 271 .thumb + 272 .thumb_func + 274 get_fattime: + 275 .LFB1188: + 128:Middlewares/Third_Party/FatFs/src/diskio.c **** #endif /* _USE_IOCTL == 1 */ + 129:Middlewares/Third_Party/FatFs/src/diskio.c **** + 130:Middlewares/Third_Party/FatFs/src/diskio.c **** /** + 131:Middlewares/Third_Party/FatFs/src/diskio.c **** * @brief Gets Time from RTC + 132:Middlewares/Third_Party/FatFs/src/diskio.c **** * @param None + 133:Middlewares/Third_Party/FatFs/src/diskio.c **** * @retval Time in DWORD + ARM GAS /tmp/ccNpyRnY.s page 8 + + + 134:Middlewares/Third_Party/FatFs/src/diskio.c **** */ + 135:Middlewares/Third_Party/FatFs/src/diskio.c **** __weak DWORD get_fattime (void) + 136:Middlewares/Third_Party/FatFs/src/diskio.c **** { + 276 .loc 1 136 1 is_stmt 1 view -0 + 277 .cfi_startproc + 278 @ args = 0, pretend = 0, frame = 0 + 279 @ frame_needed = 0, uses_anonymous_args = 0 + 280 @ link register save eliminated. + 137:Middlewares/Third_Party/FatFs/src/diskio.c **** return 0; + 281 .loc 1 137 3 view .LVU58 + 138:Middlewares/Third_Party/FatFs/src/diskio.c **** } + 282 .loc 1 138 1 is_stmt 0 view .LVU59 + 283 0000 0020 movs r0, #0 + 284 0002 7047 bx lr + 285 .cfi_endproc + 286 .LFE1188: + 288 .text + 289 .Letext0: + 290 .file 2 "Middlewares/Third_Party/FatFs/src/integer.h" + 291 .file 3 "Middlewares/Third_Party/FatFs/src/diskio.h" + 292 .file 4 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 293 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h" + 294 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h" + 295 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h" + 296 .file 8 "Middlewares/Third_Party/FatFs/src/ff_gen_drv.h" + ARM GAS /tmp/ccNpyRnY.s page 9 + + +DEFINED SYMBOLS + *ABS*:00000000 diskio.c + /tmp/ccNpyRnY.s:20 .text.disk_status:00000000 $t + /tmp/ccNpyRnY.s:26 .text.disk_status:00000000 disk_status + /tmp/ccNpyRnY.s:60 .text.disk_status:00000014 $d + /tmp/ccNpyRnY.s:65 .text.disk_initialize:00000000 $t + /tmp/ccNpyRnY.s:71 .text.disk_initialize:00000000 disk_initialize + /tmp/ccNpyRnY.s:124 .text.disk_initialize:00000024 $d + /tmp/ccNpyRnY.s:129 .text.disk_read:00000000 $t + /tmp/ccNpyRnY.s:135 .text.disk_read:00000000 disk_read + /tmp/ccNpyRnY.s:171 .text.disk_read:00000014 $d + /tmp/ccNpyRnY.s:176 .text.disk_write:00000000 $t + /tmp/ccNpyRnY.s:182 .text.disk_write:00000000 disk_write + /tmp/ccNpyRnY.s:218 .text.disk_write:00000014 $d + /tmp/ccNpyRnY.s:223 .text.disk_ioctl:00000000 $t + /tmp/ccNpyRnY.s:229 .text.disk_ioctl:00000000 disk_ioctl + /tmp/ccNpyRnY.s:263 .text.disk_ioctl:00000014 $d + /tmp/ccNpyRnY.s:268 .text.get_fattime:00000000 $t + /tmp/ccNpyRnY.s:274 .text.get_fattime:00000000 get_fattime + +UNDEFINED SYMBOLS +disk diff --git a/build/diskio.o b/build/diskio.o new file mode 100644 index 0000000000000000000000000000000000000000..fabe7340663086cd2e9364815aebf669651175a4 GIT binary patch literal 9212 zcmeHMdvILUc|Z5=-PM(L^_C@B7O*zP$O+n&WE&Yjz_MPJZ6UE*htNFMt9?kDO1tXr z$`&ppCO~*J)4YMCGsGRz2^o?$&4d`*rlf&k7^Xuz`GXcFw9~Xnrx4OG4CAC>lKy_@ zes}lo)-Gk*KYM1+{hjY|zVEx|eCOPA?|y9Z_>^H7$}NT(P*qB)uV1bu{@oe|)HbzM z*^gVte6O7~W6QB+-$d`3Pfy$5rPzMlKDOn93r_})8Qc2ejz&jSBmDNis;8*8_i^jE z_1ang>hd?1t%>lNN2mAd{#E|#HT*WmpOs$To}<5W(`{N`h1aIv^ebi3sIrVXTtf#D z{R7@R&_XEL4UIm4)o?lVO~d{b1U}23%a@h)Ua~s7hiK+iT+HsCQGov@woU(^P;555 z2WCyn|5u=_f2ZV%o;wLvLoXzj0rS4j7WN4=80_!sZh0Ee5JwNy;K$Wym_*ZTXrr{@ zleDC)Cjq{G-vg8wf!9Epw*OYj4)GG{r7imvT>QK={tOo%JT@`j2IYSfVA|HtzzSNS zCG_z}x~X8d4IFy^+P&wV&|R)|yV%OV1MSd*&chV@d1+ev>3cC7V4U}D`S(vaWvK&^*~Y5%L|HOLZ>^-{-+vvpW9Kx zs6DCGv@%X>9#`lw)b7vF%7)FMI0O0=YHu-9QpWEFpGNx;)IUVs+<}W(R(-}zjc@wi zGIm}Vy#OLc!rXab=mNx>49>KXs14~mkQm>ogmhB7e;LddQ62Zm7S5cXk)U=zN-K*t z?|2CGHRMHUC8gKw2SDG9>V%oqVcrFr^W=oN?gev|2HqxLMQK8yyT-DMU^tEhhIT2_#Vn$m4iLzY~tqq1d*`xH{w*ZTD*@9Z<2|=%~`^HGV_rKuD>s zh`J%<-UIu$8y&`>rUws0wkcv7RIk$3w&0hodFhcQY$;8i>duNO}1d7JP1xPf8* z++hUOcR$kHZ2An_TQ2VL0moy%H+->v*(G~$Dp8mgrn+4tlL2i$cWMfsn1-4sP^C#> zIVrs#e7QysL_4aXZX#4vovq^%s<9eXXJhfGaucE_f%m6L=i<<{s%VD#QeCiC!^CU9efBFk|{P z4t<%(&ge*BM^g=XCdE77aiUe8Ho%>bNSTDdOD*fin&vnVkx>1pWQVwHM+5pI5KuT z;c%lf`IJ)WT~sl2*tBui5(D~a@K5?nlz zYPjXx>P5K4RLbFIvx%ilK7k`0Xl4e^AbdH%i0m)|hTj+1+U4&+qxY!4DI6i~Hv*le z52I97-BVHB3{`(5u+4u38-auVE@0mQe@OS;#=icbZzCMW5zTAi1ywQ8jvhTn{f(FO z_Al>3_m}TN_Z|e~>(sYrBDe|61_vg7>sn?alU1?Fg~W|>@z}&I7~y1DEgYGdiYMY@ zhZ8g78yhNBSjX!dXDX4)=gPU{O72WXce*(?AB(H$8&8DCheyLsR)j}}Ms^Jk4P6%= zTurU5A50aB<;=$5>L}>)^7`r`FbjTm?bM#Z^zgMLR|?7UAQJ1~aA4JNX z8qEx@zBjuTNw0+mm+(s?VY7oH;lVjj*>tj;94uv0vn~w4&M@=R1-JP z#U_+?qSo`J+)_T14yWMCbE9*-(Un4eDO}OuJ8Nkf(buxxap6QO$)1djk0<7jA72=o znV5NBY#wVZ6;Cd%WK^!?8OpR;T+e1zbh)saiDonDWOR0BJ|2xF)49U@a-m$v=TeD< z^~F-Am`$cKiDELHEJmj@`AjicE))~<{%!AX<~*)o^6b64rYI{iA6SV)yu^!!c6 zVskOiD2$J9%vXnq18`#I#<!lX_oClo!(w5_Lrxi>!+LnNxIm>3_Qjcq7SZJ{WWz#bFOK5;zm*wGBV zuXuC0n!9r|3ozlCZGH2_Ofsz|7UE;^6APYrYG!?n?}2K1e0*PcV0h0yo!7<8%JAUG z&iW+BITbs~Z%}Y_yR9YEth%_xNa3D6)?(jj{=QMe=N|6z-F=;19R0RCt-E}8v(JAg zyNI8=*oX1Bh0l<&VO)~jwv}-;n*Pzr!C4h(ZkTN}o9qs&3$L3!zFuRq(P#7rJ-8!}F)oX2XYPAr82nVyR|O)%&S^^7&MtPCuaaw^uCS zxa}!Ed`YRbZ`awkJ=%h$sEY=F5V`R1X z6b}~F;`59Yxjxlh6>8d>HI(y2RV_Y!IP%hbf2N=*s!Lh7 zs(Vu+r#Cn6HUuBcEfYaAXNWFckIW>q$63=RZkjVe+$6Y}h~d17h+(@%_`3x63G#l~ zFD94~ToEh@ZU}xt@b?7&NboViKNUPL_+7zg1b-m-lHflG1~Dm&qeJk3U`&u71}Xoj z;O7OO68wSSOM`eDI87W|grc_RFMU+8BAUle><@E?irV<8c#-$q0_b_wa94kcVZxFGa-X?gK2)p--{0l;V zQSf2me@*Cb2!31m-y@u-%CQjBKRZWzb^C}f=GX7UIn=$bDp_(5w{C+ z|02yVkVL(Xf&79>dO`5F1V1czM)0G8cMIMp_=wO2&@OYmO7bAn$Hd`wXP<%Imz`xWqM;qwmz+IvBepH)f!T<{lyZwvakk3ila$nUJo z<1K<$3SKS9&#si;AUGv>RFI!wDPI=U&m}zOb^d~nC87O=i5Q0g$(JD_@^&wg4>uz8 zvFtS>MBPuX2N2pG`s?Q)P}@ZwV5#YR2oqtiX1zdJKlgz8xdQwAJCOJPF`3`Th_Lf_ zMD+J@oS?7$Tqb_dPul^l<3|4p`U8E0hVr; zTy${RZQ&)ftRj46RFTC}Nkwp?kB}MBM+iA>)NwuUyLA%%9#O}0jv;kS=Ro3k@*YdH zS~|11zJyo7YyqL^c5-pCm^tM{=WtdEDKD8UCi6@96UWp4zj9V``HX831E3ZC#oXe08D{^-MgQvnZRRG+ZU-t?Ot~&waYY*79O{&MJ<3@4 zZh{neM?K~W`*{5_Z{5ONXJKyf57$GeEN5|uqx~yTsl!To3e{`xIOqXXx48BWgW^U;z6px=;g;{AaRGaPTU^=K!SIgDqwxD2l85ugHzoHz z=*R7YraF&F;Pb~VZu12&+%{!*U~o^n$>@t^i{R;(Z(y$9S3G^tRKLJJ zb%YHmt}mX&z4i|EJNq*2b)mZUevY==2TgSdgS(dvDX#3NpuP4sVDBV&w8u9<*Pe+E zZXdAK2JH2?lK|S4{Tgkry}yS&t}WVQzPk2W#2#fVpTa)Of4$v8d#s!5^uCS#nQPiD zuHFvObNN4n-Z_^5(k~0YLwMt}@mx3wKI22EmH2i+58`S&64+~V3p*fn~~h;Q5#LgqIA69G3gGXMYp literal 0 HcmV?d00001 diff --git a/build/fatfs.d b/build/fatfs.d new file mode 100644 index 0000000..9937f1d --- /dev/null +++ b/build/fatfs.d @@ -0,0 +1,107 @@ +build/fatfs.o: Src/fatfs.c Inc/fatfs.h \ + Middlewares/Third_Party/FatFs/src/ff.h \ + Middlewares/Third_Party/FatFs/src/integer.h Inc/ffconf.h Inc/main.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h Inc/bsp_driver_sd.h \ + Inc/fatfs_platform.h Middlewares/Third_Party/FatFs/src/ff_gen_drv.h \ + Middlewares/Third_Party/FatFs/src/diskio.h \ + Middlewares/Third_Party/FatFs/src/ff.h Inc/sd_diskio.h +Inc/fatfs.h: +Middlewares/Third_Party/FatFs/src/ff.h: +Middlewares/Third_Party/FatFs/src/integer.h: +Inc/ffconf.h: +Inc/main.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h: +Inc/bsp_driver_sd.h: +Inc/fatfs_platform.h: +Middlewares/Third_Party/FatFs/src/ff_gen_drv.h: +Middlewares/Third_Party/FatFs/src/diskio.h: +Middlewares/Third_Party/FatFs/src/ff.h: +Inc/sd_diskio.h: diff --git a/build/fatfs.lst b/build/fatfs.lst new file mode 100644 index 0000000..8fc8cb4 --- /dev/null +++ b/build/fatfs.lst @@ -0,0 +1,193 @@ +ARM GAS /tmp/ccgsRqtI.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "fatfs.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Src/fatfs.c" + 19 .section .text.MX_FATFS_Init,"ax",%progbits + 20 .align 1 + 21 .global MX_FATFS_Init + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 MX_FATFS_Init: + 27 .LFB1183: + 1:Src/fatfs.c **** /* USER CODE BEGIN Header */ + 2:Src/fatfs.c **** /** + 3:Src/fatfs.c **** ****************************************************************************** + 4:Src/fatfs.c **** * @file fatfs.c + 5:Src/fatfs.c **** * @brief Code for fatfs applications + 6:Src/fatfs.c **** ****************************************************************************** + 7:Src/fatfs.c **** * @attention + 8:Src/fatfs.c **** * + 9:Src/fatfs.c **** * Copyright (c) 2023 STMicroelectronics. + 10:Src/fatfs.c **** * All rights reserved. + 11:Src/fatfs.c **** * + 12:Src/fatfs.c **** * This software is licensed under terms that can be found in the LICENSE file + 13:Src/fatfs.c **** * in the root directory of this software component. + 14:Src/fatfs.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Src/fatfs.c **** * + 16:Src/fatfs.c **** ****************************************************************************** + 17:Src/fatfs.c **** */ + 18:Src/fatfs.c **** /* USER CODE END Header */ + 19:Src/fatfs.c **** #include "fatfs.h" + 20:Src/fatfs.c **** + 21:Src/fatfs.c **** uint8_t retSD; /* Return value for SD */ + 22:Src/fatfs.c **** char SDPath[4]; /* SD logical drive path */ + 23:Src/fatfs.c **** FATFS SDFatFS; /* File system object for SD logical drive */ + 24:Src/fatfs.c **** FIL SDFile; /* File object for SD */ + 25:Src/fatfs.c **** + 26:Src/fatfs.c **** /* USER CODE BEGIN Variables */ + 27:Src/fatfs.c **** + 28:Src/fatfs.c **** /* USER CODE END Variables */ + 29:Src/fatfs.c **** + 30:Src/fatfs.c **** void MX_FATFS_Init(void) + 31:Src/fatfs.c **** { + ARM GAS /tmp/ccgsRqtI.s page 2 + + + 28 .loc 1 31 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 0000 08B5 push {r3, lr} + 33 .LCFI0: + 34 .cfi_def_cfa_offset 8 + 35 .cfi_offset 3, -8 + 36 .cfi_offset 14, -4 + 32:Src/fatfs.c **** /*## FatFS: Link the SD driver ###########################*/ + 33:Src/fatfs.c **** retSD = FATFS_LinkDriver(&SD_Driver, SDPath); + 37 .loc 1 33 3 view .LVU1 + 38 .loc 1 33 11 is_stmt 0 view .LVU2 + 39 0002 0349 ldr r1, .L3 + 40 0004 0348 ldr r0, .L3+4 + 41 0006 FFF7FEFF bl FATFS_LinkDriver + 42 .LVL0: + 43 .loc 1 33 9 discriminator 1 view .LVU3 + 44 000a 034B ldr r3, .L3+8 + 45 000c 1870 strb r0, [r3] + 34:Src/fatfs.c **** + 35:Src/fatfs.c **** /* USER CODE BEGIN Init */ + 36:Src/fatfs.c **** /* additional user code for init */ + 37:Src/fatfs.c **** /* USER CODE END Init */ + 38:Src/fatfs.c **** } + 46 .loc 1 38 1 view .LVU4 + 47 000e 08BD pop {r3, pc} + 48 .L4: + 49 .align 2 + 50 .L3: + 51 0010 00000000 .word SDPath + 52 0014 00000000 .word SD_Driver + 53 0018 00000000 .word retSD + 54 .cfi_endproc + 55 .LFE1183: + 57 .section .text.get_fattime,"ax",%progbits + 58 .align 1 + 59 .global get_fattime + 60 .syntax unified + 61 .thumb + 62 .thumb_func + 64 get_fattime: + 65 .LFB1184: + 39:Src/fatfs.c **** + 40:Src/fatfs.c **** /** + 41:Src/fatfs.c **** * @brief Gets Time from RTC + 42:Src/fatfs.c **** * @param None + 43:Src/fatfs.c **** * @retval Time in DWORD + 44:Src/fatfs.c **** */ + 45:Src/fatfs.c **** DWORD get_fattime(void) + 46:Src/fatfs.c **** { + 66 .loc 1 46 1 is_stmt 1 view -0 + 67 .cfi_startproc + 68 @ args = 0, pretend = 0, frame = 0 + 69 @ frame_needed = 0, uses_anonymous_args = 0 + 70 @ link register save eliminated. + 47:Src/fatfs.c **** /* USER CODE BEGIN get_fattime */ + ARM GAS /tmp/ccgsRqtI.s page 3 + + + 48:Src/fatfs.c **** return 0; + 71 .loc 1 48 3 view .LVU6 + 49:Src/fatfs.c **** /* USER CODE END get_fattime */ + 50:Src/fatfs.c **** } + 72 .loc 1 50 1 is_stmt 0 view .LVU7 + 73 0000 0020 movs r0, #0 + 74 0002 7047 bx lr + 75 .cfi_endproc + 76 .LFE1184: + 78 .global SDFile + 79 .section .bss.SDFile,"aw",%nobits + 80 .align 2 + 83 SDFile: + 84 0000 00000000 .space 4144 + 84 00000000 + 84 00000000 + 84 00000000 + 84 00000000 + 85 .global SDFatFS + 86 .section .bss.SDFatFS,"aw",%nobits + 87 .align 2 + 90 SDFatFS: + 91 0000 00000000 .space 4148 + 91 00000000 + 91 00000000 + 91 00000000 + 91 00000000 + 92 .global SDPath + 93 .section .bss.SDPath,"aw",%nobits + 94 .align 2 + 97 SDPath: + 98 0000 00000000 .space 4 + 99 .global retSD + 100 .section .bss.retSD,"aw",%nobits + 103 retSD: + 104 0000 00 .space 1 + 105 .text + 106 .Letext0: + 107 .file 2 "Middlewares/Third_Party/FatFs/src/integer.h" + 108 .file 3 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 109 .file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h" + 110 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h" + 111 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h" + 112 .file 7 "Middlewares/Third_Party/FatFs/src/ff.h" + 113 .file 8 "Middlewares/Third_Party/FatFs/src/diskio.h" + 114 .file 9 "Middlewares/Third_Party/FatFs/src/ff_gen_drv.h" + 115 .file 10 "Inc/sd_diskio.h" + 116 .file 11 "Inc/fatfs.h" + ARM GAS /tmp/ccgsRqtI.s page 4 + + +DEFINED SYMBOLS + *ABS*:00000000 fatfs.c + /tmp/ccgsRqtI.s:20 .text.MX_FATFS_Init:00000000 $t + /tmp/ccgsRqtI.s:26 .text.MX_FATFS_Init:00000000 MX_FATFS_Init + /tmp/ccgsRqtI.s:51 .text.MX_FATFS_Init:00000010 $d + /tmp/ccgsRqtI.s:97 .bss.SDPath:00000000 SDPath + /tmp/ccgsRqtI.s:103 .bss.retSD:00000000 retSD + /tmp/ccgsRqtI.s:58 .text.get_fattime:00000000 $t + /tmp/ccgsRqtI.s:64 .text.get_fattime:00000000 get_fattime + /tmp/ccgsRqtI.s:83 .bss.SDFile:00000000 SDFile + /tmp/ccgsRqtI.s:80 .bss.SDFile:00000000 $d + /tmp/ccgsRqtI.s:90 .bss.SDFatFS:00000000 SDFatFS + /tmp/ccgsRqtI.s:87 .bss.SDFatFS:00000000 $d + /tmp/ccgsRqtI.s:94 .bss.SDPath:00000000 $d + /tmp/ccgsRqtI.s:104 .bss.retSD:00000000 $d + +UNDEFINED SYMBOLS +FATFS_LinkDriver +SD_Driver diff --git a/build/fatfs.o b/build/fatfs.o new file mode 100644 index 0000000000000000000000000000000000000000..0f7e425acba66a313c7af13b0c2704b0730bce39 GIT binary patch literal 6788 zcmb7Id2AzB9e(4nJ$5|K=5Vsvqg!{AZ3ErdNp{O_+b!K}oNPmrCbhjs3&o7>abni7 z!+4U-_MjXEN)Z%Fp;SO=X$y$6Tmm7Ee*hs6NQgt6e;^QQ0f|dMC649$-n>aBX(hx{ zJm2sB{oXlma`)8iw5DmoZ<-huo173o?30?vVF|-xpSVQCKCjQ{H(dP3e=h1b4y?q! z;`>TWubey`6(S^=uy#rp!YqNiA{bS9gu;<}(-r!+z=wMKj{(AA<4U;b1&aE276Fk- z%C*>A5Fs3jjDgb^sop)%q$Xr^A$~X!n13!ah7$Wj{KsXk@8$Pjc{2xq_>8C-gYxwxtm3trkqI7xIcZrF} z)1c#Thh=1>pYk|d3_|Jico;YBxD$%R z;V$D;{3j5YyTKZ#4Gwu|P$a9)nlR2NRx=?L##zON%w8tGMX|bhEw#5QHk_|nL}8>9 zi$m?q(5taFMv&4Jd!J&bQk)zZ{c6MLz=n~ef=2VwGztSR9&>u}m@4&sFVq;M`XqWA z9}le|Y~*GLI>NW%+4m@F?-;y{w5Ijt;E>qg^#nlEqTK2aLZJ?ZzK6jl29x)Aws8bZ z40Un^!SiQ;!~ydF!fRUp8cq7*5tsmYh8TR42eYI#R(mUs@^a3&TA6aCazA*^dg1QbYj>p7nDRbZKhWP zVO$12o51SX0dLfOIN-S#xjQJQOQKgxM7)@EG?M|tqcBWD5c6|V&?!Ts@*VI@YrKD+ z^gd>?-hqtRD(=>LwBsEQoj`b>ce#Kx3z!h_A9>Y%)VMWBm=c!sopb|$eL<=q6lR&Xj}u3oJ+ z?DLjmx3k5ix>GGJSdM!kJ8iks?Q9zs+10j_ZPd%z#Y!b>Im;u>R?{A_t#Um(b|^ER z8Ozq2mBwn-7CEQBW;^X{p*VMFeEP`xdg+FV*^(#C&NM56KT)&XT02wWod{PId(n0> zOYC9Wt%3)QUD9@!4~^Ftq0uN+mn}%qr!7*qzWh8=r&95xwHgpntM&G|dds70wbG*9 zEa468@$G79Lyg7d6}H4fNJKOdk)y8f(<1u*NFu65;vy8*UJ}s`g$#`1ro{*>QV}hh z3WXqVmJp{c@>7M#+BSDcy8=fozcn&V8RfjB1NU?+zhf|pi1>--K|><8lIZDsptvYuH~+_ z(GRE9!W=npcFPS<=h#+NSoz7x(!%U)VPYmXb2`6(wNxou<%Z23A=G)XYjDwax!AE2v8aprsfoGL zW;UAR3@Ko7VnuTeiM3WkM#Cjg4(FCZVV@T!^4K#XC-*G(X%YJ+XV=8Zn@*)C$Bv}E z11CK`I(}$uboA=<$Z}<6^|}f+ki9;#d<49^w7Ogd)*!E~tX(xy9eWX3?vN3jS=V7H zR3WgO%F=Z>&DM_CBg!K&1B_Etw^8MTN z1KaqW+xXpL2PB*`u8SUw_ay-fX3r>|>!Ta}ziONQdc`wFH~K#XBu)Ds%*V|@wowG@ z#`yD#gzd28F~0s0Gvtb)>b4`}IS0*iPFC;zwdHv5&JO=f;0owKr`VU!KHO-Dm*Q$g zOyg2Xd{QAlfSBip3jd=pg+ZqLg$j==JgxAx3LjMXn8FV!Nt?&kgXA~|gd_dt-3csfC zdkTN4@DB?Asc;+%l6hto<`te*_;Q6+h36E$M&bPmA5r)Tgf$6b!`>k7{+e3!z< z6@FUbw}@#WeoVx={0(tXh`$i`3-K%w@%s6Z1l&)=cDY>PsFEKg!uFWL<3ud-X~h?a zh|fkllq*rLckpsw0AYsj^GzNpWj??bKc0xJL;3@+<$8htZA9>Le__)|f5;Eg9{i~C z6PfmfW!yG_uH)g7PvO<-iVRTFcA4 zmIt!d91B;O%tU@J!y8Y%yy_zC|Izlq7DF!Qjc$ke2sCUj*)GGAcGw28ZMUP2jqiKT z?f~mn`@9i=F8z1jJKe40NMP0oCX)HuLz#+ z6u&VZTN%IYc6`_P&9`ekkDafhtxwzBiC8?-{pOP&fxxG!%fdNLLN#Ca1o&XygDKCBd3o#b^L_!e z?*mfIBi=9x)qLG&!3X2bA|CfV<8iqCc;5!?`+yYZ5s!9$^L5{ZAQ-P2sE@ZEKi)4u z`#y|uKjN(f1U~r_=z{U?K|I#Q`ao{Pdm1!-M)7022&X^!n*cm@{QXs-Z}&%B-MDA` z=G)PjwBH6WxJP{k$bPW>3%_7}4+i?n@$vi1e~_b`75cC(Al|q~%BP=;=n)a0R_|h=;@gEdEld0gihuZu;}3<0AB3TzXgjndq-i8YwXZ-@KTE3o z>@_S=c=Q#3`ZrP)=1fv4kvpV%i}}t#MRV8sq5i1ukfib z@;%Gq@u#4~7EUrXbt(S-_{DfBgRIUo0!f!VaZ2w9zIUNcPh_6kdO&InkZ$SOwjzK z=BG6^iM%Pl^tf4?PxICASJxAaO)mv@q=bLCjtyr%_aa9n3RpVx`4>4;CT_1&$%ydc zFh1!c6&XCXJtR~VL>4F&u<$bB6b5Hyg5iR~%V2#vg(sP#lKzt(^36#_P);I(%6^9_ zh5s{^WVq%O6N6Ws2Ga+wqj%bMeZSGr4X2yy**z;~8TGbaSj-pm1-;#CbOxryHl6l? z<+%FBPPJ6kH?4zq!_upJ_}f`5US2*t)JtQQqnX;3wX3z^dNN|HX?RVy*6#ppr<-q3 zI<9Bpw&q*3JJ;(j7Msf#;1vpWq&PgRwTw<}zu&f@rvhl_7_|-TafWN!nHen_=2`@I zo_|nFp4POm8p~=toYAJ#TUjN9?O)yaP=)R6Zf;fB_S4t18-?ZUaHrYgLUFOMuy8S( z>o)p>m4@wj)?u!@4B2Z9x^-X^`ey&&e9kOfAhBZ`UJk`tX&H_Qh2b<>D=6c^vX$$; zui4L={cLU@f94ItY37RA+%BZ1X?RA?wHjXA?zxbggPzZibf|#g4P3Un_iP!74tj2T zzh{}*2I8=e-P_NORMg_!7IHnV8bH5Tta)s`TB$I-Wp^#TX__Ek9n@XRX&Mcy<`|~o=-XD$atzOQYUPdfF=J?IuHE#oAxi|N6n3lStu3^?V|i_t zOS`qbn|*83YBFCam!7UwwyIluj1qhT`IWDivCQ9-{~%}U)pD&YPDjbzv^8vNBJK$9WqlHT3>)vHfn6XR%QNYZe*b{`bBU=DoY*-;8Zp_Ca1?_^w$8X zW7(?6mg-BpCY(n8dcd9<>ix~a8KZ~0`~=W1im2fGXlRX@J9lFA@C0Z{~~Y}MWMXr1(pOpBk(za z9~XEi@Y4dnBk)y1{8)NT;Om6=)V(3*e=X$S3j94G?1>2J1QGgm1JXMo`JBM_3M>k| zAaF(Cnn1t)IBs%1)W`h4DP%gk3XT<>2S1Ozd$a2qb(VKMXNWDyq2GHfPu-d2>#oc4 zxZrtG=Kn`W@(oO@KG?6ddrcc_ecq_o9qVAYe5mQzji6{aMsME|0frX$YdY}0nXw<8}! z)WfI){6D(|*o?=e_ajMm8M-snK~}}Y;}FRINer@~LGm>WnFCmM731xILb5y12mLKU zSimItqw^&FeGI%@1C~9BLYxjLBx{e^eFPh)TqH?5`rjlN*Tj7(Lq~B*FXMg+yj%m8 zeHZ?+#0Zjew;%`oy#jx956B;NSn2OJc)12F`z8F5og_K;1t^04eiraY9a{SP26(xK zeEbpq(gB5J>DOw|-yQgq?~OXV^!Eesw1&;rr{gg@#_l4LBxK-%nkuv>-l0qE&_ fO8%(s6cheNbQeWg9Z5&I)3@Z99rAngzu5f;5`7O| literal 0 HcmV?d00001 diff --git a/build/ff.d b/build/ff.d new file mode 100644 index 0000000..bdd5cad --- /dev/null +++ b/build/ff.d @@ -0,0 +1,101 @@ +build/ff.o: Middlewares/Third_Party/FatFs/src/ff.c \ + Middlewares/Third_Party/FatFs/src/ff.h \ + Middlewares/Third_Party/FatFs/src/integer.h Inc/ffconf.h Inc/main.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h Inc/bsp_driver_sd.h \ + Inc/fatfs_platform.h Middlewares/Third_Party/FatFs/src/diskio.h +Middlewares/Third_Party/FatFs/src/ff.h: +Middlewares/Third_Party/FatFs/src/integer.h: +Inc/ffconf.h: +Inc/main.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h: +Inc/bsp_driver_sd.h: +Inc/fatfs_platform.h: +Middlewares/Third_Party/FatFs/src/diskio.h: diff --git a/build/ff.lst b/build/ff.lst new file mode 100644 index 0000000..69cf08a --- /dev/null +++ b/build/ff.lst @@ -0,0 +1,22719 @@ +ARM GAS /tmp/cc2SVLkL.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "ff.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Middlewares/Third_Party/FatFs/src/ff.c" + 19 .section .text.ld_word,"ax",%progbits + 20 .align 1 + 21 .syntax unified + 22 .thumb + 23 .thumb_func + 25 ld_word: + 26 .LVL0: + 27 .LFB1183: + 1:Middlewares/Third_Party/FatFs/src/ff.c **** /*----------------------------------------------------------------------------/ + 2:Middlewares/Third_Party/FatFs/src/ff.c **** / FatFs - Generic FAT file system module R0.12c / + 3:Middlewares/Third_Party/FatFs/src/ff.c **** /-----------------------------------------------------------------------------/ + 4:Middlewares/Third_Party/FatFs/src/ff.c **** / + 5:Middlewares/Third_Party/FatFs/src/ff.c **** / Copyright (C) 2017, ChaN, all right reserved. + 6:Middlewares/Third_Party/FatFs/src/ff.c **** / + 7:Middlewares/Third_Party/FatFs/src/ff.c **** / FatFs module is an open source software. Redistribution and use of FatFs in + 8:Middlewares/Third_Party/FatFs/src/ff.c **** / source and binary forms, with or without modification, are permitted provided + 9:Middlewares/Third_Party/FatFs/src/ff.c **** / that the following condition is met: + 10:Middlewares/Third_Party/FatFs/src/ff.c **** / + 11:Middlewares/Third_Party/FatFs/src/ff.c **** / 1. Redistributions of source code must retain the above copyright notice, + 12:Middlewares/Third_Party/FatFs/src/ff.c **** / this condition and the following disclaimer. + 13:Middlewares/Third_Party/FatFs/src/ff.c **** / + 14:Middlewares/Third_Party/FatFs/src/ff.c **** / This software is provided by the copyright holder and contributors "AS IS" + 15:Middlewares/Third_Party/FatFs/src/ff.c **** / and any warranties related to this software are DISCLAIMED. + 16:Middlewares/Third_Party/FatFs/src/ff.c **** / The copyright owner or contributors be NOT LIABLE for any damages caused + 17:Middlewares/Third_Party/FatFs/src/ff.c **** / by use of this software. + 18:Middlewares/Third_Party/FatFs/src/ff.c **** /----------------------------------------------------------------------------*/ + 19:Middlewares/Third_Party/FatFs/src/ff.c **** + 20:Middlewares/Third_Party/FatFs/src/ff.c **** + 21:Middlewares/Third_Party/FatFs/src/ff.c **** #include "ff.h" /* Declarations of FatFs API */ + 22:Middlewares/Third_Party/FatFs/src/ff.c **** #include "diskio.h" /* Declarations of device I/O functions */ + 23:Middlewares/Third_Party/FatFs/src/ff.c **** + 24:Middlewares/Third_Party/FatFs/src/ff.c **** + 25:Middlewares/Third_Party/FatFs/src/ff.c **** /*-------------------------------------------------------------------------- + 26:Middlewares/Third_Party/FatFs/src/ff.c **** + 27:Middlewares/Third_Party/FatFs/src/ff.c **** Module Private Definitions + 28:Middlewares/Third_Party/FatFs/src/ff.c **** + 29:Middlewares/Third_Party/FatFs/src/ff.c **** ---------------------------------------------------------------------------*/ + 30:Middlewares/Third_Party/FatFs/src/ff.c **** + 31:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FATFS != 68300 /* Revision ID */ + ARM GAS /tmp/cc2SVLkL.s page 2 + + + 32:Middlewares/Third_Party/FatFs/src/ff.c **** #error Wrong include file (ff.h). + 33:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 34:Middlewares/Third_Party/FatFs/src/ff.c **** + 35:Middlewares/Third_Party/FatFs/src/ff.c **** + 36:Middlewares/Third_Party/FatFs/src/ff.c **** /* DBCS code ranges and SBCS upper conversion tables */ + 37:Middlewares/Third_Party/FatFs/src/ff.c **** + 38:Middlewares/Third_Party/FatFs/src/ff.c **** #if _CODE_PAGE == 932 /* Japanese Shift-JIS */ + 39:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0x81 /* DBC 1st byte range 1 start */ + 40:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1E 0x9F /* DBC 1st byte range 1 end */ + 41:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF2S 0xE0 /* DBC 1st byte range 2 start */ + 42:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF2E 0xFC /* DBC 1st byte range 2 end */ + 43:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS1S 0x40 /* DBC 2nd byte range 1 start */ + 44:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS1E 0x7E /* DBC 2nd byte range 1 end */ + 45:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS2S 0x80 /* DBC 2nd byte range 2 start */ + 46:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS2E 0xFC /* DBC 2nd byte range 2 end */ + 47:Middlewares/Third_Party/FatFs/src/ff.c **** + 48:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 936 /* Simplified Chinese GBK */ + 49:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0x81 + 50:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1E 0xFE + 51:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS1S 0x40 + 52:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS1E 0x7E + 53:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS2S 0x80 + 54:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS2E 0xFE + 55:Middlewares/Third_Party/FatFs/src/ff.c **** + 56:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 949 /* Korean */ + 57:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0x81 + 58:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1E 0xFE + 59:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS1S 0x41 + 60:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS1E 0x5A + 61:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS2S 0x61 + 62:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS2E 0x7A + 63:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS3S 0x81 + 64:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS3E 0xFE + 65:Middlewares/Third_Party/FatFs/src/ff.c **** + 66:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */ + 67:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0x81 + 68:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1E 0xFE + 69:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS1S 0x40 + 70:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS1E 0x7E + 71:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS2S 0xA1 + 72:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DS2E 0xFE + 73:Middlewares/Third_Party/FatFs/src/ff.c **** + 74:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 437 /* U.S. */ + 75:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0 + 76:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ + 77:Middlewares/Third_Party/FatFs/src/ff.c **** 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 78:Middlewares/Third_Party/FatFs/src/ff.c **** 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 79:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 80:Middlewares/Third_Party/FatFs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 81:Middlewares/Third_Party/FatFs/src/ff.c **** 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 82:Middlewares/Third_Party/FatFs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 83:Middlewares/Third_Party/FatFs/src/ff.c **** 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 84:Middlewares/Third_Party/FatFs/src/ff.c **** + 85:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 720 /* Arabic */ + 86:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0 + 87:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 88:Middlewares/Third_Party/FatFs/src/ff.c **** 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + ARM GAS /tmp/cc2SVLkL.s page 3 + + + 89:Middlewares/Third_Party/FatFs/src/ff.c **** 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 90:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 91:Middlewares/Third_Party/FatFs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 92:Middlewares/Third_Party/FatFs/src/ff.c **** 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 93:Middlewares/Third_Party/FatFs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 94:Middlewares/Third_Party/FatFs/src/ff.c **** 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 95:Middlewares/Third_Party/FatFs/src/ff.c **** + 96:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 737 /* Greek */ + 97:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0 + 98:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 99:Middlewares/Third_Party/FatFs/src/ff.c **** 0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ + 100:Middlewares/Third_Party/FatFs/src/ff.c **** 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96, \ + 101:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 102:Middlewares/Third_Party/FatFs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 103:Middlewares/Third_Party/FatFs/src/ff.c **** 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 104:Middlewares/Third_Party/FatFs/src/ff.c **** 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xEF,0xF5,0xF0,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 105:Middlewares/Third_Party/FatFs/src/ff.c **** 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 106:Middlewares/Third_Party/FatFs/src/ff.c **** + 107:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 771 /* KBL */ + 108:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0 + 109:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 110:Middlewares/Third_Party/FatFs/src/ff.c **** 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 111:Middlewares/Third_Party/FatFs/src/ff.c **** 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 112:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 113:Middlewares/Third_Party/FatFs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 114:Middlewares/Third_Party/FatFs/src/ff.c **** 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDC,0xDE,0xDE, \ + 115:Middlewares/Third_Party/FatFs/src/ff.c **** 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 116:Middlewares/Third_Party/FatFs/src/ff.c **** 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFE,0xFF} + 117:Middlewares/Third_Party/FatFs/src/ff.c **** + 118:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 775 /* Baltic */ + 119:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0 + 120:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F, \ + 121:Middlewares/Third_Party/FatFs/src/ff.c **** 0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 122:Middlewares/Third_Party/FatFs/src/ff.c **** 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 123:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 124:Middlewares/Third_Party/FatFs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 125:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 126:Middlewares/Third_Party/FatFs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF, \ + 127:Middlewares/Third_Party/FatFs/src/ff.c **** 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 128:Middlewares/Third_Party/FatFs/src/ff.c **** + 129:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 850 /* Latin 1 */ + 130:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0 + 131:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x43,0x55,0x45,0x41,0x41,0x41,0x41,0x43,0x45,0x45,0x45,0x49,0x49,0x49,0x41,0x41, \ + 132:Middlewares/Third_Party/FatFs/src/ff.c **** 0x45,0x92,0x92,0x4F,0x4F,0x4F,0x55,0x55,0x59,0x4F,0x55,0x4F,0x9C,0x4F,0x9E,0x9F, \ + 133:Middlewares/Third_Party/FatFs/src/ff.c **** 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 134:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB0,0xB1,0xB2,0xB3,0xB4,0x41,0x41,0x41,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 135:Middlewares/Third_Party/FatFs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0x41,0x41,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 136:Middlewares/Third_Party/FatFs/src/ff.c **** 0xD1,0xD1,0x45,0x45,0x45,0x49,0x49,0x49,0x49,0xD9,0xDA,0xDB,0xDC,0xDD,0x49,0xDF, \ + 137:Middlewares/Third_Party/FatFs/src/ff.c **** 0x4F,0xE1,0x4F,0x4F,0x4F,0x4F,0xE6,0xE8,0xE8,0x55,0x55,0x55,0x59,0x59,0xEE,0xEF, \ + 138:Middlewares/Third_Party/FatFs/src/ff.c **** 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 139:Middlewares/Third_Party/FatFs/src/ff.c **** + 140:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 852 /* Latin 2 */ + 141:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0 + 142:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F, \ + 143:Middlewares/Third_Party/FatFs/src/ff.c **** 0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0xAC, \ + 144:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF, \ + 145:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ + ARM GAS /tmp/cc2SVLkL.s page 4 + + + 146:Middlewares/Third_Party/FatFs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 147:Middlewares/Third_Party/FatFs/src/ff.c **** 0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 148:Middlewares/Third_Party/FatFs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF, \ + 149:Middlewares/Third_Party/FatFs/src/ff.c **** 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} + 150:Middlewares/Third_Party/FatFs/src/ff.c **** + 151:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 855 /* Cyrillic */ + 152:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0 + 153:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F, \ + 154:Middlewares/Third_Party/FatFs/src/ff.c **** 0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ + 155:Middlewares/Third_Party/FatFs/src/ff.c **** 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF, \ + 156:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ + 157:Middlewares/Third_Party/FatFs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 158:Middlewares/Third_Party/FatFs/src/ff.c **** 0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ + 159:Middlewares/Third_Party/FatFs/src/ff.c **** 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF, \ + 160:Middlewares/Third_Party/FatFs/src/ff.c **** 0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} + 161:Middlewares/Third_Party/FatFs/src/ff.c **** + 162:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 857 /* Turkish */ + 163:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0 + 164:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x49,0x8E,0x8F, \ + 165:Middlewares/Third_Party/FatFs/src/ff.c **** 0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ + 166:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 167:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 168:Middlewares/Third_Party/FatFs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 169:Middlewares/Third_Party/FatFs/src/ff.c **** 0xD0,0xD1,0xD2,0xD3,0xD4,0x49,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 170:Middlewares/Third_Party/FatFs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0xED,0xEE,0xEF, \ + 171:Middlewares/Third_Party/FatFs/src/ff.c **** 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 172:Middlewares/Third_Party/FatFs/src/ff.c **** + 173:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 860 /* Portuguese */ + 174:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0 + 175:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x90,0x8F,0x8E,0x91,0x86,0x80,0x89,0x89,0x92,0x8B,0x8C,0x98,0x8E,0x8F, \ + 176:Middlewares/Third_Party/FatFs/src/ff.c **** 0x90,0x91,0x92,0x8C,0x99,0xA9,0x96,0x9D,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 177:Middlewares/Third_Party/FatFs/src/ff.c **** 0x86,0x8B,0x9F,0x96,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 178:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 179:Middlewares/Third_Party/FatFs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 180:Middlewares/Third_Party/FatFs/src/ff.c **** 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 181:Middlewares/Third_Party/FatFs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 182:Middlewares/Third_Party/FatFs/src/ff.c **** 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 183:Middlewares/Third_Party/FatFs/src/ff.c **** + 184:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 861 /* Icelandic */ + 185:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0 + 186:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x8B,0x8B,0x8D,0x8E,0x8F, \ + 187:Middlewares/Third_Party/FatFs/src/ff.c **** 0x90,0x92,0x92,0x4F,0x99,0x8D,0x55,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 188:Middlewares/Third_Party/FatFs/src/ff.c **** 0xA4,0xA5,0xA6,0xA7,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 189:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 190:Middlewares/Third_Party/FatFs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 191:Middlewares/Third_Party/FatFs/src/ff.c **** 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 192:Middlewares/Third_Party/FatFs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 193:Middlewares/Third_Party/FatFs/src/ff.c **** 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 194:Middlewares/Third_Party/FatFs/src/ff.c **** + 195:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 862 /* Hebrew */ + 196:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0 + 197:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 198:Middlewares/Third_Party/FatFs/src/ff.c **** 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 199:Middlewares/Third_Party/FatFs/src/ff.c **** 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 200:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 201:Middlewares/Third_Party/FatFs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 202:Middlewares/Third_Party/FatFs/src/ff.c **** 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + ARM GAS /tmp/cc2SVLkL.s page 5 + + + 203:Middlewares/Third_Party/FatFs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 204:Middlewares/Third_Party/FatFs/src/ff.c **** 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 205:Middlewares/Third_Party/FatFs/src/ff.c **** + 206:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 863 /* Canadian-French */ + 207:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0 + 208:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x43,0x55,0x45,0x41,0x41,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x41,0x8F, \ + 209:Middlewares/Third_Party/FatFs/src/ff.c **** 0x45,0x45,0x45,0x4F,0x45,0x49,0x55,0x55,0x98,0x4F,0x55,0x9B,0x9C,0x55,0x55,0x9F, \ + 210:Middlewares/Third_Party/FatFs/src/ff.c **** 0xA0,0xA1,0x4F,0x55,0xA4,0xA5,0xA6,0xA7,0x49,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 211:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 212:Middlewares/Third_Party/FatFs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 213:Middlewares/Third_Party/FatFs/src/ff.c **** 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 214:Middlewares/Third_Party/FatFs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 215:Middlewares/Third_Party/FatFs/src/ff.c **** 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 216:Middlewares/Third_Party/FatFs/src/ff.c **** + 217:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 864 /* Arabic */ + 218:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0 + 219:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ + 220:Middlewares/Third_Party/FatFs/src/ff.c **** 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 221:Middlewares/Third_Party/FatFs/src/ff.c **** 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 222:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 223:Middlewares/Third_Party/FatFs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 224:Middlewares/Third_Party/FatFs/src/ff.c **** 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 225:Middlewares/Third_Party/FatFs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 226:Middlewares/Third_Party/FatFs/src/ff.c **** 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 227:Middlewares/Third_Party/FatFs/src/ff.c **** + 228:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 865 /* Nordic */ + 229:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0 + 230:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \ + 231:Middlewares/Third_Party/FatFs/src/ff.c **** 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 232:Middlewares/Third_Party/FatFs/src/ff.c **** 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 233:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 234:Middlewares/Third_Party/FatFs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 235:Middlewares/Third_Party/FatFs/src/ff.c **** 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 236:Middlewares/Third_Party/FatFs/src/ff.c **** 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \ + 237:Middlewares/Third_Party/FatFs/src/ff.c **** 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 238:Middlewares/Third_Party/FatFs/src/ff.c **** + 239:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 866 /* Russian */ + 240:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0 + 241:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 242:Middlewares/Third_Party/FatFs/src/ff.c **** 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 243:Middlewares/Third_Party/FatFs/src/ff.c **** 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 244:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 245:Middlewares/Third_Party/FatFs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 246:Middlewares/Third_Party/FatFs/src/ff.c **** 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 247:Middlewares/Third_Party/FatFs/src/ff.c **** 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 248:Middlewares/Third_Party/FatFs/src/ff.c **** 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + 249:Middlewares/Third_Party/FatFs/src/ff.c **** + 250:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 869 /* Greek 2 */ + 251:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0 + 252:Middlewares/Third_Party/FatFs/src/ff.c **** #define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \ + 253:Middlewares/Third_Party/FatFs/src/ff.c **** 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x86,0x9C,0x8D,0x8F,0x90, \ + 254:Middlewares/Third_Party/FatFs/src/ff.c **** 0x91,0x90,0x92,0x95,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \ + 255:Middlewares/Third_Party/FatFs/src/ff.c **** 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 256:Middlewares/Third_Party/FatFs/src/ff.c **** 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \ + 257:Middlewares/Third_Party/FatFs/src/ff.c **** 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xA4,0xA5,0xA6,0xD9,0xDA,0xDB,0xDC,0xA7,0xA8,0xDF, \ + 258:Middlewares/Third_Party/FatFs/src/ff.c **** 0xA9,0xAA,0xAC,0xAD,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xCF,0xCF,0xD0,0xEF, \ + 259:Middlewares/Third_Party/FatFs/src/ff.c **** 0xF0,0xF1,0xD1,0xD2,0xD3,0xF5,0xD4,0xF7,0xF8,0xF9,0xD5,0x96,0x95,0x98,0xFE,0xFF} + ARM GAS /tmp/cc2SVLkL.s page 6 + + + 260:Middlewares/Third_Party/FatFs/src/ff.c **** + 261:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */ + 262:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 + 263:Middlewares/Third_Party/FatFs/src/ff.c **** #error Cannot enable LFN without valid code page. + 264:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 265:Middlewares/Third_Party/FatFs/src/ff.c **** #define _DF1S 0 + 266:Middlewares/Third_Party/FatFs/src/ff.c **** + 267:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 268:Middlewares/Third_Party/FatFs/src/ff.c **** #error Unknown code page + 269:Middlewares/Third_Party/FatFs/src/ff.c **** + 270:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 271:Middlewares/Third_Party/FatFs/src/ff.c **** + 272:Middlewares/Third_Party/FatFs/src/ff.c **** + 273:Middlewares/Third_Party/FatFs/src/ff.c **** /* Character code support macros */ + 274:Middlewares/Third_Party/FatFs/src/ff.c **** #define IsUpper(c) (((c)>='A')&&((c)<='Z')) + 275:Middlewares/Third_Party/FatFs/src/ff.c **** #define IsLower(c) (((c)>='a')&&((c)<='z')) + 276:Middlewares/Third_Party/FatFs/src/ff.c **** #define IsDigit(c) (((c)>='0')&&((c)<='9')) + 277:Middlewares/Third_Party/FatFs/src/ff.c **** + 278:Middlewares/Third_Party/FatFs/src/ff.c **** #if _DF1S != 0 /* Code page is DBCS */ + 279:Middlewares/Third_Party/FatFs/src/ff.c **** + 280:Middlewares/Third_Party/FatFs/src/ff.c **** #ifdef _DF2S /* Two 1st byte areas */ + 281:Middlewares/Third_Party/FatFs/src/ff.c **** #define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) + 282:Middlewares/Third_Party/FatFs/src/ff.c **** #else /* One 1st byte area */ + 283:Middlewares/Third_Party/FatFs/src/ff.c **** #define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) + 284:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 285:Middlewares/Third_Party/FatFs/src/ff.c **** + 286:Middlewares/Third_Party/FatFs/src/ff.c **** #ifdef _DS3S /* Three 2nd byte areas */ + 287:Middlewares/Third_Party/FatFs/src/ff.c **** #define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) + 288:Middlewares/Third_Party/FatFs/src/ff.c **** #else /* Two 2nd byte areas */ + 289:Middlewares/Third_Party/FatFs/src/ff.c **** #define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) + 290:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 291:Middlewares/Third_Party/FatFs/src/ff.c **** + 292:Middlewares/Third_Party/FatFs/src/ff.c **** #else /* Code page is SBCS */ + 293:Middlewares/Third_Party/FatFs/src/ff.c **** + 294:Middlewares/Third_Party/FatFs/src/ff.c **** #define IsDBCS1(c) 0 + 295:Middlewares/Third_Party/FatFs/src/ff.c **** #define IsDBCS2(c) 0 + 296:Middlewares/Third_Party/FatFs/src/ff.c **** + 297:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _DF1S */ + 298:Middlewares/Third_Party/FatFs/src/ff.c **** + 299:Middlewares/Third_Party/FatFs/src/ff.c **** + 300:Middlewares/Third_Party/FatFs/src/ff.c **** /* Additional file attribute bits for internal use */ + 301:Middlewares/Third_Party/FatFs/src/ff.c **** #define AM_VOL 0x08 /* Volume label */ + 302:Middlewares/Third_Party/FatFs/src/ff.c **** #define AM_LFN 0x0F /* LFN entry */ + 303:Middlewares/Third_Party/FatFs/src/ff.c **** #define AM_MASK 0x3F /* Mask of defined bits */ + 304:Middlewares/Third_Party/FatFs/src/ff.c **** + 305:Middlewares/Third_Party/FatFs/src/ff.c **** + 306:Middlewares/Third_Party/FatFs/src/ff.c **** /* Additional file access control and file status flags for internal use */ + 307:Middlewares/Third_Party/FatFs/src/ff.c **** #define FA_SEEKEND 0x20 /* Seek to end of the file on file open */ + 308:Middlewares/Third_Party/FatFs/src/ff.c **** #define FA_MODIFIED 0x40 /* File has been modified */ + 309:Middlewares/Third_Party/FatFs/src/ff.c **** #define FA_DIRTY 0x80 /* FIL.buf[] needs to be written-back */ + 310:Middlewares/Third_Party/FatFs/src/ff.c **** + 311:Middlewares/Third_Party/FatFs/src/ff.c **** + 312:Middlewares/Third_Party/FatFs/src/ff.c **** /* Name status flags in fn[] */ + 313:Middlewares/Third_Party/FatFs/src/ff.c **** #define NSFLAG 11 /* Index of the name status byte */ + 314:Middlewares/Third_Party/FatFs/src/ff.c **** #define NS_LOSS 0x01 /* Out of 8.3 format */ + 315:Middlewares/Third_Party/FatFs/src/ff.c **** #define NS_LFN 0x02 /* Force to create LFN entry */ + 316:Middlewares/Third_Party/FatFs/src/ff.c **** #define NS_LAST 0x04 /* Last segment */ + ARM GAS /tmp/cc2SVLkL.s page 7 + + + 317:Middlewares/Third_Party/FatFs/src/ff.c **** #define NS_BODY 0x08 /* Lower case flag (body) */ + 318:Middlewares/Third_Party/FatFs/src/ff.c **** #define NS_EXT 0x10 /* Lower case flag (ext) */ + 319:Middlewares/Third_Party/FatFs/src/ff.c **** #define NS_DOT 0x20 /* Dot entry */ + 320:Middlewares/Third_Party/FatFs/src/ff.c **** #define NS_NOLFN 0x40 /* Do not find LFN */ + 321:Middlewares/Third_Party/FatFs/src/ff.c **** #define NS_NONAME 0x80 /* Not followed */ + 322:Middlewares/Third_Party/FatFs/src/ff.c **** + 323:Middlewares/Third_Party/FatFs/src/ff.c **** + 324:Middlewares/Third_Party/FatFs/src/ff.c **** /* Limits and boundaries */ + 325:Middlewares/Third_Party/FatFs/src/ff.c **** #define MAX_DIR 0x200000 /* Max size of FAT directory */ + 326:Middlewares/Third_Party/FatFs/src/ff.c **** #define MAX_DIR_EX 0x10000000 /* Max size of exFAT directory */ + 327:Middlewares/Third_Party/FatFs/src/ff.c **** #define MAX_FAT12 0xFF5 /* Max FAT12 clusters (differs from specs, but correct for real DOS/Windo + 328:Middlewares/Third_Party/FatFs/src/ff.c **** #define MAX_FAT16 0xFFF5 /* Max FAT16 clusters (differs from specs, but correct for real DOS/Wind + 329:Middlewares/Third_Party/FatFs/src/ff.c **** #define MAX_FAT32 0x0FFFFFF5 /* Max FAT32 clusters (not specified, practical limit) */ + 330:Middlewares/Third_Party/FatFs/src/ff.c **** #define MAX_EXFAT 0x7FFFFFFD /* Max exFAT clusters (differs from specs, implementation limit) */ + 331:Middlewares/Third_Party/FatFs/src/ff.c **** + 332:Middlewares/Third_Party/FatFs/src/ff.c **** + 333:Middlewares/Third_Party/FatFs/src/ff.c **** /* FatFs refers the FAT structure as simple byte array instead of structure member + 334:Middlewares/Third_Party/FatFs/src/ff.c **** / because the C structure is not binary compatible between different platforms */ + 335:Middlewares/Third_Party/FatFs/src/ff.c **** + 336:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_JmpBoot 0 /* x86 jump instruction (3-byte) */ + 337:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_OEMName 3 /* OEM name (8-byte) */ + 338:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_BytsPerSec 11 /* Sector size [byte] (WORD) */ + 339:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_SecPerClus 13 /* Cluster size [sector] (BYTE) */ + 340:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_RsvdSecCnt 14 /* Size of reserved area [sector] (WORD) */ + 341:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_NumFATs 16 /* Number of FATs (BYTE) */ + 342:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_RootEntCnt 17 /* Size of root directory area for FAT12/16 [entry] (WORD) */ + 343:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_TotSec16 19 /* Volume size (16-bit) [sector] (WORD) */ + 344:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_Media 21 /* Media descriptor byte (BYTE) */ + 345:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_FATSz16 22 /* FAT size (16-bit) [sector] (WORD) */ + 346:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_SecPerTrk 24 /* Track size for int13h [sector] (WORD) */ + 347:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_NumHeads 26 /* Number of heads for int13h (WORD) */ + 348:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_HiddSec 28 /* Volume offset from top of the drive (DWORD) */ + 349:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_TotSec32 32 /* Volume size (32-bit) [sector] (DWORD) */ + 350:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_DrvNum 36 /* Physical drive number for int13h (BYTE) */ + 351:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_NTres 37 /* Error flag (BYTE) */ + 352:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_BootSig 38 /* Extended boot signature (BYTE) */ + 353:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_VolID 39 /* Volume serial number (DWORD) */ + 354:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_VolLab 43 /* Volume label string (8-byte) */ + 355:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_FilSysType 54 /* File system type string (8-byte) */ + 356:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_BootCode 62 /* Boot code (448-byte) */ + 357:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_55AA 510 /* Signature word (WORD) */ + 358:Middlewares/Third_Party/FatFs/src/ff.c **** + 359:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_FATSz32 36 /* FAT32: FAT size [sector] (DWORD) */ + 360:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_ExtFlags32 40 /* FAT32: Extended flags (WORD) */ + 361:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_FSVer32 42 /* FAT32: File system version (WORD) */ + 362:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_RootClus32 44 /* FAT32: Root directory cluster (DWORD) */ + 363:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_FSInfo32 48 /* FAT32: Offset of FSINFO sector (WORD) */ + 364:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_BkBootSec32 50 /* FAT32: Offset of backup boot sector (WORD) */ + 365:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_DrvNum32 64 /* FAT32: Physical drive number for int13h (BYTE) */ + 366:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_NTres32 65 /* FAT32: Error flag (BYTE) */ + 367:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_BootSig32 66 /* FAT32: Extended boot signature (BYTE) */ + 368:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_VolID32 67 /* FAT32: Volume serial number (DWORD) */ + 369:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_VolLab32 71 /* FAT32: Volume label string (8-byte) */ + 370:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_FilSysType32 82 /* FAT32: File system type string (8-byte) */ + 371:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_BootCode32 90 /* FAT32: Boot code (420-byte) */ + 372:Middlewares/Third_Party/FatFs/src/ff.c **** + 373:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_ZeroedEx 11 /* exFAT: MBZ field (53-byte) */ + ARM GAS /tmp/cc2SVLkL.s page 8 + + + 374:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_VolOfsEx 64 /* exFAT: Volume offset from top of the drive [sector] (QWORD) */ + 375:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_TotSecEx 72 /* exFAT: Volume size [sector] (QWORD) */ + 376:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_FatOfsEx 80 /* exFAT: FAT offset from top of the volume [sector] (DWORD) */ + 377:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_FatSzEx 84 /* exFAT: FAT size [sector] (DWORD) */ + 378:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_DataOfsEx 88 /* exFAT: Data offset from top of the volume [sector] (DWORD) */ + 379:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_NumClusEx 92 /* exFAT: Number of clusters (DWORD) */ + 380:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_RootClusEx 96 /* exFAT: Root directory start cluster (DWORD) */ + 381:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_VolIDEx 100 /* exFAT: Volume serial number (DWORD) */ + 382:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_FSVerEx 104 /* exFAT: File system version (WORD) */ + 383:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_VolFlagEx 106 /* exFAT: Volume flags (BYTE) */ + 384:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_ActFatEx 107 /* exFAT: Active FAT flags (BYTE) */ + 385:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_BytsPerSecEx 108 /* exFAT: Log2 of sector size in unit of byte (BYTE) */ + 386:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_SecPerClusEx 109 /* exFAT: Log2 of cluster size in unit of sector (BYTE) */ + 387:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_NumFATsEx 110 /* exFAT: Number of FATs (BYTE) */ + 388:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_DrvNumEx 111 /* exFAT: Physical drive number for int13h (BYTE) */ + 389:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_PercInUseEx 112 /* exFAT: Percent in use (BYTE) */ + 390:Middlewares/Third_Party/FatFs/src/ff.c **** #define BPB_RsvdEx 113 /* exFAT: Reserved (7-byte) */ + 391:Middlewares/Third_Party/FatFs/src/ff.c **** #define BS_BootCodeEx 120 /* exFAT: Boot code (390-byte) */ + 392:Middlewares/Third_Party/FatFs/src/ff.c **** + 393:Middlewares/Third_Party/FatFs/src/ff.c **** #define DIR_Name 0 /* Short file name (11-byte) */ + 394:Middlewares/Third_Party/FatFs/src/ff.c **** #define DIR_Attr 11 /* Attribute (BYTE) */ + 395:Middlewares/Third_Party/FatFs/src/ff.c **** #define DIR_NTres 12 /* Lower case flag (BYTE) */ + 396:Middlewares/Third_Party/FatFs/src/ff.c **** #define DIR_CrtTime10 13 /* Created time sub-second (BYTE) */ + 397:Middlewares/Third_Party/FatFs/src/ff.c **** #define DIR_CrtTime 14 /* Created time (DWORD) */ + 398:Middlewares/Third_Party/FatFs/src/ff.c **** #define DIR_LstAccDate 18 /* Last accessed date (WORD) */ + 399:Middlewares/Third_Party/FatFs/src/ff.c **** #define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (WORD) */ + 400:Middlewares/Third_Party/FatFs/src/ff.c **** #define DIR_ModTime 22 /* Modified time (DWORD) */ + 401:Middlewares/Third_Party/FatFs/src/ff.c **** #define DIR_FstClusLO 26 /* Lower 16-bit of first cluster (WORD) */ + 402:Middlewares/Third_Party/FatFs/src/ff.c **** #define DIR_FileSize 28 /* File size (DWORD) */ + 403:Middlewares/Third_Party/FatFs/src/ff.c **** #define LDIR_Ord 0 /* LFN: LFN order and LLE flag (BYTE) */ + 404:Middlewares/Third_Party/FatFs/src/ff.c **** #define LDIR_Attr 11 /* LFN: LFN attribute (BYTE) */ + 405:Middlewares/Third_Party/FatFs/src/ff.c **** #define LDIR_Type 12 /* LFN: Entry type (BYTE) */ + 406:Middlewares/Third_Party/FatFs/src/ff.c **** #define LDIR_Chksum 13 /* LFN: Checksum of the SFN (BYTE) */ + 407:Middlewares/Third_Party/FatFs/src/ff.c **** #define LDIR_FstClusLO 26 /* LFN: MBZ field (WORD) */ + 408:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_Type 0 /* exFAT: Type of exFAT directory entry (BYTE) */ + 409:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_NumLabel 1 /* exFAT: Number of volume label characters (BYTE) */ + 410:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_Label 2 /* exFAT: Volume label (11-WORD) */ + 411:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_CaseSum 4 /* exFAT: Sum of case conversion table (DWORD) */ + 412:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_NumSec 1 /* exFAT: Number of secondary entries (BYTE) */ + 413:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_SetSum 2 /* exFAT: Sum of the set of directory entries (WORD) */ + 414:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_Attr 4 /* exFAT: File attribute (WORD) */ + 415:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_CrtTime 8 /* exFAT: Created time (DWORD) */ + 416:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_ModTime 12 /* exFAT: Modified time (DWORD) */ + 417:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_AccTime 16 /* exFAT: Last accessed time (DWORD) */ + 418:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_CrtTime10 20 /* exFAT: Created time subsecond (BYTE) */ + 419:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_ModTime10 21 /* exFAT: Modified time subsecond (BYTE) */ + 420:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_CrtTZ 22 /* exFAT: Created timezone (BYTE) */ + 421:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_ModTZ 23 /* exFAT: Modified timezone (BYTE) */ + 422:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_AccTZ 24 /* exFAT: Last accessed timezone (BYTE) */ + 423:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_GenFlags 33 /* exFAT: General secondary flags (WORD) */ + 424:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_NumName 35 /* exFAT: Number of file name characters (BYTE) */ + 425:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_NameHash 36 /* exFAT: Hash of file name (WORD) */ + 426:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_ValidFileSize 40 /* exFAT: Valid file size (QWORD) */ + 427:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_FstClus 52 /* exFAT: First cluster of the file data (DWORD) */ + 428:Middlewares/Third_Party/FatFs/src/ff.c **** #define XDIR_FileSize 56 /* exFAT: File/Directory size (QWORD) */ + 429:Middlewares/Third_Party/FatFs/src/ff.c **** + 430:Middlewares/Third_Party/FatFs/src/ff.c **** #define SZDIRE 32 /* Size of a directory entry */ + ARM GAS /tmp/cc2SVLkL.s page 9 + + + 431:Middlewares/Third_Party/FatFs/src/ff.c **** #define DDEM 0xE5 /* Deleted directory entry mark set to DIR_Name[0] */ + 432:Middlewares/Third_Party/FatFs/src/ff.c **** #define RDDEM 0x05 /* Replacement of the character collides with DDEM */ + 433:Middlewares/Third_Party/FatFs/src/ff.c **** #define LLEF 0x40 /* Last long entry flag in LDIR_Ord */ + 434:Middlewares/Third_Party/FatFs/src/ff.c **** + 435:Middlewares/Third_Party/FatFs/src/ff.c **** #define FSI_LeadSig 0 /* FAT32 FSI: Leading signature (DWORD) */ + 436:Middlewares/Third_Party/FatFs/src/ff.c **** #define FSI_StrucSig 484 /* FAT32 FSI: Structure signature (DWORD) */ + 437:Middlewares/Third_Party/FatFs/src/ff.c **** #define FSI_Free_Count 488 /* FAT32 FSI: Number of free clusters (DWORD) */ + 438:Middlewares/Third_Party/FatFs/src/ff.c **** #define FSI_Nxt_Free 492 /* FAT32 FSI: Last allocated cluster (DWORD) */ + 439:Middlewares/Third_Party/FatFs/src/ff.c **** + 440:Middlewares/Third_Party/FatFs/src/ff.c **** #define MBR_Table 446 /* MBR: Offset of partition table in the MBR */ + 441:Middlewares/Third_Party/FatFs/src/ff.c **** #define SZ_PTE 16 /* MBR: Size of a partition table entry */ + 442:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_Boot 0 /* MBR PTE: Boot indicator */ + 443:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_StHead 1 /* MBR PTE: Start head */ + 444:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_StSec 2 /* MBR PTE: Start sector */ + 445:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_StCyl 3 /* MBR PTE: Start cylinder */ + 446:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_System 4 /* MBR PTE: System ID */ + 447:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_EdHead 5 /* MBR PTE: End head */ + 448:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_EdSec 6 /* MBR PTE: End sector */ + 449:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_EdCyl 7 /* MBR PTE: End cylinder */ + 450:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_StLba 8 /* MBR PTE: Start in LBA */ + 451:Middlewares/Third_Party/FatFs/src/ff.c **** #define PTE_SizLba 12 /* MBR PTE: Size in LBA */ + 452:Middlewares/Third_Party/FatFs/src/ff.c **** + 453:Middlewares/Third_Party/FatFs/src/ff.c **** + 454:Middlewares/Third_Party/FatFs/src/ff.c **** /* Post process after fatal error on file operation */ + 455:Middlewares/Third_Party/FatFs/src/ff.c **** #define ABORT(fs, res) { fp->err = (BYTE)(res); LEAVE_FF(fs, res); } + 456:Middlewares/Third_Party/FatFs/src/ff.c **** + 457:Middlewares/Third_Party/FatFs/src/ff.c **** + 458:Middlewares/Third_Party/FatFs/src/ff.c **** /* Reentrancy related */ + 459:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT + 460:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN == 1 + 461:Middlewares/Third_Party/FatFs/src/ff.c **** #error Static LFN work area cannot be used at thread-safe configuration + 462:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 463:Middlewares/Third_Party/FatFs/src/ff.c **** #define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; } + 464:Middlewares/Third_Party/FatFs/src/ff.c **** #define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; } + 465:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 466:Middlewares/Third_Party/FatFs/src/ff.c **** #define ENTER_FF(fs) + 467:Middlewares/Third_Party/FatFs/src/ff.c **** #define LEAVE_FF(fs, res) return res + 468:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 469:Middlewares/Third_Party/FatFs/src/ff.c **** + 470:Middlewares/Third_Party/FatFs/src/ff.c **** + 471:Middlewares/Third_Party/FatFs/src/ff.c **** /* Definitions of volume - partition conversion */ + 472:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MULTI_PARTITION + 473:Middlewares/Third_Party/FatFs/src/ff.c **** #define LD2PD(vol) VolToPart[vol].pd /* Get physical drive number */ + 474:Middlewares/Third_Party/FatFs/src/ff.c **** #define LD2PT(vol) VolToPart[vol].pt /* Get partition index */ + 475:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 476:Middlewares/Third_Party/FatFs/src/ff.c **** #define LD2PD(vol) (BYTE)(vol) /* Each logical drive is bound to the same physical drive number */ + 477:Middlewares/Third_Party/FatFs/src/ff.c **** #define LD2PT(vol) 0 /* Find first valid partition or in SFD */ + 478:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 479:Middlewares/Third_Party/FatFs/src/ff.c **** + 480:Middlewares/Third_Party/FatFs/src/ff.c **** + 481:Middlewares/Third_Party/FatFs/src/ff.c **** /* Definitions of sector size */ + 482:Middlewares/Third_Party/FatFs/src/ff.c **** #if (_MAX_SS < _MIN_SS) || (_MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096 + 483:Middlewares/Third_Party/FatFs/src/ff.c **** #error Wrong sector size configuration + 484:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 485:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS == _MIN_SS + 486:Middlewares/Third_Party/FatFs/src/ff.c **** #define SS(fs) ((UINT)_MAX_SS) /* Fixed sector size */ + 487:Middlewares/Third_Party/FatFs/src/ff.c **** #else + ARM GAS /tmp/cc2SVLkL.s page 10 + + + 488:Middlewares/Third_Party/FatFs/src/ff.c **** #define SS(fs) ((fs)->ssize) /* Variable sector size */ + 489:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 490:Middlewares/Third_Party/FatFs/src/ff.c **** + 491:Middlewares/Third_Party/FatFs/src/ff.c **** + 492:Middlewares/Third_Party/FatFs/src/ff.c **** /* Timestamp */ + 493:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_NORTC == 1 + 494:Middlewares/Third_Party/FatFs/src/ff.c **** #if _NORTC_YEAR < 1980 || _NORTC_YEAR > 2107 || _NORTC_MON < 1 || _NORTC_MON > 12 || _NORTC_MDAY < + 495:Middlewares/Third_Party/FatFs/src/ff.c **** #error Invalid _FS_NORTC settings + 496:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 497:Middlewares/Third_Party/FatFs/src/ff.c **** #define GET_FATTIME() ((DWORD)(_NORTC_YEAR - 1980) << 25 | (DWORD)_NORTC_MON << 21 | (DWORD)_NORTC_ + 498:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 499:Middlewares/Third_Party/FatFs/src/ff.c **** #define GET_FATTIME() get_fattime() + 500:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 501:Middlewares/Third_Party/FatFs/src/ff.c **** + 502:Middlewares/Third_Party/FatFs/src/ff.c **** + 503:Middlewares/Third_Party/FatFs/src/ff.c **** /* File lock controls */ + 504:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 505:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_READONLY + 506:Middlewares/Third_Party/FatFs/src/ff.c **** #error _FS_LOCK must be 0 at read-only configuration + 507:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 508:Middlewares/Third_Party/FatFs/src/ff.c **** typedef struct { + 509:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; /* Object ID 1, volume (NULL:blank entry) */ + 510:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clu; /* Object ID 2, containing directory (0:root) */ + 511:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD ofs; /* Object ID 3, offset in the directory */ + 512:Middlewares/Third_Party/FatFs/src/ff.c **** WORD ctr; /* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */ + 513:Middlewares/Third_Party/FatFs/src/ff.c **** } FILESEM; + 514:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 515:Middlewares/Third_Party/FatFs/src/ff.c **** + 516:Middlewares/Third_Party/FatFs/src/ff.c **** + 517:Middlewares/Third_Party/FatFs/src/ff.c **** + 518:Middlewares/Third_Party/FatFs/src/ff.c **** + 519:Middlewares/Third_Party/FatFs/src/ff.c **** + 520:Middlewares/Third_Party/FatFs/src/ff.c **** /*-------------------------------------------------------------------------- + 521:Middlewares/Third_Party/FatFs/src/ff.c **** + 522:Middlewares/Third_Party/FatFs/src/ff.c **** Module Private Work Area + 523:Middlewares/Third_Party/FatFs/src/ff.c **** + 524:Middlewares/Third_Party/FatFs/src/ff.c **** ---------------------------------------------------------------------------*/ + 525:Middlewares/Third_Party/FatFs/src/ff.c **** + 526:Middlewares/Third_Party/FatFs/src/ff.c **** /* Remark: Variables defined here without initial value shall be guaranteed + 527:Middlewares/Third_Party/FatFs/src/ff.c **** / zero/null at start-up. If not, the linker option or start-up routine is + 528:Middlewares/Third_Party/FatFs/src/ff.c **** / not compliance with C standard. */ + 529:Middlewares/Third_Party/FatFs/src/ff.c **** + 530:Middlewares/Third_Party/FatFs/src/ff.c **** #if _VOLUMES < 1 || _VOLUMES > 10 + 531:Middlewares/Third_Party/FatFs/src/ff.c **** #error Wrong _VOLUMES setting + 532:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 533:Middlewares/Third_Party/FatFs/src/ff.c **** static FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */ + 534:Middlewares/Third_Party/FatFs/src/ff.c **** static WORD Fsid; /* File system mount ID */ + 535:Middlewares/Third_Party/FatFs/src/ff.c **** + 536:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0 && _VOLUMES >= 2 + 537:Middlewares/Third_Party/FatFs/src/ff.c **** static BYTE CurrVol; /* Current drive */ + 538:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 539:Middlewares/Third_Party/FatFs/src/ff.c **** + 540:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 541:Middlewares/Third_Party/FatFs/src/ff.c **** static FILESEM Files[_FS_LOCK]; /* Open object lock semaphores */ + 542:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 543:Middlewares/Third_Party/FatFs/src/ff.c **** + 544:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN == 0 /* Non-LFN configuration */ + ARM GAS /tmp/cc2SVLkL.s page 11 + + + 545:Middlewares/Third_Party/FatFs/src/ff.c **** #define DEF_NAMBUF + 546:Middlewares/Third_Party/FatFs/src/ff.c **** #define INIT_NAMBUF(fs) + 547:Middlewares/Third_Party/FatFs/src/ff.c **** #define FREE_NAMBUF() + 548:Middlewares/Third_Party/FatFs/src/ff.c **** + 549:Middlewares/Third_Party/FatFs/src/ff.c **** #else /* LFN configuration */ + 550:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_LFN < 12 || _MAX_LFN > 255 + 551:Middlewares/Third_Party/FatFs/src/ff.c **** #error Wrong _MAX_LFN value + 552:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 553:Middlewares/Third_Party/FatFs/src/ff.c **** #define MAXDIRB(nc) ((nc + 44U) / 15 * SZDIRE) + 554:Middlewares/Third_Party/FatFs/src/ff.c **** + 555:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN == 1 /* LFN enabled with static working buffer */ + 556:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 557:Middlewares/Third_Party/FatFs/src/ff.c **** static BYTE DirBuf[MAXDIRB(_MAX_LFN)]; /* Directory entry block scratchpad buffer */ + 558:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 559:Middlewares/Third_Party/FatFs/src/ff.c **** static WCHAR LfnBuf[_MAX_LFN + 1]; /* LFN enabled with static working buffer */ + 560:Middlewares/Third_Party/FatFs/src/ff.c **** #define DEF_NAMBUF + 561:Middlewares/Third_Party/FatFs/src/ff.c **** #define INIT_NAMBUF(fs) + 562:Middlewares/Third_Party/FatFs/src/ff.c **** #define FREE_NAMBUF() + 563:Middlewares/Third_Party/FatFs/src/ff.c **** + 564:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _USE_LFN == 2 /* LFN enabled with dynamic working buffer on the stack */ + 565:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 566:Middlewares/Third_Party/FatFs/src/ff.c **** #define DEF_NAMBUF WCHAR lbuf[_MAX_LFN+1]; BYTE dbuf[MAXDIRB(_MAX_LFN)]; + 567:Middlewares/Third_Party/FatFs/src/ff.c **** #define INIT_NAMBUF(fs) { (fs)->lfnbuf = lbuf; (fs)->dirbuf = dbuf; } + 568:Middlewares/Third_Party/FatFs/src/ff.c **** #define FREE_NAMBUF() + 569:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 570:Middlewares/Third_Party/FatFs/src/ff.c **** #define DEF_NAMBUF WCHAR lbuf[_MAX_LFN+1]; + 571:Middlewares/Third_Party/FatFs/src/ff.c **** #define INIT_NAMBUF(fs) { (fs)->lfnbuf = lbuf; } + 572:Middlewares/Third_Party/FatFs/src/ff.c **** #define FREE_NAMBUF() + 573:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 574:Middlewares/Third_Party/FatFs/src/ff.c **** + 575:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _USE_LFN == 3 /* LFN enabled with dynamic working buffer on the heap */ + 576:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 577:Middlewares/Third_Party/FatFs/src/ff.c **** #define DEF_NAMBUF WCHAR *lfn; + 578:Middlewares/Third_Party/FatFs/src/ff.c **** #define INIT_NAMBUF(fs) { lfn = ff_memalloc((_MAX_LFN+1)*2 + MAXDIRB(_MAX_LFN)); if (!lfn) LEAVE_FF + 579:Middlewares/Third_Party/FatFs/src/ff.c **** #define FREE_NAMBUF() ff_memfree(lfn) + 580:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 581:Middlewares/Third_Party/FatFs/src/ff.c **** #define DEF_NAMBUF WCHAR *lfn; + 582:Middlewares/Third_Party/FatFs/src/ff.c **** #define INIT_NAMBUF(fs) { lfn = ff_memalloc((_MAX_LFN+1)*2); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_C + 583:Middlewares/Third_Party/FatFs/src/ff.c **** #define FREE_NAMBUF() ff_memfree(lfn) + 584:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 585:Middlewares/Third_Party/FatFs/src/ff.c **** + 586:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 587:Middlewares/Third_Party/FatFs/src/ff.c **** #error Wrong _USE_LFN setting + 588:Middlewares/Third_Party/FatFs/src/ff.c **** + 589:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 590:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* else _USE_LFN == 0 */ + 591:Middlewares/Third_Party/FatFs/src/ff.c **** + 592:Middlewares/Third_Party/FatFs/src/ff.c **** #ifdef _EXCVT + 593:Middlewares/Third_Party/FatFs/src/ff.c **** static const BYTE ExCvt[] = _EXCVT; /* Upper conversion table for SBCS extended characters */ + 594:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 595:Middlewares/Third_Party/FatFs/src/ff.c **** + 596:Middlewares/Third_Party/FatFs/src/ff.c **** + 597:Middlewares/Third_Party/FatFs/src/ff.c **** + 598:Middlewares/Third_Party/FatFs/src/ff.c **** + 599:Middlewares/Third_Party/FatFs/src/ff.c **** + 600:Middlewares/Third_Party/FatFs/src/ff.c **** + 601:Middlewares/Third_Party/FatFs/src/ff.c **** /*-------------------------------------------------------------------------- + ARM GAS /tmp/cc2SVLkL.s page 12 + + + 602:Middlewares/Third_Party/FatFs/src/ff.c **** + 603:Middlewares/Third_Party/FatFs/src/ff.c **** Module Private Functions + 604:Middlewares/Third_Party/FatFs/src/ff.c **** + 605:Middlewares/Third_Party/FatFs/src/ff.c **** ---------------------------------------------------------------------------*/ + 606:Middlewares/Third_Party/FatFs/src/ff.c **** + 607:Middlewares/Third_Party/FatFs/src/ff.c **** + 608:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ + 609:Middlewares/Third_Party/FatFs/src/ff.c **** /* Load/Store multi-byte word in the FAT structure */ + 610:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ + 611:Middlewares/Third_Party/FatFs/src/ff.c **** + 612:Middlewares/Third_Party/FatFs/src/ff.c **** static + 613:Middlewares/Third_Party/FatFs/src/ff.c **** WORD ld_word (const BYTE* ptr) /* Load a 2-byte little-endian word */ + 614:Middlewares/Third_Party/FatFs/src/ff.c **** { + 28 .loc 1 614 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 615:Middlewares/Third_Party/FatFs/src/ff.c **** WORD rv; + 33 .loc 1 615 2 view .LVU1 + 616:Middlewares/Third_Party/FatFs/src/ff.c **** + 617:Middlewares/Third_Party/FatFs/src/ff.c **** rv = ptr[1]; + 34 .loc 1 617 2 view .LVU2 + 35 .loc 1 617 10 is_stmt 0 view .LVU3 + 36 0000 4278 ldrb r2, [r0, #1] @ zero_extendqisi2 + 37 .LVL1: + 618:Middlewares/Third_Party/FatFs/src/ff.c **** rv = rv << 8 | ptr[0]; + 38 .loc 1 618 2 is_stmt 1 view .LVU4 + 39 .loc 1 618 20 is_stmt 0 view .LVU5 + 40 0002 0078 ldrb r0, [r0] @ zero_extendqisi2 + 41 .LVL2: + 619:Middlewares/Third_Party/FatFs/src/ff.c **** return rv; + 42 .loc 1 619 2 is_stmt 1 view .LVU6 + 620:Middlewares/Third_Party/FatFs/src/ff.c **** } + 43 .loc 1 620 1 is_stmt 0 view .LVU7 + 44 0004 40EA0220 orr r0, r0, r2, lsl #8 + 45 .LVL3: + 46 .loc 1 620 1 view .LVU8 + 47 0008 7047 bx lr + 48 .cfi_endproc + 49 .LFE1183: + 51 .section .text.ld_dword,"ax",%progbits + 52 .align 1 + 53 .syntax unified + 54 .thumb + 55 .thumb_func + 57 ld_dword: + 58 .LVL4: + 59 .LFB1184: + 621:Middlewares/Third_Party/FatFs/src/ff.c **** + 622:Middlewares/Third_Party/FatFs/src/ff.c **** static + 623:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD ld_dword (const BYTE* ptr) /* Load a 4-byte little-endian word */ + 624:Middlewares/Third_Party/FatFs/src/ff.c **** { + 60 .loc 1 624 1 is_stmt 1 view -0 + 61 .cfi_startproc + 62 @ args = 0, pretend = 0, frame = 0 + 63 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/cc2SVLkL.s page 13 + + + 64 @ link register save eliminated. + 625:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD rv; + 65 .loc 1 625 2 view .LVU10 + 626:Middlewares/Third_Party/FatFs/src/ff.c **** + 627:Middlewares/Third_Party/FatFs/src/ff.c **** rv = ptr[3]; + 66 .loc 1 627 2 view .LVU11 + 67 .loc 1 627 10 is_stmt 0 view .LVU12 + 68 0000 C378 ldrb r3, [r0, #3] @ zero_extendqisi2 + 69 .LVL5: + 628:Middlewares/Third_Party/FatFs/src/ff.c **** rv = rv << 8 | ptr[2]; + 70 .loc 1 628 2 is_stmt 1 view .LVU13 + 71 .loc 1 628 20 is_stmt 0 view .LVU14 + 72 0002 8278 ldrb r2, [r0, #2] @ zero_extendqisi2 + 73 .loc 1 628 5 view .LVU15 + 74 0004 42EA0322 orr r2, r2, r3, lsl #8 + 75 .LVL6: + 629:Middlewares/Third_Party/FatFs/src/ff.c **** rv = rv << 8 | ptr[1]; + 76 .loc 1 629 2 is_stmt 1 view .LVU16 + 77 .loc 1 629 20 is_stmt 0 view .LVU17 + 78 0008 4378 ldrb r3, [r0, #1] @ zero_extendqisi2 + 79 .loc 1 629 5 view .LVU18 + 80 000a 43EA0223 orr r3, r3, r2, lsl #8 + 81 .LVL7: + 630:Middlewares/Third_Party/FatFs/src/ff.c **** rv = rv << 8 | ptr[0]; + 82 .loc 1 630 2 is_stmt 1 view .LVU19 + 83 .loc 1 630 20 is_stmt 0 view .LVU20 + 84 000e 0078 ldrb r0, [r0] @ zero_extendqisi2 + 85 .LVL8: + 631:Middlewares/Third_Party/FatFs/src/ff.c **** return rv; + 86 .loc 1 631 2 is_stmt 1 view .LVU21 + 632:Middlewares/Third_Party/FatFs/src/ff.c **** } + 87 .loc 1 632 1 is_stmt 0 view .LVU22 + 88 0010 40EA0320 orr r0, r0, r3, lsl #8 + 89 .LVL9: + 90 .loc 1 632 1 view .LVU23 + 91 0014 7047 bx lr + 92 .cfi_endproc + 93 .LFE1184: + 95 .section .text.st_word,"ax",%progbits + 96 .align 1 + 97 .syntax unified + 98 .thumb + 99 .thumb_func + 101 st_word: + 102 .LVL10: + 103 .LFB1185: + 633:Middlewares/Third_Party/FatFs/src/ff.c **** + 634:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 635:Middlewares/Third_Party/FatFs/src/ff.c **** static + 636:Middlewares/Third_Party/FatFs/src/ff.c **** QWORD ld_qword (const BYTE* ptr) /* Load an 8-byte little-endian word */ + 637:Middlewares/Third_Party/FatFs/src/ff.c **** { + 638:Middlewares/Third_Party/FatFs/src/ff.c **** QWORD rv; + 639:Middlewares/Third_Party/FatFs/src/ff.c **** + 640:Middlewares/Third_Party/FatFs/src/ff.c **** rv = ptr[7]; + 641:Middlewares/Third_Party/FatFs/src/ff.c **** rv = rv << 8 | ptr[6]; + 642:Middlewares/Third_Party/FatFs/src/ff.c **** rv = rv << 8 | ptr[5]; + 643:Middlewares/Third_Party/FatFs/src/ff.c **** rv = rv << 8 | ptr[4]; + ARM GAS /tmp/cc2SVLkL.s page 14 + + + 644:Middlewares/Third_Party/FatFs/src/ff.c **** rv = rv << 8 | ptr[3]; + 645:Middlewares/Third_Party/FatFs/src/ff.c **** rv = rv << 8 | ptr[2]; + 646:Middlewares/Third_Party/FatFs/src/ff.c **** rv = rv << 8 | ptr[1]; + 647:Middlewares/Third_Party/FatFs/src/ff.c **** rv = rv << 8 | ptr[0]; + 648:Middlewares/Third_Party/FatFs/src/ff.c **** return rv; + 649:Middlewares/Third_Party/FatFs/src/ff.c **** } + 650:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 651:Middlewares/Third_Party/FatFs/src/ff.c **** + 652:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 653:Middlewares/Third_Party/FatFs/src/ff.c **** static + 654:Middlewares/Third_Party/FatFs/src/ff.c **** void st_word (BYTE* ptr, WORD val) /* Store a 2-byte word in little-endian */ + 655:Middlewares/Third_Party/FatFs/src/ff.c **** { + 104 .loc 1 655 1 is_stmt 1 view -0 + 105 .cfi_startproc + 106 @ args = 0, pretend = 0, frame = 0 + 107 @ frame_needed = 0, uses_anonymous_args = 0 + 108 @ link register save eliminated. + 656:Middlewares/Third_Party/FatFs/src/ff.c **** *ptr++ = (BYTE)val; val >>= 8; + 109 .loc 1 656 2 view .LVU25 + 110 .loc 1 656 9 is_stmt 0 view .LVU26 + 111 0000 0170 strb r1, [r0] + 112 .loc 1 656 22 is_stmt 1 view .LVU27 + 113 .LVL11: + 657:Middlewares/Third_Party/FatFs/src/ff.c **** *ptr++ = (BYTE)val; + 114 .loc 1 657 2 view .LVU28 + 115 .loc 1 657 11 is_stmt 0 view .LVU29 + 116 0002 090A lsrs r1, r1, #8 + 117 .loc 1 657 9 view .LVU30 + 118 0004 4170 strb r1, [r0, #1] + 658:Middlewares/Third_Party/FatFs/src/ff.c **** } + 119 .loc 1 658 1 view .LVU31 + 120 0006 7047 bx lr + 121 .cfi_endproc + 122 .LFE1185: + 124 .section .text.st_dword,"ax",%progbits + 125 .align 1 + 126 .syntax unified + 127 .thumb + 128 .thumb_func + 130 st_dword: + 131 .LVL12: + 132 .LFB1186: + 659:Middlewares/Third_Party/FatFs/src/ff.c **** + 660:Middlewares/Third_Party/FatFs/src/ff.c **** static + 661:Middlewares/Third_Party/FatFs/src/ff.c **** void st_dword (BYTE* ptr, DWORD val) /* Store a 4-byte word in little-endian */ + 662:Middlewares/Third_Party/FatFs/src/ff.c **** { + 133 .loc 1 662 1 is_stmt 1 view -0 + 134 .cfi_startproc + 135 @ args = 0, pretend = 0, frame = 0 + 136 @ frame_needed = 0, uses_anonymous_args = 0 + 137 @ link register save eliminated. + 663:Middlewares/Third_Party/FatFs/src/ff.c **** *ptr++ = (BYTE)val; val >>= 8; + 138 .loc 1 663 2 view .LVU33 + 139 .loc 1 663 9 is_stmt 0 view .LVU34 + 140 0000 0170 strb r1, [r0] + 141 .loc 1 663 22 is_stmt 1 view .LVU35 + 142 .LVL13: + ARM GAS /tmp/cc2SVLkL.s page 15 + + + 664:Middlewares/Third_Party/FatFs/src/ff.c **** *ptr++ = (BYTE)val; val >>= 8; + 143 .loc 1 664 2 view .LVU36 + 144 .loc 1 664 11 is_stmt 0 view .LVU37 + 145 0002 C1F30723 ubfx r3, r1, #8, #8 + 146 .loc 1 664 9 view .LVU38 + 147 0006 4370 strb r3, [r0, #1] + 148 .loc 1 664 22 is_stmt 1 view .LVU39 + 149 .LVL14: + 665:Middlewares/Third_Party/FatFs/src/ff.c **** *ptr++ = (BYTE)val; val >>= 8; + 150 .loc 1 665 2 view .LVU40 + 151 .loc 1 665 11 is_stmt 0 view .LVU41 + 152 0008 C1F30743 ubfx r3, r1, #16, #8 + 153 .loc 1 665 9 view .LVU42 + 154 000c 8370 strb r3, [r0, #2] + 155 .loc 1 665 22 is_stmt 1 view .LVU43 + 156 .LVL15: + 666:Middlewares/Third_Party/FatFs/src/ff.c **** *ptr++ = (BYTE)val; + 157 .loc 1 666 2 view .LVU44 + 158 .loc 1 666 11 is_stmt 0 view .LVU45 + 159 000e 090E lsrs r1, r1, #24 + 160 .LVL16: + 161 .loc 1 666 9 view .LVU46 + 162 0010 C170 strb r1, [r0, #3] + 667:Middlewares/Third_Party/FatFs/src/ff.c **** } + 163 .loc 1 667 1 view .LVU47 + 164 0012 7047 bx lr + 165 .cfi_endproc + 166 .LFE1186: + 168 .section .text.mem_cpy,"ax",%progbits + 169 .align 1 + 170 .syntax unified + 171 .thumb + 172 .thumb_func + 174 mem_cpy: + 175 .LVL17: + 176 .LFB1187: + 668:Middlewares/Third_Party/FatFs/src/ff.c **** + 669:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 670:Middlewares/Third_Party/FatFs/src/ff.c **** static + 671:Middlewares/Third_Party/FatFs/src/ff.c **** void st_qword (BYTE* ptr, QWORD val) /* Store an 8-byte word in little-endian */ + 672:Middlewares/Third_Party/FatFs/src/ff.c **** { + 673:Middlewares/Third_Party/FatFs/src/ff.c **** *ptr++ = (BYTE)val; val >>= 8; + 674:Middlewares/Third_Party/FatFs/src/ff.c **** *ptr++ = (BYTE)val; val >>= 8; + 675:Middlewares/Third_Party/FatFs/src/ff.c **** *ptr++ = (BYTE)val; val >>= 8; + 676:Middlewares/Third_Party/FatFs/src/ff.c **** *ptr++ = (BYTE)val; val >>= 8; + 677:Middlewares/Third_Party/FatFs/src/ff.c **** *ptr++ = (BYTE)val; val >>= 8; + 678:Middlewares/Third_Party/FatFs/src/ff.c **** *ptr++ = (BYTE)val; val >>= 8; + 679:Middlewares/Third_Party/FatFs/src/ff.c **** *ptr++ = (BYTE)val; val >>= 8; + 680:Middlewares/Third_Party/FatFs/src/ff.c **** *ptr++ = (BYTE)val; + 681:Middlewares/Third_Party/FatFs/src/ff.c **** } + 682:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 683:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* !_FS_READONLY */ + 684:Middlewares/Third_Party/FatFs/src/ff.c **** + 685:Middlewares/Third_Party/FatFs/src/ff.c **** + 686:Middlewares/Third_Party/FatFs/src/ff.c **** + 687:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ + 688:Middlewares/Third_Party/FatFs/src/ff.c **** /* String functions */ + ARM GAS /tmp/cc2SVLkL.s page 16 + + + 689:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ + 690:Middlewares/Third_Party/FatFs/src/ff.c **** + 691:Middlewares/Third_Party/FatFs/src/ff.c **** /* Copy memory to memory */ + 692:Middlewares/Third_Party/FatFs/src/ff.c **** static + 693:Middlewares/Third_Party/FatFs/src/ff.c **** void mem_cpy (void* dst, const void* src, UINT cnt) { + 177 .loc 1 693 53 is_stmt 1 view -0 + 178 .cfi_startproc + 179 @ args = 0, pretend = 0, frame = 0 + 180 @ frame_needed = 0, uses_anonymous_args = 0 + 181 @ link register save eliminated. + 694:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE *d = (BYTE*)dst; + 182 .loc 1 694 2 view .LVU49 + 695:Middlewares/Third_Party/FatFs/src/ff.c **** const BYTE *s = (const BYTE*)src; + 183 .loc 1 695 2 view .LVU50 + 696:Middlewares/Third_Party/FatFs/src/ff.c **** + 697:Middlewares/Third_Party/FatFs/src/ff.c **** if (cnt) { + 184 .loc 1 697 2 view .LVU51 + 185 .loc 1 697 5 is_stmt 0 view .LVU52 + 186 0000 9446 mov ip, r2 + 187 0002 32B1 cbz r2, .L5 + 188 .LVL18: + 189 .L7: + 698:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 190 .loc 1 698 3 is_stmt 1 view .LVU53 + 699:Middlewares/Third_Party/FatFs/src/ff.c **** *d++ = *s++; + 191 .loc 1 699 4 view .LVU54 + 192 .loc 1 699 11 is_stmt 0 view .LVU55 + 193 0004 0A78 ldrb r2, [r1] @ zero_extendqisi2 + 194 0006 0131 adds r1, r1, #1 + 195 .LVL19: + 196 .loc 1 699 9 view .LVU56 + 197 0008 0270 strb r2, [r0] + 198 000a 0130 adds r0, r0, #1 + 199 .LVL20: + 700:Middlewares/Third_Party/FatFs/src/ff.c **** } while (--cnt); + 200 .loc 1 700 12 is_stmt 1 discriminator 1 view .LVU57 + 201 .loc 1 700 12 is_stmt 0 discriminator 1 view .LVU58 + 202 000c BCF1010C subs ip, ip, #1 + 203 .LVL21: + 204 .loc 1 700 12 discriminator 1 view .LVU59 + 205 0010 F8D1 bne .L7 + 206 .LVL22: + 207 .L5: + 701:Middlewares/Third_Party/FatFs/src/ff.c **** } + 702:Middlewares/Third_Party/FatFs/src/ff.c **** } + 208 .loc 1 702 1 view .LVU60 + 209 0012 7047 bx lr + 210 .cfi_endproc + 211 .LFE1187: + 213 .section .text.mem_set,"ax",%progbits + 214 .align 1 + 215 .syntax unified + 216 .thumb + 217 .thumb_func + 219 mem_set: + 220 .LFB1188: + 703:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 17 + + + 704:Middlewares/Third_Party/FatFs/src/ff.c **** /* Fill memory block */ + 705:Middlewares/Third_Party/FatFs/src/ff.c **** static + 706:Middlewares/Third_Party/FatFs/src/ff.c **** void mem_set (void* dst, int val, UINT cnt) { + 221 .loc 1 706 45 is_stmt 1 view -0 + 222 .cfi_startproc + 223 @ args = 0, pretend = 0, frame = 0 + 224 @ frame_needed = 0, uses_anonymous_args = 0 + 225 @ link register save eliminated. + 226 .LVL23: + 227 .L9: + 707:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE *d = (BYTE*)dst; + 708:Middlewares/Third_Party/FatFs/src/ff.c **** + 709:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 228 .loc 1 709 2 view .LVU62 + 710:Middlewares/Third_Party/FatFs/src/ff.c **** *d++ = (BYTE)val; + 229 .loc 1 710 3 view .LVU63 + 230 .loc 1 710 8 is_stmt 0 view .LVU64 + 231 0000 0170 strb r1, [r0] + 232 0002 0130 adds r0, r0, #1 + 711:Middlewares/Third_Party/FatFs/src/ff.c **** } while (--cnt); + 233 .loc 1 711 11 is_stmt 1 discriminator 1 view .LVU65 + 234 .LVL24: + 235 .loc 1 711 11 is_stmt 0 discriminator 1 view .LVU66 + 236 0004 013A subs r2, r2, #1 + 237 .LVL25: + 238 .loc 1 711 11 discriminator 1 view .LVU67 + 239 0006 FBD1 bne .L9 + 712:Middlewares/Third_Party/FatFs/src/ff.c **** } + 240 .loc 1 712 1 view .LVU68 + 241 0008 7047 bx lr + 242 .cfi_endproc + 243 .LFE1188: + 245 .section .text.mem_cmp,"ax",%progbits + 246 .align 1 + 247 .syntax unified + 248 .thumb + 249 .thumb_func + 251 mem_cmp: + 252 .LVL26: + 253 .LFB1189: + 713:Middlewares/Third_Party/FatFs/src/ff.c **** + 714:Middlewares/Third_Party/FatFs/src/ff.c **** /* Compare memory block */ + 715:Middlewares/Third_Party/FatFs/src/ff.c **** static + 716:Middlewares/Third_Party/FatFs/src/ff.c **** int mem_cmp (const void* dst, const void* src, UINT cnt) { /* ZR:same, NZ:different */ + 254 .loc 1 716 58 is_stmt 1 view -0 + 255 .cfi_startproc + 256 @ args = 0, pretend = 0, frame = 0 + 257 @ frame_needed = 0, uses_anonymous_args = 0 + 258 @ link register save eliminated. + 259 .loc 1 716 58 is_stmt 0 view .LVU70 + 260 0000 8446 mov ip, r0 + 717:Middlewares/Third_Party/FatFs/src/ff.c **** const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src; + 261 .loc 1 717 2 is_stmt 1 view .LVU71 + 262 .LVL27: + 718:Middlewares/Third_Party/FatFs/src/ff.c **** int r = 0; + 263 .loc 1 718 2 view .LVU72 + 264 .L12: + ARM GAS /tmp/cc2SVLkL.s page 18 + + + 719:Middlewares/Third_Party/FatFs/src/ff.c **** + 720:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 265 .loc 1 720 2 view .LVU73 + 721:Middlewares/Third_Party/FatFs/src/ff.c **** r = *d++ - *s++; + 266 .loc 1 721 3 view .LVU74 + 267 .loc 1 721 7 is_stmt 0 view .LVU75 + 268 0002 9CF80000 ldrb r0, [ip] @ zero_extendqisi2 + 269 0006 0CF1010C add ip, ip, #1 + 270 .LVL28: + 271 .loc 1 721 14 view .LVU76 + 272 000a 0B78 ldrb r3, [r1] @ zero_extendqisi2 + 273 000c 0131 adds r1, r1, #1 + 274 .LVL29: + 275 .loc 1 721 5 view .LVU77 + 276 000e C01A subs r0, r0, r3 + 277 .LVL30: + 722:Middlewares/Third_Party/FatFs/src/ff.c **** } while (--cnt && r == 0); + 278 .loc 1 722 17 is_stmt 1 discriminator 2 view .LVU78 + 279 .loc 1 722 17 is_stmt 0 discriminator 2 view .LVU79 + 280 0010 013A subs r2, r2, #1 + 281 .LVL31: + 282 .loc 1 722 17 discriminator 2 view .LVU80 + 283 0012 01D0 beq .L10 + 284 .loc 1 722 17 discriminator 1 view .LVU81 + 285 0014 0028 cmp r0, #0 + 286 0016 F4D0 beq .L12 + 287 .L10: + 723:Middlewares/Third_Party/FatFs/src/ff.c **** + 724:Middlewares/Third_Party/FatFs/src/ff.c **** return r; + 725:Middlewares/Third_Party/FatFs/src/ff.c **** } + 288 .loc 1 725 1 view .LVU82 + 289 0018 7047 bx lr + 290 .cfi_endproc + 291 .LFE1189: + 293 .section .text.chk_chr,"ax",%progbits + 294 .align 1 + 295 .syntax unified + 296 .thumb + 297 .thumb_func + 299 chk_chr: + 300 .LVL32: + 301 .LFB1190: + 726:Middlewares/Third_Party/FatFs/src/ff.c **** + 727:Middlewares/Third_Party/FatFs/src/ff.c **** /* Check if chr is contained in the string */ + 728:Middlewares/Third_Party/FatFs/src/ff.c **** static + 729:Middlewares/Third_Party/FatFs/src/ff.c **** int chk_chr (const char* str, int chr) { /* NZ:contained, ZR:not contained */ + 302 .loc 1 729 40 is_stmt 1 view -0 + 303 .cfi_startproc + 304 @ args = 0, pretend = 0, frame = 0 + 305 @ frame_needed = 0, uses_anonymous_args = 0 + 306 @ link register save eliminated. + 307 .loc 1 729 40 is_stmt 0 view .LVU84 + 308 0000 0346 mov r3, r0 + 730:Middlewares/Third_Party/FatFs/src/ff.c **** while (*str && *str != chr) str++; + 309 .loc 1 730 2 is_stmt 1 view .LVU85 + 310 .loc 1 730 8 is_stmt 0 view .LVU86 + 311 0002 00E0 b .L14 + ARM GAS /tmp/cc2SVLkL.s page 19 + + + 312 .LVL33: + 313 .L16: + 314 .loc 1 730 30 is_stmt 1 discriminator 3 view .LVU87 + 315 .loc 1 730 33 is_stmt 0 discriminator 3 view .LVU88 + 316 0004 0133 adds r3, r3, #1 + 317 .LVL34: + 318 .L14: + 319 .loc 1 730 14 is_stmt 1 discriminator 1 view .LVU89 + 320 .loc 1 730 9 is_stmt 0 discriminator 1 view .LVU90 + 321 0006 1878 ldrb r0, [r3] @ zero_extendqisi2 + 322 .loc 1 730 14 discriminator 1 view .LVU91 + 323 0008 08B1 cbz r0, .L15 + 324 .loc 1 730 14 discriminator 2 view .LVU92 + 325 000a 8842 cmp r0, r1 + 326 000c FAD1 bne .L16 + 327 .L15: + 731:Middlewares/Third_Party/FatFs/src/ff.c **** return *str; + 328 .loc 1 731 2 is_stmt 1 view .LVU93 + 732:Middlewares/Third_Party/FatFs/src/ff.c **** } + 329 .loc 1 732 1 is_stmt 0 view .LVU94 + 330 000e 7047 bx lr + 331 .cfi_endproc + 332 .LFE1190: + 334 .section .text.chk_lock,"ax",%progbits + 335 .align 1 + 336 .syntax unified + 337 .thumb + 338 .thumb_func + 340 chk_lock: + 341 .LVL35: + 342 .LFB1191: + 733:Middlewares/Third_Party/FatFs/src/ff.c **** + 734:Middlewares/Third_Party/FatFs/src/ff.c **** + 735:Middlewares/Third_Party/FatFs/src/ff.c **** + 736:Middlewares/Third_Party/FatFs/src/ff.c **** + 737:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT + 738:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ + 739:Middlewares/Third_Party/FatFs/src/ff.c **** /* Request/Release grant to access the volume */ + 740:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ + 741:Middlewares/Third_Party/FatFs/src/ff.c **** static + 742:Middlewares/Third_Party/FatFs/src/ff.c **** int lock_fs ( + 743:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS* fs /* File system object */ + 744:Middlewares/Third_Party/FatFs/src/ff.c **** ) + 745:Middlewares/Third_Party/FatFs/src/ff.c **** { + 746:Middlewares/Third_Party/FatFs/src/ff.c **** return (fs && ff_req_grant(fs->sobj)) ? 1 : 0; + 747:Middlewares/Third_Party/FatFs/src/ff.c **** } + 748:Middlewares/Third_Party/FatFs/src/ff.c **** + 749:Middlewares/Third_Party/FatFs/src/ff.c **** + 750:Middlewares/Third_Party/FatFs/src/ff.c **** static + 751:Middlewares/Third_Party/FatFs/src/ff.c **** void unlock_fs ( + 752:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS* fs, /* File system object */ + 753:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res /* Result code to be returned */ + 754:Middlewares/Third_Party/FatFs/src/ff.c **** ) + 755:Middlewares/Third_Party/FatFs/src/ff.c **** { + 756:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs && res != FR_NOT_ENABLED && res != FR_INVALID_DRIVE && res != FR_TIMEOUT) { + 757:Middlewares/Third_Party/FatFs/src/ff.c **** ff_rel_grant(fs->sobj); + 758:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 20 + + + 759:Middlewares/Third_Party/FatFs/src/ff.c **** } + 760:Middlewares/Third_Party/FatFs/src/ff.c **** + 761:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 762:Middlewares/Third_Party/FatFs/src/ff.c **** + 763:Middlewares/Third_Party/FatFs/src/ff.c **** + 764:Middlewares/Third_Party/FatFs/src/ff.c **** + 765:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 766:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ + 767:Middlewares/Third_Party/FatFs/src/ff.c **** /* File lock control functions */ + 768:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ + 769:Middlewares/Third_Party/FatFs/src/ff.c **** + 770:Middlewares/Third_Party/FatFs/src/ff.c **** static + 771:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT chk_lock ( /* Check if the file can be accessed */ + 772:Middlewares/Third_Party/FatFs/src/ff.c **** DIR* dp, /* Directory object pointing the file to be checked */ + 773:Middlewares/Third_Party/FatFs/src/ff.c **** int acc /* Desired access type (0:Read, 1:Write, 2:Delete/Rename) */ + 774:Middlewares/Third_Party/FatFs/src/ff.c **** ) + 775:Middlewares/Third_Party/FatFs/src/ff.c **** { + 343 .loc 1 775 1 is_stmt 1 view -0 + 344 .cfi_startproc + 345 @ args = 0, pretend = 0, frame = 0 + 346 @ frame_needed = 0, uses_anonymous_args = 0 + 347 @ link register save eliminated. + 348 .loc 1 775 1 is_stmt 0 view .LVU96 + 349 0000 10B4 push {r4} + 350 .LCFI0: + 351 .cfi_def_cfa_offset 4 + 352 .cfi_offset 4, -4 + 776:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i, be; + 353 .loc 1 776 2 is_stmt 1 view .LVU97 + 777:Middlewares/Third_Party/FatFs/src/ff.c **** + 778:Middlewares/Third_Party/FatFs/src/ff.c **** /* Search file semaphore table */ + 779:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = be = 0; i < _FS_LOCK; i++) { + 354 .loc 1 779 2 view .LVU98 + 355 .LVL36: + 356 .loc 1 779 14 is_stmt 0 view .LVU99 + 357 0002 4FF0000C mov ip, #0 + 358 .loc 1 779 9 view .LVU100 + 359 0006 6346 mov r3, ip + 360 .loc 1 779 2 view .LVU101 + 361 0008 02E0 b .L18 + 362 .LVL37: + 363 .L25: + 780:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs) { /* Existing entry */ + 781:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs == dp->obj.fs && /* Check if the object matched with an open object */ + 782:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].clu == dp->obj.sclust && + 783:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].ofs == dp->dptr) break; + 784:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* Blank entry */ + 785:Middlewares/Third_Party/FatFs/src/ff.c **** be = 1; + 364 .loc 1 785 7 view .LVU102 + 365 000a 4FF0010C mov ip, #1 + 366 .LVL38: + 367 .L19: + 779:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs) { /* Existing entry */ + 368 .loc 1 779 34 is_stmt 1 discriminator 2 view .LVU103 + 369 000e 0133 adds r3, r3, #1 + 370 .LVL39: + 371 .L18: + ARM GAS /tmp/cc2SVLkL.s page 21 + + + 779:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs) { /* Existing entry */ + 372 .loc 1 779 21 discriminator 1 view .LVU104 + 373 0010 012B cmp r3, #1 + 374 0012 15D8 bhi .L20 + 780:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs) { /* Existing entry */ + 375 .loc 1 780 3 view .LVU105 + 780:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs) { /* Existing entry */ + 376 .loc 1 780 15 is_stmt 0 view .LVU106 + 377 0014 1A01 lsls r2, r3, #4 + 378 0016 184C ldr r4, .L32 + 379 0018 A258 ldr r2, [r4, r2] + 780:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs) { /* Existing entry */ + 380 .loc 1 780 6 view .LVU107 + 381 001a 002A cmp r2, #0 + 382 001c F5D0 beq .L25 + 781:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].clu == dp->obj.sclust && + 383 .loc 1 781 4 is_stmt 1 view .LVU108 + 781:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].clu == dp->obj.sclust && + 384 .loc 1 781 30 is_stmt 0 view .LVU109 + 385 001e 0468 ldr r4, [r0] + 781:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].clu == dp->obj.sclust && + 386 .loc 1 781 7 view .LVU110 + 387 0020 A242 cmp r2, r4 + 388 0022 F4D1 bne .L19 + 782:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].ofs == dp->dptr) break; + 389 .loc 1 782 13 view .LVU111 + 390 0024 144A ldr r2, .L32 + 391 0026 02EB0312 add r2, r2, r3, lsl #4 + 392 002a 5468 ldr r4, [r2, #4] + 782:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].ofs == dp->dptr) break; + 393 .loc 1 782 28 view .LVU112 + 394 002c 8268 ldr r2, [r0, #8] + 781:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].clu == dp->obj.sclust && + 395 .loc 1 781 34 discriminator 1 view .LVU113 + 396 002e 9442 cmp r4, r2 + 397 0030 EDD1 bne .L19 + 783:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* Blank entry */ + 398 .loc 1 783 13 view .LVU114 + 399 0032 114A ldr r2, .L32 + 400 0034 02EB0312 add r2, r2, r3, lsl #4 + 401 0038 9468 ldr r4, [r2, #8] + 783:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* Blank entry */ + 402 .loc 1 783 23 view .LVU115 + 403 003a 4269 ldr r2, [r0, #20] + 782:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].ofs == dp->dptr) break; + 404 .loc 1 782 36 view .LVU116 + 405 003c 9442 cmp r4, r2 + 406 003e E6D1 bne .L19 + 407 .L20: + 786:Middlewares/Third_Party/FatFs/src/ff.c **** } + 787:Middlewares/Third_Party/FatFs/src/ff.c **** } + 788:Middlewares/Third_Party/FatFs/src/ff.c **** if (i == _FS_LOCK) { /* The object is not opened */ + 408 .loc 1 788 2 is_stmt 1 view .LVU117 + 409 .loc 1 788 5 is_stmt 0 view .LVU118 + 410 0040 022B cmp r3, #2 + 411 0042 0BD0 beq .L30 + 789:Middlewares/Third_Party/FatFs/src/ff.c **** return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new objec + ARM GAS /tmp/cc2SVLkL.s page 22 + + + 790:Middlewares/Third_Party/FatFs/src/ff.c **** } + 791:Middlewares/Third_Party/FatFs/src/ff.c **** + 792:Middlewares/Third_Party/FatFs/src/ff.c **** /* The object has been opened. Reject any open against writing file and all write mode open */ + 793:Middlewares/Third_Party/FatFs/src/ff.c **** return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK; + 412 .loc 1 793 2 is_stmt 1 view .LVU119 + 413 .loc 1 793 52 is_stmt 0 view .LVU120 + 414 0044 B1B9 cbnz r1, .L27 + 415 .loc 1 793 25 discriminator 2 view .LVU121 + 416 0046 0C4A ldr r2, .L32 + 417 0048 02EB0313 add r3, r2, r3, lsl #4 + 418 .LVL40: + 419 .loc 1 793 25 discriminator 2 view .LVU122 + 420 004c 9B89 ldrh r3, [r3, #12] + 421 .loc 1 793 14 discriminator 2 view .LVU123 + 422 004e B3F5807F cmp r3, #256 + 423 0052 0DD0 beq .L31 + 424 .loc 1 793 52 discriminator 4 view .LVU124 + 425 0054 0020 movs r0, #0 + 426 .LVL41: + 427 .L24: + 794:Middlewares/Third_Party/FatFs/src/ff.c **** } + 428 .loc 1 794 1 view .LVU125 + 429 0056 5DF8044B ldr r4, [sp], #4 + 430 .LCFI1: + 431 .cfi_remember_state + 432 .cfi_restore 4 + 433 .cfi_def_cfa_offset 0 + 434 005a 7047 bx lr + 435 .LVL42: + 436 .L30: + 437 .LCFI2: + 438 .cfi_restore_state + 789:Middlewares/Third_Party/FatFs/src/ff.c **** return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new objec + 439 .loc 1 789 3 is_stmt 1 view .LVU126 + 789:Middlewares/Third_Party/FatFs/src/ff.c **** return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new objec + 440 .loc 1 789 14 is_stmt 0 view .LVU127 + 441 005c 0229 cmp r1, #2 + 442 005e 14BF ite ne + 443 0060 6346 movne r3, ip + 444 0062 4CF00103 orreq r3, ip, #1 + 445 .LVL43: + 789:Middlewares/Third_Party/FatFs/src/ff.c **** return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new objec + 446 .loc 1 789 35 view .LVU128 + 447 0066 0BB1 cbz r3, .L26 + 789:Middlewares/Third_Party/FatFs/src/ff.c **** return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new objec + 448 .loc 1 789 35 discriminator 1 view .LVU129 + 449 0068 0020 movs r0, #0 + 450 .LVL44: + 789:Middlewares/Third_Party/FatFs/src/ff.c **** return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new objec + 451 .loc 1 789 35 discriminator 1 view .LVU130 + 452 006a F4E7 b .L24 + 453 .LVL45: + 454 .L26: + 789:Middlewares/Third_Party/FatFs/src/ff.c **** return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new objec + 455 .loc 1 789 35 discriminator 2 view .LVU131 + 456 006c 1220 movs r0, #18 + 457 .LVL46: + ARM GAS /tmp/cc2SVLkL.s page 23 + + + 789:Middlewares/Third_Party/FatFs/src/ff.c **** return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new objec + 458 .loc 1 789 35 view .LVU132 + 459 006e F2E7 b .L24 + 460 .LVL47: + 461 .L31: + 793:Middlewares/Third_Party/FatFs/src/ff.c **** } + 462 .loc 1 793 52 discriminator 3 view .LVU133 + 463 0070 1020 movs r0, #16 + 464 .LVL48: + 793:Middlewares/Third_Party/FatFs/src/ff.c **** } + 465 .loc 1 793 52 discriminator 3 view .LVU134 + 466 0072 F0E7 b .L24 + 467 .LVL49: + 468 .L27: + 793:Middlewares/Third_Party/FatFs/src/ff.c **** } + 469 .loc 1 793 52 discriminator 3 view .LVU135 + 470 0074 1020 movs r0, #16 + 471 .LVL50: + 793:Middlewares/Third_Party/FatFs/src/ff.c **** } + 472 .loc 1 793 52 discriminator 3 view .LVU136 + 473 0076 EEE7 b .L24 + 474 .L33: + 475 .align 2 + 476 .L32: + 477 0078 00000000 .word Files + 478 .cfi_endproc + 479 .LFE1191: + 481 .section .text.enq_lock,"ax",%progbits + 482 .align 1 + 483 .syntax unified + 484 .thumb + 485 .thumb_func + 487 enq_lock: + 488 .LFB1192: + 795:Middlewares/Third_Party/FatFs/src/ff.c **** + 796:Middlewares/Third_Party/FatFs/src/ff.c **** + 797:Middlewares/Third_Party/FatFs/src/ff.c **** static + 798:Middlewares/Third_Party/FatFs/src/ff.c **** int enq_lock (void) /* Check if an entry is available for a new object */ + 799:Middlewares/Third_Party/FatFs/src/ff.c **** { + 489 .loc 1 799 1 is_stmt 1 view -0 + 490 .cfi_startproc + 491 @ args = 0, pretend = 0, frame = 0 + 492 @ frame_needed = 0, uses_anonymous_args = 0 + 493 @ link register save eliminated. + 800:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i; + 494 .loc 1 800 2 view .LVU138 + 801:Middlewares/Third_Party/FatFs/src/ff.c **** + 802:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ; + 495 .loc 1 802 2 view .LVU139 + 496 .LVL51: + 497 .loc 1 802 9 is_stmt 0 view .LVU140 + 498 0000 0020 movs r0, #0 + 499 .loc 1 802 2 view .LVU141 + 500 0002 00E0 b .L35 + 501 .LVL52: + 502 .L37: + 503 .loc 1 802 44 is_stmt 1 discriminator 4 view .LVU142 + ARM GAS /tmp/cc2SVLkL.s page 24 + + + 504 0004 0130 adds r0, r0, #1 + 505 .LVL53: + 506 .L35: + 507 .loc 1 802 27 discriminator 1 view .LVU143 + 508 0006 0128 cmp r0, #1 + 509 0008 04D8 bhi .L36 + 510 .loc 1 802 38 is_stmt 0 discriminator 3 view .LVU144 + 511 000a 0301 lsls r3, r0, #4 + 512 000c 034A ldr r2, .L38 + 513 000e D358 ldr r3, [r2, r3] + 514 .loc 1 802 27 discriminator 3 view .LVU145 + 515 0010 002B cmp r3, #0 + 516 0012 F7D1 bne .L37 + 517 .L36: + 803:Middlewares/Third_Party/FatFs/src/ff.c **** return (i == _FS_LOCK) ? 0 : 1; + 518 .loc 1 803 2 is_stmt 1 view .LVU146 + 804:Middlewares/Third_Party/FatFs/src/ff.c **** } + 519 .loc 1 804 1 is_stmt 0 view .LVU147 + 520 0014 0238 subs r0, r0, #2 + 521 .LVL54: + 522 .loc 1 804 1 view .LVU148 + 523 0016 18BF it ne + 524 0018 0120 movne r0, #1 + 525 .LVL55: + 526 .loc 1 804 1 view .LVU149 + 527 001a 7047 bx lr + 528 .L39: + 529 .align 2 + 530 .L38: + 531 001c 00000000 .word Files + 532 .cfi_endproc + 533 .LFE1192: + 535 .section .text.inc_lock,"ax",%progbits + 536 .align 1 + 537 .syntax unified + 538 .thumb + 539 .thumb_func + 541 inc_lock: + 542 .LVL56: + 543 .LFB1193: + 805:Middlewares/Third_Party/FatFs/src/ff.c **** + 806:Middlewares/Third_Party/FatFs/src/ff.c **** + 807:Middlewares/Third_Party/FatFs/src/ff.c **** static + 808:Middlewares/Third_Party/FatFs/src/ff.c **** UINT inc_lock ( /* Increment object open counter and returns its index (0:Internal error) */ + 809:Middlewares/Third_Party/FatFs/src/ff.c **** DIR* dp, /* Directory object pointing the file to register or increment */ + 810:Middlewares/Third_Party/FatFs/src/ff.c **** int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ + 811:Middlewares/Third_Party/FatFs/src/ff.c **** ) + 812:Middlewares/Third_Party/FatFs/src/ff.c **** { + 544 .loc 1 812 1 is_stmt 1 view -0 + 545 .cfi_startproc + 546 @ args = 0, pretend = 0, frame = 0 + 547 @ frame_needed = 0, uses_anonymous_args = 0 + 548 @ link register save eliminated. + 549 .loc 1 812 1 is_stmt 0 view .LVU151 + 550 0000 70B4 push {r4, r5, r6} + 551 .LCFI3: + 552 .cfi_def_cfa_offset 12 + ARM GAS /tmp/cc2SVLkL.s page 25 + + + 553 .cfi_offset 4, -12 + 554 .cfi_offset 5, -8 + 555 .cfi_offset 6, -4 + 813:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i; + 556 .loc 1 813 2 is_stmt 1 view .LVU152 + 814:Middlewares/Third_Party/FatFs/src/ff.c **** + 815:Middlewares/Third_Party/FatFs/src/ff.c **** + 816:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < _FS_LOCK; i++) { /* Find the object */ + 557 .loc 1 816 2 view .LVU153 + 558 .LVL57: + 559 .loc 1 816 9 is_stmt 0 view .LVU154 + 560 0002 0023 movs r3, #0 + 561 .loc 1 816 2 view .LVU155 + 562 0004 00E0 b .L41 + 563 .LVL58: + 564 .L42: + 565 .loc 1 816 29 is_stmt 1 discriminator 2 view .LVU156 + 566 0006 0133 adds r3, r3, #1 + 567 .LVL59: + 568 .L41: + 569 .loc 1 816 16 discriminator 1 view .LVU157 + 570 0008 012B cmp r3, #1 + 571 000a 13D8 bhi .L43 + 817:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs == dp->obj.fs && + 572 .loc 1 817 3 view .LVU158 + 573 .loc 1 817 15 is_stmt 0 view .LVU159 + 574 000c 1A01 lsls r2, r3, #4 + 575 000e 234C ldr r4, .L57 + 576 0010 A458 ldr r4, [r4, r2] + 577 .loc 1 817 29 view .LVU160 + 578 0012 0268 ldr r2, [r0] + 579 .loc 1 817 6 view .LVU161 + 580 0014 9442 cmp r4, r2 + 581 0016 F6D1 bne .L42 + 818:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].clu == dp->obj.sclust && + 582 .loc 1 818 12 view .LVU162 + 583 0018 204A ldr r2, .L57 + 584 001a 02EB0312 add r2, r2, r3, lsl #4 + 585 001e 5468 ldr r4, [r2, #4] + 586 .loc 1 818 27 view .LVU163 + 587 0020 8268 ldr r2, [r0, #8] + 817:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs == dp->obj.fs && + 588 .loc 1 817 33 discriminator 1 view .LVU164 + 589 0022 9442 cmp r4, r2 + 590 0024 EFD1 bne .L42 + 819:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].ofs == dp->dptr) break; + 591 .loc 1 819 12 view .LVU165 + 592 0026 1D4A ldr r2, .L57 + 593 0028 02EB0312 add r2, r2, r3, lsl #4 + 594 002c 9468 ldr r4, [r2, #8] + 595 .loc 1 819 22 view .LVU166 + 596 002e 4269 ldr r2, [r0, #20] + 818:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].clu == dp->obj.sclust && + 597 .loc 1 818 35 view .LVU167 + 598 0030 9442 cmp r4, r2 + 599 0032 E8D1 bne .L42 + 600 .L43: + ARM GAS /tmp/cc2SVLkL.s page 26 + + + 820:Middlewares/Third_Party/FatFs/src/ff.c **** } + 821:Middlewares/Third_Party/FatFs/src/ff.c **** + 822:Middlewares/Third_Party/FatFs/src/ff.c **** if (i == _FS_LOCK) { /* Not opened. Register it as new. */ + 601 .loc 1 822 2 is_stmt 1 view .LVU168 + 602 .loc 1 822 5 is_stmt 0 view .LVU169 + 603 0034 022B cmp r3, #2 + 604 0036 08D0 beq .L56 + 605 .LVL60: + 606 .L46: + 823:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ; + 824:Middlewares/Third_Party/FatFs/src/ff.c **** if (i == _FS_LOCK) return 0; /* No free entry to register (int err) */ + 825:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].fs = dp->obj.fs; + 826:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].clu = dp->obj.sclust; + 827:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].ofs = dp->dptr; + 828:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].ctr = 0; + 829:Middlewares/Third_Party/FatFs/src/ff.c **** } + 830:Middlewares/Third_Party/FatFs/src/ff.c **** + 831:Middlewares/Third_Party/FatFs/src/ff.c **** if (acc && Files[i].ctr) return 0; /* Access violation (int err) */ + 607 .loc 1 831 2 is_stmt 1 view .LVU170 + 608 .loc 1 831 5 is_stmt 0 view .LVU171 + 609 0038 F9B1 cbz r1, .L50 + 610 .loc 1 831 21 discriminator 1 view .LVU172 + 611 003a 184A ldr r2, .L57 + 612 003c 02EB0312 add r2, r2, r3, lsl #4 + 613 0040 9289 ldrh r2, [r2, #12] + 614 .loc 1 831 10 discriminator 1 view .LVU173 + 615 0042 4ABB cbnz r2, .L54 + 832:Middlewares/Third_Party/FatFs/src/ff.c **** + 833:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */ + 616 .loc 1 833 15 discriminator 2 view .LVU174 + 617 0044 4FF48072 mov r2, #256 + 618 0048 1DE0 b .L51 + 619 .LVL61: + 620 .L56: + 823:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ; + 621 .loc 1 823 10 view .LVU175 + 622 004a 0023 movs r3, #0 + 623 .LVL62: + 624 .L45: + 823:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ; + 625 .loc 1 823 28 is_stmt 1 discriminator 1 view .LVU176 + 626 004c 012B cmp r3, #1 + 627 004e 05D8 bhi .L47 + 823:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ; + 628 .loc 1 823 39 is_stmt 0 discriminator 3 view .LVU177 + 629 0050 1A01 lsls r2, r3, #4 + 630 0052 124C ldr r4, .L57 + 631 0054 A258 ldr r2, [r4, r2] + 823:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ; + 632 .loc 1 823 28 discriminator 3 view .LVU178 + 633 0056 0AB1 cbz r2, .L47 + 823:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ; + 634 .loc 1 823 45 is_stmt 1 discriminator 4 view .LVU179 + 635 0058 0133 adds r3, r3, #1 + 636 .LVL63: + 823:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ; + 637 .loc 1 823 45 is_stmt 0 discriminator 4 view .LVU180 + ARM GAS /tmp/cc2SVLkL.s page 27 + + + 638 005a F7E7 b .L45 + 639 .L47: + 824:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].fs = dp->obj.fs; + 640 .loc 1 824 3 is_stmt 1 view .LVU181 + 824:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].fs = dp->obj.fs; + 641 .loc 1 824 6 is_stmt 0 view .LVU182 + 642 005c 022B cmp r3, #2 + 643 005e 19D0 beq .L53 + 825:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].clu = dp->obj.sclust; + 644 .loc 1 825 3 is_stmt 1 view .LVU183 + 825:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].clu = dp->obj.sclust; + 645 .loc 1 825 15 is_stmt 0 view .LVU184 + 646 0060 0E4D ldr r5, .L57 + 647 0062 1C01 lsls r4, r3, #4 + 648 0064 05EB0312 add r2, r5, r3, lsl #4 + 649 0068 0668 ldr r6, [r0] + 650 006a 2E51 str r6, [r5, r4] + 826:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].ofs = dp->dptr; + 651 .loc 1 826 3 is_stmt 1 view .LVU185 + 826:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].ofs = dp->dptr; + 652 .loc 1 826 25 is_stmt 0 view .LVU186 + 653 006c 8468 ldr r4, [r0, #8] + 826:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].ofs = dp->dptr; + 654 .loc 1 826 16 view .LVU187 + 655 006e 5460 str r4, [r2, #4] + 827:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].ctr = 0; + 656 .loc 1 827 3 is_stmt 1 view .LVU188 + 827:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].ctr = 0; + 657 .loc 1 827 20 is_stmt 0 view .LVU189 + 658 0070 4069 ldr r0, [r0, #20] + 659 .LVL64: + 827:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].ctr = 0; + 660 .loc 1 827 16 view .LVU190 + 661 0072 9060 str r0, [r2, #8] + 828:Middlewares/Third_Party/FatFs/src/ff.c **** } + 662 .loc 1 828 3 is_stmt 1 view .LVU191 + 828:Middlewares/Third_Party/FatFs/src/ff.c **** } + 663 .loc 1 828 16 is_stmt 0 view .LVU192 + 664 0074 0020 movs r0, #0 + 665 0076 9081 strh r0, [r2, #12] @ movhi + 666 0078 DEE7 b .L46 + 667 .L50: + 668 .loc 1 833 39 discriminator 1 view .LVU193 + 669 007a 084A ldr r2, .L57 + 670 007c 02EB0312 add r2, r2, r3, lsl #4 + 671 0080 9289 ldrh r2, [r2, #12] + 672 .loc 1 833 15 discriminator 1 view .LVU194 + 673 0082 0132 adds r2, r2, #1 + 674 0084 92B2 uxth r2, r2 + 675 .L51: + 676 .loc 1 833 15 discriminator 4 view .LVU195 + 677 0086 0549 ldr r1, .L57 + 678 .LVL65: + 679 .loc 1 833 15 discriminator 4 view .LVU196 + 680 0088 01EB0311 add r1, r1, r3, lsl #4 + 681 008c 8A81 strh r2, [r1, #12] @ movhi + 834:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 28 + + + 835:Middlewares/Third_Party/FatFs/src/ff.c **** return i + 1; + 682 .loc 1 835 2 is_stmt 1 view .LVU197 + 683 .loc 1 835 11 is_stmt 0 view .LVU198 + 684 008e 581C adds r0, r3, #1 + 685 .L40: + 836:Middlewares/Third_Party/FatFs/src/ff.c **** } + 686 .loc 1 836 1 view .LVU199 + 687 0090 70BC pop {r4, r5, r6} + 688 .LCFI4: + 689 .cfi_remember_state + 690 .cfi_restore 6 + 691 .cfi_restore 5 + 692 .cfi_restore 4 + 693 .cfi_def_cfa_offset 0 + 694 0092 7047 bx lr + 695 .LVL66: + 696 .L53: + 697 .LCFI5: + 698 .cfi_restore_state + 824:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].fs = dp->obj.fs; + 699 .loc 1 824 29 discriminator 1 view .LVU200 + 700 0094 0020 movs r0, #0 + 701 .LVL67: + 824:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].fs = dp->obj.fs; + 702 .loc 1 824 29 discriminator 1 view .LVU201 + 703 0096 FBE7 b .L40 + 704 .L54: + 831:Middlewares/Third_Party/FatFs/src/ff.c **** + 705 .loc 1 831 34 discriminator 2 view .LVU202 + 706 0098 0020 movs r0, #0 + 707 009a F9E7 b .L40 + 708 .L58: + 709 .align 2 + 710 .L57: + 711 009c 00000000 .word Files + 712 .cfi_endproc + 713 .LFE1193: + 715 .section .text.dec_lock,"ax",%progbits + 716 .align 1 + 717 .syntax unified + 718 .thumb + 719 .thumb_func + 721 dec_lock: + 722 .LVL68: + 723 .LFB1194: + 837:Middlewares/Third_Party/FatFs/src/ff.c **** + 838:Middlewares/Third_Party/FatFs/src/ff.c **** + 839:Middlewares/Third_Party/FatFs/src/ff.c **** static + 840:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT dec_lock ( /* Decrement object open counter */ + 841:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i /* Semaphore index (1..) */ + 842:Middlewares/Third_Party/FatFs/src/ff.c **** ) + 843:Middlewares/Third_Party/FatFs/src/ff.c **** { + 724 .loc 1 843 1 is_stmt 1 view -0 + 725 .cfi_startproc + 726 @ args = 0, pretend = 0, frame = 0 + 727 @ frame_needed = 0, uses_anonymous_args = 0 + 728 @ link register save eliminated. + ARM GAS /tmp/cc2SVLkL.s page 29 + + + 844:Middlewares/Third_Party/FatFs/src/ff.c **** WORD n; + 729 .loc 1 844 2 view .LVU204 + 845:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 730 .loc 1 845 2 view .LVU205 + 846:Middlewares/Third_Party/FatFs/src/ff.c **** + 847:Middlewares/Third_Party/FatFs/src/ff.c **** + 848:Middlewares/Third_Party/FatFs/src/ff.c **** if (--i < _FS_LOCK) { /* Shift index number origin from 0 */ + 731 .loc 1 848 2 view .LVU206 + 732 .loc 1 848 5 is_stmt 0 view .LVU207 + 733 0000 0138 subs r0, r0, #1 + 734 .LVL69: + 735 .loc 1 848 5 view .LVU208 + 736 0002 0128 cmp r0, #1 + 737 0004 15D8 bhi .L63 + 849:Middlewares/Third_Party/FatFs/src/ff.c **** n = Files[i].ctr; + 738 .loc 1 849 3 is_stmt 1 view .LVU209 + 739 .loc 1 849 5 is_stmt 0 view .LVU210 + 740 0006 0D4B ldr r3, .L66 + 741 0008 03EB0013 add r3, r3, r0, lsl #4 + 742 000c 9B89 ldrh r3, [r3, #12] + 743 .LVL70: + 850:Middlewares/Third_Party/FatFs/src/ff.c **** if (n == 0x100) n = 0; /* If write mode open, delete the entry */ + 744 .loc 1 850 3 is_stmt 1 view .LVU211 + 745 .loc 1 850 6 is_stmt 0 view .LVU212 + 746 000e B3F5807F cmp r3, #256 + 747 0012 03D0 beq .L64 + 851:Middlewares/Third_Party/FatFs/src/ff.c **** if (n > 0) n--; /* Decrement read mode open count */ + 748 .loc 1 851 3 is_stmt 1 view .LVU213 + 749 .loc 1 851 6 is_stmt 0 view .LVU214 + 750 0014 43B1 cbz r3, .L62 + 751 .loc 1 851 14 is_stmt 1 discriminator 1 view .LVU215 + 752 .loc 1 851 15 is_stmt 0 discriminator 1 view .LVU216 + 753 0016 013B subs r3, r3, #1 + 754 .LVL71: + 755 .loc 1 851 15 discriminator 1 view .LVU217 + 756 0018 9BB2 uxth r3, r3 + 757 .LVL72: + 758 .loc 1 851 15 discriminator 1 view .LVU218 + 759 001a 00E0 b .L61 + 760 .L64: + 850:Middlewares/Third_Party/FatFs/src/ff.c **** if (n == 0x100) n = 0; /* If write mode open, delete the entry */ + 761 .loc 1 850 21 discriminator 1 view .LVU219 + 762 001c 0023 movs r3, #0 + 763 .LVL73: + 764 .L61: + 852:Middlewares/Third_Party/FatFs/src/ff.c **** Files[i].ctr = n; + 765 .loc 1 852 3 is_stmt 1 view .LVU220 + 766 .loc 1 852 16 is_stmt 0 view .LVU221 + 767 001e 074A ldr r2, .L66 + 768 0020 02EB0012 add r2, r2, r0, lsl #4 + 769 0024 9381 strh r3, [r2, #12] @ movhi + 853:Middlewares/Third_Party/FatFs/src/ff.c **** if (n == 0) Files[i].fs = 0; /* Delete the entry if open count gets zero */ + 770 .loc 1 853 3 is_stmt 1 view .LVU222 + 771 .loc 1 853 6 is_stmt 0 view .LVU223 + 772 0026 33B9 cbnz r3, .L65 + 773 .L62: + 774 .LVL74: + ARM GAS /tmp/cc2SVLkL.s page 30 + + + 775 .loc 1 853 15 is_stmt 1 discriminator 1 view .LVU224 + 776 .loc 1 853 27 is_stmt 0 discriminator 1 view .LVU225 + 777 0028 0301 lsls r3, r0, #4 + 778 002a 0020 movs r0, #0 + 779 .LVL75: + 780 .loc 1 853 27 discriminator 1 view .LVU226 + 781 002c 034A ldr r2, .L66 + 782 002e D050 str r0, [r2, r3] + 783 0030 7047 bx lr + 784 .LVL76: + 785 .L63: + 854:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; + 855:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 856:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INT_ERR; /* Invalid index nunber */ + 786 .loc 1 856 7 view .LVU227 + 787 0032 0220 movs r0, #2 + 788 .LVL77: + 789 .loc 1 856 7 view .LVU228 + 790 0034 7047 bx lr + 791 .LVL78: + 792 .L65: + 854:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; + 793 .loc 1 854 7 view .LVU229 + 794 0036 0020 movs r0, #0 + 795 .LVL79: + 857:Middlewares/Third_Party/FatFs/src/ff.c **** } + 858:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 796 .loc 1 858 2 is_stmt 1 view .LVU230 + 859:Middlewares/Third_Party/FatFs/src/ff.c **** } + 797 .loc 1 859 1 is_stmt 0 view .LVU231 + 798 0038 7047 bx lr + 799 .L67: + 800 003a 00BF .align 2 + 801 .L66: + 802 003c 00000000 .word Files + 803 .cfi_endproc + 804 .LFE1194: + 806 .section .text.clear_lock,"ax",%progbits + 807 .align 1 + 808 .syntax unified + 809 .thumb + 810 .thumb_func + 812 clear_lock: + 813 .LVL80: + 814 .LFB1195: + 860:Middlewares/Third_Party/FatFs/src/ff.c **** + 861:Middlewares/Third_Party/FatFs/src/ff.c **** + 862:Middlewares/Third_Party/FatFs/src/ff.c **** static + 863:Middlewares/Third_Party/FatFs/src/ff.c **** void clear_lock ( /* Clear lock entries of the volume */ + 864:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs + 865:Middlewares/Third_Party/FatFs/src/ff.c **** ) + 866:Middlewares/Third_Party/FatFs/src/ff.c **** { + 815 .loc 1 866 1 is_stmt 1 view -0 + 816 .cfi_startproc + 817 @ args = 0, pretend = 0, frame = 0 + 818 @ frame_needed = 0, uses_anonymous_args = 0 + 819 @ link register save eliminated. + ARM GAS /tmp/cc2SVLkL.s page 31 + + + 867:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i; + 820 .loc 1 867 2 view .LVU233 + 868:Middlewares/Third_Party/FatFs/src/ff.c **** + 869:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < _FS_LOCK; i++) { + 821 .loc 1 869 2 view .LVU234 + 822 .loc 1 869 9 is_stmt 0 view .LVU235 + 823 0000 0023 movs r3, #0 + 824 .loc 1 869 2 view .LVU236 + 825 0002 03E0 b .L73 + 826 .LVL81: + 827 .L80: + 828 .LCFI6: + 829 .cfi_def_cfa_offset 4 + 830 .cfi_offset 4, -4 + 870:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs == fs) Files[i].fs = 0; + 871:Middlewares/Third_Party/FatFs/src/ff.c **** } + 872:Middlewares/Third_Party/FatFs/src/ff.c **** } + 831 .loc 1 872 1 view .LVU237 + 832 0004 5DF8044B ldr r4, [sp], #4 + 833 .LCFI7: + 834 .cfi_restore 4 + 835 .cfi_def_cfa_offset 0 + 836 0008 7047 bx lr + 837 .L79: + 869:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs == fs) Files[i].fs = 0; + 838 .loc 1 869 29 is_stmt 1 discriminator 2 view .LVU238 + 839 000a 0133 adds r3, r3, #1 + 840 .LVL82: + 841 .L73: + 869:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs == fs) Files[i].fs = 0; + 842 .loc 1 869 16 discriminator 1 view .LVU239 + 843 000c 012B cmp r3, #1 + 844 000e 11D8 bhi .L78 + 870:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs == fs) Files[i].fs = 0; + 845 .loc 1 870 3 view .LVU240 + 870:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs == fs) Files[i].fs = 0; + 846 .loc 1 870 15 is_stmt 0 view .LVU241 + 847 0010 1A01 lsls r2, r3, #4 + 848 0012 0949 ldr r1, .L81 + 849 0014 8A58 ldr r2, [r1, r2] + 870:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs == fs) Files[i].fs = 0; + 850 .loc 1 870 6 view .LVU242 + 851 0016 8242 cmp r2, r0 + 852 0018 F7D1 bne .L79 + 866:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i; + 853 .loc 1 866 1 view .LVU243 + 854 001a 10B4 push {r4} + 855 .LCFI8: + 856 .cfi_def_cfa_offset 4 + 857 .cfi_offset 4, -4 + 858 .L74: + 870:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs == fs) Files[i].fs = 0; + 859 .loc 1 870 26 is_stmt 1 discriminator 1 view .LVU244 + 870:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs == fs) Files[i].fs = 0; + 860 .loc 1 870 38 is_stmt 0 discriminator 1 view .LVU245 + 861 001c 1A01 lsls r2, r3, #4 + 862 001e 0024 movs r4, #0 + ARM GAS /tmp/cc2SVLkL.s page 32 + + + 863 0020 8C50 str r4, [r1, r2] + 864 .L70: + 869:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs == fs) Files[i].fs = 0; + 865 .loc 1 869 29 is_stmt 1 discriminator 2 view .LVU246 + 866 0022 0133 adds r3, r3, #1 + 867 .LVL83: + 869:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs == fs) Files[i].fs = 0; + 868 .loc 1 869 16 discriminator 1 view .LVU247 + 869 0024 012B cmp r3, #1 + 870 0026 EDD8 bhi .L80 + 870:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs == fs) Files[i].fs = 0; + 871 .loc 1 870 3 view .LVU248 + 870:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs == fs) Files[i].fs = 0; + 872 .loc 1 870 15 is_stmt 0 view .LVU249 + 873 0028 1A01 lsls r2, r3, #4 + 874 002a 0349 ldr r1, .L81 + 875 002c 8A58 ldr r2, [r1, r2] + 870:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs == fs) Files[i].fs = 0; + 876 .loc 1 870 6 view .LVU250 + 877 002e 8242 cmp r2, r0 + 878 0030 F7D1 bne .L70 + 879 0032 F3E7 b .L74 + 880 .L78: + 881 .LCFI9: + 882 .cfi_def_cfa_offset 0 + 883 .cfi_restore 4 + 870:Middlewares/Third_Party/FatFs/src/ff.c **** if (Files[i].fs == fs) Files[i].fs = 0; + 884 .loc 1 870 6 view .LVU251 + 885 0034 7047 bx lr + 886 .L82: + 887 0036 00BF .align 2 + 888 .L81: + 889 0038 00000000 .word Files + 890 .cfi_endproc + 891 .LFE1195: + 893 .section .text.clust2sect,"ax",%progbits + 894 .align 1 + 895 .syntax unified + 896 .thumb + 897 .thumb_func + 899 clust2sect: + 900 .LVL84: + 901 .LFB1199: + 873:Middlewares/Third_Party/FatFs/src/ff.c **** + 874:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _FS_LOCK != 0 */ + 875:Middlewares/Third_Party/FatFs/src/ff.c **** + 876:Middlewares/Third_Party/FatFs/src/ff.c **** + 877:Middlewares/Third_Party/FatFs/src/ff.c **** + 878:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ + 879:Middlewares/Third_Party/FatFs/src/ff.c **** /* Move/Flush disk access window in the file system object */ + 880:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ + 881:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 882:Middlewares/Third_Party/FatFs/src/ff.c **** static + 883:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT sync_window ( /* Returns FR_OK or FR_DISK_ERROR */ + 884:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS* fs /* File system object */ + 885:Middlewares/Third_Party/FatFs/src/ff.c **** ) + 886:Middlewares/Third_Party/FatFs/src/ff.c **** { + ARM GAS /tmp/cc2SVLkL.s page 33 + + + 887:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD wsect; + 888:Middlewares/Third_Party/FatFs/src/ff.c **** UINT nf; + 889:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res = FR_OK; + 890:Middlewares/Third_Party/FatFs/src/ff.c **** + 891:Middlewares/Third_Party/FatFs/src/ff.c **** + 892:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->wflag) { /* Write back the sector if it is dirty */ + 893:Middlewares/Third_Party/FatFs/src/ff.c **** wsect = fs->winsect; /* Current sector number */ + 894:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) { + 895:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DISK_ERR; + 896:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 897:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 0; + 898:Middlewares/Third_Party/FatFs/src/ff.c **** if (wsect - fs->fatbase < fs->fsize) { /* Is it in the FAT area? */ + 899:Middlewares/Third_Party/FatFs/src/ff.c **** for (nf = fs->n_fats; nf >= 2; nf--) { /* Reflect the change to all FAT copies */ + 900:Middlewares/Third_Party/FatFs/src/ff.c **** wsect += fs->fsize; + 901:Middlewares/Third_Party/FatFs/src/ff.c **** disk_write(fs->drv, fs->win, wsect, 1); + 902:Middlewares/Third_Party/FatFs/src/ff.c **** } + 903:Middlewares/Third_Party/FatFs/src/ff.c **** } + 904:Middlewares/Third_Party/FatFs/src/ff.c **** } + 905:Middlewares/Third_Party/FatFs/src/ff.c **** } + 906:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 907:Middlewares/Third_Party/FatFs/src/ff.c **** } + 908:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 909:Middlewares/Third_Party/FatFs/src/ff.c **** + 910:Middlewares/Third_Party/FatFs/src/ff.c **** + 911:Middlewares/Third_Party/FatFs/src/ff.c **** static + 912:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT move_window ( /* Returns FR_OK or FR_DISK_ERROR */ + 913:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS* fs, /* File system object */ + 914:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD sector /* Sector number to make appearance in the fs->win[] */ + 915:Middlewares/Third_Party/FatFs/src/ff.c **** ) + 916:Middlewares/Third_Party/FatFs/src/ff.c **** { + 917:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res = FR_OK; + 918:Middlewares/Third_Party/FatFs/src/ff.c **** + 919:Middlewares/Third_Party/FatFs/src/ff.c **** + 920:Middlewares/Third_Party/FatFs/src/ff.c **** if (sector != fs->winsect) { /* Window offset changed? */ + 921:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 922:Middlewares/Third_Party/FatFs/src/ff.c **** res = sync_window(fs); /* Write-back changes */ + 923:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 924:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Fill sector window with new data */ + 925:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) { + 926:Middlewares/Third_Party/FatFs/src/ff.c **** sector = 0xFFFFFFFF; /* Invalidate window if data is not reliable */ + 927:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DISK_ERR; + 928:Middlewares/Third_Party/FatFs/src/ff.c **** } + 929:Middlewares/Third_Party/FatFs/src/ff.c **** fs->winsect = sector; + 930:Middlewares/Third_Party/FatFs/src/ff.c **** } + 931:Middlewares/Third_Party/FatFs/src/ff.c **** } + 932:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 933:Middlewares/Third_Party/FatFs/src/ff.c **** } + 934:Middlewares/Third_Party/FatFs/src/ff.c **** + 935:Middlewares/Third_Party/FatFs/src/ff.c **** + 936:Middlewares/Third_Party/FatFs/src/ff.c **** + 937:Middlewares/Third_Party/FatFs/src/ff.c **** + 938:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 939:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ + 940:Middlewares/Third_Party/FatFs/src/ff.c **** /* Synchronize file system and strage device */ + 941:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ + 942:Middlewares/Third_Party/FatFs/src/ff.c **** + 943:Middlewares/Third_Party/FatFs/src/ff.c **** static + ARM GAS /tmp/cc2SVLkL.s page 34 + + + 944:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT sync_fs ( /* FR_OK:succeeded, !=0:error */ + 945:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS* fs /* File system object */ + 946:Middlewares/Third_Party/FatFs/src/ff.c **** ) + 947:Middlewares/Third_Party/FatFs/src/ff.c **** { + 948:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 949:Middlewares/Third_Party/FatFs/src/ff.c **** + 950:Middlewares/Third_Party/FatFs/src/ff.c **** + 951:Middlewares/Third_Party/FatFs/src/ff.c **** res = sync_window(fs); + 952:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 953:Middlewares/Third_Party/FatFs/src/ff.c **** /* Update FSInfo sector if needed */ + 954:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) { + 955:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create FSInfo structure */ + 956:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(fs->win, 0, SS(fs)); + 957:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(fs->win + BS_55AA, 0xAA55); + 958:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->win + FSI_LeadSig, 0x41615252); + 959:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->win + FSI_StrucSig, 0x61417272); + 960:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->win + FSI_Free_Count, fs->free_clst); + 961:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->win + FSI_Nxt_Free, fs->last_clst); + 962:Middlewares/Third_Party/FatFs/src/ff.c **** /* Write it into the FSInfo sector */ + 963:Middlewares/Third_Party/FatFs/src/ff.c **** fs->winsect = fs->volbase + 1; + 964:Middlewares/Third_Party/FatFs/src/ff.c **** disk_write(fs->drv, fs->win, fs->winsect, 1); + 965:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag = 0; + 966:Middlewares/Third_Party/FatFs/src/ff.c **** } + 967:Middlewares/Third_Party/FatFs/src/ff.c **** /* Make sure that no pending write process in the physical drive */ + 968:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK) res = FR_DISK_ERR; + 969:Middlewares/Third_Party/FatFs/src/ff.c **** } + 970:Middlewares/Third_Party/FatFs/src/ff.c **** + 971:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 972:Middlewares/Third_Party/FatFs/src/ff.c **** } + 973:Middlewares/Third_Party/FatFs/src/ff.c **** + 974:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 975:Middlewares/Third_Party/FatFs/src/ff.c **** + 976:Middlewares/Third_Party/FatFs/src/ff.c **** + 977:Middlewares/Third_Party/FatFs/src/ff.c **** + 978:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ + 979:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get sector# from cluster# */ + 980:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ + 981:Middlewares/Third_Party/FatFs/src/ff.c **** + 982:Middlewares/Third_Party/FatFs/src/ff.c **** static + 983:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clust2sect ( /* !=0:Sector number, 0:Failed (invalid cluster#) */ + 984:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS* fs, /* File system object */ + 985:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clst /* Cluster# to be converted */ + 986:Middlewares/Third_Party/FatFs/src/ff.c **** ) + 987:Middlewares/Third_Party/FatFs/src/ff.c **** { + 902 .loc 1 987 1 is_stmt 1 view -0 + 903 .cfi_startproc + 904 @ args = 0, pretend = 0, frame = 0 + 905 @ frame_needed = 0, uses_anonymous_args = 0 + 906 @ link register save eliminated. + 988:Middlewares/Third_Party/FatFs/src/ff.c **** clst -= 2; + 907 .loc 1 988 2 view .LVU253 + 908 .loc 1 988 7 is_stmt 0 view .LVU254 + 909 0000 0239 subs r1, r1, #2 + 910 .LVL85: + 989:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst >= fs->n_fatent - 2) return 0; /* Invalid cluster# */ + 911 .loc 1 989 2 is_stmt 1 view .LVU255 + 912 .loc 1 989 16 is_stmt 0 view .LVU256 + ARM GAS /tmp/cc2SVLkL.s page 35 + + + 913 0002 8369 ldr r3, [r0, #24] + 914 .loc 1 989 27 view .LVU257 + 915 0004 023B subs r3, r3, #2 + 916 .loc 1 989 5 view .LVU258 + 917 0006 8B42 cmp r3, r1 + 918 0008 04D9 bls .L85 + 990:Middlewares/Third_Party/FatFs/src/ff.c **** return clst * fs->csize + fs->database; + 919 .loc 1 990 2 is_stmt 1 view .LVU259 + 920 .loc 1 990 18 is_stmt 0 view .LVU260 + 921 000a 4389 ldrh r3, [r0, #10] + 922 .loc 1 990 30 view .LVU261 + 923 000c C06A ldr r0, [r0, #44] + 924 .LVL86: + 925 .loc 1 990 26 view .LVU262 + 926 000e 01FB0300 mla r0, r1, r3, r0 + 927 0012 7047 bx lr + 928 .LVL87: + 929 .L85: + 989:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst >= fs->n_fatent - 2) return 0; /* Invalid cluster# */ + 930 .loc 1 989 39 discriminator 1 view .LVU263 + 931 0014 0020 movs r0, #0 + 932 .LVL88: + 991:Middlewares/Third_Party/FatFs/src/ff.c **** } + 933 .loc 1 991 1 view .LVU264 + 934 0016 7047 bx lr + 935 .cfi_endproc + 936 .LFE1199: + 938 .section .text.clmt_clust,"ax",%progbits + 939 .align 1 + 940 .syntax unified + 941 .thumb + 942 .thumb_func + 944 clmt_clust: + 945 .LVL89: + 946 .LFB1204: + 992:Middlewares/Third_Party/FatFs/src/ff.c **** + 993:Middlewares/Third_Party/FatFs/src/ff.c **** + 994:Middlewares/Third_Party/FatFs/src/ff.c **** + 995:Middlewares/Third_Party/FatFs/src/ff.c **** + 996:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ + 997:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT access - Read value of a FAT entry */ + 998:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ + 999:Middlewares/Third_Party/FatFs/src/ff.c **** +1000:Middlewares/Third_Party/FatFs/src/ff.c **** static +1001:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x7FFFFFFF:Cluster status */ +1002:Middlewares/Third_Party/FatFs/src/ff.c **** _FDID* obj, /* Corresponding object */ +1003:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clst /* Cluster number to get the value */ +1004:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1005:Middlewares/Third_Party/FatFs/src/ff.c **** { +1006:Middlewares/Third_Party/FatFs/src/ff.c **** UINT wc, bc; +1007:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD val; +1008:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = obj->fs; +1009:Middlewares/Third_Party/FatFs/src/ff.c **** +1010:Middlewares/Third_Party/FatFs/src/ff.c **** +1011:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst < 2 || clst >= fs->n_fatent) { /* Check if in valid range */ +1012:Middlewares/Third_Party/FatFs/src/ff.c **** val = 1; /* Internal error */ +1013:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 36 + + +1014:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +1015:Middlewares/Third_Party/FatFs/src/ff.c **** val = 0xFFFFFFFF; /* Default value falls on disk error */ +1016:Middlewares/Third_Party/FatFs/src/ff.c **** +1017:Middlewares/Third_Party/FatFs/src/ff.c **** switch (fs->fs_type) { +1018:Middlewares/Third_Party/FatFs/src/ff.c **** case FS_FAT12 : +1019:Middlewares/Third_Party/FatFs/src/ff.c **** bc = (UINT)clst; bc += bc / 2; +1020:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; +1021:Middlewares/Third_Party/FatFs/src/ff.c **** wc = fs->win[bc++ % SS(fs)]; +1022:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; +1023:Middlewares/Third_Party/FatFs/src/ff.c **** wc |= fs->win[bc % SS(fs)] << 8; +1024:Middlewares/Third_Party/FatFs/src/ff.c **** val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF); +1025:Middlewares/Third_Party/FatFs/src/ff.c **** break; +1026:Middlewares/Third_Party/FatFs/src/ff.c **** +1027:Middlewares/Third_Party/FatFs/src/ff.c **** case FS_FAT16 : +1028:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break; +1029:Middlewares/Third_Party/FatFs/src/ff.c **** val = ld_word(fs->win + clst * 2 % SS(fs)); +1030:Middlewares/Third_Party/FatFs/src/ff.c **** break; +1031:Middlewares/Third_Party/FatFs/src/ff.c **** +1032:Middlewares/Third_Party/FatFs/src/ff.c **** case FS_FAT32 : +1033:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break; +1034:Middlewares/Third_Party/FatFs/src/ff.c **** val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF; +1035:Middlewares/Third_Party/FatFs/src/ff.c **** break; +1036:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +1037:Middlewares/Third_Party/FatFs/src/ff.c **** case FS_EXFAT : +1038:Middlewares/Third_Party/FatFs/src/ff.c **** if (obj->objsize) { +1039:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD cofs = clst - obj->sclust; /* Offset from start cluster */ +1040:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clen = (DWORD)((obj->objsize - 1) / SS(fs)) / fs->csize; /* Number of clusters - 1 */ +1041:Middlewares/Third_Party/FatFs/src/ff.c **** +1042:Middlewares/Third_Party/FatFs/src/ff.c **** if (obj->stat == 2) { /* Is there no valid chain on the FAT? */ +1043:Middlewares/Third_Party/FatFs/src/ff.c **** if (cofs <= clen) { +1044:Middlewares/Third_Party/FatFs/src/ff.c **** val = (cofs == clen) ? 0x7FFFFFFF : clst + 1; /* Generate the value */ +1045:Middlewares/Third_Party/FatFs/src/ff.c **** break; +1046:Middlewares/Third_Party/FatFs/src/ff.c **** } +1047:Middlewares/Third_Party/FatFs/src/ff.c **** } +1048:Middlewares/Third_Party/FatFs/src/ff.c **** if (obj->stat == 3 && cofs < obj->n_cont) { /* Is it in the 1st fragment? */ +1049:Middlewares/Third_Party/FatFs/src/ff.c **** val = clst + 1; /* Generate the value */ +1050:Middlewares/Third_Party/FatFs/src/ff.c **** break; +1051:Middlewares/Third_Party/FatFs/src/ff.c **** } +1052:Middlewares/Third_Party/FatFs/src/ff.c **** if (obj->stat != 2) { /* Get value from FAT if FAT chain is valid */ +1053:Middlewares/Third_Party/FatFs/src/ff.c **** if (obj->n_frag != 0) { /* Is it on the growing edge? */ +1054:Middlewares/Third_Party/FatFs/src/ff.c **** val = 0x7FFFFFFF; /* Generate EOC */ +1055:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +1056:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break; +1057:Middlewares/Third_Party/FatFs/src/ff.c **** val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x7FFFFFFF; +1058:Middlewares/Third_Party/FatFs/src/ff.c **** } +1059:Middlewares/Third_Party/FatFs/src/ff.c **** break; +1060:Middlewares/Third_Party/FatFs/src/ff.c **** } +1061:Middlewares/Third_Party/FatFs/src/ff.c **** } +1062:Middlewares/Third_Party/FatFs/src/ff.c **** /* go to default */ +1063:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +1064:Middlewares/Third_Party/FatFs/src/ff.c **** default: +1065:Middlewares/Third_Party/FatFs/src/ff.c **** val = 1; /* Internal error */ +1066:Middlewares/Third_Party/FatFs/src/ff.c **** } +1067:Middlewares/Third_Party/FatFs/src/ff.c **** } +1068:Middlewares/Third_Party/FatFs/src/ff.c **** +1069:Middlewares/Third_Party/FatFs/src/ff.c **** return val; +1070:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 37 + + +1071:Middlewares/Third_Party/FatFs/src/ff.c **** +1072:Middlewares/Third_Party/FatFs/src/ff.c **** +1073:Middlewares/Third_Party/FatFs/src/ff.c **** +1074:Middlewares/Third_Party/FatFs/src/ff.c **** +1075:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +1076:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1077:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT access - Change value of a FAT entry */ +1078:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1079:Middlewares/Third_Party/FatFs/src/ff.c **** +1080:Middlewares/Third_Party/FatFs/src/ff.c **** static +1081:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT put_fat ( /* FR_OK(0):succeeded, !=0:error */ +1082:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS* fs, /* Corresponding file system object */ +1083:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clst, /* FAT index number (cluster number) to be changed */ +1084:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD val /* New value to be set to the entry */ +1085:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1086:Middlewares/Third_Party/FatFs/src/ff.c **** { +1087:Middlewares/Third_Party/FatFs/src/ff.c **** UINT bc; +1088:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE *p; +1089:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res = FR_INT_ERR; +1090:Middlewares/Third_Party/FatFs/src/ff.c **** +1091:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst >= 2 && clst < fs->n_fatent) { /* Check if in valid range */ +1092:Middlewares/Third_Party/FatFs/src/ff.c **** switch (fs->fs_type) { +1093:Middlewares/Third_Party/FatFs/src/ff.c **** case FS_FAT12 : /* Bitfield items */ +1094:Middlewares/Third_Party/FatFs/src/ff.c **** bc = (UINT)clst; bc += bc / 2; +1095:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, fs->fatbase + (bc / SS(fs))); +1096:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +1097:Middlewares/Third_Party/FatFs/src/ff.c **** p = fs->win + bc++ % SS(fs); +1098:Middlewares/Third_Party/FatFs/src/ff.c **** *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; +1099:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +1100:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, fs->fatbase + (bc / SS(fs))); +1101:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +1102:Middlewares/Third_Party/FatFs/src/ff.c **** p = fs->win + bc % SS(fs); +1103:Middlewares/Third_Party/FatFs/src/ff.c **** *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); +1104:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +1105:Middlewares/Third_Party/FatFs/src/ff.c **** break; +1106:Middlewares/Third_Party/FatFs/src/ff.c **** +1107:Middlewares/Third_Party/FatFs/src/ff.c **** case FS_FAT16 : /* WORD aligned items */ +1108:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))); +1109:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +1110:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(fs->win + clst * 2 % SS(fs), (WORD)val); +1111:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +1112:Middlewares/Third_Party/FatFs/src/ff.c **** break; +1113:Middlewares/Third_Party/FatFs/src/ff.c **** +1114:Middlewares/Third_Party/FatFs/src/ff.c **** case FS_FAT32 : /* DWORD aligned items */ +1115:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +1116:Middlewares/Third_Party/FatFs/src/ff.c **** case FS_EXFAT : +1117:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +1118:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))); +1119:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +1120:Middlewares/Third_Party/FatFs/src/ff.c **** if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { +1121:Middlewares/Third_Party/FatFs/src/ff.c **** val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000); +1122:Middlewares/Third_Party/FatFs/src/ff.c **** } +1123:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->win + clst * 4 % SS(fs), val); +1124:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +1125:Middlewares/Third_Party/FatFs/src/ff.c **** break; +1126:Middlewares/Third_Party/FatFs/src/ff.c **** } +1127:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 38 + + +1128:Middlewares/Third_Party/FatFs/src/ff.c **** return res; +1129:Middlewares/Third_Party/FatFs/src/ff.c **** } +1130:Middlewares/Third_Party/FatFs/src/ff.c **** +1131:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* !_FS_READONLY */ +1132:Middlewares/Third_Party/FatFs/src/ff.c **** +1133:Middlewares/Third_Party/FatFs/src/ff.c **** +1134:Middlewares/Third_Party/FatFs/src/ff.c **** +1135:Middlewares/Third_Party/FatFs/src/ff.c **** +1136:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT && !_FS_READONLY +1137:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1138:Middlewares/Third_Party/FatFs/src/ff.c **** /* exFAT: Accessing FAT and Allocation Bitmap */ +1139:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1140:Middlewares/Third_Party/FatFs/src/ff.c **** +1141:Middlewares/Third_Party/FatFs/src/ff.c **** /*--------------------------------------*/ +1142:Middlewares/Third_Party/FatFs/src/ff.c **** /* Find a contiguous free cluster block */ +1143:Middlewares/Third_Party/FatFs/src/ff.c **** /*--------------------------------------*/ +1144:Middlewares/Third_Party/FatFs/src/ff.c **** +1145:Middlewares/Third_Party/FatFs/src/ff.c **** static +1146:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD find_bitmap ( /* 0:Not found, 2..:Cluster block found, 0xFFFFFFFF:Disk error */ +1147:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS* fs, /* File system object */ +1148:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clst, /* Cluster number to scan from */ +1149:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD ncl /* Number of contiguous clusters to find (1..) */ +1150:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1151:Middlewares/Third_Party/FatFs/src/ff.c **** { +1152:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE bm, bv; +1153:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i; +1154:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD val, scl, ctr; +1155:Middlewares/Third_Party/FatFs/src/ff.c **** +1156:Middlewares/Third_Party/FatFs/src/ff.c **** +1157:Middlewares/Third_Party/FatFs/src/ff.c **** clst -= 2; /* The first bit in the bitmap corresponds to cluster #2 */ +1158:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst >= fs->n_fatent - 2) clst = 0; +1159:Middlewares/Third_Party/FatFs/src/ff.c **** scl = val = clst; ctr = 0; +1160:Middlewares/Third_Party/FatFs/src/ff.c **** for (;;) { +1161:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, fs->database + val / 8 / SS(fs)) != FR_OK) return 0xFFFFFFFF; /* (assuming bi +1162:Middlewares/Third_Party/FatFs/src/ff.c **** i = val / 8 % SS(fs); bm = 1 << (val % 8); +1163:Middlewares/Third_Party/FatFs/src/ff.c **** do { +1164:Middlewares/Third_Party/FatFs/src/ff.c **** do { +1165:Middlewares/Third_Party/FatFs/src/ff.c **** bv = fs->win[i] & bm; bm <<= 1; /* Get bit value */ +1166:Middlewares/Third_Party/FatFs/src/ff.c **** if (++val >= fs->n_fatent - 2) { /* Next cluster (with wrap-around) */ +1167:Middlewares/Third_Party/FatFs/src/ff.c **** val = 0; bm = 0; i = SS(fs); +1168:Middlewares/Third_Party/FatFs/src/ff.c **** } +1169:Middlewares/Third_Party/FatFs/src/ff.c **** if (!bv) { /* Is it a free cluster? */ +1170:Middlewares/Third_Party/FatFs/src/ff.c **** if (++ctr == ncl) return scl + 2; /* Check if run length is sufficient for required */ +1171:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +1172:Middlewares/Third_Party/FatFs/src/ff.c **** scl = val; ctr = 0; /* Encountered a cluster in-use, restart to scan */ +1173:Middlewares/Third_Party/FatFs/src/ff.c **** } +1174:Middlewares/Third_Party/FatFs/src/ff.c **** if (val == clst) return 0; /* All cluster scanned? */ +1175:Middlewares/Third_Party/FatFs/src/ff.c **** } while (bm); +1176:Middlewares/Third_Party/FatFs/src/ff.c **** bm = 1; +1177:Middlewares/Third_Party/FatFs/src/ff.c **** } while (++i < SS(fs)); +1178:Middlewares/Third_Party/FatFs/src/ff.c **** } +1179:Middlewares/Third_Party/FatFs/src/ff.c **** } +1180:Middlewares/Third_Party/FatFs/src/ff.c **** +1181:Middlewares/Third_Party/FatFs/src/ff.c **** +1182:Middlewares/Third_Party/FatFs/src/ff.c **** /*----------------------------------------*/ +1183:Middlewares/Third_Party/FatFs/src/ff.c **** /* Set/Clear a block of allocation bitmap */ +1184:Middlewares/Third_Party/FatFs/src/ff.c **** /*----------------------------------------*/ + ARM GAS /tmp/cc2SVLkL.s page 39 + + +1185:Middlewares/Third_Party/FatFs/src/ff.c **** +1186:Middlewares/Third_Party/FatFs/src/ff.c **** static +1187:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT change_bitmap ( +1188:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS* fs, /* File system object */ +1189:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clst, /* Cluster number to change from */ +1190:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD ncl, /* Number of clusters to be changed */ +1191:Middlewares/Third_Party/FatFs/src/ff.c **** int bv /* bit value to be set (0 or 1) */ +1192:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1193:Middlewares/Third_Party/FatFs/src/ff.c **** { +1194:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE bm; +1195:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i; +1196:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD sect; +1197:Middlewares/Third_Party/FatFs/src/ff.c **** +1198:Middlewares/Third_Party/FatFs/src/ff.c **** clst -= 2; /* The first bit corresponds to cluster #2 */ +1199:Middlewares/Third_Party/FatFs/src/ff.c **** sect = fs->database + clst / 8 / SS(fs); /* Sector address (assuming bitmap is located top of the +1200:Middlewares/Third_Party/FatFs/src/ff.c **** i = clst / 8 % SS(fs); /* Byte offset in the sector */ +1201:Middlewares/Third_Party/FatFs/src/ff.c **** bm = 1 << (clst % 8); /* Bit mask in the byte */ +1202:Middlewares/Third_Party/FatFs/src/ff.c **** for (;;) { +1203:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, sect++) != FR_OK) return FR_DISK_ERR; +1204:Middlewares/Third_Party/FatFs/src/ff.c **** do { +1205:Middlewares/Third_Party/FatFs/src/ff.c **** do { +1206:Middlewares/Third_Party/FatFs/src/ff.c **** if (bv == (int)((fs->win[i] & bm) != 0)) return FR_INT_ERR; /* Is the bit expected value? */ +1207:Middlewares/Third_Party/FatFs/src/ff.c **** fs->win[i] ^= bm; /* Flip the bit */ +1208:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +1209:Middlewares/Third_Party/FatFs/src/ff.c **** if (--ncl == 0) return FR_OK; /* All bits processed? */ +1210:Middlewares/Third_Party/FatFs/src/ff.c **** } while (bm <<= 1); /* Next bit */ +1211:Middlewares/Third_Party/FatFs/src/ff.c **** bm = 1; +1212:Middlewares/Third_Party/FatFs/src/ff.c **** } while (++i < SS(fs)); /* Next byte */ +1213:Middlewares/Third_Party/FatFs/src/ff.c **** i = 0; +1214:Middlewares/Third_Party/FatFs/src/ff.c **** } +1215:Middlewares/Third_Party/FatFs/src/ff.c **** } +1216:Middlewares/Third_Party/FatFs/src/ff.c **** +1217:Middlewares/Third_Party/FatFs/src/ff.c **** +1218:Middlewares/Third_Party/FatFs/src/ff.c **** /*---------------------------------------------*/ +1219:Middlewares/Third_Party/FatFs/src/ff.c **** /* Fill the first fragment of the FAT chain */ +1220:Middlewares/Third_Party/FatFs/src/ff.c **** /*---------------------------------------------*/ +1221:Middlewares/Third_Party/FatFs/src/ff.c **** +1222:Middlewares/Third_Party/FatFs/src/ff.c **** static +1223:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT fill_first_frag ( +1224:Middlewares/Third_Party/FatFs/src/ff.c **** _FDID* obj /* Pointer to the corresponding object */ +1225:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1226:Middlewares/Third_Party/FatFs/src/ff.c **** { +1227:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +1228:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD cl, n; +1229:Middlewares/Third_Party/FatFs/src/ff.c **** +1230:Middlewares/Third_Party/FatFs/src/ff.c **** if (obj->stat == 3) { /* Has the object been changed 'fragmented'? */ +1231:Middlewares/Third_Party/FatFs/src/ff.c **** for (cl = obj->sclust, n = obj->n_cont; n; cl++, n--) { /* Create cluster chain on the FAT */ +1232:Middlewares/Third_Party/FatFs/src/ff.c **** res = put_fat(obj->fs, cl, cl + 1); +1233:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; +1234:Middlewares/Third_Party/FatFs/src/ff.c **** } +1235:Middlewares/Third_Party/FatFs/src/ff.c **** obj->stat = 0; /* Change status 'FAT chain is valid' */ +1236:Middlewares/Third_Party/FatFs/src/ff.c **** } +1237:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_OK; +1238:Middlewares/Third_Party/FatFs/src/ff.c **** } +1239:Middlewares/Third_Party/FatFs/src/ff.c **** +1240:Middlewares/Third_Party/FatFs/src/ff.c **** +1241:Middlewares/Third_Party/FatFs/src/ff.c **** /*---------------------------------------------*/ + ARM GAS /tmp/cc2SVLkL.s page 40 + + +1242:Middlewares/Third_Party/FatFs/src/ff.c **** /* Fill the last fragment of the FAT chain */ +1243:Middlewares/Third_Party/FatFs/src/ff.c **** /*---------------------------------------------*/ +1244:Middlewares/Third_Party/FatFs/src/ff.c **** +1245:Middlewares/Third_Party/FatFs/src/ff.c **** static +1246:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT fill_last_frag ( +1247:Middlewares/Third_Party/FatFs/src/ff.c **** _FDID* obj, /* Pointer to the corresponding object */ +1248:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD lcl, /* Last cluster of the fragment */ +1249:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD term /* Value to set the last FAT entry */ +1250:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1251:Middlewares/Third_Party/FatFs/src/ff.c **** { +1252:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +1253:Middlewares/Third_Party/FatFs/src/ff.c **** +1254:Middlewares/Third_Party/FatFs/src/ff.c **** while (obj->n_frag > 0) { /* Create the last chain on the FAT */ +1255:Middlewares/Third_Party/FatFs/src/ff.c **** res = put_fat(obj->fs, lcl - obj->n_frag + 1, (obj->n_frag > 1) ? lcl - obj->n_frag + 2 : term); +1256:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; +1257:Middlewares/Third_Party/FatFs/src/ff.c **** obj->n_frag--; +1258:Middlewares/Third_Party/FatFs/src/ff.c **** } +1259:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_OK; +1260:Middlewares/Third_Party/FatFs/src/ff.c **** } +1261:Middlewares/Third_Party/FatFs/src/ff.c **** +1262:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _FS_EXFAT && !_FS_READONLY */ +1263:Middlewares/Third_Party/FatFs/src/ff.c **** +1264:Middlewares/Third_Party/FatFs/src/ff.c **** +1265:Middlewares/Third_Party/FatFs/src/ff.c **** +1266:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +1267:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1268:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT handling - Remove a cluster chain */ +1269:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1270:Middlewares/Third_Party/FatFs/src/ff.c **** static +1271:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT remove_chain ( /* FR_OK(0):succeeded, !=0:error */ +1272:Middlewares/Third_Party/FatFs/src/ff.c **** _FDID* obj, /* Corresponding object */ +1273:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clst, /* Cluster to remove a chain from */ +1274:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD pclst /* Previous cluster of clst (0:an entire chain) */ +1275:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1276:Middlewares/Third_Party/FatFs/src/ff.c **** { +1277:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res = FR_OK; +1278:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD nxt; +1279:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = obj->fs; +1280:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT || _USE_TRIM +1281:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD scl = clst, ecl = clst; +1282:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +1283:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_TRIM +1284:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD rt[2]; +1285:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +1286:Middlewares/Third_Party/FatFs/src/ff.c **** +1287:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Check if in valid range */ +1288:Middlewares/Third_Party/FatFs/src/ff.c **** +1289:Middlewares/Third_Party/FatFs/src/ff.c **** /* Mark the previous cluster 'EOC' on the FAT if it exists */ +1290:Middlewares/Third_Party/FatFs/src/ff.c **** if (pclst && (!_FS_EXFAT || fs->fs_type != FS_EXFAT || obj->stat != 2)) { +1291:Middlewares/Third_Party/FatFs/src/ff.c **** res = put_fat(fs, pclst, 0xFFFFFFFF); +1292:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; +1293:Middlewares/Third_Party/FatFs/src/ff.c **** } +1294:Middlewares/Third_Party/FatFs/src/ff.c **** +1295:Middlewares/Third_Party/FatFs/src/ff.c **** /* Remove the chain */ +1296:Middlewares/Third_Party/FatFs/src/ff.c **** do { +1297:Middlewares/Third_Party/FatFs/src/ff.c **** nxt = get_fat(obj, clst); /* Get cluster status */ +1298:Middlewares/Third_Party/FatFs/src/ff.c **** if (nxt == 0) break; /* Empty cluster? */ + ARM GAS /tmp/cc2SVLkL.s page 41 + + +1299:Middlewares/Third_Party/FatFs/src/ff.c **** if (nxt == 1) return FR_INT_ERR; /* Internal error? */ +1300:Middlewares/Third_Party/FatFs/src/ff.c **** if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error? */ +1301:Middlewares/Third_Party/FatFs/src/ff.c **** if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { +1302:Middlewares/Third_Party/FatFs/src/ff.c **** res = put_fat(fs, clst, 0); /* Mark the cluster 'free' on the FAT */ +1303:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; +1304:Middlewares/Third_Party/FatFs/src/ff.c **** } +1305:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->free_clst < fs->n_fatent - 2) { /* Update FSINFO */ +1306:Middlewares/Third_Party/FatFs/src/ff.c **** fs->free_clst++; +1307:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag |= 1; +1308:Middlewares/Third_Party/FatFs/src/ff.c **** } +1309:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT || _USE_TRIM +1310:Middlewares/Third_Party/FatFs/src/ff.c **** if (ecl + 1 == nxt) { /* Is next cluster contiguous? */ +1311:Middlewares/Third_Party/FatFs/src/ff.c **** ecl = nxt; +1312:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* End of contiguous cluster block */ +1313:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +1314:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { +1315:Middlewares/Third_Party/FatFs/src/ff.c **** res = change_bitmap(fs, scl, ecl - scl + 1, 0); /* Mark the cluster block 'free' on the bitmap +1316:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; +1317:Middlewares/Third_Party/FatFs/src/ff.c **** } +1318:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +1319:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_TRIM +1320:Middlewares/Third_Party/FatFs/src/ff.c **** rt[0] = clust2sect(fs, scl); /* Start sector */ +1321:Middlewares/Third_Party/FatFs/src/ff.c **** rt[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */ +1322:Middlewares/Third_Party/FatFs/src/ff.c **** disk_ioctl(fs->drv, CTRL_TRIM, rt); /* Inform device the block can be erased */ +1323:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +1324:Middlewares/Third_Party/FatFs/src/ff.c **** scl = ecl = nxt; +1325:Middlewares/Third_Party/FatFs/src/ff.c **** } +1326:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +1327:Middlewares/Third_Party/FatFs/src/ff.c **** clst = nxt; /* Next cluster */ +1328:Middlewares/Third_Party/FatFs/src/ff.c **** } while (clst < fs->n_fatent); /* Repeat while not the last link */ +1329:Middlewares/Third_Party/FatFs/src/ff.c **** +1330:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +1331:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { +1332:Middlewares/Third_Party/FatFs/src/ff.c **** if (pclst == 0) { /* Does the object have no chain? */ +1333:Middlewares/Third_Party/FatFs/src/ff.c **** obj->stat = 0; /* Change the object status 'initial' */ +1334:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +1335:Middlewares/Third_Party/FatFs/src/ff.c **** if (obj->stat == 3 && pclst >= obj->sclust && pclst <= obj->sclust + obj->n_cont) { /* Did the c +1336:Middlewares/Third_Party/FatFs/src/ff.c **** obj->stat = 2; /* Change the object status 'contiguous' */ +1337:Middlewares/Third_Party/FatFs/src/ff.c **** } +1338:Middlewares/Third_Party/FatFs/src/ff.c **** } +1339:Middlewares/Third_Party/FatFs/src/ff.c **** } +1340:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +1341:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_OK; +1342:Middlewares/Third_Party/FatFs/src/ff.c **** } +1343:Middlewares/Third_Party/FatFs/src/ff.c **** +1344:Middlewares/Third_Party/FatFs/src/ff.c **** +1345:Middlewares/Third_Party/FatFs/src/ff.c **** +1346:Middlewares/Third_Party/FatFs/src/ff.c **** +1347:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1348:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT handling - Stretch a chain or Create a new chain */ +1349:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1350:Middlewares/Third_Party/FatFs/src/ff.c **** static +1351:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster +1352:Middlewares/Third_Party/FatFs/src/ff.c **** _FDID* obj, /* Corresponding object */ +1353:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clst /* Cluster# to stretch, 0:Create a new chain */ +1354:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1355:Middlewares/Third_Party/FatFs/src/ff.c **** { + ARM GAS /tmp/cc2SVLkL.s page 42 + + +1356:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD cs, ncl, scl; +1357:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +1358:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = obj->fs; +1359:Middlewares/Third_Party/FatFs/src/ff.c **** +1360:Middlewares/Third_Party/FatFs/src/ff.c **** +1361:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0) { /* Create a new chain */ +1362:Middlewares/Third_Party/FatFs/src/ff.c **** scl = fs->last_clst; /* Get suggested cluster to start from */ +1363:Middlewares/Third_Party/FatFs/src/ff.c **** if (scl == 0 || scl >= fs->n_fatent) scl = 1; +1364:Middlewares/Third_Party/FatFs/src/ff.c **** } +1365:Middlewares/Third_Party/FatFs/src/ff.c **** else { /* Stretch current chain */ +1366:Middlewares/Third_Party/FatFs/src/ff.c **** cs = get_fat(obj, clst); /* Check the cluster status */ +1367:Middlewares/Third_Party/FatFs/src/ff.c **** if (cs < 2) return 1; /* Invalid FAT value */ +1368:Middlewares/Third_Party/FatFs/src/ff.c **** if (cs == 0xFFFFFFFF) return cs; /* A disk error occurred */ +1369:Middlewares/Third_Party/FatFs/src/ff.c **** if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ +1370:Middlewares/Third_Party/FatFs/src/ff.c **** scl = clst; +1371:Middlewares/Third_Party/FatFs/src/ff.c **** } +1372:Middlewares/Third_Party/FatFs/src/ff.c **** +1373:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +1374:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ +1375:Middlewares/Third_Party/FatFs/src/ff.c **** ncl = find_bitmap(fs, scl, 1); /* Find a free cluster */ +1376:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl == 0 || ncl == 0xFFFFFFFF) return ncl; /* No free cluster or hard error? */ +1377:Middlewares/Third_Party/FatFs/src/ff.c **** res = change_bitmap(fs, ncl, 1, 1); /* Mark the cluster 'in use' */ +1378:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_INT_ERR) return 1; +1379:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_DISK_ERR) return 0xFFFFFFFF; +1380:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0) { /* Is it a new chain? */ +1381:Middlewares/Third_Party/FatFs/src/ff.c **** obj->stat = 2; /* Set status 'contiguous' */ +1382:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* It is a stretched chain */ +1383:Middlewares/Third_Party/FatFs/src/ff.c **** if (obj->stat == 2 && ncl != scl + 1) { /* Is the chain got fragmented? */ +1384:Middlewares/Third_Party/FatFs/src/ff.c **** obj->n_cont = scl - obj->sclust; /* Set size of the contiguous part */ +1385:Middlewares/Third_Party/FatFs/src/ff.c **** obj->stat = 3; /* Change status 'just fragmented' */ +1386:Middlewares/Third_Party/FatFs/src/ff.c **** } +1387:Middlewares/Third_Party/FatFs/src/ff.c **** } +1388:Middlewares/Third_Party/FatFs/src/ff.c **** if (obj->stat != 2) { /* Is the file non-contiguous? */ +1389:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl == clst + 1) { /* Is the cluster next to previous one? */ +1390:Middlewares/Third_Party/FatFs/src/ff.c **** obj->n_frag = obj->n_frag ? obj->n_frag + 1 : 2; /* Increment size of last framgent */ +1391:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* New fragment */ +1392:Middlewares/Third_Party/FatFs/src/ff.c **** if (obj->n_frag == 0) obj->n_frag = 1; +1393:Middlewares/Third_Party/FatFs/src/ff.c **** res = fill_last_frag(obj, clst, ncl); /* Fill last fragment on the FAT and link it to new one * +1394:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) obj->n_frag = 1; +1395:Middlewares/Third_Party/FatFs/src/ff.c **** } +1396:Middlewares/Third_Party/FatFs/src/ff.c **** } +1397:Middlewares/Third_Party/FatFs/src/ff.c **** } else +1398:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +1399:Middlewares/Third_Party/FatFs/src/ff.c **** { /* On the FAT12/16/32 volume */ +1400:Middlewares/Third_Party/FatFs/src/ff.c **** ncl = scl; /* Start cluster */ +1401:Middlewares/Third_Party/FatFs/src/ff.c **** for (;;) { +1402:Middlewares/Third_Party/FatFs/src/ff.c **** ncl++; /* Next cluster */ +1403:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl >= fs->n_fatent) { /* Check wrap-around */ +1404:Middlewares/Third_Party/FatFs/src/ff.c **** ncl = 2; +1405:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl > scl) return 0; /* No free cluster */ +1406:Middlewares/Third_Party/FatFs/src/ff.c **** } +1407:Middlewares/Third_Party/FatFs/src/ff.c **** cs = get_fat(obj, ncl); /* Get the cluster status */ +1408:Middlewares/Third_Party/FatFs/src/ff.c **** if (cs == 0) break; /* Found a free cluster */ +1409:Middlewares/Third_Party/FatFs/src/ff.c **** if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* An error occurred */ +1410:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl == scl) return 0; /* No free cluster */ +1411:Middlewares/Third_Party/FatFs/src/ff.c **** } +1412:Middlewares/Third_Party/FatFs/src/ff.c **** res = put_fat(fs, ncl, 0xFFFFFFFF); /* Mark the new cluster 'EOC' */ + ARM GAS /tmp/cc2SVLkL.s page 43 + + +1413:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && clst != 0) { +1414:Middlewares/Third_Party/FatFs/src/ff.c **** res = put_fat(fs, clst, ncl); /* Link it from the previous one if needed */ +1415:Middlewares/Third_Party/FatFs/src/ff.c **** } +1416:Middlewares/Third_Party/FatFs/src/ff.c **** } +1417:Middlewares/Third_Party/FatFs/src/ff.c **** +1418:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Update FSINFO if function succeeded. */ +1419:Middlewares/Third_Party/FatFs/src/ff.c **** fs->last_clst = ncl; +1420:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->free_clst <= fs->n_fatent - 2) fs->free_clst--; +1421:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag |= 1; +1422:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +1423:Middlewares/Third_Party/FatFs/src/ff.c **** ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; /* Failed. Generate error status */ +1424:Middlewares/Third_Party/FatFs/src/ff.c **** } +1425:Middlewares/Third_Party/FatFs/src/ff.c **** +1426:Middlewares/Third_Party/FatFs/src/ff.c **** return ncl; /* Return new cluster number or error status */ +1427:Middlewares/Third_Party/FatFs/src/ff.c **** } +1428:Middlewares/Third_Party/FatFs/src/ff.c **** +1429:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* !_FS_READONLY */ +1430:Middlewares/Third_Party/FatFs/src/ff.c **** +1431:Middlewares/Third_Party/FatFs/src/ff.c **** +1432:Middlewares/Third_Party/FatFs/src/ff.c **** +1433:Middlewares/Third_Party/FatFs/src/ff.c **** +1434:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FASTSEEK +1435:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1436:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT handling - Convert offset into cluster with link map table */ +1437:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1438:Middlewares/Third_Party/FatFs/src/ff.c **** +1439:Middlewares/Third_Party/FatFs/src/ff.c **** static +1440:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */ +1441:Middlewares/Third_Party/FatFs/src/ff.c **** FIL* fp, /* Pointer to the file object */ +1442:Middlewares/Third_Party/FatFs/src/ff.c **** FSIZE_t ofs /* File offset to be converted to cluster# */ +1443:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1444:Middlewares/Third_Party/FatFs/src/ff.c **** { + 947 .loc 1 1444 1 is_stmt 1 view -0 + 948 .cfi_startproc + 949 @ args = 0, pretend = 0, frame = 0 + 950 @ frame_needed = 0, uses_anonymous_args = 0 + 951 @ link register save eliminated. +1445:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD cl, ncl, *tbl; + 952 .loc 1 1445 2 view .LVU266 +1446:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = fp->obj.fs; + 953 .loc 1 1446 2 view .LVU267 + 954 .loc 1 1446 9 is_stmt 0 view .LVU268 + 955 0000 0268 ldr r2, [r0] + 956 .LVL90: +1447:Middlewares/Third_Party/FatFs/src/ff.c **** +1448:Middlewares/Third_Party/FatFs/src/ff.c **** +1449:Middlewares/Third_Party/FatFs/src/ff.c **** tbl = fp->cltbl + 1; /* Top of CLMT */ + 957 .loc 1 1449 2 is_stmt 1 view .LVU269 + 958 .loc 1 1449 10 is_stmt 0 view .LVU270 + 959 0002 C36A ldr r3, [r0, #44] + 960 .loc 1 1449 6 view .LVU271 + 961 0004 0433 adds r3, r3, #4 + 962 .LVL91: +1450:Middlewares/Third_Party/FatFs/src/ff.c **** cl = (DWORD)(ofs / SS(fs) / fs->csize); /* Cluster order from top of the file */ + 963 .loc 1 1450 2 is_stmt 1 view .LVU272 + 964 .loc 1 1450 21 is_stmt 0 view .LVU273 + 965 0006 9089 ldrh r0, [r2, #12] + ARM GAS /tmp/cc2SVLkL.s page 44 + + + 966 .LVL92: + 967 .loc 1 1450 19 view .LVU274 + 968 0008 B1FBF0F1 udiv r1, r1, r0 + 969 .LVL93: + 970 .loc 1 1450 32 view .LVU275 + 971 000c 5289 ldrh r2, [r2, #10] + 972 .LVL94: + 973 .loc 1 1450 5 view .LVU276 + 974 000e B1FBF2F1 udiv r1, r1, r2 + 975 .LVL95: + 976 .loc 1 1450 5 view .LVU277 + 977 0012 01E0 b .L89 + 978 .LVL96: + 979 .L90: +1451:Middlewares/Third_Party/FatFs/src/ff.c **** for (;;) { +1452:Middlewares/Third_Party/FatFs/src/ff.c **** ncl = *tbl++; /* Number of cluters in the fragment */ +1453:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl == 0) return 0; /* End of table? (error) */ +1454:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl < ncl) break; /* In this fragment? */ +1455:Middlewares/Third_Party/FatFs/src/ff.c **** cl -= ncl; tbl++; /* Next fragment */ + 980 .loc 1 1455 3 is_stmt 1 view .LVU278 + 981 .loc 1 1455 6 is_stmt 0 view .LVU279 + 982 0014 091A subs r1, r1, r0 + 983 .LVL97: + 984 .loc 1 1455 14 is_stmt 1 view .LVU280 + 985 .loc 1 1455 17 is_stmt 0 view .LVU281 + 986 0016 0833 adds r3, r3, #8 + 987 .LVL98: +1451:Middlewares/Third_Party/FatFs/src/ff.c **** for (;;) { + 988 .loc 1 1451 2 is_stmt 1 view .LVU282 + 989 .L89: +1451:Middlewares/Third_Party/FatFs/src/ff.c **** for (;;) { + 990 .loc 1 1451 2 view .LVU283 +1452:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl == 0) return 0; /* End of table? (error) */ + 991 .loc 1 1452 3 view .LVU284 +1452:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl == 0) return 0; /* End of table? (error) */ + 992 .loc 1 1452 7 is_stmt 0 view .LVU285 + 993 0018 1868 ldr r0, [r3] + 994 .LVL99: +1453:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl < ncl) break; /* In this fragment? */ + 995 .loc 1 1453 3 is_stmt 1 view .LVU286 +1453:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl < ncl) break; /* In this fragment? */ + 996 .loc 1 1453 6 is_stmt 0 view .LVU287 + 997 001a 18B1 cbz r0, .L86 +1454:Middlewares/Third_Party/FatFs/src/ff.c **** cl -= ncl; tbl++; /* Next fragment */ + 998 .loc 1 1454 3 is_stmt 1 view .LVU288 +1454:Middlewares/Third_Party/FatFs/src/ff.c **** cl -= ncl; tbl++; /* Next fragment */ + 999 .loc 1 1454 6 is_stmt 0 view .LVU289 + 1000 001c 8142 cmp r1, r0 + 1001 001e F9D2 bcs .L90 +1456:Middlewares/Third_Party/FatFs/src/ff.c **** } +1457:Middlewares/Third_Party/FatFs/src/ff.c **** return cl + *tbl; /* Return the cluster number */ + 1002 .loc 1 1457 2 is_stmt 1 view .LVU290 + 1003 .loc 1 1457 14 is_stmt 0 view .LVU291 + 1004 0020 5868 ldr r0, [r3, #4] + 1005 .LVL100: + 1006 .loc 1 1457 12 view .LVU292 + 1007 0022 0844 add r0, r0, r1 + ARM GAS /tmp/cc2SVLkL.s page 45 + + + 1008 .L86: +1458:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1009 .loc 1 1458 1 view .LVU293 + 1010 0024 7047 bx lr + 1011 .cfi_endproc + 1012 .LFE1204: + 1014 .section .text.ld_clust,"ax",%progbits + 1015 .align 1 + 1016 .syntax unified + 1017 .thumb + 1018 .thumb_func + 1020 ld_clust: + 1021 .LVL101: + 1022 .LFB1208: +1459:Middlewares/Third_Party/FatFs/src/ff.c **** +1460:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _USE_FASTSEEK */ +1461:Middlewares/Third_Party/FatFs/src/ff.c **** +1462:Middlewares/Third_Party/FatFs/src/ff.c **** +1463:Middlewares/Third_Party/FatFs/src/ff.c **** +1464:Middlewares/Third_Party/FatFs/src/ff.c **** +1465:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1466:Middlewares/Third_Party/FatFs/src/ff.c **** /* Directory handling - Set directory index */ +1467:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1468:Middlewares/Third_Party/FatFs/src/ff.c **** +1469:Middlewares/Third_Party/FatFs/src/ff.c **** static +1470:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT dir_sdi ( /* FR_OK(0):succeeded, !=0:error */ +1471:Middlewares/Third_Party/FatFs/src/ff.c **** DIR* dp, /* Pointer to directory object */ +1472:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD ofs /* Offset of directory table */ +1473:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1474:Middlewares/Third_Party/FatFs/src/ff.c **** { +1475:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD csz, clst; +1476:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = dp->obj.fs; +1477:Middlewares/Third_Party/FatFs/src/ff.c **** +1478:Middlewares/Third_Party/FatFs/src/ff.c **** +1479:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR) || ofs % SZDIRE) +1480:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_INT_ERR; +1481:Middlewares/Third_Party/FatFs/src/ff.c **** } +1482:Middlewares/Third_Party/FatFs/src/ff.c **** dp->dptr = ofs; /* Set current offset */ +1483:Middlewares/Third_Party/FatFs/src/ff.c **** clst = dp->obj.sclust; /* Table start cluster (0:root) */ +1484:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0 && fs->fs_type >= FS_FAT32) { /* Replace cluster# 0 with root cluster# */ +1485:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fs->dirbase; +1486:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_EXFAT) dp->obj.stat = 0; /* exFAT: Root dir has an FAT chain */ +1487:Middlewares/Third_Party/FatFs/src/ff.c **** } +1488:Middlewares/Third_Party/FatFs/src/ff.c **** +1489:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0) { /* Static table (root-directory in FAT12/16) */ +1490:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs / SZDIRE >= fs->n_rootdir) return FR_INT_ERR; /* Is index out of range? */ +1491:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect = fs->dirbase; +1492:Middlewares/Third_Party/FatFs/src/ff.c **** +1493:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* Dynamic table (sub-directory or root-directory in FAT32+) */ +1494:Middlewares/Third_Party/FatFs/src/ff.c **** csz = (DWORD)fs->csize * SS(fs); /* Bytes per cluster */ +1495:Middlewares/Third_Party/FatFs/src/ff.c **** while (ofs >= csz) { /* Follow cluster chain */ +1496:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&dp->obj, clst); /* Get next cluster */ +1497:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ +1498:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Reached to end of table or internal +1499:Middlewares/Third_Party/FatFs/src/ff.c **** ofs -= csz; +1500:Middlewares/Third_Party/FatFs/src/ff.c **** } +1501:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect = clust2sect(fs, clst); + ARM GAS /tmp/cc2SVLkL.s page 46 + + +1502:Middlewares/Third_Party/FatFs/src/ff.c **** } +1503:Middlewares/Third_Party/FatFs/src/ff.c **** dp->clust = clst; /* Current cluster# */ +1504:Middlewares/Third_Party/FatFs/src/ff.c **** if (!dp->sect) return FR_INT_ERR; +1505:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect += ofs / SS(fs); /* Sector# of the directory entry */ +1506:Middlewares/Third_Party/FatFs/src/ff.c **** dp->dir = fs->win + (ofs % SS(fs)); /* Pointer to the entry in the win[] */ +1507:Middlewares/Third_Party/FatFs/src/ff.c **** +1508:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_OK; +1509:Middlewares/Third_Party/FatFs/src/ff.c **** } +1510:Middlewares/Third_Party/FatFs/src/ff.c **** +1511:Middlewares/Third_Party/FatFs/src/ff.c **** +1512:Middlewares/Third_Party/FatFs/src/ff.c **** +1513:Middlewares/Third_Party/FatFs/src/ff.c **** +1514:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1515:Middlewares/Third_Party/FatFs/src/ff.c **** /* Directory handling - Move directory table index next */ +1516:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1517:Middlewares/Third_Party/FatFs/src/ff.c **** +1518:Middlewares/Third_Party/FatFs/src/ff.c **** static +1519:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT dir_next ( /* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */ +1520:Middlewares/Third_Party/FatFs/src/ff.c **** DIR* dp, /* Pointer to the directory object */ +1521:Middlewares/Third_Party/FatFs/src/ff.c **** int stretch /* 0: Do not stretch table, 1: Stretch table if needed */ +1522:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1523:Middlewares/Third_Party/FatFs/src/ff.c **** { +1524:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD ofs, clst; +1525:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = dp->obj.fs; +1526:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +1527:Middlewares/Third_Party/FatFs/src/ff.c **** UINT n; +1528:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +1529:Middlewares/Third_Party/FatFs/src/ff.c **** +1530:Middlewares/Third_Party/FatFs/src/ff.c **** ofs = dp->dptr + SZDIRE; /* Next entry */ +1531:Middlewares/Third_Party/FatFs/src/ff.c **** if (!dp->sect || ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) re +1532:Middlewares/Third_Party/FatFs/src/ff.c **** +1533:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs % SS(fs) == 0) { /* Sector changed? */ +1534:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect++; /* Next sector */ +1535:Middlewares/Third_Party/FatFs/src/ff.c **** +1536:Middlewares/Third_Party/FatFs/src/ff.c **** if (!dp->clust) { /* Static table */ +1537:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs / SZDIRE >= fs->n_rootdir) { /* Report EOT if it reached end of static table */ +1538:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect = 0; return FR_NO_FILE; +1539:Middlewares/Third_Party/FatFs/src/ff.c **** } +1540:Middlewares/Third_Party/FatFs/src/ff.c **** } +1541:Middlewares/Third_Party/FatFs/src/ff.c **** else { /* Dynamic table */ +1542:Middlewares/Third_Party/FatFs/src/ff.c **** if ((ofs / SS(fs) & (fs->csize - 1)) == 0) { /* Cluster changed? */ +1543:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&dp->obj, dp->clust); /* Get next cluster */ +1544:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst <= 1) return FR_INT_ERR; /* Internal error */ +1545:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ +1546:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst >= fs->n_fatent) { /* Reached end of dynamic table */ +1547:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +1548:Middlewares/Third_Party/FatFs/src/ff.c **** if (!stretch) { /* If no stretch, report EOT */ +1549:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect = 0; return FR_NO_FILE; +1550:Middlewares/Third_Party/FatFs/src/ff.c **** } +1551:Middlewares/Third_Party/FatFs/src/ff.c **** clst = create_chain(&dp->obj, dp->clust); /* Allocate a cluster */ +1552:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0) return FR_DENIED; /* No free cluster */ +1553:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 1) return FR_INT_ERR; /* Internal error */ +1554:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ +1555:Middlewares/Third_Party/FatFs/src/ff.c **** /* Clean-up the stretched table */ +1556:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_EXFAT) dp->obj.stat |= 4; /* The directory needs to be updated */ +1557:Middlewares/Third_Party/FatFs/src/ff.c **** if (sync_window(fs) != FR_OK) return FR_DISK_ERR; /* Flush disk access window */ +1558:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(fs->win, 0, SS(fs)); /* Clear window buffer */ + ARM GAS /tmp/cc2SVLkL.s page 47 + + +1559:Middlewares/Third_Party/FatFs/src/ff.c **** for (n = 0, fs->winsect = clust2sect(fs, clst); n < fs->csize; n++, fs->winsect++) { /* Fill t +1560:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +1561:Middlewares/Third_Party/FatFs/src/ff.c **** if (sync_window(fs) != FR_OK) return FR_DISK_ERR; +1562:Middlewares/Third_Party/FatFs/src/ff.c **** } +1563:Middlewares/Third_Party/FatFs/src/ff.c **** fs->winsect -= n; /* Restore window offset */ +1564:Middlewares/Third_Party/FatFs/src/ff.c **** #else +1565:Middlewares/Third_Party/FatFs/src/ff.c **** if (!stretch) dp->sect = 0; /* (this line is to suppress compiler warning) */ +1566:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect = 0; return FR_NO_FILE; /* Report EOT */ +1567:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +1568:Middlewares/Third_Party/FatFs/src/ff.c **** } +1569:Middlewares/Third_Party/FatFs/src/ff.c **** dp->clust = clst; /* Initialize data for new cluster */ +1570:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect = clust2sect(fs, clst); +1571:Middlewares/Third_Party/FatFs/src/ff.c **** } +1572:Middlewares/Third_Party/FatFs/src/ff.c **** } +1573:Middlewares/Third_Party/FatFs/src/ff.c **** } +1574:Middlewares/Third_Party/FatFs/src/ff.c **** dp->dptr = ofs; /* Current entry */ +1575:Middlewares/Third_Party/FatFs/src/ff.c **** dp->dir = fs->win + ofs % SS(fs); /* Pointer to the entry in the win[] */ +1576:Middlewares/Third_Party/FatFs/src/ff.c **** +1577:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_OK; +1578:Middlewares/Third_Party/FatFs/src/ff.c **** } +1579:Middlewares/Third_Party/FatFs/src/ff.c **** +1580:Middlewares/Third_Party/FatFs/src/ff.c **** +1581:Middlewares/Third_Party/FatFs/src/ff.c **** +1582:Middlewares/Third_Party/FatFs/src/ff.c **** +1583:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +1584:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1585:Middlewares/Third_Party/FatFs/src/ff.c **** /* Directory handling - Reserve a block of directory entries */ +1586:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1587:Middlewares/Third_Party/FatFs/src/ff.c **** +1588:Middlewares/Third_Party/FatFs/src/ff.c **** static +1589:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT dir_alloc ( /* FR_OK(0):succeeded, !=0:error */ +1590:Middlewares/Third_Party/FatFs/src/ff.c **** DIR* dp, /* Pointer to the directory object */ +1591:Middlewares/Third_Party/FatFs/src/ff.c **** UINT nent /* Number of contiguous entries to allocate */ +1592:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1593:Middlewares/Third_Party/FatFs/src/ff.c **** { +1594:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +1595:Middlewares/Third_Party/FatFs/src/ff.c **** UINT n; +1596:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = dp->obj.fs; +1597:Middlewares/Third_Party/FatFs/src/ff.c **** +1598:Middlewares/Third_Party/FatFs/src/ff.c **** +1599:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(dp, 0); +1600:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +1601:Middlewares/Third_Party/FatFs/src/ff.c **** n = 0; +1602:Middlewares/Third_Party/FatFs/src/ff.c **** do { +1603:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dp->sect); +1604:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +1605:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +1606:Middlewares/Third_Party/FatFs/src/ff.c **** if ((fs->fs_type == FS_EXFAT) ? (int)((dp->dir[XDIR_Type] & 0x80) == 0) : (int)(dp->dir[DIR_Name +1607:Middlewares/Third_Party/FatFs/src/ff.c **** #else +1608:Middlewares/Third_Party/FatFs/src/ff.c **** if (dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0) { +1609:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +1610:Middlewares/Third_Party/FatFs/src/ff.c **** if (++n == nent) break; /* A block of contiguous free entries is found */ +1611:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +1612:Middlewares/Third_Party/FatFs/src/ff.c **** n = 0; /* Not a blank entry. Restart to search */ +1613:Middlewares/Third_Party/FatFs/src/ff.c **** } +1614:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_next(dp, 1); +1615:Middlewares/Third_Party/FatFs/src/ff.c **** } while (res == FR_OK); /* Next entry with table stretch enabled */ + ARM GAS /tmp/cc2SVLkL.s page 48 + + +1616:Middlewares/Third_Party/FatFs/src/ff.c **** } +1617:Middlewares/Third_Party/FatFs/src/ff.c **** +1618:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) res = FR_DENIED; /* No directory entry to allocate */ +1619:Middlewares/Third_Party/FatFs/src/ff.c **** return res; +1620:Middlewares/Third_Party/FatFs/src/ff.c **** } +1621:Middlewares/Third_Party/FatFs/src/ff.c **** +1622:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* !_FS_READONLY */ +1623:Middlewares/Third_Party/FatFs/src/ff.c **** +1624:Middlewares/Third_Party/FatFs/src/ff.c **** +1625:Middlewares/Third_Party/FatFs/src/ff.c **** +1626:Middlewares/Third_Party/FatFs/src/ff.c **** +1627:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1628:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT: Directory handling - Load/Store start cluster number */ +1629:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1630:Middlewares/Third_Party/FatFs/src/ff.c **** +1631:Middlewares/Third_Party/FatFs/src/ff.c **** static +1632:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD ld_clust ( /* Returns the top cluster value of the SFN entry */ +1633:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS* fs, /* Pointer to the fs object */ +1634:Middlewares/Third_Party/FatFs/src/ff.c **** const BYTE* dir /* Pointer to the key entry */ +1635:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1636:Middlewares/Third_Party/FatFs/src/ff.c **** { + 1023 .loc 1 1636 1 is_stmt 1 view -0 + 1024 .cfi_startproc + 1025 @ args = 0, pretend = 0, frame = 0 + 1026 @ frame_needed = 0, uses_anonymous_args = 0 + 1027 .loc 1 1636 1 is_stmt 0 view .LVU295 + 1028 0000 70B5 push {r4, r5, r6, lr} + 1029 .LCFI10: + 1030 .cfi_def_cfa_offset 16 + 1031 .cfi_offset 4, -16 + 1032 .cfi_offset 5, -12 + 1033 .cfi_offset 6, -8 + 1034 .cfi_offset 14, -4 + 1035 0002 0646 mov r6, r0 + 1036 0004 0D46 mov r5, r1 +1637:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD cl; + 1037 .loc 1 1637 2 is_stmt 1 view .LVU296 +1638:Middlewares/Third_Party/FatFs/src/ff.c **** +1639:Middlewares/Third_Party/FatFs/src/ff.c **** cl = ld_word(dir + DIR_FstClusLO); + 1038 .loc 1 1639 2 view .LVU297 + 1039 .loc 1 1639 7 is_stmt 0 view .LVU298 + 1040 0006 01F11A00 add r0, r1, #26 + 1041 .LVL102: + 1042 .loc 1 1639 7 view .LVU299 + 1043 000a FFF7FEFF bl ld_word + 1044 .LVL103: +1640:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_FAT32) { + 1045 .loc 1 1640 2 is_stmt 1 view .LVU300 + 1046 .loc 1 1640 8 is_stmt 0 view .LVU301 + 1047 000e 3378 ldrb r3, [r6] @ zero_extendqisi2 + 1048 .loc 1 1640 5 view .LVU302 + 1049 0010 032B cmp r3, #3 + 1050 0012 00D0 beq .L94 + 1051 .LVL104: + 1052 .L91: +1641:Middlewares/Third_Party/FatFs/src/ff.c **** cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16; +1642:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 49 + + +1643:Middlewares/Third_Party/FatFs/src/ff.c **** +1644:Middlewares/Third_Party/FatFs/src/ff.c **** return cl; +1645:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1053 .loc 1 1645 1 view .LVU303 + 1054 0014 70BD pop {r4, r5, r6, pc} + 1055 .LVL105: + 1056 .L94: + 1057 .loc 1 1645 1 view .LVU304 + 1058 0016 0446 mov r4, r0 +1641:Middlewares/Third_Party/FatFs/src/ff.c **** cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16; + 1059 .loc 1 1641 3 is_stmt 1 view .LVU305 +1641:Middlewares/Third_Party/FatFs/src/ff.c **** cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16; + 1060 .loc 1 1641 16 is_stmt 0 view .LVU306 + 1061 0018 05F11400 add r0, r5, #20 + 1062 .LVL106: +1641:Middlewares/Third_Party/FatFs/src/ff.c **** cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16; + 1063 .loc 1 1641 16 view .LVU307 + 1064 001c FFF7FEFF bl ld_word + 1065 .LVL107: +1641:Middlewares/Third_Party/FatFs/src/ff.c **** cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16; + 1066 .loc 1 1641 6 discriminator 1 view .LVU308 + 1067 0020 44EA0040 orr r0, r4, r0, lsl #16 + 1068 .LVL108: +1644:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1069 .loc 1 1644 2 is_stmt 1 view .LVU309 +1644:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1070 .loc 1 1644 9 is_stmt 0 view .LVU310 + 1071 0024 F6E7 b .L91 + 1072 .cfi_endproc + 1073 .LFE1208: + 1075 .section .text.st_clust,"ax",%progbits + 1076 .align 1 + 1077 .syntax unified + 1078 .thumb + 1079 .thumb_func + 1081 st_clust: + 1082 .LVL109: + 1083 .LFB1209: +1646:Middlewares/Third_Party/FatFs/src/ff.c **** +1647:Middlewares/Third_Party/FatFs/src/ff.c **** +1648:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +1649:Middlewares/Third_Party/FatFs/src/ff.c **** static +1650:Middlewares/Third_Party/FatFs/src/ff.c **** void st_clust ( +1651:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS* fs, /* Pointer to the fs object */ +1652:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE* dir, /* Pointer to the key entry */ +1653:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD cl /* Value to be set */ +1654:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1655:Middlewares/Third_Party/FatFs/src/ff.c **** { + 1084 .loc 1 1655 1 is_stmt 1 view -0 + 1085 .cfi_startproc + 1086 @ args = 0, pretend = 0, frame = 0 + 1087 @ frame_needed = 0, uses_anonymous_args = 0 + 1088 .loc 1 1655 1 is_stmt 0 view .LVU312 + 1089 0000 70B5 push {r4, r5, r6, lr} + 1090 .LCFI11: + 1091 .cfi_def_cfa_offset 16 + 1092 .cfi_offset 4, -16 + ARM GAS /tmp/cc2SVLkL.s page 50 + + + 1093 .cfi_offset 5, -12 + 1094 .cfi_offset 6, -8 + 1095 .cfi_offset 14, -4 + 1096 0002 0646 mov r6, r0 + 1097 0004 0C46 mov r4, r1 + 1098 0006 1546 mov r5, r2 +1656:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(dir + DIR_FstClusLO, (WORD)cl); + 1099 .loc 1 1656 2 is_stmt 1 view .LVU313 + 1100 0008 91B2 uxth r1, r2 + 1101 .LVL110: + 1102 .loc 1 1656 2 is_stmt 0 view .LVU314 + 1103 000a 04F11A00 add r0, r4, #26 + 1104 .LVL111: + 1105 .loc 1 1656 2 view .LVU315 + 1106 000e FFF7FEFF bl st_word + 1107 .LVL112: +1657:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_FAT32) { + 1108 .loc 1 1657 2 is_stmt 1 view .LVU316 + 1109 .loc 1 1657 8 is_stmt 0 view .LVU317 + 1110 0012 3378 ldrb r3, [r6] @ zero_extendqisi2 + 1111 .loc 1 1657 5 view .LVU318 + 1112 0014 032B cmp r3, #3 + 1113 0016 00D0 beq .L98 + 1114 .L95: +1658:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(dir + DIR_FstClusHI, (WORD)(cl >> 16)); +1659:Middlewares/Third_Party/FatFs/src/ff.c **** } +1660:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1115 .loc 1 1660 1 view .LVU319 + 1116 0018 70BD pop {r4, r5, r6, pc} + 1117 .LVL113: + 1118 .L98: +1658:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(dir + DIR_FstClusHI, (WORD)(cl >> 16)); + 1119 .loc 1 1658 3 is_stmt 1 view .LVU320 + 1120 001a 290C lsrs r1, r5, #16 + 1121 001c 04F11400 add r0, r4, #20 + 1122 0020 FFF7FEFF bl st_word + 1123 .LVL114: + 1124 .loc 1 1660 1 is_stmt 0 view .LVU321 + 1125 0024 F8E7 b .L95 + 1126 .cfi_endproc + 1127 .LFE1209: + 1129 .section .text.get_fileinfo,"ax",%progbits + 1130 .align 1 + 1131 .syntax unified + 1132 .thumb + 1133 .thumb_func + 1135 get_fileinfo: + 1136 .LVL115: + 1137 .LFB1214: +1661:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +1662:Middlewares/Third_Party/FatFs/src/ff.c **** +1663:Middlewares/Third_Party/FatFs/src/ff.c **** +1664:Middlewares/Third_Party/FatFs/src/ff.c **** +1665:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 +1666:Middlewares/Third_Party/FatFs/src/ff.c **** /*------------------------------------------------------------------------*/ +1667:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT-LFN: LFN handling */ +1668:Middlewares/Third_Party/FatFs/src/ff.c **** /*------------------------------------------------------------------------*/ + ARM GAS /tmp/cc2SVLkL.s page 51 + + +1669:Middlewares/Third_Party/FatFs/src/ff.c **** static +1670:Middlewares/Third_Party/FatFs/src/ff.c **** const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN characters in the direc +1671:Middlewares/Third_Party/FatFs/src/ff.c **** +1672:Middlewares/Third_Party/FatFs/src/ff.c **** +1673:Middlewares/Third_Party/FatFs/src/ff.c **** /*--------------------------------------------------------*/ +1674:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT-LFN: Compare a part of file name with an LFN entry */ +1675:Middlewares/Third_Party/FatFs/src/ff.c **** /*--------------------------------------------------------*/ +1676:Middlewares/Third_Party/FatFs/src/ff.c **** static +1677:Middlewares/Third_Party/FatFs/src/ff.c **** int cmp_lfn ( /* 1:matched, 0:not matched */ +1678:Middlewares/Third_Party/FatFs/src/ff.c **** const WCHAR* lfnbuf, /* Pointer to the LFN working buffer to be compared */ +1679:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE* dir /* Pointer to the directory entry containing the part of LFN */ +1680:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1681:Middlewares/Third_Party/FatFs/src/ff.c **** { +1682:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i, s; +1683:Middlewares/Third_Party/FatFs/src/ff.c **** WCHAR wc, uc; +1684:Middlewares/Third_Party/FatFs/src/ff.c **** +1685:Middlewares/Third_Party/FatFs/src/ff.c **** +1686:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO */ +1687:Middlewares/Third_Party/FatFs/src/ff.c **** +1688:Middlewares/Third_Party/FatFs/src/ff.c **** i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ +1689:Middlewares/Third_Party/FatFs/src/ff.c **** +1690:Middlewares/Third_Party/FatFs/src/ff.c **** for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */ +1691:Middlewares/Third_Party/FatFs/src/ff.c **** uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */ +1692:Middlewares/Third_Party/FatFs/src/ff.c **** if (wc) { +1693:Middlewares/Third_Party/FatFs/src/ff.c **** if (i >= _MAX_LFN || ff_wtoupper(uc) != ff_wtoupper(lfnbuf[i++])) { /* Compare it */ +1694:Middlewares/Third_Party/FatFs/src/ff.c **** return 0; /* Not matched */ +1695:Middlewares/Third_Party/FatFs/src/ff.c **** } +1696:Middlewares/Third_Party/FatFs/src/ff.c **** wc = uc; +1697:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +1698:Middlewares/Third_Party/FatFs/src/ff.c **** if (uc != 0xFFFF) return 0; /* Check filler */ +1699:Middlewares/Third_Party/FatFs/src/ff.c **** } +1700:Middlewares/Third_Party/FatFs/src/ff.c **** } +1701:Middlewares/Third_Party/FatFs/src/ff.c **** +1702:Middlewares/Third_Party/FatFs/src/ff.c **** if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i]) return 0; /* Last segment matched but different len +1703:Middlewares/Third_Party/FatFs/src/ff.c **** +1704:Middlewares/Third_Party/FatFs/src/ff.c **** return 1; /* The part of LFN matched */ +1705:Middlewares/Third_Party/FatFs/src/ff.c **** } +1706:Middlewares/Third_Party/FatFs/src/ff.c **** +1707:Middlewares/Third_Party/FatFs/src/ff.c **** +1708:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 || _USE_LABEL || _FS_EXFAT +1709:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------*/ +1710:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT-LFN: Pick a part of file name from an LFN entry */ +1711:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------*/ +1712:Middlewares/Third_Party/FatFs/src/ff.c **** static +1713:Middlewares/Third_Party/FatFs/src/ff.c **** int pick_lfn ( /* 1:succeeded, 0:buffer overflow or invalid LFN entry */ +1714:Middlewares/Third_Party/FatFs/src/ff.c **** WCHAR* lfnbuf, /* Pointer to the LFN working buffer */ +1715:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE* dir /* Pointer to the LFN entry */ +1716:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1717:Middlewares/Third_Party/FatFs/src/ff.c **** { +1718:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i, s; +1719:Middlewares/Third_Party/FatFs/src/ff.c **** WCHAR wc, uc; +1720:Middlewares/Third_Party/FatFs/src/ff.c **** +1721:Middlewares/Third_Party/FatFs/src/ff.c **** +1722:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO is 0 */ +1723:Middlewares/Third_Party/FatFs/src/ff.c **** +1724:Middlewares/Third_Party/FatFs/src/ff.c **** i = ((dir[LDIR_Ord] & ~LLEF) - 1) * 13; /* Offset in the LFN buffer */ +1725:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 52 + + +1726:Middlewares/Third_Party/FatFs/src/ff.c **** for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */ +1727:Middlewares/Third_Party/FatFs/src/ff.c **** uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */ +1728:Middlewares/Third_Party/FatFs/src/ff.c **** if (wc) { +1729:Middlewares/Third_Party/FatFs/src/ff.c **** if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ +1730:Middlewares/Third_Party/FatFs/src/ff.c **** lfnbuf[i++] = wc = uc; /* Store it */ +1731:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +1732:Middlewares/Third_Party/FatFs/src/ff.c **** if (uc != 0xFFFF) return 0; /* Check filler */ +1733:Middlewares/Third_Party/FatFs/src/ff.c **** } +1734:Middlewares/Third_Party/FatFs/src/ff.c **** } +1735:Middlewares/Third_Party/FatFs/src/ff.c **** +1736:Middlewares/Third_Party/FatFs/src/ff.c **** if (dir[LDIR_Ord] & LLEF) { /* Put terminator if it is the last LFN part */ +1737:Middlewares/Third_Party/FatFs/src/ff.c **** if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ +1738:Middlewares/Third_Party/FatFs/src/ff.c **** lfnbuf[i] = 0; +1739:Middlewares/Third_Party/FatFs/src/ff.c **** } +1740:Middlewares/Third_Party/FatFs/src/ff.c **** +1741:Middlewares/Third_Party/FatFs/src/ff.c **** return 1; /* The part of LFN is valid */ +1742:Middlewares/Third_Party/FatFs/src/ff.c **** } +1743:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +1744:Middlewares/Third_Party/FatFs/src/ff.c **** +1745:Middlewares/Third_Party/FatFs/src/ff.c **** +1746:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +1747:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------*/ +1748:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT-LFN: Create an entry of LFN entries */ +1749:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------*/ +1750:Middlewares/Third_Party/FatFs/src/ff.c **** static +1751:Middlewares/Third_Party/FatFs/src/ff.c **** void put_lfn ( +1752:Middlewares/Third_Party/FatFs/src/ff.c **** const WCHAR* lfn, /* Pointer to the LFN */ +1753:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE* dir, /* Pointer to the LFN entry to be created */ +1754:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE ord, /* LFN order (1-20) */ +1755:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE sum /* Checksum of the corresponding SFN */ +1756:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1757:Middlewares/Third_Party/FatFs/src/ff.c **** { +1758:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i, s; +1759:Middlewares/Third_Party/FatFs/src/ff.c **** WCHAR wc; +1760:Middlewares/Third_Party/FatFs/src/ff.c **** +1761:Middlewares/Third_Party/FatFs/src/ff.c **** +1762:Middlewares/Third_Party/FatFs/src/ff.c **** dir[LDIR_Chksum] = sum; /* Set checksum */ +1763:Middlewares/Third_Party/FatFs/src/ff.c **** dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ +1764:Middlewares/Third_Party/FatFs/src/ff.c **** dir[LDIR_Type] = 0; +1765:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(dir + LDIR_FstClusLO, 0); +1766:Middlewares/Third_Party/FatFs/src/ff.c **** +1767:Middlewares/Third_Party/FatFs/src/ff.c **** i = (ord - 1) * 13; /* Get offset in the LFN working buffer */ +1768:Middlewares/Third_Party/FatFs/src/ff.c **** s = wc = 0; +1769:Middlewares/Third_Party/FatFs/src/ff.c **** do { +1770:Middlewares/Third_Party/FatFs/src/ff.c **** if (wc != 0xFFFF) wc = lfn[i++]; /* Get an effective character */ +1771:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(dir + LfnOfs[s], wc); /* Put it */ +1772:Middlewares/Third_Party/FatFs/src/ff.c **** if (wc == 0) wc = 0xFFFF; /* Padding characters for left locations */ +1773:Middlewares/Third_Party/FatFs/src/ff.c **** } while (++s < 13); +1774:Middlewares/Third_Party/FatFs/src/ff.c **** if (wc == 0xFFFF || !lfn[i]) ord |= LLEF; /* Last LFN part is the start of LFN sequence */ +1775:Middlewares/Third_Party/FatFs/src/ff.c **** dir[LDIR_Ord] = ord; /* Set the LFN order */ +1776:Middlewares/Third_Party/FatFs/src/ff.c **** } +1777:Middlewares/Third_Party/FatFs/src/ff.c **** +1778:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* !_FS_READONLY */ +1779:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _USE_LFN != 0 */ +1780:Middlewares/Third_Party/FatFs/src/ff.c **** +1781:Middlewares/Third_Party/FatFs/src/ff.c **** +1782:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 53 + + +1783:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 && !_FS_READONLY +1784:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1785:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT-LFN: Create a Numbered SFN */ +1786:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1787:Middlewares/Third_Party/FatFs/src/ff.c **** +1788:Middlewares/Third_Party/FatFs/src/ff.c **** static +1789:Middlewares/Third_Party/FatFs/src/ff.c **** void gen_numname ( +1790:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE* dst, /* Pointer to the buffer to store numbered SFN */ +1791:Middlewares/Third_Party/FatFs/src/ff.c **** const BYTE* src, /* Pointer to SFN */ +1792:Middlewares/Third_Party/FatFs/src/ff.c **** const WCHAR* lfn, /* Pointer to LFN */ +1793:Middlewares/Third_Party/FatFs/src/ff.c **** UINT seq /* Sequence number */ +1794:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1795:Middlewares/Third_Party/FatFs/src/ff.c **** { +1796:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE ns[8], c; +1797:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i, j; +1798:Middlewares/Third_Party/FatFs/src/ff.c **** WCHAR wc; +1799:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD sr; +1800:Middlewares/Third_Party/FatFs/src/ff.c **** +1801:Middlewares/Third_Party/FatFs/src/ff.c **** +1802:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(dst, src, 11); +1803:Middlewares/Third_Party/FatFs/src/ff.c **** +1804:Middlewares/Third_Party/FatFs/src/ff.c **** if (seq > 5) { /* In case of many collisions, generate a hash number instead of sequential number +1805:Middlewares/Third_Party/FatFs/src/ff.c **** sr = seq; +1806:Middlewares/Third_Party/FatFs/src/ff.c **** while (*lfn) { /* Create a CRC */ +1807:Middlewares/Third_Party/FatFs/src/ff.c **** wc = *lfn++; +1808:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < 16; i++) { +1809:Middlewares/Third_Party/FatFs/src/ff.c **** sr = (sr << 1) + (wc & 1); +1810:Middlewares/Third_Party/FatFs/src/ff.c **** wc >>= 1; +1811:Middlewares/Third_Party/FatFs/src/ff.c **** if (sr & 0x10000) sr ^= 0x11021; +1812:Middlewares/Third_Party/FatFs/src/ff.c **** } +1813:Middlewares/Third_Party/FatFs/src/ff.c **** } +1814:Middlewares/Third_Party/FatFs/src/ff.c **** seq = (UINT)sr; +1815:Middlewares/Third_Party/FatFs/src/ff.c **** } +1816:Middlewares/Third_Party/FatFs/src/ff.c **** +1817:Middlewares/Third_Party/FatFs/src/ff.c **** /* itoa (hexdecimal) */ +1818:Middlewares/Third_Party/FatFs/src/ff.c **** i = 7; +1819:Middlewares/Third_Party/FatFs/src/ff.c **** do { +1820:Middlewares/Third_Party/FatFs/src/ff.c **** c = (BYTE)((seq % 16) + '0'); +1821:Middlewares/Third_Party/FatFs/src/ff.c **** if (c > '9') c += 7; +1822:Middlewares/Third_Party/FatFs/src/ff.c **** ns[i--] = c; +1823:Middlewares/Third_Party/FatFs/src/ff.c **** seq /= 16; +1824:Middlewares/Third_Party/FatFs/src/ff.c **** } while (seq); +1825:Middlewares/Third_Party/FatFs/src/ff.c **** ns[i] = '~'; +1826:Middlewares/Third_Party/FatFs/src/ff.c **** +1827:Middlewares/Third_Party/FatFs/src/ff.c **** /* Append the number */ +1828:Middlewares/Third_Party/FatFs/src/ff.c **** for (j = 0; j < i && dst[j] != ' '; j++) { +1829:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsDBCS1(dst[j])) { +1830:Middlewares/Third_Party/FatFs/src/ff.c **** if (j == i - 1) break; +1831:Middlewares/Third_Party/FatFs/src/ff.c **** j++; +1832:Middlewares/Third_Party/FatFs/src/ff.c **** } +1833:Middlewares/Third_Party/FatFs/src/ff.c **** } +1834:Middlewares/Third_Party/FatFs/src/ff.c **** do { +1835:Middlewares/Third_Party/FatFs/src/ff.c **** dst[j++] = (i < 8) ? ns[i++] : ' '; +1836:Middlewares/Third_Party/FatFs/src/ff.c **** } while (j < 8); +1837:Middlewares/Third_Party/FatFs/src/ff.c **** } +1838:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _USE_LFN != 0 && !_FS_READONLY */ +1839:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 54 + + +1840:Middlewares/Third_Party/FatFs/src/ff.c **** +1841:Middlewares/Third_Party/FatFs/src/ff.c **** +1842:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 +1843:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1844:Middlewares/Third_Party/FatFs/src/ff.c **** /* FAT-LFN: Calculate checksum of an SFN entry */ +1845:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1846:Middlewares/Third_Party/FatFs/src/ff.c **** +1847:Middlewares/Third_Party/FatFs/src/ff.c **** static +1848:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE sum_sfn ( +1849:Middlewares/Third_Party/FatFs/src/ff.c **** const BYTE* dir /* Pointer to the SFN entry */ +1850:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1851:Middlewares/Third_Party/FatFs/src/ff.c **** { +1852:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE sum = 0; +1853:Middlewares/Third_Party/FatFs/src/ff.c **** UINT n = 11; +1854:Middlewares/Third_Party/FatFs/src/ff.c **** +1855:Middlewares/Third_Party/FatFs/src/ff.c **** do { +1856:Middlewares/Third_Party/FatFs/src/ff.c **** sum = (sum >> 1) + (sum << 7) + *dir++; +1857:Middlewares/Third_Party/FatFs/src/ff.c **** } while (--n); +1858:Middlewares/Third_Party/FatFs/src/ff.c **** return sum; +1859:Middlewares/Third_Party/FatFs/src/ff.c **** } +1860:Middlewares/Third_Party/FatFs/src/ff.c **** +1861:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _USE_LFN != 0 */ +1862:Middlewares/Third_Party/FatFs/src/ff.c **** +1863:Middlewares/Third_Party/FatFs/src/ff.c **** +1864:Middlewares/Third_Party/FatFs/src/ff.c **** +1865:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +1866:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1867:Middlewares/Third_Party/FatFs/src/ff.c **** /* exFAT: Checksum */ +1868:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +1869:Middlewares/Third_Party/FatFs/src/ff.c **** +1870:Middlewares/Third_Party/FatFs/src/ff.c **** static +1871:Middlewares/Third_Party/FatFs/src/ff.c **** WORD xdir_sum ( /* Get checksum of the directoly block */ +1872:Middlewares/Third_Party/FatFs/src/ff.c **** const BYTE* dir /* Directory entry block to be calculated */ +1873:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1874:Middlewares/Third_Party/FatFs/src/ff.c **** { +1875:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i, szblk; +1876:Middlewares/Third_Party/FatFs/src/ff.c **** WORD sum; +1877:Middlewares/Third_Party/FatFs/src/ff.c **** +1878:Middlewares/Third_Party/FatFs/src/ff.c **** +1879:Middlewares/Third_Party/FatFs/src/ff.c **** szblk = (dir[XDIR_NumSec] + 1) * SZDIRE; +1880:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = sum = 0; i < szblk; i++) { +1881:Middlewares/Third_Party/FatFs/src/ff.c **** if (i == XDIR_SetSum) { /* Skip sum field */ +1882:Middlewares/Third_Party/FatFs/src/ff.c **** i++; +1883:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +1884:Middlewares/Third_Party/FatFs/src/ff.c **** sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + dir[i]; +1885:Middlewares/Third_Party/FatFs/src/ff.c **** } +1886:Middlewares/Third_Party/FatFs/src/ff.c **** } +1887:Middlewares/Third_Party/FatFs/src/ff.c **** return sum; +1888:Middlewares/Third_Party/FatFs/src/ff.c **** } +1889:Middlewares/Third_Party/FatFs/src/ff.c **** +1890:Middlewares/Third_Party/FatFs/src/ff.c **** +1891:Middlewares/Third_Party/FatFs/src/ff.c **** +1892:Middlewares/Third_Party/FatFs/src/ff.c **** static +1893:Middlewares/Third_Party/FatFs/src/ff.c **** WORD xname_sum ( /* Get check sum (to be used as hash) of the name */ +1894:Middlewares/Third_Party/FatFs/src/ff.c **** const WCHAR* name /* File name to be calculated */ +1895:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1896:Middlewares/Third_Party/FatFs/src/ff.c **** { + ARM GAS /tmp/cc2SVLkL.s page 55 + + +1897:Middlewares/Third_Party/FatFs/src/ff.c **** WCHAR chr; +1898:Middlewares/Third_Party/FatFs/src/ff.c **** WORD sum = 0; +1899:Middlewares/Third_Party/FatFs/src/ff.c **** +1900:Middlewares/Third_Party/FatFs/src/ff.c **** +1901:Middlewares/Third_Party/FatFs/src/ff.c **** while ((chr = *name++) != 0) { +1902:Middlewares/Third_Party/FatFs/src/ff.c **** chr = ff_wtoupper(chr); /* File name needs to be ignored case */ +1903:Middlewares/Third_Party/FatFs/src/ff.c **** sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr & 0xFF); +1904:Middlewares/Third_Party/FatFs/src/ff.c **** sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr >> 8); +1905:Middlewares/Third_Party/FatFs/src/ff.c **** } +1906:Middlewares/Third_Party/FatFs/src/ff.c **** return sum; +1907:Middlewares/Third_Party/FatFs/src/ff.c **** } +1908:Middlewares/Third_Party/FatFs/src/ff.c **** +1909:Middlewares/Third_Party/FatFs/src/ff.c **** +1910:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _USE_MKFS +1911:Middlewares/Third_Party/FatFs/src/ff.c **** static +1912:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD xsum32 ( +1913:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE dat, /* Data to be sumed */ +1914:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD sum /* Previous value */ +1915:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1916:Middlewares/Third_Party/FatFs/src/ff.c **** { +1917:Middlewares/Third_Party/FatFs/src/ff.c **** sum = ((sum & 1) ? 0x80000000 : 0) + (sum >> 1) + dat; +1918:Middlewares/Third_Party/FatFs/src/ff.c **** return sum; +1919:Middlewares/Third_Party/FatFs/src/ff.c **** } +1920:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +1921:Middlewares/Third_Party/FatFs/src/ff.c **** +1922:Middlewares/Third_Party/FatFs/src/ff.c **** +1923:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 +1924:Middlewares/Third_Party/FatFs/src/ff.c **** /*------------------------------------------------------*/ +1925:Middlewares/Third_Party/FatFs/src/ff.c **** /* exFAT: Get object information from a directory block */ +1926:Middlewares/Third_Party/FatFs/src/ff.c **** /*------------------------------------------------------*/ +1927:Middlewares/Third_Party/FatFs/src/ff.c **** +1928:Middlewares/Third_Party/FatFs/src/ff.c **** static +1929:Middlewares/Third_Party/FatFs/src/ff.c **** void get_xdir_info ( +1930:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE* dirb, /* Pointer to the direcotry entry block 85+C0+C1s */ +1931:Middlewares/Third_Party/FatFs/src/ff.c **** FILINFO* fno /* Buffer to store the extracted file information */ +1932:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1933:Middlewares/Third_Party/FatFs/src/ff.c **** { +1934:Middlewares/Third_Party/FatFs/src/ff.c **** UINT di, si; +1935:Middlewares/Third_Party/FatFs/src/ff.c **** WCHAR w; +1936:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_LFN_UNICODE +1937:Middlewares/Third_Party/FatFs/src/ff.c **** UINT nc; +1938:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +1939:Middlewares/Third_Party/FatFs/src/ff.c **** +1940:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get file name */ +1941:Middlewares/Third_Party/FatFs/src/ff.c **** di = 0; +1942:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE +1943:Middlewares/Third_Party/FatFs/src/ff.c **** for (si = SZDIRE * 2; di < dirb[XDIR_NumName]; si += 2, di++) { +1944:Middlewares/Third_Party/FatFs/src/ff.c **** if ((si % SZDIRE) == 0) si += 2; /* Skip entry type field */ +1945:Middlewares/Third_Party/FatFs/src/ff.c **** w = ld_word(dirb + si); /* Get a character */ +1946:Middlewares/Third_Party/FatFs/src/ff.c **** if (di >= _MAX_LFN) { di = 0; break; } /* Buffer overflow --> inaccessible object name */ +1947:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fname[di] = w; /* Store it */ +1948:Middlewares/Third_Party/FatFs/src/ff.c **** } +1949:Middlewares/Third_Party/FatFs/src/ff.c **** #else +1950:Middlewares/Third_Party/FatFs/src/ff.c **** for (si = SZDIRE * 2, nc = 0; nc < dirb[XDIR_NumName]; si += 2, nc++) { +1951:Middlewares/Third_Party/FatFs/src/ff.c **** if ((si % SZDIRE) == 0) si += 2; /* Skip entry type field */ +1952:Middlewares/Third_Party/FatFs/src/ff.c **** w = ff_convert(ld_word(dirb + si), 0); /* Get a character and Unicode -> OEM */ +1953:Middlewares/Third_Party/FatFs/src/ff.c **** if (_DF1S && w >= 0x100) { /* Is it a double byte char? (always false at SBCS cfg) */ + ARM GAS /tmp/cc2SVLkL.s page 56 + + +1954:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fname[di++] = (char)(w >> 8); /* Put 1st byte of the DBC */ +1955:Middlewares/Third_Party/FatFs/src/ff.c **** } +1956:Middlewares/Third_Party/FatFs/src/ff.c **** if (w == 0 || di >= _MAX_LFN) { di = 0; break; } /* Invalid char or buffer overflow --> inaccessi +1957:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fname[di++] = (char)w; +1958:Middlewares/Third_Party/FatFs/src/ff.c **** } +1959:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +1960:Middlewares/Third_Party/FatFs/src/ff.c **** if (di == 0) fno->fname[di++] = '?'; /* Inaccessible object name? */ +1961:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fname[di] = 0; /* Terminate file name */ +1962:Middlewares/Third_Party/FatFs/src/ff.c **** +1963:Middlewares/Third_Party/FatFs/src/ff.c **** fno->altname[0] = 0; /* No SFN */ +1964:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fattrib = dirb[XDIR_Attr]; /* Attribute */ +1965:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fsize = (fno->fattrib & AM_DIR) ? 0 : ld_qword(dirb + XDIR_FileSize); /* Size */ +1966:Middlewares/Third_Party/FatFs/src/ff.c **** fno->ftime = ld_word(dirb + XDIR_ModTime + 0); /* Time */ +1967:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fdate = ld_word(dirb + XDIR_ModTime + 2); /* Date */ +1968:Middlewares/Third_Party/FatFs/src/ff.c **** } +1969:Middlewares/Third_Party/FatFs/src/ff.c **** +1970:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 */ +1971:Middlewares/Third_Party/FatFs/src/ff.c **** +1972:Middlewares/Third_Party/FatFs/src/ff.c **** +1973:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------*/ +1974:Middlewares/Third_Party/FatFs/src/ff.c **** /* exFAT: Get a directry entry block */ +1975:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------*/ +1976:Middlewares/Third_Party/FatFs/src/ff.c **** +1977:Middlewares/Third_Party/FatFs/src/ff.c **** static +1978:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT load_xdir ( /* FR_INT_ERR: invalid entry block */ +1979:Middlewares/Third_Party/FatFs/src/ff.c **** DIR* dp /* Pointer to the reading direcotry object pointing the 85 entry */ +1980:Middlewares/Third_Party/FatFs/src/ff.c **** ) +1981:Middlewares/Third_Party/FatFs/src/ff.c **** { +1982:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +1983:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i, sz_ent; +1984:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE* dirb = dp->obj.fs->dirbuf; /* Pointer to the on-memory direcotry entry block 85+C0+C1s */ +1985:Middlewares/Third_Party/FatFs/src/ff.c **** +1986:Middlewares/Third_Party/FatFs/src/ff.c **** +1987:Middlewares/Third_Party/FatFs/src/ff.c **** /* Load 85 entry */ +1988:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(dp->obj.fs, dp->sect); +1989:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; +1990:Middlewares/Third_Party/FatFs/src/ff.c **** if (dp->dir[XDIR_Type] != 0x85) return FR_INT_ERR; +1991:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(dirb + 0, dp->dir, SZDIRE); +1992:Middlewares/Third_Party/FatFs/src/ff.c **** sz_ent = (dirb[XDIR_NumSec] + 1) * SZDIRE; +1993:Middlewares/Third_Party/FatFs/src/ff.c **** if (sz_ent < 3 * SZDIRE || sz_ent > 19 * SZDIRE) return FR_INT_ERR; +1994:Middlewares/Third_Party/FatFs/src/ff.c **** +1995:Middlewares/Third_Party/FatFs/src/ff.c **** /* Load C0 entry */ +1996:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_next(dp, 0); +1997:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; +1998:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(dp->obj.fs, dp->sect); +1999:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; +2000:Middlewares/Third_Party/FatFs/src/ff.c **** if (dp->dir[XDIR_Type] != 0xC0) return FR_INT_ERR; +2001:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(dirb + SZDIRE, dp->dir, SZDIRE); +2002:Middlewares/Third_Party/FatFs/src/ff.c **** if (MAXDIRB(dirb[XDIR_NumName]) > sz_ent) return FR_INT_ERR; +2003:Middlewares/Third_Party/FatFs/src/ff.c **** +2004:Middlewares/Third_Party/FatFs/src/ff.c **** /* Load C1 entries */ +2005:Middlewares/Third_Party/FatFs/src/ff.c **** i = SZDIRE * 2; /* C1 offset */ +2006:Middlewares/Third_Party/FatFs/src/ff.c **** do { +2007:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_next(dp, 0); +2008:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; +2009:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(dp->obj.fs, dp->sect); +2010:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; + ARM GAS /tmp/cc2SVLkL.s page 57 + + +2011:Middlewares/Third_Party/FatFs/src/ff.c **** if (dp->dir[XDIR_Type] != 0xC1) return FR_INT_ERR; +2012:Middlewares/Third_Party/FatFs/src/ff.c **** if (i < MAXDIRB(_MAX_LFN)) mem_cpy(dirb + i, dp->dir, SZDIRE); +2013:Middlewares/Third_Party/FatFs/src/ff.c **** } while ((i += SZDIRE) < sz_ent); +2014:Middlewares/Third_Party/FatFs/src/ff.c **** +2015:Middlewares/Third_Party/FatFs/src/ff.c **** /* Sanity check (do it when accessible object name) */ +2016:Middlewares/Third_Party/FatFs/src/ff.c **** if (i <= MAXDIRB(_MAX_LFN)) { +2017:Middlewares/Third_Party/FatFs/src/ff.c **** if (xdir_sum(dirb) != ld_word(dirb + XDIR_SetSum)) return FR_INT_ERR; +2018:Middlewares/Third_Party/FatFs/src/ff.c **** } +2019:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_OK; +2020:Middlewares/Third_Party/FatFs/src/ff.c **** } +2021:Middlewares/Third_Party/FatFs/src/ff.c **** +2022:Middlewares/Third_Party/FatFs/src/ff.c **** +2023:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY || _FS_RPATH != 0 +2024:Middlewares/Third_Party/FatFs/src/ff.c **** /*------------------------------------------------*/ +2025:Middlewares/Third_Party/FatFs/src/ff.c **** /* exFAT: Load the object's directory entry block */ +2026:Middlewares/Third_Party/FatFs/src/ff.c **** /*------------------------------------------------*/ +2027:Middlewares/Third_Party/FatFs/src/ff.c **** static +2028:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT load_obj_dir ( +2029:Middlewares/Third_Party/FatFs/src/ff.c **** DIR* dp, /* Blank directory object to be used to access containing direcotry */ +2030:Middlewares/Third_Party/FatFs/src/ff.c **** const _FDID* obj /* Object with its containing directory information */ +2031:Middlewares/Third_Party/FatFs/src/ff.c **** ) +2032:Middlewares/Third_Party/FatFs/src/ff.c **** { +2033:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +2034:Middlewares/Third_Party/FatFs/src/ff.c **** +2035:Middlewares/Third_Party/FatFs/src/ff.c **** /* Open object containing directory */ +2036:Middlewares/Third_Party/FatFs/src/ff.c **** dp->obj.fs = obj->fs; +2037:Middlewares/Third_Party/FatFs/src/ff.c **** dp->obj.sclust = obj->c_scl; +2038:Middlewares/Third_Party/FatFs/src/ff.c **** dp->obj.stat = (BYTE)obj->c_size; +2039:Middlewares/Third_Party/FatFs/src/ff.c **** dp->obj.objsize = obj->c_size & 0xFFFFFF00; +2040:Middlewares/Third_Party/FatFs/src/ff.c **** dp->blk_ofs = obj->c_ofs; +2041:Middlewares/Third_Party/FatFs/src/ff.c **** +2042:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(dp, dp->blk_ofs); /* Goto object's entry block */ +2043:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +2044:Middlewares/Third_Party/FatFs/src/ff.c **** res = load_xdir(dp); /* Load the object's entry block */ +2045:Middlewares/Third_Party/FatFs/src/ff.c **** } +2046:Middlewares/Third_Party/FatFs/src/ff.c **** return res; +2047:Middlewares/Third_Party/FatFs/src/ff.c **** } +2048:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2049:Middlewares/Third_Party/FatFs/src/ff.c **** +2050:Middlewares/Third_Party/FatFs/src/ff.c **** +2051:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +2052:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------*/ +2053:Middlewares/Third_Party/FatFs/src/ff.c **** /* exFAT: Store the directory block to the media */ +2054:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------*/ +2055:Middlewares/Third_Party/FatFs/src/ff.c **** static +2056:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT store_xdir ( +2057:Middlewares/Third_Party/FatFs/src/ff.c **** DIR* dp /* Pointer to the direcotry object */ +2058:Middlewares/Third_Party/FatFs/src/ff.c **** ) +2059:Middlewares/Third_Party/FatFs/src/ff.c **** { +2060:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +2061:Middlewares/Third_Party/FatFs/src/ff.c **** UINT nent; +2062:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE* dirb = dp->obj.fs->dirbuf; /* Pointer to the direcotry entry block 85+C0+C1s */ +2063:Middlewares/Third_Party/FatFs/src/ff.c **** +2064:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create set sum */ +2065:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(dirb + XDIR_SetSum, xdir_sum(dirb)); +2066:Middlewares/Third_Party/FatFs/src/ff.c **** nent = dirb[XDIR_NumSec] + 1; +2067:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 58 + + +2068:Middlewares/Third_Party/FatFs/src/ff.c **** /* Store the set of directory to the volume */ +2069:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(dp, dp->blk_ofs); +2070:Middlewares/Third_Party/FatFs/src/ff.c **** while (res == FR_OK) { +2071:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(dp->obj.fs, dp->sect); +2072:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +2073:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(dp->dir, dirb, SZDIRE); +2074:Middlewares/Third_Party/FatFs/src/ff.c **** dp->obj.fs->wflag = 1; +2075:Middlewares/Third_Party/FatFs/src/ff.c **** if (--nent == 0) break; +2076:Middlewares/Third_Party/FatFs/src/ff.c **** dirb += SZDIRE; +2077:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_next(dp, 0); +2078:Middlewares/Third_Party/FatFs/src/ff.c **** } +2079:Middlewares/Third_Party/FatFs/src/ff.c **** return (res == FR_OK || res == FR_DISK_ERR) ? res : FR_INT_ERR; +2080:Middlewares/Third_Party/FatFs/src/ff.c **** } +2081:Middlewares/Third_Party/FatFs/src/ff.c **** +2082:Middlewares/Third_Party/FatFs/src/ff.c **** +2083:Middlewares/Third_Party/FatFs/src/ff.c **** +2084:Middlewares/Third_Party/FatFs/src/ff.c **** /*-------------------------------------------*/ +2085:Middlewares/Third_Party/FatFs/src/ff.c **** /* exFAT: Create a new directory enrty block */ +2086:Middlewares/Third_Party/FatFs/src/ff.c **** /*-------------------------------------------*/ +2087:Middlewares/Third_Party/FatFs/src/ff.c **** +2088:Middlewares/Third_Party/FatFs/src/ff.c **** static +2089:Middlewares/Third_Party/FatFs/src/ff.c **** void create_xdir ( +2090:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE* dirb, /* Pointer to the direcotry entry block buffer */ +2091:Middlewares/Third_Party/FatFs/src/ff.c **** const WCHAR* lfn /* Pointer to the nul terminated file name */ +2092:Middlewares/Third_Party/FatFs/src/ff.c **** ) +2093:Middlewares/Third_Party/FatFs/src/ff.c **** { +2094:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i; +2095:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE nb, nc; +2096:Middlewares/Third_Party/FatFs/src/ff.c **** WCHAR chr; +2097:Middlewares/Third_Party/FatFs/src/ff.c **** +2098:Middlewares/Third_Party/FatFs/src/ff.c **** +2099:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create 85+C0 entry */ +2100:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(dirb, 0, 2 * SZDIRE); +2101:Middlewares/Third_Party/FatFs/src/ff.c **** dirb[XDIR_Type] = 0x85; +2102:Middlewares/Third_Party/FatFs/src/ff.c **** dirb[XDIR_Type + SZDIRE] = 0xC0; +2103:Middlewares/Third_Party/FatFs/src/ff.c **** +2104:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create C1 entries */ +2105:Middlewares/Third_Party/FatFs/src/ff.c **** nc = 0; nb = 1; chr = 1; i = SZDIRE * 2; +2106:Middlewares/Third_Party/FatFs/src/ff.c **** do { +2107:Middlewares/Third_Party/FatFs/src/ff.c **** dirb[i++] = 0xC1; dirb[i++] = 0; /* Entry type C1 */ +2108:Middlewares/Third_Party/FatFs/src/ff.c **** do { /* Fill name field */ +2109:Middlewares/Third_Party/FatFs/src/ff.c **** if (chr && (chr = lfn[nc]) != 0) nc++; /* Get a character if exist */ +2110:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(dirb + i, chr); /* Store it */ +2111:Middlewares/Third_Party/FatFs/src/ff.c **** } while ((i += 2) % SZDIRE != 0); +2112:Middlewares/Third_Party/FatFs/src/ff.c **** nb++; +2113:Middlewares/Third_Party/FatFs/src/ff.c **** } while (lfn[nc]); /* Fill next entry if any char follows */ +2114:Middlewares/Third_Party/FatFs/src/ff.c **** +2115:Middlewares/Third_Party/FatFs/src/ff.c **** dirb[XDIR_NumName] = nc; /* Set name length */ +2116:Middlewares/Third_Party/FatFs/src/ff.c **** dirb[XDIR_NumSec] = nb; /* Set block length */ +2117:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(dirb + XDIR_NameHash, xname_sum(lfn)); /* Set name hash */ +2118:Middlewares/Third_Party/FatFs/src/ff.c **** } +2119:Middlewares/Third_Party/FatFs/src/ff.c **** +2120:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* !_FS_READONLY */ +2121:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _FS_EXFAT */ +2122:Middlewares/Third_Party/FatFs/src/ff.c **** +2123:Middlewares/Third_Party/FatFs/src/ff.c **** +2124:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 59 + + +2125:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 || _USE_LABEL || _FS_EXFAT +2126:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2127:Middlewares/Third_Party/FatFs/src/ff.c **** /* Read an object from the directory */ +2128:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2129:Middlewares/Third_Party/FatFs/src/ff.c **** +2130:Middlewares/Third_Party/FatFs/src/ff.c **** static +2131:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT dir_read ( +2132:Middlewares/Third_Party/FatFs/src/ff.c **** DIR* dp, /* Pointer to the directory object */ +2133:Middlewares/Third_Party/FatFs/src/ff.c **** int vol /* Filtered by 0:file/directory or 1:volume label */ +2134:Middlewares/Third_Party/FatFs/src/ff.c **** ) +2135:Middlewares/Third_Party/FatFs/src/ff.c **** { +2136:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res = FR_NO_FILE; +2137:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = dp->obj.fs; +2138:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE a, c; +2139:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 +2140:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE ord = 0xFF, sum = 0xFF; +2141:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2142:Middlewares/Third_Party/FatFs/src/ff.c **** +2143:Middlewares/Third_Party/FatFs/src/ff.c **** while (dp->sect) { +2144:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dp->sect); +2145:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +2146:Middlewares/Third_Party/FatFs/src/ff.c **** c = dp->dir[DIR_Name]; /* Test for the entry type */ +2147:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == 0) { +2148:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_NO_FILE; break; /* Reached to end of the directory */ +2149:Middlewares/Third_Party/FatFs/src/ff.c **** } +2150:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +2151:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ +2152:Middlewares/Third_Party/FatFs/src/ff.c **** if (_USE_LABEL && vol) { +2153:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == 0x83) break; /* Volume label entry? */ +2154:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +2155:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == 0x85) { /* Start of the file entry block? */ +2156:Middlewares/Third_Party/FatFs/src/ff.c **** dp->blk_ofs = dp->dptr; /* Get location of the block */ +2157:Middlewares/Third_Party/FatFs/src/ff.c **** res = load_xdir(dp); /* Load the entry block */ +2158:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +2159:Middlewares/Third_Party/FatFs/src/ff.c **** dp->obj.attr = fs->dirbuf[XDIR_Attr] & AM_MASK; /* Get attribute */ +2160:Middlewares/Third_Party/FatFs/src/ff.c **** } +2161:Middlewares/Third_Party/FatFs/src/ff.c **** break; +2162:Middlewares/Third_Party/FatFs/src/ff.c **** } +2163:Middlewares/Third_Party/FatFs/src/ff.c **** } +2164:Middlewares/Third_Party/FatFs/src/ff.c **** } else +2165:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2166:Middlewares/Third_Party/FatFs/src/ff.c **** { /* On the FAT12/16/32 volume */ +2167:Middlewares/Third_Party/FatFs/src/ff.c **** dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK; /* Get attribute */ +2168:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 /* LFN configuration */ +2169:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == DDEM || c == '.' || (int)((a & ~AM_ARC) == AM_VOL) != vol) { /* An entry without valid +2170:Middlewares/Third_Party/FatFs/src/ff.c **** ord = 0xFF; +2171:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +2172:Middlewares/Third_Party/FatFs/src/ff.c **** if (a == AM_LFN) { /* An LFN entry is found */ +2173:Middlewares/Third_Party/FatFs/src/ff.c **** if (c & LLEF) { /* Is it start of an LFN sequence? */ +2174:Middlewares/Third_Party/FatFs/src/ff.c **** sum = dp->dir[LDIR_Chksum]; +2175:Middlewares/Third_Party/FatFs/src/ff.c **** c &= (BYTE)~LLEF; ord = c; +2176:Middlewares/Third_Party/FatFs/src/ff.c **** dp->blk_ofs = dp->dptr; +2177:Middlewares/Third_Party/FatFs/src/ff.c **** } +2178:Middlewares/Third_Party/FatFs/src/ff.c **** /* Check LFN validity and capture it */ +2179:Middlewares/Third_Party/FatFs/src/ff.c **** ord = (c == ord && sum == dp->dir[LDIR_Chksum] && pick_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0 +2180:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* An SFN entry is found */ +2181:Middlewares/Third_Party/FatFs/src/ff.c **** if (ord || sum != sum_sfn(dp->dir)) { /* Is there a valid LFN? */ + ARM GAS /tmp/cc2SVLkL.s page 60 + + +2182:Middlewares/Third_Party/FatFs/src/ff.c **** dp->blk_ofs = 0xFFFFFFFF; /* It has no LFN. */ +2183:Middlewares/Third_Party/FatFs/src/ff.c **** } +2184:Middlewares/Third_Party/FatFs/src/ff.c **** break; +2185:Middlewares/Third_Party/FatFs/src/ff.c **** } +2186:Middlewares/Third_Party/FatFs/src/ff.c **** } +2187:Middlewares/Third_Party/FatFs/src/ff.c **** #else /* Non LFN configuration */ +2188:Middlewares/Third_Party/FatFs/src/ff.c **** if (c != DDEM && c != '.' && a != AM_LFN && (int)((a & ~AM_ARC) == AM_VOL) == vol) { /* Is it a +2189:Middlewares/Third_Party/FatFs/src/ff.c **** break; +2190:Middlewares/Third_Party/FatFs/src/ff.c **** } +2191:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2192:Middlewares/Third_Party/FatFs/src/ff.c **** } +2193:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_next(dp, 0); /* Next entry */ +2194:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +2195:Middlewares/Third_Party/FatFs/src/ff.c **** } +2196:Middlewares/Third_Party/FatFs/src/ff.c **** +2197:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) dp->sect = 0; /* Terminate the read operation on error or EOT */ +2198:Middlewares/Third_Party/FatFs/src/ff.c **** return res; +2199:Middlewares/Third_Party/FatFs/src/ff.c **** } +2200:Middlewares/Third_Party/FatFs/src/ff.c **** +2201:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 */ +2202:Middlewares/Third_Party/FatFs/src/ff.c **** +2203:Middlewares/Third_Party/FatFs/src/ff.c **** +2204:Middlewares/Third_Party/FatFs/src/ff.c **** +2205:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2206:Middlewares/Third_Party/FatFs/src/ff.c **** /* Directory handling - Find an object in the directory */ +2207:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2208:Middlewares/Third_Party/FatFs/src/ff.c **** +2209:Middlewares/Third_Party/FatFs/src/ff.c **** static +2210:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT dir_find ( /* FR_OK(0):succeeded, !=0:error */ +2211:Middlewares/Third_Party/FatFs/src/ff.c **** DIR* dp /* Pointer to the directory object with the file name */ +2212:Middlewares/Third_Party/FatFs/src/ff.c **** ) +2213:Middlewares/Third_Party/FatFs/src/ff.c **** { +2214:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +2215:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = dp->obj.fs; +2216:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE c; +2217:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 +2218:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE a, ord, sum; +2219:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2220:Middlewares/Third_Party/FatFs/src/ff.c **** +2221:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(dp, 0); /* Rewind directory object */ +2222:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; +2223:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +2224:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ +2225:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE nc; +2226:Middlewares/Third_Party/FatFs/src/ff.c **** UINT di, ni; +2227:Middlewares/Third_Party/FatFs/src/ff.c **** WORD hash = xname_sum(fs->lfnbuf); /* Hash value of the name to find */ +2228:Middlewares/Third_Party/FatFs/src/ff.c **** +2229:Middlewares/Third_Party/FatFs/src/ff.c **** while ((res = dir_read(dp, 0)) == FR_OK) { /* Read an item */ +2230:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_LFN < 255 +2231:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->dirbuf[XDIR_NumName] > _MAX_LFN) continue; /* Skip comparison if inaccessible object n +2232:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2233:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_word(fs->dirbuf + XDIR_NameHash) != hash) continue; /* Skip comparison if hash mismatched +2234:Middlewares/Third_Party/FatFs/src/ff.c **** for (nc = fs->dirbuf[XDIR_NumName], di = SZDIRE * 2, ni = 0; nc; nc--, di += 2, ni++) { /* Compa +2235:Middlewares/Third_Party/FatFs/src/ff.c **** if ((di % SZDIRE) == 0) di += 2; +2236:Middlewares/Third_Party/FatFs/src/ff.c **** if (ff_wtoupper(ld_word(fs->dirbuf + di)) != ff_wtoupper(fs->lfnbuf[ni])) break; +2237:Middlewares/Third_Party/FatFs/src/ff.c **** } +2238:Middlewares/Third_Party/FatFs/src/ff.c **** if (nc == 0 && !fs->lfnbuf[ni]) break; /* Name matched? */ + ARM GAS /tmp/cc2SVLkL.s page 61 + + +2239:Middlewares/Third_Party/FatFs/src/ff.c **** } +2240:Middlewares/Third_Party/FatFs/src/ff.c **** return res; +2241:Middlewares/Third_Party/FatFs/src/ff.c **** } +2242:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2243:Middlewares/Third_Party/FatFs/src/ff.c **** /* On the FAT12/16/32 volume */ +2244:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 +2245:Middlewares/Third_Party/FatFs/src/ff.c **** ord = sum = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ +2246:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2247:Middlewares/Third_Party/FatFs/src/ff.c **** do { +2248:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dp->sect); +2249:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +2250:Middlewares/Third_Party/FatFs/src/ff.c **** c = dp->dir[DIR_Name]; +2251:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ +2252:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 /* LFN configuration */ +2253:Middlewares/Third_Party/FatFs/src/ff.c **** dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK; +2254:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ +2255:Middlewares/Third_Party/FatFs/src/ff.c **** ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ +2256:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +2257:Middlewares/Third_Party/FatFs/src/ff.c **** if (a == AM_LFN) { /* An LFN entry is found */ +2258:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(dp->fn[NSFLAG] & NS_NOLFN)) { +2259:Middlewares/Third_Party/FatFs/src/ff.c **** if (c & LLEF) { /* Is it start of LFN sequence? */ +2260:Middlewares/Third_Party/FatFs/src/ff.c **** sum = dp->dir[LDIR_Chksum]; +2261:Middlewares/Third_Party/FatFs/src/ff.c **** c &= (BYTE)~LLEF; ord = c; /* LFN start order */ +2262:Middlewares/Third_Party/FatFs/src/ff.c **** dp->blk_ofs = dp->dptr; /* Start offset of LFN */ +2263:Middlewares/Third_Party/FatFs/src/ff.c **** } +2264:Middlewares/Third_Party/FatFs/src/ff.c **** /* Check validity of the LFN entry and compare it with given name */ +2265:Middlewares/Third_Party/FatFs/src/ff.c **** ord = (c == ord && sum == dp->dir[LDIR_Chksum] && cmp_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0x +2266:Middlewares/Third_Party/FatFs/src/ff.c **** } +2267:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* An SFN entry is found */ +2268:Middlewares/Third_Party/FatFs/src/ff.c **** if (!ord && sum == sum_sfn(dp->dir)) break; /* LFN matched? */ +2269:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(dp->fn[NSFLAG] & NS_LOSS) && !mem_cmp(dp->dir, dp->fn, 11)) break; /* SFN matched? */ +2270:Middlewares/Third_Party/FatFs/src/ff.c **** ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */ +2271:Middlewares/Third_Party/FatFs/src/ff.c **** } +2272:Middlewares/Third_Party/FatFs/src/ff.c **** } +2273:Middlewares/Third_Party/FatFs/src/ff.c **** #else /* Non LFN configuration */ +2274:Middlewares/Third_Party/FatFs/src/ff.c **** dp->obj.attr = dp->dir[DIR_Attr] & AM_MASK; +2275:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(dp->dir[DIR_Attr] & AM_VOL) && !mem_cmp(dp->dir, dp->fn, 11)) break; /* Is it a valid entry +2276:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2277:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_next(dp, 0); /* Next entry */ +2278:Middlewares/Third_Party/FatFs/src/ff.c **** } while (res == FR_OK); +2279:Middlewares/Third_Party/FatFs/src/ff.c **** +2280:Middlewares/Third_Party/FatFs/src/ff.c **** return res; +2281:Middlewares/Third_Party/FatFs/src/ff.c **** } +2282:Middlewares/Third_Party/FatFs/src/ff.c **** +2283:Middlewares/Third_Party/FatFs/src/ff.c **** +2284:Middlewares/Third_Party/FatFs/src/ff.c **** +2285:Middlewares/Third_Party/FatFs/src/ff.c **** +2286:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +2287:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2288:Middlewares/Third_Party/FatFs/src/ff.c **** /* Register an object to the directory */ +2289:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2290:Middlewares/Third_Party/FatFs/src/ff.c **** +2291:Middlewares/Third_Party/FatFs/src/ff.c **** static +2292:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT dir_register ( /* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DI +2293:Middlewares/Third_Party/FatFs/src/ff.c **** DIR* dp /* Target directory with object name to be created */ +2294:Middlewares/Third_Party/FatFs/src/ff.c **** ) +2295:Middlewares/Third_Party/FatFs/src/ff.c **** { + ARM GAS /tmp/cc2SVLkL.s page 62 + + +2296:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +2297:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = dp->obj.fs; +2298:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 /* LFN configuration */ +2299:Middlewares/Third_Party/FatFs/src/ff.c **** UINT n, nlen, nent; +2300:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE sn[12], sum; +2301:Middlewares/Third_Party/FatFs/src/ff.c **** +2302:Middlewares/Third_Party/FatFs/src/ff.c **** +2303:Middlewares/Third_Party/FatFs/src/ff.c **** if (dp->fn[NSFLAG] & (NS_DOT | NS_NONAME)) return FR_INVALID_NAME; /* Check name validity */ +2304:Middlewares/Third_Party/FatFs/src/ff.c **** for (nlen = 0; fs->lfnbuf[nlen]; nlen++) ; /* Get lfn length */ +2305:Middlewares/Third_Party/FatFs/src/ff.c **** +2306:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +2307:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ +2308:Middlewares/Third_Party/FatFs/src/ff.c **** DIR dj; +2309:Middlewares/Third_Party/FatFs/src/ff.c **** +2310:Middlewares/Third_Party/FatFs/src/ff.c **** nent = (nlen + 14) / 15 + 2; /* Number of entries to allocate (85+C0+C1s) */ +2311:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_alloc(dp, nent); /* Allocate entries */ +2312:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; +2313:Middlewares/Third_Party/FatFs/src/ff.c **** dp->blk_ofs = dp->dptr - SZDIRE * (nent - 1); /* Set the allocated entry block offset */ +2314:Middlewares/Third_Party/FatFs/src/ff.c **** +2315:Middlewares/Third_Party/FatFs/src/ff.c **** if (dp->obj.sclust != 0 && (dp->obj.stat & 4)) { /* Has the sub-directory been stretched? */ +2316:Middlewares/Third_Party/FatFs/src/ff.c **** dp->obj.objsize += (DWORD)fs->csize * SS(fs); /* Increase the directory size by cluster size */ +2317:Middlewares/Third_Party/FatFs/src/ff.c **** res = fill_first_frag(&dp->obj); /* Fill first fragment on the FAT if needed */ +2318:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; +2319:Middlewares/Third_Party/FatFs/src/ff.c **** res = fill_last_frag(&dp->obj, dp->clust, 0xFFFFFFFF); /* Fill last fragment on the FAT if neede +2320:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; +2321:Middlewares/Third_Party/FatFs/src/ff.c **** res = load_obj_dir(&dj, &dp->obj); /* Load the object status */ +2322:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; +2323:Middlewares/Third_Party/FatFs/src/ff.c **** st_qword(fs->dirbuf + XDIR_FileSize, dp->obj.objsize); /* Update the allocation status */ +2324:Middlewares/Third_Party/FatFs/src/ff.c **** st_qword(fs->dirbuf + XDIR_ValidFileSize, dp->obj.objsize); +2325:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbuf[XDIR_GenFlags] = dp->obj.stat | 1; +2326:Middlewares/Third_Party/FatFs/src/ff.c **** res = store_xdir(&dj); /* Store the object status */ +2327:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; +2328:Middlewares/Third_Party/FatFs/src/ff.c **** } +2329:Middlewares/Third_Party/FatFs/src/ff.c **** +2330:Middlewares/Third_Party/FatFs/src/ff.c **** create_xdir(fs->dirbuf, fs->lfnbuf); /* Create on-memory directory block to be written later */ +2331:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_OK; +2332:Middlewares/Third_Party/FatFs/src/ff.c **** } +2333:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2334:Middlewares/Third_Party/FatFs/src/ff.c **** /* On the FAT12/16/32 volume */ +2335:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(sn, dp->fn, 12); +2336:Middlewares/Third_Party/FatFs/src/ff.c **** if (sn[NSFLAG] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */ +2337:Middlewares/Third_Party/FatFs/src/ff.c **** dp->fn[NSFLAG] = NS_NOLFN; /* Find only SFN */ +2338:Middlewares/Third_Party/FatFs/src/ff.c **** for (n = 1; n < 100; n++) { +2339:Middlewares/Third_Party/FatFs/src/ff.c **** gen_numname(dp->fn, sn, fs->lfnbuf, n); /* Generate a numbered name */ +2340:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_find(dp); /* Check if the name collides with existing SFN */ +2341:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +2342:Middlewares/Third_Party/FatFs/src/ff.c **** } +2343:Middlewares/Third_Party/FatFs/src/ff.c **** if (n == 100) return FR_DENIED; /* Abort if too many collisions */ +2344:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ +2345:Middlewares/Third_Party/FatFs/src/ff.c **** dp->fn[NSFLAG] = sn[NSFLAG]; +2346:Middlewares/Third_Party/FatFs/src/ff.c **** } +2347:Middlewares/Third_Party/FatFs/src/ff.c **** +2348:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create an SFN with/without LFNs. */ +2349:Middlewares/Third_Party/FatFs/src/ff.c **** nent = (sn[NSFLAG] & NS_LFN) ? (nlen + 12) / 13 + 1 : 1; /* Number of entries to allocate */ +2350:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_alloc(dp, nent); /* Allocate entries */ +2351:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && --nent) { /* Set LFN entry if needed */ +2352:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(dp, dp->dptr - nent * SZDIRE); + ARM GAS /tmp/cc2SVLkL.s page 63 + + +2353:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +2354:Middlewares/Third_Party/FatFs/src/ff.c **** sum = sum_sfn(dp->fn); /* Checksum value of the SFN tied to the LFN */ +2355:Middlewares/Third_Party/FatFs/src/ff.c **** do { /* Store LFN entries in bottom first */ +2356:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dp->sect); +2357:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +2358:Middlewares/Third_Party/FatFs/src/ff.c **** put_lfn(fs->lfnbuf, dp->dir, (BYTE)nent, sum); +2359:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +2360:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_next(dp, 0); /* Next entry */ +2361:Middlewares/Third_Party/FatFs/src/ff.c **** } while (res == FR_OK && --nent); +2362:Middlewares/Third_Party/FatFs/src/ff.c **** } +2363:Middlewares/Third_Party/FatFs/src/ff.c **** } +2364:Middlewares/Third_Party/FatFs/src/ff.c **** +2365:Middlewares/Third_Party/FatFs/src/ff.c **** #else /* Non LFN configuration */ +2366:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_alloc(dp, 1); /* Allocate an entry for SFN */ +2367:Middlewares/Third_Party/FatFs/src/ff.c **** +2368:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2369:Middlewares/Third_Party/FatFs/src/ff.c **** +2370:Middlewares/Third_Party/FatFs/src/ff.c **** /* Set SFN entry */ +2371:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +2372:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dp->sect); +2373:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +2374:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(dp->dir, 0, SZDIRE); /* Clean the entry */ +2375:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(dp->dir + DIR_Name, dp->fn, 11); /* Put SFN */ +2376:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 +2377:Middlewares/Third_Party/FatFs/src/ff.c **** dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT); /* Put NT flag */ +2378:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2379:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +2380:Middlewares/Third_Party/FatFs/src/ff.c **** } +2381:Middlewares/Third_Party/FatFs/src/ff.c **** } +2382:Middlewares/Third_Party/FatFs/src/ff.c **** +2383:Middlewares/Third_Party/FatFs/src/ff.c **** return res; +2384:Middlewares/Third_Party/FatFs/src/ff.c **** } +2385:Middlewares/Third_Party/FatFs/src/ff.c **** +2386:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* !_FS_READONLY */ +2387:Middlewares/Third_Party/FatFs/src/ff.c **** +2388:Middlewares/Third_Party/FatFs/src/ff.c **** +2389:Middlewares/Third_Party/FatFs/src/ff.c **** +2390:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE == 0 +2391:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2392:Middlewares/Third_Party/FatFs/src/ff.c **** /* Remove an object from the directory */ +2393:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2394:Middlewares/Third_Party/FatFs/src/ff.c **** +2395:Middlewares/Third_Party/FatFs/src/ff.c **** static +2396:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT dir_remove ( /* FR_OK:Succeeded, FR_DISK_ERR:A disk error */ +2397:Middlewares/Third_Party/FatFs/src/ff.c **** DIR* dp /* Directory object pointing the entry to be removed */ +2398:Middlewares/Third_Party/FatFs/src/ff.c **** ) +2399:Middlewares/Third_Party/FatFs/src/ff.c **** { +2400:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +2401:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = dp->obj.fs; +2402:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 /* LFN configuration */ +2403:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD last = dp->dptr; +2404:Middlewares/Third_Party/FatFs/src/ff.c **** +2405:Middlewares/Third_Party/FatFs/src/ff.c **** res = (dp->blk_ofs == 0xFFFFFFFF) ? FR_OK : dir_sdi(dp, dp->blk_ofs); /* Goto top of the entry blo +2406:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +2407:Middlewares/Third_Party/FatFs/src/ff.c **** do { +2408:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dp->sect); +2409:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + ARM GAS /tmp/cc2SVLkL.s page 64 + + +2410:Middlewares/Third_Party/FatFs/src/ff.c **** /* Mark an entry 'deleted' */ +2411:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_EXFAT && fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ +2412:Middlewares/Third_Party/FatFs/src/ff.c **** dp->dir[XDIR_Type] &= 0x7F; +2413:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* On the FAT12/16/32 volume */ +2414:Middlewares/Third_Party/FatFs/src/ff.c **** dp->dir[DIR_Name] = DDEM; +2415:Middlewares/Third_Party/FatFs/src/ff.c **** } +2416:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +2417:Middlewares/Third_Party/FatFs/src/ff.c **** if (dp->dptr >= last) break; /* If reached last entry then all entries of the object has been de +2418:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_next(dp, 0); /* Next entry */ +2419:Middlewares/Third_Party/FatFs/src/ff.c **** } while (res == FR_OK); +2420:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) res = FR_INT_ERR; +2421:Middlewares/Third_Party/FatFs/src/ff.c **** } +2422:Middlewares/Third_Party/FatFs/src/ff.c **** #else /* Non LFN configuration */ +2423:Middlewares/Third_Party/FatFs/src/ff.c **** +2424:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dp->sect); +2425:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +2426:Middlewares/Third_Party/FatFs/src/ff.c **** dp->dir[DIR_Name] = DDEM; +2427:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +2428:Middlewares/Third_Party/FatFs/src/ff.c **** } +2429:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2430:Middlewares/Third_Party/FatFs/src/ff.c **** +2431:Middlewares/Third_Party/FatFs/src/ff.c **** return res; +2432:Middlewares/Third_Party/FatFs/src/ff.c **** } +2433:Middlewares/Third_Party/FatFs/src/ff.c **** +2434:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* !_FS_READONLY && _FS_MINIMIZE == 0 */ +2435:Middlewares/Third_Party/FatFs/src/ff.c **** +2436:Middlewares/Third_Party/FatFs/src/ff.c **** +2437:Middlewares/Third_Party/FatFs/src/ff.c **** +2438:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 +2439:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2440:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get file information from directory entry */ +2441:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2442:Middlewares/Third_Party/FatFs/src/ff.c **** +2443:Middlewares/Third_Party/FatFs/src/ff.c **** static +2444:Middlewares/Third_Party/FatFs/src/ff.c **** void get_fileinfo ( /* No return code */ +2445:Middlewares/Third_Party/FatFs/src/ff.c **** DIR* dp, /* Pointer to the directory object */ +2446:Middlewares/Third_Party/FatFs/src/ff.c **** FILINFO* fno /* Pointer to the file information to be filled */ +2447:Middlewares/Third_Party/FatFs/src/ff.c **** ) +2448:Middlewares/Third_Party/FatFs/src/ff.c **** { + 1138 .loc 1 2448 1 is_stmt 1 view -0 + 1139 .cfi_startproc + 1140 @ args = 0, pretend = 0, frame = 0 + 1141 @ frame_needed = 0, uses_anonymous_args = 0 + 1142 .loc 1 2448 1 is_stmt 0 view .LVU323 + 1143 0000 38B5 push {r3, r4, r5, lr} + 1144 .LCFI12: + 1145 .cfi_def_cfa_offset 16 + 1146 .cfi_offset 3, -16 + 1147 .cfi_offset 4, -12 + 1148 .cfi_offset 5, -8 + 1149 .cfi_offset 14, -4 +2449:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i, j; + 1150 .loc 1 2449 2 is_stmt 1 view .LVU324 +2450:Middlewares/Third_Party/FatFs/src/ff.c **** TCHAR c; + 1151 .loc 1 2450 2 view .LVU325 +2451:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD tm; + 1152 .loc 1 2451 2 view .LVU326 + ARM GAS /tmp/cc2SVLkL.s page 65 + + +2452:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 +2453:Middlewares/Third_Party/FatFs/src/ff.c **** WCHAR w, lfv; +2454:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = dp->obj.fs; +2455:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2456:Middlewares/Third_Party/FatFs/src/ff.c **** +2457:Middlewares/Third_Party/FatFs/src/ff.c **** +2458:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fname[0] = 0; /* Invaidate file info */ + 1153 .loc 1 2458 2 view .LVU327 + 1154 .loc 1 2458 16 is_stmt 0 view .LVU328 + 1155 0002 0023 movs r3, #0 + 1156 0004 4B72 strb r3, [r1, #9] +2459:Middlewares/Third_Party/FatFs/src/ff.c **** if (!dp->sect) return; /* Exit if read pointer has reached end of directory */ + 1157 .loc 1 2459 2 is_stmt 1 view .LVU329 + 1158 .loc 1 2459 9 is_stmt 0 view .LVU330 + 1159 0006 C369 ldr r3, [r0, #28] + 1160 .loc 1 2459 5 view .LVU331 + 1161 0008 73B3 cbz r3, .L99 + 1162 000a 0546 mov r5, r0 + 1163 000c 0C46 mov r4, r1 +2460:Middlewares/Third_Party/FatFs/src/ff.c **** +2461:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 /* LFN configuration */ +2462:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +2463:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ +2464:Middlewares/Third_Party/FatFs/src/ff.c **** get_xdir_info(fs->dirbuf, fno); +2465:Middlewares/Third_Party/FatFs/src/ff.c **** return; +2466:Middlewares/Third_Party/FatFs/src/ff.c **** } else +2467:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2468:Middlewares/Third_Party/FatFs/src/ff.c **** { /* On the FAT12/16/32 volume */ +2469:Middlewares/Third_Party/FatFs/src/ff.c **** if (dp->blk_ofs != 0xFFFFFFFF) { /* Get LFN if available */ +2470:Middlewares/Third_Party/FatFs/src/ff.c **** i = j = 0; +2471:Middlewares/Third_Party/FatFs/src/ff.c **** while ((w = fs->lfnbuf[j++]) != 0) { /* Get an LFN character */ +2472:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_LFN_UNICODE +2473:Middlewares/Third_Party/FatFs/src/ff.c **** w = ff_convert(w, 0); /* Unicode -> OEM */ +2474:Middlewares/Third_Party/FatFs/src/ff.c **** if (w == 0) { i = 0; break; } /* No LFN if it could not be converted */ +2475:Middlewares/Third_Party/FatFs/src/ff.c **** if (_DF1S && w >= 0x100) { /* Put 1st byte if it is a DBC (always false at SBCS cfg) */ +2476:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fname[i++] = (char)(w >> 8); +2477:Middlewares/Third_Party/FatFs/src/ff.c **** } +2478:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2479:Middlewares/Third_Party/FatFs/src/ff.c **** if (i >= _MAX_LFN) { i = 0; break; } /* No LFN if buffer overflow */ +2480:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fname[i++] = (TCHAR)w; +2481:Middlewares/Third_Party/FatFs/src/ff.c **** } +2482:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fname[i] = 0; /* Terminate the LFN */ +2483:Middlewares/Third_Party/FatFs/src/ff.c **** } +2484:Middlewares/Third_Party/FatFs/src/ff.c **** } +2485:Middlewares/Third_Party/FatFs/src/ff.c **** +2486:Middlewares/Third_Party/FatFs/src/ff.c **** i = j = 0; +2487:Middlewares/Third_Party/FatFs/src/ff.c **** lfv = fno->fname[i]; /* LFN is exist if non-zero */ +2488:Middlewares/Third_Party/FatFs/src/ff.c **** while (i < 11) { /* Copy name body and extension */ +2489:Middlewares/Third_Party/FatFs/src/ff.c **** c = (TCHAR)dp->dir[i++]; +2490:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == ' ') continue; /* Skip padding spaces */ +2491:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == RDDEM) c = (TCHAR)DDEM; /* Restore replaced DDEM character */ +2492:Middlewares/Third_Party/FatFs/src/ff.c **** if (i == 9) { /* Insert a . if extension is exist */ +2493:Middlewares/Third_Party/FatFs/src/ff.c **** if (!lfv) fno->fname[j] = '.'; +2494:Middlewares/Third_Party/FatFs/src/ff.c **** fno->altname[j++] = '.'; +2495:Middlewares/Third_Party/FatFs/src/ff.c **** } +2496:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE +2497:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsDBCS1(c) && i != 8 && i != 11 && IsDBCS2(dp->dir[i])) { + ARM GAS /tmp/cc2SVLkL.s page 66 + + +2498:Middlewares/Third_Party/FatFs/src/ff.c **** c = c << 8 | dp->dir[i++]; +2499:Middlewares/Third_Party/FatFs/src/ff.c **** } +2500:Middlewares/Third_Party/FatFs/src/ff.c **** c = ff_convert(c, 1); /* OEM -> Unicode */ +2501:Middlewares/Third_Party/FatFs/src/ff.c **** if (!c) c = '?'; +2502:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2503:Middlewares/Third_Party/FatFs/src/ff.c **** fno->altname[j] = c; +2504:Middlewares/Third_Party/FatFs/src/ff.c **** if (!lfv) { +2505:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsUpper(c) && (dp->dir[DIR_NTres] & ((i >= 9) ? NS_EXT : NS_BODY))) { +2506:Middlewares/Third_Party/FatFs/src/ff.c **** c += 0x20; /* To lower */ +2507:Middlewares/Third_Party/FatFs/src/ff.c **** } +2508:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fname[j] = c; +2509:Middlewares/Third_Party/FatFs/src/ff.c **** } +2510:Middlewares/Third_Party/FatFs/src/ff.c **** j++; +2511:Middlewares/Third_Party/FatFs/src/ff.c **** } +2512:Middlewares/Third_Party/FatFs/src/ff.c **** if (!lfv) { +2513:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fname[j] = 0; +2514:Middlewares/Third_Party/FatFs/src/ff.c **** if (!dp->dir[DIR_NTres]) j = 0; /* Altname is no longer needed if neither LFN nor case info is ex +2515:Middlewares/Third_Party/FatFs/src/ff.c **** } +2516:Middlewares/Third_Party/FatFs/src/ff.c **** fno->altname[j] = 0; /* Terminate the SFN */ +2517:Middlewares/Third_Party/FatFs/src/ff.c **** +2518:Middlewares/Third_Party/FatFs/src/ff.c **** #else /* Non-LFN configuration */ +2519:Middlewares/Third_Party/FatFs/src/ff.c **** i = j = 0; + 1164 .loc 1 2519 8 view .LVU332 + 1165 000e 0022 movs r2, #0 + 1166 .loc 1 2519 4 view .LVU333 + 1167 0010 1346 mov r3, r2 + 1168 0012 06E0 b .L101 + 1169 .LVL116: + 1170 .L103: +2520:Middlewares/Third_Party/FatFs/src/ff.c **** while (i < 11) { /* Copy name body and extension */ +2521:Middlewares/Third_Party/FatFs/src/ff.c **** c = (TCHAR)dp->dir[i++]; +2522:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == ' ') continue; /* Skip padding spaces */ +2523:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == RDDEM) c = (TCHAR)DDEM; /* Restore replaced DDEM character */ +2524:Middlewares/Third_Party/FatFs/src/ff.c **** if (i == 9) fno->fname[j++] = '.'; /* Insert a . if extension is exist */ + 1171 .loc 1 2524 3 is_stmt 1 view .LVU334 + 1172 .loc 1 2524 6 is_stmt 0 view .LVU335 + 1173 0014 BCF1090F cmp ip, #9 + 1174 0018 0FD0 beq .L108 + 1175 .L104: +2525:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fname[j++] = c; + 1176 .loc 1 2525 3 is_stmt 1 view .LVU336 + 1177 .LVL117: + 1178 .loc 1 2525 19 is_stmt 0 view .LVU337 + 1179 001a A118 adds r1, r4, r2 + 1180 001c 4B72 strb r3, [r1, #9] + 1181 .loc 1 2525 15 view .LVU338 + 1182 001e 0132 adds r2, r2, #1 + 1183 .LVL118: + 1184 .L102: + 1185 .loc 1 2525 15 view .LVU339 + 1186 0020 6346 mov r3, ip + 1187 .LVL119: + 1188 .L101: +2520:Middlewares/Third_Party/FatFs/src/ff.c **** while (i < 11) { /* Copy name body and extension */ + 1189 .loc 1 2520 11 is_stmt 1 view .LVU340 + 1190 0022 0A2B cmp r3, #10 + 1191 0024 0ED8 bhi .L109 + ARM GAS /tmp/cc2SVLkL.s page 67 + + +2521:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == ' ') continue; /* Skip padding spaces */ + 1192 .loc 1 2521 3 view .LVU341 +2521:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == ' ') continue; /* Skip padding spaces */ + 1193 .loc 1 2521 23 is_stmt 0 view .LVU342 + 1194 0026 03F1010C add ip, r3, #1 + 1195 .LVL120: +2521:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == ' ') continue; /* Skip padding spaces */ + 1196 .loc 1 2521 5 view .LVU343 + 1197 002a 296A ldr r1, [r5, #32] + 1198 002c CB5C ldrb r3, [r1, r3] @ zero_extendqisi2 + 1199 .LVL121: +2522:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == RDDEM) c = (TCHAR)DDEM; /* Restore replaced DDEM character */ + 1200 .loc 1 2522 3 is_stmt 1 view .LVU344 +2522:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == RDDEM) c = (TCHAR)DDEM; /* Restore replaced DDEM character */ + 1201 .loc 1 2522 6 is_stmt 0 view .LVU345 + 1202 002e 202B cmp r3, #32 + 1203 0030 F6D0 beq .L102 +2523:Middlewares/Third_Party/FatFs/src/ff.c **** if (i == 9) fno->fname[j++] = '.'; /* Insert a . if extension is exist */ + 1204 .loc 1 2523 3 is_stmt 1 view .LVU346 +2523:Middlewares/Third_Party/FatFs/src/ff.c **** if (i == 9) fno->fname[j++] = '.'; /* Insert a . if extension is exist */ + 1205 .loc 1 2523 6 is_stmt 0 view .LVU347 + 1206 0032 052B cmp r3, #5 + 1207 0034 EED1 bne .L103 +2523:Middlewares/Third_Party/FatFs/src/ff.c **** if (i == 9) fno->fname[j++] = '.'; /* Insert a . if extension is exist */ + 1208 .loc 1 2523 21 discriminator 1 view .LVU348 + 1209 0036 E523 movs r3, #229 + 1210 .LVL122: +2523:Middlewares/Third_Party/FatFs/src/ff.c **** if (i == 9) fno->fname[j++] = '.'; /* Insert a . if extension is exist */ + 1211 .loc 1 2523 21 discriminator 1 view .LVU349 + 1212 0038 ECE7 b .L103 + 1213 .LVL123: + 1214 .L108: +2524:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fname[j++] = c; + 1215 .loc 1 2524 15 is_stmt 1 discriminator 1 view .LVU350 +2524:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fname[j++] = c; + 1216 .loc 1 2524 31 is_stmt 0 discriminator 1 view .LVU351 + 1217 003a A118 adds r1, r4, r2 + 1218 003c 2E20 movs r0, #46 + 1219 003e 4872 strb r0, [r1, #9] +2524:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fname[j++] = c; + 1220 .loc 1 2524 27 discriminator 1 view .LVU352 + 1221 0040 0132 adds r2, r2, #1 + 1222 .LVL124: +2524:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fname[j++] = c; + 1223 .loc 1 2524 27 discriminator 1 view .LVU353 + 1224 0042 EAE7 b .L104 + 1225 .LVL125: + 1226 .L109: +2526:Middlewares/Third_Party/FatFs/src/ff.c **** } +2527:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fname[j] = 0; + 1227 .loc 1 2527 2 is_stmt 1 view .LVU354 + 1228 .loc 1 2527 16 is_stmt 0 view .LVU355 + 1229 0044 2244 add r2, r2, r4 + 1230 .LVL126: + 1231 .loc 1 2527 16 view .LVU356 + 1232 0046 0023 movs r3, #0 + 1233 .LVL127: + ARM GAS /tmp/cc2SVLkL.s page 68 + + + 1234 .loc 1 2527 16 view .LVU357 + 1235 0048 5372 strb r3, [r2, #9] +2528:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2529:Middlewares/Third_Party/FatFs/src/ff.c **** +2530:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fattrib = dp->dir[DIR_Attr]; /* Attribute */ + 1236 .loc 1 2530 2 is_stmt 1 view .LVU358 + 1237 .loc 1 2530 19 is_stmt 0 view .LVU359 + 1238 004a 2B6A ldr r3, [r5, #32] + 1239 .loc 1 2530 15 view .LVU360 + 1240 004c DB7A ldrb r3, [r3, #11] @ zero_extendqisi2 + 1241 004e 2372 strb r3, [r4, #8] +2531:Middlewares/Third_Party/FatFs/src/ff.c **** fno->fsize = ld_dword(dp->dir + DIR_FileSize); /* Size */ + 1242 .loc 1 2531 2 is_stmt 1 view .LVU361 + 1243 .loc 1 2531 26 is_stmt 0 view .LVU362 + 1244 0050 286A ldr r0, [r5, #32] + 1245 .loc 1 2531 15 view .LVU363 + 1246 0052 1C30 adds r0, r0, #28 + 1247 0054 FFF7FEFF bl ld_dword + 1248 .LVL128: + 1249 .loc 1 2531 13 discriminator 1 view .LVU364 + 1250 0058 2060 str r0, [r4] +2532:Middlewares/Third_Party/FatFs/src/ff.c **** tm = ld_dword(dp->dir + DIR_ModTime); /* Timestamp */ + 1251 .loc 1 2532 2 is_stmt 1 view .LVU365 + 1252 .loc 1 2532 18 is_stmt 0 view .LVU366 + 1253 005a 286A ldr r0, [r5, #32] + 1254 .loc 1 2532 7 view .LVU367 + 1255 005c 1630 adds r0, r0, #22 + 1256 005e FFF7FEFF bl ld_dword + 1257 .LVL129: +2533:Middlewares/Third_Party/FatFs/src/ff.c **** fno->ftime = (WORD)tm; fno->fdate = (WORD)(tm >> 16); + 1258 .loc 1 2533 2 is_stmt 1 view .LVU368 + 1259 .loc 1 2533 13 is_stmt 0 view .LVU369 + 1260 0062 E080 strh r0, [r4, #6] @ movhi + 1261 .loc 1 2533 25 is_stmt 1 view .LVU370 + 1262 .loc 1 2533 38 is_stmt 0 view .LVU371 + 1263 0064 000C lsrs r0, r0, #16 + 1264 .LVL130: + 1265 .loc 1 2533 36 view .LVU372 + 1266 0066 A080 strh r0, [r4, #4] @ movhi + 1267 .LVL131: + 1268 .L99: +2534:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1269 .loc 1 2534 1 view .LVU373 + 1270 0068 38BD pop {r3, r4, r5, pc} + 1271 .cfi_endproc + 1272 .LFE1214: + 1274 .section .rodata.create_name.str1.4,"aMS",%progbits,1 + 1275 .align 2 + 1276 .LC0: + 1277 0000 222A2B2C .ascii "\"*+,:;<=>?[]|\177\000" + 1277 3A3B3C3D + 1277 3E3F5B5D + 1277 7C7F00 + 1278 .section .text.create_name,"ax",%progbits + 1279 .align 1 + 1280 .syntax unified + 1281 .thumb + ARM GAS /tmp/cc2SVLkL.s page 69 + + + 1282 .thumb_func + 1284 create_name: + 1285 .LVL132: + 1286 .LFB1215: +2535:Middlewares/Third_Party/FatFs/src/ff.c **** +2536:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 */ +2537:Middlewares/Third_Party/FatFs/src/ff.c **** +2538:Middlewares/Third_Party/FatFs/src/ff.c **** +2539:Middlewares/Third_Party/FatFs/src/ff.c **** +2540:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FIND && _FS_MINIMIZE <= 1 +2541:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2542:Middlewares/Third_Party/FatFs/src/ff.c **** /* Pattern matching */ +2543:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2544:Middlewares/Third_Party/FatFs/src/ff.c **** +2545:Middlewares/Third_Party/FatFs/src/ff.c **** static +2546:Middlewares/Third_Party/FatFs/src/ff.c **** WCHAR get_achar ( /* Get a character and advances ptr 1 or 2 */ +2547:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR** ptr /* Pointer to pointer to the SBCS/DBCS/Unicode string */ +2548:Middlewares/Third_Party/FatFs/src/ff.c **** ) +2549:Middlewares/Third_Party/FatFs/src/ff.c **** { +2550:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_LFN_UNICODE +2551:Middlewares/Third_Party/FatFs/src/ff.c **** WCHAR chr; +2552:Middlewares/Third_Party/FatFs/src/ff.c **** +2553:Middlewares/Third_Party/FatFs/src/ff.c **** chr = (BYTE)*(*ptr)++; /* Get a byte */ +2554:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsLower(chr)) chr -= 0x20; /* To upper ASCII char */ +2555:Middlewares/Third_Party/FatFs/src/ff.c **** #ifdef _EXCVT +2556:Middlewares/Third_Party/FatFs/src/ff.c **** if (chr >= 0x80) chr = ExCvt[chr - 0x80]; /* To upper SBCS extended char */ +2557:Middlewares/Third_Party/FatFs/src/ff.c **** #else +2558:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsDBCS1(chr) && IsDBCS2(**ptr)) { /* Get DBC 2nd byte if needed */ +2559:Middlewares/Third_Party/FatFs/src/ff.c **** chr = chr << 8 | (BYTE)*(*ptr)++; +2560:Middlewares/Third_Party/FatFs/src/ff.c **** } +2561:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2562:Middlewares/Third_Party/FatFs/src/ff.c **** return chr; +2563:Middlewares/Third_Party/FatFs/src/ff.c **** #else +2564:Middlewares/Third_Party/FatFs/src/ff.c **** return ff_wtoupper(*(*ptr)++); /* Get a word and to upper */ +2565:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2566:Middlewares/Third_Party/FatFs/src/ff.c **** } +2567:Middlewares/Third_Party/FatFs/src/ff.c **** +2568:Middlewares/Third_Party/FatFs/src/ff.c **** +2569:Middlewares/Third_Party/FatFs/src/ff.c **** static +2570:Middlewares/Third_Party/FatFs/src/ff.c **** int pattern_matching ( /* 0:not matched, 1:matched */ +2571:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* pat, /* Matching pattern */ +2572:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* nam, /* String to be tested */ +2573:Middlewares/Third_Party/FatFs/src/ff.c **** int skip, /* Number of pre-skip chars (number of ?s) */ +2574:Middlewares/Third_Party/FatFs/src/ff.c **** int inf /* Infinite search (* specified) */ +2575:Middlewares/Third_Party/FatFs/src/ff.c **** ) +2576:Middlewares/Third_Party/FatFs/src/ff.c **** { +2577:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR *pp, *np; +2578:Middlewares/Third_Party/FatFs/src/ff.c **** WCHAR pc, nc; +2579:Middlewares/Third_Party/FatFs/src/ff.c **** int nm, nx; +2580:Middlewares/Third_Party/FatFs/src/ff.c **** +2581:Middlewares/Third_Party/FatFs/src/ff.c **** +2582:Middlewares/Third_Party/FatFs/src/ff.c **** while (skip--) { /* Pre-skip name chars */ +2583:Middlewares/Third_Party/FatFs/src/ff.c **** if (!get_achar(&nam)) return 0; /* Branch mismatched if less name chars */ +2584:Middlewares/Third_Party/FatFs/src/ff.c **** } +2585:Middlewares/Third_Party/FatFs/src/ff.c **** if (!*pat && inf) return 1; /* (short circuit) */ +2586:Middlewares/Third_Party/FatFs/src/ff.c **** +2587:Middlewares/Third_Party/FatFs/src/ff.c **** do { + ARM GAS /tmp/cc2SVLkL.s page 70 + + +2588:Middlewares/Third_Party/FatFs/src/ff.c **** pp = pat; np = nam; /* Top of pattern and name to match */ +2589:Middlewares/Third_Party/FatFs/src/ff.c **** for (;;) { +2590:Middlewares/Third_Party/FatFs/src/ff.c **** if (*pp == '?' || *pp == '*') { /* Wildcard? */ +2591:Middlewares/Third_Party/FatFs/src/ff.c **** nm = nx = 0; +2592:Middlewares/Third_Party/FatFs/src/ff.c **** do { /* Analyze the wildcard chars */ +2593:Middlewares/Third_Party/FatFs/src/ff.c **** if (*pp++ == '?') nm++; else nx = 1; +2594:Middlewares/Third_Party/FatFs/src/ff.c **** } while (*pp == '?' || *pp == '*'); +2595:Middlewares/Third_Party/FatFs/src/ff.c **** if (pattern_matching(pp, np, nm, nx)) return 1; /* Test new branch (recurs upto number of wildc +2596:Middlewares/Third_Party/FatFs/src/ff.c **** nc = *np; break; /* Branch mismatched */ +2597:Middlewares/Third_Party/FatFs/src/ff.c **** } +2598:Middlewares/Third_Party/FatFs/src/ff.c **** pc = get_achar(&pp); /* Get a pattern char */ +2599:Middlewares/Third_Party/FatFs/src/ff.c **** nc = get_achar(&np); /* Get a name char */ +2600:Middlewares/Third_Party/FatFs/src/ff.c **** if (pc != nc) break; /* Branch mismatched? */ +2601:Middlewares/Third_Party/FatFs/src/ff.c **** if (pc == 0) return 1; /* Branch matched? (matched at end of both strings) */ +2602:Middlewares/Third_Party/FatFs/src/ff.c **** } +2603:Middlewares/Third_Party/FatFs/src/ff.c **** get_achar(&nam); /* nam++ */ +2604:Middlewares/Third_Party/FatFs/src/ff.c **** } while (inf && nc); /* Retry until end of name if infinite search is specified */ +2605:Middlewares/Third_Party/FatFs/src/ff.c **** +2606:Middlewares/Third_Party/FatFs/src/ff.c **** return 0; +2607:Middlewares/Third_Party/FatFs/src/ff.c **** } +2608:Middlewares/Third_Party/FatFs/src/ff.c **** +2609:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _USE_FIND && _FS_MINIMIZE <= 1 */ +2610:Middlewares/Third_Party/FatFs/src/ff.c **** +2611:Middlewares/Third_Party/FatFs/src/ff.c **** +2612:Middlewares/Third_Party/FatFs/src/ff.c **** +2613:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2614:Middlewares/Third_Party/FatFs/src/ff.c **** /* Pick a top segment and create the object name in directory form */ +2615:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2616:Middlewares/Third_Party/FatFs/src/ff.c **** +2617:Middlewares/Third_Party/FatFs/src/ff.c **** static +2618:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT create_name ( /* FR_OK: successful, FR_INVALID_NAME: could not create */ +2619:Middlewares/Third_Party/FatFs/src/ff.c **** DIR* dp, /* Pointer to the directory object */ +2620:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR** path /* Pointer to pointer to the segment in the path string */ +2621:Middlewares/Third_Party/FatFs/src/ff.c **** ) +2622:Middlewares/Third_Party/FatFs/src/ff.c **** { + 1287 .loc 1 2622 1 is_stmt 1 view -0 + 1288 .cfi_startproc + 1289 @ args = 0, pretend = 0, frame = 0 + 1290 @ frame_needed = 0, uses_anonymous_args = 0 + 1291 .loc 1 2622 1 is_stmt 0 view .LVU375 + 1292 0000 2DE9F84F push {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr} + 1293 .LCFI13: + 1294 .cfi_def_cfa_offset 40 + 1295 .cfi_offset 3, -40 + 1296 .cfi_offset 4, -36 + 1297 .cfi_offset 5, -32 + 1298 .cfi_offset 6, -28 + 1299 .cfi_offset 7, -24 + 1300 .cfi_offset 8, -20 + 1301 .cfi_offset 9, -16 + 1302 .cfi_offset 10, -12 + 1303 .cfi_offset 11, -8 + 1304 .cfi_offset 14, -4 + 1305 0004 8146 mov r9, r0 + 1306 0006 8A46 mov r10, r1 +2623:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 /* LFN configuration */ +2624:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE b, cf; + ARM GAS /tmp/cc2SVLkL.s page 71 + + +2625:Middlewares/Third_Party/FatFs/src/ff.c **** WCHAR w, *lfn; +2626:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i, ni, si, di; +2627:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR *p; +2628:Middlewares/Third_Party/FatFs/src/ff.c **** +2629:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create LFN in Unicode */ +2630:Middlewares/Third_Party/FatFs/src/ff.c **** p = *path; lfn = dp->obj.fs->lfnbuf; si = di = 0; +2631:Middlewares/Third_Party/FatFs/src/ff.c **** for (;;) { +2632:Middlewares/Third_Party/FatFs/src/ff.c **** w = p[si++]; /* Get a character */ +2633:Middlewares/Third_Party/FatFs/src/ff.c **** if (w < ' ') break; /* Break if end of the path name */ +2634:Middlewares/Third_Party/FatFs/src/ff.c **** if (w == '/' || w == '\\') { /* Break if a separator is found */ +2635:Middlewares/Third_Party/FatFs/src/ff.c **** while (p[si] == '/' || p[si] == '\\') si++; /* Skip duplicated separator if exist */ +2636:Middlewares/Third_Party/FatFs/src/ff.c **** break; +2637:Middlewares/Third_Party/FatFs/src/ff.c **** } +2638:Middlewares/Third_Party/FatFs/src/ff.c **** if (di >= _MAX_LFN) return FR_INVALID_NAME; /* Reject too long name */ +2639:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_LFN_UNICODE +2640:Middlewares/Third_Party/FatFs/src/ff.c **** w &= 0xFF; +2641:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsDBCS1(w)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ +2642:Middlewares/Third_Party/FatFs/src/ff.c **** b = (BYTE)p[si++]; /* Get 2nd byte */ +2643:Middlewares/Third_Party/FatFs/src/ff.c **** w = (w << 8) + b; /* Create a DBC */ +2644:Middlewares/Third_Party/FatFs/src/ff.c **** if (!IsDBCS2(b)) return FR_INVALID_NAME; /* Reject invalid sequence */ +2645:Middlewares/Third_Party/FatFs/src/ff.c **** } +2646:Middlewares/Third_Party/FatFs/src/ff.c **** w = ff_convert(w, 1); /* Convert ANSI/OEM to Unicode */ +2647:Middlewares/Third_Party/FatFs/src/ff.c **** if (!w) return FR_INVALID_NAME; /* Reject invalid code */ +2648:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2649:Middlewares/Third_Party/FatFs/src/ff.c **** if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) return FR_INVALID_NAME; /* Reject illegal characters +2650:Middlewares/Third_Party/FatFs/src/ff.c **** lfn[di++] = w; /* Store the Unicode character */ +2651:Middlewares/Third_Party/FatFs/src/ff.c **** } +2652:Middlewares/Third_Party/FatFs/src/ff.c **** *path = &p[si]; /* Return pointer to the next segment */ +2653:Middlewares/Third_Party/FatFs/src/ff.c **** cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */ +2654:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0 +2655:Middlewares/Third_Party/FatFs/src/ff.c **** if ((di == 1 && lfn[di - 1] == '.') || +2656:Middlewares/Third_Party/FatFs/src/ff.c **** (di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) { /* Is this segment a dot name? */ +2657:Middlewares/Third_Party/FatFs/src/ff.c **** lfn[di] = 0; +2658:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < 11; i++) /* Create dot name for SFN entry */ +2659:Middlewares/Third_Party/FatFs/src/ff.c **** dp->fn[i] = (i < di) ? '.' : ' '; +2660:Middlewares/Third_Party/FatFs/src/ff.c **** dp->fn[i] = cf | NS_DOT; /* This is a dot entry */ +2661:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_OK; +2662:Middlewares/Third_Party/FatFs/src/ff.c **** } +2663:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2664:Middlewares/Third_Party/FatFs/src/ff.c **** while (di) { /* Snip off trailing spaces and dots if exist */ +2665:Middlewares/Third_Party/FatFs/src/ff.c **** w = lfn[di - 1]; +2666:Middlewares/Third_Party/FatFs/src/ff.c **** if (w != ' ' && w != '.') break; +2667:Middlewares/Third_Party/FatFs/src/ff.c **** di--; +2668:Middlewares/Third_Party/FatFs/src/ff.c **** } +2669:Middlewares/Third_Party/FatFs/src/ff.c **** lfn[di] = 0; /* LFN is created */ +2670:Middlewares/Third_Party/FatFs/src/ff.c **** if (di == 0) return FR_INVALID_NAME; /* Reject nul name */ +2671:Middlewares/Third_Party/FatFs/src/ff.c **** +2672:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create SFN in directory form */ +2673:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(dp->fn, ' ', 11); +2674:Middlewares/Third_Party/FatFs/src/ff.c **** for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */ +2675:Middlewares/Third_Party/FatFs/src/ff.c **** if (si) cf |= NS_LOSS | NS_LFN; +2676:Middlewares/Third_Party/FatFs/src/ff.c **** while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */ +2677:Middlewares/Third_Party/FatFs/src/ff.c **** +2678:Middlewares/Third_Party/FatFs/src/ff.c **** i = b = 0; ni = 8; +2679:Middlewares/Third_Party/FatFs/src/ff.c **** for (;;) { +2680:Middlewares/Third_Party/FatFs/src/ff.c **** w = lfn[si++]; /* Get an LFN character */ +2681:Middlewares/Third_Party/FatFs/src/ff.c **** if (!w) break; /* Break on end of the LFN */ + ARM GAS /tmp/cc2SVLkL.s page 72 + + +2682:Middlewares/Third_Party/FatFs/src/ff.c **** if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */ +2683:Middlewares/Third_Party/FatFs/src/ff.c **** cf |= NS_LOSS | NS_LFN; continue; +2684:Middlewares/Third_Party/FatFs/src/ff.c **** } +2685:Middlewares/Third_Party/FatFs/src/ff.c **** +2686:Middlewares/Third_Party/FatFs/src/ff.c **** if (i >= ni || si == di) { /* Extension or end of SFN */ +2687:Middlewares/Third_Party/FatFs/src/ff.c **** if (ni == 11) { /* Long extension */ +2688:Middlewares/Third_Party/FatFs/src/ff.c **** cf |= NS_LOSS | NS_LFN; break; +2689:Middlewares/Third_Party/FatFs/src/ff.c **** } +2690:Middlewares/Third_Party/FatFs/src/ff.c **** if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */ +2691:Middlewares/Third_Party/FatFs/src/ff.c **** if (si > di) break; /* No extension */ +2692:Middlewares/Third_Party/FatFs/src/ff.c **** si = di; i = 8; ni = 11; /* Enter extension section */ +2693:Middlewares/Third_Party/FatFs/src/ff.c **** b <<= 2; continue; +2694:Middlewares/Third_Party/FatFs/src/ff.c **** } +2695:Middlewares/Third_Party/FatFs/src/ff.c **** +2696:Middlewares/Third_Party/FatFs/src/ff.c **** if (w >= 0x80) { /* Non ASCII character */ +2697:Middlewares/Third_Party/FatFs/src/ff.c **** #ifdef _EXCVT +2698:Middlewares/Third_Party/FatFs/src/ff.c **** w = ff_convert(w, 0); /* Unicode -> OEM code */ +2699:Middlewares/Third_Party/FatFs/src/ff.c **** if (w) w = ExCvt[w - 0x80]; /* Convert extended character to upper (SBCS) */ +2700:Middlewares/Third_Party/FatFs/src/ff.c **** #else +2701:Middlewares/Third_Party/FatFs/src/ff.c **** w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */ +2702:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2703:Middlewares/Third_Party/FatFs/src/ff.c **** cf |= NS_LFN; /* Force create LFN entry */ +2704:Middlewares/Third_Party/FatFs/src/ff.c **** } +2705:Middlewares/Third_Party/FatFs/src/ff.c **** +2706:Middlewares/Third_Party/FatFs/src/ff.c **** if (_DF1S && w >= 0x100) { /* Is this DBC? (always false at SBCS cfg) */ +2707:Middlewares/Third_Party/FatFs/src/ff.c **** if (i >= ni - 1) { +2708:Middlewares/Third_Party/FatFs/src/ff.c **** cf |= NS_LOSS | NS_LFN; i = ni; continue; +2709:Middlewares/Third_Party/FatFs/src/ff.c **** } +2710:Middlewares/Third_Party/FatFs/src/ff.c **** dp->fn[i++] = (BYTE)(w >> 8); +2711:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* SBC */ +2712:Middlewares/Third_Party/FatFs/src/ff.c **** if (!w || chk_chr("+,;=[]", w)) { /* Replace illegal characters for SFN */ +2713:Middlewares/Third_Party/FatFs/src/ff.c **** w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ +2714:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +2715:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsUpper(w)) { /* ASCII large capital */ +2716:Middlewares/Third_Party/FatFs/src/ff.c **** b |= 2; +2717:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +2718:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsLower(w)) { /* ASCII small capital */ +2719:Middlewares/Third_Party/FatFs/src/ff.c **** b |= 1; w -= 0x20; +2720:Middlewares/Third_Party/FatFs/src/ff.c **** } +2721:Middlewares/Third_Party/FatFs/src/ff.c **** } +2722:Middlewares/Third_Party/FatFs/src/ff.c **** } +2723:Middlewares/Third_Party/FatFs/src/ff.c **** } +2724:Middlewares/Third_Party/FatFs/src/ff.c **** dp->fn[i++] = (BYTE)w; +2725:Middlewares/Third_Party/FatFs/src/ff.c **** } +2726:Middlewares/Third_Party/FatFs/src/ff.c **** +2727:Middlewares/Third_Party/FatFs/src/ff.c **** if (dp->fn[0] == DDEM) dp->fn[0] = RDDEM; /* If the first character collides with DDEM, replace it +2728:Middlewares/Third_Party/FatFs/src/ff.c **** +2729:Middlewares/Third_Party/FatFs/src/ff.c **** if (ni == 8) b <<= 2; +2730:Middlewares/Third_Party/FatFs/src/ff.c **** if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) cf |= NS_LFN; /* Create LFN entry when there are com +2731:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended character, NT flags are c +2732:Middlewares/Third_Party/FatFs/src/ff.c **** if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */ +2733:Middlewares/Third_Party/FatFs/src/ff.c **** if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */ +2734:Middlewares/Third_Party/FatFs/src/ff.c **** } +2735:Middlewares/Third_Party/FatFs/src/ff.c **** +2736:Middlewares/Third_Party/FatFs/src/ff.c **** dp->fn[NSFLAG] = cf; /* SFN is created */ +2737:Middlewares/Third_Party/FatFs/src/ff.c **** +2738:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_OK; + ARM GAS /tmp/cc2SVLkL.s page 73 + + +2739:Middlewares/Third_Party/FatFs/src/ff.c **** +2740:Middlewares/Third_Party/FatFs/src/ff.c **** +2741:Middlewares/Third_Party/FatFs/src/ff.c **** #else /* _USE_LFN != 0 : Non-LFN configuration */ +2742:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE c, d, *sfn; + 1307 .loc 1 2742 2 is_stmt 1 view .LVU376 +2743:Middlewares/Third_Party/FatFs/src/ff.c **** UINT ni, si, i; + 1308 .loc 1 2743 2 view .LVU377 +2744:Middlewares/Third_Party/FatFs/src/ff.c **** const char *p; + 1309 .loc 1 2744 2 view .LVU378 +2745:Middlewares/Third_Party/FatFs/src/ff.c **** +2746:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create file name in directory form */ +2747:Middlewares/Third_Party/FatFs/src/ff.c **** p = *path; sfn = dp->fn; + 1310 .loc 1 2747 2 view .LVU379 + 1311 .loc 1 2747 4 is_stmt 0 view .LVU380 + 1312 0008 D1F80080 ldr r8, [r1] + 1313 .LVL133: + 1314 .loc 1 2747 13 is_stmt 1 view .LVU381 + 1315 .loc 1 2747 17 is_stmt 0 view .LVU382 + 1316 000c 00F1240B add fp, r0, #36 + 1317 .LVL134: +2748:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(sfn, ' ', 11); + 1318 .loc 1 2748 2 is_stmt 1 view .LVU383 + 1319 0010 0B22 movs r2, #11 + 1320 0012 2021 movs r1, #32 + 1321 .LVL135: + 1322 .loc 1 2748 2 is_stmt 0 view .LVU384 + 1323 0014 5846 mov r0, fp + 1324 .LVL136: + 1325 .loc 1 2748 2 view .LVU385 + 1326 0016 FFF7FEFF bl mem_set + 1327 .LVL137: +2749:Middlewares/Third_Party/FatFs/src/ff.c **** si = i = 0; ni = 8; + 1328 .loc 1 2749 2 is_stmt 1 view .LVU386 + 1329 .loc 1 2749 14 view .LVU387 + 1330 .loc 1 2749 9 is_stmt 0 view .LVU388 + 1331 001a 0025 movs r5, #0 + 1332 .loc 1 2749 5 view .LVU389 + 1333 001c 2B46 mov r3, r5 + 1334 .loc 1 2749 17 view .LVU390 + 1335 001e 0827 movs r7, #8 + 1336 0020 29E0 b .L111 + 1337 .LVL138: + 1338 .L115: +2750:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0 +2751:Middlewares/Third_Party/FatFs/src/ff.c **** if (p[si] == '.') { /* Is this a dot entry? */ +2752:Middlewares/Third_Party/FatFs/src/ff.c **** for (;;) { +2753:Middlewares/Third_Party/FatFs/src/ff.c **** c = (BYTE)p[si++]; +2754:Middlewares/Third_Party/FatFs/src/ff.c **** if (c != '.' || si >= 3) break; +2755:Middlewares/Third_Party/FatFs/src/ff.c **** sfn[i++] = c; +2756:Middlewares/Third_Party/FatFs/src/ff.c **** } +2757:Middlewares/Third_Party/FatFs/src/ff.c **** if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME; +2758:Middlewares/Third_Party/FatFs/src/ff.c **** *path = p + si; /* Return pointer to the next segment */ +2759:Middlewares/Third_Party/FatFs/src/ff.c **** sfn[NSFLAG] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of the path +2760:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_OK; +2761:Middlewares/Third_Party/FatFs/src/ff.c **** } +2762:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2763:Middlewares/Third_Party/FatFs/src/ff.c **** for (;;) { + ARM GAS /tmp/cc2SVLkL.s page 74 + + +2764:Middlewares/Third_Party/FatFs/src/ff.c **** c = (BYTE)p[si++]; +2765:Middlewares/Third_Party/FatFs/src/ff.c **** if (c <= ' ') break; /* Break if end of the path name */ +2766:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == '/' || c == '\\') { /* Break if a separator is found */ +2767:Middlewares/Third_Party/FatFs/src/ff.c **** while (p[si] == '/' || p[si] == '\\') si++; /* Skip duplicated separator if exist */ + 1339 .loc 1 2767 42 is_stmt 1 discriminator 2 view .LVU391 + 1340 .loc 1 2767 44 is_stmt 0 discriminator 2 view .LVU392 + 1341 0022 0136 adds r6, r6, #1 + 1342 .LVL139: + 1343 .L113: + 1344 .loc 1 2767 24 is_stmt 1 discriminator 1 view .LVU393 + 1345 .loc 1 2767 12 is_stmt 0 discriminator 1 view .LVU394 + 1346 0024 18F80630 ldrb r3, [r8, r6] @ zero_extendqisi2 + 1347 .loc 1 2767 24 discriminator 1 view .LVU395 + 1348 0028 2F2B cmp r3, #47 + 1349 002a FAD0 beq .L115 + 1350 .loc 1 2767 24 discriminator 1 view .LVU396 + 1351 002c 5C2B cmp r3, #92 + 1352 002e F8D0 beq .L115 + 1353 .L112: +2768:Middlewares/Third_Party/FatFs/src/ff.c **** break; +2769:Middlewares/Third_Party/FatFs/src/ff.c **** } +2770:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == '.' || i >= ni) { /* End of body or over size? */ +2771:Middlewares/Third_Party/FatFs/src/ff.c **** if (ni == 11 || c != '.') return FR_INVALID_NAME; /* Over size or invalid dot */ +2772:Middlewares/Third_Party/FatFs/src/ff.c **** i = 8; ni = 11; /* Goto extension */ +2773:Middlewares/Third_Party/FatFs/src/ff.c **** continue; +2774:Middlewares/Third_Party/FatFs/src/ff.c **** } +2775:Middlewares/Third_Party/FatFs/src/ff.c **** if (c >= 0x80) { /* Extended character? */ +2776:Middlewares/Third_Party/FatFs/src/ff.c **** #ifdef _EXCVT +2777:Middlewares/Third_Party/FatFs/src/ff.c **** c = ExCvt[c - 0x80]; /* To upper extended characters (SBCS cfg) */ +2778:Middlewares/Third_Party/FatFs/src/ff.c **** #else +2779:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_DF1S +2780:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_INVALID_NAME; /* Reject extended characters (ASCII only cfg) */ +2781:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2782:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2783:Middlewares/Third_Party/FatFs/src/ff.c **** } +2784:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsDBCS1(c)) { /* Check if it is a DBC 1st byte (always false at SBCS cfg.) */ +2785:Middlewares/Third_Party/FatFs/src/ff.c **** d = (BYTE)p[si++]; /* Get 2nd byte */ +2786:Middlewares/Third_Party/FatFs/src/ff.c **** if (!IsDBCS2(d) || i >= ni - 1) return FR_INVALID_NAME; /* Reject invalid DBC */ +2787:Middlewares/Third_Party/FatFs/src/ff.c **** sfn[i++] = c; +2788:Middlewares/Third_Party/FatFs/src/ff.c **** sfn[i++] = d; +2789:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* SBC */ +2790:Middlewares/Third_Party/FatFs/src/ff.c **** if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) return FR_INVALID_NAME; /* Reject illegal chrs for SFN */ +2791:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsLower(c)) c -= 0x20; /* To upper */ +2792:Middlewares/Third_Party/FatFs/src/ff.c **** sfn[i++] = c; +2793:Middlewares/Third_Party/FatFs/src/ff.c **** } +2794:Middlewares/Third_Party/FatFs/src/ff.c **** } +2795:Middlewares/Third_Party/FatFs/src/ff.c **** *path = p + si; /* Return pointer to the next segment */ + 1354 .loc 1 2795 2 is_stmt 1 view .LVU397 + 1355 .loc 1 2795 12 is_stmt 0 view .LVU398 + 1356 0030 4644 add r6, r6, r8 + 1357 .LVL140: + 1358 .loc 1 2795 8 view .LVU399 + 1359 0032 CAF80060 str r6, [r10] +2796:Middlewares/Third_Party/FatFs/src/ff.c **** if (i == 0) return FR_INVALID_NAME; /* Reject nul string */ + 1360 .loc 1 2796 2 is_stmt 1 view .LVU400 + 1361 .loc 1 2796 5 is_stmt 0 view .LVU401 + 1362 0036 002D cmp r5, #0 + ARM GAS /tmp/cc2SVLkL.s page 75 + + + 1363 0038 44D0 beq .L125 +2797:Middlewares/Third_Party/FatFs/src/ff.c **** +2798:Middlewares/Third_Party/FatFs/src/ff.c **** if (sfn[0] == DDEM) sfn[0] = RDDEM; /* If the first character collides with DDEM, replace it with + 1364 .loc 1 2798 2 is_stmt 1 view .LVU402 + 1365 .loc 1 2798 9 is_stmt 0 view .LVU403 + 1366 003a 99F82430 ldrb r3, [r9, #36] @ zero_extendqisi2 + 1367 .loc 1 2798 5 view .LVU404 + 1368 003e E52B cmp r3, #229 + 1369 0040 35D0 beq .L129 + 1370 .L121: +2799:Middlewares/Third_Party/FatFs/src/ff.c **** sfn[NSFLAG] = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */ + 1371 .loc 1 2799 2 is_stmt 1 view .LVU405 + 1372 .loc 1 2799 14 is_stmt 0 view .LVU406 + 1373 0042 202C cmp r4, #32 + 1374 0044 37D8 bhi .L126 + 1375 .loc 1 2799 14 discriminator 1 view .LVU407 + 1376 0046 0423 movs r3, #4 + 1377 .L122: + 1378 .loc 1 2799 14 discriminator 4 view .LVU408 + 1379 0048 89F82F30 strb r3, [r9, #47] +2800:Middlewares/Third_Party/FatFs/src/ff.c **** +2801:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_OK; + 1380 .loc 1 2801 2 is_stmt 1 view .LVU409 + 1381 .loc 1 2801 9 is_stmt 0 view .LVU410 + 1382 004c 0020 movs r0, #0 + 1383 004e 35E0 b .L117 + 1384 .LVL141: + 1385 .L116: +2775:Middlewares/Third_Party/FatFs/src/ff.c **** #ifdef _EXCVT + 1386 .loc 1 2775 3 is_stmt 1 view .LVU411 +2775:Middlewares/Third_Party/FatFs/src/ff.c **** #ifdef _EXCVT + 1387 .loc 1 2775 6 is_stmt 0 view .LVU412 + 1388 0050 14F0800F tst r4, #128 + 1389 0054 27D1 bne .L130 + 1390 .L119: +2784:Middlewares/Third_Party/FatFs/src/ff.c **** d = (BYTE)p[si++]; /* Get 2nd byte */ + 1391 .loc 1 2784 3 is_stmt 1 view .LVU413 +2790:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsLower(c)) c -= 0x20; /* To upper */ + 1392 .loc 1 2790 4 view .LVU414 +2790:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsLower(c)) c -= 0x20; /* To upper */ + 1393 .loc 1 2790 8 is_stmt 0 view .LVU415 + 1394 0056 2146 mov r1, r4 + 1395 0058 1B48 ldr r0, .L131 + 1396 005a FFF7FEFF bl chk_chr + 1397 .LVL142: +2790:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsLower(c)) c -= 0x20; /* To upper */ + 1398 .loc 1 2790 7 discriminator 1 view .LVU416 + 1399 005e 78BB cbnz r0, .L124 +2791:Middlewares/Third_Party/FatFs/src/ff.c **** sfn[i++] = c; + 1400 .loc 1 2791 4 is_stmt 1 view .LVU417 +2791:Middlewares/Third_Party/FatFs/src/ff.c **** sfn[i++] = c; + 1401 .loc 1 2791 8 is_stmt 0 view .LVU418 + 1402 0060 A4F16103 sub r3, r4, #97 + 1403 0064 DBB2 uxtb r3, r3 +2791:Middlewares/Third_Party/FatFs/src/ff.c **** sfn[i++] = c; + 1404 .loc 1 2791 7 view .LVU419 + 1405 0066 192B cmp r3, #25 + ARM GAS /tmp/cc2SVLkL.s page 76 + + + 1406 0068 01D8 bhi .L120 +2791:Middlewares/Third_Party/FatFs/src/ff.c **** sfn[i++] = c; + 1407 .loc 1 2791 20 is_stmt 1 discriminator 1 view .LVU420 +2791:Middlewares/Third_Party/FatFs/src/ff.c **** sfn[i++] = c; + 1408 .loc 1 2791 22 is_stmt 0 discriminator 1 view .LVU421 + 1409 006a 203C subs r4, r4, #32 + 1410 .LVL143: +2791:Middlewares/Third_Party/FatFs/src/ff.c **** sfn[i++] = c; + 1411 .loc 1 2791 22 discriminator 1 view .LVU422 + 1412 006c E4B2 uxtb r4, r4 + 1413 .LVL144: + 1414 .L120: +2792:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1415 .loc 1 2792 4 is_stmt 1 view .LVU423 +2792:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1416 .loc 1 2792 13 is_stmt 0 view .LVU424 + 1417 006e 0BF80540 strb r4, [fp, r5] +2792:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1418 .loc 1 2792 9 view .LVU425 + 1419 0072 0135 adds r5, r5, #1 + 1420 .LVL145: + 1421 .L118: +2792:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1422 .loc 1 2792 9 view .LVU426 + 1423 0074 3346 mov r3, r6 + 1424 .LVL146: + 1425 .L111: +2763:Middlewares/Third_Party/FatFs/src/ff.c **** c = (BYTE)p[si++]; + 1426 .loc 1 2763 2 is_stmt 1 view .LVU427 +2764:Middlewares/Third_Party/FatFs/src/ff.c **** if (c <= ' ') break; /* Break if end of the path name */ + 1427 .loc 1 2764 3 view .LVU428 +2764:Middlewares/Third_Party/FatFs/src/ff.c **** if (c <= ' ') break; /* Break if end of the path name */ + 1428 .loc 1 2764 17 is_stmt 0 view .LVU429 + 1429 0076 5E1C adds r6, r3, #1 + 1430 .LVL147: +2764:Middlewares/Third_Party/FatFs/src/ff.c **** if (c <= ' ') break; /* Break if end of the path name */ + 1431 .loc 1 2764 5 view .LVU430 + 1432 0078 18F80340 ldrb r4, [r8, r3] @ zero_extendqisi2 + 1433 .LVL148: +2765:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == '/' || c == '\\') { /* Break if a separator is found */ + 1434 .loc 1 2765 3 is_stmt 1 view .LVU431 +2765:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == '/' || c == '\\') { /* Break if a separator is found */ + 1435 .loc 1 2765 6 is_stmt 0 view .LVU432 + 1436 007c 202C cmp r4, #32 + 1437 007e D7D9 bls .L112 +2766:Middlewares/Third_Party/FatFs/src/ff.c **** while (p[si] == '/' || p[si] == '\\') si++; /* Skip duplicated separator if exist */ + 1438 .loc 1 2766 3 is_stmt 1 view .LVU433 +2766:Middlewares/Third_Party/FatFs/src/ff.c **** while (p[si] == '/' || p[si] == '\\') si++; /* Skip duplicated separator if exist */ + 1439 .loc 1 2766 6 is_stmt 0 view .LVU434 + 1440 0080 5C2C cmp r4, #92 + 1441 0082 18BF it ne + 1442 0084 2F2C cmpne r4, #47 + 1443 0086 CDD0 beq .L113 +2770:Middlewares/Third_Party/FatFs/src/ff.c **** if (ni == 11 || c != '.') return FR_INVALID_NAME; /* Over size or invalid dot */ + 1444 .loc 1 2770 3 is_stmt 1 view .LVU435 +2770:Middlewares/Third_Party/FatFs/src/ff.c **** if (ni == 11 || c != '.') return FR_INVALID_NAME; /* Over size or invalid dot */ + 1445 .loc 1 2770 6 is_stmt 0 view .LVU436 + ARM GAS /tmp/cc2SVLkL.s page 77 + + + 1446 0088 2E2C cmp r4, #46 + 1447 008a 18BF it ne + 1448 008c AF42 cmpne r7, r5 + 1449 008e DFD8 bhi .L116 +2771:Middlewares/Third_Party/FatFs/src/ff.c **** i = 8; ni = 11; /* Goto extension */ + 1450 .loc 1 2771 4 is_stmt 1 view .LVU437 +2771:Middlewares/Third_Party/FatFs/src/ff.c **** i = 8; ni = 11; /* Goto extension */ + 1451 .loc 1 2771 22 is_stmt 0 view .LVU438 + 1452 0090 2E3C subs r4, r4, #46 + 1453 .LVL149: +2771:Middlewares/Third_Party/FatFs/src/ff.c **** i = 8; ni = 11; /* Goto extension */ + 1454 .loc 1 2771 22 view .LVU439 + 1455 0092 18BF it ne + 1456 0094 0124 movne r4, #1 + 1457 .LVL150: +2771:Middlewares/Third_Party/FatFs/src/ff.c **** i = 8; ni = 11; /* Goto extension */ + 1458 .loc 1 2771 17 view .LVU440 + 1459 0096 0B2F cmp r7, #11 + 1460 0098 08BF it eq + 1461 009a 44F00104 orreq r4, r4, #1 +2771:Middlewares/Third_Party/FatFs/src/ff.c **** i = 8; ni = 11; /* Goto extension */ + 1462 .loc 1 2771 7 view .LVU441 + 1463 009e 64B9 cbnz r4, .L123 +2772:Middlewares/Third_Party/FatFs/src/ff.c **** continue; + 1464 .loc 1 2772 6 view .LVU442 + 1465 00a0 0825 movs r5, #8 + 1466 .LVL151: +2772:Middlewares/Third_Party/FatFs/src/ff.c **** continue; + 1467 .loc 1 2772 14 view .LVU443 + 1468 00a2 0B27 movs r7, #11 + 1469 .LVL152: +2772:Middlewares/Third_Party/FatFs/src/ff.c **** continue; + 1470 .loc 1 2772 14 view .LVU444 + 1471 00a4 E6E7 b .L118 + 1472 .LVL153: + 1473 .L130: +2777:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 1474 .loc 1 2777 4 is_stmt 1 view .LVU445 +2777:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 1475 .loc 1 2777 16 is_stmt 0 view .LVU446 + 1476 00a6 803C subs r4, r4, #128 + 1477 .LVL154: +2777:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 1478 .loc 1 2777 6 view .LVU447 + 1479 00a8 084B ldr r3, .L131+4 + 1480 00aa 1C5D ldrb r4, [r3, r4] @ zero_extendqisi2 + 1481 .LVL155: +2777:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 1482 .loc 1 2777 6 view .LVU448 + 1483 00ac D3E7 b .L119 + 1484 .LVL156: + 1485 .L129: +2798:Middlewares/Third_Party/FatFs/src/ff.c **** sfn[NSFLAG] = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */ + 1486 .loc 1 2798 22 is_stmt 1 discriminator 1 view .LVU449 +2798:Middlewares/Third_Party/FatFs/src/ff.c **** sfn[NSFLAG] = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */ + 1487 .loc 1 2798 29 is_stmt 0 discriminator 1 view .LVU450 + 1488 00ae 0523 movs r3, #5 + ARM GAS /tmp/cc2SVLkL.s page 78 + + + 1489 00b0 89F82430 strb r3, [r9, #36] + 1490 00b4 C5E7 b .L121 + 1491 .L126: +2799:Middlewares/Third_Party/FatFs/src/ff.c **** + 1492 .loc 1 2799 14 discriminator 2 view .LVU451 + 1493 00b6 0023 movs r3, #0 + 1494 00b8 C6E7 b .L122 + 1495 .LVL157: + 1496 .L123: +2771:Middlewares/Third_Party/FatFs/src/ff.c **** i = 8; ni = 11; /* Goto extension */ + 1497 .loc 1 2771 37 discriminator 1 view .LVU452 + 1498 00ba 0620 movs r0, #6 + 1499 .LVL158: + 1500 .L117: +2802:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _USE_LFN != 0 */ +2803:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1501 .loc 1 2803 1 view .LVU453 + 1502 00bc BDE8F88F pop {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc} + 1503 .LVL159: + 1504 .L124: +2790:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsLower(c)) c -= 0x20; /* To upper */ + 1505 .loc 1 2790 50 discriminator 1 view .LVU454 + 1506 00c0 0620 movs r0, #6 + 1507 00c2 FBE7 b .L117 + 1508 .LVL160: + 1509 .L125: +2796:Middlewares/Third_Party/FatFs/src/ff.c **** + 1510 .loc 1 2796 21 discriminator 1 view .LVU455 + 1511 00c4 0620 movs r0, #6 + 1512 00c6 F9E7 b .L117 + 1513 .L132: + 1514 .align 2 + 1515 .L131: + 1516 00c8 00000000 .word .LC0 + 1517 00cc 00000000 .word ExCvt + 1518 .cfi_endproc + 1519 .LFE1215: + 1521 .section .text.get_ldnumber,"ax",%progbits + 1522 .align 1 + 1523 .syntax unified + 1524 .thumb + 1525 .thumb_func + 1527 get_ldnumber: + 1528 .LVL161: + 1529 .LFB1217: +2804:Middlewares/Third_Party/FatFs/src/ff.c **** +2805:Middlewares/Third_Party/FatFs/src/ff.c **** +2806:Middlewares/Third_Party/FatFs/src/ff.c **** +2807:Middlewares/Third_Party/FatFs/src/ff.c **** +2808:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2809:Middlewares/Third_Party/FatFs/src/ff.c **** /* Follow a file path */ +2810:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2811:Middlewares/Third_Party/FatFs/src/ff.c **** +2812:Middlewares/Third_Party/FatFs/src/ff.c **** static +2813:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ +2814:Middlewares/Third_Party/FatFs/src/ff.c **** DIR* dp, /* Directory object to return last directory and found object */ +2815:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* path /* Full-path string to find a file or directory */ + ARM GAS /tmp/cc2SVLkL.s page 79 + + +2816:Middlewares/Third_Party/FatFs/src/ff.c **** ) +2817:Middlewares/Third_Party/FatFs/src/ff.c **** { +2818:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +2819:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE ns; +2820:Middlewares/Third_Party/FatFs/src/ff.c **** _FDID *obj = &dp->obj; +2821:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = obj->fs; +2822:Middlewares/Third_Party/FatFs/src/ff.c **** +2823:Middlewares/Third_Party/FatFs/src/ff.c **** +2824:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0 +2825:Middlewares/Third_Party/FatFs/src/ff.c **** if (*path != '/' && *path != '\\') { /* Without heading separator */ +2826:Middlewares/Third_Party/FatFs/src/ff.c **** obj->sclust = fs->cdir; /* Start from current directory */ +2827:Middlewares/Third_Party/FatFs/src/ff.c **** } else +2828:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2829:Middlewares/Third_Party/FatFs/src/ff.c **** { /* With heading separator */ +2830:Middlewares/Third_Party/FatFs/src/ff.c **** while (*path == '/' || *path == '\\') path++; /* Strip heading separator */ +2831:Middlewares/Third_Party/FatFs/src/ff.c **** obj->sclust = 0; /* Start from root directory */ +2832:Middlewares/Third_Party/FatFs/src/ff.c **** } +2833:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +2834:Middlewares/Third_Party/FatFs/src/ff.c **** obj->n_frag = 0; /* Invalidate last fragment counter of the object */ +2835:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0 +2836:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT && obj->sclust) { /* Retrieve the sub-directory status if needed */ +2837:Middlewares/Third_Party/FatFs/src/ff.c **** DIR dj; +2838:Middlewares/Third_Party/FatFs/src/ff.c **** +2839:Middlewares/Third_Party/FatFs/src/ff.c **** obj->c_scl = fs->cdc_scl; +2840:Middlewares/Third_Party/FatFs/src/ff.c **** obj->c_size = fs->cdc_size; +2841:Middlewares/Third_Party/FatFs/src/ff.c **** obj->c_ofs = fs->cdc_ofs; +2842:Middlewares/Third_Party/FatFs/src/ff.c **** res = load_obj_dir(&dj, obj); +2843:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; +2844:Middlewares/Third_Party/FatFs/src/ff.c **** obj->objsize = ld_dword(fs->dirbuf + XDIR_FileSize); +2845:Middlewares/Third_Party/FatFs/src/ff.c **** obj->stat = fs->dirbuf[XDIR_GenFlags] & 2; +2846:Middlewares/Third_Party/FatFs/src/ff.c **** } +2847:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2848:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2849:Middlewares/Third_Party/FatFs/src/ff.c **** +2850:Middlewares/Third_Party/FatFs/src/ff.c **** if ((UINT)*path < ' ') { /* Null path name is the origin directory itself */ +2851:Middlewares/Third_Party/FatFs/src/ff.c **** dp->fn[NSFLAG] = NS_NONAME; +2852:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(dp, 0); +2853:Middlewares/Third_Party/FatFs/src/ff.c **** +2854:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* Follow path */ +2855:Middlewares/Third_Party/FatFs/src/ff.c **** for (;;) { +2856:Middlewares/Third_Party/FatFs/src/ff.c **** res = create_name(dp, &path); /* Get a segment name of the path */ +2857:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +2858:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_find(dp); /* Find an object with the segment name */ +2859:Middlewares/Third_Party/FatFs/src/ff.c **** ns = dp->fn[NSFLAG]; +2860:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) { /* Failed to find the object */ +2861:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) { /* Object is not found */ +2862:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exist, stay there */ +2863:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(ns & NS_LAST)) continue; /* Continue to follow if not last segment */ +2864:Middlewares/Third_Party/FatFs/src/ff.c **** dp->fn[NSFLAG] = NS_NONAME; +2865:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; +2866:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* Could not find the object */ +2867:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(ns & NS_LAST)) res = FR_NO_PATH; /* Adjust error code if not last segment */ +2868:Middlewares/Third_Party/FatFs/src/ff.c **** } +2869:Middlewares/Third_Party/FatFs/src/ff.c **** } +2870:Middlewares/Third_Party/FatFs/src/ff.c **** break; +2871:Middlewares/Third_Party/FatFs/src/ff.c **** } +2872:Middlewares/Third_Party/FatFs/src/ff.c **** if (ns & NS_LAST) break; /* Last segment matched. Function completed. */ + ARM GAS /tmp/cc2SVLkL.s page 80 + + +2873:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get into the sub-directory */ +2874:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(obj->attr & AM_DIR)) { /* It is not a sub-directory and cannot follow */ +2875:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_NO_PATH; break; +2876:Middlewares/Third_Party/FatFs/src/ff.c **** } +2877:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +2878:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { /* Save containing directory information for next dir */ +2879:Middlewares/Third_Party/FatFs/src/ff.c **** obj->c_scl = obj->sclust; +2880:Middlewares/Third_Party/FatFs/src/ff.c **** obj->c_size = ((DWORD)obj->objsize & 0xFFFFFF00) | obj->stat; +2881:Middlewares/Third_Party/FatFs/src/ff.c **** obj->c_ofs = dp->blk_ofs; +2882:Middlewares/Third_Party/FatFs/src/ff.c **** obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus); /* Open next directory */ +2883:Middlewares/Third_Party/FatFs/src/ff.c **** obj->stat = fs->dirbuf[XDIR_GenFlags] & 2; +2884:Middlewares/Third_Party/FatFs/src/ff.c **** obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize); +2885:Middlewares/Third_Party/FatFs/src/ff.c **** } else +2886:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2887:Middlewares/Third_Party/FatFs/src/ff.c **** { +2888:Middlewares/Third_Party/FatFs/src/ff.c **** obj->sclust = ld_clust(fs, fs->win + dp->dptr % SS(fs)); /* Open next directory */ +2889:Middlewares/Third_Party/FatFs/src/ff.c **** } +2890:Middlewares/Third_Party/FatFs/src/ff.c **** } +2891:Middlewares/Third_Party/FatFs/src/ff.c **** } +2892:Middlewares/Third_Party/FatFs/src/ff.c **** +2893:Middlewares/Third_Party/FatFs/src/ff.c **** return res; +2894:Middlewares/Third_Party/FatFs/src/ff.c **** } +2895:Middlewares/Third_Party/FatFs/src/ff.c **** +2896:Middlewares/Third_Party/FatFs/src/ff.c **** +2897:Middlewares/Third_Party/FatFs/src/ff.c **** +2898:Middlewares/Third_Party/FatFs/src/ff.c **** +2899:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2900:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get logical drive number from path name */ +2901:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2902:Middlewares/Third_Party/FatFs/src/ff.c **** +2903:Middlewares/Third_Party/FatFs/src/ff.c **** static +2904:Middlewares/Third_Party/FatFs/src/ff.c **** int get_ldnumber ( /* Returns logical drive number (-1:invalid drive) */ +2905:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR** path /* Pointer to pointer to the path name */ +2906:Middlewares/Third_Party/FatFs/src/ff.c **** ) +2907:Middlewares/Third_Party/FatFs/src/ff.c **** { + 1530 .loc 1 2907 1 is_stmt 1 view -0 + 1531 .cfi_startproc + 1532 @ args = 0, pretend = 0, frame = 0 + 1533 @ frame_needed = 0, uses_anonymous_args = 0 + 1534 @ link register save eliminated. + 1535 .loc 1 2907 1 is_stmt 0 view .LVU457 + 1536 0000 0146 mov r1, r0 +2908:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR *tp, *tt; + 1537 .loc 1 2908 2 is_stmt 1 view .LVU458 +2909:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i; + 1538 .loc 1 2909 2 view .LVU459 +2910:Middlewares/Third_Party/FatFs/src/ff.c **** int vol = -1; + 1539 .loc 1 2910 2 view .LVU460 + 1540 .LVL162: +2911:Middlewares/Third_Party/FatFs/src/ff.c **** #if _STR_VOLUME_ID /* Find string drive id */ +2912:Middlewares/Third_Party/FatFs/src/ff.c **** static const char* const volid[] = {_VOLUME_STRS}; +2913:Middlewares/Third_Party/FatFs/src/ff.c **** const char *sp; +2914:Middlewares/Third_Party/FatFs/src/ff.c **** char c; +2915:Middlewares/Third_Party/FatFs/src/ff.c **** TCHAR tc; +2916:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2917:Middlewares/Third_Party/FatFs/src/ff.c **** +2918:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 81 + + +2919:Middlewares/Third_Party/FatFs/src/ff.c **** if (*path) { /* If the pointer is not a null */ + 1541 .loc 1 2919 2 view .LVU461 + 1542 .loc 1 2919 6 is_stmt 0 view .LVU462 + 1543 0002 0068 ldr r0, [r0] + 1544 .LVL163: + 1545 .loc 1 2919 5 view .LVU463 + 1546 0004 08B1 cbz r0, .L144 +2920:Middlewares/Third_Party/FatFs/src/ff.c **** for (tt = *path; (UINT)*tt >= (_USE_LFN ? ' ' : '!') && *tt != ':'; tt++) ; /* Find ':' in the pa + 1547 .loc 1 2920 11 view .LVU464 + 1548 0006 0246 mov r2, r0 + 1549 0008 03E0 b .L134 + 1550 .L144: +2910:Middlewares/Third_Party/FatFs/src/ff.c **** int vol = -1; + 1551 .loc 1 2910 6 view .LVU465 + 1552 000a 4FF0FF30 mov r0, #-1 + 1553 000e 7047 bx lr + 1554 .LVL164: + 1555 .L136: + 1556 .loc 1 2920 73 is_stmt 1 discriminator 3 view .LVU466 + 1557 0010 0132 adds r2, r2, #1 + 1558 .LVL165: + 1559 .L134: + 1560 .loc 1 2920 56 discriminator 1 view .LVU467 + 1561 .loc 1 2920 26 is_stmt 0 discriminator 1 view .LVU468 + 1562 0012 1378 ldrb r3, [r2] @ zero_extendqisi2 + 1563 .loc 1 2920 56 discriminator 1 view .LVU469 + 1564 0014 202B cmp r3, #32 + 1565 0016 01D9 bls .L143 + 1566 0018 3A2B cmp r3, #58 + 1567 001a F9D1 bne .L136 + 1568 .L143: +2921:Middlewares/Third_Party/FatFs/src/ff.c **** if (*tt == ':') { /* If a ':' is exist in the path name */ + 1569 .loc 1 2921 3 is_stmt 1 view .LVU470 + 1570 .loc 1 2921 6 is_stmt 0 view .LVU471 + 1571 001c 3A2B cmp r3, #58 + 1572 001e 01D0 beq .L145 +2922:Middlewares/Third_Party/FatFs/src/ff.c **** tp = *path; +2923:Middlewares/Third_Party/FatFs/src/ff.c **** i = *tp++ - '0'; +2924:Middlewares/Third_Party/FatFs/src/ff.c **** if (i < 10 && tp == tt) { /* Is there a numeric drive id? */ +2925:Middlewares/Third_Party/FatFs/src/ff.c **** if (i < _VOLUMES) { /* If a drive id is found, get the value and strip it */ +2926:Middlewares/Third_Party/FatFs/src/ff.c **** vol = (int)i; +2927:Middlewares/Third_Party/FatFs/src/ff.c **** *path = ++tt; +2928:Middlewares/Third_Party/FatFs/src/ff.c **** } +2929:Middlewares/Third_Party/FatFs/src/ff.c **** } +2930:Middlewares/Third_Party/FatFs/src/ff.c **** #if _STR_VOLUME_ID +2931:Middlewares/Third_Party/FatFs/src/ff.c **** else { /* No numeric drive number, find string drive id */ +2932:Middlewares/Third_Party/FatFs/src/ff.c **** i = 0; tt++; +2933:Middlewares/Third_Party/FatFs/src/ff.c **** do { +2934:Middlewares/Third_Party/FatFs/src/ff.c **** sp = volid[i]; tp = *path; +2935:Middlewares/Third_Party/FatFs/src/ff.c **** do { /* Compare a string drive id with path name */ +2936:Middlewares/Third_Party/FatFs/src/ff.c **** c = *sp++; tc = *tp++; +2937:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsLower(tc)) tc -= 0x20; +2938:Middlewares/Third_Party/FatFs/src/ff.c **** } while (c && (TCHAR)c == tc); +2939:Middlewares/Third_Party/FatFs/src/ff.c **** } while ((c || tp != tt) && ++i < _VOLUMES); /* Repeat for each id until pattern match */ +2940:Middlewares/Third_Party/FatFs/src/ff.c **** if (i < _VOLUMES) { /* If a drive id is found, get the value and strip it */ +2941:Middlewares/Third_Party/FatFs/src/ff.c **** vol = (int)i; +2942:Middlewares/Third_Party/FatFs/src/ff.c **** *path = tt; + ARM GAS /tmp/cc2SVLkL.s page 82 + + +2943:Middlewares/Third_Party/FatFs/src/ff.c **** } +2944:Middlewares/Third_Party/FatFs/src/ff.c **** } +2945:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2946:Middlewares/Third_Party/FatFs/src/ff.c **** return vol; +2947:Middlewares/Third_Party/FatFs/src/ff.c **** } +2948:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0 && _VOLUMES >= 2 +2949:Middlewares/Third_Party/FatFs/src/ff.c **** vol = CurrVol; /* Current drive */ +2950:Middlewares/Third_Party/FatFs/src/ff.c **** #else +2951:Middlewares/Third_Party/FatFs/src/ff.c **** vol = 0; /* Drive 0 */ + 1573 .loc 1 2951 7 view .LVU472 + 1574 0020 0020 movs r0, #0 + 1575 .LVL166: +2952:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2953:Middlewares/Third_Party/FatFs/src/ff.c **** } +2954:Middlewares/Third_Party/FatFs/src/ff.c **** return vol; +2955:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1576 .loc 1 2955 1 view .LVU473 + 1577 0022 7047 bx lr + 1578 .LVL167: + 1579 .L145: +2922:Middlewares/Third_Party/FatFs/src/ff.c **** tp = *path; + 1580 .loc 1 2922 4 is_stmt 1 view .LVU474 +2923:Middlewares/Third_Party/FatFs/src/ff.c **** if (i < 10 && tp == tt) { /* Is there a numeric drive id? */ + 1581 .loc 1 2923 4 view .LVU475 +2923:Middlewares/Third_Party/FatFs/src/ff.c **** if (i < 10 && tp == tt) { /* Is there a numeric drive id? */ + 1582 .loc 1 2923 11 is_stmt 0 view .LVU476 + 1583 0024 0346 mov r3, r0 + 1584 .LVL168: +2923:Middlewares/Third_Party/FatFs/src/ff.c **** if (i < 10 && tp == tt) { /* Is there a numeric drive id? */ + 1585 .loc 1 2923 8 view .LVU477 + 1586 0026 13F8010B ldrb r0, [r3], #1 @ zero_extendqisi2 + 1587 .LVL169: +2923:Middlewares/Third_Party/FatFs/src/ff.c **** if (i < 10 && tp == tt) { /* Is there a numeric drive id? */ + 1588 .loc 1 2923 14 view .LVU478 + 1589 002a 3038 subs r0, r0, #48 + 1590 .LVL170: +2924:Middlewares/Third_Party/FatFs/src/ff.c **** if (i < _VOLUMES) { /* If a drive id is found, get the value and strip it */ + 1591 .loc 1 2924 4 is_stmt 1 view .LVU479 +2924:Middlewares/Third_Party/FatFs/src/ff.c **** if (i < _VOLUMES) { /* If a drive id is found, get the value and strip it */ + 1592 .loc 1 2924 7 is_stmt 0 view .LVU480 + 1593 002c 0928 cmp r0, #9 + 1594 002e 98BF it ls + 1595 0030 9A42 cmpls r2, r3 + 1596 0032 03D1 bne .L141 +2925:Middlewares/Third_Party/FatFs/src/ff.c **** vol = (int)i; + 1597 .loc 1 2925 5 is_stmt 1 view .LVU481 +2925:Middlewares/Third_Party/FatFs/src/ff.c **** vol = (int)i; + 1598 .loc 1 2925 8 is_stmt 0 view .LVU482 + 1599 0034 28B9 cbnz r0, .L142 +2926:Middlewares/Third_Party/FatFs/src/ff.c **** *path = ++tt; + 1600 .loc 1 2926 6 is_stmt 1 view .LVU483 + 1601 .LVL171: +2927:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1602 .loc 1 2927 6 view .LVU484 +2927:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1603 .loc 1 2927 12 is_stmt 0 view .LVU485 + 1604 0036 0132 adds r2, r2, #1 + ARM GAS /tmp/cc2SVLkL.s page 83 + + + 1605 .LVL172: +2927:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1606 .loc 1 2927 12 view .LVU486 + 1607 0038 0A60 str r2, [r1] + 1608 003a 7047 bx lr + 1609 .LVL173: + 1610 .L141: +2910:Middlewares/Third_Party/FatFs/src/ff.c **** #if _STR_VOLUME_ID /* Find string drive id */ + 1611 .loc 1 2910 6 view .LVU487 + 1612 003c 4FF0FF30 mov r0, #-1 + 1613 .LVL174: +2910:Middlewares/Third_Party/FatFs/src/ff.c **** #if _STR_VOLUME_ID /* Find string drive id */ + 1614 .loc 1 2910 6 view .LVU488 + 1615 0040 7047 bx lr + 1616 .LVL175: + 1617 .L142: +2910:Middlewares/Third_Party/FatFs/src/ff.c **** #if _STR_VOLUME_ID /* Find string drive id */ + 1618 .loc 1 2910 6 view .LVU489 + 1619 0042 4FF0FF30 mov r0, #-1 + 1620 .LVL176: +2946:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1621 .loc 1 2946 4 is_stmt 1 view .LVU490 +2946:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1622 .loc 1 2946 11 is_stmt 0 view .LVU491 + 1623 0046 7047 bx lr + 1624 .cfi_endproc + 1625 .LFE1217: + 1627 .section .text.putc_init,"ax",%progbits + 1628 .align 1 + 1629 .syntax unified + 1630 .thumb + 1631 .thumb_func + 1633 putc_init: + 1634 .LVL177: + 1635 .LFB1241: +2956:Middlewares/Third_Party/FatFs/src/ff.c **** +2957:Middlewares/Third_Party/FatFs/src/ff.c **** +2958:Middlewares/Third_Party/FatFs/src/ff.c **** +2959:Middlewares/Third_Party/FatFs/src/ff.c **** +2960:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2961:Middlewares/Third_Party/FatFs/src/ff.c **** /* Load a sector and check if it is an FAT boot sector */ +2962:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2963:Middlewares/Third_Party/FatFs/src/ff.c **** +2964:Middlewares/Third_Party/FatFs/src/ff.c **** static +2965:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE check_fs ( /* 0:FAT, 1:exFAT, 2:Valid BS but not FAT, 3:Not a BS, 4:Disk error */ +2966:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS* fs, /* File system object */ +2967:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD sect /* Sector# (lba) to load and check if it is an FAT-VBR or not */ +2968:Middlewares/Third_Party/FatFs/src/ff.c **** ) +2969:Middlewares/Third_Party/FatFs/src/ff.c **** { +2970:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 0; fs->winsect = 0xFFFFFFFF; /* Invaidate window */ +2971:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, sect) != FR_OK) return 4; /* Load boot record */ +2972:Middlewares/Third_Party/FatFs/src/ff.c **** +2973:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_word(fs->win + BS_55AA) != 0xAA55) return 3; /* Check boot record signature (always placed +2974:Middlewares/Third_Party/FatFs/src/ff.c **** +2975:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->win[BS_JmpBoot] == 0xE9 || (fs->win[BS_JmpBoot] == 0xEB && fs->win[BS_JmpBoot + 2] == 0x90 +2976:Middlewares/Third_Party/FatFs/src/ff.c **** if ((ld_dword(fs->win + BS_FilSysType) & 0xFFFFFF) == 0x544146) return 0; /* Check "FAT" string * +2977:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_dword(fs->win + BS_FilSysType32) == 0x33544146) return 0; /* Check "FAT3" string */ + ARM GAS /tmp/cc2SVLkL.s page 84 + + +2978:Middlewares/Third_Party/FatFs/src/ff.c **** } +2979:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +2980:Middlewares/Third_Party/FatFs/src/ff.c **** if (!mem_cmp(fs->win + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11)) return 1; +2981:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +2982:Middlewares/Third_Party/FatFs/src/ff.c **** return 2; +2983:Middlewares/Third_Party/FatFs/src/ff.c **** } +2984:Middlewares/Third_Party/FatFs/src/ff.c **** +2985:Middlewares/Third_Party/FatFs/src/ff.c **** +2986:Middlewares/Third_Party/FatFs/src/ff.c **** +2987:Middlewares/Third_Party/FatFs/src/ff.c **** +2988:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2989:Middlewares/Third_Party/FatFs/src/ff.c **** /* Find logical drive and check if the volume is mounted */ +2990:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +2991:Middlewares/Third_Party/FatFs/src/ff.c **** +2992:Middlewares/Third_Party/FatFs/src/ff.c **** static +2993:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT find_volume ( /* FR_OK(0): successful, !=0: any error occurred */ +2994:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR** path, /* Pointer to pointer to the path name (drive number) */ +2995:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS** rfs, /* Pointer to pointer to the found file system object */ +2996:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE mode /* !=0: Check write protection for write access */ +2997:Middlewares/Third_Party/FatFs/src/ff.c **** ) +2998:Middlewares/Third_Party/FatFs/src/ff.c **** { +2999:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE fmt, *pt; +3000:Middlewares/Third_Party/FatFs/src/ff.c **** int vol; +3001:Middlewares/Third_Party/FatFs/src/ff.c **** DSTATUS stat; +3002:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD bsect, fasize, tsect, sysect, nclst, szbfat, br[4]; +3003:Middlewares/Third_Party/FatFs/src/ff.c **** WORD nrsv; +3004:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +3005:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i; +3006:Middlewares/Third_Party/FatFs/src/ff.c **** +3007:Middlewares/Third_Party/FatFs/src/ff.c **** +3008:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get logical drive number */ +3009:Middlewares/Third_Party/FatFs/src/ff.c **** *rfs = 0; +3010:Middlewares/Third_Party/FatFs/src/ff.c **** vol = get_ldnumber(path); +3011:Middlewares/Third_Party/FatFs/src/ff.c **** if (vol < 0) return FR_INVALID_DRIVE; +3012:Middlewares/Third_Party/FatFs/src/ff.c **** +3013:Middlewares/Third_Party/FatFs/src/ff.c **** /* Check if the file system object is valid or not */ +3014:Middlewares/Third_Party/FatFs/src/ff.c **** fs = FatFs[vol]; /* Get pointer to the file system object */ +3015:Middlewares/Third_Party/FatFs/src/ff.c **** if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */ +3016:Middlewares/Third_Party/FatFs/src/ff.c **** +3017:Middlewares/Third_Party/FatFs/src/ff.c **** ENTER_FF(fs); /* Lock the volume */ +3018:Middlewares/Third_Party/FatFs/src/ff.c **** *rfs = fs; /* Return pointer to the file system object */ +3019:Middlewares/Third_Party/FatFs/src/ff.c **** +3020:Middlewares/Third_Party/FatFs/src/ff.c **** mode &= (BYTE)~FA_READ; /* Desired access mode, write access or not */ +3021:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type) { /* If the volume has been mounted */ +3022:Middlewares/Third_Party/FatFs/src/ff.c **** stat = disk_status(fs->drv); +3023:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized */ +3024:Middlewares/Third_Party/FatFs/src/ff.c **** if (!_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check write protection if needed */ +3025:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_WRITE_PROTECTED; +3026:Middlewares/Third_Party/FatFs/src/ff.c **** } +3027:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_OK; /* The file system object is valid */ +3028:Middlewares/Third_Party/FatFs/src/ff.c **** } +3029:Middlewares/Third_Party/FatFs/src/ff.c **** } +3030:Middlewares/Third_Party/FatFs/src/ff.c **** +3031:Middlewares/Third_Party/FatFs/src/ff.c **** /* The file system object is not valid. */ +3032:Middlewares/Third_Party/FatFs/src/ff.c **** /* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */ +3033:Middlewares/Third_Party/FatFs/src/ff.c **** +3034:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fs_type = 0; /* Clear the file system object */ + ARM GAS /tmp/cc2SVLkL.s page 85 + + +3035:Middlewares/Third_Party/FatFs/src/ff.c **** fs->drv = LD2PD(vol); /* Bind the logical drive and a physical drive */ +3036:Middlewares/Third_Party/FatFs/src/ff.c **** stat = disk_initialize(fs->drv); /* Initialize the physical drive */ +3037:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat & STA_NOINIT) { /* Check if the initialization succeeded */ +3038:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */ +3039:Middlewares/Third_Party/FatFs/src/ff.c **** } +3040:Middlewares/Third_Party/FatFs/src/ff.c **** if (!_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */ +3041:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_WRITE_PROTECTED; +3042:Middlewares/Third_Party/FatFs/src/ff.c **** } +3043:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS /* Get sector size (multiple sector size cfg only) */ +3044:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) return FR_DISK_ERR; +3045:Middlewares/Third_Party/FatFs/src/ff.c **** if (SS(fs) > _MAX_SS || SS(fs) < _MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR; +3046:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3047:Middlewares/Third_Party/FatFs/src/ff.c **** +3048:Middlewares/Third_Party/FatFs/src/ff.c **** /* Find an FAT partition on the drive. Supports only generic partitioning rules, FDISK and SFD. */ +3049:Middlewares/Third_Party/FatFs/src/ff.c **** bsect = 0; +3050:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = check_fs(fs, bsect); /* Load sector 0 and check if it is an FAT-VBR as SFD */ +3051:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == 2 || (fmt < 2 && LD2PT(vol) != 0)) { /* Not an FAT-VBR or forced partition number */ +3052:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < 4; i++) { /* Get partition offset */ +3053:Middlewares/Third_Party/FatFs/src/ff.c **** pt = fs->win + (MBR_Table + i * SZ_PTE); +3054:Middlewares/Third_Party/FatFs/src/ff.c **** br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0; +3055:Middlewares/Third_Party/FatFs/src/ff.c **** } +3056:Middlewares/Third_Party/FatFs/src/ff.c **** i = LD2PT(vol); /* Partition number: 0:auto, 1-4:forced */ +3057:Middlewares/Third_Party/FatFs/src/ff.c **** if (i) i--; +3058:Middlewares/Third_Party/FatFs/src/ff.c **** do { /* Find an FAT volume */ +3059:Middlewares/Third_Party/FatFs/src/ff.c **** bsect = br[i]; +3060:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = bsect ? check_fs(fs, bsect) : 3; /* Check the partition */ +3061:Middlewares/Third_Party/FatFs/src/ff.c **** } while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4); +3062:Middlewares/Third_Party/FatFs/src/ff.c **** } +3063:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == 4) return FR_DISK_ERR; /* An error occured in the disk I/O layer */ +3064:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt >= 2) return FR_NO_FILESYSTEM; /* No FAT volume is found */ +3065:Middlewares/Third_Party/FatFs/src/ff.c **** +3066:Middlewares/Third_Party/FatFs/src/ff.c **** /* An FAT volume is found (bsect). Following code initializes the file system object */ +3067:Middlewares/Third_Party/FatFs/src/ff.c **** +3068:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +3069:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == 1) { +3070:Middlewares/Third_Party/FatFs/src/ff.c **** QWORD maxlba; +3071:Middlewares/Third_Party/FatFs/src/ff.c **** +3072:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = BPB_ZeroedEx; i < BPB_ZeroedEx + 53 && fs->win[i] == 0; i++) ; /* Check zero filler */ +3073:Middlewares/Third_Party/FatFs/src/ff.c **** if (i < BPB_ZeroedEx + 53) return FR_NO_FILESYSTEM; +3074:Middlewares/Third_Party/FatFs/src/ff.c **** +3075:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_word(fs->win + BPB_FSVerEx) != 0x100) return FR_NO_FILESYSTEM; /* Check exFAT revision (Mu +3076:Middlewares/Third_Party/FatFs/src/ff.c **** +3077:Middlewares/Third_Party/FatFs/src/ff.c **** if (1 << fs->win[BPB_BytsPerSecEx] != SS(fs)) { /* (BPB_BytsPerSecEx must be equal to the physica +3078:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_NO_FILESYSTEM; +3079:Middlewares/Third_Party/FatFs/src/ff.c **** } +3080:Middlewares/Third_Party/FatFs/src/ff.c **** +3081:Middlewares/Third_Party/FatFs/src/ff.c **** maxlba = ld_qword(fs->win + BPB_TotSecEx) + bsect; /* Last LBA + 1 of the volume */ +3082:Middlewares/Third_Party/FatFs/src/ff.c **** if (maxlba >= 0x100000000) return FR_NO_FILESYSTEM; /* (It cannot be handled in 32-bit LBA) */ +3083:Middlewares/Third_Party/FatFs/src/ff.c **** +3084:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsize = ld_dword(fs->win + BPB_FatSzEx); /* Number of sectors per FAT */ +3085:Middlewares/Third_Party/FatFs/src/ff.c **** +3086:Middlewares/Third_Party/FatFs/src/ff.c **** fs->n_fats = fs->win[BPB_NumFATsEx]; /* Number of FATs */ +3087:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->n_fats != 1) return FR_NO_FILESYSTEM; /* (Supports only 1 FAT) */ +3088:Middlewares/Third_Party/FatFs/src/ff.c **** +3089:Middlewares/Third_Party/FatFs/src/ff.c **** fs->csize = 1 << fs->win[BPB_SecPerClusEx]; /* Cluster size */ +3090:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->csize == 0) return FR_NO_FILESYSTEM; /* (Must be 1..32768) */ +3091:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 86 + + +3092:Middlewares/Third_Party/FatFs/src/ff.c **** nclst = ld_dword(fs->win + BPB_NumClusEx); /* Number of clusters */ +3093:Middlewares/Third_Party/FatFs/src/ff.c **** if (nclst > MAX_EXFAT) return FR_NO_FILESYSTEM; /* (Too many clusters) */ +3094:Middlewares/Third_Party/FatFs/src/ff.c **** fs->n_fatent = nclst + 2; +3095:Middlewares/Third_Party/FatFs/src/ff.c **** +3096:Middlewares/Third_Party/FatFs/src/ff.c **** /* Boundaries and Limits */ +3097:Middlewares/Third_Party/FatFs/src/ff.c **** fs->volbase = bsect; +3098:Middlewares/Third_Party/FatFs/src/ff.c **** fs->database = bsect + ld_dword(fs->win + BPB_DataOfsEx); +3099:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fatbase = bsect + ld_dword(fs->win + BPB_FatOfsEx); +3100:Middlewares/Third_Party/FatFs/src/ff.c **** if (maxlba < (QWORD)fs->database + nclst * fs->csize) return FR_NO_FILESYSTEM; /* (Volume size mu +3101:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbase = ld_dword(fs->win + BPB_RootClusEx); +3102:Middlewares/Third_Party/FatFs/src/ff.c **** +3103:Middlewares/Third_Party/FatFs/src/ff.c **** /* Check if bitmap location is in assumption (at the first cluster) */ +3104:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, clust2sect(fs, fs->dirbase)) != FR_OK) return FR_DISK_ERR; +3105:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < SS(fs); i += SZDIRE) { +3106:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->win[i] == 0x81 && ld_dword(fs->win + i + 20) == 2) break; /* 81 entry with cluster #2? * +3107:Middlewares/Third_Party/FatFs/src/ff.c **** } +3108:Middlewares/Third_Party/FatFs/src/ff.c **** if (i == SS(fs)) return FR_NO_FILESYSTEM; +3109:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +3110:Middlewares/Third_Party/FatFs/src/ff.c **** fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */ +3111:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3112:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = FS_EXFAT; /* FAT sub-type */ +3113:Middlewares/Third_Party/FatFs/src/ff.c **** } else +3114:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _FS_EXFAT */ +3115:Middlewares/Third_Party/FatFs/src/ff.c **** { +3116:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_word(fs->win + BPB_BytsPerSec) != SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_BytsPerSec must +3117:Middlewares/Third_Party/FatFs/src/ff.c **** +3118:Middlewares/Third_Party/FatFs/src/ff.c **** fasize = ld_word(fs->win + BPB_FATSz16); /* Number of sectors per FAT */ +3119:Middlewares/Third_Party/FatFs/src/ff.c **** if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32); +3120:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsize = fasize; +3121:Middlewares/Third_Party/FatFs/src/ff.c **** +3122:Middlewares/Third_Party/FatFs/src/ff.c **** fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FATs */ +3123:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */ +3124:Middlewares/Third_Party/FatFs/src/ff.c **** fasize *= fs->n_fats; /* Number of sectors for FAT area */ +3125:Middlewares/Third_Party/FatFs/src/ff.c **** +3126:Middlewares/Third_Party/FatFs/src/ff.c **** fs->csize = fs->win[BPB_SecPerClus]; /* Cluster size */ +3127:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM; /* (Must be power o +3128:Middlewares/Third_Party/FatFs/src/ff.c **** +3129:Middlewares/Third_Party/FatFs/src/ff.c **** fs->n_rootdir = ld_word(fs->win + BPB_RootEntCnt); /* Number of root directory entries */ +3130:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM; /* (Must be sector aligned) */ +3131:Middlewares/Third_Party/FatFs/src/ff.c **** +3132:Middlewares/Third_Party/FatFs/src/ff.c **** tsect = ld_word(fs->win + BPB_TotSec16); /* Number of sectors on the volume */ +3133:Middlewares/Third_Party/FatFs/src/ff.c **** if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32); +3134:Middlewares/Third_Party/FatFs/src/ff.c **** +3135:Middlewares/Third_Party/FatFs/src/ff.c **** nrsv = ld_word(fs->win + BPB_RsvdSecCnt); /* Number of reserved sectors */ +3136:Middlewares/Third_Party/FatFs/src/ff.c **** if (nrsv == 0) return FR_NO_FILESYSTEM; /* (Must not be 0) */ +3137:Middlewares/Third_Party/FatFs/src/ff.c **** +3138:Middlewares/Third_Party/FatFs/src/ff.c **** /* Determine the FAT sub type */ +3139:Middlewares/Third_Party/FatFs/src/ff.c **** sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZDIRE); /* RSV + FAT + DIR */ +3140:Middlewares/Third_Party/FatFs/src/ff.c **** if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ +3141:Middlewares/Third_Party/FatFs/src/ff.c **** nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ +3142:Middlewares/Third_Party/FatFs/src/ff.c **** if (nclst == 0) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ +3143:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = FS_FAT32; +3144:Middlewares/Third_Party/FatFs/src/ff.c **** if (nclst <= MAX_FAT16) fmt = FS_FAT16; +3145:Middlewares/Third_Party/FatFs/src/ff.c **** if (nclst <= MAX_FAT12) fmt = FS_FAT12; +3146:Middlewares/Third_Party/FatFs/src/ff.c **** +3147:Middlewares/Third_Party/FatFs/src/ff.c **** /* Boundaries and Limits */ +3148:Middlewares/Third_Party/FatFs/src/ff.c **** fs->n_fatent = nclst + 2; /* Number of FAT entries */ + ARM GAS /tmp/cc2SVLkL.s page 87 + + +3149:Middlewares/Third_Party/FatFs/src/ff.c **** fs->volbase = bsect; /* Volume start sector */ +3150:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fatbase = bsect + nrsv; /* FAT start sector */ +3151:Middlewares/Third_Party/FatFs/src/ff.c **** fs->database = bsect + sysect; /* Data start sector */ +3152:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { +3153:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM; /* (Must be FAT32 revision 0.0 +3154:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ +3155:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbase = ld_dword(fs->win + BPB_RootClus32); /* Root directory start cluster */ +3156:Middlewares/Third_Party/FatFs/src/ff.c **** szbfat = fs->n_fatent * 4; /* (Needed FAT size) */ +3157:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +3158:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->n_rootdir == 0) return FR_NO_FILESYSTEM;/* (BPB_RootEntCnt must not be 0) */ +3159:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ +3160:Middlewares/Third_Party/FatFs/src/ff.c **** szbfat = (fmt == FS_FAT16) ? /* (Needed FAT size) */ +3161:Middlewares/Third_Party/FatFs/src/ff.c **** fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); +3162:Middlewares/Third_Party/FatFs/src/ff.c **** } +3163:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_FATSz must not +3164:Middlewares/Third_Party/FatFs/src/ff.c **** +3165:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +3166:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get FSINFO if available */ +3167:Middlewares/Third_Party/FatFs/src/ff.c **** fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */ +3168:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag = 0x80; +3169:Middlewares/Third_Party/FatFs/src/ff.c **** #if (_FS_NOFSINFO & 3) != 3 +3170:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32 /* Enable FSINFO only if FAT32 and BPB_FSInfo32 == 1 */ +3171:Middlewares/Third_Party/FatFs/src/ff.c **** && ld_word(fs->win + BPB_FSInfo32) == 1 +3172:Middlewares/Third_Party/FatFs/src/ff.c **** && move_window(fs, bsect + 1) == FR_OK) +3173:Middlewares/Third_Party/FatFs/src/ff.c **** { +3174:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag = 0; +3175:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_word(fs->win + BS_55AA) == 0xAA55 /* Load FSINFO data if available */ +3176:Middlewares/Third_Party/FatFs/src/ff.c **** && ld_dword(fs->win + FSI_LeadSig) == 0x41615252 +3177:Middlewares/Third_Party/FatFs/src/ff.c **** && ld_dword(fs->win + FSI_StrucSig) == 0x61417272) +3178:Middlewares/Third_Party/FatFs/src/ff.c **** { +3179:Middlewares/Third_Party/FatFs/src/ff.c **** #if (_FS_NOFSINFO & 1) == 0 +3180:Middlewares/Third_Party/FatFs/src/ff.c **** fs->free_clst = ld_dword(fs->win + FSI_Free_Count); +3181:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3182:Middlewares/Third_Party/FatFs/src/ff.c **** #if (_FS_NOFSINFO & 2) == 0 +3183:Middlewares/Third_Party/FatFs/src/ff.c **** fs->last_clst = ld_dword(fs->win + FSI_Nxt_Free); +3184:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3185:Middlewares/Third_Party/FatFs/src/ff.c **** } +3186:Middlewares/Third_Party/FatFs/src/ff.c **** } +3187:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* (_FS_NOFSINFO & 3) != 3 */ +3188:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* !_FS_READONLY */ +3189:Middlewares/Third_Party/FatFs/src/ff.c **** } +3190:Middlewares/Third_Party/FatFs/src/ff.c **** +3191:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fs_type = fmt; /* FAT sub-type */ +3192:Middlewares/Third_Party/FatFs/src/ff.c **** fs->id = ++Fsid; /* File system mount ID */ +3193:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN == 1 +3194:Middlewares/Third_Party/FatFs/src/ff.c **** fs->lfnbuf = LfnBuf; /* Static LFN working buffer */ +3195:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +3196:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbuf = DirBuf; /* Static directory block scratchpad buuffer */ +3197:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3198:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3199:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0 +3200:Middlewares/Third_Party/FatFs/src/ff.c **** fs->cdir = 0; /* Initialize current directory */ +3201:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3202:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 /* Clear file lock semaphores */ +3203:Middlewares/Third_Party/FatFs/src/ff.c **** clear_lock(fs); +3204:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3205:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_OK; + ARM GAS /tmp/cc2SVLkL.s page 88 + + +3206:Middlewares/Third_Party/FatFs/src/ff.c **** } +3207:Middlewares/Third_Party/FatFs/src/ff.c **** +3208:Middlewares/Third_Party/FatFs/src/ff.c **** +3209:Middlewares/Third_Party/FatFs/src/ff.c **** +3210:Middlewares/Third_Party/FatFs/src/ff.c **** +3211:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +3212:Middlewares/Third_Party/FatFs/src/ff.c **** /* Check if the file/directory object is valid or not */ +3213:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +3214:Middlewares/Third_Party/FatFs/src/ff.c **** +3215:Middlewares/Third_Party/FatFs/src/ff.c **** static +3216:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT validate ( /* Returns FR_OK or FR_INVALID_OBJECT */ +3217:Middlewares/Third_Party/FatFs/src/ff.c **** _FDID* obj, /* Pointer to the _OBJ, the 1st member in the FIL/DIR object, to check validity */ +3218:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS** fs /* Pointer to pointer to the owner file system object to return */ +3219:Middlewares/Third_Party/FatFs/src/ff.c **** ) +3220:Middlewares/Third_Party/FatFs/src/ff.c **** { +3221:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res = FR_INVALID_OBJECT; +3222:Middlewares/Third_Party/FatFs/src/ff.c **** +3223:Middlewares/Third_Party/FatFs/src/ff.c **** +3224:Middlewares/Third_Party/FatFs/src/ff.c **** if (obj && obj->fs && obj->fs->fs_type && obj->id == obj->fs->id) { /* Test if the object is valid +3225:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT +3226:Middlewares/Third_Party/FatFs/src/ff.c **** if (lock_fs(obj->fs)) { /* Obtain the filesystem object */ +3227:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(disk_status(obj->fs->drv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialize +3228:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; +3229:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +3230:Middlewares/Third_Party/FatFs/src/ff.c **** unlock_fs(obj->fs, FR_OK); +3231:Middlewares/Third_Party/FatFs/src/ff.c **** } +3232:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +3233:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_TIMEOUT; +3234:Middlewares/Third_Party/FatFs/src/ff.c **** } +3235:Middlewares/Third_Party/FatFs/src/ff.c **** #else +3236:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(disk_status(obj->fs->drv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialized +3237:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; +3238:Middlewares/Third_Party/FatFs/src/ff.c **** } +3239:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3240:Middlewares/Third_Party/FatFs/src/ff.c **** } +3241:Middlewares/Third_Party/FatFs/src/ff.c **** *fs = (res == FR_OK) ? obj->fs : 0; /* Corresponding filesystem object */ +3242:Middlewares/Third_Party/FatFs/src/ff.c **** return res; +3243:Middlewares/Third_Party/FatFs/src/ff.c **** } +3244:Middlewares/Third_Party/FatFs/src/ff.c **** +3245:Middlewares/Third_Party/FatFs/src/ff.c **** +3246:Middlewares/Third_Party/FatFs/src/ff.c **** +3247:Middlewares/Third_Party/FatFs/src/ff.c **** +3248:Middlewares/Third_Party/FatFs/src/ff.c **** /*--------------------------------------------------------------------------- +3249:Middlewares/Third_Party/FatFs/src/ff.c **** +3250:Middlewares/Third_Party/FatFs/src/ff.c **** Public Functions (FatFs API) +3251:Middlewares/Third_Party/FatFs/src/ff.c **** +3252:Middlewares/Third_Party/FatFs/src/ff.c **** ----------------------------------------------------------------------------*/ +3253:Middlewares/Third_Party/FatFs/src/ff.c **** +3254:Middlewares/Third_Party/FatFs/src/ff.c **** +3255:Middlewares/Third_Party/FatFs/src/ff.c **** +3256:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +3257:Middlewares/Third_Party/FatFs/src/ff.c **** /* Mount/Unmount a Logical Drive */ +3258:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +3259:Middlewares/Third_Party/FatFs/src/ff.c **** +3260:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_mount ( +3261:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS* fs, /* Pointer to the file system object (NULL:unmount)*/ +3262:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* path, /* Logical drive number to be mounted/unmounted */ + ARM GAS /tmp/cc2SVLkL.s page 89 + + +3263:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE opt /* Mode option 0:Do not mount (delayed mount), 1:Mount immediately */ +3264:Middlewares/Third_Party/FatFs/src/ff.c **** ) +3265:Middlewares/Third_Party/FatFs/src/ff.c **** { +3266:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *cfs; +3267:Middlewares/Third_Party/FatFs/src/ff.c **** int vol; +3268:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +3269:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR *rp = path; +3270:Middlewares/Third_Party/FatFs/src/ff.c **** +3271:Middlewares/Third_Party/FatFs/src/ff.c **** +3272:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get logical drive number */ +3273:Middlewares/Third_Party/FatFs/src/ff.c **** vol = get_ldnumber(&rp); +3274:Middlewares/Third_Party/FatFs/src/ff.c **** if (vol < 0) return FR_INVALID_DRIVE; +3275:Middlewares/Third_Party/FatFs/src/ff.c **** cfs = FatFs[vol]; /* Pointer to fs object */ +3276:Middlewares/Third_Party/FatFs/src/ff.c **** +3277:Middlewares/Third_Party/FatFs/src/ff.c **** if (cfs) { +3278:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 +3279:Middlewares/Third_Party/FatFs/src/ff.c **** clear_lock(cfs); +3280:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3281:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT /* Discard sync object of the current volume */ +3282:Middlewares/Third_Party/FatFs/src/ff.c **** if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR; +3283:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3284:Middlewares/Third_Party/FatFs/src/ff.c **** cfs->fs_type = 0; /* Clear old fs object */ +3285:Middlewares/Third_Party/FatFs/src/ff.c **** } +3286:Middlewares/Third_Party/FatFs/src/ff.c **** +3287:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs) { +3288:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fs_type = 0; /* Clear new fs object */ +3289:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT /* Create sync object for the new volume */ +3290:Middlewares/Third_Party/FatFs/src/ff.c **** if (!ff_cre_syncobj((BYTE)vol, &fs->sobj)) return FR_INT_ERR; +3291:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3292:Middlewares/Third_Party/FatFs/src/ff.c **** } +3293:Middlewares/Third_Party/FatFs/src/ff.c **** FatFs[vol] = fs; /* Register new fs object */ +3294:Middlewares/Third_Party/FatFs/src/ff.c **** +3295:Middlewares/Third_Party/FatFs/src/ff.c **** if (!fs || opt != 1) return FR_OK; /* Do not mount now, it will be mounted later */ +3296:Middlewares/Third_Party/FatFs/src/ff.c **** +3297:Middlewares/Third_Party/FatFs/src/ff.c **** res = find_volume(&path, &fs, 0); /* Force mounted the volume */ +3298:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); +3299:Middlewares/Third_Party/FatFs/src/ff.c **** } +3300:Middlewares/Third_Party/FatFs/src/ff.c **** +3301:Middlewares/Third_Party/FatFs/src/ff.c **** +3302:Middlewares/Third_Party/FatFs/src/ff.c **** +3303:Middlewares/Third_Party/FatFs/src/ff.c **** +3304:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +3305:Middlewares/Third_Party/FatFs/src/ff.c **** /* Open or Create a File */ +3306:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +3307:Middlewares/Third_Party/FatFs/src/ff.c **** +3308:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_open ( +3309:Middlewares/Third_Party/FatFs/src/ff.c **** FIL* fp, /* Pointer to the blank file object */ +3310:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* path, /* Pointer to the file name */ +3311:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE mode /* Access mode and file open mode flags */ +3312:Middlewares/Third_Party/FatFs/src/ff.c **** ) +3313:Middlewares/Third_Party/FatFs/src/ff.c **** { +3314:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +3315:Middlewares/Third_Party/FatFs/src/ff.c **** DIR dj; +3316:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +3317:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +3318:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD dw, cl, bcs, clst, sc; +3319:Middlewares/Third_Party/FatFs/src/ff.c **** FSIZE_t ofs; + ARM GAS /tmp/cc2SVLkL.s page 90 + + +3320:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3321:Middlewares/Third_Party/FatFs/src/ff.c **** DEF_NAMBUF +3322:Middlewares/Third_Party/FatFs/src/ff.c **** +3323:Middlewares/Third_Party/FatFs/src/ff.c **** +3324:Middlewares/Third_Party/FatFs/src/ff.c **** if (!fp) return FR_INVALID_OBJECT; +3325:Middlewares/Third_Party/FatFs/src/ff.c **** +3326:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get logical drive */ +3327:Middlewares/Third_Party/FatFs/src/ff.c **** mode &= _FS_READONLY ? FA_READ : FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_CREATE_NEW | FA_OPEN_A +3328:Middlewares/Third_Party/FatFs/src/ff.c **** res = find_volume(&path, &fs, mode); +3329:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +3330:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.fs = fs; +3331:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); +3332:Middlewares/Third_Party/FatFs/src/ff.c **** res = follow_path(&dj, path); /* Follow the file path */ +3333:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY /* R/W configuration */ +3334:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +3335:Middlewares/Third_Party/FatFs/src/ff.c **** if (dj.fn[NSFLAG] & NS_NONAME) { /* Origin directory itself? */ +3336:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INVALID_NAME; +3337:Middlewares/Third_Party/FatFs/src/ff.c **** } +3338:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 +3339:Middlewares/Third_Party/FatFs/src/ff.c **** else { +3340:Middlewares/Third_Party/FatFs/src/ff.c **** res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0); +3341:Middlewares/Third_Party/FatFs/src/ff.c **** } +3342:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3343:Middlewares/Third_Party/FatFs/src/ff.c **** } +3344:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create or Open a file */ +3345:Middlewares/Third_Party/FatFs/src/ff.c **** if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) { +3346:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) { /* No file, create new */ +3347:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) { /* There is no file to open, create a new entry */ +3348:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 +3349:Middlewares/Third_Party/FatFs/src/ff.c **** res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES; +3350:Middlewares/Third_Party/FatFs/src/ff.c **** #else +3351:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_register(&dj); +3352:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3353:Middlewares/Third_Party/FatFs/src/ff.c **** } +3354:Middlewares/Third_Party/FatFs/src/ff.c **** mode |= FA_CREATE_ALWAYS; /* File is created */ +3355:Middlewares/Third_Party/FatFs/src/ff.c **** } +3356:Middlewares/Third_Party/FatFs/src/ff.c **** else { /* Any object is already existing */ +3357:Middlewares/Third_Party/FatFs/src/ff.c **** if (dj.obj.attr & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */ +3358:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DENIED; +3359:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +3360:Middlewares/Third_Party/FatFs/src/ff.c **** if (mode & FA_CREATE_NEW) res = FR_EXIST; /* Cannot create as new file */ +3361:Middlewares/Third_Party/FatFs/src/ff.c **** } +3362:Middlewares/Third_Party/FatFs/src/ff.c **** } +3363:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */ +3364:Middlewares/Third_Party/FatFs/src/ff.c **** dw = GET_FATTIME(); +3365:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +3366:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { +3367:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get current allocation info */ +3368:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.fs = fs; +3369:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.sclust = ld_dword(fs->dirbuf + XDIR_FstClus); +3370:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize); +3371:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2; +3372:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.n_frag = 0; +3373:Middlewares/Third_Party/FatFs/src/ff.c **** /* Initialize directory entry block */ +3374:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->dirbuf + XDIR_CrtTime, dw); /* Set created time */ +3375:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbuf[XDIR_CrtTime10] = 0; +3376:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->dirbuf + XDIR_ModTime, dw); /* Set modified time */ + ARM GAS /tmp/cc2SVLkL.s page 91 + + +3377:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbuf[XDIR_ModTime10] = 0; +3378:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbuf[XDIR_Attr] = AM_ARC; /* Reset attribute */ +3379:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->dirbuf + XDIR_FstClus, 0); /* Reset file allocation info */ +3380:Middlewares/Third_Party/FatFs/src/ff.c **** st_qword(fs->dirbuf + XDIR_FileSize, 0); +3381:Middlewares/Third_Party/FatFs/src/ff.c **** st_qword(fs->dirbuf + XDIR_ValidFileSize, 0); +3382:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbuf[XDIR_GenFlags] = 1; +3383:Middlewares/Third_Party/FatFs/src/ff.c **** res = store_xdir(&dj); +3384:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && fp->obj.sclust) { /* Remove the cluster chain if exist */ +3385:Middlewares/Third_Party/FatFs/src/ff.c **** res = remove_chain(&fp->obj, fp->obj.sclust, 0); +3386:Middlewares/Third_Party/FatFs/src/ff.c **** fs->last_clst = fp->obj.sclust - 1; /* Reuse the cluster hole */ +3387:Middlewares/Third_Party/FatFs/src/ff.c **** } +3388:Middlewares/Third_Party/FatFs/src/ff.c **** } else +3389:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3390:Middlewares/Third_Party/FatFs/src/ff.c **** { +3391:Middlewares/Third_Party/FatFs/src/ff.c **** /* Clean directory info */ +3392:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(dj.dir + DIR_CrtTime, dw); /* Set created time */ +3393:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(dj.dir + DIR_ModTime, dw); /* Set modified time */ +3394:Middlewares/Third_Party/FatFs/src/ff.c **** dj.dir[DIR_Attr] = AM_ARC; /* Reset attribute */ +3395:Middlewares/Third_Party/FatFs/src/ff.c **** cl = ld_clust(fs, dj.dir); /* Get cluster chain */ +3396:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dj.dir, 0); /* Reset file allocation info */ +3397:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(dj.dir + DIR_FileSize, 0); +3398:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +3399:Middlewares/Third_Party/FatFs/src/ff.c **** +3400:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl) { /* Remove the cluster chain if exist */ +3401:Middlewares/Third_Party/FatFs/src/ff.c **** dw = fs->winsect; +3402:Middlewares/Third_Party/FatFs/src/ff.c **** res = remove_chain(&dj.obj, cl, 0); +3403:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +3404:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dw); +3405:Middlewares/Third_Party/FatFs/src/ff.c **** fs->last_clst = cl - 1; /* Reuse the cluster hole */ +3406:Middlewares/Third_Party/FatFs/src/ff.c **** } +3407:Middlewares/Third_Party/FatFs/src/ff.c **** } +3408:Middlewares/Third_Party/FatFs/src/ff.c **** } +3409:Middlewares/Third_Party/FatFs/src/ff.c **** } +3410:Middlewares/Third_Party/FatFs/src/ff.c **** } +3411:Middlewares/Third_Party/FatFs/src/ff.c **** else { /* Open an existing file */ +3412:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Following succeeded */ +3413:Middlewares/Third_Party/FatFs/src/ff.c **** if (dj.obj.attr & AM_DIR) { /* It is a directory */ +3414:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_NO_FILE; +3415:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +3416:Middlewares/Third_Party/FatFs/src/ff.c **** if ((mode & FA_WRITE) && (dj.obj.attr & AM_RDO)) { /* R/O violation */ +3417:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DENIED; +3418:Middlewares/Third_Party/FatFs/src/ff.c **** } +3419:Middlewares/Third_Party/FatFs/src/ff.c **** } +3420:Middlewares/Third_Party/FatFs/src/ff.c **** } +3421:Middlewares/Third_Party/FatFs/src/ff.c **** } +3422:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +3423:Middlewares/Third_Party/FatFs/src/ff.c **** if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */ +3424:Middlewares/Third_Party/FatFs/src/ff.c **** mode |= FA_MODIFIED; +3425:Middlewares/Third_Party/FatFs/src/ff.c **** fp->dir_sect = fs->winsect; /* Pointer to the directory entry */ +3426:Middlewares/Third_Party/FatFs/src/ff.c **** fp->dir_ptr = dj.dir; +3427:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 +3428:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0); +3429:Middlewares/Third_Party/FatFs/src/ff.c **** if (!fp->obj.lockid) res = FR_INT_ERR; +3430:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3431:Middlewares/Third_Party/FatFs/src/ff.c **** } +3432:Middlewares/Third_Party/FatFs/src/ff.c **** #else /* R/O configuration */ +3433:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + ARM GAS /tmp/cc2SVLkL.s page 92 + + +3434:Middlewares/Third_Party/FatFs/src/ff.c **** if (dj.fn[NSFLAG] & NS_NONAME) { /* Origin directory itself? */ +3435:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INVALID_NAME; +3436:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +3437:Middlewares/Third_Party/FatFs/src/ff.c **** if (dj.obj.attr & AM_DIR) { /* It is a directory */ +3438:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_NO_FILE; +3439:Middlewares/Third_Party/FatFs/src/ff.c **** } +3440:Middlewares/Third_Party/FatFs/src/ff.c **** } +3441:Middlewares/Third_Party/FatFs/src/ff.c **** } +3442:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3443:Middlewares/Third_Party/FatFs/src/ff.c **** +3444:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +3445:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +3446:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { +3447:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.c_scl = dj.obj.sclust; /* Get containing directory info */ +3448:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.c_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat; +3449:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.c_ofs = dj.blk_ofs; +3450:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.sclust = ld_dword(fs->dirbuf + XDIR_FstClus); /* Get object allocation info */ +3451:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize); +3452:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2; +3453:Middlewares/Third_Party/FatFs/src/ff.c **** } else +3454:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3455:Middlewares/Third_Party/FatFs/src/ff.c **** { +3456:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.sclust = ld_clust(fs, dj.dir); /* Get object allocation info */ +3457:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize); +3458:Middlewares/Third_Party/FatFs/src/ff.c **** } +3459:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FASTSEEK +3460:Middlewares/Third_Party/FatFs/src/ff.c **** fp->cltbl = 0; /* Disable fast seek mode */ +3461:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3462:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.fs = fs; /* Validate the file object */ +3463:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.id = fs->id; +3464:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag = mode; /* Set file access mode */ +3465:Middlewares/Third_Party/FatFs/src/ff.c **** fp->err = 0; /* Clear error flag */ +3466:Middlewares/Third_Party/FatFs/src/ff.c **** fp->sect = 0; /* Invalidate current data sector */ +3467:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = 0; /* Set file pointer top of the file */ +3468:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +3469:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY +3470:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(fp->buf, 0, _MAX_SS); /* Clear sector buffer */ +3471:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3472:Middlewares/Third_Party/FatFs/src/ff.c **** if ((mode & FA_SEEKEND) && fp->obj.objsize > 0) { /* Seek to end of file if FA_OPEN_APPEND is sp +3473:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = fp->obj.objsize; /* Offset to seek */ +3474:Middlewares/Third_Party/FatFs/src/ff.c **** bcs = (DWORD)fs->csize * SS(fs); /* Cluster size in byte */ +3475:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fp->obj.sclust; /* Follow the cluster chain */ +3476:Middlewares/Third_Party/FatFs/src/ff.c **** for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) { +3477:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&fp->obj, clst); +3478:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst <= 1) res = FR_INT_ERR; +3479:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) res = FR_DISK_ERR; +3480:Middlewares/Third_Party/FatFs/src/ff.c **** } +3481:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; +3482:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && ofs % SS(fs)) { /* Fill sector buffer if not on the sector boundary */ +3483:Middlewares/Third_Party/FatFs/src/ff.c **** if ((sc = clust2sect(fs, clst)) == 0) { +3484:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INT_ERR; +3485:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +3486:Middlewares/Third_Party/FatFs/src/ff.c **** fp->sect = sc + (DWORD)(ofs / SS(fs)); +3487:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY +3488:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_read(fs->drv, fp->buf, fp->sect, 1) != RES_OK) res = FR_DISK_ERR; +3489:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3490:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 93 + + +3491:Middlewares/Third_Party/FatFs/src/ff.c **** } +3492:Middlewares/Third_Party/FatFs/src/ff.c **** } +3493:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3494:Middlewares/Third_Party/FatFs/src/ff.c **** } +3495:Middlewares/Third_Party/FatFs/src/ff.c **** +3496:Middlewares/Third_Party/FatFs/src/ff.c **** FREE_NAMBUF(); +3497:Middlewares/Third_Party/FatFs/src/ff.c **** } +3498:Middlewares/Third_Party/FatFs/src/ff.c **** +3499:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) fp->obj.fs = 0; /* Invalidate file object on error */ +3500:Middlewares/Third_Party/FatFs/src/ff.c **** +3501:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); +3502:Middlewares/Third_Party/FatFs/src/ff.c **** } +3503:Middlewares/Third_Party/FatFs/src/ff.c **** +3504:Middlewares/Third_Party/FatFs/src/ff.c **** +3505:Middlewares/Third_Party/FatFs/src/ff.c **** +3506:Middlewares/Third_Party/FatFs/src/ff.c **** +3507:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +3508:Middlewares/Third_Party/FatFs/src/ff.c **** /* Read File */ +3509:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +3510:Middlewares/Third_Party/FatFs/src/ff.c **** +3511:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_read ( +3512:Middlewares/Third_Party/FatFs/src/ff.c **** FIL* fp, /* Pointer to the file object */ +3513:Middlewares/Third_Party/FatFs/src/ff.c **** void* buff, /* Pointer to data buffer */ +3514:Middlewares/Third_Party/FatFs/src/ff.c **** UINT btr, /* Number of bytes to read */ +3515:Middlewares/Third_Party/FatFs/src/ff.c **** UINT* br /* Pointer to number of bytes read */ +3516:Middlewares/Third_Party/FatFs/src/ff.c **** ) +3517:Middlewares/Third_Party/FatFs/src/ff.c **** { +3518:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +3519:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +3520:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clst, sect; +3521:Middlewares/Third_Party/FatFs/src/ff.c **** FSIZE_t remain; +3522:Middlewares/Third_Party/FatFs/src/ff.c **** UINT rcnt, cc, csect; +3523:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE *rbuff = (BYTE*)buff; +3524:Middlewares/Third_Party/FatFs/src/ff.c **** +3525:Middlewares/Third_Party/FatFs/src/ff.c **** +3526:Middlewares/Third_Party/FatFs/src/ff.c **** *br = 0; /* Clear read byte counter */ +3527:Middlewares/Third_Party/FatFs/src/ff.c **** res = validate(&fp->obj, &fs); /* Check validity of the file object */ +3528:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ +3529:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ +3530:Middlewares/Third_Party/FatFs/src/ff.c **** remain = fp->obj.objsize - fp->fptr; +3531:Middlewares/Third_Party/FatFs/src/ff.c **** if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ +3532:Middlewares/Third_Party/FatFs/src/ff.c **** +3533:Middlewares/Third_Party/FatFs/src/ff.c **** for ( ; btr; /* Repeat until all data read */ +3534:Middlewares/Third_Party/FatFs/src/ff.c **** rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) { +3535:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ +3536:Middlewares/Third_Party/FatFs/src/ff.c **** csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ +3537:Middlewares/Third_Party/FatFs/src/ff.c **** if (csect == 0) { /* On the cluster boundary? */ +3538:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr == 0) { /* On the top of the file? */ +3539:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fp->obj.sclust; /* Follow cluster chain from the origin */ +3540:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* Middle or end of the file */ +3541:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FASTSEEK +3542:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->cltbl) { +3543:Middlewares/Third_Party/FatFs/src/ff.c **** clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ +3544:Middlewares/Third_Party/FatFs/src/ff.c **** } else +3545:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3546:Middlewares/Third_Party/FatFs/src/ff.c **** { +3547:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&fp->obj, fp->clust); /* Follow cluster chain on the FAT */ + ARM GAS /tmp/cc2SVLkL.s page 94 + + +3548:Middlewares/Third_Party/FatFs/src/ff.c **** } +3549:Middlewares/Third_Party/FatFs/src/ff.c **** } +3550:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst < 2) ABORT(fs, FR_INT_ERR); +3551:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); +3552:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; /* Update current cluster */ +3553:Middlewares/Third_Party/FatFs/src/ff.c **** } +3554:Middlewares/Third_Party/FatFs/src/ff.c **** sect = clust2sect(fs, fp->clust); /* Get current sector */ +3555:Middlewares/Third_Party/FatFs/src/ff.c **** if (!sect) ABORT(fs, FR_INT_ERR); +3556:Middlewares/Third_Party/FatFs/src/ff.c **** sect += csect; +3557:Middlewares/Third_Party/FatFs/src/ff.c **** cc = btr / SS(fs); /* When remaining bytes >= sector size, */ +3558:Middlewares/Third_Party/FatFs/src/ff.c **** if (cc) { /* Read maximum contiguous sectors directly */ +3559:Middlewares/Third_Party/FatFs/src/ff.c **** if (csect + cc > fs->csize) { /* Clip at cluster boundary */ +3560:Middlewares/Third_Party/FatFs/src/ff.c **** cc = fs->csize - csect; +3561:Middlewares/Third_Party/FatFs/src/ff.c **** } +3562:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_read(fs->drv, rbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR); +3563:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it +3564:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY +3565:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->wflag && fs->winsect - sect < cc) { +3566:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(rbuff + ((fs->winsect - sect) * SS(fs)), fs->win, SS(fs)); +3567:Middlewares/Third_Party/FatFs/src/ff.c **** } +3568:Middlewares/Third_Party/FatFs/src/ff.c **** #else +3569:Middlewares/Third_Party/FatFs/src/ff.c **** if ((fp->flag & FA_DIRTY) && fp->sect - sect < cc) { +3570:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs)); +3571:Middlewares/Third_Party/FatFs/src/ff.c **** } +3572:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3573:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3574:Middlewares/Third_Party/FatFs/src/ff.c **** rcnt = SS(fs) * cc; /* Number of bytes transferred */ +3575:Middlewares/Third_Party/FatFs/src/ff.c **** continue; +3576:Middlewares/Third_Party/FatFs/src/ff.c **** } +3577:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY +3578:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->sect != sect) { /* Load data sector if not in cache */ +3579:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +3580:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ +3581:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); +3582:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; +3583:Middlewares/Third_Party/FatFs/src/ff.c **** } +3584:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3585:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cach +3586:Middlewares/Third_Party/FatFs/src/ff.c **** } +3587:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3588:Middlewares/Third_Party/FatFs/src/ff.c **** fp->sect = sect; +3589:Middlewares/Third_Party/FatFs/src/ff.c **** } +3590:Middlewares/Third_Party/FatFs/src/ff.c **** rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes left in the sector */ +3591:Middlewares/Third_Party/FatFs/src/ff.c **** if (rcnt > btr) rcnt = btr; /* Clip it by btr if needed */ +3592:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY +3593:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */ +3594:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(rbuff, fs->win + fp->fptr % SS(fs), rcnt); /* Extract partial sector */ +3595:Middlewares/Third_Party/FatFs/src/ff.c **** #else +3596:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(rbuff, fp->buf + fp->fptr % SS(fs), rcnt); /* Extract partial sector */ +3597:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3598:Middlewares/Third_Party/FatFs/src/ff.c **** } +3599:Middlewares/Third_Party/FatFs/src/ff.c **** +3600:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, FR_OK); +3601:Middlewares/Third_Party/FatFs/src/ff.c **** } +3602:Middlewares/Third_Party/FatFs/src/ff.c **** +3603:Middlewares/Third_Party/FatFs/src/ff.c **** +3604:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 95 + + +3605:Middlewares/Third_Party/FatFs/src/ff.c **** +3606:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +3607:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +3608:Middlewares/Third_Party/FatFs/src/ff.c **** /* Write File */ +3609:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +3610:Middlewares/Third_Party/FatFs/src/ff.c **** +3611:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_write ( +3612:Middlewares/Third_Party/FatFs/src/ff.c **** FIL* fp, /* Pointer to the file object */ +3613:Middlewares/Third_Party/FatFs/src/ff.c **** const void* buff, /* Pointer to the data to be written */ +3614:Middlewares/Third_Party/FatFs/src/ff.c **** UINT btw, /* Number of bytes to write */ +3615:Middlewares/Third_Party/FatFs/src/ff.c **** UINT* bw /* Pointer to number of bytes written */ +3616:Middlewares/Third_Party/FatFs/src/ff.c **** ) +3617:Middlewares/Third_Party/FatFs/src/ff.c **** { +3618:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +3619:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +3620:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clst, sect; +3621:Middlewares/Third_Party/FatFs/src/ff.c **** UINT wcnt, cc, csect; +3622:Middlewares/Third_Party/FatFs/src/ff.c **** const BYTE *wbuff = (const BYTE*)buff; +3623:Middlewares/Third_Party/FatFs/src/ff.c **** +3624:Middlewares/Third_Party/FatFs/src/ff.c **** +3625:Middlewares/Third_Party/FatFs/src/ff.c **** *bw = 0; /* Clear write byte counter */ +3626:Middlewares/Third_Party/FatFs/src/ff.c **** res = validate(&fp->obj, &fs); /* Check validity of the file object */ +3627:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ +3628:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ +3629:Middlewares/Third_Party/FatFs/src/ff.c **** +3630:Middlewares/Third_Party/FatFs/src/ff.c **** /* Check fptr wrap-around (file size cannot reach 4GiB on FATxx) */ +3631:Middlewares/Third_Party/FatFs/src/ff.c **** if ((!_FS_EXFAT || fs->fs_type != FS_EXFAT) && (DWORD)(fp->fptr + btw) < (DWORD)fp->fptr) { +3632:Middlewares/Third_Party/FatFs/src/ff.c **** btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr); +3633:Middlewares/Third_Party/FatFs/src/ff.c **** } +3634:Middlewares/Third_Party/FatFs/src/ff.c **** +3635:Middlewares/Third_Party/FatFs/src/ff.c **** for ( ; btw; /* Repeat until all data written */ +3636:Middlewares/Third_Party/FatFs/src/ff.c **** wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp-> +3637:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ +3638:Middlewares/Third_Party/FatFs/src/ff.c **** csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1); /* Sector offset in the cluster */ +3639:Middlewares/Third_Party/FatFs/src/ff.c **** if (csect == 0) { /* On the cluster boundary? */ +3640:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr == 0) { /* On the top of the file? */ +3641:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fp->obj.sclust; /* Follow from the origin */ +3642:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0) { /* If no cluster is allocated, */ +3643:Middlewares/Third_Party/FatFs/src/ff.c **** clst = create_chain(&fp->obj, 0); /* create a new cluster chain */ +3644:Middlewares/Third_Party/FatFs/src/ff.c **** } +3645:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* On the middle or end of the file */ +3646:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FASTSEEK +3647:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->cltbl) { +3648:Middlewares/Third_Party/FatFs/src/ff.c **** clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ +3649:Middlewares/Third_Party/FatFs/src/ff.c **** } else +3650:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3651:Middlewares/Third_Party/FatFs/src/ff.c **** { +3652:Middlewares/Third_Party/FatFs/src/ff.c **** clst = create_chain(&fp->obj, fp->clust); /* Follow or stretch cluster chain on the FAT */ +3653:Middlewares/Third_Party/FatFs/src/ff.c **** } +3654:Middlewares/Third_Party/FatFs/src/ff.c **** } +3655:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ +3656:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 1) ABORT(fs, FR_INT_ERR); +3657:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); +3658:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; /* Update current cluster */ +3659:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->obj.sclust == 0) fp->obj.sclust = clst; /* Set start cluster if the first write */ +3660:Middlewares/Third_Party/FatFs/src/ff.c **** } +3661:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY + ARM GAS /tmp/cc2SVLkL.s page 96 + + +3662:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->winsect == fp->sect && sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Write-back s +3663:Middlewares/Third_Party/FatFs/src/ff.c **** #else +3664:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->flag & FA_DIRTY) { /* Write-back sector cache */ +3665:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); +3666:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; +3667:Middlewares/Third_Party/FatFs/src/ff.c **** } +3668:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3669:Middlewares/Third_Party/FatFs/src/ff.c **** sect = clust2sect(fs, fp->clust); /* Get current sector */ +3670:Middlewares/Third_Party/FatFs/src/ff.c **** if (!sect) ABORT(fs, FR_INT_ERR); +3671:Middlewares/Third_Party/FatFs/src/ff.c **** sect += csect; +3672:Middlewares/Third_Party/FatFs/src/ff.c **** cc = btw / SS(fs); /* When remaining bytes >= sector size, */ +3673:Middlewares/Third_Party/FatFs/src/ff.c **** if (cc) { /* Write maximum contiguous sectors directly */ +3674:Middlewares/Third_Party/FatFs/src/ff.c **** if (csect + cc > fs->csize) { /* Clip at cluster boundary */ +3675:Middlewares/Third_Party/FatFs/src/ff.c **** cc = fs->csize - csect; +3676:Middlewares/Third_Party/FatFs/src/ff.c **** } +3677:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, wbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR); +3678:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 2 +3679:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY +3680:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct writ +3681:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(fs->win, wbuff + ((fs->winsect - sect) * SS(fs)), SS(fs)); +3682:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 0; +3683:Middlewares/Third_Party/FatFs/src/ff.c **** } +3684:Middlewares/Third_Party/FatFs/src/ff.c **** #else +3685:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->sect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write * +3686:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs)); +3687:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; +3688:Middlewares/Third_Party/FatFs/src/ff.c **** } +3689:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3690:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3691:Middlewares/Third_Party/FatFs/src/ff.c **** wcnt = SS(fs) * cc; /* Number of bytes transferred */ +3692:Middlewares/Third_Party/FatFs/src/ff.c **** continue; +3693:Middlewares/Third_Party/FatFs/src/ff.c **** } +3694:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY +3695:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr >= fp->obj.objsize) { /* Avoid silly cache filling on the growing edge */ +3696:Middlewares/Third_Party/FatFs/src/ff.c **** if (sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR); +3697:Middlewares/Third_Party/FatFs/src/ff.c **** fs->winsect = sect; +3698:Middlewares/Third_Party/FatFs/src/ff.c **** } +3699:Middlewares/Third_Party/FatFs/src/ff.c **** #else +3700:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->sect != sect && /* Fill sector cache with file data */ +3701:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr < fp->obj.objsize && +3702:Middlewares/Third_Party/FatFs/src/ff.c **** disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) { +3703:Middlewares/Third_Party/FatFs/src/ff.c **** ABORT(fs, FR_DISK_ERR); +3704:Middlewares/Third_Party/FatFs/src/ff.c **** } +3705:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3706:Middlewares/Third_Party/FatFs/src/ff.c **** fp->sect = sect; +3707:Middlewares/Third_Party/FatFs/src/ff.c **** } +3708:Middlewares/Third_Party/FatFs/src/ff.c **** wcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes left in the sector */ +3709:Middlewares/Third_Party/FatFs/src/ff.c **** if (wcnt > btw) wcnt = btw; /* Clip it by btw if needed */ +3710:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY +3711:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */ +3712:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(fs->win + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */ +3713:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +3714:Middlewares/Third_Party/FatFs/src/ff.c **** #else +3715:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(fp->buf + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */ +3716:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag |= FA_DIRTY; +3717:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3718:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 97 + + +3719:Middlewares/Third_Party/FatFs/src/ff.c **** +3720:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag |= FA_MODIFIED; /* Set file change flag */ +3721:Middlewares/Third_Party/FatFs/src/ff.c **** +3722:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, FR_OK); +3723:Middlewares/Third_Party/FatFs/src/ff.c **** } +3724:Middlewares/Third_Party/FatFs/src/ff.c **** +3725:Middlewares/Third_Party/FatFs/src/ff.c **** +3726:Middlewares/Third_Party/FatFs/src/ff.c **** +3727:Middlewares/Third_Party/FatFs/src/ff.c **** +3728:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +3729:Middlewares/Third_Party/FatFs/src/ff.c **** /* Synchronize the File */ +3730:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +3731:Middlewares/Third_Party/FatFs/src/ff.c **** +3732:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_sync ( +3733:Middlewares/Third_Party/FatFs/src/ff.c **** FIL* fp /* Pointer to the file object */ +3734:Middlewares/Third_Party/FatFs/src/ff.c **** ) +3735:Middlewares/Third_Party/FatFs/src/ff.c **** { +3736:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +3737:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +3738:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD tm; +3739:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE *dir; +3740:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +3741:Middlewares/Third_Party/FatFs/src/ff.c **** DIR dj; +3742:Middlewares/Third_Party/FatFs/src/ff.c **** DEF_NAMBUF +3743:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3744:Middlewares/Third_Party/FatFs/src/ff.c **** +3745:Middlewares/Third_Party/FatFs/src/ff.c **** res = validate(&fp->obj, &fs); /* Check validity of the file object */ +3746:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +3747:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->flag & FA_MODIFIED) { /* Is there any change to the file? */ +3748:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY +3749:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->flag & FA_DIRTY) { /* Write-back cached data if needed */ +3750:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR); +3751:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; +3752:Middlewares/Third_Party/FatFs/src/ff.c **** } +3753:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3754:Middlewares/Third_Party/FatFs/src/ff.c **** /* Update the directory entry */ +3755:Middlewares/Third_Party/FatFs/src/ff.c **** tm = GET_FATTIME(); /* Modified time */ +3756:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +3757:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { +3758:Middlewares/Third_Party/FatFs/src/ff.c **** res = fill_first_frag(&fp->obj); /* Fill first fragment on the FAT if needed */ +3759:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +3760:Middlewares/Third_Party/FatFs/src/ff.c **** res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF); /* Fill last fragment on the FAT if nee +3761:Middlewares/Third_Party/FatFs/src/ff.c **** } +3762:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +3763:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); +3764:Middlewares/Third_Party/FatFs/src/ff.c **** res = load_obj_dir(&dj, &fp->obj); /* Load directory entry block */ +3765:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +3766:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbuf[XDIR_Attr] |= AM_ARC; /* Set archive bit */ +3767:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbuf[XDIR_GenFlags] = fp->obj.stat | 1; /* Update file allocation info */ +3768:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->dirbuf + XDIR_FstClus, fp->obj.sclust); +3769:Middlewares/Third_Party/FatFs/src/ff.c **** st_qword(fs->dirbuf + XDIR_FileSize, fp->obj.objsize); +3770:Middlewares/Third_Party/FatFs/src/ff.c **** st_qword(fs->dirbuf + XDIR_ValidFileSize, fp->obj.objsize); +3771:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->dirbuf + XDIR_ModTime, tm); /* Update modified time */ +3772:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbuf[XDIR_ModTime10] = 0; +3773:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->dirbuf + XDIR_AccTime, 0); +3774:Middlewares/Third_Party/FatFs/src/ff.c **** res = store_xdir(&dj); /* Restore it to the directory */ +3775:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + ARM GAS /tmp/cc2SVLkL.s page 98 + + +3776:Middlewares/Third_Party/FatFs/src/ff.c **** res = sync_fs(fs); +3777:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_MODIFIED; +3778:Middlewares/Third_Party/FatFs/src/ff.c **** } +3779:Middlewares/Third_Party/FatFs/src/ff.c **** } +3780:Middlewares/Third_Party/FatFs/src/ff.c **** FREE_NAMBUF(); +3781:Middlewares/Third_Party/FatFs/src/ff.c **** } +3782:Middlewares/Third_Party/FatFs/src/ff.c **** } else +3783:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3784:Middlewares/Third_Party/FatFs/src/ff.c **** { +3785:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, fp->dir_sect); +3786:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +3787:Middlewares/Third_Party/FatFs/src/ff.c **** dir = fp->dir_ptr; +3788:Middlewares/Third_Party/FatFs/src/ff.c **** dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ +3789:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fp->obj.fs, dir, fp->obj.sclust); /* Update file allocation info */ +3790:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize); /* Update file size */ +3791:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(dir + DIR_ModTime, tm); /* Update modified time */ +3792:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(dir + DIR_LstAccDate, 0); +3793:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +3794:Middlewares/Third_Party/FatFs/src/ff.c **** res = sync_fs(fs); /* Restore it to the directory */ +3795:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_MODIFIED; +3796:Middlewares/Third_Party/FatFs/src/ff.c **** } +3797:Middlewares/Third_Party/FatFs/src/ff.c **** } +3798:Middlewares/Third_Party/FatFs/src/ff.c **** } +3799:Middlewares/Third_Party/FatFs/src/ff.c **** } +3800:Middlewares/Third_Party/FatFs/src/ff.c **** +3801:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); +3802:Middlewares/Third_Party/FatFs/src/ff.c **** } +3803:Middlewares/Third_Party/FatFs/src/ff.c **** +3804:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* !_FS_READONLY */ +3805:Middlewares/Third_Party/FatFs/src/ff.c **** +3806:Middlewares/Third_Party/FatFs/src/ff.c **** +3807:Middlewares/Third_Party/FatFs/src/ff.c **** +3808:Middlewares/Third_Party/FatFs/src/ff.c **** +3809:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +3810:Middlewares/Third_Party/FatFs/src/ff.c **** /* Close File */ +3811:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +3812:Middlewares/Third_Party/FatFs/src/ff.c **** +3813:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_close ( +3814:Middlewares/Third_Party/FatFs/src/ff.c **** FIL* fp /* Pointer to the file object to be closed */ +3815:Middlewares/Third_Party/FatFs/src/ff.c **** ) +3816:Middlewares/Third_Party/FatFs/src/ff.c **** { +3817:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +3818:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +3819:Middlewares/Third_Party/FatFs/src/ff.c **** +3820:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +3821:Middlewares/Third_Party/FatFs/src/ff.c **** res = f_sync(fp); /* Flush cached data */ +3822:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) +3823:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3824:Middlewares/Third_Party/FatFs/src/ff.c **** { +3825:Middlewares/Third_Party/FatFs/src/ff.c **** res = validate(&fp->obj, &fs); /* Lock volume */ +3826:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +3827:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 +3828:Middlewares/Third_Party/FatFs/src/ff.c **** res = dec_lock(fp->obj.lockid); /* Decrement file open counter */ +3829:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) +3830:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3831:Middlewares/Third_Party/FatFs/src/ff.c **** { +3832:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.fs = 0; /* Invalidate file object */ + ARM GAS /tmp/cc2SVLkL.s page 99 + + +3833:Middlewares/Third_Party/FatFs/src/ff.c **** } +3834:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT +3835:Middlewares/Third_Party/FatFs/src/ff.c **** unlock_fs(fs, FR_OK); /* Unlock volume */ +3836:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3837:Middlewares/Third_Party/FatFs/src/ff.c **** } +3838:Middlewares/Third_Party/FatFs/src/ff.c **** } +3839:Middlewares/Third_Party/FatFs/src/ff.c **** return res; +3840:Middlewares/Third_Party/FatFs/src/ff.c **** } +3841:Middlewares/Third_Party/FatFs/src/ff.c **** +3842:Middlewares/Third_Party/FatFs/src/ff.c **** +3843:Middlewares/Third_Party/FatFs/src/ff.c **** +3844:Middlewares/Third_Party/FatFs/src/ff.c **** +3845:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH >= 1 +3846:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +3847:Middlewares/Third_Party/FatFs/src/ff.c **** /* Change Current Directory or Current Drive, Get Current Directory */ +3848:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +3849:Middlewares/Third_Party/FatFs/src/ff.c **** +3850:Middlewares/Third_Party/FatFs/src/ff.c **** #if _VOLUMES >= 2 +3851:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_chdrive ( +3852:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* path /* Drive number */ +3853:Middlewares/Third_Party/FatFs/src/ff.c **** ) +3854:Middlewares/Third_Party/FatFs/src/ff.c **** { +3855:Middlewares/Third_Party/FatFs/src/ff.c **** int vol; +3856:Middlewares/Third_Party/FatFs/src/ff.c **** +3857:Middlewares/Third_Party/FatFs/src/ff.c **** +3858:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get logical drive number */ +3859:Middlewares/Third_Party/FatFs/src/ff.c **** vol = get_ldnumber(&path); +3860:Middlewares/Third_Party/FatFs/src/ff.c **** if (vol < 0) return FR_INVALID_DRIVE; +3861:Middlewares/Third_Party/FatFs/src/ff.c **** +3862:Middlewares/Third_Party/FatFs/src/ff.c **** CurrVol = (BYTE)vol; /* Set it as current volume */ +3863:Middlewares/Third_Party/FatFs/src/ff.c **** +3864:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_OK; +3865:Middlewares/Third_Party/FatFs/src/ff.c **** } +3866:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3867:Middlewares/Third_Party/FatFs/src/ff.c **** +3868:Middlewares/Third_Party/FatFs/src/ff.c **** +3869:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_chdir ( +3870:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* path /* Pointer to the directory path */ +3871:Middlewares/Third_Party/FatFs/src/ff.c **** ) +3872:Middlewares/Third_Party/FatFs/src/ff.c **** { +3873:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +3874:Middlewares/Third_Party/FatFs/src/ff.c **** DIR dj; +3875:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +3876:Middlewares/Third_Party/FatFs/src/ff.c **** DEF_NAMBUF +3877:Middlewares/Third_Party/FatFs/src/ff.c **** +3878:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get logical drive */ +3879:Middlewares/Third_Party/FatFs/src/ff.c **** res = find_volume(&path, &fs, 0); +3880:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +3881:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.fs = fs; +3882:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); +3883:Middlewares/Third_Party/FatFs/src/ff.c **** res = follow_path(&dj, path); /* Follow the path */ +3884:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Follow completed */ +3885:Middlewares/Third_Party/FatFs/src/ff.c **** if (dj.fn[NSFLAG] & NS_NONAME) { +3886:Middlewares/Third_Party/FatFs/src/ff.c **** fs->cdir = dj.obj.sclust; /* It is the start directory itself */ +3887:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +3888:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { +3889:Middlewares/Third_Party/FatFs/src/ff.c **** fs->cdc_scl = dj.obj.c_scl; + ARM GAS /tmp/cc2SVLkL.s page 100 + + +3890:Middlewares/Third_Party/FatFs/src/ff.c **** fs->cdc_size = dj.obj.c_size; +3891:Middlewares/Third_Party/FatFs/src/ff.c **** fs->cdc_ofs = dj.obj.c_ofs; +3892:Middlewares/Third_Party/FatFs/src/ff.c **** } +3893:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3894:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +3895:Middlewares/Third_Party/FatFs/src/ff.c **** if (dj.obj.attr & AM_DIR) { /* It is a sub-directory */ +3896:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +3897:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { +3898:Middlewares/Third_Party/FatFs/src/ff.c **** fs->cdir = ld_dword(fs->dirbuf + XDIR_FstClus); /* Sub-directory cluster */ +3899:Middlewares/Third_Party/FatFs/src/ff.c **** fs->cdc_scl = dj.obj.sclust; /* Save containing directory information */ +3900:Middlewares/Third_Party/FatFs/src/ff.c **** fs->cdc_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat; +3901:Middlewares/Third_Party/FatFs/src/ff.c **** fs->cdc_ofs = dj.blk_ofs; +3902:Middlewares/Third_Party/FatFs/src/ff.c **** } else +3903:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3904:Middlewares/Third_Party/FatFs/src/ff.c **** { +3905:Middlewares/Third_Party/FatFs/src/ff.c **** fs->cdir = ld_clust(fs, dj.dir); /* Sub-directory cluster */ +3906:Middlewares/Third_Party/FatFs/src/ff.c **** } +3907:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +3908:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_NO_PATH; /* Reached but a file */ +3909:Middlewares/Third_Party/FatFs/src/ff.c **** } +3910:Middlewares/Third_Party/FatFs/src/ff.c **** } +3911:Middlewares/Third_Party/FatFs/src/ff.c **** } +3912:Middlewares/Third_Party/FatFs/src/ff.c **** FREE_NAMBUF(); +3913:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) res = FR_NO_PATH; +3914:Middlewares/Third_Party/FatFs/src/ff.c **** } +3915:Middlewares/Third_Party/FatFs/src/ff.c **** +3916:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); +3917:Middlewares/Third_Party/FatFs/src/ff.c **** } +3918:Middlewares/Third_Party/FatFs/src/ff.c **** +3919:Middlewares/Third_Party/FatFs/src/ff.c **** +3920:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH >= 2 +3921:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_getcwd ( +3922:Middlewares/Third_Party/FatFs/src/ff.c **** TCHAR* buff, /* Pointer to the directory path */ +3923:Middlewares/Third_Party/FatFs/src/ff.c **** UINT len /* Size of path */ +3924:Middlewares/Third_Party/FatFs/src/ff.c **** ) +3925:Middlewares/Third_Party/FatFs/src/ff.c **** { +3926:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +3927:Middlewares/Third_Party/FatFs/src/ff.c **** DIR dj; +3928:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +3929:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i, n; +3930:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD ccl; +3931:Middlewares/Third_Party/FatFs/src/ff.c **** TCHAR *tp; +3932:Middlewares/Third_Party/FatFs/src/ff.c **** FILINFO fno; +3933:Middlewares/Third_Party/FatFs/src/ff.c **** DEF_NAMBUF +3934:Middlewares/Third_Party/FatFs/src/ff.c **** +3935:Middlewares/Third_Party/FatFs/src/ff.c **** +3936:Middlewares/Third_Party/FatFs/src/ff.c **** *buff = 0; +3937:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get logical drive */ +3938:Middlewares/Third_Party/FatFs/src/ff.c **** res = find_volume((const TCHAR**)&buff, &fs, 0); /* Get current volume */ +3939:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +3940:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.fs = fs; +3941:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); +3942:Middlewares/Third_Party/FatFs/src/ff.c **** i = len; /* Bottom of buffer (directory stack base) */ +3943:Middlewares/Third_Party/FatFs/src/ff.c **** if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { /* (Cannot do getcwd on exFAT and returns root path) +3944:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.sclust = fs->cdir; /* Start to follow upper directory from current directory */ +3945:Middlewares/Third_Party/FatFs/src/ff.c **** while ((ccl = dj.obj.sclust) != 0) { /* Repeat while current directory is a sub-directory */ +3946:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(&dj, 1 * SZDIRE); /* Get parent directory */ + ARM GAS /tmp/cc2SVLkL.s page 101 + + +3947:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +3948:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dj.sect); +3949:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +3950:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.sclust = ld_clust(fs, dj.dir); /* Goto parent directory */ +3951:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(&dj, 0); +3952:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +3953:Middlewares/Third_Party/FatFs/src/ff.c **** do { /* Find the entry links to the child directory */ +3954:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_read(&dj, 0); +3955:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +3956:Middlewares/Third_Party/FatFs/src/ff.c **** if (ccl == ld_clust(fs, dj.dir)) break; /* Found the entry */ +3957:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_next(&dj, 0); +3958:Middlewares/Third_Party/FatFs/src/ff.c **** } while (res == FR_OK); +3959:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */ +3960:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +3961:Middlewares/Third_Party/FatFs/src/ff.c **** get_fileinfo(&dj, &fno); /* Get the directory name and push it to the buffer */ +3962:Middlewares/Third_Party/FatFs/src/ff.c **** for (n = 0; fno.fname[n]; n++) ; +3963:Middlewares/Third_Party/FatFs/src/ff.c **** if (i < n + 3) { +3964:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_NOT_ENOUGH_CORE; break; +3965:Middlewares/Third_Party/FatFs/src/ff.c **** } +3966:Middlewares/Third_Party/FatFs/src/ff.c **** while (n) buff[--i] = fno.fname[--n]; +3967:Middlewares/Third_Party/FatFs/src/ff.c **** buff[--i] = '/'; +3968:Middlewares/Third_Party/FatFs/src/ff.c **** } +3969:Middlewares/Third_Party/FatFs/src/ff.c **** } +3970:Middlewares/Third_Party/FatFs/src/ff.c **** tp = buff; +3971:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +3972:Middlewares/Third_Party/FatFs/src/ff.c **** #if _VOLUMES >= 2 +3973:Middlewares/Third_Party/FatFs/src/ff.c **** *tp++ = '0' + CurrVol; /* Put drive number */ +3974:Middlewares/Third_Party/FatFs/src/ff.c **** *tp++ = ':'; +3975:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +3976:Middlewares/Third_Party/FatFs/src/ff.c **** if (i == len) { /* Root-directory */ +3977:Middlewares/Third_Party/FatFs/src/ff.c **** *tp++ = '/'; +3978:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* Sub-directroy */ +3979:Middlewares/Third_Party/FatFs/src/ff.c **** do /* Add stacked path str */ +3980:Middlewares/Third_Party/FatFs/src/ff.c **** *tp++ = buff[i++]; +3981:Middlewares/Third_Party/FatFs/src/ff.c **** while (i < len); +3982:Middlewares/Third_Party/FatFs/src/ff.c **** } +3983:Middlewares/Third_Party/FatFs/src/ff.c **** } +3984:Middlewares/Third_Party/FatFs/src/ff.c **** *tp = 0; +3985:Middlewares/Third_Party/FatFs/src/ff.c **** FREE_NAMBUF(); +3986:Middlewares/Third_Party/FatFs/src/ff.c **** } +3987:Middlewares/Third_Party/FatFs/src/ff.c **** +3988:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); +3989:Middlewares/Third_Party/FatFs/src/ff.c **** } +3990:Middlewares/Third_Party/FatFs/src/ff.c **** +3991:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _FS_RPATH >= 2 */ +3992:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _FS_RPATH >= 1 */ +3993:Middlewares/Third_Party/FatFs/src/ff.c **** +3994:Middlewares/Third_Party/FatFs/src/ff.c **** +3995:Middlewares/Third_Party/FatFs/src/ff.c **** +3996:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 2 +3997:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +3998:Middlewares/Third_Party/FatFs/src/ff.c **** /* Seek File R/W Pointer */ +3999:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4000:Middlewares/Third_Party/FatFs/src/ff.c **** +4001:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_lseek ( +4002:Middlewares/Third_Party/FatFs/src/ff.c **** FIL* fp, /* Pointer to the file object */ +4003:Middlewares/Third_Party/FatFs/src/ff.c **** FSIZE_t ofs /* File pointer from top of file */ + ARM GAS /tmp/cc2SVLkL.s page 102 + + +4004:Middlewares/Third_Party/FatFs/src/ff.c **** ) +4005:Middlewares/Third_Party/FatFs/src/ff.c **** { +4006:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +4007:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +4008:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clst, bcs, nsect; +4009:Middlewares/Third_Party/FatFs/src/ff.c **** FSIZE_t ifptr; +4010:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FASTSEEK +4011:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl; +4012:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4013:Middlewares/Third_Party/FatFs/src/ff.c **** +4014:Middlewares/Third_Party/FatFs/src/ff.c **** res = validate(&fp->obj, &fs); /* Check validity of the file object */ +4015:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) res = (FRESULT)fp->err; +4016:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT && !_FS_READONLY +4017:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && fs->fs_type == FS_EXFAT) { +4018:Middlewares/Third_Party/FatFs/src/ff.c **** res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF); /* Fill last fragment on the FAT if needed +4019:Middlewares/Third_Party/FatFs/src/ff.c **** } +4020:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4021:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) LEAVE_FF(fs, res); +4022:Middlewares/Third_Party/FatFs/src/ff.c **** +4023:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FASTSEEK +4024:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->cltbl) { /* Fast seek */ +4025:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs == CREATE_LINKMAP) { /* Create CLMT */ +4026:Middlewares/Third_Party/FatFs/src/ff.c **** tbl = fp->cltbl; +4027:Middlewares/Third_Party/FatFs/src/ff.c **** tlen = *tbl++; ulen = 2; /* Given table size and required table size */ +4028:Middlewares/Third_Party/FatFs/src/ff.c **** cl = fp->obj.sclust; /* Origin of the chain */ +4029:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl) { +4030:Middlewares/Third_Party/FatFs/src/ff.c **** do { +4031:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get a fragment */ +4032:Middlewares/Third_Party/FatFs/src/ff.c **** tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */ +4033:Middlewares/Third_Party/FatFs/src/ff.c **** do { +4034:Middlewares/Third_Party/FatFs/src/ff.c **** pcl = cl; ncl++; +4035:Middlewares/Third_Party/FatFs/src/ff.c **** cl = get_fat(&fp->obj, cl); +4036:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl <= 1) ABORT(fs, FR_INT_ERR); +4037:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); +4038:Middlewares/Third_Party/FatFs/src/ff.c **** } while (cl == pcl + 1); +4039:Middlewares/Third_Party/FatFs/src/ff.c **** if (ulen <= tlen) { /* Store the length and top of the fragment */ +4040:Middlewares/Third_Party/FatFs/src/ff.c **** *tbl++ = ncl; *tbl++ = tcl; +4041:Middlewares/Third_Party/FatFs/src/ff.c **** } +4042:Middlewares/Third_Party/FatFs/src/ff.c **** } while (cl < fs->n_fatent); /* Repeat until end of chain */ +4043:Middlewares/Third_Party/FatFs/src/ff.c **** } +4044:Middlewares/Third_Party/FatFs/src/ff.c **** *fp->cltbl = ulen; /* Number of items used */ +4045:Middlewares/Third_Party/FatFs/src/ff.c **** if (ulen <= tlen) { +4046:Middlewares/Third_Party/FatFs/src/ff.c **** *tbl = 0; /* Terminate table */ +4047:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +4048:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */ +4049:Middlewares/Third_Party/FatFs/src/ff.c **** } +4050:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* Fast seek */ +4051:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs > fp->obj.objsize) ofs = fp->obj.objsize; /* Clip offset at the file size */ +4052:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = ofs; /* Set file pointer */ +4053:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs) { +4054:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clmt_clust(fp, ofs - 1); +4055:Middlewares/Third_Party/FatFs/src/ff.c **** dsc = clust2sect(fs, fp->clust); +4056:Middlewares/Third_Party/FatFs/src/ff.c **** if (!dsc) ABORT(fs, FR_INT_ERR); +4057:Middlewares/Third_Party/FatFs/src/ff.c **** dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1); +4058:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) && dsc != fp->sect) { /* Refill sector cache if needed */ +4059:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY +4060:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + ARM GAS /tmp/cc2SVLkL.s page 103 + + +4061:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ +4062:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); +4063:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; +4064:Middlewares/Third_Party/FatFs/src/ff.c **** } +4065:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4066:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_read(fs->drv, fp->buf, dsc, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Load current sec +4067:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4068:Middlewares/Third_Party/FatFs/src/ff.c **** fp->sect = dsc; +4069:Middlewares/Third_Party/FatFs/src/ff.c **** } +4070:Middlewares/Third_Party/FatFs/src/ff.c **** } +4071:Middlewares/Third_Party/FatFs/src/ff.c **** } +4072:Middlewares/Third_Party/FatFs/src/ff.c **** } else +4073:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4074:Middlewares/Third_Party/FatFs/src/ff.c **** +4075:Middlewares/Third_Party/FatFs/src/ff.c **** /* Normal Seek */ +4076:Middlewares/Third_Party/FatFs/src/ff.c **** { +4077:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +4078:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type != FS_EXFAT && ofs >= 0x100000000) ofs = 0xFFFFFFFF; /* Clip at 4GiB-1 if at FATx +4079:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4080:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs > fp->obj.objsize && (_FS_READONLY || !(fp->flag & FA_WRITE))) { /* In read-only mode, cl +4081:Middlewares/Third_Party/FatFs/src/ff.c **** ofs = fp->obj.objsize; +4082:Middlewares/Third_Party/FatFs/src/ff.c **** } +4083:Middlewares/Third_Party/FatFs/src/ff.c **** ifptr = fp->fptr; +4084:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = nsect = 0; +4085:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs) { +4086:Middlewares/Third_Party/FatFs/src/ff.c **** bcs = (DWORD)fs->csize * SS(fs); /* Cluster size (byte) */ +4087:Middlewares/Third_Party/FatFs/src/ff.c **** if (ifptr > 0 && +4088:Middlewares/Third_Party/FatFs/src/ff.c **** (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ +4089:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1); /* start from the current cluster */ +4090:Middlewares/Third_Party/FatFs/src/ff.c **** ofs -= fp->fptr; +4091:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fp->clust; +4092:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* When seek to back cluster, */ +4093:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fp->obj.sclust; /* start from the first cluster */ +4094:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +4095:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0) { /* If no cluster chain, create a new chain */ +4096:Middlewares/Third_Party/FatFs/src/ff.c **** clst = create_chain(&fp->obj, 0); +4097:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 1) ABORT(fs, FR_INT_ERR); +4098:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); +4099:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.sclust = clst; +4100:Middlewares/Third_Party/FatFs/src/ff.c **** } +4101:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4102:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; +4103:Middlewares/Third_Party/FatFs/src/ff.c **** } +4104:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst != 0) { +4105:Middlewares/Third_Party/FatFs/src/ff.c **** while (ofs > bcs) { /* Cluster following loop */ +4106:Middlewares/Third_Party/FatFs/src/ff.c **** ofs -= bcs; fp->fptr += bcs; +4107:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +4108:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ +4109:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_EXFAT && fp->fptr > fp->obj.objsize) { /* No FAT chain object needs correct objsize t +4110:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.objsize = fp->fptr; +4111:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag |= FA_MODIFIED; +4112:Middlewares/Third_Party/FatFs/src/ff.c **** } +4113:Middlewares/Third_Party/FatFs/src/ff.c **** clst = create_chain(&fp->obj, clst); /* Follow chain with forceed stretch */ +4114:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0) { /* Clip file size in case of disk full */ +4115:Middlewares/Third_Party/FatFs/src/ff.c **** ofs = 0; break; +4116:Middlewares/Third_Party/FatFs/src/ff.c **** } +4117:Middlewares/Third_Party/FatFs/src/ff.c **** } else + ARM GAS /tmp/cc2SVLkL.s page 104 + + +4118:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4119:Middlewares/Third_Party/FatFs/src/ff.c **** { +4120:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&fp->obj, clst); /* Follow cluster chain if not in write mode */ +4121:Middlewares/Third_Party/FatFs/src/ff.c **** } +4122:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); +4123:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR); +4124:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; +4125:Middlewares/Third_Party/FatFs/src/ff.c **** } +4126:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr += ofs; +4127:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs % SS(fs)) { +4128:Middlewares/Third_Party/FatFs/src/ff.c **** nsect = clust2sect(fs, clst); /* Current sector */ +4129:Middlewares/Third_Party/FatFs/src/ff.c **** if (!nsect) ABORT(fs, FR_INT_ERR); +4130:Middlewares/Third_Party/FatFs/src/ff.c **** nsect += (DWORD)(ofs / SS(fs)); +4131:Middlewares/Third_Party/FatFs/src/ff.c **** } +4132:Middlewares/Third_Party/FatFs/src/ff.c **** } +4133:Middlewares/Third_Party/FatFs/src/ff.c **** } +4134:Middlewares/Third_Party/FatFs/src/ff.c **** if (!_FS_READONLY && fp->fptr > fp->obj.objsize) { /* Set file change flag if the file size is e +4135:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.objsize = fp->fptr; +4136:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag |= FA_MODIFIED; +4137:Middlewares/Third_Party/FatFs/src/ff.c **** } +4138:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) && nsect != fp->sect) { /* Fill sector cache if needed */ +4139:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY +4140:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +4141:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ +4142:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); +4143:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; +4144:Middlewares/Third_Party/FatFs/src/ff.c **** } +4145:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4146:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_read(fs->drv, fp->buf, nsect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cach +4147:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4148:Middlewares/Third_Party/FatFs/src/ff.c **** fp->sect = nsect; +4149:Middlewares/Third_Party/FatFs/src/ff.c **** } +4150:Middlewares/Third_Party/FatFs/src/ff.c **** } +4151:Middlewares/Third_Party/FatFs/src/ff.c **** +4152:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); +4153:Middlewares/Third_Party/FatFs/src/ff.c **** } +4154:Middlewares/Third_Party/FatFs/src/ff.c **** +4155:Middlewares/Third_Party/FatFs/src/ff.c **** +4156:Middlewares/Third_Party/FatFs/src/ff.c **** +4157:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 1 +4158:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4159:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create a Directory Object */ +4160:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4161:Middlewares/Third_Party/FatFs/src/ff.c **** +4162:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_opendir ( +4163:Middlewares/Third_Party/FatFs/src/ff.c **** DIR* dp, /* Pointer to directory object to create */ +4164:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* path /* Pointer to the directory path */ +4165:Middlewares/Third_Party/FatFs/src/ff.c **** ) +4166:Middlewares/Third_Party/FatFs/src/ff.c **** { +4167:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +4168:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +4169:Middlewares/Third_Party/FatFs/src/ff.c **** _FDID *obj; +4170:Middlewares/Third_Party/FatFs/src/ff.c **** DEF_NAMBUF +4171:Middlewares/Third_Party/FatFs/src/ff.c **** +4172:Middlewares/Third_Party/FatFs/src/ff.c **** +4173:Middlewares/Third_Party/FatFs/src/ff.c **** if (!dp) return FR_INVALID_OBJECT; +4174:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 105 + + +4175:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get logical drive */ +4176:Middlewares/Third_Party/FatFs/src/ff.c **** obj = &dp->obj; +4177:Middlewares/Third_Party/FatFs/src/ff.c **** res = find_volume(&path, &fs, 0); +4178:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4179:Middlewares/Third_Party/FatFs/src/ff.c **** obj->fs = fs; +4180:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); +4181:Middlewares/Third_Party/FatFs/src/ff.c **** res = follow_path(dp, path); /* Follow the path to the directory */ +4182:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Follow completed */ +4183:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(dp->fn[NSFLAG] & NS_NONAME)) { /* It is not the origin directory itself */ +4184:Middlewares/Third_Party/FatFs/src/ff.c **** if (obj->attr & AM_DIR) { /* This object is a sub-directory */ +4185:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +4186:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { +4187:Middlewares/Third_Party/FatFs/src/ff.c **** obj->c_scl = obj->sclust; /* Get containing directory inforamation */ +4188:Middlewares/Third_Party/FatFs/src/ff.c **** obj->c_size = ((DWORD)obj->objsize & 0xFFFFFF00) | obj->stat; +4189:Middlewares/Third_Party/FatFs/src/ff.c **** obj->c_ofs = dp->blk_ofs; +4190:Middlewares/Third_Party/FatFs/src/ff.c **** obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus); /* Get object allocation info */ +4191:Middlewares/Third_Party/FatFs/src/ff.c **** obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize); +4192:Middlewares/Third_Party/FatFs/src/ff.c **** obj->stat = fs->dirbuf[XDIR_GenFlags] & 2; +4193:Middlewares/Third_Party/FatFs/src/ff.c **** } else +4194:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4195:Middlewares/Third_Party/FatFs/src/ff.c **** { +4196:Middlewares/Third_Party/FatFs/src/ff.c **** obj->sclust = ld_clust(fs, dp->dir); /* Get object allocation info */ +4197:Middlewares/Third_Party/FatFs/src/ff.c **** } +4198:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* This object is a file */ +4199:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_NO_PATH; +4200:Middlewares/Third_Party/FatFs/src/ff.c **** } +4201:Middlewares/Third_Party/FatFs/src/ff.c **** } +4202:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4203:Middlewares/Third_Party/FatFs/src/ff.c **** obj->id = fs->id; +4204:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(dp, 0); /* Rewind directory */ +4205:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 +4206:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4207:Middlewares/Third_Party/FatFs/src/ff.c **** if (obj->sclust) { +4208:Middlewares/Third_Party/FatFs/src/ff.c **** obj->lockid = inc_lock(dp, 0); /* Lock the sub directory */ +4209:Middlewares/Third_Party/FatFs/src/ff.c **** if (!obj->lockid) res = FR_TOO_MANY_OPEN_FILES; +4210:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +4211:Middlewares/Third_Party/FatFs/src/ff.c **** obj->lockid = 0; /* Root directory need not to be locked */ +4212:Middlewares/Third_Party/FatFs/src/ff.c **** } +4213:Middlewares/Third_Party/FatFs/src/ff.c **** } +4214:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4215:Middlewares/Third_Party/FatFs/src/ff.c **** } +4216:Middlewares/Third_Party/FatFs/src/ff.c **** } +4217:Middlewares/Third_Party/FatFs/src/ff.c **** FREE_NAMBUF(); +4218:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) res = FR_NO_PATH; +4219:Middlewares/Third_Party/FatFs/src/ff.c **** } +4220:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) obj->fs = 0; /* Invalidate the directory object if function faild */ +4221:Middlewares/Third_Party/FatFs/src/ff.c **** +4222:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); +4223:Middlewares/Third_Party/FatFs/src/ff.c **** } +4224:Middlewares/Third_Party/FatFs/src/ff.c **** +4225:Middlewares/Third_Party/FatFs/src/ff.c **** +4226:Middlewares/Third_Party/FatFs/src/ff.c **** +4227:Middlewares/Third_Party/FatFs/src/ff.c **** +4228:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4229:Middlewares/Third_Party/FatFs/src/ff.c **** /* Close Directory */ +4230:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4231:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 106 + + +4232:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_closedir ( +4233:Middlewares/Third_Party/FatFs/src/ff.c **** DIR *dp /* Pointer to the directory object to be closed */ +4234:Middlewares/Third_Party/FatFs/src/ff.c **** ) +4235:Middlewares/Third_Party/FatFs/src/ff.c **** { +4236:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +4237:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +4238:Middlewares/Third_Party/FatFs/src/ff.c **** +4239:Middlewares/Third_Party/FatFs/src/ff.c **** +4240:Middlewares/Third_Party/FatFs/src/ff.c **** res = validate(&dp->obj, &fs); /* Check validity of the file object */ +4241:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4242:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 +4243:Middlewares/Third_Party/FatFs/src/ff.c **** if (dp->obj.lockid) { /* Decrement sub-directory open counter */ +4244:Middlewares/Third_Party/FatFs/src/ff.c **** res = dec_lock(dp->obj.lockid); +4245:Middlewares/Third_Party/FatFs/src/ff.c **** } +4246:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) +4247:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4248:Middlewares/Third_Party/FatFs/src/ff.c **** { +4249:Middlewares/Third_Party/FatFs/src/ff.c **** dp->obj.fs = 0; /* Invalidate directory object */ +4250:Middlewares/Third_Party/FatFs/src/ff.c **** } +4251:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT +4252:Middlewares/Third_Party/FatFs/src/ff.c **** unlock_fs(fs, FR_OK); /* Unlock volume */ +4253:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4254:Middlewares/Third_Party/FatFs/src/ff.c **** } +4255:Middlewares/Third_Party/FatFs/src/ff.c **** return res; +4256:Middlewares/Third_Party/FatFs/src/ff.c **** } +4257:Middlewares/Third_Party/FatFs/src/ff.c **** +4258:Middlewares/Third_Party/FatFs/src/ff.c **** +4259:Middlewares/Third_Party/FatFs/src/ff.c **** +4260:Middlewares/Third_Party/FatFs/src/ff.c **** +4261:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4262:Middlewares/Third_Party/FatFs/src/ff.c **** /* Read Directory Entries in Sequence */ +4263:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4264:Middlewares/Third_Party/FatFs/src/ff.c **** +4265:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_readdir ( +4266:Middlewares/Third_Party/FatFs/src/ff.c **** DIR* dp, /* Pointer to the open directory object */ +4267:Middlewares/Third_Party/FatFs/src/ff.c **** FILINFO* fno /* Pointer to file information to return */ +4268:Middlewares/Third_Party/FatFs/src/ff.c **** ) +4269:Middlewares/Third_Party/FatFs/src/ff.c **** { +4270:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +4271:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +4272:Middlewares/Third_Party/FatFs/src/ff.c **** DEF_NAMBUF +4273:Middlewares/Third_Party/FatFs/src/ff.c **** +4274:Middlewares/Third_Party/FatFs/src/ff.c **** +4275:Middlewares/Third_Party/FatFs/src/ff.c **** res = validate(&dp->obj, &fs); /* Check validity of the directory object */ +4276:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4277:Middlewares/Third_Party/FatFs/src/ff.c **** if (!fno) { +4278:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(dp, 0); /* Rewind the directory object */ +4279:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +4280:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); +4281:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_read(dp, 0); /* Read an item */ +4282:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory */ +4283:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* A valid entry is found */ +4284:Middlewares/Third_Party/FatFs/src/ff.c **** get_fileinfo(dp, fno); /* Get the object information */ +4285:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_next(dp, 0); /* Increment index for next */ +4286:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory now */ +4287:Middlewares/Third_Party/FatFs/src/ff.c **** } +4288:Middlewares/Third_Party/FatFs/src/ff.c **** FREE_NAMBUF(); + ARM GAS /tmp/cc2SVLkL.s page 107 + + +4289:Middlewares/Third_Party/FatFs/src/ff.c **** } +4290:Middlewares/Third_Party/FatFs/src/ff.c **** } +4291:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); +4292:Middlewares/Third_Party/FatFs/src/ff.c **** } +4293:Middlewares/Third_Party/FatFs/src/ff.c **** +4294:Middlewares/Third_Party/FatFs/src/ff.c **** +4295:Middlewares/Third_Party/FatFs/src/ff.c **** +4296:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FIND +4297:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4298:Middlewares/Third_Party/FatFs/src/ff.c **** /* Find Next File */ +4299:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4300:Middlewares/Third_Party/FatFs/src/ff.c **** +4301:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_findnext ( +4302:Middlewares/Third_Party/FatFs/src/ff.c **** DIR* dp, /* Pointer to the open directory object */ +4303:Middlewares/Third_Party/FatFs/src/ff.c **** FILINFO* fno /* Pointer to the file information structure */ +4304:Middlewares/Third_Party/FatFs/src/ff.c **** ) +4305:Middlewares/Third_Party/FatFs/src/ff.c **** { +4306:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +4307:Middlewares/Third_Party/FatFs/src/ff.c **** +4308:Middlewares/Third_Party/FatFs/src/ff.c **** +4309:Middlewares/Third_Party/FatFs/src/ff.c **** for (;;) { +4310:Middlewares/Third_Party/FatFs/src/ff.c **** res = f_readdir(dp, fno); /* Get a directory item */ +4311:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK || !fno || !fno->fname[0]) break; /* Terminate if any error or end of directory +4312:Middlewares/Third_Party/FatFs/src/ff.c **** if (pattern_matching(dp->pat, fno->fname, 0, 0)) break; /* Test for the file name */ +4313:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 && _USE_FIND == 2 +4314:Middlewares/Third_Party/FatFs/src/ff.c **** if (pattern_matching(dp->pat, fno->altname, 0, 0)) break; /* Test for alternative name if exist * +4315:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4316:Middlewares/Third_Party/FatFs/src/ff.c **** } +4317:Middlewares/Third_Party/FatFs/src/ff.c **** return res; +4318:Middlewares/Third_Party/FatFs/src/ff.c **** } +4319:Middlewares/Third_Party/FatFs/src/ff.c **** +4320:Middlewares/Third_Party/FatFs/src/ff.c **** +4321:Middlewares/Third_Party/FatFs/src/ff.c **** +4322:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4323:Middlewares/Third_Party/FatFs/src/ff.c **** /* Find First File */ +4324:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4325:Middlewares/Third_Party/FatFs/src/ff.c **** +4326:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_findfirst ( +4327:Middlewares/Third_Party/FatFs/src/ff.c **** DIR* dp, /* Pointer to the blank directory object */ +4328:Middlewares/Third_Party/FatFs/src/ff.c **** FILINFO* fno, /* Pointer to the file information structure */ +4329:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* path, /* Pointer to the directory to open */ +4330:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* pattern /* Pointer to the matching pattern */ +4331:Middlewares/Third_Party/FatFs/src/ff.c **** ) +4332:Middlewares/Third_Party/FatFs/src/ff.c **** { +4333:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +4334:Middlewares/Third_Party/FatFs/src/ff.c **** +4335:Middlewares/Third_Party/FatFs/src/ff.c **** +4336:Middlewares/Third_Party/FatFs/src/ff.c **** dp->pat = pattern; /* Save pointer to pattern string */ +4337:Middlewares/Third_Party/FatFs/src/ff.c **** res = f_opendir(dp, path); /* Open the target directory */ +4338:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4339:Middlewares/Third_Party/FatFs/src/ff.c **** res = f_findnext(dp, fno); /* Find the first item */ +4340:Middlewares/Third_Party/FatFs/src/ff.c **** } +4341:Middlewares/Third_Party/FatFs/src/ff.c **** return res; +4342:Middlewares/Third_Party/FatFs/src/ff.c **** } +4343:Middlewares/Third_Party/FatFs/src/ff.c **** +4344:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _USE_FIND */ +4345:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 108 + + +4346:Middlewares/Third_Party/FatFs/src/ff.c **** +4347:Middlewares/Third_Party/FatFs/src/ff.c **** +4348:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE == 0 +4349:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4350:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get File Status */ +4351:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4352:Middlewares/Third_Party/FatFs/src/ff.c **** +4353:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_stat ( +4354:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* path, /* Pointer to the file path */ +4355:Middlewares/Third_Party/FatFs/src/ff.c **** FILINFO* fno /* Pointer to file information to return */ +4356:Middlewares/Third_Party/FatFs/src/ff.c **** ) +4357:Middlewares/Third_Party/FatFs/src/ff.c **** { +4358:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +4359:Middlewares/Third_Party/FatFs/src/ff.c **** DIR dj; +4360:Middlewares/Third_Party/FatFs/src/ff.c **** DEF_NAMBUF +4361:Middlewares/Third_Party/FatFs/src/ff.c **** +4362:Middlewares/Third_Party/FatFs/src/ff.c **** +4363:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get logical drive */ +4364:Middlewares/Third_Party/FatFs/src/ff.c **** res = find_volume(&path, &dj.obj.fs, 0); +4365:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4366:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(dj.obj.fs); +4367:Middlewares/Third_Party/FatFs/src/ff.c **** res = follow_path(&dj, path); /* Follow the file path */ +4368:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Follow completed */ +4369:Middlewares/Third_Party/FatFs/src/ff.c **** if (dj.fn[NSFLAG] & NS_NONAME) { /* It is origin directory */ +4370:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INVALID_NAME; +4371:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* Found an object */ +4372:Middlewares/Third_Party/FatFs/src/ff.c **** if (fno) get_fileinfo(&dj, fno); +4373:Middlewares/Third_Party/FatFs/src/ff.c **** } +4374:Middlewares/Third_Party/FatFs/src/ff.c **** } +4375:Middlewares/Third_Party/FatFs/src/ff.c **** FREE_NAMBUF(); +4376:Middlewares/Third_Party/FatFs/src/ff.c **** } +4377:Middlewares/Third_Party/FatFs/src/ff.c **** +4378:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(dj.obj.fs, res); +4379:Middlewares/Third_Party/FatFs/src/ff.c **** } +4380:Middlewares/Third_Party/FatFs/src/ff.c **** +4381:Middlewares/Third_Party/FatFs/src/ff.c **** +4382:Middlewares/Third_Party/FatFs/src/ff.c **** +4383:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +4384:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4385:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get Number of Free Clusters */ +4386:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4387:Middlewares/Third_Party/FatFs/src/ff.c **** +4388:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_getfree ( +4389:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* path, /* Path name of the logical drive number */ +4390:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD* nclst, /* Pointer to a variable to return number of free clusters */ +4391:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS** fatfs /* Pointer to return pointer to corresponding file system object */ +4392:Middlewares/Third_Party/FatFs/src/ff.c **** ) +4393:Middlewares/Third_Party/FatFs/src/ff.c **** { +4394:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +4395:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +4396:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD nfree, clst, sect, stat; +4397:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i; +4398:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE *p; +4399:Middlewares/Third_Party/FatFs/src/ff.c **** _FDID obj; +4400:Middlewares/Third_Party/FatFs/src/ff.c **** +4401:Middlewares/Third_Party/FatFs/src/ff.c **** +4402:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get logical drive */ + ARM GAS /tmp/cc2SVLkL.s page 109 + + +4403:Middlewares/Third_Party/FatFs/src/ff.c **** res = find_volume(&path, &fs, 0); +4404:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4405:Middlewares/Third_Party/FatFs/src/ff.c **** *fatfs = fs; /* Return ptr to the fs object */ +4406:Middlewares/Third_Party/FatFs/src/ff.c **** /* If free_clst is valid, return it without full cluster scan */ +4407:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->free_clst <= fs->n_fatent - 2) { +4408:Middlewares/Third_Party/FatFs/src/ff.c **** *nclst = fs->free_clst; +4409:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +4410:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get number of free clusters */ +4411:Middlewares/Third_Party/FatFs/src/ff.c **** nfree = 0; +4412:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_FAT12) { /* FAT12: Sector unalighed FAT entries */ +4413:Middlewares/Third_Party/FatFs/src/ff.c **** clst = 2; obj.fs = fs; +4414:Middlewares/Third_Party/FatFs/src/ff.c **** do { +4415:Middlewares/Third_Party/FatFs/src/ff.c **** stat = get_fat(&obj, clst); +4416:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } +4417:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat == 1) { res = FR_INT_ERR; break; } +4418:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat == 0) nfree++; +4419:Middlewares/Third_Party/FatFs/src/ff.c **** } while (++clst < fs->n_fatent); +4420:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +4421:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +4422:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { /* exFAT: Scan bitmap table */ +4423:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE bm; +4424:Middlewares/Third_Party/FatFs/src/ff.c **** UINT b; +4425:Middlewares/Third_Party/FatFs/src/ff.c **** +4426:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fs->n_fatent - 2; +4427:Middlewares/Third_Party/FatFs/src/ff.c **** sect = fs->database; +4428:Middlewares/Third_Party/FatFs/src/ff.c **** i = 0; +4429:Middlewares/Third_Party/FatFs/src/ff.c **** do { +4430:Middlewares/Third_Party/FatFs/src/ff.c **** if (i == 0 && (res = move_window(fs, sect++)) != FR_OK) break; +4431:Middlewares/Third_Party/FatFs/src/ff.c **** for (b = 8, bm = fs->win[i]; b && clst; b--, clst--) { +4432:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(bm & 1)) nfree++; +4433:Middlewares/Third_Party/FatFs/src/ff.c **** bm >>= 1; +4434:Middlewares/Third_Party/FatFs/src/ff.c **** } +4435:Middlewares/Third_Party/FatFs/src/ff.c **** i = (i + 1) % SS(fs); +4436:Middlewares/Third_Party/FatFs/src/ff.c **** } while (clst); +4437:Middlewares/Third_Party/FatFs/src/ff.c **** } else +4438:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4439:Middlewares/Third_Party/FatFs/src/ff.c **** { /* FAT16/32: Sector alighed FAT entries */ +4440:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fs->n_fatent; sect = fs->fatbase; +4441:Middlewares/Third_Party/FatFs/src/ff.c **** i = 0; p = 0; +4442:Middlewares/Third_Party/FatFs/src/ff.c **** do { +4443:Middlewares/Third_Party/FatFs/src/ff.c **** if (i == 0) { +4444:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, sect++); +4445:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +4446:Middlewares/Third_Party/FatFs/src/ff.c **** p = fs->win; +4447:Middlewares/Third_Party/FatFs/src/ff.c **** i = SS(fs); +4448:Middlewares/Third_Party/FatFs/src/ff.c **** } +4449:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_FAT16) { +4450:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_word(p) == 0) nfree++; +4451:Middlewares/Third_Party/FatFs/src/ff.c **** p += 2; i -= 2; +4452:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +4453:Middlewares/Third_Party/FatFs/src/ff.c **** if ((ld_dword(p) & 0x0FFFFFFF) == 0) nfree++; +4454:Middlewares/Third_Party/FatFs/src/ff.c **** p += 4; i -= 4; +4455:Middlewares/Third_Party/FatFs/src/ff.c **** } +4456:Middlewares/Third_Party/FatFs/src/ff.c **** } while (--clst); +4457:Middlewares/Third_Party/FatFs/src/ff.c **** } +4458:Middlewares/Third_Party/FatFs/src/ff.c **** } +4459:Middlewares/Third_Party/FatFs/src/ff.c **** *nclst = nfree; /* Return the free clusters */ + ARM GAS /tmp/cc2SVLkL.s page 110 + + +4460:Middlewares/Third_Party/FatFs/src/ff.c **** fs->free_clst = nfree; /* Now free_clst is valid */ +4461:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag |= 1; /* FSInfo is to be updated */ +4462:Middlewares/Third_Party/FatFs/src/ff.c **** } +4463:Middlewares/Third_Party/FatFs/src/ff.c **** } +4464:Middlewares/Third_Party/FatFs/src/ff.c **** +4465:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); +4466:Middlewares/Third_Party/FatFs/src/ff.c **** } +4467:Middlewares/Third_Party/FatFs/src/ff.c **** +4468:Middlewares/Third_Party/FatFs/src/ff.c **** +4469:Middlewares/Third_Party/FatFs/src/ff.c **** +4470:Middlewares/Third_Party/FatFs/src/ff.c **** +4471:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4472:Middlewares/Third_Party/FatFs/src/ff.c **** /* Truncate File */ +4473:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4474:Middlewares/Third_Party/FatFs/src/ff.c **** +4475:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_truncate ( +4476:Middlewares/Third_Party/FatFs/src/ff.c **** FIL* fp /* Pointer to the file object */ +4477:Middlewares/Third_Party/FatFs/src/ff.c **** ) +4478:Middlewares/Third_Party/FatFs/src/ff.c **** { +4479:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +4480:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +4481:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD ncl; +4482:Middlewares/Third_Party/FatFs/src/ff.c **** +4483:Middlewares/Third_Party/FatFs/src/ff.c **** +4484:Middlewares/Third_Party/FatFs/src/ff.c **** res = validate(&fp->obj, &fs); /* Check validity of the file object */ +4485:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); +4486:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ +4487:Middlewares/Third_Party/FatFs/src/ff.c **** +4488:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr < fp->obj.objsize) { /* Process when fptr is not on the eof */ +4489:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ +4490:Middlewares/Third_Party/FatFs/src/ff.c **** res = remove_chain(&fp->obj, fp->obj.sclust, 0); +4491:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.sclust = 0; +4492:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* When truncate a part of the file, remove remaining clusters */ +4493:Middlewares/Third_Party/FatFs/src/ff.c **** ncl = get_fat(&fp->obj, fp->clust); +4494:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; +4495:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; +4496:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl == 1) res = FR_INT_ERR; +4497:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && ncl < fs->n_fatent) { +4498:Middlewares/Third_Party/FatFs/src/ff.c **** res = remove_chain(&fp->obj, ncl, fp->clust); +4499:Middlewares/Third_Party/FatFs/src/ff.c **** } +4500:Middlewares/Third_Party/FatFs/src/ff.c **** } +4501:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.objsize = fp->fptr; /* Set file size to current R/W point */ +4502:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag |= FA_MODIFIED; +4503:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY +4504:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && (fp->flag & FA_DIRTY)) { +4505:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) { +4506:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DISK_ERR; +4507:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +4508:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; +4509:Middlewares/Third_Party/FatFs/src/ff.c **** } +4510:Middlewares/Third_Party/FatFs/src/ff.c **** } +4511:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4512:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) ABORT(fs, res); +4513:Middlewares/Third_Party/FatFs/src/ff.c **** } +4514:Middlewares/Third_Party/FatFs/src/ff.c **** +4515:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); +4516:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 111 + + +4517:Middlewares/Third_Party/FatFs/src/ff.c **** +4518:Middlewares/Third_Party/FatFs/src/ff.c **** +4519:Middlewares/Third_Party/FatFs/src/ff.c **** +4520:Middlewares/Third_Party/FatFs/src/ff.c **** +4521:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4522:Middlewares/Third_Party/FatFs/src/ff.c **** /* Delete a File/Directory */ +4523:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4524:Middlewares/Third_Party/FatFs/src/ff.c **** +4525:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_unlink ( +4526:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* path /* Pointer to the file or directory path */ +4527:Middlewares/Third_Party/FatFs/src/ff.c **** ) +4528:Middlewares/Third_Party/FatFs/src/ff.c **** { +4529:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +4530:Middlewares/Third_Party/FatFs/src/ff.c **** DIR dj, sdj; +4531:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD dclst = 0; +4532:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +4533:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +4534:Middlewares/Third_Party/FatFs/src/ff.c **** _FDID obj; +4535:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4536:Middlewares/Third_Party/FatFs/src/ff.c **** DEF_NAMBUF +4537:Middlewares/Third_Party/FatFs/src/ff.c **** +4538:Middlewares/Third_Party/FatFs/src/ff.c **** +4539:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get logical drive */ +4540:Middlewares/Third_Party/FatFs/src/ff.c **** res = find_volume(&path, &fs, FA_WRITE); +4541:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.fs = fs; +4542:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4543:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); +4544:Middlewares/Third_Party/FatFs/src/ff.c **** res = follow_path(&dj, path); /* Follow the file path */ +4545:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) { +4546:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INVALID_NAME; /* Cannot remove dot entry */ +4547:Middlewares/Third_Party/FatFs/src/ff.c **** } +4548:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 +4549:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) res = chk_lock(&dj, 2); /* Check if it is an open object */ +4550:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4551:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* The object is accessible */ +4552:Middlewares/Third_Party/FatFs/src/ff.c **** if (dj.fn[NSFLAG] & NS_NONAME) { +4553:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INVALID_NAME; /* Cannot remove the origin directory */ +4554:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +4555:Middlewares/Third_Party/FatFs/src/ff.c **** if (dj.obj.attr & AM_RDO) { +4556:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DENIED; /* Cannot remove R/O object */ +4557:Middlewares/Third_Party/FatFs/src/ff.c **** } +4558:Middlewares/Third_Party/FatFs/src/ff.c **** } +4559:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4560:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +4561:Middlewares/Third_Party/FatFs/src/ff.c **** obj.fs = fs; +4562:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { +4563:Middlewares/Third_Party/FatFs/src/ff.c **** obj.sclust = dclst = ld_dword(fs->dirbuf + XDIR_FstClus); +4564:Middlewares/Third_Party/FatFs/src/ff.c **** obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize); +4565:Middlewares/Third_Party/FatFs/src/ff.c **** obj.stat = fs->dirbuf[XDIR_GenFlags] & 2; +4566:Middlewares/Third_Party/FatFs/src/ff.c **** } else +4567:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4568:Middlewares/Third_Party/FatFs/src/ff.c **** { +4569:Middlewares/Third_Party/FatFs/src/ff.c **** dclst = ld_clust(fs, dj.dir); +4570:Middlewares/Third_Party/FatFs/src/ff.c **** } +4571:Middlewares/Third_Party/FatFs/src/ff.c **** if (dj.obj.attr & AM_DIR) { /* Is it a sub-directory? */ +4572:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0 +4573:Middlewares/Third_Party/FatFs/src/ff.c **** if (dclst == fs->cdir) { /* Is it the current directory? */ + ARM GAS /tmp/cc2SVLkL.s page 112 + + +4574:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DENIED; +4575:Middlewares/Third_Party/FatFs/src/ff.c **** } else +4576:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4577:Middlewares/Third_Party/FatFs/src/ff.c **** { +4578:Middlewares/Third_Party/FatFs/src/ff.c **** sdj.obj.fs = fs; /* Open the sub-directory */ +4579:Middlewares/Third_Party/FatFs/src/ff.c **** sdj.obj.sclust = dclst; +4580:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +4581:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { +4582:Middlewares/Third_Party/FatFs/src/ff.c **** sdj.obj.objsize = obj.objsize; +4583:Middlewares/Third_Party/FatFs/src/ff.c **** sdj.obj.stat = obj.stat; +4584:Middlewares/Third_Party/FatFs/src/ff.c **** } +4585:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4586:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(&sdj, 0); +4587:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4588:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_read(&sdj, 0); /* Read an item */ +4589:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) res = FR_DENIED; /* Not empty? */ +4590:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) res = FR_OK; /* Empty? */ +4591:Middlewares/Third_Party/FatFs/src/ff.c **** } +4592:Middlewares/Third_Party/FatFs/src/ff.c **** } +4593:Middlewares/Third_Party/FatFs/src/ff.c **** } +4594:Middlewares/Third_Party/FatFs/src/ff.c **** } +4595:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4596:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_remove(&dj); /* Remove the directory entry */ +4597:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && dclst) { /* Remove the cluster chain if exist */ +4598:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +4599:Middlewares/Third_Party/FatFs/src/ff.c **** res = remove_chain(&obj, dclst, 0); +4600:Middlewares/Third_Party/FatFs/src/ff.c **** #else +4601:Middlewares/Third_Party/FatFs/src/ff.c **** res = remove_chain(&dj.obj, dclst, 0); +4602:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4603:Middlewares/Third_Party/FatFs/src/ff.c **** } +4604:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) res = sync_fs(fs); +4605:Middlewares/Third_Party/FatFs/src/ff.c **** } +4606:Middlewares/Third_Party/FatFs/src/ff.c **** } +4607:Middlewares/Third_Party/FatFs/src/ff.c **** FREE_NAMBUF(); +4608:Middlewares/Third_Party/FatFs/src/ff.c **** } +4609:Middlewares/Third_Party/FatFs/src/ff.c **** +4610:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); +4611:Middlewares/Third_Party/FatFs/src/ff.c **** } +4612:Middlewares/Third_Party/FatFs/src/ff.c **** +4613:Middlewares/Third_Party/FatFs/src/ff.c **** +4614:Middlewares/Third_Party/FatFs/src/ff.c **** +4615:Middlewares/Third_Party/FatFs/src/ff.c **** +4616:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4617:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create a Directory */ +4618:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4619:Middlewares/Third_Party/FatFs/src/ff.c **** +4620:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_mkdir ( +4621:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* path /* Pointer to the directory path */ +4622:Middlewares/Third_Party/FatFs/src/ff.c **** ) +4623:Middlewares/Third_Party/FatFs/src/ff.c **** { +4624:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +4625:Middlewares/Third_Party/FatFs/src/ff.c **** DIR dj; +4626:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +4627:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE *dir; +4628:Middlewares/Third_Party/FatFs/src/ff.c **** UINT n; +4629:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD dsc, dcl, pcl, tm; +4630:Middlewares/Third_Party/FatFs/src/ff.c **** DEF_NAMBUF + ARM GAS /tmp/cc2SVLkL.s page 113 + + +4631:Middlewares/Third_Party/FatFs/src/ff.c **** +4632:Middlewares/Third_Party/FatFs/src/ff.c **** +4633:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get logical drive */ +4634:Middlewares/Third_Party/FatFs/src/ff.c **** res = find_volume(&path, &fs, FA_WRITE); +4635:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.fs = fs; +4636:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4637:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); +4638:Middlewares/Third_Party/FatFs/src/ff.c **** res = follow_path(&dj, path); /* Follow the file path */ +4639:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */ +4640:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) { +4641:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INVALID_NAME; +4642:Middlewares/Third_Party/FatFs/src/ff.c **** } +4643:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) { /* Can create a new directory */ +4644:Middlewares/Third_Party/FatFs/src/ff.c **** dcl = create_chain(&dj.obj, 0); /* Allocate a cluster for the new directory table */ +4645:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.objsize = (DWORD)fs->csize * SS(fs); +4646:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; +4647:Middlewares/Third_Party/FatFs/src/ff.c **** if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */ +4648:Middlewares/Third_Party/FatFs/src/ff.c **** if (dcl == 1) res = FR_INT_ERR; +4649:Middlewares/Third_Party/FatFs/src/ff.c **** if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; +4650:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) res = sync_window(fs); /* Flush FAT */ +4651:Middlewares/Third_Party/FatFs/src/ff.c **** tm = GET_FATTIME(); +4652:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Initialize the new directory table */ +4653:Middlewares/Third_Party/FatFs/src/ff.c **** dsc = clust2sect(fs, dcl); +4654:Middlewares/Third_Party/FatFs/src/ff.c **** dir = fs->win; +4655:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(dir, 0, SS(fs)); +4656:Middlewares/Third_Party/FatFs/src/ff.c **** if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { +4657:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(dir + DIR_Name, ' ', 11); /* Create "." entry */ +4658:Middlewares/Third_Party/FatFs/src/ff.c **** dir[DIR_Name] = '.'; +4659:Middlewares/Third_Party/FatFs/src/ff.c **** dir[DIR_Attr] = AM_DIR; +4660:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(dir + DIR_ModTime, tm); +4661:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dir, dcl); +4662:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(dir + SZDIRE, dir, SZDIRE); /* Create ".." entry */ +4663:Middlewares/Third_Party/FatFs/src/ff.c **** dir[SZDIRE + 1] = '.'; pcl = dj.obj.sclust; +4664:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_FAT32 && pcl == fs->dirbase) pcl = 0; +4665:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dir + SZDIRE, pcl); +4666:Middlewares/Third_Party/FatFs/src/ff.c **** } +4667:Middlewares/Third_Party/FatFs/src/ff.c **** for (n = fs->csize; n; n--) { /* Write dot entries and clear following sectors */ +4668:Middlewares/Third_Party/FatFs/src/ff.c **** fs->winsect = dsc++; +4669:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +4670:Middlewares/Third_Party/FatFs/src/ff.c **** res = sync_window(fs); +4671:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +4672:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(dir, 0, SS(fs)); +4673:Middlewares/Third_Party/FatFs/src/ff.c **** } +4674:Middlewares/Third_Party/FatFs/src/ff.c **** } +4675:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4676:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_register(&dj); /* Register the object to the directoy */ +4677:Middlewares/Third_Party/FatFs/src/ff.c **** } +4678:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4679:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +4680:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { /* Initialize directory entry block */ +4681:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->dirbuf + XDIR_ModTime, tm); /* Created time */ +4682:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->dirbuf + XDIR_FstClus, dcl); /* Table start cluster */ +4683:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->dirbuf + XDIR_FileSize, (DWORD)dj.obj.objsize); /* File size needs to be valid */ +4684:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->dirbuf + XDIR_ValidFileSize, (DWORD)dj.obj.objsize); +4685:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbuf[XDIR_GenFlags] = 3; /* Initialize the object flag (contiguous) */ +4686:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbuf[XDIR_Attr] = AM_DIR; /* Attribute */ +4687:Middlewares/Third_Party/FatFs/src/ff.c **** res = store_xdir(&dj); + ARM GAS /tmp/cc2SVLkL.s page 114 + + +4688:Middlewares/Third_Party/FatFs/src/ff.c **** } else +4689:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4690:Middlewares/Third_Party/FatFs/src/ff.c **** { +4691:Middlewares/Third_Party/FatFs/src/ff.c **** dir = dj.dir; +4692:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(dir + DIR_ModTime, tm); /* Created time */ +4693:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dir, dcl); /* Table start cluster */ +4694:Middlewares/Third_Party/FatFs/src/ff.c **** dir[DIR_Attr] = AM_DIR; /* Attribute */ +4695:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +4696:Middlewares/Third_Party/FatFs/src/ff.c **** } +4697:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4698:Middlewares/Third_Party/FatFs/src/ff.c **** res = sync_fs(fs); +4699:Middlewares/Third_Party/FatFs/src/ff.c **** } +4700:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +4701:Middlewares/Third_Party/FatFs/src/ff.c **** remove_chain(&dj.obj, dcl, 0); /* Could not register, remove cluster chain */ +4702:Middlewares/Third_Party/FatFs/src/ff.c **** } +4703:Middlewares/Third_Party/FatFs/src/ff.c **** } +4704:Middlewares/Third_Party/FatFs/src/ff.c **** FREE_NAMBUF(); +4705:Middlewares/Third_Party/FatFs/src/ff.c **** } +4706:Middlewares/Third_Party/FatFs/src/ff.c **** +4707:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); +4708:Middlewares/Third_Party/FatFs/src/ff.c **** } +4709:Middlewares/Third_Party/FatFs/src/ff.c **** +4710:Middlewares/Third_Party/FatFs/src/ff.c **** +4711:Middlewares/Third_Party/FatFs/src/ff.c **** +4712:Middlewares/Third_Party/FatFs/src/ff.c **** +4713:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4714:Middlewares/Third_Party/FatFs/src/ff.c **** /* Rename a File/Directory */ +4715:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4716:Middlewares/Third_Party/FatFs/src/ff.c **** +4717:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_rename ( +4718:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* path_old, /* Pointer to the object name to be renamed */ +4719:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* path_new /* Pointer to the new name */ +4720:Middlewares/Third_Party/FatFs/src/ff.c **** ) +4721:Middlewares/Third_Party/FatFs/src/ff.c **** { +4722:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +4723:Middlewares/Third_Party/FatFs/src/ff.c **** DIR djo, djn; +4724:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +4725:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE buf[_FS_EXFAT ? SZDIRE * 2 : 24], *dir; +4726:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD dw; +4727:Middlewares/Third_Party/FatFs/src/ff.c **** DEF_NAMBUF +4728:Middlewares/Third_Party/FatFs/src/ff.c **** +4729:Middlewares/Third_Party/FatFs/src/ff.c **** +4730:Middlewares/Third_Party/FatFs/src/ff.c **** get_ldnumber(&path_new); /* Snip drive number of new name off */ +4731:Middlewares/Third_Party/FatFs/src/ff.c **** res = find_volume(&path_old, &fs, FA_WRITE); /* Get logical drive of the old object */ +4732:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4733:Middlewares/Third_Party/FatFs/src/ff.c **** djo.obj.fs = fs; +4734:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); +4735:Middlewares/Third_Party/FatFs/src/ff.c **** res = follow_path(&djo, path_old); /* Check old object */ +4736:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check vali +4737:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 +4738:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4739:Middlewares/Third_Party/FatFs/src/ff.c **** res = chk_lock(&djo, 2); +4740:Middlewares/Third_Party/FatFs/src/ff.c **** } +4741:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4742:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Object to be renamed is found */ +4743:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +4744:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { /* At exFAT */ + ARM GAS /tmp/cc2SVLkL.s page 115 + + +4745:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE nf, nn; +4746:Middlewares/Third_Party/FatFs/src/ff.c **** WORD nh; +4747:Middlewares/Third_Party/FatFs/src/ff.c **** +4748:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(buf, fs->dirbuf, SZDIRE * 2); /* Save 85+C0 entry of old object */ +4749:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(&djn, &djo, sizeof djo); +4750:Middlewares/Third_Party/FatFs/src/ff.c **** res = follow_path(&djn, path_new); /* Make sure if new object name is not in use */ +4751:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Is new name already in use by any other object? */ +4752:Middlewares/Third_Party/FatFs/src/ff.c **** res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST; +4753:Middlewares/Third_Party/FatFs/src/ff.c **** } +4754:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) { /* It is a valid path and no name collision */ +4755:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_register(&djn); /* Register the new entry */ +4756:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4757:Middlewares/Third_Party/FatFs/src/ff.c **** nf = fs->dirbuf[XDIR_NumSec]; nn = fs->dirbuf[XDIR_NumName]; +4758:Middlewares/Third_Party/FatFs/src/ff.c **** nh = ld_word(fs->dirbuf + XDIR_NameHash); +4759:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(fs->dirbuf, buf, SZDIRE * 2); +4760:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbuf[XDIR_NumSec] = nf; fs->dirbuf[XDIR_NumName] = nn; +4761:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(fs->dirbuf + XDIR_NameHash, nh); +4762:Middlewares/Third_Party/FatFs/src/ff.c **** /* Start of critical section where an interruption can cause a cross-link */ +4763:Middlewares/Third_Party/FatFs/src/ff.c **** res = store_xdir(&djn); +4764:Middlewares/Third_Party/FatFs/src/ff.c **** } +4765:Middlewares/Third_Party/FatFs/src/ff.c **** } +4766:Middlewares/Third_Party/FatFs/src/ff.c **** } else +4767:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4768:Middlewares/Third_Party/FatFs/src/ff.c **** { /* At FAT12/FAT16/FAT32 */ +4769:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(buf, djo.dir + DIR_Attr, 21); /* Save information about the object except name */ +4770:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(&djn, &djo, sizeof (DIR)); /* Duplicate the directory object */ +4771:Middlewares/Third_Party/FatFs/src/ff.c **** res = follow_path(&djn, path_new); /* Make sure if new object name is not in use */ +4772:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Is new name already in use by any other object? */ +4773:Middlewares/Third_Party/FatFs/src/ff.c **** res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST; +4774:Middlewares/Third_Party/FatFs/src/ff.c **** } +4775:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) { /* It is a valid path and no name collision */ +4776:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_register(&djn); /* Register the new entry */ +4777:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4778:Middlewares/Third_Party/FatFs/src/ff.c **** dir = djn.dir; /* Copy information about object except name */ +4779:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(dir + 13, buf + 2, 19); +4780:Middlewares/Third_Party/FatFs/src/ff.c **** dir[DIR_Attr] = buf[0] | AM_ARC; +4781:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +4782:Middlewares/Third_Party/FatFs/src/ff.c **** if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) { /* Update .. entry in the +4783:Middlewares/Third_Party/FatFs/src/ff.c **** dw = clust2sect(fs, ld_clust(fs, dir)); +4784:Middlewares/Third_Party/FatFs/src/ff.c **** if (!dw) { +4785:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INT_ERR; +4786:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +4787:Middlewares/Third_Party/FatFs/src/ff.c **** /* Start of critical section where an interruption can cause a cross-link */ +4788:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dw); +4789:Middlewares/Third_Party/FatFs/src/ff.c **** dir = fs->win + SZDIRE * 1; /* Ptr to .. entry */ +4790:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && dir[1] == '.') { +4791:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dir, djn.obj.sclust); +4792:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +4793:Middlewares/Third_Party/FatFs/src/ff.c **** } +4794:Middlewares/Third_Party/FatFs/src/ff.c **** } +4795:Middlewares/Third_Party/FatFs/src/ff.c **** } +4796:Middlewares/Third_Party/FatFs/src/ff.c **** } +4797:Middlewares/Third_Party/FatFs/src/ff.c **** } +4798:Middlewares/Third_Party/FatFs/src/ff.c **** } +4799:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4800:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_remove(&djo); /* Remove old entry */ +4801:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + ARM GAS /tmp/cc2SVLkL.s page 116 + + +4802:Middlewares/Third_Party/FatFs/src/ff.c **** res = sync_fs(fs); +4803:Middlewares/Third_Party/FatFs/src/ff.c **** } +4804:Middlewares/Third_Party/FatFs/src/ff.c **** } +4805:Middlewares/Third_Party/FatFs/src/ff.c **** /* End of the critical section */ +4806:Middlewares/Third_Party/FatFs/src/ff.c **** } +4807:Middlewares/Third_Party/FatFs/src/ff.c **** FREE_NAMBUF(); +4808:Middlewares/Third_Party/FatFs/src/ff.c **** } +4809:Middlewares/Third_Party/FatFs/src/ff.c **** +4810:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); +4811:Middlewares/Third_Party/FatFs/src/ff.c **** } +4812:Middlewares/Third_Party/FatFs/src/ff.c **** +4813:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* !_FS_READONLY */ +4814:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _FS_MINIMIZE == 0 */ +4815:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _FS_MINIMIZE <= 1 */ +4816:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _FS_MINIMIZE <= 2 */ +4817:Middlewares/Third_Party/FatFs/src/ff.c **** +4818:Middlewares/Third_Party/FatFs/src/ff.c **** +4819:Middlewares/Third_Party/FatFs/src/ff.c **** +4820:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_CHMOD && !_FS_READONLY +4821:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4822:Middlewares/Third_Party/FatFs/src/ff.c **** /* Change Attribute */ +4823:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4824:Middlewares/Third_Party/FatFs/src/ff.c **** +4825:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_chmod ( +4826:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* path, /* Pointer to the file path */ +4827:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE attr, /* Attribute bits */ +4828:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE mask /* Attribute mask to change */ +4829:Middlewares/Third_Party/FatFs/src/ff.c **** ) +4830:Middlewares/Third_Party/FatFs/src/ff.c **** { +4831:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +4832:Middlewares/Third_Party/FatFs/src/ff.c **** DIR dj; +4833:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +4834:Middlewares/Third_Party/FatFs/src/ff.c **** DEF_NAMBUF +4835:Middlewares/Third_Party/FatFs/src/ff.c **** +4836:Middlewares/Third_Party/FatFs/src/ff.c **** +4837:Middlewares/Third_Party/FatFs/src/ff.c **** res = find_volume(&path, &fs, FA_WRITE); /* Get logical drive */ +4838:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.fs = fs; +4839:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4840:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); +4841:Middlewares/Third_Party/FatFs/src/ff.c **** res = follow_path(&dj, path); /* Follow the file path */ +4842:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check objec +4843:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4844:Middlewares/Third_Party/FatFs/src/ff.c **** mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ +4845:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +4846:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { +4847:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbuf[XDIR_Attr] = (attr & mask) | (fs->dirbuf[XDIR_Attr] & (BYTE)~mask); /* Apply attribu +4848:Middlewares/Third_Party/FatFs/src/ff.c **** res = store_xdir(&dj); +4849:Middlewares/Third_Party/FatFs/src/ff.c **** } else +4850:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4851:Middlewares/Third_Party/FatFs/src/ff.c **** { +4852:Middlewares/Third_Party/FatFs/src/ff.c **** dj.dir[DIR_Attr] = (attr & mask) | (dj.dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change +4853:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +4854:Middlewares/Third_Party/FatFs/src/ff.c **** } +4855:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4856:Middlewares/Third_Party/FatFs/src/ff.c **** res = sync_fs(fs); +4857:Middlewares/Third_Party/FatFs/src/ff.c **** } +4858:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 117 + + +4859:Middlewares/Third_Party/FatFs/src/ff.c **** FREE_NAMBUF(); +4860:Middlewares/Third_Party/FatFs/src/ff.c **** } +4861:Middlewares/Third_Party/FatFs/src/ff.c **** +4862:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); +4863:Middlewares/Third_Party/FatFs/src/ff.c **** } +4864:Middlewares/Third_Party/FatFs/src/ff.c **** +4865:Middlewares/Third_Party/FatFs/src/ff.c **** +4866:Middlewares/Third_Party/FatFs/src/ff.c **** +4867:Middlewares/Third_Party/FatFs/src/ff.c **** +4868:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4869:Middlewares/Third_Party/FatFs/src/ff.c **** /* Change Timestamp */ +4870:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4871:Middlewares/Third_Party/FatFs/src/ff.c **** +4872:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_utime ( +4873:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* path, /* Pointer to the file/directory name */ +4874:Middlewares/Third_Party/FatFs/src/ff.c **** const FILINFO* fno /* Pointer to the time stamp to be set */ +4875:Middlewares/Third_Party/FatFs/src/ff.c **** ) +4876:Middlewares/Third_Party/FatFs/src/ff.c **** { +4877:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +4878:Middlewares/Third_Party/FatFs/src/ff.c **** DIR dj; +4879:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +4880:Middlewares/Third_Party/FatFs/src/ff.c **** DEF_NAMBUF +4881:Middlewares/Third_Party/FatFs/src/ff.c **** +4882:Middlewares/Third_Party/FatFs/src/ff.c **** +4883:Middlewares/Third_Party/FatFs/src/ff.c **** res = find_volume(&path, &fs, FA_WRITE); /* Get logical drive */ +4884:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.fs = fs; +4885:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4886:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); +4887:Middlewares/Third_Party/FatFs/src/ff.c **** res = follow_path(&dj, path); /* Follow the file path */ +4888:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check objec +4889:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4890:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +4891:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { +4892:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->dirbuf + XDIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime); +4893:Middlewares/Third_Party/FatFs/src/ff.c **** res = store_xdir(&dj); +4894:Middlewares/Third_Party/FatFs/src/ff.c **** } else +4895:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4896:Middlewares/Third_Party/FatFs/src/ff.c **** { +4897:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(dj.dir + DIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime); +4898:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +4899:Middlewares/Third_Party/FatFs/src/ff.c **** } +4900:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4901:Middlewares/Third_Party/FatFs/src/ff.c **** res = sync_fs(fs); +4902:Middlewares/Third_Party/FatFs/src/ff.c **** } +4903:Middlewares/Third_Party/FatFs/src/ff.c **** } +4904:Middlewares/Third_Party/FatFs/src/ff.c **** FREE_NAMBUF(); +4905:Middlewares/Third_Party/FatFs/src/ff.c **** } +4906:Middlewares/Third_Party/FatFs/src/ff.c **** +4907:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); +4908:Middlewares/Third_Party/FatFs/src/ff.c **** } +4909:Middlewares/Third_Party/FatFs/src/ff.c **** +4910:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _USE_CHMOD && !_FS_READONLY */ +4911:Middlewares/Third_Party/FatFs/src/ff.c **** +4912:Middlewares/Third_Party/FatFs/src/ff.c **** +4913:Middlewares/Third_Party/FatFs/src/ff.c **** +4914:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LABEL +4915:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ + ARM GAS /tmp/cc2SVLkL.s page 118 + + +4916:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get Volume Label */ +4917:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +4918:Middlewares/Third_Party/FatFs/src/ff.c **** +4919:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_getlabel ( +4920:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* path, /* Path name of the logical drive number */ +4921:Middlewares/Third_Party/FatFs/src/ff.c **** TCHAR* label, /* Pointer to a buffer to return the volume label */ +4922:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD* vsn /* Pointer to a variable to return the volume serial number */ +4923:Middlewares/Third_Party/FatFs/src/ff.c **** ) +4924:Middlewares/Third_Party/FatFs/src/ff.c **** { +4925:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +4926:Middlewares/Third_Party/FatFs/src/ff.c **** DIR dj; +4927:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +4928:Middlewares/Third_Party/FatFs/src/ff.c **** UINT si, di; +4929:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE || _FS_EXFAT +4930:Middlewares/Third_Party/FatFs/src/ff.c **** WCHAR w; +4931:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4932:Middlewares/Third_Party/FatFs/src/ff.c **** +4933:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get logical drive */ +4934:Middlewares/Third_Party/FatFs/src/ff.c **** res = find_volume(&path, &fs, 0); +4935:Middlewares/Third_Party/FatFs/src/ff.c **** +4936:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get volume label */ +4937:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && label) { +4938:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.fs = fs; dj.obj.sclust = 0; /* Open root directory */ +4939:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(&dj, 0); +4940:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4941:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_read(&dj, 1); /* Find a volume label entry */ +4942:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4943:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +4944:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { +4945:Middlewares/Third_Party/FatFs/src/ff.c **** for (si = di = 0; si < dj.dir[XDIR_NumLabel]; si++) { /* Extract volume label from 83 entry */ +4946:Middlewares/Third_Party/FatFs/src/ff.c **** w = ld_word(dj.dir + XDIR_Label + si * 2); +4947:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE +4948:Middlewares/Third_Party/FatFs/src/ff.c **** label[di++] = w; +4949:Middlewares/Third_Party/FatFs/src/ff.c **** #else +4950:Middlewares/Third_Party/FatFs/src/ff.c **** w = ff_convert(w, 0); /* Unicode -> OEM */ +4951:Middlewares/Third_Party/FatFs/src/ff.c **** if (w == 0) w = '?'; /* Replace wrong character */ +4952:Middlewares/Third_Party/FatFs/src/ff.c **** if (_DF1S && w >= 0x100) label[di++] = (char)(w >> 8); +4953:Middlewares/Third_Party/FatFs/src/ff.c **** label[di++] = (char)w; +4954:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4955:Middlewares/Third_Party/FatFs/src/ff.c **** } +4956:Middlewares/Third_Party/FatFs/src/ff.c **** label[di] = 0; +4957:Middlewares/Third_Party/FatFs/src/ff.c **** } else +4958:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4959:Middlewares/Third_Party/FatFs/src/ff.c **** { +4960:Middlewares/Third_Party/FatFs/src/ff.c **** si = di = 0; /* Extract volume label from AM_VOL entry with code comversion */ +4961:Middlewares/Third_Party/FatFs/src/ff.c **** do { +4962:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE +4963:Middlewares/Third_Party/FatFs/src/ff.c **** w = (si < 11) ? dj.dir[si++] : ' '; +4964:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsDBCS1(w) && si < 11 && IsDBCS2(dj.dir[si])) { +4965:Middlewares/Third_Party/FatFs/src/ff.c **** w = w << 8 | dj.dir[si++]; +4966:Middlewares/Third_Party/FatFs/src/ff.c **** } +4967:Middlewares/Third_Party/FatFs/src/ff.c **** label[di++] = ff_convert(w, 1); /* OEM -> Unicode */ +4968:Middlewares/Third_Party/FatFs/src/ff.c **** #else +4969:Middlewares/Third_Party/FatFs/src/ff.c **** label[di++] = dj.dir[si++]; +4970:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +4971:Middlewares/Third_Party/FatFs/src/ff.c **** } while (di < 11); +4972:Middlewares/Third_Party/FatFs/src/ff.c **** do { /* Truncate trailing spaces */ + ARM GAS /tmp/cc2SVLkL.s page 119 + + +4973:Middlewares/Third_Party/FatFs/src/ff.c **** label[di] = 0; +4974:Middlewares/Third_Party/FatFs/src/ff.c **** if (di == 0) break; +4975:Middlewares/Third_Party/FatFs/src/ff.c **** } while (label[--di] == ' '); +4976:Middlewares/Third_Party/FatFs/src/ff.c **** } +4977:Middlewares/Third_Party/FatFs/src/ff.c **** } +4978:Middlewares/Third_Party/FatFs/src/ff.c **** } +4979:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) { /* No label entry and return nul string */ +4980:Middlewares/Third_Party/FatFs/src/ff.c **** label[0] = 0; +4981:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; +4982:Middlewares/Third_Party/FatFs/src/ff.c **** } +4983:Middlewares/Third_Party/FatFs/src/ff.c **** } +4984:Middlewares/Third_Party/FatFs/src/ff.c **** +4985:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get volume serial number */ +4986:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && vsn) { +4987:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, fs->volbase); +4988:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +4989:Middlewares/Third_Party/FatFs/src/ff.c **** switch (fs->fs_type) { +4990:Middlewares/Third_Party/FatFs/src/ff.c **** case FS_EXFAT: +4991:Middlewares/Third_Party/FatFs/src/ff.c **** di = BPB_VolIDEx; break; +4992:Middlewares/Third_Party/FatFs/src/ff.c **** +4993:Middlewares/Third_Party/FatFs/src/ff.c **** case FS_FAT32: +4994:Middlewares/Third_Party/FatFs/src/ff.c **** di = BS_VolID32; break; +4995:Middlewares/Third_Party/FatFs/src/ff.c **** +4996:Middlewares/Third_Party/FatFs/src/ff.c **** default: +4997:Middlewares/Third_Party/FatFs/src/ff.c **** di = BS_VolID; +4998:Middlewares/Third_Party/FatFs/src/ff.c **** } +4999:Middlewares/Third_Party/FatFs/src/ff.c **** *vsn = ld_dword(fs->win + di); +5000:Middlewares/Third_Party/FatFs/src/ff.c **** } +5001:Middlewares/Third_Party/FatFs/src/ff.c **** } +5002:Middlewares/Third_Party/FatFs/src/ff.c **** +5003:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); +5004:Middlewares/Third_Party/FatFs/src/ff.c **** } +5005:Middlewares/Third_Party/FatFs/src/ff.c **** +5006:Middlewares/Third_Party/FatFs/src/ff.c **** +5007:Middlewares/Third_Party/FatFs/src/ff.c **** +5008:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +5009:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +5010:Middlewares/Third_Party/FatFs/src/ff.c **** /* Set Volume Label */ +5011:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +5012:Middlewares/Third_Party/FatFs/src/ff.c **** +5013:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_setlabel ( +5014:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* label /* Pointer to the volume label to set */ +5015:Middlewares/Third_Party/FatFs/src/ff.c **** ) +5016:Middlewares/Third_Party/FatFs/src/ff.c **** { +5017:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +5018:Middlewares/Third_Party/FatFs/src/ff.c **** DIR dj; +5019:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +5020:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE dirvn[22]; +5021:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i, j, slen; +5022:Middlewares/Third_Party/FatFs/src/ff.c **** WCHAR w; +5023:Middlewares/Third_Party/FatFs/src/ff.c **** static const char badchr[] = "\"*+,.:;<=>\?[]|\x7F"; +5024:Middlewares/Third_Party/FatFs/src/ff.c **** +5025:Middlewares/Third_Party/FatFs/src/ff.c **** +5026:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get logical drive */ +5027:Middlewares/Third_Party/FatFs/src/ff.c **** res = find_volume(&label, &fs, FA_WRITE); +5028:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) LEAVE_FF(fs, res); +5029:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.fs = fs; + ARM GAS /tmp/cc2SVLkL.s page 120 + + +5030:Middlewares/Third_Party/FatFs/src/ff.c **** +5031:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get length of given volume label */ +5032:Middlewares/Third_Party/FatFs/src/ff.c **** for (slen = 0; (UINT)label[slen] >= ' '; slen++) ; /* Get name length */ +5033:Middlewares/Third_Party/FatFs/src/ff.c **** +5034:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +5035:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */ +5036:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = j = 0; i < slen; ) { /* Create volume label in directory form */ +5037:Middlewares/Third_Party/FatFs/src/ff.c **** w = label[i++]; +5038:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_LFN_UNICODE +5039:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsDBCS1(w)) { +5040:Middlewares/Third_Party/FatFs/src/ff.c **** w = (i < slen && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0; +5041:Middlewares/Third_Party/FatFs/src/ff.c **** } +5042:Middlewares/Third_Party/FatFs/src/ff.c **** w = ff_convert(w, 1); +5043:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +5044:Middlewares/Third_Party/FatFs/src/ff.c **** if (w == 0 || chk_chr(badchr, w) || j == 22) { /* Check validity check validity of the volume la +5045:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, FR_INVALID_NAME); +5046:Middlewares/Third_Party/FatFs/src/ff.c **** } +5047:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(dirvn + j, w); j += 2; +5048:Middlewares/Third_Party/FatFs/src/ff.c **** } +5049:Middlewares/Third_Party/FatFs/src/ff.c **** slen = j; +5050:Middlewares/Third_Party/FatFs/src/ff.c **** } else +5051:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +5052:Middlewares/Third_Party/FatFs/src/ff.c **** { /* On the FAT12/16/32 volume */ +5053:Middlewares/Third_Party/FatFs/src/ff.c **** for ( ; slen && label[slen - 1] == ' '; slen--) ; /* Remove trailing spaces */ +5054:Middlewares/Third_Party/FatFs/src/ff.c **** if (slen) { /* Is there a volume label to be set? */ +5055:Middlewares/Third_Party/FatFs/src/ff.c **** dirvn[0] = 0; i = j = 0; /* Create volume label in directory form */ +5056:Middlewares/Third_Party/FatFs/src/ff.c **** do { +5057:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE +5058:Middlewares/Third_Party/FatFs/src/ff.c **** w = ff_convert(ff_wtoupper(label[i++]), 0); +5059:Middlewares/Third_Party/FatFs/src/ff.c **** #else +5060:Middlewares/Third_Party/FatFs/src/ff.c **** w = (BYTE)label[i++]; +5061:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsDBCS1(w)) { +5062:Middlewares/Third_Party/FatFs/src/ff.c **** w = (j < 10 && i < slen && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0; +5063:Middlewares/Third_Party/FatFs/src/ff.c **** } +5064:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 +5065:Middlewares/Third_Party/FatFs/src/ff.c **** w = ff_convert(ff_wtoupper(ff_convert(w, 1)), 0); +5066:Middlewares/Third_Party/FatFs/src/ff.c **** #else +5067:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsLower(w)) w -= 0x20; /* To upper ASCII characters */ +5068:Middlewares/Third_Party/FatFs/src/ff.c **** #ifdef _EXCVT +5069:Middlewares/Third_Party/FatFs/src/ff.c **** if (w >= 0x80) w = ExCvt[w - 0x80]; /* To upper extended characters (SBCS cfg) */ +5070:Middlewares/Third_Party/FatFs/src/ff.c **** #else +5071:Middlewares/Third_Party/FatFs/src/ff.c **** if (!_DF1S && w >= 0x80) w = 0; /* Reject extended characters (ASCII cfg) */ +5072:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +5073:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +5074:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +5075:Middlewares/Third_Party/FatFs/src/ff.c **** if (w == 0 || chk_chr(badchr, w) || j >= (UINT)((w >= 0x100) ? 10 : 11)) { /* Reject invalid ch +5076:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, FR_INVALID_NAME); +5077:Middlewares/Third_Party/FatFs/src/ff.c **** } +5078:Middlewares/Third_Party/FatFs/src/ff.c **** if (w >= 0x100) dirvn[j++] = (BYTE)(w >> 8); +5079:Middlewares/Third_Party/FatFs/src/ff.c **** dirvn[j++] = (BYTE)w; +5080:Middlewares/Third_Party/FatFs/src/ff.c **** } while (i < slen); +5081:Middlewares/Third_Party/FatFs/src/ff.c **** while (j < 11) dirvn[j++] = ' '; /* Fill remaining name field */ +5082:Middlewares/Third_Party/FatFs/src/ff.c **** if (dirvn[0] == DDEM) LEAVE_FF(fs, FR_INVALID_NAME); /* Reject illegal name (heading DDEM) */ +5083:Middlewares/Third_Party/FatFs/src/ff.c **** } +5084:Middlewares/Third_Party/FatFs/src/ff.c **** } +5085:Middlewares/Third_Party/FatFs/src/ff.c **** +5086:Middlewares/Third_Party/FatFs/src/ff.c **** /* Set volume label */ + ARM GAS /tmp/cc2SVLkL.s page 121 + + +5087:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.sclust = 0; /* Open root directory */ +5088:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(&dj, 0); +5089:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +5090:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_read(&dj, 1); /* Get volume label entry */ +5091:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +5092:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_EXFAT && fs->fs_type == FS_EXFAT) { +5093:Middlewares/Third_Party/FatFs/src/ff.c **** dj.dir[XDIR_NumLabel] = (BYTE)(slen / 2); /* Change the volume label */ +5094:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(dj.dir + XDIR_Label, dirvn, slen); +5095:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +5096:Middlewares/Third_Party/FatFs/src/ff.c **** if (slen) { +5097:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(dj.dir, dirvn, 11); /* Change the volume label */ +5098:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +5099:Middlewares/Third_Party/FatFs/src/ff.c **** dj.dir[DIR_Name] = DDEM; /* Remove the volume label */ +5100:Middlewares/Third_Party/FatFs/src/ff.c **** } +5101:Middlewares/Third_Party/FatFs/src/ff.c **** } +5102:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +5103:Middlewares/Third_Party/FatFs/src/ff.c **** res = sync_fs(fs); +5104:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* No volume label entry is found or error */ +5105:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) { +5106:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; +5107:Middlewares/Third_Party/FatFs/src/ff.c **** if (slen) { /* Create a volume label entry */ +5108:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_alloc(&dj, 1); /* Allocate an entry */ +5109:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +5110:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(dj.dir, 0, SZDIRE); /* Clear the entry */ +5111:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_EXFAT && fs->fs_type == FS_EXFAT) { +5112:Middlewares/Third_Party/FatFs/src/ff.c **** dj.dir[XDIR_Type] = 0x83; /* Create 83 entry */ +5113:Middlewares/Third_Party/FatFs/src/ff.c **** dj.dir[XDIR_NumLabel] = (BYTE)(slen / 2); +5114:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(dj.dir + XDIR_Label, dirvn, slen); +5115:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +5116:Middlewares/Third_Party/FatFs/src/ff.c **** dj.dir[DIR_Attr] = AM_VOL; /* Create volume label entry */ +5117:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(dj.dir, dirvn, 11); +5118:Middlewares/Third_Party/FatFs/src/ff.c **** } +5119:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; +5120:Middlewares/Third_Party/FatFs/src/ff.c **** res = sync_fs(fs); +5121:Middlewares/Third_Party/FatFs/src/ff.c **** } +5122:Middlewares/Third_Party/FatFs/src/ff.c **** } +5123:Middlewares/Third_Party/FatFs/src/ff.c **** } +5124:Middlewares/Third_Party/FatFs/src/ff.c **** } +5125:Middlewares/Third_Party/FatFs/src/ff.c **** } +5126:Middlewares/Third_Party/FatFs/src/ff.c **** +5127:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); +5128:Middlewares/Third_Party/FatFs/src/ff.c **** } +5129:Middlewares/Third_Party/FatFs/src/ff.c **** +5130:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* !_FS_READONLY */ +5131:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _USE_LABEL */ +5132:Middlewares/Third_Party/FatFs/src/ff.c **** +5133:Middlewares/Third_Party/FatFs/src/ff.c **** +5134:Middlewares/Third_Party/FatFs/src/ff.c **** +5135:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_EXPAND && !_FS_READONLY +5136:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +5137:Middlewares/Third_Party/FatFs/src/ff.c **** /* Allocate a Contiguous Blocks to the File */ +5138:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +5139:Middlewares/Third_Party/FatFs/src/ff.c **** +5140:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_expand ( +5141:Middlewares/Third_Party/FatFs/src/ff.c **** FIL* fp, /* Pointer to the file object */ +5142:Middlewares/Third_Party/FatFs/src/ff.c **** FSIZE_t fsz, /* File size to be expanded to */ +5143:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE opt /* Operation mode 0:Find and prepare or 1:Find and allocate */ + ARM GAS /tmp/cc2SVLkL.s page 122 + + +5144:Middlewares/Third_Party/FatFs/src/ff.c **** ) +5145:Middlewares/Third_Party/FatFs/src/ff.c **** { +5146:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +5147:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +5148:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD n, clst, stcl, scl, ncl, tcl, lclst; +5149:Middlewares/Third_Party/FatFs/src/ff.c **** +5150:Middlewares/Third_Party/FatFs/src/ff.c **** +5151:Middlewares/Third_Party/FatFs/src/ff.c **** res = validate(&fp->obj, &fs); /* Check validity of the file object */ +5152:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); +5153:Middlewares/Third_Party/FatFs/src/ff.c **** if (fsz == 0 || fp->obj.objsize != 0 || !(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); +5154:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +5155:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type != FS_EXFAT && fsz >= 0x100000000) LEAVE_FF(fs, FR_DENIED); /* Check if in size li +5156:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +5157:Middlewares/Third_Party/FatFs/src/ff.c **** n = (DWORD)fs->csize * SS(fs); /* Cluster size */ +5158:Middlewares/Third_Party/FatFs/src/ff.c **** tcl = (DWORD)(fsz / n) + ((fsz & (n - 1)) ? 1 : 0); /* Number of clusters required */ +5159:Middlewares/Third_Party/FatFs/src/ff.c **** stcl = fs->last_clst; lclst = 0; +5160:Middlewares/Third_Party/FatFs/src/ff.c **** if (stcl < 2 || stcl >= fs->n_fatent) stcl = 2; +5161:Middlewares/Third_Party/FatFs/src/ff.c **** +5162:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +5163:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_EXFAT) { +5164:Middlewares/Third_Party/FatFs/src/ff.c **** scl = find_bitmap(fs, stcl, tcl); /* Find a contiguous cluster block */ +5165:Middlewares/Third_Party/FatFs/src/ff.c **** if (scl == 0) res = FR_DENIED; /* No contiguous cluster block was found */ +5166:Middlewares/Third_Party/FatFs/src/ff.c **** if (scl == 0xFFFFFFFF) res = FR_DISK_ERR; +5167:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* A contiguous free area is found */ +5168:Middlewares/Third_Party/FatFs/src/ff.c **** if (opt) { /* Allocate it now */ +5169:Middlewares/Third_Party/FatFs/src/ff.c **** res = change_bitmap(fs, scl, tcl, 1); /* Mark the cluster block 'in use' */ +5170:Middlewares/Third_Party/FatFs/src/ff.c **** lclst = scl + tcl - 1; +5171:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* Set it as suggested point for next allocation */ +5172:Middlewares/Third_Party/FatFs/src/ff.c **** lclst = scl - 1; +5173:Middlewares/Third_Party/FatFs/src/ff.c **** } +5174:Middlewares/Third_Party/FatFs/src/ff.c **** } +5175:Middlewares/Third_Party/FatFs/src/ff.c **** } else +5176:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +5177:Middlewares/Third_Party/FatFs/src/ff.c **** { +5178:Middlewares/Third_Party/FatFs/src/ff.c **** scl = clst = stcl; ncl = 0; +5179:Middlewares/Third_Party/FatFs/src/ff.c **** for (;;) { /* Find a contiguous cluster block */ +5180:Middlewares/Third_Party/FatFs/src/ff.c **** n = get_fat(&fp->obj, clst); +5181:Middlewares/Third_Party/FatFs/src/ff.c **** if (++clst >= fs->n_fatent) clst = 2; +5182:Middlewares/Third_Party/FatFs/src/ff.c **** if (n == 1) { res = FR_INT_ERR; break; } +5183:Middlewares/Third_Party/FatFs/src/ff.c **** if (n == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } +5184:Middlewares/Third_Party/FatFs/src/ff.c **** if (n == 0) { /* Is it a free cluster? */ +5185:Middlewares/Third_Party/FatFs/src/ff.c **** if (++ncl == tcl) break; /* Break if a contiguous cluster block is found */ +5186:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +5187:Middlewares/Third_Party/FatFs/src/ff.c **** scl = clst; ncl = 0; /* Not a free cluster */ +5188:Middlewares/Third_Party/FatFs/src/ff.c **** } +5189:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == stcl) { res = FR_DENIED; break; } /* No contiguous cluster? */ +5190:Middlewares/Third_Party/FatFs/src/ff.c **** } +5191:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* A contiguous free area is found */ +5192:Middlewares/Third_Party/FatFs/src/ff.c **** if (opt) { /* Allocate it now */ +5193:Middlewares/Third_Party/FatFs/src/ff.c **** for (clst = scl, n = tcl; n; clst++, n--) { /* Create a cluster chain on the FAT */ +5194:Middlewares/Third_Party/FatFs/src/ff.c **** res = put_fat(fs, clst, (n == 1) ? 0xFFFFFFFF : clst + 1); +5195:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; +5196:Middlewares/Third_Party/FatFs/src/ff.c **** lclst = clst; +5197:Middlewares/Third_Party/FatFs/src/ff.c **** } +5198:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* Set it as suggested point for next allocation */ +5199:Middlewares/Third_Party/FatFs/src/ff.c **** lclst = scl - 1; +5200:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 123 + + +5201:Middlewares/Third_Party/FatFs/src/ff.c **** } +5202:Middlewares/Third_Party/FatFs/src/ff.c **** } +5203:Middlewares/Third_Party/FatFs/src/ff.c **** +5204:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { +5205:Middlewares/Third_Party/FatFs/src/ff.c **** fs->last_clst = lclst; /* Set suggested start cluster to start next */ +5206:Middlewares/Third_Party/FatFs/src/ff.c **** if (opt) { /* Is it allocated now? */ +5207:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.sclust = scl; /* Update object allocation information */ +5208:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.objsize = fsz; +5209:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_EXFAT) fp->obj.stat = 2; /* Set status 'contiguous chain' */ +5210:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag |= FA_MODIFIED; +5211:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->free_clst <= fs->n_fatent - 2) { /* Update FSINFO */ +5212:Middlewares/Third_Party/FatFs/src/ff.c **** fs->free_clst -= tcl; +5213:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag |= 1; +5214:Middlewares/Third_Party/FatFs/src/ff.c **** } +5215:Middlewares/Third_Party/FatFs/src/ff.c **** } +5216:Middlewares/Third_Party/FatFs/src/ff.c **** } +5217:Middlewares/Third_Party/FatFs/src/ff.c **** +5218:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); +5219:Middlewares/Third_Party/FatFs/src/ff.c **** } +5220:Middlewares/Third_Party/FatFs/src/ff.c **** +5221:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _USE_EXPAND && !_FS_READONLY */ +5222:Middlewares/Third_Party/FatFs/src/ff.c **** +5223:Middlewares/Third_Party/FatFs/src/ff.c **** +5224:Middlewares/Third_Party/FatFs/src/ff.c **** +5225:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FORWARD +5226:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +5227:Middlewares/Third_Party/FatFs/src/ff.c **** /* Forward data to the stream directly */ +5228:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +5229:Middlewares/Third_Party/FatFs/src/ff.c **** +5230:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_forward ( +5231:Middlewares/Third_Party/FatFs/src/ff.c **** FIL* fp, /* Pointer to the file object */ +5232:Middlewares/Third_Party/FatFs/src/ff.c **** UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ +5233:Middlewares/Third_Party/FatFs/src/ff.c **** UINT btf, /* Number of bytes to forward */ +5234:Middlewares/Third_Party/FatFs/src/ff.c **** UINT* bf /* Pointer to number of bytes forwarded */ +5235:Middlewares/Third_Party/FatFs/src/ff.c **** ) +5236:Middlewares/Third_Party/FatFs/src/ff.c **** { +5237:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; +5238:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; +5239:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clst, sect; +5240:Middlewares/Third_Party/FatFs/src/ff.c **** FSIZE_t remain; +5241:Middlewares/Third_Party/FatFs/src/ff.c **** UINT rcnt, csect; +5242:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE *dbuf; +5243:Middlewares/Third_Party/FatFs/src/ff.c **** +5244:Middlewares/Third_Party/FatFs/src/ff.c **** +5245:Middlewares/Third_Party/FatFs/src/ff.c **** *bf = 0; /* Clear transfer byte counter */ +5246:Middlewares/Third_Party/FatFs/src/ff.c **** res = validate(&fp->obj, &fs); /* Check validity of the file object */ +5247:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); +5248:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ +5249:Middlewares/Third_Party/FatFs/src/ff.c **** +5250:Middlewares/Third_Party/FatFs/src/ff.c **** remain = fp->obj.objsize - fp->fptr; +5251:Middlewares/Third_Party/FatFs/src/ff.c **** if (btf > remain) btf = (UINT)remain; /* Truncate btf by remaining bytes */ +5252:Middlewares/Third_Party/FatFs/src/ff.c **** +5253:Middlewares/Third_Party/FatFs/src/ff.c **** for ( ; btf && (*func)(0, 0); /* Repeat until all data transferred or stream goes busy */ +5254:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) { +5255:Middlewares/Third_Party/FatFs/src/ff.c **** csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ +5256:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ +5257:Middlewares/Third_Party/FatFs/src/ff.c **** if (csect == 0) { /* On the cluster boundary? */ + ARM GAS /tmp/cc2SVLkL.s page 124 + + +5258:Middlewares/Third_Party/FatFs/src/ff.c **** clst = (fp->fptr == 0) ? /* On the top of the file? */ +5259:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.sclust : get_fat(&fp->obj, fp->clust); +5260:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst <= 1) ABORT(fs, FR_INT_ERR); +5261:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); +5262:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; /* Update current cluster */ +5263:Middlewares/Third_Party/FatFs/src/ff.c **** } +5264:Middlewares/Third_Party/FatFs/src/ff.c **** } +5265:Middlewares/Third_Party/FatFs/src/ff.c **** sect = clust2sect(fs, fp->clust); /* Get current data sector */ +5266:Middlewares/Third_Party/FatFs/src/ff.c **** if (!sect) ABORT(fs, FR_INT_ERR); +5267:Middlewares/Third_Party/FatFs/src/ff.c **** sect += csect; +5268:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY +5269:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window to the file dat +5270:Middlewares/Third_Party/FatFs/src/ff.c **** dbuf = fs->win; +5271:Middlewares/Third_Party/FatFs/src/ff.c **** #else +5272:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->sect != sect) { /* Fill sector cache with file data */ +5273:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +5274:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */ +5275:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); +5276:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; +5277:Middlewares/Third_Party/FatFs/src/ff.c **** } +5278:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +5279:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); +5280:Middlewares/Third_Party/FatFs/src/ff.c **** } +5281:Middlewares/Third_Party/FatFs/src/ff.c **** dbuf = fp->buf; +5282:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +5283:Middlewares/Third_Party/FatFs/src/ff.c **** fp->sect = sect; +5284:Middlewares/Third_Party/FatFs/src/ff.c **** rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes left in the sector */ +5285:Middlewares/Third_Party/FatFs/src/ff.c **** if (rcnt > btf) rcnt = btf; /* Clip it by btr if needed */ +5286:Middlewares/Third_Party/FatFs/src/ff.c **** rcnt = (*func)(dbuf + ((UINT)fp->fptr % SS(fs)), rcnt); /* Forward the file data */ +5287:Middlewares/Third_Party/FatFs/src/ff.c **** if (!rcnt) ABORT(fs, FR_INT_ERR); +5288:Middlewares/Third_Party/FatFs/src/ff.c **** } +5289:Middlewares/Third_Party/FatFs/src/ff.c **** +5290:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, FR_OK); +5291:Middlewares/Third_Party/FatFs/src/ff.c **** } +5292:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _USE_FORWARD */ +5293:Middlewares/Third_Party/FatFs/src/ff.c **** +5294:Middlewares/Third_Party/FatFs/src/ff.c **** +5295:Middlewares/Third_Party/FatFs/src/ff.c **** +5296:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_MKFS && !_FS_READONLY +5297:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +5298:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create an FAT/exFAT volume */ +5299:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +5300:Middlewares/Third_Party/FatFs/src/ff.c **** +5301:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_mkfs ( +5302:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* path, /* Logical drive number */ +5303:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE opt, /* Format option */ +5304:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD au, /* Size of allocation unit (cluster) [byte] */ +5305:Middlewares/Third_Party/FatFs/src/ff.c **** void* work, /* Pointer to working buffer */ +5306:Middlewares/Third_Party/FatFs/src/ff.c **** UINT len /* Size of working buffer */ +5307:Middlewares/Third_Party/FatFs/src/ff.c **** ) +5308:Middlewares/Third_Party/FatFs/src/ff.c **** { +5309:Middlewares/Third_Party/FatFs/src/ff.c **** const UINT n_fats = 1; /* Number of FATs for FAT12/16/32 volume (1 or 2) */ +5310:Middlewares/Third_Party/FatFs/src/ff.c **** const UINT n_rootdir = 512; /* Number of root directory entries for FAT12/16 volume */ +5311:Middlewares/Third_Party/FatFs/src/ff.c **** static const WORD cst[] = {1, 4, 16, 64, 256, 512, 0}; /* Cluster size boundary for FAT12/16 volum +5312:Middlewares/Third_Party/FatFs/src/ff.c **** static const WORD cst32[] = {1, 2, 4, 8, 16, 32, 0}; /* Cluster size boundary for FAT32 volume (12 +5313:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE fmt, sys, *buf, *pte, pdrv, part; +5314:Middlewares/Third_Party/FatFs/src/ff.c **** WORD ss; + ARM GAS /tmp/cc2SVLkL.s page 125 + + +5315:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD szb_buf, sz_buf, sz_blk, n_clst, pau, sect, nsect, n; +5316:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD b_vol, b_fat, b_data; /* Base LBA for volume, fat, data */ +5317:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD sz_vol, sz_rsv, sz_fat, sz_dir; /* Size for volume, fat, dir, data */ +5318:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i; +5319:Middlewares/Third_Party/FatFs/src/ff.c **** int vol; +5320:Middlewares/Third_Party/FatFs/src/ff.c **** DSTATUS stat; +5321:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_TRIM || _FS_EXFAT +5322:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD tbl[3]; +5323:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +5324:Middlewares/Third_Party/FatFs/src/ff.c **** +5325:Middlewares/Third_Party/FatFs/src/ff.c **** +5326:Middlewares/Third_Party/FatFs/src/ff.c **** /* Check mounted drive and clear work area */ +5327:Middlewares/Third_Party/FatFs/src/ff.c **** vol = get_ldnumber(&path); /* Get target logical drive */ +5328:Middlewares/Third_Party/FatFs/src/ff.c **** if (vol < 0) return FR_INVALID_DRIVE; +5329:Middlewares/Third_Party/FatFs/src/ff.c **** if (FatFs[vol]) FatFs[vol]->fs_type = 0; /* Clear the volume */ +5330:Middlewares/Third_Party/FatFs/src/ff.c **** pdrv = LD2PD(vol); /* Physical drive */ +5331:Middlewares/Third_Party/FatFs/src/ff.c **** part = LD2PT(vol); /* Partition (0:create as new, 1-4:get from partition table) */ +5332:Middlewares/Third_Party/FatFs/src/ff.c **** +5333:Middlewares/Third_Party/FatFs/src/ff.c **** /* Check physical drive status */ +5334:Middlewares/Third_Party/FatFs/src/ff.c **** stat = disk_initialize(pdrv); +5335:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat & STA_NOINIT) return FR_NOT_READY; +5336:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; +5337:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 32768 || (sz_blk & +5338:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS /* Get sector size of the medium if variable sector size cfg. */ +5339:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR; +5340:Middlewares/Third_Party/FatFs/src/ff.c **** if (ss > _MAX_SS || ss < _MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR; +5341:Middlewares/Third_Party/FatFs/src/ff.c **** #else +5342:Middlewares/Third_Party/FatFs/src/ff.c **** ss = _MAX_SS; +5343:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +5344:Middlewares/Third_Party/FatFs/src/ff.c **** if ((au != 0 && au < ss) || au > 0x1000000 || (au & (au - 1))) return FR_INVALID_PARAMETER; /* Che +5345:Middlewares/Third_Party/FatFs/src/ff.c **** au /= ss; /* Cluster size in unit of sector */ +5346:Middlewares/Third_Party/FatFs/src/ff.c **** +5347:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get working buffer */ +5348:Middlewares/Third_Party/FatFs/src/ff.c **** buf = (BYTE*)work; /* Working buffer */ +5349:Middlewares/Third_Party/FatFs/src/ff.c **** sz_buf = len / ss; /* Size of working buffer (sector) */ +5350:Middlewares/Third_Party/FatFs/src/ff.c **** szb_buf = sz_buf * ss; /* Size of working buffer (byte) */ +5351:Middlewares/Third_Party/FatFs/src/ff.c **** if (!szb_buf) return FR_MKFS_ABORTED; +5352:Middlewares/Third_Party/FatFs/src/ff.c **** +5353:Middlewares/Third_Party/FatFs/src/ff.c **** /* Determine where the volume to be located (b_vol, sz_vol) */ +5354:Middlewares/Third_Party/FatFs/src/ff.c **** if (_MULTI_PARTITION && part != 0) { +5355:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get partition information from partition table in the MBR */ +5356:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_read(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; /* Load MBR */ +5357:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_word(buf + BS_55AA) != 0xAA55) return FR_MKFS_ABORTED; /* Check if MBR is valid */ +5358:Middlewares/Third_Party/FatFs/src/ff.c **** pte = buf + (MBR_Table + (part - 1) * SZ_PTE); +5359:Middlewares/Third_Party/FatFs/src/ff.c **** if (!pte[PTE_System]) return FR_MKFS_ABORTED; /* No partition? */ +5360:Middlewares/Third_Party/FatFs/src/ff.c **** b_vol = ld_dword(pte + PTE_StLba); /* Get volume start sector */ +5361:Middlewares/Third_Party/FatFs/src/ff.c **** sz_vol = ld_dword(pte + PTE_SizLba); /* Get volume size */ +5362:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +5363:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create a single-partition in this function */ +5364:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) return FR_DISK_ERR; +5365:Middlewares/Third_Party/FatFs/src/ff.c **** b_vol = (opt & FM_SFD) ? 0 : 63; /* Volume start sector */ +5366:Middlewares/Third_Party/FatFs/src/ff.c **** if (sz_vol < b_vol) return FR_MKFS_ABORTED; +5367:Middlewares/Third_Party/FatFs/src/ff.c **** sz_vol -= b_vol; /* Volume size */ +5368:Middlewares/Third_Party/FatFs/src/ff.c **** } +5369:Middlewares/Third_Party/FatFs/src/ff.c **** if (sz_vol < 128) return FR_MKFS_ABORTED; /* Check if volume size is >=128s */ +5370:Middlewares/Third_Party/FatFs/src/ff.c **** +5371:Middlewares/Third_Party/FatFs/src/ff.c **** /* Pre-determine the FAT type */ + ARM GAS /tmp/cc2SVLkL.s page 126 + + +5372:Middlewares/Third_Party/FatFs/src/ff.c **** do { +5373:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_EXFAT && (opt & FM_EXFAT)) { /* exFAT possible? */ +5374:Middlewares/Third_Party/FatFs/src/ff.c **** if ((opt & FM_ANY) == FM_EXFAT || sz_vol >= 0x4000000 || au > 128) { /* exFAT only, vol >= 64Ms +5375:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = FS_EXFAT; break; +5376:Middlewares/Third_Party/FatFs/src/ff.c **** } +5377:Middlewares/Third_Party/FatFs/src/ff.c **** } +5378:Middlewares/Third_Party/FatFs/src/ff.c **** if (au > 128) return FR_INVALID_PARAMETER; /* Too large au for FAT/FAT32 */ +5379:Middlewares/Third_Party/FatFs/src/ff.c **** if (opt & FM_FAT32) { /* FAT32 possible? */ +5380:Middlewares/Third_Party/FatFs/src/ff.c **** if ((opt & FM_ANY) == FM_FAT32 || !(opt & FM_FAT)) { /* FAT32 only or no-FAT? */ +5381:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = FS_FAT32; break; +5382:Middlewares/Third_Party/FatFs/src/ff.c **** } +5383:Middlewares/Third_Party/FatFs/src/ff.c **** } +5384:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(opt & FM_FAT)) return FR_INVALID_PARAMETER; /* no-FAT? */ +5385:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = FS_FAT16; +5386:Middlewares/Third_Party/FatFs/src/ff.c **** } while (0); +5387:Middlewares/Third_Party/FatFs/src/ff.c **** +5388:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT +5389:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_EXFAT) { /* Create an exFAT volume */ +5390:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD szb_bit, szb_case, sum, nb, cl; +5391:Middlewares/Third_Party/FatFs/src/ff.c **** WCHAR ch, si; +5392:Middlewares/Third_Party/FatFs/src/ff.c **** UINT j, st; +5393:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE b; +5394:Middlewares/Third_Party/FatFs/src/ff.c **** +5395:Middlewares/Third_Party/FatFs/src/ff.c **** if (sz_vol < 0x1000) return FR_MKFS_ABORTED; /* Too small volume? */ +5396:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_TRIM +5397:Middlewares/Third_Party/FatFs/src/ff.c **** tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1; /* Inform the device the volume area may be erased * +5398:Middlewares/Third_Party/FatFs/src/ff.c **** disk_ioctl(pdrv, CTRL_TRIM, tbl); +5399:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +5400:Middlewares/Third_Party/FatFs/src/ff.c **** /* Determine FAT location, data location and number of clusters */ +5401:Middlewares/Third_Party/FatFs/src/ff.c **** if (!au) { /* au auto-selection */ +5402:Middlewares/Third_Party/FatFs/src/ff.c **** au = 8; +5403:Middlewares/Third_Party/FatFs/src/ff.c **** if (sz_vol >= 0x80000) au = 64; /* >= 512Ks */ +5404:Middlewares/Third_Party/FatFs/src/ff.c **** if (sz_vol >= 0x4000000) au = 256; /* >= 64Ms */ +5405:Middlewares/Third_Party/FatFs/src/ff.c **** } +5406:Middlewares/Third_Party/FatFs/src/ff.c **** b_fat = b_vol + 32; /* FAT start at offset 32 */ +5407:Middlewares/Third_Party/FatFs/src/ff.c **** sz_fat = ((sz_vol / au + 2) * 4 + ss - 1) / ss; /* Number of FAT sectors */ +5408:Middlewares/Third_Party/FatFs/src/ff.c **** b_data = (b_fat + sz_fat + sz_blk - 1) & ~(sz_blk - 1); /* Align data area to the erase block bou +5409:Middlewares/Third_Party/FatFs/src/ff.c **** if (b_data >= sz_vol / 2) return FR_MKFS_ABORTED; /* Too small volume? */ +5410:Middlewares/Third_Party/FatFs/src/ff.c **** n_clst = (sz_vol - (b_data - b_vol)) / au; /* Number of clusters */ +5411:Middlewares/Third_Party/FatFs/src/ff.c **** if (n_clst <16) return FR_MKFS_ABORTED; /* Too few clusters? */ +5412:Middlewares/Third_Party/FatFs/src/ff.c **** if (n_clst > MAX_EXFAT) return FR_MKFS_ABORTED; /* Too many clusters? */ +5413:Middlewares/Third_Party/FatFs/src/ff.c **** +5414:Middlewares/Third_Party/FatFs/src/ff.c **** szb_bit = (n_clst + 7) / 8; /* Size of allocation bitmap */ +5415:Middlewares/Third_Party/FatFs/src/ff.c **** tbl[0] = (szb_bit + au * ss - 1) / (au * ss); /* Number of allocation bitmap clusters */ +5416:Middlewares/Third_Party/FatFs/src/ff.c **** +5417:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create a compressed up-case table */ +5418:Middlewares/Third_Party/FatFs/src/ff.c **** sect = b_data + au * tbl[0]; /* Table start sector */ +5419:Middlewares/Third_Party/FatFs/src/ff.c **** sum = 0; /* Table checksum to be stored in the 82 entry */ +5420:Middlewares/Third_Party/FatFs/src/ff.c **** st = si = i = j = szb_case = 0; +5421:Middlewares/Third_Party/FatFs/src/ff.c **** do { +5422:Middlewares/Third_Party/FatFs/src/ff.c **** switch (st) { +5423:Middlewares/Third_Party/FatFs/src/ff.c **** case 0: +5424:Middlewares/Third_Party/FatFs/src/ff.c **** ch = ff_wtoupper(si); /* Get an up-case char */ +5425:Middlewares/Third_Party/FatFs/src/ff.c **** if (ch != si) { +5426:Middlewares/Third_Party/FatFs/src/ff.c **** si++; break; /* Store the up-case char if exist */ +5427:Middlewares/Third_Party/FatFs/src/ff.c **** } +5428:Middlewares/Third_Party/FatFs/src/ff.c **** for (j = 1; (WCHAR)(si + j) && (WCHAR)(si + j) == ff_wtoupper((WCHAR)(si + j)); j++) ; /* Get r + ARM GAS /tmp/cc2SVLkL.s page 127 + + +5429:Middlewares/Third_Party/FatFs/src/ff.c **** if (j >= 128) { +5430:Middlewares/Third_Party/FatFs/src/ff.c **** ch = 0xFFFF; st = 2; break; /* Compress the no-case block if run is >= 128 */ +5431:Middlewares/Third_Party/FatFs/src/ff.c **** } +5432:Middlewares/Third_Party/FatFs/src/ff.c **** st = 1; /* Do not compress short run */ +5433:Middlewares/Third_Party/FatFs/src/ff.c **** /* go to next case */ +5434:Middlewares/Third_Party/FatFs/src/ff.c **** case 1: +5435:Middlewares/Third_Party/FatFs/src/ff.c **** ch = si++; /* Fill the short run */ +5436:Middlewares/Third_Party/FatFs/src/ff.c **** if (--j == 0) st = 0; +5437:Middlewares/Third_Party/FatFs/src/ff.c **** break; +5438:Middlewares/Third_Party/FatFs/src/ff.c **** +5439:Middlewares/Third_Party/FatFs/src/ff.c **** default: +5440:Middlewares/Third_Party/FatFs/src/ff.c **** ch = (WCHAR)j; si += j; /* Number of chars to skip */ +5441:Middlewares/Third_Party/FatFs/src/ff.c **** st = 0; +5442:Middlewares/Third_Party/FatFs/src/ff.c **** } +5443:Middlewares/Third_Party/FatFs/src/ff.c **** sum = xsum32(buf[i + 0] = (BYTE)ch, sum); /* Put it into the write buffer */ +5444:Middlewares/Third_Party/FatFs/src/ff.c **** sum = xsum32(buf[i + 1] = (BYTE)(ch >> 8), sum); +5445:Middlewares/Third_Party/FatFs/src/ff.c **** i += 2; szb_case += 2; +5446:Middlewares/Third_Party/FatFs/src/ff.c **** if (!si || i == szb_buf) { /* Write buffered data when buffer full or end of process */ +5447:Middlewares/Third_Party/FatFs/src/ff.c **** n = (i + ss - 1) / ss; +5448:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR; +5449:Middlewares/Third_Party/FatFs/src/ff.c **** sect += n; i = 0; +5450:Middlewares/Third_Party/FatFs/src/ff.c **** } +5451:Middlewares/Third_Party/FatFs/src/ff.c **** } while (si); +5452:Middlewares/Third_Party/FatFs/src/ff.c **** tbl[1] = (szb_case + au * ss - 1) / (au * ss); /* Number of up-case table clusters */ +5453:Middlewares/Third_Party/FatFs/src/ff.c **** tbl[2] = 1; /* Number of root dir clusters */ +5454:Middlewares/Third_Party/FatFs/src/ff.c **** +5455:Middlewares/Third_Party/FatFs/src/ff.c **** /* Initialize the allocation bitmap */ +5456:Middlewares/Third_Party/FatFs/src/ff.c **** sect = b_data; nsect = (szb_bit + ss - 1) / ss; /* Start of bitmap and number of sectors */ +5457:Middlewares/Third_Party/FatFs/src/ff.c **** nb = tbl[0] + tbl[1] + tbl[2]; /* Number of clusters in-use by system */ +5458:Middlewares/Third_Party/FatFs/src/ff.c **** do { +5459:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, szb_buf); +5460:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; nb >= 8 && i < szb_buf; buf[i++] = 0xFF, nb -= 8) ; +5461:Middlewares/Third_Party/FatFs/src/ff.c **** for (b = 1; nb && i < szb_buf; buf[i] |= b, b <<= 1, nb--) ; +5462:Middlewares/Third_Party/FatFs/src/ff.c **** n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */ +5463:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR; +5464:Middlewares/Third_Party/FatFs/src/ff.c **** sect += n; nsect -= n; +5465:Middlewares/Third_Party/FatFs/src/ff.c **** } while (nsect); +5466:Middlewares/Third_Party/FatFs/src/ff.c **** +5467:Middlewares/Third_Party/FatFs/src/ff.c **** /* Initialize the FAT */ +5468:Middlewares/Third_Party/FatFs/src/ff.c **** sect = b_fat; nsect = sz_fat; /* Start of FAT and number of FAT sectors */ +5469:Middlewares/Third_Party/FatFs/src/ff.c **** j = nb = cl = 0; +5470:Middlewares/Third_Party/FatFs/src/ff.c **** do { +5471:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, szb_buf); i = 0; /* Clear work area and reset write index */ +5472:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl == 0) { /* Set entry 0 and 1 */ +5473:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + i, 0xFFFFFFF8); i += 4; cl++; +5474:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + i, 0xFFFFFFFF); i += 4; cl++; +5475:Middlewares/Third_Party/FatFs/src/ff.c **** } +5476:Middlewares/Third_Party/FatFs/src/ff.c **** do { /* Create chains of bitmap, up-case and root dir */ +5477:Middlewares/Third_Party/FatFs/src/ff.c **** while (nb && i < szb_buf) { /* Create a chain */ +5478:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + i, (nb > 1) ? cl + 1 : 0xFFFFFFFF); +5479:Middlewares/Third_Party/FatFs/src/ff.c **** i += 4; cl++; nb--; +5480:Middlewares/Third_Party/FatFs/src/ff.c **** } +5481:Middlewares/Third_Party/FatFs/src/ff.c **** if (!nb && j < 3) nb = tbl[j++]; /* Next chain */ +5482:Middlewares/Third_Party/FatFs/src/ff.c **** } while (nb && i < szb_buf); +5483:Middlewares/Third_Party/FatFs/src/ff.c **** n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */ +5484:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR; +5485:Middlewares/Third_Party/FatFs/src/ff.c **** sect += n; nsect -= n; + ARM GAS /tmp/cc2SVLkL.s page 128 + + +5486:Middlewares/Third_Party/FatFs/src/ff.c **** } while (nsect); +5487:Middlewares/Third_Party/FatFs/src/ff.c **** +5488:Middlewares/Third_Party/FatFs/src/ff.c **** /* Initialize the root directory */ +5489:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, szb_buf); +5490:Middlewares/Third_Party/FatFs/src/ff.c **** buf[SZDIRE * 0 + 0] = 0x83; /* 83 entry (volume label) */ +5491:Middlewares/Third_Party/FatFs/src/ff.c **** buf[SZDIRE * 1 + 0] = 0x81; /* 81 entry (allocation bitmap) */ +5492:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + SZDIRE * 1 + 20, 2); +5493:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + SZDIRE * 1 + 24, szb_bit); +5494:Middlewares/Third_Party/FatFs/src/ff.c **** buf[SZDIRE * 2 + 0] = 0x82; /* 82 entry (up-case table) */ +5495:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + SZDIRE * 2 + 4, sum); +5496:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + SZDIRE * 2 + 20, 2 + tbl[0]); +5497:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + SZDIRE * 2 + 24, szb_case); +5498:Middlewares/Third_Party/FatFs/src/ff.c **** sect = b_data + au * (tbl[0] + tbl[1]); nsect = au; /* Start of the root directory and number of +5499:Middlewares/Third_Party/FatFs/src/ff.c **** do { /* Fill root directory sectors */ +5500:Middlewares/Third_Party/FatFs/src/ff.c **** n = (nsect > sz_buf) ? sz_buf : nsect; +5501:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, sect, n) != RES_OK) return FR_DISK_ERR; +5502:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, ss); +5503:Middlewares/Third_Party/FatFs/src/ff.c **** sect += n; nsect -= n; +5504:Middlewares/Third_Party/FatFs/src/ff.c **** } while (nsect); +5505:Middlewares/Third_Party/FatFs/src/ff.c **** +5506:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create two set of the exFAT VBR blocks */ +5507:Middlewares/Third_Party/FatFs/src/ff.c **** sect = b_vol; +5508:Middlewares/Third_Party/FatFs/src/ff.c **** for (n = 0; n < 2; n++) { +5509:Middlewares/Third_Party/FatFs/src/ff.c **** /* Main record (+0) */ +5510:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, ss); +5511:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(buf + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11); /* Boot jump code (x86), OEM name */ +5512:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BPB_VolOfsEx, b_vol); /* Volume offset in the physical drive [sector] */ +5513:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BPB_TotSecEx, sz_vol); /* Volume size [sector] */ +5514:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BPB_FatOfsEx, b_fat - b_vol); /* FAT offset [sector] */ +5515:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BPB_FatSzEx, sz_fat); /* FAT size [sector] */ +5516:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BPB_DataOfsEx, b_data - b_vol); /* Data offset [sector] */ +5517:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BPB_NumClusEx, n_clst); /* Number of clusters */ +5518:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BPB_RootClusEx, 2 + tbl[0] + tbl[1]); /* Root dir cluster # */ +5519:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BPB_VolIDEx, GET_FATTIME()); /* VSN */ +5520:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_FSVerEx, 0x100); /* File system version (1.00) */ +5521:Middlewares/Third_Party/FatFs/src/ff.c **** for (buf[BPB_BytsPerSecEx] = 0, i = ss; i >>= 1; buf[BPB_BytsPerSecEx]++) ; /* Log2 of sector si +5522:Middlewares/Third_Party/FatFs/src/ff.c **** for (buf[BPB_SecPerClusEx] = 0, i = au; i >>= 1; buf[BPB_SecPerClusEx]++) ; /* Log2 of cluster s +5523:Middlewares/Third_Party/FatFs/src/ff.c **** buf[BPB_NumFATsEx] = 1; /* Number of FATs */ +5524:Middlewares/Third_Party/FatFs/src/ff.c **** buf[BPB_DrvNumEx] = 0x80; /* Drive number (for int13) */ +5525:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BS_BootCodeEx, 0xFEEB); /* Boot code (x86) */ +5526:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BS_55AA, 0xAA55); /* Signature (placed here regardless of sector size) */ +5527:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = sum = 0; i < ss; i++) { /* VBR checksum */ +5528:Middlewares/Third_Party/FatFs/src/ff.c **** if (i != BPB_VolFlagEx && i != BPB_VolFlagEx + 1 && i != BPB_PercInUseEx) sum = xsum32(buf[i], +5529:Middlewares/Third_Party/FatFs/src/ff.c **** } +5530:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR; +5531:Middlewares/Third_Party/FatFs/src/ff.c **** /* Extended bootstrap record (+1..+8) */ +5532:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, ss); +5533:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + ss - 2, 0xAA55); /* Signature (placed at end of sector) */ +5534:Middlewares/Third_Party/FatFs/src/ff.c **** for (j = 1; j < 9; j++) { +5535:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */ +5536:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR; +5537:Middlewares/Third_Party/FatFs/src/ff.c **** } +5538:Middlewares/Third_Party/FatFs/src/ff.c **** /* OEM/Reserved record (+9..+10) */ +5539:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, ss); +5540:Middlewares/Third_Party/FatFs/src/ff.c **** for ( ; j < 11; j++) { +5541:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */ +5542:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR; + ARM GAS /tmp/cc2SVLkL.s page 129 + + +5543:Middlewares/Third_Party/FatFs/src/ff.c **** } +5544:Middlewares/Third_Party/FatFs/src/ff.c **** /* Sum record (+11) */ +5545:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < ss; i += 4) st_dword(buf + i, sum); /* Fill with checksum value */ +5546:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, sect++, 1) != RES_OK) return FR_DISK_ERR; +5547:Middlewares/Third_Party/FatFs/src/ff.c **** } +5548:Middlewares/Third_Party/FatFs/src/ff.c **** +5549:Middlewares/Third_Party/FatFs/src/ff.c **** } else +5550:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _FS_EXFAT */ +5551:Middlewares/Third_Party/FatFs/src/ff.c **** { /* Create an FAT12/16/32 volume */ +5552:Middlewares/Third_Party/FatFs/src/ff.c **** do { +5553:Middlewares/Third_Party/FatFs/src/ff.c **** pau = au; +5554:Middlewares/Third_Party/FatFs/src/ff.c **** /* Pre-determine number of clusters and FAT sub-type */ +5555:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { /* FAT32 volume */ +5556:Middlewares/Third_Party/FatFs/src/ff.c **** if (!pau) { /* au auto-selection */ +5557:Middlewares/Third_Party/FatFs/src/ff.c **** n = sz_vol / 0x20000; /* Volume size in unit of 128KS */ +5558:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ; /* Get from table */ +5559:Middlewares/Third_Party/FatFs/src/ff.c **** } +5560:Middlewares/Third_Party/FatFs/src/ff.c **** n_clst = sz_vol / pau; /* Number of clusters */ +5561:Middlewares/Third_Party/FatFs/src/ff.c **** sz_fat = (n_clst * 4 + 8 + ss - 1) / ss; /* FAT size [sector] */ +5562:Middlewares/Third_Party/FatFs/src/ff.c **** sz_rsv = 32; /* Number of reserved sectors */ +5563:Middlewares/Third_Party/FatFs/src/ff.c **** sz_dir = 0; /* No static directory */ +5564:Middlewares/Third_Party/FatFs/src/ff.c **** if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) return FR_MKFS_ABORTED; +5565:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* FAT12/16 volume */ +5566:Middlewares/Third_Party/FatFs/src/ff.c **** if (!pau) { /* au auto-selection */ +5567:Middlewares/Third_Party/FatFs/src/ff.c **** n = sz_vol / 0x1000; /* Volume size in unit of 4KS */ +5568:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ; /* Get from table */ +5569:Middlewares/Third_Party/FatFs/src/ff.c **** } +5570:Middlewares/Third_Party/FatFs/src/ff.c **** n_clst = sz_vol / pau; +5571:Middlewares/Third_Party/FatFs/src/ff.c **** if (n_clst > MAX_FAT12) { +5572:Middlewares/Third_Party/FatFs/src/ff.c **** n = n_clst * 2 + 4; /* FAT size [byte] */ +5573:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +5574:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = FS_FAT12; +5575:Middlewares/Third_Party/FatFs/src/ff.c **** n = (n_clst * 3 + 1) / 2 + 3; /* FAT size [byte] */ +5576:Middlewares/Third_Party/FatFs/src/ff.c **** } +5577:Middlewares/Third_Party/FatFs/src/ff.c **** sz_fat = (n + ss - 1) / ss; /* FAT size [sector] */ +5578:Middlewares/Third_Party/FatFs/src/ff.c **** sz_rsv = 1; /* Number of reserved sectors */ +5579:Middlewares/Third_Party/FatFs/src/ff.c **** sz_dir = (DWORD)n_rootdir * SZDIRE / ss; /* Rootdir size [sector] */ +5580:Middlewares/Third_Party/FatFs/src/ff.c **** } +5581:Middlewares/Third_Party/FatFs/src/ff.c **** b_fat = b_vol + sz_rsv; /* FAT base */ +5582:Middlewares/Third_Party/FatFs/src/ff.c **** b_data = b_fat + sz_fat * n_fats + sz_dir; /* Data base */ +5583:Middlewares/Third_Party/FatFs/src/ff.c **** +5584:Middlewares/Third_Party/FatFs/src/ff.c **** /* Align data base to erase block boundary (for flash memory media) */ +5585:Middlewares/Third_Party/FatFs/src/ff.c **** n = ((b_data + sz_blk - 1) & ~(sz_blk - 1)) - b_data; /* Next nearest erase block from current d +5586:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { /* FAT32: Move FAT base */ +5587:Middlewares/Third_Party/FatFs/src/ff.c **** sz_rsv += n; b_fat += n; +5588:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* FAT12/16: Expand FAT size */ +5589:Middlewares/Third_Party/FatFs/src/ff.c **** sz_fat += n / n_fats; +5590:Middlewares/Third_Party/FatFs/src/ff.c **** } +5591:Middlewares/Third_Party/FatFs/src/ff.c **** +5592:Middlewares/Third_Party/FatFs/src/ff.c **** /* Determine number of clusters and final check of validity of the FAT sub-type */ +5593:Middlewares/Third_Party/FatFs/src/ff.c **** if (sz_vol < b_data + pau * 16 - b_vol) return FR_MKFS_ABORTED; /* Too small volume */ +5594:Middlewares/Third_Party/FatFs/src/ff.c **** n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau; +5595:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { +5596:Middlewares/Third_Party/FatFs/src/ff.c **** if (n_clst <= MAX_FAT16) { /* Too few clusters for FAT32 */ +5597:Middlewares/Third_Party/FatFs/src/ff.c **** if (!au && (au = pau / 2) != 0) continue; /* Adjust cluster size and retry */ +5598:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_MKFS_ABORTED; +5599:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 130 + + +5600:Middlewares/Third_Party/FatFs/src/ff.c **** } +5601:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT16) { +5602:Middlewares/Third_Party/FatFs/src/ff.c **** if (n_clst > MAX_FAT16) { /* Too many clusters for FAT16 */ +5603:Middlewares/Third_Party/FatFs/src/ff.c **** if (!au && (pau * 2) <= 64) { +5604:Middlewares/Third_Party/FatFs/src/ff.c **** au = pau * 2; continue; /* Adjust cluster size and retry */ +5605:Middlewares/Third_Party/FatFs/src/ff.c **** } +5606:Middlewares/Third_Party/FatFs/src/ff.c **** if ((opt & FM_FAT32)) { +5607:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = FS_FAT32; continue; /* Switch type to FAT32 and retry */ +5608:Middlewares/Third_Party/FatFs/src/ff.c **** } +5609:Middlewares/Third_Party/FatFs/src/ff.c **** if (!au && (au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */ +5610:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_MKFS_ABORTED; +5611:Middlewares/Third_Party/FatFs/src/ff.c **** } +5612:Middlewares/Third_Party/FatFs/src/ff.c **** if (n_clst <= MAX_FAT12) { /* Too few clusters for FAT16 */ +5613:Middlewares/Third_Party/FatFs/src/ff.c **** if (!au && (au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */ +5614:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_MKFS_ABORTED; +5615:Middlewares/Third_Party/FatFs/src/ff.c **** } +5616:Middlewares/Third_Party/FatFs/src/ff.c **** } +5617:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT12 && n_clst > MAX_FAT12) return FR_MKFS_ABORTED; /* Too many clusters for FAT1 +5618:Middlewares/Third_Party/FatFs/src/ff.c **** +5619:Middlewares/Third_Party/FatFs/src/ff.c **** /* Ok, it is the valid cluster configuration */ +5620:Middlewares/Third_Party/FatFs/src/ff.c **** break; +5621:Middlewares/Third_Party/FatFs/src/ff.c **** } while (1); +5622:Middlewares/Third_Party/FatFs/src/ff.c **** +5623:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_TRIM +5624:Middlewares/Third_Party/FatFs/src/ff.c **** tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1; /* Inform the device the volume area can be erased * +5625:Middlewares/Third_Party/FatFs/src/ff.c **** disk_ioctl(pdrv, CTRL_TRIM, tbl); +5626:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +5627:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create FAT VBR */ +5628:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, ss); +5629:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code (x86), OEM name */ +5630:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_BytsPerSec, ss); /* Sector size [byte] */ +5631:Middlewares/Third_Party/FatFs/src/ff.c **** buf[BPB_SecPerClus] = (BYTE)pau; /* Cluster size [sector] */ +5632:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv); /* Size of reserved area */ +5633:Middlewares/Third_Party/FatFs/src/ff.c **** buf[BPB_NumFATs] = (BYTE)n_fats; /* Number of FATs */ +5634:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_RootEntCnt, (WORD)((fmt == FS_FAT32) ? 0 : n_rootdir)); /* Number of root direc +5635:Middlewares/Third_Party/FatFs/src/ff.c **** if (sz_vol < 0x10000) { +5636:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_TotSec16, (WORD)sz_vol); /* Volume size in 16-bit LBA */ +5637:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +5638:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BPB_TotSec32, sz_vol); /* Volume size in 32-bit LBA */ +5639:Middlewares/Third_Party/FatFs/src/ff.c **** } +5640:Middlewares/Third_Party/FatFs/src/ff.c **** buf[BPB_Media] = 0xF8; /* Media descriptor byte */ +5641:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_SecPerTrk, 63); /* Number of sectors per track (for int13) */ +5642:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_NumHeads, 255); /* Number of heads (for int13) */ +5643:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BPB_HiddSec, b_vol); /* Volume offset in the physical drive [sector] */ +5644:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { +5645:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BS_VolID32, GET_FATTIME()); /* VSN */ +5646:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BPB_FATSz32, sz_fat); /* FAT size [sector] */ +5647:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BPB_RootClus32, 2); /* Root directory cluster # (2) */ +5648:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_FSInfo32, 1); /* Offset of FSINFO sector (VBR + 1) */ +5649:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_BkBootSec32, 6); /* Offset of backup VBR (VBR + 6) */ +5650:Middlewares/Third_Party/FatFs/src/ff.c **** buf[BS_DrvNum32] = 0x80; /* Drive number (for int13) */ +5651:Middlewares/Third_Party/FatFs/src/ff.c **** buf[BS_BootSig32] = 0x29; /* Extended boot signature */ +5652:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(buf + BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ +5653:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +5654:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BS_VolID, GET_FATTIME()); /* VSN */ +5655:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_FATSz16, (WORD)sz_fat); /* FAT size [sector] */ +5656:Middlewares/Third_Party/FatFs/src/ff.c **** buf[BS_DrvNum] = 0x80; /* Drive number (for int13) */ + ARM GAS /tmp/cc2SVLkL.s page 131 + + +5657:Middlewares/Third_Party/FatFs/src/ff.c **** buf[BS_BootSig] = 0x29; /* Extended boot signature */ +5658:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(buf + BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ +5659:Middlewares/Third_Party/FatFs/src/ff.c **** } +5660:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BS_55AA, 0xAA55); /* Signature (offset is fixed here regardless of sector size) +5661:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) return FR_DISK_ERR; /* Write it to the VBR sector +5662:Middlewares/Third_Party/FatFs/src/ff.c **** +5663:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create FSINFO record if needed */ +5664:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { +5665:Middlewares/Third_Party/FatFs/src/ff.c **** disk_write(pdrv, buf, b_vol + 6, 1); /* Write backup VBR (VBR + 6) */ +5666:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, ss); +5667:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + FSI_LeadSig, 0x41615252); +5668:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + FSI_StrucSig, 0x61417272); +5669:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + FSI_Free_Count, n_clst - 1); /* Number of free clusters */ +5670:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + FSI_Nxt_Free, 2); /* Last allocated cluster# */ +5671:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BS_55AA, 0xAA55); +5672:Middlewares/Third_Party/FatFs/src/ff.c **** disk_write(pdrv, buf, b_vol + 7, 1); /* Write backup FSINFO (VBR + 7) */ +5673:Middlewares/Third_Party/FatFs/src/ff.c **** disk_write(pdrv, buf, b_vol + 1, 1); /* Write original FSINFO (VBR + 1) */ +5674:Middlewares/Third_Party/FatFs/src/ff.c **** } +5675:Middlewares/Third_Party/FatFs/src/ff.c **** +5676:Middlewares/Third_Party/FatFs/src/ff.c **** /* Initialize FAT area */ +5677:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, (UINT)szb_buf); +5678:Middlewares/Third_Party/FatFs/src/ff.c **** sect = b_fat; /* FAT start sector */ +5679:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < n_fats; i++) { /* Initialize FATs each */ +5680:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { +5681:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + 0, 0xFFFFFFF8); /* Entry 0 */ +5682:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + 4, 0xFFFFFFFF); /* Entry 1 */ +5683:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + 8, 0x0FFFFFFF); /* Entry 2 (root directory) */ +5684:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +5685:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + 0, (fmt == FS_FAT12) ? 0xFFFFF8 : 0xFFFFFFF8); /* Entry 0 and 1 */ +5686:Middlewares/Third_Party/FatFs/src/ff.c **** } +5687:Middlewares/Third_Party/FatFs/src/ff.c **** nsect = sz_fat; /* Number of FAT sectors */ +5688:Middlewares/Third_Party/FatFs/src/ff.c **** do { /* Fill FAT sectors */ +5689:Middlewares/Third_Party/FatFs/src/ff.c **** n = (nsect > sz_buf) ? sz_buf : nsect; +5690:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR; +5691:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, ss); +5692:Middlewares/Third_Party/FatFs/src/ff.c **** sect += n; nsect -= n; +5693:Middlewares/Third_Party/FatFs/src/ff.c **** } while (nsect); +5694:Middlewares/Third_Party/FatFs/src/ff.c **** } +5695:Middlewares/Third_Party/FatFs/src/ff.c **** +5696:Middlewares/Third_Party/FatFs/src/ff.c **** /* Initialize root directory (fill with zero) */ +5697:Middlewares/Third_Party/FatFs/src/ff.c **** nsect = (fmt == FS_FAT32) ? pau : sz_dir; /* Number of root directory sectors */ +5698:Middlewares/Third_Party/FatFs/src/ff.c **** do { +5699:Middlewares/Third_Party/FatFs/src/ff.c **** n = (nsect > sz_buf) ? sz_buf : nsect; +5700:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR; +5701:Middlewares/Third_Party/FatFs/src/ff.c **** sect += n; nsect -= n; +5702:Middlewares/Third_Party/FatFs/src/ff.c **** } while (nsect); +5703:Middlewares/Third_Party/FatFs/src/ff.c **** } +5704:Middlewares/Third_Party/FatFs/src/ff.c **** +5705:Middlewares/Third_Party/FatFs/src/ff.c **** /* Determine system ID in the partition table */ +5706:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_EXFAT && fmt == FS_EXFAT) { +5707:Middlewares/Third_Party/FatFs/src/ff.c **** sys = 0x07; /* HPFS/NTFS/exFAT */ +5708:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +5709:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { +5710:Middlewares/Third_Party/FatFs/src/ff.c **** sys = 0x0C; /* FAT32X */ +5711:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +5712:Middlewares/Third_Party/FatFs/src/ff.c **** if (sz_vol >= 0x10000) { +5713:Middlewares/Third_Party/FatFs/src/ff.c **** sys = 0x06; /* FAT12/16 (>=64KS) */ + ARM GAS /tmp/cc2SVLkL.s page 132 + + +5714:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +5715:Middlewares/Third_Party/FatFs/src/ff.c **** sys = (fmt == FS_FAT16) ? 0x04 : 0x01; /* FAT16 (<64KS) : FAT12 (<64KS) */ +5716:Middlewares/Third_Party/FatFs/src/ff.c **** } +5717:Middlewares/Third_Party/FatFs/src/ff.c **** } +5718:Middlewares/Third_Party/FatFs/src/ff.c **** } +5719:Middlewares/Third_Party/FatFs/src/ff.c **** +5720:Middlewares/Third_Party/FatFs/src/ff.c **** /* Update partition information */ +5721:Middlewares/Third_Party/FatFs/src/ff.c **** if (_MULTI_PARTITION && part != 0) { /* Created in the existing partition */ +5722:Middlewares/Third_Party/FatFs/src/ff.c **** /* Update system ID in the partition table */ +5723:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_read(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; /* Read the MBR */ +5724:Middlewares/Third_Party/FatFs/src/ff.c **** buf[MBR_Table + (part - 1) * SZ_PTE + PTE_System] = sys; /* Set system ID */ +5725:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; /* Write it back to the MBR */ +5726:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* Created as a new single partition */ +5727:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(opt & FM_SFD)) { /* Create partition table if in FDISK format */ +5728:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, ss); +5729:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BS_55AA, 0xAA55); /* MBR signature */ +5730:Middlewares/Third_Party/FatFs/src/ff.c **** pte = buf + MBR_Table; /* Create partition table for single partition in the drive */ +5731:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_Boot] = 0; /* Boot indicator */ +5732:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_StHead] = 1; /* Start head */ +5733:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_StSec] = 1; /* Start sector */ +5734:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_StCyl] = 0; /* Start cylinder */ +5735:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_System] = sys; /* System type */ +5736:Middlewares/Third_Party/FatFs/src/ff.c **** n = (b_vol + sz_vol) / (63 * 255); /* (End CHS may be invalid) */ +5737:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_EdHead] = 254; /* End head */ +5738:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_EdSec] = (BYTE)(n >> 2 | 63); /* End sector */ +5739:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_EdCyl] = (BYTE)n; /* End cylinder */ +5740:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(pte + PTE_StLba, b_vol); /* Start offset in LBA */ +5741:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(pte + PTE_SizLba, sz_vol); /* Size in sectors */ +5742:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; /* Write it to the MBR */ +5743:Middlewares/Third_Party/FatFs/src/ff.c **** } +5744:Middlewares/Third_Party/FatFs/src/ff.c **** } +5745:Middlewares/Third_Party/FatFs/src/ff.c **** +5746:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) return FR_DISK_ERR; +5747:Middlewares/Third_Party/FatFs/src/ff.c **** +5748:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_OK; +5749:Middlewares/Third_Party/FatFs/src/ff.c **** } +5750:Middlewares/Third_Party/FatFs/src/ff.c **** +5751:Middlewares/Third_Party/FatFs/src/ff.c **** +5752:Middlewares/Third_Party/FatFs/src/ff.c **** +5753:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MULTI_PARTITION +5754:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +5755:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create partition table on the physical drive */ +5756:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +5757:Middlewares/Third_Party/FatFs/src/ff.c **** +5758:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT f_fdisk ( +5759:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE pdrv, /* Physical drive number */ +5760:Middlewares/Third_Party/FatFs/src/ff.c **** const DWORD* szt, /* Pointer to the size table for each partitions */ +5761:Middlewares/Third_Party/FatFs/src/ff.c **** void* work /* Pointer to the working buffer */ +5762:Middlewares/Third_Party/FatFs/src/ff.c **** ) +5763:Middlewares/Third_Party/FatFs/src/ff.c **** { +5764:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl; +5765:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE s_hd, e_hd, *p, *buf = (BYTE*)work; +5766:Middlewares/Third_Party/FatFs/src/ff.c **** DSTATUS stat; +5767:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD sz_disk, sz_part, s_part; +5768:Middlewares/Third_Party/FatFs/src/ff.c **** +5769:Middlewares/Third_Party/FatFs/src/ff.c **** +5770:Middlewares/Third_Party/FatFs/src/ff.c **** stat = disk_initialize(pdrv); + ARM GAS /tmp/cc2SVLkL.s page 133 + + +5771:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat & STA_NOINIT) return FR_NOT_READY; +5772:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; +5773:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR; +5774:Middlewares/Third_Party/FatFs/src/ff.c **** +5775:Middlewares/Third_Party/FatFs/src/ff.c **** /* Determine the CHS without any consideration of the drive geometry */ +5776:Middlewares/Third_Party/FatFs/src/ff.c **** for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ; +5777:Middlewares/Third_Party/FatFs/src/ff.c **** if (n == 256) n--; +5778:Middlewares/Third_Party/FatFs/src/ff.c **** e_hd = n - 1; +5779:Middlewares/Third_Party/FatFs/src/ff.c **** sz_cyl = 63 * n; +5780:Middlewares/Third_Party/FatFs/src/ff.c **** tot_cyl = sz_disk / sz_cyl; +5781:Middlewares/Third_Party/FatFs/src/ff.c **** +5782:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create partition table */ +5783:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, _MAX_SS); +5784:Middlewares/Third_Party/FatFs/src/ff.c **** p = buf + MBR_Table; b_cyl = 0; +5785:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < 4; i++, p += SZ_PTE) { +5786:Middlewares/Third_Party/FatFs/src/ff.c **** p_cyl = (szt[i] <= 100U) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl; /* Number of cylinder +5787:Middlewares/Third_Party/FatFs/src/ff.c **** if (!p_cyl) continue; +5788:Middlewares/Third_Party/FatFs/src/ff.c **** s_part = (DWORD)sz_cyl * b_cyl; +5789:Middlewares/Third_Party/FatFs/src/ff.c **** sz_part = (DWORD)sz_cyl * p_cyl; +5790:Middlewares/Third_Party/FatFs/src/ff.c **** if (i == 0) { /* Exclude first track of cylinder 0 */ +5791:Middlewares/Third_Party/FatFs/src/ff.c **** s_hd = 1; +5792:Middlewares/Third_Party/FatFs/src/ff.c **** s_part += 63; sz_part -= 63; +5793:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +5794:Middlewares/Third_Party/FatFs/src/ff.c **** s_hd = 0; +5795:Middlewares/Third_Party/FatFs/src/ff.c **** } +5796:Middlewares/Third_Party/FatFs/src/ff.c **** e_cyl = b_cyl + p_cyl - 1; /* End cylinder */ +5797:Middlewares/Third_Party/FatFs/src/ff.c **** if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER; +5798:Middlewares/Third_Party/FatFs/src/ff.c **** +5799:Middlewares/Third_Party/FatFs/src/ff.c **** /* Set partition table */ +5800:Middlewares/Third_Party/FatFs/src/ff.c **** p[1] = s_hd; /* Start head */ +5801:Middlewares/Third_Party/FatFs/src/ff.c **** p[2] = (BYTE)((b_cyl >> 2) + 1); /* Start sector */ +5802:Middlewares/Third_Party/FatFs/src/ff.c **** p[3] = (BYTE)b_cyl; /* Start cylinder */ +5803:Middlewares/Third_Party/FatFs/src/ff.c **** p[4] = 0x07; /* System type (temporary setting) */ +5804:Middlewares/Third_Party/FatFs/src/ff.c **** p[5] = e_hd; /* End head */ +5805:Middlewares/Third_Party/FatFs/src/ff.c **** p[6] = (BYTE)((e_cyl >> 2) + 63); /* End sector */ +5806:Middlewares/Third_Party/FatFs/src/ff.c **** p[7] = (BYTE)e_cyl; /* End cylinder */ +5807:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(p + 8, s_part); /* Start sector in LBA */ +5808:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(p + 12, sz_part); /* Number of sectors */ +5809:Middlewares/Third_Party/FatFs/src/ff.c **** +5810:Middlewares/Third_Party/FatFs/src/ff.c **** /* Next partition */ +5811:Middlewares/Third_Party/FatFs/src/ff.c **** b_cyl += p_cyl; +5812:Middlewares/Third_Party/FatFs/src/ff.c **** } +5813:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(p, 0xAA55); +5814:Middlewares/Third_Party/FatFs/src/ff.c **** +5815:Middlewares/Third_Party/FatFs/src/ff.c **** /* Write it to the MBR */ +5816:Middlewares/Third_Party/FatFs/src/ff.c **** return (disk_write(pdrv, buf, 0, 1) != RES_OK || disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) ? FR_DI +5817:Middlewares/Third_Party/FatFs/src/ff.c **** } +5818:Middlewares/Third_Party/FatFs/src/ff.c **** +5819:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _MULTI_PARTITION */ +5820:Middlewares/Third_Party/FatFs/src/ff.c **** #endif /* _USE_MKFS && !_FS_READONLY */ +5821:Middlewares/Third_Party/FatFs/src/ff.c **** +5822:Middlewares/Third_Party/FatFs/src/ff.c **** +5823:Middlewares/Third_Party/FatFs/src/ff.c **** +5824:Middlewares/Third_Party/FatFs/src/ff.c **** +5825:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_STRFUNC +5826:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +5827:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get a string from the file */ + ARM GAS /tmp/cc2SVLkL.s page 134 + + +5828:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +5829:Middlewares/Third_Party/FatFs/src/ff.c **** +5830:Middlewares/Third_Party/FatFs/src/ff.c **** TCHAR* f_gets ( +5831:Middlewares/Third_Party/FatFs/src/ff.c **** TCHAR* buff, /* Pointer to the string buffer to read */ +5832:Middlewares/Third_Party/FatFs/src/ff.c **** int len, /* Size of string buffer (characters) */ +5833:Middlewares/Third_Party/FatFs/src/ff.c **** FIL* fp /* Pointer to the file object */ +5834:Middlewares/Third_Party/FatFs/src/ff.c **** ) +5835:Middlewares/Third_Party/FatFs/src/ff.c **** { +5836:Middlewares/Third_Party/FatFs/src/ff.c **** int n = 0; +5837:Middlewares/Third_Party/FatFs/src/ff.c **** TCHAR c, *p = buff; +5838:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE s[2]; +5839:Middlewares/Third_Party/FatFs/src/ff.c **** UINT rc; +5840:Middlewares/Third_Party/FatFs/src/ff.c **** +5841:Middlewares/Third_Party/FatFs/src/ff.c **** +5842:Middlewares/Third_Party/FatFs/src/ff.c **** while (n < len - 1) { /* Read characters until buffer gets filled */ +5843:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE +5844:Middlewares/Third_Party/FatFs/src/ff.c **** #if _STRF_ENCODE == 3 /* Read a character in UTF-8 */ +5845:Middlewares/Third_Party/FatFs/src/ff.c **** f_read(fp, s, 1, &rc); +5846:Middlewares/Third_Party/FatFs/src/ff.c **** if (rc != 1) break; +5847:Middlewares/Third_Party/FatFs/src/ff.c **** c = s[0]; +5848:Middlewares/Third_Party/FatFs/src/ff.c **** if (c >= 0x80) { +5849:Middlewares/Third_Party/FatFs/src/ff.c **** if (c < 0xC0) continue; /* Skip stray trailer */ +5850:Middlewares/Third_Party/FatFs/src/ff.c **** if (c < 0xE0) { /* Two-byte sequence (0x80-0x7FF) */ +5851:Middlewares/Third_Party/FatFs/src/ff.c **** f_read(fp, s, 1, &rc); +5852:Middlewares/Third_Party/FatFs/src/ff.c **** if (rc != 1) break; +5853:Middlewares/Third_Party/FatFs/src/ff.c **** c = (c & 0x1F) << 6 | (s[0] & 0x3F); +5854:Middlewares/Third_Party/FatFs/src/ff.c **** if (c < 0x80) c = '?'; /* Reject invalid code range */ +5855:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +5856:Middlewares/Third_Party/FatFs/src/ff.c **** if (c < 0xF0) { /* Three-byte sequence (0x800-0xFFFF) */ +5857:Middlewares/Third_Party/FatFs/src/ff.c **** f_read(fp, s, 2, &rc); +5858:Middlewares/Third_Party/FatFs/src/ff.c **** if (rc != 2) break; +5859:Middlewares/Third_Party/FatFs/src/ff.c **** c = c << 12 | (s[0] & 0x3F) << 6 | (s[1] & 0x3F); +5860:Middlewares/Third_Party/FatFs/src/ff.c **** if (c < 0x800) c = '?'; /* Reject invalid code range */ +5861:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* Reject four-byte sequence */ +5862:Middlewares/Third_Party/FatFs/src/ff.c **** c = '?'; +5863:Middlewares/Third_Party/FatFs/src/ff.c **** } +5864:Middlewares/Third_Party/FatFs/src/ff.c **** } +5865:Middlewares/Third_Party/FatFs/src/ff.c **** } +5866:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _STRF_ENCODE == 2 /* Read a character in UTF-16BE */ +5867:Middlewares/Third_Party/FatFs/src/ff.c **** f_read(fp, s, 2, &rc); +5868:Middlewares/Third_Party/FatFs/src/ff.c **** if (rc != 2) break; +5869:Middlewares/Third_Party/FatFs/src/ff.c **** c = s[1] + (s[0] << 8); +5870:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _STRF_ENCODE == 1 /* Read a character in UTF-16LE */ +5871:Middlewares/Third_Party/FatFs/src/ff.c **** f_read(fp, s, 2, &rc); +5872:Middlewares/Third_Party/FatFs/src/ff.c **** if (rc != 2) break; +5873:Middlewares/Third_Party/FatFs/src/ff.c **** c = s[0] + (s[1] << 8); +5874:Middlewares/Third_Party/FatFs/src/ff.c **** #else /* Read a character in ANSI/OEM */ +5875:Middlewares/Third_Party/FatFs/src/ff.c **** f_read(fp, s, 1, &rc); +5876:Middlewares/Third_Party/FatFs/src/ff.c **** if (rc != 1) break; +5877:Middlewares/Third_Party/FatFs/src/ff.c **** c = s[0]; +5878:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsDBCS1(c)) { +5879:Middlewares/Third_Party/FatFs/src/ff.c **** f_read(fp, s, 1, &rc); +5880:Middlewares/Third_Party/FatFs/src/ff.c **** if (rc != 1) break; +5881:Middlewares/Third_Party/FatFs/src/ff.c **** c = (c << 8) + s[0]; +5882:Middlewares/Third_Party/FatFs/src/ff.c **** } +5883:Middlewares/Third_Party/FatFs/src/ff.c **** c = ff_convert(c, 1); /* OEM -> Unicode */ +5884:Middlewares/Third_Party/FatFs/src/ff.c **** if (!c) c = '?'; + ARM GAS /tmp/cc2SVLkL.s page 135 + + +5885:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +5886:Middlewares/Third_Party/FatFs/src/ff.c **** #else /* Read a character without conversion */ +5887:Middlewares/Third_Party/FatFs/src/ff.c **** f_read(fp, s, 1, &rc); +5888:Middlewares/Third_Party/FatFs/src/ff.c **** if (rc != 1) break; +5889:Middlewares/Third_Party/FatFs/src/ff.c **** c = s[0]; +5890:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +5891:Middlewares/Third_Party/FatFs/src/ff.c **** if (_USE_STRFUNC == 2 && c == '\r') continue; /* Strip '\r' */ +5892:Middlewares/Third_Party/FatFs/src/ff.c **** *p++ = c; +5893:Middlewares/Third_Party/FatFs/src/ff.c **** n++; +5894:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == '\n') break; /* Break on EOL */ +5895:Middlewares/Third_Party/FatFs/src/ff.c **** } +5896:Middlewares/Third_Party/FatFs/src/ff.c **** *p = 0; +5897:Middlewares/Third_Party/FatFs/src/ff.c **** return n ? buff : 0; /* When no data read (eof or error), return with error. */ +5898:Middlewares/Third_Party/FatFs/src/ff.c **** } +5899:Middlewares/Third_Party/FatFs/src/ff.c **** +5900:Middlewares/Third_Party/FatFs/src/ff.c **** +5901:Middlewares/Third_Party/FatFs/src/ff.c **** +5902:Middlewares/Third_Party/FatFs/src/ff.c **** +5903:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY +5904:Middlewares/Third_Party/FatFs/src/ff.c **** #include +5905:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +5906:Middlewares/Third_Party/FatFs/src/ff.c **** /* Put a character to the file */ +5907:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +5908:Middlewares/Third_Party/FatFs/src/ff.c **** +5909:Middlewares/Third_Party/FatFs/src/ff.c **** typedef struct { +5910:Middlewares/Third_Party/FatFs/src/ff.c **** FIL *fp; /* Ptr to the writing file */ +5911:Middlewares/Third_Party/FatFs/src/ff.c **** int idx, nchr; /* Write index of buf[] (-1:error), number of chars written */ +5912:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE buf[64]; /* Write buffer */ +5913:Middlewares/Third_Party/FatFs/src/ff.c **** } putbuff; +5914:Middlewares/Third_Party/FatFs/src/ff.c **** +5915:Middlewares/Third_Party/FatFs/src/ff.c **** +5916:Middlewares/Third_Party/FatFs/src/ff.c **** static +5917:Middlewares/Third_Party/FatFs/src/ff.c **** void putc_bfd ( /* Buffered write with code conversion */ +5918:Middlewares/Third_Party/FatFs/src/ff.c **** putbuff* pb, +5919:Middlewares/Third_Party/FatFs/src/ff.c **** TCHAR c +5920:Middlewares/Third_Party/FatFs/src/ff.c **** ) +5921:Middlewares/Third_Party/FatFs/src/ff.c **** { +5922:Middlewares/Third_Party/FatFs/src/ff.c **** UINT bw; +5923:Middlewares/Third_Party/FatFs/src/ff.c **** int i; +5924:Middlewares/Third_Party/FatFs/src/ff.c **** +5925:Middlewares/Third_Party/FatFs/src/ff.c **** +5926:Middlewares/Third_Party/FatFs/src/ff.c **** if (_USE_STRFUNC == 2 && c == '\n') { /* LF -> CRLF conversion */ +5927:Middlewares/Third_Party/FatFs/src/ff.c **** putc_bfd(pb, '\r'); +5928:Middlewares/Third_Party/FatFs/src/ff.c **** } +5929:Middlewares/Third_Party/FatFs/src/ff.c **** +5930:Middlewares/Third_Party/FatFs/src/ff.c **** i = pb->idx; /* Write index of pb->buf[] */ +5931:Middlewares/Third_Party/FatFs/src/ff.c **** if (i < 0) return; +5932:Middlewares/Third_Party/FatFs/src/ff.c **** +5933:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE +5934:Middlewares/Third_Party/FatFs/src/ff.c **** #if _STRF_ENCODE == 3 /* Write a character in UTF-8 */ +5935:Middlewares/Third_Party/FatFs/src/ff.c **** if (c < 0x80) { /* 7-bit */ +5936:Middlewares/Third_Party/FatFs/src/ff.c **** pb->buf[i++] = (BYTE)c; +5937:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +5938:Middlewares/Third_Party/FatFs/src/ff.c **** if (c < 0x800) { /* 11-bit */ +5939:Middlewares/Third_Party/FatFs/src/ff.c **** pb->buf[i++] = (BYTE)(0xC0 | c >> 6); +5940:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* 16-bit */ +5941:Middlewares/Third_Party/FatFs/src/ff.c **** pb->buf[i++] = (BYTE)(0xE0 | c >> 12); + ARM GAS /tmp/cc2SVLkL.s page 136 + + +5942:Middlewares/Third_Party/FatFs/src/ff.c **** pb->buf[i++] = (BYTE)(0x80 | (c >> 6 & 0x3F)); +5943:Middlewares/Third_Party/FatFs/src/ff.c **** } +5944:Middlewares/Third_Party/FatFs/src/ff.c **** pb->buf[i++] = (BYTE)(0x80 | (c & 0x3F)); +5945:Middlewares/Third_Party/FatFs/src/ff.c **** } +5946:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _STRF_ENCODE == 2 /* Write a character in UTF-16BE */ +5947:Middlewares/Third_Party/FatFs/src/ff.c **** pb->buf[i++] = (BYTE)(c >> 8); +5948:Middlewares/Third_Party/FatFs/src/ff.c **** pb->buf[i++] = (BYTE)c; +5949:Middlewares/Third_Party/FatFs/src/ff.c **** #elif _STRF_ENCODE == 1 /* Write a character in UTF-16LE */ +5950:Middlewares/Third_Party/FatFs/src/ff.c **** pb->buf[i++] = (BYTE)c; +5951:Middlewares/Third_Party/FatFs/src/ff.c **** pb->buf[i++] = (BYTE)(c >> 8); +5952:Middlewares/Third_Party/FatFs/src/ff.c **** #else /* Write a character in ANSI/OEM */ +5953:Middlewares/Third_Party/FatFs/src/ff.c **** c = ff_convert(c, 0); /* Unicode -> OEM */ +5954:Middlewares/Third_Party/FatFs/src/ff.c **** if (!c) c = '?'; +5955:Middlewares/Third_Party/FatFs/src/ff.c **** if (c >= 0x100) +5956:Middlewares/Third_Party/FatFs/src/ff.c **** pb->buf[i++] = (BYTE)(c >> 8); +5957:Middlewares/Third_Party/FatFs/src/ff.c **** pb->buf[i++] = (BYTE)c; +5958:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +5959:Middlewares/Third_Party/FatFs/src/ff.c **** #else /* Write a character without conversion */ +5960:Middlewares/Third_Party/FatFs/src/ff.c **** pb->buf[i++] = (BYTE)c; +5961:Middlewares/Third_Party/FatFs/src/ff.c **** #endif +5962:Middlewares/Third_Party/FatFs/src/ff.c **** +5963:Middlewares/Third_Party/FatFs/src/ff.c **** if (i >= (int)(sizeof pb->buf) - 3) { /* Write buffered characters to the file */ +5964:Middlewares/Third_Party/FatFs/src/ff.c **** f_write(pb->fp, pb->buf, (UINT)i, &bw); +5965:Middlewares/Third_Party/FatFs/src/ff.c **** i = (bw == (UINT)i) ? 0 : -1; +5966:Middlewares/Third_Party/FatFs/src/ff.c **** } +5967:Middlewares/Third_Party/FatFs/src/ff.c **** pb->idx = i; +5968:Middlewares/Third_Party/FatFs/src/ff.c **** pb->nchr++; +5969:Middlewares/Third_Party/FatFs/src/ff.c **** } +5970:Middlewares/Third_Party/FatFs/src/ff.c **** +5971:Middlewares/Third_Party/FatFs/src/ff.c **** +5972:Middlewares/Third_Party/FatFs/src/ff.c **** static +5973:Middlewares/Third_Party/FatFs/src/ff.c **** int putc_flush ( /* Flush left characters in the buffer */ +5974:Middlewares/Third_Party/FatFs/src/ff.c **** putbuff* pb +5975:Middlewares/Third_Party/FatFs/src/ff.c **** ) +5976:Middlewares/Third_Party/FatFs/src/ff.c **** { +5977:Middlewares/Third_Party/FatFs/src/ff.c **** UINT nw; +5978:Middlewares/Third_Party/FatFs/src/ff.c **** +5979:Middlewares/Third_Party/FatFs/src/ff.c **** if ( pb->idx >= 0 /* Flush buffered characters to the file */ +5980:Middlewares/Third_Party/FatFs/src/ff.c **** && f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK +5981:Middlewares/Third_Party/FatFs/src/ff.c **** && (UINT)pb->idx == nw) return pb->nchr; +5982:Middlewares/Third_Party/FatFs/src/ff.c **** return EOF; +5983:Middlewares/Third_Party/FatFs/src/ff.c **** } +5984:Middlewares/Third_Party/FatFs/src/ff.c **** +5985:Middlewares/Third_Party/FatFs/src/ff.c **** +5986:Middlewares/Third_Party/FatFs/src/ff.c **** static +5987:Middlewares/Third_Party/FatFs/src/ff.c **** void putc_init ( /* Initialize write buffer */ +5988:Middlewares/Third_Party/FatFs/src/ff.c **** putbuff* pb, +5989:Middlewares/Third_Party/FatFs/src/ff.c **** FIL* fp +5990:Middlewares/Third_Party/FatFs/src/ff.c **** ) +5991:Middlewares/Third_Party/FatFs/src/ff.c **** { + 1636 .loc 1 5991 1 is_stmt 1 view -0 + 1637 .cfi_startproc + 1638 @ args = 0, pretend = 0, frame = 0 + 1639 @ frame_needed = 0, uses_anonymous_args = 0 + 1640 @ link register save eliminated. +5992:Middlewares/Third_Party/FatFs/src/ff.c **** pb->fp = fp; + 1641 .loc 1 5992 2 view .LVU493 + ARM GAS /tmp/cc2SVLkL.s page 137 + + + 1642 .loc 1 5992 9 is_stmt 0 view .LVU494 + 1643 0000 0160 str r1, [r0] +5993:Middlewares/Third_Party/FatFs/src/ff.c **** pb->nchr = pb->idx = 0; + 1644 .loc 1 5993 2 is_stmt 1 view .LVU495 + 1645 .loc 1 5993 21 is_stmt 0 view .LVU496 + 1646 0002 0023 movs r3, #0 + 1647 0004 4360 str r3, [r0, #4] + 1648 .loc 1 5993 11 view .LVU497 + 1649 0006 8360 str r3, [r0, #8] +5994:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1650 .loc 1 5994 1 view .LVU498 + 1651 0008 7047 bx lr + 1652 .cfi_endproc + 1653 .LFE1241: + 1655 .section .text.validate,"ax",%progbits + 1656 .align 1 + 1657 .syntax unified + 1658 .thumb + 1659 .thumb_func + 1661 validate: + 1662 .LVL178: + 1663 .LFB1220: +3220:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res = FR_INVALID_OBJECT; + 1664 .loc 1 3220 1 is_stmt 1 view -0 + 1665 .cfi_startproc + 1666 @ args = 0, pretend = 0, frame = 0 + 1667 @ frame_needed = 0, uses_anonymous_args = 0 +3220:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res = FR_INVALID_OBJECT; + 1668 .loc 1 3220 1 is_stmt 0 view .LVU500 + 1669 0000 38B5 push {r3, r4, r5, lr} + 1670 .LCFI14: + 1671 .cfi_def_cfa_offset 16 + 1672 .cfi_offset 3, -16 + 1673 .cfi_offset 4, -12 + 1674 .cfi_offset 5, -8 + 1675 .cfi_offset 14, -4 + 1676 0002 0D46 mov r5, r1 +3221:Middlewares/Third_Party/FatFs/src/ff.c **** + 1677 .loc 1 3221 2 is_stmt 1 view .LVU501 + 1678 .LVL179: +3224:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT + 1679 .loc 1 3224 2 view .LVU502 +3224:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT + 1680 .loc 1 3224 5 is_stmt 0 view .LVU503 + 1681 0004 0446 mov r4, r0 + 1682 0006 98B1 cbz r0, .L149 +3224:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT + 1683 .loc 1 3224 16 discriminator 1 view .LVU504 + 1684 0008 0368 ldr r3, [r0] +3224:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT + 1685 .loc 1 3224 10 discriminator 1 view .LVU505 + 1686 000a 9BB1 cbz r3, .L150 +3224:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT + 1687 .loc 1 3224 31 discriminator 2 view .LVU506 + 1688 000c 1A78 ldrb r2, [r3] @ zero_extendqisi2 +3224:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT + 1689 .loc 1 3224 21 discriminator 2 view .LVU507 + ARM GAS /tmp/cc2SVLkL.s page 138 + + + 1690 000e A2B1 cbz r2, .L151 +3224:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT + 1691 .loc 1 3224 47 discriminator 3 view .LVU508 + 1692 0010 8188 ldrh r1, [r0, #4] + 1693 .LVL180: +3224:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT + 1694 .loc 1 3224 62 discriminator 3 view .LVU509 + 1695 0012 DA88 ldrh r2, [r3, #6] +3224:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT + 1696 .loc 1 3224 41 discriminator 3 view .LVU510 + 1697 0014 9142 cmp r1, r2 + 1698 0016 03D0 beq .L155 +3221:Middlewares/Third_Party/FatFs/src/ff.c **** + 1699 .loc 1 3221 10 view .LVU511 + 1700 0018 0920 movs r0, #9 + 1701 .LVL181: +3241:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 1702 .loc 1 3241 33 discriminator 2 view .LVU512 + 1703 001a 0024 movs r4, #0 + 1704 .LVL182: + 1705 .L148: +3241:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 1706 .loc 1 3241 6 discriminator 4 view .LVU513 + 1707 001c 2C60 str r4, [r5] +3242:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1708 .loc 1 3242 2 is_stmt 1 view .LVU514 +3243:Middlewares/Third_Party/FatFs/src/ff.c **** + 1709 .loc 1 3243 1 is_stmt 0 view .LVU515 + 1710 001e 38BD pop {r3, r4, r5, pc} + 1711 .LVL183: + 1712 .L155: +3236:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; + 1713 .loc 1 3236 3 is_stmt 1 view .LVU516 +3236:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; + 1714 .loc 1 3236 9 is_stmt 0 view .LVU517 + 1715 0020 5878 ldrb r0, [r3, #1] @ zero_extendqisi2 + 1716 .LVL184: +3236:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; + 1717 .loc 1 3236 9 view .LVU518 + 1718 0022 FFF7FEFF bl disk_status + 1719 .LVL185: +3236:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; + 1720 .loc 1 3236 6 discriminator 1 view .LVU519 + 1721 0026 10F00100 ands r0, r0, #1 + 1722 002a 09D1 bne .L153 +3237:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1723 .loc 1 3237 4 is_stmt 1 view .LVU520 + 1724 .LVL186: +3241:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 1725 .loc 1 3241 2 view .LVU521 +3241:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 1726 .loc 1 3241 33 is_stmt 0 discriminator 1 view .LVU522 + 1727 002c 2468 ldr r4, [r4] + 1728 .LVL187: +3241:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 1729 .loc 1 3241 33 discriminator 1 view .LVU523 + 1730 002e F5E7 b .L148 + ARM GAS /tmp/cc2SVLkL.s page 139 + + + 1731 .LVL188: + 1732 .L149: +3221:Middlewares/Third_Party/FatFs/src/ff.c **** + 1733 .loc 1 3221 10 view .LVU524 + 1734 0030 0920 movs r0, #9 + 1735 .LVL189: +3221:Middlewares/Third_Party/FatFs/src/ff.c **** + 1736 .loc 1 3221 10 view .LVU525 + 1737 0032 F3E7 b .L148 + 1738 .LVL190: + 1739 .L150: +3241:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 1740 .loc 1 3241 33 discriminator 2 view .LVU526 + 1741 0034 1C46 mov r4, r3 +3221:Middlewares/Third_Party/FatFs/src/ff.c **** + 1742 .loc 1 3221 10 view .LVU527 + 1743 0036 0920 movs r0, #9 + 1744 .LVL191: +3221:Middlewares/Third_Party/FatFs/src/ff.c **** + 1745 .loc 1 3221 10 view .LVU528 + 1746 0038 F0E7 b .L148 + 1747 .LVL192: + 1748 .L151: +3221:Middlewares/Third_Party/FatFs/src/ff.c **** + 1749 .loc 1 3221 10 view .LVU529 + 1750 003a 0920 movs r0, #9 + 1751 .LVL193: +3241:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 1752 .loc 1 3241 33 discriminator 2 view .LVU530 + 1753 003c 0024 movs r4, #0 + 1754 .LVL194: +3241:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 1755 .loc 1 3241 33 discriminator 2 view .LVU531 + 1756 003e EDE7 b .L148 + 1757 .LVL195: + 1758 .L153: +3221:Middlewares/Third_Party/FatFs/src/ff.c **** + 1759 .loc 1 3221 10 view .LVU532 + 1760 0040 0920 movs r0, #9 +3241:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 1761 .loc 1 3241 33 discriminator 2 view .LVU533 + 1762 0042 0024 movs r4, #0 + 1763 .LVL196: +3241:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 1764 .loc 1 3241 33 discriminator 2 view .LVU534 + 1765 0044 EAE7 b .L148 + 1766 .cfi_endproc + 1767 .LFE1220: + 1769 .section .text.sync_window,"ax",%progbits + 1770 .align 1 + 1771 .syntax unified + 1772 .thumb + 1773 .thumb_func + 1775 sync_window: + 1776 .LVL197: + 1777 .LFB1196: + 886:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD wsect; + ARM GAS /tmp/cc2SVLkL.s page 140 + + + 1778 .loc 1 886 1 is_stmt 1 view -0 + 1779 .cfi_startproc + 1780 @ args = 0, pretend = 0, frame = 0 + 1781 @ frame_needed = 0, uses_anonymous_args = 0 + 886:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD wsect; + 1782 .loc 1 886 1 is_stmt 0 view .LVU536 + 1783 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 1784 .LCFI15: + 1785 .cfi_def_cfa_offset 24 + 1786 .cfi_offset 4, -24 + 1787 .cfi_offset 5, -20 + 1788 .cfi_offset 6, -16 + 1789 .cfi_offset 7, -12 + 1790 .cfi_offset 8, -8 + 1791 .cfi_offset 14, -4 + 887:Middlewares/Third_Party/FatFs/src/ff.c **** UINT nf; + 1792 .loc 1 887 2 is_stmt 1 view .LVU537 + 888:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res = FR_OK; + 1793 .loc 1 888 2 view .LVU538 + 889:Middlewares/Third_Party/FatFs/src/ff.c **** + 1794 .loc 1 889 2 view .LVU539 + 1795 .LVL198: + 892:Middlewares/Third_Party/FatFs/src/ff.c **** wsect = fs->winsect; /* Current sector number */ + 1796 .loc 1 892 2 view .LVU540 + 892:Middlewares/Third_Party/FatFs/src/ff.c **** wsect = fs->winsect; /* Current sector number */ + 1797 .loc 1 892 8 is_stmt 0 view .LVU541 + 1798 0004 C578 ldrb r5, [r0, #3] @ zero_extendqisi2 + 892:Middlewares/Third_Party/FatFs/src/ff.c **** wsect = fs->winsect; /* Current sector number */ + 1799 .loc 1 892 5 view .LVU542 + 1800 0006 15B9 cbnz r5, .L162 + 1801 .LVL199: + 1802 .L157: + 906:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1803 .loc 1 906 2 is_stmt 1 view .LVU543 + 907:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 1804 .loc 1 907 1 is_stmt 0 view .LVU544 + 1805 0008 2846 mov r0, r5 + 1806 000a BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 1807 .LVL200: + 1808 .L162: + 907:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 1809 .loc 1 907 1 view .LVU545 + 1810 000e 0446 mov r4, r0 + 893:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) { + 1811 .loc 1 893 3 is_stmt 1 view .LVU546 + 893:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) { + 1812 .loc 1 893 9 is_stmt 0 view .LVU547 + 1813 0010 076B ldr r7, [r0, #48] + 1814 .LVL201: + 894:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DISK_ERR; + 1815 .loc 1 894 3 is_stmt 1 view .LVU548 + 894:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DISK_ERR; + 1816 .loc 1 894 29 is_stmt 0 view .LVU549 + 1817 0012 00F13408 add r8, r0, #52 + 894:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DISK_ERR; + 1818 .loc 1 894 7 view .LVU550 + 1819 0016 0123 movs r3, #1 + ARM GAS /tmp/cc2SVLkL.s page 141 + + + 1820 0018 3A46 mov r2, r7 + 1821 001a 4146 mov r1, r8 + 1822 001c 4078 ldrb r0, [r0, #1] @ zero_extendqisi2 + 1823 .LVL202: + 894:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DISK_ERR; + 1824 .loc 1 894 7 view .LVU551 + 1825 001e FFF7FEFF bl disk_write + 1826 .LVL203: + 894:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DISK_ERR; + 1827 .loc 1 894 6 discriminator 1 view .LVU552 + 1828 0022 0546 mov r5, r0 + 1829 0024 A0B9 cbnz r0, .L160 + 897:Middlewares/Third_Party/FatFs/src/ff.c **** if (wsect - fs->fatbase < fs->fsize) { /* Is it in the FAT area? */ + 1830 .loc 1 897 4 is_stmt 1 view .LVU553 + 897:Middlewares/Third_Party/FatFs/src/ff.c **** if (wsect - fs->fatbase < fs->fsize) { /* Is it in the FAT area? */ + 1831 .loc 1 897 14 is_stmt 0 view .LVU554 + 1832 0026 0023 movs r3, #0 + 1833 0028 E370 strb r3, [r4, #3] + 898:Middlewares/Third_Party/FatFs/src/ff.c **** for (nf = fs->n_fats; nf >= 2; nf--) { /* Reflect the change to all FAT copies */ + 1834 .loc 1 898 4 is_stmt 1 view .LVU555 + 898:Middlewares/Third_Party/FatFs/src/ff.c **** for (nf = fs->n_fats; nf >= 2; nf--) { /* Reflect the change to all FAT copies */ + 1835 .loc 1 898 18 is_stmt 0 view .LVU556 + 1836 002a 636A ldr r3, [r4, #36] + 898:Middlewares/Third_Party/FatFs/src/ff.c **** for (nf = fs->n_fats; nf >= 2; nf--) { /* Reflect the change to all FAT copies */ + 1837 .loc 1 898 14 view .LVU557 + 1838 002c FB1A subs r3, r7, r3 + 898:Middlewares/Third_Party/FatFs/src/ff.c **** for (nf = fs->n_fats; nf >= 2; nf--) { /* Reflect the change to all FAT copies */ + 1839 .loc 1 898 32 view .LVU558 + 1840 002e E269 ldr r2, [r4, #28] + 898:Middlewares/Third_Party/FatFs/src/ff.c **** for (nf = fs->n_fats; nf >= 2; nf--) { /* Reflect the change to all FAT copies */ + 1841 .loc 1 898 7 view .LVU559 + 1842 0030 9342 cmp r3, r2 + 1843 0032 E9D2 bcs .L157 + 899:Middlewares/Third_Party/FatFs/src/ff.c **** wsect += fs->fsize; + 1844 .loc 1 899 5 is_stmt 1 view .LVU560 + 899:Middlewares/Third_Party/FatFs/src/ff.c **** wsect += fs->fsize; + 1845 .loc 1 899 17 is_stmt 0 view .LVU561 + 1846 0034 A678 ldrb r6, [r4, #2] @ zero_extendqisi2 + 1847 .LVL204: + 899:Middlewares/Third_Party/FatFs/src/ff.c **** wsect += fs->fsize; + 1848 .loc 1 899 5 view .LVU562 + 1849 0036 08E0 b .L158 + 1850 .L159: + 900:Middlewares/Third_Party/FatFs/src/ff.c **** disk_write(fs->drv, fs->win, wsect, 1); + 1851 .loc 1 900 6 is_stmt 1 view .LVU563 + 900:Middlewares/Third_Party/FatFs/src/ff.c **** disk_write(fs->drv, fs->win, wsect, 1); + 1852 .loc 1 900 17 is_stmt 0 view .LVU564 + 1853 0038 E369 ldr r3, [r4, #28] + 900:Middlewares/Third_Party/FatFs/src/ff.c **** disk_write(fs->drv, fs->win, wsect, 1); + 1854 .loc 1 900 12 view .LVU565 + 1855 003a 1F44 add r7, r7, r3 + 1856 .LVL205: + 901:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1857 .loc 1 901 6 is_stmt 1 view .LVU566 + 1858 003c 0123 movs r3, #1 + 1859 003e 3A46 mov r2, r7 + 1860 0040 4146 mov r1, r8 + ARM GAS /tmp/cc2SVLkL.s page 142 + + + 1861 0042 6078 ldrb r0, [r4, #1] @ zero_extendqisi2 + 1862 0044 FFF7FEFF bl disk_write + 1863 .LVL206: + 899:Middlewares/Third_Party/FatFs/src/ff.c **** wsect += fs->fsize; + 1864 .loc 1 899 38 discriminator 3 view .LVU567 + 1865 0048 013E subs r6, r6, #1 + 1866 .LVL207: + 1867 .L158: + 899:Middlewares/Third_Party/FatFs/src/ff.c **** wsect += fs->fsize; + 1868 .loc 1 899 30 discriminator 1 view .LVU568 + 1869 004a 012E cmp r6, #1 + 1870 004c F4D8 bhi .L159 + 899:Middlewares/Third_Party/FatFs/src/ff.c **** wsect += fs->fsize; + 1871 .loc 1 899 30 is_stmt 0 discriminator 1 view .LVU569 + 1872 004e DBE7 b .L157 + 1873 .LVL208: + 1874 .L160: + 895:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 1875 .loc 1 895 8 view .LVU570 + 1876 0050 0125 movs r5, #1 + 1877 0052 D9E7 b .L157 + 1878 .cfi_endproc + 1879 .LFE1196: + 1881 .section .text.move_window,"ax",%progbits + 1882 .align 1 + 1883 .syntax unified + 1884 .thumb + 1885 .thumb_func + 1887 move_window: + 1888 .LVL209: + 1889 .LFB1197: + 916:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res = FR_OK; + 1890 .loc 1 916 1 is_stmt 1 view -0 + 1891 .cfi_startproc + 1892 @ args = 0, pretend = 0, frame = 0 + 1893 @ frame_needed = 0, uses_anonymous_args = 0 + 916:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res = FR_OK; + 1894 .loc 1 916 1 is_stmt 0 view .LVU572 + 1895 0000 70B5 push {r4, r5, r6, lr} + 1896 .LCFI16: + 1897 .cfi_def_cfa_offset 16 + 1898 .cfi_offset 4, -16 + 1899 .cfi_offset 5, -12 + 1900 .cfi_offset 6, -8 + 1901 .cfi_offset 14, -4 + 917:Middlewares/Third_Party/FatFs/src/ff.c **** + 1902 .loc 1 917 2 is_stmt 1 view .LVU573 + 1903 .LVL210: + 920:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 1904 .loc 1 920 2 view .LVU574 + 920:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 1905 .loc 1 920 18 is_stmt 0 view .LVU575 + 1906 0002 036B ldr r3, [r0, #48] + 920:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 1907 .loc 1 920 5 view .LVU576 + 1908 0004 8B42 cmp r3, r1 + 1909 0006 02D1 bne .L169 + ARM GAS /tmp/cc2SVLkL.s page 143 + + + 917:Middlewares/Third_Party/FatFs/src/ff.c **** + 1910 .loc 1 917 10 view .LVU577 + 1911 0008 0026 movs r6, #0 + 1912 .LVL211: + 1913 .L164: + 932:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1914 .loc 1 932 2 is_stmt 1 view .LVU578 + 933:Middlewares/Third_Party/FatFs/src/ff.c **** + 1915 .loc 1 933 1 is_stmt 0 view .LVU579 + 1916 000a 3046 mov r0, r6 + 1917 000c 70BD pop {r4, r5, r6, pc} + 1918 .LVL212: + 1919 .L169: + 933:Middlewares/Third_Party/FatFs/src/ff.c **** + 1920 .loc 1 933 1 view .LVU580 + 1921 000e 0446 mov r4, r0 + 1922 0010 0D46 mov r5, r1 + 922:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 1923 .loc 1 922 3 is_stmt 1 view .LVU581 + 922:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 1924 .loc 1 922 9 is_stmt 0 view .LVU582 + 1925 0012 FFF7FEFF bl sync_window + 1926 .LVL213: + 924:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) { + 1927 .loc 1 924 3 is_stmt 1 view .LVU583 + 924:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) { + 1928 .loc 1 924 6 is_stmt 0 view .LVU584 + 1929 0016 0646 mov r6, r0 + 1930 0018 0028 cmp r0, #0 + 1931 001a F6D1 bne .L164 + 925:Middlewares/Third_Party/FatFs/src/ff.c **** sector = 0xFFFFFFFF; /* Invalidate window if data is not reliable */ + 1932 .loc 1 925 4 is_stmt 1 view .LVU585 + 925:Middlewares/Third_Party/FatFs/src/ff.c **** sector = 0xFFFFFFFF; /* Invalidate window if data is not reliable */ + 1933 .loc 1 925 8 is_stmt 0 view .LVU586 + 1934 001c 0123 movs r3, #1 + 1935 001e 2A46 mov r2, r5 + 1936 0020 04F13401 add r1, r4, #52 + 1937 0024 6078 ldrb r0, [r4, #1] @ zero_extendqisi2 + 1938 .LVL214: + 925:Middlewares/Third_Party/FatFs/src/ff.c **** sector = 0xFFFFFFFF; /* Invalidate window if data is not reliable */ + 1939 .loc 1 925 8 view .LVU587 + 1940 0026 FFF7FEFF bl disk_read + 1941 .LVL215: + 925:Middlewares/Third_Party/FatFs/src/ff.c **** sector = 0xFFFFFFFF; /* Invalidate window if data is not reliable */ + 1942 .loc 1 925 7 discriminator 1 view .LVU588 + 1943 002a 10B1 cbz r0, .L165 + 927:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1944 .loc 1 927 9 view .LVU589 + 1945 002c 0126 movs r6, #1 + 1946 .LVL216: + 926:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DISK_ERR; + 1947 .loc 1 926 12 view .LVU590 + 1948 002e 4FF0FF35 mov r5, #-1 + 1949 .LVL217: + 1950 .L165: + 929:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1951 .loc 1 929 4 is_stmt 1 view .LVU591 + ARM GAS /tmp/cc2SVLkL.s page 144 + + + 929:Middlewares/Third_Party/FatFs/src/ff.c **** } + 1952 .loc 1 929 16 is_stmt 0 view .LVU592 + 1953 0032 2563 str r5, [r4, #48] + 1954 0034 E9E7 b .L164 + 1955 .cfi_endproc + 1956 .LFE1197: + 1958 .section .text.check_fs,"ax",%progbits + 1959 .align 1 + 1960 .syntax unified + 1961 .thumb + 1962 .thumb_func + 1964 check_fs: + 1965 .LVL218: + 1966 .LFB1218: +2969:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 0; fs->winsect = 0xFFFFFFFF; /* Invaidate window */ + 1967 .loc 1 2969 1 is_stmt 1 view -0 + 1968 .cfi_startproc + 1969 @ args = 0, pretend = 0, frame = 0 + 1970 @ frame_needed = 0, uses_anonymous_args = 0 +2969:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 0; fs->winsect = 0xFFFFFFFF; /* Invaidate window */ + 1971 .loc 1 2969 1 is_stmt 0 view .LVU594 + 1972 0000 38B5 push {r3, r4, r5, lr} + 1973 .LCFI17: + 1974 .cfi_def_cfa_offset 16 + 1975 .cfi_offset 3, -16 + 1976 .cfi_offset 4, -12 + 1977 .cfi_offset 5, -8 + 1978 .cfi_offset 14, -4 + 1979 0002 0446 mov r4, r0 +2970:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, sect) != FR_OK) return 4; /* Load boot record */ + 1980 .loc 1 2970 2 is_stmt 1 view .LVU595 +2970:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, sect) != FR_OK) return 4; /* Load boot record */ + 1981 .loc 1 2970 12 is_stmt 0 view .LVU596 + 1982 0004 0023 movs r3, #0 + 1983 0006 C370 strb r3, [r0, #3] +2970:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, sect) != FR_OK) return 4; /* Load boot record */ + 1984 .loc 1 2970 17 is_stmt 1 view .LVU597 +2970:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, sect) != FR_OK) return 4; /* Load boot record */ + 1985 .loc 1 2970 29 is_stmt 0 view .LVU598 + 1986 0008 4FF0FF33 mov r3, #-1 + 1987 000c 0363 str r3, [r0, #48] +2971:Middlewares/Third_Party/FatFs/src/ff.c **** + 1988 .loc 1 2971 2 is_stmt 1 view .LVU599 +2971:Middlewares/Third_Party/FatFs/src/ff.c **** + 1989 .loc 1 2971 6 is_stmt 0 view .LVU600 + 1990 000e FFF7FEFF bl move_window + 1991 .LVL219: +2971:Middlewares/Third_Party/FatFs/src/ff.c **** + 1992 .loc 1 2971 5 discriminator 1 view .LVU601 + 1993 0012 30BB cbnz r0, .L173 + 1994 0014 0546 mov r5, r0 +2973:Middlewares/Third_Party/FatFs/src/ff.c **** + 1995 .loc 1 2973 2 is_stmt 1 view .LVU602 +2973:Middlewares/Third_Party/FatFs/src/ff.c **** + 1996 .loc 1 2973 6 is_stmt 0 view .LVU603 + 1997 0016 04F23220 addw r0, r4, #562 + 1998 001a FFF7FEFF bl ld_word + ARM GAS /tmp/cc2SVLkL.s page 145 + + + 1999 .LVL220: +2973:Middlewares/Third_Party/FatFs/src/ff.c **** + 2000 .loc 1 2973 5 discriminator 1 view .LVU604 + 2001 001e 4AF65523 movw r3, #43605 + 2002 0022 9842 cmp r0, r3 + 2003 0024 1FD1 bne .L174 +2975:Middlewares/Third_Party/FatFs/src/ff.c **** if ((ld_dword(fs->win + BS_FilSysType) & 0xFFFFFF) == 0x544146) return 0; /* Check "FAT" string * + 2004 .loc 1 2975 2 is_stmt 1 view .LVU605 +2975:Middlewares/Third_Party/FatFs/src/ff.c **** if ((ld_dword(fs->win + BS_FilSysType) & 0xFFFFFF) == 0x544146) return 0; /* Check "FAT" string * + 2005 .loc 1 2975 13 is_stmt 0 view .LVU606 + 2006 0026 94F83430 ldrb r3, [r4, #52] @ zero_extendqisi2 +2975:Middlewares/Third_Party/FatFs/src/ff.c **** if ((ld_dword(fs->win + BS_FilSysType) & 0xFFFFFF) == 0x544146) return 0; /* Check "FAT" string * + 2007 .loc 1 2975 5 view .LVU607 + 2008 002a E92B cmp r3, #233 + 2009 002c 07D0 beq .L172 +2975:Middlewares/Third_Party/FatFs/src/ff.c **** if ((ld_dword(fs->win + BS_FilSysType) & 0xFFFFFF) == 0x544146) return 0; /* Check "FAT" string * + 2010 .loc 1 2975 66 discriminator 1 view .LVU608 + 2011 002e 636B ldr r3, [r4, #52] + 2012 0030 03F0FF13 and r3, r3, #16711935 +2975:Middlewares/Third_Party/FatFs/src/ff.c **** if ((ld_dword(fs->win + BS_FilSysType) & 0xFFFFFF) == 0x544146) return 0; /* Check "FAT" string * + 2013 .loc 1 2975 34 discriminator 1 view .LVU609 + 2014 0034 0D4A ldr r2, .L177 + 2015 0036 9342 cmp r3, r2 + 2016 0038 01D0 beq .L172 +2982:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2017 .loc 1 2982 9 view .LVU610 + 2018 003a 0225 movs r5, #2 + 2019 003c 14E0 b .L171 + 2020 .L172: +2976:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_dword(fs->win + BS_FilSysType32) == 0x33544146) return 0; /* Check "FAT3" string */ + 2021 .loc 1 2976 3 is_stmt 1 view .LVU611 +2976:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_dword(fs->win + BS_FilSysType32) == 0x33544146) return 0; /* Check "FAT3" string */ + 2022 .loc 1 2976 8 is_stmt 0 view .LVU612 + 2023 003e 04F16A00 add r0, r4, #106 + 2024 0042 FFF7FEFF bl ld_dword + 2025 .LVL221: +2976:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_dword(fs->win + BS_FilSysType32) == 0x33544146) return 0; /* Check "FAT3" string */ + 2026 .loc 1 2976 42 discriminator 1 view .LVU613 + 2027 0046 20F07F40 bic r0, r0, #-16777216 +2976:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_dword(fs->win + BS_FilSysType32) == 0x33544146) return 0; /* Check "FAT3" string */ + 2028 .loc 1 2976 6 discriminator 1 view .LVU614 + 2029 004a 094B ldr r3, .L177+4 + 2030 004c 9842 cmp r0, r3 + 2031 004e 0BD0 beq .L171 +2977:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2032 .loc 1 2977 3 is_stmt 1 view .LVU615 +2977:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2033 .loc 1 2977 7 is_stmt 0 view .LVU616 + 2034 0050 04F18600 add r0, r4, #134 + 2035 0054 FFF7FEFF bl ld_dword + 2036 .LVL222: +2977:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2037 .loc 1 2977 6 discriminator 1 view .LVU617 + 2038 0058 064B ldr r3, .L177+8 + 2039 005a 9842 cmp r0, r3 + 2040 005c 04D0 beq .L171 +2982:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 146 + + + 2041 .loc 1 2982 9 view .LVU618 + 2042 005e 0225 movs r5, #2 + 2043 0060 02E0 b .L171 + 2044 .L173: +2971:Middlewares/Third_Party/FatFs/src/ff.c **** + 2045 .loc 1 2971 45 discriminator 1 view .LVU619 + 2046 0062 0425 movs r5, #4 + 2047 0064 00E0 b .L171 + 2048 .L174: +2973:Middlewares/Third_Party/FatFs/src/ff.c **** + 2049 .loc 1 2973 51 discriminator 1 view .LVU620 + 2050 0066 0325 movs r5, #3 + 2051 .L171: +2983:Middlewares/Third_Party/FatFs/src/ff.c **** + 2052 .loc 1 2983 1 view .LVU621 + 2053 0068 2846 mov r0, r5 + 2054 006a 38BD pop {r3, r4, r5, pc} + 2055 .LVL223: + 2056 .L178: +2983:Middlewares/Third_Party/FatFs/src/ff.c **** + 2057 .loc 1 2983 1 view .LVU622 + 2058 .align 2 + 2059 .L177: + 2060 006c EB009000 .word 9437419 + 2061 0070 46415400 .word 5521734 + 2062 0074 46415433 .word 861159750 + 2063 .cfi_endproc + 2064 .LFE1218: + 2066 .section .text.find_volume,"ax",%progbits + 2067 .align 1 + 2068 .syntax unified + 2069 .thumb + 2070 .thumb_func + 2072 find_volume: + 2073 .LVL224: + 2074 .LFB1219: +2998:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE fmt, *pt; + 2075 .loc 1 2998 1 is_stmt 1 view -0 + 2076 .cfi_startproc + 2077 @ args = 0, pretend = 0, frame = 24 + 2078 @ frame_needed = 0, uses_anonymous_args = 0 +2998:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE fmt, *pt; + 2079 .loc 1 2998 1 is_stmt 0 view .LVU624 + 2080 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 2081 .LCFI18: + 2082 .cfi_def_cfa_offset 36 + 2083 .cfi_offset 4, -36 + 2084 .cfi_offset 5, -32 + 2085 .cfi_offset 6, -28 + 2086 .cfi_offset 7, -24 + 2087 .cfi_offset 8, -20 + 2088 .cfi_offset 9, -16 + 2089 .cfi_offset 10, -12 + 2090 .cfi_offset 11, -8 + 2091 .cfi_offset 14, -4 + 2092 0004 87B0 sub sp, sp, #28 + 2093 .LCFI19: + ARM GAS /tmp/cc2SVLkL.s page 147 + + + 2094 .cfi_def_cfa_offset 64 + 2095 0006 0D46 mov r5, r1 + 2096 0008 1646 mov r6, r2 +2999:Middlewares/Third_Party/FatFs/src/ff.c **** int vol; + 2097 .loc 1 2999 2 is_stmt 1 view .LVU625 +3000:Middlewares/Third_Party/FatFs/src/ff.c **** DSTATUS stat; + 2098 .loc 1 3000 2 view .LVU626 +3001:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD bsect, fasize, tsect, sysect, nclst, szbfat, br[4]; + 2099 .loc 1 3001 2 view .LVU627 +3002:Middlewares/Third_Party/FatFs/src/ff.c **** WORD nrsv; + 2100 .loc 1 3002 2 view .LVU628 +3003:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; + 2101 .loc 1 3003 2 view .LVU629 +3004:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i; + 2102 .loc 1 3004 2 view .LVU630 +3005:Middlewares/Third_Party/FatFs/src/ff.c **** + 2103 .loc 1 3005 2 view .LVU631 +3009:Middlewares/Third_Party/FatFs/src/ff.c **** vol = get_ldnumber(path); + 2104 .loc 1 3009 2 view .LVU632 +3009:Middlewares/Third_Party/FatFs/src/ff.c **** vol = get_ldnumber(path); + 2105 .loc 1 3009 7 is_stmt 0 view .LVU633 + 2106 000a 0023 movs r3, #0 + 2107 000c 0B60 str r3, [r1] +3010:Middlewares/Third_Party/FatFs/src/ff.c **** if (vol < 0) return FR_INVALID_DRIVE; + 2108 .loc 1 3010 2 is_stmt 1 view .LVU634 +3010:Middlewares/Third_Party/FatFs/src/ff.c **** if (vol < 0) return FR_INVALID_DRIVE; + 2109 .loc 1 3010 8 is_stmt 0 view .LVU635 + 2110 000e FFF7FEFF bl get_ldnumber + 2111 .LVL225: +3011:Middlewares/Third_Party/FatFs/src/ff.c **** + 2112 .loc 1 3011 2 is_stmt 1 view .LVU636 +3011:Middlewares/Third_Party/FatFs/src/ff.c **** + 2113 .loc 1 3011 5 is_stmt 0 view .LVU637 + 2114 0012 071E subs r7, r0, #0 + 2115 0014 C0F26781 blt .L196 +3014:Middlewares/Third_Party/FatFs/src/ff.c **** if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */ + 2116 .loc 1 3014 2 is_stmt 1 view .LVU638 +3014:Middlewares/Third_Party/FatFs/src/ff.c **** if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */ + 2117 .loc 1 3014 5 is_stmt 0 view .LVU639 + 2118 0018 BE4B ldr r3, .L230 + 2119 001a 53F82740 ldr r4, [r3, r7, lsl #2] + 2120 .LVL226: +3015:Middlewares/Third_Party/FatFs/src/ff.c **** + 2121 .loc 1 3015 2 is_stmt 1 view .LVU640 +3015:Middlewares/Third_Party/FatFs/src/ff.c **** + 2122 .loc 1 3015 5 is_stmt 0 view .LVU641 + 2123 001e 002C cmp r4, #0 + 2124 0020 00F06681 beq .L197 +3017:Middlewares/Third_Party/FatFs/src/ff.c **** *rfs = fs; /* Return pointer to the file system object */ + 2125 .loc 1 3017 14 is_stmt 1 view .LVU642 +3018:Middlewares/Third_Party/FatFs/src/ff.c **** + 2126 .loc 1 3018 2 view .LVU643 +3018:Middlewares/Third_Party/FatFs/src/ff.c **** + 2127 .loc 1 3018 7 is_stmt 0 view .LVU644 + 2128 0024 2C60 str r4, [r5] +3020:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type) { /* If the volume has been mounted */ + 2129 .loc 1 3020 2 is_stmt 1 view .LVU645 + ARM GAS /tmp/cc2SVLkL.s page 148 + + +3020:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type) { /* If the volume has been mounted */ + 2130 .loc 1 3020 7 is_stmt 0 view .LVU646 + 2131 0026 06F0FE06 and r6, r6, #254 + 2132 .LVL227: +3021:Middlewares/Third_Party/FatFs/src/ff.c **** stat = disk_status(fs->drv); + 2133 .loc 1 3021 2 is_stmt 1 view .LVU647 +3021:Middlewares/Third_Party/FatFs/src/ff.c **** stat = disk_status(fs->drv); + 2134 .loc 1 3021 8 is_stmt 0 view .LVU648 + 2135 002a 2378 ldrb r3, [r4] @ zero_extendqisi2 +3021:Middlewares/Third_Party/FatFs/src/ff.c **** stat = disk_status(fs->drv); + 2136 .loc 1 3021 5 view .LVU649 + 2137 002c 73B1 cbz r3, .L181 +3022:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized */ + 2138 .loc 1 3022 3 is_stmt 1 view .LVU650 +3022:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized */ + 2139 .loc 1 3022 10 is_stmt 0 view .LVU651 + 2140 002e 6078 ldrb r0, [r4, #1] @ zero_extendqisi2 + 2141 .LVL228: +3022:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized */ + 2142 .loc 1 3022 10 view .LVU652 + 2143 0030 FFF7FEFF bl disk_status + 2144 .LVL229: +3023:Middlewares/Third_Party/FatFs/src/ff.c **** if (!_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check write protection if needed */ + 2145 .loc 1 3023 3 is_stmt 1 view .LVU653 +3023:Middlewares/Third_Party/FatFs/src/ff.c **** if (!_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check write protection if needed */ + 2146 .loc 1 3023 6 is_stmt 0 view .LVU654 + 2147 0034 10F00105 ands r5, r0, #1 + 2148 .LVL230: +3023:Middlewares/Third_Party/FatFs/src/ff.c **** if (!_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check write protection if needed */ + 2149 .loc 1 3023 6 view .LVU655 + 2150 0038 08D1 bne .L181 +3024:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_WRITE_PROTECTED; + 2151 .loc 1 3024 4 is_stmt 1 view .LVU656 +3024:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_WRITE_PROTECTED; + 2152 .loc 1 3024 7 is_stmt 0 view .LVU657 + 2153 003a 002E cmp r6, #0 + 2154 003c 00F05481 beq .L180 +3024:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_WRITE_PROTECTED; + 2155 .loc 1 3024 30 discriminator 1 view .LVU658 + 2156 0040 10F0040F tst r0, #4 + 2157 0044 00F05081 beq .L180 +3025:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2158 .loc 1 3025 12 view .LVU659 + 2159 0048 0A25 movs r5, #10 + 2160 004a 4DE1 b .L180 + 2161 .LVL231: + 2162 .L181: +3034:Middlewares/Third_Party/FatFs/src/ff.c **** fs->drv = LD2PD(vol); /* Bind the logical drive and a physical drive */ + 2163 .loc 1 3034 2 is_stmt 1 view .LVU660 +3034:Middlewares/Third_Party/FatFs/src/ff.c **** fs->drv = LD2PD(vol); /* Bind the logical drive and a physical drive */ + 2164 .loc 1 3034 14 is_stmt 0 view .LVU661 + 2165 004c 0023 movs r3, #0 + 2166 004e 2370 strb r3, [r4] +3035:Middlewares/Third_Party/FatFs/src/ff.c **** stat = disk_initialize(fs->drv); /* Initialize the physical drive */ + 2167 .loc 1 3035 2 is_stmt 1 view .LVU662 +3035:Middlewares/Third_Party/FatFs/src/ff.c **** stat = disk_initialize(fs->drv); /* Initialize the physical drive */ + 2168 .loc 1 3035 12 is_stmt 0 view .LVU663 + ARM GAS /tmp/cc2SVLkL.s page 149 + + + 2169 0050 F8B2 uxtb r0, r7 +3035:Middlewares/Third_Party/FatFs/src/ff.c **** stat = disk_initialize(fs->drv); /* Initialize the physical drive */ + 2170 .loc 1 3035 10 view .LVU664 + 2171 0052 6070 strb r0, [r4, #1] +3036:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat & STA_NOINIT) { /* Check if the initialization succeeded */ + 2172 .loc 1 3036 2 is_stmt 1 view .LVU665 +3036:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat & STA_NOINIT) { /* Check if the initialization succeeded */ + 2173 .loc 1 3036 9 is_stmt 0 view .LVU666 + 2174 0054 FFF7FEFF bl disk_initialize + 2175 .LVL232: +3037:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */ + 2176 .loc 1 3037 2 is_stmt 1 view .LVU667 +3037:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */ + 2177 .loc 1 3037 5 is_stmt 0 view .LVU668 + 2178 0058 10F0010F tst r0, #1 + 2179 005c 40F04A81 bne .L199 +3040:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_WRITE_PROTECTED; + 2180 .loc 1 3040 2 is_stmt 1 view .LVU669 +3040:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_WRITE_PROTECTED; + 2181 .loc 1 3040 5 is_stmt 0 view .LVU670 + 2182 0060 1EB1 cbz r6, .L182 +3040:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_WRITE_PROTECTED; + 2183 .loc 1 3040 28 discriminator 1 view .LVU671 + 2184 0062 10F0040F tst r0, #4 + 2185 0066 40F04781 bne .L200 + 2186 .L182: +3044:Middlewares/Third_Party/FatFs/src/ff.c **** if (SS(fs) > _MAX_SS || SS(fs) < _MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR; + 2187 .loc 1 3044 2 is_stmt 1 view .LVU672 +3044:Middlewares/Third_Party/FatFs/src/ff.c **** if (SS(fs) > _MAX_SS || SS(fs) < _MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR; + 2188 .loc 1 3044 6 is_stmt 0 view .LVU673 + 2189 006a 04F10C02 add r2, r4, #12 + 2190 006e 0221 movs r1, #2 + 2191 0070 6078 ldrb r0, [r4, #1] @ zero_extendqisi2 + 2192 .LVL233: +3044:Middlewares/Third_Party/FatFs/src/ff.c **** if (SS(fs) > _MAX_SS || SS(fs) < _MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR; + 2193 .loc 1 3044 6 view .LVU674 + 2194 0072 FFF7FEFF bl disk_ioctl + 2195 .LVL234: +3044:Middlewares/Third_Party/FatFs/src/ff.c **** if (SS(fs) > _MAX_SS || SS(fs) < _MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR; + 2196 .loc 1 3044 5 discriminator 1 view .LVU675 + 2197 0076 0546 mov r5, r0 + 2198 0078 0028 cmp r0, #0 + 2199 007a 40F03F81 bne .L201 +3045:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 2200 .loc 1 3045 2 is_stmt 1 view .LVU676 +3045:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 2201 .loc 1 3045 6 is_stmt 0 view .LVU677 + 2202 007e A289 ldrh r2, [r4, #12] +3045:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 2203 .loc 1 3045 23 view .LVU678 + 2204 0080 A2F50073 sub r3, r2, #512 + 2205 0084 9BB2 uxth r3, r3 +3045:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 2206 .loc 1 3045 5 view .LVU679 + 2207 0086 B3F5606F cmp r3, #3584 + 2208 008a 00F23981 bhi .L202 +3045:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + ARM GAS /tmp/cc2SVLkL.s page 150 + + + 2209 .loc 1 3045 64 discriminator 2 view .LVU680 + 2210 008e 531E subs r3, r2, #1 +3045:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 2211 .loc 1 3045 43 discriminator 2 view .LVU681 + 2212 0090 1A42 tst r2, r3 + 2213 0092 01D0 beq .L224 +3045:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 2214 .loc 1 3045 78 discriminator 3 view .LVU682 + 2215 0094 0125 movs r5, #1 + 2216 0096 27E1 b .L180 + 2217 .L224: +3049:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = check_fs(fs, bsect); /* Load sector 0 and check if it is an FAT-VBR as SFD */ + 2218 .loc 1 3049 2 is_stmt 1 view .LVU683 + 2219 .LVL235: +3050:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == 2 || (fmt < 2 && LD2PT(vol) != 0)) { /* Not an FAT-VBR or forced partition number */ + 2220 .loc 1 3050 2 view .LVU684 +3050:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == 2 || (fmt < 2 && LD2PT(vol) != 0)) { /* Not an FAT-VBR or forced partition number */ + 2221 .loc 1 3050 8 is_stmt 0 view .LVU685 + 2222 0098 0021 movs r1, #0 + 2223 009a 2046 mov r0, r4 + 2224 009c FFF7FEFF bl check_fs + 2225 .LVL236: +3051:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < 4; i++) { /* Get partition offset */ + 2226 .loc 1 3051 2 is_stmt 1 view .LVU686 +3051:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < 4; i++) { /* Get partition offset */ + 2227 .loc 1 3051 5 is_stmt 0 view .LVU687 + 2228 00a0 0228 cmp r0, #2 + 2229 00a2 00F08880 beq .L204 +3049:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = check_fs(fs, bsect); /* Load sector 0 and check if it is an FAT-VBR as SFD */ + 2230 .loc 1 3049 8 view .LVU688 + 2231 00a6 0026 movs r6, #0 + 2232 .LVL237: + 2233 .L184: +3063:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt >= 2) return FR_NO_FILESYSTEM; /* No FAT volume is found */ + 2234 .loc 1 3063 2 is_stmt 1 view .LVU689 +3063:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt >= 2) return FR_NO_FILESYSTEM; /* No FAT volume is found */ + 2235 .loc 1 3063 5 is_stmt 0 view .LVU690 + 2236 00a8 0428 cmp r0, #4 + 2237 00aa 00F02B81 beq .L207 +3064:Middlewares/Third_Party/FatFs/src/ff.c **** + 2238 .loc 1 3064 2 is_stmt 1 view .LVU691 +3064:Middlewares/Third_Party/FatFs/src/ff.c **** + 2239 .loc 1 3064 5 is_stmt 0 view .LVU692 + 2240 00ae 0128 cmp r0, #1 + 2241 00b0 00F22A81 bhi .L208 +3116:Middlewares/Third_Party/FatFs/src/ff.c **** + 2242 .loc 1 3116 3 is_stmt 1 view .LVU693 +3116:Middlewares/Third_Party/FatFs/src/ff.c **** + 2243 .loc 1 3116 7 is_stmt 0 view .LVU694 + 2244 00b4 04F13F00 add r0, r4, #63 + 2245 .LVL238: +3116:Middlewares/Third_Party/FatFs/src/ff.c **** + 2246 .loc 1 3116 7 view .LVU695 + 2247 00b8 FFF7FEFF bl ld_word + 2248 .LVL239: +3116:Middlewares/Third_Party/FatFs/src/ff.c **** + 2249 .loc 1 3116 44 discriminator 1 view .LVU696 + ARM GAS /tmp/cc2SVLkL.s page 151 + + + 2250 00bc B4F80C80 ldrh r8, [r4, #12] +3116:Middlewares/Third_Party/FatFs/src/ff.c **** + 2251 .loc 1 3116 6 discriminator 1 view .LVU697 + 2252 00c0 4045 cmp r0, r8 + 2253 00c2 40F02381 bne .L209 +3118:Middlewares/Third_Party/FatFs/src/ff.c **** if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32); + 2254 .loc 1 3118 3 is_stmt 1 view .LVU698 +3118:Middlewares/Third_Party/FatFs/src/ff.c **** if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32); + 2255 .loc 1 3118 12 is_stmt 0 view .LVU699 + 2256 00c6 04F14A00 add r0, r4, #74 + 2257 00ca FFF7FEFF bl ld_word + 2258 .LVL240: +3118:Middlewares/Third_Party/FatFs/src/ff.c **** if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32); + 2259 .loc 1 3118 10 discriminator 1 view .LVU700 + 2260 00ce 0746 mov r7, r0 + 2261 .LVL241: +3119:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsize = fasize; + 2262 .loc 1 3119 3 is_stmt 1 view .LVU701 +3119:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsize = fasize; + 2263 .loc 1 3119 6 is_stmt 0 view .LVU702 + 2264 00d0 20B9 cbnz r0, .L189 +3119:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsize = fasize; + 2265 .loc 1 3119 20 is_stmt 1 discriminator 1 view .LVU703 +3119:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsize = fasize; + 2266 .loc 1 3119 29 is_stmt 0 discriminator 1 view .LVU704 + 2267 00d2 04F15800 add r0, r4, #88 + 2268 .LVL242: +3119:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsize = fasize; + 2269 .loc 1 3119 29 discriminator 1 view .LVU705 + 2270 00d6 FFF7FEFF bl ld_dword + 2271 .LVL243: + 2272 00da 0746 mov r7, r0 + 2273 .LVL244: + 2274 .L189: +3120:Middlewares/Third_Party/FatFs/src/ff.c **** + 2275 .loc 1 3120 3 is_stmt 1 view .LVU706 +3120:Middlewares/Third_Party/FatFs/src/ff.c **** + 2276 .loc 1 3120 13 is_stmt 0 view .LVU707 + 2277 00dc E761 str r7, [r4, #28] +3122:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */ + 2278 .loc 1 3122 3 is_stmt 1 view .LVU708 +3122:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */ + 2279 .loc 1 3122 23 is_stmt 0 view .LVU709 + 2280 00de 94F84420 ldrb r2, [r4, #68] @ zero_extendqisi2 +3122:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */ + 2281 .loc 1 3122 14 view .LVU710 + 2282 00e2 A270 strb r2, [r4, #2] +3123:Middlewares/Third_Party/FatFs/src/ff.c **** fasize *= fs->n_fats; /* Number of sectors for FAT area */ + 2283 .loc 1 3123 3 is_stmt 1 view .LVU711 +3123:Middlewares/Third_Party/FatFs/src/ff.c **** fasize *= fs->n_fats; /* Number of sectors for FAT area */ + 2284 .loc 1 3123 23 is_stmt 0 view .LVU712 + 2285 00e4 531E subs r3, r2, #1 + 2286 00e6 DBB2 uxtb r3, r3 +3123:Middlewares/Third_Party/FatFs/src/ff.c **** fasize *= fs->n_fats; /* Number of sectors for FAT area */ + 2287 .loc 1 3123 6 view .LVU713 + 2288 00e8 012B cmp r3, #1 + 2289 00ea 00F21181 bhi .L210 + ARM GAS /tmp/cc2SVLkL.s page 152 + + +3124:Middlewares/Third_Party/FatFs/src/ff.c **** + 2290 .loc 1 3124 3 is_stmt 1 view .LVU714 +3124:Middlewares/Third_Party/FatFs/src/ff.c **** + 2291 .loc 1 3124 10 is_stmt 0 view .LVU715 + 2292 00ee 07FB02F3 mul r3, r7, r2 + 2293 00f2 0093 str r3, [sp] + 2294 .LVL245: +3126:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM; /* (Must be power o + 2295 .loc 1 3126 3 is_stmt 1 view .LVU716 +3126:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM; /* (Must be power o + 2296 .loc 1 3126 22 is_stmt 0 view .LVU717 + 2297 00f4 94F84190 ldrb r9, [r4, #65] @ zero_extendqisi2 +3126:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM; /* (Must be power o + 2298 .loc 1 3126 13 view .LVU718 + 2299 00f8 A4F80A90 strh r9, [r4, #10] @ movhi +3127:Middlewares/Third_Party/FatFs/src/ff.c **** + 2300 .loc 1 3127 3 is_stmt 1 view .LVU719 +3127:Middlewares/Third_Party/FatFs/src/ff.c **** + 2301 .loc 1 3127 6 is_stmt 0 view .LVU720 + 2302 00fc B9F1000F cmp r9, #0 + 2303 0100 00F01081 beq .L211 +3127:Middlewares/Third_Party/FatFs/src/ff.c **** + 2304 .loc 1 3127 49 discriminator 2 view .LVU721 + 2305 0104 09F1FF33 add r3, r9, #-1 + 2306 .LVL246: +3127:Middlewares/Third_Party/FatFs/src/ff.c **** + 2307 .loc 1 3127 22 discriminator 2 view .LVU722 + 2308 0108 19EA030F tst r9, r3 + 2309 010c 40F00C81 bne .L212 +3129:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM; /* (Must be sector aligned) */ + 2310 .loc 1 3129 3 is_stmt 1 view .LVU723 +3129:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM; /* (Must be sector aligned) */ + 2311 .loc 1 3129 19 is_stmt 0 view .LVU724 + 2312 0110 04F14500 add r0, r4, #69 + 2313 0114 FFF7FEFF bl ld_word + 2314 .LVL247: + 2315 0118 8246 mov r10, r0 +3129:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM; /* (Must be sector aligned) */ + 2316 .loc 1 3129 17 discriminator 1 view .LVU725 + 2317 011a 2081 strh r0, [r4, #8] @ movhi +3130:Middlewares/Third_Party/FatFs/src/ff.c **** + 2318 .loc 1 3130 3 is_stmt 1 view .LVU726 +3130:Middlewares/Third_Party/FatFs/src/ff.c **** + 2319 .loc 1 3130 7 is_stmt 0 view .LVU727 + 2320 011c 4FEA581B lsr fp, r8, #5 + 2321 0120 B0FBFBF3 udiv r3, r0, fp + 2322 0124 0BFB1303 mls r3, fp, r3, r0 + 2323 0128 9BB2 uxth r3, r3 +3130:Middlewares/Third_Party/FatFs/src/ff.c **** + 2324 .loc 1 3130 6 view .LVU728 + 2325 012a 002B cmp r3, #0 + 2326 012c 40F0FE80 bne .L213 +3132:Middlewares/Third_Party/FatFs/src/ff.c **** if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32); + 2327 .loc 1 3132 3 is_stmt 1 view .LVU729 +3132:Middlewares/Third_Party/FatFs/src/ff.c **** if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32); + 2328 .loc 1 3132 11 is_stmt 0 view .LVU730 + 2329 0130 04F14700 add r0, r4, #71 + ARM GAS /tmp/cc2SVLkL.s page 153 + + + 2330 0134 FFF7FEFF bl ld_word + 2331 .LVL248: +3132:Middlewares/Third_Party/FatFs/src/ff.c **** if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32); + 2332 .loc 1 3132 9 discriminator 1 view .LVU731 + 2333 0138 0190 str r0, [sp, #4] + 2334 .LVL249: +3133:Middlewares/Third_Party/FatFs/src/ff.c **** + 2335 .loc 1 3133 3 is_stmt 1 view .LVU732 +3133:Middlewares/Third_Party/FatFs/src/ff.c **** + 2336 .loc 1 3133 6 is_stmt 0 view .LVU733 + 2337 013a 20B9 cbnz r0, .L190 +3133:Middlewares/Third_Party/FatFs/src/ff.c **** + 2338 .loc 1 3133 19 is_stmt 1 discriminator 1 view .LVU734 +3133:Middlewares/Third_Party/FatFs/src/ff.c **** + 2339 .loc 1 3133 27 is_stmt 0 discriminator 1 view .LVU735 + 2340 013c 04F15400 add r0, r4, #84 + 2341 .LVL250: +3133:Middlewares/Third_Party/FatFs/src/ff.c **** + 2342 .loc 1 3133 27 discriminator 1 view .LVU736 + 2343 0140 FFF7FEFF bl ld_dword + 2344 .LVL251: + 2345 0144 0190 str r0, [sp, #4] + 2346 .LVL252: + 2347 .L190: +3135:Middlewares/Third_Party/FatFs/src/ff.c **** if (nrsv == 0) return FR_NO_FILESYSTEM; /* (Must not be 0) */ + 2348 .loc 1 3135 3 is_stmt 1 view .LVU737 +3135:Middlewares/Third_Party/FatFs/src/ff.c **** if (nrsv == 0) return FR_NO_FILESYSTEM; /* (Must not be 0) */ + 2349 .loc 1 3135 10 is_stmt 0 view .LVU738 + 2350 0146 04F14200 add r0, r4, #66 + 2351 014a FFF7FEFF bl ld_word + 2352 .LVL253: +3136:Middlewares/Third_Party/FatFs/src/ff.c **** + 2353 .loc 1 3136 3 is_stmt 1 view .LVU739 +3136:Middlewares/Third_Party/FatFs/src/ff.c **** + 2354 .loc 1 3136 6 is_stmt 0 view .LVU740 + 2355 014e 0146 mov r1, r0 + 2356 0150 0028 cmp r0, #0 + 2357 0152 00F0ED80 beq .L214 +3139:Middlewares/Third_Party/FatFs/src/ff.c **** if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + 2358 .loc 1 3139 3 is_stmt 1 view .LVU741 +3139:Middlewares/Third_Party/FatFs/src/ff.c **** if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + 2359 .loc 1 3139 17 is_stmt 0 view .LVU742 + 2360 0156 009B ldr r3, [sp] + 2361 0158 C318 adds r3, r0, r3 +3139:Middlewares/Third_Party/FatFs/src/ff.c **** if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + 2362 .loc 1 3139 42 view .LVU743 + 2363 015a BAFBFBFB udiv fp, r10, fp +3139:Middlewares/Third_Party/FatFs/src/ff.c **** if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + 2364 .loc 1 3139 10 view .LVU744 + 2365 015e 5B44 add r3, r3, fp + 2366 .LVL254: +3140:Middlewares/Third_Party/FatFs/src/ff.c **** nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ + 2367 .loc 1 3140 3 is_stmt 1 view .LVU745 +3140:Middlewares/Third_Party/FatFs/src/ff.c **** nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ + 2368 .loc 1 3140 6 is_stmt 0 view .LVU746 + 2369 0160 019A ldr r2, [sp, #4] + 2370 0162 9A42 cmp r2, r3 + ARM GAS /tmp/cc2SVLkL.s page 154 + + + 2371 0164 C0F0E680 bcc .L215 +3141:Middlewares/Third_Party/FatFs/src/ff.c **** if (nclst == 0) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + 2372 .loc 1 3141 3 is_stmt 1 view .LVU747 +3141:Middlewares/Third_Party/FatFs/src/ff.c **** if (nclst == 0) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + 2373 .loc 1 3141 18 is_stmt 0 view .LVU748 + 2374 0168 D21A subs r2, r2, r3 +3141:Middlewares/Third_Party/FatFs/src/ff.c **** if (nclst == 0) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + 2375 .loc 1 3141 9 view .LVU749 + 2376 016a B2FBF9F0 udiv r0, r2, r9 + 2377 .LVL255: +3142:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = FS_FAT32; + 2378 .loc 1 3142 3 is_stmt 1 view .LVU750 +3142:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = FS_FAT32; + 2379 .loc 1 3142 6 is_stmt 0 view .LVU751 + 2380 016e 4A45 cmp r2, r9 + 2381 0170 C0F0E280 bcc .L216 +3143:Middlewares/Third_Party/FatFs/src/ff.c **** if (nclst <= MAX_FAT16) fmt = FS_FAT16; + 2382 .loc 1 3143 3 is_stmt 1 view .LVU752 + 2383 .LVL256: +3144:Middlewares/Third_Party/FatFs/src/ff.c **** if (nclst <= MAX_FAT12) fmt = FS_FAT12; + 2384 .loc 1 3144 3 view .LVU753 +3144:Middlewares/Third_Party/FatFs/src/ff.c **** if (nclst <= MAX_FAT12) fmt = FS_FAT12; + 2385 .loc 1 3144 6 is_stmt 0 view .LVU754 + 2386 0174 4FF6F572 movw r2, #65525 + 2387 0178 9042 cmp r0, r2 + 2388 017a 34D8 bhi .L217 +3144:Middlewares/Third_Party/FatFs/src/ff.c **** if (nclst <= MAX_FAT12) fmt = FS_FAT12; + 2389 .loc 1 3144 27 is_stmt 1 discriminator 1 view .LVU755 + 2390 .LVL257: +3145:Middlewares/Third_Party/FatFs/src/ff.c **** + 2391 .loc 1 3145 3 view .LVU756 +3145:Middlewares/Third_Party/FatFs/src/ff.c **** + 2392 .loc 1 3145 6 is_stmt 0 view .LVU757 + 2393 017c 40F6F572 movw r2, #4085 + 2394 0180 9042 cmp r0, r2 + 2395 0182 6AD9 bls .L218 + 2396 0184 4FF0020B mov fp, #2 + 2397 0188 2FE0 b .L191 + 2398 .LVL258: + 2399 .L205: +3054:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2400 .loc 1 3054 54 discriminator 2 view .LVU758 + 2401 018a 0020 movs r0, #0 + 2402 .LVL259: + 2403 .L185: +3054:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2404 .loc 1 3054 10 discriminator 4 view .LVU759 + 2405 018c 06AB add r3, sp, #24 + 2406 018e 03EB8603 add r3, r3, r6, lsl #2 + 2407 0192 43F8100C str r0, [r3, #-16] +3052:Middlewares/Third_Party/FatFs/src/ff.c **** pt = fs->win + (MBR_Table + i * SZ_PTE); + 2408 .loc 1 3052 23 is_stmt 1 discriminator 2 view .LVU760 + 2409 0196 0136 adds r6, r6, #1 + 2410 .LVL260: + 2411 .L183: +3052:Middlewares/Third_Party/FatFs/src/ff.c **** pt = fs->win + (MBR_Table + i * SZ_PTE); + 2412 .loc 1 3052 17 discriminator 1 view .LVU761 + ARM GAS /tmp/cc2SVLkL.s page 155 + + + 2413 0198 032E cmp r6, #3 + 2414 019a 0ED8 bhi .L225 +3053:Middlewares/Third_Party/FatFs/src/ff.c **** br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0; + 2415 .loc 1 3053 4 view .LVU762 +3053:Middlewares/Third_Party/FatFs/src/ff.c **** br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0; + 2416 .loc 1 3053 9 is_stmt 0 view .LVU763 + 2417 019c 04F13400 add r0, r4, #52 +3053:Middlewares/Third_Party/FatFs/src/ff.c **** br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0; + 2418 .loc 1 3053 34 view .LVU764 + 2419 01a0 3301 lsls r3, r6, #4 +3053:Middlewares/Third_Party/FatFs/src/ff.c **** br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0; + 2420 .loc 1 3053 30 view .LVU765 + 2421 01a2 03F5DF73 add r3, r3, #446 +3053:Middlewares/Third_Party/FatFs/src/ff.c **** br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0; + 2422 .loc 1 3053 7 view .LVU766 + 2423 01a6 1844 add r0, r0, r3 + 2424 .LVL261: +3054:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2425 .loc 1 3054 4 is_stmt 1 view .LVU767 +3054:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2426 .loc 1 3054 14 is_stmt 0 view .LVU768 + 2427 01a8 0379 ldrb r3, [r0, #4] @ zero_extendqisi2 +3054:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2428 .loc 1 3054 54 view .LVU769 + 2429 01aa 002B cmp r3, #0 + 2430 01ac EDD0 beq .L205 +3054:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2431 .loc 1 3054 29 discriminator 1 view .LVU770 + 2432 01ae 0830 adds r0, r0, #8 + 2433 .LVL262: +3054:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2434 .loc 1 3054 29 discriminator 1 view .LVU771 + 2435 01b0 FFF7FEFF bl ld_dword + 2436 .LVL263: +3054:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2437 .loc 1 3054 29 discriminator 1 view .LVU772 + 2438 01b4 EAE7 b .L185 + 2439 .LVL264: + 2440 .L204: +3052:Middlewares/Third_Party/FatFs/src/ff.c **** pt = fs->win + (MBR_Table + i * SZ_PTE); + 2441 .loc 1 3052 10 view .LVU773 + 2442 01b6 0026 movs r6, #0 + 2443 .LVL265: +3052:Middlewares/Third_Party/FatFs/src/ff.c **** pt = fs->win + (MBR_Table + i * SZ_PTE); + 2444 .loc 1 3052 10 view .LVU774 + 2445 01b8 EEE7 b .L183 + 2446 .LVL266: + 2447 .L225: +3052:Middlewares/Third_Party/FatFs/src/ff.c **** pt = fs->win + (MBR_Table + i * SZ_PTE); + 2448 .loc 1 3052 10 view .LVU775 + 2449 01ba 0027 movs r7, #0 + 2450 .LVL267: +3052:Middlewares/Third_Party/FatFs/src/ff.c **** pt = fs->win + (MBR_Table + i * SZ_PTE); + 2451 .loc 1 3052 10 view .LVU776 + 2452 01bc 0AE0 b .L188 + 2453 .LVL268: + 2454 .L226: + ARM GAS /tmp/cc2SVLkL.s page 156 + + +3060:Middlewares/Third_Party/FatFs/src/ff.c **** } while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4); + 2455 .loc 1 3060 18 discriminator 1 view .LVU777 + 2456 01be 3146 mov r1, r6 + 2457 01c0 2046 mov r0, r4 + 2458 01c2 FFF7FEFF bl check_fs + 2459 .LVL269: +3061:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2460 .loc 1 3061 40 is_stmt 1 view .LVU778 + 2461 01c6 0128 cmp r0, #1 + 2462 01c8 7FF66EAF bls .L184 + 2463 .LVL270: + 2464 .L187: +3061:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2465 .loc 1 3061 40 is_stmt 0 discriminator 1 view .LVU779 + 2466 01cc 0137 adds r7, r7, #1 + 2467 .LVL271: +3061:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2468 .loc 1 3061 40 discriminator 1 view .LVU780 + 2469 01ce 032F cmp r7, #3 + 2470 01d0 3FF66AAF bhi .L184 + 2471 .LVL272: + 2472 .L188: +3058:Middlewares/Third_Party/FatFs/src/ff.c **** bsect = br[i]; + 2473 .loc 1 3058 3 is_stmt 1 view .LVU781 +3059:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = bsect ? check_fs(fs, bsect) : 3; /* Check the partition */ + 2474 .loc 1 3059 4 view .LVU782 +3059:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = bsect ? check_fs(fs, bsect) : 3; /* Check the partition */ + 2475 .loc 1 3059 10 is_stmt 0 view .LVU783 + 2476 01d4 06AB add r3, sp, #24 + 2477 01d6 03EB8703 add r3, r3, r7, lsl #2 + 2478 01da 53F8106C ldr r6, [r3, #-16] + 2479 .LVL273: +3060:Middlewares/Third_Party/FatFs/src/ff.c **** } while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4); + 2480 .loc 1 3060 4 is_stmt 1 view .LVU784 +3060:Middlewares/Third_Party/FatFs/src/ff.c **** } while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4); + 2481 .loc 1 3060 8 is_stmt 0 view .LVU785 + 2482 01de 002E cmp r6, #0 + 2483 01e0 EDD1 bne .L226 +3060:Middlewares/Third_Party/FatFs/src/ff.c **** } while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4); + 2484 .loc 1 3060 8 discriminator 2 view .LVU786 + 2485 01e2 0320 movs r0, #3 + 2486 01e4 F2E7 b .L187 + 2487 .LVL274: + 2488 .L217: +3143:Middlewares/Third_Party/FatFs/src/ff.c **** if (nclst <= MAX_FAT16) fmt = FS_FAT16; + 2489 .loc 1 3143 7 view .LVU787 + 2490 01e6 4FF0030B mov fp, #3 + 2491 .LVL275: + 2492 .L191: +3148:Middlewares/Third_Party/FatFs/src/ff.c **** fs->volbase = bsect; /* Volume start sector */ + 2493 .loc 1 3148 3 is_stmt 1 view .LVU788 +3148:Middlewares/Third_Party/FatFs/src/ff.c **** fs->volbase = bsect; /* Volume start sector */ + 2494 .loc 1 3148 24 is_stmt 0 view .LVU789 + 2495 01ea 00F10209 add r9, r0, #2 +3148:Middlewares/Third_Party/FatFs/src/ff.c **** fs->volbase = bsect; /* Volume start sector */ + 2496 .loc 1 3148 16 view .LVU790 + 2497 01ee C4F81890 str r9, [r4, #24] + ARM GAS /tmp/cc2SVLkL.s page 157 + + +3149:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fatbase = bsect + nrsv; /* FAT start sector */ + 2498 .loc 1 3149 3 is_stmt 1 view .LVU791 +3149:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fatbase = bsect + nrsv; /* FAT start sector */ + 2499 .loc 1 3149 15 is_stmt 0 view .LVU792 + 2500 01f2 2662 str r6, [r4, #32] +3150:Middlewares/Third_Party/FatFs/src/ff.c **** fs->database = bsect + sysect; /* Data start sector */ + 2501 .loc 1 3150 3 is_stmt 1 view .LVU793 +3150:Middlewares/Third_Party/FatFs/src/ff.c **** fs->database = bsect + sysect; /* Data start sector */ + 2502 .loc 1 3150 23 is_stmt 0 view .LVU794 + 2503 01f4 8A19 adds r2, r1, r6 +3150:Middlewares/Third_Party/FatFs/src/ff.c **** fs->database = bsect + sysect; /* Data start sector */ + 2504 .loc 1 3150 15 view .LVU795 + 2505 01f6 6262 str r2, [r4, #36] +3151:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { + 2506 .loc 1 3151 3 is_stmt 1 view .LVU796 +3151:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { + 2507 .loc 1 3151 24 is_stmt 0 view .LVU797 + 2508 01f8 3344 add r3, r3, r6 + 2509 .LVL276: +3151:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { + 2510 .loc 1 3151 16 view .LVU798 + 2511 01fa E362 str r3, [r4, #44] +3152:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM; /* (Must be FAT32 revision 0.0 + 2512 .loc 1 3152 3 is_stmt 1 view .LVU799 +3152:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM; /* (Must be FAT32 revision 0.0 + 2513 .loc 1 3152 6 is_stmt 0 view .LVU800 + 2514 01fc BBF1030F cmp fp, #3 + 2515 0200 2ED0 beq .L227 +3158:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ + 2516 .loc 1 3158 4 is_stmt 1 view .LVU801 +3158:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ + 2517 .loc 1 3158 7 is_stmt 0 view .LVU802 + 2518 0202 BAF1000F cmp r10, #0 + 2519 0206 00F09D80 beq .L221 +3159:Middlewares/Third_Party/FatFs/src/ff.c **** szbfat = (fmt == FS_FAT16) ? /* (Needed FAT size) */ + 2520 .loc 1 3159 4 is_stmt 1 view .LVU803 +3159:Middlewares/Third_Party/FatFs/src/ff.c **** szbfat = (fmt == FS_FAT16) ? /* (Needed FAT size) */ + 2521 .loc 1 3159 30 is_stmt 0 view .LVU804 + 2522 020a 009B ldr r3, [sp] + 2523 020c 1A44 add r2, r2, r3 +3159:Middlewares/Third_Party/FatFs/src/ff.c **** szbfat = (fmt == FS_FAT16) ? /* (Needed FAT size) */ + 2524 .loc 1 3159 16 view .LVU805 + 2525 020e A262 str r2, [r4, #40] +3160:Middlewares/Third_Party/FatFs/src/ff.c **** fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); + 2526 .loc 1 3160 4 is_stmt 1 view .LVU806 +3161:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2527 .loc 1 3161 22 is_stmt 0 view .LVU807 + 2528 0210 BBF1020F cmp fp, #2 + 2529 0214 35D0 beq .L228 +3161:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2530 .loc 1 3161 37 discriminator 2 view .LVU808 + 2531 0216 09EB4902 add r2, r9, r9, lsl #1 +3161:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2532 .loc 1 3161 61 discriminator 2 view .LVU809 + 2533 021a 09F00103 and r3, r9, #1 +3161:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2534 .loc 1 3161 22 discriminator 2 view .LVU810 + ARM GAS /tmp/cc2SVLkL.s page 158 + + + 2535 021e 03EB5203 add r3, r3, r2, lsr #1 + 2536 .LVL277: + 2537 .L193: +3163:Middlewares/Third_Party/FatFs/src/ff.c **** + 2538 .loc 1 3163 3 is_stmt 1 view .LVU811 +3163:Middlewares/Third_Party/FatFs/src/ff.c **** + 2539 .loc 1 3163 27 is_stmt 0 view .LVU812 + 2540 0222 4344 add r3, r3, r8 + 2541 .LVL278: +3163:Middlewares/Third_Party/FatFs/src/ff.c **** + 2542 .loc 1 3163 27 view .LVU813 + 2543 0224 013B subs r3, r3, #1 +3163:Middlewares/Third_Party/FatFs/src/ff.c **** + 2544 .loc 1 3163 43 view .LVU814 + 2545 0226 B3FBF8F3 udiv r3, r3, r8 +3163:Middlewares/Third_Party/FatFs/src/ff.c **** + 2546 .loc 1 3163 6 view .LVU815 + 2547 022a BB42 cmp r3, r7 + 2548 022c 00F28C80 bhi .L222 +3167:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag = 0x80; + 2549 .loc 1 3167 3 is_stmt 1 view .LVU816 +3167:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag = 0x80; + 2550 .loc 1 3167 33 is_stmt 0 view .LVU817 + 2551 0230 4FF0FF33 mov r3, #-1 + 2552 0234 6361 str r3, [r4, #20] +3167:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag = 0x80; + 2553 .loc 1 3167 17 view .LVU818 + 2554 0236 2361 str r3, [r4, #16] +3168:Middlewares/Third_Party/FatFs/src/ff.c **** #if (_FS_NOFSINFO & 3) != 3 + 2555 .loc 1 3168 3 is_stmt 1 view .LVU819 +3168:Middlewares/Third_Party/FatFs/src/ff.c **** #if (_FS_NOFSINFO & 3) != 3 + 2556 .loc 1 3168 16 is_stmt 0 view .LVU820 + 2557 0238 8023 movs r3, #128 + 2558 023a 2371 strb r3, [r4, #4] +3170:Middlewares/Third_Party/FatFs/src/ff.c **** && ld_word(fs->win + BPB_FSInfo32) == 1 + 2559 .loc 1 3170 3 is_stmt 1 view .LVU821 +3170:Middlewares/Third_Party/FatFs/src/ff.c **** && ld_word(fs->win + BPB_FSInfo32) == 1 + 2560 .loc 1 3170 6 is_stmt 0 view .LVU822 + 2561 023c BBF1030F cmp fp, #3 + 2562 0240 22D0 beq .L229 + 2563 .L195: +3191:Middlewares/Third_Party/FatFs/src/ff.c **** fs->id = ++Fsid; /* File system mount ID */ + 2564 .loc 1 3191 2 is_stmt 1 view .LVU823 +3191:Middlewares/Third_Party/FatFs/src/ff.c **** fs->id = ++Fsid; /* File system mount ID */ + 2565 .loc 1 3191 14 is_stmt 0 view .LVU824 + 2566 0242 84F800B0 strb fp, [r4] +3192:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN == 1 + 2567 .loc 1 3192 2 is_stmt 1 view .LVU825 +3192:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN == 1 + 2568 .loc 1 3192 11 is_stmt 0 view .LVU826 + 2569 0246 344A ldr r2, .L230+4 + 2570 0248 1388 ldrh r3, [r2] + 2571 024a 0133 adds r3, r3, #1 + 2572 024c 9BB2 uxth r3, r3 +3192:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN == 1 + 2573 .loc 1 3192 9 view .LVU827 + 2574 024e 1380 strh r3, [r2] @ movhi + ARM GAS /tmp/cc2SVLkL.s page 159 + + + 2575 0250 E380 strh r3, [r4, #6] @ movhi +3203:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 2576 .loc 1 3203 2 is_stmt 1 view .LVU828 + 2577 0252 2046 mov r0, r4 + 2578 0254 FFF7FEFF bl clear_lock + 2579 .LVL279: +3205:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2580 .loc 1 3205 2 view .LVU829 +3205:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2581 .loc 1 3205 9 is_stmt 0 view .LVU830 + 2582 0258 46E0 b .L180 + 2583 .LVL280: + 2584 .L218: +3145:Middlewares/Third_Party/FatFs/src/ff.c **** + 2585 .loc 1 3145 31 discriminator 1 view .LVU831 + 2586 025a 4FF0010B mov fp, #1 + 2587 025e C4E7 b .L191 + 2588 .LVL281: + 2589 .L227: +3153:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ + 2590 .loc 1 3153 4 is_stmt 1 view .LVU832 +3153:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ + 2591 .loc 1 3153 8 is_stmt 0 view .LVU833 + 2592 0260 04F15E00 add r0, r4, #94 + 2593 .LVL282: +3153:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ + 2594 .loc 1 3153 8 view .LVU834 + 2595 0264 FFF7FEFF bl ld_word + 2596 .LVL283: +3153:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ + 2597 .loc 1 3153 7 discriminator 1 view .LVU835 + 2598 0268 0028 cmp r0, #0 + 2599 026a 67D1 bne .L219 +3154:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbase = ld_dword(fs->win + BPB_RootClus32); /* Root directory start cluster */ + 2600 .loc 1 3154 4 is_stmt 1 view .LVU836 +3154:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbase = ld_dword(fs->win + BPB_RootClus32); /* Root directory start cluster */ + 2601 .loc 1 3154 7 is_stmt 0 view .LVU837 + 2602 026c BAF1000F cmp r10, #0 + 2603 0270 66D1 bne .L220 +3155:Middlewares/Third_Party/FatFs/src/ff.c **** szbfat = fs->n_fatent * 4; /* (Needed FAT size) */ + 2604 .loc 1 3155 4 is_stmt 1 view .LVU838 +3155:Middlewares/Third_Party/FatFs/src/ff.c **** szbfat = fs->n_fatent * 4; /* (Needed FAT size) */ + 2605 .loc 1 3155 18 is_stmt 0 view .LVU839 + 2606 0272 04F16000 add r0, r4, #96 + 2607 0276 FFF7FEFF bl ld_dword + 2608 .LVL284: +3155:Middlewares/Third_Party/FatFs/src/ff.c **** szbfat = fs->n_fatent * 4; /* (Needed FAT size) */ + 2609 .loc 1 3155 16 discriminator 1 view .LVU840 + 2610 027a A062 str r0, [r4, #40] +3156:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 2611 .loc 1 3156 4 is_stmt 1 view .LVU841 +3156:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 2612 .loc 1 3156 11 is_stmt 0 view .LVU842 + 2613 027c 4FEA8903 lsl r3, r9, #2 + 2614 .LVL285: +3156:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 2615 .loc 1 3156 11 view .LVU843 + ARM GAS /tmp/cc2SVLkL.s page 160 + + + 2616 0280 CFE7 b .L193 + 2617 .LVL286: + 2618 .L228: +3161:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2619 .loc 1 3161 22 discriminator 1 view .LVU844 + 2620 0282 4FEA4903 lsl r3, r9, #1 + 2621 0286 CCE7 b .L193 + 2622 .LVL287: + 2623 .L229: +3171:Middlewares/Third_Party/FatFs/src/ff.c **** && move_window(fs, bsect + 1) == FR_OK) + 2624 .loc 1 3171 7 view .LVU845 + 2625 0288 04F16400 add r0, r4, #100 + 2626 028c FFF7FEFF bl ld_word + 2627 .LVL288: +3171:Middlewares/Third_Party/FatFs/src/ff.c **** && move_window(fs, bsect + 1) == FR_OK) + 2628 .loc 1 3171 4 discriminator 1 view .LVU846 + 2629 0290 0128 cmp r0, #1 + 2630 0292 D6D1 bne .L195 +3172:Middlewares/Third_Party/FatFs/src/ff.c **** { + 2631 .loc 1 3172 7 view .LVU847 + 2632 0294 711C adds r1, r6, #1 + 2633 0296 2046 mov r0, r4 + 2634 0298 FFF7FEFF bl move_window + 2635 .LVL289: +3172:Middlewares/Third_Party/FatFs/src/ff.c **** { + 2636 .loc 1 3172 4 discriminator 1 view .LVU848 + 2637 029c 0028 cmp r0, #0 + 2638 029e D0D1 bne .L195 +3174:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_word(fs->win + BS_55AA) == 0xAA55 /* Load FSINFO data if available */ + 2639 .loc 1 3174 4 is_stmt 1 view .LVU849 +3174:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_word(fs->win + BS_55AA) == 0xAA55 /* Load FSINFO data if available */ + 2640 .loc 1 3174 17 is_stmt 0 view .LVU850 + 2641 02a0 0023 movs r3, #0 + 2642 02a2 2371 strb r3, [r4, #4] +3175:Middlewares/Third_Party/FatFs/src/ff.c **** && ld_dword(fs->win + FSI_LeadSig) == 0x41615252 + 2643 .loc 1 3175 4 is_stmt 1 view .LVU851 +3175:Middlewares/Third_Party/FatFs/src/ff.c **** && ld_dword(fs->win + FSI_LeadSig) == 0x41615252 + 2644 .loc 1 3175 8 is_stmt 0 view .LVU852 + 2645 02a4 04F23220 addw r0, r4, #562 + 2646 02a8 FFF7FEFF bl ld_word + 2647 .LVL290: +3175:Middlewares/Third_Party/FatFs/src/ff.c **** && ld_dword(fs->win + FSI_LeadSig) == 0x41615252 + 2648 .loc 1 3175 7 discriminator 1 view .LVU853 + 2649 02ac 4AF65523 movw r3, #43605 + 2650 02b0 9842 cmp r0, r3 + 2651 02b2 C6D1 bne .L195 +3176:Middlewares/Third_Party/FatFs/src/ff.c **** && ld_dword(fs->win + FSI_StrucSig) == 0x61417272) + 2652 .loc 1 3176 8 view .LVU854 + 2653 02b4 04F13400 add r0, r4, #52 + 2654 02b8 FFF7FEFF bl ld_dword + 2655 .LVL291: +3176:Middlewares/Third_Party/FatFs/src/ff.c **** && ld_dword(fs->win + FSI_StrucSig) == 0x61417272) + 2656 .loc 1 3176 5 discriminator 1 view .LVU855 + 2657 02bc 174B ldr r3, .L230+8 + 2658 02be 9842 cmp r0, r3 + 2659 02c0 BFD1 bne .L195 +3177:Middlewares/Third_Party/FatFs/src/ff.c **** { + ARM GAS /tmp/cc2SVLkL.s page 161 + + + 2660 .loc 1 3177 8 view .LVU856 + 2661 02c2 04F50670 add r0, r4, #536 + 2662 02c6 FFF7FEFF bl ld_dword + 2663 .LVL292: +3177:Middlewares/Third_Party/FatFs/src/ff.c **** { + 2664 .loc 1 3177 5 discriminator 1 view .LVU857 + 2665 02ca 154B ldr r3, .L230+12 + 2666 02cc 9842 cmp r0, r3 + 2667 02ce B8D1 bne .L195 +3180:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 2668 .loc 1 3180 5 is_stmt 1 view .LVU858 +3180:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 2669 .loc 1 3180 21 is_stmt 0 view .LVU859 + 2670 02d0 04F50770 add r0, r4, #540 + 2671 02d4 FFF7FEFF bl ld_dword + 2672 .LVL293: +3180:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 2673 .loc 1 3180 19 discriminator 1 view .LVU860 + 2674 02d8 6061 str r0, [r4, #20] +3183:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 2675 .loc 1 3183 5 is_stmt 1 view .LVU861 +3183:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 2676 .loc 1 3183 21 is_stmt 0 view .LVU862 + 2677 02da 04F50870 add r0, r4, #544 + 2678 02de FFF7FEFF bl ld_dword + 2679 .LVL294: +3183:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 2680 .loc 1 3183 19 discriminator 1 view .LVU863 + 2681 02e2 2061 str r0, [r4, #16] + 2682 02e4 ADE7 b .L195 + 2683 .LVL295: + 2684 .L196: +3011:Middlewares/Third_Party/FatFs/src/ff.c **** + 2685 .loc 1 3011 22 discriminator 1 view .LVU864 + 2686 02e6 0B25 movs r5, #11 + 2687 .LVL296: + 2688 .L180: +3206:Middlewares/Third_Party/FatFs/src/ff.c **** + 2689 .loc 1 3206 1 view .LVU865 + 2690 02e8 2846 mov r0, r5 + 2691 02ea 07B0 add sp, sp, #28 + 2692 .LCFI20: + 2693 .cfi_remember_state + 2694 .cfi_def_cfa_offset 36 + 2695 @ sp needed + 2696 02ec BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 2697 .LVL297: + 2698 .L197: + 2699 .LCFI21: + 2700 .cfi_restore_state +3015:Middlewares/Third_Party/FatFs/src/ff.c **** + 2701 .loc 1 3015 18 discriminator 1 view .LVU866 + 2702 02f0 0C25 movs r5, #12 + 2703 .LVL298: +3015:Middlewares/Third_Party/FatFs/src/ff.c **** + 2704 .loc 1 3015 18 discriminator 1 view .LVU867 + 2705 02f2 F9E7 b .L180 + ARM GAS /tmp/cc2SVLkL.s page 162 + + + 2706 .LVL299: + 2707 .L199: +3038:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2708 .loc 1 3038 10 view .LVU868 + 2709 02f4 0325 movs r5, #3 + 2710 02f6 F7E7 b .L180 + 2711 .L200: +3041:Middlewares/Third_Party/FatFs/src/ff.c **** } + 2712 .loc 1 3041 10 view .LVU869 + 2713 02f8 0A25 movs r5, #10 + 2714 02fa F5E7 b .L180 + 2715 .LVL300: + 2716 .L201: +3044:Middlewares/Third_Party/FatFs/src/ff.c **** if (SS(fs) > _MAX_SS || SS(fs) < _MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR; + 2717 .loc 1 3044 70 discriminator 1 view .LVU870 + 2718 02fc 0125 movs r5, #1 + 2719 02fe F3E7 b .L180 + 2720 .L202: +3045:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 2721 .loc 1 3045 78 discriminator 3 view .LVU871 + 2722 0300 0125 movs r5, #1 + 2723 0302 F1E7 b .L180 + 2724 .LVL301: + 2725 .L207: +3063:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt >= 2) return FR_NO_FILESYSTEM; /* No FAT volume is found */ + 2726 .loc 1 3063 23 discriminator 1 view .LVU872 + 2727 0304 0125 movs r5, #1 + 2728 0306 EFE7 b .L180 + 2729 .L208: +3064:Middlewares/Third_Party/FatFs/src/ff.c **** + 2730 .loc 1 3064 23 discriminator 1 view .LVU873 + 2731 0308 0D25 movs r5, #13 + 2732 030a EDE7 b .L180 + 2733 .LVL302: + 2734 .L209: +3116:Middlewares/Third_Party/FatFs/src/ff.c **** + 2735 .loc 1 3116 59 discriminator 1 view .LVU874 + 2736 030c 0D25 movs r5, #13 + 2737 030e EBE7 b .L180 + 2738 .LVL303: + 2739 .L210: +3123:Middlewares/Third_Party/FatFs/src/ff.c **** fasize *= fs->n_fats; /* Number of sectors for FAT area */ + 2740 .loc 1 3123 50 discriminator 1 view .LVU875 + 2741 0310 0D25 movs r5, #13 + 2742 0312 E9E7 b .L180 + 2743 .L231: + 2744 .align 2 + 2745 .L230: + 2746 0314 00000000 .word FatFs + 2747 0318 00000000 .word Fsid + 2748 031c 52526141 .word 1096897106 + 2749 0320 72724161 .word 1631679090 + 2750 .LVL304: + 2751 .L211: +3127:Middlewares/Third_Party/FatFs/src/ff.c **** + 2752 .loc 1 3127 63 discriminator 3 view .LVU876 + 2753 0324 0D25 movs r5, #13 + ARM GAS /tmp/cc2SVLkL.s page 163 + + + 2754 0326 DFE7 b .L180 + 2755 .LVL305: + 2756 .L212: +3127:Middlewares/Third_Party/FatFs/src/ff.c **** + 2757 .loc 1 3127 63 discriminator 3 view .LVU877 + 2758 0328 0D25 movs r5, #13 + 2759 032a DDE7 b .L180 + 2760 .L213: +3130:Middlewares/Third_Party/FatFs/src/ff.c **** + 2761 .loc 1 3130 49 discriminator 1 view .LVU878 + 2762 032c 0D25 movs r5, #13 + 2763 032e DBE7 b .L180 + 2764 .LVL306: + 2765 .L214: +3136:Middlewares/Third_Party/FatFs/src/ff.c **** + 2766 .loc 1 3136 25 discriminator 1 view .LVU879 + 2767 0330 0D25 movs r5, #13 + 2768 0332 D9E7 b .L180 + 2769 .LVL307: + 2770 .L215: +3140:Middlewares/Third_Party/FatFs/src/ff.c **** nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ + 2771 .loc 1 3140 30 discriminator 1 view .LVU880 + 2772 0334 0D25 movs r5, #13 + 2773 0336 D7E7 b .L180 + 2774 .LVL308: + 2775 .L216: +3142:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = FS_FAT32; + 2776 .loc 1 3142 26 discriminator 1 view .LVU881 + 2777 0338 0D25 movs r5, #13 + 2778 033a D5E7 b .L180 + 2779 .LVL309: + 2780 .L219: +3153:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ + 2781 .loc 1 3153 52 discriminator 1 view .LVU882 + 2782 033c 0D25 movs r5, #13 + 2783 033e D3E7 b .L180 + 2784 .L220: +3154:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbase = ld_dword(fs->win + BPB_RootClus32); /* Root directory start cluster */ + 2785 .loc 1 3154 30 discriminator 1 view .LVU883 + 2786 0340 0D25 movs r5, #13 + 2787 0342 D1E7 b .L180 + 2788 .LVL310: + 2789 .L221: +3158:Middlewares/Third_Party/FatFs/src/ff.c **** fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ + 2790 .loc 1 3158 35 discriminator 1 view .LVU884 + 2791 0344 0D25 movs r5, #13 + 2792 0346 CFE7 b .L180 + 2793 .LVL311: + 2794 .L222: +3163:Middlewares/Third_Party/FatFs/src/ff.c **** + 2795 .loc 1 3163 60 discriminator 1 view .LVU885 + 2796 0348 0D25 movs r5, #13 + 2797 034a CDE7 b .L180 + 2798 .cfi_endproc + 2799 .LFE1219: + 2801 .section .text.put_fat,"ax",%progbits + 2802 .align 1 + ARM GAS /tmp/cc2SVLkL.s page 164 + + + 2803 .syntax unified + 2804 .thumb + 2805 .thumb_func + 2807 put_fat: + 2808 .LVL312: + 2809 .LFB1201: +1086:Middlewares/Third_Party/FatFs/src/ff.c **** UINT bc; + 2810 .loc 1 1086 1 is_stmt 1 view -0 + 2811 .cfi_startproc + 2812 @ args = 0, pretend = 0, frame = 0 + 2813 @ frame_needed = 0, uses_anonymous_args = 0 +1086:Middlewares/Third_Party/FatFs/src/ff.c **** UINT bc; + 2814 .loc 1 1086 1 is_stmt 0 view .LVU887 + 2815 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, r10, lr} + 2816 .LCFI22: + 2817 .cfi_def_cfa_offset 32 + 2818 .cfi_offset 4, -32 + 2819 .cfi_offset 5, -28 + 2820 .cfi_offset 6, -24 + 2821 .cfi_offset 7, -20 + 2822 .cfi_offset 8, -16 + 2823 .cfi_offset 9, -12 + 2824 .cfi_offset 10, -8 + 2825 .cfi_offset 14, -4 +1087:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE *p; + 2826 .loc 1 1087 2 is_stmt 1 view .LVU888 +1088:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res = FR_INT_ERR; + 2827 .loc 1 1088 2 view .LVU889 +1089:Middlewares/Third_Party/FatFs/src/ff.c **** + 2828 .loc 1 1089 2 view .LVU890 + 2829 .LVL313: +1091:Middlewares/Third_Party/FatFs/src/ff.c **** switch (fs->fs_type) { + 2830 .loc 1 1091 2 view .LVU891 +1091:Middlewares/Third_Party/FatFs/src/ff.c **** switch (fs->fs_type) { + 2831 .loc 1 1091 5 is_stmt 0 view .LVU892 + 2832 0004 0129 cmp r1, #1 + 2833 0006 40F28E80 bls .L240 + 2834 000a 0446 mov r4, r0 + 2835 000c 0D46 mov r5, r1 + 2836 000e 1746 mov r7, r2 +1091:Middlewares/Third_Party/FatFs/src/ff.c **** switch (fs->fs_type) { + 2837 .loc 1 1091 28 discriminator 1 view .LVU893 + 2838 0010 8369 ldr r3, [r0, #24] +1091:Middlewares/Third_Party/FatFs/src/ff.c **** switch (fs->fs_type) { + 2839 .loc 1 1091 16 discriminator 1 view .LVU894 + 2840 0012 8B42 cmp r3, r1 + 2841 0014 40F28B80 bls .L241 +1092:Middlewares/Third_Party/FatFs/src/ff.c **** case FS_FAT12 : /* Bitfield items */ + 2842 .loc 1 1092 3 is_stmt 1 view .LVU895 +1092:Middlewares/Third_Party/FatFs/src/ff.c **** case FS_FAT12 : /* Bitfield items */ + 2843 .loc 1 1092 13 is_stmt 0 view .LVU896 + 2844 0018 0378 ldrb r3, [r0] @ zero_extendqisi2 +1092:Middlewares/Third_Party/FatFs/src/ff.c **** case FS_FAT12 : /* Bitfield items */ + 2845 .loc 1 1092 3 view .LVU897 + 2846 001a 022B cmp r3, #2 + 2847 001c 49D0 beq .L234 + 2848 001e 032B cmp r3, #3 + ARM GAS /tmp/cc2SVLkL.s page 165 + + + 2849 0020 60D0 beq .L235 + 2850 0022 012B cmp r3, #1 + 2851 0024 40F08580 bne .L242 +1094:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, fs->fatbase + (bc / SS(fs))); + 2852 .loc 1 1094 4 is_stmt 1 view .LVU898 + 2853 .LVL314: +1094:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, fs->fatbase + (bc / SS(fs))); + 2854 .loc 1 1094 21 view .LVU899 +1094:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, fs->fatbase + (bc / SS(fs))); + 2855 .loc 1 1094 24 is_stmt 0 view .LVU900 + 2856 0028 01EB5108 add r8, r1, r1, lsr #1 + 2857 .LVL315: +1095:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 2858 .loc 1 1095 4 is_stmt 1 view .LVU901 +1095:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 2859 .loc 1 1095 28 is_stmt 0 view .LVU902 + 2860 002c 416A ldr r1, [r0, #36] + 2861 .LVL316: +1095:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 2862 .loc 1 1095 46 view .LVU903 + 2863 002e 8389 ldrh r3, [r0, #12] +1095:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 2864 .loc 1 1095 44 view .LVU904 + 2865 0030 B8FBF3F3 udiv r3, r8, r3 +1095:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 2866 .loc 1 1095 10 view .LVU905 + 2867 0034 1944 add r1, r1, r3 + 2868 0036 FFF7FEFF bl move_window + 2869 .LVL317: +1096:Middlewares/Third_Party/FatFs/src/ff.c **** p = fs->win + bc++ % SS(fs); + 2870 .loc 1 1096 4 is_stmt 1 view .LVU906 +1096:Middlewares/Third_Party/FatFs/src/ff.c **** p = fs->win + bc++ % SS(fs); + 2871 .loc 1 1096 7 is_stmt 0 view .LVU907 + 2872 003a 0646 mov r6, r0 + 2873 003c 0028 cmp r0, #0 + 2874 003e 73D1 bne .L233 +1097:Middlewares/Third_Party/FatFs/src/ff.c **** *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; + 2875 .loc 1 1097 4 is_stmt 1 view .LVU908 +1097:Middlewares/Third_Party/FatFs/src/ff.c **** *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; + 2876 .loc 1 1097 8 is_stmt 0 view .LVU909 + 2877 0040 04F1340A add r10, r4, #52 +1097:Middlewares/Third_Party/FatFs/src/ff.c **** *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; + 2878 .loc 1 1097 20 view .LVU910 + 2879 0044 08F10109 add r9, r8, #1 + 2880 .LVL318: +1097:Middlewares/Third_Party/FatFs/src/ff.c **** *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; + 2881 .loc 1 1097 25 view .LVU911 + 2882 0048 A389 ldrh r3, [r4, #12] +1097:Middlewares/Third_Party/FatFs/src/ff.c **** *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; + 2883 .loc 1 1097 23 view .LVU912 + 2884 004a B8FBF3F2 udiv r2, r8, r3 + 2885 004e 03FB1288 mls r8, r3, r2, r8 + 2886 .LVL319: +1098:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2887 .loc 1 1098 4 is_stmt 1 view .LVU913 +1098:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2888 .loc 1 1098 7 is_stmt 0 view .LVU914 + ARM GAS /tmp/cc2SVLkL.s page 166 + + + 2889 0052 15F00105 ands r5, r5, #1 + 2890 .LVL320: +1098:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2891 .loc 1 1098 7 view .LVU915 + 2892 0056 22D0 beq .L236 +1098:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2893 .loc 1 1098 24 discriminator 1 view .LVU916 + 2894 0058 1AF80830 ldrb r3, [r10, r8] @ zero_extendqisi2 +1098:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2895 .loc 1 1098 7 discriminator 1 view .LVU917 + 2896 005c 03F00F03 and r3, r3, #15 + 2897 0060 43EA0713 orr r3, r3, r7, lsl #4 + 2898 0064 DBB2 uxtb r3, r3 + 2899 .L237: +1098:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2900 .loc 1 1098 7 discriminator 4 view .LVU918 + 2901 0066 0AF80830 strb r3, [r10, r8] +1099:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, fs->fatbase + (bc / SS(fs))); + 2902 .loc 1 1099 4 is_stmt 1 view .LVU919 +1099:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, fs->fatbase + (bc / SS(fs))); + 2903 .loc 1 1099 14 is_stmt 0 view .LVU920 + 2904 006a 0123 movs r3, #1 + 2905 006c E370 strb r3, [r4, #3] +1100:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 2906 .loc 1 1100 4 is_stmt 1 view .LVU921 +1100:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 2907 .loc 1 1100 28 is_stmt 0 view .LVU922 + 2908 006e 616A ldr r1, [r4, #36] +1100:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 2909 .loc 1 1100 46 view .LVU923 + 2910 0070 A389 ldrh r3, [r4, #12] +1100:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 2911 .loc 1 1100 44 view .LVU924 + 2912 0072 B9FBF3F3 udiv r3, r9, r3 +1100:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 2913 .loc 1 1100 10 view .LVU925 + 2914 0076 1944 add r1, r1, r3 + 2915 0078 2046 mov r0, r4 + 2916 .LVL321: +1100:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 2917 .loc 1 1100 10 view .LVU926 + 2918 007a FFF7FEFF bl move_window + 2919 .LVL322: +1101:Middlewares/Third_Party/FatFs/src/ff.c **** p = fs->win + bc % SS(fs); + 2920 .loc 1 1101 4 is_stmt 1 view .LVU927 +1101:Middlewares/Third_Party/FatFs/src/ff.c **** p = fs->win + bc % SS(fs); + 2921 .loc 1 1101 7 is_stmt 0 view .LVU928 + 2922 007e 0646 mov r6, r0 + 2923 0080 0028 cmp r0, #0 + 2924 0082 51D1 bne .L233 +1102:Middlewares/Third_Party/FatFs/src/ff.c **** *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); + 2925 .loc 1 1102 4 is_stmt 1 view .LVU929 +1102:Middlewares/Third_Party/FatFs/src/ff.c **** *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); + 2926 .loc 1 1102 23 is_stmt 0 view .LVU930 + 2927 0084 A389 ldrh r3, [r4, #12] +1102:Middlewares/Third_Party/FatFs/src/ff.c **** *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); + 2928 .loc 1 1102 21 view .LVU931 + ARM GAS /tmp/cc2SVLkL.s page 167 + + + 2929 0086 B9FBF3F2 udiv r2, r9, r3 + 2930 008a 03FB1299 mls r9, r3, r2, r9 + 2931 .LVL323: +1103:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2932 .loc 1 1103 4 is_stmt 1 view .LVU932 +1103:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2933 .loc 1 1103 7 is_stmt 0 view .LVU933 + 2934 008e 45B1 cbz r5, .L238 +1103:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2935 .loc 1 1103 7 discriminator 1 view .LVU934 + 2936 0090 C7F30713 ubfx r3, r7, #4, #8 + 2937 .L239: +1103:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2938 .loc 1 1103 7 discriminator 4 view .LVU935 + 2939 0094 0AF80930 strb r3, [r10, r9] +1104:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 2940 .loc 1 1104 4 is_stmt 1 view .LVU936 +1104:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 2941 .loc 1 1104 14 is_stmt 0 view .LVU937 + 2942 0098 0123 movs r3, #1 + 2943 009a E370 strb r3, [r4, #3] +1105:Middlewares/Third_Party/FatFs/src/ff.c **** + 2944 .loc 1 1105 4 is_stmt 1 view .LVU938 + 2945 009c 44E0 b .L233 + 2946 .LVL324: + 2947 .L236: +1098:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2948 .loc 1 1098 7 is_stmt 0 discriminator 2 view .LVU939 + 2949 009e FBB2 uxtb r3, r7 + 2950 00a0 E1E7 b .L237 + 2951 .LVL325: + 2952 .L238: +1103:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2953 .loc 1 1103 43 discriminator 2 view .LVU940 + 2954 00a2 1AF80930 ldrb r3, [r10, r9] @ zero_extendqisi2 +1103:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2955 .loc 1 1103 74 discriminator 2 view .LVU941 + 2956 00a6 C7F30322 ubfx r2, r7, #8, #4 +1103:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2957 .loc 1 1103 7 discriminator 2 view .LVU942 + 2958 00aa 23F00F03 bic r3, r3, #15 + 2959 00ae 1343 orrs r3, r3, r2 + 2960 00b0 F0E7 b .L239 + 2961 .LVL326: + 2962 .L234: +1108:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 2963 .loc 1 1108 4 is_stmt 1 view .LVU943 +1108:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 2964 .loc 1 1108 28 is_stmt 0 view .LVU944 + 2965 00b2 416A ldr r1, [r0, #36] + 2966 .LVL327: +1108:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 2967 .loc 1 1108 49 view .LVU945 + 2968 00b4 8389 ldrh r3, [r0, #12] +1108:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 2969 .loc 1 1108 56 view .LVU946 + 2970 00b6 5B08 lsrs r3, r3, #1 + ARM GAS /tmp/cc2SVLkL.s page 168 + + +1108:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 2971 .loc 1 1108 46 view .LVU947 + 2972 00b8 B5FBF3F3 udiv r3, r5, r3 +1108:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 2973 .loc 1 1108 10 view .LVU948 + 2974 00bc 1944 add r1, r1, r3 + 2975 00be FFF7FEFF bl move_window + 2976 .LVL328: +1109:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(fs->win + clst * 2 % SS(fs), (WORD)val); + 2977 .loc 1 1109 4 is_stmt 1 view .LVU949 +1109:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(fs->win + clst * 2 % SS(fs), (WORD)val); + 2978 .loc 1 1109 7 is_stmt 0 view .LVU950 + 2979 00c2 0646 mov r6, r0 + 2980 00c4 80BB cbnz r0, .L233 +1110:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2981 .loc 1 1110 4 is_stmt 1 view .LVU951 +1110:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2982 .loc 1 1110 12 is_stmt 0 view .LVU952 + 2983 00c6 04F13400 add r0, r4, #52 + 2984 .LVL329: +1110:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2985 .loc 1 1110 27 view .LVU953 + 2986 00ca 6D00 lsls r5, r5, #1 + 2987 .LVL330: +1110:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2988 .loc 1 1110 33 view .LVU954 + 2989 00cc A389 ldrh r3, [r4, #12] +1110:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2990 .loc 1 1110 31 view .LVU955 + 2991 00ce B5FBF3F2 udiv r2, r5, r3 + 2992 00d2 03FB1255 mls r5, r3, r2, r5 +1110:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 2993 .loc 1 1110 4 view .LVU956 + 2994 00d6 B9B2 uxth r1, r7 + 2995 00d8 2844 add r0, r0, r5 + 2996 00da FFF7FEFF bl st_word + 2997 .LVL331: +1111:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 2998 .loc 1 1111 4 is_stmt 1 view .LVU957 +1111:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 2999 .loc 1 1111 14 is_stmt 0 view .LVU958 + 3000 00de 0123 movs r3, #1 + 3001 00e0 E370 strb r3, [r4, #3] +1112:Middlewares/Third_Party/FatFs/src/ff.c **** + 3002 .loc 1 1112 4 is_stmt 1 view .LVU959 + 3003 00e2 21E0 b .L233 + 3004 .LVL332: + 3005 .L235: +1118:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 3006 .loc 1 1118 4 view .LVU960 +1118:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 3007 .loc 1 1118 28 is_stmt 0 view .LVU961 + 3008 00e4 416A ldr r1, [r0, #36] + 3009 .LVL333: +1118:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 3010 .loc 1 1118 49 view .LVU962 + 3011 00e6 8389 ldrh r3, [r0, #12] + ARM GAS /tmp/cc2SVLkL.s page 169 + + +1118:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 3012 .loc 1 1118 56 view .LVU963 + 3013 00e8 9B08 lsrs r3, r3, #2 +1118:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 3014 .loc 1 1118 46 view .LVU964 + 3015 00ea B5FBF3F3 udiv r3, r5, r3 +1118:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 3016 .loc 1 1118 10 view .LVU965 + 3017 00ee 1944 add r1, r1, r3 + 3018 00f0 FFF7FEFF bl move_window + 3019 .LVL334: +1119:Middlewares/Third_Party/FatFs/src/ff.c **** if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { + 3020 .loc 1 1119 4 is_stmt 1 view .LVU966 +1119:Middlewares/Third_Party/FatFs/src/ff.c **** if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { + 3021 .loc 1 1119 7 is_stmt 0 view .LVU967 + 3022 00f4 0646 mov r6, r0 + 3023 00f6 B8B9 cbnz r0, .L233 +1120:Middlewares/Third_Party/FatFs/src/ff.c **** val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000); + 3024 .loc 1 1120 4 is_stmt 1 view .LVU968 +1121:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3025 .loc 1 1121 5 view .LVU969 +1121:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3026 .loc 1 1121 16 is_stmt 0 view .LVU970 + 3027 00f8 27F07047 bic r7, r7, #-268435456 + 3028 .LVL335: +1121:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3029 .loc 1 1121 42 view .LVU971 + 3030 00fc 04F13403 add r3, r4, #52 +1121:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3031 .loc 1 1121 57 view .LVU972 + 3032 0100 AD00 lsls r5, r5, #2 + 3033 .LVL336: +1121:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3034 .loc 1 1121 63 view .LVU973 + 3035 0102 A289 ldrh r2, [r4, #12] +1121:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3036 .loc 1 1121 61 view .LVU974 + 3037 0104 B5FBF2F1 udiv r1, r5, r2 + 3038 0108 02FB1155 mls r5, r2, r1, r5 +1121:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3039 .loc 1 1121 33 view .LVU975 + 3040 010c 1D44 add r5, r5, r3 + 3041 010e 2846 mov r0, r5 + 3042 .LVL337: +1121:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3043 .loc 1 1121 33 view .LVU976 + 3044 0110 FFF7FEFF bl ld_dword + 3045 .LVL338: +1121:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3046 .loc 1 1121 71 discriminator 1 view .LVU977 + 3047 0114 00F07041 and r1, r0, #-268435456 + 3048 .LVL339: +1123:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 3049 .loc 1 1123 4 is_stmt 1 view .LVU978 + 3050 0118 3943 orrs r1, r1, r7 + 3051 .LVL340: +1123:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + ARM GAS /tmp/cc2SVLkL.s page 170 + + + 3052 .loc 1 1123 4 is_stmt 0 view .LVU979 + 3053 011a 2846 mov r0, r5 + 3054 011c FFF7FEFF bl st_dword + 3055 .LVL341: +1124:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3056 .loc 1 1124 4 is_stmt 1 view .LVU980 +1124:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3057 .loc 1 1124 14 is_stmt 0 view .LVU981 + 3058 0120 0123 movs r3, #1 + 3059 0122 E370 strb r3, [r4, #3] +1125:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3060 .loc 1 1125 4 is_stmt 1 view .LVU982 + 3061 0124 00E0 b .L233 + 3062 .LVL342: + 3063 .L240: +1089:Middlewares/Third_Party/FatFs/src/ff.c **** + 3064 .loc 1 1089 10 is_stmt 0 view .LVU983 + 3065 0126 0226 movs r6, #2 + 3066 .LVL343: + 3067 .L233: +1128:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3068 .loc 1 1128 2 is_stmt 1 view .LVU984 +1129:Middlewares/Third_Party/FatFs/src/ff.c **** + 3069 .loc 1 1129 1 is_stmt 0 view .LVU985 + 3070 0128 3046 mov r0, r6 + 3071 012a BDE8F087 pop {r4, r5, r6, r7, r8, r9, r10, pc} + 3072 .LVL344: + 3073 .L241: +1089:Middlewares/Third_Party/FatFs/src/ff.c **** + 3074 .loc 1 1089 10 view .LVU986 + 3075 012e 0226 movs r6, #2 + 3076 0130 FAE7 b .L233 + 3077 .L242: +1092:Middlewares/Third_Party/FatFs/src/ff.c **** case FS_FAT12 : /* Bitfield items */ + 3078 .loc 1 1092 3 view .LVU987 + 3079 0132 0226 movs r6, #2 + 3080 0134 F8E7 b .L233 + 3081 .cfi_endproc + 3082 .LFE1201: + 3084 .section .text.get_fat,"ax",%progbits + 3085 .align 1 + 3086 .syntax unified + 3087 .thumb + 3088 .thumb_func + 3090 get_fat: + 3091 .LVL345: + 3092 .LFB1200: +1005:Middlewares/Third_Party/FatFs/src/ff.c **** UINT wc, bc; + 3093 .loc 1 1005 1 is_stmt 1 view -0 + 3094 .cfi_startproc + 3095 @ args = 0, pretend = 0, frame = 0 + 3096 @ frame_needed = 0, uses_anonymous_args = 0 +1005:Middlewares/Third_Party/FatFs/src/ff.c **** UINT wc, bc; + 3097 .loc 1 1005 1 is_stmt 0 view .LVU989 + 3098 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 3099 .LCFI23: + 3100 .cfi_def_cfa_offset 24 + ARM GAS /tmp/cc2SVLkL.s page 171 + + + 3101 .cfi_offset 3, -24 + 3102 .cfi_offset 4, -20 + 3103 .cfi_offset 5, -16 + 3104 .cfi_offset 6, -12 + 3105 .cfi_offset 7, -8 + 3106 .cfi_offset 14, -4 +1006:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD val; + 3107 .loc 1 1006 2 is_stmt 1 view .LVU990 +1007:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = obj->fs; + 3108 .loc 1 1007 2 view .LVU991 +1008:Middlewares/Third_Party/FatFs/src/ff.c **** + 3109 .loc 1 1008 2 view .LVU992 +1008:Middlewares/Third_Party/FatFs/src/ff.c **** + 3110 .loc 1 1008 9 is_stmt 0 view .LVU993 + 3111 0002 0568 ldr r5, [r0] + 3112 .LVL346: +1011:Middlewares/Third_Party/FatFs/src/ff.c **** val = 1; /* Internal error */ + 3113 .loc 1 1011 2 is_stmt 1 view .LVU994 +1011:Middlewares/Third_Party/FatFs/src/ff.c **** val = 1; /* Internal error */ + 3114 .loc 1 1011 5 is_stmt 0 view .LVU995 + 3115 0004 0129 cmp r1, #1 + 3116 0006 6AD9 bls .L249 + 3117 0008 0C46 mov r4, r1 +1011:Middlewares/Third_Party/FatFs/src/ff.c **** val = 1; /* Internal error */ + 3118 .loc 1 1011 28 discriminator 1 view .LVU996 + 3119 000a AB69 ldr r3, [r5, #24] +1011:Middlewares/Third_Party/FatFs/src/ff.c **** val = 1; /* Internal error */ + 3120 .loc 1 1011 15 discriminator 1 view .LVU997 + 3121 000c 8B42 cmp r3, r1 + 3122 000e 68D9 bls .L250 +1015:Middlewares/Third_Party/FatFs/src/ff.c **** + 3123 .loc 1 1015 3 is_stmt 1 view .LVU998 + 3124 .LVL347: +1017:Middlewares/Third_Party/FatFs/src/ff.c **** case FS_FAT12 : + 3125 .loc 1 1017 3 view .LVU999 +1017:Middlewares/Third_Party/FatFs/src/ff.c **** case FS_FAT12 : + 3126 .loc 1 1017 13 is_stmt 0 view .LVU1000 + 3127 0010 2B78 ldrb r3, [r5] @ zero_extendqisi2 +1017:Middlewares/Third_Party/FatFs/src/ff.c **** case FS_FAT12 : + 3128 .loc 1 1017 3 view .LVU1001 + 3129 0012 022B cmp r3, #2 + 3130 0014 35D0 beq .L246 + 3131 0016 032B cmp r3, #3 + 3132 0018 49D0 beq .L247 + 3133 001a 012B cmp r3, #1 + 3134 001c 63D1 bne .L251 +1019:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; + 3135 .loc 1 1019 4 is_stmt 1 view .LVU1002 + 3136 .LVL348: +1019:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; + 3137 .loc 1 1019 21 view .LVU1003 +1019:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; + 3138 .loc 1 1019 24 is_stmt 0 view .LVU1004 + 3139 001e 01EB5106 add r6, r1, r1, lsr #1 + 3140 .LVL349: +1020:Middlewares/Third_Party/FatFs/src/ff.c **** wc = fs->win[bc++ % SS(fs)]; + 3141 .loc 1 1020 4 is_stmt 1 view .LVU1005 + ARM GAS /tmp/cc2SVLkL.s page 172 + + +1020:Middlewares/Third_Party/FatFs/src/ff.c **** wc = fs->win[bc++ % SS(fs)]; + 3142 .loc 1 1020 26 is_stmt 0 view .LVU1006 + 3143 0022 696A ldr r1, [r5, #36] + 3144 .LVL350: +1020:Middlewares/Third_Party/FatFs/src/ff.c **** wc = fs->win[bc++ % SS(fs)]; + 3145 .loc 1 1020 44 view .LVU1007 + 3146 0024 AB89 ldrh r3, [r5, #12] +1020:Middlewares/Third_Party/FatFs/src/ff.c **** wc = fs->win[bc++ % SS(fs)]; + 3147 .loc 1 1020 42 view .LVU1008 + 3148 0026 B6FBF3F3 udiv r3, r6, r3 +1020:Middlewares/Third_Party/FatFs/src/ff.c **** wc = fs->win[bc++ % SS(fs)]; + 3149 .loc 1 1020 8 view .LVU1009 + 3150 002a 1944 add r1, r1, r3 + 3151 002c 2846 mov r0, r5 + 3152 .LVL351: +1020:Middlewares/Third_Party/FatFs/src/ff.c **** wc = fs->win[bc++ % SS(fs)]; + 3153 .loc 1 1020 8 view .LVU1010 + 3154 002e FFF7FEFF bl move_window + 3155 .LVL352: +1020:Middlewares/Third_Party/FatFs/src/ff.c **** wc = fs->win[bc++ % SS(fs)]; + 3156 .loc 1 1020 7 discriminator 1 view .LVU1011 + 3157 0032 10B1 cbz r0, .L257 +1015:Middlewares/Third_Party/FatFs/src/ff.c **** + 3158 .loc 1 1015 7 view .LVU1012 + 3159 0034 4FF0FF30 mov r0, #-1 + 3160 0038 52E0 b .L244 + 3161 .L257: +1021:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; + 3162 .loc 1 1021 4 is_stmt 1 view .LVU1013 +1021:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; + 3163 .loc 1 1021 19 is_stmt 0 view .LVU1014 + 3164 003a 771C adds r7, r6, #1 + 3165 .LVL353: +1021:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; + 3166 .loc 1 1021 24 view .LVU1015 + 3167 003c AB89 ldrh r3, [r5, #12] +1021:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; + 3168 .loc 1 1021 22 view .LVU1016 + 3169 003e B6FBF3F2 udiv r2, r6, r3 + 3170 0042 03FB1266 mls r6, r3, r2, r6 +1021:Middlewares/Third_Party/FatFs/src/ff.c **** if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break; + 3171 .loc 1 1021 16 view .LVU1017 + 3172 0046 2E44 add r6, r6, r5 + 3173 0048 96F83460 ldrb r6, [r6, #52] @ zero_extendqisi2 + 3174 .LVL354: +1022:Middlewares/Third_Party/FatFs/src/ff.c **** wc |= fs->win[bc % SS(fs)] << 8; + 3175 .loc 1 1022 4 is_stmt 1 view .LVU1018 +1022:Middlewares/Third_Party/FatFs/src/ff.c **** wc |= fs->win[bc % SS(fs)] << 8; + 3176 .loc 1 1022 26 is_stmt 0 view .LVU1019 + 3177 004c 696A ldr r1, [r5, #36] +1022:Middlewares/Third_Party/FatFs/src/ff.c **** wc |= fs->win[bc % SS(fs)] << 8; + 3178 .loc 1 1022 42 view .LVU1020 + 3179 004e B7FBF3F3 udiv r3, r7, r3 +1022:Middlewares/Third_Party/FatFs/src/ff.c **** wc |= fs->win[bc % SS(fs)] << 8; + 3180 .loc 1 1022 8 view .LVU1021 + 3181 0052 1944 add r1, r1, r3 + 3182 0054 2846 mov r0, r5 + ARM GAS /tmp/cc2SVLkL.s page 173 + + + 3183 0056 FFF7FEFF bl move_window + 3184 .LVL355: +1022:Middlewares/Third_Party/FatFs/src/ff.c **** wc |= fs->win[bc % SS(fs)] << 8; + 3185 .loc 1 1022 7 discriminator 1 view .LVU1022 + 3186 005a 0028 cmp r0, #0 + 3187 005c 45D1 bne .L253 +1023:Middlewares/Third_Party/FatFs/src/ff.c **** val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF); + 3188 .loc 1 1023 4 is_stmt 1 view .LVU1023 +1023:Middlewares/Third_Party/FatFs/src/ff.c **** val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF); + 3189 .loc 1 1023 23 is_stmt 0 view .LVU1024 + 3190 005e AB89 ldrh r3, [r5, #12] +1023:Middlewares/Third_Party/FatFs/src/ff.c **** val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF); + 3191 .loc 1 1023 21 view .LVU1025 + 3192 0060 B7FBF3F2 udiv r2, r7, r3 + 3193 0064 03FB1277 mls r7, r3, r2, r7 + 3194 .LVL356: +1023:Middlewares/Third_Party/FatFs/src/ff.c **** val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF); + 3195 .loc 1 1023 17 view .LVU1026 + 3196 0068 2F44 add r7, r7, r5 + 3197 006a 97F83430 ldrb r3, [r7, #52] @ zero_extendqisi2 +1023:Middlewares/Third_Party/FatFs/src/ff.c **** val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF); + 3198 .loc 1 1023 7 view .LVU1027 + 3199 006e 46EA0320 orr r0, r6, r3, lsl #8 + 3200 .LVL357: +1024:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3201 .loc 1 1024 4 is_stmt 1 view .LVU1028 +1024:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3202 .loc 1 1024 33 is_stmt 0 view .LVU1029 + 3203 0072 14F0010F tst r4, #1 + 3204 0076 01D0 beq .L248 +1024:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3205 .loc 1 1024 33 discriminator 1 view .LVU1030 + 3206 0078 0009 lsrs r0, r0, #4 + 3207 .LVL358: +1024:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3208 .loc 1 1024 33 discriminator 1 view .LVU1031 + 3209 007a 31E0 b .L244 + 3210 .LVL359: + 3211 .L248: +1024:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3212 .loc 1 1024 33 discriminator 2 view .LVU1032 + 3213 007c C0F30B00 ubfx r0, r0, #0, #12 + 3214 .LVL360: +1024:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3215 .loc 1 1024 33 discriminator 2 view .LVU1033 + 3216 0080 2EE0 b .L244 + 3217 .LVL361: + 3218 .L246: +1028:Middlewares/Third_Party/FatFs/src/ff.c **** val = ld_word(fs->win + clst * 2 % SS(fs)); + 3219 .loc 1 1028 4 is_stmt 1 view .LVU1034 +1028:Middlewares/Third_Party/FatFs/src/ff.c **** val = ld_word(fs->win + clst * 2 % SS(fs)); + 3220 .loc 1 1028 26 is_stmt 0 view .LVU1035 + 3221 0082 696A ldr r1, [r5, #36] + 3222 .LVL362: +1028:Middlewares/Third_Party/FatFs/src/ff.c **** val = ld_word(fs->win + clst * 2 % SS(fs)); + 3223 .loc 1 1028 47 view .LVU1036 + 3224 0084 AB89 ldrh r3, [r5, #12] + ARM GAS /tmp/cc2SVLkL.s page 174 + + +1028:Middlewares/Third_Party/FatFs/src/ff.c **** val = ld_word(fs->win + clst * 2 % SS(fs)); + 3225 .loc 1 1028 54 view .LVU1037 + 3226 0086 5B08 lsrs r3, r3, #1 +1028:Middlewares/Third_Party/FatFs/src/ff.c **** val = ld_word(fs->win + clst * 2 % SS(fs)); + 3227 .loc 1 1028 44 view .LVU1038 + 3228 0088 B4FBF3F3 udiv r3, r4, r3 +1028:Middlewares/Third_Party/FatFs/src/ff.c **** val = ld_word(fs->win + clst * 2 % SS(fs)); + 3229 .loc 1 1028 8 view .LVU1039 + 3230 008c 1944 add r1, r1, r3 + 3231 008e 2846 mov r0, r5 + 3232 .LVL363: +1028:Middlewares/Third_Party/FatFs/src/ff.c **** val = ld_word(fs->win + clst * 2 % SS(fs)); + 3233 .loc 1 1028 8 view .LVU1040 + 3234 0090 FFF7FEFF bl move_window + 3235 .LVL364: +1028:Middlewares/Third_Party/FatFs/src/ff.c **** val = ld_word(fs->win + clst * 2 % SS(fs)); + 3236 .loc 1 1028 7 discriminator 1 view .LVU1041 + 3237 0094 60BB cbnz r0, .L254 +1029:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3238 .loc 1 1029 4 is_stmt 1 view .LVU1042 +1029:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3239 .loc 1 1029 18 is_stmt 0 view .LVU1043 + 3240 0096 05F13400 add r0, r5, #52 +1029:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3241 .loc 1 1029 33 view .LVU1044 + 3242 009a 6400 lsls r4, r4, #1 + 3243 .LVL365: +1029:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3244 .loc 1 1029 39 view .LVU1045 + 3245 009c AB89 ldrh r3, [r5, #12] +1029:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3246 .loc 1 1029 37 view .LVU1046 + 3247 009e B4FBF3F2 udiv r2, r4, r3 + 3248 00a2 03FB1244 mls r4, r3, r2, r4 +1029:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3249 .loc 1 1029 10 view .LVU1047 + 3250 00a6 2044 add r0, r0, r4 + 3251 00a8 FFF7FEFF bl ld_word + 3252 .LVL366: +1030:Middlewares/Third_Party/FatFs/src/ff.c **** + 3253 .loc 1 1030 4 is_stmt 1 view .LVU1048 + 3254 00ac 18E0 b .L244 + 3255 .LVL367: + 3256 .L247: +1033:Middlewares/Third_Party/FatFs/src/ff.c **** val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF; + 3257 .loc 1 1033 4 view .LVU1049 +1033:Middlewares/Third_Party/FatFs/src/ff.c **** val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF; + 3258 .loc 1 1033 26 is_stmt 0 view .LVU1050 + 3259 00ae 696A ldr r1, [r5, #36] + 3260 .LVL368: +1033:Middlewares/Third_Party/FatFs/src/ff.c **** val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF; + 3261 .loc 1 1033 47 view .LVU1051 + 3262 00b0 AB89 ldrh r3, [r5, #12] +1033:Middlewares/Third_Party/FatFs/src/ff.c **** val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF; + 3263 .loc 1 1033 54 view .LVU1052 + 3264 00b2 9B08 lsrs r3, r3, #2 +1033:Middlewares/Third_Party/FatFs/src/ff.c **** val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF; + ARM GAS /tmp/cc2SVLkL.s page 175 + + + 3265 .loc 1 1033 44 view .LVU1053 + 3266 00b4 B4FBF3F3 udiv r3, r4, r3 +1033:Middlewares/Third_Party/FatFs/src/ff.c **** val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF; + 3267 .loc 1 1033 8 view .LVU1054 + 3268 00b8 1944 add r1, r1, r3 + 3269 00ba 2846 mov r0, r5 + 3270 .LVL369: +1033:Middlewares/Third_Party/FatFs/src/ff.c **** val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF; + 3271 .loc 1 1033 8 view .LVU1055 + 3272 00bc FFF7FEFF bl move_window + 3273 .LVL370: +1033:Middlewares/Third_Party/FatFs/src/ff.c **** val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF; + 3274 .loc 1 1033 7 discriminator 1 view .LVU1056 + 3275 00c0 C8B9 cbnz r0, .L255 +1034:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3276 .loc 1 1034 4 is_stmt 1 view .LVU1057 +1034:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3277 .loc 1 1034 19 is_stmt 0 view .LVU1058 + 3278 00c2 05F13400 add r0, r5, #52 +1034:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3279 .loc 1 1034 34 view .LVU1059 + 3280 00c6 A400 lsls r4, r4, #2 + 3281 .LVL371: +1034:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3282 .loc 1 1034 40 view .LVU1060 + 3283 00c8 AB89 ldrh r3, [r5, #12] +1034:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3284 .loc 1 1034 38 view .LVU1061 + 3285 00ca B4FBF3F2 udiv r2, r4, r3 + 3286 00ce 03FB1244 mls r4, r3, r2, r4 +1034:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3287 .loc 1 1034 10 view .LVU1062 + 3288 00d2 2044 add r0, r0, r4 + 3289 00d4 FFF7FEFF bl ld_dword + 3290 .LVL372: +1034:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 3291 .loc 1 1034 8 discriminator 1 view .LVU1063 + 3292 00d8 20F07040 bic r0, r0, #-268435456 + 3293 .LVL373: +1035:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 3294 .loc 1 1035 4 is_stmt 1 view .LVU1064 + 3295 00dc 00E0 b .L244 + 3296 .LVL374: + 3297 .L249: +1012:Middlewares/Third_Party/FatFs/src/ff.c **** + 3298 .loc 1 1012 7 is_stmt 0 view .LVU1065 + 3299 00de 0120 movs r0, #1 + 3300 .LVL375: + 3301 .L244: +1070:Middlewares/Third_Party/FatFs/src/ff.c **** + 3302 .loc 1 1070 1 view .LVU1066 + 3303 00e0 F8BD pop {r3, r4, r5, r6, r7, pc} + 3304 .LVL376: + 3305 .L250: +1012:Middlewares/Third_Party/FatFs/src/ff.c **** + 3306 .loc 1 1012 7 view .LVU1067 + 3307 00e2 0120 movs r0, #1 + ARM GAS /tmp/cc2SVLkL.s page 176 + + + 3308 .LVL377: +1012:Middlewares/Third_Party/FatFs/src/ff.c **** + 3309 .loc 1 1012 7 view .LVU1068 + 3310 00e4 FCE7 b .L244 + 3311 .LVL378: + 3312 .L251: +1017:Middlewares/Third_Party/FatFs/src/ff.c **** case FS_FAT12 : + 3313 .loc 1 1017 3 view .LVU1069 + 3314 00e6 0120 movs r0, #1 + 3315 .LVL379: +1017:Middlewares/Third_Party/FatFs/src/ff.c **** case FS_FAT12 : + 3316 .loc 1 1017 3 view .LVU1070 + 3317 00e8 FAE7 b .L244 + 3318 .LVL380: + 3319 .L253: +1015:Middlewares/Third_Party/FatFs/src/ff.c **** + 3320 .loc 1 1015 7 view .LVU1071 + 3321 00ea 4FF0FF30 mov r0, #-1 + 3322 00ee F7E7 b .L244 + 3323 .LVL381: + 3324 .L254: +1015:Middlewares/Third_Party/FatFs/src/ff.c **** + 3325 .loc 1 1015 7 view .LVU1072 + 3326 00f0 4FF0FF30 mov r0, #-1 + 3327 00f4 F4E7 b .L244 + 3328 .L255: +1015:Middlewares/Third_Party/FatFs/src/ff.c **** + 3329 .loc 1 1015 7 view .LVU1073 + 3330 00f6 4FF0FF30 mov r0, #-1 +1069:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3331 .loc 1 1069 2 is_stmt 1 view .LVU1074 +1069:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3332 .loc 1 1069 9 is_stmt 0 view .LVU1075 + 3333 00fa F1E7 b .L244 + 3334 .cfi_endproc + 3335 .LFE1200: + 3337 .section .text.dir_sdi,"ax",%progbits + 3338 .align 1 + 3339 .syntax unified + 3340 .thumb + 3341 .thumb_func + 3343 dir_sdi: + 3344 .LVL382: + 3345 .LFB1205: +1474:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD csz, clst; + 3346 .loc 1 1474 1 is_stmt 1 view -0 + 3347 .cfi_startproc + 3348 @ args = 0, pretend = 0, frame = 0 + 3349 @ frame_needed = 0, uses_anonymous_args = 0 +1474:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD csz, clst; + 3350 .loc 1 1474 1 is_stmt 0 view .LVU1077 + 3351 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 3352 .LCFI24: + 3353 .cfi_def_cfa_offset 24 + 3354 .cfi_offset 4, -24 + 3355 .cfi_offset 5, -20 + 3356 .cfi_offset 6, -16 + ARM GAS /tmp/cc2SVLkL.s page 177 + + + 3357 .cfi_offset 7, -12 + 3358 .cfi_offset 8, -8 + 3359 .cfi_offset 14, -4 +1475:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = dp->obj.fs; + 3360 .loc 1 1475 2 is_stmt 1 view .LVU1078 +1476:Middlewares/Third_Party/FatFs/src/ff.c **** + 3361 .loc 1 1476 2 view .LVU1079 +1476:Middlewares/Third_Party/FatFs/src/ff.c **** + 3362 .loc 1 1476 9 is_stmt 0 view .LVU1080 + 3363 0004 D0F80080 ldr r8, [r0] + 3364 .LVL383: +1479:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_INT_ERR; + 3365 .loc 1 1479 2 is_stmt 1 view .LVU1081 +1479:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_INT_ERR; + 3366 .loc 1 1479 5 is_stmt 0 view .LVU1082 + 3367 0008 B1F5001F cmp r1, #2097152 + 3368 000c 49D2 bcs .L265 + 3369 000e 0746 mov r7, r0 + 3370 0010 0E46 mov r6, r1 +1479:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_INT_ERR; + 3371 .loc 1 1479 84 discriminator 1 view .LVU1083 + 3372 0012 11F01F0F tst r1, #31 + 3373 0016 47D1 bne .L266 +1482:Middlewares/Third_Party/FatFs/src/ff.c **** clst = dp->obj.sclust; /* Table start cluster (0:root) */ + 3374 .loc 1 1482 2 is_stmt 1 view .LVU1084 +1482:Middlewares/Third_Party/FatFs/src/ff.c **** clst = dp->obj.sclust; /* Table start cluster (0:root) */ + 3375 .loc 1 1482 11 is_stmt 0 view .LVU1085 + 3376 0018 4161 str r1, [r0, #20] +1483:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0 && fs->fs_type >= FS_FAT32) { /* Replace cluster# 0 with root cluster# */ + 3377 .loc 1 1483 2 is_stmt 1 view .LVU1086 +1483:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0 && fs->fs_type >= FS_FAT32) { /* Replace cluster# 0 with root cluster# */ + 3378 .loc 1 1483 7 is_stmt 0 view .LVU1087 + 3379 001a 8468 ldr r4, [r0, #8] + 3380 .LVL384: +1484:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fs->dirbase; + 3381 .loc 1 1484 2 is_stmt 1 view .LVU1088 +1484:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fs->dirbase; + 3382 .loc 1 1484 5 is_stmt 0 view .LVU1089 + 3383 001c 1CBB cbnz r4, .L260 +1484:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fs->dirbase; + 3384 .loc 1 1484 21 discriminator 1 view .LVU1090 + 3385 001e 98F80030 ldrb r3, [r8] @ zero_extendqisi2 +1484:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fs->dirbase; + 3386 .loc 1 1484 16 discriminator 1 view .LVU1091 + 3387 0022 022B cmp r3, #2 + 3388 0024 01D9 bls .L261 +1485:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_EXFAT) dp->obj.stat = 0; /* exFAT: Root dir has an FAT chain */ + 3389 .loc 1 1485 3 is_stmt 1 view .LVU1092 +1485:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_EXFAT) dp->obj.stat = 0; /* exFAT: Root dir has an FAT chain */ + 3390 .loc 1 1485 8 is_stmt 0 view .LVU1093 + 3391 0026 D8F82840 ldr r4, [r8, #40] + 3392 .LVL385: +1486:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3393 .loc 1 1486 3 is_stmt 1 view .LVU1094 + 3394 .L261: +1489:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs / SZDIRE >= fs->n_rootdir) return FR_INT_ERR; /* Is index out of range? */ + 3395 .loc 1 1489 2 view .LVU1095 + ARM GAS /tmp/cc2SVLkL.s page 178 + + +1489:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs / SZDIRE >= fs->n_rootdir) return FR_INT_ERR; /* Is index out of range? */ + 3396 .loc 1 1489 5 is_stmt 0 view .LVU1096 + 3397 002a E4B9 cbnz r4, .L260 +1490:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect = fs->dirbase; + 3398 .loc 1 1490 3 is_stmt 1 view .LVU1097 +1490:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect = fs->dirbase; + 3399 .loc 1 1490 25 is_stmt 0 view .LVU1098 + 3400 002c B8F80830 ldrh r3, [r8, #8] +1490:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect = fs->dirbase; + 3401 .loc 1 1490 6 view .LVU1099 + 3402 0030 B3EB561F cmp r3, r6, lsr #5 + 3403 0034 3AD9 bls .L267 +1491:Middlewares/Third_Party/FatFs/src/ff.c **** + 3404 .loc 1 1491 3 is_stmt 1 view .LVU1100 +1491:Middlewares/Third_Party/FatFs/src/ff.c **** + 3405 .loc 1 1491 16 is_stmt 0 view .LVU1101 + 3406 0036 D8F82830 ldr r3, [r8, #40] +1491:Middlewares/Third_Party/FatFs/src/ff.c **** + 3407 .loc 1 1491 12 view .LVU1102 + 3408 003a FB61 str r3, [r7, #28] + 3409 .LVL386: + 3410 .L262: +1503:Middlewares/Third_Party/FatFs/src/ff.c **** if (!dp->sect) return FR_INT_ERR; + 3411 .loc 1 1503 2 is_stmt 1 view .LVU1103 +1503:Middlewares/Third_Party/FatFs/src/ff.c **** if (!dp->sect) return FR_INT_ERR; + 3412 .loc 1 1503 12 is_stmt 0 view .LVU1104 + 3413 003c BC61 str r4, [r7, #24] +1504:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect += ofs / SS(fs); /* Sector# of the directory entry */ + 3414 .loc 1 1504 2 is_stmt 1 view .LVU1105 +1504:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect += ofs / SS(fs); /* Sector# of the directory entry */ + 3415 .loc 1 1504 9 is_stmt 0 view .LVU1106 + 3416 003e FB69 ldr r3, [r7, #28] +1504:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect += ofs / SS(fs); /* Sector# of the directory entry */ + 3417 .loc 1 1504 5 view .LVU1107 + 3418 0040 E3B3 cbz r3, .L271 +1505:Middlewares/Third_Party/FatFs/src/ff.c **** dp->dir = fs->win + (ofs % SS(fs)); /* Pointer to the entry in the win[] */ + 3419 .loc 1 1505 2 is_stmt 1 view .LVU1108 +1505:Middlewares/Third_Party/FatFs/src/ff.c **** dp->dir = fs->win + (ofs % SS(fs)); /* Pointer to the entry in the win[] */ + 3420 .loc 1 1505 20 is_stmt 0 view .LVU1109 + 3421 0042 B8F80C20 ldrh r2, [r8, #12] +1505:Middlewares/Third_Party/FatFs/src/ff.c **** dp->dir = fs->win + (ofs % SS(fs)); /* Pointer to the entry in the win[] */ + 3422 .loc 1 1505 18 view .LVU1110 + 3423 0046 B6FBF2F2 udiv r2, r6, r2 +1505:Middlewares/Third_Party/FatFs/src/ff.c **** dp->dir = fs->win + (ofs % SS(fs)); /* Pointer to the entry in the win[] */ + 3424 .loc 1 1505 11 view .LVU1111 + 3425 004a 1344 add r3, r3, r2 + 3426 004c FB61 str r3, [r7, #28] +1506:Middlewares/Third_Party/FatFs/src/ff.c **** + 3427 .loc 1 1506 2 is_stmt 1 view .LVU1112 +1506:Middlewares/Third_Party/FatFs/src/ff.c **** + 3428 .loc 1 1506 12 is_stmt 0 view .LVU1113 + 3429 004e 08F13403 add r3, r8, #52 +1506:Middlewares/Third_Party/FatFs/src/ff.c **** + 3430 .loc 1 1506 29 view .LVU1114 + 3431 0052 B8F80C20 ldrh r2, [r8, #12] +1506:Middlewares/Third_Party/FatFs/src/ff.c **** + 3432 .loc 1 1506 27 view .LVU1115 + ARM GAS /tmp/cc2SVLkL.s page 179 + + + 3433 0056 B6FBF2F1 udiv r1, r6, r2 + 3434 005a 02FB1161 mls r1, r2, r1, r6 +1506:Middlewares/Third_Party/FatFs/src/ff.c **** + 3435 .loc 1 1506 20 view .LVU1116 + 3436 005e 0B44 add r3, r3, r1 +1506:Middlewares/Third_Party/FatFs/src/ff.c **** + 3437 .loc 1 1506 10 view .LVU1117 + 3438 0060 3B62 str r3, [r7, #32] +1508:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3439 .loc 1 1508 2 is_stmt 1 view .LVU1118 +1508:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3440 .loc 1 1508 9 is_stmt 0 view .LVU1119 + 3441 0062 0020 movs r0, #0 + 3442 0064 1EE0 b .L259 + 3443 .LVL387: + 3444 .L260: +1494:Middlewares/Third_Party/FatFs/src/ff.c **** while (ofs >= csz) { /* Follow cluster chain */ + 3445 .loc 1 1494 3 is_stmt 1 view .LVU1120 +1494:Middlewares/Third_Party/FatFs/src/ff.c **** while (ofs >= csz) { /* Follow cluster chain */ + 3446 .loc 1 1494 18 is_stmt 0 view .LVU1121 + 3447 0066 B8F80A50 ldrh r5, [r8, #10] +1494:Middlewares/Third_Party/FatFs/src/ff.c **** while (ofs >= csz) { /* Follow cluster chain */ + 3448 .loc 1 1494 28 view .LVU1122 + 3449 006a B8F80C30 ldrh r3, [r8, #12] +1494:Middlewares/Third_Party/FatFs/src/ff.c **** while (ofs >= csz) { /* Follow cluster chain */ + 3450 .loc 1 1494 7 view .LVU1123 + 3451 006e 03FB05F5 mul r5, r3, r5 + 3452 .LVL388: +1495:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&dp->obj, clst); /* Get next cluster */ + 3453 .loc 1 1495 3 is_stmt 1 view .LVU1124 + 3454 .L263: +1495:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&dp->obj, clst); /* Get next cluster */ + 3455 .loc 1 1495 14 view .LVU1125 + 3456 0072 AE42 cmp r6, r5 + 3457 0074 0FD3 bcc .L273 +1496:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + 3458 .loc 1 1496 4 view .LVU1126 +1496:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + 3459 .loc 1 1496 11 is_stmt 0 view .LVU1127 + 3460 0076 2146 mov r1, r4 + 3461 0078 3846 mov r0, r7 + 3462 007a FFF7FEFF bl get_fat + 3463 .LVL389: + 3464 007e 0446 mov r4, r0 + 3465 .LVL390: +1497:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Reached to end of table or internal + 3466 .loc 1 1497 4 is_stmt 1 view .LVU1128 +1497:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Reached to end of table or internal + 3467 .loc 1 1497 7 is_stmt 0 view .LVU1129 + 3468 0080 B0F1FF3F cmp r0, #-1 + 3469 0084 14D0 beq .L268 +1498:Middlewares/Third_Party/FatFs/src/ff.c **** ofs -= csz; + 3470 .loc 1 1498 4 is_stmt 1 view .LVU1130 +1498:Middlewares/Third_Party/FatFs/src/ff.c **** ofs -= csz; + 3471 .loc 1 1498 7 is_stmt 0 view .LVU1131 + 3472 0086 0128 cmp r0, #1 + 3473 0088 14D9 bls .L269 + ARM GAS /tmp/cc2SVLkL.s page 180 + + +1498:Middlewares/Third_Party/FatFs/src/ff.c **** ofs -= csz; + 3474 .loc 1 1498 30 discriminator 2 view .LVU1132 + 3475 008a D8F81830 ldr r3, [r8, #24] +1498:Middlewares/Third_Party/FatFs/src/ff.c **** ofs -= csz; + 3476 .loc 1 1498 17 discriminator 2 view .LVU1133 + 3477 008e 8342 cmp r3, r0 + 3478 0090 12D9 bls .L270 +1499:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3479 .loc 1 1499 4 is_stmt 1 view .LVU1134 +1499:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3480 .loc 1 1499 8 is_stmt 0 view .LVU1135 + 3481 0092 761B subs r6, r6, r5 + 3482 .LVL391: +1499:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3483 .loc 1 1499 8 view .LVU1136 + 3484 0094 EDE7 b .L263 + 3485 .LVL392: + 3486 .L273: +1501:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3487 .loc 1 1501 3 is_stmt 1 view .LVU1137 +1501:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3488 .loc 1 1501 14 is_stmt 0 view .LVU1138 + 3489 0096 2146 mov r1, r4 + 3490 0098 4046 mov r0, r8 + 3491 009a FFF7FEFF bl clust2sect + 3492 .LVL393: +1501:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3493 .loc 1 1501 12 discriminator 1 view .LVU1139 + 3494 009e F861 str r0, [r7, #28] + 3495 00a0 CCE7 b .L262 + 3496 .LVL394: + 3497 .L265: +1480:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3498 .loc 1 1480 10 view .LVU1140 + 3499 00a2 0220 movs r0, #2 + 3500 .LVL395: + 3501 .L259: +1509:Middlewares/Third_Party/FatFs/src/ff.c **** + 3502 .loc 1 1509 1 view .LVU1141 + 3503 00a4 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 3504 .LVL396: + 3505 .L266: +1480:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3506 .loc 1 1480 10 view .LVU1142 + 3507 00a8 0220 movs r0, #2 + 3508 .LVL397: +1480:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3509 .loc 1 1480 10 view .LVU1143 + 3510 00aa FBE7 b .L259 + 3511 .LVL398: + 3512 .L267: +1490:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect = fs->dirbase; + 3513 .loc 1 1490 45 discriminator 1 view .LVU1144 + 3514 00ac 0220 movs r0, #2 + 3515 .LVL399: +1490:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect = fs->dirbase; + 3516 .loc 1 1490 45 discriminator 1 view .LVU1145 + ARM GAS /tmp/cc2SVLkL.s page 181 + + + 3517 00ae F9E7 b .L259 + 3518 .LVL400: + 3519 .L268: +1497:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Reached to end of table or internal + 3520 .loc 1 1497 35 discriminator 1 view .LVU1146 + 3521 00b0 0120 movs r0, #1 + 3522 .LVL401: +1497:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Reached to end of table or internal + 3523 .loc 1 1497 35 discriminator 1 view .LVU1147 + 3524 00b2 F7E7 b .L259 + 3525 .LVL402: + 3526 .L269: +1498:Middlewares/Third_Party/FatFs/src/ff.c **** ofs -= csz; + 3527 .loc 1 1498 49 discriminator 3 view .LVU1148 + 3528 00b4 0220 movs r0, #2 + 3529 .LVL403: +1498:Middlewares/Third_Party/FatFs/src/ff.c **** ofs -= csz; + 3530 .loc 1 1498 49 discriminator 3 view .LVU1149 + 3531 00b6 F5E7 b .L259 + 3532 .LVL404: + 3533 .L270: +1498:Middlewares/Third_Party/FatFs/src/ff.c **** ofs -= csz; + 3534 .loc 1 1498 49 discriminator 3 view .LVU1150 + 3535 00b8 0220 movs r0, #2 + 3536 .LVL405: +1498:Middlewares/Third_Party/FatFs/src/ff.c **** ofs -= csz; + 3537 .loc 1 1498 49 discriminator 3 view .LVU1151 + 3538 00ba F3E7 b .L259 + 3539 .LVL406: + 3540 .L271: +1504:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect += ofs / SS(fs); /* Sector# of the directory entry */ + 3541 .loc 1 1504 24 discriminator 1 view .LVU1152 + 3542 00bc 0220 movs r0, #2 + 3543 00be F1E7 b .L259 + 3544 .cfi_endproc + 3545 .LFE1205: + 3547 .section .text.create_chain,"ax",%progbits + 3548 .align 1 + 3549 .syntax unified + 3550 .thumb + 3551 .thumb_func + 3553 create_chain: + 3554 .LVL407: + 3555 .LFB1203: +1355:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD cs, ncl, scl; + 3556 .loc 1 1355 1 is_stmt 1 view -0 + 3557 .cfi_startproc + 3558 @ args = 0, pretend = 0, frame = 0 + 3559 @ frame_needed = 0, uses_anonymous_args = 0 +1355:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD cs, ncl, scl; + 3560 .loc 1 1355 1 is_stmt 0 view .LVU1154 + 3561 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 3562 .LCFI25: + 3563 .cfi_def_cfa_offset 24 + 3564 .cfi_offset 4, -24 + 3565 .cfi_offset 5, -20 + 3566 .cfi_offset 6, -16 + ARM GAS /tmp/cc2SVLkL.s page 182 + + + 3567 .cfi_offset 7, -12 + 3568 .cfi_offset 8, -8 + 3569 .cfi_offset 14, -4 + 3570 0004 0546 mov r5, r0 +1356:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 3571 .loc 1 1356 2 is_stmt 1 view .LVU1155 +1357:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = obj->fs; + 3572 .loc 1 1357 2 view .LVU1156 +1358:Middlewares/Third_Party/FatFs/src/ff.c **** + 3573 .loc 1 1358 2 view .LVU1157 +1358:Middlewares/Third_Party/FatFs/src/ff.c **** + 3574 .loc 1 1358 9 is_stmt 0 view .LVU1158 + 3575 0006 0668 ldr r6, [r0] + 3576 .LVL408: +1361:Middlewares/Third_Party/FatFs/src/ff.c **** scl = fs->last_clst; /* Get suggested cluster to start from */ + 3577 .loc 1 1361 2 is_stmt 1 view .LVU1159 +1361:Middlewares/Third_Party/FatFs/src/ff.c **** scl = fs->last_clst; /* Get suggested cluster to start from */ + 3578 .loc 1 1361 5 is_stmt 0 view .LVU1160 + 3579 0008 0F46 mov r7, r1 + 3580 000a 51B9 cbnz r1, .L275 +1362:Middlewares/Third_Party/FatFs/src/ff.c **** if (scl == 0 || scl >= fs->n_fatent) scl = 1; + 3581 .loc 1 1362 3 is_stmt 1 view .LVU1161 +1362:Middlewares/Third_Party/FatFs/src/ff.c **** if (scl == 0 || scl >= fs->n_fatent) scl = 1; + 3582 .loc 1 1362 7 is_stmt 0 view .LVU1162 + 3583 000c D6F81080 ldr r8, [r6, #16] + 3584 .LVL409: +1363:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3585 .loc 1 1363 3 is_stmt 1 view .LVU1163 +1363:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3586 .loc 1 1363 6 is_stmt 0 view .LVU1164 + 3587 0010 B8F1000F cmp r8, #0 + 3588 0014 12D0 beq .L284 +1363:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3589 .loc 1 1363 28 discriminator 2 view .LVU1165 + 3590 0016 B369 ldr r3, [r6, #24] +1363:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3591 .loc 1 1363 16 discriminator 2 view .LVU1166 + 3592 0018 4345 cmp r3, r8 + 3593 001a 11D8 bhi .L276 +1363:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3594 .loc 1 1363 44 discriminator 3 view .LVU1167 + 3595 001c 4FF00108 mov r8, #1 + 3596 .LVL410: +1363:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3597 .loc 1 1363 44 discriminator 3 view .LVU1168 + 3598 0020 0EE0 b .L276 + 3599 .LVL411: + 3600 .L275: +1366:Middlewares/Third_Party/FatFs/src/ff.c **** if (cs < 2) return 1; /* Invalid FAT value */ + 3601 .loc 1 1366 3 is_stmt 1 view .LVU1169 +1366:Middlewares/Third_Party/FatFs/src/ff.c **** if (cs < 2) return 1; /* Invalid FAT value */ + 3602 .loc 1 1366 8 is_stmt 0 view .LVU1170 + 3603 0022 FFF7FEFF bl get_fat + 3604 .LVL412: +1366:Middlewares/Third_Party/FatFs/src/ff.c **** if (cs < 2) return 1; /* Invalid FAT value */ + 3605 .loc 1 1366 8 view .LVU1171 + 3606 0026 0346 mov r3, r0 + ARM GAS /tmp/cc2SVLkL.s page 183 + + + 3607 .LVL413: +1367:Middlewares/Third_Party/FatFs/src/ff.c **** if (cs == 0xFFFFFFFF) return cs; /* A disk error occurred */ + 3608 .loc 1 1367 3 is_stmt 1 view .LVU1172 +1367:Middlewares/Third_Party/FatFs/src/ff.c **** if (cs == 0xFFFFFFFF) return cs; /* A disk error occurred */ + 3609 .loc 1 1367 6 is_stmt 0 view .LVU1173 + 3610 0028 0128 cmp r0, #1 + 3611 002a 4CD9 bls .L286 +1368:Middlewares/Third_Party/FatFs/src/ff.c **** if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ + 3612 .loc 1 1368 3 is_stmt 1 view .LVU1174 +1368:Middlewares/Third_Party/FatFs/src/ff.c **** if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ + 3613 .loc 1 1368 6 is_stmt 0 view .LVU1175 + 3614 002c B0F1FF3F cmp r0, #-1 + 3615 0030 4ED0 beq .L274 +1369:Middlewares/Third_Party/FatFs/src/ff.c **** scl = clst; + 3616 .loc 1 1369 3 is_stmt 1 view .LVU1176 +1369:Middlewares/Third_Party/FatFs/src/ff.c **** scl = clst; + 3617 .loc 1 1369 14 is_stmt 0 view .LVU1177 + 3618 0032 B269 ldr r2, [r6, #24] +1369:Middlewares/Third_Party/FatFs/src/ff.c **** scl = clst; + 3619 .loc 1 1369 6 view .LVU1178 + 3620 0034 8242 cmp r2, r0 + 3621 0036 4BD8 bhi .L274 +1370:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3622 .loc 1 1370 7 view .LVU1179 + 3623 0038 B846 mov r8, r7 + 3624 003a 01E0 b .L276 + 3625 .LVL414: + 3626 .L284: +1363:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3627 .loc 1 1363 44 discriminator 3 view .LVU1180 + 3628 003c 4FF00108 mov r8, #1 + 3629 .LVL415: + 3630 .L276: +1400:Middlewares/Third_Party/FatFs/src/ff.c **** for (;;) { + 3631 .loc 1 1400 3 is_stmt 1 view .LVU1181 +1400:Middlewares/Third_Party/FatFs/src/ff.c **** for (;;) { + 3632 .loc 1 1400 7 is_stmt 0 view .LVU1182 + 3633 0040 4446 mov r4, r8 + 3634 0042 0CE0 b .L280 + 3635 .LVL416: + 3636 .L278: +1407:Middlewares/Third_Party/FatFs/src/ff.c **** if (cs == 0) break; /* Found a free cluster */ + 3637 .loc 1 1407 4 is_stmt 1 view .LVU1183 +1407:Middlewares/Third_Party/FatFs/src/ff.c **** if (cs == 0) break; /* Found a free cluster */ + 3638 .loc 1 1407 9 is_stmt 0 view .LVU1184 + 3639 0044 2146 mov r1, r4 + 3640 0046 2846 mov r0, r5 + 3641 0048 FFF7FEFF bl get_fat + 3642 .LVL417: +1408:Middlewares/Third_Party/FatFs/src/ff.c **** if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* An error occurred */ + 3643 .loc 1 1408 4 is_stmt 1 view .LVU1185 +1408:Middlewares/Third_Party/FatFs/src/ff.c **** if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* An error occurred */ + 3644 .loc 1 1408 7 is_stmt 0 view .LVU1186 + 3645 004c 0346 mov r3, r0 + 3646 004e 78B1 cbz r0, .L279 +1409:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl == scl) return 0; /* No free cluster */ + 3647 .loc 1 1409 4 is_stmt 1 view .LVU1187 + ARM GAS /tmp/cc2SVLkL.s page 184 + + +1409:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl == scl) return 0; /* No free cluster */ + 3648 .loc 1 1409 7 is_stmt 0 view .LVU1188 + 3649 0050 B0F1FF3F cmp r0, #-1 + 3650 0054 18BF it ne + 3651 0056 0128 cmpne r0, #1 + 3652 0058 3AD0 beq .L274 +1410:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3653 .loc 1 1410 4 is_stmt 1 view .LVU1189 +1410:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3654 .loc 1 1410 7 is_stmt 0 view .LVU1190 + 3655 005a 4445 cmp r4, r8 + 3656 005c 37D0 beq .L291 + 3657 .LVL418: + 3658 .L280: +1401:Middlewares/Third_Party/FatFs/src/ff.c **** ncl++; /* Next cluster */ + 3659 .loc 1 1401 3 is_stmt 1 view .LVU1191 +1402:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl >= fs->n_fatent) { /* Check wrap-around */ + 3660 .loc 1 1402 4 view .LVU1192 +1402:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl >= fs->n_fatent) { /* Check wrap-around */ + 3661 .loc 1 1402 7 is_stmt 0 view .LVU1193 + 3662 005e 0134 adds r4, r4, #1 + 3663 .LVL419: +1403:Middlewares/Third_Party/FatFs/src/ff.c **** ncl = 2; + 3664 .loc 1 1403 4 is_stmt 1 view .LVU1194 +1403:Middlewares/Third_Party/FatFs/src/ff.c **** ncl = 2; + 3665 .loc 1 1403 17 is_stmt 0 view .LVU1195 + 3666 0060 B369 ldr r3, [r6, #24] +1403:Middlewares/Third_Party/FatFs/src/ff.c **** ncl = 2; + 3667 .loc 1 1403 7 view .LVU1196 + 3668 0062 A342 cmp r3, r4 + 3669 0064 EED8 bhi .L278 +1404:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl > scl) return 0; /* No free cluster */ + 3670 .loc 1 1404 5 is_stmt 1 view .LVU1197 + 3671 .LVL420: +1405:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3672 .loc 1 1405 5 view .LVU1198 +1405:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3673 .loc 1 1405 8 is_stmt 0 view .LVU1199 + 3674 0066 B8F1010F cmp r8, #1 + 3675 006a 2ED9 bls .L287 +1404:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl > scl) return 0; /* No free cluster */ + 3676 .loc 1 1404 9 view .LVU1200 + 3677 006c 0224 movs r4, #2 + 3678 006e E9E7 b .L278 + 3679 .LVL421: + 3680 .L279: +1412:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && clst != 0) { + 3681 .loc 1 1412 3 is_stmt 1 view .LVU1201 +1412:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && clst != 0) { + 3682 .loc 1 1412 9 is_stmt 0 view .LVU1202 + 3683 0070 4FF0FF32 mov r2, #-1 + 3684 0074 2146 mov r1, r4 + 3685 0076 3046 mov r0, r6 + 3686 .LVL422: +1412:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && clst != 0) { + 3687 .loc 1 1412 9 view .LVU1203 + 3688 0078 FFF7FEFF bl put_fat + ARM GAS /tmp/cc2SVLkL.s page 185 + + + 3689 .LVL423: +1413:Middlewares/Third_Party/FatFs/src/ff.c **** res = put_fat(fs, clst, ncl); /* Link it from the previous one if needed */ + 3690 .loc 1 1413 3 is_stmt 1 view .LVU1204 +1413:Middlewares/Third_Party/FatFs/src/ff.c **** res = put_fat(fs, clst, ncl); /* Link it from the previous one if needed */ + 3691 .loc 1 1413 11 is_stmt 0 view .LVU1205 + 3692 007c 0246 mov r2, r0 +1413:Middlewares/Third_Party/FatFs/src/ff.c **** res = put_fat(fs, clst, ncl); /* Link it from the previous one if needed */ + 3693 .loc 1 1413 20 view .LVU1206 + 3694 007e B0FA80F0 clz r0, r0 + 3695 .LVL424: +1413:Middlewares/Third_Party/FatFs/src/ff.c **** res = put_fat(fs, clst, ncl); /* Link it from the previous one if needed */ + 3696 .loc 1 1413 20 view .LVU1207 + 3697 0082 4009 lsrs r0, r0, #5 + 3698 0084 002F cmp r7, #0 + 3699 0086 08BF it eq + 3700 0088 0020 moveq r0, #0 +1413:Middlewares/Third_Party/FatFs/src/ff.c **** res = put_fat(fs, clst, ncl); /* Link it from the previous one if needed */ + 3701 .loc 1 1413 6 view .LVU1208 + 3702 008a 70B9 cbnz r0, .L292 + 3703 .LVL425: + 3704 .L281: +1418:Middlewares/Third_Party/FatFs/src/ff.c **** fs->last_clst = ncl; + 3705 .loc 1 1418 2 is_stmt 1 view .LVU1209 +1418:Middlewares/Third_Party/FatFs/src/ff.c **** fs->last_clst = ncl; + 3706 .loc 1 1418 5 is_stmt 0 view .LVU1210 + 3707 008c A2B9 cbnz r2, .L282 +1419:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->free_clst <= fs->n_fatent - 2) fs->free_clst--; + 3708 .loc 1 1419 3 is_stmt 1 view .LVU1211 +1419:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->free_clst <= fs->n_fatent - 2) fs->free_clst--; + 3709 .loc 1 1419 17 is_stmt 0 view .LVU1212 + 3710 008e 3461 str r4, [r6, #16] +1420:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag |= 1; + 3711 .loc 1 1420 3 is_stmt 1 view .LVU1213 +1420:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag |= 1; + 3712 .loc 1 1420 9 is_stmt 0 view .LVU1214 + 3713 0090 7269 ldr r2, [r6, #20] + 3714 .LVL426: +1420:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag |= 1; + 3715 .loc 1 1420 26 view .LVU1215 + 3716 0092 B369 ldr r3, [r6, #24] +1420:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag |= 1; + 3717 .loc 1 1420 37 view .LVU1216 + 3718 0094 023B subs r3, r3, #2 +1420:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag |= 1; + 3719 .loc 1 1420 6 view .LVU1217 + 3720 0096 9A42 cmp r2, r3 + 3721 0098 01D8 bhi .L283 +1420:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag |= 1; + 3722 .loc 1 1420 42 is_stmt 1 discriminator 1 view .LVU1218 +1420:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag |= 1; + 3723 .loc 1 1420 55 is_stmt 0 discriminator 1 view .LVU1219 + 3724 009a 013A subs r2, r2, #1 + 3725 009c 7261 str r2, [r6, #20] + 3726 .L283: +1421:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 3727 .loc 1 1421 3 is_stmt 1 view .LVU1220 +1421:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + ARM GAS /tmp/cc2SVLkL.s page 186 + + + 3728 .loc 1 1421 5 is_stmt 0 view .LVU1221 + 3729 009e 3379 ldrb r3, [r6, #4] @ zero_extendqisi2 +1421:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 3730 .loc 1 1421 16 view .LVU1222 + 3731 00a0 43F00103 orr r3, r3, #1 + 3732 00a4 3371 strb r3, [r6, #4] + 3733 00a6 2346 mov r3, r4 + 3734 00a8 12E0 b .L274 + 3735 .LVL427: + 3736 .L292: +1414:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3737 .loc 1 1414 4 is_stmt 1 view .LVU1223 +1414:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3738 .loc 1 1414 10 is_stmt 0 view .LVU1224 + 3739 00aa 2246 mov r2, r4 + 3740 .LVL428: +1414:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3741 .loc 1 1414 10 view .LVU1225 + 3742 00ac 3946 mov r1, r7 + 3743 00ae 3046 mov r0, r6 + 3744 00b0 FFF7FEFF bl put_fat + 3745 .LVL429: + 3746 00b4 0246 mov r2, r0 + 3747 .LVL430: +1414:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3748 .loc 1 1414 10 view .LVU1226 + 3749 00b6 E9E7 b .L281 + 3750 .L282: +1423:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3751 .loc 1 1423 3 is_stmt 1 view .LVU1227 +1423:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3752 .loc 1 1423 43 is_stmt 0 view .LVU1228 + 3753 00b8 012A cmp r2, #1 + 3754 00ba 01D0 beq .L293 +1423:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3755 .loc 1 1423 43 discriminator 2 view .LVU1229 + 3756 00bc 0123 movs r3, #1 + 3757 .LVL431: +1423:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3758 .loc 1 1423 43 discriminator 2 view .LVU1230 + 3759 00be 07E0 b .L274 + 3760 .LVL432: + 3761 .L293: +1423:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3762 .loc 1 1423 43 discriminator 1 view .LVU1231 + 3763 00c0 4FF0FF33 mov r3, #-1 + 3764 00c4 04E0 b .L274 + 3765 .LVL433: + 3766 .L286: +1367:Middlewares/Third_Party/FatFs/src/ff.c **** if (cs == 0xFFFFFFFF) return cs; /* A disk error occurred */ + 3767 .loc 1 1367 22 discriminator 1 view .LVU1232 + 3768 00c6 0123 movs r3, #1 + 3769 00c8 02E0 b .L274 + 3770 .LVL434: + 3771 .L287: +1405:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3772 .loc 1 1405 27 discriminator 1 view .LVU1233 + ARM GAS /tmp/cc2SVLkL.s page 187 + + + 3773 00ca 0023 movs r3, #0 + 3774 00cc 00E0 b .L274 + 3775 .LVL435: + 3776 .L291: +1410:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3777 .loc 1 1410 27 discriminator 1 view .LVU1234 + 3778 00ce 0023 movs r3, #0 + 3779 .LVL436: + 3780 .L274: +1427:Middlewares/Third_Party/FatFs/src/ff.c **** + 3781 .loc 1 1427 1 view .LVU1235 + 3782 00d0 1846 mov r0, r3 + 3783 00d2 BDE8F081 pop {r4, r5, r6, r7, r8, pc} +1427:Middlewares/Third_Party/FatFs/src/ff.c **** + 3784 .loc 1 1427 1 view .LVU1236 + 3785 .cfi_endproc + 3786 .LFE1203: + 3788 .section .text.remove_chain,"ax",%progbits + 3789 .align 1 + 3790 .syntax unified + 3791 .thumb + 3792 .thumb_func + 3794 remove_chain: + 3795 .LVL437: + 3796 .LFB1202: +1276:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res = FR_OK; + 3797 .loc 1 1276 1 is_stmt 1 view -0 + 3798 .cfi_startproc + 3799 @ args = 0, pretend = 0, frame = 0 + 3800 @ frame_needed = 0, uses_anonymous_args = 0 +1276:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res = FR_OK; + 3801 .loc 1 1276 1 is_stmt 0 view .LVU1238 + 3802 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 3803 .LCFI26: + 3804 .cfi_def_cfa_offset 24 + 3805 .cfi_offset 3, -24 + 3806 .cfi_offset 4, -20 + 3807 .cfi_offset 5, -16 + 3808 .cfi_offset 6, -12 + 3809 .cfi_offset 7, -8 + 3810 .cfi_offset 14, -4 + 3811 0002 0C46 mov r4, r1 +1277:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD nxt; + 3812 .loc 1 1277 2 is_stmt 1 view .LVU1239 + 3813 .LVL438: +1278:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = obj->fs; + 3814 .loc 1 1278 2 view .LVU1240 +1279:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT || _USE_TRIM + 3815 .loc 1 1279 2 view .LVU1241 +1279:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT || _USE_TRIM + 3816 .loc 1 1279 9 is_stmt 0 view .LVU1242 + 3817 0004 0568 ldr r5, [r0] + 3818 .LVL439: +1287:Middlewares/Third_Party/FatFs/src/ff.c **** + 3819 .loc 1 1287 2 is_stmt 1 view .LVU1243 +1287:Middlewares/Third_Party/FatFs/src/ff.c **** + 3820 .loc 1 1287 5 is_stmt 0 view .LVU1244 + ARM GAS /tmp/cc2SVLkL.s page 188 + + + 3821 0006 0129 cmp r1, #1 + 3822 0008 2ED9 bls .L299 + 3823 000a 0646 mov r6, r0 + 3824 000c 1146 mov r1, r2 + 3825 .LVL440: +1287:Middlewares/Third_Party/FatFs/src/ff.c **** + 3826 .loc 1 1287 28 discriminator 2 view .LVU1245 + 3827 000e AB69 ldr r3, [r5, #24] +1287:Middlewares/Third_Party/FatFs/src/ff.c **** + 3828 .loc 1 1287 15 discriminator 2 view .LVU1246 + 3829 0010 A342 cmp r3, r4 + 3830 0012 2BD9 bls .L300 +1290:Middlewares/Third_Party/FatFs/src/ff.c **** res = put_fat(fs, pclst, 0xFFFFFFFF); + 3831 .loc 1 1290 2 is_stmt 1 view .LVU1247 +1290:Middlewares/Third_Party/FatFs/src/ff.c **** res = put_fat(fs, pclst, 0xFFFFFFFF); + 3832 .loc 1 1290 5 is_stmt 0 view .LVU1248 + 3833 0014 4AB1 cbz r2, .L298 +1291:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; + 3834 .loc 1 1291 3 is_stmt 1 view .LVU1249 +1291:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; + 3835 .loc 1 1291 9 is_stmt 0 view .LVU1250 + 3836 0016 4FF0FF32 mov r2, #-1 + 3837 .LVL441: +1291:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; + 3838 .loc 1 1291 9 view .LVU1251 + 3839 001a 2846 mov r0, r5 + 3840 .LVL442: +1291:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; + 3841 .loc 1 1291 9 view .LVU1252 + 3842 001c FFF7FEFF bl put_fat + 3843 .LVL443: +1292:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3844 .loc 1 1292 3 is_stmt 1 view .LVU1253 +1292:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3845 .loc 1 1292 6 is_stmt 0 view .LVU1254 + 3846 0020 0746 mov r7, r0 + 3847 0022 10B1 cbz r0, .L298 + 3848 0024 23E0 b .L295 + 3849 .LVL444: + 3850 .L297: +1327:Middlewares/Third_Party/FatFs/src/ff.c **** } while (clst < fs->n_fatent); /* Repeat while not the last link */ + 3851 .loc 1 1327 3 is_stmt 1 view .LVU1255 +1328:Middlewares/Third_Party/FatFs/src/ff.c **** + 3852 .loc 1 1328 16 view .LVU1256 + 3853 0026 A242 cmp r2, r4 + 3854 0028 21D9 bls .L295 + 3855 .LVL445: + 3856 .L298: +1296:Middlewares/Third_Party/FatFs/src/ff.c **** nxt = get_fat(obj, clst); /* Get cluster status */ + 3857 .loc 1 1296 2 view .LVU1257 +1297:Middlewares/Third_Party/FatFs/src/ff.c **** if (nxt == 0) break; /* Empty cluster? */ + 3858 .loc 1 1297 3 view .LVU1258 + 3859 002a 2746 mov r7, r4 +1297:Middlewares/Third_Party/FatFs/src/ff.c **** if (nxt == 0) break; /* Empty cluster? */ + 3860 .loc 1 1297 9 is_stmt 0 view .LVU1259 + 3861 002c 2146 mov r1, r4 + 3862 002e 3046 mov r0, r6 + ARM GAS /tmp/cc2SVLkL.s page 189 + + + 3863 0030 FFF7FEFF bl get_fat + 3864 .LVL446: +1298:Middlewares/Third_Party/FatFs/src/ff.c **** if (nxt == 1) return FR_INT_ERR; /* Internal error? */ + 3865 .loc 1 1298 3 is_stmt 1 view .LVU1260 +1298:Middlewares/Third_Party/FatFs/src/ff.c **** if (nxt == 1) return FR_INT_ERR; /* Internal error? */ + 3866 .loc 1 1298 6 is_stmt 0 view .LVU1261 + 3867 0034 0446 mov r4, r0 + 3868 .LVL447: +1298:Middlewares/Third_Party/FatFs/src/ff.c **** if (nxt == 1) return FR_INT_ERR; /* Internal error? */ + 3869 .loc 1 1298 6 view .LVU1262 + 3870 0036 E0B1 cbz r0, .L301 +1299:Middlewares/Third_Party/FatFs/src/ff.c **** if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error? */ + 3871 .loc 1 1299 3 is_stmt 1 view .LVU1263 +1299:Middlewares/Third_Party/FatFs/src/ff.c **** if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error? */ + 3872 .loc 1 1299 6 is_stmt 0 view .LVU1264 + 3873 0038 0128 cmp r0, #1 + 3874 003a 1CD0 beq .L302 +1300:Middlewares/Third_Party/FatFs/src/ff.c **** if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { + 3875 .loc 1 1300 3 is_stmt 1 view .LVU1265 +1300:Middlewares/Third_Party/FatFs/src/ff.c **** if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { + 3876 .loc 1 1300 6 is_stmt 0 view .LVU1266 + 3877 003c B0F1FF3F cmp r0, #-1 + 3878 0040 1BD0 beq .L303 +1301:Middlewares/Third_Party/FatFs/src/ff.c **** res = put_fat(fs, clst, 0); /* Mark the cluster 'free' on the FAT */ + 3879 .loc 1 1301 3 is_stmt 1 view .LVU1267 +1302:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; + 3880 .loc 1 1302 4 view .LVU1268 +1302:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; + 3881 .loc 1 1302 10 is_stmt 0 view .LVU1269 + 3882 0042 0022 movs r2, #0 + 3883 0044 3946 mov r1, r7 + 3884 0046 2846 mov r0, r5 + 3885 .LVL448: +1302:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; + 3886 .loc 1 1302 10 view .LVU1270 + 3887 0048 FFF7FEFF bl put_fat + 3888 .LVL449: +1303:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3889 .loc 1 1303 4 is_stmt 1 view .LVU1271 +1303:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3890 .loc 1 1303 7 is_stmt 0 view .LVU1272 + 3891 004c 0746 mov r7, r0 + 3892 .LVL450: +1303:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3893 .loc 1 1303 7 view .LVU1273 + 3894 004e 70B9 cbnz r0, .L295 +1305:Middlewares/Third_Party/FatFs/src/ff.c **** fs->free_clst++; + 3895 .loc 1 1305 3 is_stmt 1 view .LVU1274 +1305:Middlewares/Third_Party/FatFs/src/ff.c **** fs->free_clst++; + 3896 .loc 1 1305 9 is_stmt 0 view .LVU1275 + 3897 0050 6B69 ldr r3, [r5, #20] +1305:Middlewares/Third_Party/FatFs/src/ff.c **** fs->free_clst++; + 3898 .loc 1 1305 25 view .LVU1276 + 3899 0052 AA69 ldr r2, [r5, #24] +1305:Middlewares/Third_Party/FatFs/src/ff.c **** fs->free_clst++; + 3900 .loc 1 1305 36 view .LVU1277 + 3901 0054 911E subs r1, r2, #2 + ARM GAS /tmp/cc2SVLkL.s page 190 + + +1305:Middlewares/Third_Party/FatFs/src/ff.c **** fs->free_clst++; + 3902 .loc 1 1305 6 view .LVU1278 + 3903 0056 8B42 cmp r3, r1 + 3904 0058 E5D2 bcs .L297 +1306:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag |= 1; + 3905 .loc 1 1306 4 is_stmt 1 view .LVU1279 +1306:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag |= 1; + 3906 .loc 1 1306 17 is_stmt 0 view .LVU1280 + 3907 005a 0133 adds r3, r3, #1 + 3908 005c 6B61 str r3, [r5, #20] +1307:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3909 .loc 1 1307 4 is_stmt 1 view .LVU1281 +1307:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3910 .loc 1 1307 6 is_stmt 0 view .LVU1282 + 3911 005e 2B79 ldrb r3, [r5, #4] @ zero_extendqisi2 +1307:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3912 .loc 1 1307 17 view .LVU1283 + 3913 0060 43F00103 orr r3, r3, #1 + 3914 0064 2B71 strb r3, [r5, #4] + 3915 0066 DEE7 b .L297 + 3916 .LVL451: + 3917 .L299: +1287:Middlewares/Third_Party/FatFs/src/ff.c **** + 3918 .loc 1 1287 47 discriminator 3 view .LVU1284 + 3919 0068 0227 movs r7, #2 + 3920 006a 00E0 b .L295 + 3921 .LVL452: + 3922 .L300: +1287:Middlewares/Third_Party/FatFs/src/ff.c **** + 3923 .loc 1 1287 47 discriminator 3 view .LVU1285 + 3924 006c 0227 movs r7, #2 + 3925 .LVL453: + 3926 .L295: +1342:Middlewares/Third_Party/FatFs/src/ff.c **** + 3927 .loc 1 1342 1 view .LVU1286 + 3928 006e 3846 mov r0, r7 + 3929 0070 F8BD pop {r3, r4, r5, r6, r7, pc} + 3930 .LVL454: + 3931 .L301: +1341:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3932 .loc 1 1341 9 view .LVU1287 + 3933 0072 0027 movs r7, #0 + 3934 .LVL455: +1341:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3935 .loc 1 1341 9 view .LVU1288 + 3936 0074 FBE7 b .L295 + 3937 .LVL456: + 3938 .L302: +1299:Middlewares/Third_Party/FatFs/src/ff.c **** if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error? */ + 3939 .loc 1 1299 24 discriminator 1 view .LVU1289 + 3940 0076 0227 movs r7, #2 + 3941 .LVL457: +1299:Middlewares/Third_Party/FatFs/src/ff.c **** if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error? */ + 3942 .loc 1 1299 24 discriminator 1 view .LVU1290 + 3943 0078 F9E7 b .L295 + 3944 .LVL458: + 3945 .L303: + ARM GAS /tmp/cc2SVLkL.s page 191 + + +1300:Middlewares/Third_Party/FatFs/src/ff.c **** if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { + 3946 .loc 1 1300 33 discriminator 1 view .LVU1291 + 3947 007a 0127 movs r7, #1 + 3948 .LVL459: +1300:Middlewares/Third_Party/FatFs/src/ff.c **** if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { + 3949 .loc 1 1300 33 discriminator 1 view .LVU1292 + 3950 007c F7E7 b .L295 + 3951 .cfi_endproc + 3952 .LFE1202: + 3954 .section .text.dir_remove,"ax",%progbits + 3955 .align 1 + 3956 .syntax unified + 3957 .thumb + 3958 .thumb_func + 3960 dir_remove: + 3961 .LVL460: + 3962 .LFB1213: +2399:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 3963 .loc 1 2399 1 is_stmt 1 view -0 + 3964 .cfi_startproc + 3965 @ args = 0, pretend = 0, frame = 0 + 3966 @ frame_needed = 0, uses_anonymous_args = 0 +2399:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 3967 .loc 1 2399 1 is_stmt 0 view .LVU1294 + 3968 0000 38B5 push {r3, r4, r5, lr} + 3969 .LCFI27: + 3970 .cfi_def_cfa_offset 16 + 3971 .cfi_offset 3, -16 + 3972 .cfi_offset 4, -12 + 3973 .cfi_offset 5, -8 + 3974 .cfi_offset 14, -4 + 3975 0002 0446 mov r4, r0 +2400:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = dp->obj.fs; + 3976 .loc 1 2400 2 is_stmt 1 view .LVU1295 +2401:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 /* LFN configuration */ + 3977 .loc 1 2401 2 view .LVU1296 +2401:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 /* LFN configuration */ + 3978 .loc 1 2401 9 is_stmt 0 view .LVU1297 + 3979 0004 0568 ldr r5, [r0] + 3980 .LVL461: +2424:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 3981 .loc 1 2424 2 is_stmt 1 view .LVU1298 +2424:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 3982 .loc 1 2424 8 is_stmt 0 view .LVU1299 + 3983 0006 C169 ldr r1, [r0, #28] + 3984 0008 2846 mov r0, r5 + 3985 .LVL462: +2424:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 3986 .loc 1 2424 8 view .LVU1300 + 3987 000a FFF7FEFF bl move_window + 3988 .LVL463: +2425:Middlewares/Third_Party/FatFs/src/ff.c **** dp->dir[DIR_Name] = DDEM; + 3989 .loc 1 2425 2 is_stmt 1 view .LVU1301 +2425:Middlewares/Third_Party/FatFs/src/ff.c **** dp->dir[DIR_Name] = DDEM; + 3990 .loc 1 2425 5 is_stmt 0 view .LVU1302 + 3991 000e 20B9 cbnz r0, .L306 +2426:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + ARM GAS /tmp/cc2SVLkL.s page 192 + + + 3992 .loc 1 2426 3 is_stmt 1 view .LVU1303 +2426:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 3993 .loc 1 2426 5 is_stmt 0 view .LVU1304 + 3994 0010 236A ldr r3, [r4, #32] +2426:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 3995 .loc 1 2426 21 view .LVU1305 + 3996 0012 E522 movs r2, #229 + 3997 0014 1A70 strb r2, [r3] +2427:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3998 .loc 1 2427 3 is_stmt 1 view .LVU1306 +2427:Middlewares/Third_Party/FatFs/src/ff.c **** } + 3999 .loc 1 2427 13 is_stmt 0 view .LVU1307 + 4000 0016 0123 movs r3, #1 + 4001 0018 EB70 strb r3, [r5, #3] + 4002 .L306: +2431:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4003 .loc 1 2431 2 is_stmt 1 view .LVU1308 +2432:Middlewares/Third_Party/FatFs/src/ff.c **** + 4004 .loc 1 2432 1 is_stmt 0 view .LVU1309 + 4005 001a 38BD pop {r3, r4, r5, pc} +2432:Middlewares/Third_Party/FatFs/src/ff.c **** + 4006 .loc 1 2432 1 view .LVU1310 + 4007 .cfi_endproc + 4008 .LFE1213: + 4010 .section .text.dir_next,"ax",%progbits + 4011 .align 1 + 4012 .syntax unified + 4013 .thumb + 4014 .thumb_func + 4016 dir_next: + 4017 .LVL464: + 4018 .LFB1206: +1523:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD ofs, clst; + 4019 .loc 1 1523 1 is_stmt 1 view -0 + 4020 .cfi_startproc + 4021 @ args = 0, pretend = 0, frame = 0 + 4022 @ frame_needed = 0, uses_anonymous_args = 0 +1523:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD ofs, clst; + 4023 .loc 1 1523 1 is_stmt 0 view .LVU1312 + 4024 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr} + 4025 .LCFI28: + 4026 .cfi_def_cfa_offset 32 + 4027 .cfi_offset 3, -32 + 4028 .cfi_offset 4, -28 + 4029 .cfi_offset 5, -24 + 4030 .cfi_offset 6, -20 + 4031 .cfi_offset 7, -16 + 4032 .cfi_offset 8, -12 + 4033 .cfi_offset 9, -8 + 4034 .cfi_offset 14, -4 +1524:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = dp->obj.fs; + 4035 .loc 1 1524 2 is_stmt 1 view .LVU1313 +1525:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 4036 .loc 1 1525 2 view .LVU1314 +1525:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 4037 .loc 1 1525 9 is_stmt 0 view .LVU1315 + 4038 0004 0668 ldr r6, [r0] + ARM GAS /tmp/cc2SVLkL.s page 193 + + + 4039 .LVL465: +1527:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 4040 .loc 1 1527 2 is_stmt 1 view .LVU1316 +1530:Middlewares/Third_Party/FatFs/src/ff.c **** if (!dp->sect || ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) re + 4041 .loc 1 1530 2 view .LVU1317 +1530:Middlewares/Third_Party/FatFs/src/ff.c **** if (!dp->sect || ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) re + 4042 .loc 1 1530 10 is_stmt 0 view .LVU1318 + 4043 0006 4469 ldr r4, [r0, #20] + 4044 .LVL466: +1531:Middlewares/Third_Party/FatFs/src/ff.c **** + 4045 .loc 1 1531 2 is_stmt 1 view .LVU1319 +1531:Middlewares/Third_Party/FatFs/src/ff.c **** + 4046 .loc 1 1531 9 is_stmt 0 view .LVU1320 + 4047 0008 C369 ldr r3, [r0, #28] +1531:Middlewares/Third_Party/FatFs/src/ff.c **** + 4048 .loc 1 1531 5 view .LVU1321 + 4049 000a 002B cmp r3, #0 + 4050 000c 74D0 beq .L316 + 4051 000e 0546 mov r5, r0 + 4052 0010 0F46 mov r7, r1 + 4053 0012 2034 adds r4, r4, #32 + 4054 .LVL467: +1531:Middlewares/Third_Party/FatFs/src/ff.c **** + 4055 .loc 1 1531 16 discriminator 2 view .LVU1322 + 4056 0014 B4F5001F cmp r4, #2097152 + 4057 0018 70D2 bcs .L317 +1533:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect++; /* Next sector */ + 4058 .loc 1 1533 2 is_stmt 1 view .LVU1323 +1533:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect++; /* Next sector */ + 4059 .loc 1 1533 12 is_stmt 0 view .LVU1324 + 4060 001a B189 ldrh r1, [r6, #12] + 4061 .LVL468: +1533:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect++; /* Next sector */ + 4062 .loc 1 1533 10 view .LVU1325 + 4063 001c B4FBF1F2 udiv r2, r4, r1 + 4064 0020 01FB1242 mls r2, r1, r2, r4 +1533:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect++; /* Next sector */ + 4065 .loc 1 1533 5 view .LVU1326 + 4066 0024 3AB9 cbnz r2, .L310 +1534:Middlewares/Third_Party/FatFs/src/ff.c **** + 4067 .loc 1 1534 3 is_stmt 1 view .LVU1327 +1534:Middlewares/Third_Party/FatFs/src/ff.c **** + 4068 .loc 1 1534 11 is_stmt 0 view .LVU1328 + 4069 0026 0133 adds r3, r3, #1 + 4070 0028 C361 str r3, [r0, #28] +1536:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs / SZDIRE >= fs->n_rootdir) { /* Report EOT if it reached end of static table */ + 4071 .loc 1 1536 3 is_stmt 1 view .LVU1329 +1536:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs / SZDIRE >= fs->n_rootdir) { /* Report EOT if it reached end of static table */ + 4072 .loc 1 1536 10 is_stmt 0 view .LVU1330 + 4073 002a 8169 ldr r1, [r0, #24] +1536:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs / SZDIRE >= fs->n_rootdir) { /* Report EOT if it reached end of static table */ + 4074 .loc 1 1536 6 view .LVU1331 + 4075 002c A1B9 cbnz r1, .L311 +1537:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect = 0; return FR_NO_FILE; + 4076 .loc 1 1537 4 is_stmt 1 view .LVU1332 +1537:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect = 0; return FR_NO_FILE; + 4077 .loc 1 1537 26 is_stmt 0 view .LVU1333 + ARM GAS /tmp/cc2SVLkL.s page 194 + + + 4078 002e 3389 ldrh r3, [r6, #8] +1537:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect = 0; return FR_NO_FILE; + 4079 .loc 1 1537 7 view .LVU1334 + 4080 0030 B3EB541F cmp r3, r4, lsr #5 + 4081 0034 0CD9 bls .L326 + 4082 .LVL469: + 4083 .L310: +1574:Middlewares/Third_Party/FatFs/src/ff.c **** dp->dir = fs->win + ofs % SS(fs); /* Pointer to the entry in the win[] */ + 4084 .loc 1 1574 2 is_stmt 1 view .LVU1335 +1574:Middlewares/Third_Party/FatFs/src/ff.c **** dp->dir = fs->win + ofs % SS(fs); /* Pointer to the entry in the win[] */ + 4085 .loc 1 1574 11 is_stmt 0 view .LVU1336 + 4086 0036 6C61 str r4, [r5, #20] +1575:Middlewares/Third_Party/FatFs/src/ff.c **** + 4087 .loc 1 1575 2 is_stmt 1 view .LVU1337 +1575:Middlewares/Third_Party/FatFs/src/ff.c **** + 4088 .loc 1 1575 12 is_stmt 0 view .LVU1338 + 4089 0038 06F13403 add r3, r6, #52 +1575:Middlewares/Third_Party/FatFs/src/ff.c **** + 4090 .loc 1 1575 28 view .LVU1339 + 4091 003c B289 ldrh r2, [r6, #12] +1575:Middlewares/Third_Party/FatFs/src/ff.c **** + 4092 .loc 1 1575 26 view .LVU1340 + 4093 003e B4FBF2F1 udiv r1, r4, r2 + 4094 0042 02FB1144 mls r4, r2, r1, r4 + 4095 .LVL470: +1575:Middlewares/Third_Party/FatFs/src/ff.c **** + 4096 .loc 1 1575 20 view .LVU1341 + 4097 0046 2344 add r3, r3, r4 +1575:Middlewares/Third_Party/FatFs/src/ff.c **** + 4098 .loc 1 1575 10 view .LVU1342 + 4099 0048 2B62 str r3, [r5, #32] +1577:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4100 .loc 1 1577 2 is_stmt 1 view .LVU1343 +1577:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4101 .loc 1 1577 9 is_stmt 0 view .LVU1344 + 4102 004a 0020 movs r0, #0 + 4103 .LVL471: + 4104 .L309: +1578:Middlewares/Third_Party/FatFs/src/ff.c **** + 4105 .loc 1 1578 1 view .LVU1345 + 4106 004c BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} + 4107 .LVL472: + 4108 .L326: +1538:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4109 .loc 1 1538 5 is_stmt 1 view .LVU1346 +1538:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4110 .loc 1 1538 14 is_stmt 0 view .LVU1347 + 4111 0050 0023 movs r3, #0 + 4112 0052 C361 str r3, [r0, #28] +1538:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4113 .loc 1 1538 19 is_stmt 1 view .LVU1348 +1538:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4114 .loc 1 1538 26 is_stmt 0 view .LVU1349 + 4115 0054 0420 movs r0, #4 + 4116 .LVL473: +1538:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4117 .loc 1 1538 26 view .LVU1350 + ARM GAS /tmp/cc2SVLkL.s page 195 + + + 4118 0056 F9E7 b .L309 + 4119 .LVL474: + 4120 .L311: +1542:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&dp->obj, dp->clust); /* Get next cluster */ + 4121 .loc 1 1542 4 is_stmt 1 view .LVU1351 +1542:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&dp->obj, dp->clust); /* Get next cluster */ + 4122 .loc 1 1542 15 is_stmt 0 view .LVU1352 + 4123 0058 B289 ldrh r2, [r6, #12] +1542:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&dp->obj, dp->clust); /* Get next cluster */ + 4124 .loc 1 1542 13 view .LVU1353 + 4125 005a B4FBF2F2 udiv r2, r4, r2 +1542:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&dp->obj, dp->clust); /* Get next cluster */ + 4126 .loc 1 1542 27 view .LVU1354 + 4127 005e 7389 ldrh r3, [r6, #10] +1542:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&dp->obj, dp->clust); /* Get next cluster */ + 4128 .loc 1 1542 35 view .LVU1355 + 4129 0060 013B subs r3, r3, #1 +1542:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&dp->obj, dp->clust); /* Get next cluster */ + 4130 .loc 1 1542 7 view .LVU1356 + 4131 0062 12EA0308 ands r8, r2, r3 + 4132 0066 E6D1 bne .L310 +1543:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst <= 1) return FR_INT_ERR; /* Internal error */ + 4133 .loc 1 1543 5 is_stmt 1 view .LVU1357 +1543:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst <= 1) return FR_INT_ERR; /* Internal error */ + 4134 .loc 1 1543 12 is_stmt 0 view .LVU1358 + 4135 0068 FFF7FEFF bl get_fat + 4136 .LVL475: +1543:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst <= 1) return FR_INT_ERR; /* Internal error */ + 4137 .loc 1 1543 12 view .LVU1359 + 4138 006c 8146 mov r9, r0 + 4139 .LVL476: +1544:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + 4140 .loc 1 1544 5 is_stmt 1 view .LVU1360 +1544:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + 4141 .loc 1 1544 8 is_stmt 0 view .LVU1361 + 4142 006e 0128 cmp r0, #1 + 4143 0070 46D9 bls .L318 +1545:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst >= fs->n_fatent) { /* Reached end of dynamic table */ + 4144 .loc 1 1545 5 is_stmt 1 view .LVU1362 +1545:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst >= fs->n_fatent) { /* Reached end of dynamic table */ + 4145 .loc 1 1545 8 is_stmt 0 view .LVU1363 + 4146 0072 B0F1FF3F cmp r0, #-1 + 4147 0076 45D0 beq .L319 +1546:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 4148 .loc 1 1546 5 is_stmt 1 view .LVU1364 +1546:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 4149 .loc 1 1546 19 is_stmt 0 view .LVU1365 + 4150 0078 B369 ldr r3, [r6, #24] +1546:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 4151 .loc 1 1546 8 view .LVU1366 + 4152 007a 8342 cmp r3, r0 + 4153 007c 34D8 bhi .L312 +1548:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect = 0; return FR_NO_FILE; + 4154 .loc 1 1548 6 is_stmt 1 view .LVU1367 +1548:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect = 0; return FR_NO_FILE; + 4155 .loc 1 1548 9 is_stmt 0 view .LVU1368 + 4156 007e 8FB1 cbz r7, .L327 + ARM GAS /tmp/cc2SVLkL.s page 196 + + +1551:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0) return FR_DENIED; /* No free cluster */ + 4157 .loc 1 1551 6 is_stmt 1 view .LVU1369 +1551:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0) return FR_DENIED; /* No free cluster */ + 4158 .loc 1 1551 13 is_stmt 0 view .LVU1370 + 4159 0080 A969 ldr r1, [r5, #24] + 4160 0082 2846 mov r0, r5 + 4161 .LVL477: +1551:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0) return FR_DENIED; /* No free cluster */ + 4162 .loc 1 1551 13 view .LVU1371 + 4163 0084 FFF7FEFF bl create_chain + 4164 .LVL478: +1552:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 1) return FR_INT_ERR; /* Internal error */ + 4165 .loc 1 1552 6 is_stmt 1 view .LVU1372 +1552:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 1) return FR_INT_ERR; /* Internal error */ + 4166 .loc 1 1552 9 is_stmt 0 view .LVU1373 + 4167 0088 8146 mov r9, r0 + 4168 008a 0028 cmp r0, #0 + 4169 008c 3CD0 beq .L320 +1553:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + 4170 .loc 1 1553 6 is_stmt 1 view .LVU1374 +1553:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + 4171 .loc 1 1553 9 is_stmt 0 view .LVU1375 + 4172 008e 0128 cmp r0, #1 + 4173 0090 3CD0 beq .L321 +1554:Middlewares/Third_Party/FatFs/src/ff.c **** /* Clean-up the stretched table */ + 4174 .loc 1 1554 6 is_stmt 1 view .LVU1376 +1554:Middlewares/Third_Party/FatFs/src/ff.c **** /* Clean-up the stretched table */ + 4175 .loc 1 1554 9 is_stmt 0 view .LVU1377 + 4176 0092 B0F1FF3F cmp r0, #-1 + 4177 0096 3BD0 beq .L322 +1556:Middlewares/Third_Party/FatFs/src/ff.c **** if (sync_window(fs) != FR_OK) return FR_DISK_ERR; /* Flush disk access window */ + 4178 .loc 1 1556 6 is_stmt 1 view .LVU1378 +1557:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(fs->win, 0, SS(fs)); /* Clear window buffer */ + 4179 .loc 1 1557 6 view .LVU1379 +1557:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(fs->win, 0, SS(fs)); /* Clear window buffer */ + 4180 .loc 1 1557 10 is_stmt 0 view .LVU1380 + 4181 0098 3046 mov r0, r6 + 4182 .LVL479: +1557:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(fs->win, 0, SS(fs)); /* Clear window buffer */ + 4183 .loc 1 1557 10 view .LVU1381 + 4184 009a FFF7FEFF bl sync_window + 4185 .LVL480: +1557:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(fs->win, 0, SS(fs)); /* Clear window buffer */ + 4186 .loc 1 1557 9 discriminator 1 view .LVU1382 + 4187 009e 28B1 cbz r0, .L328 +1557:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(fs->win, 0, SS(fs)); /* Clear window buffer */ + 4188 .loc 1 1557 43 discriminator 1 view .LVU1383 + 4189 00a0 0120 movs r0, #1 + 4190 00a2 D3E7 b .L309 + 4191 .LVL481: + 4192 .L327: +1549:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4193 .loc 1 1549 7 is_stmt 1 view .LVU1384 +1549:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4194 .loc 1 1549 16 is_stmt 0 view .LVU1385 + 4195 00a4 0023 movs r3, #0 + 4196 00a6 EB61 str r3, [r5, #28] + ARM GAS /tmp/cc2SVLkL.s page 197 + + +1549:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4197 .loc 1 1549 21 is_stmt 1 view .LVU1386 +1549:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4198 .loc 1 1549 28 is_stmt 0 view .LVU1387 + 4199 00a8 0420 movs r0, #4 + 4200 .LVL482: +1549:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4201 .loc 1 1549 28 view .LVU1388 + 4202 00aa CFE7 b .L309 + 4203 .L328: +1558:Middlewares/Third_Party/FatFs/src/ff.c **** for (n = 0, fs->winsect = clust2sect(fs, clst); n < fs->csize; n++, fs->winsect++) { /* Fill t + 4204 .loc 1 1558 6 is_stmt 1 view .LVU1389 + 4205 00ac B289 ldrh r2, [r6, #12] + 4206 00ae 0021 movs r1, #0 + 4207 00b0 06F13400 add r0, r6, #52 + 4208 00b4 FFF7FEFF bl mem_set + 4209 .LVL483: +1559:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 4210 .loc 1 1559 6 view .LVU1390 +1559:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 4211 .loc 1 1559 32 is_stmt 0 view .LVU1391 + 4212 00b8 4946 mov r1, r9 + 4213 00ba 3046 mov r0, r6 + 4214 00bc FFF7FEFF bl clust2sect + 4215 .LVL484: +1559:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 4216 .loc 1 1559 30 discriminator 1 view .LVU1392 + 4217 00c0 3063 str r0, [r6, #48] + 4218 .LVL485: + 4219 .L314: +1559:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 4220 .loc 1 1559 56 is_stmt 1 discriminator 1 view .LVU1393 +1559:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 4221 .loc 1 1559 60 is_stmt 0 discriminator 1 view .LVU1394 + 4222 00c2 7389 ldrh r3, [r6, #10] +1559:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 4223 .loc 1 1559 56 discriminator 1 view .LVU1395 + 4224 00c4 9845 cmp r8, r3 + 4225 00c6 0BD2 bcs .L329 +1560:Middlewares/Third_Party/FatFs/src/ff.c **** if (sync_window(fs) != FR_OK) return FR_DISK_ERR; + 4226 .loc 1 1560 7 is_stmt 1 view .LVU1396 +1560:Middlewares/Third_Party/FatFs/src/ff.c **** if (sync_window(fs) != FR_OK) return FR_DISK_ERR; + 4227 .loc 1 1560 17 is_stmt 0 view .LVU1397 + 4228 00c8 0123 movs r3, #1 + 4229 00ca F370 strb r3, [r6, #3] +1561:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4230 .loc 1 1561 7 is_stmt 1 view .LVU1398 +1561:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4231 .loc 1 1561 11 is_stmt 0 view .LVU1399 + 4232 00cc 3046 mov r0, r6 + 4233 00ce FFF7FEFF bl sync_window + 4234 .LVL486: +1561:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4235 .loc 1 1561 10 discriminator 1 view .LVU1400 + 4236 00d2 F8B9 cbnz r0, .L324 +1559:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 4237 .loc 1 1559 72 is_stmt 1 discriminator 2 view .LVU1401 + ARM GAS /tmp/cc2SVLkL.s page 198 + + +1559:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 4238 .loc 1 1559 70 is_stmt 0 discriminator 2 view .LVU1402 + 4239 00d4 08F10108 add r8, r8, #1 + 4240 .LVL487: +1559:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 4241 .loc 1 1559 76 discriminator 2 view .LVU1403 + 4242 00d8 336B ldr r3, [r6, #48] +1559:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 4243 .loc 1 1559 85 discriminator 2 view .LVU1404 + 4244 00da 0133 adds r3, r3, #1 + 4245 00dc 3363 str r3, [r6, #48] + 4246 00de F0E7 b .L314 + 4247 .L329: +1563:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 4248 .loc 1 1563 6 is_stmt 1 view .LVU1405 +1563:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 4249 .loc 1 1563 8 is_stmt 0 view .LVU1406 + 4250 00e0 336B ldr r3, [r6, #48] +1563:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 4251 .loc 1 1563 18 view .LVU1407 + 4252 00e2 A3EB0803 sub r3, r3, r8 + 4253 00e6 3363 str r3, [r6, #48] + 4254 .LVL488: + 4255 .L312: +1569:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect = clust2sect(fs, clst); + 4256 .loc 1 1569 5 is_stmt 1 view .LVU1408 +1569:Middlewares/Third_Party/FatFs/src/ff.c **** dp->sect = clust2sect(fs, clst); + 4257 .loc 1 1569 15 is_stmt 0 view .LVU1409 + 4258 00e8 C5F81890 str r9, [r5, #24] +1570:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4259 .loc 1 1570 5 is_stmt 1 view .LVU1410 +1570:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4260 .loc 1 1570 16 is_stmt 0 view .LVU1411 + 4261 00ec 4946 mov r1, r9 + 4262 00ee 3046 mov r0, r6 + 4263 00f0 FFF7FEFF bl clust2sect + 4264 .LVL489: +1570:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4265 .loc 1 1570 14 discriminator 1 view .LVU1412 + 4266 00f4 E861 str r0, [r5, #28] + 4267 00f6 9EE7 b .L310 + 4268 .LVL490: + 4269 .L316: +1531:Middlewares/Third_Party/FatFs/src/ff.c **** + 4270 .loc 1 1531 105 discriminator 3 view .LVU1413 + 4271 00f8 0420 movs r0, #4 + 4272 .LVL491: +1531:Middlewares/Third_Party/FatFs/src/ff.c **** + 4273 .loc 1 1531 105 discriminator 3 view .LVU1414 + 4274 00fa A7E7 b .L309 + 4275 .LVL492: + 4276 .L317: +1531:Middlewares/Third_Party/FatFs/src/ff.c **** + 4277 .loc 1 1531 105 discriminator 3 view .LVU1415 + 4278 00fc 0420 movs r0, #4 + 4279 .LVL493: +1531:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 199 + + + 4280 .loc 1 1531 105 discriminator 3 view .LVU1416 + 4281 00fe A5E7 b .L309 + 4282 .LVL494: + 4283 .L318: +1544:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + 4284 .loc 1 1544 27 discriminator 1 view .LVU1417 + 4285 0100 0220 movs r0, #2 + 4286 .LVL495: +1544:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + 4287 .loc 1 1544 27 discriminator 1 view .LVU1418 + 4288 0102 A3E7 b .L309 + 4289 .LVL496: + 4290 .L319: +1545:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst >= fs->n_fatent) { /* Reached end of dynamic table */ + 4291 .loc 1 1545 36 discriminator 1 view .LVU1419 + 4292 0104 0120 movs r0, #1 + 4293 .LVL497: +1545:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst >= fs->n_fatent) { /* Reached end of dynamic table */ + 4294 .loc 1 1545 36 discriminator 1 view .LVU1420 + 4295 0106 A1E7 b .L309 + 4296 .LVL498: + 4297 .L320: +1552:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 1) return FR_INT_ERR; /* Internal error */ + 4298 .loc 1 1552 28 discriminator 1 view .LVU1421 + 4299 0108 0720 movs r0, #7 + 4300 .LVL499: +1552:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 1) return FR_INT_ERR; /* Internal error */ + 4301 .loc 1 1552 28 discriminator 1 view .LVU1422 + 4302 010a 9FE7 b .L309 + 4303 .LVL500: + 4304 .L321: +1553:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + 4305 .loc 1 1553 28 discriminator 1 view .LVU1423 + 4306 010c 0220 movs r0, #2 + 4307 .LVL501: +1553:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + 4308 .loc 1 1553 28 discriminator 1 view .LVU1424 + 4309 010e 9DE7 b .L309 + 4310 .LVL502: + 4311 .L322: +1554:Middlewares/Third_Party/FatFs/src/ff.c **** /* Clean-up the stretched table */ + 4312 .loc 1 1554 37 discriminator 1 view .LVU1425 + 4313 0110 0120 movs r0, #1 + 4314 .LVL503: +1554:Middlewares/Third_Party/FatFs/src/ff.c **** /* Clean-up the stretched table */ + 4315 .loc 1 1554 37 discriminator 1 view .LVU1426 + 4316 0112 9BE7 b .L309 + 4317 .LVL504: + 4318 .L324: +1561:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4319 .loc 1 1561 44 discriminator 1 view .LVU1427 + 4320 0114 0120 movs r0, #1 + 4321 0116 99E7 b .L309 + 4322 .cfi_endproc + 4323 .LFE1206: + 4325 .section .text.dir_find,"ax",%progbits + 4326 .align 1 + ARM GAS /tmp/cc2SVLkL.s page 200 + + + 4327 .syntax unified + 4328 .thumb + 4329 .thumb_func + 4331 dir_find: + 4332 .LVL505: + 4333 .LFB1211: +2213:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 4334 .loc 1 2213 1 is_stmt 1 view -0 + 4335 .cfi_startproc + 4336 @ args = 0, pretend = 0, frame = 0 + 4337 @ frame_needed = 0, uses_anonymous_args = 0 +2213:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 4338 .loc 1 2213 1 is_stmt 0 view .LVU1429 + 4339 0000 70B5 push {r4, r5, r6, lr} + 4340 .LCFI29: + 4341 .cfi_def_cfa_offset 16 + 4342 .cfi_offset 4, -16 + 4343 .cfi_offset 5, -12 + 4344 .cfi_offset 6, -8 + 4345 .cfi_offset 14, -4 + 4346 0002 0446 mov r4, r0 +2214:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = dp->obj.fs; + 4347 .loc 1 2214 2 is_stmt 1 view .LVU1430 +2215:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE c; + 4348 .loc 1 2215 2 view .LVU1431 +2215:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE c; + 4349 .loc 1 2215 9 is_stmt 0 view .LVU1432 + 4350 0004 0668 ldr r6, [r0] + 4351 .LVL506: +2216:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 + 4352 .loc 1 2216 2 is_stmt 1 view .LVU1433 +2221:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; + 4353 .loc 1 2221 2 view .LVU1434 +2221:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) return res; + 4354 .loc 1 2221 8 is_stmt 0 view .LVU1435 + 4355 0006 0021 movs r1, #0 + 4356 0008 FFF7FEFF bl dir_sdi + 4357 .LVL507: +2222:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 4358 .loc 1 2222 2 is_stmt 1 view .LVU1436 +2222:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 4359 .loc 1 2222 5 is_stmt 0 view .LVU1437 + 4360 000c 0546 mov r5, r0 + 4361 000e 40B1 cbz r0, .L333 + 4362 .LVL508: + 4363 .L331: +2281:Middlewares/Third_Party/FatFs/src/ff.c **** + 4364 .loc 1 2281 1 view .LVU1438 + 4365 0010 2846 mov r0, r5 + 4366 0012 70BD pop {r4, r5, r6, pc} + 4367 .LVL509: + 4368 .L332: +2277:Middlewares/Third_Party/FatFs/src/ff.c **** } while (res == FR_OK); + 4369 .loc 1 2277 3 is_stmt 1 view .LVU1439 +2277:Middlewares/Third_Party/FatFs/src/ff.c **** } while (res == FR_OK); + 4370 .loc 1 2277 9 is_stmt 0 view .LVU1440 + 4371 0014 0021 movs r1, #0 + ARM GAS /tmp/cc2SVLkL.s page 201 + + + 4372 0016 2046 mov r0, r4 + 4373 0018 FFF7FEFF bl dir_next + 4374 .LVL510: +2278:Middlewares/Third_Party/FatFs/src/ff.c **** + 4375 .loc 1 2278 15 is_stmt 1 view .LVU1441 + 4376 001c 0546 mov r5, r0 + 4377 001e 0028 cmp r0, #0 + 4378 0020 F6D1 bne .L331 + 4379 .LVL511: + 4380 .L333: +2247:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dp->sect); + 4381 .loc 1 2247 2 view .LVU1442 +2248:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 4382 .loc 1 2248 3 view .LVU1443 +2248:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 4383 .loc 1 2248 9 is_stmt 0 view .LVU1444 + 4384 0022 E169 ldr r1, [r4, #28] + 4385 0024 3046 mov r0, r6 + 4386 .LVL512: +2248:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 4387 .loc 1 2248 9 view .LVU1445 + 4388 0026 FFF7FEFF bl move_window + 4389 .LVL513: +2249:Middlewares/Third_Party/FatFs/src/ff.c **** c = dp->dir[DIR_Name]; + 4390 .loc 1 2249 3 is_stmt 1 view .LVU1446 +2249:Middlewares/Third_Party/FatFs/src/ff.c **** c = dp->dir[DIR_Name]; + 4391 .loc 1 2249 6 is_stmt 0 view .LVU1447 + 4392 002a 0546 mov r5, r0 + 4393 002c 0028 cmp r0, #0 + 4394 002e EFD1 bne .L331 +2250:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ + 4395 .loc 1 2250 3 is_stmt 1 view .LVU1448 +2250:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ + 4396 .loc 1 2250 9 is_stmt 0 view .LVU1449 + 4397 0030 206A ldr r0, [r4, #32] + 4398 .LVL514: +2250:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ + 4399 .loc 1 2250 5 view .LVU1450 + 4400 0032 0378 ldrb r3, [r0] @ zero_extendqisi2 + 4401 .LVL515: +2251:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 /* LFN configuration */ + 4402 .loc 1 2251 3 is_stmt 1 view .LVU1451 +2251:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 /* LFN configuration */ + 4403 .loc 1 2251 6 is_stmt 0 view .LVU1452 + 4404 0034 7BB1 cbz r3, .L334 +2274:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(dp->dir[DIR_Attr] & AM_VOL) && !mem_cmp(dp->dir, dp->fn, 11)) break; /* Is it a valid entry + 4405 .loc 1 2274 3 is_stmt 1 view .LVU1453 +2274:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(dp->dir[DIR_Attr] & AM_VOL) && !mem_cmp(dp->dir, dp->fn, 11)) break; /* Is it a valid entry + 4406 .loc 1 2274 25 is_stmt 0 view .LVU1454 + 4407 0036 C37A ldrb r3, [r0, #11] @ zero_extendqisi2 +2274:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(dp->dir[DIR_Attr] & AM_VOL) && !mem_cmp(dp->dir, dp->fn, 11)) break; /* Is it a valid entry + 4408 .loc 1 2274 36 view .LVU1455 + 4409 0038 03F03F03 and r3, r3, #63 +2274:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(dp->dir[DIR_Attr] & AM_VOL) && !mem_cmp(dp->dir, dp->fn, 11)) break; /* Is it a valid entry + 4410 .loc 1 2274 16 view .LVU1456 + 4411 003c A371 strb r3, [r4, #6] + 4412 .LVL516: + ARM GAS /tmp/cc2SVLkL.s page 202 + + +2275:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 4413 .loc 1 2275 3 is_stmt 1 view .LVU1457 +2275:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 4414 .loc 1 2275 16 is_stmt 0 view .LVU1458 + 4415 003e C37A ldrb r3, [r0, #11] @ zero_extendqisi2 +2275:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 4416 .loc 1 2275 6 view .LVU1459 + 4417 0040 13F0080F tst r3, #8 + 4418 0044 E6D1 bne .L332 +2275:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 4419 .loc 1 2275 41 discriminator 1 view .LVU1460 + 4420 0046 0B22 movs r2, #11 + 4421 0048 04F12401 add r1, r4, #36 + 4422 004c FFF7FEFF bl mem_cmp + 4423 .LVL517: +2275:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 4424 .loc 1 2275 37 discriminator 1 view .LVU1461 + 4425 0050 0028 cmp r0, #0 + 4426 0052 DFD1 bne .L332 + 4427 0054 DCE7 b .L331 + 4428 .LVL518: + 4429 .L334: +2251:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 /* LFN configuration */ + 4430 .loc 1 2251 21 discriminator 1 view .LVU1462 + 4431 0056 0425 movs r5, #4 + 4432 .LVL519: +2251:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 /* LFN configuration */ + 4433 .loc 1 2251 21 discriminator 1 view .LVU1463 + 4434 0058 DAE7 b .L331 + 4435 .cfi_endproc + 4436 .LFE1211: + 4438 .section .text.follow_path,"ax",%progbits + 4439 .align 1 + 4440 .syntax unified + 4441 .thumb + 4442 .thumb_func + 4444 follow_path: + 4445 .LVL520: + 4446 .LFB1216: +2817:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 4447 .loc 1 2817 1 is_stmt 1 view -0 + 4448 .cfi_startproc + 4449 @ args = 0, pretend = 0, frame = 8 + 4450 @ frame_needed = 0, uses_anonymous_args = 0 +2817:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 4451 .loc 1 2817 1 is_stmt 0 view .LVU1465 + 4452 0000 30B5 push {r4, r5, lr} + 4453 .LCFI30: + 4454 .cfi_def_cfa_offset 12 + 4455 .cfi_offset 4, -12 + 4456 .cfi_offset 5, -8 + 4457 .cfi_offset 14, -4 + 4458 0002 83B0 sub sp, sp, #12 + 4459 .LCFI31: + 4460 .cfi_def_cfa_offset 24 + 4461 0004 0446 mov r4, r0 + 4462 0006 0191 str r1, [sp, #4] + ARM GAS /tmp/cc2SVLkL.s page 203 + + +2818:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE ns; + 4463 .loc 1 2818 2 is_stmt 1 view .LVU1466 +2819:Middlewares/Third_Party/FatFs/src/ff.c **** _FDID *obj = &dp->obj; + 4464 .loc 1 2819 2 view .LVU1467 +2820:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = obj->fs; + 4465 .loc 1 2820 2 view .LVU1468 + 4466 .LVL521: +2821:Middlewares/Third_Party/FatFs/src/ff.c **** + 4467 .loc 1 2821 2 view .LVU1469 +2821:Middlewares/Third_Party/FatFs/src/ff.c **** + 4468 .loc 1 2821 9 is_stmt 0 view .LVU1470 + 4469 0008 0568 ldr r5, [r0] + 4470 .LVL522: +2830:Middlewares/Third_Party/FatFs/src/ff.c **** obj->sclust = 0; /* Start from root directory */ + 4471 .loc 1 2830 3 is_stmt 1 view .LVU1471 +2830:Middlewares/Third_Party/FatFs/src/ff.c **** obj->sclust = 0; /* Start from root directory */ + 4472 .loc 1 2830 9 is_stmt 0 view .LVU1472 + 4473 000a 01E0 b .L337 + 4474 .L338: +2830:Middlewares/Third_Party/FatFs/src/ff.c **** obj->sclust = 0; /* Start from root directory */ + 4475 .loc 1 2830 41 is_stmt 1 discriminator 2 view .LVU1473 +2830:Middlewares/Third_Party/FatFs/src/ff.c **** obj->sclust = 0; /* Start from root directory */ + 4476 .loc 1 2830 45 is_stmt 0 discriminator 2 view .LVU1474 + 4477 000c 0133 adds r3, r3, #1 + 4478 000e 0193 str r3, [sp, #4] + 4479 .L337: +2830:Middlewares/Third_Party/FatFs/src/ff.c **** obj->sclust = 0; /* Start from root directory */ + 4480 .loc 1 2830 23 is_stmt 1 discriminator 1 view .LVU1475 +2830:Middlewares/Third_Party/FatFs/src/ff.c **** obj->sclust = 0; /* Start from root directory */ + 4481 .loc 1 2830 10 is_stmt 0 discriminator 1 view .LVU1476 + 4482 0010 019B ldr r3, [sp, #4] + 4483 0012 1A78 ldrb r2, [r3] @ zero_extendqisi2 +2830:Middlewares/Third_Party/FatFs/src/ff.c **** obj->sclust = 0; /* Start from root directory */ + 4484 .loc 1 2830 23 discriminator 1 view .LVU1477 + 4485 0014 2F2A cmp r2, #47 + 4486 0016 F9D0 beq .L338 + 4487 0018 5C2A cmp r2, #92 + 4488 001a F7D0 beq .L338 +2831:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4489 .loc 1 2831 3 is_stmt 1 view .LVU1478 +2831:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4490 .loc 1 2831 15 is_stmt 0 view .LVU1479 + 4491 001c 0022 movs r2, #0 + 4492 001e A260 str r2, [r4, #8] +2850:Middlewares/Third_Party/FatFs/src/ff.c **** dp->fn[NSFLAG] = NS_NONAME; + 4493 .loc 1 2850 2 is_stmt 1 view .LVU1480 +2850:Middlewares/Third_Party/FatFs/src/ff.c **** dp->fn[NSFLAG] = NS_NONAME; + 4494 .loc 1 2850 12 is_stmt 0 view .LVU1481 + 4495 0020 1B78 ldrb r3, [r3] @ zero_extendqisi2 +2850:Middlewares/Third_Party/FatFs/src/ff.c **** dp->fn[NSFLAG] = NS_NONAME; + 4496 .loc 1 2850 5 view .LVU1482 + 4497 0022 1F2B cmp r3, #31 + 4498 0024 21D9 bls .L345 + 4499 .LVL523: + 4500 .L339: +2855:Middlewares/Third_Party/FatFs/src/ff.c **** res = create_name(dp, &path); /* Get a segment name of the path */ + 4501 .loc 1 2855 3 is_stmt 1 view .LVU1483 + ARM GAS /tmp/cc2SVLkL.s page 204 + + +2856:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 4502 .loc 1 2856 4 view .LVU1484 +2856:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 4503 .loc 1 2856 10 is_stmt 0 view .LVU1485 + 4504 0026 01A9 add r1, sp, #4 + 4505 0028 2046 mov r0, r4 + 4506 002a FFF7FEFF bl create_name + 4507 .LVL524: +2857:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_find(dp); /* Find an object with the segment name */ + 4508 .loc 1 2857 4 is_stmt 1 view .LVU1486 +2857:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_find(dp); /* Find an object with the segment name */ + 4509 .loc 1 2857 7 is_stmt 0 view .LVU1487 + 4510 002e 0346 mov r3, r0 + 4511 0030 18BB cbnz r0, .L340 +2858:Middlewares/Third_Party/FatFs/src/ff.c **** ns = dp->fn[NSFLAG]; + 4512 .loc 1 2858 4 is_stmt 1 view .LVU1488 +2858:Middlewares/Third_Party/FatFs/src/ff.c **** ns = dp->fn[NSFLAG]; + 4513 .loc 1 2858 10 is_stmt 0 view .LVU1489 + 4514 0032 2046 mov r0, r4 + 4515 .LVL525: +2858:Middlewares/Third_Party/FatFs/src/ff.c **** ns = dp->fn[NSFLAG]; + 4516 .loc 1 2858 10 view .LVU1490 + 4517 0034 FFF7FEFF bl dir_find + 4518 .LVL526: +2859:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) { /* Failed to find the object */ + 4519 .loc 1 2859 4 is_stmt 1 view .LVU1491 +2859:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) { /* Failed to find the object */ + 4520 .loc 1 2859 7 is_stmt 0 view .LVU1492 + 4521 0038 94F82F20 ldrb r2, [r4, #47] @ zero_extendqisi2 + 4522 .LVL527: +2860:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) { /* Object is not found */ + 4523 .loc 1 2860 4 is_stmt 1 view .LVU1493 +2860:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) { /* Object is not found */ + 4524 .loc 1 2860 7 is_stmt 0 view .LVU1494 + 4525 003c 0346 mov r3, r0 + 4526 003e F8B9 cbnz r0, .L346 +2872:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get into the sub-directory */ + 4527 .loc 1 2872 4 is_stmt 1 view .LVU1495 +2872:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get into the sub-directory */ + 4528 .loc 1 2872 7 is_stmt 0 view .LVU1496 + 4529 0040 12F0040F tst r2, #4 + 4530 0044 19D1 bne .L340 +2874:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_NO_PATH; break; + 4531 .loc 1 2874 4 is_stmt 1 view .LVU1497 +2874:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_NO_PATH; break; + 4532 .loc 1 2874 13 is_stmt 0 view .LVU1498 + 4533 0046 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 +2874:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_NO_PATH; break; + 4534 .loc 1 2874 7 view .LVU1499 + 4535 0048 13F0100F tst r3, #16 + 4536 004c 1FD0 beq .L343 +2888:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4537 .loc 1 2888 5 is_stmt 1 view .LVU1500 +2888:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4538 .loc 1 2888 32 is_stmt 0 view .LVU1501 + 4539 004e 05F13401 add r1, r5, #52 +2888:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 205 + + + 4540 .loc 1 2888 44 view .LVU1502 + 4541 0052 6369 ldr r3, [r4, #20] +2888:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4542 .loc 1 2888 53 view .LVU1503 + 4543 0054 AA89 ldrh r2, [r5, #12] + 4544 .LVL528: +2888:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4545 .loc 1 2888 51 view .LVU1504 + 4546 0056 B3FBF2F0 udiv r0, r3, r2 + 4547 .LVL529: +2888:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4548 .loc 1 2888 51 view .LVU1505 + 4549 005a 02FB1033 mls r3, r2, r0, r3 +2888:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4550 .loc 1 2888 19 view .LVU1506 + 4551 005e 1944 add r1, r1, r3 + 4552 0060 2846 mov r0, r5 + 4553 0062 FFF7FEFF bl ld_clust + 4554 .LVL530: +2888:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4555 .loc 1 2888 17 discriminator 1 view .LVU1507 + 4556 0066 A060 str r0, [r4, #8] +2855:Middlewares/Third_Party/FatFs/src/ff.c **** res = create_name(dp, &path); /* Get a segment name of the path */ + 4557 .loc 1 2855 3 is_stmt 1 view .LVU1508 +2856:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 4558 .loc 1 2856 8 is_stmt 0 view .LVU1509 + 4559 0068 DDE7 b .L339 + 4560 .LVL531: + 4561 .L345: +2851:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(dp, 0); + 4562 .loc 1 2851 3 is_stmt 1 view .LVU1510 +2851:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(dp, 0); + 4563 .loc 1 2851 18 is_stmt 0 view .LVU1511 + 4564 006a 8023 movs r3, #128 + 4565 006c 84F82F30 strb r3, [r4, #47] +2852:Middlewares/Third_Party/FatFs/src/ff.c **** + 4566 .loc 1 2852 3 is_stmt 1 view .LVU1512 +2852:Middlewares/Third_Party/FatFs/src/ff.c **** + 4567 .loc 1 2852 9 is_stmt 0 view .LVU1513 + 4568 0070 1146 mov r1, r2 + 4569 .LVL532: +2852:Middlewares/Third_Party/FatFs/src/ff.c **** + 4570 .loc 1 2852 9 view .LVU1514 + 4571 0072 2046 mov r0, r4 + 4572 .LVL533: +2852:Middlewares/Third_Party/FatFs/src/ff.c **** + 4573 .loc 1 2852 9 view .LVU1515 + 4574 0074 FFF7FEFF bl dir_sdi + 4575 .LVL534: + 4576 0078 0346 mov r3, r0 + 4577 .LVL535: + 4578 .L340: +2893:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4579 .loc 1 2893 2 is_stmt 1 view .LVU1516 +2894:Middlewares/Third_Party/FatFs/src/ff.c **** + 4580 .loc 1 2894 1 is_stmt 0 view .LVU1517 + 4581 007a 1846 mov r0, r3 + ARM GAS /tmp/cc2SVLkL.s page 206 + + + 4582 007c 03B0 add sp, sp, #12 + 4583 .LCFI32: + 4584 .cfi_remember_state + 4585 .cfi_def_cfa_offset 12 + 4586 @ sp needed + 4587 007e 30BD pop {r4, r5, pc} + 4588 .LVL536: + 4589 .L346: + 4590 .LCFI33: + 4591 .cfi_restore_state +2861:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exist, stay there */ + 4592 .loc 1 2861 5 is_stmt 1 view .LVU1518 +2861:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exist, stay there */ + 4593 .loc 1 2861 8 is_stmt 0 view .LVU1519 + 4594 0080 0428 cmp r0, #4 + 4595 0082 FAD1 bne .L340 +2862:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(ns & NS_LAST)) continue; /* Continue to follow if not last segment */ + 4596 .loc 1 2862 6 is_stmt 1 view .LVU1520 +2867:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4597 .loc 1 2867 7 view .LVU1521 +2867:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4598 .loc 1 2867 10 is_stmt 0 view .LVU1522 + 4599 0084 12F0040F tst r2, #4 + 4600 0088 F7D1 bne .L340 +2867:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4601 .loc 1 2867 32 discriminator 1 view .LVU1523 + 4602 008a 0523 movs r3, #5 + 4603 008c F5E7 b .L340 + 4604 .L343: +2875:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4605 .loc 1 2875 9 view .LVU1524 + 4606 008e 0523 movs r3, #5 + 4607 0090 F3E7 b .L340 + 4608 .cfi_endproc + 4609 .LFE1216: + 4611 .section .text.dir_alloc,"ax",%progbits + 4612 .align 1 + 4613 .syntax unified + 4614 .thumb + 4615 .thumb_func + 4617 dir_alloc: + 4618 .LVL537: + 4619 .LFB1207: +1593:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 4620 .loc 1 1593 1 is_stmt 1 view -0 + 4621 .cfi_startproc + 4622 @ args = 0, pretend = 0, frame = 0 + 4623 @ frame_needed = 0, uses_anonymous_args = 0 +1593:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 4624 .loc 1 1593 1 is_stmt 0 view .LVU1526 + 4625 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 4626 .LCFI34: + 4627 .cfi_def_cfa_offset 24 + 4628 .cfi_offset 3, -24 + 4629 .cfi_offset 4, -20 + 4630 .cfi_offset 5, -16 + 4631 .cfi_offset 6, -12 + ARM GAS /tmp/cc2SVLkL.s page 207 + + + 4632 .cfi_offset 7, -8 + 4633 .cfi_offset 14, -4 + 4634 0002 0446 mov r4, r0 + 4635 0004 0E46 mov r6, r1 +1594:Middlewares/Third_Party/FatFs/src/ff.c **** UINT n; + 4636 .loc 1 1594 2 is_stmt 1 view .LVU1527 +1595:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = dp->obj.fs; + 4637 .loc 1 1595 2 view .LVU1528 +1596:Middlewares/Third_Party/FatFs/src/ff.c **** + 4638 .loc 1 1596 2 view .LVU1529 +1596:Middlewares/Third_Party/FatFs/src/ff.c **** + 4639 .loc 1 1596 9 is_stmt 0 view .LVU1530 + 4640 0006 0768 ldr r7, [r0] + 4641 .LVL538: +1599:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 4642 .loc 1 1599 2 is_stmt 1 view .LVU1531 +1599:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 4643 .loc 1 1599 8 is_stmt 0 view .LVU1532 + 4644 0008 0021 movs r1, #0 + 4645 .LVL539: +1599:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 4646 .loc 1 1599 8 view .LVU1533 + 4647 000a FFF7FEFF bl dir_sdi + 4648 .LVL540: +1600:Middlewares/Third_Party/FatFs/src/ff.c **** n = 0; + 4649 .loc 1 1600 2 is_stmt 1 view .LVU1534 +1600:Middlewares/Third_Party/FatFs/src/ff.c **** n = 0; + 4650 .loc 1 1600 5 is_stmt 0 view .LVU1535 + 4651 000e 0246 mov r2, r0 + 4652 0010 B8B9 cbnz r0, .L348 +1601:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 4653 .loc 1 1601 5 view .LVU1536 + 4654 0012 0025 movs r5, #0 + 4655 0014 06E0 b .L350 + 4656 .LVL541: + 4657 .L352: +1612:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4658 .loc 1 1612 7 view .LVU1537 + 4659 0016 0025 movs r5, #0 + 4660 .LVL542: + 4661 .L349: +1614:Middlewares/Third_Party/FatFs/src/ff.c **** } while (res == FR_OK); /* Next entry with table stretch enabled */ + 4662 .loc 1 1614 4 is_stmt 1 view .LVU1538 +1614:Middlewares/Third_Party/FatFs/src/ff.c **** } while (res == FR_OK); /* Next entry with table stretch enabled */ + 4663 .loc 1 1614 10 is_stmt 0 view .LVU1539 + 4664 0018 0121 movs r1, #1 + 4665 001a 2046 mov r0, r4 + 4666 .LVL543: +1614:Middlewares/Third_Party/FatFs/src/ff.c **** } while (res == FR_OK); /* Next entry with table stretch enabled */ + 4667 .loc 1 1614 10 view .LVU1540 + 4668 001c FFF7FEFF bl dir_next + 4669 .LVL544: +1615:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4670 .loc 1 1615 16 is_stmt 1 view .LVU1541 + 4671 0020 0246 mov r2, r0 + 4672 0022 70B9 cbnz r0, .L348 + 4673 .LVL545: + ARM GAS /tmp/cc2SVLkL.s page 208 + + + 4674 .L350: +1602:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dp->sect); + 4675 .loc 1 1602 3 view .LVU1542 +1603:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 4676 .loc 1 1603 4 view .LVU1543 +1603:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 4677 .loc 1 1603 10 is_stmt 0 view .LVU1544 + 4678 0024 E169 ldr r1, [r4, #28] + 4679 0026 3846 mov r0, r7 + 4680 .LVL546: +1603:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 4681 .loc 1 1603 10 view .LVU1545 + 4682 0028 FFF7FEFF bl move_window + 4683 .LVL547: +1604:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 4684 .loc 1 1604 4 is_stmt 1 view .LVU1546 +1604:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 4685 .loc 1 1604 7 is_stmt 0 view .LVU1547 + 4686 002c 0246 mov r2, r0 + 4687 002e 40B9 cbnz r0, .L348 +1608:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 4688 .loc 1 1608 4 is_stmt 1 view .LVU1548 +1608:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 4689 .loc 1 1608 10 is_stmt 0 view .LVU1549 + 4690 0030 236A ldr r3, [r4, #32] +1608:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 4691 .loc 1 1608 15 view .LVU1550 + 4692 0032 1B78 ldrb r3, [r3] @ zero_extendqisi2 +1608:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 4693 .loc 1 1608 7 view .LVU1551 + 4694 0034 002B cmp r3, #0 + 4695 0036 18BF it ne + 4696 0038 E52B cmpne r3, #229 + 4697 003a ECD1 bne .L352 +1610:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 4698 .loc 1 1610 5 is_stmt 1 view .LVU1552 +1610:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 4699 .loc 1 1610 8 is_stmt 0 view .LVU1553 + 4700 003c 0135 adds r5, r5, #1 + 4701 .LVL548: +1610:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 4702 .loc 1 1610 8 view .LVU1554 + 4703 003e B542 cmp r5, r6 + 4704 0040 EAD1 bne .L349 + 4705 .LVL549: + 4706 .L348: +1618:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 4707 .loc 1 1618 2 is_stmt 1 view .LVU1555 +1618:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 4708 .loc 1 1618 5 is_stmt 0 view .LVU1556 + 4709 0042 042A cmp r2, #4 + 4710 0044 01D0 beq .L355 + 4711 .LVL550: + 4712 .L351: +1619:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4713 .loc 1 1619 2 is_stmt 1 view .LVU1557 +1620:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 209 + + + 4714 .loc 1 1620 1 is_stmt 0 view .LVU1558 + 4715 0046 1046 mov r0, r2 + 4716 0048 F8BD pop {r3, r4, r5, r6, r7, pc} + 4717 .LVL551: + 4718 .L355: +1618:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 4719 .loc 1 1618 29 discriminator 1 view .LVU1559 + 4720 004a 0722 movs r2, #7 + 4721 .LVL552: +1618:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 4722 .loc 1 1618 29 discriminator 1 view .LVU1560 + 4723 004c FBE7 b .L351 + 4724 .cfi_endproc + 4725 .LFE1207: + 4727 .section .text.dir_register,"ax",%progbits + 4728 .align 1 + 4729 .syntax unified + 4730 .thumb + 4731 .thumb_func + 4733 dir_register: + 4734 .LVL553: + 4735 .LFB1212: +2295:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 4736 .loc 1 2295 1 is_stmt 1 view -0 + 4737 .cfi_startproc + 4738 @ args = 0, pretend = 0, frame = 0 + 4739 @ frame_needed = 0, uses_anonymous_args = 0 +2295:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 4740 .loc 1 2295 1 is_stmt 0 view .LVU1562 + 4741 0000 70B5 push {r4, r5, r6, lr} + 4742 .LCFI35: + 4743 .cfi_def_cfa_offset 16 + 4744 .cfi_offset 4, -16 + 4745 .cfi_offset 5, -12 + 4746 .cfi_offset 6, -8 + 4747 .cfi_offset 14, -4 + 4748 0002 0446 mov r4, r0 +2296:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = dp->obj.fs; + 4749 .loc 1 2296 2 is_stmt 1 view .LVU1563 +2297:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 /* LFN configuration */ + 4750 .loc 1 2297 2 view .LVU1564 +2297:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 /* LFN configuration */ + 4751 .loc 1 2297 9 is_stmt 0 view .LVU1565 + 4752 0004 0668 ldr r6, [r0] + 4753 .LVL554: +2366:Middlewares/Third_Party/FatFs/src/ff.c **** + 4754 .loc 1 2366 2 is_stmt 1 view .LVU1566 +2366:Middlewares/Third_Party/FatFs/src/ff.c **** + 4755 .loc 1 2366 8 is_stmt 0 view .LVU1567 + 4756 0006 0121 movs r1, #1 + 4757 0008 FFF7FEFF bl dir_alloc + 4758 .LVL555: +2371:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dp->sect); + 4759 .loc 1 2371 2 is_stmt 1 view .LVU1568 +2371:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dp->sect); + 4760 .loc 1 2371 5 is_stmt 0 view .LVU1569 + 4761 000c 0546 mov r5, r0 + ARM GAS /tmp/cc2SVLkL.s page 210 + + + 4762 000e 08B1 cbz r0, .L359 + 4763 .LVL556: + 4764 .L357: +2383:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4765 .loc 1 2383 2 is_stmt 1 view .LVU1570 +2384:Middlewares/Third_Party/FatFs/src/ff.c **** + 4766 .loc 1 2384 1 is_stmt 0 view .LVU1571 + 4767 0010 2846 mov r0, r5 + 4768 0012 70BD pop {r4, r5, r6, pc} + 4769 .LVL557: + 4770 .L359: +2372:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 4771 .loc 1 2372 3 is_stmt 1 view .LVU1572 +2372:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 4772 .loc 1 2372 9 is_stmt 0 view .LVU1573 + 4773 0014 E169 ldr r1, [r4, #28] + 4774 0016 3046 mov r0, r6 + 4775 .LVL558: +2372:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 4776 .loc 1 2372 9 view .LVU1574 + 4777 0018 FFF7FEFF bl move_window + 4778 .LVL559: +2373:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(dp->dir, 0, SZDIRE); /* Clean the entry */ + 4779 .loc 1 2373 3 is_stmt 1 view .LVU1575 +2373:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(dp->dir, 0, SZDIRE); /* Clean the entry */ + 4780 .loc 1 2373 6 is_stmt 0 view .LVU1576 + 4781 001c 0546 mov r5, r0 + 4782 001e 0028 cmp r0, #0 + 4783 0020 F6D1 bne .L357 +2374:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(dp->dir + DIR_Name, dp->fn, 11); /* Put SFN */ + 4784 .loc 1 2374 4 is_stmt 1 view .LVU1577 + 4785 0022 2022 movs r2, #32 + 4786 0024 0021 movs r1, #0 + 4787 0026 206A ldr r0, [r4, #32] + 4788 .LVL560: +2374:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(dp->dir + DIR_Name, dp->fn, 11); /* Put SFN */ + 4789 .loc 1 2374 4 is_stmt 0 view .LVU1578 + 4790 0028 FFF7FEFF bl mem_set + 4791 .LVL561: +2375:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 + 4792 .loc 1 2375 4 is_stmt 1 view .LVU1579 + 4793 002c 0B22 movs r2, #11 + 4794 002e 04F12401 add r1, r4, #36 + 4795 0032 206A ldr r0, [r4, #32] + 4796 0034 FFF7FEFF bl mem_cpy + 4797 .LVL562: +2379:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4798 .loc 1 2379 4 view .LVU1580 +2379:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4799 .loc 1 2379 14 is_stmt 0 view .LVU1581 + 4800 0038 0123 movs r3, #1 + 4801 003a F370 strb r3, [r6, #3] + 4802 003c E8E7 b .L357 + 4803 .cfi_endproc + 4804 .LFE1212: + 4806 .section .text.dir_read,"ax",%progbits + 4807 .align 1 + ARM GAS /tmp/cc2SVLkL.s page 211 + + + 4808 .syntax unified + 4809 .thumb + 4810 .thumb_func + 4812 dir_read: + 4813 .LVL563: + 4814 .LFB1210: +2135:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res = FR_NO_FILE; + 4815 .loc 1 2135 1 is_stmt 1 view -0 + 4816 .cfi_startproc + 4817 @ args = 0, pretend = 0, frame = 0 + 4818 @ frame_needed = 0, uses_anonymous_args = 0 +2135:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res = FR_NO_FILE; + 4819 .loc 1 2135 1 is_stmt 0 view .LVU1583 + 4820 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 4821 .LCFI36: + 4822 .cfi_def_cfa_offset 24 + 4823 .cfi_offset 3, -24 + 4824 .cfi_offset 4, -20 + 4825 .cfi_offset 5, -16 + 4826 .cfi_offset 6, -12 + 4827 .cfi_offset 7, -8 + 4828 .cfi_offset 14, -4 + 4829 0002 0446 mov r4, r0 + 4830 0004 0E46 mov r6, r1 +2136:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = dp->obj.fs; + 4831 .loc 1 2136 2 is_stmt 1 view .LVU1584 + 4832 .LVL564: +2137:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE a, c; + 4833 .loc 1 2137 2 view .LVU1585 +2137:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE a, c; + 4834 .loc 1 2137 9 is_stmt 0 view .LVU1586 + 4835 0006 0568 ldr r5, [r0] + 4836 .LVL565: +2138:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 + 4837 .loc 1 2138 2 is_stmt 1 view .LVU1587 +2143:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dp->sect); + 4838 .loc 1 2143 2 view .LVU1588 +2136:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs = dp->obj.fs; + 4839 .loc 1 2136 10 is_stmt 0 view .LVU1589 + 4840 0008 0427 movs r7, #4 +2143:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dp->sect); + 4841 .loc 1 2143 8 view .LVU1590 + 4842 000a 05E0 b .L361 + 4843 .LVL566: + 4844 .L363: +2193:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 4845 .loc 1 2193 3 is_stmt 1 view .LVU1591 +2193:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 4846 .loc 1 2193 9 is_stmt 0 view .LVU1592 + 4847 000c 0021 movs r1, #0 + 4848 000e 2046 mov r0, r4 + 4849 .LVL567: +2193:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 4850 .loc 1 2193 9 view .LVU1593 + 4851 0010 FFF7FEFF bl dir_next + 4852 .LVL568: +2194:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 212 + + + 4853 .loc 1 2194 3 is_stmt 1 view .LVU1594 +2194:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4854 .loc 1 2194 6 is_stmt 0 view .LVU1595 + 4855 0014 0746 mov r7, r0 + 4856 0016 E8B9 cbnz r0, .L362 + 4857 .LVL569: + 4858 .L361: +2143:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dp->sect); + 4859 .loc 1 2143 9 is_stmt 1 view .LVU1596 +2143:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dp->sect); + 4860 .loc 1 2143 11 is_stmt 0 view .LVU1597 + 4861 0018 E169 ldr r1, [r4, #28] +2143:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dp->sect); + 4862 .loc 1 2143 9 view .LVU1598 + 4863 001a D9B1 cbz r1, .L362 +2144:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 4864 .loc 1 2144 3 is_stmt 1 view .LVU1599 +2144:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 4865 .loc 1 2144 9 is_stmt 0 view .LVU1600 + 4866 001c 2846 mov r0, r5 + 4867 001e FFF7FEFF bl move_window + 4868 .LVL570: +2145:Middlewares/Third_Party/FatFs/src/ff.c **** c = dp->dir[DIR_Name]; /* Test for the entry type */ + 4869 .loc 1 2145 3 is_stmt 1 view .LVU1601 +2145:Middlewares/Third_Party/FatFs/src/ff.c **** c = dp->dir[DIR_Name]; /* Test for the entry type */ + 4870 .loc 1 2145 6 is_stmt 0 view .LVU1602 + 4871 0022 0746 mov r7, r0 + 4872 0024 B0B9 cbnz r0, .L362 +2146:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == 0) { + 4873 .loc 1 2146 3 is_stmt 1 view .LVU1603 +2146:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == 0) { + 4874 .loc 1 2146 9 is_stmt 0 view .LVU1604 + 4875 0026 236A ldr r3, [r4, #32] +2146:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == 0) { + 4876 .loc 1 2146 5 view .LVU1605 + 4877 0028 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 4878 .LVL571: +2147:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_NO_FILE; break; /* Reached to end of the directory */ + 4879 .loc 1 2147 3 is_stmt 1 view .LVU1606 +2147:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_NO_FILE; break; /* Reached to end of the directory */ + 4880 .loc 1 2147 6 is_stmt 0 view .LVU1607 + 4881 002a 92B1 cbz r2, .L366 +2167:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 /* LFN configuration */ + 4882 .loc 1 2167 4 is_stmt 1 view .LVU1608 +2167:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 /* LFN configuration */ + 4883 .loc 1 2167 30 is_stmt 0 view .LVU1609 + 4884 002c DB7A ldrb r3, [r3, #11] @ zero_extendqisi2 +2167:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 /* LFN configuration */ + 4885 .loc 1 2167 21 view .LVU1610 + 4886 002e 03F03F03 and r3, r3, #63 + 4887 .LVL572: +2167:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_LFN != 0 /* LFN configuration */ + 4888 .loc 1 2167 17 view .LVU1611 + 4889 0032 A371 strb r3, [r4, #6] +2188:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 4890 .loc 1 2188 4 is_stmt 1 view .LVU1612 +2188:Middlewares/Third_Party/FatFs/src/ff.c **** break; + ARM GAS /tmp/cc2SVLkL.s page 213 + + + 4891 .loc 1 2188 7 is_stmt 0 view .LVU1613 + 4892 0034 E52A cmp r2, #229 + 4893 0036 18BF it ne + 4894 0038 2E2A cmpne r2, #46 + 4895 003a E7D0 beq .L363 +2188:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 4896 .loc 1 2188 30 discriminator 1 view .LVU1614 + 4897 003c 0F2B cmp r3, #15 + 4898 003e E5D0 beq .L363 +2188:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 4899 .loc 1 2188 57 discriminator 2 view .LVU1615 + 4900 0040 23F02003 bic r3, r3, #32 + 4901 .LVL573: +2188:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 4902 .loc 1 2188 48 discriminator 2 view .LVU1616 + 4903 0044 082B cmp r3, #8 + 4904 0046 14BF ite ne + 4905 0048 0023 movne r3, #0 + 4906 004a 0123 moveq r3, #1 +2188:Middlewares/Third_Party/FatFs/src/ff.c **** break; + 4907 .loc 1 2188 45 discriminator 2 view .LVU1617 + 4908 004c B342 cmp r3, r6 + 4909 004e DDD1 bne .L363 + 4910 0050 00E0 b .L362 + 4911 .LVL574: + 4912 .L366: +2148:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4913 .loc 1 2148 8 view .LVU1618 + 4914 0052 0427 movs r7, #4 + 4915 .LVL575: + 4916 .L362: +2197:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 4917 .loc 1 2197 2 is_stmt 1 view .LVU1619 +2197:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 4918 .loc 1 2197 5 is_stmt 0 view .LVU1620 + 4919 0054 0FB1 cbz r7, .L365 +2197:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 4920 .loc 1 2197 20 is_stmt 1 discriminator 1 view .LVU1621 +2197:Middlewares/Third_Party/FatFs/src/ff.c **** return res; + 4921 .loc 1 2197 29 is_stmt 0 discriminator 1 view .LVU1622 + 4922 0056 0023 movs r3, #0 + 4923 0058 E361 str r3, [r4, #28] + 4924 .L365: +2198:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4925 .loc 1 2198 2 is_stmt 1 view .LVU1623 +2199:Middlewares/Third_Party/FatFs/src/ff.c **** + 4926 .loc 1 2199 1 is_stmt 0 view .LVU1624 + 4927 005a 3846 mov r0, r7 + 4928 005c F8BD pop {r3, r4, r5, r6, r7, pc} +2199:Middlewares/Third_Party/FatFs/src/ff.c **** + 4929 .loc 1 2199 1 view .LVU1625 + 4930 .cfi_endproc + 4931 .LFE1210: + 4933 .section .text.sync_fs,"ax",%progbits + 4934 .align 1 + 4935 .syntax unified + 4936 .thumb + ARM GAS /tmp/cc2SVLkL.s page 214 + + + 4937 .thumb_func + 4939 sync_fs: + 4940 .LVL576: + 4941 .LFB1198: + 947:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 4942 .loc 1 947 1 is_stmt 1 view -0 + 4943 .cfi_startproc + 4944 @ args = 0, pretend = 0, frame = 0 + 4945 @ frame_needed = 0, uses_anonymous_args = 0 + 947:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 4946 .loc 1 947 1 is_stmt 0 view .LVU1627 + 4947 0000 70B5 push {r4, r5, r6, lr} + 4948 .LCFI37: + 4949 .cfi_def_cfa_offset 16 + 4950 .cfi_offset 4, -16 + 4951 .cfi_offset 5, -12 + 4952 .cfi_offset 6, -8 + 4953 .cfi_offset 14, -4 + 4954 0002 0446 mov r4, r0 + 948:Middlewares/Third_Party/FatFs/src/ff.c **** + 4955 .loc 1 948 2 is_stmt 1 view .LVU1628 + 951:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 4956 .loc 1 951 2 view .LVU1629 + 951:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 4957 .loc 1 951 8 is_stmt 0 view .LVU1630 + 4958 0004 FFF7FEFF bl sync_window + 4959 .LVL577: + 952:Middlewares/Third_Party/FatFs/src/ff.c **** /* Update FSInfo sector if needed */ + 4960 .loc 1 952 2 is_stmt 1 view .LVU1631 + 952:Middlewares/Third_Party/FatFs/src/ff.c **** /* Update FSInfo sector if needed */ + 4961 .loc 1 952 5 is_stmt 0 view .LVU1632 + 4962 0008 0546 mov r5, r0 + 4963 000a 48B9 cbnz r0, .L369 + 954:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create FSInfo structure */ + 4964 .loc 1 954 3 is_stmt 1 view .LVU1633 + 954:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create FSInfo structure */ + 4965 .loc 1 954 9 is_stmt 0 view .LVU1634 + 4966 000c 2378 ldrb r3, [r4] @ zero_extendqisi2 + 954:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create FSInfo structure */ + 4967 .loc 1 954 6 view .LVU1635 + 4968 000e 032B cmp r3, #3 + 4969 0010 08D0 beq .L373 + 4970 .LVL578: + 4971 .L370: + 968:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4972 .loc 1 968 3 is_stmt 1 view .LVU1636 + 968:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4973 .loc 1 968 7 is_stmt 0 view .LVU1637 + 4974 0012 0022 movs r2, #0 + 4975 0014 1146 mov r1, r2 + 4976 0016 6078 ldrb r0, [r4, #1] @ zero_extendqisi2 + 4977 0018 FFF7FEFF bl disk_ioctl + 4978 .LVL579: + 968:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4979 .loc 1 968 6 discriminator 1 view .LVU1638 + 4980 001c 00B1 cbz r0, .L369 + 968:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 215 + + + 4981 .loc 1 968 56 discriminator 1 view .LVU1639 + 4982 001e 0125 movs r5, #1 + 4983 .LVL580: + 4984 .L369: + 971:Middlewares/Third_Party/FatFs/src/ff.c **** } + 4985 .loc 1 971 2 is_stmt 1 view .LVU1640 + 972:Middlewares/Third_Party/FatFs/src/ff.c **** + 4986 .loc 1 972 1 is_stmt 0 view .LVU1641 + 4987 0020 2846 mov r0, r5 + 4988 0022 70BD pop {r4, r5, r6, pc} + 4989 .LVL581: + 4990 .L373: + 954:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create FSInfo structure */ + 4991 .loc 1 954 36 discriminator 1 view .LVU1642 + 4992 0024 2379 ldrb r3, [r4, #4] @ zero_extendqisi2 + 954:Middlewares/Third_Party/FatFs/src/ff.c **** /* Create FSInfo structure */ + 4993 .loc 1 954 31 discriminator 1 view .LVU1643 + 4994 0026 012B cmp r3, #1 + 4995 0028 F3D1 bne .L370 + 956:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(fs->win + BS_55AA, 0xAA55); + 4996 .loc 1 956 4 is_stmt 1 view .LVU1644 + 956:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(fs->win + BS_55AA, 0xAA55); + 4997 .loc 1 956 14 is_stmt 0 view .LVU1645 + 4998 002a 04F13406 add r6, r4, #52 + 956:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(fs->win + BS_55AA, 0xAA55); + 4999 .loc 1 956 4 view .LVU1646 + 5000 002e A289 ldrh r2, [r4, #12] + 5001 0030 0021 movs r1, #0 + 5002 0032 3046 mov r0, r6 + 5003 .LVL582: + 956:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(fs->win + BS_55AA, 0xAA55); + 5004 .loc 1 956 4 view .LVU1647 + 5005 0034 FFF7FEFF bl mem_set + 5006 .LVL583: + 957:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->win + FSI_LeadSig, 0x41615252); + 5007 .loc 1 957 4 is_stmt 1 view .LVU1648 + 5008 0038 4AF65521 movw r1, #43605 + 5009 003c 04F23220 addw r0, r4, #562 + 5010 0040 FFF7FEFF bl st_word + 5011 .LVL584: + 958:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->win + FSI_StrucSig, 0x61417272); + 5012 .loc 1 958 4 view .LVU1649 + 5013 0044 0E49 ldr r1, .L374 + 5014 0046 3046 mov r0, r6 + 5015 0048 FFF7FEFF bl st_dword + 5016 .LVL585: + 959:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->win + FSI_Free_Count, fs->free_clst); + 5017 .loc 1 959 4 view .LVU1650 + 5018 004c 0D49 ldr r1, .L374+4 + 5019 004e 04F50670 add r0, r4, #536 + 5020 0052 FFF7FEFF bl st_dword + 5021 .LVL586: + 960:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(fs->win + FSI_Nxt_Free, fs->last_clst); + 5022 .loc 1 960 4 view .LVU1651 + 5023 0056 6169 ldr r1, [r4, #20] + 5024 0058 04F50770 add r0, r4, #540 + 5025 005c FFF7FEFF bl st_dword + ARM GAS /tmp/cc2SVLkL.s page 216 + + + 5026 .LVL587: + 961:Middlewares/Third_Party/FatFs/src/ff.c **** /* Write it into the FSInfo sector */ + 5027 .loc 1 961 4 view .LVU1652 + 5028 0060 2169 ldr r1, [r4, #16] + 5029 0062 04F50870 add r0, r4, #544 + 5030 0066 FFF7FEFF bl st_dword + 5031 .LVL588: + 963:Middlewares/Third_Party/FatFs/src/ff.c **** disk_write(fs->drv, fs->win, fs->winsect, 1); + 5032 .loc 1 963 4 view .LVU1653 + 963:Middlewares/Third_Party/FatFs/src/ff.c **** disk_write(fs->drv, fs->win, fs->winsect, 1); + 5033 .loc 1 963 20 is_stmt 0 view .LVU1654 + 5034 006a 226A ldr r2, [r4, #32] + 963:Middlewares/Third_Party/FatFs/src/ff.c **** disk_write(fs->drv, fs->win, fs->winsect, 1); + 5035 .loc 1 963 30 view .LVU1655 + 5036 006c 0132 adds r2, r2, #1 + 963:Middlewares/Third_Party/FatFs/src/ff.c **** disk_write(fs->drv, fs->win, fs->winsect, 1); + 5037 .loc 1 963 16 view .LVU1656 + 5038 006e 2263 str r2, [r4, #48] + 964:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag = 0; + 5039 .loc 1 964 4 is_stmt 1 view .LVU1657 + 5040 0070 0123 movs r3, #1 + 5041 0072 3146 mov r1, r6 + 5042 0074 6078 ldrb r0, [r4, #1] @ zero_extendqisi2 + 5043 0076 FFF7FEFF bl disk_write + 5044 .LVL589: + 965:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5045 .loc 1 965 4 view .LVU1658 + 965:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5046 .loc 1 965 17 is_stmt 0 view .LVU1659 + 5047 007a 0023 movs r3, #0 + 5048 007c 2371 strb r3, [r4, #4] + 5049 007e C8E7 b .L370 + 5050 .L375: + 5051 .align 2 + 5052 .L374: + 5053 0080 52526141 .word 1096897106 + 5054 0084 72724161 .word 1631679090 + 5055 .cfi_endproc + 5056 .LFE1198: + 5058 .section .text.f_mount,"ax",%progbits + 5059 .align 1 + 5060 .global f_mount + 5061 .syntax unified + 5062 .thumb + 5063 .thumb_func + 5065 f_mount: + 5066 .LVL590: + 5067 .LFB1221: +3265:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *cfs; + 5068 .loc 1 3265 1 is_stmt 1 view -0 + 5069 .cfi_startproc + 5070 @ args = 0, pretend = 0, frame = 16 + 5071 @ frame_needed = 0, uses_anonymous_args = 0 +3265:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *cfs; + 5072 .loc 1 3265 1 is_stmt 0 view .LVU1661 + 5073 0000 70B5 push {r4, r5, r6, lr} + 5074 .LCFI38: + ARM GAS /tmp/cc2SVLkL.s page 217 + + + 5075 .cfi_def_cfa_offset 16 + 5076 .cfi_offset 4, -16 + 5077 .cfi_offset 5, -12 + 5078 .cfi_offset 6, -8 + 5079 .cfi_offset 14, -4 + 5080 0002 84B0 sub sp, sp, #16 + 5081 .LCFI39: + 5082 .cfi_def_cfa_offset 32 + 5083 0004 0190 str r0, [sp, #4] + 5084 0006 0091 str r1, [sp] + 5085 0008 1646 mov r6, r2 +3266:Middlewares/Third_Party/FatFs/src/ff.c **** int vol; + 5086 .loc 1 3266 2 is_stmt 1 view .LVU1662 +3267:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 5087 .loc 1 3267 2 view .LVU1663 +3268:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR *rp = path; + 5088 .loc 1 3268 2 view .LVU1664 +3269:Middlewares/Third_Party/FatFs/src/ff.c **** + 5089 .loc 1 3269 2 view .LVU1665 +3269:Middlewares/Third_Party/FatFs/src/ff.c **** + 5090 .loc 1 3269 15 is_stmt 0 view .LVU1666 + 5091 000a 0391 str r1, [sp, #12] +3273:Middlewares/Third_Party/FatFs/src/ff.c **** if (vol < 0) return FR_INVALID_DRIVE; + 5092 .loc 1 3273 2 is_stmt 1 view .LVU1667 +3273:Middlewares/Third_Party/FatFs/src/ff.c **** if (vol < 0) return FR_INVALID_DRIVE; + 5093 .loc 1 3273 8 is_stmt 0 view .LVU1668 + 5094 000c 03A8 add r0, sp, #12 + 5095 .LVL591: +3273:Middlewares/Third_Party/FatFs/src/ff.c **** if (vol < 0) return FR_INVALID_DRIVE; + 5096 .loc 1 3273 8 view .LVU1669 + 5097 000e FFF7FEFF bl get_ldnumber + 5098 .LVL592: +3274:Middlewares/Third_Party/FatFs/src/ff.c **** cfs = FatFs[vol]; /* Pointer to fs object */ + 5099 .loc 1 3274 2 is_stmt 1 view .LVU1670 +3274:Middlewares/Third_Party/FatFs/src/ff.c **** cfs = FatFs[vol]; /* Pointer to fs object */ + 5100 .loc 1 3274 5 is_stmt 0 view .LVU1671 + 5101 0012 041E subs r4, r0, #0 + 5102 0014 20DB blt .L380 +3275:Middlewares/Third_Party/FatFs/src/ff.c **** + 5103 .loc 1 3275 2 is_stmt 1 view .LVU1672 +3275:Middlewares/Third_Party/FatFs/src/ff.c **** + 5104 .loc 1 3275 6 is_stmt 0 view .LVU1673 + 5105 0016 114B ldr r3, .L384 + 5106 0018 53F82450 ldr r5, [r3, r4, lsl #2] + 5107 .LVL593: +3277:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 5108 .loc 1 3277 2 is_stmt 1 view .LVU1674 +3277:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 5109 .loc 1 3277 5 is_stmt 0 view .LVU1675 + 5110 001c 25B1 cbz r5, .L378 +3279:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5111 .loc 1 3279 3 is_stmt 1 view .LVU1676 + 5112 001e 2846 mov r0, r5 + 5113 .LVL594: +3279:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5114 .loc 1 3279 3 is_stmt 0 view .LVU1677 + 5115 0020 FFF7FEFF bl clear_lock + ARM GAS /tmp/cc2SVLkL.s page 218 + + + 5116 .LVL595: +3284:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5117 .loc 1 3284 3 is_stmt 1 view .LVU1678 +3284:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5118 .loc 1 3284 16 is_stmt 0 view .LVU1679 + 5119 0024 0023 movs r3, #0 + 5120 0026 2B70 strb r3, [r5] + 5121 .L378: +3287:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fs_type = 0; /* Clear new fs object */ + 5122 .loc 1 3287 2 is_stmt 1 view .LVU1680 +3287:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fs_type = 0; /* Clear new fs object */ + 5123 .loc 1 3287 6 is_stmt 0 view .LVU1681 + 5124 0028 019B ldr r3, [sp, #4] +3287:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fs_type = 0; /* Clear new fs object */ + 5125 .loc 1 3287 5 view .LVU1682 + 5126 002a 0BB1 cbz r3, .L379 +3288:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT /* Create sync object for the new volume */ + 5127 .loc 1 3288 3 is_stmt 1 view .LVU1683 +3288:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_REENTRANT /* Create sync object for the new volume */ + 5128 .loc 1 3288 15 is_stmt 0 view .LVU1684 + 5129 002c 0022 movs r2, #0 + 5130 002e 1A70 strb r2, [r3] + 5131 .L379: +3293:Middlewares/Third_Party/FatFs/src/ff.c **** + 5132 .loc 1 3293 2 is_stmt 1 view .LVU1685 +3293:Middlewares/Third_Party/FatFs/src/ff.c **** + 5133 .loc 1 3293 13 is_stmt 0 view .LVU1686 + 5134 0030 019B ldr r3, [sp, #4] + 5135 0032 0A4A ldr r2, .L384 + 5136 0034 42F82430 str r3, [r2, r4, lsl #2] +3295:Middlewares/Third_Party/FatFs/src/ff.c **** + 5137 .loc 1 3295 2 is_stmt 1 view .LVU1687 +3295:Middlewares/Third_Party/FatFs/src/ff.c **** + 5138 .loc 1 3295 17 is_stmt 0 view .LVU1688 + 5139 0038 721E subs r2, r6, #1 + 5140 003a 18BF it ne + 5141 003c 0122 movne r2, #1 +3295:Middlewares/Third_Party/FatFs/src/ff.c **** + 5142 .loc 1 3295 10 view .LVU1689 + 5143 003e 002B cmp r3, #0 + 5144 0040 08BF it eq + 5145 0042 42F00102 orreq r2, r2, #1 +3295:Middlewares/Third_Party/FatFs/src/ff.c **** + 5146 .loc 1 3295 5 view .LVU1690 + 5147 0046 12B1 cbz r2, .L383 +3295:Middlewares/Third_Party/FatFs/src/ff.c **** + 5148 .loc 1 3295 30 discriminator 1 view .LVU1691 + 5149 0048 0020 movs r0, #0 + 5150 .LVL596: + 5151 .L377: +3299:Middlewares/Third_Party/FatFs/src/ff.c **** + 5152 .loc 1 3299 1 view .LVU1692 + 5153 004a 04B0 add sp, sp, #16 + 5154 .LCFI40: + 5155 .cfi_remember_state + 5156 .cfi_def_cfa_offset 16 + 5157 @ sp needed + ARM GAS /tmp/cc2SVLkL.s page 219 + + + 5158 004c 70BD pop {r4, r5, r6, pc} + 5159 .LVL597: + 5160 .L383: + 5161 .LCFI41: + 5162 .cfi_restore_state +3297:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); + 5163 .loc 1 3297 2 is_stmt 1 view .LVU1693 +3297:Middlewares/Third_Party/FatFs/src/ff.c **** LEAVE_FF(fs, res); + 5164 .loc 1 3297 8 is_stmt 0 view .LVU1694 + 5165 004e 01A9 add r1, sp, #4 + 5166 0050 6846 mov r0, sp + 5167 0052 FFF7FEFF bl find_volume + 5168 .LVL598: +3298:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5169 .loc 1 3298 2 is_stmt 1 view .LVU1695 + 5170 0056 F8E7 b .L377 + 5171 .LVL599: + 5172 .L380: +3274:Middlewares/Third_Party/FatFs/src/ff.c **** cfs = FatFs[vol]; /* Pointer to fs object */ + 5173 .loc 1 3274 22 is_stmt 0 discriminator 1 view .LVU1696 + 5174 0058 0B20 movs r0, #11 + 5175 .LVL600: +3274:Middlewares/Third_Party/FatFs/src/ff.c **** cfs = FatFs[vol]; /* Pointer to fs object */ + 5176 .loc 1 3274 22 discriminator 1 view .LVU1697 + 5177 005a F6E7 b .L377 + 5178 .L385: + 5179 .align 2 + 5180 .L384: + 5181 005c 00000000 .word FatFs + 5182 .cfi_endproc + 5183 .LFE1221: + 5185 .section .text.f_open,"ax",%progbits + 5186 .align 1 + 5187 .global f_open + 5188 .syntax unified + 5189 .thumb + 5190 .thumb_func + 5192 f_open: + 5193 .LVL601: + 5194 .LFB1222: +3313:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 5195 .loc 1 3313 1 is_stmt 1 view -0 + 5196 .cfi_startproc + 5197 @ args = 0, pretend = 0, frame = 64 + 5198 @ frame_needed = 0, uses_anonymous_args = 0 +3313:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 5199 .loc 1 3313 1 is_stmt 0 view .LVU1699 + 5200 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 5201 .LCFI42: + 5202 .cfi_def_cfa_offset 28 + 5203 .cfi_offset 4, -28 + 5204 .cfi_offset 5, -24 + 5205 .cfi_offset 6, -20 + 5206 .cfi_offset 7, -16 + 5207 .cfi_offset 8, -12 + 5208 .cfi_offset 9, -8 + 5209 .cfi_offset 14, -4 + ARM GAS /tmp/cc2SVLkL.s page 220 + + + 5210 0004 91B0 sub sp, sp, #68 + 5211 .LCFI43: + 5212 .cfi_def_cfa_offset 96 + 5213 0006 0191 str r1, [sp, #4] +3314:Middlewares/Third_Party/FatFs/src/ff.c **** DIR dj; + 5214 .loc 1 3314 2 is_stmt 1 view .LVU1700 +3315:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; + 5215 .loc 1 3315 2 view .LVU1701 +3316:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 5216 .loc 1 3316 2 view .LVU1702 +3318:Middlewares/Third_Party/FatFs/src/ff.c **** FSIZE_t ofs; + 5217 .loc 1 3318 2 view .LVU1703 +3319:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5218 .loc 1 3319 2 view .LVU1704 +3324:Middlewares/Third_Party/FatFs/src/ff.c **** + 5219 .loc 1 3324 2 view .LVU1705 +3324:Middlewares/Third_Party/FatFs/src/ff.c **** + 5220 .loc 1 3324 5 is_stmt 0 view .LVU1706 + 5221 0008 0028 cmp r0, #0 + 5222 000a 00F01081 beq .L401 + 5223 000e 1446 mov r4, r2 + 5224 0010 0646 mov r6, r0 +3327:Middlewares/Third_Party/FatFs/src/ff.c **** res = find_volume(&path, &fs, mode); + 5225 .loc 1 3327 2 is_stmt 1 view .LVU1707 +3327:Middlewares/Third_Party/FatFs/src/ff.c **** res = find_volume(&path, &fs, mode); + 5226 .loc 1 3327 7 is_stmt 0 view .LVU1708 + 5227 0012 02F03F07 and r7, r2, #63 + 5228 .LVL602: +3328:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 5229 .loc 1 3328 2 is_stmt 1 view .LVU1709 +3328:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 5230 .loc 1 3328 8 is_stmt 0 view .LVU1710 + 5231 0016 3A46 mov r2, r7 + 5232 0018 03A9 add r1, sp, #12 + 5233 .LVL603: +3328:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 5234 .loc 1 3328 8 view .LVU1711 + 5235 001a 01A8 add r0, sp, #4 + 5236 .LVL604: +3328:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 5237 .loc 1 3328 8 view .LVU1712 + 5238 001c FFF7FEFF bl find_volume + 5239 .LVL605: +3329:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.fs = fs; + 5240 .loc 1 3329 2 is_stmt 1 view .LVU1713 +3329:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.fs = fs; + 5241 .loc 1 3329 5 is_stmt 0 view .LVU1714 + 5242 0020 0546 mov r5, r0 + 5243 0022 28B1 cbz r0, .L415 + 5244 .LVL606: + 5245 .L388: +3499:Middlewares/Third_Party/FatFs/src/ff.c **** + 5246 .loc 1 3499 20 is_stmt 1 discriminator 1 view .LVU1715 +3499:Middlewares/Third_Party/FatFs/src/ff.c **** + 5247 .loc 1 3499 31 is_stmt 0 discriminator 1 view .LVU1716 + 5248 0024 0023 movs r3, #0 + 5249 0026 3360 str r3, [r6] + ARM GAS /tmp/cc2SVLkL.s page 221 + + + 5250 .LVL607: + 5251 .L387: +3502:Middlewares/Third_Party/FatFs/src/ff.c **** + 5252 .loc 1 3502 1 view .LVU1717 + 5253 0028 2846 mov r0, r5 + 5254 002a 11B0 add sp, sp, #68 + 5255 .LCFI44: + 5256 .cfi_remember_state + 5257 .cfi_def_cfa_offset 28 + 5258 @ sp needed + 5259 002c BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} + 5260 .LVL608: + 5261 .L415: + 5262 .LCFI45: + 5263 .cfi_restore_state +3330:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); + 5264 .loc 1 3330 3 is_stmt 1 view .LVU1718 +3330:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); + 5265 .loc 1 3330 13 is_stmt 0 view .LVU1719 + 5266 0030 039B ldr r3, [sp, #12] + 5267 0032 0493 str r3, [sp, #16] +3331:Middlewares/Third_Party/FatFs/src/ff.c **** res = follow_path(&dj, path); /* Follow the file path */ + 5268 .loc 1 3331 18 is_stmt 1 view .LVU1720 +3332:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY /* R/W configuration */ + 5269 .loc 1 3332 3 view .LVU1721 +3332:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY /* R/W configuration */ + 5270 .loc 1 3332 9 is_stmt 0 view .LVU1722 + 5271 0034 0199 ldr r1, [sp, #4] + 5272 0036 04A8 add r0, sp, #16 + 5273 .LVL609: +3332:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY /* R/W configuration */ + 5274 .loc 1 3332 9 view .LVU1723 + 5275 0038 FFF7FEFF bl follow_path + 5276 .LVL610: +3334:Middlewares/Third_Party/FatFs/src/ff.c **** if (dj.fn[NSFLAG] & NS_NONAME) { /* Origin directory itself? */ + 5277 .loc 1 3334 3 is_stmt 1 view .LVU1724 +3334:Middlewares/Third_Party/FatFs/src/ff.c **** if (dj.fn[NSFLAG] & NS_NONAME) { /* Origin directory itself? */ + 5278 .loc 1 3334 6 is_stmt 0 view .LVU1725 + 5279 003c 0546 mov r5, r0 + 5280 003e 60B9 cbnz r0, .L389 +3335:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INVALID_NAME; + 5281 .loc 1 3335 4 is_stmt 1 view .LVU1726 +3335:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INVALID_NAME; + 5282 .loc 1 3335 8 is_stmt 0 view .LVU1727 + 5283 0040 9DF93F30 ldrsb r3, [sp, #63] +3335:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INVALID_NAME; + 5284 .loc 1 3335 7 view .LVU1728 + 5285 0044 002B cmp r3, #0 + 5286 0046 52DB blt .L402 +3340:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5287 .loc 1 3340 5 is_stmt 1 view .LVU1729 +3340:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5288 .loc 1 3340 11 is_stmt 0 view .LVU1730 + 5289 0048 14F03E0F tst r4, #62 + 5290 004c 14BF ite ne + 5291 004e 0121 movne r1, #1 + 5292 0050 0021 moveq r1, #0 + ARM GAS /tmp/cc2SVLkL.s page 222 + + + 5293 0052 04A8 add r0, sp, #16 + 5294 .LVL611: +3340:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5295 .loc 1 3340 11 view .LVU1731 + 5296 0054 FFF7FEFF bl chk_lock + 5297 .LVL612: + 5298 0058 0546 mov r5, r0 + 5299 .LVL613: + 5300 .L389: +3345:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) { /* No file, create new */ + 5301 .loc 1 3345 3 is_stmt 1 view .LVU1732 +3345:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) { /* No file, create new */ + 5302 .loc 1 3345 6 is_stmt 0 view .LVU1733 + 5303 005a 14F01C0F tst r4, #28 + 5304 005e 5CD0 beq .L390 +3346:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) { /* There is no file to open, create a new entry */ + 5305 .loc 1 3346 4 is_stmt 1 view .LVU1734 +3346:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) { /* There is no file to open, create a new entry */ + 5306 .loc 1 3346 7 is_stmt 0 view .LVU1735 + 5307 0060 002D cmp r5, #0 + 5308 0062 50D0 beq .L391 +3347:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 5309 .loc 1 3347 5 is_stmt 1 view .LVU1736 +3347:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 5310 .loc 1 3347 8 is_stmt 0 view .LVU1737 + 5311 0064 042D cmp r5, #4 + 5312 0066 44D0 beq .L416 + 5313 .LVL614: + 5314 .L392: +3354:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5315 .loc 1 3354 5 is_stmt 1 view .LVU1738 +3354:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5316 .loc 1 3354 10 is_stmt 0 view .LVU1739 + 5317 0068 47F00807 orr r7, r7, #8 + 5318 .LVL615: + 5319 .L393: +3363:Middlewares/Third_Party/FatFs/src/ff.c **** dw = GET_FATTIME(); + 5320 .loc 1 3363 4 is_stmt 1 view .LVU1740 +3363:Middlewares/Third_Party/FatFs/src/ff.c **** dw = GET_FATTIME(); + 5321 .loc 1 3363 7 is_stmt 0 view .LVU1741 + 5322 006c 002D cmp r5, #0 + 5323 006e D9D1 bne .L388 +3363:Middlewares/Third_Party/FatFs/src/ff.c **** dw = GET_FATTIME(); + 5324 .loc 1 3363 21 discriminator 1 view .LVU1742 + 5325 0070 17F0080F tst r7, #8 + 5326 0074 61D0 beq .L394 +3364:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 5327 .loc 1 3364 5 is_stmt 1 view .LVU1743 +3364:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 5328 .loc 1 3364 10 is_stmt 0 view .LVU1744 + 5329 0076 FFF7FEFF bl get_fattime + 5330 .LVL616: + 5331 007a 0446 mov r4, r0 + 5332 .LVL617: +3392:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(dj.dir + DIR_ModTime, dw); /* Set modified time */ + 5333 .loc 1 3392 6 is_stmt 1 view .LVU1745 + 5334 007c 0146 mov r1, r0 + ARM GAS /tmp/cc2SVLkL.s page 223 + + + 5335 007e 0C98 ldr r0, [sp, #48] + 5336 .LVL618: +3392:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(dj.dir + DIR_ModTime, dw); /* Set modified time */ + 5337 .loc 1 3392 6 is_stmt 0 view .LVU1746 + 5338 0080 0E30 adds r0, r0, #14 + 5339 0082 FFF7FEFF bl st_dword + 5340 .LVL619: +3393:Middlewares/Third_Party/FatFs/src/ff.c **** dj.dir[DIR_Attr] = AM_ARC; /* Reset attribute */ + 5341 .loc 1 3393 6 is_stmt 1 view .LVU1747 + 5342 0086 2146 mov r1, r4 + 5343 0088 0C98 ldr r0, [sp, #48] + 5344 008a 1630 adds r0, r0, #22 + 5345 008c FFF7FEFF bl st_dword + 5346 .LVL620: +3394:Middlewares/Third_Party/FatFs/src/ff.c **** cl = ld_clust(fs, dj.dir); /* Get cluster chain */ + 5347 .loc 1 3394 6 view .LVU1748 +3394:Middlewares/Third_Party/FatFs/src/ff.c **** cl = ld_clust(fs, dj.dir); /* Get cluster chain */ + 5348 .loc 1 3394 23 is_stmt 0 view .LVU1749 + 5349 0090 0C9B ldr r3, [sp, #48] + 5350 0092 2022 movs r2, #32 + 5351 0094 DA72 strb r2, [r3, #11] +3395:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dj.dir, 0); /* Reset file allocation info */ + 5352 .loc 1 3395 6 is_stmt 1 view .LVU1750 +3395:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dj.dir, 0); /* Reset file allocation info */ + 5353 .loc 1 3395 11 is_stmt 0 view .LVU1751 + 5354 0096 DDF80C80 ldr r8, [sp, #12] +3395:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dj.dir, 0); /* Reset file allocation info */ + 5355 .loc 1 3395 26 view .LVU1752 + 5356 009a DDF83090 ldr r9, [sp, #48] +3395:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dj.dir, 0); /* Reset file allocation info */ + 5357 .loc 1 3395 11 view .LVU1753 + 5358 009e 4946 mov r1, r9 + 5359 00a0 4046 mov r0, r8 + 5360 00a2 FFF7FEFF bl ld_clust + 5361 .LVL621: + 5362 00a6 0446 mov r4, r0 + 5363 .LVL622: +3396:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(dj.dir + DIR_FileSize, 0); + 5364 .loc 1 3396 6 is_stmt 1 view .LVU1754 + 5365 00a8 0022 movs r2, #0 + 5366 00aa 4946 mov r1, r9 + 5367 00ac 4046 mov r0, r8 + 5368 .LVL623: +3396:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(dj.dir + DIR_FileSize, 0); + 5369 .loc 1 3396 6 is_stmt 0 view .LVU1755 + 5370 00ae FFF7FEFF bl st_clust + 5371 .LVL624: +3397:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 5372 .loc 1 3397 6 is_stmt 1 view .LVU1756 + 5373 00b2 0021 movs r1, #0 + 5374 00b4 0C98 ldr r0, [sp, #48] + 5375 00b6 1C30 adds r0, r0, #28 + 5376 00b8 FFF7FEFF bl st_dword + 5377 .LVL625: +3398:Middlewares/Third_Party/FatFs/src/ff.c **** + 5378 .loc 1 3398 6 view .LVU1757 +3398:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 224 + + + 5379 .loc 1 3398 16 is_stmt 0 view .LVU1758 + 5380 00bc 039B ldr r3, [sp, #12] + 5381 00be 0122 movs r2, #1 + 5382 00c0 DA70 strb r2, [r3, #3] +3400:Middlewares/Third_Party/FatFs/src/ff.c **** dw = fs->winsect; + 5383 .loc 1 3400 6 is_stmt 1 view .LVU1759 +3400:Middlewares/Third_Party/FatFs/src/ff.c **** dw = fs->winsect; + 5384 .loc 1 3400 9 is_stmt 0 view .LVU1760 + 5385 00c2 002C cmp r4, #0 + 5386 00c4 39D0 beq .L394 +3401:Middlewares/Third_Party/FatFs/src/ff.c **** res = remove_chain(&dj.obj, cl, 0); + 5387 .loc 1 3401 7 is_stmt 1 view .LVU1761 +3401:Middlewares/Third_Party/FatFs/src/ff.c **** res = remove_chain(&dj.obj, cl, 0); + 5388 .loc 1 3401 14 is_stmt 0 view .LVU1762 + 5389 00c6 039B ldr r3, [sp, #12] +3401:Middlewares/Third_Party/FatFs/src/ff.c **** res = remove_chain(&dj.obj, cl, 0); + 5390 .loc 1 3401 10 view .LVU1763 + 5391 00c8 D3F83080 ldr r8, [r3, #48] + 5392 .LVL626: +3402:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 5393 .loc 1 3402 7 is_stmt 1 view .LVU1764 +3402:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 5394 .loc 1 3402 13 is_stmt 0 view .LVU1765 + 5395 00cc 0022 movs r2, #0 + 5396 00ce 2146 mov r1, r4 + 5397 00d0 04A8 add r0, sp, #16 + 5398 00d2 FFF7FEFF bl remove_chain + 5399 .LVL627: +3403:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dw); + 5400 .loc 1 3403 7 is_stmt 1 view .LVU1766 +3403:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, dw); + 5401 .loc 1 3403 10 is_stmt 0 view .LVU1767 + 5402 00d6 0546 mov r5, r0 + 5403 00d8 0028 cmp r0, #0 + 5404 00da A3D1 bne .L388 +3404:Middlewares/Third_Party/FatFs/src/ff.c **** fs->last_clst = cl - 1; /* Reuse the cluster hole */ + 5405 .loc 1 3404 8 is_stmt 1 view .LVU1768 +3404:Middlewares/Third_Party/FatFs/src/ff.c **** fs->last_clst = cl - 1; /* Reuse the cluster hole */ + 5406 .loc 1 3404 14 is_stmt 0 view .LVU1769 + 5407 00dc 4146 mov r1, r8 + 5408 00de 0398 ldr r0, [sp, #12] + 5409 .LVL628: +3404:Middlewares/Third_Party/FatFs/src/ff.c **** fs->last_clst = cl - 1; /* Reuse the cluster hole */ + 5410 .loc 1 3404 14 view .LVU1770 + 5411 00e0 FFF7FEFF bl move_window + 5412 .LVL629: + 5413 00e4 0546 mov r5, r0 + 5414 .LVL630: +3405:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5415 .loc 1 3405 8 is_stmt 1 view .LVU1771 +3405:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5416 .loc 1 3405 27 is_stmt 0 view .LVU1772 + 5417 00e6 013C subs r4, r4, #1 + 5418 .LVL631: +3405:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5419 .loc 1 3405 22 view .LVU1773 + 5420 00e8 039B ldr r3, [sp, #12] + ARM GAS /tmp/cc2SVLkL.s page 225 + + + 5421 00ea 1C61 str r4, [r3, #16] + 5422 00ec 25E0 b .L394 + 5423 .LVL632: + 5424 .L402: +3336:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5425 .loc 1 3336 9 view .LVU1774 + 5426 00ee 0625 movs r5, #6 + 5427 00f0 B3E7 b .L389 + 5428 .LVL633: + 5429 .L416: +3349:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 5430 .loc 1 3349 6 is_stmt 1 view .LVU1775 +3349:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 5431 .loc 1 3349 12 is_stmt 0 view .LVU1776 + 5432 00f2 FFF7FEFF bl enq_lock + 5433 .LVL634: +3349:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 5434 .loc 1 3349 43 discriminator 1 view .LVU1777 + 5435 00f6 08B9 cbnz r0, .L417 +3349:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 5436 .loc 1 3349 43 discriminator 2 view .LVU1778 + 5437 00f8 1225 movs r5, #18 + 5438 .LVL635: +3349:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 5439 .loc 1 3349 43 discriminator 2 view .LVU1779 + 5440 00fa B5E7 b .L392 + 5441 .LVL636: + 5442 .L417: +3349:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 5443 .loc 1 3349 25 discriminator 1 view .LVU1780 + 5444 00fc 04A8 add r0, sp, #16 + 5445 00fe FFF7FEFF bl dir_register + 5446 .LVL637: + 5447 0102 0546 mov r5, r0 + 5448 .LVL638: +3349:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 5449 .loc 1 3349 25 discriminator 1 view .LVU1781 + 5450 0104 B0E7 b .L392 + 5451 .LVL639: + 5452 .L391: +3357:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DENIED; + 5453 .loc 1 3357 5 is_stmt 1 view .LVU1782 +3357:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DENIED; + 5454 .loc 1 3357 15 is_stmt 0 view .LVU1783 + 5455 0106 9DF81630 ldrb r3, [sp, #22] @ zero_extendqisi2 +3357:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DENIED; + 5456 .loc 1 3357 8 view .LVU1784 + 5457 010a 13F0110F tst r3, #17 + 5458 010e 13D1 bne .L404 +3360:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5459 .loc 1 3360 6 is_stmt 1 view .LVU1785 +3360:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5460 .loc 1 3360 9 is_stmt 0 view .LVU1786 + 5461 0110 14F0040F tst r4, #4 + 5462 0114 AAD0 beq .L393 +3360:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5463 .loc 1 3360 36 discriminator 1 view .LVU1787 + ARM GAS /tmp/cc2SVLkL.s page 226 + + + 5464 0116 0825 movs r5, #8 + 5465 .LVL640: +3360:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5466 .loc 1 3360 36 discriminator 1 view .LVU1788 + 5467 0118 84E7 b .L388 + 5468 .LVL641: + 5469 .L390: +3412:Middlewares/Third_Party/FatFs/src/ff.c **** if (dj.obj.attr & AM_DIR) { /* It is a directory */ + 5470 .loc 1 3412 4 is_stmt 1 view .LVU1789 +3412:Middlewares/Third_Party/FatFs/src/ff.c **** if (dj.obj.attr & AM_DIR) { /* It is a directory */ + 5471 .loc 1 3412 7 is_stmt 0 view .LVU1790 + 5472 011a 002D cmp r5, #0 + 5473 011c 82D1 bne .L388 +3413:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_NO_FILE; + 5474 .loc 1 3413 5 is_stmt 1 view .LVU1791 +3413:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_NO_FILE; + 5475 .loc 1 3413 15 is_stmt 0 view .LVU1792 + 5476 011e 9DF81630 ldrb r3, [sp, #22] @ zero_extendqisi2 +3413:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_NO_FILE; + 5477 .loc 1 3413 8 view .LVU1793 + 5478 0122 13F0100F tst r3, #16 + 5479 0126 7ED1 bne .L406 +3416:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DENIED; + 5480 .loc 1 3416 6 is_stmt 1 view .LVU1794 +3416:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DENIED; + 5481 .loc 1 3416 9 is_stmt 0 view .LVU1795 + 5482 0128 14F0020F tst r4, #2 + 5483 012c 05D0 beq .L394 +3416:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DENIED; + 5484 .loc 1 3416 28 discriminator 1 view .LVU1796 + 5485 012e 13F0010F tst r3, #1 + 5486 0132 02D0 beq .L394 +3417:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5487 .loc 1 3417 11 view .LVU1797 + 5488 0134 0725 movs r5, #7 + 5489 .LVL642: +3417:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5490 .loc 1 3417 11 view .LVU1798 + 5491 0136 75E7 b .L388 + 5492 .LVL643: + 5493 .L404: +3358:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 5494 .loc 1 3358 10 view .LVU1799 + 5495 0138 0725 movs r5, #7 + 5496 .LVL644: + 5497 .L394: +3422:Middlewares/Third_Party/FatFs/src/ff.c **** if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */ + 5498 .loc 1 3422 3 is_stmt 1 view .LVU1800 +3422:Middlewares/Third_Party/FatFs/src/ff.c **** if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */ + 5499 .loc 1 3422 6 is_stmt 0 view .LVU1801 + 5500 013a 002D cmp r5, #0 + 5501 013c 7FF472AF bne .L388 +3423:Middlewares/Third_Party/FatFs/src/ff.c **** mode |= FA_MODIFIED; + 5502 .loc 1 3423 4 is_stmt 1 view .LVU1802 +3423:Middlewares/Third_Party/FatFs/src/ff.c **** mode |= FA_MODIFIED; + 5503 .loc 1 3423 7 is_stmt 0 view .LVU1803 + 5504 0140 17F0080F tst r7, #8 + ARM GAS /tmp/cc2SVLkL.s page 227 + + + 5505 0144 01D0 beq .L395 +3424:Middlewares/Third_Party/FatFs/src/ff.c **** fp->dir_sect = fs->winsect; /* Pointer to the directory entry */ + 5506 .loc 1 3424 5 is_stmt 1 view .LVU1804 +3424:Middlewares/Third_Party/FatFs/src/ff.c **** fp->dir_sect = fs->winsect; /* Pointer to the directory entry */ + 5507 .loc 1 3424 10 is_stmt 0 view .LVU1805 + 5508 0146 47F04007 orr r7, r7, #64 + 5509 .LVL645: + 5510 .L395: +3425:Middlewares/Third_Party/FatFs/src/ff.c **** fp->dir_ptr = dj.dir; + 5511 .loc 1 3425 4 is_stmt 1 view .LVU1806 +3425:Middlewares/Third_Party/FatFs/src/ff.c **** fp->dir_ptr = dj.dir; + 5512 .loc 1 3425 21 is_stmt 0 view .LVU1807 + 5513 014a 039B ldr r3, [sp, #12] + 5514 014c 1B6B ldr r3, [r3, #48] +3425:Middlewares/Third_Party/FatFs/src/ff.c **** fp->dir_ptr = dj.dir; + 5515 .loc 1 3425 17 view .LVU1808 + 5516 014e 7362 str r3, [r6, #36] +3426:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 5517 .loc 1 3426 4 is_stmt 1 view .LVU1809 +3426:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 5518 .loc 1 3426 20 is_stmt 0 view .LVU1810 + 5519 0150 0C9B ldr r3, [sp, #48] +3426:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 5520 .loc 1 3426 16 view .LVU1811 + 5521 0152 B362 str r3, [r6, #40] +3428:Middlewares/Third_Party/FatFs/src/ff.c **** if (!fp->obj.lockid) res = FR_INT_ERR; + 5522 .loc 1 3428 4 is_stmt 1 view .LVU1812 +3428:Middlewares/Third_Party/FatFs/src/ff.c **** if (!fp->obj.lockid) res = FR_INT_ERR; + 5523 .loc 1 3428 21 is_stmt 0 view .LVU1813 + 5524 0154 012F cmp r7, #1 + 5525 0156 94BF ite ls + 5526 0158 0021 movls r1, #0 + 5527 015a 0121 movhi r1, #1 + 5528 015c 04A8 add r0, sp, #16 + 5529 015e FFF7FEFF bl inc_lock + 5530 .LVL646: +3428:Middlewares/Third_Party/FatFs/src/ff.c **** if (!fp->obj.lockid) res = FR_INT_ERR; + 5531 .loc 1 3428 19 discriminator 1 view .LVU1814 + 5532 0162 3061 str r0, [r6, #16] +3429:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5533 .loc 1 3429 4 is_stmt 1 view .LVU1815 +3429:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5534 .loc 1 3429 7 is_stmt 0 view .LVU1816 + 5535 0164 08B9 cbnz r0, .L418 +3429:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5536 .loc 1 3429 29 discriminator 1 view .LVU1817 + 5537 0166 0225 movs r5, #2 + 5538 .LVL647: +3429:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5539 .loc 1 3429 29 discriminator 1 view .LVU1818 + 5540 0168 5CE7 b .L388 + 5541 .LVL648: + 5542 .L418: +3444:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 5543 .loc 1 3444 3 is_stmt 1 view .LVU1819 +3456:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize); + 5544 .loc 1 3456 5 view .LVU1820 + ARM GAS /tmp/cc2SVLkL.s page 228 + + +3456:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize); + 5545 .loc 1 3456 22 is_stmt 0 view .LVU1821 + 5546 016a 039C ldr r4, [sp, #12] +3456:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize); + 5547 .loc 1 3456 37 view .LVU1822 + 5548 016c DDF83080 ldr r8, [sp, #48] +3456:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize); + 5549 .loc 1 3456 22 view .LVU1823 + 5550 0170 4146 mov r1, r8 + 5551 0172 2046 mov r0, r4 + 5552 0174 FFF7FEFF bl ld_clust + 5553 .LVL649: +3456:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize); + 5554 .loc 1 3456 20 discriminator 1 view .LVU1824 + 5555 0178 B060 str r0, [r6, #8] +3457:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5556 .loc 1 3457 5 is_stmt 1 view .LVU1825 +3457:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5557 .loc 1 3457 23 is_stmt 0 view .LVU1826 + 5558 017a 08F11C00 add r0, r8, #28 + 5559 017e FFF7FEFF bl ld_dword + 5560 .LVL650: +3457:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5561 .loc 1 3457 21 discriminator 1 view .LVU1827 + 5562 0182 F060 str r0, [r6, #12] +3460:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5563 .loc 1 3460 4 is_stmt 1 view .LVU1828 +3460:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5564 .loc 1 3460 14 is_stmt 0 view .LVU1829 + 5565 0184 0021 movs r1, #0 + 5566 0186 F162 str r1, [r6, #44] +3462:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.id = fs->id; + 5567 .loc 1 3462 4 is_stmt 1 view .LVU1830 +3462:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.id = fs->id; + 5568 .loc 1 3462 15 is_stmt 0 view .LVU1831 + 5569 0188 3460 str r4, [r6] +3463:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag = mode; /* Set file access mode */ + 5570 .loc 1 3463 4 is_stmt 1 view .LVU1832 +3463:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag = mode; /* Set file access mode */ + 5571 .loc 1 3463 19 is_stmt 0 view .LVU1833 + 5572 018a E388 ldrh r3, [r4, #6] +3463:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag = mode; /* Set file access mode */ + 5573 .loc 1 3463 15 view .LVU1834 + 5574 018c B380 strh r3, [r6, #4] @ movhi +3464:Middlewares/Third_Party/FatFs/src/ff.c **** fp->err = 0; /* Clear error flag */ + 5575 .loc 1 3464 4 is_stmt 1 view .LVU1835 +3464:Middlewares/Third_Party/FatFs/src/ff.c **** fp->err = 0; /* Clear error flag */ + 5576 .loc 1 3464 13 is_stmt 0 view .LVU1836 + 5577 018e 3775 strb r7, [r6, #20] +3465:Middlewares/Third_Party/FatFs/src/ff.c **** fp->sect = 0; /* Invalidate current data sector */ + 5578 .loc 1 3465 4 is_stmt 1 view .LVU1837 +3465:Middlewares/Third_Party/FatFs/src/ff.c **** fp->sect = 0; /* Invalidate current data sector */ + 5579 .loc 1 3465 12 is_stmt 0 view .LVU1838 + 5580 0190 7175 strb r1, [r6, #21] +3466:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = 0; /* Set file pointer top of the file */ + 5581 .loc 1 3466 4 is_stmt 1 view .LVU1839 +3466:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = 0; /* Set file pointer top of the file */ + ARM GAS /tmp/cc2SVLkL.s page 229 + + + 5582 .loc 1 3466 13 is_stmt 0 view .LVU1840 + 5583 0192 3162 str r1, [r6, #32] +3467:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 5584 .loc 1 3467 4 is_stmt 1 view .LVU1841 +3467:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 5585 .loc 1 3467 13 is_stmt 0 view .LVU1842 + 5586 0194 B161 str r1, [r6, #24] +3470:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5587 .loc 1 3470 4 is_stmt 1 view .LVU1843 +3470:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5588 .loc 1 3470 14 is_stmt 0 view .LVU1844 + 5589 0196 06F13008 add r8, r6, #48 +3470:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5590 .loc 1 3470 4 view .LVU1845 + 5591 019a 4FF48052 mov r2, #4096 + 5592 019e 4046 mov r0, r8 + 5593 01a0 FFF7FEFF bl mem_set + 5594 .LVL651: +3472:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = fp->obj.objsize; /* Offset to seek */ + 5595 .loc 1 3472 4 is_stmt 1 view .LVU1846 +3472:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = fp->obj.objsize; /* Offset to seek */ + 5596 .loc 1 3472 7 is_stmt 0 view .LVU1847 + 5597 01a4 17F0200F tst r7, #32 + 5598 01a8 39D0 beq .L396 +3472:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = fp->obj.objsize; /* Offset to seek */ + 5599 .loc 1 3472 38 discriminator 1 view .LVU1848 + 5600 01aa F468 ldr r4, [r6, #12] +3472:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = fp->obj.objsize; /* Offset to seek */ + 5601 .loc 1 3472 28 discriminator 1 view .LVU1849 + 5602 01ac 002C cmp r4, #0 + 5603 01ae 36D0 beq .L396 +3473:Middlewares/Third_Party/FatFs/src/ff.c **** bcs = (DWORD)fs->csize * SS(fs); /* Cluster size in byte */ + 5604 .loc 1 3473 5 is_stmt 1 view .LVU1850 +3473:Middlewares/Third_Party/FatFs/src/ff.c **** bcs = (DWORD)fs->csize * SS(fs); /* Cluster size in byte */ + 5605 .loc 1 3473 14 is_stmt 0 view .LVU1851 + 5606 01b0 B461 str r4, [r6, #24] +3474:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fp->obj.sclust; /* Follow the cluster chain */ + 5607 .loc 1 3474 5 is_stmt 1 view .LVU1852 +3474:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fp->obj.sclust; /* Follow the cluster chain */ + 5608 .loc 1 3474 20 is_stmt 0 view .LVU1853 + 5609 01b2 039B ldr r3, [sp, #12] + 5610 01b4 5F89 ldrh r7, [r3, #10] + 5611 .LVL652: +3474:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fp->obj.sclust; /* Follow the cluster chain */ + 5612 .loc 1 3474 30 view .LVU1854 + 5613 01b6 9B89 ldrh r3, [r3, #12] +3474:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fp->obj.sclust; /* Follow the cluster chain */ + 5614 .loc 1 3474 9 view .LVU1855 + 5615 01b8 03FB07F7 mul r7, r3, r7 + 5616 .LVL653: +3475:Middlewares/Third_Party/FatFs/src/ff.c **** for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) { + 5617 .loc 1 3475 5 is_stmt 1 view .LVU1856 +3475:Middlewares/Third_Party/FatFs/src/ff.c **** for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) { + 5618 .loc 1 3475 10 is_stmt 0 view .LVU1857 + 5619 01bc B168 ldr r1, [r6, #8] + 5620 .LVL654: +3476:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&fp->obj, clst); + ARM GAS /tmp/cc2SVLkL.s page 230 + + + 5621 .loc 1 3476 5 is_stmt 1 view .LVU1858 +3476:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&fp->obj, clst); + 5622 .loc 1 3476 5 is_stmt 0 view .LVU1859 + 5623 01be 01E0 b .L397 + 5624 .LVL655: + 5625 .L409: +3478:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) res = FR_DISK_ERR; + 5626 .loc 1 3478 25 discriminator 1 view .LVU1860 + 5627 01c0 0225 movs r5, #2 + 5628 .LVL656: + 5629 .L398: +3476:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&fp->obj, clst); + 5630 .loc 1 3476 64 is_stmt 1 discriminator 2 view .LVU1861 + 5631 01c2 E41B subs r4, r4, r7 + 5632 .LVL657: + 5633 .L397: +3476:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&fp->obj, clst); + 5634 .loc 1 3476 46 discriminator 1 view .LVU1862 +3476:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&fp->obj, clst); + 5635 .loc 1 3476 53 is_stmt 0 discriminator 1 view .LVU1863 + 5636 01c4 BC42 cmp r4, r7 + 5637 01c6 94BF ite ls + 5638 01c8 0023 movls r3, #0 + 5639 01ca 0123 movhi r3, #1 +3476:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&fp->obj, clst); + 5640 .loc 1 3476 46 discriminator 1 view .LVU1864 + 5641 01cc 5DB9 cbnz r5, .L413 +3476:Middlewares/Third_Party/FatFs/src/ff.c **** clst = get_fat(&fp->obj, clst); + 5642 .loc 1 3476 46 discriminator 1 view .LVU1865 + 5643 01ce 53B1 cbz r3, .L413 +3477:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst <= 1) res = FR_INT_ERR; + 5644 .loc 1 3477 6 is_stmt 1 view .LVU1866 +3477:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst <= 1) res = FR_INT_ERR; + 5645 .loc 1 3477 13 is_stmt 0 view .LVU1867 + 5646 01d0 3046 mov r0, r6 + 5647 01d2 FFF7FEFF bl get_fat + 5648 .LVL658: +3477:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst <= 1) res = FR_INT_ERR; + 5649 .loc 1 3477 13 view .LVU1868 + 5650 01d6 0146 mov r1, r0 + 5651 .LVL659: +3478:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) res = FR_DISK_ERR; + 5652 .loc 1 3478 6 is_stmt 1 view .LVU1869 +3478:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) res = FR_DISK_ERR; + 5653 .loc 1 3478 9 is_stmt 0 view .LVU1870 + 5654 01d8 0128 cmp r0, #1 + 5655 01da F1D9 bls .L409 +3479:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5656 .loc 1 3479 6 is_stmt 1 view .LVU1871 +3479:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5657 .loc 1 3479 9 is_stmt 0 view .LVU1872 + 5658 01dc B0F1FF3F cmp r0, #-1 + 5659 01e0 EFD1 bne .L398 +3479:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5660 .loc 1 3479 34 discriminator 1 view .LVU1873 + 5661 01e2 0125 movs r5, #1 + 5662 .LVL660: + ARM GAS /tmp/cc2SVLkL.s page 231 + + +3479:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5663 .loc 1 3479 34 discriminator 1 view .LVU1874 + 5664 01e4 EDE7 b .L398 + 5665 .LVL661: + 5666 .L413: +3481:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && ofs % SS(fs)) { /* Fill sector buffer if not on the sector boundary */ + 5667 .loc 1 3481 5 is_stmt 1 view .LVU1875 +3481:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && ofs % SS(fs)) { /* Fill sector buffer if not on the sector boundary */ + 5668 .loc 1 3481 15 is_stmt 0 view .LVU1876 + 5669 01e6 F161 str r1, [r6, #28] +3482:Middlewares/Third_Party/FatFs/src/ff.c **** if ((sc = clust2sect(fs, clst)) == 0) { + 5670 .loc 1 3482 5 is_stmt 1 view .LVU1877 +3482:Middlewares/Third_Party/FatFs/src/ff.c **** if ((sc = clust2sect(fs, clst)) == 0) { + 5671 .loc 1 3482 8 is_stmt 0 view .LVU1878 + 5672 01e8 002D cmp r5, #0 + 5673 01ea 7FF41BAF bne .L388 +3482:Middlewares/Third_Party/FatFs/src/ff.c **** if ((sc = clust2sect(fs, clst)) == 0) { + 5674 .loc 1 3482 31 discriminator 1 view .LVU1879 + 5675 01ee 039F ldr r7, [sp, #12] + 5676 .LVL662: +3482:Middlewares/Third_Party/FatFs/src/ff.c **** if ((sc = clust2sect(fs, clst)) == 0) { + 5677 .loc 1 3482 31 discriminator 1 view .LVU1880 + 5678 01f0 B7F80C90 ldrh r9, [r7, #12] +3482:Middlewares/Third_Party/FatFs/src/ff.c **** if ((sc = clust2sect(fs, clst)) == 0) { + 5679 .loc 1 3482 29 discriminator 1 view .LVU1881 + 5680 01f4 B4FBF9F3 udiv r3, r4, r9 + 5681 01f8 09FB1343 mls r3, r9, r3, r4 +3482:Middlewares/Third_Party/FatFs/src/ff.c **** if ((sc = clust2sect(fs, clst)) == 0) { + 5682 .loc 1 3482 22 discriminator 1 view .LVU1882 + 5683 01fc 7BB1 cbz r3, .L396 +3483:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INT_ERR; + 5684 .loc 1 3483 6 is_stmt 1 view .LVU1883 +3483:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INT_ERR; + 5685 .loc 1 3483 16 is_stmt 0 view .LVU1884 + 5686 01fe 3846 mov r0, r7 + 5687 0200 FFF7FEFF bl clust2sect + 5688 .LVL663: +3483:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INT_ERR; + 5689 .loc 1 3483 9 discriminator 1 view .LVU1885 + 5690 0204 08B9 cbnz r0, .L419 +3484:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 5691 .loc 1 3484 11 view .LVU1886 + 5692 0206 0225 movs r5, #2 + 5693 .LVL664: +3484:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 5694 .loc 1 3484 11 view .LVU1887 + 5695 0208 0CE7 b .L388 + 5696 .LVL665: + 5697 .L419: +3486:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 5698 .loc 1 3486 7 is_stmt 1 view .LVU1888 +3486:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 5699 .loc 1 3486 23 is_stmt 0 view .LVU1889 + 5700 020a B4FBF9F2 udiv r2, r4, r9 +3486:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 5701 .loc 1 3486 21 view .LVU1890 + 5702 020e 0244 add r2, r2, r0 + ARM GAS /tmp/cc2SVLkL.s page 232 + + +3486:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 5703 .loc 1 3486 16 view .LVU1891 + 5704 0210 3262 str r2, [r6, #32] +3488:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5705 .loc 1 3488 7 is_stmt 1 view .LVU1892 +3488:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5706 .loc 1 3488 11 is_stmt 0 view .LVU1893 + 5707 0212 0123 movs r3, #1 + 5708 0214 4146 mov r1, r8 + 5709 0216 7878 ldrb r0, [r7, #1] @ zero_extendqisi2 + 5710 .LVL666: +3488:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5711 .loc 1 3488 11 view .LVU1894 + 5712 0218 FFF7FEFF bl disk_read + 5713 .LVL667: +3488:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5714 .loc 1 3488 10 discriminator 1 view .LVU1895 + 5715 021c 28B9 cbnz r0, .L412 + 5716 .LVL668: + 5717 .L396: +3496:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5718 .loc 1 3496 16 is_stmt 1 view .LVU1896 +3499:Middlewares/Third_Party/FatFs/src/ff.c **** + 5719 .loc 1 3499 2 view .LVU1897 +3499:Middlewares/Third_Party/FatFs/src/ff.c **** + 5720 .loc 1 3499 5 is_stmt 0 view .LVU1898 + 5721 021e 002D cmp r5, #0 + 5722 0220 3FF402AF beq .L387 +3499:Middlewares/Third_Party/FatFs/src/ff.c **** + 5723 .loc 1 3499 5 view .LVU1899 + 5724 0224 FEE6 b .L388 + 5725 .LVL669: + 5726 .L406: +3414:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 5727 .loc 1 3414 10 view .LVU1900 + 5728 0226 0425 movs r5, #4 + 5729 .LVL670: +3414:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 5730 .loc 1 3414 10 view .LVU1901 + 5731 0228 FCE6 b .L388 + 5732 .LVL671: + 5733 .L412: +3488:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5734 .loc 1 3488 67 discriminator 1 view .LVU1902 + 5735 022a 0125 movs r5, #1 + 5736 .LVL672: +3488:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5737 .loc 1 3488 67 discriminator 1 view .LVU1903 + 5738 022c FAE6 b .L388 + 5739 .LVL673: + 5740 .L401: +3324:Middlewares/Third_Party/FatFs/src/ff.c **** + 5741 .loc 1 3324 18 discriminator 1 view .LVU1904 + 5742 022e 0925 movs r5, #9 + 5743 0230 FAE6 b .L387 + 5744 .cfi_endproc + 5745 .LFE1222: + ARM GAS /tmp/cc2SVLkL.s page 233 + + + 5747 .section .text.f_read,"ax",%progbits + 5748 .align 1 + 5749 .global f_read + 5750 .syntax unified + 5751 .thumb + 5752 .thumb_func + 5754 f_read: + 5755 .LVL674: + 5756 .LFB1223: +3517:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 5757 .loc 1 3517 1 is_stmt 1 view -0 + 5758 .cfi_startproc + 5759 @ args = 0, pretend = 0, frame = 16 + 5760 @ frame_needed = 0, uses_anonymous_args = 0 +3517:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 5761 .loc 1 3517 1 is_stmt 0 view .LVU1906 + 5762 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 5763 .LCFI46: + 5764 .cfi_def_cfa_offset 36 + 5765 .cfi_offset 4, -36 + 5766 .cfi_offset 5, -32 + 5767 .cfi_offset 6, -28 + 5768 .cfi_offset 7, -24 + 5769 .cfi_offset 8, -20 + 5770 .cfi_offset 9, -16 + 5771 .cfi_offset 10, -12 + 5772 .cfi_offset 11, -8 + 5773 .cfi_offset 14, -4 + 5774 0004 85B0 sub sp, sp, #20 + 5775 .LCFI47: + 5776 .cfi_def_cfa_offset 56 + 5777 0006 0446 mov r4, r0 + 5778 0008 0F46 mov r7, r1 + 5779 000a 1546 mov r5, r2 + 5780 000c 9846 mov r8, r3 +3518:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; + 5781 .loc 1 3518 2 is_stmt 1 view .LVU1907 +3519:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clst, sect; + 5782 .loc 1 3519 2 view .LVU1908 +3520:Middlewares/Third_Party/FatFs/src/ff.c **** FSIZE_t remain; + 5783 .loc 1 3520 2 view .LVU1909 +3521:Middlewares/Third_Party/FatFs/src/ff.c **** UINT rcnt, cc, csect; + 5784 .loc 1 3521 2 view .LVU1910 +3522:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE *rbuff = (BYTE*)buff; + 5785 .loc 1 3522 2 view .LVU1911 +3523:Middlewares/Third_Party/FatFs/src/ff.c **** + 5786 .loc 1 3523 2 view .LVU1912 + 5787 .LVL675: +3526:Middlewares/Third_Party/FatFs/src/ff.c **** res = validate(&fp->obj, &fs); /* Check validity of the file object */ + 5788 .loc 1 3526 2 view .LVU1913 +3526:Middlewares/Third_Party/FatFs/src/ff.c **** res = validate(&fp->obj, &fs); /* Check validity of the file object */ + 5789 .loc 1 3526 6 is_stmt 0 view .LVU1914 + 5790 000e 0023 movs r3, #0 + 5791 .LVL676: +3526:Middlewares/Third_Party/FatFs/src/ff.c **** res = validate(&fp->obj, &fs); /* Check validity of the file object */ + 5792 .loc 1 3526 6 view .LVU1915 + 5793 0010 C8F80030 str r3, [r8] + ARM GAS /tmp/cc2SVLkL.s page 234 + + +3527:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ + 5794 .loc 1 3527 2 is_stmt 1 view .LVU1916 +3527:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ + 5795 .loc 1 3527 8 is_stmt 0 view .LVU1917 + 5796 0014 03A9 add r1, sp, #12 + 5797 .LVL677: +3527:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ + 5798 .loc 1 3527 8 view .LVU1918 + 5799 0016 FFF7FEFF bl validate + 5800 .LVL678: +3528:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + 5801 .loc 1 3528 2 is_stmt 1 view .LVU1919 +3528:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + 5802 .loc 1 3528 5 is_stmt 0 view .LVU1920 + 5803 001a 0190 str r0, [sp, #4] + 5804 001c 0028 cmp r0, #0 + 5805 001e 40F0B980 bne .L423 +3528:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + 5806 .loc 1 3528 27 discriminator 2 view .LVU1921 + 5807 0022 637D ldrb r3, [r4, #21] @ zero_extendqisi2 + 5808 0024 0193 str r3, [sp, #4] + 5809 .LVL679: +3528:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + 5810 .loc 1 3528 19 discriminator 2 view .LVU1922 + 5811 0026 002B cmp r3, #0 + 5812 0028 40F0B480 bne .L423 +3529:Middlewares/Third_Party/FatFs/src/ff.c **** remain = fp->obj.objsize - fp->fptr; + 5813 .loc 1 3529 2 is_stmt 1 view .LVU1923 +3529:Middlewares/Third_Party/FatFs/src/ff.c **** remain = fp->obj.objsize - fp->fptr; + 5814 .loc 1 3529 10 is_stmt 0 view .LVU1924 + 5815 002c 237D ldrb r3, [r4, #20] @ zero_extendqisi2 + 5816 .LVL680: +3529:Middlewares/Third_Party/FatFs/src/ff.c **** remain = fp->obj.objsize - fp->fptr; + 5817 .loc 1 3529 5 view .LVU1925 + 5818 002e 13F0010F tst r3, #1 + 5819 0032 00F0CE80 beq .L445 +3530:Middlewares/Third_Party/FatFs/src/ff.c **** if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + 5820 .loc 1 3530 2 is_stmt 1 view .LVU1926 +3530:Middlewares/Third_Party/FatFs/src/ff.c **** if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + 5821 .loc 1 3530 18 is_stmt 0 view .LVU1927 + 5822 0036 E668 ldr r6, [r4, #12] +3530:Middlewares/Third_Party/FatFs/src/ff.c **** if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + 5823 .loc 1 3530 31 view .LVU1928 + 5824 0038 A369 ldr r3, [r4, #24] +3530:Middlewares/Third_Party/FatFs/src/ff.c **** if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + 5825 .loc 1 3530 9 view .LVU1929 + 5826 003a F61A subs r6, r6, r3 + 5827 .LVL681: +3531:Middlewares/Third_Party/FatFs/src/ff.c **** + 5828 .loc 1 3531 2 is_stmt 1 view .LVU1930 +3531:Middlewares/Third_Party/FatFs/src/ff.c **** + 5829 .loc 1 3531 5 is_stmt 0 view .LVU1931 + 5830 003c AE42 cmp r6, r5 + 5831 003e 67D3 bcc .L443 + 5832 0040 2E46 mov r6, r5 + 5833 .LVL682: +3531:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 235 + + + 5834 .loc 1 3531 5 view .LVU1932 + 5835 0042 65E0 b .L443 + 5836 .LVL683: + 5837 .L428: +3542:Middlewares/Third_Party/FatFs/src/ff.c **** clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + 5838 .loc 1 3542 6 is_stmt 1 view .LVU1933 +3542:Middlewares/Third_Party/FatFs/src/ff.c **** clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + 5839 .loc 1 3542 12 is_stmt 0 view .LVU1934 + 5840 0044 E36A ldr r3, [r4, #44] +3542:Middlewares/Third_Party/FatFs/src/ff.c **** clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + 5841 .loc 1 3542 9 view .LVU1935 + 5842 0046 1BB1 cbz r3, .L430 +3543:Middlewares/Third_Party/FatFs/src/ff.c **** } else + 5843 .loc 1 3543 7 is_stmt 1 view .LVU1936 +3543:Middlewares/Third_Party/FatFs/src/ff.c **** } else + 5844 .loc 1 3543 14 is_stmt 0 view .LVU1937 + 5845 0048 2046 mov r0, r4 + 5846 004a FFF7FEFF bl clmt_clust + 5847 .LVL684: +3543:Middlewares/Third_Party/FatFs/src/ff.c **** } else + 5848 .loc 1 3543 14 view .LVU1938 + 5849 004e 73E0 b .L429 + 5850 .LVL685: + 5851 .L430: +3547:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5852 .loc 1 3547 7 is_stmt 1 view .LVU1939 +3547:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5853 .loc 1 3547 14 is_stmt 0 view .LVU1940 + 5854 0050 E169 ldr r1, [r4, #28] + 5855 0052 2046 mov r0, r4 + 5856 0054 FFF7FEFF bl get_fat + 5857 .LVL686: +3547:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5858 .loc 1 3547 14 view .LVU1941 + 5859 0058 6EE0 b .L429 + 5860 .L452: +3550:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 5861 .loc 1 3550 19 is_stmt 1 discriminator 1 view .LVU1942 + 5862 005a 4FF0020A mov r10, #2 + 5863 005e 84F815A0 strb r10, [r4, #21] +3550:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 5864 .loc 1 3550 19 discriminator 1 view .LVU1943 + 5865 0062 CDF804A0 str r10, [sp, #4] + 5866 .LVL687: +3550:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 5867 .loc 1 3550 19 is_stmt 0 view .LVU1944 + 5868 0066 95E0 b .L423 + 5869 .LVL688: + 5870 .L453: +3551:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; /* Update current cluster */ + 5871 .loc 1 3551 29 is_stmt 1 discriminator 1 view .LVU1945 + 5872 0068 4FF0010A mov r10, #1 + 5873 006c 84F815A0 strb r10, [r4, #21] +3551:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; /* Update current cluster */ + 5874 .loc 1 3551 29 discriminator 1 view .LVU1946 + 5875 0070 CDF804A0 str r10, [sp, #4] + 5876 .LVL689: + ARM GAS /tmp/cc2SVLkL.s page 236 + + +3551:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; /* Update current cluster */ + 5877 .loc 1 3551 29 is_stmt 0 view .LVU1947 + 5878 0074 8EE0 b .L423 + 5879 .LVL690: + 5880 .L454: +3555:Middlewares/Third_Party/FatFs/src/ff.c **** sect += csect; + 5881 .loc 1 3555 15 is_stmt 1 discriminator 1 view .LVU1948 + 5882 0076 4FF0020A mov r10, #2 + 5883 007a 84F815A0 strb r10, [r4, #21] +3555:Middlewares/Third_Party/FatFs/src/ff.c **** sect += csect; + 5884 .loc 1 3555 15 discriminator 1 view .LVU1949 + 5885 007e CDF804A0 str r10, [sp, #4] + 5886 .LVL691: +3555:Middlewares/Third_Party/FatFs/src/ff.c **** sect += csect; + 5887 .loc 1 3555 15 is_stmt 0 view .LVU1950 + 5888 0082 87E0 b .L423 + 5889 .LVL692: + 5890 .L436: +3562:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it + 5891 .loc 1 3562 78 is_stmt 1 discriminator 2 view .LVU1951 +3569:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs)); + 5892 .loc 1 3569 5 view .LVU1952 +3569:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs)); + 5893 .loc 1 3569 9 is_stmt 0 view .LVU1953 + 5894 0084 94F91430 ldrsb r3, [r4, #20] +3569:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs)); + 5895 .loc 1 3569 8 view .LVU1954 + 5896 0088 002B cmp r3, #0 + 5897 008a 04DB blt .L449 + 5898 .L437: +3574:Middlewares/Third_Party/FatFs/src/ff.c **** continue; + 5899 .loc 1 3574 5 is_stmt 1 view .LVU1955 +3574:Middlewares/Third_Party/FatFs/src/ff.c **** continue; + 5900 .loc 1 3574 12 is_stmt 0 view .LVU1956 + 5901 008c 039B ldr r3, [sp, #12] + 5902 008e 9D89 ldrh r5, [r3, #12] + 5903 .LVL693: +3574:Middlewares/Third_Party/FatFs/src/ff.c **** continue; + 5904 .loc 1 3574 10 view .LVU1957 + 5905 0090 0AFB05F5 mul r5, r10, r5 + 5906 .LVL694: +3575:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5907 .loc 1 3575 5 is_stmt 1 view .LVU1958 + 5908 0094 32E0 b .L438 + 5909 .LVL695: + 5910 .L449: +3569:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs)); + 5911 .loc 1 3569 36 is_stmt 0 discriminator 1 view .LVU1959 + 5912 0096 236A ldr r3, [r4, #32] +3569:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs)); + 5913 .loc 1 3569 43 discriminator 1 view .LVU1960 + 5914 0098 A3EB0903 sub r3, r3, r9 +3569:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs)); + 5915 .loc 1 3569 31 discriminator 1 view .LVU1961 + 5916 009c 5345 cmp r3, r10 + 5917 009e F5D2 bcs .L437 +3570:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 237 + + + 5918 .loc 1 3570 6 is_stmt 1 view .LVU1962 +3570:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5919 .loc 1 3570 43 is_stmt 0 view .LVU1963 + 5920 00a0 039A ldr r2, [sp, #12] + 5921 00a2 9289 ldrh r2, [r2, #12] +3570:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5922 .loc 1 3570 6 view .LVU1964 + 5923 00a4 04F13001 add r1, r4, #48 + 5924 00a8 02FB0370 mla r0, r2, r3, r7 + 5925 00ac FFF7FEFF bl mem_cpy + 5926 .LVL696: + 5927 00b0 ECE7 b .L437 + 5928 .L434: +3578:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 5929 .loc 1 3578 4 is_stmt 1 view .LVU1965 +3578:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 5930 .loc 1 3578 10 is_stmt 0 view .LVU1966 + 5931 00b2 226A ldr r2, [r4, #32] +3578:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 5932 .loc 1 3578 7 view .LVU1967 + 5933 00b4 4A45 cmp r2, r9 + 5934 00b6 0DD0 beq .L439 +3580:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + 5935 .loc 1 3580 5 is_stmt 1 view .LVU1968 +3580:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + 5936 .loc 1 3580 9 is_stmt 0 view .LVU1969 + 5937 00b8 94F91430 ldrsb r3, [r4, #20] +3580:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + 5938 .loc 1 3580 8 view .LVU1970 + 5939 00bc 002B cmp r3, #0 + 5940 00be 6DDB blt .L450 + 5941 .L440: +3585:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5942 .loc 1 3585 5 is_stmt 1 view .LVU1971 +3585:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5943 .loc 1 3585 9 is_stmt 0 view .LVU1972 + 5944 00c0 0123 movs r3, #1 + 5945 00c2 4A46 mov r2, r9 + 5946 00c4 04F13001 add r1, r4, #48 + 5947 00c8 0398 ldr r0, [sp, #12] + 5948 00ca 4078 ldrb r0, [r0, #1] @ zero_extendqisi2 + 5949 00cc FFF7FEFF bl disk_read + 5950 .LVL697: +3585:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5951 .loc 1 3585 8 discriminator 1 view .LVU1973 + 5952 00d0 0028 cmp r0, #0 + 5953 00d2 77D1 bne .L451 + 5954 .L439: +3585:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5955 .loc 1 3585 79 is_stmt 1 discriminator 2 view .LVU1974 +3588:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5956 .loc 1 3588 4 view .LVU1975 +3588:Middlewares/Third_Party/FatFs/src/ff.c **** } + 5957 .loc 1 3588 13 is_stmt 0 view .LVU1976 + 5958 00d4 C4F82090 str r9, [r4, #32] + 5959 .LVL698: + 5960 .L426: + ARM GAS /tmp/cc2SVLkL.s page 238 + + +3590:Middlewares/Third_Party/FatFs/src/ff.c **** if (rcnt > btr) rcnt = btr; /* Clip it by btr if needed */ + 5961 .loc 1 3590 3 is_stmt 1 view .LVU1977 +3590:Middlewares/Third_Party/FatFs/src/ff.c **** if (rcnt > btr) rcnt = btr; /* Clip it by btr if needed */ + 5962 .loc 1 3590 10 is_stmt 0 view .LVU1978 + 5963 00d8 039B ldr r3, [sp, #12] + 5964 00da 9D89 ldrh r5, [r3, #12] +3590:Middlewares/Third_Party/FatFs/src/ff.c **** if (rcnt > btr) rcnt = btr; /* Clip it by btr if needed */ + 5965 .loc 1 3590 27 view .LVU1979 + 5966 00dc A369 ldr r3, [r4, #24] +3590:Middlewares/Third_Party/FatFs/src/ff.c **** if (rcnt > btr) rcnt = btr; /* Clip it by btr if needed */ + 5967 .loc 1 3590 34 view .LVU1980 + 5968 00de B3FBF5F2 udiv r2, r3, r5 + 5969 00e2 05FB1233 mls r3, r5, r2, r3 +3590:Middlewares/Third_Party/FatFs/src/ff.c **** if (rcnt > btr) rcnt = btr; /* Clip it by btr if needed */ + 5970 .loc 1 3590 8 view .LVU1981 + 5971 00e6 ED1A subs r5, r5, r3 + 5972 .LVL699: +3591:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY + 5973 .loc 1 3591 3 is_stmt 1 view .LVU1982 +3591:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY + 5974 .loc 1 3591 6 is_stmt 0 view .LVU1983 + 5975 00e8 AE42 cmp r6, r5 + 5976 00ea 00D2 bcs .L442 +3591:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY + 5977 .loc 1 3591 24 discriminator 1 view .LVU1984 + 5978 00ec 3546 mov r5, r6 + 5979 .LVL700: + 5980 .L442: +3596:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5981 .loc 1 3596 3 is_stmt 1 view .LVU1985 +3596:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5982 .loc 1 3596 18 is_stmt 0 view .LVU1986 + 5983 00ee 04F13001 add r1, r4, #48 +3596:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 5984 .loc 1 3596 3 view .LVU1987 + 5985 00f2 2A46 mov r2, r5 + 5986 00f4 1944 add r1, r1, r3 + 5987 00f6 3846 mov r0, r7 + 5988 00f8 FFF7FEFF bl mem_cpy + 5989 .LVL701: + 5990 .L438: +3534:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + 5991 .loc 1 3534 47 is_stmt 1 view .LVU1988 +3534:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + 5992 .loc 1 3534 9 is_stmt 0 view .LVU1989 + 5993 00fc 2F44 add r7, r7, r5 + 5994 .LVL702: +3534:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + 5995 .loc 1 3534 20 view .LVU1990 + 5996 00fe A369 ldr r3, [r4, #24] +3534:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + 5997 .loc 1 3534 27 view .LVU1991 + 5998 0100 2B44 add r3, r3, r5 + 5999 0102 A361 str r3, [r4, #24] +3534:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + 6000 .loc 1 3534 36 view .LVU1992 + 6001 0104 D8F80030 ldr r3, [r8] + ARM GAS /tmp/cc2SVLkL.s page 239 + + +3534:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + 6002 .loc 1 3534 40 view .LVU1993 + 6003 0108 2B44 add r3, r3, r5 + 6004 010a C8F80030 str r3, [r8] +3534:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + 6005 .loc 1 3534 53 view .LVU1994 + 6006 010e 761B subs r6, r6, r5 + 6007 .LVL703: + 6008 .L443: +3533:Middlewares/Third_Party/FatFs/src/ff.c **** rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) { + 6009 .loc 1 3533 11 is_stmt 1 view .LVU1995 + 6010 0110 002E cmp r6, #0 + 6011 0112 3FD0 beq .L423 +3535:Middlewares/Third_Party/FatFs/src/ff.c **** csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ + 6012 .loc 1 3535 3 view .LVU1996 +3535:Middlewares/Third_Party/FatFs/src/ff.c **** csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ + 6013 .loc 1 3535 9 is_stmt 0 view .LVU1997 + 6014 0114 A169 ldr r1, [r4, #24] +3535:Middlewares/Third_Party/FatFs/src/ff.c **** csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ + 6015 .loc 1 3535 18 view .LVU1998 + 6016 0116 039A ldr r2, [sp, #12] + 6017 0118 9589 ldrh r5, [r2, #12] +3535:Middlewares/Third_Party/FatFs/src/ff.c **** csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ + 6018 .loc 1 3535 16 view .LVU1999 + 6019 011a B1FBF5F3 udiv r3, r1, r5 + 6020 011e 05FB1313 mls r3, r5, r3, r1 +3535:Middlewares/Third_Party/FatFs/src/ff.c **** csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */ + 6021 .loc 1 3535 6 view .LVU2000 + 6022 0122 002B cmp r3, #0 + 6023 0124 D8D1 bne .L426 +3536:Middlewares/Third_Party/FatFs/src/ff.c **** if (csect == 0) { /* On the cluster boundary? */ + 6024 .loc 1 3536 4 is_stmt 1 view .LVU2001 +3536:Middlewares/Third_Party/FatFs/src/ff.c **** if (csect == 0) { /* On the cluster boundary? */ + 6025 .loc 1 3536 28 is_stmt 0 view .LVU2002 + 6026 0126 B1FBF5F5 udiv r5, r1, r5 +3536:Middlewares/Third_Party/FatFs/src/ff.c **** if (csect == 0) { /* On the cluster boundary? */ + 6027 .loc 1 3536 42 view .LVU2003 + 6028 012a 5389 ldrh r3, [r2, #10] +3536:Middlewares/Third_Party/FatFs/src/ff.c **** if (csect == 0) { /* On the cluster boundary? */ + 6029 .loc 1 3536 50 view .LVU2004 + 6030 012c 013B subs r3, r3, #1 + 6031 .LVL704: +3537:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr == 0) { /* On the top of the file? */ + 6032 .loc 1 3537 4 is_stmt 1 view .LVU2005 +3537:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr == 0) { /* On the top of the file? */ + 6033 .loc 1 3537 7 is_stmt 0 view .LVU2006 + 6034 012e 1D40 ands r5, r5, r3 + 6035 .LVL705: +3537:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr == 0) { /* On the top of the file? */ + 6036 .loc 1 3537 7 view .LVU2007 + 6037 0130 08D1 bne .L427 +3538:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fp->obj.sclust; /* Follow cluster chain from the origin */ + 6038 .loc 1 3538 5 is_stmt 1 view .LVU2008 +3538:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fp->obj.sclust; /* Follow cluster chain from the origin */ + 6039 .loc 1 3538 8 is_stmt 0 view .LVU2009 + 6040 0132 0029 cmp r1, #0 + 6041 0134 86D1 bne .L428 + ARM GAS /tmp/cc2SVLkL.s page 240 + + +3539:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* Middle or end of the file */ + 6042 .loc 1 3539 6 is_stmt 1 view .LVU2010 +3539:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* Middle or end of the file */ + 6043 .loc 1 3539 11 is_stmt 0 view .LVU2011 + 6044 0136 A068 ldr r0, [r4, #8] + 6045 .LVL706: + 6046 .L429: +3550:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 6047 .loc 1 3550 5 is_stmt 1 view .LVU2012 +3550:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 6048 .loc 1 3550 8 is_stmt 0 view .LVU2013 + 6049 0138 0128 cmp r0, #1 + 6050 013a 8ED9 bls .L452 +3550:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 6051 .loc 1 3550 40 is_stmt 1 discriminator 2 view .LVU2014 +3551:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; /* Update current cluster */ + 6052 .loc 1 3551 5 view .LVU2015 +3551:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; /* Update current cluster */ + 6053 .loc 1 3551 8 is_stmt 0 view .LVU2016 + 6054 013c B0F1FF3F cmp r0, #-1 + 6055 0140 92D0 beq .L453 +3551:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; /* Update current cluster */ + 6056 .loc 1 3551 51 is_stmt 1 discriminator 2 view .LVU2017 +3552:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6057 .loc 1 3552 5 view .LVU2018 +3552:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6058 .loc 1 3552 15 is_stmt 0 view .LVU2019 + 6059 0142 E061 str r0, [r4, #28] + 6060 .LVL707: + 6061 .L427: +3554:Middlewares/Third_Party/FatFs/src/ff.c **** if (!sect) ABORT(fs, FR_INT_ERR); + 6062 .loc 1 3554 4 is_stmt 1 view .LVU2020 +3554:Middlewares/Third_Party/FatFs/src/ff.c **** if (!sect) ABORT(fs, FR_INT_ERR); + 6063 .loc 1 3554 11 is_stmt 0 view .LVU2021 + 6064 0144 DDF80CB0 ldr fp, [sp, #12] + 6065 0148 E169 ldr r1, [r4, #28] + 6066 014a 5846 mov r0, fp + 6067 014c FFF7FEFF bl clust2sect + 6068 .LVL708: +3555:Middlewares/Third_Party/FatFs/src/ff.c **** sect += csect; + 6069 .loc 1 3555 4 is_stmt 1 view .LVU2022 +3555:Middlewares/Third_Party/FatFs/src/ff.c **** sect += csect; + 6070 .loc 1 3555 7 is_stmt 0 view .LVU2023 + 6071 0150 8146 mov r9, r0 + 6072 0152 0028 cmp r0, #0 + 6073 0154 8FD0 beq .L454 +3555:Middlewares/Third_Party/FatFs/src/ff.c **** sect += csect; + 6074 .loc 1 3555 36 is_stmt 1 discriminator 2 view .LVU2024 +3556:Middlewares/Third_Party/FatFs/src/ff.c **** cc = btr / SS(fs); /* When remaining bytes >= sector size, */ + 6075 .loc 1 3556 4 view .LVU2025 +3556:Middlewares/Third_Party/FatFs/src/ff.c **** cc = btr / SS(fs); /* When remaining bytes >= sector size, */ + 6076 .loc 1 3556 9 is_stmt 0 view .LVU2026 + 6077 0156 A944 add r9, r9, r5 + 6078 .LVL709: +3557:Middlewares/Third_Party/FatFs/src/ff.c **** if (cc) { /* Read maximum contiguous sectors directly */ + 6079 .loc 1 3557 4 is_stmt 1 view .LVU2027 +3557:Middlewares/Third_Party/FatFs/src/ff.c **** if (cc) { /* Read maximum contiguous sectors directly */ + ARM GAS /tmp/cc2SVLkL.s page 241 + + + 6080 .loc 1 3557 15 is_stmt 0 view .LVU2028 + 6081 0158 BBF80C30 ldrh r3, [fp, #12] +3557:Middlewares/Third_Party/FatFs/src/ff.c **** if (cc) { /* Read maximum contiguous sectors directly */ + 6082 .loc 1 3557 7 view .LVU2029 + 6083 015c B6FBF3FA udiv r10, r6, r3 + 6084 .LVL710: +3558:Middlewares/Third_Party/FatFs/src/ff.c **** if (csect + cc > fs->csize) { /* Clip at cluster boundary */ + 6085 .loc 1 3558 4 is_stmt 1 view .LVU2030 +3558:Middlewares/Third_Party/FatFs/src/ff.c **** if (csect + cc > fs->csize) { /* Clip at cluster boundary */ + 6086 .loc 1 3558 7 is_stmt 0 view .LVU2031 + 6087 0160 B342 cmp r3, r6 + 6088 0162 A6D8 bhi .L434 +3559:Middlewares/Third_Party/FatFs/src/ff.c **** cc = fs->csize - csect; + 6089 .loc 1 3559 5 is_stmt 1 view .LVU2032 +3559:Middlewares/Third_Party/FatFs/src/ff.c **** cc = fs->csize - csect; + 6090 .loc 1 3559 15 is_stmt 0 view .LVU2033 + 6091 0164 05EB0A03 add r3, r5, r10 +3559:Middlewares/Third_Party/FatFs/src/ff.c **** cc = fs->csize - csect; + 6092 .loc 1 3559 24 view .LVU2034 + 6093 0168 BBF80A20 ldrh r2, [fp, #10] +3559:Middlewares/Third_Party/FatFs/src/ff.c **** cc = fs->csize - csect; + 6094 .loc 1 3559 8 view .LVU2035 + 6095 016c 9342 cmp r3, r2 + 6096 016e 01D9 bls .L435 +3560:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6097 .loc 1 3560 6 is_stmt 1 view .LVU2036 +3560:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6098 .loc 1 3560 9 is_stmt 0 view .LVU2037 + 6099 0170 A2EB050A sub r10, r2, r5 + 6100 .LVL711: + 6101 .L435: +3562:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it + 6102 .loc 1 3562 5 is_stmt 1 view .LVU2038 +3562:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it + 6103 .loc 1 3562 9 is_stmt 0 view .LVU2039 + 6104 0174 5346 mov r3, r10 + 6105 0176 4A46 mov r2, r9 + 6106 0178 3946 mov r1, r7 + 6107 017a 9BF80100 ldrb r0, [fp, #1] @ zero_extendqisi2 + 6108 017e FFF7FEFF bl disk_read + 6109 .LVL712: +3562:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it + 6110 .loc 1 3562 8 discriminator 1 view .LVU2040 + 6111 0182 0028 cmp r0, #0 + 6112 0184 3FF47EAF beq .L436 +3562:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it + 6113 .loc 1 3562 56 is_stmt 1 discriminator 1 view .LVU2041 + 6114 0188 4FF0010A mov r10, #1 + 6115 .LVL713: +3562:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it + 6116 .loc 1 3562 56 is_stmt 0 discriminator 1 view .LVU2042 + 6117 018c 84F815A0 strb r10, [r4, #21] +3562:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it + 6118 .loc 1 3562 56 is_stmt 1 discriminator 1 view .LVU2043 + 6119 0190 CDF804A0 str r10, [sp, #4] + 6120 .LVL714: + 6121 .L423: + ARM GAS /tmp/cc2SVLkL.s page 242 + + +3601:Middlewares/Third_Party/FatFs/src/ff.c **** + 6122 .loc 1 3601 1 is_stmt 0 view .LVU2044 + 6123 0194 0198 ldr r0, [sp, #4] + 6124 0196 05B0 add sp, sp, #20 + 6125 .LCFI48: + 6126 .cfi_remember_state + 6127 .cfi_def_cfa_offset 36 + 6128 @ sp needed + 6129 0198 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 6130 .LVL715: + 6131 .L450: + 6132 .LCFI49: + 6133 .cfi_restore_state +3581:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6134 .loc 1 3581 6 is_stmt 1 view .LVU2045 +3581:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6135 .loc 1 3581 10 is_stmt 0 view .LVU2046 + 6136 019c 0123 movs r3, #1 + 6137 019e 04F13001 add r1, r4, #48 + 6138 01a2 9BF80100 ldrb r0, [fp, #1] @ zero_extendqisi2 + 6139 01a6 FFF7FEFF bl disk_write + 6140 .LVL716: +3581:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6141 .loc 1 3581 9 discriminator 1 view .LVU2047 + 6142 01aa 20B9 cbnz r0, .L455 +3581:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6143 .loc 1 3581 85 is_stmt 1 discriminator 2 view .LVU2048 +3582:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6144 .loc 1 3582 6 view .LVU2049 +3582:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6145 .loc 1 3582 8 is_stmt 0 view .LVU2050 + 6146 01ac 237D ldrb r3, [r4, #20] @ zero_extendqisi2 +3582:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6147 .loc 1 3582 15 view .LVU2051 + 6148 01ae 03F07F03 and r3, r3, #127 + 6149 01b2 2375 strb r3, [r4, #20] + 6150 01b4 84E7 b .L440 + 6151 .L455: +3581:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6152 .loc 1 3581 63 is_stmt 1 discriminator 1 view .LVU2052 + 6153 01b6 4FF0010A mov r10, #1 + 6154 .LVL717: +3581:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6155 .loc 1 3581 63 is_stmt 0 discriminator 1 view .LVU2053 + 6156 01ba 84F815A0 strb r10, [r4, #21] +3581:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6157 .loc 1 3581 63 is_stmt 1 discriminator 1 view .LVU2054 + 6158 01be CDF804A0 str r10, [sp, #4] + 6159 .LVL718: +3581:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6160 .loc 1 3581 63 is_stmt 0 view .LVU2055 + 6161 01c2 E7E7 b .L423 + 6162 .LVL719: + 6163 .L451: +3585:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6164 .loc 1 3585 57 is_stmt 1 discriminator 1 view .LVU2056 + 6165 01c4 4FF0010A mov r10, #1 + ARM GAS /tmp/cc2SVLkL.s page 243 + + + 6166 .LVL720: +3585:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6167 .loc 1 3585 57 is_stmt 0 discriminator 1 view .LVU2057 + 6168 01c8 84F815A0 strb r10, [r4, #21] +3585:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6169 .loc 1 3585 57 is_stmt 1 discriminator 1 view .LVU2058 + 6170 01cc CDF804A0 str r10, [sp, #4] + 6171 .LVL721: +3585:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6172 .loc 1 3585 57 is_stmt 0 view .LVU2059 + 6173 01d0 E0E7 b .L423 + 6174 .LVL722: + 6175 .L445: +3529:Middlewares/Third_Party/FatFs/src/ff.c **** remain = fp->obj.objsize - fp->fptr; + 6176 .loc 1 3529 29 discriminator 1 view .LVU2060 + 6177 01d2 0723 movs r3, #7 + 6178 01d4 0193 str r3, [sp, #4] + 6179 .LVL723: +3529:Middlewares/Third_Party/FatFs/src/ff.c **** remain = fp->obj.objsize - fp->fptr; + 6180 .loc 1 3529 29 discriminator 1 view .LVU2061 + 6181 01d6 DDE7 b .L423 + 6182 .cfi_endproc + 6183 .LFE1223: + 6185 .section .text.f_write,"ax",%progbits + 6186 .align 1 + 6187 .global f_write + 6188 .syntax unified + 6189 .thumb + 6190 .thumb_func + 6192 f_write: + 6193 .LVL724: + 6194 .LFB1224: +3617:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 6195 .loc 1 3617 1 is_stmt 1 view -0 + 6196 .cfi_startproc + 6197 @ args = 0, pretend = 0, frame = 16 + 6198 @ frame_needed = 0, uses_anonymous_args = 0 +3617:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 6199 .loc 1 3617 1 is_stmt 0 view .LVU2063 + 6200 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 6201 .LCFI50: + 6202 .cfi_def_cfa_offset 36 + 6203 .cfi_offset 4, -36 + 6204 .cfi_offset 5, -32 + 6205 .cfi_offset 6, -28 + 6206 .cfi_offset 7, -24 + 6207 .cfi_offset 8, -20 + 6208 .cfi_offset 9, -16 + 6209 .cfi_offset 10, -12 + 6210 .cfi_offset 11, -8 + 6211 .cfi_offset 14, -4 + 6212 0004 85B0 sub sp, sp, #20 + 6213 .LCFI51: + 6214 .cfi_def_cfa_offset 56 + 6215 0006 0446 mov r4, r0 + 6216 0008 0F46 mov r7, r1 + 6217 000a 1546 mov r5, r2 + ARM GAS /tmp/cc2SVLkL.s page 244 + + + 6218 000c 9846 mov r8, r3 +3618:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; + 6219 .loc 1 3618 2 is_stmt 1 view .LVU2064 +3619:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clst, sect; + 6220 .loc 1 3619 2 view .LVU2065 +3620:Middlewares/Third_Party/FatFs/src/ff.c **** UINT wcnt, cc, csect; + 6221 .loc 1 3620 2 view .LVU2066 +3621:Middlewares/Third_Party/FatFs/src/ff.c **** const BYTE *wbuff = (const BYTE*)buff; + 6222 .loc 1 3621 2 view .LVU2067 +3622:Middlewares/Third_Party/FatFs/src/ff.c **** + 6223 .loc 1 3622 2 view .LVU2068 + 6224 .LVL725: +3625:Middlewares/Third_Party/FatFs/src/ff.c **** res = validate(&fp->obj, &fs); /* Check validity of the file object */ + 6225 .loc 1 3625 2 view .LVU2069 +3625:Middlewares/Third_Party/FatFs/src/ff.c **** res = validate(&fp->obj, &fs); /* Check validity of the file object */ + 6226 .loc 1 3625 6 is_stmt 0 view .LVU2070 + 6227 000e 0023 movs r3, #0 + 6228 .LVL726: +3625:Middlewares/Third_Party/FatFs/src/ff.c **** res = validate(&fp->obj, &fs); /* Check validity of the file object */ + 6229 .loc 1 3625 6 view .LVU2071 + 6230 0010 C8F80030 str r3, [r8] +3626:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ + 6231 .loc 1 3626 2 is_stmt 1 view .LVU2072 +3626:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ + 6232 .loc 1 3626 8 is_stmt 0 view .LVU2073 + 6233 0014 03A9 add r1, sp, #12 + 6234 .LVL727: +3626:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */ + 6235 .loc 1 3626 8 view .LVU2074 + 6236 0016 FFF7FEFF bl validate + 6237 .LVL728: +3627:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + 6238 .loc 1 3627 2 is_stmt 1 view .LVU2075 +3627:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + 6239 .loc 1 3627 5 is_stmt 0 view .LVU2076 + 6240 001a 0190 str r0, [sp, #4] + 6241 001c 0028 cmp r0, #0 + 6242 001e 4AD1 bne .L459 +3627:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + 6243 .loc 1 3627 27 discriminator 2 view .LVU2077 + 6244 0020 637D ldrb r3, [r4, #21] @ zero_extendqisi2 + 6245 0022 0193 str r3, [sp, #4] + 6246 .LVL729: +3627:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + 6247 .loc 1 3627 19 discriminator 2 view .LVU2078 + 6248 0024 002B cmp r3, #0 + 6249 0026 46D1 bne .L459 +3628:Middlewares/Third_Party/FatFs/src/ff.c **** + 6250 .loc 1 3628 2 is_stmt 1 view .LVU2079 +3628:Middlewares/Third_Party/FatFs/src/ff.c **** + 6251 .loc 1 3628 10 is_stmt 0 view .LVU2080 + 6252 0028 237D ldrb r3, [r4, #20] @ zero_extendqisi2 + 6253 .LVL730: +3628:Middlewares/Third_Party/FatFs/src/ff.c **** + 6254 .loc 1 3628 5 view .LVU2081 + 6255 002a 13F0020F tst r3, #2 + 6256 002e 00F0EC80 beq .L482 + ARM GAS /tmp/cc2SVLkL.s page 245 + + +3631:Middlewares/Third_Party/FatFs/src/ff.c **** btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr); + 6257 .loc 1 3631 2 is_stmt 1 view .LVU2082 +3631:Middlewares/Third_Party/FatFs/src/ff.c **** btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr); + 6258 .loc 1 3631 59 is_stmt 0 view .LVU2083 + 6259 0032 A369 ldr r3, [r4, #24] +3631:Middlewares/Third_Party/FatFs/src/ff.c **** btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr); + 6260 .loc 1 3631 5 view .LVU2084 + 6261 0034 EB42 cmn r3, r5 + 6262 0036 C0F0B680 bcc .L480 +3632:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6263 .loc 1 3632 3 is_stmt 1 view .LVU2085 +3632:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6264 .loc 1 3632 7 is_stmt 0 view .LVU2086 + 6265 003a DD43 mvns r5, r3 + 6266 .LVL731: +3632:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6267 .loc 1 3632 7 view .LVU2087 + 6268 003c B3E0 b .L480 + 6269 .LVL732: + 6270 .L463: +3647:Middlewares/Third_Party/FatFs/src/ff.c **** clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + 6271 .loc 1 3647 6 is_stmt 1 view .LVU2088 +3647:Middlewares/Third_Party/FatFs/src/ff.c **** clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + 6272 .loc 1 3647 12 is_stmt 0 view .LVU2089 + 6273 003e E36A ldr r3, [r4, #44] +3647:Middlewares/Third_Party/FatFs/src/ff.c **** clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + 6274 .loc 1 3647 9 view .LVU2090 + 6275 0040 002B cmp r3, #0 + 6276 0042 3CD0 beq .L466 +3648:Middlewares/Third_Party/FatFs/src/ff.c **** } else + 6277 .loc 1 3648 7 is_stmt 1 view .LVU2091 +3648:Middlewares/Third_Party/FatFs/src/ff.c **** } else + 6278 .loc 1 3648 14 is_stmt 0 view .LVU2092 + 6279 0044 2046 mov r0, r4 + 6280 0046 FFF7FEFF bl clmt_clust + 6281 .LVL733: + 6282 .L465: +3655:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 1) ABORT(fs, FR_INT_ERR); + 6283 .loc 1 3655 5 is_stmt 1 view .LVU2093 +3655:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 1) ABORT(fs, FR_INT_ERR); + 6284 .loc 1 3655 8 is_stmt 0 view .LVU2094 + 6285 004a 0028 cmp r0, #0 + 6286 004c 00F0D880 beq .L467 + 6287 .L464: + 6288 .LVL734: +3656:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 6289 .loc 1 3656 5 is_stmt 1 view .LVU2095 +3656:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 6290 .loc 1 3656 8 is_stmt 0 view .LVU2096 + 6291 0050 0128 cmp r0, #1 + 6292 0052 39D0 beq .L485 +3656:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 6293 .loc 1 3656 41 is_stmt 1 discriminator 2 view .LVU2097 +3657:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; /* Update current cluster */ + 6294 .loc 1 3657 5 view .LVU2098 +3657:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; /* Update current cluster */ + 6295 .loc 1 3657 8 is_stmt 0 view .LVU2099 + ARM GAS /tmp/cc2SVLkL.s page 246 + + + 6296 0054 B0F1FF3F cmp r0, #-1 + 6297 0058 3DD0 beq .L486 +3657:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; /* Update current cluster */ + 6298 .loc 1 3657 51 is_stmt 1 discriminator 2 view .LVU2100 +3658:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->obj.sclust == 0) fp->obj.sclust = clst; /* Set start cluster if the first write */ + 6299 .loc 1 3658 5 view .LVU2101 +3658:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->obj.sclust == 0) fp->obj.sclust = clst; /* Set start cluster if the first write */ + 6300 .loc 1 3658 15 is_stmt 0 view .LVU2102 + 6301 005a E061 str r0, [r4, #28] +3659:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6302 .loc 1 3659 5 is_stmt 1 view .LVU2103 +3659:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6303 .loc 1 3659 16 is_stmt 0 view .LVU2104 + 6304 005c A368 ldr r3, [r4, #8] +3659:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6305 .loc 1 3659 8 view .LVU2105 + 6306 005e 03B9 cbnz r3, .L462 +3659:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6307 .loc 1 3659 30 is_stmt 1 discriminator 1 view .LVU2106 +3659:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6308 .loc 1 3659 45 is_stmt 0 discriminator 1 view .LVU2107 + 6309 0060 A060 str r0, [r4, #8] + 6310 .L462: +3664:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + 6311 .loc 1 3664 4 is_stmt 1 view .LVU2108 +3664:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + 6312 .loc 1 3664 8 is_stmt 0 view .LVU2109 + 6313 0062 94F91430 ldrsb r3, [r4, #20] +3664:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + 6314 .loc 1 3664 7 view .LVU2110 + 6315 0066 002B cmp r3, #0 + 6316 0068 3CDB blt .L487 + 6317 .L470: +3669:Middlewares/Third_Party/FatFs/src/ff.c **** if (!sect) ABORT(fs, FR_INT_ERR); + 6318 .loc 1 3669 4 is_stmt 1 view .LVU2111 +3669:Middlewares/Third_Party/FatFs/src/ff.c **** if (!sect) ABORT(fs, FR_INT_ERR); + 6319 .loc 1 3669 11 is_stmt 0 view .LVU2112 + 6320 006a DDF80CB0 ldr fp, [sp, #12] + 6321 006e E169 ldr r1, [r4, #28] + 6322 0070 5846 mov r0, fp + 6323 0072 FFF7FEFF bl clust2sect + 6324 .LVL735: +3670:Middlewares/Third_Party/FatFs/src/ff.c **** sect += csect; + 6325 .loc 1 3670 4 is_stmt 1 view .LVU2113 +3670:Middlewares/Third_Party/FatFs/src/ff.c **** sect += csect; + 6326 .loc 1 3670 7 is_stmt 0 view .LVU2114 + 6327 0076 8146 mov r9, r0 + 6328 0078 0028 cmp r0, #0 + 6329 007a 48D0 beq .L488 +3670:Middlewares/Third_Party/FatFs/src/ff.c **** sect += csect; + 6330 .loc 1 3670 36 is_stmt 1 discriminator 2 view .LVU2115 +3671:Middlewares/Third_Party/FatFs/src/ff.c **** cc = btw / SS(fs); /* When remaining bytes >= sector size, */ + 6331 .loc 1 3671 4 view .LVU2116 +3671:Middlewares/Third_Party/FatFs/src/ff.c **** cc = btw / SS(fs); /* When remaining bytes >= sector size, */ + 6332 .loc 1 3671 9 is_stmt 0 view .LVU2117 + 6333 007c B144 add r9, r9, r6 + 6334 .LVL736: + ARM GAS /tmp/cc2SVLkL.s page 247 + + +3672:Middlewares/Third_Party/FatFs/src/ff.c **** if (cc) { /* Write maximum contiguous sectors directly */ + 6335 .loc 1 3672 4 is_stmt 1 view .LVU2118 +3672:Middlewares/Third_Party/FatFs/src/ff.c **** if (cc) { /* Write maximum contiguous sectors directly */ + 6336 .loc 1 3672 15 is_stmt 0 view .LVU2119 + 6337 007e BBF80C30 ldrh r3, [fp, #12] +3672:Middlewares/Third_Party/FatFs/src/ff.c **** if (cc) { /* Write maximum contiguous sectors directly */ + 6338 .loc 1 3672 7 view .LVU2120 + 6339 0082 B5FBF3FA udiv r10, r5, r3 + 6340 .LVL737: +3673:Middlewares/Third_Party/FatFs/src/ff.c **** if (csect + cc > fs->csize) { /* Clip at cluster boundary */ + 6341 .loc 1 3673 4 is_stmt 1 view .LVU2121 +3673:Middlewares/Third_Party/FatFs/src/ff.c **** if (csect + cc > fs->csize) { /* Clip at cluster boundary */ + 6342 .loc 1 3673 7 is_stmt 0 view .LVU2122 + 6343 0086 AB42 cmp r3, r5 + 6344 0088 5FD8 bhi .L473 +3674:Middlewares/Third_Party/FatFs/src/ff.c **** cc = fs->csize - csect; + 6345 .loc 1 3674 5 is_stmt 1 view .LVU2123 +3674:Middlewares/Third_Party/FatFs/src/ff.c **** cc = fs->csize - csect; + 6346 .loc 1 3674 15 is_stmt 0 view .LVU2124 + 6347 008a 06EB0A03 add r3, r6, r10 +3674:Middlewares/Third_Party/FatFs/src/ff.c **** cc = fs->csize - csect; + 6348 .loc 1 3674 24 view .LVU2125 + 6349 008e BBF80A20 ldrh r2, [fp, #10] +3674:Middlewares/Third_Party/FatFs/src/ff.c **** cc = fs->csize - csect; + 6350 .loc 1 3674 8 view .LVU2126 + 6351 0092 9342 cmp r3, r2 + 6352 0094 01D9 bls .L474 +3675:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6353 .loc 1 3675 6 is_stmt 1 view .LVU2127 +3675:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6354 .loc 1 3675 9 is_stmt 0 view .LVU2128 + 6355 0096 A2EB060A sub r10, r2, r6 + 6356 .LVL738: + 6357 .L474: +3677:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 2 + 6358 .loc 1 3677 5 is_stmt 1 view .LVU2129 +3677:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 2 + 6359 .loc 1 3677 9 is_stmt 0 view .LVU2130 + 6360 009a 5346 mov r3, r10 + 6361 009c 4A46 mov r2, r9 + 6362 009e 3946 mov r1, r7 + 6363 00a0 9BF80100 ldrb r0, [fp, #1] @ zero_extendqisi2 + 6364 00a4 FFF7FEFF bl disk_write + 6365 .LVL739: +3677:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 2 + 6366 .loc 1 3677 8 discriminator 1 view .LVU2131 + 6367 00a8 C0B3 cbz r0, .L475 +3677:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 2 + 6368 .loc 1 3677 57 is_stmt 1 discriminator 1 view .LVU2132 + 6369 00aa 4FF0010A mov r10, #1 + 6370 .LVL740: +3677:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 2 + 6371 .loc 1 3677 57 is_stmt 0 discriminator 1 view .LVU2133 + 6372 00ae 84F815A0 strb r10, [r4, #21] +3677:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 2 + 6373 .loc 1 3677 57 is_stmt 1 discriminator 1 view .LVU2134 + 6374 00b2 CDF804A0 str r10, [sp, #4] + ARM GAS /tmp/cc2SVLkL.s page 248 + + + 6375 .LVL741: + 6376 .L459: +3723:Middlewares/Third_Party/FatFs/src/ff.c **** + 6377 .loc 1 3723 1 is_stmt 0 view .LVU2135 + 6378 00b6 0198 ldr r0, [sp, #4] + 6379 00b8 05B0 add sp, sp, #20 + 6380 .LCFI52: + 6381 .cfi_remember_state + 6382 .cfi_def_cfa_offset 36 + 6383 @ sp needed + 6384 00ba BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 6385 .LVL742: + 6386 .L466: + 6387 .LCFI53: + 6388 .cfi_restore_state +3652:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6389 .loc 1 3652 7 is_stmt 1 view .LVU2136 +3652:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6390 .loc 1 3652 14 is_stmt 0 view .LVU2137 + 6391 00be E169 ldr r1, [r4, #28] + 6392 00c0 2046 mov r0, r4 + 6393 00c2 FFF7FEFF bl create_chain + 6394 .LVL743: +3652:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6395 .loc 1 3652 14 view .LVU2138 + 6396 00c6 C0E7 b .L465 + 6397 .LVL744: + 6398 .L485: +3656:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 6399 .loc 1 3656 20 is_stmt 1 discriminator 1 view .LVU2139 + 6400 00c8 4FF0020A mov r10, #2 + 6401 00cc 84F815A0 strb r10, [r4, #21] +3656:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 6402 .loc 1 3656 20 discriminator 1 view .LVU2140 + 6403 00d0 CDF804A0 str r10, [sp, #4] + 6404 .LVL745: +3656:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 6405 .loc 1 3656 20 is_stmt 0 view .LVU2141 + 6406 00d4 EFE7 b .L459 + 6407 .LVL746: + 6408 .L486: +3657:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; /* Update current cluster */ + 6409 .loc 1 3657 29 is_stmt 1 discriminator 1 view .LVU2142 + 6410 00d6 4FF0010A mov r10, #1 + 6411 00da 84F815A0 strb r10, [r4, #21] +3657:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; /* Update current cluster */ + 6412 .loc 1 3657 29 discriminator 1 view .LVU2143 + 6413 00de CDF804A0 str r10, [sp, #4] + 6414 .LVL747: +3657:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; /* Update current cluster */ + 6415 .loc 1 3657 29 is_stmt 0 view .LVU2144 + 6416 00e2 E8E7 b .L459 + 6417 .LVL748: + 6418 .L487: +3665:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6419 .loc 1 3665 5 is_stmt 1 view .LVU2145 +3665:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + ARM GAS /tmp/cc2SVLkL.s page 249 + + + 6420 .loc 1 3665 9 is_stmt 0 view .LVU2146 + 6421 00e4 0123 movs r3, #1 + 6422 00e6 226A ldr r2, [r4, #32] + 6423 00e8 04F13001 add r1, r4, #48 + 6424 00ec 0398 ldr r0, [sp, #12] + 6425 00ee 4078 ldrb r0, [r0, #1] @ zero_extendqisi2 + 6426 00f0 FFF7FEFF bl disk_write + 6427 .LVL749: +3665:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6428 .loc 1 3665 8 discriminator 1 view .LVU2147 + 6429 00f4 20B9 cbnz r0, .L489 +3665:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6430 .loc 1 3665 84 is_stmt 1 discriminator 2 view .LVU2148 +3666:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6431 .loc 1 3666 5 view .LVU2149 +3666:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6432 .loc 1 3666 7 is_stmt 0 view .LVU2150 + 6433 00f6 237D ldrb r3, [r4, #20] @ zero_extendqisi2 +3666:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6434 .loc 1 3666 14 view .LVU2151 + 6435 00f8 03F07F03 and r3, r3, #127 + 6436 00fc 2375 strb r3, [r4, #20] + 6437 00fe B4E7 b .L470 + 6438 .L489: +3665:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6439 .loc 1 3665 62 is_stmt 1 discriminator 1 view .LVU2152 + 6440 0100 4FF0010A mov r10, #1 + 6441 0104 84F815A0 strb r10, [r4, #21] +3665:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6442 .loc 1 3665 62 discriminator 1 view .LVU2153 + 6443 0108 CDF804A0 str r10, [sp, #4] + 6444 .LVL750: +3665:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6445 .loc 1 3665 62 is_stmt 0 view .LVU2154 + 6446 010c D3E7 b .L459 + 6447 .LVL751: + 6448 .L488: +3670:Middlewares/Third_Party/FatFs/src/ff.c **** sect += csect; + 6449 .loc 1 3670 15 is_stmt 1 discriminator 1 view .LVU2155 + 6450 010e 4FF0020A mov r10, #2 + 6451 0112 84F815A0 strb r10, [r4, #21] +3670:Middlewares/Third_Party/FatFs/src/ff.c **** sect += csect; + 6452 .loc 1 3670 15 discriminator 1 view .LVU2156 + 6453 0116 CDF804A0 str r10, [sp, #4] + 6454 .LVL752: +3670:Middlewares/Third_Party/FatFs/src/ff.c **** sect += csect; + 6455 .loc 1 3670 15 is_stmt 0 view .LVU2157 + 6456 011a CCE7 b .L459 + 6457 .LVL753: + 6458 .L475: +3677:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_MINIMIZE <= 2 + 6459 .loc 1 3677 79 is_stmt 1 discriminator 2 view .LVU2158 +3685:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs)); + 6460 .loc 1 3685 5 view .LVU2159 +3685:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs)); + 6461 .loc 1 3685 11 is_stmt 0 view .LVU2160 + 6462 011c 236A ldr r3, [r4, #32] + ARM GAS /tmp/cc2SVLkL.s page 250 + + +3685:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs)); + 6463 .loc 1 3685 18 view .LVU2161 + 6464 011e A3EB0903 sub r3, r3, r9 +3685:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs)); + 6465 .loc 1 3685 8 view .LVU2162 + 6466 0122 5345 cmp r3, r10 + 6467 0124 04D3 bcc .L490 + 6468 .L476: +3691:Middlewares/Third_Party/FatFs/src/ff.c **** continue; + 6469 .loc 1 3691 5 is_stmt 1 view .LVU2163 +3691:Middlewares/Third_Party/FatFs/src/ff.c **** continue; + 6470 .loc 1 3691 12 is_stmt 0 view .LVU2164 + 6471 0126 039B ldr r3, [sp, #12] + 6472 0128 9E89 ldrh r6, [r3, #12] + 6473 .LVL754: +3691:Middlewares/Third_Party/FatFs/src/ff.c **** continue; + 6474 .loc 1 3691 10 view .LVU2165 + 6475 012a 0AFB06F6 mul r6, r10, r6 + 6476 .LVL755: +3692:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6477 .loc 1 3692 5 is_stmt 1 view .LVU2166 + 6478 012e 2BE0 b .L477 + 6479 .LVL756: + 6480 .L490: +3686:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6481 .loc 1 3686 6 view .LVU2167 +3686:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6482 .loc 1 3686 52 is_stmt 0 view .LVU2168 + 6483 0130 039A ldr r2, [sp, #12] + 6484 0132 9289 ldrh r2, [r2, #12] +3686:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6485 .loc 1 3686 6 view .LVU2169 + 6486 0134 02FB0371 mla r1, r2, r3, r7 + 6487 0138 04F13000 add r0, r4, #48 + 6488 013c FFF7FEFF bl mem_cpy + 6489 .LVL757: +3687:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6490 .loc 1 3687 6 is_stmt 1 view .LVU2170 +3687:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6491 .loc 1 3687 8 is_stmt 0 view .LVU2171 + 6492 0140 237D ldrb r3, [r4, #20] @ zero_extendqisi2 +3687:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6493 .loc 1 3687 15 view .LVU2172 + 6494 0142 03F07F03 and r3, r3, #127 + 6495 0146 2375 strb r3, [r4, #20] + 6496 0148 EDE7 b .L476 + 6497 .L473: +3700:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr < fp->obj.objsize && + 6498 .loc 1 3700 4 is_stmt 1 view .LVU2173 +3700:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr < fp->obj.objsize && + 6499 .loc 1 3700 10 is_stmt 0 view .LVU2174 + 6500 014a 236A ldr r3, [r4, #32] +3700:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr < fp->obj.objsize && + 6501 .loc 1 3700 7 view .LVU2175 + 6502 014c 4B45 cmp r3, r9 + 6503 014e 03D0 beq .L478 +3701:Middlewares/Third_Party/FatFs/src/ff.c **** disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) { + ARM GAS /tmp/cc2SVLkL.s page 251 + + + 6504 .loc 1 3701 7 view .LVU2176 + 6505 0150 A269 ldr r2, [r4, #24] +3701:Middlewares/Third_Party/FatFs/src/ff.c **** disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) { + 6506 .loc 1 3701 23 view .LVU2177 + 6507 0152 E368 ldr r3, [r4, #12] +3700:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr < fp->obj.objsize && + 6508 .loc 1 3700 25 discriminator 1 view .LVU2178 + 6509 0154 9A42 cmp r2, r3 + 6510 0156 42D3 bcc .L491 + 6511 .L478: +3703:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6512 .loc 1 3703 28 is_stmt 1 view .LVU2179 +3706:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6513 .loc 1 3706 4 view .LVU2180 +3706:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6514 .loc 1 3706 13 is_stmt 0 view .LVU2181 + 6515 0158 C4F82090 str r9, [r4, #32] + 6516 .LVL758: + 6517 .L461: +3708:Middlewares/Third_Party/FatFs/src/ff.c **** if (wcnt > btw) wcnt = btw; /* Clip it by btw if needed */ + 6518 .loc 1 3708 3 is_stmt 1 view .LVU2182 +3708:Middlewares/Third_Party/FatFs/src/ff.c **** if (wcnt > btw) wcnt = btw; /* Clip it by btw if needed */ + 6519 .loc 1 3708 10 is_stmt 0 view .LVU2183 + 6520 015c 039B ldr r3, [sp, #12] + 6521 015e 9E89 ldrh r6, [r3, #12] +3708:Middlewares/Third_Party/FatFs/src/ff.c **** if (wcnt > btw) wcnt = btw; /* Clip it by btw if needed */ + 6522 .loc 1 3708 27 view .LVU2184 + 6523 0160 A369 ldr r3, [r4, #24] +3708:Middlewares/Third_Party/FatFs/src/ff.c **** if (wcnt > btw) wcnt = btw; /* Clip it by btw if needed */ + 6524 .loc 1 3708 34 view .LVU2185 + 6525 0162 B3FBF6F2 udiv r2, r3, r6 + 6526 0166 06FB1233 mls r3, r6, r2, r3 +3708:Middlewares/Third_Party/FatFs/src/ff.c **** if (wcnt > btw) wcnt = btw; /* Clip it by btw if needed */ + 6527 .loc 1 3708 8 view .LVU2186 + 6528 016a F61A subs r6, r6, r3 + 6529 .LVL759: +3709:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY + 6530 .loc 1 3709 3 is_stmt 1 view .LVU2187 +3709:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY + 6531 .loc 1 3709 6 is_stmt 0 view .LVU2188 + 6532 016c B542 cmp r5, r6 + 6533 016e 00D2 bcs .L479 +3709:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_TINY + 6534 .loc 1 3709 24 discriminator 1 view .LVU2189 + 6535 0170 2E46 mov r6, r5 + 6536 .LVL760: + 6537 .L479: +3715:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag |= FA_DIRTY; + 6538 .loc 1 3715 3 is_stmt 1 view .LVU2190 +3715:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag |= FA_DIRTY; + 6539 .loc 1 3715 11 is_stmt 0 view .LVU2191 + 6540 0172 04F13000 add r0, r4, #48 +3715:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag |= FA_DIRTY; + 6541 .loc 1 3715 3 view .LVU2192 + 6542 0176 3246 mov r2, r6 + 6543 0178 3946 mov r1, r7 + 6544 017a 1844 add r0, r0, r3 + ARM GAS /tmp/cc2SVLkL.s page 252 + + + 6545 017c FFF7FEFF bl mem_cpy + 6546 .LVL761: +3716:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 6547 .loc 1 3716 3 is_stmt 1 view .LVU2193 +3716:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 6548 .loc 1 3716 5 is_stmt 0 view .LVU2194 + 6549 0180 237D ldrb r3, [r4, #20] @ zero_extendqisi2 +3716:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 6550 .loc 1 3716 12 view .LVU2195 + 6551 0182 63F07F03 orn r3, r3, #127 + 6552 0186 2375 strb r3, [r4, #20] + 6553 .L477: +3636:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + 6554 .loc 1 3636 124 is_stmt 1 view .LVU2196 +3636:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + 6555 .loc 1 3636 9 is_stmt 0 view .LVU2197 + 6556 0188 3744 add r7, r7, r6 + 6557 .LVL762: +3636:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + 6558 .loc 1 3636 20 view .LVU2198 + 6559 018a A369 ldr r3, [r4, #24] +3636:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + 6560 .loc 1 3636 27 view .LVU2199 + 6561 018c 3344 add r3, r3, r6 + 6562 018e A361 str r3, [r4, #24] +3636:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + 6563 .loc 1 3636 73 view .LVU2200 + 6564 0190 E268 ldr r2, [r4, #12] +3636:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + 6565 .loc 1 3636 94 view .LVU2201 + 6566 0192 9342 cmp r3, r2 + 6567 0194 38BF it cc + 6568 0196 1346 movcc r3, r2 +3636:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + 6569 .loc 1 3636 52 view .LVU2202 + 6570 0198 E360 str r3, [r4, #12] +3636:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + 6571 .loc 1 3636 113 view .LVU2203 + 6572 019a D8F80030 ldr r3, [r8] +3636:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + 6573 .loc 1 3636 117 view .LVU2204 + 6574 019e 3344 add r3, r3, r6 + 6575 01a0 C8F80030 str r3, [r8] +3636:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */ + 6576 .loc 1 3636 130 view .LVU2205 + 6577 01a4 AD1B subs r5, r5, r6 + 6578 .LVL763: + 6579 .L480: +3635:Middlewares/Third_Party/FatFs/src/ff.c **** wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp-> + 6580 .loc 1 3635 11 is_stmt 1 view .LVU2206 + 6581 01a6 5DB3 cbz r5, .L467 +3637:Middlewares/Third_Party/FatFs/src/ff.c **** csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1); /* Sector offset in the cluster */ + 6582 .loc 1 3637 3 view .LVU2207 +3637:Middlewares/Third_Party/FatFs/src/ff.c **** csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1); /* Sector offset in the cluster */ + 6583 .loc 1 3637 9 is_stmt 0 view .LVU2208 + 6584 01a8 A169 ldr r1, [r4, #24] +3637:Middlewares/Third_Party/FatFs/src/ff.c **** csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1); /* Sector offset in the cluster */ + ARM GAS /tmp/cc2SVLkL.s page 253 + + + 6585 .loc 1 3637 18 view .LVU2209 + 6586 01aa 039A ldr r2, [sp, #12] + 6587 01ac 9689 ldrh r6, [r2, #12] +3637:Middlewares/Third_Party/FatFs/src/ff.c **** csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1); /* Sector offset in the cluster */ + 6588 .loc 1 3637 16 view .LVU2210 + 6589 01ae B1FBF6F3 udiv r3, r1, r6 + 6590 01b2 06FB1313 mls r3, r6, r3, r1 +3637:Middlewares/Third_Party/FatFs/src/ff.c **** csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1); /* Sector offset in the cluster */ + 6591 .loc 1 3637 6 view .LVU2211 + 6592 01b6 002B cmp r3, #0 + 6593 01b8 D0D1 bne .L461 +3638:Middlewares/Third_Party/FatFs/src/ff.c **** if (csect == 0) { /* On the cluster boundary? */ + 6594 .loc 1 3638 4 is_stmt 1 view .LVU2212 +3638:Middlewares/Third_Party/FatFs/src/ff.c **** if (csect == 0) { /* On the cluster boundary? */ + 6595 .loc 1 3638 28 is_stmt 0 view .LVU2213 + 6596 01ba B1FBF6F6 udiv r6, r1, r6 +3638:Middlewares/Third_Party/FatFs/src/ff.c **** if (csect == 0) { /* On the cluster boundary? */ + 6597 .loc 1 3638 43 view .LVU2214 + 6598 01be 5389 ldrh r3, [r2, #10] +3638:Middlewares/Third_Party/FatFs/src/ff.c **** if (csect == 0) { /* On the cluster boundary? */ + 6599 .loc 1 3638 51 view .LVU2215 + 6600 01c0 013B subs r3, r3, #1 + 6601 .LVL764: +3639:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr == 0) { /* On the top of the file? */ + 6602 .loc 1 3639 4 is_stmt 1 view .LVU2216 +3639:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr == 0) { /* On the top of the file? */ + 6603 .loc 1 3639 7 is_stmt 0 view .LVU2217 + 6604 01c2 1E40 ands r6, r6, r3 + 6605 .LVL765: +3639:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr == 0) { /* On the top of the file? */ + 6606 .loc 1 3639 7 view .LVU2218 + 6607 01c4 7FF44DAF bne .L462 +3640:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fp->obj.sclust; /* Follow from the origin */ + 6608 .loc 1 3640 5 is_stmt 1 view .LVU2219 +3640:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fp->obj.sclust; /* Follow from the origin */ + 6609 .loc 1 3640 8 is_stmt 0 view .LVU2220 + 6610 01c8 0029 cmp r1, #0 + 6611 01ca 7FF438AF bne .L463 +3641:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0) { /* If no cluster is allocated, */ + 6612 .loc 1 3641 6 is_stmt 1 view .LVU2221 +3641:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0) { /* If no cluster is allocated, */ + 6613 .loc 1 3641 11 is_stmt 0 view .LVU2222 + 6614 01ce A068 ldr r0, [r4, #8] + 6615 .LVL766: +3642:Middlewares/Third_Party/FatFs/src/ff.c **** clst = create_chain(&fp->obj, 0); /* create a new cluster chain */ + 6616 .loc 1 3642 6 is_stmt 1 view .LVU2223 +3642:Middlewares/Third_Party/FatFs/src/ff.c **** clst = create_chain(&fp->obj, 0); /* create a new cluster chain */ + 6617 .loc 1 3642 9 is_stmt 0 view .LVU2224 + 6618 01d0 0028 cmp r0, #0 + 6619 01d2 7FF43DAF bne .L464 +3643:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6620 .loc 1 3643 7 is_stmt 1 view .LVU2225 +3643:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6621 .loc 1 3643 14 is_stmt 0 view .LVU2226 + 6622 01d6 2046 mov r0, r4 + 6623 .LVL767: +3643:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 254 + + + 6624 .loc 1 3643 14 view .LVU2227 + 6625 01d8 FFF7FEFF bl create_chain + 6626 .LVL768: +3643:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6627 .loc 1 3643 14 view .LVU2228 + 6628 01dc 35E7 b .L465 + 6629 .LVL769: + 6630 .L491: +3702:Middlewares/Third_Party/FatFs/src/ff.c **** ABORT(fs, FR_DISK_ERR); + 6631 .loc 1 3702 5 view .LVU2229 + 6632 01de 0123 movs r3, #1 + 6633 01e0 4A46 mov r2, r9 + 6634 01e2 04F13001 add r1, r4, #48 + 6635 01e6 9BF80100 ldrb r0, [fp, #1] @ zero_extendqisi2 + 6636 01ea FFF7FEFF bl disk_read + 6637 .LVL770: +3701:Middlewares/Third_Party/FatFs/src/ff.c **** disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) { + 6638 .loc 1 3701 32 view .LVU2230 + 6639 01ee 0028 cmp r0, #0 + 6640 01f0 B2D0 beq .L478 +3703:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6641 .loc 1 3703 6 is_stmt 1 view .LVU2231 + 6642 01f2 4FF0010A mov r10, #1 + 6643 .LVL771: +3703:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6644 .loc 1 3703 6 is_stmt 0 view .LVU2232 + 6645 01f6 84F815A0 strb r10, [r4, #21] +3703:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6646 .loc 1 3703 6 is_stmt 1 view .LVU2233 + 6647 01fa CDF804A0 str r10, [sp, #4] + 6648 .LVL772: +3703:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6649 .loc 1 3703 6 is_stmt 0 view .LVU2234 + 6650 01fe 5AE7 b .L459 + 6651 .LVL773: + 6652 .L467: +3720:Middlewares/Third_Party/FatFs/src/ff.c **** + 6653 .loc 1 3720 2 is_stmt 1 view .LVU2235 +3720:Middlewares/Third_Party/FatFs/src/ff.c **** + 6654 .loc 1 3720 4 is_stmt 0 view .LVU2236 + 6655 0200 237D ldrb r3, [r4, #20] @ zero_extendqisi2 +3720:Middlewares/Third_Party/FatFs/src/ff.c **** + 6656 .loc 1 3720 11 view .LVU2237 + 6657 0202 43F04003 orr r3, r3, #64 + 6658 0206 2375 strb r3, [r4, #20] +3722:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6659 .loc 1 3722 2 is_stmt 1 view .LVU2238 + 6660 0208 55E7 b .L459 + 6661 .LVL774: + 6662 .L482: +3628:Middlewares/Third_Party/FatFs/src/ff.c **** + 6663 .loc 1 3628 30 is_stmt 0 discriminator 1 view .LVU2239 + 6664 020a 0723 movs r3, #7 + 6665 020c 0193 str r3, [sp, #4] + 6666 .LVL775: +3628:Middlewares/Third_Party/FatFs/src/ff.c **** + 6667 .loc 1 3628 30 discriminator 1 view .LVU2240 + ARM GAS /tmp/cc2SVLkL.s page 255 + + + 6668 020e 52E7 b .L459 + 6669 .cfi_endproc + 6670 .LFE1224: + 6672 .section .text.putc_bfd,"ax",%progbits + 6673 .align 1 + 6674 .syntax unified + 6675 .thumb + 6676 .thumb_func + 6678 putc_bfd: + 6679 .LVL776: + 6680 .LFB1239: +5921:Middlewares/Third_Party/FatFs/src/ff.c **** UINT bw; + 6681 .loc 1 5921 1 is_stmt 1 view -0 + 6682 .cfi_startproc + 6683 @ args = 0, pretend = 0, frame = 8 + 6684 @ frame_needed = 0, uses_anonymous_args = 0 +5921:Middlewares/Third_Party/FatFs/src/ff.c **** UINT bw; + 6685 .loc 1 5921 1 is_stmt 0 view .LVU2242 + 6686 0000 70B5 push {r4, r5, r6, lr} + 6687 .LCFI54: + 6688 .cfi_def_cfa_offset 16 + 6689 .cfi_offset 4, -16 + 6690 .cfi_offset 5, -12 + 6691 .cfi_offset 6, -8 + 6692 .cfi_offset 14, -4 + 6693 0002 82B0 sub sp, sp, #8 + 6694 .LCFI55: + 6695 .cfi_def_cfa_offset 24 + 6696 0004 0446 mov r4, r0 + 6697 0006 0D46 mov r5, r1 +5922:Middlewares/Third_Party/FatFs/src/ff.c **** int i; + 6698 .loc 1 5922 2 is_stmt 1 view .LVU2243 +5923:Middlewares/Third_Party/FatFs/src/ff.c **** + 6699 .loc 1 5923 2 view .LVU2244 +5926:Middlewares/Third_Party/FatFs/src/ff.c **** putc_bfd(pb, '\r'); + 6700 .loc 1 5926 2 view .LVU2245 +5926:Middlewares/Third_Party/FatFs/src/ff.c **** putc_bfd(pb, '\r'); + 6701 .loc 1 5926 5 is_stmt 0 view .LVU2246 + 6702 0008 0A29 cmp r1, #10 + 6703 000a 0DD0 beq .L499 + 6704 .LVL777: + 6705 .L493: +5930:Middlewares/Third_Party/FatFs/src/ff.c **** if (i < 0) return; + 6706 .loc 1 5930 2 is_stmt 1 view .LVU2247 +5930:Middlewares/Third_Party/FatFs/src/ff.c **** if (i < 0) return; + 6707 .loc 1 5930 4 is_stmt 0 view .LVU2248 + 6708 000c 6368 ldr r3, [r4, #4] + 6709 .LVL778: +5931:Middlewares/Third_Party/FatFs/src/ff.c **** + 6710 .loc 1 5931 2 is_stmt 1 view .LVU2249 +5931:Middlewares/Third_Party/FatFs/src/ff.c **** + 6711 .loc 1 5931 5 is_stmt 0 view .LVU2250 + 6712 000e 002B cmp r3, #0 + 6713 0010 08DB blt .L492 +5960:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 6714 .loc 1 5960 2 is_stmt 1 view .LVU2251 +5960:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + ARM GAS /tmp/cc2SVLkL.s page 256 + + + 6715 .loc 1 5960 11 is_stmt 0 view .LVU2252 + 6716 0012 5E1C adds r6, r3, #1 + 6717 .LVL779: +5960:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 6718 .loc 1 5960 15 view .LVU2253 + 6719 0014 2344 add r3, r3, r4 + 6720 0016 1D73 strb r5, [r3, #12] +5963:Middlewares/Third_Party/FatFs/src/ff.c **** f_write(pb->fp, pb->buf, (UINT)i, &bw); + 6721 .loc 1 5963 2 is_stmt 1 view .LVU2254 +5963:Middlewares/Third_Party/FatFs/src/ff.c **** f_write(pb->fp, pb->buf, (UINT)i, &bw); + 6722 .loc 1 5963 5 is_stmt 0 view .LVU2255 + 6723 0018 3C2E cmp r6, #60 + 6724 001a 09DC bgt .L500 + 6725 .LVL780: + 6726 .L496: +5967:Middlewares/Third_Party/FatFs/src/ff.c **** pb->nchr++; + 6727 .loc 1 5967 2 is_stmt 1 view .LVU2256 +5967:Middlewares/Third_Party/FatFs/src/ff.c **** pb->nchr++; + 6728 .loc 1 5967 10 is_stmt 0 view .LVU2257 + 6729 001c 6660 str r6, [r4, #4] +5968:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6730 .loc 1 5968 2 is_stmt 1 view .LVU2258 +5968:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6731 .loc 1 5968 4 is_stmt 0 view .LVU2259 + 6732 001e A368 ldr r3, [r4, #8] +5968:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6733 .loc 1 5968 10 view .LVU2260 + 6734 0020 0133 adds r3, r3, #1 + 6735 0022 A360 str r3, [r4, #8] + 6736 .LVL781: + 6737 .L492: +5969:Middlewares/Third_Party/FatFs/src/ff.c **** + 6738 .loc 1 5969 1 view .LVU2261 + 6739 0024 02B0 add sp, sp, #8 + 6740 .LCFI56: + 6741 .cfi_remember_state + 6742 .cfi_def_cfa_offset 16 + 6743 @ sp needed + 6744 0026 70BD pop {r4, r5, r6, pc} + 6745 .LVL782: + 6746 .L499: + 6747 .LCFI57: + 6748 .cfi_restore_state +5927:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6749 .loc 1 5927 3 is_stmt 1 view .LVU2262 + 6750 0028 0D21 movs r1, #13 + 6751 .LVL783: +5927:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6752 .loc 1 5927 3 is_stmt 0 view .LVU2263 + 6753 002a FFF7E9FF bl putc_bfd + 6754 .LVL784: +5927:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6755 .loc 1 5927 3 view .LVU2264 + 6756 002e EDE7 b .L493 + 6757 .LVL785: + 6758 .L500: +5964:Middlewares/Third_Party/FatFs/src/ff.c **** i = (bw == (UINT)i) ? 0 : -1; + ARM GAS /tmp/cc2SVLkL.s page 257 + + + 6759 .loc 1 5964 3 is_stmt 1 view .LVU2265 +5964:Middlewares/Third_Party/FatFs/src/ff.c **** i = (bw == (UINT)i) ? 0 : -1; + 6760 .loc 1 5964 21 is_stmt 0 view .LVU2266 + 6761 0030 2146 mov r1, r4 +5964:Middlewares/Third_Party/FatFs/src/ff.c **** i = (bw == (UINT)i) ? 0 : -1; + 6762 .loc 1 5964 3 view .LVU2267 + 6763 0032 51F80C0B ldr r0, [r1], #12 + 6764 0036 01AB add r3, sp, #4 + 6765 0038 3246 mov r2, r6 + 6766 003a FFF7FEFF bl f_write + 6767 .LVL786: +5965:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6768 .loc 1 5965 3 is_stmt 1 view .LVU2268 +5965:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6769 .loc 1 5965 11 is_stmt 0 view .LVU2269 + 6770 003e 019B ldr r3, [sp, #4] +5965:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6771 .loc 1 5965 27 view .LVU2270 + 6772 0040 9E42 cmp r6, r3 + 6773 0042 02D0 beq .L501 +5965:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6774 .loc 1 5965 27 discriminator 2 view .LVU2271 + 6775 0044 4FF0FF36 mov r6, #-1 + 6776 .LVL787: +5965:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6777 .loc 1 5965 27 discriminator 2 view .LVU2272 + 6778 0048 E8E7 b .L496 + 6779 .LVL788: + 6780 .L501: +5965:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6781 .loc 1 5965 27 discriminator 1 view .LVU2273 + 6782 004a 0026 movs r6, #0 + 6783 .LVL789: +5965:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6784 .loc 1 5965 27 discriminator 1 view .LVU2274 + 6785 004c E6E7 b .L496 + 6786 .cfi_endproc + 6787 .LFE1239: + 6789 .section .text.putc_flush,"ax",%progbits + 6790 .align 1 + 6791 .syntax unified + 6792 .thumb + 6793 .thumb_func + 6795 putc_flush: + 6796 .LVL790: + 6797 .LFB1240: +5976:Middlewares/Third_Party/FatFs/src/ff.c **** UINT nw; + 6798 .loc 1 5976 1 is_stmt 1 view -0 + 6799 .cfi_startproc + 6800 @ args = 0, pretend = 0, frame = 8 + 6801 @ frame_needed = 0, uses_anonymous_args = 0 +5977:Middlewares/Third_Party/FatFs/src/ff.c **** + 6802 .loc 1 5977 2 view .LVU2276 +5979:Middlewares/Third_Party/FatFs/src/ff.c **** && f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK + 6803 .loc 1 5979 2 view .LVU2277 +5979:Middlewares/Third_Party/FatFs/src/ff.c **** && f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK + 6804 .loc 1 5979 11 is_stmt 0 view .LVU2278 + ARM GAS /tmp/cc2SVLkL.s page 258 + + + 6805 0000 4268 ldr r2, [r0, #4] +5979:Middlewares/Third_Party/FatFs/src/ff.c **** && f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK + 6806 .loc 1 5979 5 view .LVU2279 + 6807 0002 002A cmp r2, #0 + 6808 0004 10DB blt .L504 +5976:Middlewares/Third_Party/FatFs/src/ff.c **** UINT nw; + 6809 .loc 1 5976 1 view .LVU2280 + 6810 0006 10B5 push {r4, lr} + 6811 .LCFI58: + 6812 .cfi_def_cfa_offset 8 + 6813 .cfi_offset 4, -8 + 6814 .cfi_offset 14, -4 + 6815 0008 82B0 sub sp, sp, #8 + 6816 .LCFI59: + 6817 .cfi_def_cfa_offset 16 + 6818 000a 0446 mov r4, r0 +5980:Middlewares/Third_Party/FatFs/src/ff.c **** && (UINT)pb->idx == nw) return pb->nchr; + 6819 .loc 1 5980 24 view .LVU2281 + 6820 000c 0146 mov r1, r0 +5980:Middlewares/Third_Party/FatFs/src/ff.c **** && (UINT)pb->idx == nw) return pb->nchr; + 6821 .loc 1 5980 6 view .LVU2282 + 6822 000e 51F80C0B ldr r0, [r1], #12 + 6823 .LVL791: +5980:Middlewares/Third_Party/FatFs/src/ff.c **** && (UINT)pb->idx == nw) return pb->nchr; + 6824 .loc 1 5980 6 view .LVU2283 + 6825 0012 01AB add r3, sp, #4 + 6826 0014 FFF7FEFF bl f_write + 6827 .LVL792: +5980:Middlewares/Third_Party/FatFs/src/ff.c **** && (UINT)pb->idx == nw) return pb->nchr; + 6828 .loc 1 5980 3 discriminator 1 view .LVU2284 + 6829 0018 48B9 cbnz r0, .L505 +5981:Middlewares/Third_Party/FatFs/src/ff.c **** return EOF; + 6830 .loc 1 5981 14 view .LVU2285 + 6831 001a 6268 ldr r2, [r4, #4] +5981:Middlewares/Third_Party/FatFs/src/ff.c **** return EOF; + 6832 .loc 1 5981 20 view .LVU2286 + 6833 001c 019B ldr r3, [sp, #4] +5981:Middlewares/Third_Party/FatFs/src/ff.c **** return EOF; + 6834 .loc 1 5981 3 view .LVU2287 + 6835 001e 9A42 cmp r2, r3 + 6836 0020 08D1 bne .L506 +5981:Middlewares/Third_Party/FatFs/src/ff.c **** return EOF; + 6837 .loc 1 5981 27 is_stmt 1 discriminator 1 view .LVU2288 +5981:Middlewares/Third_Party/FatFs/src/ff.c **** return EOF; + 6838 .loc 1 5981 36 is_stmt 0 discriminator 1 view .LVU2289 + 6839 0022 A068 ldr r0, [r4, #8] + 6840 .L502: +5983:Middlewares/Third_Party/FatFs/src/ff.c **** + 6841 .loc 1 5983 1 view .LVU2290 + 6842 0024 02B0 add sp, sp, #8 + 6843 .LCFI60: + 6844 .cfi_def_cfa_offset 8 + 6845 @ sp needed + 6846 0026 10BD pop {r4, pc} + 6847 .LVL793: + 6848 .L504: + 6849 .LCFI61: + ARM GAS /tmp/cc2SVLkL.s page 259 + + + 6850 .cfi_def_cfa_offset 0 + 6851 .cfi_restore 4 + 6852 .cfi_restore 14 +5982:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6853 .loc 1 5982 9 view .LVU2291 + 6854 0028 4FF0FF30 mov r0, #-1 + 6855 .LVL794: +5983:Middlewares/Third_Party/FatFs/src/ff.c **** + 6856 .loc 1 5983 1 view .LVU2292 + 6857 002c 7047 bx lr + 6858 .LVL795: + 6859 .L505: + 6860 .LCFI62: + 6861 .cfi_def_cfa_offset 16 + 6862 .cfi_offset 4, -8 + 6863 .cfi_offset 14, -4 +5982:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6864 .loc 1 5982 9 view .LVU2293 + 6865 002e 4FF0FF30 mov r0, #-1 + 6866 0032 F7E7 b .L502 + 6867 .L506: + 6868 0034 4FF0FF30 mov r0, #-1 + 6869 0038 F4E7 b .L502 + 6870 .cfi_endproc + 6871 .LFE1240: + 6873 .section .text.f_sync,"ax",%progbits + 6874 .align 1 + 6875 .global f_sync + 6876 .syntax unified + 6877 .thumb + 6878 .thumb_func + 6880 f_sync: + 6881 .LVL796: + 6882 .LFB1225: +3735:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 6883 .loc 1 3735 1 is_stmt 1 view -0 + 6884 .cfi_startproc + 6885 @ args = 0, pretend = 0, frame = 8 + 6886 @ frame_needed = 0, uses_anonymous_args = 0 +3735:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 6887 .loc 1 3735 1 is_stmt 0 view .LVU2295 + 6888 0000 70B5 push {r4, r5, r6, lr} + 6889 .LCFI63: + 6890 .cfi_def_cfa_offset 16 + 6891 .cfi_offset 4, -16 + 6892 .cfi_offset 5, -12 + 6893 .cfi_offset 6, -8 + 6894 .cfi_offset 14, -4 + 6895 0002 82B0 sub sp, sp, #8 + 6896 .LCFI64: + 6897 .cfi_def_cfa_offset 24 + 6898 0004 0446 mov r4, r0 +3736:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; + 6899 .loc 1 3736 2 is_stmt 1 view .LVU2296 +3737:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD tm; + 6900 .loc 1 3737 2 view .LVU2297 +3738:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE *dir; + ARM GAS /tmp/cc2SVLkL.s page 260 + + + 6901 .loc 1 3738 2 view .LVU2298 +3739:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 6902 .loc 1 3739 2 view .LVU2299 +3745:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 6903 .loc 1 3745 2 view .LVU2300 +3745:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 6904 .loc 1 3745 8 is_stmt 0 view .LVU2301 + 6905 0006 01A9 add r1, sp, #4 + 6906 0008 FFF7FEFF bl validate + 6907 .LVL797: +3746:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->flag & FA_MODIFIED) { /* Is there any change to the file? */ + 6908 .loc 1 3746 2 is_stmt 1 view .LVU2302 +3746:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->flag & FA_MODIFIED) { /* Is there any change to the file? */ + 6909 .loc 1 3746 5 is_stmt 0 view .LVU2303 + 6910 000c 70B9 cbnz r0, .L512 +3747:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 6911 .loc 1 3747 3 is_stmt 1 view .LVU2304 +3747:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 6912 .loc 1 3747 9 is_stmt 0 view .LVU2305 + 6913 000e 237D ldrb r3, [r4, #20] @ zero_extendqisi2 +3747:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 6914 .loc 1 3747 6 view .LVU2306 + 6915 0010 13F0400F tst r3, #64 + 6916 0014 0AD0 beq .L512 +3749:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR); + 6917 .loc 1 3749 4 is_stmt 1 view .LVU2307 +3749:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR); + 6918 .loc 1 3749 7 is_stmt 0 view .LVU2308 + 6919 0016 13F0800F tst r3, #128 + 6920 001a 09D1 bne .L516 + 6921 .L513: +3755:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 6922 .loc 1 3755 4 is_stmt 1 view .LVU2309 +3755:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 6923 .loc 1 3755 9 is_stmt 0 view .LVU2310 + 6924 001c FFF7FEFF bl get_fattime + 6925 .LVL798: + 6926 0020 0546 mov r5, r0 + 6927 .LVL799: +3785:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 6928 .loc 1 3785 5 is_stmt 1 view .LVU2311 +3785:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 6929 .loc 1 3785 11 is_stmt 0 view .LVU2312 + 6930 0022 616A ldr r1, [r4, #36] + 6931 0024 0198 ldr r0, [sp, #4] + 6932 .LVL800: +3785:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 6933 .loc 1 3785 11 view .LVU2313 + 6934 0026 FFF7FEFF bl move_window + 6935 .LVL801: +3786:Middlewares/Third_Party/FatFs/src/ff.c **** dir = fp->dir_ptr; + 6936 .loc 1 3786 5 is_stmt 1 view .LVU2314 +3786:Middlewares/Third_Party/FatFs/src/ff.c **** dir = fp->dir_ptr; + 6937 .loc 1 3786 8 is_stmt 0 view .LVU2315 + 6938 002a 78B1 cbz r0, .L517 + 6939 .LVL802: + 6940 .L512: + ARM GAS /tmp/cc2SVLkL.s page 261 + + +3802:Middlewares/Third_Party/FatFs/src/ff.c **** + 6941 .loc 1 3802 1 view .LVU2316 + 6942 002c 02B0 add sp, sp, #8 + 6943 .LCFI65: + 6944 .cfi_remember_state + 6945 .cfi_def_cfa_offset 16 + 6946 @ sp needed + 6947 002e 70BD pop {r4, r5, r6, pc} + 6948 .LVL803: + 6949 .L516: + 6950 .LCFI66: + 6951 .cfi_restore_state +3750:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6952 .loc 1 3750 5 is_stmt 1 view .LVU2317 +3750:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6953 .loc 1 3750 9 is_stmt 0 view .LVU2318 + 6954 0030 0123 movs r3, #1 + 6955 0032 226A ldr r2, [r4, #32] + 6956 0034 04F13001 add r1, r4, #48 + 6957 0038 0198 ldr r0, [sp, #4] + 6958 003a 4078 ldrb r0, [r0, #1] @ zero_extendqisi2 + 6959 003c FFF7FEFF bl disk_write + 6960 .LVL804: +3750:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 6961 .loc 1 3750 8 discriminator 1 view .LVU2319 + 6962 0040 40BB cbnz r0, .L514 +3751:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6963 .loc 1 3751 5 is_stmt 1 view .LVU2320 +3751:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6964 .loc 1 3751 7 is_stmt 0 view .LVU2321 + 6965 0042 237D ldrb r3, [r4, #20] @ zero_extendqisi2 +3751:Middlewares/Third_Party/FatFs/src/ff.c **** } + 6966 .loc 1 3751 14 view .LVU2322 + 6967 0044 03F07F03 and r3, r3, #127 + 6968 0048 2375 strb r3, [r4, #20] + 6969 004a E7E7 b .L513 + 6970 .LVL805: + 6971 .L517: +3787:Middlewares/Third_Party/FatFs/src/ff.c **** dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ + 6972 .loc 1 3787 6 is_stmt 1 view .LVU2323 +3787:Middlewares/Third_Party/FatFs/src/ff.c **** dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ + 6973 .loc 1 3787 10 is_stmt 0 view .LVU2324 + 6974 004c A66A ldr r6, [r4, #40] + 6975 .LVL806: +3788:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fp->obj.fs, dir, fp->obj.sclust); /* Update file allocation info */ + 6976 .loc 1 3788 6 is_stmt 1 view .LVU2325 +3788:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fp->obj.fs, dir, fp->obj.sclust); /* Update file allocation info */ + 6977 .loc 1 3788 9 is_stmt 0 view .LVU2326 + 6978 004e F37A ldrb r3, [r6, #11] @ zero_extendqisi2 +3788:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fp->obj.fs, dir, fp->obj.sclust); /* Update file allocation info */ + 6979 .loc 1 3788 20 view .LVU2327 + 6980 0050 43F02003 orr r3, r3, #32 + 6981 0054 F372 strb r3, [r6, #11] +3789:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize); /* Update file size */ + 6982 .loc 1 3789 6 is_stmt 1 view .LVU2328 + 6983 0056 A268 ldr r2, [r4, #8] + 6984 0058 3146 mov r1, r6 + ARM GAS /tmp/cc2SVLkL.s page 262 + + + 6985 005a 2068 ldr r0, [r4] + 6986 .LVL807: +3789:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize); /* Update file size */ + 6987 .loc 1 3789 6 is_stmt 0 view .LVU2329 + 6988 005c FFF7FEFF bl st_clust + 6989 .LVL808: +3790:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(dir + DIR_ModTime, tm); /* Update modified time */ + 6990 .loc 1 3790 6 is_stmt 1 view .LVU2330 + 6991 0060 E168 ldr r1, [r4, #12] + 6992 0062 06F11C00 add r0, r6, #28 + 6993 0066 FFF7FEFF bl st_dword + 6994 .LVL809: +3791:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(dir + DIR_LstAccDate, 0); + 6995 .loc 1 3791 6 view .LVU2331 + 6996 006a 2946 mov r1, r5 + 6997 006c 06F11600 add r0, r6, #22 + 6998 0070 FFF7FEFF bl st_dword + 6999 .LVL810: +3792:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 7000 .loc 1 3792 6 view .LVU2332 + 7001 0074 0021 movs r1, #0 + 7002 0076 06F11200 add r0, r6, #18 + 7003 007a FFF7FEFF bl st_word + 7004 .LVL811: +3793:Middlewares/Third_Party/FatFs/src/ff.c **** res = sync_fs(fs); /* Restore it to the directory */ + 7005 .loc 1 3793 6 view .LVU2333 +3793:Middlewares/Third_Party/FatFs/src/ff.c **** res = sync_fs(fs); /* Restore it to the directory */ + 7006 .loc 1 3793 16 is_stmt 0 view .LVU2334 + 7007 007e 019B ldr r3, [sp, #4] + 7008 0080 0122 movs r2, #1 + 7009 0082 DA70 strb r2, [r3, #3] +3794:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_MODIFIED; + 7010 .loc 1 3794 6 is_stmt 1 view .LVU2335 +3794:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_MODIFIED; + 7011 .loc 1 3794 12 is_stmt 0 view .LVU2336 + 7012 0084 0198 ldr r0, [sp, #4] + 7013 0086 FFF7FEFF bl sync_fs + 7014 .LVL812: +3795:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7015 .loc 1 3795 6 is_stmt 1 view .LVU2337 +3795:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7016 .loc 1 3795 8 is_stmt 0 view .LVU2338 + 7017 008a 237D ldrb r3, [r4, #20] @ zero_extendqisi2 +3795:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7018 .loc 1 3795 15 view .LVU2339 + 7019 008c 23F04003 bic r3, r3, #64 + 7020 0090 2375 strb r3, [r4, #20] + 7021 0092 CBE7 b .L512 + 7022 .LVL813: + 7023 .L514: +3750:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 7024 .loc 1 3750 62 discriminator 1 view .LVU2340 + 7025 0094 0120 movs r0, #1 + 7026 0096 C9E7 b .L512 + 7027 .cfi_endproc + 7028 .LFE1225: + 7030 .section .text.f_close,"ax",%progbits + ARM GAS /tmp/cc2SVLkL.s page 263 + + + 7031 .align 1 + 7032 .global f_close + 7033 .syntax unified + 7034 .thumb + 7035 .thumb_func + 7037 f_close: + 7038 .LVL814: + 7039 .LFB1226: +3816:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 7040 .loc 1 3816 1 is_stmt 1 view -0 + 7041 .cfi_startproc + 7042 @ args = 0, pretend = 0, frame = 8 + 7043 @ frame_needed = 0, uses_anonymous_args = 0 +3816:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 7044 .loc 1 3816 1 is_stmt 0 view .LVU2342 + 7045 0000 10B5 push {r4, lr} + 7046 .LCFI67: + 7047 .cfi_def_cfa_offset 8 + 7048 .cfi_offset 4, -8 + 7049 .cfi_offset 14, -4 + 7050 0002 82B0 sub sp, sp, #8 + 7051 .LCFI68: + 7052 .cfi_def_cfa_offset 16 + 7053 0004 0446 mov r4, r0 +3817:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; + 7054 .loc 1 3817 2 is_stmt 1 view .LVU2343 +3818:Middlewares/Third_Party/FatFs/src/ff.c **** + 7055 .loc 1 3818 2 view .LVU2344 +3821:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) + 7056 .loc 1 3821 2 view .LVU2345 +3821:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) + 7057 .loc 1 3821 8 is_stmt 0 view .LVU2346 + 7058 0006 FFF7FEFF bl f_sync + 7059 .LVL815: +3822:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7060 .loc 1 3822 2 is_stmt 1 view .LVU2347 +3822:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7061 .loc 1 3822 5 is_stmt 0 view .LVU2348 + 7062 000a 08B1 cbz r0, .L521 + 7063 .L519: + 7064 .LVL816: +3839:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7065 .loc 1 3839 2 is_stmt 1 view .LVU2349 +3840:Middlewares/Third_Party/FatFs/src/ff.c **** + 7066 .loc 1 3840 1 is_stmt 0 view .LVU2350 + 7067 000c 02B0 add sp, sp, #8 + 7068 .LCFI69: + 7069 .cfi_remember_state + 7070 .cfi_def_cfa_offset 8 + 7071 @ sp needed + 7072 000e 10BD pop {r4, pc} + 7073 .LVL817: + 7074 .L521: + 7075 .LCFI70: + 7076 .cfi_restore_state +3825:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 7077 .loc 1 3825 3 is_stmt 1 view .LVU2351 + ARM GAS /tmp/cc2SVLkL.s page 264 + + +3825:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 7078 .loc 1 3825 9 is_stmt 0 view .LVU2352 + 7079 0010 01A9 add r1, sp, #4 + 7080 0012 2046 mov r0, r4 + 7081 0014 FFF7FEFF bl validate + 7082 .LVL818: +3826:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 7083 .loc 1 3826 3 is_stmt 1 view .LVU2353 +3826:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 7084 .loc 1 3826 6 is_stmt 0 view .LVU2354 + 7085 0018 0028 cmp r0, #0 + 7086 001a F7D1 bne .L519 +3828:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) + 7087 .loc 1 3828 4 is_stmt 1 view .LVU2355 +3828:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) + 7088 .loc 1 3828 10 is_stmt 0 view .LVU2356 + 7089 001c 2069 ldr r0, [r4, #16] + 7090 .LVL819: +3828:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) + 7091 .loc 1 3828 10 view .LVU2357 + 7092 001e FFF7FEFF bl dec_lock + 7093 .LVL820: +3829:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7094 .loc 1 3829 4 is_stmt 1 view .LVU2358 +3829:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7095 .loc 1 3829 7 is_stmt 0 view .LVU2359 + 7096 0022 0028 cmp r0, #0 + 7097 0024 F2D1 bne .L519 +3832:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7098 .loc 1 3832 5 is_stmt 1 view .LVU2360 +3832:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7099 .loc 1 3832 16 is_stmt 0 view .LVU2361 + 7100 0026 2060 str r0, [r4] + 7101 0028 F0E7 b .L519 + 7102 .cfi_endproc + 7103 .LFE1226: + 7105 .section .text.f_lseek,"ax",%progbits + 7106 .align 1 + 7107 .global f_lseek + 7108 .syntax unified + 7109 .thumb + 7110 .thumb_func + 7112 f_lseek: + 7113 .LVL821: + 7114 .LFB1227: +4005:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 7115 .loc 1 4005 1 is_stmt 1 view -0 + 7116 .cfi_startproc + 7117 @ args = 0, pretend = 0, frame = 8 + 7118 @ frame_needed = 0, uses_anonymous_args = 0 +4005:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 7119 .loc 1 4005 1 is_stmt 0 view .LVU2363 + 7120 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 7121 .LCFI71: + 7122 .cfi_def_cfa_offset 36 + 7123 .cfi_offset 4, -36 + 7124 .cfi_offset 5, -32 + ARM GAS /tmp/cc2SVLkL.s page 265 + + + 7125 .cfi_offset 6, -28 + 7126 .cfi_offset 7, -24 + 7127 .cfi_offset 8, -20 + 7128 .cfi_offset 9, -16 + 7129 .cfi_offset 10, -12 + 7130 .cfi_offset 11, -8 + 7131 .cfi_offset 14, -4 + 7132 0004 83B0 sub sp, sp, #12 + 7133 .LCFI72: + 7134 .cfi_def_cfa_offset 48 + 7135 0006 0446 mov r4, r0 + 7136 0008 0D46 mov r5, r1 +4006:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; + 7137 .loc 1 4006 2 is_stmt 1 view .LVU2364 +4007:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD clst, bcs, nsect; + 7138 .loc 1 4007 2 view .LVU2365 +4008:Middlewares/Third_Party/FatFs/src/ff.c **** FSIZE_t ifptr; + 7139 .loc 1 4008 2 view .LVU2366 +4009:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_FASTSEEK + 7140 .loc 1 4009 2 view .LVU2367 +4011:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7141 .loc 1 4011 2 view .LVU2368 +4014:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) res = (FRESULT)fp->err; + 7142 .loc 1 4014 2 view .LVU2369 +4014:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) res = (FRESULT)fp->err; + 7143 .loc 1 4014 8 is_stmt 0 view .LVU2370 + 7144 000a 01A9 add r1, sp, #4 + 7145 .LVL822: +4014:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) res = (FRESULT)fp->err; + 7146 .loc 1 4014 8 view .LVU2371 + 7147 000c FFF7FEFF bl validate + 7148 .LVL823: +4015:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT && !_FS_READONLY + 7149 .loc 1 4015 2 is_stmt 1 view .LVU2372 +4015:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT && !_FS_READONLY + 7150 .loc 1 4015 5 is_stmt 0 view .LVU2373 + 7151 0010 0646 mov r6, r0 + 7152 0012 78B9 cbnz r0, .L525 +4015:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT && !_FS_READONLY + 7153 .loc 1 4015 20 is_stmt 1 discriminator 1 view .LVU2374 +4015:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT && !_FS_READONLY + 7154 .loc 1 4015 24 is_stmt 0 discriminator 1 view .LVU2375 + 7155 0014 667D ldrb r6, [r4, #21] @ zero_extendqisi2 + 7156 .LVL824: +4021:Middlewares/Third_Party/FatFs/src/ff.c **** + 7157 .loc 1 4021 2 is_stmt 1 view .LVU2376 +4021:Middlewares/Third_Party/FatFs/src/ff.c **** + 7158 .loc 1 4021 5 is_stmt 0 view .LVU2377 + 7159 0016 6EB9 cbnz r6, .L525 +4024:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs == CREATE_LINKMAP) { /* Create CLMT */ + 7160 .loc 1 4024 2 is_stmt 1 view .LVU2378 +4024:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs == CREATE_LINKMAP) { /* Create CLMT */ + 7161 .loc 1 4024 8 is_stmt 0 view .LVU2379 + 7162 0018 E36A ldr r3, [r4, #44] +4024:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs == CREATE_LINKMAP) { /* Create CLMT */ + 7163 .loc 1 4024 5 view .LVU2380 + 7164 001a 002B cmp r3, #0 + ARM GAS /tmp/cc2SVLkL.s page 266 + + + 7165 001c 00F08E80 beq .L526 +4025:Middlewares/Third_Party/FatFs/src/ff.c **** tbl = fp->cltbl; + 7166 .loc 1 4025 3 is_stmt 1 view .LVU2381 +4025:Middlewares/Third_Party/FatFs/src/ff.c **** tbl = fp->cltbl; + 7167 .loc 1 4025 6 is_stmt 0 view .LVU2382 + 7168 0020 B5F1FF3F cmp r5, #-1 + 7169 0024 0AD0 beq .L566 +4051:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = ofs; /* Set file pointer */ + 7170 .loc 1 4051 4 is_stmt 1 view .LVU2383 +4051:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = ofs; /* Set file pointer */ + 7171 .loc 1 4051 21 is_stmt 0 view .LVU2384 + 7172 0026 E768 ldr r7, [r4, #12] +4051:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = ofs; /* Set file pointer */ + 7173 .loc 1 4051 7 view .LVU2385 + 7174 0028 AF42 cmp r7, r5 + 7175 002a 00D3 bcc .L534 + 7176 002c 2F46 mov r7, r5 + 7177 .L534: + 7178 .LVL825: +4052:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs) { + 7179 .loc 1 4052 4 is_stmt 1 view .LVU2386 +4052:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs) { + 7180 .loc 1 4052 13 is_stmt 0 view .LVU2387 + 7181 002e A761 str r7, [r4, #24] +4053:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clmt_clust(fp, ofs - 1); + 7182 .loc 1 4053 4 is_stmt 1 view .LVU2388 +4053:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clmt_clust(fp, ofs - 1); + 7183 .loc 1 4053 7 is_stmt 0 view .LVU2389 + 7184 0030 002F cmp r7, #0 + 7185 0032 3FD1 bne .L567 + 7186 .LVL826: + 7187 .L525: +4153:Middlewares/Third_Party/FatFs/src/ff.c **** + 7188 .loc 1 4153 1 view .LVU2390 + 7189 0034 3046 mov r0, r6 + 7190 0036 03B0 add sp, sp, #12 + 7191 .LCFI73: + 7192 .cfi_remember_state + 7193 .cfi_def_cfa_offset 36 + 7194 @ sp needed + 7195 0038 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 7196 .LVL827: + 7197 .L566: + 7198 .LCFI74: + 7199 .cfi_restore_state +4026:Middlewares/Third_Party/FatFs/src/ff.c **** tlen = *tbl++; ulen = 2; /* Given table size and required table size */ + 7200 .loc 1 4026 4 is_stmt 1 view .LVU2391 +4027:Middlewares/Third_Party/FatFs/src/ff.c **** cl = fp->obj.sclust; /* Origin of the chain */ + 7201 .loc 1 4027 4 view .LVU2392 +4027:Middlewares/Third_Party/FatFs/src/ff.c **** cl = fp->obj.sclust; /* Origin of the chain */ + 7202 .loc 1 4027 15 is_stmt 0 view .LVU2393 + 7203 003c 9846 mov r8, r3 + 7204 .LVL828: +4027:Middlewares/Third_Party/FatFs/src/ff.c **** cl = fp->obj.sclust; /* Origin of the chain */ + 7205 .loc 1 4027 9 view .LVU2394 + 7206 003e 58F804BB ldr fp, [r8], #4 + 7207 .LVL829: + ARM GAS /tmp/cc2SVLkL.s page 267 + + +4027:Middlewares/Third_Party/FatFs/src/ff.c **** cl = fp->obj.sclust; /* Origin of the chain */ + 7208 .loc 1 4027 19 is_stmt 1 view .LVU2395 +4028:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl) { + 7209 .loc 1 4028 4 view .LVU2396 +4028:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl) { + 7210 .loc 1 4028 7 is_stmt 0 view .LVU2397 + 7211 0042 D4F808A0 ldr r10, [r4, #8] + 7212 .LVL830: +4029:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 7213 .loc 1 4029 4 is_stmt 1 view .LVU2398 +4029:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 7214 .loc 1 4029 7 is_stmt 0 view .LVU2399 + 7215 0046 BAF1000F cmp r10, #0 + 7216 004a 27D0 beq .L559 +4027:Middlewares/Third_Party/FatFs/src/ff.c **** cl = fp->obj.sclust; /* Origin of the chain */ + 7217 .loc 1 4027 24 view .LVU2400 + 7218 004c 4FF00209 mov r9, #2 + 7219 .LVL831: + 7220 .L533: +4030:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get a fragment */ + 7221 .loc 1 4030 5 is_stmt 1 view .LVU2401 +4032:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 7222 .loc 1 4032 6 view .LVU2402 +4032:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 7223 .loc 1 4032 16 view .LVU2403 +4032:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 7224 .loc 1 4032 25 view .LVU2404 +4032:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 7225 .loc 1 4032 30 is_stmt 0 view .LVU2405 + 7226 0050 09F10209 add r9, r9, #2 + 7227 .LVL832: +4032:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 7228 .loc 1 4032 30 view .LVU2406 + 7229 0054 5146 mov r1, r10 +4032:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 7230 .loc 1 4032 20 view .LVU2407 + 7231 0056 0027 movs r7, #0 + 7232 .LVL833: + 7233 .L531: +4033:Middlewares/Third_Party/FatFs/src/ff.c **** pcl = cl; ncl++; + 7234 .loc 1 4033 6 is_stmt 1 view .LVU2408 +4034:Middlewares/Third_Party/FatFs/src/ff.c **** cl = get_fat(&fp->obj, cl); + 7235 .loc 1 4034 7 view .LVU2409 +4034:Middlewares/Third_Party/FatFs/src/ff.c **** cl = get_fat(&fp->obj, cl); + 7236 .loc 1 4034 17 view .LVU2410 +4034:Middlewares/Third_Party/FatFs/src/ff.c **** cl = get_fat(&fp->obj, cl); + 7237 .loc 1 4034 20 is_stmt 0 view .LVU2411 + 7238 0058 0137 adds r7, r7, #1 + 7239 .LVL834: +4035:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl <= 1) ABORT(fs, FR_INT_ERR); + 7240 .loc 1 4035 7 is_stmt 1 view .LVU2412 + 7241 005a 0D46 mov r5, r1 +4035:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl <= 1) ABORT(fs, FR_INT_ERR); + 7242 .loc 1 4035 12 is_stmt 0 view .LVU2413 + 7243 005c 2046 mov r0, r4 + 7244 005e FFF7FEFF bl get_fat + 7245 .LVL835: + ARM GAS /tmp/cc2SVLkL.s page 268 + + +4035:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl <= 1) ABORT(fs, FR_INT_ERR); + 7246 .loc 1 4035 12 view .LVU2414 + 7247 0062 0146 mov r1, r0 + 7248 .LVL836: +4036:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 7249 .loc 1 4036 7 is_stmt 1 view .LVU2415 +4036:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 7250 .loc 1 4036 10 is_stmt 0 view .LVU2416 + 7251 0064 0128 cmp r0, #1 + 7252 0066 13D9 bls .L568 +4036:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 7253 .loc 1 4036 41 is_stmt 1 discriminator 2 view .LVU2417 +4037:Middlewares/Third_Party/FatFs/src/ff.c **** } while (cl == pcl + 1); + 7254 .loc 1 4037 7 view .LVU2418 +4037:Middlewares/Third_Party/FatFs/src/ff.c **** } while (cl == pcl + 1); + 7255 .loc 1 4037 10 is_stmt 0 view .LVU2419 + 7256 0068 B0F1FF3F cmp r0, #-1 + 7257 006c 13D0 beq .L569 +4037:Middlewares/Third_Party/FatFs/src/ff.c **** } while (cl == pcl + 1); + 7258 .loc 1 4037 51 is_stmt 1 discriminator 2 view .LVU2420 +4038:Middlewares/Third_Party/FatFs/src/ff.c **** if (ulen <= tlen) { /* Store the length and top of the fragment */ + 7259 .loc 1 4038 18 view .LVU2421 +4038:Middlewares/Third_Party/FatFs/src/ff.c **** if (ulen <= tlen) { /* Store the length and top of the fragment */ + 7260 .loc 1 4038 25 is_stmt 0 view .LVU2422 + 7261 006e 0135 adds r5, r5, #1 + 7262 .LVL837: +4038:Middlewares/Third_Party/FatFs/src/ff.c **** if (ulen <= tlen) { /* Store the length and top of the fragment */ + 7263 .loc 1 4038 18 view .LVU2423 + 7264 0070 8542 cmp r5, r0 + 7265 0072 F1D0 beq .L531 +4039:Middlewares/Third_Party/FatFs/src/ff.c **** *tbl++ = ncl; *tbl++ = tcl; + 7266 .loc 1 4039 6 is_stmt 1 view .LVU2424 +4039:Middlewares/Third_Party/FatFs/src/ff.c **** *tbl++ = ncl; *tbl++ = tcl; + 7267 .loc 1 4039 9 is_stmt 0 view .LVU2425 + 7268 0074 CB45 cmp fp, r9 + 7269 0076 05D3 bcc .L532 +4040:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7270 .loc 1 4040 7 is_stmt 1 view .LVU2426 + 7271 .LVL838: +4040:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7272 .loc 1 4040 14 is_stmt 0 view .LVU2427 + 7273 0078 4346 mov r3, r8 + 7274 007a 43F8087B str r7, [r3], #8 +4040:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7275 .loc 1 4040 21 is_stmt 1 view .LVU2428 + 7276 .LVL839: +4040:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7277 .loc 1 4040 28 is_stmt 0 view .LVU2429 + 7278 007e C8F804A0 str r10, [r8, #4] +4040:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7279 .loc 1 4040 25 view .LVU2430 + 7280 0082 9846 mov r8, r3 + 7281 .LVL840: + 7282 .L532: +4042:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7283 .loc 1 4042 17 is_stmt 1 view .LVU2431 +4042:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 269 + + + 7284 .loc 1 4042 21 is_stmt 0 view .LVU2432 + 7285 0084 019B ldr r3, [sp, #4] + 7286 0086 9B69 ldr r3, [r3, #24] +4042:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7287 .loc 1 4042 17 view .LVU2433 + 7288 0088 8B42 cmp r3, r1 + 7289 008a 09D9 bls .L528 +4035:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl <= 1) ABORT(fs, FR_INT_ERR); + 7290 .loc 1 4035 12 view .LVU2434 + 7291 008c 8A46 mov r10, r1 + 7292 .LVL841: +4035:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl <= 1) ABORT(fs, FR_INT_ERR); + 7293 .loc 1 4035 12 view .LVU2435 + 7294 008e DFE7 b .L533 + 7295 .LVL842: + 7296 .L568: +4036:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 7297 .loc 1 4036 20 is_stmt 1 discriminator 1 view .LVU2436 + 7298 0090 0226 movs r6, #2 + 7299 .LVL843: +4036:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 7300 .loc 1 4036 20 is_stmt 0 discriminator 1 view .LVU2437 + 7301 0092 6675 strb r6, [r4, #21] +4036:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 7302 .loc 1 4036 20 is_stmt 1 discriminator 1 view .LVU2438 +4036:Middlewares/Third_Party/FatFs/src/ff.c **** if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 7303 .loc 1 4036 20 is_stmt 0 view .LVU2439 + 7304 0094 CEE7 b .L525 + 7305 .LVL844: + 7306 .L569: +4037:Middlewares/Third_Party/FatFs/src/ff.c **** } while (cl == pcl + 1); + 7307 .loc 1 4037 29 is_stmt 1 discriminator 1 view .LVU2440 + 7308 0096 0126 movs r6, #1 + 7309 .LVL845: +4037:Middlewares/Third_Party/FatFs/src/ff.c **** } while (cl == pcl + 1); + 7310 .loc 1 4037 29 is_stmt 0 discriminator 1 view .LVU2441 + 7311 0098 6675 strb r6, [r4, #21] +4037:Middlewares/Third_Party/FatFs/src/ff.c **** } while (cl == pcl + 1); + 7312 .loc 1 4037 29 is_stmt 1 discriminator 1 view .LVU2442 +4037:Middlewares/Third_Party/FatFs/src/ff.c **** } while (cl == pcl + 1); + 7313 .loc 1 4037 29 is_stmt 0 view .LVU2443 + 7314 009a CBE7 b .L525 + 7315 .LVL846: + 7316 .L559: +4027:Middlewares/Third_Party/FatFs/src/ff.c **** cl = fp->obj.sclust; /* Origin of the chain */ + 7317 .loc 1 4027 24 view .LVU2444 + 7318 009c 4FF00209 mov r9, #2 + 7319 .LVL847: + 7320 .L528: +4044:Middlewares/Third_Party/FatFs/src/ff.c **** if (ulen <= tlen) { + 7321 .loc 1 4044 4 is_stmt 1 view .LVU2445 +4044:Middlewares/Third_Party/FatFs/src/ff.c **** if (ulen <= tlen) { + 7322 .loc 1 4044 7 is_stmt 0 view .LVU2446 + 7323 00a0 E36A ldr r3, [r4, #44] +4044:Middlewares/Third_Party/FatFs/src/ff.c **** if (ulen <= tlen) { + 7324 .loc 1 4044 15 view .LVU2447 + 7325 00a2 C3F80090 str r9, [r3] + ARM GAS /tmp/cc2SVLkL.s page 270 + + +4045:Middlewares/Third_Party/FatFs/src/ff.c **** *tbl = 0; /* Terminate table */ + 7326 .loc 1 4045 4 is_stmt 1 view .LVU2448 +4045:Middlewares/Third_Party/FatFs/src/ff.c **** *tbl = 0; /* Terminate table */ + 7327 .loc 1 4045 7 is_stmt 0 view .LVU2449 + 7328 00a6 D945 cmp r9, fp + 7329 00a8 00F2FB80 bhi .L561 +4046:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 7330 .loc 1 4046 5 is_stmt 1 view .LVU2450 +4046:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 7331 .loc 1 4046 10 is_stmt 0 view .LVU2451 + 7332 00ac 0023 movs r3, #0 + 7333 00ae C8F80030 str r3, [r8] + 7334 00b2 BFE7 b .L525 + 7335 .LVL848: + 7336 .L567: +4054:Middlewares/Third_Party/FatFs/src/ff.c **** dsc = clust2sect(fs, fp->clust); + 7337 .loc 1 4054 5 is_stmt 1 view .LVU2452 +4054:Middlewares/Third_Party/FatFs/src/ff.c **** dsc = clust2sect(fs, fp->clust); + 7338 .loc 1 4054 17 is_stmt 0 view .LVU2453 + 7339 00b4 7D1E subs r5, r7, #1 + 7340 00b6 2946 mov r1, r5 + 7341 00b8 2046 mov r0, r4 + 7342 00ba FFF7FEFF bl clmt_clust + 7343 .LVL849: + 7344 00be 0146 mov r1, r0 +4054:Middlewares/Third_Party/FatFs/src/ff.c **** dsc = clust2sect(fs, fp->clust); + 7345 .loc 1 4054 15 discriminator 1 view .LVU2454 + 7346 00c0 E061 str r0, [r4, #28] +4055:Middlewares/Third_Party/FatFs/src/ff.c **** if (!dsc) ABORT(fs, FR_INT_ERR); + 7347 .loc 1 4055 5 is_stmt 1 view .LVU2455 +4055:Middlewares/Third_Party/FatFs/src/ff.c **** if (!dsc) ABORT(fs, FR_INT_ERR); + 7348 .loc 1 4055 11 is_stmt 0 view .LVU2456 + 7349 00c2 DDF80480 ldr r8, [sp, #4] + 7350 00c6 4046 mov r0, r8 + 7351 00c8 FFF7FEFF bl clust2sect + 7352 .LVL850: +4056:Middlewares/Third_Party/FatFs/src/ff.c **** dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1); + 7353 .loc 1 4056 5 is_stmt 1 view .LVU2457 +4056:Middlewares/Third_Party/FatFs/src/ff.c **** dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1); + 7354 .loc 1 4056 8 is_stmt 0 view .LVU2458 + 7355 00cc 00B3 cbz r0, .L570 +4056:Middlewares/Third_Party/FatFs/src/ff.c **** dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1); + 7356 .loc 1 4056 36 is_stmt 1 discriminator 2 view .LVU2459 +4057:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) && dsc != fp->sect) { /* Refill sector cache if needed */ + 7357 .loc 1 4057 5 view .LVU2460 +4057:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) && dsc != fp->sect) { /* Refill sector cache if needed */ + 7358 .loc 1 4057 32 is_stmt 0 view .LVU2461 + 7359 00ce B8F80C30 ldrh r3, [r8, #12] +4057:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) && dsc != fp->sect) { /* Refill sector cache if needed */ + 7360 .loc 1 4057 12 view .LVU2462 + 7361 00d2 B5FBF3F5 udiv r5, r5, r3 +4057:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) && dsc != fp->sect) { /* Refill sector cache if needed */ + 7362 .loc 1 4057 45 view .LVU2463 + 7363 00d6 B8F80A20 ldrh r2, [r8, #10] +4057:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) && dsc != fp->sect) { /* Refill sector cache if needed */ + 7364 .loc 1 4057 53 view .LVU2464 + 7365 00da 013A subs r2, r2, #1 + ARM GAS /tmp/cc2SVLkL.s page 271 + + +4057:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) && dsc != fp->sect) { /* Refill sector cache if needed */ + 7366 .loc 1 4057 40 view .LVU2465 + 7367 00dc 1540 ands r5, r5, r2 +4057:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr % SS(fs) && dsc != fp->sect) { /* Refill sector cache if needed */ + 7368 .loc 1 4057 9 view .LVU2466 + 7369 00de 0544 add r5, r5, r0 + 7370 .LVL851: +4058:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 7371 .loc 1 4058 5 is_stmt 1 view .LVU2467 +4058:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 7372 .loc 1 4058 18 is_stmt 0 view .LVU2468 + 7373 00e0 B7FBF3F2 udiv r2, r7, r3 + 7374 00e4 03FB1277 mls r7, r3, r2, r7 + 7375 .LVL852: +4058:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 7376 .loc 1 4058 8 view .LVU2469 + 7377 00e8 002F cmp r7, #0 + 7378 00ea A3D0 beq .L525 +4058:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 7379 .loc 1 4058 39 discriminator 1 view .LVU2470 + 7380 00ec 226A ldr r2, [r4, #32] +4058:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 7381 .loc 1 4058 27 discriminator 1 view .LVU2471 + 7382 00ee AA42 cmp r2, r5 + 7383 00f0 A0D0 beq .L525 +4061:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + 7384 .loc 1 4061 6 is_stmt 1 view .LVU2472 +4061:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + 7385 .loc 1 4061 10 is_stmt 0 view .LVU2473 + 7386 00f2 94F91430 ldrsb r3, [r4, #20] +4061:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + 7387 .loc 1 4061 9 view .LVU2474 + 7388 00f6 002B cmp r3, #0 + 7389 00f8 0DDB blt .L571 + 7390 .L536: +4066:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7391 .loc 1 4066 6 is_stmt 1 view .LVU2475 +4066:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7392 .loc 1 4066 10 is_stmt 0 view .LVU2476 + 7393 00fa 0123 movs r3, #1 + 7394 00fc 2A46 mov r2, r5 + 7395 00fe 04F13001 add r1, r4, #48 + 7396 0102 0198 ldr r0, [sp, #4] + 7397 0104 4078 ldrb r0, [r0, #1] @ zero_extendqisi2 + 7398 0106 FFF7FEFF bl disk_read + 7399 .LVL853: +4066:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7400 .loc 1 4066 9 discriminator 1 view .LVU2477 + 7401 010a A0B9 cbnz r0, .L572 +4066:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7402 .loc 1 4066 79 is_stmt 1 discriminator 2 view .LVU2478 +4068:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7403 .loc 1 4068 6 view .LVU2479 +4068:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7404 .loc 1 4068 15 is_stmt 0 view .LVU2480 + 7405 010c 2562 str r5, [r4, #32] + 7406 010e 91E7 b .L525 + ARM GAS /tmp/cc2SVLkL.s page 272 + + + 7407 .LVL854: + 7408 .L570: +4056:Middlewares/Third_Party/FatFs/src/ff.c **** dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1); + 7409 .loc 1 4056 15 is_stmt 1 discriminator 1 view .LVU2481 + 7410 0110 0226 movs r6, #2 + 7411 .LVL855: +4056:Middlewares/Third_Party/FatFs/src/ff.c **** dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1); + 7412 .loc 1 4056 15 is_stmt 0 discriminator 1 view .LVU2482 + 7413 0112 6675 strb r6, [r4, #21] +4056:Middlewares/Third_Party/FatFs/src/ff.c **** dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1); + 7414 .loc 1 4056 15 is_stmt 1 discriminator 1 view .LVU2483 +4056:Middlewares/Third_Party/FatFs/src/ff.c **** dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1); + 7415 .loc 1 4056 15 is_stmt 0 view .LVU2484 + 7416 0114 8EE7 b .L525 + 7417 .LVL856: + 7418 .L571: +4062:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 7419 .loc 1 4062 7 is_stmt 1 view .LVU2485 +4062:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 7420 .loc 1 4062 11 is_stmt 0 view .LVU2486 + 7421 0116 0123 movs r3, #1 + 7422 0118 04F13001 add r1, r4, #48 + 7423 011c 98F80100 ldrb r0, [r8, #1] @ zero_extendqisi2 + 7424 0120 FFF7FEFF bl disk_write + 7425 .LVL857: +4062:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 7426 .loc 1 4062 10 discriminator 1 view .LVU2487 + 7427 0124 20B9 cbnz r0, .L573 +4062:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 7428 .loc 1 4062 86 is_stmt 1 discriminator 2 view .LVU2488 +4063:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7429 .loc 1 4063 7 view .LVU2489 +4063:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7430 .loc 1 4063 9 is_stmt 0 view .LVU2490 + 7431 0126 237D ldrb r3, [r4, #20] @ zero_extendqisi2 +4063:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7432 .loc 1 4063 16 view .LVU2491 + 7433 0128 03F07F03 and r3, r3, #127 + 7434 012c 2375 strb r3, [r4, #20] + 7435 012e E4E7 b .L536 + 7436 .L573: +4062:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 7437 .loc 1 4062 64 is_stmt 1 discriminator 1 view .LVU2492 + 7438 0130 0126 movs r6, #1 + 7439 .LVL858: +4062:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 7440 .loc 1 4062 64 is_stmt 0 discriminator 1 view .LVU2493 + 7441 0132 6675 strb r6, [r4, #21] +4062:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 7442 .loc 1 4062 64 is_stmt 1 discriminator 1 view .LVU2494 +4062:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 7443 .loc 1 4062 64 is_stmt 0 view .LVU2495 + 7444 0134 7EE7 b .L525 + 7445 .LVL859: + 7446 .L572: +4066:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7447 .loc 1 4066 57 is_stmt 1 discriminator 1 view .LVU2496 + ARM GAS /tmp/cc2SVLkL.s page 273 + + + 7448 0136 0126 movs r6, #1 + 7449 .LVL860: +4066:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7450 .loc 1 4066 57 is_stmt 0 discriminator 1 view .LVU2497 + 7451 0138 6675 strb r6, [r4, #21] +4066:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7452 .loc 1 4066 57 is_stmt 1 discriminator 1 view .LVU2498 +4066:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7453 .loc 1 4066 57 is_stmt 0 view .LVU2499 + 7454 013a 7BE7 b .L525 + 7455 .LVL861: + 7456 .L526: +4080:Middlewares/Third_Party/FatFs/src/ff.c **** ofs = fp->obj.objsize; + 7457 .loc 1 4080 3 is_stmt 1 view .LVU2500 +4080:Middlewares/Third_Party/FatFs/src/ff.c **** ofs = fp->obj.objsize; + 7458 .loc 1 4080 20 is_stmt 0 view .LVU2501 + 7459 013c E368 ldr r3, [r4, #12] +4080:Middlewares/Third_Party/FatFs/src/ff.c **** ofs = fp->obj.objsize; + 7460 .loc 1 4080 6 view .LVU2502 + 7461 013e AB42 cmp r3, r5 + 7462 0140 04D2 bcs .L539 +4080:Middlewares/Third_Party/FatFs/src/ff.c **** ofs = fp->obj.objsize; + 7463 .loc 1 4080 53 discriminator 1 view .LVU2503 + 7464 0142 227D ldrb r2, [r4, #20] @ zero_extendqisi2 +4080:Middlewares/Third_Party/FatFs/src/ff.c **** ofs = fp->obj.objsize; + 7465 .loc 1 4080 29 discriminator 1 view .LVU2504 + 7466 0144 12F0020F tst r2, #2 + 7467 0148 00D1 bne .L539 +4081:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7468 .loc 1 4081 8 view .LVU2505 + 7469 014a 1D46 mov r5, r3 + 7470 .LVL862: + 7471 .L539: +4083:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = nsect = 0; + 7472 .loc 1 4083 3 is_stmt 1 view .LVU2506 +4083:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = nsect = 0; + 7473 .loc 1 4083 9 is_stmt 0 view .LVU2507 + 7474 014c A369 ldr r3, [r4, #24] + 7475 .LVL863: +4084:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs) { + 7476 .loc 1 4084 3 is_stmt 1 view .LVU2508 +4084:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs) { + 7477 .loc 1 4084 12 is_stmt 0 view .LVU2509 + 7478 014e 0022 movs r2, #0 + 7479 0150 A261 str r2, [r4, #24] +4085:Middlewares/Third_Party/FatFs/src/ff.c **** bcs = (DWORD)fs->csize * SS(fs); /* Cluster size (byte) */ + 7480 .loc 1 4085 3 is_stmt 1 view .LVU2510 +4085:Middlewares/Third_Party/FatFs/src/ff.c **** bcs = (DWORD)fs->csize * SS(fs); /* Cluster size (byte) */ + 7481 .loc 1 4085 6 is_stmt 0 view .LVU2511 + 7482 0152 E5B1 cbz r5, .L540 +4086:Middlewares/Third_Party/FatFs/src/ff.c **** if (ifptr > 0 && + 7483 .loc 1 4086 4 is_stmt 1 view .LVU2512 +4086:Middlewares/Third_Party/FatFs/src/ff.c **** if (ifptr > 0 && + 7484 .loc 1 4086 19 is_stmt 0 view .LVU2513 + 7485 0154 019A ldr r2, [sp, #4] + 7486 0156 B2F80A80 ldrh r8, [r2, #10] +4086:Middlewares/Third_Party/FatFs/src/ff.c **** if (ifptr > 0 && + ARM GAS /tmp/cc2SVLkL.s page 274 + + + 7487 .loc 1 4086 29 view .LVU2514 + 7488 015a 9289 ldrh r2, [r2, #12] +4086:Middlewares/Third_Party/FatFs/src/ff.c **** if (ifptr > 0 && + 7489 .loc 1 4086 8 view .LVU2515 + 7490 015c 02FB08F8 mul r8, r2, r8 + 7491 .LVL864: +4087:Middlewares/Third_Party/FatFs/src/ff.c **** (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ + 7492 .loc 1 4087 4 is_stmt 1 view .LVU2516 +4087:Middlewares/Third_Party/FatFs/src/ff.c **** (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ + 7493 .loc 1 4087 7 is_stmt 0 view .LVU2517 + 7494 0160 73B1 cbz r3, .L541 +4088:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1); /* start from the current cluster */ + 7495 .loc 1 4088 10 view .LVU2518 + 7496 0162 6A1E subs r2, r5, #1 +4088:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1); /* start from the current cluster */ + 7497 .loc 1 4088 15 view .LVU2519 + 7498 0164 B2FBF8F2 udiv r2, r2, r8 +4088:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1); /* start from the current cluster */ + 7499 .loc 1 4088 31 view .LVU2520 + 7500 0168 013B subs r3, r3, #1 + 7501 .LVL865: +4088:Middlewares/Third_Party/FatFs/src/ff.c **** fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1); /* start from the current cluster */ + 7502 .loc 1 4088 36 view .LVU2521 + 7503 016a B3FBF8F1 udiv r1, r3, r8 +4087:Middlewares/Third_Party/FatFs/src/ff.c **** (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ + 7504 .loc 1 4087 18 discriminator 1 view .LVU2522 + 7505 016e 8A42 cmp r2, r1 + 7506 0170 06D3 bcc .L541 +4089:Middlewares/Third_Party/FatFs/src/ff.c **** ofs -= fp->fptr; + 7507 .loc 1 4089 5 is_stmt 1 view .LVU2523 +4089:Middlewares/Third_Party/FatFs/src/ff.c **** ofs -= fp->fptr; + 7508 .loc 1 4089 30 is_stmt 0 view .LVU2524 + 7509 0172 C8F10002 rsb r2, r8, #0 +4089:Middlewares/Third_Party/FatFs/src/ff.c **** ofs -= fp->fptr; + 7510 .loc 1 4089 28 view .LVU2525 + 7511 0176 1340 ands r3, r3, r2 + 7512 .LVL866: +4089:Middlewares/Third_Party/FatFs/src/ff.c **** ofs -= fp->fptr; + 7513 .loc 1 4089 14 view .LVU2526 + 7514 0178 A361 str r3, [r4, #24] +4090:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fp->clust; + 7515 .loc 1 4090 5 is_stmt 1 view .LVU2527 +4090:Middlewares/Third_Party/FatFs/src/ff.c **** clst = fp->clust; + 7516 .loc 1 4090 9 is_stmt 0 view .LVU2528 + 7517 017a EF1A subs r7, r5, r3 + 7518 .LVL867: +4091:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* When seek to back cluster, */ + 7519 .loc 1 4091 5 is_stmt 1 view .LVU2529 +4091:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* When seek to back cluster, */ + 7520 .loc 1 4091 10 is_stmt 0 view .LVU2530 + 7521 017c E569 ldr r5, [r4, #28] + 7522 .LVL868: +4091:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* When seek to back cluster, */ + 7523 .loc 1 4091 10 view .LVU2531 + 7524 017e 04E0 b .L542 + 7525 .LVL869: + 7526 .L541: + ARM GAS /tmp/cc2SVLkL.s page 275 + + +4093:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 7527 .loc 1 4093 5 is_stmt 1 view .LVU2532 +4093:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 7528 .loc 1 4093 10 is_stmt 0 view .LVU2533 + 7529 0180 A068 ldr r0, [r4, #8] + 7530 .LVL870: +4095:Middlewares/Third_Party/FatFs/src/ff.c **** clst = create_chain(&fp->obj, 0); + 7531 .loc 1 4095 5 is_stmt 1 view .LVU2534 +4095:Middlewares/Third_Party/FatFs/src/ff.c **** clst = create_chain(&fp->obj, 0); + 7532 .loc 1 4095 8 is_stmt 0 view .LVU2535 + 7533 0182 50B3 cbz r0, .L574 + 7534 .L543: +4102:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7535 .loc 1 4102 5 is_stmt 1 view .LVU2536 +4102:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7536 .loc 1 4102 15 is_stmt 0 view .LVU2537 + 7537 0184 E061 str r0, [r4, #28] + 7538 0186 2F46 mov r7, r5 + 7539 0188 0546 mov r5, r0 + 7540 .LVL871: + 7541 .L542: +4104:Middlewares/Third_Party/FatFs/src/ff.c **** while (ofs > bcs) { /* Cluster following loop */ + 7542 .loc 1 4104 4 is_stmt 1 view .LVU2538 +4104:Middlewares/Third_Party/FatFs/src/ff.c **** while (ofs > bcs) { /* Cluster following loop */ + 7543 .loc 1 4104 7 is_stmt 0 view .LVU2539 + 7544 018a 002D cmp r5, #0 + 7545 018c 45D1 bne .L546 + 7546 .LVL872: + 7547 .L540: +4134:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.objsize = fp->fptr; + 7548 .loc 1 4134 3 is_stmt 1 view .LVU2540 +4134:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.objsize = fp->fptr; + 7549 .loc 1 4134 26 is_stmt 0 view .LVU2541 + 7550 018e A369 ldr r3, [r4, #24] +4134:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.objsize = fp->fptr; + 7551 .loc 1 4134 42 view .LVU2542 + 7552 0190 E268 ldr r2, [r4, #12] +4134:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.objsize = fp->fptr; + 7553 .loc 1 4134 6 view .LVU2543 + 7554 0192 9342 cmp r3, r2 + 7555 0194 04D9 bls .L555 +4135:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag |= FA_MODIFIED; + 7556 .loc 1 4135 4 is_stmt 1 view .LVU2544 +4135:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag |= FA_MODIFIED; + 7557 .loc 1 4135 20 is_stmt 0 view .LVU2545 + 7558 0196 E360 str r3, [r4, #12] +4136:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7559 .loc 1 4136 4 is_stmt 1 view .LVU2546 +4136:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7560 .loc 1 4136 6 is_stmt 0 view .LVU2547 + 7561 0198 227D ldrb r2, [r4, #20] @ zero_extendqisi2 +4136:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7562 .loc 1 4136 13 view .LVU2548 + 7563 019a 42F04002 orr r2, r2, #64 + 7564 019e 2275 strb r2, [r4, #20] + 7565 .L555: +4138:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + ARM GAS /tmp/cc2SVLkL.s page 276 + + + 7566 .loc 1 4138 3 is_stmt 1 view .LVU2549 +4138:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 7567 .loc 1 4138 18 is_stmt 0 view .LVU2550 + 7568 01a0 0198 ldr r0, [sp, #4] + 7569 01a2 8289 ldrh r2, [r0, #12] +4138:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 7570 .loc 1 4138 16 view .LVU2551 + 7571 01a4 B3FBF2F1 udiv r1, r3, r2 + 7572 01a8 02FB1133 mls r3, r2, r1, r3 +4138:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 7573 .loc 1 4138 6 view .LVU2552 + 7574 01ac 002B cmp r3, #0 + 7575 01ae 3FF441AF beq .L525 +4138:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 7576 .loc 1 4138 39 discriminator 1 view .LVU2553 + 7577 01b2 226A ldr r2, [r4, #32] +4138:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 7578 .loc 1 4138 25 discriminator 1 view .LVU2554 + 7579 01b4 AA42 cmp r2, r5 + 7580 01b6 3FF43DAF beq .L525 +4141:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + 7581 .loc 1 4141 4 is_stmt 1 view .LVU2555 +4141:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + 7582 .loc 1 4141 8 is_stmt 0 view .LVU2556 + 7583 01ba 94F91430 ldrsb r3, [r4, #20] +4141:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); + 7584 .loc 1 4141 7 view .LVU2557 + 7585 01be 002B cmp r3, #0 + 7586 01c0 5DDB blt .L575 + 7587 .L556: +4146:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7588 .loc 1 4146 4 is_stmt 1 view .LVU2558 +4146:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7589 .loc 1 4146 8 is_stmt 0 view .LVU2559 + 7590 01c2 0123 movs r3, #1 + 7591 01c4 2A46 mov r2, r5 + 7592 01c6 04F13001 add r1, r4, #48 + 7593 01ca 0198 ldr r0, [sp, #4] + 7594 01cc 4078 ldrb r0, [r0, #1] @ zero_extendqisi2 + 7595 01ce FFF7FEFF bl disk_read + 7596 .LVL873: +4146:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7597 .loc 1 4146 7 discriminator 1 view .LVU2560 + 7598 01d2 0028 cmp r0, #0 + 7599 01d4 62D1 bne .L576 +4146:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7600 .loc 1 4146 79 is_stmt 1 discriminator 2 view .LVU2561 +4148:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7601 .loc 1 4148 4 view .LVU2562 +4148:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7602 .loc 1 4148 13 is_stmt 0 view .LVU2563 + 7603 01d6 2562 str r5, [r4, #32] + 7604 01d8 2CE7 b .L525 + 7605 .LVL874: + 7606 .L574: +4096:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 1) ABORT(fs, FR_INT_ERR); + 7607 .loc 1 4096 6 is_stmt 1 view .LVU2564 + ARM GAS /tmp/cc2SVLkL.s page 277 + + +4096:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 1) ABORT(fs, FR_INT_ERR); + 7608 .loc 1 4096 13 is_stmt 0 view .LVU2565 + 7609 01da 0021 movs r1, #0 + 7610 01dc 2046 mov r0, r4 + 7611 .LVL875: +4096:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 1) ABORT(fs, FR_INT_ERR); + 7612 .loc 1 4096 13 view .LVU2566 + 7613 01de FFF7FEFF bl create_chain + 7614 .LVL876: +4097:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 7615 .loc 1 4097 6 is_stmt 1 view .LVU2567 +4097:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 7616 .loc 1 4097 9 is_stmt 0 view .LVU2568 + 7617 01e2 0128 cmp r0, #1 + 7618 01e4 04D0 beq .L577 +4097:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 7619 .loc 1 4097 42 is_stmt 1 discriminator 2 view .LVU2569 +4098:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.sclust = clst; + 7620 .loc 1 4098 6 view .LVU2570 +4098:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.sclust = clst; + 7621 .loc 1 4098 9 is_stmt 0 view .LVU2571 + 7622 01e6 B0F1FF3F cmp r0, #-1 + 7623 01ea 04D0 beq .L578 +4098:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.sclust = clst; + 7624 .loc 1 4098 52 is_stmt 1 discriminator 2 view .LVU2572 +4099:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7625 .loc 1 4099 6 view .LVU2573 +4099:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7626 .loc 1 4099 21 is_stmt 0 view .LVU2574 + 7627 01ec A060 str r0, [r4, #8] + 7628 01ee C9E7 b .L543 + 7629 .L577: +4097:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 7630 .loc 1 4097 21 is_stmt 1 discriminator 1 view .LVU2575 + 7631 01f0 0226 movs r6, #2 + 7632 .LVL877: +4097:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 7633 .loc 1 4097 21 is_stmt 0 discriminator 1 view .LVU2576 + 7634 01f2 6675 strb r6, [r4, #21] +4097:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 7635 .loc 1 4097 21 is_stmt 1 discriminator 1 view .LVU2577 +4097:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR); + 7636 .loc 1 4097 21 is_stmt 0 view .LVU2578 + 7637 01f4 1EE7 b .L525 + 7638 .LVL878: + 7639 .L578: +4098:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.sclust = clst; + 7640 .loc 1 4098 30 is_stmt 1 discriminator 1 view .LVU2579 + 7641 01f6 0126 movs r6, #1 + 7642 .LVL879: +4098:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.sclust = clst; + 7643 .loc 1 4098 30 is_stmt 0 discriminator 1 view .LVU2580 + 7644 01f8 6675 strb r6, [r4, #21] +4098:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.sclust = clst; + 7645 .loc 1 4098 30 is_stmt 1 discriminator 1 view .LVU2581 +4098:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.sclust = clst; + 7646 .loc 1 4098 30 is_stmt 0 view .LVU2582 + ARM GAS /tmp/cc2SVLkL.s page 278 + + + 7647 01fa 1BE7 b .L525 + 7648 .LVL880: + 7649 .L547: +4120:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7650 .loc 1 4120 7 is_stmt 1 view .LVU2583 +4120:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7651 .loc 1 4120 14 is_stmt 0 view .LVU2584 + 7652 01fc 2946 mov r1, r5 + 7653 01fe 2046 mov r0, r4 + 7654 0200 FFF7FEFF bl get_fat + 7655 .LVL881: + 7656 0204 0546 mov r5, r0 + 7657 .LVL882: + 7658 .L549: +4122:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR); + 7659 .loc 1 4122 6 is_stmt 1 view .LVU2585 +4122:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR); + 7660 .loc 1 4122 9 is_stmt 0 view .LVU2586 + 7661 0206 B5F1FF3F cmp r5, #-1 + 7662 020a 2DD0 beq .L579 +4122:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR); + 7663 .loc 1 4122 52 is_stmt 1 discriminator 2 view .LVU2587 +4123:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; + 7664 .loc 1 4123 6 view .LVU2588 +4123:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; + 7665 .loc 1 4123 9 is_stmt 0 view .LVU2589 + 7666 020c 012D cmp r5, #1 + 7667 020e 2ED9 bls .L551 +4123:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; + 7668 .loc 1 4123 33 discriminator 2 view .LVU2590 + 7669 0210 019B ldr r3, [sp, #4] + 7670 0212 9B69 ldr r3, [r3, #24] +4123:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; + 7671 .loc 1 4123 20 discriminator 2 view .LVU2591 + 7672 0214 AB42 cmp r3, r5 + 7673 0216 2AD9 bls .L551 +4123:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; + 7674 .loc 1 4123 66 is_stmt 1 discriminator 4 view .LVU2592 +4124:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7675 .loc 1 4124 6 view .LVU2593 +4124:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7676 .loc 1 4124 16 is_stmt 0 view .LVU2594 + 7677 0218 E561 str r5, [r4, #28] + 7678 .LVL883: + 7679 .L546: +4105:Middlewares/Third_Party/FatFs/src/ff.c **** ofs -= bcs; fp->fptr += bcs; + 7680 .loc 1 4105 16 is_stmt 1 view .LVU2595 + 7681 021a 4745 cmp r7, r8 + 7682 021c 10D9 bls .L548 +4106:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 7683 .loc 1 4106 6 view .LVU2596 +4106:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 7684 .loc 1 4106 10 is_stmt 0 view .LVU2597 + 7685 021e A7EB0807 sub r7, r7, r8 + 7686 .LVL884: +4106:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 7687 .loc 1 4106 18 is_stmt 1 view .LVU2598 + ARM GAS /tmp/cc2SVLkL.s page 279 + + +4106:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 7688 .loc 1 4106 20 is_stmt 0 view .LVU2599 + 7689 0222 A369 ldr r3, [r4, #24] +4106:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_READONLY + 7690 .loc 1 4106 27 view .LVU2600 + 7691 0224 4344 add r3, r3, r8 + 7692 0226 A361 str r3, [r4, #24] +4108:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_EXFAT && fp->fptr > fp->obj.objsize) { /* No FAT chain object needs correct objsize t + 7693 .loc 1 4108 6 is_stmt 1 view .LVU2601 +4108:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_EXFAT && fp->fptr > fp->obj.objsize) { /* No FAT chain object needs correct objsize t + 7694 .loc 1 4108 12 is_stmt 0 view .LVU2602 + 7695 0228 237D ldrb r3, [r4, #20] @ zero_extendqisi2 +4108:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_EXFAT && fp->fptr > fp->obj.objsize) { /* No FAT chain object needs correct objsize t + 7696 .loc 1 4108 9 view .LVU2603 + 7697 022a 13F0020F tst r3, #2 + 7698 022e E5D0 beq .L547 +4109:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.objsize = fp->fptr; + 7699 .loc 1 4109 7 is_stmt 1 view .LVU2604 +4113:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0) { /* Clip file size in case of disk full */ + 7700 .loc 1 4113 7 view .LVU2605 +4113:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst == 0) { /* Clip file size in case of disk full */ + 7701 .loc 1 4113 14 is_stmt 0 view .LVU2606 + 7702 0230 2946 mov r1, r5 + 7703 0232 2046 mov r0, r4 + 7704 0234 FFF7FEFF bl create_chain + 7705 .LVL885: +4114:Middlewares/Third_Party/FatFs/src/ff.c **** ofs = 0; break; + 7706 .loc 1 4114 7 is_stmt 1 view .LVU2607 +4114:Middlewares/Third_Party/FatFs/src/ff.c **** ofs = 0; break; + 7707 .loc 1 4114 10 is_stmt 0 view .LVU2608 + 7708 0238 0546 mov r5, r0 + 7709 023a 0028 cmp r0, #0 + 7710 023c E3D1 bne .L549 +4115:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7711 .loc 1 4115 12 view .LVU2609 + 7712 023e 0746 mov r7, r0 + 7713 .LVL886: + 7714 .L548: +4126:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs % SS(fs)) { + 7715 .loc 1 4126 5 is_stmt 1 view .LVU2610 +4126:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs % SS(fs)) { + 7716 .loc 1 4126 7 is_stmt 0 view .LVU2611 + 7717 0240 A369 ldr r3, [r4, #24] +4126:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs % SS(fs)) { + 7718 .loc 1 4126 14 view .LVU2612 + 7719 0242 3B44 add r3, r3, r7 + 7720 0244 A361 str r3, [r4, #24] +4127:Middlewares/Third_Party/FatFs/src/ff.c **** nsect = clust2sect(fs, clst); /* Current sector */ + 7721 .loc 1 4127 5 is_stmt 1 view .LVU2613 +4127:Middlewares/Third_Party/FatFs/src/ff.c **** nsect = clust2sect(fs, clst); /* Current sector */ + 7722 .loc 1 4127 15 is_stmt 0 view .LVU2614 + 7723 0246 0198 ldr r0, [sp, #4] + 7724 0248 B0F80C80 ldrh r8, [r0, #12] + 7725 .LVL887: +4127:Middlewares/Third_Party/FatFs/src/ff.c **** nsect = clust2sect(fs, clst); /* Current sector */ + 7726 .loc 1 4127 13 view .LVU2615 + 7727 024c B7FBF8F3 udiv r3, r7, r8 + ARM GAS /tmp/cc2SVLkL.s page 280 + + + 7728 0250 08FB1373 mls r3, r8, r3, r7 +4127:Middlewares/Third_Party/FatFs/src/ff.c **** nsect = clust2sect(fs, clst); /* Current sector */ + 7729 .loc 1 4127 8 view .LVU2616 + 7730 0254 8BB1 cbz r3, .L564 +4128:Middlewares/Third_Party/FatFs/src/ff.c **** if (!nsect) ABORT(fs, FR_INT_ERR); + 7731 .loc 1 4128 6 is_stmt 1 view .LVU2617 +4128:Middlewares/Third_Party/FatFs/src/ff.c **** if (!nsect) ABORT(fs, FR_INT_ERR); + 7732 .loc 1 4128 14 is_stmt 0 view .LVU2618 + 7733 0256 2946 mov r1, r5 + 7734 0258 FFF7FEFF bl clust2sect + 7735 .LVL888: +4129:Middlewares/Third_Party/FatFs/src/ff.c **** nsect += (DWORD)(ofs / SS(fs)); + 7736 .loc 1 4129 6 is_stmt 1 view .LVU2619 +4129:Middlewares/Third_Party/FatFs/src/ff.c **** nsect += (DWORD)(ofs / SS(fs)); + 7737 .loc 1 4129 9 is_stmt 0 view .LVU2620 + 7738 025c 0546 mov r5, r0 + 7739 .LVL889: +4129:Middlewares/Third_Party/FatFs/src/ff.c **** nsect += (DWORD)(ofs / SS(fs)); + 7740 .loc 1 4129 9 view .LVU2621 + 7741 025e 48B1 cbz r0, .L580 +4129:Middlewares/Third_Party/FatFs/src/ff.c **** nsect += (DWORD)(ofs / SS(fs)); + 7742 .loc 1 4129 39 is_stmt 1 discriminator 2 view .LVU2622 +4130:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7743 .loc 1 4130 6 view .LVU2623 +4130:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7744 .loc 1 4130 15 is_stmt 0 view .LVU2624 + 7745 0260 B7FBF8F7 udiv r7, r7, r8 + 7746 .LVL890: +4130:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7747 .loc 1 4130 12 view .LVU2625 + 7748 0264 3D44 add r5, r5, r7 + 7749 .LVL891: +4130:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7750 .loc 1 4130 12 view .LVU2626 + 7751 0266 92E7 b .L540 + 7752 .LVL892: + 7753 .L579: +4122:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR); + 7754 .loc 1 4122 30 is_stmt 1 discriminator 1 view .LVU2627 + 7755 0268 0126 movs r6, #1 + 7756 .LVL893: +4122:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR); + 7757 .loc 1 4122 30 is_stmt 0 discriminator 1 view .LVU2628 + 7758 026a 6675 strb r6, [r4, #21] +4122:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR); + 7759 .loc 1 4122 30 is_stmt 1 discriminator 1 view .LVU2629 +4122:Middlewares/Third_Party/FatFs/src/ff.c **** if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR); + 7760 .loc 1 4122 30 is_stmt 0 view .LVU2630 + 7761 026c E2E6 b .L525 + 7762 .LVL894: + 7763 .L551: +4123:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; + 7764 .loc 1 4123 45 is_stmt 1 discriminator 3 view .LVU2631 + 7765 026e 0226 movs r6, #2 + 7766 .LVL895: +4123:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; + 7767 .loc 1 4123 45 is_stmt 0 discriminator 3 view .LVU2632 + ARM GAS /tmp/cc2SVLkL.s page 281 + + + 7768 0270 6675 strb r6, [r4, #21] +4123:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; + 7769 .loc 1 4123 45 is_stmt 1 discriminator 3 view .LVU2633 +4123:Middlewares/Third_Party/FatFs/src/ff.c **** fp->clust = clst; + 7770 .loc 1 4123 45 is_stmt 0 view .LVU2634 + 7771 0272 DFE6 b .L525 + 7772 .LVL896: + 7773 .L580: +4129:Middlewares/Third_Party/FatFs/src/ff.c **** nsect += (DWORD)(ofs / SS(fs)); + 7774 .loc 1 4129 18 is_stmt 1 discriminator 1 view .LVU2635 + 7775 0274 0226 movs r6, #2 + 7776 .LVL897: +4129:Middlewares/Third_Party/FatFs/src/ff.c **** nsect += (DWORD)(ofs / SS(fs)); + 7777 .loc 1 4129 18 is_stmt 0 discriminator 1 view .LVU2636 + 7778 0276 6675 strb r6, [r4, #21] +4129:Middlewares/Third_Party/FatFs/src/ff.c **** nsect += (DWORD)(ofs / SS(fs)); + 7779 .loc 1 4129 18 is_stmt 1 discriminator 1 view .LVU2637 +4129:Middlewares/Third_Party/FatFs/src/ff.c **** nsect += (DWORD)(ofs / SS(fs)); + 7780 .loc 1 4129 18 is_stmt 0 view .LVU2638 + 7781 0278 DCE6 b .L525 + 7782 .LVL898: + 7783 .L564: +4084:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs) { + 7784 .loc 1 4084 20 view .LVU2639 + 7785 027a 1D46 mov r5, r3 + 7786 .LVL899: +4084:Middlewares/Third_Party/FatFs/src/ff.c **** if (ofs) { + 7787 .loc 1 4084 20 view .LVU2640 + 7788 027c 87E7 b .L540 + 7789 .LVL900: + 7790 .L575: +4142:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 7791 .loc 1 4142 5 is_stmt 1 view .LVU2641 +4142:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 7792 .loc 1 4142 9 is_stmt 0 view .LVU2642 + 7793 027e 0123 movs r3, #1 + 7794 0280 04F13001 add r1, r4, #48 + 7795 0284 4078 ldrb r0, [r0, #1] @ zero_extendqisi2 + 7796 0286 FFF7FEFF bl disk_write + 7797 .LVL901: +4142:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 7798 .loc 1 4142 8 discriminator 1 view .LVU2643 + 7799 028a 20B9 cbnz r0, .L581 +4142:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 7800 .loc 1 4142 84 is_stmt 1 discriminator 2 view .LVU2644 +4143:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7801 .loc 1 4143 5 view .LVU2645 +4143:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7802 .loc 1 4143 7 is_stmt 0 view .LVU2646 + 7803 028c 237D ldrb r3, [r4, #20] @ zero_extendqisi2 +4143:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7804 .loc 1 4143 14 view .LVU2647 + 7805 028e 03F07F03 and r3, r3, #127 + 7806 0292 2375 strb r3, [r4, #20] + 7807 0294 95E7 b .L556 + 7808 .L581: +4142:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + ARM GAS /tmp/cc2SVLkL.s page 282 + + + 7809 .loc 1 4142 62 is_stmt 1 discriminator 1 view .LVU2648 + 7810 0296 0126 movs r6, #1 + 7811 .LVL902: +4142:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 7812 .loc 1 4142 62 is_stmt 0 discriminator 1 view .LVU2649 + 7813 0298 6675 strb r6, [r4, #21] +4142:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 7814 .loc 1 4142 62 is_stmt 1 discriminator 1 view .LVU2650 +4142:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag &= (BYTE)~FA_DIRTY; + 7815 .loc 1 4142 62 is_stmt 0 view .LVU2651 + 7816 029a CBE6 b .L525 + 7817 .LVL903: + 7818 .L576: +4146:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7819 .loc 1 4146 57 is_stmt 1 discriminator 1 view .LVU2652 + 7820 029c 0126 movs r6, #1 + 7821 .LVL904: +4146:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7822 .loc 1 4146 57 is_stmt 0 discriminator 1 view .LVU2653 + 7823 029e 6675 strb r6, [r4, #21] +4146:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7824 .loc 1 4146 57 is_stmt 1 discriminator 1 view .LVU2654 +4146:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 7825 .loc 1 4146 57 is_stmt 0 view .LVU2655 + 7826 02a0 C8E6 b .L525 + 7827 .LVL905: + 7828 .L561: +4048:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7829 .loc 1 4048 9 view .LVU2656 + 7830 02a2 1126 movs r6, #17 + 7831 .LVL906: +4048:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7832 .loc 1 4048 9 view .LVU2657 + 7833 02a4 C6E6 b .L525 + 7834 .cfi_endproc + 7835 .LFE1227: + 7837 .section .text.f_opendir,"ax",%progbits + 7838 .align 1 + 7839 .global f_opendir + 7840 .syntax unified + 7841 .thumb + 7842 .thumb_func + 7844 f_opendir: + 7845 .LVL907: + 7846 .LFB1228: +4166:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 7847 .loc 1 4166 1 is_stmt 1 view -0 + 7848 .cfi_startproc + 7849 @ args = 0, pretend = 0, frame = 16 + 7850 @ frame_needed = 0, uses_anonymous_args = 0 +4166:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 7851 .loc 1 4166 1 is_stmt 0 view .LVU2659 + 7852 0000 30B5 push {r4, r5, lr} + 7853 .LCFI75: + 7854 .cfi_def_cfa_offset 12 + 7855 .cfi_offset 4, -12 + 7856 .cfi_offset 5, -8 + ARM GAS /tmp/cc2SVLkL.s page 283 + + + 7857 .cfi_offset 14, -4 + 7858 0002 85B0 sub sp, sp, #20 + 7859 .LCFI76: + 7860 .cfi_def_cfa_offset 32 + 7861 0004 0191 str r1, [sp, #4] +4167:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; + 7862 .loc 1 4167 2 is_stmt 1 view .LVU2660 +4168:Middlewares/Third_Party/FatFs/src/ff.c **** _FDID *obj; + 7863 .loc 1 4168 2 view .LVU2661 +4169:Middlewares/Third_Party/FatFs/src/ff.c **** DEF_NAMBUF + 7864 .loc 1 4169 2 view .LVU2662 +4173:Middlewares/Third_Party/FatFs/src/ff.c **** + 7865 .loc 1 4173 2 view .LVU2663 +4173:Middlewares/Third_Party/FatFs/src/ff.c **** + 7866 .loc 1 4173 5 is_stmt 0 view .LVU2664 + 7867 0006 0028 cmp r0, #0 + 7868 0008 3FD0 beq .L589 + 7869 000a 0546 mov r5, r0 +4176:Middlewares/Third_Party/FatFs/src/ff.c **** res = find_volume(&path, &fs, 0); + 7870 .loc 1 4176 2 is_stmt 1 view .LVU2665 + 7871 .LVL908: +4177:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 7872 .loc 1 4177 2 view .LVU2666 +4177:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 7873 .loc 1 4177 8 is_stmt 0 view .LVU2667 + 7874 000c 0022 movs r2, #0 + 7875 000e 03A9 add r1, sp, #12 + 7876 .LVL909: +4177:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 7877 .loc 1 4177 8 view .LVU2668 + 7878 0010 01A8 add r0, sp, #4 + 7879 .LVL910: +4177:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 7880 .loc 1 4177 8 view .LVU2669 + 7881 0012 FFF7FEFF bl find_volume + 7882 .LVL911: +4178:Middlewares/Third_Party/FatFs/src/ff.c **** obj->fs = fs; + 7883 .loc 1 4178 2 is_stmt 1 view .LVU2670 +4178:Middlewares/Third_Party/FatFs/src/ff.c **** obj->fs = fs; + 7884 .loc 1 4178 5 is_stmt 0 view .LVU2671 + 7885 0016 0446 mov r4, r0 + 7886 0018 20B1 cbz r0, .L594 + 7887 .LVL912: + 7888 .L584: +4220:Middlewares/Third_Party/FatFs/src/ff.c **** + 7889 .loc 1 4220 20 is_stmt 1 discriminator 1 view .LVU2672 +4220:Middlewares/Third_Party/FatFs/src/ff.c **** + 7890 .loc 1 4220 28 is_stmt 0 discriminator 1 view .LVU2673 + 7891 001a 0023 movs r3, #0 + 7892 001c 2B60 str r3, [r5] + 7893 .LVL913: + 7894 .L583: +4223:Middlewares/Third_Party/FatFs/src/ff.c **** + 7895 .loc 1 4223 1 view .LVU2674 + 7896 001e 2046 mov r0, r4 + 7897 0020 05B0 add sp, sp, #20 + 7898 .LCFI77: + ARM GAS /tmp/cc2SVLkL.s page 284 + + + 7899 .cfi_remember_state + 7900 .cfi_def_cfa_offset 12 + 7901 @ sp needed + 7902 0022 30BD pop {r4, r5, pc} + 7903 .LVL914: + 7904 .L594: + 7905 .LCFI78: + 7906 .cfi_restore_state +4179:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); + 7907 .loc 1 4179 3 is_stmt 1 view .LVU2675 +4179:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); + 7908 .loc 1 4179 11 is_stmt 0 view .LVU2676 + 7909 0024 039B ldr r3, [sp, #12] + 7910 0026 2B60 str r3, [r5] +4180:Middlewares/Third_Party/FatFs/src/ff.c **** res = follow_path(dp, path); /* Follow the path to the directory */ + 7911 .loc 1 4180 18 is_stmt 1 view .LVU2677 +4181:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Follow completed */ + 7912 .loc 1 4181 3 view .LVU2678 +4181:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Follow completed */ + 7913 .loc 1 4181 9 is_stmt 0 view .LVU2679 + 7914 0028 0199 ldr r1, [sp, #4] + 7915 002a 2846 mov r0, r5 + 7916 .LVL915: +4181:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Follow completed */ + 7917 .loc 1 4181 9 view .LVU2680 + 7918 002c FFF7FEFF bl follow_path + 7919 .LVL916: +4182:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(dp->fn[NSFLAG] & NS_NONAME)) { /* It is not the origin directory itself */ + 7920 .loc 1 4182 3 is_stmt 1 view .LVU2681 +4182:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(dp->fn[NSFLAG] & NS_NONAME)) { /* It is not the origin directory itself */ + 7921 .loc 1 4182 6 is_stmt 0 view .LVU2682 + 7922 0030 0446 mov r4, r0 + 7923 0032 18BB cbnz r0, .L585 +4183:Middlewares/Third_Party/FatFs/src/ff.c **** if (obj->attr & AM_DIR) { /* This object is a sub-directory */ + 7924 .loc 1 4183 4 is_stmt 1 view .LVU2683 +4183:Middlewares/Third_Party/FatFs/src/ff.c **** if (obj->attr & AM_DIR) { /* This object is a sub-directory */ + 7925 .loc 1 4183 8 is_stmt 0 view .LVU2684 + 7926 0034 95F92F30 ldrsb r3, [r5, #47] +4183:Middlewares/Third_Party/FatFs/src/ff.c **** if (obj->attr & AM_DIR) { /* This object is a sub-directory */ + 7927 .loc 1 4183 7 view .LVU2685 + 7928 0038 002B cmp r3, #0 + 7929 003a 08DB blt .L586 +4184:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 7930 .loc 1 4184 5 is_stmt 1 view .LVU2686 +4184:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 7931 .loc 1 4184 12 is_stmt 0 view .LVU2687 + 7932 003c AB79 ldrb r3, [r5, #6] @ zero_extendqisi2 +4184:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 7933 .loc 1 4184 8 view .LVU2688 + 7934 003e 13F0100F tst r3, #16 + 7935 0042 1AD0 beq .L590 +4196:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7936 .loc 1 4196 7 is_stmt 1 view .LVU2689 +4196:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7937 .loc 1 4196 21 is_stmt 0 view .LVU2690 + 7938 0044 296A ldr r1, [r5, #32] + 7939 0046 0398 ldr r0, [sp, #12] + ARM GAS /tmp/cc2SVLkL.s page 285 + + + 7940 .LVL917: +4196:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7941 .loc 1 4196 21 view .LVU2691 + 7942 0048 FFF7FEFF bl ld_clust + 7943 .LVL918: +4196:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7944 .loc 1 4196 19 discriminator 1 view .LVU2692 + 7945 004c A860 str r0, [r5, #8] + 7946 .L586: +4202:Middlewares/Third_Party/FatFs/src/ff.c **** obj->id = fs->id; + 7947 .loc 1 4202 4 is_stmt 1 view .LVU2693 +4203:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(dp, 0); /* Rewind directory */ + 7948 .loc 1 4203 5 view .LVU2694 +4203:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(dp, 0); /* Rewind directory */ + 7949 .loc 1 4203 17 is_stmt 0 view .LVU2695 + 7950 004e 039B ldr r3, [sp, #12] + 7951 0050 DB88 ldrh r3, [r3, #6] +4203:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(dp, 0); /* Rewind directory */ + 7952 .loc 1 4203 13 view .LVU2696 + 7953 0052 AB80 strh r3, [r5, #4] @ movhi +4204:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 7954 .loc 1 4204 5 is_stmt 1 view .LVU2697 +4204:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 7955 .loc 1 4204 11 is_stmt 0 view .LVU2698 + 7956 0054 0021 movs r1, #0 + 7957 0056 2846 mov r0, r5 + 7958 0058 FFF7FEFF bl dir_sdi + 7959 .LVL919: +4206:Middlewares/Third_Party/FatFs/src/ff.c **** if (obj->sclust) { + 7960 .loc 1 4206 5 is_stmt 1 view .LVU2699 +4206:Middlewares/Third_Party/FatFs/src/ff.c **** if (obj->sclust) { + 7961 .loc 1 4206 8 is_stmt 0 view .LVU2700 + 7962 005c 0446 mov r4, r0 + 7963 005e 68B9 cbnz r0, .L585 +4207:Middlewares/Third_Party/FatFs/src/ff.c **** obj->lockid = inc_lock(dp, 0); /* Lock the sub directory */ + 7964 .loc 1 4207 6 is_stmt 1 view .LVU2701 +4207:Middlewares/Third_Party/FatFs/src/ff.c **** obj->lockid = inc_lock(dp, 0); /* Lock the sub directory */ + 7965 .loc 1 4207 13 is_stmt 0 view .LVU2702 + 7966 0060 AB68 ldr r3, [r5, #8] +4207:Middlewares/Third_Party/FatFs/src/ff.c **** obj->lockid = inc_lock(dp, 0); /* Lock the sub directory */ + 7967 .loc 1 4207 9 view .LVU2703 + 7968 0062 13B9 cbnz r3, .L595 +4211:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7969 .loc 1 4211 7 is_stmt 1 view .LVU2704 +4211:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7970 .loc 1 4211 19 is_stmt 0 view .LVU2705 + 7971 0064 0023 movs r3, #0 + 7972 0066 2B61 str r3, [r5, #16] + 7973 0068 08E0 b .L585 + 7974 .L595: +4208:Middlewares/Third_Party/FatFs/src/ff.c **** if (!obj->lockid) res = FR_TOO_MANY_OPEN_FILES; + 7975 .loc 1 4208 7 is_stmt 1 view .LVU2706 +4208:Middlewares/Third_Party/FatFs/src/ff.c **** if (!obj->lockid) res = FR_TOO_MANY_OPEN_FILES; + 7976 .loc 1 4208 21 is_stmt 0 view .LVU2707 + 7977 006a 0021 movs r1, #0 + 7978 006c 2846 mov r0, r5 + 7979 .LVL920: + ARM GAS /tmp/cc2SVLkL.s page 286 + + +4208:Middlewares/Third_Party/FatFs/src/ff.c **** if (!obj->lockid) res = FR_TOO_MANY_OPEN_FILES; + 7980 .loc 1 4208 21 view .LVU2708 + 7981 006e FFF7FEFF bl inc_lock + 7982 .LVL921: +4208:Middlewares/Third_Party/FatFs/src/ff.c **** if (!obj->lockid) res = FR_TOO_MANY_OPEN_FILES; + 7983 .loc 1 4208 19 discriminator 1 view .LVU2709 + 7984 0072 2861 str r0, [r5, #16] +4209:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 7985 .loc 1 4209 7 is_stmt 1 view .LVU2710 +4209:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 7986 .loc 1 4209 10 is_stmt 0 view .LVU2711 + 7987 0074 10B9 cbnz r0, .L585 + 7988 .LVL922: +4209:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 7989 .loc 1 4209 29 discriminator 1 view .LVU2712 + 7990 0076 1224 movs r4, #18 + 7991 0078 02E0 b .L588 + 7992 .LVL923: + 7993 .L590: +4199:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7994 .loc 1 4199 10 view .LVU2713 + 7995 007a 0524 movs r4, #5 + 7996 .LVL924: + 7997 .L585: +4217:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) res = FR_NO_PATH; + 7998 .loc 1 4217 16 is_stmt 1 view .LVU2714 +4218:Middlewares/Third_Party/FatFs/src/ff.c **** } + 7999 .loc 1 4218 3 view .LVU2715 +4218:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8000 .loc 1 4218 6 is_stmt 0 view .LVU2716 + 8001 007c 042C cmp r4, #4 + 8002 007e 02D0 beq .L596 + 8003 .LVL925: + 8004 .L588: +4220:Middlewares/Third_Party/FatFs/src/ff.c **** + 8005 .loc 1 4220 2 is_stmt 1 view .LVU2717 +4220:Middlewares/Third_Party/FatFs/src/ff.c **** + 8006 .loc 1 4220 5 is_stmt 0 view .LVU2718 + 8007 0080 002C cmp r4, #0 + 8008 0082 CCD0 beq .L583 + 8009 0084 C9E7 b .L584 + 8010 .L596: + 8011 .LVL926: +4218:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8012 .loc 1 4218 30 discriminator 1 view .LVU2719 + 8013 0086 0524 movs r4, #5 + 8014 0088 C7E7 b .L584 + 8015 .LVL927: + 8016 .L589: +4173:Middlewares/Third_Party/FatFs/src/ff.c **** + 8017 .loc 1 4173 18 discriminator 1 view .LVU2720 + 8018 008a 0924 movs r4, #9 + 8019 008c C7E7 b .L583 + 8020 .cfi_endproc + 8021 .LFE1228: + 8023 .section .text.f_closedir,"ax",%progbits + 8024 .align 1 + ARM GAS /tmp/cc2SVLkL.s page 287 + + + 8025 .global f_closedir + 8026 .syntax unified + 8027 .thumb + 8028 .thumb_func + 8030 f_closedir: + 8031 .LVL928: + 8032 .LFB1229: +4235:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 8033 .loc 1 4235 1 is_stmt 1 view -0 + 8034 .cfi_startproc + 8035 @ args = 0, pretend = 0, frame = 8 + 8036 @ frame_needed = 0, uses_anonymous_args = 0 +4235:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 8037 .loc 1 4235 1 is_stmt 0 view .LVU2722 + 8038 0000 10B5 push {r4, lr} + 8039 .LCFI79: + 8040 .cfi_def_cfa_offset 8 + 8041 .cfi_offset 4, -8 + 8042 .cfi_offset 14, -4 + 8043 0002 82B0 sub sp, sp, #8 + 8044 .LCFI80: + 8045 .cfi_def_cfa_offset 16 + 8046 0004 0446 mov r4, r0 +4236:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; + 8047 .loc 1 4236 2 is_stmt 1 view .LVU2723 +4237:Middlewares/Third_Party/FatFs/src/ff.c **** + 8048 .loc 1 4237 2 view .LVU2724 +4240:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 8049 .loc 1 4240 2 view .LVU2725 +4240:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 8050 .loc 1 4240 8 is_stmt 0 view .LVU2726 + 8051 0006 01A9 add r1, sp, #4 + 8052 0008 FFF7FEFF bl validate + 8053 .LVL929: +4241:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 8054 .loc 1 4241 2 is_stmt 1 view .LVU2727 +4241:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 8055 .loc 1 4241 5 is_stmt 0 view .LVU2728 + 8056 000c 20B9 cbnz r0, .L598 +4243:Middlewares/Third_Party/FatFs/src/ff.c **** res = dec_lock(dp->obj.lockid); + 8057 .loc 1 4243 3 is_stmt 1 view .LVU2729 +4243:Middlewares/Third_Party/FatFs/src/ff.c **** res = dec_lock(dp->obj.lockid); + 8058 .loc 1 4243 14 is_stmt 0 view .LVU2730 + 8059 000e 2369 ldr r3, [r4, #16] +4243:Middlewares/Third_Party/FatFs/src/ff.c **** res = dec_lock(dp->obj.lockid); + 8060 .loc 1 4243 6 view .LVU2731 + 8061 0010 23B9 cbnz r3, .L601 + 8062 .L599: + 8063 .LVL930: +4246:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 8064 .loc 1 4246 3 is_stmt 1 view .LVU2732 +4246:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 8065 .loc 1 4246 6 is_stmt 0 view .LVU2733 + 8066 0012 08B9 cbnz r0, .L598 +4249:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8067 .loc 1 4249 4 is_stmt 1 view .LVU2734 +4249:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 288 + + + 8068 .loc 1 4249 15 is_stmt 0 view .LVU2735 + 8069 0014 0023 movs r3, #0 + 8070 0016 2360 str r3, [r4] + 8071 .LVL931: + 8072 .L598: +4255:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8073 .loc 1 4255 2 is_stmt 1 view .LVU2736 +4256:Middlewares/Third_Party/FatFs/src/ff.c **** + 8074 .loc 1 4256 1 is_stmt 0 view .LVU2737 + 8075 0018 02B0 add sp, sp, #8 + 8076 .LCFI81: + 8077 .cfi_remember_state + 8078 .cfi_def_cfa_offset 8 + 8079 @ sp needed + 8080 001a 10BD pop {r4, pc} + 8081 .LVL932: + 8082 .L601: + 8083 .LCFI82: + 8084 .cfi_restore_state +4244:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8085 .loc 1 4244 4 is_stmt 1 view .LVU2738 +4244:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8086 .loc 1 4244 10 is_stmt 0 view .LVU2739 + 8087 001c 1846 mov r0, r3 + 8088 001e FFF7FEFF bl dec_lock + 8089 .LVL933: +4244:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8090 .loc 1 4244 10 view .LVU2740 + 8091 0022 F6E7 b .L599 + 8092 .cfi_endproc + 8093 .LFE1229: + 8095 .section .text.f_readdir,"ax",%progbits + 8096 .align 1 + 8097 .global f_readdir + 8098 .syntax unified + 8099 .thumb + 8100 .thumb_func + 8102 f_readdir: + 8103 .LVL934: + 8104 .LFB1230: +4269:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 8105 .loc 1 4269 1 is_stmt 1 view -0 + 8106 .cfi_startproc + 8107 @ args = 0, pretend = 0, frame = 8 + 8108 @ frame_needed = 0, uses_anonymous_args = 0 +4269:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 8109 .loc 1 4269 1 is_stmt 0 view .LVU2742 + 8110 0000 70B5 push {r4, r5, r6, lr} + 8111 .LCFI83: + 8112 .cfi_def_cfa_offset 16 + 8113 .cfi_offset 4, -16 + 8114 .cfi_offset 5, -12 + 8115 .cfi_offset 6, -8 + 8116 .cfi_offset 14, -4 + 8117 0002 82B0 sub sp, sp, #8 + 8118 .LCFI84: + 8119 .cfi_def_cfa_offset 24 + ARM GAS /tmp/cc2SVLkL.s page 289 + + + 8120 0004 0446 mov r4, r0 + 8121 0006 0D46 mov r5, r1 +4270:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; + 8122 .loc 1 4270 2 is_stmt 1 view .LVU2743 +4271:Middlewares/Third_Party/FatFs/src/ff.c **** DEF_NAMBUF + 8123 .loc 1 4271 2 view .LVU2744 +4275:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 8124 .loc 1 4275 2 view .LVU2745 +4275:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 8125 .loc 1 4275 8 is_stmt 0 view .LVU2746 + 8126 0008 01A9 add r1, sp, #4 + 8127 .LVL935: +4275:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 8128 .loc 1 4275 8 view .LVU2747 + 8129 000a FFF7FEFF bl validate + 8130 .LVL936: +4276:Middlewares/Third_Party/FatFs/src/ff.c **** if (!fno) { + 8131 .loc 1 4276 2 is_stmt 1 view .LVU2748 +4276:Middlewares/Third_Party/FatFs/src/ff.c **** if (!fno) { + 8132 .loc 1 4276 5 is_stmt 0 view .LVU2749 + 8133 000e 0646 mov r6, r0 + 8134 0010 C0B9 cbnz r0, .L603 +4277:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(dp, 0); /* Rewind the directory object */ + 8135 .loc 1 4277 3 is_stmt 1 view .LVU2750 +4277:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_sdi(dp, 0); /* Rewind the directory object */ + 8136 .loc 1 4277 6 is_stmt 0 view .LVU2751 + 8137 0012 95B1 cbz r5, .L608 +4280:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_read(dp, 0); /* Read an item */ + 8138 .loc 1 4280 19 is_stmt 1 view .LVU2752 +4281:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory */ + 8139 .loc 1 4281 4 view .LVU2753 +4281:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory */ + 8140 .loc 1 4281 10 is_stmt 0 view .LVU2754 + 8141 0014 0021 movs r1, #0 + 8142 0016 2046 mov r0, r4 + 8143 .LVL937: +4281:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory */ + 8144 .loc 1 4281 10 view .LVU2755 + 8145 0018 FFF7FEFF bl dir_read + 8146 .LVL938: +4282:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* A valid entry is found */ + 8147 .loc 1 4282 4 is_stmt 1 view .LVU2756 +4282:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* A valid entry is found */ + 8148 .loc 1 4282 7 is_stmt 0 view .LVU2757 + 8149 001c 0428 cmp r0, #4 + 8150 001e 00D0 beq .L605 +4283:Middlewares/Third_Party/FatFs/src/ff.c **** get_fileinfo(dp, fno); /* Get the object information */ + 8151 .loc 1 4283 4 is_stmt 1 view .LVU2758 +4283:Middlewares/Third_Party/FatFs/src/ff.c **** get_fileinfo(dp, fno); /* Get the object information */ + 8152 .loc 1 4283 7 is_stmt 0 view .LVU2759 + 8153 0020 98B9 cbnz r0, .L606 + 8154 .L605: + 8155 .LVL939: +4284:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_next(dp, 0); /* Increment index for next */ + 8156 .loc 1 4284 5 is_stmt 1 view .LVU2760 + 8157 0022 2946 mov r1, r5 + 8158 0024 2046 mov r0, r4 + ARM GAS /tmp/cc2SVLkL.s page 290 + + + 8159 0026 FFF7FEFF bl get_fileinfo + 8160 .LVL940: +4285:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory now */ + 8161 .loc 1 4285 5 view .LVU2761 +4285:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory now */ + 8162 .loc 1 4285 11 is_stmt 0 view .LVU2762 + 8163 002a 0021 movs r1, #0 + 8164 002c 2046 mov r0, r4 + 8165 002e FFF7FEFF bl dir_next + 8166 .LVL941: +4286:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8167 .loc 1 4286 5 is_stmt 1 view .LVU2763 +4286:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8168 .loc 1 4286 8 is_stmt 0 view .LVU2764 + 8169 0032 0428 cmp r0, #4 + 8170 0034 06D0 beq .L603 +4285:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory now */ + 8171 .loc 1 4285 11 view .LVU2765 + 8172 0036 0646 mov r6, r0 + 8173 0038 04E0 b .L603 + 8174 .L608: +4278:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 8175 .loc 1 4278 4 is_stmt 1 view .LVU2766 +4278:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 8176 .loc 1 4278 10 is_stmt 0 view .LVU2767 + 8177 003a 0021 movs r1, #0 + 8178 003c 2046 mov r0, r4 + 8179 .LVL942: +4278:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 8180 .loc 1 4278 10 view .LVU2768 + 8181 003e FFF7FEFF bl dir_sdi + 8182 .LVL943: + 8183 0042 0646 mov r6, r0 + 8184 .LVL944: + 8185 .L603: +4288:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8186 .loc 1 4288 17 is_stmt 1 view .LVU2769 +4291:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8187 .loc 1 4291 2 view .LVU2770 +4292:Middlewares/Third_Party/FatFs/src/ff.c **** + 8188 .loc 1 4292 1 is_stmt 0 view .LVU2771 + 8189 0044 3046 mov r0, r6 + 8190 0046 02B0 add sp, sp, #8 + 8191 .LCFI85: + 8192 .cfi_remember_state + 8193 .cfi_def_cfa_offset 16 + 8194 @ sp needed + 8195 0048 70BD pop {r4, r5, r6, pc} + 8196 .LVL945: + 8197 .L606: + 8198 .LCFI86: + 8199 .cfi_restore_state +4292:Middlewares/Third_Party/FatFs/src/ff.c **** + 8200 .loc 1 4292 1 view .LVU2772 + 8201 004a 0646 mov r6, r0 + 8202 004c FAE7 b .L603 + 8203 .cfi_endproc + ARM GAS /tmp/cc2SVLkL.s page 291 + + + 8204 .LFE1230: + 8206 .section .text.f_stat,"ax",%progbits + 8207 .align 1 + 8208 .global f_stat + 8209 .syntax unified + 8210 .thumb + 8211 .thumb_func + 8213 f_stat: + 8214 .LVL946: + 8215 .LFB1231: +4357:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 8216 .loc 1 4357 1 is_stmt 1 view -0 + 8217 .cfi_startproc + 8218 @ args = 0, pretend = 0, frame = 56 + 8219 @ frame_needed = 0, uses_anonymous_args = 0 +4357:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 8220 .loc 1 4357 1 is_stmt 0 view .LVU2774 + 8221 0000 30B5 push {r4, r5, lr} + 8222 .LCFI87: + 8223 .cfi_def_cfa_offset 12 + 8224 .cfi_offset 4, -12 + 8225 .cfi_offset 5, -8 + 8226 .cfi_offset 14, -4 + 8227 0002 8FB0 sub sp, sp, #60 + 8228 .LCFI88: + 8229 .cfi_def_cfa_offset 72 + 8230 0004 0190 str r0, [sp, #4] + 8231 0006 0C46 mov r4, r1 +4358:Middlewares/Third_Party/FatFs/src/ff.c **** DIR dj; + 8232 .loc 1 4358 2 is_stmt 1 view .LVU2775 +4359:Middlewares/Third_Party/FatFs/src/ff.c **** DEF_NAMBUF + 8233 .loc 1 4359 2 view .LVU2776 +4364:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 8234 .loc 1 4364 2 view .LVU2777 +4364:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 8235 .loc 1 4364 8 is_stmt 0 view .LVU2778 + 8236 0008 0022 movs r2, #0 + 8237 000a 02A9 add r1, sp, #8 + 8238 .LVL947: +4364:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 8239 .loc 1 4364 8 view .LVU2779 + 8240 000c 01A8 add r0, sp, #4 + 8241 .LVL948: +4364:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 8242 .loc 1 4364 8 view .LVU2780 + 8243 000e FFF7FEFF bl find_volume + 8244 .LVL949: +4365:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(dj.obj.fs); + 8245 .loc 1 4365 2 is_stmt 1 view .LVU2781 +4365:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(dj.obj.fs); + 8246 .loc 1 4365 5 is_stmt 0 view .LVU2782 + 8247 0012 0546 mov r5, r0 + 8248 0014 10B1 cbz r0, .L613 + 8249 .LVL950: + 8250 .L610: +4375:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8251 .loc 1 4375 16 is_stmt 1 view .LVU2783 + ARM GAS /tmp/cc2SVLkL.s page 292 + + +4378:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8252 .loc 1 4378 2 view .LVU2784 +4379:Middlewares/Third_Party/FatFs/src/ff.c **** + 8253 .loc 1 4379 1 is_stmt 0 view .LVU2785 + 8254 0016 2846 mov r0, r5 + 8255 0018 0FB0 add sp, sp, #60 + 8256 .LCFI89: + 8257 .cfi_remember_state + 8258 .cfi_def_cfa_offset 12 + 8259 @ sp needed + 8260 001a 30BD pop {r4, r5, pc} + 8261 .LVL951: + 8262 .L613: + 8263 .LCFI90: + 8264 .cfi_restore_state +4366:Middlewares/Third_Party/FatFs/src/ff.c **** res = follow_path(&dj, path); /* Follow the file path */ + 8265 .loc 1 4366 25 is_stmt 1 view .LVU2786 +4367:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Follow completed */ + 8266 .loc 1 4367 3 view .LVU2787 +4367:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Follow completed */ + 8267 .loc 1 4367 9 is_stmt 0 view .LVU2788 + 8268 001c 0199 ldr r1, [sp, #4] + 8269 001e 02A8 add r0, sp, #8 + 8270 .LVL952: +4367:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Follow completed */ + 8271 .loc 1 4367 9 view .LVU2789 + 8272 0020 FFF7FEFF bl follow_path + 8273 .LVL953: +4368:Middlewares/Third_Party/FatFs/src/ff.c **** if (dj.fn[NSFLAG] & NS_NONAME) { /* It is origin directory */ + 8274 .loc 1 4368 3 is_stmt 1 view .LVU2790 +4368:Middlewares/Third_Party/FatFs/src/ff.c **** if (dj.fn[NSFLAG] & NS_NONAME) { /* It is origin directory */ + 8275 .loc 1 4368 6 is_stmt 0 view .LVU2791 + 8276 0024 0546 mov r5, r0 + 8277 0026 0028 cmp r0, #0 + 8278 0028 F5D1 bne .L610 +4369:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INVALID_NAME; + 8279 .loc 1 4369 4 is_stmt 1 view .LVU2792 +4369:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INVALID_NAME; + 8280 .loc 1 4369 8 is_stmt 0 view .LVU2793 + 8281 002a 9DF93730 ldrsb r3, [sp, #55] +4369:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INVALID_NAME; + 8282 .loc 1 4369 7 view .LVU2794 + 8283 002e 002B cmp r3, #0 + 8284 0030 06DB blt .L611 +4372:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8285 .loc 1 4372 5 is_stmt 1 view .LVU2795 +4372:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8286 .loc 1 4372 8 is_stmt 0 view .LVU2796 + 8287 0032 002C cmp r4, #0 + 8288 0034 EFD0 beq .L610 +4372:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8289 .loc 1 4372 14 is_stmt 1 discriminator 1 view .LVU2797 + 8290 0036 2146 mov r1, r4 + 8291 0038 02A8 add r0, sp, #8 + 8292 .LVL954: +4372:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8293 .loc 1 4372 14 is_stmt 0 discriminator 1 view .LVU2798 + ARM GAS /tmp/cc2SVLkL.s page 293 + + + 8294 003a FFF7FEFF bl get_fileinfo + 8295 .LVL955: + 8296 003e EAE7 b .L610 + 8297 .LVL956: + 8298 .L611: +4370:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* Found an object */ + 8299 .loc 1 4370 9 view .LVU2799 + 8300 0040 0625 movs r5, #6 + 8301 0042 E8E7 b .L610 + 8302 .cfi_endproc + 8303 .LFE1231: + 8305 .section .text.f_getfree,"ax",%progbits + 8306 .align 1 + 8307 .global f_getfree + 8308 .syntax unified + 8309 .thumb + 8310 .thumb_func + 8312 f_getfree: + 8313 .LVL957: + 8314 .LFB1232: +4393:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 8315 .loc 1 4393 1 is_stmt 1 view -0 + 8316 .cfi_startproc + 8317 @ args = 0, pretend = 0, frame = 32 + 8318 @ frame_needed = 0, uses_anonymous_args = 0 +4393:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 8319 .loc 1 4393 1 is_stmt 0 view .LVU2801 + 8320 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 8321 .LCFI91: + 8322 .cfi_def_cfa_offset 36 + 8323 .cfi_offset 4, -36 + 8324 .cfi_offset 5, -32 + 8325 .cfi_offset 6, -28 + 8326 .cfi_offset 7, -24 + 8327 .cfi_offset 8, -20 + 8328 .cfi_offset 9, -16 + 8329 .cfi_offset 10, -12 + 8330 .cfi_offset 11, -8 + 8331 .cfi_offset 14, -4 + 8332 0004 89B0 sub sp, sp, #36 + 8333 .LCFI92: + 8334 .cfi_def_cfa_offset 72 + 8335 0006 0190 str r0, [sp, #4] + 8336 0008 8846 mov r8, r1 + 8337 000a 1446 mov r4, r2 +4394:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; + 8338 .loc 1 4394 2 is_stmt 1 view .LVU2802 +4395:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD nfree, clst, sect, stat; + 8339 .loc 1 4395 2 view .LVU2803 +4396:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i; + 8340 .loc 1 4396 2 view .LVU2804 +4397:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE *p; + 8341 .loc 1 4397 2 view .LVU2805 +4398:Middlewares/Third_Party/FatFs/src/ff.c **** _FDID obj; + 8342 .loc 1 4398 2 view .LVU2806 +4399:Middlewares/Third_Party/FatFs/src/ff.c **** + 8343 .loc 1 4399 2 view .LVU2807 + ARM GAS /tmp/cc2SVLkL.s page 294 + + +4403:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 8344 .loc 1 4403 2 view .LVU2808 +4403:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 8345 .loc 1 4403 8 is_stmt 0 view .LVU2809 + 8346 000c 0022 movs r2, #0 + 8347 .LVL958: +4403:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 8348 .loc 1 4403 8 view .LVU2810 + 8349 000e 07A9 add r1, sp, #28 + 8350 .LVL959: +4403:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 8351 .loc 1 4403 8 view .LVU2811 + 8352 0010 01A8 add r0, sp, #4 + 8353 .LVL960: +4403:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 8354 .loc 1 4403 8 view .LVU2812 + 8355 0012 FFF7FEFF bl find_volume + 8356 .LVL961: +4404:Middlewares/Third_Party/FatFs/src/ff.c **** *fatfs = fs; /* Return ptr to the fs object */ + 8357 .loc 1 4404 2 is_stmt 1 view .LVU2813 +4404:Middlewares/Third_Party/FatFs/src/ff.c **** *fatfs = fs; /* Return ptr to the fs object */ + 8358 .loc 1 4404 5 is_stmt 0 view .LVU2814 + 8359 0016 8146 mov r9, r0 + 8360 0018 0028 cmp r0, #0 + 8361 001a 59D1 bne .L615 +4405:Middlewares/Third_Party/FatFs/src/ff.c **** /* If free_clst is valid, return it without full cluster scan */ + 8362 .loc 1 4405 3 is_stmt 1 view .LVU2815 +4405:Middlewares/Third_Party/FatFs/src/ff.c **** /* If free_clst is valid, return it without full cluster scan */ + 8363 .loc 1 4405 10 is_stmt 0 view .LVU2816 + 8364 001c 079B ldr r3, [sp, #28] + 8365 001e 2360 str r3, [r4] +4407:Middlewares/Third_Party/FatFs/src/ff.c **** *nclst = fs->free_clst; + 8366 .loc 1 4407 3 is_stmt 1 view .LVU2817 +4407:Middlewares/Third_Party/FatFs/src/ff.c **** *nclst = fs->free_clst; + 8367 .loc 1 4407 9 is_stmt 0 view .LVU2818 + 8368 0020 5A69 ldr r2, [r3, #20] +4407:Middlewares/Third_Party/FatFs/src/ff.c **** *nclst = fs->free_clst; + 8369 .loc 1 4407 26 view .LVU2819 + 8370 0022 9D69 ldr r5, [r3, #24] +4407:Middlewares/Third_Party/FatFs/src/ff.c **** *nclst = fs->free_clst; + 8371 .loc 1 4407 37 view .LVU2820 + 8372 0024 A91E subs r1, r5, #2 +4407:Middlewares/Third_Party/FatFs/src/ff.c **** *nclst = fs->free_clst; + 8373 .loc 1 4407 6 view .LVU2821 + 8374 0026 8A42 cmp r2, r1 + 8375 0028 02D8 bhi .L616 +4408:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 8376 .loc 1 4408 4 is_stmt 1 view .LVU2822 +4408:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 8377 .loc 1 4408 11 is_stmt 0 view .LVU2823 + 8378 002a C8F80020 str r2, [r8] + 8379 002e 4FE0 b .L615 + 8380 .L616: +4411:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_FAT12) { /* FAT12: Sector unalighed FAT entries */ + 8381 .loc 1 4411 4 is_stmt 1 view .LVU2824 + 8382 .LVL962: +4412:Middlewares/Third_Party/FatFs/src/ff.c **** clst = 2; obj.fs = fs; + ARM GAS /tmp/cc2SVLkL.s page 295 + + + 8383 .loc 1 4412 4 view .LVU2825 +4412:Middlewares/Third_Party/FatFs/src/ff.c **** clst = 2; obj.fs = fs; + 8384 .loc 1 4412 10 is_stmt 0 view .LVU2826 + 8385 0030 1E78 ldrb r6, [r3] @ zero_extendqisi2 +4412:Middlewares/Third_Party/FatFs/src/ff.c **** clst = 2; obj.fs = fs; + 8386 .loc 1 4412 7 view .LVU2827 + 8387 0032 012E cmp r6, #1 + 8388 0034 05D0 beq .L630 +4440:Middlewares/Third_Party/FatFs/src/ff.c **** i = 0; p = 0; + 8389 .loc 1 4440 6 is_stmt 1 view .LVU2828 + 8390 .LVL963: +4440:Middlewares/Third_Party/FatFs/src/ff.c **** i = 0; p = 0; + 8391 .loc 1 4440 27 view .LVU2829 +4440:Middlewares/Third_Party/FatFs/src/ff.c **** i = 0; p = 0; + 8392 .loc 1 4440 32 is_stmt 0 view .LVU2830 + 8393 0036 D3F824A0 ldr r10, [r3, #36] + 8394 .LVL964: +4441:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 8395 .loc 1 4441 6 is_stmt 1 view .LVU2831 +4441:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 8396 .loc 1 4441 13 view .LVU2832 +4441:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 8397 .loc 1 4441 15 is_stmt 0 view .LVU2833 + 8398 003a 0024 movs r4, #0 + 8399 .LVL965: +4441:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 8400 .loc 1 4441 8 view .LVU2834 + 8401 003c 2646 mov r6, r4 +4411:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_FAT12) { /* FAT12: Sector unalighed FAT entries */ + 8402 .loc 1 4411 10 view .LVU2835 + 8403 003e 2746 mov r7, r4 + 8404 0040 2FE0 b .L626 + 8405 .LVL966: + 8406 .L630: +4413:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 8407 .loc 1 4413 5 is_stmt 1 view .LVU2836 +4413:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 8408 .loc 1 4413 15 view .LVU2837 +4413:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 8409 .loc 1 4413 22 is_stmt 0 view .LVU2838 + 8410 0042 0293 str r3, [sp, #8] +4413:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 8411 .loc 1 4413 10 view .LVU2839 + 8412 0044 0224 movs r4, #2 + 8413 .LVL967: +4411:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_FAT12) { /* FAT12: Sector unalighed FAT entries */ + 8414 .loc 1 4411 10 view .LVU2840 + 8415 0046 0027 movs r7, #0 + 8416 0048 04E0 b .L620 + 8417 .LVL968: + 8418 .L619: +4419:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 8419 .loc 1 4419 21 is_stmt 1 view .LVU2841 + 8420 004a 0134 adds r4, r4, #1 + 8421 .LVL969: +4419:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 8422 .loc 1 4419 25 is_stmt 0 view .LVU2842 + ARM GAS /tmp/cc2SVLkL.s page 296 + + + 8423 004c 079B ldr r3, [sp, #28] + 8424 004e 9B69 ldr r3, [r3, #24] +4419:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 8425 .loc 1 4419 21 view .LVU2843 + 8426 0050 A342 cmp r3, r4 + 8427 0052 35D9 bls .L618 + 8428 .LVL970: + 8429 .L620: +4414:Middlewares/Third_Party/FatFs/src/ff.c **** stat = get_fat(&obj, clst); + 8430 .loc 1 4414 5 is_stmt 1 view .LVU2844 +4415:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } + 8431 .loc 1 4415 6 view .LVU2845 +4415:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } + 8432 .loc 1 4415 13 is_stmt 0 view .LVU2846 + 8433 0054 2146 mov r1, r4 + 8434 0056 02A8 add r0, sp, #8 + 8435 0058 FFF7FEFF bl get_fat + 8436 .LVL971: +4416:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat == 1) { res = FR_INT_ERR; break; } + 8437 .loc 1 4416 6 is_stmt 1 view .LVU2847 +4416:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat == 1) { res = FR_INT_ERR; break; } + 8438 .loc 1 4416 9 is_stmt 0 view .LVU2848 + 8439 005c B0F1FF3F cmp r0, #-1 + 8440 0060 2DD0 beq .L627 +4417:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat == 0) nfree++; + 8441 .loc 1 4417 6 is_stmt 1 view .LVU2849 +4417:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat == 0) nfree++; + 8442 .loc 1 4417 9 is_stmt 0 view .LVU2850 + 8443 0062 0128 cmp r0, #1 + 8444 0064 38D0 beq .L628 +4418:Middlewares/Third_Party/FatFs/src/ff.c **** } while (++clst < fs->n_fatent); + 8445 .loc 1 4418 6 is_stmt 1 view .LVU2851 +4418:Middlewares/Third_Party/FatFs/src/ff.c **** } while (++clst < fs->n_fatent); + 8446 .loc 1 4418 9 is_stmt 0 view .LVU2852 + 8447 0066 0028 cmp r0, #0 + 8448 0068 EFD1 bne .L619 +4418:Middlewares/Third_Party/FatFs/src/ff.c **** } while (++clst < fs->n_fatent); + 8449 .loc 1 4418 21 is_stmt 1 discriminator 1 view .LVU2853 +4418:Middlewares/Third_Party/FatFs/src/ff.c **** } while (++clst < fs->n_fatent); + 8450 .loc 1 4418 26 is_stmt 0 discriminator 1 view .LVU2854 + 8451 006a 0137 adds r7, r7, #1 + 8452 .LVL972: +4418:Middlewares/Third_Party/FatFs/src/ff.c **** } while (++clst < fs->n_fatent); + 8453 .loc 1 4418 26 discriminator 1 view .LVU2855 + 8454 006c EDE7 b .L619 + 8455 .LVL973: + 8456 .L631: +4444:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 8457 .loc 1 4444 8 is_stmt 1 view .LVU2856 +4444:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 8458 .loc 1 4444 14 is_stmt 0 view .LVU2857 + 8459 006e 0AF1010B add fp, r10, #1 + 8460 .LVL974: +4444:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 8461 .loc 1 4444 14 view .LVU2858 + 8462 0072 5146 mov r1, r10 + 8463 0074 0798 ldr r0, [sp, #28] + ARM GAS /tmp/cc2SVLkL.s page 297 + + + 8464 0076 FFF7FEFF bl move_window + 8465 .LVL975: +4445:Middlewares/Third_Party/FatFs/src/ff.c **** p = fs->win; + 8466 .loc 1 4445 8 is_stmt 1 view .LVU2859 +4445:Middlewares/Third_Party/FatFs/src/ff.c **** p = fs->win; + 8467 .loc 1 4445 11 is_stmt 0 view .LVU2860 + 8468 007a 8146 mov r9, r0 + 8469 007c 00BB cbnz r0, .L618 +4446:Middlewares/Third_Party/FatFs/src/ff.c **** i = SS(fs); + 8470 .loc 1 4446 8 is_stmt 1 view .LVU2861 +4446:Middlewares/Third_Party/FatFs/src/ff.c **** i = SS(fs); + 8471 .loc 1 4446 14 is_stmt 0 view .LVU2862 + 8472 007e 079B ldr r3, [sp, #28] +4446:Middlewares/Third_Party/FatFs/src/ff.c **** i = SS(fs); + 8473 .loc 1 4446 10 view .LVU2863 + 8474 0080 03F13404 add r4, r3, #52 + 8475 .LVL976: +4447:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8476 .loc 1 4447 8 is_stmt 1 view .LVU2864 +4447:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8477 .loc 1 4447 12 is_stmt 0 view .LVU2865 + 8478 0084 9E89 ldrh r6, [r3, #12] + 8479 .LVL977: +4444:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 8480 .loc 1 4444 14 view .LVU2866 + 8481 0086 DA46 mov r10, fp + 8482 0088 0DE0 b .L621 + 8483 .LVL978: + 8484 .L632: +4450:Middlewares/Third_Party/FatFs/src/ff.c **** p += 2; i -= 2; + 8485 .loc 1 4450 8 is_stmt 1 view .LVU2867 +4450:Middlewares/Third_Party/FatFs/src/ff.c **** p += 2; i -= 2; + 8486 .loc 1 4450 12 is_stmt 0 view .LVU2868 + 8487 008a 2046 mov r0, r4 + 8488 008c FFF7FEFF bl ld_word + 8489 .LVL979: +4450:Middlewares/Third_Party/FatFs/src/ff.c **** p += 2; i -= 2; + 8490 .loc 1 4450 11 discriminator 1 view .LVU2869 + 8491 0090 00B9 cbnz r0, .L623 +4450:Middlewares/Third_Party/FatFs/src/ff.c **** p += 2; i -= 2; + 8492 .loc 1 4450 29 is_stmt 1 discriminator 1 view .LVU2870 +4450:Middlewares/Third_Party/FatFs/src/ff.c **** p += 2; i -= 2; + 8493 .loc 1 4450 34 is_stmt 0 discriminator 1 view .LVU2871 + 8494 0092 0137 adds r7, r7, #1 + 8495 .LVL980: + 8496 .L623: +4451:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 8497 .loc 1 4451 8 is_stmt 1 view .LVU2872 +4451:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 8498 .loc 1 4451 10 is_stmt 0 view .LVU2873 + 8499 0094 0234 adds r4, r4, #2 + 8500 .LVL981: +4451:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 8501 .loc 1 4451 16 is_stmt 1 view .LVU2874 +4451:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 8502 .loc 1 4451 18 is_stmt 0 view .LVU2875 + 8503 0096 023E subs r6, r6, #2 + ARM GAS /tmp/cc2SVLkL.s page 298 + + + 8504 .LVL982: +4451:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 8505 .loc 1 4451 18 view .LVU2876 + 8506 0098 01E0 b .L624 + 8507 .L625: +4454:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8508 .loc 1 4454 8 is_stmt 1 view .LVU2877 +4454:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8509 .loc 1 4454 10 is_stmt 0 view .LVU2878 + 8510 009a 0434 adds r4, r4, #4 + 8511 .LVL983: +4454:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8512 .loc 1 4454 16 is_stmt 1 view .LVU2879 +4454:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8513 .loc 1 4454 18 is_stmt 0 view .LVU2880 + 8514 009c 043E subs r6, r6, #4 + 8515 .LVL984: + 8516 .L624: +4456:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8517 .loc 1 4456 15 is_stmt 1 view .LVU2881 +4456:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8518 .loc 1 4456 15 is_stmt 0 view .LVU2882 + 8519 009e 013D subs r5, r5, #1 + 8520 .LVL985: +4456:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8521 .loc 1 4456 15 view .LVU2883 + 8522 00a0 0ED0 beq .L618 + 8523 .LVL986: + 8524 .L626: +4442:Middlewares/Third_Party/FatFs/src/ff.c **** if (i == 0) { + 8525 .loc 1 4442 6 is_stmt 1 view .LVU2884 +4443:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, sect++); + 8526 .loc 1 4443 7 view .LVU2885 +4443:Middlewares/Third_Party/FatFs/src/ff.c **** res = move_window(fs, sect++); + 8527 .loc 1 4443 10 is_stmt 0 view .LVU2886 + 8528 00a2 002E cmp r6, #0 + 8529 00a4 E3D0 beq .L631 + 8530 .LVL987: + 8531 .L621: +4449:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_word(p) == 0) nfree++; + 8532 .loc 1 4449 7 is_stmt 1 view .LVU2887 +4449:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_word(p) == 0) nfree++; + 8533 .loc 1 4449 13 is_stmt 0 view .LVU2888 + 8534 00a6 079B ldr r3, [sp, #28] + 8535 00a8 1B78 ldrb r3, [r3] @ zero_extendqisi2 +4449:Middlewares/Third_Party/FatFs/src/ff.c **** if (ld_word(p) == 0) nfree++; + 8536 .loc 1 4449 10 view .LVU2889 + 8537 00aa 022B cmp r3, #2 + 8538 00ac EDD0 beq .L632 +4453:Middlewares/Third_Party/FatFs/src/ff.c **** p += 4; i -= 4; + 8539 .loc 1 4453 8 is_stmt 1 view .LVU2890 +4453:Middlewares/Third_Party/FatFs/src/ff.c **** p += 4; i -= 4; + 8540 .loc 1 4453 13 is_stmt 0 view .LVU2891 + 8541 00ae 2046 mov r0, r4 + 8542 00b0 FFF7FEFF bl ld_dword + 8543 .LVL988: +4453:Middlewares/Third_Party/FatFs/src/ff.c **** p += 4; i -= 4; + ARM GAS /tmp/cc2SVLkL.s page 299 + + + 8544 .loc 1 4453 11 discriminator 1 view .LVU2892 + 8545 00b4 30F07043 bics r3, r0, #-268435456 + 8546 00b8 EFD1 bne .L625 +4453:Middlewares/Third_Party/FatFs/src/ff.c **** p += 4; i -= 4; + 8547 .loc 1 4453 45 is_stmt 1 discriminator 1 view .LVU2893 +4453:Middlewares/Third_Party/FatFs/src/ff.c **** p += 4; i -= 4; + 8548 .loc 1 4453 50 is_stmt 0 discriminator 1 view .LVU2894 + 8549 00ba 0137 adds r7, r7, #1 + 8550 .LVL989: +4453:Middlewares/Third_Party/FatFs/src/ff.c **** p += 4; i -= 4; + 8551 .loc 1 4453 50 discriminator 1 view .LVU2895 + 8552 00bc EDE7 b .L625 + 8553 .LVL990: + 8554 .L627: +4416:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat == 1) { res = FR_INT_ERR; break; } + 8555 .loc 1 4416 36 discriminator 1 view .LVU2896 + 8556 00be B146 mov r9, r6 + 8557 .LVL991: + 8558 .L618: +4459:Middlewares/Third_Party/FatFs/src/ff.c **** fs->free_clst = nfree; /* Now free_clst is valid */ + 8559 .loc 1 4459 4 is_stmt 1 view .LVU2897 +4459:Middlewares/Third_Party/FatFs/src/ff.c **** fs->free_clst = nfree; /* Now free_clst is valid */ + 8560 .loc 1 4459 11 is_stmt 0 view .LVU2898 + 8561 00c0 C8F80070 str r7, [r8] +4460:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag |= 1; /* FSInfo is to be updated */ + 8562 .loc 1 4460 4 is_stmt 1 view .LVU2899 +4460:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag |= 1; /* FSInfo is to be updated */ + 8563 .loc 1 4460 6 is_stmt 0 view .LVU2900 + 8564 00c4 079B ldr r3, [sp, #28] +4460:Middlewares/Third_Party/FatFs/src/ff.c **** fs->fsi_flag |= 1; /* FSInfo is to be updated */ + 8565 .loc 1 4460 18 view .LVU2901 + 8566 00c6 5F61 str r7, [r3, #20] +4461:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8567 .loc 1 4461 4 is_stmt 1 view .LVU2902 +4461:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8568 .loc 1 4461 6 is_stmt 0 view .LVU2903 + 8569 00c8 1A79 ldrb r2, [r3, #4] @ zero_extendqisi2 +4461:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8570 .loc 1 4461 17 view .LVU2904 + 8571 00ca 42F00102 orr r2, r2, #1 + 8572 00ce 1A71 strb r2, [r3, #4] + 8573 .LVL992: + 8574 .L615: +4465:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8575 .loc 1 4465 2 is_stmt 1 view .LVU2905 +4466:Middlewares/Third_Party/FatFs/src/ff.c **** + 8576 .loc 1 4466 1 is_stmt 0 view .LVU2906 + 8577 00d0 4846 mov r0, r9 + 8578 00d2 09B0 add sp, sp, #36 + 8579 .LCFI93: + 8580 .cfi_remember_state + 8581 .cfi_def_cfa_offset 36 + 8582 @ sp needed + 8583 00d4 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 8584 .LVL993: + 8585 .L628: + 8586 .LCFI94: + ARM GAS /tmp/cc2SVLkL.s page 300 + + + 8587 .cfi_restore_state +4417:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat == 0) nfree++; + 8588 .loc 1 4417 27 discriminator 1 view .LVU2907 + 8589 00d8 4FF00209 mov r9, #2 + 8590 .LVL994: +4417:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat == 0) nfree++; + 8591 .loc 1 4417 27 discriminator 1 view .LVU2908 + 8592 00dc F0E7 b .L618 + 8593 .cfi_endproc + 8594 .LFE1232: + 8596 .section .text.f_truncate,"ax",%progbits + 8597 .align 1 + 8598 .global f_truncate + 8599 .syntax unified + 8600 .thumb + 8601 .thumb_func + 8603 f_truncate: + 8604 .LVL995: + 8605 .LFB1233: +4478:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 8606 .loc 1 4478 1 is_stmt 1 view -0 + 8607 .cfi_startproc + 8608 @ args = 0, pretend = 0, frame = 8 + 8609 @ frame_needed = 0, uses_anonymous_args = 0 +4478:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 8610 .loc 1 4478 1 is_stmt 0 view .LVU2910 + 8611 0000 30B5 push {r4, r5, lr} + 8612 .LCFI95: + 8613 .cfi_def_cfa_offset 12 + 8614 .cfi_offset 4, -12 + 8615 .cfi_offset 5, -8 + 8616 .cfi_offset 14, -4 + 8617 0002 83B0 sub sp, sp, #12 + 8618 .LCFI96: + 8619 .cfi_def_cfa_offset 24 + 8620 0004 0446 mov r4, r0 +4479:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; + 8621 .loc 1 4479 2 is_stmt 1 view .LVU2911 +4480:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD ncl; + 8622 .loc 1 4480 2 view .LVU2912 +4481:Middlewares/Third_Party/FatFs/src/ff.c **** + 8623 .loc 1 4481 2 view .LVU2913 +4484:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); + 8624 .loc 1 4484 2 view .LVU2914 +4484:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); + 8625 .loc 1 4484 8 is_stmt 0 view .LVU2915 + 8626 0006 01A9 add r1, sp, #4 + 8627 0008 FFF7FEFF bl validate + 8628 .LVL996: +4485:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + 8629 .loc 1 4485 2 is_stmt 1 view .LVU2916 +4485:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + 8630 .loc 1 4485 5 is_stmt 0 view .LVU2917 + 8631 000c 0546 mov r5, r0 + 8632 000e 0028 cmp r0, #0 + 8633 0010 49D1 bne .L636 +4485:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + ARM GAS /tmp/cc2SVLkL.s page 301 + + + 8634 .loc 1 4485 27 discriminator 2 view .LVU2918 + 8635 0012 657D ldrb r5, [r4, #21] @ zero_extendqisi2 + 8636 .LVL997: +4485:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */ + 8637 .loc 1 4485 19 discriminator 2 view .LVU2919 + 8638 0014 002D cmp r5, #0 + 8639 0016 46D1 bne .L636 +4486:Middlewares/Third_Party/FatFs/src/ff.c **** + 8640 .loc 1 4486 2 is_stmt 1 view .LVU2920 +4486:Middlewares/Third_Party/FatFs/src/ff.c **** + 8641 .loc 1 4486 10 is_stmt 0 view .LVU2921 + 8642 0018 237D ldrb r3, [r4, #20] @ zero_extendqisi2 +4486:Middlewares/Third_Party/FatFs/src/ff.c **** + 8643 .loc 1 4486 5 view .LVU2922 + 8644 001a 13F0020F tst r3, #2 + 8645 001e 41D0 beq .L641 +4488:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ + 8646 .loc 1 4488 2 is_stmt 1 view .LVU2923 +4488:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ + 8647 .loc 1 4488 8 is_stmt 0 view .LVU2924 + 8648 0020 A369 ldr r3, [r4, #24] +4488:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ + 8649 .loc 1 4488 24 view .LVU2925 + 8650 0022 E268 ldr r2, [r4, #12] +4488:Middlewares/Third_Party/FatFs/src/ff.c **** if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ + 8651 .loc 1 4488 5 view .LVU2926 + 8652 0024 9342 cmp r3, r2 + 8653 0026 3ED2 bcs .L636 +4489:Middlewares/Third_Party/FatFs/src/ff.c **** res = remove_chain(&fp->obj, fp->obj.sclust, 0); + 8654 .loc 1 4489 3 is_stmt 1 view .LVU2927 +4489:Middlewares/Third_Party/FatFs/src/ff.c **** res = remove_chain(&fp->obj, fp->obj.sclust, 0); + 8655 .loc 1 4489 6 is_stmt 0 view .LVU2928 + 8656 0028 FBB9 cbnz r3, .L637 +4490:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.sclust = 0; + 8657 .loc 1 4490 4 is_stmt 1 view .LVU2929 +4490:Middlewares/Third_Party/FatFs/src/ff.c **** fp->obj.sclust = 0; + 8658 .loc 1 4490 10 is_stmt 0 view .LVU2930 + 8659 002a 0022 movs r2, #0 + 8660 002c A168 ldr r1, [r4, #8] + 8661 002e 2046 mov r0, r4 + 8662 0030 FFF7FEFF bl remove_chain + 8663 .LVL998: + 8664 0034 0546 mov r5, r0 + 8665 .LVL999: +4491:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* When truncate a part of the file, remove remaining clusters */ + 8666 .loc 1 4491 4 is_stmt 1 view .LVU2931 +4491:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* When truncate a part of the file, remove remaining clusters */ + 8667 .loc 1 4491 19 is_stmt 0 view .LVU2932 + 8668 0036 0023 movs r3, #0 + 8669 0038 A360 str r3, [r4, #8] + 8670 .LVL1000: + 8671 .L638: +4501:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag |= FA_MODIFIED; + 8672 .loc 1 4501 3 is_stmt 1 view .LVU2933 +4501:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag |= FA_MODIFIED; + 8673 .loc 1 4501 23 is_stmt 0 view .LVU2934 + 8674 003a A369 ldr r3, [r4, #24] + ARM GAS /tmp/cc2SVLkL.s page 302 + + +4501:Middlewares/Third_Party/FatFs/src/ff.c **** fp->flag |= FA_MODIFIED; + 8675 .loc 1 4501 19 view .LVU2935 + 8676 003c E360 str r3, [r4, #12] +4502:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 8677 .loc 1 4502 3 is_stmt 1 view .LVU2936 +4502:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 8678 .loc 1 4502 5 is_stmt 0 view .LVU2937 + 8679 003e 237D ldrb r3, [r4, #20] @ zero_extendqisi2 +4502:Middlewares/Third_Party/FatFs/src/ff.c **** #if !_FS_TINY + 8680 .loc 1 4502 12 view .LVU2938 + 8681 0040 43F04003 orr r3, r3, #64 + 8682 0044 2375 strb r3, [r4, #20] +4504:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) { + 8683 .loc 1 4504 3 is_stmt 1 view .LVU2939 +4504:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) { + 8684 .loc 1 4504 6 is_stmt 0 view .LVU2940 + 8685 0046 5DBB cbnz r5, .L640 +4504:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) { + 8686 .loc 1 4504 20 discriminator 1 view .LVU2941 + 8687 0048 13F0800F tst r3, #128 + 8688 004c 2BD0 beq .L636 +4505:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DISK_ERR; + 8689 .loc 1 4505 4 is_stmt 1 view .LVU2942 +4505:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DISK_ERR; + 8690 .loc 1 4505 8 is_stmt 0 view .LVU2943 + 8691 004e 0123 movs r3, #1 + 8692 0050 226A ldr r2, [r4, #32] + 8693 0052 04F13001 add r1, r4, #48 + 8694 0056 0198 ldr r0, [sp, #4] + 8695 0058 4078 ldrb r0, [r0, #1] @ zero_extendqisi2 + 8696 005a FFF7FEFF bl disk_write + 8697 .LVL1001: +4505:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DISK_ERR; + 8698 .loc 1 4505 7 discriminator 1 view .LVU2944 + 8699 005e F0B9 cbnz r0, .L644 +4508:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8700 .loc 1 4508 5 is_stmt 1 view .LVU2945 +4508:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8701 .loc 1 4508 7 is_stmt 0 view .LVU2946 + 8702 0060 237D ldrb r3, [r4, #20] @ zero_extendqisi2 +4508:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8703 .loc 1 4508 14 view .LVU2947 + 8704 0062 03F07F03 and r3, r3, #127 + 8705 0066 2375 strb r3, [r4, #20] + 8706 0068 1DE0 b .L636 + 8707 .L637: +4493:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; + 8708 .loc 1 4493 4 is_stmt 1 view .LVU2948 +4493:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; + 8709 .loc 1 4493 10 is_stmt 0 view .LVU2949 + 8710 006a E169 ldr r1, [r4, #28] + 8711 006c 2046 mov r0, r4 + 8712 006e FFF7FEFF bl get_fat + 8713 .LVL1002: +4494:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; + 8714 .loc 1 4494 4 is_stmt 1 view .LVU2950 +4495:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl == 1) res = FR_INT_ERR; + ARM GAS /tmp/cc2SVLkL.s page 303 + + + 8715 .loc 1 4495 4 view .LVU2951 +4495:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl == 1) res = FR_INT_ERR; + 8716 .loc 1 4495 7 is_stmt 0 view .LVU2952 + 8717 0072 B0F1FF3F cmp r0, #-1 + 8718 0076 0ED0 beq .L642 +4496:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && ncl < fs->n_fatent) { + 8719 .loc 1 4496 4 is_stmt 1 view .LVU2953 +4496:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && ncl < fs->n_fatent) { + 8720 .loc 1 4496 7 is_stmt 0 view .LVU2954 + 8721 0078 0128 cmp r0, #1 + 8722 007a 0ED0 beq .L646 + 8723 .L639: + 8724 .LVL1003: +4497:Middlewares/Third_Party/FatFs/src/ff.c **** res = remove_chain(&fp->obj, ncl, fp->clust); + 8725 .loc 1 4497 4 is_stmt 1 view .LVU2955 +4497:Middlewares/Third_Party/FatFs/src/ff.c **** res = remove_chain(&fp->obj, ncl, fp->clust); + 8726 .loc 1 4497 7 is_stmt 0 view .LVU2956 + 8727 007c 002D cmp r5, #0 + 8728 007e DCD1 bne .L638 +4497:Middlewares/Third_Party/FatFs/src/ff.c **** res = remove_chain(&fp->obj, ncl, fp->clust); + 8729 .loc 1 4497 32 discriminator 1 view .LVU2957 + 8730 0080 019B ldr r3, [sp, #4] + 8731 0082 9B69 ldr r3, [r3, #24] +4497:Middlewares/Third_Party/FatFs/src/ff.c **** res = remove_chain(&fp->obj, ncl, fp->clust); + 8732 .loc 1 4497 21 discriminator 1 view .LVU2958 + 8733 0084 8342 cmp r3, r0 + 8734 0086 D8D9 bls .L638 +4498:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8735 .loc 1 4498 5 is_stmt 1 view .LVU2959 +4498:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8736 .loc 1 4498 11 is_stmt 0 view .LVU2960 + 8737 0088 E269 ldr r2, [r4, #28] + 8738 008a 0146 mov r1, r0 + 8739 008c 2046 mov r0, r4 + 8740 .LVL1004: +4498:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8741 .loc 1 4498 11 view .LVU2961 + 8742 008e FFF7FEFF bl remove_chain + 8743 .LVL1005: +4498:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8744 .loc 1 4498 11 view .LVU2962 + 8745 0092 0546 mov r5, r0 + 8746 .LVL1006: +4498:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8747 .loc 1 4498 11 view .LVU2963 + 8748 0094 D1E7 b .L638 + 8749 .LVL1007: + 8750 .L642: +4495:Middlewares/Third_Party/FatFs/src/ff.c **** if (ncl == 1) res = FR_INT_ERR; + 8751 .loc 1 4495 31 discriminator 1 view .LVU2964 + 8752 0096 0125 movs r5, #1 + 8753 0098 F0E7 b .L639 + 8754 .L646: +4496:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && ncl < fs->n_fatent) { + 8755 .loc 1 4496 22 discriminator 1 view .LVU2965 + 8756 009a 0225 movs r5, #2 + 8757 009c CDE7 b .L638 + ARM GAS /tmp/cc2SVLkL.s page 304 + + + 8758 .LVL1008: + 8759 .L644: +4506:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 8760 .loc 1 4506 9 view .LVU2966 + 8761 009e 0125 movs r5, #1 + 8762 .LVL1009: + 8763 .L640: +4512:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8764 .loc 1 4512 21 is_stmt 1 discriminator 1 view .LVU2967 + 8765 00a0 6575 strb r5, [r4, #21] +4512:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8766 .loc 1 4512 21 discriminator 1 view .LVU2968 +4512:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8767 .loc 1 4512 21 is_stmt 0 view .LVU2969 + 8768 00a2 00E0 b .L636 + 8769 .LVL1010: + 8770 .L641: +4486:Middlewares/Third_Party/FatFs/src/ff.c **** + 8771 .loc 1 4486 30 discriminator 1 view .LVU2970 + 8772 00a4 0725 movs r5, #7 + 8773 .LVL1011: + 8774 .L636: +4516:Middlewares/Third_Party/FatFs/src/ff.c **** + 8775 .loc 1 4516 1 view .LVU2971 + 8776 00a6 2846 mov r0, r5 + 8777 00a8 03B0 add sp, sp, #12 + 8778 .LCFI97: + 8779 .cfi_def_cfa_offset 12 + 8780 @ sp needed + 8781 00aa 30BD pop {r4, r5, pc} +4516:Middlewares/Third_Party/FatFs/src/ff.c **** + 8782 .loc 1 4516 1 view .LVU2972 + 8783 .cfi_endproc + 8784 .LFE1233: + 8786 .section .text.f_unlink,"ax",%progbits + 8787 .align 1 + 8788 .global f_unlink + 8789 .syntax unified + 8790 .thumb + 8791 .thumb_func + 8793 f_unlink: + 8794 .LVL1012: + 8795 .LFB1234: +4528:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 8796 .loc 1 4528 1 is_stmt 1 view -0 + 8797 .cfi_startproc + 8798 @ args = 0, pretend = 0, frame = 112 + 8799 @ frame_needed = 0, uses_anonymous_args = 0 +4528:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 8800 .loc 1 4528 1 is_stmt 0 view .LVU2974 + 8801 0000 F0B5 push {r4, r5, r6, r7, lr} + 8802 .LCFI98: + 8803 .cfi_def_cfa_offset 20 + 8804 .cfi_offset 4, -20 + 8805 .cfi_offset 5, -16 + 8806 .cfi_offset 6, -12 + 8807 .cfi_offset 7, -8 + ARM GAS /tmp/cc2SVLkL.s page 305 + + + 8808 .cfi_offset 14, -4 + 8809 0002 9DB0 sub sp, sp, #116 + 8810 .LCFI99: + 8811 .cfi_def_cfa_offset 136 + 8812 0004 0190 str r0, [sp, #4] +4529:Middlewares/Third_Party/FatFs/src/ff.c **** DIR dj, sdj; + 8813 .loc 1 4529 2 is_stmt 1 view .LVU2975 +4530:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD dclst = 0; + 8814 .loc 1 4530 2 view .LVU2976 +4531:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; + 8815 .loc 1 4531 2 view .LVU2977 + 8816 .LVL1013: +4532:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 8817 .loc 1 4532 2 view .LVU2978 +4540:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.fs = fs; + 8818 .loc 1 4540 2 view .LVU2979 +4540:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.fs = fs; + 8819 .loc 1 4540 8 is_stmt 0 view .LVU2980 + 8820 0006 0222 movs r2, #2 + 8821 0008 03A9 add r1, sp, #12 + 8822 000a 01A8 add r0, sp, #4 + 8823 .LVL1014: +4540:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.fs = fs; + 8824 .loc 1 4540 8 view .LVU2981 + 8825 000c FFF7FEFF bl find_volume + 8826 .LVL1015: +4541:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 8827 .loc 1 4541 2 is_stmt 1 view .LVU2982 +4541:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 8828 .loc 1 4541 12 is_stmt 0 view .LVU2983 + 8829 0010 039B ldr r3, [sp, #12] + 8830 0012 1093 str r3, [sp, #64] +4542:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); + 8831 .loc 1 4542 2 is_stmt 1 view .LVU2984 +4542:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); + 8832 .loc 1 4542 5 is_stmt 0 view .LVU2985 + 8833 0014 0446 mov r4, r0 + 8834 0016 10B1 cbz r0, .L656 + 8835 .LVL1016: + 8836 .L648: +4607:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8837 .loc 1 4607 16 is_stmt 1 view .LVU2986 +4610:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8838 .loc 1 4610 2 view .LVU2987 +4611:Middlewares/Third_Party/FatFs/src/ff.c **** + 8839 .loc 1 4611 1 is_stmt 0 view .LVU2988 + 8840 0018 2046 mov r0, r4 + 8841 001a 1DB0 add sp, sp, #116 + 8842 .LCFI100: + 8843 .cfi_remember_state + 8844 .cfi_def_cfa_offset 20 + 8845 @ sp needed + 8846 001c F0BD pop {r4, r5, r6, r7, pc} + 8847 .LVL1017: + 8848 .L656: + 8849 .LCFI101: + 8850 .cfi_restore_state + ARM GAS /tmp/cc2SVLkL.s page 306 + + +4543:Middlewares/Third_Party/FatFs/src/ff.c **** res = follow_path(&dj, path); /* Follow the file path */ + 8851 .loc 1 4543 18 is_stmt 1 view .LVU2989 +4544:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) { + 8852 .loc 1 4544 3 view .LVU2990 +4544:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) { + 8853 .loc 1 4544 9 is_stmt 0 view .LVU2991 + 8854 001e 0199 ldr r1, [sp, #4] + 8855 0020 10A8 add r0, sp, #64 + 8856 .LVL1018: +4544:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) { + 8857 .loc 1 4544 9 view .LVU2992 + 8858 0022 FFF7FEFF bl follow_path + 8859 .LVL1019: +4545:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INVALID_NAME; /* Cannot remove dot entry */ + 8860 .loc 1 4545 3 is_stmt 1 view .LVU2993 +4549:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 8861 .loc 1 4549 3 view .LVU2994 +4549:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 8862 .loc 1 4549 6 is_stmt 0 view .LVU2995 + 8863 0026 0446 mov r4, r0 + 8864 0028 0028 cmp r0, #0 + 8865 002a F5D1 bne .L648 +4549:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 8866 .loc 1 4549 21 is_stmt 1 discriminator 1 view .LVU2996 +4549:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 8867 .loc 1 4549 27 is_stmt 0 discriminator 1 view .LVU2997 + 8868 002c 0221 movs r1, #2 + 8869 002e 10A8 add r0, sp, #64 + 8870 .LVL1020: +4549:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 8871 .loc 1 4549 27 discriminator 1 view .LVU2998 + 8872 0030 FFF7FEFF bl chk_lock + 8873 .LVL1021: +4551:Middlewares/Third_Party/FatFs/src/ff.c **** if (dj.fn[NSFLAG] & NS_NONAME) { + 8874 .loc 1 4551 3 is_stmt 1 view .LVU2999 +4551:Middlewares/Third_Party/FatFs/src/ff.c **** if (dj.fn[NSFLAG] & NS_NONAME) { + 8875 .loc 1 4551 6 is_stmt 0 view .LVU3000 + 8876 0034 0446 mov r4, r0 + 8877 0036 0028 cmp r0, #0 + 8878 0038 EED1 bne .L648 +4552:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INVALID_NAME; /* Cannot remove the origin directory */ + 8879 .loc 1 4552 4 is_stmt 1 view .LVU3001 +4552:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INVALID_NAME; /* Cannot remove the origin directory */ + 8880 .loc 1 4552 8 is_stmt 0 view .LVU3002 + 8881 003a 9DF96F30 ldrsb r3, [sp, #111] +4552:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INVALID_NAME; /* Cannot remove the origin directory */ + 8882 .loc 1 4552 7 view .LVU3003 + 8883 003e 002B cmp r3, #0 + 8884 0040 3CDB blt .L652 +4555:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DENIED; /* Cannot remove R/O object */ + 8885 .loc 1 4555 5 is_stmt 1 view .LVU3004 +4555:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DENIED; /* Cannot remove R/O object */ + 8886 .loc 1 4555 15 is_stmt 0 view .LVU3005 + 8887 0042 9DF84650 ldrb r5, [sp, #70] @ zero_extendqisi2 +4555:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_DENIED; /* Cannot remove R/O object */ + 8888 .loc 1 4555 8 view .LVU3006 + 8889 0046 15F0010F tst r5, #1 + ARM GAS /tmp/cc2SVLkL.s page 307 + + + 8890 004a 39D1 bne .L653 + 8891 .LVL1022: +4559:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 8892 .loc 1 4559 4 is_stmt 1 view .LVU3007 +4569:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8893 .loc 1 4569 6 view .LVU3008 +4569:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8894 .loc 1 4569 14 is_stmt 0 view .LVU3009 + 8895 004c 039F ldr r7, [sp, #12] + 8896 004e 1899 ldr r1, [sp, #96] + 8897 0050 3846 mov r0, r7 + 8898 0052 FFF7FEFF bl ld_clust + 8899 .LVL1023: + 8900 0056 0646 mov r6, r0 + 8901 .LVL1024: +4571:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0 + 8902 .loc 1 4571 5 is_stmt 1 view .LVU3010 +4571:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_RPATH != 0 + 8903 .loc 1 4571 8 is_stmt 0 view .LVU3011 + 8904 0058 15F0100F tst r5, #16 + 8905 005c 13D1 bne .L657 + 8906 .LVL1025: + 8907 .L649: +4595:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_remove(&dj); /* Remove the directory entry */ + 8908 .loc 1 4595 4 is_stmt 1 view .LVU3012 +4595:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_remove(&dj); /* Remove the directory entry */ + 8909 .loc 1 4595 7 is_stmt 0 view .LVU3013 + 8910 005e 002C cmp r4, #0 + 8911 0060 DAD1 bne .L648 + 8912 .LVL1026: + 8913 .L650: +4596:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && dclst) { /* Remove the cluster chain if exist */ + 8914 .loc 1 4596 5 is_stmt 1 view .LVU3014 +4596:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && dclst) { /* Remove the cluster chain if exist */ + 8915 .loc 1 4596 11 is_stmt 0 view .LVU3015 + 8916 0062 10A8 add r0, sp, #64 + 8917 0064 FFF7FEFF bl dir_remove + 8918 .LVL1027: +4597:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 8919 .loc 1 4597 5 is_stmt 1 view .LVU3016 +4597:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 8920 .loc 1 4597 13 is_stmt 0 view .LVU3017 + 8921 0068 0446 mov r4, r0 +4597:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 8922 .loc 1 4597 22 view .LVU3018 + 8923 006a B0FA80F0 clz r0, r0 + 8924 .LVL1028: +4597:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 8925 .loc 1 4597 22 view .LVU3019 + 8926 006e 4009 lsrs r0, r0, #5 + 8927 0070 002E cmp r6, #0 + 8928 0072 08BF it eq + 8929 0074 0020 moveq r0, #0 +4597:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 8930 .loc 1 4597 8 view .LVU3020 + 8931 0076 D0B9 cbnz r0, .L658 + 8932 .LVL1029: + ARM GAS /tmp/cc2SVLkL.s page 308 + + + 8933 .L651: +4604:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8934 .loc 1 4604 5 is_stmt 1 view .LVU3021 +4604:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8935 .loc 1 4604 8 is_stmt 0 view .LVU3022 + 8936 0078 002C cmp r4, #0 + 8937 007a CDD1 bne .L648 +4604:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8938 .loc 1 4604 23 is_stmt 1 discriminator 1 view .LVU3023 +4604:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8939 .loc 1 4604 29 is_stmt 0 discriminator 1 view .LVU3024 + 8940 007c 0398 ldr r0, [sp, #12] + 8941 007e FFF7FEFF bl sync_fs + 8942 .LVL1030: + 8943 0082 0446 mov r4, r0 + 8944 .LVL1031: +4604:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8945 .loc 1 4604 29 discriminator 1 view .LVU3025 + 8946 0084 C8E7 b .L648 + 8947 .LVL1032: + 8948 .L657: +4578:Middlewares/Third_Party/FatFs/src/ff.c **** sdj.obj.sclust = dclst; + 8949 .loc 1 4578 7 is_stmt 1 view .LVU3026 +4578:Middlewares/Third_Party/FatFs/src/ff.c **** sdj.obj.sclust = dclst; + 8950 .loc 1 4578 18 is_stmt 0 view .LVU3027 + 8951 0086 0497 str r7, [sp, #16] +4579:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 8952 .loc 1 4579 7 is_stmt 1 view .LVU3028 +4579:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 8953 .loc 1 4579 22 is_stmt 0 view .LVU3029 + 8954 0088 0690 str r0, [sp, #24] +4586:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 8955 .loc 1 4586 7 is_stmt 1 view .LVU3030 +4586:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 8956 .loc 1 4586 13 is_stmt 0 view .LVU3031 + 8957 008a 0021 movs r1, #0 + 8958 008c 04A8 add r0, sp, #16 + 8959 .LVL1033: +4586:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 8960 .loc 1 4586 13 view .LVU3032 + 8961 008e FFF7FEFF bl dir_sdi + 8962 .LVL1034: +4587:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_read(&sdj, 0); /* Read an item */ + 8963 .loc 1 4587 7 is_stmt 1 view .LVU3033 +4587:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_read(&sdj, 0); /* Read an item */ + 8964 .loc 1 4587 10 is_stmt 0 view .LVU3034 + 8965 0092 0446 mov r4, r0 + 8966 0094 0028 cmp r0, #0 + 8967 0096 BFD1 bne .L648 +4588:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) res = FR_DENIED; /* Not empty? */ + 8968 .loc 1 4588 8 is_stmt 1 view .LVU3035 +4588:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) res = FR_DENIED; /* Not empty? */ + 8969 .loc 1 4588 14 is_stmt 0 view .LVU3036 + 8970 0098 0021 movs r1, #0 + 8971 009a 04A8 add r0, sp, #16 + 8972 .LVL1035: +4588:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) res = FR_DENIED; /* Not empty? */ + ARM GAS /tmp/cc2SVLkL.s page 309 + + + 8973 .loc 1 4588 14 view .LVU3037 + 8974 009c FFF7FEFF bl dir_read + 8975 .LVL1036: +4589:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) res = FR_OK; /* Empty? */ + 8976 .loc 1 4589 8 is_stmt 1 view .LVU3038 +4589:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) res = FR_OK; /* Empty? */ + 8977 .loc 1 4589 11 is_stmt 0 view .LVU3039 + 8978 00a0 0446 mov r4, r0 + 8979 00a2 10B1 cbz r0, .L654 +4590:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8980 .loc 1 4590 8 is_stmt 1 view .LVU3040 +4590:Middlewares/Third_Party/FatFs/src/ff.c **** } + 8981 .loc 1 4590 11 is_stmt 0 view .LVU3041 + 8982 00a4 0428 cmp r0, #4 + 8983 00a6 DAD1 bne .L649 + 8984 00a8 DBE7 b .L650 + 8985 .L654: +4589:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_NO_FILE) res = FR_OK; /* Empty? */ + 8986 .loc 1 4589 30 discriminator 1 view .LVU3042 + 8987 00aa 0724 movs r4, #7 + 8988 00ac D7E7 b .L649 + 8989 .LVL1037: + 8990 .L658: +4601:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 8991 .loc 1 4601 6 is_stmt 1 view .LVU3043 +4601:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 8992 .loc 1 4601 12 is_stmt 0 view .LVU3044 + 8993 00ae 0022 movs r2, #0 + 8994 00b0 3146 mov r1, r6 + 8995 00b2 10A8 add r0, sp, #64 + 8996 00b4 FFF7FEFF bl remove_chain + 8997 .LVL1038: + 8998 00b8 0446 mov r4, r0 + 8999 .LVL1039: +4601:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 9000 .loc 1 4601 12 view .LVU3045 + 9001 00ba DDE7 b .L651 + 9002 .LVL1040: + 9003 .L652: +4553:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 9004 .loc 1 4553 9 view .LVU3046 + 9005 00bc 0624 movs r4, #6 + 9006 00be ABE7 b .L648 + 9007 .L653: +4556:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9008 .loc 1 4556 10 view .LVU3047 + 9009 00c0 0724 movs r4, #7 + 9010 00c2 A9E7 b .L648 + 9011 .cfi_endproc + 9012 .LFE1234: + 9014 .section .text.f_mkdir,"ax",%progbits + 9015 .align 1 + 9016 .global f_mkdir + 9017 .syntax unified + 9018 .thumb + 9019 .thumb_func + 9021 f_mkdir: + ARM GAS /tmp/cc2SVLkL.s page 310 + + + 9022 .LVL1041: + 9023 .LFB1235: +4623:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 9024 .loc 1 4623 1 is_stmt 1 view -0 + 9025 .cfi_startproc + 9026 @ args = 0, pretend = 0, frame = 64 + 9027 @ frame_needed = 0, uses_anonymous_args = 0 +4623:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 9028 .loc 1 4623 1 is_stmt 0 view .LVU3049 + 9029 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 9030 .LCFI102: + 9031 .cfi_def_cfa_offset 36 + 9032 .cfi_offset 4, -36 + 9033 .cfi_offset 5, -32 + 9034 .cfi_offset 6, -28 + 9035 .cfi_offset 7, -24 + 9036 .cfi_offset 8, -20 + 9037 .cfi_offset 9, -16 + 9038 .cfi_offset 10, -12 + 9039 .cfi_offset 11, -8 + 9040 .cfi_offset 14, -4 + 9041 0004 91B0 sub sp, sp, #68 + 9042 .LCFI103: + 9043 .cfi_def_cfa_offset 104 + 9044 0006 0190 str r0, [sp, #4] +4624:Middlewares/Third_Party/FatFs/src/ff.c **** DIR dj; + 9045 .loc 1 4624 2 is_stmt 1 view .LVU3050 +4625:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; + 9046 .loc 1 4625 2 view .LVU3051 +4626:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE *dir; + 9047 .loc 1 4626 2 view .LVU3052 +4627:Middlewares/Third_Party/FatFs/src/ff.c **** UINT n; + 9048 .loc 1 4627 2 view .LVU3053 +4628:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD dsc, dcl, pcl, tm; + 9049 .loc 1 4628 2 view .LVU3054 +4629:Middlewares/Third_Party/FatFs/src/ff.c **** DEF_NAMBUF + 9050 .loc 1 4629 2 view .LVU3055 +4634:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.fs = fs; + 9051 .loc 1 4634 2 view .LVU3056 +4634:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.fs = fs; + 9052 .loc 1 4634 8 is_stmt 0 view .LVU3057 + 9053 0008 0222 movs r2, #2 + 9054 000a 03A9 add r1, sp, #12 + 9055 000c 01A8 add r0, sp, #4 + 9056 .LVL1042: +4634:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.fs = fs; + 9057 .loc 1 4634 8 view .LVU3058 + 9058 000e FFF7FEFF bl find_volume + 9059 .LVL1043: +4635:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 9060 .loc 1 4635 2 is_stmt 1 view .LVU3059 +4635:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 9061 .loc 1 4635 12 is_stmt 0 view .LVU3060 + 9062 0012 039B ldr r3, [sp, #12] + 9063 0014 0493 str r3, [sp, #16] +4636:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); + 9064 .loc 1 4636 2 is_stmt 1 view .LVU3061 + ARM GAS /tmp/cc2SVLkL.s page 311 + + +4636:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); + 9065 .loc 1 4636 5 is_stmt 0 view .LVU3062 + 9066 0016 0446 mov r4, r0 + 9067 0018 18B1 cbz r0, .L676 + 9068 .LVL1044: + 9069 .L660: +4704:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9070 .loc 1 4704 16 is_stmt 1 view .LVU3063 +4707:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9071 .loc 1 4707 2 view .LVU3064 +4708:Middlewares/Third_Party/FatFs/src/ff.c **** + 9072 .loc 1 4708 1 is_stmt 0 view .LVU3065 + 9073 001a 2046 mov r0, r4 + 9074 001c 11B0 add sp, sp, #68 + 9075 .LCFI104: + 9076 .cfi_remember_state + 9077 .cfi_def_cfa_offset 36 + 9078 @ sp needed + 9079 001e BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 9080 .LVL1045: + 9081 .L676: + 9082 .LCFI105: + 9083 .cfi_restore_state +4637:Middlewares/Third_Party/FatFs/src/ff.c **** res = follow_path(&dj, path); /* Follow the file path */ + 9084 .loc 1 4637 18 is_stmt 1 view .LVU3066 +4638:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */ + 9085 .loc 1 4638 3 view .LVU3067 +4638:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */ + 9086 .loc 1 4638 9 is_stmt 0 view .LVU3068 + 9087 0022 0199 ldr r1, [sp, #4] + 9088 0024 04A8 add r0, sp, #16 + 9089 .LVL1046: +4638:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */ + 9090 .loc 1 4638 9 view .LVU3069 + 9091 0026 FFF7FEFF bl follow_path + 9092 .LVL1047: +4639:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) { + 9093 .loc 1 4639 3 is_stmt 1 view .LVU3070 +4639:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) { + 9094 .loc 1 4639 6 is_stmt 0 view .LVU3071 + 9095 002a 0028 cmp r0, #0 + 9096 002c 00F09780 beq .L669 +4640:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INVALID_NAME; + 9097 .loc 1 4640 3 is_stmt 1 view .LVU3072 +4643:Middlewares/Third_Party/FatFs/src/ff.c **** dcl = create_chain(&dj.obj, 0); /* Allocate a cluster for the new directory table */ + 9098 .loc 1 4643 3 view .LVU3073 +4643:Middlewares/Third_Party/FatFs/src/ff.c **** dcl = create_chain(&dj.obj, 0); /* Allocate a cluster for the new directory table */ + 9099 .loc 1 4643 6 is_stmt 0 view .LVU3074 + 9100 0030 0428 cmp r0, #4 + 9101 0032 01D0 beq .L677 + 9102 0034 0446 mov r4, r0 + 9103 0036 F0E7 b .L660 + 9104 .L677: +4644:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.objsize = (DWORD)fs->csize * SS(fs); + 9105 .loc 1 4644 4 is_stmt 1 view .LVU3075 +4644:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.objsize = (DWORD)fs->csize * SS(fs); + 9106 .loc 1 4644 10 is_stmt 0 view .LVU3076 + ARM GAS /tmp/cc2SVLkL.s page 312 + + + 9107 0038 0021 movs r1, #0 + 9108 003a 04A8 add r0, sp, #16 + 9109 .LVL1048: +4644:Middlewares/Third_Party/FatFs/src/ff.c **** dj.obj.objsize = (DWORD)fs->csize * SS(fs); + 9110 .loc 1 4644 10 view .LVU3077 + 9111 003c FFF7FEFF bl create_chain + 9112 .LVL1049: +4645:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; + 9113 .loc 1 4645 4 is_stmt 1 view .LVU3078 +4645:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; + 9114 .loc 1 4645 30 is_stmt 0 view .LVU3079 + 9115 0040 039A ldr r2, [sp, #12] + 9116 0042 5389 ldrh r3, [r2, #10] +4645:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; + 9117 .loc 1 4645 40 view .LVU3080 + 9118 0044 9189 ldrh r1, [r2, #12] +4645:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; + 9119 .loc 1 4645 38 view .LVU3081 + 9120 0046 01FB03F3 mul r3, r1, r3 +4645:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_OK; + 9121 .loc 1 4645 19 view .LVU3082 + 9122 004a 0793 str r3, [sp, #28] +4646:Middlewares/Third_Party/FatFs/src/ff.c **** if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */ + 9123 .loc 1 4646 4 is_stmt 1 view .LVU3083 + 9124 .LVL1050: +4647:Middlewares/Third_Party/FatFs/src/ff.c **** if (dcl == 1) res = FR_INT_ERR; + 9125 .loc 1 4647 4 view .LVU3084 +4647:Middlewares/Third_Party/FatFs/src/ff.c **** if (dcl == 1) res = FR_INT_ERR; + 9126 .loc 1 4647 7 is_stmt 0 view .LVU3085 + 9127 004c 8146 mov r9, r0 + 9128 004e 18B1 cbz r0, .L671 +4648:Middlewares/Third_Party/FatFs/src/ff.c **** if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; + 9129 .loc 1 4648 4 is_stmt 1 view .LVU3086 +4648:Middlewares/Third_Party/FatFs/src/ff.c **** if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; + 9130 .loc 1 4648 7 is_stmt 0 view .LVU3087 + 9131 0050 0128 cmp r0, #1 + 9132 0052 02D1 bne .L661 +4648:Middlewares/Third_Party/FatFs/src/ff.c **** if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; + 9133 .loc 1 4648 22 discriminator 1 view .LVU3088 + 9134 0054 0224 movs r4, #2 + 9135 0056 03E0 b .L662 + 9136 .L671: +4647:Middlewares/Third_Party/FatFs/src/ff.c **** if (dcl == 1) res = FR_INT_ERR; + 9137 .loc 1 4647 22 discriminator 1 view .LVU3089 + 9138 0058 0724 movs r4, #7 + 9139 .L661: + 9140 .LVL1051: +4649:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) res = sync_window(fs); /* Flush FAT */ + 9141 .loc 1 4649 4 is_stmt 1 view .LVU3090 +4649:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) res = sync_window(fs); /* Flush FAT */ + 9142 .loc 1 4649 7 is_stmt 0 view .LVU3091 + 9143 005a B9F1FF3F cmp r9, #-1 + 9144 005e 55D0 beq .L678 + 9145 .LVL1052: + 9146 .L662: +4650:Middlewares/Third_Party/FatFs/src/ff.c **** tm = GET_FATTIME(); + 9147 .loc 1 4650 4 is_stmt 1 view .LVU3092 + ARM GAS /tmp/cc2SVLkL.s page 313 + + +4650:Middlewares/Third_Party/FatFs/src/ff.c **** tm = GET_FATTIME(); + 9148 .loc 1 4650 7 is_stmt 0 view .LVU3093 + 9149 0060 002C cmp r4, #0 + 9150 0062 4ED0 beq .L679 + 9151 .LVL1053: + 9152 .L663: +4651:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Initialize the new directory table */ + 9153 .loc 1 4651 4 is_stmt 1 view .LVU3094 +4651:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Initialize the new directory table */ + 9154 .loc 1 4651 9 is_stmt 0 view .LVU3095 + 9155 0064 FFF7FEFF bl get_fattime + 9156 .LVL1054: + 9157 0068 8246 mov r10, r0 + 9158 .LVL1055: +4652:Middlewares/Third_Party/FatFs/src/ff.c **** dsc = clust2sect(fs, dcl); + 9159 .loc 1 4652 4 is_stmt 1 view .LVU3096 +4652:Middlewares/Third_Party/FatFs/src/ff.c **** dsc = clust2sect(fs, dcl); + 9160 .loc 1 4652 7 is_stmt 0 view .LVU3097 + 9161 006a 002C cmp r4, #0 + 9162 006c 56D1 bne .L664 +4653:Middlewares/Third_Party/FatFs/src/ff.c **** dir = fs->win; + 9163 .loc 1 4653 5 is_stmt 1 view .LVU3098 +4653:Middlewares/Third_Party/FatFs/src/ff.c **** dir = fs->win; + 9164 .loc 1 4653 11 is_stmt 0 view .LVU3099 + 9165 006e 039E ldr r6, [sp, #12] + 9166 0070 4946 mov r1, r9 + 9167 0072 3046 mov r0, r6 + 9168 .LVL1056: +4653:Middlewares/Third_Party/FatFs/src/ff.c **** dir = fs->win; + 9169 .loc 1 4653 11 view .LVU3100 + 9170 0074 FFF7FEFF bl clust2sect + 9171 .LVL1057: + 9172 0078 0546 mov r5, r0 + 9173 .LVL1058: +4654:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(dir, 0, SS(fs)); + 9174 .loc 1 4654 5 is_stmt 1 view .LVU3101 +4654:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(dir, 0, SS(fs)); + 9175 .loc 1 4654 9 is_stmt 0 view .LVU3102 + 9176 007a 06F13408 add r8, r6, #52 + 9177 .LVL1059: +4655:Middlewares/Third_Party/FatFs/src/ff.c **** if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { + 9178 .loc 1 4655 5 is_stmt 1 view .LVU3103 + 9179 007e B289 ldrh r2, [r6, #12] + 9180 0080 0021 movs r1, #0 + 9181 0082 4046 mov r0, r8 + 9182 .LVL1060: +4655:Middlewares/Third_Party/FatFs/src/ff.c **** if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) { + 9183 .loc 1 4655 5 is_stmt 0 view .LVU3104 + 9184 0084 FFF7FEFF bl mem_set + 9185 .LVL1061: +4656:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(dir + DIR_Name, ' ', 11); /* Create "." entry */ + 9186 .loc 1 4656 5 is_stmt 1 view .LVU3105 +4657:Middlewares/Third_Party/FatFs/src/ff.c **** dir[DIR_Name] = '.'; + 9187 .loc 1 4657 6 view .LVU3106 + 9188 0088 0B22 movs r2, #11 + 9189 008a 2021 movs r1, #32 + 9190 008c 4046 mov r0, r8 + ARM GAS /tmp/cc2SVLkL.s page 314 + + + 9191 008e FFF7FEFF bl mem_set + 9192 .LVL1062: +4658:Middlewares/Third_Party/FatFs/src/ff.c **** dir[DIR_Attr] = AM_DIR; + 9193 .loc 1 4658 6 view .LVU3107 +4658:Middlewares/Third_Party/FatFs/src/ff.c **** dir[DIR_Attr] = AM_DIR; + 9194 .loc 1 4658 20 is_stmt 0 view .LVU3108 + 9195 0092 4FF02E0B mov fp, #46 + 9196 0096 86F834B0 strb fp, [r6, #52] +4659:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(dir + DIR_ModTime, tm); + 9197 .loc 1 4659 6 is_stmt 1 view .LVU3109 +4659:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(dir + DIR_ModTime, tm); + 9198 .loc 1 4659 20 is_stmt 0 view .LVU3110 + 9199 009a 1023 movs r3, #16 + 9200 009c 86F83F30 strb r3, [r6, #63] +4660:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dir, dcl); + 9201 .loc 1 4660 6 is_stmt 1 view .LVU3111 + 9202 00a0 5146 mov r1, r10 + 9203 00a2 06F14A00 add r0, r6, #74 + 9204 00a6 FFF7FEFF bl st_dword + 9205 .LVL1063: +4661:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(dir + SZDIRE, dir, SZDIRE); /* Create ".." entry */ + 9206 .loc 1 4661 6 view .LVU3112 + 9207 00aa 4A46 mov r2, r9 + 9208 00ac 4146 mov r1, r8 + 9209 00ae 0398 ldr r0, [sp, #12] + 9210 00b0 FFF7FEFF bl st_clust + 9211 .LVL1064: +4662:Middlewares/Third_Party/FatFs/src/ff.c **** dir[SZDIRE + 1] = '.'; pcl = dj.obj.sclust; + 9212 .loc 1 4662 6 view .LVU3113 +4662:Middlewares/Third_Party/FatFs/src/ff.c **** dir[SZDIRE + 1] = '.'; pcl = dj.obj.sclust; + 9213 .loc 1 4662 18 is_stmt 0 view .LVU3114 + 9214 00b4 06F15407 add r7, r6, #84 +4662:Middlewares/Third_Party/FatFs/src/ff.c **** dir[SZDIRE + 1] = '.'; pcl = dj.obj.sclust; + 9215 .loc 1 4662 6 view .LVU3115 + 9216 00b8 2022 movs r2, #32 + 9217 00ba 4146 mov r1, r8 + 9218 00bc 3846 mov r0, r7 + 9219 00be FFF7FEFF bl mem_cpy + 9220 .LVL1065: +4663:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_FAT32 && pcl == fs->dirbase) pcl = 0; + 9221 .loc 1 4663 6 is_stmt 1 view .LVU3116 +4663:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_FAT32 && pcl == fs->dirbase) pcl = 0; + 9222 .loc 1 4663 22 is_stmt 0 view .LVU3117 + 9223 00c2 86F855B0 strb fp, [r6, #85] +4663:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_FAT32 && pcl == fs->dirbase) pcl = 0; + 9224 .loc 1 4663 29 is_stmt 1 view .LVU3118 +4663:Middlewares/Third_Party/FatFs/src/ff.c **** if (fs->fs_type == FS_FAT32 && pcl == fs->dirbase) pcl = 0; + 9225 .loc 1 4663 33 is_stmt 0 view .LVU3119 + 9226 00c6 069A ldr r2, [sp, #24] + 9227 .LVL1066: +4664:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dir + SZDIRE, pcl); + 9228 .loc 1 4664 6 is_stmt 1 view .LVU3120 +4664:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dir + SZDIRE, pcl); + 9229 .loc 1 4664 12 is_stmt 0 view .LVU3121 + 9230 00c8 0398 ldr r0, [sp, #12] + 9231 00ca 0378 ldrb r3, [r0] @ zero_extendqisi2 +4664:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dir + SZDIRE, pcl); + ARM GAS /tmp/cc2SVLkL.s page 315 + + + 9232 .loc 1 4664 9 view .LVU3122 + 9233 00cc 032B cmp r3, #3 + 9234 00ce 1FD0 beq .L680 + 9235 .LVL1067: + 9236 .L665: +4665:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9237 .loc 1 4665 6 is_stmt 1 view .LVU3123 + 9238 00d0 3946 mov r1, r7 + 9239 00d2 FFF7FEFF bl st_clust + 9240 .LVL1068: +4667:Middlewares/Third_Party/FatFs/src/ff.c **** fs->winsect = dsc++; + 9241 .loc 1 4667 5 view .LVU3124 +4667:Middlewares/Third_Party/FatFs/src/ff.c **** fs->winsect = dsc++; + 9242 .loc 1 4667 16 is_stmt 0 view .LVU3125 + 9243 00d6 039B ldr r3, [sp, #12] + 9244 00d8 5E89 ldrh r6, [r3, #10] + 9245 .LVL1069: + 9246 .L666: +4667:Middlewares/Third_Party/FatFs/src/ff.c **** fs->winsect = dsc++; + 9247 .loc 1 4667 25 is_stmt 1 discriminator 1 view .LVU3126 + 9248 00da F6B1 cbz r6, .L667 +4668:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 9249 .loc 1 4668 6 view .LVU3127 +4668:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 9250 .loc 1 4668 23 is_stmt 0 view .LVU3128 + 9251 00dc 6F1C adds r7, r5, #1 + 9252 .LVL1070: +4668:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 9253 .loc 1 4668 8 view .LVU3129 + 9254 00de 039B ldr r3, [sp, #12] +4668:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 9255 .loc 1 4668 18 view .LVU3130 + 9256 00e0 1D63 str r5, [r3, #48] +4669:Middlewares/Third_Party/FatFs/src/ff.c **** res = sync_window(fs); + 9257 .loc 1 4669 6 is_stmt 1 view .LVU3131 +4669:Middlewares/Third_Party/FatFs/src/ff.c **** res = sync_window(fs); + 9258 .loc 1 4669 16 is_stmt 0 view .LVU3132 + 9259 00e2 0122 movs r2, #1 + 9260 00e4 DA70 strb r2, [r3, #3] +4670:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 9261 .loc 1 4670 6 is_stmt 1 view .LVU3133 +4670:Middlewares/Third_Party/FatFs/src/ff.c **** if (res != FR_OK) break; + 9262 .loc 1 4670 12 is_stmt 0 view .LVU3134 + 9263 00e6 0398 ldr r0, [sp, #12] + 9264 00e8 FFF7FEFF bl sync_window + 9265 .LVL1071: +4671:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(dir, 0, SS(fs)); + 9266 .loc 1 4671 6 is_stmt 1 view .LVU3135 +4671:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(dir, 0, SS(fs)); + 9267 .loc 1 4671 9 is_stmt 0 view .LVU3136 + 9268 00ec 0446 mov r4, r0 + 9269 00ee A0B9 cbnz r0, .L667 +4672:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9270 .loc 1 4672 6 is_stmt 1 view .LVU3137 + 9271 00f0 039B ldr r3, [sp, #12] + 9272 00f2 9A89 ldrh r2, [r3, #12] + 9273 00f4 0021 movs r1, #0 + ARM GAS /tmp/cc2SVLkL.s page 316 + + + 9274 00f6 4046 mov r0, r8 + 9275 .LVL1072: +4672:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9276 .loc 1 4672 6 is_stmt 0 view .LVU3138 + 9277 00f8 FFF7FEFF bl mem_set + 9278 .LVL1073: +4667:Middlewares/Third_Party/FatFs/src/ff.c **** fs->winsect = dsc++; + 9279 .loc 1 4667 29 is_stmt 1 discriminator 2 view .LVU3139 + 9280 00fc 013E subs r6, r6, #1 + 9281 .LVL1074: +4668:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 9282 .loc 1 4668 23 is_stmt 0 view .LVU3140 + 9283 00fe 3D46 mov r5, r7 + 9284 0100 EBE7 b .L666 + 9285 .LVL1075: + 9286 .L679: +4650:Middlewares/Third_Party/FatFs/src/ff.c **** tm = GET_FATTIME(); + 9287 .loc 1 4650 22 is_stmt 1 discriminator 1 view .LVU3141 +4650:Middlewares/Third_Party/FatFs/src/ff.c **** tm = GET_FATTIME(); + 9288 .loc 1 4650 28 is_stmt 0 discriminator 1 view .LVU3142 + 9289 0102 1046 mov r0, r2 + 9290 .LVL1076: +4650:Middlewares/Third_Party/FatFs/src/ff.c **** tm = GET_FATTIME(); + 9291 .loc 1 4650 28 discriminator 1 view .LVU3143 + 9292 0104 FFF7FEFF bl sync_window + 9293 .LVL1077: + 9294 0108 0446 mov r4, r0 + 9295 .LVL1078: +4650:Middlewares/Third_Party/FatFs/src/ff.c **** tm = GET_FATTIME(); + 9296 .loc 1 4650 28 discriminator 1 view .LVU3144 + 9297 010a ABE7 b .L663 + 9298 .LVL1079: + 9299 .L678: +4649:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) res = sync_window(fs); /* Flush FAT */ + 9300 .loc 1 4649 31 discriminator 1 view .LVU3145 + 9301 010c 0124 movs r4, #1 + 9302 .LVL1080: +4649:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) res = sync_window(fs); /* Flush FAT */ + 9303 .loc 1 4649 31 discriminator 1 view .LVU3146 + 9304 010e A9E7 b .L663 + 9305 .LVL1081: + 9306 .L680: +4664:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dir + SZDIRE, pcl); + 9307 .loc 1 4664 46 discriminator 1 view .LVU3147 + 9308 0110 836A ldr r3, [r0, #40] +4664:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dir + SZDIRE, pcl); + 9309 .loc 1 4664 34 discriminator 1 view .LVU3148 + 9310 0112 9342 cmp r3, r2 + 9311 0114 DCD1 bne .L665 +4664:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dir + SZDIRE, pcl); + 9312 .loc 1 4664 61 discriminator 2 view .LVU3149 + 9313 0116 0022 movs r2, #0 + 9314 .LVL1082: +4664:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dir + SZDIRE, pcl); + 9315 .loc 1 4664 61 discriminator 2 view .LVU3150 + 9316 0118 DAE7 b .L665 + 9317 .LVL1083: + ARM GAS /tmp/cc2SVLkL.s page 317 + + + 9318 .L667: +4675:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_register(&dj); /* Register the object to the directoy */ + 9319 .loc 1 4675 4 is_stmt 1 view .LVU3151 +4675:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_register(&dj); /* Register the object to the directoy */ + 9320 .loc 1 4675 7 is_stmt 0 view .LVU3152 + 9321 011a 2CB1 cbz r4, .L681 + 9322 .LVL1084: + 9323 .L664: +4701:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9324 .loc 1 4701 5 is_stmt 1 view .LVU3153 + 9325 011c 0022 movs r2, #0 + 9326 011e 4946 mov r1, r9 + 9327 0120 04A8 add r0, sp, #16 + 9328 0122 FFF7FEFF bl remove_chain + 9329 .LVL1085: + 9330 0126 78E7 b .L660 + 9331 .LVL1086: + 9332 .L681: +4676:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9333 .loc 1 4676 5 view .LVU3154 +4676:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9334 .loc 1 4676 11 is_stmt 0 view .LVU3155 + 9335 0128 04A8 add r0, sp, #16 + 9336 012a FFF7FEFF bl dir_register + 9337 .LVL1087: +4678:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 9338 .loc 1 4678 4 is_stmt 1 view .LVU3156 +4678:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 9339 .loc 1 4678 7 is_stmt 0 view .LVU3157 + 9340 012e 0446 mov r4, r0 + 9341 0130 0028 cmp r0, #0 + 9342 0132 F3D1 bne .L664 +4691:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(dir + DIR_ModTime, tm); /* Created time */ + 9343 .loc 1 4691 6 is_stmt 1 view .LVU3158 +4691:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(dir + DIR_ModTime, tm); /* Created time */ + 9344 .loc 1 4691 10 is_stmt 0 view .LVU3159 + 9345 0134 0C9C ldr r4, [sp, #48] + 9346 .LVL1088: +4692:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dir, dcl); /* Table start cluster */ + 9347 .loc 1 4692 6 is_stmt 1 view .LVU3160 + 9348 0136 5146 mov r1, r10 + 9349 0138 04F11600 add r0, r4, #22 + 9350 .LVL1089: +4692:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dir, dcl); /* Table start cluster */ + 9351 .loc 1 4692 6 is_stmt 0 view .LVU3161 + 9352 013c FFF7FEFF bl st_dword + 9353 .LVL1090: +4693:Middlewares/Third_Party/FatFs/src/ff.c **** dir[DIR_Attr] = AM_DIR; /* Attribute */ + 9354 .loc 1 4693 6 is_stmt 1 view .LVU3162 + 9355 0140 4A46 mov r2, r9 + 9356 0142 2146 mov r1, r4 + 9357 0144 0398 ldr r0, [sp, #12] + 9358 0146 FFF7FEFF bl st_clust + 9359 .LVL1091: +4694:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 9360 .loc 1 4694 6 view .LVU3163 +4694:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + ARM GAS /tmp/cc2SVLkL.s page 318 + + + 9361 .loc 1 4694 20 is_stmt 0 view .LVU3164 + 9362 014a 1023 movs r3, #16 + 9363 014c E372 strb r3, [r4, #11] +4695:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9364 .loc 1 4695 6 is_stmt 1 view .LVU3165 +4695:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9365 .loc 1 4695 16 is_stmt 0 view .LVU3166 + 9366 014e 039B ldr r3, [sp, #12] + 9367 0150 0122 movs r2, #1 + 9368 0152 DA70 strb r2, [r3, #3] +4697:Middlewares/Third_Party/FatFs/src/ff.c **** res = sync_fs(fs); + 9369 .loc 1 4697 5 is_stmt 1 view .LVU3167 +4698:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9370 .loc 1 4698 6 view .LVU3168 +4698:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9371 .loc 1 4698 12 is_stmt 0 view .LVU3169 + 9372 0154 0398 ldr r0, [sp, #12] + 9373 0156 FFF7FEFF bl sync_fs + 9374 .LVL1092: + 9375 015a 0446 mov r4, r0 + 9376 .LVL1093: +4698:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9377 .loc 1 4698 12 view .LVU3170 + 9378 015c 5DE7 b .L660 + 9379 .LVL1094: + 9380 .L669: +4639:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) { + 9381 .loc 1 4639 25 discriminator 1 view .LVU3171 + 9382 015e 0824 movs r4, #8 + 9383 0160 5BE7 b .L660 + 9384 .cfi_endproc + 9385 .LFE1235: + 9387 .section .text.f_rename,"ax",%progbits + 9388 .align 1 + 9389 .global f_rename + 9390 .syntax unified + 9391 .thumb + 9392 .thumb_func + 9394 f_rename: + 9395 .LVL1095: + 9396 .LFB1236: +4721:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 9397 .loc 1 4721 1 is_stmt 1 view -0 + 9398 .cfi_startproc + 9399 @ args = 0, pretend = 0, frame = 136 + 9400 @ frame_needed = 0, uses_anonymous_args = 0 +4721:Middlewares/Third_Party/FatFs/src/ff.c **** FRESULT res; + 9401 .loc 1 4721 1 is_stmt 0 view .LVU3173 + 9402 0000 30B5 push {r4, r5, lr} + 9403 .LCFI106: + 9404 .cfi_def_cfa_offset 12 + 9405 .cfi_offset 4, -12 + 9406 .cfi_offset 5, -8 + 9407 .cfi_offset 14, -4 + 9408 0002 A3B0 sub sp, sp, #140 + 9409 .LCFI107: + 9410 .cfi_def_cfa_offset 152 + ARM GAS /tmp/cc2SVLkL.s page 319 + + + 9411 0004 0190 str r0, [sp, #4] + 9412 0006 0091 str r1, [sp] +4722:Middlewares/Third_Party/FatFs/src/ff.c **** DIR djo, djn; + 9413 .loc 1 4722 2 is_stmt 1 view .LVU3174 +4723:Middlewares/Third_Party/FatFs/src/ff.c **** FATFS *fs; + 9414 .loc 1 4723 2 view .LVU3175 +4724:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE buf[_FS_EXFAT ? SZDIRE * 2 : 24], *dir; + 9415 .loc 1 4724 2 view .LVU3176 +4725:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD dw; + 9416 .loc 1 4725 2 view .LVU3177 +4726:Middlewares/Third_Party/FatFs/src/ff.c **** DEF_NAMBUF + 9417 .loc 1 4726 2 view .LVU3178 +4730:Middlewares/Third_Party/FatFs/src/ff.c **** res = find_volume(&path_old, &fs, FA_WRITE); /* Get logical drive of the old object */ + 9418 .loc 1 4730 2 view .LVU3179 + 9419 0008 6846 mov r0, sp + 9420 .LVL1096: +4730:Middlewares/Third_Party/FatFs/src/ff.c **** res = find_volume(&path_old, &fs, FA_WRITE); /* Get logical drive of the old object */ + 9421 .loc 1 4730 2 is_stmt 0 view .LVU3180 + 9422 000a FFF7FEFF bl get_ldnumber + 9423 .LVL1097: +4731:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 9424 .loc 1 4731 2 is_stmt 1 view .LVU3181 +4731:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 9425 .loc 1 4731 8 is_stmt 0 view .LVU3182 + 9426 000e 0222 movs r2, #2 + 9427 0010 09A9 add r1, sp, #36 + 9428 0012 01A8 add r0, sp, #4 + 9429 0014 FFF7FEFF bl find_volume + 9430 .LVL1098: +4732:Middlewares/Third_Party/FatFs/src/ff.c **** djo.obj.fs = fs; + 9431 .loc 1 4732 2 is_stmt 1 view .LVU3183 +4732:Middlewares/Third_Party/FatFs/src/ff.c **** djo.obj.fs = fs; + 9432 .loc 1 4732 5 is_stmt 0 view .LVU3184 + 9433 0018 0446 mov r4, r0 + 9434 001a 10B1 cbz r0, .L692 + 9435 .LVL1099: + 9436 .L683: +4807:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9437 .loc 1 4807 16 is_stmt 1 view .LVU3185 +4810:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9438 .loc 1 4810 2 view .LVU3186 +4811:Middlewares/Third_Party/FatFs/src/ff.c **** + 9439 .loc 1 4811 1 is_stmt 0 view .LVU3187 + 9440 001c 2046 mov r0, r4 + 9441 001e 23B0 add sp, sp, #140 + 9442 .LCFI108: + 9443 .cfi_remember_state + 9444 .cfi_def_cfa_offset 12 + 9445 @ sp needed + 9446 0020 30BD pop {r4, r5, pc} + 9447 .LVL1100: + 9448 .L692: + 9449 .LCFI109: + 9450 .cfi_restore_state +4733:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); + 9451 .loc 1 4733 3 is_stmt 1 view .LVU3188 +4733:Middlewares/Third_Party/FatFs/src/ff.c **** INIT_NAMBUF(fs); + ARM GAS /tmp/cc2SVLkL.s page 320 + + + 9452 .loc 1 4733 14 is_stmt 0 view .LVU3189 + 9453 0022 099B ldr r3, [sp, #36] + 9454 0024 1693 str r3, [sp, #88] +4734:Middlewares/Third_Party/FatFs/src/ff.c **** res = follow_path(&djo, path_old); /* Check old object */ + 9455 .loc 1 4734 18 is_stmt 1 view .LVU3190 +4735:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check vali + 9456 .loc 1 4735 3 view .LVU3191 +4735:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check vali + 9457 .loc 1 4735 9 is_stmt 0 view .LVU3192 + 9458 0026 0199 ldr r1, [sp, #4] + 9459 0028 16A8 add r0, sp, #88 + 9460 .LVL1101: +4735:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check vali + 9461 .loc 1 4735 9 view .LVU3193 + 9462 002a FFF7FEFF bl follow_path + 9463 .LVL1102: +4736:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 9464 .loc 1 4736 3 is_stmt 1 view .LVU3194 +4736:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 9465 .loc 1 4736 6 is_stmt 0 view .LVU3195 + 9466 002e 0446 mov r4, r0 + 9467 0030 48B9 cbnz r0, .L684 +4736:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 9468 .loc 1 4736 30 discriminator 1 view .LVU3196 + 9469 0032 9DF88730 ldrb r3, [sp, #135] @ zero_extendqisi2 +4736:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_LOCK != 0 + 9470 .loc 1 4736 20 discriminator 1 view .LVU3197 + 9471 0036 13F0A00F tst r3, #160 + 9472 003a 72D1 bne .L688 +4738:Middlewares/Third_Party/FatFs/src/ff.c **** res = chk_lock(&djo, 2); + 9473 .loc 1 4738 3 is_stmt 1 view .LVU3198 +4739:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9474 .loc 1 4739 4 view .LVU3199 +4739:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9475 .loc 1 4739 10 is_stmt 0 view .LVU3200 + 9476 003c 0221 movs r1, #2 + 9477 003e 16A8 add r0, sp, #88 + 9478 .LVL1103: +4739:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9479 .loc 1 4739 10 view .LVU3201 + 9480 0040 FFF7FEFF bl chk_lock + 9481 .LVL1104: + 9482 0044 0446 mov r4, r0 + 9483 .LVL1105: + 9484 .L684: +4742:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 9485 .loc 1 4742 3 is_stmt 1 view .LVU3202 +4742:Middlewares/Third_Party/FatFs/src/ff.c **** #if _FS_EXFAT + 9486 .loc 1 4742 6 is_stmt 0 view .LVU3203 + 9487 0046 002C cmp r4, #0 + 9488 0048 E8D1 bne .L683 +4769:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(&djn, &djo, sizeof (DIR)); /* Duplicate the directory object */ + 9489 .loc 1 4769 5 is_stmt 1 view .LVU3204 + 9490 004a 1522 movs r2, #21 + 9491 004c 1E99 ldr r1, [sp, #120] + 9492 004e 0B31 adds r1, r1, #11 + 9493 0050 03A8 add r0, sp, #12 + ARM GAS /tmp/cc2SVLkL.s page 321 + + + 9494 0052 FFF7FEFF bl mem_cpy + 9495 .LVL1106: +4770:Middlewares/Third_Party/FatFs/src/ff.c **** res = follow_path(&djn, path_new); /* Make sure if new object name is not in use */ + 9496 .loc 1 4770 5 view .LVU3205 + 9497 0056 3022 movs r2, #48 + 9498 0058 16A9 add r1, sp, #88 + 9499 005a 0AA8 add r0, sp, #40 + 9500 005c FFF7FEFF bl mem_cpy + 9501 .LVL1107: +4771:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Is new name already in use by any other object? */ + 9502 .loc 1 4771 5 view .LVU3206 +4771:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { /* Is new name already in use by any other object? */ + 9503 .loc 1 4771 11 is_stmt 0 view .LVU3207 + 9504 0060 0099 ldr r1, [sp] + 9505 0062 0AA8 add r0, sp, #40 + 9506 0064 FFF7FEFF bl follow_path + 9507 .LVL1108: +4772:Middlewares/Third_Party/FatFs/src/ff.c **** res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST; + 9508 .loc 1 4772 5 is_stmt 1 view .LVU3208 +4772:Middlewares/Third_Party/FatFs/src/ff.c **** res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST; + 9509 .loc 1 4772 8 is_stmt 0 view .LVU3209 + 9510 0068 0446 mov r4, r0 + 9511 006a 58B9 cbnz r0, .L685 +4773:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9512 .loc 1 4773 6 is_stmt 1 view .LVU3210 +4773:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9513 .loc 1 4773 84 is_stmt 0 view .LVU3211 + 9514 006c 0C9A ldr r2, [sp, #48] + 9515 006e 189B ldr r3, [sp, #96] + 9516 0070 9A42 cmp r2, r3 + 9517 0072 01D0 beq .L693 + 9518 .LVL1109: +4773:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9519 .loc 1 4773 10 discriminator 6 view .LVU3212 + 9520 0074 0824 movs r4, #8 + 9521 0076 07E0 b .L686 + 9522 .LVL1110: + 9523 .L693: +4773:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9524 .loc 1 4773 46 discriminator 1 view .LVU3213 + 9525 0078 0F9A ldr r2, [sp, #60] + 9526 007a 1B9B ldr r3, [sp, #108] + 9527 007c 9A42 cmp r2, r3 + 9528 007e 10D0 beq .L687 + 9529 .LVL1111: +4773:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9530 .loc 1 4773 10 discriminator 6 view .LVU3214 + 9531 0080 0824 movs r4, #8 + 9532 0082 01E0 b .L686 + 9533 .LVL1112: + 9534 .L685: +4775:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_register(&djn); /* Register the new entry */ + 9535 .loc 1 4775 5 is_stmt 1 view .LVU3215 +4775:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_register(&djn); /* Register the new entry */ + 9536 .loc 1 4775 8 is_stmt 0 view .LVU3216 + 9537 0084 0428 cmp r0, #4 + 9538 0086 0CD0 beq .L687 + ARM GAS /tmp/cc2SVLkL.s page 322 + + + 9539 .LVL1113: + 9540 .L686: +4799:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_remove(&djo); /* Remove old entry */ + 9541 .loc 1 4799 4 is_stmt 1 view .LVU3217 +4799:Middlewares/Third_Party/FatFs/src/ff.c **** res = dir_remove(&djo); /* Remove old entry */ + 9542 .loc 1 4799 7 is_stmt 0 view .LVU3218 + 9543 0088 002C cmp r4, #0 + 9544 008a C7D1 bne .L683 +4800:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 9545 .loc 1 4800 5 is_stmt 1 view .LVU3219 +4800:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 9546 .loc 1 4800 11 is_stmt 0 view .LVU3220 + 9547 008c 16A8 add r0, sp, #88 + 9548 008e FFF7FEFF bl dir_remove + 9549 .LVL1114: +4801:Middlewares/Third_Party/FatFs/src/ff.c **** res = sync_fs(fs); + 9550 .loc 1 4801 5 is_stmt 1 view .LVU3221 +4801:Middlewares/Third_Party/FatFs/src/ff.c **** res = sync_fs(fs); + 9551 .loc 1 4801 8 is_stmt 0 view .LVU3222 + 9552 0092 0446 mov r4, r0 + 9553 0094 0028 cmp r0, #0 + 9554 0096 C1D1 bne .L683 +4802:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9555 .loc 1 4802 6 is_stmt 1 view .LVU3223 +4802:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9556 .loc 1 4802 12 is_stmt 0 view .LVU3224 + 9557 0098 0998 ldr r0, [sp, #36] + 9558 .LVL1115: +4802:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9559 .loc 1 4802 12 view .LVU3225 + 9560 009a FFF7FEFF bl sync_fs + 9561 .LVL1116: + 9562 009e 0446 mov r4, r0 + 9563 .LVL1117: +4802:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9564 .loc 1 4802 12 view .LVU3226 + 9565 00a0 BCE7 b .L683 + 9566 .LVL1118: + 9567 .L687: +4776:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 9568 .loc 1 4776 6 is_stmt 1 view .LVU3227 +4776:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK) { + 9569 .loc 1 4776 12 is_stmt 0 view .LVU3228 + 9570 00a2 0AA8 add r0, sp, #40 + 9571 00a4 FFF7FEFF bl dir_register + 9572 .LVL1119: +4777:Middlewares/Third_Party/FatFs/src/ff.c **** dir = djn.dir; /* Copy information about object except name */ + 9573 .loc 1 4777 6 is_stmt 1 view .LVU3229 +4777:Middlewares/Third_Party/FatFs/src/ff.c **** dir = djn.dir; /* Copy information about object except name */ + 9574 .loc 1 4777 9 is_stmt 0 view .LVU3230 + 9575 00a8 0446 mov r4, r0 + 9576 00aa 0028 cmp r0, #0 + 9577 00ac B6D1 bne .L683 +4778:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(dir + 13, buf + 2, 19); + 9578 .loc 1 4778 7 is_stmt 1 view .LVU3231 +4778:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(dir + 13, buf + 2, 19); + 9579 .loc 1 4778 11 is_stmt 0 view .LVU3232 + ARM GAS /tmp/cc2SVLkL.s page 323 + + + 9580 00ae 129D ldr r5, [sp, #72] + 9581 .LVL1120: +4779:Middlewares/Third_Party/FatFs/src/ff.c **** dir[DIR_Attr] = buf[0] | AM_ARC; + 9582 .loc 1 4779 7 is_stmt 1 view .LVU3233 + 9583 00b0 1322 movs r2, #19 + 9584 00b2 0DF10E01 add r1, sp, #14 + 9585 00b6 05F10D00 add r0, r5, #13 + 9586 .LVL1121: +4779:Middlewares/Third_Party/FatFs/src/ff.c **** dir[DIR_Attr] = buf[0] | AM_ARC; + 9587 .loc 1 4779 7 is_stmt 0 view .LVU3234 + 9588 00ba FFF7FEFF bl mem_cpy + 9589 .LVL1122: +4780:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 9590 .loc 1 4780 7 is_stmt 1 view .LVU3235 +4780:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 9591 .loc 1 4780 26 is_stmt 0 view .LVU3236 + 9592 00be 9DF80C30 ldrb r3, [sp, #12] @ zero_extendqisi2 +4780:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 9593 .loc 1 4780 21 view .LVU3237 + 9594 00c2 43F02003 orr r3, r3, #32 + 9595 00c6 EB72 strb r3, [r5, #11] +4781:Middlewares/Third_Party/FatFs/src/ff.c **** if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) { /* Update .. entry in the + 9596 .loc 1 4781 7 is_stmt 1 view .LVU3238 +4781:Middlewares/Third_Party/FatFs/src/ff.c **** if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) { /* Update .. entry in the + 9597 .loc 1 4781 17 is_stmt 0 view .LVU3239 + 9598 00c8 099B ldr r3, [sp, #36] + 9599 00ca 0122 movs r2, #1 + 9600 00cc DA70 strb r2, [r3, #3] +4782:Middlewares/Third_Party/FatFs/src/ff.c **** dw = clust2sect(fs, ld_clust(fs, dir)); + 9601 .loc 1 4782 7 is_stmt 1 view .LVU3240 +4782:Middlewares/Third_Party/FatFs/src/ff.c **** dw = clust2sect(fs, ld_clust(fs, dir)); + 9602 .loc 1 4782 15 is_stmt 0 view .LVU3241 + 9603 00ce EB7A ldrb r3, [r5, #11] @ zero_extendqisi2 +4782:Middlewares/Third_Party/FatFs/src/ff.c **** dw = clust2sect(fs, ld_clust(fs, dir)); + 9604 .loc 1 4782 10 view .LVU3242 + 9605 00d0 13F0100F tst r3, #16 + 9606 00d4 D8D0 beq .L686 +4782:Middlewares/Third_Party/FatFs/src/ff.c **** dw = clust2sect(fs, ld_clust(fs, dir)); + 9607 .loc 1 4782 36 discriminator 1 view .LVU3243 + 9608 00d6 189A ldr r2, [sp, #96] + 9609 00d8 0C9B ldr r3, [sp, #48] + 9610 00da 9A42 cmp r2, r3 + 9611 00dc D4D0 beq .L686 +4783:Middlewares/Third_Party/FatFs/src/ff.c **** if (!dw) { + 9612 .loc 1 4783 8 is_stmt 1 view .LVU3244 +4783:Middlewares/Third_Party/FatFs/src/ff.c **** if (!dw) { + 9613 .loc 1 4783 13 is_stmt 0 view .LVU3245 + 9614 00de 099C ldr r4, [sp, #36] + 9615 .LVL1123: +4783:Middlewares/Third_Party/FatFs/src/ff.c **** if (!dw) { + 9616 .loc 1 4783 13 view .LVU3246 + 9617 00e0 2946 mov r1, r5 + 9618 00e2 2046 mov r0, r4 + 9619 00e4 FFF7FEFF bl ld_clust + 9620 .LVL1124: + 9621 00e8 0146 mov r1, r0 +4783:Middlewares/Third_Party/FatFs/src/ff.c **** if (!dw) { + ARM GAS /tmp/cc2SVLkL.s page 324 + + + 9622 .loc 1 4783 13 discriminator 1 view .LVU3247 + 9623 00ea 2046 mov r0, r4 + 9624 00ec FFF7FEFF bl clust2sect + 9625 .LVL1125: +4784:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INT_ERR; + 9626 .loc 1 4784 8 is_stmt 1 view .LVU3248 +4784:Middlewares/Third_Party/FatFs/src/ff.c **** res = FR_INT_ERR; + 9627 .loc 1 4784 11 is_stmt 0 view .LVU3249 + 9628 00f0 0146 mov r1, r0 + 9629 00f2 08B9 cbnz r0, .L694 + 9630 .LVL1126: +4785:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 9631 .loc 1 4785 13 view .LVU3250 + 9632 00f4 0224 movs r4, #2 + 9633 00f6 91E7 b .L683 + 9634 .LVL1127: + 9635 .L694: +4788:Middlewares/Third_Party/FatFs/src/ff.c **** dir = fs->win + SZDIRE * 1; /* Ptr to .. entry */ + 9636 .loc 1 4788 9 is_stmt 1 view .LVU3251 +4788:Middlewares/Third_Party/FatFs/src/ff.c **** dir = fs->win + SZDIRE * 1; /* Ptr to .. entry */ + 9637 .loc 1 4788 15 is_stmt 0 view .LVU3252 + 9638 00f8 2046 mov r0, r4 + 9639 .LVL1128: +4788:Middlewares/Third_Party/FatFs/src/ff.c **** dir = fs->win + SZDIRE * 1; /* Ptr to .. entry */ + 9640 .loc 1 4788 15 view .LVU3253 + 9641 00fa FFF7FEFF bl move_window + 9642 .LVL1129: +4789:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && dir[1] == '.') { + 9643 .loc 1 4789 9 is_stmt 1 view .LVU3254 +4789:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && dir[1] == '.') { + 9644 .loc 1 4789 17 is_stmt 0 view .LVU3255 + 9645 00fe 099B ldr r3, [sp, #36] +4789:Middlewares/Third_Party/FatFs/src/ff.c **** if (res == FR_OK && dir[1] == '.') { + 9646 .loc 1 4789 13 view .LVU3256 + 9647 0100 03F15401 add r1, r3, #84 + 9648 .LVL1130: +4790:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dir, djn.obj.sclust); + 9649 .loc 1 4790 9 is_stmt 1 view .LVU3257 +4790:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dir, djn.obj.sclust); + 9650 .loc 1 4790 12 is_stmt 0 view .LVU3258 + 9651 0104 0446 mov r4, r0 + 9652 0106 0028 cmp r0, #0 + 9653 0108 88D1 bne .L683 +4790:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dir, djn.obj.sclust); + 9654 .loc 1 4790 32 discriminator 1 view .LVU3259 + 9655 010a 93F85520 ldrb r2, [r3, #85] @ zero_extendqisi2 +4790:Middlewares/Third_Party/FatFs/src/ff.c **** st_clust(fs, dir, djn.obj.sclust); + 9656 .loc 1 4790 26 discriminator 1 view .LVU3260 + 9657 010e 2E2A cmp r2, #46 + 9658 0110 BAD1 bne .L686 +4791:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 9659 .loc 1 4791 10 is_stmt 1 view .LVU3261 + 9660 0112 0C9A ldr r2, [sp, #48] + 9661 0114 1846 mov r0, r3 + 9662 .LVL1131: +4791:Middlewares/Third_Party/FatFs/src/ff.c **** fs->wflag = 1; + 9663 .loc 1 4791 10 is_stmt 0 view .LVU3262 + ARM GAS /tmp/cc2SVLkL.s page 325 + + + 9664 0116 FFF7FEFF bl st_clust + 9665 .LVL1132: +4792:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9666 .loc 1 4792 10 is_stmt 1 view .LVU3263 +4792:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9667 .loc 1 4792 20 is_stmt 0 view .LVU3264 + 9668 011a 099B ldr r3, [sp, #36] + 9669 011c 0122 movs r2, #1 + 9670 011e DA70 strb r2, [r3, #3] + 9671 0120 B2E7 b .L686 + 9672 .LVL1133: + 9673 .L688: +4792:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9674 .loc 1 4792 20 view .LVU3265 + 9675 0122 0624 movs r4, #6 + 9676 0124 7AE7 b .L683 + 9677 .cfi_endproc + 9678 .LFE1236: + 9680 .section .rodata.f_mkfs.str1.4,"aMS",%progbits,1 + 9681 .align 2 + 9682 .LC1: + 9683 0000 EBFE904D .ascii "\353\376\220MSDOS5.0\000" + 9683 53444F53 + 9683 352E3000 + 9684 .align 2 + 9685 .LC2: + 9686 000c 4E4F204E .ascii "NO NAME FAT32 \000" + 9686 414D4520 + 9686 20202046 + 9686 41543332 + 9686 20202000 + 9687 .align 2 + 9688 .LC3: + 9689 0020 4E4F204E .ascii "NO NAME FAT \000" + 9689 414D4520 + 9689 20202046 + 9689 41542020 + 9689 20202000 + 9690 .section .text.f_mkfs,"ax",%progbits + 9691 .align 1 + 9692 .global f_mkfs + 9693 .syntax unified + 9694 .thumb + 9695 .thumb_func + 9697 f_mkfs: + 9698 .LVL1134: + 9699 .LFB1237: +5308:Middlewares/Third_Party/FatFs/src/ff.c **** const UINT n_fats = 1; /* Number of FATs for FAT12/16/32 volume (1 or 2) */ + 9700 .loc 1 5308 1 is_stmt 1 view -0 + 9701 .cfi_startproc + 9702 @ args = 4, pretend = 0, frame = 56 + 9703 @ frame_needed = 0, uses_anonymous_args = 0 +5308:Middlewares/Third_Party/FatFs/src/ff.c **** const UINT n_fats = 1; /* Number of FATs for FAT12/16/32 volume (1 or 2) */ + 9704 .loc 1 5308 1 is_stmt 0 view .LVU3267 + 9705 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 9706 .LCFI110: + 9707 .cfi_def_cfa_offset 36 + ARM GAS /tmp/cc2SVLkL.s page 326 + + + 9708 .cfi_offset 4, -36 + 9709 .cfi_offset 5, -32 + 9710 .cfi_offset 6, -28 + 9711 .cfi_offset 7, -24 + 9712 .cfi_offset 8, -20 + 9713 .cfi_offset 9, -16 + 9714 .cfi_offset 10, -12 + 9715 .cfi_offset 11, -8 + 9716 .cfi_offset 14, -4 + 9717 0004 8FB0 sub sp, sp, #60 + 9718 .LCFI111: + 9719 .cfi_def_cfa_offset 96 + 9720 0006 0990 str r0, [sp, #36] + 9721 0008 0F46 mov r7, r1 + 9722 000a 1546 mov r5, r2 + 9723 000c 1E46 mov r6, r3 +5309:Middlewares/Third_Party/FatFs/src/ff.c **** const UINT n_rootdir = 512; /* Number of root directory entries for FAT12/16 volume */ + 9724 .loc 1 5309 2 is_stmt 1 view .LVU3268 + 9725 .LVL1135: +5310:Middlewares/Third_Party/FatFs/src/ff.c **** static const WORD cst[] = {1, 4, 16, 64, 256, 512, 0}; /* Cluster size boundary for FAT12/16 volum + 9726 .loc 1 5310 2 view .LVU3269 +5311:Middlewares/Third_Party/FatFs/src/ff.c **** static const WORD cst32[] = {1, 2, 4, 8, 16, 32, 0}; /* Cluster size boundary for FAT32 volume (12 + 9727 .loc 1 5311 2 view .LVU3270 +5312:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE fmt, sys, *buf, *pte, pdrv, part; + 9728 .loc 1 5312 2 view .LVU3271 +5313:Middlewares/Third_Party/FatFs/src/ff.c **** WORD ss; + 9729 .loc 1 5313 2 view .LVU3272 +5314:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD szb_buf, sz_buf, sz_blk, n_clst, pau, sect, nsect, n; + 9730 .loc 1 5314 2 view .LVU3273 +5315:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD b_vol, b_fat, b_data; /* Base LBA for volume, fat, data */ + 9731 .loc 1 5315 2 view .LVU3274 +5316:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD sz_vol, sz_rsv, sz_fat, sz_dir; /* Size for volume, fat, dir, data */ + 9732 .loc 1 5316 2 view .LVU3275 +5317:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i; + 9733 .loc 1 5317 2 view .LVU3276 +5318:Middlewares/Third_Party/FatFs/src/ff.c **** int vol; + 9734 .loc 1 5318 2 view .LVU3277 +5319:Middlewares/Third_Party/FatFs/src/ff.c **** DSTATUS stat; + 9735 .loc 1 5319 2 view .LVU3278 +5320:Middlewares/Third_Party/FatFs/src/ff.c **** #if _USE_TRIM || _FS_EXFAT + 9736 .loc 1 5320 2 view .LVU3279 +5327:Middlewares/Third_Party/FatFs/src/ff.c **** if (vol < 0) return FR_INVALID_DRIVE; + 9737 .loc 1 5327 2 view .LVU3280 +5327:Middlewares/Third_Party/FatFs/src/ff.c **** if (vol < 0) return FR_INVALID_DRIVE; + 9738 .loc 1 5327 8 is_stmt 0 view .LVU3281 + 9739 000e 09A8 add r0, sp, #36 + 9740 .LVL1136: +5327:Middlewares/Third_Party/FatFs/src/ff.c **** if (vol < 0) return FR_INVALID_DRIVE; + 9741 .loc 1 5327 8 view .LVU3282 + 9742 0010 FFF7FEFF bl get_ldnumber + 9743 .LVL1137: +5328:Middlewares/Third_Party/FatFs/src/ff.c **** if (FatFs[vol]) FatFs[vol]->fs_type = 0; /* Clear the volume */ + 9744 .loc 1 5328 2 is_stmt 1 view .LVU3283 +5328:Middlewares/Third_Party/FatFs/src/ff.c **** if (FatFs[vol]) FatFs[vol]->fs_type = 0; /* Clear the volume */ + 9745 .loc 1 5328 5 is_stmt 0 view .LVU3284 + 9746 0014 0028 cmp r0, #0 +5328:Middlewares/Third_Party/FatFs/src/ff.c **** if (FatFs[vol]) FatFs[vol]->fs_type = 0; /* Clear the volume */ + ARM GAS /tmp/cc2SVLkL.s page 327 + + + 9747 .loc 1 5328 5 view .LVU3285 + 9748 0016 C0F2FA82 blt .L738 +5329:Middlewares/Third_Party/FatFs/src/ff.c **** pdrv = LD2PD(vol); /* Physical drive */ + 9749 .loc 1 5329 2 is_stmt 1 view .LVU3286 +5329:Middlewares/Third_Party/FatFs/src/ff.c **** pdrv = LD2PD(vol); /* Physical drive */ + 9750 .loc 1 5329 11 is_stmt 0 view .LVU3287 + 9751 001a A14B ldr r3, .L793 + 9752 001c 53F82030 ldr r3, [r3, r0, lsl #2] +5329:Middlewares/Third_Party/FatFs/src/ff.c **** pdrv = LD2PD(vol); /* Physical drive */ + 9753 .loc 1 5329 5 view .LVU3288 + 9754 0020 0BB1 cbz r3, .L697 +5329:Middlewares/Third_Party/FatFs/src/ff.c **** pdrv = LD2PD(vol); /* Physical drive */ + 9755 .loc 1 5329 18 is_stmt 1 discriminator 1 view .LVU3289 +5329:Middlewares/Third_Party/FatFs/src/ff.c **** pdrv = LD2PD(vol); /* Physical drive */ + 9756 .loc 1 5329 38 is_stmt 0 discriminator 1 view .LVU3290 + 9757 0022 0022 movs r2, #0 + 9758 0024 1A70 strb r2, [r3] + 9759 .L697: +5330:Middlewares/Third_Party/FatFs/src/ff.c **** part = LD2PT(vol); /* Partition (0:create as new, 1-4:get from partition table) */ + 9760 .loc 1 5330 2 is_stmt 1 view .LVU3291 +5330:Middlewares/Third_Party/FatFs/src/ff.c **** part = LD2PT(vol); /* Partition (0:create as new, 1-4:get from partition table) */ + 9761 .loc 1 5330 7 is_stmt 0 view .LVU3292 + 9762 0026 C4B2 uxtb r4, r0 + 9763 .LVL1138: +5331:Middlewares/Third_Party/FatFs/src/ff.c **** + 9764 .loc 1 5331 2 is_stmt 1 view .LVU3293 +5334:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat & STA_NOINIT) return FR_NOT_READY; + 9765 .loc 1 5334 2 view .LVU3294 +5334:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat & STA_NOINIT) return FR_NOT_READY; + 9766 .loc 1 5334 9 is_stmt 0 view .LVU3295 + 9767 0028 2046 mov r0, r4 + 9768 .LVL1139: +5334:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat & STA_NOINIT) return FR_NOT_READY; + 9769 .loc 1 5334 9 view .LVU3296 + 9770 002a FFF7FEFF bl disk_initialize + 9771 .LVL1140: +5335:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; + 9772 .loc 1 5335 2 is_stmt 1 view .LVU3297 +5335:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; + 9773 .loc 1 5335 5 is_stmt 0 view .LVU3298 + 9774 002e 10F0010F tst r0, #1 + 9775 0032 40F0EE82 bne .L739 +5336:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 32768 || (sz_blk & + 9776 .loc 1 5336 2 is_stmt 1 view .LVU3299 +5336:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 32768 || (sz_blk & + 9777 .loc 1 5336 5 is_stmt 0 view .LVU3300 + 9778 0036 10F0040F tst r0, #4 + 9779 003a 40F0EC82 bne .L740 +5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS /* Get sector size of the medium if variable sector size cfg. */ + 9780 .loc 1 5337 2 is_stmt 1 view .LVU3301 +5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS /* Get sector size of the medium if variable sector size cfg. */ + 9781 .loc 1 5337 6 is_stmt 0 view .LVU3302 + 9782 003e 0CAA add r2, sp, #48 + 9783 0040 0321 movs r1, #3 + 9784 0042 2046 mov r0, r4 + 9785 .LVL1141: +5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS /* Get sector size of the medium if variable sector size cfg. */ + ARM GAS /tmp/cc2SVLkL.s page 328 + + + 9786 .loc 1 5337 6 view .LVU3303 + 9787 0044 FFF7FEFF bl disk_ioctl + 9788 .LVL1142: +5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS /* Get sector size of the medium if variable sector size cfg. */ + 9789 .loc 1 5337 5 discriminator 1 view .LVU3304 + 9790 0048 38B9 cbnz r0, .L698 +5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS /* Get sector size of the medium if variable sector size cfg. */ + 9791 .loc 1 5337 61 discriminator 2 view .LVU3305 + 9792 004a 0C9B ldr r3, [sp, #48] +5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS /* Get sector size of the medium if variable sector size cfg. */ + 9793 .loc 1 5337 58 discriminator 2 view .LVU3306 + 9794 004c 2BB1 cbz r3, .L698 +5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS /* Get sector size of the medium if variable sector size cfg. */ + 9795 .loc 1 5337 69 discriminator 4 view .LVU3307 + 9796 004e B3F5004F cmp r3, #32768 + 9797 0052 02D8 bhi .L698 +5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS /* Get sector size of the medium if variable sector size cfg. */ + 9798 .loc 1 5337 108 discriminator 6 view .LVU3308 + 9799 0054 5A1E subs r2, r3, #1 +5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS /* Get sector size of the medium if variable sector size cfg. */ + 9800 .loc 1 5337 87 discriminator 6 view .LVU3309 + 9801 0056 1342 tst r3, r2 + 9802 0058 01D0 beq .L699 + 9803 .L698: +5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS /* Get sector size of the medium if variable sector size cfg. */ + 9804 .loc 1 5337 115 is_stmt 1 discriminator 7 view .LVU3310 +5337:Middlewares/Third_Party/FatFs/src/ff.c **** #if _MAX_SS != _MIN_SS /* Get sector size of the medium if variable sector size cfg. */ + 9805 .loc 1 5337 122 is_stmt 0 discriminator 7 view .LVU3311 + 9806 005a 0123 movs r3, #1 + 9807 005c 0C93 str r3, [sp, #48] + 9808 .L699: +5339:Middlewares/Third_Party/FatFs/src/ff.c **** if (ss > _MAX_SS || ss < _MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR; + 9809 .loc 1 5339 2 is_stmt 1 view .LVU3312 +5339:Middlewares/Third_Party/FatFs/src/ff.c **** if (ss > _MAX_SS || ss < _MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR; + 9810 .loc 1 5339 6 is_stmt 0 view .LVU3313 + 9811 005e 0DF13602 add r2, sp, #54 + 9812 0062 0221 movs r1, #2 + 9813 0064 2046 mov r0, r4 + 9814 0066 FFF7FEFF bl disk_ioctl + 9815 .LVL1143: +5339:Middlewares/Third_Party/FatFs/src/ff.c **** if (ss > _MAX_SS || ss < _MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR; + 9816 .loc 1 5339 5 discriminator 1 view .LVU3314 + 9817 006a 0028 cmp r0, #0 + 9818 006c 40F0D782 bne .L741 +5340:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 9819 .loc 1 5340 2 is_stmt 1 view .LVU3315 +5340:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 9820 .loc 1 5340 19 is_stmt 0 view .LVU3316 + 9821 0070 BDF83630 ldrh r3, [sp, #54] + 9822 0074 A3F50072 sub r2, r3, #512 + 9823 0078 92B2 uxth r2, r2 +5340:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 9824 .loc 1 5340 5 view .LVU3317 + 9825 007a B2F5606F cmp r2, #3584 + 9826 007e 00F2D082 bhi .L742 +5340:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 9827 .loc 1 5340 48 discriminator 2 view .LVU3318 + ARM GAS /tmp/cc2SVLkL.s page 329 + + + 9828 0082 5A1E subs r2, r3, #1 +5340:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 9829 .loc 1 5340 35 discriminator 2 view .LVU3319 + 9830 0084 1342 tst r3, r2 + 9831 0086 40F0CE82 bne .L743 +5344:Middlewares/Third_Party/FatFs/src/ff.c **** au /= ss; /* Cluster size in unit of sector */ + 9832 .loc 1 5344 2 is_stmt 1 view .LVU3320 +5344:Middlewares/Third_Party/FatFs/src/ff.c **** au /= ss; /* Cluster size in unit of sector */ + 9833 .loc 1 5344 5 is_stmt 0 view .LVU3321 + 9834 008a 35B1 cbz r5, .L700 +5344:Middlewares/Third_Party/FatFs/src/ff.c **** au /= ss; /* Cluster size in unit of sector */ + 9835 .loc 1 5344 15 discriminator 1 view .LVU3322 + 9836 008c AB42 cmp r3, r5 + 9837 008e 00F2CC82 bhi .L744 +5344:Middlewares/Third_Party/FatFs/src/ff.c **** au /= ss; /* Cluster size in unit of sector */ + 9838 .loc 1 5344 27 discriminator 4 view .LVU3323 + 9839 0092 B5F1807F cmp r5, #16777216 + 9840 0096 00F2CA82 bhi .L745 + 9841 .L700: +5344:Middlewares/Third_Party/FatFs/src/ff.c **** au /= ss; /* Cluster size in unit of sector */ + 9842 .loc 1 5344 58 discriminator 6 view .LVU3324 + 9843 009a 6A1E subs r2, r5, #1 +5344:Middlewares/Third_Party/FatFs/src/ff.c **** au /= ss; /* Cluster size in unit of sector */ + 9844 .loc 1 5344 45 discriminator 6 view .LVU3325 + 9845 009c 2A40 ands r2, r2, r5 + 9846 009e 0192 str r2, [sp, #4] + 9847 00a0 40F0C782 bne .L746 +5345:Middlewares/Third_Party/FatFs/src/ff.c **** + 9848 .loc 1 5345 2 is_stmt 1 view .LVU3326 +5345:Middlewares/Third_Party/FatFs/src/ff.c **** + 9849 .loc 1 5345 5 is_stmt 0 view .LVU3327 + 9850 00a4 B5FBF3F5 udiv r5, r5, r3 + 9851 .LVL1144: +5348:Middlewares/Third_Party/FatFs/src/ff.c **** sz_buf = len / ss; /* Size of working buffer (sector) */ + 9852 .loc 1 5348 2 is_stmt 1 view .LVU3328 +5349:Middlewares/Third_Party/FatFs/src/ff.c **** szb_buf = sz_buf * ss; /* Size of working buffer (byte) */ + 9853 .loc 1 5349 2 view .LVU3329 +5349:Middlewares/Third_Party/FatFs/src/ff.c **** szb_buf = sz_buf * ss; /* Size of working buffer (byte) */ + 9854 .loc 1 5349 9 is_stmt 0 view .LVU3330 + 9855 00a8 189A ldr r2, [sp, #96] + 9856 00aa B2FBF3F9 udiv r9, r2, r3 + 9857 .LVL1145: +5350:Middlewares/Third_Party/FatFs/src/ff.c **** if (!szb_buf) return FR_MKFS_ABORTED; + 9858 .loc 1 5350 2 is_stmt 1 view .LVU3331 +5350:Middlewares/Third_Party/FatFs/src/ff.c **** if (!szb_buf) return FR_MKFS_ABORTED; + 9859 .loc 1 5350 10 is_stmt 0 view .LVU3332 + 9860 00ae 09FB03F3 mul r3, r9, r3 + 9861 00b2 0293 str r3, [sp, #8] + 9862 .LVL1146: +5351:Middlewares/Third_Party/FatFs/src/ff.c **** + 9863 .loc 1 5351 2 is_stmt 1 view .LVU3333 +5351:Middlewares/Third_Party/FatFs/src/ff.c **** + 9864 .loc 1 5351 5 is_stmt 0 view .LVU3334 + 9865 00b4 002B cmp r3, #0 + 9866 00b6 00F0BE82 beq .L747 +5354:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get partition information from partition table in the MBR */ + 9867 .loc 1 5354 2 is_stmt 1 view .LVU3335 + ARM GAS /tmp/cc2SVLkL.s page 330 + + +5364:Middlewares/Third_Party/FatFs/src/ff.c **** b_vol = (opt & FM_SFD) ? 0 : 63; /* Volume start sector */ + 9868 .loc 1 5364 3 view .LVU3336 +5364:Middlewares/Third_Party/FatFs/src/ff.c **** b_vol = (opt & FM_SFD) ? 0 : 63; /* Volume start sector */ + 9869 .loc 1 5364 7 is_stmt 0 view .LVU3337 + 9870 00ba 0BAA add r2, sp, #44 + 9871 00bc 0121 movs r1, #1 + 9872 00be 2046 mov r0, r4 + 9873 00c0 FFF7FEFF bl disk_ioctl + 9874 .LVL1147: +5364:Middlewares/Third_Party/FatFs/src/ff.c **** b_vol = (opt & FM_SFD) ? 0 : 63; /* Volume start sector */ + 9875 .loc 1 5364 6 discriminator 1 view .LVU3338 + 9876 00c4 0028 cmp r0, #0 + 9877 00c6 40F0B882 bne .L748 +5365:Middlewares/Third_Party/FatFs/src/ff.c **** if (sz_vol < b_vol) return FR_MKFS_ABORTED; + 9878 .loc 1 5365 3 is_stmt 1 view .LVU3339 +5365:Middlewares/Third_Party/FatFs/src/ff.c **** if (sz_vol < b_vol) return FR_MKFS_ABORTED; + 9879 .loc 1 5365 30 is_stmt 0 view .LVU3340 + 9880 00ca 17F00803 ands r3, r7, #8 + 9881 00ce 0393 str r3, [sp, #12] + 9882 00d0 22D0 beq .L749 +5365:Middlewares/Third_Party/FatFs/src/ff.c **** if (sz_vol < b_vol) return FR_MKFS_ABORTED; + 9883 .loc 1 5365 30 discriminator 1 view .LVU3341 + 9884 00d2 DDF804B0 ldr fp, [sp, #4] + 9885 .L701: + 9886 .LVL1148: +5366:Middlewares/Third_Party/FatFs/src/ff.c **** sz_vol -= b_vol; /* Volume size */ + 9887 .loc 1 5366 3 is_stmt 1 view .LVU3342 +5366:Middlewares/Third_Party/FatFs/src/ff.c **** sz_vol -= b_vol; /* Volume size */ + 9888 .loc 1 5366 14 is_stmt 0 view .LVU3343 + 9889 00d6 0B9A ldr r2, [sp, #44] +5366:Middlewares/Third_Party/FatFs/src/ff.c **** sz_vol -= b_vol; /* Volume size */ + 9890 .loc 1 5366 6 view .LVU3344 + 9891 00d8 5A45 cmp r2, fp + 9892 00da C0F0B082 bcc .L750 +5367:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9893 .loc 1 5367 3 is_stmt 1 view .LVU3345 +5367:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9894 .loc 1 5367 10 is_stmt 0 view .LVU3346 + 9895 00de A2EB0B02 sub r2, r2, fp + 9896 00e2 0B92 str r2, [sp, #44] +5369:Middlewares/Third_Party/FatFs/src/ff.c **** + 9897 .loc 1 5369 2 is_stmt 1 view .LVU3347 +5369:Middlewares/Third_Party/FatFs/src/ff.c **** + 9898 .loc 1 5369 5 is_stmt 0 view .LVU3348 + 9899 00e4 7F2A cmp r2, #127 + 9900 00e6 40F2B982 bls .L751 +5372:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_EXFAT && (opt & FM_EXFAT)) { /* exFAT possible? */ + 9901 .loc 1 5372 2 is_stmt 1 view .LVU3349 +5373:Middlewares/Third_Party/FatFs/src/ff.c **** if ((opt & FM_ANY) == FM_EXFAT || sz_vol >= 0x4000000 || au > 128) { /* exFAT only, vol >= 64Ms + 9902 .loc 1 5373 3 view .LVU3350 +5378:Middlewares/Third_Party/FatFs/src/ff.c **** if (opt & FM_FAT32) { /* FAT32 possible? */ + 9903 .loc 1 5378 3 view .LVU3351 +5378:Middlewares/Third_Party/FatFs/src/ff.c **** if (opt & FM_FAT32) { /* FAT32 possible? */ + 9904 .loc 1 5378 6 is_stmt 0 view .LVU3352 + 9905 00ea 802D cmp r5, #128 + 9906 00ec 00F2B882 bhi .L752 +5379:Middlewares/Third_Party/FatFs/src/ff.c **** if ((opt & FM_ANY) == FM_FAT32 || !(opt & FM_FAT)) { /* FAT32 only or no-FAT? */ + ARM GAS /tmp/cc2SVLkL.s page 331 + + + 9907 .loc 1 5379 3 is_stmt 1 view .LVU3353 +5379:Middlewares/Third_Party/FatFs/src/ff.c **** if ((opt & FM_ANY) == FM_FAT32 || !(opt & FM_FAT)) { /* FAT32 only or no-FAT? */ + 9908 .loc 1 5379 6 is_stmt 0 view .LVU3354 + 9909 00f0 17F00201 ands r1, r7, #2 + 9910 00f4 06D0 beq .L702 +5380:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = FS_FAT32; break; + 9911 .loc 1 5380 4 is_stmt 1 view .LVU3355 +5380:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = FS_FAT32; break; + 9912 .loc 1 5380 7 is_stmt 0 view .LVU3356 + 9913 00f6 07F00703 and r3, r7, #7 + 9914 00fa 022B cmp r3, #2 + 9915 00fc 0FD0 beq .L753 +5380:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = FS_FAT32; break; + 9916 .loc 1 5380 35 discriminator 1 view .LVU3357 + 9917 00fe 17F0010F tst r7, #1 + 9918 0102 12D0 beq .L754 + 9919 .L702: +5384:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = FS_FAT16; + 9920 .loc 1 5384 3 is_stmt 1 view .LVU3358 +5384:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = FS_FAT16; + 9921 .loc 1 5384 6 is_stmt 0 view .LVU3359 + 9922 0104 17F0010F tst r7, #1 + 9923 0108 00F0AC82 beq .L755 +5385:Middlewares/Third_Party/FatFs/src/ff.c **** } while (0); + 9924 .loc 1 5385 7 view .LVU3360 + 9925 010c 4FF0020A mov r10, #2 + 9926 0110 0494 str r4, [sp, #16] + 9927 0112 CDF81490 str r9, [sp, #20] + 9928 0116 6DE0 b .L704 + 9929 .LVL1149: + 9930 .L749: +5365:Middlewares/Third_Party/FatFs/src/ff.c **** if (sz_vol < b_vol) return FR_MKFS_ABORTED; + 9931 .loc 1 5365 30 discriminator 2 view .LVU3361 + 9932 0118 4FF03F0B mov fp, #63 + 9933 011c DBE7 b .L701 + 9934 .LVL1150: + 9935 .L753: +5381:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9936 .loc 1 5381 9 view .LVU3362 + 9937 011e 4FF0030A mov r10, #3 + 9938 0122 0494 str r4, [sp, #16] + 9939 0124 CDF81490 str r9, [sp, #20] + 9940 0128 64E0 b .L704 + 9941 .L754: +5381:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9942 .loc 1 5381 9 view .LVU3363 + 9943 012a 4FF0030A mov r10, #3 + 9944 012e 0494 str r4, [sp, #16] + 9945 0130 CDF81490 str r9, [sp, #20] + 9946 0134 5EE0 b .L704 + 9947 .LVL1151: + 9948 .L761: +5604:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9949 .loc 1 5604 10 view .LVU3364 + 9950 0136 1D46 mov r5, r3 + 9951 .LVL1152: +5604:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 332 + + + 9952 .loc 1 5604 10 view .LVU3365 + 9953 0138 5CE0 b .L704 + 9954 .LVL1153: + 9955 .L762: +5607:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9956 .loc 1 5607 11 view .LVU3366 + 9957 013a 4FF0030A mov r10, #3 + 9958 .LVL1154: +5607:Middlewares/Third_Party/FatFs/src/ff.c **** } + 9959 .loc 1 5607 11 view .LVU3367 + 9960 013e 59E0 b .L704 + 9961 .LVL1155: + 9962 .L782: +5556:Middlewares/Third_Party/FatFs/src/ff.c **** n = sz_vol / 0x20000; /* Volume size in unit of 128KS */ + 9963 .loc 1 5556 5 is_stmt 1 view .LVU3368 +5556:Middlewares/Third_Party/FatFs/src/ff.c **** n = sz_vol / 0x20000; /* Volume size in unit of 128KS */ + 9964 .loc 1 5556 8 is_stmt 0 view .LVU3369 + 9965 0140 ADB1 cbz r5, .L780 +5553:Middlewares/Third_Party/FatFs/src/ff.c **** /* Pre-determine number of clusters and FAT sub-type */ + 9966 .loc 1 5553 8 view .LVU3370 + 9967 0142 A846 mov r8, r5 + 9968 .LVL1156: + 9969 .L706: +5560:Middlewares/Third_Party/FatFs/src/ff.c **** sz_fat = (n_clst * 4 + 8 + ss - 1) / ss; /* FAT size [sector] */ + 9970 .loc 1 5560 5 is_stmt 1 view .LVU3371 +5560:Middlewares/Third_Party/FatFs/src/ff.c **** sz_fat = (n_clst * 4 + 8 + ss - 1) / ss; /* FAT size [sector] */ + 9971 .loc 1 5560 12 is_stmt 0 view .LVU3372 + 9972 0144 B2FBF8F0 udiv r0, r2, r8 + 9973 .LVL1157: +5561:Middlewares/Third_Party/FatFs/src/ff.c **** sz_rsv = 32; /* Number of reserved sectors */ + 9974 .loc 1 5561 5 is_stmt 1 view .LVU3373 +5561:Middlewares/Third_Party/FatFs/src/ff.c **** sz_rsv = 32; /* Number of reserved sectors */ + 9975 .loc 1 5561 26 is_stmt 0 view .LVU3374 + 9976 0148 831C adds r3, r0, #2 +5561:Middlewares/Third_Party/FatFs/src/ff.c **** sz_rsv = 32; /* Number of reserved sectors */ + 9977 .loc 1 5561 30 view .LVU3375 + 9978 014a BDF83640 ldrh r4, [sp, #54] + 9979 014e 04EB8303 add r3, r4, r3, lsl #2 +5561:Middlewares/Third_Party/FatFs/src/ff.c **** sz_rsv = 32; /* Number of reserved sectors */ + 9980 .loc 1 5561 35 view .LVU3376 + 9981 0152 013B subs r3, r3, #1 +5561:Middlewares/Third_Party/FatFs/src/ff.c **** sz_rsv = 32; /* Number of reserved sectors */ + 9982 .loc 1 5561 12 view .LVU3377 + 9983 0154 B3FBF4F3 udiv r3, r3, r4 + 9984 .LVL1158: +5562:Middlewares/Third_Party/FatFs/src/ff.c **** sz_dir = 0; /* No static directory */ + 9985 .loc 1 5562 5 is_stmt 1 view .LVU3378 +5563:Middlewares/Third_Party/FatFs/src/ff.c **** if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) return FR_MKFS_ABORTED; + 9986 .loc 1 5563 5 view .LVU3379 +5564:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* FAT12/16 volume */ + 9987 .loc 1 5564 5 view .LVU3380 +5564:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* FAT12/16 volume */ + 9988 .loc 1 5564 29 is_stmt 0 view .LVU3381 + 9989 0158 524C ldr r4, .L793+4 + 9990 015a 0444 add r4, r4, r0 +5564:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* FAT12/16 volume */ + 9991 .loc 1 5564 8 view .LVU3382 + ARM GAS /tmp/cc2SVLkL.s page 333 + + + 9992 015c 5248 ldr r0, .L793+8 + 9993 .LVL1159: +5564:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* FAT12/16 volume */ + 9994 .loc 1 5564 8 view .LVU3383 + 9995 015e 8442 cmp r4, r0 + 9996 0160 00F28282 bhi .L757 +5563:Middlewares/Third_Party/FatFs/src/ff.c **** if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) return FR_MKFS_ABORTED; + 9997 .loc 1 5563 12 view .LVU3384 + 9998 0164 DDF804C0 ldr ip, [sp, #4] +5562:Middlewares/Third_Party/FatFs/src/ff.c **** sz_dir = 0; /* No static directory */ + 9999 .loc 1 5562 12 view .LVU3385 + 10000 0168 4FF0200E mov lr, #32 + 10001 016c 5CE0 b .L709 + 10002 .LVL1160: + 10003 .L780: +5557:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ; /* Get from table */ + 10004 .loc 1 5557 6 is_stmt 1 view .LVU3386 +5557:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ; /* Get from table */ + 10005 .loc 1 5557 8 is_stmt 0 view .LVU3387 + 10006 016e 540C lsrs r4, r2, #17 + 10007 .LVL1161: +5558:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10008 .loc 1 5558 6 is_stmt 1 view .LVU3388 +5558:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10009 .loc 1 5558 13 is_stmt 0 view .LVU3389 + 10010 0170 2846 mov r0, r5 +5558:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10011 .loc 1 5558 22 view .LVU3390 + 10012 0172 4FF00108 mov r8, #1 +5558:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10013 .loc 1 5558 6 view .LVU3391 + 10014 0176 02E0 b .L707 + 10015 .LVL1162: + 10016 .L708: +5558:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10017 .loc 1 5558 57 is_stmt 1 discriminator 4 view .LVU3392 +5558:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10018 .loc 1 5558 55 is_stmt 0 discriminator 4 view .LVU3393 + 10019 0178 0130 adds r0, r0, #1 + 10020 .LVL1163: +5558:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10021 .loc 1 5558 63 discriminator 4 view .LVU3394 + 10022 017a 4FEA4808 lsl r8, r8, #1 + 10023 .LVL1164: + 10024 .L707: +5558:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10025 .loc 1 5558 36 is_stmt 1 discriminator 1 view .LVU3395 +5558:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10026 .loc 1 5558 32 is_stmt 0 discriminator 1 view .LVU3396 + 10027 017e 4B4B ldr r3, .L793+12 + 10028 0180 33F81030 ldrh r3, [r3, r0, lsl #1] +5558:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10029 .loc 1 5558 36 discriminator 1 view .LVU3397 + 10030 0184 002B cmp r3, #0 + 10031 0186 DDD0 beq .L706 +5558:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10032 .loc 1 5558 36 discriminator 3 view .LVU3398 + ARM GAS /tmp/cc2SVLkL.s page 334 + + + 10033 0188 A342 cmp r3, r4 + 10034 018a F5D9 bls .L708 + 10035 018c DAE7 b .L706 + 10036 .LVL1165: + 10037 .L783: +5567:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ; /* Get from table */ + 10038 .loc 1 5567 6 is_stmt 1 view .LVU3399 +5567:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ; /* Get from table */ + 10039 .loc 1 5567 8 is_stmt 0 view .LVU3400 + 10040 018e 140B lsrs r4, r2, #12 + 10041 .LVL1166: +5568:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10042 .loc 1 5568 6 is_stmt 1 view .LVU3401 +5568:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10043 .loc 1 5568 13 is_stmt 0 view .LVU3402 + 10044 0190 2846 mov r0, r5 +5568:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10045 .loc 1 5568 22 view .LVU3403 + 10046 0192 4FF00108 mov r8, #1 +5568:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10047 .loc 1 5568 6 view .LVU3404 + 10048 0196 02E0 b .L711 + 10049 .LVL1167: + 10050 .L712: +5568:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10051 .loc 1 5568 53 is_stmt 1 discriminator 4 view .LVU3405 +5568:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10052 .loc 1 5568 51 is_stmt 0 discriminator 4 view .LVU3406 + 10053 0198 0130 adds r0, r0, #1 + 10054 .LVL1168: +5568:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10055 .loc 1 5568 59 discriminator 4 view .LVU3407 + 10056 019a 4FEA4808 lsl r8, r8, #1 + 10057 .LVL1169: + 10058 .L711: +5568:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10059 .loc 1 5568 34 is_stmt 1 discriminator 1 view .LVU3408 +5568:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10060 .loc 1 5568 30 is_stmt 0 discriminator 1 view .LVU3409 + 10061 019e 444B ldr r3, .L793+16 + 10062 01a0 33F81030 ldrh r3, [r3, r0, lsl #1] +5568:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10063 .loc 1 5568 34 discriminator 1 view .LVU3410 + 10064 01a4 63B3 cbz r3, .L710 +5568:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10065 .loc 1 5568 34 discriminator 3 view .LVU3411 + 10066 01a6 A342 cmp r3, r4 + 10067 01a8 F6D9 bls .L712 + 10068 01aa 29E0 b .L710 + 10069 .LVL1170: + 10070 .L713: +5574:Middlewares/Third_Party/FatFs/src/ff.c **** n = (n_clst * 3 + 1) / 2 + 3; /* FAT size [byte] */ + 10071 .loc 1 5574 6 is_stmt 1 view .LVU3412 +5575:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10072 .loc 1 5575 6 view .LVU3413 +5575:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10073 .loc 1 5575 18 is_stmt 0 view .LVU3414 + ARM GAS /tmp/cc2SVLkL.s page 335 + + + 10074 01ac 03EB4303 add r3, r3, r3, lsl #1 + 10075 .LVL1171: +5575:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10076 .loc 1 5575 22 view .LVU3415 + 10077 01b0 0133 adds r3, r3, #1 +5575:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10078 .loc 1 5575 27 view .LVU3416 + 10079 01b2 5B08 lsrs r3, r3, #1 +5575:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10080 .loc 1 5575 8 view .LVU3417 + 10081 01b4 0333 adds r3, r3, #3 + 10082 .LVL1172: +5574:Middlewares/Third_Party/FatFs/src/ff.c **** n = (n_clst * 3 + 1) / 2 + 3; /* FAT size [byte] */ + 10083 .loc 1 5574 10 view .LVU3418 + 10084 01b6 4FF0010A mov r10, #1 + 10085 01ba 29E0 b .L714 + 10086 .LVL1173: + 10087 .L784: +5587:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* FAT12/16: Expand FAT size */ + 10088 .loc 1 5587 5 is_stmt 1 view .LVU3419 +5587:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* FAT12/16: Expand FAT size */ + 10089 .loc 1 5587 12 is_stmt 0 view .LVU3420 + 10090 01bc A644 add lr, lr, r4 + 10091 .LVL1174: +5587:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* FAT12/16: Expand FAT size */ + 10092 .loc 1 5587 18 is_stmt 1 view .LVU3421 +5587:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* FAT12/16: Expand FAT size */ + 10093 .loc 1 5587 24 is_stmt 0 view .LVU3422 + 10094 01be A144 add r9, r9, r4 + 10095 .LVL1175: +5587:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* FAT12/16: Expand FAT size */ + 10096 .loc 1 5587 24 view .LVU3423 + 10097 01c0 41E0 b .L716 + 10098 .LVL1176: + 10099 .L785: +5596:Middlewares/Third_Party/FatFs/src/ff.c **** if (!au && (au = pau / 2) != 0) continue; /* Adjust cluster size and retry */ + 10100 .loc 1 5596 5 is_stmt 1 view .LVU3424 +5596:Middlewares/Third_Party/FatFs/src/ff.c **** if (!au && (au = pau / 2) != 0) continue; /* Adjust cluster size and retry */ + 10101 .loc 1 5596 8 is_stmt 0 view .LVU3425 + 10102 01c2 4FF6F574 movw r4, #65525 + 10103 .LVL1177: +5596:Middlewares/Third_Party/FatFs/src/ff.c **** if (!au && (au = pau / 2) != 0) continue; /* Adjust cluster size and retry */ + 10104 .loc 1 5596 8 view .LVU3426 + 10105 01c6 A042 cmp r0, r4 + 10106 01c8 4ED8 bhi .L717 +5597:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_MKFS_ABORTED; + 10107 .loc 1 5597 6 is_stmt 1 view .LVU3427 +5597:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_MKFS_ABORTED; + 10108 .loc 1 5597 9 is_stmt 0 view .LVU3428 + 10109 01ca 002D cmp r5, #0 + 10110 01cc 40F05082 bne .L760 +5597:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_MKFS_ABORTED; + 10111 .loc 1 5597 21 discriminator 1 view .LVU3429 + 10112 01d0 4FEA5805 lsr r5, r8, #1 + 10113 .LVL1178: +5597:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_MKFS_ABORTED; + 10114 .loc 1 5597 14 discriminator 1 view .LVU3430 + ARM GAS /tmp/cc2SVLkL.s page 336 + + + 10115 01d4 B8F1010F cmp r8, #1 + 10116 01d8 0CD8 bhi .L704 +5598:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10117 .loc 1 5598 13 view .LVU3431 + 10118 01da 0E20 movs r0, #14 + 10119 .LVL1179: +5598:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10120 .loc 1 5598 13 view .LVU3432 + 10121 01dc 1CE2 b .L696 + 10122 .LVL1180: + 10123 .L720: +5612:Middlewares/Third_Party/FatFs/src/ff.c **** if (!au && (au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */ + 10124 .loc 1 5612 5 is_stmt 1 view .LVU3433 +5612:Middlewares/Third_Party/FatFs/src/ff.c **** if (!au && (au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */ + 10125 .loc 1 5612 9 is_stmt 0 view .LVU3434 + 10126 01de 40F6F574 movw r4, #4085 + 10127 01e2 A042 cmp r0, r4 + 10128 01e4 66D8 bhi .L719 +5613:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_MKFS_ABORTED; + 10129 .loc 1 5613 6 is_stmt 1 view .LVU3435 +5613:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_MKFS_ABORTED; + 10130 .loc 1 5613 9 is_stmt 0 view .LVU3436 + 10131 01e6 002D cmp r5, #0 + 10132 01e8 40F04682 bne .L764 +5613:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_MKFS_ABORTED; + 10133 .loc 1 5613 21 discriminator 1 view .LVU3437 + 10134 01ec 4FEA4805 lsl r5, r8, #1 + 10135 .LVL1181: +5613:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_MKFS_ABORTED; + 10136 .loc 1 5613 14 discriminator 1 view .LVU3438 + 10137 01f0 802D cmp r5, #128 + 10138 01f2 52D8 bhi .L781 + 10139 .LVL1182: + 10140 .L704: +5372:Middlewares/Third_Party/FatFs/src/ff.c **** if (_FS_EXFAT && (opt & FM_EXFAT)) { /* exFAT possible? */ + 10141 .loc 1 5372 5 is_stmt 1 view .LVU3439 +5552:Middlewares/Third_Party/FatFs/src/ff.c **** pau = au; + 10142 .loc 1 5552 3 view .LVU3440 +5553:Middlewares/Third_Party/FatFs/src/ff.c **** /* Pre-determine number of clusters and FAT sub-type */ + 10143 .loc 1 5553 4 view .LVU3441 +5555:Middlewares/Third_Party/FatFs/src/ff.c **** if (!pau) { /* au auto-selection */ + 10144 .loc 1 5555 4 view .LVU3442 +5555:Middlewares/Third_Party/FatFs/src/ff.c **** if (!pau) { /* au auto-selection */ + 10145 .loc 1 5555 7 is_stmt 0 view .LVU3443 + 10146 01f4 BAF1030F cmp r10, #3 + 10147 01f8 A2D0 beq .L782 +5566:Middlewares/Third_Party/FatFs/src/ff.c **** n = sz_vol / 0x1000; /* Volume size in unit of 4KS */ + 10148 .loc 1 5566 5 is_stmt 1 view .LVU3444 +5566:Middlewares/Third_Party/FatFs/src/ff.c **** n = sz_vol / 0x1000; /* Volume size in unit of 4KS */ + 10149 .loc 1 5566 8 is_stmt 0 view .LVU3445 + 10150 01fa 002D cmp r5, #0 + 10151 01fc C7D0 beq .L783 +5553:Middlewares/Third_Party/FatFs/src/ff.c **** /* Pre-determine number of clusters and FAT sub-type */ + 10152 .loc 1 5553 8 view .LVU3446 + 10153 01fe A846 mov r8, r5 + 10154 .LVL1183: + 10155 .L710: + ARM GAS /tmp/cc2SVLkL.s page 337 + + +5570:Middlewares/Third_Party/FatFs/src/ff.c **** if (n_clst > MAX_FAT12) { + 10156 .loc 1 5570 5 is_stmt 1 view .LVU3447 +5570:Middlewares/Third_Party/FatFs/src/ff.c **** if (n_clst > MAX_FAT12) { + 10157 .loc 1 5570 12 is_stmt 0 view .LVU3448 + 10158 0200 B2FBF8F3 udiv r3, r2, r8 + 10159 .LVL1184: +5571:Middlewares/Third_Party/FatFs/src/ff.c **** n = n_clst * 2 + 4; /* FAT size [byte] */ + 10160 .loc 1 5571 5 is_stmt 1 view .LVU3449 +5571:Middlewares/Third_Party/FatFs/src/ff.c **** n = n_clst * 2 + 4; /* FAT size [byte] */ + 10161 .loc 1 5571 8 is_stmt 0 view .LVU3450 + 10162 0204 40F6F570 movw r0, #4085 + 10163 0208 8342 cmp r3, r0 + 10164 020a CFD9 bls .L713 +5572:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 10165 .loc 1 5572 6 is_stmt 1 view .LVU3451 +5572:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 10166 .loc 1 5572 21 is_stmt 0 view .LVU3452 + 10167 020c 0233 adds r3, r3, #2 + 10168 .LVL1185: +5572:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 10169 .loc 1 5572 8 view .LVU3453 + 10170 020e 5B00 lsls r3, r3, #1 + 10171 .LVL1186: + 10172 .L714: +5577:Middlewares/Third_Party/FatFs/src/ff.c **** sz_rsv = 1; /* Number of reserved sectors */ + 10173 .loc 1 5577 5 is_stmt 1 view .LVU3454 +5577:Middlewares/Third_Party/FatFs/src/ff.c **** sz_rsv = 1; /* Number of reserved sectors */ + 10174 .loc 1 5577 17 is_stmt 0 view .LVU3455 + 10175 0210 BDF83600 ldrh r0, [sp, #54] + 10176 0214 0344 add r3, r3, r0 + 10177 .LVL1187: +5577:Middlewares/Third_Party/FatFs/src/ff.c **** sz_rsv = 1; /* Number of reserved sectors */ + 10178 .loc 1 5577 22 view .LVU3456 + 10179 0216 013B subs r3, r3, #1 +5577:Middlewares/Third_Party/FatFs/src/ff.c **** sz_rsv = 1; /* Number of reserved sectors */ + 10180 .loc 1 5577 12 view .LVU3457 + 10181 0218 B3FBF0F3 udiv r3, r3, r0 + 10182 .LVL1188: +5578:Middlewares/Third_Party/FatFs/src/ff.c **** sz_dir = (DWORD)n_rootdir * SZDIRE / ss; /* Rootdir size [sector] */ + 10183 .loc 1 5578 5 is_stmt 1 view .LVU3458 +5579:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10184 .loc 1 5579 5 view .LVU3459 +5579:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10185 .loc 1 5579 12 is_stmt 0 view .LVU3460 + 10186 021c 4FF4804C mov ip, #16384 + 10187 0220 BCFBF0FC udiv ip, ip, r0 + 10188 .LVL1189: +5578:Middlewares/Third_Party/FatFs/src/ff.c **** sz_dir = (DWORD)n_rootdir * SZDIRE / ss; /* Rootdir size [sector] */ + 10189 .loc 1 5578 12 view .LVU3461 + 10190 0224 4FF0010E mov lr, #1 + 10191 .LVL1190: + 10192 .L709: +5581:Middlewares/Third_Party/FatFs/src/ff.c **** b_data = b_fat + sz_fat * n_fats + sz_dir; /* Data base */ + 10193 .loc 1 5581 4 is_stmt 1 view .LVU3462 +5581:Middlewares/Third_Party/FatFs/src/ff.c **** b_data = b_fat + sz_fat * n_fats + sz_dir; /* Data base */ + 10194 .loc 1 5581 10 is_stmt 0 view .LVU3463 + 10195 0228 0EEB0B09 add r9, lr, fp + ARM GAS /tmp/cc2SVLkL.s page 338 + + + 10196 .LVL1191: +5582:Middlewares/Third_Party/FatFs/src/ff.c **** + 10197 .loc 1 5582 4 is_stmt 1 view .LVU3464 +5582:Middlewares/Third_Party/FatFs/src/ff.c **** + 10198 .loc 1 5582 19 is_stmt 0 view .LVU3465 + 10199 022c 03EB0900 add r0, r3, r9 +5582:Middlewares/Third_Party/FatFs/src/ff.c **** + 10200 .loc 1 5582 11 view .LVU3466 + 10201 0230 6044 add r0, r0, ip + 10202 .LVL1192: +5585:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { /* FAT32: Move FAT base */ + 10203 .loc 1 5585 4 is_stmt 1 view .LVU3467 +5585:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { /* FAT32: Move FAT base */ + 10204 .loc 1 5585 17 is_stmt 0 view .LVU3468 + 10205 0232 0C9F ldr r7, [sp, #48] + 10206 0234 3C18 adds r4, r7, r0 +5585:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { /* FAT32: Move FAT base */ + 10207 .loc 1 5585 26 view .LVU3469 + 10208 0236 013C subs r4, r4, #1 +5585:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { /* FAT32: Move FAT base */ + 10209 .loc 1 5585 33 view .LVU3470 + 10210 0238 7F42 rsbs r7, r7, #0 +5585:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { /* FAT32: Move FAT base */ + 10211 .loc 1 5585 31 view .LVU3471 + 10212 023a 3C40 ands r4, r4, r7 +5585:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { /* FAT32: Move FAT base */ + 10213 .loc 1 5585 6 view .LVU3472 + 10214 023c 241A subs r4, r4, r0 + 10215 .LVL1193: +5586:Middlewares/Third_Party/FatFs/src/ff.c **** sz_rsv += n; b_fat += n; + 10216 .loc 1 5586 4 is_stmt 1 view .LVU3473 +5586:Middlewares/Third_Party/FatFs/src/ff.c **** sz_rsv += n; b_fat += n; + 10217 .loc 1 5586 7 is_stmt 0 view .LVU3474 + 10218 023e BAF1030F cmp r10, #3 + 10219 0242 BBD0 beq .L784 +5589:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10220 .loc 1 5589 5 is_stmt 1 view .LVU3475 +5589:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10221 .loc 1 5589 12 is_stmt 0 view .LVU3476 + 10222 0244 2344 add r3, r3, r4 + 10223 .LVL1194: + 10224 .L716: +5593:Middlewares/Third_Party/FatFs/src/ff.c **** n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau; + 10225 .loc 1 5593 4 is_stmt 1 view .LVU3477 +5593:Middlewares/Third_Party/FatFs/src/ff.c **** n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau; + 10226 .loc 1 5593 24 is_stmt 0 view .LVU3478 + 10227 0246 00EB0810 add r0, r0, r8, lsl #4 + 10228 .LVL1195: +5593:Middlewares/Third_Party/FatFs/src/ff.c **** n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau; + 10229 .loc 1 5593 35 view .LVU3479 + 10230 024a A0EB0B00 sub r0, r0, fp +5593:Middlewares/Third_Party/FatFs/src/ff.c **** n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau; + 10231 .loc 1 5593 7 view .LVU3480 + 10232 024e 8242 cmp r2, r0 + 10233 0250 C0F00C82 bcc .L759 +5594:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { + 10234 .loc 1 5594 4 is_stmt 1 view .LVU3481 + ARM GAS /tmp/cc2SVLkL.s page 339 + + +5594:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { + 10235 .loc 1 5594 21 is_stmt 0 view .LVU3482 + 10236 0254 A2EB0E00 sub r0, r2, lr +5594:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { + 10237 .loc 1 5594 30 view .LVU3483 + 10238 0258 C01A subs r0, r0, r3 +5594:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { + 10239 .loc 1 5594 48 view .LVU3484 + 10240 025a A0EB0C00 sub r0, r0, ip +5594:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { + 10241 .loc 1 5594 11 view .LVU3485 + 10242 025e B0FBF8F0 udiv r0, r0, r8 + 10243 .LVL1196: +5595:Middlewares/Third_Party/FatFs/src/ff.c **** if (n_clst <= MAX_FAT16) { /* Too few clusters for FAT32 */ + 10244 .loc 1 5595 4 is_stmt 1 view .LVU3486 +5595:Middlewares/Third_Party/FatFs/src/ff.c **** if (n_clst <= MAX_FAT16) { /* Too few clusters for FAT32 */ + 10245 .loc 1 5595 7 is_stmt 0 view .LVU3487 + 10246 0262 BAF1030F cmp r10, #3 + 10247 0266 ACD0 beq .L785 + 10248 .LVL1197: + 10249 .L717: +5601:Middlewares/Third_Party/FatFs/src/ff.c **** if (n_clst > MAX_FAT16) { /* Too many clusters for FAT16 */ + 10250 .loc 1 5601 4 is_stmt 1 view .LVU3488 +5601:Middlewares/Third_Party/FatFs/src/ff.c **** if (n_clst > MAX_FAT16) { /* Too many clusters for FAT16 */ + 10251 .loc 1 5601 7 is_stmt 0 view .LVU3489 + 10252 0268 BAF1020F cmp r10, #2 + 10253 026c 22D1 bne .L719 +5602:Middlewares/Third_Party/FatFs/src/ff.c **** if (!au && (pau * 2) <= 64) { + 10254 .loc 1 5602 5 is_stmt 1 view .LVU3490 +5602:Middlewares/Third_Party/FatFs/src/ff.c **** if (!au && (pau * 2) <= 64) { + 10255 .loc 1 5602 8 is_stmt 0 view .LVU3491 + 10256 026e 4FF6F574 movw r4, #65525 + 10257 0272 A042 cmp r0, r4 + 10258 0274 B3D9 bls .L720 +5603:Middlewares/Third_Party/FatFs/src/ff.c **** au = pau * 2; continue; /* Adjust cluster size and retry */ + 10259 .loc 1 5603 6 is_stmt 1 view .LVU3492 +5603:Middlewares/Third_Party/FatFs/src/ff.c **** au = pau * 2; continue; /* Adjust cluster size and retry */ + 10260 .loc 1 5603 9 is_stmt 0 view .LVU3493 + 10261 0276 25B9 cbnz r5, .L721 +5603:Middlewares/Third_Party/FatFs/src/ff.c **** au = pau * 2; continue; /* Adjust cluster size and retry */ + 10262 .loc 1 5603 22 discriminator 1 view .LVU3494 + 10263 0278 4FEA4803 lsl r3, r8, #1 + 10264 .LVL1198: +5603:Middlewares/Third_Party/FatFs/src/ff.c **** au = pau * 2; continue; /* Adjust cluster size and retry */ + 10265 .loc 1 5603 14 discriminator 1 view .LVU3495 + 10266 027c 402B cmp r3, #64 + 10267 027e 7FF65AAF bls .L761 + 10268 .L721: +5606:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = FS_FAT32; continue; /* Switch type to FAT32 and retry */ + 10269 .loc 1 5606 6 is_stmt 1 view .LVU3496 +5606:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = FS_FAT32; continue; /* Switch type to FAT32 and retry */ + 10270 .loc 1 5606 9 is_stmt 0 view .LVU3497 + 10271 0282 0029 cmp r1, #0 + 10272 0284 7FF459AF bne .L762 +5609:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_MKFS_ABORTED; + 10273 .loc 1 5609 6 is_stmt 1 view .LVU3498 +5609:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_MKFS_ABORTED; + ARM GAS /tmp/cc2SVLkL.s page 340 + + + 10274 .loc 1 5609 9 is_stmt 0 view .LVU3499 + 10275 0288 002D cmp r5, #0 + 10276 028a 40F0F381 bne .L763 +5609:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_MKFS_ABORTED; + 10277 .loc 1 5609 21 discriminator 1 view .LVU3500 + 10278 028e 4FEA4805 lsl r5, r8, #1 + 10279 .LVL1199: +5609:Middlewares/Third_Party/FatFs/src/ff.c **** return FR_MKFS_ABORTED; + 10280 .loc 1 5609 14 discriminator 1 view .LVU3501 + 10281 0292 802D cmp r5, #128 + 10282 0294 AED9 bls .L704 +5610:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10283 .loc 1 5610 13 view .LVU3502 + 10284 0296 0E20 movs r0, #14 + 10285 .LVL1200: +5610:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10286 .loc 1 5610 13 view .LVU3503 + 10287 0298 BEE1 b .L696 + 10288 .LVL1201: + 10289 .L781: +5614:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10290 .loc 1 5614 13 view .LVU3504 + 10291 029a 0E20 movs r0, #14 + 10292 .LVL1202: +5614:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10293 .loc 1 5614 13 view .LVU3505 + 10294 029c BCE1 b .L696 + 10295 .L794: + 10296 029e 00BF .align 2 + 10297 .L793: + 10298 02a0 00000000 .word FatFs + 10299 02a4 0A00FFFF .word -65526 + 10300 02a8 FFFFFE0F .word 268369919 + 10301 02ac 00000000 .word cst32.1 + 10302 02b0 00000000 .word cst.0 + 10303 .LVL1203: + 10304 .L719: +5617:Middlewares/Third_Party/FatFs/src/ff.c **** + 10305 .loc 1 5617 24 view .LVU3506 + 10306 02b4 CDF820C0 str ip, [sp, #32] + 10307 02b8 7746 mov r7, lr + 10308 02ba 0793 str r3, [sp, #28] + 10309 02bc CDF81890 str r9, [sp, #24] + 10310 02c0 049C ldr r4, [sp, #16] + 10311 02c2 DDF81490 ldr r9, [sp, #20] + 10312 .LVL1204: +5617:Middlewares/Third_Party/FatFs/src/ff.c **** + 10313 .loc 1 5617 24 view .LVU3507 + 10314 02c6 0546 mov r5, r0 + 10315 .LVL1205: +5617:Middlewares/Third_Party/FatFs/src/ff.c **** + 10316 .loc 1 5617 4 is_stmt 1 view .LVU3508 +5617:Middlewares/Third_Party/FatFs/src/ff.c **** + 10317 .loc 1 5617 24 is_stmt 0 view .LVU3509 + 10318 02c8 40F6F572 movw r2, #4085 + 10319 02cc BAF1010F cmp r10, #1 + 10320 02d0 14BF ite ne + ARM GAS /tmp/cc2SVLkL.s page 341 + + + 10321 02d2 0023 movne r3, #0 + 10322 .LVL1206: +5617:Middlewares/Third_Party/FatFs/src/ff.c **** + 10323 .loc 1 5617 24 view .LVU3510 + 10324 02d4 0123 moveq r3, #1 + 10325 02d6 9042 cmp r0, r2 + 10326 02d8 98BF it ls + 10327 02da 0023 movls r3, #0 +5617:Middlewares/Third_Party/FatFs/src/ff.c **** + 10328 .loc 1 5617 7 view .LVU3511 + 10329 02dc 002B cmp r3, #0 + 10330 02de 40F0CD81 bne .L765 + 10331 .LVL1207: +5620:Middlewares/Third_Party/FatFs/src/ff.c **** } while (1); + 10332 .loc 1 5620 4 is_stmt 1 view .LVU3512 +5628:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code (x86), OEM name */ + 10333 .loc 1 5628 3 view .LVU3513 + 10334 02e2 BDF83620 ldrh r2, [sp, #54] + 10335 02e6 0021 movs r1, #0 + 10336 02e8 3046 mov r0, r6 + 10337 .LVL1208: +5628:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code (x86), OEM name */ + 10338 .loc 1 5628 3 is_stmt 0 view .LVU3514 + 10339 02ea FFF7FEFF bl mem_set + 10340 .LVL1209: +5629:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_BytsPerSec, ss); /* Sector size [byte] */ + 10341 .loc 1 5629 3 is_stmt 1 view .LVU3515 + 10342 02ee 0B22 movs r2, #11 + 10343 02f0 D449 ldr r1, .L795 + 10344 02f2 3046 mov r0, r6 + 10345 02f4 FFF7FEFF bl mem_cpy + 10346 .LVL1210: +5630:Middlewares/Third_Party/FatFs/src/ff.c **** buf[BPB_SecPerClus] = (BYTE)pau; /* Cluster size [sector] */ + 10347 .loc 1 5630 3 view .LVU3516 + 10348 02f8 BDF83610 ldrh r1, [sp, #54] + 10349 02fc 06F10B00 add r0, r6, #11 + 10350 0300 FFF7FEFF bl st_word + 10351 .LVL1211: +5631:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv); /* Size of reserved area */ + 10352 .loc 1 5631 3 view .LVU3517 +5631:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv); /* Size of reserved area */ + 10353 .loc 1 5631 23 is_stmt 0 view .LVU3518 + 10354 0304 86F80D80 strb r8, [r6, #13] +5632:Middlewares/Third_Party/FatFs/src/ff.c **** buf[BPB_NumFATs] = (BYTE)n_fats; /* Number of FATs */ + 10355 .loc 1 5632 3 is_stmt 1 view .LVU3519 + 10356 0308 B9B2 uxth r1, r7 + 10357 030a 06F10E00 add r0, r6, #14 + 10358 030e FFF7FEFF bl st_word + 10359 .LVL1212: +5633:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_RootEntCnt, (WORD)((fmt == FS_FAT32) ? 0 : n_rootdir)); /* Number of root direc + 10360 .loc 1 5633 3 view .LVU3520 +5633:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_RootEntCnt, (WORD)((fmt == FS_FAT32) ? 0 : n_rootdir)); /* Number of root direc + 10361 .loc 1 5633 20 is_stmt 0 view .LVU3521 + 10362 0312 0123 movs r3, #1 + 10363 0314 3374 strb r3, [r6, #16] +5634:Middlewares/Third_Party/FatFs/src/ff.c **** if (sz_vol < 0x10000) { + 10364 .loc 1 5634 3 is_stmt 1 view .LVU3522 + ARM GAS /tmp/cc2SVLkL.s page 342 + + + 10365 0316 06F11100 add r0, r6, #17 + 10366 031a BAF1030F cmp r10, #3 + 10367 031e 00F08680 beq .L786 +5634:Middlewares/Third_Party/FatFs/src/ff.c **** if (sz_vol < 0x10000) { + 10368 .loc 1 5634 3 is_stmt 0 discriminator 2 view .LVU3523 + 10369 0322 4FF40071 mov r1, #512 + 10370 .L722: +5634:Middlewares/Third_Party/FatFs/src/ff.c **** if (sz_vol < 0x10000) { + 10371 .loc 1 5634 3 discriminator 4 view .LVU3524 + 10372 0326 FFF7FEFF bl st_word + 10373 .LVL1213: +5635:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_TotSec16, (WORD)sz_vol); /* Volume size in 16-bit LBA */ + 10374 .loc 1 5635 3 is_stmt 1 view .LVU3525 +5635:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_TotSec16, (WORD)sz_vol); /* Volume size in 16-bit LBA */ + 10375 .loc 1 5635 14 is_stmt 0 view .LVU3526 + 10376 032a 0B99 ldr r1, [sp, #44] +5635:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_TotSec16, (WORD)sz_vol); /* Volume size in 16-bit LBA */ + 10377 .loc 1 5635 6 view .LVU3527 + 10378 032c B1F5803F cmp r1, #65536 + 10379 0330 7FD2 bcs .L723 +5636:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 10380 .loc 1 5636 4 is_stmt 1 view .LVU3528 + 10381 0332 89B2 uxth r1, r1 + 10382 0334 06F11300 add r0, r6, #19 + 10383 0338 FFF7FEFF bl st_word + 10384 .LVL1214: + 10385 .L724: +5640:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_SecPerTrk, 63); /* Number of sectors per track (for int13) */ + 10386 .loc 1 5640 3 view .LVU3529 +5640:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_SecPerTrk, 63); /* Number of sectors per track (for int13) */ + 10387 .loc 1 5640 18 is_stmt 0 view .LVU3530 + 10388 033c F823 movs r3, #248 + 10389 033e 7375 strb r3, [r6, #21] +5641:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_NumHeads, 255); /* Number of heads (for int13) */ + 10390 .loc 1 5641 3 is_stmt 1 view .LVU3531 + 10391 0340 3F21 movs r1, #63 + 10392 0342 06F11800 add r0, r6, #24 + 10393 0346 FFF7FEFF bl st_word + 10394 .LVL1215: +5642:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BPB_HiddSec, b_vol); /* Volume offset in the physical drive [sector] */ + 10395 .loc 1 5642 3 view .LVU3532 + 10396 034a FF21 movs r1, #255 + 10397 034c 06F11A00 add r0, r6, #26 + 10398 0350 FFF7FEFF bl st_word + 10399 .LVL1216: +5643:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { + 10400 .loc 1 5643 3 view .LVU3533 + 10401 0354 5946 mov r1, fp + 10402 0356 06F11C00 add r0, r6, #28 + 10403 035a FFF7FEFF bl st_dword + 10404 .LVL1217: +5644:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BS_VolID32, GET_FATTIME()); /* VSN */ + 10405 .loc 1 5644 3 view .LVU3534 +5644:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BS_VolID32, GET_FATTIME()); /* VSN */ + 10406 .loc 1 5644 6 is_stmt 0 view .LVU3535 + 10407 035e BAF1030F cmp r10, #3 + 10408 0362 6BD0 beq .L787 + ARM GAS /tmp/cc2SVLkL.s page 343 + + +5654:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_FATSz16, (WORD)sz_fat); /* FAT size [sector] */ + 10409 .loc 1 5654 4 is_stmt 1 view .LVU3536 + 10410 0364 FFF7FEFF bl get_fattime + 10411 .LVL1218: + 10412 0368 0146 mov r1, r0 +5654:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_FATSz16, (WORD)sz_fat); /* FAT size [sector] */ + 10413 .loc 1 5654 4 is_stmt 0 discriminator 1 view .LVU3537 + 10414 036a 06F12700 add r0, r6, #39 + 10415 036e FFF7FEFF bl st_dword + 10416 .LVL1219: +5655:Middlewares/Third_Party/FatFs/src/ff.c **** buf[BS_DrvNum] = 0x80; /* Drive number (for int13) */ + 10417 .loc 1 5655 4 is_stmt 1 view .LVU3538 + 10418 0372 BDF81C10 ldrh r1, [sp, #28] + 10419 0376 06F11600 add r0, r6, #22 + 10420 037a FFF7FEFF bl st_word + 10421 .LVL1220: +5656:Middlewares/Third_Party/FatFs/src/ff.c **** buf[BS_BootSig] = 0x29; /* Extended boot signature */ + 10422 .loc 1 5656 4 view .LVU3539 +5656:Middlewares/Third_Party/FatFs/src/ff.c **** buf[BS_BootSig] = 0x29; /* Extended boot signature */ + 10423 .loc 1 5656 19 is_stmt 0 view .LVU3540 + 10424 037e 8023 movs r3, #128 + 10425 0380 86F82430 strb r3, [r6, #36] +5657:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(buf + BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ + 10426 .loc 1 5657 4 is_stmt 1 view .LVU3541 +5657:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(buf + BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ + 10427 .loc 1 5657 20 is_stmt 0 view .LVU3542 + 10428 0384 2923 movs r3, #41 + 10429 0386 86F82630 strb r3, [r6, #38] +5658:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10430 .loc 1 5658 4 is_stmt 1 view .LVU3543 + 10431 038a 1322 movs r2, #19 + 10432 038c AE49 ldr r1, .L795+4 + 10433 038e 06F12B00 add r0, r6, #43 + 10434 0392 FFF7FEFF bl mem_cpy + 10435 .LVL1221: + 10436 .L726: +5660:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) return FR_DISK_ERR; /* Write it to the VBR sector + 10437 .loc 1 5660 3 view .LVU3544 + 10438 0396 06F5FF77 add r7, r6, #510 + 10439 .LVL1222: +5660:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) return FR_DISK_ERR; /* Write it to the VBR sector + 10440 .loc 1 5660 3 is_stmt 0 view .LVU3545 + 10441 039a 4AF65521 movw r1, #43605 + 10442 039e 3846 mov r0, r7 + 10443 03a0 FFF7FEFF bl st_word + 10444 .LVL1223: +5661:Middlewares/Third_Party/FatFs/src/ff.c **** + 10445 .loc 1 5661 3 is_stmt 1 view .LVU3546 +5661:Middlewares/Third_Party/FatFs/src/ff.c **** + 10446 .loc 1 5661 7 is_stmt 0 view .LVU3547 + 10447 03a4 0123 movs r3, #1 + 10448 03a6 5A46 mov r2, fp + 10449 03a8 3146 mov r1, r6 + 10450 03aa 2046 mov r0, r4 + 10451 03ac FFF7FEFF bl disk_write + 10452 .LVL1224: +5661:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 344 + + + 10453 .loc 1 5661 6 discriminator 1 view .LVU3548 + 10454 03b0 0028 cmp r0, #0 + 10455 03b2 40F06581 bne .L767 +5664:Middlewares/Third_Party/FatFs/src/ff.c **** disk_write(pdrv, buf, b_vol + 6, 1); /* Write backup VBR (VBR + 6) */ + 10456 .loc 1 5664 3 is_stmt 1 view .LVU3549 +5664:Middlewares/Third_Party/FatFs/src/ff.c **** disk_write(pdrv, buf, b_vol + 6, 1); /* Write backup VBR (VBR + 6) */ + 10457 .loc 1 5664 6 is_stmt 0 view .LVU3550 + 10458 03b6 BAF1030F cmp r10, #3 + 10459 03ba 67D0 beq .L788 + 10460 .L727: +5677:Middlewares/Third_Party/FatFs/src/ff.c **** sect = b_fat; /* FAT start sector */ + 10461 .loc 1 5677 3 is_stmt 1 view .LVU3551 + 10462 03bc 029A ldr r2, [sp, #8] + 10463 03be 0021 movs r1, #0 + 10464 03c0 3046 mov r0, r6 + 10465 03c2 FFF7FEFF bl mem_set + 10466 .LVL1225: +5678:Middlewares/Third_Party/FatFs/src/ff.c **** for (i = 0; i < n_fats; i++) { /* Initialize FATs each */ + 10467 .loc 1 5678 3 view .LVU3552 +5679:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { + 10468 .loc 1 5679 3 view .LVU3553 +5679:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { + 10469 .loc 1 5679 3 is_stmt 0 view .LVU3554 + 10470 03c6 4546 mov r5, r8 + 10471 .LVL1226: +5679:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { + 10472 .loc 1 5679 3 view .LVU3555 + 10473 03c8 0297 str r7, [sp, #8] + 10474 .LVL1227: +5679:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { + 10475 .loc 1 5679 3 view .LVU3556 + 10476 03ca 069F ldr r7, [sp, #24] + 10477 .LVL1228: + 10478 .L728: +5679:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { + 10479 .loc 1 5679 17 is_stmt 1 discriminator 1 view .LVU3557 + 10480 03cc 019B ldr r3, [sp, #4] + 10481 03ce 002B cmp r3, #0 + 10482 03d0 00F09080 beq .L733 +5697:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 10483 .loc 1 5697 35 is_stmt 0 view .LVU3558 + 10484 03d4 A846 mov r8, r5 + 10485 03d6 0697 str r7, [sp, #24] + 10486 .LVL1229: +5697:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 10487 .loc 1 5697 35 view .LVU3559 + 10488 03d8 029F ldr r7, [sp, #8] + 10489 .LVL1230: +5697:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 10490 .loc 1 5697 3 is_stmt 1 view .LVU3560 +5697:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 10491 .loc 1 5697 35 is_stmt 0 view .LVU3561 + 10492 03da BAF1030F cmp r10, #3 + 10493 03de 00F0C880 beq .L789 +5697:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 10494 .loc 1 5697 35 view .LVU3562 + 10495 03e2 DDF82080 ldr r8, [sp, #32] + ARM GAS /tmp/cc2SVLkL.s page 345 + + + 10496 03e6 0197 str r7, [sp, #4] + 10497 .LVL1231: +5697:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 10498 .loc 1 5697 35 view .LVU3563 + 10499 03e8 069F ldr r7, [sp, #24] + 10500 .LVL1232: + 10501 .L735: +5698:Middlewares/Third_Party/FatFs/src/ff.c **** n = (nsect > sz_buf) ? sz_buf : nsect; + 10502 .loc 1 5698 3 is_stmt 1 view .LVU3564 +5699:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR; + 10503 .loc 1 5699 4 view .LVU3565 +5699:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR; + 10504 .loc 1 5699 6 is_stmt 0 view .LVU3566 + 10505 03ea 4546 mov r5, r8 + 10506 03ec C845 cmp r8, r9 + 10507 03ee 28BF it cs + 10508 03f0 4D46 movcs r5, r9 + 10509 .LVL1233: +5700:Middlewares/Third_Party/FatFs/src/ff.c **** sect += n; nsect -= n; + 10510 .loc 1 5700 4 is_stmt 1 view .LVU3567 +5700:Middlewares/Third_Party/FatFs/src/ff.c **** sect += n; nsect -= n; + 10511 .loc 1 5700 8 is_stmt 0 view .LVU3568 + 10512 03f2 2B46 mov r3, r5 + 10513 03f4 3A46 mov r2, r7 + 10514 03f6 3146 mov r1, r6 + 10515 03f8 2046 mov r0, r4 + 10516 03fa FFF7FEFF bl disk_write + 10517 .LVL1234: +5700:Middlewares/Third_Party/FatFs/src/ff.c **** sect += n; nsect -= n; + 10518 .loc 1 5700 7 discriminator 1 view .LVU3569 + 10519 03fe 0028 cmp r0, #0 + 10520 0400 40F04281 bne .L770 +5701:Middlewares/Third_Party/FatFs/src/ff.c **** } while (nsect); + 10521 .loc 1 5701 4 is_stmt 1 view .LVU3570 +5701:Middlewares/Third_Party/FatFs/src/ff.c **** } while (nsect); + 10522 .loc 1 5701 9 is_stmt 0 view .LVU3571 + 10523 0404 2F44 add r7, r7, r5 + 10524 .LVL1235: +5701:Middlewares/Third_Party/FatFs/src/ff.c **** } while (nsect); + 10525 .loc 1 5701 15 is_stmt 1 view .LVU3572 +5702:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10526 .loc 1 5702 12 view .LVU3573 + 10527 0406 B8EB0508 subs r8, r8, r5 + 10528 .LVL1236: +5702:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10529 .loc 1 5702 12 is_stmt 0 view .LVU3574 + 10530 040a EED1 bne .L735 +5709:Middlewares/Third_Party/FatFs/src/ff.c **** sys = 0x0C; /* FAT32X */ + 10531 .loc 1 5709 6 view .LVU3575 + 10532 040c 019F ldr r7, [sp, #4] + 10533 .LVL1237: +5706:Middlewares/Third_Party/FatFs/src/ff.c **** sys = 0x07; /* HPFS/NTFS/exFAT */ + 10534 .loc 1 5706 2 is_stmt 1 view .LVU3576 +5709:Middlewares/Third_Party/FatFs/src/ff.c **** sys = 0x0C; /* FAT32X */ + 10535 .loc 1 5709 3 view .LVU3577 +5709:Middlewares/Third_Party/FatFs/src/ff.c **** sys = 0x0C; /* FAT32X */ + 10536 .loc 1 5709 6 is_stmt 0 view .LVU3578 + ARM GAS /tmp/cc2SVLkL.s page 346 + + + 10537 040e BAF1030F cmp r10, #3 + 10538 0412 00F0B480 beq .L771 +5712:Middlewares/Third_Party/FatFs/src/ff.c **** sys = 0x06; /* FAT12/16 (>=64KS) */ + 10539 .loc 1 5712 4 is_stmt 1 view .LVU3579 +5712:Middlewares/Third_Party/FatFs/src/ff.c **** sys = 0x06; /* FAT12/16 (>=64KS) */ + 10540 .loc 1 5712 15 is_stmt 0 view .LVU3580 + 10541 0416 0B9B ldr r3, [sp, #44] +5712:Middlewares/Third_Party/FatFs/src/ff.c **** sys = 0x06; /* FAT12/16 (>=64KS) */ + 10542 .loc 1 5712 7 view .LVU3581 + 10543 0418 B3F5803F cmp r3, #65536 + 10544 041c 80F0F480 bcs .L772 +5715:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10545 .loc 1 5715 5 is_stmt 1 view .LVU3582 +5715:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10546 .loc 1 5715 9 is_stmt 0 view .LVU3583 + 10547 0420 BAF1020F cmp r10, #2 + 10548 0424 00F0A880 beq .L790 +5715:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10549 .loc 1 5715 9 discriminator 2 view .LVU3584 + 10550 0428 4FF00108 mov r8, #1 + 10551 .LVL1238: +5715:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10552 .loc 1 5715 9 discriminator 2 view .LVU3585 + 10553 042c A9E0 b .L736 + 10554 .LVL1239: + 10555 .L786: +5634:Middlewares/Third_Party/FatFs/src/ff.c **** if (sz_vol < 0x10000) { + 10556 .loc 1 5634 3 discriminator 1 view .LVU3586 + 10557 042e 0021 movs r1, #0 + 10558 0430 79E7 b .L722 + 10559 .L723: +5638:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10560 .loc 1 5638 4 is_stmt 1 view .LVU3587 + 10561 0432 06F12000 add r0, r6, #32 + 10562 0436 FFF7FEFF bl st_dword + 10563 .LVL1240: + 10564 043a 7FE7 b .L724 + 10565 .L787: +5645:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BPB_FATSz32, sz_fat); /* FAT size [sector] */ + 10566 .loc 1 5645 4 view .LVU3588 + 10567 043c FFF7FEFF bl get_fattime + 10568 .LVL1241: + 10569 0440 0146 mov r1, r0 +5645:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BPB_FATSz32, sz_fat); /* FAT size [sector] */ + 10570 .loc 1 5645 4 is_stmt 0 discriminator 1 view .LVU3589 + 10571 0442 06F14300 add r0, r6, #67 + 10572 0446 FFF7FEFF bl st_dword + 10573 .LVL1242: +5646:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + BPB_RootClus32, 2); /* Root directory cluster # (2) */ + 10574 .loc 1 5646 4 is_stmt 1 view .LVU3590 + 10575 044a 0799 ldr r1, [sp, #28] + 10576 044c 06F12400 add r0, r6, #36 + 10577 0450 FFF7FEFF bl st_dword + 10578 .LVL1243: +5647:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_FSInfo32, 1); /* Offset of FSINFO sector (VBR + 1) */ + 10579 .loc 1 5647 4 view .LVU3591 + 10580 0454 0221 movs r1, #2 + ARM GAS /tmp/cc2SVLkL.s page 347 + + + 10581 0456 06F12C00 add r0, r6, #44 + 10582 045a FFF7FEFF bl st_dword + 10583 .LVL1244: +5648:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BPB_BkBootSec32, 6); /* Offset of backup VBR (VBR + 6) */ + 10584 .loc 1 5648 4 view .LVU3592 + 10585 045e 0121 movs r1, #1 + 10586 0460 06F13000 add r0, r6, #48 + 10587 0464 FFF7FEFF bl st_word + 10588 .LVL1245: +5649:Middlewares/Third_Party/FatFs/src/ff.c **** buf[BS_DrvNum32] = 0x80; /* Drive number (for int13) */ + 10589 .loc 1 5649 4 view .LVU3593 + 10590 0468 0621 movs r1, #6 + 10591 046a 06F13200 add r0, r6, #50 + 10592 046e FFF7FEFF bl st_word + 10593 .LVL1246: +5650:Middlewares/Third_Party/FatFs/src/ff.c **** buf[BS_BootSig32] = 0x29; /* Extended boot signature */ + 10594 .loc 1 5650 4 view .LVU3594 +5650:Middlewares/Third_Party/FatFs/src/ff.c **** buf[BS_BootSig32] = 0x29; /* Extended boot signature */ + 10595 .loc 1 5650 21 is_stmt 0 view .LVU3595 + 10596 0472 8023 movs r3, #128 + 10597 0474 86F84030 strb r3, [r6, #64] +5651:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(buf + BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ + 10598 .loc 1 5651 4 is_stmt 1 view .LVU3596 +5651:Middlewares/Third_Party/FatFs/src/ff.c **** mem_cpy(buf + BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ + 10599 .loc 1 5651 22 is_stmt 0 view .LVU3597 + 10600 0478 2923 movs r3, #41 + 10601 047a 86F84230 strb r3, [r6, #66] +5652:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 10602 .loc 1 5652 4 is_stmt 1 view .LVU3598 + 10603 047e 1322 movs r2, #19 + 10604 0480 7249 ldr r1, .L795+8 + 10605 0482 06F14700 add r0, r6, #71 + 10606 0486 FFF7FEFF bl mem_cpy + 10607 .LVL1247: + 10608 048a 84E7 b .L726 + 10609 .LVL1248: + 10610 .L788: +5665:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, ss); + 10611 .loc 1 5665 4 view .LVU3599 + 10612 048c 0123 movs r3, #1 + 10613 048e 0BF10602 add r2, fp, #6 + 10614 0492 3146 mov r1, r6 + 10615 0494 2046 mov r0, r4 + 10616 0496 FFF7FEFF bl disk_write + 10617 .LVL1249: +5666:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + FSI_LeadSig, 0x41615252); + 10618 .loc 1 5666 4 view .LVU3600 + 10619 049a BDF83620 ldrh r2, [sp, #54] + 10620 049e 0021 movs r1, #0 + 10621 04a0 3046 mov r0, r6 + 10622 04a2 FFF7FEFF bl mem_set + 10623 .LVL1250: +5667:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + FSI_StrucSig, 0x61417272); + 10624 .loc 1 5667 4 view .LVU3601 + 10625 04a6 6A49 ldr r1, .L795+12 + 10626 04a8 3046 mov r0, r6 + 10627 04aa FFF7FEFF bl st_dword + ARM GAS /tmp/cc2SVLkL.s page 348 + + + 10628 .LVL1251: +5668:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + FSI_Free_Count, n_clst - 1); /* Number of free clusters */ + 10629 .loc 1 5668 4 view .LVU3602 + 10630 04ae 6949 ldr r1, .L795+16 + 10631 04b0 06F5F270 add r0, r6, #484 + 10632 04b4 FFF7FEFF bl st_dword + 10633 .LVL1252: +5669:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + FSI_Nxt_Free, 2); /* Last allocated cluster# */ + 10634 .loc 1 5669 4 view .LVU3603 + 10635 04b8 691E subs r1, r5, #1 + 10636 04ba 06F5F470 add r0, r6, #488 + 10637 04be FFF7FEFF bl st_dword + 10638 .LVL1253: +5670:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BS_55AA, 0xAA55); + 10639 .loc 1 5670 4 view .LVU3604 + 10640 04c2 0221 movs r1, #2 + 10641 04c4 06F5F670 add r0, r6, #492 + 10642 04c8 FFF7FEFF bl st_dword + 10643 .LVL1254: +5671:Middlewares/Third_Party/FatFs/src/ff.c **** disk_write(pdrv, buf, b_vol + 7, 1); /* Write backup FSINFO (VBR + 7) */ + 10644 .loc 1 5671 4 view .LVU3605 + 10645 04cc 4AF65521 movw r1, #43605 + 10646 04d0 3846 mov r0, r7 + 10647 04d2 FFF7FEFF bl st_word + 10648 .LVL1255: +5672:Middlewares/Third_Party/FatFs/src/ff.c **** disk_write(pdrv, buf, b_vol + 1, 1); /* Write original FSINFO (VBR + 1) */ + 10649 .loc 1 5672 4 view .LVU3606 + 10650 04d6 0123 movs r3, #1 + 10651 04d8 0BF10702 add r2, fp, #7 + 10652 04dc 3146 mov r1, r6 + 10653 04de 2046 mov r0, r4 + 10654 04e0 FFF7FEFF bl disk_write + 10655 .LVL1256: +5673:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10656 .loc 1 5673 4 view .LVU3607 + 10657 04e4 0123 movs r3, #1 + 10658 04e6 0BEB0302 add r2, fp, r3 + 10659 04ea 3146 mov r1, r6 + 10660 04ec 2046 mov r0, r4 + 10661 04ee FFF7FEFF bl disk_write + 10662 .LVL1257: + 10663 04f2 63E7 b .L727 + 10664 .LVL1258: + 10665 .L733: +5680:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + 0, 0xFFFFFFF8); /* Entry 0 */ + 10666 .loc 1 5680 4 view .LVU3608 +5680:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + 0, 0xFFFFFFF8); /* Entry 0 */ + 10667 .loc 1 5680 7 is_stmt 0 view .LVU3609 + 10668 04f4 BAF1030F cmp r10, #3 + 10669 04f8 28D0 beq .L791 +5685:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10670 .loc 1 5685 5 is_stmt 1 view .LVU3610 + 10671 04fa BAF1010F cmp r10, #1 + 10672 04fe 36D0 beq .L792 +5685:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10673 .loc 1 5685 5 is_stmt 0 discriminator 2 view .LVU3611 + 10674 0500 6FF00701 mvn r1, #7 + ARM GAS /tmp/cc2SVLkL.s page 349 + + + 10675 .L731: +5685:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10676 .loc 1 5685 5 discriminator 4 view .LVU3612 + 10677 0504 3046 mov r0, r6 + 10678 0506 FFF7FEFF bl st_dword + 10679 .LVL1259: + 10680 .L730: +5685:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10681 .loc 1 5685 5 discriminator 2 view .LVU3613 + 10682 050a DDF81C80 ldr r8, [sp, #28] + 10683 050e CDF810A0 str r10, [sp, #16] + 10684 .L732: + 10685 .LVL1260: +5688:Middlewares/Third_Party/FatFs/src/ff.c **** n = (nsect > sz_buf) ? sz_buf : nsect; + 10686 .loc 1 5688 4 is_stmt 1 view .LVU3614 +5689:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR; + 10687 .loc 1 5689 5 view .LVU3615 +5689:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) return FR_DISK_ERR; + 10688 .loc 1 5689 7 is_stmt 0 view .LVU3616 + 10689 0512 C246 mov r10, r8 + 10690 0514 C845 cmp r8, r9 + 10691 0516 28BF it cs + 10692 0518 CA46 movcs r10, r9 + 10693 .LVL1261: +5690:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, ss); + 10694 .loc 1 5690 5 is_stmt 1 view .LVU3617 +5690:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, ss); + 10695 .loc 1 5690 9 is_stmt 0 view .LVU3618 + 10696 051a 5346 mov r3, r10 + 10697 051c 3A46 mov r2, r7 + 10698 051e 3146 mov r1, r6 + 10699 0520 2046 mov r0, r4 + 10700 0522 FFF7FEFF bl disk_write + 10701 .LVL1262: +5690:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, ss); + 10702 .loc 1 5690 8 discriminator 1 view .LVU3619 + 10703 0526 0028 cmp r0, #0 + 10704 0528 40F0AC80 bne .L769 +5691:Middlewares/Third_Party/FatFs/src/ff.c **** sect += n; nsect -= n; + 10705 .loc 1 5691 5 is_stmt 1 view .LVU3620 + 10706 052c BDF83620 ldrh r2, [sp, #54] + 10707 0530 0021 movs r1, #0 + 10708 0532 3046 mov r0, r6 + 10709 0534 FFF7FEFF bl mem_set + 10710 .LVL1263: +5692:Middlewares/Third_Party/FatFs/src/ff.c **** } while (nsect); + 10711 .loc 1 5692 5 view .LVU3621 +5692:Middlewares/Third_Party/FatFs/src/ff.c **** } while (nsect); + 10712 .loc 1 5692 10 is_stmt 0 view .LVU3622 + 10713 0538 5744 add r7, r7, r10 + 10714 .LVL1264: +5692:Middlewares/Third_Party/FatFs/src/ff.c **** } while (nsect); + 10715 .loc 1 5692 16 is_stmt 1 view .LVU3623 +5693:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10716 .loc 1 5693 13 view .LVU3624 + 10717 053a B8EB0A08 subs r8, r8, r10 + 10718 .LVL1265: + ARM GAS /tmp/cc2SVLkL.s page 350 + + +5693:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10719 .loc 1 5693 13 is_stmt 0 view .LVU3625 + 10720 053e E8D1 bne .L732 +5679:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { + 10721 .loc 1 5679 28 discriminator 2 view .LVU3626 + 10722 0540 DDF810A0 ldr r10, [sp, #16] + 10723 .LVL1266: +5679:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { + 10724 .loc 1 5679 28 is_stmt 1 discriminator 2 view .LVU3627 + 10725 0544 019B ldr r3, [sp, #4] + 10726 0546 0133 adds r3, r3, #1 + 10727 0548 0193 str r3, [sp, #4] + 10728 .LVL1267: +5679:Middlewares/Third_Party/FatFs/src/ff.c **** if (fmt == FS_FAT32) { + 10729 .loc 1 5679 28 is_stmt 0 discriminator 2 view .LVU3628 + 10730 054a 3FE7 b .L728 + 10731 .LVL1268: + 10732 .L791: +5681:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + 4, 0xFFFFFFFF); /* Entry 1 */ + 10733 .loc 1 5681 5 is_stmt 1 view .LVU3629 + 10734 054c 6FF00701 mvn r1, #7 + 10735 0550 3046 mov r0, r6 + 10736 0552 FFF7FEFF bl st_dword + 10737 .LVL1269: +5682:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(buf + 8, 0x0FFFFFFF); /* Entry 2 (root directory) */ + 10738 .loc 1 5682 5 view .LVU3630 + 10739 0556 4FF0FF31 mov r1, #-1 + 10740 055a 301D adds r0, r6, #4 + 10741 055c FFF7FEFF bl st_dword + 10742 .LVL1270: +5683:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 10743 .loc 1 5683 5 view .LVU3631 + 10744 0560 6FF07041 mvn r1, #-268435456 + 10745 0564 06F10800 add r0, r6, #8 + 10746 0568 FFF7FEFF bl st_dword + 10747 .LVL1271: + 10748 056c CDE7 b .L730 + 10749 .LVL1272: + 10750 .L792: +5685:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10751 .loc 1 5685 5 is_stmt 0 discriminator 1 view .LVU3632 + 10752 056e 3A49 ldr r1, .L795+20 + 10753 0570 C8E7 b .L731 + 10754 .LVL1273: + 10755 .L789: +5697:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 10756 .loc 1 5697 35 discriminator 1 view .LVU3633 + 10757 0572 0197 str r7, [sp, #4] + 10758 0574 069F ldr r7, [sp, #24] + 10759 0576 38E7 b .L735 + 10760 .LVL1274: + 10761 .L790: +5715:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10762 .loc 1 5715 9 discriminator 1 view .LVU3634 + 10763 0578 4FF00408 mov r8, #4 + 10764 .LVL1275: +5715:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 351 + + + 10765 .loc 1 5715 9 discriminator 1 view .LVU3635 + 10766 057c 01E0 b .L736 + 10767 .LVL1276: + 10768 .L771: +5710:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 10769 .loc 1 5710 8 view .LVU3636 + 10770 057e 4FF00C08 mov r8, #12 + 10771 .LVL1277: + 10772 .L736: +5721:Middlewares/Third_Party/FatFs/src/ff.c **** /* Update system ID in the partition table */ + 10773 .loc 1 5721 2 is_stmt 1 view .LVU3637 +5727:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, ss); + 10774 .loc 1 5727 3 view .LVU3638 +5727:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, ss); + 10775 .loc 1 5727 6 is_stmt 0 view .LVU3639 + 10776 0582 039B ldr r3, [sp, #12] + 10777 0584 C3BB cbnz r3, .L737 +5728:Middlewares/Third_Party/FatFs/src/ff.c **** st_word(buf + BS_55AA, 0xAA55); /* MBR signature */ + 10778 .loc 1 5728 4 is_stmt 1 view .LVU3640 + 10779 0586 BDF83620 ldrh r2, [sp, #54] + 10780 058a 0021 movs r1, #0 + 10781 058c 3046 mov r0, r6 + 10782 058e FFF7FEFF bl mem_set + 10783 .LVL1278: +5729:Middlewares/Third_Party/FatFs/src/ff.c **** pte = buf + MBR_Table; /* Create partition table for single partition in the drive */ + 10784 .loc 1 5729 4 view .LVU3641 + 10785 0592 4AF65521 movw r1, #43605 + 10786 0596 3846 mov r0, r7 + 10787 0598 FFF7FEFF bl st_word + 10788 .LVL1279: +5730:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_Boot] = 0; /* Boot indicator */ + 10789 .loc 1 5730 4 view .LVU3642 +5731:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_StHead] = 1; /* Start head */ + 10790 .loc 1 5731 4 view .LVU3643 +5731:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_StHead] = 1; /* Start head */ + 10791 .loc 1 5731 18 is_stmt 0 view .LVU3644 + 10792 059c 0025 movs r5, #0 + 10793 .LVL1280: +5731:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_StHead] = 1; /* Start head */ + 10794 .loc 1 5731 18 view .LVU3645 + 10795 059e 86F8BE51 strb r5, [r6, #446] +5732:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_StSec] = 1; /* Start sector */ + 10796 .loc 1 5732 4 is_stmt 1 view .LVU3646 +5732:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_StSec] = 1; /* Start sector */ + 10797 .loc 1 5732 20 is_stmt 0 view .LVU3647 + 10798 05a2 0127 movs r7, #1 + 10799 05a4 86F8BF71 strb r7, [r6, #447] +5733:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_StCyl] = 0; /* Start cylinder */ + 10800 .loc 1 5733 4 is_stmt 1 view .LVU3648 +5733:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_StCyl] = 0; /* Start cylinder */ + 10801 .loc 1 5733 19 is_stmt 0 view .LVU3649 + 10802 05a8 86F8C071 strb r7, [r6, #448] +5734:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_System] = sys; /* System type */ + 10803 .loc 1 5734 4 is_stmt 1 view .LVU3650 +5734:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_System] = sys; /* System type */ + 10804 .loc 1 5734 19 is_stmt 0 view .LVU3651 + 10805 05ac 86F8C151 strb r5, [r6, #449] + ARM GAS /tmp/cc2SVLkL.s page 352 + + +5735:Middlewares/Third_Party/FatFs/src/ff.c **** n = (b_vol + sz_vol) / (63 * 255); /* (End CHS may be invalid) */ + 10806 .loc 1 5735 4 is_stmt 1 view .LVU3652 +5735:Middlewares/Third_Party/FatFs/src/ff.c **** n = (b_vol + sz_vol) / (63 * 255); /* (End CHS may be invalid) */ + 10807 .loc 1 5735 20 is_stmt 0 view .LVU3653 + 10808 05b0 86F8C281 strb r8, [r6, #450] +5736:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_EdHead] = 254; /* End head */ + 10809 .loc 1 5736 4 is_stmt 1 view .LVU3654 +5736:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_EdHead] = 254; /* End head */ + 10810 .loc 1 5736 15 is_stmt 0 view .LVU3655 + 10811 05b4 0B9B ldr r3, [sp, #44] + 10812 05b6 5B44 add r3, r3, fp +5736:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_EdHead] = 254; /* End head */ + 10813 .loc 1 5736 6 view .LVU3656 + 10814 05b8 43F6C162 movw r2, #16065 + 10815 05bc B3FBF2F3 udiv r3, r3, r2 + 10816 .LVL1281: +5737:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_EdSec] = (BYTE)(n >> 2 | 63); /* End sector */ + 10817 .loc 1 5737 4 is_stmt 1 view .LVU3657 +5737:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_EdSec] = (BYTE)(n >> 2 | 63); /* End sector */ + 10818 .loc 1 5737 20 is_stmt 0 view .LVU3658 + 10819 05c0 FE22 movs r2, #254 + 10820 05c2 86F8C321 strb r2, [r6, #451] +5738:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_EdCyl] = (BYTE)n; /* End cylinder */ + 10821 .loc 1 5738 4 is_stmt 1 view .LVU3659 +5738:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_EdCyl] = (BYTE)n; /* End cylinder */ + 10822 .loc 1 5738 30 is_stmt 0 view .LVU3660 + 10823 05c6 9A08 lsrs r2, r3, #2 +5738:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_EdCyl] = (BYTE)n; /* End cylinder */ + 10824 .loc 1 5738 21 view .LVU3661 + 10825 05c8 42F03F02 orr r2, r2, #63 +5738:Middlewares/Third_Party/FatFs/src/ff.c **** pte[PTE_EdCyl] = (BYTE)n; /* End cylinder */ + 10826 .loc 1 5738 19 view .LVU3662 + 10827 05cc 86F8C421 strb r2, [r6, #452] +5739:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(pte + PTE_StLba, b_vol); /* Start offset in LBA */ + 10828 .loc 1 5739 4 is_stmt 1 view .LVU3663 +5739:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(pte + PTE_StLba, b_vol); /* Start offset in LBA */ + 10829 .loc 1 5739 19 is_stmt 0 view .LVU3664 + 10830 05d0 86F8C531 strb r3, [r6, #453] +5740:Middlewares/Third_Party/FatFs/src/ff.c **** st_dword(pte + PTE_SizLba, sz_vol); /* Size in sectors */ + 10831 .loc 1 5740 4 is_stmt 1 view .LVU3665 + 10832 05d4 5946 mov r1, fp + 10833 05d6 06F5E370 add r0, r6, #454 + 10834 05da FFF7FEFF bl st_dword + 10835 .LVL1282: +5741:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_write(pdrv, buf, 0, 1) != RES_OK) return FR_DISK_ERR; /* Write it to the MBR */ + 10836 .loc 1 5741 4 view .LVU3666 + 10837 05de 0B99 ldr r1, [sp, #44] + 10838 05e0 06F5E570 add r0, r6, #458 + 10839 05e4 FFF7FEFF bl st_dword + 10840 .LVL1283: +5742:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10841 .loc 1 5742 4 view .LVU3667 +5742:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10842 .loc 1 5742 8 is_stmt 0 view .LVU3668 + 10843 05e8 3B46 mov r3, r7 + 10844 05ea 2A46 mov r2, r5 + 10845 05ec 3146 mov r1, r6 + ARM GAS /tmp/cc2SVLkL.s page 353 + + + 10846 05ee 2046 mov r0, r4 + 10847 05f0 FFF7FEFF bl disk_write + 10848 .LVL1284: +5742:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10849 .loc 1 5742 7 discriminator 1 view .LVU3669 + 10850 05f4 0028 cmp r0, #0 + 10851 05f6 49D1 bne .L774 + 10852 .LVL1285: + 10853 .L737: +5746:Middlewares/Third_Party/FatFs/src/ff.c **** + 10854 .loc 1 5746 2 is_stmt 1 view .LVU3670 +5746:Middlewares/Third_Party/FatFs/src/ff.c **** + 10855 .loc 1 5746 6 is_stmt 0 view .LVU3671 + 10856 05f8 0022 movs r2, #0 + 10857 05fa 1146 mov r1, r2 + 10858 05fc 2046 mov r0, r4 + 10859 05fe FFF7FEFF bl disk_ioctl + 10860 .LVL1286: +5746:Middlewares/Third_Party/FatFs/src/ff.c **** + 10861 .loc 1 5746 5 discriminator 1 view .LVU3672 + 10862 0602 48B1 cbz r0, .L696 +5746:Middlewares/Third_Party/FatFs/src/ff.c **** + 10863 .loc 1 5746 55 discriminator 1 view .LVU3673 + 10864 0604 0120 movs r0, #1 + 10865 0606 07E0 b .L696 + 10866 .LVL1287: + 10867 .L772: +5713:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 10868 .loc 1 5713 9 view .LVU3674 + 10869 0608 4FF00608 mov r8, #6 + 10870 .LVL1288: +5713:Middlewares/Third_Party/FatFs/src/ff.c **** } else { + 10871 .loc 1 5713 9 view .LVU3675 + 10872 060c B9E7 b .L736 + 10873 .LVL1289: + 10874 .L738: +5328:Middlewares/Third_Party/FatFs/src/ff.c **** if (FatFs[vol]) FatFs[vol]->fs_type = 0; /* Clear the volume */ + 10875 .loc 1 5328 22 discriminator 1 view .LVU3676 + 10876 060e 0B20 movs r0, #11 + 10877 .LVL1290: +5328:Middlewares/Third_Party/FatFs/src/ff.c **** if (FatFs[vol]) FatFs[vol]->fs_type = 0; /* Clear the volume */ + 10878 .loc 1 5328 22 discriminator 1 view .LVU3677 + 10879 0610 02E0 b .L696 + 10880 .LVL1291: + 10881 .L739: +5335:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; + 10882 .loc 1 5335 32 discriminator 1 view .LVU3678 + 10883 0612 0320 movs r0, #3 + 10884 .LVL1292: +5335:Middlewares/Third_Party/FatFs/src/ff.c **** if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; + 10885 .loc 1 5335 32 discriminator 1 view .LVU3679 + 10886 0614 00E0 b .L696 + 10887 .LVL1293: + 10888 .L740: +5336:Middlewares/Third_Party/FatFs/src/ff.c **** if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 32768 || (sz_blk & + 10889 .loc 1 5336 33 discriminator 1 view .LVU3680 + 10890 0616 0A20 movs r0, #10 + ARM GAS /tmp/cc2SVLkL.s page 354 + + + 10891 .LVL1294: + 10892 .L696: +5749:Middlewares/Third_Party/FatFs/src/ff.c **** + 10893 .loc 1 5749 1 view .LVU3681 + 10894 0618 0FB0 add sp, sp, #60 + 10895 .LCFI112: + 10896 .cfi_remember_state + 10897 .cfi_def_cfa_offset 36 + 10898 @ sp needed + 10899 061a BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 10900 .LVL1295: + 10901 .L741: + 10902 .LCFI113: + 10903 .cfi_restore_state +5339:Middlewares/Third_Party/FatFs/src/ff.c **** if (ss > _MAX_SS || ss < _MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR; + 10904 .loc 1 5339 63 discriminator 1 view .LVU3682 + 10905 061e 0120 movs r0, #1 + 10906 0620 FAE7 b .L696 + 10907 .L742: +5340:Middlewares/Third_Party/FatFs/src/ff.c **** #else + 10908 .loc 1 5340 62 discriminator 3 view .LVU3683 + 10909 0622 0120 movs r0, #1 + 10910 0624 F8E7 b .L696 + 10911 .L743: + 10912 0626 0120 movs r0, #1 + 10913 0628 F6E7 b .L696 + 10914 .L744: +5344:Middlewares/Third_Party/FatFs/src/ff.c **** au /= ss; /* Cluster size in unit of sector */ + 10915 .loc 1 5344 72 discriminator 7 view .LVU3684 + 10916 062a 1320 movs r0, #19 + 10917 062c F4E7 b .L696 + 10918 .L745: + 10919 062e 1320 movs r0, #19 + 10920 0630 F2E7 b .L696 + 10921 .L746: +5344:Middlewares/Third_Party/FatFs/src/ff.c **** au /= ss; /* Cluster size in unit of sector */ + 10922 .loc 1 5344 72 discriminator 7 view .LVU3685 + 10923 0632 1320 movs r0, #19 + 10924 0634 F0E7 b .L696 + 10925 .LVL1296: + 10926 .L747: +5351:Middlewares/Third_Party/FatFs/src/ff.c **** + 10927 .loc 1 5351 23 discriminator 1 view .LVU3686 + 10928 0636 0E20 movs r0, #14 + 10929 0638 EEE7 b .L696 + 10930 .LVL1297: + 10931 .L748: +5364:Middlewares/Third_Party/FatFs/src/ff.c **** b_vol = (opt & FM_SFD) ? 0 : 63; /* Volume start sector */ + 10932 .loc 1 5364 69 discriminator 1 view .LVU3687 + 10933 063a 0120 movs r0, #1 + 10934 063c ECE7 b .L696 + 10935 .LVL1298: + 10936 .L750: +5366:Middlewares/Third_Party/FatFs/src/ff.c **** sz_vol -= b_vol; /* Volume size */ + 10937 .loc 1 5366 30 discriminator 1 view .LVU3688 + 10938 063e 0E20 movs r0, #14 + 10939 0640 EAE7 b .L696 + ARM GAS /tmp/cc2SVLkL.s page 355 + + + 10940 .L796: + 10941 0642 00BF .align 2 + 10942 .L795: + 10943 0644 00000000 .word .LC1 + 10944 0648 20000000 .word .LC3 + 10945 064c 0C000000 .word .LC2 + 10946 0650 52526141 .word 1096897106 + 10947 0654 72724161 .word 1631679090 + 10948 0658 F8FFFF00 .word 16777208 + 10949 .L751: +5369:Middlewares/Third_Party/FatFs/src/ff.c **** + 10950 .loc 1 5369 27 discriminator 1 view .LVU3689 + 10951 065c 0E20 movs r0, #14 + 10952 065e DBE7 b .L696 + 10953 .L752: +5378:Middlewares/Third_Party/FatFs/src/ff.c **** if (opt & FM_FAT32) { /* FAT32 possible? */ + 10954 .loc 1 5378 24 discriminator 1 view .LVU3690 + 10955 0660 1320 movs r0, #19 + 10956 0662 D9E7 b .L696 + 10957 .L755: +5384:Middlewares/Third_Party/FatFs/src/ff.c **** fmt = FS_FAT16; + 10958 .loc 1 5384 31 discriminator 1 view .LVU3691 + 10959 0664 1320 movs r0, #19 + 10960 0666 D7E7 b .L696 + 10961 .LVL1299: + 10962 .L757: +5564:Middlewares/Third_Party/FatFs/src/ff.c **** } else { /* FAT12/16 volume */ + 10963 .loc 1 5564 59 discriminator 1 view .LVU3692 + 10964 0668 0E20 movs r0, #14 + 10965 066a D5E7 b .L696 + 10966 .LVL1300: + 10967 .L759: +5593:Middlewares/Third_Party/FatFs/src/ff.c **** n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau; + 10968 .loc 1 5593 51 discriminator 1 view .LVU3693 + 10969 066c 0E20 movs r0, #14 + 10970 066e D3E7 b .L696 + 10971 .LVL1301: + 10972 .L760: +5598:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10973 .loc 1 5598 13 view .LVU3694 + 10974 0670 0E20 movs r0, #14 + 10975 .LVL1302: +5598:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10976 .loc 1 5598 13 view .LVU3695 + 10977 0672 D1E7 b .L696 + 10978 .LVL1303: + 10979 .L763: +5610:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10980 .loc 1 5610 13 view .LVU3696 + 10981 0674 0E20 movs r0, #14 + 10982 .LVL1304: +5610:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10983 .loc 1 5610 13 view .LVU3697 + 10984 0676 CFE7 b .L696 + 10985 .LVL1305: + 10986 .L764: +5614:Middlewares/Third_Party/FatFs/src/ff.c **** } + ARM GAS /tmp/cc2SVLkL.s page 356 + + + 10987 .loc 1 5614 13 view .LVU3698 + 10988 0678 0E20 movs r0, #14 + 10989 .LVL1306: +5614:Middlewares/Third_Party/FatFs/src/ff.c **** } + 10990 .loc 1 5614 13 view .LVU3699 + 10991 067a CDE7 b .L696 + 10992 .LVL1307: + 10993 .L765: +5617:Middlewares/Third_Party/FatFs/src/ff.c **** + 10994 .loc 1 5617 54 discriminator 1 view .LVU3700 + 10995 067c 0E20 movs r0, #14 + 10996 .LVL1308: +5617:Middlewares/Third_Party/FatFs/src/ff.c **** + 10997 .loc 1 5617 54 discriminator 1 view .LVU3701 + 10998 067e CBE7 b .L696 + 10999 .LVL1309: + 11000 .L767: +5661:Middlewares/Third_Party/FatFs/src/ff.c **** + 11001 .loc 1 5661 57 discriminator 1 view .LVU3702 + 11002 0680 0120 movs r0, #1 + 11003 0682 C9E7 b .L696 + 11004 .LVL1310: + 11005 .L769: +5690:Middlewares/Third_Party/FatFs/src/ff.c **** mem_set(buf, 0, ss); + 11006 .loc 1 5690 64 discriminator 1 view .LVU3703 + 11007 0684 0120 movs r0, #1 + 11008 0686 C7E7 b .L696 + 11009 .LVL1311: + 11010 .L770: +5700:Middlewares/Third_Party/FatFs/src/ff.c **** sect += n; nsect -= n; + 11011 .loc 1 5700 63 discriminator 1 view .LVU3704 + 11012 0688 0120 movs r0, #1 + 11013 068a C5E7 b .L696 + 11014 .LVL1312: + 11015 .L774: +5742:Middlewares/Third_Party/FatFs/src/ff.c **** } + 11016 .loc 1 5742 54 discriminator 1 view .LVU3705 + 11017 068c 0120 movs r0, #1 + 11018 068e C3E7 b .L696 + 11019 .cfi_endproc + 11020 .LFE1237: + 11022 .section .text.f_gets,"ax",%progbits + 11023 .align 1 + 11024 .global f_gets + 11025 .syntax unified + 11026 .thumb + 11027 .thumb_func + 11029 f_gets: + 11030 .LVL1313: + 11031 .LFB1238: +5835:Middlewares/Third_Party/FatFs/src/ff.c **** int n = 0; + 11032 .loc 1 5835 1 is_stmt 1 view -0 + 11033 .cfi_startproc + 11034 @ args = 0, pretend = 0, frame = 8 + 11035 @ frame_needed = 0, uses_anonymous_args = 0 +5835:Middlewares/Third_Party/FatFs/src/ff.c **** int n = 0; + 11036 .loc 1 5835 1 is_stmt 0 view .LVU3707 + ARM GAS /tmp/cc2SVLkL.s page 357 + + + 11037 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 11038 .LCFI114: + 11039 .cfi_def_cfa_offset 24 + 11040 .cfi_offset 4, -24 + 11041 .cfi_offset 5, -20 + 11042 .cfi_offset 6, -16 + 11043 .cfi_offset 7, -12 + 11044 .cfi_offset 8, -8 + 11045 .cfi_offset 14, -4 + 11046 0004 82B0 sub sp, sp, #8 + 11047 .LCFI115: + 11048 .cfi_def_cfa_offset 32 + 11049 0006 8046 mov r8, r0 + 11050 0008 0E46 mov r6, r1 + 11051 000a 1746 mov r7, r2 +5836:Middlewares/Third_Party/FatFs/src/ff.c **** TCHAR c, *p = buff; + 11052 .loc 1 5836 2 is_stmt 1 view .LVU3708 + 11053 .LVL1314: +5837:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE s[2]; + 11054 .loc 1 5837 2 view .LVU3709 +5838:Middlewares/Third_Party/FatFs/src/ff.c **** UINT rc; + 11055 .loc 1 5838 2 view .LVU3710 +5839:Middlewares/Third_Party/FatFs/src/ff.c **** + 11056 .loc 1 5839 2 view .LVU3711 +5842:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE + 11057 .loc 1 5842 2 view .LVU3712 +5837:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE s[2]; + 11058 .loc 1 5837 12 is_stmt 0 view .LVU3713 + 11059 000c 0446 mov r4, r0 +5836:Middlewares/Third_Party/FatFs/src/ff.c **** TCHAR c, *p = buff; + 11060 .loc 1 5836 6 view .LVU3714 + 11061 000e 0025 movs r5, #0 +5842:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE + 11062 .loc 1 5842 8 view .LVU3715 + 11063 0010 01E0 b .L798 + 11064 .LVL1315: + 11065 .L803: +5842:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE + 11066 .loc 1 5842 8 view .LVU3716 + 11067 0012 A446 mov ip, r4 + 11068 .LVL1316: + 11069 .L800: +5842:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE + 11070 .loc 1 5842 8 view .LVU3717 + 11071 0014 6446 mov r4, ip + 11072 .LVL1317: + 11073 .L798: +5842:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE + 11074 .loc 1 5842 11 is_stmt 1 view .LVU3718 +5842:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE + 11075 .loc 1 5842 17 is_stmt 0 view .LVU3719 + 11076 0016 731E subs r3, r6, #1 +5842:Middlewares/Third_Party/FatFs/src/ff.c **** #if _LFN_UNICODE + 11077 .loc 1 5842 11 view .LVU3720 + 11078 0018 AB42 cmp r3, r5 + 11079 001a 13DD ble .L799 +5887:Middlewares/Third_Party/FatFs/src/ff.c **** if (rc != 1) break; + ARM GAS /tmp/cc2SVLkL.s page 358 + + + 11080 .loc 1 5887 3 is_stmt 1 view .LVU3721 + 11081 001c 6B46 mov r3, sp + 11082 001e 0122 movs r2, #1 + 11083 0020 01A9 add r1, sp, #4 + 11084 0022 3846 mov r0, r7 + 11085 0024 FFF7FEFF bl f_read + 11086 .LVL1318: +5888:Middlewares/Third_Party/FatFs/src/ff.c **** c = s[0]; + 11087 .loc 1 5888 3 view .LVU3722 +5888:Middlewares/Third_Party/FatFs/src/ff.c **** c = s[0]; + 11088 .loc 1 5888 10 is_stmt 0 view .LVU3723 + 11089 0028 009B ldr r3, [sp] +5888:Middlewares/Third_Party/FatFs/src/ff.c **** c = s[0]; + 11090 .loc 1 5888 6 view .LVU3724 + 11091 002a 012B cmp r3, #1 + 11092 002c 0AD1 bne .L799 +5889:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 11093 .loc 1 5889 3 is_stmt 1 view .LVU3725 +5889:Middlewares/Third_Party/FatFs/src/ff.c **** #endif + 11094 .loc 1 5889 5 is_stmt 0 view .LVU3726 + 11095 002e 9DF80430 ldrb r3, [sp, #4] @ zero_extendqisi2 + 11096 .LVL1319: +5891:Middlewares/Third_Party/FatFs/src/ff.c **** *p++ = c; + 11097 .loc 1 5891 3 is_stmt 1 view .LVU3727 +5891:Middlewares/Third_Party/FatFs/src/ff.c **** *p++ = c; + 11098 .loc 1 5891 6 is_stmt 0 view .LVU3728 + 11099 0032 0D2B cmp r3, #13 + 11100 0034 EDD0 beq .L803 +5892:Middlewares/Third_Party/FatFs/src/ff.c **** n++; + 11101 .loc 1 5892 3 is_stmt 1 view .LVU3729 +5892:Middlewares/Third_Party/FatFs/src/ff.c **** n++; + 11102 .loc 1 5892 5 is_stmt 0 view .LVU3730 + 11103 0036 A446 mov ip, r4 + 11104 .LVL1320: +5892:Middlewares/Third_Party/FatFs/src/ff.c **** n++; + 11105 .loc 1 5892 8 view .LVU3731 + 11106 0038 0CF8013B strb r3, [ip], #1 + 11107 .LVL1321: +5893:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == '\n') break; /* Break on EOL */ + 11108 .loc 1 5893 3 is_stmt 1 view .LVU3732 +5893:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == '\n') break; /* Break on EOL */ + 11109 .loc 1 5893 4 is_stmt 0 view .LVU3733 + 11110 003c 0135 adds r5, r5, #1 + 11111 .LVL1322: +5894:Middlewares/Third_Party/FatFs/src/ff.c **** } + 11112 .loc 1 5894 3 is_stmt 1 view .LVU3734 +5894:Middlewares/Third_Party/FatFs/src/ff.c **** } + 11113 .loc 1 5894 6 is_stmt 0 view .LVU3735 + 11114 003e 0A2B cmp r3, #10 + 11115 0040 E8D1 bne .L800 +5892:Middlewares/Third_Party/FatFs/src/ff.c **** n++; + 11116 .loc 1 5892 5 view .LVU3736 + 11117 0042 6446 mov r4, ip + 11118 .LVL1323: + 11119 .L799: +5896:Middlewares/Third_Party/FatFs/src/ff.c **** return n ? buff : 0; /* When no data read (eof or error), return with error. */ + 11120 .loc 1 5896 2 is_stmt 1 view .LVU3737 + ARM GAS /tmp/cc2SVLkL.s page 359 + + +5896:Middlewares/Third_Party/FatFs/src/ff.c **** return n ? buff : 0; /* When no data read (eof or error), return with error. */ + 11121 .loc 1 5896 5 is_stmt 0 view .LVU3738 + 11122 0044 0023 movs r3, #0 + 11123 0046 2370 strb r3, [r4] +5897:Middlewares/Third_Party/FatFs/src/ff.c **** } + 11124 .loc 1 5897 2 is_stmt 1 view .LVU3739 +5897:Middlewares/Third_Party/FatFs/src/ff.c **** } + 11125 .loc 1 5897 18 is_stmt 0 view .LVU3740 + 11126 0048 1DB1 cbz r5, .L805 +5897:Middlewares/Third_Party/FatFs/src/ff.c **** } + 11127 .loc 1 5897 18 discriminator 1 view .LVU3741 + 11128 004a 4046 mov r0, r8 + 11129 .L797: +5898:Middlewares/Third_Party/FatFs/src/ff.c **** + 11130 .loc 1 5898 1 view .LVU3742 + 11131 004c 02B0 add sp, sp, #8 + 11132 .LCFI116: + 11133 .cfi_remember_state + 11134 .cfi_def_cfa_offset 24 + 11135 @ sp needed + 11136 004e BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 11137 .LVL1324: + 11138 .L805: + 11139 .LCFI117: + 11140 .cfi_restore_state +5897:Middlewares/Third_Party/FatFs/src/ff.c **** } + 11141 .loc 1 5897 18 discriminator 2 view .LVU3743 + 11142 0052 0020 movs r0, #0 +5897:Middlewares/Third_Party/FatFs/src/ff.c **** } + 11143 .loc 1 5897 18 view .LVU3744 + 11144 0054 FAE7 b .L797 + 11145 .cfi_endproc + 11146 .LFE1238: + 11148 .section .text.f_putc,"ax",%progbits + 11149 .align 1 + 11150 .global f_putc + 11151 .syntax unified + 11152 .thumb + 11153 .thumb_func + 11155 f_putc: + 11156 .LVL1325: + 11157 .LFB1242: +5995:Middlewares/Third_Party/FatFs/src/ff.c **** +5996:Middlewares/Third_Party/FatFs/src/ff.c **** +5997:Middlewares/Third_Party/FatFs/src/ff.c **** +5998:Middlewares/Third_Party/FatFs/src/ff.c **** int f_putc ( +5999:Middlewares/Third_Party/FatFs/src/ff.c **** TCHAR c, /* A character to be output */ +6000:Middlewares/Third_Party/FatFs/src/ff.c **** FIL* fp /* Pointer to the file object */ +6001:Middlewares/Third_Party/FatFs/src/ff.c **** ) +6002:Middlewares/Third_Party/FatFs/src/ff.c **** { + 11158 .loc 1 6002 1 is_stmt 1 view -0 + 11159 .cfi_startproc + 11160 @ args = 0, pretend = 0, frame = 80 + 11161 @ frame_needed = 0, uses_anonymous_args = 0 + 11162 .loc 1 6002 1 is_stmt 0 view .LVU3746 + 11163 0000 10B5 push {r4, lr} + 11164 .LCFI118: + ARM GAS /tmp/cc2SVLkL.s page 360 + + + 11165 .cfi_def_cfa_offset 8 + 11166 .cfi_offset 4, -8 + 11167 .cfi_offset 14, -4 + 11168 0002 94B0 sub sp, sp, #80 + 11169 .LCFI119: + 11170 .cfi_def_cfa_offset 88 + 11171 0004 0446 mov r4, r0 +6003:Middlewares/Third_Party/FatFs/src/ff.c **** putbuff pb; + 11172 .loc 1 6003 2 is_stmt 1 view .LVU3747 +6004:Middlewares/Third_Party/FatFs/src/ff.c **** +6005:Middlewares/Third_Party/FatFs/src/ff.c **** +6006:Middlewares/Third_Party/FatFs/src/ff.c **** putc_init(&pb, fp); + 11173 .loc 1 6006 2 view .LVU3748 + 11174 0006 01A8 add r0, sp, #4 + 11175 .LVL1326: + 11176 .loc 1 6006 2 is_stmt 0 view .LVU3749 + 11177 0008 FFF7FEFF bl putc_init + 11178 .LVL1327: +6007:Middlewares/Third_Party/FatFs/src/ff.c **** putc_bfd(&pb, c); /* Put the character */ + 11179 .loc 1 6007 2 is_stmt 1 view .LVU3750 + 11180 000c 2146 mov r1, r4 + 11181 000e 01A8 add r0, sp, #4 + 11182 0010 FFF7FEFF bl putc_bfd + 11183 .LVL1328: +6008:Middlewares/Third_Party/FatFs/src/ff.c **** return putc_flush(&pb); + 11184 .loc 1 6008 2 view .LVU3751 + 11185 .loc 1 6008 9 is_stmt 0 view .LVU3752 + 11186 0014 01A8 add r0, sp, #4 + 11187 0016 FFF7FEFF bl putc_flush + 11188 .LVL1329: +6009:Middlewares/Third_Party/FatFs/src/ff.c **** } + 11189 .loc 1 6009 1 view .LVU3753 + 11190 001a 14B0 add sp, sp, #80 + 11191 .LCFI120: + 11192 .cfi_def_cfa_offset 8 + 11193 @ sp needed + 11194 001c 10BD pop {r4, pc} + 11195 .loc 1 6009 1 view .LVU3754 + 11196 .cfi_endproc + 11197 .LFE1242: + 11199 .section .text.f_puts,"ax",%progbits + 11200 .align 1 + 11201 .global f_puts + 11202 .syntax unified + 11203 .thumb + 11204 .thumb_func + 11206 f_puts: + 11207 .LVL1330: + 11208 .LFB1243: +6010:Middlewares/Third_Party/FatFs/src/ff.c **** +6011:Middlewares/Third_Party/FatFs/src/ff.c **** +6012:Middlewares/Third_Party/FatFs/src/ff.c **** +6013:Middlewares/Third_Party/FatFs/src/ff.c **** +6014:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +6015:Middlewares/Third_Party/FatFs/src/ff.c **** /* Put a string to the file */ +6016:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +6017:Middlewares/Third_Party/FatFs/src/ff.c **** + ARM GAS /tmp/cc2SVLkL.s page 361 + + +6018:Middlewares/Third_Party/FatFs/src/ff.c **** int f_puts ( +6019:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* str, /* Pointer to the string to be output */ +6020:Middlewares/Third_Party/FatFs/src/ff.c **** FIL* fp /* Pointer to the file object */ +6021:Middlewares/Third_Party/FatFs/src/ff.c **** ) +6022:Middlewares/Third_Party/FatFs/src/ff.c **** { + 11209 .loc 1 6022 1 is_stmt 1 view -0 + 11210 .cfi_startproc + 11211 @ args = 0, pretend = 0, frame = 80 + 11212 @ frame_needed = 0, uses_anonymous_args = 0 + 11213 .loc 1 6022 1 is_stmt 0 view .LVU3756 + 11214 0000 10B5 push {r4, lr} + 11215 .LCFI121: + 11216 .cfi_def_cfa_offset 8 + 11217 .cfi_offset 4, -8 + 11218 .cfi_offset 14, -4 + 11219 0002 94B0 sub sp, sp, #80 + 11220 .LCFI122: + 11221 .cfi_def_cfa_offset 88 + 11222 0004 0446 mov r4, r0 +6023:Middlewares/Third_Party/FatFs/src/ff.c **** putbuff pb; + 11223 .loc 1 6023 2 is_stmt 1 view .LVU3757 +6024:Middlewares/Third_Party/FatFs/src/ff.c **** +6025:Middlewares/Third_Party/FatFs/src/ff.c **** +6026:Middlewares/Third_Party/FatFs/src/ff.c **** putc_init(&pb, fp); + 11224 .loc 1 6026 2 view .LVU3758 + 11225 0006 01A8 add r0, sp, #4 + 11226 .LVL1331: + 11227 .loc 1 6026 2 is_stmt 0 view .LVU3759 + 11228 0008 FFF7FEFF bl putc_init + 11229 .LVL1332: +6027:Middlewares/Third_Party/FatFs/src/ff.c **** while (*str) putc_bfd(&pb, *str++); /* Put the string */ + 11230 .loc 1 6027 2 is_stmt 1 view .LVU3760 + 11231 .loc 1 6027 8 is_stmt 0 view .LVU3761 + 11232 000c 03E0 b .L810 + 11233 .L811: + 11234 .loc 1 6027 15 is_stmt 1 discriminator 2 view .LVU3762 + 11235 .loc 1 6027 33 is_stmt 0 discriminator 2 view .LVU3763 + 11236 000e 0134 adds r4, r4, #1 + 11237 .LVL1333: + 11238 .loc 1 6027 15 discriminator 2 view .LVU3764 + 11239 0010 01A8 add r0, sp, #4 + 11240 0012 FFF7FEFF bl putc_bfd + 11241 .LVL1334: + 11242 .L810: + 11243 .loc 1 6027 9 is_stmt 1 discriminator 1 view .LVU3765 + 11244 0016 2178 ldrb r1, [r4] @ zero_extendqisi2 + 11245 0018 0029 cmp r1, #0 + 11246 001a F8D1 bne .L811 +6028:Middlewares/Third_Party/FatFs/src/ff.c **** return putc_flush(&pb); + 11247 .loc 1 6028 2 view .LVU3766 + 11248 .loc 1 6028 9 is_stmt 0 view .LVU3767 + 11249 001c 01A8 add r0, sp, #4 + 11250 001e FFF7FEFF bl putc_flush + 11251 .LVL1335: +6029:Middlewares/Third_Party/FatFs/src/ff.c **** } + 11252 .loc 1 6029 1 view .LVU3768 + 11253 0022 14B0 add sp, sp, #80 + ARM GAS /tmp/cc2SVLkL.s page 362 + + + 11254 .LCFI123: + 11255 .cfi_def_cfa_offset 8 + 11256 @ sp needed + 11257 0024 10BD pop {r4, pc} + 11258 .loc 1 6029 1 view .LVU3769 + 11259 .cfi_endproc + 11260 .LFE1243: + 11262 .section .text.f_printf,"ax",%progbits + 11263 .align 1 + 11264 .global f_printf + 11265 .syntax unified + 11266 .thumb + 11267 .thumb_func + 11269 f_printf: + 11270 .LVL1336: + 11271 .LFB1244: +6030:Middlewares/Third_Party/FatFs/src/ff.c **** +6031:Middlewares/Third_Party/FatFs/src/ff.c **** +6032:Middlewares/Third_Party/FatFs/src/ff.c **** +6033:Middlewares/Third_Party/FatFs/src/ff.c **** +6034:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +6035:Middlewares/Third_Party/FatFs/src/ff.c **** /* Put a formatted string to the file */ +6036:Middlewares/Third_Party/FatFs/src/ff.c **** /*-----------------------------------------------------------------------*/ +6037:Middlewares/Third_Party/FatFs/src/ff.c **** +6038:Middlewares/Third_Party/FatFs/src/ff.c **** int f_printf ( +6039:Middlewares/Third_Party/FatFs/src/ff.c **** FIL* fp, /* Pointer to the file object */ +6040:Middlewares/Third_Party/FatFs/src/ff.c **** const TCHAR* fmt, /* Pointer to the format string */ +6041:Middlewares/Third_Party/FatFs/src/ff.c **** ... /* Optional arguments... */ +6042:Middlewares/Third_Party/FatFs/src/ff.c **** ) +6043:Middlewares/Third_Party/FatFs/src/ff.c **** { + 11272 .loc 1 6043 1 is_stmt 1 view -0 + 11273 .cfi_startproc + 11274 @ args = 4, pretend = 12, frame = 112 + 11275 @ frame_needed = 0, uses_anonymous_args = 1 + 11276 .loc 1 6043 1 is_stmt 0 view .LVU3771 + 11277 0000 0EB4 push {r1, r2, r3} + 11278 .LCFI124: + 11279 .cfi_def_cfa_offset 12 + 11280 .cfi_offset 1, -12 + 11281 .cfi_offset 2, -8 + 11282 .cfi_offset 3, -4 + 11283 0002 2DE9F047 push {r4, r5, r6, r7, r8, r9, r10, lr} + 11284 .LCFI125: + 11285 .cfi_def_cfa_offset 44 + 11286 .cfi_offset 4, -44 + 11287 .cfi_offset 5, -40 + 11288 .cfi_offset 6, -36 + 11289 .cfi_offset 7, -32 + 11290 .cfi_offset 8, -28 + 11291 .cfi_offset 9, -24 + 11292 .cfi_offset 10, -20 + 11293 .cfi_offset 14, -16 + 11294 0006 9DB0 sub sp, sp, #116 + 11295 .LCFI126: + 11296 .cfi_def_cfa_offset 160 + 11297 0008 0146 mov r1, r0 + 11298 000a 25AC add r4, sp, #148 + ARM GAS /tmp/cc2SVLkL.s page 363 + + + 11299 000c 54F8045B ldr r5, [r4], #4 +6044:Middlewares/Third_Party/FatFs/src/ff.c **** va_list arp; + 11300 .loc 1 6044 2 is_stmt 1 view .LVU3772 +6045:Middlewares/Third_Party/FatFs/src/ff.c **** putbuff pb; + 11301 .loc 1 6045 2 view .LVU3773 +6046:Middlewares/Third_Party/FatFs/src/ff.c **** BYTE f, r; + 11302 .loc 1 6046 2 view .LVU3774 +6047:Middlewares/Third_Party/FatFs/src/ff.c **** UINT i, j, w; + 11303 .loc 1 6047 2 view .LVU3775 +6048:Middlewares/Third_Party/FatFs/src/ff.c **** DWORD v; + 11304 .loc 1 6048 2 view .LVU3776 +6049:Middlewares/Third_Party/FatFs/src/ff.c **** TCHAR c, d, str[32], *p; + 11305 .loc 1 6049 2 view .LVU3777 +6050:Middlewares/Third_Party/FatFs/src/ff.c **** +6051:Middlewares/Third_Party/FatFs/src/ff.c **** +6052:Middlewares/Third_Party/FatFs/src/ff.c **** putc_init(&pb, fp); + 11306 .loc 1 6052 2 view .LVU3778 + 11307 0010 08A8 add r0, sp, #32 + 11308 .LVL1337: + 11309 .loc 1 6052 2 is_stmt 0 view .LVU3779 + 11310 0012 FFF7FEFF bl putc_init + 11311 .LVL1338: +6053:Middlewares/Third_Party/FatFs/src/ff.c **** +6054:Middlewares/Third_Party/FatFs/src/ff.c **** va_start(arp, fmt); + 11312 .loc 1 6054 2 is_stmt 1 view .LVU3780 + 11313 0016 1B94 str r4, [sp, #108] + 11314 .LVL1339: + 11315 .L814: +6055:Middlewares/Third_Party/FatFs/src/ff.c **** +6056:Middlewares/Third_Party/FatFs/src/ff.c **** for (;;) { + 11316 .loc 1 6056 2 view .LVU3781 +6057:Middlewares/Third_Party/FatFs/src/ff.c **** c = *fmt++; + 11317 .loc 1 6057 3 view .LVU3782 + 11318 .loc 1 6057 11 is_stmt 0 view .LVU3783 + 11319 0018 2C46 mov r4, r5 + 11320 .LVL1340: + 11321 .loc 1 6057 5 view .LVU3784 + 11322 001a 14F8011B ldrb r1, [r4], #1 @ zero_extendqisi2 + 11323 .LVL1341: +6058:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == 0) break; /* End of string */ + 11324 .loc 1 6058 3 is_stmt 1 view .LVU3785 + 11325 .loc 1 6058 6 is_stmt 0 view .LVU3786 + 11326 001e 0029 cmp r1, #0 + 11327 0020 00F00881 beq .L815 +6059:Middlewares/Third_Party/FatFs/src/ff.c **** if (c != '%') { /* Non escape character */ + 11328 .loc 1 6059 3 is_stmt 1 view .LVU3787 + 11329 .loc 1 6059 6 is_stmt 0 view .LVU3788 + 11330 0024 2529 cmp r1, #37 + 11331 0026 04D0 beq .L816 +6060:Middlewares/Third_Party/FatFs/src/ff.c **** putc_bfd(&pb, c); + 11332 .loc 1 6060 4 is_stmt 1 view .LVU3789 + 11333 0028 08A8 add r0, sp, #32 + 11334 002a FFF7FEFF bl putc_bfd + 11335 .LVL1342: +6061:Middlewares/Third_Party/FatFs/src/ff.c **** continue; + 11336 .loc 1 6061 4 view .LVU3790 +6057:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == 0) break; /* End of string */ + ARM GAS /tmp/cc2SVLkL.s page 364 + + + 11337 .loc 1 6057 11 is_stmt 0 view .LVU3791 + 11338 002e 2546 mov r5, r4 + 11339 .loc 1 6061 4 view .LVU3792 + 11340 0030 F2E7 b .L814 + 11341 .LVL1343: + 11342 .L816: +6062:Middlewares/Third_Party/FatFs/src/ff.c **** } +6063:Middlewares/Third_Party/FatFs/src/ff.c **** w = f = 0; + 11343 .loc 1 6063 3 is_stmt 1 view .LVU3793 +6064:Middlewares/Third_Party/FatFs/src/ff.c **** c = *fmt++; + 11344 .loc 1 6064 3 view .LVU3794 + 11345 .loc 1 6064 11 is_stmt 0 view .LVU3795 + 11346 0032 AB1C adds r3, r5, #2 + 11347 .LVL1344: + 11348 .loc 1 6064 5 view .LVU3796 + 11349 0034 2178 ldrb r1, [r4] @ zero_extendqisi2 + 11350 .LVL1345: +6065:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == '0') { /* Flag: '0' padding */ + 11351 .loc 1 6065 3 is_stmt 1 view .LVU3797 + 11352 .loc 1 6065 6 is_stmt 0 view .LVU3798 + 11353 0036 3029 cmp r1, #48 + 11354 0038 05D0 beq .L865 +6066:Middlewares/Third_Party/FatFs/src/ff.c **** f = 1; c = *fmt++; +6067:Middlewares/Third_Party/FatFs/src/ff.c **** } else { +6068:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == '-') { /* Flag: left justified */ + 11355 .loc 1 6068 4 is_stmt 1 view .LVU3799 + 11356 .loc 1 6068 7 is_stmt 0 view .LVU3800 + 11357 003a 2D29 cmp r1, #45 + 11358 003c 07D0 beq .L866 +6064:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == '0') { /* Flag: '0' padding */ + 11359 .loc 1 6064 11 view .LVU3801 + 11360 003e 1D46 mov r5, r3 +6063:Middlewares/Third_Party/FatFs/src/ff.c **** c = *fmt++; + 11361 .loc 1 6063 9 view .LVU3802 + 11362 0040 0026 movs r6, #0 + 11363 .LVL1346: + 11364 .L819: +6066:Middlewares/Third_Party/FatFs/src/ff.c **** f = 1; c = *fmt++; + 11365 .loc 1 6066 6 view .LVU3803 + 11366 0042 0024 movs r4, #0 + 11367 0044 0EE0 b .L820 + 11368 .LVL1347: + 11369 .L865: +6066:Middlewares/Third_Party/FatFs/src/ff.c **** f = 1; c = *fmt++; + 11370 .loc 1 6066 4 is_stmt 1 view .LVU3804 +6066:Middlewares/Third_Party/FatFs/src/ff.c **** f = 1; c = *fmt++; + 11371 .loc 1 6066 11 view .LVU3805 +6066:Middlewares/Third_Party/FatFs/src/ff.c **** f = 1; c = *fmt++; + 11372 .loc 1 6066 19 is_stmt 0 view .LVU3806 + 11373 0046 0335 adds r5, r5, #3 + 11374 .LVL1348: +6066:Middlewares/Third_Party/FatFs/src/ff.c **** f = 1; c = *fmt++; + 11375 .loc 1 6066 13 view .LVU3807 + 11376 0048 6178 ldrb r1, [r4, #1] @ zero_extendqisi2 + 11377 .LVL1349: +6066:Middlewares/Third_Party/FatFs/src/ff.c **** f = 1; c = *fmt++; + 11378 .loc 1 6066 6 view .LVU3808 + ARM GAS /tmp/cc2SVLkL.s page 365 + + + 11379 004a 0126 movs r6, #1 + 11380 004c F9E7 b .L819 + 11381 .LVL1350: + 11382 .L866: +6069:Middlewares/Third_Party/FatFs/src/ff.c **** f = 2; c = *fmt++; + 11383 .loc 1 6069 5 is_stmt 1 view .LVU3809 + 11384 .loc 1 6069 12 view .LVU3810 + 11385 .loc 1 6069 20 is_stmt 0 view .LVU3811 + 11386 004e 0335 adds r5, r5, #3 + 11387 .LVL1351: + 11388 .loc 1 6069 14 view .LVU3812 + 11389 0050 6178 ldrb r1, [r4, #1] @ zero_extendqisi2 + 11390 .LVL1352: + 11391 .loc 1 6069 7 view .LVU3813 + 11392 0052 0226 movs r6, #2 + 11393 0054 F5E7 b .L819 + 11394 .LVL1353: + 11395 .L821: +6070:Middlewares/Third_Party/FatFs/src/ff.c **** } +6071:Middlewares/Third_Party/FatFs/src/ff.c **** } +6072:Middlewares/Third_Party/FatFs/src/ff.c **** while (IsDigit(c)) { /* Precision */ +6073:Middlewares/Third_Party/FatFs/src/ff.c **** w = w * 10 + c - '0'; + 11396 .loc 1 6073 4 is_stmt 1 view .LVU3814 + 11397 .loc 1 6073 10 is_stmt 0 view .LVU3815 + 11398 0056 04EB8404 add r4, r4, r4, lsl #2 + 11399 .LVL1354: + 11400 .loc 1 6073 15 view .LVU3816 + 11401 005a 01EB4404 add r4, r1, r4, lsl #1 + 11402 .loc 1 6073 6 view .LVU3817 + 11403 005e 303C subs r4, r4, #48 + 11404 .LVL1355: +6074:Middlewares/Third_Party/FatFs/src/ff.c **** c = *fmt++; + 11405 .loc 1 6074 4 is_stmt 1 view .LVU3818 + 11406 .loc 1 6074 6 is_stmt 0 view .LVU3819 + 11407 0060 15F8011B ldrb r1, [r5], #1 @ zero_extendqisi2 + 11408 .LVL1356: + 11409 .L820: +6072:Middlewares/Third_Party/FatFs/src/ff.c **** w = w * 10 + c - '0'; + 11410 .loc 1 6072 10 is_stmt 1 view .LVU3820 + 11411 0064 A1F13003 sub r3, r1, #48 + 11412 0068 DBB2 uxtb r3, r3 + 11413 006a 092B cmp r3, #9 + 11414 006c F3D9 bls .L821 +6075:Middlewares/Third_Party/FatFs/src/ff.c **** } +6076:Middlewares/Third_Party/FatFs/src/ff.c **** if (c == 'l' || c == 'L') { /* Prefix: Size is long int */ + 11415 .loc 1 6076 3 view .LVU3821 + 11416 .loc 1 6076 6 is_stmt 0 view .LVU3822 + 11417 006e 4C29 cmp r1, #76 + 11418 0070 18BF it ne + 11419 0072 6C29 cmpne r1, #108 + 11420 0074 03D1 bne .L822 +6077:Middlewares/Third_Party/FatFs/src/ff.c **** f |= 4; c = *fmt++; + 11421 .loc 1 6077 4 is_stmt 1 view .LVU3823 + 11422 .loc 1 6077 6 is_stmt 0 view .LVU3824 + 11423 0076 46F00406 orr r6, r6, #4 + 11424 .LVL1357: + 11425 .loc 1 6077 12 is_stmt 1 view .LVU3825 + ARM GAS /tmp/cc2SVLkL.s page 366 + + + 11426 .loc 1 6077 14 is_stmt 0 view .LVU3826 + 11427 007a 15F8011B ldrb r1, [r5], #1 @ zero_extendqisi2 + 11428 .LVL1358: + 11429 .L822: +6078:Middlewares/Third_Party/FatFs/src/ff.c **** } +6079:Middlewares/Third_Party/FatFs/src/ff.c **** if (!c) break; + 11430 .loc 1 6079 3 is_stmt 1 view .LVU3827 + 11431 .loc 1 6079 6 is_stmt 0 view .LVU3828 + 11432 007e 0029 cmp r1, #0 + 11433 0080 00F0D880 beq .L815 +6080:Middlewares/Third_Party/FatFs/src/ff.c **** d = c; + 11434 .loc 1 6080 3 is_stmt 1 view .LVU3829 + 11435 .LVL1359: +6081:Middlewares/Third_Party/FatFs/src/ff.c **** if (IsLower(d)) d -= 0x20; + 11436 .loc 1 6081 3 view .LVU3830 + 11437 .loc 1 6081 7 is_stmt 0 view .LVU3831 + 11438 0084 A1F16103 sub r3, r1, #97 + 11439 0088 DBB2 uxtb r3, r3 + 11440 .loc 1 6081 6 view .LVU3832 + 11441 008a 192B cmp r3, #25 + 11442 008c 14D8 bhi .L858 + 11443 .loc 1 6081 19 is_stmt 1 discriminator 1 view .LVU3833 + 11444 .loc 1 6081 21 is_stmt 0 discriminator 1 view .LVU3834 + 11445 008e A1F12003 sub r3, r1, #32 + 11446 0092 DBB2 uxtb r3, r3 + 11447 .LVL1360: + 11448 .L823: +6082:Middlewares/Third_Party/FatFs/src/ff.c **** switch (d) { /* Type is... */ + 11449 .loc 1 6082 3 is_stmt 1 view .LVU3835 + 11450 0094 A3F14202 sub r2, r3, #66 + 11451 0098 162A cmp r2, #22 + 11452 009a 5DD8 bhi .L824 + 11453 009c DFE802F0 tbb [pc, r2] + 11454 .L826: + 11455 00a0 60 .byte (.L831-.L826)/2 + 11456 00a1 3D .byte (.L830-.L826)/2 + 11457 00a2 45 .byte (.L827-.L826)/2 + 11458 00a3 5C .byte (.L824-.L826)/2 + 11459 00a4 5C .byte (.L824-.L826)/2 + 11460 00a5 5C .byte (.L824-.L826)/2 + 11461 00a6 5C .byte (.L824-.L826)/2 + 11462 00a7 5C .byte (.L824-.L826)/2 + 11463 00a8 5C .byte (.L824-.L826)/2 + 11464 00a9 5C .byte (.L824-.L826)/2 + 11465 00aa 5C .byte (.L824-.L826)/2 + 11466 00ab 5C .byte (.L824-.L826)/2 + 11467 00ac 5C .byte (.L824-.L826)/2 + 11468 00ad 62 .byte (.L859-.L826)/2 + 11469 00ae 5C .byte (.L824-.L826)/2 + 11470 00af 5C .byte (.L824-.L826)/2 + 11471 00b0 5C .byte (.L824-.L826)/2 + 11472 00b1 0E .byte (.L828-.L826)/2 + 11473 00b2 5C .byte (.L824-.L826)/2 + 11474 00b3 45 .byte (.L827-.L826)/2 + 11475 00b4 5C .byte (.L824-.L826)/2 + 11476 00b5 5C .byte (.L824-.L826)/2 + 11477 00b6 5A .byte (.L825-.L826)/2 + ARM GAS /tmp/cc2SVLkL.s page 367 + + + 11478 .LVL1361: + 11479 00b7 00 .p2align 1 + 11480 .L858: +6080:Middlewares/Third_Party/FatFs/src/ff.c **** d = c; + 11481 .loc 1 6080 5 is_stmt 0 view .LVU3836 + 11482 00b8 0B46 mov r3, r1 + 11483 00ba EBE7 b .L823 + 11484 .LVL1362: + 11485 .L828: +6083:Middlewares/Third_Party/FatFs/src/ff.c **** case 'S' : /* String */ +6084:Middlewares/Third_Party/FatFs/src/ff.c **** p = va_arg(arp, TCHAR*); + 11486 .loc 1 6084 4 is_stmt 1 view .LVU3837 + 11487 .loc 1 6084 6 is_stmt 0 view .LVU3838 + 11488 00bc 1B9B ldr r3, [sp, #108] + 11489 .LVL1363: + 11490 .loc 1 6084 6 view .LVU3839 + 11491 00be 1A1D adds r2, r3, #4 + 11492 .LVL1364: + 11493 .loc 1 6084 6 view .LVU3840 + 11494 00c0 1B92 str r2, [sp, #108] + 11495 00c2 D3F80080 ldr r8, [r3] +6085:Middlewares/Third_Party/FatFs/src/ff.c **** for (j = 0; p[j]; j++) ; + 11496 .loc 1 6085 4 is_stmt 1 view .LVU3841 + 11497 .LVL1365: + 11498 .loc 1 6085 11 is_stmt 0 view .LVU3842 + 11499 00c6 0027 movs r7, #0 + 11500 .loc 1 6085 4 view .LVU3843 + 11501 00c8 00E0 b .L832 + 11502 .LVL1366: + 11503 .L833: + 11504 .loc 1 6085 23 is_stmt 1 discriminator 3 view .LVU3844 + 11505 00ca 0137 adds r7, r7, #1 + 11506 .LVL1367: + 11507 .L832: + 11508 .loc 1 6085 16 discriminator 1 view .LVU3845 + 11509 .loc 1 6085 17 is_stmt 0 discriminator 1 view .LVU3846 + 11510 00cc 18F80730 ldrb r3, [r8, r7] @ zero_extendqisi2 + 11511 .loc 1 6085 16 discriminator 1 view .LVU3847 + 11512 00d0 002B cmp r3, #0 + 11513 00d2 FAD1 bne .L833 +6086:Middlewares/Third_Party/FatFs/src/ff.c **** if (!(f & 2)) { + 11514 .loc 1 6086 4 is_stmt 1 view .LVU3848 + 11515 .loc 1 6086 7 is_stmt 0 view .LVU3849 + 11516 00d4 16F0020F tst r6, #2 + 11517 00d8 10D1 bne .L837 + 11518 00da 05E0 b .L834 + 11519 .LVL1368: + 11520 .L836: +6087:Middlewares/Third_Party/FatFs/src/ff.c **** while (j++ < w) putc_bfd(&pb, ' '); + 11521 .loc 1 6087 21 is_stmt 1 discriminator 2 view .LVU3850 + 11522 00dc 2021 movs r1, #32 + 11523 00de 0DEB0100 add r0, sp, r1 + 11524 00e2 FFF7FEFF bl putc_bfd + 11525 .LVL1369: + 11526 .loc 1 6087 13 is_stmt 0 discriminator 1 view .LVU3851 + 11527 00e6 3746 mov r7, r6 + 11528 .LVL1370: + ARM GAS /tmp/cc2SVLkL.s page 368 + + + 11529 .L834: + 11530 .loc 1 6087 16 is_stmt 1 discriminator 1 view .LVU3852 + 11531 .loc 1 6087 13 is_stmt 0 discriminator 1 view .LVU3853 + 11532 00e8 7E1C adds r6, r7, #1 + 11533 .LVL1371: + 11534 .loc 1 6087 16 discriminator 1 view .LVU3854 + 11535 00ea A742 cmp r7, r4 + 11536 00ec F6D3 bcc .L836 + 11537 .loc 1 6087 13 discriminator 1 view .LVU3855 + 11538 00ee 3746 mov r7, r6 + 11539 00f0 04E0 b .L837 + 11540 .LVL1372: + 11541 .L838: +6088:Middlewares/Third_Party/FatFs/src/ff.c **** } +6089:Middlewares/Third_Party/FatFs/src/ff.c **** while (*p) putc_bfd(&pb, *p++); + 11542 .loc 1 6089 15 is_stmt 1 discriminator 2 view .LVU3856 + 11543 .loc 1 6089 31 is_stmt 0 discriminator 2 view .LVU3857 + 11544 00f2 08F10108 add r8, r8, #1 + 11545 .LVL1373: + 11546 .loc 1 6089 15 discriminator 2 view .LVU3858 + 11547 00f6 08A8 add r0, sp, #32 + 11548 00f8 FFF7FEFF bl putc_bfd + 11549 .LVL1374: + 11550 .L837: + 11551 .loc 1 6089 11 is_stmt 1 discriminator 1 view .LVU3859 + 11552 00fc 98F80010 ldrb r1, [r8] @ zero_extendqisi2 + 11553 0100 0029 cmp r1, #0 + 11554 0102 F6D1 bne .L838 + 11555 .loc 1 6089 11 is_stmt 0 discriminator 1 view .LVU3860 + 11556 0104 05E0 b .L839 + 11557 .LVL1375: + 11558 .L840: +6090:Middlewares/Third_Party/FatFs/src/ff.c **** while (j++ < w) putc_bfd(&pb, ' '); + 11559 .loc 1 6090 20 is_stmt 1 discriminator 2 view .LVU3861 + 11560 0106 2021 movs r1, #32 + 11561 0108 0DEB0100 add r0, sp, r1 + 11562 010c FFF7FEFF bl putc_bfd + 11563 .LVL1376: + 11564 .loc 1 6090 12 is_stmt 0 discriminator 1 view .LVU3862 + 11565 0110 3746 mov r7, r6 + 11566 .LVL1377: + 11567 .L839: + 11568 .loc 1 6090 15 is_stmt 1 discriminator 1 view .LVU3863 + 11569 .loc 1 6090 12 is_stmt 0 discriminator 1 view .LVU3864 + 11570 0112 7E1C adds r6, r7, #1 + 11571 .LVL1378: + 11572 .loc 1 6090 15 discriminator 1 view .LVU3865 + 11573 0114 A742 cmp r7, r4 + 11574 0116 F6D3 bcc .L840 + 11575 0118 7EE7 b .L814 + 11576 .LVL1379: + 11577 .L830: +6091:Middlewares/Third_Party/FatFs/src/ff.c **** continue; +6092:Middlewares/Third_Party/FatFs/src/ff.c **** +6093:Middlewares/Third_Party/FatFs/src/ff.c **** case 'C' : /* Character */ +6094:Middlewares/Third_Party/FatFs/src/ff.c **** putc_bfd(&pb, (TCHAR)va_arg(arp, int)); continue; + 11578 .loc 1 6094 4 is_stmt 1 view .LVU3866 + ARM GAS /tmp/cc2SVLkL.s page 369 + + + 11579 .loc 1 6094 25 is_stmt 0 view .LVU3867 + 11580 011a 1B9B ldr r3, [sp, #108] + 11581 .LVL1380: + 11582 .loc 1 6094 25 view .LVU3868 + 11583 011c 1A1D adds r2, r3, #4 + 11584 .LVL1381: + 11585 .loc 1 6094 25 view .LVU3869 + 11586 011e 1B92 str r2, [sp, #108] + 11587 .loc 1 6094 4 discriminator 1 view .LVU3870 + 11588 0120 1978 ldrb r1, [r3] @ zero_extendqisi2 + 11589 .LVL1382: + 11590 .loc 1 6094 4 discriminator 1 view .LVU3871 + 11591 0122 08A8 add r0, sp, #32 + 11592 0124 FFF7FEFF bl putc_bfd + 11593 .LVL1383: + 11594 .loc 1 6094 44 is_stmt 1 discriminator 2 view .LVU3872 + 11595 .loc 1 6094 44 is_stmt 0 view .LVU3873 + 11596 0128 76E7 b .L814 + 11597 .LVL1384: + 11598 .L827: +6095:Middlewares/Third_Party/FatFs/src/ff.c **** +6096:Middlewares/Third_Party/FatFs/src/ff.c **** case 'B' : /* Binary */ +6097:Middlewares/Third_Party/FatFs/src/ff.c **** r = 2; break; +6098:Middlewares/Third_Party/FatFs/src/ff.c **** +6099:Middlewares/Third_Party/FatFs/src/ff.c **** case 'O' : /* Octal */ +6100:Middlewares/Third_Party/FatFs/src/ff.c **** r = 8; break; +6101:Middlewares/Third_Party/FatFs/src/ff.c **** +6102:Middlewares/Third_Party/FatFs/src/ff.c **** case 'D' : /* Signed decimal */ +6103:Middlewares/Third_Party/FatFs/src/ff.c **** case 'U' : /* Unsigned decimal */ +6104:Middlewares/Third_Party/FatFs/src/ff.c **** r = 10; break; + 11599 .loc 1 6104 4 is_stmt 1 view .LVU3874 + 11600 .loc 1 6104 12 view .LVU3875 + 11601 .loc 1 6104 6 is_stmt 0 view .LVU3876 + 11602 012a 0A20 movs r0, #10 + 11603 .LVL1385: + 11604 .L829: +6105:Middlewares/Third_Party/FatFs/src/ff.c **** +6106:Middlewares/Third_Party/FatFs/src/ff.c **** case 'X' : /* Hexdecimal */ +6107:Middlewares/Third_Party/FatFs/src/ff.c **** r = 16; break; +6108:Middlewares/Third_Party/FatFs/src/ff.c **** +6109:Middlewares/Third_Party/FatFs/src/ff.c **** default: /* Unknown type (pass-through) */ +6110:Middlewares/Third_Party/FatFs/src/ff.c **** putc_bfd(&pb, c); continue; +6111:Middlewares/Third_Party/FatFs/src/ff.c **** } +6112:Middlewares/Third_Party/FatFs/src/ff.c **** +6113:Middlewares/Third_Party/FatFs/src/ff.c **** /* Get an argument and put it in numeral */ +6114:Middlewares/Third_Party/FatFs/src/ff.c **** v = (f & 4) ? (DWORD)va_arg(arp, long) : ((d == 'D') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_ + 11605 .loc 1 6114 3 is_stmt 1 view .LVU3877 + 11606 .loc 1 6114 42 is_stmt 0 view .LVU3878 + 11607 012c 16F0040F tst r6, #4 + 11608 0130 1AD0 beq .L841 + 11609 .loc 1 6114 24 discriminator 1 view .LVU3879 + 11610 0132 1B9A ldr r2, [sp, #108] + 11611 0134 171D adds r7, r2, #4 + 11612 0136 1B97 str r7, [sp, #108] + 11613 0138 1268 ldr r2, [r2] + 11614 .L842: + 11615 .LVL1386: + ARM GAS /tmp/cc2SVLkL.s page 370 + + +6115:Middlewares/Third_Party/FatFs/src/ff.c **** if (d == 'D' && (v & 0x80000000)) { + 11616 .loc 1 6115 3 is_stmt 1 view .LVU3880 + 11617 .loc 1 6115 16 is_stmt 0 view .LVU3881 + 11618 013a D70F lsrs r7, r2, #31 + 11619 013c 442B cmp r3, #68 + 11620 013e 14BF ite ne + 11621 0140 0027 movne r7, #0 + 11622 0142 07F00107 andeq r7, r7, #1 + 11623 .loc 1 6115 6 view .LVU3882 + 11624 0146 17B1 cbz r7, .L844 +6116:Middlewares/Third_Party/FatFs/src/ff.c **** v = 0 - v; + 11625 .loc 1 6116 4 is_stmt 1 view .LVU3883 + 11626 .loc 1 6116 6 is_stmt 0 view .LVU3884 + 11627 0148 5242 rsbs r2, r2, #0 + 11628 .LVL1387: +6117:Middlewares/Third_Party/FatFs/src/ff.c **** f |= 8; + 11629 .loc 1 6117 4 is_stmt 1 view .LVU3885 + 11630 .loc 1 6117 6 is_stmt 0 view .LVU3886 + 11631 014a 46F00806 orr r6, r6, #8 + 11632 .LVL1388: + 11633 .L844: +6118:Middlewares/Third_Party/FatFs/src/ff.c **** } +6119:Middlewares/Third_Party/FatFs/src/ff.c **** i = 0; + 11634 .loc 1 6119 3 is_stmt 1 view .LVU3887 + 11635 .loc 1 6119 5 is_stmt 0 view .LVU3888 + 11636 014e 4FF0000C mov ip, #0 + 11637 0152 28E0 b .L847 + 11638 .LVL1389: + 11639 .L825: +6107:Middlewares/Third_Party/FatFs/src/ff.c **** + 11640 .loc 1 6107 4 is_stmt 1 view .LVU3889 +6107:Middlewares/Third_Party/FatFs/src/ff.c **** + 11641 .loc 1 6107 12 view .LVU3890 +6107:Middlewares/Third_Party/FatFs/src/ff.c **** + 11642 .loc 1 6107 6 is_stmt 0 view .LVU3891 + 11643 0154 1020 movs r0, #16 +6107:Middlewares/Third_Party/FatFs/src/ff.c **** + 11644 .loc 1 6107 12 view .LVU3892 + 11645 0156 E9E7 b .L829 + 11646 .LVL1390: + 11647 .L824: +6110:Middlewares/Third_Party/FatFs/src/ff.c **** } + 11648 .loc 1 6110 4 is_stmt 1 view .LVU3893 + 11649 0158 08A8 add r0, sp, #32 + 11650 015a FFF7FEFF bl putc_bfd + 11651 .LVL1391: +6110:Middlewares/Third_Party/FatFs/src/ff.c **** } + 11652 .loc 1 6110 22 discriminator 1 view .LVU3894 +6110:Middlewares/Third_Party/FatFs/src/ff.c **** } + 11653 .loc 1 6110 22 is_stmt 0 view .LVU3895 + 11654 015e 5BE7 b .L814 + 11655 .LVL1392: + 11656 .L831: +6082:Middlewares/Third_Party/FatFs/src/ff.c **** case 'S' : /* String */ + 11657 .loc 1 6082 3 view .LVU3896 + 11658 0160 0220 movs r0, #2 + 11659 0162 E3E7 b .L829 + ARM GAS /tmp/cc2SVLkL.s page 371 + + + 11660 .L859: +6100:Middlewares/Third_Party/FatFs/src/ff.c **** + 11661 .loc 1 6100 6 view .LVU3897 + 11662 0164 0820 movs r0, #8 + 11663 0166 E1E7 b .L829 + 11664 .LVL1393: + 11665 .L841: +6114:Middlewares/Third_Party/FatFs/src/ff.c **** if (d == 'D' && (v & 0x80000000)) { + 11666 .loc 1 6114 88 discriminator 2 view .LVU3898 + 11667 0168 442B cmp r3, #68 + 11668 016a 04D0 beq .L867 +6114:Middlewares/Third_Party/FatFs/src/ff.c **** if (d == 'D' && (v & 0x80000000)) { + 11669 .loc 1 6114 88 discriminator 5 view .LVU3899 + 11670 016c 1B9A ldr r2, [sp, #108] + 11671 016e 171D adds r7, r2, #4 + 11672 0170 1B97 str r7, [sp, #108] + 11673 0172 1268 ldr r2, [r2] + 11674 0174 E1E7 b .L842 + 11675 .L867: +6114:Middlewares/Third_Party/FatFs/src/ff.c **** if (d == 'D' && (v & 0x80000000)) { + 11676 .loc 1 6114 71 discriminator 4 view .LVU3900 + 11677 0176 1B9A ldr r2, [sp, #108] + 11678 0178 171D adds r7, r2, #4 + 11679 017a 1B97 str r7, [sp, #108] + 11680 017c 1268 ldr r2, [r2] + 11681 017e DCE7 b .L842 + 11682 .LVL1394: + 11683 .L868: +6120:Middlewares/Third_Party/FatFs/src/ff.c **** do { +6121:Middlewares/Third_Party/FatFs/src/ff.c **** d = (TCHAR)(v % r); v /= r; +6122:Middlewares/Third_Party/FatFs/src/ff.c **** if (d > 9) d += (c == 'x') ? 0x27 : 0x07; + 11684 .loc 1 6122 17 discriminator 2 view .LVU3901 + 11685 0180 2727 movs r7, #39 + 11686 .L846: + 11687 .loc 1 6122 17 discriminator 5 view .LVU3902 + 11688 0182 3B44 add r3, r3, r7 + 11689 .LVL1395: + 11690 .loc 1 6122 17 discriminator 5 view .LVU3903 + 11691 0184 DBB2 uxtb r3, r3 + 11692 .LVL1396: + 11693 .L845: +6123:Middlewares/Third_Party/FatFs/src/ff.c **** str[i++] = d + '0'; + 11694 .loc 1 6123 4 is_stmt 1 view .LVU3904 + 11695 .loc 1 6123 9 is_stmt 0 view .LVU3905 + 11696 0186 0CF10107 add r7, ip, #1 + 11697 .LVL1397: + 11698 .loc 1 6123 17 view .LVU3906 + 11699 018a 3033 adds r3, r3, #48 + 11700 .LVL1398: + 11701 .loc 1 6123 13 view .LVU3907 + 11702 018c 0CF17009 add r9, ip, #112 + 11703 0190 E944 add r9, sp, r9 + 11704 0192 09F8703C strb r3, [r9, #-112] +6124:Middlewares/Third_Party/FatFs/src/ff.c **** } while (v && i < sizeof str / sizeof str[0]); + 11705 .loc 1 6124 14 is_stmt 1 view .LVU3908 + 11706 .loc 1 6124 19 is_stmt 0 view .LVU3909 + 11707 0196 1F2F cmp r7, #31 + ARM GAS /tmp/cc2SVLkL.s page 372 + + + 11708 0198 8CBF ite hi + 11709 019a 0023 movhi r3, #0 + 11710 .LVL1399: + 11711 .loc 1 6124 19 view .LVU3910 + 11712 019c 0123 movls r3, #1 + 11713 .loc 1 6124 14 view .LVU3911 + 11714 019e C645 cmp lr, r8 + 11715 01a0 0FD8 bhi .L863 + 11716 01a2 73B1 cbz r3, .L863 +6123:Middlewares/Third_Party/FatFs/src/ff.c **** str[i++] = d + '0'; + 11717 .loc 1 6123 9 view .LVU3912 + 11718 01a4 BC46 mov ip, r7 + 11719 .LVL1400: + 11720 .L847: +6120:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 11721 .loc 1 6120 3 is_stmt 1 view .LVU3913 +6121:Middlewares/Third_Party/FatFs/src/ff.c **** if (d > 9) d += (c == 'x') ? 0x27 : 0x07; + 11722 .loc 1 6121 4 view .LVU3914 +6121:Middlewares/Third_Party/FatFs/src/ff.c **** if (d > 9) d += (c == 'x') ? 0x27 : 0x07; + 11723 .loc 1 6121 18 is_stmt 0 view .LVU3915 + 11724 01a6 8646 mov lr, r0 + 11725 01a8 B2FBF0F7 udiv r7, r2, r0 + 11726 01ac 00FB1723 mls r3, r0, r7, r2 +6121:Middlewares/Third_Party/FatFs/src/ff.c **** if (d > 9) d += (c == 'x') ? 0x27 : 0x07; + 11727 .loc 1 6121 6 view .LVU3916 + 11728 01b0 DBB2 uxtb r3, r3 + 11729 .LVL1401: +6121:Middlewares/Third_Party/FatFs/src/ff.c **** if (d > 9) d += (c == 'x') ? 0x27 : 0x07; + 11730 .loc 1 6121 24 is_stmt 1 view .LVU3917 + 11731 01b2 9046 mov r8, r2 +6121:Middlewares/Third_Party/FatFs/src/ff.c **** if (d > 9) d += (c == 'x') ? 0x27 : 0x07; + 11732 .loc 1 6121 26 is_stmt 0 view .LVU3918 + 11733 01b4 3A46 mov r2, r7 + 11734 .LVL1402: +6122:Middlewares/Third_Party/FatFs/src/ff.c **** str[i++] = d + '0'; + 11735 .loc 1 6122 4 is_stmt 1 view .LVU3919 +6122:Middlewares/Third_Party/FatFs/src/ff.c **** str[i++] = d + '0'; + 11736 .loc 1 6122 7 is_stmt 0 view .LVU3920 + 11737 01b6 092B cmp r3, #9 + 11738 01b8 E5D9 bls .L845 +6122:Middlewares/Third_Party/FatFs/src/ff.c **** str[i++] = d + '0'; + 11739 .loc 1 6122 15 is_stmt 1 discriminator 1 view .LVU3921 +6122:Middlewares/Third_Party/FatFs/src/ff.c **** str[i++] = d + '0'; + 11740 .loc 1 6122 17 is_stmt 0 discriminator 1 view .LVU3922 + 11741 01ba 7829 cmp r1, #120 + 11742 01bc E0D0 beq .L868 +6122:Middlewares/Third_Party/FatFs/src/ff.c **** str[i++] = d + '0'; + 11743 .loc 1 6122 17 discriminator 3 view .LVU3923 + 11744 01be 0727 movs r7, #7 + 11745 01c0 DFE7 b .L846 + 11746 .LVL1403: + 11747 .L863: +6125:Middlewares/Third_Party/FatFs/src/ff.c **** if (f & 8) str[i++] = '-'; + 11748 .loc 1 6125 3 is_stmt 1 view .LVU3924 + 11749 .loc 1 6125 6 is_stmt 0 view .LVU3925 + 11750 01c2 16F0080F tst r6, #8 + 11751 01c6 08D0 beq .L849 + ARM GAS /tmp/cc2SVLkL.s page 373 + + + 11752 .loc 1 6125 14 is_stmt 1 discriminator 1 view .LVU3926 + 11753 .LVL1404: + 11754 .loc 1 6125 23 is_stmt 0 discriminator 1 view .LVU3927 + 11755 01c8 07F17003 add r3, r7, #112 + 11756 01cc 0DEB0307 add r7, sp, r3 + 11757 01d0 2D23 movs r3, #45 + 11758 01d2 07F8703C strb r3, [r7, #-112] + 11759 .loc 1 6125 19 discriminator 1 view .LVU3928 + 11760 01d6 0CF10207 add r7, ip, #2 + 11761 .LVL1405: + 11762 .L849: +6126:Middlewares/Third_Party/FatFs/src/ff.c **** j = i; d = (f & 1) ? '0' : ' '; + 11763 .loc 1 6126 3 is_stmt 1 view .LVU3929 + 11764 .loc 1 6126 10 view .LVU3930 + 11765 .loc 1 6126 12 is_stmt 0 view .LVU3931 + 11766 01da 16F0010F tst r6, #1 + 11767 01de 03D0 beq .L862 + 11768 .loc 1 6126 12 discriminator 1 view .LVU3932 + 11769 01e0 4FF0300A mov r10, #48 + 11770 .L850: + 11771 .LVL1406: +6127:Middlewares/Third_Party/FatFs/src/ff.c **** while (!(f & 2) && j++ < w) putc_bfd(&pb, d); + 11772 .loc 1 6127 3 is_stmt 1 view .LVU3933 +6126:Middlewares/Third_Party/FatFs/src/ff.c **** j = i; d = (f & 1) ? '0' : ' '; + 11773 .loc 1 6126 5 is_stmt 0 view .LVU3934 + 11774 01e4 B846 mov r8, r7 + 11775 .loc 1 6127 9 view .LVU3935 + 11776 01e6 07E0 b .L851 + 11777 .LVL1407: + 11778 .L862: +6126:Middlewares/Third_Party/FatFs/src/ff.c **** j = i; d = (f & 1) ? '0' : ' '; + 11779 .loc 1 6126 12 discriminator 2 view .LVU3936 + 11780 01e8 4FF0200A mov r10, #32 + 11781 01ec FAE7 b .L850 + 11782 .LVL1408: + 11783 .L853: + 11784 .loc 1 6127 31 is_stmt 1 discriminator 3 view .LVU3937 + 11785 01ee 5146 mov r1, r10 + 11786 01f0 08A8 add r0, sp, #32 + 11787 01f2 FFF7FEFF bl putc_bfd + 11788 .LVL1409: + 11789 .loc 1 6127 23 is_stmt 0 discriminator 2 view .LVU3938 + 11790 01f6 C846 mov r8, r9 + 11791 .LVL1410: + 11792 .L851: + 11793 .loc 1 6127 19 is_stmt 1 discriminator 1 view .LVU3939 + 11794 01f8 16F0020F tst r6, #2 + 11795 01fc 04D1 bne .L854 + 11796 .loc 1 6127 23 is_stmt 0 discriminator 2 view .LVU3940 + 11797 01fe 08F10109 add r9, r8, #1 + 11798 .LVL1411: + 11799 .loc 1 6127 19 discriminator 2 view .LVU3941 + 11800 0202 A045 cmp r8, r4 + 11801 0204 F3D3 bcc .L853 + 11802 .loc 1 6127 23 discriminator 2 view .LVU3942 + 11803 0206 C846 mov r8, r9 + 11804 .LVL1412: + ARM GAS /tmp/cc2SVLkL.s page 374 + + + 11805 .L854: +6128:Middlewares/Third_Party/FatFs/src/ff.c **** do { + 11806 .loc 1 6128 3 is_stmt 1 view .LVU3943 +6129:Middlewares/Third_Party/FatFs/src/ff.c **** putc_bfd(&pb, str[--i]); + 11807 .loc 1 6129 4 view .LVU3944 + 11808 0208 013F subs r7, r7, #1 + 11809 .LVL1413: + 11810 .loc 1 6129 4 is_stmt 0 view .LVU3945 + 11811 020a 07F17003 add r3, r7, #112 + 11812 020e 6B44 add r3, sp, r3 + 11813 0210 13F8701C ldrb r1, [r3, #-112] @ zero_extendqisi2 + 11814 0214 08A8 add r0, sp, #32 + 11815 0216 FFF7FEFF bl putc_bfd + 11816 .LVL1414: +6130:Middlewares/Third_Party/FatFs/src/ff.c **** } while (i); + 11817 .loc 1 6130 12 is_stmt 1 discriminator 1 view .LVU3946 + 11818 021a 002F cmp r7, #0 + 11819 021c F4D1 bne .L854 + 11820 .LVL1415: + 11821 .L855: +6131:Middlewares/Third_Party/FatFs/src/ff.c **** while (j++ < w) putc_bfd(&pb, d); + 11822 .loc 1 6131 14 discriminator 1 view .LVU3947 + 11823 .loc 1 6131 11 is_stmt 0 discriminator 1 view .LVU3948 + 11824 021e 08F10106 add r6, r8, #1 + 11825 .LVL1416: + 11826 .loc 1 6131 14 discriminator 1 view .LVU3949 + 11827 0222 A045 cmp r8, r4 + 11828 0224 BFF4F8AE bcs .L814 + 11829 .loc 1 6131 19 is_stmt 1 discriminator 2 view .LVU3950 + 11830 0228 5146 mov r1, r10 + 11831 022a 08A8 add r0, sp, #32 + 11832 022c FFF7FEFF bl putc_bfd + 11833 .LVL1417: + 11834 .loc 1 6131 11 is_stmt 0 discriminator 1 view .LVU3951 + 11835 0230 B046 mov r8, r6 + 11836 0232 F4E7 b .L855 + 11837 .LVL1418: + 11838 .L815: +6132:Middlewares/Third_Party/FatFs/src/ff.c **** } +6133:Middlewares/Third_Party/FatFs/src/ff.c **** +6134:Middlewares/Third_Party/FatFs/src/ff.c **** va_end(arp); + 11839 .loc 1 6134 2 is_stmt 1 view .LVU3952 +6135:Middlewares/Third_Party/FatFs/src/ff.c **** +6136:Middlewares/Third_Party/FatFs/src/ff.c **** return putc_flush(&pb); + 11840 .loc 1 6136 2 view .LVU3953 + 11841 .loc 1 6136 9 is_stmt 0 view .LVU3954 + 11842 0234 08A8 add r0, sp, #32 + 11843 0236 FFF7FEFF bl putc_flush + 11844 .LVL1419: +6137:Middlewares/Third_Party/FatFs/src/ff.c **** } + 11845 .loc 1 6137 1 view .LVU3955 + 11846 023a 1DB0 add sp, sp, #116 + 11847 .LCFI127: + 11848 .cfi_def_cfa_offset 44 + 11849 @ sp needed + 11850 023c BDE8F047 pop {r4, r5, r6, r7, r8, r9, r10, lr} + 11851 .LCFI128: + ARM GAS /tmp/cc2SVLkL.s page 375 + + + 11852 .cfi_restore 14 + 11853 .cfi_restore 10 + 11854 .cfi_restore 9 + 11855 .cfi_restore 8 + 11856 .cfi_restore 7 + 11857 .cfi_restore 6 + 11858 .cfi_restore 5 + 11859 .cfi_restore 4 + 11860 .cfi_def_cfa_offset 12 + 11861 0240 03B0 add sp, sp, #12 + 11862 .LCFI129: + 11863 .cfi_restore 3 + 11864 .cfi_restore 2 + 11865 .cfi_restore 1 + 11866 .cfi_def_cfa_offset 0 + 11867 0242 7047 bx lr + 11868 .cfi_endproc + 11869 .LFE1244: + 11871 .section .rodata.cst.0,"a" + 11872 .align 2 + 11875 cst.0: + 11876 0000 0100 .short 1 + 11877 0002 0400 .short 4 + 11878 0004 1000 .short 16 + 11879 0006 4000 .short 64 + 11880 0008 0001 .short 256 + 11881 000a 0002 .short 512 + 11882 000c 0000 .short 0 + 11883 .section .rodata.cst32.1,"a" + 11884 .align 2 + 11887 cst32.1: + 11888 0000 0100 .short 1 + 11889 0002 0200 .short 2 + 11890 0004 0400 .short 4 + 11891 0006 0800 .short 8 + 11892 0008 1000 .short 16 + 11893 000a 2000 .short 32 + 11894 000c 0000 .short 0 + 11895 .section .rodata.ExCvt,"a" + 11896 .align 2 + 11899 ExCvt: + 11900 0000 43554541 .ascii "CUEAAAACEEEIIIAAE\222\222OOOUUYOUO\234O\236\237AIOU" + 11900 41414143 + 11900 45454549 + 11900 49494141 + 11900 4592924F + 11901 0024 A5A5A6A7 .ascii "\245\245\246\247\250\251\252\253\254\255\256\257\260" + 11901 A8A9AAAB + 11901 ACADAEAF + 11901 B0 + 11902 0031 B1B2B3B4 .ascii "\261\262\263\264AAA\270\271\272\273\274\275\276\277" + 11902 414141B8 + 11902 B9BABBBC + 11902 BDBEBF + 11903 0040 C0C1C2C3 .ascii "\300\301\302\303\304\305AA\310\311\312\313\314\315\316" + 11903 C4C54141 + 11903 C8C9CACB + ARM GAS /tmp/cc2SVLkL.s page 376 + + + 11903 CCCDCE + 11904 004f CFD1D145 .ascii "\317\321\321EEEIIII\331\332\333\334\335I\337O\341OO" + 11904 45454949 + 11904 4949D9DA + 11904 DBDCDD49 + 11904 DF4FE14F + 11905 0064 4F4FE6E8 .ascii "OO\346\350\350UUUYY\356\357\360\361\362\363\364\365" + 11905 E8555555 + 11905 5959EEEF + 11905 F0F1F2F3 + 11905 F4F5 + 11906 0076 F6F7F8F9 .ascii "\366\367\370\371\372\373\374\375\376\377" + 11906 FAFBFCFD + 11906 FEFF + 11907 .section .bss.Files,"aw",%nobits + 11908 .align 2 + 11911 Files: + 11912 0000 00000000 .space 32 + 11912 00000000 + 11912 00000000 + 11912 00000000 + 11912 00000000 + 11913 .section .bss.Fsid,"aw",%nobits + 11914 .align 1 + 11917 Fsid: + 11918 0000 0000 .space 2 + 11919 .section .bss.FatFs,"aw",%nobits + 11920 .align 2 + 11923 FatFs: + 11924 0000 00000000 .space 4 + 11925 .text + 11926 .Letext0: + 11927 .file 2 "Middlewares/Third_Party/FatFs/src/integer.h" + 11928 .file 3 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 11929 .file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h" + 11930 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h" + 11931 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h" + 11932 .file 7 "Middlewares/Third_Party/FatFs/src/ff.h" + 11933 .file 8 "Middlewares/Third_Party/FatFs/src/diskio.h" + 11934 .file 9 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdarg.h" + 11935 .file 10 "" + ARM GAS /tmp/cc2SVLkL.s page 377 + + +DEFINED SYMBOLS + *ABS*:00000000 ff.c + /tmp/cc2SVLkL.s:20 .text.ld_word:00000000 $t + /tmp/cc2SVLkL.s:25 .text.ld_word:00000000 ld_word + /tmp/cc2SVLkL.s:52 .text.ld_dword:00000000 $t + /tmp/cc2SVLkL.s:57 .text.ld_dword:00000000 ld_dword + /tmp/cc2SVLkL.s:96 .text.st_word:00000000 $t + /tmp/cc2SVLkL.s:101 .text.st_word:00000000 st_word + /tmp/cc2SVLkL.s:125 .text.st_dword:00000000 $t + /tmp/cc2SVLkL.s:130 .text.st_dword:00000000 st_dword + /tmp/cc2SVLkL.s:169 .text.mem_cpy:00000000 $t + /tmp/cc2SVLkL.s:174 .text.mem_cpy:00000000 mem_cpy + /tmp/cc2SVLkL.s:214 .text.mem_set:00000000 $t + /tmp/cc2SVLkL.s:219 .text.mem_set:00000000 mem_set + /tmp/cc2SVLkL.s:246 .text.mem_cmp:00000000 $t + /tmp/cc2SVLkL.s:251 .text.mem_cmp:00000000 mem_cmp + /tmp/cc2SVLkL.s:294 .text.chk_chr:00000000 $t + /tmp/cc2SVLkL.s:299 .text.chk_chr:00000000 chk_chr + /tmp/cc2SVLkL.s:335 .text.chk_lock:00000000 $t + /tmp/cc2SVLkL.s:340 .text.chk_lock:00000000 chk_lock + /tmp/cc2SVLkL.s:477 .text.chk_lock:00000078 $d + /tmp/cc2SVLkL.s:11911 .bss.Files:00000000 Files + /tmp/cc2SVLkL.s:482 .text.enq_lock:00000000 $t + /tmp/cc2SVLkL.s:487 .text.enq_lock:00000000 enq_lock + /tmp/cc2SVLkL.s:531 .text.enq_lock:0000001c $d + /tmp/cc2SVLkL.s:536 .text.inc_lock:00000000 $t + /tmp/cc2SVLkL.s:541 .text.inc_lock:00000000 inc_lock + /tmp/cc2SVLkL.s:711 .text.inc_lock:0000009c $d + /tmp/cc2SVLkL.s:716 .text.dec_lock:00000000 $t + /tmp/cc2SVLkL.s:721 .text.dec_lock:00000000 dec_lock + /tmp/cc2SVLkL.s:802 .text.dec_lock:0000003c $d + /tmp/cc2SVLkL.s:807 .text.clear_lock:00000000 $t + /tmp/cc2SVLkL.s:812 .text.clear_lock:00000000 clear_lock + /tmp/cc2SVLkL.s:889 .text.clear_lock:00000038 $d + /tmp/cc2SVLkL.s:894 .text.clust2sect:00000000 $t + /tmp/cc2SVLkL.s:899 .text.clust2sect:00000000 clust2sect + /tmp/cc2SVLkL.s:939 .text.clmt_clust:00000000 $t + /tmp/cc2SVLkL.s:944 .text.clmt_clust:00000000 clmt_clust + /tmp/cc2SVLkL.s:1015 .text.ld_clust:00000000 $t + /tmp/cc2SVLkL.s:1020 .text.ld_clust:00000000 ld_clust + /tmp/cc2SVLkL.s:1076 .text.st_clust:00000000 $t + /tmp/cc2SVLkL.s:1081 .text.st_clust:00000000 st_clust + /tmp/cc2SVLkL.s:1130 .text.get_fileinfo:00000000 $t + /tmp/cc2SVLkL.s:1135 .text.get_fileinfo:00000000 get_fileinfo + /tmp/cc2SVLkL.s:1275 .rodata.create_name.str1.4:00000000 $d + /tmp/cc2SVLkL.s:1279 .text.create_name:00000000 $t + /tmp/cc2SVLkL.s:1284 .text.create_name:00000000 create_name + /tmp/cc2SVLkL.s:1516 .text.create_name:000000c8 $d + /tmp/cc2SVLkL.s:11899 .rodata.ExCvt:00000000 ExCvt + /tmp/cc2SVLkL.s:1522 .text.get_ldnumber:00000000 $t + /tmp/cc2SVLkL.s:1527 .text.get_ldnumber:00000000 get_ldnumber + /tmp/cc2SVLkL.s:1628 .text.putc_init:00000000 $t + /tmp/cc2SVLkL.s:1633 .text.putc_init:00000000 putc_init + /tmp/cc2SVLkL.s:1656 .text.validate:00000000 $t + /tmp/cc2SVLkL.s:1661 .text.validate:00000000 validate + /tmp/cc2SVLkL.s:1770 .text.sync_window:00000000 $t + /tmp/cc2SVLkL.s:1775 .text.sync_window:00000000 sync_window + ARM GAS /tmp/cc2SVLkL.s page 378 + + + /tmp/cc2SVLkL.s:1882 .text.move_window:00000000 $t + /tmp/cc2SVLkL.s:1887 .text.move_window:00000000 move_window + /tmp/cc2SVLkL.s:1959 .text.check_fs:00000000 $t + /tmp/cc2SVLkL.s:1964 .text.check_fs:00000000 check_fs + /tmp/cc2SVLkL.s:2060 .text.check_fs:0000006c $d + /tmp/cc2SVLkL.s:2067 .text.find_volume:00000000 $t + /tmp/cc2SVLkL.s:2072 .text.find_volume:00000000 find_volume + /tmp/cc2SVLkL.s:2746 .text.find_volume:00000314 $d + /tmp/cc2SVLkL.s:11923 .bss.FatFs:00000000 FatFs + /tmp/cc2SVLkL.s:11917 .bss.Fsid:00000000 Fsid + /tmp/cc2SVLkL.s:2753 .text.find_volume:00000324 $t + /tmp/cc2SVLkL.s:2802 .text.put_fat:00000000 $t + /tmp/cc2SVLkL.s:2807 .text.put_fat:00000000 put_fat + /tmp/cc2SVLkL.s:3085 .text.get_fat:00000000 $t + /tmp/cc2SVLkL.s:3090 .text.get_fat:00000000 get_fat + /tmp/cc2SVLkL.s:3338 .text.dir_sdi:00000000 $t + /tmp/cc2SVLkL.s:3343 .text.dir_sdi:00000000 dir_sdi + /tmp/cc2SVLkL.s:3548 .text.create_chain:00000000 $t + /tmp/cc2SVLkL.s:3553 .text.create_chain:00000000 create_chain + /tmp/cc2SVLkL.s:3789 .text.remove_chain:00000000 $t + /tmp/cc2SVLkL.s:3794 .text.remove_chain:00000000 remove_chain + /tmp/cc2SVLkL.s:3955 .text.dir_remove:00000000 $t + /tmp/cc2SVLkL.s:3960 .text.dir_remove:00000000 dir_remove + /tmp/cc2SVLkL.s:4011 .text.dir_next:00000000 $t + /tmp/cc2SVLkL.s:4016 .text.dir_next:00000000 dir_next + /tmp/cc2SVLkL.s:4326 .text.dir_find:00000000 $t + /tmp/cc2SVLkL.s:4331 .text.dir_find:00000000 dir_find + /tmp/cc2SVLkL.s:4439 .text.follow_path:00000000 $t + /tmp/cc2SVLkL.s:4444 .text.follow_path:00000000 follow_path + /tmp/cc2SVLkL.s:4612 .text.dir_alloc:00000000 $t + /tmp/cc2SVLkL.s:4617 .text.dir_alloc:00000000 dir_alloc + /tmp/cc2SVLkL.s:4728 .text.dir_register:00000000 $t + /tmp/cc2SVLkL.s:4733 .text.dir_register:00000000 dir_register + /tmp/cc2SVLkL.s:4807 .text.dir_read:00000000 $t + /tmp/cc2SVLkL.s:4812 .text.dir_read:00000000 dir_read + /tmp/cc2SVLkL.s:4934 .text.sync_fs:00000000 $t + /tmp/cc2SVLkL.s:4939 .text.sync_fs:00000000 sync_fs + /tmp/cc2SVLkL.s:5053 .text.sync_fs:00000080 $d + /tmp/cc2SVLkL.s:5059 .text.f_mount:00000000 $t + /tmp/cc2SVLkL.s:5065 .text.f_mount:00000000 f_mount + /tmp/cc2SVLkL.s:5181 .text.f_mount:0000005c $d + /tmp/cc2SVLkL.s:5186 .text.f_open:00000000 $t + /tmp/cc2SVLkL.s:5192 .text.f_open:00000000 f_open + /tmp/cc2SVLkL.s:5748 .text.f_read:00000000 $t + /tmp/cc2SVLkL.s:5754 .text.f_read:00000000 f_read + /tmp/cc2SVLkL.s:6186 .text.f_write:00000000 $t + /tmp/cc2SVLkL.s:6192 .text.f_write:00000000 f_write + /tmp/cc2SVLkL.s:6673 .text.putc_bfd:00000000 $t + /tmp/cc2SVLkL.s:6678 .text.putc_bfd:00000000 putc_bfd + /tmp/cc2SVLkL.s:6790 .text.putc_flush:00000000 $t + /tmp/cc2SVLkL.s:6795 .text.putc_flush:00000000 putc_flush + /tmp/cc2SVLkL.s:6874 .text.f_sync:00000000 $t + /tmp/cc2SVLkL.s:6880 .text.f_sync:00000000 f_sync + /tmp/cc2SVLkL.s:7031 .text.f_close:00000000 $t + /tmp/cc2SVLkL.s:7037 .text.f_close:00000000 f_close + /tmp/cc2SVLkL.s:7106 .text.f_lseek:00000000 $t + /tmp/cc2SVLkL.s:7112 .text.f_lseek:00000000 f_lseek + ARM GAS /tmp/cc2SVLkL.s page 379 + + + /tmp/cc2SVLkL.s:7838 .text.f_opendir:00000000 $t + /tmp/cc2SVLkL.s:7844 .text.f_opendir:00000000 f_opendir + /tmp/cc2SVLkL.s:8024 .text.f_closedir:00000000 $t + /tmp/cc2SVLkL.s:8030 .text.f_closedir:00000000 f_closedir + /tmp/cc2SVLkL.s:8096 .text.f_readdir:00000000 $t + /tmp/cc2SVLkL.s:8102 .text.f_readdir:00000000 f_readdir + /tmp/cc2SVLkL.s:8207 .text.f_stat:00000000 $t + /tmp/cc2SVLkL.s:8213 .text.f_stat:00000000 f_stat + /tmp/cc2SVLkL.s:8306 .text.f_getfree:00000000 $t + /tmp/cc2SVLkL.s:8312 .text.f_getfree:00000000 f_getfree + /tmp/cc2SVLkL.s:8597 .text.f_truncate:00000000 $t + /tmp/cc2SVLkL.s:8603 .text.f_truncate:00000000 f_truncate + /tmp/cc2SVLkL.s:8787 .text.f_unlink:00000000 $t + /tmp/cc2SVLkL.s:8793 .text.f_unlink:00000000 f_unlink + /tmp/cc2SVLkL.s:9015 .text.f_mkdir:00000000 $t + /tmp/cc2SVLkL.s:9021 .text.f_mkdir:00000000 f_mkdir + /tmp/cc2SVLkL.s:9388 .text.f_rename:00000000 $t + /tmp/cc2SVLkL.s:9394 .text.f_rename:00000000 f_rename + /tmp/cc2SVLkL.s:9681 .rodata.f_mkfs.str1.4:00000000 $d + /tmp/cc2SVLkL.s:9691 .text.f_mkfs:00000000 $t + /tmp/cc2SVLkL.s:9697 .text.f_mkfs:00000000 f_mkfs + /tmp/cc2SVLkL.s:10298 .text.f_mkfs:000002a0 $d + /tmp/cc2SVLkL.s:11887 .rodata.cst32.1:00000000 cst32.1 + /tmp/cc2SVLkL.s:11875 .rodata.cst.0:00000000 cst.0 + /tmp/cc2SVLkL.s:10306 .text.f_mkfs:000002b4 $t + /tmp/cc2SVLkL.s:10943 .text.f_mkfs:00000644 $d + /tmp/cc2SVLkL.s:10951 .text.f_mkfs:0000065c $t + /tmp/cc2SVLkL.s:11023 .text.f_gets:00000000 $t + /tmp/cc2SVLkL.s:11029 .text.f_gets:00000000 f_gets + /tmp/cc2SVLkL.s:11149 .text.f_putc:00000000 $t + /tmp/cc2SVLkL.s:11155 .text.f_putc:00000000 f_putc + /tmp/cc2SVLkL.s:11200 .text.f_puts:00000000 $t + /tmp/cc2SVLkL.s:11206 .text.f_puts:00000000 f_puts + /tmp/cc2SVLkL.s:11263 .text.f_printf:00000000 $t + /tmp/cc2SVLkL.s:11269 .text.f_printf:00000000 f_printf + /tmp/cc2SVLkL.s:11455 .text.f_printf:000000a0 $d + /tmp/cc2SVLkL.s:11872 .rodata.cst.0:00000000 $d + /tmp/cc2SVLkL.s:11884 .rodata.cst32.1:00000000 $d + /tmp/cc2SVLkL.s:11896 .rodata.ExCvt:00000000 $d + /tmp/cc2SVLkL.s:11908 .bss.Files:00000000 $d + /tmp/cc2SVLkL.s:11914 .bss.Fsid:00000000 $d + /tmp/cc2SVLkL.s:11920 .bss.FatFs:00000000 $d + /tmp/cc2SVLkL.s:11479 .text.f_printf:000000b7 $d + /tmp/cc2SVLkL.s:11479 .text.f_printf:000000b8 $t + +UNDEFINED SYMBOLS +disk_status +disk_write +disk_read +disk_initialize +disk_ioctl +get_fattime diff --git a/build/ff.o b/build/ff.o new file mode 100644 index 0000000000000000000000000000000000000000..8e7fcbe14bc7e208e5f5148083ae529e44dad6d3 GIT binary patch literal 130972 zcmb5X33yaR_C8$Ix3?snbXJHELMNR-AS6UUMPwv|&;l~DD9Dro==Z)=_a+_2`Td{oKF{f@dTTr9 z)TvX;y@5r;M+c;o!g{1A5bY@;%D+}A#{gBJK-@3x6J@ocw)BY2S995(+9kDRM~vKI zwZo3s{6r0)vL-HmXbr>HkGuTC_&aQAOX5G}HQX05w%dD$71Ox`*sB0Mt!ww5sw>5=_q zVaEP0GIR9$$)fkkpuK8+*@;m4DBDpZbz;?$s)x$H4W+2mLsezf50xDX*$NYajZGe6 zX$>p3oUB`v7!6rl8~MGHCu(B+{(f<@Z=x;18>x^hzESo+9kvyo7fkwfmUKWeXI1gIyQ(Hulvb~-5Wba* zKM%Xj`m)~xn;j$NQ6uG^#gnsYc7QM6*|6~ap!k;qWkJUN#LJDN!j#Vu2>HyKj+j8Va{&3bT|akP)cg zY(J-DFOS_U84VBICj6Jr*;74tivy)aZd$kY2UynK%AHzN>Vn6%%3E%uuA z-ZWp~si33qyUCU<^9&qLw5!S2hmuGtrMpr5>wx5C2zcG&6Lc{qB%6Sm|u zZHe|E1ER{^XbTvai$9lOKKDzj^%ctIL4`kr1{Gok!*Yy3T2v;K42&ySwQF^m5h`es z{o*TXF4Hy4dKJPytYRt9f!h)T_Q0w}qpG2?OYQo`#mhfgUSDPe<9s5oPsPBUlWQqy zazu)_P+rx^aGdXWI4cl`Im!~>s^25wqOT)E->S`MDhTX699e7+xNZ=w1KiR-C@?fo zs#fe_!_fr;5K_e`1jNR>2J&+_a(17 z0`_D5e2kAeHOarKtb6F8=zx;13thn(HyDwh(-KELSSEwE{PY%k>nvs8zR04|xXV|S zB?RrQ%M{{7%8oL&7JI&EG4cxn19u)3D@9=FL{fj~V9ec{5(AykdqM^Ka%Jy6_S?m; zT|Ob&vsCmEk?R-tsc=Sqa{6oMHkzDAq{AH&#Ue6sadO1&6_K%v#xV^PZ#~_!8d|M|P_GG?t_UzfK z%jN3TWxFGX>OShS`RosoQNwpf{#`fb)X6z3%LeQ(RpG4WF%err-xlF>ZZwWAGloTz zJ@P`MIB7p@Mf8`($$!nwEH`cyh2I9<%5NMAiyl~Mdd9b$AJAHo1&dDI_@cbX=sV=p ztQXnN-NuAy@@!H3ZOFjtG$vvsh*n$No6*dbJ*MAt-t_7H%MVU}wbk$z2VYTIcpN-; zDPIrF=Di>ocXXsJ4(pq7bi6UFTwb!}Z1ni6W#ZVqb+peJmHx^)zyD^|&kf!c6`KZ( zN?R`bH*8L;J6NYV3UJ*`cr$Eoy;f;P6#O>Co~{qsTPqZ@cKVnjD~!K|#~c}HypM7- zwFV3R5xO}`w;>9GA=uQ-9cRJYXkmaV+ZndKD`Y?ER2G+k)OMs?DpgTwKj~I6U*%uI z39x(DCd~5tJ^4R`jr`N$`23TYug5{Hpzp(p`QL($f;b!XGk$#K&^dF4Rwm~E3;1WC z1E6NmKS6&7?E{5Ce*=9$e{z}ZReJ2cI?nsffu+@dC@VeohdQIyRyZ#&N1U`>hcWCwA^5qsJq07c#UC4Txkb3 z$0H@-lPYIzSka_f(Ar`f<3b8!-A9KvzH{7_79WjMrOR8+ZvG)<%k$vX0utr0N8rz$CMrtlYE#og@J!&0mwVh3w z)UCWguUL_qp%)L+akd~@Z19X2iMwq*&V+3}qT%Q^N0sa~tJxFS2z^yG7eZSXKwBfB ztr;Qc%2_>Y%no!_$ic!DTyVf$CRx5m`0c+~+d%oH0}0A=lRpVC35D%;SZ?A|7p zee%D``XV)@*yZ`6JEiZ(u=Jh5Ed06TwE8`vep}TF6vQgucv5s9`H?G-6iA75_g)qn zT6tGh)~l5{XRJ1WmsAKbD%>hZmF_Smts^0Sq0 zjDeZv7*r;dUou_zvRk%CO7l)cW&~^q?$AN1K@?OUqK5 z7j*qLoD(Qj`O(Vv!#1qwk;OKw=r*kA(uWJE?`%Z3JY&=w|kHMR0TVlCsP9Zx2ZN2X}eE(~=X=qiO_d8(9W>jeMhtk zt}c`N<)As0{cjxxAJ+e7e;~CbH*j%Vy|2TvH&z+Hi~EuO_7>^4VP7jinQA8x-R23< zCX1V$ffQKfhO)xuQM9>!np0OGxzXRUzAUG?XTajd9%yNl1zAB#&^0J>FE*ue1!|gZ zsD7@xKKl=4UwtI|-%weoxGKE)^RTTaW<$?`f#^=r6Z-85{q{VKeJA#-Rj*g;zI;vo zSzqOLsgeGpH3N5IXE@ARRbIWPS`^L;Is)E+Z@^aAPR&P+u+-LL@@#6^peEUWPvzq3 zbxr+OY&klyyQg_}r4yF1870)*Eccfe!Y;5=TZ$b=r5)p{@{Y}2AumZiVz>{5IBJVA zY5_HB!!e>uv0mNZ_^ip*V)&ZDu$#e3-b;ddL<$izsggOG<9Dx zWA2Jo!xKJ|{^K>ePP7Rg&)xq9*}wmcNVxwE8;-h-{xjafI%U;4T=_)U?)x+7DcIZw z*xZt> zoIMt?olWk4p6MmmR(uw&^WTO2dWyNCqoshcsbr_U;7o{ZoDMnsC$ZN)4u5HfpKzJd z+5+2~M82~{pcMAgwN?~n?)s|mn~=OtSztjImqJvGxo}BQ=&d(%L6fR$F_79K`eS^%helq7X?5;nHmS7(0 z)d1&{Tq`beJgf9+)@YEqpVWvx7YB`oebJISk((2+dKU#7LPG<_Dm{jBu+flJncw2f z-x4O`Zc5GH7PiW63O^q0RFW1+@ur2+Veiic-T8NgMbVOw#*@8w0=Ib`!8EMiwxBD2 ze%O^SiWZ%i^CIPukgn8aG<3aT?sQMXmg%zZL%T$dG&NCD>29*+PYWB5L87{$<{aBp z;cm@R{wY!+a$2Vks5rQMOWj5DZ=Qet^hWs15;tyH#%t+2M||FkgD0v)p9_OqD~*QV ztY}zaoOPXUgkP}bf7x|M8Tx}2U(+<9QCpmZ|7=zM^ZSs*?y|L#+;)A@So3n!vvTX% zACAYJO&fN5qn@ec&l3iE%vRoSy7UhX)T*;(L6ayNa>DlFPlxRJKOU0#XAZ@IcxwAS z{E`>97^`q{+l!ro@hr6pJH^SWscyzX`5;d$TkHG_sWB1xuRY~{y0Cmh<$lOqSWd|obQQ%z zg6pb{)eqxl=;U$7*|aoKxIcvW$q87~x|QOz+G|;8ZIvvzPmRa}!Inzc_ogqZC#$*0 z_3ZxOv*oX1mxP_>nJr~c?{^%HH(rg#`*6l?UVqdPKOry*dx(apR2Cx&hMc(b#aR8w zRStE+kbX*LmBaeI(1_fvte5>qM~qcP>&>i$^JT7aIspUe+79rR2fZcEA$8qK5(w|BZ7@edhGho zY%KfDerE^io##ludrPb=mgJTd?S^daR`h)bNe_pmKX+E_*tctFYlo8iI<)eB*s?DB zKBM6YSe)}zVGHdHHg+@GQ=?+(`dgH~e7F%@UwyD@by?XyZCg($+d6g33EMi=WgBd( zn6@SQVO%rS{@%ZEh8nAjU}ODZWB;ytux#M2w7|g%T3df*ZGY){%@*3)pI~dJjysjD z1z~HaPSMt~OBbE^^^2m{q7wsOTw5gy7M=Lji+V&ZfaKchE!z+Un}e}>oEr8o92O~s ztxQt(FdnP(63p_%Kzy&n;EXD)BnPg|@|Sm;JGeOR)9WiXRLTAuDr{I&60v@N{WEv& z5#%4vGyUIAxoCq2WkdrVa^sn!_XzJH-#Y3M!d`~Di%vZ&Pr z{U&2=wXFYi$X88V6dVirDk5rTaVLk{VI_q#P}_9^FUDAT` zg5Q_52HzX**f%UNEb6{}FTClhfNW^M2{*3!p1{9w^1Xikhhd4|_h{#F2WRbxij~d7 z#j&$>+Mn+VFU;=M);9f>y{=S^tKg}x1T*y{PIf*yD5KO-Zk=*P-wnasSWtAP*lU*FaXnLEG#psIu}>Ye#TC!_pu_L%InzvTu^$7F~^lh;{Xv-5laW62y1uNN5c0se% z15fv`pMrrwo+9N%--hE`Wx}|COZh(Z@v5uAXdPgGV#Ozc#1_*RHOY%?18kSd7W)AE zrSexvK~a1#=xXSSd#-QI)w(27GfcPF7ywr_u7=-KcDa?OhAuac2*fEbL@yDs&ZBBf zc$OU*x^AH;vUUVRgL-CN`q9}Yk-M%+bAWRG4HX-z4^~*~%QdgkcNgLgM6bn`Z-}(* zR=TzA2`O_DWCq_wpN2SZmX_^r{&%%BeUl>)!VPL9Y{Lzx%)f5FXmR0W#+74s%2*d+RV5YltN9@rbUKjK_zoru`iu26d_xzS$mN$5b> zmG{rE$UQ$`wf9-rnYR(>v&x!qHtQgT9a3aM3UwO0-#UqL$Mr~^y+8)-fe5^kKG_(n zC#d-+477QS6&nJIterG3Uv}&5)gf^3>i;Yw;s4v!@DTnp=h7a zcYr!JCQ_WREIMFQvVU20NXa;q)9*e;;jNXH+SxkM<;xvv-tsMrPTJ&LZLBhIg6NaTJJ z?t`=L$bgoz);z~izsEzK$HrmB(X03<+>q(kll=$h=+mOr+cjZ#-qo<^4bZQs*Qa7z zZk#z|wWauBM{y0EaNg}?TFZ#0$D?=Sq`1~Q2UcUDqR-(_MsD__3Fqq*dP#1lXX8~3 z@u&{%fyqst)tT7m$e=sV)#6><74c-mF*6H17>Rd6ZLJl&9*R?Q+8)>uw(5(5mqMwJ zr{yNLCP_zYqS~80j+L0ZnWJ;!)Gp;H?vj$d`-7RQJ!t*oVBBMt|Fh07VCF^i^;VaR%6>o0VoZxLK-hh3#M8B{5 zW{KxH!}QPtn>-DLjayENF}D3vv(xy7&hL3JvGqc{&(n2z=KSZ9ozV+RHk=f59@xBD zz0V6SVd>Jyhf6MK+=#bF?=RWbTDM3Xdw0pK?B1pFfzrr3OSp^4T)p}1@gL$aM{GE= zipXnA5}vbev)JQ_XbU&0fK{h<${=_`MSbL^0W1K4#LCNdL<6~DHnTVR?>Pigr} z<1+#5X(CIrAX%yX=u(5bn-j;!kG7YOA8{8XTCxNj?H&{HB~5FY=qU(bH}AIL+mA6v zMz}A(yni$qUhK2rhO(2*pM=vBI_8(F{25y|l$~ns)nXhSX2||m&B;RXaB>8rHp}!T07eC|q$;*2%J|9GVyKf1&9{d0|z;@i$ zq_4z%F5Z*A0=e});mWdAxM|_t#s`Zbk}*X?^K)4=v94*evo%Sd zB>es7Ia^Z%`4*97bz@G5n|Vq|c(n0k-H=5etw6~%RWj&b zi%VO-ZZX^aZP2#bl52Rt_K0(hY~ajTS@%r9`G{?e=6^5l=X`Y%xx)i{hZpSnb)YaX zs6%UIi~E*uKk9IQ7m{Y3t#t_v_?l@*UF1X^$4x|@siW0Ci~ZQGVP~sP@wiCc&{3{o zD(!mI*_x+fHfW-cib=%usoRNIKZQ}|QYCX4WS#?=_1p5humetLb=oXRW5;clIcn7- zohOf}+oI}h=gAW)hTcw|Qn6T#CA7NQT0*-=jkeT`Ff~&Eir zAey}P4W*}d0~5~C)AMz)99;#S#k&uOK0^(hJ#p(lB;4K>&c)}KbfeYWgm;_HR=1M; zgYck{d&3-yf$%JLH{Wl0+(yHmS7TdlmqO$(i@r8a_FNX-b@Q_5ZqV!FmPOxKoX~J} z`LI*3Psds4_)odZqI+^yyUQX&Y|El=<}8c8bw2Fxopo(#@cMqU7H}`#>Sk-#{OL^a)-1-a%_`f%b4OHFU|Q zI=sE;jIVd_#-ioPz|6qh?2Tn(Cq#oRjK{sNy(AGkQk)q0UQ$4Y}{9g8;#`6Qm!W*-4YD;=Kf0HLkN$*}$CU3Pi2++H#`1FfuUEx}h;afQd5NB7FyHM^G)3PkKq=CJ+! zb?eNpveNgjYxSYzhSoA$r{34>|JPw#q~ce@r?oxP5lfl|V5&&K{;X?5mu_7j*vD_h z@IFyqlo@ql)j1RDgwuL*$kF15FgOv^03joGf~s`o)rW znysH#tIIA3$NM_rcD_rn>*~(kx;~Ox^-pg(-{16fMWm~9+84@<> zeh(?b?x?TyB*n%i6&~ZJKgb~jtyF1xtw}%jqp8(t*FLofFa5LmO05W>R_|L}Axt zGimcqViQx$q~YDgE~c7Edvf(m;kw$ThScx${t7I+rkP2%cR8zGVNWW_o>0-eM-RyaSo6HIqK?Bnot^nauNcA{)1v z$pY_Z?Duvv*~hz}GLx^LD_p-t5V@&&2!^VY(CzT|-8serx{^Xmc&l0Z3+?hM}qfXYETx5B_L>sPkX42=~%R$~?CiA=_+5MAlc53q% zcyFUXe~znA$v(-`=U*>e&zTA=0n5~&$Ifw03yd5sT+bVvkEtcD&2fKk<9kaR-wot@ ztJzt)=4_jp%+#E{WG1tcXI4Y1mrYiD$=74-w!7G>&7Y^o?kgnJ6i*OoaWU`#sg?pW_*Z>wv0alF)|(` zd&2$-0(X`nQM6OC{87f;g;-}y0{I_l&4SJ|X3rP$CuxqAz4J}X|Jh2rJI|Omhu+I_ z03vfgT9t5)gV30h(`p?eN|i#KcZ``CHg7#J2l4>jN2rr6k?uxAPV(_jtCke!)l!0P zw&Zu(YB{H)^ckzjBH=iK_<0-I)HqujGjvn-`>5-JuIr&Z``2hD?zfq#&_SosGNW_c zJj6O*UxV&DyBNoW>s&pvR>;nsotL5mo8R6g8*L$-pwsTooES2*v+Fih-h(;8i<#^ZCpk#+LzL*o!Rw}CEYfW_e$X<7 z%#tsnfIHtT{bO5cPTX$orL*K!5YOGyEY}^@rCU`^bD2R?-JuP)KTe(m19G5M1R1NL zA9tRaF|I8mTUJx`f9mXzl%G#In&2bvix;9hmG_8N-VA`(fVyA*yLm#c>g;8KMgR|k zd^weKQ1r3R@ic5({pg&U=|VogyKeLaR@7R#UPHyi5h2AWjS|Huu^dON7urh*{~;6nYdeT)Hn&gse>Af`Z_g6`WbnmC zerN}+@&#sA64)|15dLdT&>st)GQmsRK{j$5nCt@GvHi*pS@HGrZV|ce=d&J?!e3$* zxuZi7*3KVafrS_%T zh+ME%1Ej3&E^TeSkj@7wJG$Glqvsd-!GRi!e6*rid47>O7SbFGjuyon)Lug5=K^fw z{&{R^vt?&;cw-EQ*(fs>eM*jXcbLyj+I;>9Yz0X1SEKoR5$TN}#oydt;P0*W-p}DL z-Q=&OLkZhF2;AjdE_=KSt;-pmozN+k6Oe78ki8&XPfoCzof8mYftL;UF~d4{$B1pYCkoO5H*UJXH@+&W)H`Q}hh9)z8b%M1`IhIhxQsPoA6r zP>5bVIF8*+uC73tTGW+UiDskOy3scQ?f_Ah-L)#Q>laZ#In&WkuGPOT9r8-?84Nv#H-0Qd(%>hiCh)QUlO90lc~*!#LzHoRvS5dF&sos@qWisY{d zq2dRfJnZ3jNd5+tgVprIPA+m_tDl)O2bKQTN$(WvEAk7#VG({{$hKRQlIv&Y$?@`h zO0^J~YTdCVnX^km$^jH(TY8-228GW`sPj$qB)h=ydwb#2{TAbLZX)g}t8c;nGuHo+2(nebZMZR zx#;JObiJ*qzq057O0Y+(V+`_#gNis)0j6*jehk1vpz}7fi#_S*5wz8hEqY9+bC`C* zRzF6e+!|_kPkJwcyAp+111jQv9bhrRyD_G>f{Ie9m_6wO2%ZA)ZxF3*Px>W<9>B%= z0#MPNWbjSR;Gks85m3=8m?l7VRJ<9$41!!10Cr;aAb|Hl=N;mVeM?uz@?3Ncb@Env zG7H&Kg!qm%ztmtR!9N0A2r9ySXGtGHnJNTs-_<((wzh~xfUX1OF1Tqn=2yC!O8IHf zFsO*fD7iO1o*R;p0EU75RO`}ySbxzcEx#UrWLXT1dm8dV488hC0OJHqM2{MyALx$> z0=*0WEHk@LhwOeT`%2+|)6BlSLpEj>YL6EF@4y-UR7}h?v*}63$r9m@BIDYC5X)jS zv=wt|ULyQ3LkDSlJV0SAgi#fNWt19F?0)_eKm_-I#MS2Q9rv~|$Vqu+7 z%~8K&(L*-j{}VDP^zBw=Au|mhbV#9x3ICI3^*@;`U!s(GN`O2Rt6Xy zM=^LRWk!RQ0ec%KFBJZJkUm>+;nutSm7nB$eB6o zCL!mhI(d0xt1m?w>(<=V1g4Gpm5XwCl`t<=T{Rf>_b$p&>-hXs7dtoVPu!Wyiy=8b zwKv!BD4IP1%AJX=;eu4PG3f$zbOQOYD5@nRv9q=b?2Y`~n~uV|QLHhe{u`dk*b(O& zESPJGtG^IsW~KU4fw$p8`~^Q(w_&Eab92D?JKt*U1X>#}hr?{loIhDPD|zC8z{t0` zF*B=Bfc@KT(NuO7Q^? zd>Hxr215T3yv+iXQ;ZSY9n61}ZV)JCxc=$#;K6v^5sb^=%jf)NOrqHV%}V^=niYT3Y(i}aAE zrK-!oDi~=6i2I%NRJFlekK|*7X3oV{IYXPlJ^=42a0d1m8L5ffi=;tKE>Lcb22%;n z0B{Y#dB0=9&cq%<`aX~!D~~dm-<+ouXw*N(fi&u$v<#*<3UDCjSp}Yfhb(0igV97g zNRuhSa*G_b?$jbe{Wt0&YS9{JyA@q7M-F|*yJk+Ua88w=iLMRkhbiYyLdw#pi3W0T`mXKx^f26U;eWS%H=zS{?nZq^)c*1QFC=Nn+3 z!c5eS1R0uVR<<}TcEb=<3HpvFeopGLj8Js;WwNI~8=o1Mp9 zhmvCyawx|km4oA@B}XwYhd51OmY2{h|B}+~z}^JB6N4!yWLakULW*)=E|{|c(q`G1 zqI^|3fF2-amYY+Qt1{}hFUpxqJKdZTuYJ|>MMZDHv&k(f%I*A&8u)NTDC6ClVmh$9 z7WuI`RTi|at7$<$YL|1DWkEeqfEM(URbV?TXaGR^oM1ah3xbEb5;>gGU+Nq>dF4&$ zIDTj^EsB?*pz<8Fn_-vWt`FkVFzT0c5UBpO$hrF>Auc>OCx1I~IB=@`b~R{REjegV z@zc<@ygf$6&!hNNFiUxUH*7L_7``J#9fltSct1#Mc#+odE&#N9rK>uvD;&skZ{)08 zto50NA?^fHmp2ECu=CeEsxgNrovn359*@W5D66^_+;C;|fEk+3JnY2OhH?%v-W`Ig zN0p&Y4EfZKDJf47knRT#YhH|Wp93BaUSwmoWkC7bfbIwS2TRkzq`2~Va z1be2$v)U&Bf*`Gk-dYj;FXXuy;1vJ@AYPXgr6_;749O*gFigcM%Bwz$ql&&+Iy*o!&V^lxjcYV+ zCbMNGhw$0tb}w`Vns^Ca%is9G=}hSUxnvjPKLI=g(%f%MR^0obp)8Q*{)J@anMMJ) z6r{}M#bo_Hrhc~C>2Qkt$K+1$1UW^ZE;YeBp&zYabLMl|BJ(A&8ERwD4>?^2;piQk zgK3|Su~cp(wjGE|Z;KuF&Fs3UEJ2OLni8>?Z(cKuWSd zT9VCcoBaPoBW?ZiKCw6#?Y}h)KiP5wcb{c3ecuN-3%ZaW=9qmC(|ykZSOL;|lk#M> z2)qJdGe|RZnP$k24kG{+LnADPX6LH;F)}%hEiXlxg`l=cvIHQxHuz5Df?K~Ye)XkT`+43t|*E(;zbvpY|&2DuGHKe0A3h$W@1>scrV$JRc#Ys`8@PH__d5*C4FToS(QnjE{toFG z#MGW_qu0aQTLC;zP%Q}?z3MvcI{-%r&ePS^ZBE_*9d+sVYC7a# zWc{xp=L`n)p8v{uA2|n0g?PfusYU5{iQ7NSot+BPOVxNa-fF?hLpE2kf5c>~jE~HE zCu1^V>irwp+<+!QU2TkW#kXTL$ag_(hMM;Sk;5uw|CKWhIS0Y_l`02!0Px!P03%~G zbZdEqUAhdY_N%0JyQH5Pf*p?h5tWr)9!gSnc{jkNAZ>zQCn*!$2;eD@GQlHBrU}mD z%PPSJ_P6n-k8&KFV{Mq4bRAv8O-^+EPz*n-(9*}~LGqn|;^$$_PgYMMGC`W3Rhpkt z0E0k^pGPfzW~-CJ>Lh&+j_hjIQ|Ho#B(Xv6|`w07PSF3)H@uHhCvi2nj1WX}RqRash9CjsKyXY=()x1^*GVQpPeD2)ZD z9h5r*=fV6W_15=mqz|&-^EA=?q?F+hJqyZD1r=Qa31kmQ z;==7NfC`WwyEQ=zn+REB1`o4;6mmGntJ-peAETmX$sHzkJ6d=K7>D#Rh4F3|OM*K6 zOi<^Uw~@~|w<)Hb6K0*insuz%rH(~Bs(oe^#&oU&-^5OL=zs?DDRS6!0<@}`7x~`- zqqDIlt;q`RD6z0mAK8*`!R5<|?Gt!E>MVgaBn?$fnC*#b0>6v&+aUdttSM2w0Ez%O z%!1STiu{#CWd#=%Lc^f$(}BI3sI1^Nq!)m+6}*`Lso0_{#z^R1*0 zx&&z}*qx}XUduP3TS?r8w)3BK(F_=e`?LjdoBlxe(?s7&Jo(%-P4GL1J9 zm1*?Dz!!jueq`-EiE3Wo24DfG%`|R;MRha{Zu4jwOWSgUe=;yS-A7`uO~5#E8x_Xc zF8o1Y9G`dFur_nyJ@Sucl`qX^v^8;lkHsJzEX948nM2!KVh(mDhJyosj_u_?hx}jg z;EkB|@*7XP0rUf~3Np(mRHO{xTaPk;!vH@A>CM!49<`Yoh_gZosP_~!FTeMw_lLIv zxCx{O`9vCp>EKjr!+t`vc!`%A*GVslK>M0IB`MDUaGJ z{0r%3Vrolr%A;OSd9YWC2kFhrDUUiI^#afxl*?q4;aQnmW2ga+DH)fdH+s(B~Y{KE4OgA05pPf_~FxAx*zNY)bW#VH@AZ^ zO3I^K9=KgT47Xq=#$DHyz-W&wvk<>HWXyz{+U$ldaE_QD+uA zdO3s~CH?~*bv1Da*ykY4>cg7VT%2~hfQoydEq)dz3iwJ$HYT*YhS69orlO48ix#!= zHYX%A@g&f-pzd?1r!5JppJo8>fwXVfnxK5c)i{KX1nF1%FKaOM0_^t)s*ey75_#9Z z4%j0gt>x_r`fEIxnjP_e}wQm0sMuay6AZ&p$EaGF!kSoir{ZqvWQ^n#n^U( za=6;Pl5oL?P=~F4M9~v)?DEwF_4Pn0@=HLu)Xt6s{VW~1EHBspZ z=sS2rQ)Xoh5&jQN>?(~J^WFtZp8({9o^65q0cK*xvNjzk_%!Cd1#qAV{>cL00ay-@ z)i+w;#{jP|OYXM7Hvn!mOMa@s_yuA>-aL`($Ct7Gw~T;Q z&?G=Me6Lk}fbjFnEMn`df~!z)zX`r%fsffm{=ZF7X>lz~)???llTKO~B~~wC3{miV zl#>r9IOUbd-~(qXT46Ji{zT34KWY2wj60naP;Yf*_=uhrzXmW8q%4fWU4~j(Ul5LV zW_=-t%NeD-X}W+hk22EFP@bDD@CcmLWD``ZFT)7+o$LZXlM~uM7#)Ek{3wlAYT9p1 z(SD;AyvzgT&Vz%TmY}v2k0Jdhh2aaKX$k4n!v{#eLkyGU8a-JAHeFFd$_rns{lj>G zqd=nIC>8ae_;%;@0ML7pC4Zow;(gpt@#;QqKfoYJGxl@5Vj>+2y$7Uyq%A>hVP*oD zO7KQZV?(>HXOZ4OOnF^r;k%Hye3sSEf$-}FlHr1;o0Io&sfP4B| zTaNHw4~$FfK@*z~jdRR-htyUZGg%Z|M(;N$M&clf<)KH(i$5jtC0gPU0LwvI;=%FC zh0g+TJ&50|y%eu}^%F=g2bJKP*q7qfSGc)z@nt>|Np#UAm%^ifa&N@2yd1B5*yTtM zBQ{rI30UvNeMr|4Q;?U?cSwFo2;;ClK8b&q&<{(02}o_Wxli~4Y*R#jAHq*!x!t)$ zysO`sS>@?>DBLzbD}XJW`TyIIms6#O8P&>sqwx6;B_E<|9W4Xx_{jO z;BgRHtdCQYe1_!T3E_skK2CjI+_e;Q3Pc?}5U0NDyB^7F3Gr>>gK=u@S&#HuP_Z>N zil+-baYR8JVsctsyIp1h*oMNATQ0@tHJZ<6fPV*-s2xQ`oH9XWQI&CO1^EG)r$PBi zLVGGI3-%!j9^guL!rk5pG%Y+s0n)rwCnw!X86^PwfV7=Q-KvwR0IncN^ZmiCI(r)F zCqe3pVgEZeyYrY-m{VYN9{b$X009ZMQL-veYne{bD zP5~)VIFHKFc)KWA6)6hu#IHFwqc<`rVVYB!@H?hEDqF1YjkUQ=!7|nuXI?3eZDBo zhgslXv=p+!ssDBYg#_8@kH#boQL$60*|`ef1dwKDx>H^7+zMbmNSz|D)9kE4`Vo+N zm%>fLFtns(?;`SjXr7o#r-OmM4)k?_vwc2YffD;rT~e27FfVkf`E(lKaZvB^268WQ zDo=7AtRn-Y2Xl~9O|qc?E+PnjdWkN#1j#x=9N)oOqDPQ^7^E1bv2w9j8p5x7sY`Cj zMm(rJ<9v1YQ^rd078EMjK%TyLw2Q(0+jD4KvSB4g#G%A!0r)Pc_aUmj)uC*15$5Y$ zkUl$~aHw(R$@U|VK6#&TsP8U*4doSqlprS^%2Hg|1UNvH_q0Rl#fM}UQ1NVV$CID> z7J|1}AyXEZh5rd;^5cT9OpJbIJ1{O0KUvrSQyIIFaj+CuyAX(St53dg11J0+A&1TM zY0DA$C(P0vN(%fF#}N9p7(MMqxlv$L@}@`WX_wa1od9Qn^xKx*S|tf1@oElW?u@y& z3AsmuGXYkBw4U~8J*@(;1f=xzrq)x}QTTojq%Lu(l!GS2>eDf9Z1brR3Q4xrHyA`k zU%nHPYaJb@3AbI;sJh8n=TJ8}{m^_dNOQg3p)NtL0WbxmX30~U>19aYMNGYxdCH+K zVAcS5l%RTr@{}XB!j1t0@K=H~-KVuAiI?MVtw5sS87DZqEQYgx0PT+~$x8}-U>)I5 zTc@jmP5|{*ufIoXJ{|#ZKL{Gd--c-HpGdz)Oz}2a^VWAX4q_l&`M~vzcBuDA_W@W& zP%WgtcBtw19)LXr$?z4LVfkx(T?b5^ft5WXp$zl4V3XQbFXq(Y;tu3Ij%D?3Ge;Ym zx?thwg6cIl^V>~JU&wK!3cBJ)p0>A7#5)0`qj$+FS|3rn(#NGh2Y|Fbez2=aw+g^A zf;T|*@{9((a7qS9i}@eB5_2wq8wlQ5i{123x@04OX9-gFpY3XThLQdXc_+*E}&F=T&+n zbtpe!R(UF>N;<^mL8{5bxcvEm(VJ>JgO%jaU4Lz~&*vY}(j(&m9xS!2s0JURO?@gwrQT*+|4t zHgXlxlR*A{rbxBm!(`V#)x_?N!5%WPwK3T9z__?JY0NcW@N|#E@@`~M-5=--_1bYi zFzN}Nv=tP6YoRIm<sIq8J?=Uu`KP+OHX&17>G|v|5_AWIF(C2jPFxU^|iGj>jnoZ(+dvJyD@JSD_Y-mSD3kZ zRxWNE+TJE!Y=LWW1#ufnS}zF5mAY0fXmUUuD`RwYA&N~#pOO+Q9o1_c)d8#p^V$zX~f9MWwjPrk|%t{ja_r|CcsUgo{AfX=0=WV zt8U%uO;=;l0_9G}AAPwEbzpx6=_f&=@5daDW?MUN$w0{)k8b);O`C09cn|R&%D)5Z zIim_Uy3IB}Ryh1gx#-J3Ntf@(G||Ouf;-XfGx-N?@7ub3h$g;8^{+wQ=gxuZ-nSJJ z%$$Zb9@KpX{)H8Q7oe6H4qyl<7gsDF*wk@l0g^R@U?m^edhiwXQ%J5O1cpAeseyP0 z$+tkF2md}ozG2gb7H_h|v$baF4O_+mfS;o5Cm_9azG2IzRA&H02`ZM}uoaM{jBBuV zg2>Vyn_4@6gXA?J(W8dbX`9(uIuNRmu1R;cO?S2kWp4**`L{s`RC^A<(*#v#+iWH5 ztQkNE#LiyQouyrii!u=9e_5;KA|(5RM2}{U!NceD&&9WU4c|aNZ0p2}sY;Z+3Z#X7 z*rxvQZZm*qR3jy5N#18RLg!5(xXkEA?z3gE5#u-5#Lc6n(6`)O}GqX2DZf!$7KO^2@8+3W&I@`yQTO0NK%vrOq!(uVvlCX;Oyx)zHe z9*gguo{?#TA!k;xJQt*d-5g4n*=@OKg;i2ysw{OrQs!Zy?hY-C?$Y^k8Ai&N33cUw z7fRX2OKt~1m-Me#f^THy`D(24?!h~MTYP;P7|*vdFh`0pLb{=z9@Tfe*>}$leWO-E zY|(QV?G>BXL4@9D#_V8ZnoToS7^_K+M4t`-2DK;_Fl!ZqYe8`^pJKZ+S+V#oiPZ$A z%>O9LnSck59<)$}P%h&hhH9dVg?$(fMj=BiTq_wV1))$MhGjbLVaOGn4gL3%3P_5v z3^G)790Qh*7j6II!x}*U>ydP$AoXzcZK8f2LoO*&Ok$7?GQ@njhLHgZpU9w0MJF%_ zsOTgHBQ(n33XL+ru?WpgU{Il=lNihdsg@bJ4TK&U+-c#As6QeX*z@YgWY}by2LLi) z6D4cdJIRW(Uz<384MQC-QE_befcIO&@KcZ!SMraIvY|CZ0jP&cA@#;jACOH9TElQ6 z2r6eVS;3`ist|ssVO>|()Xe}FSKx;g$XOl2dq7f5WALlx z4%-?=v@WnA)DMtzo>=5<#nQwI1iCyo z+HKDu^h3Q$F}@CgW@LO@c1(n(TLh9~9J|n}7)K#;RsC@s=4*7c0)cL79Q(Xjv5d31 zevtWpJa-}QArSgu@Un_dV6a1@3|`YHgWVvznDd5MLte5J0}~izgLFnaXA{WTUAhc| zWuQ2`c&!n0M0VC1Chyg`3?2g+V(!>An-S5rHQ`G{4}+wbN(r?}sbllu(324-t|@ zWTB4Yf)Nfh*+bCbiQ$4p{%{J-#| z0yCXCD}qG^eKg8|O~v|krrG2}26Mk16D~bYQ3;T#dgWcV%WBoBHNcLE~b_ucwR>t>;Q3B!ti|_xy00BX!!&P(JFMS zj`t$QE92b^_N{Kk(PaKJf10^A7mb$0Gaw2Ho-b@G!2wkdOYmO+h=S~5!E44Es~Md# zi**P%S@j@HWI$dGf$ujhZdD=`eQCW;q)Ny>EXa~V6|ov6588{6Pi6XMWyaeTTJj6y zyA?I}fG`^v;9nsiFVDpC^2{R2JxDPyfdSR13ZX)W=LMv+U{e^78T3a}Fwm9^ zyhG*xUkNr}3WD8_K%oAy8!?u_jUW$}?bE$#L0w_gw2e(5h{%BE(XjxR@K05Nu?#*3 zWuS$*BI^#3b*IQ`Z;DwbbV)nRpZ_`?T4lgLt-zk(&NYk_fI4FAD$t~ zU@Pc<^v0|sx+H_W7#qwo%SsTXGG~K2_EiI94hS7EmjRRsDkNn5TWs4235#(9U2ogCpnaa5CLPEhew2PA$%42FsO@ZIZFg_J{wF zjX80*FJgrMj3B%!19k$t-@b^EB;|gtVmEVCH&-!WkE#eeqQ^khw#H+WXJKr~sal%M zARgqz{&c>`TEloBot27K2dPdbGq@DQQn#TL;D-OA zDm*s%d_qMh?MCpKicTP(+8s}#>C@QZ7u&~cDu+#T-!^ob>wh4~RBT+GjX*bY^`$7T zy*_Spf9Ywr*eMi5o7j{-;QVdH{S*fKts$ov9AGuLWKb`NQy7plg~xWoHuV`|EdMTJ zlxlNqdkJJiz}Tmqp=&22hZDvSZl7BBGO}-(-^Q*>?TSrIa!)wYT2eSV5cl%bz>>L zW6#W`vDbpw2t#f7W7{23iE>1G5{$LH1WVIN9M)#?}kOX-tA@bQ*(IxI#|4nhX^8tJ-BCj@%i(V;jM z!QCoD@XNS|p$~*j=_<)cE{GWndq6iT1Mv<|JW}YAK_UpOe{*Mt0t&`fwIlfdN@bz| zPpN2{-J8NQpq%g!3`$jWEQ5fGPOL&OPesQvs0G=?z%>l(KxmD@T_C~?mxBO5fMB(b zGFYpk6B(>m(Xre%zM`WHT2yr62?S9PZ^?c_*a>PvYYg;t$wUTJo=sfXVY{{orR}Qp zBnIcHXa^-lP~r>-?J@X|igqZ$5#uN_#5gma$B?IT4Ax;4q57D?a5{QX8Hjgyl8{0_ z3{pV9eC9yqa~__(x`0rX0lUD^FzBIC272r!GT<=^WqBl>3gR?k_>F=mGN3Y1f$sjUB}ZIa`wX3mP`=o@BqPiO zp)vz@f>C5ZQv}LDTjWFrB^qTgKtVh>V$0oZF_8p zoij4Z$v>y@Ooq?vICb9P(Kn4_8L&vlNzrzA=TXJFf*PBS=p0pc5`#NH4elM5O`!jcLPtr;2w=K_*A3#RSzaQ9$GxBa9kJ$LD&vj+KAa1O5n`Y_249t zAe$I22D*`cs*xKNJdpth6(ty~1>ud=qBV@X1_I7tw~9_|?{Xr54$mN@bXQZ^CXE26 z2L_Z&imMsu7N;WC;UQma5UQDmK(jWsz2C9z{f@ONQbemyDu$JG^H*9$Z2z-J2ku$y zmnK{n;K~FU$949l$ygdLtFq#y%>|Fs@-=D`FRu$hiC6oB>6jA=1wjsd&HP%!YR z=vW4MDmsY)Re`b$N>y|c1KmZN&VWGD|B_bSo{!LYCPQr}3zHdMVd4lnJlr;-Lk2AJ z3xdQecpL*=;un`qDl1c!RI7j%^hyS~8tsSRQXOSLo^T0hu?7|Zv^~EdoqChQA;cIb z#|)*LeNc78+Zr$3 zWUJ^T2CNtRx`gR_bT$Jvd5(5~sE6X3evobA%r%ptLO>iym_(GIgh>cf zNJ1E-hCmWPL%<{;dT<04J6N^W($*IBSnIJ?YpWfswP>xi+T*d-+SXI8ZMC(-sn+(` z9_z91b=~*1_Fj7vYTx(s{`LF(7OZ@qdAOhZ8Q0o-yDM=K?nE%}5V_aPryRNpWO)+7 zDVbT)M>lq%BLx!^0{k;qAx!M!WXjDp&CGK16tYI{Bwz7Ic-A22;tB`VAsD0&tPh?@cOvL5{srigttV2J z-)dr{8S9Bz?n=ycSK=IZWh<~QNSO8TgPptqbt97Yrd-Q%EVJNivoY63wS#BgwL(!j zlQId$hsqEekPMy44okA0V6q4irOps69}A~4QfcT+QpyM&&y`u8YuPjsdvN3Ez97@f zvthZqV%f2tAX?41ifA+AYJysWjI*6&Jsj*p)^_E^-3dn&iMS58t$Jwigfd0t!oMCj zW3x7-2gw{2GXn;>7B|Y6O(atUc-Zwl{CycW3QDk_q6pdUYDW-M?>t$}LtyrAETf`6 z2qPTqLU>&a$CB`1gY<%~i-bbwTj1?6_dSJ&XxMM=jf7{jHk%D)m$@i44#{Mpn{BEtbMruQpxnt5ioaii#jw|pbj_34qS=er41--s{N(^J3^&$GL?4=RG^IX>1gX5_&2FwF zDctu^Y6f|4rCwmg;)kGvXAvQ;)UH$L&O-PFxM74t-o-F106d8wn{iz|g0J-`go|xmR%|&6UV}I;<7R?#E(&@} zQ+TH!XPLqA@+RD93$CCCTKY#wJzI+P8xi7z7HU1Se$b5+%M)%yDtQ+(zYaI@U{+q8 z)lnBr;UO}+0(*(qX?3x14$xPE8o6#^9H&5-d z(T}qI9EN~6o+B#F$S+U|zU-2ih>TCP%-3WSYJmSgd8HA~Q>|yJvv8vxM2#6&6HV?) zJnyc=%VxBd-5=bQc+*{px83y}pwLRYIt2`OBPW)bZkz>dbt9L?uekA7K(W+B-o4yBlN!P*@yXb!pZp0*BGh-9M;P!4EsOuq= z>kTVnA0ytw@HlLqs|a=xBuen72{E)&fmt)S5}{Qk*6@XJ7;cXBQHBT>Fx@fc+(Zeu z=CM687hI{~xHDbCmU3J*!97i`aPvTNqnpz}&Q%5*3P%jWjWMq+$KPC0kz7aG7#w;^ zFaz|AC?D%MI7ZHY+mGFVO9V6~gR)inXxG7TPMcRf;h~xc&c-M!vC)h%i8RB(gJuK? z7ZXn;rbT8y@-&R$`o7qSks-mdW9B5%xZ`63?G?BYlBhDHJquk$`)jn*YtI5Y<_*Nm$OCK78T z=%wwR3gJvyB!bfpr9qCqG?Pq$dr8t|ep=3a#JFq|GUaAFt@?e!2I|8B4R7E^ph|KX zcBvS_4Z)+2kQRfJ1@HSsItWAXLsI_vo3xz_f^h4zP%{q~|D$Kmun+z8E4@3$6W z`XO>X3WCi&u@N`->?G>}XO^whidoO!uwyY}Cjr?4F;8Ei)Ds7B_s6o!zvA!B@X(!b z_yTSefcO&bFxa{05DgS+PT*{^SyQ${*gWaYw1(MoKERSB5#kVb^Mxp|x9*T2#zH58R1bcD! z{Gj6EAXRZF(nmzvh)`RO9`Xu!9XPr-3rp2SLJNS!xQ~)$pM}pjc4cZ|U5G`8xCj#>Th!E`X+unv?ljM>tzVxxOQ*JsPRDqFl&@jS-B;_BYS4(LNg zQ#^!g7P~w80Y@fw78nVZC2wPaL`-AJJ#HSDn;dOEcH5NG2`i>rg5hnr)ph~aoXca` zoRbN9l&ONVBIHIaHe;sNC^D`}+!Jvl48cPl3~dF6Xz&QxW=XIvti(**=sv_O++omN zaEJzv&;V1;#aVnVZsbAC!(AGjAEa(9DE|A%;whtIF9+0fhG#Ol0pMU4TGZAHEJy|J zFzEO9L#zUeVip>>u0dV|lQMTOb1^mt6Ow{~*`7CE;^yJxWpXEPaPx5Bh$|+$bK!{w zBznzgZx%5!T=Dma%j2#h7%9FWpuHP6G@4){ac@}jE-n*i;6}ZPQ_a}OMp^H!7Xg=< zv61j%W#$RE;G)EuaieXCcHB6btG*2M@C`88g@&-J7=QoYi=YItJi*LvovEoUjGRu; zE|cgUzlOnrIuZ<$cSy&OL(F*<;UOr1e{fNcVtua*R_xi*_Krj^ENHyFfS1?ajJnB# zR2`z>4%|uf*q)$*#yfE%25~p;!l3uEfg#5A~K7^?@E42;AcGd2?UxNB5$ z1UL+r$J`Zv?cxCF`Q)chfnwQ9u(b9OZ{~2DyJyQA(}hy_c_r4ul({H{sN=GSz&tSH znK2B32`WNtHREa`)5DH3rsgP)$Fo;$Gx3fxz%m=Q1U|w|oM=WnEMMTR#A0{FU%x0S z6BlDsVCZo~8n=z6G@Onb?!-LY=1#*RcgNqHD_amdu4LE8oJuf-A`G~DgNmu6Xz`L| z2X=e+uEQcw4Kh~(rbynS+yAob3dmU(!yAqyitXwRtJ2u0Vx#ERg57)kQE>>6u>9er0qOyFk zLQS+N_0$~ii?*9zYp!|a^VD<7Hv{2Zh&yfU_A>5-YxauQ;T$-l4irqz#qvRn1cUTZ z2M=LyV|j>7IlSXX$x)CDn+RqcB9CaGHF*tGfj}6!h$b`gyWmuc%piu%L&h;C6}VYu zkB<{MEBnL?3yuIIO}D+^Eekz%|oOuq(~AiSW4fFlDZI z`BuQSFRl9j@Z#GMa`Y0$ip8^UG+r7|hdvp`dFEPAEHh)QNm(!Vk4c#N#B%2?+za7^ zs@N)II5ZpPG@Rb!nhAdhknr5?fivY5U&zzW`XMBtK2DtHuEbx>xSDv|U5R&a$CIM{ zUH2wf(%8WoTyid#-YUY2w}!|RPjegXp8FaC3F7}M!jq46Mtb{2F;abO(L}={+!#Ix zW|9bY4ap|l#DrOP3r>S4eMH}YPoGy8T=(OK2#Et`Tt|GuU5VS>mAK1Y39s5Z)+b?A zt0(;7!a5@5u7sadtRqU?l_)i%eIlXEU5SD2N(^>a!s``##Fj!4+>vc>7lPsXD(**d z^8|)`4L9Bv8Inn4EgUjeAxx2e9(MEaj3*6RhsE7$=f-TMGsHs{BG%bm(hQlsM#1PMXrc@*!wtP9ZZcy%;fXe}l3s!);)@=DxZjLT z#FyQbV4ET_;z4&M4x2Hi>%|$zoHmB5O?PNBhM0&u-VXGRU!|}>G(;xo5zE!V@@0>X zE|ba-*r-9sY$QQ^&dPN-*+K#zv33DjV0{D`g~ziSW364t$f~ z?HSr@Nxmkk-wD?}xKSeFU(DF}IPj#qJ`FtMM*Ou4%@FG$bK$lCH--SB!;DP?)8-L3 z`LH`52ADW>jp;LShR9|TQ#SbF8i+fM8_5%F=R~l3AZy|Ytz|-9!nH8vTzg@=0yk<$ z++fBAjtT4_XjAIGC({6vF6yugvN>`hsR|s)$V=Qzwdvy;1vg|#Y&Byu(dDj0H|}^3 zp`A%$vx>i&>&Q`{41Q>8Vxk%C(^E6uNUSj98s^t&##IFKgvgmquNiF%?(M$jBDhdc zc?%1;WG;3zNQ>~*%qoJJSS|FSnQW#F*-Te4Z`Lgy5>~sS3bOB{adS!`Ps9xYE(4e- zj096+2q5R8Bs_*aOh0pK&qhqa=#H^*H}_O$Cd&8T>#5T`KjMpKY$6_U zSK<|SCH~~D#6%>HHX$aNv7V^H9oG!nSqxMNao+Q)LI~&wK~2IiLa;oRs76`Z?>FyN z#P`g&nqV2@A!+}Wd9NaT9kQBWx#J>JC*!VXzw3*L||WCPN$3t=+XB$!Ud zjYx#+*;?XSb6rP#8uxI{5MJ@A6Een%@dbzIdz%L)SgoT6hG)*jLNSXJp5p8YDh@^2 z(S9N9QR0z*ltbhnB^I5AM)oWVVLTl-$7J#%+|WG2yGk>`Qp1&a6gLBt9Eagdc>6RH zf5y!aq^~^fW3iMvM!QJ(3=ydfoTG-IGvZ~g1WeHo%w|5?9Gi(CLluak5m(?g&CtOb z?bo?CaZjE%?GL#(@lu{Q?Jwg-;>0g-#}lXBWl>MC3&p)@e+@Tc6Rc6(8`k%{DiH$u zNU$atP>B8RO5E(OM5b=)leB-qylt8Kgoh+D)l|rAHCMe1?@Tr2P5Wfl`7yTlJmD9n@6_ z()lP$yE5~#1DYW)#`S>qVeUSrY&D42M4X&>s|1XJmwfKd{* zRPx~V{jwfBQ>JVyvn(EoON=OEs2KC3*y&78#0}vPRc36S26(#7Fl8<_I3-Osxw+5v zB4vpLiN5Meg@!l5RC4M{*}G##Z@nn>7BW*DAMsfb=E9mpxj`G5sh2NzX%#QON4vO? z9A!ydY@FfdLb68gfL+lvpg5rClh za|6(2mIol_;?4~Khn$OI@cv@E!I7}qXO?J~gd4?XnseQVzq+E-QIg1sWDTNzc7vNs z$s6TP-s0v`pwBB-{yGGR_X66xaU)lPsl~l%zsbFcTX4s{Va>Y^z>blE$fTvwJt}Ez zAo0pYFR)EHltQ#yEQLn=wJU17ik?Vnj7kL0B<7qa+v{-y(f!Mo~CuGdO!Jl#=i; z=V!xsWj&{Q1hC6Td#2e}9kaeMP3Pz3;**5RO=(&h+F#JlPGCcfyJ3)`i&rFDSva|4 zUqvua{E4;M5DR|vFGTmCtB6d{{1$_StM%)nmap@C6hNn|D{Si(bWVipUQ!i*ZAQnAKi zWMmzsk;FD{)`Uzdw9cJi>9C5lE}n2GTifgsiG@T6zy4tfqd<{x^GaZ<;4OiIWCF{; ztdTk~4EH}$2A7bFwvlkXxARC(#y%-W`S==nCl=7OF=5pJrp)CkU<1O@x`Kygg&4RP zZ&=yOPd0_K1jQKtW>qpD+FZr!VX~_b@mz$A>=%RZVv%?;8ZQ=;SHvhBJ1#HQj~B-_ zUTOR5lMRh?Wv>xAf%BT^ID+TO{TXqw80EW2_9k(rxJTrRcD#5b!|NSKa9Dg^yhI!& z^8A6*Ycnf5I zNxWNpOx&dWxKHQBukqv6?66PV(iq8mf%22LsRqsex7}SLH%Ks%{QpmE_ZR1JpdJK` zNfi98Y=8~Zs5a~c%eS?)b+%v7il5c0ZrZx7yRD_ZwY&Gi>P4-+i+Za0Lr>Madb+DS zw{5E4vUziLYxnlaT|2tkC%3n5+EzVvdeyY5sny%?Ta~-o+Jgn%+jh5i_f$7FEuTJZ z(W!g(v@EV&*5a&9(AvEPX5>(_Y1g*S-pSj#yrGi? zLDG6i_-bK6GEqJxS&{-%e1Gj#mo`vO!<(BWN;>Sk)FQW@JKrByeq#c_s0i z-pOGpL@ZDChp}HeSuidytB>{_vMMKDt}UC&DN)_-w^UHMB(e!n%tGZ@l`IVsg$1c< z`-|V*DJ-Z;7F2j4CP&d9Vf3NNusm6e`2F)^WHUTHit!X`ZDK^8h*ktkSzR(&l^le~ z5Q_a}c8N4oLkd$p&q+}VKaNtcJjWnZ2uU#_e&sD$##pfTGs@1S5@~A&$UIMwSEW>< zp~*5N(61_qphXjt6^xV$FRDroWm@TESe-lu0a7)|LI`RMj790>fa>I^ItyDcHaTEQ z^4Pj$r+QLnknYI{SO@_eXXzv-GG406tYJ+gf^=10BA?3&LFtS}#01hA=;^5P zqid3IE3Hl*S7#zerAwzIht(y=v(nR4=@3GsLP>BXOrkD%3{$K~mV~=&lB4K^l#T~k zJlavb$p8xPe<7H0N&FzU=_Mr}rnV$UfCJGM>W4B8ge#LOsI^=Q>XSKh!sf| zDvIa<)hZsLDp_=9dJKwJ$$=oR7(cgSWE!<#yp=tXIxVj~po|44CP!K^Dy^}p%-(jh zj|f|nm&*%9tgLlHjz=u;ap|N+sll*~Nhe2oBNfcf^#07i_^0X{+1G1no3v2;!j2NF=&bPdBHzi?s<+YFCSqNVy5gP z$h0`D!C=6Qr)Sio9A3v%rJ-`ial|;5At`}sg>aghNDo~%#wEvEE20U=8vday$1_t5 z1vFXOG*%}^G8+s(78Wk!l58&wNQu;(GcydH6ITyVZz-4@Y4FL8xLcEeC@{ zYKkZ5?S`?IDKLh0Quho~VF%g|!C~qL;SRS3E@IF+lyjV0Ym!4Od(3Y}?}6sey7z

d%l8R5mRwt>+Hma3!;>}gY6%skX-pqh0_C(m%4;3zrCri(;41SNu# zHMy;T*w7bZzP7T$2mQ7XDx4VR^NR*o%o?4LF=u&8!>n05ozoU36U3bID*NA><*KRl z8aSXQW#}TQ@*0+;+e!ixCJTtMs0tbp70SmY&i(9ah=c;6!zJOsj)Ufe)Xj*oi$QNCmP&q0qUxK4hVGRawUg(Sg`AC>|7kZPI!L z{3?>AW8pfL8k?8;!DH2K)*A<*0IU|r2&RyrIyZ7MHd(Wf)u6!ei2tU7W##RDqcx^laQX(sYPouizO z8)u4hjAfY5Gm}Spm2kWmXHw2)yWFy~ zl?uIWxWH1?MUv2p;8-X?O>!!L}%3a zbjGDycJ{(g{(9NyT4yTBM)H9#GZuLiik|}?mmQpOFd|TeX+)FLmzx)+h@mbyAUhvT zMSK*TqiBMz%WRI}S{(YtB&<<;EvoHA=#wo>IjxukY|4t3HO$7dixy4Gtyi3g0mIA1 zdT>Z%Kf>N7J2cNJH%0X1kd0esvUK5RF734e2SdlPbVxPZo&il==o4~971t|8-r{WC znUa#tO4b2Uf-z}y+rcdNq~xU3QmcR_+Yrku?0;DH!qhryIrG7^5dI)w!KWvO!)u^R z&ljXFWAs(Z%6#3(8WyJJnfN%vaJPVnoWO>q%5CPrR$z{&pOOBQZ$X{B!3d)-ARgbgRwR z;d7U8()qRdO8W zcjQ!uGArSU|1esz+!jvg?59;F&rB!hV3w|{N}k0+vV2ogX~-oiV@WF9U~9GGZMsAI zuZ6l#&1;X}M{{JkAB}J=%rVrOrN*~>?03_K_$WxpY>l@ISIcOW6R~8kiaNt_2sF=z zyW#2NFl=<$59Zjy+QLN|&X$n82cbLo?jIeK74m_D@}&GB+d}N-m|1n2qYtvo<_AAt zq>rmgqP7ztaLaN0Ka9X7KL)l*Sj=05V#^k3u_K4uAhqyxXi&HaqgseGi^gC}f>xht zYlgh_&m;XKz1CDW)x_AuG}j{5nKqViCgiYBQp(!J+gRaaANxNCZ5;hD0EZ{;%Qe+- z-CSy$0IY*JyGBzhre_*?euj+%x?(i_j>h>!RdPt3&%+g3?S$P`Hb`MBfkB=5VM~Is zp5qYrl5(m)`!$chIcFMv3Fr%nCi2<~fEUz+rrjnrl`4NmGV z+acKVq&S~U$h0n_v2ffb;6MO+h9cPt5N&=cYC#b&KGgwdGT3cgxYpKTTt$SK<4@9L zYPDws^f@A2T;r>UaH0+H)6qVI(lt3t~sJW4Pg zf-g@d!i|s~6QQTAPG~q%=)MZ@t`0f7BC+x#(#cAzJUd`C9kR)=N4AYm*vU~Ajam?% zioL|-v@1>6EG45(71*D2Ugvyia8yeZGx{*53R8<{Ny?I1hxDp(!N)TWA_!8V&Tu?~&Y(aOYBB=^`!zZylp(j<;*>u2w6r}C07$neXdnvFe^CED$ROvOe{kPbhB+h7_PIv zPo>ZZqh2sTdcs3r>4{HsJ}|{xC&bJg8VZij8<=h%l&4VRjCqawk2X0!NCipSPs*1Hal^1g+gQcMLABu zaV-4M16pcK*3{RcW34w?!(tOXGq0Jx8XaoJ<`0{^)a{V~m#u}E%1{d`b9FKdan9s} zl+SiviD{M*b|Y4gWh?=UHPf1#$+2*D2yP0KKLWj#uQ1`a0~>;nMy=AI#Fz>M(Q8YL ztfpWtPSvEU&*hAp_juv?fv$?!-?4!)5K$)Kh3MqRGpT8I?2=8YUn*Q~r&Yc^^ofU( zj%LR^jl_I|gC%aVuqwtu9_%nsDC**;QI)EaQyivPbvVAoViT=~6)^il-p(36Ca|iU zvGt2uisB%QV^wx&)@s~EBoH?d*WbQzeTB}jC9L!E7r&yPO zKH$WMZQ=*-i0MZnm<&eMq^eSL*7;!xoH^8wwB>0kwT=qC&V-hNAgOhn4Y+&3kr9m) zS`ikboG*(J8(usgo5P(vcNP7@uV0F1W~mT|E*zq`6|=pb?-($Q(!oTDv!&D|Yt3R# zbZ1(2rY$~zQmbdUR$9}6MTxe=|7`>P6oRx}Kn&Tk1~GBGNb$m<<=2l+ZF5T#{iapH3HW88{5fc4o}7`&ozym>Zk%uGP?PmXyiq@db?( z8%dGG?e4CqRjKt>go$1?t0B9pHvlu_RstvDSYOhWZ2(vNHKA7cu^gsqTUn-)r!XD( znw85mTMbxY*hD_cL@NwG^YlPTjJ>Qxv{Er;Ril`EbaH~@P^7}SzMmJl|2VdnpUDly z(Cs#8SdC9+9L*JJan9osk`j#bSPWedsck% zuvG;P_;^r<@sCr#Nr@r-{0*CXh>uG{3=^iQ{e9O4*CMz=p?N%6NrR_Tkg~IrI?Tvc zd3$JIK&wB=GL@xu1v5<@pG=N0Rfe*%!?MY7)W8O_kT_BH6ABdH1naB3lMoDP6sGoC ziET#nF;?lYGum$WisVYm2!V&1Vnyp$EHx`IfBC|e9l_39ILl1%skS^EcA)7CmZ;kg#}JcU3n#TmHevK? zHEY_LGEIjRFch99`K{^c`brU&Kq zFU}7!wQn+ofdcA18h_}f=F9d+Ta44{-30w{r0E^>+Pcz=c$c)^$X8Y{DQ=0h0u#>w zSDd0W4#PBQjYVge`p@^diI!bt6Z&@`U@h6G0h@t_+)Z8%VOrx)#yNifjH;^6=$M=S!O zM>AC#Yq9HtFekGB{l?}!jk{^IR}KeR<^I?`+9~Qt#Sa9|u)&IFr))S3c4O>Rz(;iU zp@I^;`;g>7 ztZ%UF;X>2o2D#!b2lOGN#u>XbmFA2+&Xg`15fOws7)?Qg%WeOTE)}hJqIK<1%s`yv z@Tg)CRxVm6mg3wIM?Gu-pYH7?Ej;=|$k-qia~&S;W@SUZR)Ik14_R4j5t3@Ky@stC zI#9cDuFd}FP1B)`Zp;Py&dHdW?I;`)VrV`-#O!V-BmRaPS~LYAv8Gt>r?A>EBa0oa z5)fht=T)nU-UW*ly9mw5PH1Nhy~$<-<52{}M{S2<&$Wm?L;7gW(#2=UtSh&IkQ)4v zgsnccWWvZh2O~gq((UWu=){E+KbOjQ*A6pPB()N(2CzUvN7h5L$&kSm+w0l=YM$@LiBRr61mD zg{!UoQ?~z!)p|(Sh;0H2f+s($q%Hh9l1+%l-1=M&#G?1DtNp@HWAl-BNcZh@W=a@_ z3^~f3X-g~ABzGVTu_(3;8UpzqzR9Kqs84(g?}rl9G}9NKG$?IoIvTUohDjW_p(;?9 zLXN5a1{b!^*#W{%w$M<%{kHXBrFEGiJi&(sWfF)+K^vmDF~+-A1MwOgG}~V-;HxjJ zmo>}jdK%qWl{dw_e_SMnXo`v6-SEdt5IUdX_*g&Q+L~_wbMCi z%ZE`GS$RgoKsi!8@`x{*uEs6ZVCnCB^`Fd~@N5Vf~V!#`yv}owe4-yyCi35^iFTz*&PIO_box+Mzi3VR=tMl0}NzQ14Xyfh0%U~iS;i_;;n82EXP|L z2Eq=kr^7LM4@`A1O0B&?8vOsRs>Cg%4qOlRdty9%fbaEcMjW zXFDEAM2DL>9n7?w!_)Wj#jM{MR81U=m7`rMlfis^Yt6@wRId$ir3ka2;0YXCb!WTG{zwc z_cGK5TXFD?nC5KF?FSJY!x$wt7U7tQ?UcZPbu1gkqVs8iCRf@` z!E0QdO{ekt4&8Y;YsZ#&>xOCA7ShH8tyrK$Bh%rQ4h;^z3`8?x`N9TA4g9>@YwAxe zlkA!HE^(c&{BXFOH^#paZ)bdL3ALi$CA8B=w|FYs!WaR*h;Bhm?rUjax}`&9c8fDI zb6|+|CWi=A;<&0U>#Pph*PW}AP4MHY9TGHY`13;8I4wjS#y2DJ4nrTxAMJo`6NG_o z5pNTo9#HAgO;T%7Gp?60qtMx2rU2PXF&)?d%*TF9*^jJ|)>I`V0QyM5iLCY^$8n^MXQbIp_s+Rz(lo*o-Rg1f}e528AC6;i|`I7(o2M$ z9PI|ybYL<0vjXT!|M8q-!sVRP3r53uyfr9QjH-gic;oAM*aZhXtK-|(#h8jpXHQ15 zr!o%c&qJ`2fe^VmXT|we4Nr@BA`6L|a>3ga1e`9<786Y^fM{G zI*Fugh(J=-)!>|Y(t*>WRBB$i4R3g`gS`-jtCF#-9!3bN>0qRWcO6+9zSM&(nY)jr zHm~`|+u%9?&!G^g%y%f!qANEH{6CBrLBsHVybxcAS1s9uaO`iD;UjKXuwY@%l&9Bl zshvrnWJ#RavI`DF*<8L1xdel{p8#->=bFPFo{zVnc&<0j-e*KTxFYfl&$Jx)jtbx7 zM0?sP@EpqrJLD;7WS?*tJbJ4)I&zMxW+OG$ijc7h#UI~AkMVLVKA<{{UHtHGT!++5 zpdI|^2{+W?$W$GkIBu~e5;WIm9~h8qBGthLj|u%$e~LRUznMkm8)>RxUmr9H`6&cTOu;_4GSb33&R@4b}GGOdN_ zVJ5<}a8!vWP%JmsC}23CcNd?MuUoh48ns_7(@3$(g*N5!y)C@F@5=#B5iFH9$!NAM znWgvumXZ@|0?Teo#NuOQ!`aEYb#N)b`@J?2aH-Re4&h*vEml~^p>}*TBOESiRBu^l zorjf(j#7N+i&Qb|uFsNEuY6^}D(VFWTg|xcA_7D}#g~wIm`vH*=)Bh7y+a=hTks&k zR51MeUK=BD(9Po7nT>x?2Crrngr7nu=a5nm{%UWHe@Lg=UTG>?0as|DtrkzQfxdtb zt!YrV{dC628-X6S9~`=Rk1WbkSwdj9luSemAS&!m${FYO0p;mPUb+$fxv z0&8#!hVz5GRmGE&eZu0-aVUD|fFvFT6i zj5QnQHXh21Gx}VIsn1jidY16zW`07SP(u4`f@h9XD!3@NS=}qcN@VA(YA#aBl7*FU ztB8g3%5p?xfA5cXy~c7g#X~TBc$1?e79l7ekCyRNpJN1uY&)jb%S7nLwzxK_mEbiH z3^-BeCrjbY;V3I}yyRnpi|-P-__fi`!tmUrcntD4Ek;{X?O7|#OVm7$Gxnl!Gy-AI z3}@&UyAG3OT3i$ipmS=idn1Qv3wwTIPs%i~xK@>ns4D8?ZN@H`0maN;0w^2jl!5O(SFm$e zFWfrtg%T|n?C5R_Hg7$zrE|yT^XSpi(b{YAclLG%iyB&1tZZs&SXjGYU9hOOX;EX) zvS`7Q1wm&k;%@Hj>1F!J4cNqph_GZubM3Mv3tAR5ENNaCbTPf2;H(v^)AOgEn)a{C zNKczGZTi$HQ%*}y-oAO~t~r}`boaLJnY{f}*n79`+P(?wfP2Tz-KR`$n>v%$&K<42 zlksgEbGEj2x51&cd-K*g_#Tekr?yYtep1KIs>FI6l-PIFxwDfkP6s^7OCg+~EZ2@G2TsnHTA>r07?#xnIt%DAH*GGGRZx?~M z7pz&?upnrfzqqy`*xA~-wxz4REsd`d@y2LsS=hj!-E379 zVq4d?-fgX&+b(JkT6@vN9WC3>W8N*hx;nRYork)#w|2WWP5;m-4@;& z9F?I0S=|w%K1ytY8@!l z4wTqDx3oj0w{^B}>+0AMm<6#r+gjR8^G$?Z?HABRU7?jSVX;`tu6D@L<+fvUZzp`Z z+gsa!o!yXdN6_nyj`Vwioo(H_1KM|V2fN@qtED$+SlCGUuWUd^u=Zom>}ubGdRa{N z&d&3K#wK*Js9jrxndsiz|Yxj;$Yht7l_1^m0hT7!|n-(?% z7nn+BGYICbYg!oWwA!?^wC)Ucb)pG7S}y3`25m9*+-&(Q>e<$20zg{SL2sqTCF>VL zFbnt0-`(q@14X<5f?B<-Dd6bUg5vB#sVKWO4fPF8f%PF&s>4bPnIQz!h)Tup=kdz6 z?bx-c6WyevyS?3dW=}gZFmZXSu{}5U^iH3~!H~lsrPm5I+Uzat74VAI*ETI?8*ubn zxT1F6GBkvg$2uc3@dibp1xp&2S}*I_ih<0!9(vV|U8onn6Uh5g8&%Z0sI^B666*=t zyUurCj?^s|pzb>^2->V-7i>msq#d=#3bY1>0}KuwEuB5>?dKt}&F4YD(Ax9hhV-oB znKG|jeb(ZZ`70Y1vYOVqUDl1*>9=hPat4akOI9?YExLE?z;_TqNKmQX_7)R%OQ!!G zIlgqXaC}55z3nzxv)GupeJ9Jlaw(?;n|?M~JD`R}W#E(1j!oy9y0o=RRNbt4rhEv5 z*`-(gwY6dX{FeG<%NlE!ELhUqP>=6x+T7I2cJKDVha)jNvkyx>uJ$cdd6uYY$?}CO zS2qRk`E^g#9sG)>1&vL$O{*KNvf?xU5&_gLweW5-L zm^nAuq}s*dQ^T{>%ElGzzOFc#I#WfmV?oRO`O6#j1e|<)AnxsM@7=sLo;3%C>a9Dr zw^w(xx3yL;UsB&x-O$>$ZAbmq9lblcwry@{+=V9S?r7cI-qPKQuYsyQtG%neyA@+q zOa1(Ld4b{5(zBzZm*0mK^s;;RT&Rx3IgFBA)3BszVM~3($|elgIiuA4`FrZwW0$O0 zw9>j*cl#EM|B#%`rqc2rZ=l_niENe$&YC~}^z@{ur<`s}gzomvsgtLjkiT9CaPjLN z|Beewuf1iZ1I$i$Ui`K^`bQVP-7RkCxBJEI{C2;8WY15J-~Ja5&u;;YzS$2(`!>MZ zvcmlZoh6Tz1-1R-Vbk#E9bLD;P+L~IKfE$=RY78L$>ZO)C^_lRMVK`1=;F5t&SU!X z5VnqnWo7&Y$#_02PuxBc_IMd-uPqz6zwpZNs>HPg|Fqw^9&cYEON@AxutyiawQye9 zqPbQV8dO-+VZ)Z211v zmC36LuMQ97mwl$k?XzBc+%J>v$*@Nkzd3PUS>=%>uPvJ!_7s$qRnF_5jsk=HhQ)bh z>HWo57G0IPI(eY*n(+NBOT4V_AY5(P@O`QM$tw%53a`%hKMeo;y2Rr@{~rFA^pSpC zj!Y{q$29EG#czB>`S%s?FS;^yRr2b>1K~CKvgEfx#&skeMF#mzfzsP+3sA|6OUg=X z@ym_z^7C5+^XnfkAHQ@io_;*;Iqwmd-#{6Un}$8QHo_3|t1U~nm6Q#v?LR3B0P-6v z=ar4ht$l6T#>SGeQS(rbxNh)UEsvrbvl8Dm)yN6YZ@)Zh`1Kw>9V?5=Dbp7rvQ&$QF zJW3s=tn(@aX`~Td*TN9fhxE!m^nqhVZKe)OEzfk60C=PvHd(pjVHO}0b|%Sz+p+GFNFB-@K?%MKJQD=8ZSg^%aE>F9d06~Qrr znCo z?(g$M<8lznt9fPSFtmxos*_7%)4J9&TqD@(5GcXjcBqH9v`PhMMCTXsu9II^JZ z_GkI7>;nC-Qv5peWC!NWU54 z-$a~%fBXuON^bha!AS_f^trZ4ST5NZ_@$7%@cn}63eUMXVYQEkFUbpE63kY3u7whr z@6q)*VbDJ>eE(p+!gH;ZfPef7u^PxNe`&B(;rCkjQk(ZVfBRJ$L_a8zhC=~13HWmzk=1u=okM#dG5i z4tBts?J*a30{)C&gWE5D8+rB$(Q3Kzhv-M}JWc}sj6W+AWk|+ELx}G)&W%4T*avs! z&-piz`MzUVaD~CKdEt)@IG!{7MBEAZ$FC5n1BwD}bV&!$tA!DK;#AuXTzLSFfiqCa-0{)c$5SaZsDL9si{KVhS9Jp3tn;ZF(9Qus?O{3+SMFonUXdErkDniQU6 zTmt^_D-2G{3x8VBqVU`oB;X&vLX7sg<)0mFRe0_Z5;hxTV}!w+yzp~^^A(=^h6McM zR~Vd`7yiuPVuk0LFaiJg6$Z6=;cJ7d75)qhUmFh&`OMD?KR>up;m@(~^Yg+l%nQFT z_>{sQu<#2_UoXqVT9`4>5C&)E#Xrl!Z^(o?D`WETOY*`m$@5>D=g-+OdxZg3PgyHW z%X4gDurkkoW$+o*$K|^+FZ`;!@T-D*6rTH#MD9;^p}viI;j_Qt!i2+Mb)J9b2d*sN z5VLu1`J>t0yb*t0p8q=c(BCjPJJ0{@JpcFQ`Exapy~3a+&%Y(>2~!xf=J~hg`ESni z-<;>)p6B15=f5S-e@mYKwmkoBdH&~_eq|lc%Nk({@e4w^^6j+nw`7*Zox#`8zPz{+ zD!{K$K9XbKZSn7qh39y^Ad{%4zaeI4TG15-U3vL;MP5eyY)YR0&OHC_Jpb-I|K2?R zUawy!RBy&aLx|r$V)?Vz?yM1}5cSXXzaYsUp8rMJ$S{SN z?{eewcaO6dehMdRfhn|Kzsx#?!KGP?`Cp!A-)py z_OpX^vU7YLjNQj(*%z3-B{*01m(1Q8^vce&h{3_;;8NKiGkbe*K=w^m{w=|EvhxgK zaIh`-xa>SH7>xeTzRmJATl}uzv$Bsd`_AB=D8AXdg9l`1y$17FnC;O=r9DNlN1~aB zrP1pGnWr()^KX(*+oESbe4l_1n==|k1iC6Z)SoGK@_TV}8JU#ZXIQvv5 zdVFk8y(kYKgpGh8$H+X(h- zvuY}zaaK+7N1A%$z#cUD9Dg#C0M$jKm+VdrJ_Bd&Weq|44NLmI}K6 zG_YSDDtQreB<&z~_$62tO(fCjEgy8wk+dWKc_h-0@-zRsAecgTq-X9w(@(R%?DZ+Z zGKga`<3A}rPa>Tm==^k_Ag~L66JhI z_UA~%v-GzF!6#^+q4t1%G40?UvMmU{AfgG)K1Kc(4*p2W^4lu+{p5C~i*~%9_F>8& z`Jk%SzHgAQ7nA4uc}vM|wL2=YjP4`+7qCjOZ9veV1j~a>Bfgan@h8z8 z@hx3U@55y`_hCw>+~+#x$8nzF3rUpM!oRF=2tSwZko#hCU|>IYNN$k5Lqt-hzmYzs zX@{^HNGzinp6zVqgnbs>_ex*K`Y%nE{4xlxpgYq4pm-aJ`rbp%ksibUS=x67!OJAd z|0Y=(1n-ha=zg+4 zccmQ8p&j*qkVHM6AW;vz%V_0Flc>+rvU7dLa+_QckLx4a*GkS;kqAGS>AcUMpHUAM z(~e56C85t<!cs3=ZQ=Y<(o@J^+bLfXa}vl@VD~yXdFa3 zx6>c_m>wbAE3`vCzb8?zx5;Mo8|9Cp1SQDV^81fMw#QTGo zN_xBs67Dldq}L$#4dPbuTKOL&k=_e(e?@$QL^|)1Xb0}`6ZfGXi_64Hw$m%>Ps=s$ zd{pD(!K}OWOSoG@@;~*cVccOTj*ete- zz2ZLc2Ju$W`XAEyrtD9PFN(hx|0bS&`^0O+4~riaKPlcSepdXv_$Bdc z;y1-_i%*H)7k?zaDE?CXt@xHWko^($8YYesE5u1+wRoj?oA?Ft=^%JO_HU8j!!NnY z{wwlHC@tnt=2J#K5d`J3j}@E54~QQZ?-ZXG-xbFddwQpf{N-S#zma?dt!PJMnd~u)oKfD9#pFkVyAz z@*6?WB5o#;?giq%h#wF?EZ$Bc-s9rW#Xpfq_Z@O6^au+pataCeIpj@vCq!IGBER+G zIbyf`uOSid2J$08aFh5667lX8za%~?J}$l@z9#+`iF5+Yh2$6#>7PV?JqW7B=_Jyh zBmX6`FBi`dH;LWiZt+U-8u6fbv-mmjUh(@R@-Hm&@(d!sg!xPyL83h4W zSX?V^5L-#qbGz*4i&uzOi60;l?&IQ@$;X1=>#~2Bd>rct66JYGd|mvLSa^*47mFjr z(P9OOe5z!hCY~zy`LdrSo-Ow+vY#jJl>1)UFB7kn`$xrF<^CD*%i@FLH%XM|DcS!+ zd`|8!%l?Y^C-E=hJ0#*4V@*f7l!}8$xQ~{7oH$YL(`271&X)U9agE&17B|YhQ}&(W zF1cSW`<3F2;z9A>#LtUgBvHPHWq(xs4hjAHPw{oJY>>N87MF?b;$HH;Ah=rgPl^wS z4~x%=zZX-3J>9f;f;dN9FP=}{hyAte9}^!EUlhY~Pw!YUEuJE-63-R)i8qV)lgQ_r zvcDq!uQ+mur$0+<6t{~9#LtV*ioX&|u~4OaCx~Z?>%`sShsC?ZZ;LO8JfL7YQ%SVr z8RWe#SP+a z@nhoM;$iW-;!EPY;_%^~?#bd@@oe(>AlOQNJ_tI+oh0ggk^HZc{r%!6#Y5sV;&b9J z#b1km72gpDV1vQ*2Z;YW+7imOSazlr=eoF9nik|^h;;y&?4@u2us@geaM66yS>_-ApzXm=kc zPA8G?T=KKnAB&4g=%f8<$gf+4~m}>ZxtUPk?$k2e_MP~?$68q zg7`DJ|4#PT#XrlP8*-MnP%IaZ6(@=(if59jZ;N=L_#yFD@oOZ?`8fF*JeLrkCXwHd z<^PK8uZjO7{;ybuGbn~1EKVem-Xd|mxQ9f3SCapVeWmyz67g>n?-0KteqH>Y_>A}p ziFDo-k4?LMs#qs(A(3w{c`KePh} z1I9TAiNi>QuaJGBc&a#CJX>rL+eoCpPyCp8i}*G1c@pXWlKfN<{961SiSqDZlq?j7 ziX+4m#VTk3@SM6mJ$kFWx79n?$^yh<_5_C6R9b3E;0E&DieqTHv+ zK2w}cqTZ{;ZQ{k^r^NfjC&ib(SGZ@D;LJYGDRM1Hem zuMunIzFhWIVlxSO>=gHl2gSR^r^Hvq{}D%==<%nJ$afC;A)IrF3rUoBy?BnenMC*< zviFF4Y7#kJyg@oMpt;@8Fh5PvDYO`={!lfn0+e&R7CDT#E~l4oOoCvGH>?z!^cE&D~{2gDDHHXQi_N8LI+&9R+QEZp{ z`Lgd4uaWylW&gPNZ{p|0hs49;w@JwPW$`!S|BAz=xPP@cUtBA07q1XMCf+SRBEBg8 zMeIM-(@l$~h;?F{c%k?q@iy@*;?GFP`}gD;tUtv+lhBub)0_ju!6d?uk-b7Zo<#h` z;`_vIaX*Q8*OQBb;G^Pga=(XsHVD2bJ}N#gJ}61AB0TpI zN6UYjI8&TWBK%phFBLb48^xVsuXv?+jrei#Q{rtT@_$HtMtntln?$}vGr;*6r^I8( zXE9ERlf=m+!k;Gl9C4XgFLsJM#mmI~;*H`#@w4LR#0SNP#cz=)-!H`1$y%K2lPC{< z>LEy+0euk%kSKqJI8i)RoGsRgE5!GSt>R9xSKKci5I;mB-l1QgooGva97mI7f4Pq;abS@IF6+bI}gM1$4 zBQL;vH{!D-^82;;JMkTnAMK(4KyipTUOZkrnY=1jz{o(=f zpm?)*D~WWzE#8#A$9X7mpQ>7f%wWkchKDTumbVP2|NmpAyd{ zk^ZIPKJfsF@HfhSQ2aOX^WsC|VeuL9Iq@eX@_SS4f4bX8kx2gpvNs4Oi&IIIXOUPZ zt|SruY}s4Hono(eA&GET%6^Ubaq&~)-QpL-2S}9TVewh z*awO0NYtZC>=yTlSBnS5o5fp6r1yE*?-L&pzb!sVBEMI}zmbSnTmxdvC>1M7lw*>3 znm9*XF0K+ci5=nv;=hO=5I-z_ltjL_k>}w(G4U?>9~K`Ize^(g4`u&}_#5%R#COHS z94~*lc&s={JXx#}=ZXtSlxKywRXiYmhD15ONOlFmm&FH3$m<#LIq@eX!oMo}Z^S>y z{cYLb6_3Fjz;w#RN^z1nORN!VNt9!&c!l_B68V0P+=S=J;+III|AhEG@%tpgzbO09 z#W%&b#MGG{zeF4%juxxLY2v9Q@?R>ph&|#B;vM3H;!`Bb^JB6-2!1NQOrrd6iEoR4 zClS8?T=zdl94n3&r;DeGi^XN)263ay8n4?jUXU92Zj zzW0$$_?io`okTq@5-$<=kqG}`**_xQF5W4Aof<*e;#cN2Ua|4Mz+)d&qNaXjBcvyU#MED<&IBWQk_y_sF zDHbg7_(^e?I8scLNM|xR5zjZpQ{-PKt`J+q&0@E>Tii<`y=%ydAo!4YyZrAI?;#QH z>*Q!W{}sO_{~wD#72g)$70VVP9^^7u98My=3FJu3$KpKsFA~ot5pFAaES_VESIYky z@e|^w#e2msiI0kpi$4^9BEBa6UVM{8zJDW!;5nc;d=c!Z$0%{KI8~e{E)rLZ>%P;^X2E#h-{jBazQ*WEu9gBEB=&%HK~MDUJ~ z_J@9nb@E>!wuqa>Z6xCDCX3O(#gEAUW8!DU&x!Yui1#p=#QVkKkL3TK;_t-Q#Q+!I zD=QRB#ew2*agF>>i-;-H!gY%miWiIbi4Tb15K&}{ z_k{R8@rUA1#Fxca#NUapi*Jc_;`8DQ;xEKsiLZ-)5{oca zGk$+@usBRSL7Xh|^B4?2OROg`C^m`wdDYDNHXNzZwi^Mu{ zmAG1L7q^Lf$dBOtK5@TzK)g=8QM_5aMZ8nITYOA>Li`W$2jUCjOX92IZ$x_!9_1-4 z@^bYTj}eE7BgJvz1hGb(E1o4T6&u86@qJ>exRd-k-a8TZikFE8#1D!$iU-A8#M{NM ziVun362Bw9AigBND*i@%N8|_VSgsW~W z#m|V}62BupEj}yS=O|E*pUM83_&0`# zE#i4%uee9NRNN=tEZ!o1R{WfJzxY-0o8q^`6gC*FM~OH{94d|y)8aI7rf8q#qWvFh`$qG7vB=!77GS= z{qb8nCI@`gxN)FZAx;!0i&MpAV!gOVJX^HSi=h4;vR^LR=SATDLD{bpzbSr8d{TT` z{Gs?0@n!K9@pt0u;$OtSiQF@@y;I@{NDDbz>p@65${S0xT zxJ0ZMo5Zul7O_J-SG-!Z&!r&!8)ZKz9uogmyj%Q&_!ZGUzk>LW%Ko_cAL0+hx5T%_ zf@7o);{Q|Goxtf-{{J7pEniW|E?I}HnKYJ|ke%#Hk+C(#EM}O^%viI9knChB`y@+f z(kQ+W3L#0M5Sn&WQmItp_x_ywb#$D3AOFYyJi2?%=bURk=eo|hu5;gW-_CUx!4g;& zL$DgwMCX1M?Y9we3v7d(up35TUyR0qI2RY-Qe25^aRa`FZ{S<_HXgwD(YfD6^*urS z8GeZu@FM<-f1pkF;|!dGi*N~M;u_q9n{gZNze#Ar-2U(x%UI2I@1G@OYG@deDpHMkvj;k)=Ap2aWlZoLO>`!9o) zuqxhhpg1)s&axB!>pN?eN@@HKn`-@>=? zARfl!coK8)E4+eNF;9u$@w*L6V|jG$H`DQ|K^$&w)bYbs*cQ8DckG8zn1D$*0Vm@O zoP#@XH}1zncoaXuv-ky`#~<)AUP0%6IJGBl$zZ$gz(QCOOJhZ>f}t3O4X_b9_thzX z8{$sb4dXEp({VVC#R>Qf&cIdp5^ls-aVu`eqxcD)#V_zY{(zV93Kr96O?Lk8#`0JR zYvBD@55uu3I`{c0PkZ9d7>xrl8Pjkij=}l32$y3fuE$Nd!+cqvlcIC~pyKz5kK;-F z0>8nF_%q(74^%AQ9at1gVk>NmUGOpNjZa`KCZKa)qVi`DKZ)bexld8so%^u;a5B!oIk*UyU?#4?*Ue0Qu7YplK0J&cp>sd3%AY0v1~1?>%w0a1 zw*VHz5Uh+f@d0d)ov{b@!u}Y8gE0k%;V66xpT_y-O5L}IEAU0!fLXW|x8ok%kEbyQ zzs2wH8s@GL+;0Iah-J;?fj|gW$55-OErHVZpH1m2lwLl|V98Y2neud8c*xK)p#J}O67*>hnf{m~# zw!!w;4SQf;?2pcU+S=b>;xrtFW6-%@Tjiz_Pse$<5SQU9T!$Mm8@J+4dTlKC+`~cR)hS&sKV>|4M-LVfwVjK>_AvhFA<9K`y7vl;tuV@0fj zp%{iu%@+cJme>KipmX28w)Y{9#(|iE={NngY3Z~;I9E(rmGx$6%!;R(~ z-4}=3a0l+i1Nb2x$20gj{)&HKpn5QWUMzzZuqxh%wedl0jqR{6_Q!!Z7{}rSdeqa175}}cpdZH z7d$RyF$Ak&O{|0U(U~_v^>yY=keyiH4P!7Kop}>f&Y3qsPO$Z}G%q^N#JTu9F2k2_ zJ#NO=@gN??<9HG;;br^_op}~ik9;+Q^|>8OV|i?Vjj#o_!A{r>Bd{+<<3JpRWASNp z=4nuUHV|jw8~7%^jr;I0euSs+EPjI*@MruDuVL;`jsxC>C9yPyVLfbwO|cEO$7mdg z$(V*CaSTqvsW=Pg;Y+w4U&SqW7(c?3cm^-y6}*ml?x+2D7nZ<#unyKoXI=`Ox8}rc zu_H!cUv%cHPI3|M*oQ5-TH9GTVs6JW5+4v^z#C>=WKf^Ea0$#*l@ejN+ zEO`71V-36?>tQ%HMQ0uk)vrBqXY7H!a1bWrQ}{Ga$Jw~toE8XV;>-97zJYJzJNPbs zfJgCL{0@J{-!Ome;QsE!idY3hF$^1EBkYNNZ~(^P7<>w+;&hyc3vn4b^Ni>?yhi*6 z?lU`Uo&)>{KgPUug4^?BAuNWa(V2fld1?{Y!H4i+Y=zFeBq|?4+!v#9ASRpv@G#rNGa3Vg7v+zY+i?85ocoNT`GY^XPe~$P^`~~yW z3)at>A4TQvA})%Ruqrz9qo`bM;yxIOaX1Kv;82{3({Uay#Pzrdo%vC;zqg4$!jJI` zevU;S47R5vmcxoz1MkNN@gZ!6t*`@j!JgO$2Vfi~V;YXcG3d;%qV_oRtH_nCUyU0u z3wPsQJcLK^B%Z zM&lq%#$h-LC*Wk9iF47JCr0&j=82IzSic+h;~_kXpWx5<8~%;C!h`KEiy_zun_?Sm zj}vhU&cwO67?Jp2aWlC$p#K zcfh|fSHs}?yRi&b!m8-ZTch81=B<&PSlg9f}t3OkK*GPiP4ydsW=>;#OdZJ-G__L{5Oi7`ETTl ztY3>+n2p3AVr(jK>sA$5A*IpT=i! zHqOU&xDm5)D?0P(=r}p^>Bvu6{~3OR7w{+i6|Z98;b6OqU4z*Eq27m zuqO_}WE_ekaT%_{b+{3od3dycXC5B8oArC~5IXboXuC5nk37TrbND^}g1=*~Cc*ao z2k*qfSOzO#7}moM*adrH9~^*jn1n-cCeFp@(V6E*?O08`4zn;D-^87`4-cX<|Bvz< zC%%Zz{6AX%C-F7>Pt)M>D1b$=Bs%i}>GvuUJM#f4u20oAhyBw*bkj~l~lh3;v^hnP7DN|!e?*>uEf>20kiNOd>0SnNBATDf`8$4%%`zx z`@bEFU> zJdUR^2Y}m zcMI`0+=YAas5wUSR^ey(CH{_oVeZz!^7-%{EQgh`IyT4F*b%#8Pju#kQauI`$6*o< z!3j7S7vc-J-ptVVF5~O?U(CU;@H_kwf5SiV_BO$McVP*<2Sczj*2D*}J~qVW*cy9a zFYJ#oI1VS`G@Oag;bL5e8!;QV;!b=A&*B&O9sY>F;h&iMk>K&jhXt_+md5hf3A3SBXJB)!l^h5o%yJA-k&F4hO2QMW??qIi92y09>fpvIG)BF{1%;gthE21 ziGRb}^tX}q$2%|tD`O~zVFPT0?ag@oyJ&nId*fJ~fY0CzoR5oeIcDN|+=N?j8y>*- z@fe=K&+tpUfEV$OcES1=!jf1TD`FK4#V~Aujj#o_!A{r>V=x|5FdY}+63oOkxCuAo zHr#=Ga6f*4NAVP%#jo)^Uc$@x7hcDF?Sse5zC+s1dl{^Nbxgh2SRWt8=GYITFdh?e zGET$gn2GCg6K=t6_#qz0)0l(j@dvz&SFm7*VEv0=DJ+Y1&B1!U#HQF1`(Px-;UFA> zLvb{Y$A$O;uELjaBfg4TaXWs3pW+wz4gP>X;T61!c{&E$cN^Y?MezZwiw&^}w#IhY z4SQf;?2iL+Fs9>hoQZRBF)qc`xDK;08{fkZ@MAoMpX1l~Jzm0Gor1^XKUmyM)_i0b zf|aoew!n7S3Ar657Qe>xcnL3KA$_K0 z?JtI768u$=CjIFROcEQIm9f#vMoQTtKCO(IY@m1V{+i@4Zi|^q__%VKq-{GI; z0L@2^`MLz-+c6ZwumLv07T5+mVKw5|E1!VcI4AIIJ}2$OLrj>L7i5wmeC?!~T$& z7QT%K@O?anC-5`;5`V$pv2c%IyNhEvtccYy6d%NguoiXES!g{aUEu1HtxfN_#qz0-|;WZ-7C2Nd{_vJVQDOn4`5wv zVOG_ABG?%p#oqV?#^E5GjMH!qK8LGu9cE!R?!o=|0UpJl@K?Nwf!@J-7sldP4Qpau zY=9ljO8P!>jKIDajRSFnSx%ql<0PDlvvEEy!4W z7Qu>G1w%0mn_(;LfL$;J)A30hhm&y{&cWw!EpEVU+=}m+r2~Nv@MAoMKbUvxdpPh4 zUd2*|4M-LW4=;V>M9PvO%z9cSZeT!&ehjql=nc-kx;2;|_OcnwSR z3vRy$L$ET|!*FbmoiP%lahzF1->;0*a3-$DO}GWO;YmD$U*S3Y5r4s}7CSod%#4$J-r{O$Yh@0_s+=09C5FWu#@iV-D7cozy>UW3! z9W363MX?N4zEFAMsoK4h!@T zZZC*sumawXwJ~2n<&Ws|Wm9=enQBjnspC}L)cFiE)i1+MjfZBY#(7&)*8}}I>0HPZ!qjJhYfbGW%hY>( zTg}daz%Em-WA>YR{dUCEYlai1t~EKP-uF0X>hG;fW_%!U#T=~v<&w#IU11L4`yMjX zev5~z{pKjO-yEa%o8#4fbE4XBPFDNPX==YYL;pV9oTd9k%sFbmIZy337w|m~i`9OM zUr_tarE0&qTs&~4z=Ih zsrH+@)qX8@zVl*!Q~$dY3!6IsI@OM)O!b4Z7-FhFRL1J23Ws8tss2$9!%g**#@Ng( zr+HYgt*Pg6y=@tMJ~!2Wx?_Z?ex%E;V}DcqDF)+B^{YfoHPyc|aD=H!jK=Y%`r9O& zYO3E&$JwU(-+WwTs*+1^g{l7dBCa*nFE?P8ss5RbTTL})JMJ>oU-#gCQ~mZ39x>H_ zkKqYZ{rEKInDP2PIXq{oUw@C6O!e=}c*Rsdzls6t2N^p5nBP>tcfS8b7PeUZzc`jM zH4e&Rh&f*8AFG=h7oiwtYJAkga8u)?F*Y+bURq&WQ{$#1b~QDAx?_Z?anu+4n;K6s z7;kD^C1R?n@s)uiOpUYAINsEFn}k!%l{)`8+tm1*kBdx=!zH-F)OdUm*P0ra8!*e% z_{_$wrpD=Z++}LK?!o=0#_b_IVru*z!xN^)@oCI4HJ-o1bLMWHe+)4-zB`!tX_vlSMqUo|y;o$qHUuJ7l{tytsr6;tE%x~cKGGmosKev(&eJQh?=8;A2vjX&r69W?G9 z%BNW4ZM_+;`9w^OukyD^jjNwcji=ZGvTY#nx2f?{`F5#sbHUVj8LK+lI5}-s6uJKurda(ie|4#T=iCqe zg1#T8hT^6ATv5ly`d6g~!>(n^c^H#(< z6;6NXP8?zCSjQ0S5IfiP4B`={j_oAksiuzYeBwo>j-hk?Q+={6R{z<>_C01*u3OrE z&SLea%WS`5>e!XC{;BO{O&z1^#G$78SvYZHGo0&$%12n-i050y&iJ?MI^~^lt$yf? zOKsn3>va&Eaj4iChaDJqici>f_0LQE{$;b9u8%f8w7t05UDrM0Ftev#7Z7(e`{;R} zc(ge{*Ae0sruwtH$d=sL;v z{-*l>2;$ME#=#Qe73LW2pLmx!UhO76ZBEqd2I8xx#!2zKQu`}qYP^IKH#RkHVu<5S zji33%i%gB9J;eJ>ji++f0?Ju9S_Lv%%t%%#28lN%5@utSVv{1HQ%CZf7Ny5(2ToRJTT&`fbo}7R z==iiit+d$0;C5S+m=ZnMvnn=uh<{Z=aW; zQp&K{f3J;>kBuH28K?7lBV(L?Gjdo;;?N{-Qtdl3F3P)Sr;#_UiAhL{Opi(MHy!p^XCZ!Bb_8x?|$duGrZ`0z`f}66$MGj9(xas^jr*S}> zcUR7;IQ2kp?c*Y?2A(>`siUQ&d(TQ-WMX=3tam^JE2M`1`}h1St)l*Q=@~bj(YQ#R z<+!xioA;TKHZ(c<<~|n}IW##jA^GN-Bn|ebPm8tguc`%yL|kOj;JEaEkA~p-n_8fH z+|)@U?U3D6LMwbF(h`z0;%@9LIz6LSm^Z3hr&jG7aqAH+hv~%X5?8B@My@hBKc*+> zG&w&-WwarEOzeQ612qn9YzKdi8ZaO&c37}B!8JGf90k&%k_TE+>uAgxeQ;qNs4dPjtRbUGZpKl?2X0U?`*B{wqvd0 z!Z%9&Q@>Tda$6OT_LS308)sRj{}<4snG@-?NV8ndaha}If9^Q%$=LbYqK9|C^%R6? zox8aCUeyY3zAK)5cWIlIvwZvY@aF5TV1?GXi<@tcR(SITn*UQjYqy*4Q~m7CXRnQ$ zX`Q>c`99GKZ@&DVd_}d*&392hd-K_Mh&FbUQO?2(dU*2{_T;mE~9$Fevkc+e0JWw z`Ko*JS$}o&+28u!e19t6AZ>RSw;hl8@`Zcy>CfRC`JN!3{`_*57+pXL@v~w3wf&8u zoO`{>P`M*kfW^w$GSau-w%Tuq*4uHZpoiOzS-yO&w4trGyNlb7Rlai5Rqj^f+}`uh ze>bkD3skO+n@qa-Hmi{LILE7gHg2qb_v+!+?|?7gX>G7;o4dIA_WJUrdX94y6?XG| z=F1nRze)7x|Bc1X_o*-6cuzjN#=H4`_2skg1RZfBTdE^S)(Y^V$DqonkTfPVMaPzhB<$L0eKwy`) zyNjEzi7($d<#We*Z54L&b@$~fe`g@@v71b~`MUb@T~WReZMXW>)x*s<*q86J@{QGY zcX9I#^yMqnGM97xv3z<9ryP+pT`>^lto8mncD6yZoapD`QnwY zx(ZpoUV6CsPWkd(Rldq@GU?{~*q3j%^10);k0;-czI-8i(RZus)px#pD?Ih<=gF5x z74?qaWaVphi~3#n<=d}(?)ixHO<$|Bn zx+&e`SJ{^@zg{T2=Ofya?_poQ#^r;bL&)d;9Wb?`KG)TD zcd`9i`e%Ln-L7)>{wNhll+W#_sh)gq`SR^jzN$B}{WC8A>&utw z$(QEI_kl0pH_F$_t(3~SKfdS7H&yu}wB3%Mz4xKb&ha}-KKJ)R^&7r(T_qvN)?nTPE>yN11_S@X( zpZ>Q(<-Gl1h5itC+xv`)yY+ij<#ZTq=sU~wTDb!5wa`}Ber+*5rzx;YO>za^^8BKkPcK_= 1) + 171 .loc 1 85 3 view .LVU43 + 172 .loc 1 85 10 is_stmt 0 view .LVU44 + 173 0000 0D4B ldr r3, .L16 + 174 0002 5B7A ldrb r3, [r3, #9] @ zero_extendqisi2 + 175 .loc 1 85 5 view .LVU45 + 176 0004 9BB1 cbz r3, .L14 + 86:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** { + 87:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** DiskNum = path[0] - '0'; + 177 .loc 1 87 5 is_stmt 1 view .LVU46 + 178 .loc 1 87 19 is_stmt 0 view .LVU47 + 179 0006 0378 ldrb r3, [r0] @ zero_extendqisi2 + 180 .loc 1 87 13 view .LVU48 + 181 0008 303B subs r3, r3, #48 + 182 000a DBB2 uxtb r3, r3 + 183 .LVL14: + 88:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** if(disk.drv[DiskNum] != 0) + 184 .loc 1 88 5 is_stmt 1 view .LVU49 + 185 .loc 1 88 16 is_stmt 0 view .LVU50 + 186 000c 0A4A ldr r2, .L16 + 187 000e 02EB8302 add r2, r2, r3, lsl #2 + 188 0012 5268 ldr r2, [r2, #4] + 189 .loc 1 88 7 view .LVU51 + 190 0014 6AB1 cbz r2, .L15 + 89:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** { + 90:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** disk.drv[DiskNum] = 0; + 191 .loc 1 90 7 is_stmt 1 view .LVU52 + 192 .loc 1 90 25 is_stmt 0 view .LVU53 + 193 0016 084A ldr r2, .L16 + 194 0018 02EB8301 add r1, r2, r3, lsl #2 + 195 .LVL15: + 196 .loc 1 90 25 view .LVU54 + 197 001c 0020 movs r0, #0 + ARM GAS /tmp/ccRuuTXi.s page 6 + + + 198 .LVL16: + 199 .loc 1 90 25 view .LVU55 + 200 001e 4860 str r0, [r1, #4] + 91:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** disk.lun[DiskNum] = 0; + 201 .loc 1 91 7 is_stmt 1 view .LVU56 + 202 .loc 1 91 25 is_stmt 0 view .LVU57 + 203 0020 1344 add r3, r3, r2 + 204 .LVL17: + 205 .loc 1 91 25 view .LVU58 + 206 0022 1872 strb r0, [r3, #8] + 92:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** disk.nbr--; + 207 .loc 1 92 7 is_stmt 1 view .LVU59 + 208 .loc 1 92 11 is_stmt 0 view .LVU60 + 209 0024 537A ldrb r3, [r2, #9] @ zero_extendqisi2 + 210 .LVL18: + 211 .loc 1 92 15 view .LVU61 + 212 0026 013B subs r3, r3, #1 + 213 0028 DBB2 uxtb r3, r3 + 214 002a 5372 strb r3, [r2, #9] + 93:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** ret = 0; + 215 .loc 1 93 7 is_stmt 1 view .LVU62 + 216 .LVL19: + 217 .loc 1 93 7 is_stmt 0 view .LVU63 + 218 002c 7047 bx lr + 219 .LVL20: + 220 .L14: + 83:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** + 221 .loc 1 83 11 view .LVU64 + 222 002e 0120 movs r0, #1 + 223 .LVL21: + 83:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** + 224 .loc 1 83 11 view .LVU65 + 225 0030 7047 bx lr + 226 .LVL22: + 227 .L15: + 83:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** + 228 .loc 1 83 11 view .LVU66 + 229 0032 0120 movs r0, #1 + 230 .LVL23: + 94:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** } + 95:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** } + 96:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** + 97:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** return ret; + 231 .loc 1 97 3 is_stmt 1 view .LVU67 + 98:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** } + 232 .loc 1 98 1 is_stmt 0 view .LVU68 + 233 0034 7047 bx lr + 234 .L17: + 235 0036 00BF .align 2 + 236 .L16: + 237 0038 00000000 .word disk + 238 .cfi_endproc + 239 .LFE1185: + 241 .section .text.FATFS_UnLinkDriver,"ax",%progbits + 242 .align 1 + 243 .global FATFS_UnLinkDriver + 244 .syntax unified + ARM GAS /tmp/ccRuuTXi.s page 7 + + + 245 .thumb + 246 .thumb_func + 248 FATFS_UnLinkDriver: + 249 .LVL24: + 250 .LFB1186: + 99:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** + 100:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** /** + 101:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** * @brief Unlinks a diskio driver and decrements the number of active linked + 102:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** * drivers. + 103:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** * @param path: pointer to the logical drive path + 104:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** * @retval Returns 0 in case of success, otherwise 1. + 105:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** */ + 106:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** uint8_t FATFS_UnLinkDriver(char *path) + 107:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** { + 251 .loc 1 107 1 is_stmt 1 view -0 + 252 .cfi_startproc + 253 @ args = 0, pretend = 0, frame = 0 + 254 @ frame_needed = 0, uses_anonymous_args = 0 + 255 .loc 1 107 1 is_stmt 0 view .LVU70 + 256 0000 08B5 push {r3, lr} + 257 .LCFI3: + 258 .cfi_def_cfa_offset 8 + 259 .cfi_offset 3, -8 + 260 .cfi_offset 14, -4 + 108:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** return FATFS_UnLinkDriverEx(path, 0); + 261 .loc 1 108 3 is_stmt 1 view .LVU71 + 262 .loc 1 108 10 is_stmt 0 view .LVU72 + 263 0002 0021 movs r1, #0 + 264 0004 FFF7FEFF bl FATFS_UnLinkDriverEx + 265 .LVL25: + 109:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** } + 266 .loc 1 109 1 view .LVU73 + 267 0008 08BD pop {r3, pc} + 268 .cfi_endproc + 269 .LFE1186: + 271 .section .text.FATFS_GetAttachedDriversNbr,"ax",%progbits + 272 .align 1 + 273 .global FATFS_GetAttachedDriversNbr + 274 .syntax unified + 275 .thumb + 276 .thumb_func + 278 FATFS_GetAttachedDriversNbr: + 279 .LFB1187: + 110:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** + 111:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** /** + 112:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** * @brief Gets number of linked drivers to the FatFs module. + 113:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** * @param None + 114:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** * @retval Number of attached drivers. + 115:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** */ + 116:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** uint8_t FATFS_GetAttachedDriversNbr(void) + 117:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** { + 280 .loc 1 117 1 is_stmt 1 view -0 + 281 .cfi_startproc + 282 @ args = 0, pretend = 0, frame = 0 + 283 @ frame_needed = 0, uses_anonymous_args = 0 + 284 @ link register save eliminated. + 118:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** return disk.nbr; + ARM GAS /tmp/ccRuuTXi.s page 8 + + + 285 .loc 1 118 3 view .LVU75 + 286 .loc 1 118 14 is_stmt 0 view .LVU76 + 287 0000 014B ldr r3, .L21 + 288 0002 587A ldrb r0, [r3, #9] @ zero_extendqisi2 + 119:Middlewares/Third_Party/FatFs/src/ff_gen_drv.c **** } + 289 .loc 1 119 1 view .LVU77 + 290 0004 7047 bx lr + 291 .L22: + 292 0006 00BF .align 2 + 293 .L21: + 294 0008 00000000 .word disk + 295 .cfi_endproc + 296 .LFE1187: + 298 .global disk + 299 .section .bss.disk,"aw",%nobits + 300 .align 2 + 303 disk: + 304 0000 00000000 .space 12 + 304 00000000 + 304 00000000 + 305 .text + 306 .Letext0: + 307 .file 2 "Middlewares/Third_Party/FatFs/src/integer.h" + 308 .file 3 "Middlewares/Third_Party/FatFs/src/diskio.h" + 309 .file 4 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 310 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h" + 311 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h" + 312 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h" + 313 .file 8 "Middlewares/Third_Party/FatFs/src/ff_gen_drv.h" + ARM GAS /tmp/ccRuuTXi.s page 9 + + +DEFINED SYMBOLS + *ABS*:00000000 ff_gen_drv.c + /tmp/ccRuuTXi.s:20 .text.FATFS_LinkDriverEx:00000000 $t + /tmp/ccRuuTXi.s:26 .text.FATFS_LinkDriverEx:00000000 FATFS_LinkDriverEx + /tmp/ccRuuTXi.s:120 .text.FATFS_LinkDriverEx:00000050 $d + /tmp/ccRuuTXi.s:303 .bss.disk:00000000 disk + /tmp/ccRuuTXi.s:125 .text.FATFS_LinkDriver:00000000 $t + /tmp/ccRuuTXi.s:131 .text.FATFS_LinkDriver:00000000 FATFS_LinkDriver + /tmp/ccRuuTXi.s:155 .text.FATFS_UnLinkDriverEx:00000000 $t + /tmp/ccRuuTXi.s:161 .text.FATFS_UnLinkDriverEx:00000000 FATFS_UnLinkDriverEx + /tmp/ccRuuTXi.s:237 .text.FATFS_UnLinkDriverEx:00000038 $d + /tmp/ccRuuTXi.s:242 .text.FATFS_UnLinkDriver:00000000 $t + /tmp/ccRuuTXi.s:248 .text.FATFS_UnLinkDriver:00000000 FATFS_UnLinkDriver + /tmp/ccRuuTXi.s:272 .text.FATFS_GetAttachedDriversNbr:00000000 $t + /tmp/ccRuuTXi.s:278 .text.FATFS_GetAttachedDriversNbr:00000000 FATFS_GetAttachedDriversNbr + /tmp/ccRuuTXi.s:294 .text.FATFS_GetAttachedDriversNbr:00000008 $d + /tmp/ccRuuTXi.s:300 .bss.disk:00000000 $d + +NO UNDEFINED SYMBOLS diff --git a/build/ff_gen_drv.o b/build/ff_gen_drv.o new file mode 100644 index 0000000000000000000000000000000000000000..e8ae7af3a2128d0afd5f0b94b3db9e50228c132b GIT binary patch literal 9024 zcmb_h3v650c|P}EKCVQHq8^rITXrbhiRIQJCE1A`zam)=TekHuMK^ApfuTssVj__O zNjb9NtVpwUNg538)}~vF&Ka5xYg!aY+n_1dtU;F!*p>}Rw`@(DwHel7%K~)SlEKE- z#rwW<|0`Y6+S&m-(7E6FALl#&dEIj^_2JReV}@ZUHyNr&tw~C~y;WQM`!w{Z?W$X~ zojQNH?GK{Q`o^rcZ>Z?0-@M-NLi#@*|Jl^rDq>v^zd_l0>+$eQ*L{QcT<#j#UjESK zRM$_wdQZ7;pmFKoj#EpC9UohI=(_br^m!w;bez=ovugW|Ywz8#pI530{GWZsTIoCV z!>=};G~asIOwQl;jLnjvVkhox8|f_1TsB~xDK8x-gJ$`*@N~O8#;J3c!LIe)ex*#^ z2cPkEVEFIR%cxe=K1@6KVVF!`a0dRSVLt)M^7#wJs`A}SRa-|Ns`#ep)v<9u%KkHW zn5MtMA_Tvy>-)Dr@>N*AW#hwi@CCmH$#))lt1ZGhfuORE|7Wx<^AYbPm;JYR`1xq~DIOLG8X0d;`QHJU zwyzt`Az%2L0DruL4tBI>@Z8cPPd=xs+~HQSmH#%B!`I;%=NjgLp47Lw0Dc>Yd(YF zv)|WL(N?=TPwSqh-_c^YxtC(1=?}FSRZ-(Hkddi{ZJ;T(5H&b!WYF3cE~%CWplTU) zoKmY!oLR?7m%L8Dr1>tby0T5jl})uYgB0yO1+8x$MSH+}6Dt3UP(;G^{su0y=2l4d zom*H&Ut4qKi^@LO^?oh-S{Ig!%047kyR|r5R`%g7Z-UL-(V!Z*Sm>(P3Fi0^%FH4+ z`Cew@a8mYB^Hr4Fmhdn-TZZ6d`0-Gx-Plc`+F+24DU57BsEiFpmX`b0EREU@-JinH zu~S>O|1~n^cEeV5ojL;9Cw|F#-~9Nk@O4W`iG z&%j|gjqSRfjqQU|5ArrWe!B+Qm~qDG>aIz4>vOPv0@>--Zr!Z_YQ6`Z)BX2p-3WAt zkx{?JxHZxivLag|X9F!p(uf8yvO85MbQDUwOr(hE@pULGaxio#bZ2P14a@O1MF{we zqoEKqj>Ui~*aOF|5Z2D^+NHrT#@lFU?1r3xA=HcpuwM3g7`rgYP1KV$(q@E0YmCiJ z9>)W4jBYS?g&oosziy-zF18yTUD~|lcZE%;+T-f3u-gaLZ!ubp!NyM?!@}JVH`cKQ zU}NMReop{q;2Xyjh=Jkjhq?2yj~L2q{KPRdvT0o+HbSD!AX*Jmh_-km6YR(Idk8b6P)4P{gz#F4#K zDD&)rnJ`dirp$W<%mi*@Z*7QmsSC29&Jb3c!rs|`OY~QP@3QH368;N^rXcHu&mfdZz6pG@KqH zT@j}nGSzO(o>|jNL-QzgP}lCeN_5snl0XJam8Y+|jdL+TrxP7G>vD$b5{HF}n~aG* zOs*Vu#MS5j#s33n%u+!te$)8RNRz_#o*RMZ!$cvMTgX3cpj27iR{B}`Tw!JKhAQ2fBQDJPESi}`YWvNb4eagj>$@}7yO>>CK9Vh!tNE4Q#r=@0 z^UI5~z&YsWmM-4jo9n-W;zB7??ZpN-GM_2upvaW7^GC2XF7D6wF1~+mDV|%3^3#R}xP<)SXH>eR6hrbeYJXNzl{8C}ugk0z5-Ni}l! zRB}Y=7}P?kcp;`A%f(9JLNT9<@vC%I$Ra?sHd0d@shiy^^XPMIwGtUPT9Z?$7B)O(;@s5%sC z84(^xR~>z&nyD^VJe?dKUYXYMPn}Yk%L&gXOTvYf=1m&}}Qk}tt@IiJa?k(ty`>g>!q%K_gZ!@~z-J^i;I)N8n$ zU+C{0*j>M%@rLK2aRUjr&nuB|lj>YOKAdxSBx3)H`Rm4PM7{VI?H(HsouP>RFl?H` zHStjTMf}+AP(L0So)h?VLD9c|w0A-Unt~GzW~1HeYsYusMyu1!{_k zHQ#|%pW3^$g`>RI-#yx$3KmAX)*jY;Yb>=_01MuXe=XJ4wp8<)2_>t}+fuD{cJIv6 zzoX9XT|KmKuCsU5$y@5=ZF=o+)_8eo#rShwFtKMX=+7P??Hrj_jQf#IW5~!NY<{!Fj=77W|~(w*|i^_+!C$1Wjyf z^0o-Z1QUYa75uT_F>HJKPYT{c#C*((TqI&^lm)Md{t;r6QjZIMoQN&(8L@vsM@-@LA>e4?X7$w4Qi^#VK zVwvdiLN$%tvmC#u;7-9F!Gxe*@9^VqcO2jIg0q5if)@oZ3qBUg6)Exg8W&Meg_2a5*!vhDX4#yhaW#y>Hi_Y`vi-E{LcpM{C%9rA2o@;EBO0@ zUl#nj;B$ideF6VJ5&3Tfe<=8t;J*m+2U7Ak3bqP%2yPYZ7UZwq^zRkqkExVT2u=&8 z1kVem1?L491Opsu9L;*4fQP3r=O;$Qy!Q~XKl+Gra2juTgI&#|Qp;9^t3?aO7(~w5#KRypMdScY+A{G!gaB ziF^+cJWC>1iR?$ba%r)enFUtM4$iwJe4$lUoZnL_K3l1%IIh5PD&zIvfjGkdXX8yK z?>WCtO|SW;y6ayE7+zf8H*^@e{Os}td?3x05WX&FW@pR!iw>KkStw<_Vy2uaUdT%y z9gmwe3x#6dWyBzdw1Z^dz!3zI#1<^mqAqJ~Cc+e*X#O_4xh@diKLj z^t%=B1vj}i_RrhyJlcI5lfZf7Yrt*y4V2wFD5@q*!Vf$OxA<>$e*YL$ig!FWxqd%| z!rSgSytod)kL|W1yY2F)QnwB{viQ%`APbUQ+kZj!@_if|hHIC6?Z_@)dmZ2B!ACzg zxqML+ynHW!ZyHYI!*y$wkN=Q&>yYCw!N;@HO|Fgi4=-O7FZ>=jk&o|eH@*Skb7Sho zXXVAZ@gwJvI=|231IGQHgIUK!zmwue9n(wjyW$k}lkGB%!Ot7t0mSF_7sb{1?uH-2 zS<;p8IDyF;a0MXSWFmToL0y60AQUm^@mZ$%qCmFk>7M!)ChH;S+~o2h>>9sE5ESoX IZgPwN4bf^%o&W#< literal 0 HcmV?d00001 diff --git a/build/main.d b/build/main.d new file mode 100644 index 0000000..48e0675 --- /dev/null +++ b/build/main.d @@ -0,0 +1,112 @@ +build/main.o: Src/main.c Inc/main.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h Inc/fatfs.h \ + Middlewares/Third_Party/FatFs/src/ff.h \ + Middlewares/Third_Party/FatFs/src/integer.h Inc/ffconf.h Inc/main.h \ + Inc/bsp_driver_sd.h Inc/fatfs_platform.h \ + Middlewares/Third_Party/FatFs/src/ff_gen_drv.h \ + Middlewares/Third_Party/FatFs/src/diskio.h \ + Middlewares/Third_Party/FatFs/src/ff.h Inc/sd_diskio.h \ + Inc/File_Handling.h Inc/fatfs.h +Inc/main.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h: +Inc/fatfs.h: +Middlewares/Third_Party/FatFs/src/ff.h: +Middlewares/Third_Party/FatFs/src/integer.h: +Inc/ffconf.h: +Inc/main.h: +Inc/bsp_driver_sd.h: +Inc/fatfs_platform.h: +Middlewares/Third_Party/FatFs/src/ff_gen_drv.h: +Middlewares/Third_Party/FatFs/src/diskio.h: +Middlewares/Third_Party/FatFs/src/ff.h: +Inc/sd_diskio.h: +Inc/File_Handling.h: +Inc/fatfs.h: diff --git a/build/main.lst b/build/main.lst new file mode 100644 index 0000000..8644ff7 --- /dev/null +++ b/build/main.lst @@ -0,0 +1,34295 @@ +ARM GAS /tmp/ccWQNJQt.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "main.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Src/main.c" + 19 .section .text.NVIC_EncodePriority,"ax",%progbits + 20 .align 1 + 21 .syntax unified + 22 .thumb + 23 .thumb_func + 25 NVIC_EncodePriority: + 26 .LVL0: + 27 .LFB113: + 28 .file 2 "Drivers/CMSIS/Include/core_cm7.h" + 1:Drivers/CMSIS/Include/core_cm7.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/core_cm7.h **** * @file core_cm7.h + 3:Drivers/CMSIS/Include/core_cm7.h **** * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + 4:Drivers/CMSIS/Include/core_cm7.h **** * @version V5.0.8 + 5:Drivers/CMSIS/Include/core_cm7.h **** * @date 04. June 2018 + 6:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/core_cm7.h **** /* + 8:Drivers/CMSIS/Include/core_cm7.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/core_cm7.h **** * + 10:Drivers/CMSIS/Include/core_cm7.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/core_cm7.h **** * + 12:Drivers/CMSIS/Include/core_cm7.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/core_cm7.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/core_cm7.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/core_cm7.h **** * + 16:Drivers/CMSIS/Include/core_cm7.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/core_cm7.h **** * + 18:Drivers/CMSIS/Include/core_cm7.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/core_cm7.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/core_cm7.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/core_cm7.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/core_cm7.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/core_cm7.h **** */ + 24:Drivers/CMSIS/Include/core_cm7.h **** + 25:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __ICCARM__ ) + 26:Drivers/CMSIS/Include/core_cm7.h **** #pragma system_include /* treat file as system include file for MISRA check */ + 27:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__clang__) + 28:Drivers/CMSIS/Include/core_cm7.h **** #pragma clang system_header /* treat file as system include file */ + 29:Drivers/CMSIS/Include/core_cm7.h **** #endif + 30:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccWQNJQt.s page 2 + + + 31:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_GENERIC + 32:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_GENERIC + 33:Drivers/CMSIS/Include/core_cm7.h **** + 34:Drivers/CMSIS/Include/core_cm7.h **** #include + 35:Drivers/CMSIS/Include/core_cm7.h **** + 36:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus + 37:Drivers/CMSIS/Include/core_cm7.h **** extern "C" { + 38:Drivers/CMSIS/Include/core_cm7.h **** #endif + 39:Drivers/CMSIS/Include/core_cm7.h **** + 40:Drivers/CMSIS/Include/core_cm7.h **** /** + 41:Drivers/CMSIS/Include/core_cm7.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + 42:Drivers/CMSIS/Include/core_cm7.h **** CMSIS violates the following MISRA-C:2004 rules: + 43:Drivers/CMSIS/Include/core_cm7.h **** + 44:Drivers/CMSIS/Include/core_cm7.h **** \li Required Rule 8.5, object/function definition in header file.
+ 45:Drivers/CMSIS/Include/core_cm7.h **** Function definitions in header files are used to allow 'inlining'. + 46:Drivers/CMSIS/Include/core_cm7.h **** + 47:Drivers/CMSIS/Include/core_cm7.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ 48:Drivers/CMSIS/Include/core_cm7.h **** Unions are used for effective representation of core registers. + 49:Drivers/CMSIS/Include/core_cm7.h **** + 50:Drivers/CMSIS/Include/core_cm7.h **** \li Advisory Rule 19.7, Function-like macro defined.
+ 51:Drivers/CMSIS/Include/core_cm7.h **** Function-like macros are used to allow more efficient code. + 52:Drivers/CMSIS/Include/core_cm7.h **** */ + 53:Drivers/CMSIS/Include/core_cm7.h **** + 54:Drivers/CMSIS/Include/core_cm7.h **** + 55:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* + 56:Drivers/CMSIS/Include/core_cm7.h **** * CMSIS definitions + 57:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ + 58:Drivers/CMSIS/Include/core_cm7.h **** /** + 59:Drivers/CMSIS/Include/core_cm7.h **** \ingroup Cortex_M7 + 60:Drivers/CMSIS/Include/core_cm7.h **** @{ + 61:Drivers/CMSIS/Include/core_cm7.h **** */ + 62:Drivers/CMSIS/Include/core_cm7.h **** + 63:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_version.h" + 64:Drivers/CMSIS/Include/core_cm7.h **** + 65:Drivers/CMSIS/Include/core_cm7.h **** /* CMSIS CM7 definitions */ + 66:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:1 + 67:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0 + 68:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + 69:Drivers/CMSIS/Include/core_cm7.h **** __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS + 70:Drivers/CMSIS/Include/core_cm7.h **** + 71:Drivers/CMSIS/Include/core_cm7.h **** #define __CORTEX_M (7U) /*!< Cortex-M Core */ + 72:Drivers/CMSIS/Include/core_cm7.h **** + 73:Drivers/CMSIS/Include/core_cm7.h **** /** __FPU_USED indicates whether an FPU is used or not. + 74:Drivers/CMSIS/Include/core_cm7.h **** For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun + 75:Drivers/CMSIS/Include/core_cm7.h **** */ + 76:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM ) + 77:Drivers/CMSIS/Include/core_cm7.h **** #if defined __TARGET_FPU_VFP + 78:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 79:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 80:Drivers/CMSIS/Include/core_cm7.h **** #else + 81:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 82:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 83:Drivers/CMSIS/Include/core_cm7.h **** #endif + 84:Drivers/CMSIS/Include/core_cm7.h **** #else + 85:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 86:Drivers/CMSIS/Include/core_cm7.h **** #endif + 87:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccWQNJQt.s page 3 + + + 88:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + 89:Drivers/CMSIS/Include/core_cm7.h **** #if defined __ARM_PCS_VFP + 90:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 91:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 92:Drivers/CMSIS/Include/core_cm7.h **** #else + 93:Drivers/CMSIS/Include/core_cm7.h **** #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN + 94:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 95:Drivers/CMSIS/Include/core_cm7.h **** #endif + 96:Drivers/CMSIS/Include/core_cm7.h **** #else + 97:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 98:Drivers/CMSIS/Include/core_cm7.h **** #endif + 99:Drivers/CMSIS/Include/core_cm7.h **** + 100:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __GNUC__ ) + 101:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__) + 102:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 103:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 104:Drivers/CMSIS/Include/core_cm7.h **** #else + 105:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 106:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 107:Drivers/CMSIS/Include/core_cm7.h **** #endif + 108:Drivers/CMSIS/Include/core_cm7.h **** #else + 109:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 110:Drivers/CMSIS/Include/core_cm7.h **** #endif + 111:Drivers/CMSIS/Include/core_cm7.h **** + 112:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __ICCARM__ ) + 113:Drivers/CMSIS/Include/core_cm7.h **** #if defined __ARMVFP__ + 114:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 115:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 116:Drivers/CMSIS/Include/core_cm7.h **** #else + 117:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 118:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 119:Drivers/CMSIS/Include/core_cm7.h **** #endif + 120:Drivers/CMSIS/Include/core_cm7.h **** #else + 121:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 122:Drivers/CMSIS/Include/core_cm7.h **** #endif + 123:Drivers/CMSIS/Include/core_cm7.h **** + 124:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TI_ARM__ ) + 125:Drivers/CMSIS/Include/core_cm7.h **** #if defined __TI_VFP_SUPPORT__ + 126:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 127:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 128:Drivers/CMSIS/Include/core_cm7.h **** #else + 129:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 130:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 131:Drivers/CMSIS/Include/core_cm7.h **** #endif + 132:Drivers/CMSIS/Include/core_cm7.h **** #else + 133:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 134:Drivers/CMSIS/Include/core_cm7.h **** #endif + 135:Drivers/CMSIS/Include/core_cm7.h **** + 136:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TASKING__ ) + 137:Drivers/CMSIS/Include/core_cm7.h **** #if defined __FPU_VFP__ + 138:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 139:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 140:Drivers/CMSIS/Include/core_cm7.h **** #else + 141:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 142:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 143:Drivers/CMSIS/Include/core_cm7.h **** #endif + 144:Drivers/CMSIS/Include/core_cm7.h **** #else + ARM GAS /tmp/ccWQNJQt.s page 4 + + + 145:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 146:Drivers/CMSIS/Include/core_cm7.h **** #endif + 147:Drivers/CMSIS/Include/core_cm7.h **** + 148:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __CSMC__ ) + 149:Drivers/CMSIS/Include/core_cm7.h **** #if ( __CSMC__ & 0x400U) + 150:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 151:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 152:Drivers/CMSIS/Include/core_cm7.h **** #else + 153:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 154:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 155:Drivers/CMSIS/Include/core_cm7.h **** #endif + 156:Drivers/CMSIS/Include/core_cm7.h **** #else + 157:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 158:Drivers/CMSIS/Include/core_cm7.h **** #endif + 159:Drivers/CMSIS/Include/core_cm7.h **** + 160:Drivers/CMSIS/Include/core_cm7.h **** #endif + 161:Drivers/CMSIS/Include/core_cm7.h **** + 162:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + 163:Drivers/CMSIS/Include/core_cm7.h **** + 164:Drivers/CMSIS/Include/core_cm7.h **** + 165:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus + 166:Drivers/CMSIS/Include/core_cm7.h **** } + 167:Drivers/CMSIS/Include/core_cm7.h **** #endif + 168:Drivers/CMSIS/Include/core_cm7.h **** + 169:Drivers/CMSIS/Include/core_cm7.h **** #endif /* __CORE_CM7_H_GENERIC */ + 170:Drivers/CMSIS/Include/core_cm7.h **** + 171:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CMSIS_GENERIC + 172:Drivers/CMSIS/Include/core_cm7.h **** + 173:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_DEPENDANT + 174:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_DEPENDANT + 175:Drivers/CMSIS/Include/core_cm7.h **** + 176:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus + 177:Drivers/CMSIS/Include/core_cm7.h **** extern "C" { + 178:Drivers/CMSIS/Include/core_cm7.h **** #endif + 179:Drivers/CMSIS/Include/core_cm7.h **** + 180:Drivers/CMSIS/Include/core_cm7.h **** /* check device defines and use defaults */ + 181:Drivers/CMSIS/Include/core_cm7.h **** #if defined __CHECK_DEVICE_DEFINES + 182:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CM7_REV + 183:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_REV 0x0000U + 184:Drivers/CMSIS/Include/core_cm7.h **** #warning "__CM7_REV not defined in device header file; using default!" + 185:Drivers/CMSIS/Include/core_cm7.h **** #endif + 186:Drivers/CMSIS/Include/core_cm7.h **** + 187:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __FPU_PRESENT + 188:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_PRESENT 0U + 189:Drivers/CMSIS/Include/core_cm7.h **** #warning "__FPU_PRESENT not defined in device header file; using default!" + 190:Drivers/CMSIS/Include/core_cm7.h **** #endif + 191:Drivers/CMSIS/Include/core_cm7.h **** + 192:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __MPU_PRESENT + 193:Drivers/CMSIS/Include/core_cm7.h **** #define __MPU_PRESENT 0U + 194:Drivers/CMSIS/Include/core_cm7.h **** #warning "__MPU_PRESENT not defined in device header file; using default!" + 195:Drivers/CMSIS/Include/core_cm7.h **** #endif + 196:Drivers/CMSIS/Include/core_cm7.h **** + 197:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __ICACHE_PRESENT + 198:Drivers/CMSIS/Include/core_cm7.h **** #define __ICACHE_PRESENT 0U + 199:Drivers/CMSIS/Include/core_cm7.h **** #warning "__ICACHE_PRESENT not defined in device header file; using default!" + 200:Drivers/CMSIS/Include/core_cm7.h **** #endif + 201:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccWQNJQt.s page 5 + + + 202:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __DCACHE_PRESENT + 203:Drivers/CMSIS/Include/core_cm7.h **** #define __DCACHE_PRESENT 0U + 204:Drivers/CMSIS/Include/core_cm7.h **** #warning "__DCACHE_PRESENT not defined in device header file; using default!" + 205:Drivers/CMSIS/Include/core_cm7.h **** #endif + 206:Drivers/CMSIS/Include/core_cm7.h **** + 207:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __DTCM_PRESENT + 208:Drivers/CMSIS/Include/core_cm7.h **** #define __DTCM_PRESENT 0U + 209:Drivers/CMSIS/Include/core_cm7.h **** #warning "__DTCM_PRESENT not defined in device header file; using default!" + 210:Drivers/CMSIS/Include/core_cm7.h **** #endif + 211:Drivers/CMSIS/Include/core_cm7.h **** + 212:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __NVIC_PRIO_BITS + 213:Drivers/CMSIS/Include/core_cm7.h **** #define __NVIC_PRIO_BITS 3U + 214:Drivers/CMSIS/Include/core_cm7.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + 215:Drivers/CMSIS/Include/core_cm7.h **** #endif + 216:Drivers/CMSIS/Include/core_cm7.h **** + 217:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __Vendor_SysTickConfig + 218:Drivers/CMSIS/Include/core_cm7.h **** #define __Vendor_SysTickConfig 0U + 219:Drivers/CMSIS/Include/core_cm7.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + 220:Drivers/CMSIS/Include/core_cm7.h **** #endif + 221:Drivers/CMSIS/Include/core_cm7.h **** #endif + 222:Drivers/CMSIS/Include/core_cm7.h **** + 223:Drivers/CMSIS/Include/core_cm7.h **** /* IO definitions (access restrictions to peripheral registers) */ + 224:Drivers/CMSIS/Include/core_cm7.h **** /** + 225:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines + 226:Drivers/CMSIS/Include/core_cm7.h **** + 227:Drivers/CMSIS/Include/core_cm7.h **** IO Type Qualifiers are used + 228:Drivers/CMSIS/Include/core_cm7.h **** \li to specify the access to peripheral variables. + 229:Drivers/CMSIS/Include/core_cm7.h **** \li for automatic generation of peripheral register debug information. + 230:Drivers/CMSIS/Include/core_cm7.h **** */ + 231:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus + 232:Drivers/CMSIS/Include/core_cm7.h **** #define __I volatile /*!< Defines 'read only' permissions */ + 233:Drivers/CMSIS/Include/core_cm7.h **** #else + 234:Drivers/CMSIS/Include/core_cm7.h **** #define __I volatile const /*!< Defines 'read only' permissions */ + 235:Drivers/CMSIS/Include/core_cm7.h **** #endif + 236:Drivers/CMSIS/Include/core_cm7.h **** #define __O volatile /*!< Defines 'write only' permissions */ + 237:Drivers/CMSIS/Include/core_cm7.h **** #define __IO volatile /*!< Defines 'read / write' permissions */ + 238:Drivers/CMSIS/Include/core_cm7.h **** + 239:Drivers/CMSIS/Include/core_cm7.h **** /* following defines should be used for structure members */ + 240:Drivers/CMSIS/Include/core_cm7.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */ + 241:Drivers/CMSIS/Include/core_cm7.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */ + 242:Drivers/CMSIS/Include/core_cm7.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */ + 243:Drivers/CMSIS/Include/core_cm7.h **** + 244:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group Cortex_M7 */ + 245:Drivers/CMSIS/Include/core_cm7.h **** + 246:Drivers/CMSIS/Include/core_cm7.h **** + 247:Drivers/CMSIS/Include/core_cm7.h **** + 248:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* + 249:Drivers/CMSIS/Include/core_cm7.h **** * Register Abstraction + 250:Drivers/CMSIS/Include/core_cm7.h **** Core Register contain: + 251:Drivers/CMSIS/Include/core_cm7.h **** - Core Register + 252:Drivers/CMSIS/Include/core_cm7.h **** - Core NVIC Register + 253:Drivers/CMSIS/Include/core_cm7.h **** - Core SCB Register + 254:Drivers/CMSIS/Include/core_cm7.h **** - Core SysTick Register + 255:Drivers/CMSIS/Include/core_cm7.h **** - Core Debug Register + 256:Drivers/CMSIS/Include/core_cm7.h **** - Core MPU Register + 257:Drivers/CMSIS/Include/core_cm7.h **** - Core FPU Register + 258:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ + ARM GAS /tmp/ccWQNJQt.s page 6 + + + 259:Drivers/CMSIS/Include/core_cm7.h **** /** + 260:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_register Defines and Type Definitions + 261:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions and defines for Cortex-M processor based devices. + 262:Drivers/CMSIS/Include/core_cm7.h **** */ + 263:Drivers/CMSIS/Include/core_cm7.h **** + 264:Drivers/CMSIS/Include/core_cm7.h **** /** + 265:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + 266:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_CORE Status and Control Registers + 267:Drivers/CMSIS/Include/core_cm7.h **** \brief Core Register type definitions. + 268:Drivers/CMSIS/Include/core_cm7.h **** @{ + 269:Drivers/CMSIS/Include/core_cm7.h **** */ + 270:Drivers/CMSIS/Include/core_cm7.h **** + 271:Drivers/CMSIS/Include/core_cm7.h **** /** + 272:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Application Program Status Register (APSR). + 273:Drivers/CMSIS/Include/core_cm7.h **** */ + 274:Drivers/CMSIS/Include/core_cm7.h **** typedef union + 275:Drivers/CMSIS/Include/core_cm7.h **** { + 276:Drivers/CMSIS/Include/core_cm7.h **** struct + 277:Drivers/CMSIS/Include/core_cm7.h **** { + 278:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + 279:Drivers/CMSIS/Include/core_cm7.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + 280:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + 281:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + 282:Drivers/CMSIS/Include/core_cm7.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + 283:Drivers/CMSIS/Include/core_cm7.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + 284:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + 285:Drivers/CMSIS/Include/core_cm7.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + 286:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ + 287:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ + 288:Drivers/CMSIS/Include/core_cm7.h **** } APSR_Type; + 289:Drivers/CMSIS/Include/core_cm7.h **** + 290:Drivers/CMSIS/Include/core_cm7.h **** /* APSR Register Definitions */ + 291:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Pos 31U /*!< APSR + 292:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR + 293:Drivers/CMSIS/Include/core_cm7.h **** + 294:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Pos 30U /*!< APSR + 295:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR + 296:Drivers/CMSIS/Include/core_cm7.h **** + 297:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Pos 29U /*!< APSR + 298:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR + 299:Drivers/CMSIS/Include/core_cm7.h **** + 300:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Pos 28U /*!< APSR + 301:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR + 302:Drivers/CMSIS/Include/core_cm7.h **** + 303:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Pos 27U /*!< APSR + 304:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR + 305:Drivers/CMSIS/Include/core_cm7.h **** + 306:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Pos 16U /*!< APSR + 307:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR + 308:Drivers/CMSIS/Include/core_cm7.h **** + 309:Drivers/CMSIS/Include/core_cm7.h **** + 310:Drivers/CMSIS/Include/core_cm7.h **** /** + 311:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Interrupt Program Status Register (IPSR). + 312:Drivers/CMSIS/Include/core_cm7.h **** */ + 313:Drivers/CMSIS/Include/core_cm7.h **** typedef union + 314:Drivers/CMSIS/Include/core_cm7.h **** { + 315:Drivers/CMSIS/Include/core_cm7.h **** struct + ARM GAS /tmp/ccWQNJQt.s page 7 + + + 316:Drivers/CMSIS/Include/core_cm7.h **** { + 317:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + 318:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + 319:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ + 320:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ + 321:Drivers/CMSIS/Include/core_cm7.h **** } IPSR_Type; + 322:Drivers/CMSIS/Include/core_cm7.h **** + 323:Drivers/CMSIS/Include/core_cm7.h **** /* IPSR Register Definitions */ + 324:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Pos 0U /*!< IPSR + 325:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR + 326:Drivers/CMSIS/Include/core_cm7.h **** + 327:Drivers/CMSIS/Include/core_cm7.h **** + 328:Drivers/CMSIS/Include/core_cm7.h **** /** + 329:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + 330:Drivers/CMSIS/Include/core_cm7.h **** */ + 331:Drivers/CMSIS/Include/core_cm7.h **** typedef union + 332:Drivers/CMSIS/Include/core_cm7.h **** { + 333:Drivers/CMSIS/Include/core_cm7.h **** struct + 334:Drivers/CMSIS/Include/core_cm7.h **** { + 335:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + 336:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + 337:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + 338:Drivers/CMSIS/Include/core_cm7.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + 339:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + 340:Drivers/CMSIS/Include/core_cm7.h **** uint32_t T:1; /*!< bit: 24 Thumb bit */ + 341:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + 342:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + 343:Drivers/CMSIS/Include/core_cm7.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + 344:Drivers/CMSIS/Include/core_cm7.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + 345:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + 346:Drivers/CMSIS/Include/core_cm7.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + 347:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ + 348:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ + 349:Drivers/CMSIS/Include/core_cm7.h **** } xPSR_Type; + 350:Drivers/CMSIS/Include/core_cm7.h **** + 351:Drivers/CMSIS/Include/core_cm7.h **** /* xPSR Register Definitions */ + 352:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Pos 31U /*!< xPSR + 353:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR + 354:Drivers/CMSIS/Include/core_cm7.h **** + 355:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Pos 30U /*!< xPSR + 356:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR + 357:Drivers/CMSIS/Include/core_cm7.h **** + 358:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Pos 29U /*!< xPSR + 359:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR + 360:Drivers/CMSIS/Include/core_cm7.h **** + 361:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Pos 28U /*!< xPSR + 362:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR + 363:Drivers/CMSIS/Include/core_cm7.h **** + 364:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Pos 27U /*!< xPSR + 365:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR + 366:Drivers/CMSIS/Include/core_cm7.h **** + 367:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR + 368:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR + 369:Drivers/CMSIS/Include/core_cm7.h **** + 370:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Pos 24U /*!< xPSR + 371:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR + 372:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccWQNJQt.s page 8 + + + 373:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Pos 16U /*!< xPSR + 374:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR + 375:Drivers/CMSIS/Include/core_cm7.h **** + 376:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR + 377:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR + 378:Drivers/CMSIS/Include/core_cm7.h **** + 379:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Pos 0U /*!< xPSR + 380:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR + 381:Drivers/CMSIS/Include/core_cm7.h **** + 382:Drivers/CMSIS/Include/core_cm7.h **** + 383:Drivers/CMSIS/Include/core_cm7.h **** /** + 384:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Control Registers (CONTROL). + 385:Drivers/CMSIS/Include/core_cm7.h **** */ + 386:Drivers/CMSIS/Include/core_cm7.h **** typedef union + 387:Drivers/CMSIS/Include/core_cm7.h **** { + 388:Drivers/CMSIS/Include/core_cm7.h **** struct + 389:Drivers/CMSIS/Include/core_cm7.h **** { + 390:Drivers/CMSIS/Include/core_cm7.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + 391:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + 392:Drivers/CMSIS/Include/core_cm7.h **** uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + 393:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + 394:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ + 395:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ + 396:Drivers/CMSIS/Include/core_cm7.h **** } CONTROL_Type; + 397:Drivers/CMSIS/Include/core_cm7.h **** + 398:Drivers/CMSIS/Include/core_cm7.h **** /* CONTROL Register Definitions */ + 399:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Pos 2U /*!< CONT + 400:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONT + 401:Drivers/CMSIS/Include/core_cm7.h **** + 402:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT + 403:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT + 404:Drivers/CMSIS/Include/core_cm7.h **** + 405:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT + 406:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT + 407:Drivers/CMSIS/Include/core_cm7.h **** + 408:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CORE */ + 409:Drivers/CMSIS/Include/core_cm7.h **** + 410:Drivers/CMSIS/Include/core_cm7.h **** + 411:Drivers/CMSIS/Include/core_cm7.h **** /** + 412:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + 413:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + 414:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the NVIC Registers + 415:Drivers/CMSIS/Include/core_cm7.h **** @{ + 416:Drivers/CMSIS/Include/core_cm7.h **** */ + 417:Drivers/CMSIS/Include/core_cm7.h **** + 418:Drivers/CMSIS/Include/core_cm7.h **** /** + 419:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + 420:Drivers/CMSIS/Include/core_cm7.h **** */ + 421:Drivers/CMSIS/Include/core_cm7.h **** typedef struct + 422:Drivers/CMSIS/Include/core_cm7.h **** { + 423:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + 424:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[24U]; + 425:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register + 426:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RSERVED1[24U]; + 427:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register * + 428:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[24U]; + 429:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register + ARM GAS /tmp/ccWQNJQt.s page 9 + + + 430:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[24U]; + 431:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + 432:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[56U]; + 433:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bi + 434:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[644U]; + 435:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regis + 436:Drivers/CMSIS/Include/core_cm7.h **** } NVIC_Type; + 437:Drivers/CMSIS/Include/core_cm7.h **** + 438:Drivers/CMSIS/Include/core_cm7.h **** /* Software Triggered Interrupt Register Definitions */ + 439:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Pos 0U /*!< STIR: I + 440:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: I + 441:Drivers/CMSIS/Include/core_cm7.h **** + 442:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_NVIC */ + 443:Drivers/CMSIS/Include/core_cm7.h **** + 444:Drivers/CMSIS/Include/core_cm7.h **** + 445:Drivers/CMSIS/Include/core_cm7.h **** /** + 446:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + 447:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SCB System Control Block (SCB) + 448:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Control Block Registers + 449:Drivers/CMSIS/Include/core_cm7.h **** @{ + 450:Drivers/CMSIS/Include/core_cm7.h **** */ + 451:Drivers/CMSIS/Include/core_cm7.h **** + 452:Drivers/CMSIS/Include/core_cm7.h **** /** + 453:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Control Block (SCB). + 454:Drivers/CMSIS/Include/core_cm7.h **** */ + 455:Drivers/CMSIS/Include/core_cm7.h **** typedef struct + 456:Drivers/CMSIS/Include/core_cm7.h **** { + 457:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + 458:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi + 459:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + 460:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset + 461:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + 462:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register * + 463:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registe + 464:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State + 465:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Regist + 466:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + 467:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + 468:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register + 469:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + 470:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register + 471:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + 472:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + 473:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + 474:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + 475:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regis + 476:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; + 477:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + 478:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + 479:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + 480:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + 481:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regis + 482:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[93U]; + 483:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Reg + 484:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[15U]; + 485:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 + 486:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 + ARM GAS /tmp/ccWQNJQt.s page 10 + + + 487:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 + 488:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[1U]; + 489:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + 490:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED6[1U]; + 491:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU + 492:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC + 493:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + 494:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + 495:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + 496:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + 497:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by + 498:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by + 499:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED7[6U]; + 500:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memo + 501:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Cont + 502:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + 503:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + 504:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + 505:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED8[1U]; + 506:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Regis + 507:Drivers/CMSIS/Include/core_cm7.h **** } SCB_Type; + 508:Drivers/CMSIS/Include/core_cm7.h **** + 509:Drivers/CMSIS/Include/core_cm7.h **** /* SCB CPUID Register Definitions */ + 510:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB + 511:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB + 512:Drivers/CMSIS/Include/core_cm7.h **** + 513:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB + 514:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB + 515:Drivers/CMSIS/Include/core_cm7.h **** + 516:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB + 517:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB + 518:Drivers/CMSIS/Include/core_cm7.h **** + 519:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB + 520:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB + 521:Drivers/CMSIS/Include/core_cm7.h **** + 522:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB + 523:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB + 524:Drivers/CMSIS/Include/core_cm7.h **** + 525:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Interrupt Control State Register Definitions */ + 526:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB + 527:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB + 528:Drivers/CMSIS/Include/core_cm7.h **** + 529:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB + 530:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB + 531:Drivers/CMSIS/Include/core_cm7.h **** + 532:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB + 533:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB + 534:Drivers/CMSIS/Include/core_cm7.h **** + 535:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB + 536:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB + 537:Drivers/CMSIS/Include/core_cm7.h **** + 538:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB + 539:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB + 540:Drivers/CMSIS/Include/core_cm7.h **** + 541:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB + 542:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB + 543:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccWQNJQt.s page 11 + + + 544:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB + 545:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB + 546:Drivers/CMSIS/Include/core_cm7.h **** + 547:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB + 548:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB + 549:Drivers/CMSIS/Include/core_cm7.h **** + 550:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB + 551:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB + 552:Drivers/CMSIS/Include/core_cm7.h **** + 553:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB + 554:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB + 555:Drivers/CMSIS/Include/core_cm7.h **** + 556:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Vector Table Offset Register Definitions */ + 557:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB + 558:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB + 559:Drivers/CMSIS/Include/core_cm7.h **** + 560:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Application Interrupt and Reset Control Register Definitions */ + 561:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB + 562:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB + 563:Drivers/CMSIS/Include/core_cm7.h **** + 564:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB + 565:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB + 566:Drivers/CMSIS/Include/core_cm7.h **** + 567:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB + 568:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB + 569:Drivers/CMSIS/Include/core_cm7.h **** + 570:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB + 571:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB + 572:Drivers/CMSIS/Include/core_cm7.h **** + 573:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB + 574:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB + 575:Drivers/CMSIS/Include/core_cm7.h **** + 576:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB + 577:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB + 578:Drivers/CMSIS/Include/core_cm7.h **** + 579:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB + 580:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB + 581:Drivers/CMSIS/Include/core_cm7.h **** + 582:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Control Register Definitions */ + 583:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB + 584:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB + 585:Drivers/CMSIS/Include/core_cm7.h **** + 586:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB + 587:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB + 588:Drivers/CMSIS/Include/core_cm7.h **** + 589:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB + 590:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB + 591:Drivers/CMSIS/Include/core_cm7.h **** + 592:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configuration Control Register Definitions */ + 593:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Pos 18U /*!< SCB + 594:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB + 595:Drivers/CMSIS/Include/core_cm7.h **** + 596:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Pos 17U /*!< SCB + 597:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB + 598:Drivers/CMSIS/Include/core_cm7.h **** + 599:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Pos 16U /*!< SCB + 600:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB + ARM GAS /tmp/ccWQNJQt.s page 12 + + + 601:Drivers/CMSIS/Include/core_cm7.h **** + 602:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB + 603:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB + 604:Drivers/CMSIS/Include/core_cm7.h **** + 605:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB + 606:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB + 607:Drivers/CMSIS/Include/core_cm7.h **** + 608:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB + 609:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB + 610:Drivers/CMSIS/Include/core_cm7.h **** + 611:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB + 612:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB + 613:Drivers/CMSIS/Include/core_cm7.h **** + 614:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB + 615:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB + 616:Drivers/CMSIS/Include/core_cm7.h **** + 617:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB + 618:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB + 619:Drivers/CMSIS/Include/core_cm7.h **** + 620:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Handler Control and State Register Definitions */ + 621:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB + 622:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB + 623:Drivers/CMSIS/Include/core_cm7.h **** + 624:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB + 625:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB + 626:Drivers/CMSIS/Include/core_cm7.h **** + 627:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB + 628:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB + 629:Drivers/CMSIS/Include/core_cm7.h **** + 630:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB + 631:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB + 632:Drivers/CMSIS/Include/core_cm7.h **** + 633:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB + 634:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB + 635:Drivers/CMSIS/Include/core_cm7.h **** + 636:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB + 637:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB + 638:Drivers/CMSIS/Include/core_cm7.h **** + 639:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB + 640:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB + 641:Drivers/CMSIS/Include/core_cm7.h **** + 642:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB + 643:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB + 644:Drivers/CMSIS/Include/core_cm7.h **** + 645:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB + 646:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB + 647:Drivers/CMSIS/Include/core_cm7.h **** + 648:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB + 649:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB + 650:Drivers/CMSIS/Include/core_cm7.h **** + 651:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB + 652:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB + 653:Drivers/CMSIS/Include/core_cm7.h **** + 654:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB + 655:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB + 656:Drivers/CMSIS/Include/core_cm7.h **** + 657:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB + ARM GAS /tmp/ccWQNJQt.s page 13 + + + 658:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB + 659:Drivers/CMSIS/Include/core_cm7.h **** + 660:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB + 661:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB + 662:Drivers/CMSIS/Include/core_cm7.h **** + 663:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configurable Fault Status Register Definitions */ + 664:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB + 665:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB + 666:Drivers/CMSIS/Include/core_cm7.h **** + 667:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB + 668:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB + 669:Drivers/CMSIS/Include/core_cm7.h **** + 670:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB + 671:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB + 672:Drivers/CMSIS/Include/core_cm7.h **** + 673:Drivers/CMSIS/Include/core_cm7.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ + 674:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB + 675:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB + 676:Drivers/CMSIS/Include/core_cm7.h **** + 677:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB + 678:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB + 679:Drivers/CMSIS/Include/core_cm7.h **** + 680:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB + 681:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB + 682:Drivers/CMSIS/Include/core_cm7.h **** + 683:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB + 684:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB + 685:Drivers/CMSIS/Include/core_cm7.h **** + 686:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB + 687:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB + 688:Drivers/CMSIS/Include/core_cm7.h **** + 689:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB + 690:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB + 691:Drivers/CMSIS/Include/core_cm7.h **** + 692:Drivers/CMSIS/Include/core_cm7.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ + 693:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB + 694:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB + 695:Drivers/CMSIS/Include/core_cm7.h **** + 696:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB + 697:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB + 698:Drivers/CMSIS/Include/core_cm7.h **** + 699:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB + 700:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB + 701:Drivers/CMSIS/Include/core_cm7.h **** + 702:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB + 703:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB + 704:Drivers/CMSIS/Include/core_cm7.h **** + 705:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB + 706:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB + 707:Drivers/CMSIS/Include/core_cm7.h **** + 708:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB + 709:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB + 710:Drivers/CMSIS/Include/core_cm7.h **** + 711:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB + 712:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB + 713:Drivers/CMSIS/Include/core_cm7.h **** + 714:Drivers/CMSIS/Include/core_cm7.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ + ARM GAS /tmp/ccWQNJQt.s page 14 + + + 715:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB + 716:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB + 717:Drivers/CMSIS/Include/core_cm7.h **** + 718:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB + 719:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB + 720:Drivers/CMSIS/Include/core_cm7.h **** + 721:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB + 722:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB + 723:Drivers/CMSIS/Include/core_cm7.h **** + 724:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB + 725:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB + 726:Drivers/CMSIS/Include/core_cm7.h **** + 727:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB + 728:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB + 729:Drivers/CMSIS/Include/core_cm7.h **** + 730:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB + 731:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB + 732:Drivers/CMSIS/Include/core_cm7.h **** + 733:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Hard Fault Status Register Definitions */ + 734:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB + 735:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB + 736:Drivers/CMSIS/Include/core_cm7.h **** + 737:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Pos 30U /*!< SCB + 738:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB + 739:Drivers/CMSIS/Include/core_cm7.h **** + 740:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB + 741:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB + 742:Drivers/CMSIS/Include/core_cm7.h **** + 743:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Debug Fault Status Register Definitions */ + 744:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB + 745:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB + 746:Drivers/CMSIS/Include/core_cm7.h **** + 747:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB + 748:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB + 749:Drivers/CMSIS/Include/core_cm7.h **** + 750:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB + 751:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB + 752:Drivers/CMSIS/Include/core_cm7.h **** + 753:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Pos 1U /*!< SCB + 754:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB + 755:Drivers/CMSIS/Include/core_cm7.h **** + 756:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Pos 0U /*!< SCB + 757:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB + 758:Drivers/CMSIS/Include/core_cm7.h **** + 759:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Level ID Register Definitions */ + 760:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB + 761:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB + 762:Drivers/CMSIS/Include/core_cm7.h **** + 763:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Pos 24U /*!< SCB + 764:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB + 765:Drivers/CMSIS/Include/core_cm7.h **** + 766:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Type Register Definitions */ + 767:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Pos 29U /*!< SCB + 768:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB + 769:Drivers/CMSIS/Include/core_cm7.h **** + 770:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Pos 24U /*!< SCB + 771:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB + ARM GAS /tmp/ccWQNJQt.s page 15 + + + 772:Drivers/CMSIS/Include/core_cm7.h **** + 773:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Pos 20U /*!< SCB + 774:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB + 775:Drivers/CMSIS/Include/core_cm7.h **** + 776:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB + 777:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB + 778:Drivers/CMSIS/Include/core_cm7.h **** + 779:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB + 780:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB + 781:Drivers/CMSIS/Include/core_cm7.h **** + 782:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size ID Register Definitions */ + 783:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Pos 31U /*!< SCB + 784:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB + 785:Drivers/CMSIS/Include/core_cm7.h **** + 786:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Pos 30U /*!< SCB + 787:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB + 788:Drivers/CMSIS/Include/core_cm7.h **** + 789:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Pos 29U /*!< SCB + 790:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB + 791:Drivers/CMSIS/Include/core_cm7.h **** + 792:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Pos 28U /*!< SCB + 793:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB + 794:Drivers/CMSIS/Include/core_cm7.h **** + 795:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB + 796:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB + 797:Drivers/CMSIS/Include/core_cm7.h **** + 798:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB + 799:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB + 800:Drivers/CMSIS/Include/core_cm7.h **** + 801:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB + 802:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB + 803:Drivers/CMSIS/Include/core_cm7.h **** + 804:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size Selection Register Definitions */ + 805:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB + 806:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB + 807:Drivers/CMSIS/Include/core_cm7.h **** + 808:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Pos 0U /*!< SCB + 809:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB + 810:Drivers/CMSIS/Include/core_cm7.h **** + 811:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Software Triggered Interrupt Register Definitions */ + 812:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Pos 0U /*!< SCB + 813:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB + 814:Drivers/CMSIS/Include/core_cm7.h **** + 815:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Invalidate by Set-way Register Definitions */ + 816:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Pos 30U /*!< SCB + 817:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB + 818:Drivers/CMSIS/Include/core_cm7.h **** + 819:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Pos 5U /*!< SCB + 820:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB + 821:Drivers/CMSIS/Include/core_cm7.h **** + 822:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean by Set-way Register Definitions */ + 823:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Pos 30U /*!< SCB + 824:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB + 825:Drivers/CMSIS/Include/core_cm7.h **** + 826:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Pos 5U /*!< SCB + 827:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB + 828:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccWQNJQt.s page 16 + + + 829:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ + 830:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Pos 30U /*!< SCB + 831:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB + 832:Drivers/CMSIS/Include/core_cm7.h **** + 833:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Pos 5U /*!< SCB + 834:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB + 835:Drivers/CMSIS/Include/core_cm7.h **** + 836:Drivers/CMSIS/Include/core_cm7.h **** /* Instruction Tightly-Coupled Memory Control Register Definitions */ + 837:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB + 838:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB + 839:Drivers/CMSIS/Include/core_cm7.h **** + 840:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB + 841:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB + 842:Drivers/CMSIS/Include/core_cm7.h **** + 843:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB + 844:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB + 845:Drivers/CMSIS/Include/core_cm7.h **** + 846:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Pos 0U /*!< SCB + 847:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB + 848:Drivers/CMSIS/Include/core_cm7.h **** + 849:Drivers/CMSIS/Include/core_cm7.h **** /* Data Tightly-Coupled Memory Control Register Definitions */ + 850:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB + 851:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB + 852:Drivers/CMSIS/Include/core_cm7.h **** + 853:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB + 854:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB + 855:Drivers/CMSIS/Include/core_cm7.h **** + 856:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB + 857:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB + 858:Drivers/CMSIS/Include/core_cm7.h **** + 859:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Pos 0U /*!< SCB + 860:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB + 861:Drivers/CMSIS/Include/core_cm7.h **** + 862:Drivers/CMSIS/Include/core_cm7.h **** /* AHBP Control Register Definitions */ + 863:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB + 864:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB + 865:Drivers/CMSIS/Include/core_cm7.h **** + 866:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Pos 0U /*!< SCB + 867:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB + 868:Drivers/CMSIS/Include/core_cm7.h **** + 869:Drivers/CMSIS/Include/core_cm7.h **** /* L1 Cache Control Register Definitions */ + 870:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB + 871:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB + 872:Drivers/CMSIS/Include/core_cm7.h **** + 873:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Pos 1U /*!< SCB + 874:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB + 875:Drivers/CMSIS/Include/core_cm7.h **** + 876:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Pos 0U /*!< SCB + 877:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB + 878:Drivers/CMSIS/Include/core_cm7.h **** + 879:Drivers/CMSIS/Include/core_cm7.h **** /* AHBS Control Register Definitions */ + 880:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB + 881:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB + 882:Drivers/CMSIS/Include/core_cm7.h **** + 883:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB + 884:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB + 885:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccWQNJQt.s page 17 + + + 886:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB + 887:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB + 888:Drivers/CMSIS/Include/core_cm7.h **** + 889:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Bus Fault Status Register Definitions */ + 890:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB + 891:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB + 892:Drivers/CMSIS/Include/core_cm7.h **** + 893:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB + 894:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB + 895:Drivers/CMSIS/Include/core_cm7.h **** + 896:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB + 897:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB + 898:Drivers/CMSIS/Include/core_cm7.h **** + 899:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB + 900:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB + 901:Drivers/CMSIS/Include/core_cm7.h **** + 902:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB + 903:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB + 904:Drivers/CMSIS/Include/core_cm7.h **** + 905:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB + 906:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB + 907:Drivers/CMSIS/Include/core_cm7.h **** + 908:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCB */ + 909:Drivers/CMSIS/Include/core_cm7.h **** + 910:Drivers/CMSIS/Include/core_cm7.h **** + 911:Drivers/CMSIS/Include/core_cm7.h **** /** + 912:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + 913:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + 914:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Control and ID Register not in the SCB + 915:Drivers/CMSIS/Include/core_cm7.h **** @{ + 916:Drivers/CMSIS/Include/core_cm7.h **** */ + 917:Drivers/CMSIS/Include/core_cm7.h **** + 918:Drivers/CMSIS/Include/core_cm7.h **** /** + 919:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Control and ID Register not in the SCB. + 920:Drivers/CMSIS/Include/core_cm7.h **** */ + 921:Drivers/CMSIS/Include/core_cm7.h **** typedef struct + 922:Drivers/CMSIS/Include/core_cm7.h **** { + 923:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; + 924:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Regist + 925:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + 926:Drivers/CMSIS/Include/core_cm7.h **** } SCnSCB_Type; + 927:Drivers/CMSIS/Include/core_cm7.h **** + 928:Drivers/CMSIS/Include/core_cm7.h **** /* Interrupt Controller Type Register Definitions */ + 929:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: I + 930:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: I + 931:Drivers/CMSIS/Include/core_cm7.h **** + 932:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Control Register Definitions */ + 933:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: + 934:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: + 935:Drivers/CMSIS/Include/core_cm7.h **** + 936:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: + 937:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: + 938:Drivers/CMSIS/Include/core_cm7.h **** + 939:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: + 940:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: + 941:Drivers/CMSIS/Include/core_cm7.h **** + 942:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: + ARM GAS /tmp/ccWQNJQt.s page 18 + + + 943:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: + 944:Drivers/CMSIS/Include/core_cm7.h **** + 945:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: + 946:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: + 947:Drivers/CMSIS/Include/core_cm7.h **** + 948:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCnotSCB */ + 949:Drivers/CMSIS/Include/core_cm7.h **** + 950:Drivers/CMSIS/Include/core_cm7.h **** + 951:Drivers/CMSIS/Include/core_cm7.h **** /** + 952:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + 953:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick) + 954:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Timer Registers. + 955:Drivers/CMSIS/Include/core_cm7.h **** @{ + 956:Drivers/CMSIS/Include/core_cm7.h **** */ + 957:Drivers/CMSIS/Include/core_cm7.h **** + 958:Drivers/CMSIS/Include/core_cm7.h **** /** + 959:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Timer (SysTick). + 960:Drivers/CMSIS/Include/core_cm7.h **** */ + 961:Drivers/CMSIS/Include/core_cm7.h **** typedef struct + 962:Drivers/CMSIS/Include/core_cm7.h **** { + 963:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis + 964:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + 965:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register * + 966:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + 967:Drivers/CMSIS/Include/core_cm7.h **** } SysTick_Type; + 968:Drivers/CMSIS/Include/core_cm7.h **** + 969:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Control / Status Register Definitions */ + 970:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT + 971:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT + 972:Drivers/CMSIS/Include/core_cm7.h **** + 973:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT + 974:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT + 975:Drivers/CMSIS/Include/core_cm7.h **** + 976:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT + 977:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT + 978:Drivers/CMSIS/Include/core_cm7.h **** + 979:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT + 980:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT + 981:Drivers/CMSIS/Include/core_cm7.h **** + 982:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Reload Register Definitions */ + 983:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT + 984:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT + 985:Drivers/CMSIS/Include/core_cm7.h **** + 986:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Current Register Definitions */ + 987:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT + 988:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT + 989:Drivers/CMSIS/Include/core_cm7.h **** + 990:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Calibration Register Definitions */ + 991:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT + 992:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT + 993:Drivers/CMSIS/Include/core_cm7.h **** + 994:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT + 995:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT + 996:Drivers/CMSIS/Include/core_cm7.h **** + 997:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT + 998:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT + 999:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccWQNJQt.s page 19 + + +1000:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SysTick */ +1001:Drivers/CMSIS/Include/core_cm7.h **** +1002:Drivers/CMSIS/Include/core_cm7.h **** +1003:Drivers/CMSIS/Include/core_cm7.h **** /** +1004:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1005:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) +1006:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Instrumentation Trace Macrocell (ITM) +1007:Drivers/CMSIS/Include/core_cm7.h **** @{ +1008:Drivers/CMSIS/Include/core_cm7.h **** */ +1009:Drivers/CMSIS/Include/core_cm7.h **** +1010:Drivers/CMSIS/Include/core_cm7.h **** /** +1011:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). +1012:Drivers/CMSIS/Include/core_cm7.h **** */ +1013:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1014:Drivers/CMSIS/Include/core_cm7.h **** { +1015:Drivers/CMSIS/Include/core_cm7.h **** __OM union +1016:Drivers/CMSIS/Include/core_cm7.h **** { +1017:Drivers/CMSIS/Include/core_cm7.h **** __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ +1018:Drivers/CMSIS/Include/core_cm7.h **** __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ +1019:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ +1020:Drivers/CMSIS/Include/core_cm7.h **** } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ +1021:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[864U]; +1022:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ +1023:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[15U]; +1024:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ +1025:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[15U]; +1026:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ +1027:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[29U]; +1028:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register * +1029:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ +1030:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Reg +1031:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[43U]; +1032:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ +1033:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ +1034:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[6U]; +1035:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Re +1036:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Re +1037:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Re +1038:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Re +1039:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Re +1040:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Re +1041:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Re +1042:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Re +1043:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Re +1044:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Re +1045:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Re +1046:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Re +1047:Drivers/CMSIS/Include/core_cm7.h **** } ITM_Type; +1048:Drivers/CMSIS/Include/core_cm7.h **** +1049:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Privilege Register Definitions */ +1050:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM +1051:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM +1052:Drivers/CMSIS/Include/core_cm7.h **** +1053:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Control Register Definitions */ +1054:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Pos 23U /*!< ITM +1055:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM +1056:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccWQNJQt.s page 20 + + +1057:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM +1058:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM +1059:Drivers/CMSIS/Include/core_cm7.h **** +1060:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM +1061:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM +1062:Drivers/CMSIS/Include/core_cm7.h **** +1063:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM +1064:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM +1065:Drivers/CMSIS/Include/core_cm7.h **** +1066:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Pos 4U /*!< ITM +1067:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM +1068:Drivers/CMSIS/Include/core_cm7.h **** +1069:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Pos 3U /*!< ITM +1070:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM +1071:Drivers/CMSIS/Include/core_cm7.h **** +1072:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM +1073:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM +1074:Drivers/CMSIS/Include/core_cm7.h **** +1075:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Pos 1U /*!< ITM +1076:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM +1077:Drivers/CMSIS/Include/core_cm7.h **** +1078:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Pos 0U /*!< ITM +1079:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM +1080:Drivers/CMSIS/Include/core_cm7.h **** +1081:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Write Register Definitions */ +1082:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM +1083:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM +1084:Drivers/CMSIS/Include/core_cm7.h **** +1085:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Read Register Definitions */ +1086:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM +1087:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM +1088:Drivers/CMSIS/Include/core_cm7.h **** +1089:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Mode Control Register Definitions */ +1090:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM +1091:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM +1092:Drivers/CMSIS/Include/core_cm7.h **** +1093:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Lock Status Register Definitions */ +1094:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM +1095:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM +1096:Drivers/CMSIS/Include/core_cm7.h **** +1097:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Pos 1U /*!< ITM +1098:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM +1099:Drivers/CMSIS/Include/core_cm7.h **** +1100:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Pos 0U /*!< ITM +1101:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM +1102:Drivers/CMSIS/Include/core_cm7.h **** +1103:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_ITM */ +1104:Drivers/CMSIS/Include/core_cm7.h **** +1105:Drivers/CMSIS/Include/core_cm7.h **** +1106:Drivers/CMSIS/Include/core_cm7.h **** /** +1107:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1108:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) +1109:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Data Watchpoint and Trace (DWT) +1110:Drivers/CMSIS/Include/core_cm7.h **** @{ +1111:Drivers/CMSIS/Include/core_cm7.h **** */ +1112:Drivers/CMSIS/Include/core_cm7.h **** +1113:Drivers/CMSIS/Include/core_cm7.h **** /** + ARM GAS /tmp/ccWQNJQt.s page 21 + + +1114:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). +1115:Drivers/CMSIS/Include/core_cm7.h **** */ +1116:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1117:Drivers/CMSIS/Include/core_cm7.h **** { +1118:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ +1119:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ +1120:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ +1121:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Registe +1122:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ +1123:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ +1124:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Registe +1125:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register +1126:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ +1127:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ +1128:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ +1129:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; +1130:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ +1131:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ +1132:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ +1133:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[1U]; +1134:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ +1135:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ +1136:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ +1137:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[1U]; +1138:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ +1139:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ +1140:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +1141:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[981U]; +1142:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ +1143:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +1144:Drivers/CMSIS/Include/core_cm7.h **** } DWT_Type; +1145:Drivers/CMSIS/Include/core_cm7.h **** +1146:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Control Register Definitions */ +1147:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTR +1148:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTR +1149:Drivers/CMSIS/Include/core_cm7.h **** +1150:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTR +1151:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTR +1152:Drivers/CMSIS/Include/core_cm7.h **** +1153:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTR +1154:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTR +1155:Drivers/CMSIS/Include/core_cm7.h **** +1156:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTR +1157:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTR +1158:Drivers/CMSIS/Include/core_cm7.h **** +1159:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTR +1160:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTR +1161:Drivers/CMSIS/Include/core_cm7.h **** +1162:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTR +1163:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTR +1164:Drivers/CMSIS/Include/core_cm7.h **** +1165:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTR +1166:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTR +1167:Drivers/CMSIS/Include/core_cm7.h **** +1168:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTR +1169:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTR +1170:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccWQNJQt.s page 22 + + +1171:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTR +1172:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTR +1173:Drivers/CMSIS/Include/core_cm7.h **** +1174:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTR +1175:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTR +1176:Drivers/CMSIS/Include/core_cm7.h **** +1177:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTR +1178:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTR +1179:Drivers/CMSIS/Include/core_cm7.h **** +1180:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTR +1181:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTR +1182:Drivers/CMSIS/Include/core_cm7.h **** +1183:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTR +1184:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTR +1185:Drivers/CMSIS/Include/core_cm7.h **** +1186:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTR +1187:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTR +1188:Drivers/CMSIS/Include/core_cm7.h **** +1189:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTR +1190:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTR +1191:Drivers/CMSIS/Include/core_cm7.h **** +1192:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTR +1193:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTR +1194:Drivers/CMSIS/Include/core_cm7.h **** +1195:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTR +1196:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTR +1197:Drivers/CMSIS/Include/core_cm7.h **** +1198:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTR +1199:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTR +1200:Drivers/CMSIS/Include/core_cm7.h **** +1201:Drivers/CMSIS/Include/core_cm7.h **** /* DWT CPI Count Register Definitions */ +1202:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPI +1203:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPI +1204:Drivers/CMSIS/Include/core_cm7.h **** +1205:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Exception Overhead Count Register Definitions */ +1206:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXC +1207:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXC +1208:Drivers/CMSIS/Include/core_cm7.h **** +1209:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Sleep Count Register Definitions */ +1210:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLE +1211:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLE +1212:Drivers/CMSIS/Include/core_cm7.h **** +1213:Drivers/CMSIS/Include/core_cm7.h **** /* DWT LSU Count Register Definitions */ +1214:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSU +1215:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSU +1216:Drivers/CMSIS/Include/core_cm7.h **** +1217:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Folded-instruction Count Register Definitions */ +1218:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOL +1219:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOL +1220:Drivers/CMSIS/Include/core_cm7.h **** +1221:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Mask Register Definitions */ +1222:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Pos 0U /*!< DWT MAS +1223:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MAS +1224:Drivers/CMSIS/Include/core_cm7.h **** +1225:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Function Register Definitions */ +1226:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUN +1227:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUN + ARM GAS /tmp/ccWQNJQt.s page 23 + + +1228:Drivers/CMSIS/Include/core_cm7.h **** +1229:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUN +1230:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUN +1231:Drivers/CMSIS/Include/core_cm7.h **** +1232:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUN +1233:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUN +1234:Drivers/CMSIS/Include/core_cm7.h **** +1235:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUN +1236:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUN +1237:Drivers/CMSIS/Include/core_cm7.h **** +1238:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUN +1239:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUN +1240:Drivers/CMSIS/Include/core_cm7.h **** +1241:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUN +1242:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUN +1243:Drivers/CMSIS/Include/core_cm7.h **** +1244:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUN +1245:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUN +1246:Drivers/CMSIS/Include/core_cm7.h **** +1247:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUN +1248:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUN +1249:Drivers/CMSIS/Include/core_cm7.h **** +1250:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUN +1251:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUN +1252:Drivers/CMSIS/Include/core_cm7.h **** +1253:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_DWT */ +1254:Drivers/CMSIS/Include/core_cm7.h **** +1255:Drivers/CMSIS/Include/core_cm7.h **** +1256:Drivers/CMSIS/Include/core_cm7.h **** /** +1257:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1258:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_TPI Trace Port Interface (TPI) +1259:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Trace Port Interface (TPI) +1260:Drivers/CMSIS/Include/core_cm7.h **** @{ +1261:Drivers/CMSIS/Include/core_cm7.h **** */ +1262:Drivers/CMSIS/Include/core_cm7.h **** +1263:Drivers/CMSIS/Include/core_cm7.h **** /** +1264:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Trace Port Interface Register (TPI). +1265:Drivers/CMSIS/Include/core_cm7.h **** */ +1266:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1267:Drivers/CMSIS/Include/core_cm7.h **** { +1268:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Reg +1269:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Regis +1270:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[2U]; +1271:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Reg +1272:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[55U]; +1273:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register * +1274:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[131U]; +1275:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regis +1276:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Regi +1277:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counte +1278:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[759U]; +1279:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ +1280:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ +1281:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ +1282:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[1U]; +1283:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ +1284:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + ARM GAS /tmp/ccWQNJQt.s page 24 + + +1285:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ +1286:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[39U]; +1287:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ +1288:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ +1289:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED7[8U]; +1290:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ +1291:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +1292:Drivers/CMSIS/Include/core_cm7.h **** } TPI_Type; +1293:Drivers/CMSIS/Include/core_cm7.h **** +1294:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */ +1295:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACP +1296:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACP +1297:Drivers/CMSIS/Include/core_cm7.h **** +1298:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Selected Pin Protocol Register Definitions */ +1299:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPP +1300:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPP +1301:Drivers/CMSIS/Include/core_cm7.h **** +1302:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Status Register Definitions */ +1303:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFS +1304:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFS +1305:Drivers/CMSIS/Include/core_cm7.h **** +1306:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFS +1307:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFS +1308:Drivers/CMSIS/Include/core_cm7.h **** +1309:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFS +1310:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFS +1311:Drivers/CMSIS/Include/core_cm7.h **** +1312:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFS +1313:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFS +1314:Drivers/CMSIS/Include/core_cm7.h **** +1315:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Control Register Definitions */ +1316:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFC +1317:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFC +1318:Drivers/CMSIS/Include/core_cm7.h **** +1319:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFC +1320:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFC +1321:Drivers/CMSIS/Include/core_cm7.h **** +1322:Drivers/CMSIS/Include/core_cm7.h **** /* TPI TRIGGER Register Definitions */ +1323:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRI +1324:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRI +1325:Drivers/CMSIS/Include/core_cm7.h **** +1326:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */ +1327:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIF +1328:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIF +1329:Drivers/CMSIS/Include/core_cm7.h **** +1330:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIF +1331:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIF +1332:Drivers/CMSIS/Include/core_cm7.h **** +1333:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIF +1334:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIF +1335:Drivers/CMSIS/Include/core_cm7.h **** +1336:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIF +1337:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIF +1338:Drivers/CMSIS/Include/core_cm7.h **** +1339:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIF +1340:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIF +1341:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccWQNJQt.s page 25 + + +1342:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIF +1343:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIF +1344:Drivers/CMSIS/Include/core_cm7.h **** +1345:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIF +1346:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIF +1347:Drivers/CMSIS/Include/core_cm7.h **** +1348:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR2 Register Definitions */ +1349:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITA +1350:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITA +1351:Drivers/CMSIS/Include/core_cm7.h **** +1352:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITA +1353:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITA +1354:Drivers/CMSIS/Include/core_cm7.h **** +1355:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */ +1356:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIF +1357:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIF +1358:Drivers/CMSIS/Include/core_cm7.h **** +1359:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIF +1360:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIF +1361:Drivers/CMSIS/Include/core_cm7.h **** +1362:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIF +1363:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIF +1364:Drivers/CMSIS/Include/core_cm7.h **** +1365:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIF +1366:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIF +1367:Drivers/CMSIS/Include/core_cm7.h **** +1368:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIF +1369:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIF +1370:Drivers/CMSIS/Include/core_cm7.h **** +1371:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIF +1372:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIF +1373:Drivers/CMSIS/Include/core_cm7.h **** +1374:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIF +1375:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIF +1376:Drivers/CMSIS/Include/core_cm7.h **** +1377:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR0 Register Definitions */ +1378:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITA +1379:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITA +1380:Drivers/CMSIS/Include/core_cm7.h **** +1381:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITA +1382:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITA +1383:Drivers/CMSIS/Include/core_cm7.h **** +1384:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration Mode Control Register Definitions */ +1385:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITC +1386:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITC +1387:Drivers/CMSIS/Include/core_cm7.h **** +1388:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVID Register Definitions */ +1389:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEV +1390:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEV +1391:Drivers/CMSIS/Include/core_cm7.h **** +1392:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEV +1393:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEV +1394:Drivers/CMSIS/Include/core_cm7.h **** +1395:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEV +1396:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEV +1397:Drivers/CMSIS/Include/core_cm7.h **** +1398:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEV + ARM GAS /tmp/ccWQNJQt.s page 26 + + +1399:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEV +1400:Drivers/CMSIS/Include/core_cm7.h **** +1401:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEV +1402:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEV +1403:Drivers/CMSIS/Include/core_cm7.h **** +1404:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEV +1405:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEV +1406:Drivers/CMSIS/Include/core_cm7.h **** +1407:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVTYPE Register Definitions */ +1408:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEV +1409:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEV +1410:Drivers/CMSIS/Include/core_cm7.h **** +1411:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEV +1412:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEV +1413:Drivers/CMSIS/Include/core_cm7.h **** +1414:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_TPI */ +1415:Drivers/CMSIS/Include/core_cm7.h **** +1416:Drivers/CMSIS/Include/core_cm7.h **** +1417:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +1418:Drivers/CMSIS/Include/core_cm7.h **** /** +1419:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1420:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU) +1421:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Memory Protection Unit (MPU) +1422:Drivers/CMSIS/Include/core_cm7.h **** @{ +1423:Drivers/CMSIS/Include/core_cm7.h **** */ +1424:Drivers/CMSIS/Include/core_cm7.h **** +1425:Drivers/CMSIS/Include/core_cm7.h **** /** +1426:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Memory Protection Unit (MPU). +1427:Drivers/CMSIS/Include/core_cm7.h **** */ +1428:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1429:Drivers/CMSIS/Include/core_cm7.h **** { +1430:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ +1431:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ +1432:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ +1433:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register +1434:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re +1435:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address +1436:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and +1437:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address +1438:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and +1439:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address +1440:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and +1441:Drivers/CMSIS/Include/core_cm7.h **** } MPU_Type; +1442:Drivers/CMSIS/Include/core_cm7.h **** +1443:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_RALIASES 4U +1444:Drivers/CMSIS/Include/core_cm7.h **** +1445:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Type Register Definitions */ +1446:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU +1447:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU +1448:Drivers/CMSIS/Include/core_cm7.h **** +1449:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU +1450:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU +1451:Drivers/CMSIS/Include/core_cm7.h **** +1452:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU +1453:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU +1454:Drivers/CMSIS/Include/core_cm7.h **** +1455:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Control Register Definitions */ + ARM GAS /tmp/ccWQNJQt.s page 27 + + +1456:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU +1457:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU +1458:Drivers/CMSIS/Include/core_cm7.h **** +1459:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU +1460:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU +1461:Drivers/CMSIS/Include/core_cm7.h **** +1462:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU +1463:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU +1464:Drivers/CMSIS/Include/core_cm7.h **** +1465:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Number Register Definitions */ +1466:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU +1467:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU +1468:Drivers/CMSIS/Include/core_cm7.h **** +1469:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Base Address Register Definitions */ +1470:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Pos 5U /*!< MPU +1471:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU +1472:Drivers/CMSIS/Include/core_cm7.h **** +1473:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU +1474:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU +1475:Drivers/CMSIS/Include/core_cm7.h **** +1476:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU +1477:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU +1478:Drivers/CMSIS/Include/core_cm7.h **** +1479:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Attribute and Size Register Definitions */ +1480:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU +1481:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU +1482:Drivers/CMSIS/Include/core_cm7.h **** +1483:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU +1484:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU +1485:Drivers/CMSIS/Include/core_cm7.h **** +1486:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU +1487:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU +1488:Drivers/CMSIS/Include/core_cm7.h **** +1489:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU +1490:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU +1491:Drivers/CMSIS/Include/core_cm7.h **** +1492:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Pos 18U /*!< MPU +1493:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU +1494:Drivers/CMSIS/Include/core_cm7.h **** +1495:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Pos 17U /*!< MPU +1496:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU +1497:Drivers/CMSIS/Include/core_cm7.h **** +1498:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Pos 16U /*!< MPU +1499:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU +1500:Drivers/CMSIS/Include/core_cm7.h **** +1501:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU +1502:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU +1503:Drivers/CMSIS/Include/core_cm7.h **** +1504:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU +1505:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU +1506:Drivers/CMSIS/Include/core_cm7.h **** +1507:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU +1508:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU +1509:Drivers/CMSIS/Include/core_cm7.h **** +1510:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_MPU */ +1511:Drivers/CMSIS/Include/core_cm7.h **** #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ +1512:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccWQNJQt.s page 28 + + +1513:Drivers/CMSIS/Include/core_cm7.h **** +1514:Drivers/CMSIS/Include/core_cm7.h **** /** +1515:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1516:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_FPU Floating Point Unit (FPU) +1517:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Floating Point Unit (FPU) +1518:Drivers/CMSIS/Include/core_cm7.h **** @{ +1519:Drivers/CMSIS/Include/core_cm7.h **** */ +1520:Drivers/CMSIS/Include/core_cm7.h **** +1521:Drivers/CMSIS/Include/core_cm7.h **** /** +1522:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Floating Point Unit (FPU). +1523:Drivers/CMSIS/Include/core_cm7.h **** */ +1524:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1525:Drivers/CMSIS/Include/core_cm7.h **** { +1526:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; +1527:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control R +1528:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address R +1529:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Co +1530:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 +1531:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 +1532:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 +1533:Drivers/CMSIS/Include/core_cm7.h **** } FPU_Type; +1534:Drivers/CMSIS/Include/core_cm7.h **** +1535:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Control Register Definitions */ +1536:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCC +1537:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCC +1538:Drivers/CMSIS/Include/core_cm7.h **** +1539:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCC +1540:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCC +1541:Drivers/CMSIS/Include/core_cm7.h **** +1542:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCC +1543:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCC +1544:Drivers/CMSIS/Include/core_cm7.h **** +1545:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCC +1546:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCC +1547:Drivers/CMSIS/Include/core_cm7.h **** +1548:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCC +1549:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCC +1550:Drivers/CMSIS/Include/core_cm7.h **** +1551:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCC +1552:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCC +1553:Drivers/CMSIS/Include/core_cm7.h **** +1554:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCC +1555:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCC +1556:Drivers/CMSIS/Include/core_cm7.h **** +1557:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Pos 1U /*!< FPCC +1558:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCC +1559:Drivers/CMSIS/Include/core_cm7.h **** +1560:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCC +1561:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCC +1562:Drivers/CMSIS/Include/core_cm7.h **** +1563:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Address Register Definitions */ +1564:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCA +1565:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCA +1566:Drivers/CMSIS/Include/core_cm7.h **** +1567:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Default Status Control Register Definitions */ +1568:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDS +1569:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDS + ARM GAS /tmp/ccWQNJQt.s page 29 + + +1570:Drivers/CMSIS/Include/core_cm7.h **** +1571:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Pos 25U /*!< FPDS +1572:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDS +1573:Drivers/CMSIS/Include/core_cm7.h **** +1574:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDS +1575:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDS +1576:Drivers/CMSIS/Include/core_cm7.h **** +1577:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDS +1578:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDS +1579:Drivers/CMSIS/Include/core_cm7.h **** +1580:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 0 Definitions */ +1581:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR +1582:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR +1583:Drivers/CMSIS/Include/core_cm7.h **** +1584:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR +1585:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR +1586:Drivers/CMSIS/Include/core_cm7.h **** +1587:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR +1588:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR +1589:Drivers/CMSIS/Include/core_cm7.h **** +1590:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR +1591:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR +1592:Drivers/CMSIS/Include/core_cm7.h **** +1593:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR +1594:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR +1595:Drivers/CMSIS/Include/core_cm7.h **** +1596:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR +1597:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR +1598:Drivers/CMSIS/Include/core_cm7.h **** +1599:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR +1600:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR +1601:Drivers/CMSIS/Include/core_cm7.h **** +1602:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR +1603:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR +1604:Drivers/CMSIS/Include/core_cm7.h **** +1605:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 1 Definitions */ +1606:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR +1607:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR +1608:Drivers/CMSIS/Include/core_cm7.h **** +1609:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR +1610:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR +1611:Drivers/CMSIS/Include/core_cm7.h **** +1612:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR +1613:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR +1614:Drivers/CMSIS/Include/core_cm7.h **** +1615:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR +1616:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR +1617:Drivers/CMSIS/Include/core_cm7.h **** +1618:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 2 Definitions */ +1619:Drivers/CMSIS/Include/core_cm7.h **** +1620:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_FPU */ +1621:Drivers/CMSIS/Include/core_cm7.h **** +1622:Drivers/CMSIS/Include/core_cm7.h **** +1623:Drivers/CMSIS/Include/core_cm7.h **** /** +1624:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1625:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) +1626:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Core Debug Registers + ARM GAS /tmp/ccWQNJQt.s page 30 + + +1627:Drivers/CMSIS/Include/core_cm7.h **** @{ +1628:Drivers/CMSIS/Include/core_cm7.h **** */ +1629:Drivers/CMSIS/Include/core_cm7.h **** +1630:Drivers/CMSIS/Include/core_cm7.h **** /** +1631:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Core Debug Register (CoreDebug). +1632:Drivers/CMSIS/Include/core_cm7.h **** */ +1633:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1634:Drivers/CMSIS/Include/core_cm7.h **** { +1635:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status +1636:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Reg +1637:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Registe +1638:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Cont +1639:Drivers/CMSIS/Include/core_cm7.h **** } CoreDebug_Type; +1640:Drivers/CMSIS/Include/core_cm7.h **** +1641:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Halting Control and Status Register Definitions */ +1642:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< Core +1643:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< Core +1644:Drivers/CMSIS/Include/core_cm7.h **** +1645:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< Core +1646:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< Core +1647:Drivers/CMSIS/Include/core_cm7.h **** +1648:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< Core +1649:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< Core +1650:Drivers/CMSIS/Include/core_cm7.h **** +1651:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< Core +1652:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< Core +1653:Drivers/CMSIS/Include/core_cm7.h **** +1654:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< Core +1655:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< Core +1656:Drivers/CMSIS/Include/core_cm7.h **** +1657:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< Core +1658:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< Core +1659:Drivers/CMSIS/Include/core_cm7.h **** +1660:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< Core +1661:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< Core +1662:Drivers/CMSIS/Include/core_cm7.h **** +1663:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< Core +1664:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< Core +1665:Drivers/CMSIS/Include/core_cm7.h **** +1666:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< Core +1667:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< Core +1668:Drivers/CMSIS/Include/core_cm7.h **** +1669:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< Core +1670:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< Core +1671:Drivers/CMSIS/Include/core_cm7.h **** +1672:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< Core +1673:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< Core +1674:Drivers/CMSIS/Include/core_cm7.h **** +1675:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< Core +1676:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< Core +1677:Drivers/CMSIS/Include/core_cm7.h **** +1678:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Core Register Selector Register Definitions */ +1679:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core +1680:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core +1681:Drivers/CMSIS/Include/core_cm7.h **** +1682:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< Core +1683:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< Core + ARM GAS /tmp/ccWQNJQt.s page 31 + + +1684:Drivers/CMSIS/Include/core_cm7.h **** +1685:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Exception and Monitor Control Register Definitions */ +1686:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< Core +1687:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< Core +1688:Drivers/CMSIS/Include/core_cm7.h **** +1689:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< Core +1690:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< Core +1691:Drivers/CMSIS/Include/core_cm7.h **** +1692:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< Core +1693:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< Core +1694:Drivers/CMSIS/Include/core_cm7.h **** +1695:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< Core +1696:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< Core +1697:Drivers/CMSIS/Include/core_cm7.h **** +1698:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< Core +1699:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< Core +1700:Drivers/CMSIS/Include/core_cm7.h **** +1701:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< Core +1702:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< Core +1703:Drivers/CMSIS/Include/core_cm7.h **** +1704:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< Core +1705:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< Core +1706:Drivers/CMSIS/Include/core_cm7.h **** +1707:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< Core +1708:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< Core +1709:Drivers/CMSIS/Include/core_cm7.h **** +1710:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< Core +1711:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< Core +1712:Drivers/CMSIS/Include/core_cm7.h **** +1713:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< Core +1714:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< Core +1715:Drivers/CMSIS/Include/core_cm7.h **** +1716:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< Core +1717:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< Core +1718:Drivers/CMSIS/Include/core_cm7.h **** +1719:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< Core +1720:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< Core +1721:Drivers/CMSIS/Include/core_cm7.h **** +1722:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< Core +1723:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< Core +1724:Drivers/CMSIS/Include/core_cm7.h **** +1725:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CoreDebug */ +1726:Drivers/CMSIS/Include/core_cm7.h **** +1727:Drivers/CMSIS/Include/core_cm7.h **** +1728:Drivers/CMSIS/Include/core_cm7.h **** /** +1729:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1730:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_bitfield Core register bit field macros +1731:Drivers/CMSIS/Include/core_cm7.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). +1732:Drivers/CMSIS/Include/core_cm7.h **** @{ +1733:Drivers/CMSIS/Include/core_cm7.h **** */ +1734:Drivers/CMSIS/Include/core_cm7.h **** +1735:Drivers/CMSIS/Include/core_cm7.h **** /** +1736:Drivers/CMSIS/Include/core_cm7.h **** \brief Mask and shift a bit field value for use in a register bit range. +1737:Drivers/CMSIS/Include/core_cm7.h **** \param[in] field Name of the register bit field. +1738:Drivers/CMSIS/Include/core_cm7.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. +1739:Drivers/CMSIS/Include/core_cm7.h **** \return Masked and shifted value. +1740:Drivers/CMSIS/Include/core_cm7.h **** */ + ARM GAS /tmp/ccWQNJQt.s page 32 + + +1741:Drivers/CMSIS/Include/core_cm7.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) +1742:Drivers/CMSIS/Include/core_cm7.h **** +1743:Drivers/CMSIS/Include/core_cm7.h **** /** +1744:Drivers/CMSIS/Include/core_cm7.h **** \brief Mask and shift a register value to extract a bit filed value. +1745:Drivers/CMSIS/Include/core_cm7.h **** \param[in] field Name of the register bit field. +1746:Drivers/CMSIS/Include/core_cm7.h **** \param[in] value Value of register. This parameter is interpreted as an uint32_t type. +1747:Drivers/CMSIS/Include/core_cm7.h **** \return Masked and shifted bit field value. +1748:Drivers/CMSIS/Include/core_cm7.h **** */ +1749:Drivers/CMSIS/Include/core_cm7.h **** #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) +1750:Drivers/CMSIS/Include/core_cm7.h **** +1751:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_core_bitfield */ +1752:Drivers/CMSIS/Include/core_cm7.h **** +1753:Drivers/CMSIS/Include/core_cm7.h **** +1754:Drivers/CMSIS/Include/core_cm7.h **** /** +1755:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1756:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_base Core Definitions +1757:Drivers/CMSIS/Include/core_cm7.h **** \brief Definitions for base addresses, unions, and structures. +1758:Drivers/CMSIS/Include/core_cm7.h **** @{ +1759:Drivers/CMSIS/Include/core_cm7.h **** */ +1760:Drivers/CMSIS/Include/core_cm7.h **** +1761:Drivers/CMSIS/Include/core_cm7.h **** /* Memory mapping of Core Hardware */ +1762:Drivers/CMSIS/Include/core_cm7.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas +1763:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +1764:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +1765:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +1766:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address +1767:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +1768:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +1769:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas +1770:Drivers/CMSIS/Include/core_cm7.h **** +1771:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register +1772:Drivers/CMSIS/Include/core_cm7.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct +1773:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st +1774:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc +1775:Drivers/CMSIS/Include/core_cm7.h **** #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct +1776:Drivers/CMSIS/Include/core_cm7.h **** #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct +1777:Drivers/CMSIS/Include/core_cm7.h **** #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct +1778:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration +1779:Drivers/CMSIS/Include/core_cm7.h **** +1780:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +1781:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit * +1782:Drivers/CMSIS/Include/core_cm7.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit * +1783:Drivers/CMSIS/Include/core_cm7.h **** #endif +1784:Drivers/CMSIS/Include/core_cm7.h **** +1785:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +1786:Drivers/CMSIS/Include/core_cm7.h **** #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +1787:Drivers/CMSIS/Include/core_cm7.h **** +1788:Drivers/CMSIS/Include/core_cm7.h **** /*@} */ +1789:Drivers/CMSIS/Include/core_cm7.h **** +1790:Drivers/CMSIS/Include/core_cm7.h **** +1791:Drivers/CMSIS/Include/core_cm7.h **** +1792:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* +1793:Drivers/CMSIS/Include/core_cm7.h **** * Hardware Abstraction Layer +1794:Drivers/CMSIS/Include/core_cm7.h **** Core Function Interface contains: +1795:Drivers/CMSIS/Include/core_cm7.h **** - Core NVIC Functions +1796:Drivers/CMSIS/Include/core_cm7.h **** - Core SysTick Functions +1797:Drivers/CMSIS/Include/core_cm7.h **** - Core Debug Functions + ARM GAS /tmp/ccWQNJQt.s page 33 + + +1798:Drivers/CMSIS/Include/core_cm7.h **** - Core Register Access Functions +1799:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ +1800:Drivers/CMSIS/Include/core_cm7.h **** /** +1801:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +1802:Drivers/CMSIS/Include/core_cm7.h **** */ +1803:Drivers/CMSIS/Include/core_cm7.h **** +1804:Drivers/CMSIS/Include/core_cm7.h **** +1805:Drivers/CMSIS/Include/core_cm7.h **** +1806:Drivers/CMSIS/Include/core_cm7.h **** /* ########################## NVIC functions #################################### */ +1807:Drivers/CMSIS/Include/core_cm7.h **** /** +1808:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_Core_FunctionInterface +1809:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions +1810:Drivers/CMSIS/Include/core_cm7.h **** \brief Functions that manage interrupts and exceptions via the NVIC. +1811:Drivers/CMSIS/Include/core_cm7.h **** @{ +1812:Drivers/CMSIS/Include/core_cm7.h **** */ +1813:Drivers/CMSIS/Include/core_cm7.h **** +1814:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_NVIC_VIRTUAL +1815:Drivers/CMSIS/Include/core_cm7.h **** #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE +1816:Drivers/CMSIS/Include/core_cm7.h **** #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" +1817:Drivers/CMSIS/Include/core_cm7.h **** #endif +1818:Drivers/CMSIS/Include/core_cm7.h **** #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +1819:Drivers/CMSIS/Include/core_cm7.h **** #else +1820:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +1821:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +1822:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_EnableIRQ __NVIC_EnableIRQ +1823:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +1824:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_DisableIRQ __NVIC_DisableIRQ +1825:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +1826:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +1827:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +1828:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetActive __NVIC_GetActive +1829:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPriority __NVIC_SetPriority +1830:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPriority __NVIC_GetPriority +1831:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SystemReset __NVIC_SystemReset +1832:Drivers/CMSIS/Include/core_cm7.h **** #endif /* CMSIS_NVIC_VIRTUAL */ +1833:Drivers/CMSIS/Include/core_cm7.h **** +1834:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_VECTAB_VIRTUAL +1835:Drivers/CMSIS/Include/core_cm7.h **** #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE +1836:Drivers/CMSIS/Include/core_cm7.h **** #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" +1837:Drivers/CMSIS/Include/core_cm7.h **** #endif +1838:Drivers/CMSIS/Include/core_cm7.h **** #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +1839:Drivers/CMSIS/Include/core_cm7.h **** #else +1840:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetVector __NVIC_SetVector +1841:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetVector __NVIC_GetVector +1842:Drivers/CMSIS/Include/core_cm7.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */ +1843:Drivers/CMSIS/Include/core_cm7.h **** +1844:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_USER_IRQ_OFFSET 16 +1845:Drivers/CMSIS/Include/core_cm7.h **** +1846:Drivers/CMSIS/Include/core_cm7.h **** +1847:Drivers/CMSIS/Include/core_cm7.h **** /* The following EXC_RETURN values are saved the LR on exception entry */ +1848:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after ret +1849:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after retu +1850:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after retu +1851:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after ret +1852:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after retu +1853:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after retu +1854:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccWQNJQt.s page 34 + + +1855:Drivers/CMSIS/Include/core_cm7.h **** +1856:Drivers/CMSIS/Include/core_cm7.h **** /** +1857:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Priority Grouping +1858:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the priority grouping field using the required unlock sequence. +1859:Drivers/CMSIS/Include/core_cm7.h **** The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. +1860:Drivers/CMSIS/Include/core_cm7.h **** Only values from 0..7 are used. +1861:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available +1862:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. +1863:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Priority grouping field. +1864:Drivers/CMSIS/Include/core_cm7.h **** */ +1865:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +1866:Drivers/CMSIS/Include/core_cm7.h **** { +1867:Drivers/CMSIS/Include/core_cm7.h **** uint32_t reg_value; +1868:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a +1869:Drivers/CMSIS/Include/core_cm7.h **** +1870:Drivers/CMSIS/Include/core_cm7.h **** reg_value = SCB->AIRCR; /* read old register +1871:Drivers/CMSIS/Include/core_cm7.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan +1872:Drivers/CMSIS/Include/core_cm7.h **** reg_value = (reg_value | +1873:Drivers/CMSIS/Include/core_cm7.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | +1874:Drivers/CMSIS/Include/core_cm7.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a +1875:Drivers/CMSIS/Include/core_cm7.h **** SCB->AIRCR = reg_value; +1876:Drivers/CMSIS/Include/core_cm7.h **** } +1877:Drivers/CMSIS/Include/core_cm7.h **** +1878:Drivers/CMSIS/Include/core_cm7.h **** +1879:Drivers/CMSIS/Include/core_cm7.h **** /** +1880:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Priority Grouping +1881:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the priority grouping field from the NVIC Interrupt Controller. +1882:Drivers/CMSIS/Include/core_cm7.h **** \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). +1883:Drivers/CMSIS/Include/core_cm7.h **** */ +1884:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +1885:Drivers/CMSIS/Include/core_cm7.h **** { +1886:Drivers/CMSIS/Include/core_cm7.h **** return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +1887:Drivers/CMSIS/Include/core_cm7.h **** } +1888:Drivers/CMSIS/Include/core_cm7.h **** +1889:Drivers/CMSIS/Include/core_cm7.h **** +1890:Drivers/CMSIS/Include/core_cm7.h **** /** +1891:Drivers/CMSIS/Include/core_cm7.h **** \brief Enable Interrupt +1892:Drivers/CMSIS/Include/core_cm7.h **** \details Enables a device specific interrupt in the NVIC interrupt controller. +1893:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1894:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1895:Drivers/CMSIS/Include/core_cm7.h **** */ +1896:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +1897:Drivers/CMSIS/Include/core_cm7.h **** { +1898:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1899:Drivers/CMSIS/Include/core_cm7.h **** { +1900:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +1901:Drivers/CMSIS/Include/core_cm7.h **** } +1902:Drivers/CMSIS/Include/core_cm7.h **** } +1903:Drivers/CMSIS/Include/core_cm7.h **** +1904:Drivers/CMSIS/Include/core_cm7.h **** +1905:Drivers/CMSIS/Include/core_cm7.h **** /** +1906:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Enable status +1907:Drivers/CMSIS/Include/core_cm7.h **** \details Returns a device specific interrupt enable status from the NVIC interrupt controller. +1908:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1909:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt is not enabled. +1910:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt is enabled. +1911:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. + ARM GAS /tmp/ccWQNJQt.s page 35 + + +1912:Drivers/CMSIS/Include/core_cm7.h **** */ +1913:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +1914:Drivers/CMSIS/Include/core_cm7.h **** { +1915:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1916:Drivers/CMSIS/Include/core_cm7.h **** { +1917:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) +1918:Drivers/CMSIS/Include/core_cm7.h **** } +1919:Drivers/CMSIS/Include/core_cm7.h **** else +1920:Drivers/CMSIS/Include/core_cm7.h **** { +1921:Drivers/CMSIS/Include/core_cm7.h **** return(0U); +1922:Drivers/CMSIS/Include/core_cm7.h **** } +1923:Drivers/CMSIS/Include/core_cm7.h **** } +1924:Drivers/CMSIS/Include/core_cm7.h **** +1925:Drivers/CMSIS/Include/core_cm7.h **** +1926:Drivers/CMSIS/Include/core_cm7.h **** /** +1927:Drivers/CMSIS/Include/core_cm7.h **** \brief Disable Interrupt +1928:Drivers/CMSIS/Include/core_cm7.h **** \details Disables a device specific interrupt in the NVIC interrupt controller. +1929:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1930:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1931:Drivers/CMSIS/Include/core_cm7.h **** */ +1932:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +1933:Drivers/CMSIS/Include/core_cm7.h **** { +1934:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1935:Drivers/CMSIS/Include/core_cm7.h **** { +1936:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +1937:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +1938:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +1939:Drivers/CMSIS/Include/core_cm7.h **** } +1940:Drivers/CMSIS/Include/core_cm7.h **** } +1941:Drivers/CMSIS/Include/core_cm7.h **** +1942:Drivers/CMSIS/Include/core_cm7.h **** +1943:Drivers/CMSIS/Include/core_cm7.h **** /** +1944:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Pending Interrupt +1945:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the NVIC pending register and returns the pending bit for the specified device spe +1946:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1947:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt status is not pending. +1948:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt status is pending. +1949:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1950:Drivers/CMSIS/Include/core_cm7.h **** */ +1951:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +1952:Drivers/CMSIS/Include/core_cm7.h **** { +1953:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1954:Drivers/CMSIS/Include/core_cm7.h **** { +1955:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) +1956:Drivers/CMSIS/Include/core_cm7.h **** } +1957:Drivers/CMSIS/Include/core_cm7.h **** else +1958:Drivers/CMSIS/Include/core_cm7.h **** { +1959:Drivers/CMSIS/Include/core_cm7.h **** return(0U); +1960:Drivers/CMSIS/Include/core_cm7.h **** } +1961:Drivers/CMSIS/Include/core_cm7.h **** } +1962:Drivers/CMSIS/Include/core_cm7.h **** +1963:Drivers/CMSIS/Include/core_cm7.h **** +1964:Drivers/CMSIS/Include/core_cm7.h **** /** +1965:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Pending Interrupt +1966:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register. +1967:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1968:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. + ARM GAS /tmp/ccWQNJQt.s page 36 + + +1969:Drivers/CMSIS/Include/core_cm7.h **** */ +1970:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +1971:Drivers/CMSIS/Include/core_cm7.h **** { +1972:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1973:Drivers/CMSIS/Include/core_cm7.h **** { +1974:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +1975:Drivers/CMSIS/Include/core_cm7.h **** } +1976:Drivers/CMSIS/Include/core_cm7.h **** } +1977:Drivers/CMSIS/Include/core_cm7.h **** +1978:Drivers/CMSIS/Include/core_cm7.h **** +1979:Drivers/CMSIS/Include/core_cm7.h **** /** +1980:Drivers/CMSIS/Include/core_cm7.h **** \brief Clear Pending Interrupt +1981:Drivers/CMSIS/Include/core_cm7.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register. +1982:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1983:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1984:Drivers/CMSIS/Include/core_cm7.h **** */ +1985:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +1986:Drivers/CMSIS/Include/core_cm7.h **** { +1987:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1988:Drivers/CMSIS/Include/core_cm7.h **** { +1989:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +1990:Drivers/CMSIS/Include/core_cm7.h **** } +1991:Drivers/CMSIS/Include/core_cm7.h **** } +1992:Drivers/CMSIS/Include/core_cm7.h **** +1993:Drivers/CMSIS/Include/core_cm7.h **** +1994:Drivers/CMSIS/Include/core_cm7.h **** /** +1995:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Active Interrupt +1996:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the active register in the NVIC and returns the active bit for the device specific +1997:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1998:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt status is not active. +1999:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt status is active. +2000:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +2001:Drivers/CMSIS/Include/core_cm7.h **** */ +2002:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +2003:Drivers/CMSIS/Include/core_cm7.h **** { +2004:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +2005:Drivers/CMSIS/Include/core_cm7.h **** { +2006:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) +2007:Drivers/CMSIS/Include/core_cm7.h **** } +2008:Drivers/CMSIS/Include/core_cm7.h **** else +2009:Drivers/CMSIS/Include/core_cm7.h **** { +2010:Drivers/CMSIS/Include/core_cm7.h **** return(0U); +2011:Drivers/CMSIS/Include/core_cm7.h **** } +2012:Drivers/CMSIS/Include/core_cm7.h **** } +2013:Drivers/CMSIS/Include/core_cm7.h **** +2014:Drivers/CMSIS/Include/core_cm7.h **** +2015:Drivers/CMSIS/Include/core_cm7.h **** /** +2016:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Interrupt Priority +2017:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the priority of a device specific interrupt or a processor exception. +2018:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, +2019:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. +2020:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number. +2021:Drivers/CMSIS/Include/core_cm7.h **** \param [in] priority Priority to set. +2022:Drivers/CMSIS/Include/core_cm7.h **** \note The priority cannot be set for every processor exception. +2023:Drivers/CMSIS/Include/core_cm7.h **** */ +2024:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +2025:Drivers/CMSIS/Include/core_cm7.h **** { + ARM GAS /tmp/ccWQNJQt.s page 37 + + +2026:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +2027:Drivers/CMSIS/Include/core_cm7.h **** { +2028:Drivers/CMSIS/Include/core_cm7.h **** NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & ( +2029:Drivers/CMSIS/Include/core_cm7.h **** } +2030:Drivers/CMSIS/Include/core_cm7.h **** else +2031:Drivers/CMSIS/Include/core_cm7.h **** { +2032:Drivers/CMSIS/Include/core_cm7.h **** SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & ( +2033:Drivers/CMSIS/Include/core_cm7.h **** } +2034:Drivers/CMSIS/Include/core_cm7.h **** } +2035:Drivers/CMSIS/Include/core_cm7.h **** +2036:Drivers/CMSIS/Include/core_cm7.h **** +2037:Drivers/CMSIS/Include/core_cm7.h **** /** +2038:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Priority +2039:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the priority of a device specific interrupt or a processor exception. +2040:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, +2041:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. +2042:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number. +2043:Drivers/CMSIS/Include/core_cm7.h **** \return Interrupt Priority. +2044:Drivers/CMSIS/Include/core_cm7.h **** Value is aligned automatically to the implemented priority bits of the microc +2045:Drivers/CMSIS/Include/core_cm7.h **** */ +2046:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +2047:Drivers/CMSIS/Include/core_cm7.h **** { +2048:Drivers/CMSIS/Include/core_cm7.h **** +2049:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +2050:Drivers/CMSIS/Include/core_cm7.h **** { +2051:Drivers/CMSIS/Include/core_cm7.h **** return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); +2052:Drivers/CMSIS/Include/core_cm7.h **** } +2053:Drivers/CMSIS/Include/core_cm7.h **** else +2054:Drivers/CMSIS/Include/core_cm7.h **** { +2055:Drivers/CMSIS/Include/core_cm7.h **** return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); +2056:Drivers/CMSIS/Include/core_cm7.h **** } +2057:Drivers/CMSIS/Include/core_cm7.h **** } +2058:Drivers/CMSIS/Include/core_cm7.h **** +2059:Drivers/CMSIS/Include/core_cm7.h **** +2060:Drivers/CMSIS/Include/core_cm7.h **** /** +2061:Drivers/CMSIS/Include/core_cm7.h **** \brief Encode Priority +2062:Drivers/CMSIS/Include/core_cm7.h **** \details Encodes the priority for an interrupt with the given priority group, +2063:Drivers/CMSIS/Include/core_cm7.h **** preemptive priority value, and subpriority value. +2064:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available +2065:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. +2066:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Used priority group. +2067:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PreemptPriority Preemptive priority value (starting from 0). +2068:Drivers/CMSIS/Include/core_cm7.h **** \param [in] SubPriority Subpriority value (starting from 0). +2069:Drivers/CMSIS/Include/core_cm7.h **** \return Encoded priority. Value can be used in the function \ref NVIC_SetP +2070:Drivers/CMSIS/Include/core_cm7.h **** */ +2071:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin +2072:Drivers/CMSIS/Include/core_cm7.h **** { + 29 .loc 2 2072 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 .loc 2 2072 1 is_stmt 0 view .LVU1 + 34 0000 00B5 push {lr} + 35 .LCFI0: + 36 .cfi_def_cfa_offset 4 + 37 .cfi_offset 14, -4 +2073:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used + ARM GAS /tmp/ccWQNJQt.s page 38 + + + 38 .loc 2 2073 3 is_stmt 1 view .LVU2 + 39 .loc 2 2073 12 is_stmt 0 view .LVU3 + 40 0002 00F00700 and r0, r0, #7 + 41 .LVL1: +2074:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PreemptPriorityBits; + 42 .loc 2 2074 3 is_stmt 1 view .LVU4 +2075:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SubPriorityBits; + 43 .loc 2 2075 3 view .LVU5 +2076:Drivers/CMSIS/Include/core_cm7.h **** +2077:Drivers/CMSIS/Include/core_cm7.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV + 44 .loc 2 2077 3 view .LVU6 + 45 .loc 2 2077 31 is_stmt 0 view .LVU7 + 46 0006 C0F1070C rsb ip, r0, #7 + 47 .loc 2 2077 23 view .LVU8 + 48 000a BCF1040F cmp ip, #4 + 49 000e 28BF it cs + 50 0010 4FF0040C movcs ip, #4 + 51 .LVL2: +2078:Drivers/CMSIS/Include/core_cm7.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint + 52 .loc 2 2078 3 is_stmt 1 view .LVU9 + 53 .loc 2 2078 44 is_stmt 0 view .LVU10 + 54 0014 031D adds r3, r0, #4 + 55 .loc 2 2078 109 view .LVU11 + 56 0016 062B cmp r3, #6 + 57 0018 0FD9 bls .L3 + 58 .loc 2 2078 109 discriminator 1 view .LVU12 + 59 001a C31E subs r3, r0, #3 + 60 .L2: + 61 .LVL3: +2079:Drivers/CMSIS/Include/core_cm7.h **** +2080:Drivers/CMSIS/Include/core_cm7.h **** return ( + 62 .loc 2 2080 3 is_stmt 1 view .LVU13 +2081:Drivers/CMSIS/Include/core_cm7.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits + 63 .loc 2 2081 30 is_stmt 0 view .LVU14 + 64 001c 4FF0FF3E mov lr, #-1 + 65 0020 0EFA0CF0 lsl r0, lr, ip + 66 .LVL4: + 67 .loc 2 2081 30 view .LVU15 + 68 0024 21EA0001 bic r1, r1, r0 + 69 .LVL5: + 70 .loc 2 2081 82 view .LVU16 + 71 0028 9940 lsls r1, r1, r3 +2082:Drivers/CMSIS/Include/core_cm7.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 72 .loc 2 2082 30 view .LVU17 + 73 002a 0EFA03FE lsl lr, lr, r3 + 74 002e 22EA0E02 bic r2, r2, lr + 75 .LVL6: +2083:Drivers/CMSIS/Include/core_cm7.h **** ); +2084:Drivers/CMSIS/Include/core_cm7.h **** } + 76 .loc 2 2084 1 view .LVU18 + 77 0032 41EA0200 orr r0, r1, r2 + 78 0036 5DF804FB ldr pc, [sp], #4 + 79 .LVL7: + 80 .L3: +2078:Drivers/CMSIS/Include/core_cm7.h **** + 81 .loc 2 2078 109 discriminator 2 view .LVU19 + 82 003a 0023 movs r3, #0 + ARM GAS /tmp/ccWQNJQt.s page 39 + + + 83 003c EEE7 b .L2 + 84 .cfi_endproc + 85 .LFE113: + 87 .section .text.MX_SDMMC1_SD_Init,"ax",%progbits + 88 .align 1 + 89 .syntax unified + 90 .thumb + 91 .thumb_func + 93 MX_SDMMC1_SD_Init: + 94 .LFB1190: + 1:Src/main.c **** /* USER CODE BEGIN Header */ + 2:Src/main.c **** /** + 3:Src/main.c **** ****************************************************************************** + 4:Src/main.c **** * @file : main.c + 5:Src/main.c **** * @brief : Main program body + 6:Src/main.c **** ****************************************************************************** + 7:Src/main.c **** * @attention + 8:Src/main.c **** * + 9:Src/main.c **** * Copyright (c) 2023 STMicroelectronics. + 10:Src/main.c **** * All rights reserved. + 11:Src/main.c **** * + 12:Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file + 13:Src/main.c **** * in the root directory of this software component. + 14:Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Src/main.c **** * + 16:Src/main.c **** ****************************************************************************** + 17:Src/main.c **** */ + 18:Src/main.c **** /* USER CODE END Header */ + 19:Src/main.c **** /* Includes ------------------------------------------------------------------*/ + 20:Src/main.c **** #include "main.h" + 21:Src/main.c **** #include "fatfs.h" + 22:Src/main.c **** + 23:Src/main.c **** /* Private includes ----------------------------------------------------------*/ + 24:Src/main.c **** /* USER CODE BEGIN Includes */ + 25:Src/main.c **** // #include "math.h" + 26:Src/main.c **** #include "File_Handling.h" + 27:Src/main.c **** #include + 28:Src/main.c **** /* USER CODE END Includes */ + 29:Src/main.c **** + 30:Src/main.c **** /* Private typedef -----------------------------------------------------------*/ + 31:Src/main.c **** /* USER CODE BEGIN PTD */ + 32:Src/main.c **** + 33:Src/main.c **** /* USER CODE END PTD */ + 34:Src/main.c **** + 35:Src/main.c **** /* Private define ------------------------------------------------------------*/ + 36:Src/main.c **** /* USER CODE BEGIN PD */ + 37:Src/main.c **** /* USER CODE END PD */ + 38:Src/main.c **** + 39:Src/main.c **** /* Private macro -------------------------------------------------------------*/ + 40:Src/main.c **** /* USER CODE BEGIN PM */ + 41:Src/main.c **** + 42:Src/main.c **** /* USER CODE END PM */ + 43:Src/main.c **** + 44:Src/main.c **** /* Private variables ---------------------------------------------------------*/ + 45:Src/main.c **** ADC_HandleTypeDef hadc1; + 46:Src/main.c **** ADC_HandleTypeDef hadc3; + 47:Src/main.c **** + ARM GAS /tmp/ccWQNJQt.s page 40 + + + 48:Src/main.c **** SD_HandleTypeDef hsd1; + 49:Src/main.c **** + 50:Src/main.c **** TIM_HandleTypeDef htim4; + 51:Src/main.c **** TIM_HandleTypeDef htim8; + 52:Src/main.c **** TIM_HandleTypeDef htim10; + 53:Src/main.c **** TIM_HandleTypeDef htim11; + 54:Src/main.c **** + 55:Src/main.c **** UART_HandleTypeDef huart8; + 56:Src/main.c **** + 57:Src/main.c **** /* USER CODE BEGIN PV */ + 58:Src/main.c **** uint32_t TO6, TO6_before, TO6_stop, TO6_uart, SD_SEEK, SD_SLIDE, temp32, TO7, TO7_before, TO7_PID, + 59:Src/main.c **** uint8_t uart_buf, CPU_state, CPU_state_old, UART_transmission_request, State_Data[2], UART_DATA[DL_ + 60:Src/main.c **** uint16_t UART_rec_incr, UART_header, CS_result, temp16, Long_Data[DL_16], COMMAND[CL_16];//, SD_mat + 61:Src/main.c **** FRESULT fresult; // result + 62:Src/main.c **** int test; + 63:Src/main.c **** unsigned long fgoto, sizeoffile;//file pointer of the file object & size of file FPGA_RECEIVE_DATA_ + 64:Src/main.c **** + 65:Src/main.c **** LDx_SetupTypeDef LD1_curr_setup, LD2_curr_setup, LD1_def_setup, LD2_def_setup; + 66:Src/main.c **** Work_SetupTypeDef Curr_setup, Def_setup; + 67:Src/main.c **** LDx_ParamTypeDef LD1_param, LD2_param; + 68:Src/main.c **** + 69:Src/main.c **** LD_Blinker_StateTypeDef LD_blinker; + 70:Src/main.c **** + 71:Src/main.c **** task_t task; + 72:Src/main.c **** + 73:Src/main.c **** + 74:Src/main.c **** + 75:Src/main.c **** /* USER CODE END PV */ + 76:Src/main.c **** + 77:Src/main.c **** /* Private function prototypes -----------------------------------------------*/ + 78:Src/main.c **** void SystemClock_Config(void); + 79:Src/main.c **** static void MX_GPIO_Init(void); + 80:Src/main.c **** static void MX_DMA_Init(void); + 81:Src/main.c **** static void MX_SPI4_Init(void); + 82:Src/main.c **** static void MX_TIM2_Init(void); + 83:Src/main.c **** static void MX_TIM5_Init(void); + 84:Src/main.c **** static void MX_ADC1_Init(void); + 85:Src/main.c **** static void MX_ADC3_Init(void); + 86:Src/main.c **** static void MX_SPI2_Init(void); + 87:Src/main.c **** static void MX_SPI5_Init(void); + 88:Src/main.c **** static void MX_SPI6_Init(void); + 89:Src/main.c **** static void MX_USART1_UART_Init(void); + 90:Src/main.c **** static void MX_SDMMC1_SD_Init(void); + 91:Src/main.c **** static void MX_TIM7_Init(void); + 92:Src/main.c **** static void MX_TIM6_Init(void); + 93:Src/main.c **** static void MX_TIM10_Init(void); + 94:Src/main.c **** static void MX_UART8_Init(void); + 95:Src/main.c **** static void MX_TIM8_Init(void); + 96:Src/main.c **** static void MX_TIM11_Init(void); + 97:Src/main.c **** static void MX_TIM4_Init(void); + 98:Src/main.c **** /* USER CODE BEGIN PFP */ + 99:Src/main.c **** static void Init_params(void); + 100:Src/main.c **** static void Decode_uart(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ + 101:Src/main.c **** static void Decode_task(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ + 102:Src/main.c **** void Set_LTEC(uint8_t num, uint16_t DATA); + 103:Src/main.c **** static uint16_t MPhD_T(uint8_t num); + 104:Src/main.c **** static uint16_t Get_ADC(uint8_t num); + ARM GAS /tmp/ccWQNJQt.s page 41 + + + 105:Src/main.c **** static uint16_t PID_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_resul + 106:Src/main.c **** uint8_t CheckChecksum(uint16_t *pbuff); + 107:Src/main.c **** uint16_t CalculateChecksum(uint16_t *pbuff, uint16_t len); + 108:Src/main.c **** //int SD_Init(void); + 109:Src/main.c **** int SD_SAVE(uint16_t *pbuff); + 110:Src/main.c **** //uint32_t Get_Length(void); + 111:Src/main.c **** int SD_READ(uint16_t *pbuff); + 112:Src/main.c **** int SD_REMOVE(void); + 113:Src/main.c **** void USART_TX (uint8_t* dt, uint16_t sz); + 114:Src/main.c **** void USART_TX_DMA (uint16_t sz); + 115:Src/main.c **** static void Stop_TIM10(); + 116:Src/main.c **** static void OUT_trigger(uint8_t); + 117:Src/main.c **** /* USER CODE END PFP */ + 118:Src/main.c **** + 119:Src/main.c **** /* Private user code ---------------------------------------------------------*/ + 120:Src/main.c **** /* USER CODE BEGIN 0 */ + 121:Src/main.c **** + 122:Src/main.c **** /* USER CODE END 0 */ + 123:Src/main.c **** + 124:Src/main.c **** /** + 125:Src/main.c **** * @brief The application entry point. + 126:Src/main.c **** * @retval int + 127:Src/main.c **** */ + 128:Src/main.c **** int main(void) + 129:Src/main.c **** { + 130:Src/main.c **** + 131:Src/main.c **** /* USER CODE BEGIN 1 */ + 132:Src/main.c **** HAL_StatusTypeDef st; + 133:Src/main.c **** /* USER CODE END 1 */ + 134:Src/main.c **** + 135:Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ + 136:Src/main.c **** + 137:Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + 138:Src/main.c **** HAL_Init(); + 139:Src/main.c **** + 140:Src/main.c **** /* USER CODE BEGIN Init */ + 141:Src/main.c **** /*I hope you don't forget that first - MX_DMA_Init(); and than - MX_USART1_UART_Init();*/ + 142:Src/main.c **** /* USER CODE END Init */ + 143:Src/main.c **** + 144:Src/main.c **** /* Configure the system clock */ + 145:Src/main.c **** SystemClock_Config(); + 146:Src/main.c **** + 147:Src/main.c **** /* USER CODE BEGIN SysInit */ + 148:Src/main.c **** + 149:Src/main.c **** /* USER CODE END SysInit */ + 150:Src/main.c **** + 151:Src/main.c **** /* Initialize all configured peripherals */ + 152:Src/main.c **** MX_GPIO_Init(); + 153:Src/main.c **** MX_DMA_Init(); + 154:Src/main.c **** MX_SPI4_Init(); + 155:Src/main.c **** MX_FATFS_Init(); + 156:Src/main.c **** MX_TIM2_Init(); + 157:Src/main.c **** MX_TIM5_Init(); + 158:Src/main.c **** MX_ADC1_Init(); + 159:Src/main.c **** MX_ADC3_Init(); + 160:Src/main.c **** MX_SPI2_Init(); + 161:Src/main.c **** MX_SPI5_Init(); + ARM GAS /tmp/ccWQNJQt.s page 42 + + + 162:Src/main.c **** MX_SPI6_Init(); + 163:Src/main.c **** MX_USART1_UART_Init(); + 164:Src/main.c **** MX_SDMMC1_SD_Init(); + 165:Src/main.c **** MX_TIM7_Init(); + 166:Src/main.c **** MX_TIM6_Init(); + 167:Src/main.c **** MX_TIM10_Init(); + 168:Src/main.c **** MX_UART8_Init(); + 169:Src/main.c **** MX_TIM8_Init(); + 170:Src/main.c **** MX_TIM11_Init(); + 171:Src/main.c **** MX_TIM4_Init(); + 172:Src/main.c **** /* USER CODE BEGIN 2 */ + 173:Src/main.c **** Init_params(); + 174:Src/main.c **** //HAL_TIM_Base_Start(&htim11); + 175:Src/main.c **** //HAL_TIM_PWM_Start(&htim11, TIM_CHANNEL_1); //start modulating by Mach-Zander modulator + 176:Src/main.c **** + 177:Src/main.c **** + 178:Src/main.c **** //TIM4,11 clocks = 92 MHz + 179:Src/main.c **** + 180:Src/main.c **** //ADC clock + 181:Src/main.c **** //TIM4 -> ARR = 60; // for 1.5 MHz + 182:Src/main.c **** //TIM4 -> ARR = 91; // for 1 MHz + 183:Src/main.c **** //TIM4 -> ARR = 45; // for 2 MHz + 184:Src/main.c **** TIM4 -> ARR = 53; // for 1.735 MHz. It`s the highest frequency for correct ADC work. At higher fre + 185:Src/main.c **** + 186:Src/main.c **** TIM4 -> CCR3 = (TIM4 -> ARR +1)/2 - 1; + 187:Src/main.c **** + 188:Src/main.c **** + 189:Src/main.c **** //Mach-Zander clock (should be half of ADC clock freq) + 190:Src/main.c **** TIM11 -> ARR = (TIM4 -> ARR +1)*2 - 1; + 191:Src/main.c **** TIM11 -> CCR1 = (TIM11 -> ARR +1)/2 - 1; + 192:Src/main.c **** + 193:Src/main.c **** /* + 194:Src/main.c **** if (HAL_GPIO_ReadPin(INP_0_GPIO_Port, INP_0_Pin) == 0){ + 195:Src/main.c **** + 196:Src/main.c **** CPU_state = DECODE_ENABLE; + 197:Src/main.c **** } + 198:Src/main.c **** */ + 199:Src/main.c **** /* USER CODE END 2 */ + 200:Src/main.c **** + 201:Src/main.c **** /* Infinite loop */ + 202:Src/main.c **** /* USER CODE BEGIN WHILE */ + 203:Src/main.c **** while (1) + 204:Src/main.c **** { + 205:Src/main.c **** if ((HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin)==GPIO_PIN_SET)&&(u_rx_flg == 0)) + 206:Src/main.c **** { + 207:Src/main.c **** //NVIC_DisableIRQ(USART1_IRQn); + 208:Src/main.c **** LL_USART_EnableIT_PE(USART1); + 209:Src/main.c **** LL_USART_EnableIT_RXNE(USART1); + 210:Src/main.c **** LL_USART_EnableIT_ERROR(USART1); + 211:Src/main.c **** NVIC_SetPriority(USART1_IRQn, 0); + 212:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn);//In other case you have FE error flag... + 213:Src/main.c **** u_rx_flg = 1; + 214:Src/main.c **** } + 215:Src/main.c **** // else + 216:Src/main.c **** // { + 217:Src/main.c **** // //NVIC_DisableIRQ(USART1_IRQn); + 218:Src/main.c **** // u_rx_flg = 0; + ARM GAS /tmp/ccWQNJQt.s page 43 + + + 219:Src/main.c **** // } + 220:Src/main.c **** switch (CPU_state) + 221:Src/main.c **** { + 222:Src/main.c **** case HALT://0 - Default state + 223:Src/main.c **** CPU_state_old = HALT;//Save main current cycle + 224:Src/main.c **** task.current_param = task.min_param; + 225:Src/main.c **** Stop_TIM10(); + 226:Src/main.c **** break; + 227:Src/main.c **** case DECODE_ENABLE://1 - Decode rec. message + 228:Src/main.c **** CS_result = CalculateChecksum(COMMAND, CL_16-2); + 229:Src/main.c **** if (CheckChecksum(COMMAND)) + 230:Src/main.c **** { + 231:Src/main.c **** LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC & TEC1 + 232:Src/main.c **** LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC & TEC2 + 233:Src/main.c **** Decode_uart(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup); + 234:Src/main.c **** TO6_before = TO6; + 235:Src/main.c **** //LD1_param.LD_TEMP_Before = LD1_param.LD_TEMP; + 236:Src/main.c **** //LD2_param.LD_TEMP_Before = LD2_param.LD_TEMP; + 237:Src/main.c **** CPU_state = WORK_ENABLE; + 238:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle + 239:Src/main.c **** } + 240:Src/main.c **** else + 241:Src/main.c **** { + 242:Src/main.c **** State_Data[0] |= UART_DECODE_ERR; + 243:Src/main.c **** CPU_state = DEFAULT_ENABLE; + 244:Src/main.c **** CPU_state_old = HALT;//Save main current cycle + 245:Src/main.c **** } + 246:Src/main.c **** UART_transmission_request = MESS_01; + 247:Src/main.c **** break; + 248:Src/main.c **** case DEFAULT_ENABLE://2 - Go to HALT + 249:Src/main.c **** //Set current setup to default + 250:Src/main.c **** task.current_param = task.min_param; + 251:Src/main.c **** Stop_TIM10(); + 252:Src/main.c **** Init_params(); + 253:Src/main.c **** LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC & TEC1 + 254:Src/main.c **** LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC & TEC2 + 255:Src/main.c **** CPU_state = HALT; + 256:Src/main.c **** CPU_state_old = HALT;//Save main current cycle + 257:Src/main.c **** UART_transmission_request = MESS_01; + 258:Src/main.c **** break; + 259:Src/main.c **** case TRANS_S_ENABLE://3 - Transmith saved packet Before this operation must to be defaulting! + 260:Src/main.c **** temp16 = SD_READ(&Long_Data[0]); + 261:Src/main.c **** State_Data[0]|=temp16&0xff; + 262:Src/main.c **** if (temp16==0) + 263:Src/main.c **** { + 264:Src/main.c **** UART_transmission_request = MESS_03; + 265:Src/main.c **** } + 266:Src/main.c **** else + 267:Src/main.c **** { + 268:Src/main.c **** UART_transmission_request = MESS_01; + 269:Src/main.c **** } + 270:Src/main.c **** CPU_state_old = HALT; + 271:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle + 272:Src/main.c **** break; + 273:Src/main.c **** case TRANS_ENABLE://4 - Transmith current packet + 274:Src/main.c **** UART_transmission_request = MESS_02; + 275:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle + ARM GAS /tmp/ccWQNJQt.s page 44 + + + 276:Src/main.c **** break; + 277:Src/main.c **** case REMOVE_FILE://5 - Remove file from SD + 278:Src/main.c **** State_Data[0]|=SD_REMOVE()&0xff; + 279:Src/main.c **** UART_transmission_request = MESS_01; + 280:Src/main.c **** CPU_state = CPU_state_old; + 281:Src/main.c **** break; + 282:Src/main.c **** case STATE://6 - Transmith state message + 283:Src/main.c **** UART_transmission_request = MESS_01; + 284:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle + 285:Src/main.c **** break; + 286:Src/main.c **** case WORK_ENABLE://7 - Main work cycle + 287:Src/main.c **** task.current_param = task.min_param; + 288:Src/main.c **** Stop_TIM10(); + 289:Src/main.c **** if (TO7>TO7_before)//Main work cycle go with the timer 7 (1000 us or 1 kHz) + 290:Src/main.c **** { + 291:Src/main.c **** TO7_before = TO7; + 292:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 + 293:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 + 294:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 + 295:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 + 296:Src/main.c **** + 297:Src/main.c **** //Correct temperature in all pulses + 298:Src/main.c **** (void) MPhD_T(3); + 299:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(3); + 300:Src/main.c **** (void) MPhD_T(4); + 301:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(4); + 302:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); + 303:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 + 304:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); + 305:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 + 306:Src/main.c **** + 307:Src/main.c **** Long_Data[1] = LD1_param.POWER;//Translate Data from monitor photodiode of LD1 to Long_Data + 308:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data + 309:Src/main.c **** + 310:Src/main.c **** Set_LTEC(1,LD1_curr_setup.CURRENT);//Drive Laser diode 1 + 311:Src/main.c **** Set_LTEC(2,LD2_curr_setup.CURRENT);//Drive Laser diode 2 + 312:Src/main.c **** + 313:Src/main.c **** //Prepare DATA of internals ADCs + 314:Src/main.c **** //Put the temperature of LD2 to Long_Data: + 315:Src/main.c **** temp16 = Get_ADC(0); + 316:Src/main.c **** temp16 = Get_ADC(1); + 317:Src/main.c **** Long_Data[7] = temp16; // PA2 -- 3V_monitor // PB1 -- U_Rt1_ext_Gain + 318:Src/main.c **** + 319:Src/main.c **** //Put the temperature of LD2 to Long_Data: + 320:Src/main.c **** temp16 = Get_ADC(1); + 321:Src/main.c **** Long_Data[8] = temp16; // PB0 -- U_Rt2_ext_Gain // PB0 -- U_Rt2_ext_Gain + 322:Src/main.c **** + 323:Src/main.c **** //Put the temperature of LD2 to Long_Data: + 324:Src/main.c **** temp16 = Get_ADC(1); + 325:Src/main.c **** Long_Data[9] = temp16; // PB1 -- U_Rt1_ext_Gain // PA2 -- 3V_monitor + 326:Src/main.c **** + 327:Src/main.c **** //Put the temperature of LD2 to Long_Data: + 328:Src/main.c **** temp16 = Get_ADC(1); + 329:Src/main.c **** Long_Data[10] = temp16; // PC0 -- 5V1_monitor // PC0 -- 5V1_monitor + 330:Src/main.c **** + 331:Src/main.c **** //Put the temperature of LD2 to Long_Data: + 332:Src/main.c **** temp16 = Get_ADC(1); + ARM GAS /tmp/ccWQNJQt.s page 45 + + + 333:Src/main.c **** Long_Data[11] = temp16; // PC1 -- 5V2_monitor // PC1 -- 5V2_monitor + 334:Src/main.c **** temp16 = Get_ADC(2); + 335:Src/main.c **** + 336:Src/main.c **** //Put the temperature of LD2 to Long_Data: + 337:Src/main.c **** temp16 = Get_ADC(3); + 338:Src/main.c **** temp16 = Get_ADC(4); + 339:Src/main.c **** Long_Data[12] = temp16; + 340:Src/main.c **** temp16 = Get_ADC(5); + 341:Src/main.c **** + 342:Src/main.c **** //Put the timer tick to Long_Data: + 343:Src/main.c **** TO6_stop = TO6; + 344:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; + 345:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; + 346:Src/main.c **** + 347:Src/main.c **** //Put the average temperature of LD1 to Long_Data: + 348:Src/main.c **** Long_Data[5] = LD1_param.LD_CURR_TEMP; + 349:Src/main.c **** + 350:Src/main.c **** //Put the average temperature of LD2 to Long_Data: + 351:Src/main.c **** Long_Data[6] = LD2_param.LD_CURR_TEMP; + 352:Src/main.c **** + 353:Src/main.c **** if (Curr_setup.SD_EN==1) + 354:Src/main.c **** { + 355:Src/main.c **** CS_result = CalculateChecksum(&Long_Data[1], DL_16-2); + 356:Src/main.c **** Long_Data[DL_16-1] = CS_result; + 357:Src/main.c **** temp16 = SD_SAVE(&Long_Data[0]); + 358:Src/main.c **** State_Data[0]|=temp16&0xff; + 359:Src/main.c **** } + 360:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle + 361:Src/main.c **** } + 362:Src/main.c **** break; + 363:Src/main.c **** case DECODE_TASK: + 364:Src/main.c **** if (CheckChecksum(COMMAND)) + 365:Src/main.c **** { + 366:Src/main.c **** Decode_task(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup); + 367:Src/main.c **** TO6_before = TO6; + 368:Src/main.c **** CPU_state = RUN_TASK; + 369:Src/main.c **** CPU_state_old = RUN_TASK;//Save main current cycle + 370:Src/main.c **** } + 371:Src/main.c **** else + 372:Src/main.c **** { + 373:Src/main.c **** State_Data[0] |= UART_DECODE_ERR; + 374:Src/main.c **** CPU_state = DEFAULT_ENABLE; + 375:Src/main.c **** CPU_state_old = HALT;//Save main current cycle + 376:Src/main.c **** } + 377:Src/main.c **** UART_transmission_request = MESS_01; + 378:Src/main.c **** break; + 379:Src/main.c **** case RUN_TASK: + 380:Src/main.c **** switch (task.task_type) + 381:Src/main.c **** { + 382:Src/main.c **** case TT_CHANGE_CURR_1: + 383:Src/main.c **** + 384:Src/main.c **** + 385:Src/main.c **** //calculating timer periods for ADC clock and Mach-Zander modulator + 386:Src/main.c **** //ADC clock + 387:Src/main.c **** //TIM4 -> ARR = 60; // for 1.5 MHz + 388:Src/main.c **** //TIM4 -> ARR = 91; // for 1 MHz + 389:Src/main.c **** //TIM4 -> ARR = 45; // for 2 MHz + ARM GAS /tmp/ccWQNJQt.s page 46 + + + 390:Src/main.c **** + 391:Src/main.c **** //online calculation for debug purposes: + 392:Src/main.c **** //manually varying TIM4 -> ARR by debugger while running + 393:Src/main.c **** //TIM4 -> CCR3 = (TIM4 -> ARR +1)/2 - 1; + 394:Src/main.c **** + 395:Src/main.c **** + 396:Src/main.c **** //Mach-Zander clock (should be half of ADC clock freq) + 397:Src/main.c **** //TIM11 -> ARR = (TIM4 -> ARR +1)*2 - 1; + 398:Src/main.c **** //TIM11 -> CCR1 = (TIM11 -> ARR +1)/2 - 1; + 399:Src/main.c **** + 400:Src/main.c **** + 401:Src/main.c **** + 402:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.curr); + 403:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); + 404:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); + 405:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); + 406:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); + 407:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); + 408:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 + 409:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); + 410:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 + 411:Src/main.c **** + 412:Src/main.c **** // Toggle pin for oscilloscope + 413:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); //start of the whole frequency sweep proc + 414:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); + 415:Src/main.c **** + 416:Src/main.c **** st = HAL_TIM_Base_Start_IT(&htim10); + 417:Src/main.c **** if (st != HAL_OK) + 418:Src/main.c **** while(1); + 419:Src/main.c **** + 420:Src/main.c **** uint16_t step_counter = 0; + 421:Src/main.c **** uint16_t trigger_counter = 0; + 422:Src/main.c **** uint16_t trigger_step = (uint8_t )((task.max_param - task.current_param)/task.delta_param * 1 + 423:Src/main.c **** uint16_t task_sheduler = 0; + 424:Src/main.c **** + 425:Src/main.c **** + 426:Src/main.c **** + 427:Src/main.c **** HAL_TIM_PWM_Stop(&htim11, TIM_CHANNEL_1); //start modulating by Mach-Zander modulator + 428:Src/main.c **** HAL_TIM_PWM_Stop(&htim4, TIM_CHANNEL_3); //start ADC clock + 429:Src/main.c **** TIM11 -> CR1 &= ~(1 << 3); //disables one-pulse mode + 430:Src/main.c **** TIM4 -> CR1 &= ~(1 << 3); //disables one-pulse mode + 431:Src/main.c **** + 432:Src/main.c **** + 433:Src/main.c **** + 434:Src/main.c **** TIM11 -> CNT = 0; + 435:Src/main.c **** TIM4 -> CNT = 0; + 436:Src/main.c **** + 437:Src/main.c **** HAL_TIM_PWM_Start(&htim11, TIM_CHANNEL_1); //start modulating by Mach-Zander modulator + 438:Src/main.c **** HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); //start ADC clock + 439:Src/main.c **** //TIM4 -> CNT = 0; + 440:Src/main.c **** + 441:Src/main.c **** TIM4 -> CNT = TIM4 -> ARR - 20; // not zero to make phase shift that will be robust to big de + 442:Src/main.c **** TIM11 -> CNT = 0; + 443:Src/main.c **** + 444:Src/main.c **** + 445:Src/main.c **** while (task.current_param < task.max_param) + 446:Src/main.c **** { + ARM GAS /tmp/ccWQNJQt.s page 47 + + + 447:Src/main.c **** if (TIM10_coflag) + 448:Src/main.c **** { + 449:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); + 450:Src/main.c **** //TIM11 -> CNT = 0; // to link modulator phase + 451:Src/main.c **** //TIM4 -> CNT = 0; // to link ADC clock phase + 452:Src/main.c **** task.current_param += task.delta_param; + 453:Src/main.c **** TO10 = 0; + 454:Src/main.c **** TIM10_coflag = 0; + 455:Src/main.c **** + 456:Src/main.c **** HAL_GPIO_WritePin(GPIOG, GPIO_PIN_9, GPIO_PIN_SET); // set the current step laser current t + 457:Src/main.c **** HAL_GPIO_WritePin(GPIOG, GPIO_PIN_9, GPIO_PIN_RESET); + 458:Src/main.c **** //* + 459:Src/main.c **** if (step_counter % trigger_step == 0){ //trigger at every 60 step + 460:Src/main.c **** OUT_trigger(trigger_counter); + 461:Src/main.c **** ++trigger_counter; + 462:Src/main.c **** } + 463:Src/main.c **** ++step_counter; + 464:Src/main.c **** //*/ + 465:Src/main.c **** /* + 466:Src/main.c **** ++task_sheduler; + 467:Src/main.c **** if (task_sheduler >= 10){ + 468:Src/main.c **** task_sheduler = 0; + 469:Src/main.c **** } + 470:Src/main.c **** //maintain stable temperature of laser 2 + 471:Src/main.c **** if (task_sheduler == 0){ + 472:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); + 473:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); + 474:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); + 475:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 + 476:Src/main.c **** } + 477:Src/main.c **** //maintain stable temperature of laser 1 + 478:Src/main.c **** //* + 479:Src/main.c **** if (task_sheduler == 5){ + 480:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); + 481:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); + 482:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); + 483:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 + 484:Src/main.c **** } + 485:Src/main.c **** //*/ + 486:Src/main.c **** } + 487:Src/main.c **** } + 488:Src/main.c **** TIM11 -> DIER |= 1; //enable update interrupt. In this IRQ handler we will set both tims to o + 489:Src/main.c **** //TIM11 -> CR1 |= 1 << 3; //sets timer to one-pulse mode. So it will turn off at the next Upd + 490:Src/main.c **** //TIM4 -> CR1 |= 1 << 3; //sets timer to one-pulse mode. So it will turn off at the next Upda + 491:Src/main.c **** //but one-pulse mode should be disabled + 492:Src/main.c **** + 493:Src/main.c **** //HAL_TIM_PWM_Stop(&htim11, TIM_CHANNEL_1); //start modulating by Mach-Zander modulator + 494:Src/main.c **** //HAL_TIM_PWM_Stop(&htim4, TIM_CHANNEL_3); //start ADC clock + 495:Src/main.c **** + 496:Src/main.c **** + 497:Src/main.c **** + 498:Src/main.c **** Stop_TIM10(); + 499:Src/main.c **** + 500:Src/main.c **** task.current_param = task.min_param; + 501:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); + 502:Src/main.c **** if (task.tau > 3) + 503:Src/main.c **** { + ARM GAS /tmp/ccWQNJQt.s page 48 + + + 504:Src/main.c **** TIM10_period = htim10.Init.Period; + 505:Src/main.c **** htim10.Init.Period = 9999; + 506:Src/main.c **** TO10_counter = (task.tau - 1) * 100; + 507:Src/main.c **** } + 508:Src/main.c **** HAL_TIM_Base_Start_IT(&htim10); + 509:Src/main.c **** break; + 510:Src/main.c **** case TT_CHANGE_CURR_2: + 511:Src/main.c **** //Blink laser 2 + 512:Src/main.c **** //* + 513:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.curr); + 514:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); + 515:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); + 516:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); + 517:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); + 518:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); + 519:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 + 520:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); + 521:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 + 522:Src/main.c **** + 523:Src/main.c **** LD_blinker.task_type = 2; + 524:Src/main.c **** LD_blinker.state = 0; // 0 -- disabled (do nothing); 1 -- update LD current; 2 -- blinking, L + 525:Src/main.c **** //LD_blinker.param = task.current_param; + 526:Src/main.c **** LD_blinker.param = 0; + 527:Src/main.c **** LD_blinker.param = 1000; // LD2 current (in unspecified units) + 528:Src/main.c **** LD_blinker.signal_port = OUT_9_GPIO_Port; + 529:Src/main.c **** LD_blinker.signal_pin = OUT_9_Pin; + 530:Src/main.c **** + 531:Src/main.c **** TIM8->ARR = 10000; //zero to LD_blinker.param change frequency (also in unspecified units). + 532:Src/main.c **** //When it is too low -- Desktop app crashes (there is not so much compute sources on MCU + 533:Src/main.c **** st = HAL_TIM_Base_Start_IT(&htim8); + 534:Src/main.c **** if (st != HAL_OK) + 535:Src/main.c **** while(1); + 536:Src/main.c **** // */ + 537:Src/main.c **** + 538:Src/main.c **** // Toggle pin for oscilloscope + 539:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); + 540:Src/main.c **** uint32_t i = 10000; while (--i){} + 541:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); + 542:Src/main.c **** LD_blinker.state = 2; + 543:Src/main.c **** + 544:Src/main.c **** st = HAL_TIM_Base_Start_IT(&htim10); + 545:Src/main.c **** if (st != HAL_OK) + 546:Src/main.c **** while(1); + 547:Src/main.c **** while (task.current_param < task.max_param) + 548:Src/main.c **** { + 549:Src/main.c **** if (TIM10_coflag) + 550:Src/main.c **** { + 551:Src/main.c **** //Set_LTEC(TT_CHANGE_CURR_2, task.current_param); + 552:Src/main.c **** //LD_blinker.param = task.current_param; + 553:Src/main.c **** //++LD_blinker.param; + 554:Src/main.c **** task.current_param += task.delta_param; + 555:Src/main.c **** TO10 = 0; + 556:Src/main.c **** TIM10_coflag = 0; + 557:Src/main.c **** + 558:Src/main.c **** + 559:Src/main.c **** } + 560:Src/main.c **** } + ARM GAS /tmp/ccWQNJQt.s page 49 + + + 561:Src/main.c **** HAL_TIM_Base_Stop(&htim10); + 562:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); + 563:Src/main.c **** + 564:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); + 565:Src/main.c **** + 566:Src/main.c **** HAL_TIM_Base_Stop_IT(&htim8); + 567:Src/main.c **** TIM8->CNT = 0; + 568:Src/main.c **** + 569:Src/main.c **** Stop_TIM10(); + 570:Src/main.c **** task.current_param = task.min_param; + 571:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); + 572:Src/main.c **** if (task.tau > 3) + 573:Src/main.c **** { + 574:Src/main.c **** TIM10_period = htim10.Init.Period; + 575:Src/main.c **** htim10.Init.Period = 9999; + 576:Src/main.c **** TO10_counter = (task.tau - 1) * 100; + 577:Src/main.c **** } + 578:Src/main.c **** HAL_TIM_Base_Start_IT(&htim10); + 579:Src/main.c **** + 580:Src/main.c **** + 581:Src/main.c **** //*/ + 582:Src/main.c **** + 583:Src/main.c **** /* // Backup + 584:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.curr); + 585:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); + 586:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); + 587:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); + 588:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); + 589:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); + 590:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 + 591:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); + 592:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 + 593:Src/main.c **** + 594:Src/main.c **** // Toggle pin for oscilloscope + 595:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); + 596:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); + 597:Src/main.c **** + 598:Src/main.c **** st = HAL_TIM_Base_Start_IT(&htim10); + 599:Src/main.c **** if (st != HAL_OK) + 600:Src/main.c **** while(1); + 601:Src/main.c **** while (task.current_param < task.max_param) + 602:Src/main.c **** { + 603:Src/main.c **** if (TIM10_coflag) + 604:Src/main.c **** { + 605:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); + 606:Src/main.c **** task.current_param += task.delta_param; + 607:Src/main.c **** TO10 = 0; + 608:Src/main.c **** TIM10_coflag = 0; + 609:Src/main.c **** + 610:Src/main.c **** + 611:Src/main.c **** } + 612:Src/main.c **** } + 613:Src/main.c **** Stop_TIM10(); + 614:Src/main.c **** task.current_param = task.min_param; + 615:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); + 616:Src/main.c **** if (task.tau > 3) + 617:Src/main.c **** { + ARM GAS /tmp/ccWQNJQt.s page 50 + + + 618:Src/main.c **** TIM10_period = htim10.Init.Period; + 619:Src/main.c **** htim10.Init.Period = 9999; + 620:Src/main.c **** TO10_counter = (task.tau - 1) * 100; + 621:Src/main.c **** } + 622:Src/main.c **** HAL_TIM_Base_Start_IT(&htim10); + 623:Src/main.c **** */ + 624:Src/main.c **** + 625:Src/main.c **** + 626:Src/main.c **** break; + 627:Src/main.c **** case TT_CHANGE_TEMP_1: + 628:Src/main.c **** // isn't implemented + 629:Src/main.c **** break; + 630:Src/main.c **** case TT_CHANGE_TEMP_2: + 631:Src/main.c **** // isn't implemented + 632:Src/main.c **** break; + 633:Src/main.c **** } + 634:Src/main.c **** + 635:Src/main.c **** if (TO7>TO7_before) + 636:Src/main.c **** { + 637:Src/main.c **** TO7_before = TO7; + 638:Src/main.c **** + 639:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 + 640:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 + 641:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 + 642:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 + 643:Src/main.c **** + 644:Src/main.c **** Long_Data[1] = LD1_param.POWER;//Translate Data from monitor photodiode of LD1 to Long_Data + 645:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data + 646:Src/main.c **** + 647:Src/main.c **** //Prepare DATA of internals ADCs + 648:Src/main.c **** //Put the temperature of LD2 to Long_Data: + 649:Src/main.c **** temp16 = Get_ADC(0); + 650:Src/main.c **** temp16 = Get_ADC(1); + 651:Src/main.c **** Long_Data[7] = temp16; + 652:Src/main.c **** + 653:Src/main.c **** //Put the temperature of LD2 to Long_Data: + 654:Src/main.c **** temp16 = Get_ADC(1); + 655:Src/main.c **** Long_Data[8] = temp16; + 656:Src/main.c **** + 657:Src/main.c **** //Put the temperature of LD2 to Long_Data: + 658:Src/main.c **** temp16 = Get_ADC(1); + 659:Src/main.c **** Long_Data[9] = temp16; + 660:Src/main.c **** + 661:Src/main.c **** //Put the temperature of LD2 to Long_Data: + 662:Src/main.c **** temp16 = Get_ADC(1); + 663:Src/main.c **** Long_Data[10] = temp16; + 664:Src/main.c **** + 665:Src/main.c **** //Put the temperature of LD2 to Long_Data: + 666:Src/main.c **** temp16 = Get_ADC(1); + 667:Src/main.c **** Long_Data[11] = temp16; + 668:Src/main.c **** temp16 = Get_ADC(2); + 669:Src/main.c **** + 670:Src/main.c **** //Put the temperature of LD2 to Long_Data: + 671:Src/main.c **** temp16 = Get_ADC(3); + 672:Src/main.c **** temp16 = Get_ADC(4); + 673:Src/main.c **** Long_Data[12] = temp16; + 674:Src/main.c **** temp16 = Get_ADC(5); + ARM GAS /tmp/ccWQNJQt.s page 51 + + + 675:Src/main.c **** + 676:Src/main.c **** //Put the timer tick to Long_Data: + 677:Src/main.c **** TO6_stop = TO6; + 678:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; + 679:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; + 680:Src/main.c **** + 681:Src/main.c **** //Put the average temperature of LD1 to Long_Data: + 682:Src/main.c **** Long_Data[5] = LD1_param.LD_CURR_TEMP; + 683:Src/main.c **** + 684:Src/main.c **** //Put the average temperature of LD2 to Long_Data: + 685:Src/main.c **** Long_Data[6] = LD2_param.LD_CURR_TEMP; + 686:Src/main.c **** } + 687:Src/main.c **** while (!TIM10_coflag); + 688:Src/main.c **** + 689:Src/main.c **** Stop_TIM10(); + 690:Src/main.c **** + 691:Src/main.c **** if (task.tau > 3) + 692:Src/main.c **** { + 693:Src/main.c **** htim10.Init.Period = TIM10_period; + 694:Src/main.c **** TO10_counter = task.dt / 10; + 695:Src/main.c **** } + 696:Src/main.c **** + 697:Src/main.c **** CPU_state_old = RUN_TASK; + 698:Src/main.c **** break; + 699:Src/main.c **** } + 700:Src/main.c **** + 701:Src/main.c **** switch (UART_transmission_request) + 702:Src/main.c **** { + 703:Src/main.c **** case MESS_01://Default state + 704:Src/main.c **** USART_TX(State_Data,2); + 705:Src/main.c **** //HAL_UART_Transmit(&huart1, State_Data, 2, 10); + 706:Src/main.c **** State_Data[0]=0; + 707:Src/main.c **** State_Data[1]=0;//All OK! + 708:Src/main.c **** UART_transmission_request = NO_MESS; + 709:Src/main.c **** break; + 710:Src/main.c **** case MESS_02://Transmith packet + 711:Src/main.c **** + 712:Src/main.c **** //Find CS and put to Long_Data: + 713:Src/main.c **** CS_result = CalculateChecksum(&Long_Data[1], DL_16-2); + 714:Src/main.c **** Long_Data[DL_16-1] = CS_result; + 715:Src/main.c **** + 716:Src/main.c **** for (uint16_t i = 0; i < DL_16; i++) + 717:Src/main.c **** { + 718:Src/main.c **** UART_DATA[i*2] = (Long_Data[i])&0xff; + 719:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; + 720:Src/main.c **** } + 721:Src/main.c **** //HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0); + 722:Src/main.c **** //HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); + 723:Src/main.c **** //HAL_UART_Transmit_DMA(&huart1, UART_DATA, DL_8); + 724:Src/main.c **** //huart1.gState = HAL_UART_STATE_READY; + 725:Src/main.c **** //hdma_usart1_tx.State=HAL_DMA_STATE_BUSY; + 726:Src/main.c **** USART_TX_DMA (DL_8);//Send data by USART using DMA + 727:Src/main.c **** UART_transmission_request = NO_MESS; + 728:Src/main.c **** break; + 729:Src/main.c **** case MESS_03://Transmith saved packet + 730:Src/main.c **** for (uint16_t i = 0; i < DL_16; i++) + 731:Src/main.c **** { + ARM GAS /tmp/ccWQNJQt.s page 52 + + + 732:Src/main.c **** UART_DATA[i*2] = (Long_Data[i])&0xff; + 733:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; + 734:Src/main.c **** } + 735:Src/main.c **** //HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); + 736:Src/main.c **** //HAL_UART_Transmit_DMA(&huart1, UART_DATA, DL_8); + 737:Src/main.c **** //huart1.gState = HAL_UART_STATE_READY; + 738:Src/main.c **** //hdma_usart1_tx.State=HAL_DMA_STATE_BUSY; + 739:Src/main.c **** USART_TX_DMA (DL_8);//Send data by USART using DMA + 740:Src/main.c **** UART_transmission_request = NO_MESS; + 741:Src/main.c **** break; + 742:Src/main.c **** } + 743:Src/main.c **** if ((flg_tmt==1)&&((TO6-TO6_uart)>100))//Uart timeout handle. if timeout beetween zero byte of + 744:Src/main.c **** { + 745:Src/main.c **** UART_rec_incr = 0;//Reset uart command counter + 746:Src/main.c **** State_Data[0] |= UART_ERR;//timeout error! + 747:Src/main.c **** UART_transmission_request = MESS_01;//Send status + 748:Src/main.c **** flg_tmt = 0;//Reset timeout flag + 749:Src/main.c **** } + 750:Src/main.c **** /* USER CODE END WHILE */ + 751:Src/main.c **** + 752:Src/main.c **** /* USER CODE BEGIN 3 */ + 753:Src/main.c **** } + 754:Src/main.c **** /* USER CODE END 3 */ + 755:Src/main.c **** } + 756:Src/main.c **** + 757:Src/main.c **** /** + 758:Src/main.c **** * @brief System Clock Configuration + 759:Src/main.c **** * @retval None + 760:Src/main.c **** */ + 761:Src/main.c **** void SystemClock_Config(void) + 762:Src/main.c **** { + 763:Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 764:Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 765:Src/main.c **** + 766:Src/main.c **** /** Configure the main internal regulator output voltage + 767:Src/main.c **** */ + 768:Src/main.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 769:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 770:Src/main.c **** + 771:Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters + 772:Src/main.c **** * in the RCC_OscInitTypeDef structure. + 773:Src/main.c **** */ + 774:Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + 775:Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 776:Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 777:Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + 778:Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 25; + 779:Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 368; + 780:Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + 781:Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 8; + 782:Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2; + 783:Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 784:Src/main.c **** { + 785:Src/main.c **** Error_Handler(); + 786:Src/main.c **** } + 787:Src/main.c **** + 788:Src/main.c **** /** Activate the Over-Drive mode + ARM GAS /tmp/ccWQNJQt.s page 53 + + + 789:Src/main.c **** */ + 790:Src/main.c **** if (HAL_PWREx_EnableOverDrive() != HAL_OK) + 791:Src/main.c **** { + 792:Src/main.c **** Error_Handler(); + 793:Src/main.c **** } + 794:Src/main.c **** + 795:Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks + 796:Src/main.c **** */ + 797:Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 798:Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + 799:Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + 800:Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 801:Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + 802:Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + 803:Src/main.c **** + 804:Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK) + 805:Src/main.c **** { + 806:Src/main.c **** Error_Handler(); + 807:Src/main.c **** } + 808:Src/main.c **** } + 809:Src/main.c **** + 810:Src/main.c **** /** + 811:Src/main.c **** * @brief ADC1 Initialization Function + 812:Src/main.c **** * @param None + 813:Src/main.c **** * @retval None + 814:Src/main.c **** */ + 815:Src/main.c **** static void MX_ADC1_Init(void) + 816:Src/main.c **** { + 817:Src/main.c **** + 818:Src/main.c **** /* USER CODE BEGIN ADC1_Init 0 */ + 819:Src/main.c **** + 820:Src/main.c **** /* USER CODE END ADC1_Init 0 */ + 821:Src/main.c **** + 822:Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0}; + 823:Src/main.c **** + 824:Src/main.c **** /* USER CODE BEGIN ADC1_Init 1 */ + 825:Src/main.c **** + 826:Src/main.c **** /* USER CODE END ADC1_Init 1 */ + 827:Src/main.c **** + 828:Src/main.c **** /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of con + 829:Src/main.c **** */ + 830:Src/main.c **** hadc1.Instance = ADC1; + 831:Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; + 832:Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; + 833:Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; + 834:Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; + 835:Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; + 836:Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + 837:Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; + 838:Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + 839:Src/main.c **** hadc1.Init.NbrOfConversion = 5; + 840:Src/main.c **** hadc1.Init.DMAContinuousRequests = DISABLE; + 841:Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + 842:Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) + 843:Src/main.c **** { + 844:Src/main.c **** Error_Handler(); + 845:Src/main.c **** } + ARM GAS /tmp/ccWQNJQt.s page 54 + + + 846:Src/main.c **** + 847:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it + 848:Src/main.c **** */ + 849:Src/main.c **** sConfig.Channel = ADC_CHANNEL_9; + 850:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; + 851:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; + 852:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 853:Src/main.c **** { + 854:Src/main.c **** Error_Handler(); + 855:Src/main.c **** } + 856:Src/main.c **** + 857:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it + 858:Src/main.c **** */ + 859:Src/main.c **** sConfig.Channel = ADC_CHANNEL_8; + 860:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_2; + 861:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 862:Src/main.c **** { + 863:Src/main.c **** Error_Handler(); + 864:Src/main.c **** } + 865:Src/main.c **** + 866:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it + 867:Src/main.c **** */ + 868:Src/main.c **** sConfig.Channel = ADC_CHANNEL_2; + 869:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_3; + 870:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 871:Src/main.c **** { + 872:Src/main.c **** Error_Handler(); + 873:Src/main.c **** } + 874:Src/main.c **** + 875:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it + 876:Src/main.c **** */ + 877:Src/main.c **** sConfig.Channel = ADC_CHANNEL_10; + 878:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_4; + 879:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 880:Src/main.c **** { + 881:Src/main.c **** Error_Handler(); + 882:Src/main.c **** } + 883:Src/main.c **** + 884:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it + 885:Src/main.c **** */ + 886:Src/main.c **** sConfig.Channel = ADC_CHANNEL_11; + 887:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_5; + 888:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 889:Src/main.c **** { + 890:Src/main.c **** Error_Handler(); + 891:Src/main.c **** } + 892:Src/main.c **** /* USER CODE BEGIN ADC1_Init 2 */ + 893:Src/main.c **** + 894:Src/main.c **** /* USER CODE END ADC1_Init 2 */ + 895:Src/main.c **** + 896:Src/main.c **** } + 897:Src/main.c **** + 898:Src/main.c **** /** + 899:Src/main.c **** * @brief ADC3 Initialization Function + 900:Src/main.c **** * @param None + 901:Src/main.c **** * @retval None + 902:Src/main.c **** */ + ARM GAS /tmp/ccWQNJQt.s page 55 + + + 903:Src/main.c **** static void MX_ADC3_Init(void) + 904:Src/main.c **** { + 905:Src/main.c **** + 906:Src/main.c **** /* USER CODE BEGIN ADC3_Init 0 */ + 907:Src/main.c **** + 908:Src/main.c **** /* USER CODE END ADC3_Init 0 */ + 909:Src/main.c **** + 910:Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0}; + 911:Src/main.c **** + 912:Src/main.c **** /* USER CODE BEGIN ADC3_Init 1 */ + 913:Src/main.c **** + 914:Src/main.c **** /* USER CODE END ADC3_Init 1 */ + 915:Src/main.c **** + 916:Src/main.c **** /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of con + 917:Src/main.c **** */ + 918:Src/main.c **** hadc3.Instance = ADC3; + 919:Src/main.c **** hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; + 920:Src/main.c **** hadc3.Init.Resolution = ADC_RESOLUTION_12B; + 921:Src/main.c **** hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; + 922:Src/main.c **** hadc3.Init.ContinuousConvMode = DISABLE; + 923:Src/main.c **** hadc3.Init.DiscontinuousConvMode = DISABLE; + 924:Src/main.c **** hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + 925:Src/main.c **** hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; + 926:Src/main.c **** hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; + 927:Src/main.c **** hadc3.Init.NbrOfConversion = 1; + 928:Src/main.c **** hadc3.Init.DMAContinuousRequests = DISABLE; + 929:Src/main.c **** hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + 930:Src/main.c **** if (HAL_ADC_Init(&hadc3) != HAL_OK) + 931:Src/main.c **** { + 932:Src/main.c **** Error_Handler(); + 933:Src/main.c **** } + 934:Src/main.c **** + 935:Src/main.c **** /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and it + 936:Src/main.c **** */ + 937:Src/main.c **** sConfig.Channel = ADC_CHANNEL_15; + 938:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; + 939:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; + 940:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) + 941:Src/main.c **** { + 942:Src/main.c **** Error_Handler(); + 943:Src/main.c **** } + 944:Src/main.c **** /* USER CODE BEGIN ADC3_Init 2 */ + 945:Src/main.c **** + 946:Src/main.c **** /* USER CODE END ADC3_Init 2 */ + 947:Src/main.c **** + 948:Src/main.c **** } + 949:Src/main.c **** + 950:Src/main.c **** /** + 951:Src/main.c **** * @brief SDMMC1 Initialization Function + 952:Src/main.c **** * @param None + 953:Src/main.c **** * @retval None + 954:Src/main.c **** */ + 955:Src/main.c **** static void MX_SDMMC1_SD_Init(void) + 956:Src/main.c **** { + 95 .loc 1 956 1 is_stmt 1 view -0 + 96 .cfi_startproc + 97 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccWQNJQt.s page 56 + + + 98 @ frame_needed = 0, uses_anonymous_args = 0 + 99 @ link register save eliminated. + 957:Src/main.c **** + 958:Src/main.c **** /* USER CODE BEGIN SDMMC1_Init 0 */ + 959:Src/main.c **** + 960:Src/main.c **** /* USER CODE END SDMMC1_Init 0 */ + 961:Src/main.c **** + 962:Src/main.c **** /* USER CODE BEGIN SDMMC1_Init 1 */ + 963:Src/main.c **** + 964:Src/main.c **** /* USER CODE END SDMMC1_Init 1 */ + 965:Src/main.c **** hsd1.Instance = SDMMC1; + 100 .loc 1 965 3 view .LVU21 + 101 .loc 1 965 17 is_stmt 0 view .LVU22 + 102 0000 064B ldr r3, .L6 + 103 0002 074A ldr r2, .L6+4 + 104 0004 1A60 str r2, [r3] + 966:Src/main.c **** hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + 105 .loc 1 966 3 is_stmt 1 view .LVU23 + 106 .loc 1 966 23 is_stmt 0 view .LVU24 + 107 0006 0022 movs r2, #0 + 108 0008 5A60 str r2, [r3, #4] + 967:Src/main.c **** hsd1.Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; + 109 .loc 1 967 3 is_stmt 1 view .LVU25 + 110 .loc 1 967 25 is_stmt 0 view .LVU26 + 111 000a 9A60 str r2, [r3, #8] + 968:Src/main.c **** hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + 112 .loc 1 968 3 is_stmt 1 view .LVU27 + 113 .loc 1 968 28 is_stmt 0 view .LVU28 + 114 000c DA60 str r2, [r3, #12] + 969:Src/main.c **** hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B; + 115 .loc 1 969 3 is_stmt 1 view .LVU29 + 116 .loc 1 969 21 is_stmt 0 view .LVU30 + 117 000e 4FF40061 mov r1, #2048 + 118 0012 1961 str r1, [r3, #16] + 970:Src/main.c **** hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + 119 .loc 1 970 3 is_stmt 1 view .LVU31 + 120 .loc 1 970 33 is_stmt 0 view .LVU32 + 121 0014 5A61 str r2, [r3, #20] + 971:Src/main.c **** hsd1.Init.ClockDiv = 20; + 122 .loc 1 971 3 is_stmt 1 view .LVU33 + 123 .loc 1 971 22 is_stmt 0 view .LVU34 + 124 0016 1422 movs r2, #20 + 125 0018 9A61 str r2, [r3, #24] + 972:Src/main.c **** /* USER CODE BEGIN SDMMC1_Init 2 */ + 973:Src/main.c **** + 974:Src/main.c **** /* USER CODE END SDMMC1_Init 2 */ + 975:Src/main.c **** + 976:Src/main.c **** } + 126 .loc 1 976 1 view .LVU35 + 127 001a 7047 bx lr + 128 .L7: + 129 .align 2 + 130 .L6: + 131 001c 00000000 .word hsd1 + 132 0020 002C0140 .word 1073818624 + 133 .cfi_endproc + 134 .LFE1190: + ARM GAS /tmp/ccWQNJQt.s page 57 + + + 136 .section .text.MX_DMA_Init,"ax",%progbits + 137 .align 1 + 138 .syntax unified + 139 .thumb + 140 .thumb_func + 142 MX_DMA_Init: + 143 .LFB1205: + 977:Src/main.c **** + 978:Src/main.c **** /** + 979:Src/main.c **** * @brief SPI2 Initialization Function + 980:Src/main.c **** * @param None + 981:Src/main.c **** * @retval None + 982:Src/main.c **** */ + 983:Src/main.c **** static void MX_SPI2_Init(void) + 984:Src/main.c **** { + 985:Src/main.c **** + 986:Src/main.c **** /* USER CODE BEGIN SPI2_Init 0 */ + 987:Src/main.c **** + 988:Src/main.c **** /* USER CODE END SPI2_Init 0 */ + 989:Src/main.c **** + 990:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; + 991:Src/main.c **** + 992:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + 993:Src/main.c **** + 994:Src/main.c **** /* Peripheral clock enable */ + 995:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2); + 996:Src/main.c **** + 997:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOB); + 998:Src/main.c **** /**SPI2 GPIO Configuration + 999:Src/main.c **** PB13 ------> SPI2_SCK +1000:Src/main.c **** PB15 ------> SPI2_MOSI +1001:Src/main.c **** */ +1002:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_13; +1003:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; +1004:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; +1005:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; +1006:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; +1007:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; +1008:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); +1009:Src/main.c **** +1010:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_15; +1011:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; +1012:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; +1013:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; +1014:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; +1015:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; +1016:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); +1017:Src/main.c **** +1018:Src/main.c **** /* USER CODE BEGIN SPI2_Init 1 */ +1019:Src/main.c **** +1020:Src/main.c **** /* USER CODE END SPI2_Init 1 */ +1021:Src/main.c **** /* SPI2 parameter configuration*/ +1022:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX; +1023:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; +1024:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; +1025:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; +1026:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; + ARM GAS /tmp/ccWQNJQt.s page 58 + + +1027:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; +1028:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8; +1029:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; +1030:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; +1031:Src/main.c **** SPI_InitStruct.CRCPoly = 7; +1032:Src/main.c **** LL_SPI_Init(SPI2, &SPI_InitStruct); +1033:Src/main.c **** LL_SPI_SetStandard(SPI2, LL_SPI_PROTOCOL_MOTOROLA); +1034:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI2); +1035:Src/main.c **** /* USER CODE BEGIN SPI2_Init 2 */ +1036:Src/main.c **** +1037:Src/main.c **** /* USER CODE END SPI2_Init 2 */ +1038:Src/main.c **** +1039:Src/main.c **** } +1040:Src/main.c **** +1041:Src/main.c **** /** +1042:Src/main.c **** * @brief SPI4 Initialization Function +1043:Src/main.c **** * @param None +1044:Src/main.c **** * @retval None +1045:Src/main.c **** */ +1046:Src/main.c **** static void MX_SPI4_Init(void) +1047:Src/main.c **** { +1048:Src/main.c **** +1049:Src/main.c **** /* USER CODE BEGIN SPI4_Init 0 */ +1050:Src/main.c **** +1051:Src/main.c **** /* USER CODE END SPI4_Init 0 */ +1052:Src/main.c **** +1053:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; +1054:Src/main.c **** +1055:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; +1056:Src/main.c **** +1057:Src/main.c **** /* Peripheral clock enable */ +1058:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI4); +1059:Src/main.c **** +1060:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOE); +1061:Src/main.c **** /**SPI4 GPIO Configuration +1062:Src/main.c **** PE12 ------> SPI4_SCK +1063:Src/main.c **** PE13 ------> SPI4_MISO +1064:Src/main.c **** */ +1065:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_12; +1066:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; +1067:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; +1068:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; +1069:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; +1070:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; +1071:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); +1072:Src/main.c **** +1073:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_13; +1074:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; +1075:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; +1076:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; +1077:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; +1078:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; +1079:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); +1080:Src/main.c **** +1081:Src/main.c **** /* USER CODE BEGIN SPI4_Init 1 */ +1082:Src/main.c **** +1083:Src/main.c **** /* USER CODE END SPI4_Init 1 */ + ARM GAS /tmp/ccWQNJQt.s page 59 + + +1084:Src/main.c **** /* SPI4 parameter configuration*/ +1085:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_SIMPLEX_RX; +1086:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; +1087:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; +1088:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; +1089:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; +1090:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; +1091:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; +1092:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; +1093:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; +1094:Src/main.c **** SPI_InitStruct.CRCPoly = 7; +1095:Src/main.c **** LL_SPI_Init(SPI4, &SPI_InitStruct); +1096:Src/main.c **** LL_SPI_SetStandard(SPI4, LL_SPI_PROTOCOL_MOTOROLA); +1097:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI4); +1098:Src/main.c **** /* USER CODE BEGIN SPI4_Init 2 */ +1099:Src/main.c **** +1100:Src/main.c **** /* USER CODE END SPI4_Init 2 */ +1101:Src/main.c **** +1102:Src/main.c **** } +1103:Src/main.c **** +1104:Src/main.c **** /** +1105:Src/main.c **** * @brief SPI5 Initialization Function +1106:Src/main.c **** * @param None +1107:Src/main.c **** * @retval None +1108:Src/main.c **** */ +1109:Src/main.c **** static void MX_SPI5_Init(void) +1110:Src/main.c **** { +1111:Src/main.c **** +1112:Src/main.c **** /* USER CODE BEGIN SPI5_Init 0 */ +1113:Src/main.c **** +1114:Src/main.c **** /* USER CODE END SPI5_Init 0 */ +1115:Src/main.c **** +1116:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; +1117:Src/main.c **** +1118:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; +1119:Src/main.c **** +1120:Src/main.c **** /* Peripheral clock enable */ +1121:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI5); +1122:Src/main.c **** +1123:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOF); +1124:Src/main.c **** /**SPI5 GPIO Configuration +1125:Src/main.c **** PF7 ------> SPI5_SCK +1126:Src/main.c **** PF8 ------> SPI5_MISO +1127:Src/main.c **** */ +1128:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_7; +1129:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; +1130:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; +1131:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; +1132:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; +1133:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; +1134:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); +1135:Src/main.c **** +1136:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_8; +1137:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; +1138:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; +1139:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; +1140:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + ARM GAS /tmp/ccWQNJQt.s page 60 + + +1141:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; +1142:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); +1143:Src/main.c **** +1144:Src/main.c **** /* USER CODE BEGIN SPI5_Init 1 */ +1145:Src/main.c **** +1146:Src/main.c **** /* USER CODE END SPI5_Init 1 */ +1147:Src/main.c **** /* SPI5 parameter configuration*/ +1148:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_SIMPLEX_RX; +1149:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; +1150:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; +1151:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; +1152:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; +1153:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; +1154:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; +1155:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; +1156:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; +1157:Src/main.c **** SPI_InitStruct.CRCPoly = 7; +1158:Src/main.c **** LL_SPI_Init(SPI5, &SPI_InitStruct); +1159:Src/main.c **** LL_SPI_SetStandard(SPI5, LL_SPI_PROTOCOL_MOTOROLA); +1160:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI5); +1161:Src/main.c **** /* USER CODE BEGIN SPI5_Init 2 */ +1162:Src/main.c **** +1163:Src/main.c **** /* USER CODE END SPI5_Init 2 */ +1164:Src/main.c **** +1165:Src/main.c **** } +1166:Src/main.c **** +1167:Src/main.c **** /** +1168:Src/main.c **** * @brief SPI6 Initialization Function +1169:Src/main.c **** * @param None +1170:Src/main.c **** * @retval None +1171:Src/main.c **** */ +1172:Src/main.c **** static void MX_SPI6_Init(void) +1173:Src/main.c **** { +1174:Src/main.c **** +1175:Src/main.c **** /* USER CODE BEGIN SPI6_Init 0 */ +1176:Src/main.c **** +1177:Src/main.c **** /* USER CODE END SPI6_Init 0 */ +1178:Src/main.c **** +1179:Src/main.c **** LL_SPI_InitTypeDef SPI_InitStruct = {0}; +1180:Src/main.c **** +1181:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; +1182:Src/main.c **** +1183:Src/main.c **** /* Peripheral clock enable */ +1184:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI6); +1185:Src/main.c **** +1186:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA); +1187:Src/main.c **** /**SPI6 GPIO Configuration +1188:Src/main.c **** PA5 ------> SPI6_SCK +1189:Src/main.c **** PA7 ------> SPI6_MOSI +1190:Src/main.c **** */ +1191:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_5; +1192:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; +1193:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; +1194:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; +1195:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; +1196:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; +1197:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + ARM GAS /tmp/ccWQNJQt.s page 61 + + +1198:Src/main.c **** +1199:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_7; +1200:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; +1201:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; +1202:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; +1203:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; +1204:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; +1205:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); +1206:Src/main.c **** +1207:Src/main.c **** /* USER CODE BEGIN SPI6_Init 1 */ +1208:Src/main.c **** +1209:Src/main.c **** /* USER CODE END SPI6_Init 1 */ +1210:Src/main.c **** /* SPI6 parameter configuration*/ +1211:Src/main.c **** SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX; +1212:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; +1213:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; +1214:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; +1215:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; +1216:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; +1217:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; +1218:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; +1219:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; +1220:Src/main.c **** SPI_InitStruct.CRCPoly = 7; +1221:Src/main.c **** LL_SPI_Init(SPI6, &SPI_InitStruct); +1222:Src/main.c **** LL_SPI_SetStandard(SPI6, LL_SPI_PROTOCOL_MOTOROLA); +1223:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI6); +1224:Src/main.c **** /* USER CODE BEGIN SPI6_Init 2 */ +1225:Src/main.c **** +1226:Src/main.c **** /* USER CODE END SPI6_Init 2 */ +1227:Src/main.c **** +1228:Src/main.c **** } +1229:Src/main.c **** +1230:Src/main.c **** /** +1231:Src/main.c **** * @brief TIM2 Initialization Function +1232:Src/main.c **** * @param None +1233:Src/main.c **** * @retval None +1234:Src/main.c **** */ +1235:Src/main.c **** static void MX_TIM2_Init(void) +1236:Src/main.c **** { +1237:Src/main.c **** +1238:Src/main.c **** /* USER CODE BEGIN TIM2_Init 0 */ +1239:Src/main.c **** +1240:Src/main.c **** /* USER CODE END TIM2_Init 0 */ +1241:Src/main.c **** +1242:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; +1243:Src/main.c **** +1244:Src/main.c **** /* Peripheral clock enable */ +1245:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2); +1246:Src/main.c **** +1247:Src/main.c **** /* TIM2 interrupt Init */ +1248:Src/main.c **** NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); +1249:Src/main.c **** NVIC_EnableIRQ(TIM2_IRQn); +1250:Src/main.c **** +1251:Src/main.c **** /* USER CODE BEGIN TIM2_Init 1 */ +1252:Src/main.c **** +1253:Src/main.c **** /* USER CODE END TIM2_Init 1 */ +1254:Src/main.c **** TIM_InitStruct.Prescaler = 1000; + ARM GAS /tmp/ccWQNJQt.s page 62 + + +1255:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; +1256:Src/main.c **** TIM_InitStruct.Autoreload = 840000; +1257:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; +1258:Src/main.c **** LL_TIM_Init(TIM2, &TIM_InitStruct); +1259:Src/main.c **** LL_TIM_DisableARRPreload(TIM2); +1260:Src/main.c **** LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL); +1261:Src/main.c **** LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET); +1262:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM2); +1263:Src/main.c **** /* USER CODE BEGIN TIM2_Init 2 */ +1264:Src/main.c **** +1265:Src/main.c **** /* USER CODE END TIM2_Init 2 */ +1266:Src/main.c **** +1267:Src/main.c **** } +1268:Src/main.c **** +1269:Src/main.c **** /** +1270:Src/main.c **** * @brief TIM4 Initialization Function +1271:Src/main.c **** * @param None +1272:Src/main.c **** * @retval None +1273:Src/main.c **** */ +1274:Src/main.c **** static void MX_TIM4_Init(void) +1275:Src/main.c **** { +1276:Src/main.c **** +1277:Src/main.c **** /* USER CODE BEGIN TIM4_Init 0 */ +1278:Src/main.c **** +1279:Src/main.c **** /* USER CODE END TIM4_Init 0 */ +1280:Src/main.c **** +1281:Src/main.c **** TIM_ClockConfigTypeDef sClockSourceConfig = {0}; +1282:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; +1283:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; +1284:Src/main.c **** +1285:Src/main.c **** /* USER CODE BEGIN TIM4_Init 1 */ +1286:Src/main.c **** +1287:Src/main.c **** /* USER CODE END TIM4_Init 1 */ +1288:Src/main.c **** htim4.Instance = TIM4; +1289:Src/main.c **** htim4.Init.Prescaler = 0; +1290:Src/main.c **** htim4.Init.CounterMode = TIM_COUNTERMODE_UP; +1291:Src/main.c **** htim4.Init.Period = 45; +1292:Src/main.c **** htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; +1293:Src/main.c **** htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; +1294:Src/main.c **** if (HAL_TIM_Base_Init(&htim4) != HAL_OK) +1295:Src/main.c **** { +1296:Src/main.c **** Error_Handler(); +1297:Src/main.c **** } +1298:Src/main.c **** sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; +1299:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) +1300:Src/main.c **** { +1301:Src/main.c **** Error_Handler(); +1302:Src/main.c **** } +1303:Src/main.c **** if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) +1304:Src/main.c **** { +1305:Src/main.c **** Error_Handler(); +1306:Src/main.c **** } +1307:Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; +1308:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; +1309:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) +1310:Src/main.c **** { +1311:Src/main.c **** Error_Handler(); + ARM GAS /tmp/ccWQNJQt.s page 63 + + +1312:Src/main.c **** } +1313:Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1; +1314:Src/main.c **** sConfigOC.Pulse = 22; +1315:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; +1316:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; +1317:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) +1318:Src/main.c **** { +1319:Src/main.c **** Error_Handler(); +1320:Src/main.c **** } +1321:Src/main.c **** /* USER CODE BEGIN TIM4_Init 2 */ +1322:Src/main.c **** +1323:Src/main.c **** /* USER CODE END TIM4_Init 2 */ +1324:Src/main.c **** HAL_TIM_MspPostInit(&htim4); +1325:Src/main.c **** +1326:Src/main.c **** } +1327:Src/main.c **** +1328:Src/main.c **** /** +1329:Src/main.c **** * @brief TIM5 Initialization Function +1330:Src/main.c **** * @param None +1331:Src/main.c **** * @retval None +1332:Src/main.c **** */ +1333:Src/main.c **** static void MX_TIM5_Init(void) +1334:Src/main.c **** { +1335:Src/main.c **** +1336:Src/main.c **** /* USER CODE BEGIN TIM5_Init 0 */ +1337:Src/main.c **** +1338:Src/main.c **** /* USER CODE END TIM5_Init 0 */ +1339:Src/main.c **** +1340:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; +1341:Src/main.c **** +1342:Src/main.c **** /* Peripheral clock enable */ +1343:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM5); +1344:Src/main.c **** +1345:Src/main.c **** /* TIM5 interrupt Init */ +1346:Src/main.c **** NVIC_SetPriority(TIM5_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); +1347:Src/main.c **** NVIC_EnableIRQ(TIM5_IRQn); +1348:Src/main.c **** +1349:Src/main.c **** /* USER CODE BEGIN TIM5_Init 1 */ +1350:Src/main.c **** +1351:Src/main.c **** /* USER CODE END TIM5_Init 1 */ +1352:Src/main.c **** TIM_InitStruct.Prescaler = 10000; +1353:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; +1354:Src/main.c **** TIM_InitStruct.Autoreload = 560; +1355:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; +1356:Src/main.c **** LL_TIM_Init(TIM5, &TIM_InitStruct); +1357:Src/main.c **** LL_TIM_DisableARRPreload(TIM5); +1358:Src/main.c **** LL_TIM_SetClockSource(TIM5, LL_TIM_CLOCKSOURCE_INTERNAL); +1359:Src/main.c **** LL_TIM_SetTriggerOutput(TIM5, LL_TIM_TRGO_RESET); +1360:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM5); +1361:Src/main.c **** /* USER CODE BEGIN TIM5_Init 2 */ +1362:Src/main.c **** +1363:Src/main.c **** /* USER CODE END TIM5_Init 2 */ +1364:Src/main.c **** +1365:Src/main.c **** } +1366:Src/main.c **** +1367:Src/main.c **** /** +1368:Src/main.c **** * @brief TIM6 Initialization Function + ARM GAS /tmp/ccWQNJQt.s page 64 + + +1369:Src/main.c **** * @param None +1370:Src/main.c **** * @retval None +1371:Src/main.c **** */ +1372:Src/main.c **** static void MX_TIM6_Init(void) +1373:Src/main.c **** { +1374:Src/main.c **** +1375:Src/main.c **** /* USER CODE BEGIN TIM6_Init 0 */ +1376:Src/main.c **** +1377:Src/main.c **** /* USER CODE END TIM6_Init 0 */ +1378:Src/main.c **** +1379:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; +1380:Src/main.c **** +1381:Src/main.c **** /* Peripheral clock enable */ +1382:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM6); +1383:Src/main.c **** +1384:Src/main.c **** /* TIM6 interrupt Init */ +1385:Src/main.c **** NVIC_SetPriority(TIM6_DAC_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); +1386:Src/main.c **** NVIC_EnableIRQ(TIM6_DAC_IRQn); +1387:Src/main.c **** +1388:Src/main.c **** /* USER CODE BEGIN TIM6_Init 1 */ +1389:Src/main.c **** +1390:Src/main.c **** /* USER CODE END TIM6_Init 1 */ +1391:Src/main.c **** TIM_InitStruct.Prescaler = 45999; +1392:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; +1393:Src/main.c **** TIM_InitStruct.Autoreload = 19; +1394:Src/main.c **** LL_TIM_Init(TIM6, &TIM_InitStruct); +1395:Src/main.c **** LL_TIM_DisableARRPreload(TIM6); +1396:Src/main.c **** LL_TIM_SetTriggerOutput(TIM6, LL_TIM_TRGO_ENABLE); +1397:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM6); +1398:Src/main.c **** /* USER CODE BEGIN TIM6_Init 2 */ +1399:Src/main.c **** +1400:Src/main.c **** /* USER CODE END TIM6_Init 2 */ +1401:Src/main.c **** +1402:Src/main.c **** } +1403:Src/main.c **** +1404:Src/main.c **** /** +1405:Src/main.c **** * @brief TIM7 Initialization Function +1406:Src/main.c **** * @param None +1407:Src/main.c **** * @retval None +1408:Src/main.c **** */ +1409:Src/main.c **** static void MX_TIM7_Init(void) +1410:Src/main.c **** { +1411:Src/main.c **** +1412:Src/main.c **** /* USER CODE BEGIN TIM7_Init 0 */ +1413:Src/main.c **** +1414:Src/main.c **** /* USER CODE END TIM7_Init 0 */ +1415:Src/main.c **** +1416:Src/main.c **** LL_TIM_InitTypeDef TIM_InitStruct = {0}; +1417:Src/main.c **** +1418:Src/main.c **** /* Peripheral clock enable */ +1419:Src/main.c **** LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM7); +1420:Src/main.c **** +1421:Src/main.c **** /* TIM7 interrupt Init */ +1422:Src/main.c **** NVIC_SetPriority(TIM7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); +1423:Src/main.c **** NVIC_EnableIRQ(TIM7_IRQn); +1424:Src/main.c **** +1425:Src/main.c **** /* USER CODE BEGIN TIM7_Init 1 */ + ARM GAS /tmp/ccWQNJQt.s page 65 + + +1426:Src/main.c **** +1427:Src/main.c **** /* USER CODE END TIM7_Init 1 */ +1428:Src/main.c **** TIM_InitStruct.Prescaler = 919; +1429:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; +1430:Src/main.c **** TIM_InitStruct.Autoreload = 99; +1431:Src/main.c **** LL_TIM_Init(TIM7, &TIM_InitStruct); +1432:Src/main.c **** LL_TIM_DisableARRPreload(TIM7); +1433:Src/main.c **** LL_TIM_SetTriggerOutput(TIM7, LL_TIM_TRGO_ENABLE); +1434:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM7); +1435:Src/main.c **** /* USER CODE BEGIN TIM7_Init 2 */ +1436:Src/main.c **** +1437:Src/main.c **** /* USER CODE END TIM7_Init 2 */ +1438:Src/main.c **** +1439:Src/main.c **** } +1440:Src/main.c **** +1441:Src/main.c **** /** +1442:Src/main.c **** * @brief TIM8 Initialization Function +1443:Src/main.c **** * @param None +1444:Src/main.c **** * @retval None +1445:Src/main.c **** */ +1446:Src/main.c **** static void MX_TIM8_Init(void) +1447:Src/main.c **** { +1448:Src/main.c **** +1449:Src/main.c **** /* USER CODE BEGIN TIM8_Init 0 */ +1450:Src/main.c **** +1451:Src/main.c **** /* USER CODE END TIM8_Init 0 */ +1452:Src/main.c **** +1453:Src/main.c **** TIM_ClockConfigTypeDef sClockSourceConfig = {0}; +1454:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; +1455:Src/main.c **** +1456:Src/main.c **** /* USER CODE BEGIN TIM8_Init 1 */ +1457:Src/main.c **** +1458:Src/main.c **** /* USER CODE END TIM8_Init 1 */ +1459:Src/main.c **** htim8.Instance = TIM8; +1460:Src/main.c **** htim8.Init.Prescaler = 0; +1461:Src/main.c **** htim8.Init.CounterMode = TIM_COUNTERMODE_UP; +1462:Src/main.c **** htim8.Init.Period = 91; +1463:Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; +1464:Src/main.c **** htim8.Init.RepetitionCounter = 0; +1465:Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; +1466:Src/main.c **** if (HAL_TIM_Base_Init(&htim8) != HAL_OK) +1467:Src/main.c **** { +1468:Src/main.c **** Error_Handler(); +1469:Src/main.c **** } +1470:Src/main.c **** sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; +1471:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) +1472:Src/main.c **** { +1473:Src/main.c **** Error_Handler(); +1474:Src/main.c **** } +1475:Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; +1476:Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; +1477:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; +1478:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) +1479:Src/main.c **** { +1480:Src/main.c **** Error_Handler(); +1481:Src/main.c **** } +1482:Src/main.c **** /* USER CODE BEGIN TIM8_Init 2 */ + ARM GAS /tmp/ccWQNJQt.s page 66 + + +1483:Src/main.c **** +1484:Src/main.c **** /* USER CODE END TIM8_Init 2 */ +1485:Src/main.c **** +1486:Src/main.c **** } +1487:Src/main.c **** +1488:Src/main.c **** /** +1489:Src/main.c **** * @brief TIM10 Initialization Function +1490:Src/main.c **** * @param None +1491:Src/main.c **** * @retval None +1492:Src/main.c **** */ +1493:Src/main.c **** static void MX_TIM10_Init(void) +1494:Src/main.c **** { +1495:Src/main.c **** +1496:Src/main.c **** /* USER CODE BEGIN TIM10_Init 0 */ +1497:Src/main.c **** +1498:Src/main.c **** /* USER CODE END TIM10_Init 0 */ +1499:Src/main.c **** +1500:Src/main.c **** /* USER CODE BEGIN TIM10_Init 1 */ +1501:Src/main.c **** +1502:Src/main.c **** /* USER CODE END TIM10_Init 1 */ +1503:Src/main.c **** htim10.Instance = TIM10; +1504:Src/main.c **** htim10.Init.Prescaler = 183; +1505:Src/main.c **** htim10.Init.CounterMode = TIM_COUNTERMODE_UP; +1506:Src/main.c **** htim10.Init.Period = 9; +1507:Src/main.c **** htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; +1508:Src/main.c **** htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; +1509:Src/main.c **** if (HAL_TIM_Base_Init(&htim10) != HAL_OK) +1510:Src/main.c **** { +1511:Src/main.c **** Error_Handler(); +1512:Src/main.c **** } +1513:Src/main.c **** /* USER CODE BEGIN TIM10_Init 2 */ +1514:Src/main.c **** +1515:Src/main.c **** /* USER CODE END TIM10_Init 2 */ +1516:Src/main.c **** +1517:Src/main.c **** } +1518:Src/main.c **** +1519:Src/main.c **** /** +1520:Src/main.c **** * @brief TIM11 Initialization Function +1521:Src/main.c **** * @param None +1522:Src/main.c **** * @retval None +1523:Src/main.c **** */ +1524:Src/main.c **** static void MX_TIM11_Init(void) +1525:Src/main.c **** { +1526:Src/main.c **** +1527:Src/main.c **** /* USER CODE BEGIN TIM11_Init 0 */ +1528:Src/main.c **** +1529:Src/main.c **** /* USER CODE END TIM11_Init 0 */ +1530:Src/main.c **** +1531:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; +1532:Src/main.c **** +1533:Src/main.c **** /* USER CODE BEGIN TIM11_Init 1 */ +1534:Src/main.c **** +1535:Src/main.c **** /* USER CODE END TIM11_Init 1 */ +1536:Src/main.c **** htim11.Instance = TIM11; +1537:Src/main.c **** htim11.Init.Prescaler = 1; +1538:Src/main.c **** htim11.Init.CounterMode = TIM_COUNTERMODE_UP; +1539:Src/main.c **** htim11.Init.Period = 91; + ARM GAS /tmp/ccWQNJQt.s page 67 + + +1540:Src/main.c **** htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; +1541:Src/main.c **** htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; +1542:Src/main.c **** if (HAL_TIM_Base_Init(&htim11) != HAL_OK) +1543:Src/main.c **** { +1544:Src/main.c **** Error_Handler(); +1545:Src/main.c **** } +1546:Src/main.c **** if (HAL_TIM_PWM_Init(&htim11) != HAL_OK) +1547:Src/main.c **** { +1548:Src/main.c **** Error_Handler(); +1549:Src/main.c **** } +1550:Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1; +1551:Src/main.c **** sConfigOC.Pulse = 91; +1552:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; +1553:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; +1554:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim11, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) +1555:Src/main.c **** { +1556:Src/main.c **** Error_Handler(); +1557:Src/main.c **** } +1558:Src/main.c **** /* USER CODE BEGIN TIM11_Init 2 */ +1559:Src/main.c **** +1560:Src/main.c **** /* USER CODE END TIM11_Init 2 */ +1561:Src/main.c **** HAL_TIM_MspPostInit(&htim11); +1562:Src/main.c **** +1563:Src/main.c **** } +1564:Src/main.c **** +1565:Src/main.c **** /** +1566:Src/main.c **** * @brief UART8 Initialization Function +1567:Src/main.c **** * @param None +1568:Src/main.c **** * @retval None +1569:Src/main.c **** */ +1570:Src/main.c **** static void MX_UART8_Init(void) +1571:Src/main.c **** { +1572:Src/main.c **** +1573:Src/main.c **** /* USER CODE BEGIN UART8_Init 0 */ +1574:Src/main.c **** +1575:Src/main.c **** /* USER CODE END UART8_Init 0 */ +1576:Src/main.c **** +1577:Src/main.c **** /* USER CODE BEGIN UART8_Init 1 */ +1578:Src/main.c **** +1579:Src/main.c **** /* USER CODE END UART8_Init 1 */ +1580:Src/main.c **** huart8.Instance = UART8; +1581:Src/main.c **** huart8.Init.BaudRate = 115200; +1582:Src/main.c **** huart8.Init.WordLength = UART_WORDLENGTH_8B; +1583:Src/main.c **** huart8.Init.StopBits = UART_STOPBITS_1; +1584:Src/main.c **** huart8.Init.Parity = UART_PARITY_NONE; +1585:Src/main.c **** huart8.Init.Mode = UART_MODE_TX_RX; +1586:Src/main.c **** huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; +1587:Src/main.c **** huart8.Init.OverSampling = UART_OVERSAMPLING_16; +1588:Src/main.c **** huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; +1589:Src/main.c **** huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; +1590:Src/main.c **** if (HAL_UART_Init(&huart8) != HAL_OK) +1591:Src/main.c **** { +1592:Src/main.c **** Error_Handler(); +1593:Src/main.c **** } +1594:Src/main.c **** /* USER CODE BEGIN UART8_Init 2 */ +1595:Src/main.c **** +1596:Src/main.c **** /* USER CODE END UART8_Init 2 */ + ARM GAS /tmp/ccWQNJQt.s page 68 + + +1597:Src/main.c **** +1598:Src/main.c **** } +1599:Src/main.c **** +1600:Src/main.c **** /** +1601:Src/main.c **** * @brief USART1 Initialization Function +1602:Src/main.c **** * @param None +1603:Src/main.c **** * @retval None +1604:Src/main.c **** */ +1605:Src/main.c **** static void MX_USART1_UART_Init(void) +1606:Src/main.c **** { +1607:Src/main.c **** +1608:Src/main.c **** /* USER CODE BEGIN USART1_Init 0 */ +1609:Src/main.c **** +1610:Src/main.c **** /* USER CODE END USART1_Init 0 */ +1611:Src/main.c **** +1612:Src/main.c **** LL_USART_InitTypeDef USART_InitStruct = {0}; +1613:Src/main.c **** +1614:Src/main.c **** LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; +1615:Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; +1616:Src/main.c **** +1617:Src/main.c **** /** Initializes the peripherals clock +1618:Src/main.c **** */ +1619:Src/main.c **** PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; +1620:Src/main.c **** PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; +1621:Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) +1622:Src/main.c **** { +1623:Src/main.c **** Error_Handler(); +1624:Src/main.c **** } +1625:Src/main.c **** +1626:Src/main.c **** /* Peripheral clock enable */ +1627:Src/main.c **** LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1); +1628:Src/main.c **** +1629:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA); +1630:Src/main.c **** /**USART1 GPIO Configuration +1631:Src/main.c **** PA9 ------> USART1_TX +1632:Src/main.c **** PA10 ------> USART1_RX +1633:Src/main.c **** */ +1634:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_9; +1635:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; +1636:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; +1637:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; +1638:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; +1639:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; +1640:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); +1641:Src/main.c **** +1642:Src/main.c **** GPIO_InitStruct.Pin = LL_GPIO_PIN_10; +1643:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; +1644:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; +1645:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; +1646:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; +1647:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; +1648:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); +1649:Src/main.c **** +1650:Src/main.c **** /* USART1 DMA Init */ +1651:Src/main.c **** +1652:Src/main.c **** /* USART1_TX Init */ +1653:Src/main.c **** LL_DMA_SetChannelSelection(DMA2, LL_DMA_STREAM_7, LL_DMA_CHANNEL_4); + ARM GAS /tmp/ccWQNJQt.s page 69 + + +1654:Src/main.c **** +1655:Src/main.c **** LL_DMA_SetDataTransferDirection(DMA2, LL_DMA_STREAM_7, LL_DMA_DIRECTION_MEMORY_TO_PERIPH); +1656:Src/main.c **** +1657:Src/main.c **** LL_DMA_SetStreamPriorityLevel(DMA2, LL_DMA_STREAM_7, LL_DMA_PRIORITY_VERYHIGH); +1658:Src/main.c **** +1659:Src/main.c **** LL_DMA_SetMode(DMA2, LL_DMA_STREAM_7, LL_DMA_MODE_NORMAL); +1660:Src/main.c **** +1661:Src/main.c **** LL_DMA_SetPeriphIncMode(DMA2, LL_DMA_STREAM_7, LL_DMA_PERIPH_NOINCREMENT); +1662:Src/main.c **** +1663:Src/main.c **** LL_DMA_SetMemoryIncMode(DMA2, LL_DMA_STREAM_7, LL_DMA_MEMORY_INCREMENT); +1664:Src/main.c **** +1665:Src/main.c **** LL_DMA_SetPeriphSize(DMA2, LL_DMA_STREAM_7, LL_DMA_PDATAALIGN_BYTE); +1666:Src/main.c **** +1667:Src/main.c **** LL_DMA_SetMemorySize(DMA2, LL_DMA_STREAM_7, LL_DMA_MDATAALIGN_BYTE); +1668:Src/main.c **** +1669:Src/main.c **** LL_DMA_DisableFifoMode(DMA2, LL_DMA_STREAM_7); +1670:Src/main.c **** +1671:Src/main.c **** /* USART1 interrupt Init */ +1672:Src/main.c **** NVIC_SetPriority(USART1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); +1673:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn); +1674:Src/main.c **** +1675:Src/main.c **** /* USER CODE BEGIN USART1_Init 1 */ +1676:Src/main.c **** +1677:Src/main.c **** /* USER CODE END USART1_Init 1 */ +1678:Src/main.c **** USART_InitStruct.BaudRate = 115200; +1679:Src/main.c **** USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; +1680:Src/main.c **** USART_InitStruct.StopBits = LL_USART_STOPBITS_1; +1681:Src/main.c **** USART_InitStruct.Parity = LL_USART_PARITY_NONE; +1682:Src/main.c **** USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; +1683:Src/main.c **** USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; +1684:Src/main.c **** USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; +1685:Src/main.c **** LL_USART_Init(USART1, &USART_InitStruct); +1686:Src/main.c **** LL_USART_ConfigAsyncMode(USART1); +1687:Src/main.c **** LL_USART_Enable(USART1); +1688:Src/main.c **** /* USER CODE BEGIN USART1_Init 2 */ +1689:Src/main.c **** +1690:Src/main.c **** /* USER CODE END USART1_Init 2 */ +1691:Src/main.c **** +1692:Src/main.c **** } +1693:Src/main.c **** +1694:Src/main.c **** /** +1695:Src/main.c **** * Enable DMA controller clock +1696:Src/main.c **** */ +1697:Src/main.c **** static void MX_DMA_Init(void) +1698:Src/main.c **** { + 144 .loc 1 1698 1 is_stmt 1 view -0 + 145 .cfi_startproc + 146 @ args = 0, pretend = 0, frame = 8 + 147 @ frame_needed = 0, uses_anonymous_args = 0 + 148 0000 00B5 push {lr} + 149 .LCFI1: + 150 .cfi_def_cfa_offset 4 + 151 .cfi_offset 14, -4 + 152 0002 83B0 sub sp, sp, #12 + 153 .LCFI2: + 154 .cfi_def_cfa_offset 16 +1699:Src/main.c **** + ARM GAS /tmp/ccWQNJQt.s page 70 + + +1700:Src/main.c **** /* Init with LL driver */ +1701:Src/main.c **** /* DMA controller clock enable */ +1702:Src/main.c **** LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2); + 155 .loc 1 1702 3 view .LVU37 + 156 .LVL8: + 157 .LBB294: + 158 .LBI294: + 159 .file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @file stm32f7xx_ll_bus.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @verbatim + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @attention + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * Copyright (c) 2017 STMicroelectronics. + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * All rights reserved. + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * This software is licensed under terms that can be found in the LICENSE file in + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * the root directory of this software component. + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifndef __STM32F7xx_LL_BUS_H + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define __STM32F7xx_LL_BUS_H + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifdef __cplusplus + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** extern "C" { + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #include "stm32f7xx.h" + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @addtogroup STM32F7xx_LL_Driver + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + ARM GAS /tmp/ccWQNJQt.s page 71 + + + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC) + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOJ) + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOJ */ + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOK) + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOK */ + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DTCMRAM RCC_AHB1ENR_DTCMRAMEN + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DMA2D) + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DMA2D */ + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(ETH) + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* ETH */ + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_AXI RCC_AHB1LPENR_AXILPEN + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + ARM GAS /tmp/ccWQNJQt.s page 72 + + + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DCMI) + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DCMI */ + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(JPEG) + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_JPEG RCC_AHB2ENR_JPEGEN + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* JPEG */ + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CRYP) + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CRYP */ + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(AES) + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* AES */ + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(HASH) + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* HASH */ + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPDIFRX) + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPDIFRX */ + ARM GAS /tmp/ccWQNJQt.s page 73 + + + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(I2C4) + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C4 RCC_APB1ENR_I2C4EN + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* I2C4 */ + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN2) + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN2 */ + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN3) + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN3 */ + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CEC) + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CEC */ + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC_APB1ENR_RTCEN) + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCEN + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* RCC_APB1ENR_RTCEN */ + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SDMMC2) + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC2 RCC_APB2ENR_SDMMC2EN + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SDMMC2 */ + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPI6) + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPI6 */ + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN + ARM GAS /tmp/ccWQNJQt.s page 74 + + + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(LTDC) + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* LTDC */ + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DSI) + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DSI */ + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DFSDM1_Channel0) + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DFSDM1_Channel0 */ + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(MDIOS) + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_MDIO RCC_APB2ENR_MDIOEN + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* MDIOS */ + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(USB_HS_PHYC) + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_OTGPHYC RCC_APB2ENR_OTGPHYCEN + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* USB_HS_PHYC */ + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_EnableClock\n + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n + ARM GAS /tmp/ccWQNJQt.s page 75 + + + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 160 .loc 3 309 22 view .LVU38 + 161 .LBB295: + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 162 .loc 3 311 3 view .LVU39 + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); + 163 .loc 3 312 3 view .LVU40 + 164 0004 0D4B ldr r3, .L10 + 165 0006 1A6B ldr r2, [r3, #48] + 166 0008 42F48002 orr r2, r2, #4194304 + 167 000c 1A63 str r2, [r3, #48] + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + 168 .loc 3 314 3 view .LVU41 + 169 .loc 3 314 12 is_stmt 0 view .LVU42 + 170 000e 1B6B ldr r3, [r3, #48] + 171 0010 03F48003 and r3, r3, #4194304 + 172 .loc 3 314 10 view .LVU43 + 173 0014 0193 str r3, [sp, #4] + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 174 .loc 3 315 3 is_stmt 1 view .LVU44 + 175 0016 019B ldr r3, [sp, #4] + 176 .LVL9: + 177 .loc 3 315 3 is_stmt 0 view .LVU45 + 178 .LBE295: + ARM GAS /tmp/ccWQNJQt.s page 76 + + + 179 .LBE294: +1703:Src/main.c **** +1704:Src/main.c **** /* DMA interrupt init */ +1705:Src/main.c **** /* DMA2_Stream7_IRQn interrupt configuration */ +1706:Src/main.c **** NVIC_SetPriority(DMA2_Stream7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + 180 .loc 1 1706 3 is_stmt 1 view .LVU46 + 181 .LBB296: + 182 .LBI296: +1884:Drivers/CMSIS/Include/core_cm7.h **** { + 183 .loc 2 1884 26 view .LVU47 + 184 .LBB297: +1886:Drivers/CMSIS/Include/core_cm7.h **** } + 185 .loc 2 1886 3 view .LVU48 +1886:Drivers/CMSIS/Include/core_cm7.h **** } + 186 .loc 2 1886 26 is_stmt 0 view .LVU49 + 187 0018 094B ldr r3, .L10+4 + 188 001a D868 ldr r0, [r3, #12] + 189 .LBE297: + 190 .LBE296: + 191 .loc 1 1706 3 discriminator 1 view .LVU50 + 192 001c 0022 movs r2, #0 + 193 001e 1146 mov r1, r2 + 194 0020 C0F30220 ubfx r0, r0, #8, #3 + 195 0024 FFF7FEFF bl NVIC_EncodePriority + 196 .LVL10: + 197 .LBB298: + 198 .LBI298: +2024:Drivers/CMSIS/Include/core_cm7.h **** { + 199 .loc 2 2024 22 is_stmt 1 view .LVU51 + 200 .LBB299: +2026:Drivers/CMSIS/Include/core_cm7.h **** { + 201 .loc 2 2026 3 view .LVU52 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 202 .loc 2 2028 5 view .LVU53 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 203 .loc 2 2028 49 is_stmt 0 view .LVU54 + 204 0028 0001 lsls r0, r0, #4 + 205 .LVL11: +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 206 .loc 2 2028 49 view .LVU55 + 207 002a C0B2 uxtb r0, r0 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 208 .loc 2 2028 47 view .LVU56 + 209 002c 054B ldr r3, .L10+8 + 210 002e 83F84603 strb r0, [r3, #838] + 211 .LVL12: +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 212 .loc 2 2028 47 view .LVU57 + 213 .LBE299: + 214 .LBE298: +1707:Src/main.c **** NVIC_EnableIRQ(DMA2_Stream7_IRQn); + 215 .loc 1 1707 3 is_stmt 1 view .LVU58 + 216 .LBB300: + 217 .LBI300: +1896:Drivers/CMSIS/Include/core_cm7.h **** { + 218 .loc 2 1896 22 view .LVU59 + 219 .LBB301: + ARM GAS /tmp/ccWQNJQt.s page 77 + + +1898:Drivers/CMSIS/Include/core_cm7.h **** { + 220 .loc 2 1898 3 view .LVU60 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 221 .loc 2 1900 5 view .LVU61 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 222 .loc 2 1900 43 is_stmt 0 view .LVU62 + 223 0032 4022 movs r2, #64 + 224 0034 9A60 str r2, [r3, #8] + 225 .LVL13: +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 226 .loc 2 1900 43 view .LVU63 + 227 .LBE301: + 228 .LBE300: +1708:Src/main.c **** +1709:Src/main.c **** } + 229 .loc 1 1709 1 view .LVU64 + 230 0036 03B0 add sp, sp, #12 + 231 .LCFI3: + 232 .cfi_def_cfa_offset 4 + 233 @ sp needed + 234 0038 5DF804FB ldr pc, [sp], #4 + 235 .L11: + 236 .align 2 + 237 .L10: + 238 003c 00380240 .word 1073887232 + 239 0040 00ED00E0 .word -536810240 + 240 0044 00E100E0 .word -536813312 + 241 .cfi_endproc + 242 .LFE1205: + 244 .section .text.Decode_task,"ax",%progbits + 245 .align 1 + 246 .syntax unified + 247 .thumb + 248 .thumb_func + 250 Decode_task: + 251 .LVL14: + 252 .LFB1209: +1710:Src/main.c **** +1711:Src/main.c **** /** +1712:Src/main.c **** * @brief GPIO Initialization Function +1713:Src/main.c **** * @param None +1714:Src/main.c **** * @retval None +1715:Src/main.c **** */ +1716:Src/main.c **** static void MX_GPIO_Init(void) +1717:Src/main.c **** { +1718:Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; +1719:Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */ +1720:Src/main.c **** /* USER CODE END MX_GPIO_Init_1 */ +1721:Src/main.c **** +1722:Src/main.c **** /* GPIO Ports Clock Enable */ +1723:Src/main.c **** __HAL_RCC_GPIOF_CLK_ENABLE(); +1724:Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); +1725:Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); +1726:Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); +1727:Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); +1728:Src/main.c **** __HAL_RCC_GPIOE_CLK_ENABLE(); +1729:Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); + ARM GAS /tmp/ccWQNJQt.s page 78 + + +1730:Src/main.c **** __HAL_RCC_GPIOG_CLK_ENABLE(); +1731:Src/main.c **** +1732:Src/main.c **** /*Configure GPIO pin Output Level */ +1733:Src/main.c **** HAL_GPIO_WritePin(GPIOF, ADC_MPD2_CS_Pin|SPI5_CNV_Pin|ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET); +1734:Src/main.c **** +1735:Src/main.c **** /*Configure GPIO pin Output Level */ +1736:Src/main.c **** HAL_GPIO_WritePin(GPIOC, EN_5V2_Pin|EN_5V1_Pin|LD2_EN_Pin|TEC2_PD_Pin, GPIO_PIN_RESET); +1737:Src/main.c **** +1738:Src/main.c **** /*Configure GPIO pin Output Level */ +1739:Src/main.c **** HAL_GPIO_WritePin(GPIOA, TECEN1_Pin|TECEN2_Pin|REF2_ON_Pin|DAC_LD2_CS_Pin, GPIO_PIN_RESET); +1740:Src/main.c **** +1741:Src/main.c **** /*Configure GPIO pin Output Level */ +1742:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET); +1743:Src/main.c **** +1744:Src/main.c **** /*Configure GPIO pin Output Level */ +1745:Src/main.c **** HAL_GPIO_WritePin(GPIOE, ADC_MPD1_CS_Pin|ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET); +1746:Src/main.c **** +1747:Src/main.c **** /*Configure GPIO pin Output Level */ +1748:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET); +1749:Src/main.c **** +1750:Src/main.c **** /*Configure GPIO pin Output Level */ +1751:Src/main.c **** HAL_GPIO_WritePin(GPIOB, REF0_EN_Pin|TEC1_PD_Pin|DAC_LD1_CS_Pin|OUT_6_Pin +1752:Src/main.c **** |OUT_7_Pin|OUT_8_Pin|OUT_9_Pin, GPIO_PIN_RESET); +1753:Src/main.c **** +1754:Src/main.c **** /*Configure GPIO pin Output Level */ +1755:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET); +1756:Src/main.c **** +1757:Src/main.c **** /*Configure GPIO pin Output Level */ +1758:Src/main.c **** HAL_GPIO_WritePin(GPIOD, LD1_EN_Pin|TEST_01_Pin|GPIO_PIN_7, GPIO_PIN_RESET); +1759:Src/main.c **** +1760:Src/main.c **** /*Configure GPIO pin Output Level */ +1761:Src/main.c **** HAL_GPIO_WritePin(GPIOG, GPIO_PIN_9|OUT_0_Pin|OUT_1_Pin|OUT_2_Pin +1762:Src/main.c **** |OUT_3_Pin|OUT_4_Pin|OUT_5_Pin, GPIO_PIN_RESET); +1763:Src/main.c **** +1764:Src/main.c **** /*Configure GPIO pins : INP_0_Pin INP_1_Pin */ +1765:Src/main.c **** GPIO_InitStruct.Pin = INP_0_Pin|INP_1_Pin; +1766:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; +1767:Src/main.c **** GPIO_InitStruct.Pull = GPIO_PULLUP; +1768:Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); +1769:Src/main.c **** +1770:Src/main.c **** /*Configure GPIO pins : ADC_MPD2_CS_Pin SPI5_CNV_Pin ADC_ThrLD2_CS_Pin */ +1771:Src/main.c **** GPIO_InitStruct.Pin = ADC_MPD2_CS_Pin|SPI5_CNV_Pin|ADC_ThrLD2_CS_Pin; +1772:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; +1773:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; +1774:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; +1775:Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); +1776:Src/main.c **** +1777:Src/main.c **** /*Configure GPIO pins : EN_5V2_Pin LD2_EN_Pin TEC2_PD_Pin */ +1778:Src/main.c **** GPIO_InitStruct.Pin = EN_5V2_Pin|LD2_EN_Pin|TEC2_PD_Pin; +1779:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; +1780:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; +1781:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; +1782:Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); +1783:Src/main.c **** +1784:Src/main.c **** /*Configure GPIO pin : EN_5V1_Pin */ +1785:Src/main.c **** GPIO_InitStruct.Pin = EN_5V1_Pin; +1786:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + ARM GAS /tmp/ccWQNJQt.s page 79 + + +1787:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; +1788:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; +1789:Src/main.c **** HAL_GPIO_Init(EN_5V1_GPIO_Port, &GPIO_InitStruct); +1790:Src/main.c **** +1791:Src/main.c **** /*Configure GPIO pins : TECEN1_Pin TECEN2_Pin REF2_ON_Pin DAC_TEC2_CS_Pin +1792:Src/main.c **** DAC_LD2_CS_Pin */ +1793:Src/main.c **** GPIO_InitStruct.Pin = TECEN1_Pin|TECEN2_Pin|REF2_ON_Pin|DAC_TEC2_CS_Pin +1794:Src/main.c **** |DAC_LD2_CS_Pin; +1795:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; +1796:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; +1797:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; +1798:Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); +1799:Src/main.c **** +1800:Src/main.c **** /*Configure GPIO pins : TEC2_FLAG1_Pin TEC2_FLAG2_Pin TEC1_FLAG1_Pin TEC1_FLAG2_Pin */ +1801:Src/main.c **** GPIO_InitStruct.Pin = TEC2_FLAG1_Pin|TEC2_FLAG2_Pin|TEC1_FLAG1_Pin|TEC1_FLAG2_Pin; +1802:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; +1803:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; +1804:Src/main.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); +1805:Src/main.c **** +1806:Src/main.c **** /*Configure GPIO pins : ADC_MPD1_CS_Pin ADC_ThrLD1_CS_Pin */ +1807:Src/main.c **** GPIO_InitStruct.Pin = ADC_MPD1_CS_Pin|ADC_ThrLD1_CS_Pin; +1808:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; +1809:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; +1810:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; +1811:Src/main.c **** HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); +1812:Src/main.c **** +1813:Src/main.c **** /*Configure GPIO pin : SPI4_CNV_Pin */ +1814:Src/main.c **** GPIO_InitStruct.Pin = SPI4_CNV_Pin; +1815:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; +1816:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; +1817:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; +1818:Src/main.c **** HAL_GPIO_Init(SPI4_CNV_GPIO_Port, &GPIO_InitStruct); +1819:Src/main.c **** +1820:Src/main.c **** /*Configure GPIO pins : REF0_EN_Pin TEC1_PD_Pin DAC_TEC1_CS_Pin DAC_LD1_CS_Pin +1821:Src/main.c **** OUT_6_Pin OUT_7_Pin OUT_8_Pin OUT_9_Pin */ +1822:Src/main.c **** GPIO_InitStruct.Pin = REF0_EN_Pin|TEC1_PD_Pin|DAC_TEC1_CS_Pin|DAC_LD1_CS_Pin +1823:Src/main.c **** |OUT_6_Pin|OUT_7_Pin|OUT_8_Pin|OUT_9_Pin; +1824:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; +1825:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; +1826:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; +1827:Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); +1828:Src/main.c **** +1829:Src/main.c **** /*Configure GPIO pins : LD1_EN_Pin TEST_01_Pin PD7 */ +1830:Src/main.c **** GPIO_InitStruct.Pin = LD1_EN_Pin|TEST_01_Pin|GPIO_PIN_7; +1831:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; +1832:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; +1833:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; +1834:Src/main.c **** HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); +1835:Src/main.c **** +1836:Src/main.c **** /*Configure GPIO pin : USB_FLAG_Pin */ +1837:Src/main.c **** GPIO_InitStruct.Pin = USB_FLAG_Pin; +1838:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; +1839:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; +1840:Src/main.c **** HAL_GPIO_Init(USB_FLAG_GPIO_Port, &GPIO_InitStruct); +1841:Src/main.c **** +1842:Src/main.c **** /*Configure GPIO pin : SDMMC1_EN_Pin */ +1843:Src/main.c **** GPIO_InitStruct.Pin = SDMMC1_EN_Pin; + ARM GAS /tmp/ccWQNJQt.s page 80 + + +1844:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; +1845:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; +1846:Src/main.c **** HAL_GPIO_Init(SDMMC1_EN_GPIO_Port, &GPIO_InitStruct); +1847:Src/main.c **** +1848:Src/main.c **** /*Configure GPIO pins : PG9 OUT_0_Pin OUT_1_Pin OUT_2_Pin +1849:Src/main.c **** OUT_3_Pin OUT_4_Pin OUT_5_Pin */ +1850:Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_9|OUT_0_Pin|OUT_1_Pin|OUT_2_Pin +1851:Src/main.c **** |OUT_3_Pin|OUT_4_Pin|OUT_5_Pin; +1852:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; +1853:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; +1854:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; +1855:Src/main.c **** HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); +1856:Src/main.c **** +1857:Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_2 */ +1858:Src/main.c **** /* USER CODE END MX_GPIO_Init_2 */ +1859:Src/main.c **** } +1860:Src/main.c **** +1861:Src/main.c **** /* USER CODE BEGIN 4 */ +1862:Src/main.c **** +1863:Src/main.c **** //void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { +1864:Src/main.c **** +1865:Src/main.c **** // UART_transmission_request = NO_MESS; +1866:Src/main.c **** +1867:Src/main.c **** //} +1868:Src/main.c **** +1869:Src/main.c **** static void Init_params(void) +1870:Src/main.c **** { +1871:Src/main.c **** TO6 = 0; +1872:Src/main.c **** TO7 = 0; +1873:Src/main.c **** TO7_before = 0; +1874:Src/main.c **** TO6_before = 0; +1875:Src/main.c **** TO6_uart = 0; +1876:Src/main.c **** flg_tmt = 0; +1877:Src/main.c **** UART_rec_incr = 0; +1878:Src/main.c **** fgoto = 0; +1879:Src/main.c **** sizeoffile = 0; +1880:Src/main.c **** u_tx_flg = 0; +1881:Src/main.c **** u_rx_flg = 0; +1882:Src/main.c **** //State_Data[0]=0; +1883:Src/main.c **** //State_Data[1]=0;//All OK! +1884:Src/main.c **** for (uint16_t i=0; iWORK_EN = ((uint8_t)((*temp2)>>0))&0x01; +2036:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; +2037:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; +2038:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; +2039:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; +2040:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; +2041:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; +2042:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; +2043:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; +2044:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; +2045:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; +2046:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; +2047:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; +2048:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; +2049:Src/main.c **** +2050:Src/main.c **** temp2++; +2051:Src/main.c **** LD1_curr_setup->LD_TEMP = (uint16_t)(*temp2); +2052:Src/main.c **** temp2++; +2053:Src/main.c **** LD2_curr_setup->LD_TEMP = (uint16_t)(*temp2); +2054:Src/main.c **** temp2++; +2055:Src/main.c **** temp2++; +2056:Src/main.c **** temp2++; +2057:Src/main.c **** Curr_setup->AVERAGES = (uint16_t)(*temp2); +2058:Src/main.c **** temp2++; +2059:Src/main.c **** LD1_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint +2060:Src/main.c **** temp2++; +2061:Src/main.c **** LD1_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint +2062:Src/main.c **** temp2++; +2063:Src/main.c **** LD2_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint +2064:Src/main.c **** temp2++; +2065:Src/main.c **** LD2_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint +2066:Src/main.c **** temp2++; +2067:Src/main.c **** Long_Data[13] = (uint16_t)(*temp2);//Message ID +2068:Src/main.c **** temp2++; +2069:Src/main.c **** LD1_curr_setup->CURRENT = (uint16_t)(*temp2); +2070:Src/main.c **** temp2++; +2071:Src/main.c **** LD2_curr_setup->CURRENT = (uint16_t)(*temp2); + ARM GAS /tmp/ccWQNJQt.s page 84 + + +2072:Src/main.c **** temp2++; +2073:Src/main.c **** +2074:Src/main.c **** if (Curr_setup->U5V1_EN) +2075:Src/main.c **** { +2076:Src/main.c **** HAL_GPIO_WritePin(EN_5V1_GPIO_Port, EN_5V1_Pin, GPIO_PIN_SET); +2077:Src/main.c **** } +2078:Src/main.c **** else +2079:Src/main.c **** { +2080:Src/main.c **** HAL_GPIO_WritePin(EN_5V1_GPIO_Port, EN_5V1_Pin, GPIO_PIN_RESET); +2081:Src/main.c **** } +2082:Src/main.c **** +2083:Src/main.c **** if (Curr_setup->U5V2_EN) +2084:Src/main.c **** { +2085:Src/main.c **** HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_SET); +2086:Src/main.c **** } +2087:Src/main.c **** else +2088:Src/main.c **** { +2089:Src/main.c **** HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_RESET); +2090:Src/main.c **** } +2091:Src/main.c **** +2092:Src/main.c **** if (Curr_setup->LD1_EN) +2093:Src/main.c **** { +2094:Src/main.c **** HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_SET); +2095:Src/main.c **** //LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC +2096:Src/main.c **** } +2097:Src/main.c **** else +2098:Src/main.c **** { +2099:Src/main.c **** HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_RESET); +2100:Src/main.c **** //LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC +2101:Src/main.c **** } +2102:Src/main.c **** +2103:Src/main.c **** if (Curr_setup->LD2_EN) +2104:Src/main.c **** { +2105:Src/main.c **** HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_SET); +2106:Src/main.c **** //LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC +2107:Src/main.c **** } +2108:Src/main.c **** else +2109:Src/main.c **** { +2110:Src/main.c **** HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_RESET); +2111:Src/main.c **** //LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC +2112:Src/main.c **** } +2113:Src/main.c **** +2114:Src/main.c **** if (Curr_setup->REF1_EN) +2115:Src/main.c **** { +2116:Src/main.c **** HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_SET); +2117:Src/main.c **** } +2118:Src/main.c **** else +2119:Src/main.c **** { +2120:Src/main.c **** HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_RESET); +2121:Src/main.c **** } +2122:Src/main.c **** +2123:Src/main.c **** if (Curr_setup->REF2_EN) +2124:Src/main.c **** { +2125:Src/main.c **** HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_SET); +2126:Src/main.c **** } +2127:Src/main.c **** else +2128:Src/main.c **** { + ARM GAS /tmp/ccWQNJQt.s page 85 + + +2129:Src/main.c **** HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_RESET); +2130:Src/main.c **** } +2131:Src/main.c **** +2132:Src/main.c **** if ((Curr_setup->TS1_EN)&&(Curr_setup->TEC1_EN)) +2133:Src/main.c **** { +2134:Src/main.c **** Set_LTEC(3,32767); +2135:Src/main.c **** Set_LTEC(3,32767); +2136:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_SET); +2137:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_SET); +2138:Src/main.c **** } +2139:Src/main.c **** else +2140:Src/main.c **** { +2141:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_RESET); +2142:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_RESET); +2143:Src/main.c **** } +2144:Src/main.c **** +2145:Src/main.c **** if ((Curr_setup->TS2_EN)&&(Curr_setup->TEC2_EN)) +2146:Src/main.c **** { +2147:Src/main.c **** Set_LTEC(4,32767); +2148:Src/main.c **** Set_LTEC(4,32767); +2149:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_SET); +2150:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_SET); +2151:Src/main.c **** } +2152:Src/main.c **** else +2153:Src/main.c **** { +2154:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_RESET); +2155:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_RESET); +2156:Src/main.c **** } +2157:Src/main.c **** +2158:Src/main.c **** if (Curr_setup->PI1_RD==0) +2159:Src/main.c **** { +2160:Src/main.c **** LD1_curr_setup->P_coef_temp = 10; +2161:Src/main.c **** LD1_curr_setup->I_coef_temp = 0.01; +2162:Src/main.c **** } +2163:Src/main.c **** +2164:Src/main.c **** if (Curr_setup->PI2_RD==0) +2165:Src/main.c **** { +2166:Src/main.c **** LD2_curr_setup->P_coef_temp = 10; +2167:Src/main.c **** LD2_curr_setup->I_coef_temp = 0.01; +2168:Src/main.c **** } +2169:Src/main.c **** } +2170:Src/main.c **** +2171:Src/main.c **** static void Decode_task(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ +2172:Src/main.c **** { + 253 .loc 1 2172 1 is_stmt 1 view -0 + 254 .cfi_startproc + 255 @ args = 0, pretend = 0, frame = 8 + 256 @ frame_needed = 0, uses_anonymous_args = 0 + 257 @ link register save eliminated. + 258 .loc 1 2172 1 is_stmt 0 view .LVU66 + 259 0000 82B0 sub sp, sp, #8 + 260 .LCFI4: + 261 .cfi_def_cfa_offset 8 +2173:Src/main.c **** uint16_t *temp2; + 262 .loc 1 2173 2 is_stmt 1 view .LVU67 +2174:Src/main.c **** +2175:Src/main.c **** temp2 = (uint16_t *)Command; + ARM GAS /tmp/ccWQNJQt.s page 86 + + + 263 .loc 1 2175 2 view .LVU68 + 264 .LVL15: +2176:Src/main.c **** Curr_setup->WORK_EN = ((uint8_t)((*temp2)>>0))&0x01; + 265 .loc 1 2176 2 view .LVU69 + 266 .loc 1 2176 36 is_stmt 0 view .LVU70 + 267 0002 0288 ldrh r2, [r0] + 268 .LVL16: + 269 .loc 1 2176 48 view .LVU71 + 270 0004 02F00102 and r2, r2, #1 + 271 .loc 1 2176 22 view .LVU72 + 272 0008 1A70 strb r2, [r3] +2177:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; + 273 .loc 1 2177 2 is_stmt 1 view .LVU73 + 274 .loc 1 2177 36 is_stmt 0 view .LVU74 + 275 000a 0288 ldrh r2, [r0] + 276 .loc 1 2177 48 view .LVU75 + 277 000c C2F34002 ubfx r2, r2, #1, #1 + 278 .loc 1 2177 22 view .LVU76 + 279 0010 5A70 strb r2, [r3, #1] +2178:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; + 280 .loc 1 2178 2 is_stmt 1 view .LVU77 + 281 .loc 1 2178 36 is_stmt 0 view .LVU78 + 282 0012 0288 ldrh r2, [r0] + 283 .loc 1 2178 48 view .LVU79 + 284 0014 C2F38002 ubfx r2, r2, #2, #1 + 285 .loc 1 2178 22 view .LVU80 + 286 0018 9A70 strb r2, [r3, #2] +2179:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; + 287 .loc 1 2179 2 is_stmt 1 view .LVU81 + 288 .loc 1 2179 35 is_stmt 0 view .LVU82 + 289 001a 0288 ldrh r2, [r0] + 290 .loc 1 2179 47 view .LVU83 + 291 001c C2F3C002 ubfx r2, r2, #3, #1 + 292 .loc 1 2179 21 view .LVU84 + 293 0020 DA70 strb r2, [r3, #3] +2180:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; + 294 .loc 1 2180 2 is_stmt 1 view .LVU85 + 295 .loc 1 2180 35 is_stmt 0 view .LVU86 + 296 0022 0288 ldrh r2, [r0] + 297 .loc 1 2180 47 view .LVU87 + 298 0024 C2F30012 ubfx r2, r2, #4, #1 + 299 .loc 1 2180 21 view .LVU88 + 300 0028 1A71 strb r2, [r3, #4] +2181:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; + 301 .loc 1 2181 2 is_stmt 1 view .LVU89 + 302 .loc 1 2181 36 is_stmt 0 view .LVU90 + 303 002a 0288 ldrh r2, [r0] + 304 .loc 1 2181 48 view .LVU91 + 305 002c C2F34012 ubfx r2, r2, #5, #1 + 306 .loc 1 2181 22 view .LVU92 + 307 0030 5A71 strb r2, [r3, #5] +2182:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; + 308 .loc 1 2182 2 is_stmt 1 view .LVU93 + 309 .loc 1 2182 36 is_stmt 0 view .LVU94 + 310 0032 0288 ldrh r2, [r0] + 311 .loc 1 2182 48 view .LVU95 + 312 0034 C2F38012 ubfx r2, r2, #6, #1 + ARM GAS /tmp/ccWQNJQt.s page 87 + + + 313 .loc 1 2182 22 view .LVU96 + 314 0038 9A71 strb r2, [r3, #6] +2183:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; + 315 .loc 1 2183 2 is_stmt 1 view .LVU97 + 316 .loc 1 2183 36 is_stmt 0 view .LVU98 + 317 003a 0288 ldrh r2, [r0] + 318 .loc 1 2183 48 view .LVU99 + 319 003c C2F3C012 ubfx r2, r2, #7, #1 + 320 .loc 1 2183 22 view .LVU100 + 321 0040 DA71 strb r2, [r3, #7] +2184:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; + 322 .loc 1 2184 2 is_stmt 1 view .LVU101 + 323 .loc 1 2184 36 is_stmt 0 view .LVU102 + 324 0042 0288 ldrh r2, [r0] + 325 .loc 1 2184 48 view .LVU103 + 326 0044 C2F30022 ubfx r2, r2, #8, #1 + 327 .loc 1 2184 22 view .LVU104 + 328 0048 1A72 strb r2, [r3, #8] +2185:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; + 329 .loc 1 2185 2 is_stmt 1 view .LVU105 + 330 .loc 1 2185 35 is_stmt 0 view .LVU106 + 331 004a 0288 ldrh r2, [r0] + 332 .loc 1 2185 47 view .LVU107 + 333 004c C2F34022 ubfx r2, r2, #9, #1 + 334 .loc 1 2185 21 view .LVU108 + 335 0050 5A72 strb r2, [r3, #9] +2186:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; + 336 .loc 1 2186 2 is_stmt 1 view .LVU109 + 337 .loc 1 2186 35 is_stmt 0 view .LVU110 + 338 0052 0288 ldrh r2, [r0] + 339 .loc 1 2186 48 view .LVU111 + 340 0054 C2F38022 ubfx r2, r2, #10, #1 + 341 .loc 1 2186 21 view .LVU112 + 342 0058 9A72 strb r2, [r3, #10] +2187:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; + 343 .loc 1 2187 2 is_stmt 1 view .LVU113 + 344 .loc 1 2187 34 is_stmt 0 view .LVU114 + 345 005a 0288 ldrh r2, [r0] + 346 .loc 1 2187 47 view .LVU115 + 347 005c C2F3C022 ubfx r2, r2, #11, #1 + 348 .loc 1 2187 20 view .LVU116 + 349 0060 DA72 strb r2, [r3, #11] +2188:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; + 350 .loc 1 2188 2 is_stmt 1 view .LVU117 + 351 .loc 1 2188 35 is_stmt 0 view .LVU118 + 352 0062 0288 ldrh r2, [r0] + 353 .loc 1 2188 48 view .LVU119 + 354 0064 C2F30032 ubfx r2, r2, #12, #1 + 355 .loc 1 2188 21 view .LVU120 + 356 0068 1A73 strb r2, [r3, #12] +2189:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; + 357 .loc 1 2189 2 is_stmt 1 view .LVU121 + 358 .loc 1 2189 35 is_stmt 0 view .LVU122 + 359 006a 0288 ldrh r2, [r0] + 360 .loc 1 2189 48 view .LVU123 + 361 006c C2F34032 ubfx r2, r2, #13, #1 + 362 .loc 1 2189 21 view .LVU124 + ARM GAS /tmp/ccWQNJQt.s page 88 + + + 363 0070 5A73 strb r2, [r3, #13] +2190:Src/main.c **** +2191:Src/main.c **** temp2++; + 364 .loc 1 2191 2 is_stmt 1 view .LVU125 + 365 .LVL17: +2192:Src/main.c **** task.task_type = (uint8_t)(*temp2); temp2++; + 366 .loc 1 2192 2 view .LVU126 + 367 .loc 1 2192 21 is_stmt 0 view .LVU127 + 368 0072 8278 ldrb r2, [r0, #2] @ zero_extendqisi2 + 369 .loc 1 2192 19 view .LVU128 + 370 0074 384B ldr r3, .L14+8 + 371 .LVL18: + 372 .loc 1 2192 19 view .LVU129 + 373 0076 1A70 strb r2, [r3] + 374 .loc 1 2192 40 is_stmt 1 view .LVU130 + 375 .LVL19: +2193:Src/main.c **** task.min_param = (float)(*temp2); temp2++; + 376 .loc 1 2193 2 view .LVU131 + 377 .loc 1 2193 29 is_stmt 0 view .LVU132 + 378 0078 8288 ldrh r2, [r0, #4] + 379 007a 07EE902A vmov s15, r2 @ int + 380 .loc 1 2193 21 view .LVU133 + 381 007e F8EE677A vcvt.f32.u32 s15, s15 + 382 .loc 1 2193 19 view .LVU134 + 383 0082 C3ED017A vstr.32 s15, [r3, #4] + 384 .loc 1 2193 38 is_stmt 1 view .LVU135 + 385 .LVL20: +2194:Src/main.c **** task.max_param = (float)(*temp2); temp2++; + 386 .loc 1 2194 2 view .LVU136 + 387 .loc 1 2194 29 is_stmt 0 view .LVU137 + 388 0086 C288 ldrh r2, [r0, #6] + 389 0088 07EE902A vmov s15, r2 @ int + 390 .loc 1 2194 21 view .LVU138 + 391 008c F8EE677A vcvt.f32.u32 s15, s15 + 392 .loc 1 2194 19 view .LVU139 + 393 0090 C3ED027A vstr.32 s15, [r3, #8] + 394 .loc 1 2194 38 is_stmt 1 view .LVU140 + 395 .LVL21: +2195:Src/main.c **** task.delta_param = (float)(*temp2); temp2++; + 396 .loc 1 2195 2 view .LVU141 + 397 .loc 1 2195 29 is_stmt 0 view .LVU142 + 398 0094 0289 ldrh r2, [r0, #8] + 399 0096 07EE902A vmov s15, r2 @ int + 400 .loc 1 2195 21 view .LVU143 + 401 009a F8EE677A vcvt.f32.u32 s15, s15 + 402 .loc 1 2195 19 view .LVU144 + 403 009e C3ED037A vstr.32 s15, [r3, #12] + 404 .loc 1 2195 38 is_stmt 1 view .LVU145 + 405 .LVL22: +2196:Src/main.c **** task.dt = (float)(*temp2) / 100.0; temp2++; + 406 .loc 1 2196 2 view .LVU146 + 407 .loc 1 2196 29 is_stmt 0 view .LVU147 + 408 00a2 4289 ldrh r2, [r0, #10] + 409 00a4 07EE102A vmov s14, r2 @ int + 410 .loc 1 2196 21 view .LVU148 + 411 00a8 B8EE477B vcvt.f64.u32 d7, s14 + 412 .loc 1 2196 37 view .LVU149 + ARM GAS /tmp/ccWQNJQt.s page 89 + + + 413 00ac 9FED285B vldr.64 d5, .L14 + 414 00b0 87EE056B vdiv.f64 d6, d7, d5 + 415 .loc 1 2196 19 view .LVU150 + 416 00b4 FCEEC67B vcvt.u32.f64 s15, d6 + 417 00b8 CDED017A vstr.32 s15, [sp, #4] @ int + 418 00bc 9DF80420 ldrb r2, [sp, #4] @ zero_extendqisi2 + 419 00c0 1A75 strb r2, [r3, #20] + 420 .loc 1 2196 46 is_stmt 1 view .LVU151 + 421 .LVL23: +2197:Src/main.c **** task.sec_param = (float)(*temp2); temp2++; + 422 .loc 1 2197 2 view .LVU152 + 423 .loc 1 2197 29 is_stmt 0 view .LVU153 + 424 00c2 8189 ldrh r1, [r0, #12] + 425 .LVL24: + 426 .loc 1 2197 29 view .LVU154 + 427 00c4 07EE901A vmov s15, r1 @ int + 428 .loc 1 2197 21 view .LVU155 + 429 00c8 F8EE677A vcvt.f32.u32 s15, s15 + 430 .loc 1 2197 19 view .LVU156 + 431 00cc C3ED067A vstr.32 s15, [r3, #24] + 432 .loc 1 2197 38 is_stmt 1 view .LVU157 + 433 .LVL25: +2198:Src/main.c **** task.curr = (float)(*temp2); temp2++; + 434 .loc 1 2198 2 view .LVU158 + 435 .loc 1 2198 29 is_stmt 0 view .LVU159 + 436 00d0 C189 ldrh r1, [r0, #14] + 437 00d2 07EE901A vmov s15, r1 @ int + 438 .loc 1 2198 21 view .LVU160 + 439 00d6 F8EE677A vcvt.f32.u32 s15, s15 + 440 .loc 1 2198 19 view .LVU161 + 441 00da C3ED077A vstr.32 s15, [r3, #28] + 442 .loc 1 2198 38 is_stmt 1 view .LVU162 + 443 .LVL26: +2199:Src/main.c **** task.temp = (float)(*temp2); temp2++; + 444 .loc 1 2199 2 view .LVU163 + 445 .loc 1 2199 29 is_stmt 0 view .LVU164 + 446 00de 018A ldrh r1, [r0, #16] + 447 00e0 07EE901A vmov s15, r1 @ int + 448 .loc 1 2199 21 view .LVU165 + 449 00e4 F8EE677A vcvt.f32.u32 s15, s15 + 450 .loc 1 2199 19 view .LVU166 + 451 00e8 C3ED087A vstr.32 s15, [r3, #32] + 452 .loc 1 2199 38 is_stmt 1 view .LVU167 + 453 .LVL27: +2200:Src/main.c **** task.tau = (float)(*temp2); temp2++; + 454 .loc 1 2200 2 view .LVU168 + 455 .loc 1 2200 29 is_stmt 0 view .LVU169 + 456 00ec 418A ldrh r1, [r0, #18] + 457 .loc 1 2200 19 view .LVU170 + 458 00ee D982 strh r1, [r3, #22] @ movhi + 459 .loc 1 2200 38 is_stmt 1 view .LVU171 + 460 .LVL28: +2201:Src/main.c **** task.p_coef_1 = (float)(*temp2) * 256.0; temp2++; + 461 .loc 1 2201 2 view .LVU172 + 462 .loc 1 2201 29 is_stmt 0 view .LVU173 + 463 00f0 818A ldrh r1, [r0, #20] + 464 00f2 07EE901A vmov s15, r1 @ int + ARM GAS /tmp/ccWQNJQt.s page 90 + + + 465 .loc 1 2201 21 view .LVU174 + 466 00f6 F8EE677A vcvt.f32.u32 s15, s15 + 467 .loc 1 2201 37 view .LVU175 + 468 00fa 9FED187A vldr.32 s14, .L14+12 + 469 00fe 67EE877A vmul.f32 s15, s15, s14 + 470 .loc 1 2201 19 view .LVU176 + 471 0102 C3ED0A7A vstr.32 s15, [r3, #40] + 472 .loc 1 2201 46 is_stmt 1 view .LVU177 + 473 .LVL29: +2202:Src/main.c **** task.i_coef_1 = (float)(*temp2) * 256.0; temp2++; + 474 .loc 1 2202 2 view .LVU178 + 475 .loc 1 2202 29 is_stmt 0 view .LVU179 + 476 0106 C18A ldrh r1, [r0, #22] + 477 0108 07EE901A vmov s15, r1 @ int + 478 .loc 1 2202 21 view .LVU180 + 479 010c F8EE677A vcvt.f32.u32 s15, s15 + 480 .loc 1 2202 37 view .LVU181 + 481 0110 67EE877A vmul.f32 s15, s15, s14 + 482 .loc 1 2202 19 view .LVU182 + 483 0114 C3ED097A vstr.32 s15, [r3, #36] + 484 .loc 1 2202 46 is_stmt 1 view .LVU183 + 485 .LVL30: +2203:Src/main.c **** task.p_coef_2 = (float)(*temp2) * 256.0; temp2++; + 486 .loc 1 2203 2 view .LVU184 + 487 .loc 1 2203 29 is_stmt 0 view .LVU185 + 488 0118 018B ldrh r1, [r0, #24] + 489 011a 07EE901A vmov s15, r1 @ int + 490 .loc 1 2203 21 view .LVU186 + 491 011e F8EE677A vcvt.f32.u32 s15, s15 + 492 .loc 1 2203 37 view .LVU187 + 493 0122 67EE877A vmul.f32 s15, s15, s14 + 494 .loc 1 2203 19 view .LVU188 + 495 0126 C3ED0C7A vstr.32 s15, [r3, #48] + 496 .loc 1 2203 46 is_stmt 1 view .LVU189 + 497 .LVL31: +2204:Src/main.c **** task.i_coef_2 = (float)(*temp2) * 256.0; temp2++; + 498 .loc 1 2204 2 view .LVU190 + 499 .loc 1 2204 29 is_stmt 0 view .LVU191 + 500 012a 418B ldrh r1, [r0, #26] + 501 012c 07EE901A vmov s15, r1 @ int + 502 .loc 1 2204 21 view .LVU192 + 503 0130 F8EE677A vcvt.f32.u32 s15, s15 + 504 .loc 1 2204 37 view .LVU193 + 505 0134 67EE877A vmul.f32 s15, s15, s14 + 506 .loc 1 2204 19 view .LVU194 + 507 0138 C3ED0B7A vstr.32 s15, [r3, #44] + 508 .loc 1 2204 46 is_stmt 1 view .LVU195 + 509 .LVL32: +2205:Src/main.c **** +2206:Src/main.c **** TO10_counter = task.dt / 10; + 510 .loc 1 2206 2 view .LVU196 + 511 .loc 1 2206 25 is_stmt 0 view .LVU197 + 512 013c 084B ldr r3, .L14+16 + 513 013e A3FB0232 umull r3, r2, r3, r2 + 514 0142 D208 lsrs r2, r2, #3 + 515 .loc 1 2206 15 view .LVU198 + 516 0144 074B ldr r3, .L14+20 + ARM GAS /tmp/ccWQNJQt.s page 91 + + + 517 0146 1A60 str r2, [r3] +2207:Src/main.c **** } + 518 .loc 1 2207 1 view .LVU199 + 519 0148 02B0 add sp, sp, #8 + 520 .LCFI5: + 521 .cfi_def_cfa_offset 0 + 522 @ sp needed + 523 014a 7047 bx lr + 524 .L15: + 525 014c AFF30080 .align 3 + 526 .L14: + 527 0150 00000000 .word 0 + 528 0154 00005940 .word 1079574528 + 529 0158 00000000 .word task + 530 015c 00008043 .word 1132462080 + 531 0160 CDCCCCCC .word -858993459 + 532 0164 00000000 .word TO10_counter + 533 .cfi_endproc + 534 .LFE1209: + 536 .section .text.PID_Controller_Temp,"ax",%progbits + 537 .align 1 + 538 .syntax unified + 539 .thumb + 540 .thumb_func + 542 PID_Controller_Temp: + 543 .LVL33: + 544 .LFB1215: +2208:Src/main.c **** +2209:Src/main.c **** void OUT_trigger(uint8_t out_n) +2210:Src/main.c **** { +2211:Src/main.c **** switch (out_n) +2212:Src/main.c **** { +2213:Src/main.c **** case 0: +2214:Src/main.c **** HAL_GPIO_WritePin(OUT_0_GPIO_Port, OUT_0_Pin, GPIO_PIN_SET); +2215:Src/main.c **** HAL_GPIO_WritePin(OUT_0_GPIO_Port, OUT_0_Pin, GPIO_PIN_RESET); +2216:Src/main.c **** break; +2217:Src/main.c **** +2218:Src/main.c **** case 1: +2219:Src/main.c **** HAL_GPIO_WritePin(OUT_1_GPIO_Port, OUT_1_Pin, GPIO_PIN_SET); +2220:Src/main.c **** HAL_GPIO_WritePin(OUT_1_GPIO_Port, OUT_1_Pin, GPIO_PIN_RESET); +2221:Src/main.c **** break; +2222:Src/main.c **** +2223:Src/main.c **** case 2: +2224:Src/main.c **** HAL_GPIO_WritePin(OUT_2_GPIO_Port, OUT_2_Pin, GPIO_PIN_SET); +2225:Src/main.c **** HAL_GPIO_WritePin(OUT_2_GPIO_Port, OUT_2_Pin, GPIO_PIN_RESET); +2226:Src/main.c **** break; +2227:Src/main.c **** +2228:Src/main.c **** case 3: +2229:Src/main.c **** HAL_GPIO_WritePin(OUT_3_GPIO_Port, OUT_3_Pin, GPIO_PIN_SET); +2230:Src/main.c **** HAL_GPIO_WritePin(OUT_3_GPIO_Port, OUT_3_Pin, GPIO_PIN_RESET); +2231:Src/main.c **** break; +2232:Src/main.c **** +2233:Src/main.c **** case 4: +2234:Src/main.c **** HAL_GPIO_WritePin(OUT_4_GPIO_Port, OUT_4_Pin, GPIO_PIN_SET); +2235:Src/main.c **** HAL_GPIO_WritePin(OUT_4_GPIO_Port, OUT_4_Pin, GPIO_PIN_RESET); +2236:Src/main.c **** break; +2237:Src/main.c **** + ARM GAS /tmp/ccWQNJQt.s page 92 + + +2238:Src/main.c **** case 5: +2239:Src/main.c **** HAL_GPIO_WritePin(OUT_5_GPIO_Port, OUT_5_Pin, GPIO_PIN_SET); +2240:Src/main.c **** HAL_GPIO_WritePin(OUT_5_GPIO_Port, OUT_5_Pin, GPIO_PIN_RESET); +2241:Src/main.c **** break; +2242:Src/main.c **** +2243:Src/main.c **** case 6: +2244:Src/main.c **** HAL_GPIO_WritePin(OUT_6_GPIO_Port, OUT_6_Pin, GPIO_PIN_SET); +2245:Src/main.c **** HAL_GPIO_WritePin(OUT_6_GPIO_Port, OUT_6_Pin, GPIO_PIN_RESET); +2246:Src/main.c **** break; +2247:Src/main.c **** +2248:Src/main.c **** case 7: +2249:Src/main.c **** HAL_GPIO_WritePin(OUT_7_GPIO_Port, OUT_7_Pin, GPIO_PIN_SET); +2250:Src/main.c **** HAL_GPIO_WritePin(OUT_7_GPIO_Port, OUT_7_Pin, GPIO_PIN_RESET); +2251:Src/main.c **** break; +2252:Src/main.c **** +2253:Src/main.c **** case 8: +2254:Src/main.c **** HAL_GPIO_WritePin(OUT_8_GPIO_Port, OUT_8_Pin, GPIO_PIN_SET); +2255:Src/main.c **** HAL_GPIO_WritePin(OUT_8_GPIO_Port, OUT_8_Pin, GPIO_PIN_RESET); +2256:Src/main.c **** break; +2257:Src/main.c **** +2258:Src/main.c **** case 9: +2259:Src/main.c **** HAL_GPIO_WritePin(OUT_9_GPIO_Port, OUT_9_Pin, GPIO_PIN_SET); +2260:Src/main.c **** HAL_GPIO_WritePin(OUT_9_GPIO_Port, OUT_9_Pin, GPIO_PIN_RESET); +2261:Src/main.c **** break; +2262:Src/main.c **** } +2263:Src/main.c **** } +2264:Src/main.c **** +2265:Src/main.c **** void Set_LTEC(uint8_t num, uint16_t DATA) +2266:Src/main.c **** { +2267:Src/main.c **** uint32_t tmp32; +2268:Src/main.c **** +2269:Src/main.c **** switch (num) +2270:Src/main.c **** { +2271:Src/main.c **** case 1: +2272:Src/main.c **** HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_RESET);//Start operation with L +2273:Src/main.c **** //tmp32=0; +2274:Src/main.c **** //while(tmp32<500){tmp32++;} +2275:Src/main.c **** tmp32 = 0; +2276:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi +2277:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC +2278:Src/main.c **** tmp32 = 0; +2279:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w +2280:Src/main.c **** (void) SPI2->DR; +2281:Src/main.c **** break; +2282:Src/main.c **** case 2: +2283:Src/main.c **** //HAL_GPIO_TogglePin(OUT_11_GPIO_Port, OUT_11_Pin); //for debug purposes +2284:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_RESET);//Start operation with L +2285:Src/main.c **** //tmp32=0; +2286:Src/main.c **** //while(tmp32<500){tmp32++;} +2287:Src/main.c **** tmp32 = 0; +2288:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi +2289:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC +2290:Src/main.c **** tmp32 = 0; +2291:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w +2292:Src/main.c **** (void) SPI6->DR; +2293:Src/main.c **** break; +2294:Src/main.c **** case 3: + ARM GAS /tmp/ccWQNJQt.s page 93 + + +2295:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_RESET);//Start operation with +2296:Src/main.c **** //tmp32=0; +2297:Src/main.c **** //while(tmp32<500){tmp32++;} +2298:Src/main.c **** tmp32 = 0; +2299:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi +2300:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC +2301:Src/main.c **** tmp32 = 0; +2302:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w +2303:Src/main.c **** (void) SPI2->DR; +2304:Src/main.c **** break; +2305:Src/main.c **** case 4: +2306:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_RESET);//Start operation with +2307:Src/main.c **** //tmp32=0; +2308:Src/main.c **** //while(tmp32<500){tmp32++;} +2309:Src/main.c **** tmp32 = 0; +2310:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi +2311:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC +2312:Src/main.c **** tmp32 = 0; +2313:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w +2314:Src/main.c **** (void) SPI6->DR; +2315:Src/main.c **** break; +2316:Src/main.c **** } +2317:Src/main.c **** HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_SET);//End operation with LDAC1 +2318:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_SET);//End operation with LDAC2 +2319:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1 +2320:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);//End operation with TEC2 +2321:Src/main.c **** } +2322:Src/main.c **** static uint16_t MPhD_T(uint8_t num) +2323:Src/main.c **** { +2324:Src/main.c **** uint16_t P; +2325:Src/main.c **** uint32_t tmp32; +2326:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion +2327:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion +2328:Src/main.c **** tmp32=0; +2329:Src/main.c **** while(tmp32<500){tmp32++;} +2330:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver +2331:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver +2332:Src/main.c **** tmp32=0; +2333:Src/main.c **** while(tmp32<500){tmp32++;} +2334:Src/main.c **** if (num==1)//MPD1 +2335:Src/main.c **** { +2336:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_SET); +2337:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_RESET); +2338:Src/main.c **** tmp32=0; +2339:Src/main.c **** while(tmp32<500){tmp32++;} +2340:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c +2341:Src/main.c **** LL_SPI_Enable(SPI4);//Enable SPI for MPhD1 ADC +2342:Src/main.c **** tmp32 = 0; +2343:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w +2344:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC +2345:Src/main.c **** while(tmp32<500){tmp32++;} +2346:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); +2347:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_SET); +2348:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); +2349:Src/main.c **** } +2350:Src/main.c **** else if (num==2)//MPD2 +2351:Src/main.c **** { + ARM GAS /tmp/ccWQNJQt.s page 94 + + +2352:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_SET); +2353:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_RESET); +2354:Src/main.c **** tmp32=0; +2355:Src/main.c **** while(tmp32<500){tmp32++;} +2356:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c +2357:Src/main.c **** LL_SPI_Enable(SPI5);//Enable SPI for MPhD2 ADC +2358:Src/main.c **** tmp32 = 0; +2359:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w +2360:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC +2361:Src/main.c **** while(tmp32<500){tmp32++;} +2362:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); +2363:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET); +2364:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); +2365:Src/main.c **** } +2366:Src/main.c **** else if (num==3)//ThrLD1 +2367:Src/main.c **** { +2368:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_SET); +2369:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET); +2370:Src/main.c **** tmp32=0; +2371:Src/main.c **** while(tmp32<500){tmp32++;} +2372:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c +2373:Src/main.c **** LL_SPI_Enable(SPI4);//Enable SPI for ThrLD1 ADC +2374:Src/main.c **** tmp32 = 0; +2375:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w +2376:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC +2377:Src/main.c **** while(tmp32<500){tmp32++;} +2378:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); +2379:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_SET); +2380:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); +2381:Src/main.c **** } +2382:Src/main.c **** else if (num==4)//ThrLD2 +2383:Src/main.c **** { +2384:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET); +2385:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET); +2386:Src/main.c **** tmp32=0; +2387:Src/main.c **** while(tmp32<500){tmp32++;} +2388:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c +2389:Src/main.c **** LL_SPI_Enable(SPI5);//Enable SPI for ThrLD2 ADC +2390:Src/main.c **** tmp32 = 0; +2391:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w +2392:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC +2393:Src/main.c **** while(tmp32<500){tmp32++;} +2394:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); +2395:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_SET); +2396:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); +2397:Src/main.c **** } +2398:Src/main.c **** /*float I_LD, Ith, I0m, T0m, Inorm, Tnorm1, Tnorm2, P, T_C, A, Pnorm; +2399:Src/main.c **** +2400:Src/main.c **** Inorm = (float) (65535) / (float) (100); +2401:Src/main.c **** Tnorm1 = (float) (65535) / (float) (50); +2402:Src/main.c **** Tnorm2 = 4; +2403:Src/main.c **** Pnorm = (float)(65535) / (float)(20); +2404:Src/main.c **** I0m = 8.1568;//@4 C - lowest temperature of system +2405:Src/main.c **** T0m = 48.6282; +2406:Src/main.c **** T_C = (float) (T_LD) / Tnorm1 + Tnorm2; +2407:Src/main.c **** +2408:Src/main.c **** Ith = I0m * expf(T_C/T0m); + ARM GAS /tmp/ccWQNJQt.s page 95 + + +2409:Src/main.c **** I_LD = (float) (C_LD) / Inorm; +2410:Src/main.c **** +2411:Src/main.c **** if (I_LD > Ith) +2412:Src/main.c **** { +2413:Src/main.c **** A = (float) (2.24276128270098e-07) * T_C * T_C * T_C - (float) (4.73392579025590e-05) * T_C * T_ +2414:Src/main.c **** P = A * (I_LD - Ith) * Pnorm; +2415:Src/main.c **** } +2416:Src/main.c **** else +2417:Src/main.c **** { +2418:Src/main.c **** P = 0; +2419:Src/main.c **** } */ +2420:Src/main.c **** return P; +2421:Src/main.c **** } +2422:Src/main.c **** /*static uint16_t Temp_LD(uint16_t T_LD_before, uint16_t T_LD, uint32_t Timer_before, uint32_t Time +2423:Src/main.c **** { +2424:Src/main.c **** uint16_t Result; +2425:Src/main.c **** // uint8_t randf; +2426:Src/main.c **** +2427:Src/main.c **** randf = 0; +2428:Src/main.c **** for (uint8_t i = 0; i < 32; i++) +2429:Src/main.c **** { +2430:Src/main.c **** randf = ((Timer>>i)&0x0001)^randf; +2431:Src/main.c **** } +2432:Src/main.c **** +2433:Src/main.c **** Result = ((float)(T_LD - T_LD_before))*((float)(1-expf(((float)(Timer_before)-(float)(Timer))/((fl +2434:Src/main.c **** +2435:Src/main.c **** return (uint16_t)(Result); +2436:Src/main.c **** }*/ +2437:Src/main.c **** static uint16_t Get_ADC(uint8_t num) +2438:Src/main.c **** { +2439:Src/main.c **** uint16_t OUT; +2440:Src/main.c **** switch (num) +2441:Src/main.c **** { +2442:Src/main.c **** case 0: +2443:Src/main.c **** HAL_ADC_Start(&hadc1); // Power on +2444:Src/main.c **** break; +2445:Src/main.c **** case 1: +2446:Src/main.c **** HAL_ADC_PollForConversion(&hadc1, 100); // Waiting for conversion +2447:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc1); // Get value adc +2448:Src/main.c **** break; +2449:Src/main.c **** case 2: +2450:Src/main.c **** HAL_ADC_Stop(&hadc1); // Power off +2451:Src/main.c **** break; +2452:Src/main.c **** case 3: +2453:Src/main.c **** HAL_ADC_Start(&hadc3); // Power on +2454:Src/main.c **** break; +2455:Src/main.c **** case 4: +2456:Src/main.c **** HAL_ADC_PollForConversion(&hadc3, 100); // Waiting for conversion +2457:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc3); // Get value adc +2458:Src/main.c **** break; +2459:Src/main.c **** case 5: +2460:Src/main.c **** HAL_ADC_Stop(&hadc3); // Power off +2461:Src/main.c **** break; +2462:Src/main.c **** } +2463:Src/main.c **** return OUT; +2464:Src/main.c **** } +2465:Src/main.c **** + ARM GAS /tmp/ccWQNJQt.s page 96 + + +2466:Src/main.c **** uint16_t Advanced_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_results +2467:Src/main.c **** { +2468:Src/main.c **** // Main idea: +2469:Src/main.c **** // I is responsible to maintaining constant temperature difference between laser and room temperat +2470:Src/main.c **** // As room temperature can be approximated as constant at current-varying time -- I should be kept +2471:Src/main.c **** // As current through laser diode heats it -- we can estimate excessive power on laser diode and t +2472:Src/main.c **** // So, equation should be look like this: +2473:Src/main.c **** // x_output = x_output_original + I(laser)*(a + (t - b)c) +2474:Src/main.c **** // t -- cycle phase +2475:Src/main.c **** // a,b,c -- constants +2476:Src/main.c **** // +2477:Src/main.c **** // How can we control laser diode temperature? +2478:Src/main.c **** // -- We can set laser to fixed current at the time we need to measure. +2479:Src/main.c **** // Then we should measure wavelength. +2480:Src/main.c **** // Calibration sequence: +2481:Src/main.c **** // 1) n +2482:Src/main.c **** +2483:Src/main.c **** +2484:Src/main.c **** +2485:Src/main.c **** int e_pid; +2486:Src/main.c **** float P_coef_current;//, I_coef_current; +2487:Src/main.c **** float e_integral; +2488:Src/main.c **** int x_output; +2489:Src/main.c **** +2490:Src/main.c **** e_pid = (int) LDx_results->LD_CURR_TEMP - (int) LDx_curr_setup->LD_TEMP; +2491:Src/main.c **** +2492:Src/main.c **** e_integral = LDx_results->e_integral; +2493:Src/main.c **** +2494:Src/main.c **** if((e_pid < 3000) && (e_pid > - 3000)){ +2495:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 +2496:Src/main.c **** } +2497:Src/main.c **** P_coef_current = LDx_curr_setup->P_coef_temp; +2498:Src/main.c **** +2499:Src/main.c **** if (e_integral > 32000){ +2500:Src/main.c **** e_integral = 32000; +2501:Src/main.c **** } +2502:Src/main.c **** else if (e_integral < - 32000){ +2503:Src/main.c **** e_integral = -32000; +2504:Src/main.c **** } +2505:Src/main.c **** LDx_results->e_integral = e_integral; +2506:Src/main.c **** +2507:Src/main.c **** x_output = 32768 + P_coef_current * e_pid + (int)e_integral;//32768 - P_coef_current * e_pid - (in +2508:Src/main.c **** +2509:Src/main.c **** if(x_output < 1000){ +2510:Src/main.c **** x_output = 8800; +2511:Src/main.c **** } +2512:Src/main.c **** else if(x_output > 56800){ +2513:Src/main.c **** x_output = 56800; +2514:Src/main.c **** } +2515:Src/main.c **** +2516:Src/main.c **** if (num==2) +2517:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser +2518:Src/main.c **** +2519:Src/main.c **** return (uint16_t)x_output; +2520:Src/main.c **** } +2521:Src/main.c **** +2522:Src/main.c **** + ARM GAS /tmp/ccWQNJQt.s page 97 + + +2523:Src/main.c **** uint16_t PID_Controller_Temp(LDx_SetupTypeDef * LDx_curr_setup, LDx_ParamTypeDef * LDx_results, uin +2524:Src/main.c **** { + 545 .loc 1 2524 1 is_stmt 1 view -0 + 546 .cfi_startproc + 547 @ args = 0, pretend = 0, frame = 0 + 548 @ frame_needed = 0, uses_anonymous_args = 0 + 549 @ link register save eliminated. + 550 .loc 1 2524 1 is_stmt 0 view .LVU201 + 551 0000 30B4 push {r4, r5} + 552 .LCFI6: + 553 .cfi_def_cfa_offset 8 + 554 .cfi_offset 4, -8 + 555 .cfi_offset 5, -4 +2525:Src/main.c **** int e_pid; + 556 .loc 1 2525 2 is_stmt 1 view .LVU202 +2526:Src/main.c **** float P_coef_current;//, I_coef_current; + 557 .loc 1 2526 2 view .LVU203 +2527:Src/main.c **** float e_integral; + 558 .loc 1 2527 2 view .LVU204 +2528:Src/main.c **** int x_output; + 559 .loc 1 2528 2 view .LVU205 +2529:Src/main.c **** +2530:Src/main.c **** e_pid = (int) LDx_results->LD_CURR_TEMP - (int) LDx_curr_setup->LD_TEMP; + 560 .loc 1 2530 2 view .LVU206 + 561 .loc 1 2530 28 is_stmt 0 view .LVU207 + 562 0002 0B88 ldrh r3, [r1] + 563 .loc 1 2530 65 view .LVU208 + 564 0004 0488 ldrh r4, [r0] + 565 .loc 1 2530 8 view .LVU209 + 566 0006 1B1B subs r3, r3, r4 + 567 .LVL34: +2531:Src/main.c **** +2532:Src/main.c **** e_integral = LDx_results->e_integral; + 568 .loc 1 2532 2 is_stmt 1 view .LVU210 + 569 .loc 1 2532 13 is_stmt 0 view .LVU211 + 570 0008 D1ED017A vldr.32 s15, [r1, #4] + 571 .LVL35: +2533:Src/main.c **** +2534:Src/main.c **** if((e_pid < 3000) && (e_pid > - 3000)){ + 572 .loc 1 2534 2 is_stmt 1 view .LVU212 + 573 .loc 1 2534 20 is_stmt 0 view .LVU213 + 574 000c 03F6B73C addw ip, r3, #2999 + 575 .loc 1 2534 4 view .LVU214 + 576 0010 41F26E74 movw r4, #5998 + 577 0014 A445 cmp ip, r4 + 578 0016 18D8 bhi .L17 +2535:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 + 579 .loc 1 2535 3 is_stmt 1 view .LVU215 + 580 .loc 1 2535 31 is_stmt 0 view .LVU216 + 581 0018 90ED027A vldr.32 s14, [r0, #8] + 582 .loc 1 2535 47 view .LVU217 + 583 001c 06EE903A vmov s13, r3 @ int + 584 0020 F8EEE66A vcvt.f32.s32 s13, s13 + 585 .loc 1 2535 45 view .LVU218 + 586 0024 27EE267A vmul.f32 s14, s14, s13 + 587 .loc 1 2535 76 view .LVU219 + 588 0028 284C ldr r4, .L27 + ARM GAS /tmp/ccWQNJQt.s page 98 + + + 589 002a 2468 ldr r4, [r4] + 590 002c 284D ldr r5, .L27+4 + 591 002e 2D68 ldr r5, [r5] + 592 0030 641B subs r4, r4, r5 + 593 .loc 1 2535 64 view .LVU220 + 594 0032 06EE904A vmov s13, r4 @ int + 595 0036 F8EE666A vcvt.f32.u32 s13, s13 + 596 .loc 1 2535 62 view .LVU221 + 597 003a 27EE267A vmul.f32 s14, s14, s13 + 598 .loc 1 2535 87 view .LVU222 + 599 003e 9FED256A vldr.32 s12, .L27+8 + 600 0042 C7EE066A vdiv.f32 s13, s14, s12 + 601 .loc 1 2535 14 view .LVU223 + 602 0046 77EEA67A vadd.f32 s15, s15, s13 + 603 .LVL36: + 604 .L17: +2536:Src/main.c **** } +2537:Src/main.c **** P_coef_current = LDx_curr_setup->P_coef_temp; + 605 .loc 1 2537 2 is_stmt 1 view .LVU224 + 606 .loc 1 2537 17 is_stmt 0 view .LVU225 + 607 004a D0ED016A vldr.32 s13, [r0, #4] + 608 .LVL37: +2538:Src/main.c **** +2539:Src/main.c **** if (e_integral > 32000){ + 609 .loc 1 2539 2 is_stmt 1 view .LVU226 + 610 .loc 1 2539 5 is_stmt 0 view .LVU227 + 611 004e 9FED227A vldr.32 s14, .L27+12 + 612 0052 F4EEC77A vcmpe.f32 s15, s14 + 613 0056 F1EE10FA vmrs APSR_nzcv, FPSCR + 614 005a 09DC bgt .L21 +2540:Src/main.c **** e_integral = 32000; +2541:Src/main.c **** } +2542:Src/main.c **** else if (e_integral < - 32000){ + 615 .loc 1 2542 7 is_stmt 1 view .LVU228 + 616 .loc 1 2542 10 is_stmt 0 view .LVU229 + 617 005c 9FED1F7A vldr.32 s14, .L27+16 + 618 0060 F4EEC77A vcmpe.f32 s15, s14 + 619 0064 F1EE10FA vmrs APSR_nzcv, FPSCR + 620 0068 04D5 bpl .L18 +2543:Src/main.c **** e_integral = -32000; + 621 .loc 1 2543 15 view .LVU230 + 622 006a DFED1C7A vldr.32 s15, .L27+16 + 623 .LVL38: + 624 .loc 1 2543 15 view .LVU231 + 625 006e 01E0 b .L18 + 626 .LVL39: + 627 .L21: +2540:Src/main.c **** e_integral = 32000; + 628 .loc 1 2540 15 view .LVU232 + 629 0070 DFED197A vldr.32 s15, .L27+12 + 630 .LVL40: + 631 .L18: +2544:Src/main.c **** } +2545:Src/main.c **** LDx_results->e_integral = e_integral; + 632 .loc 1 2545 2 is_stmt 1 view .LVU233 + 633 .loc 1 2545 26 is_stmt 0 view .LVU234 + 634 0074 C1ED017A vstr.32 s15, [r1, #4] + ARM GAS /tmp/ccWQNJQt.s page 99 + + +2546:Src/main.c **** +2547:Src/main.c **** x_output = 32768 + P_coef_current * e_pid + (int)e_integral;//32768 - P_coef_current * e_pid - (in + 635 .loc 1 2547 2 is_stmt 1 view .LVU235 + 636 .loc 1 2547 36 is_stmt 0 view .LVU236 + 637 0078 07EE103A vmov s14, r3 @ int + 638 007c B8EEC77A vcvt.f32.s32 s14, s14 + 639 0080 27EE267A vmul.f32 s14, s14, s13 + 640 .loc 1 2547 19 view .LVU237 + 641 0084 DFED166A vldr.32 s13, .L27+20 + 642 .LVL41: + 643 .loc 1 2547 19 view .LVU238 + 644 0088 37EE267A vadd.f32 s14, s14, s13 + 645 .loc 1 2547 46 view .LVU239 + 646 008c FDEEE77A vcvt.s32.f32 s15, s15 + 647 .LVL42: + 648 .loc 1 2547 44 view .LVU240 + 649 0090 F8EEE77A vcvt.f32.s32 s15, s15 + 650 0094 77EE877A vadd.f32 s15, s15, s14 + 651 .loc 1 2547 11 view .LVU241 + 652 0098 FDEEE77A vcvt.s32.f32 s15, s15 + 653 009c 17EE900A vmov r0, s15 @ int + 654 .LVL43: +2548:Src/main.c **** +2549:Src/main.c **** if(x_output < 1000){ + 655 .loc 1 2549 2 is_stmt 1 view .LVU242 + 656 .loc 1 2549 4 is_stmt 0 view .LVU243 + 657 00a0 B0F57A7F cmp r0, #1000 + 658 00a4 06DB blt .L23 +2550:Src/main.c **** x_output = 8800; +2551:Src/main.c **** } +2552:Src/main.c **** else if(x_output > 56800){ + 659 .loc 1 2552 7 is_stmt 1 view .LVU244 + 660 .loc 1 2552 9 is_stmt 0 view .LVU245 + 661 00a6 4DF6E053 movw r3, #56800 + 662 .LVL44: + 663 .loc 1 2552 9 view .LVU246 + 664 00aa 9842 cmp r0, r3 + 665 00ac 04DD ble .L19 +2553:Src/main.c **** x_output = 56800; + 666 .loc 1 2553 12 view .LVU247 + 667 00ae 4DF6E050 movw r0, #56800 + 668 .LVL45: + 669 .loc 1 2553 12 view .LVU248 + 670 00b2 01E0 b .L19 + 671 .LVL46: + 672 .L23: +2550:Src/main.c **** x_output = 8800; + 673 .loc 1 2550 12 view .LVU249 + 674 00b4 42F26020 movw r0, #8800 + 675 .LVL47: + 676 .L19: +2554:Src/main.c **** } +2555:Src/main.c **** +2556:Src/main.c **** if (num==2) + 677 .loc 1 2556 2 is_stmt 1 view .LVU250 + 678 .loc 1 2556 5 is_stmt 0 view .LVU251 + 679 00b8 022A cmp r2, #2 + ARM GAS /tmp/ccWQNJQt.s page 100 + + + 680 00ba 02D0 beq .L26 + 681 .LVL48: + 682 .L20: +2557:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser +2558:Src/main.c **** +2559:Src/main.c **** return (uint16_t)x_output; + 683 .loc 1 2559 2 is_stmt 1 view .LVU252 +2560:Src/main.c **** } + 684 .loc 1 2560 1 is_stmt 0 view .LVU253 + 685 00bc 80B2 uxth r0, r0 + 686 .LVL49: + 687 .loc 1 2560 1 view .LVU254 + 688 00be 30BC pop {r4, r5} + 689 .LCFI7: + 690 .cfi_remember_state + 691 .cfi_restore 5 + 692 .cfi_restore 4 + 693 .cfi_def_cfa_offset 0 + 694 00c0 7047 bx lr + 695 .LVL50: + 696 .L26: + 697 .LCFI8: + 698 .cfi_restore_state +2557:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser + 699 .loc 1 2557 3 is_stmt 1 view .LVU255 +2557:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser + 700 .loc 1 2557 11 is_stmt 0 view .LVU256 + 701 00c2 024B ldr r3, .L27 + 702 00c4 1A68 ldr r2, [r3] + 703 .LVL51: +2557:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser + 704 .loc 1 2557 11 view .LVU257 + 705 00c6 024B ldr r3, .L27+4 + 706 00c8 1A60 str r2, [r3] + 707 00ca F7E7 b .L20 + 708 .L28: + 709 .align 2 + 710 .L27: + 711 00cc 00000000 .word TO7 + 712 00d0 00000000 .word TO7_PID + 713 00d4 0000C842 .word 1120403456 + 714 00d8 0000FA46 .word 1190789120 + 715 00dc 0000FAC6 .word -956694528 + 716 00e0 00000047 .word 1191182336 + 717 .cfi_endproc + 718 .LFE1215: + 720 .section .text.OUT_trigger,"ax",%progbits + 721 .align 1 + 722 .syntax unified + 723 .thumb + 724 .thumb_func + 726 OUT_trigger: + 727 .LVL52: + 728 .LFB1210: +2210:Src/main.c **** switch (out_n) + 729 .loc 1 2210 1 is_stmt 1 view -0 + 730 .cfi_startproc + ARM GAS /tmp/ccWQNJQt.s page 101 + + + 731 @ args = 0, pretend = 0, frame = 0 + 732 @ frame_needed = 0, uses_anonymous_args = 0 +2210:Src/main.c **** switch (out_n) + 733 .loc 1 2210 1 is_stmt 0 view .LVU259 + 734 0000 10B5 push {r4, lr} + 735 .LCFI9: + 736 .cfi_def_cfa_offset 8 + 737 .cfi_offset 4, -8 + 738 .cfi_offset 14, -4 +2211:Src/main.c **** { + 739 .loc 1 2211 2 is_stmt 1 view .LVU260 + 740 0002 0928 cmp r0, #9 + 741 0004 13D8 bhi .L29 + 742 0006 DFE800F0 tbb [pc, r0] + 743 .L32: + 744 000a 05 .byte (.L41-.L32)/2 + 745 000b 13 .byte (.L40-.L32)/2 + 746 000c 21 .byte (.L39-.L32)/2 + 747 000d 2F .byte (.L38-.L32)/2 + 748 000e 3D .byte (.L37-.L32)/2 + 749 000f 4B .byte (.L36-.L32)/2 + 750 0010 59 .byte (.L35-.L32)/2 + 751 0011 65 .byte (.L34-.L32)/2 + 752 0012 71 .byte (.L33-.L32)/2 + 753 0013 7D .byte (.L31-.L32)/2 + 754 .p2align 1 + 755 .L41: +2214:Src/main.c **** HAL_GPIO_WritePin(OUT_0_GPIO_Port, OUT_0_Pin, GPIO_PIN_RESET); + 756 .loc 1 2214 3 view .LVU261 + 757 0014 414C ldr r4, .L44 + 758 0016 0122 movs r2, #1 + 759 0018 4FF48061 mov r1, #1024 + 760 001c 2046 mov r0, r4 + 761 .LVL53: +2214:Src/main.c **** HAL_GPIO_WritePin(OUT_0_GPIO_Port, OUT_0_Pin, GPIO_PIN_RESET); + 762 .loc 1 2214 3 is_stmt 0 view .LVU262 + 763 001e FFF7FEFF bl HAL_GPIO_WritePin + 764 .LVL54: +2215:Src/main.c **** break; + 765 .loc 1 2215 3 is_stmt 1 view .LVU263 + 766 0022 0022 movs r2, #0 + 767 0024 4FF48061 mov r1, #1024 + 768 0028 2046 mov r0, r4 + 769 002a FFF7FEFF bl HAL_GPIO_WritePin + 770 .LVL55: +2216:Src/main.c **** + 771 .loc 1 2216 2 view .LVU264 + 772 .L29: +2263:Src/main.c **** + 773 .loc 1 2263 1 is_stmt 0 view .LVU265 + 774 002e 10BD pop {r4, pc} + 775 .LVL56: + 776 .L40: +2219:Src/main.c **** HAL_GPIO_WritePin(OUT_1_GPIO_Port, OUT_1_Pin, GPIO_PIN_RESET); + 777 .loc 1 2219 3 is_stmt 1 view .LVU266 + 778 0030 3A4C ldr r4, .L44 + 779 0032 0122 movs r2, #1 + ARM GAS /tmp/ccWQNJQt.s page 102 + + + 780 0034 4FF40061 mov r1, #2048 + 781 0038 2046 mov r0, r4 + 782 .LVL57: +2219:Src/main.c **** HAL_GPIO_WritePin(OUT_1_GPIO_Port, OUT_1_Pin, GPIO_PIN_RESET); + 783 .loc 1 2219 3 is_stmt 0 view .LVU267 + 784 003a FFF7FEFF bl HAL_GPIO_WritePin + 785 .LVL58: +2220:Src/main.c **** break; + 786 .loc 1 2220 3 is_stmt 1 view .LVU268 + 787 003e 0022 movs r2, #0 + 788 0040 4FF40061 mov r1, #2048 + 789 0044 2046 mov r0, r4 + 790 0046 FFF7FEFF bl HAL_GPIO_WritePin + 791 .LVL59: +2221:Src/main.c **** + 792 .loc 1 2221 2 view .LVU269 + 793 004a F0E7 b .L29 + 794 .LVL60: + 795 .L39: +2224:Src/main.c **** HAL_GPIO_WritePin(OUT_2_GPIO_Port, OUT_2_Pin, GPIO_PIN_RESET); + 796 .loc 1 2224 3 view .LVU270 + 797 004c 334C ldr r4, .L44 + 798 004e 0122 movs r2, #1 + 799 0050 4FF48051 mov r1, #4096 + 800 0054 2046 mov r0, r4 + 801 .LVL61: +2224:Src/main.c **** HAL_GPIO_WritePin(OUT_2_GPIO_Port, OUT_2_Pin, GPIO_PIN_RESET); + 802 .loc 1 2224 3 is_stmt 0 view .LVU271 + 803 0056 FFF7FEFF bl HAL_GPIO_WritePin + 804 .LVL62: +2225:Src/main.c **** break; + 805 .loc 1 2225 3 is_stmt 1 view .LVU272 + 806 005a 0022 movs r2, #0 + 807 005c 4FF48051 mov r1, #4096 + 808 0060 2046 mov r0, r4 + 809 0062 FFF7FEFF bl HAL_GPIO_WritePin + 810 .LVL63: +2226:Src/main.c **** + 811 .loc 1 2226 2 view .LVU273 + 812 0066 E2E7 b .L29 + 813 .LVL64: + 814 .L38: +2229:Src/main.c **** HAL_GPIO_WritePin(OUT_3_GPIO_Port, OUT_3_Pin, GPIO_PIN_RESET); + 815 .loc 1 2229 3 view .LVU274 + 816 0068 2C4C ldr r4, .L44 + 817 006a 0122 movs r2, #1 + 818 006c 4FF40051 mov r1, #8192 + 819 0070 2046 mov r0, r4 + 820 .LVL65: +2229:Src/main.c **** HAL_GPIO_WritePin(OUT_3_GPIO_Port, OUT_3_Pin, GPIO_PIN_RESET); + 821 .loc 1 2229 3 is_stmt 0 view .LVU275 + 822 0072 FFF7FEFF bl HAL_GPIO_WritePin + 823 .LVL66: +2230:Src/main.c **** break; + 824 .loc 1 2230 3 is_stmt 1 view .LVU276 + 825 0076 0022 movs r2, #0 + 826 0078 4FF40051 mov r1, #8192 + ARM GAS /tmp/ccWQNJQt.s page 103 + + + 827 007c 2046 mov r0, r4 + 828 007e FFF7FEFF bl HAL_GPIO_WritePin + 829 .LVL67: +2231:Src/main.c **** + 830 .loc 1 2231 2 view .LVU277 + 831 0082 D4E7 b .L29 + 832 .LVL68: + 833 .L37: +2234:Src/main.c **** HAL_GPIO_WritePin(OUT_4_GPIO_Port, OUT_4_Pin, GPIO_PIN_RESET); + 834 .loc 1 2234 3 view .LVU278 + 835 0084 254C ldr r4, .L44 + 836 0086 0122 movs r2, #1 + 837 0088 4FF48041 mov r1, #16384 + 838 008c 2046 mov r0, r4 + 839 .LVL69: +2234:Src/main.c **** HAL_GPIO_WritePin(OUT_4_GPIO_Port, OUT_4_Pin, GPIO_PIN_RESET); + 840 .loc 1 2234 3 is_stmt 0 view .LVU279 + 841 008e FFF7FEFF bl HAL_GPIO_WritePin + 842 .LVL70: +2235:Src/main.c **** break; + 843 .loc 1 2235 3 is_stmt 1 view .LVU280 + 844 0092 0022 movs r2, #0 + 845 0094 4FF48041 mov r1, #16384 + 846 0098 2046 mov r0, r4 + 847 009a FFF7FEFF bl HAL_GPIO_WritePin + 848 .LVL71: +2236:Src/main.c **** + 849 .loc 1 2236 2 view .LVU281 + 850 009e C6E7 b .L29 + 851 .LVL72: + 852 .L36: +2239:Src/main.c **** HAL_GPIO_WritePin(OUT_5_GPIO_Port, OUT_5_Pin, GPIO_PIN_RESET); + 853 .loc 1 2239 3 view .LVU282 + 854 00a0 1E4C ldr r4, .L44 + 855 00a2 0122 movs r2, #1 + 856 00a4 4FF40041 mov r1, #32768 + 857 00a8 2046 mov r0, r4 + 858 .LVL73: +2239:Src/main.c **** HAL_GPIO_WritePin(OUT_5_GPIO_Port, OUT_5_Pin, GPIO_PIN_RESET); + 859 .loc 1 2239 3 is_stmt 0 view .LVU283 + 860 00aa FFF7FEFF bl HAL_GPIO_WritePin + 861 .LVL74: +2240:Src/main.c **** break; + 862 .loc 1 2240 3 is_stmt 1 view .LVU284 + 863 00ae 0022 movs r2, #0 + 864 00b0 4FF40041 mov r1, #32768 + 865 00b4 2046 mov r0, r4 + 866 00b6 FFF7FEFF bl HAL_GPIO_WritePin + 867 .LVL75: +2241:Src/main.c **** + 868 .loc 1 2241 2 view .LVU285 + 869 00ba B8E7 b .L29 + 870 .LVL76: + 871 .L35: +2244:Src/main.c **** HAL_GPIO_WritePin(OUT_6_GPIO_Port, OUT_6_Pin, GPIO_PIN_RESET); + 872 .loc 1 2244 3 view .LVU286 + 873 00bc 184C ldr r4, .L44+4 + ARM GAS /tmp/ccWQNJQt.s page 104 + + + 874 00be 0122 movs r2, #1 + 875 00c0 1021 movs r1, #16 + 876 00c2 2046 mov r0, r4 + 877 .LVL77: +2244:Src/main.c **** HAL_GPIO_WritePin(OUT_6_GPIO_Port, OUT_6_Pin, GPIO_PIN_RESET); + 878 .loc 1 2244 3 is_stmt 0 view .LVU287 + 879 00c4 FFF7FEFF bl HAL_GPIO_WritePin + 880 .LVL78: +2245:Src/main.c **** break; + 881 .loc 1 2245 3 is_stmt 1 view .LVU288 + 882 00c8 0022 movs r2, #0 + 883 00ca 1021 movs r1, #16 + 884 00cc 2046 mov r0, r4 + 885 00ce FFF7FEFF bl HAL_GPIO_WritePin + 886 .LVL79: +2246:Src/main.c **** + 887 .loc 1 2246 2 view .LVU289 + 888 00d2 ACE7 b .L29 + 889 .LVL80: + 890 .L34: +2249:Src/main.c **** HAL_GPIO_WritePin(OUT_7_GPIO_Port, OUT_7_Pin, GPIO_PIN_RESET); + 891 .loc 1 2249 3 view .LVU290 + 892 00d4 124C ldr r4, .L44+4 + 893 00d6 0122 movs r2, #1 + 894 00d8 2021 movs r1, #32 + 895 00da 2046 mov r0, r4 + 896 .LVL81: +2249:Src/main.c **** HAL_GPIO_WritePin(OUT_7_GPIO_Port, OUT_7_Pin, GPIO_PIN_RESET); + 897 .loc 1 2249 3 is_stmt 0 view .LVU291 + 898 00dc FFF7FEFF bl HAL_GPIO_WritePin + 899 .LVL82: +2250:Src/main.c **** break; + 900 .loc 1 2250 3 is_stmt 1 view .LVU292 + 901 00e0 0022 movs r2, #0 + 902 00e2 2021 movs r1, #32 + 903 00e4 2046 mov r0, r4 + 904 00e6 FFF7FEFF bl HAL_GPIO_WritePin + 905 .LVL83: +2251:Src/main.c **** + 906 .loc 1 2251 2 view .LVU293 + 907 00ea A0E7 b .L29 + 908 .LVL84: + 909 .L33: +2254:Src/main.c **** HAL_GPIO_WritePin(OUT_8_GPIO_Port, OUT_8_Pin, GPIO_PIN_RESET); + 910 .loc 1 2254 3 view .LVU294 + 911 00ec 0C4C ldr r4, .L44+4 + 912 00ee 0122 movs r2, #1 + 913 00f0 4021 movs r1, #64 + 914 00f2 2046 mov r0, r4 + 915 .LVL85: +2254:Src/main.c **** HAL_GPIO_WritePin(OUT_8_GPIO_Port, OUT_8_Pin, GPIO_PIN_RESET); + 916 .loc 1 2254 3 is_stmt 0 view .LVU295 + 917 00f4 FFF7FEFF bl HAL_GPIO_WritePin + 918 .LVL86: +2255:Src/main.c **** break; + 919 .loc 1 2255 3 is_stmt 1 view .LVU296 + 920 00f8 0022 movs r2, #0 + ARM GAS /tmp/ccWQNJQt.s page 105 + + + 921 00fa 4021 movs r1, #64 + 922 00fc 2046 mov r0, r4 + 923 00fe FFF7FEFF bl HAL_GPIO_WritePin + 924 .LVL87: +2256:Src/main.c **** + 925 .loc 1 2256 2 view .LVU297 + 926 0102 94E7 b .L29 + 927 .LVL88: + 928 .L31: +2259:Src/main.c **** HAL_GPIO_WritePin(OUT_9_GPIO_Port, OUT_9_Pin, GPIO_PIN_RESET); + 929 .loc 1 2259 3 view .LVU298 + 930 0104 064C ldr r4, .L44+4 + 931 0106 0122 movs r2, #1 + 932 0108 8021 movs r1, #128 + 933 010a 2046 mov r0, r4 + 934 .LVL89: +2259:Src/main.c **** HAL_GPIO_WritePin(OUT_9_GPIO_Port, OUT_9_Pin, GPIO_PIN_RESET); + 935 .loc 1 2259 3 is_stmt 0 view .LVU299 + 936 010c FFF7FEFF bl HAL_GPIO_WritePin + 937 .LVL90: +2260:Src/main.c **** break; + 938 .loc 1 2260 3 is_stmt 1 view .LVU300 + 939 0110 0022 movs r2, #0 + 940 0112 8021 movs r1, #128 + 941 0114 2046 mov r0, r4 + 942 0116 FFF7FEFF bl HAL_GPIO_WritePin + 943 .LVL91: +2261:Src/main.c **** } + 944 .loc 1 2261 2 view .LVU301 +2263:Src/main.c **** + 945 .loc 1 2263 1 is_stmt 0 view .LVU302 + 946 011a 88E7 b .L29 + 947 .L45: + 948 .align 2 + 949 .L44: + 950 011c 00180240 .word 1073879040 + 951 0120 00040240 .word 1073873920 + 952 .cfi_endproc + 953 .LFE1210: + 955 .section .text.MPhD_T,"ax",%progbits + 956 .align 1 + 957 .syntax unified + 958 .thumb + 959 .thumb_func + 961 MPhD_T: + 962 .LVL92: + 963 .LFB1212: +2323:Src/main.c **** uint16_t P; + 964 .loc 1 2323 1 is_stmt 1 view -0 + 965 .cfi_startproc + 966 @ args = 0, pretend = 0, frame = 0 + 967 @ frame_needed = 0, uses_anonymous_args = 0 +2323:Src/main.c **** uint16_t P; + 968 .loc 1 2323 1 is_stmt 0 view .LVU304 + 969 0000 38B5 push {r3, r4, r5, lr} + 970 .LCFI10: + 971 .cfi_def_cfa_offset 16 + ARM GAS /tmp/ccWQNJQt.s page 106 + + + 972 .cfi_offset 3, -16 + 973 .cfi_offset 4, -12 + 974 .cfi_offset 5, -8 + 975 .cfi_offset 14, -4 + 976 0002 0446 mov r4, r0 +2324:Src/main.c **** uint32_t tmp32; + 977 .loc 1 2324 2 is_stmt 1 view .LVU305 +2325:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion + 978 .loc 1 2325 2 view .LVU306 +2326:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion + 979 .loc 1 2326 2 view .LVU307 + 980 0004 0022 movs r2, #0 + 981 0006 4FF48041 mov r1, #16384 + 982 000a 8148 ldr r0, .L87 + 983 .LVL93: +2326:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_RESET);//Prepare conversion + 984 .loc 1 2326 2 is_stmt 0 view .LVU308 + 985 000c FFF7FEFF bl HAL_GPIO_WritePin + 986 .LVL94: +2327:Src/main.c **** tmp32=0; + 987 .loc 1 2327 2 is_stmt 1 view .LVU309 + 988 0010 0022 movs r2, #0 + 989 0012 4FF40071 mov r1, #512 + 990 0016 7F48 ldr r0, .L87+4 + 991 0018 FFF7FEFF bl HAL_GPIO_WritePin + 992 .LVL95: +2328:Src/main.c **** while(tmp32<500){tmp32++;} + 993 .loc 1 2328 2 view .LVU310 +2329:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver + 994 .loc 1 2329 2 view .LVU311 +2328:Src/main.c **** while(tmp32<500){tmp32++;} + 995 .loc 1 2328 7 is_stmt 0 view .LVU312 + 996 001c 0023 movs r3, #0 +2329:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver + 997 .loc 1 2329 7 view .LVU313 + 998 001e 00E0 b .L47 + 999 .LVL96: + 1000 .L48: +2329:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver + 1001 .loc 1 2329 19 is_stmt 1 discriminator 2 view .LVU314 +2329:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver + 1002 .loc 1 2329 24 is_stmt 0 discriminator 2 view .LVU315 + 1003 0020 0133 adds r3, r3, #1 + 1004 .LVL97: + 1005 .L47: +2329:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver + 1006 .loc 1 2329 13 is_stmt 1 discriminator 1 view .LVU316 + 1007 0022 B3F5FA7F cmp r3, #500 + 1008 0026 FBD3 bcc .L48 +2330:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI5_CNV_Pin, GPIO_PIN_SET);//Stop acqusition & start conver + 1009 .loc 1 2330 2 view .LVU317 + 1010 0028 0122 movs r2, #1 + 1011 002a 4FF48041 mov r1, #16384 + 1012 002e 7848 ldr r0, .L87 + 1013 0030 FFF7FEFF bl HAL_GPIO_WritePin + 1014 .LVL98: +2331:Src/main.c **** tmp32=0; + ARM GAS /tmp/ccWQNJQt.s page 107 + + + 1015 .loc 1 2331 2 view .LVU318 + 1016 0034 0122 movs r2, #1 + 1017 0036 4FF40071 mov r1, #512 + 1018 003a 7648 ldr r0, .L87+4 + 1019 003c FFF7FEFF bl HAL_GPIO_WritePin + 1020 .LVL99: +2332:Src/main.c **** while(tmp32<500){tmp32++;} + 1021 .loc 1 2332 2 view .LVU319 +2333:Src/main.c **** if (num==1)//MPD1 + 1022 .loc 1 2333 2 view .LVU320 +2332:Src/main.c **** while(tmp32<500){tmp32++;} + 1023 .loc 1 2332 7 is_stmt 0 view .LVU321 + 1024 0040 0023 movs r3, #0 +2333:Src/main.c **** if (num==1)//MPD1 + 1025 .loc 1 2333 7 view .LVU322 + 1026 0042 00E0 b .L49 + 1027 .LVL100: + 1028 .L50: +2333:Src/main.c **** if (num==1)//MPD1 + 1029 .loc 1 2333 19 is_stmt 1 discriminator 2 view .LVU323 +2333:Src/main.c **** if (num==1)//MPD1 + 1030 .loc 1 2333 24 is_stmt 0 discriminator 2 view .LVU324 + 1031 0044 0133 adds r3, r3, #1 + 1032 .LVL101: + 1033 .L49: +2333:Src/main.c **** if (num==1)//MPD1 + 1034 .loc 1 2333 13 is_stmt 1 discriminator 1 view .LVU325 + 1035 0046 B3F5FA7F cmp r3, #500 + 1036 004a FBD3 bcc .L50 +2334:Src/main.c **** { + 1037 .loc 1 2334 2 view .LVU326 + 1038 004c 631E subs r3, r4, #1 + 1039 .LVL102: +2334:Src/main.c **** { + 1040 .loc 1 2334 2 is_stmt 0 view .LVU327 + 1041 004e 032B cmp r3, #3 + 1042 0050 39D8 bhi .L51 + 1043 0052 DFE803F0 tbb [pc, r3] + 1044 .L53: + 1045 0056 02 .byte (.L56-.L53)/2 + 1046 0057 3A .byte (.L55-.L53)/2 + 1047 0058 6F .byte (.L54-.L53)/2 + 1048 0059 A6 .byte (.L52-.L53)/2 + 1049 .p2align 1 + 1050 .L56: +2336:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_RESET); + 1051 .loc 1 2336 3 is_stmt 1 view .LVU328 + 1052 005a 6D4C ldr r4, .L87 + 1053 .LVL103: +2336:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD1_CS_GPIO_Port, ADC_MPD1_CS_Pin, GPIO_PIN_RESET); + 1054 .loc 1 2336 3 is_stmt 0 view .LVU329 + 1055 005c 0122 movs r2, #1 + 1056 005e 4FF40061 mov r1, #2048 + 1057 0062 2046 mov r0, r4 + 1058 0064 FFF7FEFF bl HAL_GPIO_WritePin + 1059 .LVL104: +2337:Src/main.c **** tmp32=0; + ARM GAS /tmp/ccWQNJQt.s page 108 + + + 1060 .loc 1 2337 3 is_stmt 1 view .LVU330 + 1061 0068 0022 movs r2, #0 + 1062 006a 4FF48061 mov r1, #1024 + 1063 006e 2046 mov r0, r4 + 1064 0070 FFF7FEFF bl HAL_GPIO_WritePin + 1065 .LVL105: +2338:Src/main.c **** while(tmp32<500){tmp32++;} + 1066 .loc 1 2338 3 view .LVU331 +2339:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + 1067 .loc 1 2339 3 view .LVU332 +2338:Src/main.c **** while(tmp32<500){tmp32++;} + 1068 .loc 1 2338 8 is_stmt 0 view .LVU333 + 1069 0074 0023 movs r3, #0 +2339:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + 1070 .loc 1 2339 8 view .LVU334 + 1071 0076 00E0 b .L57 + 1072 .LVL106: + 1073 .L58: +2339:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + 1074 .loc 1 2339 20 is_stmt 1 discriminator 2 view .LVU335 +2339:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + 1075 .loc 1 2339 25 is_stmt 0 discriminator 2 view .LVU336 + 1076 0078 0133 adds r3, r3, #1 + 1077 .LVL107: + 1078 .L57: +2339:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + 1079 .loc 1 2339 14 is_stmt 1 discriminator 1 view .LVU337 + 1080 007a B3F5FA7F cmp r3, #500 + 1081 007e FBD3 bcc .L58 +2341:Src/main.c **** tmp32 = 0; + 1082 .loc 1 2341 3 view .LVU338 + 1083 .LVL108: + 1084 .LBB302: + 1085 .LBI302: + 1086 .file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @file stm32f7xx_ll_spi.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Header file of SPI LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * This software is licensed under terms that can be found in the LICENSE file + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * in the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #ifndef STM32F7xx_LL_SPI_H + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define STM32F7xx_LL_SPI_H + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + ARM GAS /tmp/ccWQNJQt.s page 109 + + + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #ifdef __cplusplus + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** extern "C" { + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Includes ------------------------------------------------------------------*/ + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #include "stm32f7xx.h" + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @addtogroup STM32F7xx_LL_Driver + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defin + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL SPI + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private types -------------------------------------------------------------*/ + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private variables ---------------------------------------------------------*/ + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private macros ------------------------------------------------------------*/ + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported types ------------------------------------------------------------*/ + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief SPI Init structures definition + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** typedef struct + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mod + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_TRANSFER_M + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_MODE. + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t DataWidth; /*!< Specifies the SPI data width. + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_POLARITY. + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_PHASE. + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + ARM GAS /tmp/ccWQNJQt.s page 110 + + + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (N + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPR + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** @note The communication clock is derived from the master c + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_CRC_CALCUL + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter must be a number between Min_Data = 0x00 an + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } LL_SPI_InitTypeDef; + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */ + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported constants --------------------------------------------------------*/ + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Flags defines which can be used with LL_SPI_ReadReg function + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format erro + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_IT IT Defines + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + ARM GAS /tmp/ccWQNJQt.s page 111 + + + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty inter + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_MODE Operation Mode + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuratio + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as de + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_PHASE Clock Phase + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition i + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_POLARITY Clock Polarity + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< Baud + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< Baud + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< Baud + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< Baud + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< Baud + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< Baud + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< Baud + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< Baud + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + ARM GAS /tmp/ccWQNJQt.s page 112 + + + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/recei + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/recei + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mo + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mod + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed inter + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in I + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in O + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled + ARM GAS /tmp/ccWQNJQt.s page 113 + + + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */ + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */ + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */ + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated i + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated i + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception em + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/ + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/ + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception fu + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */ + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */ + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + ARM GAS /tmp/ccWQNJQt.s page 114 + + + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported macro ------------------------------------------------------------*/ + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Write a value in SPI register + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __INSTANCE__ SPI Instance + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __REG__ Register to be written + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __VALUE__ Value to be written in the register + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Read a value in SPI register + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __INSTANCE__ SPI Instance + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __REG__ Register to be read + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Register value + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported functions --------------------------------------------------------*/ + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_Configuration Configuration + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable SPI peripheral + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_Enable + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) + 1087 .loc 4 358 22 view .LVU339 + 1088 .LBB303: + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_SPE); + 1089 .loc 4 360 3 view .LVU340 + 1090 0080 654A ldr r2, .L87+8 + ARM GAS /tmp/ccWQNJQt.s page 115 + + + 1091 0082 1368 ldr r3, [r2] + 1092 .LVL109: + 1093 .loc 4 360 3 is_stmt 0 view .LVU341 + 1094 0084 43F04003 orr r3, r3, #64 + 1095 0088 1360 str r3, [r2] + 1096 .LVL110: + 1097 .loc 4 360 3 view .LVU342 + 1098 .LBE303: + 1099 .LBE302: +2342:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w + 1100 .loc 1 2342 3 is_stmt 1 view .LVU343 +2343:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC + 1101 .loc 1 2343 3 view .LVU344 +2342:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w + 1102 .loc 1 2342 9 is_stmt 0 view .LVU345 + 1103 008a 0023 movs r3, #0 + 1104 .LVL111: + 1105 .L59: +2343:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC + 1106 .loc 1 2343 43 is_stmt 1 discriminator 1 view .LVU346 + 1107 .LBB304: + 1108 .LBI304: + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable SPI peripheral + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note When disabling the SPI, follow the procedure described in the Reference Manual. + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_Disable + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if SPI peripheral is enabled + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_IsEnabled + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set SPI operation mode to Master or Slave + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 MSTR LL_SPI_SetMode\n + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 SSI LL_SPI_SetMode + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Mode This parameter can be one of the following values: + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_MASTER + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_SLAVE + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + ARM GAS /tmp/ccWQNJQt.s page 116 + + + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get SPI operation mode (Master or Slave) + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 MSTR LL_SPI_GetMode\n + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 SSI LL_SPI_GetMode + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_MASTER + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_SLAVE + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set serial protocol used + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRF LL_SPI_SetStandard + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Standard This parameter can be one of the following values: + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_TI + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get serial protocol used + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRF LL_SPI_GetStandard + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_TI + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set clock phase + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * This bit is not used in SPI TI mode. + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPHA LL_SPI_SetClockPhase + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param ClockPhase This parameter can be one of the following values: + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_1EDGE + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_2EDGE + ARM GAS /tmp/ccWQNJQt.s page 117 + + + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get clock phase + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPHA LL_SPI_GetClockPhase + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_1EDGE + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_2EDGE + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set clock polarity + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * This bit is not used in SPI TI mode. + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param ClockPolarity This parameter can be one of the following values: + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_LOW + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_HIGH + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get clock polarity + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_LOW + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_HIGH + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set baud rate prescaler + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Pr + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param BaudRate This parameter can be one of the following values: + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + ARM GAS /tmp/ccWQNJQt.s page 118 + + + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get baud rate prescaler + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set transfer bit order + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param BitOrder This parameter can be one of the following values: + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_LSB_FIRST + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MSB_FIRST + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get transfer bit order + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_LSB_FIRST + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MSB_FIRST + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + ARM GAS /tmp/ccWQNJQt.s page 119 + + + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set transfer direction mode + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note For Half-Duplex mode, Rx Direction is set by default. + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-D + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIMODE LL_SPI_SetTransferDirection\n + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIOE LL_SPI_SetTransferDirection + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param TransferDirection This parameter can be one of the following values: + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_FULL_DUPLEX + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_SIMPLEX_RX + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_RX + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_TX + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get transfer direction mode + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIMODE LL_SPI_GetTransferDirection\n + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIOE LL_SPI_GetTransferDirection + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_FULL_DUPLEX + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_SIMPLEX_RX + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_RX + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_TX + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set frame data width + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 DS LL_SPI_SetDataWidth + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param DataWidth This parameter can be one of the following values: + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_4BIT + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_5BIT + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_6BIT + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_7BIT + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_8BIT + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_9BIT + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_10BIT + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_11BIT + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_12BIT + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_13BIT + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_14BIT + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_15BIT + ARM GAS /tmp/ccWQNJQt.s page 120 + + + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_16BIT + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth); + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get frame data width + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 DS LL_SPI_GetDataWidth + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_4BIT + 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_5BIT + 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_6BIT + 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_7BIT + 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_8BIT + 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_9BIT + 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_10BIT + 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_11BIT + 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_12BIT + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_13BIT + 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_14BIT + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_15BIT + 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_16BIT + 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) + 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); + 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set threshold of RXFIFO that triggers an RXNE event + 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold + 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Threshold This parameter can be one of the following values: + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_HALF + 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) + 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold); + 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get threshold of RXFIFO that triggers an RXNE event + 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold + 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_HALF + 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER + 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) + 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); + ARM GAS /tmp/ccWQNJQt.s page 121 + + + 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_CRC_Management CRC Management + 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable CRC + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_EnableCRC + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) + 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); + 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable CRC + 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_DisableCRC + 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) + 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); + 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if CRC is enabled + 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC + 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) + 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); + 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set CRC Length + 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth + 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param CRCLength This parameter can be one of the following values: + 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_8BIT + 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_16BIT + 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) + ARM GAS /tmp/ccWQNJQt.s page 122 + + + 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength); + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get CRC Length + 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth + 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_8BIT + 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_16BIT + 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) + 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); + 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set CRCNext to transfer CRC on the line + 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. + 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext + 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) + 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); + 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set polynomial for CRC calculation + 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial + 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF + 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) + 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly); + 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get polynomial for CRC calculation + 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial + 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) + 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->CRCPR)); + 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get Rx CRC + 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC + 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + ARM GAS /tmp/ccWQNJQt.s page 123 + + + 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) + 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->RXCRCR)); + 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get Tx CRC + 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC + 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) + 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->TXCRCR)); + 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management + 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set NSS mode + 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. + 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n + 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 SSOE LL_SPI_SetNSSMode + 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param NSS This parameter can be one of the following values: + 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_SOFT + 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_INPUT + 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_OUTPUT + 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) + 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); + 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); + 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get NSS mode + 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n + 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 SSOE LL_SPI_GetNSSMode + 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_SOFT + 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_INPUT + 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_OUTPUT + 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) + 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); + 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); + ARM GAS /tmp/ccWQNJQt.s page 124 + + + 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (Ssm | Ssoe); + 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable NSS pulse management + 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S + 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt + 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) + 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_NSSP); + 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable NSS pulse management + 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S + 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt + 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) + 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP); + 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if NSS pulse is enabled + 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S + 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse + 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) + 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); + 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management + 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Rx buffer is not empty + 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE + 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) + 1109 .loc 4 905 26 view .LVU347 + 1110 .LBB305: + 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + ARM GAS /tmp/ccWQNJQt.s page 125 + + + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); + 1111 .loc 4 907 3 view .LVU348 + 1112 .loc 4 907 12 is_stmt 0 view .LVU349 + 1113 008c 624A ldr r2, .L87+8 + 1114 008e 9268 ldr r2, [r2, #8] + 1115 .loc 4 907 68 view .LVU350 + 1116 0090 12F0010F tst r2, #1 + 1117 0094 04D1 bne .L60 + 1118 .LVL112: + 1119 .loc 4 907 68 view .LVU351 + 1120 .LBE305: + 1121 .LBE304: +2343:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC + 1122 .loc 1 2343 43 discriminator 2 view .LVU352 + 1123 0096 B3F57A7F cmp r3, #1000 + 1124 009a 01D8 bhi .L60 +2343:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC + 1125 .loc 1 2343 62 is_stmt 1 discriminator 3 view .LVU353 +2343:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC + 1126 .loc 1 2343 67 is_stmt 0 discriminator 3 view .LVU354 + 1127 009c 0133 adds r3, r3, #1 + 1128 .LVL113: +2343:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for MPhD1 ADC + 1129 .loc 1 2343 67 discriminator 3 view .LVU355 + 1130 009e F5E7 b .L59 + 1131 .L60: +2344:Src/main.c **** while(tmp32<500){tmp32++;} + 1132 .loc 1 2344 3 is_stmt 1 view .LVU356 + 1133 .LVL114: + 1134 .LBB306: + 1135 .LBI306: + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 1136 .loc 4 370 22 view .LVU357 + 1137 .LBB307: + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1138 .loc 4 372 3 view .LVU358 + 1139 00a0 5D49 ldr r1, .L87+8 + 1140 00a2 0A68 ldr r2, [r1] + 1141 00a4 22F04002 bic r2, r2, #64 + 1142 00a8 0A60 str r2, [r1] + 1143 .LVL115: + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1144 .loc 4 372 3 is_stmt 0 view .LVU359 + 1145 .LBE307: + 1146 .LBE306: +2345:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); + 1147 .loc 1 2345 3 is_stmt 1 view .LVU360 + 1148 .LBB309: + 1149 .LBB308: + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 1150 .loc 4 373 1 is_stmt 0 view .LVU361 + 1151 00aa 00E0 b .L62 + 1152 .L63: + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 1153 .loc 4 373 1 view .LVU362 + 1154 .LBE308: + 1155 .LBE309: + ARM GAS /tmp/ccWQNJQt.s page 126 + + +2345:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); + 1156 .loc 1 2345 20 is_stmt 1 discriminator 2 view .LVU363 +2345:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); + 1157 .loc 1 2345 25 is_stmt 0 discriminator 2 view .LVU364 + 1158 00ac 0133 adds r3, r3, #1 + 1159 .LVL116: + 1160 .L62: +2345:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); + 1161 .loc 1 2345 14 is_stmt 1 discriminator 1 view .LVU365 + 1162 00ae B3F5FA7F cmp r3, #500 + 1163 00b2 FBD3 bcc .L63 +2347:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); + 1164 .loc 1 2347 3 view .LVU366 + 1165 00b4 0122 movs r2, #1 + 1166 00b6 4FF48061 mov r1, #1024 + 1167 00ba 5548 ldr r0, .L87 + 1168 00bc FFF7FEFF bl HAL_GPIO_WritePin + 1169 .LVL117: +2348:Src/main.c **** } + 1170 .loc 1 2348 3 view .LVU367 + 1171 .LBB310: + 1172 .LBI310: + 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Tx buffer is empty + 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE + 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) + 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); + 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get CRC error flag + 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR + 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) + 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); + 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get mode fault error flag + 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF + 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) + 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); + 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + ARM GAS /tmp/ccWQNJQt.s page 127 + + + 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get overrun error flag + 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR + 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) + 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); + 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get busy flag + 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note The BSY flag is cleared under any one of the following conditions: + 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -When the SPI is correctly disabled + 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -When a fault is detected in Master mode (MODF bit set to 1) + 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -In Master mode, when it finishes a data transmission and no new data is ready to be + 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * sent + 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between + 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * each data transfer. + 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY + 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) + 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); + 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get frame format error flag + 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE + 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) + 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); + 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get FIFO reception Level + 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel + 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_EMPTY + 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL + 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_HALF_FULL + 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_FULL + 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) + 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); + 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get FIFO Transmission Level + ARM GAS /tmp/ccWQNJQt.s page 128 + + +1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel +1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: +1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_EMPTY +1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL +1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_HALF_FULL +1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_FULL +1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) +1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); +1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear CRC error flag +1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR +1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) +1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); +1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear mode fault error flag +1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note Clearing this flag is done by a read access to the SPIx_SR +1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * register followed by a write access to the SPIx_CR1 register +1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR MODF LL_SPI_ClearFlag_MODF +1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) +1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint32_t tmpreg_sr; +1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg_sr = SPIx->SR; +1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg_sr; +1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear overrun error flag +1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note Clearing this flag is done by a read access to the SPIx_DR +1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * register followed by a read access to the SPIx_SR register +1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR OVR LL_SPI_ClearFlag_OVR +1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint32_t tmpreg; +1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg = SPIx->DR; +1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg; +1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg = SPIx->SR; +1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg; +1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + ARM GAS /tmp/ccWQNJQt.s page 129 + + +1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear frame format error flag +1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note Clearing this flag is done by reading SPIx_SR register +1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FRE LL_SPI_ClearFlag_FRE +1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) +1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint32_t tmpreg; +1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg = SPIx->SR; +1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg; +1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_IT_Management Interrupt Management +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable error interrupt +1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR +1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR +1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) +1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); +1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable Rx buffer not empty interrupt +1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE +1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) +1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable Tx buffer empty interrupt +1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE +1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) +1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); +1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + ARM GAS /tmp/ccWQNJQt.s page 130 + + +1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable error interrupt +1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR +1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR +1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) +1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); +1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable Rx buffer not empty interrupt +1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE +1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) +1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable Tx buffer empty interrupt +1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE +1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) +1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); +1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if error interrupt is enabled +1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR +1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). +1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); +1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Rx buffer not empty interrupt is enabled +1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE +1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). +1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); +1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Tx buffer empty interrupt + ARM GAS /tmp/ccWQNJQt.s page 131 + + +1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE +1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). +1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); +1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_DMA_Management DMA Management +1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable DMA Rx +1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX +1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) +1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable DMA Rx +1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX +1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) +1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if DMA Rx is enabled +1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX +1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). +1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); +1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable DMA Tx +1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX +1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) + ARM GAS /tmp/ccWQNJQt.s page 132 + + +1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable DMA Tx +1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX +1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) +1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if DMA Tx is enabled +1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX +1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). +1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); +1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set parity of Last DMA reception +1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX +1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Parity This parameter can be one of the following values: +1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD +1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN +1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) +1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos)); +1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get parity configuration for Last DMA reception +1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX +1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: +1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD +1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN +1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) +1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); +1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set parity of Last DMA transmission +1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX +1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + ARM GAS /tmp/ccWQNJQt.s page 133 + + +1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Parity This parameter can be one of the following values: +1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD +1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN +1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) +1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos)); +1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get parity configuration for Last DMA transmission +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX +1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: +1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD +1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN +1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) +1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); +1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get the data register address used for DMA transfer +1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_DMA_GetRegAddr +1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Address of data register +1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t) &(SPIx->DR); +1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_DATA_Management DATA Management +1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Read 8-Bits in the data register +1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_ReceiveData8 +1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF +1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) +1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (*((__IO uint8_t *)&SPIx->DR)); +1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Read 16-Bits in the data register +1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_ReceiveData16 +1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + ARM GAS /tmp/ccWQNJQt.s page 134 + + +1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF +1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) + 1173 .loc 4 1344 26 view .LVU368 + 1174 .LBB311: +1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint16_t)(READ_REG(SPIx->DR)); + 1175 .loc 4 1346 3 view .LVU369 + 1176 .loc 4 1346 21 is_stmt 0 view .LVU370 + 1177 00c0 554B ldr r3, .L87+8 + 1178 00c2 DD68 ldr r5, [r3, #12] + 1179 .loc 4 1346 10 view .LVU371 + 1180 00c4 ADB2 uxth r5, r5 + 1181 .LVL118: + 1182 .L51: + 1183 .loc 4 1346 10 view .LVU372 + 1184 .LBE311: + 1185 .LBE310: +2420:Src/main.c **** } + 1186 .loc 1 2420 2 is_stmt 1 view .LVU373 +2421:Src/main.c **** /*static uint16_t Temp_LD(uint16_t T_LD_before, uint16_t T_LD, uint32_t Timer_before, uint32_t Time + 1187 .loc 1 2421 1 is_stmt 0 view .LVU374 + 1188 00c6 2846 mov r0, r5 + 1189 00c8 38BD pop {r3, r4, r5, pc} + 1190 .LVL119: + 1191 .L55: +2352:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_RESET); + 1192 .loc 1 2352 3 is_stmt 1 view .LVU375 + 1193 00ca 524C ldr r4, .L87+4 + 1194 00cc 0122 movs r2, #1 + 1195 00ce 4FF48061 mov r1, #1024 + 1196 00d2 2046 mov r0, r4 + 1197 00d4 FFF7FEFF bl HAL_GPIO_WritePin + 1198 .LVL120: +2353:Src/main.c **** tmp32=0; + 1199 .loc 1 2353 3 view .LVU376 + 1200 00d8 0022 movs r2, #0 + 1201 00da 4021 movs r1, #64 + 1202 00dc 2046 mov r0, r4 + 1203 00de FFF7FEFF bl HAL_GPIO_WritePin + 1204 .LVL121: +2354:Src/main.c **** while(tmp32<500){tmp32++;} + 1205 .loc 1 2354 3 view .LVU377 +2355:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + 1206 .loc 1 2355 3 view .LVU378 +2354:Src/main.c **** while(tmp32<500){tmp32++;} + 1207 .loc 1 2354 8 is_stmt 0 view .LVU379 + 1208 00e2 0023 movs r3, #0 +2355:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + 1209 .loc 1 2355 8 view .LVU380 + 1210 00e4 00E0 b .L64 + 1211 .LVL122: + 1212 .L65: +2355:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + 1213 .loc 1 2355 20 is_stmt 1 discriminator 2 view .LVU381 +2355:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + 1214 .loc 1 2355 25 is_stmt 0 discriminator 2 view .LVU382 + ARM GAS /tmp/ccWQNJQt.s page 135 + + + 1215 00e6 0133 adds r3, r3, #1 + 1216 .LVL123: + 1217 .L64: +2355:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + 1218 .loc 1 2355 14 is_stmt 1 discriminator 1 view .LVU383 + 1219 00e8 B3F5FA7F cmp r3, #500 + 1220 00ec FBD3 bcc .L65 +2357:Src/main.c **** tmp32 = 0; + 1221 .loc 1 2357 3 view .LVU384 + 1222 .LVL124: + 1223 .LBB312: + 1224 .LBI312: + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 1225 .loc 4 358 22 view .LVU385 + 1226 .LBB313: + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1227 .loc 4 360 3 view .LVU386 + 1228 00ee 4B4A ldr r2, .L87+12 + 1229 00f0 1368 ldr r3, [r2] + 1230 .LVL125: + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1231 .loc 4 360 3 is_stmt 0 view .LVU387 + 1232 00f2 43F04003 orr r3, r3, #64 + 1233 00f6 1360 str r3, [r2] + 1234 .LVL126: + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1235 .loc 4 360 3 view .LVU388 + 1236 .LBE313: + 1237 .LBE312: +2358:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w + 1238 .loc 1 2358 3 is_stmt 1 view .LVU389 +2359:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC + 1239 .loc 1 2359 3 view .LVU390 +2358:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w + 1240 .loc 1 2358 9 is_stmt 0 view .LVU391 + 1241 00f8 0023 movs r3, #0 + 1242 .LVL127: + 1243 .L66: +2359:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC + 1244 .loc 1 2359 43 is_stmt 1 discriminator 1 view .LVU392 + 1245 .LBB314: + 1246 .LBI314: + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 1247 .loc 4 905 26 view .LVU393 + 1248 .LBB315: + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1249 .loc 4 907 3 view .LVU394 + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1250 .loc 4 907 12 is_stmt 0 view .LVU395 + 1251 00fa 484A ldr r2, .L87+12 + 1252 00fc 9268 ldr r2, [r2, #8] + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1253 .loc 4 907 68 view .LVU396 + 1254 00fe 12F0010F tst r2, #1 + 1255 0102 04D1 bne .L67 + 1256 .LVL128: + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + ARM GAS /tmp/ccWQNJQt.s page 136 + + + 1257 .loc 4 907 68 view .LVU397 + 1258 .LBE315: + 1259 .LBE314: +2359:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC + 1260 .loc 1 2359 43 discriminator 2 view .LVU398 + 1261 0104 B3F57A7F cmp r3, #1000 + 1262 0108 01D8 bhi .L67 +2359:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC + 1263 .loc 1 2359 62 is_stmt 1 discriminator 3 view .LVU399 +2359:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC + 1264 .loc 1 2359 67 is_stmt 0 discriminator 3 view .LVU400 + 1265 010a 0133 adds r3, r3, #1 + 1266 .LVL129: +2359:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for MPhD2 ADC + 1267 .loc 1 2359 67 discriminator 3 view .LVU401 + 1268 010c F5E7 b .L66 + 1269 .L67: +2360:Src/main.c **** while(tmp32<500){tmp32++;} + 1270 .loc 1 2360 3 is_stmt 1 view .LVU402 + 1271 .LVL130: + 1272 .LBB316: + 1273 .LBI316: + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 1274 .loc 4 370 22 view .LVU403 + 1275 .LBB317: + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1276 .loc 4 372 3 view .LVU404 + 1277 010e 4349 ldr r1, .L87+12 + 1278 0110 0A68 ldr r2, [r1] + 1279 0112 22F04002 bic r2, r2, #64 + 1280 0116 0A60 str r2, [r1] + 1281 .LVL131: + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1282 .loc 4 372 3 is_stmt 0 view .LVU405 + 1283 .LBE317: + 1284 .LBE316: +2361:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); + 1285 .loc 1 2361 3 is_stmt 1 view .LVU406 + 1286 .LBB319: + 1287 .LBB318: + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 1288 .loc 4 373 1 is_stmt 0 view .LVU407 + 1289 0118 00E0 b .L69 + 1290 .L70: + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 1291 .loc 4 373 1 view .LVU408 + 1292 .LBE318: + 1293 .LBE319: +2361:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); + 1294 .loc 1 2361 20 is_stmt 1 discriminator 2 view .LVU409 +2361:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); + 1295 .loc 1 2361 25 is_stmt 0 discriminator 2 view .LVU410 + 1296 011a 0133 adds r3, r3, #1 + 1297 .LVL132: + 1298 .L69: +2361:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); + 1299 .loc 1 2361 14 is_stmt 1 discriminator 1 view .LVU411 + ARM GAS /tmp/ccWQNJQt.s page 137 + + + 1300 011c B3F5FA7F cmp r3, #500 + 1301 0120 FBD3 bcc .L70 +2363:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); + 1302 .loc 1 2363 3 view .LVU412 + 1303 0122 0122 movs r2, #1 + 1304 0124 4021 movs r1, #64 + 1305 0126 3B48 ldr r0, .L87+4 + 1306 0128 FFF7FEFF bl HAL_GPIO_WritePin + 1307 .LVL133: +2364:Src/main.c **** } + 1308 .loc 1 2364 3 view .LVU413 + 1309 .LBB320: + 1310 .LBI320: +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 1311 .loc 4 1344 26 view .LVU414 + 1312 .LBB321: + 1313 .loc 4 1346 3 view .LVU415 + 1314 .loc 4 1346 21 is_stmt 0 view .LVU416 + 1315 012c 3B4B ldr r3, .L87+12 + 1316 012e DD68 ldr r5, [r3, #12] + 1317 .loc 4 1346 10 view .LVU417 + 1318 0130 ADB2 uxth r5, r5 + 1319 .LVL134: + 1320 .loc 4 1346 10 view .LVU418 + 1321 .LBE321: + 1322 .LBE320: + 1323 0132 C8E7 b .L51 + 1324 .LVL135: + 1325 .L54: +2368:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD1_CS_GPIO_Port, ADC_ThrLD1_CS_Pin, GPIO_PIN_RESET); + 1326 .loc 1 2368 3 is_stmt 1 view .LVU419 + 1327 0134 364C ldr r4, .L87 + 1328 0136 0122 movs r2, #1 + 1329 0138 4FF48061 mov r1, #1024 + 1330 013c 2046 mov r0, r4 + 1331 013e FFF7FEFF bl HAL_GPIO_WritePin + 1332 .LVL136: +2369:Src/main.c **** tmp32=0; + 1333 .loc 1 2369 3 view .LVU420 + 1334 0142 0022 movs r2, #0 + 1335 0144 4FF40061 mov r1, #2048 + 1336 0148 2046 mov r0, r4 + 1337 014a FFF7FEFF bl HAL_GPIO_WritePin + 1338 .LVL137: +2370:Src/main.c **** while(tmp32<500){tmp32++;} + 1339 .loc 1 2370 3 view .LVU421 +2371:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + 1340 .loc 1 2371 3 view .LVU422 +2370:Src/main.c **** while(tmp32<500){tmp32++;} + 1341 .loc 1 2370 8 is_stmt 0 view .LVU423 + 1342 014e 0023 movs r3, #0 +2371:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + 1343 .loc 1 2371 8 view .LVU424 + 1344 0150 00E0 b .L71 + 1345 .LVL138: + 1346 .L72: +2371:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + ARM GAS /tmp/ccWQNJQt.s page 138 + + + 1347 .loc 1 2371 20 is_stmt 1 discriminator 2 view .LVU425 +2371:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + 1348 .loc 1 2371 25 is_stmt 0 discriminator 2 view .LVU426 + 1349 0152 0133 adds r3, r3, #1 + 1350 .LVL139: + 1351 .L71: +2371:Src/main.c **** //LL_SPI_TransmitData16(SPI4, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + 1352 .loc 1 2371 14 is_stmt 1 discriminator 1 view .LVU427 + 1353 0154 B3F5FA7F cmp r3, #500 + 1354 0158 FBD3 bcc .L72 +2373:Src/main.c **** tmp32 = 0; + 1355 .loc 1 2373 3 view .LVU428 + 1356 .LVL140: + 1357 .LBB322: + 1358 .LBI322: + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 1359 .loc 4 358 22 view .LVU429 + 1360 .LBB323: + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1361 .loc 4 360 3 view .LVU430 + 1362 015a 2F4A ldr r2, .L87+8 + 1363 015c 1368 ldr r3, [r2] + 1364 .LVL141: + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1365 .loc 4 360 3 is_stmt 0 view .LVU431 + 1366 015e 43F04003 orr r3, r3, #64 + 1367 0162 1360 str r3, [r2] + 1368 .LVL142: + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1369 .loc 4 360 3 view .LVU432 + 1370 .LBE323: + 1371 .LBE322: +2374:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w + 1372 .loc 1 2374 3 is_stmt 1 view .LVU433 +2375:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC + 1373 .loc 1 2375 3 view .LVU434 +2374:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI4))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w + 1374 .loc 1 2374 9 is_stmt 0 view .LVU435 + 1375 0164 0023 movs r3, #0 + 1376 .LVL143: + 1377 .L73: +2375:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC + 1378 .loc 1 2375 43 is_stmt 1 discriminator 1 view .LVU436 + 1379 .LBB324: + 1380 .LBI324: + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 1381 .loc 4 905 26 view .LVU437 + 1382 .LBB325: + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1383 .loc 4 907 3 view .LVU438 + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1384 .loc 4 907 12 is_stmt 0 view .LVU439 + 1385 0166 2C4A ldr r2, .L87+8 + 1386 0168 9268 ldr r2, [r2, #8] + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1387 .loc 4 907 68 view .LVU440 + 1388 016a 12F0010F tst r2, #1 + ARM GAS /tmp/ccWQNJQt.s page 139 + + + 1389 016e 04D1 bne .L74 + 1390 .LVL144: + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1391 .loc 4 907 68 view .LVU441 + 1392 .LBE325: + 1393 .LBE324: +2375:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC + 1394 .loc 1 2375 43 discriminator 2 view .LVU442 + 1395 0170 B3F57A7F cmp r3, #1000 + 1396 0174 01D8 bhi .L74 +2375:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC + 1397 .loc 1 2375 62 is_stmt 1 discriminator 3 view .LVU443 +2375:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC + 1398 .loc 1 2375 67 is_stmt 0 discriminator 3 view .LVU444 + 1399 0176 0133 adds r3, r3, #1 + 1400 .LVL145: +2375:Src/main.c **** LL_SPI_Disable(SPI4);//Enable SPI for ThrLD1 ADC + 1401 .loc 1 2375 67 discriminator 3 view .LVU445 + 1402 0178 F5E7 b .L73 + 1403 .L74: +2376:Src/main.c **** while(tmp32<500){tmp32++;} + 1404 .loc 1 2376 3 is_stmt 1 view .LVU446 + 1405 .LVL146: + 1406 .LBB326: + 1407 .LBI326: + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 1408 .loc 4 370 22 view .LVU447 + 1409 .LBB327: + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1410 .loc 4 372 3 view .LVU448 + 1411 017a 2749 ldr r1, .L87+8 + 1412 017c 0A68 ldr r2, [r1] + 1413 017e 22F04002 bic r2, r2, #64 + 1414 0182 0A60 str r2, [r1] + 1415 .LVL147: + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1416 .loc 4 372 3 is_stmt 0 view .LVU449 + 1417 .LBE327: + 1418 .LBE326: +2377:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); + 1419 .loc 1 2377 3 is_stmt 1 view .LVU450 + 1420 .LBB329: + 1421 .LBB328: + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 1422 .loc 4 373 1 is_stmt 0 view .LVU451 + 1423 0184 00E0 b .L76 + 1424 .L77: + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 1425 .loc 4 373 1 view .LVU452 + 1426 .LBE328: + 1427 .LBE329: +2377:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); + 1428 .loc 1 2377 20 is_stmt 1 discriminator 2 view .LVU453 +2377:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); + 1429 .loc 1 2377 25 is_stmt 0 discriminator 2 view .LVU454 + 1430 0186 0133 adds r3, r3, #1 + 1431 .LVL148: + ARM GAS /tmp/ccWQNJQt.s page 140 + + + 1432 .L76: +2377:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); + 1433 .loc 1 2377 14 is_stmt 1 discriminator 1 view .LVU455 + 1434 0188 B3F5FA7F cmp r3, #500 + 1435 018c FBD3 bcc .L77 +2379:Src/main.c **** P = LL_SPI_ReceiveData16(SPI4); + 1436 .loc 1 2379 3 view .LVU456 + 1437 018e 0122 movs r2, #1 + 1438 0190 4FF40061 mov r1, #2048 + 1439 0194 1E48 ldr r0, .L87 + 1440 0196 FFF7FEFF bl HAL_GPIO_WritePin + 1441 .LVL149: +2380:Src/main.c **** } + 1442 .loc 1 2380 3 view .LVU457 + 1443 .LBB330: + 1444 .LBI330: +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 1445 .loc 4 1344 26 view .LVU458 + 1446 .LBB331: + 1447 .loc 4 1346 3 view .LVU459 + 1448 .loc 4 1346 21 is_stmt 0 view .LVU460 + 1449 019a 1F4B ldr r3, .L87+8 + 1450 019c DD68 ldr r5, [r3, #12] + 1451 .loc 4 1346 10 view .LVU461 + 1452 019e ADB2 uxth r5, r5 + 1453 .LVL150: + 1454 .loc 4 1346 10 view .LVU462 + 1455 .LBE331: + 1456 .LBE330: + 1457 01a0 91E7 b .L51 + 1458 .LVL151: + 1459 .L52: +2384:Src/main.c **** HAL_GPIO_WritePin(ADC_ThrLD2_CS_GPIO_Port, ADC_ThrLD2_CS_Pin, GPIO_PIN_RESET); + 1460 .loc 1 2384 3 is_stmt 1 view .LVU463 + 1461 01a2 1C4C ldr r4, .L87+4 + 1462 01a4 0122 movs r2, #1 + 1463 01a6 4021 movs r1, #64 + 1464 01a8 2046 mov r0, r4 + 1465 01aa FFF7FEFF bl HAL_GPIO_WritePin + 1466 .LVL152: +2385:Src/main.c **** tmp32=0; + 1467 .loc 1 2385 3 view .LVU464 + 1468 01ae 0022 movs r2, #0 + 1469 01b0 4FF48061 mov r1, #1024 + 1470 01b4 2046 mov r0, r4 + 1471 01b6 FFF7FEFF bl HAL_GPIO_WritePin + 1472 .LVL153: +2386:Src/main.c **** while(tmp32<500){tmp32++;} + 1473 .loc 1 2386 3 view .LVU465 +2387:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + 1474 .loc 1 2387 3 view .LVU466 +2386:Src/main.c **** while(tmp32<500){tmp32++;} + 1475 .loc 1 2386 8 is_stmt 0 view .LVU467 + 1476 01ba 0023 movs r3, #0 +2387:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + 1477 .loc 1 2387 8 view .LVU468 + 1478 01bc 00E0 b .L78 + ARM GAS /tmp/ccWQNJQt.s page 141 + + + 1479 .LVL154: + 1480 .L79: +2387:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + 1481 .loc 1 2387 20 is_stmt 1 discriminator 2 view .LVU469 +2387:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + 1482 .loc 1 2387 25 is_stmt 0 discriminator 2 view .LVU470 + 1483 01be 0133 adds r3, r3, #1 + 1484 .LVL155: + 1485 .L78: +2387:Src/main.c **** //LL_SPI_TransmitData16(SPI5, 0xFFFF);//We must to clock the CLK output for collect RX data. We c + 1486 .loc 1 2387 14 is_stmt 1 discriminator 1 view .LVU471 + 1487 01c0 B3F5FA7F cmp r3, #500 + 1488 01c4 FBD3 bcc .L79 +2389:Src/main.c **** tmp32 = 0; + 1489 .loc 1 2389 3 view .LVU472 + 1490 .LVL156: + 1491 .LBB332: + 1492 .LBI332: + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 1493 .loc 4 358 22 view .LVU473 + 1494 .LBB333: + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1495 .loc 4 360 3 view .LVU474 + 1496 01c6 154A ldr r2, .L87+12 + 1497 01c8 1368 ldr r3, [r2] + 1498 .LVL157: + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1499 .loc 4 360 3 is_stmt 0 view .LVU475 + 1500 01ca 43F04003 orr r3, r3, #64 + 1501 01ce 1360 str r3, [r2] + 1502 .LVL158: + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1503 .loc 4 360 3 view .LVU476 + 1504 .LBE333: + 1505 .LBE332: +2390:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w + 1506 .loc 1 2390 3 is_stmt 1 view .LVU477 +2391:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC + 1507 .loc 1 2391 3 view .LVU478 +2390:Src/main.c **** while(((!LL_SPI_IsActiveFlag_RXNE(SPI5))&&(tmp32<=1000))) {tmp32++;}//When rec. last data cycle w + 1508 .loc 1 2390 9 is_stmt 0 view .LVU479 + 1509 01d0 0023 movs r3, #0 + 1510 .LVL159: + 1511 .L80: +2391:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC + 1512 .loc 1 2391 43 is_stmt 1 discriminator 1 view .LVU480 + 1513 .LBB334: + 1514 .LBI334: + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 1515 .loc 4 905 26 view .LVU481 + 1516 .LBB335: + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1517 .loc 4 907 3 view .LVU482 + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1518 .loc 4 907 12 is_stmt 0 view .LVU483 + 1519 01d2 124A ldr r2, .L87+12 + 1520 01d4 9268 ldr r2, [r2, #8] + ARM GAS /tmp/ccWQNJQt.s page 142 + + + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1521 .loc 4 907 68 view .LVU484 + 1522 01d6 12F0010F tst r2, #1 + 1523 01da 04D1 bne .L81 + 1524 .LVL160: + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1525 .loc 4 907 68 view .LVU485 + 1526 .LBE335: + 1527 .LBE334: +2391:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC + 1528 .loc 1 2391 43 discriminator 2 view .LVU486 + 1529 01dc B3F57A7F cmp r3, #1000 + 1530 01e0 01D8 bhi .L81 +2391:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC + 1531 .loc 1 2391 62 is_stmt 1 discriminator 3 view .LVU487 +2391:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC + 1532 .loc 1 2391 67 is_stmt 0 discriminator 3 view .LVU488 + 1533 01e2 0133 adds r3, r3, #1 + 1534 .LVL161: +2391:Src/main.c **** LL_SPI_Disable(SPI5);//Enable SPI for ThrLD2 ADC + 1535 .loc 1 2391 67 discriminator 3 view .LVU489 + 1536 01e4 F5E7 b .L80 + 1537 .L81: +2392:Src/main.c **** while(tmp32<500){tmp32++;} + 1538 .loc 1 2392 3 is_stmt 1 view .LVU490 + 1539 .LVL162: + 1540 .LBB336: + 1541 .LBI336: + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 1542 .loc 4 370 22 view .LVU491 + 1543 .LBB337: + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1544 .loc 4 372 3 view .LVU492 + 1545 01e6 0D49 ldr r1, .L87+12 + 1546 01e8 0A68 ldr r2, [r1] + 1547 01ea 22F04002 bic r2, r2, #64 + 1548 01ee 0A60 str r2, [r1] + 1549 .LVL163: + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 1550 .loc 4 372 3 is_stmt 0 view .LVU493 + 1551 .LBE337: + 1552 .LBE336: +2393:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); + 1553 .loc 1 2393 3 is_stmt 1 view .LVU494 + 1554 .LBB339: + 1555 .LBB338: + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 1556 .loc 4 373 1 is_stmt 0 view .LVU495 + 1557 01f0 00E0 b .L83 + 1558 .L84: + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 1559 .loc 4 373 1 view .LVU496 + 1560 .LBE338: + 1561 .LBE339: +2393:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); + 1562 .loc 1 2393 20 is_stmt 1 discriminator 2 view .LVU497 +2393:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); + ARM GAS /tmp/ccWQNJQt.s page 143 + + + 1563 .loc 1 2393 25 is_stmt 0 discriminator 2 view .LVU498 + 1564 01f2 0133 adds r3, r3, #1 + 1565 .LVL164: + 1566 .L83: +2393:Src/main.c **** //HAL_SPI_Receive(&hspi4, &P[0], 1, 100); + 1567 .loc 1 2393 14 is_stmt 1 discriminator 1 view .LVU499 + 1568 01f4 B3F5FA7F cmp r3, #500 + 1569 01f8 FBD3 bcc .L84 +2395:Src/main.c **** P = LL_SPI_ReceiveData16(SPI5); + 1570 .loc 1 2395 3 view .LVU500 + 1571 01fa 0122 movs r2, #1 + 1572 01fc 4FF48061 mov r1, #1024 + 1573 0200 0448 ldr r0, .L87+4 + 1574 0202 FFF7FEFF bl HAL_GPIO_WritePin + 1575 .LVL165: +2396:Src/main.c **** } + 1576 .loc 1 2396 3 view .LVU501 + 1577 .LBB340: + 1578 .LBI340: +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 1579 .loc 4 1344 26 view .LVU502 + 1580 .LBB341: + 1581 .loc 4 1346 3 view .LVU503 + 1582 .loc 4 1346 21 is_stmt 0 view .LVU504 + 1583 0206 054B ldr r3, .L87+12 + 1584 0208 DD68 ldr r5, [r3, #12] + 1585 .loc 4 1346 10 view .LVU505 + 1586 020a ADB2 uxth r5, r5 + 1587 .LVL166: + 1588 .loc 4 1346 10 view .LVU506 + 1589 020c 5BE7 b .L51 + 1590 .L88: + 1591 020e 00BF .align 2 + 1592 .L87: + 1593 0210 00100240 .word 1073876992 + 1594 0214 00140240 .word 1073878016 + 1595 0218 00340140 .word 1073820672 + 1596 021c 00500140 .word 1073827840 + 1597 .LBE341: + 1598 .LBE340: + 1599 .cfi_endproc + 1600 .LFE1212: + 1602 .section .text.Stop_TIM10,"ax",%progbits + 1603 .align 1 + 1604 .syntax unified + 1605 .thumb + 1606 .thumb_func + 1608 Stop_TIM10: + 1609 .LFB1223: +2561:Src/main.c **** uint8_t CheckChecksum(uint16_t *pbuff) +2562:Src/main.c **** { +2563:Src/main.c **** uint16_t cl_ind; +2564:Src/main.c **** +2565:Src/main.c **** switch (UART_header) +2566:Src/main.c **** { +2567:Src/main.c **** case 0x7777: +2568:Src/main.c **** cl_ind = TSK_16 - 2; + ARM GAS /tmp/ccWQNJQt.s page 144 + + +2569:Src/main.c **** break; +2570:Src/main.c **** case 0x1111: +2571:Src/main.c **** cl_ind = CL_16 - 2; +2572:Src/main.c **** break; +2573:Src/main.c **** default: +2574:Src/main.c **** return 0; +2575:Src/main.c **** break; +2576:Src/main.c **** } +2577:Src/main.c **** +2578:Src/main.c **** CS_result = CalculateChecksum(pbuff, cl_ind); +2579:Src/main.c **** +2580:Src/main.c **** return ((CS_result == COMMAND[cl_ind]) ? 1 : 0); +2581:Src/main.c **** } +2582:Src/main.c **** uint16_t CalculateChecksum(uint16_t *pbuff, uint16_t len) +2583:Src/main.c **** { +2584:Src/main.c **** short i; +2585:Src/main.c **** uint16_t cs = *pbuff; +2586:Src/main.c **** +2587:Src/main.c **** for(i = 1; i < len; i++) +2588:Src/main.c **** { +2589:Src/main.c **** cs ^= *(pbuff+i); +2590:Src/main.c **** } +2591:Src/main.c **** return cs; +2592:Src/main.c **** } +2593:Src/main.c **** +2594:Src/main.c **** /*int SD_Init(void) +2595:Src/main.c **** { +2596:Src/main.c **** int test=0; +2597:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) +2598:Src/main.c **** { +2599:Src/main.c **** test = Mount_SD("/"); +2600:Src/main.c **** if (test == 0) //0 - suc +2601:Src/main.c **** { +2602:Src/main.c **** //Format_SD(); +2603:Src/main.c **** test = Create_File("FILE1.TXT"); // 0 -suc +2604:Src/main.c **** //Create_File("FILE2.TXT"); +2605:Src/main.c **** Write_File ("FILE1.TXT", "____OSGG main borad information. Program made by Kazakov Viktor. Part +2606:Src/main.c **** test = Unmount_SD("/"); // 0 - succ +2607:Src/main.c **** return test; +2608:Src/main.c **** } +2609:Src/main.c **** else +2610:Src/main.c **** { +2611:Src/main.c **** return 1; +2612:Src/main.c **** } +2613:Src/main.c **** } +2614:Src/main.c **** else +2615:Src/main.c **** { +2616:Src/main.c **** return 1; +2617:Src/main.c **** } +2618:Src/main.c **** }*/ +2619:Src/main.c **** +2620:Src/main.c **** int SD_SAVE(uint16_t *pbuff) +2621:Src/main.c **** { +2622:Src/main.c **** int test=0; +2623:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) +2624:Src/main.c **** { +2625:Src/main.c **** test = Mount_SD("/"); + ARM GAS /tmp/ccWQNJQt.s page 145 + + +2626:Src/main.c **** if (test == 0) //0 - suc +2627:Src/main.c **** { +2628:Src/main.c **** //Format_SD(); +2629:Src/main.c **** test = Update_File_byte("FILE1.TXT", (uint8_t *)pbuff, DL_8); +2630:Src/main.c **** test = Unmount_SD("/"); // 0 - succ +2631:Src/main.c **** return test; +2632:Src/main.c **** } +2633:Src/main.c **** else +2634:Src/main.c **** { +2635:Src/main.c **** return 1; +2636:Src/main.c **** } +2637:Src/main.c **** } +2638:Src/main.c **** else +2639:Src/main.c **** { +2640:Src/main.c **** return 1; +2641:Src/main.c **** } +2642:Src/main.c **** } +2643:Src/main.c **** +2644:Src/main.c **** +2645:Src/main.c **** +2646:Src/main.c **** //uint32_t Get_Length(void) +2647:Src/main.c **** //{ +2648:Src/main.c **** // return SD_matr[0][0] + ((uint32_t) (SD_matr[0][1])<<16); +2649:Src/main.c **** //} +2650:Src/main.c **** +2651:Src/main.c **** int SD_READ(uint16_t *pbuff) +2652:Src/main.c **** { +2653:Src/main.c **** int test=0; +2654:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) +2655:Src/main.c **** { +2656:Src/main.c **** test = Mount_SD("/"); +2657:Src/main.c **** if (test == 0) //0 - suc +2658:Src/main.c **** { +2659:Src/main.c **** //Format_SD(); +2660:Src/main.c **** test = Seek_Read_File ("FILE1.TXT", (uint8_t *)pbuff, DL_8, fgoto);//Read next 246 bytes +2661:Src/main.c **** fgoto+=DL_8; +2662:Src/main.c **** test = Unmount_SD("/"); // 0 - succ +2663:Src/main.c **** return test; +2664:Src/main.c **** } +2665:Src/main.c **** else +2666:Src/main.c **** { +2667:Src/main.c **** return 1; +2668:Src/main.c **** } +2669:Src/main.c **** } +2670:Src/main.c **** else +2671:Src/main.c **** { +2672:Src/main.c **** return 1; +2673:Src/main.c **** } +2674:Src/main.c **** +2675:Src/main.c **** /* for (uint16_t j = 0; j < DL_16; j++) +2676:Src/main.c **** { +2677:Src/main.c **** *(pbuff+j) = SD_matr[SD_SLIDE][j]; +2678:Src/main.c **** } +2679:Src/main.c **** if (SD_SLIDEAHB1ENR, Periphs) == Periphs); + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_DisableClock\n + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n + ARM GAS /tmp/ccWQNJQt.s page 161 + + + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_DisableClock + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1ENR, Periphs); + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset + ARM GAS /tmp/ccWQNJQt.s page 162 + + + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1RSTR, Periphs); + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + ARM GAS /tmp/ccWQNJQt.s page 163 + + + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1RSTR, Periphs); + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB1 peripheral clocks in low-power mode + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR AXILPEN LL_AHB1_GRP1_EnableClockLowPower\n + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + ARM GAS /tmp/ccWQNJQt.s page 164 + + + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_AXI + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1LPENR, Periphs); + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB1 peripheral clocks in low-power mode + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR AXILPEN LL_AHB1_GRP1_DisableClockLowPower\n + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n + ARM GAS /tmp/ccWQNJQt.s page 165 + + + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_AXI + 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF + 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 + 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) + 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1LPENR, Periphs); + 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB2 AHB2 + 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB2 peripherals clock. + 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n + 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_EnableClock\n + 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n + 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n + 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n + 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n + 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock + ARM GAS /tmp/ccWQNJQt.s page 166 + + + 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) + 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2ENR, Periphs); + 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB2 peripheral clock is enabled or not + 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n + 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_IsEnabledClock\n + 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n + 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n + 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n + 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n + 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock + 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) + 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); + 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB2 peripherals clock. + 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n + 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_DisableClock\n + 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n + 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n + 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n + 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n + 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock + 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + ARM GAS /tmp/ccWQNJQt.s page 167 + + + 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) + 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2ENR, Periphs); + 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB2 peripherals reset. + 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n + 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR JPEGRST LL_AHB2_GRP1_ForceReset\n + 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n + 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n + 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n + 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n + 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset + 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) + 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2RSTR, Periphs); + 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB2 peripherals reset. + 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n + 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR JPEGRST LL_AHB2_GRP1_ReleaseReset\n + 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n + 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n + 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n + 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n + 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset + 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + ARM GAS /tmp/ccWQNJQt.s page 168 + + + 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) + 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2RSTR, Periphs); + 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB2 peripheral clocks in low-power mode + 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n + 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower + 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) + 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2LPENR, Periphs); + 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); + 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB2 peripheral clocks in low-power mode + 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n + 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_DisableClockLowPower\n + 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n + 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n + 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n + 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n + 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower + 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + ARM GAS /tmp/ccWQNJQt.s page 169 + + + 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) + 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2LPENR, Periphs); + 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB3 AHB3 + 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB3 peripherals clock. + 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n + 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) + 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3ENR, Periphs); + 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); + 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB3 peripheral clock is enabled or not + 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n + 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock + 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) + 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); + 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + ARM GAS /tmp/ccWQNJQt.s page 170 + + + 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB3 peripherals clock. + 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n + 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock + 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) + 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3ENR, Periphs); + 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB3 peripherals reset. + 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n + 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset + 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) + 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3RSTR, Periphs); + 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB3 peripherals reset. + 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n + 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset + 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) + 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3RSTR, Periphs); + 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB3 peripheral clocks in low-power mode + 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n + 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower + 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + ARM GAS /tmp/ccWQNJQt.s page 171 + + + 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) + 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3LPENR, Periphs); + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); + 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB3 peripheral clocks in low-power mode + 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n + 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower + 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) + 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3LPENR, Periphs); + 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1 + 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ +1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB1 peripherals clock. +1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n +1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n +1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n +1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n +1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n +1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n +1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n +1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n +1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n +1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n +1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n +1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n +1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n +1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n +1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n +1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n +1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n +1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n +1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + ARM GAS /tmp/ccWQNJQt.s page 172 + + +1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n +1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n +1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_EnableClock\n +1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n +1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n +1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n +1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n +1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n +1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n +1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n +1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_EnableClock +1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; +1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); +1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; +1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + ARM GAS /tmp/ccWQNJQt.s page 173 + + +1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not +1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n +1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n +1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n +1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n +1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n +1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n +1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n +1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n +1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n +1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n +1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n +1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n +1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n +1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n +1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n +1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n +1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n +1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n +1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n +1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n +1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n +1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_IsEnabledClock\n +1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n +1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n +1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n +1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n +1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n +1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n +1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n +1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n +1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_IsEnabledClock +1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + ARM GAS /tmp/ccWQNJQt.s page 174 + + +1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). +1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); +1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable APB1 peripherals clock. +1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n +1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n +1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n +1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n +1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n +1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n +1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n +1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n +1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n +1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n +1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n +1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n +1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n +1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n +1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n +1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n +1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n +1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n +1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n +1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n +1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n +1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_DisableClock\n +1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n +1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n +1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n +1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n +1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n +1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n +1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n +1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n +1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_DisableClock +1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + ARM GAS /tmp/ccWQNJQt.s page 175 + + +1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); +1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force APB1 peripherals reset. +1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n +1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n +1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n +1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n +1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n +1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n +1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n +1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n +1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n +1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n +1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n +1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n +1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n +1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n +1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n +1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n +1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n +1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n +1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n +1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n +1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n + ARM GAS /tmp/ccWQNJQt.s page 176 + + +1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C4RST LL_APB1_GRP1_ForceReset\n +1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n +1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n +1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n +1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n +1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n +1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n +1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n +1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset +1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); +1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release APB1 peripherals reset. +1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n +1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n +1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n +1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n +1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n +1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + ARM GAS /tmp/ccWQNJQt.s page 177 + + +1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n +1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n +1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n +1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n +1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n +1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n +1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n +1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n +1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n +1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n +1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n +1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n +1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n +1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n +1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C4RST LL_APB1_GRP1_ReleaseReset\n +1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n +1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n +1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n +1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n +1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n +1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n +1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n +1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset +1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + ARM GAS /tmp/ccWQNJQt.s page 178 + + +1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB1 peripheral clocks in low-power mode +1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n +1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n +1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n +1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n +1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n +1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n +1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n +1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n +1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n +1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n +1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n +1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n +1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n +1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C4LPEN LL_APB1_GRP1_EnableClockLowPower\n +1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n +1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n +1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n +1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n +1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n +1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n +1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR RTCLPEN LL_APB1_GRP1_EnableClockLowPower +1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + ARM GAS /tmp/ccWQNJQt.s page 179 + + +1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) +1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; +1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1LPENR, Periphs); +1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ +1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); +1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; +1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable APB1 peripheral clocks in low-power mode +1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n +1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n +1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n +1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n +1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n +1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n +1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n +1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n +1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n +1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n +1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n +1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n +1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n +1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C4LPEN LL_APB1_GRP1_DisableClockLowPower\n +1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n +1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n +1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n + ARM GAS /tmp/ccWQNJQt.s page 180 + + +1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n +1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n +1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n +1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR RTCLPEN LL_APB1_GRP1_DisableClockLowPower +1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) +1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1LPENR, Periphs); +1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} +1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB2 APB2 +1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ +1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB2 peripherals clock. +1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n +1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n + ARM GAS /tmp/ccWQNJQt.s page 181 + + +1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n +1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n +1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n +1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n +1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n +1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n +1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC2EN LL_APB2_GRP1_EnableClock\n +1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n +1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n +1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n +1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n +1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n +1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n +1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n +1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n +1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n +1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n +1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n +1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n +1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n +1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR MDIOEN LL_APB2_GRP1_EnableClock\n +1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR OTGPHYCEN LL_APB2_GRP1_EnableClock +1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 +1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 +1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 +1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 +1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 +1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 +1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 +1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 +1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) +1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 +1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 +1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG +1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 +1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 +1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 +1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 +1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) +1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 +1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 +1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) +1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) +1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) +1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) +1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) +1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) + 2153 .loc 3 1587 22 view .LVU691 + 2154 .LBB351: +1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 2155 .loc 3 1589 3 view .LVU692 + ARM GAS /tmp/ccWQNJQt.s page 182 + + +1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); + 2156 .loc 3 1590 3 view .LVU693 + 2157 001e 2A4B ldr r3, .L99 + 2158 0020 5A6C ldr r2, [r3, #68] + 2159 0022 42F40052 orr r2, r2, #8192 + 2160 0026 5A64 str r2, [r3, #68] +1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + 2161 .loc 3 1592 3 view .LVU694 + 2162 .loc 3 1592 12 is_stmt 0 view .LVU695 + 2163 0028 5A6C ldr r2, [r3, #68] + 2164 002a 02F40052 and r2, r2, #8192 + 2165 .loc 3 1592 10 view .LVU696 + 2166 002e 0192 str r2, [sp, #4] +1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2167 .loc 3 1593 3 is_stmt 1 view .LVU697 + 2168 0030 019A ldr r2, [sp, #4] + 2169 .LVL193: + 2170 .loc 3 1593 3 is_stmt 0 view .LVU698 + 2171 .LBE351: + 2172 .LBE350: +1060:Src/main.c **** /**SPI4 GPIO Configuration + 2173 .loc 1 1060 3 is_stmt 1 view .LVU699 + 2174 .LBB352: + 2175 .LBI352: + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 2176 .loc 3 309 22 view .LVU700 + 2177 .LBB353: + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); + 2178 .loc 3 311 3 view .LVU701 + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 2179 .loc 3 312 3 view .LVU702 + 2180 0032 1A6B ldr r2, [r3, #48] + 2181 0034 42F01002 orr r2, r2, #16 + 2182 0038 1A63 str r2, [r3, #48] + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2183 .loc 3 314 3 view .LVU703 + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2184 .loc 3 314 12 is_stmt 0 view .LVU704 + 2185 003a 1B6B ldr r3, [r3, #48] + 2186 003c 03F01003 and r3, r3, #16 + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2187 .loc 3 314 10 view .LVU705 + 2188 0040 0093 str r3, [sp] + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 2189 .loc 3 315 3 is_stmt 1 view .LVU706 + 2190 0042 009B ldr r3, [sp] + 2191 .LVL194: + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 2192 .loc 3 315 3 is_stmt 0 view .LVU707 + 2193 .LBE353: + 2194 .LBE352: +1065:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 2195 .loc 1 1065 3 is_stmt 1 view .LVU708 +1065:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 2196 .loc 1 1065 23 is_stmt 0 view .LVU709 + 2197 0044 4FF48053 mov r3, #4096 + ARM GAS /tmp/ccWQNJQt.s page 183 + + + 2198 0048 0293 str r3, [sp, #8] +1066:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 2199 .loc 1 1066 3 is_stmt 1 view .LVU710 +1066:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 2200 .loc 1 1066 24 is_stmt 0 view .LVU711 + 2201 004a 0225 movs r5, #2 + 2202 004c 0395 str r5, [sp, #12] +1067:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 2203 .loc 1 1067 3 is_stmt 1 view .LVU712 +1067:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 2204 .loc 1 1067 25 is_stmt 0 view .LVU713 + 2205 004e 4FF00308 mov r8, #3 + 2206 0052 CDF81080 str r8, [sp, #16] +1068:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 2207 .loc 1 1068 3 is_stmt 1 view .LVU714 +1069:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; + 2208 .loc 1 1069 3 view .LVU715 +1070:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 2209 .loc 1 1070 3 view .LVU716 +1070:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 2210 .loc 1 1070 29 is_stmt 0 view .LVU717 + 2211 0056 0527 movs r7, #5 + 2212 0058 0797 str r7, [sp, #28] +1071:Src/main.c **** + 2213 .loc 1 1071 3 is_stmt 1 view .LVU718 + 2214 005a 1C4E ldr r6, .L99+4 + 2215 005c 02A9 add r1, sp, #8 + 2216 005e 3046 mov r0, r6 + 2217 0060 FFF7FEFF bl LL_GPIO_Init + 2218 .LVL195: +1073:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 2219 .loc 1 1073 3 view .LVU719 +1073:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 2220 .loc 1 1073 23 is_stmt 0 view .LVU720 + 2221 0064 4FF40053 mov r3, #8192 + 2222 0068 0293 str r3, [sp, #8] +1074:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 2223 .loc 1 1074 3 is_stmt 1 view .LVU721 +1074:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 2224 .loc 1 1074 24 is_stmt 0 view .LVU722 + 2225 006a 0395 str r5, [sp, #12] +1075:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 2226 .loc 1 1075 3 is_stmt 1 view .LVU723 +1075:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 2227 .loc 1 1075 25 is_stmt 0 view .LVU724 + 2228 006c CDF81080 str r8, [sp, #16] +1076:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 2229 .loc 1 1076 3 is_stmt 1 view .LVU725 +1076:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 2230 .loc 1 1076 30 is_stmt 0 view .LVU726 + 2231 0070 0594 str r4, [sp, #20] +1077:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; + 2232 .loc 1 1077 3 is_stmt 1 view .LVU727 +1077:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; + 2233 .loc 1 1077 24 is_stmt 0 view .LVU728 + 2234 0072 0694 str r4, [sp, #24] +1078:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); + ARM GAS /tmp/ccWQNJQt.s page 184 + + + 2235 .loc 1 1078 3 is_stmt 1 view .LVU729 +1078:Src/main.c **** LL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 2236 .loc 1 1078 29 is_stmt 0 view .LVU730 + 2237 0074 0797 str r7, [sp, #28] +1079:Src/main.c **** + 2238 .loc 1 1079 3 is_stmt 1 view .LVU731 + 2239 0076 02A9 add r1, sp, #8 + 2240 0078 3046 mov r0, r6 + 2241 007a FFF7FEFF bl LL_GPIO_Init + 2242 .LVL196: +1085:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; + 2243 .loc 1 1085 3 view .LVU732 +1085:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; + 2244 .loc 1 1085 36 is_stmt 0 view .LVU733 + 2245 007e 4FF48063 mov r3, #1024 + 2246 0082 0893 str r3, [sp, #32] +1086:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; + 2247 .loc 1 1086 3 is_stmt 1 view .LVU734 +1086:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; + 2248 .loc 1 1086 23 is_stmt 0 view .LVU735 + 2249 0084 4FF48273 mov r3, #260 + 2250 0088 0993 str r3, [sp, #36] +1087:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; + 2251 .loc 1 1087 3 is_stmt 1 view .LVU736 +1087:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; + 2252 .loc 1 1087 28 is_stmt 0 view .LVU737 + 2253 008a 4FF47063 mov r3, #3840 + 2254 008e 0A93 str r3, [sp, #40] +1088:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; + 2255 .loc 1 1088 3 is_stmt 1 view .LVU738 +1088:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; + 2256 .loc 1 1088 32 is_stmt 0 view .LVU739 + 2257 0090 0B95 str r5, [sp, #44] +1089:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; + 2258 .loc 1 1089 3 is_stmt 1 view .LVU740 +1089:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; + 2259 .loc 1 1089 29 is_stmt 0 view .LVU741 + 2260 0092 0C94 str r4, [sp, #48] +1090:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; + 2261 .loc 1 1090 3 is_stmt 1 view .LVU742 +1090:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; + 2262 .loc 1 1090 22 is_stmt 0 view .LVU743 + 2263 0094 4FF40073 mov r3, #512 + 2264 0098 0D93 str r3, [sp, #52] +1091:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; + 2265 .loc 1 1091 3 is_stmt 1 view .LVU744 +1091:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; + 2266 .loc 1 1091 27 is_stmt 0 view .LVU745 + 2267 009a 1823 movs r3, #24 + 2268 009c 0E93 str r3, [sp, #56] +1092:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; + 2269 .loc 1 1092 3 is_stmt 1 view .LVU746 +1092:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; + 2270 .loc 1 1092 27 is_stmt 0 view .LVU747 + 2271 009e 0F94 str r4, [sp, #60] +1093:Src/main.c **** SPI_InitStruct.CRCPoly = 7; + 2272 .loc 1 1093 3 is_stmt 1 view .LVU748 + ARM GAS /tmp/ccWQNJQt.s page 185 + + +1093:Src/main.c **** SPI_InitStruct.CRCPoly = 7; + 2273 .loc 1 1093 33 is_stmt 0 view .LVU749 + 2274 00a0 1094 str r4, [sp, #64] +1094:Src/main.c **** LL_SPI_Init(SPI4, &SPI_InitStruct); + 2275 .loc 1 1094 3 is_stmt 1 view .LVU750 +1094:Src/main.c **** LL_SPI_Init(SPI4, &SPI_InitStruct); + 2276 .loc 1 1094 26 is_stmt 0 view .LVU751 + 2277 00a2 0723 movs r3, #7 + 2278 00a4 1193 str r3, [sp, #68] +1095:Src/main.c **** LL_SPI_SetStandard(SPI4, LL_SPI_PROTOCOL_MOTOROLA); + 2279 .loc 1 1095 3 is_stmt 1 view .LVU752 + 2280 00a6 0A4C ldr r4, .L99+8 + 2281 00a8 08A9 add r1, sp, #32 + 2282 00aa 2046 mov r0, r4 + 2283 00ac FFF7FEFF bl LL_SPI_Init + 2284 .LVL197: +1096:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI4); + 2285 .loc 1 1096 3 view .LVU753 + 2286 .LBB354: + 2287 .LBI354: + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 2288 .loc 4 426 22 view .LVU754 + 2289 .LBB355: + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 2290 .loc 4 428 3 view .LVU755 + 2291 00b0 6368 ldr r3, [r4, #4] + 2292 00b2 23F01003 bic r3, r3, #16 + 2293 00b6 6360 str r3, [r4, #4] + 2294 .LVL198: + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 2295 .loc 4 428 3 is_stmt 0 view .LVU756 + 2296 .LBE355: + 2297 .LBE354: +1097:Src/main.c **** /* USER CODE BEGIN SPI4_Init 2 */ + 2298 .loc 1 1097 3 is_stmt 1 view .LVU757 + 2299 .LBB356: + 2300 .LBI356: + 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 2301 .loc 4 874 22 view .LVU758 + 2302 .LBB357: + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 2303 .loc 4 876 3 view .LVU759 + 2304 00b8 6368 ldr r3, [r4, #4] + 2305 00ba 23F00803 bic r3, r3, #8 + 2306 00be 6360 str r3, [r4, #4] + 2307 .LVL199: + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 2308 .loc 4 876 3 is_stmt 0 view .LVU760 + 2309 .LBE357: + 2310 .LBE356: +1102:Src/main.c **** + 2311 .loc 1 1102 1 view .LVU761 + 2312 00c0 12B0 add sp, sp, #72 + 2313 .LCFI17: + 2314 .cfi_def_cfa_offset 24 + 2315 @ sp needed + 2316 00c2 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + ARM GAS /tmp/ccWQNJQt.s page 186 + + + 2317 .L100: + 2318 00c6 00BF .align 2 + 2319 .L99: + 2320 00c8 00380240 .word 1073887232 + 2321 00cc 00100240 .word 1073876992 + 2322 00d0 00340140 .word 1073820672 + 2323 .cfi_endproc + 2324 .LFE1192: + 2326 .section .text.MX_SPI2_Init,"ax",%progbits + 2327 .align 1 + 2328 .syntax unified + 2329 .thumb + 2330 .thumb_func + 2332 MX_SPI2_Init: + 2333 .LFB1191: + 984:Src/main.c **** + 2334 .loc 1 984 1 is_stmt 1 view -0 + 2335 .cfi_startproc + 2336 @ args = 0, pretend = 0, frame = 72 + 2337 @ frame_needed = 0, uses_anonymous_args = 0 + 2338 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 2339 .LCFI18: + 2340 .cfi_def_cfa_offset 24 + 2341 .cfi_offset 4, -24 + 2342 .cfi_offset 5, -20 + 2343 .cfi_offset 6, -16 + 2344 .cfi_offset 7, -12 + 2345 .cfi_offset 8, -8 + 2346 .cfi_offset 14, -4 + 2347 0004 92B0 sub sp, sp, #72 + 2348 .LCFI19: + 2349 .cfi_def_cfa_offset 96 + 990:Src/main.c **** + 2350 .loc 1 990 3 view .LVU763 + 990:Src/main.c **** + 2351 .loc 1 990 22 is_stmt 0 view .LVU764 + 2352 0006 2822 movs r2, #40 + 2353 0008 0021 movs r1, #0 + 2354 000a 08A8 add r0, sp, #32 + 2355 000c FFF7FEFF bl memset + 2356 .LVL200: + 992:Src/main.c **** + 2357 .loc 1 992 3 is_stmt 1 view .LVU765 + 992:Src/main.c **** + 2358 .loc 1 992 23 is_stmt 0 view .LVU766 + 2359 0010 0024 movs r4, #0 + 2360 0012 0294 str r4, [sp, #8] + 2361 0014 0394 str r4, [sp, #12] + 2362 0016 0494 str r4, [sp, #16] + 2363 0018 0594 str r4, [sp, #20] + 2364 001a 0694 str r4, [sp, #24] + 2365 001c 0794 str r4, [sp, #28] + 995:Src/main.c **** + 2366 .loc 1 995 3 is_stmt 1 view .LVU767 + 2367 .LVL201: + 2368 .LBB358: + 2369 .LBI358: + ARM GAS /tmp/ccWQNJQt.s page 187 + + +1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 2370 .loc 3 1071 22 view .LVU768 + 2371 .LBB359: +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); + 2372 .loc 3 1073 3 view .LVU769 +1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 2373 .loc 3 1074 3 view .LVU770 + 2374 001e 294B ldr r3, .L103 + 2375 0020 1A6C ldr r2, [r3, #64] + 2376 0022 42F48042 orr r2, r2, #16384 + 2377 0026 1A64 str r2, [r3, #64] +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2378 .loc 3 1076 3 view .LVU771 +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2379 .loc 3 1076 12 is_stmt 0 view .LVU772 + 2380 0028 1A6C ldr r2, [r3, #64] + 2381 002a 02F48042 and r2, r2, #16384 +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2382 .loc 3 1076 10 view .LVU773 + 2383 002e 0192 str r2, [sp, #4] +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 2384 .loc 3 1077 3 is_stmt 1 view .LVU774 + 2385 0030 019A ldr r2, [sp, #4] + 2386 .LVL202: +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 2387 .loc 3 1077 3 is_stmt 0 view .LVU775 + 2388 .LBE359: + 2389 .LBE358: + 997:Src/main.c **** /**SPI2 GPIO Configuration + 2390 .loc 1 997 3 is_stmt 1 view .LVU776 + 2391 .LBB360: + 2392 .LBI360: + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 2393 .loc 3 309 22 view .LVU777 + 2394 .LBB361: + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); + 2395 .loc 3 311 3 view .LVU778 + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 2396 .loc 3 312 3 view .LVU779 + 2397 0032 1A6B ldr r2, [r3, #48] + 2398 0034 42F00202 orr r2, r2, #2 + 2399 0038 1A63 str r2, [r3, #48] + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2400 .loc 3 314 3 view .LVU780 + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2401 .loc 3 314 12 is_stmt 0 view .LVU781 + 2402 003a 1B6B ldr r3, [r3, #48] + 2403 003c 03F00203 and r3, r3, #2 + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2404 .loc 3 314 10 view .LVU782 + 2405 0040 0093 str r3, [sp] + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 2406 .loc 3 315 3 is_stmt 1 view .LVU783 + 2407 0042 009B ldr r3, [sp] + 2408 .LVL203: + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 2409 .loc 3 315 3 is_stmt 0 view .LVU784 + ARM GAS /tmp/ccWQNJQt.s page 188 + + + 2410 .LBE361: + 2411 .LBE360: +1002:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 2412 .loc 1 1002 3 is_stmt 1 view .LVU785 +1002:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 2413 .loc 1 1002 23 is_stmt 0 view .LVU786 + 2414 0044 4FF40053 mov r3, #8192 + 2415 0048 0293 str r3, [sp, #8] +1003:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 2416 .loc 1 1003 3 is_stmt 1 view .LVU787 +1003:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 2417 .loc 1 1003 24 is_stmt 0 view .LVU788 + 2418 004a 0225 movs r5, #2 + 2419 004c 0395 str r5, [sp, #12] +1004:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 2420 .loc 1 1004 3 is_stmt 1 view .LVU789 +1004:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 2421 .loc 1 1004 25 is_stmt 0 view .LVU790 + 2422 004e 4FF00308 mov r8, #3 + 2423 0052 CDF81080 str r8, [sp, #16] +1005:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 2424 .loc 1 1005 3 is_stmt 1 view .LVU791 +1006:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; + 2425 .loc 1 1006 3 view .LVU792 +1007:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 2426 .loc 1 1007 3 view .LVU793 +1007:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 2427 .loc 1 1007 29 is_stmt 0 view .LVU794 + 2428 0056 0527 movs r7, #5 + 2429 0058 0797 str r7, [sp, #28] +1008:Src/main.c **** + 2430 .loc 1 1008 3 is_stmt 1 view .LVU795 + 2431 005a 1B4E ldr r6, .L103+4 + 2432 005c 02A9 add r1, sp, #8 + 2433 005e 3046 mov r0, r6 + 2434 0060 FFF7FEFF bl LL_GPIO_Init + 2435 .LVL204: +1010:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 2436 .loc 1 1010 3 view .LVU796 +1010:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 2437 .loc 1 1010 23 is_stmt 0 view .LVU797 + 2438 0064 4FF40043 mov r3, #32768 + 2439 0068 0293 str r3, [sp, #8] +1011:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 2440 .loc 1 1011 3 is_stmt 1 view .LVU798 +1011:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 2441 .loc 1 1011 24 is_stmt 0 view .LVU799 + 2442 006a 0395 str r5, [sp, #12] +1012:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 2443 .loc 1 1012 3 is_stmt 1 view .LVU800 +1012:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 2444 .loc 1 1012 25 is_stmt 0 view .LVU801 + 2445 006c CDF81080 str r8, [sp, #16] +1013:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 2446 .loc 1 1013 3 is_stmt 1 view .LVU802 +1013:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 2447 .loc 1 1013 30 is_stmt 0 view .LVU803 + ARM GAS /tmp/ccWQNJQt.s page 189 + + + 2448 0070 0594 str r4, [sp, #20] +1014:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; + 2449 .loc 1 1014 3 is_stmt 1 view .LVU804 +1014:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; + 2450 .loc 1 1014 24 is_stmt 0 view .LVU805 + 2451 0072 0694 str r4, [sp, #24] +1015:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 2452 .loc 1 1015 3 is_stmt 1 view .LVU806 +1015:Src/main.c **** LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 2453 .loc 1 1015 29 is_stmt 0 view .LVU807 + 2454 0074 0797 str r7, [sp, #28] +1016:Src/main.c **** + 2455 .loc 1 1016 3 is_stmt 1 view .LVU808 + 2456 0076 02A9 add r1, sp, #8 + 2457 0078 3046 mov r0, r6 + 2458 007a FFF7FEFF bl LL_GPIO_Init + 2459 .LVL205: +1022:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; + 2460 .loc 1 1022 3 view .LVU809 +1022:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; + 2461 .loc 1 1022 36 is_stmt 0 view .LVU810 + 2462 007e 0894 str r4, [sp, #32] +1023:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; + 2463 .loc 1 1023 3 is_stmt 1 view .LVU811 +1023:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; + 2464 .loc 1 1023 23 is_stmt 0 view .LVU812 + 2465 0080 4FF48273 mov r3, #260 + 2466 0084 0993 str r3, [sp, #36] +1024:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; + 2467 .loc 1 1024 3 is_stmt 1 view .LVU813 +1024:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; + 2468 .loc 1 1024 28 is_stmt 0 view .LVU814 + 2469 0086 4FF47063 mov r3, #3840 + 2470 008a 0A93 str r3, [sp, #40] +1025:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; + 2471 .loc 1 1025 3 is_stmt 1 view .LVU815 +1025:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; + 2472 .loc 1 1025 32 is_stmt 0 view .LVU816 + 2473 008c 0B95 str r5, [sp, #44] +1026:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; + 2474 .loc 1 1026 3 is_stmt 1 view .LVU817 +1026:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; + 2475 .loc 1 1026 29 is_stmt 0 view .LVU818 + 2476 008e 0123 movs r3, #1 + 2477 0090 0C93 str r3, [sp, #48] +1027:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8; + 2478 .loc 1 1027 3 is_stmt 1 view .LVU819 +1027:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV8; + 2479 .loc 1 1027 22 is_stmt 0 view .LVU820 + 2480 0092 4FF40073 mov r3, #512 + 2481 0096 0D93 str r3, [sp, #52] +1028:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; + 2482 .loc 1 1028 3 is_stmt 1 view .LVU821 +1028:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; + 2483 .loc 1 1028 27 is_stmt 0 view .LVU822 + 2484 0098 1023 movs r3, #16 + 2485 009a 0E93 str r3, [sp, #56] + ARM GAS /tmp/ccWQNJQt.s page 190 + + +1029:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; + 2486 .loc 1 1029 3 is_stmt 1 view .LVU823 +1029:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; + 2487 .loc 1 1029 27 is_stmt 0 view .LVU824 + 2488 009c 0F94 str r4, [sp, #60] +1030:Src/main.c **** SPI_InitStruct.CRCPoly = 7; + 2489 .loc 1 1030 3 is_stmt 1 view .LVU825 +1030:Src/main.c **** SPI_InitStruct.CRCPoly = 7; + 2490 .loc 1 1030 33 is_stmt 0 view .LVU826 + 2491 009e 1094 str r4, [sp, #64] +1031:Src/main.c **** LL_SPI_Init(SPI2, &SPI_InitStruct); + 2492 .loc 1 1031 3 is_stmt 1 view .LVU827 +1031:Src/main.c **** LL_SPI_Init(SPI2, &SPI_InitStruct); + 2493 .loc 1 1031 26 is_stmt 0 view .LVU828 + 2494 00a0 0723 movs r3, #7 + 2495 00a2 1193 str r3, [sp, #68] +1032:Src/main.c **** LL_SPI_SetStandard(SPI2, LL_SPI_PROTOCOL_MOTOROLA); + 2496 .loc 1 1032 3 is_stmt 1 view .LVU829 + 2497 00a4 094C ldr r4, .L103+8 + 2498 00a6 08A9 add r1, sp, #32 + 2499 00a8 2046 mov r0, r4 + 2500 00aa FFF7FEFF bl LL_SPI_Init + 2501 .LVL206: +1033:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI2); + 2502 .loc 1 1033 3 view .LVU830 + 2503 .LBB362: + 2504 .LBI362: + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 2505 .loc 4 426 22 view .LVU831 + 2506 .LBB363: + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 2507 .loc 4 428 3 view .LVU832 + 2508 00ae 6368 ldr r3, [r4, #4] + 2509 00b0 23F01003 bic r3, r3, #16 + 2510 00b4 6360 str r3, [r4, #4] + 2511 .LVL207: + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 2512 .loc 4 428 3 is_stmt 0 view .LVU833 + 2513 .LBE363: + 2514 .LBE362: +1034:Src/main.c **** /* USER CODE BEGIN SPI2_Init 2 */ + 2515 .loc 1 1034 3 is_stmt 1 view .LVU834 + 2516 .LBB364: + 2517 .LBI364: + 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 2518 .loc 4 874 22 view .LVU835 + 2519 .LBB365: + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 2520 .loc 4 876 3 view .LVU836 + 2521 00b6 6368 ldr r3, [r4, #4] + 2522 00b8 23F00803 bic r3, r3, #8 + 2523 00bc 6360 str r3, [r4, #4] + 2524 .LVL208: + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 2525 .loc 4 876 3 is_stmt 0 view .LVU837 + 2526 .LBE365: + 2527 .LBE364: + ARM GAS /tmp/ccWQNJQt.s page 191 + + +1039:Src/main.c **** + 2528 .loc 1 1039 1 view .LVU838 + 2529 00be 12B0 add sp, sp, #72 + 2530 .LCFI20: + 2531 .cfi_def_cfa_offset 24 + 2532 @ sp needed + 2533 00c0 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 2534 .L104: + 2535 .align 2 + 2536 .L103: + 2537 00c4 00380240 .word 1073887232 + 2538 00c8 00040240 .word 1073873920 + 2539 00cc 00380040 .word 1073756160 + 2540 .cfi_endproc + 2541 .LFE1191: + 2543 .section .text.MX_SPI5_Init,"ax",%progbits + 2544 .align 1 + 2545 .syntax unified + 2546 .thumb + 2547 .thumb_func + 2549 MX_SPI5_Init: + 2550 .LFB1193: +1110:Src/main.c **** + 2551 .loc 1 1110 1 is_stmt 1 view -0 + 2552 .cfi_startproc + 2553 @ args = 0, pretend = 0, frame = 72 + 2554 @ frame_needed = 0, uses_anonymous_args = 0 + 2555 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 2556 .LCFI21: + 2557 .cfi_def_cfa_offset 24 + 2558 .cfi_offset 4, -24 + 2559 .cfi_offset 5, -20 + 2560 .cfi_offset 6, -16 + 2561 .cfi_offset 7, -12 + 2562 .cfi_offset 8, -8 + 2563 .cfi_offset 14, -4 + 2564 0004 92B0 sub sp, sp, #72 + 2565 .LCFI22: + 2566 .cfi_def_cfa_offset 96 +1116:Src/main.c **** + 2567 .loc 1 1116 3 view .LVU840 +1116:Src/main.c **** + 2568 .loc 1 1116 22 is_stmt 0 view .LVU841 + 2569 0006 2822 movs r2, #40 + 2570 0008 0021 movs r1, #0 + 2571 000a 08A8 add r0, sp, #32 + 2572 000c FFF7FEFF bl memset + 2573 .LVL209: +1118:Src/main.c **** + 2574 .loc 1 1118 3 is_stmt 1 view .LVU842 +1118:Src/main.c **** + 2575 .loc 1 1118 23 is_stmt 0 view .LVU843 + 2576 0010 0024 movs r4, #0 + 2577 0012 0294 str r4, [sp, #8] + 2578 0014 0394 str r4, [sp, #12] + 2579 0016 0494 str r4, [sp, #16] + 2580 0018 0594 str r4, [sp, #20] + ARM GAS /tmp/ccWQNJQt.s page 192 + + + 2581 001a 0694 str r4, [sp, #24] + 2582 001c 0794 str r4, [sp, #28] +1121:Src/main.c **** + 2583 .loc 1 1121 3 is_stmt 1 view .LVU844 + 2584 .LVL210: + 2585 .LBB366: + 2586 .LBI366: +1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 2587 .loc 3 1587 22 view .LVU845 + 2588 .LBB367: +1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); + 2589 .loc 3 1589 3 view .LVU846 +1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 2590 .loc 3 1590 3 view .LVU847 + 2591 001e 294B ldr r3, .L107 + 2592 0020 5A6C ldr r2, [r3, #68] + 2593 0022 42F48012 orr r2, r2, #1048576 + 2594 0026 5A64 str r2, [r3, #68] +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2595 .loc 3 1592 3 view .LVU848 +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2596 .loc 3 1592 12 is_stmt 0 view .LVU849 + 2597 0028 5A6C ldr r2, [r3, #68] + 2598 002a 02F48012 and r2, r2, #1048576 +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2599 .loc 3 1592 10 view .LVU850 + 2600 002e 0192 str r2, [sp, #4] + 2601 .loc 3 1593 3 is_stmt 1 view .LVU851 + 2602 0030 019A ldr r2, [sp, #4] + 2603 .LVL211: + 2604 .loc 3 1593 3 is_stmt 0 view .LVU852 + 2605 .LBE367: + 2606 .LBE366: +1123:Src/main.c **** /**SPI5 GPIO Configuration + 2607 .loc 1 1123 3 is_stmt 1 view .LVU853 + 2608 .LBB368: + 2609 .LBI368: + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 2610 .loc 3 309 22 view .LVU854 + 2611 .LBB369: + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); + 2612 .loc 3 311 3 view .LVU855 + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 2613 .loc 3 312 3 view .LVU856 + 2614 0032 1A6B ldr r2, [r3, #48] + 2615 0034 42F02002 orr r2, r2, #32 + 2616 0038 1A63 str r2, [r3, #48] + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2617 .loc 3 314 3 view .LVU857 + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2618 .loc 3 314 12 is_stmt 0 view .LVU858 + 2619 003a 1B6B ldr r3, [r3, #48] + 2620 003c 03F02003 and r3, r3, #32 + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2621 .loc 3 314 10 view .LVU859 + 2622 0040 0093 str r3, [sp] + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + ARM GAS /tmp/ccWQNJQt.s page 193 + + + 2623 .loc 3 315 3 is_stmt 1 view .LVU860 + 2624 0042 009B ldr r3, [sp] + 2625 .LVL212: + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 2626 .loc 3 315 3 is_stmt 0 view .LVU861 + 2627 .LBE369: + 2628 .LBE368: +1128:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 2629 .loc 1 1128 3 is_stmt 1 view .LVU862 +1128:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 2630 .loc 1 1128 23 is_stmt 0 view .LVU863 + 2631 0044 8023 movs r3, #128 + 2632 0046 0293 str r3, [sp, #8] +1129:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 2633 .loc 1 1129 3 is_stmt 1 view .LVU864 +1129:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 2634 .loc 1 1129 24 is_stmt 0 view .LVU865 + 2635 0048 0225 movs r5, #2 + 2636 004a 0395 str r5, [sp, #12] +1130:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 2637 .loc 1 1130 3 is_stmt 1 view .LVU866 +1130:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 2638 .loc 1 1130 25 is_stmt 0 view .LVU867 + 2639 004c 4FF00308 mov r8, #3 + 2640 0050 CDF81080 str r8, [sp, #16] +1131:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 2641 .loc 1 1131 3 is_stmt 1 view .LVU868 +1132:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; + 2642 .loc 1 1132 3 view .LVU869 +1133:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); + 2643 .loc 1 1133 3 view .LVU870 +1133:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); + 2644 .loc 1 1133 29 is_stmt 0 view .LVU871 + 2645 0054 0527 movs r7, #5 + 2646 0056 0797 str r7, [sp, #28] +1134:Src/main.c **** + 2647 .loc 1 1134 3 is_stmt 1 view .LVU872 + 2648 0058 1B4E ldr r6, .L107+4 + 2649 005a 02A9 add r1, sp, #8 + 2650 005c 3046 mov r0, r6 + 2651 005e FFF7FEFF bl LL_GPIO_Init + 2652 .LVL213: +1136:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 2653 .loc 1 1136 3 view .LVU873 +1136:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 2654 .loc 1 1136 23 is_stmt 0 view .LVU874 + 2655 0062 4FF48073 mov r3, #256 + 2656 0066 0293 str r3, [sp, #8] +1137:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 2657 .loc 1 1137 3 is_stmt 1 view .LVU875 +1137:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 2658 .loc 1 1137 24 is_stmt 0 view .LVU876 + 2659 0068 0395 str r5, [sp, #12] +1138:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 2660 .loc 1 1138 3 is_stmt 1 view .LVU877 +1138:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 2661 .loc 1 1138 25 is_stmt 0 view .LVU878 + ARM GAS /tmp/ccWQNJQt.s page 194 + + + 2662 006a CDF81080 str r8, [sp, #16] +1139:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 2663 .loc 1 1139 3 is_stmt 1 view .LVU879 +1139:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 2664 .loc 1 1139 30 is_stmt 0 view .LVU880 + 2665 006e 0594 str r4, [sp, #20] +1140:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; + 2666 .loc 1 1140 3 is_stmt 1 view .LVU881 +1140:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_5; + 2667 .loc 1 1140 24 is_stmt 0 view .LVU882 + 2668 0070 0694 str r4, [sp, #24] +1141:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); + 2669 .loc 1 1141 3 is_stmt 1 view .LVU883 +1141:Src/main.c **** LL_GPIO_Init(GPIOF, &GPIO_InitStruct); + 2670 .loc 1 1141 29 is_stmt 0 view .LVU884 + 2671 0072 0797 str r7, [sp, #28] +1142:Src/main.c **** + 2672 .loc 1 1142 3 is_stmt 1 view .LVU885 + 2673 0074 02A9 add r1, sp, #8 + 2674 0076 3046 mov r0, r6 + 2675 0078 FFF7FEFF bl LL_GPIO_Init + 2676 .LVL214: +1148:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; + 2677 .loc 1 1148 3 view .LVU886 +1148:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; + 2678 .loc 1 1148 36 is_stmt 0 view .LVU887 + 2679 007c 4FF48063 mov r3, #1024 + 2680 0080 0893 str r3, [sp, #32] +1149:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; + 2681 .loc 1 1149 3 is_stmt 1 view .LVU888 +1149:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; + 2682 .loc 1 1149 23 is_stmt 0 view .LVU889 + 2683 0082 4FF48273 mov r3, #260 + 2684 0086 0993 str r3, [sp, #36] +1150:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; + 2685 .loc 1 1150 3 is_stmt 1 view .LVU890 +1150:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; + 2686 .loc 1 1150 28 is_stmt 0 view .LVU891 + 2687 0088 4FF47063 mov r3, #3840 + 2688 008c 0A93 str r3, [sp, #40] +1151:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; + 2689 .loc 1 1151 3 is_stmt 1 view .LVU892 +1151:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; + 2690 .loc 1 1151 32 is_stmt 0 view .LVU893 + 2691 008e 0B95 str r5, [sp, #44] +1152:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; + 2692 .loc 1 1152 3 is_stmt 1 view .LVU894 +1152:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; + 2693 .loc 1 1152 29 is_stmt 0 view .LVU895 + 2694 0090 0C94 str r4, [sp, #48] +1153:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; + 2695 .loc 1 1153 3 is_stmt 1 view .LVU896 +1153:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; + 2696 .loc 1 1153 22 is_stmt 0 view .LVU897 + 2697 0092 4FF40073 mov r3, #512 + 2698 0096 0D93 str r3, [sp, #52] +1154:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; + ARM GAS /tmp/ccWQNJQt.s page 195 + + + 2699 .loc 1 1154 3 is_stmt 1 view .LVU898 +1154:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; + 2700 .loc 1 1154 27 is_stmt 0 view .LVU899 + 2701 0098 1823 movs r3, #24 + 2702 009a 0E93 str r3, [sp, #56] +1155:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; + 2703 .loc 1 1155 3 is_stmt 1 view .LVU900 +1155:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; + 2704 .loc 1 1155 27 is_stmt 0 view .LVU901 + 2705 009c 0F94 str r4, [sp, #60] +1156:Src/main.c **** SPI_InitStruct.CRCPoly = 7; + 2706 .loc 1 1156 3 is_stmt 1 view .LVU902 +1156:Src/main.c **** SPI_InitStruct.CRCPoly = 7; + 2707 .loc 1 1156 33 is_stmt 0 view .LVU903 + 2708 009e 1094 str r4, [sp, #64] +1157:Src/main.c **** LL_SPI_Init(SPI5, &SPI_InitStruct); + 2709 .loc 1 1157 3 is_stmt 1 view .LVU904 +1157:Src/main.c **** LL_SPI_Init(SPI5, &SPI_InitStruct); + 2710 .loc 1 1157 26 is_stmt 0 view .LVU905 + 2711 00a0 0723 movs r3, #7 + 2712 00a2 1193 str r3, [sp, #68] +1158:Src/main.c **** LL_SPI_SetStandard(SPI5, LL_SPI_PROTOCOL_MOTOROLA); + 2713 .loc 1 1158 3 is_stmt 1 view .LVU906 + 2714 00a4 094C ldr r4, .L107+8 + 2715 00a6 08A9 add r1, sp, #32 + 2716 00a8 2046 mov r0, r4 + 2717 00aa FFF7FEFF bl LL_SPI_Init + 2718 .LVL215: +1159:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI5); + 2719 .loc 1 1159 3 view .LVU907 + 2720 .LBB370: + 2721 .LBI370: + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 2722 .loc 4 426 22 view .LVU908 + 2723 .LBB371: + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 2724 .loc 4 428 3 view .LVU909 + 2725 00ae 6368 ldr r3, [r4, #4] + 2726 00b0 23F01003 bic r3, r3, #16 + 2727 00b4 6360 str r3, [r4, #4] + 2728 .LVL216: + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 2729 .loc 4 428 3 is_stmt 0 view .LVU910 + 2730 .LBE371: + 2731 .LBE370: +1160:Src/main.c **** /* USER CODE BEGIN SPI5_Init 2 */ + 2732 .loc 1 1160 3 is_stmt 1 view .LVU911 + 2733 .LBB372: + 2734 .LBI372: + 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 2735 .loc 4 874 22 view .LVU912 + 2736 .LBB373: + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 2737 .loc 4 876 3 view .LVU913 + 2738 00b6 6368 ldr r3, [r4, #4] + 2739 00b8 23F00803 bic r3, r3, #8 + 2740 00bc 6360 str r3, [r4, #4] + ARM GAS /tmp/ccWQNJQt.s page 196 + + + 2741 .LVL217: + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 2742 .loc 4 876 3 is_stmt 0 view .LVU914 + 2743 .LBE373: + 2744 .LBE372: +1165:Src/main.c **** + 2745 .loc 1 1165 1 view .LVU915 + 2746 00be 12B0 add sp, sp, #72 + 2747 .LCFI23: + 2748 .cfi_def_cfa_offset 24 + 2749 @ sp needed + 2750 00c0 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 2751 .L108: + 2752 .align 2 + 2753 .L107: + 2754 00c4 00380240 .word 1073887232 + 2755 00c8 00140240 .word 1073878016 + 2756 00cc 00500140 .word 1073827840 + 2757 .cfi_endproc + 2758 .LFE1193: + 2760 .section .text.MX_SPI6_Init,"ax",%progbits + 2761 .align 1 + 2762 .syntax unified + 2763 .thumb + 2764 .thumb_func + 2766 MX_SPI6_Init: + 2767 .LFB1194: +1173:Src/main.c **** + 2768 .loc 1 1173 1 is_stmt 1 view -0 + 2769 .cfi_startproc + 2770 @ args = 0, pretend = 0, frame = 72 + 2771 @ frame_needed = 0, uses_anonymous_args = 0 + 2772 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 2773 .LCFI24: + 2774 .cfi_def_cfa_offset 24 + 2775 .cfi_offset 4, -24 + 2776 .cfi_offset 5, -20 + 2777 .cfi_offset 6, -16 + 2778 .cfi_offset 7, -12 + 2779 .cfi_offset 8, -8 + 2780 .cfi_offset 14, -4 + 2781 0004 92B0 sub sp, sp, #72 + 2782 .LCFI25: + 2783 .cfi_def_cfa_offset 96 +1179:Src/main.c **** + 2784 .loc 1 1179 3 view .LVU917 +1179:Src/main.c **** + 2785 .loc 1 1179 22 is_stmt 0 view .LVU918 + 2786 0006 2822 movs r2, #40 + 2787 0008 0021 movs r1, #0 + 2788 000a 08A8 add r0, sp, #32 + 2789 000c FFF7FEFF bl memset + 2790 .LVL218: +1181:Src/main.c **** + 2791 .loc 1 1181 3 is_stmt 1 view .LVU919 +1181:Src/main.c **** + 2792 .loc 1 1181 23 is_stmt 0 view .LVU920 + ARM GAS /tmp/ccWQNJQt.s page 197 + + + 2793 0010 0024 movs r4, #0 + 2794 0012 0294 str r4, [sp, #8] + 2795 0014 0394 str r4, [sp, #12] + 2796 0016 0494 str r4, [sp, #16] + 2797 0018 0594 str r4, [sp, #20] + 2798 001a 0694 str r4, [sp, #24] + 2799 001c 0794 str r4, [sp, #28] +1184:Src/main.c **** + 2800 .loc 1 1184 3 is_stmt 1 view .LVU921 + 2801 .LVL219: + 2802 .LBB374: + 2803 .LBI374: +1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 2804 .loc 3 1587 22 view .LVU922 + 2805 .LBB375: +1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); + 2806 .loc 3 1589 3 view .LVU923 +1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 2807 .loc 3 1590 3 view .LVU924 + 2808 001e 294B ldr r3, .L111 + 2809 0020 5A6C ldr r2, [r3, #68] + 2810 0022 42F40012 orr r2, r2, #2097152 + 2811 0026 5A64 str r2, [r3, #68] +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2812 .loc 3 1592 3 view .LVU925 +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2813 .loc 3 1592 12 is_stmt 0 view .LVU926 + 2814 0028 5A6C ldr r2, [r3, #68] + 2815 002a 02F40012 and r2, r2, #2097152 +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2816 .loc 3 1592 10 view .LVU927 + 2817 002e 0192 str r2, [sp, #4] + 2818 .loc 3 1593 3 is_stmt 1 view .LVU928 + 2819 0030 019A ldr r2, [sp, #4] + 2820 .LVL220: + 2821 .loc 3 1593 3 is_stmt 0 view .LVU929 + 2822 .LBE375: + 2823 .LBE374: +1186:Src/main.c **** /**SPI6 GPIO Configuration + 2824 .loc 1 1186 3 is_stmt 1 view .LVU930 + 2825 .LBB376: + 2826 .LBI376: + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 2827 .loc 3 309 22 view .LVU931 + 2828 .LBB377: + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); + 2829 .loc 3 311 3 view .LVU932 + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 2830 .loc 3 312 3 view .LVU933 + 2831 0032 1A6B ldr r2, [r3, #48] + 2832 0034 42F00102 orr r2, r2, #1 + 2833 0038 1A63 str r2, [r3, #48] + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2834 .loc 3 314 3 view .LVU934 + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2835 .loc 3 314 12 is_stmt 0 view .LVU935 + 2836 003a 1B6B ldr r3, [r3, #48] + ARM GAS /tmp/ccWQNJQt.s page 198 + + + 2837 003c 03F00103 and r3, r3, #1 + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 2838 .loc 3 314 10 view .LVU936 + 2839 0040 0093 str r3, [sp] + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 2840 .loc 3 315 3 is_stmt 1 view .LVU937 + 2841 0042 009B ldr r3, [sp] + 2842 .LVL221: + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 2843 .loc 3 315 3 is_stmt 0 view .LVU938 + 2844 .LBE377: + 2845 .LBE376: +1191:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 2846 .loc 1 1191 3 is_stmt 1 view .LVU939 +1191:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 2847 .loc 1 1191 23 is_stmt 0 view .LVU940 + 2848 0044 2023 movs r3, #32 + 2849 0046 0293 str r3, [sp, #8] +1192:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 2850 .loc 1 1192 3 is_stmt 1 view .LVU941 +1192:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 2851 .loc 1 1192 24 is_stmt 0 view .LVU942 + 2852 0048 0225 movs r5, #2 + 2853 004a 0395 str r5, [sp, #12] +1193:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 2854 .loc 1 1193 3 is_stmt 1 view .LVU943 +1193:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 2855 .loc 1 1193 25 is_stmt 0 view .LVU944 + 2856 004c 4FF00308 mov r8, #3 + 2857 0050 CDF81080 str r8, [sp, #16] +1194:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 2858 .loc 1 1194 3 is_stmt 1 view .LVU945 +1195:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; + 2859 .loc 1 1195 3 view .LVU946 +1196:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 2860 .loc 1 1196 3 view .LVU947 +1196:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 2861 .loc 1 1196 29 is_stmt 0 view .LVU948 + 2862 0054 0827 movs r7, #8 + 2863 0056 0797 str r7, [sp, #28] +1197:Src/main.c **** + 2864 .loc 1 1197 3 is_stmt 1 view .LVU949 + 2865 0058 1B4E ldr r6, .L111+4 + 2866 005a 0DEB0701 add r1, sp, r7 + 2867 005e 3046 mov r0, r6 + 2868 0060 FFF7FEFF bl LL_GPIO_Init + 2869 .LVL222: +1199:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 2870 .loc 1 1199 3 view .LVU950 +1199:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 2871 .loc 1 1199 23 is_stmt 0 view .LVU951 + 2872 0064 8023 movs r3, #128 + 2873 0066 0293 str r3, [sp, #8] +1200:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 2874 .loc 1 1200 3 is_stmt 1 view .LVU952 +1200:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 2875 .loc 1 1200 24 is_stmt 0 view .LVU953 + ARM GAS /tmp/ccWQNJQt.s page 199 + + + 2876 0068 0395 str r5, [sp, #12] +1201:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 2877 .loc 1 1201 3 is_stmt 1 view .LVU954 +1201:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 2878 .loc 1 1201 25 is_stmt 0 view .LVU955 + 2879 006a CDF81080 str r8, [sp, #16] +1202:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 2880 .loc 1 1202 3 is_stmt 1 view .LVU956 +1202:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 2881 .loc 1 1202 30 is_stmt 0 view .LVU957 + 2882 006e 0594 str r4, [sp, #20] +1203:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; + 2883 .loc 1 1203 3 is_stmt 1 view .LVU958 +1203:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_8; + 2884 .loc 1 1203 24 is_stmt 0 view .LVU959 + 2885 0070 0694 str r4, [sp, #24] +1204:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 2886 .loc 1 1204 3 is_stmt 1 view .LVU960 +1204:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 2887 .loc 1 1204 29 is_stmt 0 view .LVU961 + 2888 0072 0797 str r7, [sp, #28] +1205:Src/main.c **** + 2889 .loc 1 1205 3 is_stmt 1 view .LVU962 + 2890 0074 0DEB0701 add r1, sp, r7 + 2891 0078 3046 mov r0, r6 + 2892 007a FFF7FEFF bl LL_GPIO_Init + 2893 .LVL223: +1211:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; + 2894 .loc 1 1211 3 view .LVU963 +1211:Src/main.c **** SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; + 2895 .loc 1 1211 36 is_stmt 0 view .LVU964 + 2896 007e 0894 str r4, [sp, #32] +1212:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; + 2897 .loc 1 1212 3 is_stmt 1 view .LVU965 +1212:Src/main.c **** SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT; + 2898 .loc 1 1212 23 is_stmt 0 view .LVU966 + 2899 0080 4FF48273 mov r3, #260 + 2900 0084 0993 str r3, [sp, #36] +1213:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; + 2901 .loc 1 1213 3 is_stmt 1 view .LVU967 +1213:Src/main.c **** SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_HIGH; + 2902 .loc 1 1213 28 is_stmt 0 view .LVU968 + 2903 0086 4FF47063 mov r3, #3840 + 2904 008a 0A93 str r3, [sp, #40] +1214:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; + 2905 .loc 1 1214 3 is_stmt 1 view .LVU969 +1214:Src/main.c **** SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; + 2906 .loc 1 1214 32 is_stmt 0 view .LVU970 + 2907 008c 0B95 str r5, [sp, #44] +1215:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; + 2908 .loc 1 1215 3 is_stmt 1 view .LVU971 +1215:Src/main.c **** SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; + 2909 .loc 1 1215 29 is_stmt 0 view .LVU972 + 2910 008e 0123 movs r3, #1 + 2911 0090 0C93 str r3, [sp, #48] +1216:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; + 2912 .loc 1 1216 3 is_stmt 1 view .LVU973 + ARM GAS /tmp/ccWQNJQt.s page 200 + + +1216:Src/main.c **** SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; + 2913 .loc 1 1216 22 is_stmt 0 view .LVU974 + 2914 0092 4FF40073 mov r3, #512 + 2915 0096 0D93 str r3, [sp, #52] +1217:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; + 2916 .loc 1 1217 3 is_stmt 1 view .LVU975 +1217:Src/main.c **** SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; + 2917 .loc 1 1217 27 is_stmt 0 view .LVU976 + 2918 0098 1823 movs r3, #24 + 2919 009a 0E93 str r3, [sp, #56] +1218:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; + 2920 .loc 1 1218 3 is_stmt 1 view .LVU977 +1218:Src/main.c **** SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; + 2921 .loc 1 1218 27 is_stmt 0 view .LVU978 + 2922 009c 0F94 str r4, [sp, #60] +1219:Src/main.c **** SPI_InitStruct.CRCPoly = 7; + 2923 .loc 1 1219 3 is_stmt 1 view .LVU979 +1219:Src/main.c **** SPI_InitStruct.CRCPoly = 7; + 2924 .loc 1 1219 33 is_stmt 0 view .LVU980 + 2925 009e 1094 str r4, [sp, #64] +1220:Src/main.c **** LL_SPI_Init(SPI6, &SPI_InitStruct); + 2926 .loc 1 1220 3 is_stmt 1 view .LVU981 +1220:Src/main.c **** LL_SPI_Init(SPI6, &SPI_InitStruct); + 2927 .loc 1 1220 26 is_stmt 0 view .LVU982 + 2928 00a0 0723 movs r3, #7 + 2929 00a2 1193 str r3, [sp, #68] +1221:Src/main.c **** LL_SPI_SetStandard(SPI6, LL_SPI_PROTOCOL_MOTOROLA); + 2930 .loc 1 1221 3 is_stmt 1 view .LVU983 + 2931 00a4 094C ldr r4, .L111+8 + 2932 00a6 08A9 add r1, sp, #32 + 2933 00a8 2046 mov r0, r4 + 2934 00aa FFF7FEFF bl LL_SPI_Init + 2935 .LVL224: +1222:Src/main.c **** LL_SPI_DisableNSSPulseMgt(SPI6); + 2936 .loc 1 1222 3 view .LVU984 + 2937 .LBB378: + 2938 .LBI378: + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 2939 .loc 4 426 22 view .LVU985 + 2940 .LBB379: + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 2941 .loc 4 428 3 view .LVU986 + 2942 00ae 6368 ldr r3, [r4, #4] + 2943 00b0 23F01003 bic r3, r3, #16 + 2944 00b4 6360 str r3, [r4, #4] + 2945 .LVL225: + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 2946 .loc 4 428 3 is_stmt 0 view .LVU987 + 2947 .LBE379: + 2948 .LBE378: +1223:Src/main.c **** /* USER CODE BEGIN SPI6_Init 2 */ + 2949 .loc 1 1223 3 is_stmt 1 view .LVU988 + 2950 .LBB380: + 2951 .LBI380: + 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 2952 .loc 4 874 22 view .LVU989 + 2953 .LBB381: + ARM GAS /tmp/ccWQNJQt.s page 201 + + + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 2954 .loc 4 876 3 view .LVU990 + 2955 00b6 6368 ldr r3, [r4, #4] + 2956 00b8 23F00803 bic r3, r3, #8 + 2957 00bc 6360 str r3, [r4, #4] + 2958 .LVL226: + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 2959 .loc 4 876 3 is_stmt 0 view .LVU991 + 2960 .LBE381: + 2961 .LBE380: +1228:Src/main.c **** + 2962 .loc 1 1228 1 view .LVU992 + 2963 00be 12B0 add sp, sp, #72 + 2964 .LCFI26: + 2965 .cfi_def_cfa_offset 24 + 2966 @ sp needed + 2967 00c0 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 2968 .L112: + 2969 .align 2 + 2970 .L111: + 2971 00c4 00380240 .word 1073887232 + 2972 00c8 00000240 .word 1073872896 + 2973 00cc 00540140 .word 1073828864 + 2974 .cfi_endproc + 2975 .LFE1194: + 2977 .section .text.MX_TIM2_Init,"ax",%progbits + 2978 .align 1 + 2979 .syntax unified + 2980 .thumb + 2981 .thumb_func + 2983 MX_TIM2_Init: + 2984 .LFB1195: +1236:Src/main.c **** + 2985 .loc 1 1236 1 is_stmt 1 view -0 + 2986 .cfi_startproc + 2987 @ args = 0, pretend = 0, frame = 24 + 2988 @ frame_needed = 0, uses_anonymous_args = 0 + 2989 0000 10B5 push {r4, lr} + 2990 .LCFI27: + 2991 .cfi_def_cfa_offset 8 + 2992 .cfi_offset 4, -8 + 2993 .cfi_offset 14, -4 + 2994 0002 86B0 sub sp, sp, #24 + 2995 .LCFI28: + 2996 .cfi_def_cfa_offset 32 +1242:Src/main.c **** + 2997 .loc 1 1242 3 view .LVU994 +1242:Src/main.c **** + 2998 .loc 1 1242 22 is_stmt 0 view .LVU995 + 2999 0004 0024 movs r4, #0 + 3000 0006 0194 str r4, [sp, #4] + 3001 0008 0294 str r4, [sp, #8] + 3002 000a 0394 str r4, [sp, #12] + 3003 000c 0494 str r4, [sp, #16] + 3004 000e 0594 str r4, [sp, #20] +1245:Src/main.c **** + 3005 .loc 1 1245 3 is_stmt 1 view .LVU996 + ARM GAS /tmp/ccWQNJQt.s page 202 + + + 3006 .LVL227: + 3007 .LBB382: + 3008 .LBI382: +1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 3009 .loc 3 1071 22 view .LVU997 + 3010 .LBB383: +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); + 3011 .loc 3 1073 3 view .LVU998 +1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 3012 .loc 3 1074 3 view .LVU999 + 3013 0010 1D4B ldr r3, .L115 + 3014 0012 1A6C ldr r2, [r3, #64] + 3015 0014 42F00102 orr r2, r2, #1 + 3016 0018 1A64 str r2, [r3, #64] +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 3017 .loc 3 1076 3 view .LVU1000 +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 3018 .loc 3 1076 12 is_stmt 0 view .LVU1001 + 3019 001a 1B6C ldr r3, [r3, #64] + 3020 001c 03F00103 and r3, r3, #1 +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 3021 .loc 3 1076 10 view .LVU1002 + 3022 0020 0093 str r3, [sp] +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 3023 .loc 3 1077 3 is_stmt 1 view .LVU1003 + 3024 0022 009B ldr r3, [sp] + 3025 .LVL228: +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 3026 .loc 3 1077 3 is_stmt 0 view .LVU1004 + 3027 .LBE383: + 3028 .LBE382: +1248:Src/main.c **** NVIC_EnableIRQ(TIM2_IRQn); + 3029 .loc 1 1248 3 is_stmt 1 view .LVU1005 + 3030 .LBB384: + 3031 .LBI384: +1884:Drivers/CMSIS/Include/core_cm7.h **** { + 3032 .loc 2 1884 26 view .LVU1006 + 3033 .LBB385: +1886:Drivers/CMSIS/Include/core_cm7.h **** } + 3034 .loc 2 1886 3 view .LVU1007 +1886:Drivers/CMSIS/Include/core_cm7.h **** } + 3035 .loc 2 1886 26 is_stmt 0 view .LVU1008 + 3036 0024 194B ldr r3, .L115+4 + 3037 0026 D868 ldr r0, [r3, #12] + 3038 .LBE385: + 3039 .LBE384: +1248:Src/main.c **** NVIC_EnableIRQ(TIM2_IRQn); + 3040 .loc 1 1248 3 discriminator 1 view .LVU1009 + 3041 0028 2246 mov r2, r4 + 3042 002a 2146 mov r1, r4 + 3043 002c C0F30220 ubfx r0, r0, #8, #3 + 3044 0030 FFF7FEFF bl NVIC_EncodePriority + 3045 .LVL229: + 3046 .LBB386: + 3047 .LBI386: +2024:Drivers/CMSIS/Include/core_cm7.h **** { + 3048 .loc 2 2024 22 is_stmt 1 view .LVU1010 + ARM GAS /tmp/ccWQNJQt.s page 203 + + + 3049 .LBB387: +2026:Drivers/CMSIS/Include/core_cm7.h **** { + 3050 .loc 2 2026 3 view .LVU1011 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 3051 .loc 2 2028 5 view .LVU1012 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 3052 .loc 2 2028 49 is_stmt 0 view .LVU1013 + 3053 0034 0001 lsls r0, r0, #4 + 3054 .LVL230: +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 3055 .loc 2 2028 49 view .LVU1014 + 3056 0036 C0B2 uxtb r0, r0 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 3057 .loc 2 2028 47 view .LVU1015 + 3058 0038 154B ldr r3, .L115+8 + 3059 003a 83F81C03 strb r0, [r3, #796] + 3060 .LVL231: +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 3061 .loc 2 2028 47 view .LVU1016 + 3062 .LBE387: + 3063 .LBE386: +1249:Src/main.c **** + 3064 .loc 1 1249 3 is_stmt 1 view .LVU1017 + 3065 .LBB388: + 3066 .LBI388: +1896:Drivers/CMSIS/Include/core_cm7.h **** { + 3067 .loc 2 1896 22 view .LVU1018 + 3068 .LBB389: +1898:Drivers/CMSIS/Include/core_cm7.h **** { + 3069 .loc 2 1898 3 view .LVU1019 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 3070 .loc 2 1900 5 view .LVU1020 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 3071 .loc 2 1900 43 is_stmt 0 view .LVU1021 + 3072 003e 4FF08052 mov r2, #268435456 + 3073 0042 1A60 str r2, [r3] + 3074 .LVL232: +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 3075 .loc 2 1900 43 view .LVU1022 + 3076 .LBE389: + 3077 .LBE388: +1254:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; + 3078 .loc 1 1254 3 is_stmt 1 view .LVU1023 +1254:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; + 3079 .loc 1 1254 28 is_stmt 0 view .LVU1024 + 3080 0044 4FF47A73 mov r3, #1000 + 3081 0048 ADF80430 strh r3, [sp, #4] @ movhi +1255:Src/main.c **** TIM_InitStruct.Autoreload = 840000; + 3082 .loc 1 1255 3 is_stmt 1 view .LVU1025 +1255:Src/main.c **** TIM_InitStruct.Autoreload = 840000; + 3083 .loc 1 1255 30 is_stmt 0 view .LVU1026 + 3084 004c 0294 str r4, [sp, #8] +1256:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + 3085 .loc 1 1256 3 is_stmt 1 view .LVU1027 +1256:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + 3086 .loc 1 1256 29 is_stmt 0 view .LVU1028 + 3087 004e 114B ldr r3, .L115+12 + ARM GAS /tmp/ccWQNJQt.s page 204 + + + 3088 0050 0393 str r3, [sp, #12] +1257:Src/main.c **** LL_TIM_Init(TIM2, &TIM_InitStruct); + 3089 .loc 1 1257 3 is_stmt 1 view .LVU1029 +1257:Src/main.c **** LL_TIM_Init(TIM2, &TIM_InitStruct); + 3090 .loc 1 1257 32 is_stmt 0 view .LVU1030 + 3091 0052 0494 str r4, [sp, #16] +1258:Src/main.c **** LL_TIM_DisableARRPreload(TIM2); + 3092 .loc 1 1258 3 is_stmt 1 view .LVU1031 + 3093 0054 01A9 add r1, sp, #4 + 3094 0056 4FF08040 mov r0, #1073741824 + 3095 005a FFF7FEFF bl LL_TIM_Init + 3096 .LVL233: +1259:Src/main.c **** LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL); + 3097 .loc 1 1259 3 view .LVU1032 + 3098 .LBB390: + 3099 .LBI390: + 3100 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @file stm32f7xx_ll_tim.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Header file of TIM LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * This software is licensed under terms that can be found in the LICENSE file + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifndef __STM32F7xx_LL_TIM_H + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __STM32F7xx_LL_TIM_H + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifdef __cplusplus + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** extern "C" { + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Includes ------------------------------------------------------------------*/ + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #include "stm32f7xx.h" + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @addtogroup STM32F7xx_LL_Driver + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defi + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL TIM + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private types -------------------------------------------------------------*/ + ARM GAS /tmp/ccWQNJQt.s page 205 + + + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private variables ---------------------------------------------------------*/ + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Variables TIM Private Variables + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t OFFSET_TAB_CCMRx[] = + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 0: TIMx_CH1 */ + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 1: TIMx_CH1N */ + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 2: TIMx_CH2 */ + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 3: TIMx_CH2N */ + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 4: TIMx_CH3 */ + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 5: TIMx_CH3N */ + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 6: TIMx_CH4 */ + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x3CU, /* 7: TIMx_CH5 */ + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x3CU /* 8: TIMx_CH6 */ + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OCxx[] = + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: OC1M, OC1FE, OC1PE */ + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 1: - NA */ + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 2: OC2M, OC2FE, OC2PE */ + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 3: - NA */ + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 4: OC3M, OC3FE, OC3PE */ + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 5: - NA */ + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 6: OC4M, OC4FE, OC4PE */ + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 7: OC5M, OC5FE, OC5PE */ + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U /* 8: OC6M, OC6FE, OC6PE */ + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_ICxx[] = + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: CC1S, IC1PSC, IC1F */ + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 1: - NA */ + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 2: CC2S, IC2PSC, IC2F */ + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 3: - NA */ + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 4: CC3S, IC3PSC, IC3F */ + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 5: - NA */ + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 6: CC4S, IC4PSC, IC4F */ + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 7: - NA */ + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U /* 8: - NA */ + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_CCxP[] = + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: CC1P */ + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2U, /* 1: CC1NP */ + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4U, /* 2: CC2P */ + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 6U, /* 3: CC2NP */ + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 4: CC3P */ + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 10U, /* 5: CC3NP */ + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 12U, /* 6: CC4P */ + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 16U, /* 7: CC5P */ + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 20U /* 8: CC6P */ + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OISx[] = + ARM GAS /tmp/ccWQNJQt.s page 206 + + + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: OIS1 */ + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1U, /* 1: OIS1N */ + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2U, /* 2: OIS2 */ + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3U, /* 3: OIS2N */ + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4U, /* 4: OIS3 */ + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 5U, /* 5: OIS3N */ + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 6U, /* 6: OIS4 */ + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 7: OIS5 */ + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 10U /* 8: OIS6 */ + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private constants ---------------------------------------------------------*/ + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Constants TIM Private Constants + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(TIM_BREAK_INPUT_SUPPORT) + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Defines used for the bit position in the register and perform offsets */ + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Generic bit definitions for TIMx_AF1 register */ + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */ + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Remap mask definitions */ + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_SHIFT 16U + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_MASK 0x0000FFFFU + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT) + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM5_OR_RMP_MASK (TIM5_OR_TI4_RMP << TIMx_OR_RMP_SHIFT) + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM11_OR_RMP_MASK (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_1 ((uint8_t)0x7F) + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_2 ((uint8_t)0x3F) + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_3 ((uint8_t)0x1F) + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_4 ((uint8_t)0x1F) + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_1 ((uint8_t)0x00) + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_2 ((uint8_t)0x80) + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_3 ((uint8_t)0xC0) + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_4 ((uint8_t)0xE0) + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private macros ------------------------------------------------------------*/ + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Macros TIM Private Macros + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief Convert channel id into channel index. + ARM GAS /tmp/ccWQNJQt.s page 207 + + + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CHANNEL__ This parameter can be one of the following values: + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval none + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief Calculate the deadtime sampling period(in ps). + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz). + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CKD__ This parameter can be one of the following values: + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval none + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported types ------------------------------------------------------------*/ + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Time Base configuration structure definition. + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data=0x0000 and Max_D + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetPrescaler().*/ + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CounterMode; /*!< Specifies the counter mode. + ARM GAS /tmp/ccWQNJQt.s page 208 + + + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetCounterMode().*/ + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Auto-Reload Register at the next update event. + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter must be a number between Min_Data=0x0000 and Max_ + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Some timer instances may support 32 bits counters. In that case + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** be a number between 0x0000 and 0xFFFFFFFF. + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetAutoReload().*/ + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ClockDivision; /*!< Specifies the clock division. + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetClockDivision().*/ + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downc + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** reaches zero, an update event is generated and counting restarts + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** from the RCR value (N). + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This means in PWM mode that (N+1) corresponds to: + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** - the number of PWM periods in edge-aligned mode + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** - the number of half PWM period in center-aligned mode + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** GP timers: this parameter must be a number between Min_Data = 0x + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Max_Data = 0xFF. + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Advanced timers: this parameter must be a number between Min_Dat + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Max_Data = 0xFFFF. + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetRepetitionCounter().*/ + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_InitTypeDef; + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Output Compare configuration structure definition. + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCMode; /*!< Specifies the output mode. + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCMODE. + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetMode().*/ + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCState; /*!< Specifies the TIM Output Compare state. + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functions + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functions + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + ARM GAS /tmp/ccWQNJQt.s page 209 + + + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Re + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data=0x0000 and Max_Data= + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** LL_TIM_OC_SetCompareCHx (x=1..6).*/ + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCPolarity; /*!< Specifies the output polarity. + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetPolarity().*/ + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetPolarity().*/ + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetIdleState().*/ + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetIdleState().*/ + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_OC_InitTypeDef; + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Input Capture configuration structure definition. + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICActiveInput; /*!< Specifies the input. + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ + ARM GAS /tmp/ccWQNJQt.s page 210 + + + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICFilter; /*!< Specifies the input capture filter. + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_IC_InitTypeDef; + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Encoder interface configuration structure definition. + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetEncoderMode().*/ + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. + ARM GAS /tmp/ccWQNJQt.s page 211 + + + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Filter; /*!< Specifies the TI2 input filter. + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_ENCODER_InitTypeDef; + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Hall sensor interface configuration structure definition. + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Prescaler must be set to get a maximum counter period longer th + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** time interval between 2 consecutive changes on the Hall inputs. + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref TIM_LL_EC_IC_FILTER. + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compa + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** A positive pulse (TRGO event) is generated with a programmable + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** a change occurs on the Hall inputs. + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data = 0x0000 and Ma + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetCompareCH2().*/ + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_HALLSENSOR_InitTypeDef; + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief BDTR (Break and Dead Time) structure definition + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OSSR + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + ARM GAS /tmp/ccWQNJQt.s page 212 + + + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetOffStates() + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field cannot be modified as long as LOCK level + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OSSI + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetOffStates() + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field cannot be modified as long as LOCK level + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t LockLevel; /*!< Specifies the LOCK level parameters. + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note The LOCK bits can be written only once after the reset. + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** register has been written, their content is frozen until the + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** switching-on of the outputs. + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data = 0x00 and Ma + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetDeadTime() + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARIT + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK() + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK() + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + ARM GAS /tmp/ccWQNJQt.s page 213 + + + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARI + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK2() + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK2() + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTP + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAut + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_BDTR_InitTypeDef; + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported constants --------------------------------------------------------*/ + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Flags defines which can be used with LL_TIM_ReadReg function. + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrup + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrup + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrup + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrup + ARM GAS /tmp/ccWQNJQt.s page 214 + + + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrup + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrup + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt fla + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapt + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapt + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapt + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapt + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt fla + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by softw + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_IT IT Defines + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrup + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrup + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrup + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrup + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable * + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + ARM GAS /tmp/ccWQNJQt.s page 215 + + + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/unde + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounte + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and + 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and + 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and + 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division + 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ + 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ + 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction + 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ + 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down + 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bi + 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bi + ARM GAS /tmp/ccWQNJQt.s page 216 + + + 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request + 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when + 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when + 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level + 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write + 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ + 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ + 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ + 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CHANNEL Channel + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 + 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output ch + 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 + 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output ch + 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 + 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output ch + 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 + 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ + 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ + 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) + 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State + 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ + 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on + 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ + 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** Legacy definitions for compatibility purpose + 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @cond 0 + 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1 + 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2 + 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + ARM GAS /tmp/ccWQNJQt.s page 217 + + + 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @endcond + 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode + 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FROZEN 0x00000000U + 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 + 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 + 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) + 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 + 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) + 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) + 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1 + 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) + 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) + 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1 + 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1 + 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) + 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity + 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ + 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ + 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State + 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!__REG__, (__VAL +1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Read a value in TIM register. +1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __INSTANCE__ TIM Instance +1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __REG__ Register to be read +1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Register value +1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro retrieving the UIFCPY flag from the counter value. +1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); +1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied +1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * to TIMx_CNT register bit 31) +1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CNT__ Counter value +1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval UIF status bit +1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ +1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) +1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested de +1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); +1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) +1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CKD__ This parameter can be one of the following values: +1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 +1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 +1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 +1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DT__ deadtime duration (in ns) +1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval DTG[0:7] +1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ +1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? +1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : +1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__C +1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMC +1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) +1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__C +1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC +1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) +1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__ +1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC +1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) +1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U) +1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the prescaler value to achieve the required counter clock freq +1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); +1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) +1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CNTCLK__ counter clock frequency (in Hz) + ARM GAS /tmp/ccWQNJQt.s page 226 + + +1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) +1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ +1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U +1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal fr +1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); +1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) +1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler +1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __FREQ__ output signal frequency (in Hz) +1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) +1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ +1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) +1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the compare value required to achieve the required timer outpu +1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * active/inactive delay. +1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); +1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) +1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler +1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DELAY__ timer output compare active/inactive delay (in us) +1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Compare value (between Min_Data=0 and Max_Data=65535) +1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ +1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ +1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) +1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration +1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (when the timer operates in one pulse mode). +1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); +1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) +1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler +1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DELAY__ timer output compare active/inactive delay (in us) +1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PULSE__ pulse duration (in us) +1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) +1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ +1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ +1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) +1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro retrieving the ratio of the input capture prescaler +1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); +1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __ICPSC__ This parameter can be one of the following values: +1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 +1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 +1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 +1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 +1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Input capture prescaler ratio (1, 2, 4 or 8) +1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ +1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) +1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + ARM GAS /tmp/ccWQNJQt.s page 227 + + +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported functions --------------------------------------------------------*/ +1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions +1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Time_Base Time Base configuration +1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable timer counter. +1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_EnableCounter +1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) +1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_CEN); +1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable timer counter. +1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_DisableCounter +1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) +1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); +1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the timer counter is enabled. +1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter +1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) +1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); +1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable update event generation. +1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent +1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) +1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); +1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + ARM GAS /tmp/ccWQNJQt.s page 228 + + +1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable update event generation. +1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent +1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) +1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_UDIS); +1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether update event generation is enabled. +1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent +1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Inverted state of bit (0 or 1). +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); +1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set update event source +1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * generate an update interrupt or DMA request if enabled: +1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Counter overflow/underflow +1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Setting the UG bit +1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Update generation through the slave mode controller +1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter +1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * overflow/underflow generates an update interrupt or DMA request if enabled. +1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 URS LL_TIM_SetUpdateSource +1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param UpdateSource This parameter can be one of the following values: +1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_REGULAR +1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_COUNTER +1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) +1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); +1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual event update source +1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 URS LL_TIM_GetUpdateSource +1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_REGULAR +1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_COUNTER +1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) +1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); +1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set one pulse mode (one shot v.s. repetitive). + ARM GAS /tmp/ccWQNJQt.s page 229 + + +1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode +1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OnePulseMode This parameter can be one of the following values: +1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE +1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE +1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) +1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); +1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual one pulse mode. +1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode +1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE +1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE +1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) +1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); +1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the timer counter counting mode. +1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to +1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * check whether or not the counter mode selection feature is supported +1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * by a timer instance. +1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) +1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * requires a timer reset to avoid unexpected direction +1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * due to DIR bit readonly in center aligned mode. +1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n +1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR1 CMS LL_TIM_SetCounterMode +1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CounterMode This parameter can be one of the following values: +1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_UP +1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_DOWN +1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP +1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN +1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN +1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) +1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); +1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual counter mode. +1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to +1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * check whether or not the counter mode selection feature is supported +1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * by a timer instance. +1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n +1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR1 CMS LL_TIM_GetCounterMode +1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance + ARM GAS /tmp/ccWQNJQt.s page 230 + + +1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_UP +1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_DOWN +1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP +1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN +1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN +1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) +1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t counter_mode; +1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); +1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** if (counter_mode == 0U) +1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return counter_mode; +1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable auto-reload (ARR) preload. +1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload +1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) +1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_ARPE); +1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable auto-reload (ARR) preload. +1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload +1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) + 3101 .loc 5 1504 22 view .LVU1033 + 3102 .LBB391: +1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); + 3103 .loc 5 1506 3 view .LVU1034 + 3104 005e 4FF08043 mov r3, #1073741824 + 3105 0062 1A68 ldr r2, [r3] + 3106 0064 22F08002 bic r2, r2, #128 + 3107 0068 1A60 str r2, [r3] + 3108 .LVL234: + 3109 .loc 5 1506 3 is_stmt 0 view .LVU1035 + 3110 .LBE391: + 3111 .LBE390: +1260:Src/main.c **** LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET); + 3112 .loc 1 1260 3 is_stmt 1 view .LVU1036 + 3113 .LBB392: + 3114 .LBI392: +1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + ARM GAS /tmp/ccWQNJQt.s page 231 + + +1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether auto-reload (ARR) preload is enabled. +1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload +1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) +1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); +1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the division ratio between the timer clock and the sampling clock used by the dead +1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (when supported) and the digital filters. +1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check +1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not the clock division feature is supported by the timer +1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * instance. +1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CKD LL_TIM_SetClockDivision +1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ClockDivision This parameter can be one of the following values: +1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 +1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 +1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 +1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) +1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); +1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the actual division ratio between the timer clock and the sampling clock used by t +1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * generators (when supported) and the digital filters. +1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check +1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not the clock division feature is supported by the timer +1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * instance. +1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CKD LL_TIM_GetClockDivision +1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 +1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 +1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 +1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) +1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); +1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the counter value. +1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CNT CNT LL_TIM_SetCounter +1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) +1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None + ARM GAS /tmp/ccWQNJQt.s page 232 + + +1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CNT, Counter); +1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the counter value. +1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CNT CNT LL_TIM_GetCounter +1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) +1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) +1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CNT)); +1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current direction of the counter +1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_GetDirection +1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERDIRECTION_UP +1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN +1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) +1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the prescaler value. +1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). +1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The prescaler can be changed on the fly as this control register is buffered. The new +1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * prescaler ratio is taken into account at the next update event. +1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter +1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll PSC PSC LL_TIM_SetPrescaler +1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Prescaler between Min_Data=0 and Max_Data=65535 +1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) +1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->PSC, Prescaler); +1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the prescaler value. +1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll PSC PSC LL_TIM_GetPrescaler +1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Prescaler value between Min_Data=0 and Max_Data=65535 +1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) +1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->PSC)); + ARM GAS /tmp/ccWQNJQt.s page 233 + + +1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the auto-reload value. +1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The counter is blocked while the auto-reload value is null. +1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter +1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll ARR ARR LL_TIM_SetAutoReload +1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param AutoReload between Min_Data=0 and Max_Data=65535 +1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) +1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->ARR, AutoReload); +1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the auto-reload value. +1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll ARR ARR LL_TIM_GetAutoReload +1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value +1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) +1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->ARR)); +1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the repetition counter value. +1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note For advanced timer instances RepetitionCounter can be up to 65535. +1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check +1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a repetition counter. +1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll RCR REP LL_TIM_SetRepetitionCounter +1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. +1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) +1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->RCR, RepetitionCounter); +1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the repetition counter value. +1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check +1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a repetition counter. +1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll RCR REP LL_TIM_GetRepetitionCounter +1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Repetition counter value +1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) +1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->RCR)); + ARM GAS /tmp/ccWQNJQt.s page 234 + + +1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter regis +1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This allows both the counter value and a potential roll-over condition signalled by the U +1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in an atomic way. +1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap +1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) +1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable update interrupt flag (UIF) remapping. +1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap +1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) +1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether update interrupt flag (UIF) copy is set. +1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Counter Counter value +1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) +1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); +1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration +1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. +1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, +1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * they are updated only when a commutation event (COM) occurs. +1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Only on channels that have a complementary output. +1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check +1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. +1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload +1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) +1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR2, TIM_CR2_CCPC); + ARM GAS /tmp/ccWQNJQt.s page 235 + + +1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. +1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check +1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. +1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload +1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) +1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); +1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is en +1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload +1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). +1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check +1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. +1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate +1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CCUpdateSource This parameter can be one of the following values: +1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI +1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) +1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); +1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger of the capture/compare DMA request. +1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger +1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMAReqTrigger This parameter can be one of the following values: +1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_CC +1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE +1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) +1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); +1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + ARM GAS /tmp/ccWQNJQt.s page 236 + + +1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual trigger of the capture/compare DMA request. +1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger +1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_CC +1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE +1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) +1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); +1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the lock level to freeze the +1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * configuration of several capture/compare parameters. +1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the lock mechanism is supported by a timer instance. +1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel +1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param LockLevel This parameter can be one of the following values: +1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_OFF +1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_1 +1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_2 +1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_3 +1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) +1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); +1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable capture/compare channels. +1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_EnableChannel\n +1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_EnableChannel\n +1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_EnableChannel\n +1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_EnableChannel\n +1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_EnableChannel\n +1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_EnableChannel\n +1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_EnableChannel\n +1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_EnableChannel +1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: +1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + ARM GAS /tmp/ccWQNJQt.s page 237 + + +1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CCER, Channels); +1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable capture/compare channels. +1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n +1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_DisableChannel\n +1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_DisableChannel\n +1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_DisableChannel\n +1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_DisableChannel\n +1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_DisableChannel\n +1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_DisableChannel\n +1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_DisableChannel\n +1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_DisableChannel +1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: +1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CCER, Channels); +1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether channel(s) is(are) enabled. +1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n +1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n +1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_IsEnabledChannel\n +1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n +1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_IsEnabledChannel\n +1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n +1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_IsEnabledChannel\n +1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_IsEnabledChannel\n +1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_IsEnabledChannel +1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: +1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) + ARM GAS /tmp/ccWQNJQt.s page 238 + + +1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); +1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration +1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure an output channel. +1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n +1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n +1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n +1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n +1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n +1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n +1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1P LL_TIM_OC_ConfigOutput\n +1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_ConfigOutput\n +1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_ConfigOutput\n +1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_ConfigOutput\n +1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_ConfigOutput\n +1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_ConfigOutput\n +1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS1 LL_TIM_OC_ConfigOutput\n +1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_ConfigOutput\n +1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_ConfigOutput\n +1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_ConfigOutput\n +1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_ConfigOutput\n +1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_ConfigOutput +1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Configuration This parameter must be a combination of all the following values: +1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW +1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH +1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configura +1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); +1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), +1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); +1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), +1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); +1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Define the behavior of the output reference signal OCxREF from which + ARM GAS /tmp/ccWQNJQt.s page 239 + + +1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * OCx and OCxN (when relevant) are derived. +1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n +1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2M LL_TIM_OC_SetMode\n +1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3M LL_TIM_OC_SetMode\n +1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4M LL_TIM_OC_SetMode\n +1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5M LL_TIM_OC_SetMode\n +1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6M LL_TIM_OC_SetMode +1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Mode This parameter can be one of the following values: +1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FROZEN +1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ACTIVE +1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_INACTIVE +1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_TOGGLE +1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE +1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE +1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM1 +1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM2 +1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 +1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 +1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 +1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 +1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 +1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 +1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) +1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT +2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the output compare mode of an output channel. +2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n +2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2M LL_TIM_OC_GetMode\n +2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3M LL_TIM_OC_GetMode\n +2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4M LL_TIM_OC_GetMode\n +2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5M LL_TIM_OC_GetMode\n +2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6M LL_TIM_OC_GetMode +2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FROZEN + ARM GAS /tmp/ccWQNJQt.s page 240 + + +2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ACTIVE +2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_INACTIVE +2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_TOGGLE +2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE +2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE +2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM1 +2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM2 +2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 +2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 +2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 +2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 +2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) +2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT +2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the polarity of an output channel. +2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n +2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_OC_SetPolarity\n +2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_SetPolarity\n +2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_OC_SetPolarity\n +2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_SetPolarity\n +2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_OC_SetPolarity\n +2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_SetPolarity\n +2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_SetPolarity\n +2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_SetPolarity +2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Polarity This parameter can be one of the following values: +2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH +2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_LOW +2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) +2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[i +2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the polarity of an output channel. +2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n + ARM GAS /tmp/ccWQNJQt.s page 241 + + +2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_OC_GetPolarity\n +2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_GetPolarity\n +2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_OC_GetPolarity\n +2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_GetPolarity\n +2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_OC_GetPolarity\n +2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_GetPolarity\n +2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_GetPolarity\n +2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_GetPolarity +2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH +2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_LOW +2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChan +2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the IDLE state of an output channel +2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function is significant only for the timer instances +2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) +2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * can be used to check whether or not a timer instance provides +2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a break input. +2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n +2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_SetIdleState\n +2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_SetIdleState\n +2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_SetIdleState\n +2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_SetIdleState\n +2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3N LL_TIM_OC_SetIdleState\n +2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_SetIdleState\n +2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_SetIdleState\n +2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_SetIdleState +2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param IdleState This parameter can be one of the following values: +2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW + ARM GAS /tmp/ccWQNJQt.s page 242 + + +2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_HIGH +2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState +2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iC +2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the IDLE state of an output channel +2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n +2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_GetIdleState\n +2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_GetIdleState\n +2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_GetIdleState\n +2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_GetIdleState\n +2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3N LL_TIM_OC_GetIdleState\n +2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_GetIdleState\n +2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_GetIdleState\n +2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_GetIdleState +2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW +2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_HIGH +2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) +2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChanne +2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable fast mode for the output channel. +2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Acts only if the channel is configured in PWM1 or PWM2 mode. +2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n +2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_EnableFast\n +2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_EnableFast\n +2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_EnableFast\n +2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_EnableFast\n +2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_EnableFast +2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 + ARM GAS /tmp/ccWQNJQt.s page 243 + + +2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) +2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); +2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable fast mode for the output channel. +2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n +2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_DisableFast\n +2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_DisableFast\n +2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_DisableFast\n +2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_DisableFast\n +2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_DisableFast +2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) +2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); +2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether fast mode is enabled for the output channel. +2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n +2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n +2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n +2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n +2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n +2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast +2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) +2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + ARM GAS /tmp/ccWQNJQt.s page 244 + + +2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; +2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable compare register (TIMx_CCRx) preload for the output channel. +2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n +2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n +2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n +2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n +2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n +2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_EnablePreload +2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable compare register (TIMx_CCRx) preload for the output channel. +2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n +2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n +2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n +2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n +2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n +2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_DisablePreload +2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + ARM GAS /tmp/ccWQNJQt.s page 245 + + +2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channe +2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n +2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n +2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n +2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n +2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n +2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload +2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) +2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; +2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable clearing the output channel on an external event. +2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function can only be used in Output compare and PWM modes. It does not work in Force +2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether +2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. +2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n +2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_EnableClear\n +2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_EnableClear\n +2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_EnableClear\n +2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_EnableClear\n +2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_EnableClear +2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) +2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable clearing the output channel on an external event. +2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether +2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. + ARM GAS /tmp/ccWQNJQt.s page 246 + + +2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n +2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_DisableClear\n +2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_DisableClear\n +2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_DisableClear\n +2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_DisableClear\n +2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_DisableClear +2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) +2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates clearing the output channel on an external event is enabled for the output ch +2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function enables clearing the output channel on an external event. +2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function can only be used in Output compare and PWM modes. It does not work in Force +2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether +2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. +2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n +2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n +2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n +2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n +2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n +2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear +2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) +2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; +2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal an +2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the Ocx and OCxN signals). +2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + ARM GAS /tmp/ccWQNJQt.s page 247 + + +2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * dead-time insertion feature is supported by a timer instance. +2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter +2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime +2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DeadTime between Min_Data=0 and Max_Data=255 +2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) +2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); +2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 1 (TIMx_CCR1). +2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. +2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not +2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 1 is supported by a timer instance. +2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 +2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) +2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR1, CompareValue); +2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 2 (TIMx_CCR2). +2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. +2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not +2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 2 is supported by a timer instance. +2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 +2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) +2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR2, CompareValue); +2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 3 (TIMx_CCR3). +2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. +2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not +2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel is supported by a timer instance. +2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 +2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None + ARM GAS /tmp/ccWQNJQt.s page 248 + + +2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) +2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR3, CompareValue); +2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 4 (TIMx_CCR4). +2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. +2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not +2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 4 is supported by a timer instance. +2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 +2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) +2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR4, CompareValue); +2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 5 (TIMx_CCR5). +2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not +2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 5 is supported by a timer instance. +2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 +2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) +2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); +2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 6 (TIMx_CCR6). +2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not +2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 6 is supported by a timer instance. +2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 +2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) +2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR6, CompareValue); +2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR1) set for output channel 1. +2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF +2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + ARM GAS /tmp/ccWQNJQt.s page 249 + + +2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 1 is supported by a timer instance. +2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 +2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) +2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR1)); +2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR2) set for output channel 2. +2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF +2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not +2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 2 is supported by a timer instance. +2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 +2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) +2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR2)); +2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR3) set for output channel 3. +2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF +2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not +2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 3 is supported by a timer instance. +2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 +2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) +2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR3)); +2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR4) set for output channel 4. +2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF +2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not +2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 4 is supported by a timer instance. +2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 +2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) +2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR4)); +2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + ARM GAS /tmp/ccWQNJQt.s page 250 + + +2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR5) set for output channel 5. +2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not +2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 5 is supported by a timer instance. +2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 +2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) +2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); +2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR6) set for output channel 6. +2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not +2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 6 is supported by a timer instance. +2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 +2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) +2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR6)); +2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Select on which reference signal the OC5REF is combined to. +2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check +2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports the combined 3-phase PWM mode. +2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n +2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n +2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels +2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param GroupCH5 This parameter can be a combination of the following values: +2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_NONE +2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC1REFC +2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC2REFC +2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC3REFC +2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) +2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); +2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration +2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure input channel. +2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n + ARM GAS /tmp/ccWQNJQt.s page 251 + + +2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC1PSC LL_TIM_IC_Config\n +2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC1F LL_TIM_IC_Config\n +2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_Config\n +2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_Config\n +2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_Config\n +2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_Config\n +2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_Config\n +2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_Config\n +2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_Config\n +2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_Config\n +2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_Config\n +2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1P LL_TIM_IC_Config\n +2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_Config\n +2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_Config\n +2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_Config\n +2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_Config\n +2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_Config\n +2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_Config\n +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_Config +2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Configuration This parameter must be a combination of all the following values: +2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_ +2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 +2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 +2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_I +2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChanne +2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) +2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** << SHIFT_TAB_ICxx[iChannel]); +2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), +2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); +2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the active input. +2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n +2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n +2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n +2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_SetActiveInput +2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICActiveInput This parameter can be one of the following values: +2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + ARM GAS /tmp/ccWQNJQt.s page 252 + + +2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI +2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_TRC +2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiv +2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT +2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current active input. +2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n +2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n +2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n +2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_GetActiveInput +2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI +2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI +2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_TRC +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) +2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann +2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the prescaler of input channel. +2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n +2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n +2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n +2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler +2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICPrescaler This parameter can be one of the following values: +2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 +2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 +2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 +2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 +2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescal +2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + ARM GAS /tmp/ccWQNJQt.s page 253 + + +2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT +2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current prescaler value acting on an input channel. +2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n +2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n +2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n +2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler +2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 +2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 +2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 +2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 +2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) +2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iCha +2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the input filter duration. +2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n +2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_SetFilter\n +2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_SetFilter\n +2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_SetFilter +2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICFilter This parameter can be one of the following values: +2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 +2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 +2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 +2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 +2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 +2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 +2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 +2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 +2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 +2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 +2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 +2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 +2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 +2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 +2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + ARM GAS /tmp/ccWQNJQt.s page 254 + + +2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 +2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) +2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ +2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the input filter duration. +2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n +2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_GetFilter\n +2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_GetFilter\n +2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_GetFilter +2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 +2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 +2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 +2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 +2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 +2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 +2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 +2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 +2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 +2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 +2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 +2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 +2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 +2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 +2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 +2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 +2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) +2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann +2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the input channel polarity. +2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n +2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_SetPolarity\n +2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_SetPolarity\n +2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_SetPolarity\n +2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_SetPolarity\n +2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_SetPolarity\n +2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_SetPolarity\n +2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_SetPolarity + ARM GAS /tmp/ccWQNJQt.s page 255 + + +2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICPolarity This parameter can be one of the following values: +2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING +2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_FALLING +2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE +2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity +2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), +2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ICPolarity << SHIFT_TAB_CCxP[iChannel]); +2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current input channel polarity. +2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n +2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_GetPolarity\n +2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_GetPolarity\n +2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_GetPolarity\n +2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_GetPolarity\n +2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_GetPolarity\n +2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_GetPolarity\n +2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_GetPolarity +2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING +2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_FALLING +2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE +2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> +2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SHIFT_TAB_CCxP[iChannel]); +2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). +2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not +2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. +2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination +2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) +2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + ARM GAS /tmp/ccWQNJQt.s page 256 + + +2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR2, TIM_CR2_TI1S); +2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. +2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not +2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. +2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination +2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) +2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); +2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. +2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not +2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. +2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination +2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) +2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); +2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 1. +2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF +2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not +2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 1 is supported by a timer instance. +2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 +2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) +2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) +2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR1)); +2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 2. +2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF +2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not +2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 2 is supported by a timer instance. +2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 +2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) +2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) + ARM GAS /tmp/ccWQNJQt.s page 257 + + +2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR2)); +2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 3. +2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF +2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not +3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 3 is supported by a timer instance. +3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 +3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) +3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) +3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR3)); +3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 4. +3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF +3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not +3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 4 is supported by a timer instance. +3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 +3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) +3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) +3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR4)); +3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection +3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable external clock mode 2. +3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ET +3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check +3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. +3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_EnableExternalClock +3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) +3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); +3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + ARM GAS /tmp/ccWQNJQt.s page 258 + + +3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable external clock mode 2. +3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check +3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. +3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_DisableExternalClock +3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) +3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); +3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether external clock mode 2 is enabled. +3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check +3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. +3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock +3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) +3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); +3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the clock source of the counter clock. +3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note when selected clock source is external clock mode 1, the timer input +3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() +3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * function. This timer input must be configured by calling +3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the @ref LL_TIM_IC_Config() function. +3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check +3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode1. +3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check +3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. +3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetClockSource\n +3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ECE LL_TIM_SetClockSource +3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ClockSource This parameter can be one of the following values: +3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL +3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 +3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 +3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) + 3115 .loc 5 3092 22 view .LVU1037 + 3116 .LBB393: +3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); + 3117 .loc 5 3094 3 view .LVU1038 + 3118 006a 9968 ldr r1, [r3, #8] + 3119 006c 0A4A ldr r2, .L115+16 + 3120 006e 0A40 ands r2, r2, r1 + 3121 0070 9A60 str r2, [r3, #8] + 3122 .LVL235: + 3123 .loc 5 3094 3 is_stmt 0 view .LVU1039 + ARM GAS /tmp/ccWQNJQt.s page 259 + + + 3124 .LBE393: + 3125 .LBE392: +1261:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM2); + 3126 .loc 1 1261 3 is_stmt 1 view .LVU1040 + 3127 .LBB394: + 3128 .LBI394: +3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the encoder interface mode. +3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check +3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports the encoder mode. +3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetEncoderMode +3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param EncoderMode This parameter can be one of the following values: +3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 +3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 +3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 +3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) +3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); +3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration +3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger output (TRGO) used for timer synchronization . +3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check +3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance can operate as a master timer. +3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput +3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TimerSynchronization This parameter can be one of the following values: +3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_RESET +3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_ENABLE +3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_UPDATE +3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_CC1IF +3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC1REF +3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC2REF +3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC3REF +3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC4REF +3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) + 3129 .loc 5 3138 22 view .LVU1041 + 3130 .LBB395: +3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); + 3131 .loc 5 3140 3 view .LVU1042 + 3132 0072 5A68 ldr r2, [r3, #4] + 3133 0074 22F07002 bic r2, r2, #112 + ARM GAS /tmp/ccWQNJQt.s page 260 + + + 3134 0078 5A60 str r2, [r3, #4] + 3135 .LVL236: + 3136 .loc 5 3140 3 is_stmt 0 view .LVU1043 + 3137 .LBE395: + 3138 .LBE394: +1262:Src/main.c **** /* USER CODE BEGIN TIM2_Init 2 */ + 3139 .loc 1 1262 3 is_stmt 1 view .LVU1044 + 3140 .LBB396: + 3141 .LBI396: +3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . +3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check +3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance can be used for ADC synchronization. +3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 +3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer Instance +3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ADCSynchronization This parameter can be one of the following values: +3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_RESET +3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_ENABLE +3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_UPDATE +3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_CC1F +3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC1 +3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC2 +3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC3 +3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4 +3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5 +3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC6 +3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING +3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING +3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING +3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING +3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING +3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING +3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) +3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); +3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the synchronization mode of a slave timer. +3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. +3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetSlaveMode +3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param SlaveMode This parameter can be one of the following values: +3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_DISABLED +3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_RESET +3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_GATED +3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_TRIGGER +3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER +3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) +3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + ARM GAS /tmp/ccWQNJQt.s page 261 + + +3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); +3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the selects the trigger input to be used to synchronize the counter. +3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. +3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR TS LL_TIM_SetTriggerInput +3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TriggerInput This parameter can be one of the following values: +3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR0 +3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR1 +3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR2 +3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR3 +3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI1F_ED +3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI1FP1 +3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI2FP2 +3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ETRF +3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) +3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); +3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the Master/Slave mode. +3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. +3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode +3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) +3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); +3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the Master/Slave mode. +3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. +3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode +3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) + 3142 .loc 5 3235 22 view .LVU1045 + 3143 .LBB397: +3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); + 3144 .loc 5 3237 3 view .LVU1046 + 3145 007a 9A68 ldr r2, [r3, #8] + 3146 007c 22F08002 bic r2, r2, #128 + 3147 0080 9A60 str r2, [r3, #8] + 3148 .LVL237: + 3149 .loc 5 3237 3 is_stmt 0 view .LVU1047 + ARM GAS /tmp/ccWQNJQt.s page 262 + + + 3150 .LBE397: + 3151 .LBE396: +1267:Src/main.c **** + 3152 .loc 1 1267 1 view .LVU1048 + 3153 0082 06B0 add sp, sp, #24 + 3154 .LCFI29: + 3155 .cfi_def_cfa_offset 8 + 3156 @ sp needed + 3157 0084 10BD pop {r4, pc} + 3158 .L116: + 3159 0086 00BF .align 2 + 3160 .L115: + 3161 0088 00380240 .word 1073887232 + 3162 008c 00ED00E0 .word -536810240 + 3163 0090 00E100E0 .word -536813312 + 3164 0094 40D10C00 .word 840000 + 3165 0098 F8BFFEFF .word -81928 + 3166 .cfi_endproc + 3167 .LFE1195: + 3169 .section .text.MX_TIM5_Init,"ax",%progbits + 3170 .align 1 + 3171 .syntax unified + 3172 .thumb + 3173 .thumb_func + 3175 MX_TIM5_Init: + 3176 .LFB1197: +1334:Src/main.c **** + 3177 .loc 1 1334 1 is_stmt 1 view -0 + 3178 .cfi_startproc + 3179 @ args = 0, pretend = 0, frame = 24 + 3180 @ frame_needed = 0, uses_anonymous_args = 0 + 3181 0000 10B5 push {r4, lr} + 3182 .LCFI30: + 3183 .cfi_def_cfa_offset 8 + 3184 .cfi_offset 4, -8 + 3185 .cfi_offset 14, -4 + 3186 0002 86B0 sub sp, sp, #24 + 3187 .LCFI31: + 3188 .cfi_def_cfa_offset 32 +1340:Src/main.c **** + 3189 .loc 1 1340 3 view .LVU1050 +1340:Src/main.c **** + 3190 .loc 1 1340 22 is_stmt 0 view .LVU1051 + 3191 0004 0024 movs r4, #0 + 3192 0006 0194 str r4, [sp, #4] + 3193 0008 0294 str r4, [sp, #8] + 3194 000a 0394 str r4, [sp, #12] + 3195 000c 0494 str r4, [sp, #16] + 3196 000e 0594 str r4, [sp, #20] +1343:Src/main.c **** + 3197 .loc 1 1343 3 is_stmt 1 view .LVU1052 + 3198 .LVL238: + 3199 .LBB398: + 3200 .LBI398: +1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 3201 .loc 3 1071 22 view .LVU1053 + 3202 .LBB399: + ARM GAS /tmp/ccWQNJQt.s page 263 + + +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); + 3203 .loc 3 1073 3 view .LVU1054 +1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 3204 .loc 3 1074 3 view .LVU1055 + 3205 0010 1C4B ldr r3, .L119 + 3206 0012 1A6C ldr r2, [r3, #64] + 3207 0014 42F00802 orr r2, r2, #8 + 3208 0018 1A64 str r2, [r3, #64] +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 3209 .loc 3 1076 3 view .LVU1056 +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 3210 .loc 3 1076 12 is_stmt 0 view .LVU1057 + 3211 001a 1B6C ldr r3, [r3, #64] + 3212 001c 03F00803 and r3, r3, #8 +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 3213 .loc 3 1076 10 view .LVU1058 + 3214 0020 0093 str r3, [sp] +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 3215 .loc 3 1077 3 is_stmt 1 view .LVU1059 + 3216 0022 009B ldr r3, [sp] + 3217 .LVL239: +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 3218 .loc 3 1077 3 is_stmt 0 view .LVU1060 + 3219 .LBE399: + 3220 .LBE398: +1346:Src/main.c **** NVIC_EnableIRQ(TIM5_IRQn); + 3221 .loc 1 1346 3 is_stmt 1 view .LVU1061 + 3222 .LBB400: + 3223 .LBI400: +1884:Drivers/CMSIS/Include/core_cm7.h **** { + 3224 .loc 2 1884 26 view .LVU1062 + 3225 .LBB401: +1886:Drivers/CMSIS/Include/core_cm7.h **** } + 3226 .loc 2 1886 3 view .LVU1063 +1886:Drivers/CMSIS/Include/core_cm7.h **** } + 3227 .loc 2 1886 26 is_stmt 0 view .LVU1064 + 3228 0024 184B ldr r3, .L119+4 + 3229 0026 D868 ldr r0, [r3, #12] + 3230 .LBE401: + 3231 .LBE400: +1346:Src/main.c **** NVIC_EnableIRQ(TIM5_IRQn); + 3232 .loc 1 1346 3 discriminator 1 view .LVU1065 + 3233 0028 2246 mov r2, r4 + 3234 002a 2146 mov r1, r4 + 3235 002c C0F30220 ubfx r0, r0, #8, #3 + 3236 0030 FFF7FEFF bl NVIC_EncodePriority + 3237 .LVL240: + 3238 .LBB402: + 3239 .LBI402: +2024:Drivers/CMSIS/Include/core_cm7.h **** { + 3240 .loc 2 2024 22 is_stmt 1 view .LVU1066 + 3241 .LBB403: +2026:Drivers/CMSIS/Include/core_cm7.h **** { + 3242 .loc 2 2026 3 view .LVU1067 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 3243 .loc 2 2028 5 view .LVU1068 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + ARM GAS /tmp/ccWQNJQt.s page 264 + + + 3244 .loc 2 2028 49 is_stmt 0 view .LVU1069 + 3245 0034 0001 lsls r0, r0, #4 + 3246 .LVL241: +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 3247 .loc 2 2028 49 view .LVU1070 + 3248 0036 C0B2 uxtb r0, r0 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 3249 .loc 2 2028 47 view .LVU1071 + 3250 0038 144B ldr r3, .L119+8 + 3251 003a 83F83203 strb r0, [r3, #818] + 3252 .LVL242: +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 3253 .loc 2 2028 47 view .LVU1072 + 3254 .LBE403: + 3255 .LBE402: +1347:Src/main.c **** + 3256 .loc 1 1347 3 is_stmt 1 view .LVU1073 + 3257 .LBB404: + 3258 .LBI404: +1896:Drivers/CMSIS/Include/core_cm7.h **** { + 3259 .loc 2 1896 22 view .LVU1074 + 3260 .LBB405: +1898:Drivers/CMSIS/Include/core_cm7.h **** { + 3261 .loc 2 1898 3 view .LVU1075 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 3262 .loc 2 1900 5 view .LVU1076 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 3263 .loc 2 1900 43 is_stmt 0 view .LVU1077 + 3264 003e 4FF48022 mov r2, #262144 + 3265 0042 5A60 str r2, [r3, #4] + 3266 .LVL243: +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 3267 .loc 2 1900 43 view .LVU1078 + 3268 .LBE405: + 3269 .LBE404: +1352:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; + 3270 .loc 1 1352 3 is_stmt 1 view .LVU1079 +1352:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; + 3271 .loc 1 1352 28 is_stmt 0 view .LVU1080 + 3272 0044 42F21073 movw r3, #10000 + 3273 0048 ADF80430 strh r3, [sp, #4] @ movhi +1353:Src/main.c **** TIM_InitStruct.Autoreload = 560; + 3274 .loc 1 1353 3 is_stmt 1 view .LVU1081 +1353:Src/main.c **** TIM_InitStruct.Autoreload = 560; + 3275 .loc 1 1353 30 is_stmt 0 view .LVU1082 + 3276 004c 0294 str r4, [sp, #8] +1354:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + 3277 .loc 1 1354 3 is_stmt 1 view .LVU1083 +1354:Src/main.c **** TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + 3278 .loc 1 1354 29 is_stmt 0 view .LVU1084 + 3279 004e 4FF40C73 mov r3, #560 + 3280 0052 0393 str r3, [sp, #12] +1355:Src/main.c **** LL_TIM_Init(TIM5, &TIM_InitStruct); + 3281 .loc 1 1355 3 is_stmt 1 view .LVU1085 +1355:Src/main.c **** LL_TIM_Init(TIM5, &TIM_InitStruct); + 3282 .loc 1 1355 32 is_stmt 0 view .LVU1086 + 3283 0054 0494 str r4, [sp, #16] + ARM GAS /tmp/ccWQNJQt.s page 265 + + +1356:Src/main.c **** LL_TIM_DisableARRPreload(TIM5); + 3284 .loc 1 1356 3 is_stmt 1 view .LVU1087 + 3285 0056 0E4C ldr r4, .L119+12 + 3286 0058 01A9 add r1, sp, #4 + 3287 005a 2046 mov r0, r4 + 3288 005c FFF7FEFF bl LL_TIM_Init + 3289 .LVL244: +1357:Src/main.c **** LL_TIM_SetClockSource(TIM5, LL_TIM_CLOCKSOURCE_INTERNAL); + 3290 .loc 1 1357 3 view .LVU1088 + 3291 .LBB406: + 3292 .LBI406: +1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 3293 .loc 5 1504 22 view .LVU1089 + 3294 .LBB407: +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 3295 .loc 5 1506 3 view .LVU1090 + 3296 0060 2368 ldr r3, [r4] + 3297 0062 23F08003 bic r3, r3, #128 + 3298 0066 2360 str r3, [r4] + 3299 .LVL245: +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 3300 .loc 5 1506 3 is_stmt 0 view .LVU1091 + 3301 .LBE407: + 3302 .LBE406: +1358:Src/main.c **** LL_TIM_SetTriggerOutput(TIM5, LL_TIM_TRGO_RESET); + 3303 .loc 1 1358 3 is_stmt 1 view .LVU1092 + 3304 .LBB408: + 3305 .LBI408: +3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 3306 .loc 5 3092 22 view .LVU1093 + 3307 .LBB409: +3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 3308 .loc 5 3094 3 view .LVU1094 + 3309 0068 A268 ldr r2, [r4, #8] + 3310 006a 0A4B ldr r3, .L119+16 + 3311 006c 1340 ands r3, r3, r2 + 3312 006e A360 str r3, [r4, #8] + 3313 .LVL246: +3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 3314 .loc 5 3094 3 is_stmt 0 view .LVU1095 + 3315 .LBE409: + 3316 .LBE408: +1359:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM5); + 3317 .loc 1 1359 3 is_stmt 1 view .LVU1096 + 3318 .LBB410: + 3319 .LBI410: +3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 3320 .loc 5 3138 22 view .LVU1097 + 3321 .LBB411: +3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 3322 .loc 5 3140 3 view .LVU1098 + 3323 0070 6368 ldr r3, [r4, #4] + 3324 0072 23F07003 bic r3, r3, #112 + 3325 0076 6360 str r3, [r4, #4] + 3326 .LVL247: +3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 3327 .loc 5 3140 3 is_stmt 0 view .LVU1099 + ARM GAS /tmp/ccWQNJQt.s page 266 + + + 3328 .LBE411: + 3329 .LBE410: +1360:Src/main.c **** /* USER CODE BEGIN TIM5_Init 2 */ + 3330 .loc 1 1360 3 is_stmt 1 view .LVU1100 + 3331 .LBB412: + 3332 .LBI412: +3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 3333 .loc 5 3235 22 view .LVU1101 + 3334 .LBB413: + 3335 .loc 5 3237 3 view .LVU1102 + 3336 0078 A368 ldr r3, [r4, #8] + 3337 007a 23F08003 bic r3, r3, #128 + 3338 007e A360 str r3, [r4, #8] + 3339 .LVL248: + 3340 .loc 5 3237 3 is_stmt 0 view .LVU1103 + 3341 .LBE413: + 3342 .LBE412: +1365:Src/main.c **** + 3343 .loc 1 1365 1 view .LVU1104 + 3344 0080 06B0 add sp, sp, #24 + 3345 .LCFI32: + 3346 .cfi_def_cfa_offset 8 + 3347 @ sp needed + 3348 0082 10BD pop {r4, pc} + 3349 .L120: + 3350 .align 2 + 3351 .L119: + 3352 0084 00380240 .word 1073887232 + 3353 0088 00ED00E0 .word -536810240 + 3354 008c 00E100E0 .word -536813312 + 3355 0090 000C0040 .word 1073744896 + 3356 0094 F8BFFEFF .word -81928 + 3357 .cfi_endproc + 3358 .LFE1197: + 3360 .section .text.MX_TIM7_Init,"ax",%progbits + 3361 .align 1 + 3362 .syntax unified + 3363 .thumb + 3364 .thumb_func + 3366 MX_TIM7_Init: + 3367 .LFB1199: +1410:Src/main.c **** + 3368 .loc 1 1410 1 is_stmt 1 view -0 + 3369 .cfi_startproc + 3370 @ args = 0, pretend = 0, frame = 24 + 3371 @ frame_needed = 0, uses_anonymous_args = 0 + 3372 0000 10B5 push {r4, lr} + 3373 .LCFI33: + 3374 .cfi_def_cfa_offset 8 + 3375 .cfi_offset 4, -8 + 3376 .cfi_offset 14, -4 + 3377 0002 86B0 sub sp, sp, #24 + 3378 .LCFI34: + 3379 .cfi_def_cfa_offset 32 +1416:Src/main.c **** + 3380 .loc 1 1416 3 view .LVU1106 +1416:Src/main.c **** + ARM GAS /tmp/ccWQNJQt.s page 267 + + + 3381 .loc 1 1416 22 is_stmt 0 view .LVU1107 + 3382 0004 0024 movs r4, #0 + 3383 0006 0194 str r4, [sp, #4] + 3384 0008 0294 str r4, [sp, #8] + 3385 000a 0394 str r4, [sp, #12] + 3386 000c 0494 str r4, [sp, #16] + 3387 000e 0594 str r4, [sp, #20] +1419:Src/main.c **** + 3388 .loc 1 1419 3 is_stmt 1 view .LVU1108 + 3389 .LVL249: + 3390 .LBB414: + 3391 .LBI414: +1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 3392 .loc 3 1071 22 view .LVU1109 + 3393 .LBB415: +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); + 3394 .loc 3 1073 3 view .LVU1110 +1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 3395 .loc 3 1074 3 view .LVU1111 + 3396 0010 1A4B ldr r3, .L123 + 3397 0012 1A6C ldr r2, [r3, #64] + 3398 0014 42F02002 orr r2, r2, #32 + 3399 0018 1A64 str r2, [r3, #64] +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 3400 .loc 3 1076 3 view .LVU1112 +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 3401 .loc 3 1076 12 is_stmt 0 view .LVU1113 + 3402 001a 1B6C ldr r3, [r3, #64] + 3403 001c 03F02003 and r3, r3, #32 +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 3404 .loc 3 1076 10 view .LVU1114 + 3405 0020 0093 str r3, [sp] +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 3406 .loc 3 1077 3 is_stmt 1 view .LVU1115 + 3407 0022 009B ldr r3, [sp] + 3408 .LVL250: +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 3409 .loc 3 1077 3 is_stmt 0 view .LVU1116 + 3410 .LBE415: + 3411 .LBE414: +1422:Src/main.c **** NVIC_EnableIRQ(TIM7_IRQn); + 3412 .loc 1 1422 3 is_stmt 1 view .LVU1117 + 3413 .LBB416: + 3414 .LBI416: +1884:Drivers/CMSIS/Include/core_cm7.h **** { + 3415 .loc 2 1884 26 view .LVU1118 + 3416 .LBB417: +1886:Drivers/CMSIS/Include/core_cm7.h **** } + 3417 .loc 2 1886 3 view .LVU1119 +1886:Drivers/CMSIS/Include/core_cm7.h **** } + 3418 .loc 2 1886 26 is_stmt 0 view .LVU1120 + 3419 0024 164B ldr r3, .L123+4 + 3420 0026 D868 ldr r0, [r3, #12] + 3421 .LBE417: + 3422 .LBE416: +1422:Src/main.c **** NVIC_EnableIRQ(TIM7_IRQn); + 3423 .loc 1 1422 3 discriminator 1 view .LVU1121 + ARM GAS /tmp/ccWQNJQt.s page 268 + + + 3424 0028 2246 mov r2, r4 + 3425 002a 2146 mov r1, r4 + 3426 002c C0F30220 ubfx r0, r0, #8, #3 + 3427 0030 FFF7FEFF bl NVIC_EncodePriority + 3428 .LVL251: + 3429 .LBB418: + 3430 .LBI418: +2024:Drivers/CMSIS/Include/core_cm7.h **** { + 3431 .loc 2 2024 22 is_stmt 1 view .LVU1122 + 3432 .LBB419: +2026:Drivers/CMSIS/Include/core_cm7.h **** { + 3433 .loc 2 2026 3 view .LVU1123 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 3434 .loc 2 2028 5 view .LVU1124 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 3435 .loc 2 2028 49 is_stmt 0 view .LVU1125 + 3436 0034 0001 lsls r0, r0, #4 + 3437 .LVL252: +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 3438 .loc 2 2028 49 view .LVU1126 + 3439 0036 C0B2 uxtb r0, r0 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 3440 .loc 2 2028 47 view .LVU1127 + 3441 0038 124B ldr r3, .L123+8 + 3442 003a 83F83703 strb r0, [r3, #823] + 3443 .LVL253: +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 3444 .loc 2 2028 47 view .LVU1128 + 3445 .LBE419: + 3446 .LBE418: +1423:Src/main.c **** + 3447 .loc 1 1423 3 is_stmt 1 view .LVU1129 + 3448 .LBB420: + 3449 .LBI420: +1896:Drivers/CMSIS/Include/core_cm7.h **** { + 3450 .loc 2 1896 22 view .LVU1130 + 3451 .LBB421: +1898:Drivers/CMSIS/Include/core_cm7.h **** { + 3452 .loc 2 1898 3 view .LVU1131 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 3453 .loc 2 1900 5 view .LVU1132 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 3454 .loc 2 1900 43 is_stmt 0 view .LVU1133 + 3455 003e 4FF40002 mov r2, #8388608 + 3456 0042 5A60 str r2, [r3, #4] + 3457 .LVL254: +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 3458 .loc 2 1900 43 view .LVU1134 + 3459 .LBE421: + 3460 .LBE420: +1428:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; + 3461 .loc 1 1428 3 is_stmt 1 view .LVU1135 +1428:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; + 3462 .loc 1 1428 28 is_stmt 0 view .LVU1136 + 3463 0044 40F29733 movw r3, #919 + 3464 0048 ADF80430 strh r3, [sp, #4] @ movhi +1429:Src/main.c **** TIM_InitStruct.Autoreload = 99; + ARM GAS /tmp/ccWQNJQt.s page 269 + + + 3465 .loc 1 1429 3 is_stmt 1 view .LVU1137 +1429:Src/main.c **** TIM_InitStruct.Autoreload = 99; + 3466 .loc 1 1429 30 is_stmt 0 view .LVU1138 + 3467 004c 0294 str r4, [sp, #8] +1430:Src/main.c **** LL_TIM_Init(TIM7, &TIM_InitStruct); + 3468 .loc 1 1430 3 is_stmt 1 view .LVU1139 +1430:Src/main.c **** LL_TIM_Init(TIM7, &TIM_InitStruct); + 3469 .loc 1 1430 29 is_stmt 0 view .LVU1140 + 3470 004e 6323 movs r3, #99 + 3471 0050 0393 str r3, [sp, #12] +1431:Src/main.c **** LL_TIM_DisableARRPreload(TIM7); + 3472 .loc 1 1431 3 is_stmt 1 view .LVU1141 + 3473 0052 0D4C ldr r4, .L123+12 + 3474 0054 01A9 add r1, sp, #4 + 3475 0056 2046 mov r0, r4 + 3476 0058 FFF7FEFF bl LL_TIM_Init + 3477 .LVL255: +1432:Src/main.c **** LL_TIM_SetTriggerOutput(TIM7, LL_TIM_TRGO_ENABLE); + 3478 .loc 1 1432 3 view .LVU1142 + 3479 .LBB422: + 3480 .LBI422: +1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 3481 .loc 5 1504 22 view .LVU1143 + 3482 .LBB423: +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 3483 .loc 5 1506 3 view .LVU1144 + 3484 005c 2368 ldr r3, [r4] + 3485 005e 23F08003 bic r3, r3, #128 + 3486 0062 2360 str r3, [r4] + 3487 .LVL256: +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 3488 .loc 5 1506 3 is_stmt 0 view .LVU1145 + 3489 .LBE423: + 3490 .LBE422: +1433:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM7); + 3491 .loc 1 1433 3 is_stmt 1 view .LVU1146 + 3492 .LBB424: + 3493 .LBI424: +3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 3494 .loc 5 3138 22 view .LVU1147 + 3495 .LBB425: +3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 3496 .loc 5 3140 3 view .LVU1148 + 3497 0064 6368 ldr r3, [r4, #4] + 3498 0066 23F07003 bic r3, r3, #112 + 3499 006a 43F01003 orr r3, r3, #16 + 3500 006e 6360 str r3, [r4, #4] + 3501 .LVL257: +3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 3502 .loc 5 3140 3 is_stmt 0 view .LVU1149 + 3503 .LBE425: + 3504 .LBE424: +1434:Src/main.c **** /* USER CODE BEGIN TIM7_Init 2 */ + 3505 .loc 1 1434 3 is_stmt 1 view .LVU1150 + 3506 .LBB426: + 3507 .LBI426: +3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + ARM GAS /tmp/ccWQNJQt.s page 270 + + + 3508 .loc 5 3235 22 view .LVU1151 + 3509 .LBB427: + 3510 .loc 5 3237 3 view .LVU1152 + 3511 0070 A368 ldr r3, [r4, #8] + 3512 0072 23F08003 bic r3, r3, #128 + 3513 0076 A360 str r3, [r4, #8] + 3514 .LVL258: + 3515 .loc 5 3237 3 is_stmt 0 view .LVU1153 + 3516 .LBE427: + 3517 .LBE426: +1439:Src/main.c **** + 3518 .loc 1 1439 1 view .LVU1154 + 3519 0078 06B0 add sp, sp, #24 + 3520 .LCFI35: + 3521 .cfi_def_cfa_offset 8 + 3522 @ sp needed + 3523 007a 10BD pop {r4, pc} + 3524 .L124: + 3525 .align 2 + 3526 .L123: + 3527 007c 00380240 .word 1073887232 + 3528 0080 00ED00E0 .word -536810240 + 3529 0084 00E100E0 .word -536813312 + 3530 0088 00140040 .word 1073746944 + 3531 .cfi_endproc + 3532 .LFE1199: + 3534 .section .text.MX_TIM6_Init,"ax",%progbits + 3535 .align 1 + 3536 .syntax unified + 3537 .thumb + 3538 .thumb_func + 3540 MX_TIM6_Init: + 3541 .LFB1198: +1373:Src/main.c **** + 3542 .loc 1 1373 1 is_stmt 1 view -0 + 3543 .cfi_startproc + 3544 @ args = 0, pretend = 0, frame = 24 + 3545 @ frame_needed = 0, uses_anonymous_args = 0 + 3546 0000 10B5 push {r4, lr} + 3547 .LCFI36: + 3548 .cfi_def_cfa_offset 8 + 3549 .cfi_offset 4, -8 + 3550 .cfi_offset 14, -4 + 3551 0002 86B0 sub sp, sp, #24 + 3552 .LCFI37: + 3553 .cfi_def_cfa_offset 32 +1379:Src/main.c **** + 3554 .loc 1 1379 3 view .LVU1156 +1379:Src/main.c **** + 3555 .loc 1 1379 22 is_stmt 0 view .LVU1157 + 3556 0004 0024 movs r4, #0 + 3557 0006 0194 str r4, [sp, #4] + 3558 0008 0294 str r4, [sp, #8] + 3559 000a 0394 str r4, [sp, #12] + 3560 000c 0494 str r4, [sp, #16] + 3561 000e 0594 str r4, [sp, #20] +1382:Src/main.c **** + ARM GAS /tmp/ccWQNJQt.s page 271 + + + 3562 .loc 1 1382 3 is_stmt 1 view .LVU1158 + 3563 .LVL259: + 3564 .LBB428: + 3565 .LBI428: +1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 3566 .loc 3 1071 22 view .LVU1159 + 3567 .LBB429: +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); + 3568 .loc 3 1073 3 view .LVU1160 +1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 3569 .loc 3 1074 3 view .LVU1161 + 3570 0010 1A4B ldr r3, .L127 + 3571 0012 1A6C ldr r2, [r3, #64] + 3572 0014 42F01002 orr r2, r2, #16 + 3573 0018 1A64 str r2, [r3, #64] +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 3574 .loc 3 1076 3 view .LVU1162 +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 3575 .loc 3 1076 12 is_stmt 0 view .LVU1163 + 3576 001a 1B6C ldr r3, [r3, #64] + 3577 001c 03F01003 and r3, r3, #16 +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 3578 .loc 3 1076 10 view .LVU1164 + 3579 0020 0093 str r3, [sp] +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 3580 .loc 3 1077 3 is_stmt 1 view .LVU1165 + 3581 0022 009B ldr r3, [sp] + 3582 .LVL260: +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 3583 .loc 3 1077 3 is_stmt 0 view .LVU1166 + 3584 .LBE429: + 3585 .LBE428: +1385:Src/main.c **** NVIC_EnableIRQ(TIM6_DAC_IRQn); + 3586 .loc 1 1385 3 is_stmt 1 view .LVU1167 + 3587 .LBB430: + 3588 .LBI430: +1884:Drivers/CMSIS/Include/core_cm7.h **** { + 3589 .loc 2 1884 26 view .LVU1168 + 3590 .LBB431: +1886:Drivers/CMSIS/Include/core_cm7.h **** } + 3591 .loc 2 1886 3 view .LVU1169 +1886:Drivers/CMSIS/Include/core_cm7.h **** } + 3592 .loc 2 1886 26 is_stmt 0 view .LVU1170 + 3593 0024 164B ldr r3, .L127+4 + 3594 0026 D868 ldr r0, [r3, #12] + 3595 .LBE431: + 3596 .LBE430: +1385:Src/main.c **** NVIC_EnableIRQ(TIM6_DAC_IRQn); + 3597 .loc 1 1385 3 discriminator 1 view .LVU1171 + 3598 0028 2246 mov r2, r4 + 3599 002a 2146 mov r1, r4 + 3600 002c C0F30220 ubfx r0, r0, #8, #3 + 3601 0030 FFF7FEFF bl NVIC_EncodePriority + 3602 .LVL261: + 3603 .LBB432: + 3604 .LBI432: +2024:Drivers/CMSIS/Include/core_cm7.h **** { + ARM GAS /tmp/ccWQNJQt.s page 272 + + + 3605 .loc 2 2024 22 is_stmt 1 view .LVU1172 + 3606 .LBB433: +2026:Drivers/CMSIS/Include/core_cm7.h **** { + 3607 .loc 2 2026 3 view .LVU1173 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 3608 .loc 2 2028 5 view .LVU1174 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 3609 .loc 2 2028 49 is_stmt 0 view .LVU1175 + 3610 0034 0001 lsls r0, r0, #4 + 3611 .LVL262: +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 3612 .loc 2 2028 49 view .LVU1176 + 3613 0036 C0B2 uxtb r0, r0 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 3614 .loc 2 2028 47 view .LVU1177 + 3615 0038 124B ldr r3, .L127+8 + 3616 003a 83F83603 strb r0, [r3, #822] + 3617 .LVL263: +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 3618 .loc 2 2028 47 view .LVU1178 + 3619 .LBE433: + 3620 .LBE432: +1386:Src/main.c **** + 3621 .loc 1 1386 3 is_stmt 1 view .LVU1179 + 3622 .LBB434: + 3623 .LBI434: +1896:Drivers/CMSIS/Include/core_cm7.h **** { + 3624 .loc 2 1896 22 view .LVU1180 + 3625 .LBB435: +1898:Drivers/CMSIS/Include/core_cm7.h **** { + 3626 .loc 2 1898 3 view .LVU1181 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 3627 .loc 2 1900 5 view .LVU1182 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 3628 .loc 2 1900 43 is_stmt 0 view .LVU1183 + 3629 003e 4FF48002 mov r2, #4194304 + 3630 0042 5A60 str r2, [r3, #4] + 3631 .LVL264: +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 3632 .loc 2 1900 43 view .LVU1184 + 3633 .LBE435: + 3634 .LBE434: +1391:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; + 3635 .loc 1 1391 3 is_stmt 1 view .LVU1185 +1391:Src/main.c **** TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; + 3636 .loc 1 1391 28 is_stmt 0 view .LVU1186 + 3637 0044 4BF2AF33 movw r3, #45999 + 3638 0048 ADF80430 strh r3, [sp, #4] @ movhi +1392:Src/main.c **** TIM_InitStruct.Autoreload = 19; + 3639 .loc 1 1392 3 is_stmt 1 view .LVU1187 +1392:Src/main.c **** TIM_InitStruct.Autoreload = 19; + 3640 .loc 1 1392 30 is_stmt 0 view .LVU1188 + 3641 004c 0294 str r4, [sp, #8] +1393:Src/main.c **** LL_TIM_Init(TIM6, &TIM_InitStruct); + 3642 .loc 1 1393 3 is_stmt 1 view .LVU1189 +1393:Src/main.c **** LL_TIM_Init(TIM6, &TIM_InitStruct); + 3643 .loc 1 1393 29 is_stmt 0 view .LVU1190 + ARM GAS /tmp/ccWQNJQt.s page 273 + + + 3644 004e 1323 movs r3, #19 + 3645 0050 0393 str r3, [sp, #12] +1394:Src/main.c **** LL_TIM_DisableARRPreload(TIM6); + 3646 .loc 1 1394 3 is_stmt 1 view .LVU1191 + 3647 0052 0D4C ldr r4, .L127+12 + 3648 0054 01A9 add r1, sp, #4 + 3649 0056 2046 mov r0, r4 + 3650 0058 FFF7FEFF bl LL_TIM_Init + 3651 .LVL265: +1395:Src/main.c **** LL_TIM_SetTriggerOutput(TIM6, LL_TIM_TRGO_ENABLE); + 3652 .loc 1 1395 3 view .LVU1192 + 3653 .LBB436: + 3654 .LBI436: +1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 3655 .loc 5 1504 22 view .LVU1193 + 3656 .LBB437: +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 3657 .loc 5 1506 3 view .LVU1194 + 3658 005c 2368 ldr r3, [r4] + 3659 005e 23F08003 bic r3, r3, #128 + 3660 0062 2360 str r3, [r4] + 3661 .LVL266: +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 3662 .loc 5 1506 3 is_stmt 0 view .LVU1195 + 3663 .LBE437: + 3664 .LBE436: +1396:Src/main.c **** LL_TIM_DisableMasterSlaveMode(TIM6); + 3665 .loc 1 1396 3 is_stmt 1 view .LVU1196 + 3666 .LBB438: + 3667 .LBI438: +3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 3668 .loc 5 3138 22 view .LVU1197 + 3669 .LBB439: +3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 3670 .loc 5 3140 3 view .LVU1198 + 3671 0064 6368 ldr r3, [r4, #4] + 3672 0066 23F07003 bic r3, r3, #112 + 3673 006a 43F01003 orr r3, r3, #16 + 3674 006e 6360 str r3, [r4, #4] + 3675 .LVL267: +3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 3676 .loc 5 3140 3 is_stmt 0 view .LVU1199 + 3677 .LBE439: + 3678 .LBE438: +1397:Src/main.c **** /* USER CODE BEGIN TIM6_Init 2 */ + 3679 .loc 1 1397 3 is_stmt 1 view .LVU1200 + 3680 .LBB440: + 3681 .LBI440: +3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 3682 .loc 5 3235 22 view .LVU1201 + 3683 .LBB441: + 3684 .loc 5 3237 3 view .LVU1202 + 3685 0070 A368 ldr r3, [r4, #8] + 3686 0072 23F08003 bic r3, r3, #128 + 3687 0076 A360 str r3, [r4, #8] + 3688 .LVL268: + 3689 .loc 5 3237 3 is_stmt 0 view .LVU1203 + ARM GAS /tmp/ccWQNJQt.s page 274 + + + 3690 .LBE441: + 3691 .LBE440: +1402:Src/main.c **** + 3692 .loc 1 1402 1 view .LVU1204 + 3693 0078 06B0 add sp, sp, #24 + 3694 .LCFI38: + 3695 .cfi_def_cfa_offset 8 + 3696 @ sp needed + 3697 007a 10BD pop {r4, pc} + 3698 .L128: + 3699 .align 2 + 3700 .L127: + 3701 007c 00380240 .word 1073887232 + 3702 0080 00ED00E0 .word -536810240 + 3703 0084 00E100E0 .word -536813312 + 3704 0088 00100040 .word 1073745920 + 3705 .cfi_endproc + 3706 .LFE1198: + 3708 .section .rodata.Init_params.str1.4,"aMS",%progbits,1 + 3709 .align 2 + 3710 .LC0: + 3711 0000 2F00 .ascii "/\000" + 3712 0002 0000 .align 2 + 3713 .LC1: + 3714 0004 434F4D4D .ascii "COMMAND.TXT\000" + 3714 414E442E + 3714 54585400 + 3715 .section .text.Init_params,"ax",%progbits + 3716 .align 1 + 3717 .syntax unified + 3718 .thumb + 3719 .thumb_func + 3721 Init_params: + 3722 .LFB1207: +1870:Src/main.c **** TO6 = 0; + 3723 .loc 1 1870 1 is_stmt 1 view -0 + 3724 .cfi_startproc + 3725 @ args = 0, pretend = 0, frame = 0 + 3726 @ frame_needed = 0, uses_anonymous_args = 0 + 3727 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 3728 .LCFI39: + 3729 .cfi_def_cfa_offset 24 + 3730 .cfi_offset 4, -24 + 3731 .cfi_offset 5, -20 + 3732 .cfi_offset 6, -16 + 3733 .cfi_offset 7, -12 + 3734 .cfi_offset 8, -8 + 3735 .cfi_offset 14, -4 +1871:Src/main.c **** TO7 = 0; + 3736 .loc 1 1871 2 view .LVU1206 +1871:Src/main.c **** TO7 = 0; + 3737 .loc 1 1871 6 is_stmt 0 view .LVU1207 + 3738 0004 0023 movs r3, #0 + 3739 0006 9E4A ldr r2, .L141 + 3740 0008 1360 str r3, [r2] +1872:Src/main.c **** TO7_before = 0; + 3741 .loc 1 1872 2 is_stmt 1 view .LVU1208 + ARM GAS /tmp/ccWQNJQt.s page 275 + + +1872:Src/main.c **** TO7_before = 0; + 3742 .loc 1 1872 6 is_stmt 0 view .LVU1209 + 3743 000a 9E4A ldr r2, .L141+4 + 3744 000c 1360 str r3, [r2] +1873:Src/main.c **** TO6_before = 0; + 3745 .loc 1 1873 2 is_stmt 1 view .LVU1210 +1873:Src/main.c **** TO6_before = 0; + 3746 .loc 1 1873 13 is_stmt 0 view .LVU1211 + 3747 000e 9E4A ldr r2, .L141+8 + 3748 0010 1360 str r3, [r2] +1874:Src/main.c **** TO6_uart = 0; + 3749 .loc 1 1874 2 is_stmt 1 view .LVU1212 +1874:Src/main.c **** TO6_uart = 0; + 3750 .loc 1 1874 13 is_stmt 0 view .LVU1213 + 3751 0012 9E4A ldr r2, .L141+12 + 3752 0014 1360 str r3, [r2] +1875:Src/main.c **** flg_tmt = 0; + 3753 .loc 1 1875 2 is_stmt 1 view .LVU1214 +1875:Src/main.c **** flg_tmt = 0; + 3754 .loc 1 1875 11 is_stmt 0 view .LVU1215 + 3755 0016 9E4A ldr r2, .L141+16 + 3756 0018 1360 str r3, [r2] +1876:Src/main.c **** UART_rec_incr = 0; + 3757 .loc 1 1876 2 is_stmt 1 view .LVU1216 +1876:Src/main.c **** UART_rec_incr = 0; + 3758 .loc 1 1876 10 is_stmt 0 view .LVU1217 + 3759 001a 9E4A ldr r2, .L141+20 + 3760 001c 1370 strb r3, [r2] +1877:Src/main.c **** fgoto = 0; + 3761 .loc 1 1877 2 is_stmt 1 view .LVU1218 +1877:Src/main.c **** fgoto = 0; + 3762 .loc 1 1877 16 is_stmt 0 view .LVU1219 + 3763 001e 9E4A ldr r2, .L141+24 + 3764 0020 1380 strh r3, [r2] @ movhi +1878:Src/main.c **** sizeoffile = 0; + 3765 .loc 1 1878 2 is_stmt 1 view .LVU1220 +1878:Src/main.c **** sizeoffile = 0; + 3766 .loc 1 1878 8 is_stmt 0 view .LVU1221 + 3767 0022 9E4A ldr r2, .L141+28 + 3768 0024 1360 str r3, [r2] +1879:Src/main.c **** u_tx_flg = 0; + 3769 .loc 1 1879 2 is_stmt 1 view .LVU1222 +1879:Src/main.c **** u_tx_flg = 0; + 3770 .loc 1 1879 13 is_stmt 0 view .LVU1223 + 3771 0026 9E4A ldr r2, .L141+32 + 3772 0028 1360 str r3, [r2] +1880:Src/main.c **** u_rx_flg = 0; + 3773 .loc 1 1880 2 is_stmt 1 view .LVU1224 +1880:Src/main.c **** u_rx_flg = 0; + 3774 .loc 1 1880 11 is_stmt 0 view .LVU1225 + 3775 002a 9E4A ldr r2, .L141+36 + 3776 002c 1370 strb r3, [r2] +1881:Src/main.c **** //State_Data[0]=0; + 3777 .loc 1 1881 2 is_stmt 1 view .LVU1226 +1881:Src/main.c **** //State_Data[0]=0; + 3778 .loc 1 1881 11 is_stmt 0 view .LVU1227 + 3779 002e 9E4A ldr r2, .L141+40 + ARM GAS /tmp/ccWQNJQt.s page 276 + + + 3780 0030 1370 strb r3, [r2] +1884:Src/main.c **** { + 3781 .loc 1 1884 2 is_stmt 1 view .LVU1228 + 3782 .LBB442: +1884:Src/main.c **** { + 3783 .loc 1 1884 7 view .LVU1229 + 3784 .LVL269: +1884:Src/main.c **** { + 3785 .loc 1 1884 2 is_stmt 0 view .LVU1230 + 3786 0032 05E0 b .L130 + 3787 .LVL270: + 3788 .L131: +1886:Src/main.c **** } + 3789 .loc 1 1886 3 is_stmt 1 view .LVU1231 +1886:Src/main.c **** } + 3790 .loc 1 1886 16 is_stmt 0 view .LVU1232 + 3791 0034 9D4A ldr r2, .L141+44 + 3792 0036 0021 movs r1, #0 + 3793 0038 22F81310 strh r1, [r2, r3, lsl #1] @ movhi +1884:Src/main.c **** { + 3794 .loc 1 1884 31 is_stmt 1 discriminator 3 view .LVU1233 + 3795 003c 0133 adds r3, r3, #1 + 3796 .LVL271: +1884:Src/main.c **** { + 3797 .loc 1 1884 31 is_stmt 0 discriminator 3 view .LVU1234 + 3798 003e 9BB2 uxth r3, r3 + 3799 .LVL272: + 3800 .L130: +1884:Src/main.c **** { + 3801 .loc 1 1884 22 is_stmt 1 discriminator 1 view .LVU1235 + 3802 0040 0E2B cmp r3, #14 + 3803 0042 F7D9 bls .L131 + 3804 .LBE442: +1888:Src/main.c **** + 3805 .loc 1 1888 2 view .LVU1236 +1888:Src/main.c **** + 3806 .loc 1 1888 14 is_stmt 0 view .LVU1237 + 3807 0044 994B ldr r3, .L141+44 + 3808 .LVL273: +1888:Src/main.c **** + 3809 .loc 1 1888 14 view .LVU1238 + 3810 0046 41F21112 movw r2, #4369 + 3811 004a 1A80 strh r2, [r3] @ movhi +1891:Src/main.c **** Def_setup.LD1_EN = 0; + 3812 .loc 1 1891 2 is_stmt 1 view .LVU1239 +1891:Src/main.c **** Def_setup.LD1_EN = 0; + 3813 .loc 1 1891 21 is_stmt 0 view .LVU1240 + 3814 004c 984B ldr r3, .L141+48 + 3815 004e 0022 movs r2, #0 + 3816 0050 DA81 strh r2, [r3, #14] @ movhi +1892:Src/main.c **** Def_setup.LD2_EN = 0; + 3817 .loc 1 1892 2 is_stmt 1 view .LVU1241 +1892:Src/main.c **** Def_setup.LD2_EN = 0; + 3818 .loc 1 1892 19 is_stmt 0 view .LVU1242 + 3819 0052 DA70 strb r2, [r3, #3] +1893:Src/main.c **** Def_setup.MES_ID = 0; + 3820 .loc 1 1893 2 is_stmt 1 view .LVU1243 + ARM GAS /tmp/ccWQNJQt.s page 277 + + +1893:Src/main.c **** Def_setup.MES_ID = 0; + 3821 .loc 1 1893 19 is_stmt 0 view .LVU1244 + 3822 0054 1A71 strb r2, [r3, #4] +1894:Src/main.c **** Def_setup.PI1_RD = 0; + 3823 .loc 1 1894 2 is_stmt 1 view .LVU1245 +1894:Src/main.c **** Def_setup.PI1_RD = 0; + 3824 .loc 1 1894 19 is_stmt 0 view .LVU1246 + 3825 0056 1A82 strh r2, [r3, #16] @ movhi +1895:Src/main.c **** Def_setup.PI2_RD = 0; + 3826 .loc 1 1895 2 is_stmt 1 view .LVU1247 +1895:Src/main.c **** Def_setup.PI2_RD = 0; + 3827 .loc 1 1895 19 is_stmt 0 view .LVU1248 + 3828 0058 1A73 strb r2, [r3, #12] +1896:Src/main.c **** Def_setup.REF1_EN = 0; + 3829 .loc 1 1896 2 is_stmt 1 view .LVU1249 +1896:Src/main.c **** Def_setup.REF1_EN = 0; + 3830 .loc 1 1896 19 is_stmt 0 view .LVU1250 + 3831 005a 5A73 strb r2, [r3, #13] +1897:Src/main.c **** Def_setup.REF2_EN = 0; + 3832 .loc 1 1897 2 is_stmt 1 view .LVU1251 +1897:Src/main.c **** Def_setup.REF2_EN = 0; + 3833 .loc 1 1897 20 is_stmt 0 view .LVU1252 + 3834 005c 5A71 strb r2, [r3, #5] +1898:Src/main.c **** Def_setup.SD_EN = 0; + 3835 .loc 1 1898 2 is_stmt 1 view .LVU1253 +1898:Src/main.c **** Def_setup.SD_EN = 0; + 3836 .loc 1 1898 20 is_stmt 0 view .LVU1254 + 3837 005e 9A71 strb r2, [r3, #6] +1899:Src/main.c **** Def_setup.TEC1_EN = 0; + 3838 .loc 1 1899 2 is_stmt 1 view .LVU1255 +1899:Src/main.c **** Def_setup.TEC1_EN = 0; + 3839 .loc 1 1899 18 is_stmt 0 view .LVU1256 + 3840 0060 DA72 strb r2, [r3, #11] +1900:Src/main.c **** Def_setup.TEC2_EN = 0; + 3841 .loc 1 1900 2 is_stmt 1 view .LVU1257 +1900:Src/main.c **** Def_setup.TEC2_EN = 0; + 3842 .loc 1 1900 20 is_stmt 0 view .LVU1258 + 3843 0062 DA71 strb r2, [r3, #7] +1901:Src/main.c **** Def_setup.TS1_EN = 0; + 3844 .loc 1 1901 2 is_stmt 1 view .LVU1259 +1901:Src/main.c **** Def_setup.TS1_EN = 0; + 3845 .loc 1 1901 20 is_stmt 0 view .LVU1260 + 3846 0064 1A72 strb r2, [r3, #8] +1902:Src/main.c **** Def_setup.TS2_EN = 0; + 3847 .loc 1 1902 2 is_stmt 1 view .LVU1261 +1902:Src/main.c **** Def_setup.TS2_EN = 0; + 3848 .loc 1 1902 19 is_stmt 0 view .LVU1262 + 3849 0066 5A72 strb r2, [r3, #9] +1903:Src/main.c **** Def_setup.U5V1_EN = 0; + 3850 .loc 1 1903 2 is_stmt 1 view .LVU1263 +1903:Src/main.c **** Def_setup.U5V1_EN = 0; + 3851 .loc 1 1903 19 is_stmt 0 view .LVU1264 + 3852 0068 9A72 strb r2, [r3, #10] +1904:Src/main.c **** Def_setup.U5V2_EN = 0; + 3853 .loc 1 1904 2 is_stmt 1 view .LVU1265 +1904:Src/main.c **** Def_setup.U5V2_EN = 0; + 3854 .loc 1 1904 20 is_stmt 0 view .LVU1266 + ARM GAS /tmp/ccWQNJQt.s page 278 + + + 3855 006a 5A70 strb r2, [r3, #1] +1905:Src/main.c **** Def_setup.WORK_EN = 0; + 3856 .loc 1 1905 2 is_stmt 1 view .LVU1267 +1905:Src/main.c **** Def_setup.WORK_EN = 0; + 3857 .loc 1 1905 20 is_stmt 0 view .LVU1268 + 3858 006c 9A70 strb r2, [r3, #2] +1906:Src/main.c **** + 3859 .loc 1 1906 2 is_stmt 1 view .LVU1269 +1906:Src/main.c **** + 3860 .loc 1 1906 20 is_stmt 0 view .LVU1270 + 3861 006e 1A70 strb r2, [r3] +1908:Src/main.c **** LD2_def_setup.LD_TEMP = 0; + 3862 .loc 1 1908 2 is_stmt 1 view .LVU1271 +1908:Src/main.c **** LD2_def_setup.LD_TEMP = 0; + 3863 .loc 1 1908 24 is_stmt 0 view .LVU1272 + 3864 0070 904D ldr r5, .L141+52 + 3865 0072 2A80 strh r2, [r5] @ movhi +1909:Src/main.c **** LD1_def_setup.P_coef_temp = 0; + 3866 .loc 1 1909 2 is_stmt 1 view .LVU1273 +1909:Src/main.c **** LD1_def_setup.P_coef_temp = 0; + 3867 .loc 1 1909 24 is_stmt 0 view .LVU1274 + 3868 0074 904C ldr r4, .L141+56 + 3869 0076 2280 strh r2, [r4] @ movhi +1910:Src/main.c **** LD2_def_setup.P_coef_temp = 0; + 3870 .loc 1 1910 2 is_stmt 1 view .LVU1275 +1910:Src/main.c **** LD2_def_setup.P_coef_temp = 0; + 3871 .loc 1 1910 28 is_stmt 0 view .LVU1276 + 3872 0078 0022 movs r2, #0 + 3873 007a 6A60 str r2, [r5, #4] @ float +1911:Src/main.c **** LD1_def_setup.I_coef_temp = 0; + 3874 .loc 1 1911 2 is_stmt 1 view .LVU1277 +1911:Src/main.c **** LD1_def_setup.I_coef_temp = 0; + 3875 .loc 1 1911 28 is_stmt 0 view .LVU1278 + 3876 007c 6260 str r2, [r4, #4] @ float +1912:Src/main.c **** LD2_def_setup.I_coef_temp = 0; + 3877 .loc 1 1912 2 is_stmt 1 view .LVU1279 +1912:Src/main.c **** LD2_def_setup.I_coef_temp = 0; + 3878 .loc 1 1912 28 is_stmt 0 view .LVU1280 + 3879 007e AA60 str r2, [r5, #8] @ float +1913:Src/main.c **** + 3880 .loc 1 1913 2 is_stmt 1 view .LVU1281 +1913:Src/main.c **** + 3881 .loc 1 1913 28 is_stmt 0 view .LVU1282 + 3882 0080 A260 str r2, [r4, #8] @ float +1916:Src/main.c **** LD1_curr_setup = LD1_def_setup; + 3883 .loc 1 1916 2 is_stmt 1 view .LVU1283 +1916:Src/main.c **** LD1_curr_setup = LD1_def_setup; + 3884 .loc 1 1916 13 is_stmt 0 view .LVU1284 + 3885 0082 8E4E ldr r6, .L141+60 + 3886 0084 9C46 mov ip, r3 + 3887 0086 BCE80F00 ldmia ip!, {r0, r1, r2, r3} + 3888 008a 0FC6 stmia r6!, {r0, r1, r2, r3} + 3889 008c DCF80030 ldr r3, [ip] + 3890 0090 3380 strh r3, [r6] @ movhi +1917:Src/main.c **** LD2_curr_setup = LD2_def_setup; + 3891 .loc 1 1917 2 is_stmt 1 view .LVU1285 +1917:Src/main.c **** LD2_curr_setup = LD2_def_setup; + ARM GAS /tmp/ccWQNJQt.s page 279 + + + 3892 .loc 1 1917 17 is_stmt 0 view .LVU1286 + 3893 0092 8B4E ldr r6, .L141+64 + 3894 0094 95E80F00 ldm r5, {r0, r1, r2, r3} + 3895 0098 86E80F00 stm r6, {r0, r1, r2, r3} +1918:Src/main.c **** + 3896 .loc 1 1918 2 is_stmt 1 view .LVU1287 +1918:Src/main.c **** + 3897 .loc 1 1918 17 is_stmt 0 view .LVU1288 + 3898 009c 894D ldr r5, .L141+68 + 3899 009e 94E80F00 ldm r4, {r0, r1, r2, r3} + 3900 00a2 85E80F00 stm r5, {r0, r1, r2, r3} +1923:Src/main.c **** LL_TIM_EnableCounter(TIM6); + 3901 .loc 1 1923 2 is_stmt 1 view .LVU1289 + 3902 .LVL274: + 3903 .LBB443: + 3904 .LBI443: +3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the Master/Slave mode is enabled. +3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. +3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode +3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) +3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); +3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the external trigger (ETR) input. +3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not +3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an external trigger input. +3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ETP LL_TIM_ConfigETR\n +3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ETPS LL_TIM_ConfigETR\n +3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ETF LL_TIM_ConfigETR +3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRPolarity This parameter can be one of the following values: +3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED +3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_POLARITY_INVERTED +3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRPrescaler This parameter can be one of the following values: +3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 +3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 +3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 +3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 +3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRFilter This parameter can be one of the following values: +3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1 +3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 +3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 +3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 +3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 +3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 +3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 +3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 +3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 + ARM GAS /tmp/ccWQNJQt.s page 280 + + +3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 +3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 +3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 +3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 +3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 +3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 +3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 +3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescale +3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ETRFilter) +3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | +3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Break_Function Break function configuration +3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the break function. +3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKE LL_TIM_EnableBRK +3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) +3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); +3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the break function. +3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKE LL_TIM_DisableBRK +3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) +3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); +3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the break input. +3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n +3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR BKF LL_TIM_ConfigBRK +3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakPolarity This parameter can be one of the following values: +3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_POLARITY_LOW + ARM GAS /tmp/ccWQNJQt.s page 281 + + +3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_POLARITY_HIGH +3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakFilter This parameter can be one of the following values: +3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 +3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 +3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 +3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 +3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 +3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 +3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 +3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 +3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 +3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 +3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 +3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 +3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 +3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 +3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 +3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 +3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, +3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakFilter) +3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); +3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the break 2 function. +3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not +3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. +3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 +3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) +3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the break 2 function. +3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not +3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. +3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 +3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) +3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the break 2 input. +3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not +3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. +3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n + ARM GAS /tmp/ccWQNJQt.s page 282 + + +3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR BK2F LL_TIM_ConfigBRK2 +3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Break2Polarity This parameter can be one of the following values: +3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_POLARITY_LOW +3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH +3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Break2Filter This parameter can be one of the following values: +3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 +3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 +3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 +3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 +3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 +3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 +3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 +3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 +3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 +3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 +3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 +3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 +3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 +3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 +3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 +3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 +3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2F +3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); +3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. +3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n +3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR OSSR LL_TIM_SetOffStates +3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OffStateIdle This parameter can be one of the following values: +3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSI_DISABLE +3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSI_ENABLE +3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OffStateRun This parameter can be one of the following values: +3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSR_DISABLE +3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSR_ENABLE +3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStat +3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); +3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable automatic output (MOE can be set by software or automatically when a break input +3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput +3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + ARM GAS /tmp/ccWQNJQt.s page 283 + + +3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) +3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); +3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable automatic output (MOE can be set only by software). +3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput +3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) +3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); +3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether automatic output is enabled. +3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput +3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) +3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); +3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). +3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by +3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * software and is reset in case of break or break2 event +3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs +3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) +3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); +3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). +3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by +3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * software and is reset in case of break or break2 event. +3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs +3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) + ARM GAS /tmp/ccWQNJQt.s page 284 + + +3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); +3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether outputs are enabled. +3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs +3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) +3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); +3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(TIM_BREAK_INPUT_SUPPORT) +3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the signals connected to the designated timer break input. +3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether +3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. +3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n +3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKE LL_TIM_EnableBreakInputSource\n +3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INE LL_TIM_EnableBreakInputSource\n +3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKE LL_TIM_EnableBreakInputSource +3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: +3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN +3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 +3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: +3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN +3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK +3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t +3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); +3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, Source); +3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the signals connected to the designated timer break input. +3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether +3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. +3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n +3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKE LL_TIM_DisableBreakInputSource\n +3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INE LL_TIM_DisableBreakInputSource\n +3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKE LL_TIM_DisableBreakInputSource +3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: +3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN +3559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 +3560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: +3561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN +3562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK +3563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None + ARM GAS /tmp/ccWQNJQt.s page 285 + + +3564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_ +3566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); +3568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, Source); +3569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the polarity of the break signal for the timer break input. +3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether +3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. +3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n +3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKP LL_TIM_SetBreakInputSourcePolarity\n +3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n +3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKP LL_TIM_SetBreakInputSourcePolarity +3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: +3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN +3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 +3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: +3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN +3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK +3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Polarity This parameter can be one of the following values: +3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_POLARITY_LOW +3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_POLARITY_HIGH +3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uin +3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Polarity) +3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); +3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOUR +3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */ +3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configures the timer DMA burst feature. +3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or +3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * not a timer instance supports the DMA burst mode. +3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n +3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * DCR DBA LL_TIM_ConfigDMABurst +3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMABurstBaseAddress This parameter can be one of the following values: +3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 +3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 +3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR +3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER +3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_SR +3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR +3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 +3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 + ARM GAS /tmp/ccWQNJQt.s page 286 + + +3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER +3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT +3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC +3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR +3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR +3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 +3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 +3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 +3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 +3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR +3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_OR +3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 +3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 +3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 +3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 (*) +3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 (*) +3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (*) value not defined in all devices +3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMABurstLength This parameter can be one of the following values: +3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER +3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS +3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS +3642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS +3643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS +3644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS +3645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS +3646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS +3647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS +3648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS +3649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS +3650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS +3651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS +3652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS +3653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS +3654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS +3655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS +3656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS +3657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_ +3660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); +3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping +3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Remap TIM inputs (input channel, internal/external triggers). +3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not +3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a some timer inputs can be remapped. +3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n +3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM5_OR TI4_RMP LL_TIM_SetRemap\n +3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM11_OR TI1_RMP LL_TIM_SetRemap + ARM GAS /tmp/ccWQNJQt.s page 287 + + +3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Remap Remap param depends on the TIMx. Description available only +3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in CHM version of the User Manual (not in .pdf). +3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Otherwise see Reference Manual description of OR registers. +3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Below description summarizes "Timer Instance" and "Remap" param combinations: +3684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM2: one of the following values +3686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * ITR1_RMP can be one of the following values +3688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO +3689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP +3690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF +3691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF +3692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM5: one of the following values +3694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO +3696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI +3697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE +3698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC +3699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM11: one of the following values +3701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO +3703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX +3704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE +3705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_MCO1 +3706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) +3710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); +3712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +3716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management +3719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +3720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the update interrupt flag (UIF). +3723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE +3724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) +3728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); +3730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). +3734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE + ARM GAS /tmp/ccWQNJQt.s page 288 + + +3735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) +3739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); +3741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). +3745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 +3746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) +3750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); +3752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 inte +3756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 +3757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) +3761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); +3763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). +3767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 +3768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) +3772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); +3774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 inte +3778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 +3779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) +3783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); +3785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). +3789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 +3790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None + ARM GAS /tmp/ccWQNJQt.s page 289 + + +3792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) +3794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); +3796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 inte +3800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 +3801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) +3805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); +3807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). +3811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 +3812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) +3816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); +3818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 inte +3822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 +3823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) +3827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); +3829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). +3833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 +3834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) +3838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); +3840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 inte +3844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 +3845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) + ARM GAS /tmp/ccWQNJQt.s page 290 + + +3849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); +3851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). +3855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 +3856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) +3860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); +3862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 inte +3866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 +3867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) +3871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); +3873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the commutation interrupt flag (COMIF). +3877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR COMIF LL_TIM_ClearFlag_COM +3878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) +3882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); +3884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pe +3888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM +3889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) +3893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); +3895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the trigger interrupt flag (TIF). +3899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG +3900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) +3904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); + ARM GAS /tmp/ccWQNJQt.s page 291 + + +3906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). +3910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG +3911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) +3915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); +3917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the break interrupt flag (BIF). +3921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR BIF LL_TIM_ClearFlag_BRK +3922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) +3926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); +3928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). +3932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK +3933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) +3937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); +3939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the break 2 interrupt flag (B2IF). +3943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 +3944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) +3948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); +3950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). +3954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 +3955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) +3959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); +3961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + ARM GAS /tmp/ccWQNJQt.s page 292 + + +3963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). +3965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR +3966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) +3970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); +3972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set +3976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 1 interrupt is pending). +3977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR +3978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) +3982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); +3984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). +3988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR +3989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) +3993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); +3995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set +3999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 2 over-capture interrupt is pending). +4000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR +4001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) +4005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); +4007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). +4011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR +4012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) +4016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); +4018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + ARM GAS /tmp/ccWQNJQt.s page 293 + + +4020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set +4022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 3 over-capture interrupt is pending). +4023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR +4024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) +4028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); +4030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). +4034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR +4035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) +4039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); +4041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set +4045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 4 over-capture interrupt is pending). +4046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR +4047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) +4051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); +4053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the system break interrupt flag (SBIF). +4057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK +4058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) +4062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); +4064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is p +4068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK +4069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) +4073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); +4075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + ARM GAS /tmp/ccWQNJQt.s page 294 + + +4077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +4079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_IT_Management IT-Management +4082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +4083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable update interrupt (UIE). +4086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE +4087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) + 3905 .loc 5 4090 22 view .LVU1290 + 3906 .LBB444: +4091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_UIE); + 3907 .loc 5 4092 3 view .LVU1291 + 3908 00a6 884B ldr r3, .L141+72 + 3909 00a8 DA68 ldr r2, [r3, #12] + 3910 00aa 42F00102 orr r2, r2, #1 + 3911 00ae DA60 str r2, [r3, #12] + 3912 .LVL275: + 3913 .loc 5 4092 3 is_stmt 0 view .LVU1292 + 3914 .LBE444: + 3915 .LBE443: +1924:Src/main.c **** LL_TIM_EnableIT_UPDATE(TIM7); + 3916 .loc 1 1924 2 is_stmt 1 view .LVU1293 + 3917 .LBB445: + 3918 .LBI445: +1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 3919 .loc 5 1313 22 view .LVU1294 + 3920 .LBB446: +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 3921 .loc 5 1315 3 view .LVU1295 + 3922 00b0 1A68 ldr r2, [r3] + 3923 00b2 42F00102 orr r2, r2, #1 + 3924 00b6 1A60 str r2, [r3] + 3925 .LVL276: +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 3926 .loc 5 1315 3 is_stmt 0 view .LVU1296 + 3927 .LBE446: + 3928 .LBE445: +1925:Src/main.c **** LL_TIM_EnableCounter(TIM7); + 3929 .loc 1 1925 2 is_stmt 1 view .LVU1297 + 3930 .LBB447: + 3931 .LBI447: +4090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 3932 .loc 5 4090 22 view .LVU1298 + 3933 .LBB448: + 3934 .loc 5 4092 3 view .LVU1299 + 3935 00b8 03F58063 add r3, r3, #1024 + 3936 00bc DA68 ldr r2, [r3, #12] + 3937 00be 42F00102 orr r2, r2, #1 + 3938 00c2 DA60 str r2, [r3, #12] + 3939 .LVL277: + ARM GAS /tmp/ccWQNJQt.s page 295 + + + 3940 .loc 5 4092 3 is_stmt 0 view .LVU1300 + 3941 .LBE448: + 3942 .LBE447: +1926:Src/main.c **** //HAL_TIM_Base_Start_IT(&htim6); + 3943 .loc 1 1926 2 is_stmt 1 view .LVU1301 + 3944 .LBB449: + 3945 .LBI449: +1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 3946 .loc 5 1313 22 view .LVU1302 + 3947 .LBB450: +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 3948 .loc 5 1315 3 view .LVU1303 + 3949 00c4 1A68 ldr r2, [r3] + 3950 00c6 42F00102 orr r2, r2, #1 + 3951 00ca 1A60 str r2, [r3] + 3952 .LVL278: +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 3953 .loc 5 1315 3 is_stmt 0 view .LVU1304 + 3954 .LBE450: + 3955 .LBE449: +1933:Src/main.c **** LL_DMA_ClearFlag_TC7(DMA2); + 3956 .loc 1 1933 3 is_stmt 1 view .LVU1305 + 3957 .LBB451: + 3958 .LBI451: + 3959 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @file stm32f7xx_ll_dma.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Header file of DMA LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * This software is licensed under terms that can be found in the LICENSE file in + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifndef __STM32F7xx_LL_DMA_H + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __STM32F7xx_LL_DMA_H + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifdef __cplusplus + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** extern "C" { + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Includes ------------------------------------------------------------------*/ + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #include "stm32f7xx.h" + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @addtogroup STM32F7xx_LL_Driver + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + ARM GAS /tmp/ccWQNJQt.s page 296 + + + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined (DMA1) || defined (DMA2) + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL DMA + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private types -------------------------------------------------------------*/ + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private variables ---------------------------------------------------------*/ + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Variables DMA Private Variables + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** static const uint8_t STREAM_OFFSET_TAB[] = + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }; + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private constants ---------------------------------------------------------*/ + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Constants DMA Private Constants + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_SxCR_CHSEL_3) + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define DMA_CHANNEL_SELECTION_8_15 + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_SxCR_CHSEL_3 */ + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private macros ------------------------------------------------------------*/ + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported types ------------------------------------------------------------*/ + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(USE_FULL_LL_DRIVER) + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** typedef struct + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or as Source base address in case of memory to memory trans + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or as Destination base address in case of memory to memory + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + ARM GAS /tmp/ccWQNJQt.s page 297 + + + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Direction; /*!< Specifies if the data will be transferred from memory to pe + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** from memory to memory or from peripheral to memory. + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_DIRECTION + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Mode; /*!< Specifies the normal or circular operation mode. + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MODE + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The circular buffer mode cannot be used if the memory + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** data transfer direction is configured on the selected + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** is incremented or not. + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PERIPH + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** is incremented or not. + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MEMORY + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** in case of memory to memory transfer direction. + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination dat + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** in case of memory to memory transfer direction. + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** The data unit is equal to the source buffer configuration s + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or MemorySize parameters depending in the transfer directio + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Channel; /*!< Specifies the peripheral channel. + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_CHANNEL + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Priority; /*!< Specifies the channel priority level. + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PRIORITY + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for + ARM GAS /tmp/ccWQNJQt.s page 298 + + + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_FIFOMODE + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The Direct mode (FIFO mode disabled) cannot be used i + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** memory-to-memory data transfer is configured on the selecte + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHO + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory t + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** It specifies the amount of data to be transferred in a sing + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** transaction. + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MBURST + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The burst mode is possible only if the address Increm + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripher + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** It specifies the amount of data to be transferred in a sing + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** transaction. + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PBURST + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The burst mode is possible only if the address Increm + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } LL_DMA_InitTypeDef; + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /*USE_FULL_LL_DRIVER*/ + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported constants --------------------------------------------------------*/ + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_STREAM STREAM + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_0 0x00000000U + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_1 0x00000001U + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_2 0x00000002U + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_3 0x00000003U + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_4 0x00000004U + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_5 0x00000005U + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_6 0x00000006U + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_7 0x00000007U + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_ALL 0xFFFF0000U + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DIRECTION DIRECTION + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direc + ARM GAS /tmp/ccWQNJQt.s page 299 + + + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direc + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MODE MODE + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mo + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering m + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mo + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PERIPH PERIPH + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MEMORY MEMORY + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disa + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enab + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : By + ARM GAS /tmp/ccWQNJQt.s page 300 + + + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : Ha + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Wo + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offse + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offse + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PRIORITY PRIORITY + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CHANNEL CHANNEL + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_0 0x00000000U + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_CHANNEL_SELECTION_8_15) + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_15 DMA_SxCR_CHSEL + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_CHANNEL_SELECTION_8_15 */ + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MBURST MBURST + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst + ARM GAS /tmp/ccWQNJQt.s page 301 + + + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PBURST PBURST + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral b + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral b + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral b + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral b + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode di + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode en + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_lev + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_l + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_l + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_l + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empt + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO thresho + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO thresho + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO thresho + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO thresho + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentT + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentT + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + ARM GAS /tmp/ccWQNJQt.s page 302 + + + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported macro ------------------------------------------------------------*/ + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Write a value in DMA register + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __INSTANCE__ DMA Instance + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __REG__ Register to be written + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __VALUE__ Value to be written in the register + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Read a value in DMA register + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __INSTANCE__ DMA Instance + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __REG__ Register to be read + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Register value + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMAx_Streamy into DMAx + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM_INSTANCE__ DMAx_Streamy + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval DMAx + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM_INSTANCE__ DMAx_Streamy + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval LL_DMA_CHANNEL_y + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ + ARM GAS /tmp/ccWQNJQt.s page 303 + + + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** LL_DMA_STREAM_7) + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __DMA_INSTANCE__ DMAx + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM__ LL_DMA_STREAM_y + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval DMAx_Streamy + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** DMA2_Stream7) + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported functions --------------------------------------------------------*/ + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_Configuration Configuration + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable DMA stream. + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_EnableStream + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + ARM GAS /tmp/ccWQNJQt.s page 304 + + + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable DMA stream. + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_DisableStream + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) + 3960 .loc 6 517 22 view .LVU1306 + 3961 .LBB452: + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 3962 .loc 6 519 3 view .LVU1307 + 3963 00cc 03F51433 add r3, r3, #151552 + 3964 00d0 D3F8B820 ldr r2, [r3, #184] + 3965 00d4 22F00102 bic r2, r2, #1 + 3966 00d8 C3F8B820 str r2, [r3, #184] + 3967 .LVL279: + 3968 .loc 6 519 3 is_stmt 0 view .LVU1308 + 3969 .LBE452: + 3970 .LBE451: +1934:Src/main.c **** LL_DMA_ClearFlag_TE7(DMA2); + 3971 .loc 1 1934 3 is_stmt 1 view .LVU1309 + 3972 .LBB453: + 3973 .LBI453: + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Check if DMA stream is enabled or disabled. + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_IsEnabledStream + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + ARM GAS /tmp/ccWQNJQt.s page 305 + + + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure all parameters linked to DMA transfer. + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_ConfigTransfer\n + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR CIRC LL_DMA_ConfigTransfer\n + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PINC LL_DMA_ConfigTransfer\n + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR MINC LL_DMA_ConfigTransfer\n + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PSIZE LL_DMA_ConfigTransfer\n + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR MSIZE LL_DMA_ConfigTransfer\n + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PL LL_DMA_ConfigTransfer\n + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_ConfigTransfer + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Configuration This parameter must be a combination of all the following values: + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH o + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDAT + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDAT + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HI + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** *@retval None + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configurati + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_Sx + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** Configuration); + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Data transfer direction (read from peripheral or from memory). + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_SetDataTransferDirection + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + ARM GAS /tmp/ccWQNJQt.s page 306 + + + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Direction This parameter can be one of the following values: + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Data transfer direction (read from peripheral or from memory). + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_GetDataTransferDirection + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set DMA mode normal, circular or peripheral flow control. + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CIRC LL_DMA_SetMode\n + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_SetMode + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Mode This parameter can be one of the following values: + 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL + 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_CIRCULAR + 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_PFCTRL + 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + ARM GAS /tmp/ccWQNJQt.s page 307 + + + 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) + 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get DMA mode normal, circular or peripheral flow control. + 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CIRC LL_DMA_GetMode\n + 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_GetMode + 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL + 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_CIRCULAR + 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_PFCTRL + 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) + 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral increment mode. + 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINC LL_DMA_SetPeriphIncMode + 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param IncrementMode This parameter can be one of the following values: + 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_NOINCREMENT + 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT + 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment + 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral increment mode. + 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINC LL_DMA_GetPeriphIncMode + 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + ARM GAS /tmp/ccWQNJQt.s page 308 + + + 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_NOINCREMENT + 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT + 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) + 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory increment mode. + 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MINC LL_DMA_SetMemoryIncMode + 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param IncrementMode This parameter can be one of the following values: + 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_NOINCREMENT + 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT + 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment + 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory increment mode. + 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MINC LL_DMA_GetMemoryIncMode + 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_NOINCREMENT + 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT + ARM GAS /tmp/ccWQNJQt.s page 309 + + + 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) + 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral size. + 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PSIZE LL_DMA_SetPeriphSize + 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Size This parameter can be one of the following values: + 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE + 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_WORD + 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) + 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral size. + 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PSIZE LL_DMA_GetPeriphSize + 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE + 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_WORD + 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) + 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory size. + 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MSIZE LL_DMA_SetMemorySize + 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + ARM GAS /tmp/ccWQNJQt.s page 310 + + + 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Size This parameter can be one of the following values: + 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE + 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_WORD + 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) + 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory size. + 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MSIZE LL_DMA_GetMemorySize + 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE + 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_WORD + 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) + 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral increment offset size. + 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize + 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param OffsetSize This parameter can be one of the following values: + ARM GAS /tmp/ccWQNJQt.s page 311 + + + 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSiz + 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral increment offset size. + 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize + 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) + 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Stream priority level. + 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Priority This parameter can be one of the following values: + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW + 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_MEDIUM + 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_HIGH + 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_VERYHIGH + 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pr + 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + ARM GAS /tmp/ccWQNJQt.s page 312 + + + 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream priority level. + 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel + 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW + 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_MEDIUM + 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_HIGH + 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_VERYHIGH + 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) + 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Number of data to transfer. + 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll NDTR NDT LL_DMA_SetDataLength + 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This action has no effect if + 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * stream is enabled. + 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param NbData Between 0 to 0xFFFFFFFF + 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) + 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, + 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Number of data to transfer. + 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll NDTR NDT LL_DMA_GetDataLength + 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Once the stream is enabled, the return value indicate the + 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * remaining bytes to be transmitted. + 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + ARM GAS /tmp/ccWQNJQt.s page 313 + + + 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF + 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) + 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Select Channel number associated to the Stream. +1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CHSEL LL_DMA_SetChannelSelection +1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: +1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_0 +1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 +1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 +1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 +1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 +1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 +1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 +1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 +1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_8 (*) +1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_9 (*) +1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_10 (*) +1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_11 (*) +1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_12 (*) +1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_13 (*) +1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_14 (*) +1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_15 (*) +1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * +1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * (*) value not defined in all devices. +1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channe +1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D +1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Channel number associated to the Stream. +1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CHSEL LL_DMA_GetChannelSelection +1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + ARM GAS /tmp/ccWQNJQt.s page 314 + + +1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: +1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_0 +1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 +1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 +1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 +1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 +1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 +1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 +1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 +1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_8 (*) +1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_9 (*) +1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_10 (*) +1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_11 (*) +1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_12 (*) +1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_13 (*) +1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_14 (*) +1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_15 (*) +1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * +1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * (*) value not defined in all devices. +1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream) +1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory burst transfer configuration. +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer +1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Mburst This parameter can be one of the following values: +1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_SINGLE +1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC4 +1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC8 +1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC16 +1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) +1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D +1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + ARM GAS /tmp/ccWQNJQt.s page 315 + + +1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory burst transfer configuration. +1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer +1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: +1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_SINGLE +1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC4 +1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC8 +1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC16 +1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral burst transfer configuration. +1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer +1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Pburst This parameter can be one of the following values: +1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_SINGLE +1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC4 +1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC8 +1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC16 +1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) +1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D +1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral burst transfer configuration. +1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer +1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + ARM GAS /tmp/ccWQNJQt.s page 316 + + +1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: +1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_SINGLE +1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC4 +1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC8 +1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC16 +1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. +1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CT LL_DMA_SetCurrentTargetMem +1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param CurrentMemory This parameter can be one of the following values: +1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM0 +1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM1 +1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Curren +1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, +1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. +1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CT LL_DMA_GetCurrentTargetMem +1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: +1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM0 +1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM1 +1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) +1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + ARM GAS /tmp/ccWQNJQt.s page 317 + + +1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable the double buffer mode. +1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode +1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA +1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable the double buffer mode. +1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode +1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D +1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get FIFO status. +1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FS LL_DMA_GetFIFOStatus +1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + ARM GAS /tmp/ccWQNJQt.s page 318 + + +1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_0_25 +1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_25_50 +1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_50_75 +1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_75_100 +1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_EMPTY +1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_FULL +1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) +1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable Fifo mode. +1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode +1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, +1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Fifo mode. +1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode +1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DM +1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Select FIFO threshold. +1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold +1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + ARM GAS /tmp/ccWQNJQt.s page 319 + + +1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Threshold This parameter can be one of the following values: +1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 +1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 +1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 +1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL +1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold +1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, +1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get FIFO threshold. +1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold +1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: +1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 +1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 +1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 +1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure the FIFO . +1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_ConfigFifo\n +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * FCR DMDIS LL_DMA_ConfigFifo +1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + ARM GAS /tmp/ccWQNJQt.s page 320 + + +1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param FifoMode This parameter can be one of the following values: +1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOMODE_ENABLE +1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOMODE_DISABLE +1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param FifoThreshold This parameter can be one of the following values: +1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 +1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 +1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 +1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL +1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint3 +1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, +1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure the Source and Destination addresses. +1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA stream is enabled. +1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n +1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * PAR PA LL_DMA_ConfigAddresses +1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param SrcAddress Between 0 to 0xFFFFFFFF +1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DstAddress Between 0 to 0xFFFFFFFF +1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Direction This parameter can be one of the following values: +1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY +1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH +1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY +1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress +1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Direction Memory to Periph */ +1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) +1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR +1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, +1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Direction Periph to Memory and Memory to Memory */ +1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** else +1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, +1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR +1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Memory address. + ARM GAS /tmp/ccWQNJQt.s page 321 + + +1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress +1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO +1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. +1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param MemoryAddress Between 0 to 0xFFFFFFFF +1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd +1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, +1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Peripheral address. +1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_SetPeriphAddress +1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO +1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. +1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param PeriphAddress Between 0 to 0xFFFFFFFF +1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAdd +1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, P +1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Memory address. +1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress +1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO +1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + ARM GAS /tmp/ccWQNJQt.s page 322 + + +1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF +1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream) +1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Peripheral address. +1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_GetPeriphAddress +1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO +1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF +1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream) +1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream]))) +1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Memory to Memory Source address. +1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress +1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. +1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. +1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param MemoryAddress Between 0 to 0xFFFFFFFF +1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd +1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, M +1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Memory to Memory Destination address. +1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress +1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. +1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. + ARM GAS /tmp/ccWQNJQt.s page 323 + + +1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param MemoryAddress Between 0 to 0xFFFFFFFF +1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd +1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR +1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Memory to Memory Source address. +1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress +1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. +1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF +1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream) +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])) +1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Memory to Memory Destination address. +1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress +1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. +1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF +1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream) +1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + ARM GAS /tmp/ccWQNJQt.s page 324 + + +1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-> +1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory 1 address (used in case of Double buffer mode). +1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M1AR M1A LL_DMA_SetMemory1Address +1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Address Between 0 to 0xFFFFFFFF +1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) +1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, +1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory 1 address (used in case of Double buffer mode). +1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M1AR M1A LL_DMA_GetMemory1Address +1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF +1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) +1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR); +1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} +1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management +1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ +1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 half transfer flag. +1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 +1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). + ARM GAS /tmp/ccWQNJQt.s page 325 + + +1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) +1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0)); +1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 half transfer flag. +1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 +1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1)); +1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 half transfer flag. +1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 +1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2)); +1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 half transfer flag. +1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 +1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3)); +1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 half transfer flag. +1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 +1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); +1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 half transfer flag. +1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 +1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) + ARM GAS /tmp/ccWQNJQt.s page 326 + + +1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); +1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 half transfer flag. +1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 +1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); +1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 half transfer flag. +1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 +1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); +1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 transfer complete flag. +1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 +1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) +1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0)); +1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 transfer complete flag. +1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1)); +1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 transfer complete flag. +1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 +1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2)); + ARM GAS /tmp/ccWQNJQt.s page 327 + + +1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 transfer complete flag. +1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 +1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3)); +1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 transfer complete flag. +1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 +1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); +1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 transfer complete flag. +1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 +1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); +1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 transfer complete flag. +1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 +1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); +1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 transfer complete flag. +1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 +1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); +1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + ARM GAS /tmp/ccWQNJQt.s page 328 + + +1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 transfer error flag. +1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 +1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) +1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0)); +1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 transfer error flag. +1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 +1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1)); +1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 transfer error flag. +1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 +1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2)); +1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 transfer error flag. +1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 +1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3)); +1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 transfer error flag. +1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 +1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); +1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 transfer error flag. + ARM GAS /tmp/ccWQNJQt.s page 329 + + +1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 +1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); +1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 transfer error flag. +1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 +1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6)); +1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 transfer error flag. +1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 +1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7)); +1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 direct mode error flag. +1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 +1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) +1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0)); +1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 direct mode error flag. +1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 +1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) +1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1)); +1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 direct mode error flag. +1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 +1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + ARM GAS /tmp/ccWQNJQt.s page 330 + + +1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) +1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2)); +1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 direct mode error flag. +1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 +1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) +1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3)); +1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 direct mode error flag. +1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 +1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) +1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4)); +1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 direct mode error flag. +1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 +1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) +1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5)); +1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 direct mode error flag. +1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 +1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) +2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6)); +2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 direct mode error flag. +2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 +2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + ARM GAS /tmp/ccWQNJQt.s page 331 + + +2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) +2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7)); +2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 FIFO error flag. +2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 +2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) +2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0)); +2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 FIFO error flag. +2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) +2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1)); +2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 FIFO error flag. +2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 +2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) +2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2)); +2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 FIFO error flag. +2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 +2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) +2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3)); +2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 FIFO error flag. +2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 +2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) +2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + ARM GAS /tmp/ccWQNJQt.s page 332 + + +2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4)); +2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 FIFO error flag. +2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 +2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) +2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5)); +2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 FIFO error flag. +2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 +2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) +2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6)); +2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 FIFO error flag. +2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 +2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) +2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7)); +2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 half transfer flag. +2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 +2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) +2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); +2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 half transfer flag. +2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 +2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1); +2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + ARM GAS /tmp/ccWQNJQt.s page 333 + + +2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 half transfer flag. +2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 +2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2); +2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 half transfer flag. +2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 +2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3); +2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 half transfer flag. +2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 +2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4); +2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 half transfer flag. +2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 +2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5); +2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 half transfer flag. +2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 +2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6); +2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + ARM GAS /tmp/ccWQNJQt.s page 334 + + +2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 half transfer flag. +2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 +2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7); +2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 transfer complete flag. +2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 +2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) +2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0); +2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 transfer complete flag. +2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 +2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1); +2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 transfer complete flag. +2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 +2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2); +2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 transfer complete flag. +2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 +2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3); +2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 transfer complete flag. +2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 + ARM GAS /tmp/ccWQNJQt.s page 335 + + +2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4); +2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 transfer complete flag. +2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 +2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5); +2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 transfer complete flag. +2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 +2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6); +2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 transfer complete flag. +2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 +2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) + 3974 .loc 6 2277 22 view .LVU1310 + 3975 .LBB454: +2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7); + 3976 .loc 6 2279 3 view .LVU1311 + 3977 00dc 4FF00062 mov r2, #134217728 + 3978 00e0 DA60 str r2, [r3, #12] + 3979 .LVL280: + 3980 .loc 6 2279 3 is_stmt 0 view .LVU1312 + 3981 .LBE454: + 3982 .LBE453: +1935:Src/main.c **** LL_USART_EnableDMAReq_TX(USART1); + 3983 .loc 1 1935 3 is_stmt 1 view .LVU1313 + 3984 .LBB455: + 3985 .LBI455: +2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 transfer error flag. +2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 + ARM GAS /tmp/ccWQNJQt.s page 336 + + +2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) +2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0); +2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 transfer error flag. +2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 +2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1); +2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 transfer error flag. +2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 +2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2); +2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 transfer error flag. +2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 +2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3); +2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 transfer error flag. +2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 +2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4); +2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 transfer error flag. +2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 +2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + ARM GAS /tmp/ccWQNJQt.s page 337 + + +2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5); +2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 transfer error flag. +2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 +2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6); +2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 transfer error flag. +2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 +2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) + 3986 .loc 6 2365 22 view .LVU1314 + 3987 .LBB456: +2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7); + 3988 .loc 6 2367 3 view .LVU1315 + 3989 00e2 4FF00072 mov r2, #33554432 + 3990 00e6 DA60 str r2, [r3, #12] + 3991 .LVL281: + 3992 .loc 6 2367 3 is_stmt 0 view .LVU1316 + 3993 .LBE456: + 3994 .LBE455: +1936:Src/main.c **** LL_DMA_EnableIT_TC(DMA2, LL_DMA_STREAM_7); + 3995 .loc 1 1936 3 is_stmt 1 view .LVU1317 + 3996 .LBB457: + 3997 .LBI457: + 3998 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @file stm32f7xx_ll_usart.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Header file of USART LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This software is licensed under terms that can be found in the LICENSE file + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * in the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + ARM GAS /tmp/ccWQNJQt.s page 338 + + + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifndef STM32F7xx_LL_USART_H + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define STM32F7xx_LL_USART_H + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifdef __cplusplus + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** extern "C" { + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Includes ------------------------------------------------------------------*/ + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #include "stm32f7xx.h" + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @addtogroup STM32F7xx_LL_Driver + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \ + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL USART + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private types -------------------------------------------------------------*/ + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private variables ---------------------------------------------------------*/ + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private constants ---------------------------------------------------------*/ + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Constants USART Private Constants + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private macros ------------------------------------------------------------*/ + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Macros USART Private Macros + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/ + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported types ------------------------------------------------------------*/ + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_ES_INIT USART Exported Init structures + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief LL USART Init Structure definition + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t BaudRate; /*!< This field defines expected Usart communication baud rat + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ARM GAS /tmp/ccWQNJQt.s page 339 + + + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetBaudRate().*/ + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or receive + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_DATAWI + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetDataWidth().*/ + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_STOPBI + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetStopBitsLength().*/ + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t Parity; /*!< Specifies the parity mode. + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_PARITY + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetParity().*/ + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is en + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_DIRECT + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetTransferDirection().*/ + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enab + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_HWCONT + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetHWFlowCtrl().*/ + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_OVERSA + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetOverSampling().*/ + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_InitTypeDef; + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief LL USART Clock Init Structure definition + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_CLOCK. + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_Disabl + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_POLARI + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using + ARM GAS /tmp/ccWQNJQt.s page 340 + + + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetClockPolarity(). + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_PHASE. + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetClockPhase(). + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the l + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** data bit (MSB) has to be output on the SCLK pin in synch + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_LASTCL + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetLastClkPulseOutput(). + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_ClockInitTypeDef; + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USE_FULL_LL_DRIVER */ + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported constants --------------------------------------------------------*/ + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Constants USART Exported Constants + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Flags defines which can be used with LL_USART_WriteReg function + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error cle + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error cl + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error dete + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error cl + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detect + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission com + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission com + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detect + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag * + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block cle + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ARM GAS /tmp/ccWQNJQt.s page 341 + + + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Flags defines which can be used with LL_USART_ReadReg function + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error fla + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error fl + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected f + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error fl + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detect + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data regist + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission com + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data re + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detect + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt fl + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block fla + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate e + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate f + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_ISR_REACK) + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable a + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_ISR_REACK */ + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission com + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IT IT Defines + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt e + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data regist + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission com + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data re + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block int + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detect + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt en + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop + ARM GAS /tmp/ccWQNJQt.s page 342 + + + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission com + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DIRECTION Communication Direction + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PARITY Parity Control + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_NONE 0x00000000U /*!< Parity co + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity co + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity co + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP Wakeup + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DATAWIDTH Datawidth + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : S + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : S + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : S + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + ARM GAS /tmp/ccWQNJQt.s page 343 + + + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLOCK Clock Signal + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provid + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided * + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/ + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the l + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the l + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PHASE Clock Phase + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transiti + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transit + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_POLARITY Clock Polarity + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCL + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_STOPBITS Stop Bits + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1 0x00000000U /*!< 1 s + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 s + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as d + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + ARM GAS /tmp/ccWQNJQt.s page 344 + + + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works usin + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works usin + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the da + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the da + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BITORDER Bit Order + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/rece + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/rece + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Me + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Fa + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + ARM GAS /tmp/ccWQNJQt.s page 345 + + + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_HWCONTROL Hardware Control + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and R + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS outpu + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and R + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS) + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake u + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake u + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake u + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */ + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode * + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection m + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection m + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + ARM GAS /tmp/ccWQNJQt.s page 346 + + + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data regis + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data regis + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported macro ------------------------------------------------------------*/ + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Macros USART Exported Macros + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Write a value in USART register + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __INSTANCE__ USART Instance + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __REG__ Register to be written + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __VALUE__ Value to be written in the register + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VAL + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Read a value in USART register + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __INSTANCE__ USART Instance + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __REG__ Register to be read + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Register value + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Compute USARTDIV value according to Peripheral Clock and + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __BAUDRATE__ Baud rate value to achieve + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\ + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ((__BAUDRATE__)/2U))/(__BAUDRATE_ + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Compute USARTDIV value according to Peripheral Clock and + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + ARM GAS /tmp/ccWQNJQt.s page 347 + + + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __BAUDRATE__ Baud rate value to achieve + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/ + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported functions --------------------------------------------------------*/ + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Functions USART Exported Functions + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration Configuration functions + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Enable + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_Enable + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR1, USART_CR1_UE); + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Disable (all USART prescalers and outputs are disabled) + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When USART is disabled, USART prescalers and outputs are stopped immediately, + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * and current operations are discarded. The configuration of the USART is kept, but all t + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * flags, in the USARTx_ISR are set to their default values. + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_Disable + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR1, USART_CR1_UE); + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART is enabled + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_IsEnabled + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); + ARM GAS /tmp/ccWQNJQt.s page 348 + + + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART enabled in STOP Mode. + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provide + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * USART clock selection is HSI or LSE in RCC. + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_EnableInStopMode + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART disabled in STOP Mode. + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_DisableInStopMode + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_UCESM) + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Clock enabled in STOP Mode + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is called, USART Clock is enabled while in STOP mode + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_EnableClockInStopMode + 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx) + 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_UCESM); + 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + ARM GAS /tmp/ccWQNJQt.s page 349 + + + 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART clock disabled in STOP Mode + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is called, USART Clock is disabled while in STOP mode + 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_DisableClockInStopMode + 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx) + 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM); + 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART clock is enabled in STOP Mode + 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_IsClockEnabledInStopMode + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(const USART_TypeDef *USARTx) + 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)); + 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_UCESM */ + 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM*/ + 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_EnableDirectionRx + 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) + 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); + 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Receiver Disable + 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_DisableDirectionRx + 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) + 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); + 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Transmitter Enable + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TE LL_USART_EnableDirectionTx + 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) + 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); + ARM GAS /tmp/ccWQNJQt.s page 350 + + + 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Transmitter Disable + 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TE LL_USART_DisableDirectionTx + 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) + 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); + 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure simultaneously enabled/disabled states + 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * of Transmitter and Receiver + 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_SetTransferDirection\n + 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 TE LL_USART_SetTransferDirection + 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param TransferDirection This parameter can be one of the following values: + 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_NONE + 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_RX + 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX + 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX_RX + 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirectio + 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); + 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return enabled/disabled states of Transmitter and Receiver + 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_GetTransferDirection\n + 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 TE LL_USART_GetTransferDirection + 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_NONE + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_RX + 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX + 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX_RX + 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) + 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); + 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Parity (enabled/disabled and parity mode if enabled). + 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This function selects if hardware parity control (generation and detection) is enabled + 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * When the parity control is enabled (Odd or Even), computed parity bit is inserted at th + 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (9th or 8th bit depending on data width) and parity is checked on the received data. + 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_SetParity\n + 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_SetParity + 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Parity This parameter can be one of the following values: + 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE + ARM GAS /tmp/ccWQNJQt.s page 351 + + + 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN + 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD + 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) + 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); + 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_GetParity\n + 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_GetParity + 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE + 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN + 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD + 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) + 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); + 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Receiver Wake Up method from Mute mode. + 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod + 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Method This parameter can be one of the following values: + 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_IDLELINE + 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) + 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); + 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Receiver Wake Up method from Mute mode + 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod + 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_IDLELINE + 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) + 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); + 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) + 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 M0 LL_USART_SetDataWidth\n + 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_SetDataWidth + 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataWidth This parameter can be one of the following values: + ARM GAS /tmp/ccWQNJQt.s page 352 + + + 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B + 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B + 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B + 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) + 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); + 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 M0 LL_USART_GetDataWidth\n + 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_GetDataWidth + 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B + 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B + 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B + 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) + 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); + 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Allow switch between Mute Mode and Active mode + 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_EnableMuteMode + 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) + 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); + 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_DisableMuteMode + 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) + 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); + 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if switch between Mute Mode and Active mode is allowed + 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode + 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). + 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) + 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); + 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + ARM GAS /tmp/ccWQNJQt.s page 353 + + + 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Oversampling to 8-bit or 16-bit mode + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 OVER8 LL_USART_SetOverSampling + 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: + 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 + 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 + 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) + 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); + 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Oversampling mode + 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 OVER8 LL_USART_GetOverSampling + 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 + 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 + 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) + 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); + 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not + 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput + 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LastBitClockPulse This parameter can be one of the following values: + 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPul + 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); + 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve Clock pulse of the last data bit output configuration + 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (Last bit Clock pulse output to the SCLK pin or not) + 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput + 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) + 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + ARM GAS /tmp/ccWQNJQt.s page 354 + + + 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); + 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select the phase of the clock output on the SCLK pin in synchronous mode + 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_SetClockPhase + 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param ClockPhase This parameter can be one of the following values: + 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE + 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE + 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) + 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); + 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return phase of the clock output on the SCLK pin in synchronous mode + 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_GetClockPhase + 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE + 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE + 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) + 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); + 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode + 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPOL LL_USART_SetClockPolarity + 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param ClockPolarity This parameter can be one of the following values: + 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW + 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) + 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); + 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return polarity of the clock output on the SCLK pin in synchronous mode + 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPOL LL_USART_GetClockPolarity + 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + ARM GAS /tmp/ccWQNJQt.s page 355 + + + 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW + 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH + 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) + 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); + 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock + 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : +1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function +1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function +1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutpu +1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_ConfigClock\n +1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CPOL LL_USART_ConfigClock\n +1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 LBCL LL_USART_ConfigClock +1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Phase This parameter can be one of the following values: +1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE +1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE +1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Polarity This parameter can be one of the following values: +1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW +1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH +1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LBCPOutput This parameter can be one of the following values: +1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT +1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT +1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, +1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCP +1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Clock output on SCLK pin +1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not +1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. +1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput +1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) +1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Clock output on SCLK pin +1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not +1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. +1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput +1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + ARM GAS /tmp/ccWQNJQt.s page 356 + + +1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) +1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); +1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Clock output on SCLK pin is enabled +1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not +1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. +1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput +1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) +1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); +1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set the length of the stop bits +1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 STOP LL_USART_SetStopBitsLength +1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param StopBits This parameter can be one of the following values: +1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 +1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 +1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 +1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 +1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) +1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve the length of the stop bits +1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 STOP LL_USART_GetStopBitsLength +1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 +1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 +1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 +1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 +1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) +1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); +1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) +1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : +1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Data Width configuration using @ref LL_USART_SetDataWidth() function +1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Parity Control and mode configuration using @ref LL_USART_SetParity() function +1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function +1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_ConfigCharacter\n +1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_ConfigCharacter\n + ARM GAS /tmp/ccWQNJQt.s page 357 + + +1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M0 LL_USART_ConfigCharacter\n +1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_ConfigCharacter\n +1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigCharacter +1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataWidth This parameter can be one of the following values: +1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B +1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B +1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B +1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Parity This parameter can be one of the following values: +1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE +1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN +1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD +1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param StopBits This parameter can be one of the following values: +1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 +1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 +1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 +1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 +1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t P +1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t StopBits) +1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); +1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure TX/RX pins swapping setting. +1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap +1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param SwapConfig This parameter can be one of the following values: +1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_STANDARD +1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_SWAPPED +1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) +1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); +1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve TX/RX pins swapping configuration. +1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap +1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_STANDARD +1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_SWAPPED +1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) +1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); +1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure RX pin active level logic +1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel +1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + ARM GAS /tmp/ccWQNJQt.s page 358 + + +1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PinInvMethod This parameter can be one of the following values: +1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD +1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED +1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); +1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve RX pin active level logic configuration +1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel +1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD +1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED +1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) +1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); +1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure TX pin active level logic +1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel +1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PinInvMethod This parameter can be one of the following values: +1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD +1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED +1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); +1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve TX pin active level logic configuration +1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel +1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD +1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED +1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) +1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); +1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Binary data logic. +1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Allow to define how Logical data from the data register are send/received : +1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) +1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic +1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataLogic This parameter can be one of the following values: + ARM GAS /tmp/ccWQNJQt.s page 359 + + +1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE +1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE +1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) +1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); +1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve Binary data configuration +1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic +1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE +1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE +1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) +1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); +1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure transfer bit order (either Less or Most Significant Bit First) +1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note MSB First means data is transmitted/received with the MSB first, following the start bi +1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LSB First means data is transmitted/received with data bit 0 first, following the start +1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder +1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BitOrder This parameter can be one of the following values: +1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_LSBFIRST +1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_MSBFIRST +1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) +1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return transfer bit order (either Less or Most Significant Bit First) +1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note MSB First means data is transmitted/received with the MSB first, following the start bi +1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LSB First means data is transmitted/received with data bit 0 first, following the start +1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder +1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_LSBFIRST +1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_MSBFIRST +1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) +1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); +1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Auto Baud-Rate Detection +1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or +1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. + ARM GAS /tmp/ccWQNJQt.s page 360 + + +1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate +1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) +1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_ABREN); +1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Auto Baud-Rate Detection +1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or +1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate +1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) +1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); +1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled +1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud +1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) +1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); +1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Auto Baud-Rate mode bits +1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or +1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode +1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AutoBaudRateMode This parameter can be one of the following values: +1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE +1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME +1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME +1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) +1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); +1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Auto Baud-Rate mode +1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or +1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. + ARM GAS /tmp/ccWQNJQt.s page 361 + + +1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode +1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT +1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE +1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME +1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME +1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) +1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); +1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Receiver Timeout +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout +1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) +1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_RTOEN); +1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Receiver Timeout +1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout +1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) +1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); +1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Receiver Timeout feature is enabled +1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) +1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Address of the USART node. +1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This is used in multiprocessor communication during Mute mode or Stop mode, +1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * for wake up with address mark detection. +1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. +1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (b7-b4 should be set to 0) +1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. +1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (This is used in multiprocessor communication during Mute mode or Stop mode, +1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * for wake up with 7-bit address mark detection. +1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * The MSB of the character sent by the transmitter should be equal to 1. +1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * It may also be used for character detection during normal reception, + ARM GAS /tmp/ccWQNJQt.s page 362 + + +1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Mute mode inactive (for example, end of block detection in ModBus protocol). +1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * In this case, the whole received character (8-bit) is compared to the ADD[7:0] +1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * value and CMF flag is set on match) +1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n +1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 ADDM7 LL_USART_ConfigNodeAddress +1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AddressLen This parameter can be one of the following values: +1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_4B +1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_7B +1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param NodeAddress 4 or 7 bit Address of the USART node. +1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_ +1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, +1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); +1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. +1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note If 4-bit Address Detection is selected in ADDM7, +1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) +1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * If 7-bit Address Detection is selected in ADDM7, +1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) +1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADD LL_USART_GetNodeAddress +1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) +1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) +1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) +1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen +1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_4B +1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_7B +1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) +1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); +1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable RTS HW Flow Control +1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl +1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) +1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_RTSE); + ARM GAS /tmp/ccWQNJQt.s page 363 + + +1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable RTS HW Flow Control +1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl +1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) +1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); +1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable CTS HW Flow Control +1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl +1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) +1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_CTSE); +1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable CTS HW Flow Control +1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl +1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) +1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); +1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure HW Flow Control mode (both CTS and RTS) +1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n +1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 CTSE LL_USART_SetHWFlowCtrl +1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param HardwareFlowControl This parameter can be one of the following values: +1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_NONE +1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS +1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_CTS +1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS_CTS +1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) +1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + ARM GAS /tmp/ccWQNJQt.s page 364 + + +1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return HW Flow Control configuration (both CTS and RTS) +1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n +1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 CTSE LL_USART_GetHWFlowCtrl +1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_NONE +1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS +1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_CTS +1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS_CTS +1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) +1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable One bit sampling method +1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp +1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) +1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); +1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable One bit sampling method +1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp +1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) +1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); +1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if One bit sampling method is enabled +1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp +1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) +1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); +1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Overrun detection +1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect + ARM GAS /tmp/ccWQNJQt.s page 365 + + +1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) +1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); +1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Overrun detection +1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect +1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) +1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); +1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Overrun detection is enabled +1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect +1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) +1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) +1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS) +1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) +1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. +1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUS LL_USART_SetWKUPType +1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Type This parameter can be one of the following values: +1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_ADDRESS +1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_STARTBIT +1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_RXNE +1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) +1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type); +1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) +1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not +1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. +1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUS LL_USART_GetWKUPType +1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_ADDRESS + ARM GAS /tmp/ccWQNJQt.s page 366 + + +1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_STARTBIT +1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_RXNE +1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx) +1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); +1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */ +1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ +1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure USART BRR register for achieving expected Baud Rate value. +1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Compute and set USARTDIV value in BRR Register (full BRR content) +1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values +1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Peripheral clock and Baud rate values provided as function parameters should be valid +1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (Baud rate value != 0) +1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. +1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll BRR BRR LL_USART_SetBaudRate +1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PeriphClk Peripheral Clock +1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: +1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 +1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 +1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BaudRate Baud Rate +1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverS +1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t BaudRate) +1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t usartdiv; +1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t brrtemp; +1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (OverSampling == LL_USART_OVERSAMPLING_8) +1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); +1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrtemp = usartdiv & 0xFFF0U; +1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); +1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->BRR = brrtemp; +1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else +1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); +1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return current Baud Rate value, according to USARTDIV present in BRR register +1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (full BRR content), and to used Peripheral Clock and Oversampling mode values +1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be ret +1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. +1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll BRR BRR LL_USART_GetBaudRate +1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PeriphClk Peripheral Clock +1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: +1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 +1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 +1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Baud Rate + ARM GAS /tmp/ccWQNJQt.s page 367 + + +1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint +1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t usartdiv; +1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t brrresult = 0x0U; +1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** usartdiv = USARTx->BRR; +1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (usartdiv == 0U) +1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Do not perform a division by 0 */ +1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else if (OverSampling == LL_USART_OVERSAMPLING_8) +1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; +1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (usartdiv != 0U) +1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrresult = (PeriphClk * 2U) / usartdiv; +1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else +1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if ((usartdiv & 0xFFFFU) != 0U) +1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrresult = PeriphClk / usartdiv; +1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (brrresult); +1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Receiver Time Out Value (expressed in nb of bits duration) +1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR RTO LL_USART_SetRxTimeout +1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF +1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout) +1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); +1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Get Receiver Time Out Value (expressed in nb of bits duration) +1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR RTO LL_USART_GetRxTimeout +1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF +1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) +1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); +1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Block Length value in reception +1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR BLEN LL_USART_SetBlockLength +1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + ARM GAS /tmp/ccWQNJQt.s page 368 + + +1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF +1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) +1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); +1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Get Block Length value in reception +1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR BLEN LL_USART_GetBlockLength +1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0xFF +1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) +1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); +1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature +1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable IrDA mode +1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not +1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. +1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IREN LL_USART_EnableIrda +1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) +1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_IREN); +1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable IrDA mode +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not +1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. +1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IREN LL_USART_DisableIrda +1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) +1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); +1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if IrDA mode is enabled +1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not +1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. + ARM GAS /tmp/ccWQNJQt.s page 369 + + +1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IREN LL_USART_IsEnabledIrda +1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) +1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); +1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure IrDA Power Mode (Normal or Low Power) +1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not +1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. +1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode +1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PowerMode This parameter can be one of the following values: +1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_IRDA_POWER_NORMAL +1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_IRDA_POWER_LOW +1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) +1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); +1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) +1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not +1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. +1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode +1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_IRDA_POWER_NORMAL +1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE +1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) +1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); +1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Irda prescaler value, used for dividing the USART clock source +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * to achieve the Irda Low Power frequency (8 bits value) +1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not +1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. +1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler +1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF +1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Irda prescaler value, used for dividing the USART clock source + ARM GAS /tmp/ccWQNJQt.s page 370 + + +1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * to achieve the Irda Low Power frequency (8 bits value) +1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not +1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. +1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler +1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) +1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) +1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feat +1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Smartcard NACK transmission +1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK +1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) +1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_NACK); +1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Smartcard NACK transmission +1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK +1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) +1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); +1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Smartcard NACK transmission is enabled +1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK +1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) +1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); + ARM GAS /tmp/ccWQNJQt.s page 371 + + +1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Smartcard mode +1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCEN LL_USART_EnableSmartcard +1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) +1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_SCEN); +1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Smartcard mode +1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCEN LL_USART_DisableSmartcard +1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) +1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); +1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Smartcard mode is enabled +1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard +1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) +1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); +1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) +1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mo +1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * In transmission mode, it specifies the number of automatic retransmission retries, befo +1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * generating a transmission error (FE bit set). +1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * In reception mode, it specifies the number or erroneous reception trials, before genera +1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * reception error (RXNE and PE bits set) +1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount +1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7 +1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryC +1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + ARM GAS /tmp/ccWQNJQt.s page 372 + + +1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); +1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) +1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount +1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) +1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) +1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); +1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Smartcard prescaler value, used for dividing the USART clock +1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * source to provide the SMARTCARD Clock (5 bits value) +1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler +1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 +1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Smartcard prescaler value, used for dividing the USART clock +1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * source to provide the SMARTCARD Clock (5 bits value) +1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler +1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) +1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) +1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods +2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (GT[7:0] bits : Guard time value) +2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime +2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF +2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) +2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + ARM GAS /tmp/ccWQNJQt.s page 373 + + +2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); +2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods +2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (GT[7:0] bits : Guard time value) +2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime +2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) +2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) +2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); +2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex f +2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Single Wire Half-Duplex mode +2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not +2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. +2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex +2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) +2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Single Wire Half-Duplex mode +2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not +2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. +2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex +2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) +2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); +2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Single Wire Half-Duplex mode is enabled +2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not +2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. +2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex +2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + ARM GAS /tmp/ccWQNJQt.s page 374 + + +2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) +2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); +2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature +2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set LIN Break Detection Length +2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen +2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LINBDLength This parameter can be one of the following values: +2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_10B +2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_11B +2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) +2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); +2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return LIN Break Detection Length +2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen +2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_10B +2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_11B +2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) +2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); +2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable LIN mode +2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_EnableLIN +2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) +2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_LINEN); + ARM GAS /tmp/ccWQNJQt.s page 375 + + +2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable LIN mode +2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_DisableLIN +2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) +2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); +2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if LIN mode is enabled +2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN +2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) +2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); +2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature +2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits) +2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not +2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. +2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime +2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Time Value between Min_Data=0 and Max_Data=31 +2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) +2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); +2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return DEDT (Driver Enable De-Assertion Time) +2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not +2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. +2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime +2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + ARM GAS /tmp/ccWQNJQt.s page 376 + + +2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) +2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). +2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not +2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. +2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime +2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Time Value between Min_Data=0 and Max_Data=31 +2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) +2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); +2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return DEAT (Driver Enable Assertion Time) +2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not +2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. +2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime +2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 +2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) +2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Driver Enable (DE) Mode +2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not +2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. +2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEM LL_USART_EnableDEMode +2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) +2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_DEM); +2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Driver Enable (DE) Mode +2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not +2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. +2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEM LL_USART_DisableDEMode +2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) +2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_DEM); + ARM GAS /tmp/ccWQNJQt.s page 377 + + +2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Driver Enable (DE) Mode is enabled +2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not +2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. +2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode +2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) +2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); +2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select Driver Enable Polarity +2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not +2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. +2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity +2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Polarity This parameter can be one of the following values: +2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_HIGH +2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_LOW +2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity) +2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity); +2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Driver Enable Polarity +2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not +2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. +2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity +2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_HIGH +2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_LOW +2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) +2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); +2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services +2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) +2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In UART mode, the following bits must be kept cleared: + ARM GAS /tmp/ccWQNJQt.s page 378 + + +2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, +2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - CLKEN bit in the USART_CR2 register, +2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, +2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, +2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. +2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : +2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function +2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function +2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function +2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function +2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function +2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Asynchronous Mode +2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, ...) should be set using +2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions +2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n +2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigAsyncMode\n +2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigAsyncMode\n +2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigAsyncMode\n +2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigAsyncMode +2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) +2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Asynchronous mode, the following bits must be kept cleared: +2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN, CLKEN bits in the USART_CR2 register, +2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN, IREN and HDSEL bits in the USART_CR3 register. +2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); +2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); +2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Synchronous Mode +2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In Synchronous mode, the following bits must be kept cleared: +2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, +2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, +2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, +2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. +2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also sets the USART in Synchronous mode. +2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not +2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. +2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : +2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function +2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function +2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function +2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function +2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function +2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Synchronous Mode +2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using +2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions +2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n +2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigSyncMode\n +2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigSyncMode\n +2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigSyncMode\n +2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigSyncMode +2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + ARM GAS /tmp/ccWQNJQt.s page 379 + + +2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) +2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Synchronous mode, the following bits must be kept cleared: +2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN bit in the USART_CR2 register, +2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN, IREN and HDSEL bits in the USART_CR3 register. +2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); +2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); +2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in Synchronous mode */ +2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in LIN Mode +2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In LIN mode, the following bits must be kept cleared: +2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - STOP and CLKEN bits in the USART_CR2 register, +2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, +2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, +2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. +2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also set the UART/USART in LIN mode. +2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : +2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function +2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function +2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function +2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function +2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function +2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function +2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to LIN Mode +2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using +2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions +2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n +2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigLINMode\n +2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 LINEN LL_USART_ConfigLINMode\n +2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigLINMode\n +2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigLINMode\n +2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigLINMode +2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) +2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In LIN mode, the following bits must be kept cleared: +2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - STOP and CLKEN bits in the USART_CR2 register, +2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - IREN, SCEN and HDSEL bits in the USART_CR3 register. +2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); +2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); +2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Set the UART/USART in LIN mode */ +2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_LINEN); +2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode + ARM GAS /tmp/ccWQNJQt.s page 380 + + +2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In Half Duplex mode, the following bits must be kept cleared: +2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, +2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - CLKEN bit in the USART_CR2 register, +2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, +2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, +2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also sets the UART/USART in Half Duplex mode. +2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not +2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. +2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : +2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function +2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function +2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function +2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function +2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function +2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Half Duplex Mode +2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, ...) should be set using +2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions +2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n +2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n +2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n +2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n +2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigHalfDuplexMode +2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) +2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Half Duplex mode, the following bits must be kept cleared: +2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN and CLKEN bits in the USART_CR2 register, +2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN and IREN bits in the USART_CR3 register. +2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); +2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); +2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in Half Duplex mode */ +2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Smartcard Mode +2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In Smartcard mode, the following bits must be kept cleared: +2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, +2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, +2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. +2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also configures Stop bits to 1.5 bits and +2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * sets the USART in Smartcard mode (SCEN bit). +2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Clock Output is also enabled (CLKEN). +2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : +2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function +2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function +2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function +2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function +2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function +2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function +2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Smartcard Mode +2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, ...) should be set using + ARM GAS /tmp/ccWQNJQt.s page 381 + + +2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions +2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n +2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigSmartcardMode\n +2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigSmartcardMode\n +2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigSmartcardMode\n +2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigSmartcardMode +2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) +2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Smartcard mode, the following bits must be kept cleared: +2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN bit in the USART_CR2 register, +2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - IREN and HDSEL bits in the USART_CR3 register. +2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); +2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); +2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Configure Stop bits to 1.5 bits */ +2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Synchronous mode is activated by default */ +2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); +2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in Smartcard mode */ +2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_SCEN); +2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Irda Mode +2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In IRDA mode, the following bits must be kept cleared: +2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, +2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - STOP and CLKEN bits in the USART_CR2 register, +2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, +2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. +2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also sets the UART/USART in IRDA mode (IREN bit). +2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not +2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. +2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : +2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function +2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function +2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function +2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function +2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function +2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function +2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Irda Mode +2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Power mode, ...) should be set using +2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions +2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n +2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigIrdaMode\n +2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigIrdaMode\n +2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigIrdaMode\n +2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigIrdaMode\n +2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigIrdaMode +2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) +2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In IRDA mode, the following bits must be kept cleared: +2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN, STOP and CLKEN bits in the USART_CR2 register, + ARM GAS /tmp/ccWQNJQt.s page 382 + + +2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN and HDSEL bits in the USART_CR3 register. +2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); +2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); +2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in IRDA mode */ +2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_IREN); +2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Multi processor Mode +2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (several USARTs connected in a network, one of the USARTs can be the master, +2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * its TX output connected to the RX inputs of the other slaves USARTs). +2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In MultiProcessor mode, the following bits must be kept cleared: +2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, +2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - CLKEN bit in the USART_CR2 register, +2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, +2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, +2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. +2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : +2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function +2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function +2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function +2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function +2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function +2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Multi processor Mode +2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Wake Up Method, Node address, ...) should be set using +2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions +2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n +2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n +2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigMultiProcessMode\n +2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n +2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigMultiProcessMode +2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) +2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Multi Processor mode, the following bits must be kept cleared: +2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN and CLKEN bits in the USART_CR2 register, +2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - IREN, SCEN and HDSEL bits in the USART_CR3 register. +2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); +2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); +2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_FLAG_Management FLAG_Management +2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Parity Error Flag is set or not +2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR PE LL_USART_IsActiveFlag_PE +2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + ARM GAS /tmp/ccWQNJQt.s page 383 + + +2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) +2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); +2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Framing Error Flag is set or not +2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR FE LL_USART_IsActiveFlag_FE +2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) +2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); +2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Noise error detected Flag is set or not +2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR NE LL_USART_IsActiveFlag_NE +2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) +2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); +2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART OverRun Error Flag is set or not +2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE +2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) +2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); +2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART IDLE line detected Flag is set or not +2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE +2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) +2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); +2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Read Data Register Not Empty Flag is set or not +2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR RXNE LL_USART_IsActiveFlag_RXNE +2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + ARM GAS /tmp/ccWQNJQt.s page 384 + + +2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(const USART_TypeDef *USARTx) +2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL); +2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmission Complete Flag is set or not +2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TC LL_USART_IsActiveFlag_TC +2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) +2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); +2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmit Data Register Empty Flag is set or not +2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TXE LL_USART_IsActiveFlag_TXE +2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx) +2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL); +2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART LIN Break Detection Flag is set or not +2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD +2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) +2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); +2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART CTS interrupt Flag is set or not +2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS +2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) +2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); +2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART CTS Flag is set or not +2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. + ARM GAS /tmp/ccWQNJQt.s page 385 + + +2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS +2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) +2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); +2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receiver Time Out Flag is set or not +2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO +2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) +2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); +2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART End Of Block Flag is set or not +2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB +2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) +2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); +2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Auto-Baud Rate Error Flag is set or not +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or +2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE +2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) +2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); +2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Auto-Baud Rate Flag is set or not +2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or +2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR +2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) +2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); + ARM GAS /tmp/ccWQNJQt.s page 386 + + +2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Busy Flag is set or not +2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY +2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) +2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); +2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Character Match Flag is set or not +2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM +2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) +2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); +2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Send Break Flag is set or not +2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK +2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) +2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); +2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not +2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU +2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) +2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); +2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) +2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) +2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Wake Up from stop mode Flag is set or not +2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not +2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. +2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP +2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx) + ARM GAS /tmp/ccWQNJQt.s page 387 + + +2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); +2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ +2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ +2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not +2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK +2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) +2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); +2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_ISR_REACK) +2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receive Enable Acknowledge Flag is set or not +2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK +2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) +2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_ISR_REACK */ +2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) +2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ +2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not +2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT +2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) +2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); +2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ +2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Parity Error Flag +2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR PECF LL_USART_ClearFlag_PE +2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) +2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_PECF); +2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Framing Error Flag + ARM GAS /tmp/ccWQNJQt.s page 388 + + +2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR FECF LL_USART_ClearFlag_FE +2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) +2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_FECF); +2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Noise Error detected Flag +2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR NCF LL_USART_ClearFlag_NE +2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) +2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_NCF); +2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear OverRun Error Flag +2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE +2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) +2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_ORECF); +2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear IDLE line detected Flag +2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE +2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) +2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); +2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Transmission Complete Flag +2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR TCCF LL_USART_ClearFlag_TC +2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) +2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_TCCF); +2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) +2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ +2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Smartcard Transmission Complete Before Guard Time Flag + ARM GAS /tmp/ccWQNJQt.s page 389 + + +2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT +2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) +2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF); +2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ +2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear LIN Break Detection Flag +2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD +2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) +2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_LBDCF); +2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear CTS Interrupt Flag +2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS +2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) +2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_CTSCF); +2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Receiver Time Out Flag +2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO +2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) +2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_RTOCF); +2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear End Of Block Flag +2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB +2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) +2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + ARM GAS /tmp/ccWQNJQt.s page 390 + + +2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); +2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Character Match Flag +2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR CMCF LL_USART_ClearFlag_CM +2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) +2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_CMCF); +2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) +2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) +2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Wake Up from stop mode Flag +3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not +3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. +3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP +3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) +3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_WUCF); +3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ +3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ +3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_IT_Management IT_Management +3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable IDLE Interrupt +3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE +3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) +3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); +3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable RX Not Empty Interrupt +3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE +3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) + ARM GAS /tmp/ccWQNJQt.s page 391 + + +3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); +3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Transmission Complete Interrupt +3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TCIE LL_USART_EnableIT_TC +3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) +3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); +3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable TX Empty Interrupt +3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE +3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) +3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE); +3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Parity Error Interrupt +3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PEIE LL_USART_EnableIT_PE +3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) +3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); +3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Character Match Interrupt +3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 CMIE LL_USART_EnableIT_CM +3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) +3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE); +3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Receiver Timeout Interrupt +3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO +3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) +3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE); + ARM GAS /tmp/ccWQNJQt.s page 392 + + +3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable End Of Block Interrupt +3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB +3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) +3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE); +3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable LIN Break Detection Interrupt +3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD +3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) +3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_LBDIE); +3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Error Interrupt +3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a fram +3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). +3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 0: Interrupt is inhibited +3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. +3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR +3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) +3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); +3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable CTS Interrupt +3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS +3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) +3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); +3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) + ARM GAS /tmp/ccWQNJQt.s page 393 + + +3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) +3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Wake Up from Stop Mode Interrupt +3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not +3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. +3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP +3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) +3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE); +3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ +3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ +3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) +3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ +3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt +3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT +3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) +3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ +3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable IDLE Interrupt +3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE +3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) +3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); +3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable RX Not Empty Interrupt +3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE +3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) +3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); +3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Transmission Complete Interrupt +3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TCIE LL_USART_DisableIT_TC + ARM GAS /tmp/ccWQNJQt.s page 394 + + +3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) +3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); +3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable TX Empty Interrupt +3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE +3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) +3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); +3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Parity Error Interrupt +3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PEIE LL_USART_DisableIT_PE +3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) +3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); +3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Character Match Interrupt +3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 CMIE LL_USART_DisableIT_CM +3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) +3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); +3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Receiver Timeout Interrupt +3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO +3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) +3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); +3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable End Of Block Interrupt +3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB + ARM GAS /tmp/ccWQNJQt.s page 395 + + +3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) +3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); +3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable LIN Break Detection Interrupt +3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD +3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) +3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); +3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Error Interrupt +3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a fram +3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). +3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 0: Interrupt is inhibited +3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. +3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR +3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) +3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); +3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable CTS Interrupt +3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS +3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) +3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); +3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) +3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) +3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Wake Up from Stop Mode Interrupt +3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not +3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. +3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP +3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + ARM GAS /tmp/ccWQNJQt.s page 396 + + +3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) +3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); +3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ +3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ +3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) +3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ +3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt +3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT +3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) +3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ +3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART IDLE Interrupt source is enabled or disabled. +3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE +3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) +3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); +3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. +3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE +3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(const USART_TypeDef *USARTx) +3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1U : 0U); +3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. +3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC +3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) +3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); +3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + ARM GAS /tmp/ccWQNJQt.s page 397 + + +3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART TX Empty Interrupt is enabled or disabled. +3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE +3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(const USART_TypeDef *USARTx) +3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1U : 0U); +3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Parity Error Interrupt is enabled or disabled. +3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE +3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) +3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); +3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Character Match Interrupt is enabled or disabled. +3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM +3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) +3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); +3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled. +3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO +3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) +3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); +3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART End Of Block Interrupt is enabled or disabled. +3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB +3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) +3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); +3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + ARM GAS /tmp/ccWQNJQt.s page 398 + + +3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. +3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD +3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) +3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); +3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Error Interrupt is enabled or disabled. +3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR +3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) +3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); +3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART CTS Interrupt is enabled or disabled. +3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS +3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) +3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); +3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) +3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) +3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. +3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not +3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. +3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP +3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx) +3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); +3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ +3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ +3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) +3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ + ARM GAS /tmp/ccWQNJQt.s page 399 + + +3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or +3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT +3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) +3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); +3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ +3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_DMA_Management DMA_Management +3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable DMA Mode for reception +3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX +3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) +3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); +3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable DMA Mode for reception +3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX +3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) +3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); +3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if DMA Mode is enabled for reception +3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX +3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) +3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); +3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable DMA Mode for transmission + ARM GAS /tmp/ccWQNJQt.s page 400 + + +3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX +3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) + 3999 .loc 7 3556 22 view .LVU1318 + 4000 .L132: +3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); + 4001 .loc 7 3558 3 discriminator 1 view .LVU1319 + 4002 .LBB458: + 4003 .loc 7 3558 3 discriminator 1 view .LVU1320 + 4004 .loc 7 3558 3 discriminator 1 view .LVU1321 + 4005 .loc 7 3558 3 discriminator 1 view .LVU1322 + 4006 .LBB459: + 4007 .LBI459: + 4008 .file 8 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + ARM GAS /tmp/ccWQNJQt.s page 401 + + + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + ARM GAS /tmp/ccWQNJQt.s page 402 + + + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccWQNJQt.s page 403 + + + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccWQNJQt.s page 404 + + + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccWQNJQt.s page 405 + + + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccWQNJQt.s page 406 + + + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + ARM GAS /tmp/ccWQNJQt.s page 407 + + + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + ARM GAS /tmp/ccWQNJQt.s page 408 + + + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccWQNJQt.s page 409 + + + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + ARM GAS /tmp/ccWQNJQt.s page 410 + + + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccWQNJQt.s page 411 + + + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + ARM GAS /tmp/ccWQNJQt.s page 412 + + + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccWQNJQt.s page 413 + + + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + ARM GAS /tmp/ccWQNJQt.s page 414 + + + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccWQNJQt.s page 415 + + + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 881:Drivers/CMSIS/Include/cmsis_gcc.h **** + 882:Drivers/CMSIS/Include/cmsis_gcc.h **** + 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier + 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. + 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) + 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); + 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 892:Drivers/CMSIS/Include/cmsis_gcc.h **** + 893:Drivers/CMSIS/Include/cmsis_gcc.h **** + 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) + ARM GAS /tmp/ccWQNJQt.s page 416 + + + 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 + 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) + 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); + 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 906:Drivers/CMSIS/Include/cmsis_gcc.h **** + 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 911:Drivers/CMSIS/Include/cmsis_gcc.h **** + 912:Drivers/CMSIS/Include/cmsis_gcc.h **** + 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes + 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) + 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 922:Drivers/CMSIS/Include/cmsis_gcc.h **** + 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 926:Drivers/CMSIS/Include/cmsis_gcc.h **** + 927:Drivers/CMSIS/Include/cmsis_gcc.h **** + 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam + 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); + 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; + 940:Drivers/CMSIS/Include/cmsis_gcc.h **** + 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 945:Drivers/CMSIS/Include/cmsis_gcc.h **** + 946:Drivers/CMSIS/Include/cmsis_gcc.h **** + 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) + 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v + 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate + 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate + 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value + ARM GAS /tmp/ccWQNJQt.s page 417 + + + 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) + 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; + 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) + 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; + 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); + 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 963:Drivers/CMSIS/Include/cmsis_gcc.h **** + 964:Drivers/CMSIS/Include/cmsis_gcc.h **** + 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint + 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. + 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula + 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. + 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break + 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) + 973:Drivers/CMSIS/Include/cmsis_gcc.h **** + 974:Drivers/CMSIS/Include/cmsis_gcc.h **** + 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value + 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. + 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) + 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 984:Drivers/CMSIS/Include/cmsis_gcc.h **** + 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + 991:Drivers/CMSIS/Include/cmsis_gcc.h **** + 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ + 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) + 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; + 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; + 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; + 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ +1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; +1002:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1003:Drivers/CMSIS/Include/cmsis_gcc.h **** +1004:Drivers/CMSIS/Include/cmsis_gcc.h **** +1005:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1006:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Count leading zeros +1007:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Counts the number of leading zeros of a data value. +1008:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to count the leading zeros +1009:Drivers/CMSIS/Include/cmsis_gcc.h **** \return number of leading zeros in value + ARM GAS /tmp/ccWQNJQt.s page 418 + + +1010:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1011:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CLZ (uint8_t)__builtin_clz +1012:Drivers/CMSIS/Include/cmsis_gcc.h **** +1013:Drivers/CMSIS/Include/cmsis_gcc.h **** +1014:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +1015:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ +1016:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ +1017:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +1018:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1019:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (8 bit) +1020:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 8 bit value. +1021:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data +1022:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) +1023:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1024:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +1025:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1026:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; +1027:Drivers/CMSIS/Include/cmsis_gcc.h **** +1028:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) +1029:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +1030:Drivers/CMSIS/Include/cmsis_gcc.h **** #else +1031:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not +1032:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. +1033:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1034:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +1035:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1036:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */ +1037:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1038:Drivers/CMSIS/Include/cmsis_gcc.h **** +1039:Drivers/CMSIS/Include/cmsis_gcc.h **** +1040:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1041:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (16 bit) +1042:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 16 bit values. +1043:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data +1044:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) +1045:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1046:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +1047:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1048:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; +1049:Drivers/CMSIS/Include/cmsis_gcc.h **** +1050:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) +1051:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +1052:Drivers/CMSIS/Include/cmsis_gcc.h **** #else +1053:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not +1054:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. +1055:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1056:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +1057:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1058:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */ +1059:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1060:Drivers/CMSIS/Include/cmsis_gcc.h **** +1061:Drivers/CMSIS/Include/cmsis_gcc.h **** +1062:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1063:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (32 bit) +1064:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 32 bit values. +1065:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data +1066:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) + ARM GAS /tmp/ccWQNJQt.s page 419 + + +1067:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) + 4009 .loc 8 1068 31 view .LVU1323 + 4010 .LBB460: +1069:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 4011 .loc 8 1070 5 view .LVU1324 +1071:Drivers/CMSIS/Include/cmsis_gcc.h **** +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 4012 .loc 8 1072 4 view .LVU1325 + 4013 00e8 784A ldr r2, .L141+76 + 4014 00ea 02F10803 add r3, r2, #8 + 4015 .syntax unified + 4016 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 4017 00ee 53E8003F ldrex r3, [r3] + 4018 @ 0 "" 2 + 4019 .LVL282: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4020 .loc 8 1073 4 view .LVU1326 + 4021 .loc 8 1073 4 is_stmt 0 view .LVU1327 + 4022 .thumb + 4023 .syntax unified + 4024 .LBE460: + 4025 .LBE459: + 4026 .loc 7 3558 3 discriminator 1 view .LVU1328 + 4027 00f2 43F08003 orr r3, r3, #128 + 4028 .LVL283: + 4029 .loc 7 3558 3 is_stmt 1 discriminator 1 view .LVU1329 + 4030 .LBB461: + 4031 .LBI461: +1074:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1075:Drivers/CMSIS/Include/cmsis_gcc.h **** +1076:Drivers/CMSIS/Include/cmsis_gcc.h **** +1077:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1078:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (8 bit) +1079:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 8 bit values. +1080:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store +1081:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location +1082:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded +1083:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed +1084:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1085:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +1086:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1087:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; +1088:Drivers/CMSIS/Include/cmsis_gcc.h **** +1089:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); +1090:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); +1091:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1092:Drivers/CMSIS/Include/cmsis_gcc.h **** +1093:Drivers/CMSIS/Include/cmsis_gcc.h **** +1094:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1095:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (16 bit) +1096:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 16 bit values. +1097:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store +1098:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location +1099:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded +1100:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed + ARM GAS /tmp/ccWQNJQt.s page 420 + + +1101:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1102:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +1103:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1104:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; +1105:Drivers/CMSIS/Include/cmsis_gcc.h **** +1106:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); +1107:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); +1108:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1109:Drivers/CMSIS/Include/cmsis_gcc.h **** +1110:Drivers/CMSIS/Include/cmsis_gcc.h **** +1111:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1112:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (32 bit) +1113:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 32 bit values. +1114:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store +1115:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location +1116:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded +1117:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed +1118:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) + 4032 .loc 8 1119 31 view .LVU1330 + 4033 .LBB462: +1120:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 4034 .loc 8 1121 4 view .LVU1331 +1122:Drivers/CMSIS/Include/cmsis_gcc.h **** +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 4035 .loc 8 1123 4 view .LVU1332 + 4036 00f6 0832 adds r2, r2, #8 + 4037 .syntax unified + 4038 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 4039 00f8 42E80031 strex r1, r3, [r2] + 4040 @ 0 "" 2 + 4041 .LVL284: +1124:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4042 .loc 8 1124 4 view .LVU1333 + 4043 .loc 8 1124 4 is_stmt 0 view .LVU1334 + 4044 .thumb + 4045 .syntax unified + 4046 .LBE462: + 4047 .LBE461: + 4048 .loc 7 3558 3 discriminator 1 view .LVU1335 + 4049 00fc 0029 cmp r1, #0 + 4050 00fe F3D1 bne .L132 + 4051 .LBE458: + 4052 .loc 7 3558 3 is_stmt 1 discriminator 2 view .LVU1336 + 4053 .LVL285: + 4054 .loc 7 3558 3 is_stmt 0 discriminator 2 view .LVU1337 + 4055 .LBE457: +1937:Src/main.c **** LL_DMA_EnableIT_TE(DMA2, LL_DMA_STREAM_7); + 4056 .loc 1 1937 3 is_stmt 1 view .LVU1338 + 4057 .LBB463: + 4058 .LBI463: +2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 direct mode error flag. +2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 + ARM GAS /tmp/ccWQNJQt.s page 421 + + +2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) +2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0); +2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 direct mode error flag. +2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 +2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) +2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1); +2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 direct mode error flag. +2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 +2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) +2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2); +2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 direct mode error flag. +2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 +2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) +2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3); +2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 direct mode error flag. +2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 +2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) +2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4); +2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 direct mode error flag. +2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 +2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + ARM GAS /tmp/ccWQNJQt.s page 422 + + +2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) +2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5); +2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 direct mode error flag. +2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 +2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) +2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6); +2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 direct mode error flag. +2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 +2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) +2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7); +2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 FIFO error flag. +2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 +2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) +2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0); +2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 FIFO error flag. +2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 +2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) +2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1); +2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 FIFO error flag. +2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 +2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) + ARM GAS /tmp/ccWQNJQt.s page 423 + + +2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2); +2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 FIFO error flag. +2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 +2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) +2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3); +2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 FIFO error flag. +2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 +2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) +2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4); +2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 FIFO error flag. +2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 +2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) +2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5); +2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 FIFO error flag. +2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 +2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) +2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6); +2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 FIFO error flag. +2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 +2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) +2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7); + ARM GAS /tmp/ccWQNJQt.s page 424 + + +2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} +2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_IT_Management IT_Management +2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ +2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Half transfer interrupt. +2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR HTIE LL_DMA_EnableIT_HT +2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA +2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Transfer error interrupt. +2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR TEIE LL_DMA_EnableIT_TE +2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA +2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Transfer complete interrupt. +2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR TCIE LL_DMA_EnableIT_TC +2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + ARM GAS /tmp/ccWQNJQt.s page 425 + + +2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) + 4059 .loc 6 2609 22 view .LVU1339 + 4060 .LBB464: +2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA + 4061 .loc 6 2611 3 view .LVU1340 + 4062 0100 734B ldr r3, .L141+80 + 4063 0102 D3F8B820 ldr r2, [r3, #184] + 4064 0106 42F01002 orr r2, r2, #16 + 4065 010a C3F8B820 str r2, [r3, #184] + 4066 .LVL286: + 4067 .loc 6 2611 3 is_stmt 0 view .LVU1341 + 4068 .LBE464: + 4069 .LBE463: +1938:Src/main.c **** LL_DMA_ClearFlag_TC7(DMA2); + 4070 .loc 1 1938 3 is_stmt 1 view .LVU1342 + 4071 .LBB465: + 4072 .LBI465: +2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 4073 .loc 6 2589 22 view .LVU1343 + 4074 .LBB466: +2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 4075 .loc 6 2591 3 view .LVU1344 + 4076 010e D3F8B820 ldr r2, [r3, #184] + 4077 0112 42F00402 orr r2, r2, #4 + 4078 0116 C3F8B820 str r2, [r3, #184] + 4079 .LVL287: +2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 4080 .loc 6 2591 3 is_stmt 0 view .LVU1345 + 4081 .LBE466: + 4082 .LBE465: +1939:Src/main.c **** LL_DMA_ClearFlag_TE7(DMA2); + 4083 .loc 1 1939 3 is_stmt 1 view .LVU1346 + 4084 .LBB467: + 4085 .LBI467: +2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 4086 .loc 6 2277 22 view .LVU1347 + 4087 .LBB468: +2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 4088 .loc 6 2279 3 view .LVU1348 + 4089 011a 4FF00062 mov r2, #134217728 + 4090 011e DA60 str r2, [r3, #12] + 4091 .LVL288: +2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 4092 .loc 6 2279 3 is_stmt 0 view .LVU1349 + 4093 .LBE468: + 4094 .LBE467: +1940:Src/main.c **** LL_DMA_ConfigAddresses(DMA2, LL_DMA_STREAM_7, (uint32_t)&UART_DATA, LL_USART_DMA_GetRegAddr(USART + 4095 .loc 1 1940 3 is_stmt 1 view .LVU1350 + ARM GAS /tmp/ccWQNJQt.s page 426 + + + 4096 .LBB469: + 4097 .LBI469: +2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 4098 .loc 6 2365 22 view .LVU1351 + 4099 .LBB470: +2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 4100 .loc 6 2367 3 view .LVU1352 + 4101 0120 4FF00072 mov r2, #33554432 + 4102 0124 DA60 str r2, [r3, #12] + 4103 .LVL289: +2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 4104 .loc 6 2367 3 is_stmt 0 view .LVU1353 + 4105 .LBE470: + 4106 .LBE469: +1941:Src/main.c **** + 4107 .loc 1 1941 3 is_stmt 1 view .LVU1354 + 4108 0126 6B4A ldr r2, .L141+84 + 4109 .LVL290: + 4110 .LBB471: + 4111 .LBI471: + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 4112 .loc 6 621 26 view .LVU1355 + 4113 .LBB472: + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 4114 .loc 6 623 3 view .LVU1356 + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 4115 .loc 6 623 11 is_stmt 0 view .LVU1357 + 4116 0128 D3F8B830 ldr r3, [r3, #184] + 4117 012c 03F0C003 and r3, r3, #192 + 4118 .LVL291: + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 4119 .loc 6 623 11 view .LVU1358 + 4120 .LBE472: + 4121 .LBE471: + 4122 .LBB473: + 4123 .LBI473: +1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 4124 .loc 6 1425 22 is_stmt 1 view .LVU1359 + 4125 .LBB474: +1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 4126 .loc 6 1428 3 view .LVU1360 +1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 4127 .loc 6 1428 6 is_stmt 0 view .LVU1361 + 4128 0130 402B cmp r3, #64 + 4129 0132 7BD0 beq .L138 +1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR + 4130 .loc 6 1436 5 is_stmt 1 view .LVU1362 + 4131 0134 664B ldr r3, .L141+80 + 4132 .LVL292: +1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR + 4133 .loc 6 1436 5 is_stmt 0 view .LVU1363 + 4134 0136 C3F8C020 str r2, [r3, #192] +1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 4135 .loc 6 1437 5 is_stmt 1 view .LVU1364 + 4136 013a 674A ldr r2, .L141+88 + 4137 013c C3F8C420 str r2, [r3, #196] + 4138 .L134: + ARM GAS /tmp/ccWQNJQt.s page 427 + + + 4139 .LVL293: +1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 4140 .loc 6 1437 5 is_stmt 0 view .LVU1365 + 4141 .LBE474: + 4142 .LBE473: +1946:Src/main.c **** SD_SLIDE = 0; + 4143 .loc 1 1946 2 is_stmt 1 view .LVU1366 +1946:Src/main.c **** SD_SLIDE = 0; + 4144 .loc 1 1946 10 is_stmt 0 view .LVU1367 + 4145 0140 0024 movs r4, #0 + 4146 0142 664B ldr r3, .L141+92 + 4147 0144 1C60 str r4, [r3] +1947:Src/main.c **** //Reset all periphery + 4148 .loc 1 1947 2 is_stmt 1 view .LVU1368 +1947:Src/main.c **** //Reset all periphery + 4149 .loc 1 1947 11 is_stmt 0 view .LVU1369 + 4150 0146 664B ldr r3, .L141+96 + 4151 0148 1C60 str r4, [r3] +1949:Src/main.c **** HAL_GPIO_WritePin(EN_5V2_GPIO_Port, EN_5V2_Pin, GPIO_PIN_RESET); + 4152 .loc 1 1949 2 is_stmt 1 view .LVU1370 + 4153 014a 664F ldr r7, .L141+100 + 4154 014c 2246 mov r2, r4 + 4155 014e 0821 movs r1, #8 + 4156 0150 3846 mov r0, r7 + 4157 0152 FFF7FEFF bl HAL_GPIO_WritePin + 4158 .LVL294: +1950:Src/main.c **** HAL_GPIO_WritePin(LD1_EN_GPIO_Port, LD1_EN_Pin, GPIO_PIN_RESET); + 4159 .loc 1 1950 2 view .LVU1371 + 4160 0156 2246 mov r2, r4 + 4161 0158 0421 movs r1, #4 + 4162 015a 3846 mov r0, r7 + 4163 015c FFF7FEFF bl HAL_GPIO_WritePin + 4164 .LVL295: +1951:Src/main.c **** HAL_GPIO_WritePin(LD2_EN_GPIO_Port, LD2_EN_Pin, GPIO_PIN_RESET); + 4165 .loc 1 1951 2 view .LVU1372 + 4166 0160 DFF8A481 ldr r8, .L141+136 + 4167 0164 2246 mov r2, r4 + 4168 0166 4FF48071 mov r1, #256 + 4169 016a 4046 mov r0, r8 + 4170 016c FFF7FEFF bl HAL_GPIO_WritePin + 4171 .LVL296: +1952:Src/main.c **** HAL_GPIO_WritePin(REF0_EN_GPIO_Port, REF0_EN_Pin, GPIO_PIN_RESET); + 4172 .loc 1 1952 2 view .LVU1373 + 4173 0170 2246 mov r2, r4 + 4174 0172 1021 movs r1, #16 + 4175 0174 3846 mov r0, r7 + 4176 0176 FFF7FEFF bl HAL_GPIO_WritePin + 4177 .LVL297: +1953:Src/main.c **** HAL_GPIO_WritePin(REF2_ON_GPIO_Port, REF2_ON_Pin, GPIO_PIN_RESET); + 4178 .loc 1 1953 2 view .LVU1374 + 4179 017a 5B4E ldr r6, .L141+104 + 4180 017c 2246 mov r2, r4 + 4181 017e 4FF48061 mov r1, #1024 + 4182 0182 3046 mov r0, r6 + 4183 0184 FFF7FEFF bl HAL_GPIO_WritePin + 4184 .LVL298: +1954:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_RESET); + ARM GAS /tmp/ccWQNJQt.s page 428 + + + 4185 .loc 1 1954 2 view .LVU1375 + 4186 0188 584D ldr r5, .L141+108 + 4187 018a 2246 mov r2, r4 + 4188 018c 0821 movs r1, #8 + 4189 018e 2846 mov r0, r5 + 4190 0190 FFF7FEFF bl HAL_GPIO_WritePin + 4191 .LVL299: +1955:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_RESET); + 4192 .loc 1 1955 2 view .LVU1376 + 4193 0194 2246 mov r2, r4 + 4194 0196 0121 movs r1, #1 + 4195 0198 2846 mov r0, r5 + 4196 019a FFF7FEFF bl HAL_GPIO_WritePin + 4197 .LVL300: +1956:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_RESET); + 4198 .loc 1 1956 2 view .LVU1377 + 4199 019e 2246 mov r2, r4 + 4200 01a0 0221 movs r1, #2 + 4201 01a2 2846 mov r0, r5 + 4202 01a4 FFF7FEFF bl HAL_GPIO_WritePin + 4203 .LVL301: +1957:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_RESET); + 4204 .loc 1 1957 2 view .LVU1378 + 4205 01a8 2246 mov r2, r4 + 4206 01aa 4FF40061 mov r1, #2048 + 4207 01ae 3046 mov r0, r6 + 4208 01b0 FFF7FEFF bl HAL_GPIO_WritePin + 4209 .LVL302: +1958:Src/main.c **** // for (uint16_t i = 0; i < SD_Length; i++) + 4210 .loc 1 1958 2 view .LVU1379 + 4211 01b4 2246 mov r2, r4 + 4212 01b6 2021 movs r1, #32 + 4213 01b8 3846 mov r0, r7 + 4214 01ba FFF7FEFF bl HAL_GPIO_WritePin + 4215 .LVL303: +1968:Src/main.c **** HAL_GPIO_WritePin(ADC_MPD2_CS_GPIO_Port, ADC_MPD2_CS_Pin, GPIO_PIN_SET);//Enable SPI for MPhD2 ADC + 4216 .loc 1 1968 2 view .LVU1380 + 4217 01be 07F50067 add r7, r7, #2048 + 4218 01c2 0122 movs r2, #1 + 4219 01c4 4FF48061 mov r1, #1024 + 4220 01c8 3846 mov r0, r7 + 4221 01ca FFF7FEFF bl HAL_GPIO_WritePin + 4222 .LVL304: +1969:Src/main.c **** HAL_GPIO_WritePin(SPI4_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET); + 4223 .loc 1 1969 2 view .LVU1381 + 4224 01ce 484C ldr r4, .L141+112 + 4225 01d0 0122 movs r2, #1 + 4226 01d2 4021 movs r1, #64 + 4227 01d4 2046 mov r0, r4 + 4228 01d6 FFF7FEFF bl HAL_GPIO_WritePin + 4229 .LVL305: +1970:Src/main.c **** HAL_GPIO_WritePin(SPI5_CNV_GPIO_Port, SPI4_CNV_Pin, GPIO_PIN_SET); + 4230 .loc 1 1970 2 view .LVU1382 + 4231 01da 0122 movs r2, #1 + 4232 01dc 4FF48041 mov r1, #16384 + 4233 01e0 3846 mov r0, r7 + 4234 01e2 FFF7FEFF bl HAL_GPIO_WritePin + ARM GAS /tmp/ccWQNJQt.s page 429 + + + 4235 .LVL306: +1971:Src/main.c **** HAL_GPIO_WritePin(DAC_LD1_CS_GPIO_Port, DAC_LD1_CS_Pin, GPIO_PIN_SET);//End operation with LDAC1 + 4236 .loc 1 1971 2 view .LVU1383 + 4237 01e6 0122 movs r2, #1 + 4238 01e8 4FF48041 mov r1, #16384 + 4239 01ec 2046 mov r0, r4 + 4240 01ee FFF7FEFF bl HAL_GPIO_WritePin + 4241 .LVL307: +1972:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_SET);//End operation with LDAC2 + 4242 .loc 1 1972 2 view .LVU1384 + 4243 01f2 0122 movs r2, #1 + 4244 01f4 4FF48041 mov r1, #16384 + 4245 01f8 3046 mov r0, r6 + 4246 01fa FFF7FEFF bl HAL_GPIO_WritePin + 4247 .LVL308: +1973:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1 + 4248 .loc 1 1973 2 view .LVU1385 + 4249 01fe 0122 movs r2, #1 + 4250 0200 4021 movs r1, #64 + 4251 0202 2846 mov r0, r5 + 4252 0204 FFF7FEFF bl HAL_GPIO_WritePin + 4253 .LVL309: +1974:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);//End operation with TEC2 + 4254 .loc 1 1974 2 view .LVU1386 + 4255 0208 0122 movs r2, #1 + 4256 020a 4FF48051 mov r1, #4096 + 4257 020e 3046 mov r0, r6 + 4258 0210 FFF7FEFF bl HAL_GPIO_WritePin + 4259 .LVL310: +1975:Src/main.c **** + 4260 .loc 1 1975 2 view .LVU1387 + 4261 0214 0122 movs r2, #1 + 4262 0216 1021 movs r1, #16 + 4263 0218 2846 mov r0, r5 + 4264 021a FFF7FEFF bl HAL_GPIO_WritePin + 4265 .LVL311: +1979:Src/main.c **** { + 4266 .loc 1 1979 2 view .LVU1388 +1979:Src/main.c **** { + 4267 .loc 1 1979 6 is_stmt 0 view .LVU1389 + 4268 021e 0121 movs r1, #1 + 4269 0220 4046 mov r0, r8 + 4270 0222 FFF7FEFF bl HAL_GPIO_ReadPin + 4271 .LVL312: +1979:Src/main.c **** { + 4272 .loc 1 1979 5 discriminator 1 view .LVU1390 + 4273 0226 40B1 cbz r0, .L139 + 4274 .L129: +2009:Src/main.c **** static void Decode_uart(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ + 4275 .loc 1 2009 1 view .LVU1391 + 4276 0228 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 4277 .LVL313: + 4278 .L138: + 4279 .LBB476: + 4280 .LBB475: +1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, + 4281 .loc 6 1430 5 is_stmt 1 view .LVU1392 + ARM GAS /tmp/ccWQNJQt.s page 430 + + + 4282 022c 284B ldr r3, .L141+80 + 4283 .LVL314: +1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, + 4284 .loc 6 1430 5 is_stmt 0 view .LVU1393 + 4285 022e C3F8C420 str r2, [r3, #196] +1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 4286 .loc 6 1431 5 is_stmt 1 view .LVU1394 + 4287 0232 294A ldr r2, .L141+88 + 4288 0234 C3F8C020 str r2, [r3, #192] + 4289 0238 82E7 b .L134 + 4290 .LVL315: + 4291 .L139: +1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 4292 .loc 6 1431 5 is_stmt 0 view .LVU1395 + 4293 .LBE475: + 4294 .LBE476: +1982:Src/main.c **** { + 4295 .loc 1 1982 3 is_stmt 1 view .LVU1396 +1982:Src/main.c **** { + 4296 .loc 1 1982 7 is_stmt 0 view .LVU1397 + 4297 023a 4FF48071 mov r1, #256 + 4298 023e 2846 mov r0, r5 + 4299 0240 FFF7FEFF bl HAL_GPIO_ReadPin + 4300 .LVL316: +1982:Src/main.c **** { + 4301 .loc 1 1982 6 discriminator 1 view .LVU1398 + 4302 0244 0028 cmp r0, #0 + 4303 0246 EFD1 bne .L129 +1985:Src/main.c **** if (test == 0) //0 - suc + 4304 .loc 1 1985 4 is_stmt 1 view .LVU1399 +1985:Src/main.c **** if (test == 0) //0 - suc + 4305 .loc 1 1985 11 is_stmt 0 view .LVU1400 + 4306 0248 2A48 ldr r0, .L141+116 + 4307 024a FFF7FEFF bl Mount_SD + 4308 .LVL317: +1985:Src/main.c **** if (test == 0) //0 - suc + 4309 .loc 1 1985 9 discriminator 1 view .LVU1401 + 4310 024e 2A4B ldr r3, .L141+120 + 4311 0250 1860 str r0, [r3] +1986:Src/main.c **** { + 4312 .loc 1 1986 4 is_stmt 1 view .LVU1402 +1986:Src/main.c **** { + 4313 .loc 1 1986 7 is_stmt 0 view .LVU1403 + 4314 0252 18B1 cbz r0, .L140 + 4315 .L136: +1998:Src/main.c **** } + 4316 .loc 1 1998 4 is_stmt 1 view .LVU1404 +1998:Src/main.c **** } + 4317 .loc 1 1998 14 is_stmt 0 view .LVU1405 + 4318 0254 294B ldr r3, .L141+124 + 4319 0256 0122 movs r2, #1 + 4320 0258 1A70 strb r2, [r3] +2009:Src/main.c **** static void Decode_uart(uint16_t *Command, LDx_SetupTypeDef *LD1_curr_setup, LDx_SetupTypeDef *LD2_ + 4321 .loc 1 2009 1 view .LVU1406 + 4322 025a E5E7 b .L129 + 4323 .L140: +1989:Src/main.c **** test = Unmount_SD("/"); // 0 - succ + ARM GAS /tmp/ccWQNJQt.s page 431 + + + 4324 .loc 1 1989 5 is_stmt 1 view .LVU1407 +1989:Src/main.c **** test = Unmount_SD("/"); // 0 - succ + 4325 .loc 1 1989 12 is_stmt 0 view .LVU1408 + 4326 025c 1E23 movs r3, #30 + 4327 025e 1A46 mov r2, r3 + 4328 0260 2749 ldr r1, .L141+128 + 4329 0262 2848 ldr r0, .L141+132 + 4330 0264 FFF7FEFF bl Seek_Read_File + 4331 .LVL318: +1989:Src/main.c **** test = Unmount_SD("/"); // 0 - succ + 4332 .loc 1 1989 10 discriminator 1 view .LVU1409 + 4333 0268 234C ldr r4, .L141+120 + 4334 026a 2060 str r0, [r4] +1990:Src/main.c **** UART_rec_incr = 0; + 4335 .loc 1 1990 5 is_stmt 1 view .LVU1410 +1990:Src/main.c **** UART_rec_incr = 0; + 4336 .loc 1 1990 12 is_stmt 0 view .LVU1411 + 4337 026c 2148 ldr r0, .L141+116 + 4338 026e FFF7FEFF bl Unmount_SD + 4339 .LVL319: +1990:Src/main.c **** UART_rec_incr = 0; + 4340 .loc 1 1990 10 discriminator 1 view .LVU1412 + 4341 0272 2060 str r0, [r4] +1991:Src/main.c **** flg_tmt = 0;//Reset the timeout flag + 4342 .loc 1 1991 5 is_stmt 1 view .LVU1413 +1991:Src/main.c **** flg_tmt = 0;//Reset the timeout flag + 4343 .loc 1 1991 19 is_stmt 0 view .LVU1414 + 4344 0274 0023 movs r3, #0 + 4345 0276 084A ldr r2, .L141+24 + 4346 0278 1380 strh r3, [r2] @ movhi +1992:Src/main.c **** } + 4347 .loc 1 1992 5 is_stmt 1 view .LVU1415 +1992:Src/main.c **** } + 4348 .loc 1 1992 13 is_stmt 0 view .LVU1416 + 4349 027a 064A ldr r2, .L141+20 + 4350 027c 1370 strb r3, [r2] + 4351 027e E9E7 b .L136 + 4352 .L142: + 4353 .align 2 + 4354 .L141: + 4355 0280 00000000 .word TO6 + 4356 0284 00000000 .word TO7 + 4357 0288 00000000 .word TO7_before + 4358 028c 00000000 .word TO6_before + 4359 0290 00000000 .word TO6_uart + 4360 0294 00000000 .word flg_tmt + 4361 0298 00000000 .word UART_rec_incr + 4362 029c 00000000 .word fgoto + 4363 02a0 00000000 .word sizeoffile + 4364 02a4 00000000 .word u_tx_flg + 4365 02a8 00000000 .word u_rx_flg + 4366 02ac 00000000 .word Long_Data + 4367 02b0 00000000 .word Def_setup + 4368 02b4 00000000 .word LD1_def_setup + 4369 02b8 00000000 .word LD2_def_setup + 4370 02bc 00000000 .word Curr_setup + 4371 02c0 00000000 .word LD1_curr_setup + ARM GAS /tmp/ccWQNJQt.s page 432 + + + 4372 02c4 00000000 .word LD2_curr_setup + 4373 02c8 00100040 .word 1073745920 + 4374 02cc 00100140 .word 1073811456 + 4375 02d0 00640240 .word 1073898496 + 4376 02d4 00000000 .word UART_DATA + 4377 02d8 28100140 .word 1073811496 + 4378 02dc 00000000 .word SD_SEEK + 4379 02e0 00000000 .word SD_SLIDE + 4380 02e4 00080240 .word 1073874944 + 4381 02e8 00040240 .word 1073873920 + 4382 02ec 00000240 .word 1073872896 + 4383 02f0 00140240 .word 1073878016 + 4384 02f4 00000000 .word .LC0 + 4385 02f8 00000000 .word test + 4386 02fc 00000000 .word CPU_state + 4387 0300 00000000 .word COMMAND + 4388 0304 04000000 .word .LC1 + 4389 0308 000C0240 .word 1073875968 + 4390 .cfi_endproc + 4391 .LFE1207: + 4393 .section .text.Get_ADC,"ax",%progbits + 4394 .align 1 + 4395 .syntax unified + 4396 .thumb + 4397 .thumb_func + 4399 Get_ADC: + 4400 .LVL320: + 4401 .LFB1213: +2438:Src/main.c **** uint16_t OUT; + 4402 .loc 1 2438 1 is_stmt 1 view -0 + 4403 .cfi_startproc + 4404 @ args = 0, pretend = 0, frame = 0 + 4405 @ frame_needed = 0, uses_anonymous_args = 0 +2438:Src/main.c **** uint16_t OUT; + 4406 .loc 1 2438 1 is_stmt 0 view .LVU1418 + 4407 0000 10B5 push {r4, lr} + 4408 .LCFI40: + 4409 .cfi_def_cfa_offset 8 + 4410 .cfi_offset 4, -8 + 4411 .cfi_offset 14, -4 + 4412 0002 0024 movs r4, #0 +2439:Src/main.c **** switch (num) + 4413 .loc 1 2439 2 is_stmt 1 view .LVU1419 +2440:Src/main.c **** { + 4414 .loc 1 2440 2 view .LVU1420 + 4415 0004 0528 cmp r0, #5 + 4416 0006 2CD8 bhi .L152 + 4417 0008 DFE800F0 tbb [pc, r0] + 4418 .L146: + 4419 000c 03 .byte (.L151-.L146)/2 + 4420 000d 08 .byte (.L150-.L146)/2 + 4421 000e 12 .byte (.L149-.L146)/2 + 4422 000f 17 .byte (.L148-.L146)/2 + 4423 0010 1C .byte (.L147-.L146)/2 + 4424 0011 26 .byte (.L145-.L146)/2 + 4425 .p2align 1 + 4426 .L151: + ARM GAS /tmp/ccWQNJQt.s page 433 + + +2443:Src/main.c **** break; + 4427 .loc 1 2443 5 view .LVU1421 + 4428 0012 1548 ldr r0, .L154 + 4429 .LVL321: +2443:Src/main.c **** break; + 4430 .loc 1 2443 5 is_stmt 0 view .LVU1422 + 4431 0014 FFF7FEFF bl HAL_ADC_Start + 4432 .LVL322: +2444:Src/main.c **** case 1: + 4433 .loc 1 2444 4 is_stmt 1 view .LVU1423 + 4434 0018 2046 mov r0, r4 + 4435 .L144: + 4436 .LVL323: +2463:Src/main.c **** } + 4437 .loc 1 2463 2 view .LVU1424 +2464:Src/main.c **** + 4438 .loc 1 2464 1 is_stmt 0 view .LVU1425 + 4439 001a 10BD pop {r4, pc} + 4440 .LVL324: + 4441 .L150: +2446:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc1); // Get value adc + 4442 .loc 1 2446 5 is_stmt 1 view .LVU1426 + 4443 001c 124C ldr r4, .L154 + 4444 001e 6421 movs r1, #100 + 4445 0020 2046 mov r0, r4 + 4446 .LVL325: +2446:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc1); // Get value adc + 4447 .loc 1 2446 5 is_stmt 0 view .LVU1427 + 4448 0022 FFF7FEFF bl HAL_ADC_PollForConversion + 4449 .LVL326: +2447:Src/main.c **** break; + 4450 .loc 1 2447 9 is_stmt 1 view .LVU1428 +2447:Src/main.c **** break; + 4451 .loc 1 2447 15 is_stmt 0 view .LVU1429 + 4452 0026 2046 mov r0, r4 + 4453 0028 FFF7FEFF bl HAL_ADC_GetValue + 4454 .LVL327: +2447:Src/main.c **** break; + 4455 .loc 1 2447 13 discriminator 1 view .LVU1430 + 4456 002c 80B2 uxth r0, r0 + 4457 .LVL328: +2448:Src/main.c **** case 2: + 4458 .loc 1 2448 4 is_stmt 1 view .LVU1431 + 4459 002e F4E7 b .L144 + 4460 .LVL329: + 4461 .L149: +2450:Src/main.c **** break; + 4462 .loc 1 2450 5 view .LVU1432 + 4463 0030 0D48 ldr r0, .L154 + 4464 .LVL330: +2450:Src/main.c **** break; + 4465 .loc 1 2450 5 is_stmt 0 view .LVU1433 + 4466 0032 FFF7FEFF bl HAL_ADC_Stop + 4467 .LVL331: +2451:Src/main.c **** case 3: + 4468 .loc 1 2451 4 is_stmt 1 view .LVU1434 + 4469 0036 2046 mov r0, r4 + ARM GAS /tmp/ccWQNJQt.s page 434 + + + 4470 0038 EFE7 b .L144 + 4471 .LVL332: + 4472 .L148: +2453:Src/main.c **** break; + 4473 .loc 1 2453 5 view .LVU1435 + 4474 003a 0C48 ldr r0, .L154+4 + 4475 .LVL333: +2453:Src/main.c **** break; + 4476 .loc 1 2453 5 is_stmt 0 view .LVU1436 + 4477 003c FFF7FEFF bl HAL_ADC_Start + 4478 .LVL334: +2454:Src/main.c **** case 4: + 4479 .loc 1 2454 4 is_stmt 1 view .LVU1437 + 4480 0040 2046 mov r0, r4 + 4481 0042 EAE7 b .L144 + 4482 .LVL335: + 4483 .L147: +2456:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc3); // Get value adc + 4484 .loc 1 2456 5 view .LVU1438 + 4485 0044 094C ldr r4, .L154+4 + 4486 0046 6421 movs r1, #100 + 4487 0048 2046 mov r0, r4 + 4488 .LVL336: +2456:Src/main.c **** OUT = HAL_ADC_GetValue(&hadc3); // Get value adc + 4489 .loc 1 2456 5 is_stmt 0 view .LVU1439 + 4490 004a FFF7FEFF bl HAL_ADC_PollForConversion + 4491 .LVL337: +2457:Src/main.c **** break; + 4492 .loc 1 2457 9 is_stmt 1 view .LVU1440 +2457:Src/main.c **** break; + 4493 .loc 1 2457 15 is_stmt 0 view .LVU1441 + 4494 004e 2046 mov r0, r4 + 4495 0050 FFF7FEFF bl HAL_ADC_GetValue + 4496 .LVL338: +2457:Src/main.c **** break; + 4497 .loc 1 2457 13 discriminator 1 view .LVU1442 + 4498 0054 80B2 uxth r0, r0 + 4499 .LVL339: +2458:Src/main.c **** case 5: + 4500 .loc 1 2458 4 is_stmt 1 view .LVU1443 + 4501 0056 E0E7 b .L144 + 4502 .LVL340: + 4503 .L145: +2460:Src/main.c **** break; + 4504 .loc 1 2460 9 view .LVU1444 + 4505 0058 0448 ldr r0, .L154+4 + 4506 .LVL341: +2460:Src/main.c **** break; + 4507 .loc 1 2460 9 is_stmt 0 view .LVU1445 + 4508 005a FFF7FEFF bl HAL_ADC_Stop + 4509 .LVL342: +2461:Src/main.c **** } + 4510 .loc 1 2461 4 is_stmt 1 view .LVU1446 + 4511 005e 2046 mov r0, r4 + 4512 0060 DBE7 b .L144 + 4513 .LVL343: + 4514 .L152: + ARM GAS /tmp/ccWQNJQt.s page 435 + + +2440:Src/main.c **** { + 4515 .loc 1 2440 2 is_stmt 0 view .LVU1447 + 4516 0062 2046 mov r0, r4 + 4517 .LVL344: +2440:Src/main.c **** { + 4518 .loc 1 2440 2 view .LVU1448 + 4519 0064 D9E7 b .L144 + 4520 .L155: + 4521 0066 00BF .align 2 + 4522 .L154: + 4523 0068 00000000 .word hadc1 + 4524 006c 00000000 .word hadc3 + 4525 .cfi_endproc + 4526 .LFE1213: + 4528 .section .text.Set_LTEC,"ax",%progbits + 4529 .align 1 + 4530 .global Set_LTEC + 4531 .syntax unified + 4532 .thumb + 4533 .thumb_func + 4535 Set_LTEC: + 4536 .LVL345: + 4537 .LFB1211: +2266:Src/main.c **** uint32_t tmp32; + 4538 .loc 1 2266 1 is_stmt 1 view -0 + 4539 .cfi_startproc + 4540 @ args = 0, pretend = 0, frame = 0 + 4541 @ frame_needed = 0, uses_anonymous_args = 0 +2266:Src/main.c **** uint32_t tmp32; + 4542 .loc 1 2266 1 is_stmt 0 view .LVU1450 + 4543 0000 38B5 push {r3, r4, r5, lr} + 4544 .LCFI41: + 4545 .cfi_def_cfa_offset 16 + 4546 .cfi_offset 3, -16 + 4547 .cfi_offset 4, -12 + 4548 .cfi_offset 5, -8 + 4549 .cfi_offset 14, -4 + 4550 0002 0C46 mov r4, r1 +2267:Src/main.c **** + 4551 .loc 1 2267 2 is_stmt 1 view .LVU1451 +2269:Src/main.c **** { + 4552 .loc 1 2269 2 view .LVU1452 + 4553 0004 0138 subs r0, r0, #1 + 4554 .LVL346: +2269:Src/main.c **** { + 4555 .loc 1 2269 2 is_stmt 0 view .LVU1453 + 4556 0006 0328 cmp r0, #3 + 4557 0008 23D8 bhi .L157 + 4558 000a DFE800F0 tbb [pc, r0] + 4559 .L159: + 4560 000e 02 .byte (.L162-.L159)/2 + 4561 000f 3B .byte (.L161-.L159)/2 + 4562 0010 5B .byte (.L160-.L159)/2 + 4563 0011 7C .byte (.L158-.L159)/2 + 4564 .p2align 1 + 4565 .L162: +2272:Src/main.c **** //tmp32=0; + ARM GAS /tmp/ccWQNJQt.s page 436 + + + 4566 .loc 1 2272 4 is_stmt 1 view .LVU1454 + 4567 0012 0022 movs r2, #0 + 4568 0014 4FF48041 mov r1, #16384 + 4569 .LVL347: +2272:Src/main.c **** //tmp32=0; + 4570 .loc 1 2272 4 is_stmt 0 view .LVU1455 + 4571 0018 4B48 ldr r0, .L189 + 4572 .LVL348: +2272:Src/main.c **** //tmp32=0; + 4573 .loc 1 2272 4 view .LVU1456 + 4574 001a FFF7FEFF bl HAL_GPIO_WritePin + 4575 .LVL349: +2275:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi + 4576 .loc 1 2275 4 is_stmt 1 view .LVU1457 +2276:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC + 4577 .loc 1 2276 4 view .LVU1458 +2275:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi + 4578 .loc 1 2275 10 is_stmt 0 view .LVU1459 + 4579 001e 0022 movs r2, #0 + 4580 .LVL350: + 4581 .L163: +2276:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC + 4582 .loc 1 2276 42 is_stmt 1 discriminator 1 view .LVU1460 + 4583 .LBB477: + 4584 .LBI477: + 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 4585 .loc 4 916 26 view .LVU1461 + 4586 .LBB478: + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4587 .loc 4 918 3 view .LVU1462 + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4588 .loc 4 918 12 is_stmt 0 view .LVU1463 + 4589 0020 4A4B ldr r3, .L189+4 + 4590 0022 9B68 ldr r3, [r3, #8] + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4591 .loc 4 918 66 view .LVU1464 + 4592 0024 13F0020F tst r3, #2 + 4593 0028 04D1 bne .L164 + 4594 .LVL351: + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4595 .loc 4 918 66 view .LVU1465 + 4596 .LBE478: + 4597 .LBE477: +2276:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC + 4598 .loc 1 2276 42 discriminator 2 view .LVU1466 + 4599 002a B2F5FA7F cmp r2, #500 + 4600 002e 01D8 bhi .L164 +2276:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC + 4601 .loc 1 2276 59 is_stmt 1 discriminator 3 view .LVU1467 +2276:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC + 4602 .loc 1 2276 64 is_stmt 0 discriminator 3 view .LVU1468 + 4603 0030 0132 adds r2, r2, #1 + 4604 .LVL352: +2276:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC + 4605 .loc 1 2276 64 discriminator 3 view .LVU1469 + 4606 0032 F5E7 b .L163 + 4607 .L164: + ARM GAS /tmp/ccWQNJQt.s page 437 + + +2277:Src/main.c **** tmp32 = 0; + 4608 .loc 1 2277 4 is_stmt 1 view .LVU1470 + 4609 .LVL353: + 4610 .LBB479: + 4611 .LBI479: +1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Write 8-Bits in the data register +1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_TransmitData8 +1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF +1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) +1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (__GNUC__) +1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR); +1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; +1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #else +1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *((__IO uint8_t *)&SPIx->DR) = TxData; +1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* __GNUC__ */ +1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Write 16-Bits in the data register +1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_TransmitData16 +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF +1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) + 4612 .loc 4 1373 22 view .LVU1471 + 4613 .LBB480: +1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (__GNUC__) +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR); + 4614 .loc 4 1376 3 view .LVU1472 +1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; + 4615 .loc 4 1377 3 view .LVU1473 + 4616 .loc 4 1377 10 is_stmt 0 view .LVU1474 + 4617 0034 454B ldr r3, .L189+4 + 4618 0036 9C81 strh r4, [r3, #12] @ movhi + 4619 .LVL354: + 4620 .loc 4 1377 10 view .LVU1475 + 4621 .LBE480: + 4622 .LBE479: +2278:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w + 4623 .loc 1 2278 4 is_stmt 1 view .LVU1476 +2279:Src/main.c **** (void) SPI2->DR; + 4624 .loc 1 2279 4 view .LVU1477 +2278:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w + 4625 .loc 1 2278 10 is_stmt 0 view .LVU1478 + 4626 0038 0022 movs r2, #0 + 4627 .LVL355: + 4628 .L166: +2279:Src/main.c **** (void) SPI2->DR; + ARM GAS /tmp/ccWQNJQt.s page 438 + + + 4629 .loc 1 2279 43 is_stmt 1 discriminator 1 view .LVU1479 + 4630 .LBB481: + 4631 .LBI481: + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 4632 .loc 4 905 26 view .LVU1480 + 4633 .LBB482: + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4634 .loc 4 907 3 view .LVU1481 + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4635 .loc 4 907 12 is_stmt 0 view .LVU1482 + 4636 003a 444B ldr r3, .L189+4 + 4637 003c 9B68 ldr r3, [r3, #8] + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4638 .loc 4 907 68 view .LVU1483 + 4639 003e 13F0010F tst r3, #1 + 4640 0042 04D1 bne .L167 + 4641 .LVL356: + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4642 .loc 4 907 68 view .LVU1484 + 4643 .LBE482: + 4644 .LBE481: +2279:Src/main.c **** (void) SPI2->DR; + 4645 .loc 1 2279 43 discriminator 2 view .LVU1485 + 4646 0044 B2F5FA7F cmp r2, #500 + 4647 0048 01D8 bhi .L167 +2279:Src/main.c **** (void) SPI2->DR; + 4648 .loc 1 2279 60 is_stmt 1 discriminator 3 view .LVU1486 +2279:Src/main.c **** (void) SPI2->DR; + 4649 .loc 1 2279 65 is_stmt 0 discriminator 3 view .LVU1487 + 4650 004a 0132 adds r2, r2, #1 + 4651 .LVL357: +2279:Src/main.c **** (void) SPI2->DR; + 4652 .loc 1 2279 65 discriminator 3 view .LVU1488 + 4653 004c F5E7 b .L166 + 4654 .L167: +2280:Src/main.c **** break; + 4655 .loc 1 2280 4 is_stmt 1 view .LVU1489 + 4656 004e 3F4B ldr r3, .L189+4 + 4657 0050 DB68 ldr r3, [r3, #12] +2281:Src/main.c **** case 2: + 4658 .loc 1 2281 3 view .LVU1490 + 4659 .LVL358: + 4660 .L157: +2317:Src/main.c **** HAL_GPIO_WritePin(DAC_LD2_CS_GPIO_Port, DAC_LD2_CS_Pin, GPIO_PIN_SET);//End operation with LDAC2 + 4661 .loc 1 2317 2 view .LVU1491 + 4662 0052 3D4D ldr r5, .L189 + 4663 0054 0122 movs r2, #1 + 4664 0056 4FF48041 mov r1, #16384 + 4665 005a 2846 mov r0, r5 + 4666 005c FFF7FEFF bl HAL_GPIO_WritePin + 4667 .LVL359: +2318:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1 + 4668 .loc 1 2318 2 view .LVU1492 + 4669 0060 3B4C ldr r4, .L189+8 + 4670 .LVL360: +2318:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC1_CS_GPIO_Port, DAC_TEC1_CS_Pin, GPIO_PIN_SET);//End operation with TEC1 + 4671 .loc 1 2318 2 is_stmt 0 view .LVU1493 + ARM GAS /tmp/ccWQNJQt.s page 439 + + + 4672 0062 0122 movs r2, #1 + 4673 0064 4021 movs r1, #64 + 4674 0066 2046 mov r0, r4 + 4675 0068 FFF7FEFF bl HAL_GPIO_WritePin + 4676 .LVL361: +2319:Src/main.c **** HAL_GPIO_WritePin(DAC_TEC2_CS_GPIO_Port, DAC_TEC2_CS_Pin, GPIO_PIN_SET);//End operation with TEC2 + 4677 .loc 1 2319 2 is_stmt 1 view .LVU1494 + 4678 006c 0122 movs r2, #1 + 4679 006e 4FF48051 mov r1, #4096 + 4680 0072 2846 mov r0, r5 + 4681 0074 FFF7FEFF bl HAL_GPIO_WritePin + 4682 .LVL362: +2320:Src/main.c **** } + 4683 .loc 1 2320 2 view .LVU1495 + 4684 0078 0122 movs r2, #1 + 4685 007a 1021 movs r1, #16 + 4686 007c 2046 mov r0, r4 + 4687 007e FFF7FEFF bl HAL_GPIO_WritePin + 4688 .LVL363: +2321:Src/main.c **** static uint16_t MPhD_T(uint8_t num) + 4689 .loc 1 2321 1 is_stmt 0 view .LVU1496 + 4690 0082 38BD pop {r3, r4, r5, pc} + 4691 .LVL364: + 4692 .L161: +2284:Src/main.c **** //tmp32=0; + 4693 .loc 1 2284 4 is_stmt 1 view .LVU1497 + 4694 0084 0022 movs r2, #0 + 4695 0086 4021 movs r1, #64 + 4696 .LVL365: +2284:Src/main.c **** //tmp32=0; + 4697 .loc 1 2284 4 is_stmt 0 view .LVU1498 + 4698 0088 3148 ldr r0, .L189+8 + 4699 008a FFF7FEFF bl HAL_GPIO_WritePin + 4700 .LVL366: +2287:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi + 4701 .loc 1 2287 4 is_stmt 1 view .LVU1499 +2288:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC + 4702 .loc 1 2288 4 view .LVU1500 +2287:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi + 4703 .loc 1 2287 10 is_stmt 0 view .LVU1501 + 4704 008e 0022 movs r2, #0 + 4705 .LVL367: + 4706 .L169: +2288:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC + 4707 .loc 1 2288 42 is_stmt 1 discriminator 1 view .LVU1502 + 4708 .LBB483: + 4709 .LBI483: + 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 4710 .loc 4 916 26 view .LVU1503 + 4711 .LBB484: + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4712 .loc 4 918 3 view .LVU1504 + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4713 .loc 4 918 12 is_stmt 0 view .LVU1505 + 4714 0090 304B ldr r3, .L189+12 + 4715 0092 9B68 ldr r3, [r3, #8] + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + ARM GAS /tmp/ccWQNJQt.s page 440 + + + 4716 .loc 4 918 66 view .LVU1506 + 4717 0094 13F0020F tst r3, #2 + 4718 0098 04D1 bne .L170 + 4719 .LVL368: + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4720 .loc 4 918 66 view .LVU1507 + 4721 .LBE484: + 4722 .LBE483: +2288:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC + 4723 .loc 1 2288 42 discriminator 2 view .LVU1508 + 4724 009a B2F5FA7F cmp r2, #500 + 4725 009e 01D8 bhi .L170 +2288:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC + 4726 .loc 1 2288 59 is_stmt 1 discriminator 3 view .LVU1509 +2288:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC + 4727 .loc 1 2288 64 is_stmt 0 discriminator 3 view .LVU1510 + 4728 00a0 0132 adds r2, r2, #1 + 4729 .LVL369: +2288:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC + 4730 .loc 1 2288 64 discriminator 3 view .LVU1511 + 4731 00a2 F5E7 b .L169 + 4732 .L170: +2289:Src/main.c **** tmp32 = 0; + 4733 .loc 1 2289 4 is_stmt 1 view .LVU1512 + 4734 .LVL370: + 4735 .LBB485: + 4736 .LBI485: +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 4737 .loc 4 1373 22 view .LVU1513 + 4738 .LBB486: +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; + 4739 .loc 4 1376 3 view .LVU1514 + 4740 .loc 4 1377 3 view .LVU1515 + 4741 .loc 4 1377 10 is_stmt 0 view .LVU1516 + 4742 00a4 2B4B ldr r3, .L189+12 + 4743 00a6 9C81 strh r4, [r3, #12] @ movhi + 4744 .LVL371: + 4745 .loc 4 1377 10 view .LVU1517 + 4746 .LBE486: + 4747 .LBE485: +2290:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w + 4748 .loc 1 2290 4 is_stmt 1 view .LVU1518 +2291:Src/main.c **** (void) SPI6->DR; + 4749 .loc 1 2291 4 view .LVU1519 +2290:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w + 4750 .loc 1 2290 10 is_stmt 0 view .LVU1520 + 4751 00a8 0022 movs r2, #0 + 4752 .LVL372: + 4753 .L172: +2291:Src/main.c **** (void) SPI6->DR; + 4754 .loc 1 2291 43 is_stmt 1 discriminator 1 view .LVU1521 + 4755 .LBB487: + 4756 .LBI487: + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 4757 .loc 4 905 26 view .LVU1522 + 4758 .LBB488: + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + ARM GAS /tmp/ccWQNJQt.s page 441 + + + 4759 .loc 4 907 3 view .LVU1523 + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4760 .loc 4 907 12 is_stmt 0 view .LVU1524 + 4761 00aa 2A4B ldr r3, .L189+12 + 4762 00ac 9B68 ldr r3, [r3, #8] + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4763 .loc 4 907 68 view .LVU1525 + 4764 00ae 13F0010F tst r3, #1 + 4765 00b2 04D1 bne .L173 + 4766 .LVL373: + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4767 .loc 4 907 68 view .LVU1526 + 4768 .LBE488: + 4769 .LBE487: +2291:Src/main.c **** (void) SPI6->DR; + 4770 .loc 1 2291 43 discriminator 2 view .LVU1527 + 4771 00b4 B2F5FA7F cmp r2, #500 + 4772 00b8 01D8 bhi .L173 +2291:Src/main.c **** (void) SPI6->DR; + 4773 .loc 1 2291 60 is_stmt 1 discriminator 3 view .LVU1528 +2291:Src/main.c **** (void) SPI6->DR; + 4774 .loc 1 2291 65 is_stmt 0 discriminator 3 view .LVU1529 + 4775 00ba 0132 adds r2, r2, #1 + 4776 .LVL374: +2291:Src/main.c **** (void) SPI6->DR; + 4777 .loc 1 2291 65 discriminator 3 view .LVU1530 + 4778 00bc F5E7 b .L172 + 4779 .L173: +2292:Src/main.c **** break; + 4780 .loc 1 2292 4 is_stmt 1 view .LVU1531 + 4781 00be 254B ldr r3, .L189+12 + 4782 00c0 DB68 ldr r3, [r3, #12] +2293:Src/main.c **** case 3: + 4783 .loc 1 2293 3 view .LVU1532 + 4784 00c2 C6E7 b .L157 + 4785 .LVL375: + 4786 .L160: +2295:Src/main.c **** //tmp32=0; + 4787 .loc 1 2295 4 view .LVU1533 + 4788 00c4 0022 movs r2, #0 + 4789 00c6 4FF48051 mov r1, #4096 + 4790 .LVL376: +2295:Src/main.c **** //tmp32=0; + 4791 .loc 1 2295 4 is_stmt 0 view .LVU1534 + 4792 00ca 1F48 ldr r0, .L189 + 4793 00cc FFF7FEFF bl HAL_GPIO_WritePin + 4794 .LVL377: +2298:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi + 4795 .loc 1 2298 4 is_stmt 1 view .LVU1535 +2299:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC + 4796 .loc 1 2299 4 view .LVU1536 +2298:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi + 4797 .loc 1 2298 10 is_stmt 0 view .LVU1537 + 4798 00d0 0022 movs r2, #0 + 4799 .LVL378: + 4800 .L175: +2299:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC + ARM GAS /tmp/ccWQNJQt.s page 442 + + + 4801 .loc 1 2299 42 is_stmt 1 discriminator 1 view .LVU1538 + 4802 .LBB489: + 4803 .LBI489: + 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 4804 .loc 4 916 26 view .LVU1539 + 4805 .LBB490: + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4806 .loc 4 918 3 view .LVU1540 + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4807 .loc 4 918 12 is_stmt 0 view .LVU1541 + 4808 00d2 1E4B ldr r3, .L189+4 + 4809 00d4 9B68 ldr r3, [r3, #8] + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4810 .loc 4 918 66 view .LVU1542 + 4811 00d6 13F0020F tst r3, #2 + 4812 00da 04D1 bne .L176 + 4813 .LVL379: + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4814 .loc 4 918 66 view .LVU1543 + 4815 .LBE490: + 4816 .LBE489: +2299:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC + 4817 .loc 1 2299 42 discriminator 2 view .LVU1544 + 4818 00dc B2F5FA7F cmp r2, #500 + 4819 00e0 01D8 bhi .L176 +2299:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC + 4820 .loc 1 2299 59 is_stmt 1 discriminator 3 view .LVU1545 +2299:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC + 4821 .loc 1 2299 64 is_stmt 0 discriminator 3 view .LVU1546 + 4822 00e2 0132 adds r2, r2, #1 + 4823 .LVL380: +2299:Src/main.c **** LL_SPI_TransmitData16(SPI2, DATA);//Transmit word to Laser1 DAC + 4824 .loc 1 2299 64 discriminator 3 view .LVU1547 + 4825 00e4 F5E7 b .L175 + 4826 .L176: +2300:Src/main.c **** tmp32 = 0; + 4827 .loc 1 2300 4 is_stmt 1 view .LVU1548 + 4828 .LVL381: + 4829 .LBB491: + 4830 .LBI491: +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 4831 .loc 4 1373 22 view .LVU1549 + 4832 .LBB492: +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; + 4833 .loc 4 1376 3 view .LVU1550 + 4834 .loc 4 1377 3 view .LVU1551 + 4835 .loc 4 1377 10 is_stmt 0 view .LVU1552 + 4836 00e6 194B ldr r3, .L189+4 + 4837 00e8 9C81 strh r4, [r3, #12] @ movhi + 4838 .LVL382: + 4839 .loc 4 1377 10 view .LVU1553 + 4840 .LBE492: + 4841 .LBE491: +2301:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w + 4842 .loc 1 2301 4 is_stmt 1 view .LVU1554 +2302:Src/main.c **** (void) SPI2->DR; + 4843 .loc 1 2302 4 view .LVU1555 + ARM GAS /tmp/ccWQNJQt.s page 443 + + +2301:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI2))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w + 4844 .loc 1 2301 10 is_stmt 0 view .LVU1556 + 4845 00ea 0022 movs r2, #0 + 4846 .LVL383: + 4847 .L178: +2302:Src/main.c **** (void) SPI2->DR; + 4848 .loc 1 2302 43 is_stmt 1 discriminator 1 view .LVU1557 + 4849 .LBB493: + 4850 .LBI493: + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 4851 .loc 4 905 26 view .LVU1558 + 4852 .LBB494: + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4853 .loc 4 907 3 view .LVU1559 + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4854 .loc 4 907 12 is_stmt 0 view .LVU1560 + 4855 00ec 174B ldr r3, .L189+4 + 4856 00ee 9B68 ldr r3, [r3, #8] + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4857 .loc 4 907 68 view .LVU1561 + 4858 00f0 13F0010F tst r3, #1 + 4859 00f4 04D1 bne .L179 + 4860 .LVL384: + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4861 .loc 4 907 68 view .LVU1562 + 4862 .LBE494: + 4863 .LBE493: +2302:Src/main.c **** (void) SPI2->DR; + 4864 .loc 1 2302 43 discriminator 2 view .LVU1563 + 4865 00f6 B2F5FA7F cmp r2, #500 + 4866 00fa 01D8 bhi .L179 +2302:Src/main.c **** (void) SPI2->DR; + 4867 .loc 1 2302 60 is_stmt 1 discriminator 3 view .LVU1564 +2302:Src/main.c **** (void) SPI2->DR; + 4868 .loc 1 2302 65 is_stmt 0 discriminator 3 view .LVU1565 + 4869 00fc 0132 adds r2, r2, #1 + 4870 .LVL385: +2302:Src/main.c **** (void) SPI2->DR; + 4871 .loc 1 2302 65 discriminator 3 view .LVU1566 + 4872 00fe F5E7 b .L178 + 4873 .L179: +2303:Src/main.c **** break; + 4874 .loc 1 2303 4 is_stmt 1 view .LVU1567 + 4875 0100 124B ldr r3, .L189+4 + 4876 0102 DB68 ldr r3, [r3, #12] +2304:Src/main.c **** case 4: + 4877 .loc 1 2304 3 view .LVU1568 + 4878 0104 A5E7 b .L157 + 4879 .LVL386: + 4880 .L158: +2306:Src/main.c **** //tmp32=0; + 4881 .loc 1 2306 4 view .LVU1569 + 4882 0106 0022 movs r2, #0 + 4883 0108 1021 movs r1, #16 + 4884 .LVL387: +2306:Src/main.c **** //tmp32=0; + 4885 .loc 1 2306 4 is_stmt 0 view .LVU1570 + ARM GAS /tmp/ccWQNJQt.s page 444 + + + 4886 010a 1148 ldr r0, .L189+8 + 4887 010c FFF7FEFF bl HAL_GPIO_WritePin + 4888 .LVL388: +2309:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi + 4889 .loc 1 2309 4 is_stmt 1 view .LVU1571 +2310:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC + 4890 .loc 1 2310 4 view .LVU1572 +2309:Src/main.c **** while((!LL_SPI_IsActiveFlag_TXE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle wi + 4891 .loc 1 2309 10 is_stmt 0 view .LVU1573 + 4892 0110 0022 movs r2, #0 + 4893 .LVL389: + 4894 .L181: +2310:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC + 4895 .loc 1 2310 42 is_stmt 1 discriminator 1 view .LVU1574 + 4896 .LBB495: + 4897 .LBI495: + 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 4898 .loc 4 916 26 view .LVU1575 + 4899 .LBB496: + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4900 .loc 4 918 3 view .LVU1576 + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4901 .loc 4 918 12 is_stmt 0 view .LVU1577 + 4902 0112 104B ldr r3, .L189+12 + 4903 0114 9B68 ldr r3, [r3, #8] + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4904 .loc 4 918 66 view .LVU1578 + 4905 0116 13F0020F tst r3, #2 + 4906 011a 04D1 bne .L182 + 4907 .LVL390: + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4908 .loc 4 918 66 view .LVU1579 + 4909 .LBE496: + 4910 .LBE495: +2310:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC + 4911 .loc 1 2310 42 discriminator 2 view .LVU1580 + 4912 011c B2F5FA7F cmp r2, #500 + 4913 0120 01D8 bhi .L182 +2310:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC + 4914 .loc 1 2310 59 is_stmt 1 discriminator 3 view .LVU1581 +2310:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC + 4915 .loc 1 2310 64 is_stmt 0 discriminator 3 view .LVU1582 + 4916 0122 0132 adds r2, r2, #1 + 4917 .LVL391: +2310:Src/main.c **** LL_SPI_TransmitData16(SPI6, DATA);//Transmit word to Laser1 DAC + 4918 .loc 1 2310 64 discriminator 3 view .LVU1583 + 4919 0124 F5E7 b .L181 + 4920 .L182: +2311:Src/main.c **** tmp32 = 0; + 4921 .loc 1 2311 4 is_stmt 1 view .LVU1584 + 4922 .LVL392: + 4923 .LBB497: + 4924 .LBI497: +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 4925 .loc 4 1373 22 view .LVU1585 + 4926 .LBB498: +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; + ARM GAS /tmp/ccWQNJQt.s page 445 + + + 4927 .loc 4 1376 3 view .LVU1586 + 4928 .loc 4 1377 3 view .LVU1587 + 4929 .loc 4 1377 10 is_stmt 0 view .LVU1588 + 4930 0126 0B4B ldr r3, .L189+12 + 4931 0128 9C81 strh r4, [r3, #12] @ movhi + 4932 .LVL393: + 4933 .loc 4 1377 10 view .LVU1589 + 4934 .LBE498: + 4935 .LBE497: +2312:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w + 4936 .loc 1 2312 4 is_stmt 1 view .LVU1590 +2313:Src/main.c **** (void) SPI6->DR; + 4937 .loc 1 2313 4 view .LVU1591 +2312:Src/main.c **** while((!LL_SPI_IsActiveFlag_RXNE(SPI6))&&(tmp32<=500)) {tmp32++;}//When trans. last data cycle w + 4938 .loc 1 2312 10 is_stmt 0 view .LVU1592 + 4939 012a 0022 movs r2, #0 + 4940 .LVL394: + 4941 .L184: +2313:Src/main.c **** (void) SPI6->DR; + 4942 .loc 1 2313 43 is_stmt 1 discriminator 1 view .LVU1593 + 4943 .LBB499: + 4944 .LBI499: + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 4945 .loc 4 905 26 view .LVU1594 + 4946 .LBB500: + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4947 .loc 4 907 3 view .LVU1595 + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4948 .loc 4 907 12 is_stmt 0 view .LVU1596 + 4949 012c 094B ldr r3, .L189+12 + 4950 012e 9B68 ldr r3, [r3, #8] + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4951 .loc 4 907 68 view .LVU1597 + 4952 0130 13F0010F tst r3, #1 + 4953 0134 04D1 bne .L185 + 4954 .LVL395: + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 4955 .loc 4 907 68 view .LVU1598 + 4956 .LBE500: + 4957 .LBE499: +2313:Src/main.c **** (void) SPI6->DR; + 4958 .loc 1 2313 43 discriminator 2 view .LVU1599 + 4959 0136 B2F5FA7F cmp r2, #500 + 4960 013a 01D8 bhi .L185 +2313:Src/main.c **** (void) SPI6->DR; + 4961 .loc 1 2313 60 is_stmt 1 discriminator 3 view .LVU1600 +2313:Src/main.c **** (void) SPI6->DR; + 4962 .loc 1 2313 65 is_stmt 0 discriminator 3 view .LVU1601 + 4963 013c 0132 adds r2, r2, #1 + 4964 .LVL396: +2313:Src/main.c **** (void) SPI6->DR; + 4965 .loc 1 2313 65 discriminator 3 view .LVU1602 + 4966 013e F5E7 b .L184 + 4967 .L185: +2314:Src/main.c **** break; + 4968 .loc 1 2314 4 is_stmt 1 view .LVU1603 + 4969 0140 044B ldr r3, .L189+12 + ARM GAS /tmp/ccWQNJQt.s page 446 + + + 4970 0142 DB68 ldr r3, [r3, #12] +2315:Src/main.c **** } + 4971 .loc 1 2315 3 view .LVU1604 + 4972 0144 85E7 b .L157 + 4973 .L190: + 4974 0146 00BF .align 2 + 4975 .L189: + 4976 0148 00040240 .word 1073873920 + 4977 014c 00380040 .word 1073756160 + 4978 0150 00000240 .word 1073872896 + 4979 0154 00540140 .word 1073828864 + 4980 .cfi_endproc + 4981 .LFE1211: + 4983 .section .text.Decode_uart,"ax",%progbits + 4984 .align 1 + 4985 .syntax unified + 4986 .thumb + 4987 .thumb_func + 4989 Decode_uart: + 4990 .LVL397: + 4991 .LFB1208: +2011:Src/main.c **** // uint8_t *temp1; + 4992 .loc 1 2011 1 view -0 + 4993 .cfi_startproc + 4994 @ args = 0, pretend = 0, frame = 0 + 4995 @ frame_needed = 0, uses_anonymous_args = 0 +2011:Src/main.c **** // uint8_t *temp1; + 4996 .loc 1 2011 1 is_stmt 0 view .LVU1606 + 4997 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr} + 4998 .LCFI42: + 4999 .cfi_def_cfa_offset 32 + 5000 .cfi_offset 3, -32 + 5001 .cfi_offset 4, -28 + 5002 .cfi_offset 5, -24 + 5003 .cfi_offset 6, -20 + 5004 .cfi_offset 7, -16 + 5005 .cfi_offset 8, -12 + 5006 .cfi_offset 9, -8 + 5007 .cfi_offset 14, -4 + 5008 0004 0546 mov r5, r0 + 5009 0006 0F46 mov r7, r1 + 5010 0008 1646 mov r6, r2 + 5011 000a 1C46 mov r4, r3 +2013:Src/main.c **** + 5012 .loc 1 2013 2 is_stmt 1 view .LVU1607 +2018:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& + 5013 .loc 1 2018 2 view .LVU1608 +2018:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& + 5014 .loc 1 2018 6 is_stmt 0 view .LVU1609 + 5015 000c AF4B ldr r3, .L215 + 5016 .LVL398: +2018:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& + 5017 .loc 1 2018 6 view .LVU1610 + 5018 000e 0022 movs r2, #0 + 5019 .LVL399: +2018:Src/main.c **** if ((HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin) == GPIO_PIN_RESET)&& + 5020 .loc 1 2018 6 view .LVU1611 + ARM GAS /tmp/ccWQNJQt.s page 447 + + + 5021 0010 1A60 str r2, [r3] +2019:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u + 5022 .loc 1 2019 2 is_stmt 1 view .LVU1612 +2019:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u + 5023 .loc 1 2019 7 is_stmt 0 view .LVU1613 + 5024 0012 0121 movs r1, #1 + 5025 .LVL400: +2019:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u + 5026 .loc 1 2019 7 view .LVU1614 + 5027 0014 AE48 ldr r0, .L215+4 + 5028 .LVL401: +2019:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u + 5029 .loc 1 2019 7 view .LVU1615 + 5030 0016 FFF7FEFF bl HAL_GPIO_ReadPin + 5031 .LVL402: +2019:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u + 5032 .loc 1 2019 5 discriminator 1 view .LVU1616 + 5033 001a 0028 cmp r0, #0 + 5034 001c 00F0D280 beq .L212 + 5035 .L192: +2034:Src/main.c **** Curr_setup->WORK_EN = ((uint8_t)((*temp2)>>0))&0x01; + 5036 .loc 1 2034 2 is_stmt 1 view .LVU1617 + 5037 .LVL403: +2035:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; + 5038 .loc 1 2035 2 view .LVU1618 +2035:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; + 5039 .loc 1 2035 36 is_stmt 0 view .LVU1619 + 5040 0020 2B88 ldrh r3, [r5] +2035:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; + 5041 .loc 1 2035 48 view .LVU1620 + 5042 0022 03F00103 and r3, r3, #1 +2035:Src/main.c **** Curr_setup->U5V1_EN = ((uint8_t)((*temp2)>>1))&0x01; + 5043 .loc 1 2035 22 view .LVU1621 + 5044 0026 2370 strb r3, [r4] +2036:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; + 5045 .loc 1 2036 2 is_stmt 1 view .LVU1622 +2036:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; + 5046 .loc 1 2036 36 is_stmt 0 view .LVU1623 + 5047 0028 2B88 ldrh r3, [r5] +2036:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; + 5048 .loc 1 2036 48 view .LVU1624 + 5049 002a C3F34003 ubfx r3, r3, #1, #1 +2036:Src/main.c **** Curr_setup->U5V2_EN = ((uint8_t)((*temp2)>>2))&0x01; + 5050 .loc 1 2036 22 view .LVU1625 + 5051 002e 6370 strb r3, [r4, #1] +2037:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; + 5052 .loc 1 2037 2 is_stmt 1 view .LVU1626 +2037:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; + 5053 .loc 1 2037 36 is_stmt 0 view .LVU1627 + 5054 0030 2B88 ldrh r3, [r5] +2037:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; + 5055 .loc 1 2037 48 view .LVU1628 + 5056 0032 C3F38003 ubfx r3, r3, #2, #1 +2037:Src/main.c **** Curr_setup->LD1_EN = ((uint8_t)((*temp2)>>3))&0x01; + 5057 .loc 1 2037 22 view .LVU1629 + 5058 0036 A370 strb r3, [r4, #2] +2038:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; + ARM GAS /tmp/ccWQNJQt.s page 448 + + + 5059 .loc 1 2038 2 is_stmt 1 view .LVU1630 +2038:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; + 5060 .loc 1 2038 35 is_stmt 0 view .LVU1631 + 5061 0038 2B88 ldrh r3, [r5] +2038:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; + 5062 .loc 1 2038 47 view .LVU1632 + 5063 003a C3F3C003 ubfx r3, r3, #3, #1 +2038:Src/main.c **** Curr_setup->LD2_EN = ((uint8_t)((*temp2)>>4))&0x01; + 5064 .loc 1 2038 21 view .LVU1633 + 5065 003e E370 strb r3, [r4, #3] +2039:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; + 5066 .loc 1 2039 2 is_stmt 1 view .LVU1634 +2039:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; + 5067 .loc 1 2039 35 is_stmt 0 view .LVU1635 + 5068 0040 2B88 ldrh r3, [r5] +2039:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; + 5069 .loc 1 2039 47 view .LVU1636 + 5070 0042 C3F30013 ubfx r3, r3, #4, #1 +2039:Src/main.c **** Curr_setup->REF1_EN = ((uint8_t)((*temp2)>>5))&0x01; + 5071 .loc 1 2039 21 view .LVU1637 + 5072 0046 2371 strb r3, [r4, #4] +2040:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; + 5073 .loc 1 2040 2 is_stmt 1 view .LVU1638 +2040:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; + 5074 .loc 1 2040 36 is_stmt 0 view .LVU1639 + 5075 0048 2B88 ldrh r3, [r5] +2040:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; + 5076 .loc 1 2040 48 view .LVU1640 + 5077 004a C3F34013 ubfx r3, r3, #5, #1 +2040:Src/main.c **** Curr_setup->REF2_EN = ((uint8_t)((*temp2)>>6))&0x01; + 5078 .loc 1 2040 22 view .LVU1641 + 5079 004e 6371 strb r3, [r4, #5] +2041:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; + 5080 .loc 1 2041 2 is_stmt 1 view .LVU1642 +2041:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; + 5081 .loc 1 2041 36 is_stmt 0 view .LVU1643 + 5082 0050 2B88 ldrh r3, [r5] +2041:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; + 5083 .loc 1 2041 48 view .LVU1644 + 5084 0052 C3F38013 ubfx r3, r3, #6, #1 +2041:Src/main.c **** Curr_setup->TEC1_EN = ((uint8_t)((*temp2)>>7))&0x01; + 5085 .loc 1 2041 22 view .LVU1645 + 5086 0056 A371 strb r3, [r4, #6] +2042:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; + 5087 .loc 1 2042 2 is_stmt 1 view .LVU1646 +2042:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; + 5088 .loc 1 2042 36 is_stmt 0 view .LVU1647 + 5089 0058 2B88 ldrh r3, [r5] +2042:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; + 5090 .loc 1 2042 48 view .LVU1648 + 5091 005a C3F3C013 ubfx r3, r3, #7, #1 +2042:Src/main.c **** Curr_setup->TEC2_EN = ((uint8_t)((*temp2)>>8))&0x01; + 5092 .loc 1 2042 22 view .LVU1649 + 5093 005e E371 strb r3, [r4, #7] +2043:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; + 5094 .loc 1 2043 2 is_stmt 1 view .LVU1650 +2043:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; + ARM GAS /tmp/ccWQNJQt.s page 449 + + + 5095 .loc 1 2043 36 is_stmt 0 view .LVU1651 + 5096 0060 2B88 ldrh r3, [r5] +2043:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; + 5097 .loc 1 2043 48 view .LVU1652 + 5098 0062 C3F30023 ubfx r3, r3, #8, #1 +2043:Src/main.c **** Curr_setup->TS1_EN = ((uint8_t)((*temp2)>>9))&0x01; + 5099 .loc 1 2043 22 view .LVU1653 + 5100 0066 2372 strb r3, [r4, #8] +2044:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; + 5101 .loc 1 2044 2 is_stmt 1 view .LVU1654 +2044:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; + 5102 .loc 1 2044 35 is_stmt 0 view .LVU1655 + 5103 0068 2B88 ldrh r3, [r5] +2044:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; + 5104 .loc 1 2044 47 view .LVU1656 + 5105 006a C3F34023 ubfx r3, r3, #9, #1 +2044:Src/main.c **** Curr_setup->TS2_EN = ((uint8_t)((*temp2)>>10))&0x01; + 5106 .loc 1 2044 21 view .LVU1657 + 5107 006e 6372 strb r3, [r4, #9] +2045:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; + 5108 .loc 1 2045 2 is_stmt 1 view .LVU1658 +2045:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; + 5109 .loc 1 2045 35 is_stmt 0 view .LVU1659 + 5110 0070 2B88 ldrh r3, [r5] +2045:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; + 5111 .loc 1 2045 48 view .LVU1660 + 5112 0072 C3F38023 ubfx r3, r3, #10, #1 +2045:Src/main.c **** Curr_setup->SD_EN = ((uint8_t)((*temp2)>>11))&0x01; + 5113 .loc 1 2045 21 view .LVU1661 + 5114 0076 A372 strb r3, [r4, #10] +2046:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; + 5115 .loc 1 2046 2 is_stmt 1 view .LVU1662 +2046:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; + 5116 .loc 1 2046 34 is_stmt 0 view .LVU1663 + 5117 0078 2B88 ldrh r3, [r5] +2046:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; + 5118 .loc 1 2046 47 view .LVU1664 + 5119 007a C3F3C023 ubfx r3, r3, #11, #1 +2046:Src/main.c **** Curr_setup->PI1_RD = ((uint8_t)((*temp2)>>12))&0x01; + 5120 .loc 1 2046 20 view .LVU1665 + 5121 007e E372 strb r3, [r4, #11] +2047:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; + 5122 .loc 1 2047 2 is_stmt 1 view .LVU1666 +2047:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; + 5123 .loc 1 2047 35 is_stmt 0 view .LVU1667 + 5124 0080 2B88 ldrh r3, [r5] +2047:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; + 5125 .loc 1 2047 48 view .LVU1668 + 5126 0082 C3F30033 ubfx r3, r3, #12, #1 +2047:Src/main.c **** Curr_setup->PI2_RD = ((uint8_t)((*temp2)>>13))&0x01; + 5127 .loc 1 2047 21 view .LVU1669 + 5128 0086 2373 strb r3, [r4, #12] +2048:Src/main.c **** + 5129 .loc 1 2048 2 is_stmt 1 view .LVU1670 +2048:Src/main.c **** + 5130 .loc 1 2048 35 is_stmt 0 view .LVU1671 + 5131 0088 2B88 ldrh r3, [r5] + ARM GAS /tmp/ccWQNJQt.s page 450 + + +2048:Src/main.c **** + 5132 .loc 1 2048 48 view .LVU1672 + 5133 008a C3F34033 ubfx r3, r3, #13, #1 +2048:Src/main.c **** + 5134 .loc 1 2048 21 view .LVU1673 + 5135 008e 6373 strb r3, [r4, #13] +2050:Src/main.c **** LD1_curr_setup->LD_TEMP = (uint16_t)(*temp2); + 5136 .loc 1 2050 2 is_stmt 1 view .LVU1674 + 5137 .LVL404: +2051:Src/main.c **** temp2++; + 5138 .loc 1 2051 2 view .LVU1675 +2051:Src/main.c **** temp2++; + 5139 .loc 1 2051 28 is_stmt 0 view .LVU1676 + 5140 0090 6B88 ldrh r3, [r5, #2] +2051:Src/main.c **** temp2++; + 5141 .loc 1 2051 26 view .LVU1677 + 5142 0092 3B80 strh r3, [r7] @ movhi +2052:Src/main.c **** LD2_curr_setup->LD_TEMP = (uint16_t)(*temp2); + 5143 .loc 1 2052 2 is_stmt 1 view .LVU1678 + 5144 .LVL405: +2053:Src/main.c **** temp2++; + 5145 .loc 1 2053 2 view .LVU1679 +2053:Src/main.c **** temp2++; + 5146 .loc 1 2053 28 is_stmt 0 view .LVU1680 + 5147 0094 AB88 ldrh r3, [r5, #4] +2053:Src/main.c **** temp2++; + 5148 .loc 1 2053 26 view .LVU1681 + 5149 0096 3380 strh r3, [r6] @ movhi +2054:Src/main.c **** temp2++; + 5150 .loc 1 2054 2 is_stmt 1 view .LVU1682 + 5151 .LVL406: +2055:Src/main.c **** temp2++; + 5152 .loc 1 2055 2 view .LVU1683 +2056:Src/main.c **** Curr_setup->AVERAGES = (uint16_t)(*temp2); + 5153 .loc 1 2056 2 view .LVU1684 +2057:Src/main.c **** temp2++; + 5154 .loc 1 2057 2 view .LVU1685 +2057:Src/main.c **** temp2++; + 5155 .loc 1 2057 25 is_stmt 0 view .LVU1686 + 5156 0098 6B89 ldrh r3, [r5, #10] +2057:Src/main.c **** temp2++; + 5157 .loc 1 2057 23 view .LVU1687 + 5158 009a E381 strh r3, [r4, #14] @ movhi +2058:Src/main.c **** LD1_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint + 5159 .loc 1 2058 2 is_stmt 1 view .LVU1688 + 5160 .LVL407: +2059:Src/main.c **** temp2++; + 5161 .loc 1 2059 2 view .LVU1689 +2059:Src/main.c **** temp2++; + 5162 .loc 1 2059 51 is_stmt 0 view .LVU1690 + 5163 009c AB89 ldrh r3, [r5, #12] + 5164 009e 07EE903A vmov s15, r3 @ int +2059:Src/main.c **** temp2++; + 5165 .loc 1 2059 32 view .LVU1691 + 5166 00a2 F8EE677A vcvt.f32.u32 s15, s15 +2059:Src/main.c **** temp2++; + 5167 .loc 1 2059 59 view .LVU1692 + ARM GAS /tmp/ccWQNJQt.s page 451 + + + 5168 00a6 9FED8B7A vldr.32 s14, .L215+8 + 5169 00aa 67EE877A vmul.f32 s15, s15, s14 +2059:Src/main.c **** temp2++; + 5170 .loc 1 2059 30 view .LVU1693 + 5171 00ae C7ED017A vstr.32 s15, [r7, #4] +2060:Src/main.c **** LD1_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint + 5172 .loc 1 2060 2 is_stmt 1 view .LVU1694 + 5173 .LVL408: +2061:Src/main.c **** temp2++; + 5174 .loc 1 2061 2 view .LVU1695 +2061:Src/main.c **** temp2++; + 5175 .loc 1 2061 51 is_stmt 0 view .LVU1696 + 5176 00b2 EB89 ldrh r3, [r5, #14] + 5177 00b4 07EE903A vmov s15, r3 @ int +2061:Src/main.c **** temp2++; + 5178 .loc 1 2061 32 view .LVU1697 + 5179 00b8 F8EE677A vcvt.f32.u32 s15, s15 +2061:Src/main.c **** temp2++; + 5180 .loc 1 2061 59 view .LVU1698 + 5181 00bc 67EE877A vmul.f32 s15, s15, s14 +2061:Src/main.c **** temp2++; + 5182 .loc 1 2061 30 view .LVU1699 + 5183 00c0 C7ED027A vstr.32 s15, [r7, #8] +2062:Src/main.c **** LD2_curr_setup->P_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint + 5184 .loc 1 2062 2 is_stmt 1 view .LVU1700 + 5185 .LVL409: +2063:Src/main.c **** temp2++; + 5186 .loc 1 2063 2 view .LVU1701 +2063:Src/main.c **** temp2++; + 5187 .loc 1 2063 51 is_stmt 0 view .LVU1702 + 5188 00c4 2B8A ldrh r3, [r5, #16] + 5189 00c6 07EE903A vmov s15, r3 @ int +2063:Src/main.c **** temp2++; + 5190 .loc 1 2063 32 view .LVU1703 + 5191 00ca F8EE677A vcvt.f32.u32 s15, s15 +2063:Src/main.c **** temp2++; + 5192 .loc 1 2063 59 view .LVU1704 + 5193 00ce 67EE877A vmul.f32 s15, s15, s14 +2063:Src/main.c **** temp2++; + 5194 .loc 1 2063 30 view .LVU1705 + 5195 00d2 C6ED017A vstr.32 s15, [r6, #4] +2064:Src/main.c **** LD2_curr_setup->I_coef_temp = (float)((uint16_t)(*temp2))/((float)(256));//(float)(1/(float)((uint + 5196 .loc 1 2064 2 is_stmt 1 view .LVU1706 + 5197 .LVL410: +2065:Src/main.c **** temp2++; + 5198 .loc 1 2065 2 view .LVU1707 +2065:Src/main.c **** temp2++; + 5199 .loc 1 2065 51 is_stmt 0 view .LVU1708 + 5200 00d6 6B8A ldrh r3, [r5, #18] + 5201 00d8 07EE903A vmov s15, r3 @ int +2065:Src/main.c **** temp2++; + 5202 .loc 1 2065 32 view .LVU1709 + 5203 00dc F8EE677A vcvt.f32.u32 s15, s15 +2065:Src/main.c **** temp2++; + 5204 .loc 1 2065 59 view .LVU1710 + 5205 00e0 67EE877A vmul.f32 s15, s15, s14 +2065:Src/main.c **** temp2++; + ARM GAS /tmp/ccWQNJQt.s page 452 + + + 5206 .loc 1 2065 30 view .LVU1711 + 5207 00e4 C6ED027A vstr.32 s15, [r6, #8] +2066:Src/main.c **** Long_Data[13] = (uint16_t)(*temp2);//Message ID + 5208 .loc 1 2066 2 is_stmt 1 view .LVU1712 + 5209 .LVL411: +2067:Src/main.c **** temp2++; + 5210 .loc 1 2067 2 view .LVU1713 +2067:Src/main.c **** temp2++; + 5211 .loc 1 2067 18 is_stmt 0 view .LVU1714 + 5212 00e8 AA8A ldrh r2, [r5, #20] +2067:Src/main.c **** temp2++; + 5213 .loc 1 2067 16 view .LVU1715 + 5214 00ea 7B4B ldr r3, .L215+12 + 5215 00ec 5A83 strh r2, [r3, #26] @ movhi +2068:Src/main.c **** LD1_curr_setup->CURRENT = (uint16_t)(*temp2); + 5216 .loc 1 2068 2 is_stmt 1 view .LVU1716 + 5217 .LVL412: +2069:Src/main.c **** temp2++; + 5218 .loc 1 2069 2 view .LVU1717 +2069:Src/main.c **** temp2++; + 5219 .loc 1 2069 28 is_stmt 0 view .LVU1718 + 5220 00ee EB8A ldrh r3, [r5, #22] +2069:Src/main.c **** temp2++; + 5221 .loc 1 2069 26 view .LVU1719 + 5222 00f0 BB81 strh r3, [r7, #12] @ movhi +2070:Src/main.c **** LD2_curr_setup->CURRENT = (uint16_t)(*temp2); + 5223 .loc 1 2070 2 is_stmt 1 view .LVU1720 + 5224 .LVL413: +2071:Src/main.c **** temp2++; + 5225 .loc 1 2071 2 view .LVU1721 +2071:Src/main.c **** temp2++; + 5226 .loc 1 2071 28 is_stmt 0 view .LVU1722 + 5227 00f2 2B8B ldrh r3, [r5, #24] +2071:Src/main.c **** temp2++; + 5228 .loc 1 2071 26 view .LVU1723 + 5229 00f4 B381 strh r3, [r6, #12] @ movhi +2072:Src/main.c **** + 5230 .loc 1 2072 2 is_stmt 1 view .LVU1724 + 5231 .LVL414: +2074:Src/main.c **** { + 5232 .loc 1 2074 2 view .LVU1725 +2074:Src/main.c **** { + 5233 .loc 1 2074 16 is_stmt 0 view .LVU1726 + 5234 00f6 6378 ldrb r3, [r4, #1] @ zero_extendqisi2 +2074:Src/main.c **** { + 5235 .loc 1 2074 5 view .LVU1727 + 5236 00f8 002B cmp r3, #0 + 5237 00fa 00F09580 beq .L193 +2076:Src/main.c **** } + 5238 .loc 1 2076 3 is_stmt 1 view .LVU1728 + 5239 00fe 0122 movs r2, #1 + 5240 0100 0821 movs r1, #8 + 5241 0102 7648 ldr r0, .L215+16 + 5242 0104 FFF7FEFF bl HAL_GPIO_WritePin + 5243 .LVL415: + 5244 .L194: +2083:Src/main.c **** { + ARM GAS /tmp/ccWQNJQt.s page 453 + + + 5245 .loc 1 2083 2 view .LVU1729 +2083:Src/main.c **** { + 5246 .loc 1 2083 16 is_stmt 0 view .LVU1730 + 5247 0108 A378 ldrb r3, [r4, #2] @ zero_extendqisi2 +2083:Src/main.c **** { + 5248 .loc 1 2083 5 view .LVU1731 + 5249 010a 002B cmp r3, #0 + 5250 010c 00F09280 beq .L195 +2085:Src/main.c **** } + 5251 .loc 1 2085 3 is_stmt 1 view .LVU1732 + 5252 0110 0122 movs r2, #1 + 5253 0112 0421 movs r1, #4 + 5254 0114 7148 ldr r0, .L215+16 + 5255 0116 FFF7FEFF bl HAL_GPIO_WritePin + 5256 .LVL416: + 5257 .L196: +2092:Src/main.c **** { + 5258 .loc 1 2092 2 view .LVU1733 +2092:Src/main.c **** { + 5259 .loc 1 2092 16 is_stmt 0 view .LVU1734 + 5260 011a E378 ldrb r3, [r4, #3] @ zero_extendqisi2 +2092:Src/main.c **** { + 5261 .loc 1 2092 5 view .LVU1735 + 5262 011c 002B cmp r3, #0 + 5263 011e 00F08F80 beq .L197 +2094:Src/main.c **** //LL_SPI_Enable(SPI2);//Enable SPI for Laser1 DAC + 5264 .loc 1 2094 3 is_stmt 1 view .LVU1736 + 5265 0122 0122 movs r2, #1 + 5266 0124 4FF48071 mov r1, #256 + 5267 0128 6948 ldr r0, .L215+4 + 5268 012a FFF7FEFF bl HAL_GPIO_WritePin + 5269 .LVL417: + 5270 .L198: +2103:Src/main.c **** { + 5271 .loc 1 2103 2 view .LVU1737 +2103:Src/main.c **** { + 5272 .loc 1 2103 16 is_stmt 0 view .LVU1738 + 5273 012e 2379 ldrb r3, [r4, #4] @ zero_extendqisi2 +2103:Src/main.c **** { + 5274 .loc 1 2103 5 view .LVU1739 + 5275 0130 002B cmp r3, #0 + 5276 0132 00F08C80 beq .L199 +2105:Src/main.c **** //LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC + 5277 .loc 1 2105 3 is_stmt 1 view .LVU1740 + 5278 0136 0122 movs r2, #1 + 5279 0138 1021 movs r1, #16 + 5280 013a 6848 ldr r0, .L215+16 + 5281 013c FFF7FEFF bl HAL_GPIO_WritePin + 5282 .LVL418: + 5283 .L200: +2114:Src/main.c **** { + 5284 .loc 1 2114 2 view .LVU1741 +2114:Src/main.c **** { + 5285 .loc 1 2114 16 is_stmt 0 view .LVU1742 + 5286 0140 6379 ldrb r3, [r4, #5] @ zero_extendqisi2 +2114:Src/main.c **** { + 5287 .loc 1 2114 5 view .LVU1743 + ARM GAS /tmp/ccWQNJQt.s page 454 + + + 5288 0142 002B cmp r3, #0 + 5289 0144 00F08980 beq .L201 +2116:Src/main.c **** } + 5290 .loc 1 2116 3 is_stmt 1 view .LVU1744 + 5291 0148 0122 movs r2, #1 + 5292 014a 4FF48061 mov r1, #1024 + 5293 014e 6448 ldr r0, .L215+20 + 5294 0150 FFF7FEFF bl HAL_GPIO_WritePin + 5295 .LVL419: + 5296 .L202: +2123:Src/main.c **** { + 5297 .loc 1 2123 2 view .LVU1745 +2123:Src/main.c **** { + 5298 .loc 1 2123 16 is_stmt 0 view .LVU1746 + 5299 0154 A379 ldrb r3, [r4, #6] @ zero_extendqisi2 +2123:Src/main.c **** { + 5300 .loc 1 2123 5 view .LVU1747 + 5301 0156 002B cmp r3, #0 + 5302 0158 00F08680 beq .L203 +2125:Src/main.c **** } + 5303 .loc 1 2125 3 is_stmt 1 view .LVU1748 + 5304 015c 0122 movs r2, #1 + 5305 015e 0821 movs r1, #8 + 5306 0160 6048 ldr r0, .L215+24 + 5307 0162 FFF7FEFF bl HAL_GPIO_WritePin + 5308 .LVL420: + 5309 .L204: +2132:Src/main.c **** { + 5310 .loc 1 2132 2 view .LVU1749 +2132:Src/main.c **** { + 5311 .loc 1 2132 17 is_stmt 0 view .LVU1750 + 5312 0166 637A ldrb r3, [r4, #9] @ zero_extendqisi2 +2132:Src/main.c **** { + 5313 .loc 1 2132 5 view .LVU1751 + 5314 0168 1BB1 cbz r3, .L205 +2132:Src/main.c **** { + 5315 .loc 1 2132 39 discriminator 1 view .LVU1752 + 5316 016a E379 ldrb r3, [r4, #7] @ zero_extendqisi2 +2132:Src/main.c **** { + 5317 .loc 1 2132 26 discriminator 1 view .LVU1753 + 5318 016c 002B cmp r3, #0 + 5319 016e 40F08180 bne .L213 + 5320 .L205: +2141:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_RESET); + 5321 .loc 1 2141 3 is_stmt 1 view .LVU1754 + 5322 0172 0022 movs r2, #0 + 5323 0174 0121 movs r1, #1 + 5324 0176 5B48 ldr r0, .L215+24 + 5325 0178 FFF7FEFF bl HAL_GPIO_WritePin + 5326 .LVL421: +2142:Src/main.c **** } + 5327 .loc 1 2142 3 view .LVU1755 + 5328 017c 0022 movs r2, #0 + 5329 017e 4FF40061 mov r1, #2048 + 5330 0182 5748 ldr r0, .L215+20 + 5331 0184 FFF7FEFF bl HAL_GPIO_WritePin + 5332 .LVL422: + ARM GAS /tmp/ccWQNJQt.s page 455 + + + 5333 .L206: +2145:Src/main.c **** { + 5334 .loc 1 2145 2 view .LVU1756 +2145:Src/main.c **** { + 5335 .loc 1 2145 17 is_stmt 0 view .LVU1757 + 5336 0188 A37A ldrb r3, [r4, #10] @ zero_extendqisi2 +2145:Src/main.c **** { + 5337 .loc 1 2145 5 view .LVU1758 + 5338 018a 1BB1 cbz r3, .L207 +2145:Src/main.c **** { + 5339 .loc 1 2145 39 discriminator 1 view .LVU1759 + 5340 018c 237A ldrb r3, [r4, #8] @ zero_extendqisi2 +2145:Src/main.c **** { + 5341 .loc 1 2145 26 discriminator 1 view .LVU1760 + 5342 018e 002B cmp r3, #0 + 5343 0190 40F08680 bne .L214 + 5344 .L207: +2154:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_RESET); + 5345 .loc 1 2154 3 is_stmt 1 view .LVU1761 + 5346 0194 0022 movs r2, #0 + 5347 0196 0221 movs r1, #2 + 5348 0198 5248 ldr r0, .L215+24 + 5349 019a FFF7FEFF bl HAL_GPIO_WritePin + 5350 .LVL423: +2155:Src/main.c **** } + 5351 .loc 1 2155 3 view .LVU1762 + 5352 019e 0022 movs r2, #0 + 5353 01a0 2021 movs r1, #32 + 5354 01a2 4E48 ldr r0, .L215+16 + 5355 01a4 FFF7FEFF bl HAL_GPIO_WritePin + 5356 .LVL424: + 5357 .L208: +2158:Src/main.c **** { + 5358 .loc 1 2158 2 view .LVU1763 +2158:Src/main.c **** { + 5359 .loc 1 2158 16 is_stmt 0 view .LVU1764 + 5360 01a8 237B ldrb r3, [r4, #12] @ zero_extendqisi2 +2158:Src/main.c **** { + 5361 .loc 1 2158 5 view .LVU1765 + 5362 01aa 1BB9 cbnz r3, .L209 +2160:Src/main.c **** LD1_curr_setup->I_coef_temp = 0.01; + 5363 .loc 1 2160 3 is_stmt 1 view .LVU1766 +2160:Src/main.c **** LD1_curr_setup->I_coef_temp = 0.01; + 5364 .loc 1 2160 31 is_stmt 0 view .LVU1767 + 5365 01ac 4E4B ldr r3, .L215+28 + 5366 01ae 7B60 str r3, [r7, #4] @ float +2161:Src/main.c **** } + 5367 .loc 1 2161 3 is_stmt 1 view .LVU1768 +2161:Src/main.c **** } + 5368 .loc 1 2161 31 is_stmt 0 view .LVU1769 + 5369 01b0 4E4B ldr r3, .L215+32 + 5370 01b2 BB60 str r3, [r7, #8] @ float + 5371 .L209: +2164:Src/main.c **** { + 5372 .loc 1 2164 2 is_stmt 1 view .LVU1770 +2164:Src/main.c **** { + 5373 .loc 1 2164 16 is_stmt 0 view .LVU1771 + ARM GAS /tmp/ccWQNJQt.s page 456 + + + 5374 01b4 637B ldrb r3, [r4, #13] @ zero_extendqisi2 +2164:Src/main.c **** { + 5375 .loc 1 2164 5 view .LVU1772 + 5376 01b6 1BB9 cbnz r3, .L191 +2166:Src/main.c **** LD2_curr_setup->I_coef_temp = 0.01; + 5377 .loc 1 2166 3 is_stmt 1 view .LVU1773 +2166:Src/main.c **** LD2_curr_setup->I_coef_temp = 0.01; + 5378 .loc 1 2166 31 is_stmt 0 view .LVU1774 + 5379 01b8 4B4B ldr r3, .L215+28 + 5380 01ba 7360 str r3, [r6, #4] @ float +2167:Src/main.c **** } + 5381 .loc 1 2167 3 is_stmt 1 view .LVU1775 +2167:Src/main.c **** } + 5382 .loc 1 2167 31 is_stmt 0 view .LVU1776 + 5383 01bc 4B4B ldr r3, .L215+32 + 5384 01be B360 str r3, [r6, #8] @ float + 5385 .L191: +2169:Src/main.c **** + 5386 .loc 1 2169 1 view .LVU1777 + 5387 01c0 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} + 5388 .LVL425: + 5389 .L212: +2020:Src/main.c **** { + 5390 .loc 1 2020 6 view .LVU1778 + 5391 01c4 4FF48071 mov r1, #256 + 5392 01c8 4648 ldr r0, .L215+24 + 5393 01ca FFF7FEFF bl HAL_GPIO_ReadPin + 5394 .LVL426: +2019:Src/main.c **** (HAL_GPIO_ReadPin(USB_FLAG_GPIO_Port, USB_FLAG_Pin) == GPIO_PIN_SET))//if exist sd && connect u + 5395 .loc 1 2019 78 discriminator 1 view .LVU1779 + 5396 01ce 0128 cmp r0, #1 + 5397 01d0 7FF426AF bne .L192 +2022:Src/main.c **** if (test == 0) //0 - suc + 5398 .loc 1 2022 3 is_stmt 1 view .LVU1780 +2022:Src/main.c **** if (test == 0) //0 - suc + 5399 .loc 1 2022 10 is_stmt 0 view .LVU1781 + 5400 01d4 4648 ldr r0, .L215+36 + 5401 01d6 FFF7FEFF bl Mount_SD + 5402 .LVL427: +2022:Src/main.c **** if (test == 0) //0 - suc + 5403 .loc 1 2022 8 discriminator 1 view .LVU1782 + 5404 01da 3C4B ldr r3, .L215 + 5405 01dc 1860 str r0, [r3] +2023:Src/main.c **** { + 5406 .loc 1 2023 3 is_stmt 1 view .LVU1783 +2023:Src/main.c **** { + 5407 .loc 1 2023 6 is_stmt 0 view .LVU1784 + 5408 01de 0028 cmp r0, #0 + 5409 01e0 7FF41EAF bne .L192 +2026:Src/main.c **** test = Create_File("COMMAND.TXT"); // 0 -succ + 5410 .loc 1 2026 4 is_stmt 1 view .LVU1785 +2026:Src/main.c **** test = Create_File("COMMAND.TXT"); // 0 -succ + 5411 .loc 1 2026 11 is_stmt 0 view .LVU1786 + 5412 01e4 DFF80C91 ldr r9, .L215+40 + 5413 01e8 4846 mov r0, r9 + 5414 01ea FFF7FEFF bl Remove_File + 5415 .LVL428: + ARM GAS /tmp/ccWQNJQt.s page 457 + + +2026:Src/main.c **** test = Create_File("COMMAND.TXT"); // 0 -succ + 5416 .loc 1 2026 9 discriminator 1 view .LVU1787 + 5417 01ee DFF8DC80 ldr r8, .L215 + 5418 01f2 C8F80000 str r0, [r8] +2027:Src/main.c **** test = Write_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); + 5419 .loc 1 2027 4 is_stmt 1 view .LVU1788 +2027:Src/main.c **** test = Write_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); + 5420 .loc 1 2027 11 is_stmt 0 view .LVU1789 + 5421 01f6 4846 mov r0, r9 + 5422 01f8 FFF7FEFF bl Create_File + 5423 .LVL429: +2027:Src/main.c **** test = Write_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); + 5424 .loc 1 2027 9 discriminator 1 view .LVU1790 + 5425 01fc C8F80000 str r0, [r8] +2028:Src/main.c **** test = Update_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); + 5426 .loc 1 2028 4 is_stmt 1 view .LVU1791 +2028:Src/main.c **** test = Update_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); + 5427 .loc 1 2028 11 is_stmt 0 view .LVU1792 + 5428 0200 1E22 movs r2, #30 + 5429 0202 2946 mov r1, r5 + 5430 0204 4846 mov r0, r9 + 5431 0206 FFF7FEFF bl Write_File_byte + 5432 .LVL430: +2028:Src/main.c **** test = Update_File_byte("COMMAND.TXT", (uint8_t *)Command, CL_8); + 5433 .loc 1 2028 9 discriminator 1 view .LVU1793 + 5434 020a C8F80000 str r0, [r8] +2029:Src/main.c **** test = Unmount_SD("/"); // 0 - succ + 5435 .loc 1 2029 4 is_stmt 1 view .LVU1794 +2029:Src/main.c **** test = Unmount_SD("/"); // 0 - succ + 5436 .loc 1 2029 11 is_stmt 0 view .LVU1795 + 5437 020e 1E22 movs r2, #30 + 5438 0210 2946 mov r1, r5 + 5439 0212 4846 mov r0, r9 + 5440 0214 FFF7FEFF bl Update_File_byte + 5441 .LVL431: +2029:Src/main.c **** test = Unmount_SD("/"); // 0 - succ + 5442 .loc 1 2029 9 discriminator 1 view .LVU1796 + 5443 0218 C8F80000 str r0, [r8] +2030:Src/main.c **** } + 5444 .loc 1 2030 4 is_stmt 1 view .LVU1797 +2030:Src/main.c **** } + 5445 .loc 1 2030 11 is_stmt 0 view .LVU1798 + 5446 021c 3448 ldr r0, .L215+36 + 5447 021e FFF7FEFF bl Unmount_SD + 5448 .LVL432: +2030:Src/main.c **** } + 5449 .loc 1 2030 9 discriminator 1 view .LVU1799 + 5450 0222 C8F80000 str r0, [r8] + 5451 0226 FBE6 b .L192 + 5452 .LVL433: + 5453 .L193: +2080:Src/main.c **** } + 5454 .loc 1 2080 3 is_stmt 1 view .LVU1800 + 5455 0228 0022 movs r2, #0 + 5456 022a 0821 movs r1, #8 + 5457 022c 2B48 ldr r0, .L215+16 + 5458 022e FFF7FEFF bl HAL_GPIO_WritePin + ARM GAS /tmp/ccWQNJQt.s page 458 + + + 5459 .LVL434: + 5460 0232 69E7 b .L194 + 5461 .L195: +2089:Src/main.c **** } + 5462 .loc 1 2089 3 view .LVU1801 + 5463 0234 0022 movs r2, #0 + 5464 0236 0421 movs r1, #4 + 5465 0238 2848 ldr r0, .L215+16 + 5466 023a FFF7FEFF bl HAL_GPIO_WritePin + 5467 .LVL435: + 5468 023e 6CE7 b .L196 + 5469 .L197: +2099:Src/main.c **** //LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC + 5470 .loc 1 2099 3 view .LVU1802 + 5471 0240 0022 movs r2, #0 + 5472 0242 4FF48071 mov r1, #256 + 5473 0246 2248 ldr r0, .L215+4 + 5474 0248 FFF7FEFF bl HAL_GPIO_WritePin + 5475 .LVL436: + 5476 024c 6FE7 b .L198 + 5477 .L199: +2110:Src/main.c **** //LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC + 5478 .loc 1 2110 3 view .LVU1803 + 5479 024e 0022 movs r2, #0 + 5480 0250 1021 movs r1, #16 + 5481 0252 2248 ldr r0, .L215+16 + 5482 0254 FFF7FEFF bl HAL_GPIO_WritePin + 5483 .LVL437: + 5484 0258 72E7 b .L200 + 5485 .L201: +2120:Src/main.c **** } + 5486 .loc 1 2120 3 view .LVU1804 + 5487 025a 0022 movs r2, #0 + 5488 025c 4FF48061 mov r1, #1024 + 5489 0260 1F48 ldr r0, .L215+20 + 5490 0262 FFF7FEFF bl HAL_GPIO_WritePin + 5491 .LVL438: + 5492 0266 75E7 b .L202 + 5493 .L203: +2129:Src/main.c **** } + 5494 .loc 1 2129 3 view .LVU1805 + 5495 0268 0022 movs r2, #0 + 5496 026a 0821 movs r1, #8 + 5497 026c 1D48 ldr r0, .L215+24 + 5498 026e FFF7FEFF bl HAL_GPIO_WritePin + 5499 .LVL439: + 5500 0272 78E7 b .L204 + 5501 .L213: +2134:Src/main.c **** Set_LTEC(3,32767); + 5502 .loc 1 2134 3 view .LVU1806 + 5503 0274 47F6FF71 movw r1, #32767 + 5504 0278 0320 movs r0, #3 + 5505 027a FFF7FEFF bl Set_LTEC + 5506 .LVL440: +2135:Src/main.c **** HAL_GPIO_WritePin(TEC1_PD_GPIO_Port, TEC1_PD_Pin, GPIO_PIN_SET); + 5507 .loc 1 2135 3 view .LVU1807 + 5508 027e 47F6FF71 movw r1, #32767 + ARM GAS /tmp/ccWQNJQt.s page 459 + + + 5509 0282 0320 movs r0, #3 + 5510 0284 FFF7FEFF bl Set_LTEC + 5511 .LVL441: +2136:Src/main.c **** HAL_GPIO_WritePin(TECEN1_GPIO_Port, TECEN1_Pin, GPIO_PIN_SET); + 5512 .loc 1 2136 3 view .LVU1808 + 5513 0288 0122 movs r2, #1 + 5514 028a 4FF40061 mov r1, #2048 + 5515 028e 1448 ldr r0, .L215+20 + 5516 0290 FFF7FEFF bl HAL_GPIO_WritePin + 5517 .LVL442: +2137:Src/main.c **** } + 5518 .loc 1 2137 3 view .LVU1809 + 5519 0294 0122 movs r2, #1 + 5520 0296 1146 mov r1, r2 + 5521 0298 1248 ldr r0, .L215+24 + 5522 029a FFF7FEFF bl HAL_GPIO_WritePin + 5523 .LVL443: + 5524 029e 73E7 b .L206 + 5525 .L214: +2147:Src/main.c **** Set_LTEC(4,32767); + 5526 .loc 1 2147 3 view .LVU1810 + 5527 02a0 47F6FF71 movw r1, #32767 + 5528 02a4 0420 movs r0, #4 + 5529 02a6 FFF7FEFF bl Set_LTEC + 5530 .LVL444: +2148:Src/main.c **** HAL_GPIO_WritePin(TEC2_PD_GPIO_Port, TEC2_PD_Pin, GPIO_PIN_SET); + 5531 .loc 1 2148 3 view .LVU1811 + 5532 02aa 47F6FF71 movw r1, #32767 + 5533 02ae 0420 movs r0, #4 + 5534 02b0 FFF7FEFF bl Set_LTEC + 5535 .LVL445: +2149:Src/main.c **** HAL_GPIO_WritePin(TECEN2_GPIO_Port, TECEN2_Pin, GPIO_PIN_SET); + 5536 .loc 1 2149 3 view .LVU1812 + 5537 02b4 0122 movs r2, #1 + 5538 02b6 2021 movs r1, #32 + 5539 02b8 0848 ldr r0, .L215+16 + 5540 02ba FFF7FEFF bl HAL_GPIO_WritePin + 5541 .LVL446: +2150:Src/main.c **** } + 5542 .loc 1 2150 3 view .LVU1813 + 5543 02be 0122 movs r2, #1 + 5544 02c0 0221 movs r1, #2 + 5545 02c2 0848 ldr r0, .L215+24 + 5546 02c4 FFF7FEFF bl HAL_GPIO_WritePin + 5547 .LVL447: + 5548 02c8 6EE7 b .L208 + 5549 .L216: + 5550 02ca 00BF .align 2 + 5551 .L215: + 5552 02cc 00000000 .word test + 5553 02d0 000C0240 .word 1073875968 + 5554 02d4 0000803B .word 998244352 + 5555 02d8 00000000 .word Long_Data + 5556 02dc 00080240 .word 1073874944 + 5557 02e0 00040240 .word 1073873920 + 5558 02e4 00000240 .word 1073872896 + 5559 02e8 00002041 .word 1092616192 + ARM GAS /tmp/ccWQNJQt.s page 460 + + + 5560 02ec 0AD7233C .word 1008981770 + 5561 02f0 00000000 .word .LC0 + 5562 02f4 04000000 .word .LC1 + 5563 .cfi_endproc + 5564 .LFE1208: + 5566 .section .text.Advanced_Controller_Temp,"ax",%progbits + 5567 .align 1 + 5568 .global Advanced_Controller_Temp + 5569 .syntax unified + 5570 .thumb + 5571 .thumb_func + 5573 Advanced_Controller_Temp: + 5574 .LVL448: + 5575 .LFB1214: +2467:Src/main.c **** // Main idea: + 5576 .loc 1 2467 1 view -0 + 5577 .cfi_startproc + 5578 @ args = 0, pretend = 0, frame = 0 + 5579 @ frame_needed = 0, uses_anonymous_args = 0 + 5580 @ link register save eliminated. +2467:Src/main.c **** // Main idea: + 5581 .loc 1 2467 1 is_stmt 0 view .LVU1815 + 5582 0000 30B4 push {r4, r5} + 5583 .LCFI43: + 5584 .cfi_def_cfa_offset 8 + 5585 .cfi_offset 4, -8 + 5586 .cfi_offset 5, -4 +2485:Src/main.c **** float P_coef_current;//, I_coef_current; + 5587 .loc 1 2485 2 is_stmt 1 view .LVU1816 +2486:Src/main.c **** float e_integral; + 5588 .loc 1 2486 2 view .LVU1817 +2487:Src/main.c **** int x_output; + 5589 .loc 1 2487 2 view .LVU1818 +2488:Src/main.c **** + 5590 .loc 1 2488 2 view .LVU1819 +2490:Src/main.c **** + 5591 .loc 1 2490 2 view .LVU1820 +2490:Src/main.c **** + 5592 .loc 1 2490 28 is_stmt 0 view .LVU1821 + 5593 0002 0B88 ldrh r3, [r1] +2490:Src/main.c **** + 5594 .loc 1 2490 65 view .LVU1822 + 5595 0004 0488 ldrh r4, [r0] +2490:Src/main.c **** + 5596 .loc 1 2490 8 view .LVU1823 + 5597 0006 1B1B subs r3, r3, r4 + 5598 .LVL449: +2492:Src/main.c **** + 5599 .loc 1 2492 2 is_stmt 1 view .LVU1824 +2492:Src/main.c **** + 5600 .loc 1 2492 13 is_stmt 0 view .LVU1825 + 5601 0008 D1ED017A vldr.32 s15, [r1, #4] + 5602 .LVL450: +2494:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 + 5603 .loc 1 2494 2 is_stmt 1 view .LVU1826 +2494:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 + 5604 .loc 1 2494 20 is_stmt 0 view .LVU1827 + ARM GAS /tmp/ccWQNJQt.s page 461 + + + 5605 000c 03F6B73C addw ip, r3, #2999 +2494:Src/main.c **** e_integral += LDx_curr_setup->I_coef_temp * (float)(e_pid) * (float)(TO7 - TO7_PID) / (float) 100 + 5606 .loc 1 2494 4 view .LVU1828 + 5607 0010 41F26E74 movw r4, #5998 + 5608 0014 A445 cmp ip, r4 + 5609 0016 18D8 bhi .L218 +2495:Src/main.c **** } + 5610 .loc 1 2495 3 is_stmt 1 view .LVU1829 +2495:Src/main.c **** } + 5611 .loc 1 2495 31 is_stmt 0 view .LVU1830 + 5612 0018 90ED027A vldr.32 s14, [r0, #8] +2495:Src/main.c **** } + 5613 .loc 1 2495 47 view .LVU1831 + 5614 001c 06EE903A vmov s13, r3 @ int + 5615 0020 F8EEE66A vcvt.f32.s32 s13, s13 +2495:Src/main.c **** } + 5616 .loc 1 2495 45 view .LVU1832 + 5617 0024 27EE267A vmul.f32 s14, s14, s13 +2495:Src/main.c **** } + 5618 .loc 1 2495 76 view .LVU1833 + 5619 0028 284C ldr r4, .L228 + 5620 002a 2468 ldr r4, [r4] + 5621 002c 284D ldr r5, .L228+4 + 5622 002e 2D68 ldr r5, [r5] + 5623 0030 641B subs r4, r4, r5 +2495:Src/main.c **** } + 5624 .loc 1 2495 64 view .LVU1834 + 5625 0032 06EE904A vmov s13, r4 @ int + 5626 0036 F8EE666A vcvt.f32.u32 s13, s13 +2495:Src/main.c **** } + 5627 .loc 1 2495 62 view .LVU1835 + 5628 003a 27EE267A vmul.f32 s14, s14, s13 +2495:Src/main.c **** } + 5629 .loc 1 2495 87 view .LVU1836 + 5630 003e 9FED256A vldr.32 s12, .L228+8 + 5631 0042 C7EE066A vdiv.f32 s13, s14, s12 +2495:Src/main.c **** } + 5632 .loc 1 2495 14 view .LVU1837 + 5633 0046 77EEA67A vadd.f32 s15, s15, s13 + 5634 .LVL451: + 5635 .L218: +2497:Src/main.c **** + 5636 .loc 1 2497 2 is_stmt 1 view .LVU1838 +2497:Src/main.c **** + 5637 .loc 1 2497 17 is_stmt 0 view .LVU1839 + 5638 004a D0ED016A vldr.32 s13, [r0, #4] + 5639 .LVL452: +2499:Src/main.c **** e_integral = 32000; + 5640 .loc 1 2499 2 is_stmt 1 view .LVU1840 +2499:Src/main.c **** e_integral = 32000; + 5641 .loc 1 2499 5 is_stmt 0 view .LVU1841 + 5642 004e 9FED227A vldr.32 s14, .L228+12 + 5643 0052 F4EEC77A vcmpe.f32 s15, s14 + 5644 0056 F1EE10FA vmrs APSR_nzcv, FPSCR + 5645 005a 09DC bgt .L222 +2502:Src/main.c **** e_integral = -32000; + 5646 .loc 1 2502 7 is_stmt 1 view .LVU1842 + ARM GAS /tmp/ccWQNJQt.s page 462 + + +2502:Src/main.c **** e_integral = -32000; + 5647 .loc 1 2502 10 is_stmt 0 view .LVU1843 + 5648 005c 9FED1F7A vldr.32 s14, .L228+16 + 5649 0060 F4EEC77A vcmpe.f32 s15, s14 + 5650 0064 F1EE10FA vmrs APSR_nzcv, FPSCR + 5651 0068 04D5 bpl .L219 +2503:Src/main.c **** } + 5652 .loc 1 2503 15 view .LVU1844 + 5653 006a DFED1C7A vldr.32 s15, .L228+16 + 5654 .LVL453: +2503:Src/main.c **** } + 5655 .loc 1 2503 15 view .LVU1845 + 5656 006e 01E0 b .L219 + 5657 .LVL454: + 5658 .L222: +2500:Src/main.c **** } + 5659 .loc 1 2500 15 view .LVU1846 + 5660 0070 DFED197A vldr.32 s15, .L228+12 + 5661 .LVL455: + 5662 .L219: +2505:Src/main.c **** + 5663 .loc 1 2505 2 is_stmt 1 view .LVU1847 +2505:Src/main.c **** + 5664 .loc 1 2505 26 is_stmt 0 view .LVU1848 + 5665 0074 C1ED017A vstr.32 s15, [r1, #4] +2507:Src/main.c **** + 5666 .loc 1 2507 2 is_stmt 1 view .LVU1849 +2507:Src/main.c **** + 5667 .loc 1 2507 36 is_stmt 0 view .LVU1850 + 5668 0078 07EE103A vmov s14, r3 @ int + 5669 007c B8EEC77A vcvt.f32.s32 s14, s14 + 5670 0080 27EE267A vmul.f32 s14, s14, s13 +2507:Src/main.c **** + 5671 .loc 1 2507 19 view .LVU1851 + 5672 0084 DFED166A vldr.32 s13, .L228+20 + 5673 .LVL456: +2507:Src/main.c **** + 5674 .loc 1 2507 19 view .LVU1852 + 5675 0088 37EE267A vadd.f32 s14, s14, s13 +2507:Src/main.c **** + 5676 .loc 1 2507 46 view .LVU1853 + 5677 008c FDEEE77A vcvt.s32.f32 s15, s15 + 5678 .LVL457: +2507:Src/main.c **** + 5679 .loc 1 2507 44 view .LVU1854 + 5680 0090 F8EEE77A vcvt.f32.s32 s15, s15 + 5681 0094 77EE877A vadd.f32 s15, s15, s14 +2507:Src/main.c **** + 5682 .loc 1 2507 11 view .LVU1855 + 5683 0098 FDEEE77A vcvt.s32.f32 s15, s15 + 5684 009c 17EE900A vmov r0, s15 @ int + 5685 .LVL458: +2509:Src/main.c **** x_output = 8800; + 5686 .loc 1 2509 2 is_stmt 1 view .LVU1856 +2509:Src/main.c **** x_output = 8800; + 5687 .loc 1 2509 4 is_stmt 0 view .LVU1857 + 5688 00a0 B0F57A7F cmp r0, #1000 + ARM GAS /tmp/ccWQNJQt.s page 463 + + + 5689 00a4 06DB blt .L224 +2512:Src/main.c **** x_output = 56800; + 5690 .loc 1 2512 7 is_stmt 1 view .LVU1858 +2512:Src/main.c **** x_output = 56800; + 5691 .loc 1 2512 9 is_stmt 0 view .LVU1859 + 5692 00a6 4DF6E053 movw r3, #56800 + 5693 .LVL459: +2512:Src/main.c **** x_output = 56800; + 5694 .loc 1 2512 9 view .LVU1860 + 5695 00aa 9842 cmp r0, r3 + 5696 00ac 04DD ble .L220 +2513:Src/main.c **** } + 5697 .loc 1 2513 12 view .LVU1861 + 5698 00ae 4DF6E050 movw r0, #56800 + 5699 .LVL460: +2513:Src/main.c **** } + 5700 .loc 1 2513 12 view .LVU1862 + 5701 00b2 01E0 b .L220 + 5702 .LVL461: + 5703 .L224: +2510:Src/main.c **** } + 5704 .loc 1 2510 12 view .LVU1863 + 5705 00b4 42F26020 movw r0, #8800 + 5706 .LVL462: + 5707 .L220: +2516:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser + 5708 .loc 1 2516 2 is_stmt 1 view .LVU1864 +2516:Src/main.c **** TO7_PID = TO7;//Save current time only on 2nd laser + 5709 .loc 1 2516 5 is_stmt 0 view .LVU1865 + 5710 00b8 022A cmp r2, #2 + 5711 00ba 02D0 beq .L227 + 5712 .LVL463: + 5713 .L221: +2519:Src/main.c **** } + 5714 .loc 1 2519 2 is_stmt 1 view .LVU1866 +2520:Src/main.c **** + 5715 .loc 1 2520 1 is_stmt 0 view .LVU1867 + 5716 00bc 80B2 uxth r0, r0 + 5717 .LVL464: +2520:Src/main.c **** + 5718 .loc 1 2520 1 view .LVU1868 + 5719 00be 30BC pop {r4, r5} + 5720 .LCFI44: + 5721 .cfi_remember_state + 5722 .cfi_restore 5 + 5723 .cfi_restore 4 + 5724 .cfi_def_cfa_offset 0 + 5725 00c0 7047 bx lr + 5726 .LVL465: + 5727 .L227: + 5728 .LCFI45: + 5729 .cfi_restore_state +2517:Src/main.c **** + 5730 .loc 1 2517 3 is_stmt 1 view .LVU1869 +2517:Src/main.c **** + 5731 .loc 1 2517 11 is_stmt 0 view .LVU1870 + 5732 00c2 024B ldr r3, .L228 + ARM GAS /tmp/ccWQNJQt.s page 464 + + + 5733 00c4 1A68 ldr r2, [r3] + 5734 .LVL466: +2517:Src/main.c **** + 5735 .loc 1 2517 11 view .LVU1871 + 5736 00c6 024B ldr r3, .L228+4 + 5737 00c8 1A60 str r2, [r3] + 5738 00ca F7E7 b .L221 + 5739 .L229: + 5740 .align 2 + 5741 .L228: + 5742 00cc 00000000 .word TO7 + 5743 00d0 00000000 .word TO7_PID + 5744 00d4 0000C842 .word 1120403456 + 5745 00d8 0000FA46 .word 1190789120 + 5746 00dc 0000FAC6 .word -956694528 + 5747 00e0 00000047 .word 1191182336 + 5748 .cfi_endproc + 5749 .LFE1214: + 5751 .section .text.CalculateChecksum,"ax",%progbits + 5752 .align 1 + 5753 .global CalculateChecksum + 5754 .syntax unified + 5755 .thumb + 5756 .thumb_func + 5758 CalculateChecksum: + 5759 .LVL467: + 5760 .LFB1217: +2583:Src/main.c **** short i; + 5761 .loc 1 2583 1 is_stmt 1 view -0 + 5762 .cfi_startproc + 5763 @ args = 0, pretend = 0, frame = 0 + 5764 @ frame_needed = 0, uses_anonymous_args = 0 + 5765 @ link register save eliminated. +2583:Src/main.c **** short i; + 5766 .loc 1 2583 1 is_stmt 0 view .LVU1873 + 5767 0000 8446 mov ip, r0 +2584:Src/main.c **** uint16_t cs = *pbuff; + 5768 .loc 1 2584 2 is_stmt 1 view .LVU1874 +2585:Src/main.c **** + 5769 .loc 1 2585 2 view .LVU1875 +2585:Src/main.c **** + 5770 .loc 1 2585 11 is_stmt 0 view .LVU1876 + 5771 0002 0088 ldrh r0, [r0] + 5772 .LVL468: +2587:Src/main.c **** { + 5773 .loc 1 2587 3 is_stmt 1 view .LVU1877 +2587:Src/main.c **** { + 5774 .loc 1 2587 9 is_stmt 0 view .LVU1878 + 5775 0004 0123 movs r3, #1 +2587:Src/main.c **** { + 5776 .loc 1 2587 3 view .LVU1879 + 5777 0006 04E0 b .L231 + 5778 .LVL469: + 5779 .L232: +2589:Src/main.c **** } + 5780 .loc 1 2589 3 is_stmt 1 view .LVU1880 +2589:Src/main.c **** } + ARM GAS /tmp/ccWQNJQt.s page 465 + + + 5781 .loc 1 2589 9 is_stmt 0 view .LVU1881 + 5782 0008 3CF81320 ldrh r2, [ip, r3, lsl #1] +2589:Src/main.c **** } + 5783 .loc 1 2589 6 view .LVU1882 + 5784 000c 5040 eors r0, r0, r2 + 5785 .LVL470: +2587:Src/main.c **** { + 5786 .loc 1 2587 24 is_stmt 1 discriminator 3 view .LVU1883 + 5787 000e 0133 adds r3, r3, #1 + 5788 .LVL471: +2587:Src/main.c **** { + 5789 .loc 1 2587 24 is_stmt 0 discriminator 3 view .LVU1884 + 5790 0010 1BB2 sxth r3, r3 + 5791 .LVL472: + 5792 .L231: +2587:Src/main.c **** { + 5793 .loc 1 2587 16 is_stmt 1 discriminator 1 view .LVU1885 + 5794 0012 8B42 cmp r3, r1 + 5795 0014 F8DB blt .L232 +2591:Src/main.c **** } + 5796 .loc 1 2591 2 view .LVU1886 +2592:Src/main.c **** + 5797 .loc 1 2592 1 is_stmt 0 view .LVU1887 + 5798 0016 7047 bx lr + 5799 .cfi_endproc + 5800 .LFE1217: + 5802 .section .text.CheckChecksum,"ax",%progbits + 5803 .align 1 + 5804 .global CheckChecksum + 5805 .syntax unified + 5806 .thumb + 5807 .thumb_func + 5809 CheckChecksum: + 5810 .LVL473: + 5811 .LFB1216: +2562:Src/main.c **** uint16_t cl_ind; + 5812 .loc 1 2562 1 is_stmt 1 view -0 + 5813 .cfi_startproc + 5814 @ args = 0, pretend = 0, frame = 0 + 5815 @ frame_needed = 0, uses_anonymous_args = 0 +2562:Src/main.c **** uint16_t cl_ind; + 5816 .loc 1 2562 1 is_stmt 0 view .LVU1889 + 5817 0000 10B5 push {r4, lr} + 5818 .LCFI46: + 5819 .cfi_def_cfa_offset 8 + 5820 .cfi_offset 4, -8 + 5821 .cfi_offset 14, -4 +2563:Src/main.c **** + 5822 .loc 1 2563 3 is_stmt 1 view .LVU1890 +2565:Src/main.c **** { + 5823 .loc 1 2565 3 view .LVU1891 + 5824 0002 0E4B ldr r3, .L239 + 5825 0004 1B88 ldrh r3, [r3] + 5826 0006 41F21112 movw r2, #4369 + 5827 000a 9342 cmp r3, r2 + 5828 000c 05D0 beq .L236 + 5829 000e 47F27772 movw r2, #30583 + ARM GAS /tmp/ccWQNJQt.s page 466 + + + 5830 0012 9342 cmp r3, r2 + 5831 0014 0FD1 bne .L237 + 5832 0016 0E24 movs r4, #14 + 5833 0018 00E0 b .L234 + 5834 .L236: +2571:Src/main.c **** break; + 5835 .loc 1 2571 14 is_stmt 0 view .LVU1892 + 5836 001a 0D24 movs r4, #13 + 5837 .L234: + 5838 .LVL474: +2575:Src/main.c **** } + 5839 .loc 1 2575 5 is_stmt 1 view .LVU1893 +2578:Src/main.c **** + 5840 .loc 1 2578 3 view .LVU1894 +2578:Src/main.c **** + 5841 .loc 1 2578 15 is_stmt 0 view .LVU1895 + 5842 001c 2146 mov r1, r4 + 5843 001e FFF7FEFF bl CalculateChecksum + 5844 .LVL475: +2578:Src/main.c **** + 5845 .loc 1 2578 13 discriminator 1 view .LVU1896 + 5846 0022 074B ldr r3, .L239+4 + 5847 0024 1880 strh r0, [r3] @ movhi +2580:Src/main.c **** } + 5848 .loc 1 2580 3 is_stmt 1 view .LVU1897 +2580:Src/main.c **** } + 5849 .loc 1 2580 32 is_stmt 0 view .LVU1898 + 5850 0026 074B ldr r3, .L239+8 + 5851 0028 33F81430 ldrh r3, [r3, r4, lsl #1] +2580:Src/main.c **** } + 5852 .loc 1 2580 46 view .LVU1899 + 5853 002c 9842 cmp r0, r3 + 5854 002e 14BF ite ne + 5855 0030 0020 movne r0, #0 + 5856 0032 0120 moveq r0, #1 + 5857 .LVL476: + 5858 .L235: +2581:Src/main.c **** uint16_t CalculateChecksum(uint16_t *pbuff, uint16_t len) + 5859 .loc 1 2581 1 view .LVU1900 + 5860 0034 10BD pop {r4, pc} + 5861 .LVL477: + 5862 .L237: +2565:Src/main.c **** { + 5863 .loc 1 2565 3 view .LVU1901 + 5864 0036 0020 movs r0, #0 + 5865 .LVL478: +2565:Src/main.c **** { + 5866 .loc 1 2565 3 view .LVU1902 + 5867 0038 FCE7 b .L235 + 5868 .L240: + 5869 003a 00BF .align 2 + 5870 .L239: + 5871 003c 00000000 .word UART_header + 5872 0040 00000000 .word CS_result + 5873 0044 00000000 .word COMMAND + 5874 .cfi_endproc + 5875 .LFE1216: + ARM GAS /tmp/ccWQNJQt.s page 467 + + + 5877 .section .rodata.SD_SAVE.str1.4,"aMS",%progbits,1 + 5878 .align 2 + 5879 .LC2: + 5880 0000 46494C45 .ascii "FILE1.TXT\000" + 5880 312E5458 + 5880 5400 + 5881 .section .text.SD_SAVE,"ax",%progbits + 5882 .align 1 + 5883 .global SD_SAVE + 5884 .syntax unified + 5885 .thumb + 5886 .thumb_func + 5888 SD_SAVE: + 5889 .LVL479: + 5890 .LFB1218: +2621:Src/main.c **** int test=0; + 5891 .loc 1 2621 1 is_stmt 1 view -0 + 5892 .cfi_startproc + 5893 @ args = 0, pretend = 0, frame = 0 + 5894 @ frame_needed = 0, uses_anonymous_args = 0 +2621:Src/main.c **** int test=0; + 5895 .loc 1 2621 1 is_stmt 0 view .LVU1904 + 5896 0000 10B5 push {r4, lr} + 5897 .LCFI47: + 5898 .cfi_def_cfa_offset 8 + 5899 .cfi_offset 4, -8 + 5900 .cfi_offset 14, -4 + 5901 0002 0446 mov r4, r0 +2622:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) + 5902 .loc 1 2622 2 is_stmt 1 view .LVU1905 + 5903 .LVL480: +2623:Src/main.c **** { + 5904 .loc 1 2623 2 view .LVU1906 +2623:Src/main.c **** { + 5905 .loc 1 2623 6 is_stmt 0 view .LVU1907 + 5906 0004 0121 movs r1, #1 + 5907 0006 0A48 ldr r0, .L248 + 5908 .LVL481: +2623:Src/main.c **** { + 5909 .loc 1 2623 6 view .LVU1908 + 5910 0008 FFF7FEFF bl HAL_GPIO_ReadPin + 5911 .LVL482: +2623:Src/main.c **** { + 5912 .loc 1 2623 5 discriminator 1 view .LVU1909 + 5913 000c 08B1 cbz r0, .L246 +2640:Src/main.c **** } + 5914 .loc 1 2640 10 view .LVU1910 + 5915 000e 0120 movs r0, #1 + 5916 .LVL483: + 5917 .L241: +2642:Src/main.c **** + 5918 .loc 1 2642 1 view .LVU1911 + 5919 0010 10BD pop {r4, pc} + 5920 .LVL484: + 5921 .L246: +2625:Src/main.c **** if (test == 0) //0 - suc + 5922 .loc 1 2625 3 is_stmt 1 view .LVU1912 + ARM GAS /tmp/ccWQNJQt.s page 468 + + +2625:Src/main.c **** if (test == 0) //0 - suc + 5923 .loc 1 2625 10 is_stmt 0 view .LVU1913 + 5924 0012 0848 ldr r0, .L248+4 + 5925 0014 FFF7FEFF bl Mount_SD + 5926 .LVL485: +2626:Src/main.c **** { + 5927 .loc 1 2626 3 is_stmt 1 view .LVU1914 +2626:Src/main.c **** { + 5928 .loc 1 2626 6 is_stmt 0 view .LVU1915 + 5929 0018 08B1 cbz r0, .L247 +2635:Src/main.c **** } + 5930 .loc 1 2635 11 view .LVU1916 + 5931 001a 0120 movs r0, #1 + 5932 .LVL486: +2635:Src/main.c **** } + 5933 .loc 1 2635 11 view .LVU1917 + 5934 001c F8E7 b .L241 + 5935 .LVL487: + 5936 .L247: +2629:Src/main.c **** test = Unmount_SD("/"); // 0 - succ + 5937 .loc 1 2629 4 is_stmt 1 view .LVU1918 +2629:Src/main.c **** test = Unmount_SD("/"); // 0 - succ + 5938 .loc 1 2629 11 is_stmt 0 view .LVU1919 + 5939 001e 1E22 movs r2, #30 + 5940 0020 2146 mov r1, r4 + 5941 0022 0548 ldr r0, .L248+8 + 5942 .LVL488: +2629:Src/main.c **** test = Unmount_SD("/"); // 0 - succ + 5943 .loc 1 2629 11 view .LVU1920 + 5944 0024 FFF7FEFF bl Update_File_byte + 5945 .LVL489: +2630:Src/main.c **** return test; + 5946 .loc 1 2630 4 is_stmt 1 view .LVU1921 +2630:Src/main.c **** return test; + 5947 .loc 1 2630 11 is_stmt 0 view .LVU1922 + 5948 0028 0248 ldr r0, .L248+4 + 5949 002a FFF7FEFF bl Unmount_SD + 5950 .LVL490: +2631:Src/main.c **** } + 5951 .loc 1 2631 4 is_stmt 1 view .LVU1923 +2631:Src/main.c **** } + 5952 .loc 1 2631 11 is_stmt 0 view .LVU1924 + 5953 002e EFE7 b .L241 + 5954 .L249: + 5955 .align 2 + 5956 .L248: + 5957 0030 000C0240 .word 1073875968 + 5958 0034 00000000 .word .LC0 + 5959 0038 00000000 .word .LC2 + 5960 .cfi_endproc + 5961 .LFE1218: + 5963 .section .text.SD_READ,"ax",%progbits + 5964 .align 1 + 5965 .global SD_READ + 5966 .syntax unified + 5967 .thumb + 5968 .thumb_func + ARM GAS /tmp/ccWQNJQt.s page 469 + + + 5970 SD_READ: + 5971 .LVL491: + 5972 .LFB1219: +2652:Src/main.c **** int test=0; + 5973 .loc 1 2652 1 is_stmt 1 view -0 + 5974 .cfi_startproc + 5975 @ args = 0, pretend = 0, frame = 0 + 5976 @ frame_needed = 0, uses_anonymous_args = 0 +2652:Src/main.c **** int test=0; + 5977 .loc 1 2652 1 is_stmt 0 view .LVU1926 + 5978 0000 38B5 push {r3, r4, r5, lr} + 5979 .LCFI48: + 5980 .cfi_def_cfa_offset 16 + 5981 .cfi_offset 3, -16 + 5982 .cfi_offset 4, -12 + 5983 .cfi_offset 5, -8 + 5984 .cfi_offset 14, -4 + 5985 0002 0446 mov r4, r0 +2653:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) + 5986 .loc 1 2653 2 is_stmt 1 view .LVU1927 + 5987 .LVL492: +2654:Src/main.c **** { + 5988 .loc 1 2654 2 view .LVU1928 +2654:Src/main.c **** { + 5989 .loc 1 2654 6 is_stmt 0 view .LVU1929 + 5990 0004 0121 movs r1, #1 + 5991 0006 0D48 ldr r0, .L257 + 5992 .LVL493: +2654:Src/main.c **** { + 5993 .loc 1 2654 6 view .LVU1930 + 5994 0008 FFF7FEFF bl HAL_GPIO_ReadPin + 5995 .LVL494: +2654:Src/main.c **** { + 5996 .loc 1 2654 5 discriminator 1 view .LVU1931 + 5997 000c 08B1 cbz r0, .L255 +2672:Src/main.c **** } + 5998 .loc 1 2672 10 view .LVU1932 + 5999 000e 0120 movs r0, #1 + 6000 .LVL495: + 6001 .L250: +2688:Src/main.c **** + 6002 .loc 1 2688 1 view .LVU1933 + 6003 0010 38BD pop {r3, r4, r5, pc} + 6004 .LVL496: + 6005 .L255: +2656:Src/main.c **** if (test == 0) //0 - suc + 6006 .loc 1 2656 3 is_stmt 1 view .LVU1934 +2656:Src/main.c **** if (test == 0) //0 - suc + 6007 .loc 1 2656 10 is_stmt 0 view .LVU1935 + 6008 0012 0B48 ldr r0, .L257+4 + 6009 0014 FFF7FEFF bl Mount_SD + 6010 .LVL497: +2657:Src/main.c **** { + 6011 .loc 1 2657 3 is_stmt 1 view .LVU1936 +2657:Src/main.c **** { + 6012 .loc 1 2657 6 is_stmt 0 view .LVU1937 + 6013 0018 08B1 cbz r0, .L256 + ARM GAS /tmp/ccWQNJQt.s page 470 + + +2667:Src/main.c **** } + 6014 .loc 1 2667 11 view .LVU1938 + 6015 001a 0120 movs r0, #1 + 6016 .LVL498: +2667:Src/main.c **** } + 6017 .loc 1 2667 11 view .LVU1939 + 6018 001c F8E7 b .L250 + 6019 .LVL499: + 6020 .L256: +2660:Src/main.c **** fgoto+=DL_8; + 6021 .loc 1 2660 4 is_stmt 1 view .LVU1940 +2660:Src/main.c **** fgoto+=DL_8; + 6022 .loc 1 2660 11 is_stmt 0 view .LVU1941 + 6023 001e 094D ldr r5, .L257+8 + 6024 0020 2B68 ldr r3, [r5] + 6025 0022 1E22 movs r2, #30 + 6026 0024 2146 mov r1, r4 + 6027 0026 0848 ldr r0, .L257+12 + 6028 .LVL500: +2660:Src/main.c **** fgoto+=DL_8; + 6029 .loc 1 2660 11 view .LVU1942 + 6030 0028 FFF7FEFF bl Seek_Read_File + 6031 .LVL501: +2661:Src/main.c **** test = Unmount_SD("/"); // 0 - succ + 6032 .loc 1 2661 4 is_stmt 1 view .LVU1943 +2661:Src/main.c **** test = Unmount_SD("/"); // 0 - succ + 6033 .loc 1 2661 9 is_stmt 0 view .LVU1944 + 6034 002c 2B68 ldr r3, [r5] + 6035 002e 1E33 adds r3, r3, #30 + 6036 0030 2B60 str r3, [r5] +2662:Src/main.c **** return test; + 6037 .loc 1 2662 4 is_stmt 1 view .LVU1945 +2662:Src/main.c **** return test; + 6038 .loc 1 2662 11 is_stmt 0 view .LVU1946 + 6039 0032 0348 ldr r0, .L257+4 + 6040 0034 FFF7FEFF bl Unmount_SD + 6041 .LVL502: +2663:Src/main.c **** } + 6042 .loc 1 2663 4 is_stmt 1 view .LVU1947 +2663:Src/main.c **** } + 6043 .loc 1 2663 11 is_stmt 0 view .LVU1948 + 6044 0038 EAE7 b .L250 + 6045 .L258: + 6046 003a 00BF .align 2 + 6047 .L257: + 6048 003c 000C0240 .word 1073875968 + 6049 0040 00000000 .word .LC0 + 6050 0044 00000000 .word fgoto + 6051 0048 00000000 .word .LC2 + 6052 .cfi_endproc + 6053 .LFE1219: + 6055 .section .text.SD_REMOVE,"ax",%progbits + 6056 .align 1 + 6057 .global SD_REMOVE + 6058 .syntax unified + 6059 .thumb + 6060 .thumb_func + ARM GAS /tmp/ccWQNJQt.s page 471 + + + 6062 SD_REMOVE: + 6063 .LFB1220: +2691:Src/main.c **** int test=0; + 6064 .loc 1 2691 1 is_stmt 1 view -0 + 6065 .cfi_startproc + 6066 @ args = 0, pretend = 0, frame = 0 + 6067 @ frame_needed = 0, uses_anonymous_args = 0 + 6068 0000 10B5 push {r4, lr} + 6069 .LCFI49: + 6070 .cfi_def_cfa_offset 8 + 6071 .cfi_offset 4, -8 + 6072 .cfi_offset 14, -4 +2692:Src/main.c **** if (HAL_GPIO_ReadPin(SDMMC1_EN_GPIO_Port, SDMMC1_EN_Pin)==GPIO_PIN_RESET) + 6073 .loc 1 2692 2 view .LVU1950 + 6074 .LVL503: +2693:Src/main.c **** { + 6075 .loc 1 2693 2 view .LVU1951 +2693:Src/main.c **** { + 6076 .loc 1 2693 6 is_stmt 0 view .LVU1952 + 6077 0002 0121 movs r1, #1 + 6078 0004 0B48 ldr r0, .L266 + 6079 0006 FFF7FEFF bl HAL_GPIO_ReadPin + 6080 .LVL504: +2693:Src/main.c **** { + 6081 .loc 1 2693 5 discriminator 1 view .LVU1953 + 6082 000a 08B1 cbz r0, .L264 +2711:Src/main.c **** } + 6083 .loc 1 2711 10 view .LVU1954 + 6084 000c 0120 movs r0, #1 + 6085 .LVL505: + 6086 .L259: +2713:Src/main.c **** + 6087 .loc 1 2713 1 view .LVU1955 + 6088 000e 10BD pop {r4, pc} + 6089 .LVL506: + 6090 .L264: +2695:Src/main.c **** if (test==FR_OK) + 6091 .loc 1 2695 3 is_stmt 1 view .LVU1956 +2695:Src/main.c **** if (test==FR_OK) + 6092 .loc 1 2695 10 is_stmt 0 view .LVU1957 + 6093 0010 0948 ldr r0, .L266+4 + 6094 0012 FFF7FEFF bl Mount_SD + 6095 .LVL507: +2696:Src/main.c **** { + 6096 .loc 1 2696 3 is_stmt 1 view .LVU1958 +2696:Src/main.c **** { + 6097 .loc 1 2696 6 is_stmt 0 view .LVU1959 + 6098 0016 08B1 cbz r0, .L265 +2706:Src/main.c **** } + 6099 .loc 1 2706 11 view .LVU1960 + 6100 0018 0120 movs r0, #1 + 6101 .LVL508: +2706:Src/main.c **** } + 6102 .loc 1 2706 11 view .LVU1961 + 6103 001a F8E7 b .L259 + 6104 .LVL509: + 6105 .L265: + ARM GAS /tmp/ccWQNJQt.s page 472 + + +2698:Src/main.c **** test = Create_File("FILE1.TXT"); // 0 -suc + 6106 .loc 1 2698 4 is_stmt 1 view .LVU1962 +2698:Src/main.c **** test = Create_File("FILE1.TXT"); // 0 -suc + 6107 .loc 1 2698 11 is_stmt 0 view .LVU1963 + 6108 001c 074C ldr r4, .L266+8 + 6109 001e 2046 mov r0, r4 + 6110 .LVL510: +2698:Src/main.c **** test = Create_File("FILE1.TXT"); // 0 -suc + 6111 .loc 1 2698 11 view .LVU1964 + 6112 0020 FFF7FEFF bl Remove_File + 6113 .LVL511: +2699:Src/main.c **** //test = Write_File ("FILE1.TXT", "____OSGG main borad information. Program made by Kazakov Vikt + 6114 .loc 1 2699 4 is_stmt 1 view .LVU1965 +2699:Src/main.c **** //test = Write_File ("FILE1.TXT", "____OSGG main borad information. Program made by Kazakov Vikt + 6115 .loc 1 2699 11 is_stmt 0 view .LVU1966 + 6116 0024 2046 mov r0, r4 + 6117 0026 FFF7FEFF bl Create_File + 6118 .LVL512: +2701:Src/main.c **** return test; + 6119 .loc 1 2701 4 is_stmt 1 view .LVU1967 +2701:Src/main.c **** return test; + 6120 .loc 1 2701 11 is_stmt 0 view .LVU1968 + 6121 002a 0348 ldr r0, .L266+4 + 6122 002c FFF7FEFF bl Unmount_SD + 6123 .LVL513: +2702:Src/main.c **** } + 6124 .loc 1 2702 4 is_stmt 1 view .LVU1969 +2702:Src/main.c **** } + 6125 .loc 1 2702 11 is_stmt 0 view .LVU1970 + 6126 0030 EDE7 b .L259 + 6127 .L267: + 6128 0032 00BF .align 2 + 6129 .L266: + 6130 0034 000C0240 .word 1073875968 + 6131 0038 00000000 .word .LC0 + 6132 003c 00000000 .word .LC2 + 6133 .cfi_endproc + 6134 .LFE1220: + 6136 .section .text.USART_TX,"ax",%progbits + 6137 .align 1 + 6138 .global USART_TX + 6139 .syntax unified + 6140 .thumb + 6141 .thumb_func + 6143 USART_TX: + 6144 .LVL514: + 6145 .LFB1221: +2717:Src/main.c **** uint16_t ind = 0; + 6146 .loc 1 2717 1 is_stmt 1 view -0 + 6147 .cfi_startproc + 6148 @ args = 0, pretend = 0, frame = 0 + 6149 @ frame_needed = 0, uses_anonymous_args = 0 + 6150 @ link register save eliminated. +2717:Src/main.c **** uint16_t ind = 0; + 6151 .loc 1 2717 1 is_stmt 0 view .LVU1972 + 6152 0000 8C46 mov ip, r1 +2718:Src/main.c **** while (indCR3, USART_CR3_DMAT); +3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if DMA Mode is enabled for transmission +3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX +3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) +3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); +3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable DMA Disabling on Reception Error +3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr +3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) +3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_DDRE); +3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable DMA Disabling on Reception Error +3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr +3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) +3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE); +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if DMA Disabling on Reception Error is disabled +3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr +3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) +3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); +3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Get the data register address used for DMA transfer +3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n +3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr +3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + ARM GAS /tmp/ccWQNJQt.s page 475 + + +3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Direction This parameter can be one of the following values: +3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT +3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE +3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Address of data register +3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) +3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t data_reg_addr; +3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) +3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* return address of TDR register */ +3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** data_reg_addr = (uint32_t) &(USARTx->TDR); +3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else +3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* return address of RDR register */ +3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** data_reg_addr = (uint32_t) &(USARTx->RDR); +3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return data_reg_addr; +3642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +3646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Data_Management Data_Management +3649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +3650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Read Receiver Data register (Receive Data value, 8 bits) +3654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RDR RDR LL_USART_ReceiveData8 +3655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0xFF +3657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) +3659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); +3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Read Receiver Data register (Receive Data value, 9 bits) +3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RDR RDR LL_USART_ReceiveData9 +3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x1FF +3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) +3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); +3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) +3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll TDR TDR LL_USART_TransmitData8 +3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + ARM GAS /tmp/ccWQNJQt.s page 476 + + +3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Value between Min_Data=0x00 and Max_Data=0xFF +3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) + 6192 .loc 7 3681 22 view .LVU1987 + 6193 .LBB504: +3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->TDR = Value; + 6194 .loc 7 3683 3 view .LVU1988 + 6195 .loc 7 3683 15 is_stmt 0 view .LVU1989 + 6196 0018 034B ldr r3, .L273 + 6197 001a 9962 str r1, [r3, #40] + 6198 .LVL520: + 6199 .loc 7 3683 15 view .LVU1990 + 6200 .LBE504: + 6201 .LBE503: +2723:Src/main.c **** } + 6202 .loc 1 2723 5 is_stmt 1 view .LVU1991 +2723:Src/main.c **** } + 6203 .loc 1 2723 8 is_stmt 0 view .LVU1992 + 6204 001c 0132 adds r2, r2, #1 + 6205 .LVL521: +2723:Src/main.c **** } + 6206 .loc 1 2723 8 view .LVU1993 + 6207 001e 92B2 uxth r2, r2 + 6208 .LVL522: + 6209 .L269: +2719:Src/main.c **** { + 6210 .loc 1 2719 13 is_stmt 1 view .LVU1994 + 6211 0020 6245 cmp r2, ip + 6212 0022 F1D3 bcc .L271 +2725:Src/main.c **** + 6213 .loc 1 2725 1 is_stmt 0 view .LVU1995 + 6214 0024 7047 bx lr + 6215 .L274: + 6216 0026 00BF .align 2 + 6217 .L273: + 6218 0028 00100140 .word 1073811456 + 6219 .cfi_endproc + 6220 .LFE1221: + 6222 .section .text.USART_TX_DMA,"ax",%progbits + 6223 .align 1 + 6224 .global USART_TX_DMA + 6225 .syntax unified + 6226 .thumb + 6227 .thumb_func + 6229 USART_TX_DMA: + 6230 .LFB1222: +2728:Src/main.c **** while (u_tx_flg) {}//Wait until previous transfer not complete. u_tx_flg is resetting in DMA inter + 6231 .loc 1 2728 1 is_stmt 1 view -0 + 6232 .cfi_startproc + 6233 @ args = 0, pretend = 0, frame = 0 + 6234 @ frame_needed = 0, uses_anonymous_args = 0 + 6235 @ link register save eliminated. + 6236 .LVL523: + 6237 .L276: +2729:Src/main.c **** LL_DMA_DisableStream(DMA2, LL_DMA_STREAM_7); + ARM GAS /tmp/ccWQNJQt.s page 477 + + + 6238 .loc 1 2729 20 discriminator 1 view .LVU1997 +2729:Src/main.c **** LL_DMA_DisableStream(DMA2, LL_DMA_STREAM_7); + 6239 .loc 1 2729 9 discriminator 1 view .LVU1998 + 6240 0000 0D4B ldr r3, .L277 + 6241 0002 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 6242 0004 002B cmp r3, #0 + 6243 0006 FBD1 bne .L276 +2730:Src/main.c **** LL_DMA_SetDataLength(DMA2, LL_DMA_STREAM_7, sz); + 6244 .loc 1 2730 2 view .LVU1999 + 6245 .LVL524: + 6246 .LBB505: + 6247 .LBI505: + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 6248 .loc 6 517 22 view .LVU2000 + 6249 .LBB506: + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6250 .loc 6 519 3 view .LVU2001 + 6251 0008 0C4B ldr r3, .L277+4 + 6252 000a D3F8B820 ldr r2, [r3, #184] + 6253 000e 22F00102 bic r2, r2, #1 + 6254 0012 C3F8B820 str r2, [r3, #184] + 6255 .LVL525: + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6256 .loc 6 519 3 is_stmt 0 view .LVU2002 + 6257 .LBE506: + 6258 .LBE505: +2731:Src/main.c **** LL_DMA_EnableStream(DMA2, LL_DMA_STREAM_7); + 6259 .loc 1 2731 3 is_stmt 1 view .LVU2003 + 6260 .LBB507: + 6261 .LBI507: + 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 6262 .loc 6 971 22 view .LVU2004 + 6263 .LBB508: + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6264 .loc 6 973 3 view .LVU2005 + 6265 0016 D3F8BC20 ldr r2, [r3, #188] + 6266 001a 6FF30F02 bfc r2, #0, #16 + 6267 001e 1043 orrs r0, r0, r2 + 6268 .LVL526: + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6269 .loc 6 973 3 is_stmt 0 view .LVU2006 + 6270 0020 C3F8BC00 str r0, [r3, #188] + 6271 .LVL527: + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6272 .loc 6 973 3 view .LVU2007 + 6273 .LBE508: + 6274 .LBE507: +2732:Src/main.c **** u_tx_flg = 1;//indicate that transfer begin + 6275 .loc 1 2732 3 is_stmt 1 view .LVU2008 + 6276 .LBB509: + 6277 .LBI509: + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 6278 .loc 6 497 22 view .LVU2009 + 6279 .LBB510: + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6280 .loc 6 499 3 view .LVU2010 + 6281 0024 D3F8B820 ldr r2, [r3, #184] + ARM GAS /tmp/ccWQNJQt.s page 478 + + + 6282 0028 42F00102 orr r2, r2, #1 + 6283 002c C3F8B820 str r2, [r3, #184] + 6284 .LVL528: + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6285 .loc 6 499 3 is_stmt 0 view .LVU2011 + 6286 .LBE510: + 6287 .LBE509: +2733:Src/main.c **** } + 6288 .loc 1 2733 2 is_stmt 1 view .LVU2012 +2733:Src/main.c **** } + 6289 .loc 1 2733 11 is_stmt 0 view .LVU2013 + 6290 0030 014B ldr r3, .L277 + 6291 0032 0122 movs r2, #1 + 6292 0034 1A70 strb r2, [r3] +2734:Src/main.c **** + 6293 .loc 1 2734 1 view .LVU2014 + 6294 0036 7047 bx lr + 6295 .L278: + 6296 .align 2 + 6297 .L277: + 6298 0038 00000000 .word u_tx_flg + 6299 003c 00640240 .word 1073898496 + 6300 .cfi_endproc + 6301 .LFE1222: + 6303 .section .text.Error_Handler,"ax",%progbits + 6304 .align 1 + 6305 .global Error_Handler + 6306 .syntax unified + 6307 .thumb + 6308 .thumb_func + 6310 Error_Handler: + 6311 .LFB1224: +2742:Src/main.c **** //------------------------------------------------------- +2743:Src/main.c **** /* USER CODE END 4 */ +2744:Src/main.c **** +2745:Src/main.c **** /** +2746:Src/main.c **** * @brief This function is executed in case of error occurrence. +2747:Src/main.c **** * @retval None +2748:Src/main.c **** */ +2749:Src/main.c **** void Error_Handler(void) +2750:Src/main.c **** { + 6312 .loc 1 2750 1 is_stmt 1 view -0 + 6313 .cfi_startproc + 6314 @ Volatile: function does not return. + 6315 @ args = 0, pretend = 0, frame = 0 + 6316 @ frame_needed = 0, uses_anonymous_args = 0 + 6317 @ link register save eliminated. +2751:Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ +2752:Src/main.c **** /* User can add his own implementation to report the HAL error return state */ +2753:Src/main.c **** __disable_irq(); + 6318 .loc 1 2753 3 view .LVU2016 + 6319 .LBB511: + 6320 .LBI511: + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 6321 .loc 8 140 27 view .LVU2017 + 6322 .LBB512: + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccWQNJQt.s page 479 + + + 6323 .loc 8 142 3 view .LVU2018 + 6324 .syntax unified + 6325 @ 142 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 6326 0000 72B6 cpsid i + 6327 @ 0 "" 2 + 6328 .thumb + 6329 .syntax unified + 6330 .L280: + 6331 .LBE512: + 6332 .LBE511: +2754:Src/main.c **** while (1) + 6333 .loc 1 2754 3 view .LVU2019 +2755:Src/main.c **** { +2756:Src/main.c **** } + 6334 .loc 1 2756 3 view .LVU2020 +2754:Src/main.c **** while (1) + 6335 .loc 1 2754 9 view .LVU2021 + 6336 0002 FEE7 b .L280 + 6337 .cfi_endproc + 6338 .LFE1224: + 6340 .section .text.MX_ADC1_Init,"ax",%progbits + 6341 .align 1 + 6342 .syntax unified + 6343 .thumb + 6344 .thumb_func + 6346 MX_ADC1_Init: + 6347 .LFB1188: + 816:Src/main.c **** + 6348 .loc 1 816 1 view -0 + 6349 .cfi_startproc + 6350 @ args = 0, pretend = 0, frame = 16 + 6351 @ frame_needed = 0, uses_anonymous_args = 0 + 6352 0000 00B5 push {lr} + 6353 .LCFI50: + 6354 .cfi_def_cfa_offset 4 + 6355 .cfi_offset 14, -4 + 6356 0002 85B0 sub sp, sp, #20 + 6357 .LCFI51: + 6358 .cfi_def_cfa_offset 24 + 822:Src/main.c **** + 6359 .loc 1 822 3 view .LVU2023 + 822:Src/main.c **** + 6360 .loc 1 822 26 is_stmt 0 view .LVU2024 + 6361 0004 0023 movs r3, #0 + 6362 0006 0093 str r3, [sp] + 6363 0008 0193 str r3, [sp, #4] + 6364 000a 0293 str r3, [sp, #8] + 6365 000c 0393 str r3, [sp, #12] + 830:Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; + 6366 .loc 1 830 3 is_stmt 1 view .LVU2025 + 830:Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; + 6367 .loc 1 830 18 is_stmt 0 view .LVU2026 + 6368 000e 2B48 ldr r0, .L295 + 6369 0010 2B4A ldr r2, .L295+4 + 6370 0012 0260 str r2, [r0] + 831:Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; + 6371 .loc 1 831 3 is_stmt 1 view .LVU2027 + ARM GAS /tmp/ccWQNJQt.s page 480 + + + 831:Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B; + 6372 .loc 1 831 29 is_stmt 0 view .LVU2028 + 6373 0014 4FF44032 mov r2, #196608 + 6374 0018 4260 str r2, [r0, #4] + 832:Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; + 6375 .loc 1 832 3 is_stmt 1 view .LVU2029 + 832:Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; + 6376 .loc 1 832 25 is_stmt 0 view .LVU2030 + 6377 001a 8360 str r3, [r0, #8] + 833:Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; + 6378 .loc 1 833 3 is_stmt 1 view .LVU2031 + 833:Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; + 6379 .loc 1 833 27 is_stmt 0 view .LVU2032 + 6380 001c 0122 movs r2, #1 + 6381 001e 0261 str r2, [r0, #16] + 834:Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; + 6382 .loc 1 834 3 is_stmt 1 view .LVU2033 + 834:Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; + 6383 .loc 1 834 33 is_stmt 0 view .LVU2034 + 6384 0020 8361 str r3, [r0, #24] + 835:Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + 6385 .loc 1 835 3 is_stmt 1 view .LVU2035 + 835:Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + 6386 .loc 1 835 36 is_stmt 0 view .LVU2036 + 6387 0022 80F82030 strb r3, [r0, #32] + 836:Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; + 6388 .loc 1 836 3 is_stmt 1 view .LVU2037 + 836:Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; + 6389 .loc 1 836 35 is_stmt 0 view .LVU2038 + 6390 0026 C362 str r3, [r0, #44] + 837:Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + 6391 .loc 1 837 3 is_stmt 1 view .LVU2039 + 837:Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + 6392 .loc 1 837 31 is_stmt 0 view .LVU2040 + 6393 0028 2649 ldr r1, .L295+8 + 6394 002a 8162 str r1, [r0, #40] + 838:Src/main.c **** hadc1.Init.NbrOfConversion = 5; + 6395 .loc 1 838 3 is_stmt 1 view .LVU2041 + 838:Src/main.c **** hadc1.Init.NbrOfConversion = 5; + 6396 .loc 1 838 24 is_stmt 0 view .LVU2042 + 6397 002c C360 str r3, [r0, #12] + 839:Src/main.c **** hadc1.Init.DMAContinuousRequests = DISABLE; + 6398 .loc 1 839 3 is_stmt 1 view .LVU2043 + 839:Src/main.c **** hadc1.Init.DMAContinuousRequests = DISABLE; + 6399 .loc 1 839 30 is_stmt 0 view .LVU2044 + 6400 002e 0521 movs r1, #5 + 6401 0030 C161 str r1, [r0, #28] + 840:Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + 6402 .loc 1 840 3 is_stmt 1 view .LVU2045 + 840:Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + 6403 .loc 1 840 36 is_stmt 0 view .LVU2046 + 6404 0032 80F83030 strb r3, [r0, #48] + 841:Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) + 6405 .loc 1 841 3 is_stmt 1 view .LVU2047 + 841:Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) + 6406 .loc 1 841 27 is_stmt 0 view .LVU2048 + 6407 0036 4261 str r2, [r0, #20] + ARM GAS /tmp/ccWQNJQt.s page 481 + + + 842:Src/main.c **** { + 6408 .loc 1 842 3 is_stmt 1 view .LVU2049 + 842:Src/main.c **** { + 6409 .loc 1 842 7 is_stmt 0 view .LVU2050 + 6410 0038 FFF7FEFF bl HAL_ADC_Init + 6411 .LVL529: + 842:Src/main.c **** { + 6412 .loc 1 842 6 discriminator 1 view .LVU2051 + 6413 003c 0028 cmp r0, #0 + 6414 003e 31D1 bne .L289 + 849:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; + 6415 .loc 1 849 3 is_stmt 1 view .LVU2052 + 849:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; + 6416 .loc 1 849 19 is_stmt 0 view .LVU2053 + 6417 0040 0923 movs r3, #9 + 6418 0042 0093 str r3, [sp] + 850:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; + 6419 .loc 1 850 3 is_stmt 1 view .LVU2054 + 850:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; + 6420 .loc 1 850 16 is_stmt 0 view .LVU2055 + 6421 0044 0123 movs r3, #1 + 6422 0046 0193 str r3, [sp, #4] + 851:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 6423 .loc 1 851 3 is_stmt 1 view .LVU2056 + 851:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 6424 .loc 1 851 24 is_stmt 0 view .LVU2057 + 6425 0048 0723 movs r3, #7 + 6426 004a 0293 str r3, [sp, #8] + 852:Src/main.c **** { + 6427 .loc 1 852 3 is_stmt 1 view .LVU2058 + 852:Src/main.c **** { + 6428 .loc 1 852 7 is_stmt 0 view .LVU2059 + 6429 004c 6946 mov r1, sp + 6430 004e 1B48 ldr r0, .L295 + 6431 0050 FFF7FEFF bl HAL_ADC_ConfigChannel + 6432 .LVL530: + 852:Src/main.c **** { + 6433 .loc 1 852 6 discriminator 1 view .LVU2060 + 6434 0054 40BB cbnz r0, .L290 + 859:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_2; + 6435 .loc 1 859 3 is_stmt 1 view .LVU2061 + 859:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_2; + 6436 .loc 1 859 19 is_stmt 0 view .LVU2062 + 6437 0056 0823 movs r3, #8 + 6438 0058 0093 str r3, [sp] + 860:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 6439 .loc 1 860 3 is_stmt 1 view .LVU2063 + 860:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 6440 .loc 1 860 16 is_stmt 0 view .LVU2064 + 6441 005a 0223 movs r3, #2 + 6442 005c 0193 str r3, [sp, #4] + 861:Src/main.c **** { + 6443 .loc 1 861 3 is_stmt 1 view .LVU2065 + 861:Src/main.c **** { + 6444 .loc 1 861 7 is_stmt 0 view .LVU2066 + 6445 005e 6946 mov r1, sp + 6446 0060 1648 ldr r0, .L295 + ARM GAS /tmp/ccWQNJQt.s page 482 + + + 6447 0062 FFF7FEFF bl HAL_ADC_ConfigChannel + 6448 .LVL531: + 861:Src/main.c **** { + 6449 .loc 1 861 6 discriminator 1 view .LVU2067 + 6450 0066 08BB cbnz r0, .L291 + 868:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_3; + 6451 .loc 1 868 3 is_stmt 1 view .LVU2068 + 868:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_3; + 6452 .loc 1 868 19 is_stmt 0 view .LVU2069 + 6453 0068 0223 movs r3, #2 + 6454 006a 0093 str r3, [sp] + 869:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 6455 .loc 1 869 3 is_stmt 1 view .LVU2070 + 869:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 6456 .loc 1 869 16 is_stmt 0 view .LVU2071 + 6457 006c 0323 movs r3, #3 + 6458 006e 0193 str r3, [sp, #4] + 870:Src/main.c **** { + 6459 .loc 1 870 3 is_stmt 1 view .LVU2072 + 870:Src/main.c **** { + 6460 .loc 1 870 7 is_stmt 0 view .LVU2073 + 6461 0070 6946 mov r1, sp + 6462 0072 1248 ldr r0, .L295 + 6463 0074 FFF7FEFF bl HAL_ADC_ConfigChannel + 6464 .LVL532: + 870:Src/main.c **** { + 6465 .loc 1 870 6 discriminator 1 view .LVU2074 + 6466 0078 D0B9 cbnz r0, .L292 + 877:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_4; + 6467 .loc 1 877 3 is_stmt 1 view .LVU2075 + 877:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_4; + 6468 .loc 1 877 19 is_stmt 0 view .LVU2076 + 6469 007a 0A23 movs r3, #10 + 6470 007c 0093 str r3, [sp] + 878:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 6471 .loc 1 878 3 is_stmt 1 view .LVU2077 + 878:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 6472 .loc 1 878 16 is_stmt 0 view .LVU2078 + 6473 007e 0423 movs r3, #4 + 6474 0080 0193 str r3, [sp, #4] + 879:Src/main.c **** { + 6475 .loc 1 879 3 is_stmt 1 view .LVU2079 + 879:Src/main.c **** { + 6476 .loc 1 879 7 is_stmt 0 view .LVU2080 + 6477 0082 6946 mov r1, sp + 6478 0084 0D48 ldr r0, .L295 + 6479 0086 FFF7FEFF bl HAL_ADC_ConfigChannel + 6480 .LVL533: + 879:Src/main.c **** { + 6481 .loc 1 879 6 discriminator 1 view .LVU2081 + 6482 008a 98B9 cbnz r0, .L293 + 886:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_5; + 6483 .loc 1 886 3 is_stmt 1 view .LVU2082 + 886:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_5; + 6484 .loc 1 886 19 is_stmt 0 view .LVU2083 + 6485 008c 0B23 movs r3, #11 + 6486 008e 0093 str r3, [sp] + ARM GAS /tmp/ccWQNJQt.s page 483 + + + 887:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 6487 .loc 1 887 3 is_stmt 1 view .LVU2084 + 887:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 6488 .loc 1 887 16 is_stmt 0 view .LVU2085 + 6489 0090 0523 movs r3, #5 + 6490 0092 0193 str r3, [sp, #4] + 888:Src/main.c **** { + 6491 .loc 1 888 3 is_stmt 1 view .LVU2086 + 888:Src/main.c **** { + 6492 .loc 1 888 7 is_stmt 0 view .LVU2087 + 6493 0094 6946 mov r1, sp + 6494 0096 0948 ldr r0, .L295 + 6495 0098 FFF7FEFF bl HAL_ADC_ConfigChannel + 6496 .LVL534: + 888:Src/main.c **** { + 6497 .loc 1 888 6 discriminator 1 view .LVU2088 + 6498 009c 60B9 cbnz r0, .L294 + 896:Src/main.c **** + 6499 .loc 1 896 1 view .LVU2089 + 6500 009e 05B0 add sp, sp, #20 + 6501 .LCFI52: + 6502 .cfi_remember_state + 6503 .cfi_def_cfa_offset 4 + 6504 @ sp needed + 6505 00a0 5DF804FB ldr pc, [sp], #4 + 6506 .L289: + 6507 .LCFI53: + 6508 .cfi_restore_state + 844:Src/main.c **** } + 6509 .loc 1 844 5 is_stmt 1 view .LVU2090 + 6510 00a4 FFF7FEFF bl Error_Handler + 6511 .LVL535: + 6512 .L290: + 854:Src/main.c **** } + 6513 .loc 1 854 5 view .LVU2091 + 6514 00a8 FFF7FEFF bl Error_Handler + 6515 .LVL536: + 6516 .L291: + 863:Src/main.c **** } + 6517 .loc 1 863 5 view .LVU2092 + 6518 00ac FFF7FEFF bl Error_Handler + 6519 .LVL537: + 6520 .L292: + 872:Src/main.c **** } + 6521 .loc 1 872 5 view .LVU2093 + 6522 00b0 FFF7FEFF bl Error_Handler + 6523 .LVL538: + 6524 .L293: + 881:Src/main.c **** } + 6525 .loc 1 881 5 view .LVU2094 + 6526 00b4 FFF7FEFF bl Error_Handler + 6527 .LVL539: + 6528 .L294: + 890:Src/main.c **** } + 6529 .loc 1 890 5 view .LVU2095 + 6530 00b8 FFF7FEFF bl Error_Handler + 6531 .LVL540: + ARM GAS /tmp/ccWQNJQt.s page 484 + + + 6532 .L296: + 6533 .align 2 + 6534 .L295: + 6535 00bc 00000000 .word hadc1 + 6536 00c0 00200140 .word 1073815552 + 6537 00c4 0100000F .word 251658241 + 6538 .cfi_endproc + 6539 .LFE1188: + 6541 .section .text.MX_ADC3_Init,"ax",%progbits + 6542 .align 1 + 6543 .syntax unified + 6544 .thumb + 6545 .thumb_func + 6547 MX_ADC3_Init: + 6548 .LFB1189: + 904:Src/main.c **** + 6549 .loc 1 904 1 view -0 + 6550 .cfi_startproc + 6551 @ args = 0, pretend = 0, frame = 16 + 6552 @ frame_needed = 0, uses_anonymous_args = 0 + 6553 0000 00B5 push {lr} + 6554 .LCFI54: + 6555 .cfi_def_cfa_offset 4 + 6556 .cfi_offset 14, -4 + 6557 0002 85B0 sub sp, sp, #20 + 6558 .LCFI55: + 6559 .cfi_def_cfa_offset 24 + 910:Src/main.c **** + 6560 .loc 1 910 3 view .LVU2097 + 910:Src/main.c **** + 6561 .loc 1 910 26 is_stmt 0 view .LVU2098 + 6562 0004 0023 movs r3, #0 + 6563 0006 0093 str r3, [sp] + 6564 0008 0193 str r3, [sp, #4] + 6565 000a 0293 str r3, [sp, #8] + 6566 000c 0393 str r3, [sp, #12] + 918:Src/main.c **** hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; + 6567 .loc 1 918 3 is_stmt 1 view .LVU2099 + 918:Src/main.c **** hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV8; + 6568 .loc 1 918 18 is_stmt 0 view .LVU2100 + 6569 000e 1448 ldr r0, .L303 + 6570 0010 144A ldr r2, .L303+4 + 6571 0012 0260 str r2, [r0] + 919:Src/main.c **** hadc3.Init.Resolution = ADC_RESOLUTION_12B; + 6572 .loc 1 919 3 is_stmt 1 view .LVU2101 + 919:Src/main.c **** hadc3.Init.Resolution = ADC_RESOLUTION_12B; + 6573 .loc 1 919 29 is_stmt 0 view .LVU2102 + 6574 0014 4FF44032 mov r2, #196608 + 6575 0018 4260 str r2, [r0, #4] + 920:Src/main.c **** hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; + 6576 .loc 1 920 3 is_stmt 1 view .LVU2103 + 920:Src/main.c **** hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; + 6577 .loc 1 920 25 is_stmt 0 view .LVU2104 + 6578 001a 8360 str r3, [r0, #8] + 921:Src/main.c **** hadc3.Init.ContinuousConvMode = DISABLE; + 6579 .loc 1 921 3 is_stmt 1 view .LVU2105 + 921:Src/main.c **** hadc3.Init.ContinuousConvMode = DISABLE; + ARM GAS /tmp/ccWQNJQt.s page 485 + + + 6580 .loc 1 921 27 is_stmt 0 view .LVU2106 + 6581 001c 0361 str r3, [r0, #16] + 922:Src/main.c **** hadc3.Init.DiscontinuousConvMode = DISABLE; + 6582 .loc 1 922 3 is_stmt 1 view .LVU2107 + 922:Src/main.c **** hadc3.Init.DiscontinuousConvMode = DISABLE; + 6583 .loc 1 922 33 is_stmt 0 view .LVU2108 + 6584 001e 8361 str r3, [r0, #24] + 923:Src/main.c **** hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + 6585 .loc 1 923 3 is_stmt 1 view .LVU2109 + 923:Src/main.c **** hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + 6586 .loc 1 923 36 is_stmt 0 view .LVU2110 + 6587 0020 80F82030 strb r3, [r0, #32] + 924:Src/main.c **** hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; + 6588 .loc 1 924 3 is_stmt 1 view .LVU2111 + 924:Src/main.c **** hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; + 6589 .loc 1 924 35 is_stmt 0 view .LVU2112 + 6590 0024 C362 str r3, [r0, #44] + 925:Src/main.c **** hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; + 6591 .loc 1 925 3 is_stmt 1 view .LVU2113 + 925:Src/main.c **** hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; + 6592 .loc 1 925 31 is_stmt 0 view .LVU2114 + 6593 0026 104A ldr r2, .L303+8 + 6594 0028 8262 str r2, [r0, #40] + 926:Src/main.c **** hadc3.Init.NbrOfConversion = 1; + 6595 .loc 1 926 3 is_stmt 1 view .LVU2115 + 926:Src/main.c **** hadc3.Init.NbrOfConversion = 1; + 6596 .loc 1 926 24 is_stmt 0 view .LVU2116 + 6597 002a C360 str r3, [r0, #12] + 927:Src/main.c **** hadc3.Init.DMAContinuousRequests = DISABLE; + 6598 .loc 1 927 3 is_stmt 1 view .LVU2117 + 927:Src/main.c **** hadc3.Init.DMAContinuousRequests = DISABLE; + 6599 .loc 1 927 30 is_stmt 0 view .LVU2118 + 6600 002c 0122 movs r2, #1 + 6601 002e C261 str r2, [r0, #28] + 928:Src/main.c **** hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + 6602 .loc 1 928 3 is_stmt 1 view .LVU2119 + 928:Src/main.c **** hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + 6603 .loc 1 928 36 is_stmt 0 view .LVU2120 + 6604 0030 80F83030 strb r3, [r0, #48] + 929:Src/main.c **** if (HAL_ADC_Init(&hadc3) != HAL_OK) + 6605 .loc 1 929 3 is_stmt 1 view .LVU2121 + 929:Src/main.c **** if (HAL_ADC_Init(&hadc3) != HAL_OK) + 6606 .loc 1 929 27 is_stmt 0 view .LVU2122 + 6607 0034 4261 str r2, [r0, #20] + 930:Src/main.c **** { + 6608 .loc 1 930 3 is_stmt 1 view .LVU2123 + 930:Src/main.c **** { + 6609 .loc 1 930 7 is_stmt 0 view .LVU2124 + 6610 0036 FFF7FEFF bl HAL_ADC_Init + 6611 .LVL541: + 930:Src/main.c **** { + 6612 .loc 1 930 6 discriminator 1 view .LVU2125 + 6613 003a 68B9 cbnz r0, .L301 + 937:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; + 6614 .loc 1 937 3 is_stmt 1 view .LVU2126 + 937:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; + 6615 .loc 1 937 19 is_stmt 0 view .LVU2127 + ARM GAS /tmp/ccWQNJQt.s page 486 + + + 6616 003c 0F23 movs r3, #15 + 6617 003e 0093 str r3, [sp] + 938:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; + 6618 .loc 1 938 3 is_stmt 1 view .LVU2128 + 938:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_480CYCLES; + 6619 .loc 1 938 16 is_stmt 0 view .LVU2129 + 6620 0040 0123 movs r3, #1 + 6621 0042 0193 str r3, [sp, #4] + 939:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) + 6622 .loc 1 939 3 is_stmt 1 view .LVU2130 + 939:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) + 6623 .loc 1 939 24 is_stmt 0 view .LVU2131 + 6624 0044 0723 movs r3, #7 + 6625 0046 0293 str r3, [sp, #8] + 940:Src/main.c **** { + 6626 .loc 1 940 3 is_stmt 1 view .LVU2132 + 940:Src/main.c **** { + 6627 .loc 1 940 7 is_stmt 0 view .LVU2133 + 6628 0048 6946 mov r1, sp + 6629 004a 0548 ldr r0, .L303 + 6630 004c FFF7FEFF bl HAL_ADC_ConfigChannel + 6631 .LVL542: + 940:Src/main.c **** { + 6632 .loc 1 940 6 discriminator 1 view .LVU2134 + 6633 0050 20B9 cbnz r0, .L302 + 948:Src/main.c **** + 6634 .loc 1 948 1 view .LVU2135 + 6635 0052 05B0 add sp, sp, #20 + 6636 .LCFI56: + 6637 .cfi_remember_state + 6638 .cfi_def_cfa_offset 4 + 6639 @ sp needed + 6640 0054 5DF804FB ldr pc, [sp], #4 + 6641 .L301: + 6642 .LCFI57: + 6643 .cfi_restore_state + 932:Src/main.c **** } + 6644 .loc 1 932 5 is_stmt 1 view .LVU2136 + 6645 0058 FFF7FEFF bl Error_Handler + 6646 .LVL543: + 6647 .L302: + 942:Src/main.c **** } + 6648 .loc 1 942 5 view .LVU2137 + 6649 005c FFF7FEFF bl Error_Handler + 6650 .LVL544: + 6651 .L304: + 6652 .align 2 + 6653 .L303: + 6654 0060 00000000 .word hadc3 + 6655 0064 00220140 .word 1073816064 + 6656 0068 0100000F .word 251658241 + 6657 .cfi_endproc + 6658 .LFE1189: + 6660 .section .text.MX_USART1_UART_Init,"ax",%progbits + 6661 .align 1 + 6662 .syntax unified + 6663 .thumb + ARM GAS /tmp/ccWQNJQt.s page 487 + + + 6664 .thumb_func + 6666 MX_USART1_UART_Init: + 6667 .LFB1204: +1606:Src/main.c **** + 6668 .loc 1 1606 1 view -0 + 6669 .cfi_startproc + 6670 @ args = 0, pretend = 0, frame = 208 + 6671 @ frame_needed = 0, uses_anonymous_args = 0 + 6672 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 6673 .LCFI58: + 6674 .cfi_def_cfa_offset 24 + 6675 .cfi_offset 4, -24 + 6676 .cfi_offset 5, -20 + 6677 .cfi_offset 6, -16 + 6678 .cfi_offset 7, -12 + 6679 .cfi_offset 8, -8 + 6680 .cfi_offset 14, -4 + 6681 0004 B4B0 sub sp, sp, #208 + 6682 .LCFI59: + 6683 .cfi_def_cfa_offset 232 +1612:Src/main.c **** + 6684 .loc 1 1612 3 view .LVU2139 +1612:Src/main.c **** + 6685 .loc 1 1612 24 is_stmt 0 view .LVU2140 + 6686 0006 0021 movs r1, #0 + 6687 0008 2D91 str r1, [sp, #180] + 6688 000a 2E91 str r1, [sp, #184] + 6689 000c 2F91 str r1, [sp, #188] + 6690 000e 3091 str r1, [sp, #192] + 6691 0010 3191 str r1, [sp, #196] + 6692 0012 3291 str r1, [sp, #200] + 6693 0014 3391 str r1, [sp, #204] +1614:Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 6694 .loc 1 1614 3 is_stmt 1 view .LVU2141 +1614:Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 6695 .loc 1 1614 23 is_stmt 0 view .LVU2142 + 6696 0016 2791 str r1, [sp, #156] + 6697 0018 2891 str r1, [sp, #160] + 6698 001a 2991 str r1, [sp, #164] + 6699 001c 2A91 str r1, [sp, #168] + 6700 001e 2B91 str r1, [sp, #172] + 6701 0020 2C91 str r1, [sp, #176] +1615:Src/main.c **** + 6702 .loc 1 1615 3 is_stmt 1 view .LVU2143 +1615:Src/main.c **** + 6703 .loc 1 1615 28 is_stmt 0 view .LVU2144 + 6704 0022 9022 movs r2, #144 + 6705 0024 03A8 add r0, sp, #12 + 6706 0026 FFF7FEFF bl memset + 6707 .LVL545: +1619:Src/main.c **** PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + 6708 .loc 1 1619 3 is_stmt 1 view .LVU2145 +1619:Src/main.c **** PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + 6709 .loc 1 1619 44 is_stmt 0 view .LVU2146 + 6710 002a 4023 movs r3, #64 + 6711 002c 0393 str r3, [sp, #12] +1620:Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + ARM GAS /tmp/ccWQNJQt.s page 488 + + + 6712 .loc 1 1620 3 is_stmt 1 view .LVU2147 +1621:Src/main.c **** { + 6713 .loc 1 1621 3 view .LVU2148 +1621:Src/main.c **** { + 6714 .loc 1 1621 7 is_stmt 0 view .LVU2149 + 6715 002e 03A8 add r0, sp, #12 + 6716 0030 FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig + 6717 .LVL546: +1621:Src/main.c **** { + 6718 .loc 1 1621 6 discriminator 1 view .LVU2150 + 6719 0034 0028 cmp r0, #0 + 6720 0036 40F09E80 bne .L308 +1627:Src/main.c **** + 6721 .loc 1 1627 3 is_stmt 1 view .LVU2151 + 6722 .LVL547: + 6723 .LBB513: + 6724 .LBI513: +1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 6725 .loc 3 1587 22 view .LVU2152 + 6726 .LBB514: +1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); + 6727 .loc 3 1589 3 view .LVU2153 +1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 6728 .loc 3 1590 3 view .LVU2154 + 6729 003a 504B ldr r3, .L309 + 6730 003c 5A6C ldr r2, [r3, #68] + 6731 003e 42F01002 orr r2, r2, #16 + 6732 0042 5A64 str r2, [r3, #68] +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 6733 .loc 3 1592 3 view .LVU2155 +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 6734 .loc 3 1592 12 is_stmt 0 view .LVU2156 + 6735 0044 5A6C ldr r2, [r3, #68] + 6736 0046 02F01002 and r2, r2, #16 +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 6737 .loc 3 1592 10 view .LVU2157 + 6738 004a 0292 str r2, [sp, #8] + 6739 .loc 3 1593 3 is_stmt 1 view .LVU2158 + 6740 004c 029A ldr r2, [sp, #8] + 6741 .LVL548: + 6742 .loc 3 1593 3 is_stmt 0 view .LVU2159 + 6743 .LBE514: + 6744 .LBE513: +1629:Src/main.c **** /**USART1 GPIO Configuration + 6745 .loc 1 1629 3 is_stmt 1 view .LVU2160 + 6746 .LBB515: + 6747 .LBI515: + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 6748 .loc 3 309 22 view .LVU2161 + 6749 .LBB516: + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); + 6750 .loc 3 311 3 view .LVU2162 + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 6751 .loc 3 312 3 view .LVU2163 + 6752 004e 1A6B ldr r2, [r3, #48] + 6753 0050 42F00102 orr r2, r2, #1 + 6754 0054 1A63 str r2, [r3, #48] + ARM GAS /tmp/ccWQNJQt.s page 489 + + + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 6755 .loc 3 314 3 view .LVU2164 + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 6756 .loc 3 314 12 is_stmt 0 view .LVU2165 + 6757 0056 1B6B ldr r3, [r3, #48] + 6758 0058 03F00103 and r3, r3, #1 + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 6759 .loc 3 314 10 view .LVU2166 + 6760 005c 0193 str r3, [sp, #4] + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 6761 .loc 3 315 3 is_stmt 1 view .LVU2167 + 6762 005e 019B ldr r3, [sp, #4] + 6763 .LVL549: + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 6764 .loc 3 315 3 is_stmt 0 view .LVU2168 + 6765 .LBE516: + 6766 .LBE515: +1634:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 6767 .loc 1 1634 3 is_stmt 1 view .LVU2169 +1634:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 6768 .loc 1 1634 23 is_stmt 0 view .LVU2170 + 6769 0060 4FF40073 mov r3, #512 + 6770 0064 2793 str r3, [sp, #156] +1635:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 6771 .loc 1 1635 3 is_stmt 1 view .LVU2171 +1635:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 6772 .loc 1 1635 24 is_stmt 0 view .LVU2172 + 6773 0066 4FF00208 mov r8, #2 + 6774 006a CDF8A080 str r8, [sp, #160] +1636:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 6775 .loc 1 1636 3 is_stmt 1 view .LVU2173 +1636:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 6776 .loc 1 1636 25 is_stmt 0 view .LVU2174 + 6777 006e 0327 movs r7, #3 + 6778 0070 2997 str r7, [sp, #164] +1637:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 6779 .loc 1 1637 3 is_stmt 1 view .LVU2175 +1637:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 6780 .loc 1 1637 30 is_stmt 0 view .LVU2176 + 6781 0072 0024 movs r4, #0 + 6782 0074 2A94 str r4, [sp, #168] +1638:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; + 6783 .loc 1 1638 3 is_stmt 1 view .LVU2177 +1638:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; + 6784 .loc 1 1638 24 is_stmt 0 view .LVU2178 + 6785 0076 2B94 str r4, [sp, #172] +1639:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 6786 .loc 1 1639 3 is_stmt 1 view .LVU2179 +1639:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 6787 .loc 1 1639 29 is_stmt 0 view .LVU2180 + 6788 0078 0726 movs r6, #7 + 6789 007a 2C96 str r6, [sp, #176] +1640:Src/main.c **** + 6790 .loc 1 1640 3 is_stmt 1 view .LVU2181 + 6791 007c 404D ldr r5, .L309+4 + 6792 007e 27A9 add r1, sp, #156 + 6793 0080 2846 mov r0, r5 + ARM GAS /tmp/ccWQNJQt.s page 490 + + + 6794 0082 FFF7FEFF bl LL_GPIO_Init + 6795 .LVL550: +1642:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 6796 .loc 1 1642 3 view .LVU2182 +1642:Src/main.c **** GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 6797 .loc 1 1642 23 is_stmt 0 view .LVU2183 + 6798 0086 4FF48063 mov r3, #1024 + 6799 008a 2793 str r3, [sp, #156] +1643:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 6800 .loc 1 1643 3 is_stmt 1 view .LVU2184 +1643:Src/main.c **** GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 6801 .loc 1 1643 24 is_stmt 0 view .LVU2185 + 6802 008c CDF8A080 str r8, [sp, #160] +1644:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 6803 .loc 1 1644 3 is_stmt 1 view .LVU2186 +1644:Src/main.c **** GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 6804 .loc 1 1644 25 is_stmt 0 view .LVU2187 + 6805 0090 2997 str r7, [sp, #164] +1645:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 6806 .loc 1 1645 3 is_stmt 1 view .LVU2188 +1645:Src/main.c **** GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 6807 .loc 1 1645 30 is_stmt 0 view .LVU2189 + 6808 0092 2A94 str r4, [sp, #168] +1646:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; + 6809 .loc 1 1646 3 is_stmt 1 view .LVU2190 +1646:Src/main.c **** GPIO_InitStruct.Alternate = LL_GPIO_AF_7; + 6810 .loc 1 1646 24 is_stmt 0 view .LVU2191 + 6811 0094 2B94 str r4, [sp, #172] +1647:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 6812 .loc 1 1647 3 is_stmt 1 view .LVU2192 +1647:Src/main.c **** LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 6813 .loc 1 1647 29 is_stmt 0 view .LVU2193 + 6814 0096 2C96 str r6, [sp, #176] +1648:Src/main.c **** + 6815 .loc 1 1648 3 is_stmt 1 view .LVU2194 + 6816 0098 27A9 add r1, sp, #156 + 6817 009a 2846 mov r0, r5 + 6818 009c FFF7FEFF bl LL_GPIO_Init + 6819 .LVL551: +1653:Src/main.c **** + 6820 .loc 1 1653 3 view .LVU2195 + 6821 .LBB517: + 6822 .LBI517: +1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 6823 .loc 6 1032 22 view .LVU2196 + 6824 .LBB518: +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6825 .loc 6 1034 3 view .LVU2197 + 6826 00a0 384B ldr r3, .L309+8 + 6827 00a2 D3F8B820 ldr r2, [r3, #184] + 6828 00a6 22F0F052 bic r2, r2, #503316480 + 6829 00aa 42F00062 orr r2, r2, #134217728 + 6830 00ae C3F8B820 str r2, [r3, #184] + 6831 .LVL552: +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6832 .loc 6 1034 3 is_stmt 0 view .LVU2198 + 6833 .LBE518: + ARM GAS /tmp/ccWQNJQt.s page 491 + + + 6834 .LBE517: +1655:Src/main.c **** + 6835 .loc 1 1655 3 is_stmt 1 view .LVU2199 + 6836 .LBB519: + 6837 .LBI519: + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 6838 .loc 6 598 22 view .LVU2200 + 6839 .LBB520: + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6840 .loc 6 600 3 view .LVU2201 + 6841 00b2 D3F8B820 ldr r2, [r3, #184] + 6842 00b6 22F0C002 bic r2, r2, #192 + 6843 00ba 42F04002 orr r2, r2, #64 + 6844 00be C3F8B820 str r2, [r3, #184] + 6845 .LVL553: + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6846 .loc 6 600 3 is_stmt 0 view .LVU2202 + 6847 .LBE520: + 6848 .LBE519: +1657:Src/main.c **** + 6849 .loc 1 1657 3 is_stmt 1 view .LVU2203 + 6850 .LBB521: + 6851 .LBI521: + 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 6852 .loc 6 924 22 view .LVU2204 + 6853 .LBB522: + 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6854 .loc 6 926 3 view .LVU2205 + 6855 00c2 D3F8B820 ldr r2, [r3, #184] + 6856 00c6 42F44032 orr r2, r2, #196608 + 6857 00ca C3F8B820 str r2, [r3, #184] + 6858 .LVL554: + 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6859 .loc 6 926 3 is_stmt 0 view .LVU2206 + 6860 .LBE522: + 6861 .LBE521: +1659:Src/main.c **** + 6862 .loc 1 1659 3 is_stmt 1 view .LVU2207 + 6863 .LBB523: + 6864 .LBI523: + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 6865 .loc 6 646 22 view .LVU2208 + 6866 .LBB524: + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6867 .loc 6 648 3 view .LVU2209 + 6868 00ce D3F8B820 ldr r2, [r3, #184] + 6869 00d2 22F49072 bic r2, r2, #288 + 6870 00d6 C3F8B820 str r2, [r3, #184] + 6871 .LVL555: + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6872 .loc 6 648 3 is_stmt 0 view .LVU2210 + 6873 .LBE524: + 6874 .LBE523: +1661:Src/main.c **** + 6875 .loc 1 1661 3 is_stmt 1 view .LVU2211 + 6876 .LBB525: + 6877 .LBI525: + ARM GAS /tmp/ccWQNJQt.s page 492 + + + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 6878 .loc 6 693 22 view .LVU2212 + 6879 .LBB526: + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6880 .loc 6 695 3 view .LVU2213 + 6881 00da D3F8B820 ldr r2, [r3, #184] + 6882 00de 22F40072 bic r2, r2, #512 + 6883 00e2 C3F8B820 str r2, [r3, #184] + 6884 .LVL556: + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6885 .loc 6 695 3 is_stmt 0 view .LVU2214 + 6886 .LBE526: + 6887 .LBE525: +1663:Src/main.c **** + 6888 .loc 1 1663 3 is_stmt 1 view .LVU2215 + 6889 .LBB527: + 6890 .LBI527: + 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 6891 .loc 6 738 22 view .LVU2216 + 6892 .LBB528: + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6893 .loc 6 740 3 view .LVU2217 + 6894 00e6 D3F8B820 ldr r2, [r3, #184] + 6895 00ea 42F48062 orr r2, r2, #1024 + 6896 00ee C3F8B820 str r2, [r3, #184] + 6897 .LVL557: + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6898 .loc 6 740 3 is_stmt 0 view .LVU2218 + 6899 .LBE528: + 6900 .LBE527: +1665:Src/main.c **** + 6901 .loc 1 1665 3 is_stmt 1 view .LVU2219 + 6902 .LBB529: + 6903 .LBI529: + 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 6904 .loc 6 784 22 view .LVU2220 + 6905 .LBB530: + 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6906 .loc 6 786 3 view .LVU2221 + 6907 00f2 D3F8B820 ldr r2, [r3, #184] + 6908 00f6 22F4C052 bic r2, r2, #6144 + 6909 00fa C3F8B820 str r2, [r3, #184] + 6910 .LVL558: + 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6911 .loc 6 786 3 is_stmt 0 view .LVU2222 + 6912 .LBE530: + 6913 .LBE529: +1667:Src/main.c **** + 6914 .loc 1 1667 3 is_stmt 1 view .LVU2223 + 6915 .LBB531: + 6916 .LBI531: + 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 6917 .loc 6 831 22 view .LVU2224 + 6918 .LBB532: + 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6919 .loc 6 833 3 view .LVU2225 + 6920 00fe D3F8B820 ldr r2, [r3, #184] + ARM GAS /tmp/ccWQNJQt.s page 493 + + + 6921 0102 22F4C042 bic r2, r2, #24576 + 6922 0106 C3F8B820 str r2, [r3, #184] + 6923 .LVL559: + 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6924 .loc 6 833 3 is_stmt 0 view .LVU2226 + 6925 .LBE532: + 6926 .LBE531: +1669:Src/main.c **** + 6927 .loc 1 1669 3 is_stmt 1 view .LVU2227 + 6928 .LBB533: + 6929 .LBI533: +1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 6930 .loc 6 1299 22 view .LVU2228 + 6931 .LBB534: +1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6932 .loc 6 1301 3 view .LVU2229 + 6933 010a D3F8CC20 ldr r2, [r3, #204] + 6934 010e 22F00402 bic r2, r2, #4 + 6935 0112 C3F8CC20 str r2, [r3, #204] + 6936 .LVL560: +1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 6937 .loc 6 1301 3 is_stmt 0 view .LVU2230 + 6938 .LBE534: + 6939 .LBE533: +1672:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn); + 6940 .loc 1 1672 3 is_stmt 1 view .LVU2231 + 6941 .LBB535: + 6942 .LBI535: +1884:Drivers/CMSIS/Include/core_cm7.h **** { + 6943 .loc 2 1884 26 view .LVU2232 + 6944 .LBB536: +1886:Drivers/CMSIS/Include/core_cm7.h **** } + 6945 .loc 2 1886 3 view .LVU2233 +1886:Drivers/CMSIS/Include/core_cm7.h **** } + 6946 .loc 2 1886 26 is_stmt 0 view .LVU2234 + 6947 0116 1C4B ldr r3, .L309+12 + 6948 0118 D868 ldr r0, [r3, #12] + 6949 .LBE536: + 6950 .LBE535: +1672:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn); + 6951 .loc 1 1672 3 discriminator 1 view .LVU2235 + 6952 011a 2246 mov r2, r4 + 6953 011c 2146 mov r1, r4 + 6954 011e C0F30220 ubfx r0, r0, #8, #3 + 6955 0122 FFF7FEFF bl NVIC_EncodePriority + 6956 .LVL561: + 6957 .LBB537: + 6958 .LBI537: +2024:Drivers/CMSIS/Include/core_cm7.h **** { + 6959 .loc 2 2024 22 is_stmt 1 view .LVU2236 + 6960 .LBB538: +2026:Drivers/CMSIS/Include/core_cm7.h **** { + 6961 .loc 2 2026 3 view .LVU2237 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 6962 .loc 2 2028 5 view .LVU2238 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 6963 .loc 2 2028 49 is_stmt 0 view .LVU2239 + ARM GAS /tmp/ccWQNJQt.s page 494 + + + 6964 0126 0001 lsls r0, r0, #4 + 6965 .LVL562: +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 6966 .loc 2 2028 49 view .LVU2240 + 6967 0128 C0B2 uxtb r0, r0 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 6968 .loc 2 2028 47 view .LVU2241 + 6969 012a 184B ldr r3, .L309+16 + 6970 012c 83F82503 strb r0, [r3, #805] + 6971 .LVL563: +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 6972 .loc 2 2028 47 view .LVU2242 + 6973 .LBE538: + 6974 .LBE537: +1673:Src/main.c **** + 6975 .loc 1 1673 3 is_stmt 1 view .LVU2243 + 6976 .LBB539: + 6977 .LBI539: +1896:Drivers/CMSIS/Include/core_cm7.h **** { + 6978 .loc 2 1896 22 view .LVU2244 + 6979 .LBB540: +1898:Drivers/CMSIS/Include/core_cm7.h **** { + 6980 .loc 2 1898 3 view .LVU2245 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 6981 .loc 2 1900 5 view .LVU2246 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 6982 .loc 2 1900 43 is_stmt 0 view .LVU2247 + 6983 0130 2022 movs r2, #32 + 6984 0132 5A60 str r2, [r3, #4] + 6985 .LVL564: +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 6986 .loc 2 1900 43 view .LVU2248 + 6987 .LBE540: + 6988 .LBE539: +1678:Src/main.c **** USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; + 6989 .loc 1 1678 3 is_stmt 1 view .LVU2249 +1678:Src/main.c **** USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; + 6990 .loc 1 1678 29 is_stmt 0 view .LVU2250 + 6991 0134 4FF4E133 mov r3, #115200 + 6992 0138 2D93 str r3, [sp, #180] +1679:Src/main.c **** USART_InitStruct.StopBits = LL_USART_STOPBITS_1; + 6993 .loc 1 1679 3 is_stmt 1 view .LVU2251 +1679:Src/main.c **** USART_InitStruct.StopBits = LL_USART_STOPBITS_1; + 6994 .loc 1 1679 30 is_stmt 0 view .LVU2252 + 6995 013a 2E94 str r4, [sp, #184] +1680:Src/main.c **** USART_InitStruct.Parity = LL_USART_PARITY_NONE; + 6996 .loc 1 1680 3 is_stmt 1 view .LVU2253 +1680:Src/main.c **** USART_InitStruct.Parity = LL_USART_PARITY_NONE; + 6997 .loc 1 1680 29 is_stmt 0 view .LVU2254 + 6998 013c 2F94 str r4, [sp, #188] +1681:Src/main.c **** USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; + 6999 .loc 1 1681 3 is_stmt 1 view .LVU2255 +1681:Src/main.c **** USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; + 7000 .loc 1 1681 27 is_stmt 0 view .LVU2256 + 7001 013e 3094 str r4, [sp, #192] +1682:Src/main.c **** USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; + 7002 .loc 1 1682 3 is_stmt 1 view .LVU2257 + ARM GAS /tmp/ccWQNJQt.s page 495 + + +1682:Src/main.c **** USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; + 7003 .loc 1 1682 38 is_stmt 0 view .LVU2258 + 7004 0140 0C23 movs r3, #12 + 7005 0142 3193 str r3, [sp, #196] +1683:Src/main.c **** USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; + 7006 .loc 1 1683 3 is_stmt 1 view .LVU2259 +1683:Src/main.c **** USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; + 7007 .loc 1 1683 40 is_stmt 0 view .LVU2260 + 7008 0144 3294 str r4, [sp, #200] +1684:Src/main.c **** LL_USART_Init(USART1, &USART_InitStruct); + 7009 .loc 1 1684 3 is_stmt 1 view .LVU2261 +1684:Src/main.c **** LL_USART_Init(USART1, &USART_InitStruct); + 7010 .loc 1 1684 33 is_stmt 0 view .LVU2262 + 7011 0146 3394 str r4, [sp, #204] +1685:Src/main.c **** LL_USART_ConfigAsyncMode(USART1); + 7012 .loc 1 1685 3 is_stmt 1 view .LVU2263 + 7013 0148 04F18044 add r4, r4, #1073741824 + 7014 014c 04F58834 add r4, r4, #69632 + 7015 0150 2DA9 add r1, sp, #180 + 7016 0152 2046 mov r0, r4 + 7017 0154 FFF7FEFF bl LL_USART_Init + 7018 .LVL565: +1686:Src/main.c **** LL_USART_Enable(USART1); + 7019 .loc 1 1686 3 view .LVU2264 + 7020 .LBB541: + 7021 .LBI541: +2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 7022 .loc 7 2320 22 view .LVU2265 + 7023 .LBB542: +2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); + 7024 .loc 7 2326 3 view .LVU2266 + 7025 0158 6368 ldr r3, [r4, #4] + 7026 015a 23F49043 bic r3, r3, #18432 + 7027 015e 6360 str r3, [r4, #4] +2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 7028 .loc 7 2327 3 view .LVU2267 + 7029 0160 A368 ldr r3, [r4, #8] + 7030 0162 23F02A03 bic r3, r3, #42 + 7031 0166 A360 str r3, [r4, #8] + 7032 .LVL566: +2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 7033 .loc 7 2327 3 is_stmt 0 view .LVU2268 + 7034 .LBE542: + 7035 .LBE541: +1687:Src/main.c **** /* USER CODE BEGIN USART1_Init 2 */ + 7036 .loc 1 1687 3 is_stmt 1 view .LVU2269 + 7037 .LBB543: + 7038 .LBI543: + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 7039 .loc 7 560 22 view .LVU2270 + 7040 .LBB544: + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 7041 .loc 7 562 3 view .LVU2271 + 7042 0168 2368 ldr r3, [r4] + 7043 016a 43F00103 orr r3, r3, #1 + 7044 016e 2360 str r3, [r4] + 7045 .LVL567: + ARM GAS /tmp/ccWQNJQt.s page 496 + + + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 7046 .loc 7 562 3 is_stmt 0 view .LVU2272 + 7047 .LBE544: + 7048 .LBE543: +1692:Src/main.c **** + 7049 .loc 1 1692 1 view .LVU2273 + 7050 0170 34B0 add sp, sp, #208 + 7051 .LCFI60: + 7052 .cfi_remember_state + 7053 .cfi_def_cfa_offset 24 + 7054 @ sp needed + 7055 0172 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 7056 .L308: + 7057 .LCFI61: + 7058 .cfi_restore_state +1623:Src/main.c **** } + 7059 .loc 1 1623 5 is_stmt 1 view .LVU2274 + 7060 0176 FFF7FEFF bl Error_Handler + 7061 .LVL568: + 7062 .L310: + 7063 017a 00BF .align 2 + 7064 .L309: + 7065 017c 00380240 .word 1073887232 + 7066 0180 00000240 .word 1073872896 + 7067 0184 00640240 .word 1073898496 + 7068 0188 00ED00E0 .word -536810240 + 7069 018c 00E100E0 .word -536813312 + 7070 .cfi_endproc + 7071 .LFE1204: + 7073 .section .text.MX_TIM10_Init,"ax",%progbits + 7074 .align 1 + 7075 .syntax unified + 7076 .thumb + 7077 .thumb_func + 7079 MX_TIM10_Init: + 7080 .LFB1201: +1494:Src/main.c **** + 7081 .loc 1 1494 1 view -0 + 7082 .cfi_startproc + 7083 @ args = 0, pretend = 0, frame = 0 + 7084 @ frame_needed = 0, uses_anonymous_args = 0 + 7085 0000 08B5 push {r3, lr} + 7086 .LCFI62: + 7087 .cfi_def_cfa_offset 8 + 7088 .cfi_offset 3, -8 + 7089 .cfi_offset 14, -4 +1503:Src/main.c **** htim10.Init.Prescaler = 183; + 7090 .loc 1 1503 3 view .LVU2276 +1503:Src/main.c **** htim10.Init.Prescaler = 183; + 7091 .loc 1 1503 19 is_stmt 0 view .LVU2277 + 7092 0002 0848 ldr r0, .L315 + 7093 0004 084B ldr r3, .L315+4 + 7094 0006 0360 str r3, [r0] +1504:Src/main.c **** htim10.Init.CounterMode = TIM_COUNTERMODE_UP; + 7095 .loc 1 1504 3 is_stmt 1 view .LVU2278 +1504:Src/main.c **** htim10.Init.CounterMode = TIM_COUNTERMODE_UP; + 7096 .loc 1 1504 25 is_stmt 0 view .LVU2279 + ARM GAS /tmp/ccWQNJQt.s page 497 + + + 7097 0008 B723 movs r3, #183 + 7098 000a 4360 str r3, [r0, #4] +1505:Src/main.c **** htim10.Init.Period = 9; + 7099 .loc 1 1505 3 is_stmt 1 view .LVU2280 +1505:Src/main.c **** htim10.Init.Period = 9; + 7100 .loc 1 1505 27 is_stmt 0 view .LVU2281 + 7101 000c 0023 movs r3, #0 + 7102 000e 8360 str r3, [r0, #8] +1506:Src/main.c **** htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 7103 .loc 1 1506 3 is_stmt 1 view .LVU2282 +1506:Src/main.c **** htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 7104 .loc 1 1506 22 is_stmt 0 view .LVU2283 + 7105 0010 0922 movs r2, #9 + 7106 0012 C260 str r2, [r0, #12] +1507:Src/main.c **** htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 7107 .loc 1 1507 3 is_stmt 1 view .LVU2284 +1507:Src/main.c **** htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 7108 .loc 1 1507 29 is_stmt 0 view .LVU2285 + 7109 0014 0361 str r3, [r0, #16] +1508:Src/main.c **** if (HAL_TIM_Base_Init(&htim10) != HAL_OK) + 7110 .loc 1 1508 3 is_stmt 1 view .LVU2286 +1508:Src/main.c **** if (HAL_TIM_Base_Init(&htim10) != HAL_OK) + 7111 .loc 1 1508 33 is_stmt 0 view .LVU2287 + 7112 0016 8361 str r3, [r0, #24] +1509:Src/main.c **** { + 7113 .loc 1 1509 3 is_stmt 1 view .LVU2288 +1509:Src/main.c **** { + 7114 .loc 1 1509 7 is_stmt 0 view .LVU2289 + 7115 0018 FFF7FEFF bl HAL_TIM_Base_Init + 7116 .LVL569: +1509:Src/main.c **** { + 7117 .loc 1 1509 6 discriminator 1 view .LVU2290 + 7118 001c 00B9 cbnz r0, .L314 +1517:Src/main.c **** + 7119 .loc 1 1517 1 view .LVU2291 + 7120 001e 08BD pop {r3, pc} + 7121 .L314: +1511:Src/main.c **** } + 7122 .loc 1 1511 5 is_stmt 1 view .LVU2292 + 7123 0020 FFF7FEFF bl Error_Handler + 7124 .LVL570: + 7125 .L316: + 7126 .align 2 + 7127 .L315: + 7128 0024 00000000 .word htim10 + 7129 0028 00440140 .word 1073824768 + 7130 .cfi_endproc + 7131 .LFE1201: + 7133 .section .text.MX_UART8_Init,"ax",%progbits + 7134 .align 1 + 7135 .syntax unified + 7136 .thumb + 7137 .thumb_func + 7139 MX_UART8_Init: + 7140 .LFB1203: +1571:Src/main.c **** + 7141 .loc 1 1571 1 view -0 + ARM GAS /tmp/ccWQNJQt.s page 498 + + + 7142 .cfi_startproc + 7143 @ args = 0, pretend = 0, frame = 0 + 7144 @ frame_needed = 0, uses_anonymous_args = 0 + 7145 0000 08B5 push {r3, lr} + 7146 .LCFI63: + 7147 .cfi_def_cfa_offset 8 + 7148 .cfi_offset 3, -8 + 7149 .cfi_offset 14, -4 +1580:Src/main.c **** huart8.Init.BaudRate = 115200; + 7150 .loc 1 1580 3 view .LVU2294 +1580:Src/main.c **** huart8.Init.BaudRate = 115200; + 7151 .loc 1 1580 19 is_stmt 0 view .LVU2295 + 7152 0002 0B48 ldr r0, .L321 + 7153 0004 0B4B ldr r3, .L321+4 + 7154 0006 0360 str r3, [r0] +1581:Src/main.c **** huart8.Init.WordLength = UART_WORDLENGTH_8B; + 7155 .loc 1 1581 3 is_stmt 1 view .LVU2296 +1581:Src/main.c **** huart8.Init.WordLength = UART_WORDLENGTH_8B; + 7156 .loc 1 1581 24 is_stmt 0 view .LVU2297 + 7157 0008 4FF4E133 mov r3, #115200 + 7158 000c 4360 str r3, [r0, #4] +1582:Src/main.c **** huart8.Init.StopBits = UART_STOPBITS_1; + 7159 .loc 1 1582 3 is_stmt 1 view .LVU2298 +1582:Src/main.c **** huart8.Init.StopBits = UART_STOPBITS_1; + 7160 .loc 1 1582 26 is_stmt 0 view .LVU2299 + 7161 000e 0023 movs r3, #0 + 7162 0010 8360 str r3, [r0, #8] +1583:Src/main.c **** huart8.Init.Parity = UART_PARITY_NONE; + 7163 .loc 1 1583 3 is_stmt 1 view .LVU2300 +1583:Src/main.c **** huart8.Init.Parity = UART_PARITY_NONE; + 7164 .loc 1 1583 24 is_stmt 0 view .LVU2301 + 7165 0012 C360 str r3, [r0, #12] +1584:Src/main.c **** huart8.Init.Mode = UART_MODE_TX_RX; + 7166 .loc 1 1584 3 is_stmt 1 view .LVU2302 +1584:Src/main.c **** huart8.Init.Mode = UART_MODE_TX_RX; + 7167 .loc 1 1584 22 is_stmt 0 view .LVU2303 + 7168 0014 0361 str r3, [r0, #16] +1585:Src/main.c **** huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 7169 .loc 1 1585 3 is_stmt 1 view .LVU2304 +1585:Src/main.c **** huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 7170 .loc 1 1585 20 is_stmt 0 view .LVU2305 + 7171 0016 0C22 movs r2, #12 + 7172 0018 4261 str r2, [r0, #20] +1586:Src/main.c **** huart8.Init.OverSampling = UART_OVERSAMPLING_16; + 7173 .loc 1 1586 3 is_stmt 1 view .LVU2306 +1586:Src/main.c **** huart8.Init.OverSampling = UART_OVERSAMPLING_16; + 7174 .loc 1 1586 25 is_stmt 0 view .LVU2307 + 7175 001a 8361 str r3, [r0, #24] +1587:Src/main.c **** huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 7176 .loc 1 1587 3 is_stmt 1 view .LVU2308 +1587:Src/main.c **** huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 7177 .loc 1 1587 28 is_stmt 0 view .LVU2309 + 7178 001c C361 str r3, [r0, #28] +1588:Src/main.c **** huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + 7179 .loc 1 1588 3 is_stmt 1 view .LVU2310 +1588:Src/main.c **** huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + 7180 .loc 1 1588 30 is_stmt 0 view .LVU2311 + ARM GAS /tmp/ccWQNJQt.s page 499 + + + 7181 001e 0362 str r3, [r0, #32] +1589:Src/main.c **** if (HAL_UART_Init(&huart8) != HAL_OK) + 7182 .loc 1 1589 3 is_stmt 1 view .LVU2312 +1589:Src/main.c **** if (HAL_UART_Init(&huart8) != HAL_OK) + 7183 .loc 1 1589 38 is_stmt 0 view .LVU2313 + 7184 0020 4362 str r3, [r0, #36] +1590:Src/main.c **** { + 7185 .loc 1 1590 3 is_stmt 1 view .LVU2314 +1590:Src/main.c **** { + 7186 .loc 1 1590 7 is_stmt 0 view .LVU2315 + 7187 0022 FFF7FEFF bl HAL_UART_Init + 7188 .LVL571: +1590:Src/main.c **** { + 7189 .loc 1 1590 6 discriminator 1 view .LVU2316 + 7190 0026 00B9 cbnz r0, .L320 +1598:Src/main.c **** + 7191 .loc 1 1598 1 view .LVU2317 + 7192 0028 08BD pop {r3, pc} + 7193 .L320: +1592:Src/main.c **** } + 7194 .loc 1 1592 5 is_stmt 1 view .LVU2318 + 7195 002a FFF7FEFF bl Error_Handler + 7196 .LVL572: + 7197 .L322: + 7198 002e 00BF .align 2 + 7199 .L321: + 7200 0030 00000000 .word huart8 + 7201 0034 007C0040 .word 1073773568 + 7202 .cfi_endproc + 7203 .LFE1203: + 7205 .section .text.MX_TIM8_Init,"ax",%progbits + 7206 .align 1 + 7207 .syntax unified + 7208 .thumb + 7209 .thumb_func + 7211 MX_TIM8_Init: + 7212 .LFB1200: +1447:Src/main.c **** + 7213 .loc 1 1447 1 view -0 + 7214 .cfi_startproc + 7215 @ args = 0, pretend = 0, frame = 32 + 7216 @ frame_needed = 0, uses_anonymous_args = 0 + 7217 0000 00B5 push {lr} + 7218 .LCFI64: + 7219 .cfi_def_cfa_offset 4 + 7220 .cfi_offset 14, -4 + 7221 0002 89B0 sub sp, sp, #36 + 7222 .LCFI65: + 7223 .cfi_def_cfa_offset 40 +1453:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; + 7224 .loc 1 1453 3 view .LVU2320 +1453:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; + 7225 .loc 1 1453 26 is_stmt 0 view .LVU2321 + 7226 0004 0023 movs r3, #0 + 7227 0006 0493 str r3, [sp, #16] + 7228 0008 0593 str r3, [sp, #20] + 7229 000a 0693 str r3, [sp, #24] + ARM GAS /tmp/ccWQNJQt.s page 500 + + + 7230 000c 0793 str r3, [sp, #28] +1454:Src/main.c **** + 7231 .loc 1 1454 3 is_stmt 1 view .LVU2322 +1454:Src/main.c **** + 7232 .loc 1 1454 27 is_stmt 0 view .LVU2323 + 7233 000e 0193 str r3, [sp, #4] + 7234 0010 0293 str r3, [sp, #8] + 7235 0012 0393 str r3, [sp, #12] +1459:Src/main.c **** htim8.Init.Prescaler = 0; + 7236 .loc 1 1459 3 is_stmt 1 view .LVU2324 +1459:Src/main.c **** htim8.Init.Prescaler = 0; + 7237 .loc 1 1459 18 is_stmt 0 view .LVU2325 + 7238 0014 1348 ldr r0, .L331 + 7239 0016 144A ldr r2, .L331+4 + 7240 0018 0260 str r2, [r0] +1460:Src/main.c **** htim8.Init.CounterMode = TIM_COUNTERMODE_UP; + 7241 .loc 1 1460 3 is_stmt 1 view .LVU2326 +1460:Src/main.c **** htim8.Init.CounterMode = TIM_COUNTERMODE_UP; + 7242 .loc 1 1460 24 is_stmt 0 view .LVU2327 + 7243 001a 4360 str r3, [r0, #4] +1461:Src/main.c **** htim8.Init.Period = 91; + 7244 .loc 1 1461 3 is_stmt 1 view .LVU2328 +1461:Src/main.c **** htim8.Init.Period = 91; + 7245 .loc 1 1461 26 is_stmt 0 view .LVU2329 + 7246 001c 8360 str r3, [r0, #8] +1462:Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 7247 .loc 1 1462 3 is_stmt 1 view .LVU2330 +1462:Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 7248 .loc 1 1462 21 is_stmt 0 view .LVU2331 + 7249 001e 5B22 movs r2, #91 + 7250 0020 C260 str r2, [r0, #12] +1463:Src/main.c **** htim8.Init.RepetitionCounter = 0; + 7251 .loc 1 1463 3 is_stmt 1 view .LVU2332 +1463:Src/main.c **** htim8.Init.RepetitionCounter = 0; + 7252 .loc 1 1463 28 is_stmt 0 view .LVU2333 + 7253 0022 0361 str r3, [r0, #16] +1464:Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 7254 .loc 1 1464 3 is_stmt 1 view .LVU2334 +1464:Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 7255 .loc 1 1464 32 is_stmt 0 view .LVU2335 + 7256 0024 4361 str r3, [r0, #20] +1465:Src/main.c **** if (HAL_TIM_Base_Init(&htim8) != HAL_OK) + 7257 .loc 1 1465 3 is_stmt 1 view .LVU2336 +1465:Src/main.c **** if (HAL_TIM_Base_Init(&htim8) != HAL_OK) + 7258 .loc 1 1465 32 is_stmt 0 view .LVU2337 + 7259 0026 8361 str r3, [r0, #24] +1466:Src/main.c **** { + 7260 .loc 1 1466 3 is_stmt 1 view .LVU2338 +1466:Src/main.c **** { + 7261 .loc 1 1466 7 is_stmt 0 view .LVU2339 + 7262 0028 FFF7FEFF bl HAL_TIM_Base_Init + 7263 .LVL573: +1466:Src/main.c **** { + 7264 .loc 1 1466 6 discriminator 1 view .LVU2340 + 7265 002c 98B9 cbnz r0, .L328 +1470:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) + 7266 .loc 1 1470 3 is_stmt 1 view .LVU2341 + ARM GAS /tmp/ccWQNJQt.s page 501 + + +1470:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) + 7267 .loc 1 1470 34 is_stmt 0 view .LVU2342 + 7268 002e 4FF48053 mov r3, #4096 + 7269 0032 0493 str r3, [sp, #16] +1471:Src/main.c **** { + 7270 .loc 1 1471 3 is_stmt 1 view .LVU2343 +1471:Src/main.c **** { + 7271 .loc 1 1471 7 is_stmt 0 view .LVU2344 + 7272 0034 04A9 add r1, sp, #16 + 7273 0036 0B48 ldr r0, .L331 + 7274 0038 FFF7FEFF bl HAL_TIM_ConfigClockSource + 7275 .LVL574: +1471:Src/main.c **** { + 7276 .loc 1 1471 6 discriminator 1 view .LVU2345 + 7277 003c 68B9 cbnz r0, .L329 +1475:Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; + 7278 .loc 1 1475 3 is_stmt 1 view .LVU2346 +1475:Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; + 7279 .loc 1 1475 37 is_stmt 0 view .LVU2347 + 7280 003e 0023 movs r3, #0 + 7281 0040 0193 str r3, [sp, #4] +1476:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 7282 .loc 1 1476 3 is_stmt 1 view .LVU2348 +1476:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 7283 .loc 1 1476 38 is_stmt 0 view .LVU2349 + 7284 0042 0293 str r3, [sp, #8] +1477:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) + 7285 .loc 1 1477 3 is_stmt 1 view .LVU2350 +1477:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) + 7286 .loc 1 1477 33 is_stmt 0 view .LVU2351 + 7287 0044 0393 str r3, [sp, #12] +1478:Src/main.c **** { + 7288 .loc 1 1478 3 is_stmt 1 view .LVU2352 +1478:Src/main.c **** { + 7289 .loc 1 1478 7 is_stmt 0 view .LVU2353 + 7290 0046 01A9 add r1, sp, #4 + 7291 0048 0648 ldr r0, .L331 + 7292 004a FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization + 7293 .LVL575: +1478:Src/main.c **** { + 7294 .loc 1 1478 6 discriminator 1 view .LVU2354 + 7295 004e 30B9 cbnz r0, .L330 +1486:Src/main.c **** + 7296 .loc 1 1486 1 view .LVU2355 + 7297 0050 09B0 add sp, sp, #36 + 7298 .LCFI66: + 7299 .cfi_remember_state + 7300 .cfi_def_cfa_offset 4 + 7301 @ sp needed + 7302 0052 5DF804FB ldr pc, [sp], #4 + 7303 .L328: + 7304 .LCFI67: + 7305 .cfi_restore_state +1468:Src/main.c **** } + 7306 .loc 1 1468 5 is_stmt 1 view .LVU2356 + 7307 0056 FFF7FEFF bl Error_Handler + 7308 .LVL576: + ARM GAS /tmp/ccWQNJQt.s page 502 + + + 7309 .L329: +1473:Src/main.c **** } + 7310 .loc 1 1473 5 view .LVU2357 + 7311 005a FFF7FEFF bl Error_Handler + 7312 .LVL577: + 7313 .L330: +1480:Src/main.c **** } + 7314 .loc 1 1480 5 view .LVU2358 + 7315 005e FFF7FEFF bl Error_Handler + 7316 .LVL578: + 7317 .L332: + 7318 0062 00BF .align 2 + 7319 .L331: + 7320 0064 00000000 .word htim8 + 7321 0068 00040140 .word 1073808384 + 7322 .cfi_endproc + 7323 .LFE1200: + 7325 .section .text.MX_TIM11_Init,"ax",%progbits + 7326 .align 1 + 7327 .syntax unified + 7328 .thumb + 7329 .thumb_func + 7331 MX_TIM11_Init: + 7332 .LFB1202: +1525:Src/main.c **** + 7333 .loc 1 1525 1 view -0 + 7334 .cfi_startproc + 7335 @ args = 0, pretend = 0, frame = 32 + 7336 @ frame_needed = 0, uses_anonymous_args = 0 + 7337 0000 00B5 push {lr} + 7338 .LCFI68: + 7339 .cfi_def_cfa_offset 4 + 7340 .cfi_offset 14, -4 + 7341 0002 89B0 sub sp, sp, #36 + 7342 .LCFI69: + 7343 .cfi_def_cfa_offset 40 +1531:Src/main.c **** + 7344 .loc 1 1531 3 view .LVU2360 +1531:Src/main.c **** + 7345 .loc 1 1531 22 is_stmt 0 view .LVU2361 + 7346 0004 0023 movs r3, #0 + 7347 0006 0193 str r3, [sp, #4] + 7348 0008 0293 str r3, [sp, #8] + 7349 000a 0393 str r3, [sp, #12] + 7350 000c 0493 str r3, [sp, #16] + 7351 000e 0593 str r3, [sp, #20] + 7352 0010 0693 str r3, [sp, #24] + 7353 0012 0793 str r3, [sp, #28] +1536:Src/main.c **** htim11.Init.Prescaler = 1; + 7354 .loc 1 1536 3 is_stmt 1 view .LVU2362 +1536:Src/main.c **** htim11.Init.Prescaler = 1; + 7355 .loc 1 1536 19 is_stmt 0 view .LVU2363 + 7356 0014 1448 ldr r0, .L341 + 7357 0016 154A ldr r2, .L341+4 + 7358 0018 0260 str r2, [r0] +1537:Src/main.c **** htim11.Init.CounterMode = TIM_COUNTERMODE_UP; + 7359 .loc 1 1537 3 is_stmt 1 view .LVU2364 + ARM GAS /tmp/ccWQNJQt.s page 503 + + +1537:Src/main.c **** htim11.Init.CounterMode = TIM_COUNTERMODE_UP; + 7360 .loc 1 1537 25 is_stmt 0 view .LVU2365 + 7361 001a 0122 movs r2, #1 + 7362 001c 4260 str r2, [r0, #4] +1538:Src/main.c **** htim11.Init.Period = 91; + 7363 .loc 1 1538 3 is_stmt 1 view .LVU2366 +1538:Src/main.c **** htim11.Init.Period = 91; + 7364 .loc 1 1538 27 is_stmt 0 view .LVU2367 + 7365 001e 8360 str r3, [r0, #8] +1539:Src/main.c **** htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 7366 .loc 1 1539 3 is_stmt 1 view .LVU2368 +1539:Src/main.c **** htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 7367 .loc 1 1539 22 is_stmt 0 view .LVU2369 + 7368 0020 5B22 movs r2, #91 + 7369 0022 C260 str r2, [r0, #12] +1540:Src/main.c **** htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; + 7370 .loc 1 1540 3 is_stmt 1 view .LVU2370 +1540:Src/main.c **** htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; + 7371 .loc 1 1540 29 is_stmt 0 view .LVU2371 + 7372 0024 0361 str r3, [r0, #16] +1541:Src/main.c **** if (HAL_TIM_Base_Init(&htim11) != HAL_OK) + 7373 .loc 1 1541 3 is_stmt 1 view .LVU2372 +1541:Src/main.c **** if (HAL_TIM_Base_Init(&htim11) != HAL_OK) + 7374 .loc 1 1541 33 is_stmt 0 view .LVU2373 + 7375 0026 8023 movs r3, #128 + 7376 0028 8361 str r3, [r0, #24] +1542:Src/main.c **** { + 7377 .loc 1 1542 3 is_stmt 1 view .LVU2374 +1542:Src/main.c **** { + 7378 .loc 1 1542 7 is_stmt 0 view .LVU2375 + 7379 002a FFF7FEFF bl HAL_TIM_Base_Init + 7380 .LVL579: +1542:Src/main.c **** { + 7381 .loc 1 1542 6 discriminator 1 view .LVU2376 + 7382 002e A8B9 cbnz r0, .L338 +1546:Src/main.c **** { + 7383 .loc 1 1546 3 is_stmt 1 view .LVU2377 +1546:Src/main.c **** { + 7384 .loc 1 1546 7 is_stmt 0 view .LVU2378 + 7385 0030 0D48 ldr r0, .L341 + 7386 0032 FFF7FEFF bl HAL_TIM_PWM_Init + 7387 .LVL580: +1546:Src/main.c **** { + 7388 .loc 1 1546 6 discriminator 1 view .LVU2379 + 7389 0036 98B9 cbnz r0, .L339 +1550:Src/main.c **** sConfigOC.Pulse = 91; + 7390 .loc 1 1550 3 is_stmt 1 view .LVU2380 +1550:Src/main.c **** sConfigOC.Pulse = 91; + 7391 .loc 1 1550 20 is_stmt 0 view .LVU2381 + 7392 0038 6023 movs r3, #96 + 7393 003a 0193 str r3, [sp, #4] +1551:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 7394 .loc 1 1551 3 is_stmt 1 view .LVU2382 +1551:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 7395 .loc 1 1551 19 is_stmt 0 view .LVU2383 + 7396 003c 5B23 movs r3, #91 + 7397 003e 0293 str r3, [sp, #8] + ARM GAS /tmp/ccWQNJQt.s page 504 + + +1552:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 7398 .loc 1 1552 3 is_stmt 1 view .LVU2384 +1552:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 7399 .loc 1 1552 24 is_stmt 0 view .LVU2385 + 7400 0040 0022 movs r2, #0 + 7401 0042 0392 str r2, [sp, #12] +1553:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim11, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + 7402 .loc 1 1553 3 is_stmt 1 view .LVU2386 +1553:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim11, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + 7403 .loc 1 1553 24 is_stmt 0 view .LVU2387 + 7404 0044 0592 str r2, [sp, #20] +1554:Src/main.c **** { + 7405 .loc 1 1554 3 is_stmt 1 view .LVU2388 +1554:Src/main.c **** { + 7406 .loc 1 1554 7 is_stmt 0 view .LVU2389 + 7407 0046 01A9 add r1, sp, #4 + 7408 0048 0748 ldr r0, .L341 + 7409 004a FFF7FEFF bl HAL_TIM_PWM_ConfigChannel + 7410 .LVL581: +1554:Src/main.c **** { + 7411 .loc 1 1554 6 discriminator 1 view .LVU2390 + 7412 004e 48B9 cbnz r0, .L340 +1561:Src/main.c **** + 7413 .loc 1 1561 3 is_stmt 1 view .LVU2391 + 7414 0050 0548 ldr r0, .L341 + 7415 0052 FFF7FEFF bl HAL_TIM_MspPostInit + 7416 .LVL582: +1563:Src/main.c **** + 7417 .loc 1 1563 1 is_stmt 0 view .LVU2392 + 7418 0056 09B0 add sp, sp, #36 + 7419 .LCFI70: + 7420 .cfi_remember_state + 7421 .cfi_def_cfa_offset 4 + 7422 @ sp needed + 7423 0058 5DF804FB ldr pc, [sp], #4 + 7424 .L338: + 7425 .LCFI71: + 7426 .cfi_restore_state +1544:Src/main.c **** } + 7427 .loc 1 1544 5 is_stmt 1 view .LVU2393 + 7428 005c FFF7FEFF bl Error_Handler + 7429 .LVL583: + 7430 .L339: +1548:Src/main.c **** } + 7431 .loc 1 1548 5 view .LVU2394 + 7432 0060 FFF7FEFF bl Error_Handler + 7433 .LVL584: + 7434 .L340: +1556:Src/main.c **** } + 7435 .loc 1 1556 5 view .LVU2395 + 7436 0064 FFF7FEFF bl Error_Handler + 7437 .LVL585: + 7438 .L342: + 7439 .align 2 + 7440 .L341: + 7441 0068 00000000 .word htim11 + 7442 006c 00480140 .word 1073825792 + ARM GAS /tmp/ccWQNJQt.s page 505 + + + 7443 .cfi_endproc + 7444 .LFE1202: + 7446 .section .text.MX_TIM4_Init,"ax",%progbits + 7447 .align 1 + 7448 .syntax unified + 7449 .thumb + 7450 .thumb_func + 7452 MX_TIM4_Init: + 7453 .LFB1196: +1275:Src/main.c **** + 7454 .loc 1 1275 1 view -0 + 7455 .cfi_startproc + 7456 @ args = 0, pretend = 0, frame = 56 + 7457 @ frame_needed = 0, uses_anonymous_args = 0 + 7458 0000 00B5 push {lr} + 7459 .LCFI72: + 7460 .cfi_def_cfa_offset 4 + 7461 .cfi_offset 14, -4 + 7462 0002 8FB0 sub sp, sp, #60 + 7463 .LCFI73: + 7464 .cfi_def_cfa_offset 64 +1281:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; + 7465 .loc 1 1281 3 view .LVU2397 +1281:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; + 7466 .loc 1 1281 26 is_stmt 0 view .LVU2398 + 7467 0004 0023 movs r3, #0 + 7468 0006 0A93 str r3, [sp, #40] + 7469 0008 0B93 str r3, [sp, #44] + 7470 000a 0C93 str r3, [sp, #48] + 7471 000c 0D93 str r3, [sp, #52] +1282:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; + 7472 .loc 1 1282 3 is_stmt 1 view .LVU2399 +1282:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; + 7473 .loc 1 1282 27 is_stmt 0 view .LVU2400 + 7474 000e 0793 str r3, [sp, #28] + 7475 0010 0893 str r3, [sp, #32] + 7476 0012 0993 str r3, [sp, #36] +1283:Src/main.c **** + 7477 .loc 1 1283 3 is_stmt 1 view .LVU2401 +1283:Src/main.c **** + 7478 .loc 1 1283 22 is_stmt 0 view .LVU2402 + 7479 0014 0093 str r3, [sp] + 7480 0016 0193 str r3, [sp, #4] + 7481 0018 0293 str r3, [sp, #8] + 7482 001a 0393 str r3, [sp, #12] + 7483 001c 0493 str r3, [sp, #16] + 7484 001e 0593 str r3, [sp, #20] + 7485 0020 0693 str r3, [sp, #24] +1288:Src/main.c **** htim4.Init.Prescaler = 0; + 7486 .loc 1 1288 3 is_stmt 1 view .LVU2403 +1288:Src/main.c **** htim4.Init.Prescaler = 0; + 7487 .loc 1 1288 18 is_stmt 0 view .LVU2404 + 7488 0022 1E48 ldr r0, .L355 + 7489 0024 1E4A ldr r2, .L355+4 + 7490 0026 0260 str r2, [r0] +1289:Src/main.c **** htim4.Init.CounterMode = TIM_COUNTERMODE_UP; + 7491 .loc 1 1289 3 is_stmt 1 view .LVU2405 + ARM GAS /tmp/ccWQNJQt.s page 506 + + +1289:Src/main.c **** htim4.Init.CounterMode = TIM_COUNTERMODE_UP; + 7492 .loc 1 1289 24 is_stmt 0 view .LVU2406 + 7493 0028 4360 str r3, [r0, #4] +1290:Src/main.c **** htim4.Init.Period = 45; + 7494 .loc 1 1290 3 is_stmt 1 view .LVU2407 +1290:Src/main.c **** htim4.Init.Period = 45; + 7495 .loc 1 1290 26 is_stmt 0 view .LVU2408 + 7496 002a 8360 str r3, [r0, #8] +1291:Src/main.c **** htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 7497 .loc 1 1291 3 is_stmt 1 view .LVU2409 +1291:Src/main.c **** htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 7498 .loc 1 1291 21 is_stmt 0 view .LVU2410 + 7499 002c 2D22 movs r2, #45 + 7500 002e C260 str r2, [r0, #12] +1292:Src/main.c **** htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 7501 .loc 1 1292 3 is_stmt 1 view .LVU2411 +1292:Src/main.c **** htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 7502 .loc 1 1292 28 is_stmt 0 view .LVU2412 + 7503 0030 0361 str r3, [r0, #16] +1293:Src/main.c **** if (HAL_TIM_Base_Init(&htim4) != HAL_OK) + 7504 .loc 1 1293 3 is_stmt 1 view .LVU2413 +1293:Src/main.c **** if (HAL_TIM_Base_Init(&htim4) != HAL_OK) + 7505 .loc 1 1293 32 is_stmt 0 view .LVU2414 + 7506 0032 8361 str r3, [r0, #24] +1294:Src/main.c **** { + 7507 .loc 1 1294 3 is_stmt 1 view .LVU2415 +1294:Src/main.c **** { + 7508 .loc 1 1294 7 is_stmt 0 view .LVU2416 + 7509 0034 FFF7FEFF bl HAL_TIM_Base_Init + 7510 .LVL586: +1294:Src/main.c **** { + 7511 .loc 1 1294 6 discriminator 1 view .LVU2417 + 7512 0038 30BB cbnz r0, .L350 +1298:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) + 7513 .loc 1 1298 3 is_stmt 1 view .LVU2418 +1298:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) + 7514 .loc 1 1298 34 is_stmt 0 view .LVU2419 + 7515 003a 4FF48053 mov r3, #4096 + 7516 003e 0A93 str r3, [sp, #40] +1299:Src/main.c **** { + 7517 .loc 1 1299 3 is_stmt 1 view .LVU2420 +1299:Src/main.c **** { + 7518 .loc 1 1299 7 is_stmt 0 view .LVU2421 + 7519 0040 0AA9 add r1, sp, #40 + 7520 0042 1648 ldr r0, .L355 + 7521 0044 FFF7FEFF bl HAL_TIM_ConfigClockSource + 7522 .LVL587: +1299:Src/main.c **** { + 7523 .loc 1 1299 6 discriminator 1 view .LVU2422 + 7524 0048 00BB cbnz r0, .L351 +1303:Src/main.c **** { + 7525 .loc 1 1303 3 is_stmt 1 view .LVU2423 +1303:Src/main.c **** { + 7526 .loc 1 1303 7 is_stmt 0 view .LVU2424 + 7527 004a 1448 ldr r0, .L355 + 7528 004c FFF7FEFF bl HAL_TIM_PWM_Init + 7529 .LVL588: + ARM GAS /tmp/ccWQNJQt.s page 507 + + +1303:Src/main.c **** { + 7530 .loc 1 1303 6 discriminator 1 view .LVU2425 + 7531 0050 F0B9 cbnz r0, .L352 +1307:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 7532 .loc 1 1307 3 is_stmt 1 view .LVU2426 +1307:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 7533 .loc 1 1307 37 is_stmt 0 view .LVU2427 + 7534 0052 0023 movs r3, #0 + 7535 0054 0793 str r3, [sp, #28] +1308:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) + 7536 .loc 1 1308 3 is_stmt 1 view .LVU2428 +1308:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) + 7537 .loc 1 1308 33 is_stmt 0 view .LVU2429 + 7538 0056 0993 str r3, [sp, #36] +1309:Src/main.c **** { + 7539 .loc 1 1309 3 is_stmt 1 view .LVU2430 +1309:Src/main.c **** { + 7540 .loc 1 1309 7 is_stmt 0 view .LVU2431 + 7541 0058 07A9 add r1, sp, #28 + 7542 005a 1048 ldr r0, .L355 + 7543 005c FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization + 7544 .LVL589: +1309:Src/main.c **** { + 7545 .loc 1 1309 6 discriminator 1 view .LVU2432 + 7546 0060 C0B9 cbnz r0, .L353 +1313:Src/main.c **** sConfigOC.Pulse = 22; + 7547 .loc 1 1313 3 is_stmt 1 view .LVU2433 +1313:Src/main.c **** sConfigOC.Pulse = 22; + 7548 .loc 1 1313 20 is_stmt 0 view .LVU2434 + 7549 0062 6023 movs r3, #96 + 7550 0064 0093 str r3, [sp] +1314:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 7551 .loc 1 1314 3 is_stmt 1 view .LVU2435 +1314:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 7552 .loc 1 1314 19 is_stmt 0 view .LVU2436 + 7553 0066 1623 movs r3, #22 + 7554 0068 0193 str r3, [sp, #4] +1315:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 7555 .loc 1 1315 3 is_stmt 1 view .LVU2437 +1315:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 7556 .loc 1 1315 24 is_stmt 0 view .LVU2438 + 7557 006a 0023 movs r3, #0 + 7558 006c 0293 str r3, [sp, #8] +1316:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + 7559 .loc 1 1316 3 is_stmt 1 view .LVU2439 +1316:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + 7560 .loc 1 1316 24 is_stmt 0 view .LVU2440 + 7561 006e 0493 str r3, [sp, #16] +1317:Src/main.c **** { + 7562 .loc 1 1317 3 is_stmt 1 view .LVU2441 +1317:Src/main.c **** { + 7563 .loc 1 1317 7 is_stmt 0 view .LVU2442 + 7564 0070 0822 movs r2, #8 + 7565 0072 6946 mov r1, sp + 7566 0074 0948 ldr r0, .L355 + 7567 0076 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel + 7568 .LVL590: + ARM GAS /tmp/ccWQNJQt.s page 508 + + +1317:Src/main.c **** { + 7569 .loc 1 1317 6 discriminator 1 view .LVU2443 + 7570 007a 68B9 cbnz r0, .L354 +1324:Src/main.c **** + 7571 .loc 1 1324 3 is_stmt 1 view .LVU2444 + 7572 007c 0748 ldr r0, .L355 + 7573 007e FFF7FEFF bl HAL_TIM_MspPostInit + 7574 .LVL591: +1326:Src/main.c **** + 7575 .loc 1 1326 1 is_stmt 0 view .LVU2445 + 7576 0082 0FB0 add sp, sp, #60 + 7577 .LCFI74: + 7578 .cfi_remember_state + 7579 .cfi_def_cfa_offset 4 + 7580 @ sp needed + 7581 0084 5DF804FB ldr pc, [sp], #4 + 7582 .L350: + 7583 .LCFI75: + 7584 .cfi_restore_state +1296:Src/main.c **** } + 7585 .loc 1 1296 5 is_stmt 1 view .LVU2446 + 7586 0088 FFF7FEFF bl Error_Handler + 7587 .LVL592: + 7588 .L351: +1301:Src/main.c **** } + 7589 .loc 1 1301 5 view .LVU2447 + 7590 008c FFF7FEFF bl Error_Handler + 7591 .LVL593: + 7592 .L352: +1305:Src/main.c **** } + 7593 .loc 1 1305 5 view .LVU2448 + 7594 0090 FFF7FEFF bl Error_Handler + 7595 .LVL594: + 7596 .L353: +1311:Src/main.c **** } + 7597 .loc 1 1311 5 view .LVU2449 + 7598 0094 FFF7FEFF bl Error_Handler + 7599 .LVL595: + 7600 .L354: +1319:Src/main.c **** } + 7601 .loc 1 1319 5 view .LVU2450 + 7602 0098 FFF7FEFF bl Error_Handler + 7603 .LVL596: + 7604 .L356: + 7605 .align 2 + 7606 .L355: + 7607 009c 00000000 .word htim4 + 7608 00a0 00080040 .word 1073743872 + 7609 .cfi_endproc + 7610 .LFE1196: + 7612 .section .text.SystemClock_Config,"ax",%progbits + 7613 .align 1 + 7614 .global SystemClock_Config + 7615 .syntax unified + 7616 .thumb + 7617 .thumb_func + 7619 SystemClock_Config: + ARM GAS /tmp/ccWQNJQt.s page 509 + + + 7620 .LFB1187: + 762:Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 7621 .loc 1 762 1 view -0 + 7622 .cfi_startproc + 7623 @ args = 0, pretend = 0, frame = 80 + 7624 @ frame_needed = 0, uses_anonymous_args = 0 + 7625 0000 00B5 push {lr} + 7626 .LCFI76: + 7627 .cfi_def_cfa_offset 4 + 7628 .cfi_offset 14, -4 + 7629 0002 95B0 sub sp, sp, #84 + 7630 .LCFI77: + 7631 .cfi_def_cfa_offset 88 + 763:Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 7632 .loc 1 763 3 view .LVU2452 + 763:Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 7633 .loc 1 763 22 is_stmt 0 view .LVU2453 + 7634 0004 3422 movs r2, #52 + 7635 0006 0021 movs r1, #0 + 7636 0008 07A8 add r0, sp, #28 + 7637 000a FFF7FEFF bl memset + 7638 .LVL597: + 764:Src/main.c **** + 7639 .loc 1 764 3 is_stmt 1 view .LVU2454 + 764:Src/main.c **** + 7640 .loc 1 764 22 is_stmt 0 view .LVU2455 + 7641 000e 0023 movs r3, #0 + 7642 0010 0293 str r3, [sp, #8] + 7643 0012 0393 str r3, [sp, #12] + 7644 0014 0493 str r3, [sp, #16] + 7645 0016 0593 str r3, [sp, #20] + 7646 0018 0693 str r3, [sp, #24] + 768:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 7647 .loc 1 768 3 is_stmt 1 view .LVU2456 + 7648 .LBB545: + 768:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 7649 .loc 1 768 3 view .LVU2457 + 768:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 7650 .loc 1 768 3 view .LVU2458 + 7651 001a 244B ldr r3, .L365 + 7652 001c 1A6C ldr r2, [r3, #64] + 7653 001e 42F08052 orr r2, r2, #268435456 + 7654 0022 1A64 str r2, [r3, #64] + 768:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 7655 .loc 1 768 3 view .LVU2459 + 7656 0024 1B6C ldr r3, [r3, #64] + 7657 0026 03F08053 and r3, r3, #268435456 + 7658 002a 0093 str r3, [sp] + 768:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 7659 .loc 1 768 3 view .LVU2460 + 7660 002c 009B ldr r3, [sp] + 7661 .LBE545: + 768:Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 7662 .loc 1 768 3 view .LVU2461 + 769:Src/main.c **** + 7663 .loc 1 769 3 view .LVU2462 + 7664 .LBB546: + ARM GAS /tmp/ccWQNJQt.s page 510 + + + 769:Src/main.c **** + 7665 .loc 1 769 3 view .LVU2463 + 769:Src/main.c **** + 7666 .loc 1 769 3 view .LVU2464 + 7667 002e 204B ldr r3, .L365+4 + 7668 0030 1A68 ldr r2, [r3] + 7669 0032 42F44042 orr r2, r2, #49152 + 7670 0036 1A60 str r2, [r3] + 769:Src/main.c **** + 7671 .loc 1 769 3 view .LVU2465 + 7672 0038 1B68 ldr r3, [r3] + 7673 003a 03F44043 and r3, r3, #49152 + 7674 003e 0193 str r3, [sp, #4] + 769:Src/main.c **** + 7675 .loc 1 769 3 view .LVU2466 + 7676 0040 019B ldr r3, [sp, #4] + 7677 .LBE546: + 769:Src/main.c **** + 7678 .loc 1 769 3 view .LVU2467 + 774:Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 7679 .loc 1 774 3 view .LVU2468 + 774:Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 7680 .loc 1 774 36 is_stmt 0 view .LVU2469 + 7681 0042 0123 movs r3, #1 + 7682 0044 0793 str r3, [sp, #28] + 775:Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 7683 .loc 1 775 3 is_stmt 1 view .LVU2470 + 775:Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 7684 .loc 1 775 30 is_stmt 0 view .LVU2471 + 7685 0046 4FF48033 mov r3, #65536 + 7686 004a 0893 str r3, [sp, #32] + 776:Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + 7687 .loc 1 776 3 is_stmt 1 view .LVU2472 + 776:Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + 7688 .loc 1 776 34 is_stmt 0 view .LVU2473 + 7689 004c 0223 movs r3, #2 + 7690 004e 0D93 str r3, [sp, #52] + 777:Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 25; + 7691 .loc 1 777 3 is_stmt 1 view .LVU2474 + 777:Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 25; + 7692 .loc 1 777 35 is_stmt 0 view .LVU2475 + 7693 0050 4FF48002 mov r2, #4194304 + 7694 0054 0E92 str r2, [sp, #56] + 778:Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 368; + 7695 .loc 1 778 3 is_stmt 1 view .LVU2476 + 778:Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 368; + 7696 .loc 1 778 30 is_stmt 0 view .LVU2477 + 7697 0056 1922 movs r2, #25 + 7698 0058 0F92 str r2, [sp, #60] + 779:Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + 7699 .loc 1 779 3 is_stmt 1 view .LVU2478 + 779:Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + 7700 .loc 1 779 30 is_stmt 0 view .LVU2479 + 7701 005a 4FF4B872 mov r2, #368 + 7702 005e 1092 str r2, [sp, #64] + 780:Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 8; + 7703 .loc 1 780 3 is_stmt 1 view .LVU2480 + ARM GAS /tmp/ccWQNJQt.s page 511 + + + 780:Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 8; + 7704 .loc 1 780 30 is_stmt 0 view .LVU2481 + 7705 0060 1193 str r3, [sp, #68] + 781:Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2; + 7706 .loc 1 781 3 is_stmt 1 view .LVU2482 + 781:Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2; + 7707 .loc 1 781 30 is_stmt 0 view .LVU2483 + 7708 0062 0822 movs r2, #8 + 7709 0064 1292 str r2, [sp, #72] + 782:Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 7710 .loc 1 782 3 is_stmt 1 view .LVU2484 + 782:Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 7711 .loc 1 782 30 is_stmt 0 view .LVU2485 + 7712 0066 1393 str r3, [sp, #76] + 783:Src/main.c **** { + 7713 .loc 1 783 3 is_stmt 1 view .LVU2486 + 783:Src/main.c **** { + 7714 .loc 1 783 7 is_stmt 0 view .LVU2487 + 7715 0068 07A8 add r0, sp, #28 + 7716 006a FFF7FEFF bl HAL_RCC_OscConfig + 7717 .LVL598: + 783:Src/main.c **** { + 7718 .loc 1 783 6 discriminator 1 view .LVU2488 + 7719 006e B0B9 cbnz r0, .L362 + 790:Src/main.c **** { + 7720 .loc 1 790 3 is_stmt 1 view .LVU2489 + 790:Src/main.c **** { + 7721 .loc 1 790 7 is_stmt 0 view .LVU2490 + 7722 0070 FFF7FEFF bl HAL_PWREx_EnableOverDrive + 7723 .LVL599: + 790:Src/main.c **** { + 7724 .loc 1 790 6 discriminator 1 view .LVU2491 + 7725 0074 A8B9 cbnz r0, .L363 + 797:Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + 7726 .loc 1 797 3 is_stmt 1 view .LVU2492 + 797:Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + 7727 .loc 1 797 31 is_stmt 0 view .LVU2493 + 7728 0076 0F23 movs r3, #15 + 7729 0078 0293 str r3, [sp, #8] + 799:Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 7730 .loc 1 799 3 is_stmt 1 view .LVU2494 + 799:Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 7731 .loc 1 799 34 is_stmt 0 view .LVU2495 + 7732 007a 0223 movs r3, #2 + 7733 007c 0393 str r3, [sp, #12] + 800:Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + 7734 .loc 1 800 3 is_stmt 1 view .LVU2496 + 800:Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + 7735 .loc 1 800 35 is_stmt 0 view .LVU2497 + 7736 007e 0023 movs r3, #0 + 7737 0080 0493 str r3, [sp, #16] + 801:Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + 7738 .loc 1 801 3 is_stmt 1 view .LVU2498 + 801:Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + 7739 .loc 1 801 36 is_stmt 0 view .LVU2499 + 7740 0082 4FF4A053 mov r3, #5120 + 7741 0086 0593 str r3, [sp, #20] + ARM GAS /tmp/ccWQNJQt.s page 512 + + + 802:Src/main.c **** + 7742 .loc 1 802 3 is_stmt 1 view .LVU2500 + 802:Src/main.c **** + 7743 .loc 1 802 36 is_stmt 0 view .LVU2501 + 7744 0088 4FF48053 mov r3, #4096 + 7745 008c 0693 str r3, [sp, #24] + 804:Src/main.c **** { + 7746 .loc 1 804 3 is_stmt 1 view .LVU2502 + 804:Src/main.c **** { + 7747 .loc 1 804 7 is_stmt 0 view .LVU2503 + 7748 008e 0621 movs r1, #6 + 7749 0090 02A8 add r0, sp, #8 + 7750 0092 FFF7FEFF bl HAL_RCC_ClockConfig + 7751 .LVL600: + 804:Src/main.c **** { + 7752 .loc 1 804 6 discriminator 1 view .LVU2504 + 7753 0096 30B9 cbnz r0, .L364 + 808:Src/main.c **** + 7754 .loc 1 808 1 view .LVU2505 + 7755 0098 15B0 add sp, sp, #84 + 7756 .LCFI78: + 7757 .cfi_remember_state + 7758 .cfi_def_cfa_offset 4 + 7759 @ sp needed + 7760 009a 5DF804FB ldr pc, [sp], #4 + 7761 .L362: + 7762 .LCFI79: + 7763 .cfi_restore_state + 785:Src/main.c **** } + 7764 .loc 1 785 5 is_stmt 1 view .LVU2506 + 7765 009e FFF7FEFF bl Error_Handler + 7766 .LVL601: + 7767 .L363: + 792:Src/main.c **** } + 7768 .loc 1 792 5 view .LVU2507 + 7769 00a2 FFF7FEFF bl Error_Handler + 7770 .LVL602: + 7771 .L364: + 806:Src/main.c **** } + 7772 .loc 1 806 5 view .LVU2508 + 7773 00a6 FFF7FEFF bl Error_Handler + 7774 .LVL603: + 7775 .L366: + 7776 00aa 00BF .align 2 + 7777 .L365: + 7778 00ac 00380240 .word 1073887232 + 7779 00b0 00700040 .word 1073770496 + 7780 .cfi_endproc + 7781 .LFE1187: + 7783 .section .text.main,"ax",%progbits + 7784 .align 1 + 7785 .global main + 7786 .syntax unified + 7787 .thumb + 7788 .thumb_func + 7790 main: + 7791 .LFB1186: + ARM GAS /tmp/ccWQNJQt.s page 513 + + + 129:Src/main.c **** + 7792 .loc 1 129 1 view -0 + 7793 .cfi_startproc + 7794 @ args = 0, pretend = 0, frame = 8 + 7795 @ frame_needed = 0, uses_anonymous_args = 0 + 7796 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 7797 .LCFI80: + 7798 .cfi_def_cfa_offset 28 + 7799 .cfi_offset 4, -28 + 7800 .cfi_offset 5, -24 + 7801 .cfi_offset 6, -20 + 7802 .cfi_offset 7, -16 + 7803 .cfi_offset 8, -12 + 7804 .cfi_offset 9, -8 + 7805 .cfi_offset 14, -4 + 7806 0004 83B0 sub sp, sp, #12 + 7807 .LCFI81: + 7808 .cfi_def_cfa_offset 40 + 132:Src/main.c **** /* USER CODE END 1 */ + 7809 .loc 1 132 2 view .LVU2510 + 138:Src/main.c **** + 7810 .loc 1 138 3 view .LVU2511 + 7811 0006 FFF7FEFF bl HAL_Init + 7812 .LVL604: + 145:Src/main.c **** + 7813 .loc 1 145 3 view .LVU2512 + 7814 000a FFF7FEFF bl SystemClock_Config + 7815 .LVL605: + 152:Src/main.c **** MX_DMA_Init(); + 7816 .loc 1 152 3 view .LVU2513 + 7817 000e FFF7FEFF bl MX_GPIO_Init + 7818 .LVL606: + 153:Src/main.c **** MX_SPI4_Init(); + 7819 .loc 1 153 3 view .LVU2514 + 7820 0012 FFF7FEFF bl MX_DMA_Init + 7821 .LVL607: + 154:Src/main.c **** MX_FATFS_Init(); + 7822 .loc 1 154 3 view .LVU2515 + 7823 0016 FFF7FEFF bl MX_SPI4_Init + 7824 .LVL608: + 155:Src/main.c **** MX_TIM2_Init(); + 7825 .loc 1 155 3 view .LVU2516 + 7826 001a FFF7FEFF bl MX_FATFS_Init + 7827 .LVL609: + 156:Src/main.c **** MX_TIM5_Init(); + 7828 .loc 1 156 3 view .LVU2517 + 7829 001e FFF7FEFF bl MX_TIM2_Init + 7830 .LVL610: + 157:Src/main.c **** MX_ADC1_Init(); + 7831 .loc 1 157 3 view .LVU2518 + 7832 0022 FFF7FEFF bl MX_TIM5_Init + 7833 .LVL611: + 158:Src/main.c **** MX_ADC3_Init(); + 7834 .loc 1 158 3 view .LVU2519 + 7835 0026 FFF7FEFF bl MX_ADC1_Init + 7836 .LVL612: + 159:Src/main.c **** MX_SPI2_Init(); + ARM GAS /tmp/ccWQNJQt.s page 514 + + + 7837 .loc 1 159 3 view .LVU2520 + 7838 002a FFF7FEFF bl MX_ADC3_Init + 7839 .LVL613: + 160:Src/main.c **** MX_SPI5_Init(); + 7840 .loc 1 160 3 view .LVU2521 + 7841 002e FFF7FEFF bl MX_SPI2_Init + 7842 .LVL614: + 161:Src/main.c **** MX_SPI6_Init(); + 7843 .loc 1 161 3 view .LVU2522 + 7844 0032 FFF7FEFF bl MX_SPI5_Init + 7845 .LVL615: + 162:Src/main.c **** MX_USART1_UART_Init(); + 7846 .loc 1 162 3 view .LVU2523 + 7847 0036 FFF7FEFF bl MX_SPI6_Init + 7848 .LVL616: + 163:Src/main.c **** MX_SDMMC1_SD_Init(); + 7849 .loc 1 163 3 view .LVU2524 + 7850 003a FFF7FEFF bl MX_USART1_UART_Init + 7851 .LVL617: + 164:Src/main.c **** MX_TIM7_Init(); + 7852 .loc 1 164 3 view .LVU2525 + 7853 003e FFF7FEFF bl MX_SDMMC1_SD_Init + 7854 .LVL618: + 165:Src/main.c **** MX_TIM6_Init(); + 7855 .loc 1 165 3 view .LVU2526 + 7856 0042 FFF7FEFF bl MX_TIM7_Init + 7857 .LVL619: + 166:Src/main.c **** MX_TIM10_Init(); + 7858 .loc 1 166 3 view .LVU2527 + 7859 0046 FFF7FEFF bl MX_TIM6_Init + 7860 .LVL620: + 167:Src/main.c **** MX_UART8_Init(); + 7861 .loc 1 167 3 view .LVU2528 + 7862 004a FFF7FEFF bl MX_TIM10_Init + 7863 .LVL621: + 168:Src/main.c **** MX_TIM8_Init(); + 7864 .loc 1 168 3 view .LVU2529 + 7865 004e FFF7FEFF bl MX_UART8_Init + 7866 .LVL622: + 169:Src/main.c **** MX_TIM11_Init(); + 7867 .loc 1 169 3 view .LVU2530 + 7868 0052 FFF7FEFF bl MX_TIM8_Init + 7869 .LVL623: + 170:Src/main.c **** MX_TIM4_Init(); + 7870 .loc 1 170 3 view .LVU2531 + 7871 0056 FFF7FEFF bl MX_TIM11_Init + 7872 .LVL624: + 171:Src/main.c **** /* USER CODE BEGIN 2 */ + 7873 .loc 1 171 3 view .LVU2532 + 7874 005a FFF7FEFF bl MX_TIM4_Init + 7875 .LVL625: + 173:Src/main.c **** //HAL_TIM_Base_Start(&htim11); + 7876 .loc 1 173 2 view .LVU2533 + 7877 005e FFF7FEFF bl Init_params + 7878 .LVL626: + 184:Src/main.c **** + 7879 .loc 1 184 2 view .LVU2534 + ARM GAS /tmp/ccWQNJQt.s page 515 + + + 184:Src/main.c **** + 7880 .loc 1 184 14 is_stmt 0 view .LVU2535 + 7881 0062 844A ldr r2, .L432 + 7882 0064 3523 movs r3, #53 + 7883 0066 D362 str r3, [r2, #44] + 186:Src/main.c **** + 7884 .loc 1 186 2 is_stmt 1 view .LVU2536 + 186:Src/main.c **** + 7885 .loc 1 186 23 is_stmt 0 view .LVU2537 + 7886 0068 D36A ldr r3, [r2, #44] + 186:Src/main.c **** + 7887 .loc 1 186 30 view .LVU2538 + 7888 006a 0133 adds r3, r3, #1 + 186:Src/main.c **** + 7889 .loc 1 186 33 view .LVU2539 + 7890 006c 5B08 lsrs r3, r3, #1 + 186:Src/main.c **** + 7891 .loc 1 186 36 view .LVU2540 + 7892 006e 013B subs r3, r3, #1 + 186:Src/main.c **** + 7893 .loc 1 186 15 view .LVU2541 + 7894 0070 D363 str r3, [r2, #60] + 190:Src/main.c **** TIM11 -> CCR1 = (TIM11 -> ARR +1)/2 - 1; + 7895 .loc 1 190 2 is_stmt 1 view .LVU2542 + 190:Src/main.c **** TIM11 -> CCR1 = (TIM11 -> ARR +1)/2 - 1; + 7896 .loc 1 190 23 is_stmt 0 view .LVU2543 + 7897 0072 D36A ldr r3, [r2, #44] + 190:Src/main.c **** TIM11 -> CCR1 = (TIM11 -> ARR +1)/2 - 1; + 7898 .loc 1 190 36 view .LVU2544 + 7899 0074 5B00 lsls r3, r3, #1 + 7900 0076 0133 adds r3, r3, #1 + 190:Src/main.c **** TIM11 -> CCR1 = (TIM11 -> ARR +1)/2 - 1; + 7901 .loc 1 190 15 view .LVU2545 + 7902 0078 02F5A032 add r2, r2, #81920 + 7903 007c D362 str r3, [r2, #44] + 191:Src/main.c **** + 7904 .loc 1 191 2 is_stmt 1 view .LVU2546 + 191:Src/main.c **** + 7905 .loc 1 191 25 is_stmt 0 view .LVU2547 + 7906 007e D36A ldr r3, [r2, #44] + 191:Src/main.c **** + 7907 .loc 1 191 32 view .LVU2548 + 7908 0080 0133 adds r3, r3, #1 + 191:Src/main.c **** + 7909 .loc 1 191 35 view .LVU2549 + 7910 0082 5B08 lsrs r3, r3, #1 + 191:Src/main.c **** + 7911 .loc 1 191 38 view .LVU2550 + 7912 0084 013B subs r3, r3, #1 + 191:Src/main.c **** + 7913 .loc 1 191 16 view .LVU2551 + 7914 0086 5363 str r3, [r2, #52] + 7915 0088 4CE0 b .L368 + 7916 .L424: + 205:Src/main.c **** { + 7917 .loc 1 205 85 discriminator 1 view .LVU2552 + 7918 008a 7B4B ldr r3, .L432+4 + ARM GAS /tmp/ccWQNJQt.s page 516 + + + 7919 008c 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 205:Src/main.c **** { + 7920 .loc 1 205 73 discriminator 1 view .LVU2553 + 7921 008e 002B cmp r3, #0 + 7922 0090 4FD1 bne .L369 + 7923 .L370: + 7924 .LBB547: +3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 7925 .loc 7 3073 3 is_stmt 1 discriminator 1 view .LVU2554 + 7926 .LBB548: +3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 7927 .loc 7 3073 3 discriminator 1 view .LVU2555 +3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 7928 .loc 7 3073 3 discriminator 1 view .LVU2556 +3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 7929 .loc 7 3073 3 discriminator 1 view .LVU2557 + 7930 .LVL627: + 7931 .LBB549: + 7932 .LBI549: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 7933 .loc 8 1068 31 view .LVU2558 + 7934 .LBB550: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 7935 .loc 8 1070 5 view .LVU2559 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 7936 .loc 8 1072 4 view .LVU2560 + 7937 0092 7A4A ldr r2, .L432+8 + 7938 .syntax unified + 7939 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 7940 0094 52E8003F ldrex r3, [r2] + 7941 @ 0 "" 2 + 7942 .LVL628: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 7943 .loc 8 1073 4 view .LVU2561 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 7944 .loc 8 1073 4 is_stmt 0 view .LVU2562 + 7945 .thumb + 7946 .syntax unified + 7947 .LBE550: + 7948 .LBE549: +3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 7949 .loc 7 3073 3 discriminator 1 view .LVU2563 + 7950 0098 43F48073 orr r3, r3, #256 + 7951 .LVL629: +3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 7952 .loc 7 3073 3 is_stmt 1 discriminator 1 view .LVU2564 + 7953 .LBB551: + 7954 .LBI551: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 7955 .loc 8 1119 31 view .LVU2565 + 7956 .LBB552: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 7957 .loc 8 1121 4 view .LVU2566 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 7958 .loc 8 1123 4 view .LVU2567 + 7959 .syntax unified + 7960 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + ARM GAS /tmp/ccWQNJQt.s page 517 + + + 7961 009c 42E80031 strex r1, r3, [r2] + 7962 @ 0 "" 2 + 7963 .LVL630: + 7964 .loc 8 1124 4 view .LVU2568 + 7965 .loc 8 1124 4 is_stmt 0 view .LVU2569 + 7966 .thumb + 7967 .syntax unified + 7968 .LBE552: + 7969 .LBE551: +3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 7970 .loc 7 3073 3 discriminator 1 view .LVU2570 + 7971 00a0 0029 cmp r1, #0 + 7972 00a2 F6D1 bne .L370 + 7973 .LVL631: + 7974 .L371: +3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 7975 .loc 7 3073 3 discriminator 1 view .LVU2571 + 7976 .LBE548: + 7977 .LBE547: + 7978 .LBB553: +3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 7979 .loc 7 3040 3 is_stmt 1 discriminator 1 view .LVU2572 + 7980 .LBB554: +3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 7981 .loc 7 3040 3 discriminator 1 view .LVU2573 +3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 7982 .loc 7 3040 3 discriminator 1 view .LVU2574 +3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 7983 .loc 7 3040 3 discriminator 1 view .LVU2575 + 7984 .LBB555: + 7985 .LBI555: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 7986 .loc 8 1068 31 view .LVU2576 + 7987 .LBB556: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 7988 .loc 8 1070 5 view .LVU2577 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 7989 .loc 8 1072 4 view .LVU2578 + 7990 00a4 754A ldr r2, .L432+8 + 7991 .syntax unified + 7992 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 7993 00a6 52E8003F ldrex r3, [r2] + 7994 @ 0 "" 2 + 7995 .LVL632: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 7996 .loc 8 1073 4 view .LVU2579 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 7997 .loc 8 1073 4 is_stmt 0 view .LVU2580 + 7998 .thumb + 7999 .syntax unified + 8000 .LBE556: + 8001 .LBE555: +3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 8002 .loc 7 3040 3 discriminator 1 view .LVU2581 + 8003 00aa 43F02003 orr r3, r3, #32 + 8004 .LVL633: +3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + ARM GAS /tmp/ccWQNJQt.s page 518 + + + 8005 .loc 7 3040 3 is_stmt 1 discriminator 1 view .LVU2582 + 8006 .LBB557: + 8007 .LBI557: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 8008 .loc 8 1119 31 view .LVU2583 + 8009 .LBB558: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 8010 .loc 8 1121 4 view .LVU2584 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 8011 .loc 8 1123 4 view .LVU2585 + 8012 .syntax unified + 8013 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 8014 00ae 42E80031 strex r1, r3, [r2] + 8015 @ 0 "" 2 + 8016 .LVL634: + 8017 .loc 8 1124 4 view .LVU2586 + 8018 .loc 8 1124 4 is_stmt 0 view .LVU2587 + 8019 .thumb + 8020 .syntax unified + 8021 .LBE558: + 8022 .LBE557: +3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 8023 .loc 7 3040 3 discriminator 1 view .LVU2588 + 8024 00b2 0029 cmp r1, #0 + 8025 00b4 F6D1 bne .L371 + 8026 .LVL635: + 8027 .L372: +3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 8028 .loc 7 3040 3 discriminator 1 view .LVU2589 + 8029 .LBE554: + 8030 .LBE553: + 8031 .LBB559: +3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 8032 .loc 7 3136 3 is_stmt 1 discriminator 1 view .LVU2590 + 8033 .LBB560: +3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 8034 .loc 7 3136 3 discriminator 1 view .LVU2591 +3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 8035 .loc 7 3136 3 discriminator 1 view .LVU2592 +3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 8036 .loc 7 3136 3 discriminator 1 view .LVU2593 + 8037 .LBB561: + 8038 .LBI561: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 8039 .loc 8 1068 31 view .LVU2594 + 8040 .LBB562: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 8041 .loc 8 1070 5 view .LVU2595 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 8042 .loc 8 1072 4 view .LVU2596 + 8043 00b6 714A ldr r2, .L432+8 + 8044 00b8 02F10803 add r3, r2, #8 + 8045 .syntax unified + 8046 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 8047 00bc 53E8003F ldrex r3, [r3] + 8048 @ 0 "" 2 + 8049 .LVL636: + ARM GAS /tmp/ccWQNJQt.s page 519 + + +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 8050 .loc 8 1073 4 view .LVU2597 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 8051 .loc 8 1073 4 is_stmt 0 view .LVU2598 + 8052 .thumb + 8053 .syntax unified + 8054 .LBE562: + 8055 .LBE561: +3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 8056 .loc 7 3136 3 discriminator 1 view .LVU2599 + 8057 00c0 43F00103 orr r3, r3, #1 + 8058 .LVL637: +3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 8059 .loc 7 3136 3 is_stmt 1 discriminator 1 view .LVU2600 + 8060 .LBB563: + 8061 .LBI563: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 8062 .loc 8 1119 31 view .LVU2601 + 8063 .LBB564: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 8064 .loc 8 1121 4 view .LVU2602 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 8065 .loc 8 1123 4 view .LVU2603 + 8066 00c4 0832 adds r2, r2, #8 + 8067 .syntax unified + 8068 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 8069 00c6 42E80031 strex r1, r3, [r2] + 8070 @ 0 "" 2 + 8071 .LVL638: + 8072 .loc 8 1124 4 view .LVU2604 + 8073 .loc 8 1124 4 is_stmt 0 view .LVU2605 + 8074 .thumb + 8075 .syntax unified + 8076 .LBE564: + 8077 .LBE563: +3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 8078 .loc 7 3136 3 discriminator 1 view .LVU2606 + 8079 00ca 0029 cmp r1, #0 + 8080 00cc F3D1 bne .L372 + 8081 .LBE560: +3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 8082 .loc 7 3136 3 is_stmt 1 discriminator 2 view .LVU2607 + 8083 .LVL639: +3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 8084 .loc 7 3136 3 is_stmt 0 discriminator 2 view .LVU2608 + 8085 .LBE559: + 211:Src/main.c **** NVIC_EnableIRQ(USART1_IRQn);//In other case you have FE error flag... + 8086 .loc 1 211 4 is_stmt 1 view .LVU2609 + 8087 .LBB565: + 8088 .LBI565: +2024:Drivers/CMSIS/Include/core_cm7.h **** { + 8089 .loc 2 2024 22 view .LVU2610 + 8090 .LBB566: +2026:Drivers/CMSIS/Include/core_cm7.h **** { + 8091 .loc 2 2026 3 view .LVU2611 +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 8092 .loc 2 2028 5 view .LVU2612 + ARM GAS /tmp/ccWQNJQt.s page 520 + + +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 8093 .loc 2 2028 47 is_stmt 0 view .LVU2613 + 8094 00ce 6C4B ldr r3, .L432+12 + 8095 00d0 0022 movs r2, #0 + 8096 00d2 83F82523 strb r2, [r3, #805] + 8097 .LVL640: +2028:Drivers/CMSIS/Include/core_cm7.h **** } + 8098 .loc 2 2028 47 view .LVU2614 + 8099 .LBE566: + 8100 .LBE565: + 212:Src/main.c **** u_rx_flg = 1; + 8101 .loc 1 212 4 is_stmt 1 view .LVU2615 + 8102 .LBB567: + 8103 .LBI567: +1896:Drivers/CMSIS/Include/core_cm7.h **** { + 8104 .loc 2 1896 22 view .LVU2616 + 8105 .LBB568: +1898:Drivers/CMSIS/Include/core_cm7.h **** { + 8106 .loc 2 1898 3 view .LVU2617 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 8107 .loc 2 1900 5 view .LVU2618 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 8108 .loc 2 1900 43 is_stmt 0 view .LVU2619 + 8109 00d6 2022 movs r2, #32 + 8110 00d8 5A60 str r2, [r3, #4] + 8111 .LVL641: +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 8112 .loc 2 1900 43 view .LVU2620 + 8113 .LBE568: + 8114 .LBE567: + 213:Src/main.c **** } + 8115 .loc 1 213 4 is_stmt 1 view .LVU2621 + 213:Src/main.c **** } + 8116 .loc 1 213 13 is_stmt 0 view .LVU2622 + 8117 00da 674B ldr r3, .L432+4 + 8118 00dc 0122 movs r2, #1 + 8119 00de 1A70 strb r2, [r3] + 8120 00e0 27E0 b .L369 + 8121 .L384: + 223:Src/main.c **** task.current_param = task.min_param; + 8122 .loc 1 223 6 is_stmt 1 view .LVU2623 + 223:Src/main.c **** task.current_param = task.min_param; + 8123 .loc 1 223 20 is_stmt 0 view .LVU2624 + 8124 00e2 684B ldr r3, .L432+16 + 8125 00e4 0022 movs r2, #0 + 8126 00e6 1A70 strb r2, [r3] + 224:Src/main.c **** Stop_TIM10(); + 8127 .loc 1 224 6 is_stmt 1 view .LVU2625 + 224:Src/main.c **** Stop_TIM10(); + 8128 .loc 1 224 31 is_stmt 0 view .LVU2626 + 8129 00e8 674B ldr r3, .L432+20 + 8130 00ea 5A68 ldr r2, [r3, #4] @ float + 224:Src/main.c **** Stop_TIM10(); + 8131 .loc 1 224 25 view .LVU2627 + 8132 00ec 1A61 str r2, [r3, #16] @ float + 225:Src/main.c **** break; + 8133 .loc 1 225 6 is_stmt 1 view .LVU2628 + ARM GAS /tmp/ccWQNJQt.s page 521 + + + 8134 00ee FFF7FEFF bl Stop_TIM10 + 8135 .LVL642: + 226:Src/main.c **** case DECODE_ENABLE://1 - Decode rec. message + 8136 .loc 1 226 5 view .LVU2629 + 8137 .L373: + 701:Src/main.c **** { + 8138 .loc 1 701 3 view .LVU2630 + 8139 00f2 664B ldr r3, .L432+24 + 8140 00f4 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 8141 00f6 022B cmp r3, #2 + 8142 00f8 00F01C84 beq .L413 + 8143 00fc 032B cmp r3, #3 + 8144 00fe 00F04F84 beq .L420 + 8145 0102 012B cmp r3, #1 + 8146 0104 09D1 bne .L415 + 704:Src/main.c **** //HAL_UART_Transmit(&huart1, State_Data, 2, 10); + 8147 .loc 1 704 5 view .LVU2631 + 8148 0106 624C ldr r4, .L432+28 + 8149 0108 0221 movs r1, #2 + 8150 010a 2046 mov r0, r4 + 8151 010c FFF7FEFF bl USART_TX + 8152 .LVL643: + 706:Src/main.c **** State_Data[1]=0;//All OK! + 8153 .loc 1 706 5 view .LVU2632 + 706:Src/main.c **** State_Data[1]=0;//All OK! + 8154 .loc 1 706 18 is_stmt 0 view .LVU2633 + 8155 0110 0023 movs r3, #0 + 8156 0112 2370 strb r3, [r4] + 707:Src/main.c **** UART_transmission_request = NO_MESS; + 8157 .loc 1 707 5 is_stmt 1 view .LVU2634 + 707:Src/main.c **** UART_transmission_request = NO_MESS; + 8158 .loc 1 707 18 is_stmt 0 view .LVU2635 + 8159 0114 6370 strb r3, [r4, #1] + 708:Src/main.c **** break; + 8160 .loc 1 708 5 is_stmt 1 view .LVU2636 + 708:Src/main.c **** break; + 8161 .loc 1 708 31 is_stmt 0 view .LVU2637 + 8162 0116 5D4A ldr r2, .L432+24 + 8163 0118 1370 strb r3, [r2] + 709:Src/main.c **** case MESS_02://Transmith packet + 8164 .loc 1 709 4 is_stmt 1 view .LVU2638 + 8165 .L415: + 743:Src/main.c **** { + 8166 .loc 1 743 5 view .LVU2639 + 743:Src/main.c **** { + 8167 .loc 1 743 17 is_stmt 0 view .LVU2640 + 8168 011a 5E4B ldr r3, .L432+32 + 8169 011c 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 743:Src/main.c **** { + 8170 .loc 1 743 8 view .LVU2641 + 8171 011e 012B cmp r3, #1 + 8172 0120 00F04084 beq .L423 + 8173 .L368: + 203:Src/main.c **** { + 8174 .loc 1 203 3 is_stmt 1 view .LVU2642 + 205:Src/main.c **** { + 8175 .loc 1 205 3 view .LVU2643 + ARM GAS /tmp/ccWQNJQt.s page 522 + + + 205:Src/main.c **** { + 8176 .loc 1 205 8 is_stmt 0 view .LVU2644 + 8177 0124 4FF48071 mov r1, #256 + 8178 0128 5B48 ldr r0, .L432+36 + 8179 012a FFF7FEFF bl HAL_GPIO_ReadPin + 8180 .LVL644: + 205:Src/main.c **** { + 8181 .loc 1 205 6 discriminator 1 view .LVU2645 + 8182 012e 0128 cmp r0, #1 + 8183 0130 ABD0 beq .L424 + 8184 .L369: + 220:Src/main.c **** { + 8185 .loc 1 220 4 is_stmt 1 view .LVU2646 + 8186 0132 5A4B ldr r3, .L432+40 + 8187 0134 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 8188 0136 092B cmp r3, #9 + 8189 0138 DBD8 bhi .L373 + 8190 013a 01A2 adr r2, .L375 + 8191 013c 52F823F0 ldr pc, [r2, r3, lsl #2] + 8192 .p2align 2 + 8193 .L375: + 8194 0140 E3000000 .word .L384+1 + 8195 0144 69010000 .word .L383+1 + 8196 0148 D3010000 .word .L382+1 + 8197 014c 09020000 .word .L381+1 + 8198 0150 39020000 .word .L380+1 + 8199 0154 49020000 .word .L379+1 + 8200 0158 65020000 .word .L378+1 + 8201 015c C9020000 .word .L377+1 + 8202 0160 1D040000 .word .L376+1 + 8203 0164 63040000 .word .L374+1 + 8204 .p2align 1 + 8205 .L383: + 228:Src/main.c **** if (CheckChecksum(COMMAND)) + 8206 .loc 1 228 6 view .LVU2647 + 228:Src/main.c **** if (CheckChecksum(COMMAND)) + 8207 .loc 1 228 18 is_stmt 0 view .LVU2648 + 8208 0168 4D4C ldr r4, .L432+44 + 8209 016a 0D21 movs r1, #13 + 8210 016c 2046 mov r0, r4 + 8211 016e FFF7FEFF bl CalculateChecksum + 8212 .LVL645: + 228:Src/main.c **** if (CheckChecksum(COMMAND)) + 8213 .loc 1 228 16 discriminator 1 view .LVU2649 + 8214 0172 4C4B ldr r3, .L432+48 + 8215 0174 1880 strh r0, [r3] @ movhi + 229:Src/main.c **** { + 8216 .loc 1 229 6 is_stmt 1 view .LVU2650 + 229:Src/main.c **** { + 8217 .loc 1 229 10 is_stmt 0 view .LVU2651 + 8218 0176 2046 mov r0, r4 + 8219 0178 FFF7FEFF bl CheckChecksum + 8220 .LVL646: + 229:Src/main.c **** { + 8221 .loc 1 229 9 discriminator 1 view .LVU2652 + 8222 017c 70B9 cbnz r0, .L425 + 242:Src/main.c **** CPU_state = DEFAULT_ENABLE; + ARM GAS /tmp/ccWQNJQt.s page 523 + + + 8223 .loc 1 242 7 is_stmt 1 view .LVU2653 + 242:Src/main.c **** CPU_state = DEFAULT_ENABLE; + 8224 .loc 1 242 17 is_stmt 0 view .LVU2654 + 8225 017e 444A ldr r2, .L432+28 + 8226 0180 1378 ldrb r3, [r2] @ zero_extendqisi2 + 242:Src/main.c **** CPU_state = DEFAULT_ENABLE; + 8227 .loc 1 242 21 view .LVU2655 + 8228 0182 43F00403 orr r3, r3, #4 + 8229 0186 1370 strb r3, [r2] + 243:Src/main.c **** CPU_state_old = HALT;//Save main current cycle + 8230 .loc 1 243 7 is_stmt 1 view .LVU2656 + 243:Src/main.c **** CPU_state_old = HALT;//Save main current cycle + 8231 .loc 1 243 17 is_stmt 0 view .LVU2657 + 8232 0188 444B ldr r3, .L432+40 + 8233 018a 0222 movs r2, #2 + 8234 018c 1A70 strb r2, [r3] + 244:Src/main.c **** } + 8235 .loc 1 244 7 is_stmt 1 view .LVU2658 + 244:Src/main.c **** } + 8236 .loc 1 244 21 is_stmt 0 view .LVU2659 + 8237 018e 3D4B ldr r3, .L432+16 + 8238 0190 0022 movs r2, #0 + 8239 0192 1A70 strb r2, [r3] + 8240 .L386: + 246:Src/main.c **** break; + 8241 .loc 1 246 6 is_stmt 1 view .LVU2660 + 246:Src/main.c **** break; + 8242 .loc 1 246 32 is_stmt 0 view .LVU2661 + 8243 0194 3D4B ldr r3, .L432+24 + 8244 0196 0122 movs r2, #1 + 8245 0198 1A70 strb r2, [r3] + 247:Src/main.c **** case DEFAULT_ENABLE://2 - Go to HALT + 8246 .loc 1 247 5 is_stmt 1 view .LVU2662 + 8247 019a AAE7 b .L373 + 8248 .L425: + 231:Src/main.c **** LL_SPI_Enable(SPI6);//Enable SPI for Laser2 DAC & TEC2 + 8249 .loc 1 231 7 view .LVU2663 + 8250 .LVL647: + 8251 .LBB569: + 8252 .LBI569: + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 8253 .loc 4 358 22 view .LVU2664 + 8254 .LBB570: + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 8255 .loc 4 360 3 view .LVU2665 + 8256 019c 424A ldr r2, .L432+52 + 8257 019e 1368 ldr r3, [r2] + 8258 01a0 43F04003 orr r3, r3, #64 + 8259 01a4 1360 str r3, [r2] + 8260 .LVL648: + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 8261 .loc 4 360 3 is_stmt 0 view .LVU2666 + 8262 .LBE570: + 8263 .LBE569: + 232:Src/main.c **** Decode_uart(COMMAND, &LD1_curr_setup, &LD2_curr_setup, &Curr_setup); + 8264 .loc 1 232 7 is_stmt 1 view .LVU2667 + 8265 .LBB571: + ARM GAS /tmp/ccWQNJQt.s page 524 + + + 8266 .LBI571: + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 8267 .loc 4 358 22 view .LVU2668 + 8268 .LBB572: + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 8269 .loc 4 360 3 view .LVU2669 + 8270 01a6 02F58E32 add r2, r2, #72704 + 8271 01aa 1368 ldr r3, [r2] + 8272 01ac 43F04003 orr r3, r3, #64 + 8273 01b0 1360 str r3, [r2] + 8274 .LVL649: + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 8275 .loc 4 360 3 is_stmt 0 view .LVU2670 + 8276 .LBE572: + 8277 .LBE571: + 233:Src/main.c **** TO6_before = TO6; + 8278 .loc 1 233 7 is_stmt 1 view .LVU2671 + 8279 01b2 3E4B ldr r3, .L432+56 + 8280 01b4 3E4A ldr r2, .L432+60 + 8281 01b6 3F49 ldr r1, .L432+64 + 8282 01b8 2046 mov r0, r4 + 8283 01ba FFF7FEFF bl Decode_uart + 8284 .LVL650: + 234:Src/main.c **** //LD1_param.LD_TEMP_Before = LD1_param.LD_TEMP; + 8285 .loc 1 234 7 view .LVU2672 + 234:Src/main.c **** //LD1_param.LD_TEMP_Before = LD1_param.LD_TEMP; + 8286 .loc 1 234 18 is_stmt 0 view .LVU2673 + 8287 01be 3E4B ldr r3, .L432+68 + 8288 01c0 1A68 ldr r2, [r3] + 8289 01c2 3E4B ldr r3, .L432+72 + 8290 01c4 1A60 str r2, [r3] + 237:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle + 8291 .loc 1 237 7 is_stmt 1 view .LVU2674 + 237:Src/main.c **** CPU_state_old = WORK_ENABLE;//Save main current cycle + 8292 .loc 1 237 17 is_stmt 0 view .LVU2675 + 8293 01c6 0723 movs r3, #7 + 8294 01c8 344A ldr r2, .L432+40 + 8295 01ca 1370 strb r3, [r2] + 238:Src/main.c **** } + 8296 .loc 1 238 7 is_stmt 1 view .LVU2676 + 238:Src/main.c **** } + 8297 .loc 1 238 21 is_stmt 0 view .LVU2677 + 8298 01cc 2D4A ldr r2, .L432+16 + 8299 01ce 1370 strb r3, [r2] + 8300 01d0 E0E7 b .L386 + 8301 .L382: + 250:Src/main.c **** Stop_TIM10(); + 8302 .loc 1 250 6 is_stmt 1 view .LVU2678 + 250:Src/main.c **** Stop_TIM10(); + 8303 .loc 1 250 31 is_stmt 0 view .LVU2679 + 8304 01d2 2D4B ldr r3, .L432+20 + 8305 01d4 5A68 ldr r2, [r3, #4] @ float + 250:Src/main.c **** Stop_TIM10(); + 8306 .loc 1 250 25 view .LVU2680 + 8307 01d6 1A61 str r2, [r3, #16] @ float + 251:Src/main.c **** Init_params(); + 8308 .loc 1 251 6 is_stmt 1 view .LVU2681 + ARM GAS /tmp/ccWQNJQt.s page 525 + + + 8309 01d8 FFF7FEFF bl Stop_TIM10 + 8310 .LVL651: + 252:Src/main.c **** LL_SPI_Disable(SPI2);//Disable SPI for Laser1 DAC & TEC1 + 8311 .loc 1 252 6 view .LVU2682 + 8312 01dc FFF7FEFF bl Init_params + 8313 .LVL652: + 253:Src/main.c **** LL_SPI_Disable(SPI6);//Disable SPI for Laser2 DAC & TEC2 + 8314 .loc 1 253 6 view .LVU2683 + 8315 .LBB573: + 8316 .LBI573: + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 8317 .loc 4 370 22 view .LVU2684 + 8318 .LBB574: + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 8319 .loc 4 372 3 view .LVU2685 + 8320 01e0 314A ldr r2, .L432+52 + 8321 01e2 1368 ldr r3, [r2] + 8322 01e4 23F04003 bic r3, r3, #64 + 8323 01e8 1360 str r3, [r2] + 8324 .LVL653: + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 8325 .loc 4 372 3 is_stmt 0 view .LVU2686 + 8326 .LBE574: + 8327 .LBE573: + 254:Src/main.c **** CPU_state = HALT; + 8328 .loc 1 254 6 is_stmt 1 view .LVU2687 + 8329 .LBB575: + 8330 .LBI575: + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 8331 .loc 4 370 22 view .LVU2688 + 8332 .LBB576: + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 8333 .loc 4 372 3 view .LVU2689 + 8334 01ea 02F58E32 add r2, r2, #72704 + 8335 01ee 1368 ldr r3, [r2] + 8336 01f0 23F04003 bic r3, r3, #64 + 8337 01f4 1360 str r3, [r2] + 8338 .LVL654: + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 8339 .loc 4 372 3 is_stmt 0 view .LVU2690 + 8340 .LBE576: + 8341 .LBE575: + 255:Src/main.c **** CPU_state_old = HALT;//Save main current cycle + 8342 .loc 1 255 6 is_stmt 1 view .LVU2691 + 255:Src/main.c **** CPU_state_old = HALT;//Save main current cycle + 8343 .loc 1 255 16 is_stmt 0 view .LVU2692 + 8344 01f6 0023 movs r3, #0 + 8345 01f8 284A ldr r2, .L432+40 + 8346 01fa 1370 strb r3, [r2] + 256:Src/main.c **** UART_transmission_request = MESS_01; + 8347 .loc 1 256 6 is_stmt 1 view .LVU2693 + 256:Src/main.c **** UART_transmission_request = MESS_01; + 8348 .loc 1 256 20 is_stmt 0 view .LVU2694 + 8349 01fc 214A ldr r2, .L432+16 + 8350 01fe 1370 strb r3, [r2] + 257:Src/main.c **** break; + 8351 .loc 1 257 6 is_stmt 1 view .LVU2695 + ARM GAS /tmp/ccWQNJQt.s page 526 + + + 257:Src/main.c **** break; + 8352 .loc 1 257 32 is_stmt 0 view .LVU2696 + 8353 0200 224B ldr r3, .L432+24 + 8354 0202 0122 movs r2, #1 + 8355 0204 1A70 strb r2, [r3] + 258:Src/main.c **** case TRANS_S_ENABLE://3 - Transmith saved packet Before this operation must to be defaulting! + 8356 .loc 1 258 5 is_stmt 1 view .LVU2697 + 8357 0206 74E7 b .L373 + 8358 .L381: + 260:Src/main.c **** State_Data[0]|=temp16&0xff; + 8359 .loc 1 260 6 view .LVU2698 + 260:Src/main.c **** State_Data[0]|=temp16&0xff; + 8360 .loc 1 260 15 is_stmt 0 view .LVU2699 + 8361 0208 2D48 ldr r0, .L432+76 + 8362 020a FFF7FEFF bl SD_READ + 8363 .LVL655: + 260:Src/main.c **** State_Data[0]|=temp16&0xff; + 8364 .loc 1 260 13 discriminator 1 view .LVU2700 + 8365 020e 82B2 uxth r2, r0 + 8366 0210 2C4B ldr r3, .L432+80 + 8367 0212 1A80 strh r2, [r3] @ movhi + 261:Src/main.c **** if (temp16==0) + 8368 .loc 1 261 6 is_stmt 1 view .LVU2701 + 261:Src/main.c **** if (temp16==0) + 8369 .loc 1 261 16 is_stmt 0 view .LVU2702 + 8370 0214 1E49 ldr r1, .L432+28 + 8371 0216 0B78 ldrb r3, [r1] @ zero_extendqisi2 + 261:Src/main.c **** if (temp16==0) + 8372 .loc 1 261 19 view .LVU2703 + 8373 0218 0343 orrs r3, r3, r0 + 8374 021a 0B70 strb r3, [r1] + 262:Src/main.c **** { + 8375 .loc 1 262 6 is_stmt 1 view .LVU2704 + 262:Src/main.c **** { + 8376 .loc 1 262 9 is_stmt 0 view .LVU2705 + 8377 021c 42B9 cbnz r2, .L387 + 264:Src/main.c **** } + 8378 .loc 1 264 7 is_stmt 1 view .LVU2706 + 264:Src/main.c **** } + 8379 .loc 1 264 33 is_stmt 0 view .LVU2707 + 8380 021e 1B4B ldr r3, .L432+24 + 8381 0220 0322 movs r2, #3 + 8382 0222 1A70 strb r2, [r3] + 8383 .L388: + 270:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle + 8384 .loc 1 270 6 is_stmt 1 view .LVU2708 + 270:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle + 8385 .loc 1 270 20 is_stmt 0 view .LVU2709 + 8386 0224 0023 movs r3, #0 + 8387 0226 174A ldr r2, .L432+16 + 8388 0228 1370 strb r3, [r2] + 271:Src/main.c **** break; + 8389 .loc 1 271 6 is_stmt 1 view .LVU2710 + 271:Src/main.c **** break; + 8390 .loc 1 271 16 is_stmt 0 view .LVU2711 + 8391 022a 1C4A ldr r2, .L432+40 + 8392 022c 1370 strb r3, [r2] + ARM GAS /tmp/ccWQNJQt.s page 527 + + + 272:Src/main.c **** case TRANS_ENABLE://4 - Transmith current packet + 8393 .loc 1 272 5 is_stmt 1 view .LVU2712 + 8394 022e 60E7 b .L373 + 8395 .L387: + 268:Src/main.c **** } + 8396 .loc 1 268 7 view .LVU2713 + 268:Src/main.c **** } + 8397 .loc 1 268 33 is_stmt 0 view .LVU2714 + 8398 0230 164B ldr r3, .L432+24 + 8399 0232 0122 movs r2, #1 + 8400 0234 1A70 strb r2, [r3] + 8401 0236 F5E7 b .L388 + 8402 .L380: + 274:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle + 8403 .loc 1 274 6 is_stmt 1 view .LVU2715 + 274:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle + 8404 .loc 1 274 32 is_stmt 0 view .LVU2716 + 8405 0238 144B ldr r3, .L432+24 + 8406 023a 0222 movs r2, #2 + 8407 023c 1A70 strb r2, [r3] + 275:Src/main.c **** break; + 8408 .loc 1 275 6 is_stmt 1 view .LVU2717 + 275:Src/main.c **** break; + 8409 .loc 1 275 16 is_stmt 0 view .LVU2718 + 8410 023e 114B ldr r3, .L432+16 + 8411 0240 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 8412 0242 164B ldr r3, .L432+40 + 8413 0244 1A70 strb r2, [r3] + 276:Src/main.c **** case REMOVE_FILE://5 - Remove file from SD + 8414 .loc 1 276 5 is_stmt 1 view .LVU2719 + 8415 0246 54E7 b .L373 + 8416 .L379: + 278:Src/main.c **** UART_transmission_request = MESS_01; + 8417 .loc 1 278 6 view .LVU2720 + 278:Src/main.c **** UART_transmission_request = MESS_01; + 8418 .loc 1 278 21 is_stmt 0 view .LVU2721 + 8419 0248 FFF7FEFF bl SD_REMOVE + 8420 .LVL656: + 278:Src/main.c **** UART_transmission_request = MESS_01; + 8421 .loc 1 278 16 discriminator 1 view .LVU2722 + 8422 024c 104A ldr r2, .L432+28 + 8423 024e 1378 ldrb r3, [r2] @ zero_extendqisi2 + 278:Src/main.c **** UART_transmission_request = MESS_01; + 8424 .loc 1 278 19 discriminator 1 view .LVU2723 + 8425 0250 0343 orrs r3, r3, r0 + 8426 0252 1370 strb r3, [r2] + 279:Src/main.c **** CPU_state = CPU_state_old; + 8427 .loc 1 279 6 is_stmt 1 view .LVU2724 + 279:Src/main.c **** CPU_state = CPU_state_old; + 8428 .loc 1 279 32 is_stmt 0 view .LVU2725 + 8429 0254 0D4B ldr r3, .L432+24 + 8430 0256 0122 movs r2, #1 + 8431 0258 1A70 strb r2, [r3] + 280:Src/main.c **** break; + 8432 .loc 1 280 6 is_stmt 1 view .LVU2726 + 280:Src/main.c **** break; + 8433 .loc 1 280 16 is_stmt 0 view .LVU2727 + ARM GAS /tmp/ccWQNJQt.s page 528 + + + 8434 025a 0A4B ldr r3, .L432+16 + 8435 025c 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 8436 025e 0F4B ldr r3, .L432+40 + 8437 0260 1A70 strb r2, [r3] + 281:Src/main.c **** case STATE://6 - Transmith state message + 8438 .loc 1 281 5 is_stmt 1 view .LVU2728 + 8439 0262 46E7 b .L373 + 8440 .L378: + 283:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle + 8441 .loc 1 283 6 view .LVU2729 + 283:Src/main.c **** CPU_state = CPU_state_old;//Return to main current cycle + 8442 .loc 1 283 32 is_stmt 0 view .LVU2730 + 8443 0264 094B ldr r3, .L432+24 + 8444 0266 0122 movs r2, #1 + 8445 0268 1A70 strb r2, [r3] + 284:Src/main.c **** break; + 8446 .loc 1 284 6 is_stmt 1 view .LVU2731 + 284:Src/main.c **** break; + 8447 .loc 1 284 16 is_stmt 0 view .LVU2732 + 8448 026a 064B ldr r3, .L432+16 + 8449 026c 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 8450 026e 0B4B ldr r3, .L432+40 + 8451 0270 1A70 strb r2, [r3] + 285:Src/main.c **** case WORK_ENABLE://7 - Main work cycle + 8452 .loc 1 285 5 is_stmt 1 view .LVU2733 + 8453 0272 3EE7 b .L373 + 8454 .L433: + 8455 .align 2 + 8456 .L432: + 8457 0274 00080040 .word 1073743872 + 8458 0278 00000000 .word u_rx_flg + 8459 027c 00100140 .word 1073811456 + 8460 0280 00E100E0 .word -536813312 + 8461 0284 00000000 .word CPU_state_old + 8462 0288 00000000 .word task + 8463 028c 00000000 .word UART_transmission_request + 8464 0290 00000000 .word State_Data + 8465 0294 00000000 .word flg_tmt + 8466 0298 00000240 .word 1073872896 + 8467 029c 00000000 .word CPU_state + 8468 02a0 00000000 .word COMMAND + 8469 02a4 00000000 .word CS_result + 8470 02a8 00380040 .word 1073756160 + 8471 02ac 00000000 .word Curr_setup + 8472 02b0 00000000 .word LD2_curr_setup + 8473 02b4 00000000 .word LD1_curr_setup + 8474 02b8 00000000 .word TO6 + 8475 02bc 00000000 .word TO6_before + 8476 02c0 00000000 .word Long_Data + 8477 02c4 00000000 .word temp16 + 8478 .L377: + 287:Src/main.c **** Stop_TIM10(); + 8479 .loc 1 287 6 view .LVU2734 + 287:Src/main.c **** Stop_TIM10(); + 8480 .loc 1 287 31 is_stmt 0 view .LVU2735 + 8481 02c8 7A4B ldr r3, .L434 + 8482 02ca 5A68 ldr r2, [r3, #4] @ float + ARM GAS /tmp/ccWQNJQt.s page 529 + + + 287:Src/main.c **** Stop_TIM10(); + 8483 .loc 1 287 25 view .LVU2736 + 8484 02cc 1A61 str r2, [r3, #16] @ float + 288:Src/main.c **** if (TO7>TO7_before)//Main work cycle go with the timer 7 (1000 us or 1 kHz) + 8485 .loc 1 288 6 is_stmt 1 view .LVU2737 + 8486 02ce FFF7FEFF bl Stop_TIM10 + 8487 .LVL657: + 289:Src/main.c **** { + 8488 .loc 1 289 6 view .LVU2738 + 289:Src/main.c **** { + 8489 .loc 1 289 13 is_stmt 0 view .LVU2739 + 8490 02d2 794B ldr r3, .L434+4 + 8491 02d4 1B68 ldr r3, [r3] + 8492 02d6 794A ldr r2, .L434+8 + 8493 02d8 1268 ldr r2, [r2] + 289:Src/main.c **** { + 8494 .loc 1 289 9 view .LVU2740 + 8495 02da 9342 cmp r3, r2 + 8496 02dc 7FF609AF bls .L373 + 291:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 + 8497 .loc 1 291 7 is_stmt 1 view .LVU2741 + 291:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 + 8498 .loc 1 291 18 is_stmt 0 view .LVU2742 + 8499 02e0 764A ldr r2, .L434+8 + 8500 02e2 1360 str r3, [r2] + 292:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 + 8501 .loc 1 292 7 is_stmt 1 view .LVU2743 + 292:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 + 8502 .loc 1 292 25 is_stmt 0 view .LVU2744 + 8503 02e4 0120 movs r0, #1 + 8504 02e6 FFF7FEFF bl MPhD_T + 8505 .LVL658: + 292:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 + 8506 .loc 1 292 23 discriminator 1 view .LVU2745 + 8507 02ea 754F ldr r7, .L434+12 + 8508 02ec 3881 strh r0, [r7, #8] @ movhi + 293:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 + 8509 .loc 1 293 7 is_stmt 1 view .LVU2746 + 293:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 + 8510 .loc 1 293 25 is_stmt 0 view .LVU2747 + 8511 02ee 0120 movs r0, #1 + 8512 02f0 FFF7FEFF bl MPhD_T + 8513 .LVL659: + 293:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 + 8514 .loc 1 293 23 discriminator 1 view .LVU2748 + 8515 02f4 3881 strh r0, [r7, #8] @ movhi + 294:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 + 8516 .loc 1 294 7 is_stmt 1 view .LVU2749 + 294:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 + 8517 .loc 1 294 25 is_stmt 0 view .LVU2750 + 8518 02f6 0220 movs r0, #2 + 8519 02f8 FFF7FEFF bl MPhD_T + 8520 .LVL660: + 294:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 + 8521 .loc 1 294 23 discriminator 1 view .LVU2751 + 8522 02fc 714E ldr r6, .L434+16 + 8523 02fe 3081 strh r0, [r6, #8] @ movhi + ARM GAS /tmp/ccWQNJQt.s page 530 + + + 295:Src/main.c **** + 8524 .loc 1 295 7 is_stmt 1 view .LVU2752 + 295:Src/main.c **** + 8525 .loc 1 295 25 is_stmt 0 view .LVU2753 + 8526 0300 0220 movs r0, #2 + 8527 0302 FFF7FEFF bl MPhD_T + 8528 .LVL661: + 295:Src/main.c **** + 8529 .loc 1 295 23 discriminator 1 view .LVU2754 + 8530 0306 3081 strh r0, [r6, #8] @ movhi + 298:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(3); + 8531 .loc 1 298 7 is_stmt 1 view .LVU2755 + 298:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(3); + 8532 .loc 1 298 14 is_stmt 0 view .LVU2756 + 8533 0308 0320 movs r0, #3 + 8534 030a FFF7FEFF bl MPhD_T + 8535 .LVL662: + 299:Src/main.c **** (void) MPhD_T(4); + 8536 .loc 1 299 7 is_stmt 1 view .LVU2757 + 299:Src/main.c **** (void) MPhD_T(4); + 8537 .loc 1 299 32 is_stmt 0 view .LVU2758 + 8538 030e 0320 movs r0, #3 + 8539 0310 FFF7FEFF bl MPhD_T + 8540 .LVL663: + 299:Src/main.c **** (void) MPhD_T(4); + 8541 .loc 1 299 30 discriminator 1 view .LVU2759 + 8542 0314 3880 strh r0, [r7] @ movhi + 300:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(4); + 8543 .loc 1 300 7 is_stmt 1 view .LVU2760 + 300:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(4); + 8544 .loc 1 300 14 is_stmt 0 view .LVU2761 + 8545 0316 0420 movs r0, #4 + 8546 0318 FFF7FEFF bl MPhD_T + 8547 .LVL664: + 301:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); + 8548 .loc 1 301 7 is_stmt 1 view .LVU2762 + 301:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); + 8549 .loc 1 301 32 is_stmt 0 view .LVU2763 + 8550 031c 0420 movs r0, #4 + 8551 031e FFF7FEFF bl MPhD_T + 8552 .LVL665: + 301:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); + 8553 .loc 1 301 30 discriminator 1 view .LVU2764 + 8554 0322 3080 strh r0, [r6] @ movhi + 302:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 + 8555 .loc 1 302 7 is_stmt 1 view .LVU2765 + 302:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 + 8556 .loc 1 302 14 is_stmt 0 view .LVU2766 + 8557 0324 DFF8D081 ldr r8, .L434+68 + 8558 0328 0122 movs r2, #1 + 8559 032a 3946 mov r1, r7 + 8560 032c 4046 mov r0, r8 + 8561 032e FFF7FEFF bl PID_Controller_Temp + 8562 .LVL666: + 8563 0332 0146 mov r1, r0 + 302:Src/main.c **** Set_LTEC(3, temp16);//Drive Laser TEC 1 + 8564 .loc 1 302 13 discriminator 1 view .LVU2767 + ARM GAS /tmp/ccWQNJQt.s page 531 + + + 8565 0334 644D ldr r5, .L434+20 + 8566 0336 2880 strh r0, [r5] @ movhi + 303:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); + 8567 .loc 1 303 7 is_stmt 1 view .LVU2768 + 8568 0338 0320 movs r0, #3 + 8569 033a FFF7FEFF bl Set_LTEC + 8570 .LVL667: + 304:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 + 8571 .loc 1 304 7 view .LVU2769 + 304:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 + 8572 .loc 1 304 14 is_stmt 0 view .LVU2770 + 8573 033e DFF8B491 ldr r9, .L434+64 + 8574 0342 0222 movs r2, #2 + 8575 0344 3146 mov r1, r6 + 8576 0346 4846 mov r0, r9 + 8577 0348 FFF7FEFF bl PID_Controller_Temp + 8578 .LVL668: + 8579 034c 0146 mov r1, r0 + 304:Src/main.c **** Set_LTEC(4, temp16);//Drive Laser TEC 2 + 8580 .loc 1 304 13 discriminator 1 view .LVU2771 + 8581 034e 2880 strh r0, [r5] @ movhi + 305:Src/main.c **** + 8582 .loc 1 305 7 is_stmt 1 view .LVU2772 + 8583 0350 0420 movs r0, #4 + 8584 0352 FFF7FEFF bl Set_LTEC + 8585 .LVL669: + 307:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data + 8586 .loc 1 307 7 view .LVU2773 + 307:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data + 8587 .loc 1 307 31 is_stmt 0 view .LVU2774 + 8588 0356 3B89 ldrh r3, [r7, #8] + 307:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data + 8589 .loc 1 307 20 view .LVU2775 + 8590 0358 5C4C ldr r4, .L434+24 + 8591 035a 6380 strh r3, [r4, #2] @ movhi + 308:Src/main.c **** + 8592 .loc 1 308 7 is_stmt 1 view .LVU2776 + 308:Src/main.c **** + 8593 .loc 1 308 31 is_stmt 0 view .LVU2777 + 8594 035c 3389 ldrh r3, [r6, #8] + 308:Src/main.c **** + 8595 .loc 1 308 20 view .LVU2778 + 8596 035e A380 strh r3, [r4, #4] @ movhi + 310:Src/main.c **** Set_LTEC(2,LD2_curr_setup.CURRENT);//Drive Laser diode 2 + 8597 .loc 1 310 7 is_stmt 1 view .LVU2779 + 8598 0360 B8F80C10 ldrh r1, [r8, #12] + 8599 0364 0120 movs r0, #1 + 8600 0366 FFF7FEFF bl Set_LTEC + 8601 .LVL670: + 311:Src/main.c **** + 8602 .loc 1 311 7 view .LVU2780 + 8603 036a B9F80C10 ldrh r1, [r9, #12] + 8604 036e 0220 movs r0, #2 + 8605 0370 FFF7FEFF bl Set_LTEC + 8606 .LVL671: + 315:Src/main.c **** temp16 = Get_ADC(1); + 8607 .loc 1 315 7 view .LVU2781 + ARM GAS /tmp/ccWQNJQt.s page 532 + + + 315:Src/main.c **** temp16 = Get_ADC(1); + 8608 .loc 1 315 16 is_stmt 0 view .LVU2782 + 8609 0374 0020 movs r0, #0 + 8610 0376 FFF7FEFF bl Get_ADC + 8611 .LVL672: + 315:Src/main.c **** temp16 = Get_ADC(1); + 8612 .loc 1 315 14 discriminator 1 view .LVU2783 + 8613 037a 2880 strh r0, [r5] @ movhi + 316:Src/main.c **** Long_Data[7] = temp16; // PA2 -- 3V_monitor // PB1 -- U_Rt1_ext_Gain + 8614 .loc 1 316 7 is_stmt 1 view .LVU2784 + 316:Src/main.c **** Long_Data[7] = temp16; // PA2 -- 3V_monitor // PB1 -- U_Rt1_ext_Gain + 8615 .loc 1 316 16 is_stmt 0 view .LVU2785 + 8616 037c 0120 movs r0, #1 + 8617 037e FFF7FEFF bl Get_ADC + 8618 .LVL673: + 316:Src/main.c **** Long_Data[7] = temp16; // PA2 -- 3V_monitor // PB1 -- U_Rt1_ext_Gain + 8619 .loc 1 316 14 discriminator 1 view .LVU2786 + 8620 0382 2880 strh r0, [r5] @ movhi + 317:Src/main.c **** + 8621 .loc 1 317 7 is_stmt 1 view .LVU2787 + 317:Src/main.c **** + 8622 .loc 1 317 20 is_stmt 0 view .LVU2788 + 8623 0384 E081 strh r0, [r4, #14] @ movhi + 320:Src/main.c **** Long_Data[8] = temp16; // PB0 -- U_Rt2_ext_Gain // PB0 -- U_Rt2_ext_Gain + 8624 .loc 1 320 7 is_stmt 1 view .LVU2789 + 320:Src/main.c **** Long_Data[8] = temp16; // PB0 -- U_Rt2_ext_Gain // PB0 -- U_Rt2_ext_Gain + 8625 .loc 1 320 16 is_stmt 0 view .LVU2790 + 8626 0386 0120 movs r0, #1 + 8627 0388 FFF7FEFF bl Get_ADC + 8628 .LVL674: + 320:Src/main.c **** Long_Data[8] = temp16; // PB0 -- U_Rt2_ext_Gain // PB0 -- U_Rt2_ext_Gain + 8629 .loc 1 320 14 discriminator 1 view .LVU2791 + 8630 038c 2880 strh r0, [r5] @ movhi + 321:Src/main.c **** + 8631 .loc 1 321 7 is_stmt 1 view .LVU2792 + 321:Src/main.c **** + 8632 .loc 1 321 20 is_stmt 0 view .LVU2793 + 8633 038e 2082 strh r0, [r4, #16] @ movhi + 324:Src/main.c **** Long_Data[9] = temp16; // PB1 -- U_Rt1_ext_Gain // PA2 -- 3V_monitor + 8634 .loc 1 324 7 is_stmt 1 view .LVU2794 + 324:Src/main.c **** Long_Data[9] = temp16; // PB1 -- U_Rt1_ext_Gain // PA2 -- 3V_monitor + 8635 .loc 1 324 16 is_stmt 0 view .LVU2795 + 8636 0390 0120 movs r0, #1 + 8637 0392 FFF7FEFF bl Get_ADC + 8638 .LVL675: + 324:Src/main.c **** Long_Data[9] = temp16; // PB1 -- U_Rt1_ext_Gain // PA2 -- 3V_monitor + 8639 .loc 1 324 14 discriminator 1 view .LVU2796 + 8640 0396 2880 strh r0, [r5] @ movhi + 325:Src/main.c **** + 8641 .loc 1 325 7 is_stmt 1 view .LVU2797 + 325:Src/main.c **** + 8642 .loc 1 325 20 is_stmt 0 view .LVU2798 + 8643 0398 6082 strh r0, [r4, #18] @ movhi + 328:Src/main.c **** Long_Data[10] = temp16; // PC0 -- 5V1_monitor // PC0 -- 5V1_monitor + 8644 .loc 1 328 7 is_stmt 1 view .LVU2799 + 328:Src/main.c **** Long_Data[10] = temp16; // PC0 -- 5V1_monitor // PC0 -- 5V1_monitor + 8645 .loc 1 328 16 is_stmt 0 view .LVU2800 + ARM GAS /tmp/ccWQNJQt.s page 533 + + + 8646 039a 0120 movs r0, #1 + 8647 039c FFF7FEFF bl Get_ADC + 8648 .LVL676: + 328:Src/main.c **** Long_Data[10] = temp16; // PC0 -- 5V1_monitor // PC0 -- 5V1_monitor + 8649 .loc 1 328 14 discriminator 1 view .LVU2801 + 8650 03a0 2880 strh r0, [r5] @ movhi + 329:Src/main.c **** + 8651 .loc 1 329 7 is_stmt 1 view .LVU2802 + 329:Src/main.c **** + 8652 .loc 1 329 21 is_stmt 0 view .LVU2803 + 8653 03a2 A082 strh r0, [r4, #20] @ movhi + 332:Src/main.c **** Long_Data[11] = temp16; // PC1 -- 5V2_monitor // PC1 -- 5V2_monitor + 8654 .loc 1 332 7 is_stmt 1 view .LVU2804 + 332:Src/main.c **** Long_Data[11] = temp16; // PC1 -- 5V2_monitor // PC1 -- 5V2_monitor + 8655 .loc 1 332 16 is_stmt 0 view .LVU2805 + 8656 03a4 0120 movs r0, #1 + 8657 03a6 FFF7FEFF bl Get_ADC + 8658 .LVL677: + 332:Src/main.c **** Long_Data[11] = temp16; // PC1 -- 5V2_monitor // PC1 -- 5V2_monitor + 8659 .loc 1 332 14 discriminator 1 view .LVU2806 + 8660 03aa 2880 strh r0, [r5] @ movhi + 333:Src/main.c **** temp16 = Get_ADC(2); + 8661 .loc 1 333 7 is_stmt 1 view .LVU2807 + 333:Src/main.c **** temp16 = Get_ADC(2); + 8662 .loc 1 333 21 is_stmt 0 view .LVU2808 + 8663 03ac E082 strh r0, [r4, #22] @ movhi + 334:Src/main.c **** + 8664 .loc 1 334 7 is_stmt 1 view .LVU2809 + 334:Src/main.c **** + 8665 .loc 1 334 16 is_stmt 0 view .LVU2810 + 8666 03ae 0220 movs r0, #2 + 8667 03b0 FFF7FEFF bl Get_ADC + 8668 .LVL678: + 334:Src/main.c **** + 8669 .loc 1 334 14 discriminator 1 view .LVU2811 + 8670 03b4 2880 strh r0, [r5] @ movhi + 337:Src/main.c **** temp16 = Get_ADC(4); + 8671 .loc 1 337 7 is_stmt 1 view .LVU2812 + 337:Src/main.c **** temp16 = Get_ADC(4); + 8672 .loc 1 337 16 is_stmt 0 view .LVU2813 + 8673 03b6 0320 movs r0, #3 + 8674 03b8 FFF7FEFF bl Get_ADC + 8675 .LVL679: + 337:Src/main.c **** temp16 = Get_ADC(4); + 8676 .loc 1 337 14 discriminator 1 view .LVU2814 + 8677 03bc 2880 strh r0, [r5] @ movhi + 338:Src/main.c **** Long_Data[12] = temp16; + 8678 .loc 1 338 7 is_stmt 1 view .LVU2815 + 338:Src/main.c **** Long_Data[12] = temp16; + 8679 .loc 1 338 16 is_stmt 0 view .LVU2816 + 8680 03be 0420 movs r0, #4 + 8681 03c0 FFF7FEFF bl Get_ADC + 8682 .LVL680: + 338:Src/main.c **** Long_Data[12] = temp16; + 8683 .loc 1 338 14 discriminator 1 view .LVU2817 + 8684 03c4 2880 strh r0, [r5] @ movhi + 339:Src/main.c **** temp16 = Get_ADC(5); + ARM GAS /tmp/ccWQNJQt.s page 534 + + + 8685 .loc 1 339 7 is_stmt 1 view .LVU2818 + 339:Src/main.c **** temp16 = Get_ADC(5); + 8686 .loc 1 339 21 is_stmt 0 view .LVU2819 + 8687 03c6 2083 strh r0, [r4, #24] @ movhi + 340:Src/main.c **** + 8688 .loc 1 340 7 is_stmt 1 view .LVU2820 + 340:Src/main.c **** + 8689 .loc 1 340 16 is_stmt 0 view .LVU2821 + 8690 03c8 0520 movs r0, #5 + 8691 03ca FFF7FEFF bl Get_ADC + 8692 .LVL681: + 340:Src/main.c **** + 8693 .loc 1 340 14 discriminator 1 view .LVU2822 + 8694 03ce 2880 strh r0, [r5] @ movhi + 343:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; + 8695 .loc 1 343 7 is_stmt 1 view .LVU2823 + 343:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; + 8696 .loc 1 343 16 is_stmt 0 view .LVU2824 + 8697 03d0 3F4B ldr r3, .L434+28 + 8698 03d2 1B68 ldr r3, [r3] + 8699 03d4 3F4A ldr r2, .L434+32 + 8700 03d6 1360 str r3, [r2] + 344:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; + 8701 .loc 1 344 7 is_stmt 1 view .LVU2825 + 344:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; + 8702 .loc 1 344 20 is_stmt 0 view .LVU2826 + 8703 03d8 E380 strh r3, [r4, #6] @ movhi + 345:Src/main.c **** + 8704 .loc 1 345 7 is_stmt 1 view .LVU2827 + 345:Src/main.c **** + 8705 .loc 1 345 31 is_stmt 0 view .LVU2828 + 8706 03da 1B0C lsrs r3, r3, #16 + 345:Src/main.c **** + 8707 .loc 1 345 20 view .LVU2829 + 8708 03dc 2381 strh r3, [r4, #8] @ movhi + 348:Src/main.c **** + 8709 .loc 1 348 7 is_stmt 1 view .LVU2830 + 348:Src/main.c **** + 8710 .loc 1 348 31 is_stmt 0 view .LVU2831 + 8711 03de 3B88 ldrh r3, [r7] + 348:Src/main.c **** + 8712 .loc 1 348 20 view .LVU2832 + 8713 03e0 6381 strh r3, [r4, #10] @ movhi + 351:Src/main.c **** + 8714 .loc 1 351 7 is_stmt 1 view .LVU2833 + 351:Src/main.c **** + 8715 .loc 1 351 31 is_stmt 0 view .LVU2834 + 8716 03e2 3388 ldrh r3, [r6] + 351:Src/main.c **** + 8717 .loc 1 351 20 view .LVU2835 + 8718 03e4 A381 strh r3, [r4, #12] @ movhi + 353:Src/main.c **** { + 8719 .loc 1 353 7 is_stmt 1 view .LVU2836 + 353:Src/main.c **** { + 8720 .loc 1 353 21 is_stmt 0 view .LVU2837 + 8721 03e6 3C4B ldr r3, .L434+36 + 8722 03e8 DB7A ldrb r3, [r3, #11] @ zero_extendqisi2 + ARM GAS /tmp/ccWQNJQt.s page 535 + + + 353:Src/main.c **** { + 8723 .loc 1 353 10 view .LVU2838 + 8724 03ea 012B cmp r3, #1 + 8725 03ec 03D0 beq .L426 + 8726 .L389: + 360:Src/main.c **** } + 8727 .loc 1 360 7 is_stmt 1 view .LVU2839 + 360:Src/main.c **** } + 8728 .loc 1 360 21 is_stmt 0 view .LVU2840 + 8729 03ee 3B4B ldr r3, .L434+40 + 8730 03f0 0722 movs r2, #7 + 8731 03f2 1A70 strb r2, [r3] + 8732 03f4 7DE6 b .L373 + 8733 .L426: + 355:Src/main.c **** Long_Data[DL_16-1] = CS_result; + 8734 .loc 1 355 8 is_stmt 1 view .LVU2841 + 355:Src/main.c **** Long_Data[DL_16-1] = CS_result; + 8735 .loc 1 355 20 is_stmt 0 view .LVU2842 + 8736 03f6 0234 adds r4, r4, #2 + 8737 03f8 0D21 movs r1, #13 + 8738 03fa 2046 mov r0, r4 + 8739 03fc FFF7FEFF bl CalculateChecksum + 8740 .LVL682: + 8741 0400 0346 mov r3, r0 + 355:Src/main.c **** Long_Data[DL_16-1] = CS_result; + 8742 .loc 1 355 18 discriminator 1 view .LVU2843 + 8743 0402 374A ldr r2, .L434+44 + 8744 0404 1080 strh r0, [r2] @ movhi + 356:Src/main.c **** temp16 = SD_SAVE(&Long_Data[0]); + 8745 .loc 1 356 8 is_stmt 1 view .LVU2844 + 356:Src/main.c **** temp16 = SD_SAVE(&Long_Data[0]); + 8746 .loc 1 356 27 is_stmt 0 view .LVU2845 + 8747 0406 A01E subs r0, r4, #2 + 8748 0408 8383 strh r3, [r0, #28] @ movhi + 357:Src/main.c **** State_Data[0]|=temp16&0xff; + 8749 .loc 1 357 8 is_stmt 1 view .LVU2846 + 357:Src/main.c **** State_Data[0]|=temp16&0xff; + 8750 .loc 1 357 17 is_stmt 0 view .LVU2847 + 8751 040a FFF7FEFF bl SD_SAVE + 8752 .LVL683: + 8753 040e 0346 mov r3, r0 + 357:Src/main.c **** State_Data[0]|=temp16&0xff; + 8754 .loc 1 357 15 discriminator 1 view .LVU2848 + 8755 0410 2880 strh r0, [r5] @ movhi + 358:Src/main.c **** } + 8756 .loc 1 358 8 is_stmt 1 view .LVU2849 + 358:Src/main.c **** } + 8757 .loc 1 358 18 is_stmt 0 view .LVU2850 + 8758 0412 3449 ldr r1, .L434+48 + 8759 0414 0A78 ldrb r2, [r1] @ zero_extendqisi2 + 358:Src/main.c **** } + 8760 .loc 1 358 21 view .LVU2851 + 8761 0416 1343 orrs r3, r3, r2 + 8762 0418 0B70 strb r3, [r1] + 8763 041a E8E7 b .L389 + 8764 .L376: + 364:Src/main.c **** { + ARM GAS /tmp/ccWQNJQt.s page 536 + + + 8765 .loc 1 364 6 is_stmt 1 view .LVU2852 + 364:Src/main.c **** { + 8766 .loc 1 364 10 is_stmt 0 view .LVU2853 + 8767 041c 3248 ldr r0, .L434+52 + 8768 041e FFF7FEFF bl CheckChecksum + 8769 .LVL684: + 364:Src/main.c **** { + 8770 .loc 1 364 9 discriminator 1 view .LVU2854 + 8771 0422 70B9 cbnz r0, .L427 + 373:Src/main.c **** CPU_state = DEFAULT_ENABLE; + 8772 .loc 1 373 7 is_stmt 1 view .LVU2855 + 373:Src/main.c **** CPU_state = DEFAULT_ENABLE; + 8773 .loc 1 373 17 is_stmt 0 view .LVU2856 + 8774 0424 2F4A ldr r2, .L434+48 + 8775 0426 1378 ldrb r3, [r2] @ zero_extendqisi2 + 373:Src/main.c **** CPU_state = DEFAULT_ENABLE; + 8776 .loc 1 373 21 view .LVU2857 + 8777 0428 43F00403 orr r3, r3, #4 + 8778 042c 1370 strb r3, [r2] + 374:Src/main.c **** CPU_state_old = HALT;//Save main current cycle + 8779 .loc 1 374 7 is_stmt 1 view .LVU2858 + 374:Src/main.c **** CPU_state_old = HALT;//Save main current cycle + 8780 .loc 1 374 17 is_stmt 0 view .LVU2859 + 8781 042e 2F4B ldr r3, .L434+56 + 8782 0430 0222 movs r2, #2 + 8783 0432 1A70 strb r2, [r3] + 375:Src/main.c **** } + 8784 .loc 1 375 7 is_stmt 1 view .LVU2860 + 375:Src/main.c **** } + 8785 .loc 1 375 21 is_stmt 0 view .LVU2861 + 8786 0434 294B ldr r3, .L434+40 + 8787 0436 0022 movs r2, #0 + 8788 0438 1A70 strb r2, [r3] + 8789 .L391: + 377:Src/main.c **** break; + 8790 .loc 1 377 6 is_stmt 1 view .LVU2862 + 377:Src/main.c **** break; + 8791 .loc 1 377 32 is_stmt 0 view .LVU2863 + 8792 043a 2D4B ldr r3, .L434+60 + 8793 043c 0122 movs r2, #1 + 8794 043e 1A70 strb r2, [r3] + 378:Src/main.c **** case RUN_TASK: + 8795 .loc 1 378 5 is_stmt 1 view .LVU2864 + 8796 0440 57E6 b .L373 + 8797 .L427: + 366:Src/main.c **** TO6_before = TO6; + 8798 .loc 1 366 7 view .LVU2865 + 8799 0442 254B ldr r3, .L434+36 + 8800 0444 2B4A ldr r2, .L434+64 + 8801 0446 2C49 ldr r1, .L434+68 + 8802 0448 2748 ldr r0, .L434+52 + 8803 044a FFF7FEFF bl Decode_task + 8804 .LVL685: + 367:Src/main.c **** CPU_state = RUN_TASK; + 8805 .loc 1 367 7 view .LVU2866 + 367:Src/main.c **** CPU_state = RUN_TASK; + 8806 .loc 1 367 18 is_stmt 0 view .LVU2867 + ARM GAS /tmp/ccWQNJQt.s page 537 + + + 8807 044e 204B ldr r3, .L434+28 + 8808 0450 1A68 ldr r2, [r3] + 8809 0452 2A4B ldr r3, .L434+72 + 8810 0454 1A60 str r2, [r3] + 368:Src/main.c **** CPU_state_old = RUN_TASK;//Save main current cycle + 8811 .loc 1 368 7 is_stmt 1 view .LVU2868 + 368:Src/main.c **** CPU_state_old = RUN_TASK;//Save main current cycle + 8812 .loc 1 368 17 is_stmt 0 view .LVU2869 + 8813 0456 0923 movs r3, #9 + 8814 0458 244A ldr r2, .L434+56 + 8815 045a 1370 strb r3, [r2] + 369:Src/main.c **** } + 8816 .loc 1 369 7 is_stmt 1 view .LVU2870 + 369:Src/main.c **** } + 8817 .loc 1 369 21 is_stmt 0 view .LVU2871 + 8818 045c 1F4A ldr r2, .L434+40 + 8819 045e 1370 strb r3, [r2] + 8820 0460 EBE7 b .L391 + 8821 .L374: + 380:Src/main.c **** { + 8822 .loc 1 380 6 is_stmt 1 view .LVU2872 + 380:Src/main.c **** { + 8823 .loc 1 380 18 is_stmt 0 view .LVU2873 + 8824 0462 144B ldr r3, .L434 + 8825 0464 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 8826 0466 012B cmp r3, #1 + 8827 0468 54D0 beq .L392 + 8828 046a 022B cmp r3, #2 + 8829 046c 00F03781 beq .L393 + 8830 .L394: + 635:Src/main.c **** { + 8831 .loc 1 635 6 is_stmt 1 view .LVU2874 + 635:Src/main.c **** { + 8832 .loc 1 635 13 is_stmt 0 view .LVU2875 + 8833 0470 114B ldr r3, .L434+4 + 8834 0472 1B68 ldr r3, [r3] + 8835 0474 114A ldr r2, .L434+8 + 8836 0476 1268 ldr r2, [r2] + 635:Src/main.c **** { + 8837 .loc 1 635 9 view .LVU2876 + 8838 0478 9342 cmp r3, r2 + 8839 047a 00F20882 bhi .L428 + 8840 .L411: + 687:Src/main.c **** + 8841 .loc 1 687 13 is_stmt 1 discriminator 1 view .LVU2877 + 8842 047e 204B ldr r3, .L434+76 + 8843 0480 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 8844 0482 002B cmp r3, #0 + 8845 0484 FBD0 beq .L411 + 689:Src/main.c **** + 8846 .loc 1 689 6 view .LVU2878 + 8847 0486 FFF7FEFF bl Stop_TIM10 + 8848 .LVL686: + 691:Src/main.c **** { + 8849 .loc 1 691 6 view .LVU2879 + 691:Src/main.c **** { + 8850 .loc 1 691 14 is_stmt 0 view .LVU2880 + ARM GAS /tmp/ccWQNJQt.s page 538 + + + 8851 048a 0A4B ldr r3, .L434 + 8852 048c DB8A ldrh r3, [r3, #22] + 691:Src/main.c **** { + 8853 .loc 1 691 9 view .LVU2881 + 8854 048e 032B cmp r3, #3 + 8855 0490 0BD9 bls .L412 + 693:Src/main.c **** TO10_counter = task.dt / 10; + 8856 .loc 1 693 7 is_stmt 1 view .LVU2882 + 693:Src/main.c **** TO10_counter = task.dt / 10; + 8857 .loc 1 693 26 is_stmt 0 view .LVU2883 + 8858 0492 1C4B ldr r3, .L434+80 + 8859 0494 1A68 ldr r2, [r3] + 8860 0496 1C4B ldr r3, .L434+84 + 8861 0498 DA60 str r2, [r3, #12] + 694:Src/main.c **** } + 8862 .loc 1 694 7 is_stmt 1 view .LVU2884 + 694:Src/main.c **** } + 8863 .loc 1 694 26 is_stmt 0 view .LVU2885 + 8864 049a 064B ldr r3, .L434 + 8865 049c 1B7D ldrb r3, [r3, #20] @ zero_extendqisi2 + 694:Src/main.c **** } + 8866 .loc 1 694 30 view .LVU2886 + 8867 049e 1B4A ldr r2, .L434+88 + 8868 04a0 A2FB0323 umull r2, r3, r2, r3 + 8869 04a4 DB08 lsrs r3, r3, #3 + 694:Src/main.c **** } + 8870 .loc 1 694 20 view .LVU2887 + 8871 04a6 1A4A ldr r2, .L434+92 + 8872 04a8 1360 str r3, [r2] + 8873 .L412: + 697:Src/main.c **** break; + 8874 .loc 1 697 6 is_stmt 1 view .LVU2888 + 697:Src/main.c **** break; + 8875 .loc 1 697 20 is_stmt 0 view .LVU2889 + 8876 04aa 0C4B ldr r3, .L434+40 + 8877 04ac 0922 movs r2, #9 + 8878 04ae 1A70 strb r2, [r3] + 698:Src/main.c **** } + 8879 .loc 1 698 9 is_stmt 1 view .LVU2890 + 8880 04b0 1FE6 b .L373 + 8881 .L435: + 8882 04b2 00BF .align 2 + 8883 .L434: + 8884 04b4 00000000 .word task + 8885 04b8 00000000 .word TO7 + 8886 04bc 00000000 .word TO7_before + 8887 04c0 00000000 .word LD1_param + 8888 04c4 00000000 .word LD2_param + 8889 04c8 00000000 .word temp16 + 8890 04cc 00000000 .word Long_Data + 8891 04d0 00000000 .word TO6 + 8892 04d4 00000000 .word TO6_stop + 8893 04d8 00000000 .word Curr_setup + 8894 04dc 00000000 .word CPU_state_old + 8895 04e0 00000000 .word CS_result + 8896 04e4 00000000 .word State_Data + 8897 04e8 00000000 .word COMMAND + ARM GAS /tmp/ccWQNJQt.s page 539 + + + 8898 04ec 00000000 .word CPU_state + 8899 04f0 00000000 .word UART_transmission_request + 8900 04f4 00000000 .word LD2_curr_setup + 8901 04f8 00000000 .word LD1_curr_setup + 8902 04fc 00000000 .word TO6_before + 8903 0500 00000000 .word TIM10_coflag + 8904 0504 00000000 .word TIM10_period + 8905 0508 00000000 .word htim10 + 8906 050c CDCCCCCC .word -858993459 + 8907 0510 00000000 .word TO10_counter + 8908 .L392: + 8909 .LBB577: + 402:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); + 8910 .loc 1 402 7 view .LVU2891 + 402:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); + 8911 .loc 1 402 38 is_stmt 0 view .LVU2892 + 8912 0514 AD4B ldr r3, .L436 + 8913 0516 D3ED077A vldr.32 s15, [r3, #28] + 402:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); + 8914 .loc 1 402 7 view .LVU2893 + 8915 051a FCEEE77A vcvt.u32.f32 s15, s15 + 8916 051e 17EE903A vmov r3, s15 @ int + 8917 0522 99B2 uxth r1, r3 + 8918 0524 0220 movs r0, #2 + 8919 0526 FFF7FEFF bl Set_LTEC + 8920 .LVL687: + 403:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); + 8921 .loc 1 403 7 is_stmt 1 view .LVU2894 + 403:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); + 8922 .loc 1 403 14 is_stmt 0 view .LVU2895 + 8923 052a 0320 movs r0, #3 + 8924 052c FFF7FEFF bl MPhD_T + 8925 .LVL688: + 404:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); + 8926 .loc 1 404 7 is_stmt 1 view .LVU2896 + 404:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); + 8927 .loc 1 404 32 is_stmt 0 view .LVU2897 + 8928 0530 0320 movs r0, #3 + 8929 0532 FFF7FEFF bl MPhD_T + 8930 .LVL689: + 404:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); + 8931 .loc 1 404 30 discriminator 1 view .LVU2898 + 8932 0536 A64C ldr r4, .L436+4 + 8933 0538 2080 strh r0, [r4] @ movhi + 405:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); + 8934 .loc 1 405 7 is_stmt 1 view .LVU2899 + 405:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); + 8935 .loc 1 405 14 is_stmt 0 view .LVU2900 + 8936 053a 0420 movs r0, #4 + 8937 053c FFF7FEFF bl MPhD_T + 8938 .LVL690: + 406:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); + 8939 .loc 1 406 7 is_stmt 1 view .LVU2901 + 406:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); + 8940 .loc 1 406 32 is_stmt 0 view .LVU2902 + 8941 0540 0420 movs r0, #4 + 8942 0542 FFF7FEFF bl MPhD_T + ARM GAS /tmp/ccWQNJQt.s page 540 + + + 8943 .LVL691: + 406:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); + 8944 .loc 1 406 30 discriminator 1 view .LVU2903 + 8945 0546 A34D ldr r5, .L436+8 + 8946 0548 2880 strh r0, [r5] @ movhi + 407:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 + 8947 .loc 1 407 7 is_stmt 1 view .LVU2904 + 407:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 + 8948 .loc 1 407 14 is_stmt 0 view .LVU2905 + 8949 054a 0122 movs r2, #1 + 8950 054c 2146 mov r1, r4 + 8951 054e A248 ldr r0, .L436+12 + 8952 0550 FFF7FEFF bl PID_Controller_Temp + 8953 .LVL692: + 8954 0554 0146 mov r1, r0 + 407:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 + 8955 .loc 1 407 13 discriminator 1 view .LVU2906 + 8956 0556 A14C ldr r4, .L436+16 + 8957 0558 2080 strh r0, [r4] @ movhi + 408:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); + 8958 .loc 1 408 7 is_stmt 1 view .LVU2907 + 8959 055a 0320 movs r0, #3 + 8960 055c FFF7FEFF bl Set_LTEC + 8961 .LVL693: + 409:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 + 8962 .loc 1 409 7 view .LVU2908 + 409:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 + 8963 .loc 1 409 14 is_stmt 0 view .LVU2909 + 8964 0560 0222 movs r2, #2 + 8965 0562 2946 mov r1, r5 + 8966 0564 9E48 ldr r0, .L436+20 + 8967 0566 FFF7FEFF bl PID_Controller_Temp + 8968 .LVL694: + 8969 056a 0146 mov r1, r0 + 409:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 + 8970 .loc 1 409 13 discriminator 1 view .LVU2910 + 8971 056c 2080 strh r0, [r4] @ movhi + 410:Src/main.c **** + 8972 .loc 1 410 7 is_stmt 1 view .LVU2911 + 8973 056e 0420 movs r0, #4 + 8974 0570 FFF7FEFF bl Set_LTEC + 8975 .LVL695: + 413:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); + 8976 .loc 1 413 7 view .LVU2912 + 8977 0574 9B4C ldr r4, .L436+24 + 8978 0576 0122 movs r2, #1 + 8979 0578 8021 movs r1, #128 + 8980 057a 2046 mov r0, r4 + 8981 057c FFF7FEFF bl HAL_GPIO_WritePin + 8982 .LVL696: + 414:Src/main.c **** + 8983 .loc 1 414 7 view .LVU2913 + 8984 0580 0022 movs r2, #0 + 8985 0582 8021 movs r1, #128 + 8986 0584 2046 mov r0, r4 + 8987 0586 FFF7FEFF bl HAL_GPIO_WritePin + 8988 .LVL697: + ARM GAS /tmp/ccWQNJQt.s page 541 + + + 416:Src/main.c **** if (st != HAL_OK) + 8989 .loc 1 416 7 view .LVU2914 + 416:Src/main.c **** if (st != HAL_OK) + 8990 .loc 1 416 12 is_stmt 0 view .LVU2915 + 8991 058a 9748 ldr r0, .L436+28 + 8992 058c FFF7FEFF bl HAL_TIM_Base_Start_IT + 8993 .LVL698: + 417:Src/main.c **** while(1); + 8994 .loc 1 417 7 is_stmt 1 view .LVU2916 + 417:Src/main.c **** while(1); + 8995 .loc 1 417 10 is_stmt 0 view .LVU2917 + 8996 0590 0028 cmp r0, #0 + 8997 0592 75D1 bne .L396 + 420:Src/main.c **** uint16_t trigger_counter = 0; + 8998 .loc 1 420 7 is_stmt 1 view .LVU2918 + 8999 .LVL699: + 421:Src/main.c **** uint16_t trigger_step = (uint8_t )((task.max_param - task.current_param)/task.delta_param * 1 + 9000 .loc 1 421 7 view .LVU2919 + 422:Src/main.c **** uint16_t task_sheduler = 0; + 9001 .loc 1 422 7 view .LVU2920 + 422:Src/main.c **** uint16_t task_sheduler = 0; + 9002 .loc 1 422 47 is_stmt 0 view .LVU2921 + 9003 0594 8D4B ldr r3, .L436 + 9004 0596 93ED027A vldr.32 s14, [r3, #8] + 422:Src/main.c **** uint16_t task_sheduler = 0; + 9005 .loc 1 422 64 view .LVU2922 + 9006 059a D3ED047A vldr.32 s15, [r3, #16] + 422:Src/main.c **** uint16_t task_sheduler = 0; + 9007 .loc 1 422 58 view .LVU2923 + 9008 059e 37EE677A vsub.f32 s14, s14, s15 + 422:Src/main.c **** uint16_t task_sheduler = 0; + 9009 .loc 1 422 84 view .LVU2924 + 9010 05a2 D3ED036A vldr.32 s13, [r3, #12] + 422:Src/main.c **** uint16_t task_sheduler = 0; + 9011 .loc 1 422 79 view .LVU2925 + 9012 05a6 C7EE267A vdiv.f32 s15, s14, s13 + 422:Src/main.c **** uint16_t task_sheduler = 0; + 9013 .loc 1 422 97 view .LVU2926 + 9014 05aa B2EE047A vmov.f32 s14, #1.0e+1 + 9015 05ae 67EE877A vmul.f32 s15, s15, s14 + 422:Src/main.c **** uint16_t task_sheduler = 0; + 9016 .loc 1 422 31 view .LVU2927 + 9017 05b2 FCEEE77A vcvt.u32.f32 s15, s15 + 9018 05b6 CDED017A vstr.32 s15, [sp, #4] @ int + 9019 05ba 9DF80460 ldrb r6, [sp, #4] @ zero_extendqisi2 + 9020 .LVL700: + 423:Src/main.c **** + 9021 .loc 1 423 7 is_stmt 1 view .LVU2928 + 427:Src/main.c **** HAL_TIM_PWM_Stop(&htim4, TIM_CHANNEL_3); //start ADC clock + 9022 .loc 1 427 7 view .LVU2929 + 9023 05be DFF85492 ldr r9, .L436+72 + 9024 05c2 0021 movs r1, #0 + 9025 05c4 4846 mov r0, r9 + 9026 .LVL701: + 427:Src/main.c **** HAL_TIM_PWM_Stop(&htim4, TIM_CHANNEL_3); //start ADC clock + 9027 .loc 1 427 7 is_stmt 0 view .LVU2930 + 9028 05c6 FFF7FEFF bl HAL_TIM_PWM_Stop + ARM GAS /tmp/ccWQNJQt.s page 542 + + + 9029 .LVL702: + 428:Src/main.c **** TIM11 -> CR1 &= ~(1 << 3); //disables one-pulse mode + 9030 .loc 1 428 7 is_stmt 1 view .LVU2931 + 9031 05ca DFF84C82 ldr r8, .L436+76 + 9032 05ce 0821 movs r1, #8 + 9033 05d0 4046 mov r0, r8 + 9034 05d2 FFF7FEFF bl HAL_TIM_PWM_Stop + 9035 .LVL703: + 429:Src/main.c **** TIM4 -> CR1 &= ~(1 << 3); //disables one-pulse mode + 9036 .loc 1 429 7 view .LVU2932 + 429:Src/main.c **** TIM4 -> CR1 &= ~(1 << 3); //disables one-pulse mode + 9037 .loc 1 429 13 is_stmt 0 view .LVU2933 + 9038 05d6 854F ldr r7, .L436+32 + 9039 05d8 3B68 ldr r3, [r7] + 429:Src/main.c **** TIM4 -> CR1 &= ~(1 << 3); //disables one-pulse mode + 9040 .loc 1 429 20 view .LVU2934 + 9041 05da 23F00803 bic r3, r3, #8 + 9042 05de 3B60 str r3, [r7] + 430:Src/main.c **** + 9043 .loc 1 430 7 is_stmt 1 view .LVU2935 + 430:Src/main.c **** + 9044 .loc 1 430 12 is_stmt 0 view .LVU2936 + 9045 05e0 834D ldr r5, .L436+36 + 9046 05e2 2B68 ldr r3, [r5] + 430:Src/main.c **** + 9047 .loc 1 430 19 view .LVU2937 + 9048 05e4 23F00803 bic r3, r3, #8 + 9049 05e8 2B60 str r3, [r5] + 434:Src/main.c **** TIM4 -> CNT = 0; + 9050 .loc 1 434 7 is_stmt 1 view .LVU2938 + 434:Src/main.c **** TIM4 -> CNT = 0; + 9051 .loc 1 434 20 is_stmt 0 view .LVU2939 + 9052 05ea 0024 movs r4, #0 + 9053 05ec 7C62 str r4, [r7, #36] + 435:Src/main.c **** + 9054 .loc 1 435 7 is_stmt 1 view .LVU2940 + 435:Src/main.c **** + 9055 .loc 1 435 19 is_stmt 0 view .LVU2941 + 9056 05ee 6C62 str r4, [r5, #36] + 437:Src/main.c **** HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); //start ADC clock + 9057 .loc 1 437 7 is_stmt 1 view .LVU2942 + 9058 05f0 2146 mov r1, r4 + 9059 05f2 4846 mov r0, r9 + 9060 05f4 FFF7FEFF bl HAL_TIM_PWM_Start + 9061 .LVL704: + 438:Src/main.c **** //TIM4 -> CNT = 0; + 9062 .loc 1 438 7 view .LVU2943 + 9063 05f8 0821 movs r1, #8 + 9064 05fa 4046 mov r0, r8 + 9065 05fc FFF7FEFF bl HAL_TIM_PWM_Start + 9066 .LVL705: + 441:Src/main.c **** TIM11 -> CNT = 0; + 9067 .loc 1 441 7 view .LVU2944 + 441:Src/main.c **** TIM11 -> CNT = 0; + 9068 .loc 1 441 26 is_stmt 0 view .LVU2945 + 9069 0600 EB6A ldr r3, [r5, #44] + 441:Src/main.c **** TIM11 -> CNT = 0; + ARM GAS /tmp/ccWQNJQt.s page 543 + + + 9070 .loc 1 441 33 view .LVU2946 + 9071 0602 143B subs r3, r3, #20 + 441:Src/main.c **** TIM11 -> CNT = 0; + 9072 .loc 1 441 19 view .LVU2947 + 9073 0604 6B62 str r3, [r5, #36] + 442:Src/main.c **** + 9074 .loc 1 442 7 is_stmt 1 view .LVU2948 + 442:Src/main.c **** + 9075 .loc 1 442 20 is_stmt 0 view .LVU2949 + 9076 0606 7C62 str r4, [r7, #36] + 445:Src/main.c **** { + 9077 .loc 1 445 7 is_stmt 1 view .LVU2950 + 421:Src/main.c **** uint16_t trigger_step = (uint8_t )((task.max_param - task.current_param)/task.delta_param * 1 + 9078 .loc 1 421 16 is_stmt 0 view .LVU2951 + 9079 0608 2546 mov r5, r4 + 9080 .LVL706: + 9081 .L398: + 445:Src/main.c **** { + 9082 .loc 1 445 33 is_stmt 1 view .LVU2952 + 445:Src/main.c **** { + 9083 .loc 1 445 18 is_stmt 0 view .LVU2953 + 9084 060a 704B ldr r3, .L436 + 9085 060c D3ED047A vldr.32 s15, [r3, #16] + 445:Src/main.c **** { + 9086 .loc 1 445 39 view .LVU2954 + 9087 0610 93ED027A vldr.32 s14, [r3, #8] + 445:Src/main.c **** { + 9088 .loc 1 445 33 view .LVU2955 + 9089 0614 F4EEC77A vcmpe.f32 s15, s14 + 9090 0618 F1EE10FA vmrs APSR_nzcv, FPSCR + 9091 061c 37D5 bpl .L429 + 447:Src/main.c **** { + 9092 .loc 1 447 8 is_stmt 1 view .LVU2956 + 447:Src/main.c **** { + 9093 .loc 1 447 12 is_stmt 0 view .LVU2957 + 9094 061e 754B ldr r3, .L436+40 + 9095 0620 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 447:Src/main.c **** { + 9096 .loc 1 447 11 view .LVU2958 + 9097 0622 002B cmp r3, #0 + 9098 0624 F1D0 beq .L398 + 449:Src/main.c **** //TIM11 -> CNT = 0; // to link modulator phase + 9099 .loc 1 449 9 is_stmt 1 view .LVU2959 + 9100 0626 FCEEE77A vcvt.u32.f32 s15, s15 + 9101 062a 17EE903A vmov r3, s15 @ int + 9102 062e 99B2 uxth r1, r3 + 9103 0630 0120 movs r0, #1 + 9104 0632 FFF7FEFF bl Set_LTEC + 9105 .LVL707: + 452:Src/main.c **** TO10 = 0; + 9106 .loc 1 452 9 view .LVU2960 + 452:Src/main.c **** TO10 = 0; + 9107 .loc 1 452 13 is_stmt 0 view .LVU2961 + 9108 0636 654B ldr r3, .L436 + 9109 0638 D3ED047A vldr.32 s15, [r3, #16] + 452:Src/main.c **** TO10 = 0; + 9110 .loc 1 452 35 view .LVU2962 + ARM GAS /tmp/ccWQNJQt.s page 544 + + + 9111 063c 93ED037A vldr.32 s14, [r3, #12] + 452:Src/main.c **** TO10 = 0; + 9112 .loc 1 452 28 view .LVU2963 + 9113 0640 77EE877A vadd.f32 s15, s15, s14 + 9114 0644 C3ED047A vstr.32 s15, [r3, #16] + 453:Src/main.c **** TIM10_coflag = 0; + 9115 .loc 1 453 9 is_stmt 1 view .LVU2964 + 453:Src/main.c **** TIM10_coflag = 0; + 9116 .loc 1 453 14 is_stmt 0 view .LVU2965 + 9117 0648 0027 movs r7, #0 + 9118 064a 6B4B ldr r3, .L436+44 + 9119 064c 1F60 str r7, [r3] + 454:Src/main.c **** + 9120 .loc 1 454 9 is_stmt 1 view .LVU2966 + 454:Src/main.c **** + 9121 .loc 1 454 22 is_stmt 0 view .LVU2967 + 9122 064e 694B ldr r3, .L436+40 + 9123 0650 1F70 strb r7, [r3] + 456:Src/main.c **** HAL_GPIO_WritePin(GPIOG, GPIO_PIN_9, GPIO_PIN_RESET); + 9124 .loc 1 456 9 is_stmt 1 view .LVU2968 + 9125 0652 DFF8C881 ldr r8, .L436+80 + 9126 0656 0122 movs r2, #1 + 9127 0658 4FF40071 mov r1, #512 + 9128 065c 4046 mov r0, r8 + 9129 065e FFF7FEFF bl HAL_GPIO_WritePin + 9130 .LVL708: + 457:Src/main.c **** //* + 9131 .loc 1 457 9 view .LVU2969 + 9132 0662 3A46 mov r2, r7 + 9133 0664 4FF40071 mov r1, #512 + 9134 0668 4046 mov r0, r8 + 9135 066a FFF7FEFF bl HAL_GPIO_WritePin + 9136 .LVL709: + 459:Src/main.c **** OUT_trigger(trigger_counter); + 9137 .loc 1 459 9 view .LVU2970 + 459:Src/main.c **** OUT_trigger(trigger_counter); + 9138 .loc 1 459 41 is_stmt 0 view .LVU2971 + 9139 066e B4FBF6F3 udiv r3, r4, r6 + 9140 0672 06FB1343 mls r3, r6, r3, r4 + 9141 0676 9BB2 uxth r3, r3 + 459:Src/main.c **** OUT_trigger(trigger_counter); + 9142 .loc 1 459 12 view .LVU2972 + 9143 0678 1BB1 cbz r3, .L430 + 9144 .L399: + 463:Src/main.c **** //*/ + 9145 .loc 1 463 9 is_stmt 1 view .LVU2973 + 9146 067a 0134 adds r4, r4, #1 + 9147 .LVL710: + 463:Src/main.c **** //*/ + 9148 .loc 1 463 9 is_stmt 0 view .LVU2974 + 9149 067c A4B2 uxth r4, r4 + 9150 .LVL711: + 463:Src/main.c **** //*/ + 9151 .loc 1 463 9 view .LVU2975 + 9152 067e C4E7 b .L398 + 9153 .LVL712: + 9154 .L396: + ARM GAS /tmp/ccWQNJQt.s page 545 + + + 418:Src/main.c **** + 9155 .loc 1 418 8 is_stmt 1 view .LVU2976 + 418:Src/main.c **** + 9156 .loc 1 418 13 view .LVU2977 + 9157 0680 FEE7 b .L396 + 9158 .LVL713: + 9159 .L430: + 460:Src/main.c **** ++trigger_counter; + 9160 .loc 1 460 10 view .LVU2978 + 9161 0682 E8B2 uxtb r0, r5 + 9162 0684 FFF7FEFF bl OUT_trigger + 9163 .LVL714: + 461:Src/main.c **** } + 9164 .loc 1 461 10 view .LVU2979 + 9165 0688 0135 adds r5, r5, #1 + 9166 .LVL715: + 461:Src/main.c **** } + 9167 .loc 1 461 10 is_stmt 0 view .LVU2980 + 9168 068a ADB2 uxth r5, r5 + 9169 .LVL716: + 461:Src/main.c **** } + 9170 .loc 1 461 10 view .LVU2981 + 9171 068c F5E7 b .L399 + 9172 .L429: + 488:Src/main.c **** //TIM11 -> CR1 |= 1 << 3; //sets timer to one-pulse mode. So it will turn off at the next Upd + 9173 .loc 1 488 7 is_stmt 1 view .LVU2982 + 488:Src/main.c **** //TIM11 -> CR1 |= 1 << 3; //sets timer to one-pulse mode. So it will turn off at the next Upd + 9174 .loc 1 488 13 is_stmt 0 view .LVU2983 + 9175 068e 574A ldr r2, .L436+32 + 9176 0690 D368 ldr r3, [r2, #12] + 488:Src/main.c **** //TIM11 -> CR1 |= 1 << 3; //sets timer to one-pulse mode. So it will turn off at the next Upd + 9177 .loc 1 488 21 view .LVU2984 + 9178 0692 43F00103 orr r3, r3, #1 + 9179 0696 D360 str r3, [r2, #12] + 498:Src/main.c **** + 9180 .loc 1 498 7 is_stmt 1 view .LVU2985 + 9181 0698 FFF7FEFF bl Stop_TIM10 + 9182 .LVL717: + 500:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); + 9183 .loc 1 500 7 view .LVU2986 + 500:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); + 9184 .loc 1 500 32 is_stmt 0 view .LVU2987 + 9185 069c 4B4C ldr r4, .L436 + 9186 .LVL718: + 500:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); + 9187 .loc 1 500 32 view .LVU2988 + 9188 069e D4ED017A vldr.32 s15, [r4, #4] + 500:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_1, task.current_param); + 9189 .loc 1 500 26 view .LVU2989 + 9190 06a2 C4ED047A vstr.32 s15, [r4, #16] + 501:Src/main.c **** if (task.tau > 3) + 9191 .loc 1 501 7 is_stmt 1 view .LVU2990 + 9192 06a6 FCEEE77A vcvt.u32.f32 s15, s15 + 9193 06aa 17EE903A vmov r3, s15 @ int + 9194 06ae 99B2 uxth r1, r3 + 9195 06b0 0120 movs r0, #1 + 9196 06b2 FFF7FEFF bl Set_LTEC + ARM GAS /tmp/ccWQNJQt.s page 546 + + + 9197 .LVL719: + 502:Src/main.c **** { + 9198 .loc 1 502 7 view .LVU2991 + 502:Src/main.c **** { + 9199 .loc 1 502 15 is_stmt 0 view .LVU2992 + 9200 06b6 E38A ldrh r3, [r4, #22] + 502:Src/main.c **** { + 9201 .loc 1 502 10 view .LVU2993 + 9202 06b8 032B cmp r3, #3 + 9203 06ba 0CD9 bls .L401 + 504:Src/main.c **** htim10.Init.Period = 9999; + 9204 .loc 1 504 8 is_stmt 1 view .LVU2994 + 504:Src/main.c **** htim10.Init.Period = 9999; + 9205 .loc 1 504 34 is_stmt 0 view .LVU2995 + 9206 06bc 4A4A ldr r2, .L436+28 + 9207 06be D068 ldr r0, [r2, #12] + 504:Src/main.c **** htim10.Init.Period = 9999; + 9208 .loc 1 504 21 view .LVU2996 + 9209 06c0 4E49 ldr r1, .L436+48 + 9210 06c2 0860 str r0, [r1] + 505:Src/main.c **** TO10_counter = (task.tau - 1) * 100; + 9211 .loc 1 505 8 is_stmt 1 view .LVU2997 + 505:Src/main.c **** TO10_counter = (task.tau - 1) * 100; + 9212 .loc 1 505 27 is_stmt 0 view .LVU2998 + 9213 06c4 42F20F71 movw r1, #9999 + 9214 06c8 D160 str r1, [r2, #12] + 506:Src/main.c **** } + 9215 .loc 1 506 8 is_stmt 1 view .LVU2999 + 506:Src/main.c **** } + 9216 .loc 1 506 33 is_stmt 0 view .LVU3000 + 9217 06ca 013B subs r3, r3, #1 + 506:Src/main.c **** } + 9218 .loc 1 506 38 view .LVU3001 + 9219 06cc 6422 movs r2, #100 + 9220 06ce 02FB03F3 mul r3, r2, r3 + 506:Src/main.c **** } + 9221 .loc 1 506 21 view .LVU3002 + 9222 06d2 4B4A ldr r2, .L436+52 + 9223 06d4 1360 str r3, [r2] + 9224 .L401: + 508:Src/main.c **** break; + 9225 .loc 1 508 7 is_stmt 1 view .LVU3003 + 9226 06d6 4448 ldr r0, .L436+28 + 9227 06d8 FFF7FEFF bl HAL_TIM_Base_Start_IT + 9228 .LVL720: + 509:Src/main.c **** case TT_CHANGE_CURR_2: + 9229 .loc 1 509 6 view .LVU3004 + 9230 06dc C8E6 b .L394 + 9231 .LVL721: + 9232 .L393: + 513:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); + 9233 .loc 1 513 7 view .LVU3005 + 513:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); + 9234 .loc 1 513 38 is_stmt 0 view .LVU3006 + 9235 06de 3B4B ldr r3, .L436 + 9236 06e0 D3ED077A vldr.32 s15, [r3, #28] + 513:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_1); + ARM GAS /tmp/ccWQNJQt.s page 547 + + + 9237 .loc 1 513 7 view .LVU3007 + 9238 06e4 FCEEE77A vcvt.u32.f32 s15, s15 + 9239 06e8 17EE903A vmov r3, s15 @ int + 9240 06ec 99B2 uxth r1, r3 + 9241 06ee 0120 movs r0, #1 + 9242 06f0 FFF7FEFF bl Set_LTEC + 9243 .LVL722: + 514:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); + 9244 .loc 1 514 7 is_stmt 1 view .LVU3008 + 514:Src/main.c **** LD1_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_1); + 9245 .loc 1 514 14 is_stmt 0 view .LVU3009 + 9246 06f4 0320 movs r0, #3 + 9247 06f6 FFF7FEFF bl MPhD_T + 9248 .LVL723: + 515:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); + 9249 .loc 1 515 7 is_stmt 1 view .LVU3010 + 515:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); + 9250 .loc 1 515 32 is_stmt 0 view .LVU3011 + 9251 06fa 0320 movs r0, #3 + 9252 06fc FFF7FEFF bl MPhD_T + 9253 .LVL724: + 515:Src/main.c **** (void) MPhD_T(TT_CHANGE_TEMP_2); + 9254 .loc 1 515 30 discriminator 1 view .LVU3012 + 9255 0700 334C ldr r4, .L436+4 + 9256 0702 2080 strh r0, [r4] @ movhi + 516:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); + 9257 .loc 1 516 7 is_stmt 1 view .LVU3013 + 516:Src/main.c **** LD2_param.LD_CURR_TEMP = MPhD_T(TT_CHANGE_TEMP_2); + 9258 .loc 1 516 14 is_stmt 0 view .LVU3014 + 9259 0704 0420 movs r0, #4 + 9260 0706 FFF7FEFF bl MPhD_T + 9261 .LVL725: + 517:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); + 9262 .loc 1 517 7 is_stmt 1 view .LVU3015 + 517:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); + 9263 .loc 1 517 32 is_stmt 0 view .LVU3016 + 9264 070a 0420 movs r0, #4 + 9265 070c FFF7FEFF bl MPhD_T + 9266 .LVL726: + 517:Src/main.c **** temp16=PID_Controller_Temp(&LD1_curr_setup, &LD1_param, 1); + 9267 .loc 1 517 30 discriminator 1 view .LVU3017 + 9268 0710 304D ldr r5, .L436+8 + 9269 0712 2880 strh r0, [r5] @ movhi + 518:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 + 9270 .loc 1 518 7 is_stmt 1 view .LVU3018 + 518:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 + 9271 .loc 1 518 14 is_stmt 0 view .LVU3019 + 9272 0714 0122 movs r2, #1 + 9273 0716 2146 mov r1, r4 + 9274 0718 2F48 ldr r0, .L436+12 + 9275 071a FFF7FEFF bl PID_Controller_Temp + 9276 .LVL727: + 9277 071e 0146 mov r1, r0 + 518:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_1, temp16);//Drive Laser TEC 1 + 9278 .loc 1 518 13 discriminator 1 view .LVU3020 + 9279 0720 2E4C ldr r4, .L436+16 + 9280 0722 2080 strh r0, [r4] @ movhi + ARM GAS /tmp/ccWQNJQt.s page 548 + + + 519:Src/main.c **** temp16=PID_Controller_Temp(&LD2_curr_setup, &LD2_param, 2); + 9281 .loc 1 519 7 is_stmt 1 view .LVU3021 + 9282 0724 0320 movs r0, #3 + 9283 0726 FFF7FEFF bl Set_LTEC + 9284 .LVL728: + 520:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 + 9285 .loc 1 520 7 view .LVU3022 + 520:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 + 9286 .loc 1 520 14 is_stmt 0 view .LVU3023 + 9287 072a 0222 movs r2, #2 + 9288 072c 2946 mov r1, r5 + 9289 072e 2C48 ldr r0, .L436+20 + 9290 0730 FFF7FEFF bl PID_Controller_Temp + 9291 .LVL729: + 9292 0734 0146 mov r1, r0 + 520:Src/main.c **** Set_LTEC(TT_CHANGE_TEMP_2, temp16);//Drive Laser TEC 2 + 9293 .loc 1 520 13 discriminator 1 view .LVU3024 + 9294 0736 2080 strh r0, [r4] @ movhi + 521:Src/main.c **** + 9295 .loc 1 521 7 is_stmt 1 view .LVU3025 + 9296 0738 0420 movs r0, #4 + 9297 073a FFF7FEFF bl Set_LTEC + 9298 .LVL730: + 523:Src/main.c **** LD_blinker.state = 0; // 0 -- disabled (do nothing); 1 -- update LD current; 2 -- blinking, L + 9299 .loc 1 523 7 view .LVU3026 + 523:Src/main.c **** LD_blinker.state = 0; // 0 -- disabled (do nothing); 1 -- update LD current; 2 -- blinking, L + 9300 .loc 1 523 28 is_stmt 0 view .LVU3027 + 9301 073e 314B ldr r3, .L436+56 + 9302 0740 0222 movs r2, #2 + 9303 0742 1A70 strb r2, [r3] + 524:Src/main.c **** //LD_blinker.param = task.current_param; + 9304 .loc 1 524 7 is_stmt 1 view .LVU3028 + 524:Src/main.c **** //LD_blinker.param = task.current_param; + 9305 .loc 1 524 24 is_stmt 0 view .LVU3029 + 9306 0744 0022 movs r2, #0 + 9307 0746 9A72 strb r2, [r3, #10] + 526:Src/main.c **** LD_blinker.param = 1000; // LD2 current (in unspecified units) + 9308 .loc 1 526 7 is_stmt 1 view .LVU3030 + 526:Src/main.c **** LD_blinker.param = 1000; // LD2 current (in unspecified units) + 9309 .loc 1 526 24 is_stmt 0 view .LVU3031 + 9310 0748 1A81 strh r2, [r3, #8] @ movhi + 527:Src/main.c **** LD_blinker.signal_port = OUT_9_GPIO_Port; + 9311 .loc 1 527 7 is_stmt 1 view .LVU3032 + 527:Src/main.c **** LD_blinker.signal_port = OUT_9_GPIO_Port; + 9312 .loc 1 527 24 is_stmt 0 view .LVU3033 + 9313 074a 4FF47A72 mov r2, #1000 + 9314 074e 1A81 strh r2, [r3, #8] @ movhi + 528:Src/main.c **** LD_blinker.signal_pin = OUT_9_Pin; + 9315 .loc 1 528 7 is_stmt 1 view .LVU3034 + 528:Src/main.c **** LD_blinker.signal_pin = OUT_9_Pin; + 9316 .loc 1 528 30 is_stmt 0 view .LVU3035 + 9317 0750 2D4A ldr r2, .L436+60 + 9318 0752 5A60 str r2, [r3, #4] + 529:Src/main.c **** + 9319 .loc 1 529 7 is_stmt 1 view .LVU3036 + 529:Src/main.c **** + 9320 .loc 1 529 29 is_stmt 0 view .LVU3037 + ARM GAS /tmp/ccWQNJQt.s page 549 + + + 9321 0754 8022 movs r2, #128 + 9322 0756 5A80 strh r2, [r3, #2] @ movhi + 531:Src/main.c **** //When it is too low -- Desktop app crashes (there is not so much compute sources on MCU + 9323 .loc 1 531 7 is_stmt 1 view .LVU3038 + 531:Src/main.c **** //When it is too low -- Desktop app crashes (there is not so much compute sources on MCU + 9324 .loc 1 531 17 is_stmt 0 view .LVU3039 + 9325 0758 2C4B ldr r3, .L436+64 + 9326 075a 42F21072 movw r2, #10000 + 9327 075e DA62 str r2, [r3, #44] + 533:Src/main.c **** if (st != HAL_OK) + 9328 .loc 1 533 7 is_stmt 1 view .LVU3040 + 533:Src/main.c **** if (st != HAL_OK) + 9329 .loc 1 533 12 is_stmt 0 view .LVU3041 + 9330 0760 2B48 ldr r0, .L436+68 + 9331 0762 FFF7FEFF bl HAL_TIM_Base_Start_IT + 9332 .LVL731: + 534:Src/main.c **** while(1); + 9333 .loc 1 534 7 is_stmt 1 view .LVU3042 + 534:Src/main.c **** while(1); + 9334 .loc 1 534 10 is_stmt 0 view .LVU3043 + 9335 0766 78BB cbnz r0, .L403 + 539:Src/main.c **** uint32_t i = 10000; while (--i){} + 9336 .loc 1 539 7 is_stmt 1 view .LVU3044 + 9337 0768 0122 movs r2, #1 + 9338 076a 8021 movs r1, #128 + 9339 076c 1D48 ldr r0, .L436+24 + 9340 .LVL732: + 539:Src/main.c **** uint32_t i = 10000; while (--i){} + 9341 .loc 1 539 7 is_stmt 0 view .LVU3045 + 9342 076e FFF7FEFF bl HAL_GPIO_WritePin + 9343 .LVL733: + 540:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); + 9344 .loc 1 540 7 is_stmt 1 view .LVU3046 + 540:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); + 9345 .loc 1 540 27 view .LVU3047 + 540:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); + 9346 .loc 1 540 16 is_stmt 0 view .LVU3048 + 9347 0772 42F21073 movw r3, #10000 + 9348 .LVL734: + 9349 .L404: + 540:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); + 9350 .loc 1 540 39 is_stmt 1 discriminator 2 view .LVU3049 + 540:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); + 9351 .loc 1 540 34 discriminator 2 view .LVU3050 + 540:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); + 9352 .loc 1 540 34 is_stmt 0 discriminator 2 view .LVU3051 + 9353 0776 013B subs r3, r3, #1 + 9354 .LVL735: + 540:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_RESET); + 9355 .loc 1 540 34 discriminator 2 view .LVU3052 + 9356 0778 FDD1 bne .L404 + 541:Src/main.c **** LD_blinker.state = 2; + 9357 .loc 1 541 7 is_stmt 1 view .LVU3053 + 9358 077a 0022 movs r2, #0 + 9359 077c 8021 movs r1, #128 + 9360 077e 1948 ldr r0, .L436+24 + 9361 0780 FFF7FEFF bl HAL_GPIO_WritePin + ARM GAS /tmp/ccWQNJQt.s page 550 + + + 9362 .LVL736: + 542:Src/main.c **** + 9363 .loc 1 542 7 view .LVU3054 + 542:Src/main.c **** + 9364 .loc 1 542 24 is_stmt 0 view .LVU3055 + 9365 0784 1F4B ldr r3, .L436+56 + 9366 0786 0222 movs r2, #2 + 9367 0788 9A72 strb r2, [r3, #10] + 544:Src/main.c **** if (st != HAL_OK) + 9368 .loc 1 544 7 is_stmt 1 view .LVU3056 + 544:Src/main.c **** if (st != HAL_OK) + 9369 .loc 1 544 12 is_stmt 0 view .LVU3057 + 9370 078a 1748 ldr r0, .L436+28 + 9371 078c FFF7FEFF bl HAL_TIM_Base_Start_IT + 9372 .LVL737: + 545:Src/main.c **** while(1); + 9373 .loc 1 545 7 is_stmt 1 view .LVU3058 + 545:Src/main.c **** while(1); + 9374 .loc 1 545 10 is_stmt 0 view .LVU3059 + 9375 0790 D8B9 cbnz r0, .L406 + 9376 .L407: + 547:Src/main.c **** { + 9377 .loc 1 547 33 is_stmt 1 view .LVU3060 + 547:Src/main.c **** { + 9378 .loc 1 547 18 is_stmt 0 view .LVU3061 + 9379 0792 0E4B ldr r3, .L436 + 9380 0794 D3ED047A vldr.32 s15, [r3, #16] + 547:Src/main.c **** { + 9381 .loc 1 547 39 view .LVU3062 + 9382 0798 93ED027A vldr.32 s14, [r3, #8] + 547:Src/main.c **** { + 9383 .loc 1 547 33 view .LVU3063 + 9384 079c F4EEC77A vcmpe.f32 s15, s14 + 9385 07a0 F1EE10FA vmrs APSR_nzcv, FPSCR + 9386 07a4 3CD5 bpl .L431 + 549:Src/main.c **** { + 9387 .loc 1 549 8 is_stmt 1 view .LVU3064 + 549:Src/main.c **** { + 9388 .loc 1 549 12 is_stmt 0 view .LVU3065 + 9389 07a6 134B ldr r3, .L436+40 + 9390 07a8 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 549:Src/main.c **** { + 9391 .loc 1 549 11 view .LVU3066 + 9392 07aa 002B cmp r3, #0 + 9393 07ac F1D0 beq .L407 + 554:Src/main.c **** TO10 = 0; + 9394 .loc 1 554 9 is_stmt 1 view .LVU3067 + 554:Src/main.c **** TO10 = 0; + 9395 .loc 1 554 35 is_stmt 0 view .LVU3068 + 9396 07ae 074B ldr r3, .L436 + 9397 07b0 93ED037A vldr.32 s14, [r3, #12] + 554:Src/main.c **** TO10 = 0; + 9398 .loc 1 554 28 view .LVU3069 + 9399 07b4 77EE277A vadd.f32 s15, s14, s15 + 9400 07b8 C3ED047A vstr.32 s15, [r3, #16] + 555:Src/main.c **** TIM10_coflag = 0; + 9401 .loc 1 555 9 is_stmt 1 view .LVU3070 + ARM GAS /tmp/ccWQNJQt.s page 551 + + + 555:Src/main.c **** TIM10_coflag = 0; + 9402 .loc 1 555 14 is_stmt 0 view .LVU3071 + 9403 07bc 0023 movs r3, #0 + 9404 07be 0E4A ldr r2, .L436+44 + 9405 07c0 1360 str r3, [r2] + 556:Src/main.c **** + 9406 .loc 1 556 9 is_stmt 1 view .LVU3072 + 556:Src/main.c **** + 9407 .loc 1 556 22 is_stmt 0 view .LVU3073 + 9408 07c2 0C4A ldr r2, .L436+40 + 9409 07c4 1370 strb r3, [r2] + 9410 07c6 E4E7 b .L407 + 9411 .LVL738: + 9412 .L403: + 535:Src/main.c **** // */ + 9413 .loc 1 535 8 is_stmt 1 view .LVU3074 + 535:Src/main.c **** // */ + 9414 .loc 1 535 13 view .LVU3075 + 9415 07c8 FEE7 b .L403 + 9416 .LVL739: + 9417 .L406: + 546:Src/main.c **** while (task.current_param < task.max_param) + 9418 .loc 1 546 8 view .LVU3076 + 546:Src/main.c **** while (task.current_param < task.max_param) + 9419 .loc 1 546 13 view .LVU3077 + 9420 07ca FEE7 b .L406 + 9421 .L437: + 9422 .align 2 + 9423 .L436: + 9424 07cc 00000000 .word task + 9425 07d0 00000000 .word LD1_param + 9426 07d4 00000000 .word LD2_param + 9427 07d8 00000000 .word LD1_curr_setup + 9428 07dc 00000000 .word temp16 + 9429 07e0 00000000 .word LD2_curr_setup + 9430 07e4 000C0240 .word 1073875968 + 9431 07e8 00000000 .word htim10 + 9432 07ec 00480140 .word 1073825792 + 9433 07f0 00080040 .word 1073743872 + 9434 07f4 00000000 .word TIM10_coflag + 9435 07f8 00000000 .word TO10 + 9436 07fc 00000000 .word TIM10_period + 9437 0800 00000000 .word TO10_counter + 9438 0804 00000000 .word LD_blinker + 9439 0808 00040240 .word 1073873920 + 9440 080c 00040140 .word 1073808384 + 9441 0810 00000000 .word htim8 + 9442 0814 00000000 .word htim11 + 9443 0818 00000000 .word htim4 + 9444 081c 00180240 .word 1073879040 + 9445 .L431: + 561:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); + 9446 .loc 1 561 7 view .LVU3078 + 9447 0820 6C48 ldr r0, .L438 + 9448 .LVL740: + 561:Src/main.c **** HAL_GPIO_WritePin(GPIOD, GPIO_PIN_7, GPIO_PIN_SET); + 9449 .loc 1 561 7 is_stmt 0 view .LVU3079 + ARM GAS /tmp/ccWQNJQt.s page 552 + + + 9450 0822 FFF7FEFF bl HAL_TIM_Base_Stop + 9451 .LVL741: + 562:Src/main.c **** + 9452 .loc 1 562 7 is_stmt 1 view .LVU3080 + 9453 0826 6C4C ldr r4, .L438+4 + 9454 0828 0122 movs r2, #1 + 9455 082a 8021 movs r1, #128 + 9456 082c 2046 mov r0, r4 + 9457 082e FFF7FEFF bl HAL_GPIO_WritePin + 9458 .LVL742: + 564:Src/main.c **** + 9459 .loc 1 564 7 view .LVU3081 + 9460 0832 0022 movs r2, #0 + 9461 0834 8021 movs r1, #128 + 9462 0836 2046 mov r0, r4 + 9463 0838 FFF7FEFF bl HAL_GPIO_WritePin + 9464 .LVL743: + 566:Src/main.c **** TIM8->CNT = 0; + 9465 .loc 1 566 7 view .LVU3082 + 9466 083c 6748 ldr r0, .L438+8 + 9467 083e FFF7FEFF bl HAL_TIM_Base_Stop_IT + 9468 .LVL744: + 567:Src/main.c **** + 9469 .loc 1 567 7 view .LVU3083 + 567:Src/main.c **** + 9470 .loc 1 567 17 is_stmt 0 view .LVU3084 + 9471 0842 674B ldr r3, .L438+12 + 9472 0844 0022 movs r2, #0 + 9473 0846 5A62 str r2, [r3, #36] + 569:Src/main.c **** task.current_param = task.min_param; + 9474 .loc 1 569 7 is_stmt 1 view .LVU3085 + 9475 0848 FFF7FEFF bl Stop_TIM10 + 9476 .LVL745: + 570:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); + 9477 .loc 1 570 7 view .LVU3086 + 570:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); + 9478 .loc 1 570 32 is_stmt 0 view .LVU3087 + 9479 084c 654C ldr r4, .L438+16 + 9480 084e D4ED017A vldr.32 s15, [r4, #4] + 570:Src/main.c **** Set_LTEC(TT_CHANGE_CURR_2, task.current_param); + 9481 .loc 1 570 26 view .LVU3088 + 9482 0852 C4ED047A vstr.32 s15, [r4, #16] + 571:Src/main.c **** if (task.tau > 3) + 9483 .loc 1 571 7 is_stmt 1 view .LVU3089 + 9484 0856 FCEEE77A vcvt.u32.f32 s15, s15 + 9485 085a 17EE903A vmov r3, s15 @ int + 9486 085e 99B2 uxth r1, r3 + 9487 0860 0220 movs r0, #2 + 9488 0862 FFF7FEFF bl Set_LTEC + 9489 .LVL746: + 572:Src/main.c **** { + 9490 .loc 1 572 7 view .LVU3090 + 572:Src/main.c **** { + 9491 .loc 1 572 15 is_stmt 0 view .LVU3091 + 9492 0866 E38A ldrh r3, [r4, #22] + 572:Src/main.c **** { + 9493 .loc 1 572 10 view .LVU3092 + ARM GAS /tmp/ccWQNJQt.s page 553 + + + 9494 0868 032B cmp r3, #3 + 9495 086a 0CD9 bls .L409 + 574:Src/main.c **** htim10.Init.Period = 9999; + 9496 .loc 1 574 8 is_stmt 1 view .LVU3093 + 574:Src/main.c **** htim10.Init.Period = 9999; + 9497 .loc 1 574 34 is_stmt 0 view .LVU3094 + 9498 086c 594A ldr r2, .L438 + 9499 086e D068 ldr r0, [r2, #12] + 574:Src/main.c **** htim10.Init.Period = 9999; + 9500 .loc 1 574 21 view .LVU3095 + 9501 0870 5D49 ldr r1, .L438+20 + 9502 0872 0860 str r0, [r1] + 575:Src/main.c **** TO10_counter = (task.tau - 1) * 100; + 9503 .loc 1 575 8 is_stmt 1 view .LVU3096 + 575:Src/main.c **** TO10_counter = (task.tau - 1) * 100; + 9504 .loc 1 575 27 is_stmt 0 view .LVU3097 + 9505 0874 42F20F71 movw r1, #9999 + 9506 0878 D160 str r1, [r2, #12] + 576:Src/main.c **** } + 9507 .loc 1 576 8 is_stmt 1 view .LVU3098 + 576:Src/main.c **** } + 9508 .loc 1 576 33 is_stmt 0 view .LVU3099 + 9509 087a 013B subs r3, r3, #1 + 576:Src/main.c **** } + 9510 .loc 1 576 38 view .LVU3100 + 9511 087c 6422 movs r2, #100 + 9512 087e 02FB03F3 mul r3, r2, r3 + 576:Src/main.c **** } + 9513 .loc 1 576 21 view .LVU3101 + 9514 0882 5A4A ldr r2, .L438+24 + 9515 0884 1360 str r3, [r2] + 9516 .L409: + 578:Src/main.c **** + 9517 .loc 1 578 7 is_stmt 1 view .LVU3102 + 9518 0886 5348 ldr r0, .L438 + 9519 0888 FFF7FEFF bl HAL_TIM_Base_Start_IT + 9520 .LVL747: + 626:Src/main.c **** case TT_CHANGE_TEMP_1: + 9521 .loc 1 626 6 view .LVU3103 + 9522 088c F0E5 b .L394 + 9523 .LVL748: + 9524 .L428: + 626:Src/main.c **** case TT_CHANGE_TEMP_1: + 9525 .loc 1 626 6 is_stmt 0 view .LVU3104 + 9526 .LBE577: + 637:Src/main.c **** + 9527 .loc 1 637 7 is_stmt 1 view .LVU3105 + 637:Src/main.c **** + 9528 .loc 1 637 18 is_stmt 0 view .LVU3106 + 9529 088e 584A ldr r2, .L438+28 + 9530 0890 1360 str r3, [r2] + 639:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 + 9531 .loc 1 639 7 is_stmt 1 view .LVU3107 + 639:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 + 9532 .loc 1 639 25 is_stmt 0 view .LVU3108 + 9533 0892 0120 movs r0, #1 + 9534 0894 FFF7FEFF bl MPhD_T + ARM GAS /tmp/ccWQNJQt.s page 554 + + + 9535 .LVL749: + 639:Src/main.c **** LD1_param.POWER = MPhD_T(1);//Get Data from monitor photodiode of LD1 + 9536 .loc 1 639 23 discriminator 1 view .LVU3109 + 9537 0898 564E ldr r6, .L438+32 + 9538 089a 3081 strh r0, [r6, #8] @ movhi + 640:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 + 9539 .loc 1 640 7 is_stmt 1 view .LVU3110 + 640:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 + 9540 .loc 1 640 25 is_stmt 0 view .LVU3111 + 9541 089c 0120 movs r0, #1 + 9542 089e FFF7FEFF bl MPhD_T + 9543 .LVL750: + 640:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 + 9544 .loc 1 640 23 discriminator 1 view .LVU3112 + 9545 08a2 3081 strh r0, [r6, #8] @ movhi + 641:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 + 9546 .loc 1 641 7 is_stmt 1 view .LVU3113 + 641:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 + 9547 .loc 1 641 25 is_stmt 0 view .LVU3114 + 9548 08a4 0220 movs r0, #2 + 9549 08a6 FFF7FEFF bl MPhD_T + 9550 .LVL751: + 641:Src/main.c **** LD2_param.POWER = MPhD_T(2);//Get Data from monitor photodiode of LD2 + 9551 .loc 1 641 23 discriminator 1 view .LVU3115 + 9552 08aa 534F ldr r7, .L438+36 + 9553 08ac 3881 strh r0, [r7, #8] @ movhi + 642:Src/main.c **** + 9554 .loc 1 642 7 is_stmt 1 view .LVU3116 + 642:Src/main.c **** + 9555 .loc 1 642 25 is_stmt 0 view .LVU3117 + 9556 08ae 0220 movs r0, #2 + 9557 08b0 FFF7FEFF bl MPhD_T + 9558 .LVL752: + 642:Src/main.c **** + 9559 .loc 1 642 23 discriminator 1 view .LVU3118 + 9560 08b4 3881 strh r0, [r7, #8] @ movhi + 644:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data + 9561 .loc 1 644 7 is_stmt 1 view .LVU3119 + 644:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data + 9562 .loc 1 644 31 is_stmt 0 view .LVU3120 + 9563 08b6 3389 ldrh r3, [r6, #8] + 644:Src/main.c **** Long_Data[2] = LD2_param.POWER;//Translate Data from monitor photodiode of LD2 to Long_Data + 9564 .loc 1 644 20 view .LVU3121 + 9565 08b8 504C ldr r4, .L438+40 + 9566 08ba 6380 strh r3, [r4, #2] @ movhi + 645:Src/main.c **** + 9567 .loc 1 645 7 is_stmt 1 view .LVU3122 + 645:Src/main.c **** + 9568 .loc 1 645 20 is_stmt 0 view .LVU3123 + 9569 08bc A080 strh r0, [r4, #4] @ movhi + 649:Src/main.c **** temp16 = Get_ADC(1); + 9570 .loc 1 649 7 is_stmt 1 view .LVU3124 + 649:Src/main.c **** temp16 = Get_ADC(1); + 9571 .loc 1 649 16 is_stmt 0 view .LVU3125 + 9572 08be 0020 movs r0, #0 + 9573 08c0 FFF7FEFF bl Get_ADC + 9574 .LVL753: + ARM GAS /tmp/ccWQNJQt.s page 555 + + + 649:Src/main.c **** temp16 = Get_ADC(1); + 9575 .loc 1 649 14 discriminator 1 view .LVU3126 + 9576 08c4 4E4D ldr r5, .L438+44 + 9577 08c6 2880 strh r0, [r5] @ movhi + 650:Src/main.c **** Long_Data[7] = temp16; + 9578 .loc 1 650 7 is_stmt 1 view .LVU3127 + 650:Src/main.c **** Long_Data[7] = temp16; + 9579 .loc 1 650 16 is_stmt 0 view .LVU3128 + 9580 08c8 0120 movs r0, #1 + 9581 08ca FFF7FEFF bl Get_ADC + 9582 .LVL754: + 650:Src/main.c **** Long_Data[7] = temp16; + 9583 .loc 1 650 14 discriminator 1 view .LVU3129 + 9584 08ce 2880 strh r0, [r5] @ movhi + 651:Src/main.c **** + 9585 .loc 1 651 7 is_stmt 1 view .LVU3130 + 651:Src/main.c **** + 9586 .loc 1 651 20 is_stmt 0 view .LVU3131 + 9587 08d0 E081 strh r0, [r4, #14] @ movhi + 654:Src/main.c **** Long_Data[8] = temp16; + 9588 .loc 1 654 7 is_stmt 1 view .LVU3132 + 654:Src/main.c **** Long_Data[8] = temp16; + 9589 .loc 1 654 16 is_stmt 0 view .LVU3133 + 9590 08d2 0120 movs r0, #1 + 9591 08d4 FFF7FEFF bl Get_ADC + 9592 .LVL755: + 654:Src/main.c **** Long_Data[8] = temp16; + 9593 .loc 1 654 14 discriminator 1 view .LVU3134 + 9594 08d8 2880 strh r0, [r5] @ movhi + 655:Src/main.c **** + 9595 .loc 1 655 7 is_stmt 1 view .LVU3135 + 655:Src/main.c **** + 9596 .loc 1 655 20 is_stmt 0 view .LVU3136 + 9597 08da 2082 strh r0, [r4, #16] @ movhi + 658:Src/main.c **** Long_Data[9] = temp16; + 9598 .loc 1 658 7 is_stmt 1 view .LVU3137 + 658:Src/main.c **** Long_Data[9] = temp16; + 9599 .loc 1 658 16 is_stmt 0 view .LVU3138 + 9600 08dc 0120 movs r0, #1 + 9601 08de FFF7FEFF bl Get_ADC + 9602 .LVL756: + 658:Src/main.c **** Long_Data[9] = temp16; + 9603 .loc 1 658 14 discriminator 1 view .LVU3139 + 9604 08e2 2880 strh r0, [r5] @ movhi + 659:Src/main.c **** + 9605 .loc 1 659 7 is_stmt 1 view .LVU3140 + 659:Src/main.c **** + 9606 .loc 1 659 20 is_stmt 0 view .LVU3141 + 9607 08e4 6082 strh r0, [r4, #18] @ movhi + 662:Src/main.c **** Long_Data[10] = temp16; + 9608 .loc 1 662 7 is_stmt 1 view .LVU3142 + 662:Src/main.c **** Long_Data[10] = temp16; + 9609 .loc 1 662 16 is_stmt 0 view .LVU3143 + 9610 08e6 0120 movs r0, #1 + 9611 08e8 FFF7FEFF bl Get_ADC + 9612 .LVL757: + 662:Src/main.c **** Long_Data[10] = temp16; + ARM GAS /tmp/ccWQNJQt.s page 556 + + + 9613 .loc 1 662 14 discriminator 1 view .LVU3144 + 9614 08ec 2880 strh r0, [r5] @ movhi + 663:Src/main.c **** + 9615 .loc 1 663 7 is_stmt 1 view .LVU3145 + 663:Src/main.c **** + 9616 .loc 1 663 21 is_stmt 0 view .LVU3146 + 9617 08ee A082 strh r0, [r4, #20] @ movhi + 666:Src/main.c **** Long_Data[11] = temp16; + 9618 .loc 1 666 7 is_stmt 1 view .LVU3147 + 666:Src/main.c **** Long_Data[11] = temp16; + 9619 .loc 1 666 16 is_stmt 0 view .LVU3148 + 9620 08f0 0120 movs r0, #1 + 9621 08f2 FFF7FEFF bl Get_ADC + 9622 .LVL758: + 666:Src/main.c **** Long_Data[11] = temp16; + 9623 .loc 1 666 14 discriminator 1 view .LVU3149 + 9624 08f6 2880 strh r0, [r5] @ movhi + 667:Src/main.c **** temp16 = Get_ADC(2); + 9625 .loc 1 667 7 is_stmt 1 view .LVU3150 + 667:Src/main.c **** temp16 = Get_ADC(2); + 9626 .loc 1 667 21 is_stmt 0 view .LVU3151 + 9627 08f8 E082 strh r0, [r4, #22] @ movhi + 668:Src/main.c **** + 9628 .loc 1 668 7 is_stmt 1 view .LVU3152 + 668:Src/main.c **** + 9629 .loc 1 668 16 is_stmt 0 view .LVU3153 + 9630 08fa 0220 movs r0, #2 + 9631 08fc FFF7FEFF bl Get_ADC + 9632 .LVL759: + 668:Src/main.c **** + 9633 .loc 1 668 14 discriminator 1 view .LVU3154 + 9634 0900 2880 strh r0, [r5] @ movhi + 671:Src/main.c **** temp16 = Get_ADC(4); + 9635 .loc 1 671 7 is_stmt 1 view .LVU3155 + 671:Src/main.c **** temp16 = Get_ADC(4); + 9636 .loc 1 671 16 is_stmt 0 view .LVU3156 + 9637 0902 0320 movs r0, #3 + 9638 0904 FFF7FEFF bl Get_ADC + 9639 .LVL760: + 671:Src/main.c **** temp16 = Get_ADC(4); + 9640 .loc 1 671 14 discriminator 1 view .LVU3157 + 9641 0908 2880 strh r0, [r5] @ movhi + 672:Src/main.c **** Long_Data[12] = temp16; + 9642 .loc 1 672 7 is_stmt 1 view .LVU3158 + 672:Src/main.c **** Long_Data[12] = temp16; + 9643 .loc 1 672 16 is_stmt 0 view .LVU3159 + 9644 090a 0420 movs r0, #4 + 9645 090c FFF7FEFF bl Get_ADC + 9646 .LVL761: + 672:Src/main.c **** Long_Data[12] = temp16; + 9647 .loc 1 672 14 discriminator 1 view .LVU3160 + 9648 0910 2880 strh r0, [r5] @ movhi + 673:Src/main.c **** temp16 = Get_ADC(5); + 9649 .loc 1 673 7 is_stmt 1 view .LVU3161 + 673:Src/main.c **** temp16 = Get_ADC(5); + 9650 .loc 1 673 21 is_stmt 0 view .LVU3162 + 9651 0912 2083 strh r0, [r4, #24] @ movhi + ARM GAS /tmp/ccWQNJQt.s page 557 + + + 674:Src/main.c **** + 9652 .loc 1 674 7 is_stmt 1 view .LVU3163 + 674:Src/main.c **** + 9653 .loc 1 674 16 is_stmt 0 view .LVU3164 + 9654 0914 0520 movs r0, #5 + 9655 0916 FFF7FEFF bl Get_ADC + 9656 .LVL762: + 674:Src/main.c **** + 9657 .loc 1 674 14 discriminator 1 view .LVU3165 + 9658 091a 2880 strh r0, [r5] @ movhi + 677:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; + 9659 .loc 1 677 7 is_stmt 1 view .LVU3166 + 677:Src/main.c **** Long_Data[3] = (TO6_stop)&0xffff; + 9660 .loc 1 677 16 is_stmt 0 view .LVU3167 + 9661 091c 394B ldr r3, .L438+48 + 9662 091e 1B68 ldr r3, [r3] + 9663 0920 394A ldr r2, .L438+52 + 9664 0922 1360 str r3, [r2] + 678:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; + 9665 .loc 1 678 7 is_stmt 1 view .LVU3168 + 678:Src/main.c **** Long_Data[4] = (TO6_stop>>16)&0xffff; + 9666 .loc 1 678 20 is_stmt 0 view .LVU3169 + 9667 0924 E380 strh r3, [r4, #6] @ movhi + 679:Src/main.c **** + 9668 .loc 1 679 7 is_stmt 1 view .LVU3170 + 679:Src/main.c **** + 9669 .loc 1 679 31 is_stmt 0 view .LVU3171 + 9670 0926 1B0C lsrs r3, r3, #16 + 679:Src/main.c **** + 9671 .loc 1 679 20 view .LVU3172 + 9672 0928 2381 strh r3, [r4, #8] @ movhi + 682:Src/main.c **** + 9673 .loc 1 682 7 is_stmt 1 view .LVU3173 + 682:Src/main.c **** + 9674 .loc 1 682 31 is_stmt 0 view .LVU3174 + 9675 092a 3388 ldrh r3, [r6] + 682:Src/main.c **** + 9676 .loc 1 682 20 view .LVU3175 + 9677 092c 6381 strh r3, [r4, #10] @ movhi + 685:Src/main.c **** } + 9678 .loc 1 685 7 is_stmt 1 view .LVU3176 + 685:Src/main.c **** } + 9679 .loc 1 685 31 is_stmt 0 view .LVU3177 + 9680 092e 3B88 ldrh r3, [r7] + 685:Src/main.c **** } + 9681 .loc 1 685 20 view .LVU3178 + 9682 0930 A381 strh r3, [r4, #12] @ movhi + 9683 0932 A4E5 b .L411 + 9684 .L413: + 713:Src/main.c **** Long_Data[DL_16-1] = CS_result; + 9685 .loc 1 713 5 is_stmt 1 view .LVU3179 + 713:Src/main.c **** Long_Data[DL_16-1] = CS_result; + 9686 .loc 1 713 17 is_stmt 0 view .LVU3180 + 9687 0934 354C ldr r4, .L438+56 + 9688 0936 0D21 movs r1, #13 + 9689 0938 2046 mov r0, r4 + 9690 093a FFF7FEFF bl CalculateChecksum + ARM GAS /tmp/ccWQNJQt.s page 558 + + + 9691 .LVL763: + 713:Src/main.c **** Long_Data[DL_16-1] = CS_result; + 9692 .loc 1 713 15 discriminator 1 view .LVU3181 + 9693 093e 344B ldr r3, .L438+60 + 9694 0940 1880 strh r0, [r3] @ movhi + 714:Src/main.c **** + 9695 .loc 1 714 5 is_stmt 1 view .LVU3182 + 714:Src/main.c **** + 9696 .loc 1 714 24 is_stmt 0 view .LVU3183 + 9697 0942 6083 strh r0, [r4, #26] @ movhi + 716:Src/main.c **** { + 9698 .loc 1 716 5 is_stmt 1 view .LVU3184 + 9699 .LBB578: + 716:Src/main.c **** { + 9700 .loc 1 716 10 view .LVU3185 + 9701 .LVL764: + 716:Src/main.c **** { + 9702 .loc 1 716 19 is_stmt 0 view .LVU3186 + 9703 0944 0023 movs r3, #0 + 716:Src/main.c **** { + 9704 .loc 1 716 5 view .LVU3187 + 9705 0946 0BE0 b .L416 + 9706 .LVL765: + 9707 .L417: + 718:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; + 9708 .loc 1 718 6 is_stmt 1 view .LVU3188 + 718:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; + 9709 .loc 1 718 33 is_stmt 0 view .LVU3189 + 9710 0948 2C4A ldr r2, .L438+40 + 9711 094a 32F81320 ldrh r2, [r2, r3, lsl #1] + 718:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; + 9712 .loc 1 718 17 view .LVU3190 + 9713 094e 5900 lsls r1, r3, #1 + 718:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; + 9714 .loc 1 718 21 view .LVU3191 + 9715 0950 3048 ldr r0, .L438+64 + 9716 0952 00F81320 strb r2, [r0, r3, lsl #1] + 719:Src/main.c **** } + 9717 .loc 1 719 6 is_stmt 1 view .LVU3192 + 719:Src/main.c **** } + 9718 .loc 1 719 19 is_stmt 0 view .LVU3193 + 9719 0956 0131 adds r1, r1, #1 + 719:Src/main.c **** } + 9720 .loc 1 719 23 view .LVU3194 + 9721 0958 120A lsrs r2, r2, #8 + 9722 095a 4254 strb r2, [r0, r1] + 716:Src/main.c **** { + 9723 .loc 1 716 38 is_stmt 1 discriminator 3 view .LVU3195 + 9724 095c 0133 adds r3, r3, #1 + 9725 .LVL766: + 716:Src/main.c **** { + 9726 .loc 1 716 38 is_stmt 0 discriminator 3 view .LVU3196 + 9727 095e 9BB2 uxth r3, r3 + 9728 .LVL767: + 9729 .L416: + 716:Src/main.c **** { + 9730 .loc 1 716 28 is_stmt 1 discriminator 1 view .LVU3197 + ARM GAS /tmp/ccWQNJQt.s page 559 + + + 9731 0960 0E2B cmp r3, #14 + 9732 0962 F1D9 bls .L417 + 9733 .LBE578: + 726:Src/main.c **** UART_transmission_request = NO_MESS; + 9734 .loc 1 726 5 view .LVU3198 + 9735 0964 1E20 movs r0, #30 + 9736 0966 FFF7FEFF bl USART_TX_DMA + 9737 .LVL768: + 727:Src/main.c **** break; + 9738 .loc 1 727 5 view .LVU3199 + 727:Src/main.c **** break; + 9739 .loc 1 727 31 is_stmt 0 view .LVU3200 + 9740 096a 2B4B ldr r3, .L438+68 + 9741 096c 0022 movs r2, #0 + 9742 096e 1A70 strb r2, [r3] + 728:Src/main.c **** case MESS_03://Transmith saved packet + 9743 .loc 1 728 4 is_stmt 1 view .LVU3201 + 9744 0970 FFF7D3BB b .L415 + 9745 .LVL769: + 9746 .L418: + 9747 .LBB579: + 732:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; + 9748 .loc 1 732 6 view .LVU3202 + 732:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; + 9749 .loc 1 732 33 is_stmt 0 view .LVU3203 + 9750 0974 214A ldr r2, .L438+40 + 9751 0976 32F81320 ldrh r2, [r2, r3, lsl #1] + 732:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; + 9752 .loc 1 732 17 view .LVU3204 + 9753 097a 5900 lsls r1, r3, #1 + 732:Src/main.c **** UART_DATA[i*2+1] = (Long_Data[i]>>8)&0xff; + 9754 .loc 1 732 21 view .LVU3205 + 9755 097c 2548 ldr r0, .L438+64 + 9756 097e 00F81320 strb r2, [r0, r3, lsl #1] + 733:Src/main.c **** } + 9757 .loc 1 733 6 is_stmt 1 view .LVU3206 + 733:Src/main.c **** } + 9758 .loc 1 733 19 is_stmt 0 view .LVU3207 + 9759 0982 0131 adds r1, r1, #1 + 733:Src/main.c **** } + 9760 .loc 1 733 23 view .LVU3208 + 9761 0984 120A lsrs r2, r2, #8 + 9762 0986 4254 strb r2, [r0, r1] + 730:Src/main.c **** { + 9763 .loc 1 730 38 is_stmt 1 discriminator 3 view .LVU3209 + 9764 0988 0133 adds r3, r3, #1 + 9765 .LVL770: + 730:Src/main.c **** { + 9766 .loc 1 730 38 is_stmt 0 discriminator 3 view .LVU3210 + 9767 098a 9BB2 uxth r3, r3 + 9768 .LVL771: + 9769 .L414: + 730:Src/main.c **** { + 9770 .loc 1 730 28 is_stmt 1 discriminator 1 view .LVU3211 + 9771 098c 0E2B cmp r3, #14 + 9772 098e F1D9 bls .L418 + 9773 .LBE579: + ARM GAS /tmp/ccWQNJQt.s page 560 + + + 739:Src/main.c **** UART_transmission_request = NO_MESS; + 9774 .loc 1 739 5 view .LVU3212 + 9775 0990 1E20 movs r0, #30 + 9776 0992 FFF7FEFF bl USART_TX_DMA + 9777 .LVL772: + 740:Src/main.c **** break; + 9778 .loc 1 740 5 view .LVU3213 + 740:Src/main.c **** break; + 9779 .loc 1 740 31 is_stmt 0 view .LVU3214 + 9780 0996 204B ldr r3, .L438+68 + 9781 0998 0022 movs r2, #0 + 9782 099a 1A70 strb r2, [r3] + 741:Src/main.c **** } + 9783 .loc 1 741 4 is_stmt 1 view .LVU3215 + 9784 099c FFF7BDBB b .L415 + 9785 .LVL773: + 9786 .L420: + 701:Src/main.c **** { + 9787 .loc 1 701 3 is_stmt 0 view .LVU3216 + 9788 09a0 0023 movs r3, #0 + 9789 09a2 F3E7 b .L414 + 9790 .L423: + 743:Src/main.c **** { + 9791 .loc 1 743 28 discriminator 1 view .LVU3217 + 9792 09a4 174B ldr r3, .L438+48 + 9793 09a6 1B68 ldr r3, [r3] + 9794 09a8 1C4A ldr r2, .L438+72 + 9795 09aa 1268 ldr r2, [r2] + 9796 09ac 9B1A subs r3, r3, r2 + 743:Src/main.c **** { + 9797 .loc 1 743 21 discriminator 1 view .LVU3218 + 9798 09ae 642B cmp r3, #100 + 9799 09b0 7FF6B8AB bls .L368 + 745:Src/main.c **** State_Data[0] |= UART_ERR;//timeout error! + 9800 .loc 1 745 4 is_stmt 1 view .LVU3219 + 745:Src/main.c **** State_Data[0] |= UART_ERR;//timeout error! + 9801 .loc 1 745 18 is_stmt 0 view .LVU3220 + 9802 09b4 0022 movs r2, #0 + 9803 09b6 1A4B ldr r3, .L438+76 + 9804 09b8 1A80 strh r2, [r3] @ movhi + 746:Src/main.c **** UART_transmission_request = MESS_01;//Send status + 9805 .loc 1 746 4 is_stmt 1 view .LVU3221 + 746:Src/main.c **** UART_transmission_request = MESS_01;//Send status + 9806 .loc 1 746 14 is_stmt 0 view .LVU3222 + 9807 09ba 1A49 ldr r1, .L438+80 + 9808 09bc 0B78 ldrb r3, [r1] @ zero_extendqisi2 + 746:Src/main.c **** UART_transmission_request = MESS_01;//Send status + 9809 .loc 1 746 18 view .LVU3223 + 9810 09be 43F00203 orr r3, r3, #2 + 9811 09c2 0B70 strb r3, [r1] + 747:Src/main.c **** flg_tmt = 0;//Reset timeout flag + 9812 .loc 1 747 4 is_stmt 1 view .LVU3224 + 747:Src/main.c **** flg_tmt = 0;//Reset timeout flag + 9813 .loc 1 747 30 is_stmt 0 view .LVU3225 + 9814 09c4 144B ldr r3, .L438+68 + 9815 09c6 0121 movs r1, #1 + 9816 09c8 1970 strb r1, [r3] + ARM GAS /tmp/ccWQNJQt.s page 561 + + + 748:Src/main.c **** } + 9817 .loc 1 748 4 is_stmt 1 view .LVU3226 + 748:Src/main.c **** } + 9818 .loc 1 748 12 is_stmt 0 view .LVU3227 + 9819 09ca 174B ldr r3, .L438+84 + 9820 09cc 1A70 strb r2, [r3] + 9821 09ce FFF7A9BB b .L368 + 9822 .L439: + 9823 09d2 00BF .align 2 + 9824 .L438: + 9825 09d4 00000000 .word htim10 + 9826 09d8 000C0240 .word 1073875968 + 9827 09dc 00000000 .word htim8 + 9828 09e0 00040140 .word 1073808384 + 9829 09e4 00000000 .word task + 9830 09e8 00000000 .word TIM10_period + 9831 09ec 00000000 .word TO10_counter + 9832 09f0 00000000 .word TO7_before + 9833 09f4 00000000 .word LD1_param + 9834 09f8 00000000 .word LD2_param + 9835 09fc 00000000 .word Long_Data + 9836 0a00 00000000 .word temp16 + 9837 0a04 00000000 .word TO6 + 9838 0a08 00000000 .word TO6_stop + 9839 0a0c 02000000 .word Long_Data+2 + 9840 0a10 00000000 .word CS_result + 9841 0a14 00000000 .word UART_DATA + 9842 0a18 00000000 .word UART_transmission_request + 9843 0a1c 00000000 .word TO6_uart + 9844 0a20 00000000 .word UART_rec_incr + 9845 0a24 00000000 .word State_Data + 9846 0a28 00000000 .word flg_tmt + 9847 .cfi_endproc + 9848 .LFE1186: + 9850 .global task + 9851 .section .bss.task,"aw",%nobits + 9852 .align 2 + 9855 task: + 9856 0000 00000000 .space 52 + 9856 00000000 + 9856 00000000 + 9856 00000000 + 9856 00000000 + 9857 .global LD_blinker + 9858 .section .bss.LD_blinker,"aw",%nobits + 9859 .align 2 + 9862 LD_blinker: + 9863 0000 00000000 .space 12 + 9863 00000000 + 9863 00000000 + 9864 .global LD2_param + 9865 .section .bss.LD2_param,"aw",%nobits + 9866 .align 2 + 9869 LD2_param: + 9870 0000 00000000 .space 12 + 9870 00000000 + 9870 00000000 + ARM GAS /tmp/ccWQNJQt.s page 562 + + + 9871 .global LD1_param + 9872 .section .bss.LD1_param,"aw",%nobits + 9873 .align 2 + 9876 LD1_param: + 9877 0000 00000000 .space 12 + 9877 00000000 + 9877 00000000 + 9878 .global Def_setup + 9879 .section .bss.Def_setup,"aw",%nobits + 9880 .align 2 + 9883 Def_setup: + 9884 0000 00000000 .space 18 + 9884 00000000 + 9884 00000000 + 9884 00000000 + 9884 0000 + 9885 .global Curr_setup + 9886 .section .bss.Curr_setup,"aw",%nobits + 9887 .align 2 + 9890 Curr_setup: + 9891 0000 00000000 .space 18 + 9891 00000000 + 9891 00000000 + 9891 00000000 + 9891 0000 + 9892 .global LD2_def_setup + 9893 .section .bss.LD2_def_setup,"aw",%nobits + 9894 .align 2 + 9897 LD2_def_setup: + 9898 0000 00000000 .space 16 + 9898 00000000 + 9898 00000000 + 9898 00000000 + 9899 .global LD1_def_setup + 9900 .section .bss.LD1_def_setup,"aw",%nobits + 9901 .align 2 + 9904 LD1_def_setup: + 9905 0000 00000000 .space 16 + 9905 00000000 + 9905 00000000 + 9905 00000000 + 9906 .global LD2_curr_setup + 9907 .section .bss.LD2_curr_setup,"aw",%nobits + 9908 .align 2 + 9911 LD2_curr_setup: + 9912 0000 00000000 .space 16 + 9912 00000000 + 9912 00000000 + 9912 00000000 + 9913 .global LD1_curr_setup + 9914 .section .bss.LD1_curr_setup,"aw",%nobits + 9915 .align 2 + 9918 LD1_curr_setup: + 9919 0000 00000000 .space 16 + 9919 00000000 + 9919 00000000 + 9919 00000000 + ARM GAS /tmp/ccWQNJQt.s page 563 + + + 9920 .global sizeoffile + 9921 .section .bss.sizeoffile,"aw",%nobits + 9922 .align 2 + 9925 sizeoffile: + 9926 0000 00000000 .space 4 + 9927 .global fgoto + 9928 .section .bss.fgoto,"aw",%nobits + 9929 .align 2 + 9932 fgoto: + 9933 0000 00000000 .space 4 + 9934 .global test + 9935 .section .bss.test,"aw",%nobits + 9936 .align 2 + 9939 test: + 9940 0000 00000000 .space 4 + 9941 .global fresult + 9942 .section .bss.fresult,"aw",%nobits + 9945 fresult: + 9946 0000 00 .space 1 + 9947 .global COMMAND + 9948 .section .bss.COMMAND,"aw",%nobits + 9949 .align 2 + 9952 COMMAND: + 9953 0000 00000000 .space 30 + 9953 00000000 + 9953 00000000 + 9953 00000000 + 9953 00000000 + 9954 .global Long_Data + 9955 .section .bss.Long_Data,"aw",%nobits + 9956 .align 2 + 9959 Long_Data: + 9960 0000 00000000 .space 30 + 9960 00000000 + 9960 00000000 + 9960 00000000 + 9960 00000000 + 9961 .global temp16 + 9962 .section .bss.temp16,"aw",%nobits + 9963 .align 1 + 9966 temp16: + 9967 0000 0000 .space 2 + 9968 .global CS_result + 9969 .section .bss.CS_result,"aw",%nobits + 9970 .align 1 + 9973 CS_result: + 9974 0000 0000 .space 2 + 9975 .global UART_header + 9976 .section .bss.UART_header,"aw",%nobits + 9977 .align 1 + 9980 UART_header: + 9981 0000 0000 .space 2 + 9982 .global UART_rec_incr + 9983 .section .bss.UART_rec_incr,"aw",%nobits + 9984 .align 1 + 9987 UART_rec_incr: + 9988 0000 0000 .space 2 + ARM GAS /tmp/ccWQNJQt.s page 564 + + + 9989 .global TIM10_coflag + 9990 .section .bss.TIM10_coflag,"aw",%nobits + 9993 TIM10_coflag: + 9994 0000 00 .space 1 + 9995 .global u_rx_flg + 9996 .section .bss.u_rx_flg,"aw",%nobits + 9999 u_rx_flg: + 10000 0000 00 .space 1 + 10001 .global u_tx_flg + 10002 .section .bss.u_tx_flg,"aw",%nobits + 10005 u_tx_flg: + 10006 0000 00 .space 1 + 10007 .global flg_tmt + 10008 .section .bss.flg_tmt,"aw",%nobits + 10011 flg_tmt: + 10012 0000 00 .space 1 + 10013 .global UART_DATA + 10014 .section .bss.UART_DATA,"aw",%nobits + 10015 .align 2 + 10018 UART_DATA: + 10019 0000 00000000 .space 30 + 10019 00000000 + 10019 00000000 + 10019 00000000 + 10019 00000000 + 10020 .global State_Data + 10021 .section .bss.State_Data,"aw",%nobits + 10022 .align 2 + 10025 State_Data: + 10026 0000 0000 .space 2 + 10027 .global UART_transmission_request + 10028 .section .bss.UART_transmission_request,"aw",%nobits + 10031 UART_transmission_request: + 10032 0000 00 .space 1 + 10033 .global CPU_state_old + 10034 .section .bss.CPU_state_old,"aw",%nobits + 10037 CPU_state_old: + 10038 0000 00 .space 1 + 10039 .global CPU_state + 10040 .section .bss.CPU_state,"aw",%nobits + 10043 CPU_state: + 10044 0000 00 .space 1 + 10045 .global uart_buf + 10046 .section .bss.uart_buf,"aw",%nobits + 10049 uart_buf: + 10050 0000 00 .space 1 + 10051 .global TIM10_period + 10052 .section .bss.TIM10_period,"aw",%nobits + 10053 .align 2 + 10056 TIM10_period: + 10057 0000 00000000 .space 4 + 10058 .global TO10_counter + 10059 .section .bss.TO10_counter,"aw",%nobits + 10060 .align 2 + 10063 TO10_counter: + 10064 0000 00000000 .space 4 + 10065 .global TO10 + ARM GAS /tmp/ccWQNJQt.s page 565 + + + 10066 .section .bss.TO10,"aw",%nobits + 10067 .align 2 + 10070 TO10: + 10071 0000 00000000 .space 4 + 10072 .global TO7_PID + 10073 .section .bss.TO7_PID,"aw",%nobits + 10074 .align 2 + 10077 TO7_PID: + 10078 0000 00000000 .space 4 + 10079 .global TO7_before + 10080 .section .bss.TO7_before,"aw",%nobits + 10081 .align 2 + 10084 TO7_before: + 10085 0000 00000000 .space 4 + 10086 .global TO7 + 10087 .section .bss.TO7,"aw",%nobits + 10088 .align 2 + 10091 TO7: + 10092 0000 00000000 .space 4 + 10093 .global temp32 + 10094 .section .bss.temp32,"aw",%nobits + 10095 .align 2 + 10098 temp32: + 10099 0000 00000000 .space 4 + 10100 .global SD_SLIDE + 10101 .section .bss.SD_SLIDE,"aw",%nobits + 10102 .align 2 + 10105 SD_SLIDE: + 10106 0000 00000000 .space 4 + 10107 .global SD_SEEK + 10108 .section .bss.SD_SEEK,"aw",%nobits + 10109 .align 2 + 10112 SD_SEEK: + 10113 0000 00000000 .space 4 + 10114 .global TO6_uart + 10115 .section .bss.TO6_uart,"aw",%nobits + 10116 .align 2 + 10119 TO6_uart: + 10120 0000 00000000 .space 4 + 10121 .global TO6_stop + 10122 .section .bss.TO6_stop,"aw",%nobits + 10123 .align 2 + 10126 TO6_stop: + 10127 0000 00000000 .space 4 + 10128 .global TO6_before + 10129 .section .bss.TO6_before,"aw",%nobits + 10130 .align 2 + 10133 TO6_before: + 10134 0000 00000000 .space 4 + 10135 .global TO6 + 10136 .section .bss.TO6,"aw",%nobits + 10137 .align 2 + 10140 TO6: + 10141 0000 00000000 .space 4 + 10142 .global huart8 + 10143 .section .bss.huart8,"aw",%nobits + 10144 .align 2 + ARM GAS /tmp/ccWQNJQt.s page 566 + + + 10147 huart8: + 10148 0000 00000000 .space 136 + 10148 00000000 + 10148 00000000 + 10148 00000000 + 10148 00000000 + 10149 .global htim11 + 10150 .section .bss.htim11,"aw",%nobits + 10151 .align 2 + 10154 htim11: + 10155 0000 00000000 .space 76 + 10155 00000000 + 10155 00000000 + 10155 00000000 + 10155 00000000 + 10156 .global htim10 + 10157 .section .bss.htim10,"aw",%nobits + 10158 .align 2 + 10161 htim10: + 10162 0000 00000000 .space 76 + 10162 00000000 + 10162 00000000 + 10162 00000000 + 10162 00000000 + 10163 .global htim8 + 10164 .section .bss.htim8,"aw",%nobits + 10165 .align 2 + 10168 htim8: + 10169 0000 00000000 .space 76 + 10169 00000000 + 10169 00000000 + 10169 00000000 + 10169 00000000 + 10170 .global htim4 + 10171 .section .bss.htim4,"aw",%nobits + 10172 .align 2 + 10175 htim4: + 10176 0000 00000000 .space 76 + 10176 00000000 + 10176 00000000 + 10176 00000000 + 10176 00000000 + 10177 .global hsd1 + 10178 .section .bss.hsd1,"aw",%nobits + 10179 .align 2 + 10182 hsd1: + 10183 0000 00000000 .space 132 + 10183 00000000 + 10183 00000000 + 10183 00000000 + 10183 00000000 + 10184 .global hadc3 + 10185 .section .bss.hadc3,"aw",%nobits + 10186 .align 2 + 10189 hadc3: + 10190 0000 00000000 .space 72 + 10190 00000000 + ARM GAS /tmp/ccWQNJQt.s page 567 + + + 10190 00000000 + 10190 00000000 + 10190 00000000 + 10191 .global hadc1 + 10192 .section .bss.hadc1,"aw",%nobits + 10193 .align 2 + 10196 hadc1: + 10197 0000 00000000 .space 72 + 10197 00000000 + 10197 00000000 + 10197 00000000 + 10197 00000000 + 10198 .text + 10199 .Letext0: + 10200 .file 9 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 10201 .file 10 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 10202 .file 11 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + 10203 .file 12 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 10204 .file 13 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h" + 10205 .file 14 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h" + 10206 .file 15 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h" + 10207 .file 16 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h" + 10208 .file 17 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h" + 10209 .file 18 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h" + 10210 .file 19 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h" + 10211 .file 20 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h" + 10212 .file 21 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h" + 10213 .file 22 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h" + 10214 .file 23 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h" + 10215 .file 24 "Inc/main.h" + 10216 .file 25 "Middlewares/Third_Party/FatFs/src/ff.h" + 10217 .file 26 "Inc/File_Handling.h" + 10218 .file 27 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h" + 10219 .file 28 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h" + 10220 .file 29 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h" + 10221 .file 30 "Inc/fatfs.h" + 10222 .file 31 "" + ARM GAS /tmp/ccWQNJQt.s page 568 + + +DEFINED SYMBOLS + *ABS*:00000000 main.c + /tmp/ccWQNJQt.s:20 .text.NVIC_EncodePriority:00000000 $t + /tmp/ccWQNJQt.s:25 .text.NVIC_EncodePriority:00000000 NVIC_EncodePriority + /tmp/ccWQNJQt.s:88 .text.MX_SDMMC1_SD_Init:00000000 $t + /tmp/ccWQNJQt.s:93 .text.MX_SDMMC1_SD_Init:00000000 MX_SDMMC1_SD_Init + /tmp/ccWQNJQt.s:131 .text.MX_SDMMC1_SD_Init:0000001c $d + /tmp/ccWQNJQt.s:10182 .bss.hsd1:00000000 hsd1 + /tmp/ccWQNJQt.s:137 .text.MX_DMA_Init:00000000 $t + /tmp/ccWQNJQt.s:142 .text.MX_DMA_Init:00000000 MX_DMA_Init + /tmp/ccWQNJQt.s:238 .text.MX_DMA_Init:0000003c $d + /tmp/ccWQNJQt.s:245 .text.Decode_task:00000000 $t + /tmp/ccWQNJQt.s:250 .text.Decode_task:00000000 Decode_task + /tmp/ccWQNJQt.s:527 .text.Decode_task:00000150 $d + /tmp/ccWQNJQt.s:9855 .bss.task:00000000 task + /tmp/ccWQNJQt.s:10063 .bss.TO10_counter:00000000 TO10_counter + /tmp/ccWQNJQt.s:537 .text.PID_Controller_Temp:00000000 $t + /tmp/ccWQNJQt.s:542 .text.PID_Controller_Temp:00000000 PID_Controller_Temp + /tmp/ccWQNJQt.s:711 .text.PID_Controller_Temp:000000cc $d + /tmp/ccWQNJQt.s:10091 .bss.TO7:00000000 TO7 + /tmp/ccWQNJQt.s:10077 .bss.TO7_PID:00000000 TO7_PID + /tmp/ccWQNJQt.s:721 .text.OUT_trigger:00000000 $t + /tmp/ccWQNJQt.s:726 .text.OUT_trigger:00000000 OUT_trigger + /tmp/ccWQNJQt.s:744 .text.OUT_trigger:0000000a $d + /tmp/ccWQNJQt.s:754 .text.OUT_trigger:00000014 $t + /tmp/ccWQNJQt.s:950 .text.OUT_trigger:0000011c $d + /tmp/ccWQNJQt.s:956 .text.MPhD_T:00000000 $t + /tmp/ccWQNJQt.s:961 .text.MPhD_T:00000000 MPhD_T + /tmp/ccWQNJQt.s:1045 .text.MPhD_T:00000056 $d + /tmp/ccWQNJQt.s:1049 .text.MPhD_T:0000005a $t + /tmp/ccWQNJQt.s:1593 .text.MPhD_T:00000210 $d + /tmp/ccWQNJQt.s:1603 .text.Stop_TIM10:00000000 $t + /tmp/ccWQNJQt.s:1608 .text.Stop_TIM10:00000000 Stop_TIM10 + /tmp/ccWQNJQt.s:1637 .text.Stop_TIM10:00000014 $d + /tmp/ccWQNJQt.s:10161 .bss.htim10:00000000 htim10 + /tmp/ccWQNJQt.s:9993 .bss.TIM10_coflag:00000000 TIM10_coflag + /tmp/ccWQNJQt.s:10070 .bss.TO10:00000000 TO10 + /tmp/ccWQNJQt.s:1644 .text.MX_GPIO_Init:00000000 $t + /tmp/ccWQNJQt.s:1649 .text.MX_GPIO_Init:00000000 MX_GPIO_Init + /tmp/ccWQNJQt.s:2098 .text.MX_GPIO_Init:00000228 $d + /tmp/ccWQNJQt.s:2110 .text.MX_SPI4_Init:00000000 $t + /tmp/ccWQNJQt.s:2115 .text.MX_SPI4_Init:00000000 MX_SPI4_Init + /tmp/ccWQNJQt.s:2320 .text.MX_SPI4_Init:000000c8 $d + /tmp/ccWQNJQt.s:2327 .text.MX_SPI2_Init:00000000 $t + /tmp/ccWQNJQt.s:2332 .text.MX_SPI2_Init:00000000 MX_SPI2_Init + /tmp/ccWQNJQt.s:2537 .text.MX_SPI2_Init:000000c4 $d + /tmp/ccWQNJQt.s:2544 .text.MX_SPI5_Init:00000000 $t + /tmp/ccWQNJQt.s:2549 .text.MX_SPI5_Init:00000000 MX_SPI5_Init + /tmp/ccWQNJQt.s:2754 .text.MX_SPI5_Init:000000c4 $d + /tmp/ccWQNJQt.s:2761 .text.MX_SPI6_Init:00000000 $t + /tmp/ccWQNJQt.s:2766 .text.MX_SPI6_Init:00000000 MX_SPI6_Init + /tmp/ccWQNJQt.s:2971 .text.MX_SPI6_Init:000000c4 $d + /tmp/ccWQNJQt.s:2978 .text.MX_TIM2_Init:00000000 $t + /tmp/ccWQNJQt.s:2983 .text.MX_TIM2_Init:00000000 MX_TIM2_Init + /tmp/ccWQNJQt.s:3161 .text.MX_TIM2_Init:00000088 $d + /tmp/ccWQNJQt.s:3170 .text.MX_TIM5_Init:00000000 $t + /tmp/ccWQNJQt.s:3175 .text.MX_TIM5_Init:00000000 MX_TIM5_Init + ARM GAS /tmp/ccWQNJQt.s page 569 + + + /tmp/ccWQNJQt.s:3352 .text.MX_TIM5_Init:00000084 $d + /tmp/ccWQNJQt.s:3361 .text.MX_TIM7_Init:00000000 $t + /tmp/ccWQNJQt.s:3366 .text.MX_TIM7_Init:00000000 MX_TIM7_Init + /tmp/ccWQNJQt.s:3527 .text.MX_TIM7_Init:0000007c $d + /tmp/ccWQNJQt.s:3535 .text.MX_TIM6_Init:00000000 $t + /tmp/ccWQNJQt.s:3540 .text.MX_TIM6_Init:00000000 MX_TIM6_Init + /tmp/ccWQNJQt.s:3701 .text.MX_TIM6_Init:0000007c $d + /tmp/ccWQNJQt.s:3709 .rodata.Init_params.str1.4:00000000 $d + /tmp/ccWQNJQt.s:3716 .text.Init_params:00000000 $t + /tmp/ccWQNJQt.s:3721 .text.Init_params:00000000 Init_params + /tmp/ccWQNJQt.s:4355 .text.Init_params:00000280 $d + /tmp/ccWQNJQt.s:10140 .bss.TO6:00000000 TO6 + /tmp/ccWQNJQt.s:10084 .bss.TO7_before:00000000 TO7_before + /tmp/ccWQNJQt.s:10133 .bss.TO6_before:00000000 TO6_before + /tmp/ccWQNJQt.s:10119 .bss.TO6_uart:00000000 TO6_uart + /tmp/ccWQNJQt.s:10011 .bss.flg_tmt:00000000 flg_tmt + /tmp/ccWQNJQt.s:9987 .bss.UART_rec_incr:00000000 UART_rec_incr + /tmp/ccWQNJQt.s:9932 .bss.fgoto:00000000 fgoto + /tmp/ccWQNJQt.s:9925 .bss.sizeoffile:00000000 sizeoffile + /tmp/ccWQNJQt.s:10005 .bss.u_tx_flg:00000000 u_tx_flg + /tmp/ccWQNJQt.s:9999 .bss.u_rx_flg:00000000 u_rx_flg + /tmp/ccWQNJQt.s:9959 .bss.Long_Data:00000000 Long_Data + /tmp/ccWQNJQt.s:9883 .bss.Def_setup:00000000 Def_setup + /tmp/ccWQNJQt.s:9904 .bss.LD1_def_setup:00000000 LD1_def_setup + /tmp/ccWQNJQt.s:9897 .bss.LD2_def_setup:00000000 LD2_def_setup + /tmp/ccWQNJQt.s:9890 .bss.Curr_setup:00000000 Curr_setup + /tmp/ccWQNJQt.s:9918 .bss.LD1_curr_setup:00000000 LD1_curr_setup + /tmp/ccWQNJQt.s:9911 .bss.LD2_curr_setup:00000000 LD2_curr_setup + /tmp/ccWQNJQt.s:10018 .bss.UART_DATA:00000000 UART_DATA + /tmp/ccWQNJQt.s:10112 .bss.SD_SEEK:00000000 SD_SEEK + /tmp/ccWQNJQt.s:10105 .bss.SD_SLIDE:00000000 SD_SLIDE + /tmp/ccWQNJQt.s:9939 .bss.test:00000000 test + /tmp/ccWQNJQt.s:10043 .bss.CPU_state:00000000 CPU_state + /tmp/ccWQNJQt.s:9952 .bss.COMMAND:00000000 COMMAND + /tmp/ccWQNJQt.s:4394 .text.Get_ADC:00000000 $t + /tmp/ccWQNJQt.s:4399 .text.Get_ADC:00000000 Get_ADC + /tmp/ccWQNJQt.s:4419 .text.Get_ADC:0000000c $d + /tmp/ccWQNJQt.s:4425 .text.Get_ADC:00000012 $t + /tmp/ccWQNJQt.s:4523 .text.Get_ADC:00000068 $d + /tmp/ccWQNJQt.s:10196 .bss.hadc1:00000000 hadc1 + /tmp/ccWQNJQt.s:10189 .bss.hadc3:00000000 hadc3 + /tmp/ccWQNJQt.s:4529 .text.Set_LTEC:00000000 $t + /tmp/ccWQNJQt.s:4535 .text.Set_LTEC:00000000 Set_LTEC + /tmp/ccWQNJQt.s:4560 .text.Set_LTEC:0000000e $d + /tmp/ccWQNJQt.s:4564 .text.Set_LTEC:00000012 $t + /tmp/ccWQNJQt.s:4976 .text.Set_LTEC:00000148 $d + /tmp/ccWQNJQt.s:4984 .text.Decode_uart:00000000 $t + /tmp/ccWQNJQt.s:4989 .text.Decode_uart:00000000 Decode_uart + /tmp/ccWQNJQt.s:5552 .text.Decode_uart:000002cc $d + /tmp/ccWQNJQt.s:5567 .text.Advanced_Controller_Temp:00000000 $t + /tmp/ccWQNJQt.s:5573 .text.Advanced_Controller_Temp:00000000 Advanced_Controller_Temp + /tmp/ccWQNJQt.s:5742 .text.Advanced_Controller_Temp:000000cc $d + /tmp/ccWQNJQt.s:5752 .text.CalculateChecksum:00000000 $t + /tmp/ccWQNJQt.s:5758 .text.CalculateChecksum:00000000 CalculateChecksum + /tmp/ccWQNJQt.s:5803 .text.CheckChecksum:00000000 $t + /tmp/ccWQNJQt.s:5809 .text.CheckChecksum:00000000 CheckChecksum + /tmp/ccWQNJQt.s:5871 .text.CheckChecksum:0000003c $d + ARM GAS /tmp/ccWQNJQt.s page 570 + + + /tmp/ccWQNJQt.s:9980 .bss.UART_header:00000000 UART_header + /tmp/ccWQNJQt.s:9973 .bss.CS_result:00000000 CS_result + /tmp/ccWQNJQt.s:5878 .rodata.SD_SAVE.str1.4:00000000 $d + /tmp/ccWQNJQt.s:5882 .text.SD_SAVE:00000000 $t + /tmp/ccWQNJQt.s:5888 .text.SD_SAVE:00000000 SD_SAVE + /tmp/ccWQNJQt.s:5957 .text.SD_SAVE:00000030 $d + /tmp/ccWQNJQt.s:5964 .text.SD_READ:00000000 $t + /tmp/ccWQNJQt.s:5970 .text.SD_READ:00000000 SD_READ + /tmp/ccWQNJQt.s:6048 .text.SD_READ:0000003c $d + /tmp/ccWQNJQt.s:6056 .text.SD_REMOVE:00000000 $t + /tmp/ccWQNJQt.s:6062 .text.SD_REMOVE:00000000 SD_REMOVE + /tmp/ccWQNJQt.s:6130 .text.SD_REMOVE:00000034 $d + /tmp/ccWQNJQt.s:6137 .text.USART_TX:00000000 $t + /tmp/ccWQNJQt.s:6143 .text.USART_TX:00000000 USART_TX + /tmp/ccWQNJQt.s:6218 .text.USART_TX:00000028 $d + /tmp/ccWQNJQt.s:6223 .text.USART_TX_DMA:00000000 $t + /tmp/ccWQNJQt.s:6229 .text.USART_TX_DMA:00000000 USART_TX_DMA + /tmp/ccWQNJQt.s:6298 .text.USART_TX_DMA:00000038 $d + /tmp/ccWQNJQt.s:6304 .text.Error_Handler:00000000 $t + /tmp/ccWQNJQt.s:6310 .text.Error_Handler:00000000 Error_Handler + /tmp/ccWQNJQt.s:6341 .text.MX_ADC1_Init:00000000 $t + /tmp/ccWQNJQt.s:6346 .text.MX_ADC1_Init:00000000 MX_ADC1_Init + /tmp/ccWQNJQt.s:6535 .text.MX_ADC1_Init:000000bc $d + /tmp/ccWQNJQt.s:6542 .text.MX_ADC3_Init:00000000 $t + /tmp/ccWQNJQt.s:6547 .text.MX_ADC3_Init:00000000 MX_ADC3_Init + /tmp/ccWQNJQt.s:6654 .text.MX_ADC3_Init:00000060 $d + /tmp/ccWQNJQt.s:6661 .text.MX_USART1_UART_Init:00000000 $t + /tmp/ccWQNJQt.s:6666 .text.MX_USART1_UART_Init:00000000 MX_USART1_UART_Init + /tmp/ccWQNJQt.s:7065 .text.MX_USART1_UART_Init:0000017c $d + /tmp/ccWQNJQt.s:7074 .text.MX_TIM10_Init:00000000 $t + /tmp/ccWQNJQt.s:7079 .text.MX_TIM10_Init:00000000 MX_TIM10_Init + /tmp/ccWQNJQt.s:7128 .text.MX_TIM10_Init:00000024 $d + /tmp/ccWQNJQt.s:7134 .text.MX_UART8_Init:00000000 $t + /tmp/ccWQNJQt.s:7139 .text.MX_UART8_Init:00000000 MX_UART8_Init + /tmp/ccWQNJQt.s:7200 .text.MX_UART8_Init:00000030 $d + /tmp/ccWQNJQt.s:10147 .bss.huart8:00000000 huart8 + /tmp/ccWQNJQt.s:7206 .text.MX_TIM8_Init:00000000 $t + /tmp/ccWQNJQt.s:7211 .text.MX_TIM8_Init:00000000 MX_TIM8_Init + /tmp/ccWQNJQt.s:7320 .text.MX_TIM8_Init:00000064 $d + /tmp/ccWQNJQt.s:10168 .bss.htim8:00000000 htim8 + /tmp/ccWQNJQt.s:7326 .text.MX_TIM11_Init:00000000 $t + /tmp/ccWQNJQt.s:7331 .text.MX_TIM11_Init:00000000 MX_TIM11_Init + /tmp/ccWQNJQt.s:7441 .text.MX_TIM11_Init:00000068 $d + /tmp/ccWQNJQt.s:10154 .bss.htim11:00000000 htim11 + /tmp/ccWQNJQt.s:7447 .text.MX_TIM4_Init:00000000 $t + /tmp/ccWQNJQt.s:7452 .text.MX_TIM4_Init:00000000 MX_TIM4_Init + /tmp/ccWQNJQt.s:7607 .text.MX_TIM4_Init:0000009c $d + /tmp/ccWQNJQt.s:10175 .bss.htim4:00000000 htim4 + /tmp/ccWQNJQt.s:7613 .text.SystemClock_Config:00000000 $t + /tmp/ccWQNJQt.s:7619 .text.SystemClock_Config:00000000 SystemClock_Config + /tmp/ccWQNJQt.s:7778 .text.SystemClock_Config:000000ac $d + /tmp/ccWQNJQt.s:7784 .text.main:00000000 $t + /tmp/ccWQNJQt.s:7790 .text.main:00000000 main + /tmp/ccWQNJQt.s:8194 .text.main:00000140 $d + /tmp/ccWQNJQt.s:8204 .text.main:00000168 $t + /tmp/ccWQNJQt.s:8457 .text.main:00000274 $d + /tmp/ccWQNJQt.s:10037 .bss.CPU_state_old:00000000 CPU_state_old + ARM GAS /tmp/ccWQNJQt.s page 571 + + + /tmp/ccWQNJQt.s:10031 .bss.UART_transmission_request:00000000 UART_transmission_request + /tmp/ccWQNJQt.s:10025 .bss.State_Data:00000000 State_Data + /tmp/ccWQNJQt.s:9966 .bss.temp16:00000000 temp16 + /tmp/ccWQNJQt.s:8481 .text.main:000002c8 $t + /tmp/ccWQNJQt.s:8884 .text.main:000004b4 $d + /tmp/ccWQNJQt.s:9876 .bss.LD1_param:00000000 LD1_param + /tmp/ccWQNJQt.s:9869 .bss.LD2_param:00000000 LD2_param + /tmp/ccWQNJQt.s:10126 .bss.TO6_stop:00000000 TO6_stop + /tmp/ccWQNJQt.s:10056 .bss.TIM10_period:00000000 TIM10_period + /tmp/ccWQNJQt.s:8912 .text.main:00000514 $t + /tmp/ccWQNJQt.s:9424 .text.main:000007cc $d + /tmp/ccWQNJQt.s:9862 .bss.LD_blinker:00000000 LD_blinker + /tmp/ccWQNJQt.s:9447 .text.main:00000820 $t + /tmp/ccWQNJQt.s:9825 .text.main:000009d4 $d + /tmp/ccWQNJQt.s:9852 .bss.task:00000000 $d + /tmp/ccWQNJQt.s:9859 .bss.LD_blinker:00000000 $d + /tmp/ccWQNJQt.s:9866 .bss.LD2_param:00000000 $d + /tmp/ccWQNJQt.s:9873 .bss.LD1_param:00000000 $d + /tmp/ccWQNJQt.s:9880 .bss.Def_setup:00000000 $d + /tmp/ccWQNJQt.s:9887 .bss.Curr_setup:00000000 $d + /tmp/ccWQNJQt.s:9894 .bss.LD2_def_setup:00000000 $d + /tmp/ccWQNJQt.s:9901 .bss.LD1_def_setup:00000000 $d + /tmp/ccWQNJQt.s:9908 .bss.LD2_curr_setup:00000000 $d + /tmp/ccWQNJQt.s:9915 .bss.LD1_curr_setup:00000000 $d + /tmp/ccWQNJQt.s:9922 .bss.sizeoffile:00000000 $d + /tmp/ccWQNJQt.s:9929 .bss.fgoto:00000000 $d + /tmp/ccWQNJQt.s:9936 .bss.test:00000000 $d + /tmp/ccWQNJQt.s:9945 .bss.fresult:00000000 fresult + /tmp/ccWQNJQt.s:9946 .bss.fresult:00000000 $d + /tmp/ccWQNJQt.s:9949 .bss.COMMAND:00000000 $d + /tmp/ccWQNJQt.s:9956 .bss.Long_Data:00000000 $d + /tmp/ccWQNJQt.s:9963 .bss.temp16:00000000 $d + /tmp/ccWQNJQt.s:9970 .bss.CS_result:00000000 $d + /tmp/ccWQNJQt.s:9977 .bss.UART_header:00000000 $d + /tmp/ccWQNJQt.s:9984 .bss.UART_rec_incr:00000000 $d + /tmp/ccWQNJQt.s:9994 .bss.TIM10_coflag:00000000 $d + /tmp/ccWQNJQt.s:10000 .bss.u_rx_flg:00000000 $d + /tmp/ccWQNJQt.s:10006 .bss.u_tx_flg:00000000 $d + /tmp/ccWQNJQt.s:10012 .bss.flg_tmt:00000000 $d + /tmp/ccWQNJQt.s:10015 .bss.UART_DATA:00000000 $d + /tmp/ccWQNJQt.s:10022 .bss.State_Data:00000000 $d + /tmp/ccWQNJQt.s:10032 .bss.UART_transmission_request:00000000 $d + /tmp/ccWQNJQt.s:10038 .bss.CPU_state_old:00000000 $d + /tmp/ccWQNJQt.s:10044 .bss.CPU_state:00000000 $d + /tmp/ccWQNJQt.s:10049 .bss.uart_buf:00000000 uart_buf + /tmp/ccWQNJQt.s:10050 .bss.uart_buf:00000000 $d + /tmp/ccWQNJQt.s:10053 .bss.TIM10_period:00000000 $d + /tmp/ccWQNJQt.s:10060 .bss.TO10_counter:00000000 $d + /tmp/ccWQNJQt.s:10067 .bss.TO10:00000000 $d + /tmp/ccWQNJQt.s:10074 .bss.TO7_PID:00000000 $d + /tmp/ccWQNJQt.s:10081 .bss.TO7_before:00000000 $d + /tmp/ccWQNJQt.s:10088 .bss.TO7:00000000 $d + /tmp/ccWQNJQt.s:10098 .bss.temp32:00000000 temp32 + /tmp/ccWQNJQt.s:10095 .bss.temp32:00000000 $d + /tmp/ccWQNJQt.s:10102 .bss.SD_SLIDE:00000000 $d + /tmp/ccWQNJQt.s:10109 .bss.SD_SEEK:00000000 $d + /tmp/ccWQNJQt.s:10116 .bss.TO6_uart:00000000 $d + ARM GAS /tmp/ccWQNJQt.s page 572 + + + /tmp/ccWQNJQt.s:10123 .bss.TO6_stop:00000000 $d + /tmp/ccWQNJQt.s:10130 .bss.TO6_before:00000000 $d + /tmp/ccWQNJQt.s:10137 .bss.TO6:00000000 $d + /tmp/ccWQNJQt.s:10144 .bss.huart8:00000000 $d + /tmp/ccWQNJQt.s:10151 .bss.htim11:00000000 $d + /tmp/ccWQNJQt.s:10158 .bss.htim10:00000000 $d + /tmp/ccWQNJQt.s:10165 .bss.htim8:00000000 $d + /tmp/ccWQNJQt.s:10172 .bss.htim4:00000000 $d + /tmp/ccWQNJQt.s:10179 .bss.hsd1:00000000 $d + /tmp/ccWQNJQt.s:10186 .bss.hadc3:00000000 $d + /tmp/ccWQNJQt.s:10193 .bss.hadc1:00000000 $d + +UNDEFINED SYMBOLS +HAL_GPIO_WritePin +HAL_TIM_Base_Stop_IT +HAL_GPIO_Init +memset +LL_GPIO_Init +LL_SPI_Init +LL_TIM_Init +HAL_GPIO_ReadPin +Mount_SD +Seek_Read_File +Unmount_SD +HAL_ADC_Start +HAL_ADC_PollForConversion +HAL_ADC_GetValue +HAL_ADC_Stop +Remove_File +Create_File +Write_File_byte +Update_File_byte +HAL_ADC_Init +HAL_ADC_ConfigChannel +HAL_RCCEx_PeriphCLKConfig +LL_USART_Init +HAL_TIM_Base_Init +HAL_UART_Init +HAL_TIM_ConfigClockSource +HAL_TIMEx_MasterConfigSynchronization +HAL_TIM_PWM_Init +HAL_TIM_PWM_ConfigChannel +HAL_TIM_MspPostInit +HAL_RCC_OscConfig +HAL_PWREx_EnableOverDrive +HAL_RCC_ClockConfig +HAL_Init +MX_FATFS_Init +HAL_TIM_Base_Start_IT +HAL_TIM_PWM_Stop +HAL_TIM_PWM_Start +HAL_TIM_Base_Stop diff --git a/build/main.o b/build/main.o new file mode 100644 index 0000000000000000000000000000000000000000..6ca86e620e049bf2f2cd1a64f1f2d484d523b517 GIT binary patch literal 134592 zcmd?ScYIVu_dh;!%kJLnCfVd}AcR25Qer|$LVyS%gakrJLJ?3AP(u*{SVB=TsDz?o z2NG1kf?~mrSRQ#0MM3O7AQl7_tg(Ti8ifbH?=yF1vxMm9^ZNb1zrTKYz2@$mbKYm> z%*>fHbLZaO%pX)<%sFT3kFzw^M1gx;P-cz*q_KP0-Hg4+8r*ElA-C_9Lq>GkYr`81 zpWe=u5&ikr_QM2l%qTosqa{pgJ3~KOqw`w6+A7;! z$x>sAw;a)u|N8yZUyN_rV3sXvEY=HBS5@fiMJ>5n0Xx9aCnwR-CTUj0TGrB!P;H_7zsLQwwnmk$n}_rQU) zaW@?_XPi8^eclJqy06hlPPlRbp%a{vT-C3KQSNGfOOwn~J>Ztl7cK~K9ykzRJ@w#C zs6V3m^$^$LSk?SirRi{d)dQMwyw#qvwI{Ufk38{S z_uqe?@|iDqml#Xhw%rN4_2d7_8*upYIS&tt-@WvJR_!{tv`^!~AEtLc*r__LyhCN$ z(5{t}+k#u#cyNl~K5(Gp^tTSWreA&V(dr!s`1A)3q*fn2_*V6ygZ@9QFCI9M6rzkz z_8my9=KJ>@XjA<<>O$Z3c^OD5d*6Xp(|hCdzX$898nY#*;L?co$ExSM_6|M1 zf7CsN#+UdU!S@#)u1MC>wH-AZGGD10td%8HB31kj4^@9}7c%x|G17K$2K!&M((K*) zeq;@%ozlHu*#(!(yly}_PaS@=WaC#=$#X$C-dLbcX9N> zWK8BiuJ7pR4G7bd`R(=X9lbCallhnH<012>C@qzHsy-I{!IWoko#7E#g6mI>#I`p+%WsIQ44ofXAOUV>@nsZL>+~K5AFdo@<{a3}nV)_8_Q{zb8ee9VJ{7{q*90sLsd^7Uz{EXA`< z#GwvaonB|unRTu@cU^kf*h>qKvXNsakG)jGr}8QC1sZ3+&T83e*f&b6)jH}chBxS* z4;uY7W@q=^iNmzVRUa|P^%X)w<=)*SshQ-d9e#8n+Bf`Y)uf18?+RZX=Hl$g+W25p zZFHT#&K-=YjVSj#?!>c6l|j@xse(Q|_>84?E|Be{He&w#bDPd8OF)}y3KJ$LpiMP} zs!ina)Fw@~iEM7(rncd2Dr&h+9@rn=9uEI;TI3IFk@Y{dh{lb^D3|?@?V&NMiFL-P zCRVkFA_280S+u7n_|L7WncZ@0Ft-1z5&B=XhkOsQ?SC2{;d8P*EYu!~QPdtT+LPR@ zJsx;m+hLKvxVhtV)ZTE9Ym)r^_=J1h|EfI8#*#&FGysXkERjd{KwT@-v%hE39 zV+AeQl_2bb&kDO7pKaBGU9qsMH|%0)eZk?odpLbIDX7;*o?#Qkh$_8E#EZYRC&11a zKgSltIAMzuG<@jL0mBA%8$D(;qq)L@_hbEU zAyt7_6UHaH%G`fnDN9LhwEeut>J3pDzkj~6Y{21|*o2yU%2?{21$(LzW+p65m_2s( z*qN(l?wPe`X2PtovsTR-TeYexp=#;S^qQsRsWmKhdd0+wCn_GQxMSG8#jpGr&7!w| z(a17;)Z9931*jX5ZXQ~P>kUXt%Jx)}$M2~~5T6MZ`mvfxXYv9)b~V17oC@Std=775 z6LDYLz-H~Km|LnH^5~;}Wc`caPoC_;A6XVV>&VX8Wu#Hq;1?QB-Z(>hMkyqjdczjI zAYz5w_mRKPYb{3u#XXQ;THe_yJANdrDPoT zCm7oaPCOYil(f_2?t+JMS||sfl-ShbWLbv$7@O+c_c-;IgzYJvoxQ_%^3Dq98G%JJUHh6n?LwA^J8y2Su3Do(kQR~ z)P96%&i+L4<)=ZP*sJ(oWF5@3F5=Eo_r$hN>=fr%T#Z|z`|F*Zc5?CF`sCuzX)iASa$ocn^ISbGC~DODj=R>mV=EJ-vDDJC)s=RG zhWn-sxL3n{Q}(g?L1p(YV5tLzgzl)CB>l_wR`wg}jIJ{-eVcp3IcluceP`}w1`o)R z^<}nDUxuhJy@mQZqQ33*!s2t1WC`tCD4~rgp>+!-#G-^pP=Y@tM(X=p(Dw>`s|9@n z`ZrL2%6*L3hhn|#`cq?(SsY#5syMOuS;VA-3ZC+eQ$reS_^2jh39XvJs*ELDj}+*W z#Al7ZR(x*JzZIX%4$c&Edy@F9vDb>vE%vwKlLdpbggiJ&eAWcliq9>E1Vo+qWkK~=YX?ptsR8Wtd$^OSLdOa8zn zobTuW5v(S}jX-EABPAj^WthkX=e6B9tZZJzu(C}RlaMbfn_W>>_I$OB z)8-%T^sJN5LwsSN+dsRn(YLHbM9Y1RU(~$a$e2S>u6^oR#eYZTh%yOv;s=JdWC(g1 zywFH-BGsjiPtQyhk}HINI{8_SWP;=ESAz1Sv=gYg^@ET9HB%QSp-nmJWi}xo5FBTv zu_8BHV2u#g$Tm~!cW{~@ip$U z9*u#_dkO=uv1Fc%J#F$y)yLF{_$wY#J}67J+|AxlIgRz!(2PpbcgjP)M@EG%V{x(8%jX4HduP3L zs-C@g!+M-z)$&^0Bh_YorWLmptu5H(0apWeT5&6<{hKs!bir|E){c!4;247A^!z;= zz2KOFFo%V1j5>(hg#t;U5Hlj)HlLfQMoZ1^)|J^ z@ss3cb&I-Eow{fr{=#~e(sfz4W!;x$F3Vb$y{yNw&dbu4owY1|S;n$1%a*3<>&W5) z?Ejq{ODkx&zh(rTp{L z)a9;%p`9Ohb_R&LlRDQD;;g$#+T|`K$(8=lFtQN4YT8|s7o;|9(F$>jtLQ?EvdX6( zT{^2N&q8^eB{bNXv!&3#L1K>pZnqt%?Xv{q0NIqjqX(*Ra0L+(hk+sEv5s zndNMgvwk+9y>67@e%voC*s`$#GprS?W3bMs^`uTKc4m0xM#skJGkSwYAvA6t>i-q% zb8s^07W0bA!P$ctjSk|p0Ouy+4!vd+okAw#xfJ}nFrlJtrGB)ah-MXsO|Z9z2azd~ za$3~#HmT9ehaY`;mVbE+tcqQ3*E;2|-$-?@Lu9~78RjsJ{P3e|Mwz5H%2n%1(S#kD z8{^Kf9OFo599811u4vJE)sp`&J{Onv4DOn^YdY^S&cplenzU>BIL3Qu$JS&waYs!m z-#<^R6vKB`myV>nYMdcE_teLCUg>afGN?E+!|uL$*xmP~*qviG2Wd7>6)Q>S{gt$1 zubNsmwlYD?wkfDb!wxlZv5xET#XQ5>Ik8+*&%T1es!3HB;$HG1;5ZNki_xDmo!ux; zdveEE@U4u!yZJ*S8-oqs!ab)UxbH%;G{(+G8iI5Q(mP1)48|rQ4K0t9HI!rD;H<7y z8wZx!bBh`b-L4u~roqa7!q$Gm@+ayGLr-h8V|Qe$=U@3{`KA4bI3?u6hmb1V!5moJ z6={Ec*HBAoG_z1fP&_wt%5d^5meGR3l*;-lv@+Z z?O*8VtJ+m<&|756GW((P4)@3zH$k?r;ay9Z|OT7CpoJ zIZk{l6U+8gxXRjI*S7Sb6MAs3Cjl+;m07So=?A$6H5>o`8>D*Y;pwtn2i(;soi_~n ztlZ%Adbo!?TAqBGkF149aO}Sy61~8SAB5b&Yq)p3UvibsYMi6gsCW~~-7Qco?aH0E zm(}8qeb)h_x;O6YcOB624n?Qx4F?Tze@}MFw@51XHI81+Qq+BG`9hC8U%O#=U(9-s z-nU{A?hGiGQNcP~JMq$qDbiOJ@|Wp>zB49XJF#PN6R&Qwg9M5@p z!?yZU^*?T)(dRv%-f*n`{L)=wKeelZcxB}u7w`hrCa0ISy`k2K9Moy#0ed4@S|vz%2U?{fPUdzxz}7f3%NMv9~$a(D3{Y^698&)uk{KC}ifAxa>_{(ZVZ5BVO}}1wC#af%v+nhKZ;*jK)mHzyF)D^lZecvtf}FOM4)e_C+jx`1_urwLAxF zdBq|Y^zQFcnvD~L3s`0e!za&*jVK)LJkL1vd3#}7hKQPf{l05cio|yOTWqq#Zr;R# zN9tR{jzq-F)d`a`<{y9gN$h8^N+)2IF2d7aZ&jd-r?jbRjkWc!-yh#3%L2w6jKS9haKv5QiLsp4jLmI^)I9EUAkw&JjSnA&`DVh}i4P;PBV)6S-%!XLqp=HPR~jo*7`w_C;bv@}p>f8pHFDAzyWY6517q{eF&@-q z;)IcLGcgLKnp0z_(B82)vodeOPRlgEiDb-WR^jS4uY&;|^QU&G(VT{Bgt^_%nAdcn zG@p4%kg-VfvQ);R%=b`owD}Ooy@n|GuGM6Nx-uQ^DdLIvrMBEW9jA(C^^HdKZ~(0<}+;>>uPEi zW8KX4Z5Zor{+^C=J2MkCW|`B_C)s8i`m=}m4$99lyP>5$&GUimWsZRTz0LLLlU&ol z^=va50c8GYW@EXOs^ybdkxXYNLg`DP~ip}!di-2!tl26BLzhgu5F5=e184(UMi zF`KbLWT#C^jXX1Sb zHr{*}mS1SbfPax$f)Xw^Z-NaKW*2BpFm*3> zQfW?uwbRUxpgY}c=V5Gy`7)4~nnO|hW$@I-VLl;*A+$bZ>yUR(CD?3S zFpEATFE-3+m(O7lMwIplw`QWn-oL1Z$9U`l5IDl}rl3o-bv*V)K_`3Z_CtHzk?X-4 z?)?K5YEL)-J-CK@pCyeaLkP{=lNe8h5SrIbQ|;*xLihG3#4{m;?%hEX{@D=1@D3rw zdLDZhsz)t`Z^#IyJ;!5T5_FBrJBk1scvTN zslAcZB~++jwsz=872TUfmP1aJ2>EZ!O){bMJ~Gi%(jtxdgP0uJ3*5LB=!mB@?JaJl zV3fV*b_V|)9y=F&>dm_`akO_GqqLymT?UZ$o}xY8r{X}ruV|ldRMAMLeV}N+uZZXm z6&>)NhY79yhsS17Il*}EgO~!^4khp4-INS^r=rumKbfFEQgj#Z5IC*2OVOF$m2f%j zV@2n9vk?HaPZXW&eG*eZ`&7|+-m@@iwa<8LnW(?OTS(5ZTeY{u+cpULb48bXr=10Q z50AY>;753`qJG)SW9JLH!tu5*c;SPHoVo;%ipV7 zwiwO+YIlG#Hd${w++V~e{>q62j4fmv&ln#QnlvM2OK2 zDMo|gZRG;vuwooFyi>`rBRuv6(fmfk`ziJ5QH5A)ddE>~k10l-=^f((VyrQ}GpUw8RP!G;z2nIh|5S)|rZe@(vBlK$GB?erNSaB-ipiO$ z7xHdm2uX#K=*%;MB*YMsY9%q4XF5rUAto|8f~Z2$H0**N@5rei1Rdqj+Z1gw|0P(! zv=dzaTt$Vim5{T@b71NrMZ1}YWHBSG?N&OP8arwvv)+yo!8pibi$-QK>m5lNAhVhE zt|UG7FcfdSCrO_@n#lJh>9==ag|R-6WWfHE$PXnMZ+}7Le;A;OWhOOjpen~3~al9~2xM1CU49Q#(pHtSPK=Gvbk^jV)tGSA*i zBJQ>rbOJu_nc#BH>^h zTTJ8wX;zhHy@;IGjag#N(n5_qMk7C4(T4XRrlvJV(H?JR2hdk4+UFZWJ$aR){l4Ku zU#;kXcLUinSJCm_PY_S7YZRU68&C{x`zDjRAxtB-Dt9(Ti#4JV65o?+i zq40CP26>Cuk&ESd4OR}zrx;kCBM1?x7+9V^p)QS53@p!I5hGeLmU8Bg!zROu(e(s) zUSP2`SGSfU^mtcM+0_n^_FAt{W9BK^@C_I_m|52<8qP9wAhWJhw9mT~w@B9YdW^GI z^Lt;zpjz`49q_(Mbd93py?>H(EKqc!_e+v5RCKcUb8?17s{9V#zbJ|=R&<)z$^d~0{-dj}X7kGEmU~Yo*m}e4EsFH} z1`P)Nx}pQ#{xo`TC_3Idi0G|~PV{C_Gq))^*;h1dG_&4RbO+yvQANz!uIMy)C(3_I z(OrBaX|&%~bf$M6_K(&(iq7%Y5dE&AbG1fcaXPypy+|VfmHs7 ziZ1c4pxN^uMVI@AL%c(gBfMqQyq$_3?Y)zV|47keymdtHQuKH%99R%OR&)jEZ0r>j zJ(>CcMWOIBT|XBd73g9e(5>w#!Wp&S6i$v>gQ966>4Au^XpgUuy6v!{ecny9upCje z-}?+X`B6m&d?U{R{+OcUeM4xNk1IOSnPk5!I@vdpyth%&9eksS{zK7e%wLZ~6YEc1 z_riJ)H9_nte?&&iBAw}YDIdFX??aq+3g(q?cV;euS)92l5l_93=!90V$9X!zOaw2$ z5JCXE8659ZdNe*XkMS^W+$GxAnNKG4L{aFsK|048j#0{k5R(|$)e@&v<1n8hyZfBAkl6{CRFT<|H0;(mqKWJ& zNspaKWUeHAb_$VwCF!?25t%Q^fSp0)07=F(S37h=`idkg?ahdfk*`VeQhO`H zLF5~ftg@fLS{nJLBBZdsB^mT? zNiX5{yKc~XC4C#*|7%Q{$gi}2)7a)jWm^^|k39q?MCAw+b`$n+oJ2(RmZV{C#0W(7 zk)+4I3>(I%evJEFXtMHRQANrp2U=GsibqC~q39u*Ua z8fs0a>i?h;hf5u1AHX0+jg+KeKSa`VCF!vzzyYGhNYZB?G(nD&q@TIYL&S)>NQ*DTkh%8D)T$LJE|{PN^XvfP zmH%!@7T85#`&UYGpnVN>-)c#g*pXz$eUdD<-@{px{{cyku)Cpt|AXzF^NZ1TBtn6I zZF^_27-K&|Ry`ug@vN0WckHc=c+OB|8@hn!gORO_qqw^M#Kr%ZMx2<;m|W{qAnaU} z8KdSHvsYr8#HcxD*yqB$7&Z1DyDL02MvcACp4Sni8f?G)CV|fhdB%41e~el^;_YuS z)nm@LX?@0BpS=}>9is+2*fD<6q@D}}m^eB?QFf6O~6&fw(OhcK`)@1;I1z`4SMVm?T5JSb0iP|SZM zxIheS%uY!T!~oH06$T4MyKbcjxmU|UL9GmW+z=BVn`xbe4zjyqbYh#P@mlnMY|}J; z39}-$X&O(&B#%`?>9eaa*)ani$?> zyOJuXNp_}U2RoCb3#By89)X3#UM!_u>{qc;**7LTo{}ki!CsP#rzNN;NBDw$i?lK-0=J8;%%gTA3(H22_yn*{3kt0p(eK z^fSm3H5APCC6!gG`)NWX28LTlsJ=VULje^WnEe7)`hW@!hJ7u%GjP5v!ed{AFc=ss zNuPZeR-k|i4u1Ot`XHbj14psg)dZ9$V5J{}`4gC~*PvDpRUP9GY`02LpZz_0|j}gv>0FDCu=zs8%@RjB5p~@ zk7`NrfF!Yt!15LNO_Cnw`k0z}Tpvf}ka~i1>k{b7`A(4L8)z&utKb~C%^(*s&qDv| zW=9O4fpr=F5a_}6wZOVbLFu2(xtR>j%f&s%DGVStqcQS$aP}zmUq7yYOF9HnIz^nH zO*)HFC^P+7{J1$7(;Yg4F^L0%x!xLbH-VJSP|j~4op#vIakCe$nn|xs8s-?}J?2bY z{pKyWCY!r4!$4h%NfS7i>t)ajlm{;4R#!|AFU`L|1@BA*I?hXLa9{%OME;2x=%r0d zU?T5C)zLv=1)_dn67SqY;FG4&ywJPeKF=?oLYZj4Q5x|Tq#Yo zhmmxiB$Mq#j7{8pNp@haB^^O8&^<8GwFaRg?#Wn+t?n0y(FXk)x7A_1NsKWX7#})} zPr-pKPBxH^;Xz6!b03H9ljCdWP31zM%;mj0m6(*`(E;y-z0gdSQFw7wR6^lDzPTS z9g*Z5vDJt>*3Ov*bM0Z6R&l?lY!M}2YhQ<16?a0A;>L~klyRrT)`Oni!t3ckrIkSs z(&Bkv7|@0;;MAjpRz`Oa{vrgQxB%CQ)z*!9=IYjpp1OJbX$51dmaKU>Ce7$+Sr|lH zN3#ue59i$S7)|az3A%Kp>7xA?Xd>H zY6qEUUyUv^lw&8`S(wU(a%?yl$FLjI^=W90cxKoUwu;H?VV*eT+rEf4n_XKGAIlrS zhLM-o_76CK*++5FV!Vy#X?u(|J%dl@vbNh$g*jSsHN)kJ@c9F6m%;JP36je--7q1D z37GF$2T+w*hs_Usj>9pV)?w4RttMw3V}kr#c8JHOb=dqS)Lpa=n?I`VVy?P0(8u(9 zP_Bmxk4bbFTQf2KqU+o$j$l`XV%@`}q7#GMDsXsgib3wC)t3g;tvc2(_L1%>QrC$= z?n@UuS=5K52GvM-;ktcC&9w_t&-I3SWNi%ZIU$X6omiyHzjG> z=O%;PE=iX?5z#sRElIlV0YttnNsk>sbc%mRl9v5%^iTY|l8mq)>jLsUNqX&RaKrfb zCF!%v5ijFEkYuF&1{wJu=}}R3f2?xxJ0yu?gbT^6kMww;V*K$RM@*((s7Ex4|1{)< zE;xGpXI>JK7y8N8-IDa!L#cw#CD@18oQ!eUk-0ikMSJ!3P>S)ze;M%%6`YPq8ow`8 za5TIle!ry(rl(2qUrQiCkTwnO3aY&!O4Xi<`5J#nk{wefA?*`{IvC(jPl{4vRk;<+w>8cFu$=S^TjmXV$i|m)LkafW1@v?~+7h zBC=7E$@WSLw0}slgZ&N+jsH`UX?7d(sS}dyVt+)^lakEDn`h*Z|1}SxMFC$tip1SxaR8<<6|bZjl!~RmGSqfsZx6L#Ns}UJ8d5N+d` zu?AYDP%aDs&$chalvFGqv3i`w`V_YDoYPqI5bAl)(^&r{R`0-IG*Fh+e)RBOjQ5G4 z?TspaAo_*(i4JGA$86$#+J>_(rb7C33}=;)jeWX@v-)A5!TaQfvtlsZyiZ{m3r6$? zt2B(&t{(ye?=w7{HGw*(&$w__1RRj}nHBx;-+&Uy+y$opF4VyfA% zU^l`0+TpBuR94^i;j96e@Vsx=Fjgexe}LzRHHEWw_febsmV649EL%XVt`gFYwc9T0 zI{%L*NV|HhQM_+uSi$Ww=(efv%y3pfSTrx3MR#bt?+xLsv#I#J2%2!Jbr)q2t4%m- z4z^J|uTwZH6-zPC%L-$OS-VY{9>v<-79_~oFMy@W-bD_RR~F8?f`+f3Me|RgZp3QI z^UcL!MvbR|=^srmswz|;LiKMI&dS7`lsXFUYHcl`hohdD3;a?h5C^Cuc%!(>m>Qmpf>%&+PIorbg+lQy;Mx% zrQ{kj4O=|7<92t%1aTpEL?EN1|73nOtWVq~F-d$JWKmU0r;v2$0ysUWNa8~fAYv}l zBz_{v=>jJcR4c&dT>5Zzz>&C#XKnV$PCKuy;l5li^Ws?9;;dlBVE|kS|%!K&# zVgShpFd--*B`rceB4fHr$OHv}?o$W|30YE59VU1Lqnr>c&8j7VFe{bchpvh*baB3p zm~?@y6m64u2HF<*(<6KNBPDMma&q|o!bl|X9l!_fR>;E&3CTVzHEla`Sw>8jtfLL( zP|^Kx(IlQ8gt~4?P_Gb(asZttK&9xpxZ|b-okt+LKu+;IiQ`uaaMGk~xJnfQ$7=C%<)HotqF)m4ht4#rObN;-khlzVK=djK zW`KZhMr&Jd(j{~nL1{nHhH?PW?md+kBECfLb8~)kNKQG(>3LWZKLmMTw(7FS2_zgK ziFbm2ph`)$hDmNfZw2mEl5dnmO(2xc0{1B~?;(p+;@ePfV3rcMRbtq>9g5LE!w>rq zQ?!M`a2tB22FHHPg7~Ls@raF&ISqm@-lw8x+INO>GQS^FquoY1j2-w*(B_*XTpXX+ zonrTM9pjHczvER4hy_OI%3qJrS*J=gkgt!36dK7w2*$@y>5S23ccR5;s2OlKmW-7C+I(!TkimPrxWcm-e2zs|vGLW2t9Pe$n1l9qNoW010WNEyeFTaC<0B7Ow%95T-$u`WNM zKvLAi6*H9ary}$Wvxc$vK)i#L(Fn}f$m~O+rqL4+ey?mA!nkPKg+1||8En8I5Ydm1 z5DmRILae0!1?mr^ZqqKG%=rBg;&vj)5d@IZhgUnT*P2@YU_@j(O3auD(Rg6SBC#$x z*B~k(<6N=(V*H^9Gh+nUR{<~wDWeF)t;pO=8mv2?9s$(C2q(r7s{m;&gq-)nmwLqd zyEwu{f%yY)w<2Xhg^|NO0~2Ueee_!|Y5W|X#j4~84_abY%=0~G}qgO1q=NSGPxSNn1!}A@(>%sUEDP(vu)c(%!-clwFPeWB2+H*lT`!vJ5 zooRRvejZKCRuK`LT0no)FElxKhb(Rt(TTdc3jk?IT`#@la#HC<8vLAY(-@DBu#!NG zL@Gt8}Loe&l%%^r_Q3JR*ha+79lkNSPGk zxb94lCJm<@Zt_=uRT+JX6%<)M4>R#-FxNSSm>!1p=K zOfb@kc^gHB{f_!%FvcTcS)r|FD}y$P-T6iEH~vsF%U1%&SDmdaf5_@ZmVW~7P9(?j zhpY?2Eq}XBfUA~}}7T+8`k<{%+w3f9A4dDwLaELrqQTgalM6d9WA|GUj*l(_HTkekuNcQyth`uf2jPG^10-#|6NcMdsfOP$W za_3vVPW_~P(*dd^ps?=;0W2Z=##nk8fylna04x-xk$o3GNcPDPM*lr6S3U6P4`zca(+Z2KC zNDF(<%3z$9D==W_%0L+(>L$ky!dHP~=Bk zT(Rsi{=LT-PypZ^5G@C2DN@D)5RW1A2vY895U(Ti8j=$u5zA2oT?bOG-s78I04_QTRCE;Xijjm-9gs;y z5=P}CL$5zLMm<4_jIJ+G?uf_tSAjHY3_#}zAQ|v77R^7!hg2h+=dyg82}nKl8$bsHkc{difOJi#oZB)^5|E6tqH)N8B#dg0Od`_RG<-h% z1g>LHQ^4;<>Xzl}SSSt31-cg!%W97c`EdzEPQWrW%+TpkM}!f6J0v2a=!_PKDll37 zXuq7Sp#q#5GSSO}&qD7!C?{(NKu4fw_>r$~7`W^8zPlD(02m6Yc;lP5PD zkTEUEQU7wOKew4&4cYxteosqs=szRnFP|p&vKm?czomS4OLFMHE#=3<bejC6JhBBbYNq`fiD#ZJRt?vrn=NfY3~l9w&z>%p&F-Ag z5g9W6B=4Fl9X$bXx3~vd1k<`3Q^;i78Ck;})hI1%sY+ zI;MQ-7N%s{2%AV*2{4CFP#R#g6Rvz3x?h~2cw`603|2CaBg>VJrFuBKIUq*@y2%pG z4FR0evF>vTDUgt>LJ(OAtPtUDv;?dS0SsY<+B+a%PLYs*hal{9L$8&9z0CnxR0&*Z zi3FSq0Ya6i{m=apl2oF4LspV4%UCA?1400&C2}^PmJflT&b~N=aEhSrU|D-0rE{OF zq*TYyV1y2WO$S!DIBX5aW?3h}qXVn^!*~&JAbKLPImDw?gVq*09LkD^m`-87Xjz;J zF`XS9am4DLH5+U(`G=@Rd%}7aP0E*mp3MQm1pp|QfH5J!=`H{Wy@5uRToZ!GN`wml zFhv6H4FN)SUn-Ovz?z zxmsK9myn(zh^$w57JTywS^97Xz|k*Q>#5!sq-5F|l2>J+w}uLJIwTZVJHIUvj#aWs z;fPrXEbCJdM~2G4LO(b42c|mzd<48N8!m+~&%Q^|bU-%V?Wa9*N&si|NG$z{YQ`Q# zhKuWZ$}MthQDxZZY=memK=e{DOFtKTBNA)k`Z56*yS3f~oD9(%fM$hCB(cWmx{ZK0 zxU~vZ;vE3p7Ald%ngG2|z#HA#&8kHD&8aik;}~Zv8a^(kc8K0Bu1M zr|`Rx`BZ2{T<2glq45nBe}`NDk+j-CbQqup0X%>mCW$q1{gHro;ydN#0G@=%7l)TB zkXZTyn2RLV#1&n}_)@q2E&-o`s1raPkosfd63aRd22l9wh2m&~bTzK$h`57o z2g|CE;&V?EQ+O2ODk;87iszEHTptCXS^`#_reC1+)ynmf6kjFvDKHBCI;sDO1cO<)B8?EgAPditVpThZM*(cO2OiAHD{AB3?kYjtae0dovs9% z9uB>!*akckj^xOxGlr${QS^|A7RqK1i8@ugF(F=XIUCUu07k>HdF^N%5uAAiWwAZ&BixAtupsq%T9_*OmAch)MJ? z(ut7x4M(gkE5KR}3Ath7NXHN4EG=*;KYv34@+4p$^}goGQ}Pd`e7uwkPtiPOO1@jl ztHb3XPx(PgS4*jwMQ{k8Qa>yKo01@(jB_&^;QO`3{^1GBcfr@mtNl6UmLnyur zt9MIDhLnh26_Q`2WRR4I?h+D;IAq(!Qqp9b4-=0h*EHAZoGc~IZqMmgDvWhHn`YpH zYUaWTZl{?${ajjivCp6=z{NG5a*w+7eJDJm4McAN_$E@nP9U^pb6Cg58u^S>Jorc? zg(qBk`g35XfpD&{Pq4e7ii{6x@Uj8Q_!22&3y7o0h&Mjc_ktp(Ka}66`l!4!QB|^ba@i+gJiRoqQ{bf<$Eqb%$bNgR$lIkr}yEtW#vwQ z8s=(EugvJnUYMV^BLaZou0&eU5tOb^e`zklENXF1U58O_oJ;?SOnDQcN)$Z>sozH+ z^kr+Vce;*n8l!6kXi+nxsv>bmQJzLqqo>-1&!LgOLq2-XlzTsKheN|$~SX}kwf z9nf@7p7AP(r;vGqi044Ofy@>pmc9hL6;jm1mEsA%+ND28MLY-57Xa-cEreNi1errb z+zrBNgIyyMOZQ)o0!0yY{g8^d#-)EpMVt*0Jy=db%IE^3FEVEnkp$u#WQHTL^dJf( zMNM4yP!aQ7dgt>2EQe?YK+{O8KZpg$%qJon#NEiOKw{~?qCisA#Fau9zs{vkry}A2 zd=8*zNy`J`Eo9y#;slhwM26l%XX!73B1KJH4^t8IUHa2h#8(jg4$v{u+6f{W4iSlz zu?<8=WP(U6{d!QOsEO+-Dq?|4Z=fO`gQ!11{YYySh;xw{Ma1nOW*{>SiKPz)bxIUL z*9f>FU*ytzi~+C;q8k8OL|T(TtVU)f5$Az;4w+|>So&NHF)3=|+KP&}!KF{5BI+P| z51@BQ>n0FiBeRdR#7rbC-WS4^HqU&CoQbq8#stAt>}A1zi3+2ccmleAP+>F^{cW)a zM`B_o5>^u$IaJuqhy$ecGk~1|>L`F!)y|_8E*`K{67VjU?zsTK`4Hs;lqZ0om){K+M|UD3B|nO{{)k_Nw3KwW0iM?<3Aqzy zEBfZFwrqSBDUC;2V@@keyf3gDVeg95*~5T-2JB_wZ1f*Wa^hqbCN`s&LDz*NSbhcA zWLy4Zm8p~&*6A&>_7iDs7qCAjYuPxolp;P^cl`9yI)rrVXq)(`)V&n!qolhIx_Kq& z7XGxEKwsw7mR08cNYy-JwxuuSQp>3(DtjcrO}&_v2XTPET z$FqFc=(O=7m6<3rtkcygsC_zF+Oo;%`{!b+0D&KA z!B`=3;w1nSl40`dR`G zhUk5O-W9;_s_|k3#G1HP5pboce@;Mp#qbA!zC+450^CVt{zPKwZ-FALCa!2IUh*+@ z4IP&8DMa*MQ2@!Aur$jOA);Xtub$B?>pUJ}dSMoWE4c7d*wLvX6=jVN8;WiyhrfzJ zbB1ElKMutdQ@;~6iJ_>3;uNHR9Excz4+Yp?P&qUd*Q1PUk;G8cBC`ys#i5vP>Lv^o zL-7Pa>jbccp_pyz-3UlS@j5`S31ACDF~`&=6Oe{tFF>CoiJ>@z%x^-gg`v38)Ndy( z8VYZFtoKMwL-80y|Er-G6GYGVltXb3iU^_{KEFZ@MczLSMSoLIxEMyzthf-0HOSGTF{}bW8o*3|x)D$;el(XVAv%2k!DwkNW%^Op zpN6y0JPb?;%Hb;~sPN01g5QgF2o`v zT$_G2;R__;+DDK%gw&#Ie{JY9NQ+$CO2$qeiKUZkUxW-7*Xfk|#n9^rNUog(P&*`+ zPOeR2O5Vb7eREoYg3!#GNBigb`X9->qJ~D6jmok za0ft-qaeNmqC8A7##bAy=!+9Li*auF?la^K-@5tY{!V}xU9$FTGV~LqLHBnjf&P;;ocp^q(CB_G9GP(9`V!@~8+sP(%P4~= zHU--Vq>OwJX~=X!V(GD<2&;+ftEBaop^qi46o}~AZ~+0uTW+*bz6K&%L6;SvXTelwxsa;9175#=p$1NW`-(Dc{(#yfayzga(H#&IPcs=UFi5+^|j`3uAcS zDXP=QH|z9^{<+g97<&FCXc~3;3Y1if^v|6>$z)kUt;M0Aua0kqW~QyV5rj%LexU1V+x5*x6mIX7M-py!!c$SiV>m? zXNdl;tNjLgww3JakD=~M1>@1Fs;k>I>*}O`?&?%Se;jp-t{#k%1|j`(S9dVy&h)qriXbY^s~#*psv0W=-Ei3t8Yc-W+bPpUq;4xvbTlwhZuSv(xR?@ z1R(kW?53{10HPMUTKV@JDGuvu<=S_iA?i%_w&2yH{V?M*e6rJ7AZU-oc@TO4mt*!^KYY?kLBTAxQ@Di(oIPh*MlzflhA0`dzYJU*7;YiK8 zx>+c}FI-lJNucQH37Kz*)dIEjj4!4O}eIVVB z4aYPHVXS(ZF#_yOVBZ+drnTZa+|-VTP^|wIGQ&De_M+JCvc|W;-as|3#k%O!*sH0= zJV>d=z2QYWui8_Mjp1xrV;1I(FeeTLhOAUVc#IHcw6^NP&iMcGj_B!6fwF(iaMPF=Bd2D&0eNA85yioS!3)8o7?$)Hba zt>`Pf`m*)&`y>F~4e2i!n>!DqWn3IkgOr)UM&A1NJJYSRhcJbh86HF>1aVs z(>KPtM8L8R;L(xqfZ6zx+u{KI+;A0m^vlJ4=o>M2cra(GuoKq}ARp%9{fB2DeHbY- zI|a-~9A+aJ4aEEsy~!VSm{}e1x))OBoPi48c@Dzwm69Mc>1rFQ$x_tRDEzh-6*S#43=ig_4C%ES9VlO{~#i(YKWT<*?KP zKlQaRJWZ?sf(&@Ksp#oa>DT5;&g()jagJ2_tEr|Mu;>X-`^%gGmXBgK&k<6E^kpT{eut&ne^er;HX-R}`pG-0B@5oc+z#vZCRT)G zt&uEvhhMUuZ(_9vi@f6#ht-02qys^w{@7GB{pu|#MO-1;-lP=rj(n-q&OvZgJ_Rgl zUrx9Z%bEo?_49d>t-hft-^E17ES8A5EhETvWYKq?UUVl+Wct$cqo=d8!KNDDblCDV z%6at@)zNpnN&H<4V$@X#@tr92#A$`*mxC=vb_z1oU9Ay8oY~y@Hn6DWAmymCJ_9YB z!y%OeMnU0y&8F9^Ug?M<2_)8M4ungQE|Y*g4uHN$euMypzhn2X9GQoa_zt7>O#G0Z zs~XR3Y+RHeHvpnjCoH~5;$s^xV-_sk176?yFhTB*AbLR~2T52;DyC4}f}Fd+ zr>8?xSXu_m5F}ygCCE%daxC433>R;*y(_hZrPTn;MG}_QA+sDwSo%0Jk0If2;Bz&O zmAbI?Q?PKpv4(2>0FqaMqJI`5P8U8#<|9%YxECUVYT~*FIsUQnHYxoK$uGeCByjYd zw0mhu6W2#6SMP2h+zpUuX;7pzkZ>f`#B~GVesssrmbgS<5(JLE(YIfeN7tVz_g_~5 z;pj_Wy?~*AVaWy(j-;Bn9w*!>SEa&@0A?8B^0A7uNtjUd9Ti5qxcpdT==H_?R>;tM zDftP=(4A^NZP)1s1@f^kXLJ~rPrgDY%=AMXjJBQPVNGYsWP?LDUHQF`q0@!@KFH8P zQGPx$^xQn3wm5XRkY9`pJ>1AIMTVXp45x?kP)r<85vrpQn2z-Bt&dIDp@&Atdo*8ShCPs7m6gsu}!Qf$+}Fk zu;c|KtEP#SC|R|Vg;gh2vL0<>(LbJ~)$2`%<*eM|r981s$%mK%`0l21=|3it#_v+Y zd0B(*j7HMvP~awwh^w52qT1<_)lRa|_BoQ3DOpgg28+HdT_jmpUKUE$c}{A9{KXbz zUa$j*=_m!V@&Y&?EBW3BDm^Me{OFUuGK5Z#8Z3zEZXq8-H&=sy^n&OTC4Qa~U#HoH z1!BDZOgKrQ+3U(gya)1Yq-hz|ua;!RGt=g<-MEOYA1} znENj;u(Z>0uzz{`gkiB?lGv$OVBKF4mVPV6!G7fx&6PG_pW|RlYGIgrN`!1My?x=} zr$h{)2D3r$1_AI}D2(2?aD;wKG>8p4h+%eTY7o*J`;IVE>q%CzLH+#LvHTegAw5ql zo`qos*{3U7f?@6mYAv;$9s@YSwY~w4@E~axl8~M(IKo0-UlJC77a?Tghwj**K{&%P z1B9f96%I1sJ6j;>$H5^h5iK2b0PQgMn?TZc1{~ymGta5;rvwO7NJ!t%bc88p?*C!$ zO~C7_>izF^&dE7V(-PXIEu|DVEd>gcq)A6gTAHy*n=~OOotO@3ax&0NWM~VPxeNlA zK~VwG0wO9-sGuka=pVUUL_|bI1VltHSGinNP*jxn`(5k1&)#PzWq9v<-{*b*&woGJ z`RuiRYy7Qw?RCzPa295>r&9Pi3d{Dh#^X4S*DgiPf~=0+^V$(qj=a<3)94KKf!{G) zcQmS3-kSJq`=t;ueo)i}uqIw^CjxbBXnEJgQ~>;dyK`_|>;&iF31lPhgPsHK<~s); zjIFT_YJNQf4$g=neSAUSglEK7IpGv?yuk#OSUgm*-iQCJ(9Ze=x2L3bj#c|&x` zDVK9O6e)ATJc0I`*GVBy?K@#-q|^!dHak&T0O7YOoPCfrF0+OYW9Ws<#W6GQO_W{@ zUv?)BrhA^YckT}^2)I93?rV0VM@y_?<>LW<=W^A=6%5(b+?#;#H~A3qRJ{}aCSSsj z91Y>MEHs{ea>8rlEB!QG8?R@+Ypb9=I6TQ3?p$CE1J=N{4#^&;p1+~;C5jl}t=RyJ zf&mt}08LFL3M`S&9*keP3XIh8$3o1>`r%_uHchehB1Uheb2ff`L^mcbt-d<-;FQGSnNW*!%BwFUj zc1g6ts)S$04u>r^Z*@t`*%N(HwM3qTbYA~nE`G?4IKY~9* zYHd=Md=#xDdO*HQI9i51$kUCg9Qg`-mYs~63$Yy-uY~PoxXUJESp!R3HNFXpuhH^Q zv|L!)FaG2g(*7RzqGJ(Y^uT;O${lqSPHf;_RB|9JXFJO@EKa56H}{9-LC$gn7DKpA zO$TjXo`8J(0;#FJ89gS9i;LL!xW5L2{UTFS^W0RJy6N)Gtjq2RrF3c5e-Y}4o-#qD zQ}psRybsV&-D5EcyUDOvkNO4{=5Pd1=q9!7w5pF!U87kUBg zU;x(7!o1^sKgD^4R>ch)P!sd7JSY;wk0sQgjy{3D=TInkYUJ?3qDisBg9U4>9|P|cE$@#tZ)v-khp!o6e2MbHqJpk986eh zi2NfgCMvLeO#O=@lj3j}cL7b>&v}EfzGwx~HyIZBPVOxBi$v;+7-!*JgjIs5_O}mE z`V_@!J!7efpeOlhoTiYFWEWDA;>ub~mj|U~MiGYUUby99Z-zIIA}>g4gBSUIe7>)tiFSTu1=U7g}Xyw#eCbuIjcj9BPUF@N=4vDPOdL1 zw~;4{jjZ9;S!3y#b(^(hLg(dLy8sT$4WJye#rauxHma$SX^}MrAFH(S;TJwii&`T0 zRK{t&WzyF8X6WLGV&uz}(~*;{`-I#d`N0b#s8Xefe!=AzMohHe+Dc>)KZD^HY&7wW zN>s9=4~DZ)&`kC*aYQLM3&(MT_XatkA^2kH59zP>yq4tVs=g>Eor_cmK_8`F+L?+n z#Gx!^gIqjrke;fR1eFqsZfQZAehZgMh**j8D;cvy`r8dp3g6lXK2GGs=KS(8nJDpO7>DuOjtg;dGB z&=oQ=X|wGjs#u2Ds>PJC>Er4lNql1j;90x~9;^2pfB07J@Ccb8s7zbkFFr+=YnjmBjyuX(ra-E--(J zyJl<`B7so~kEd8``{KUsfMAys+ zlJ1eZTH_w^KYInEYJe?j2E)p^7&ihV=p}3=Fslo-g z@wftTK{ewkdj%6y4qGH9n{UriATf0E-$@KB3ldWdxS(UCVWrCtGbh%d3hLl=JQXm6xww%sVj1pWo1&QtmYx|(Pz<9k z){Z5(13IK6n1lzd`J8<6yYAWYCD{Wx*Uc~?UV=`>j~4=6_kn0!1VgvZqeuN^5qbui zA9i9Q8=Azh%DJffJ8(nC#9g@a%t>j~iW_Pm7(W7TBJX$B%o=^e1^#ERD4x8I`9b&mfAoIM|GRo; zA@8fnK{V!?4jU9B!Pex}cUEAU=Q%O4C?ux2%!!GWAu-M6PE1sX#5AvSVq!~3O!G-j zOl%8@Y3^`hf|(Ac9LB&k8_&!OvRMo;-FVytFqU_y!^x=CdrMYXEAV)+9R)SdRd^WKHgI)|UfU%9?z@S-%MUR@USno%Nf*-(*c5V>6N3 z0JPv{l;mm7x&!ExHF<-x{uaPjdUQ=b>a3pto|H8iw_3>#MiFy9B4lzo8CepTyF_dT zK02=CX4u{_uH-@3vdSxe>NEk1Kf?wp8xeR8!4-TRK+qTiCuft|WnCVWkcGfof2qyxpvw zA5p~fI1MWSS7=rQn{5nP-OC61c&D}mCxL4go-tP?w%Ny4g0!;P?sS7c4Pe6&nK(xx$a2!uQuH(V2}jI<_Q{+J$n zMNASr8aGRJh4I%0fiDLQPO6u{DRUQg9>d8gmrqD0=LSR#RFC5)VwG{DB&|7(?l#yu z^|a#2UJ-l5hL(&x=sad6R2w4?O8l<^4f}~$-9D?(audwH&uKdlxo63Mg3e>M%Va4q z@}MMQ%jwVKM!_PQ=@Lyj{zj4>#{;`au8Q z#afQGODw`2Y_2r3d?6+pLSmXZ9z#rYhr~1wIWe&(B&L~d2EK`#aR=k3`3~F=6Zhc` zifLw@fS7nHB&M0g4>7@}6!cB=>rPB?00@d{o{Ss532HYehL7wOEQNJ&$5J5O2hZ_# zCv>?qpGeS&4Hg|+a8JVXk%tE~aw6*#tB~=W?yyc%MAm66*J(8J4wtP=fwJ0#fY6CY z_wwNqXUN;jhwGdnv6m0GIz#?mK77|13hWAs-5Ua!yq6EpJ44}KK2Y_LOxeqa*PLP6 zUOupuK{9!C zCJZQEf=&W+HP6*_>*7Shx!CMUJWjDLS_tQ2lPB?5XkDZT=c3h3jL`M`xJ1mk)n-hFN?0@Q^Km(b;`8LB{XAQS)RD94NVhL4q+AJYsoybvBD6*BtR!bAFG59A63F@l>zu`bfbw&l z)0TI@dBleC);P|6Nx(TiaRH~i1Dl5^JEVd0;-D6M+c7!HegR+5z5lg*W8Ke2*h$=D zCA8%@8J6&969z8a!8m-|vF@E~j;hG-LR3Kh{7o?H$TY)SgB!jVP_=Zn61QiDlkDZY zg(mR1Z{MvmXC30fbIY`P?sC)ZyYW))x%14y@bX~rdb)&ro=@^?Qe);P5kBm|&HjVD#uLytFaMj9qB*U417xS;=3XgaFaH~mkeRi9 zW_Qix{11_>GRC)mDqFc{x!c8XF2jU_X?Hc}`v+HJ*KLYCPMq;V_JU zj!BJg8%&L7J2n)CP+;p%P&2-5Fci;rY$yz2rVSdfH* zz0ivLNjcX3_Z%_sU`OwNu~ArpoT9?mredjPolkr33d)0Bz!o?_6I(!@;-2%!LD>V@ zD;UN?*uvj?ilfE3T|jPf&v|68?1AhRj6>_>$z6?l~K`|2;WSWiqQ_H^*28 z$2q0pO*r5-Sf;Dtt{Qiawg1&N)Oqggp#zScmVzCDXFJwC-R{C2mcYuE8gggJ+)}gT zd&_mO|9kgLFUu;(|ArrA+PBWlbnZ0E%U&=_|7(40#mwo9gP9J7^iG++&?z8EUhkgA zDe9-}9cIe&%8OF&6?Lzx9>+qaB@-|NZX0LHVvGt3guvL*ax#xV(li#X>Bk8-S zI%*mMS@zmg(ANL*5DdlZf@9wqh5}y+*B%zIu_~}k zxMw>Nc@WQbQpJZSa6?bC0DJi##Ycb@!Az7vUX44bGynTJf;GaoWw{4;y8LhE2um3G ze?P%%#!GNc*XgHi-zjbmZ1Ux%I4F6i6n_^&t71Mpg?nErE--$t?teW>un+RTA|f}z zcOuk#a8r>>auQ722gi}X>c6jIe3x^e8TfS~*x!5!5q%wZZh}2qCU`|oD0F*2?yv+_ z2*WDRQuV|360OdD7P-Ye=aCwDXW=n>?JJC%;erK2-sYb3$Vc4sdkW)5xJ5}nZGScD zlL~~q%M*avYn&R+<5`BEq(@2?WF6{(pW=QPH-`E1;qF4*c;sh)`*GuupVgg*jx8_` zz`RS>b?{jLFDwUgxAopioQpeVM$X&I2L_GT2@L&{?$HZ@n&TA?$@$nwAD3Gn8~GEG z&$~zG#r?k@NpOxg(Xn&E8Irx2RL=zy={d=*IPPTzKiRwkH|F3|j@-*9-dOJvyKvjR z6+T?#>=lQtIeg}4gzIoKaPl%(-_PLAvGza0OZDaUVz;9)zS16WPhE^c-u; zo@NFRP!~+P%0TSj6Ip-SzxVyMc&;6pu=%)=ID+mb>kuRow|w?q-)A#qx~79J8Ck6wCilRd{LUL1P7>t;OMq5BJ-CFmU?;5!U%ZF-mY%6|{+E(zHG7SFHg{$s$N z`vPllds~5CIOP8+Kc|iVPWh$qnbny6ZSH8~?}hu}L;%kOpyilIYN*{*5B2QG3=Nl5 zHKyuQCH4L7y`vqOtZk~badBDg@?E>qbrlV1=a!DL4xG2@%#NP+Oi8L0fAWwGs$_I{ zsHC@NTS-@Ydr8|+-?9Az{h4DkZQFWEN*5QG6_=LuC{l*o*wfL`o7vemlo>8*?d}=s zNH@0)jht0d+cr`=Tr!LVo4&T5{^E9KpnYH{lWy-@Ufj)=KRnX6xU7?D?d?r(8y$u% znq7|V@LzuUGdZ@iUonctxNyfA88tfSu&wiYoF#NU-raUKbC~ml;uWyV! zoey_}UDI|P-O+k9tEFttSt`g9$4NjnUF{QYDzP)%Nse(sgb99lbsMU9f`4 z4^au&hn5C+4vjByN$6}F>0}*2h~?WxdwNHX?df;@OtufMQr~jW5JwU(!VLA~es7ACf3q7jG$!A2K%{X^8hh5RIL^E*eFv^TWJ% z0z!;UjKrtfAXmi?a6!ipw458CBhHX~uFNyR$l_=`C$wAkLuh4r_-5JI)uVWvUUZU8 zYe6}aok-?I60!d(h#*t5V_!uwV${rG%Y(B-_MIE$btnT#(;B;(Pd_`xvF zD32Ev$B#(B_xrFoyf}`kQJff&FPoV68%|LY@dgv(g&Ir??TQi8`>>mCtKRVOqvyw&e>0ln~|9aarN{Zvhu8TJm$JcC$uU;45 zTpTZ42ltC?btmI+KOwO*UI6YtT6{2si&-bFBbH)OC(>UWUsxQUM4t`uJnQ3x_(asa z_~a7nWr+7i!&p=mB5B}GN_*i{4-Or0AqVi$oTon;w`@5e^TB3{+??oQw? zmgr6-6Lg!;;HE3M0~K7Mf{U%r%R?Lf&LG==q8LpZ4SxSf5i~kAevEZA7cOSUUL2td z+ksTmnH5H3H%*GfSHoE>Q68_d#K-gUVvL{uX2u?MA#Y*8ckds89UdMVjG+5bqGEUL zABm4mSC@_Ux?MI}wzh&|`iUlDU(H7!gU_6!54!if;?b?|EsI|XX7TayviRiqS^UDg zW${~qEPl_+;(a+;d}!P(Znat56V4*?_0I{((f3$%w*>R`{CN5L?)dq-@7?lsM<8E6 z@$&VBoP0esZoXX6y}mP4bja6L`N{WMC9e(U>(%k{_0{q7_1L@R>&8I7e&glqrks4e z^bYxYDJNg}q-}5rzjFqv=-gHD{cW$c3T+v6wIn(r$I)FJnOE8FF_zdKiELSyEQ&!4(VqFD59A&g0b z7xx%JIC1-Okd1rw`;Plvqwo^vYfP&3^1IJC(Iah$PR}XkkD{N7RbmRo!Z}F_+i53c z*P=_YS^E-kZrq!Sa=1nc*tN}!y=ZfhSjW!)6LEI_ zGh?@$%bd{;6U7%Jkx&Er8Rx*`EA25upX1D8?>x^b?TLLU?aTk8N}HQ45H~*$E3M@H zDeaaIcnV6yp3ieidm*T_PeEz9v+JMiyQV!E+lSKb*zJ_|Br{zsi4wc7^AcwQ)x?7p?hps^`xzv<21|9N8IA_E!)}UEG{qn zfEJgRCB|P|zHydYTwaQn>lU9_Tx#L@H&vdo$P)t zKR06SK3nKjibU*ZXF9u|1nlmR9p2!!-FaptIypxV7htj#st>pAOAkMn9v-)?E2lo(xm)$&nY{7!@F|Ro z+-&%{^P8iG&+gur9xx2C9z0?P4p+~=fw6*ipL2P&b>pYX>j#5*{TuR{JGXmwY?=St zzVdpP^7^N-dA-8R>)ZRt>pxZI{~RZ;7rk3v|1*%+4=JyY2lDzA<@HO!y#8cNUVi{_ zv?QKDcNWF0z_COtd!JZXLtbK6?Bo=g^F_B4P{IYcb>~}ifVTkIe|h=wLt_v3M!5TzH+?I{hzZ&ryt~LcOB7ote}$90>C;yQ99(D}L=(jb z4Q0(Fe16y^;bz;ZCq`)ZOH_6y>k4OQ+vDr9doqyxFDm(;3nc%iNPYr)6Hkv~zhOEn z**c6&v0G6#u^G0`#uLl13sS<|Qh)z|XKpUBCb_D(sB7y*TSvRL;(Oc*wp`SOYirjj z&MUQmjjz}tNkkG)#J>H3VjC7`u2{-`2H@&0L3dlQ6IE)1oJeCij3ri@mxxVHvKk|x zN#zWtH|gf|bk_-s65mLu` zCc=`dPrG5ngv^b{=gDz=k^eBR%ZZ*#C~JFhGMdPV|L58>E17PC=}D9)6QxDa=+yYp z%#PjinH{^+?l#+ORobm03Zt>d(S06|CvFw3vD8)(l4z$MZ*n7K2E()4$WYzI6R;D- z;Db9+xB9^cccR!kmn-;+Q1I~>6*V6}`4HYdqTX z&f=5(u;$s98Q9~n5RF!v7OTw%f6-bL-Zv(Svh(^IJ8V#HJX3jU!TMhhuHtg_!Md$V^_3{LuNFRqmK)0XxI#! zj`8|IjHmNCiwF#*F}$MUc35$FJhC1yY6p|aXnsx*_bEZB+~_%qz3!qQHWg#^JQmMD z(pCZPv~f;7DK-(k3dW+dlgxr&+<9(>652Ta#lFIyhVWx(SBT;Ca0~@5hO=x8tY0No zONs$zI~NM|ffvreED3sLB5kL)E?$6&qFnUvBaU4*j$#`JD{UT{u%nA3S6esDVDUlW zMVKp0jZeg@be7M&c&UoX8ad^h9jk#u_x1^2#>eKve|*`DCbrT|Vjq}bXMrd%**}Oe z0}GKPW>Rxd-bZ=0$q>yWkEf}k;H-OpKm z&pFiO{998|p2$#SRp<@hw-Hfn2Ik2J#lF9t!Qk!sUDK1(;}fTZs^FKYk0th%XDo4g zoSh|Wird^+ugs(BHP^+hykY zzoo*ly7Bf+13Gfq7-Tj=N&g;KVU;SiJ=!DevcqI7vB4fGK@$0XSgQ_p_?31KZVP;l zw=+K9?eRWsr$t3$_jo^piBay`g!QUr-m3z?7HNwu{BFT}{V+GX7w1(w=V5M>ZB!q2 zOV(@He*RNS)?eB;X>Q4SOTKGU+Q_x*z~``$YuARH{7rZJcyCN_cJ~DA9+BOz19qQ~ z-PLZ7(}wp4EJGRIeF3|NWOtR@_q6W*q|KYB?7msfM%5kOshAh`aVq8$Iu-Lv=htmi zu|q=Fd@FWJy|(PVh>?=A?@^9WMOYg257T(Hw8w}c2fK}?p z{2Jumgt<)_Hn#AwCQm0$2RZ#yHtO6rskgiBNB7cctCU!g?Kr)f=;U+lE)pZ=%#$6Z z_j1c)wq>zHoR4KQow=8|*$!}i{BRYKmrSo4&icl#f$gjM%NH*Vjo_~b_e(F`M`7R> z7Zin8J6sfjuGl3o8zXyy`Ff#TlI@|r-p5lz*17AcBN&}gSNh7!mW3Aje{;M1xoTad zRGsy{)tim?9o3q3o!g_MACOdk4X`n_kk4FaE7L9J)UK9%58@E>}6{~%3sA%(9 zggxa;V}-?`s&+nSG$)|HSh}=i>=lnLicP`^EL5~8bi+a5kYs#rGCn^U-=7P#`PPmm zF7I4_ftloCIBAB7bTYn?b0)+ZuXj^1Z44%2cg?gjG`l_M{@E?U&*RjE-9=m#*d%;n zf9pcKh|j|bb`eVg4nE-=*bo!3bRbYWWwRmUG|||Qznl~D+haq13+L21hvdIR>;)Vf z<{Z%fXM=uaKtTt$KChl)ohi|KUC_Z?J!|6*Y<*%P9Q$yOdxP;2yYbEhBcJTFA$u7w zo%nX+I=fL%*)iEYu>Zi!liTQtM66()ZQ==(2CK?}#juaJ*>O2)U2MOk zT_xkRQoH~cW6k;@h4>wcK9z2ZD z#JNa1;_7h%T(HkcBr3DowhMg7C(Mzk*@ox&j$_FVU(|zD9nM+Ws%67u#36@ctfI%b z!^5sb-RqT!>yVVyQjHrc4`8S)h>+2}Ki-%0Fx$vkP>h#LVH?KWce1vd#}_iDRn}S7 zJa@G%lIcmC3f3*WD`Y8Vm;$K z3BQ$Ll18WR+R8?fUdve@ZaH|>z~Ipq-j0me?gQ1y9U+Y^DUT-_7TIE*$aF8V^EBp} z2<9eqpM8}C4 z#20nPkHXXBEilYaU|7sg#8TL3!0V;h(aBY`LEm-|w;oiGv4V2DdxVWgrnclF+YJ@a zryKB5+rh^>lYwJkg^gt_QJS!c&7jm36ZK8J6ta!UeQ z-(F6w=f@^l?N5m9A3X*;e2J3ole__Hwd?$6+m7>nsy()-9NUE`N=)0CIA-5&iz74d zzbAIv!|FR-2Qxpn({h_H|GRgan6aW+WxK;Im^HXXB1ci|NbsdR_R|v@iKmvwXVB!{ z{^O0r5zs!4_1pi+_#Bo6N-2&V6*n>BmS&>NHlg?IcVfUVCP-U~UAVEMi{mpG0XI(F zXw1+#ZJx$`PS-j}bVSioY%uckaIN)?>E_Li>D0);pn;)uQM!Ggv$w6wq?+r~_5D2~ zsga@4_7T%O)H5*DGji72p@GrCR{Y*H9G9i*TTbjZO|5IwwJGjp zSuItHtKoH1MU|<}Y#Z%r96&CS0-Kl7^w6$!XK$COZK+9ZY-lxWGb8DWYB;rCHk#I5 z)omkf5T_g0BhwX?O)af8)uy_!q6|tL%Cz+@kyffUG!OK)QD;^|b*Vt2s+u>Zhez5* zGU9sA*rRkdf zwr#x`TWF@Gsw&-j)?lVO(`o8<*7gqUtQzU{ims|{sH48WbHH;@U!AV5Z86Y~3w2<0 zB;9WvZ)A2_cGc`a+UeT!VKZ$SD^lx?EwtwP4QXh)rqxtdx3=Ir)2Tr!1PV>3GOT^D z@G4(JW=E#iX0~du*Uzh0kt?cN>o?V;tLiE?Y^Z5SFE+LHwN0(v_#kFC)jW#NGL|k& zkC>KJP0Oa5>QZy!#)@iN&smKFMW|{*T{I212U>xju*OW^z|dK#p0hJ%*j4v|(V_NC z)j)q|PnT7Je0w(dY$^-fKxg$RY*W#(qc+nvGCGuD_{LU%WloJfXoH!~bg8MRtE_5R zU){5#rvv4U$eGyco?#Z3S0=7Gp>o$WZER&GY^(M3je1(YVN*o|Vr{Nysc5Wet!Xhf zy>x*OB4!2=nX6BYTNpm7FVoX7&{b($F>}~Zovzy0(vohiX>7KoUDe&z-=FDa-n^Jn zjm<5khX2bn7FK6YgrDhje2bvNh!N?)hi`hExrsDQ;~>nvkPy_&nxz zq%qanQd7~G_B$4*A86f-Wcmh6m!Vd&;E=phmry9m)3ZUHT3m)Y)mUBMq&~1>6x~Ut zcc87qHqp&J9V6YQaS_TKsoUkZcB|)+zQLhP7rK{5bhoUAEv;4Q3iKO&Qi^Q=_5B^0 zU1r0!p{C9%*C8N#{LnMHSKEoA;8b}A)ls9z&J4G=^&*FLwJFrM=E|}_Wy zv<=l_v`V*DEjMXY5PS%>r$617=^M_Voug(oXNGzPyOHr=Z9i>pHETepe-!Q)^?3GPQ}luPe6Bu7QyOQ#m?}(#L1fdxkU= z;^W&LLk1Pd_lB&YQy)Y+2RbN$d4+3(f#{dIV5tV%dUI=cbtgXaTv{>O(KF!sqU_Mi zz%fud-(JB~whd?Oh@Y-+HO;QGVO2Mq2ZlNtGW}hsuT>Qr7N=8HHO^%4i56@zjUYU|Kwzt?$afZi`lTLz6v8! zJ9-JP+cyn^_>gvKC~GXlQp5jc?Do8Z((p_BB~biu`#?Xc#OT22Fq@3+d^n8Rlv-7L z+R3ERmNQ*LZM|MkTR&WZ3Cxa+t6^Je0^<_LUTF$b8gwAlA)y`0(e3#~UtNoCtu$TR z(5hYzI&i~&uxj?9`nrnA23xbC#WoIGTUs)09h~2+Yp#)g-DC+pl{Y`aqw|oRXSKFe zY)I9z$Ma%yqrGX#3}!}pI6tdW|6d=d2~GVObeE~NzCnI!-Bht3_cNe=u(hVDEM2pK zf)=#C4mU8Rdxp+56_vDu1I#Wq7^|YjrcE`bs->#g_P&*__eC{C-|F?!tX0{RQ>j}6 zT6HZM->_iIu)eH)ai~J5srPQDJ~eG^?dikNb5?(Q_YkIeXSdn;Cn)7IYN6zGl9O?P6jc6b=qFW zU}}?YfO?EewDo99n%U0@fQ194V6NJkMyED9$f$$U$u ztAc81ZME~nwU{n)W>XrrDDx)mHJBh{lImtC&GoxDDO=po%$8}hJmTi;!yJmCc^t8$S769xmeq1vHmC*LZnkxcx=Yuqo9cSBwu)X%V){ApK!jy3La2~^7c#)P zPq;%|*Hnuc82^{q|BDS{RK-qp(5GqLf)C_>eG~&G7sn&4FY8h#wiv2pWEbYl>^XPU<9})}lR;5){cKCYwS1Er z-R6a6=d`Sc8ulvNMmt(qY1s7aI8PmVTC3{Lv~RcnhDZB2)5Aos8$;_7`+o&y#kN1! z`lF1qk=lw@uI<@x;# zndS0q1zPNeZ5&)pi(NIiN>i7rhst`k4Ox|KYU>@%7-~JUYa}@ItEzL-$mWT*g?)!D z(j7Vi>I5ax>XycC;-?OnQC9S#yXnJ%)fS&!&e;}pTw1d)4qgMjXStOtRiZ(rDwV2f zuyfSquAH2vP^qW|PU!vZ2#j0dHH*@z)HhYtwhfQiI+yLQnQ$$+avGec)1WTvTdNw; z!d3B9J}oDjrc`rHO*J|#tfW?iMow-k7`JTFbl9oLO~zPz+?uGSqbp--8!A$DE}zgT z8!vR~r7k=1^wy6Up;#BC!TPHDiiU=bm`|Xm!oM>9Tg-n;_-`ryEyL7gc%XOGwvLTU zH`yxLg5~xOH#nHo&bC22JZo+4)o!E)buXPWYirrEp~m3*m$(b#h6R_Clq=pkR=n&~ z+zW_Z=n^!BUBS-4Zc|lp?YhI(KV;n7@lmOB9}K%Zwxyy5uvKazuarSgD8Bv7qr)C6DcE z9~@nUZ_q+NaBSalm`A!t`?i6duwRtOMY(CUgEjgtTgGUU1)u(n*v)M^zMLmb@ z$`qzN>Ns4X{DZSco-RXn9*Ln_rg+B=+S>_Ro+j>-ye@7C|1TnCPd=5^pK z8WaY$TLxQpRbm3$Jc4~4>{Qr97%jCqgkp;~br!Z>`fQ5Qn#>HgW_@vM!S1_a5|_(z;da5Os9+aZ4HaPq#jJ262`fYF zx!L^G*FuY!PucMSu1dX~;p1Gh4eVHsS$WusTGBnxmnrGYbhMQ;);G77w6tN(-Q11E zet%DU8UyoiW~j5RJ(C`4Lo+W~o9WMB(8BI=b5&)?F>KPq1DzwNaxNPzSS`(=Zm!K; zmz?TFMy+zHYS&^8jJ;#q$Ef$WGw^PF6yOd-42>azQGZpX5*t-r0y z>fQxnXGiD~P_Y;uRhc^%<07mTgEj*y4R(m=BCsW9w*$Sh!9MHINHRNb$AE74>%1vE zYHN7Tik=4*#~Y)$x23t4H?%bl4>k`BkK|NGSF_Z^xmh^nUMlF7wHC8|H&sw8uuF37 zu47lPx`8XxR25X}vSPKX1Zgnl7~uL<%;|Ec$ad!Csm#?r`!ay-b6L8&!rRnDDKlYi zl<|`2DseaVVb~{cZmGu`5p2R?LCBX0uxf2;N;g()*qUy_O2aMYf-@bBIGdaBUIV%C z7c(sBoW+c_z%a|bTr3%TxJTLWGjKo5gQV>l}FPf?zM!^&1c zZtOOe=4{5N>ad)sc9Rf)dqXoNu6DW0wW+oR6At_@wg1b^t~A~qU>}Z2LwPi9M*Bsn zV4Z7A1tsXh%FZ{vmFxB;;mJ%@rrqY&fByvEY+KH+x7*=Wu<(48^&N@8vcR8ZTdgn% zzADSDeF~dXAiG`e<`pjK8%%?@>+i+pHk7=oo2@><6+bNln;=y+^_#dai|ALRTU*wq ztD4aNqwCU)-)#zKcZ2P;1rwgOKCiB+Xi*3GPRC#S)N}3QZ-D5$yVsrs4O=+iWk)t!LU5- zfYQp%i=16bj1u-sOjDJ$J=o0h(nJsTjhDCohJfs3+bdW%O+a<=*0!1KIum8icM*Pj zbiGDhTW@Dh&%rI*s>W(JS>;3%DP{a)=I0Hm8apL0?c5l$^;_9f!*Wt2ICojcoV&u} z$hw_jdwKARiYs7znW+Y$zP4SOqNkdx>uWJkxo(eJ$#~7zRApPqwoE79_n0~_RSm5e zd~Ek`5SixG}rc< zb5+%@W`n)~qeiu3lcSX+6H_ySr@fOX#PZME#8 zUOe5v{o<_q)~4lYWgPZPvi8_BvoYK-SNa;Mum0; zhM6o?FYl##yLQa^(gbsN^kFqM>$PKHr-|P7j6E&k-leo`QKNO8A`-?ju;(ShlOkAl zWop~7nsbT54nipDq56USmu7!Yj)Rm9ygI|TD0Vy4U@sV3ky`e`JKKVm1+_h$18#a* z6L?WX2f?12+Ek^pbpvm-@WQ0sZ79=maM~E?{k4>U3-1k$-xYD~I`#+xoR(q2&iaaR z)QXz9JcJ^NfolGh)mSyKad8%dJa|p88GC$~ zl|eU%W@Kof7lUiMmG2F0EnXH<11At%WSUwno7;NTFLM)xhjeTaW69Xs)4tsqkV@C@ zmQ|i;uTuaTC&2IZI`v$X38N!mKx_%RL zKiuAG&rvisRbwKsVW6L50&VK?!o?}JXD z^6b+JQ`1!C4~Mon<_azxT}8w)iozzu@a%<4uw8oVRmLt?8CXM^5_brV)x}n(@Vh-M1d#g;JR@WWO&l(=uLn7Pd&;V> zsKk~zH$QF5Q^*)+g7d%dyTH^&yxUBruos4R2Yu`TybT?WI9OYG3DnA*GaR;mTY>E9 ziWa+7&$mc5SahRf!lc+b!J8}|)5_NA>{QQgN`@!9c5l_CG-nUC%d0I<;W*y z&Mg&dYf?@pIN{S;XVz7t@bM4tfU2>lgnvuCl2qe&S+xg3Tv^}@%HlH38B{-PJqxZj zyxDQ4zayn7gPT9dLne)r4GaTQ1X=NYhE*TuhS)gotsUU091Qn%5$dh&-1H&0UIx3J zbh@G1Ht6c%5wC3gn#QF{eVLA6Wp|$$V=xTV8SnK~bqmgjp>?>OD7R3vyPQam-RK0N z*}!g|1{8R~>k@SCZuZ5_y?eN$)Nt;giGiwyckGXIBy^V?O&T$pU@zO&sI;40YoMY#g6XKV}9(CeSCCgjvM?5s#np zB}Suti_wU-mecFmUcDP{DA5JDZKyh|*0|Yc4^_Gm6mv&xP?ov$V7=nb0W>yJ&zM%` zR*@=o%G|#kJ8R;~#m#fFufMZ{cv&jg7~C$MZ8)|S;81IQqbA<024faxJUoc{tIbra zJG)Jm9bBn#HycOKsDkvC8e=94e4WibaFx8BO!*BLd9%9-NRlcm^nh+y@3Sx%<;<;l zIEAt6C8KJOYq9F*(DtiqHq@i!tE-weqKn3H?|KOju-_BCI1)`4eD9$`Q!yzRH-GrY$`N}ot|WfY1JPWR zwwEiczUcbQpo)9 z_O7S!P+2%@PvYYEC3%;|E^{uUrxhY0L3dA#@9xz933ox=@kfoMn~K6@bWLG?u5Pc- zk)KC#j_$9_k$>QQ%lV^8A^qf(!=N92PT6g-W$Kq*67IZ+WUS#4!jbVEU5Uge}5d2c}8?Zoys&0%dX{%}-C_Z5XNN1|UZD4d0$a`Ml#A)mHA z1oN^YU>{6dAnpZSiaRKG<%<5GqHw_(J1CFgv&X>;-^3U+;+J?(;R9C;KO)37IKC6+`ZF9h9!X1U2{vXTwp*H+0X7&sD-_M*5G5xcj zk3vrW{%@N(_kNvq@;TY`?FZNX6*K#X!r$NikQ$vQQIt{08GiPcEam>BY!FU9C0p$K zXC-`ynW>@hr;a2Wj9_~NlDQ1ocg@1(k6YLp2$Lc8LOyBw0`gH_M{)Hc*3;ADQ z*g?`i`}`>6^gkK5yPW%Jo>B7dfI0h!hnP7!6#mgRJWL67Ik_L6lh-i;_Bz^ou#91L zms_3-%>=lmbIv28kTboHW%Ii*QX8J%A2T)n z6*G&i+_zcmKjJBd-aR*eORRf8R`&k>6*J31?w5t)U*)sEQGX(#N z;TJt~-LJIn7i69A7eD`5SBwrnpuQvE{V_V*jz-1Ia zM@bFem-Xd-F3vN?%$kt@H6|(lz1II4>;H7m1KbC%n5hi;uQbQXKj&jn$Ql1`JiDvX zd$5e*m)LXlhxg0!&zc#9oc=i%a96eWU>P&DA^)|eN&czRDCG3-*N@te|GJR>I&-T0 zyZqN#{~cLhb=fCA#LT*o|8?dJ`FH)pI_tkX>uX*1$@y;x`EM}05U0DGoO2(~%=kyL{e_c15-?MKSDu_J z{OQ?gnhXE2?6k}IPi70<$)CzjtD3!lEMum{rq8#`{e9k;NrmJo-zlDArZpsQ4aql# zpD)By z%=Cxk{UP~4NInpf4~FFI75yt_&J4-V^o4kenW2z;C?p>a$%jMok&t{OBp(gQM?>-* zA^DDwd}m0$GbG;?lJ5%1&kD)U3dzq7$}OGD<%Lgvdu z<|{+yt3u{$Lgo*J%-4p@*O`ko_A;eY&4p&ITyPFL731OMlIL0TndW0T=27$U9P_aG zl*|lf3hui@=0|1b%wj6a^G7lhQ%$FNUS=2HkomRD5Zmzn5Hi0RGRL!X1?PTh$b4|f zTpThl51DI2<`ZRh>Dz5K=9ov!={e>PnC&@cd`d)SCVMLSEWTOp)2?XP23kW8P`z=9o`2N675*({C2Z?7}&;_iUSrKG%u<;b zTJuV?I!AuISuZmH|EtVaKIo!;J45E(A@fH==G#K%uZPSJ$;_T@syWAeKP3N6$UI4N zdDlOjZ>DDF_OATrh0Nt4b90XWbIs-)^9ANqn5oaZa8JW}W-#Rc!jSoII&6$o&w_eETgGJfdcg*#r+6j(0XJcsxSK2m%L!5WIhk&7G~ln`oY`a0a{@_YFEy z=Oj8;2m@Xf`_5qSoxz}Umd=^{Fi7tpAzmo+j5$7DZ_i4)(+~-3mw!ys|2l-+lfk(MxC0+3 z3VnKs?gAh6wkffvNWIg%r2T-S{eZTA-qbr{P1W$25stm!(3)o&d(6p`WIv7MS+Et@ zPi%Rg+rk-p_ni-|6ZU!LV(g*(+>e3>53BeeQJ@O!hcomICos3v z*st+$hcs~>-FvWS_3il~9a?ecg1vKCS^c=fA;HhT?DH6q3))sms*H8gKcGt+n`kT7 zhZ#L*iX?DMSCV%*3&;kvB6|)fdyLu(cI=0LJW23FYWip=v1Gi@L(&h=%HYGxIw?b& z@ejm%ZtdYexwfaCD6lz4FB15Kezum{ua&d<85!^EDeO@#cifmq*m0PNtwX1zv*(Di zp8$gD(Y+12&u%g5Y+2aK&%VdAb;meSv2!ihL;_#A8+oI6hxm2zA@OnXS@E~x>*7Df$w()|n<;YKrkV3ia*@dSBh4M+pm?A7 zl=!^3K;f+x*NGn$?-0K(Mlpe5_#F2OlI}cEbgoNB6bAw3z&?6d#N4Uy?-w5xz4%|0 z`Bl-&XMy5DQQ3Ho5Lb|RdEFqMCJu>vM4N87v*`vOl>JlU%i`a}eC7x4=7?6Wheyom zOcx^O&ItJh^2mstpB0QFx8)m)%+2JI zh+QW~mqyHIX<%WxsN;^^@J>sn1{$!5%Uy@M)53pLd3j4 zu8Ek}$p*dm#7m{OXs(1Zu-=PSK@TM4(^)>%5i^ghiP$qm1+@{wzNlbr#IExwUnhAp z3ArtI$h%>V)j6kP%_HKu;^pFFVz%F)8Rd|ta+@ilC~P>$x@EJt zP245!5ySPx)(?bh>jwh+9o?;um^Vo@)&%rZ(1?D5+<<_ zL#85la|oiG^FivX^;FZp*w`Xg2eWF*!=>!L;a^ax?e+gaBss$eXgS! z{3^unJtqaBb1Cq=M=1y9y^1=@N8ULyPJ#oNfO zXg}f?#5={i#Cyd1K-SY`G$S4)!N#*ia$8>!-sv#29@})I|Fr!YI;jik4*lazB8Cvd z@wt`6OVb@B{Li8soqm#pc|OQ-XCBRI=^geAH+s6-8{Ds;yiM&4mD-NmaA(^YX!~if zgZ|nT4*c16+97|L2zE#jPN&)*+@DUf{E^-C-=*?|f0iTTwfaCfRu71O2kjA_ZLbLL zGKF)cc#U|Sc)dvdM7tyQ%ofL=GiZNC#GV%^*d8$-qPaI>J}LLNinogivS0ptBBqdL zR90KBV3xM;^IjDvQZLjT2nEjk=AkAqC#Z^@*w{TlhE%u$R-G#7~6x22i;wd5gUF*y_E zN3KKuWNwkUQydg`kgdjW-<7;f{E&E)c)NI~c#rs?_^9|63H=x3F+9{i66LUtL?yk1 zL_T>Yfb;fyNX!%NBa5LIas+xIM%IyUb`Mg4+yj~+wp0ATApEpUA&s!wQ1xHE^=f8R6PK*yE`ll)69Q1o2^}3LR-pfSp zYtmdPa$l3>a0&_coicO(lIGnc#I9o-EELk?tc%_+KRRN}0Ej2(O<+{O5~T z%ARLASgucyD95Krl;hJR^!zM|@_d1W{$D1c-`7d#{Y~;PM7}N~k&o-F+?Y>_w~Kd*50YpXkBU!; z&xfu=u`Fn|k9$zM*hgV4G;WZNN!~VDB1ckSAtIo?MMikC?;B8E!s9d!EoEF{D^lh)}6DpCq0xc8a~?khn|4 z&}IGY5ib`x-ZCBxJ(hNyh51&QKP!Goyi5F+_@MZ(_?Y;l__X-E_>%ZL@ipCqf|e)>%M~Ju%$n_ZiEvSstr=Cya+7$9xJ^V8v2u=& zOb@D#CAt>N^TkWVE5#3q*NdMNZxinj?-ai--Y0%nd_;U)d`f&qd_nxJ_=@;P@lElc zVjjjt=7ZxnIYpc)&Jnq8rF?HZB7KLTydGsGHkqnHs##f!y{h@Tek7QZL{MEs5ThKL`gbMc9Xi#6gV zu}j<~eo(wo{JeOd_yh5I@xMfTgvG`;Rh%a-7OTaLVyC!MyiB}7yhFTKwBtGS`JBwJ zif@Z{Jcj&x82706g&c>#$Dc&Z2P5iF-Bk=|Czr=rv`*B=CJjaO5;-GlG zc#C+C_=xzl__Fv{@$gA5+@)fTxKX@V{D}B<@j3AyV&P;L&JwX&><~x9J>qrZZQ@eN}UE)*XOX3@1qR_>AfVe7OExjRIhFCHTv zCpL&J;ui5VF(aNQUMyZI-Xh*9J|I3WJ}15+{$1pUk(rOASR$?#8^u$_A@Kt78gZ}q zW$_{L$Ks3PA4E<>8Snn$A>y%Oxwu|DN$e4KiI<8W6+bQBCH^n*N%2?WYvS8tA=Xe# z&%xqC@py5ac#?RAc(!w)ivgIq}!xe~AAjz9GIP z?uP{m^)g#LN?akX6*q|)aYVdG{E&Eyc&GS)__+9-xF6Q!jCY<`Dy|Wm#M8t+akqGd zc%%3^@gDJC#h;0YSNxHP->-G`PdrLoA+8lSi5YQJyj;9N{H*v5@nP{N;!EP|V&S36 zueeY=UR*C`#1Zi#@x$WR#BYiZh~E>xFFq;$N&Kt$wwOq|^c*Q3D=rpSiYJS0Vwcz_ z4vS}r=ZTkypAf$&ep~#3_?-Bk;y=Xw=1N~;zqm*Iuz0KZ74bpwhvM_%e~SMQr_FQW z&lMMmCx{!wQ^j8K1LEc44dUm-yTymapNTJvZ-{w^x%i93d19%!Mr;yK6Z^#7;uYeJ z;^)MB#D5ikD*i@%U5w3FI>b70qc|*HC|)bxEPh%1f%vTWd+~2#!Qn2RW5fz^v)CtI zB;G21MSM{Fq4>P`s+fO-3;zJ|2yv-cEvCe6;*fZ~_#N>H@t5MO;y=Xwj&$+O6HCQ4 zVv~59*eC85uMlq(KPTQJ{;T*?@i*e@Vr+rRO$JH>Ovi^LC#SBoDJKQ7)Pen$MF_%-pH;sfIM#P5qg5`QK>C;nRe5AikeEwSJj ztxR?Au=<^9|&=c&{t-7s$$p`HIXB zkb`*dCG(Rc_T~Rw<~PV8>~|guBHgpd)hGv!vTl4W==CG+KEOT=6)^Cw8WH@H>iJ4w7}_@2x^Ch>mZX_WTF>jIcf26ohY!`Qn9}({qpAlad4=i=ztQJobcZr`6zb(Efz9r5rbN(B| zGsSDg&x_v^UlL=Boxg*{a`7ZFBaVpYkY^inf%qZudhsUlb`pC1GKsPLYvMP^X%X`s znI9+7pZt`B`(Khfjrq0scM|U37W0=ld7(H>JdA|9BgIAH5^*(&aI3{SajWE~ik;#a z;;^_=ynsYFmx@=2*Gqnr_-XNT;#WxI?_1=EG53ovkx2K;;$Ovoh>4}n{bX^9IG2RK z!^INWFBOjyYb9SNro_!+nnb#K$usf&C*p|Y=SqIL%vXsYCgJ|e;)7&^F%Qf9jQFbf zcgbVRTzpf=ew@=2XOYOyJjsh?E)$o_zDnk`VgreAy2Z0dq~ko9uOWMkxkctLNq!%R zeE%D{-IyPUKO&KiUr7G%GXGwDP4;ieY?eFsaT4Lo70XDZV};E1B+_w`%w3WXkVwaF zvcs73#eb3g4J6X@3GrU>0r7|8kHu$5g!k`cr!l`5|4Z_}N*-U~!ks7PNG-z455`!CA;74hq`|E|mri{F?1 z&t(3E_^RyxPPXAYAH~>lF1`Da$nSwNA1uz3{VJI G<6$h=8BS@vBrZx;t;zgy<> z#fxQst;`=0KQ8;vk}bx3LA+D)hs8(5Ux>dHUn1e}4HEOczso#hrL#XuTuDN{M&=Vq z%m+8ie5QD@_#w$}Afd0@N$gGBA%2NO`9CB+BK}PLh4=yq|F6jWn)p`|;k_-!j(6ti zB*L8~&XfHDaiO?M@(OXi>`x@8I)#7R5 zZW8tWVseWy9~A$EM1DUden$KP3HSHNe4qFo+5bT1ABoS92=@i?CGic(|0>4TICm4p z{lr5^q+_0Vj94PB5X;3{67e;N&0?G68F4`NqvBcO<&s||UN8GkinoeiBayCeh!2Vn zi9Zm3B>sX#x_%}8M*Oqne-ra6oVxA6}O3<;vk81 z?GVovuaNv|@dnxN6+b23CHXz#cV+*G_?Y;dMjNePL_FGA~KTEtp{HFMG@vq{6 z)z1BK;#To2@dojm;?Kpuh%;)O|0QBd91^b;?-U;+k*}YSQ;hk!_#BCR{k!CU7NfP! zJ|Rvb;r{@c4-%8IUnuh;ajEPpWUdiUl>JHMsm7cpZj-!M@?A3T7B7(fzsP*8_)*#4 zD)a5)=Vkv5neP=Jl>K8eKOz2vM0)-pPFw5Di^WaiPVq+ZUh!G+Z82Hr{8x&ni)WIU zSMQYh3URM^zxbT^Dhc%FPZWztgnyuTuvjd4nOH9SO0iblEcwY| zM)upq0r7mv_lQ@?{yOn`@pF=YQT)32E%6}|>3vjuT>PcvzZU;f_J0!pBIctkslUnM zOcLSE5tCx6pd);=fM3Ui`G=pA)|-eqDS( z{9ob^Nrdwg@#o_2B!5->i}-gj-st>I689IAB=j_2#1}|gbE)`$HFhs>HkJDy$CpS% z5t1V@LZ+HD<2pqdj2bmEm~l&uF&8t;&0ORbDn+^GObDS6MTLV(H-uD3l7xh#C@Pgg zl>hg))@O~~ZqDmJ>t%cI-}5}{x1M#`d#}Cr-p{l)wY+xN5qnVI2U92?h}k%r`p0k* z<^RSRxP}SpJ$|G9(ym^8MXY9OzJ|o17(sal;=3`9^8UnWm_zv^#E;`-%I6a=#8)VP zkNADuO8Eie!+4zX^TgNby{)b19ryr_z&ZFfeuaNx-R|D}?XfQo!KwH%Zo~t42CKz; zdBX56?1#g#$kcXz&aABKPq@g`{`n8_oA?fHr+z0Mq5OON5zk?n1TX)kSkqMg+SmXa zV}z;xw8GY?zvk}F7l%D4A7pAh3e2&NGZaUfTFw*HPshdhwyE|Ta5H{kYQBB=Bju;? z3|8#nwYvgCOy#=)Z^G8px5XHY#RTk)$)@sTU>1&|{!yHOQ*b8E!52;CS%%ATJ@uP# zJMP4N_%(iKD$h^&E0*i2a&4yycoklab@6%(GnJ<)w#2)szZc_Ce_74VpMdb`fhkXCSr!E{5hD9W2qmHlPO<<@0r@ZTTESR+lo6( z^?NV%KT>`Q&tSzwuiX_`&s3g9cq6vNHW-CnO)Vz@AH@EcX)0eH4#9EMPrzp=pN;cy zIrXdXUCKA&7W|U>ukc&^9#5I-#~=6?R_W*UzdF{z5WLBZ(wO(y96Op??@ri-@(dhf zYQH>b&UBnf__V3{W>dcu-@=bgwcl^1>-!VLzY<>{uA1c4*EH3>F>y2EXyOFoG~!I+ zLL7zTa4OC+)&B)%8^>9UOHK8EHT54-{t14DM@+RlhJR3Q14miDa(ES9gV$o1srke4 zHoODxHkGF{cE$eGr(rJTLvT1wpneKIOZhxpfUBr~1J~mw{KQm0KF2Tdd+LA0(|8Uq zP4?!igjF!a)Ot6>n<$UQzNYp|su`*CY0NS;-$T@o!#UKyfG^_frrN)S+bQ3Ld+#m9jf;VAm|C9=)bGTj)c=4#<0a`{ z`||iNQ~By)18h!xB;HGTS4_Y(>IY&zK7@~$%0CV#;2i4bT8v>JQ>Kl>bcp8~#Cg`AjeW1=Zo?n&%4{$1^>{PhiCs*~Pn?b;a56rR zt8kO4_1aDR9sXfzy(;B+%dLyIntET_g19FR!>3I3V=D3U#EXeH<2U%bseI>&FU|Fq zR|^}N$`?i)jvY)LS9fD)%DZ9;<>{D5`4F6dQ*frKd~HMN`;cpKhD{XN(n zdtyIK!CX^$hTw2~iu%bo183tRQ}Zpw*YG{+-^Xo~e}-S+QRDr{V%!gCF94{0S>OmN0*i0~F2{}d86LzR@lUMuFvkIgVk?ZsuJ|Ah!eKZbpTPyV z65qqExEH^}-?8i{uRm8|2;PFXV+{7h6da7BaWc-vCAbDR;ZFP-f57utakSU3n%EGV zVH9@8`!O3w;FCBL7vV}=ho9hn{2tF@dA%33` zd*K6=XAoy$9_6EmAH{K$|C@LQ&Y^q>@iJUV`Fh-r`|&uQ#R`vj>v=7PVhikqeK7+c z!pCqNI-2bFQ{}KSRz+30zeftiTd^5-#;&N#XKs64esI-c?5f4N&c=DT0$1b5_z51u zZ}3l3uf=7`cvis5*Z>=&eiG`o*G~vt_0vCB{Y29BZq$&=Zrm63QKK6V!QnUor{Drp z=d6qIHT(~5!%y)`{0hIp@9-p^!gF{5ue?Od(|fUMSR3nNQ*4QMU_0!C4`Lb)#5^2= z591@~j#sDUPb9X#V`jfgnum*VDZYpA<43q1kK%Fs747enS>6j+wyYOlj#uK<_%94I zbxkxJTVZRo@oufY2R?}XF$1&E#=*7r!*K#m!MUcc1-^hU>t1VAWtc~H=9NSo*u?aTCZs?8|sO3CBoP>ig2Z!Kr zoQ%_O2`hE6?O!Ecjc?+IxDDNLiq(D(u{$oY;uFNb;%U50*Q#y3Dq%IO ziOtc*A+~mHu>;z_Nmqx#vLI1<}p2fP=%U=Qqr{n5rjw)M`!!8i;b#<4gar(zM##(B6Hm*PrXgYTj{ z-lUfQA@Mf+9KS?&97?r2LhO#mtoS7HX*`EzFZb5#GIYmTR(p4xW!aSSmKclfIF_nU zBOZwEc$O+3OFRqb;wp5ZzGC?3aCcm}W639RM20dK(wjKnq=i*eW!@5la_hFLfmhvGjY( z6Ys}l9DqY{Bu>NWxEPn>dfbHj@N0C(8P)bUOI+njZ+)v{Lv+U-Rl7Th+hZ^6i+MN% zC*o9m9v9(T_#S?aU*b>rD^{%H_3sL-i`Qc$w!t{FmgB@@U+jl7aSpoUnX3I_;@9yl z+<=>LH}1tl_znJsXVL!HsP(5D)RF&5wZh+0O72b*Mu^aZl2QUc-V?Kf^EZARfUV@Mru3|H8|vdFxjRYhW#`kBzViHpSN17Gp3L6RJd9`XJi6lnYkOC#>GeAl-Eo0c-k$g_?2G*{4~O7n zoQBWhbGRH=;X2%i?zq8P?m^(ae84t zOuMFbu~? zY=a%K6L!S}Ovg+dg^ywp&ctQ795>)*+>ZzGS3Hds|K;`H9S2$K(SW!yw#K&D6%%j} z=HMgvIL^S?xB^$>2lz3%<0Gpdhlo$(IjmCK>u+^zgg0Va?0^Z_8wX(yK8{b~Y@CNH za5a96pWq?<2Ho+M)&C2`Rj>8>TLT;8&3Gra$6nYMbIpnReGrbsF*wyM()ke1!TGoZ zm*FaW1J~h3++~i}^$t9UNAQ$6ReygB?GM6QTn;N^Rjh?|upx$Gq#3R6%c46DwBi`z zIE=@>*bnn?2tJ9Ea4x=ptMN_TiaYRI{2tGvbDh`Enphi~m@#_aj<@5Tco(|kMyp*n z;vVRZAFc9C;!*f0{u^iD%lIm;$4$5ozs8^OH>{*<0M_3s*uad^_Y?6}Y=*6|ExO}T ztNp#i4`34J<3l(eC*nL@fNO9q?!aC6Eq;$qJ+HszuqM{VaBPk-=1j+l#dz$6{V)Zy za4-(ThjFsm#&M?MES!rk;>)-a*Wec1iU;s8y5nLi|7qfiA>Q(?zGx4s3+rG*48;g+fp_D*n25<(h{JFK zPQgX!j_a*{ykl{=e(#AN;x_yozr@4%EuO*iShazduLjLwjFn)`_n{)L0D74SMEiR8&Vl})L z>tSQO8QYli9489hamp3P631gN%*6s6fur#WdrO=O*IT*cKD8Hx9&X9E;=eS$qy(#g+Izet=)$ zA^Zh@$I6Yp{#V8N*a%zV?RYP`mB$uqED(aTt&3=A}A+!U7zM6VV+{UhQTO&&D_L9o&dpa1ZXspYb<5kIs!= zKdNF4yb*7~<`{|h;C+~g$yk6xvAm<@RMp=#G_^i@8|VH$Cd91lxPOPv5*~-pkbMNIz3ErJH)a%{4XiP*dk4W6UW19bhwB*I`X1n`!EL z!F;ou<18_ibh-I}#%C~-9A}-GqQ|G1<~TddL3*EIX6t%`Iar@_m<9U$%zQ}iGtA-o zuZ+~|fct%)F?#*Ac&ygn9Ix-in-jJEraBjH7HNE3bEcl3O+C-+Cp+%(ri||PD2EkL zo6s$^6l8)7(WQ@QOUQJd=GcGmWeC62>*>}P7bX_L67V|WQ_D!Xcx-TkjscAal(r5556Q~g_p%T2A^DtyBXb)2_xof+mh8*z)N zjj$DWnA#Y-aE}@3IQ#LS*+!p};xRKypQGbRGg{-Q;TbbVe~%d5{jcp+&i0>lj{_ZV z?)Sc=dpz{gc+XZZ-Qz;XUmc63dweA6I*rBBJx)>_C(L5$9xpmBn_Dd1<3`7)zUu5A zr|$8i<22f0=^jTqUSlnmab|%&x4~Yfj$iltWU`;dI*wB?-5jasEzC8?=zTs8HOFfI z;}~i{^@EYf&SINzM9{f|q`IokiY+|={%D!i?%VjX{z%nFXP z&#bKHhjOy2w|%bE zT;r`MhaDf`)ufJ#NW1C8dGXewl1)e|)OG+kTkXNRHL_ zmh5#(+dW$AV%z&YQ`bQs`cK>dzHhK(ktf}Lq7ja)x$4feKra4lti^LPnF?t;&US^I}|A_aP zrs>Fh%{6PV2<2pqrcF4&t$jiyhOwCJ-PtD2= zsO^#vpIDHWFJr=y>v&wJ<|P+5 zExEWw$;B;8C{`~@N}}SDlBl><$w`WH=h%K}Vp}*dHz_YEE8litM3d$LYZ_1)PRFmog+NJ2^GwpL@nVGCCw>CKqNV6{L1ZPfZ?_ zUzioJ47Vtt-0QxMk?!q!bo^)6sR&4*l5QQ_MF*F3?$VPhLAHa^G6n>!URF{@w)-e<;yuvxcy1CKo!CD!BYTi- z2QO~w9ZP-~5g10NrX}X578L4nXpK7*=H&&(vC&NvQ~us0Hag;;MNJcv|1oF8Kg#km zhNtGFrDbHMdP_?ikW-N3-7QGX*D+~bNXtvjFU%z9(4}+dcK7M{aMvU!dq85e|HP$d zrmWnEmR?nd?umi3xw|htH7Uj42yQ`MYI0&mb~4+=+n32XX_-mdq?W%hF>h#MT4r%n z5D=+2u^@|Hx!I!I#p~#^`MMYA(Gk!wx4IxNDLX$aBR@YQCtH0RTv)t<9pVxa^W9l; zGE?ZjUqnar08Q*)nC3-ZM{`s4v`q8(E)n60$vK7D1^)V339Y-dO4QTr#h`y`T23At zJibdSufn!nv!>pCdsN1Diq-?pT^U6kJKpQh-!jpAwy>)BE-lsZ91azW{+^qCk#2KD zdI{1CGO{8f0`AjGD-USWoEG^he%qv!gdcJjR+fsRu-}zRotn*{fAW`mj|u|&r_&&(q2EaA)WV(a(*G58i*h5KdnD_;Mfac4O{cnUJBxK1_P2aG zZE>$Z2zT=H^;Z;_Z(=|`y{#zDr_-#zwaLqI3)=2cNXo0vq87OeDQjdIYwocPj9!1^L?TFf%$TEAcm;SpZxxPrh>qH zyOb|PWtQ(M-K?E$zZ1Fz=9{W~whjHs&v#4(f%#4;-y15ke0tkgoUg2s1?JnMh3rzj zKl%ACs30)kveb+HyIOUA|7r*2Tc(+I_{nHzp?)^_w|rXz@?AqaTVMSdy}$Kuq`os< zQodV)@|_6Cr?;`i{fi087psG*qf(I%+c*6ye!hA``Rp<5Pkz3eJ5l$HJg|`~OG2`9b;m2IOlHkneT!HC35S=~wEyl6Tkr-_}=6oZUgo9jbPf z{U>47``cw_&~h`iTzfxl+xZ6C*?QP}XZjXV;_r$F>SN!;q6ZL-N!Q}JkGCBS>WSx ztn!6uM#~qbo8Q02LHVL}jpvA$+Wp_}UxT203o|Yrr%eL#-4&ECR1ex(0r^zzPW^-0 z*>})l0^0e@wckbtuE#1ZH$?4hJtB1T*Ta4zY1_p=UdAh*o)U^DYiIRO2Q9Zq?b;N# z^72_YDQLO7wA^r&+j8w3z+diypnN-&FIM&bYHYpI)`Z*@?< zI@)+qs`n>9--@7oZ36OHUO(TapnQFm&-TAR`T6Wxjcp(QxElXImTT8`0@tHJ%eCX& z)}ys<{&MX%q=EUiD4)M9HFH$$PWD^Uz;;{JZVPpWKac(PG;p~iwcK>o+j8yv$zN{m zpnOGolFwAVKl%A;s$F2dBgz-5MwTy1H$PuQP(DZ3Jf~WRnf!dW1m&wd=;HouueN@^ zE60r{o}<+JaKmGpc%EhyhI<%?1t+aGo=>~BB&EpOoQV&4^8sCs|$*Vlgg z8@PW@C|^G{vV5_+`S~^l&WP`=pAi~ILJHTLrz4$2p*>%n0GPegvc z13~%5D&J5&_^f|%0r`GVy9$bhJK1Ng_Wa{de!kNsw5#kll773(bSF4pN$qNuvR$JR z+EpuIxy?)2&aSNn_pfRR`FfVJ-M~_|8&%47(@JQkqTd)_ZA;m%b1B>PDWP3S`y-=-cK$lr`f9Ve)36fSm9)MyOWAH|Dch|rWxFjUwDbFJ zE8ySXTgrAPO4;uBQno9r=h)!m%I{NP|7;9^(zL5n%66fpY}c}s?K+gQUDr~!ODttO z8_S?H+r?hXg4>OEk6`aVf18gjp`E=x`;*_!u4e@2E2-U_Qnp)M%62PDXgAjHob>zm zb_wlbN@({%DckKp68s`1%P#3yz_|1>7Q-4!$J8Dzoc`0 zJ!bsL&vz=Q-LY3Se(;TctBZX)8MNHDH|X=|2HtYVtGR6#TW(ohH1u;@mYh9*fB);( zT?opT`E42ZdmVN@^ptLXzM4V#KKRmc*7-@)&c9nt?E<&Us-t?}sBY#9^EC|0x9fYIpQ_UGP1eotUvu)=dqtZLXq>C^w|MvMf6HgLwn6QVwAJ6U zw+2jpyI9)!<(0M2h5kXOLjP`z+6As}4PD3>qZbhCpIuw^``26Tv>A#|!I$fTmj9mF zmSM}a$qan`Ibs*S^afwxb;sZA%&t~HcCBBQWm}k)E!%Qz?Mkx2#@LSaYi)sT$txKQ)LpN3SJDPa ztL&~EnKmJ@;Q;*+LVN-zr6~zbLfXJdaO;E|N}x#^T9QM7BosI_CBLB|;06*CIKlmX z-`v@q6^175zkNqDpLg%O@4owf%$wO6T|2NRY8ZxclA+pFNm6P{yDsr=(r8y})N18F zRdK1Ya@p+JGjE;^eZ{(@VctCbrr9uST-rSEe?UD*)7n#3v}9F#uZ6PO2SQQSf!*w{ ze`eeHPf_E4z<ZUI?u&vXE zwfynLQFC3(Q~&Y2aoS^5)z(BCo}1JW_-oiXMN(%P8_#6^mf+G5p_xWLn6L!`~8aFN340!i5@9}P>{@<8i);yfMXZlv>u zAnW^X#i^pgphL4M_+7xi4#mpvN4$o=lePUTSiv8L#!}WxaACHXcfrVG_Wq?s8HT&UD5giP;J$OyjN9z9@)T`QR+QZa~ANd zQh^^+jEiUmZiR_AA)-If0{`Bmh&6#nX`B|ZHULR^Cq!%v3{uR9*c@m@Z@gEF*rKc? zeNB7V`QWdS_l27nuD`Z@=fT+QK{8crzjluh9n-Hzx!BRkh4k3;b9fGO6L&yiy zXv`mOqTcdY{#uV^Rlz3~(KS#lvN+8(jg@OEzYj66m65gwIEftJA&Tonv;tRAd{>|W zW8+!n4_pMR$_;@XTC52iq!-VDh=a4=<9fbXRgI2<1cZp8mKh5n2n#ZSf98! z>xw5>Gv8!9j0mdw#k$dY8|x)TKkWv^Zi#U_#a8w=Qp7$Ck*|d7vn^EKf2k( zQJ>R~6HOfI%b<+mu={bMmFxUCMR?%k*GUC%yKt5EDju}_lI|pRd zhT}J|G;BXtw$aadTrxP$uYsWF1#KCtgALVYaCz{6ug-`WwFuYKrmCxVK#3cYWYJBl zNtwZ|)fZP^R6W>$i++tFd>3d`SjLX(Y82Q821@+xuy3ixCSn+a4b)V%!Zrd;^&&KY z-Lt`{t}ayw1Y8Yl!Co8OXM; zB>_@g95&uv<8)~)sxZc;a^+xytzHsVZdPczTAtE zT?Soo3`MsbVJ@_5x#^gJsp-);N`U3M|CWkE6J?RGH{T~JJUw_Qvyc(-$>GiVzn?~v>OV@`mEI#7x$=EMbU zDV&%S4z#5xVr5a-JL4UtC}K_s`pKWqcJd2=v+*t*9@TXR$<{rpQ;*Jtq9@rt^<=;3 zNk%}u6AAq|%`%VTVsfvBHfS-^oYAtxcreohP2PE?ecE_Gu}Ei!iDEtbW>FRbijml= zp<;wxZ+}@m89iE-ry7Wc8X@d@v9fyhEvVQY1{sNsaMR>qkRcrKK`_w&A0rIH|6z<+ z^<3-73q95mL6f&zNA4xr{x+`gjBPt3_+VkEQG)iri(h-1-@4RsA7Y3^amg;&)cR4z z5OELGXP#)w#O9gUJtjx*@Sv?Oo*n(~Q;$CdOcljS_84yj1K2e5w!!UVB$rfsGpW>6 z`h5vJhek#xGr3fJIFTzHjYJcLXg-pMMPx3Yi%ez4A`{7EB$1o$n90thJJN}3D=2B_ZpUWIc=kk$}(Y+hHqnqdF-2rq7|x zC6l&xd^|ppo{6V&Mjz>|5!r(#oqejfls>$d~H=oOOK>UBmS4bk&4Ivoa*Lyk4IY(jcg+9M7P!(qPtpeH31h|48yS3Yxo+x)n+d2@s#;G`S!kA z%YA9_9eq6}VMiJob>Don-sAO}mB+Sw&qFv3A@sbpp>4aj1yX%cV%hqTQ|#3(`OH+v zYnZD--pVZ=FJkVU$|kQK$y}3G<5Ss0L5=jsbLm7%^^Oe3k>8ar^d)ks!I|-_8reM< z9gUCn^v3)8=7&{&GMg)e_IRv*QUeLyu;abaNXH-6&L_@5WN7Qq9HI<#2 z2YGgDv(6cvQ@~Y=`AQl^nacT5Trg2f& z>%&>s`WoSS819L|Q1$C=nY*FWAudJTVW+2R*S-UxzOKz7d+QH%cXn^=>g>EI)G?i$ zo!g$o^^>0OnBEMzFgZ6p2985NK6~VXj#Sr$6nRZ{;O?;La=-^VvlFvgPpPSM7qE4w@eSKR)?Ohja)xqV` zQ(Yb1>lQ}Jn<=0E&LZKL(H{qE0;-WpNxaAQ1pUW7A2!PLyyrrH-9kO@-RH7@J3nrH z2z8yrdwox^<~s9ww9pgmOjQMIdhlS;!(R{y-foq#7FqA+fsVb(7pT}<>8bM9TaCtI zV~N>pEH#!HEyfCiZ~w~PmVle?0s7P}-q z%kjarluT8Mj9ODID-~+F6scXlVnKOmfm|M~iP_`2a}uM!7zgK)*F-($k8kmv#BzR3 zVL4}}9_P5ooYQ*D&jjcs+8@P1d%L_w9dimnmVXQf%Xy8|V|@P#bP~(&6@k}r9c#Gn zA#M5zz`g&qrR@9rxi)$3c&?kT{m7vAYm~@c5IOe)g?oqYkC)v)-1oWSURvI){T$LS zkIC{=XSGrx^u>dzm;9)C{<-qlf$r9}UpR*thxu1?BJNh}?NpgbXY3jzH` zDQCO1iwgNVgK}E<9^t(3TH$rVj|y)Seo6Qb!mkPcS@@{%d%_DWBz#HOWZCukx|@DB33rm%lKO?a$@7#tBuoh3E1VPZ z6*m1`FY-;oj|)E`ypx38y(HTCC*jk=pG)}}5{vE);aL)KGfDObI82(qx)0g%_RJPTKGBPJyQNn67`-SvFSW1 ze1=55mxZqgUz2hJdl2pGNz`9KqE9P@Ye>}JEWB8_Q_67}>Uqa>YU=$3>wx<@*8}%G zl6Nt(O^B^Z%bmha!rj6>!V%%+!Vd|r7yg;>Bf?J#KP~*c@C(8RgUBZ3BnD7eWAz?~5Db)KH+RKZ4TzG?! zUm+RK-wIC(za;#s@N2?HgpUfJ6h0%=`yc%MROFY0zZAYMd{e0RM_gz1+}FTm!WBY( zs-*rx;dWt7hM92e^Q3d%nqvcA7S*7q0iQ`BQW`i$@%p}xOB&+nlu|CaCx;giCD7ydxV z524)8ek;T)G%Z&O_5B9tc)S z4}fk5&1(8d)YJPTsP{+I=QA(;Xut5I_en5BJ^Zx^o&9nHWn7O3c)cN>TS)kOiiDpt zB4fvw8Q?<4`dxT>i3JR_h0z=1CbAt@K+Fdoga%XIpAzD#33$Cs(> zS0P%J%Q6}^FK?uDbYZ?=v7<|+$L1#RQvxp;!*)I~HkL~tahKvfrCUto5;GI{cM#ox zUFWTusmx5;@rdD3;beAtI*s>0u3F={#59b0Vtd1hLLrwKn=8QW?~$-v`B<#iF01k0 z>P}b^I%d8lzX2%R{$7MXUQhJL>(}v@K;G@|gOJ&dlbmrm1clq5g^QAQ^hY}W z=8$*$yAg654ktPO-V24>Uk&{6`lml!dPRRXAn*2fH{^5qI}W|uUyI9MjmzI(Eb#Xj zWR9Ve*bk;#ak%|$fWHuQj4z18>F+(rGd`zZ?GU)HILYz%H&D3!?Sa2`=;)9AcKq>K zjQ&g?9}8XEP_yvh5Hq!Skn+oU%utaJO4Py9d!2+r<`GZ1)-DojS;>8!)Lq za4DSZiwo=~xldy6bdqEDJQVJBza3KQIcb+~dz}8hfxJ@(S#>w|)!ocUa?1EGLT-O| zueR?i><8Di<1dH`P93^<75=s`BgrYNLdNay$MAO;HuQ&|mPLP|1^zZ*vVQ4IHtZaK zEerhhud(kV^oJoY`r9D>I-z4)fk}AHwDUaEACJuo?3$L?dk$@w9J_w8v$fbiV8?63 zNgNlZov?HFw}AK#L(lj^IGpk0y8(nV3zbeU!e6%|fGF09bPaCApi*=dKF*>(lw<=vfk+mYRw zb!L{fSfqS^6-7WHh99UX{LpBOMj%4`Q4$g{!2pRwj7`*N3=oZ|7!3G4ciwmQ-m`7= zzuxUT&wb84_ndR@x%bYzx3>(A4#i?IiAqemWuA%r@odx5(Qlwz*2CfUQ3e26W1i=22+oA=jd zg3VJw+25SY=1ZFkez{W1@2@p$)ykw-oSSF_^(lWc@alfquWud>szKdv*6Ln9y+bKO z;x%eh%>#Ztkl|fpU8!PMZ?eBv3PB@idLw?dJRQ{KLzFN)IZ>RcF0}fAKT(kwr==rZ zt2cv#n{orPc-bkrCH9!myr3kUQw6!gpIs8N$fjuRP(3<~#@e=4hn$M~=@wsu`o}H) z5!5fRc)N;9LQatlwg7xSdu%wxX-&XeA0#IKrUhxYN%M?FX@lA?fu6R!IYZb36ewX5p zD*kQ7f2{aRioc=wpA>&z@l}{eh}!dcvEpgPuTi|A`2C81Q}G`t{-WY&nfOQtyTOY#kVOws`zz^&nSLG@rM#oAcvEp%-;~i>Z8lw-J(TgAezsa^35F`u(^m)e+C-xv+3HjU^1!2}tS`$x zZ+5D>Cz!;~$A)BrDSvKy{%4`rsFYzzyhaP~i_|b$@&bOkKO?;WKWHa!km8|6Gng>} zc;0knV$!2i&#%}0Lo(x6s2gggEMvt~q2y>7$wD0`V$NgF7SEj*uJzQkU!Sp~++7;>hKdXJ0ET>N zH0wQ%Gt&}IyW`U|*wgOJnQ3*W-CB|Zc1S}xXNeUvxg6%(+O)9cED_9^6Ui8+%yCYE z(*qW^dYP2t2QnuNgx7nL9T~};s4RVF!YsKHr6qTQ9V|JA52-$(uyuMD?z&!Y;jW|1 ziPCgcyDnS<)(l&*IrC=8om0V*J9B8(s-uaG(zkF|Kvb|Z%!o#c-eA7R+dWn~NlSLu z2^#cNg_i8GrSZjO@xm_WYhx%sX18+bxI=>AQdr7lnRtfoA+(9QuWl z@w+MXi(rl4&0_8e)Ka2bmZ$SQu z)5t$@2Kgsek$)mC2lK>P-^4E=-^2%zZ{nAcZ{kD9H}PTQoA?Ow zP5cV-O~j?>yTnJu+~39*i6A8s?-W@~ToLZumEpc!74F;B;l2f)O+Dbc5HBQR-($-f zGX(d! zN%tktC?@r*q|vT4>fVj!U9;7@%(pbWAXWpLSE^GrI5KVi#6&%~(QftYesx~}_bmlP zXtzd4BJ_XOyjt5>>b9$ zbKTM&mUP?RZKy|mP?Zk&oyv#5007TaXfZDUV~rmOO69uwe9zNsMB^7`w`f?2Rtfl 0U) + 133 .loc 1 234 3 is_stmt 1 view .LVU20 + 134 .loc 1 234 51 is_stmt 0 view .LVU21 + 135 0004 0E4B ldr r3, .L13 + 136 0006 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 137 0008 4FF47A73 mov r3, #1000 + 138 000c B3FBF2F3 udiv r3, r3, r2 + 139 .loc 1 234 7 view .LVU22 + 140 0010 0C4A ldr r2, .L13+4 + 141 0012 1068 ldr r0, [r2] + 142 .LVL2: + 143 .loc 1 234 7 view .LVU23 + 144 0014 B0FBF3F0 udiv r0, r0, r3 + 145 0018 FFF7FEFF bl HAL_SYSTICK_Config + 146 .LVL3: + 147 .loc 1 234 6 discriminator 1 view .LVU24 + 148 001c 68B9 cbnz r0, .L9 + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** return HAL_ERROR; + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /* Configure the SysTick IRQ priority */ + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 149 .loc 1 240 3 is_stmt 1 view .LVU25 + 150 .loc 1 240 6 is_stmt 0 view .LVU26 + 151 001e 0F2C cmp r4, #15 + 152 0020 01D9 bls .L12 + ARM GAS /tmp/cchM4bQp.s page 8 + + + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uwTickPrio = TickPriority; + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** else + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** return HAL_ERROR; + 153 .loc 1 247 12 view .LVU27 + 154 0022 0120 movs r0, #1 + 155 0024 0AE0 b .L8 + 156 .L12: + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uwTickPrio = TickPriority; + 157 .loc 1 242 5 is_stmt 1 view .LVU28 + 158 0026 0022 movs r2, #0 + 159 0028 2146 mov r1, r4 + 160 002a 4FF0FF30 mov r0, #-1 + 161 002e FFF7FEFF bl HAL_NVIC_SetPriority + 162 .LVL4: + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 163 .loc 1 243 5 view .LVU29 + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 164 .loc 1 243 16 is_stmt 0 view .LVU30 + 165 0032 054B ldr r3, .L13+8 + 166 0034 1C60 str r4, [r3] + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /* Return function status */ + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** return HAL_OK; + 167 .loc 1 251 3 is_stmt 1 view .LVU31 + 168 .loc 1 251 10 is_stmt 0 view .LVU32 + 169 0036 0020 movs r0, #0 + 170 0038 00E0 b .L8 + 171 .L9: + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 172 .loc 1 236 12 view .LVU33 + 173 003a 0120 movs r0, #1 + 174 .L8: + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 175 .loc 1 252 1 view .LVU34 + 176 003c 10BD pop {r4, pc} + 177 .LVL5: + 178 .L14: + 179 .loc 1 252 1 view .LVU35 + 180 003e 00BF .align 2 + 181 .L13: + 182 0040 00000000 .word uwTickFreq + 183 0044 00000000 .word SystemCoreClock + 184 0048 00000000 .word uwTickPrio + 185 .cfi_endproc + 186 .LFE145: + 188 .section .text.HAL_Init,"ax",%progbits + 189 .align 1 + 190 .global HAL_Init + 191 .syntax unified + 192 .thumb + 193 .thumb_func + 195 HAL_Init: + ARM GAS /tmp/cchM4bQp.s page 9 + + + 196 .LFB141: + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /* Configure Instruction cache through ART accelerator */ + 197 .loc 1 139 1 is_stmt 1 view -0 + 198 .cfi_startproc + 199 @ args = 0, pretend = 0, frame = 0 + 200 @ frame_needed = 0, uses_anonymous_args = 0 + 201 0000 08B5 push {r3, lr} + 202 .LCFI2: + 203 .cfi_def_cfa_offset 8 + 204 .cfi_offset 3, -8 + 205 .cfi_offset 14, -4 + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 206 .loc 1 151 3 view .LVU37 + 207 0002 0320 movs r0, #3 + 208 0004 FFF7FEFF bl HAL_NVIC_SetPriorityGrouping + 209 .LVL6: + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 210 .loc 1 154 3 view .LVU38 + 211 0008 0020 movs r0, #0 + 212 000a FFF7FEFF bl HAL_InitTick + 213 .LVL7: + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 214 .loc 1 157 3 view .LVU39 + 215 000e FFF7FEFF bl HAL_MspInit + 216 .LVL8: + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 217 .loc 1 160 3 view .LVU40 + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 218 .loc 1 161 1 is_stmt 0 view .LVU41 + 219 0012 0020 movs r0, #0 + 220 0014 08BD pop {r3, pc} + 221 .cfi_endproc + 222 .LFE141: + 224 .section .text.HAL_IncTick,"ax",%progbits + 225 .align 1 + 226 .weak HAL_IncTick + 227 .syntax unified + 228 .thumb + 229 .thumb_func + 231 HAL_IncTick: + 232 .LFB146: + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @} + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief HAL Control functions + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** @verbatim + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** =============================================================================== + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** ##### HAL Control functions ##### + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** =============================================================================== + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** [..] This section provides functions allowing to: + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** (+) Provide a tick value in millisecond + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** (+) Provide a blocking delay in millisecond + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** (+) Suspend the time base source interrupt + ARM GAS /tmp/cchM4bQp.s page 10 + + + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** (+) Resume the time base source interrupt + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** (+) Get the HAL API driver version + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** (+) Get the device identifier + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** (+) Get the device revision identifier + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** (+) Enable/Disable Debug module during SLEEP mode + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** (+) Enable/Disable Debug module during STOP mode + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** (+) Enable/Disable Debug module during STANDBY mode + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** @endverbatim + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @{ + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief This function is called to increment a global variable "uwTick" + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * used as application time base. + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note In the default implementation, this variable is incremented each 1ms + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * in SysTick ISR. + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * implementations in user file. + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval None + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** __weak void HAL_IncTick(void) + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 233 .loc 1 291 1 is_stmt 1 view -0 + 234 .cfi_startproc + 235 @ args = 0, pretend = 0, frame = 0 + 236 @ frame_needed = 0, uses_anonymous_args = 0 + 237 @ link register save eliminated. + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uwTick += uwTickFreq; + 238 .loc 1 292 3 view .LVU43 + 239 .loc 1 292 10 is_stmt 0 view .LVU44 + 240 0000 034A ldr r2, .L18 + 241 0002 1168 ldr r1, [r2] + 242 0004 034B ldr r3, .L18+4 + 243 0006 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 244 0008 0B44 add r3, r3, r1 + 245 000a 1360 str r3, [r2] + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 246 .loc 1 293 1 view .LVU45 + 247 000c 7047 bx lr + 248 .L19: + 249 000e 00BF .align 2 + 250 .L18: + 251 0010 00000000 .word uwTick + 252 0014 00000000 .word uwTickFreq + 253 .cfi_endproc + 254 .LFE146: + 256 .section .text.HAL_GetTick,"ax",%progbits + 257 .align 1 + 258 .weak HAL_GetTick + 259 .syntax unified + 260 .thumb + 261 .thumb_func + 263 HAL_GetTick: + 264 .LFB147: + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + ARM GAS /tmp/cchM4bQp.s page 11 + + + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Provides a tick value in millisecond. + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * implementations in user file. + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval tick value + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** __weak uint32_t HAL_GetTick(void) + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 265 .loc 1 302 1 is_stmt 1 view -0 + 266 .cfi_startproc + 267 @ args = 0, pretend = 0, frame = 0 + 268 @ frame_needed = 0, uses_anonymous_args = 0 + 269 @ link register save eliminated. + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** return uwTick; + 270 .loc 1 303 3 view .LVU47 + 271 .loc 1 303 10 is_stmt 0 view .LVU48 + 272 0000 014B ldr r3, .L21 + 273 0002 1868 ldr r0, [r3] + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 274 .loc 1 304 1 view .LVU49 + 275 0004 7047 bx lr + 276 .L22: + 277 0006 00BF .align 2 + 278 .L21: + 279 0008 00000000 .word uwTick + 280 .cfi_endproc + 281 .LFE147: + 283 .section .text.HAL_GetTickPrio,"ax",%progbits + 284 .align 1 + 285 .global HAL_GetTickPrio + 286 .syntax unified + 287 .thumb + 288 .thumb_func + 290 HAL_GetTickPrio: + 291 .LFB148: + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief This function returns a tick priority. + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval tick priority + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uint32_t HAL_GetTickPrio(void) + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 292 .loc 1 311 1 is_stmt 1 view -0 + 293 .cfi_startproc + 294 @ args = 0, pretend = 0, frame = 0 + 295 @ frame_needed = 0, uses_anonymous_args = 0 + 296 @ link register save eliminated. + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** return uwTickPrio; + 297 .loc 1 312 3 view .LVU51 + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 298 .loc 1 313 1 is_stmt 0 view .LVU52 + 299 0000 014B ldr r3, .L24 + 300 0002 1868 ldr r0, [r3] + 301 0004 7047 bx lr + 302 .L25: + 303 0006 00BF .align 2 + 304 .L24: + 305 0008 00000000 .word uwTickPrio + ARM GAS /tmp/cchM4bQp.s page 12 + + + 306 .cfi_endproc + 307 .LFE148: + 309 .section .text.HAL_SetTickFreq,"ax",%progbits + 310 .align 1 + 311 .global HAL_SetTickFreq + 312 .syntax unified + 313 .thumb + 314 .thumb_func + 316 HAL_SetTickFreq: + 317 .LVL9: + 318 .LFB149: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Set new tick Freq. + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval Status + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 319 .loc 1 320 1 is_stmt 1 view -0 + 320 .cfi_startproc + 321 @ args = 0, pretend = 0, frame = 0 + 322 @ frame_needed = 0, uses_anonymous_args = 0 + 323 .loc 1 320 1 is_stmt 0 view .LVU54 + 324 0000 10B5 push {r4, lr} + 325 .LCFI3: + 326 .cfi_def_cfa_offset 8 + 327 .cfi_offset 4, -8 + 328 .cfi_offset 14, -4 + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** HAL_StatusTypeDef status = HAL_OK; + 329 .loc 1 321 3 is_stmt 1 view .LVU55 + 330 .LVL10: + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** HAL_TickFreqTypeDef prevTickFreq; + 331 .loc 1 322 3 view .LVU56 + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** assert_param(IS_TICKFREQ(Freq)); + 332 .loc 1 324 3 view .LVU57 + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** if (uwTickFreq != Freq) + 333 .loc 1 326 3 view .LVU58 + 334 .loc 1 326 18 is_stmt 0 view .LVU59 + 335 0002 084B ldr r3, .L31 + 336 0004 1C78 ldrb r4, [r3] @ zero_extendqisi2 + 337 .loc 1 326 6 view .LVU60 + 338 0006 8442 cmp r4, r0 + 339 0008 01D1 bne .L30 + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** HAL_TickFreqTypeDef prevTickFreq; + 340 .loc 1 321 21 view .LVU61 + 341 000a 0020 movs r0, #0 + 342 .LVL11: + 343 .L27: + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /* Back up uwTickFreq frequency */ + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** prevTickFreq = uwTickFreq; + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /* Update uwTickFreq global variable used by HAL_InitTick() */ + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uwTickFreq = Freq; + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + ARM GAS /tmp/cchM4bQp.s page 13 + + + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /* Apply the new tick Freq */ + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** status = HAL_InitTick(uwTickPrio); + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** if (status != HAL_OK) + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /* Restore previous tick frequency */ + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uwTickFreq = prevTickFreq; + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** return status; + 344 .loc 1 344 3 is_stmt 1 view .LVU62 + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 345 .loc 1 345 1 is_stmt 0 view .LVU63 + 346 000c 10BD pop {r4, pc} + 347 .LVL12: + 348 .L30: + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 349 .loc 1 329 5 is_stmt 1 view .LVU64 + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 350 .loc 1 332 5 view .LVU65 + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 351 .loc 1 332 16 is_stmt 0 view .LVU66 + 352 000e 1870 strb r0, [r3] + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 353 .loc 1 335 5 is_stmt 1 view .LVU67 + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 354 .loc 1 335 14 is_stmt 0 view .LVU68 + 355 0010 054B ldr r3, .L31+4 + 356 0012 1868 ldr r0, [r3] + 357 .LVL13: + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 358 .loc 1 335 14 view .LVU69 + 359 0014 FFF7FEFF bl HAL_InitTick + 360 .LVL14: + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 361 .loc 1 337 5 is_stmt 1 view .LVU70 + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 362 .loc 1 337 8 is_stmt 0 view .LVU71 + 363 0018 0028 cmp r0, #0 + 364 001a F7D0 beq .L27 + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 365 .loc 1 340 7 is_stmt 1 view .LVU72 + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 366 .loc 1 340 18 is_stmt 0 view .LVU73 + 367 001c 014B ldr r3, .L31 + 368 001e 1C70 strb r4, [r3] + 369 0020 F4E7 b .L27 + 370 .L32: + 371 0022 00BF .align 2 + 372 .L31: + 373 0024 00000000 .word uwTickFreq + 374 0028 00000000 .word uwTickPrio + 375 .cfi_endproc + 376 .LFE149: + 378 .section .text.HAL_GetTickFreq,"ax",%progbits + 379 .align 1 + ARM GAS /tmp/cchM4bQp.s page 14 + + + 380 .global HAL_GetTickFreq + 381 .syntax unified + 382 .thumb + 383 .thumb_func + 385 HAL_GetTickFreq: + 386 .LFB150: + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Return tick frequency. + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval Tick frequency. + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * Value of @ref HAL_TickFreqTypeDef. + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** HAL_TickFreqTypeDef HAL_GetTickFreq(void) + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 387 .loc 1 353 1 is_stmt 1 view -0 + 388 .cfi_startproc + 389 @ args = 0, pretend = 0, frame = 0 + 390 @ frame_needed = 0, uses_anonymous_args = 0 + 391 @ link register save eliminated. + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** return uwTickFreq; + 392 .loc 1 354 3 view .LVU75 + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 393 .loc 1 355 1 is_stmt 0 view .LVU76 + 394 0000 014B ldr r3, .L34 + 395 0002 1878 ldrb r0, [r3] @ zero_extendqisi2 + 396 0004 7047 bx lr + 397 .L35: + 398 0006 00BF .align 2 + 399 .L34: + 400 0008 00000000 .word uwTickFreq + 401 .cfi_endproc + 402 .LFE150: + 404 .section .text.HAL_Delay,"ax",%progbits + 405 .align 1 + 406 .weak HAL_Delay + 407 .syntax unified + 408 .thumb + 409 .thumb_func + 411 HAL_Delay: + 412 .LVL15: + 413 .LFB151: + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief This function provides minimum delay (in milliseconds) based + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * on variable incremented. + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * It is used to generate interrupts at regular time intervals where uwTick + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * is incremented. + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * implementations in user file. + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @param Delay specifies the delay time length, in milliseconds. + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval None + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** __weak void HAL_Delay(uint32_t Delay) + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 414 .loc 1 369 1 is_stmt 1 view -0 + 415 .cfi_startproc + ARM GAS /tmp/cchM4bQp.s page 15 + + + 416 @ args = 0, pretend = 0, frame = 0 + 417 @ frame_needed = 0, uses_anonymous_args = 0 + 418 .loc 1 369 1 is_stmt 0 view .LVU78 + 419 0000 38B5 push {r3, r4, r5, lr} + 420 .LCFI4: + 421 .cfi_def_cfa_offset 16 + 422 .cfi_offset 3, -16 + 423 .cfi_offset 4, -12 + 424 .cfi_offset 5, -8 + 425 .cfi_offset 14, -4 + 426 0002 0446 mov r4, r0 + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uint32_t tickstart = HAL_GetTick(); + 427 .loc 1 370 3 is_stmt 1 view .LVU79 + 428 .loc 1 370 24 is_stmt 0 view .LVU80 + 429 0004 FFF7FEFF bl HAL_GetTick + 430 .LVL16: + 431 .loc 1 370 24 view .LVU81 + 432 0008 0546 mov r5, r0 + 433 .LVL17: + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uint32_t wait = Delay; + 434 .loc 1 371 3 is_stmt 1 view .LVU82 + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /* Add a freq to guarantee minimum wait */ + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** if (wait < HAL_MAX_DELAY) + 435 .loc 1 374 3 view .LVU83 + 436 .loc 1 374 6 is_stmt 0 view .LVU84 + 437 000a B4F1FF3F cmp r4, #-1 + 438 000e 02D0 beq .L38 + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** wait += (uint32_t)(uwTickFreq); + 439 .loc 1 376 5 is_stmt 1 view .LVU85 + 440 .loc 1 376 13 is_stmt 0 view .LVU86 + 441 0010 044B ldr r3, .L40 + 442 0012 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 443 .loc 1 376 10 view .LVU87 + 444 0014 1C44 add r4, r4, r3 + 445 .LVL18: + 446 .L38: + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** while ((HAL_GetTick() - tickstart) < wait) + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 447 .loc 1 381 3 is_stmt 1 view .LVU88 + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 448 .loc 1 379 38 discriminator 1 view .LVU89 + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 449 .loc 1 379 11 is_stmt 0 discriminator 1 view .LVU90 + 450 0016 FFF7FEFF bl HAL_GetTick + 451 .LVL19: + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 452 .loc 1 379 25 discriminator 1 view .LVU91 + 453 001a 401B subs r0, r0, r5 + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 454 .loc 1 379 38 discriminator 1 view .LVU92 + 455 001c A042 cmp r0, r4 + 456 001e FAD3 bcc .L38 + ARM GAS /tmp/cchM4bQp.s page 16 + + + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 457 .loc 1 382 1 view .LVU93 + 458 0020 38BD pop {r3, r4, r5, pc} + 459 .LVL20: + 460 .L41: + 461 .loc 1 382 1 view .LVU94 + 462 0022 00BF .align 2 + 463 .L40: + 464 0024 00000000 .word uwTickFreq + 465 .cfi_endproc + 466 .LFE151: + 468 .section .text.HAL_SuspendTick,"ax",%progbits + 469 .align 1 + 470 .weak HAL_SuspendTick + 471 .syntax unified + 472 .thumb + 473 .thumb_func + 475 HAL_SuspendTick: + 476 .LFB152: + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Suspend Tick increment. + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. It is + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * is called, the SysTick interrupt will be disabled and so Tick increment + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * is suspended. + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * implementations in user file. + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval None + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** __weak void HAL_SuspendTick(void) + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 477 .loc 1 395 1 is_stmt 1 view -0 + 478 .cfi_startproc + 479 @ args = 0, pretend = 0, frame = 0 + 480 @ frame_needed = 0, uses_anonymous_args = 0 + 481 @ link register save eliminated. + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /* Disable SysTick Interrupt */ + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; + 482 .loc 1 397 3 view .LVU96 + 483 .loc 1 397 10 is_stmt 0 view .LVU97 + 484 0000 4FF0E022 mov r2, #-536813568 + 485 0004 1369 ldr r3, [r2, #16] + 486 .loc 1 397 17 view .LVU98 + 487 0006 23F00203 bic r3, r3, #2 + 488 000a 1361 str r3, [r2, #16] + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 489 .loc 1 398 1 view .LVU99 + 490 000c 7047 bx lr + 491 .cfi_endproc + 492 .LFE152: + 494 .section .text.HAL_ResumeTick,"ax",%progbits + 495 .align 1 + 496 .weak HAL_ResumeTick + 497 .syntax unified + 498 .thumb + 499 .thumb_func + ARM GAS /tmp/cchM4bQp.s page 17 + + + 501 HAL_ResumeTick: + 502 .LFB153: + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Resume Tick increment. + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. It is + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * is called, the SysTick interrupt will be enabled and so Tick increment + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * is resumed. + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * implementations in user file. + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval None + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** __weak void HAL_ResumeTick(void) + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 503 .loc 1 411 1 is_stmt 1 view -0 + 504 .cfi_startproc + 505 @ args = 0, pretend = 0, frame = 0 + 506 @ frame_needed = 0, uses_anonymous_args = 0 + 507 @ link register save eliminated. + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /* Enable SysTick Interrupt */ + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; + 508 .loc 1 413 3 view .LVU101 + 509 .loc 1 413 10 is_stmt 0 view .LVU102 + 510 0000 4FF0E022 mov r2, #-536813568 + 511 0004 1369 ldr r3, [r2, #16] + 512 .loc 1 413 18 view .LVU103 + 513 0006 43F00203 orr r3, r3, #2 + 514 000a 1361 str r3, [r2, #16] + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 515 .loc 1 414 1 view .LVU104 + 516 000c 7047 bx lr + 517 .cfi_endproc + 518 .LFE153: + 520 .section .text.HAL_GetHalVersion,"ax",%progbits + 521 .align 1 + 522 .global HAL_GetHalVersion + 523 .syntax unified + 524 .thumb + 525 .thumb_func + 527 HAL_GetHalVersion: + 528 .LFB154: + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Returns the HAL revision + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval version : 0xXYZR (8bits for each decimal, R for RC) + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uint32_t HAL_GetHalVersion(void) + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 529 .loc 1 421 1 is_stmt 1 view -0 + 530 .cfi_startproc + 531 @ args = 0, pretend = 0, frame = 0 + 532 @ frame_needed = 0, uses_anonymous_args = 0 + 533 @ link register save eliminated. + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** return __STM32F7xx_HAL_VERSION; + 534 .loc 1 422 3 view .LVU106 + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + ARM GAS /tmp/cchM4bQp.s page 18 + + + 535 .loc 1 423 1 is_stmt 0 view .LVU107 + 536 0000 0048 ldr r0, .L45 + 537 0002 7047 bx lr + 538 .L46: + 539 .align 2 + 540 .L45: + 541 0004 00010301 .word 16974080 + 542 .cfi_endproc + 543 .LFE154: + 545 .section .text.HAL_GetREVID,"ax",%progbits + 546 .align 1 + 547 .global HAL_GetREVID + 548 .syntax unified + 549 .thumb + 550 .thumb_func + 552 HAL_GetREVID: + 553 .LFB155: + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Returns the device revision identifier. + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval Device revision identifier + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uint32_t HAL_GetREVID(void) + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 554 .loc 1 430 1 is_stmt 1 view -0 + 555 .cfi_startproc + 556 @ args = 0, pretend = 0, frame = 0 + 557 @ frame_needed = 0, uses_anonymous_args = 0 + 558 @ link register save eliminated. + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** return((DBGMCU->IDCODE) >> 16U); + 559 .loc 1 431 4 view .LVU109 + 560 .loc 1 431 18 is_stmt 0 view .LVU110 + 561 0000 014B ldr r3, .L48 + 562 0002 1868 ldr r0, [r3] + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 563 .loc 1 432 1 view .LVU111 + 564 0004 000C lsrs r0, r0, #16 + 565 0006 7047 bx lr + 566 .L49: + 567 .align 2 + 568 .L48: + 569 0008 002004E0 .word -536600576 + 570 .cfi_endproc + 571 .LFE155: + 573 .section .text.HAL_GetDEVID,"ax",%progbits + 574 .align 1 + 575 .global HAL_GetDEVID + 576 .syntax unified + 577 .thumb + 578 .thumb_func + 580 HAL_GetDEVID: + 581 .LFB156: + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Returns the device identifier. + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval Device identifier + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + ARM GAS /tmp/cchM4bQp.s page 19 + + + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uint32_t HAL_GetDEVID(void) + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 582 .loc 1 439 1 is_stmt 1 view -0 + 583 .cfi_startproc + 584 @ args = 0, pretend = 0, frame = 0 + 585 @ frame_needed = 0, uses_anonymous_args = 0 + 586 @ link register save eliminated. + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); + 587 .loc 1 440 4 view .LVU113 + 588 .loc 1 440 18 is_stmt 0 view .LVU114 + 589 0000 024B ldr r3, .L51 + 590 0002 1868 ldr r0, [r3] + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 591 .loc 1 441 1 view .LVU115 + 592 0004 C0F30B00 ubfx r0, r0, #0, #12 + 593 0008 7047 bx lr + 594 .L52: + 595 000a 00BF .align 2 + 596 .L51: + 597 000c 002004E0 .word -536600576 + 598 .cfi_endproc + 599 .LFE156: + 601 .section .text.HAL_GetUIDw0,"ax",%progbits + 602 .align 1 + 603 .global HAL_GetUIDw0 + 604 .syntax unified + 605 .thumb + 606 .thumb_func + 608 HAL_GetUIDw0: + 609 .LFB157: + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Returns first word of the unique device identifier (UID based on 96 bits) + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval Device identifier + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uint32_t HAL_GetUIDw0(void) + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 610 .loc 1 448 1 is_stmt 1 view -0 + 611 .cfi_startproc + 612 @ args = 0, pretend = 0, frame = 0 + 613 @ frame_needed = 0, uses_anonymous_args = 0 + 614 @ link register save eliminated. + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** return(READ_REG(*((uint32_t *)UID_BASE))); + 615 .loc 1 449 3 view .LVU117 + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 616 .loc 1 450 1 is_stmt 0 view .LVU118 + 617 0000 014B ldr r3, .L54 + 618 0002 D3F82004 ldr r0, [r3, #1056] + 619 0006 7047 bx lr + 620 .L55: + 621 .align 2 + 622 .L54: + 623 0008 00F0F01F .word 535883776 + 624 .cfi_endproc + 625 .LFE157: + 627 .section .text.HAL_GetUIDw1,"ax",%progbits + 628 .align 1 + ARM GAS /tmp/cchM4bQp.s page 20 + + + 629 .global HAL_GetUIDw1 + 630 .syntax unified + 631 .thumb + 632 .thumb_func + 634 HAL_GetUIDw1: + 635 .LFB158: + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Returns second word of the unique device identifier (UID based on 96 bits) + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval Device identifier + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uint32_t HAL_GetUIDw1(void) + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 636 .loc 1 457 1 is_stmt 1 view -0 + 637 .cfi_startproc + 638 @ args = 0, pretend = 0, frame = 0 + 639 @ frame_needed = 0, uses_anonymous_args = 0 + 640 @ link register save eliminated. + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); + 641 .loc 1 458 3 view .LVU120 + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 642 .loc 1 459 1 is_stmt 0 view .LVU121 + 643 0000 014B ldr r3, .L57 + 644 0002 D3F82404 ldr r0, [r3, #1060] + 645 0006 7047 bx lr + 646 .L58: + 647 .align 2 + 648 .L57: + 649 0008 00F0F01F .word 535883776 + 650 .cfi_endproc + 651 .LFE158: + 653 .section .text.HAL_GetUIDw2,"ax",%progbits + 654 .align 1 + 655 .global HAL_GetUIDw2 + 656 .syntax unified + 657 .thumb + 658 .thumb_func + 660 HAL_GetUIDw2: + 661 .LFB159: + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Returns third word of the unique device identifier (UID based on 96 bits) + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval Device identifier + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** uint32_t HAL_GetUIDw2(void) + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 662 .loc 1 466 1 is_stmt 1 view -0 + 663 .cfi_startproc + 664 @ args = 0, pretend = 0, frame = 0 + 665 @ frame_needed = 0, uses_anonymous_args = 0 + 666 @ link register save eliminated. + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); + 667 .loc 1 467 3 view .LVU123 + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 668 .loc 1 468 1 is_stmt 0 view .LVU124 + 669 0000 014B ldr r3, .L60 + 670 0002 D3F82804 ldr r0, [r3, #1064] + ARM GAS /tmp/cchM4bQp.s page 21 + + + 671 0006 7047 bx lr + 672 .L61: + 673 .align 2 + 674 .L60: + 675 0008 00F0F01F .word 535883776 + 676 .cfi_endproc + 677 .LFE159: + 679 .section .text.HAL_DBGMCU_EnableDBGSleepMode,"ax",%progbits + 680 .align 1 + 681 .global HAL_DBGMCU_EnableDBGSleepMode + 682 .syntax unified + 683 .thumb + 684 .thumb_func + 686 HAL_DBGMCU_EnableDBGSleepMode: + 687 .LFB160: + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Enable the Debug Module during SLEEP mode + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval None + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_DBGMCU_EnableDBGSleepMode(void) + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 688 .loc 1 475 1 is_stmt 1 view -0 + 689 .cfi_startproc + 690 @ args = 0, pretend = 0, frame = 0 + 691 @ frame_needed = 0, uses_anonymous_args = 0 + 692 @ link register save eliminated. + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); + 693 .loc 1 476 3 view .LVU126 + 694 0000 024A ldr r2, .L63 + 695 0002 5368 ldr r3, [r2, #4] + 696 0004 43F00103 orr r3, r3, #1 + 697 0008 5360 str r3, [r2, #4] + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 698 .loc 1 477 1 is_stmt 0 view .LVU127 + 699 000a 7047 bx lr + 700 .L64: + 701 .align 2 + 702 .L63: + 703 000c 002004E0 .word -536600576 + 704 .cfi_endproc + 705 .LFE160: + 707 .section .text.HAL_DBGMCU_DisableDBGSleepMode,"ax",%progbits + 708 .align 1 + 709 .global HAL_DBGMCU_DisableDBGSleepMode + 710 .syntax unified + 711 .thumb + 712 .thumb_func + 714 HAL_DBGMCU_DisableDBGSleepMode: + 715 .LFB161: + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Disable the Debug Module during SLEEP mode + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval None + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_DBGMCU_DisableDBGSleepMode(void) + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + ARM GAS /tmp/cchM4bQp.s page 22 + + + 716 .loc 1 484 1 is_stmt 1 view -0 + 717 .cfi_startproc + 718 @ args = 0, pretend = 0, frame = 0 + 719 @ frame_needed = 0, uses_anonymous_args = 0 + 720 @ link register save eliminated. + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); + 721 .loc 1 485 3 view .LVU129 + 722 0000 024A ldr r2, .L66 + 723 0002 5368 ldr r3, [r2, #4] + 724 0004 23F00103 bic r3, r3, #1 + 725 0008 5360 str r3, [r2, #4] + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 726 .loc 1 486 1 is_stmt 0 view .LVU130 + 727 000a 7047 bx lr + 728 .L67: + 729 .align 2 + 730 .L66: + 731 000c 002004E0 .word -536600576 + 732 .cfi_endproc + 733 .LFE161: + 735 .section .text.HAL_DBGMCU_EnableDBGStopMode,"ax",%progbits + 736 .align 1 + 737 .global HAL_DBGMCU_EnableDBGStopMode + 738 .syntax unified + 739 .thumb + 740 .thumb_func + 742 HAL_DBGMCU_EnableDBGStopMode: + 743 .LFB162: + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Enable the Debug Module during STOP mode + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval None + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_DBGMCU_EnableDBGStopMode(void) + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 744 .loc 1 493 1 is_stmt 1 view -0 + 745 .cfi_startproc + 746 @ args = 0, pretend = 0, frame = 0 + 747 @ frame_needed = 0, uses_anonymous_args = 0 + 748 @ link register save eliminated. + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); + 749 .loc 1 494 3 view .LVU132 + 750 0000 024A ldr r2, .L69 + 751 0002 5368 ldr r3, [r2, #4] + 752 0004 43F00203 orr r3, r3, #2 + 753 0008 5360 str r3, [r2, #4] + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 754 .loc 1 495 1 is_stmt 0 view .LVU133 + 755 000a 7047 bx lr + 756 .L70: + 757 .align 2 + 758 .L69: + 759 000c 002004E0 .word -536600576 + 760 .cfi_endproc + 761 .LFE162: + 763 .section .text.HAL_DBGMCU_DisableDBGStopMode,"ax",%progbits + 764 .align 1 + ARM GAS /tmp/cchM4bQp.s page 23 + + + 765 .global HAL_DBGMCU_DisableDBGStopMode + 766 .syntax unified + 767 .thumb + 768 .thumb_func + 770 HAL_DBGMCU_DisableDBGStopMode: + 771 .LFB163: + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Disable the Debug Module during STOP mode + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval None + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_DBGMCU_DisableDBGStopMode(void) + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 772 .loc 1 502 1 is_stmt 1 view -0 + 773 .cfi_startproc + 774 @ args = 0, pretend = 0, frame = 0 + 775 @ frame_needed = 0, uses_anonymous_args = 0 + 776 @ link register save eliminated. + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); + 777 .loc 1 503 3 view .LVU135 + 778 0000 024A ldr r2, .L72 + 779 0002 5368 ldr r3, [r2, #4] + 780 0004 23F00203 bic r3, r3, #2 + 781 0008 5360 str r3, [r2, #4] + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 782 .loc 1 504 1 is_stmt 0 view .LVU136 + 783 000a 7047 bx lr + 784 .L73: + 785 .align 2 + 786 .L72: + 787 000c 002004E0 .word -536600576 + 788 .cfi_endproc + 789 .LFE163: + 791 .section .text.HAL_DBGMCU_EnableDBGStandbyMode,"ax",%progbits + 792 .align 1 + 793 .global HAL_DBGMCU_EnableDBGStandbyMode + 794 .syntax unified + 795 .thumb + 796 .thumb_func + 798 HAL_DBGMCU_EnableDBGStandbyMode: + 799 .LFB164: + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Enable the Debug Module during STANDBY mode + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval None + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_DBGMCU_EnableDBGStandbyMode(void) + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 800 .loc 1 511 1 is_stmt 1 view -0 + 801 .cfi_startproc + 802 @ args = 0, pretend = 0, frame = 0 + 803 @ frame_needed = 0, uses_anonymous_args = 0 + 804 @ link register save eliminated. + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); + 805 .loc 1 512 3 view .LVU138 + 806 0000 024A ldr r2, .L75 + 807 0002 5368 ldr r3, [r2, #4] + ARM GAS /tmp/cchM4bQp.s page 24 + + + 808 0004 43F00403 orr r3, r3, #4 + 809 0008 5360 str r3, [r2, #4] + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 810 .loc 1 513 1 is_stmt 0 view .LVU139 + 811 000a 7047 bx lr + 812 .L76: + 813 .align 2 + 814 .L75: + 815 000c 002004E0 .word -536600576 + 816 .cfi_endproc + 817 .LFE164: + 819 .section .text.HAL_DBGMCU_DisableDBGStandbyMode,"ax",%progbits + 820 .align 1 + 821 .global HAL_DBGMCU_DisableDBGStandbyMode + 822 .syntax unified + 823 .thumb + 824 .thumb_func + 826 HAL_DBGMCU_DisableDBGStandbyMode: + 827 .LFB165: + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Disable the Debug Module during STANDBY mode + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval None + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_DBGMCU_DisableDBGStandbyMode(void) + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 828 .loc 1 520 1 is_stmt 1 view -0 + 829 .cfi_startproc + 830 @ args = 0, pretend = 0, frame = 0 + 831 @ frame_needed = 0, uses_anonymous_args = 0 + 832 @ link register save eliminated. + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); + 833 .loc 1 521 3 view .LVU141 + 834 0000 024A ldr r2, .L78 + 835 0002 5368 ldr r3, [r2, #4] + 836 0004 23F00403 bic r3, r3, #4 + 837 0008 5360 str r3, [r2, #4] + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 838 .loc 1 522 1 is_stmt 0 view .LVU142 + 839 000a 7047 bx lr + 840 .L79: + 841 .align 2 + 842 .L78: + 843 000c 002004E0 .word -536600576 + 844 .cfi_endproc + 845 .LFE165: + 847 .section .text.HAL_EnableCompensationCell,"ax",%progbits + 848 .align 1 + 849 .global HAL_EnableCompensationCell + 850 .syntax unified + 851 .thumb + 852 .thumb_func + 854 HAL_EnableCompensationCell: + 855 .LFB166: + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Enables the I/O Compensation Cell. + ARM GAS /tmp/cchM4bQp.s page 25 + + + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note The I/O compensation cell can be used only when the device supply + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * voltage ranges from 2.4 to 3.6 V. + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval None + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_EnableCompensationCell(void) + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 856 .loc 1 531 1 is_stmt 1 view -0 + 857 .cfi_startproc + 858 @ args = 0, pretend = 0, frame = 0 + 859 @ frame_needed = 0, uses_anonymous_args = 0 + 860 @ link register save eliminated. + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** SYSCFG->CMPCR |= SYSCFG_CMPCR_CMP_PD; + 861 .loc 1 532 3 view .LVU144 + 862 .loc 1 532 9 is_stmt 0 view .LVU145 + 863 0000 024A ldr r2, .L81 + 864 0002 136A ldr r3, [r2, #32] + 865 .loc 1 532 17 view .LVU146 + 866 0004 43F00103 orr r3, r3, #1 + 867 0008 1362 str r3, [r2, #32] + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 868 .loc 1 533 1 view .LVU147 + 869 000a 7047 bx lr + 870 .L82: + 871 .align 2 + 872 .L81: + 873 000c 00380140 .word 1073821696 + 874 .cfi_endproc + 875 .LFE166: + 877 .section .text.HAL_DisableCompensationCell,"ax",%progbits + 878 .align 1 + 879 .global HAL_DisableCompensationCell + 880 .syntax unified + 881 .thumb + 882 .thumb_func + 884 HAL_DisableCompensationCell: + 885 .LFB167: + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Power-down the I/O Compensation Cell. + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note The I/O compensation cell can be used only when the device supply + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * voltage ranges from 2.4 to 3.6 V. + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval None + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_DisableCompensationCell(void) + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 886 .loc 1 542 1 is_stmt 1 view -0 + 887 .cfi_startproc + 888 @ args = 0, pretend = 0, frame = 0 + 889 @ frame_needed = 0, uses_anonymous_args = 0 + 890 @ link register save eliminated. + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** SYSCFG->CMPCR &= (uint32_t)~((uint32_t)SYSCFG_CMPCR_CMP_PD); + 891 .loc 1 543 3 view .LVU149 + 892 .loc 1 543 9 is_stmt 0 view .LVU150 + 893 0000 024A ldr r2, .L84 + 894 0002 136A ldr r3, [r2, #32] + 895 .loc 1 543 17 view .LVU151 + 896 0004 23F00103 bic r3, r3, #1 + ARM GAS /tmp/cchM4bQp.s page 26 + + + 897 0008 1362 str r3, [r2, #32] + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 898 .loc 1 544 1 view .LVU152 + 899 000a 7047 bx lr + 900 .L85: + 901 .align 2 + 902 .L84: + 903 000c 00380140 .word 1073821696 + 904 .cfi_endproc + 905 .LFE167: + 907 .section .text.HAL_EnableFMCMemorySwapping,"ax",%progbits + 908 .align 1 + 909 .global HAL_EnableFMCMemorySwapping + 910 .syntax unified + 911 .thumb + 912 .thumb_func + 914 HAL_EnableFMCMemorySwapping: + 915 .LFB168: + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Enables the FMC Memory Mapping Swapping. + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note SDRAM is accessible at 0x60000000 + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * and NOR/RAM is accessible at 0xC0000000 + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval None + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_EnableFMCMemorySwapping(void) + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 916 .loc 1 555 1 is_stmt 1 view -0 + 917 .cfi_startproc + 918 @ args = 0, pretend = 0, frame = 0 + 919 @ frame_needed = 0, uses_anonymous_args = 0 + 920 @ link register save eliminated. + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0; + 921 .loc 1 556 3 view .LVU154 + 922 .loc 1 556 9 is_stmt 0 view .LVU155 + 923 0000 024A ldr r2, .L87 + 924 0002 1368 ldr r3, [r2] + 925 .loc 1 556 18 view .LVU156 + 926 0004 43F48063 orr r3, r3, #1024 + 927 0008 1360 str r3, [r2] + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 928 .loc 1 557 1 view .LVU157 + 929 000a 7047 bx lr + 930 .L88: + 931 .align 2 + 932 .L87: + 933 000c 00380140 .word 1073821696 + 934 .cfi_endproc + 935 .LFE168: + 937 .section .text.HAL_DisableFMCMemorySwapping,"ax",%progbits + 938 .align 1 + 939 .global HAL_DisableFMCMemorySwapping + 940 .syntax unified + 941 .thumb + 942 .thumb_func + ARM GAS /tmp/cchM4bQp.s page 27 + + + 944 HAL_DisableFMCMemorySwapping: + 945 .LFB169: + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Disables the FMC Memory Mapping Swapping + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note SDRAM is accessible at 0xC0000000 (default mapping) + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * and NOR/RAM is accessible at 0x60000000 (default mapping) + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval None + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_DisableFMCMemorySwapping(void) + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 946 .loc 1 568 1 is_stmt 1 view -0 + 947 .cfi_startproc + 948 @ args = 0, pretend = 0, frame = 0 + 949 @ frame_needed = 0, uses_anonymous_args = 0 + 950 @ link register save eliminated. + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC); + 951 .loc 1 569 3 view .LVU159 + 952 .loc 1 569 9 is_stmt 0 view .LVU160 + 953 0000 024A ldr r2, .L90 + 954 0002 1368 ldr r3, [r2] + 955 .loc 1 569 18 view .LVU161 + 956 0004 23F44063 bic r3, r3, #3072 + 957 0008 1360 str r3, [r2] + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 958 .loc 1 570 1 view .LVU162 + 959 000a 7047 bx lr + 960 .L91: + 961 .align 2 + 962 .L90: + 963 000c 00380140 .word 1073821696 + 964 .cfi_endproc + 965 .LFE169: + 967 .section .text.HAL_EnableMemorySwappingBank,"ax",%progbits + 968 .align 1 + 969 .global HAL_EnableMemorySwappingBank + 970 .syntax unified + 971 .thumb + 972 .thumb_func + 974 HAL_EnableMemorySwappingBank: + 975 .LFB170: + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Enable the Internal FLASH Bank Swapping. + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note This function can be used only for STM32F77xx/STM32F76xx devices. + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM)) + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval None + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_EnableMemorySwappingBank(void) + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + ARM GAS /tmp/cchM4bQp.s page 28 + + + 976 .loc 1 584 1 is_stmt 1 view -0 + 977 .cfi_startproc + 978 @ args = 0, pretend = 0, frame = 0 + 979 @ frame_needed = 0, uses_anonymous_args = 0 + 980 @ link register save eliminated. + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB); + 981 .loc 1 585 3 view .LVU164 + 982 0000 024A ldr r2, .L93 + 983 0002 1368 ldr r3, [r2] + 984 0004 43F48073 orr r3, r3, #256 + 985 0008 1360 str r3, [r2] + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 986 .loc 1 586 1 is_stmt 0 view .LVU165 + 987 000a 7047 bx lr + 988 .L94: + 989 .align 2 + 990 .L93: + 991 000c 00380140 .word 1073821696 + 992 .cfi_endproc + 993 .LFE170: + 995 .section .text.HAL_DisableMemorySwappingBank,"ax",%progbits + 996 .align 1 + 997 .global HAL_DisableMemorySwappingBank + 998 .syntax unified + 999 .thumb + 1000 .thumb_func + 1002 HAL_DisableMemorySwappingBank: + 1003 .LFB171: + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** /** + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @brief Disable the Internal FLASH Bank Swapping. + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note This function can be used only for STM32F77xx/STM32F76xx devices. + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @note The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM)) + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** * @retval None + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** */ + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** void HAL_DisableMemorySwappingBank(void) + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** { + 1004 .loc 1 599 1 is_stmt 1 view -0 + 1005 .cfi_startproc + 1006 @ args = 0, pretend = 0, frame = 0 + 1007 @ frame_needed = 0, uses_anonymous_args = 0 + 1008 @ link register save eliminated. + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB); + 1009 .loc 1 600 3 view .LVU167 + 1010 0000 024A ldr r2, .L96 + 1011 0002 1368 ldr r3, [r2] + 1012 0004 23F48073 bic r3, r3, #256 + 1013 0008 1360 str r3, [r2] + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c **** } + 1014 .loc 1 601 1 is_stmt 0 view .LVU168 + 1015 000a 7047 bx lr + 1016 .L97: + 1017 .align 2 + ARM GAS /tmp/cchM4bQp.s page 29 + + + 1018 .L96: + 1019 000c 00380140 .word 1073821696 + 1020 .cfi_endproc + 1021 .LFE171: + 1023 .global uwTickFreq + 1024 .section .data.uwTickFreq,"aw" + 1027 uwTickFreq: + 1028 0000 01 .byte 1 + 1029 .global uwTickPrio + 1030 .section .data.uwTickPrio,"aw" + 1031 .align 2 + 1034 uwTickPrio: + 1035 0000 10000000 .word 16 + 1036 .global uwTick + 1037 .section .bss.uwTick,"aw",%nobits + 1038 .align 2 + 1041 uwTick: + 1042 0000 00000000 .space 4 + 1043 .text + 1044 .Letext0: + 1045 .file 2 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 1046 .file 3 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 1047 .file 4 "Drivers/CMSIS/Include/core_cm7.h" + 1048 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 1049 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h" + 1050 .file 7 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h" + 1051 .file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h" + ARM GAS /tmp/cchM4bQp.s page 30 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal.c + /tmp/cchM4bQp.s:20 .text.HAL_MspInit:00000000 $t + /tmp/cchM4bQp.s:26 .text.HAL_MspInit:00000000 HAL_MspInit + /tmp/cchM4bQp.s:39 .text.HAL_MspDeInit:00000000 $t + /tmp/cchM4bQp.s:45 .text.HAL_MspDeInit:00000000 HAL_MspDeInit + /tmp/cchM4bQp.s:58 .text.HAL_DeInit:00000000 $t + /tmp/cchM4bQp.s:64 .text.HAL_DeInit:00000000 HAL_DeInit + /tmp/cchM4bQp.s:108 .text.HAL_DeInit:00000028 $d + /tmp/cchM4bQp.s:113 .text.HAL_InitTick:00000000 $t + /tmp/cchM4bQp.s:119 .text.HAL_InitTick:00000000 HAL_InitTick + /tmp/cchM4bQp.s:182 .text.HAL_InitTick:00000040 $d + /tmp/cchM4bQp.s:1027 .data.uwTickFreq:00000000 uwTickFreq + /tmp/cchM4bQp.s:1034 .data.uwTickPrio:00000000 uwTickPrio + /tmp/cchM4bQp.s:189 .text.HAL_Init:00000000 $t + /tmp/cchM4bQp.s:195 .text.HAL_Init:00000000 HAL_Init + /tmp/cchM4bQp.s:225 .text.HAL_IncTick:00000000 $t + /tmp/cchM4bQp.s:231 .text.HAL_IncTick:00000000 HAL_IncTick + /tmp/cchM4bQp.s:251 .text.HAL_IncTick:00000010 $d + /tmp/cchM4bQp.s:1041 .bss.uwTick:00000000 uwTick + /tmp/cchM4bQp.s:257 .text.HAL_GetTick:00000000 $t + /tmp/cchM4bQp.s:263 .text.HAL_GetTick:00000000 HAL_GetTick + /tmp/cchM4bQp.s:279 .text.HAL_GetTick:00000008 $d + /tmp/cchM4bQp.s:284 .text.HAL_GetTickPrio:00000000 $t + /tmp/cchM4bQp.s:290 .text.HAL_GetTickPrio:00000000 HAL_GetTickPrio + /tmp/cchM4bQp.s:305 .text.HAL_GetTickPrio:00000008 $d + /tmp/cchM4bQp.s:310 .text.HAL_SetTickFreq:00000000 $t + /tmp/cchM4bQp.s:316 .text.HAL_SetTickFreq:00000000 HAL_SetTickFreq + /tmp/cchM4bQp.s:373 .text.HAL_SetTickFreq:00000024 $d + /tmp/cchM4bQp.s:379 .text.HAL_GetTickFreq:00000000 $t + /tmp/cchM4bQp.s:385 .text.HAL_GetTickFreq:00000000 HAL_GetTickFreq + /tmp/cchM4bQp.s:400 .text.HAL_GetTickFreq:00000008 $d + /tmp/cchM4bQp.s:405 .text.HAL_Delay:00000000 $t + /tmp/cchM4bQp.s:411 .text.HAL_Delay:00000000 HAL_Delay + /tmp/cchM4bQp.s:464 .text.HAL_Delay:00000024 $d + /tmp/cchM4bQp.s:469 .text.HAL_SuspendTick:00000000 $t + /tmp/cchM4bQp.s:475 .text.HAL_SuspendTick:00000000 HAL_SuspendTick + /tmp/cchM4bQp.s:495 .text.HAL_ResumeTick:00000000 $t + /tmp/cchM4bQp.s:501 .text.HAL_ResumeTick:00000000 HAL_ResumeTick + /tmp/cchM4bQp.s:521 .text.HAL_GetHalVersion:00000000 $t + /tmp/cchM4bQp.s:527 .text.HAL_GetHalVersion:00000000 HAL_GetHalVersion + /tmp/cchM4bQp.s:541 .text.HAL_GetHalVersion:00000004 $d + /tmp/cchM4bQp.s:546 .text.HAL_GetREVID:00000000 $t + /tmp/cchM4bQp.s:552 .text.HAL_GetREVID:00000000 HAL_GetREVID + /tmp/cchM4bQp.s:569 .text.HAL_GetREVID:00000008 $d + /tmp/cchM4bQp.s:574 .text.HAL_GetDEVID:00000000 $t + /tmp/cchM4bQp.s:580 .text.HAL_GetDEVID:00000000 HAL_GetDEVID + /tmp/cchM4bQp.s:597 .text.HAL_GetDEVID:0000000c $d + /tmp/cchM4bQp.s:602 .text.HAL_GetUIDw0:00000000 $t + /tmp/cchM4bQp.s:608 .text.HAL_GetUIDw0:00000000 HAL_GetUIDw0 + /tmp/cchM4bQp.s:623 .text.HAL_GetUIDw0:00000008 $d + /tmp/cchM4bQp.s:628 .text.HAL_GetUIDw1:00000000 $t + /tmp/cchM4bQp.s:634 .text.HAL_GetUIDw1:00000000 HAL_GetUIDw1 + /tmp/cchM4bQp.s:649 .text.HAL_GetUIDw1:00000008 $d + /tmp/cchM4bQp.s:654 .text.HAL_GetUIDw2:00000000 $t + /tmp/cchM4bQp.s:660 .text.HAL_GetUIDw2:00000000 HAL_GetUIDw2 + /tmp/cchM4bQp.s:675 .text.HAL_GetUIDw2:00000008 $d + ARM GAS /tmp/cchM4bQp.s page 31 + + + /tmp/cchM4bQp.s:680 .text.HAL_DBGMCU_EnableDBGSleepMode:00000000 $t + /tmp/cchM4bQp.s:686 .text.HAL_DBGMCU_EnableDBGSleepMode:00000000 HAL_DBGMCU_EnableDBGSleepMode + /tmp/cchM4bQp.s:703 .text.HAL_DBGMCU_EnableDBGSleepMode:0000000c $d + /tmp/cchM4bQp.s:708 .text.HAL_DBGMCU_DisableDBGSleepMode:00000000 $t + /tmp/cchM4bQp.s:714 .text.HAL_DBGMCU_DisableDBGSleepMode:00000000 HAL_DBGMCU_DisableDBGSleepMode + /tmp/cchM4bQp.s:731 .text.HAL_DBGMCU_DisableDBGSleepMode:0000000c $d + /tmp/cchM4bQp.s:736 .text.HAL_DBGMCU_EnableDBGStopMode:00000000 $t + /tmp/cchM4bQp.s:742 .text.HAL_DBGMCU_EnableDBGStopMode:00000000 HAL_DBGMCU_EnableDBGStopMode + /tmp/cchM4bQp.s:759 .text.HAL_DBGMCU_EnableDBGStopMode:0000000c $d + /tmp/cchM4bQp.s:764 .text.HAL_DBGMCU_DisableDBGStopMode:00000000 $t + /tmp/cchM4bQp.s:770 .text.HAL_DBGMCU_DisableDBGStopMode:00000000 HAL_DBGMCU_DisableDBGStopMode + /tmp/cchM4bQp.s:787 .text.HAL_DBGMCU_DisableDBGStopMode:0000000c $d + /tmp/cchM4bQp.s:792 .text.HAL_DBGMCU_EnableDBGStandbyMode:00000000 $t + /tmp/cchM4bQp.s:798 .text.HAL_DBGMCU_EnableDBGStandbyMode:00000000 HAL_DBGMCU_EnableDBGStandbyMode + /tmp/cchM4bQp.s:815 .text.HAL_DBGMCU_EnableDBGStandbyMode:0000000c $d + /tmp/cchM4bQp.s:820 .text.HAL_DBGMCU_DisableDBGStandbyMode:00000000 $t + /tmp/cchM4bQp.s:826 .text.HAL_DBGMCU_DisableDBGStandbyMode:00000000 HAL_DBGMCU_DisableDBGStandbyMode + /tmp/cchM4bQp.s:843 .text.HAL_DBGMCU_DisableDBGStandbyMode:0000000c $d + /tmp/cchM4bQp.s:848 .text.HAL_EnableCompensationCell:00000000 $t + /tmp/cchM4bQp.s:854 .text.HAL_EnableCompensationCell:00000000 HAL_EnableCompensationCell + /tmp/cchM4bQp.s:873 .text.HAL_EnableCompensationCell:0000000c $d + /tmp/cchM4bQp.s:878 .text.HAL_DisableCompensationCell:00000000 $t + /tmp/cchM4bQp.s:884 .text.HAL_DisableCompensationCell:00000000 HAL_DisableCompensationCell + /tmp/cchM4bQp.s:903 .text.HAL_DisableCompensationCell:0000000c $d + /tmp/cchM4bQp.s:908 .text.HAL_EnableFMCMemorySwapping:00000000 $t + /tmp/cchM4bQp.s:914 .text.HAL_EnableFMCMemorySwapping:00000000 HAL_EnableFMCMemorySwapping + /tmp/cchM4bQp.s:933 .text.HAL_EnableFMCMemorySwapping:0000000c $d + /tmp/cchM4bQp.s:938 .text.HAL_DisableFMCMemorySwapping:00000000 $t + /tmp/cchM4bQp.s:944 .text.HAL_DisableFMCMemorySwapping:00000000 HAL_DisableFMCMemorySwapping + /tmp/cchM4bQp.s:963 .text.HAL_DisableFMCMemorySwapping:0000000c $d + /tmp/cchM4bQp.s:968 .text.HAL_EnableMemorySwappingBank:00000000 $t + /tmp/cchM4bQp.s:974 .text.HAL_EnableMemorySwappingBank:00000000 HAL_EnableMemorySwappingBank + /tmp/cchM4bQp.s:991 .text.HAL_EnableMemorySwappingBank:0000000c $d + /tmp/cchM4bQp.s:996 .text.HAL_DisableMemorySwappingBank:00000000 $t + /tmp/cchM4bQp.s:1002 .text.HAL_DisableMemorySwappingBank:00000000 HAL_DisableMemorySwappingBank + /tmp/cchM4bQp.s:1019 .text.HAL_DisableMemorySwappingBank:0000000c $d + /tmp/cchM4bQp.s:1031 .data.uwTickPrio:00000000 $d + /tmp/cchM4bQp.s:1038 .bss.uwTick:00000000 $d + +UNDEFINED SYMBOLS +HAL_SYSTICK_Config +HAL_NVIC_SetPriority +SystemCoreClock +HAL_NVIC_SetPriorityGrouping diff --git a/build/stm32f7xx_hal.o b/build/stm32f7xx_hal.o new file mode 100644 index 0000000000000000000000000000000000000000..7dabe94f4c5a3255ea69362dce7594c2c821ce25 GIT binary patch literal 22260 zcmdsfdwg8Qm1f=UE=g9)LJ!;6vcPRwequfS27@hiOR_A<7HZiT#xrtDYFP?;A+@kQ zF^K~XufPByvtfV$Nnl_Sk}ydK!*4=>9T;FkW?>;42rwb9A=xE~2@sya^L=$sb>F^{ zlKp4@*e%oj)p^vZQ>UJ{`if6BwKqGCqik~2DwUy>y0hI#^m+rURHJH8<1OPYMfcBX z+kN6>eOa%nEbqObcYkkLqC9ayVt?Z1#I1>w?|gJJ(p>bAdRT1^Y%jV$)LhtBc6j$& ze?9rF4}SkwT-)=7NA*F&liwA>kiw}omr3c1aP_HDXZQ-D$z4@a1^V-S}A8&M?Rj6a(xQ3pw zw(6Z{oVN1uw_eM#aoF0}jJ6mLo4@_W$!&pWLa4JmM$Y!dcQn5L+-9~JY4?d&D@uo! zod^U=6XPu|6%|VDfHf!R&>vNRd?fU00QpDW3?sHE587#a?%hZT)QJ;In6LEYS4lpw zGd>tS;RNGsF>Qce=A&6>wmh4To(TEmUb^&Sv|ri_`|g_5=Y=-etMy zdF^OYbp}GeoTJo4XcJ1OLLu;{Liyla9EyaL`grISm_Hi&5^DQIXsK4}lR7~!^lp4P zdIh8b9S0|=)=*j#6{= z*TFB;Z^Hg5dL`;A(pSQhVtp&DmFQt;mg)x7I8Xly-}CkJ;4jcypn0mk1!WiNNASH! zZ$n*Wx*B#C>#I;>xz0yjr|DLBc)I>3$}Z8@p=?Bd4AP~#2K);BkFdW?p9xPY^%OYE z^+&L?LLY+8N_`!qt8@hX)%ph1xJJ)~{WJ8}kzcFNLcU6;V7XckAZ|7KJd~}~KStR) zy#_Yx^*;EvPG1iF^?E&|8}vBx8}&D!ze)cNG2E>0f>&E~J?c7B{}eXQ(!D6PRbPty z*}56}=ja|-+ot!SuI>63_|u?&hEk3Cm#`VtoJBGH3-FutB1ErQmqNcq-;4YXeKVx3 zx&Zcf>Zed|n|=>v+x7RL)1jY%x4ZNksIgNg!9Q1b;JZuTjZ$%a1NhzgH2APbzXEG} z_4o08p8f!3_vw4!;raRyzAw=I`2Guh6YTHTap?S|ehL2kmA)VR9(@G0AJ7`568aFN zeL4<)zy4p~By}z78qlA@_dz|077gkF)0&iG4uOQlrx_@u!g799} z{idah!XL2wTb7;|zMO4%+tLfeCG_GCwk_r1FS7hQRvrn5SpHp0SBA@}|6ZW@KE`_4 zs&E_eeJigGpUx%k152+D|B&(zExkFsg602c>)RS`WGp|j^6lZzu!~MwIu@>_z6wfx zJHi)o2slCMtIqH+{S8>UI~-y8pr!YP&t&;fQ2J_r_!;VJD?bqa3FDDt>Hctx`nk5g z!SG!e=z%;dA1{c;5$`#cPK9?-Ki}#f4qrz7uqzKPJLZHFtf0U$jyqw8jJcL^r4#-K zHmT4uu5rTOB;ypzxZY87pJh~wgTZgIY+mRvf)>nmHeuZAl}-U%(C;J8N|!<4=;Ms3 z-Ud!k<@^9e^xEJr(QYY{Q}1kJk-tRO_UkjCmakvKx1&D;B}e6a1(35TxDZN3cR`Tz zuM0SW9jEA8Sk8GuCT7vils#EaV~$hYM%Z}@_fG6h=aXv77wRCX_W3SV;#`ah^0brV zI1fWmT7V*@ob2XH&2#=8+`KtXzGGH^7pcRXDsegx-n<#1~Zte*n zaEWr}I}c#4I4#rIpTSz?Y?{WNr1qL=?41nhY17#E!x5)s8v7)?a&o7!{~4Y+AHnTx z2P@Q=)J3scZ7dTs4<+Bn)R*U8-#$|z{7=R~d6urr+ zAD&UPkMa4AN5rF+Yw!)a@HLOfQx}w+J3S((no{$f|6mAjcIKL(6sFlX(%98L_NmTY zjMccXS3#S}X~4u-xSqpy+=+0EtN=HH&!ROnGvO4FxgQLk3l{x>L78-!N5S}Oe9Gw2 ztFTj6CK7-X0k0>i~~MI+niD}?Op za@xK5&L2QI6%r>}V;7Y>nr^*TmUg-w5*}3@p7c(;mW5ucWvs3Mljnl6a_}BTsnhF` zxgD7$PG?}w$tBLYffVvx4mRtE^KW$W8MhCSHMK>Y+c=CK&*qjp!!YmMlO4DR>BGbD zp{xR>>5N+HjIw!GXA~EJ`yv%9*jHQ+egj4L&NensXgu~(1(lf(ng|~#AQk+UwsbFC_wtQ_eFq5+Y z99N+g3b`8;A#a6&IbsZ+<(E3)F!Z!*C_L9K2C}tuGdjBfj67HFGUke5qrp+(w3gC^ zQ+`)4PCL)KB<1nTFjH-m4h)$i24qizS8PH<6FJE_V! z;HW)T?4X=wc3URV>&{w3U&5I&Lqf08B?2dk^8yJo4_36*F0C;Cmet{zqBNkhioNFGXsm-dwR#;e zcc2;Hi2^K{nf!r)>SF^@oL1f!Dx2`~z z^h*IqON|BRU?3+;_BD^JCJ@S!eaDs2`Rqau;}(a`FD;!nPnRH@Q?2K(1|xWCgl&cA z!STp^R2X_msQuRv(Z;KTX$6(eH}TOq=jgdGmrveu zy@Jsz(qRI)i-^@O7cSLB0>P~6t`5Tgc_t*qTeWkxuTyW%h)ZS=-$`+)>DBCreGP(8 zsR@ZQEt**}UqCYkvjtDiCU|x>!H=!rd|#7)KAYh6*#vLTCirMJ!4)A1jKA{Fx`H|A znqmy$vwgmO;ZKXdk`b58Q2K#CEq=lkJ2`%*{%5v;OJhqiwIeaS7i;Fw*r+m#<}J8Q z>uK8S60wek`kr`dBAFQ3;Bx4GJei`Y=85D*s-vl+tE1DpS(j15@=GN(JT`hTV!ozE zCx;G>Ci^42U~P>>cgLDkS9i3hVHit)y7Kz8Qxdy9t+7M(3XNLt>afUpZF@Rh>b&z} zEpD!1M`K-kXVb1OwI`0|h%1@uS*tkEH<*~9%M79D#iDJ|=9aEHC7F7+qZ(T}qI-Ip zM%i7l#+G<0G1}jIq+<-5SF}k&>QpR3)YqYJWxvS~ip1Rr{7cfj4dtwdZS!a7Y z8>QI2620BsEj`U~kG0O^Xn$O~+l(AU7FZ|aFMec_{`Pbq8BdxDJ0{0t$<|Rc(2Qg^ zKrwefGeX13p^?m2E_M96T`!9KHAXU+UO08Ok2~gX#;W0jWX=F*2j%~ zvs85NbB$pduTRe;I&4NDM^)Vh3>8<2meHT4H#thtFKCmU5t%V59I9gmq^2f08e+)- zGql|~H#vyYjhWfh!YJpotu-AeL>&j`=AOo`HZ#7Yadv!}#m;oBUAc^QcUMbKba#g- zAtN}`x8fG!>xqPMbTT*=w(A?~X;&;c{aq1EGC)L(DeAENEu2 zjYpeYtDbQzGsZL2#N&8pthE_Sja$O3PBLyfVy(O5E*s6Yi$QWYafBTqt@0QY4yS_Y zPqT*EE(f>X?F=?`*WT7BSL*bFPiAI*#hRKM_OxSGVLGN4Cp#l-_sWQMH=>SC{02pJ zw+?h1PP|c^m!rdDSm!g{B2Jo+rX$a8G2!cKiZ^xbZHm<@o2yIb>eIP(>D>BsZbLe^ zkmc@JO;4qu{-V3 zP2_fC#-|+H;QeGGh4WN2 zIXuiY)ApNeCT98WADhCqZ5rITCw{(i*Lh9|b?%;q7>0ryL=yos=@4(vZX|oP=}FJx z-MY&yX2-AEH8$Fjn7oi@gx1lND>S{3K3$AYBrmp;OYQ7z${bltmvlFDboRu}w+Uj) zu04@x-KL295FDwmtzTDHTe~GvHPSaeb+-E)Sv9f=bZT&Fq!%~<{=oRf8>;&2Hj*43 zOQfps9DO!UI{jcICi(`?#xd*SP06Z}GX}=1`^O_y2k~G3p~S>MRehvtH>iRBL@H4= zne1a^CqWNPjhcL#r@F8_+Yt~;_D&t_7{kmSn{Zo=jjn@$}5y8%IZ3w9OhTQ#c-v;s}JEm4V19A{VNQ-vJpfLw)&&Jr5oSYg-ni*9yI5v{38A$dgYC2jwyKA}< z{X=7&gJUU#s;?(L)jOG-7)bObdnOY7iHVw))^h}Noq|i%AvoK^2 z&zPBJ&7FH>(DAUB@qYR?=N|66T8_qOyU?MqOS5?2-KOx*Z$CF671wUGd zA06ynA+P9oz2c{Nt7;SP^BM~CjtBn6F_*)Z&-=ZZ_`L4}|1#=(?ehN9OEd4MXRFt* zXYW#B!d#{|6c$|;Iv)JAzfRtrddvE0-l=-!%zJ6xoqB1%{Lj(;^8YW;4RvUAg13vx zS&6LP)Kt}>a^~iC%n9V@m4xQuH_%gq3!Ozy8Gc1P-KpS>r!RR~A@#;duNb#MUJ}=d z=7KNH3%b8Jc<7KSPE*We?%qiSaZ#8p=fzdoQ0o!dQQyPruOUXKJ;-2)K0w@rGlz{UV=! zrY4pMsuG`miP5i2yUZU;GbspZw*7fN``%eg`wM*f3w-wNF9L2ILHsh3ZQnb)X>XBF zz9{1yazRz*lb4zLGNXjQ;%8D&E%xaz_O)kmMj5%FD);G^8~x0>z~99)DX32K>7VAa ze_BQvxu81Tr+>On|8$@J5}*DOpZ*e`e#ECA@%bO|=`Z!^FZJm!_32mm^ecS&6+ZoC zKK*4r{bfG=N}qnEPd_tqSum)U`}CLl^q2eWukh)w@agjnl1vJ!l|KEIK7Fp5nH0nh zl|8;!`Sdd@5laQtYM=gUpZ@BMaihP+r@zLhzs9G3hEM+tpZ*y>{k1;2%IIg9RhcYu zK~?ROSNr5OKDy3F^YxNU3aa%P0=b~t=%Y9L=reuvRv&$qk3Przyv<#SJ5dGp7mmOT ztra~a%}A7Bzo13Z?f6t+zi0*8#MO4cC4i(a5}IX-VdbdM1j?@wnrl|Es#2c^QkN@b z3HFyefHqMde~w_}Tq!HCzdR*Ew|upFM&t!XUZ`I7&?Ttxb)nY+OYrZ*Ecrae-?>>o zM`i`Q;2TP$x${(Dy%ooXApa_$mbE?rE%u|IDIWdE#FlNS^md8d4@NS zXFnNU*!&EhD#i(PQPJE-|=|FnZow|#Uq^IcE%(16wUld z;*onxXDhfRr#)+%vhIcLj54>_^oLwextWD-!5N-xJtb$5^0bma;=b>aKaM~1AdLlZ zJ1{VzRE#*O)DB|GJ zo*-ZLr+%N{kl>i$l;Fn&KP7mD;I)D`3jUqo?Sgj+epQfrBGn=80jutIRPV6ET=!4APb!AZdz1@9DmRPaT?cLnpX z@UWeW1ZxF51rG=w6a0I@rv+aY{7|q!yY|Wj*9vYGY!}=wI4pQn@EXBe1@9I7uHe&x zFAKgd_@Q6{7EHFMTyU-6R>5|`VZoz<*9zVy_zl5F1pkNNPX*r+d|y!Iy7lG=&J|oK zSS7elaEst}!FIt51P28_NyI*KEfM<#{~VJ0#}`HZsNhS2{3AcMpRe%;E>P+t!Mr?| zUram?`-k8X;jbcgWB(A`D183OW#C-=0is}s@b?mT;g13Z`-MM3Y{N5z;Kzl3oVY`& zD+NC*{9A}kctKzAAB6u+Vxv;u5qw1WPZ75%^#j2l3IA2%R;7L+_*>z>L)@a&2ZDMI z=s}$8iFh) zEEB%@Q(x$<5q=F3_W9mFF)DhUL|h4V3;vbxFC^mXYD{pF2z!@^{3@ZZ75uF5Zxi}U zf_Dr5TS7k|_+29GKOyqxiKi;{g5b}D&p)>f;IQ?k;2(w0KcNob@RTn&kBE3ghTkw*K`WP?RS!~sn;xR3~8xnP8dcvcFoA|gI(1<@oEr}cuH ziHH}PVsJYVaf=C}2_}B+f}O+&)g{yk!?Qa>Uh&L@b7@0<`2ajhUCo@Wse$8KUH>=6++^LOfq*X^Vcr|%IFpI3;8 zi#abN9*faN#$i1X?MD+-U`XaSc$Gr0A|ej!h2Bg=JlcisBqA>TLJtxVpQAz_BO*@M z2z@;fmE9`z9Yn30y;!oj`d3Dc|^oH zB6KAY@vaqmJrQx=E_95D_;(7;J6ZO_0ipYe=#O!sQ$+O3F`!@m{cIOT?17YR#6!%%y9lA#u;uYliE&fXy&r)N>7+ z#dlv}%VN1#vRN$mVs;v<&eH>^!+nQ6qc!_g?KB3Ga!ZfK`zc`ePP=31F{W$Ups%cX8c!!YYl#?EiUM3{@;kif2cr^)95pu>_g4 z6yMat7H5)Qk1{4K-{#!)=k(S>&tI>ti*{_@{S(-Xe^}1bGOylV5MF!S`&frf*iudE z!Z)@=wcSuyoAFSShdh>j69ejzz7QX;J?@$9_}FCa9R$N`?_Jni1s?6ujY9k9oC(q17x*50GYd+ogrn)TUa?eQ7UYp>H|kA7NvFCp)>_b%wQ z_}FCa{Rj-Ny?vhel|W|gy^XxrUL}Z`{CmS^Z`|YGJdeFoP~K~=76iwEP1e6K_+I}G zd;D7fW$Pb*bMV^R2ZHgn$&MHMJGGs^JQL5Px6@}Y1)BY4ll8CHr*{GAh$ z_Loi8p8cKM`ghYT_HOanXP%k#9`@<2okfqoO?ds=I*VQq z3%ysbeHOhHK0UsVFq40+KE2^t^!QB1dI2UKg&t{}Z2l8Iy<^a`W0Sfze;xEVAFRFO zv*_I}_G~@W3ws8jt@jq_dFT1{nCG=vz`0J=NWHA@t3G?zVe-ac(0A)nrJ2;O^E z2xXf!|0_Gt+r_{m$h-g{>#fI!?Pa}B`|Lf9#j(g5f!t=F^tI!rMpsCCJOfyJKk?an zxzuCClYPl=FX}!Y(H=sSw)ckL9v0gjc-FPa`u7{3y({s2#=U{|HsfRc`=i*a6$6!c zZrwar2mtNz!{54yR&PHJG(6MTWcB8Yp5-5h66calte2@68Sgka)|_cC9zE0k@vZKD+9pn~n-597mnF*Hn_u$N9DJQu(2DQNBCaX&rgsXV>| L^;+jaTfP4Tbaey# literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_hal_adc.d b/build/stm32f7xx_hal_adc.d new file mode 100644 index 0000000..28e5d85 --- /dev/null +++ b/build/stm32f7xx_hal_adc.d @@ -0,0 +1,68 @@ +build/stm32f7xx_hal_adc.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/build/stm32f7xx_hal_adc.lst b/build/stm32f7xx_hal_adc.lst new file mode 100644 index 0000000..e0c50a0 --- /dev/null +++ b/build/stm32f7xx_hal_adc.lst @@ -0,0 +1,6376 @@ +ARM GAS /tmp/ccMiLMrd.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_hal_adc.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c" + 19 .section .text.ADC_Init,"ax",%progbits + 20 .align 1 + 21 .syntax unified + 22 .thumb + 23 .thumb_func + 25 ADC_Init: + 26 .LVL0: + 27 .LFB163: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @file stm32f7xx_hal_adc.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief This file provides firmware functions to manage the following + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * functionalities of the Analog to Digital Converter (ADC) peripheral: + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * + Initialization and de-initialization functions + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * + Peripheral Control functions + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * + Peripheral State functions + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ****************************************************************************** + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @attention + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * Copyright (c) 2017 STMicroelectronics. + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * All rights reserved. + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * This software is licensed under terms that can be found in the LICENSE file + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * in the root directory of this software component. + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ****************************************************************************** + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** @verbatim + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ============================================================================== + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ##### ADC Peripheral features ##### + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ============================================================================== + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) Interrupt generation at the end of conversion, end of injected conversion, + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** and in case of analog watchdog or overrun events + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) Single and continuous conversion modes. + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) Scan mode for automatic conversion of channel 0 to channel x. + ARM GAS /tmp/ccMiLMrd.s page 2 + + + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) Data alignment with in-built data coherency. + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) Channel-wise programmable sampling time. + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) External trigger option with configurable polarity for both regular and + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** injected conversion. + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) Dual/Triple mode (on devices with 2 ADCs or more). + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) Configurable DMA data storage in Dual/Triple ADC mode. + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) Configurable delay between conversions in Dual/Triple interleaved mode. + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) ADC conversion type (refer to the datasheets). + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** slower speed. + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) ADC input range: VREF(minus) = VIN = VREF(plus). + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) DMA request generation during regular channel conversion. + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ##### How to use this driver ##### + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ============================================================================== + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit(): + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE() + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (##) ADC pins configuration + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+++) Enable the clock for the ADC GPIOs using the following function: + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_RCC_GPIOx_CLK_ENABLE() + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (##) In case of using interrupts (e.g. HAL_ADC_Start_IT()) + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority() + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ() + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler() + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA()) + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE() + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+++) Configure and enable two DMA streams stream for managing data + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** transfer from peripheral to memory (output stream) + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+++) Associate the initialized DMA handle to the CRYP DMA handle + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** using __HAL_LINKDMA() + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+++) Configure the priority and enable the NVIC for the transfer complete + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** interrupt on the two DMA Streams. The output stream should have higher + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** priority than the input stream. + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** *** Configuration of ADC, groups regular/injected, channels parameters *** + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ============================================================================== + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) Configure the ADC parameters (resolution, data alignment, ...) + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** and regular group parameters (conversion trigger, sequencer, ...) + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** using function HAL_ADC_Init(). + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) Configure the channels for regular group parameters (channel number, + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** channel rank into sequencer, ..., into regular group) + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** using function HAL_ADC_ConfigChannel(). + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) Optionally, configure the injected group parameters (conversion trigger, + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** sequencer, ..., of injected group) + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** and the channels for injected group parameters (channel number, + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** channel rank into sequencer, ..., into injected group) + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** using function HAL_ADCEx_InjectedConfigChannel(). + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) Optionally, configure the analog watchdog parameters (channels + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig(). + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + ARM GAS /tmp/ccMiLMrd.s page 3 + + + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) Optionally, for devices with several ADC instances: configure the + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** multimode parameters using function HAL_ADCEx_MultiModeConfigChannel(). + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** *** Execution of ADC conversions *** + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ============================================================================== + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) ADC driver can be used among three modes: polling, interruption, + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** transfer by DMA. + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** *** Polling mode IO operation *** + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ================================= + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Start the ADC peripheral using HAL_ADC_Start() + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** user can specify the value of timeout according to his end application + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) To read the ADC converted values, use the HAL_ADC_GetValue() function. + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Stop the ADC peripheral using HAL_ADC_Stop() + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** *** Interrupt mode IO operation *** + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** =================================== + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Start the ADC peripheral using HAL_ADC_Start_IT() + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** add his own code by customization of function pointer HAL_ADC_ConvCpltCallback + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** add his own code by customization of function pointer HAL_ADC_ErrorCallback + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Stop the ADC peripheral using HAL_ADC_Stop_IT() + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** *** DMA mode IO operation *** + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ============================== + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the l + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** of data to be transferred at each end of conversion + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** add his own code by customization of function pointer HAL_ADC_ConvCpltCallback + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** add his own code by customization of function pointer HAL_ADC_ErrorCallback + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA() + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** *** ADC HAL driver macros list *** + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ============================================= + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** Below the list of most used macros in ADC HAL driver. + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) __HAL_ADC_ENABLE : Enable the ADC peripheral + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) __HAL_ADC_DISABLE : Disable the ADC peripheral + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabl + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** *** Callback functions *** + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ============================== + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] + ARM GAS /tmp/ccMiLMrd.s page 4 + + + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (@) Callback functions must be implemented in user program: + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+@) HAL_ADC_ErrorCallback() + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+@) HAL_ADC_ConvCpltCallback() + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+@) HAL_ADC_ConvHalfCpltCallback + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (@) You can refer to the ADC HAL driver header file for more useful macros + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** *** Deinitialization of ADC *** + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ============================================================================== + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) Disable the ADC interface + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (++) ADC clock can be hard reset and disabled at RCC top level. + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (++) Hard reset of ADC peripherals + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET(). + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (++) ADC clock disable using the equivalent macro/functions as configuration step. + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+++) Example: + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** Into HAL_ADC_MspDeInit() (recommended code location) or with + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** other device clock parameters configuration: + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure); + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock) + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) ADC pins configuration + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE() + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) Optionally, in case of usage of ADC with interruptions: + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn) + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (#) Optionally, in case of usage of DMA: + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (++) Deinitialize the DMA using function HAL_DMA_DeInit(). + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn) + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** *** Callback registration *** + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ============================================================================== + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** allows the user to configure dynamically the driver callbacks. + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** Use Functions HAL_ADC_RegisterCallback() + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** to register an interrupt callback. + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** Function HAL_ADC_RegisterCallback() allows to register following callbacks: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) ConvCpltCallback : ADC conversion complete callback + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) ErrorCallback : ADC error callback + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) InjectedConvCpltCallback : ADC group injected conversion complete callback + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) EndOfSamplingCallback : ADC end of sampling callback + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) MspInitCallback : ADC Msp Init callback + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) MspDeInitCallback : ADC Msp DeInit callback + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** This function takes as parameters the HAL peripheral handle, the Callback ID + ARM GAS /tmp/ccMiLMrd.s page 5 + + + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** and a pointer to the user callback function. + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** Use function HAL_ADC_UnRegisterCallback to reset a callback to the default + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** weak function. + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** and the Callback ID. + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** This function allows to reset following callbacks: + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) ConvCpltCallback : ADC conversion complete callback + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) ErrorCallback : ADC error callback + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) InjectedConvCpltCallback : ADC group injected conversion complete callback + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) EndOfSamplingCallback : ADC end of sampling callback + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) MspInitCallback : ADC Msp Init callback + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) MspDeInitCallback : ADC Msp DeInit callback + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** all callbacks are set to the corresponding weak functions: + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(). + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** Exception done for MspInit and MspDeInit functions that are + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** these callbacks are null (not registered beforehand). + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit() + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only. + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** Exception done MspInit/MspDeInit functions that can be registered/unregistered + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state, + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** Then, the user first registers the MspInit/MspDeInit user callbacks + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit() + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** or HAL_ADC_Init() function. + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** not defined, the callback registration feature is not available and all callbacks + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** are set to the corresponding weak functions. + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** @endverbatim + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ****************************************************************************** + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Includes ------------------------------------------------------------------*/ + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #include "stm32f7xx_hal.h" + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + ARM GAS /tmp/ccMiLMrd.s page 6 + + + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** @addtogroup STM32F7xx_HAL_Driver + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @{ + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** @defgroup ADC ADC + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief ADC driver modules + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @{ + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #ifdef HAL_ADC_MODULE_ENABLED + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Private typedef -----------------------------------------------------------*/ + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Private define ------------------------------------------------------------*/ + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Private macro -------------------------------------------------------------*/ + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Private variables ---------------------------------------------------------*/ + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** @addtogroup ADC_Private_Functions + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @{ + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Private function prototypes -----------------------------------------------*/ + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** static void ADC_Init(ADC_HandleTypeDef* hadc); + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** static void ADC_DMAError(DMA_HandleTypeDef *hdma); + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @} + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Exported functions --------------------------------------------------------*/ + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions ADC Exported Functions + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @{ + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Initialization and Configuration functions + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** @verbatim + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** =============================================================================== + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ##### Initialization and de-initialization functions ##### + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** =============================================================================== + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] This section provides functions allowing to: + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Initialize and configure the ADC. + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) De-initialize the ADC. + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** @endverbatim + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @{ + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Initializes the ADCx peripheral according to the specified parameters + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * in the ADC_InitStruct and initializes the ADC MSP. + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @note This function is used to configure the global features of the ADC ( + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * ClockPrescaler, Resolution, Data Alignment and number of conversion), however, + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the rest of the configuration parameters are specific to the regular + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * channels group (scan mode activation, continuous mode activation, + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * External trigger source and edge, DMA continuous request after the + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * last transfer and End of conversion selection). + ARM GAS /tmp/ccMiLMrd.s page 7 + + + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval HAL status + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check ADC handle */ + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(hadc == NULL) + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return HAL_ERROR; + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check the parameters */ + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv)); + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(hadc->State == HAL_ADC_STATE_RESET) + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Init the ADC Callback settings */ + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (hadc->MspInitCallback == NULL) + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Init the low level hardware */ + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->MspInitCallback(hadc); + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Init the low level hardware */ + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_MspInit(hadc); + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Initialize ADC error code */ + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_CLEAR_ERRORCODE(hadc); + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + ARM GAS /tmp/ccMiLMrd.s page 8 + + + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Allocate lock resource and initialize it */ + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Lock = HAL_UNLOCKED; + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Configuration of ADC parameters if previous preliminary actions are */ + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* correctly completed. */ + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC state */ + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_BUSY_INTERNAL); + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC parameters */ + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_Init(hadc); + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC error code to none */ + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_CLEAR_ERRORCODE(hadc); + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set the ADC state */ + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_BUSY_INTERNAL, + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_READY); + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** tmp_hal_status = HAL_ERROR; + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Release Lock */ + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_UNLOCK(hadc); + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return function status */ + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return tmp_hal_status; + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Deinitializes the ADCx peripheral registers to their default reset values. + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval HAL status + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check ADC handle */ + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(hadc == NULL) + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return HAL_ERROR; + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check the parameters */ + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC state */ + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); + ARM GAS /tmp/ccMiLMrd.s page 9 + + + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Stop potential conversion on going, on regular and injected groups */ + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Disable ADC peripheral */ + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_DISABLE(hadc); + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Configuration of ADC parameters if previous preliminary actions are */ + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* correctly completed. */ + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (hadc->MspDeInitCallback == NULL) + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* DeInit the low level hardware: RCC clock, NVIC */ + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->MspDeInitCallback(hadc); + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* DeInit the low level hardware: RCC clock, NVIC */ + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_MspDeInit(hadc); + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC error code to none */ + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_CLEAR_ERRORCODE(hadc); + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC state */ + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->State = HAL_ADC_STATE_RESET; + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process unlocked */ + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_UNLOCK(hadc); + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return function status */ + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return tmp_hal_status; + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Initializes the ADC MSP. + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval None + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** UNUSED(hadc); + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** the HAL_ADC_MspInit could be implemented in the user file + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief DeInitializes the ADC MSP. + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval None + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + ARM GAS /tmp/ccMiLMrd.s page 10 + + + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** UNUSED(hadc); + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** the HAL_ADC_MspDeInit could be implemented in the user file + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Register a User ADC Callback + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * To be used instead of the weak predefined callback + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param CallbackID ID of the callback to be registered + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * This parameter can be one of the following values: + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer call + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complet + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue over + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param pCallback pointer to the Callback function + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval HAL status + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef Callb + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef status = HAL_OK; + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (pCallback == NULL) + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Update the error code */ + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return HAL_ERROR; + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** switch (CallbackID) + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ConvCpltCallback = pCallback; + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** case HAL_ADC_CONVERSION_HALF_CB_ID : + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ConvHalfCpltCallback = pCallback; + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->LevelOutOfWindowCallback = pCallback; + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** case HAL_ADC_ERROR_CB_ID : + ARM GAS /tmp/ccMiLMrd.s page 11 + + + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ErrorCallback = pCallback; + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->InjectedConvCpltCallback = pCallback; + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** case HAL_ADC_MSPINIT_CB_ID : + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->MspInitCallback = pCallback; + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** case HAL_ADC_MSPDEINIT_CB_ID : + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->MspDeInitCallback = pCallback; + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** default : + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Update the error code */ + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return error status */ + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** status = HAL_ERROR; + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else if (HAL_ADC_STATE_RESET == hadc->State) + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** switch (CallbackID) + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** case HAL_ADC_MSPINIT_CB_ID : + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->MspInitCallback = pCallback; + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** case HAL_ADC_MSPDEINIT_CB_ID : + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->MspDeInitCallback = pCallback; + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** default : + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Update the error code */ + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return error status */ + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** status = HAL_ERROR; + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Update the error code */ + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return error status */ + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** status = HAL_ERROR; + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return status; + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + ARM GAS /tmp/ccMiLMrd.s page 12 + + + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Unregister a ADC Callback + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * ADC callback is redirected to the weak predefined callback + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param CallbackID ID of the callback to be unregistered + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * This parameter can be one of the following values: + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer call + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complet + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue over + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval HAL status + 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef Cal + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef status = HAL_OK; + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** switch (CallbackID) + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** case HAL_ADC_CONVERSION_HALF_CB_ID : + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** case HAL_ADC_ERROR_CB_ID : + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ErrorCallback = HAL_ADC_ErrorCallback; + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** case HAL_ADC_MSPINIT_CB_ID : + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** case HAL_ADC_MSPDEINIT_CB_ID : + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** default : + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Update the error code */ + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + ARM GAS /tmp/ccMiLMrd.s page 13 + + + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return error status */ + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** status = HAL_ERROR; + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else if (HAL_ADC_STATE_RESET == hadc->State) + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** switch (CallbackID) + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** case HAL_ADC_MSPINIT_CB_ID : + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** case HAL_ADC_MSPDEINIT_CB_ID : + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** default : + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Update the error code */ + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return error status */ + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** status = HAL_ERROR; + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** break; + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Update the error code */ + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return error status */ + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** status = HAL_ERROR; + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return status; + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @} + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions_Group2 IO operation functions + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief IO operation functions + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** @verbatim + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** =============================================================================== + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ##### IO operation functions ##### + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** =============================================================================== + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] This section provides functions allowing to: + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Start conversion of regular channel. + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Stop conversion of regular channel. + 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Start conversion of regular channel and enable interrupt. + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Stop conversion of regular channel and disable interrupt. + ARM GAS /tmp/ccMiLMrd.s page 14 + + + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Start conversion of regular channel and enable DMA transfer. + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Stop conversion of regular channel and disable DMA transfer. + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Handle ADC interrupt request. + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** @endverbatim + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @{ + 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Enables ADC and starts conversion of the regular channels. + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval HAL status + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __IO uint32_t counter = 0; + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check the parameters */ + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process locked */ + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_LOCK(hadc); + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable the ADC peripheral */ + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check if ADC peripheral is disabled in order to enable it and wait during + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** Tstab time the ADC's stabilization */ + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable the Peripheral */ + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_ENABLE(hadc); + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Delay for ADC stabilization time */ + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Compute number of CPU cycles to wait for */ + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) + 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** counter--; + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Start conversion if ADC is effectively enabled */ + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC state */ + 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* - Clear state bitfield related to regular group conversion results */ + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* - Set state bitfield related to regular group operation */ + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY); + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* If conversions on group regular are also triggering group injected, */ + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* update ADC state. */ + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + ARM GAS /tmp/ccMiLMrd.s page 15 + + + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* State machine update: Check if an injected conversion is ongoing */ + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Reset ADC error code fields related to conversions on group regular */ + 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Reset ADC all error code fields */ + 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_CLEAR_ERRORCODE(hadc); + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process unlocked */ + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Unlock before starting ADC conversions: in case of potential */ + 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* interruption, to let the process to ADC IRQ Handler. */ + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_UNLOCK(hadc); + 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Clear regular group conversion flag and overrun flag */ + 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* (To ensure of no unknown state from potential previous ADC operations) */ + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check if Multimode enabled */ + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* if no external trigger present enable software conversion of regular channels */ + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable the selected ADC software conversion for regular group */ + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* if instance of handle correspond to ADC1 and no external trigger present enable software + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable the selected ADC software conversion for regular group */ + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* if dual mode is selected, ADC3 works independently. */ + 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* check if the mode selected is not triple */ + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) ) + 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* if instance of handle correspond to ADC3 and no external trigger present enable software + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable the selected ADC software conversion for regular group */ + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else + 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + ARM GAS /tmp/ccMiLMrd.s page 16 + + + 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Update ADC state machine to error */ + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC error code to ADC IP internal error */ + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return function status */ + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return HAL_OK; + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** + 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Disables ADC and stop conversion of regular channels. + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @note Caution: This function will stop also injected channels. + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * + 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains + 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * + 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval HAL status. + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check the parameters */ + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process locked */ + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_LOCK(hadc); + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Stop potential conversion on going, on regular and injected groups */ + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Disable ADC peripheral */ + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_DISABLE(hadc); + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check if ADC is effectively disabled */ + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC state */ + 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_READY); + 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process unlocked */ + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_UNLOCK(hadc); + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return function status */ + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return HAL_OK; + 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** + 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Poll for regular conversion complete + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @note ADC conversion flags EOS (end of sequence) and EOC (end of + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * conversion) are cleared by this function. + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @note This function cannot be used in a particular setup: ADC configured + 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * in DMA mode and polling for end of each conversion (ADC init + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * In this case, DMA resets the flag EOC and polling cannot be + ARM GAS /tmp/ccMiLMrd.s page 17 + + + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * performed on each conversion. Nevertheless, polling can still + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * be performed on the complete sequence. + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. + 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param Timeout Timeout value in millisecond. + 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval HAL status + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t tickstart = 0; + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Verification that ADC configuration is compliant with polling for */ + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* each conversion: */ + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Particular case is ADC configured in DMA mode and ADC sequencer with */ + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* several ranks and polling for end of each conversion. */ + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* For code simplicity sake, this particular case is generalized to */ + 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* ADC configured in DMA mode and polling for end of each conversion. */ + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) && + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Update ADC state machine to error */ + 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process unlocked */ + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_UNLOCK(hadc); + 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return HAL_ERROR; + 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Get tick */ + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** tickstart = HAL_GetTick(); + 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check End of conversion flag */ + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) + 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check if timeout is disabled (set to infinite wait) */ + 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(Timeout != HAL_MAX_DELAY) + 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* New check to avoid false timeout detection in case of preemption */ + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Update ADC state machine to timeout */ + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process unlocked */ + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_UNLOCK(hadc); + 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return HAL_TIMEOUT; + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Clear regular group conversion flag */ + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); + ARM GAS /tmp/ccMiLMrd.s page 18 + + + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Update ADC state machine */ + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Determine whether any further conversion upcoming on group regular */ + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* by external trigger, continuous mode or scan sequence on going. */ + 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Note: On STM32F7, there is no independent flag of end of sequence. */ + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* The test of scan sequence on going is done either with scan */ + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* sequence disabled or with end of conversion flag set to */ + 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* of end of sequence. */ + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) && + 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC state */ + 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_READY); + 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return ADC state */ + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return HAL_OK; + 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** + 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Poll for conversion event + 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains + 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. + 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param EventType the ADC event type. + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * This parameter can be one of the following values: + 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @arg ADC_AWD_EVENT: ADC Analog watch Dog event. + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @arg ADC_OVR_EVENT: ADC Overrun event. + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param Timeout Timeout value in millisecond. + 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval HAL status + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeou + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t tickstart = 0; + 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check the parameters */ + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_EVENT_TYPE(EventType)); + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Get tick */ + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** tickstart = HAL_GetTick(); + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check selected event flag */ + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(!(__HAL_ADC_GET_FLAG(hadc,EventType))) + 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check for the Timeout */ + 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(Timeout != HAL_MAX_DELAY) + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + ARM GAS /tmp/ccMiLMrd.s page 19 + + +1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* New check to avoid false timeout detection in case of preemption */ +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(!(__HAL_ADC_GET_FLAG(hadc,EventType))) +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Update ADC state machine to timeout */ +1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process unlocked */ +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_UNLOCK(hadc); +1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return HAL_TIMEOUT; +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Analog watchdog (level out of window) event */ +1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(EventType == ADC_AWD_EVENT) +1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC state */ +1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); +1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Clear ADC analog watchdog flag */ +1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Overrun event */ +1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC state */ +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); +1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC error code to overrun */ +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); +1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Clear ADC overrun flag */ +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); +1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return ADC state */ +1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return HAL_OK; +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Enables the interrupt and starts ADC conversion of regular channels. +1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains +1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. +1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval HAL status. +1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) +1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __IO uint32_t counter = 0; +1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check the parameters */ +1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); +1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process locked */ + ARM GAS /tmp/ccMiLMrd.s page 20 + + +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_LOCK(hadc); +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable the ADC peripheral */ +1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check if ADC peripheral is disabled in order to enable it and wait during +1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** Tstab time the ADC's stabilization */ +1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) +1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable the Peripheral */ +1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_ENABLE(hadc); +1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Delay for ADC stabilization time */ +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Compute number of CPU cycles to wait for */ +1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) +1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** counter--; +1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Start conversion if ADC is effectively enabled */ +1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) +1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC state */ +1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* - Clear state bitfield related to regular group conversion results */ +1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* - Set state bitfield related to regular group operation */ +1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, +1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY); +1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* If conversions on group regular are also triggering group injected, */ +1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* update ADC state. */ +1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); +1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* State machine update: Check if an injected conversion is ongoing */ +1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) +1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Reset ADC error code fields related to conversions on group regular */ +1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); +1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Reset ADC all error code fields */ +1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_CLEAR_ERRORCODE(hadc); +1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process unlocked */ +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Unlock before starting ADC conversions: in case of potential */ +1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* interruption, to let the process to ADC IRQ Handler. */ +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_UNLOCK(hadc); +1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Clear regular group conversion flag and overrun flag */ +1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* (To ensure of no unknown state from potential previous ADC operations) */ +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); +1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + ARM GAS /tmp/ccMiLMrd.s page 21 + + +1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable end of conversion interrupt for regular group */ +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); +1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check if Multimode enabled */ +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) +1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* if no external trigger present enable software conversion of regular channels */ +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) +1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable the selected ADC software conversion for regular group */ +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else +1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* if instance of handle correspond to ADC1 and no external trigger present enable software +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) +1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable the selected ADC software conversion for regular group */ +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* if dual mode is selected, ADC3 works independently. */ +1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* check if the mode selected is not triple */ +1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) ) +1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* if instance of handle correspond to ADC3 and no external trigger present enable softwar +1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) +1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable the selected ADC software conversion for regular group */ +1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; +1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else +1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Update ADC state machine to error */ +1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); +1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC error code to ADC IP internal error */ +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); +1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return function status */ +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return HAL_OK; +1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Disables the interrupt and stop ADC conversion of regular channels. +1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @note Caution: This function will stop also injected channels. +1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * +1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains +1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. +1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval HAL status. +1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + ARM GAS /tmp/ccMiLMrd.s page 22 + + +1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) +1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check the parameters */ +1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); +1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process locked */ +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_LOCK(hadc); +1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Stop potential conversion on going, on regular and injected groups */ +1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Disable ADC peripheral */ +1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_DISABLE(hadc); +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check if ADC is effectively disabled */ +1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Disable ADC end of conversion interrupt for regular group */ +1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); +1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC state */ +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_READY); +1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process unlocked */ +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_UNLOCK(hadc); +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return function status */ +1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return HAL_OK; +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Handles ADC interrupt request +1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains +1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval None +1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t tmp1 = 0, tmp2 = 0; +1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t tmp_sr = hadc->Instance->SR; +1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t tmp_cr1 = hadc->Instance->CR1; +1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check the parameters */ +1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); +1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); +1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); +1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** tmp1 = tmp_sr & ADC_FLAG_EOC; +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** tmp2 = tmp_cr1 & ADC_IT_EOC; +1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check End of conversion flag for regular channels */ +1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(tmp1 && tmp2) +1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Update state machine on conversion status if not in error state */ +1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + ARM GAS /tmp/ccMiLMrd.s page 23 + + +1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC state */ +1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Determine whether any further conversion upcoming on group regular */ +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* by external trigger, continuous mode or scan sequence on going. */ +1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Note: On STM32F7, there is no independent flag of end of sequence. */ +1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* The test of scan sequence on going is done either with scan */ +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* sequence disabled or with end of conversion flag set to */ +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* of end of sequence. */ +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) && +1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || +1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) +1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Disable ADC end of single conversion interrupt on group regular */ +1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Note: Overrun interrupt was enabled with EOC interrupt in */ +1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ +1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* by overrun IRQ process below. */ +1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); +1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC state */ +1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); +1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) +1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_READY); +1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Conversion complete callback */ +1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ConvCpltCallback(hadc); +1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else +1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_ConvCpltCallback(hadc); +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Clear regular group conversion flag */ +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); +1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** tmp1 = tmp_sr & ADC_FLAG_JEOC; +1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** tmp2 = tmp_cr1 & ADC_IT_JEOC; +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check End of conversion flag for injected channels */ +1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(tmp1 && tmp2) +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Update state machine on conversion status if not in error state */ +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) +1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC state */ +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); +1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Determine whether any further conversion upcoming on group injected */ +1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* by external trigger, scan sequence on going or by automatic injected */ +1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* conversion from group regular (same conditions as group regular */ + ARM GAS /tmp/ccMiLMrd.s page 24 + + +1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* interruption disabling above). */ +1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || +1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) && +1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && +1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (ADC_IS_SOFTWARE_START_REGULAR(hadc) && +1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE)))) +1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Disable ADC end of single conversion interrupt on group injected */ +1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); +1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC state */ +1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); +1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) +1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_READY); +1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Conversion complete callback */ +1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->InjectedConvCpltCallback(hadc); +1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else +1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADCEx_InjectedConvCpltCallback(hadc); +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Clear injected group conversion flag */ +1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); +1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** tmp1 = tmp_sr & ADC_FLAG_AWD; +1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** tmp2 = tmp_cr1 & ADC_IT_AWD; +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check Analog watchdog flag */ +1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(tmp1 && tmp2) +1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) +1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC state */ +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); +1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Level out of window callback */ +1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->LevelOutOfWindowCallback(hadc); +1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else +1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_LevelOutOfWindowCallback(hadc); +1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Clear the ADC analog watchdog flag */ +1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); +1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** tmp1 = tmp_sr & ADC_FLAG_OVR; +1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** tmp2 = tmp_cr1 & ADC_IT_OVR; +1342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check Overrun flag */ + ARM GAS /tmp/ccMiLMrd.s page 25 + + +1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(tmp1 && tmp2) +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Note: On STM32F7, ADC overrun can be set through other parameters */ +1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* refer to description of parameter "EOCSelection" for more */ +1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* details. */ +1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC error code to overrun */ +1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); +1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Clear ADC overrun flag */ +1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); +1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Error callback */ +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ErrorCallback(hadc); +1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else +1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_ErrorCallback(hadc); +1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Clear the Overrun flag */ +1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); +1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC periphera +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains +1370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. +1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param pData The destination Buffer address. +1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param Length The length of data to be transferred from ADC peripheral to memory. +1373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval HAL status +1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __IO uint32_t counter = 0; +1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check the parameters */ +1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); +1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); +1382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process locked */ +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_LOCK(hadc); +1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable the ADC peripheral */ +1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check if ADC peripheral is disabled in order to enable it and wait during +1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** Tstab time the ADC's stabilization */ +1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable the Peripheral */ +1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_ENABLE(hadc); +1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Delay for ADC stabilization time */ +1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Compute number of CPU cycles to wait for */ +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); +1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) +1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** counter--; + ARM GAS /tmp/ccMiLMrd.s page 26 + + +1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Start conversion if ADC is effectively enabled */ +1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) +1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC state */ +1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* - Clear state bitfield related to regular group conversion results */ +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* - Set state bitfield related to regular group operation */ +1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, +1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY); +1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* If conversions on group regular are also triggering group injected, */ +1414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* update ADC state. */ +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) +1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); +1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* State machine update: Check if an injected conversion is ongoing */ +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) +1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Reset ADC error code fields related to conversions on group regular */ +1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); +1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else +1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Reset ADC all error code fields */ +1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_CLEAR_ERRORCODE(hadc); +1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process unlocked */ +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Unlock before starting ADC conversions: in case of potential */ +1434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* interruption, to let the process to ADC IRQ Handler. */ +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_UNLOCK(hadc); +1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set the DMA transfer complete callback */ +1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; +1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set the DMA half transfer complete callback */ +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; +1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set the DMA error callback */ +1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; +1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ +1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* start (in case of SW start): */ +1449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Clear regular group conversion flag and overrun flag */ +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* (To ensure of no unknown state from potential previous ADC operations) */ +1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); +1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable ADC overrun interrupt */ +1455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); +1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + ARM GAS /tmp/ccMiLMrd.s page 27 + + +1457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable ADC DMA mode */ +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 |= ADC_CR2_DMA; +1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Start the DMA channel */ +1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); +1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check if Multimode enabled */ +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* if no external trigger present enable software conversion of regular channels */ +1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable the selected ADC software conversion for regular group */ +1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else +1474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* if instance of handle correspond to ADC1 and no external trigger present enable software +1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) +1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable the selected ADC software conversion for regular group */ +1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; +1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* if dual mode is selected, ADC3 works independently. */ +1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* check if the mode selected is not triple */ +1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) ) +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* if instance of handle correspond to ADC3 and no external trigger present enable softwar +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) +1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable the selected ADC software conversion for regular group */ +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; +1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else +1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Update ADC state machine to error */ +1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); +1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC error code to ADC IP internal error */ +1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); +1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return function status */ +1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return HAL_OK; +1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral +1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains +1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. +1511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval HAL status +1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) + ARM GAS /tmp/ccMiLMrd.s page 28 + + +1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; +1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check the parameters */ +1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); +1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process locked */ +1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_LOCK(hadc); +1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Stop potential conversion on going, on regular and injected groups */ +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Disable ADC peripheral */ +1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_DISABLE(hadc); +1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check if ADC is effectively disabled */ +1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) +1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Disable the selected ADC DMA mode */ +1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 &= ~ADC_CR2_DMA; +1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Disable the DMA channel (in case of DMA in circular mode or stop while */ +1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* DMA transfer is on going) */ +1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) +1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); +1538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check if DMA channel effectively disabled */ +1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (tmp_hal_status != HAL_OK) +1541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Update ADC state machine to error */ +1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); +1544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Disable ADC overrun interrupt */ +1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); +1549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC state */ +1551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_STATE_CLR_SET(hadc->State, +1552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, +1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_READY); +1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process unlocked */ +1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_UNLOCK(hadc); +1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return function status */ +1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return tmp_hal_status; +1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Gets the converted value from data register of regular channel. +1565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains +1566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. +1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval Converted value +1568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) +1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + ARM GAS /tmp/ccMiLMrd.s page 29 + + +1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return the selected ADC converted value */ +1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return hadc->Instance->DR; +1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Regular conversion complete callback in non blocking mode +1577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains +1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. +1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval None +1580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) +1582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ +1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** UNUSED(hadc); +1585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** the HAL_ADC_ConvCpltCallback could be implemented in the user file +1587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Regular conversion half DMA transfer callback in non blocking mode +1592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains +1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval None +1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) +1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ +1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** UNUSED(hadc); +1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file +1602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Analog watchdog callback in non blocking mode +1607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains +1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. +1609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval None +1610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) +1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ +1614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** UNUSED(hadc); +1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file +1617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Error ADC callback. +1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @note In case of error due to overrun when using ADC with DMA transfer +1623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): +1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". +1625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * - If needed, restart a new ADC conversion using function +1626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * "HAL_ADC_Start_DMA()" +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * (this function is also clearing overrun flag) + ARM GAS /tmp/ccMiLMrd.s page 30 + + +1628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains +1629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. +1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval None +1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) +1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ +1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** UNUSED(hadc); +1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** the HAL_ADC_ErrorCallback could be implemented in the user file +1638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @} +1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions +1646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Peripheral Control functions +1647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * +1648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** @verbatim +1649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** =============================================================================== +1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ##### Peripheral Control functions ##### +1651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** =============================================================================== +1652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] This section provides functions allowing to: +1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Configure regular channels. +1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Configure injected channels. +1655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Configure multimode. +1656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Configure the analog watch dog. +1657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** @endverbatim +1659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @{ +1660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Configures for the selected ADC regular channel its corresponding +1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * rank in the sequencer and its sample time. +1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains +1666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. +1667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param sConfig ADC configuration structure. +1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval HAL status +1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __IO uint32_t counter = 0; +1673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check the parameters */ +1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_CHANNEL(sConfig->Channel)); +1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); +1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); +1678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process locked */ +1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_LOCK(hadc); +1681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ +1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if ((sConfig->Channel > ADC_CHANNEL_9) && (sConfig->Channel != ADC_INTERNAL_NONE)) +1684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + ARM GAS /tmp/ccMiLMrd.s page 31 + + +1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Clear the old sample time */ +1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel); +1687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) +1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set the new sample time */ +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18); +1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else +1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set the new sample time */ +1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); +1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else /* ADC_Channel include in ADC_Channel_[0..9] */ +1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Clear the old sample time */ +1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel); +1703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set the new sample time */ +1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel); +1706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* For Rank 1 to 6 */ +1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (sConfig->Rank < 7) +1710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Clear the old SQx bits for the selected rank */ +1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank); +1713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set the SQx bits for the selected rank */ +1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank); +1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* For Rank 7 to 12 */ +1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else if (sConfig->Rank < 13) +1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Clear the old SQx bits for the selected rank */ +1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank); +1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set the SQx bits for the selected rank */ +1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank); +1725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* For Rank 13 to 16 */ +1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else +1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Clear the old SQx bits for the selected rank */ +1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank); +1731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set the SQx bits for the selected rank */ +1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank); +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* if no internal channel selected */ +1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_INTERNAL_NONE)) +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Disable the VBAT & TSVREFE channel*/ +1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE); +1741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + ARM GAS /tmp/ccMiLMrd.s page 32 + + +1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* if ADC1 Channel_18 is selected enable VBAT Channel */ +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT)) +1745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Disable the TEMPSENSOR channel as it is multiplixed with the VBAT channel */ +1747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC->CCR &= ~ADC_CCR_TSVREFE; +1748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable the VBAT channel*/ +1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC->CCR |= ADC_CCR_VBATE; +1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VRE +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channe +1755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Disable the VBAT channel as it is multiplixed with TEMPSENSOR channel */ +1757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC->CCR &= ~ADC_CCR_VBATE; +1758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable the TSVREFE channel*/ +1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC->CCR |= ADC_CCR_TSVREFE; +1761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) +1763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Delay for temperature sensor stabilization time */ +1765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Compute number of CPU cycles to wait for */ +1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); +1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) +1768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** counter--; +1770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process unlocked */ +1775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_UNLOCK(hadc); +1776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return function status */ +1778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return HAL_OK; +1779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Configures the analog watchdog. +1783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @note Analog watchdog thresholds can be modified while ADC conversion +1784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * is on going. +1785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * In this case, some constraints must be taken into account: +1786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the programmed threshold values are effective from the next +1787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * ADC EOC (end of unitary conversion). +1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * Considering that registers write delay may happen due to +1789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * bus activity, this might cause an uncertainty on the +1790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * effective timing of the new programmed threshold values. +1791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains +1792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. +1793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure +1794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * that contains the configuration information of ADC analog watchdog. +1795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval HAL status +1796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* Analog +1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + ARM GAS /tmp/ccMiLMrd.s page 33 + + +1799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #ifdef USE_FULL_ASSERT +1800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t tmp = 0; +1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_FULL_ASSERT */ +1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check the parameters */ +1804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode)); +1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); +1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); +1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #ifdef USE_FULL_ASSERT +1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** tmp = ADC_GET_RESOLUTION(hadc); +1810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold)); +1811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold)); +1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_FULL_ASSERT */ +1813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process locked */ +1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_LOCK(hadc); +1816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(AnalogWDGConfig->ITMode == ENABLE) +1818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable the ADC Analog watchdog interrupt */ +1820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); +1821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else +1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Disable the ADC Analog watchdog interrupt */ +1825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); +1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Clear AWDEN, JAWDEN and AWDSGL bits */ +1829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN); +1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set the analog watchdog enable mode */ +1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode; +1833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set the high threshold */ +1835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; +1836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set the low threshold */ +1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; +1839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Clear the Analog watchdog channel select bits */ +1841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR1 &= ~ADC_CR1_AWDCH; +1842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set the Analog watchdog channel */ +1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel)); +1845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Process unlocked */ +1847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_UNLOCK(hadc); +1848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return function status */ +1850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return HAL_OK; +1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @} +1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ + ARM GAS /tmp/ccMiLMrd.s page 34 + + +1856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions +1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief ADC Peripheral State functions +1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * +1860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** @verbatim +1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** =============================================================================== +1862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ##### Peripheral State and errors functions ##### +1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** =============================================================================== +1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** [..] +1865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** This subsection provides functions allowing to +1866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Check the ADC state +1867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (+) Check the ADC Error +1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** @endverbatim +1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @{ +1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief return the ADC state +1875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains +1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. +1877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval HAL state +1878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) +1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return ADC state */ +1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return hadc->State; +1883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Return the ADC error code +1887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains +1888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. +1889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval ADC Error Code +1890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) +1892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return hadc->ErrorCode; +1894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @} +1898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @} +1902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Private functions ---------------------------------------------------------*/ +1905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** @defgroup ADC_Private_Functions ADC Private Functions +1907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @{ +1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief Initializes the ADCx peripheral according to the specified parameters +1912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * in the ADC_InitStruct without initializing the ADC MSP. + ARM GAS /tmp/ccMiLMrd.s page 35 + + +1913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains +1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified ADC. +1915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval None +1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** static void ADC_Init(ADC_HandleTypeDef* hadc) +1918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 28 .loc 1 1918 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. +1919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC parameters */ +1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set the ADC clock prescaler */ +1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC->CCR &= ~(ADC_CCR_ADCPRE); + 33 .loc 1 1921 3 view .LVU1 + 34 .loc 1 1921 6 is_stmt 0 view .LVU2 + 35 0000 4A4B ldr r3, .L6 + 36 0002 5A68 ldr r2, [r3, #4] + 37 .loc 1 1921 12 view .LVU3 + 38 0004 22F44032 bic r2, r2, #196608 + 39 0008 5A60 str r2, [r3, #4] +1922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC->CCR |= hadc->Init.ClockPrescaler; + 40 .loc 1 1922 3 is_stmt 1 view .LVU4 + 41 .loc 1 1922 6 is_stmt 0 view .LVU5 + 42 000a 5A68 ldr r2, [r3, #4] + 43 .loc 1 1922 26 view .LVU6 + 44 000c 4168 ldr r1, [r0, #4] + 45 .loc 1 1922 12 view .LVU7 + 46 000e 0A43 orrs r2, r2, r1 + 47 0010 5A60 str r2, [r3, #4] +1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC scan mode */ +1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR1 &= ~(ADC_CR1_SCAN); + 48 .loc 1 1925 3 is_stmt 1 view .LVU8 + 49 .loc 1 1925 7 is_stmt 0 view .LVU9 + 50 0012 0268 ldr r2, [r0] + 51 .loc 1 1925 17 view .LVU10 + 52 0014 5368 ldr r3, [r2, #4] + 53 .loc 1 1925 23 view .LVU11 + 54 0016 23F48073 bic r3, r3, #256 + 55 001a 5360 str r3, [r2, #4] +1926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode); + 56 .loc 1 1926 3 is_stmt 1 view .LVU12 + 57 .loc 1 1926 7 is_stmt 0 view .LVU13 + 58 001c 0268 ldr r2, [r0] + 59 .loc 1 1926 17 view .LVU14 + 60 001e 5368 ldr r3, [r2, #4] + 61 .loc 1 1926 27 view .LVU15 + 62 0020 0169 ldr r1, [r0, #16] + 63 .loc 1 1926 23 view .LVU16 + 64 0022 43EA0123 orr r3, r3, r1, lsl #8 + 65 0026 5360 str r3, [r2, #4] +1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC resolution */ +1929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR1 &= ~(ADC_CR1_RES); + 66 .loc 1 1929 3 is_stmt 1 view .LVU17 + 67 .loc 1 1929 7 is_stmt 0 view .LVU18 + ARM GAS /tmp/ccMiLMrd.s page 36 + + + 68 0028 0268 ldr r2, [r0] + 69 .loc 1 1929 17 view .LVU19 + 70 002a 5368 ldr r3, [r2, #4] + 71 .loc 1 1929 23 view .LVU20 + 72 002c 23F04073 bic r3, r3, #50331648 + 73 0030 5360 str r3, [r2, #4] +1930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR1 |= hadc->Init.Resolution; + 74 .loc 1 1930 3 is_stmt 1 view .LVU21 + 75 .loc 1 1930 7 is_stmt 0 view .LVU22 + 76 0032 0268 ldr r2, [r0] + 77 .loc 1 1930 17 view .LVU23 + 78 0034 5368 ldr r3, [r2, #4] + 79 .loc 1 1930 37 view .LVU24 + 80 0036 8168 ldr r1, [r0, #8] + 81 .loc 1 1930 23 view .LVU25 + 82 0038 0B43 orrs r3, r3, r1 + 83 003a 5360 str r3, [r2, #4] +1931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC data alignment */ +1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN); + 84 .loc 1 1933 3 is_stmt 1 view .LVU26 + 85 .loc 1 1933 7 is_stmt 0 view .LVU27 + 86 003c 0268 ldr r2, [r0] + 87 .loc 1 1933 17 view .LVU28 + 88 003e 9368 ldr r3, [r2, #8] + 89 .loc 1 1933 23 view .LVU29 + 90 0040 23F40063 bic r3, r3, #2048 + 91 0044 9360 str r3, [r2, #8] +1934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 |= hadc->Init.DataAlign; + 92 .loc 1 1934 3 is_stmt 1 view .LVU30 + 93 .loc 1 1934 7 is_stmt 0 view .LVU31 + 94 0046 0268 ldr r2, [r0] + 95 .loc 1 1934 17 view .LVU32 + 96 0048 9368 ldr r3, [r2, #8] + 97 .loc 1 1934 36 view .LVU33 + 98 004a C168 ldr r1, [r0, #12] + 99 .loc 1 1934 23 view .LVU34 + 100 004c 0B43 orrs r3, r3, r1 + 101 004e 9360 str r3, [r2, #8] +1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable external trigger if trigger selection is different of software */ +1937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* start. */ +1938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Note: This configuration keeps the hardware feature of parameter */ +1939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* ExternalTrigConvEdge "trigger edge none" equivalent to */ +1940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* software start. */ +1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + 102 .loc 1 1941 3 is_stmt 1 view .LVU35 + 103 .loc 1 1941 16 is_stmt 0 view .LVU36 + 104 0050 826A ldr r2, [r0, #40] + 105 .loc 1 1941 5 view .LVU37 + 106 0052 374B ldr r3, .L6+4 + 107 0054 9A42 cmp r2, r3 + 108 0056 57D0 beq .L2 +1942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Select external trigger to start conversion */ +1944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); + 109 .loc 1 1944 5 is_stmt 1 view .LVU38 + ARM GAS /tmp/ccMiLMrd.s page 37 + + + 110 .loc 1 1944 9 is_stmt 0 view .LVU39 + 111 0058 0268 ldr r2, [r0] + 112 .loc 1 1944 19 view .LVU40 + 113 005a 9368 ldr r3, [r2, #8] + 114 .loc 1 1944 25 view .LVU41 + 115 005c 23F07063 bic r3, r3, #251658240 + 116 0060 9360 str r3, [r2, #8] +1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv; + 117 .loc 1 1945 5 is_stmt 1 view .LVU42 + 118 .loc 1 1945 9 is_stmt 0 view .LVU43 + 119 0062 0268 ldr r2, [r0] + 120 .loc 1 1945 19 view .LVU44 + 121 0064 9368 ldr r3, [r2, #8] + 122 .loc 1 1945 38 view .LVU45 + 123 0066 816A ldr r1, [r0, #40] + 124 .loc 1 1945 25 view .LVU46 + 125 0068 0B43 orrs r3, r3, r1 + 126 006a 9360 str r3, [r2, #8] +1946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Select external trigger polarity */ +1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); + 127 .loc 1 1948 5 is_stmt 1 view .LVU47 + 128 .loc 1 1948 9 is_stmt 0 view .LVU48 + 129 006c 0268 ldr r2, [r0] + 130 .loc 1 1948 19 view .LVU49 + 131 006e 9368 ldr r3, [r2, #8] + 132 .loc 1 1948 25 view .LVU50 + 133 0070 23F04053 bic r3, r3, #805306368 + 134 0074 9360 str r3, [r2, #8] +1949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge; + 135 .loc 1 1949 5 is_stmt 1 view .LVU51 + 136 .loc 1 1949 9 is_stmt 0 view .LVU52 + 137 0076 0268 ldr r2, [r0] + 138 .loc 1 1949 19 view .LVU53 + 139 0078 9368 ldr r3, [r2, #8] + 140 .loc 1 1949 38 view .LVU54 + 141 007a C16A ldr r1, [r0, #44] + 142 .loc 1 1949 25 view .LVU55 + 143 007c 0B43 orrs r3, r3, r1 + 144 007e 9360 str r3, [r2, #8] + 145 .L3: +1950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else +1952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Reset the external trigger */ +1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); +1955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); +1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable or disable ADC continuous conversion mode */ +1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 &= ~(ADC_CR2_CONT); + 146 .loc 1 1959 3 is_stmt 1 view .LVU56 + 147 .loc 1 1959 7 is_stmt 0 view .LVU57 + 148 0080 0268 ldr r2, [r0] + 149 .loc 1 1959 17 view .LVU58 + 150 0082 9368 ldr r3, [r2, #8] + 151 .loc 1 1959 23 view .LVU59 + ARM GAS /tmp/ccMiLMrd.s page 38 + + + 152 0084 23F00203 bic r3, r3, #2 + 153 0088 9360 str r3, [r2, #8] +1960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode); + 154 .loc 1 1960 3 is_stmt 1 view .LVU60 + 155 .loc 1 1960 7 is_stmt 0 view .LVU61 + 156 008a 0268 ldr r2, [r0] + 157 .loc 1 1960 17 view .LVU62 + 158 008c 9368 ldr r3, [r2, #8] + 159 .loc 1 1960 26 view .LVU63 + 160 008e 8169 ldr r1, [r0, #24] + 161 .loc 1 1960 23 view .LVU64 + 162 0090 43EA4103 orr r3, r3, r1, lsl #1 + 163 0094 9360 str r3, [r2, #8] +1961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(hadc->Init.DiscontinuousConvMode != DISABLE) + 164 .loc 1 1962 3 is_stmt 1 view .LVU65 + 165 .loc 1 1962 16 is_stmt 0 view .LVU66 + 166 0096 90F82030 ldrb r3, [r0, #32] @ zero_extendqisi2 + 167 .loc 1 1962 5 view .LVU67 + 168 009a 002B cmp r3, #0 + 169 009c 3FD0 beq .L4 +1963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion)); + 170 .loc 1 1964 5 is_stmt 1 view .LVU68 +1965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable the selected ADC regular discontinuous mode */ +1967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN; + 171 .loc 1 1967 5 view .LVU69 + 172 .loc 1 1967 9 is_stmt 0 view .LVU70 + 173 009e 0268 ldr r2, [r0] + 174 .loc 1 1967 19 view .LVU71 + 175 00a0 5368 ldr r3, [r2, #4] + 176 .loc 1 1967 25 view .LVU72 + 177 00a2 43F40063 orr r3, r3, #2048 + 178 00a6 5360 str r3, [r2, #4] +1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set the number of channels to be converted in discontinuous mode */ +1970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM); + 179 .loc 1 1970 5 is_stmt 1 view .LVU73 + 180 .loc 1 1970 9 is_stmt 0 view .LVU74 + 181 00a8 0268 ldr r2, [r0] + 182 .loc 1 1970 19 view .LVU75 + 183 00aa 5368 ldr r3, [r2, #4] + 184 .loc 1 1970 25 view .LVU76 + 185 00ac 23F46043 bic r3, r3, #57344 + 186 00b0 5360 str r3, [r2, #4] +1971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion); + 187 .loc 1 1971 5 is_stmt 1 view .LVU77 + 188 .loc 1 1971 9 is_stmt 0 view .LVU78 + 189 00b2 0168 ldr r1, [r0] + 190 .loc 1 1971 19 view .LVU79 + 191 00b4 4B68 ldr r3, [r1, #4] + 192 .loc 1 1971 29 view .LVU80 + 193 00b6 426A ldr r2, [r0, #36] + 194 00b8 013A subs r2, r2, #1 + 195 .loc 1 1971 25 view .LVU81 + 196 00ba 43EA4233 orr r3, r3, r2, lsl #13 + ARM GAS /tmp/ccMiLMrd.s page 39 + + + 197 00be 4B60 str r3, [r1, #4] + 198 .L5: +1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else +1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +1975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Disable the selected ADC regular discontinuous mode */ +1976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN); +1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +1978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC number of conversion */ +1980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->SQR1 &= ~(ADC_SQR1_L); + 199 .loc 1 1980 3 is_stmt 1 view .LVU82 + 200 .loc 1 1980 7 is_stmt 0 view .LVU83 + 201 00c0 0268 ldr r2, [r0] + 202 .loc 1 1980 17 view .LVU84 + 203 00c2 D36A ldr r3, [r2, #44] + 204 .loc 1 1980 24 view .LVU85 + 205 00c4 23F47003 bic r3, r3, #15728640 + 206 00c8 D362 str r3, [r2, #44] +1981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion); + 207 .loc 1 1981 3 is_stmt 1 view .LVU86 + 208 .loc 1 1981 7 is_stmt 0 view .LVU87 + 209 00ca 0168 ldr r1, [r0] + 210 .loc 1 1981 17 view .LVU88 + 211 00cc CB6A ldr r3, [r1, #44] + 212 .loc 1 1981 28 view .LVU89 + 213 00ce C269 ldr r2, [r0, #28] + 214 00d0 013A subs r2, r2, #1 + 215 .loc 1 1981 24 view .LVU90 + 216 00d2 43EA0253 orr r3, r3, r2, lsl #20 + 217 00d6 CB62 str r3, [r1, #44] +1982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable or disable ADC DMA continuous request */ +1984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 &= ~(ADC_CR2_DDS); + 218 .loc 1 1984 3 is_stmt 1 view .LVU91 + 219 .loc 1 1984 7 is_stmt 0 view .LVU92 + 220 00d8 0268 ldr r2, [r0] + 221 .loc 1 1984 17 view .LVU93 + 222 00da 9368 ldr r3, [r2, #8] + 223 .loc 1 1984 23 view .LVU94 + 224 00dc 23F40073 bic r3, r3, #512 + 225 00e0 9360 str r3, [r2, #8] +1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests); + 226 .loc 1 1985 3 is_stmt 1 view .LVU95 + 227 .loc 1 1985 7 is_stmt 0 view .LVU96 + 228 00e2 0268 ldr r2, [r0] + 229 .loc 1 1985 17 view .LVU97 + 230 00e4 9368 ldr r3, [r2, #8] + 231 .loc 1 1985 26 view .LVU98 + 232 00e6 90F83010 ldrb r1, [r0, #48] @ zero_extendqisi2 + 233 .loc 1 1985 23 view .LVU99 + 234 00ea 43EA4123 orr r3, r3, r1, lsl #9 + 235 00ee 9360 str r3, [r2, #8] +1986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Enable or disable ADC end of conversion selection */ +1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 &= ~(ADC_CR2_EOCS); + 236 .loc 1 1988 3 is_stmt 1 view .LVU100 + ARM GAS /tmp/ccMiLMrd.s page 40 + + + 237 .loc 1 1988 7 is_stmt 0 view .LVU101 + 238 00f0 0268 ldr r2, [r0] + 239 .loc 1 1988 17 view .LVU102 + 240 00f2 9368 ldr r3, [r2, #8] + 241 .loc 1 1988 23 view .LVU103 + 242 00f4 23F48063 bic r3, r3, #1024 + 243 00f8 9360 str r3, [r2, #8] +1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection); + 244 .loc 1 1989 3 is_stmt 1 view .LVU104 + 245 .loc 1 1989 7 is_stmt 0 view .LVU105 + 246 00fa 0268 ldr r2, [r0] + 247 .loc 1 1989 17 view .LVU106 + 248 00fc 9368 ldr r3, [r2, #8] + 249 .loc 1 1989 26 view .LVU107 + 250 00fe 4169 ldr r1, [r0, #20] + 251 .loc 1 1989 23 view .LVU108 + 252 0100 43EA8123 orr r3, r3, r1, lsl #10 + 253 0104 9360 str r3, [r2, #8] +1990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 254 .loc 1 1990 1 view .LVU109 + 255 0106 7047 bx lr + 256 .L2: +1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); + 257 .loc 1 1954 5 is_stmt 1 view .LVU110 +1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); + 258 .loc 1 1954 9 is_stmt 0 view .LVU111 + 259 0108 0268 ldr r2, [r0] +1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); + 260 .loc 1 1954 19 view .LVU112 + 261 010a 9368 ldr r3, [r2, #8] +1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); + 262 .loc 1 1954 25 view .LVU113 + 263 010c 23F07063 bic r3, r3, #251658240 + 264 0110 9360 str r3, [r2, #8] +1955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 265 .loc 1 1955 5 is_stmt 1 view .LVU114 +1955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 266 .loc 1 1955 9 is_stmt 0 view .LVU115 + 267 0112 0268 ldr r2, [r0] +1955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 268 .loc 1 1955 19 view .LVU116 + 269 0114 9368 ldr r3, [r2, #8] +1955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 270 .loc 1 1955 25 view .LVU117 + 271 0116 23F04053 bic r3, r3, #805306368 + 272 011a 9360 str r3, [r2, #8] + 273 011c B0E7 b .L3 + 274 .L4: +1976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 275 .loc 1 1976 5 is_stmt 1 view .LVU118 +1976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 276 .loc 1 1976 9 is_stmt 0 view .LVU119 + 277 011e 0268 ldr r2, [r0] +1976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 278 .loc 1 1976 19 view .LVU120 + 279 0120 5368 ldr r3, [r2, #4] +1976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + ARM GAS /tmp/ccMiLMrd.s page 41 + + + 280 .loc 1 1976 25 view .LVU121 + 281 0122 23F40063 bic r3, r3, #2048 + 282 0126 5360 str r3, [r2, #4] + 283 0128 CAE7 b .L5 + 284 .L7: + 285 012a 00BF .align 2 + 286 .L6: + 287 012c 00230140 .word 1073816320 + 288 0130 0100000F .word 251658241 + 289 .cfi_endproc + 290 .LFE163: + 292 .section .text.HAL_ADC_MspInit,"ax",%progbits + 293 .align 1 + 294 .weak HAL_ADC_MspInit + 295 .syntax unified + 296 .thumb + 297 .thumb_func + 299 HAL_ADC_MspInit: + 300 .LVL1: + 301 .LFB143: + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ + 302 .loc 1 474 1 is_stmt 1 view -0 + 303 .cfi_startproc + 304 @ args = 0, pretend = 0, frame = 0 + 305 @ frame_needed = 0, uses_anonymous_args = 0 + 306 @ link register save eliminated. + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 307 .loc 1 476 3 view .LVU123 + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 308 .loc 1 480 1 is_stmt 0 view .LVU124 + 309 0000 7047 bx lr + 310 .cfi_endproc + 311 .LFE143: + 313 .section .text.HAL_ADC_Init,"ax",%progbits + 314 .align 1 + 315 .global HAL_ADC_Init + 316 .syntax unified + 317 .thumb + 318 .thumb_func + 320 HAL_ADC_Init: + 321 .LVL2: + 322 .LFB141: + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 323 .loc 1 323 1 is_stmt 1 view -0 + 324 .cfi_startproc + 325 @ args = 0, pretend = 0, frame = 0 + 326 @ frame_needed = 0, uses_anonymous_args = 0 + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 327 .loc 1 324 3 view .LVU126 + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 328 .loc 1 327 3 view .LVU127 + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 329 .loc 1 327 5 is_stmt 0 view .LVU128 + 330 0000 28B3 cbz r0, .L13 + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 331 .loc 1 323 1 view .LVU129 + 332 0002 10B5 push {r4, lr} + ARM GAS /tmp/ccMiLMrd.s page 42 + + + 333 .LCFI0: + 334 .cfi_def_cfa_offset 8 + 335 .cfi_offset 4, -8 + 336 .cfi_offset 14, -4 + 337 0004 0446 mov r4, r0 + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); + 338 .loc 1 333 3 is_stmt 1 view .LVU130 + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); + 339 .loc 1 334 3 view .LVU131 + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); + 340 .loc 1 335 3 view .LVU132 + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + 341 .loc 1 336 3 view .LVU133 + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv)); + 342 .loc 1 337 3 view .LVU134 + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); + 343 .loc 1 338 3 view .LVU135 + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); + 344 .loc 1 339 3 view .LVU136 + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); + 345 .loc 1 340 3 view .LVU137 + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); + 346 .loc 1 341 3 view .LVU138 + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); + 347 .loc 1 342 3 view .LVU139 + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 348 .loc 1 343 3 view .LVU140 + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 349 .loc 1 345 3 view .LVU141 + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 350 .loc 1 347 5 view .LVU142 + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 351 .loc 1 350 3 view .LVU143 + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 352 .loc 1 350 10 is_stmt 0 view .LVU144 + 353 0006 036C ldr r3, [r0, #64] + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 354 .loc 1 350 5 view .LVU145 + 355 0008 43B1 cbz r3, .L19 + 356 .LVL3: + 357 .L11: + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 358 .loc 1 380 3 is_stmt 1 view .LVU146 + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 359 .loc 1 380 7 is_stmt 0 view .LVU147 + 360 000a 236C ldr r3, [r4, #64] + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 361 .loc 1 380 6 view .LVU148 + 362 000c 13F0100F tst r3, #16 + 363 0010 0BD0 beq .L20 + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 364 .loc 1 400 20 view .LVU149 + 365 0012 0120 movs r0, #1 + 366 .L12: + 367 .LVL4: + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 368 .loc 1 404 3 is_stmt 1 view .LVU150 + ARM GAS /tmp/ccMiLMrd.s page 43 + + + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 369 .loc 1 404 3 view .LVU151 + 370 0014 0023 movs r3, #0 + 371 0016 84F83C30 strb r3, [r4, #60] + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 372 .loc 1 404 3 view .LVU152 + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 373 .loc 1 407 3 view .LVU153 + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 374 .loc 1 408 1 is_stmt 0 view .LVU154 + 375 001a 10BD pop {r4, pc} + 376 .LVL5: + 377 .L19: + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + 378 .loc 1 368 5 is_stmt 1 view .LVU155 + 379 001c FFF7FEFF bl HAL_ADC_MspInit + 380 .LVL6: + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 381 .loc 1 372 5 view .LVU156 + 382 0020 0023 movs r3, #0 + 383 0022 6364 str r3, [r4, #68] + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 384 .loc 1 375 5 view .LVU157 + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 385 .loc 1 375 16 is_stmt 0 view .LVU158 + 386 0024 84F83C30 strb r3, [r4, #60] + 387 0028 EFE7 b .L11 + 388 .L20: + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + 389 .loc 1 383 5 is_stmt 1 view .LVU159 + 390 002a 226C ldr r2, [r4, #64] + 391 002c 094B ldr r3, .L21 + 392 002e 1340 ands r3, r3, r2 + 393 0030 43F00203 orr r3, r3, #2 + 394 0034 2364 str r3, [r4, #64] + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 395 .loc 1 388 5 view .LVU160 + 396 0036 2046 mov r0, r4 + 397 0038 FFF7FEFF bl ADC_Init + 398 .LVL7: + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 399 .loc 1 391 5 view .LVU161 + 400 003c 0020 movs r0, #0 + 401 003e 6064 str r0, [r4, #68] + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_BUSY_INTERNAL, + 402 .loc 1 394 5 view .LVU162 + 403 0040 236C ldr r3, [r4, #64] + 404 0042 23F00303 bic r3, r3, #3 + 405 0046 43F00103 orr r3, r3, #1 + 406 004a 2364 str r3, [r4, #64] + 407 004c E2E7 b .L12 + 408 .LVL8: + 409 .L13: + 410 .LCFI1: + 411 .cfi_def_cfa_offset 0 + 412 .cfi_restore 4 + 413 .cfi_restore 14 + ARM GAS /tmp/ccMiLMrd.s page 44 + + + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 414 .loc 1 329 12 is_stmt 0 view .LVU163 + 415 004e 0120 movs r0, #1 + 416 .LVL9: + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 417 .loc 1 408 1 view .LVU164 + 418 0050 7047 bx lr + 419 .L22: + 420 0052 00BF .align 2 + 421 .L21: + 422 0054 FDEEFFFF .word -4355 + 423 .cfi_endproc + 424 .LFE141: + 426 .section .text.HAL_ADC_MspDeInit,"ax",%progbits + 427 .align 1 + 428 .weak HAL_ADC_MspDeInit + 429 .syntax unified + 430 .thumb + 431 .thumb_func + 433 HAL_ADC_MspDeInit: + 434 .LVL10: + 435 .LFB144: + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ + 436 .loc 1 489 1 is_stmt 1 view -0 + 437 .cfi_startproc + 438 @ args = 0, pretend = 0, frame = 0 + 439 @ frame_needed = 0, uses_anonymous_args = 0 + 440 @ link register save eliminated. + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 441 .loc 1 491 3 view .LVU166 + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 442 .loc 1 495 1 is_stmt 0 view .LVU167 + 443 0000 7047 bx lr + 444 .cfi_endproc + 445 .LFE144: + 447 .section .text.HAL_ADC_DeInit,"ax",%progbits + 448 .align 1 + 449 .global HAL_ADC_DeInit + 450 .syntax unified + 451 .thumb + 452 .thumb_func + 454 HAL_ADC_DeInit: + 455 .LVL11: + 456 .LFB142: + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 457 .loc 1 417 1 is_stmt 1 view -0 + 458 .cfi_startproc + 459 @ args = 0, pretend = 0, frame = 0 + 460 @ frame_needed = 0, uses_anonymous_args = 0 + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 461 .loc 1 418 3 view .LVU169 + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 462 .loc 1 421 3 view .LVU170 + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 463 .loc 1 421 5 is_stmt 0 view .LVU171 + 464 0000 C8B1 cbz r0, .L27 + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + ARM GAS /tmp/ccMiLMrd.s page 45 + + + 465 .loc 1 417 1 view .LVU172 + 466 0002 10B5 push {r4, lr} + 467 .LCFI2: + 468 .cfi_def_cfa_offset 8 + 469 .cfi_offset 4, -8 + 470 .cfi_offset 14, -4 + 471 0004 0446 mov r4, r0 + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 472 .loc 1 427 3 is_stmt 1 view .LVU173 + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 473 .loc 1 430 3 view .LVU174 + 474 0006 036C ldr r3, [r0, #64] + 475 0008 43F00203 orr r3, r3, #2 + 476 000c 0364 str r3, [r0, #64] + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 477 .loc 1 434 3 view .LVU175 + 478 000e 0268 ldr r2, [r0] + 479 0010 9368 ldr r3, [r2, #8] + 480 0012 23F00103 bic r3, r3, #1 + 481 0016 9360 str r3, [r2, #8] + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 482 .loc 1 438 3 view .LVU176 + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 483 .loc 1 438 6 is_stmt 0 view .LVU177 + 484 0018 0368 ldr r3, [r0] + 485 001a 9B68 ldr r3, [r3, #8] + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 486 .loc 1 438 5 view .LVU178 + 487 001c 13F0010F tst r3, #1 + 488 0020 03D0 beq .L32 + 489 .LVL12: + 490 .L26: + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 491 .loc 1 461 3 is_stmt 1 view .LVU179 + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 492 .loc 1 461 3 view .LVU180 + 493 0022 0020 movs r0, #0 + 494 0024 84F83C00 strb r0, [r4, #60] + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 495 .loc 1 461 3 view .LVU181 + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 496 .loc 1 464 3 view .LVU182 + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 497 .loc 1 465 1 is_stmt 0 view .LVU183 + 498 0028 10BD pop {r4, pc} + 499 .LVL13: + 500 .L32: + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + 501 .loc 1 450 3 is_stmt 1 view .LVU184 + 502 002a FFF7FEFF bl HAL_ADC_MspDeInit + 503 .LVL14: + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 504 .loc 1 454 5 view .LVU185 + 505 002e 0023 movs r3, #0 + 506 0030 6364 str r3, [r4, #68] + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 507 .loc 1 457 5 view .LVU186 + ARM GAS /tmp/ccMiLMrd.s page 46 + + + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 508 .loc 1 457 17 is_stmt 0 view .LVU187 + 509 0032 2364 str r3, [r4, #64] + 510 0034 F5E7 b .L26 + 511 .LVL15: + 512 .L27: + 513 .LCFI3: + 514 .cfi_def_cfa_offset 0 + 515 .cfi_restore 4 + 516 .cfi_restore 14 + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 517 .loc 1 423 12 view .LVU188 + 518 0036 0120 movs r0, #1 + 519 .LVL16: + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 520 .loc 1 465 1 view .LVU189 + 521 0038 7047 bx lr + 522 .cfi_endproc + 523 .LFE142: + 525 .section .text.HAL_ADC_Start,"ax",%progbits + 526 .align 1 + 527 .global HAL_ADC_Start + 528 .syntax unified + 529 .thumb + 530 .thumb_func + 532 HAL_ADC_Start: + 533 .LVL17: + 534 .LFB145: + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __IO uint32_t counter = 0; + 535 .loc 1 731 1 is_stmt 1 view -0 + 536 .cfi_startproc + 537 @ args = 0, pretend = 0, frame = 8 + 538 @ frame_needed = 0, uses_anonymous_args = 0 + 539 @ link register save eliminated. + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __IO uint32_t counter = 0; + 540 .loc 1 731 1 is_stmt 0 view .LVU191 + 541 0000 82B0 sub sp, sp, #8 + 542 .LCFI4: + 543 .cfi_def_cfa_offset 8 + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 544 .loc 1 732 3 is_stmt 1 view .LVU192 + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 545 .loc 1 732 17 is_stmt 0 view .LVU193 + 546 0002 0023 movs r3, #0 + 547 0004 0193 str r3, [sp, #4] + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + 548 .loc 1 735 3 is_stmt 1 view .LVU194 + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 549 .loc 1 736 3 view .LVU195 + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 550 .loc 1 739 3 view .LVU196 + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 551 .loc 1 739 3 view .LVU197 + 552 0006 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 553 000a 012B cmp r3, #1 + 554 000c 7ED0 beq .L44 + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + ARM GAS /tmp/ccMiLMrd.s page 47 + + + 555 .loc 1 739 3 discriminator 2 view .LVU198 + 556 000e 0123 movs r3, #1 + 557 0010 80F83C30 strb r3, [r0, #60] + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 558 .loc 1 739 3 discriminator 2 view .LVU199 + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 559 .loc 1 744 3 view .LVU200 + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 560 .loc 1 744 11 is_stmt 0 view .LVU201 + 561 0014 0368 ldr r3, [r0] + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 562 .loc 1 744 21 view .LVU202 + 563 0016 9A68 ldr r2, [r3, #8] + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 564 .loc 1 744 5 view .LVU203 + 565 0018 12F0010F tst r2, #1 + 566 001c 13D1 bne .L35 + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 567 .loc 1 747 5 is_stmt 1 view .LVU204 + 568 001e 9A68 ldr r2, [r3, #8] + 569 0020 42F00102 orr r2, r2, #1 + 570 0024 9A60 str r2, [r3, #8] + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) + 571 .loc 1 751 5 view .LVU205 + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) + 572 .loc 1 751 53 is_stmt 0 view .LVU206 + 573 0026 3D4B ldr r3, .L52 + 574 0028 1B68 ldr r3, [r3] + 575 002a 3D4A ldr r2, .L52+4 + 576 002c A2FB0323 umull r2, r3, r2, r3 + 577 0030 9B0C lsrs r3, r3, #18 + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) + 578 .loc 1 751 34 view .LVU207 + 579 0032 03EB4303 add r3, r3, r3, lsl #1 + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) + 580 .loc 1 751 13 view .LVU208 + 581 0036 0193 str r3, [sp, #4] + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 582 .loc 1 752 5 is_stmt 1 view .LVU209 + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 583 .loc 1 752 10 is_stmt 0 view .LVU210 + 584 0038 02E0 b .L36 + 585 .L37: + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 586 .loc 1 754 7 is_stmt 1 view .LVU211 + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 587 .loc 1 754 14 is_stmt 0 view .LVU212 + 588 003a 019B ldr r3, [sp, #4] + 589 003c 013B subs r3, r3, #1 + 590 003e 0193 str r3, [sp, #4] + 591 .L36: + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 592 .loc 1 752 19 is_stmt 1 view .LVU213 + 593 0040 019B ldr r3, [sp, #4] + 594 0042 002B cmp r3, #0 + 595 0044 F9D1 bne .L37 + 596 .L35: + ARM GAS /tmp/ccMiLMrd.s page 48 + + + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 597 .loc 1 759 3 view .LVU214 + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 598 .loc 1 759 6 is_stmt 0 view .LVU215 + 599 0046 0368 ldr r3, [r0] + 600 0048 9A68 ldr r2, [r3, #8] + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 601 .loc 1 759 5 view .LVU216 + 602 004a 12F0010F tst r2, #1 + 603 004e 52D0 beq .L38 + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + 604 .loc 1 764 5 is_stmt 1 view .LVU217 + 605 0050 016C ldr r1, [r0, #64] + 606 0052 344A ldr r2, .L52+8 + 607 0054 0A40 ands r2, r2, r1 + 608 0056 42F48072 orr r2, r2, #256 + 609 005a 0264 str r2, [r0, #64] + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 610 .loc 1 770 5 view .LVU218 + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 611 .loc 1 770 9 is_stmt 0 view .LVU219 + 612 005c 5A68 ldr r2, [r3, #4] + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 613 .loc 1 770 8 view .LVU220 + 614 005e 12F4806F tst r2, #1024 + 615 0062 05D0 beq .L39 + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 616 .loc 1 772 7 is_stmt 1 view .LVU221 + 617 0064 026C ldr r2, [r0, #64] + 618 0066 22F44052 bic r2, r2, #12288 + 619 006a 42F48052 orr r2, r2, #4096 + 620 006e 0264 str r2, [r0, #64] + 621 .L39: + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 622 .loc 1 776 5 view .LVU222 + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 623 .loc 1 776 9 is_stmt 0 view .LVU223 + 624 0070 026C ldr r2, [r0, #64] + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 625 .loc 1 776 8 view .LVU224 + 626 0072 12F4805F tst r2, #4096 + 627 0076 19D0 beq .L40 + 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 628 .loc 1 779 7 is_stmt 1 view .LVU225 + 629 0078 426C ldr r2, [r0, #68] + 630 007a 22F00602 bic r2, r2, #6 + 631 007e 4264 str r2, [r0, #68] + 632 .L41: + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 633 .loc 1 790 5 view .LVU226 + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 634 .loc 1 790 5 view .LVU227 + 635 0080 0022 movs r2, #0 + 636 0082 80F83C20 strb r2, [r0, #60] + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 637 .loc 1 790 5 view .LVU228 + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + ARM GAS /tmp/ccMiLMrd.s page 49 + + + 638 .loc 1 794 5 view .LVU229 + 639 0086 6FF02202 mvn r2, #34 + 640 008a 1A60 str r2, [r3] + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 641 .loc 1 797 5 view .LVU230 + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 642 .loc 1 797 8 is_stmt 0 view .LVU231 + 643 008c 264B ldr r3, .L52+12 + 644 008e 5B68 ldr r3, [r3, #4] + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 645 .loc 1 797 7 view .LVU232 + 646 0090 13F01F0F tst r3, #31 + 647 0094 0DD1 bne .L42 + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 648 .loc 1 800 7 is_stmt 1 view .LVU233 + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 649 .loc 1 800 15 is_stmt 0 view .LVU234 + 650 0096 0368 ldr r3, [r0] + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 651 .loc 1 800 25 view .LVU235 + 652 0098 9A68 ldr r2, [r3, #8] + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 653 .loc 1 800 9 view .LVU236 + 654 009a 12F0405F tst r2, #805306368 + 655 009e 37D1 bne .L45 + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 656 .loc 1 803 9 is_stmt 1 view .LVU237 + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 657 .loc 1 803 23 is_stmt 0 view .LVU238 + 658 00a0 9A68 ldr r2, [r3, #8] + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 659 .loc 1 803 29 view .LVU239 + 660 00a2 42F08042 orr r2, r2, #1073741824 + 661 00a6 9A60 str r2, [r3, #8] + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 662 .loc 1 838 10 view .LVU240 + 663 00a8 0020 movs r0, #0 + 664 .LVL18: + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 665 .loc 1 838 10 view .LVU241 + 666 00aa 2DE0 b .L34 + 667 .LVL19: + 668 .L40: + 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 669 .loc 1 784 7 is_stmt 1 view .LVU242 + 670 00ac 0022 movs r2, #0 + 671 00ae 4264 str r2, [r0, #68] + 672 00b0 E6E7 b .L41 + 673 .L42: + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 674 .loc 1 809 7 view .LVU243 + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 675 .loc 1 809 15 is_stmt 0 view .LVU244 + 676 00b2 0368 ldr r3, [r0] + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 677 .loc 1 809 9 view .LVU245 + 678 00b4 1D4A ldr r2, .L52+16 + ARM GAS /tmp/ccMiLMrd.s page 50 + + + 679 00b6 9342 cmp r3, r2 + 680 00b8 0AD0 beq .L50 + 681 .L43: + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 682 .loc 1 817 7 is_stmt 1 view .LVU246 + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 683 .loc 1 817 11 is_stmt 0 view .LVU247 + 684 00ba 1B4B ldr r3, .L52+12 + 685 00bc 5B68 ldr r3, [r3, #4] + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 686 .loc 1 817 9 view .LVU248 + 687 00be 13F0100F tst r3, #16 + 688 00c2 27D1 bne .L46 + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 689 .loc 1 820 9 is_stmt 1 view .LVU249 + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 690 .loc 1 820 17 is_stmt 0 view .LVU250 + 691 00c4 0368 ldr r3, [r0] + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 692 .loc 1 820 11 view .LVU251 + 693 00c6 1A4A ldr r2, .L52+20 + 694 00c8 9342 cmp r3, r2 + 695 00ca 0AD0 beq .L51 + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 696 .loc 1 838 10 view .LVU252 + 697 00cc 0020 movs r0, #0 + 698 .LVL20: + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 699 .loc 1 838 10 view .LVU253 + 700 00ce 1BE0 b .L34 + 701 .LVL21: + 702 .L50: + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 703 .loc 1 809 54 discriminator 1 view .LVU254 + 704 00d0 9A68 ldr r2, [r3, #8] + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 705 .loc 1 809 35 discriminator 1 view .LVU255 + 706 00d2 12F0405F tst r2, #805306368 + 707 00d6 F0D1 bne .L43 + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 708 .loc 1 812 11 is_stmt 1 view .LVU256 + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 709 .loc 1 812 25 is_stmt 0 view .LVU257 + 710 00d8 9A68 ldr r2, [r3, #8] + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 711 .loc 1 812 31 view .LVU258 + 712 00da 42F08042 orr r2, r2, #1073741824 + 713 00de 9A60 str r2, [r3, #8] + 714 00e0 EBE7 b .L43 + 715 .L51: + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 716 .loc 1 820 56 discriminator 1 view .LVU259 + 717 00e2 9A68 ldr r2, [r3, #8] + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 718 .loc 1 820 37 discriminator 1 view .LVU260 + 719 00e4 12F0405F tst r2, #805306368 + 720 00e8 16D1 bne .L48 + ARM GAS /tmp/ccMiLMrd.s page 51 + + + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 721 .loc 1 823 11 is_stmt 1 view .LVU261 + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 722 .loc 1 823 25 is_stmt 0 view .LVU262 + 723 00ea 9A68 ldr r2, [r3, #8] + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 724 .loc 1 823 31 view .LVU263 + 725 00ec 42F08042 orr r2, r2, #1073741824 + 726 00f0 9A60 str r2, [r3, #8] + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 727 .loc 1 838 10 view .LVU264 + 728 00f2 0020 movs r0, #0 + 729 .LVL22: + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 730 .loc 1 838 10 view .LVU265 + 731 00f4 08E0 b .L34 + 732 .LVL23: + 733 .L38: + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 734 .loc 1 831 5 is_stmt 1 view .LVU266 + 735 00f6 036C ldr r3, [r0, #64] + 736 00f8 43F01003 orr r3, r3, #16 + 737 00fc 0364 str r3, [r0, #64] + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 738 .loc 1 834 5 view .LVU267 + 739 00fe 436C ldr r3, [r0, #68] + 740 0100 43F00103 orr r3, r3, #1 + 741 0104 4364 str r3, [r0, #68] + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 742 .loc 1 838 10 is_stmt 0 view .LVU268 + 743 0106 0020 movs r0, #0 + 744 .LVL24: + 745 .L34: + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 746 .loc 1 839 1 view .LVU269 + 747 0108 02B0 add sp, sp, #8 + 748 .LCFI5: + 749 .cfi_remember_state + 750 .cfi_def_cfa_offset 0 + 751 @ sp needed + 752 010a 7047 bx lr + 753 .LVL25: + 754 .L44: + 755 .LCFI6: + 756 .cfi_restore_state + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 757 .loc 1 739 3 discriminator 1 view .LVU270 + 758 010c 0220 movs r0, #2 + 759 .LVL26: + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 760 .loc 1 739 3 discriminator 1 view .LVU271 + 761 010e FBE7 b .L34 + 762 .LVL27: + 763 .L45: + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 764 .loc 1 838 10 view .LVU272 + 765 0110 0020 movs r0, #0 + ARM GAS /tmp/ccMiLMrd.s page 52 + + + 766 .LVL28: + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 767 .loc 1 838 10 view .LVU273 + 768 0112 F9E7 b .L34 + 769 .LVL29: + 770 .L46: + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 771 .loc 1 838 10 view .LVU274 + 772 0114 0020 movs r0, #0 + 773 .LVL30: + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 774 .loc 1 838 10 view .LVU275 + 775 0116 F7E7 b .L34 + 776 .LVL31: + 777 .L48: + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 778 .loc 1 838 10 view .LVU276 + 779 0118 0020 movs r0, #0 + 780 .LVL32: + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 781 .loc 1 838 10 view .LVU277 + 782 011a F5E7 b .L34 + 783 .L53: + 784 .align 2 + 785 .L52: + 786 011c 00000000 .word SystemCoreClock + 787 0120 83DE1B43 .word 1125899907 + 788 0124 FEF8FFFF .word -1794 + 789 0128 00230140 .word 1073816320 + 790 012c 00200140 .word 1073815552 + 791 0130 00220140 .word 1073816064 + 792 .cfi_endproc + 793 .LFE145: + 795 .section .text.HAL_ADC_Stop,"ax",%progbits + 796 .align 1 + 797 .global HAL_ADC_Stop + 798 .syntax unified + 799 .thumb + 800 .thumb_func + 802 HAL_ADC_Stop: + 803 .LVL33: + 804 .LFB146: + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check the parameters */ + 805 .loc 1 852 1 is_stmt 1 view -0 + 806 .cfi_startproc + 807 @ args = 0, pretend = 0, frame = 0 + 808 @ frame_needed = 0, uses_anonymous_args = 0 + 809 @ link register save eliminated. + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 810 .loc 1 854 3 view .LVU279 + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 811 .loc 1 857 3 view .LVU280 + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 812 .loc 1 857 3 view .LVU281 + 813 0000 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 814 0004 012B cmp r3, #1 + 815 0006 17D0 beq .L57 + ARM GAS /tmp/ccMiLMrd.s page 53 + + + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 816 .loc 1 857 3 discriminator 2 view .LVU282 + 817 0008 0123 movs r3, #1 + 818 000a 80F83C30 strb r3, [r0, #60] + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 819 .loc 1 857 3 discriminator 2 view .LVU283 + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 820 .loc 1 861 3 view .LVU284 + 821 000e 0268 ldr r2, [r0] + 822 0010 9368 ldr r3, [r2, #8] + 823 0012 23F00103 bic r3, r3, #1 + 824 0016 9360 str r3, [r2, #8] + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 825 .loc 1 864 3 view .LVU285 + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 826 .loc 1 864 6 is_stmt 0 view .LVU286 + 827 0018 0368 ldr r3, [r0] + 828 001a 9B68 ldr r3, [r3, #8] + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 829 .loc 1 864 5 view .LVU287 + 830 001c 13F0010F tst r3, #1 + 831 0020 05D1 bne .L56 + 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + 832 .loc 1 867 5 is_stmt 1 view .LVU288 + 833 0022 026C ldr r2, [r0, #64] + 834 0024 054B ldr r3, .L58 + 835 0026 1340 ands r3, r3, r2 + 836 0028 43F00103 orr r3, r3, #1 + 837 002c 0364 str r3, [r0, #64] + 838 .L56: + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 839 .loc 1 873 3 view .LVU289 + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 840 .loc 1 873 3 view .LVU290 + 841 002e 0023 movs r3, #0 + 842 0030 80F83C30 strb r3, [r0, #60] + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 843 .loc 1 873 3 view .LVU291 + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 844 .loc 1 876 3 view .LVU292 + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 845 .loc 1 876 10 is_stmt 0 view .LVU293 + 846 0034 1846 mov r0, r3 + 847 .LVL34: + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 848 .loc 1 876 10 view .LVU294 + 849 0036 7047 bx lr + 850 .LVL35: + 851 .L57: + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 852 .loc 1 857 3 discriminator 1 view .LVU295 + 853 0038 0220 movs r0, #2 + 854 .LVL36: + 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 855 .loc 1 877 1 view .LVU296 + 856 003a 7047 bx lr + 857 .L59: + ARM GAS /tmp/ccMiLMrd.s page 54 + + + 858 .align 2 + 859 .L58: + 860 003c FEEEFFFF .word -4354 + 861 .cfi_endproc + 862 .LFE146: + 864 .section .text.HAL_ADC_PollForConversion,"ax",%progbits + 865 .align 1 + 866 .global HAL_ADC_PollForConversion + 867 .syntax unified + 868 .thumb + 869 .thumb_func + 871 HAL_ADC_PollForConversion: + 872 .LVL37: + 873 .LFB147: + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t tickstart = 0; + 874 .loc 1 895 1 is_stmt 1 view -0 + 875 .cfi_startproc + 876 @ args = 0, pretend = 0, frame = 0 + 877 @ frame_needed = 0, uses_anonymous_args = 0 + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t tickstart = 0; + 878 .loc 1 895 1 is_stmt 0 view .LVU298 + 879 0000 70B5 push {r4, r5, r6, lr} + 880 .LCFI7: + 881 .cfi_def_cfa_offset 16 + 882 .cfi_offset 4, -16 + 883 .cfi_offset 5, -12 + 884 .cfi_offset 6, -8 + 885 .cfi_offset 14, -4 + 886 0002 0446 mov r4, r0 + 887 0004 0D46 mov r5, r1 + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 888 .loc 1 896 3 is_stmt 1 view .LVU299 + 889 .LVL38: + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) + 890 .loc 1 904 3 view .LVU300 + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) + 891 .loc 1 904 7 is_stmt 0 view .LVU301 + 892 0006 0368 ldr r3, [r0] + 893 0008 9A68 ldr r2, [r3, #8] + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) + 894 .loc 1 904 6 view .LVU302 + 895 000a 12F4806F tst r2, #1024 + 896 000e 03D0 beq .L61 + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 897 .loc 1 905 7 view .LVU303 + 898 0010 9B68 ldr r3, [r3, #8] + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) + 899 .loc 1 904 57 discriminator 1 view .LVU304 + 900 0012 13F4807F tst r3, #256 + 901 0016 19D1 bne .L74 + 902 .L61: + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 903 .loc 1 917 3 is_stmt 1 view .LVU305 + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 904 .loc 1 917 15 is_stmt 0 view .LVU306 + 905 0018 FFF7FEFF bl HAL_GetTick + 906 .LVL39: + ARM GAS /tmp/ccMiLMrd.s page 55 + + + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 907 .loc 1 917 15 view .LVU307 + 908 001c 0646 mov r6, r0 + 909 .LVL40: + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 910 .loc 1 920 3 is_stmt 1 view .LVU308 + 911 .L64: + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 912 .loc 1 920 9 view .LVU309 + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 913 .loc 1 920 11 is_stmt 0 view .LVU310 + 914 001e 2368 ldr r3, [r4] + 915 0020 1A68 ldr r2, [r3] + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 916 .loc 1 920 9 view .LVU311 + 917 0022 12F0020F tst r2, #2 + 918 0026 20D1 bne .L75 + 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 919 .loc 1 923 5 is_stmt 1 view .LVU312 + 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 920 .loc 1 923 7 is_stmt 0 view .LVU313 + 921 0028 B5F1FF3F cmp r5, #-1 + 922 002c F7D0 beq .L64 + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 923 .loc 1 925 7 is_stmt 1 view .LVU314 + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 924 .loc 1 925 9 is_stmt 0 view .LVU315 + 925 002e B5B9 cbnz r5, .L76 + 926 .L65: + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 927 .loc 1 928 9 is_stmt 1 view .LVU316 + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 928 .loc 1 928 14 is_stmt 0 view .LVU317 + 929 0030 2368 ldr r3, [r4] + 930 0032 1B68 ldr r3, [r3] + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 931 .loc 1 928 11 view .LVU318 + 932 0034 13F0020F tst r3, #2 + 933 0038 F1D1 bne .L64 + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 934 .loc 1 931 11 is_stmt 1 view .LVU319 + 935 003a 236C ldr r3, [r4, #64] + 936 003c 43F00403 orr r3, r3, #4 + 937 0040 2364 str r3, [r4, #64] + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 938 .loc 1 934 11 view .LVU320 + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 939 .loc 1 934 11 view .LVU321 + 940 0042 0023 movs r3, #0 + 941 0044 84F83C30 strb r3, [r4, #60] + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 942 .loc 1 934 11 view .LVU322 + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 943 .loc 1 936 11 view .LVU323 + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 944 .loc 1 936 18 is_stmt 0 view .LVU324 + 945 0048 0320 movs r0, #3 + ARM GAS /tmp/ccMiLMrd.s page 56 + + + 946 004a 33E0 b .L62 + 947 .LVL41: + 948 .L74: + 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 949 .loc 1 908 5 is_stmt 1 view .LVU325 + 950 004c 036C ldr r3, [r0, #64] + 951 004e 43F02003 orr r3, r3, #32 + 952 0052 0364 str r3, [r0, #64] + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 953 .loc 1 911 5 view .LVU326 + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 954 .loc 1 911 5 view .LVU327 + 955 0054 0023 movs r3, #0 + 956 0056 80F83C30 strb r3, [r0, #60] + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 957 .loc 1 911 5 view .LVU328 + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 958 .loc 1 913 5 view .LVU329 + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 959 .loc 1 913 12 is_stmt 0 view .LVU330 + 960 005a 0120 movs r0, #1 + 961 .LVL42: + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 962 .loc 1 913 12 view .LVU331 + 963 005c 2AE0 b .L62 + 964 .LVL43: + 965 .L76: + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 966 .loc 1 925 30 discriminator 1 view .LVU332 + 967 005e FFF7FEFF bl HAL_GetTick + 968 .LVL44: + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 969 .loc 1 925 44 discriminator 1 view .LVU333 + 970 0062 801B subs r0, r0, r6 + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 971 .loc 1 925 25 discriminator 1 view .LVU334 + 972 0064 A842 cmp r0, r5 + 973 0066 DAD9 bls .L64 + 974 0068 E2E7 b .L65 + 975 .L75: + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 976 .loc 1 943 3 is_stmt 1 view .LVU335 + 977 006a 6FF01202 mvn r2, #18 + 978 006e 1A60 str r2, [r3] + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 979 .loc 1 946 3 view .LVU336 + 980 0070 236C ldr r3, [r4, #64] + 981 0072 43F40073 orr r3, r3, #512 + 982 0076 2364 str r3, [r4, #64] + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) && + 983 .loc 1 954 3 view .LVU337 + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) && + 984 .loc 1 954 6 is_stmt 0 view .LVU338 + 985 0078 2368 ldr r3, [r4] + 986 007a 9A68 ldr r2, [r3, #8] + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) && + 987 .loc 1 954 5 view .LVU339 + ARM GAS /tmp/ccMiLMrd.s page 57 + + + 988 007c 12F0405F tst r2, #805306368 + 989 0080 17D1 bne .L69 + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + 990 .loc 1 955 17 view .LVU340 + 991 0082 A269 ldr r2, [r4, #24] + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) && + 992 .loc 1 954 60 discriminator 1 view .LVU341 + 993 0084 BAB9 cbnz r2, .L70 + 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + 994 .loc 1 956 7 view .LVU342 + 995 0086 DA6A ldr r2, [r3, #44] + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + 996 .loc 1 955 60 view .LVU343 + 997 0088 12F4700F tst r2, #15728640 + 998 008c 03D0 beq .L68 + 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 999 .loc 1 957 7 view .LVU344 + 1000 008e 9B68 ldr r3, [r3, #8] + 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + 1001 .loc 1 956 56 view .LVU345 + 1002 0090 13F4806F tst r3, #1024 + 1003 0094 11D1 bne .L71 + 1004 .L68: + 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1005 .loc 1 960 5 is_stmt 1 view .LVU346 + 1006 0096 236C ldr r3, [r4, #64] + 1007 0098 23F48073 bic r3, r3, #256 + 1008 009c 2364 str r3, [r4, #64] + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1009 .loc 1 962 5 view .LVU347 + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1010 .loc 1 962 9 is_stmt 0 view .LVU348 + 1011 009e 236C ldr r3, [r4, #64] + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1012 .loc 1 962 8 view .LVU349 + 1013 00a0 13F4805F tst r3, #4096 + 1014 00a4 0BD1 bne .L72 + 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1015 .loc 1 964 7 is_stmt 1 view .LVU350 + 1016 00a6 236C ldr r3, [r4, #64] + 1017 00a8 43F00103 orr r3, r3, #1 + 1018 00ac 2364 str r3, [r4, #64] + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1019 .loc 1 969 10 is_stmt 0 view .LVU351 + 1020 00ae 0020 movs r0, #0 + 1021 00b0 00E0 b .L62 + 1022 .L69: + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1023 .loc 1 969 10 view .LVU352 + 1024 00b2 0020 movs r0, #0 + 1025 .LVL45: + 1026 .L62: + 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1027 .loc 1 970 1 view .LVU353 + 1028 00b4 70BD pop {r4, r5, r6, pc} + 1029 .LVL46: + 1030 .L70: + ARM GAS /tmp/ccMiLMrd.s page 58 + + + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1031 .loc 1 969 10 view .LVU354 + 1032 00b6 0020 movs r0, #0 + 1033 00b8 FCE7 b .L62 + 1034 .L71: + 1035 00ba 0020 movs r0, #0 + 1036 00bc FAE7 b .L62 + 1037 .L72: + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1038 .loc 1 969 10 view .LVU355 + 1039 00be 0020 movs r0, #0 + 1040 00c0 F8E7 b .L62 + 1041 .cfi_endproc + 1042 .LFE147: + 1044 .section .text.HAL_ADC_PollForEvent,"ax",%progbits + 1045 .align 1 + 1046 .global HAL_ADC_PollForEvent + 1047 .syntax unified + 1048 .thumb + 1049 .thumb_func + 1051 HAL_ADC_PollForEvent: + 1052 .LVL47: + 1053 .LFB148: + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t tickstart = 0; + 1054 .loc 1 984 1 is_stmt 1 view -0 + 1055 .cfi_startproc + 1056 @ args = 0, pretend = 0, frame = 0 + 1057 @ frame_needed = 0, uses_anonymous_args = 0 + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t tickstart = 0; + 1058 .loc 1 984 1 is_stmt 0 view .LVU357 + 1059 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 1060 .LCFI8: + 1061 .cfi_def_cfa_offset 24 + 1062 .cfi_offset 4, -24 + 1063 .cfi_offset 5, -20 + 1064 .cfi_offset 6, -16 + 1065 .cfi_offset 7, -12 + 1066 .cfi_offset 8, -8 + 1067 .cfi_offset 14, -4 + 1068 0004 0546 mov r5, r0 + 1069 0006 0E46 mov r6, r1 + 1070 0008 1746 mov r7, r2 + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1071 .loc 1 985 3 is_stmt 1 view .LVU358 + 1072 .LVL48: + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_EVENT_TYPE(EventType)); + 1073 .loc 1 988 3 view .LVU359 + 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1074 .loc 1 989 3 view .LVU360 + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1075 .loc 1 992 3 view .LVU361 + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1076 .loc 1 992 15 is_stmt 0 view .LVU362 + 1077 000a FFF7FEFF bl HAL_GetTick + 1078 .LVL49: + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1079 .loc 1 992 15 view .LVU363 + ARM GAS /tmp/ccMiLMrd.s page 59 + + + 1080 000e 8046 mov r8, r0 + 1081 .LVL50: + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1082 .loc 1 995 3 is_stmt 1 view .LVU364 + 1083 .L79: + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1084 .loc 1 995 9 view .LVU365 + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1085 .loc 1 995 11 is_stmt 0 view .LVU366 + 1086 0010 2C68 ldr r4, [r5] + 1087 0012 2368 ldr r3, [r4] + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1088 .loc 1 995 9 view .LVU367 + 1089 0014 36EA0303 bics r3, r6, r3 + 1090 0018 18D0 beq .L86 + 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1091 .loc 1 998 5 is_stmt 1 view .LVU368 + 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1092 .loc 1 998 7 is_stmt 0 view .LVU369 + 1093 001a B7F1FF3F cmp r7, #-1 + 1094 001e F7D0 beq .L79 +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1095 .loc 1 1000 7 is_stmt 1 view .LVU370 +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1096 .loc 1 1000 9 is_stmt 0 view .LVU371 + 1097 0020 6FB9 cbnz r7, .L87 + 1098 .L80: +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1099 .loc 1 1003 9 is_stmt 1 view .LVU372 +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1100 .loc 1 1003 14 is_stmt 0 view .LVU373 + 1101 0022 2B68 ldr r3, [r5] + 1102 0024 1B68 ldr r3, [r3] +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1103 .loc 1 1003 11 view .LVU374 + 1104 0026 36EA0303 bics r3, r6, r3 + 1105 002a F1D0 beq .L79 +1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1106 .loc 1 1006 11 is_stmt 1 view .LVU375 + 1107 002c 2B6C ldr r3, [r5, #64] + 1108 002e 43F00403 orr r3, r3, #4 + 1109 0032 2B64 str r3, [r5, #64] +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1110 .loc 1 1009 11 view .LVU376 +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1111 .loc 1 1009 11 view .LVU377 + 1112 0034 0023 movs r3, #0 + 1113 0036 85F83C30 strb r3, [r5, #60] +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1114 .loc 1 1009 11 view .LVU378 +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1115 .loc 1 1011 11 view .LVU379 +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1116 .loc 1 1011 18 is_stmt 0 view .LVU380 + 1117 003a 0320 movs r0, #3 + 1118 003c 14E0 b .L82 + 1119 .L87: + ARM GAS /tmp/ccMiLMrd.s page 60 + + +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1120 .loc 1 1000 30 discriminator 1 view .LVU381 + 1121 003e FFF7FEFF bl HAL_GetTick + 1122 .LVL51: +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1123 .loc 1 1000 44 discriminator 1 view .LVU382 + 1124 0042 A0EB0800 sub r0, r0, r8 +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1125 .loc 1 1000 25 discriminator 1 view .LVU383 + 1126 0046 B842 cmp r0, r7 + 1127 0048 E2D9 bls .L79 + 1128 004a EAE7 b .L80 + 1129 .L86: +1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1130 .loc 1 1018 3 is_stmt 1 view .LVU384 +1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1131 .loc 1 1018 5 is_stmt 0 view .LVU385 + 1132 004c 012E cmp r6, #1 + 1133 004e 0DD0 beq .L88 +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC error code to overrun */ + 1134 .loc 1 1030 5 is_stmt 1 view .LVU386 + 1135 0050 2B6C ldr r3, [r5, #64] + 1136 0052 43F48063 orr r3, r3, #1024 + 1137 0056 2B64 str r3, [r5, #64] +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1138 .loc 1 1032 5 view .LVU387 + 1139 0058 6B6C ldr r3, [r5, #68] + 1140 005a 43F00203 orr r3, r3, #2 + 1141 005e 6B64 str r3, [r5, #68] +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1142 .loc 1 1035 5 view .LVU388 + 1143 0060 6FF02003 mvn r3, #32 + 1144 0064 2360 str r3, [r4] +1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1145 .loc 1 1039 10 is_stmt 0 view .LVU389 + 1146 0066 0020 movs r0, #0 + 1147 .L82: +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1148 .loc 1 1040 1 view .LVU390 + 1149 0068 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 1150 .LVL52: + 1151 .L88: +1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1152 .loc 1 1021 5 is_stmt 1 view .LVU391 + 1153 006c 2B6C ldr r3, [r5, #64] + 1154 006e 43F48033 orr r3, r3, #65536 + 1155 0072 2B64 str r3, [r5, #64] +1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1156 .loc 1 1024 5 view .LVU392 + 1157 0074 6FF00103 mvn r3, #1 + 1158 0078 2360 str r3, [r4] +1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1159 .loc 1 1039 10 is_stmt 0 view .LVU393 + 1160 007a 0020 movs r0, #0 + 1161 007c F4E7 b .L82 + 1162 .cfi_endproc + 1163 .LFE148: + ARM GAS /tmp/ccMiLMrd.s page 61 + + + 1165 .section .text.HAL_ADC_Start_IT,"ax",%progbits + 1166 .align 1 + 1167 .global HAL_ADC_Start_IT + 1168 .syntax unified + 1169 .thumb + 1170 .thumb_func + 1172 HAL_ADC_Start_IT: + 1173 .LVL53: + 1174 .LFB149: +1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __IO uint32_t counter = 0; + 1175 .loc 1 1050 1 is_stmt 1 view -0 + 1176 .cfi_startproc + 1177 @ args = 0, pretend = 0, frame = 8 + 1178 @ frame_needed = 0, uses_anonymous_args = 0 + 1179 @ link register save eliminated. +1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __IO uint32_t counter = 0; + 1180 .loc 1 1050 1 is_stmt 0 view .LVU395 + 1181 0000 82B0 sub sp, sp, #8 + 1182 .LCFI9: + 1183 .cfi_def_cfa_offset 8 +1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1184 .loc 1 1051 3 is_stmt 1 view .LVU396 +1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1185 .loc 1 1051 17 is_stmt 0 view .LVU397 + 1186 0002 0023 movs r3, #0 + 1187 0004 0193 str r3, [sp, #4] +1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + 1188 .loc 1 1054 3 is_stmt 1 view .LVU398 +1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1189 .loc 1 1055 3 view .LVU399 +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1190 .loc 1 1058 3 view .LVU400 +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1191 .loc 1 1058 3 view .LVU401 + 1192 0006 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 1193 000a 012B cmp r3, #1 + 1194 000c 00F08480 beq .L100 +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1195 .loc 1 1058 3 discriminator 2 view .LVU402 + 1196 0010 0123 movs r3, #1 + 1197 0012 80F83C30 strb r3, [r0, #60] +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1198 .loc 1 1058 3 discriminator 2 view .LVU403 +1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1199 .loc 1 1063 3 view .LVU404 +1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1200 .loc 1 1063 11 is_stmt 0 view .LVU405 + 1201 0016 0368 ldr r3, [r0] +1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1202 .loc 1 1063 21 view .LVU406 + 1203 0018 9A68 ldr r2, [r3, #8] +1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1204 .loc 1 1063 5 view .LVU407 + 1205 001a 12F0010F tst r2, #1 + 1206 001e 13D1 bne .L91 +1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1207 .loc 1 1066 5 is_stmt 1 view .LVU408 + ARM GAS /tmp/ccMiLMrd.s page 62 + + + 1208 0020 9A68 ldr r2, [r3, #8] + 1209 0022 42F00102 orr r2, r2, #1 + 1210 0026 9A60 str r2, [r3, #8] +1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) + 1211 .loc 1 1070 5 view .LVU409 +1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) + 1212 .loc 1 1070 53 is_stmt 0 view .LVU410 + 1213 0028 3F4B ldr r3, .L108 + 1214 002a 1B68 ldr r3, [r3] + 1215 002c 3F4A ldr r2, .L108+4 + 1216 002e A2FB0323 umull r2, r3, r2, r3 + 1217 0032 9B0C lsrs r3, r3, #18 +1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) + 1218 .loc 1 1070 34 view .LVU411 + 1219 0034 03EB4303 add r3, r3, r3, lsl #1 +1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) + 1220 .loc 1 1070 13 view .LVU412 + 1221 0038 0193 str r3, [sp, #4] +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1222 .loc 1 1071 5 is_stmt 1 view .LVU413 +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1223 .loc 1 1071 10 is_stmt 0 view .LVU414 + 1224 003a 02E0 b .L92 + 1225 .L93: +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1226 .loc 1 1073 7 is_stmt 1 view .LVU415 +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1227 .loc 1 1073 14 is_stmt 0 view .LVU416 + 1228 003c 019B ldr r3, [sp, #4] + 1229 003e 013B subs r3, r3, #1 + 1230 0040 0193 str r3, [sp, #4] + 1231 .L92: +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1232 .loc 1 1071 19 is_stmt 1 view .LVU417 + 1233 0042 019B ldr r3, [sp, #4] + 1234 0044 002B cmp r3, #0 + 1235 0046 F9D1 bne .L93 + 1236 .L91: +1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1237 .loc 1 1078 3 view .LVU418 +1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1238 .loc 1 1078 6 is_stmt 0 view .LVU419 + 1239 0048 0368 ldr r3, [r0] + 1240 004a 9A68 ldr r2, [r3, #8] +1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1241 .loc 1 1078 5 view .LVU420 + 1242 004c 12F0010F tst r2, #1 + 1243 0050 57D0 beq .L94 +1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + 1244 .loc 1 1083 5 is_stmt 1 view .LVU421 + 1245 0052 016C ldr r1, [r0, #64] + 1246 0054 364A ldr r2, .L108+8 + 1247 0056 0A40 ands r2, r2, r1 + 1248 0058 42F48072 orr r2, r2, #256 + 1249 005c 0264 str r2, [r0, #64] +1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1250 .loc 1 1089 5 view .LVU422 + ARM GAS /tmp/ccMiLMrd.s page 63 + + +1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1251 .loc 1 1089 9 is_stmt 0 view .LVU423 + 1252 005e 5A68 ldr r2, [r3, #4] +1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1253 .loc 1 1089 8 view .LVU424 + 1254 0060 12F4806F tst r2, #1024 + 1255 0064 05D0 beq .L95 +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1256 .loc 1 1091 7 is_stmt 1 view .LVU425 + 1257 0066 026C ldr r2, [r0, #64] + 1258 0068 22F44052 bic r2, r2, #12288 + 1259 006c 42F48052 orr r2, r2, #4096 + 1260 0070 0264 str r2, [r0, #64] + 1261 .L95: +1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1262 .loc 1 1095 5 view .LVU426 +1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1263 .loc 1 1095 9 is_stmt 0 view .LVU427 + 1264 0072 026C ldr r2, [r0, #64] +1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1265 .loc 1 1095 8 view .LVU428 + 1266 0074 12F4805F tst r2, #4096 + 1267 0078 1ED0 beq .L96 +1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1268 .loc 1 1098 7 is_stmt 1 view .LVU429 + 1269 007a 426C ldr r2, [r0, #68] + 1270 007c 22F00602 bic r2, r2, #6 + 1271 0080 4264 str r2, [r0, #68] + 1272 .L97: +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1273 .loc 1 1109 5 view .LVU430 +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1274 .loc 1 1109 5 view .LVU431 + 1275 0082 0022 movs r2, #0 + 1276 0084 80F83C20 strb r2, [r0, #60] +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1277 .loc 1 1109 5 view .LVU432 +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1278 .loc 1 1113 5 view .LVU433 + 1279 0088 6FF02202 mvn r2, #34 + 1280 008c 1A60 str r2, [r3] +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1281 .loc 1 1116 5 view .LVU434 + 1282 008e 0268 ldr r2, [r0] + 1283 0090 5168 ldr r1, [r2, #4] + 1284 0092 284B ldr r3, .L108+12 + 1285 0094 0B43 orrs r3, r3, r1 + 1286 0096 5360 str r3, [r2, #4] +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1287 .loc 1 1119 5 view .LVU435 +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1288 .loc 1 1119 8 is_stmt 0 view .LVU436 + 1289 0098 274B ldr r3, .L108+16 + 1290 009a 5B68 ldr r3, [r3, #4] +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1291 .loc 1 1119 7 view .LVU437 + 1292 009c 13F01F0F tst r3, #31 + ARM GAS /tmp/ccMiLMrd.s page 64 + + + 1293 00a0 0DD1 bne .L98 +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1294 .loc 1 1122 7 is_stmt 1 view .LVU438 +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1295 .loc 1 1122 15 is_stmt 0 view .LVU439 + 1296 00a2 0368 ldr r3, [r0] +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1297 .loc 1 1122 25 view .LVU440 + 1298 00a4 9A68 ldr r2, [r3, #8] +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1299 .loc 1 1122 9 view .LVU441 + 1300 00a6 12F0405F tst r2, #805306368 + 1301 00aa 37D1 bne .L101 +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1302 .loc 1 1125 9 is_stmt 1 view .LVU442 +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1303 .loc 1 1125 23 is_stmt 0 view .LVU443 + 1304 00ac 9A68 ldr r2, [r3, #8] +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1305 .loc 1 1125 29 view .LVU444 + 1306 00ae 42F08042 orr r2, r2, #1073741824 + 1307 00b2 9A60 str r2, [r3, #8] +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1308 .loc 1 1160 10 view .LVU445 + 1309 00b4 0020 movs r0, #0 + 1310 .LVL54: +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1311 .loc 1 1160 10 view .LVU446 + 1312 00b6 2DE0 b .L90 + 1313 .LVL55: + 1314 .L96: +1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1315 .loc 1 1103 7 is_stmt 1 view .LVU447 + 1316 00b8 0022 movs r2, #0 + 1317 00ba 4264 str r2, [r0, #68] + 1318 00bc E1E7 b .L97 + 1319 .L98: +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1320 .loc 1 1131 7 view .LVU448 +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1321 .loc 1 1131 15 is_stmt 0 view .LVU449 + 1322 00be 0368 ldr r3, [r0] +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1323 .loc 1 1131 9 view .LVU450 + 1324 00c0 1E4A ldr r2, .L108+20 + 1325 00c2 9342 cmp r3, r2 + 1326 00c4 0AD0 beq .L106 + 1327 .L99: +1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1328 .loc 1 1139 7 is_stmt 1 view .LVU451 +1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1329 .loc 1 1139 11 is_stmt 0 view .LVU452 + 1330 00c6 1C4B ldr r3, .L108+16 + 1331 00c8 5B68 ldr r3, [r3, #4] +1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1332 .loc 1 1139 9 view .LVU453 + 1333 00ca 13F0100F tst r3, #16 + ARM GAS /tmp/ccMiLMrd.s page 65 + + + 1334 00ce 27D1 bne .L102 +1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1335 .loc 1 1142 9 is_stmt 1 view .LVU454 +1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1336 .loc 1 1142 17 is_stmt 0 view .LVU455 + 1337 00d0 0368 ldr r3, [r0] +1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1338 .loc 1 1142 11 view .LVU456 + 1339 00d2 1B4A ldr r2, .L108+24 + 1340 00d4 9342 cmp r3, r2 + 1341 00d6 0AD0 beq .L107 +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1342 .loc 1 1160 10 view .LVU457 + 1343 00d8 0020 movs r0, #0 + 1344 .LVL56: +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1345 .loc 1 1160 10 view .LVU458 + 1346 00da 1BE0 b .L90 + 1347 .LVL57: + 1348 .L106: +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1349 .loc 1 1131 54 discriminator 1 view .LVU459 + 1350 00dc 9A68 ldr r2, [r3, #8] +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1351 .loc 1 1131 35 discriminator 1 view .LVU460 + 1352 00de 12F0405F tst r2, #805306368 + 1353 00e2 F0D1 bne .L99 +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1354 .loc 1 1134 11 is_stmt 1 view .LVU461 +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1355 .loc 1 1134 25 is_stmt 0 view .LVU462 + 1356 00e4 9A68 ldr r2, [r3, #8] +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1357 .loc 1 1134 31 view .LVU463 + 1358 00e6 42F08042 orr r2, r2, #1073741824 + 1359 00ea 9A60 str r2, [r3, #8] + 1360 00ec EBE7 b .L99 + 1361 .L107: +1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1362 .loc 1 1142 56 discriminator 1 view .LVU464 + 1363 00ee 9A68 ldr r2, [r3, #8] +1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1364 .loc 1 1142 37 discriminator 1 view .LVU465 + 1365 00f0 12F0405F tst r2, #805306368 + 1366 00f4 16D1 bne .L104 +1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1367 .loc 1 1145 11 is_stmt 1 view .LVU466 +1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1368 .loc 1 1145 25 is_stmt 0 view .LVU467 + 1369 00f6 9A68 ldr r2, [r3, #8] +1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1370 .loc 1 1145 31 view .LVU468 + 1371 00f8 42F08042 orr r2, r2, #1073741824 + 1372 00fc 9A60 str r2, [r3, #8] +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1373 .loc 1 1160 10 view .LVU469 + 1374 00fe 0020 movs r0, #0 + ARM GAS /tmp/ccMiLMrd.s page 66 + + + 1375 .LVL58: +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1376 .loc 1 1160 10 view .LVU470 + 1377 0100 08E0 b .L90 + 1378 .LVL59: + 1379 .L94: +1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1380 .loc 1 1153 5 is_stmt 1 view .LVU471 + 1381 0102 036C ldr r3, [r0, #64] + 1382 0104 43F01003 orr r3, r3, #16 + 1383 0108 0364 str r3, [r0, #64] +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1384 .loc 1 1156 5 view .LVU472 + 1385 010a 436C ldr r3, [r0, #68] + 1386 010c 43F00103 orr r3, r3, #1 + 1387 0110 4364 str r3, [r0, #68] +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1388 .loc 1 1160 10 is_stmt 0 view .LVU473 + 1389 0112 0020 movs r0, #0 + 1390 .LVL60: + 1391 .L90: +1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1392 .loc 1 1161 1 view .LVU474 + 1393 0114 02B0 add sp, sp, #8 + 1394 .LCFI10: + 1395 .cfi_remember_state + 1396 .cfi_def_cfa_offset 0 + 1397 @ sp needed + 1398 0116 7047 bx lr + 1399 .LVL61: + 1400 .L100: + 1401 .LCFI11: + 1402 .cfi_restore_state +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1403 .loc 1 1058 3 discriminator 1 view .LVU475 + 1404 0118 0220 movs r0, #2 + 1405 .LVL62: +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1406 .loc 1 1058 3 discriminator 1 view .LVU476 + 1407 011a FBE7 b .L90 + 1408 .LVL63: + 1409 .L101: +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1410 .loc 1 1160 10 view .LVU477 + 1411 011c 0020 movs r0, #0 + 1412 .LVL64: +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1413 .loc 1 1160 10 view .LVU478 + 1414 011e F9E7 b .L90 + 1415 .LVL65: + 1416 .L102: +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1417 .loc 1 1160 10 view .LVU479 + 1418 0120 0020 movs r0, #0 + 1419 .LVL66: +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1420 .loc 1 1160 10 view .LVU480 + ARM GAS /tmp/ccMiLMrd.s page 67 + + + 1421 0122 F7E7 b .L90 + 1422 .LVL67: + 1423 .L104: +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1424 .loc 1 1160 10 view .LVU481 + 1425 0124 0020 movs r0, #0 + 1426 .LVL68: +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1427 .loc 1 1160 10 view .LVU482 + 1428 0126 F5E7 b .L90 + 1429 .L109: + 1430 .align 2 + 1431 .L108: + 1432 0128 00000000 .word SystemCoreClock + 1433 012c 83DE1B43 .word 1125899907 + 1434 0130 FEF8FFFF .word -1794 + 1435 0134 20000004 .word 67108896 + 1436 0138 00230140 .word 1073816320 + 1437 013c 00200140 .word 1073815552 + 1438 0140 00220140 .word 1073816064 + 1439 .cfi_endproc + 1440 .LFE149: + 1442 .section .text.HAL_ADC_Stop_IT,"ax",%progbits + 1443 .align 1 + 1444 .global HAL_ADC_Stop_IT + 1445 .syntax unified + 1446 .thumb + 1447 .thumb_func + 1449 HAL_ADC_Stop_IT: + 1450 .LVL69: + 1451 .LFB150: +1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check the parameters */ + 1452 .loc 1 1173 1 is_stmt 1 view -0 + 1453 .cfi_startproc + 1454 @ args = 0, pretend = 0, frame = 0 + 1455 @ frame_needed = 0, uses_anonymous_args = 0 + 1456 @ link register save eliminated. +1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1457 .loc 1 1175 3 view .LVU484 +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1458 .loc 1 1178 3 view .LVU485 +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1459 .loc 1 1178 3 view .LVU486 + 1460 0000 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 1461 0004 012B cmp r3, #1 + 1462 0006 1BD0 beq .L113 +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1463 .loc 1 1178 3 discriminator 2 view .LVU487 + 1464 0008 0123 movs r3, #1 + 1465 000a 80F83C30 strb r3, [r0, #60] +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1466 .loc 1 1178 3 discriminator 2 view .LVU488 +1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1467 .loc 1 1182 3 view .LVU489 + 1468 000e 0268 ldr r2, [r0] + 1469 0010 9368 ldr r3, [r2, #8] + 1470 0012 23F00103 bic r3, r3, #1 + ARM GAS /tmp/ccMiLMrd.s page 68 + + + 1471 0016 9360 str r3, [r2, #8] +1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1472 .loc 1 1185 3 view .LVU490 +1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1473 .loc 1 1185 6 is_stmt 0 view .LVU491 + 1474 0018 0368 ldr r3, [r0] + 1475 001a 9A68 ldr r2, [r3, #8] +1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1476 .loc 1 1185 5 view .LVU492 + 1477 001c 12F0010F tst r2, #1 + 1478 0020 09D1 bne .L112 +1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1479 .loc 1 1188 5 is_stmt 1 view .LVU493 + 1480 0022 5968 ldr r1, [r3, #4] + 1481 0024 074A ldr r2, .L114 + 1482 0026 0A40 ands r2, r2, r1 + 1483 0028 5A60 str r2, [r3, #4] +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + 1484 .loc 1 1191 5 view .LVU494 + 1485 002a 026C ldr r2, [r0, #64] + 1486 002c 064B ldr r3, .L114+4 + 1487 002e 1340 ands r3, r3, r2 + 1488 0030 43F00103 orr r3, r3, #1 + 1489 0034 0364 str r3, [r0, #64] + 1490 .L112: +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1491 .loc 1 1197 3 view .LVU495 +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1492 .loc 1 1197 3 view .LVU496 + 1493 0036 0023 movs r3, #0 + 1494 0038 80F83C30 strb r3, [r0, #60] +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1495 .loc 1 1197 3 view .LVU497 +1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1496 .loc 1 1200 3 view .LVU498 +1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1497 .loc 1 1200 10 is_stmt 0 view .LVU499 + 1498 003c 1846 mov r0, r3 + 1499 .LVL70: +1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1500 .loc 1 1200 10 view .LVU500 + 1501 003e 7047 bx lr + 1502 .LVL71: + 1503 .L113: +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1504 .loc 1 1178 3 discriminator 1 view .LVU501 + 1505 0040 0220 movs r0, #2 + 1506 .LVL72: +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1507 .loc 1 1201 1 view .LVU502 + 1508 0042 7047 bx lr + 1509 .L115: + 1510 .align 2 + 1511 .L114: + 1512 0044 DFFFFFFB .word -67108897 + 1513 0048 FEEEFFFF .word -4354 + 1514 .cfi_endproc + ARM GAS /tmp/ccMiLMrd.s page 69 + + + 1515 .LFE150: + 1517 .section .text.HAL_ADC_Start_DMA,"ax",%progbits + 1518 .align 1 + 1519 .global HAL_ADC_Start_DMA + 1520 .syntax unified + 1521 .thumb + 1522 .thumb_func + 1524 HAL_ADC_Start_DMA: + 1525 .LVL73: + 1526 .LFB152: +1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __IO uint32_t counter = 0; + 1527 .loc 1 1376 1 is_stmt 1 view -0 + 1528 .cfi_startproc + 1529 @ args = 0, pretend = 0, frame = 8 + 1530 @ frame_needed = 0, uses_anonymous_args = 0 +1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __IO uint32_t counter = 0; + 1531 .loc 1 1376 1 is_stmt 0 view .LVU504 + 1532 0000 30B5 push {r4, r5, lr} + 1533 .LCFI12: + 1534 .cfi_def_cfa_offset 12 + 1535 .cfi_offset 4, -12 + 1536 .cfi_offset 5, -8 + 1537 .cfi_offset 14, -4 + 1538 0002 83B0 sub sp, sp, #12 + 1539 .LCFI13: + 1540 .cfi_def_cfa_offset 24 + 1541 0004 1346 mov r3, r2 +1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1542 .loc 1 1377 3 is_stmt 1 view .LVU505 +1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1543 .loc 1 1377 17 is_stmt 0 view .LVU506 + 1544 0006 0022 movs r2, #0 + 1545 .LVL74: +1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1546 .loc 1 1377 17 view .LVU507 + 1547 0008 0192 str r2, [sp, #4] +1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + 1548 .loc 1 1380 3 is_stmt 1 view .LVU508 +1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1549 .loc 1 1381 3 view .LVU509 +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1550 .loc 1 1384 3 view .LVU510 +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1551 .loc 1 1384 3 view .LVU511 + 1552 000a 90F83C20 ldrb r2, [r0, #60] @ zero_extendqisi2 + 1553 000e 012A cmp r2, #1 + 1554 0010 00F09B80 beq .L127 + 1555 0014 0446 mov r4, r0 +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1556 .loc 1 1384 3 discriminator 2 view .LVU512 + 1557 0016 0122 movs r2, #1 + 1558 0018 80F83C20 strb r2, [r0, #60] +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1559 .loc 1 1384 3 discriminator 2 view .LVU513 +1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1560 .loc 1 1389 3 view .LVU514 +1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + ARM GAS /tmp/ccMiLMrd.s page 70 + + + 1561 .loc 1 1389 11 is_stmt 0 view .LVU515 + 1562 001c 0268 ldr r2, [r0] +1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1563 .loc 1 1389 21 view .LVU516 + 1564 001e 9068 ldr r0, [r2, #8] + 1565 .LVL75: +1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1566 .loc 1 1389 5 view .LVU517 + 1567 0020 10F0010F tst r0, #1 + 1568 0024 13D1 bne .L118 +1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1569 .loc 1 1392 5 is_stmt 1 view .LVU518 + 1570 0026 9068 ldr r0, [r2, #8] + 1571 0028 40F00100 orr r0, r0, #1 + 1572 002c 9060 str r0, [r2, #8] +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) + 1573 .loc 1 1396 5 view .LVU519 +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) + 1574 .loc 1 1396 53 is_stmt 0 view .LVU520 + 1575 002e 4B4A ldr r2, .L135 + 1576 0030 1068 ldr r0, [r2] + 1577 0032 4B4A ldr r2, .L135+4 + 1578 0034 A2FB0020 umull r2, r0, r2, r0 + 1579 0038 800C lsrs r0, r0, #18 +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) + 1580 .loc 1 1396 34 view .LVU521 + 1581 003a 00EB4000 add r0, r0, r0, lsl #1 +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) + 1582 .loc 1 1396 13 view .LVU522 + 1583 003e 0190 str r0, [sp, #4] +1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1584 .loc 1 1397 5 is_stmt 1 view .LVU523 +1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1585 .loc 1 1397 10 is_stmt 0 view .LVU524 + 1586 0040 02E0 b .L119 + 1587 .L120: +1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1588 .loc 1 1399 7 is_stmt 1 view .LVU525 +1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1589 .loc 1 1399 14 is_stmt 0 view .LVU526 + 1590 0042 0198 ldr r0, [sp, #4] + 1591 0044 0138 subs r0, r0, #1 + 1592 0046 0190 str r0, [sp, #4] + 1593 .L119: +1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1594 .loc 1 1397 19 is_stmt 1 view .LVU527 + 1595 0048 0198 ldr r0, [sp, #4] + 1596 004a 0028 cmp r0, #0 + 1597 004c F9D1 bne .L120 + 1598 .L118: +1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1599 .loc 1 1404 3 view .LVU528 +1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1600 .loc 1 1404 6 is_stmt 0 view .LVU529 + 1601 004e 2068 ldr r0, [r4] + 1602 0050 8268 ldr r2, [r0, #8] +1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + ARM GAS /tmp/ccMiLMrd.s page 71 + + + 1603 .loc 1 1404 5 view .LVU530 + 1604 0052 12F0010F tst r2, #1 + 1605 0056 6DD0 beq .L121 +1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + 1606 .loc 1 1409 5 is_stmt 1 view .LVU531 + 1607 0058 256C ldr r5, [r4, #64] + 1608 005a 424A ldr r2, .L135+8 + 1609 005c 2A40 ands r2, r2, r5 + 1610 005e 42F48072 orr r2, r2, #256 + 1611 0062 2264 str r2, [r4, #64] +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1612 .loc 1 1415 5 view .LVU532 +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1613 .loc 1 1415 9 is_stmt 0 view .LVU533 + 1614 0064 4268 ldr r2, [r0, #4] +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1615 .loc 1 1415 8 view .LVU534 + 1616 0066 12F4806F tst r2, #1024 + 1617 006a 05D0 beq .L122 +1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1618 .loc 1 1417 7 is_stmt 1 view .LVU535 + 1619 006c 226C ldr r2, [r4, #64] + 1620 006e 22F44052 bic r2, r2, #12288 + 1621 0072 42F48052 orr r2, r2, #4096 + 1622 0076 2264 str r2, [r4, #64] + 1623 .L122: +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1624 .loc 1 1421 5 view .LVU536 +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1625 .loc 1 1421 9 is_stmt 0 view .LVU537 + 1626 0078 226C ldr r2, [r4, #64] +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1627 .loc 1 1421 8 view .LVU538 + 1628 007a 12F4805F tst r2, #4096 + 1629 007e 34D0 beq .L123 +1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1630 .loc 1 1424 7 is_stmt 1 view .LVU539 + 1631 0080 626C ldr r2, [r4, #68] + 1632 0082 22F00602 bic r2, r2, #6 + 1633 0086 6264 str r2, [r4, #68] + 1634 .L124: +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1635 .loc 1 1435 5 view .LVU540 +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1636 .loc 1 1435 5 view .LVU541 + 1637 0088 0022 movs r2, #0 + 1638 008a 84F83C20 strb r2, [r4, #60] +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1639 .loc 1 1435 5 view .LVU542 +1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1640 .loc 1 1438 5 view .LVU543 +1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1641 .loc 1 1438 9 is_stmt 0 view .LVU544 + 1642 008e A26B ldr r2, [r4, #56] +1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1643 .loc 1 1438 40 view .LVU545 + 1644 0090 3548 ldr r0, .L135+12 + ARM GAS /tmp/ccMiLMrd.s page 72 + + + 1645 0092 D063 str r0, [r2, #60] +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1646 .loc 1 1441 5 is_stmt 1 view .LVU546 +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1647 .loc 1 1441 9 is_stmt 0 view .LVU547 + 1648 0094 A26B ldr r2, [r4, #56] +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1649 .loc 1 1441 44 view .LVU548 + 1650 0096 3548 ldr r0, .L135+16 + 1651 0098 1064 str r0, [r2, #64] +1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1652 .loc 1 1444 5 is_stmt 1 view .LVU549 +1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1653 .loc 1 1444 9 is_stmt 0 view .LVU550 + 1654 009a A26B ldr r2, [r4, #56] +1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1655 .loc 1 1444 41 view .LVU551 + 1656 009c 3448 ldr r0, .L135+20 + 1657 009e D064 str r0, [r2, #76] +1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1658 .loc 1 1452 5 is_stmt 1 view .LVU552 + 1659 00a0 2268 ldr r2, [r4] + 1660 00a2 6FF02200 mvn r0, #34 + 1661 00a6 1060 str r0, [r2] +1455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1662 .loc 1 1455 5 view .LVU553 + 1663 00a8 2068 ldr r0, [r4] + 1664 00aa 4268 ldr r2, [r0, #4] + 1665 00ac 42F08062 orr r2, r2, #67108864 + 1666 00b0 4260 str r2, [r0, #4] +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1667 .loc 1 1458 5 view .LVU554 +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1668 .loc 1 1458 9 is_stmt 0 view .LVU555 + 1669 00b2 2068 ldr r0, [r4] +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1670 .loc 1 1458 19 view .LVU556 + 1671 00b4 8268 ldr r2, [r0, #8] +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1672 .loc 1 1458 25 view .LVU557 + 1673 00b6 42F48072 orr r2, r2, #256 + 1674 00ba 8260 str r2, [r0, #8] +1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1675 .loc 1 1461 5 is_stmt 1 view .LVU558 +1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1676 .loc 1 1461 55 is_stmt 0 view .LVU559 + 1677 00bc 2068 ldr r0, [r4] +1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1678 .loc 1 1461 5 view .LVU560 + 1679 00be 0A46 mov r2, r1 + 1680 00c0 00F14C01 add r1, r0, #76 + 1681 .LVL76: +1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1682 .loc 1 1461 5 view .LVU561 + 1683 00c4 A06B ldr r0, [r4, #56] + 1684 00c6 FFF7FEFF bl HAL_DMA_Start_IT + 1685 .LVL77: + ARM GAS /tmp/ccMiLMrd.s page 73 + + +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1686 .loc 1 1464 5 is_stmt 1 view .LVU562 +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1687 .loc 1 1464 8 is_stmt 0 view .LVU563 + 1688 00ca 2A4B ldr r3, .L135+24 + 1689 00cc 5B68 ldr r3, [r3, #4] +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1690 .loc 1 1464 7 view .LVU564 + 1691 00ce 13F01F0F tst r3, #31 + 1692 00d2 0DD1 bne .L125 +1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1693 .loc 1 1467 7 is_stmt 1 view .LVU565 +1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1694 .loc 1 1467 15 is_stmt 0 view .LVU566 + 1695 00d4 2368 ldr r3, [r4] +1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1696 .loc 1 1467 25 view .LVU567 + 1697 00d6 9A68 ldr r2, [r3, #8] +1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1698 .loc 1 1467 9 view .LVU568 + 1699 00d8 12F0405F tst r2, #805306368 + 1700 00dc 37D1 bne .L128 +1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1701 .loc 1 1470 9 is_stmt 1 view .LVU569 +1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1702 .loc 1 1470 23 is_stmt 0 view .LVU570 + 1703 00de 9A68 ldr r2, [r3, #8] +1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1704 .loc 1 1470 29 view .LVU571 + 1705 00e0 42F08042 orr r2, r2, #1073741824 + 1706 00e4 9A60 str r2, [r3, #8] +1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1707 .loc 1 1504 10 view .LVU572 + 1708 00e6 0020 movs r0, #0 + 1709 00e8 2DE0 b .L117 + 1710 .LVL78: + 1711 .L123: +1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1712 .loc 1 1429 7 is_stmt 1 view .LVU573 + 1713 00ea 0022 movs r2, #0 + 1714 00ec 6264 str r2, [r4, #68] + 1715 00ee CBE7 b .L124 + 1716 .LVL79: + 1717 .L125: +1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1718 .loc 1 1476 7 view .LVU574 +1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1719 .loc 1 1476 15 is_stmt 0 view .LVU575 + 1720 00f0 2368 ldr r3, [r4] +1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1721 .loc 1 1476 9 view .LVU576 + 1722 00f2 214A ldr r2, .L135+28 + 1723 00f4 9342 cmp r3, r2 + 1724 00f6 0AD0 beq .L133 + 1725 .L126: +1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1726 .loc 1 1483 7 is_stmt 1 view .LVU577 + ARM GAS /tmp/ccMiLMrd.s page 74 + + +1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1727 .loc 1 1483 11 is_stmt 0 view .LVU578 + 1728 00f8 1E4B ldr r3, .L135+24 + 1729 00fa 5B68 ldr r3, [r3, #4] +1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1730 .loc 1 1483 9 view .LVU579 + 1731 00fc 13F0100F tst r3, #16 + 1732 0100 27D1 bne .L129 +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1733 .loc 1 1486 9 is_stmt 1 view .LVU580 +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1734 .loc 1 1486 17 is_stmt 0 view .LVU581 + 1735 0102 2368 ldr r3, [r4] +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1736 .loc 1 1486 11 view .LVU582 + 1737 0104 1D4A ldr r2, .L135+32 + 1738 0106 9342 cmp r3, r2 + 1739 0108 0AD0 beq .L134 +1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1740 .loc 1 1504 10 view .LVU583 + 1741 010a 0020 movs r0, #0 + 1742 010c 1BE0 b .L117 + 1743 .L133: +1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1744 .loc 1 1476 54 discriminator 1 view .LVU584 + 1745 010e 9A68 ldr r2, [r3, #8] +1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1746 .loc 1 1476 35 discriminator 1 view .LVU585 + 1747 0110 12F0405F tst r2, #805306368 + 1748 0114 F0D1 bne .L126 +1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1749 .loc 1 1479 11 is_stmt 1 view .LVU586 +1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1750 .loc 1 1479 25 is_stmt 0 view .LVU587 + 1751 0116 9A68 ldr r2, [r3, #8] +1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1752 .loc 1 1479 31 view .LVU588 + 1753 0118 42F08042 orr r2, r2, #1073741824 + 1754 011c 9A60 str r2, [r3, #8] + 1755 011e EBE7 b .L126 + 1756 .L134: +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1757 .loc 1 1486 56 discriminator 1 view .LVU589 + 1758 0120 9A68 ldr r2, [r3, #8] +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1759 .loc 1 1486 37 discriminator 1 view .LVU590 + 1760 0122 12F0405F tst r2, #805306368 + 1761 0126 16D1 bne .L131 +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1762 .loc 1 1489 11 is_stmt 1 view .LVU591 +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1763 .loc 1 1489 25 is_stmt 0 view .LVU592 + 1764 0128 9A68 ldr r2, [r3, #8] +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1765 .loc 1 1489 31 view .LVU593 + 1766 012a 42F08042 orr r2, r2, #1073741824 + 1767 012e 9A60 str r2, [r3, #8] + ARM GAS /tmp/ccMiLMrd.s page 75 + + +1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1768 .loc 1 1504 10 view .LVU594 + 1769 0130 0020 movs r0, #0 + 1770 0132 08E0 b .L117 + 1771 .LVL80: + 1772 .L121: +1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1773 .loc 1 1497 5 is_stmt 1 view .LVU595 + 1774 0134 236C ldr r3, [r4, #64] + 1775 .LVL81: +1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1776 .loc 1 1497 5 is_stmt 0 view .LVU596 + 1777 0136 43F01003 orr r3, r3, #16 + 1778 013a 2364 str r3, [r4, #64] +1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1779 .loc 1 1500 5 is_stmt 1 view .LVU597 + 1780 013c 636C ldr r3, [r4, #68] + 1781 013e 43F00103 orr r3, r3, #1 + 1782 0142 6364 str r3, [r4, #68] +1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1783 .loc 1 1504 10 is_stmt 0 view .LVU598 + 1784 0144 0020 movs r0, #0 + 1785 .LVL82: + 1786 .L117: +1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1787 .loc 1 1505 1 view .LVU599 + 1788 0146 03B0 add sp, sp, #12 + 1789 .LCFI14: + 1790 .cfi_remember_state + 1791 .cfi_def_cfa_offset 12 + 1792 @ sp needed + 1793 0148 30BD pop {r4, r5, pc} + 1794 .LVL83: + 1795 .L127: + 1796 .LCFI15: + 1797 .cfi_restore_state +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1798 .loc 1 1384 3 discriminator 1 view .LVU600 + 1799 014a 0220 movs r0, #2 + 1800 .LVL84: +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1801 .loc 1 1384 3 discriminator 1 view .LVU601 + 1802 014c FBE7 b .L117 + 1803 .LVL85: + 1804 .L128: +1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1805 .loc 1 1504 10 view .LVU602 + 1806 014e 0020 movs r0, #0 + 1807 0150 F9E7 b .L117 + 1808 .L129: +1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1809 .loc 1 1504 10 view .LVU603 + 1810 0152 0020 movs r0, #0 + 1811 0154 F7E7 b .L117 + 1812 .L131: +1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1813 .loc 1 1504 10 view .LVU604 + ARM GAS /tmp/ccMiLMrd.s page 76 + + + 1814 0156 0020 movs r0, #0 + 1815 0158 F5E7 b .L117 + 1816 .L136: + 1817 015a 00BF .align 2 + 1818 .L135: + 1819 015c 00000000 .word SystemCoreClock + 1820 0160 83DE1B43 .word 1125899907 + 1821 0164 FEF8FFFF .word -1794 + 1822 0168 00000000 .word ADC_DMAConvCplt + 1823 016c 00000000 .word ADC_DMAHalfConvCplt + 1824 0170 00000000 .word ADC_DMAError + 1825 0174 00230140 .word 1073816320 + 1826 0178 00200140 .word 1073815552 + 1827 017c 00220140 .word 1073816064 + 1828 .cfi_endproc + 1829 .LFE152: + 1831 .section .text.HAL_ADC_Stop_DMA,"ax",%progbits + 1832 .align 1 + 1833 .global HAL_ADC_Stop_DMA + 1834 .syntax unified + 1835 .thumb + 1836 .thumb_func + 1838 HAL_ADC_Stop_DMA: + 1839 .LVL86: + 1840 .LFB153: +1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 1841 .loc 1 1514 1 is_stmt 1 view -0 + 1842 .cfi_startproc + 1843 @ args = 0, pretend = 0, frame = 0 + 1844 @ frame_needed = 0, uses_anonymous_args = 0 +1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1845 .loc 1 1515 3 view .LVU606 +1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1846 .loc 1 1518 3 view .LVU607 +1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1847 .loc 1 1521 3 view .LVU608 +1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1848 .loc 1 1521 3 view .LVU609 + 1849 0000 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 1850 0004 012B cmp r3, #1 + 1851 0006 33D0 beq .L141 +1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 1852 .loc 1 1514 1 is_stmt 0 view .LVU610 + 1853 0008 10B5 push {r4, lr} + 1854 .LCFI16: + 1855 .cfi_def_cfa_offset 8 + 1856 .cfi_offset 4, -8 + 1857 .cfi_offset 14, -4 + 1858 000a 0446 mov r4, r0 +1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1859 .loc 1 1521 3 is_stmt 1 discriminator 2 view .LVU611 + 1860 000c 0123 movs r3, #1 + 1861 000e 80F83C30 strb r3, [r0, #60] +1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1862 .loc 1 1521 3 discriminator 2 view .LVU612 +1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1863 .loc 1 1525 3 view .LVU613 + ARM GAS /tmp/ccMiLMrd.s page 77 + + + 1864 0012 0268 ldr r2, [r0] + 1865 0014 9368 ldr r3, [r2, #8] + 1866 0016 23F00103 bic r3, r3, #1 + 1867 001a 9360 str r3, [r2, #8] +1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1868 .loc 1 1528 3 view .LVU614 +1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1869 .loc 1 1528 6 is_stmt 0 view .LVU615 + 1870 001c 0368 ldr r3, [r0] + 1871 001e 9A68 ldr r2, [r3, #8] +1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1872 .loc 1 1528 5 view .LVU616 + 1873 0020 12F0010F tst r2, #1 + 1874 0024 1FD1 bne .L142 +1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1875 .loc 1 1531 5 is_stmt 1 view .LVU617 +1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1876 .loc 1 1531 19 is_stmt 0 view .LVU618 + 1877 0026 9A68 ldr r2, [r3, #8] +1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1878 .loc 1 1531 25 view .LVU619 + 1879 0028 22F48072 bic r2, r2, #256 + 1880 002c 9A60 str r2, [r3, #8] +1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1881 .loc 1 1535 5 is_stmt 1 view .LVU620 +1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1882 .loc 1 1535 13 is_stmt 0 view .LVU621 + 1883 002e 806B ldr r0, [r0, #56] + 1884 .LVL87: +1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1885 .loc 1 1535 25 view .LVU622 + 1886 0030 90F83530 ldrb r3, [r0, #53] @ zero_extendqisi2 + 1887 0034 DBB2 uxtb r3, r3 +1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1888 .loc 1 1535 8 view .LVU623 + 1889 0036 022B cmp r3, #2 + 1890 0038 0CD0 beq .L148 +1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1891 .loc 1 1515 21 view .LVU624 + 1892 003a 0020 movs r0, #0 + 1893 .LVL88: + 1894 .L140: +1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1895 .loc 1 1548 5 is_stmt 1 view .LVU625 + 1896 003c 2268 ldr r2, [r4] + 1897 003e 5368 ldr r3, [r2, #4] + 1898 0040 23F08063 bic r3, r3, #67108864 + 1899 0044 5360 str r3, [r2, #4] +1551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + 1900 .loc 1 1551 5 view .LVU626 + 1901 0046 226C ldr r2, [r4, #64] + 1902 0048 0A4B ldr r3, .L149 + 1903 004a 1340 ands r3, r3, r2 + 1904 004c 43F00103 orr r3, r3, #1 + 1905 0050 2364 str r3, [r4, #64] + 1906 0052 09E0 b .L139 + 1907 .LVL89: + ARM GAS /tmp/ccMiLMrd.s page 78 + + + 1908 .L148: +1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1909 .loc 1 1537 7 view .LVU627 +1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1910 .loc 1 1537 24 is_stmt 0 view .LVU628 + 1911 0054 FFF7FEFF bl HAL_DMA_Abort + 1912 .LVL90: +1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1913 .loc 1 1540 7 is_stmt 1 view .LVU629 +1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 1914 .loc 1 1540 10 is_stmt 0 view .LVU630 + 1915 0058 0028 cmp r0, #0 + 1916 005a EFD0 beq .L140 +1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1917 .loc 1 1543 9 is_stmt 1 view .LVU631 + 1918 005c 236C ldr r3, [r4, #64] + 1919 005e 43F04003 orr r3, r3, #64 + 1920 0062 2364 str r3, [r4, #64] + 1921 0064 EAE7 b .L140 + 1922 .LVL91: + 1923 .L142: +1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1924 .loc 1 1515 21 is_stmt 0 view .LVU632 + 1925 0066 0020 movs r0, #0 + 1926 .LVL92: + 1927 .L139: +1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1928 .loc 1 1557 3 is_stmt 1 view .LVU633 +1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1929 .loc 1 1557 3 view .LVU634 + 1930 0068 0023 movs r3, #0 + 1931 006a 84F83C30 strb r3, [r4, #60] +1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1932 .loc 1 1557 3 view .LVU635 +1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1933 .loc 1 1560 3 view .LVU636 +1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1934 .loc 1 1561 1 is_stmt 0 view .LVU637 + 1935 006e 10BD pop {r4, pc} + 1936 .LVL93: + 1937 .L141: + 1938 .LCFI17: + 1939 .cfi_def_cfa_offset 0 + 1940 .cfi_restore 4 + 1941 .cfi_restore 14 +1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1942 .loc 1 1521 3 discriminator 1 view .LVU638 + 1943 0070 0220 movs r0, #2 + 1944 .LVL94: +1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1945 .loc 1 1561 1 view .LVU639 + 1946 0072 7047 bx lr + 1947 .L150: + 1948 .align 2 + 1949 .L149: + 1950 0074 FEEEFFFF .word -4354 + 1951 .cfi_endproc + ARM GAS /tmp/ccMiLMrd.s page 79 + + + 1952 .LFE153: + 1954 .section .text.HAL_ADC_GetValue,"ax",%progbits + 1955 .align 1 + 1956 .global HAL_ADC_GetValue + 1957 .syntax unified + 1958 .thumb + 1959 .thumb_func + 1961 HAL_ADC_GetValue: + 1962 .LVL95: + 1963 .LFB154: +1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return the selected ADC converted value */ + 1964 .loc 1 1570 1 is_stmt 1 view -0 + 1965 .cfi_startproc + 1966 @ args = 0, pretend = 0, frame = 0 + 1967 @ frame_needed = 0, uses_anonymous_args = 0 + 1968 @ link register save eliminated. +1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1969 .loc 1 1572 3 view .LVU641 +1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1970 .loc 1 1572 14 is_stmt 0 view .LVU642 + 1971 0000 0368 ldr r3, [r0] +1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 1972 .loc 1 1572 24 view .LVU643 + 1973 0002 D86C ldr r0, [r3, #76] + 1974 .LVL96: +1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1975 .loc 1 1573 1 view .LVU644 + 1976 0004 7047 bx lr + 1977 .cfi_endproc + 1978 .LFE154: + 1980 .section .text.HAL_ADC_ConvCpltCallback,"ax",%progbits + 1981 .align 1 + 1982 .weak HAL_ADC_ConvCpltCallback + 1983 .syntax unified + 1984 .thumb + 1985 .thumb_func + 1987 HAL_ADC_ConvCpltCallback: + 1988 .LVL97: + 1989 .LFB155: +1582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ + 1990 .loc 1 1582 1 is_stmt 1 view -0 + 1991 .cfi_startproc + 1992 @ args = 0, pretend = 0, frame = 0 + 1993 @ frame_needed = 0, uses_anonymous_args = 0 + 1994 @ link register save eliminated. +1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 1995 .loc 1 1584 3 view .LVU646 +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 1996 .loc 1 1588 1 is_stmt 0 view .LVU647 + 1997 0000 7047 bx lr + 1998 .cfi_endproc + 1999 .LFE155: + 2001 .section .text.HAL_ADC_ConvHalfCpltCallback,"ax",%progbits + 2002 .align 1 + 2003 .weak HAL_ADC_ConvHalfCpltCallback + 2004 .syntax unified + 2005 .thumb + ARM GAS /tmp/ccMiLMrd.s page 80 + + + 2006 .thumb_func + 2008 HAL_ADC_ConvHalfCpltCallback: + 2009 .LVL98: + 2010 .LFB156: +1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ + 2011 .loc 1 1597 1 is_stmt 1 view -0 + 2012 .cfi_startproc + 2013 @ args = 0, pretend = 0, frame = 0 + 2014 @ frame_needed = 0, uses_anonymous_args = 0 + 2015 @ link register save eliminated. +1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 2016 .loc 1 1599 3 view .LVU649 +1603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2017 .loc 1 1603 1 is_stmt 0 view .LVU650 + 2018 0000 7047 bx lr + 2019 .cfi_endproc + 2020 .LFE156: + 2022 .section .text.ADC_DMAHalfConvCplt,"ax",%progbits + 2023 .align 1 + 2024 .syntax unified + 2025 .thumb + 2026 .thumb_func + 2028 ADC_DMAHalfConvCplt: + 2029 .LVL99: + 2030 .LFB165: +1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief DMA transfer complete callback. +1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified DMA module. +1996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval None +1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +1998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +2000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Retrieve ADC handle corresponding to current DMA handle */ +2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; +2002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Update state machine on conversion status if not in error state */ +2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) +2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +2006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Update ADC state machine */ +2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); +2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +2009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Determine whether any further conversion upcoming on group regular */ +2010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* by external trigger, continuous mode or scan sequence on going. */ +2011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Note: On STM32F7, there is no independent flag of end of sequence. */ +2012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* The test of scan sequence on going is done either with scan */ +2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* sequence disabled or with end of conversion flag set to */ +2014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* of end of sequence. */ +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && +2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) && +2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || +2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) +2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +2020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Disable ADC end of single conversion interrupt on group regular */ +2021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Note: Overrun interrupt was enabled with EOC interrupt in */ +2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ + ARM GAS /tmp/ccMiLMrd.s page 81 + + +2023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* by overrun IRQ process below. */ +2024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); +2025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +2026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC state */ +2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); +2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) +2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** SET_BIT(hadc->State, HAL_ADC_STATE_READY); +2032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +2035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Conversion complete callback */ +2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ConvCpltCallback(hadc); +2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_ConvCpltCallback(hadc); +2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +2041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else /* DMA and-or internal error occurred */ +2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) +2045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +2046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Call HAL ADC Error Callback function */ +2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +2048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ErrorCallback(hadc); +2049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else +2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_ErrorCallback(hadc); +2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +2052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** else +2054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { +2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Call DMA error callback */ +2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->DMA_Handle->XferErrorCallback(hdma); +2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } +2060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +2062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief DMA half transfer complete callback. +2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +2064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified DMA module. +2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval None +2066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) +2068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2031 .loc 1 2068 1 is_stmt 1 view -0 + 2032 .cfi_startproc + 2033 @ args = 0, pretend = 0, frame = 0 + 2034 @ frame_needed = 0, uses_anonymous_args = 0 + 2035 .loc 1 2068 1 is_stmt 0 view .LVU652 + 2036 0000 08B5 push {r3, lr} + 2037 .LCFI18: + 2038 .cfi_def_cfa_offset 8 + 2039 .cfi_offset 3, -8 + 2040 .cfi_offset 14, -4 +2069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + ARM GAS /tmp/ccMiLMrd.s page 82 + + + 2041 .loc 1 2069 3 is_stmt 1 view .LVU653 + 2042 .LVL100: +2070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Half conversion callback */ +2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +2072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ConvHalfCpltCallback(hadc); +2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else +2074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_ConvHalfCpltCallback(hadc); + 2043 .loc 1 2074 3 view .LVU654 + 2044 0002 806B ldr r0, [r0, #56] + 2045 .LVL101: + 2046 .loc 1 2074 3 is_stmt 0 view .LVU655 + 2047 0004 FFF7FEFF bl HAL_ADC_ConvHalfCpltCallback + 2048 .LVL102: +2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2049 .loc 1 2076 1 view .LVU656 + 2050 0008 08BD pop {r3, pc} + 2051 .cfi_endproc + 2052 .LFE165: + 2054 .section .text.HAL_ADC_LevelOutOfWindowCallback,"ax",%progbits + 2055 .align 1 + 2056 .weak HAL_ADC_LevelOutOfWindowCallback + 2057 .syntax unified + 2058 .thumb + 2059 .thumb_func + 2061 HAL_ADC_LevelOutOfWindowCallback: + 2062 .LVL103: + 2063 .LFB157: +1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ + 2064 .loc 1 1612 1 is_stmt 1 view -0 + 2065 .cfi_startproc + 2066 @ args = 0, pretend = 0, frame = 0 + 2067 @ frame_needed = 0, uses_anonymous_args = 0 + 2068 @ link register save eliminated. +1614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 2069 .loc 1 1614 3 view .LVU658 +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2070 .loc 1 1618 1 is_stmt 0 view .LVU659 + 2071 0000 7047 bx lr + 2072 .cfi_endproc + 2073 .LFE157: + 2075 .section .text.HAL_ADC_ErrorCallback,"ax",%progbits + 2076 .align 1 + 2077 .weak HAL_ADC_ErrorCallback + 2078 .syntax unified + 2079 .thumb + 2080 .thumb_func + 2082 HAL_ADC_ErrorCallback: + 2083 .LVL104: + 2084 .LFB158: +1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Prevent unused argument(s) compilation warning */ + 2085 .loc 1 1633 1 is_stmt 1 view -0 + 2086 .cfi_startproc + 2087 @ args = 0, pretend = 0, frame = 0 + 2088 @ frame_needed = 0, uses_anonymous_args = 0 + 2089 @ link register save eliminated. +1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* NOTE : This function Should not be modified, when the callback is needed, + ARM GAS /tmp/ccMiLMrd.s page 83 + + + 2090 .loc 1 1635 3 view .LVU661 +1639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2091 .loc 1 1639 1 is_stmt 0 view .LVU662 + 2092 0000 7047 bx lr + 2093 .cfi_endproc + 2094 .LFE158: + 2096 .section .text.HAL_ADC_IRQHandler,"ax",%progbits + 2097 .align 1 + 2098 .global HAL_ADC_IRQHandler + 2099 .syntax unified + 2100 .thumb + 2101 .thumb_func + 2103 HAL_ADC_IRQHandler: + 2104 .LVL105: + 2105 .LFB151: +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t tmp1 = 0, tmp2 = 0; + 2106 .loc 1 1210 1 is_stmt 1 view -0 + 2107 .cfi_startproc + 2108 @ args = 0, pretend = 0, frame = 0 + 2109 @ frame_needed = 0, uses_anonymous_args = 0 +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t tmp1 = 0, tmp2 = 0; + 2110 .loc 1 1210 1 is_stmt 0 view .LVU664 + 2111 0000 70B5 push {r4, r5, r6, lr} + 2112 .LCFI19: + 2113 .cfi_def_cfa_offset 16 + 2114 .cfi_offset 4, -16 + 2115 .cfi_offset 5, -12 + 2116 .cfi_offset 6, -8 + 2117 .cfi_offset 14, -4 + 2118 0002 0446 mov r4, r0 +1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2119 .loc 1 1211 3 is_stmt 1 view .LVU665 + 2120 .LVL106: +1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t tmp_cr1 = hadc->Instance->CR1; + 2121 .loc 1 1213 3 view .LVU666 +1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t tmp_cr1 = hadc->Instance->CR1; + 2122 .loc 1 1213 25 is_stmt 0 view .LVU667 + 2123 0004 0368 ldr r3, [r0] +1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** uint32_t tmp_cr1 = hadc->Instance->CR1; + 2124 .loc 1 1213 12 view .LVU668 + 2125 0006 1E68 ldr r6, [r3] + 2126 .LVL107: +1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2127 .loc 1 1214 3 is_stmt 1 view .LVU669 +1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2128 .loc 1 1214 12 is_stmt 0 view .LVU670 + 2129 0008 5D68 ldr r5, [r3, #4] + 2130 .LVL108: +1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); + 2131 .loc 1 1217 3 is_stmt 1 view .LVU671 +1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); + 2132 .loc 1 1218 3 view .LVU672 +1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2133 .loc 1 1219 3 view .LVU673 +1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** tmp2 = tmp_cr1 & ADC_IT_EOC; + 2134 .loc 1 1221 3 view .LVU674 +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + ARM GAS /tmp/ccMiLMrd.s page 84 + + + 2135 .loc 1 1222 3 view .LVU675 +1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2136 .loc 1 1225 3 view .LVU676 +1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2137 .loc 1 1225 11 is_stmt 0 view .LVU677 + 2138 000a C5F34012 ubfx r2, r5, #5, #1 +1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2139 .loc 1 1225 5 view .LVU678 + 2140 000e 12EA5602 ands r2, r2, r6, lsr #1 + 2141 0012 2CD0 beq .L159 +1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2142 .loc 1 1228 5 is_stmt 1 view .LVU679 +1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2143 .loc 1 1228 9 is_stmt 0 view .LVU680 + 2144 0014 026C ldr r2, [r0, #64] +1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2145 .loc 1 1228 8 view .LVU681 + 2146 0016 12F0100F tst r2, #16 + 2147 001a 03D1 bne .L160 +1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2148 .loc 1 1231 7 is_stmt 1 view .LVU682 + 2149 001c 026C ldr r2, [r0, #64] + 2150 001e 42F40072 orr r2, r2, #512 + 2151 0022 0264 str r2, [r0, #64] + 2152 .L160: +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) && + 2153 .loc 1 1240 5 view .LVU683 +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) && + 2154 .loc 1 1240 8 is_stmt 0 view .LVU684 + 2155 0024 9A68 ldr r2, [r3, #8] +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) && + 2156 .loc 1 1240 7 view .LVU685 + 2157 0026 12F0405F tst r2, #805306368 + 2158 002a 19D1 bne .L161 +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + 2159 .loc 1 1241 19 view .LVU686 + 2160 002c A269 ldr r2, [r4, #24] +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) && + 2161 .loc 1 1240 62 discriminator 1 view .LVU687 + 2162 002e BAB9 cbnz r2, .L161 +1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + 2163 .loc 1 1242 9 view .LVU688 + 2164 0030 DA6A ldr r2, [r3, #44] +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + 2165 .loc 1 1241 62 view .LVU689 + 2166 0032 12F4700F tst r2, #15728640 + 2167 0036 03D0 beq .L162 +1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2168 .loc 1 1243 9 view .LVU690 + 2169 0038 9A68 ldr r2, [r3, #8] +1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + 2170 .loc 1 1242 58 view .LVU691 + 2171 003a 12F4806F tst r2, #1024 + 2172 003e 0FD1 bne .L161 + 2173 .L162: +1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2174 .loc 1 1249 7 is_stmt 1 view .LVU692 + ARM GAS /tmp/ccMiLMrd.s page 85 + + + 2175 0040 5A68 ldr r2, [r3, #4] + 2176 0042 22F02002 bic r2, r2, #32 + 2177 0046 5A60 str r2, [r3, #4] +1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2178 .loc 1 1252 7 view .LVU693 + 2179 0048 236C ldr r3, [r4, #64] + 2180 004a 23F48073 bic r3, r3, #256 + 2181 004e 2364 str r3, [r4, #64] +1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2182 .loc 1 1254 7 view .LVU694 +1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2183 .loc 1 1254 11 is_stmt 0 view .LVU695 + 2184 0050 236C ldr r3, [r4, #64] +1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2185 .loc 1 1254 10 view .LVU696 + 2186 0052 13F4805F tst r3, #4096 + 2187 0056 03D1 bne .L161 +1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2188 .loc 1 1256 9 is_stmt 1 view .LVU697 + 2189 0058 236C ldr r3, [r4, #64] + 2190 005a 43F00103 orr r3, r3, #1 + 2191 005e 2364 str r3, [r4, #64] + 2192 .L161: +1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + 2193 .loc 1 1264 5 view .LVU698 + 2194 0060 2046 mov r0, r4 + 2195 .LVL109: +1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + 2196 .loc 1 1264 5 is_stmt 0 view .LVU699 + 2197 0062 FFF7FEFF bl HAL_ADC_ConvCpltCallback + 2198 .LVL110: +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2199 .loc 1 1268 5 is_stmt 1 view .LVU700 + 2200 0066 2368 ldr r3, [r4] + 2201 0068 6FF01202 mvn r2, #18 + 2202 006c 1A60 str r2, [r3] + 2203 .L159: +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** tmp2 = tmp_cr1 & ADC_IT_JEOC; + 2204 .loc 1 1271 3 view .LVU701 + 2205 .LVL111: +1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check End of conversion flag for injected channels */ + 2206 .loc 1 1272 3 view .LVU702 +1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2207 .loc 1 1274 3 view .LVU703 +1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2208 .loc 1 1274 11 is_stmt 0 view .LVU704 + 2209 006e C5F3C013 ubfx r3, r5, #7, #1 +1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2210 .loc 1 1274 5 view .LVU705 + 2211 0072 13EA9603 ands r3, r3, r6, lsr #2 + 2212 0076 35D0 beq .L163 +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2213 .loc 1 1277 5 is_stmt 1 view .LVU706 +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2214 .loc 1 1277 9 is_stmt 0 view .LVU707 + 2215 0078 236C ldr r3, [r4, #64] +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + ARM GAS /tmp/ccMiLMrd.s page 86 + + + 2216 .loc 1 1277 8 view .LVU708 + 2217 007a 13F0100F tst r3, #16 + 2218 007e 03D1 bne .L164 +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2219 .loc 1 1280 7 is_stmt 1 view .LVU709 + 2220 0080 236C ldr r3, [r4, #64] + 2221 0082 43F40053 orr r3, r3, #8192 + 2222 0086 2364 str r3, [r4, #64] + 2223 .L164: +1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + 2224 .loc 1 1287 5 view .LVU710 +1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + 2225 .loc 1 1287 8 is_stmt 0 view .LVU711 + 2226 0088 2368 ldr r3, [r4] + 2227 008a 9A68 ldr r2, [r3, #8] +1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + 2228 .loc 1 1287 7 view .LVU712 + 2229 008c 12F4401F tst r2, #3145728 + 2230 0090 21D1 bne .L165 +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) && + 2231 .loc 1 1288 9 view .LVU713 + 2232 0092 9A6B ldr r2, [r3, #56] +1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + 2233 .loc 1 1287 64 discriminator 1 view .LVU714 + 2234 0094 12F4401F tst r2, #3145728 + 2235 0098 03D0 beq .L166 +1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + 2236 .loc 1 1289 9 view .LVU715 + 2237 009a 9A68 ldr r2, [r3, #8] +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) && + 2238 .loc 1 1288 59 view .LVU716 + 2239 009c 12F4806F tst r2, #1024 + 2240 00a0 19D1 bne .L165 + 2241 .L166: +1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 2242 .loc 1 1290 9 view .LVU717 + 2243 00a2 5A68 ldr r2, [r3, #4] +1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + 2244 .loc 1 1289 60 view .LVU718 + 2245 00a4 12F4806F tst r2, #1024 + 2246 00a8 15D1 bne .L165 +1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE)))) + 2247 .loc 1 1291 9 view .LVU719 + 2248 00aa 9A68 ldr r2, [r3, #8] +1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 2249 .loc 1 1290 60 view .LVU720 + 2250 00ac 12F0405F tst r2, #805306368 + 2251 00b0 11D1 bne .L165 +1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2252 .loc 1 1292 19 view .LVU721 + 2253 00b2 A269 ldr r2, [r4, #24] +1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE)))) + 2254 .loc 1 1291 45 view .LVU722 + 2255 00b4 7AB9 cbnz r2, .L165 +1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2256 .loc 1 1295 7 is_stmt 1 view .LVU723 + 2257 00b6 5A68 ldr r2, [r3, #4] + ARM GAS /tmp/ccMiLMrd.s page 87 + + + 2258 00b8 22F08002 bic r2, r2, #128 + 2259 00bc 5A60 str r2, [r3, #4] +1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2260 .loc 1 1298 7 view .LVU724 + 2261 00be 236C ldr r3, [r4, #64] + 2262 00c0 23F48053 bic r3, r3, #4096 + 2263 00c4 2364 str r3, [r4, #64] +1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2264 .loc 1 1300 7 view .LVU725 +1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2265 .loc 1 1300 11 is_stmt 0 view .LVU726 + 2266 00c6 236C ldr r3, [r4, #64] +1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2267 .loc 1 1300 10 view .LVU727 + 2268 00c8 13F4807F tst r3, #256 + 2269 00cc 03D1 bne .L165 +1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2270 .loc 1 1302 9 is_stmt 1 view .LVU728 + 2271 00ce 236C ldr r3, [r4, #64] + 2272 00d0 43F00103 orr r3, r3, #1 + 2273 00d4 2364 str r3, [r4, #64] + 2274 .L165: +1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + 2275 .loc 1 1310 7 view .LVU729 + 2276 00d6 2046 mov r0, r4 + 2277 00d8 FFF7FEFF bl HAL_ADCEx_InjectedConvCpltCallback + 2278 .LVL112: +1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2279 .loc 1 1314 5 view .LVU730 + 2280 00dc 2368 ldr r3, [r4] + 2281 00de 6FF00C02 mvn r2, #12 + 2282 00e2 1A60 str r2, [r3] + 2283 .L163: +1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** tmp2 = tmp_cr1 & ADC_IT_AWD; + 2284 .loc 1 1317 3 view .LVU731 + 2285 .LVL113: +1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check Analog watchdog flag */ + 2286 .loc 1 1318 3 view .LVU732 +1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2287 .loc 1 1320 3 view .LVU733 +1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2288 .loc 1 1320 11 is_stmt 0 view .LVU734 + 2289 00e4 C5F38013 ubfx r3, r5, #6, #1 +1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2290 .loc 1 1320 5 view .LVU735 + 2291 00e8 1E42 tst r6, r3 + 2292 00ea 04D0 beq .L167 +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2293 .loc 1 1322 5 is_stmt 1 view .LVU736 +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2294 .loc 1 1322 8 is_stmt 0 view .LVU737 + 2295 00ec 2368 ldr r3, [r4] + 2296 00ee 1B68 ldr r3, [r3] +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2297 .loc 1 1322 7 view .LVU738 + 2298 00f0 13F0010F tst r3, #1 + 2299 00f4 05D1 bne .L170 + ARM GAS /tmp/ccMiLMrd.s page 88 + + + 2300 .L167: +1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** tmp2 = tmp_cr1 & ADC_IT_OVR; + 2301 .loc 1 1340 3 is_stmt 1 view .LVU739 + 2302 .LVL114: +1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Check Overrun flag */ + 2303 .loc 1 1341 3 view .LVU740 +1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2304 .loc 1 1343 3 view .LVU741 +1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2305 .loc 1 1343 11 is_stmt 0 view .LVU742 + 2306 00f6 C5F38065 ubfx r5, r5, #26, #1 + 2307 .LVL115: +1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2308 .loc 1 1343 5 view .LVU743 + 2309 00fa 15EA5615 ands r5, r5, r6, lsr #5 + 2310 00fe 0CD1 bne .L171 + 2311 .L158: +1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2312 .loc 1 1365 1 view .LVU744 + 2313 0100 70BD pop {r4, r5, r6, pc} + 2314 .LVL116: + 2315 .L170: +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2316 .loc 1 1325 7 is_stmt 1 view .LVU745 + 2317 0102 236C ldr r3, [r4, #64] + 2318 0104 43F48033 orr r3, r3, #65536 + 2319 0108 2364 str r3, [r4, #64] +1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + 2320 .loc 1 1331 7 view .LVU746 + 2321 010a 2046 mov r0, r4 + 2322 010c FFF7FEFF bl HAL_ADC_LevelOutOfWindowCallback + 2323 .LVL117: +1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2324 .loc 1 1336 7 view .LVU747 + 2325 0110 2368 ldr r3, [r4] + 2326 0112 6FF00102 mvn r2, #1 + 2327 0116 1A60 str r2, [r3] + 2328 0118 EDE7 b .L167 + 2329 .LVL118: + 2330 .L171: +1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2331 .loc 1 1350 5 view .LVU748 + 2332 011a 636C ldr r3, [r4, #68] + 2333 011c 43F00203 orr r3, r3, #2 + 2334 0120 6364 str r3, [r4, #68] +1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2335 .loc 1 1353 5 view .LVU749 + 2336 0122 2368 ldr r3, [r4] + 2337 0124 6FF02005 mvn r5, #32 + 2338 0128 1D60 str r5, [r3] +1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + 2339 .loc 1 1359 7 view .LVU750 + 2340 012a 2046 mov r0, r4 + 2341 012c FFF7FEFF bl HAL_ADC_ErrorCallback + 2342 .LVL119: +1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2343 .loc 1 1363 5 view .LVU751 + ARM GAS /tmp/ccMiLMrd.s page 89 + + + 2344 0130 2368 ldr r3, [r4] + 2345 0132 1D60 str r5, [r3] +1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2346 .loc 1 1365 1 is_stmt 0 view .LVU752 + 2347 0134 E4E7 b .L158 + 2348 .cfi_endproc + 2349 .LFE151: + 2351 .section .text.ADC_DMAError,"ax",%progbits + 2352 .align 1 + 2353 .syntax unified + 2354 .thumb + 2355 .thumb_func + 2357 ADC_DMAError: + 2358 .LVL120: + 2359 .LFB166: +2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** +2078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /** +2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @brief DMA error callback +2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * the configuration information for the specified DMA module. +2082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** * @retval None +2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** */ +2084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** static void ADC_DMAError(DMA_HandleTypeDef *hdma) +2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2360 .loc 1 2085 1 is_stmt 1 view -0 + 2361 .cfi_startproc + 2362 @ args = 0, pretend = 0, frame = 0 + 2363 @ frame_needed = 0, uses_anonymous_args = 0 + 2364 .loc 1 2085 1 is_stmt 0 view .LVU754 + 2365 0000 08B5 push {r3, lr} + 2366 .LCFI20: + 2367 .cfi_def_cfa_offset 8 + 2368 .cfi_offset 3, -8 + 2369 .cfi_offset 14, -4 +2086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + 2370 .loc 1 2086 3 is_stmt 1 view .LVU755 + 2371 .loc 1 2086 22 is_stmt 0 view .LVU756 + 2372 0002 806B ldr r0, [r0, #56] + 2373 .LVL121: +2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->State= HAL_ADC_STATE_ERROR_DMA; + 2374 .loc 1 2087 3 is_stmt 1 view .LVU757 + 2375 .loc 1 2087 14 is_stmt 0 view .LVU758 + 2376 0004 4023 movs r3, #64 + 2377 0006 0364 str r3, [r0, #64] +2088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Set ADC error code to DMA error */ +2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ErrorCode |= HAL_ADC_ERROR_DMA; + 2378 .loc 1 2089 3 is_stmt 1 view .LVU759 + 2379 .loc 1 2089 7 is_stmt 0 view .LVU760 + 2380 0008 436C ldr r3, [r0, #68] + 2381 .loc 1 2089 19 view .LVU761 + 2382 000a 43F00403 orr r3, r3, #4 + 2383 000e 4364 str r3, [r0, #68] +2090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Error callback */ +2091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +2092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** hadc->ErrorCallback(hadc); +2093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #else +2094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_ADC_ErrorCallback(hadc); + ARM GAS /tmp/ccMiLMrd.s page 90 + + + 2384 .loc 1 2094 3 is_stmt 1 view .LVU762 + 2385 0010 FFF7FEFF bl HAL_ADC_ErrorCallback + 2386 .LVL122: +2095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +2096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2387 .loc 1 2096 1 is_stmt 0 view .LVU763 + 2388 0014 08BD pop {r3, pc} + 2389 .cfi_endproc + 2390 .LFE166: + 2392 .section .text.ADC_DMAConvCplt,"ax",%progbits + 2393 .align 1 + 2394 .syntax unified + 2395 .thumb + 2396 .thumb_func + 2398 ADC_DMAConvCplt: + 2399 .LVL123: + 2400 .LFB164: +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Retrieve ADC handle corresponding to current DMA handle */ + 2401 .loc 1 1999 1 is_stmt 1 view -0 + 2402 .cfi_startproc + 2403 @ args = 0, pretend = 0, frame = 0 + 2404 @ frame_needed = 0, uses_anonymous_args = 0 +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Retrieve ADC handle corresponding to current DMA handle */ + 2405 .loc 1 1999 1 is_stmt 0 view .LVU765 + 2406 0000 08B5 push {r3, lr} + 2407 .LCFI21: + 2408 .cfi_def_cfa_offset 8 + 2409 .cfi_offset 3, -8 + 2410 .cfi_offset 14, -4 + 2411 0002 0346 mov r3, r0 +2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2412 .loc 1 2001 3 is_stmt 1 view .LVU766 +2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2413 .loc 1 2001 22 is_stmt 0 view .LVU767 + 2414 0004 806B ldr r0, [r0, #56] + 2415 .LVL124: +2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2416 .loc 1 2004 3 is_stmt 1 view .LVU768 +2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2417 .loc 1 2004 7 is_stmt 0 view .LVU769 + 2418 0006 026C ldr r2, [r0, #64] +2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2419 .loc 1 2004 6 view .LVU770 + 2420 0008 12F0500F tst r2, #80 + 2421 000c 25D1 bne .L175 +2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2422 .loc 1 2007 5 is_stmt 1 view .LVU771 + 2423 000e 036C ldr r3, [r0, #64] + 2424 .LVL125: +2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2425 .loc 1 2007 5 is_stmt 0 view .LVU772 + 2426 0010 43F40073 orr r3, r3, #512 + 2427 0014 0364 str r3, [r0, #64] +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) && + 2428 .loc 1 2015 5 is_stmt 1 view .LVU773 +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) && + 2429 .loc 1 2015 8 is_stmt 0 view .LVU774 + ARM GAS /tmp/ccMiLMrd.s page 91 + + + 2430 0016 0368 ldr r3, [r0] + 2431 0018 9A68 ldr r2, [r3, #8] +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) && + 2432 .loc 1 2015 7 view .LVU775 + 2433 001a 12F0405F tst r2, #805306368 + 2434 001e 19D1 bne .L176 +2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + 2435 .loc 1 2016 19 view .LVU776 + 2436 0020 8269 ldr r2, [r0, #24] +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (hadc->Init.ContinuousConvMode == DISABLE) && + 2437 .loc 1 2015 62 discriminator 1 view .LVU777 + 2438 0022 BAB9 cbnz r2, .L176 +2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + 2439 .loc 1 2017 9 view .LVU778 + 2440 0024 DA6A ldr r2, [r3, #44] +2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + 2441 .loc 1 2016 62 view .LVU779 + 2442 0026 12F4700F tst r2, #15728640 + 2443 002a 03D0 beq .L177 +2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2444 .loc 1 2018 9 view .LVU780 + 2445 002c 9A68 ldr r2, [r3, #8] +2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + 2446 .loc 1 2017 58 view .LVU781 + 2447 002e 12F4806F tst r2, #1024 + 2448 0032 0FD1 bne .L176 + 2449 .L177: +2024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2450 .loc 1 2024 7 is_stmt 1 view .LVU782 + 2451 0034 5A68 ldr r2, [r3, #4] + 2452 0036 22F02002 bic r2, r2, #32 + 2453 003a 5A60 str r2, [r3, #4] +2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2454 .loc 1 2027 7 view .LVU783 + 2455 003c 036C ldr r3, [r0, #64] + 2456 003e 23F48073 bic r3, r3, #256 + 2457 0042 0364 str r3, [r0, #64] +2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2458 .loc 1 2029 7 view .LVU784 +2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2459 .loc 1 2029 11 is_stmt 0 view .LVU785 + 2460 0044 036C ldr r3, [r0, #64] +2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2461 .loc 1 2029 10 view .LVU786 + 2462 0046 13F4805F tst r3, #4096 + 2463 004a 03D1 bne .L176 +2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2464 .loc 1 2031 9 is_stmt 1 view .LVU787 + 2465 004c 036C ldr r3, [r0, #64] + 2466 004e 43F00103 orr r3, r3, #1 + 2467 0052 0364 str r3, [r0, #64] + 2468 .L176: +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + 2469 .loc 1 2039 5 view .LVU788 + 2470 0054 FFF7FEFF bl HAL_ADC_ConvCpltCallback + 2471 .LVL126: + 2472 .L174: + ARM GAS /tmp/ccMiLMrd.s page 92 + + +2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2473 .loc 1 2059 1 is_stmt 0 view .LVU789 + 2474 0058 08BD pop {r3, pc} + 2475 .LVL127: + 2476 .L175: +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2477 .loc 1 2044 5 is_stmt 1 view .LVU790 +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2478 .loc 1 2044 14 is_stmt 0 view .LVU791 + 2479 005a 026C ldr r2, [r0, #64] +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2480 .loc 1 2044 8 view .LVU792 + 2481 005c 12F0100F tst r2, #16 + 2482 0060 04D1 bne .L181 +2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2483 .loc 1 2056 7 is_stmt 1 view .LVU793 +2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2484 .loc 1 2056 11 is_stmt 0 view .LVU794 + 2485 0062 826B ldr r2, [r0, #56] +2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2486 .loc 1 2056 23 view .LVU795 + 2487 0064 D26C ldr r2, [r2, #76] +2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2488 .loc 1 2056 7 view .LVU796 + 2489 0066 1846 mov r0, r3 + 2490 .LVL128: +2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2491 .loc 1 2056 7 view .LVU797 + 2492 0068 9047 blx r2 + 2493 .LVL129: +2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2494 .loc 1 2059 1 view .LVU798 + 2495 006a F5E7 b .L174 + 2496 .LVL130: + 2497 .L181: +2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + 2498 .loc 1 2050 7 is_stmt 1 view .LVU799 + 2499 006c FFF7FEFF bl HAL_ADC_ErrorCallback + 2500 .LVL131: +2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + 2501 .loc 1 2050 7 is_stmt 0 view .LVU800 + 2502 0070 F2E7 b .L174 + 2503 .cfi_endproc + 2504 .LFE164: + 2506 .section .text.HAL_ADC_ConfigChannel,"ax",%progbits + 2507 .align 1 + 2508 .global HAL_ADC_ConfigChannel + 2509 .syntax unified + 2510 .thumb + 2511 .thumb_func + 2513 HAL_ADC_ConfigChannel: + 2514 .LVL132: + 2515 .LFB159: +1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __IO uint32_t counter = 0; + 2516 .loc 1 1671 1 is_stmt 1 view -0 + 2517 .cfi_startproc + 2518 @ args = 0, pretend = 0, frame = 8 + ARM GAS /tmp/ccMiLMrd.s page 93 + + + 2519 @ frame_needed = 0, uses_anonymous_args = 0 + 2520 @ link register save eliminated. +1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** __IO uint32_t counter = 0; + 2521 .loc 1 1671 1 is_stmt 0 view .LVU802 + 2522 0000 30B4 push {r4, r5} + 2523 .LCFI22: + 2524 .cfi_def_cfa_offset 8 + 2525 .cfi_offset 4, -8 + 2526 .cfi_offset 5, -4 + 2527 0002 82B0 sub sp, sp, #8 + 2528 .LCFI23: + 2529 .cfi_def_cfa_offset 16 +1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2530 .loc 1 1672 3 is_stmt 1 view .LVU803 +1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2531 .loc 1 1672 17 is_stmt 0 view .LVU804 + 2532 0004 0022 movs r2, #0 + 2533 0006 0192 str r2, [sp, #4] +1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); + 2534 .loc 1 1675 3 is_stmt 1 view .LVU805 +1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); + 2535 .loc 1 1676 3 view .LVU806 +1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2536 .loc 1 1677 3 view .LVU807 +1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2537 .loc 1 1680 3 view .LVU808 +1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2538 .loc 1 1680 3 view .LVU809 + 2539 0008 90F83C20 ldrb r2, [r0, #60] @ zero_extendqisi2 + 2540 000c 012A cmp r2, #1 + 2541 000e 00F0DC80 beq .L195 + 2542 0012 0346 mov r3, r0 +1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2543 .loc 1 1680 3 discriminator 2 view .LVU810 + 2544 0014 0122 movs r2, #1 + 2545 0016 80F83C20 strb r2, [r0, #60] +1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2546 .loc 1 1680 3 discriminator 2 view .LVU811 +1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2547 .loc 1 1683 3 view .LVU812 +1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2548 .loc 1 1683 15 is_stmt 0 view .LVU813 + 2549 001a 0A68 ldr r2, [r1] +1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2550 .loc 1 1683 6 view .LVU814 + 2551 001c B2F1004F cmp r2, #-2147483648 + 2552 0020 18BF it ne + 2553 0022 092A cmpne r2, #9 + 2554 0024 22D9 bls .L184 +1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2555 .loc 1 1686 5 is_stmt 1 view .LVU815 +1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2556 .loc 1 1686 9 is_stmt 0 view .LVU816 + 2557 0026 0468 ldr r4, [r0] +1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2558 .loc 1 1686 19 view .LVU817 + 2559 0028 E068 ldr r0, [r4, #12] + ARM GAS /tmp/ccMiLMrd.s page 94 + + + 2560 .LVL133: +1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2561 .loc 1 1686 31 view .LVU818 + 2562 002a 92B2 uxth r2, r2 + 2563 002c 02EB4202 add r2, r2, r2, lsl #1 + 2564 0030 1E3A subs r2, r2, #30 + 2565 0032 4FF0070C mov ip, #7 + 2566 0036 0CFA02F2 lsl r2, ip, r2 +1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2567 .loc 1 1686 27 view .LVU819 + 2568 003a 20EA0202 bic r2, r0, r2 + 2569 003e E260 str r2, [r4, #12] +1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2570 .loc 1 1688 5 is_stmt 1 view .LVU820 +1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2571 .loc 1 1688 16 is_stmt 0 view .LVU821 + 2572 0040 0A68 ldr r2, [r1] +1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2573 .loc 1 1688 8 view .LVU822 + 2574 0042 6348 ldr r0, .L201 + 2575 0044 8242 cmp r2, r0 + 2576 0046 0AD0 beq .L197 +1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2577 .loc 1 1696 7 is_stmt 1 view .LVU823 +1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2578 .loc 1 1696 11 is_stmt 0 view .LVU824 + 2579 0048 1D68 ldr r5, [r3] +1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2580 .loc 1 1696 21 view .LVU825 + 2581 004a E868 ldr r0, [r5, #12] +1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2582 .loc 1 1696 32 view .LVU826 + 2583 004c 8C68 ldr r4, [r1, #8] + 2584 004e 92B2 uxth r2, r2 + 2585 0050 02EB4202 add r2, r2, r2, lsl #1 + 2586 0054 1E3A subs r2, r2, #30 + 2587 0056 9440 lsls r4, r4, r2 +1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2588 .loc 1 1696 29 view .LVU827 + 2589 0058 2043 orrs r0, r0, r4 + 2590 005a E860 str r0, [r5, #12] + 2591 005c 1CE0 b .L186 + 2592 .L197: +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2593 .loc 1 1691 7 is_stmt 1 view .LVU828 +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2594 .loc 1 1691 11 is_stmt 0 view .LVU829 + 2595 005e 1868 ldr r0, [r3] +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2596 .loc 1 1691 21 view .LVU830 + 2597 0060 C268 ldr r2, [r0, #12] +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2598 .loc 1 1691 32 view .LVU831 + 2599 0062 8C68 ldr r4, [r1, #8] +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2600 .loc 1 1691 29 view .LVU832 + 2601 0064 42EA0462 orr r2, r2, r4, lsl #24 + ARM GAS /tmp/ccMiLMrd.s page 95 + + + 2602 0068 C260 str r2, [r0, #12] + 2603 006a 15E0 b .L186 + 2604 .LVL134: + 2605 .L184: +1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2606 .loc 1 1702 5 is_stmt 1 view .LVU833 +1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2607 .loc 1 1702 9 is_stmt 0 view .LVU834 + 2608 006c 0468 ldr r4, [r0] +1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2609 .loc 1 1702 19 view .LVU835 + 2610 006e 2069 ldr r0, [r4, #16] + 2611 .LVL135: +1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2612 .loc 1 1702 31 view .LVU836 + 2613 0070 92B2 uxth r2, r2 + 2614 0072 02EB4202 add r2, r2, r2, lsl #1 + 2615 0076 4FF0070C mov ip, #7 + 2616 007a 0CFA02F2 lsl r2, ip, r2 +1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2617 .loc 1 1702 27 view .LVU837 + 2618 007e 20EA0202 bic r2, r0, r2 + 2619 0082 2261 str r2, [r4, #16] +1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2620 .loc 1 1705 5 is_stmt 1 view .LVU838 +1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2621 .loc 1 1705 9 is_stmt 0 view .LVU839 + 2622 0084 1C68 ldr r4, [r3] +1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2623 .loc 1 1705 19 view .LVU840 + 2624 0086 2069 ldr r0, [r4, #16] +1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2625 .loc 1 1705 30 view .LVU841 + 2626 0088 0A88 ldrh r2, [r1] + 2627 008a 02EB4202 add r2, r2, r2, lsl #1 + 2628 008e 8D68 ldr r5, [r1, #8] + 2629 0090 05FA02F2 lsl r2, r5, r2 +1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2630 .loc 1 1705 27 view .LVU842 + 2631 0094 0243 orrs r2, r2, r0 + 2632 0096 2261 str r2, [r4, #16] + 2633 .L186: +1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2634 .loc 1 1709 3 is_stmt 1 view .LVU843 +1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2635 .loc 1 1709 14 is_stmt 0 view .LVU844 + 2636 0098 4A68 ldr r2, [r1, #4] +1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2637 .loc 1 1709 6 view .LVU845 + 2638 009a 062A cmp r2, #6 + 2639 009c 29D8 bhi .L187 +1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2640 .loc 1 1712 5 is_stmt 1 view .LVU846 +1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2641 .loc 1 1712 9 is_stmt 0 view .LVU847 + 2642 009e 1C68 ldr r4, [r3] +1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + ARM GAS /tmp/ccMiLMrd.s page 96 + + + 2643 .loc 1 1712 19 view .LVU848 + 2644 00a0 606B ldr r0, [r4, #52] +1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2645 .loc 1 1712 30 view .LVU849 + 2646 00a2 02EB8202 add r2, r2, r2, lsl #2 + 2647 00a6 053A subs r2, r2, #5 + 2648 00a8 4FF01F0C mov ip, #31 + 2649 00ac 0CFA02F2 lsl r2, ip, r2 +1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2650 .loc 1 1712 26 view .LVU850 + 2651 00b0 20EA0202 bic r2, r0, r2 + 2652 00b4 6263 str r2, [r4, #52] +1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2653 .loc 1 1715 5 is_stmt 1 view .LVU851 +1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2654 .loc 1 1715 9 is_stmt 0 view .LVU852 + 2655 00b6 1C68 ldr r4, [r3] +1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2656 .loc 1 1715 19 view .LVU853 + 2657 00b8 606B ldr r0, [r4, #52] +1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2658 .loc 1 1715 29 view .LVU854 + 2659 00ba 4A68 ldr r2, [r1, #4] + 2660 00bc 02EB8202 add r2, r2, r2, lsl #2 + 2661 00c0 053A subs r2, r2, #5 + 2662 00c2 B1F800C0 ldrh ip, [r1] + 2663 00c6 0CFA02F2 lsl r2, ip, r2 +1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2664 .loc 1 1715 26 view .LVU855 + 2665 00ca 0243 orrs r2, r2, r0 + 2666 00cc 6263 str r2, [r4, #52] + 2667 .L188: +1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2668 .loc 1 1737 3 is_stmt 1 view .LVU856 +1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2669 .loc 1 1737 12 is_stmt 0 view .LVU857 + 2670 00ce 1868 ldr r0, [r3] +1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2671 .loc 1 1737 6 view .LVU858 + 2672 00d0 404A ldr r2, .L201+4 + 2673 00d2 9042 cmp r0, r2 + 2674 00d4 3DD0 beq .L198 + 2675 .L190: +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2676 .loc 1 1744 3 is_stmt 1 view .LVU859 +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2677 .loc 1 1744 12 is_stmt 0 view .LVU860 + 2678 00d6 1868 ldr r0, [r3] +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2679 .loc 1 1744 6 view .LVU861 + 2680 00d8 3E4A ldr r2, .L201+4 + 2681 00da 9042 cmp r0, r2 + 2682 00dc 43D0 beq .L199 + 2683 .L191: +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2684 .loc 1 1754 3 is_stmt 1 view .LVU862 +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + ARM GAS /tmp/ccMiLMrd.s page 97 + + + 2685 .loc 1 1754 12 is_stmt 0 view .LVU863 + 2686 00de 1868 ldr r0, [r3] +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2687 .loc 1 1754 6 view .LVU864 + 2688 00e0 3C4A ldr r2, .L201+4 + 2689 00e2 9042 cmp r0, r2 + 2690 00e4 4CD0 beq .L200 + 2691 .LVL136: + 2692 .L192: +1775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2693 .loc 1 1775 3 is_stmt 1 view .LVU865 +1775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2694 .loc 1 1775 3 view .LVU866 + 2695 00e6 0020 movs r0, #0 + 2696 00e8 83F83C00 strb r0, [r3, #60] +1775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2697 .loc 1 1775 3 view .LVU867 +1778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2698 .loc 1 1778 3 view .LVU868 + 2699 .LVL137: + 2700 .L183: +1779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2701 .loc 1 1779 1 is_stmt 0 view .LVU869 + 2702 00ec 02B0 add sp, sp, #8 + 2703 .LCFI24: + 2704 .cfi_remember_state + 2705 .cfi_def_cfa_offset 8 + 2706 @ sp needed + 2707 00ee 30BC pop {r4, r5} + 2708 .LCFI25: + 2709 .cfi_restore 5 + 2710 .cfi_restore 4 + 2711 .cfi_def_cfa_offset 0 + 2712 00f0 7047 bx lr + 2713 .LVL138: + 2714 .L187: + 2715 .LCFI26: + 2716 .cfi_restore_state +1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2717 .loc 1 1718 8 is_stmt 1 view .LVU870 +1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2718 .loc 1 1718 11 is_stmt 0 view .LVU871 + 2719 00f2 0C2A cmp r2, #12 + 2720 00f4 16D8 bhi .L189 +1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2721 .loc 1 1721 5 is_stmt 1 view .LVU872 +1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2722 .loc 1 1721 9 is_stmt 0 view .LVU873 + 2723 00f6 1D68 ldr r5, [r3] +1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2724 .loc 1 1721 19 view .LVU874 + 2725 00f8 286B ldr r0, [r5, #48] +1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2726 .loc 1 1721 30 view .LVU875 + 2727 00fa 02EB8202 add r2, r2, r2, lsl #2 + 2728 00fe 233A subs r2, r2, #35 + 2729 0100 1F24 movs r4, #31 + ARM GAS /tmp/ccMiLMrd.s page 98 + + + 2730 0102 04FA02F2 lsl r2, r4, r2 +1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2731 .loc 1 1721 26 view .LVU876 + 2732 0106 20EA0202 bic r2, r0, r2 + 2733 010a 2A63 str r2, [r5, #48] +1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2734 .loc 1 1724 5 is_stmt 1 view .LVU877 +1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2735 .loc 1 1724 9 is_stmt 0 view .LVU878 + 2736 010c 1D68 ldr r5, [r3] +1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2737 .loc 1 1724 19 view .LVU879 + 2738 010e 286B ldr r0, [r5, #48] +1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2739 .loc 1 1724 29 view .LVU880 + 2740 0110 4A68 ldr r2, [r1, #4] + 2741 0112 02EB8202 add r2, r2, r2, lsl #2 + 2742 0116 233A subs r2, r2, #35 + 2743 0118 0C88 ldrh r4, [r1] + 2744 011a 04FA02F2 lsl r2, r4, r2 +1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2745 .loc 1 1724 26 view .LVU881 + 2746 011e 0243 orrs r2, r2, r0 + 2747 0120 2A63 str r2, [r5, #48] + 2748 0122 D4E7 b .L188 + 2749 .L189: +1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2750 .loc 1 1730 5 is_stmt 1 view .LVU882 +1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2751 .loc 1 1730 9 is_stmt 0 view .LVU883 + 2752 0124 1D68 ldr r5, [r3] +1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2753 .loc 1 1730 19 view .LVU884 + 2754 0126 E86A ldr r0, [r5, #44] +1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2755 .loc 1 1730 30 view .LVU885 + 2756 0128 02EB8202 add r2, r2, r2, lsl #2 + 2757 012c 413A subs r2, r2, #65 + 2758 012e 1F24 movs r4, #31 + 2759 0130 04FA02F2 lsl r2, r4, r2 +1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2760 .loc 1 1730 26 view .LVU886 + 2761 0134 20EA0202 bic r2, r0, r2 + 2762 0138 EA62 str r2, [r5, #44] +1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2763 .loc 1 1733 5 is_stmt 1 view .LVU887 +1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2764 .loc 1 1733 9 is_stmt 0 view .LVU888 + 2765 013a 1D68 ldr r5, [r3] +1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2766 .loc 1 1733 19 view .LVU889 + 2767 013c E86A ldr r0, [r5, #44] +1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2768 .loc 1 1733 29 view .LVU890 + 2769 013e 4A68 ldr r2, [r1, #4] + 2770 0140 02EB8202 add r2, r2, r2, lsl #2 + 2771 0144 413A subs r2, r2, #65 + ARM GAS /tmp/ccMiLMrd.s page 99 + + + 2772 0146 0C88 ldrh r4, [r1] + 2773 0148 04FA02F2 lsl r2, r4, r2 +1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2774 .loc 1 1733 26 view .LVU891 + 2775 014c 0243 orrs r2, r2, r0 + 2776 014e EA62 str r2, [r5, #44] + 2777 0150 BDE7 b .L188 + 2778 .L198: +1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2779 .loc 1 1737 43 discriminator 1 view .LVU892 + 2780 0152 0A68 ldr r2, [r1] +1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2781 .loc 1 1737 32 discriminator 1 view .LVU893 + 2782 0154 B2F1004F cmp r2, #-2147483648 + 2783 0158 BDD1 bne .L190 +1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2784 .loc 1 1740 5 is_stmt 1 view .LVU894 +1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2785 .loc 1 1740 8 is_stmt 0 view .LVU895 + 2786 015a 1F48 ldr r0, .L201+8 + 2787 015c 4268 ldr r2, [r0, #4] +1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2788 .loc 1 1740 14 view .LVU896 + 2789 015e 22F44002 bic r2, r2, #12582912 + 2790 0162 4260 str r2, [r0, #4] + 2791 0164 B7E7 b .L190 + 2792 .L199: +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2793 .loc 1 1744 43 discriminator 1 view .LVU897 + 2794 0166 0A68 ldr r2, [r1] +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2795 .loc 1 1744 32 discriminator 1 view .LVU898 + 2796 0168 122A cmp r2, #18 + 2797 016a B8D1 bne .L191 +1747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2798 .loc 1 1747 5 is_stmt 1 view .LVU899 +1747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2799 .loc 1 1747 8 is_stmt 0 view .LVU900 + 2800 016c 1A4A ldr r2, .L201+8 + 2801 016e 5068 ldr r0, [r2, #4] +1747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2802 .loc 1 1747 14 view .LVU901 + 2803 0170 20F40000 bic r0, r0, #8388608 + 2804 0174 5060 str r0, [r2, #4] +1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2805 .loc 1 1750 5 is_stmt 1 view .LVU902 +1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2806 .loc 1 1750 8 is_stmt 0 view .LVU903 + 2807 0176 5068 ldr r0, [r2, #4] +1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2808 .loc 1 1750 14 view .LVU904 + 2809 0178 40F48000 orr r0, r0, #4194304 + 2810 017c 5060 str r0, [r2, #4] + 2811 017e AEE7 b .L191 + 2812 .L200: +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2813 .loc 1 1754 44 discriminator 1 view .LVU905 + ARM GAS /tmp/ccMiLMrd.s page 100 + + + 2814 0180 0A68 ldr r2, [r1] +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2815 .loc 1 1754 32 discriminator 1 view .LVU906 + 2816 0182 1348 ldr r0, .L201 + 2817 0184 112A cmp r2, #17 + 2818 0186 18BF it ne + 2819 0188 8242 cmpne r2, r0 + 2820 018a ACD1 bne .L192 +1757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2821 .loc 1 1757 5 is_stmt 1 view .LVU907 +1757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2822 .loc 1 1757 8 is_stmt 0 view .LVU908 + 2823 018c 124A ldr r2, .L201+8 + 2824 018e 5068 ldr r0, [r2, #4] +1757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2825 .loc 1 1757 14 view .LVU909 + 2826 0190 20F48000 bic r0, r0, #4194304 + 2827 0194 5060 str r0, [r2, #4] +1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2828 .loc 1 1760 5 is_stmt 1 view .LVU910 +1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2829 .loc 1 1760 8 is_stmt 0 view .LVU911 + 2830 0196 5068 ldr r0, [r2, #4] +1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2831 .loc 1 1760 14 view .LVU912 + 2832 0198 40F40000 orr r0, r0, #8388608 + 2833 019c 5060 str r0, [r2, #4] +1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2834 .loc 1 1762 5 is_stmt 1 view .LVU913 +1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2835 .loc 1 1762 15 is_stmt 0 view .LVU914 + 2836 019e 0968 ldr r1, [r1] + 2837 .LVL139: +1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2838 .loc 1 1762 7 view .LVU915 + 2839 01a0 0B4A ldr r2, .L201 + 2840 01a2 9142 cmp r1, r2 + 2841 01a4 9FD1 bne .L192 +1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) + 2842 .loc 1 1766 7 is_stmt 1 view .LVU916 +1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) + 2843 .loc 1 1766 61 is_stmt 0 view .LVU917 + 2844 01a6 0D4A ldr r2, .L201+12 + 2845 01a8 1268 ldr r2, [r2] + 2846 01aa 0D49 ldr r1, .L201+16 + 2847 01ac A1FB0212 umull r1, r2, r1, r2 + 2848 01b0 920C lsrs r2, r2, #18 +1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) + 2849 .loc 1 1766 42 view .LVU918 + 2850 01b2 02EB8202 add r2, r2, r2, lsl #2 + 2851 01b6 5200 lsls r2, r2, #1 +1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** while(counter != 0) + 2852 .loc 1 1766 15 view .LVU919 + 2853 01b8 0192 str r2, [sp, #4] +1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2854 .loc 1 1767 7 is_stmt 1 view .LVU920 +1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + ARM GAS /tmp/ccMiLMrd.s page 101 + + + 2855 .loc 1 1767 12 is_stmt 0 view .LVU921 + 2856 01ba 02E0 b .L193 + 2857 .L194: +1769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2858 .loc 1 1769 9 is_stmt 1 view .LVU922 +1769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2859 .loc 1 1769 16 is_stmt 0 view .LVU923 + 2860 01bc 019A ldr r2, [sp, #4] + 2861 01be 013A subs r2, r2, #1 + 2862 01c0 0192 str r2, [sp, #4] + 2863 .L193: +1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2864 .loc 1 1767 21 is_stmt 1 view .LVU924 + 2865 01c2 019A ldr r2, [sp, #4] + 2866 01c4 002A cmp r2, #0 + 2867 01c6 F9D1 bne .L194 + 2868 01c8 8DE7 b .L192 + 2869 .LVL140: + 2870 .L195: +1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2871 .loc 1 1680 3 is_stmt 0 discriminator 1 view .LVU925 + 2872 01ca 0220 movs r0, #2 + 2873 .LVL141: +1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2874 .loc 1 1680 3 discriminator 1 view .LVU926 + 2875 01cc 8EE7 b .L183 + 2876 .L202: + 2877 01ce 00BF .align 2 + 2878 .L201: + 2879 01d0 12000010 .word 268435474 + 2880 01d4 00200140 .word 1073815552 + 2881 01d8 00230140 .word 1073816320 + 2882 01dc 00000000 .word SystemCoreClock + 2883 01e0 83DE1B43 .word 1125899907 + 2884 .cfi_endproc + 2885 .LFE159: + 2887 .section .text.HAL_ADC_AnalogWDGConfig,"ax",%progbits + 2888 .align 1 + 2889 .global HAL_ADC_AnalogWDGConfig + 2890 .syntax unified + 2891 .thumb + 2892 .thumb_func + 2894 HAL_ADC_AnalogWDGConfig: + 2895 .LVL142: + 2896 .LFB160: +1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #ifdef USE_FULL_ASSERT + 2897 .loc 1 1798 1 is_stmt 1 view -0 + 2898 .cfi_startproc + 2899 @ args = 0, pretend = 0, frame = 0 + 2900 @ frame_needed = 0, uses_anonymous_args = 0 + 2901 @ link register save eliminated. +1804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); + 2902 .loc 1 1804 3 view .LVU928 +1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); + 2903 .loc 1 1805 3 view .LVU929 +1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2904 .loc 1 1806 3 view .LVU930 + ARM GAS /tmp/ccMiLMrd.s page 102 + + +1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2905 .loc 1 1815 3 view .LVU931 +1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2906 .loc 1 1815 3 view .LVU932 + 2907 0000 90F83C20 ldrb r2, [r0, #60] @ zero_extendqisi2 + 2908 0004 012A cmp r2, #1 + 2909 0006 32D0 beq .L207 +1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** #ifdef USE_FULL_ASSERT + 2910 .loc 1 1798 1 is_stmt 0 view .LVU933 + 2911 0008 10B4 push {r4} + 2912 .LCFI27: + 2913 .cfi_def_cfa_offset 4 + 2914 .cfi_offset 4, -4 + 2915 000a 0346 mov r3, r0 +1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2916 .loc 1 1815 3 is_stmt 1 discriminator 2 view .LVU934 + 2917 000c 0122 movs r2, #1 + 2918 000e 80F83C20 strb r2, [r0, #60] +1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2919 .loc 1 1815 3 discriminator 2 view .LVU935 +1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2920 .loc 1 1817 3 view .LVU936 +1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2921 .loc 1 1817 21 is_stmt 0 view .LVU937 + 2922 0012 0A7C ldrb r2, [r1, #16] @ zero_extendqisi2 +1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** { + 2923 .loc 1 1817 5 view .LVU938 + 2924 0014 012A cmp r2, #1 + 2925 0016 24D0 beq .L212 +1825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2926 .loc 1 1825 5 is_stmt 1 view .LVU939 + 2927 0018 0068 ldr r0, [r0] + 2928 .LVL143: +1825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2929 .loc 1 1825 5 is_stmt 0 view .LVU940 + 2930 001a 4268 ldr r2, [r0, #4] + 2931 001c 22F04002 bic r2, r2, #64 + 2932 0020 4260 str r2, [r0, #4] + 2933 .L206: +1829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2934 .loc 1 1829 3 is_stmt 1 view .LVU941 +1829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2935 .loc 1 1829 7 is_stmt 0 view .LVU942 + 2936 0022 1868 ldr r0, [r3] +1829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2937 .loc 1 1829 17 view .LVU943 + 2938 0024 4468 ldr r4, [r0, #4] +1829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2939 .loc 1 1829 23 view .LVU944 + 2940 0026 134A ldr r2, .L213 + 2941 0028 2240 ands r2, r2, r4 + 2942 002a 4260 str r2, [r0, #4] +1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2943 .loc 1 1832 3 is_stmt 1 view .LVU945 +1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2944 .loc 1 1832 7 is_stmt 0 view .LVU946 + 2945 002c 1868 ldr r0, [r3] + ARM GAS /tmp/ccMiLMrd.s page 103 + + +1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2946 .loc 1 1832 17 view .LVU947 + 2947 002e 4268 ldr r2, [r0, #4] +1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2948 .loc 1 1832 41 view .LVU948 + 2949 0030 0C68 ldr r4, [r1] +1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2950 .loc 1 1832 23 view .LVU949 + 2951 0032 2243 orrs r2, r2, r4 + 2952 0034 4260 str r2, [r0, #4] +1835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2953 .loc 1 1835 3 is_stmt 1 view .LVU950 +1835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2954 .loc 1 1835 7 is_stmt 0 view .LVU951 + 2955 0036 1A68 ldr r2, [r3] +1835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2956 .loc 1 1835 40 view .LVU952 + 2957 0038 4868 ldr r0, [r1, #4] +1835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2958 .loc 1 1835 23 view .LVU953 + 2959 003a 5062 str r0, [r2, #36] +1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2960 .loc 1 1838 3 is_stmt 1 view .LVU954 +1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2961 .loc 1 1838 7 is_stmt 0 view .LVU955 + 2962 003c 1A68 ldr r2, [r3] +1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2963 .loc 1 1838 40 view .LVU956 + 2964 003e 8868 ldr r0, [r1, #8] +1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2965 .loc 1 1838 23 view .LVU957 + 2966 0040 9062 str r0, [r2, #40] +1841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2967 .loc 1 1841 3 is_stmt 1 view .LVU958 +1841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2968 .loc 1 1841 7 is_stmt 0 view .LVU959 + 2969 0042 1868 ldr r0, [r3] +1841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2970 .loc 1 1841 17 view .LVU960 + 2971 0044 4268 ldr r2, [r0, #4] +1841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2972 .loc 1 1841 23 view .LVU961 + 2973 0046 22F01F02 bic r2, r2, #31 + 2974 004a 4260 str r2, [r0, #4] +1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2975 .loc 1 1844 3 is_stmt 1 view .LVU962 +1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2976 .loc 1 1844 7 is_stmt 0 view .LVU963 + 2977 004c 1868 ldr r0, [r3] +1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2978 .loc 1 1844 17 view .LVU964 + 2979 004e 4468 ldr r4, [r0, #4] +1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2980 .loc 1 1844 23 view .LVU965 + 2981 0050 8A89 ldrh r2, [r1, #12] + 2982 0052 2243 orrs r2, r2, r4 + 2983 0054 4260 str r2, [r0, #4] + ARM GAS /tmp/ccMiLMrd.s page 104 + + +1847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2984 .loc 1 1847 3 is_stmt 1 view .LVU966 +1847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2985 .loc 1 1847 3 view .LVU967 + 2986 0056 0020 movs r0, #0 + 2987 0058 83F83C00 strb r0, [r3, #60] +1847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2988 .loc 1 1847 3 view .LVU968 +1850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 2989 .loc 1 1850 3 view .LVU969 +1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 2990 .loc 1 1851 1 is_stmt 0 view .LVU970 + 2991 005c 5DF8044B ldr r4, [sp], #4 + 2992 .LCFI28: + 2993 .cfi_remember_state + 2994 .cfi_restore 4 + 2995 .cfi_def_cfa_offset 0 + 2996 0060 7047 bx lr + 2997 .LVL144: + 2998 .L212: + 2999 .LCFI29: + 3000 .cfi_restore_state +1820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 3001 .loc 1 1820 5 is_stmt 1 view .LVU971 + 3002 0062 0068 ldr r0, [r0] + 3003 .LVL145: +1820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 3004 .loc 1 1820 5 is_stmt 0 view .LVU972 + 3005 0064 4268 ldr r2, [r0, #4] + 3006 0066 42F04002 orr r2, r2, #64 + 3007 006a 4260 str r2, [r0, #4] + 3008 006c D9E7 b .L206 + 3009 .LVL146: + 3010 .L207: + 3011 .LCFI30: + 3012 .cfi_def_cfa_offset 0 + 3013 .cfi_restore 4 +1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 3014 .loc 1 1815 3 discriminator 1 view .LVU973 + 3015 006e 0220 movs r0, #2 + 3016 .LVL147: +1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 3017 .loc 1 1851 1 view .LVU974 + 3018 0070 7047 bx lr + 3019 .L214: + 3020 0072 00BF .align 2 + 3021 .L213: + 3022 0074 FFFD3FFF .word -12583425 + 3023 .cfi_endproc + 3024 .LFE160: + 3026 .section .text.HAL_ADC_GetState,"ax",%progbits + 3027 .align 1 + 3028 .global HAL_ADC_GetState + 3029 .syntax unified + 3030 .thumb + 3031 .thumb_func + 3033 HAL_ADC_GetState: + ARM GAS /tmp/ccMiLMrd.s page 105 + + + 3034 .LVL148: + 3035 .LFB161: +1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** /* Return ADC state */ + 3036 .loc 1 1880 1 is_stmt 1 view -0 + 3037 .cfi_startproc + 3038 @ args = 0, pretend = 0, frame = 0 + 3039 @ frame_needed = 0, uses_anonymous_args = 0 + 3040 @ link register save eliminated. +1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 3041 .loc 1 1882 3 view .LVU976 +1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 3042 .loc 1 1882 14 is_stmt 0 view .LVU977 + 3043 0000 006C ldr r0, [r0, #64] + 3044 .LVL149: +1883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 3045 .loc 1 1883 1 view .LVU978 + 3046 0002 7047 bx lr + 3047 .cfi_endproc + 3048 .LFE161: + 3050 .section .text.HAL_ADC_GetError,"ax",%progbits + 3051 .align 1 + 3052 .global HAL_ADC_GetError + 3053 .syntax unified + 3054 .thumb + 3055 .thumb_func + 3057 HAL_ADC_GetError: + 3058 .LVL150: + 3059 .LFB162: +1892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** return hadc->ErrorCode; + 3060 .loc 1 1892 1 is_stmt 1 view -0 + 3061 .cfi_startproc + 3062 @ args = 0, pretend = 0, frame = 0 + 3063 @ frame_needed = 0, uses_anonymous_args = 0 + 3064 @ link register save eliminated. +1893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 3065 .loc 1 1893 3 view .LVU980 +1893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** } + 3066 .loc 1 1893 14 is_stmt 0 view .LVU981 + 3067 0000 406C ldr r0, [r0, #68] + 3068 .LVL151: +1894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c **** + 3069 .loc 1 1894 1 view .LVU982 + 3070 0002 7047 bx lr + 3071 .cfi_endproc + 3072 .LFE162: + 3074 .text + 3075 .Letext0: + 3076 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 3077 .file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 3078 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + 3079 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 3080 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h" + 3081 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h" + 3082 .file 8 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h" + 3083 .file 9 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h" + 3084 .file 10 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h" + ARM GAS /tmp/ccMiLMrd.s page 106 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_adc.c + /tmp/ccMiLMrd.s:20 .text.ADC_Init:00000000 $t + /tmp/ccMiLMrd.s:25 .text.ADC_Init:00000000 ADC_Init + /tmp/ccMiLMrd.s:287 .text.ADC_Init:0000012c $d + /tmp/ccMiLMrd.s:293 .text.HAL_ADC_MspInit:00000000 $t + /tmp/ccMiLMrd.s:299 .text.HAL_ADC_MspInit:00000000 HAL_ADC_MspInit + /tmp/ccMiLMrd.s:314 .text.HAL_ADC_Init:00000000 $t + /tmp/ccMiLMrd.s:320 .text.HAL_ADC_Init:00000000 HAL_ADC_Init + /tmp/ccMiLMrd.s:422 .text.HAL_ADC_Init:00000054 $d + /tmp/ccMiLMrd.s:427 .text.HAL_ADC_MspDeInit:00000000 $t + /tmp/ccMiLMrd.s:433 .text.HAL_ADC_MspDeInit:00000000 HAL_ADC_MspDeInit + /tmp/ccMiLMrd.s:448 .text.HAL_ADC_DeInit:00000000 $t + /tmp/ccMiLMrd.s:454 .text.HAL_ADC_DeInit:00000000 HAL_ADC_DeInit + /tmp/ccMiLMrd.s:526 .text.HAL_ADC_Start:00000000 $t + /tmp/ccMiLMrd.s:532 .text.HAL_ADC_Start:00000000 HAL_ADC_Start + /tmp/ccMiLMrd.s:786 .text.HAL_ADC_Start:0000011c $d + /tmp/ccMiLMrd.s:796 .text.HAL_ADC_Stop:00000000 $t + /tmp/ccMiLMrd.s:802 .text.HAL_ADC_Stop:00000000 HAL_ADC_Stop + /tmp/ccMiLMrd.s:860 .text.HAL_ADC_Stop:0000003c $d + /tmp/ccMiLMrd.s:865 .text.HAL_ADC_PollForConversion:00000000 $t + /tmp/ccMiLMrd.s:871 .text.HAL_ADC_PollForConversion:00000000 HAL_ADC_PollForConversion + /tmp/ccMiLMrd.s:1045 .text.HAL_ADC_PollForEvent:00000000 $t + /tmp/ccMiLMrd.s:1051 .text.HAL_ADC_PollForEvent:00000000 HAL_ADC_PollForEvent + /tmp/ccMiLMrd.s:1166 .text.HAL_ADC_Start_IT:00000000 $t + /tmp/ccMiLMrd.s:1172 .text.HAL_ADC_Start_IT:00000000 HAL_ADC_Start_IT + /tmp/ccMiLMrd.s:1432 .text.HAL_ADC_Start_IT:00000128 $d + /tmp/ccMiLMrd.s:1443 .text.HAL_ADC_Stop_IT:00000000 $t + /tmp/ccMiLMrd.s:1449 .text.HAL_ADC_Stop_IT:00000000 HAL_ADC_Stop_IT + /tmp/ccMiLMrd.s:1512 .text.HAL_ADC_Stop_IT:00000044 $d + /tmp/ccMiLMrd.s:1518 .text.HAL_ADC_Start_DMA:00000000 $t + /tmp/ccMiLMrd.s:1524 .text.HAL_ADC_Start_DMA:00000000 HAL_ADC_Start_DMA + /tmp/ccMiLMrd.s:1819 .text.HAL_ADC_Start_DMA:0000015c $d + /tmp/ccMiLMrd.s:2398 .text.ADC_DMAConvCplt:00000000 ADC_DMAConvCplt + /tmp/ccMiLMrd.s:2028 .text.ADC_DMAHalfConvCplt:00000000 ADC_DMAHalfConvCplt + /tmp/ccMiLMrd.s:2357 .text.ADC_DMAError:00000000 ADC_DMAError + /tmp/ccMiLMrd.s:1832 .text.HAL_ADC_Stop_DMA:00000000 $t + /tmp/ccMiLMrd.s:1838 .text.HAL_ADC_Stop_DMA:00000000 HAL_ADC_Stop_DMA + /tmp/ccMiLMrd.s:1950 .text.HAL_ADC_Stop_DMA:00000074 $d + /tmp/ccMiLMrd.s:1955 .text.HAL_ADC_GetValue:00000000 $t + /tmp/ccMiLMrd.s:1961 .text.HAL_ADC_GetValue:00000000 HAL_ADC_GetValue + /tmp/ccMiLMrd.s:1981 .text.HAL_ADC_ConvCpltCallback:00000000 $t + /tmp/ccMiLMrd.s:1987 .text.HAL_ADC_ConvCpltCallback:00000000 HAL_ADC_ConvCpltCallback + /tmp/ccMiLMrd.s:2002 .text.HAL_ADC_ConvHalfCpltCallback:00000000 $t + /tmp/ccMiLMrd.s:2008 .text.HAL_ADC_ConvHalfCpltCallback:00000000 HAL_ADC_ConvHalfCpltCallback + /tmp/ccMiLMrd.s:2023 .text.ADC_DMAHalfConvCplt:00000000 $t + /tmp/ccMiLMrd.s:2055 .text.HAL_ADC_LevelOutOfWindowCallback:00000000 $t + /tmp/ccMiLMrd.s:2061 .text.HAL_ADC_LevelOutOfWindowCallback:00000000 HAL_ADC_LevelOutOfWindowCallback + /tmp/ccMiLMrd.s:2076 .text.HAL_ADC_ErrorCallback:00000000 $t + /tmp/ccMiLMrd.s:2082 .text.HAL_ADC_ErrorCallback:00000000 HAL_ADC_ErrorCallback + /tmp/ccMiLMrd.s:2097 .text.HAL_ADC_IRQHandler:00000000 $t + /tmp/ccMiLMrd.s:2103 .text.HAL_ADC_IRQHandler:00000000 HAL_ADC_IRQHandler + /tmp/ccMiLMrd.s:2352 .text.ADC_DMAError:00000000 $t + /tmp/ccMiLMrd.s:2393 .text.ADC_DMAConvCplt:00000000 $t + /tmp/ccMiLMrd.s:2507 .text.HAL_ADC_ConfigChannel:00000000 $t + /tmp/ccMiLMrd.s:2513 .text.HAL_ADC_ConfigChannel:00000000 HAL_ADC_ConfigChannel + /tmp/ccMiLMrd.s:2879 .text.HAL_ADC_ConfigChannel:000001d0 $d + ARM GAS /tmp/ccMiLMrd.s page 107 + + + /tmp/ccMiLMrd.s:2888 .text.HAL_ADC_AnalogWDGConfig:00000000 $t + /tmp/ccMiLMrd.s:2894 .text.HAL_ADC_AnalogWDGConfig:00000000 HAL_ADC_AnalogWDGConfig + /tmp/ccMiLMrd.s:3022 .text.HAL_ADC_AnalogWDGConfig:00000074 $d + /tmp/ccMiLMrd.s:3027 .text.HAL_ADC_GetState:00000000 $t + /tmp/ccMiLMrd.s:3033 .text.HAL_ADC_GetState:00000000 HAL_ADC_GetState + /tmp/ccMiLMrd.s:3051 .text.HAL_ADC_GetError:00000000 $t + /tmp/ccMiLMrd.s:3057 .text.HAL_ADC_GetError:00000000 HAL_ADC_GetError + +UNDEFINED SYMBOLS +SystemCoreClock +HAL_GetTick +HAL_DMA_Start_IT +HAL_DMA_Abort +HAL_ADCEx_InjectedConvCpltCallback diff --git a/build/stm32f7xx_hal_adc.o b/build/stm32f7xx_hal_adc.o new file mode 100644 index 0000000000000000000000000000000000000000..777df97d577f43cfb95ffee4c6a16ed202a646d3 GIT binary patch literal 32704 zcmdsgXG9+p=WKk^r*=ZQXLq))uK{OcFpC z!vG11Stel})+8j85Fn610)a5V5Fj9j%m9vuVF_?i(M!Io^|>yIZN##>?`TCfESFdmYS(RDRl(oI z;0~=%j2AUUl=mL8azX#k9#W5~5+jIwW(}=Zs_aME54!8kzMA_=`f?|-v(mIuVjW5=3Jvm$F6?)a-&a#OnbPK{|?>w4X|$@rXct#OlD@R$8| ziI#DrZ+Sy%u=>c@uq$*{BI1KR=6H2q@r2h^9a6>c7#N%= zb`^G;>CT(GiSQ-`Jr7i(Xg7)uFcznUND3uB}cTpQW|4v*tm&P;*pZ z*6WNs*gg>}_s$`UGd;#pft1(L1{2xHR1MHDYeFjEx)<#k`0F7R_zTVtasK%byZj}u z&8qq2=rOd75mW)3#YWJ|)(pwktr559M7-G}23K3o!+g}k`3-rHY-c-?4ytJj!;Wx6JT zm=_~3|8-g!n{{{ffmh!+G&qriyrR?*HBu5P(d`;+pRxar-k&~vU`Ni8A@mIGeQ+9V za|A=H57D%zXzp0d}vB3mP6 zn>e@4`wac}ztDeY>)u-A=)bf6*ZXfkDfi?)JZp+R%<*Dm`S+h0@gXOe+xxu7>C69l z?ATw~pDP}`Gq}>$#*jR4sE!acnLr4i)RUWchfP zo=dtgmtc+y+_7`ThVgEGW{2+BxqQQTs5pZ8MP+vcBGs7B#=5F;wI{+kY7eeb>(zUW z#%((}Zsx~Y&>kzvGf-FPxkDw9xw^e($6ByN=A_R)192p0V{~-`4YM1g%)Gba(MdDV zW0->Ca}Wvpm^2?P8|OX18Vk-j$!gCznE#4V;~P81cJ4d6qT;vryB4J5u29T7_rw_P zR>gg((#|CzzaFEi>`&v2Gl)13W8B;KDtjI?Bd_!gt>=F!502^lr97%>-sK{*BcG2v z^+7Nv=kV#Sg}4Xg;ErcvW~@G@_rfaWbxwEU?K^}$#;|M2Pg>HCKs<%~PF%)WOsQUhiF z`w&~(h1Mn~;5nhguE_}_9>=ByL+|coIg|N588T0H(45e%@oU4i@5ji+4<|fg8F^y|9prZ-^X3A;sMOCj?sK@ z%#_ib8oB>HwWZ)O|NP=t-I3QL*WB-Vr`k1p^_B@=diqDM_XCGrt~WYTBi$SJ;0}F4 z;Ib12u1V6un*$c>>((!|tvpI`Ut4M*_W;6{n5j&LZ$rFQ@gZA|6il@lUm+HT3}Ii+r?%lvL~EvqG~(=R9ARWrZ)H-}KS9rRV@ z&_3KnuBBZS(>~nw=pid_kM5tdp_(gaS9Qlvz{{Ec(Eh@P=1Aa(Qq3LBk>HUr;60G! zZkRT|;ITc`-`}63<>XUNJ%1#v;p*yJ_h&TZL^3ws{#RGdHR+6`MH$y%CcV*EZCqpA zsOJA=|5b-vfv;f=nuBG$Ub}G4z`-?*HB&Dg&we1*wqG{pmyRpUk;M~?upm+!$!#bO z@~S$L9x1M=?kJ3Gh%|Qms*!VvcBDc?IQGPCtLty$Nem$g8!bR}lx-s>lAe z?wG=i5yW|4mQpS~m${9NKBdy9dz9LpqB#j4t`y%@V7T1AgV1*w-nCdxyIh|4q3?2g z?jV)osQ{Q~p}4EOpq=VQ%8O7i@t<-nnK?|B%XbDS^GYwSm(RQsEcf}A<+AOCD)U((Q~as){G5>K z{%n%Z3z_Y|)D7}iLgx9uLh=P63;b7;d{M|E|2IjF3mHh+(1tMf3t5`dNb=W0miaf) z(Mv)u^f#0IjgS@o(@6fCkjwqI(DJ_vxys**+?g*6S?M1j`HGN1{|L!fg{<|z%d!WA z+>la>D1IwcqcW$Xoy>#gw~;Gfy7`*_1kfopOyKLH1hNL?e+h{M(!?7=rYQ4aHq@Ku zTgZHBfqA>(zZN#qSmsW{wvm1kx{Z04O}o>Yt04cDO{b)zhbi;hHl3b6LH+O8baq-j z?cHtDc`9Qi6~1ejC&O8$&tN}t-)#I0RMt0;JeA#A*QSh^=nmuGDJnyMQdtinR706( zv&^?lmT{%HABIQ_dFC0}s8rTEe5kCOAuzI9aOuh#hc5c*0SG(`%|C#$i!3!xVUahH ze3kWcMc{^M+a3~e__837_C+h$tD(hr?7+D{qYObu$vHxX_l0 z`5&xvzbgX;+$=S17rb|PugG2kfq#_Jugu{!#;ZS%zOI_hWVuS*{%uUq*Jm@ku9D^c zHyHQTvm3Q^g?}xj*UmXbmtE!eGwy$!%faO;sq{CnR^Jpd=)Z{M4MNuXZ>HaygxuhN z4<^002-)cWkmZBw-pX@+^2#t575_lT;%vFe5?GkP%HmS`0%Zkq$4d9t`XAhzY8{ecH5`;?}h`P z-S+AJZB(`!JKO(ln%XL5^Za*E+9qUye>$q>J0q7P!c|h_|25L$vl~0$|0NxrE6Sz* zH6*))Eb|v4!@jVTMbGG=ryZ`(qgK9b--y4THDMq3jY=8iA0m04kZ!-9p?^`x6#sHY zbBU1YN{=evUe`PtF7RF9{|{QciDkYLv-mvn?Yk;w@j*(z9b|{Q)rD_?Ug_LRYSy zi;Sb7i`ckUFGRDk* zhN4lLk^z7Ne&8@F&@zQ%P=sg^eV2k8z&Yz35XMO<(`m8^j7>O;IB?5T@iFsfsEm;- z=E&*5Xtx=3eks z(A>x1{t>5TZof}Q7e$r&a29QY?_^fnXjXF#hGca6tTdvSLZn)~3F?Jfz1vq#^&ddfUUfTO?E$Yy#vyjFXmw9d$xC}}0I!@E)vSZbs)#7#-6Y;{X@lea3S zT0w7>Nvdp7OSRIwCZ^g%)kR6F2V$y=yr+ulT;rDvV6Hdbf+(uv%}TR#G1seG@Fi6F zMV!dsG1~uwC!Rqz#z&AD-LX=C@SH*?OJV;coU?XN{EjD|D~oHv;L=ie$|$s8b2i(u z-C=VK3@+Y`!!eufo>jD2i3Y5|S@<4XrQNfE8s7usdNSW+_S-$%II=e(&{J_*P1Wg< zrs_NKSqM3$%r;s$2n=fwpaog#B%_YK;bFHIAt<#Hp9fguC(`YdJnUY`Kt2KYBb>8L z2LCg+o>b>UP=s?G{M=%ef)T(uuLs50yjQ?0 z#;ObR^t^-MalX67!OMmlcCP#4yc4;_;9!<=7<6G~@;Z0C$r@pb1N%c1v-zh*&0x#CYUERWS- zuEbeXWP9wgJbInsH)gZkm}n zEAuq(G^54HMn`d#s|AWYTCwJ+_+XKf=3i!$-CU4ur9q4iN@_G zEzK%pKshBtnJKo3Rp=UiFk&{zNRn9Vpz)OW&AV zsiiYwY~*AfD$F7Uol*1!J(#5A4IY!X?&1$V)h~17zHs-p#KdI*ID2dc{ z5?;|2dki(rSOO0x;1Z2RXS1&a*Ohv8HBvKYl8;pJ5lHX>)w!|2r9L_&TfKNnsU2`h zLU1rvny8*&>O?D4Mt#y0YPQXJwi@eH=5)a3IytfA#@tu}(S>>F;i@js$hD|TU4ZVG zcwlBxhH55IB~`^%a<|46DMbWSj58DMqr!jBK2@f&kGVjHNG~om#6_yYkp47p`m3!e zYJ*a8pu5ljAzNRz63)Wu41sj7B_{MGiAfJyVgkK7OM^@}=ykj@E;X_$ zZZIK{km?MeAlr-y_%uJ%`3$PkBrs*|8_@jj4qSKP#I?o&>)K7^+Kc?-9fc6UErBKs z)k+9iTmp@NOBk}a1e!fwZCDe!B(m1HP9gr$y3Qs}2%q@Ab*+($ZRlr%$CHquwF$q} zmo0?DIGz21^n?~~C2&3G6qB}M-I@@q^eV>6fZ)fD%UK!*Kjlb)%up=^E5O!-09|_9 zb89@n)`S2>%mBFu!iXZok}2YNfUOAuir5*Qv$bhzig`fhsOBz|vz*4-z;L_q^cN0o zlD)(lFBP{EIemH5F157qR$jg-dHFv=E-Ac~moC`wLOCT+cq^|9ak4PPyrg4W z3~hZF9*;{Opr-QeRioOR?OfAiaqpTATJArB4IlJ_^`&wDwu0r3pKLZO2dBrGR;_8l zP^a0k#F?8Ub@DNU?d(sCiG2vj6m^6yAG=W)gmL{ENi3yC;DJIQUMrlG(l9;sqGD0;I z0!d=h#W+!#P?{treUc?6FfUHu4BS50i|B^j3FlZ` z0t+8!hPBFWjh8)*WzW?Gwi2weu|99r1AH7_oU?JVHbkC?gJ8vRx^0UZ=Ysu!);OL0 z(6T!zgOI3|TC16`3a7JCNw2oVgdk3*7-Z~l;fifeOhwqZP9dgS*BUwBk{>Jd87{sD z9n_NWeVk7Bq+hVagz+RX=_8hy@IOgn()x=m)l6WVPUECAal$u&-$gmaq;o7WfuqqW zCe4`yrR@pDDNY)w%!^Zu$YO_cEU}50KO)a@8)1&cCC~^$Av9ZD0?kep3VWD!ZXNDci$_O>7x(pcE#BVUy|{C@f6>6; zKzLEOv#WRUl4a#f%a<(f9q8^G4TY6$s-~%RW9#DD@UGtOFzm)nFW#7>Ii*u5DK!%9 zU$(S|;Y2$7+B-wt<=yDuV2AK@OL>H?E-EXb1O~pTjFm|uwTV!;2W&KUOv_^TcTUBo zLreSok!ZNTJyvKc(@<^?GlpdA7E5^y<~4ktjY<#K$RJD&iHMY#8?hyz4xET;v8kGXowEya;uYFqYVi zsl=w&Of8=}3{*nLwbt@e?ybmAuyh=^C%`Q;Vfrg=y9EigFA8`HsBoOx)9v382Rz0a z)YLpDkPuL;=DMP0enVX9@?(U=TkTa7t(NC8ywkCIbPAquL6Dmd9%RD;GGb(MDi02FF0dP7E0j8Vhmc!TlKvESCAUxRg&edAz zqq+I`8rJP<;78>QPa358FoS-z*|P#fagQgX9QB#2>+SOvdosbz^{)1qH4=xns!!)S zh3Q!9@$86G>pUJat-+|AzRr_^V!m>;dloLxMt*kP8MsE5Ni|CpeZtW+8`bD+5r(cJg6=KJy4KVjB7}k{50gF$*9cp zd**nUBti_WZw&+6r^DJRwZop>rw`hv7BT%NyBDK?Z<2 z_Lq}F6DCD+L(0_sc^j(tzuKSA{%jq3eZVaGf8L>Qh><*ok(16#WhaI;=H%;!* zJJ_RV1YDj3EB~1)J({DFovcJ=lb-+G>|1xDGLB~J_O>v7c``3oHl3|IvVB)v=Q)K# zB~Xdc^y%|ZF>hPugBO*Xiyh5YGvz!a(@?1Vc+=3<<4i;B(C3$XIRPe2ME?+Px1%ah zUhc|INcSJo&}g~&`IwkczClkmF7FDRYv+8Fi@NHYV9=9cU8Yoe^36WZCg$A0*&d%c z9Q71HN%TUzR+Z-JZ@Kq~{~t;ElOS_n9A9;>q{e zM~)}BHd{vW4BStRiX?l_9k1By#}hp4x9ly>)3*k_BAbi5Fv3PZ&CSEi#W~i)n+w-W z`tHU1mA}F2BLPqD8qZp$V2;OM>{*M?wVu_OEWI^Njk;_qS0K3IwV)}Ndd#NWys1rY zl}_jJuki%M;9Ae;v_Z_iFpJOJwVp*ZUYcm!*W&R66Kq%5*7T$v^NB{9t~>9xKywwU zk-4qO<7;MN!<(GVyX;(hrt5sn)$M3{E8t(RB~5SD6vbZ1vQk@(+$9XU^TODtV@YtxNjrdR4bV*Tk0pfAvkd0xO&SEQW z$O;pbvC=8r!yz`kTz5pMo8FrErI}jkAo62NyA-ckW2MBN@G!B_dXF;{TBo~eM{HAR zEMN}|dIAL9bh_Cx%RO4KIWAaY3s_%Ho0+n#aOhaKK@@iAFuh#l`2x6ouffIq9#0m# zrZxQhSVMB}lFv0HgYcT)y@=~iBj8F;nD8#;_NpK^*YtDo;WY>CInSKN6`Ko7pnMp@ zVs)iXb}vvN~@fHL0l9TxZXR=n9>c^u%CWG2luANh|r6 z8L>4hPMQ*bM_I1!Cn7teGuj;q4Q}5&+TRr(R!tT7rNG94-l(c=s%qy&+xbJ`+HjB3 zTX^tV+p5~?+FRf<+%>$V zr)G3`I6M%gLww5s2Q8fgJ1505DPaCWft6qw&4Yb?^@GE8yI@B}`-hhBV`)shJ{+wZ z9v&QyF;IcwXggA(;vq6J39>uVIjpwzgoihD_Vv^Z^+jts`}(>%yLZNe&;~ZfBd87Q zEVEG4l1W7x2fKGBB!$ixI6|-@tJ_>v-B_oZ!^6Ep5q`bV6z;Dc9Uh5VIjZd)>5eDJ zu1DQ&G{BBpzW7y+VHmEAR)2JuBuYj@`W z%WI->@VvGN0*DOugR-V^iIh)7n%*Ct~($BAo*R;Xc@jb-7VwcFD^2sA|>U z%G3-Fhim#6J32&r_wW*{!4oW5Y1lXr3h&nLwrom_p&iYP(1xRdgkm(vFP=s)7)D2Q z5sooyJXKY1X=zisX=_+ryQ88fT7w788yg1w%(<@5V1NJMK)c;i8+x}#67#~cqa!i7 z^nN5=cRqVaS9KxSn9IiSu5jO$(dd?*GkOO?gXbmmWqNIm4i4F!(e6enVLbP4S9M!z zTEl(Pl6GxalG$kqj|}#W>PC))`a4y_mU{eZjGs&O=Q91dTs5?AZILk_8|*qxq@}G_ zI#}bDnoV`JvG5@}y|Zr=UmYU3R&TWH-%#7KTn|$#&-NJI*k<*xre*}uiqEC7uN|lS zG7;ZkE{=V9=lCuW!J_#XJr}SL4aR8lQpgZ2o$=PeE<7{P34wL2- z+my@)S}vnG-sSa_WH+$xLUtCcuE_}{Ce~BBp0m3LM+Y#ct0=OI7||`z@i@KIZfw;P zj@^`O_(_pDg$a`jLv`Lv+BuOWwGKz(vZWY_^&9KA=oX>5x|WtLEehVEy#u3zqa*aI zg?b_m4UTs8g>{K|$JgVx8Ph{|CubsEd8NxRjKnTsN344$Vv4m|Vi(z5i=Pw5L)Mqp zG!Pqn>o=bks9ADK!1@9^u(V?7vLzK2rv?`FcMpxO>Ba~P?_Sh@3g~DA_gY{N_&r0r zRxAoFSxK^Qurs;{-+`~e-6RA?=Wusq4Za=UbxL?q|AL;O^3YIV(RTbFIm;l(}SQ0L;N zjm>R~TRKC%gUyk_=-@zacYEt-*GPD{r?WfUKHM4V9A3OWJP;o4j1CUBH`i1rDTC8K zGT0MER;&@lhO(wrtM{LrYJ4vDuA-EuqiCO1#^(gugHv9*N?Pr*F8{ zomQ={saYK;Te4!cZuH@B-;za3PfqRuDjk0YI)(#Z-F-O|kKmHF5B?>~N%K4X0$T{= zUy7E!cyH=AE-2LR+>48h;)x)e3ec8#WHrc^!kq}3+;E2({0^>*(ycBX1+ zJu2^v(GA69x@rlSo%}1BGUnmZb4uN!CgsiWHThksDLMFgWWF)OEHGvog+>v608@-u zk`E`#t=>E4l;f*pCy76gG2`(=|DrrjLhe@i4w`=#?EpN@(CX6z`$}G zCLV=J^p~OItBmRJ8JYNDs>~$)%(xI&CZ17Fw3nSE&q<& z%h{vpKR-!7U+bR}v!Ac5M`^6bK3(_$;{w>Cm}Ad{nPi>N95*gijL-OCsu@Z4XK4G; zn97XU6)#LRGf97DlDsfUUYI1Gl_Y2M@xw&CiTQSpQ2L*pBS-`jj|#whxZhyK&Nf5N8hNhX;jzLerV* zMWB69|F<})&--o;#{Y!SywB#~KLbcPGH2k7;>6UTXz`9JI%{$m0Da2ji_S zN!}`Q&YU?IUm>Bb`WC7S66jg##sqq{`dI=!N9`Ay_s|>_h&?d_^ZFMTJ{X2b^K;N& z`9ciRR(xe@h0we+3B1H?Acwn=Wi5?07g!EyJ3fA{Nz#GRIH)A3c3us-d}E4!4nL9sW; zHaB^9ZSzq>YjfyeSY1J{c~kMbidE=$srZ=@XRg#%JkW;D={nt7FQ=YqJtRs@r5w0c zkoR2bJx%&tJcufEgm@x;XF|mE%bz&9uvp`oCAC8y^~SSGU8M2x3UNEudeBP^S!<=# zur+pwx*YWSs0aEW?ZGd{uWN&~MszjdM|-4!yq^$xr*v(?4;hJ=JQfOnnIPvg>QxEC zl%}@`(l6zVlZX&CjtYKJ@G8L@1P=n25WHUSJAywJd`j>)g1-}dUl4y2(D4)r77LaMmJ2QyTrF57*do|2I3Rd| z;8z8268xUv!-CHUzAX5b;GYHE9xJ|F!D7J{!R>;(1TPi5PVi2_`vrd?I4<~~f`1hJ zn_xNy2HUAfaEV}0aEsu%f&+q=2wo$2yWqWoj|sjY_?qAcf-cM<^gB&3Ah=j?tzeU2 zui!4heS!}Q{zmW(LB9LKb*fT-68wO;QK`R)+@E668G<=P#4}syV!?St*jXa-)kN$o z*9!8N`n209@@+z&BiJeYexbi0xQhroVJaA<>y%m`xJvl7#Etl2nBW%SpF^xsszb0} z_~#QhDs_S2Ug2L&3@Y`Hf;Wi#PLcmm=pP9_B>Wcz4-)ZCpw|W8ByPk{ABl+nBcVSL zG;t#$KZ^*xT)_h2R|uX;T%pt&!3N=qCRKaOP@MjatuqGEgN#qqGuM|2cSSS3gLZ2ph z77=#BA|ECeE454Ti$wU}EAo9pUnh8j@V_PWcLnbe{!fMex!}JD|0N>)yf5@$iP(M| z6ExE;zZpc-cc#!M2o?*!T;s23{yuB~@7vXy|z{j>ZRS*w~YrO(u6MoMmbeZ5H;ja^HBo^Wq z2!d@y_&HbPJA@t(91;FSLSG_yx$v(O`g*}zg#TTke;{~25q^Ir_%yLesh5ZaSPuyP zmWX(MPi#`^J)!?B_>u6v_$r5b_*ztB77_Zhgq|ZX zw@0vF_+KRA>z)e*_lW$fBEMefn+0zd{*MG7A>w>o@K?frP4E!Wk5^>~9u>YHzY1Wy z(}~z{77ETLBF-|AFBf{1;2Pm?BBI>sLU$7}Mz#y?B*M-YM1FzL7Ykk{{A+~%hTu&^ z*tts(%T9ft!*WC;x~oR+k$L|s6~t7b>BWM2eGECOsQK6;XzU>3{uUDK6C4uUD|or! z*9ET?{Gs5F1b-&@nBWUU+~h(DIQK5GWUL<&l;FW^-s$JXph9JK$pk2P7i}&681RoN7MDP_N?z4J7 z1N@!PhXna5E>{rW*>L?0OcTr!oFO<%utad4;9|jLf_#Y=?X(J>C3vo2Sg==cNH8k+ zCBcgXFB7~{@D3vGLal-w@=R!)V_tm?5b5 zA>bDX&6i_RuS9U3V7cH@!D>Oil8O3yzXIGU^fp1ge*vE_DWl#VLA`$geU;F+2;MHp zcWF}p`+|=MJ}$_&e{p^AvfyiiZwT`3U%ZchBIw0HCe0U|5px8m3-Y~S3<3_5KL_dxZY6;7A8mme6{?3i?B#^*$B!v=plx zUsK2OWrB+ZmkIJMa$J{g7CcSxOhLZGnR2}^1xAJDYqiPeTjsb z62X5E{F>l3f_DghTkr>h_X++&@F~IP1;+*Xem$<2-xWL}cvO&Y+M_&MaE9P4LB4d4 z@}+`$e+pXfPl5cMGUaW8dY=lqU1+|FkMiAuV}g9QCHY?w)caP@d=Vel*>?zjPw*Z= zzLJmfX9f2Q{+poQ$3p(P(1!%y5#(Bv<@J6Rm?5;@&w?%xns4Z$UWwp5!D_*J!Oem# zf@cbTUN9sW5gZbX3VuoOB0;_Zko$=n1#cJB`&#fH6#8Mo#|57hJV?a;;&s8d1>Y4s zB6w7g4=YgLEy#BXl3pdaPEhY-!EY7%48d~+y99>?^}ZGQ7YKc^;MIcvD0s8rZG!g- zJ|Orr!N&w&6nshWfZ%I_dcO<5dcOYb!p_Y?-zoSVLB0r)efD1jpA&phQ15pk z*ZW-{Uz14vzY21%NLuf6ff+(i6D$xc5-bs%Cs;1HRFH36q`fx5a|AmCw+r&smfEiZ zuDAX!!teVqr1btYK!lw#B6KT=$ipfk+9OCrf8Rhvp=KiHhiyd6*BwOMA0kBD_lJlu zwwt&B>j2^+r7kC8lemwFec<&(Y!+`LuCV^@%lp^8q_KZ|h=_gA<3y~3pCJaV*JW_u z^9t!Yd=OC|EbBC;5HY8sn`z7@qJDXT1w_;np=%5fp;Rh}&~?2R3RVzN|K)h z6}+5?yna=19})SzPVjmn@_e)4ZA9ezF2TEr$ouyN?ETD9K^spd@db``s?`; z^)@(OQQtQ>Zi2{L77+Ejmxy}hv0j^H{2<0sp%H?v-*TZ>5#gg*=r$s3b_g9JqTae4 zVQ-8y>aW`ev~C~d;cn5_?SXteDfBZ$=Mj;w5?J;7j+_Mf`#haAfB)M}zcKNOtEia+!)SzR7~m@Kd! zgh(``e>yN(b@GD{$JMcZvNKs6dmv)6Lp~;PyaIUaVM-YurqCjtLOW-%Cn6GkOnNS2 zvUt+d5%GBB5tM|-QW6au_X&zbwZ!Kr;tuTS9Zyumh2q_M>R}SwuGthRN_^5HF_Prx zEfS@%r!FS39Z`hBU8CFEdk1<3(WCWsXIIy7c$XE4#lg>XoMh*4=fL(bx;=Zer7@X< zUpR$rix@Ymyc<8E;m>ItrFw=t@e`=>s+Okm&S-SFw`(*Cv!DH#1yu}pg{fU1oHLyV zhO$29;*)x~Rp=vGk1`(faHin=dwL6@lkAuCp?$dJ0@F}}o_;39Rs!1botC7>XI8d3 z^lW=u!NYAz1x5C8tF;cJALf91j6Z_Y8Q+s2Y+n$?uJ{|7TV2fFeYkeoTaJbaf@dFgUY-HNsmFiB;R#y_ zXxHOOTs!Mg1i!d->Uv}X?Rvb6Yo|Sam&xY>?ZdYBHW*HO3mx`o*S5#M4LI#R06{Go za!`*4|CZpiSLw(LZs{?5e4gBC?^xtVq^F;apn@E>-nWwU zYGKcoQPsYFK1r`0dRX4Y4qNXT=sEKeb<~4PB-R&2)musSnvdf*1BRg*t0UjvYWo5^ zcD*P`uMK*9uG2p3GAHB08Q+%?UjRyMH=-S1Lz2BKQD{2k_F>zrPqKHjqrSyZw(WH$ z*}Dz)hHYa&+aCXA24{SC!Ja+dN*(t2HyvkQ^3WJ>I_gWmJot|vIPE>)i0>rG?fAZ# zWRKsCOw~{M&nr3o4y9W*v@?7_tdHlD^rFYnJ0yBiOzno=gIMp|hh3%LLC;x_N7!zN zk?n@1bF3a8B-vYpPWNN*?8CN)->B<)*!Tb`J3j6K?J_hm8~cfWog&XGlI)cZS^Iw4Tkfz|C-xXKkKeDw{*ZylL0>$Zll10p zu+|L8dY?~$tbU%7;zcxga{+s5hba pI40Ce@VR!Ny=401jInstance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Enable the Peripheral */ + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_ADC_ENABLE(hadc); + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Delay for ADC stabilization time */ + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Compute number of CPU cycles to wait for */ + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** while(counter != 0) + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** counter--; + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Start conversion if ADC is effectively enabled */ + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set ADC state */ + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* - Clear state bitfield related to injected group conversion results */ + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* - Set state bitfield related to injected operation */ + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC_STATE_CLR_SET(hadc->State, + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_STATE_INJ_BUSY); + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check if a regular conversion is ongoing */ + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Note: On this device, there is no ADC error code fields related to */ + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* conversions on group injected only. In case of conversion on */ + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* going on group regular, no error code is reset. */ + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Reset ADC all error code fields */ + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC_CLEAR_ERRORCODE(hadc); + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Process unlocked */ + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Unlock before starting ADC conversions: in case of potential */ + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* interruption, to let the process to ADC IRQ Handler. */ + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_UNLOCK(hadc); + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Clear injected group conversion flag */ + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* (To ensure of no unknown state from potential previous ADC operations) */ + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check if Multimode enabled */ + ARM GAS /tmp/cc5LZY9S.s page 5 + + + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(tmp1 && tmp2) + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Enable the selected ADC software conversion for injected group */ + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** else + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if((hadc->Instance == ADC1) && tmp1 && tmp2) + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Enable the selected ADC software conversion for injected group */ + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** else + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Update ADC state machine to error */ + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set ADC error code to ADC IP internal error */ + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Return function status */ + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** return HAL_OK; + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @brief Enables the interrupt and starts ADC conversion of injected channels. + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * the configuration information for the specified ADC. + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @retval HAL status. + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** */ + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __IO uint32_t counter = 0; + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** uint32_t tmp1 = 0, tmp2 = 0; + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Process locked */ + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_LOCK(hadc); + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Enable the ADC peripheral */ + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check if ADC peripheral is disabled in order to enable it and wait during + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** Tstab time the ADC's stabilization */ + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Enable the Peripheral */ + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_ADC_ENABLE(hadc); + ARM GAS /tmp/cc5LZY9S.s page 6 + + + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Delay for ADC stabilization time */ + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Compute number of CPU cycles to wait for */ + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** while(counter != 0) + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** counter--; + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Start conversion if ADC is effectively enabled */ + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set ADC state */ + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* - Clear state bitfield related to injected group conversion results */ + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* - Set state bitfield related to injected operation */ + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC_STATE_CLR_SET(hadc->State, + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_STATE_INJ_BUSY); + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check if a regular conversion is ongoing */ + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Note: On this device, there is no ADC error code fields related to */ + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* conversions on group injected only. In case of conversion on */ + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* going on group regular, no error code is reset. */ + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Reset ADC all error code fields */ + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC_CLEAR_ERRORCODE(hadc); + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Process unlocked */ + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Unlock before starting ADC conversions: in case of potential */ + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* interruption, to let the process to ADC IRQ Handler. */ + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_UNLOCK(hadc); + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Clear injected group conversion flag */ + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* (To ensure of no unknown state from potential previous ADC operations) */ + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Enable end of conversion interrupt for injected channels */ + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check if Multimode enabled */ + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(tmp1 && tmp2) + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Enable the selected ADC software conversion for injected group */ + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** else + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + ARM GAS /tmp/cc5LZY9S.s page 7 + + + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if((hadc->Instance == ADC1) && tmp1 && tmp2) + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Enable the selected ADC software conversion for injected group */ + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** else + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Update ADC state machine to error */ + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set ADC error code to ADC IP internal error */ + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Return function status */ + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** return HAL_OK; + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @brief Stop conversion of injected channels. Disable ADC peripheral if + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * no regular conversion is on going. + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @note If ADC must be disabled and if conversion is on going on + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * regular group, function HAL_ADC_Stop must be used to stop both + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * injected and regular groups, and disable the ADC. + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @note If injected group mode auto-injection is enabled, + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * function HAL_ADC_Stop must be used. + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @note In case of auto-injection mode, HAL_ADC_Stop must be used. + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param hadc ADC handle + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @retval None + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** */ + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check the parameters */ + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Process locked */ + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_LOCK(hadc); + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Stop potential conversion and disable ADC peripheral */ + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Conditioned to: */ + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* - No conversion on the other group (regular group) is intended to */ + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* continue (injected and regular groups stop conversion and ADC disable */ + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* are common) */ + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Stop potential conversion on going, on regular and injected groups */ + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Disable ADC peripheral */ + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_ADC_DISABLE(hadc); + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check if ADC is effectively disabled */ + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + ARM GAS /tmp/cc5LZY9S.s page 8 + + + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set ADC state */ + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC_STATE_CLR_SET(hadc->State, + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_STATE_READY); + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** else + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Update ADC state machine to error */ + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp_hal_status = HAL_ERROR; + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Process unlocked */ + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_UNLOCK(hadc); + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Return function status */ + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** return tmp_hal_status; + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @brief Poll for injected conversion complete + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * the configuration information for the specified ADC. + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param Timeout Timeout value in millisecond. + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @retval HAL status + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** */ + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** uint32_t tickstart = 0; + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Get tick */ + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tickstart = HAL_GetTick(); + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check End of conversion flag */ + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check for the Timeout */ + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(Timeout != HAL_MAX_DELAY) + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* New check to avoid false timeout detection in case of preemption */ + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->State= HAL_ADC_STATE_TIMEOUT; + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Process unlocked */ + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_UNLOCK(hadc); + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** return HAL_TIMEOUT; + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Clear injected group conversion flag */ + ARM GAS /tmp/cc5LZY9S.s page 9 + + + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC); + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Update ADC state machine */ + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Determine whether any further conversion upcoming on group injected */ + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* by external trigger, continuous mode or scan sequence on going. */ + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Note: On STM32F7, there is no independent flag of end of sequence. */ + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* The test of scan sequence on going is done either with scan */ + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* sequence disabled or with end of conversion flag set to */ + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* of end of sequence. */ + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set ADC state */ + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** SET_BIT(hadc->State, HAL_ADC_STATE_READY); + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Return ADC state */ + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** return HAL_OK; + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @brief Stop conversion of injected channels, disable interruption of + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * end-of-conversion. Disable ADC peripheral if no regular conversion + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * is on going. + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @note If ADC must be disabled and if conversion is on going on + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * regular group, function HAL_ADC_Stop must be used to stop both + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * injected and regular groups, and disable the ADC. + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @note If injected group mode auto-injection is enabled, + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * function HAL_ADC_Stop must be used. + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param hadc ADC handle + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @retval None + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** */ + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check the parameters */ + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Process locked */ + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_LOCK(hadc); + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Stop potential conversion and disable ADC peripheral */ + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Conditioned to: */ + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* - No conversion on the other group (regular group) is intended to */ + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* continue (injected and regular groups stop conversion and ADC disable */ + ARM GAS /tmp/cc5LZY9S.s page 10 + + + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* are common) */ + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Stop potential conversion on going, on regular and injected groups */ + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Disable ADC peripheral */ + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_ADC_DISABLE(hadc); + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check if ADC is effectively disabled */ + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Disable ADC end of conversion interrupt for injected channels */ + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set ADC state */ + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC_STATE_CLR_SET(hadc->State, + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_STATE_READY); + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** else + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Update ADC state machine to error */ + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp_hal_status = HAL_ERROR; + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Process unlocked */ + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_UNLOCK(hadc); + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Return function status */ + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** return tmp_hal_status; + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @brief Gets the converted value from data register of injected channel. + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * the configuration information for the specified ADC. + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param InjectedRank the ADC injected rank. + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * This parameter can be one of the following values: + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @retval None + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** */ + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __IO uint32_t tmp = 0; + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check the parameters */ + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Clear injected group conversion flag to have similar behaviour as */ + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* regular group: reading data register also clears end of conversion flag. */ + ARM GAS /tmp/cc5LZY9S.s page 11 + + + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Return the selected ADC converted value */ + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** switch(InjectedRank) + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** case ADC_INJECTED_RANK_4: + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp = hadc->Instance->JDR4; + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** case ADC_INJECTED_RANK_3: + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp = hadc->Instance->JDR3; + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** case ADC_INJECTED_RANK_2: + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp = hadc->Instance->JDR2; + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** case ADC_INJECTED_RANK_1: + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp = hadc->Instance->JDR1; + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** default: + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** return tmp; + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @note Caution: This function must be used only with the ADC master. + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * the configuration information for the specified ADC. + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param pData Pointer to buffer in which transferred from ADC peripheral to memory will be st + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param Length The length of data to be transferred from ADC peripheral to memory. + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @retval HAL status + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** */ + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t L + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __IO uint32_t counter = 0; + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check the parameters */ + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Process locked */ + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_LOCK(hadc); + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check if ADC peripheral is disabled in order to enable it and wait during + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** Tstab time the ADC's stabilization */ + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + ARM GAS /tmp/cc5LZY9S.s page 12 + + + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Enable the Peripheral */ + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_ADC_ENABLE(hadc); + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Delay for temperature sensor stabilization time */ + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Compute number of CPU cycles to wait for */ + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** while(counter != 0) + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** counter--; + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Start conversion if ADC is effectively enabled */ + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set ADC state */ + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* - Clear state bitfield related to regular group conversion results */ + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* - Set state bitfield related to regular group operation */ + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC_STATE_CLR_SET(hadc->State, + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_STATE_REG_BUSY); + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* If conversions on group regular are also triggering group injected, */ + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* update ADC state. */ + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* State machine update: Check if an injected conversion is ongoing */ + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Reset ADC error code fields related to conversions on group regular */ + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** else + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Reset ADC all error code fields */ + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC_CLEAR_ERRORCODE(hadc); + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Process unlocked */ + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Unlock before starting ADC conversions: in case of potential */ + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* interruption, to let the process to ADC IRQ Handler. */ + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_UNLOCK(hadc); + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set the DMA transfer complete callback */ + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt; + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set the DMA half transfer complete callback */ + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt; + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set the DMA error callback */ + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ; + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ + ARM GAS /tmp/cc5LZY9S.s page 13 + + + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* start (in case of SW start): */ + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Clear regular group conversion flag and overrun flag */ + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* (To ensure of no unknown state from potential previous ADC operations) */ + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Enable ADC overrun interrupt */ + 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if (hadc->Init.DMAContinuousRequests != DISABLE) + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Enable the selected ADC DMA request after last transfer */ + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR |= ADC_CCR_DDS; + 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** else + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Disable the selected ADC EOC rising on each regular channel conversion */ + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR &= ~ADC_CCR_DDS; + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Enable the DMA Stream */ + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length); + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* if no external trigger present enable software conversion of regular channels */ + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Enable the selected ADC software conversion for regular group */ + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** else + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Update ADC state machine to error */ + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set ADC error code to ADC IP internal error */ + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Return function status */ + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** return HAL_OK; + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * the configuration information for the specified ADC. + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @retval HAL status + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** */ + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check the parameters */ + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Process locked */ + ARM GAS /tmp/cc5LZY9S.s page 14 + + + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_LOCK(hadc); + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Stop potential conversion on going, on regular and injected groups */ + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Disable ADC peripheral */ + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_ADC_DISABLE(hadc); + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check if ADC is effectively disabled */ + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Disable the selected ADC DMA mode for multimode */ + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR &= ~ADC_CCR_DDS; + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Disable the DMA channel (in case of DMA in circular mode or stop while */ + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* DMA transfer is on going) */ + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Disable ADC overrun interrupt */ + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set ADC state */ + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC_STATE_CLR_SET(hadc->State, + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_STATE_READY); + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Process unlocked */ + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_UNLOCK(hadc); + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Return function status */ + 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** return tmp_hal_status; + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * data in the selected multi mode. + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * the configuration information for the specified ADC. + 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @retval The converted data value. + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** */ + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Prevent unused argument(s) compilation warning */ + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** UNUSED(hadc); + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Return the multi mode conversion value */ + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** return ADC->CDR; + 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @brief Injected conversion complete callback in non blocking mode + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * the configuration information for the specified ADC. + 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @retval None + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** */ + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Prevent unused argument(s) compilation warning */ + ARM GAS /tmp/cc5LZY9S.s page 15 + + + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** UNUSED(hadc); + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** */ + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @brief Configures for the selected ADC injected channel its corresponding + 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * rank in the sequencer and its sample time. + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * the configuration information for the specified ADC. + 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param sConfigInjected ADC configuration structure for injected channel. + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @retval None + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** */ + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** #ifdef USE_FULL_ASSERT + 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** uint32_t tmp = 0; + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** #endif /* USE_FULL_ASSERT */ + 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check the parameters */ + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv)); + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion)); + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** #ifdef USE_FULL_ASSERT + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp = ADC_GET_RESOLUTION(hadc); + 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset)); + 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** #endif /* USE_FULL_ASSERT */ + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Process locked */ + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_LOCK(hadc); + 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9) + 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Clear the old sample time */ + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel); + 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set the new sample time */ + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->Inje + 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** else /* ADC_Channel include in ADC_Channel_[0..9] */ + 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Clear the old sample time */ + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel); + 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + ARM GAS /tmp/cc5LZY9S.s page 16 + + + 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set the new sample time */ + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->Inje + 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /*---------------------------- ADCx JSQR Configuration -----------------*/ + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JSQR &= ~(ADC_JSQR_JL); + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion); + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Rank configuration */ + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Clear the old SQx bits for the selected rank */ + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->I + 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set the SQx bits for the selected rank */ + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank, + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Enable external trigger if trigger selection is different of software */ + 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* start. */ + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Note: This configuration keeps the hardware feature of parameter */ + 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* software start. */ + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Select external trigger to start conversion */ + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv; + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Select external trigger polarity */ + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge; + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** else + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Reset the external trigger */ + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); + 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if (sConfigInjected->AutoInjectedConv != DISABLE) + 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Enable the selected ADC automatic injected group conversion */ + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR1 |= ADC_CR1_JAUTO; + 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** else + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Disable the selected ADC automatic injected group conversion */ + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO); + 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE) + 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Enable the selected ADC injected discontinuous mode */ + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR1 |= ADC_CR1_JDISCEN; + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** else + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Disable the selected ADC injected discontinuous mode */ + ARM GAS /tmp/cc5LZY9S.s page 17 + + + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN); + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** switch(sConfigInjected->InjectedRank) + 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** case 1: + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set injected channel 1 offset */ + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1); + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset; + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** case 2: + 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set injected channel 2 offset */ + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2); + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset; + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** case 3: + 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set injected channel 3 offset */ + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3); + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset; + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** default: + 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set injected channel 4 offset */ + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4); + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset; + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* if ADC1 Channel_18 is selected enable VBAT Channel */ + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)) + 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Enable the VBAT channel*/ + 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR |= ADC_CCR_VBATE; + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VRE + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || + 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Enable the TSVREFE channel*/ + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR |= ADC_CCR_TSVREFE; + 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Process unlocked */ + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_UNLOCK(hadc); + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Return function status */ + 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** return HAL_OK; + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @brief Configures the ADC multi-mode + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param hadc pointer to a ADC_HandleTypeDef structure that contains + 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * the configuration information for the specified ADC. + 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param multimode pointer to an ADC_MultiModeTypeDef structure that contains + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * the configuration information for multimode. + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @retval HAL status + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** */ + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* m + ARM GAS /tmp/cc5LZY9S.s page 18 + + + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check the parameters */ + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_MODE(multimode->Mode)); + 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode)); + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Process locked */ + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_LOCK(hadc); + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set ADC mode */ + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR &= ~(ADC_CCR_MULTI); + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR |= multimode->Mode; + 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set the ADC DMA access mode */ + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR &= ~(ADC_CCR_DMA); + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR |= multimode->DMAAccessMode; + 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set delay between two sampling phases */ + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR &= ~(ADC_CCR_DELAY); + 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR |= multimode->TwoSamplingDelay; + 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Process unlocked */ + 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_UNLOCK(hadc); + 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Return function status */ + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** return HAL_OK; + 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** + 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @} + 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** */ + 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @brief DMA transfer complete callback. + 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * the configuration information for the specified DMA module. + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @retval None + 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** */ + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Retrieve ADC handle corresponding to current DMA handle */ + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Update state machine on conversion status if not in error state */ + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) + 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Update ADC state machine */ + 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Determine whether any further conversion upcoming on group regular */ + 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* by external trigger, continuous mode or scan sequence on going. */ + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Note: On STM32F7, there is no independent flag of end of sequence. */ + 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* The test of scan sequence on going is done either with scan */ + 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* sequence disabled or with end of conversion flag set to */ + 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* of end of sequence. */ + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (hadc->Init.ContinuousConvMode == DISABLE) && + ARM GAS /tmp/cc5LZY9S.s page 19 + + +1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || +1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Disable ADC end of single conversion interrupt on group regular */ +1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Note: Overrun interrupt was enabled with EOC interrupt in */ +1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* by overrun IRQ process below. */ +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** +1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set ADC state */ +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** +1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) +1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { +1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** SET_BIT(hadc->State, HAL_ADC_STATE_READY); +1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } +1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } +1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** +1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Conversion complete callback */ +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_ConvCpltCallback(hadc); +1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } +1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** else +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { +1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Call DMA error callback */ +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->DMA_Handle->XferErrorCallback(hdma); +1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } +1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** +1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @brief DMA half transfer complete callback. +1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * the configuration information for the specified DMA module. +1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @retval None +1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** */ +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) +1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { +1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; +1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Conversion complete callback */ +1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_ConvHalfCpltCallback(hadc); +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** +1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /** +1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @brief DMA error callback +1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * the configuration information for the specified DMA module. +1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** * @retval None +1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** */ +1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma) +1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 28 .loc 1 1049 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 .loc 1 1049 1 is_stmt 0 view .LVU1 + 33 0000 08B5 push {r3, lr} + 34 .LCFI0: + 35 .cfi_def_cfa_offset 8 + ARM GAS /tmp/cc5LZY9S.s page 20 + + + 36 .cfi_offset 3, -8 + 37 .cfi_offset 14, -4 +1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + 38 .loc 1 1050 5 is_stmt 1 view .LVU2 + 39 .loc 1 1050 24 is_stmt 0 view .LVU3 + 40 0002 806B ldr r0, [r0, #56] + 41 .LVL1: +1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->State= HAL_ADC_STATE_ERROR_DMA; + 42 .loc 1 1051 5 is_stmt 1 view .LVU4 + 43 .loc 1 1051 16 is_stmt 0 view .LVU5 + 44 0004 4023 movs r3, #64 + 45 0006 0364 str r3, [r0, #64] +1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Set ADC error code to DMA error */ +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->ErrorCode |= HAL_ADC_ERROR_DMA; + 46 .loc 1 1053 5 is_stmt 1 view .LVU6 + 47 .loc 1 1053 9 is_stmt 0 view .LVU7 + 48 0008 436C ldr r3, [r0, #68] + 49 .loc 1 1053 21 view .LVU8 + 50 000a 43F00403 orr r3, r3, #4 + 51 000e 4364 str r3, [r0, #68] +1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_ErrorCallback(hadc); + 52 .loc 1 1054 5 is_stmt 1 view .LVU9 + 53 0010 FFF7FEFF bl HAL_ADC_ErrorCallback + 54 .LVL2: +1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 55 .loc 1 1055 1 is_stmt 0 view .LVU10 + 56 0014 08BD pop {r3, pc} + 57 .cfi_endproc + 58 .LFE155: + 60 .section .text.ADC_MultiModeDMAHalfConvCplt,"ax",%progbits + 61 .align 1 + 62 .syntax unified + 63 .thumb + 64 .thumb_func + 66 ADC_MultiModeDMAHalfConvCplt: + 67 .LVL3: + 68 .LFB154: +1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + 69 .loc 1 1036 1 is_stmt 1 view -0 + 70 .cfi_startproc + 71 @ args = 0, pretend = 0, frame = 0 + 72 @ frame_needed = 0, uses_anonymous_args = 0 +1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + 73 .loc 1 1036 1 is_stmt 0 view .LVU12 + 74 0000 08B5 push {r3, lr} + 75 .LCFI1: + 76 .cfi_def_cfa_offset 8 + 77 .cfi_offset 3, -8 + 78 .cfi_offset 14, -4 +1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Conversion complete callback */ + 79 .loc 1 1037 5 is_stmt 1 view .LVU13 + 80 .LVL4: +1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 81 .loc 1 1039 5 view .LVU14 + 82 0002 806B ldr r0, [r0, #56] + 83 .LVL5: +1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + ARM GAS /tmp/cc5LZY9S.s page 21 + + + 84 .loc 1 1039 5 is_stmt 0 view .LVU15 + 85 0004 FFF7FEFF bl HAL_ADC_ConvHalfCpltCallback + 86 .LVL6: +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 87 .loc 1 1040 1 view .LVU16 + 88 0008 08BD pop {r3, pc} + 89 .cfi_endproc + 90 .LFE154: + 92 .section .text.ADC_MultiModeDMAConvCplt,"ax",%progbits + 93 .align 1 + 94 .syntax unified + 95 .thumb + 96 .thumb_func + 98 ADC_MultiModeDMAConvCplt: + 99 .LVL7: + 100 .LFB153: + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Retrieve ADC handle corresponding to current DMA handle */ + 101 .loc 1 983 1 is_stmt 1 view -0 + 102 .cfi_startproc + 103 @ args = 0, pretend = 0, frame = 0 + 104 @ frame_needed = 0, uses_anonymous_args = 0 + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Retrieve ADC handle corresponding to current DMA handle */ + 105 .loc 1 983 1 is_stmt 0 view .LVU18 + 106 0000 08B5 push {r3, lr} + 107 .LCFI2: + 108 .cfi_def_cfa_offset 8 + 109 .cfi_offset 3, -8 + 110 .cfi_offset 14, -4 + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 111 .loc 1 985 3 is_stmt 1 view .LVU19 + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 112 .loc 1 985 22 is_stmt 0 view .LVU20 + 113 0002 836B ldr r3, [r0, #56] + 114 .LVL8: + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 115 .loc 1 988 3 is_stmt 1 view .LVU21 + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 116 .loc 1 988 7 is_stmt 0 view .LVU22 + 117 0004 1A6C ldr r2, [r3, #64] + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 118 .loc 1 988 6 view .LVU23 + 119 0006 12F0500F tst r2, #80 + 120 000a 26D1 bne .L6 + 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 121 .loc 1 991 5 is_stmt 1 view .LVU24 + 122 000c 1A6C ldr r2, [r3, #64] + 123 000e 42F40072 orr r2, r2, #512 + 124 0012 1A64 str r2, [r3, #64] + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (hadc->Init.ContinuousConvMode == DISABLE) && + 125 .loc 1 999 5 view .LVU25 + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (hadc->Init.ContinuousConvMode == DISABLE) && + 126 .loc 1 999 8 is_stmt 0 view .LVU26 + 127 0014 1A68 ldr r2, [r3] + 128 0016 9168 ldr r1, [r2, #8] + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (hadc->Init.ContinuousConvMode == DISABLE) && + 129 .loc 1 999 7 view .LVU27 + 130 0018 11F0405F tst r1, #805306368 + ARM GAS /tmp/cc5LZY9S.s page 22 + + + 131 001c 19D1 bne .L7 +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + 132 .loc 1 1000 19 view .LVU28 + 133 001e 9969 ldr r1, [r3, #24] + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (hadc->Init.ContinuousConvMode == DISABLE) && + 134 .loc 1 999 62 discriminator 1 view .LVU29 + 135 0020 B9B9 cbnz r1, .L7 +1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + 136 .loc 1 1001 9 view .LVU30 + 137 0022 D16A ldr r1, [r2, #44] +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + 138 .loc 1 1000 62 view .LVU31 + 139 0024 11F4700F tst r1, #15728640 + 140 0028 03D0 beq .L8 +1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 141 .loc 1 1002 9 view .LVU32 + 142 002a 9168 ldr r1, [r2, #8] +1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + 143 .loc 1 1001 58 view .LVU33 + 144 002c 11F4806F tst r1, #1024 + 145 0030 0FD1 bne .L7 + 146 .L8: +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 147 .loc 1 1008 7 is_stmt 1 view .LVU34 + 148 0032 5168 ldr r1, [r2, #4] + 149 0034 21F02001 bic r1, r1, #32 + 150 0038 5160 str r1, [r2, #4] +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 151 .loc 1 1011 7 view .LVU35 + 152 003a 1A6C ldr r2, [r3, #64] + 153 003c 22F48072 bic r2, r2, #256 + 154 0040 1A64 str r2, [r3, #64] +1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 155 .loc 1 1013 7 view .LVU36 +1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 156 .loc 1 1013 11 is_stmt 0 view .LVU37 + 157 0042 1A6C ldr r2, [r3, #64] +1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 158 .loc 1 1013 10 view .LVU38 + 159 0044 12F4805F tst r2, #4096 + 160 0048 03D1 bne .L7 +1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 161 .loc 1 1015 9 is_stmt 1 view .LVU39 + 162 004a 1A6C ldr r2, [r3, #64] + 163 004c 42F00102 orr r2, r2, #1 + 164 0050 1A64 str r2, [r3, #64] + 165 .L7: +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 166 .loc 1 1020 5 view .LVU40 + 167 0052 1846 mov r0, r3 + 168 .LVL9: +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 169 .loc 1 1020 5 is_stmt 0 view .LVU41 + 170 0054 FFF7FEFF bl HAL_ADC_ConvCpltCallback + 171 .LVL10: + 172 .L5: +1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + ARM GAS /tmp/cc5LZY9S.s page 23 + + + 173 .loc 1 1027 1 view .LVU42 + 174 0058 08BD pop {r3, pc} + 175 .LVL11: + 176 .L6: +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 177 .loc 1 1025 5 is_stmt 1 view .LVU43 +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 178 .loc 1 1025 9 is_stmt 0 view .LVU44 + 179 005a 9B6B ldr r3, [r3, #56] + 180 .LVL12: +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 181 .loc 1 1025 21 view .LVU45 + 182 005c DB6C ldr r3, [r3, #76] +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 183 .loc 1 1025 5 view .LVU46 + 184 005e 9847 blx r3 + 185 .LVL13: +1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 186 .loc 1 1027 1 view .LVU47 + 187 0060 FAE7 b .L5 + 188 .cfi_endproc + 189 .LFE153: + 191 .section .text.HAL_ADCEx_InjectedStart,"ax",%progbits + 192 .align 1 + 193 .global HAL_ADCEx_InjectedStart + 194 .syntax unified + 195 .thumb + 196 .thumb_func + 198 HAL_ADCEx_InjectedStart: + 199 .LVL14: + 200 .LFB141: + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __IO uint32_t counter = 0; + 201 .loc 1 148 1 is_stmt 1 view -0 + 202 .cfi_startproc + 203 @ args = 0, pretend = 0, frame = 8 + 204 @ frame_needed = 0, uses_anonymous_args = 0 + 205 @ link register save eliminated. + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __IO uint32_t counter = 0; + 206 .loc 1 148 1 is_stmt 0 view .LVU49 + 207 0000 82B0 sub sp, sp, #8 + 208 .LCFI3: + 209 .cfi_def_cfa_offset 8 + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** uint32_t tmp1 = 0, tmp2 = 0; + 210 .loc 1 149 3 is_stmt 1 view .LVU50 + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** uint32_t tmp1 = 0, tmp2 = 0; + 211 .loc 1 149 17 is_stmt 0 view .LVU51 + 212 0002 0023 movs r3, #0 + 213 0004 0193 str r3, [sp, #4] + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 214 .loc 1 150 3 is_stmt 1 view .LVU52 + 215 .LVL15: + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 216 .loc 1 153 3 view .LVU53 + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 217 .loc 1 153 3 view .LVU54 + 218 0006 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 219 000a 012B cmp r3, #1 + ARM GAS /tmp/cc5LZY9S.s page 24 + + + 220 000c 65D0 beq .L19 + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 221 .loc 1 153 3 discriminator 2 view .LVU55 + 222 000e 0123 movs r3, #1 + 223 0010 80F83C30 strb r3, [r0, #60] + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 224 .loc 1 153 3 discriminator 2 view .LVU56 + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 225 .loc 1 159 3 view .LVU57 + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 226 .loc 1 159 11 is_stmt 0 view .LVU58 + 227 0014 0368 ldr r3, [r0] + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 228 .loc 1 159 21 view .LVU59 + 229 0016 9A68 ldr r2, [r3, #8] + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 230 .loc 1 159 5 view .LVU60 + 231 0018 12F0010F tst r2, #1 + 232 001c 13D1 bne .L13 + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 233 .loc 1 162 5 is_stmt 1 view .LVU61 + 234 001e 9A68 ldr r2, [r3, #8] + 235 0020 42F00102 orr r2, r2, #1 + 236 0024 9A60 str r2, [r3, #8] + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** while(counter != 0) + 237 .loc 1 166 5 view .LVU62 + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** while(counter != 0) + 238 .loc 1 166 53 is_stmt 0 view .LVU63 + 239 0026 304B ldr r3, .L25 + 240 0028 1B68 ldr r3, [r3] + 241 002a 304A ldr r2, .L25+4 + 242 002c A2FB0323 umull r2, r3, r2, r3 + 243 0030 9B0C lsrs r3, r3, #18 + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** while(counter != 0) + 244 .loc 1 166 34 view .LVU64 + 245 0032 03EB4303 add r3, r3, r3, lsl #1 + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** while(counter != 0) + 246 .loc 1 166 13 view .LVU65 + 247 0036 0193 str r3, [sp, #4] + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 248 .loc 1 167 5 is_stmt 1 view .LVU66 + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 249 .loc 1 167 10 is_stmt 0 view .LVU67 + 250 0038 02E0 b .L14 + 251 .L15: + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 252 .loc 1 169 7 is_stmt 1 view .LVU68 + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 253 .loc 1 169 14 is_stmt 0 view .LVU69 + 254 003a 019B ldr r3, [sp, #4] + 255 003c 013B subs r3, r3, #1 + 256 003e 0193 str r3, [sp, #4] + 257 .L14: + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 258 .loc 1 167 19 is_stmt 1 view .LVU70 + 259 0040 019B ldr r3, [sp, #4] + 260 0042 002B cmp r3, #0 + ARM GAS /tmp/cc5LZY9S.s page 25 + + + 261 0044 F9D1 bne .L15 + 262 .L13: + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 263 .loc 1 174 3 view .LVU71 + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 264 .loc 1 174 6 is_stmt 0 view .LVU72 + 265 0046 0268 ldr r2, [r0] + 266 0048 9368 ldr r3, [r2, #8] + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 267 .loc 1 174 5 view .LVU73 + 268 004a 13F0010F tst r3, #1 + 269 004e 39D0 beq .L16 + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + 270 .loc 1 179 5 is_stmt 1 view .LVU74 + 271 0050 016C ldr r1, [r0, #64] + 272 0052 274B ldr r3, .L25+8 + 273 0054 0B40 ands r3, r3, r1 + 274 0056 43F48053 orr r3, r3, #4096 + 275 005a 0364 str r3, [r0, #64] + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 276 .loc 1 187 5 view .LVU75 + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 277 .loc 1 187 9 is_stmt 0 view .LVU76 + 278 005c 036C ldr r3, [r0, #64] + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 279 .loc 1 187 8 view .LVU77 + 280 005e 13F4807F tst r3, #256 + 281 0062 01D1 bne .L17 + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 282 .loc 1 190 7 is_stmt 1 view .LVU78 + 283 0064 0023 movs r3, #0 + 284 0066 4364 str r3, [r0, #68] + 285 .L17: + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 286 .loc 1 196 5 view .LVU79 + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 287 .loc 1 196 5 view .LVU80 + 288 0068 0023 movs r3, #0 + 289 006a 80F83C30 strb r3, [r0, #60] + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 290 .loc 1 196 5 view .LVU81 + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 291 .loc 1 200 5 view .LVU82 + 292 006e 6FF00403 mvn r3, #4 + 293 0072 1360 str r3, [r2] + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 294 .loc 1 203 5 view .LVU83 + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 295 .loc 1 203 8 is_stmt 0 view .LVU84 + 296 0074 1F4B ldr r3, .L25+12 + 297 0076 5B68 ldr r3, [r3, #4] + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 298 .loc 1 203 7 view .LVU85 + 299 0078 13F01F0F tst r3, #31 + 300 007c 0ED1 bne .L18 + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + 301 .loc 1 205 7 is_stmt 1 view .LVU86 + ARM GAS /tmp/cc5LZY9S.s page 26 + + + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + 302 .loc 1 205 14 is_stmt 0 view .LVU87 + 303 007e 0168 ldr r1, [r0] + 304 0080 8B68 ldr r3, [r1, #8] + 305 0082 03F44013 and r3, r3, #3145728 + 306 .LVL16: + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(tmp1 && tmp2) + 307 .loc 1 206 7 is_stmt 1 view .LVU88 + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(tmp1 && tmp2) + 308 .loc 1 206 14 is_stmt 0 view .LVU89 + 309 0086 4A68 ldr r2, [r1, #4] + 310 0088 02F48062 and r2, r2, #1024 + 311 .LVL17: + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 312 .loc 1 207 7 is_stmt 1 view .LVU90 + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 313 .loc 1 207 9 is_stmt 0 view .LVU91 + 314 008c 1343 orrs r3, r3, r2 + 315 .LVL18: + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 316 .loc 1 207 9 view .LVU92 + 317 008e 26D1 bne .L20 + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 318 .loc 1 210 9 is_stmt 1 view .LVU93 + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 319 .loc 1 210 23 is_stmt 0 view .LVU94 + 320 0090 8B68 ldr r3, [r1, #8] + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 321 .loc 1 210 29 view .LVU95 + 322 0092 43F48003 orr r3, r3, #4194304 + 323 0096 8B60 str r3, [r1, #8] + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 324 .loc 1 234 10 view .LVU96 + 325 0098 0020 movs r0, #0 + 326 .LVL19: + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 327 .loc 1 234 10 view .LVU97 + 328 009a 1CE0 b .L12 + 329 .LVL20: + 330 .L18: + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + 331 .loc 1 215 7 is_stmt 1 view .LVU98 + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + 332 .loc 1 215 14 is_stmt 0 view .LVU99 + 333 009c 0368 ldr r3, [r0] + 334 009e 9A68 ldr r2, [r3, #8] + 335 00a0 02F44012 and r2, r2, #3145728 + 336 .LVL21: + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if((hadc->Instance == ADC1) && tmp1 && tmp2) + 337 .loc 1 216 7 is_stmt 1 view .LVU100 + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if((hadc->Instance == ADC1) && tmp1 && tmp2) + 338 .loc 1 216 14 is_stmt 0 view .LVU101 + 339 00a4 5968 ldr r1, [r3, #4] + 340 00a6 01F48061 and r1, r1, #1024 + 341 .LVL22: + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 342 .loc 1 217 7 is_stmt 1 view .LVU102 + ARM GAS /tmp/cc5LZY9S.s page 27 + + + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 343 .loc 1 217 9 is_stmt 0 view .LVU103 + 344 00aa 1348 ldr r0, .L25+16 + 345 .LVL23: + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 346 .loc 1 217 9 view .LVU104 + 347 00ac 8342 cmp r3, r0 + 348 00ae 01D0 beq .L24 + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 349 .loc 1 234 10 view .LVU105 + 350 00b0 0020 movs r0, #0 + 351 00b2 10E0 b .L12 + 352 .L24: + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 353 .loc 1 217 43 discriminator 1 view .LVU106 + 354 00b4 0A43 orrs r2, r2, r1 + 355 .LVL24: + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 356 .loc 1 217 43 discriminator 1 view .LVU107 + 357 00b6 14D1 bne .L22 + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 358 .loc 1 220 9 is_stmt 1 view .LVU108 + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 359 .loc 1 220 23 is_stmt 0 view .LVU109 + 360 00b8 9A68 ldr r2, [r3, #8] + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 361 .loc 1 220 29 view .LVU110 + 362 00ba 42F48002 orr r2, r2, #4194304 + 363 00be 9A60 str r2, [r3, #8] + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 364 .loc 1 234 10 view .LVU111 + 365 00c0 0020 movs r0, #0 + 366 00c2 08E0 b .L12 + 367 .LVL25: + 368 .L16: + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 369 .loc 1 227 5 is_stmt 1 view .LVU112 + 370 00c4 036C ldr r3, [r0, #64] + 371 00c6 43F01003 orr r3, r3, #16 + 372 00ca 0364 str r3, [r0, #64] + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 373 .loc 1 230 5 view .LVU113 + 374 00cc 436C ldr r3, [r0, #68] + 375 00ce 43F00103 orr r3, r3, #1 + 376 00d2 4364 str r3, [r0, #68] + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 377 .loc 1 234 10 is_stmt 0 view .LVU114 + 378 00d4 0020 movs r0, #0 + 379 .LVL26: + 380 .L12: + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 381 .loc 1 235 1 view .LVU115 + 382 00d6 02B0 add sp, sp, #8 + 383 .LCFI4: + 384 .cfi_remember_state + 385 .cfi_def_cfa_offset 0 + 386 @ sp needed + ARM GAS /tmp/cc5LZY9S.s page 28 + + + 387 00d8 7047 bx lr + 388 .LVL27: + 389 .L19: + 390 .LCFI5: + 391 .cfi_restore_state + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 392 .loc 1 153 3 discriminator 1 view .LVU116 + 393 00da 0220 movs r0, #2 + 394 .LVL28: + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 395 .loc 1 153 3 discriminator 1 view .LVU117 + 396 00dc FBE7 b .L12 + 397 .LVL29: + 398 .L20: + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 399 .loc 1 234 10 view .LVU118 + 400 00de 0020 movs r0, #0 + 401 .LVL30: + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 402 .loc 1 234 10 view .LVU119 + 403 00e0 F9E7 b .L12 + 404 .LVL31: + 405 .L22: + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 406 .loc 1 234 10 view .LVU120 + 407 00e2 0020 movs r0, #0 + 408 00e4 F7E7 b .L12 + 409 .L26: + 410 00e6 00BF .align 2 + 411 .L25: + 412 00e8 00000000 .word SystemCoreClock + 413 00ec 83DE1B43 .word 1125899907 + 414 00f0 FECFFFFF .word -12290 + 415 00f4 00230140 .word 1073816320 + 416 00f8 00200140 .word 1073815552 + 417 .cfi_endproc + 418 .LFE141: + 420 .section .text.HAL_ADCEx_InjectedStart_IT,"ax",%progbits + 421 .align 1 + 422 .global HAL_ADCEx_InjectedStart_IT + 423 .syntax unified + 424 .thumb + 425 .thumb_func + 427 HAL_ADCEx_InjectedStart_IT: + 428 .LVL32: + 429 .LFB142: + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __IO uint32_t counter = 0; + 430 .loc 1 245 1 is_stmt 1 view -0 + 431 .cfi_startproc + 432 @ args = 0, pretend = 0, frame = 8 + 433 @ frame_needed = 0, uses_anonymous_args = 0 + 434 @ link register save eliminated. + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __IO uint32_t counter = 0; + 435 .loc 1 245 1 is_stmt 0 view .LVU122 + 436 0000 82B0 sub sp, sp, #8 + 437 .LCFI6: + 438 .cfi_def_cfa_offset 8 + ARM GAS /tmp/cc5LZY9S.s page 29 + + + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** uint32_t tmp1 = 0, tmp2 = 0; + 439 .loc 1 246 3 is_stmt 1 view .LVU123 + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** uint32_t tmp1 = 0, tmp2 = 0; + 440 .loc 1 246 17 is_stmt 0 view .LVU124 + 441 0002 0023 movs r3, #0 + 442 0004 0193 str r3, [sp, #4] + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 443 .loc 1 247 3 is_stmt 1 view .LVU125 + 444 .LVL33: + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 445 .loc 1 250 3 view .LVU126 + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 446 .loc 1 250 3 view .LVU127 + 447 0006 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 448 000a 012B cmp r3, #1 + 449 000c 6AD0 beq .L35 + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 450 .loc 1 250 3 discriminator 2 view .LVU128 + 451 000e 0123 movs r3, #1 + 452 0010 80F83C30 strb r3, [r0, #60] + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 453 .loc 1 250 3 discriminator 2 view .LVU129 + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 454 .loc 1 256 3 view .LVU130 + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 455 .loc 1 256 11 is_stmt 0 view .LVU131 + 456 0014 0368 ldr r3, [r0] + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 457 .loc 1 256 21 view .LVU132 + 458 0016 9A68 ldr r2, [r3, #8] + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 459 .loc 1 256 5 view .LVU133 + 460 0018 12F0010F tst r2, #1 + 461 001c 13D1 bne .L29 + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 462 .loc 1 259 5 is_stmt 1 view .LVU134 + 463 001e 9A68 ldr r2, [r3, #8] + 464 0020 42F00102 orr r2, r2, #1 + 465 0024 9A60 str r2, [r3, #8] + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** while(counter != 0) + 466 .loc 1 263 5 view .LVU135 + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** while(counter != 0) + 467 .loc 1 263 53 is_stmt 0 view .LVU136 + 468 0026 324B ldr r3, .L41 + 469 0028 1B68 ldr r3, [r3] + 470 002a 324A ldr r2, .L41+4 + 471 002c A2FB0323 umull r2, r3, r2, r3 + 472 0030 9B0C lsrs r3, r3, #18 + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** while(counter != 0) + 473 .loc 1 263 34 view .LVU137 + 474 0032 03EB4303 add r3, r3, r3, lsl #1 + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** while(counter != 0) + 475 .loc 1 263 13 view .LVU138 + 476 0036 0193 str r3, [sp, #4] + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 477 .loc 1 264 5 is_stmt 1 view .LVU139 + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + ARM GAS /tmp/cc5LZY9S.s page 30 + + + 478 .loc 1 264 10 is_stmt 0 view .LVU140 + 479 0038 02E0 b .L30 + 480 .L31: + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 481 .loc 1 266 7 is_stmt 1 view .LVU141 + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 482 .loc 1 266 14 is_stmt 0 view .LVU142 + 483 003a 019B ldr r3, [sp, #4] + 484 003c 013B subs r3, r3, #1 + 485 003e 0193 str r3, [sp, #4] + 486 .L30: + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 487 .loc 1 264 19 is_stmt 1 view .LVU143 + 488 0040 019B ldr r3, [sp, #4] + 489 0042 002B cmp r3, #0 + 490 0044 F9D1 bne .L31 + 491 .L29: + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 492 .loc 1 271 3 view .LVU144 + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 493 .loc 1 271 6 is_stmt 0 view .LVU145 + 494 0046 0268 ldr r2, [r0] + 495 0048 9368 ldr r3, [r2, #8] + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 496 .loc 1 271 5 view .LVU146 + 497 004a 13F0010F tst r3, #1 + 498 004e 3ED0 beq .L32 + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + 499 .loc 1 276 5 is_stmt 1 view .LVU147 + 500 0050 016C ldr r1, [r0, #64] + 501 0052 294B ldr r3, .L41+8 + 502 0054 0B40 ands r3, r3, r1 + 503 0056 43F48053 orr r3, r3, #4096 + 504 005a 0364 str r3, [r0, #64] + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 505 .loc 1 284 5 view .LVU148 + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 506 .loc 1 284 9 is_stmt 0 view .LVU149 + 507 005c 036C ldr r3, [r0, #64] + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 508 .loc 1 284 8 view .LVU150 + 509 005e 13F4807F tst r3, #256 + 510 0062 01D1 bne .L33 + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 511 .loc 1 287 7 is_stmt 1 view .LVU151 + 512 0064 0023 movs r3, #0 + 513 0066 4364 str r3, [r0, #68] + 514 .L33: + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 515 .loc 1 293 5 view .LVU152 + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 516 .loc 1 293 5 view .LVU153 + 517 0068 0023 movs r3, #0 + 518 006a 80F83C30 strb r3, [r0, #60] + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 519 .loc 1 293 5 view .LVU154 + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + ARM GAS /tmp/cc5LZY9S.s page 31 + + + 520 .loc 1 297 5 view .LVU155 + 521 006e 6FF00403 mvn r3, #4 + 522 0072 1360 str r3, [r2] + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 523 .loc 1 300 5 view .LVU156 + 524 0074 0268 ldr r2, [r0] + 525 0076 5368 ldr r3, [r2, #4] + 526 0078 43F08003 orr r3, r3, #128 + 527 007c 5360 str r3, [r2, #4] + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 528 .loc 1 303 5 view .LVU157 + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 529 .loc 1 303 8 is_stmt 0 view .LVU158 + 530 007e 1F4B ldr r3, .L41+12 + 531 0080 5B68 ldr r3, [r3, #4] + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 532 .loc 1 303 7 view .LVU159 + 533 0082 13F01F0F tst r3, #31 + 534 0086 0ED1 bne .L34 + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + 535 .loc 1 305 7 is_stmt 1 view .LVU160 + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + 536 .loc 1 305 14 is_stmt 0 view .LVU161 + 537 0088 0168 ldr r1, [r0] + 538 008a 8B68 ldr r3, [r1, #8] + 539 008c 03F44013 and r3, r3, #3145728 + 540 .LVL34: + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(tmp1 && tmp2) + 541 .loc 1 306 7 is_stmt 1 view .LVU162 + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if(tmp1 && tmp2) + 542 .loc 1 306 14 is_stmt 0 view .LVU163 + 543 0090 4A68 ldr r2, [r1, #4] + 544 0092 02F48062 and r2, r2, #1024 + 545 .LVL35: + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 546 .loc 1 307 7 is_stmt 1 view .LVU164 + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 547 .loc 1 307 9 is_stmt 0 view .LVU165 + 548 0096 1343 orrs r3, r3, r2 + 549 .LVL36: + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 550 .loc 1 307 9 view .LVU166 + 551 0098 26D1 bne .L36 + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 552 .loc 1 310 9 is_stmt 1 view .LVU167 + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 553 .loc 1 310 23 is_stmt 0 view .LVU168 + 554 009a 8B68 ldr r3, [r1, #8] + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 555 .loc 1 310 29 view .LVU169 + 556 009c 43F48003 orr r3, r3, #4194304 + 557 00a0 8B60 str r3, [r1, #8] + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 558 .loc 1 334 10 view .LVU170 + 559 00a2 0020 movs r0, #0 + 560 .LVL37: + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + ARM GAS /tmp/cc5LZY9S.s page 32 + + + 561 .loc 1 334 10 view .LVU171 + 562 00a4 1CE0 b .L28 + 563 .LVL38: + 564 .L34: + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + 565 .loc 1 315 7 is_stmt 1 view .LVU172 + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + 566 .loc 1 315 14 is_stmt 0 view .LVU173 + 567 00a6 0368 ldr r3, [r0] + 568 00a8 9A68 ldr r2, [r3, #8] + 569 00aa 02F44012 and r2, r2, #3145728 + 570 .LVL39: + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if((hadc->Instance == ADC1) && tmp1 && tmp2) + 571 .loc 1 316 7 is_stmt 1 view .LVU174 + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** if((hadc->Instance == ADC1) && tmp1 && tmp2) + 572 .loc 1 316 14 is_stmt 0 view .LVU175 + 573 00ae 5968 ldr r1, [r3, #4] + 574 00b0 01F48061 and r1, r1, #1024 + 575 .LVL40: + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 576 .loc 1 317 7 is_stmt 1 view .LVU176 + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 577 .loc 1 317 9 is_stmt 0 view .LVU177 + 578 00b4 1248 ldr r0, .L41+16 + 579 .LVL41: + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 580 .loc 1 317 9 view .LVU178 + 581 00b6 8342 cmp r3, r0 + 582 00b8 01D0 beq .L40 + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 583 .loc 1 334 10 view .LVU179 + 584 00ba 0020 movs r0, #0 + 585 00bc 10E0 b .L28 + 586 .L40: + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 587 .loc 1 317 43 discriminator 1 view .LVU180 + 588 00be 0A43 orrs r2, r2, r1 + 589 .LVL42: + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 590 .loc 1 317 43 discriminator 1 view .LVU181 + 591 00c0 14D1 bne .L38 + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 592 .loc 1 320 9 is_stmt 1 view .LVU182 + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 593 .loc 1 320 23 is_stmt 0 view .LVU183 + 594 00c2 9A68 ldr r2, [r3, #8] + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 595 .loc 1 320 29 view .LVU184 + 596 00c4 42F48002 orr r2, r2, #4194304 + 597 00c8 9A60 str r2, [r3, #8] + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 598 .loc 1 334 10 view .LVU185 + 599 00ca 0020 movs r0, #0 + 600 00cc 08E0 b .L28 + 601 .LVL43: + 602 .L32: + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + ARM GAS /tmp/cc5LZY9S.s page 33 + + + 603 .loc 1 327 5 is_stmt 1 view .LVU186 + 604 00ce 036C ldr r3, [r0, #64] + 605 00d0 43F01003 orr r3, r3, #16 + 606 00d4 0364 str r3, [r0, #64] + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 607 .loc 1 330 5 view .LVU187 + 608 00d6 436C ldr r3, [r0, #68] + 609 00d8 43F00103 orr r3, r3, #1 + 610 00dc 4364 str r3, [r0, #68] + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 611 .loc 1 334 10 is_stmt 0 view .LVU188 + 612 00de 0020 movs r0, #0 + 613 .LVL44: + 614 .L28: + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 615 .loc 1 335 1 view .LVU189 + 616 00e0 02B0 add sp, sp, #8 + 617 .LCFI7: + 618 .cfi_remember_state + 619 .cfi_def_cfa_offset 0 + 620 @ sp needed + 621 00e2 7047 bx lr + 622 .LVL45: + 623 .L35: + 624 .LCFI8: + 625 .cfi_restore_state + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 626 .loc 1 250 3 discriminator 1 view .LVU190 + 627 00e4 0220 movs r0, #2 + 628 .LVL46: + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 629 .loc 1 250 3 discriminator 1 view .LVU191 + 630 00e6 FBE7 b .L28 + 631 .LVL47: + 632 .L36: + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 633 .loc 1 334 10 view .LVU192 + 634 00e8 0020 movs r0, #0 + 635 .LVL48: + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 636 .loc 1 334 10 view .LVU193 + 637 00ea F9E7 b .L28 + 638 .LVL49: + 639 .L38: + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 640 .loc 1 334 10 view .LVU194 + 641 00ec 0020 movs r0, #0 + 642 00ee F7E7 b .L28 + 643 .L42: + 644 .align 2 + 645 .L41: + 646 00f0 00000000 .word SystemCoreClock + 647 00f4 83DE1B43 .word 1125899907 + 648 00f8 FECFFFFF .word -12290 + 649 00fc 00230140 .word 1073816320 + 650 0100 00200140 .word 1073815552 + 651 .cfi_endproc + ARM GAS /tmp/cc5LZY9S.s page 34 + + + 652 .LFE142: + 654 .section .text.HAL_ADCEx_InjectedStop,"ax",%progbits + 655 .align 1 + 656 .global HAL_ADCEx_InjectedStop + 657 .syntax unified + 658 .thumb + 659 .thumb_func + 661 HAL_ADCEx_InjectedStop: + 662 .LVL50: + 663 .LFB143: + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 664 .loc 1 350 1 is_stmt 1 view -0 + 665 .cfi_startproc + 666 @ args = 0, pretend = 0, frame = 0 + 667 @ frame_needed = 0, uses_anonymous_args = 0 + 668 @ link register save eliminated. + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 669 .loc 1 350 1 is_stmt 0 view .LVU196 + 670 0000 0346 mov r3, r0 + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 671 .loc 1 351 3 is_stmt 1 view .LVU197 + 672 .LVL51: + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 673 .loc 1 354 3 view .LVU198 + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 674 .loc 1 357 3 view .LVU199 + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 675 .loc 1 357 3 view .LVU200 + 676 0002 90F83C20 ldrb r2, [r0, #60] @ zero_extendqisi2 + 677 0006 012A cmp r2, #1 + 678 0008 27D0 beq .L47 + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 679 .loc 1 357 3 discriminator 2 view .LVU201 + 680 000a 0122 movs r2, #1 + 681 000c 80F83C20 strb r2, [r0, #60] + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 682 .loc 1 357 3 discriminator 2 view .LVU202 + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + 683 .loc 1 365 3 view .LVU203 + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + 684 .loc 1 365 12 is_stmt 0 view .LVU204 + 685 0010 026C ldr r2, [r0, #64] + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + 686 .loc 1 365 5 view .LVU205 + 687 0012 12F4807F tst r2, #256 + 688 0016 15D1 bne .L45 + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 689 .loc 1 366 6 view .LVU206 + 690 0018 0268 ldr r2, [r0] + 691 001a 5168 ldr r1, [r2, #4] + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + 692 .loc 1 365 57 discriminator 1 view .LVU207 + 693 001c 11F4806F tst r1, #1024 + 694 0020 10D1 bne .L45 + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 695 .loc 1 370 5 is_stmt 1 view .LVU208 + 696 0022 9168 ldr r1, [r2, #8] + ARM GAS /tmp/cc5LZY9S.s page 35 + + + 697 0024 21F00101 bic r1, r1, #1 + 698 0028 9160 str r1, [r2, #8] + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 699 .loc 1 373 5 view .LVU209 + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 700 .loc 1 373 8 is_stmt 0 view .LVU210 + 701 002a 0268 ldr r2, [r0] + 702 002c 9268 ldr r2, [r2, #8] + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 703 .loc 1 373 7 view .LVU211 + 704 002e 12F0010F tst r2, #1 + 705 0032 10D1 bne .L48 + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + 706 .loc 1 376 7 is_stmt 1 view .LVU212 + 707 0034 016C ldr r1, [r0, #64] + 708 0036 0A4A ldr r2, .L49 + 709 0038 0A40 ands r2, r2, r1 + 710 003a 42F00102 orr r2, r2, #1 + 711 003e 0264 str r2, [r0, #64] + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 712 .loc 1 351 21 is_stmt 0 view .LVU213 + 713 0040 0020 movs r0, #0 + 714 .LVL52: + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 715 .loc 1 351 21 view .LVU214 + 716 0042 04E0 b .L46 + 717 .LVL53: + 718 .L45: + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 719 .loc 1 384 5 is_stmt 1 view .LVU215 + 720 0044 1A6C ldr r2, [r3, #64] + 721 0046 42F02002 orr r2, r2, #32 + 722 004a 1A64 str r2, [r3, #64] + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 723 .loc 1 386 5 view .LVU216 + 724 .LVL54: + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 725 .loc 1 386 20 is_stmt 0 view .LVU217 + 726 004c 0120 movs r0, #1 + 727 .LVL55: + 728 .L46: + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 729 .loc 1 390 3 is_stmt 1 view .LVU218 + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 730 .loc 1 390 3 view .LVU219 + 731 004e 0022 movs r2, #0 + 732 0050 83F83C20 strb r2, [r3, #60] + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 733 .loc 1 390 3 view .LVU220 + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 734 .loc 1 393 3 view .LVU221 + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 735 .loc 1 393 10 is_stmt 0 view .LVU222 + 736 0054 7047 bx lr + 737 .LVL56: + 738 .L48: + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + ARM GAS /tmp/cc5LZY9S.s page 36 + + + 739 .loc 1 351 21 view .LVU223 + 740 0056 0020 movs r0, #0 + 741 .LVL57: + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 742 .loc 1 351 21 view .LVU224 + 743 0058 F9E7 b .L46 + 744 .LVL58: + 745 .L47: + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 746 .loc 1 357 3 discriminator 1 view .LVU225 + 747 005a 0220 movs r0, #2 + 748 .LVL59: + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 749 .loc 1 394 1 view .LVU226 + 750 005c 7047 bx lr + 751 .L50: + 752 005e 00BF .align 2 + 753 .L49: + 754 0060 FEEEFFFF .word -4354 + 755 .cfi_endproc + 756 .LFE143: + 758 .section .text.HAL_ADCEx_InjectedPollForConversion,"ax",%progbits + 759 .align 1 + 760 .global HAL_ADCEx_InjectedPollForConversion + 761 .syntax unified + 762 .thumb + 763 .thumb_func + 765 HAL_ADCEx_InjectedPollForConversion: + 766 .LVL60: + 767 .LFB144: + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** uint32_t tickstart = 0; + 768 .loc 1 404 1 is_stmt 1 view -0 + 769 .cfi_startproc + 770 @ args = 0, pretend = 0, frame = 0 + 771 @ frame_needed = 0, uses_anonymous_args = 0 + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** uint32_t tickstart = 0; + 772 .loc 1 404 1 is_stmt 0 view .LVU228 + 773 0000 70B5 push {r4, r5, r6, lr} + 774 .LCFI9: + 775 .cfi_def_cfa_offset 16 + 776 .cfi_offset 4, -16 + 777 .cfi_offset 5, -12 + 778 .cfi_offset 6, -8 + 779 .cfi_offset 14, -4 + 780 0002 0446 mov r4, r0 + 781 0004 0D46 mov r5, r1 + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 782 .loc 1 405 3 is_stmt 1 view .LVU229 + 783 .LVL61: + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 784 .loc 1 408 3 view .LVU230 + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 785 .loc 1 408 15 is_stmt 0 view .LVU231 + 786 0006 FFF7FEFF bl HAL_GetTick + 787 .LVL62: + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 788 .loc 1 408 15 view .LVU232 + ARM GAS /tmp/cc5LZY9S.s page 37 + + + 789 000a 0646 mov r6, r0 + 790 .LVL63: + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 791 .loc 1 411 3 is_stmt 1 view .LVU233 + 792 .L53: + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 793 .loc 1 411 9 view .LVU234 + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 794 .loc 1 411 11 is_stmt 0 view .LVU235 + 795 000c 2368 ldr r3, [r4] + 796 000e 1A68 ldr r2, [r3] + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 797 .loc 1 411 9 view .LVU236 + 798 0010 12F0040F tst r2, #4 + 799 0014 15D1 bne .L66 + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 800 .loc 1 414 5 is_stmt 1 view .LVU237 + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 801 .loc 1 414 7 is_stmt 0 view .LVU238 + 802 0016 B5F1FF3F cmp r5, #-1 + 803 001a F7D0 beq .L53 + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 804 .loc 1 416 7 is_stmt 1 view .LVU239 + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 805 .loc 1 416 9 is_stmt 0 view .LVU240 + 806 001c 5DB9 cbnz r5, .L67 + 807 .L54: + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 808 .loc 1 419 9 is_stmt 1 view .LVU241 + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 809 .loc 1 419 14 is_stmt 0 view .LVU242 + 810 001e 2368 ldr r3, [r4] + 811 0020 1B68 ldr r3, [r3] + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 812 .loc 1 419 11 view .LVU243 + 813 0022 13F0040F tst r3, #4 + 814 0026 F1D1 bne .L53 + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Process unlocked */ + 815 .loc 1 421 11 is_stmt 1 view .LVU244 + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Process unlocked */ + 816 .loc 1 421 22 is_stmt 0 view .LVU245 + 817 0028 0423 movs r3, #4 + 818 002a 2364 str r3, [r4, #64] + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** return HAL_TIMEOUT; + 819 .loc 1 423 11 is_stmt 1 view .LVU246 + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** return HAL_TIMEOUT; + 820 .loc 1 423 11 view .LVU247 + 821 002c 0023 movs r3, #0 + 822 002e 84F83C30 strb r3, [r4, #60] + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** return HAL_TIMEOUT; + 823 .loc 1 423 11 view .LVU248 + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 824 .loc 1 424 11 view .LVU249 + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 825 .loc 1 424 18 is_stmt 0 view .LVU250 + 826 0032 0320 movs r0, #3 + 827 0034 32E0 b .L56 + ARM GAS /tmp/cc5LZY9S.s page 38 + + + 828 .L67: + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 829 .loc 1 416 28 discriminator 1 view .LVU251 + 830 0036 FFF7FEFF bl HAL_GetTick + 831 .LVL64: + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 832 .loc 1 416 42 discriminator 1 view .LVU252 + 833 003a 801B subs r0, r0, r6 + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 834 .loc 1 416 24 discriminator 1 view .LVU253 + 835 003c A842 cmp r0, r5 + 836 003e E5D9 bls .L53 + 837 0040 EDE7 b .L54 + 838 .L66: + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 839 .loc 1 431 3 is_stmt 1 view .LVU254 + 840 0042 6FF00C02 mvn r2, #12 + 841 0046 1A60 str r2, [r3] + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 842 .loc 1 434 3 view .LVU255 + 843 0048 236C ldr r3, [r4, #64] + 844 004a 43F40053 orr r3, r3, #8192 + 845 004e 2364 str r3, [r4, #64] + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + 846 .loc 1 442 3 view .LVU256 + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + 847 .loc 1 442 6 is_stmt 0 view .LVU257 + 848 0050 2368 ldr r3, [r4] + 849 0052 9A68 ldr r2, [r3, #8] + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + 850 .loc 1 442 5 view .LVU258 + 851 0054 12F4401F tst r2, #3145728 + 852 0058 1FD1 bne .L59 + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && + 853 .loc 1 443 7 view .LVU259 + 854 005a 9A6B ldr r2, [r3, #56] + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + 855 .loc 1 442 62 discriminator 1 view .LVU260 + 856 005c 12F4401F tst r2, #3145728 + 857 0060 03D0 beq .L58 + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + 858 .loc 1 444 7 view .LVU261 + 859 0062 9A68 ldr r2, [r3, #8] + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && + 860 .loc 1 443 58 view .LVU262 + 861 0064 12F4806F tst r2, #1024 + 862 0068 19D1 bne .L60 + 863 .L58: + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 864 .loc 1 445 7 view .LVU263 + 865 006a 5A68 ldr r2, [r3, #4] + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + 866 .loc 1 444 62 view .LVU264 + 867 006c 12F4806F tst r2, #1024 + 868 0070 17D1 bne .L61 + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) + 869 .loc 1 446 8 view .LVU265 + ARM GAS /tmp/cc5LZY9S.s page 39 + + + 870 0072 9B68 ldr r3, [r3, #8] + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 871 .loc 1 445 58 view .LVU266 + 872 0074 13F0405F tst r3, #805306368 + 873 0078 15D1 bne .L62 + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 874 .loc 1 447 18 view .LVU267 + 875 007a A369 ldr r3, [r4, #24] + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) + 876 .loc 1 446 50 view .LVU268 + 877 007c ABB9 cbnz r3, .L63 + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 878 .loc 1 450 5 is_stmt 1 view .LVU269 + 879 007e 236C ldr r3, [r4, #64] + 880 0080 23F48053 bic r3, r3, #4096 + 881 0084 2364 str r3, [r4, #64] + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 882 .loc 1 452 5 view .LVU270 + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 883 .loc 1 452 9 is_stmt 0 view .LVU271 + 884 0086 236C ldr r3, [r4, #64] + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 885 .loc 1 452 8 view .LVU272 + 886 0088 13F4807F tst r3, #256 + 887 008c 0FD1 bne .L64 + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 888 .loc 1 454 7 is_stmt 1 view .LVU273 + 889 008e 236C ldr r3, [r4, #64] + 890 0090 43F00103 orr r3, r3, #1 + 891 0094 2364 str r3, [r4, #64] + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 892 .loc 1 459 10 is_stmt 0 view .LVU274 + 893 0096 0020 movs r0, #0 + 894 0098 00E0 b .L56 + 895 .L59: + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 896 .loc 1 459 10 view .LVU275 + 897 009a 0020 movs r0, #0 + 898 .L56: + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 899 .loc 1 460 1 view .LVU276 + 900 009c 70BD pop {r4, r5, r6, pc} + 901 .LVL65: + 902 .L60: + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 903 .loc 1 459 10 view .LVU277 + 904 009e 0020 movs r0, #0 + 905 00a0 FCE7 b .L56 + 906 .L61: + 907 00a2 0020 movs r0, #0 + 908 00a4 FAE7 b .L56 + 909 .L62: + 910 00a6 0020 movs r0, #0 + 911 00a8 F8E7 b .L56 + 912 .L63: + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 913 .loc 1 459 10 view .LVU278 + ARM GAS /tmp/cc5LZY9S.s page 40 + + + 914 00aa 0020 movs r0, #0 + 915 00ac F6E7 b .L56 + 916 .L64: + 917 00ae 0020 movs r0, #0 + 918 00b0 F4E7 b .L56 + 919 .cfi_endproc + 920 .LFE144: + 922 .section .text.HAL_ADCEx_InjectedStop_IT,"ax",%progbits + 923 .align 1 + 924 .global HAL_ADCEx_InjectedStop_IT + 925 .syntax unified + 926 .thumb + 927 .thumb_func + 929 HAL_ADCEx_InjectedStop_IT: + 930 .LVL66: + 931 .LFB145: + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 932 .loc 1 475 1 is_stmt 1 view -0 + 933 .cfi_startproc + 934 @ args = 0, pretend = 0, frame = 0 + 935 @ frame_needed = 0, uses_anonymous_args = 0 + 936 @ link register save eliminated. + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 937 .loc 1 475 1 is_stmt 0 view .LVU280 + 938 0000 0346 mov r3, r0 + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 939 .loc 1 476 3 is_stmt 1 view .LVU281 + 940 .LVL67: + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 941 .loc 1 479 3 view .LVU282 + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 942 .loc 1 482 3 view .LVU283 + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 943 .loc 1 482 3 view .LVU284 + 944 0002 90F83C20 ldrb r2, [r0, #60] @ zero_extendqisi2 + 945 0006 012A cmp r2, #1 + 946 0008 2BD0 beq .L72 + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 947 .loc 1 482 3 discriminator 2 view .LVU285 + 948 000a 0122 movs r2, #1 + 949 000c 80F83C20 strb r2, [r0, #60] + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 950 .loc 1 482 3 discriminator 2 view .LVU286 + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + 951 .loc 1 490 3 view .LVU287 + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + 952 .loc 1 490 12 is_stmt 0 view .LVU288 + 953 0010 026C ldr r2, [r0, #64] + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + 954 .loc 1 490 5 view .LVU289 + 955 0012 12F4807F tst r2, #256 + 956 0016 19D1 bne .L70 + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 957 .loc 1 491 6 view .LVU290 + 958 0018 0268 ldr r2, [r0] + 959 001a 5168 ldr r1, [r2, #4] + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + ARM GAS /tmp/cc5LZY9S.s page 41 + + + 960 .loc 1 490 57 discriminator 1 view .LVU291 + 961 001c 11F4806F tst r1, #1024 + 962 0020 14D1 bne .L70 + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 963 .loc 1 495 5 is_stmt 1 view .LVU292 + 964 0022 9168 ldr r1, [r2, #8] + 965 0024 21F00101 bic r1, r1, #1 + 966 0028 9160 str r1, [r2, #8] + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 967 .loc 1 498 5 view .LVU293 + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 968 .loc 1 498 8 is_stmt 0 view .LVU294 + 969 002a 0268 ldr r2, [r0] + 970 002c 9168 ldr r1, [r2, #8] + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 971 .loc 1 498 7 view .LVU295 + 972 002e 11F0010F tst r1, #1 + 973 0032 14D1 bne .L73 + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 974 .loc 1 501 7 is_stmt 1 view .LVU296 + 975 0034 5168 ldr r1, [r2, #4] + 976 0036 21F08001 bic r1, r1, #128 + 977 003a 5160 str r1, [r2, #4] + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + 978 .loc 1 504 7 view .LVU297 + 979 003c 016C ldr r1, [r0, #64] + 980 003e 0A4A ldr r2, .L74 + 981 0040 0A40 ands r2, r2, r1 + 982 0042 42F00102 orr r2, r2, #1 + 983 0046 0264 str r2, [r0, #64] + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 984 .loc 1 476 21 is_stmt 0 view .LVU298 + 985 0048 0020 movs r0, #0 + 986 .LVL68: + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 987 .loc 1 476 21 view .LVU299 + 988 004a 04E0 b .L71 + 989 .LVL69: + 990 .L70: + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 991 .loc 1 512 5 is_stmt 1 view .LVU300 + 992 004c 1A6C ldr r2, [r3, #64] + 993 004e 42F02002 orr r2, r2, #32 + 994 0052 1A64 str r2, [r3, #64] + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 995 .loc 1 514 5 view .LVU301 + 996 .LVL70: + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 997 .loc 1 514 20 is_stmt 0 view .LVU302 + 998 0054 0120 movs r0, #1 + 999 .LVL71: + 1000 .L71: + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1001 .loc 1 518 3 is_stmt 1 view .LVU303 + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1002 .loc 1 518 3 view .LVU304 + 1003 0056 0022 movs r2, #0 + ARM GAS /tmp/cc5LZY9S.s page 42 + + + 1004 0058 83F83C20 strb r2, [r3, #60] + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1005 .loc 1 518 3 view .LVU305 + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1006 .loc 1 521 3 view .LVU306 + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1007 .loc 1 521 10 is_stmt 0 view .LVU307 + 1008 005c 7047 bx lr + 1009 .LVL72: + 1010 .L73: + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1011 .loc 1 476 21 view .LVU308 + 1012 005e 0020 movs r0, #0 + 1013 .LVL73: + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1014 .loc 1 476 21 view .LVU309 + 1015 0060 F9E7 b .L71 + 1016 .LVL74: + 1017 .L72: + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1018 .loc 1 482 3 discriminator 1 view .LVU310 + 1019 0062 0220 movs r0, #2 + 1020 .LVL75: + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1021 .loc 1 522 1 view .LVU311 + 1022 0064 7047 bx lr + 1023 .L75: + 1024 0066 00BF .align 2 + 1025 .L74: + 1026 0068 FEEEFFFF .word -4354 + 1027 .cfi_endproc + 1028 .LFE145: + 1030 .section .text.HAL_ADCEx_InjectedGetValue,"ax",%progbits + 1031 .align 1 + 1032 .global HAL_ADCEx_InjectedGetValue + 1033 .syntax unified + 1034 .thumb + 1035 .thumb_func + 1037 HAL_ADCEx_InjectedGetValue: + 1038 .LVL76: + 1039 .LFB146: + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __IO uint32_t tmp = 0; + 1040 .loc 1 537 1 is_stmt 1 view -0 + 1041 .cfi_startproc + 1042 @ args = 0, pretend = 0, frame = 8 + 1043 @ frame_needed = 0, uses_anonymous_args = 0 + 1044 @ link register save eliminated. + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __IO uint32_t tmp = 0; + 1045 .loc 1 537 1 is_stmt 0 view .LVU313 + 1046 0000 82B0 sub sp, sp, #8 + 1047 .LCFI10: + 1048 .cfi_def_cfa_offset 8 + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1049 .loc 1 538 3 is_stmt 1 view .LVU314 + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1050 .loc 1 538 17 is_stmt 0 view .LVU315 + 1051 0002 0023 movs r3, #0 + ARM GAS /tmp/cc5LZY9S.s page 43 + + + 1052 0004 0193 str r3, [sp, #4] + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1053 .loc 1 541 3 is_stmt 1 view .LVU316 + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1054 .loc 1 545 3 view .LVU317 + 1055 0006 0368 ldr r3, [r0] + 1056 0008 6FF00402 mvn r2, #4 + 1057 000c 1A60 str r2, [r3] + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1058 .loc 1 548 3 view .LVU318 + 1059 000e 0139 subs r1, r1, #1 + 1060 .LVL77: + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1061 .loc 1 548 3 is_stmt 0 view .LVU319 + 1062 0010 0329 cmp r1, #3 + 1063 0012 06D8 bhi .L77 + 1064 0014 DFE801F0 tbb [pc, r1] + 1065 .L79: + 1066 0018 10 .byte (.L82-.L79)/2 + 1067 0019 0C .byte (.L81-.L79)/2 + 1068 001a 08 .byte (.L80-.L79)/2 + 1069 001b 02 .byte (.L78-.L79)/2 + 1070 .p2align 1 + 1071 .L78: + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1072 .loc 1 552 7 is_stmt 1 view .LVU320 + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1073 .loc 1 552 18 is_stmt 0 view .LVU321 + 1074 001c 0368 ldr r3, [r0] + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1075 .loc 1 552 28 view .LVU322 + 1076 001e 9B6C ldr r3, [r3, #72] + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1077 .loc 1 552 11 view .LVU323 + 1078 0020 0193 str r3, [sp, #4] + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** case ADC_INJECTED_RANK_3: + 1079 .loc 1 554 5 is_stmt 1 view .LVU324 + 1080 .L77: + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1081 .loc 1 573 3 view .LVU325 + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1082 .loc 1 573 10 is_stmt 0 view .LVU326 + 1083 0022 0198 ldr r0, [sp, #4] + 1084 .LVL78: + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1085 .loc 1 574 1 view .LVU327 + 1086 0024 02B0 add sp, sp, #8 + 1087 .LCFI11: + 1088 .cfi_remember_state + 1089 .cfi_def_cfa_offset 0 + 1090 @ sp needed + 1091 0026 7047 bx lr + 1092 .LVL79: + 1093 .L80: + 1094 .LCFI12: + 1095 .cfi_restore_state + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + ARM GAS /tmp/cc5LZY9S.s page 44 + + + 1096 .loc 1 557 7 is_stmt 1 view .LVU328 + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1097 .loc 1 557 18 is_stmt 0 view .LVU329 + 1098 0028 0368 ldr r3, [r0] + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1099 .loc 1 557 28 view .LVU330 + 1100 002a 5B6C ldr r3, [r3, #68] + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1101 .loc 1 557 11 view .LVU331 + 1102 002c 0193 str r3, [sp, #4] + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** case ADC_INJECTED_RANK_2: + 1103 .loc 1 559 5 is_stmt 1 view .LVU332 + 1104 002e F8E7 b .L77 + 1105 .L81: + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1106 .loc 1 562 7 view .LVU333 + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1107 .loc 1 562 18 is_stmt 0 view .LVU334 + 1108 0030 0368 ldr r3, [r0] + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1109 .loc 1 562 28 view .LVU335 + 1110 0032 1B6C ldr r3, [r3, #64] + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1111 .loc 1 562 11 view .LVU336 + 1112 0034 0193 str r3, [sp, #4] + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** case ADC_INJECTED_RANK_1: + 1113 .loc 1 564 5 is_stmt 1 view .LVU337 + 1114 0036 F4E7 b .L77 + 1115 .L82: + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1116 .loc 1 567 7 view .LVU338 + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1117 .loc 1 567 18 is_stmt 0 view .LVU339 + 1118 0038 0368 ldr r3, [r0] + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1119 .loc 1 567 28 view .LVU340 + 1120 003a DB6B ldr r3, [r3, #60] + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1121 .loc 1 567 11 view .LVU341 + 1122 003c 0193 str r3, [sp, #4] + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** default: + 1123 .loc 1 569 5 is_stmt 1 view .LVU342 + 1124 003e F0E7 b .L77 + 1125 .cfi_endproc + 1126 .LFE146: + 1128 .section .text.HAL_ADCEx_MultiModeStart_DMA,"ax",%progbits + 1129 .align 1 + 1130 .global HAL_ADCEx_MultiModeStart_DMA + 1131 .syntax unified + 1132 .thumb + 1133 .thumb_func + 1135 HAL_ADCEx_MultiModeStart_DMA: + 1136 .LVL80: + 1137 .LFB147: + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __IO uint32_t counter = 0; + 1138 .loc 1 588 1 view -0 + 1139 .cfi_startproc + ARM GAS /tmp/cc5LZY9S.s page 45 + + + 1140 @ args = 0, pretend = 0, frame = 8 + 1141 @ frame_needed = 0, uses_anonymous_args = 0 + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** __IO uint32_t counter = 0; + 1142 .loc 1 588 1 is_stmt 0 view .LVU344 + 1143 0000 30B5 push {r4, r5, lr} + 1144 .LCFI13: + 1145 .cfi_def_cfa_offset 12 + 1146 .cfi_offset 4, -12 + 1147 .cfi_offset 5, -8 + 1148 .cfi_offset 14, -4 + 1149 0002 83B0 sub sp, sp, #12 + 1150 .LCFI14: + 1151 .cfi_def_cfa_offset 24 + 1152 0004 1346 mov r3, r2 + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1153 .loc 1 589 3 is_stmt 1 view .LVU345 + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1154 .loc 1 589 17 is_stmt 0 view .LVU346 + 1155 0006 0022 movs r2, #0 + 1156 .LVL81: + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1157 .loc 1 589 17 view .LVU347 + 1158 0008 0192 str r2, [sp, #4] + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + 1159 .loc 1 592 3 is_stmt 1 view .LVU348 + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); + 1160 .loc 1 593 3 view .LVU349 + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1161 .loc 1 594 3 view .LVU350 + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1162 .loc 1 597 3 view .LVU351 + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1163 .loc 1 597 3 view .LVU352 + 1164 000a 90F83C20 ldrb r2, [r0, #60] @ zero_extendqisi2 + 1165 000e 012A cmp r2, #1 + 1166 0010 7AD0 beq .L96 + 1167 0012 0446 mov r4, r0 + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1168 .loc 1 597 3 discriminator 2 view .LVU353 + 1169 0014 0122 movs r2, #1 + 1170 0016 80F83C20 strb r2, [r0, #60] + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1171 .loc 1 597 3 discriminator 2 view .LVU354 + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1172 .loc 1 601 3 view .LVU355 + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1173 .loc 1 601 11 is_stmt 0 view .LVU356 + 1174 001a 0268 ldr r2, [r0] + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1175 .loc 1 601 21 view .LVU357 + 1176 001c 9068 ldr r0, [r2, #8] + 1177 .LVL82: + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1178 .loc 1 601 5 view .LVU358 + 1179 001e 10F0010F tst r0, #1 + 1180 0022 13D1 bne .L87 + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + ARM GAS /tmp/cc5LZY9S.s page 46 + + + 1181 .loc 1 604 5 is_stmt 1 view .LVU359 + 1182 0024 9068 ldr r0, [r2, #8] + 1183 0026 40F00100 orr r0, r0, #1 + 1184 002a 9060 str r0, [r2, #8] + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** while(counter != 0) + 1185 .loc 1 608 5 view .LVU360 + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** while(counter != 0) + 1186 .loc 1 608 53 is_stmt 0 view .LVU361 + 1187 002c 384A ldr r2, .L99 + 1188 002e 1068 ldr r0, [r2] + 1189 0030 384A ldr r2, .L99+4 + 1190 0032 A2FB0020 umull r2, r0, r2, r0 + 1191 0036 800C lsrs r0, r0, #18 + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** while(counter != 0) + 1192 .loc 1 608 34 view .LVU362 + 1193 0038 00EB4000 add r0, r0, r0, lsl #1 + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** while(counter != 0) + 1194 .loc 1 608 13 view .LVU363 + 1195 003c 0190 str r0, [sp, #4] + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1196 .loc 1 609 5 is_stmt 1 view .LVU364 + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1197 .loc 1 609 10 is_stmt 0 view .LVU365 + 1198 003e 02E0 b .L88 + 1199 .L89: + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1200 .loc 1 611 7 is_stmt 1 view .LVU366 + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1201 .loc 1 611 14 is_stmt 0 view .LVU367 + 1202 0040 0198 ldr r0, [sp, #4] + 1203 0042 0138 subs r0, r0, #1 + 1204 0044 0190 str r0, [sp, #4] + 1205 .L88: + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1206 .loc 1 609 19 is_stmt 1 view .LVU368 + 1207 0046 0198 ldr r0, [sp, #4] + 1208 0048 0028 cmp r0, #0 + 1209 004a F9D1 bne .L89 + 1210 .L87: + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1211 .loc 1 616 3 view .LVU369 + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1212 .loc 1 616 6 is_stmt 0 view .LVU370 + 1213 004c 2068 ldr r0, [r4] + 1214 004e 8268 ldr r2, [r0, #8] + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1215 .loc 1 616 5 view .LVU371 + 1216 0050 12F0010F tst r2, #1 + 1217 0054 4DD0 beq .L90 + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + 1218 .loc 1 621 5 is_stmt 1 view .LVU372 + 1219 0056 256C ldr r5, [r4, #64] + 1220 0058 2F4A ldr r2, .L99+8 + 1221 005a 2A40 ands r2, r2, r5 + 1222 005c 42F48072 orr r2, r2, #256 + 1223 0060 2264 str r2, [r4, #64] + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + ARM GAS /tmp/cc5LZY9S.s page 47 + + + 1224 .loc 1 627 5 view .LVU373 + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1225 .loc 1 627 9 is_stmt 0 view .LVU374 + 1226 0062 4268 ldr r2, [r0, #4] + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1227 .loc 1 627 8 view .LVU375 + 1228 0064 12F4806F tst r2, #1024 + 1229 0068 05D0 beq .L91 + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1230 .loc 1 629 7 is_stmt 1 view .LVU376 + 1231 006a 226C ldr r2, [r4, #64] + 1232 006c 22F44052 bic r2, r2, #12288 + 1233 0070 42F48052 orr r2, r2, #4096 + 1234 0074 2264 str r2, [r4, #64] + 1235 .L91: + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1236 .loc 1 633 5 view .LVU377 + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1237 .loc 1 633 9 is_stmt 0 view .LVU378 + 1238 0076 226C ldr r2, [r4, #64] + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1239 .loc 1 633 8 view .LVU379 + 1240 0078 12F4805F tst r2, #4096 + 1241 007c 30D0 beq .L92 + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1242 .loc 1 636 7 is_stmt 1 view .LVU380 + 1243 007e 626C ldr r2, [r4, #68] + 1244 0080 22F00602 bic r2, r2, #6 + 1245 0084 6264 str r2, [r4, #68] + 1246 .L93: + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1247 .loc 1 647 5 view .LVU381 + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1248 .loc 1 647 5 view .LVU382 + 1249 0086 0022 movs r2, #0 + 1250 0088 84F83C20 strb r2, [r4, #60] + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1251 .loc 1 647 5 view .LVU383 + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1252 .loc 1 650 5 view .LVU384 + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1253 .loc 1 650 9 is_stmt 0 view .LVU385 + 1254 008c A26B ldr r2, [r4, #56] + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1255 .loc 1 650 40 view .LVU386 + 1256 008e 2348 ldr r0, .L99+12 + 1257 0090 D063 str r0, [r2, #60] + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1258 .loc 1 653 5 is_stmt 1 view .LVU387 + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1259 .loc 1 653 9 is_stmt 0 view .LVU388 + 1260 0092 A26B ldr r2, [r4, #56] + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1261 .loc 1 653 44 view .LVU389 + 1262 0094 2248 ldr r0, .L99+16 + 1263 0096 1064 str r0, [r2, #64] + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + ARM GAS /tmp/cc5LZY9S.s page 48 + + + 1264 .loc 1 656 5 is_stmt 1 view .LVU390 + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1265 .loc 1 656 9 is_stmt 0 view .LVU391 + 1266 0098 A26B ldr r2, [r4, #56] + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1267 .loc 1 656 41 view .LVU392 + 1268 009a 2248 ldr r0, .L99+20 + 1269 009c D064 str r0, [r2, #76] + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1270 .loc 1 663 5 is_stmt 1 view .LVU393 + 1271 009e 2268 ldr r2, [r4] + 1272 00a0 6FF00200 mvn r0, #2 + 1273 00a4 1060 str r0, [r2] + 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1274 .loc 1 666 5 view .LVU394 + 1275 00a6 2068 ldr r0, [r4] + 1276 00a8 4268 ldr r2, [r0, #4] + 1277 00aa 42F08062 orr r2, r2, #67108864 + 1278 00ae 4260 str r2, [r0, #4] + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1279 .loc 1 668 5 view .LVU395 + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1280 .loc 1 668 19 is_stmt 0 view .LVU396 + 1281 00b0 94F83020 ldrb r2, [r4, #48] @ zero_extendqisi2 + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1282 .loc 1 668 8 view .LVU397 + 1283 00b4 BAB1 cbz r2, .L94 + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1284 .loc 1 671 7 is_stmt 1 view .LVU398 + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1285 .loc 1 671 10 is_stmt 0 view .LVU399 + 1286 00b6 1C48 ldr r0, .L99+24 + 1287 00b8 4268 ldr r2, [r0, #4] + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1288 .loc 1 671 16 view .LVU400 + 1289 00ba 42F40052 orr r2, r2, #8192 + 1290 00be 4260 str r2, [r0, #4] + 1291 .L95: + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1292 .loc 1 680 5 is_stmt 1 view .LVU401 + 1293 00c0 0A46 mov r2, r1 + 1294 00c2 1A49 ldr r1, .L99+28 + 1295 .LVL83: + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1296 .loc 1 680 5 is_stmt 0 view .LVU402 + 1297 00c4 A06B ldr r0, [r4, #56] + 1298 00c6 FFF7FEFF bl HAL_DMA_Start_IT + 1299 .LVL84: + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1300 .loc 1 683 5 is_stmt 1 view .LVU403 + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1301 .loc 1 683 13 is_stmt 0 view .LVU404 + 1302 00ca 2368 ldr r3, [r4] + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1303 .loc 1 683 23 view .LVU405 + 1304 00cc 9A68 ldr r2, [r3, #8] + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + ARM GAS /tmp/cc5LZY9S.s page 49 + + + 1305 .loc 1 683 7 view .LVU406 + 1306 00ce 12F0405F tst r2, #805306368 + 1307 00d2 1BD1 bne .L97 + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1308 .loc 1 686 7 is_stmt 1 view .LVU407 + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1309 .loc 1 686 21 is_stmt 0 view .LVU408 + 1310 00d4 9A68 ldr r2, [r3, #8] + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1311 .loc 1 686 27 view .LVU409 + 1312 00d6 42F08042 orr r2, r2, #1073741824 + 1313 00da 9A60 str r2, [r3, #8] + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1314 .loc 1 699 10 view .LVU410 + 1315 00dc 0020 movs r0, #0 + 1316 00de 11E0 b .L86 + 1317 .LVL85: + 1318 .L92: + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1319 .loc 1 641 7 is_stmt 1 view .LVU411 + 1320 00e0 0022 movs r2, #0 + 1321 00e2 6264 str r2, [r4, #68] + 1322 00e4 CFE7 b .L93 + 1323 .L94: + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1324 .loc 1 676 7 view .LVU412 + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1325 .loc 1 676 10 is_stmt 0 view .LVU413 + 1326 00e6 1048 ldr r0, .L99+24 + 1327 00e8 4268 ldr r2, [r0, #4] + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1328 .loc 1 676 16 view .LVU414 + 1329 00ea 22F40052 bic r2, r2, #8192 + 1330 00ee 4260 str r2, [r0, #4] + 1331 00f0 E6E7 b .L95 + 1332 .L90: + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1333 .loc 1 692 5 is_stmt 1 view .LVU415 + 1334 00f2 236C ldr r3, [r4, #64] + 1335 .LVL86: + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1336 .loc 1 692 5 is_stmt 0 view .LVU416 + 1337 00f4 43F01003 orr r3, r3, #16 + 1338 00f8 2364 str r3, [r4, #64] + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1339 .loc 1 695 5 is_stmt 1 view .LVU417 + 1340 00fa 636C ldr r3, [r4, #68] + 1341 00fc 43F00103 orr r3, r3, #1 + 1342 0100 6364 str r3, [r4, #68] + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1343 .loc 1 699 10 is_stmt 0 view .LVU418 + 1344 0102 0020 movs r0, #0 + 1345 .LVL87: + 1346 .L86: + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1347 .loc 1 700 1 view .LVU419 + 1348 0104 03B0 add sp, sp, #12 + ARM GAS /tmp/cc5LZY9S.s page 50 + + + 1349 .LCFI15: + 1350 .cfi_remember_state + 1351 .cfi_def_cfa_offset 12 + 1352 @ sp needed + 1353 0106 30BD pop {r4, r5, pc} + 1354 .LVL88: + 1355 .L96: + 1356 .LCFI16: + 1357 .cfi_restore_state + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1358 .loc 1 597 3 discriminator 1 view .LVU420 + 1359 0108 0220 movs r0, #2 + 1360 .LVL89: + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1361 .loc 1 597 3 discriminator 1 view .LVU421 + 1362 010a FBE7 b .L86 + 1363 .LVL90: + 1364 .L97: + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1365 .loc 1 699 10 view .LVU422 + 1366 010c 0020 movs r0, #0 + 1367 010e F9E7 b .L86 + 1368 .L100: + 1369 .align 2 + 1370 .L99: + 1371 0110 00000000 .word SystemCoreClock + 1372 0114 83DE1B43 .word 1125899907 + 1373 0118 FEF8FFFF .word -1794 + 1374 011c 00000000 .word ADC_MultiModeDMAConvCplt + 1375 0120 00000000 .word ADC_MultiModeDMAHalfConvCplt + 1376 0124 00000000 .word ADC_MultiModeDMAError + 1377 0128 00230140 .word 1073816320 + 1378 012c 08230140 .word 1073816328 + 1379 .cfi_endproc + 1380 .LFE147: + 1382 .section .text.HAL_ADCEx_MultiModeStop_DMA,"ax",%progbits + 1383 .align 1 + 1384 .global HAL_ADCEx_MultiModeStop_DMA + 1385 .syntax unified + 1386 .thumb + 1387 .thumb_func + 1389 HAL_ADCEx_MultiModeStop_DMA: + 1390 .LVL91: + 1391 .LFB148: + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 1392 .loc 1 709 1 is_stmt 1 view -0 + 1393 .cfi_startproc + 1394 @ args = 0, pretend = 0, frame = 0 + 1395 @ frame_needed = 0, uses_anonymous_args = 0 + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1396 .loc 1 710 3 view .LVU424 + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1397 .loc 1 713 3 view .LVU425 + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1398 .loc 1 716 3 view .LVU426 + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1399 .loc 1 716 3 view .LVU427 + ARM GAS /tmp/cc5LZY9S.s page 51 + + + 1400 0000 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 1401 0004 012B cmp r3, #1 + 1402 0006 27D0 beq .L104 + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 1403 .loc 1 709 1 is_stmt 0 view .LVU428 + 1404 0008 10B5 push {r4, lr} + 1405 .LCFI17: + 1406 .cfi_def_cfa_offset 8 + 1407 .cfi_offset 4, -8 + 1408 .cfi_offset 14, -4 + 1409 000a 0446 mov r4, r0 + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1410 .loc 1 716 3 is_stmt 1 discriminator 2 view .LVU429 + 1411 000c 0123 movs r3, #1 + 1412 000e 80F83C30 strb r3, [r0, #60] + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1413 .loc 1 716 3 discriminator 2 view .LVU430 + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1414 .loc 1 720 3 view .LVU431 + 1415 0012 0268 ldr r2, [r0] + 1416 0014 9368 ldr r3, [r2, #8] + 1417 0016 23F00103 bic r3, r3, #1 + 1418 001a 9360 str r3, [r2, #8] + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1419 .loc 1 723 3 view .LVU432 + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1420 .loc 1 723 6 is_stmt 0 view .LVU433 + 1421 001c 0368 ldr r3, [r0] + 1422 001e 9B68 ldr r3, [r3, #8] + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1423 .loc 1 723 5 view .LVU434 + 1424 0020 13F0010F tst r3, #1 + 1425 0024 04D0 beq .L110 + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1426 .loc 1 710 21 view .LVU435 + 1427 0026 0020 movs r0, #0 + 1428 .LVL92: + 1429 .L103: + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1430 .loc 1 742 3 is_stmt 1 view .LVU436 + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1431 .loc 1 742 3 view .LVU437 + 1432 0028 0023 movs r3, #0 + 1433 002a 84F83C30 strb r3, [r4, #60] + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1434 .loc 1 742 3 view .LVU438 + 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1435 .loc 1 745 3 view .LVU439 + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1436 .loc 1 746 1 is_stmt 0 view .LVU440 + 1437 002e 10BD pop {r4, pc} + 1438 .LVL93: + 1439 .L110: + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1440 .loc 1 726 5 is_stmt 1 view .LVU441 + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1441 .loc 1 726 8 is_stmt 0 view .LVU442 + ARM GAS /tmp/cc5LZY9S.s page 52 + + + 1442 0030 0A4A ldr r2, .L111 + 1443 0032 5368 ldr r3, [r2, #4] + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1444 .loc 1 726 14 view .LVU443 + 1445 0034 23F40053 bic r3, r3, #8192 + 1446 0038 5360 str r3, [r2, #4] + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1447 .loc 1 730 5 is_stmt 1 view .LVU444 + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1448 .loc 1 730 22 is_stmt 0 view .LVU445 + 1449 003a 806B ldr r0, [r0, #56] + 1450 .LVL94: + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1451 .loc 1 730 22 view .LVU446 + 1452 003c FFF7FEFF bl HAL_DMA_Abort + 1453 .LVL95: + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1454 .loc 1 733 5 is_stmt 1 view .LVU447 + 1455 0040 2268 ldr r2, [r4] + 1456 0042 5368 ldr r3, [r2, #4] + 1457 0044 23F08063 bic r3, r3, #67108864 + 1458 0048 5360 str r3, [r2, #4] + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + 1459 .loc 1 736 5 view .LVU448 + 1460 004a 226C ldr r2, [r4, #64] + 1461 004c 044B ldr r3, .L111+4 + 1462 004e 1340 ands r3, r3, r2 + 1463 0050 43F00103 orr r3, r3, #1 + 1464 0054 2364 str r3, [r4, #64] + 1465 0056 E7E7 b .L103 + 1466 .LVL96: + 1467 .L104: + 1468 .LCFI18: + 1469 .cfi_def_cfa_offset 0 + 1470 .cfi_restore 4 + 1471 .cfi_restore 14 + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1472 .loc 1 716 3 is_stmt 0 discriminator 1 view .LVU449 + 1473 0058 0220 movs r0, #2 + 1474 .LVL97: + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1475 .loc 1 746 1 view .LVU450 + 1476 005a 7047 bx lr + 1477 .L112: + 1478 .align 2 + 1479 .L111: + 1480 005c 00230140 .word 1073816320 + 1481 0060 FEEEFFFF .word -4354 + 1482 .cfi_endproc + 1483 .LFE148: + 1485 .section .text.HAL_ADCEx_MultiModeGetValue,"ax",%progbits + 1486 .align 1 + 1487 .global HAL_ADCEx_MultiModeGetValue + 1488 .syntax unified + 1489 .thumb + 1490 .thumb_func + 1492 HAL_ADCEx_MultiModeGetValue: + ARM GAS /tmp/cc5LZY9S.s page 53 + + + 1493 .LVL98: + 1494 .LFB149: + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Prevent unused argument(s) compilation warning */ + 1495 .loc 1 756 1 is_stmt 1 view -0 + 1496 .cfi_startproc + 1497 @ args = 0, pretend = 0, frame = 0 + 1498 @ frame_needed = 0, uses_anonymous_args = 0 + 1499 @ link register save eliminated. + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1500 .loc 1 758 3 view .LVU452 + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1501 .loc 1 761 3 view .LVU453 + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1502 .loc 1 761 13 is_stmt 0 view .LVU454 + 1503 0000 014B ldr r3, .L114 + 1504 0002 9868 ldr r0, [r3, #8] + 1505 .LVL99: + 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1506 .loc 1 762 1 view .LVU455 + 1507 0004 7047 bx lr + 1508 .L115: + 1509 0006 00BF .align 2 + 1510 .L114: + 1511 0008 00230140 .word 1073816320 + 1512 .cfi_endproc + 1513 .LFE149: + 1515 .section .text.HAL_ADCEx_InjectedConvCpltCallback,"ax",%progbits + 1516 .align 1 + 1517 .weak HAL_ADCEx_InjectedConvCpltCallback + 1518 .syntax unified + 1519 .thumb + 1520 .thumb_func + 1522 HAL_ADCEx_InjectedConvCpltCallback: + 1523 .LVL100: + 1524 .LFB150: + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Prevent unused argument(s) compilation warning */ + 1525 .loc 1 771 1 is_stmt 1 view -0 + 1526 .cfi_startproc + 1527 @ args = 0, pretend = 0, frame = 0 + 1528 @ frame_needed = 0, uses_anonymous_args = 0 + 1529 @ link register save eliminated. + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 1530 .loc 1 773 3 view .LVU457 + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1531 .loc 1 777 1 is_stmt 0 view .LVU458 + 1532 0000 7047 bx lr + 1533 .cfi_endproc + 1534 .LFE150: + 1536 .section .text.HAL_ADCEx_InjectedConfigChannel,"ax",%progbits + 1537 .align 1 + 1538 .global HAL_ADCEx_InjectedConfigChannel + 1539 .syntax unified + 1540 .thumb + 1541 .thumb_func + 1543 HAL_ADCEx_InjectedConfigChannel: + 1544 .LVL101: + 1545 .LFB151: + ARM GAS /tmp/cc5LZY9S.s page 54 + + + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1546 .loc 1 788 1 is_stmt 1 view -0 + 1547 .cfi_startproc + 1548 @ args = 0, pretend = 0, frame = 0 + 1549 @ frame_needed = 0, uses_anonymous_args = 0 + 1550 @ link register save eliminated. + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); + 1551 .loc 1 795 3 view .LVU460 + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); + 1552 .loc 1 796 3 view .LVU461 + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv)); + 1553 .loc 1 797 3 view .LVU462 + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion)); + 1554 .loc 1 798 3 view .LVU463 + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); + 1555 .loc 1 799 3 view .LVU464 + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); + 1556 .loc 1 800 3 view .LVU465 + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1557 .loc 1 801 3 view .LVU466 + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1558 .loc 1 808 3 view .LVU467 + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1559 .loc 1 810 5 view .LVU468 + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1560 .loc 1 814 3 view .LVU469 + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1561 .loc 1 814 3 view .LVU470 + 1562 0000 90F83C20 ldrb r2, [r0, #60] @ zero_extendqisi2 + 1563 0004 012A cmp r2, #1 + 1564 0006 00F0F480 beq .L133 + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1565 .loc 1 788 1 is_stmt 0 view .LVU471 + 1566 000a 30B4 push {r4, r5} + 1567 .LCFI19: + 1568 .cfi_def_cfa_offset 8 + 1569 .cfi_offset 4, -8 + 1570 .cfi_offset 5, -4 + 1571 000c 0346 mov r3, r0 + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1572 .loc 1 814 3 is_stmt 1 discriminator 2 view .LVU472 + 1573 000e 0122 movs r2, #1 + 1574 0010 80F83C20 strb r2, [r0, #60] + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1575 .loc 1 814 3 discriminator 2 view .LVU473 + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1576 .loc 1 817 3 view .LVU474 + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1577 .loc 1 817 22 is_stmt 0 view .LVU475 + 1578 0014 0A68 ldr r2, [r1] + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1579 .loc 1 817 6 view .LVU476 + 1580 0016 092A cmp r2, #9 + 1581 0018 40F28980 bls .L119 + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1582 .loc 1 820 5 is_stmt 1 view .LVU477 + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + ARM GAS /tmp/cc5LZY9S.s page 55 + + + 1583 .loc 1 820 9 is_stmt 0 view .LVU478 + 1584 001c 0568 ldr r5, [r0] + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1585 .loc 1 820 19 view .LVU479 + 1586 001e E868 ldr r0, [r5, #12] + 1587 .LVL102: + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1588 .loc 1 820 31 view .LVU480 + 1589 0020 92B2 uxth r2, r2 + 1590 0022 02EB4202 add r2, r2, r2, lsl #1 + 1591 0026 1E3A subs r2, r2, #30 + 1592 0028 0724 movs r4, #7 + 1593 002a 04FA02F2 lsl r2, r4, r2 + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1594 .loc 1 820 27 view .LVU481 + 1595 002e 20EA0202 bic r2, r0, r2 + 1596 0032 EA60 str r2, [r5, #12] + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1597 .loc 1 823 5 is_stmt 1 view .LVU482 + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1598 .loc 1 823 9 is_stmt 0 view .LVU483 + 1599 0034 1D68 ldr r5, [r3] + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1600 .loc 1 823 19 view .LVU484 + 1601 0036 E868 ldr r0, [r5, #12] + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1602 .loc 1 823 30 view .LVU485 + 1603 0038 8C68 ldr r4, [r1, #8] + 1604 003a 0A88 ldrh r2, [r1] + 1605 003c 02EB4202 add r2, r2, r2, lsl #1 + 1606 0040 1E3A subs r2, r2, #30 + 1607 0042 9440 lsls r4, r4, r2 + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1608 .loc 1 823 27 view .LVU486 + 1609 0044 2043 orrs r0, r0, r4 + 1610 0046 E860 str r0, [r5, #12] + 1611 .L120: + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion); + 1612 .loc 1 835 3 is_stmt 1 view .LVU487 + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion); + 1613 .loc 1 835 7 is_stmt 0 view .LVU488 + 1614 0048 1868 ldr r0, [r3] + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion); + 1615 .loc 1 835 17 view .LVU489 + 1616 004a 826B ldr r2, [r0, #56] + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion); + 1617 .loc 1 835 24 view .LVU490 + 1618 004c 22F44012 bic r2, r2, #3145728 + 1619 0050 8263 str r2, [r0, #56] + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1620 .loc 1 836 3 is_stmt 1 view .LVU491 + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1621 .loc 1 836 7 is_stmt 0 view .LVU492 + 1622 0052 1C68 ldr r4, [r3] + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1623 .loc 1 836 17 view .LVU493 + 1624 0054 A26B ldr r2, [r4, #56] + ARM GAS /tmp/cc5LZY9S.s page 56 + + + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1625 .loc 1 836 28 view .LVU494 + 1626 0056 0869 ldr r0, [r1, #16] + 1627 0058 0138 subs r0, r0, #1 + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1628 .loc 1 836 24 view .LVU495 + 1629 005a 42EA0052 orr r2, r2, r0, lsl #20 + 1630 005e A263 str r2, [r4, #56] + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1631 .loc 1 841 3 is_stmt 1 view .LVU496 + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1632 .loc 1 841 7 is_stmt 0 view .LVU497 + 1633 0060 1C68 ldr r4, [r3] + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1634 .loc 1 841 17 view .LVU498 + 1635 0062 A06B ldr r0, [r4, #56] + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1636 .loc 1 841 28 view .LVU499 + 1637 0064 4A68 ldr r2, [r1, #4] + 1638 0066 0D69 ldr r5, [r1, #16] + 1639 0068 521B subs r2, r2, r5 + 1640 006a D2B2 uxtb r2, r2 + 1641 006c 0332 adds r2, r2, #3 + 1642 006e D2B2 uxtb r2, r2 + 1643 0070 02EB8202 add r2, r2, r2, lsl #2 + 1644 0074 4FF01F0C mov ip, #31 + 1645 0078 0CFA02F2 lsl r2, ip, r2 + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1646 .loc 1 841 24 view .LVU500 + 1647 007c 20EA0202 bic r2, r0, r2 + 1648 0080 A263 str r2, [r4, #56] + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1649 .loc 1 844 3 is_stmt 1 view .LVU501 + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1650 .loc 1 844 7 is_stmt 0 view .LVU502 + 1651 0082 1C68 ldr r4, [r3] + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1652 .loc 1 844 17 view .LVU503 + 1653 0084 A06B ldr r0, [r4, #56] + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1654 .loc 1 844 27 view .LVU504 + 1655 0086 4A68 ldr r2, [r1, #4] + 1656 0088 0D69 ldr r5, [r1, #16] + 1657 008a 521B subs r2, r2, r5 + 1658 008c D2B2 uxtb r2, r2 + 1659 008e 0332 adds r2, r2, #3 + 1660 0090 D2B2 uxtb r2, r2 + 1661 0092 02EB8202 add r2, r2, r2, lsl #2 + 1662 0096 B1F800C0 ldrh ip, [r1] + 1663 009a 0CFA02F2 lsl r2, ip, r2 + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1664 .loc 1 844 24 view .LVU505 + 1665 009e 0243 orrs r2, r2, r0 + 1666 00a0 A263 str r2, [r4, #56] + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1667 .loc 1 851 3 is_stmt 1 view .LVU506 + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + ARM GAS /tmp/cc5LZY9S.s page 57 + + + 1668 .loc 1 851 21 is_stmt 0 view .LVU507 + 1669 00a2 8869 ldr r0, [r1, #24] + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1670 .loc 1 851 5 view .LVU508 + 1671 00a4 544A ldr r2, .L140 + 1672 00a6 9042 cmp r0, r2 + 1673 00a8 56D0 beq .L121 + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv; + 1674 .loc 1 854 5 is_stmt 1 view .LVU509 + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv; + 1675 .loc 1 854 9 is_stmt 0 view .LVU510 + 1676 00aa 1868 ldr r0, [r3] + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv; + 1677 .loc 1 854 19 view .LVU511 + 1678 00ac 8268 ldr r2, [r0, #8] + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv; + 1679 .loc 1 854 25 view .LVU512 + 1680 00ae 22F47022 bic r2, r2, #983040 + 1681 00b2 8260 str r2, [r0, #8] + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1682 .loc 1 855 5 is_stmt 1 view .LVU513 + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1683 .loc 1 855 9 is_stmt 0 view .LVU514 + 1684 00b4 1868 ldr r0, [r3] + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1685 .loc 1 855 19 view .LVU515 + 1686 00b6 8268 ldr r2, [r0, #8] + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1687 .loc 1 855 44 view .LVU516 + 1688 00b8 8C69 ldr r4, [r1, #24] + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1689 .loc 1 855 25 view .LVU517 + 1690 00ba 2243 orrs r2, r2, r4 + 1691 00bc 8260 str r2, [r0, #8] + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge; + 1692 .loc 1 858 5 is_stmt 1 view .LVU518 + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge; + 1693 .loc 1 858 9 is_stmt 0 view .LVU519 + 1694 00be 1868 ldr r0, [r3] + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge; + 1695 .loc 1 858 19 view .LVU520 + 1696 00c0 8268 ldr r2, [r0, #8] + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge; + 1697 .loc 1 858 25 view .LVU521 + 1698 00c2 22F44012 bic r2, r2, #3145728 + 1699 00c6 8260 str r2, [r0, #8] + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1700 .loc 1 859 5 is_stmt 1 view .LVU522 + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1701 .loc 1 859 9 is_stmt 0 view .LVU523 + 1702 00c8 1868 ldr r0, [r3] + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1703 .loc 1 859 19 view .LVU524 + 1704 00ca 8268 ldr r2, [r0, #8] + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1705 .loc 1 859 43 view .LVU525 + 1706 00cc CC69 ldr r4, [r1, #28] + ARM GAS /tmp/cc5LZY9S.s page 58 + + + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1707 .loc 1 859 25 view .LVU526 + 1708 00ce 2243 orrs r2, r2, r4 + 1709 00d0 8260 str r2, [r0, #8] + 1710 .L122: + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1711 .loc 1 868 3 is_stmt 1 view .LVU527 + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1712 .loc 1 868 22 is_stmt 0 view .LVU528 + 1713 00d2 4A7D ldrb r2, [r1, #21] @ zero_extendqisi2 + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1714 .loc 1 868 6 view .LVU529 + 1715 00d4 002A cmp r2, #0 + 1716 00d6 4AD0 beq .L123 + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1717 .loc 1 871 5 is_stmt 1 view .LVU530 + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1718 .loc 1 871 9 is_stmt 0 view .LVU531 + 1719 00d8 1868 ldr r0, [r3] + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1720 .loc 1 871 19 view .LVU532 + 1721 00da 4268 ldr r2, [r0, #4] + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1722 .loc 1 871 25 view .LVU533 + 1723 00dc 42F48062 orr r2, r2, #1024 + 1724 00e0 4260 str r2, [r0, #4] + 1725 .L124: + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1726 .loc 1 879 3 is_stmt 1 view .LVU534 + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1727 .loc 1 879 22 is_stmt 0 view .LVU535 + 1728 00e2 0A7D ldrb r2, [r1, #20] @ zero_extendqisi2 + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1729 .loc 1 879 6 view .LVU536 + 1730 00e4 002A cmp r2, #0 + 1731 00e6 48D0 beq .L125 + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1732 .loc 1 882 5 is_stmt 1 view .LVU537 + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1733 .loc 1 882 9 is_stmt 0 view .LVU538 + 1734 00e8 1868 ldr r0, [r3] + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1735 .loc 1 882 19 view .LVU539 + 1736 00ea 4268 ldr r2, [r0, #4] + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1737 .loc 1 882 25 view .LVU540 + 1738 00ec 42F48052 orr r2, r2, #4096 + 1739 00f0 4260 str r2, [r0, #4] + 1740 .L126: + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1741 .loc 1 890 3 is_stmt 1 view .LVU541 + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1742 .loc 1 890 25 is_stmt 0 view .LVU542 + 1743 00f2 4A68 ldr r2, [r1, #4] + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1744 .loc 1 890 3 view .LVU543 + 1745 00f4 022A cmp r2, #2 + ARM GAS /tmp/cc5LZY9S.s page 59 + + + 1746 00f6 46D0 beq .L127 + 1747 00f8 032A cmp r2, #3 + 1748 00fa 4FD0 beq .L128 + 1749 00fc 012A cmp r2, #1 + 1750 00fe 58D1 bne .L129 + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset; + 1751 .loc 1 894 7 is_stmt 1 view .LVU544 + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset; + 1752 .loc 1 894 11 is_stmt 0 view .LVU545 + 1753 0100 1868 ldr r0, [r3] + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset; + 1754 .loc 1 894 21 view .LVU546 + 1755 0102 4269 ldr r2, [r0, #20] + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset; + 1756 .loc 1 894 29 view .LVU547 + 1757 0104 6FF30B02 bfc r2, #0, #12 + 1758 0108 4261 str r2, [r0, #20] + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1759 .loc 1 895 7 is_stmt 1 view .LVU548 + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1760 .loc 1 895 11 is_stmt 0 view .LVU549 + 1761 010a 1868 ldr r0, [r3] + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1762 .loc 1 895 21 view .LVU550 + 1763 010c 4269 ldr r2, [r0, #20] + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1764 .loc 1 895 47 view .LVU551 + 1765 010e CC68 ldr r4, [r1, #12] + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1766 .loc 1 895 29 view .LVU552 + 1767 0110 2243 orrs r2, r2, r4 + 1768 0112 4261 str r2, [r0, #20] + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** case 2: + 1769 .loc 1 896 7 is_stmt 1 view .LVU553 + 1770 .L130: + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1771 .loc 1 915 3 view .LVU554 + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1772 .loc 1 915 12 is_stmt 0 view .LVU555 + 1773 0114 1868 ldr r0, [r3] + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1774 .loc 1 915 6 view .LVU556 + 1775 0116 394A ldr r2, .L140+4 + 1776 0118 9042 cmp r0, r2 + 1777 011a 55D0 beq .L138 + 1778 .L131: + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1779 .loc 1 922 3 is_stmt 1 view .LVU557 + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1780 .loc 1 922 12 is_stmt 0 view .LVU558 + 1781 011c 1868 ldr r0, [r3] + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1782 .loc 1 922 6 view .LVU559 + 1783 011e 374A ldr r2, .L140+4 + 1784 0120 9042 cmp r0, r2 + 1785 0122 5AD0 beq .L139 + 1786 .LVL103: + ARM GAS /tmp/cc5LZY9S.s page 60 + + + 1787 .L132: + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1788 .loc 1 929 3 is_stmt 1 view .LVU560 + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1789 .loc 1 929 3 view .LVU561 + 1790 0124 0020 movs r0, #0 + 1791 0126 83F83C00 strb r0, [r3, #60] + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1792 .loc 1 929 3 view .LVU562 + 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1793 .loc 1 932 3 view .LVU563 + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1794 .loc 1 933 1 is_stmt 0 view .LVU564 + 1795 012a 30BC pop {r4, r5} + 1796 .LCFI20: + 1797 .cfi_remember_state + 1798 .cfi_restore 5 + 1799 .cfi_restore 4 + 1800 .cfi_def_cfa_offset 0 + 1801 012c 7047 bx lr + 1802 .LVL104: + 1803 .L119: + 1804 .LCFI21: + 1805 .cfi_restore_state + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1806 .loc 1 828 5 is_stmt 1 view .LVU565 + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1807 .loc 1 828 9 is_stmt 0 view .LVU566 + 1808 012e 0568 ldr r5, [r0] + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1809 .loc 1 828 19 view .LVU567 + 1810 0130 2869 ldr r0, [r5, #16] + 1811 .LVL105: + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1812 .loc 1 828 31 view .LVU568 + 1813 0132 92B2 uxth r2, r2 + 1814 0134 02EB4202 add r2, r2, r2, lsl #1 + 1815 0138 0724 movs r4, #7 + 1816 013a 04FA02F2 lsl r2, r4, r2 + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1817 .loc 1 828 27 view .LVU569 + 1818 013e 20EA0202 bic r2, r0, r2 + 1819 0142 2A61 str r2, [r5, #16] + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1820 .loc 1 831 5 is_stmt 1 view .LVU570 + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1821 .loc 1 831 9 is_stmt 0 view .LVU571 + 1822 0144 1D68 ldr r5, [r3] + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1823 .loc 1 831 19 view .LVU572 + 1824 0146 2869 ldr r0, [r5, #16] + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1825 .loc 1 831 30 view .LVU573 + 1826 0148 8C68 ldr r4, [r1, #8] + 1827 014a 0A88 ldrh r2, [r1] + 1828 014c 02EB4202 add r2, r2, r2, lsl #1 + 1829 0150 9440 lsls r4, r4, r2 + ARM GAS /tmp/cc5LZY9S.s page 61 + + + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1830 .loc 1 831 27 view .LVU574 + 1831 0152 2043 orrs r0, r0, r4 + 1832 0154 2861 str r0, [r5, #16] + 1833 0156 77E7 b .L120 + 1834 .L121: + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); + 1835 .loc 1 864 5 is_stmt 1 view .LVU575 + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); + 1836 .loc 1 864 9 is_stmt 0 view .LVU576 + 1837 0158 1868 ldr r0, [r3] + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); + 1838 .loc 1 864 19 view .LVU577 + 1839 015a 8268 ldr r2, [r0, #8] + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); + 1840 .loc 1 864 25 view .LVU578 + 1841 015c 22F47022 bic r2, r2, #983040 + 1842 0160 8260 str r2, [r0, #8] + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1843 .loc 1 865 5 is_stmt 1 view .LVU579 + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1844 .loc 1 865 9 is_stmt 0 view .LVU580 + 1845 0162 1868 ldr r0, [r3] + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1846 .loc 1 865 19 view .LVU581 + 1847 0164 8268 ldr r2, [r0, #8] + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1848 .loc 1 865 25 view .LVU582 + 1849 0166 22F44012 bic r2, r2, #3145728 + 1850 016a 8260 str r2, [r0, #8] + 1851 016c B1E7 b .L122 + 1852 .L123: + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1853 .loc 1 876 5 is_stmt 1 view .LVU583 + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1854 .loc 1 876 9 is_stmt 0 view .LVU584 + 1855 016e 1868 ldr r0, [r3] + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1856 .loc 1 876 19 view .LVU585 + 1857 0170 4268 ldr r2, [r0, #4] + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1858 .loc 1 876 25 view .LVU586 + 1859 0172 22F48062 bic r2, r2, #1024 + 1860 0176 4260 str r2, [r0, #4] + 1861 0178 B3E7 b .L124 + 1862 .L125: + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1863 .loc 1 887 5 is_stmt 1 view .LVU587 + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1864 .loc 1 887 9 is_stmt 0 view .LVU588 + 1865 017a 1868 ldr r0, [r3] + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1866 .loc 1 887 19 view .LVU589 + 1867 017c 4268 ldr r2, [r0, #4] + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1868 .loc 1 887 25 view .LVU590 + 1869 017e 22F48052 bic r2, r2, #4096 + ARM GAS /tmp/cc5LZY9S.s page 62 + + + 1870 0182 4260 str r2, [r0, #4] + 1871 0184 B5E7 b .L126 + 1872 .L127: + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset; + 1873 .loc 1 899 7 is_stmt 1 view .LVU591 + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset; + 1874 .loc 1 899 11 is_stmt 0 view .LVU592 + 1875 0186 1868 ldr r0, [r3] + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset; + 1876 .loc 1 899 21 view .LVU593 + 1877 0188 8269 ldr r2, [r0, #24] + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset; + 1878 .loc 1 899 29 view .LVU594 + 1879 018a 6FF30B02 bfc r2, #0, #12 + 1880 018e 8261 str r2, [r0, #24] + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1881 .loc 1 900 7 is_stmt 1 view .LVU595 + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1882 .loc 1 900 11 is_stmt 0 view .LVU596 + 1883 0190 1868 ldr r0, [r3] + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1884 .loc 1 900 21 view .LVU597 + 1885 0192 8269 ldr r2, [r0, #24] + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1886 .loc 1 900 47 view .LVU598 + 1887 0194 CC68 ldr r4, [r1, #12] + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1888 .loc 1 900 29 view .LVU599 + 1889 0196 2243 orrs r2, r2, r4 + 1890 0198 8261 str r2, [r0, #24] + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** case 3: + 1891 .loc 1 901 7 is_stmt 1 view .LVU600 + 1892 019a BBE7 b .L130 + 1893 .L128: + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset; + 1894 .loc 1 904 7 view .LVU601 + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset; + 1895 .loc 1 904 11 is_stmt 0 view .LVU602 + 1896 019c 1868 ldr r0, [r3] + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset; + 1897 .loc 1 904 21 view .LVU603 + 1898 019e C269 ldr r2, [r0, #28] + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset; + 1899 .loc 1 904 29 view .LVU604 + 1900 01a0 6FF30B02 bfc r2, #0, #12 + 1901 01a4 C261 str r2, [r0, #28] + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1902 .loc 1 905 7 is_stmt 1 view .LVU605 + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1903 .loc 1 905 11 is_stmt 0 view .LVU606 + 1904 01a6 1868 ldr r0, [r3] + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1905 .loc 1 905 21 view .LVU607 + 1906 01a8 C269 ldr r2, [r0, #28] + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1907 .loc 1 905 47 view .LVU608 + 1908 01aa CC68 ldr r4, [r1, #12] + ARM GAS /tmp/cc5LZY9S.s page 63 + + + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1909 .loc 1 905 29 view .LVU609 + 1910 01ac 2243 orrs r2, r2, r4 + 1911 01ae C261 str r2, [r0, #28] + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** default: + 1912 .loc 1 906 7 is_stmt 1 view .LVU610 + 1913 01b0 B0E7 b .L130 + 1914 .L129: + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset; + 1915 .loc 1 909 7 view .LVU611 + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset; + 1916 .loc 1 909 11 is_stmt 0 view .LVU612 + 1917 01b2 1868 ldr r0, [r3] + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset; + 1918 .loc 1 909 21 view .LVU613 + 1919 01b4 026A ldr r2, [r0, #32] + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset; + 1920 .loc 1 909 29 view .LVU614 + 1921 01b6 6FF30B02 bfc r2, #0, #12 + 1922 01ba 0262 str r2, [r0, #32] + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1923 .loc 1 910 7 is_stmt 1 view .LVU615 + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1924 .loc 1 910 11 is_stmt 0 view .LVU616 + 1925 01bc 1868 ldr r0, [r3] + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1926 .loc 1 910 21 view .LVU617 + 1927 01be 026A ldr r2, [r0, #32] + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1928 .loc 1 910 47 view .LVU618 + 1929 01c0 CC68 ldr r4, [r1, #12] + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** break; + 1930 .loc 1 910 29 view .LVU619 + 1931 01c2 2243 orrs r2, r2, r4 + 1932 01c4 0262 str r2, [r0, #32] + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1933 .loc 1 911 7 is_stmt 1 view .LVU620 + 1934 01c6 A5E7 b .L130 + 1935 .L138: + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1936 .loc 1 915 51 is_stmt 0 discriminator 1 view .LVU621 + 1937 01c8 0A68 ldr r2, [r1] + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1938 .loc 1 915 32 discriminator 1 view .LVU622 + 1939 01ca 122A cmp r2, #18 + 1940 01cc A6D1 bne .L131 + 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1941 .loc 1 918 5 is_stmt 1 view .LVU623 + 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1942 .loc 1 918 8 is_stmt 0 view .LVU624 + 1943 01ce 0C48 ldr r0, .L140+8 + 1944 01d0 4268 ldr r2, [r0, #4] + 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1945 .loc 1 918 14 view .LVU625 + 1946 01d2 42F48002 orr r2, r2, #4194304 + 1947 01d6 4260 str r2, [r0, #4] + 1948 01d8 A0E7 b .L131 + ARM GAS /tmp/cc5LZY9S.s page 64 + + + 1949 .L139: + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1950 .loc 1 922 52 discriminator 1 view .LVU626 + 1951 01da 0A68 ldr r2, [r1] + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1952 .loc 1 922 32 discriminator 1 view .LVU627 + 1953 01dc 0949 ldr r1, .L140+12 + 1954 .LVL106: + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** { + 1955 .loc 1 922 32 discriminator 1 view .LVU628 + 1956 01de 112A cmp r2, #17 + 1957 01e0 18BF it ne + 1958 01e2 8A42 cmpne r2, r1 + 1959 01e4 9ED1 bne .L132 + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1960 .loc 1 925 5 is_stmt 1 view .LVU629 + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1961 .loc 1 925 8 is_stmt 0 view .LVU630 + 1962 01e6 0649 ldr r1, .L140+8 + 1963 01e8 4A68 ldr r2, [r1, #4] + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 1964 .loc 1 925 14 view .LVU631 + 1965 01ea 42F40002 orr r2, r2, #8388608 + 1966 01ee 4A60 str r2, [r1, #4] + 1967 01f0 98E7 b .L132 + 1968 .LVL107: + 1969 .L133: + 1970 .LCFI22: + 1971 .cfi_def_cfa_offset 0 + 1972 .cfi_restore 4 + 1973 .cfi_restore 5 + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1974 .loc 1 814 3 discriminator 1 view .LVU632 + 1975 01f2 0220 movs r0, #2 + 1976 .LVL108: + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 1977 .loc 1 933 1 view .LVU633 + 1978 01f4 7047 bx lr + 1979 .L141: + 1980 01f6 00BF .align 2 + 1981 .L140: + 1982 01f8 01000F00 .word 983041 + 1983 01fc 00200140 .word 1073815552 + 1984 0200 00230140 .word 1073816320 + 1985 0204 12000010 .word 268435474 + 1986 .cfi_endproc + 1987 .LFE151: + 1989 .section .text.HAL_ADCEx_MultiModeConfigChannel,"ax",%progbits + 1990 .align 1 + 1991 .global HAL_ADCEx_MultiModeConfigChannel + 1992 .syntax unified + 1993 .thumb + 1994 .thumb_func + 1996 HAL_ADCEx_MultiModeConfigChannel: + 1997 .LVL109: + 1998 .LFB152: + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check the parameters */ + ARM GAS /tmp/cc5LZY9S.s page 65 + + + 1999 .loc 1 944 1 is_stmt 1 view -0 + 2000 .cfi_startproc + 2001 @ args = 0, pretend = 0, frame = 0 + 2002 @ frame_needed = 0, uses_anonymous_args = 0 + 2003 @ link register save eliminated. + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode)); + 2004 .loc 1 946 3 view .LVU635 + 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); + 2005 .loc 1 947 3 view .LVU636 + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2006 .loc 1 948 3 view .LVU637 + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2007 .loc 1 951 3 view .LVU638 + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2008 .loc 1 951 3 view .LVU639 + 2009 0000 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 2010 0004 012B cmp r3, #1 + 2011 0006 23D0 beq .L144 + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** /* Check the parameters */ + 2012 .loc 1 944 1 is_stmt 0 view .LVU640 + 2013 0008 10B4 push {r4} + 2014 .LCFI23: + 2015 .cfi_def_cfa_offset 4 + 2016 .cfi_offset 4, -4 + 2017 000a 0246 mov r2, r0 + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2018 .loc 1 951 3 is_stmt 1 discriminator 2 view .LVU641 + 2019 000c 0123 movs r3, #1 + 2020 000e 80F83C30 strb r3, [r0, #60] + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2021 .loc 1 951 3 discriminator 2 view .LVU642 + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR |= multimode->Mode; + 2022 .loc 1 954 3 view .LVU643 + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR |= multimode->Mode; + 2023 .loc 1 954 6 is_stmt 0 view .LVU644 + 2024 0012 104B ldr r3, .L149 + 2025 0014 5868 ldr r0, [r3, #4] + 2026 .LVL110: + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR |= multimode->Mode; + 2027 .loc 1 954 12 view .LVU645 + 2028 0016 20F01F00 bic r0, r0, #31 + 2029 001a 5860 str r0, [r3, #4] + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2030 .loc 1 955 3 is_stmt 1 view .LVU646 + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2031 .loc 1 955 6 is_stmt 0 view .LVU647 + 2032 001c 5868 ldr r0, [r3, #4] + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2033 .loc 1 955 12 view .LVU648 + 2034 001e 0C68 ldr r4, [r1] + 2035 0020 2043 orrs r0, r0, r4 + 2036 0022 5860 str r0, [r3, #4] + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR |= multimode->DMAAccessMode; + 2037 .loc 1 958 3 is_stmt 1 view .LVU649 + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR |= multimode->DMAAccessMode; + 2038 .loc 1 958 6 is_stmt 0 view .LVU650 + 2039 0024 5868 ldr r0, [r3, #4] + ARM GAS /tmp/cc5LZY9S.s page 66 + + + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR |= multimode->DMAAccessMode; + 2040 .loc 1 958 12 view .LVU651 + 2041 0026 20F44040 bic r0, r0, #49152 + 2042 002a 5860 str r0, [r3, #4] + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2043 .loc 1 959 3 is_stmt 1 view .LVU652 + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2044 .loc 1 959 6 is_stmt 0 view .LVU653 + 2045 002c 5868 ldr r0, [r3, #4] + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2046 .loc 1 959 12 view .LVU654 + 2047 002e 4C68 ldr r4, [r1, #4] + 2048 0030 2043 orrs r0, r0, r4 + 2049 0032 5860 str r0, [r3, #4] + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR |= multimode->TwoSamplingDelay; + 2050 .loc 1 962 3 is_stmt 1 view .LVU655 + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR |= multimode->TwoSamplingDelay; + 2051 .loc 1 962 6 is_stmt 0 view .LVU656 + 2052 0034 5868 ldr r0, [r3, #4] + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** ADC->CCR |= multimode->TwoSamplingDelay; + 2053 .loc 1 962 12 view .LVU657 + 2054 0036 20F47060 bic r0, r0, #3840 + 2055 003a 5860 str r0, [r3, #4] + 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2056 .loc 1 963 3 is_stmt 1 view .LVU658 + 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2057 .loc 1 963 6 is_stmt 0 view .LVU659 + 2058 003c 5868 ldr r0, [r3, #4] + 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2059 .loc 1 963 24 view .LVU660 + 2060 003e 8968 ldr r1, [r1, #8] + 2061 .LVL111: + 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2062 .loc 1 963 12 view .LVU661 + 2063 0040 0143 orrs r1, r1, r0 + 2064 0042 5960 str r1, [r3, #4] + 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2065 .loc 1 966 3 is_stmt 1 view .LVU662 + 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2066 .loc 1 966 3 view .LVU663 + 2067 0044 0020 movs r0, #0 + 2068 0046 82F83C00 strb r0, [r2, #60] + 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2069 .loc 1 966 3 view .LVU664 + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** } + 2070 .loc 1 969 3 view .LVU665 + 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2071 .loc 1 970 1 is_stmt 0 view .LVU666 + 2072 004a 5DF8044B ldr r4, [sp], #4 + 2073 .LCFI24: + 2074 .cfi_restore 4 + 2075 .cfi_def_cfa_offset 0 + 2076 004e 7047 bx lr + 2077 .LVL112: + 2078 .L144: + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2079 .loc 1 951 3 discriminator 1 view .LVU667 + ARM GAS /tmp/cc5LZY9S.s page 67 + + + 2080 0050 0220 movs r0, #2 + 2081 .LVL113: + 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c **** + 2082 .loc 1 970 1 view .LVU668 + 2083 0052 7047 bx lr + 2084 .L150: + 2085 .align 2 + 2086 .L149: + 2087 0054 00230140 .word 1073816320 + 2088 .cfi_endproc + 2089 .LFE152: + 2091 .text + 2092 .Letext0: + 2093 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 2094 .file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 2095 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + 2096 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 2097 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h" + 2098 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h" + 2099 .file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h" + 2100 .file 9 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h" + 2101 .file 10 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h" + ARM GAS /tmp/cc5LZY9S.s page 68 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_adc_ex.c + /tmp/cc5LZY9S.s:20 .text.ADC_MultiModeDMAError:00000000 $t + /tmp/cc5LZY9S.s:25 .text.ADC_MultiModeDMAError:00000000 ADC_MultiModeDMAError + /tmp/cc5LZY9S.s:61 .text.ADC_MultiModeDMAHalfConvCplt:00000000 $t + /tmp/cc5LZY9S.s:66 .text.ADC_MultiModeDMAHalfConvCplt:00000000 ADC_MultiModeDMAHalfConvCplt + /tmp/cc5LZY9S.s:93 .text.ADC_MultiModeDMAConvCplt:00000000 $t + /tmp/cc5LZY9S.s:98 .text.ADC_MultiModeDMAConvCplt:00000000 ADC_MultiModeDMAConvCplt + /tmp/cc5LZY9S.s:192 .text.HAL_ADCEx_InjectedStart:00000000 $t + /tmp/cc5LZY9S.s:198 .text.HAL_ADCEx_InjectedStart:00000000 HAL_ADCEx_InjectedStart + /tmp/cc5LZY9S.s:412 .text.HAL_ADCEx_InjectedStart:000000e8 $d + /tmp/cc5LZY9S.s:421 .text.HAL_ADCEx_InjectedStart_IT:00000000 $t + /tmp/cc5LZY9S.s:427 .text.HAL_ADCEx_InjectedStart_IT:00000000 HAL_ADCEx_InjectedStart_IT + /tmp/cc5LZY9S.s:646 .text.HAL_ADCEx_InjectedStart_IT:000000f0 $d + /tmp/cc5LZY9S.s:655 .text.HAL_ADCEx_InjectedStop:00000000 $t + /tmp/cc5LZY9S.s:661 .text.HAL_ADCEx_InjectedStop:00000000 HAL_ADCEx_InjectedStop + /tmp/cc5LZY9S.s:754 .text.HAL_ADCEx_InjectedStop:00000060 $d + /tmp/cc5LZY9S.s:759 .text.HAL_ADCEx_InjectedPollForConversion:00000000 $t + /tmp/cc5LZY9S.s:765 .text.HAL_ADCEx_InjectedPollForConversion:00000000 HAL_ADCEx_InjectedPollForConversion + /tmp/cc5LZY9S.s:923 .text.HAL_ADCEx_InjectedStop_IT:00000000 $t + /tmp/cc5LZY9S.s:929 .text.HAL_ADCEx_InjectedStop_IT:00000000 HAL_ADCEx_InjectedStop_IT + /tmp/cc5LZY9S.s:1026 .text.HAL_ADCEx_InjectedStop_IT:00000068 $d + /tmp/cc5LZY9S.s:1031 .text.HAL_ADCEx_InjectedGetValue:00000000 $t + /tmp/cc5LZY9S.s:1037 .text.HAL_ADCEx_InjectedGetValue:00000000 HAL_ADCEx_InjectedGetValue + /tmp/cc5LZY9S.s:1066 .text.HAL_ADCEx_InjectedGetValue:00000018 $d + /tmp/cc5LZY9S.s:1070 .text.HAL_ADCEx_InjectedGetValue:0000001c $t + /tmp/cc5LZY9S.s:1129 .text.HAL_ADCEx_MultiModeStart_DMA:00000000 $t + /tmp/cc5LZY9S.s:1135 .text.HAL_ADCEx_MultiModeStart_DMA:00000000 HAL_ADCEx_MultiModeStart_DMA + /tmp/cc5LZY9S.s:1371 .text.HAL_ADCEx_MultiModeStart_DMA:00000110 $d + /tmp/cc5LZY9S.s:1383 .text.HAL_ADCEx_MultiModeStop_DMA:00000000 $t + /tmp/cc5LZY9S.s:1389 .text.HAL_ADCEx_MultiModeStop_DMA:00000000 HAL_ADCEx_MultiModeStop_DMA + /tmp/cc5LZY9S.s:1480 .text.HAL_ADCEx_MultiModeStop_DMA:0000005c $d + /tmp/cc5LZY9S.s:1486 .text.HAL_ADCEx_MultiModeGetValue:00000000 $t + /tmp/cc5LZY9S.s:1492 .text.HAL_ADCEx_MultiModeGetValue:00000000 HAL_ADCEx_MultiModeGetValue + /tmp/cc5LZY9S.s:1511 .text.HAL_ADCEx_MultiModeGetValue:00000008 $d + /tmp/cc5LZY9S.s:1516 .text.HAL_ADCEx_InjectedConvCpltCallback:00000000 $t + /tmp/cc5LZY9S.s:1522 .text.HAL_ADCEx_InjectedConvCpltCallback:00000000 HAL_ADCEx_InjectedConvCpltCallback + /tmp/cc5LZY9S.s:1537 .text.HAL_ADCEx_InjectedConfigChannel:00000000 $t + /tmp/cc5LZY9S.s:1543 .text.HAL_ADCEx_InjectedConfigChannel:00000000 HAL_ADCEx_InjectedConfigChannel + /tmp/cc5LZY9S.s:1982 .text.HAL_ADCEx_InjectedConfigChannel:000001f8 $d + /tmp/cc5LZY9S.s:1990 .text.HAL_ADCEx_MultiModeConfigChannel:00000000 $t + /tmp/cc5LZY9S.s:1996 .text.HAL_ADCEx_MultiModeConfigChannel:00000000 HAL_ADCEx_MultiModeConfigChannel + /tmp/cc5LZY9S.s:2087 .text.HAL_ADCEx_MultiModeConfigChannel:00000054 $d + +UNDEFINED SYMBOLS +HAL_ADC_ErrorCallback +HAL_ADC_ConvHalfCpltCallback +HAL_ADC_ConvCpltCallback +SystemCoreClock +HAL_GetTick +HAL_DMA_Start_IT +HAL_DMA_Abort diff --git a/build/stm32f7xx_hal_adc_ex.o b/build/stm32f7xx_hal_adc_ex.o new file mode 100644 index 0000000000000000000000000000000000000000..3da64659959396a16f4928b2fbda6a0b0c40e0bc GIT binary patch literal 25984 zcmc(n33wdEwePFDXGSxUY{`;k%d)V?lEAXT+H8aE$hM^MDqFTJiChyP(nvG%2#=O% zF^0fJnB_tsiNTOKkOYS%`vb!E0tt`61;P@76$peS;4I*TaCr(5TOjcM|LW5-J!2Ve z?)|=Z`%}-aGt=+uNFbw5vhALM{NvY<~>Jsk~jdE3?7AgOoqdV(L ztw<;y8uwVC$Vcyd_>uo!YMrACb{56+#+!4F8!L)8OsK)4NKx#H*tGGw_E}?J>$&^x zu`{Mk4CGh`p_>@(&l%emn>QXbwsjQ6OD0BX9nYH>ZMRr^+%StGh3jn3*Y12FzJLAS z4=c6jR#j^3+xu>9m2rIZpiw%CBP(`IEN|S%$sfBW#(LLuRBf6at7^RdeXI1^Z0j!} z%h+cgGOjf~W$ZJqRmZRc(esQkRT_#Y?YSTQ z%_+HGe30P*kv))wJz&W!Qw-V!7Y+@9Vsi6Omh5Y4Ob{-AnQ3cIg2iBXx_YbS!d)VJOtnOplFL-Ho z=))&J`UpL)Q$eH7-S;z&+V>jtz2-mB_f_cof=}$b8EcJ&#z(Ez|6&&M{ySNiBnQ?y zjD65pIRBtgg0T;poH6GWU_`g+Ih8wh1?H4tT+w01uGF(4cg%=qHfGjwW|+ve=MZOC z5VOk&s*(%fV_-e=Zj$$X_{K*c4czHjH$~4p-@4LR5xjVE3dZjI>qo2KIe7ZrrLozV z4W698j(JK;F;6b!3=GyB;!GW#{oRIFp8Jo({o~nYQAcS!G@)8cBc+_56LoXvj$N~p zv<^}p?VmOF8O@nv*TQ36d%@TZJwLd+G+v6?h+29!=8VD1xM88CpgN?21NW-n2bd!` z7lQ9%e;fM*&I>0m$EW0FRw6IcU3uXdY2-}TXWuB!zJE49_B^y=I6KfwW4X1!_nVjh zWQ^x#`%No$Z5(IWe$Hqsb}EkFJ#58hgA?EjJB@wghpXHa`9?P>2de+Hk z#`eZ?^_jdkRyS^_y&cOMb7RXen^kZ$Tm7X@8GCUi?>CkidyW07{JpVYY>yu0rh~`E zD;pQq;Vc_0i8ScEdJmRhU8!qxwoW&}*I^S&ZClz4DAU z@cf>3NR@O(o;;ij`x0&c>S2yyF2=A+k7XCe(z>)yO{)EoO#?8@8BzciS0R%DcU z{%*b*e9bgp>o^Ab%VU|B*dc?Fh1NBms}?rGnxn{3&4j$ckuj=R(-*EgXf51&&{(*A40b*Jf6Fo(!aVv# ztR%#vnQf1?L9h*J>j1~`+(Ly0PO=>`#|_sXw5SivDwKZMr?N8bT~7XxA5Cz z*?R7dnhhNXpb2c8wy^NNFEo5}%(thK<9j45^ z+)dkK!ST6jd&l-zb}SeogA;Xi;Ede)$>lTl|u^^^~)C9}Q&mFFz#JsCdey&i8*->~xiJ6Z`WpT-iy z$Y{164m=MZ{?-;{Ju>Yg+LtPSsHIw2kBaDlSfi}RMDzy~TYg-`?0}ErFGS1@oa%x2 zgox7vVT!*Lu`sZM;*%m42g(qvbx_2he?uF>7!$F~znS8%L@W&Lhv)jh{fuISt8Exvgv4l#wX9-gt&ZBPdZheF)W1);4H7H(9J>`aO%_ zP#k&Z8@ZTeIc0cJIj>+?jhr|R&73f7Ees>);0e~BAvslQjFVVpRe)7)L`u-W$!N#B z)G9_nMwPEBU_c!>3(@&%vh{2(Re=@o;ae)ACoqC4zU3nN1IM6kU#*DQfmUS2w_3#9 z!2NLSYY=gIpb0(jtrf8_aDc{*A{GZ;q^l+ogMsBVZV|C8a30$|S;X?dh3JOwR1r^5 zRtb9L>o7xTP&(}EHtNuwoLdmT$_e4c$hjF^GjqPcq03na51yPeQNgRMFSF0R<`h)$ zu-3Hu5KM>f(%fnk1X@{o*<2pud<|@&_{BL)mRafvyv4}AJcrpeOP2)JGwv(qY}Tbq z18=Z&-`taQ-DQE(8TZxmHfgaoV6pV8BGv^OD1J@EHGxhxbghUR0x!X(?;9d+4s4>U z>qKl0T!!|2-)|fxFqzXT`WI@GlfQMJx~W zAuSnEsf(F0%*tn&r=wRH8!{dUT*IDlL^B>L;juHK89$%LPI5%QNso`ty9nTjUdmV> zFFBw~m+A4&cw(MC-nDwXGoBRVIz0>-VYAdIB{_kbk#`SZG^W ze73n2m1Y=!gy8#EGheS%#t)$@U|B<;lqj2N z^x-(;JZdKr+8IVQr}()}3&$XFx`hJH`Q(c#H1=b5Wj>W@u)vtr3&|+-OhIkL$ro(K z=TW`r({|B`473c|AokfCQDPK%3K?e;6q~RYPsa-*RI|9o8d>5l6Pga}#$yS0S)P@2 zcOkT+*ll-HYeSpxuwX=v;Q`7ORUE ze}Lk**fBz!5p#^|(7KWDa_EP30c+fuaF}ncqr)h)r(iD{XI}HIZdyD5#gDPWA?N>G z<3@NlOzANT%yX6TDlCIKIMWKzm(i@|8JE!XZ>BwxuvFP%J{yU*`|>w)In8Hc_T^(o zz%$wSgECE6DS~|!%8dR*tq08p*4hQ_8Q5pXSp2YAz^m+2*dN7ST!(sB!U{g|qKr*0 zpH)y5u%V9<@F=vWU@v;kuG313C!x5X$_7rZO=cITW)p^rCwR&I9J40VzBjod zUiugcIq}PkZQg7?!<88=fxlUA84KR2;tgz`zV)1AT*#p*bfu>bh4<1~N0yVHLUS2= z`aZO8VK3r(gF5ROKsD+w!hY;~;=cG;|Ihh2nnfNL@BP?Q?m$4QhpoMlnXy9>je{BVCnY4`MH>!L&e~QyAnrC>pTO zZo!LjwV{`vGjJTiUX0u-t^~y^@fBvoBDuS^vdC%oMvIY)K{Cr!R@N#gamkvYtf?!qK9#jRYhymr zuv8IVF+c}>OI!x4vulxujC><2%dTU<*gr*Ce#gZ!1RH=N;ggC?so-6n#R^$c0piAd zmS;*UwzD~@0d34rX=-k2sV>WuFoG#z zAkp(ujm4E?UXl_a%u5j-CJ@6b`vM|0Gp}fX`dHX;!0nzuaa_W!WG5xU`4WYmV$$() z_pCDEVnK?+&e+1Ey5-EqrmrRHTuol*O?572Z0d%yOc|<~ph>2}va0m5dR@|xrRXFL zlgd>8i1CyB(_}LLyqGXlwqmM*WhBn+k87<{n;zL4s8yR?mG}&HcZ-zy9EyGr^x`gt z=-L*URRr;`vsI|3(Jt%DiCl+i8x}7W(^ue{!tEsB4OL}jn_c~FN zw)^H}s8y~rnYHckNu~f@$tHbB7>)}`zkQrd^2UyOm`u9OffijLcsF3EHi9+Xz0tBR zZq5X<(~2pxA=I9<5v_bsx3rCTR3Ekwhp@W`p0XXtwv<5RtY9E)4fDcj)Lk2ukFxop z#~Di4t+%GMZrW?+Arwz&%T^+h1}RRq-kQ?76r)CBbC1(;&|(byq&)-9)vOaekhYaU z#;6di;2sLfb=Xmi*OV<65)wnyVYk%hjFhcdtdq7R#ixUI#j-VFIT-GszR!C6nzt*NT7OS;z|uCq2xfW*eCNE>#gc$1A|b}eNK zKtdM?noKeQZHsM5i<2D(oJNMiy^H-AhSsy?7#?|Odt{_X-5O8=YhsN)Y$bT*fR7bZKKtvJ$~JB6E}VSY&a`c!>g(tR`Cv-ZcO@b|j>TtE3o`&g5w z8D}R{AG_U%Qgn*=Hg@-%q~eJ%7F; zHYB|#y-~VDN=bV6tIvHxTWs@nZRtcsNw0^Ax=-1ijg9^Uz}}@H#_|GKHN&df>(h!!2S%uV*}ri(Dt)!<{{q)r%`?Dyl1c`nuvHk*IQ9g_>G7wpOl* z?&|4^!f(=b<;FD2NgIWcQbWVNi)*?WPAnX64@bJ%qq{4*FyB!U!KbYiF(zEBPJ|s4 zc-t;fElt#3BGGQBF(VRIwz@YwnHp^#Ma@ubKW7aMM|;~7?x1zYK<~Dp@*2vk=Y_T3 zZ}<$a*Ei3LyHCwr%_?sIEC@oi(rfrCO#`Eptah1GZMrY$HPTC;$)HoqSK^(aS?bLI zVd?d)Zt?nYoKfM;U+Gqwo1EvJrkkuRz#!z-b~*XuQAVSY1^C66XQ&4Oa+5MlV?wITqgcM zrQy{7={)=(nTMx!9py^3zbDw3mxw62U<1;GIdZ{;H=&2Xr zR9lVdU|`~4qM(G+C#wP?PmwHNl~J4T&BI}_9_HN@-i17<@D>ti)@S9^;^eWXrZ*#T z@?_Yj%_^Qketn#`%3CuR?Uij#PTy7N!PW{+qs+P8X>mU@@;+V4p{U#n*{;XKdqona>-=*{9Vlz1(C*rT(L&~Y~PSEQ9^lzxIDZJl^r+Fi+Y zf@v+y&$p+@b|l)Yo$+5>D&p>3d(TKpSU9Y#M$REFsO9WcwLUx{dANXwOPfA}^~dn~ zE6~wW-RE3R8!J%jtH9)$g0h)N5tcBd-tf-mA~U6ySy@+MmDajy#RmS$xYuNrtm*JSBW>*Vv0zrd-e!5d)4kRV z9dP${3D_#);%Fi`o>Z7mJn5MB{GfMk&^vqBt(XHvH@lO~gd5&zL2n@^#7ajhhJt5t zy<2e)6#7J_J%*r=ilur$cyV!Bo5i;EHGyqosI|f#cqmefkJk!Bf@LBRxZBq9tvPzZ zEM~<%b$HptRSuV*3^XoMr6?-xbBQY;GGqBddNH&QUE}%H^D3N9FlF88DccT(HLupO zN$rW2Fx^v1Q)Nuo>_#WHqeNQz-z@ho#xyW|W!@mEC!{k;mr%1s3Y=2=3V9h@bZDYN#L3{Fh07n7VO1^O((T;dGkDxJ+FuTCC*oE8&Ln^!vnVF%J%i#YOw zriCzg8(hC8w03uU(@1={r>Q>@Z5<8|4!5sqs#i@__{JCx+Bf#~47Z&%5M2}PR&8hY zw}yKM;yryk)euG%`3C?Hi^W z+`{+t_qBxkb{^4!3dQ@ob~X=2hq}V?=%5;)7lluKtNBvnYKu)sYhAJMpxWLY9o!I( zcZUYz!=Z3I-Wl%NsgRRoMvwxwPJ?7`b(S`^>FQ0@DV3R#&4|WHneHN+UAsm1yE!`8 zGZ5nwKvT50VPtT~cAGX1>!ZV;4#!9AyxCLFW;Jy09_F)~j(`@VT zU^Lv@5FU!wM94RW#WcE_2Hzgr#IR^f>G)jL@XE%)!G&A zV?>-hYTZbm)`sJlN5gjTZ5x}`Zauk8CBlz|`}(4B)ypZ@%UUVppPZ9U1$#;&+39nQ zUpQ>l&nKb&!Kj`BDKkSmU~ESWs2*`=P>-C0cJ4OzMWVZPqgyv6qIYIL6QPD;{e#27 zl<-rgjx!dRgF1~vNXp1iT0iO=wzjmXwS$BGgCSGqnQp|1YE;hw&c{*j?XhA|uK zySgx(I^UQ-0+fLHzI}vNbxqWUS1NKR!)@}{8M&mN1$suqp3;hFn zRY;aOaq8hwEzzO=_=uhnu}E)NHEvypZvpeQM!zmTVhnVTRb%V67CF( zsXX4iHMD8%8r8T4E}7s^e{XMpU%S&qE>au9eUW(7(ZF(vJ~!>OI_EXh*xj?kiCncd zHNzucYjiuQ=UH=qJid;DlE@Nbh50sE<7IIonOnQNhoa1F4_`3IeO*!2vX;}6%S%)B z5erO6&Vj_#(Q6UA%D!*_6J4?A7}t+Pv0iHRTH4h=(ucKnlHgm1F<>}nm@d1&I9b_! zCq?vT_ct-fc6OZDFt@l!aR`^#Bg7f$%7%ErX!PwmqKEFnl;zP5D0xLm#^DUh$1i;t zKPSR=ovqZ7=UTY925aHEjqA4RbA%17ZE4xsGWpt|FHYz}`iWLQGTiS(#2(t$kVyYX zXB_JsoVUfWs>b@`5v9jV>BfdJWibJ8rm>%?p*bl@os(PE;A`s18LSWO^(QgE*KavF z7^*%gXulT~tf{J5TwPVQJh-U0YhYw$7tZVG?nS*PK^~5c^mc;X(032)TDmAweImtp ze|UHi-p*QyOI`$u@L*SLCEn=Tby9Ru@A2IO6_J79q8<2)oEaYMUQ`oYv=vf!1Xs~T zL-wjL1i4$5_k>Puj`r;sj;R>lNm5PKxM8rbZmElslSX~%o_twjZuHdGbKALOG!ORl z5B3b7r8ug~FsMgP7S3}n3|M8>;FPS4_4h_AyQ7hCWz)vyw#t@pq^G|*)<4|e*VEPB zI?_259qbNwMcW6%k?>&U`eBL}8-Xd!g zPjtP+Ca%iVq|AKOPtLQJ=;ubFL&LZ#>)QeQK0vJxg;oU1tCz0OLp>OcS1+nrkUs8s z$CYo$euNG0N1ZbjUniRGdKZ>&!q!jqUtoU8NYV36;mP!!E`6cP58pI~y}2`Us;bAE ztL`$sk<79IDRbT+X7vbmw=F+3tDl;Cq30s&V#egQji=exX!)U4 zXk7#^^-~MY^E0PrBQSScY`?DRkYo~fHG&*5|t-cyBVZK?6@3P_0d(zrPP0BYVqbXo!`t$IW^a5k1 zRcOpIii~1oj!}Ysq;GDONB#99cR6m<-6Gz8W#q{Xzm7->II{5euRACFfM7QC^uoDe zx;`*~2zy_ey-%@AwC9{L^(R_5kj=t}5vl(D^7*FyNwA4>_h!LMs(q%~0Rw)fWpB>M z6}Dtylv3@pwf(qbo-&Gze`=cjRBhjpu-C(skSzR$E7d=K)8*PMH7%`tn)Vk<*i1_t z@xW4fY4&;AKG}v{UYw|vmpHQP=cm=r*Y$G~!_Kd2B{xeIq}dl}`_mF81&JdbSZZdP z{Y-729Hp6Q_JwKo$)4E$W~G(S(*E8}#5*g^Us0NUk+$cD|Mpho9B5j4wkB1U;!l;5 zo2BL?1squ_m?oE`$?mh9_Q$1_m#4`*i<6tB7OFFnqT*K$M$_bPq{(+dW;(cr=3)Nx zQ(k9deSXl#a;~F!n9uKt%=Ie|^Ob$IBwl9YK5QO_g)2Ma%#Et?6WU7rd2A zf5tqD9dEZME5Z%Rk?JEKE@1mSNoiZ}R{x)CcM!UXQBj5iy3170N zUyv&*$(7AqimwEdXygRZFBYy4)(bZXw+gxD(NCw4*Fnl7!n1{66n;(kqVO-mzY7D5 zANBbo8*;v|P1q$I6rL~KE4)s4v+!Qw3&J@#ujw}=>=F(M`TGHu^EZj)W5R>NXN9i_ z-xYo+^x)Qo^)iLig#48l_0_^0zC z#ljL{xv)aGM7Tm&FKiLE3;TrU3NII4EBwCjZs8-sXN9i{-x7N8TNB2aFDwzZ2zLl~ z2`>^}CA>j+n~=ZepudB{mxXT#{~^rAiAB3&A%9pyxlXuM_*r4E@EqY~!tV%wDtuh{ zyztM$cZC@^H`&e%;jzLc!ZpHEgfZcn!haL;H!$>bv+yzDA>rG?xwt8!-6G+MByzAq zxQfKdzCp^{MBXkuUGzO7_X-C|_&G<)FCwvDD*Pe|zh5QM{tY63NBBe0|5)Uo3hyVe zKTe|F(OG+kYd`yyN1`7ygvW@UKTN{!XjO%y;A;lkq-!O68(=vzEgOQ=pPpOG2xSx7U$AY!}6NqLRP zCkj6$`t>4j5_XEdpTxy*NH{9`%SrY}c(v%iCGt(eABz5NawdM$C%j+EAD8lHMSeke zNc69ZJT81o^agHN*}hkpNy2}=a1M!l98cm+lS(0f=0*Jm67@F=w~79Ak;B56=!Z$% zBEtmk19CZxsGOc#H5Z;XT6pg%1h& zqh_{uSonsJznY=mn?a1faGvm3;UZzRaJg`$aIJ8oFe>a34hV;Z zpBJ7d{IYPL@EYMag*OXt6Y}TfjQ1(w^Fsay5$azN{#p2*@E<~b-wZoH?`Oe6VX?4O zIA6$LuG5bH<$~NUyj^&Y z@c#%O5Ad5g%W2|I)_p?;o$-Pt1ltMFps7lhvz-YmRJ zc#rTA;V*A9{}h7p zEf7`*pEp8zSrH8pyYZe7o=`!uy0z2*-ra z34bemMfhjoJHq#cSk~~5`Y^5})_8s*!~1Dmdh~s3If*!`NR0n766bXtiS=m%iS@LZ z#QM(n>3JRNAWM~sk;mbFm0W=58S;4ha}M4&a$~!=oNA(J-M)SGwm?zb(9+q_mgmbqsZSS5%14Levm}m2St9GMEtLdJWd8N&ddwi zn@*xXCx~1{qF?-HO)Re?(Z9_iHQa;8##o zMJK+#Sb?uYR8U!w{&|r75z^7iQ$9>Ox|#FIg{!6HXA{n67y1*GPqyG^L3Xf{xxgnv z$uN#IIP$Zhk8|~LO(j03nXI|Q$1TZEi9W$hJ|0SsCgCXAoF1nmd*-A#@!?RqD<{pV zp8%y>B^pdK;|z&JJ4bf3_w;r5WAfPW|(bpqy}Gk zjyfJOMO8%?zJ$oHTi(|Jx{(rfM z_#zyCAEw#yAD{9&1J35;h3|X0+x;=x&4rHRmV@1Cw;YYS+dT+>ag;lo)9!{eyIK^~ zIYyw7!-(-gjQYWPdcd;YgDj)Su~{(h5YR}4F+kF<4;4IH@r1!3p>SekZ@zxio)eD2y# z1KAwA7O`{mqp(|!_h_AsZE@p$i93JqvcFKUzg$zC{(d&i-`z;YbI>`P}AJfqd)HaPspTWcjgLv%@#9V#_~tf;yVDl%UK{B`@!wOwD@)- zzH#UoUpaQCzrThZPVE7x^malm?nNB|bX=1#O>7;oI|L^uK!dMiXn(mNy9R%Wt*##b W{n1s?@rPT|6ua1|c<*i!yZ;9Yh$s>O literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_hal_cortex.d b/build/stm32f7xx_hal_cortex.d new file mode 100644 index 0000000..95a1c86 --- /dev/null +++ b/build/stm32f7xx_hal_cortex.d @@ -0,0 +1,68 @@ +build/stm32f7xx_hal_cortex.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/build/stm32f7xx_hal_cortex.lst b/build/stm32f7xx_hal_cortex.lst new file mode 100644 index 0000000..186ae19 --- /dev/null +++ b/build/stm32f7xx_hal_cortex.lst @@ -0,0 +1,5769 @@ +ARM GAS /tmp/ccB9Q52u.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_hal_cortex.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c" + 19 .section .text.__NVIC_DisableIRQ,"ax",%progbits + 20 .align 1 + 21 .syntax unified + 22 .thumb + 23 .thumb_func + 25 __NVIC_DisableIRQ: + 26 .LVL0: + 27 .LFB106: + 28 .file 2 "Drivers/CMSIS/Include/core_cm7.h" + 1:Drivers/CMSIS/Include/core_cm7.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/core_cm7.h **** * @file core_cm7.h + 3:Drivers/CMSIS/Include/core_cm7.h **** * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + 4:Drivers/CMSIS/Include/core_cm7.h **** * @version V5.0.8 + 5:Drivers/CMSIS/Include/core_cm7.h **** * @date 04. June 2018 + 6:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/core_cm7.h **** /* + 8:Drivers/CMSIS/Include/core_cm7.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/core_cm7.h **** * + 10:Drivers/CMSIS/Include/core_cm7.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/core_cm7.h **** * + 12:Drivers/CMSIS/Include/core_cm7.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/core_cm7.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/core_cm7.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/core_cm7.h **** * + 16:Drivers/CMSIS/Include/core_cm7.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/core_cm7.h **** * + 18:Drivers/CMSIS/Include/core_cm7.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/core_cm7.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/core_cm7.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/core_cm7.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/core_cm7.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/core_cm7.h **** */ + 24:Drivers/CMSIS/Include/core_cm7.h **** + 25:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __ICCARM__ ) + 26:Drivers/CMSIS/Include/core_cm7.h **** #pragma system_include /* treat file as system include file for MISRA check */ + 27:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__clang__) + 28:Drivers/CMSIS/Include/core_cm7.h **** #pragma clang system_header /* treat file as system include file */ + 29:Drivers/CMSIS/Include/core_cm7.h **** #endif + 30:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccB9Q52u.s page 2 + + + 31:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_GENERIC + 32:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_GENERIC + 33:Drivers/CMSIS/Include/core_cm7.h **** + 34:Drivers/CMSIS/Include/core_cm7.h **** #include + 35:Drivers/CMSIS/Include/core_cm7.h **** + 36:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus + 37:Drivers/CMSIS/Include/core_cm7.h **** extern "C" { + 38:Drivers/CMSIS/Include/core_cm7.h **** #endif + 39:Drivers/CMSIS/Include/core_cm7.h **** + 40:Drivers/CMSIS/Include/core_cm7.h **** /** + 41:Drivers/CMSIS/Include/core_cm7.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + 42:Drivers/CMSIS/Include/core_cm7.h **** CMSIS violates the following MISRA-C:2004 rules: + 43:Drivers/CMSIS/Include/core_cm7.h **** + 44:Drivers/CMSIS/Include/core_cm7.h **** \li Required Rule 8.5, object/function definition in header file.
+ 45:Drivers/CMSIS/Include/core_cm7.h **** Function definitions in header files are used to allow 'inlining'. + 46:Drivers/CMSIS/Include/core_cm7.h **** + 47:Drivers/CMSIS/Include/core_cm7.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ 48:Drivers/CMSIS/Include/core_cm7.h **** Unions are used for effective representation of core registers. + 49:Drivers/CMSIS/Include/core_cm7.h **** + 50:Drivers/CMSIS/Include/core_cm7.h **** \li Advisory Rule 19.7, Function-like macro defined.
+ 51:Drivers/CMSIS/Include/core_cm7.h **** Function-like macros are used to allow more efficient code. + 52:Drivers/CMSIS/Include/core_cm7.h **** */ + 53:Drivers/CMSIS/Include/core_cm7.h **** + 54:Drivers/CMSIS/Include/core_cm7.h **** + 55:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* + 56:Drivers/CMSIS/Include/core_cm7.h **** * CMSIS definitions + 57:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ + 58:Drivers/CMSIS/Include/core_cm7.h **** /** + 59:Drivers/CMSIS/Include/core_cm7.h **** \ingroup Cortex_M7 + 60:Drivers/CMSIS/Include/core_cm7.h **** @{ + 61:Drivers/CMSIS/Include/core_cm7.h **** */ + 62:Drivers/CMSIS/Include/core_cm7.h **** + 63:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_version.h" + 64:Drivers/CMSIS/Include/core_cm7.h **** + 65:Drivers/CMSIS/Include/core_cm7.h **** /* CMSIS CM7 definitions */ + 66:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:1 + 67:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0 + 68:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + 69:Drivers/CMSIS/Include/core_cm7.h **** __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS + 70:Drivers/CMSIS/Include/core_cm7.h **** + 71:Drivers/CMSIS/Include/core_cm7.h **** #define __CORTEX_M (7U) /*!< Cortex-M Core */ + 72:Drivers/CMSIS/Include/core_cm7.h **** + 73:Drivers/CMSIS/Include/core_cm7.h **** /** __FPU_USED indicates whether an FPU is used or not. + 74:Drivers/CMSIS/Include/core_cm7.h **** For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun + 75:Drivers/CMSIS/Include/core_cm7.h **** */ + 76:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM ) + 77:Drivers/CMSIS/Include/core_cm7.h **** #if defined __TARGET_FPU_VFP + 78:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 79:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 80:Drivers/CMSIS/Include/core_cm7.h **** #else + 81:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 82:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 83:Drivers/CMSIS/Include/core_cm7.h **** #endif + 84:Drivers/CMSIS/Include/core_cm7.h **** #else + 85:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 86:Drivers/CMSIS/Include/core_cm7.h **** #endif + 87:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccB9Q52u.s page 3 + + + 88:Drivers/CMSIS/Include/core_cm7.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + 89:Drivers/CMSIS/Include/core_cm7.h **** #if defined __ARM_PCS_VFP + 90:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 91:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 92:Drivers/CMSIS/Include/core_cm7.h **** #else + 93:Drivers/CMSIS/Include/core_cm7.h **** #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN + 94:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 95:Drivers/CMSIS/Include/core_cm7.h **** #endif + 96:Drivers/CMSIS/Include/core_cm7.h **** #else + 97:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 98:Drivers/CMSIS/Include/core_cm7.h **** #endif + 99:Drivers/CMSIS/Include/core_cm7.h **** + 100:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __GNUC__ ) + 101:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__) + 102:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 103:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 104:Drivers/CMSIS/Include/core_cm7.h **** #else + 105:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 106:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 107:Drivers/CMSIS/Include/core_cm7.h **** #endif + 108:Drivers/CMSIS/Include/core_cm7.h **** #else + 109:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 110:Drivers/CMSIS/Include/core_cm7.h **** #endif + 111:Drivers/CMSIS/Include/core_cm7.h **** + 112:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __ICCARM__ ) + 113:Drivers/CMSIS/Include/core_cm7.h **** #if defined __ARMVFP__ + 114:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 115:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 116:Drivers/CMSIS/Include/core_cm7.h **** #else + 117:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 118:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 119:Drivers/CMSIS/Include/core_cm7.h **** #endif + 120:Drivers/CMSIS/Include/core_cm7.h **** #else + 121:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 122:Drivers/CMSIS/Include/core_cm7.h **** #endif + 123:Drivers/CMSIS/Include/core_cm7.h **** + 124:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TI_ARM__ ) + 125:Drivers/CMSIS/Include/core_cm7.h **** #if defined __TI_VFP_SUPPORT__ + 126:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 127:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 128:Drivers/CMSIS/Include/core_cm7.h **** #else + 129:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 130:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 131:Drivers/CMSIS/Include/core_cm7.h **** #endif + 132:Drivers/CMSIS/Include/core_cm7.h **** #else + 133:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 134:Drivers/CMSIS/Include/core_cm7.h **** #endif + 135:Drivers/CMSIS/Include/core_cm7.h **** + 136:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __TASKING__ ) + 137:Drivers/CMSIS/Include/core_cm7.h **** #if defined __FPU_VFP__ + 138:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 139:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 140:Drivers/CMSIS/Include/core_cm7.h **** #else + 141:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 142:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 143:Drivers/CMSIS/Include/core_cm7.h **** #endif + 144:Drivers/CMSIS/Include/core_cm7.h **** #else + ARM GAS /tmp/ccB9Q52u.s page 4 + + + 145:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 146:Drivers/CMSIS/Include/core_cm7.h **** #endif + 147:Drivers/CMSIS/Include/core_cm7.h **** + 148:Drivers/CMSIS/Include/core_cm7.h **** #elif defined ( __CSMC__ ) + 149:Drivers/CMSIS/Include/core_cm7.h **** #if ( __CSMC__ & 0x400U) + 150:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 151:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 1U + 152:Drivers/CMSIS/Include/core_cm7.h **** #else + 153:Drivers/CMSIS/Include/core_cm7.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 154:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 155:Drivers/CMSIS/Include/core_cm7.h **** #endif + 156:Drivers/CMSIS/Include/core_cm7.h **** #else + 157:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_USED 0U + 158:Drivers/CMSIS/Include/core_cm7.h **** #endif + 159:Drivers/CMSIS/Include/core_cm7.h **** + 160:Drivers/CMSIS/Include/core_cm7.h **** #endif + 161:Drivers/CMSIS/Include/core_cm7.h **** + 162:Drivers/CMSIS/Include/core_cm7.h **** #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + 163:Drivers/CMSIS/Include/core_cm7.h **** + 164:Drivers/CMSIS/Include/core_cm7.h **** + 165:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus + 166:Drivers/CMSIS/Include/core_cm7.h **** } + 167:Drivers/CMSIS/Include/core_cm7.h **** #endif + 168:Drivers/CMSIS/Include/core_cm7.h **** + 169:Drivers/CMSIS/Include/core_cm7.h **** #endif /* __CORE_CM7_H_GENERIC */ + 170:Drivers/CMSIS/Include/core_cm7.h **** + 171:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CMSIS_GENERIC + 172:Drivers/CMSIS/Include/core_cm7.h **** + 173:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CORE_CM7_H_DEPENDANT + 174:Drivers/CMSIS/Include/core_cm7.h **** #define __CORE_CM7_H_DEPENDANT + 175:Drivers/CMSIS/Include/core_cm7.h **** + 176:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus + 177:Drivers/CMSIS/Include/core_cm7.h **** extern "C" { + 178:Drivers/CMSIS/Include/core_cm7.h **** #endif + 179:Drivers/CMSIS/Include/core_cm7.h **** + 180:Drivers/CMSIS/Include/core_cm7.h **** /* check device defines and use defaults */ + 181:Drivers/CMSIS/Include/core_cm7.h **** #if defined __CHECK_DEVICE_DEFINES + 182:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __CM7_REV + 183:Drivers/CMSIS/Include/core_cm7.h **** #define __CM7_REV 0x0000U + 184:Drivers/CMSIS/Include/core_cm7.h **** #warning "__CM7_REV not defined in device header file; using default!" + 185:Drivers/CMSIS/Include/core_cm7.h **** #endif + 186:Drivers/CMSIS/Include/core_cm7.h **** + 187:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __FPU_PRESENT + 188:Drivers/CMSIS/Include/core_cm7.h **** #define __FPU_PRESENT 0U + 189:Drivers/CMSIS/Include/core_cm7.h **** #warning "__FPU_PRESENT not defined in device header file; using default!" + 190:Drivers/CMSIS/Include/core_cm7.h **** #endif + 191:Drivers/CMSIS/Include/core_cm7.h **** + 192:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __MPU_PRESENT + 193:Drivers/CMSIS/Include/core_cm7.h **** #define __MPU_PRESENT 0U + 194:Drivers/CMSIS/Include/core_cm7.h **** #warning "__MPU_PRESENT not defined in device header file; using default!" + 195:Drivers/CMSIS/Include/core_cm7.h **** #endif + 196:Drivers/CMSIS/Include/core_cm7.h **** + 197:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __ICACHE_PRESENT + 198:Drivers/CMSIS/Include/core_cm7.h **** #define __ICACHE_PRESENT 0U + 199:Drivers/CMSIS/Include/core_cm7.h **** #warning "__ICACHE_PRESENT not defined in device header file; using default!" + 200:Drivers/CMSIS/Include/core_cm7.h **** #endif + 201:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccB9Q52u.s page 5 + + + 202:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __DCACHE_PRESENT + 203:Drivers/CMSIS/Include/core_cm7.h **** #define __DCACHE_PRESENT 0U + 204:Drivers/CMSIS/Include/core_cm7.h **** #warning "__DCACHE_PRESENT not defined in device header file; using default!" + 205:Drivers/CMSIS/Include/core_cm7.h **** #endif + 206:Drivers/CMSIS/Include/core_cm7.h **** + 207:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __DTCM_PRESENT + 208:Drivers/CMSIS/Include/core_cm7.h **** #define __DTCM_PRESENT 0U + 209:Drivers/CMSIS/Include/core_cm7.h **** #warning "__DTCM_PRESENT not defined in device header file; using default!" + 210:Drivers/CMSIS/Include/core_cm7.h **** #endif + 211:Drivers/CMSIS/Include/core_cm7.h **** + 212:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __NVIC_PRIO_BITS + 213:Drivers/CMSIS/Include/core_cm7.h **** #define __NVIC_PRIO_BITS 3U + 214:Drivers/CMSIS/Include/core_cm7.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + 215:Drivers/CMSIS/Include/core_cm7.h **** #endif + 216:Drivers/CMSIS/Include/core_cm7.h **** + 217:Drivers/CMSIS/Include/core_cm7.h **** #ifndef __Vendor_SysTickConfig + 218:Drivers/CMSIS/Include/core_cm7.h **** #define __Vendor_SysTickConfig 0U + 219:Drivers/CMSIS/Include/core_cm7.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + 220:Drivers/CMSIS/Include/core_cm7.h **** #endif + 221:Drivers/CMSIS/Include/core_cm7.h **** #endif + 222:Drivers/CMSIS/Include/core_cm7.h **** + 223:Drivers/CMSIS/Include/core_cm7.h **** /* IO definitions (access restrictions to peripheral registers) */ + 224:Drivers/CMSIS/Include/core_cm7.h **** /** + 225:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines + 226:Drivers/CMSIS/Include/core_cm7.h **** + 227:Drivers/CMSIS/Include/core_cm7.h **** IO Type Qualifiers are used + 228:Drivers/CMSIS/Include/core_cm7.h **** \li to specify the access to peripheral variables. + 229:Drivers/CMSIS/Include/core_cm7.h **** \li for automatic generation of peripheral register debug information. + 230:Drivers/CMSIS/Include/core_cm7.h **** */ + 231:Drivers/CMSIS/Include/core_cm7.h **** #ifdef __cplusplus + 232:Drivers/CMSIS/Include/core_cm7.h **** #define __I volatile /*!< Defines 'read only' permissions */ + 233:Drivers/CMSIS/Include/core_cm7.h **** #else + 234:Drivers/CMSIS/Include/core_cm7.h **** #define __I volatile const /*!< Defines 'read only' permissions */ + 235:Drivers/CMSIS/Include/core_cm7.h **** #endif + 236:Drivers/CMSIS/Include/core_cm7.h **** #define __O volatile /*!< Defines 'write only' permissions */ + 237:Drivers/CMSIS/Include/core_cm7.h **** #define __IO volatile /*!< Defines 'read / write' permissions */ + 238:Drivers/CMSIS/Include/core_cm7.h **** + 239:Drivers/CMSIS/Include/core_cm7.h **** /* following defines should be used for structure members */ + 240:Drivers/CMSIS/Include/core_cm7.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */ + 241:Drivers/CMSIS/Include/core_cm7.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */ + 242:Drivers/CMSIS/Include/core_cm7.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */ + 243:Drivers/CMSIS/Include/core_cm7.h **** + 244:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group Cortex_M7 */ + 245:Drivers/CMSIS/Include/core_cm7.h **** + 246:Drivers/CMSIS/Include/core_cm7.h **** + 247:Drivers/CMSIS/Include/core_cm7.h **** + 248:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* + 249:Drivers/CMSIS/Include/core_cm7.h **** * Register Abstraction + 250:Drivers/CMSIS/Include/core_cm7.h **** Core Register contain: + 251:Drivers/CMSIS/Include/core_cm7.h **** - Core Register + 252:Drivers/CMSIS/Include/core_cm7.h **** - Core NVIC Register + 253:Drivers/CMSIS/Include/core_cm7.h **** - Core SCB Register + 254:Drivers/CMSIS/Include/core_cm7.h **** - Core SysTick Register + 255:Drivers/CMSIS/Include/core_cm7.h **** - Core Debug Register + 256:Drivers/CMSIS/Include/core_cm7.h **** - Core MPU Register + 257:Drivers/CMSIS/Include/core_cm7.h **** - Core FPU Register + 258:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ + ARM GAS /tmp/ccB9Q52u.s page 6 + + + 259:Drivers/CMSIS/Include/core_cm7.h **** /** + 260:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_register Defines and Type Definitions + 261:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions and defines for Cortex-M processor based devices. + 262:Drivers/CMSIS/Include/core_cm7.h **** */ + 263:Drivers/CMSIS/Include/core_cm7.h **** + 264:Drivers/CMSIS/Include/core_cm7.h **** /** + 265:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + 266:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_CORE Status and Control Registers + 267:Drivers/CMSIS/Include/core_cm7.h **** \brief Core Register type definitions. + 268:Drivers/CMSIS/Include/core_cm7.h **** @{ + 269:Drivers/CMSIS/Include/core_cm7.h **** */ + 270:Drivers/CMSIS/Include/core_cm7.h **** + 271:Drivers/CMSIS/Include/core_cm7.h **** /** + 272:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Application Program Status Register (APSR). + 273:Drivers/CMSIS/Include/core_cm7.h **** */ + 274:Drivers/CMSIS/Include/core_cm7.h **** typedef union + 275:Drivers/CMSIS/Include/core_cm7.h **** { + 276:Drivers/CMSIS/Include/core_cm7.h **** struct + 277:Drivers/CMSIS/Include/core_cm7.h **** { + 278:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + 279:Drivers/CMSIS/Include/core_cm7.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + 280:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + 281:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + 282:Drivers/CMSIS/Include/core_cm7.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + 283:Drivers/CMSIS/Include/core_cm7.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + 284:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + 285:Drivers/CMSIS/Include/core_cm7.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + 286:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ + 287:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ + 288:Drivers/CMSIS/Include/core_cm7.h **** } APSR_Type; + 289:Drivers/CMSIS/Include/core_cm7.h **** + 290:Drivers/CMSIS/Include/core_cm7.h **** /* APSR Register Definitions */ + 291:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Pos 31U /*!< APSR + 292:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR + 293:Drivers/CMSIS/Include/core_cm7.h **** + 294:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Pos 30U /*!< APSR + 295:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR + 296:Drivers/CMSIS/Include/core_cm7.h **** + 297:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Pos 29U /*!< APSR + 298:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR + 299:Drivers/CMSIS/Include/core_cm7.h **** + 300:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Pos 28U /*!< APSR + 301:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR + 302:Drivers/CMSIS/Include/core_cm7.h **** + 303:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Pos 27U /*!< APSR + 304:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR + 305:Drivers/CMSIS/Include/core_cm7.h **** + 306:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Pos 16U /*!< APSR + 307:Drivers/CMSIS/Include/core_cm7.h **** #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR + 308:Drivers/CMSIS/Include/core_cm7.h **** + 309:Drivers/CMSIS/Include/core_cm7.h **** + 310:Drivers/CMSIS/Include/core_cm7.h **** /** + 311:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Interrupt Program Status Register (IPSR). + 312:Drivers/CMSIS/Include/core_cm7.h **** */ + 313:Drivers/CMSIS/Include/core_cm7.h **** typedef union + 314:Drivers/CMSIS/Include/core_cm7.h **** { + 315:Drivers/CMSIS/Include/core_cm7.h **** struct + ARM GAS /tmp/ccB9Q52u.s page 7 + + + 316:Drivers/CMSIS/Include/core_cm7.h **** { + 317:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + 318:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + 319:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ + 320:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ + 321:Drivers/CMSIS/Include/core_cm7.h **** } IPSR_Type; + 322:Drivers/CMSIS/Include/core_cm7.h **** + 323:Drivers/CMSIS/Include/core_cm7.h **** /* IPSR Register Definitions */ + 324:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Pos 0U /*!< IPSR + 325:Drivers/CMSIS/Include/core_cm7.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR + 326:Drivers/CMSIS/Include/core_cm7.h **** + 327:Drivers/CMSIS/Include/core_cm7.h **** + 328:Drivers/CMSIS/Include/core_cm7.h **** /** + 329:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + 330:Drivers/CMSIS/Include/core_cm7.h **** */ + 331:Drivers/CMSIS/Include/core_cm7.h **** typedef union + 332:Drivers/CMSIS/Include/core_cm7.h **** { + 333:Drivers/CMSIS/Include/core_cm7.h **** struct + 334:Drivers/CMSIS/Include/core_cm7.h **** { + 335:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + 336:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + 337:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + 338:Drivers/CMSIS/Include/core_cm7.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + 339:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + 340:Drivers/CMSIS/Include/core_cm7.h **** uint32_t T:1; /*!< bit: 24 Thumb bit */ + 341:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + 342:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + 343:Drivers/CMSIS/Include/core_cm7.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + 344:Drivers/CMSIS/Include/core_cm7.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + 345:Drivers/CMSIS/Include/core_cm7.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + 346:Drivers/CMSIS/Include/core_cm7.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + 347:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ + 348:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ + 349:Drivers/CMSIS/Include/core_cm7.h **** } xPSR_Type; + 350:Drivers/CMSIS/Include/core_cm7.h **** + 351:Drivers/CMSIS/Include/core_cm7.h **** /* xPSR Register Definitions */ + 352:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Pos 31U /*!< xPSR + 353:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR + 354:Drivers/CMSIS/Include/core_cm7.h **** + 355:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Pos 30U /*!< xPSR + 356:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR + 357:Drivers/CMSIS/Include/core_cm7.h **** + 358:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Pos 29U /*!< xPSR + 359:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR + 360:Drivers/CMSIS/Include/core_cm7.h **** + 361:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Pos 28U /*!< xPSR + 362:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR + 363:Drivers/CMSIS/Include/core_cm7.h **** + 364:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Pos 27U /*!< xPSR + 365:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR + 366:Drivers/CMSIS/Include/core_cm7.h **** + 367:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR + 368:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR + 369:Drivers/CMSIS/Include/core_cm7.h **** + 370:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Pos 24U /*!< xPSR + 371:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR + 372:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccB9Q52u.s page 8 + + + 373:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Pos 16U /*!< xPSR + 374:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR + 375:Drivers/CMSIS/Include/core_cm7.h **** + 376:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR + 377:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR + 378:Drivers/CMSIS/Include/core_cm7.h **** + 379:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Pos 0U /*!< xPSR + 380:Drivers/CMSIS/Include/core_cm7.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR + 381:Drivers/CMSIS/Include/core_cm7.h **** + 382:Drivers/CMSIS/Include/core_cm7.h **** + 383:Drivers/CMSIS/Include/core_cm7.h **** /** + 384:Drivers/CMSIS/Include/core_cm7.h **** \brief Union type to access the Control Registers (CONTROL). + 385:Drivers/CMSIS/Include/core_cm7.h **** */ + 386:Drivers/CMSIS/Include/core_cm7.h **** typedef union + 387:Drivers/CMSIS/Include/core_cm7.h **** { + 388:Drivers/CMSIS/Include/core_cm7.h **** struct + 389:Drivers/CMSIS/Include/core_cm7.h **** { + 390:Drivers/CMSIS/Include/core_cm7.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + 391:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + 392:Drivers/CMSIS/Include/core_cm7.h **** uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + 393:Drivers/CMSIS/Include/core_cm7.h **** uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + 394:Drivers/CMSIS/Include/core_cm7.h **** } b; /*!< Structure used for bit access */ + 395:Drivers/CMSIS/Include/core_cm7.h **** uint32_t w; /*!< Type used for word access */ + 396:Drivers/CMSIS/Include/core_cm7.h **** } CONTROL_Type; + 397:Drivers/CMSIS/Include/core_cm7.h **** + 398:Drivers/CMSIS/Include/core_cm7.h **** /* CONTROL Register Definitions */ + 399:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Pos 2U /*!< CONT + 400:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONT + 401:Drivers/CMSIS/Include/core_cm7.h **** + 402:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT + 403:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT + 404:Drivers/CMSIS/Include/core_cm7.h **** + 405:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT + 406:Drivers/CMSIS/Include/core_cm7.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT + 407:Drivers/CMSIS/Include/core_cm7.h **** + 408:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CORE */ + 409:Drivers/CMSIS/Include/core_cm7.h **** + 410:Drivers/CMSIS/Include/core_cm7.h **** + 411:Drivers/CMSIS/Include/core_cm7.h **** /** + 412:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + 413:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + 414:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the NVIC Registers + 415:Drivers/CMSIS/Include/core_cm7.h **** @{ + 416:Drivers/CMSIS/Include/core_cm7.h **** */ + 417:Drivers/CMSIS/Include/core_cm7.h **** + 418:Drivers/CMSIS/Include/core_cm7.h **** /** + 419:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + 420:Drivers/CMSIS/Include/core_cm7.h **** */ + 421:Drivers/CMSIS/Include/core_cm7.h **** typedef struct + 422:Drivers/CMSIS/Include/core_cm7.h **** { + 423:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + 424:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[24U]; + 425:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register + 426:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RSERVED1[24U]; + 427:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register * + 428:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[24U]; + 429:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register + ARM GAS /tmp/ccB9Q52u.s page 9 + + + 430:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[24U]; + 431:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + 432:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[56U]; + 433:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bi + 434:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[644U]; + 435:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regis + 436:Drivers/CMSIS/Include/core_cm7.h **** } NVIC_Type; + 437:Drivers/CMSIS/Include/core_cm7.h **** + 438:Drivers/CMSIS/Include/core_cm7.h **** /* Software Triggered Interrupt Register Definitions */ + 439:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Pos 0U /*!< STIR: I + 440:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: I + 441:Drivers/CMSIS/Include/core_cm7.h **** + 442:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_NVIC */ + 443:Drivers/CMSIS/Include/core_cm7.h **** + 444:Drivers/CMSIS/Include/core_cm7.h **** + 445:Drivers/CMSIS/Include/core_cm7.h **** /** + 446:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + 447:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SCB System Control Block (SCB) + 448:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Control Block Registers + 449:Drivers/CMSIS/Include/core_cm7.h **** @{ + 450:Drivers/CMSIS/Include/core_cm7.h **** */ + 451:Drivers/CMSIS/Include/core_cm7.h **** + 452:Drivers/CMSIS/Include/core_cm7.h **** /** + 453:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Control Block (SCB). + 454:Drivers/CMSIS/Include/core_cm7.h **** */ + 455:Drivers/CMSIS/Include/core_cm7.h **** typedef struct + 456:Drivers/CMSIS/Include/core_cm7.h **** { + 457:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + 458:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi + 459:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + 460:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset + 461:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + 462:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register * + 463:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registe + 464:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State + 465:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Regist + 466:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + 467:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + 468:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register + 469:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + 470:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register + 471:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + 472:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + 473:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + 474:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + 475:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regis + 476:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; + 477:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + 478:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + 479:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + 480:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + 481:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regis + 482:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[93U]; + 483:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Reg + 484:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[15U]; + 485:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 + 486:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 + ARM GAS /tmp/ccB9Q52u.s page 10 + + + 487:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 + 488:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[1U]; + 489:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + 490:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED6[1U]; + 491:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU + 492:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC + 493:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + 494:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + 495:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + 496:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + 497:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by + 498:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by + 499:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED7[6U]; + 500:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memo + 501:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Cont + 502:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + 503:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + 504:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + 505:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED8[1U]; + 506:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Regis + 507:Drivers/CMSIS/Include/core_cm7.h **** } SCB_Type; + 508:Drivers/CMSIS/Include/core_cm7.h **** + 509:Drivers/CMSIS/Include/core_cm7.h **** /* SCB CPUID Register Definitions */ + 510:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB + 511:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB + 512:Drivers/CMSIS/Include/core_cm7.h **** + 513:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB + 514:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB + 515:Drivers/CMSIS/Include/core_cm7.h **** + 516:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB + 517:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB + 518:Drivers/CMSIS/Include/core_cm7.h **** + 519:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB + 520:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB + 521:Drivers/CMSIS/Include/core_cm7.h **** + 522:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB + 523:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB + 524:Drivers/CMSIS/Include/core_cm7.h **** + 525:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Interrupt Control State Register Definitions */ + 526:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB + 527:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB + 528:Drivers/CMSIS/Include/core_cm7.h **** + 529:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB + 530:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB + 531:Drivers/CMSIS/Include/core_cm7.h **** + 532:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB + 533:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB + 534:Drivers/CMSIS/Include/core_cm7.h **** + 535:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB + 536:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB + 537:Drivers/CMSIS/Include/core_cm7.h **** + 538:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB + 539:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB + 540:Drivers/CMSIS/Include/core_cm7.h **** + 541:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB + 542:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB + 543:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccB9Q52u.s page 11 + + + 544:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB + 545:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB + 546:Drivers/CMSIS/Include/core_cm7.h **** + 547:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB + 548:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB + 549:Drivers/CMSIS/Include/core_cm7.h **** + 550:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB + 551:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB + 552:Drivers/CMSIS/Include/core_cm7.h **** + 553:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB + 554:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB + 555:Drivers/CMSIS/Include/core_cm7.h **** + 556:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Vector Table Offset Register Definitions */ + 557:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB + 558:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB + 559:Drivers/CMSIS/Include/core_cm7.h **** + 560:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Application Interrupt and Reset Control Register Definitions */ + 561:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB + 562:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB + 563:Drivers/CMSIS/Include/core_cm7.h **** + 564:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB + 565:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB + 566:Drivers/CMSIS/Include/core_cm7.h **** + 567:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB + 568:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB + 569:Drivers/CMSIS/Include/core_cm7.h **** + 570:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB + 571:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB + 572:Drivers/CMSIS/Include/core_cm7.h **** + 573:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB + 574:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB + 575:Drivers/CMSIS/Include/core_cm7.h **** + 576:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB + 577:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB + 578:Drivers/CMSIS/Include/core_cm7.h **** + 579:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB + 580:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB + 581:Drivers/CMSIS/Include/core_cm7.h **** + 582:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Control Register Definitions */ + 583:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB + 584:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB + 585:Drivers/CMSIS/Include/core_cm7.h **** + 586:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB + 587:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB + 588:Drivers/CMSIS/Include/core_cm7.h **** + 589:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB + 590:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB + 591:Drivers/CMSIS/Include/core_cm7.h **** + 592:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configuration Control Register Definitions */ + 593:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Pos 18U /*!< SCB + 594:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB + 595:Drivers/CMSIS/Include/core_cm7.h **** + 596:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Pos 17U /*!< SCB + 597:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB + 598:Drivers/CMSIS/Include/core_cm7.h **** + 599:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Pos 16U /*!< SCB + 600:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB + ARM GAS /tmp/ccB9Q52u.s page 12 + + + 601:Drivers/CMSIS/Include/core_cm7.h **** + 602:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB + 603:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB + 604:Drivers/CMSIS/Include/core_cm7.h **** + 605:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB + 606:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB + 607:Drivers/CMSIS/Include/core_cm7.h **** + 608:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB + 609:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB + 610:Drivers/CMSIS/Include/core_cm7.h **** + 611:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB + 612:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB + 613:Drivers/CMSIS/Include/core_cm7.h **** + 614:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB + 615:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB + 616:Drivers/CMSIS/Include/core_cm7.h **** + 617:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB + 618:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB + 619:Drivers/CMSIS/Include/core_cm7.h **** + 620:Drivers/CMSIS/Include/core_cm7.h **** /* SCB System Handler Control and State Register Definitions */ + 621:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB + 622:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB + 623:Drivers/CMSIS/Include/core_cm7.h **** + 624:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB + 625:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB + 626:Drivers/CMSIS/Include/core_cm7.h **** + 627:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB + 628:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB + 629:Drivers/CMSIS/Include/core_cm7.h **** + 630:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB + 631:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB + 632:Drivers/CMSIS/Include/core_cm7.h **** + 633:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB + 634:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB + 635:Drivers/CMSIS/Include/core_cm7.h **** + 636:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB + 637:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB + 638:Drivers/CMSIS/Include/core_cm7.h **** + 639:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB + 640:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB + 641:Drivers/CMSIS/Include/core_cm7.h **** + 642:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB + 643:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB + 644:Drivers/CMSIS/Include/core_cm7.h **** + 645:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB + 646:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB + 647:Drivers/CMSIS/Include/core_cm7.h **** + 648:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB + 649:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB + 650:Drivers/CMSIS/Include/core_cm7.h **** + 651:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB + 652:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB + 653:Drivers/CMSIS/Include/core_cm7.h **** + 654:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB + 655:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB + 656:Drivers/CMSIS/Include/core_cm7.h **** + 657:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB + ARM GAS /tmp/ccB9Q52u.s page 13 + + + 658:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB + 659:Drivers/CMSIS/Include/core_cm7.h **** + 660:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB + 661:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB + 662:Drivers/CMSIS/Include/core_cm7.h **** + 663:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Configurable Fault Status Register Definitions */ + 664:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB + 665:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB + 666:Drivers/CMSIS/Include/core_cm7.h **** + 667:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB + 668:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB + 669:Drivers/CMSIS/Include/core_cm7.h **** + 670:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB + 671:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB + 672:Drivers/CMSIS/Include/core_cm7.h **** + 673:Drivers/CMSIS/Include/core_cm7.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ + 674:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB + 675:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB + 676:Drivers/CMSIS/Include/core_cm7.h **** + 677:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB + 678:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB + 679:Drivers/CMSIS/Include/core_cm7.h **** + 680:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB + 681:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB + 682:Drivers/CMSIS/Include/core_cm7.h **** + 683:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB + 684:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB + 685:Drivers/CMSIS/Include/core_cm7.h **** + 686:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB + 687:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB + 688:Drivers/CMSIS/Include/core_cm7.h **** + 689:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB + 690:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB + 691:Drivers/CMSIS/Include/core_cm7.h **** + 692:Drivers/CMSIS/Include/core_cm7.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ + 693:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB + 694:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB + 695:Drivers/CMSIS/Include/core_cm7.h **** + 696:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB + 697:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB + 698:Drivers/CMSIS/Include/core_cm7.h **** + 699:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB + 700:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB + 701:Drivers/CMSIS/Include/core_cm7.h **** + 702:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB + 703:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB + 704:Drivers/CMSIS/Include/core_cm7.h **** + 705:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB + 706:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB + 707:Drivers/CMSIS/Include/core_cm7.h **** + 708:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB + 709:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB + 710:Drivers/CMSIS/Include/core_cm7.h **** + 711:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB + 712:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB + 713:Drivers/CMSIS/Include/core_cm7.h **** + 714:Drivers/CMSIS/Include/core_cm7.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ + ARM GAS /tmp/ccB9Q52u.s page 14 + + + 715:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB + 716:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB + 717:Drivers/CMSIS/Include/core_cm7.h **** + 718:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB + 719:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB + 720:Drivers/CMSIS/Include/core_cm7.h **** + 721:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB + 722:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB + 723:Drivers/CMSIS/Include/core_cm7.h **** + 724:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB + 725:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB + 726:Drivers/CMSIS/Include/core_cm7.h **** + 727:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB + 728:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB + 729:Drivers/CMSIS/Include/core_cm7.h **** + 730:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB + 731:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB + 732:Drivers/CMSIS/Include/core_cm7.h **** + 733:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Hard Fault Status Register Definitions */ + 734:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB + 735:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB + 736:Drivers/CMSIS/Include/core_cm7.h **** + 737:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Pos 30U /*!< SCB + 738:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB + 739:Drivers/CMSIS/Include/core_cm7.h **** + 740:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB + 741:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB + 742:Drivers/CMSIS/Include/core_cm7.h **** + 743:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Debug Fault Status Register Definitions */ + 744:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB + 745:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB + 746:Drivers/CMSIS/Include/core_cm7.h **** + 747:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB + 748:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB + 749:Drivers/CMSIS/Include/core_cm7.h **** + 750:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB + 751:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB + 752:Drivers/CMSIS/Include/core_cm7.h **** + 753:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Pos 1U /*!< SCB + 754:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB + 755:Drivers/CMSIS/Include/core_cm7.h **** + 756:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Pos 0U /*!< SCB + 757:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB + 758:Drivers/CMSIS/Include/core_cm7.h **** + 759:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Level ID Register Definitions */ + 760:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB + 761:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB + 762:Drivers/CMSIS/Include/core_cm7.h **** + 763:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Pos 24U /*!< SCB + 764:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB + 765:Drivers/CMSIS/Include/core_cm7.h **** + 766:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Type Register Definitions */ + 767:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Pos 29U /*!< SCB + 768:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB + 769:Drivers/CMSIS/Include/core_cm7.h **** + 770:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Pos 24U /*!< SCB + 771:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB + ARM GAS /tmp/ccB9Q52u.s page 15 + + + 772:Drivers/CMSIS/Include/core_cm7.h **** + 773:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Pos 20U /*!< SCB + 774:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB + 775:Drivers/CMSIS/Include/core_cm7.h **** + 776:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB + 777:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB + 778:Drivers/CMSIS/Include/core_cm7.h **** + 779:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB + 780:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB + 781:Drivers/CMSIS/Include/core_cm7.h **** + 782:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size ID Register Definitions */ + 783:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Pos 31U /*!< SCB + 784:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB + 785:Drivers/CMSIS/Include/core_cm7.h **** + 786:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Pos 30U /*!< SCB + 787:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB + 788:Drivers/CMSIS/Include/core_cm7.h **** + 789:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Pos 29U /*!< SCB + 790:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB + 791:Drivers/CMSIS/Include/core_cm7.h **** + 792:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Pos 28U /*!< SCB + 793:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB + 794:Drivers/CMSIS/Include/core_cm7.h **** + 795:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB + 796:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB + 797:Drivers/CMSIS/Include/core_cm7.h **** + 798:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB + 799:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB + 800:Drivers/CMSIS/Include/core_cm7.h **** + 801:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB + 802:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB + 803:Drivers/CMSIS/Include/core_cm7.h **** + 804:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Cache Size Selection Register Definitions */ + 805:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB + 806:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB + 807:Drivers/CMSIS/Include/core_cm7.h **** + 808:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Pos 0U /*!< SCB + 809:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB + 810:Drivers/CMSIS/Include/core_cm7.h **** + 811:Drivers/CMSIS/Include/core_cm7.h **** /* SCB Software Triggered Interrupt Register Definitions */ + 812:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Pos 0U /*!< SCB + 813:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB + 814:Drivers/CMSIS/Include/core_cm7.h **** + 815:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Invalidate by Set-way Register Definitions */ + 816:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Pos 30U /*!< SCB + 817:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB + 818:Drivers/CMSIS/Include/core_cm7.h **** + 819:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Pos 5U /*!< SCB + 820:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB + 821:Drivers/CMSIS/Include/core_cm7.h **** + 822:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean by Set-way Register Definitions */ + 823:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Pos 30U /*!< SCB + 824:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB + 825:Drivers/CMSIS/Include/core_cm7.h **** + 826:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Pos 5U /*!< SCB + 827:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB + 828:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccB9Q52u.s page 16 + + + 829:Drivers/CMSIS/Include/core_cm7.h **** /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ + 830:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Pos 30U /*!< SCB + 831:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB + 832:Drivers/CMSIS/Include/core_cm7.h **** + 833:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Pos 5U /*!< SCB + 834:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB + 835:Drivers/CMSIS/Include/core_cm7.h **** + 836:Drivers/CMSIS/Include/core_cm7.h **** /* Instruction Tightly-Coupled Memory Control Register Definitions */ + 837:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB + 838:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB + 839:Drivers/CMSIS/Include/core_cm7.h **** + 840:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB + 841:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB + 842:Drivers/CMSIS/Include/core_cm7.h **** + 843:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB + 844:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB + 845:Drivers/CMSIS/Include/core_cm7.h **** + 846:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Pos 0U /*!< SCB + 847:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB + 848:Drivers/CMSIS/Include/core_cm7.h **** + 849:Drivers/CMSIS/Include/core_cm7.h **** /* Data Tightly-Coupled Memory Control Register Definitions */ + 850:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB + 851:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB + 852:Drivers/CMSIS/Include/core_cm7.h **** + 853:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB + 854:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB + 855:Drivers/CMSIS/Include/core_cm7.h **** + 856:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB + 857:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB + 858:Drivers/CMSIS/Include/core_cm7.h **** + 859:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Pos 0U /*!< SCB + 860:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB + 861:Drivers/CMSIS/Include/core_cm7.h **** + 862:Drivers/CMSIS/Include/core_cm7.h **** /* AHBP Control Register Definitions */ + 863:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB + 864:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB + 865:Drivers/CMSIS/Include/core_cm7.h **** + 866:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Pos 0U /*!< SCB + 867:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB + 868:Drivers/CMSIS/Include/core_cm7.h **** + 869:Drivers/CMSIS/Include/core_cm7.h **** /* L1 Cache Control Register Definitions */ + 870:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB + 871:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB + 872:Drivers/CMSIS/Include/core_cm7.h **** + 873:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Pos 1U /*!< SCB + 874:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB + 875:Drivers/CMSIS/Include/core_cm7.h **** + 876:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Pos 0U /*!< SCB + 877:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB + 878:Drivers/CMSIS/Include/core_cm7.h **** + 879:Drivers/CMSIS/Include/core_cm7.h **** /* AHBS Control Register Definitions */ + 880:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB + 881:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB + 882:Drivers/CMSIS/Include/core_cm7.h **** + 883:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB + 884:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB + 885:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccB9Q52u.s page 17 + + + 886:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB + 887:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB + 888:Drivers/CMSIS/Include/core_cm7.h **** + 889:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Bus Fault Status Register Definitions */ + 890:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB + 891:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB + 892:Drivers/CMSIS/Include/core_cm7.h **** + 893:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB + 894:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB + 895:Drivers/CMSIS/Include/core_cm7.h **** + 896:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB + 897:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB + 898:Drivers/CMSIS/Include/core_cm7.h **** + 899:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB + 900:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB + 901:Drivers/CMSIS/Include/core_cm7.h **** + 902:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB + 903:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB + 904:Drivers/CMSIS/Include/core_cm7.h **** + 905:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB + 906:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB + 907:Drivers/CMSIS/Include/core_cm7.h **** + 908:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCB */ + 909:Drivers/CMSIS/Include/core_cm7.h **** + 910:Drivers/CMSIS/Include/core_cm7.h **** + 911:Drivers/CMSIS/Include/core_cm7.h **** /** + 912:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + 913:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + 914:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Control and ID Register not in the SCB + 915:Drivers/CMSIS/Include/core_cm7.h **** @{ + 916:Drivers/CMSIS/Include/core_cm7.h **** */ + 917:Drivers/CMSIS/Include/core_cm7.h **** + 918:Drivers/CMSIS/Include/core_cm7.h **** /** + 919:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Control and ID Register not in the SCB. + 920:Drivers/CMSIS/Include/core_cm7.h **** */ + 921:Drivers/CMSIS/Include/core_cm7.h **** typedef struct + 922:Drivers/CMSIS/Include/core_cm7.h **** { + 923:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; + 924:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Regist + 925:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + 926:Drivers/CMSIS/Include/core_cm7.h **** } SCnSCB_Type; + 927:Drivers/CMSIS/Include/core_cm7.h **** + 928:Drivers/CMSIS/Include/core_cm7.h **** /* Interrupt Controller Type Register Definitions */ + 929:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: I + 930:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: I + 931:Drivers/CMSIS/Include/core_cm7.h **** + 932:Drivers/CMSIS/Include/core_cm7.h **** /* Auxiliary Control Register Definitions */ + 933:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: + 934:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: + 935:Drivers/CMSIS/Include/core_cm7.h **** + 936:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: + 937:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: + 938:Drivers/CMSIS/Include/core_cm7.h **** + 939:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: + 940:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: + 941:Drivers/CMSIS/Include/core_cm7.h **** + 942:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: + ARM GAS /tmp/ccB9Q52u.s page 18 + + + 943:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: + 944:Drivers/CMSIS/Include/core_cm7.h **** + 945:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: + 946:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: + 947:Drivers/CMSIS/Include/core_cm7.h **** + 948:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SCnotSCB */ + 949:Drivers/CMSIS/Include/core_cm7.h **** + 950:Drivers/CMSIS/Include/core_cm7.h **** + 951:Drivers/CMSIS/Include/core_cm7.h **** /** + 952:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register + 953:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick) + 954:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the System Timer Registers. + 955:Drivers/CMSIS/Include/core_cm7.h **** @{ + 956:Drivers/CMSIS/Include/core_cm7.h **** */ + 957:Drivers/CMSIS/Include/core_cm7.h **** + 958:Drivers/CMSIS/Include/core_cm7.h **** /** + 959:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the System Timer (SysTick). + 960:Drivers/CMSIS/Include/core_cm7.h **** */ + 961:Drivers/CMSIS/Include/core_cm7.h **** typedef struct + 962:Drivers/CMSIS/Include/core_cm7.h **** { + 963:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis + 964:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + 965:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register * + 966:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + 967:Drivers/CMSIS/Include/core_cm7.h **** } SysTick_Type; + 968:Drivers/CMSIS/Include/core_cm7.h **** + 969:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Control / Status Register Definitions */ + 970:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT + 971:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT + 972:Drivers/CMSIS/Include/core_cm7.h **** + 973:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT + 974:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT + 975:Drivers/CMSIS/Include/core_cm7.h **** + 976:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT + 977:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT + 978:Drivers/CMSIS/Include/core_cm7.h **** + 979:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT + 980:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT + 981:Drivers/CMSIS/Include/core_cm7.h **** + 982:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Reload Register Definitions */ + 983:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT + 984:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT + 985:Drivers/CMSIS/Include/core_cm7.h **** + 986:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Current Register Definitions */ + 987:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT + 988:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT + 989:Drivers/CMSIS/Include/core_cm7.h **** + 990:Drivers/CMSIS/Include/core_cm7.h **** /* SysTick Calibration Register Definitions */ + 991:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT + 992:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT + 993:Drivers/CMSIS/Include/core_cm7.h **** + 994:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT + 995:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT + 996:Drivers/CMSIS/Include/core_cm7.h **** + 997:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT + 998:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT + 999:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccB9Q52u.s page 19 + + +1000:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_SysTick */ +1001:Drivers/CMSIS/Include/core_cm7.h **** +1002:Drivers/CMSIS/Include/core_cm7.h **** +1003:Drivers/CMSIS/Include/core_cm7.h **** /** +1004:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1005:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) +1006:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Instrumentation Trace Macrocell (ITM) +1007:Drivers/CMSIS/Include/core_cm7.h **** @{ +1008:Drivers/CMSIS/Include/core_cm7.h **** */ +1009:Drivers/CMSIS/Include/core_cm7.h **** +1010:Drivers/CMSIS/Include/core_cm7.h **** /** +1011:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). +1012:Drivers/CMSIS/Include/core_cm7.h **** */ +1013:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1014:Drivers/CMSIS/Include/core_cm7.h **** { +1015:Drivers/CMSIS/Include/core_cm7.h **** __OM union +1016:Drivers/CMSIS/Include/core_cm7.h **** { +1017:Drivers/CMSIS/Include/core_cm7.h **** __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ +1018:Drivers/CMSIS/Include/core_cm7.h **** __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ +1019:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ +1020:Drivers/CMSIS/Include/core_cm7.h **** } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ +1021:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[864U]; +1022:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ +1023:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[15U]; +1024:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ +1025:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[15U]; +1026:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ +1027:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[29U]; +1028:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register * +1029:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ +1030:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Reg +1031:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[43U]; +1032:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ +1033:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ +1034:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[6U]; +1035:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Re +1036:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Re +1037:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Re +1038:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Re +1039:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Re +1040:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Re +1041:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Re +1042:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Re +1043:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Re +1044:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Re +1045:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Re +1046:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Re +1047:Drivers/CMSIS/Include/core_cm7.h **** } ITM_Type; +1048:Drivers/CMSIS/Include/core_cm7.h **** +1049:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Privilege Register Definitions */ +1050:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM +1051:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM +1052:Drivers/CMSIS/Include/core_cm7.h **** +1053:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Trace Control Register Definitions */ +1054:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Pos 23U /*!< ITM +1055:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM +1056:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccB9Q52u.s page 20 + + +1057:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM +1058:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM +1059:Drivers/CMSIS/Include/core_cm7.h **** +1060:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM +1061:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM +1062:Drivers/CMSIS/Include/core_cm7.h **** +1063:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM +1064:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM +1065:Drivers/CMSIS/Include/core_cm7.h **** +1066:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Pos 4U /*!< ITM +1067:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM +1068:Drivers/CMSIS/Include/core_cm7.h **** +1069:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Pos 3U /*!< ITM +1070:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM +1071:Drivers/CMSIS/Include/core_cm7.h **** +1072:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM +1073:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM +1074:Drivers/CMSIS/Include/core_cm7.h **** +1075:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Pos 1U /*!< ITM +1076:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM +1077:Drivers/CMSIS/Include/core_cm7.h **** +1078:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Pos 0U /*!< ITM +1079:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM +1080:Drivers/CMSIS/Include/core_cm7.h **** +1081:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Write Register Definitions */ +1082:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM +1083:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM +1084:Drivers/CMSIS/Include/core_cm7.h **** +1085:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Read Register Definitions */ +1086:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM +1087:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM +1088:Drivers/CMSIS/Include/core_cm7.h **** +1089:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Integration Mode Control Register Definitions */ +1090:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM +1091:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM +1092:Drivers/CMSIS/Include/core_cm7.h **** +1093:Drivers/CMSIS/Include/core_cm7.h **** /* ITM Lock Status Register Definitions */ +1094:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM +1095:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM +1096:Drivers/CMSIS/Include/core_cm7.h **** +1097:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Pos 1U /*!< ITM +1098:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM +1099:Drivers/CMSIS/Include/core_cm7.h **** +1100:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Pos 0U /*!< ITM +1101:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM +1102:Drivers/CMSIS/Include/core_cm7.h **** +1103:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_ITM */ +1104:Drivers/CMSIS/Include/core_cm7.h **** +1105:Drivers/CMSIS/Include/core_cm7.h **** +1106:Drivers/CMSIS/Include/core_cm7.h **** /** +1107:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1108:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) +1109:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Data Watchpoint and Trace (DWT) +1110:Drivers/CMSIS/Include/core_cm7.h **** @{ +1111:Drivers/CMSIS/Include/core_cm7.h **** */ +1112:Drivers/CMSIS/Include/core_cm7.h **** +1113:Drivers/CMSIS/Include/core_cm7.h **** /** + ARM GAS /tmp/ccB9Q52u.s page 21 + + +1114:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). +1115:Drivers/CMSIS/Include/core_cm7.h **** */ +1116:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1117:Drivers/CMSIS/Include/core_cm7.h **** { +1118:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ +1119:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ +1120:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ +1121:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Registe +1122:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ +1123:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ +1124:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Registe +1125:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register +1126:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ +1127:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ +1128:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ +1129:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; +1130:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ +1131:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ +1132:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ +1133:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[1U]; +1134:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ +1135:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ +1136:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ +1137:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[1U]; +1138:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ +1139:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ +1140:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +1141:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[981U]; +1142:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ +1143:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +1144:Drivers/CMSIS/Include/core_cm7.h **** } DWT_Type; +1145:Drivers/CMSIS/Include/core_cm7.h **** +1146:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Control Register Definitions */ +1147:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTR +1148:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTR +1149:Drivers/CMSIS/Include/core_cm7.h **** +1150:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTR +1151:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTR +1152:Drivers/CMSIS/Include/core_cm7.h **** +1153:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTR +1154:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTR +1155:Drivers/CMSIS/Include/core_cm7.h **** +1156:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTR +1157:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTR +1158:Drivers/CMSIS/Include/core_cm7.h **** +1159:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTR +1160:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTR +1161:Drivers/CMSIS/Include/core_cm7.h **** +1162:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTR +1163:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTR +1164:Drivers/CMSIS/Include/core_cm7.h **** +1165:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTR +1166:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTR +1167:Drivers/CMSIS/Include/core_cm7.h **** +1168:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTR +1169:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTR +1170:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccB9Q52u.s page 22 + + +1171:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTR +1172:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTR +1173:Drivers/CMSIS/Include/core_cm7.h **** +1174:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTR +1175:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTR +1176:Drivers/CMSIS/Include/core_cm7.h **** +1177:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTR +1178:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTR +1179:Drivers/CMSIS/Include/core_cm7.h **** +1180:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTR +1181:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTR +1182:Drivers/CMSIS/Include/core_cm7.h **** +1183:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTR +1184:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTR +1185:Drivers/CMSIS/Include/core_cm7.h **** +1186:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTR +1187:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTR +1188:Drivers/CMSIS/Include/core_cm7.h **** +1189:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTR +1190:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTR +1191:Drivers/CMSIS/Include/core_cm7.h **** +1192:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTR +1193:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTR +1194:Drivers/CMSIS/Include/core_cm7.h **** +1195:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTR +1196:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTR +1197:Drivers/CMSIS/Include/core_cm7.h **** +1198:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTR +1199:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTR +1200:Drivers/CMSIS/Include/core_cm7.h **** +1201:Drivers/CMSIS/Include/core_cm7.h **** /* DWT CPI Count Register Definitions */ +1202:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPI +1203:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPI +1204:Drivers/CMSIS/Include/core_cm7.h **** +1205:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Exception Overhead Count Register Definitions */ +1206:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXC +1207:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXC +1208:Drivers/CMSIS/Include/core_cm7.h **** +1209:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Sleep Count Register Definitions */ +1210:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLE +1211:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLE +1212:Drivers/CMSIS/Include/core_cm7.h **** +1213:Drivers/CMSIS/Include/core_cm7.h **** /* DWT LSU Count Register Definitions */ +1214:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSU +1215:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSU +1216:Drivers/CMSIS/Include/core_cm7.h **** +1217:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Folded-instruction Count Register Definitions */ +1218:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOL +1219:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOL +1220:Drivers/CMSIS/Include/core_cm7.h **** +1221:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Mask Register Definitions */ +1222:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Pos 0U /*!< DWT MAS +1223:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MAS +1224:Drivers/CMSIS/Include/core_cm7.h **** +1225:Drivers/CMSIS/Include/core_cm7.h **** /* DWT Comparator Function Register Definitions */ +1226:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUN +1227:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUN + ARM GAS /tmp/ccB9Q52u.s page 23 + + +1228:Drivers/CMSIS/Include/core_cm7.h **** +1229:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUN +1230:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUN +1231:Drivers/CMSIS/Include/core_cm7.h **** +1232:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUN +1233:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUN +1234:Drivers/CMSIS/Include/core_cm7.h **** +1235:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUN +1236:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUN +1237:Drivers/CMSIS/Include/core_cm7.h **** +1238:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUN +1239:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUN +1240:Drivers/CMSIS/Include/core_cm7.h **** +1241:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUN +1242:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUN +1243:Drivers/CMSIS/Include/core_cm7.h **** +1244:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUN +1245:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUN +1246:Drivers/CMSIS/Include/core_cm7.h **** +1247:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUN +1248:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUN +1249:Drivers/CMSIS/Include/core_cm7.h **** +1250:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUN +1251:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUN +1252:Drivers/CMSIS/Include/core_cm7.h **** +1253:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_DWT */ +1254:Drivers/CMSIS/Include/core_cm7.h **** +1255:Drivers/CMSIS/Include/core_cm7.h **** +1256:Drivers/CMSIS/Include/core_cm7.h **** /** +1257:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1258:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_TPI Trace Port Interface (TPI) +1259:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Trace Port Interface (TPI) +1260:Drivers/CMSIS/Include/core_cm7.h **** @{ +1261:Drivers/CMSIS/Include/core_cm7.h **** */ +1262:Drivers/CMSIS/Include/core_cm7.h **** +1263:Drivers/CMSIS/Include/core_cm7.h **** /** +1264:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Trace Port Interface Register (TPI). +1265:Drivers/CMSIS/Include/core_cm7.h **** */ +1266:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1267:Drivers/CMSIS/Include/core_cm7.h **** { +1268:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Reg +1269:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Regis +1270:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[2U]; +1271:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Reg +1272:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED1[55U]; +1273:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register * +1274:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED2[131U]; +1275:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regis +1276:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Regi +1277:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counte +1278:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED3[759U]; +1279:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ +1280:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ +1281:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ +1282:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED4[1U]; +1283:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ +1284:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + ARM GAS /tmp/ccB9Q52u.s page 24 + + +1285:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ +1286:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED5[39U]; +1287:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ +1288:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ +1289:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED7[8U]; +1290:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ +1291:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +1292:Drivers/CMSIS/Include/core_cm7.h **** } TPI_Type; +1293:Drivers/CMSIS/Include/core_cm7.h **** +1294:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */ +1295:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACP +1296:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACP +1297:Drivers/CMSIS/Include/core_cm7.h **** +1298:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Selected Pin Protocol Register Definitions */ +1299:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPP +1300:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPP +1301:Drivers/CMSIS/Include/core_cm7.h **** +1302:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Status Register Definitions */ +1303:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFS +1304:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFS +1305:Drivers/CMSIS/Include/core_cm7.h **** +1306:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFS +1307:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFS +1308:Drivers/CMSIS/Include/core_cm7.h **** +1309:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFS +1310:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFS +1311:Drivers/CMSIS/Include/core_cm7.h **** +1312:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFS +1313:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFS +1314:Drivers/CMSIS/Include/core_cm7.h **** +1315:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Formatter and Flush Control Register Definitions */ +1316:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFC +1317:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFC +1318:Drivers/CMSIS/Include/core_cm7.h **** +1319:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFC +1320:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFC +1321:Drivers/CMSIS/Include/core_cm7.h **** +1322:Drivers/CMSIS/Include/core_cm7.h **** /* TPI TRIGGER Register Definitions */ +1323:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRI +1324:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRI +1325:Drivers/CMSIS/Include/core_cm7.h **** +1326:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */ +1327:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIF +1328:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIF +1329:Drivers/CMSIS/Include/core_cm7.h **** +1330:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIF +1331:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIF +1332:Drivers/CMSIS/Include/core_cm7.h **** +1333:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIF +1334:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIF +1335:Drivers/CMSIS/Include/core_cm7.h **** +1336:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIF +1337:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIF +1338:Drivers/CMSIS/Include/core_cm7.h **** +1339:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIF +1340:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIF +1341:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccB9Q52u.s page 25 + + +1342:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIF +1343:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIF +1344:Drivers/CMSIS/Include/core_cm7.h **** +1345:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIF +1346:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIF +1347:Drivers/CMSIS/Include/core_cm7.h **** +1348:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR2 Register Definitions */ +1349:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITA +1350:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITA +1351:Drivers/CMSIS/Include/core_cm7.h **** +1352:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITA +1353:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITA +1354:Drivers/CMSIS/Include/core_cm7.h **** +1355:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */ +1356:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIF +1357:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIF +1358:Drivers/CMSIS/Include/core_cm7.h **** +1359:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIF +1360:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIF +1361:Drivers/CMSIS/Include/core_cm7.h **** +1362:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIF +1363:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIF +1364:Drivers/CMSIS/Include/core_cm7.h **** +1365:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIF +1366:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIF +1367:Drivers/CMSIS/Include/core_cm7.h **** +1368:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIF +1369:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIF +1370:Drivers/CMSIS/Include/core_cm7.h **** +1371:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIF +1372:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIF +1373:Drivers/CMSIS/Include/core_cm7.h **** +1374:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIF +1375:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIF +1376:Drivers/CMSIS/Include/core_cm7.h **** +1377:Drivers/CMSIS/Include/core_cm7.h **** /* TPI ITATBCTR0 Register Definitions */ +1378:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITA +1379:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITA +1380:Drivers/CMSIS/Include/core_cm7.h **** +1381:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITA +1382:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITA +1383:Drivers/CMSIS/Include/core_cm7.h **** +1384:Drivers/CMSIS/Include/core_cm7.h **** /* TPI Integration Mode Control Register Definitions */ +1385:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITC +1386:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITC +1387:Drivers/CMSIS/Include/core_cm7.h **** +1388:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVID Register Definitions */ +1389:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEV +1390:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEV +1391:Drivers/CMSIS/Include/core_cm7.h **** +1392:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEV +1393:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEV +1394:Drivers/CMSIS/Include/core_cm7.h **** +1395:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEV +1396:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEV +1397:Drivers/CMSIS/Include/core_cm7.h **** +1398:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEV + ARM GAS /tmp/ccB9Q52u.s page 26 + + +1399:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEV +1400:Drivers/CMSIS/Include/core_cm7.h **** +1401:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEV +1402:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEV +1403:Drivers/CMSIS/Include/core_cm7.h **** +1404:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEV +1405:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEV +1406:Drivers/CMSIS/Include/core_cm7.h **** +1407:Drivers/CMSIS/Include/core_cm7.h **** /* TPI DEVTYPE Register Definitions */ +1408:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEV +1409:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEV +1410:Drivers/CMSIS/Include/core_cm7.h **** +1411:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEV +1412:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEV +1413:Drivers/CMSIS/Include/core_cm7.h **** +1414:Drivers/CMSIS/Include/core_cm7.h **** /*@}*/ /* end of group CMSIS_TPI */ +1415:Drivers/CMSIS/Include/core_cm7.h **** +1416:Drivers/CMSIS/Include/core_cm7.h **** +1417:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +1418:Drivers/CMSIS/Include/core_cm7.h **** /** +1419:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1420:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU) +1421:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Memory Protection Unit (MPU) +1422:Drivers/CMSIS/Include/core_cm7.h **** @{ +1423:Drivers/CMSIS/Include/core_cm7.h **** */ +1424:Drivers/CMSIS/Include/core_cm7.h **** +1425:Drivers/CMSIS/Include/core_cm7.h **** /** +1426:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Memory Protection Unit (MPU). +1427:Drivers/CMSIS/Include/core_cm7.h **** */ +1428:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1429:Drivers/CMSIS/Include/core_cm7.h **** { +1430:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ +1431:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ +1432:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ +1433:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register +1434:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re +1435:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address +1436:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and +1437:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address +1438:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and +1439:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address +1440:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and +1441:Drivers/CMSIS/Include/core_cm7.h **** } MPU_Type; +1442:Drivers/CMSIS/Include/core_cm7.h **** +1443:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_RALIASES 4U +1444:Drivers/CMSIS/Include/core_cm7.h **** +1445:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Type Register Definitions */ +1446:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU +1447:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU +1448:Drivers/CMSIS/Include/core_cm7.h **** +1449:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU +1450:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU +1451:Drivers/CMSIS/Include/core_cm7.h **** +1452:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU +1453:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU +1454:Drivers/CMSIS/Include/core_cm7.h **** +1455:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Control Register Definitions */ + ARM GAS /tmp/ccB9Q52u.s page 27 + + +1456:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU +1457:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU +1458:Drivers/CMSIS/Include/core_cm7.h **** +1459:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU +1460:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU +1461:Drivers/CMSIS/Include/core_cm7.h **** +1462:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU +1463:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU +1464:Drivers/CMSIS/Include/core_cm7.h **** +1465:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Number Register Definitions */ +1466:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU +1467:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU +1468:Drivers/CMSIS/Include/core_cm7.h **** +1469:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Base Address Register Definitions */ +1470:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Pos 5U /*!< MPU +1471:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU +1472:Drivers/CMSIS/Include/core_cm7.h **** +1473:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU +1474:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU +1475:Drivers/CMSIS/Include/core_cm7.h **** +1476:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU +1477:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU +1478:Drivers/CMSIS/Include/core_cm7.h **** +1479:Drivers/CMSIS/Include/core_cm7.h **** /* MPU Region Attribute and Size Register Definitions */ +1480:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU +1481:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU +1482:Drivers/CMSIS/Include/core_cm7.h **** +1483:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU +1484:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU +1485:Drivers/CMSIS/Include/core_cm7.h **** +1486:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU +1487:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU +1488:Drivers/CMSIS/Include/core_cm7.h **** +1489:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU +1490:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU +1491:Drivers/CMSIS/Include/core_cm7.h **** +1492:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Pos 18U /*!< MPU +1493:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU +1494:Drivers/CMSIS/Include/core_cm7.h **** +1495:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Pos 17U /*!< MPU +1496:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU +1497:Drivers/CMSIS/Include/core_cm7.h **** +1498:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Pos 16U /*!< MPU +1499:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU +1500:Drivers/CMSIS/Include/core_cm7.h **** +1501:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU +1502:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU +1503:Drivers/CMSIS/Include/core_cm7.h **** +1504:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU +1505:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU +1506:Drivers/CMSIS/Include/core_cm7.h **** +1507:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU +1508:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU +1509:Drivers/CMSIS/Include/core_cm7.h **** +1510:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_MPU */ +1511:Drivers/CMSIS/Include/core_cm7.h **** #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ +1512:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccB9Q52u.s page 28 + + +1513:Drivers/CMSIS/Include/core_cm7.h **** +1514:Drivers/CMSIS/Include/core_cm7.h **** /** +1515:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1516:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_FPU Floating Point Unit (FPU) +1517:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Floating Point Unit (FPU) +1518:Drivers/CMSIS/Include/core_cm7.h **** @{ +1519:Drivers/CMSIS/Include/core_cm7.h **** */ +1520:Drivers/CMSIS/Include/core_cm7.h **** +1521:Drivers/CMSIS/Include/core_cm7.h **** /** +1522:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Floating Point Unit (FPU). +1523:Drivers/CMSIS/Include/core_cm7.h **** */ +1524:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1525:Drivers/CMSIS/Include/core_cm7.h **** { +1526:Drivers/CMSIS/Include/core_cm7.h **** uint32_t RESERVED0[1U]; +1527:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control R +1528:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address R +1529:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Co +1530:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 +1531:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 +1532:Drivers/CMSIS/Include/core_cm7.h **** __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 +1533:Drivers/CMSIS/Include/core_cm7.h **** } FPU_Type; +1534:Drivers/CMSIS/Include/core_cm7.h **** +1535:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Control Register Definitions */ +1536:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCC +1537:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCC +1538:Drivers/CMSIS/Include/core_cm7.h **** +1539:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCC +1540:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCC +1541:Drivers/CMSIS/Include/core_cm7.h **** +1542:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCC +1543:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCC +1544:Drivers/CMSIS/Include/core_cm7.h **** +1545:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCC +1546:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCC +1547:Drivers/CMSIS/Include/core_cm7.h **** +1548:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCC +1549:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCC +1550:Drivers/CMSIS/Include/core_cm7.h **** +1551:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCC +1552:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCC +1553:Drivers/CMSIS/Include/core_cm7.h **** +1554:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCC +1555:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCC +1556:Drivers/CMSIS/Include/core_cm7.h **** +1557:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Pos 1U /*!< FPCC +1558:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCC +1559:Drivers/CMSIS/Include/core_cm7.h **** +1560:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCC +1561:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCC +1562:Drivers/CMSIS/Include/core_cm7.h **** +1563:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Context Address Register Definitions */ +1564:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCA +1565:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCA +1566:Drivers/CMSIS/Include/core_cm7.h **** +1567:Drivers/CMSIS/Include/core_cm7.h **** /* Floating-Point Default Status Control Register Definitions */ +1568:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDS +1569:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDS + ARM GAS /tmp/ccB9Q52u.s page 29 + + +1570:Drivers/CMSIS/Include/core_cm7.h **** +1571:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Pos 25U /*!< FPDS +1572:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDS +1573:Drivers/CMSIS/Include/core_cm7.h **** +1574:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDS +1575:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDS +1576:Drivers/CMSIS/Include/core_cm7.h **** +1577:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDS +1578:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDS +1579:Drivers/CMSIS/Include/core_cm7.h **** +1580:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 0 Definitions */ +1581:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR +1582:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR +1583:Drivers/CMSIS/Include/core_cm7.h **** +1584:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR +1585:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR +1586:Drivers/CMSIS/Include/core_cm7.h **** +1587:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR +1588:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR +1589:Drivers/CMSIS/Include/core_cm7.h **** +1590:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR +1591:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR +1592:Drivers/CMSIS/Include/core_cm7.h **** +1593:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR +1594:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR +1595:Drivers/CMSIS/Include/core_cm7.h **** +1596:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR +1597:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR +1598:Drivers/CMSIS/Include/core_cm7.h **** +1599:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR +1600:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR +1601:Drivers/CMSIS/Include/core_cm7.h **** +1602:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR +1603:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR +1604:Drivers/CMSIS/Include/core_cm7.h **** +1605:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 1 Definitions */ +1606:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR +1607:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR +1608:Drivers/CMSIS/Include/core_cm7.h **** +1609:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR +1610:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR +1611:Drivers/CMSIS/Include/core_cm7.h **** +1612:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR +1613:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR +1614:Drivers/CMSIS/Include/core_cm7.h **** +1615:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR +1616:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR +1617:Drivers/CMSIS/Include/core_cm7.h **** +1618:Drivers/CMSIS/Include/core_cm7.h **** /* Media and FP Feature Register 2 Definitions */ +1619:Drivers/CMSIS/Include/core_cm7.h **** +1620:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_FPU */ +1621:Drivers/CMSIS/Include/core_cm7.h **** +1622:Drivers/CMSIS/Include/core_cm7.h **** +1623:Drivers/CMSIS/Include/core_cm7.h **** /** +1624:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1625:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) +1626:Drivers/CMSIS/Include/core_cm7.h **** \brief Type definitions for the Core Debug Registers + ARM GAS /tmp/ccB9Q52u.s page 30 + + +1627:Drivers/CMSIS/Include/core_cm7.h **** @{ +1628:Drivers/CMSIS/Include/core_cm7.h **** */ +1629:Drivers/CMSIS/Include/core_cm7.h **** +1630:Drivers/CMSIS/Include/core_cm7.h **** /** +1631:Drivers/CMSIS/Include/core_cm7.h **** \brief Structure type to access the Core Debug Register (CoreDebug). +1632:Drivers/CMSIS/Include/core_cm7.h **** */ +1633:Drivers/CMSIS/Include/core_cm7.h **** typedef struct +1634:Drivers/CMSIS/Include/core_cm7.h **** { +1635:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status +1636:Drivers/CMSIS/Include/core_cm7.h **** __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Reg +1637:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Registe +1638:Drivers/CMSIS/Include/core_cm7.h **** __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Cont +1639:Drivers/CMSIS/Include/core_cm7.h **** } CoreDebug_Type; +1640:Drivers/CMSIS/Include/core_cm7.h **** +1641:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Halting Control and Status Register Definitions */ +1642:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< Core +1643:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< Core +1644:Drivers/CMSIS/Include/core_cm7.h **** +1645:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< Core +1646:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< Core +1647:Drivers/CMSIS/Include/core_cm7.h **** +1648:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< Core +1649:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< Core +1650:Drivers/CMSIS/Include/core_cm7.h **** +1651:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< Core +1652:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< Core +1653:Drivers/CMSIS/Include/core_cm7.h **** +1654:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< Core +1655:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< Core +1656:Drivers/CMSIS/Include/core_cm7.h **** +1657:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< Core +1658:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< Core +1659:Drivers/CMSIS/Include/core_cm7.h **** +1660:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< Core +1661:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< Core +1662:Drivers/CMSIS/Include/core_cm7.h **** +1663:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< Core +1664:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< Core +1665:Drivers/CMSIS/Include/core_cm7.h **** +1666:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< Core +1667:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< Core +1668:Drivers/CMSIS/Include/core_cm7.h **** +1669:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< Core +1670:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< Core +1671:Drivers/CMSIS/Include/core_cm7.h **** +1672:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< Core +1673:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< Core +1674:Drivers/CMSIS/Include/core_cm7.h **** +1675:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< Core +1676:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< Core +1677:Drivers/CMSIS/Include/core_cm7.h **** +1678:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Core Register Selector Register Definitions */ +1679:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core +1680:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core +1681:Drivers/CMSIS/Include/core_cm7.h **** +1682:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< Core +1683:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< Core + ARM GAS /tmp/ccB9Q52u.s page 31 + + +1684:Drivers/CMSIS/Include/core_cm7.h **** +1685:Drivers/CMSIS/Include/core_cm7.h **** /* Debug Exception and Monitor Control Register Definitions */ +1686:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< Core +1687:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< Core +1688:Drivers/CMSIS/Include/core_cm7.h **** +1689:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< Core +1690:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< Core +1691:Drivers/CMSIS/Include/core_cm7.h **** +1692:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< Core +1693:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< Core +1694:Drivers/CMSIS/Include/core_cm7.h **** +1695:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< Core +1696:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< Core +1697:Drivers/CMSIS/Include/core_cm7.h **** +1698:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< Core +1699:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< Core +1700:Drivers/CMSIS/Include/core_cm7.h **** +1701:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< Core +1702:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< Core +1703:Drivers/CMSIS/Include/core_cm7.h **** +1704:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< Core +1705:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< Core +1706:Drivers/CMSIS/Include/core_cm7.h **** +1707:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< Core +1708:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< Core +1709:Drivers/CMSIS/Include/core_cm7.h **** +1710:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< Core +1711:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< Core +1712:Drivers/CMSIS/Include/core_cm7.h **** +1713:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< Core +1714:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< Core +1715:Drivers/CMSIS/Include/core_cm7.h **** +1716:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< Core +1717:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< Core +1718:Drivers/CMSIS/Include/core_cm7.h **** +1719:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< Core +1720:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< Core +1721:Drivers/CMSIS/Include/core_cm7.h **** +1722:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< Core +1723:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< Core +1724:Drivers/CMSIS/Include/core_cm7.h **** +1725:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_CoreDebug */ +1726:Drivers/CMSIS/Include/core_cm7.h **** +1727:Drivers/CMSIS/Include/core_cm7.h **** +1728:Drivers/CMSIS/Include/core_cm7.h **** /** +1729:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1730:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_bitfield Core register bit field macros +1731:Drivers/CMSIS/Include/core_cm7.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). +1732:Drivers/CMSIS/Include/core_cm7.h **** @{ +1733:Drivers/CMSIS/Include/core_cm7.h **** */ +1734:Drivers/CMSIS/Include/core_cm7.h **** +1735:Drivers/CMSIS/Include/core_cm7.h **** /** +1736:Drivers/CMSIS/Include/core_cm7.h **** \brief Mask and shift a bit field value for use in a register bit range. +1737:Drivers/CMSIS/Include/core_cm7.h **** \param[in] field Name of the register bit field. +1738:Drivers/CMSIS/Include/core_cm7.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. +1739:Drivers/CMSIS/Include/core_cm7.h **** \return Masked and shifted value. +1740:Drivers/CMSIS/Include/core_cm7.h **** */ + ARM GAS /tmp/ccB9Q52u.s page 32 + + +1741:Drivers/CMSIS/Include/core_cm7.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) +1742:Drivers/CMSIS/Include/core_cm7.h **** +1743:Drivers/CMSIS/Include/core_cm7.h **** /** +1744:Drivers/CMSIS/Include/core_cm7.h **** \brief Mask and shift a register value to extract a bit filed value. +1745:Drivers/CMSIS/Include/core_cm7.h **** \param[in] field Name of the register bit field. +1746:Drivers/CMSIS/Include/core_cm7.h **** \param[in] value Value of register. This parameter is interpreted as an uint32_t type. +1747:Drivers/CMSIS/Include/core_cm7.h **** \return Masked and shifted bit field value. +1748:Drivers/CMSIS/Include/core_cm7.h **** */ +1749:Drivers/CMSIS/Include/core_cm7.h **** #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) +1750:Drivers/CMSIS/Include/core_cm7.h **** +1751:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of group CMSIS_core_bitfield */ +1752:Drivers/CMSIS/Include/core_cm7.h **** +1753:Drivers/CMSIS/Include/core_cm7.h **** +1754:Drivers/CMSIS/Include/core_cm7.h **** /** +1755:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_core_register +1756:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_core_base Core Definitions +1757:Drivers/CMSIS/Include/core_cm7.h **** \brief Definitions for base addresses, unions, and structures. +1758:Drivers/CMSIS/Include/core_cm7.h **** @{ +1759:Drivers/CMSIS/Include/core_cm7.h **** */ +1760:Drivers/CMSIS/Include/core_cm7.h **** +1761:Drivers/CMSIS/Include/core_cm7.h **** /* Memory mapping of Core Hardware */ +1762:Drivers/CMSIS/Include/core_cm7.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas +1763:Drivers/CMSIS/Include/core_cm7.h **** #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +1764:Drivers/CMSIS/Include/core_cm7.h **** #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +1765:Drivers/CMSIS/Include/core_cm7.h **** #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +1766:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address +1767:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +1768:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +1769:Drivers/CMSIS/Include/core_cm7.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas +1770:Drivers/CMSIS/Include/core_cm7.h **** +1771:Drivers/CMSIS/Include/core_cm7.h **** #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register +1772:Drivers/CMSIS/Include/core_cm7.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct +1773:Drivers/CMSIS/Include/core_cm7.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st +1774:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc +1775:Drivers/CMSIS/Include/core_cm7.h **** #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct +1776:Drivers/CMSIS/Include/core_cm7.h **** #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct +1777:Drivers/CMSIS/Include/core_cm7.h **** #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct +1778:Drivers/CMSIS/Include/core_cm7.h **** #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration +1779:Drivers/CMSIS/Include/core_cm7.h **** +1780:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +1781:Drivers/CMSIS/Include/core_cm7.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit * +1782:Drivers/CMSIS/Include/core_cm7.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit * +1783:Drivers/CMSIS/Include/core_cm7.h **** #endif +1784:Drivers/CMSIS/Include/core_cm7.h **** +1785:Drivers/CMSIS/Include/core_cm7.h **** #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +1786:Drivers/CMSIS/Include/core_cm7.h **** #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +1787:Drivers/CMSIS/Include/core_cm7.h **** +1788:Drivers/CMSIS/Include/core_cm7.h **** /*@} */ +1789:Drivers/CMSIS/Include/core_cm7.h **** +1790:Drivers/CMSIS/Include/core_cm7.h **** +1791:Drivers/CMSIS/Include/core_cm7.h **** +1792:Drivers/CMSIS/Include/core_cm7.h **** /******************************************************************************* +1793:Drivers/CMSIS/Include/core_cm7.h **** * Hardware Abstraction Layer +1794:Drivers/CMSIS/Include/core_cm7.h **** Core Function Interface contains: +1795:Drivers/CMSIS/Include/core_cm7.h **** - Core NVIC Functions +1796:Drivers/CMSIS/Include/core_cm7.h **** - Core SysTick Functions +1797:Drivers/CMSIS/Include/core_cm7.h **** - Core Debug Functions + ARM GAS /tmp/ccB9Q52u.s page 33 + + +1798:Drivers/CMSIS/Include/core_cm7.h **** - Core Register Access Functions +1799:Drivers/CMSIS/Include/core_cm7.h **** ******************************************************************************/ +1800:Drivers/CMSIS/Include/core_cm7.h **** /** +1801:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +1802:Drivers/CMSIS/Include/core_cm7.h **** */ +1803:Drivers/CMSIS/Include/core_cm7.h **** +1804:Drivers/CMSIS/Include/core_cm7.h **** +1805:Drivers/CMSIS/Include/core_cm7.h **** +1806:Drivers/CMSIS/Include/core_cm7.h **** /* ########################## NVIC functions #################################### */ +1807:Drivers/CMSIS/Include/core_cm7.h **** /** +1808:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_Core_FunctionInterface +1809:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions +1810:Drivers/CMSIS/Include/core_cm7.h **** \brief Functions that manage interrupts and exceptions via the NVIC. +1811:Drivers/CMSIS/Include/core_cm7.h **** @{ +1812:Drivers/CMSIS/Include/core_cm7.h **** */ +1813:Drivers/CMSIS/Include/core_cm7.h **** +1814:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_NVIC_VIRTUAL +1815:Drivers/CMSIS/Include/core_cm7.h **** #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE +1816:Drivers/CMSIS/Include/core_cm7.h **** #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" +1817:Drivers/CMSIS/Include/core_cm7.h **** #endif +1818:Drivers/CMSIS/Include/core_cm7.h **** #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +1819:Drivers/CMSIS/Include/core_cm7.h **** #else +1820:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +1821:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +1822:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_EnableIRQ __NVIC_EnableIRQ +1823:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +1824:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_DisableIRQ __NVIC_DisableIRQ +1825:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +1826:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +1827:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +1828:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetActive __NVIC_GetActive +1829:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetPriority __NVIC_SetPriority +1830:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetPriority __NVIC_GetPriority +1831:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SystemReset __NVIC_SystemReset +1832:Drivers/CMSIS/Include/core_cm7.h **** #endif /* CMSIS_NVIC_VIRTUAL */ +1833:Drivers/CMSIS/Include/core_cm7.h **** +1834:Drivers/CMSIS/Include/core_cm7.h **** #ifdef CMSIS_VECTAB_VIRTUAL +1835:Drivers/CMSIS/Include/core_cm7.h **** #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE +1836:Drivers/CMSIS/Include/core_cm7.h **** #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" +1837:Drivers/CMSIS/Include/core_cm7.h **** #endif +1838:Drivers/CMSIS/Include/core_cm7.h **** #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +1839:Drivers/CMSIS/Include/core_cm7.h **** #else +1840:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_SetVector __NVIC_SetVector +1841:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_GetVector __NVIC_GetVector +1842:Drivers/CMSIS/Include/core_cm7.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */ +1843:Drivers/CMSIS/Include/core_cm7.h **** +1844:Drivers/CMSIS/Include/core_cm7.h **** #define NVIC_USER_IRQ_OFFSET 16 +1845:Drivers/CMSIS/Include/core_cm7.h **** +1846:Drivers/CMSIS/Include/core_cm7.h **** +1847:Drivers/CMSIS/Include/core_cm7.h **** /* The following EXC_RETURN values are saved the LR on exception entry */ +1848:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after ret +1849:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after retu +1850:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after retu +1851:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after ret +1852:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after retu +1853:Drivers/CMSIS/Include/core_cm7.h **** #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after retu +1854:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccB9Q52u.s page 34 + + +1855:Drivers/CMSIS/Include/core_cm7.h **** +1856:Drivers/CMSIS/Include/core_cm7.h **** /** +1857:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Priority Grouping +1858:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the priority grouping field using the required unlock sequence. +1859:Drivers/CMSIS/Include/core_cm7.h **** The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. +1860:Drivers/CMSIS/Include/core_cm7.h **** Only values from 0..7 are used. +1861:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available +1862:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. +1863:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Priority grouping field. +1864:Drivers/CMSIS/Include/core_cm7.h **** */ +1865:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +1866:Drivers/CMSIS/Include/core_cm7.h **** { +1867:Drivers/CMSIS/Include/core_cm7.h **** uint32_t reg_value; +1868:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a +1869:Drivers/CMSIS/Include/core_cm7.h **** +1870:Drivers/CMSIS/Include/core_cm7.h **** reg_value = SCB->AIRCR; /* read old register +1871:Drivers/CMSIS/Include/core_cm7.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan +1872:Drivers/CMSIS/Include/core_cm7.h **** reg_value = (reg_value | +1873:Drivers/CMSIS/Include/core_cm7.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | +1874:Drivers/CMSIS/Include/core_cm7.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a +1875:Drivers/CMSIS/Include/core_cm7.h **** SCB->AIRCR = reg_value; +1876:Drivers/CMSIS/Include/core_cm7.h **** } +1877:Drivers/CMSIS/Include/core_cm7.h **** +1878:Drivers/CMSIS/Include/core_cm7.h **** +1879:Drivers/CMSIS/Include/core_cm7.h **** /** +1880:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Priority Grouping +1881:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the priority grouping field from the NVIC Interrupt Controller. +1882:Drivers/CMSIS/Include/core_cm7.h **** \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). +1883:Drivers/CMSIS/Include/core_cm7.h **** */ +1884:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +1885:Drivers/CMSIS/Include/core_cm7.h **** { +1886:Drivers/CMSIS/Include/core_cm7.h **** return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +1887:Drivers/CMSIS/Include/core_cm7.h **** } +1888:Drivers/CMSIS/Include/core_cm7.h **** +1889:Drivers/CMSIS/Include/core_cm7.h **** +1890:Drivers/CMSIS/Include/core_cm7.h **** /** +1891:Drivers/CMSIS/Include/core_cm7.h **** \brief Enable Interrupt +1892:Drivers/CMSIS/Include/core_cm7.h **** \details Enables a device specific interrupt in the NVIC interrupt controller. +1893:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1894:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1895:Drivers/CMSIS/Include/core_cm7.h **** */ +1896:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +1897:Drivers/CMSIS/Include/core_cm7.h **** { +1898:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1899:Drivers/CMSIS/Include/core_cm7.h **** { +1900:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +1901:Drivers/CMSIS/Include/core_cm7.h **** } +1902:Drivers/CMSIS/Include/core_cm7.h **** } +1903:Drivers/CMSIS/Include/core_cm7.h **** +1904:Drivers/CMSIS/Include/core_cm7.h **** +1905:Drivers/CMSIS/Include/core_cm7.h **** /** +1906:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Enable status +1907:Drivers/CMSIS/Include/core_cm7.h **** \details Returns a device specific interrupt enable status from the NVIC interrupt controller. +1908:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1909:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt is not enabled. +1910:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt is enabled. +1911:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. + ARM GAS /tmp/ccB9Q52u.s page 35 + + +1912:Drivers/CMSIS/Include/core_cm7.h **** */ +1913:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +1914:Drivers/CMSIS/Include/core_cm7.h **** { +1915:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1916:Drivers/CMSIS/Include/core_cm7.h **** { +1917:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) +1918:Drivers/CMSIS/Include/core_cm7.h **** } +1919:Drivers/CMSIS/Include/core_cm7.h **** else +1920:Drivers/CMSIS/Include/core_cm7.h **** { +1921:Drivers/CMSIS/Include/core_cm7.h **** return(0U); +1922:Drivers/CMSIS/Include/core_cm7.h **** } +1923:Drivers/CMSIS/Include/core_cm7.h **** } +1924:Drivers/CMSIS/Include/core_cm7.h **** +1925:Drivers/CMSIS/Include/core_cm7.h **** +1926:Drivers/CMSIS/Include/core_cm7.h **** /** +1927:Drivers/CMSIS/Include/core_cm7.h **** \brief Disable Interrupt +1928:Drivers/CMSIS/Include/core_cm7.h **** \details Disables a device specific interrupt in the NVIC interrupt controller. +1929:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1930:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1931:Drivers/CMSIS/Include/core_cm7.h **** */ +1932:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +1933:Drivers/CMSIS/Include/core_cm7.h **** { + 29 .loc 2 1933 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. +1934:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) + 34 .loc 2 1934 3 view .LVU1 + 35 .loc 2 1934 6 is_stmt 0 view .LVU2 + 36 0000 0028 cmp r0, #0 + 37 .loc 2 1934 6 view .LVU3 + 38 0002 0CDB blt .L1 +1935:Drivers/CMSIS/Include/core_cm7.h **** { +1936:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 39 .loc 2 1936 5 is_stmt 1 view .LVU4 + 40 .loc 2 1936 81 is_stmt 0 view .LVU5 + 41 0004 00F01F02 and r2, r0, #31 + 42 .loc 2 1936 34 view .LVU6 + 43 0008 4009 lsrs r0, r0, #5 + 44 .LVL1: + 45 .loc 2 1936 45 view .LVU7 + 46 000a 0123 movs r3, #1 + 47 000c 9340 lsls r3, r3, r2 + 48 .loc 2 1936 43 view .LVU8 + 49 000e 2030 adds r0, r0, #32 + 50 0010 034A ldr r2, .L3 + 51 0012 42F82030 str r3, [r2, r0, lsl #2] +1937:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); + 52 .loc 2 1937 5 is_stmt 1 view .LVU9 + 53 .LBB38: + 54 .LBI38: + 55 .file 3 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + ARM GAS /tmp/ccB9Q52u.s page 36 + + + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + ARM GAS /tmp/ccB9Q52u.s page 37 + + + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + ARM GAS /tmp/ccB9Q52u.s page 38 + + + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccB9Q52u.s page 39 + + + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccB9Q52u.s page 40 + + + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + ARM GAS /tmp/ccB9Q52u.s page 41 + + + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccB9Q52u.s page 42 + + + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccB9Q52u.s page 43 + + + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccB9Q52u.s page 44 + + + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccB9Q52u.s page 45 + + + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccB9Q52u.s page 46 + + + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + ARM GAS /tmp/ccB9Q52u.s page 47 + + + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + ARM GAS /tmp/ccB9Q52u.s page 48 + + + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccB9Q52u.s page 49 + + + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + ARM GAS /tmp/ccB9Q52u.s page 50 + + + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccB9Q52u.s page 51 + + + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 56 .loc 3 877 27 view .LVU10 + 57 .LBB39: + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 58 .loc 3 879 3 view .LVU11 + 59 .syntax unified + 60 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 61 0016 BFF34F8F dsb 0xF + 62 @ 0 "" 2 + 63 .thumb + 64 .syntax unified + 65 .LBE39: + 66 .LBE38: +1938:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); + 67 .loc 2 1938 5 view .LVU12 + 68 .LBB40: + 69 .LBI40: + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 70 .loc 3 866 27 view .LVU13 + 71 .LBB41: + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 72 .loc 3 868 3 view .LVU14 + 73 .syntax unified + 74 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 75 001a BFF36F8F isb 0xF + 76 @ 0 "" 2 + 77 .thumb + 78 .syntax unified + 79 .L1: + 80 .LBE41: + 81 .LBE40: +1939:Drivers/CMSIS/Include/core_cm7.h **** } +1940:Drivers/CMSIS/Include/core_cm7.h **** } + 82 .loc 2 1940 1 is_stmt 0 view .LVU15 + 83 001e 7047 bx lr + 84 .L4: + 85 .align 2 + 86 .L3: + 87 0020 00E100E0 .word -536813312 + ARM GAS /tmp/ccB9Q52u.s page 52 + + + 88 .cfi_endproc + 89 .LFE106: + 91 .section .text.__NVIC_SetPriority,"ax",%progbits + 92 .align 1 + 93 .syntax unified + 94 .thumb + 95 .thumb_func + 97 __NVIC_SetPriority: + 98 .LVL2: + 99 .LFB111: +1941:Drivers/CMSIS/Include/core_cm7.h **** +1942:Drivers/CMSIS/Include/core_cm7.h **** +1943:Drivers/CMSIS/Include/core_cm7.h **** /** +1944:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Pending Interrupt +1945:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the NVIC pending register and returns the pending bit for the specified device spe +1946:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1947:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt status is not pending. +1948:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt status is pending. +1949:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1950:Drivers/CMSIS/Include/core_cm7.h **** */ +1951:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +1952:Drivers/CMSIS/Include/core_cm7.h **** { +1953:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1954:Drivers/CMSIS/Include/core_cm7.h **** { +1955:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) +1956:Drivers/CMSIS/Include/core_cm7.h **** } +1957:Drivers/CMSIS/Include/core_cm7.h **** else +1958:Drivers/CMSIS/Include/core_cm7.h **** { +1959:Drivers/CMSIS/Include/core_cm7.h **** return(0U); +1960:Drivers/CMSIS/Include/core_cm7.h **** } +1961:Drivers/CMSIS/Include/core_cm7.h **** } +1962:Drivers/CMSIS/Include/core_cm7.h **** +1963:Drivers/CMSIS/Include/core_cm7.h **** +1964:Drivers/CMSIS/Include/core_cm7.h **** /** +1965:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Pending Interrupt +1966:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register. +1967:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1968:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1969:Drivers/CMSIS/Include/core_cm7.h **** */ +1970:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +1971:Drivers/CMSIS/Include/core_cm7.h **** { +1972:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +1973:Drivers/CMSIS/Include/core_cm7.h **** { +1974:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +1975:Drivers/CMSIS/Include/core_cm7.h **** } +1976:Drivers/CMSIS/Include/core_cm7.h **** } +1977:Drivers/CMSIS/Include/core_cm7.h **** +1978:Drivers/CMSIS/Include/core_cm7.h **** +1979:Drivers/CMSIS/Include/core_cm7.h **** /** +1980:Drivers/CMSIS/Include/core_cm7.h **** \brief Clear Pending Interrupt +1981:Drivers/CMSIS/Include/core_cm7.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register. +1982:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1983:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +1984:Drivers/CMSIS/Include/core_cm7.h **** */ +1985:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +1986:Drivers/CMSIS/Include/core_cm7.h **** { +1987:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) + ARM GAS /tmp/ccB9Q52u.s page 53 + + +1988:Drivers/CMSIS/Include/core_cm7.h **** { +1989:Drivers/CMSIS/Include/core_cm7.h **** NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +1990:Drivers/CMSIS/Include/core_cm7.h **** } +1991:Drivers/CMSIS/Include/core_cm7.h **** } +1992:Drivers/CMSIS/Include/core_cm7.h **** +1993:Drivers/CMSIS/Include/core_cm7.h **** +1994:Drivers/CMSIS/Include/core_cm7.h **** /** +1995:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Active Interrupt +1996:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the active register in the NVIC and returns the active bit for the device specific +1997:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Device specific interrupt number. +1998:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Interrupt status is not active. +1999:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Interrupt status is active. +2000:Drivers/CMSIS/Include/core_cm7.h **** \note IRQn must not be negative. +2001:Drivers/CMSIS/Include/core_cm7.h **** */ +2002:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +2003:Drivers/CMSIS/Include/core_cm7.h **** { +2004:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) +2005:Drivers/CMSIS/Include/core_cm7.h **** { +2006:Drivers/CMSIS/Include/core_cm7.h **** return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) +2007:Drivers/CMSIS/Include/core_cm7.h **** } +2008:Drivers/CMSIS/Include/core_cm7.h **** else +2009:Drivers/CMSIS/Include/core_cm7.h **** { +2010:Drivers/CMSIS/Include/core_cm7.h **** return(0U); +2011:Drivers/CMSIS/Include/core_cm7.h **** } +2012:Drivers/CMSIS/Include/core_cm7.h **** } +2013:Drivers/CMSIS/Include/core_cm7.h **** +2014:Drivers/CMSIS/Include/core_cm7.h **** +2015:Drivers/CMSIS/Include/core_cm7.h **** /** +2016:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Interrupt Priority +2017:Drivers/CMSIS/Include/core_cm7.h **** \details Sets the priority of a device specific interrupt or a processor exception. +2018:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, +2019:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. +2020:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number. +2021:Drivers/CMSIS/Include/core_cm7.h **** \param [in] priority Priority to set. +2022:Drivers/CMSIS/Include/core_cm7.h **** \note The priority cannot be set for every processor exception. +2023:Drivers/CMSIS/Include/core_cm7.h **** */ +2024:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +2025:Drivers/CMSIS/Include/core_cm7.h **** { + 100 .loc 2 2025 1 is_stmt 1 view -0 + 101 .cfi_startproc + 102 @ args = 0, pretend = 0, frame = 0 + 103 @ frame_needed = 0, uses_anonymous_args = 0 + 104 @ link register save eliminated. +2026:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) + 105 .loc 2 2026 3 view .LVU17 + 106 .loc 2 2026 6 is_stmt 0 view .LVU18 + 107 0000 0028 cmp r0, #0 + 108 .loc 2 2026 6 view .LVU19 + 109 0002 04DB blt .L6 +2027:Drivers/CMSIS/Include/core_cm7.h **** { +2028:Drivers/CMSIS/Include/core_cm7.h **** NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & ( + 110 .loc 2 2028 5 is_stmt 1 view .LVU20 + 111 .loc 2 2028 49 is_stmt 0 view .LVU21 + 112 0004 0901 lsls r1, r1, #4 + 113 .LVL3: + 114 .loc 2 2028 49 view .LVU22 + 115 0006 C9B2 uxtb r1, r1 + ARM GAS /tmp/ccB9Q52u.s page 54 + + + 116 .loc 2 2028 47 view .LVU23 + 117 0008 044B ldr r3, .L8 + 118 000a 1954 strb r1, [r3, r0] + 119 000c 7047 bx lr + 120 .LVL4: + 121 .L6: +2029:Drivers/CMSIS/Include/core_cm7.h **** } +2030:Drivers/CMSIS/Include/core_cm7.h **** else +2031:Drivers/CMSIS/Include/core_cm7.h **** { +2032:Drivers/CMSIS/Include/core_cm7.h **** SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & ( + 122 .loc 2 2032 5 is_stmt 1 view .LVU24 + 123 .loc 2 2032 33 is_stmt 0 view .LVU25 + 124 000e 00F00F00 and r0, r0, #15 + 125 .LVL5: + 126 .loc 2 2032 49 view .LVU26 + 127 0012 0901 lsls r1, r1, #4 + 128 .LVL6: + 129 .loc 2 2032 49 view .LVU27 + 130 0014 C9B2 uxtb r1, r1 + 131 .loc 2 2032 47 view .LVU28 + 132 0016 024B ldr r3, .L8+4 + 133 0018 1954 strb r1, [r3, r0] +2033:Drivers/CMSIS/Include/core_cm7.h **** } +2034:Drivers/CMSIS/Include/core_cm7.h **** } + 134 .loc 2 2034 1 view .LVU29 + 135 001a 7047 bx lr + 136 .L9: + 137 .align 2 + 138 .L8: + 139 001c 00E400E0 .word -536812544 + 140 0020 14ED00E0 .word -536810220 + 141 .cfi_endproc + 142 .LFE111: + 144 .section .text.__NVIC_GetPriority,"ax",%progbits + 145 .align 1 + 146 .syntax unified + 147 .thumb + 148 .thumb_func + 150 __NVIC_GetPriority: + 151 .LVL7: + 152 .LFB112: +2035:Drivers/CMSIS/Include/core_cm7.h **** +2036:Drivers/CMSIS/Include/core_cm7.h **** +2037:Drivers/CMSIS/Include/core_cm7.h **** /** +2038:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Priority +2039:Drivers/CMSIS/Include/core_cm7.h **** \details Reads the priority of a device specific interrupt or a processor exception. +2040:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, +2041:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. +2042:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number. +2043:Drivers/CMSIS/Include/core_cm7.h **** \return Interrupt Priority. +2044:Drivers/CMSIS/Include/core_cm7.h **** Value is aligned automatically to the implemented priority bits of the microc +2045:Drivers/CMSIS/Include/core_cm7.h **** */ +2046:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +2047:Drivers/CMSIS/Include/core_cm7.h **** { + 153 .loc 2 2047 1 is_stmt 1 view -0 + 154 .cfi_startproc + 155 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccB9Q52u.s page 55 + + + 156 @ frame_needed = 0, uses_anonymous_args = 0 + 157 @ link register save eliminated. +2048:Drivers/CMSIS/Include/core_cm7.h **** +2049:Drivers/CMSIS/Include/core_cm7.h **** if ((int32_t)(IRQn) >= 0) + 158 .loc 2 2049 3 view .LVU31 + 159 .loc 2 2049 6 is_stmt 0 view .LVU32 + 160 0000 0028 cmp r0, #0 + 161 .loc 2 2049 6 view .LVU33 + 162 0002 03DB blt .L11 +2050:Drivers/CMSIS/Include/core_cm7.h **** { +2051:Drivers/CMSIS/Include/core_cm7.h **** return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + 163 .loc 2 2051 5 is_stmt 1 view .LVU34 + 164 .loc 2 2051 31 is_stmt 0 view .LVU35 + 165 0004 044B ldr r3, .L13 + 166 0006 185C ldrb r0, [r3, r0] @ zero_extendqisi2 + 167 .LVL8: + 168 .loc 2 2051 65 view .LVU36 + 169 0008 0009 lsrs r0, r0, #4 + 170 000a 7047 bx lr + 171 .L11: +2052:Drivers/CMSIS/Include/core_cm7.h **** } +2053:Drivers/CMSIS/Include/core_cm7.h **** else +2054:Drivers/CMSIS/Include/core_cm7.h **** { +2055:Drivers/CMSIS/Include/core_cm7.h **** return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + 172 .loc 2 2055 5 is_stmt 1 view .LVU37 + 173 .loc 2 2055 51 is_stmt 0 view .LVU38 + 174 000c 00F00F00 and r0, r0, #15 + 175 .loc 2 2055 32 view .LVU39 + 176 0010 024B ldr r3, .L13+4 + 177 0012 185C ldrb r0, [r3, r0] @ zero_extendqisi2 + 178 .loc 2 2055 65 view .LVU40 + 179 0014 0009 lsrs r0, r0, #4 +2056:Drivers/CMSIS/Include/core_cm7.h **** } +2057:Drivers/CMSIS/Include/core_cm7.h **** } + 180 .loc 2 2057 1 view .LVU41 + 181 0016 7047 bx lr + 182 .L14: + 183 .align 2 + 184 .L13: + 185 0018 00E400E0 .word -536812544 + 186 001c 14ED00E0 .word -536810220 + 187 .cfi_endproc + 188 .LFE112: + 190 .section .text.NVIC_EncodePriority,"ax",%progbits + 191 .align 1 + 192 .syntax unified + 193 .thumb + 194 .thumb_func + 196 NVIC_EncodePriority: + 197 .LVL9: + 198 .LFB113: +2058:Drivers/CMSIS/Include/core_cm7.h **** +2059:Drivers/CMSIS/Include/core_cm7.h **** +2060:Drivers/CMSIS/Include/core_cm7.h **** /** +2061:Drivers/CMSIS/Include/core_cm7.h **** \brief Encode Priority +2062:Drivers/CMSIS/Include/core_cm7.h **** \details Encodes the priority for an interrupt with the given priority group, +2063:Drivers/CMSIS/Include/core_cm7.h **** preemptive priority value, and subpriority value. + ARM GAS /tmp/ccB9Q52u.s page 56 + + +2064:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available +2065:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. +2066:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Used priority group. +2067:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PreemptPriority Preemptive priority value (starting from 0). +2068:Drivers/CMSIS/Include/core_cm7.h **** \param [in] SubPriority Subpriority value (starting from 0). +2069:Drivers/CMSIS/Include/core_cm7.h **** \return Encoded priority. Value can be used in the function \ref NVIC_SetP +2070:Drivers/CMSIS/Include/core_cm7.h **** */ +2071:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin +2072:Drivers/CMSIS/Include/core_cm7.h **** { + 199 .loc 2 2072 1 is_stmt 1 view -0 + 200 .cfi_startproc + 201 @ args = 0, pretend = 0, frame = 0 + 202 @ frame_needed = 0, uses_anonymous_args = 0 + 203 .loc 2 2072 1 is_stmt 0 view .LVU43 + 204 0000 00B5 push {lr} + 205 .LCFI0: + 206 .cfi_def_cfa_offset 4 + 207 .cfi_offset 14, -4 +2073:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used + 208 .loc 2 2073 3 is_stmt 1 view .LVU44 + 209 .loc 2 2073 12 is_stmt 0 view .LVU45 + 210 0002 00F00700 and r0, r0, #7 + 211 .LVL10: +2074:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PreemptPriorityBits; + 212 .loc 2 2074 3 is_stmt 1 view .LVU46 +2075:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SubPriorityBits; + 213 .loc 2 2075 3 view .LVU47 +2076:Drivers/CMSIS/Include/core_cm7.h **** +2077:Drivers/CMSIS/Include/core_cm7.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV + 214 .loc 2 2077 3 view .LVU48 + 215 .loc 2 2077 31 is_stmt 0 view .LVU49 + 216 0006 C0F1070C rsb ip, r0, #7 + 217 .loc 2 2077 23 view .LVU50 + 218 000a BCF1040F cmp ip, #4 + 219 000e 28BF it cs + 220 0010 4FF0040C movcs ip, #4 + 221 .LVL11: +2078:Drivers/CMSIS/Include/core_cm7.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint + 222 .loc 2 2078 3 is_stmt 1 view .LVU51 + 223 .loc 2 2078 44 is_stmt 0 view .LVU52 + 224 0014 031D adds r3, r0, #4 + 225 .loc 2 2078 109 view .LVU53 + 226 0016 062B cmp r3, #6 + 227 0018 0FD9 bls .L17 + 228 .loc 2 2078 109 discriminator 1 view .LVU54 + 229 001a C31E subs r3, r0, #3 + 230 .L16: + 231 .LVL12: +2079:Drivers/CMSIS/Include/core_cm7.h **** +2080:Drivers/CMSIS/Include/core_cm7.h **** return ( + 232 .loc 2 2080 3 is_stmt 1 view .LVU55 +2081:Drivers/CMSIS/Include/core_cm7.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits + 233 .loc 2 2081 30 is_stmt 0 view .LVU56 + 234 001c 4FF0FF3E mov lr, #-1 + 235 0020 0EFA0CF0 lsl r0, lr, ip + 236 .LVL13: + 237 .loc 2 2081 30 view .LVU57 + ARM GAS /tmp/ccB9Q52u.s page 57 + + + 238 0024 21EA0001 bic r1, r1, r0 + 239 .LVL14: + 240 .loc 2 2081 82 view .LVU58 + 241 0028 9940 lsls r1, r1, r3 +2082:Drivers/CMSIS/Include/core_cm7.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 242 .loc 2 2082 30 view .LVU59 + 243 002a 0EFA03FE lsl lr, lr, r3 + 244 002e 22EA0E02 bic r2, r2, lr + 245 .LVL15: +2083:Drivers/CMSIS/Include/core_cm7.h **** ); +2084:Drivers/CMSIS/Include/core_cm7.h **** } + 246 .loc 2 2084 1 view .LVU60 + 247 0032 41EA0200 orr r0, r1, r2 + 248 0036 5DF804FB ldr pc, [sp], #4 + 249 .LVL16: + 250 .L17: +2078:Drivers/CMSIS/Include/core_cm7.h **** + 251 .loc 2 2078 109 discriminator 2 view .LVU61 + 252 003a 0023 movs r3, #0 + 253 003c EEE7 b .L16 + 254 .cfi_endproc + 255 .LFE113: + 257 .section .text.NVIC_DecodePriority,"ax",%progbits + 258 .align 1 + 259 .syntax unified + 260 .thumb + 261 .thumb_func + 263 NVIC_DecodePriority: + 264 .LVL17: + 265 .LFB114: +2085:Drivers/CMSIS/Include/core_cm7.h **** +2086:Drivers/CMSIS/Include/core_cm7.h **** +2087:Drivers/CMSIS/Include/core_cm7.h **** /** +2088:Drivers/CMSIS/Include/core_cm7.h **** \brief Decode Priority +2089:Drivers/CMSIS/Include/core_cm7.h **** \details Decodes an interrupt priority value with a given priority group to +2090:Drivers/CMSIS/Include/core_cm7.h **** preemptive priority value and subpriority value. +2091:Drivers/CMSIS/Include/core_cm7.h **** In case of a conflict between priority grouping and available +2092:Drivers/CMSIS/Include/core_cm7.h **** priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. +2093:Drivers/CMSIS/Include/core_cm7.h **** \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC +2094:Drivers/CMSIS/Include/core_cm7.h **** \param [in] PriorityGroup Used priority group. +2095:Drivers/CMSIS/Include/core_cm7.h **** \param [out] pPreemptPriority Preemptive priority value (starting from 0). +2096:Drivers/CMSIS/Include/core_cm7.h **** \param [out] pSubPriority Subpriority value (starting from 0). +2097:Drivers/CMSIS/Include/core_cm7.h **** */ +2098:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons +2099:Drivers/CMSIS/Include/core_cm7.h **** { + 266 .loc 2 2099 1 is_stmt 1 view -0 + 267 .cfi_startproc + 268 @ args = 0, pretend = 0, frame = 0 + 269 @ frame_needed = 0, uses_anonymous_args = 0 + 270 .loc 2 2099 1 is_stmt 0 view .LVU63 + 271 0000 10B5 push {r4, lr} + 272 .LCFI1: + 273 .cfi_def_cfa_offset 8 + 274 .cfi_offset 4, -8 + 275 .cfi_offset 14, -4 +2100:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used + 276 .loc 2 2100 3 is_stmt 1 view .LVU64 + ARM GAS /tmp/ccB9Q52u.s page 58 + + + 277 .loc 2 2100 12 is_stmt 0 view .LVU65 + 278 0002 01F00701 and r1, r1, #7 + 279 .LVL18: +2101:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PreemptPriorityBits; + 280 .loc 2 2101 3 is_stmt 1 view .LVU66 +2102:Drivers/CMSIS/Include/core_cm7.h **** uint32_t SubPriorityBits; + 281 .loc 2 2102 3 view .LVU67 +2103:Drivers/CMSIS/Include/core_cm7.h **** +2104:Drivers/CMSIS/Include/core_cm7.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV + 282 .loc 2 2104 3 view .LVU68 + 283 .loc 2 2104 31 is_stmt 0 view .LVU69 + 284 0006 C1F1070C rsb ip, r1, #7 + 285 .loc 2 2104 23 view .LVU70 + 286 000a BCF1040F cmp ip, #4 + 287 000e 28BF it cs + 288 0010 4FF0040C movcs ip, #4 + 289 .LVL19: +2105:Drivers/CMSIS/Include/core_cm7.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint + 290 .loc 2 2105 3 is_stmt 1 view .LVU71 + 291 .loc 2 2105 44 is_stmt 0 view .LVU72 + 292 0014 0C1D adds r4, r1, #4 + 293 .loc 2 2105 109 view .LVU73 + 294 0016 062C cmp r4, #6 + 295 0018 0FD9 bls .L21 + 296 .loc 2 2105 109 discriminator 1 view .LVU74 + 297 001a 0339 subs r1, r1, #3 + 298 .LVL20: + 299 .L20: +2106:Drivers/CMSIS/Include/core_cm7.h **** +2107:Drivers/CMSIS/Include/core_cm7.h **** *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1 + 300 .loc 2 2107 3 is_stmt 1 view .LVU75 + 301 .loc 2 2107 33 is_stmt 0 view .LVU76 + 302 001c 20FA01F4 lsr r4, r0, r1 + 303 .LVL21: + 304 .loc 2 2107 53 view .LVU77 + 305 0020 4FF0FF3E mov lr, #-1 + 306 0024 0EFA0CFC lsl ip, lr, ip + 307 .LVL22: + 308 .loc 2 2107 53 view .LVU78 + 309 0028 24EA0C04 bic r4, r4, ip + 310 .loc 2 2107 21 view .LVU79 + 311 002c 1460 str r4, [r2] +2108:Drivers/CMSIS/Include/core_cm7.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 + 312 .loc 2 2108 3 is_stmt 1 view .LVU80 + 313 .loc 2 2108 53 is_stmt 0 view .LVU81 + 314 002e 0EFA01FE lsl lr, lr, r1 + 315 0032 20EA0E00 bic r0, r0, lr + 316 .LVL23: + 317 .loc 2 2108 21 view .LVU82 + 318 0036 1860 str r0, [r3] +2109:Drivers/CMSIS/Include/core_cm7.h **** } + 319 .loc 2 2109 1 view .LVU83 + 320 0038 10BD pop {r4, pc} + 321 .LVL24: + 322 .L21: +2105:Drivers/CMSIS/Include/core_cm7.h **** + 323 .loc 2 2105 109 discriminator 2 view .LVU84 + ARM GAS /tmp/ccB9Q52u.s page 59 + + + 324 003a 0021 movs r1, #0 + 325 .LVL25: +2105:Drivers/CMSIS/Include/core_cm7.h **** + 326 .loc 2 2105 109 discriminator 2 view .LVU85 + 327 003c EEE7 b .L20 + 328 .cfi_endproc + 329 .LFE114: + 331 .section .text.__NVIC_SystemReset,"ax",%progbits + 332 .align 1 + 333 .syntax unified + 334 .thumb + 335 .thumb_func + 337 __NVIC_SystemReset: + 338 .LFB117: +2110:Drivers/CMSIS/Include/core_cm7.h **** +2111:Drivers/CMSIS/Include/core_cm7.h **** +2112:Drivers/CMSIS/Include/core_cm7.h **** /** +2113:Drivers/CMSIS/Include/core_cm7.h **** \brief Set Interrupt Vector +2114:Drivers/CMSIS/Include/core_cm7.h **** \details Sets an interrupt vector in SRAM based interrupt vector table. +2115:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, +2116:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. +2117:Drivers/CMSIS/Include/core_cm7.h **** VTOR must been relocated to SRAM before. +2118:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number +2119:Drivers/CMSIS/Include/core_cm7.h **** \param [in] vector Address of interrupt handler function +2120:Drivers/CMSIS/Include/core_cm7.h **** */ +2121:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +2122:Drivers/CMSIS/Include/core_cm7.h **** { +2123:Drivers/CMSIS/Include/core_cm7.h **** uint32_t *vectors = (uint32_t *)SCB->VTOR; +2124:Drivers/CMSIS/Include/core_cm7.h **** vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +2125:Drivers/CMSIS/Include/core_cm7.h **** } +2126:Drivers/CMSIS/Include/core_cm7.h **** +2127:Drivers/CMSIS/Include/core_cm7.h **** +2128:Drivers/CMSIS/Include/core_cm7.h **** /** +2129:Drivers/CMSIS/Include/core_cm7.h **** \brief Get Interrupt Vector +2130:Drivers/CMSIS/Include/core_cm7.h **** \details Reads an interrupt vector from interrupt vector table. +2131:Drivers/CMSIS/Include/core_cm7.h **** The interrupt number can be positive to specify a device specific interrupt, +2132:Drivers/CMSIS/Include/core_cm7.h **** or negative to specify a processor exception. +2133:Drivers/CMSIS/Include/core_cm7.h **** \param [in] IRQn Interrupt number. +2134:Drivers/CMSIS/Include/core_cm7.h **** \return Address of interrupt handler function +2135:Drivers/CMSIS/Include/core_cm7.h **** */ +2136:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +2137:Drivers/CMSIS/Include/core_cm7.h **** { +2138:Drivers/CMSIS/Include/core_cm7.h **** uint32_t *vectors = (uint32_t *)SCB->VTOR; +2139:Drivers/CMSIS/Include/core_cm7.h **** return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +2140:Drivers/CMSIS/Include/core_cm7.h **** } +2141:Drivers/CMSIS/Include/core_cm7.h **** +2142:Drivers/CMSIS/Include/core_cm7.h **** +2143:Drivers/CMSIS/Include/core_cm7.h **** /** +2144:Drivers/CMSIS/Include/core_cm7.h **** \brief System Reset +2145:Drivers/CMSIS/Include/core_cm7.h **** \details Initiates a system reset request to reset the MCU. +2146:Drivers/CMSIS/Include/core_cm7.h **** */ +2147:Drivers/CMSIS/Include/core_cm7.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +2148:Drivers/CMSIS/Include/core_cm7.h **** { + 339 .loc 2 2148 1 is_stmt 1 view -0 + 340 .cfi_startproc + 341 @ Volatile: function does not return. + 342 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccB9Q52u.s page 60 + + + 343 @ frame_needed = 0, uses_anonymous_args = 0 + 344 @ link register save eliminated. +2149:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); /* Ensure all outstanding memor + 345 .loc 2 2149 3 view .LVU87 + 346 .LBB42: + 347 .LBI42: + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 348 .loc 3 877 27 view .LVU88 + 349 .LBB43: + 350 .loc 3 879 3 view .LVU89 + 351 .syntax unified + 352 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 353 0000 BFF34F8F dsb 0xF + 354 @ 0 "" 2 + 355 .thumb + 356 .syntax unified + 357 .LBE43: + 358 .LBE42: +2150:Drivers/CMSIS/Include/core_cm7.h **** buffered write are completed +2151:Drivers/CMSIS/Include/core_cm7.h **** SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 359 .loc 2 2151 3 view .LVU90 +2152:Drivers/CMSIS/Include/core_cm7.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + 360 .loc 2 2152 32 is_stmt 0 view .LVU91 + 361 0004 0549 ldr r1, .L25 + 362 0006 CA68 ldr r2, [r1, #12] + 363 .loc 2 2152 40 view .LVU92 + 364 0008 02F4E062 and r2, r2, #1792 +2151:Drivers/CMSIS/Include/core_cm7.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + 365 .loc 2 2151 17 view .LVU93 + 366 000c 044B ldr r3, .L25+4 + 367 000e 1343 orrs r3, r3, r2 +2151:Drivers/CMSIS/Include/core_cm7.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + 368 .loc 2 2151 15 view .LVU94 + 369 0010 CB60 str r3, [r1, #12] +2153:Drivers/CMSIS/Include/core_cm7.h **** SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchange +2154:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); /* Ensure completion of memory + 370 .loc 2 2154 3 is_stmt 1 view .LVU95 + 371 .LBB44: + 372 .LBI44: + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 373 .loc 3 877 27 view .LVU96 + 374 .LBB45: + 375 .loc 3 879 3 view .LVU97 + 376 .syntax unified + 377 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 378 0012 BFF34F8F dsb 0xF + 379 @ 0 "" 2 + 380 .thumb + 381 .syntax unified + 382 .L24: + 383 .LBE45: + 384 .LBE44: +2155:Drivers/CMSIS/Include/core_cm7.h **** +2156:Drivers/CMSIS/Include/core_cm7.h **** for(;;) /* wait until reset */ + 385 .loc 2 2156 3 view .LVU98 +2157:Drivers/CMSIS/Include/core_cm7.h **** { +2158:Drivers/CMSIS/Include/core_cm7.h **** __NOP(); + ARM GAS /tmp/ccB9Q52u.s page 61 + + + 386 .loc 2 2158 5 discriminator 1 view .LVU99 + 387 .syntax unified + 388 @ 2158 "Drivers/CMSIS/Include/core_cm7.h" 1 + 389 0016 00BF nop + 390 @ 0 "" 2 +2156:Drivers/CMSIS/Include/core_cm7.h **** { + 391 .loc 2 2156 3 view .LVU100 + 392 .thumb + 393 .syntax unified + 394 0018 FDE7 b .L24 + 395 .L26: + 396 001a 00BF .align 2 + 397 .L25: + 398 001c 00ED00E0 .word -536810240 + 399 0020 0400FA05 .word 100270084 + 400 .cfi_endproc + 401 .LFE117: + 403 .section .text.HAL_NVIC_SetPriorityGrouping,"ax",%progbits + 404 .align 1 + 405 .global HAL_NVIC_SetPriorityGrouping + 406 .syntax unified + 407 .thumb + 408 .thumb_func + 410 HAL_NVIC_SetPriorityGrouping: + 411 .LVL26: + 412 .LFB141: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @file stm32f7xx_hal_cortex.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief CORTEX HAL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * functionalities of the CORTEX: + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * + Peripheral Control functions + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** @verbatim + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ============================================================================== + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ##### How to use this driver ##### + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ============================================================================== + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** [..] + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** *** How to configure Interrupts using CORTEX HAL driver *** + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** =========================================================== + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** [..] + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** This section provides functions allowing to configure the NVIC interrupts (IRQ). + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** The Cortex-M4 exceptions are managed by CMSIS functions. + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** function according to the following table. + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (#) please refer to programming manual for details in how to configure priority. + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** The pending IRQ priority will be managed only by the sub priority. + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + ARM GAS /tmp/ccB9Q52u.s page 62 + + + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** -@- IRQ priority order (sorted by highest to lowest priority): + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (+@) Lowest preemption priority + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (+@) Lowest sub priority + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (+@) Lowest hardware priority (IRQ number) + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** [..] + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** *** How to configure Systick using CORTEX HAL driver *** + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ======================================================== + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** [..] + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** Setup SysTick Timer for time base. + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** is a CMSIS function that: + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (++) Configures the SysTick Reload register with value passed as function parameter. + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (++) Configures the SysTick IRQ priority to the lowest value (0x0F). + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (++) Resets the SysTick Counter register. + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (++) Enables the SysTick Interrupt. + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (++) Starts the SysTick Counter. + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** inside the stm32f7xx_hal_cortex.h file. + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (+) You can change the SysTick IRQ priority by calling the + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS funct + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (+) To adjust the SysTick time base, use the following formula: + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (++) Reload Value should not exceed 0xFFFFFF + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** @endverbatim + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ****************************************************************************** + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @attention + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * Copyright (c) 2017 STMicroelectronics. + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * All rights reserved. + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * This software is licensed under terms that can be found in the LICENSE file in + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * the root directory of this software component. + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ****************************************************************************** + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Includes ------------------------------------------------------------------*/ + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** #include "stm32f7xx_hal.h" + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** @addtogroup STM32F7xx_HAL_Driver + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @{ + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** @defgroup CORTEX CORTEX + ARM GAS /tmp/ccB9Q52u.s page 63 + + + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief CORTEX HAL module driver + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @{ + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** #ifdef HAL_CORTEX_MODULE_ENABLED + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Private types -------------------------------------------------------------*/ + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Private variables ---------------------------------------------------------*/ + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Private constants ---------------------------------------------------------*/ + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Private macros ------------------------------------------------------------*/ + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Private functions ---------------------------------------------------------*/ + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Exported functions --------------------------------------------------------*/ + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @{ + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Initialization and Configuration functions + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** @verbatim + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ============================================================================== + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ##### Initialization and de-initialization functions ##### + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ============================================================================== + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** [..] + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** This section provides the CORTEX HAL driver functions allowing to configure Interrupts + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** Systick functionalities + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** @endverbatim + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @{ + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Sets the priority grouping field (preemption priority and subpriority) + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * using the required unlock sequence. + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @param PriorityGroup The priority grouping bits length. + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * This parameter can be one of the following values: + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * 4 bits for subpriority + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * 3 bits for subpriority + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * 2 bits for subpriority + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * 1 bits for subpriority + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * 0 bits for subpriority + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * The pending IRQ priority will be managed only by the subpriority. + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval None + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 413 .loc 1 143 1 view -0 + 414 .cfi_startproc + ARM GAS /tmp/ccB9Q52u.s page 64 + + + 415 @ args = 0, pretend = 0, frame = 0 + 416 @ frame_needed = 0, uses_anonymous_args = 0 + 417 @ link register save eliminated. + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Check the parameters */ + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + 418 .loc 1 145 3 view .LVU102 + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** NVIC_SetPriorityGrouping(PriorityGroup); + 419 .loc 1 148 3 view .LVU103 + 420 .LBB46: + 421 .LBI46: +1865:Drivers/CMSIS/Include/core_cm7.h **** { + 422 .loc 2 1865 22 view .LVU104 + 423 .LBB47: +1867:Drivers/CMSIS/Include/core_cm7.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a + 424 .loc 2 1867 3 view .LVU105 +1868:Drivers/CMSIS/Include/core_cm7.h **** + 425 .loc 2 1868 3 view .LVU106 +1870:Drivers/CMSIS/Include/core_cm7.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan + 426 .loc 2 1870 3 view .LVU107 +1870:Drivers/CMSIS/Include/core_cm7.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan + 427 .loc 2 1870 14 is_stmt 0 view .LVU108 + 428 0000 0649 ldr r1, .L28 + 429 0002 CB68 ldr r3, [r1, #12] + 430 .LVL27: +1871:Drivers/CMSIS/Include/core_cm7.h **** reg_value = (reg_value | + 431 .loc 2 1871 3 is_stmt 1 view .LVU109 +1871:Drivers/CMSIS/Include/core_cm7.h **** reg_value = (reg_value | + 432 .loc 2 1871 13 is_stmt 0 view .LVU110 + 433 0004 23F4E063 bic r3, r3, #1792 + 434 .LVL28: +1871:Drivers/CMSIS/Include/core_cm7.h **** reg_value = (reg_value | + 435 .loc 2 1871 13 view .LVU111 + 436 0008 1B04 lsls r3, r3, #16 + 437 000a 1B0C lsrs r3, r3, #16 + 438 .LVL29: +1872:Drivers/CMSIS/Include/core_cm7.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 439 .loc 2 1872 3 is_stmt 1 view .LVU112 +1874:Drivers/CMSIS/Include/core_cm7.h **** SCB->AIRCR = reg_value; + 440 .loc 2 1874 35 is_stmt 0 view .LVU113 + 441 000c 0002 lsls r0, r0, #8 + 442 .LVL30: +1874:Drivers/CMSIS/Include/core_cm7.h **** SCB->AIRCR = reg_value; + 443 .loc 2 1874 35 view .LVU114 + 444 000e 00F4E060 and r0, r0, #1792 +1873:Drivers/CMSIS/Include/core_cm7.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a + 445 .loc 2 1873 62 view .LVU115 + 446 0012 0343 orrs r3, r3, r0 + 447 .LVL31: +1872:Drivers/CMSIS/Include/core_cm7.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 448 .loc 2 1872 14 view .LVU116 + 449 0014 024A ldr r2, .L28+4 + 450 0016 1A43 orrs r2, r2, r3 + 451 .LVL32: +1875:Drivers/CMSIS/Include/core_cm7.h **** } + 452 .loc 2 1875 3 is_stmt 1 view .LVU117 + ARM GAS /tmp/ccB9Q52u.s page 65 + + +1875:Drivers/CMSIS/Include/core_cm7.h **** } + 453 .loc 2 1875 14 is_stmt 0 view .LVU118 + 454 0018 CA60 str r2, [r1, #12] + 455 .LVL33: +1875:Drivers/CMSIS/Include/core_cm7.h **** } + 456 .loc 2 1875 14 view .LVU119 + 457 .LBE47: + 458 .LBE46: + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 459 .loc 1 149 1 view .LVU120 + 460 001a 7047 bx lr + 461 .L29: + 462 .align 2 + 463 .L28: + 464 001c 00ED00E0 .word -536810240 + 465 0020 0000FA05 .word 100270080 + 466 .cfi_endproc + 467 .LFE141: + 469 .section .text.HAL_NVIC_SetPriority,"ax",%progbits + 470 .align 1 + 471 .global HAL_NVIC_SetPriority + 472 .syntax unified + 473 .thumb + 474 .thumb_func + 476 HAL_NVIC_SetPriority: + 477 .LVL34: + 478 .LFB142: + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Sets the priority of an interrupt. + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @param IRQn External interrupt number. + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @param PreemptPriority The preemption priority for the IRQn channel. + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * This parameter can be a value between 0 and 15 + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * A lower priority value indicates a higher priority + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @param SubPriority the subpriority level for the IRQ channel. + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * This parameter can be a value between 0 and 15 + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * A lower priority value indicates a higher priority. + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval None + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 479 .loc 1 165 1 is_stmt 1 view -0 + 480 .cfi_startproc + 481 @ args = 0, pretend = 0, frame = 0 + 482 @ frame_needed = 0, uses_anonymous_args = 0 + 483 .loc 1 165 1 is_stmt 0 view .LVU122 + 484 0000 10B5 push {r4, lr} + 485 .LCFI2: + 486 .cfi_def_cfa_offset 8 + 487 .cfi_offset 4, -8 + 488 .cfi_offset 14, -4 + 489 0002 0446 mov r4, r0 + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** uint32_t prioritygroup = 0x00; + 490 .loc 1 166 3 is_stmt 1 view .LVU123 + 491 .LVL35: + ARM GAS /tmp/ccB9Q52u.s page 66 + + + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Check the parameters */ + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + 492 .loc 1 169 3 view .LVU124 + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + 493 .loc 1 170 3 view .LVU125 + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** prioritygroup = NVIC_GetPriorityGrouping(); + 494 .loc 1 172 3 view .LVU126 + 495 .LBB48: + 496 .LBI48: +1884:Drivers/CMSIS/Include/core_cm7.h **** { + 497 .loc 2 1884 26 view .LVU127 + 498 .LBB49: +1886:Drivers/CMSIS/Include/core_cm7.h **** } + 499 .loc 2 1886 3 view .LVU128 +1886:Drivers/CMSIS/Include/core_cm7.h **** } + 500 .loc 2 1886 26 is_stmt 0 view .LVU129 + 501 0004 054B ldr r3, .L32 + 502 0006 D868 ldr r0, [r3, #12] + 503 .LVL36: +1886:Drivers/CMSIS/Include/core_cm7.h **** } + 504 .loc 2 1886 26 view .LVU130 + 505 .LBE49: + 506 .LBE48: + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 507 .loc 1 174 3 is_stmt 1 view .LVU131 + 508 0008 C0F30220 ubfx r0, r0, #8, #3 + 509 .LVL37: + 510 .loc 1 174 3 is_stmt 0 view .LVU132 + 511 000c FFF7FEFF bl NVIC_EncodePriority + 512 .LVL38: + 513 .loc 1 174 3 view .LVU133 + 514 0010 0146 mov r1, r0 + 515 .loc 1 174 3 discriminator 1 view .LVU134 + 516 0012 2046 mov r0, r4 + 517 0014 FFF7FEFF bl __NVIC_SetPriority + 518 .LVL39: + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 519 .loc 1 175 1 view .LVU135 + 520 0018 10BD pop {r4, pc} + 521 .LVL40: + 522 .L33: + 523 .loc 1 175 1 view .LVU136 + 524 001a 00BF .align 2 + 525 .L32: + 526 001c 00ED00E0 .word -536810240 + 527 .cfi_endproc + 528 .LFE142: + 530 .section .text.HAL_NVIC_EnableIRQ,"ax",%progbits + 531 .align 1 + 532 .global HAL_NVIC_EnableIRQ + 533 .syntax unified + 534 .thumb + 535 .thumb_func + 537 HAL_NVIC_EnableIRQ: + ARM GAS /tmp/ccB9Q52u.s page 67 + + + 538 .LVL41: + 539 .LFB143: + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Enables a device specific interrupt in the NVIC interrupt controller. + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * function should be called before. + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @param IRQn External interrupt number. + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval None + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 540 .loc 1 187 1 is_stmt 1 view -0 + 541 .cfi_startproc + 542 @ args = 0, pretend = 0, frame = 0 + 543 @ frame_needed = 0, uses_anonymous_args = 0 + 544 @ link register save eliminated. + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Check the parameters */ + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 545 .loc 1 189 3 view .LVU138 + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Enable interrupt */ + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** NVIC_EnableIRQ(IRQn); + 546 .loc 1 192 3 view .LVU139 + 547 .LBB50: + 548 .LBI50: +1896:Drivers/CMSIS/Include/core_cm7.h **** { + 549 .loc 2 1896 22 view .LVU140 + 550 .LBB51: +1898:Drivers/CMSIS/Include/core_cm7.h **** { + 551 .loc 2 1898 3 view .LVU141 +1898:Drivers/CMSIS/Include/core_cm7.h **** { + 552 .loc 2 1898 6 is_stmt 0 view .LVU142 + 553 0000 0028 cmp r0, #0 +1898:Drivers/CMSIS/Include/core_cm7.h **** { + 554 .loc 2 1898 6 view .LVU143 + 555 0002 07DB blt .L34 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 556 .loc 2 1900 5 is_stmt 1 view .LVU144 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 557 .loc 2 1900 81 is_stmt 0 view .LVU145 + 558 0004 00F01F02 and r2, r0, #31 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 559 .loc 2 1900 34 view .LVU146 + 560 0008 4009 lsrs r0, r0, #5 + 561 .LVL42: +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 562 .loc 2 1900 45 view .LVU147 + 563 000a 0123 movs r3, #1 + 564 000c 9340 lsls r3, r3, r2 +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 565 .loc 2 1900 43 view .LVU148 + 566 000e 024A ldr r2, .L36 + 567 0010 42F82030 str r3, [r2, r0, lsl #2] + 568 .LVL43: + ARM GAS /tmp/ccB9Q52u.s page 68 + + + 569 .L34: +1900:Drivers/CMSIS/Include/core_cm7.h **** } + 570 .loc 2 1900 43 view .LVU149 + 571 .LBE51: + 572 .LBE50: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 573 .loc 1 193 1 view .LVU150 + 574 0014 7047 bx lr + 575 .L37: + 576 0016 00BF .align 2 + 577 .L36: + 578 0018 00E100E0 .word -536813312 + 579 .cfi_endproc + 580 .LFE143: + 582 .section .text.HAL_NVIC_DisableIRQ,"ax",%progbits + 583 .align 1 + 584 .global HAL_NVIC_DisableIRQ + 585 .syntax unified + 586 .thumb + 587 .thumb_func + 589 HAL_NVIC_DisableIRQ: + 590 .LVL44: + 591 .LFB144: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Disables a device specific interrupt in the NVIC interrupt controller. + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @param IRQn External interrupt number. + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval None + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 592 .loc 1 203 1 is_stmt 1 view -0 + 593 .cfi_startproc + 594 @ args = 0, pretend = 0, frame = 0 + 595 @ frame_needed = 0, uses_anonymous_args = 0 + 596 .loc 1 203 1 is_stmt 0 view .LVU152 + 597 0000 08B5 push {r3, lr} + 598 .LCFI3: + 599 .cfi_def_cfa_offset 8 + 600 .cfi_offset 3, -8 + 601 .cfi_offset 14, -4 + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Check the parameters */ + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 602 .loc 1 205 3 is_stmt 1 view .LVU153 + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Disable interrupt */ + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** NVIC_DisableIRQ(IRQn); + 603 .loc 1 208 3 view .LVU154 + 604 0002 FFF7FEFF bl __NVIC_DisableIRQ + 605 .LVL45: + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 606 .loc 1 209 1 is_stmt 0 view .LVU155 + 607 0006 08BD pop {r3, pc} + 608 .cfi_endproc + 609 .LFE144: + ARM GAS /tmp/ccB9Q52u.s page 69 + + + 611 .section .text.HAL_NVIC_SystemReset,"ax",%progbits + 612 .align 1 + 613 .global HAL_NVIC_SystemReset + 614 .syntax unified + 615 .thumb + 616 .thumb_func + 618 HAL_NVIC_SystemReset: + 619 .LFB145: + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Initiates a system reset request to reset the MCU. + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval None + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_NVIC_SystemReset(void) + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 620 .loc 1 216 1 is_stmt 1 view -0 + 621 .cfi_startproc + 622 @ Volatile: function does not return. + 623 @ args = 0, pretend = 0, frame = 0 + 624 @ frame_needed = 0, uses_anonymous_args = 0 + 625 0000 08B5 push {r3, lr} + 626 .LCFI4: + 627 .cfi_def_cfa_offset 8 + 628 .cfi_offset 3, -8 + 629 .cfi_offset 14, -4 + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* System Reset */ + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** NVIC_SystemReset(); + 630 .loc 1 218 3 view .LVU157 + 631 0002 FFF7FEFF bl __NVIC_SystemReset + 632 .LVL46: + 633 .cfi_endproc + 634 .LFE145: + 636 .section .text.HAL_SYSTICK_Config,"ax",%progbits + 637 .align 1 + 638 .global HAL_SYSTICK_Config + 639 .syntax unified + 640 .thumb + 641 .thumb_func + 643 HAL_SYSTICK_Config: + 644 .LVL47: + 645 .LFB146: + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * Counter is in free running mode to generate periodic interrupts. + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval status: - 0 Function succeeded. + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * - 1 Function failed. + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 646 .loc 1 229 1 view -0 + 647 .cfi_startproc + 648 @ args = 0, pretend = 0, frame = 0 + 649 @ frame_needed = 0, uses_anonymous_args = 0 + 650 @ link register save eliminated. + ARM GAS /tmp/ccB9Q52u.s page 70 + + + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** return SysTick_Config(TicksNumb); + 651 .loc 1 230 4 view .LVU159 + 652 .LBB52: + 653 .LBI52: +2159:Drivers/CMSIS/Include/core_cm7.h **** } +2160:Drivers/CMSIS/Include/core_cm7.h **** } +2161:Drivers/CMSIS/Include/core_cm7.h **** +2162:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of CMSIS_Core_NVICFunctions */ +2163:Drivers/CMSIS/Include/core_cm7.h **** +2164:Drivers/CMSIS/Include/core_cm7.h **** /* ########################## MPU functions #################################### */ +2165:Drivers/CMSIS/Include/core_cm7.h **** +2166:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +2167:Drivers/CMSIS/Include/core_cm7.h **** +2168:Drivers/CMSIS/Include/core_cm7.h **** #include "mpu_armv7.h" +2169:Drivers/CMSIS/Include/core_cm7.h **** +2170:Drivers/CMSIS/Include/core_cm7.h **** #endif +2171:Drivers/CMSIS/Include/core_cm7.h **** +2172:Drivers/CMSIS/Include/core_cm7.h **** /* ########################## FPU functions #################################### */ +2173:Drivers/CMSIS/Include/core_cm7.h **** /** +2174:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_Core_FunctionInterface +2175:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_FpuFunctions FPU Functions +2176:Drivers/CMSIS/Include/core_cm7.h **** \brief Function that provides FPU type. +2177:Drivers/CMSIS/Include/core_cm7.h **** @{ +2178:Drivers/CMSIS/Include/core_cm7.h **** */ +2179:Drivers/CMSIS/Include/core_cm7.h **** +2180:Drivers/CMSIS/Include/core_cm7.h **** /** +2181:Drivers/CMSIS/Include/core_cm7.h **** \brief get FPU type +2182:Drivers/CMSIS/Include/core_cm7.h **** \details returns the FPU type +2183:Drivers/CMSIS/Include/core_cm7.h **** \returns +2184:Drivers/CMSIS/Include/core_cm7.h **** - \b 0: No FPU +2185:Drivers/CMSIS/Include/core_cm7.h **** - \b 1: Single precision FPU +2186:Drivers/CMSIS/Include/core_cm7.h **** - \b 2: Double + Single precision FPU +2187:Drivers/CMSIS/Include/core_cm7.h **** */ +2188:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t SCB_GetFPUType(void) +2189:Drivers/CMSIS/Include/core_cm7.h **** { +2190:Drivers/CMSIS/Include/core_cm7.h **** uint32_t mvfr0; +2191:Drivers/CMSIS/Include/core_cm7.h **** +2192:Drivers/CMSIS/Include/core_cm7.h **** mvfr0 = SCB->MVFR0; +2193:Drivers/CMSIS/Include/core_cm7.h **** if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) +2194:Drivers/CMSIS/Include/core_cm7.h **** { +2195:Drivers/CMSIS/Include/core_cm7.h **** return 2U; /* Double + Single precision FPU */ +2196:Drivers/CMSIS/Include/core_cm7.h **** } +2197:Drivers/CMSIS/Include/core_cm7.h **** else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) +2198:Drivers/CMSIS/Include/core_cm7.h **** { +2199:Drivers/CMSIS/Include/core_cm7.h **** return 1U; /* Single precision FPU */ +2200:Drivers/CMSIS/Include/core_cm7.h **** } +2201:Drivers/CMSIS/Include/core_cm7.h **** else +2202:Drivers/CMSIS/Include/core_cm7.h **** { +2203:Drivers/CMSIS/Include/core_cm7.h **** return 0U; /* No FPU */ +2204:Drivers/CMSIS/Include/core_cm7.h **** } +2205:Drivers/CMSIS/Include/core_cm7.h **** } +2206:Drivers/CMSIS/Include/core_cm7.h **** +2207:Drivers/CMSIS/Include/core_cm7.h **** +2208:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of CMSIS_Core_FpuFunctions */ +2209:Drivers/CMSIS/Include/core_cm7.h **** +2210:Drivers/CMSIS/Include/core_cm7.h **** +2211:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccB9Q52u.s page 71 + + +2212:Drivers/CMSIS/Include/core_cm7.h **** /* ########################## Cache functions #################################### */ +2213:Drivers/CMSIS/Include/core_cm7.h **** /** +2214:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_Core_FunctionInterface +2215:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_CacheFunctions Cache Functions +2216:Drivers/CMSIS/Include/core_cm7.h **** \brief Functions that configure Instruction and Data cache. +2217:Drivers/CMSIS/Include/core_cm7.h **** @{ +2218:Drivers/CMSIS/Include/core_cm7.h **** */ +2219:Drivers/CMSIS/Include/core_cm7.h **** +2220:Drivers/CMSIS/Include/core_cm7.h **** /* Cache Size ID Register Macros */ +2221:Drivers/CMSIS/Include/core_cm7.h **** #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Po +2222:Drivers/CMSIS/Include/core_cm7.h **** #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos +2223:Drivers/CMSIS/Include/core_cm7.h **** +2224:Drivers/CMSIS/Include/core_cm7.h **** +2225:Drivers/CMSIS/Include/core_cm7.h **** /** +2226:Drivers/CMSIS/Include/core_cm7.h **** \brief Enable I-Cache +2227:Drivers/CMSIS/Include/core_cm7.h **** \details Turns on I-Cache +2228:Drivers/CMSIS/Include/core_cm7.h **** */ +2229:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_EnableICache (void) +2230:Drivers/CMSIS/Include/core_cm7.h **** { +2231:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) +2232:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2233:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2234:Drivers/CMSIS/Include/core_cm7.h **** SCB->ICIALLU = 0UL; /* invalidate I-Cache */ +2235:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2236:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2237:Drivers/CMSIS/Include/core_cm7.h **** SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ +2238:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2239:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2240:Drivers/CMSIS/Include/core_cm7.h **** #endif +2241:Drivers/CMSIS/Include/core_cm7.h **** } +2242:Drivers/CMSIS/Include/core_cm7.h **** +2243:Drivers/CMSIS/Include/core_cm7.h **** +2244:Drivers/CMSIS/Include/core_cm7.h **** /** +2245:Drivers/CMSIS/Include/core_cm7.h **** \brief Disable I-Cache +2246:Drivers/CMSIS/Include/core_cm7.h **** \details Turns off I-Cache +2247:Drivers/CMSIS/Include/core_cm7.h **** */ +2248:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_DisableICache (void) +2249:Drivers/CMSIS/Include/core_cm7.h **** { +2250:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) +2251:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2252:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2253:Drivers/CMSIS/Include/core_cm7.h **** SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ +2254:Drivers/CMSIS/Include/core_cm7.h **** SCB->ICIALLU = 0UL; /* invalidate I-Cache */ +2255:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2256:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2257:Drivers/CMSIS/Include/core_cm7.h **** #endif +2258:Drivers/CMSIS/Include/core_cm7.h **** } +2259:Drivers/CMSIS/Include/core_cm7.h **** +2260:Drivers/CMSIS/Include/core_cm7.h **** +2261:Drivers/CMSIS/Include/core_cm7.h **** /** +2262:Drivers/CMSIS/Include/core_cm7.h **** \brief Invalidate I-Cache +2263:Drivers/CMSIS/Include/core_cm7.h **** \details Invalidates I-Cache +2264:Drivers/CMSIS/Include/core_cm7.h **** */ +2265:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_InvalidateICache (void) +2266:Drivers/CMSIS/Include/core_cm7.h **** { +2267:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) +2268:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); + ARM GAS /tmp/ccB9Q52u.s page 72 + + +2269:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2270:Drivers/CMSIS/Include/core_cm7.h **** SCB->ICIALLU = 0UL; +2271:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2272:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2273:Drivers/CMSIS/Include/core_cm7.h **** #endif +2274:Drivers/CMSIS/Include/core_cm7.h **** } +2275:Drivers/CMSIS/Include/core_cm7.h **** +2276:Drivers/CMSIS/Include/core_cm7.h **** +2277:Drivers/CMSIS/Include/core_cm7.h **** /** +2278:Drivers/CMSIS/Include/core_cm7.h **** \brief Enable D-Cache +2279:Drivers/CMSIS/Include/core_cm7.h **** \details Turns on D-Cache +2280:Drivers/CMSIS/Include/core_cm7.h **** */ +2281:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_EnableDCache (void) +2282:Drivers/CMSIS/Include/core_cm7.h **** { +2283:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) +2284:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ccsidr; +2285:Drivers/CMSIS/Include/core_cm7.h **** uint32_t sets; +2286:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ways; +2287:Drivers/CMSIS/Include/core_cm7.h **** +2288:Drivers/CMSIS/Include/core_cm7.h **** SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ +2289:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2290:Drivers/CMSIS/Include/core_cm7.h **** +2291:Drivers/CMSIS/Include/core_cm7.h **** ccsidr = SCB->CCSIDR; +2292:Drivers/CMSIS/Include/core_cm7.h **** +2293:Drivers/CMSIS/Include/core_cm7.h **** /* invalidate D-Cache */ +2294:Drivers/CMSIS/Include/core_cm7.h **** sets = (uint32_t)(CCSIDR_SETS(ccsidr)); +2295:Drivers/CMSIS/Include/core_cm7.h **** do { +2296:Drivers/CMSIS/Include/core_cm7.h **** ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); +2297:Drivers/CMSIS/Include/core_cm7.h **** do { +2298:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | +2299:Drivers/CMSIS/Include/core_cm7.h **** ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); +2300:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM ) +2301:Drivers/CMSIS/Include/core_cm7.h **** __schedule_barrier(); +2302:Drivers/CMSIS/Include/core_cm7.h **** #endif +2303:Drivers/CMSIS/Include/core_cm7.h **** } while (ways-- != 0U); +2304:Drivers/CMSIS/Include/core_cm7.h **** } while(sets-- != 0U); +2305:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2306:Drivers/CMSIS/Include/core_cm7.h **** +2307:Drivers/CMSIS/Include/core_cm7.h **** SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ +2308:Drivers/CMSIS/Include/core_cm7.h **** +2309:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2310:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2311:Drivers/CMSIS/Include/core_cm7.h **** #endif +2312:Drivers/CMSIS/Include/core_cm7.h **** } +2313:Drivers/CMSIS/Include/core_cm7.h **** +2314:Drivers/CMSIS/Include/core_cm7.h **** +2315:Drivers/CMSIS/Include/core_cm7.h **** /** +2316:Drivers/CMSIS/Include/core_cm7.h **** \brief Disable D-Cache +2317:Drivers/CMSIS/Include/core_cm7.h **** \details Turns off D-Cache +2318:Drivers/CMSIS/Include/core_cm7.h **** */ +2319:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_DisableDCache (void) +2320:Drivers/CMSIS/Include/core_cm7.h **** { +2321:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) +2322:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ccsidr; +2323:Drivers/CMSIS/Include/core_cm7.h **** uint32_t sets; +2324:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ways; +2325:Drivers/CMSIS/Include/core_cm7.h **** + ARM GAS /tmp/ccB9Q52u.s page 73 + + +2326:Drivers/CMSIS/Include/core_cm7.h **** SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ +2327:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2328:Drivers/CMSIS/Include/core_cm7.h **** +2329:Drivers/CMSIS/Include/core_cm7.h **** SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ +2330:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2331:Drivers/CMSIS/Include/core_cm7.h **** +2332:Drivers/CMSIS/Include/core_cm7.h **** ccsidr = SCB->CCSIDR; +2333:Drivers/CMSIS/Include/core_cm7.h **** +2334:Drivers/CMSIS/Include/core_cm7.h **** /* clean & invalidate D-Cache */ +2335:Drivers/CMSIS/Include/core_cm7.h **** sets = (uint32_t)(CCSIDR_SETS(ccsidr)); +2336:Drivers/CMSIS/Include/core_cm7.h **** do { +2337:Drivers/CMSIS/Include/core_cm7.h **** ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); +2338:Drivers/CMSIS/Include/core_cm7.h **** do { +2339:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | +2340:Drivers/CMSIS/Include/core_cm7.h **** ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); +2341:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM ) +2342:Drivers/CMSIS/Include/core_cm7.h **** __schedule_barrier(); +2343:Drivers/CMSIS/Include/core_cm7.h **** #endif +2344:Drivers/CMSIS/Include/core_cm7.h **** } while (ways-- != 0U); +2345:Drivers/CMSIS/Include/core_cm7.h **** } while(sets-- != 0U); +2346:Drivers/CMSIS/Include/core_cm7.h **** +2347:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2348:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2349:Drivers/CMSIS/Include/core_cm7.h **** #endif +2350:Drivers/CMSIS/Include/core_cm7.h **** } +2351:Drivers/CMSIS/Include/core_cm7.h **** +2352:Drivers/CMSIS/Include/core_cm7.h **** +2353:Drivers/CMSIS/Include/core_cm7.h **** /** +2354:Drivers/CMSIS/Include/core_cm7.h **** \brief Invalidate D-Cache +2355:Drivers/CMSIS/Include/core_cm7.h **** \details Invalidates D-Cache +2356:Drivers/CMSIS/Include/core_cm7.h **** */ +2357:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_InvalidateDCache (void) +2358:Drivers/CMSIS/Include/core_cm7.h **** { +2359:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) +2360:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ccsidr; +2361:Drivers/CMSIS/Include/core_cm7.h **** uint32_t sets; +2362:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ways; +2363:Drivers/CMSIS/Include/core_cm7.h **** +2364:Drivers/CMSIS/Include/core_cm7.h **** SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ +2365:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2366:Drivers/CMSIS/Include/core_cm7.h **** +2367:Drivers/CMSIS/Include/core_cm7.h **** ccsidr = SCB->CCSIDR; +2368:Drivers/CMSIS/Include/core_cm7.h **** +2369:Drivers/CMSIS/Include/core_cm7.h **** /* invalidate D-Cache */ +2370:Drivers/CMSIS/Include/core_cm7.h **** sets = (uint32_t)(CCSIDR_SETS(ccsidr)); +2371:Drivers/CMSIS/Include/core_cm7.h **** do { +2372:Drivers/CMSIS/Include/core_cm7.h **** ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); +2373:Drivers/CMSIS/Include/core_cm7.h **** do { +2374:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | +2375:Drivers/CMSIS/Include/core_cm7.h **** ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); +2376:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM ) +2377:Drivers/CMSIS/Include/core_cm7.h **** __schedule_barrier(); +2378:Drivers/CMSIS/Include/core_cm7.h **** #endif +2379:Drivers/CMSIS/Include/core_cm7.h **** } while (ways-- != 0U); +2380:Drivers/CMSIS/Include/core_cm7.h **** } while(sets-- != 0U); +2381:Drivers/CMSIS/Include/core_cm7.h **** +2382:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); + ARM GAS /tmp/ccB9Q52u.s page 74 + + +2383:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2384:Drivers/CMSIS/Include/core_cm7.h **** #endif +2385:Drivers/CMSIS/Include/core_cm7.h **** } +2386:Drivers/CMSIS/Include/core_cm7.h **** +2387:Drivers/CMSIS/Include/core_cm7.h **** +2388:Drivers/CMSIS/Include/core_cm7.h **** /** +2389:Drivers/CMSIS/Include/core_cm7.h **** \brief Clean D-Cache +2390:Drivers/CMSIS/Include/core_cm7.h **** \details Cleans D-Cache +2391:Drivers/CMSIS/Include/core_cm7.h **** */ +2392:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_CleanDCache (void) +2393:Drivers/CMSIS/Include/core_cm7.h **** { +2394:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) +2395:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ccsidr; +2396:Drivers/CMSIS/Include/core_cm7.h **** uint32_t sets; +2397:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ways; +2398:Drivers/CMSIS/Include/core_cm7.h **** +2399:Drivers/CMSIS/Include/core_cm7.h **** SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ +2400:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2401:Drivers/CMSIS/Include/core_cm7.h **** +2402:Drivers/CMSIS/Include/core_cm7.h **** ccsidr = SCB->CCSIDR; +2403:Drivers/CMSIS/Include/core_cm7.h **** +2404:Drivers/CMSIS/Include/core_cm7.h **** /* clean D-Cache */ +2405:Drivers/CMSIS/Include/core_cm7.h **** sets = (uint32_t)(CCSIDR_SETS(ccsidr)); +2406:Drivers/CMSIS/Include/core_cm7.h **** do { +2407:Drivers/CMSIS/Include/core_cm7.h **** ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); +2408:Drivers/CMSIS/Include/core_cm7.h **** do { +2409:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | +2410:Drivers/CMSIS/Include/core_cm7.h **** ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); +2411:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM ) +2412:Drivers/CMSIS/Include/core_cm7.h **** __schedule_barrier(); +2413:Drivers/CMSIS/Include/core_cm7.h **** #endif +2414:Drivers/CMSIS/Include/core_cm7.h **** } while (ways-- != 0U); +2415:Drivers/CMSIS/Include/core_cm7.h **** } while(sets-- != 0U); +2416:Drivers/CMSIS/Include/core_cm7.h **** +2417:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2418:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2419:Drivers/CMSIS/Include/core_cm7.h **** #endif +2420:Drivers/CMSIS/Include/core_cm7.h **** } +2421:Drivers/CMSIS/Include/core_cm7.h **** +2422:Drivers/CMSIS/Include/core_cm7.h **** +2423:Drivers/CMSIS/Include/core_cm7.h **** /** +2424:Drivers/CMSIS/Include/core_cm7.h **** \brief Clean & Invalidate D-Cache +2425:Drivers/CMSIS/Include/core_cm7.h **** \details Cleans and Invalidates D-Cache +2426:Drivers/CMSIS/Include/core_cm7.h **** */ +2427:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_CleanInvalidateDCache (void) +2428:Drivers/CMSIS/Include/core_cm7.h **** { +2429:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) +2430:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ccsidr; +2431:Drivers/CMSIS/Include/core_cm7.h **** uint32_t sets; +2432:Drivers/CMSIS/Include/core_cm7.h **** uint32_t ways; +2433:Drivers/CMSIS/Include/core_cm7.h **** +2434:Drivers/CMSIS/Include/core_cm7.h **** SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ +2435:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2436:Drivers/CMSIS/Include/core_cm7.h **** +2437:Drivers/CMSIS/Include/core_cm7.h **** ccsidr = SCB->CCSIDR; +2438:Drivers/CMSIS/Include/core_cm7.h **** +2439:Drivers/CMSIS/Include/core_cm7.h **** /* clean & invalidate D-Cache */ + ARM GAS /tmp/ccB9Q52u.s page 75 + + +2440:Drivers/CMSIS/Include/core_cm7.h **** sets = (uint32_t)(CCSIDR_SETS(ccsidr)); +2441:Drivers/CMSIS/Include/core_cm7.h **** do { +2442:Drivers/CMSIS/Include/core_cm7.h **** ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); +2443:Drivers/CMSIS/Include/core_cm7.h **** do { +2444:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | +2445:Drivers/CMSIS/Include/core_cm7.h **** ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); +2446:Drivers/CMSIS/Include/core_cm7.h **** #if defined ( __CC_ARM ) +2447:Drivers/CMSIS/Include/core_cm7.h **** __schedule_barrier(); +2448:Drivers/CMSIS/Include/core_cm7.h **** #endif +2449:Drivers/CMSIS/Include/core_cm7.h **** } while (ways-- != 0U); +2450:Drivers/CMSIS/Include/core_cm7.h **** } while(sets-- != 0U); +2451:Drivers/CMSIS/Include/core_cm7.h **** +2452:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2453:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2454:Drivers/CMSIS/Include/core_cm7.h **** #endif +2455:Drivers/CMSIS/Include/core_cm7.h **** } +2456:Drivers/CMSIS/Include/core_cm7.h **** +2457:Drivers/CMSIS/Include/core_cm7.h **** +2458:Drivers/CMSIS/Include/core_cm7.h **** /** +2459:Drivers/CMSIS/Include/core_cm7.h **** \brief D-Cache Invalidate by address +2460:Drivers/CMSIS/Include/core_cm7.h **** \details Invalidates D-Cache for the given address +2461:Drivers/CMSIS/Include/core_cm7.h **** \param[in] addr address (aligned to 32-byte boundary) +2462:Drivers/CMSIS/Include/core_cm7.h **** \param[in] dsize size of memory block (in number of bytes) +2463:Drivers/CMSIS/Include/core_cm7.h **** */ +2464:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +2465:Drivers/CMSIS/Include/core_cm7.h **** { +2466:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) +2467:Drivers/CMSIS/Include/core_cm7.h **** int32_t op_size = dsize; +2468:Drivers/CMSIS/Include/core_cm7.h **** uint32_t op_addr = (uint32_t)addr; +2469:Drivers/CMSIS/Include/core_cm7.h **** int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words ( +2470:Drivers/CMSIS/Include/core_cm7.h **** +2471:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2472:Drivers/CMSIS/Include/core_cm7.h **** +2473:Drivers/CMSIS/Include/core_cm7.h **** while (op_size > 0) { +2474:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCIMVAC = op_addr; +2475:Drivers/CMSIS/Include/core_cm7.h **** op_addr += (uint32_t)linesize; +2476:Drivers/CMSIS/Include/core_cm7.h **** op_size -= linesize; +2477:Drivers/CMSIS/Include/core_cm7.h **** } +2478:Drivers/CMSIS/Include/core_cm7.h **** +2479:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2480:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2481:Drivers/CMSIS/Include/core_cm7.h **** #endif +2482:Drivers/CMSIS/Include/core_cm7.h **** } +2483:Drivers/CMSIS/Include/core_cm7.h **** +2484:Drivers/CMSIS/Include/core_cm7.h **** +2485:Drivers/CMSIS/Include/core_cm7.h **** /** +2486:Drivers/CMSIS/Include/core_cm7.h **** \brief D-Cache Clean by address +2487:Drivers/CMSIS/Include/core_cm7.h **** \details Cleans D-Cache for the given address +2488:Drivers/CMSIS/Include/core_cm7.h **** \param[in] addr address (aligned to 32-byte boundary) +2489:Drivers/CMSIS/Include/core_cm7.h **** \param[in] dsize size of memory block (in number of bytes) +2490:Drivers/CMSIS/Include/core_cm7.h **** */ +2491:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +2492:Drivers/CMSIS/Include/core_cm7.h **** { +2493:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) +2494:Drivers/CMSIS/Include/core_cm7.h **** int32_t op_size = dsize; +2495:Drivers/CMSIS/Include/core_cm7.h **** uint32_t op_addr = (uint32_t) addr; +2496:Drivers/CMSIS/Include/core_cm7.h **** int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words ( + ARM GAS /tmp/ccB9Q52u.s page 76 + + +2497:Drivers/CMSIS/Include/core_cm7.h **** +2498:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2499:Drivers/CMSIS/Include/core_cm7.h **** +2500:Drivers/CMSIS/Include/core_cm7.h **** while (op_size > 0) { +2501:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCCMVAC = op_addr; +2502:Drivers/CMSIS/Include/core_cm7.h **** op_addr += (uint32_t)linesize; +2503:Drivers/CMSIS/Include/core_cm7.h **** op_size -= linesize; +2504:Drivers/CMSIS/Include/core_cm7.h **** } +2505:Drivers/CMSIS/Include/core_cm7.h **** +2506:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2507:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2508:Drivers/CMSIS/Include/core_cm7.h **** #endif +2509:Drivers/CMSIS/Include/core_cm7.h **** } +2510:Drivers/CMSIS/Include/core_cm7.h **** +2511:Drivers/CMSIS/Include/core_cm7.h **** +2512:Drivers/CMSIS/Include/core_cm7.h **** /** +2513:Drivers/CMSIS/Include/core_cm7.h **** \brief D-Cache Clean and Invalidate by address +2514:Drivers/CMSIS/Include/core_cm7.h **** \details Cleans and invalidates D_Cache for the given address +2515:Drivers/CMSIS/Include/core_cm7.h **** \param[in] addr address (aligned to 32-byte boundary) +2516:Drivers/CMSIS/Include/core_cm7.h **** \param[in] dsize size of memory block (in number of bytes) +2517:Drivers/CMSIS/Include/core_cm7.h **** */ +2518:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +2519:Drivers/CMSIS/Include/core_cm7.h **** { +2520:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) +2521:Drivers/CMSIS/Include/core_cm7.h **** int32_t op_size = dsize; +2522:Drivers/CMSIS/Include/core_cm7.h **** uint32_t op_addr = (uint32_t) addr; +2523:Drivers/CMSIS/Include/core_cm7.h **** int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words ( +2524:Drivers/CMSIS/Include/core_cm7.h **** +2525:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2526:Drivers/CMSIS/Include/core_cm7.h **** +2527:Drivers/CMSIS/Include/core_cm7.h **** while (op_size > 0) { +2528:Drivers/CMSIS/Include/core_cm7.h **** SCB->DCCIMVAC = op_addr; +2529:Drivers/CMSIS/Include/core_cm7.h **** op_addr += (uint32_t)linesize; +2530:Drivers/CMSIS/Include/core_cm7.h **** op_size -= linesize; +2531:Drivers/CMSIS/Include/core_cm7.h **** } +2532:Drivers/CMSIS/Include/core_cm7.h **** +2533:Drivers/CMSIS/Include/core_cm7.h **** __DSB(); +2534:Drivers/CMSIS/Include/core_cm7.h **** __ISB(); +2535:Drivers/CMSIS/Include/core_cm7.h **** #endif +2536:Drivers/CMSIS/Include/core_cm7.h **** } +2537:Drivers/CMSIS/Include/core_cm7.h **** +2538:Drivers/CMSIS/Include/core_cm7.h **** +2539:Drivers/CMSIS/Include/core_cm7.h **** /*@} end of CMSIS_Core_CacheFunctions */ +2540:Drivers/CMSIS/Include/core_cm7.h **** +2541:Drivers/CMSIS/Include/core_cm7.h **** +2542:Drivers/CMSIS/Include/core_cm7.h **** +2543:Drivers/CMSIS/Include/core_cm7.h **** /* ################################## SysTick function ######################################## +2544:Drivers/CMSIS/Include/core_cm7.h **** /** +2545:Drivers/CMSIS/Include/core_cm7.h **** \ingroup CMSIS_Core_FunctionInterface +2546:Drivers/CMSIS/Include/core_cm7.h **** \defgroup CMSIS_Core_SysTickFunctions SysTick Functions +2547:Drivers/CMSIS/Include/core_cm7.h **** \brief Functions that configure the System. +2548:Drivers/CMSIS/Include/core_cm7.h **** @{ +2549:Drivers/CMSIS/Include/core_cm7.h **** */ +2550:Drivers/CMSIS/Include/core_cm7.h **** +2551:Drivers/CMSIS/Include/core_cm7.h **** #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) +2552:Drivers/CMSIS/Include/core_cm7.h **** +2553:Drivers/CMSIS/Include/core_cm7.h **** /** + ARM GAS /tmp/ccB9Q52u.s page 77 + + +2554:Drivers/CMSIS/Include/core_cm7.h **** \brief System Tick Configuration +2555:Drivers/CMSIS/Include/core_cm7.h **** \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. +2556:Drivers/CMSIS/Include/core_cm7.h **** Counter is in free running mode to generate periodic interrupts. +2557:Drivers/CMSIS/Include/core_cm7.h **** \param [in] ticks Number of ticks between two interrupts. +2558:Drivers/CMSIS/Include/core_cm7.h **** \return 0 Function succeeded. +2559:Drivers/CMSIS/Include/core_cm7.h **** \return 1 Function failed. +2560:Drivers/CMSIS/Include/core_cm7.h **** \note When the variable __Vendor_SysTickConfig is set to 1, then the +2561:Drivers/CMSIS/Include/core_cm7.h **** function SysTick_Config is not included. In this case, the file device. +2562:Drivers/CMSIS/Include/core_cm7.h **** must contain a vendor-specific implementation of this function. +2563:Drivers/CMSIS/Include/core_cm7.h **** */ +2564:Drivers/CMSIS/Include/core_cm7.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) + 654 .loc 2 2564 26 view .LVU160 + 655 .LBB53: +2565:Drivers/CMSIS/Include/core_cm7.h **** { +2566:Drivers/CMSIS/Include/core_cm7.h **** if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 656 .loc 2 2566 3 view .LVU161 + 657 .loc 2 2566 14 is_stmt 0 view .LVU162 + 658 0000 0138 subs r0, r0, #1 + 659 .LVL48: + 660 .loc 2 2566 6 view .LVU163 + 661 0002 B0F1807F cmp r0, #16777216 + 662 0006 0BD2 bcs .L44 +2567:Drivers/CMSIS/Include/core_cm7.h **** { +2568:Drivers/CMSIS/Include/core_cm7.h **** return (1UL); /* Reload value impossible */ +2569:Drivers/CMSIS/Include/core_cm7.h **** } +2570:Drivers/CMSIS/Include/core_cm7.h **** +2571:Drivers/CMSIS/Include/core_cm7.h **** SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 663 .loc 2 2571 3 is_stmt 1 view .LVU164 + 664 .loc 2 2571 18 is_stmt 0 view .LVU165 + 665 0008 4FF0E023 mov r3, #-536813568 + 666 000c 5861 str r0, [r3, #20] +2572:Drivers/CMSIS/Include/core_cm7.h **** NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int + 667 .loc 2 2572 3 is_stmt 1 view .LVU166 + 668 .LVL49: + 669 .LBB54: + 670 .LBI54: +2024:Drivers/CMSIS/Include/core_cm7.h **** { + 671 .loc 2 2024 22 view .LVU167 + 672 .LBB55: +2026:Drivers/CMSIS/Include/core_cm7.h **** { + 673 .loc 2 2026 3 view .LVU168 +2032:Drivers/CMSIS/Include/core_cm7.h **** } + 674 .loc 2 2032 5 view .LVU169 +2032:Drivers/CMSIS/Include/core_cm7.h **** } + 675 .loc 2 2032 47 is_stmt 0 view .LVU170 + 676 000e 054A ldr r2, .L45 + 677 0010 F021 movs r1, #240 + 678 0012 82F82310 strb r1, [r2, #35] + 679 .LVL50: +2032:Drivers/CMSIS/Include/core_cm7.h **** } + 680 .loc 2 2032 47 view .LVU171 + 681 .LBE55: + 682 .LBE54: +2573:Drivers/CMSIS/Include/core_cm7.h **** SysTick->VAL = 0UL; /* Load the SysTick Counter Val + 683 .loc 2 2573 3 is_stmt 1 view .LVU172 + 684 .loc 2 2573 18 is_stmt 0 view .LVU173 + 685 0016 0020 movs r0, #0 + ARM GAS /tmp/ccB9Q52u.s page 78 + + + 686 .LVL51: + 687 .loc 2 2573 18 view .LVU174 + 688 0018 9861 str r0, [r3, #24] +2574:Drivers/CMSIS/Include/core_cm7.h **** SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 689 .loc 2 2574 3 is_stmt 1 view .LVU175 + 690 .loc 2 2574 18 is_stmt 0 view .LVU176 + 691 001a 0722 movs r2, #7 + 692 001c 1A61 str r2, [r3, #16] +2575:Drivers/CMSIS/Include/core_cm7.h **** SysTick_CTRL_TICKINT_Msk | +2576:Drivers/CMSIS/Include/core_cm7.h **** SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTi +2577:Drivers/CMSIS/Include/core_cm7.h **** return (0UL); /* Function successful */ + 693 .loc 2 2577 3 is_stmt 1 view .LVU177 + 694 .loc 2 2577 10 is_stmt 0 view .LVU178 + 695 001e 7047 bx lr + 696 .L44: +2568:Drivers/CMSIS/Include/core_cm7.h **** } + 697 .loc 2 2568 12 view .LVU179 + 698 0020 0120 movs r0, #1 + 699 .LVL52: +2568:Drivers/CMSIS/Include/core_cm7.h **** } + 700 .loc 2 2568 12 view .LVU180 + 701 .LBE53: + 702 .LBE52: + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 703 .loc 1 231 1 view .LVU181 + 704 0022 7047 bx lr + 705 .L46: + 706 .align 2 + 707 .L45: + 708 0024 00ED00E0 .word -536810240 + 709 .cfi_endproc + 710 .LFE146: + 712 .section .text.HAL_MPU_Disable,"ax",%progbits + 713 .align 1 + 714 .global HAL_MPU_Disable + 715 .syntax unified + 716 .thumb + 717 .thumb_func + 719 HAL_MPU_Disable: + 720 .LFB147: + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @} + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Cortex control functions + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** @verbatim + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ============================================================================== + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ##### Peripheral Control functions ##### + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ============================================================================== + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** [..] + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** This subsection provides a set of functions allowing to control the CORTEX + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** (NVIC, SYSTICK, MPU) functionalities. + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** @endverbatim + ARM GAS /tmp/ccB9Q52u.s page 79 + + + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @{ + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** #if (__MPU_PRESENT == 1) + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Disables the MPU + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval None + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_MPU_Disable(void) + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 721 .loc 1 258 1 is_stmt 1 view -0 + 722 .cfi_startproc + 723 @ args = 0, pretend = 0, frame = 0 + 724 @ frame_needed = 0, uses_anonymous_args = 0 + 725 @ link register save eliminated. + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Make sure outstanding transfers are done */ + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** __DMB(); + 726 .loc 1 260 3 view .LVU183 + 727 .LBB56: + 728 .LBI56: + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 881:Drivers/CMSIS/Include/cmsis_gcc.h **** + 882:Drivers/CMSIS/Include/cmsis_gcc.h **** + 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier + 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. + 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) + 729 .loc 3 888 27 view .LVU184 + 730 .LBB57: + 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); + 731 .loc 3 890 3 view .LVU185 + 732 .syntax unified + 733 @ 890 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 734 0000 BFF35F8F dmb 0xF + 735 @ 0 "" 2 + 736 .thumb + 737 .syntax unified + 738 .LBE57: + 739 .LBE56: + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Disable fault exceptions */ + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + 740 .loc 1 263 3 view .LVU186 + 741 .loc 1 263 6 is_stmt 0 view .LVU187 + 742 0004 044B ldr r3, .L48 + 743 0006 5A6A ldr r2, [r3, #36] + 744 .loc 1 263 14 view .LVU188 + 745 0008 22F48032 bic r2, r2, #65536 + 746 000c 5A62 str r2, [r3, #36] + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Disable the MPU and clear the control register*/ + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** MPU->CTRL = 0; + 747 .loc 1 266 3 is_stmt 1 view .LVU189 + 748 .loc 1 266 13 is_stmt 0 view .LVU190 + ARM GAS /tmp/ccB9Q52u.s page 80 + + + 749 000e 0022 movs r2, #0 + 750 0010 C3F89420 str r2, [r3, #148] + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 751 .loc 1 267 1 view .LVU191 + 752 0014 7047 bx lr + 753 .L49: + 754 0016 00BF .align 2 + 755 .L48: + 756 0018 00ED00E0 .word -536810240 + 757 .cfi_endproc + 758 .LFE147: + 760 .section .text.HAL_MPU_Enable,"ax",%progbits + 761 .align 1 + 762 .global HAL_MPU_Enable + 763 .syntax unified + 764 .thumb + 765 .thumb_func + 767 HAL_MPU_Enable: + 768 .LVL53: + 769 .LFB148: + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Enables the MPU + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @param MPU_Control Specifies the control mode of the MPU during hard fault, + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * NMI, FAULTMASK and privileged access to the default memory + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * This parameter can be one of the following values: + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF_NONE + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @arg MPU_HARDFAULT_NMI + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @arg MPU_PRIVILEGED_DEFAULT + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval None + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_MPU_Enable(uint32_t MPU_Control) + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 770 .loc 1 281 1 is_stmt 1 view -0 + 771 .cfi_startproc + 772 @ args = 0, pretend = 0, frame = 0 + 773 @ frame_needed = 0, uses_anonymous_args = 0 + 774 @ link register save eliminated. + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Enable the MPU */ + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + 775 .loc 1 283 3 view .LVU193 + 776 .loc 1 283 27 is_stmt 0 view .LVU194 + 777 0000 40F00100 orr r0, r0, #1 + 778 .LVL54: + 779 .loc 1 283 13 view .LVU195 + 780 0004 054B ldr r3, .L51 + 781 0006 C3F89400 str r0, [r3, #148] + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Enable fault exceptions */ + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + 782 .loc 1 286 3 is_stmt 1 view .LVU196 + 783 .loc 1 286 6 is_stmt 0 view .LVU197 + 784 000a 5A6A ldr r2, [r3, #36] + 785 .loc 1 286 14 view .LVU198 + 786 000c 42F48032 orr r2, r2, #65536 + 787 0010 5A62 str r2, [r3, #36] + ARM GAS /tmp/ccB9Q52u.s page 81 + + + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Ensure MPU setting take effects */ + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** __DSB(); + 788 .loc 1 289 3 is_stmt 1 view .LVU199 + 789 .LBB58: + 790 .LBI58: + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 791 .loc 3 877 27 view .LVU200 + 792 .LBB59: + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 793 .loc 3 879 3 view .LVU201 + 794 .syntax unified + 795 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 796 0012 BFF34F8F dsb 0xF + 797 @ 0 "" 2 + 798 .thumb + 799 .syntax unified + 800 .LBE59: + 801 .LBE58: + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** __ISB(); + 802 .loc 1 290 3 view .LVU202 + 803 .LBB60: + 804 .LBI60: + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 805 .loc 3 866 27 view .LVU203 + 806 .LBB61: + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 807 .loc 3 868 3 view .LVU204 + 808 .syntax unified + 809 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 810 0016 BFF36F8F isb 0xF + 811 @ 0 "" 2 + 812 .thumb + 813 .syntax unified + 814 .LBE61: + 815 .LBE60: + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 816 .loc 1 291 1 is_stmt 0 view .LVU205 + 817 001a 7047 bx lr + 818 .L52: + 819 .align 2 + 820 .L51: + 821 001c 00ED00E0 .word -536810240 + 822 .cfi_endproc + 823 .LFE148: + 825 .section .text.HAL_MPU_EnableRegion,"ax",%progbits + 826 .align 1 + 827 .global HAL_MPU_EnableRegion + 828 .syntax unified + 829 .thumb + 830 .thumb_func + 832 HAL_MPU_EnableRegion: + 833 .LVL55: + 834 .LFB149: + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Enables the MPU Region. + ARM GAS /tmp/ccB9Q52u.s page 82 + + + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval None + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_MPU_EnableRegion(uint32_t RegionNumber) + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 835 .loc 1 298 1 is_stmt 1 view -0 + 836 .cfi_startproc + 837 @ args = 0, pretend = 0, frame = 0 + 838 @ frame_needed = 0, uses_anonymous_args = 0 + 839 @ link register save eliminated. + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Check the parameters */ + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + 840 .loc 1 300 3 view .LVU207 + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Set the Region number */ + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** MPU->RNR = RegionNumber; + 841 .loc 1 303 3 view .LVU208 + 842 .loc 1 303 12 is_stmt 0 view .LVU209 + 843 0000 044B ldr r3, .L54 + 844 0002 C3F89800 str r0, [r3, #152] + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Enable the Region */ + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); + 845 .loc 1 306 3 is_stmt 1 view .LVU210 + 846 0006 D3F8A020 ldr r2, [r3, #160] + 847 000a 42F00102 orr r2, r2, #1 + 848 000e C3F8A020 str r2, [r3, #160] + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 849 .loc 1 307 1 is_stmt 0 view .LVU211 + 850 0012 7047 bx lr + 851 .L55: + 852 .align 2 + 853 .L54: + 854 0014 00ED00E0 .word -536810240 + 855 .cfi_endproc + 856 .LFE149: + 858 .section .text.HAL_MPU_DisableRegion,"ax",%progbits + 859 .align 1 + 860 .global HAL_MPU_DisableRegion + 861 .syntax unified + 862 .thumb + 863 .thumb_func + 865 HAL_MPU_DisableRegion: + 866 .LVL56: + 867 .LFB150: + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Disables the MPU Region. + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval None + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_MPU_DisableRegion(uint32_t RegionNumber) + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 868 .loc 1 314 1 is_stmt 1 view -0 + 869 .cfi_startproc + 870 @ args = 0, pretend = 0, frame = 0 + 871 @ frame_needed = 0, uses_anonymous_args = 0 + 872 @ link register save eliminated. + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Check the parameters */ + ARM GAS /tmp/ccB9Q52u.s page 83 + + + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + 873 .loc 1 316 3 view .LVU213 + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Set the Region number */ + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** MPU->RNR = RegionNumber; + 874 .loc 1 319 3 view .LVU214 + 875 .loc 1 319 12 is_stmt 0 view .LVU215 + 876 0000 044B ldr r3, .L57 + 877 0002 C3F89800 str r0, [r3, #152] + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Disable the Region */ + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); + 878 .loc 1 322 3 is_stmt 1 view .LVU216 + 879 0006 D3F8A020 ldr r2, [r3, #160] + 880 000a 22F00102 bic r2, r2, #1 + 881 000e C3F8A020 str r2, [r3, #160] + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 882 .loc 1 323 1 is_stmt 0 view .LVU217 + 883 0012 7047 bx lr + 884 .L58: + 885 .align 2 + 886 .L57: + 887 0014 00ED00E0 .word -536810240 + 888 .cfi_endproc + 889 .LFE150: + 891 .section .text.HAL_MPU_ConfigRegion,"ax",%progbits + 892 .align 1 + 893 .global HAL_MPU_ConfigRegion + 894 .syntax unified + 895 .thumb + 896 .thumb_func + 898 HAL_MPU_ConfigRegion: + 899 .LVL57: + 900 .LFB151: + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Initializes and configures the Region and the memory to be protected. + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * the initialization and configuration information. + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval None + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 901 .loc 1 332 1 is_stmt 1 view -0 + 902 .cfi_startproc + 903 @ args = 0, pretend = 0, frame = 0 + 904 @ frame_needed = 0, uses_anonymous_args = 0 + 905 @ link register save eliminated. + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Check the parameters */ + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + 906 .loc 1 334 3 view .LVU219 + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + 907 .loc 1 335 3 view .LVU220 + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + 908 .loc 1 336 3 view .LVU221 + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + 909 .loc 1 337 3 view .LVU222 + ARM GAS /tmp/ccB9Q52u.s page 84 + + + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + 910 .loc 1 338 3 view .LVU223 + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + 911 .loc 1 339 3 view .LVU224 + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + 912 .loc 1 340 3 view .LVU225 + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + 913 .loc 1 341 3 view .LVU226 + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + 914 .loc 1 342 3 view .LVU227 + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + 915 .loc 1 343 3 view .LVU228 + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Set the Region number */ + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** MPU->RNR = MPU_Init->Number; + 916 .loc 1 346 3 view .LVU229 + 917 .loc 1 346 22 is_stmt 0 view .LVU230 + 918 0000 4378 ldrb r3, [r0, #1] @ zero_extendqisi2 + 919 .loc 1 346 12 view .LVU231 + 920 0002 144A ldr r2, .L60 + 921 0004 C2F89830 str r3, [r2, #152] + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Disable the Region */ + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); + 922 .loc 1 349 3 is_stmt 1 view .LVU232 + 923 0008 D2F8A030 ldr r3, [r2, #160] + 924 000c 23F00103 bic r3, r3, #1 + 925 0010 C2F8A030 str r3, [r2, #160] + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Apply configuration */ + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** MPU->RBAR = MPU_Init->BaseAddress; + 926 .loc 1 352 3 view .LVU233 + 927 .loc 1 352 23 is_stmt 0 view .LVU234 + 928 0014 4368 ldr r3, [r0, #4] + 929 .loc 1 352 13 view .LVU235 + 930 0016 C2F89C30 str r3, [r2, #156] + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + 931 .loc 1 353 3 is_stmt 1 view .LVU236 + 932 .loc 1 353 34 is_stmt 0 view .LVU237 + 933 001a 017B ldrb r1, [r0, #12] @ zero_extendqisi2 + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 934 .loc 1 354 34 view .LVU238 + 935 001c C37A ldrb r3, [r0, #11] @ zero_extendqisi2 + 936 .loc 1 354 60 view .LVU239 + 937 001e 1B06 lsls r3, r3, #24 + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + 938 .loc 1 353 82 view .LVU240 + 939 0020 43EA0173 orr r3, r3, r1, lsl #28 + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + 940 .loc 1 355 34 view .LVU241 + 941 0024 817A ldrb r1, [r0, #10] @ zero_extendqisi2 + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 942 .loc 1 354 82 view .LVU242 + 943 0026 43EAC143 orr r3, r3, r1, lsl #19 + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + 944 .loc 1 356 34 view .LVU243 + 945 002a 417B ldrb r1, [r0, #13] @ zero_extendqisi2 + ARM GAS /tmp/ccB9Q52u.s page 85 + + + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + 946 .loc 1 355 82 view .LVU244 + 947 002c 43EA8143 orr r3, r3, r1, lsl #18 + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + 948 .loc 1 357 34 view .LVU245 + 949 0030 817B ldrb r1, [r0, #14] @ zero_extendqisi2 + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + 950 .loc 1 356 82 view .LVU246 + 951 0032 43EA4143 orr r3, r3, r1, lsl #17 + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + 952 .loc 1 358 34 view .LVU247 + 953 0036 C17B ldrb r1, [r0, #15] @ zero_extendqisi2 + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + 954 .loc 1 357 82 view .LVU248 + 955 0038 43EA0143 orr r3, r3, r1, lsl #16 + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + 956 .loc 1 359 34 view .LVU249 + 957 003c 417A ldrb r1, [r0, #9] @ zero_extendqisi2 + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + 958 .loc 1 358 82 view .LVU250 + 959 003e 43EA0123 orr r3, r3, r1, lsl #8 + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + 960 .loc 1 360 34 view .LVU251 + 961 0042 017A ldrb r1, [r0, #8] @ zero_extendqisi2 + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + 962 .loc 1 359 82 view .LVU252 + 963 0044 43EA4103 orr r3, r3, r1, lsl #1 + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + 964 .loc 1 361 34 view .LVU253 + 965 0048 0178 ldrb r1, [r0] @ zero_extendqisi2 + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + 966 .loc 1 360 82 view .LVU254 + 967 004a 0B43 orrs r3, r3, r1 + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 968 .loc 1 353 13 view .LVU255 + 969 004c C2F8A030 str r3, [r2, #160] + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 970 .loc 1 362 1 view .LVU256 + 971 0050 7047 bx lr + 972 .L61: + 973 0052 00BF .align 2 + 974 .L60: + 975 0054 00ED00E0 .word -536810240 + 976 .cfi_endproc + 977 .LFE151: + 979 .section .text.HAL_NVIC_GetPriorityGrouping,"ax",%progbits + 980 .align 1 + 981 .global HAL_NVIC_GetPriorityGrouping + 982 .syntax unified + 983 .thumb + 984 .thumb_func + 986 HAL_NVIC_GetPriorityGrouping: + 987 .LFB152: + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** #endif /* __MPU_PRESENT */ + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Gets the priority grouping field from the NVIC Interrupt Controller. + ARM GAS /tmp/ccB9Q52u.s page 86 + + + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPriorityGrouping(void) + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 988 .loc 1 370 1 is_stmt 1 view -0 + 989 .cfi_startproc + 990 @ args = 0, pretend = 0, frame = 0 + 991 @ frame_needed = 0, uses_anonymous_args = 0 + 992 @ link register save eliminated. + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Get the PRIGROUP[10:8] field value */ + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** return NVIC_GetPriorityGrouping(); + 993 .loc 1 372 3 view .LVU258 + 994 .LBB62: + 995 .LBI62: +1884:Drivers/CMSIS/Include/core_cm7.h **** { + 996 .loc 2 1884 26 view .LVU259 + 997 .LBB63: +1886:Drivers/CMSIS/Include/core_cm7.h **** } + 998 .loc 2 1886 3 view .LVU260 +1886:Drivers/CMSIS/Include/core_cm7.h **** } + 999 .loc 2 1886 26 is_stmt 0 view .LVU261 + 1000 0000 024B ldr r3, .L63 + 1001 0002 D868 ldr r0, [r3, #12] + 1002 .LBE63: + 1003 .LBE62: + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 1004 .loc 1 373 1 view .LVU262 + 1005 0004 C0F30220 ubfx r0, r0, #8, #3 + 1006 0008 7047 bx lr + 1007 .L64: + 1008 000a 00BF .align 2 + 1009 .L63: + 1010 000c 00ED00E0 .word -536810240 + 1011 .cfi_endproc + 1012 .LFE152: + 1014 .section .text.HAL_NVIC_GetPriority,"ax",%progbits + 1015 .align 1 + 1016 .global HAL_NVIC_GetPriority + 1017 .syntax unified + 1018 .thumb + 1019 .thumb_func + 1021 HAL_NVIC_GetPriority: + 1022 .LVL58: + 1023 .LFB153: + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Gets the priority of an interrupt. + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @param IRQn External interrupt number. + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @param PriorityGroup the priority grouping bits length. + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * This parameter can be one of the following values: + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * 4 bits for subpriority + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * 3 bits for subpriority + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + ARM GAS /tmp/ccB9Q52u.s page 87 + + + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * 2 bits for subpriority + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * 1 bits for subpriority + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * 0 bits for subpriority + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @param pSubPriority Pointer on the Subpriority value (starting from 0). + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval None + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint3 + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 1024 .loc 1 397 1 is_stmt 1 view -0 + 1025 .cfi_startproc + 1026 @ args = 0, pretend = 0, frame = 0 + 1027 @ frame_needed = 0, uses_anonymous_args = 0 + 1028 .loc 1 397 1 is_stmt 0 view .LVU264 + 1029 0000 70B5 push {r4, r5, r6, lr} + 1030 .LCFI5: + 1031 .cfi_def_cfa_offset 16 + 1032 .cfi_offset 4, -16 + 1033 .cfi_offset 5, -12 + 1034 .cfi_offset 6, -8 + 1035 .cfi_offset 14, -4 + 1036 0002 0C46 mov r4, r1 + 1037 0004 1546 mov r5, r2 + 1038 0006 1E46 mov r6, r3 + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Check the parameters */ + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + 1039 .loc 1 399 3 is_stmt 1 view .LVU265 + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Get priority for Cortex-M system or device specific interrupts */ + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); + 1040 .loc 1 401 3 view .LVU266 + 1041 0008 FFF7FEFF bl __NVIC_GetPriority + 1042 .LVL59: + 1043 .loc 1 401 3 is_stmt 0 discriminator 1 view .LVU267 + 1044 000c 3346 mov r3, r6 + 1045 000e 2A46 mov r2, r5 + 1046 0010 2146 mov r1, r4 + 1047 0012 FFF7FEFF bl NVIC_DecodePriority + 1048 .LVL60: + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 1049 .loc 1 402 1 view .LVU268 + 1050 0016 70BD pop {r4, r5, r6, pc} + 1051 .loc 1 402 1 view .LVU269 + 1052 .cfi_endproc + 1053 .LFE153: + 1055 .section .text.HAL_NVIC_SetPendingIRQ,"ax",%progbits + 1056 .align 1 + 1057 .global HAL_NVIC_SetPendingIRQ + 1058 .syntax unified + 1059 .thumb + 1060 .thumb_func + 1062 HAL_NVIC_SetPendingIRQ: + 1063 .LVL61: + 1064 .LFB154: + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + ARM GAS /tmp/ccB9Q52u.s page 88 + + + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Sets Pending bit of an external interrupt. + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @param IRQn External interrupt number + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval None + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 1065 .loc 1 412 1 is_stmt 1 view -0 + 1066 .cfi_startproc + 1067 @ args = 0, pretend = 0, frame = 0 + 1068 @ frame_needed = 0, uses_anonymous_args = 0 + 1069 @ link register save eliminated. + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Check the parameters */ + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 1070 .loc 1 414 3 view .LVU271 + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Set interrupt pending */ + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** NVIC_SetPendingIRQ(IRQn); + 1071 .loc 1 417 3 view .LVU272 + 1072 .LBB64: + 1073 .LBI64: +1970:Drivers/CMSIS/Include/core_cm7.h **** { + 1074 .loc 2 1970 22 view .LVU273 + 1075 .LBB65: +1972:Drivers/CMSIS/Include/core_cm7.h **** { + 1076 .loc 2 1972 3 view .LVU274 +1972:Drivers/CMSIS/Include/core_cm7.h **** { + 1077 .loc 2 1972 6 is_stmt 0 view .LVU275 + 1078 0000 0028 cmp r0, #0 +1972:Drivers/CMSIS/Include/core_cm7.h **** { + 1079 .loc 2 1972 6 view .LVU276 + 1080 0002 08DB blt .L67 +1974:Drivers/CMSIS/Include/core_cm7.h **** } + 1081 .loc 2 1974 5 is_stmt 1 view .LVU277 +1974:Drivers/CMSIS/Include/core_cm7.h **** } + 1082 .loc 2 1974 81 is_stmt 0 view .LVU278 + 1083 0004 00F01F02 and r2, r0, #31 +1974:Drivers/CMSIS/Include/core_cm7.h **** } + 1084 .loc 2 1974 34 view .LVU279 + 1085 0008 4009 lsrs r0, r0, #5 + 1086 .LVL62: +1974:Drivers/CMSIS/Include/core_cm7.h **** } + 1087 .loc 2 1974 45 view .LVU280 + 1088 000a 0123 movs r3, #1 + 1089 000c 9340 lsls r3, r3, r2 +1974:Drivers/CMSIS/Include/core_cm7.h **** } + 1090 .loc 2 1974 43 view .LVU281 + 1091 000e 4030 adds r0, r0, #64 + 1092 0010 014A ldr r2, .L69 + 1093 0012 42F82030 str r3, [r2, r0, lsl #2] + 1094 .LVL63: + 1095 .L67: +1974:Drivers/CMSIS/Include/core_cm7.h **** } + 1096 .loc 2 1974 43 view .LVU282 + 1097 .LBE65: + 1098 .LBE64: + ARM GAS /tmp/ccB9Q52u.s page 89 + + + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 1099 .loc 1 418 1 view .LVU283 + 1100 0016 7047 bx lr + 1101 .L70: + 1102 .align 2 + 1103 .L69: + 1104 0018 00E100E0 .word -536813312 + 1105 .cfi_endproc + 1106 .LFE154: + 1108 .section .text.HAL_NVIC_GetPendingIRQ,"ax",%progbits + 1109 .align 1 + 1110 .global HAL_NVIC_GetPendingIRQ + 1111 .syntax unified + 1112 .thumb + 1113 .thumb_func + 1115 HAL_NVIC_GetPendingIRQ: + 1116 .LVL64: + 1117 .LFB155: + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Gets Pending Interrupt (reads the pending register in the NVIC + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * and returns the pending bit for the specified interrupt). + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @param IRQn External interrupt number. + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval status: - 0 Interrupt status is not pending. + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * - 1 Interrupt status is pending. + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 1118 .loc 1 430 1 is_stmt 1 view -0 + 1119 .cfi_startproc + 1120 @ args = 0, pretend = 0, frame = 0 + 1121 @ frame_needed = 0, uses_anonymous_args = 0 + 1122 @ link register save eliminated. + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Check the parameters */ + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 1123 .loc 1 432 3 view .LVU285 + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Return 1 if pending else 0 */ + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** return NVIC_GetPendingIRQ(IRQn); + 1124 .loc 1 435 3 view .LVU286 + 1125 .LBB66: + 1126 .LBI66: +1951:Drivers/CMSIS/Include/core_cm7.h **** { + 1127 .loc 2 1951 26 view .LVU287 + 1128 .LBB67: +1953:Drivers/CMSIS/Include/core_cm7.h **** { + 1129 .loc 2 1953 3 view .LVU288 +1953:Drivers/CMSIS/Include/core_cm7.h **** { + 1130 .loc 2 1953 6 is_stmt 0 view .LVU289 + 1131 0000 0028 cmp r0, #0 +1953:Drivers/CMSIS/Include/core_cm7.h **** { + 1132 .loc 2 1953 6 view .LVU290 + 1133 0002 0BDB blt .L73 +1955:Drivers/CMSIS/Include/core_cm7.h **** } + 1134 .loc 2 1955 5 is_stmt 1 view .LVU291 + ARM GAS /tmp/ccB9Q52u.s page 90 + + +1955:Drivers/CMSIS/Include/core_cm7.h **** } + 1135 .loc 2 1955 54 is_stmt 0 view .LVU292 + 1136 0004 4309 lsrs r3, r0, #5 +1955:Drivers/CMSIS/Include/core_cm7.h **** } + 1137 .loc 2 1955 35 view .LVU293 + 1138 0006 4033 adds r3, r3, #64 + 1139 0008 054A ldr r2, .L74 + 1140 000a 52F82330 ldr r3, [r2, r3, lsl #2] +1955:Drivers/CMSIS/Include/core_cm7.h **** } + 1141 .loc 2 1955 91 view .LVU294 + 1142 000e 00F01F00 and r0, r0, #31 + 1143 .LVL65: +1955:Drivers/CMSIS/Include/core_cm7.h **** } + 1144 .loc 2 1955 103 view .LVU295 + 1145 0012 23FA00F0 lsr r0, r3, r0 +1955:Drivers/CMSIS/Include/core_cm7.h **** } + 1146 .loc 2 1955 12 view .LVU296 + 1147 0016 00F00100 and r0, r0, #1 + 1148 001a 7047 bx lr + 1149 .L73: +1959:Drivers/CMSIS/Include/core_cm7.h **** } + 1150 .loc 2 1959 11 view .LVU297 + 1151 001c 0020 movs r0, #0 + 1152 .LVL66: +1959:Drivers/CMSIS/Include/core_cm7.h **** } + 1153 .loc 2 1959 11 view .LVU298 + 1154 .LBE67: + 1155 .LBE66: + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 1156 .loc 1 436 1 view .LVU299 + 1157 001e 7047 bx lr + 1158 .L75: + 1159 .align 2 + 1160 .L74: + 1161 0020 00E100E0 .word -536813312 + 1162 .cfi_endproc + 1163 .LFE155: + 1165 .section .text.HAL_NVIC_ClearPendingIRQ,"ax",%progbits + 1166 .align 1 + 1167 .global HAL_NVIC_ClearPendingIRQ + 1168 .syntax unified + 1169 .thumb + 1170 .thumb_func + 1172 HAL_NVIC_ClearPendingIRQ: + 1173 .LVL67: + 1174 .LFB156: + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Clears the pending bit of an external interrupt. + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @param IRQn External interrupt number. + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval None + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 1175 .loc 1 446 1 is_stmt 1 view -0 + ARM GAS /tmp/ccB9Q52u.s page 91 + + + 1176 .cfi_startproc + 1177 @ args = 0, pretend = 0, frame = 0 + 1178 @ frame_needed = 0, uses_anonymous_args = 0 + 1179 @ link register save eliminated. + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Check the parameters */ + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 1180 .loc 1 448 3 view .LVU301 + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Clear pending interrupt */ + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** NVIC_ClearPendingIRQ(IRQn); + 1181 .loc 1 451 3 view .LVU302 + 1182 .LBB68: + 1183 .LBI68: +1985:Drivers/CMSIS/Include/core_cm7.h **** { + 1184 .loc 2 1985 22 view .LVU303 + 1185 .LBB69: +1987:Drivers/CMSIS/Include/core_cm7.h **** { + 1186 .loc 2 1987 3 view .LVU304 +1987:Drivers/CMSIS/Include/core_cm7.h **** { + 1187 .loc 2 1987 6 is_stmt 0 view .LVU305 + 1188 0000 0028 cmp r0, #0 +1987:Drivers/CMSIS/Include/core_cm7.h **** { + 1189 .loc 2 1987 6 view .LVU306 + 1190 0002 08DB blt .L76 +1989:Drivers/CMSIS/Include/core_cm7.h **** } + 1191 .loc 2 1989 5 is_stmt 1 view .LVU307 +1989:Drivers/CMSIS/Include/core_cm7.h **** } + 1192 .loc 2 1989 81 is_stmt 0 view .LVU308 + 1193 0004 00F01F02 and r2, r0, #31 +1989:Drivers/CMSIS/Include/core_cm7.h **** } + 1194 .loc 2 1989 34 view .LVU309 + 1195 0008 4009 lsrs r0, r0, #5 + 1196 .LVL68: +1989:Drivers/CMSIS/Include/core_cm7.h **** } + 1197 .loc 2 1989 45 view .LVU310 + 1198 000a 0123 movs r3, #1 + 1199 000c 9340 lsls r3, r3, r2 +1989:Drivers/CMSIS/Include/core_cm7.h **** } + 1200 .loc 2 1989 43 view .LVU311 + 1201 000e 6030 adds r0, r0, #96 + 1202 0010 014A ldr r2, .L78 + 1203 0012 42F82030 str r3, [r2, r0, lsl #2] + 1204 .LVL69: + 1205 .L76: +1989:Drivers/CMSIS/Include/core_cm7.h **** } + 1206 .loc 2 1989 43 view .LVU312 + 1207 .LBE69: + 1208 .LBE68: + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 1209 .loc 1 452 1 view .LVU313 + 1210 0016 7047 bx lr + 1211 .L79: + 1212 .align 2 + 1213 .L78: + 1214 0018 00E100E0 .word -536813312 + 1215 .cfi_endproc + 1216 .LFE156: + ARM GAS /tmp/ccB9Q52u.s page 92 + + + 1218 .section .text.HAL_NVIC_GetActive,"ax",%progbits + 1219 .align 1 + 1220 .global HAL_NVIC_GetActive + 1221 .syntax unified + 1222 .thumb + 1223 .thumb_func + 1225 HAL_NVIC_GetActive: + 1226 .LVL70: + 1227 .LFB157: + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @param IRQn External interrupt number + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval status: - 0 Interrupt status is not pending. + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * - 1 Interrupt status is pending. + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 1228 .loc 1 463 1 is_stmt 1 view -0 + 1229 .cfi_startproc + 1230 @ args = 0, pretend = 0, frame = 0 + 1231 @ frame_needed = 0, uses_anonymous_args = 0 + 1232 @ link register save eliminated. + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Check the parameters */ + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 1233 .loc 1 465 3 view .LVU315 + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Return 1 if active else 0 */ + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** return NVIC_GetActive(IRQn); + 1234 .loc 1 468 3 view .LVU316 + 1235 .LBB70: + 1236 .LBI70: +2002:Drivers/CMSIS/Include/core_cm7.h **** { + 1237 .loc 2 2002 26 view .LVU317 + 1238 .LBB71: +2004:Drivers/CMSIS/Include/core_cm7.h **** { + 1239 .loc 2 2004 3 view .LVU318 +2004:Drivers/CMSIS/Include/core_cm7.h **** { + 1240 .loc 2 2004 6 is_stmt 0 view .LVU319 + 1241 0000 0028 cmp r0, #0 +2004:Drivers/CMSIS/Include/core_cm7.h **** { + 1242 .loc 2 2004 6 view .LVU320 + 1243 0002 0BDB blt .L82 +2006:Drivers/CMSIS/Include/core_cm7.h **** } + 1244 .loc 2 2006 5 is_stmt 1 view .LVU321 +2006:Drivers/CMSIS/Include/core_cm7.h **** } + 1245 .loc 2 2006 54 is_stmt 0 view .LVU322 + 1246 0004 4309 lsrs r3, r0, #5 +2006:Drivers/CMSIS/Include/core_cm7.h **** } + 1247 .loc 2 2006 35 view .LVU323 + 1248 0006 8033 adds r3, r3, #128 + 1249 0008 054A ldr r2, .L83 + 1250 000a 52F82330 ldr r3, [r2, r3, lsl #2] +2006:Drivers/CMSIS/Include/core_cm7.h **** } + 1251 .loc 2 2006 91 view .LVU324 + ARM GAS /tmp/ccB9Q52u.s page 93 + + + 1252 000e 00F01F00 and r0, r0, #31 + 1253 .LVL71: +2006:Drivers/CMSIS/Include/core_cm7.h **** } + 1254 .loc 2 2006 103 view .LVU325 + 1255 0012 23FA00F0 lsr r0, r3, r0 +2006:Drivers/CMSIS/Include/core_cm7.h **** } + 1256 .loc 2 2006 12 view .LVU326 + 1257 0016 00F00100 and r0, r0, #1 + 1258 001a 7047 bx lr + 1259 .L82: +2010:Drivers/CMSIS/Include/core_cm7.h **** } + 1260 .loc 2 2010 11 view .LVU327 + 1261 001c 0020 movs r0, #0 + 1262 .LVL72: +2010:Drivers/CMSIS/Include/core_cm7.h **** } + 1263 .loc 2 2010 11 view .LVU328 + 1264 .LBE71: + 1265 .LBE70: + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 1266 .loc 1 469 1 view .LVU329 + 1267 001e 7047 bx lr + 1268 .L84: + 1269 .align 2 + 1270 .L83: + 1271 0020 00E100E0 .word -536813312 + 1272 .cfi_endproc + 1273 .LFE157: + 1275 .section .text.HAL_SYSTICK_CLKSourceConfig,"ax",%progbits + 1276 .align 1 + 1277 .global HAL_SYSTICK_CLKSourceConfig + 1278 .syntax unified + 1279 .thumb + 1280 .thumb_func + 1282 HAL_SYSTICK_CLKSourceConfig: + 1283 .LVL73: + 1284 .LFB158: + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief Configures the SysTick clock source. + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @param CLKSource specifies the SysTick clock source. + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * This parameter can be one of the following values: + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval None + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 1285 .loc 1 480 1 is_stmt 1 view -0 + 1286 .cfi_startproc + 1287 @ args = 0, pretend = 0, frame = 0 + 1288 @ frame_needed = 0, uses_anonymous_args = 0 + 1289 @ link register save eliminated. + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* Check the parameters */ + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + 1290 .loc 1 482 3 view .LVU331 + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + 1291 .loc 1 483 3 view .LVU332 + ARM GAS /tmp/ccB9Q52u.s page 94 + + + 1292 .loc 1 483 6 is_stmt 0 view .LVU333 + 1293 0000 0428 cmp r0, #4 + 1294 0002 06D0 beq .L88 + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** else + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + 1295 .loc 1 489 5 is_stmt 1 view .LVU334 + 1296 .loc 1 489 12 is_stmt 0 view .LVU335 + 1297 0004 4FF0E022 mov r2, #-536813568 + 1298 0008 1369 ldr r3, [r2, #16] + 1299 .loc 1 489 19 view .LVU336 + 1300 000a 23F00403 bic r3, r3, #4 + 1301 000e 1361 str r3, [r2, #16] + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 1302 .loc 1 491 1 view .LVU337 + 1303 0010 7047 bx lr + 1304 .L88: + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 1305 .loc 1 485 5 is_stmt 1 view .LVU338 + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 1306 .loc 1 485 12 is_stmt 0 view .LVU339 + 1307 0012 4FF0E022 mov r2, #-536813568 + 1308 0016 1369 ldr r3, [r2, #16] + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 1309 .loc 1 485 19 view .LVU340 + 1310 0018 43F00403 orr r3, r3, #4 + 1311 001c 1361 str r3, [r2, #16] + 1312 001e 7047 bx lr + 1313 .cfi_endproc + 1314 .LFE158: + 1316 .section .text.HAL_SYSTICK_Callback,"ax",%progbits + 1317 .align 1 + 1318 .weak HAL_SYSTICK_Callback + 1319 .syntax unified + 1320 .thumb + 1321 .thumb_func + 1323 HAL_SYSTICK_Callback: + 1324 .LFB160: + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief This function handles SYSTICK interrupt request. + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval None + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** void HAL_SYSTICK_IRQHandler(void) + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** HAL_SYSTICK_Callback(); + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /** + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @brief SYSTICK callback. + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** * @retval None + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** __weak void HAL_SYSTICK_Callback(void) + ARM GAS /tmp/ccB9Q52u.s page 95 + + + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** { + 1325 .loc 1 507 1 is_stmt 1 view -0 + 1326 .cfi_startproc + 1327 @ args = 0, pretend = 0, frame = 0 + 1328 @ frame_needed = 0, uses_anonymous_args = 0 + 1329 @ link register save eliminated. + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** the HAL_SYSTICK_Callback could be implemented in the user file + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** */ + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 1330 .loc 1 511 1 view .LVU342 + 1331 0000 7047 bx lr + 1332 .cfi_endproc + 1333 .LFE160: + 1335 .section .text.HAL_SYSTICK_IRQHandler,"ax",%progbits + 1336 .align 1 + 1337 .global HAL_SYSTICK_IRQHandler + 1338 .syntax unified + 1339 .thumb + 1340 .thumb_func + 1342 HAL_SYSTICK_IRQHandler: + 1343 .LFB159: + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** HAL_SYSTICK_Callback(); + 1344 .loc 1 498 1 view -0 + 1345 .cfi_startproc + 1346 @ args = 0, pretend = 0, frame = 0 + 1347 @ frame_needed = 0, uses_anonymous_args = 0 + 1348 0000 08B5 push {r3, lr} + 1349 .LCFI6: + 1350 .cfi_def_cfa_offset 8 + 1351 .cfi_offset 3, -8 + 1352 .cfi_offset 14, -4 + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** } + 1353 .loc 1 499 3 view .LVU344 + 1354 0002 FFF7FEFF bl HAL_SYSTICK_Callback + 1355 .LVL74: + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c **** + 1356 .loc 1 500 1 is_stmt 0 view .LVU345 + 1357 0006 08BD pop {r3, pc} + 1358 .cfi_endproc + 1359 .LFE159: + 1361 .text + 1362 .Letext0: + 1363 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 1364 .file 5 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 1365 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h" + ARM GAS /tmp/ccB9Q52u.s page 96 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_cortex.c + /tmp/ccB9Q52u.s:20 .text.__NVIC_DisableIRQ:00000000 $t + /tmp/ccB9Q52u.s:25 .text.__NVIC_DisableIRQ:00000000 __NVIC_DisableIRQ + /tmp/ccB9Q52u.s:87 .text.__NVIC_DisableIRQ:00000020 $d + /tmp/ccB9Q52u.s:92 .text.__NVIC_SetPriority:00000000 $t + /tmp/ccB9Q52u.s:97 .text.__NVIC_SetPriority:00000000 __NVIC_SetPriority + /tmp/ccB9Q52u.s:139 .text.__NVIC_SetPriority:0000001c $d + /tmp/ccB9Q52u.s:145 .text.__NVIC_GetPriority:00000000 $t + /tmp/ccB9Q52u.s:150 .text.__NVIC_GetPriority:00000000 __NVIC_GetPriority + /tmp/ccB9Q52u.s:185 .text.__NVIC_GetPriority:00000018 $d + /tmp/ccB9Q52u.s:191 .text.NVIC_EncodePriority:00000000 $t + /tmp/ccB9Q52u.s:196 .text.NVIC_EncodePriority:00000000 NVIC_EncodePriority + /tmp/ccB9Q52u.s:258 .text.NVIC_DecodePriority:00000000 $t + /tmp/ccB9Q52u.s:263 .text.NVIC_DecodePriority:00000000 NVIC_DecodePriority + /tmp/ccB9Q52u.s:332 .text.__NVIC_SystemReset:00000000 $t + /tmp/ccB9Q52u.s:337 .text.__NVIC_SystemReset:00000000 __NVIC_SystemReset + /tmp/ccB9Q52u.s:398 .text.__NVIC_SystemReset:0000001c $d + /tmp/ccB9Q52u.s:404 .text.HAL_NVIC_SetPriorityGrouping:00000000 $t + /tmp/ccB9Q52u.s:410 .text.HAL_NVIC_SetPriorityGrouping:00000000 HAL_NVIC_SetPriorityGrouping + /tmp/ccB9Q52u.s:464 .text.HAL_NVIC_SetPriorityGrouping:0000001c $d + /tmp/ccB9Q52u.s:470 .text.HAL_NVIC_SetPriority:00000000 $t + /tmp/ccB9Q52u.s:476 .text.HAL_NVIC_SetPriority:00000000 HAL_NVIC_SetPriority + /tmp/ccB9Q52u.s:526 .text.HAL_NVIC_SetPriority:0000001c $d + /tmp/ccB9Q52u.s:531 .text.HAL_NVIC_EnableIRQ:00000000 $t + /tmp/ccB9Q52u.s:537 .text.HAL_NVIC_EnableIRQ:00000000 HAL_NVIC_EnableIRQ + /tmp/ccB9Q52u.s:578 .text.HAL_NVIC_EnableIRQ:00000018 $d + /tmp/ccB9Q52u.s:583 .text.HAL_NVIC_DisableIRQ:00000000 $t + /tmp/ccB9Q52u.s:589 .text.HAL_NVIC_DisableIRQ:00000000 HAL_NVIC_DisableIRQ + /tmp/ccB9Q52u.s:612 .text.HAL_NVIC_SystemReset:00000000 $t + /tmp/ccB9Q52u.s:618 .text.HAL_NVIC_SystemReset:00000000 HAL_NVIC_SystemReset + /tmp/ccB9Q52u.s:637 .text.HAL_SYSTICK_Config:00000000 $t + /tmp/ccB9Q52u.s:643 .text.HAL_SYSTICK_Config:00000000 HAL_SYSTICK_Config + /tmp/ccB9Q52u.s:708 .text.HAL_SYSTICK_Config:00000024 $d + /tmp/ccB9Q52u.s:713 .text.HAL_MPU_Disable:00000000 $t + /tmp/ccB9Q52u.s:719 .text.HAL_MPU_Disable:00000000 HAL_MPU_Disable + /tmp/ccB9Q52u.s:756 .text.HAL_MPU_Disable:00000018 $d + /tmp/ccB9Q52u.s:761 .text.HAL_MPU_Enable:00000000 $t + /tmp/ccB9Q52u.s:767 .text.HAL_MPU_Enable:00000000 HAL_MPU_Enable + /tmp/ccB9Q52u.s:821 .text.HAL_MPU_Enable:0000001c $d + /tmp/ccB9Q52u.s:826 .text.HAL_MPU_EnableRegion:00000000 $t + /tmp/ccB9Q52u.s:832 .text.HAL_MPU_EnableRegion:00000000 HAL_MPU_EnableRegion + /tmp/ccB9Q52u.s:854 .text.HAL_MPU_EnableRegion:00000014 $d + /tmp/ccB9Q52u.s:859 .text.HAL_MPU_DisableRegion:00000000 $t + /tmp/ccB9Q52u.s:865 .text.HAL_MPU_DisableRegion:00000000 HAL_MPU_DisableRegion + /tmp/ccB9Q52u.s:887 .text.HAL_MPU_DisableRegion:00000014 $d + /tmp/ccB9Q52u.s:892 .text.HAL_MPU_ConfigRegion:00000000 $t + /tmp/ccB9Q52u.s:898 .text.HAL_MPU_ConfigRegion:00000000 HAL_MPU_ConfigRegion + /tmp/ccB9Q52u.s:975 .text.HAL_MPU_ConfigRegion:00000054 $d + /tmp/ccB9Q52u.s:980 .text.HAL_NVIC_GetPriorityGrouping:00000000 $t + /tmp/ccB9Q52u.s:986 .text.HAL_NVIC_GetPriorityGrouping:00000000 HAL_NVIC_GetPriorityGrouping + /tmp/ccB9Q52u.s:1010 .text.HAL_NVIC_GetPriorityGrouping:0000000c $d + /tmp/ccB9Q52u.s:1015 .text.HAL_NVIC_GetPriority:00000000 $t + /tmp/ccB9Q52u.s:1021 .text.HAL_NVIC_GetPriority:00000000 HAL_NVIC_GetPriority + /tmp/ccB9Q52u.s:1056 .text.HAL_NVIC_SetPendingIRQ:00000000 $t + /tmp/ccB9Q52u.s:1062 .text.HAL_NVIC_SetPendingIRQ:00000000 HAL_NVIC_SetPendingIRQ + /tmp/ccB9Q52u.s:1104 .text.HAL_NVIC_SetPendingIRQ:00000018 $d + ARM GAS /tmp/ccB9Q52u.s page 97 + + + /tmp/ccB9Q52u.s:1109 .text.HAL_NVIC_GetPendingIRQ:00000000 $t + /tmp/ccB9Q52u.s:1115 .text.HAL_NVIC_GetPendingIRQ:00000000 HAL_NVIC_GetPendingIRQ + /tmp/ccB9Q52u.s:1161 .text.HAL_NVIC_GetPendingIRQ:00000020 $d + /tmp/ccB9Q52u.s:1166 .text.HAL_NVIC_ClearPendingIRQ:00000000 $t + /tmp/ccB9Q52u.s:1172 .text.HAL_NVIC_ClearPendingIRQ:00000000 HAL_NVIC_ClearPendingIRQ + /tmp/ccB9Q52u.s:1214 .text.HAL_NVIC_ClearPendingIRQ:00000018 $d + /tmp/ccB9Q52u.s:1219 .text.HAL_NVIC_GetActive:00000000 $t + /tmp/ccB9Q52u.s:1225 .text.HAL_NVIC_GetActive:00000000 HAL_NVIC_GetActive + /tmp/ccB9Q52u.s:1271 .text.HAL_NVIC_GetActive:00000020 $d + /tmp/ccB9Q52u.s:1276 .text.HAL_SYSTICK_CLKSourceConfig:00000000 $t + /tmp/ccB9Q52u.s:1282 .text.HAL_SYSTICK_CLKSourceConfig:00000000 HAL_SYSTICK_CLKSourceConfig + /tmp/ccB9Q52u.s:1317 .text.HAL_SYSTICK_Callback:00000000 $t + /tmp/ccB9Q52u.s:1323 .text.HAL_SYSTICK_Callback:00000000 HAL_SYSTICK_Callback + /tmp/ccB9Q52u.s:1336 .text.HAL_SYSTICK_IRQHandler:00000000 $t + /tmp/ccB9Q52u.s:1342 .text.HAL_SYSTICK_IRQHandler:00000000 HAL_SYSTICK_IRQHandler + +NO UNDEFINED SYMBOLS diff --git a/build/stm32f7xx_hal_cortex.o b/build/stm32f7xx_hal_cortex.o new file mode 100644 index 0000000000000000000000000000000000000000..2c598836e3f4a47d796a7a92b0180e348edc37dd GIT binary patch literal 28472 zcmd6Qd0cy4Tv4 zYOQ{iR$KI^wpg{bTB~ifiq>k?R_oqsD|HvOh0l#*TYt}U?t5qMT!Q_+|Gq0X&wZEk zp7*@xJ?GqQuIJV_HCUFV+|5#@Dn%*v$Oa?Pa}1QKd1|gwrP(j4{Zj+gSyssv)sb?0 zS?$3{`F-!NyzIXB`!4HWqW-G(s?y+#S=MiF4=$h34$l5jid4X%UQ>Gu-lLBFVsQER zQ&g6t5pa)P`JHNihPwYiM)o}if}=|BTe&}&ZBGu(9QDTsr>xxn>G3&-viBG5Q`Wbu za}L@6F5Z_DsM!}#rydM`qDubuX6~KV{tRnRTIuY`p;@E;XfKQ$vOW+C|D3ijJ6NzT z=aBX9$i5skeqHXps_1WTvNgK#(M^F5_O1^u&yPK}jvRI0zur{$Dfk{#hjgg%u}vi( z?CmTJ7G|q}`e5%mI~G_rG4|*>w1@43PVSw-2EF`+P4~Yah4Vos zYWG`#2Z4^w6u&r)AKO;2?16(j%bz-UZF$Ll%YFbD+w{P}Ys#&&9z3%!6x(MFo_}U+ z-=0{_S+RZR$Ii#!n%ExvwPH2kTO}6$*4WmzaExVLKLZjom+rqayJ1Yj6cf9uhGQCv z%u)Znsx;FRzv^MFgg^r{5v)>3S^|dU+N&6GX%oqYY5X@MR z39vHXMKN1j+D6d|2QJe}4FrFMzeB;3LrQH4-U#W|;Peco&I)$J^4Y=nMk;kq@S7-n zuD%|cN@sy@>9=qk(5%?ji!s)N`cCk*F2~=H9s_BH9tUZregzh?^e3=6LbE_vp97Dw z^^>qUQrBfGm7}XsYLq?}rE+x@N{!Yhk5DR4N5IL~g+ZkXbTRCV(IesKSlx-^ar#Ug zkJneg!UVk$)+Xvq=ojiQ!JkQb3@l96Jt#XxKZ(Cn^=7m#qGzJ^BE1x4i?t1}O7!2L zKTS`C{&f8XXwJ~PVC^WKfVZW37XBWsZ-eGB`XDrC>UwxMOE;me+4_EX64lu`N|ouA z&@9(~gPjU}HR`I=rO>a^C!*{e-G>_I>M&}brys)cd_5h17wFN@S*Y7#;aL4$NI$0! zq4wkSC5Xu){b%SLuYU>tVtp?(t93K%*XZrAU#qvmhnQXh{W{$W{d(O6PJ@07noIOq z;4IZ^;Z>vFgD5T2|A4p4^{vop((k}>vt940gJ8^u1{wI#t>Yu{qi8=z`PSU@F<&$*}IH%}4Aw5-R!t!Z)En*edV<26p z8_>oMJrg>edOm9J((TYm=wj$>(Eo(xjd}{CoAm9_@7Dhh{+zBC!=E#BHrlvZkApuw z$mY@1j&*eWd?;ruq&SeV z3$=tkMumFLgpFWju!)(cnz9-DP*qk?clQpd5y70mjaJsla4>u<+7S4Gm3Ib+K#2;! z!YX!KdHsftguCEv;3h|Imz-z8DKLKMDA*;}TH!yV*1*k4jX?OztnikkMj(708WFfP zsbPmNr^b(x8g}?(GJc%Y2!^xCxXsEt4{o5AV0L4R3jD;%yVlU>g~DU0aJ!XvqhajN z2tP)L@38XNTsS&OjpPxVl~c|bsSLJvBtt@@hB?lmzv0sJ)yR6tS&5PVU1d;a3jGWR zqiE^EfXe+Gf*JU!72E>t5w`>a4_jFr2;t)xz291S>%nIj7DVLrV{+NC}?b7Ap8>#<{OV0^!r`=~=dOEvF%N$>YKB8|>+~ z-CCXuh9h)+pR4gqFnk4z@kN*#Wc>Hm?-*r~(oXyap-ag7e2LdOoejB9mx4mJMaHva}49>r8RWOcg@2+YNn+ zBWD~8o#W6ya%rt{UuP>mvFr!YywSOVJ$6*DBHfh%>^?`iiuCegQaayl{fT&1O+V0P;Y43C{I zof)3X;rVTs&JN$tUigkn=Z0Tp{#@uM3$2BfJKKu^l-*xFp;U_5no=Zo*eLvs16rc0Lm%Gx!fQCoeZtmUTJ!`4d2eDkhr6szl|#jKZNRA+7v+ z_!^o!k@GWV%KY1q$f0>6&CDN(nnMeO%*ww2D}Lx$AxGrzq4YQ*!}&jEMaK)7o&O%m zY9UAFAI*wth0MwS2BmdEj#8n8wAB!J1uZDB6f)mBWQ{~Wz%A}yRMr@44Ti3DzzP{Q z%A3vl6B;=d6PWrg4%9en2@Ah0S`n~VSfkbBzYZ-(X0owXi<)3vN5=215f(YzreUZ0 zX;7cI9yLRH6c&SkG7^CcO^sN)XE_f)8iX(|g5-Nnp|F9Z942 zT1V69nGkHnUiiM(=vZ*92Q7P2AYZ8)L0pF&=cd*aq?vW=Fy3aPHpkmrt(i3ZB=jH0 zUN{>jxTUk%AUpZ5ef7aHujWe^uVEX`&;~myH-MSnD(|R;Dt&CwFv_YxFOaYHhW1@2YoQr)b&8$E!q-U9$ zVNIr)U!=$A#-x>Bl+a2ScCOmfe&`)UjG=YEJ?ZCQUIyvcu+y=d>HQ6k#Rxb*1K&Cg zPCJg>U`EhOU_OVvWIogE1~Y*2P%sC3$;XWJ4J#PwMW7dAKkEA!BG&h_$vYi%7xq#n zH&6xnhf}L{Oa5d==Q#|VW*lJfa7)wT`uEsv?Id3RT(p_m!dL7J1A^i>ZqyHPk$2d4Z;!_aQFa_|U z9v9PxP*or}VxpPDZT9HQZZsOKO4g!gU54BZbY>PiHx{RfH=Gd6AfOSGEwHTuiA?+O zp%FMe(^j+l5#B&$=2(m-TuWnL#d(PFnRp@$Kx9Jy1#mx)-Arg;E}<8^RK5xOcur_w zZWzVBY8}t14CEz-Y>PgN$Oqg2tMHZqNO6CEZa{dJ>B?+P8}4PfvJT$P{8DE&JlE7uZ8n zT)-UR9;ZH4@p)#^?G$p!bcDA{$zu*Oth-#(9Q%&Ku8f7obmgnaoxl#1Mm@=M2##>4 zRXZ{&srLpvdT+71$-xHlSO#cLG0zQ`XPDfYV-l^&A=KQfQOw?E7h3k*xoC;qV-DBw za6J#_v4glx!_E#f^XzCO>qzWo2Cl{d?+_x@MqAT!^22scVb1E%XsgxAWiCxq;qdWb z!er1oJ{%4=<{yj8=7nJkjS7}3J7*G_qRj!iH8d6+N1+i48FLjObB2K|F^1|!Bt?%NXu%>XPr4kuvLbtMwtWjaIVy83gdbJro$=Ic|wZI z`BD=|$8bSZEzUMRqx@0Xqpduvdc;+=7zksc)?tzmB=lnJS1z#BXsZH;vlG$z9rbY6uC z&y=sivA~GSYf;%$SAaQp6#9`}Q8XC^4>MPsbPI7gD%<@O=b-HA%dXJ@%n;u8LtNA^P=ec zq!A8fY?yqof6*X^H;&CHr_9|rIasQNzzJf6N}hY~a#c71bMvTjh8s@R=oy)@iu_YN z;T%rYwMrd0K;X1GoGRF6^EmK-+E;Jfd3uGo^K2|_L!YtP1gd;ivmMn{uBxTl(=35- zGRc5Z)-Xr4 zHBHsIW=N{y%mW)U#tCHkE+SS<(ETdwAJZzP?;_=xYQa(3W-bR+3&A^_y&30D5*}4H z(`}+x)iLclW2rXQ%sAtasp&+i)ltJqiX70ghPU%4?s6T;mN^jC!F3A|yo84lIu=bJ=Q!-p zCeXam26{Hesua7WP9d<+(P~cevN1A$qW8FZ`LyC}MEksB@O*P@zNy1$*(oR}8-1f4 zRP3^d!-SFjmbN+JXh{nP?g<^<<1FR4y~=gl8#`9-_?6~@Q&%OxQmq8)nR1fjsdCAb zamvsmrYpLTK)v*YNtN{UF@yUV;c0_7ZOa6O8VC{WZVvs28Hf&jmTDg4uuAw(s!%aw zL{gGt!y8u8&fr=_NLuqvCa*!p-gagQb6|9N#4_9>=C2bT9x_baT)B%8!*xz5c*xjr zV~22K?{j0)af_J0&H}|lP6FK4I-uMo+2y_U_ zzW+<@+KMY)+&!_-i`FMOBNc8V;utxkth#~jt%-rbvbOf-s>+7>+qT7*)-=T(Zduzv zr*aiy&25csWsSX^o40f&eB8Rk*6z*(Y^2O2HOsaP4wP-~USGDcv$L#Ypl5b(UvFY| zqGNq`Sw&T}GFnmA?Xx+oE2vnh!J(e2$_;dKQ^)3bXWzh3Vq3J6?Z9y&-q|xhx`~O} z*)!NZ7)ON;DaGcYAQ)JT28X)vG60T)N3gjGiwTlFpz(5)Nfdj>D7sGd@!ttO2(Hi7~B%w>Uq&zsx-cUIZ7xzS~M3@a(p zb3u+-rmZ5Uf=R3;60m%Ayqe2CFk!u9s}pJaU{+K|LixHhsz=Y(qiC+gXk6%O{0kbI z?J3aqlmK2Uu~NNyDG0k@3_4`2edkCXBN#bw#txO?{Uj5DGF=iXi0I>I>zt|JS5O`a z!ifFAfMueavUdaT&$IBDe5S!f`!-`#PlPEHu|xKg16C*+r8^OAEsB_YNR|JE$DiF! z(P1<0I8*<#s6Uw2o=2tr;xXC^m6-shj6YA~#ir*{%-6sS<{MwXmj}7i{7?kG*62Lb zm_-QAOJ^CG9t{uo#5#w4x0q2!V0`V`Y0BwB$VNJ9rUWZrY^*)*TD#*cXWZQ{48*~{?<{BBrCNQH zu{TCWz+xzE^m+R8|ETep(a3kVF?uW;Z(Qouang2xm($7DwSaoRc_lznDIXkTv}vaPYcL3V(4 zijt$RwXME&O?_R3YHg3jPguUXCEnP&s#n#oZEvh}4(l4)>Y6L!4NdJ;!f39kh_?+5 zBszNLIh^*!<^^#S1y+bsV`Xekync-%U$SC#Bvvs$;;g5U%JRypit_S>k=Z?+{aY3} z%jE2y`Jjh3ZRuGL+yMTD{;hLocU8UB-)0q$*EQFw##l=$4vm4> z=0wLpOQIJi2OH5%Dps?iGTyqj+^KeTTTN@b^a#(9Xsf=rWBuj?j5O9XHLYeVq$1O0 zwXMrdp9ybSOZ^hZR83Bi`P+BpzGYY^s#lip?dd$f&mMgYDg&XL#D=rc|sA{m^}8LJf9r>`in< zI*|-&3tU^k4s2_yZ!(U!$tkUBt#?wqTy5#~7WBA0$EnQKoTJ>Mxyhq>$)ownqXlkA zJRQprOCL1W)V89F5J<$av948NOjN|{Tb;^G-?hc+)2psb8n0qjNGw+mc5F;EbZpr? z-Zj zyBY^$9i5wST8wl;X13L`rQ%<0$6%tSt7{-JIH;D=ay;G$g_@RrW`2}STk8AXRP}6rJi6(^i1=;9f>@aMu6+g?vg7^lo}?=npnr?&5n;w zimq0iT^;3kV{i8md$BIDK{bGFYG6yH|9$S(b`N2g$OP@FsSY(sw|LVY8CZp3C@xCo zq*m&h&Q1)wmc&3$_uwEFCf7tNT&=Y=t??SH@CGr%7_2gDym*Lrd7Bu;dGWd$cMLcy z2XnX1X_3>#GPII&DOU!JGvBbqe4a`xx2;&%Hgs=vf~IO4YSLzFH;)Euw`|yu7%=mU zXW+;hAmOUtmgsa=KX+)ltA?58+^jbfV0%x$YHW`+Vg(<9j3YM(69XGMIur4Mj;@Y@vL%UL zglVX6Al?$I^(liBAMD#Ogp;8Jr{NYf-qe~_A^WB6#J2Xv*m9n9pl?)7EvIi}g2da* z)6zA}Xc=a$D`ZA8$(funK=FJ;^lRMJr7>2I*dvQ@g5stp=kW9lG2!$~?a9@PBh7@_ z%_B(yNhFu+oR`Ljz7!^IK zBPrlXS~(GDT3J)4>Jsa>Y-~nXvd7E};iQO+Cr(v{%jTF+NGriq&CMJvgPU+a$()I` zx(ijmoK7k(gJz5y#27bNrQ|f#y+=0eoh#f#D?7rCE7QI15KGPZ5&)c4V%V?t#z4}> zn^|bU(vIG)%{W_LwYsJbW5w4{|5+`vufn~Wkeb|fZscjRbKc^fN6D;S-%=4@xw_pk z?U~)pWZS%^p|xD`Z-x0=Y0etWdB4|FPV(zJI?v#V8ZKT^Cu%$mlB}t7W)k0&ZZah~ zl-yNJGK(p*FfOZ})3u4Twb`>4`!5fiK2IC9vK~le5Ud4pHyv=MC8sm77M^!Dw&B#A z)l0W<#I;GndE(Z%!U>xvmt~wMlaXhYso}~M1je0F-NFU3rLM67K}yYtH;~wH946V(!Q4;^606MZ?h}w zC>-kf^|PB*Xk5Ap*}w>PXA8Oq25sDtPcN@kIV7p_+LUJuosDjjkRfb1Keum=97c9@Q5CHAn@T(l3ex^Dd3MqZ} z0g+P*FF^S8v(!1F@5Cp|*FL;U=-F&M*Gu_M!3du|-)%^3Hr_T#*AM&j`I1R$v+;Y7 zbp4UOc;Vea&t~I=k92)LYfNo69^9qN-3NJ&j*a(}(&c%kKE}e?`1mum*(%?spYQVz zFNt|J8zU#(eu1z3-jT(}XJdT&V~l=EYmCP_^~d`3$NKd7GE8d28~#51aYnyAsluON zr#2hf>Hd#5`lq%g8q-S@8ha@oM{8=c@qjiZBY%?7k0e!6Batjy zP4?+e_Sv7DEa~V^@##XS!&@`z7fkI%@Xy3O5BYh$&`y1Y>K8&g?VF_jkS3q3_NB?EsDB9^G4`jb30RWAGAmQDim0g2 zPWy|F@a(r!O-tU4^;{%O>+)V(xfce9pIa((3hKK(^ckn6-g^b4D8$=3TWDbi%_Rg0JDx#&WEan2oq<%Mg(2rQdC6B>cj0fU%knQtTT z_8eEN5t#N3zsGsyCD7`W51fG4-61D(B_VQ#4&WV7&NKm>Y;eXPze8z#7n~qCRdBlCOhL|D)SoZ7NH8YYD7aE^wcyEu z9fBJLdjtmsw+o&t_$9%w30^LEmEd;;IsehGn*@I>c&Fem1@{Q@Cz{m%o#4}ge-wOK z@O8m=1P=&)EXaA2c5EajF-vfi;26O|!6Lz<1o?wTma7t6D7aX#UU0eKD!~&3PZjJG z>=x`3+#-0E;Q4}I7W}&46@uRuR9~3lSRzSHYgnm}=MZv!c zzA5;g;QNCA5d2gSzg#nZj1(*sj0i>r`O`-Fd#qryV5{Kig69ifE_j{b?Sc;qJ|k#; zx(~Y_37rvi>KQM{UnH{LWrBAJJ|XzB;NJy56)e+Exy6Dj1>=H!g69feCb&!R$Ab3> zJ|XzB;NJy56&!^V75Z5wSS`r6ZOLCRI4F3L;C~5zU+^x$M+E;UxKHpC!EDaqusc~W zD!5pXAK9V2LvTRwLcuEqZxsBQ;KPD12)-?NNRU6`r`_KOJ}3B*UsrOvEDh2ccgg!ajfF9axT^P6~b`{0y$ekQWe_;yhDu zy6`KAus2umc#+2hmk73te68R*BJA?BT7i0e#z^o?;a^OI-LDE>A@ZGq*9hJu@>>P@ z*)7_AfLM$E7kpay{A>j6zAE^x$PWm9C>X#A3H3sPIYihUM_i2Gp$V1>e-07)3j}LK z-XOS4@C1>cEZ9ke-Oa>BO7#m4iToUqe^uy91^JmTmgBDqSnu_MyM@n>QIUVQ;Jw2C ztdS&Ov_)UM2k9 zf4orT1i z_;tD93c)tP69m^2q2Eg^Rcb)+T;YF}2!AdWyh`NP2wp3Ai^y*i{JHRdCHR2g6C!_F z@Fl^$f^QSy&jI2Ld>BCRA0oGL&P;v|5qe{Z)9@P*!6`)eTPpG@q2~)8M}+=rk)KK| z!h9{*EBx(5*!iO1#UlTj;AMhWi+q>h4~X#V$3)zYxI^$Rk?#@t<3c|v_^j~v3jLbk z+rs}q=!1g)5`HEwoatw_;20w6ohUd(aE9Ot!F5FVxrvC|IGY8x3;!Y_>|P>xxyZjI z_#MITi~NUzcL?4kc)#GU1s@}#-oFUGEBFy{9KMDr7{-MU>0H4A!6LyKg2xEXA;Rt= zA}+dW1nY@t$4Zf(EOcD3OZfdl4+(A;{w0D}30^Pq9|+ze{JVv|M{tkue<$=G1fLiF zYeejC3BF5&pC1v?jsPwUNrwc(MDWK6T__k4{w$%(1?LLCM(BFMWx`)0^htto;h!ON zpWqhZUqHm1bg|$S!rw)NpVtfCB>cMt9};|8@D0Ha1nqpMU84mff>FU5!Igq*i8%K= zMX+1=TZnB+Z5O0eob(v;CBVD6TF#-`2Irh5y9sL-w=FXkQesU&k>v;I8CsM zh;yX*f_20;e6UfFzpWv?S`e49=DY@{(FU=68N_ffh$+jQuV9KcSSDB{xKa=%jr=6R z(*(~X;=JS>!7mAZMes(!n*?tY{HfrRM4W#-Blx1=%Yx=Q9P&?v<~K&DKSFQ@5$74l z2%76{&~t@eC1|dz!RLKK>aP>zSBkiQj3jRRwW>{LGuYj(EOeb*Voeo6N2Wt zmg}z2TLt-b9qR8CG}o=5uNV3jL4FvFdi>N5@%Msz1z!{72X?q_n(I&?J_clHEy!={ za9x}rSR^=I(0ry0@Lv6XYj!xNiMI@BzW! z2=Z$>lLAiugpd5z#w!6rd|frs*5!L5R43SJ_( zLy%w1;W~P~;130VB*<^(Q2u+tX9fQ#$j|6d{)r&xF47^vk%FTI`K2AoO9iV0=L@bP zVs2S2c&cEBAU}sg`B{P&2wp7sEy3>y@=H0?|B2w;g7*mWvpAH$BKWr8dx9Sc9umwB zIr`=+Bq%pdXnypScKAgd;yl4cf;EEufrM^L&k9n1d>%nV@n8$Y$ zvEJN9ti^REu^#zBT#C<_5tlok@ZPfw`p7J~YYTcp}=# z=UK!E5kfS@U?~ypo+VgLMEl{o!39Lb;W)u+BH~de2v<#9ngm;jh)=uVS|TbrMQ|Mv z@#+%XL`2*+3-%KczahbGL^yM{;CV#E^CH1Zh=}VB!EX=|-zx=o5)tQX1g|9`-Zu#D zCL->)2;N3qs?<*f?WQ6l2RFHJB$ z4-pZU14P6lF9bv!T8U`CnXl@RSESKi^XXu;lOOY9`!*2KF1V@!=*00v*n&%jhAXCh zsM632h-hb>&@gG*Yx*7K*O7*?A(3w*qWu>MeF+h9xKikyM8w1N3(A{*L0n8ffWDt{ zIP;9?zd)RU?>-8>p9m-aDYRlgAa2=2l+Pt1ev^cb5D~{&LYEWgAn%2)CL*p)LbnhR z-&2HMM?{>>c_ZwfO&akw=Zm0skY?OP{~99Vzgy^AhzQ!@`e<3#k!3qrp{ zpY=O zdE$Leoz9h~)x$C6>2$g%{mFH@EbaMqN@RlU>6OolmPgGWt@Nkb!y7=yOyt{WpA2Qw?cdTDOkl3m`(#?IHUb17L zqjzHh!-8qxlsTNUxw|*vTEw_g(ayde{tU-kYQsQB50q+Jo1+~=Lj&FGw+zAT|9r!= z$LYzOv#=DVowN;0h1rVmmwH$l%;wjljN4JzGqL|Cy;;!l*US0c-GXvZ2lVP;Iy38l zU++|(-r1ldt`g9-w-v`;d)I(I-lONXmutCK?@ve2`=L*7JPHlhjt6~u#~nd$pHFWc z^djK7o7;{zz`zo(szoqoiF5wNdn94()MG#3H{WUPI1ltB@ZHU|$M;|HFPR5iBUs+u z+_+2u-&=1T>ZKm*&B5;0TkW%V186Mw$<4LLIC$+fdFPMk-(~RDTMfO4r(TH7_OMTH9rRoo72M-De0uAlH(cJo0zGg1 zx;%MW1bc4$GEkoWxf|bEIJv;3QZgHSuf5H%$LAd!M1+@z^`jXYbkRO7T8|ySesO`|RDb&bh9o zJ+48ne+jWyE(TW4#&rlMG}&m6d%sWb&d)h(o?q{aKL1{V-n*_-P-eZ{w)_0s(UEE| zeR2K!D)jKL-xR{1M{vGh=@LNKG||m%ivJ0{{peq=*C%7AJInstance)); + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_CHANNEL(hdma->Init.Channel)); + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_MODE(hdma->Init.Mode)); + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Check the memory burst, peripheral burst and FIFO threshold parameters only + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** when FIFO mode is enabled */ + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + ARM GAS /tmp/ccjAMZS2.s page 5 + + + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Change DMA peripheral state */ + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_BUSY; + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Allocate lock resource */ + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Disable the peripheral */ + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Check if the DMA Stream is effectively disabled */ + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Check for the Timeout */ + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Update error code */ + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Change the DMA state */ + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_TIMEOUT; + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_TIMEOUT; + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Get the CR register value */ + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** tmp = hdma->Instance->CR; + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Prepare the DMA Stream configuration */ + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** tmp |= hdma->Init.Channel | hdma->Init.Direction | + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Init.Mode | hdma->Init.Priority; + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Get memory burst and peripheral burst */ + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Write to DMA Stream CR register */ + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->CR = tmp; + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Get the FCR register value */ + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** tmp = hdma->Instance->FCR; + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clear Direct mode and FIFO threshold bits */ + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + ARM GAS /tmp/ccjAMZS2.s page 6 + + + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Prepare the DMA Stream FIFO configuration */ + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** tmp |= hdma->Init.FIFOMode; + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* The FIFO threshold is not used when the FIFO mode is disabled */ + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Get the FIFO threshold */ + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** tmp |= hdma->Init.FIFOThreshold; + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Check compatibility between FIFO threshold level and size of the memory burst */ + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* for INCR4, INCR8, INCR16 bursts */ + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if (DMA_CheckFifoParam(hdma) != HAL_OK) + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Update error code */ + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Change the DMA state */ + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_RESET; + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_ERROR; + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Write to DMA Stream FCR */ + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->FCR = tmp; + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clear all interrupt flags */ + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** regs->IFCR = 0x3FU << hdma->StreamIndex; + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Initialize the error code */ + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Initialize the DMA state */ + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_OK; + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @brief DeInitializes the DMA peripheral + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @retval HAL status + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** DMA_Base_Registers *regs; + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Check the DMA peripheral state */ + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma == NULL) + ARM GAS /tmp/ccjAMZS2.s page 7 + + + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_ERROR; + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Check the DMA peripheral state */ + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma->State == HAL_DMA_STATE_BUSY) + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Return error status */ + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_BUSY; + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Check the parameters */ + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Disable the selected DMA Streamx */ + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Reset DMA Streamx control register */ + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->CR = 0U; + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Reset DMA Streamx number of data to transfer register */ + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->NDTR = 0U; + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Reset DMA Streamx peripheral address register */ + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->PAR = 0U; + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Reset DMA Streamx memory 0 address register */ + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->M0AR = 0U; + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Reset DMA Streamx memory 1 address register */ + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->M1AR = 0U; + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Reset DMA Streamx FIFO control register */ + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->FCR = (uint32_t)0x00000021U; + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Get DMA steam Base Address */ + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clear all interrupt flags at correct offset within the register */ + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** regs->IFCR = 0x3FU << hdma->StreamIndex; + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clean all callbacks */ + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferCpltCallback = NULL; + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferM1CpltCallback = NULL; + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferM1HalfCpltCallback = NULL; + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Reset the error code */ + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Reset the DMA state */ + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_RESET; + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Release Lock */ + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + ARM GAS /tmp/ccjAMZS2.s page 8 + + + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_OK; + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @} + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** @addtogroup DMA_Exported_Functions_Group2 + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** @verbatim + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** =============================================================================== + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** ##### IO operation functions ##### + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** =============================================================================== + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** [..] This section provides functions allowing to: + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** (+) Configure the source, destination address and data length and Start DMA transfer + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** (+) Configure the source, destination address and data length and + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** Start DMA transfer with interrupt + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** (+) Abort DMA transfer + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** (+) Poll for transfer complete + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** (+) Handle DMA interrupt request + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** @endverbatim + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @{ + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @brief Starts the DMA Transfer. + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param SrcAddress The source memory Buffer address + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param DstAddress The destination memory Buffer address + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param DataLength The length of data to be transferred from source to destination + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @retval HAL status + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Check the parameters */ + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Process locked */ + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_LOCK(hdma); + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(HAL_DMA_STATE_READY == hdma->State) + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Change DMA peripheral state */ + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_BUSY; + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Initialize the error code */ + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Configure the source, destination address and the data length */ + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Enable the Peripheral */ + ARM GAS /tmp/ccjAMZS2.s page 9 + + + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_DMA_ENABLE(hdma); + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** else + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Process unlocked */ + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Return error status */ + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** status = HAL_BUSY; + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return status; + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @brief Start the DMA Transfer with interrupt enabled. + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param SrcAddress The source memory Buffer address + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param DstAddress The destination memory Buffer address + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param DataLength The length of data to be transferred from source to destination + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @retval HAL status + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddres + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* calculate DMA base and stream number */ + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Check the parameters */ + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Process locked */ + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_LOCK(hdma); + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(HAL_DMA_STATE_READY == hdma->State) + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Change DMA peripheral state */ + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_BUSY; + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Initialize the error code */ + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Configure the source, destination address and the data length */ + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clear all interrupt flags at correct offset within the register */ + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** regs->IFCR = 0x3FU << hdma->StreamIndex; + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Enable Common interrupts*/ + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->FCR |= DMA_IT_FE; + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma->XferHalfCpltCallback != NULL) + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->CR |= DMA_IT_HT; + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + ARM GAS /tmp/ccjAMZS2.s page 10 + + + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Enable the Peripheral */ + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_DMA_ENABLE(hdma); + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** else + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Process unlocked */ + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Return error status */ + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** status = HAL_BUSY; + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return status; + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @brief Aborts the DMA Transfer. + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @note After disabling a DMA Stream, a check for wait until the DMA Stream is + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * effectively disabled is added. If a Stream is disabled + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * while a data transfer is ongoing, the current data will be transferred + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * and the Stream will be effectively disabled only after the transfer of + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * this single data is finished. + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @retval HAL status + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* calculate DMA base and stream number */ + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tickstart = HAL_GetTick(); + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma->State != HAL_DMA_STATE_BUSY) + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Process Unlocked */ + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_ERROR; + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** else + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Disable all the transfer interrupts */ + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->FCR &= ~(DMA_IT_FE); + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->CR &= ~(DMA_IT_HT); + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Disable the stream */ + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + ARM GAS /tmp/ccjAMZS2.s page 11 + + + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Check if the DMA Stream is effectively disabled */ + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Check for the Timeout */ + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Update error code */ + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Change the DMA state */ + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_TIMEOUT; + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Process Unlocked */ + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_TIMEOUT; + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clear all interrupt flags at correct offset within the register */ + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** regs->IFCR = 0x3FU << hdma->StreamIndex; + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Change the DMA state*/ + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Process Unlocked */ + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_OK; + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @brief Aborts the DMA Transfer in Interrupt mode. + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @retval HAL status + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma->State != HAL_DMA_STATE_BUSY) + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_ERROR; + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** else + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Set Abort State */ + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_ABORT; + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Disable the stream */ + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_OK; + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + ARM GAS /tmp/ccjAMZS2.s page 12 + + + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @brief Polling for transfer complete. + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param CompleteLevel Specifies the DMA level complete. + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @note The polling mode is kept in this version for legacy. it is recommended to use the IT mo + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * This model could be used for debug purpose. + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (a + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param Timeout Timeout duration. + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @retval HAL status + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef Com + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t mask_cpltlevel; + 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tickstart = HAL_GetTick(); + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tmpisr; + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* calculate DMA base and stream number */ + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** DMA_Base_Registers *regs; + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(HAL_DMA_STATE_BUSY != hdma->State) + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* No transfer ongoing */ + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_ERROR; + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Polling mode not supported in circular mode and double buffering mode */ + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET) + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_ERROR; + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Get the level transfer complete flag */ + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Transfer Complete flag */ + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** else + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Half Transfer Complete flag */ + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** tmpisr = regs->ISR; + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET)) + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Check for the Timeout (Not applicable in circular mode)*/ + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(Timeout != HAL_MAX_DELAY) + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + ARM GAS /tmp/ccjAMZS2.s page 13 + + + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Update error code */ + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Change the DMA state */ + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Process Unlocked */ + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_TIMEOUT; + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Get the ISR register value */ + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** tmpisr = regs->ISR; + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Update error code */ + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->ErrorCode |= HAL_DMA_ERROR_TE; + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clear the transfer error flag */ + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Update error code */ + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->ErrorCode |= HAL_DMA_ERROR_FE; + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clear the FIFO error flag */ + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Update error code */ + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->ErrorCode |= HAL_DMA_ERROR_DME; + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clear the Direct Mode error flag */ + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_DMA_Abort(hdma); + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clear the half transfer and transfer complete flags */ + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Change the DMA state */ + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->State= HAL_DMA_STATE_READY; + ARM GAS /tmp/ccjAMZS2.s page 14 + + + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Process Unlocked */ + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_ERROR; + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Get the level transfer complete flag */ + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clear the half transfer and transfer complete flags */ + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Process Unlocked */ + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** else + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clear the half transfer flag */ + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex; + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return status; + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @brief Handles DMA interrupt request. + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @retval None + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tmpisr; + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __IO uint32_t count = 0; + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t timeout = SystemCoreClock / 9600; + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* calculate DMA base and stream number */ + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** tmpisr = regs->ISR; + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Transfer Error Interrupt management ***************************************/ + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Disable the transfer error interrupt */ + 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->CR &= ~(DMA_IT_TE); + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clear the transfer error flag */ + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + ARM GAS /tmp/ccjAMZS2.s page 15 + + + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Update error code */ + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->ErrorCode |= HAL_DMA_ERROR_TE; + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* FIFO Error Interrupt management ******************************************/ + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) + 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) + 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clear the FIFO error flag */ + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; + 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Update error code */ + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->ErrorCode |= HAL_DMA_ERROR_FE; + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Direct Mode Error Interrupt management ***********************************/ + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) + 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) + 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clear the direct mode error flag */ + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Update error code */ + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->ErrorCode |= HAL_DMA_ERROR_DME; + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Half Transfer Complete Interrupt management ******************************/ + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) + 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clear the half transfer complete flag */ + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Multi_Buffering mode enabled */ + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Current memory buffer used is Memory 0 */ + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma->XferHalfCpltCallback != NULL) + 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Half transfer callback */ + 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferHalfCpltCallback(hdma); + 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Current memory buffer used is Memory 1 */ + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** else + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma->XferM1HalfCpltCallback != NULL) + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Half transfer callback */ + 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferM1HalfCpltCallback(hdma); + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + ARM GAS /tmp/ccjAMZS2.s page 16 + + + 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** else + 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Disable the half transfer interrupt */ + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->CR &= ~(DMA_IT_HT); + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma->XferHalfCpltCallback != NULL) + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Half transfer callback */ + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferHalfCpltCallback(hdma); + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Transfer Complete Interrupt management ***********************************/ + 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clear the transfer complete flag */ + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(HAL_DMA_STATE_ABORT == hdma->State) + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Disable all the transfer interrupts */ + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->FCR &= ~(DMA_IT_FE); + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->CR &= ~(DMA_IT_HT); + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clear all interrupt flags at correct offset within the register */ + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** regs->IFCR = 0x3FU << hdma->StreamIndex; + 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Change the DMA state */ + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Process Unlocked */ + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma->XferAbortCallback != NULL) + 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferAbortCallback(hdma); + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return; + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) + 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Current memory buffer used is Memory 0 */ + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) + ARM GAS /tmp/ccjAMZS2.s page 17 + + + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma->XferM1CpltCallback != NULL) + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Transfer complete Callback for memory1 */ + 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferM1CpltCallback(hdma); + 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Current memory buffer used is Memory 1 */ + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** else + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma->XferCpltCallback != NULL) + 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Transfer complete Callback for memory0 */ + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferCpltCallback(hdma); + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** else + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) + 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Disable the transfer complete interrupt */ + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->CR &= ~(DMA_IT_TC); + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Change the DMA state */ + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Process Unlocked */ + 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma->XferCpltCallback != NULL) + 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Transfer complete callback */ + 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferCpltCallback(hdma); + 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* manage error case */ + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_ABORT; + 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Disable the stream */ + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** do + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if (++count > timeout) + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + ARM GAS /tmp/ccjAMZS2.s page 18 + + + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); + 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Change the DMA state */ + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Process Unlocked */ + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma->XferErrorCallback != NULL) + 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Transfer error callback */ + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferErrorCallback(hdma); + 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** + 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @brief Register callbacks + 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param CallbackID User Callback identifier + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * a DMA_HandleTypeDef structure as parameter. + 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param pCallback pointer to private callbacsk function which has pointer to + 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * a DMA_HandleTypeDef structure as parameter. + 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @retval HAL status + 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ + 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Callb + 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Process locked */ + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_LOCK(hdma); + 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(HAL_DMA_STATE_READY == hdma->State) + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** switch (CallbackID) + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case HAL_DMA_XFER_CPLT_CB_ID: + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferCpltCallback = pCallback; + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case HAL_DMA_XFER_HALFCPLT_CB_ID: + 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferHalfCpltCallback = pCallback; + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case HAL_DMA_XFER_M1CPLT_CB_ID: + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferM1CpltCallback = pCallback; + 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferM1HalfCpltCallback = pCallback; +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + ARM GAS /tmp/ccjAMZS2.s page 19 + + +1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case HAL_DMA_XFER_ERROR_CB_ID: +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferErrorCallback = pCallback; +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case HAL_DMA_XFER_ABORT_CB_ID: +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferAbortCallback = pCallback; +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** default: +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Return error status */ +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** status = HAL_ERROR; +1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** else +1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Return error status */ +1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** status = HAL_ERROR; +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Release Lock */ +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_UNLOCK(hdma); +1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return status; +1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** +1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @brief UnRegister callbacks +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param CallbackID User Callback identifier +1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. +1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @retval HAL status +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ +1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Cal +1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; +1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Process locked */ +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_LOCK(hdma); +1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(HAL_DMA_STATE_READY == hdma->State) +1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** switch (CallbackID) +1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case HAL_DMA_XFER_CPLT_CB_ID: +1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferCpltCallback = NULL; +1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case HAL_DMA_XFER_HALFCPLT_CB_ID: +1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case HAL_DMA_XFER_M1CPLT_CB_ID: +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferM1CpltCallback = NULL; +1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + ARM GAS /tmp/ccjAMZS2.s page 20 + + +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case HAL_DMA_XFER_M1HALFCPLT_CB_ID: +1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferM1HalfCpltCallback = NULL; +1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case HAL_DMA_XFER_ERROR_CB_ID: +1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferErrorCallback = NULL; +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case HAL_DMA_XFER_ABORT_CB_ID: +1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferAbortCallback = NULL; +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case HAL_DMA_XFER_ALL_CB_ID: +1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferCpltCallback = NULL; +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; +1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferM1CpltCallback = NULL; +1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferM1HalfCpltCallback = NULL; +1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferErrorCallback = NULL; +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferAbortCallback = NULL; +1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** default: +1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** status = HAL_ERROR; +1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** else +1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** status = HAL_ERROR; +1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Release Lock */ +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_UNLOCK(hdma); +1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return status; +1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** +1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @} +1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ +1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** @addtogroup DMA_Exported_Functions_Group3 +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * +1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** @verbatim +1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** =============================================================================== +1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** ##### State and Errors functions ##### +1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** =============================================================================== +1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** [..] +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** This subsection provides functions allowing to +1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** (+) Check the DMA state +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** (+) Get error code +1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** @endverbatim +1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @{ +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ +1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + ARM GAS /tmp/ccjAMZS2.s page 21 + + +1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @brief Returns the DMA state. +1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @retval HAL state +1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ +1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return hdma->State; +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @brief Return the DMA error code +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. +1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @retval DMA Error Code +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ +1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return hdma->ErrorCode; +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** +1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @} +1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ +1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** +1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @} +1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ +1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** @addtogroup DMA_Private_Functions +1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @{ +1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ +1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @brief Sets the DMA Transfer parameter. +1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. +1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param SrcAddress The source memory Buffer address +1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param DstAddress The destination memory Buffer address +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param DataLength The length of data to be transferred from source to destination +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @retval HAL status +1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32 +1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 28 .loc 1 1159 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .loc 1 1159 1 is_stmt 0 view .LVU1 + 34 0000 30B4 push {r4, r5} + 35 .LCFI0: + 36 .cfi_def_cfa_offset 8 + 37 .cfi_offset 4, -8 + 38 .cfi_offset 5, -4 +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Clear DBM bit */ + ARM GAS /tmp/ccjAMZS2.s page 22 + + +1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); + 39 .loc 1 1161 3 is_stmt 1 view .LVU2 + 40 .loc 1 1161 7 is_stmt 0 view .LVU3 + 41 0002 0568 ldr r5, [r0] + 42 .loc 1 1161 17 view .LVU4 + 43 0004 2C68 ldr r4, [r5] + 44 .loc 1 1161 22 view .LVU5 + 45 0006 24F48024 bic r4, r4, #262144 + 46 000a 2C60 str r4, [r5] +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Configure DMA Stream data length */ +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->NDTR = DataLength; + 47 .loc 1 1164 3 is_stmt 1 view .LVU6 + 48 .loc 1 1164 7 is_stmt 0 view .LVU7 + 49 000c 0468 ldr r4, [r0] + 50 .loc 1 1164 24 view .LVU8 + 51 000e 6360 str r3, [r4, #4] +1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Memory to Peripheral */ +1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + 52 .loc 1 1167 3 is_stmt 1 view .LVU9 + 53 .loc 1 1167 17 is_stmt 0 view .LVU10 + 54 0010 8368 ldr r3, [r0, #8] + 55 .LVL1: + 56 .loc 1 1167 5 view .LVU11 + 57 0012 402B cmp r3, #64 + 58 0014 05D0 beq .L5 +1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Configure DMA Stream destination address */ +1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->PAR = DstAddress; +1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Configure DMA Stream source address */ +1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->M0AR = SrcAddress; +1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Peripheral to Memory */ +1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** else +1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Configure DMA Stream source address */ +1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->PAR = SrcAddress; + 59 .loc 1 1179 5 is_stmt 1 view .LVU12 + 60 .loc 1 1179 9 is_stmt 0 view .LVU13 + 61 0016 0368 ldr r3, [r0] + 62 .loc 1 1179 25 view .LVU14 + 63 0018 9960 str r1, [r3, #8] + 64 .LVL2: +1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Configure DMA Stream destination address */ +1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->M0AR = DstAddress; + 65 .loc 1 1182 5 is_stmt 1 view .LVU15 + 66 .loc 1 1182 9 is_stmt 0 view .LVU16 + 67 001a 0368 ldr r3, [r0] + 68 .loc 1 1182 26 view .LVU17 + 69 001c DA60 str r2, [r3, #12] + 70 .L1: +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 71 .loc 1 1184 1 view .LVU18 + ARM GAS /tmp/ccjAMZS2.s page 23 + + + 72 001e 30BC pop {r4, r5} + 73 .LCFI1: + 74 .cfi_remember_state + 75 .cfi_restore 5 + 76 .cfi_restore 4 + 77 .cfi_def_cfa_offset 0 + 78 0020 7047 bx lr + 79 .LVL3: + 80 .L5: + 81 .LCFI2: + 82 .cfi_restore_state +1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 83 .loc 1 1170 5 is_stmt 1 view .LVU19 +1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 84 .loc 1 1170 9 is_stmt 0 view .LVU20 + 85 0022 0368 ldr r3, [r0] +1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 86 .loc 1 1170 25 view .LVU21 + 87 0024 9A60 str r2, [r3, #8] + 88 .LVL4: +1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 89 .loc 1 1173 5 is_stmt 1 view .LVU22 +1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 90 .loc 1 1173 9 is_stmt 0 view .LVU23 + 91 0026 0368 ldr r3, [r0] +1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 92 .loc 1 1173 26 view .LVU24 + 93 0028 D960 str r1, [r3, #12] + 94 002a F8E7 b .L1 + 95 .cfi_endproc + 96 .LFE153: + 98 .section .text.DMA_CalcBaseAndBitshift,"ax",%progbits + 99 .align 1 + 100 .syntax unified + 101 .thumb + 102 .thumb_func + 104 DMA_CalcBaseAndBitshift: + 105 .LVL5: + 106 .LFB154: +1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** +1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @brief Returns the DMA Stream base address depending on stream number +1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @retval Stream base address +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 107 .loc 1 1193 1 is_stmt 1 view -0 + 108 .cfi_startproc + 109 @ args = 0, pretend = 0, frame = 0 + 110 @ frame_needed = 0, uses_anonymous_args = 0 + 111 @ link register save eliminated. + 112 .loc 1 1193 1 is_stmt 0 view .LVU26 + 113 0000 10B4 push {r4} + 114 .LCFI3: + 115 .cfi_def_cfa_offset 4 + ARM GAS /tmp/ccjAMZS2.s page 24 + + + 116 .cfi_offset 4, -4 +1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; + 117 .loc 1 1194 3 is_stmt 1 view .LVU27 + 118 .loc 1 1194 44 is_stmt 0 view .LVU28 + 119 0002 0368 ldr r3, [r0] + 120 .loc 1 1194 55 view .LVU29 + 121 0004 D9B2 uxtb r1, r3 + 122 .loc 1 1194 64 view .LVU30 + 123 0006 1039 subs r1, r1, #16 + 124 .loc 1 1194 12 view .LVU31 + 125 0008 0A4A ldr r2, .L10 + 126 000a A2FB0142 umull r4, r2, r2, r1 + 127 000e 1209 lsrs r2, r2, #4 + 128 .LVL6: +1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* lookup table for necessary bitshift of flags within status registers */ +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; + 129 .loc 1 1197 3 is_stmt 1 view .LVU32 +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->StreamIndex = flagBitshiftOffset[stream_number]; + 130 .loc 1 1198 3 view .LVU33 + 131 .loc 1 1198 41 is_stmt 0 view .LVU34 + 132 0010 094C ldr r4, .L10+4 + 133 0012 A25C ldrb r2, [r4, r2] @ zero_extendqisi2 + 134 .LVL7: + 135 .loc 1 1198 21 view .LVU35 + 136 0014 C265 str r2, [r0, #92] +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if (stream_number > 3U) + 137 .loc 1 1200 3 is_stmt 1 view .LVU36 + 138 .loc 1 1200 6 is_stmt 0 view .LVU37 + 139 0016 5F29 cmp r1, #95 + 140 0018 07D9 bls .L7 +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* return pointer to HISR and HIFCR */ +1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); + 141 .loc 1 1203 5 is_stmt 1 view .LVU38 + 142 .loc 1 1203 58 is_stmt 0 view .LVU39 + 143 001a 6FF30903 bfc r3, #0, #10 + 144 .loc 1 1203 81 view .LVU40 + 145 001e 0433 adds r3, r3, #4 + 146 .loc 1 1203 29 view .LVU41 + 147 0020 8365 str r3, [r0, #88] + 148 .L8: +1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** else +1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* return pointer to LISR and LIFCR */ +1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); +1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return hdma->StreamBaseAddress; + 149 .loc 1 1211 3 is_stmt 1 view .LVU42 +1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 150 .loc 1 1212 1 is_stmt 0 view .LVU43 + 151 0022 806D ldr r0, [r0, #88] + 152 .LVL8: + 153 .loc 1 1212 1 view .LVU44 + ARM GAS /tmp/ccjAMZS2.s page 25 + + + 154 0024 5DF8044B ldr r4, [sp], #4 + 155 .LCFI4: + 156 .cfi_remember_state + 157 .cfi_restore 4 + 158 .cfi_def_cfa_offset 0 + 159 0028 7047 bx lr + 160 .LVL9: + 161 .L7: + 162 .LCFI5: + 163 .cfi_restore_state +1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 164 .loc 1 1208 5 is_stmt 1 view .LVU45 +1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 165 .loc 1 1208 57 is_stmt 0 view .LVU46 + 166 002a 6FF30903 bfc r3, #0, #10 +1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 167 .loc 1 1208 29 view .LVU47 + 168 002e 8365 str r3, [r0, #88] + 169 0030 F7E7 b .L8 + 170 .L11: + 171 0032 00BF .align 2 + 172 .L10: + 173 0034 ABAAAAAA .word -1431655765 + 174 0038 00000000 .word flagBitshiftOffset.0 + 175 .cfi_endproc + 176 .LFE154: + 178 .section .text.DMA_CheckFifoParam,"ax",%progbits + 179 .align 1 + 180 .syntax unified + 181 .thumb + 182 .thumb_func + 184 DMA_CheckFifoParam: + 185 .LVL10: + 186 .LFB155: +1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /** +1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @brief Check compatibility between FIFO threshold level and size of the memory burst +1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * the configuration information for the specified DMA Stream. +1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** * @retval HAL status +1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** */ +1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) +1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 187 .loc 1 1221 1 is_stmt 1 view -0 + 188 .cfi_startproc + 189 @ args = 0, pretend = 0, frame = 0 + 190 @ frame_needed = 0, uses_anonymous_args = 0 + 191 @ link register save eliminated. +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 192 .loc 1 1222 3 view .LVU49 +1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tmp = hdma->Init.FIFOThreshold; + 193 .loc 1 1223 3 view .LVU50 + 194 .loc 1 1223 12 is_stmt 0 view .LVU51 + 195 0000 836A ldr r3, [r0, #40] + 196 .LVL11: +1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Memory Data size equal to Byte */ + ARM GAS /tmp/ccjAMZS2.s page 26 + + +1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) + 197 .loc 1 1226 3 is_stmt 1 view .LVU52 + 198 .loc 1 1226 16 is_stmt 0 view .LVU53 + 199 0002 8269 ldr r2, [r0, #24] + 200 .loc 1 1226 5 view .LVU54 + 201 0004 92B9 cbnz r2, .L13 +1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** switch (tmp) + 202 .loc 1 1228 5 is_stmt 1 view .LVU55 + 203 0006 012B cmp r3, #1 + 204 0008 0AD0 beq .L14 + 205 000a 022B cmp r3, #2 + 206 000c 02D0 beq .L15 + 207 000e 0BB1 cbz r3, .L15 + 208 0010 0020 movs r0, #0 + 209 .LVL12: + 210 .loc 1 1228 5 is_stmt 0 view .LVU56 + 211 0012 7047 bx lr + 212 .LVL13: + 213 .L15: +1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_1QUARTERFULL: +1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_3QUARTERSFULL: +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + 214 .loc 1 1232 7 is_stmt 1 view .LVU57 + 215 .loc 1 1232 22 is_stmt 0 view .LVU58 + 216 0014 C36A ldr r3, [r0, #44] + 217 .LVL14: + 218 .loc 1 1232 10 view .LVU59 + 219 0016 13F0807F tst r3, #16777216 + 220 001a 28D1 bne .L23 +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tmp = hdma->Init.FIFOThreshold; + 221 .loc 1 1222 21 view .LVU60 + 222 001c 0020 movs r0, #0 + 223 .LVL15: +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tmp = hdma->Init.FIFOThreshold; + 224 .loc 1 1222 21 view .LVU61 + 225 001e 7047 bx lr + 226 .LVL16: + 227 .L14: +1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** status = HAL_ERROR; +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_HALFFULL: +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if (hdma->Init.MemBurst == DMA_MBURST_INC16) + 228 .loc 1 1238 7 is_stmt 1 view .LVU62 + 229 .loc 1 1238 21 is_stmt 0 view .LVU63 + 230 0020 C36A ldr r3, [r0, #44] + 231 .LVL17: + 232 .loc 1 1238 10 view .LVU64 + 233 0022 B3F1C07F cmp r3, #25165824 + 234 0026 24D0 beq .L24 +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tmp = hdma->Init.FIFOThreshold; + 235 .loc 1 1222 21 view .LVU65 + 236 0028 0020 movs r0, #0 + 237 .LVL18: + ARM GAS /tmp/ccjAMZS2.s page 27 + + +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tmp = hdma->Init.FIFOThreshold; + 238 .loc 1 1222 21 view .LVU66 + 239 002a 7047 bx lr + 240 .LVL19: + 241 .L13: +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** status = HAL_ERROR; +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_FULL: +1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** default: +1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Memory Data size equal to Half-Word */ +1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + 242 .loc 1 1251 8 is_stmt 1 view .LVU67 + 243 .loc 1 1251 11 is_stmt 0 view .LVU68 + 244 002c B2F5005F cmp r2, #8192 + 245 0030 09D0 beq .L31 +1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** switch (tmp) +1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_1QUARTERFULL: +1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_3QUARTERSFULL: +1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** status = HAL_ERROR; +1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_HALFFULL: +1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) +1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** status = HAL_ERROR; +1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_FULL: +1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if (hdma->Init.MemBurst == DMA_MBURST_INC16) +1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** status = HAL_ERROR; +1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** default: +1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Memory Data size equal to Word */ +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** else +1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** switch (tmp) + 246 .loc 1 1279 5 is_stmt 1 view .LVU69 + 247 0032 022B cmp r3, #2 + 248 0034 25D9 bls .L28 + 249 0036 032B cmp r3, #3 + 250 0038 25D1 bne .L29 +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_1QUARTERFULL: + ARM GAS /tmp/ccjAMZS2.s page 28 + + +1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_HALFFULL: +1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_3QUARTERSFULL: +1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** status = HAL_ERROR; +1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** case DMA_FIFO_THRESHOLD_FULL: +1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + 251 .loc 1 1287 7 view .LVU70 + 252 .loc 1 1287 22 is_stmt 0 view .LVU71 + 253 003a C36A ldr r3, [r0, #44] + 254 .LVL20: + 255 .loc 1 1287 10 view .LVU72 + 256 003c 13F0807F tst r3, #16777216 + 257 0040 23D1 bne .L30 +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tmp = hdma->Init.FIFOThreshold; + 258 .loc 1 1222 21 view .LVU73 + 259 0042 0020 movs r0, #0 + 260 .LVL21: +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tmp = hdma->Init.FIFOThreshold; + 261 .loc 1 1222 21 view .LVU74 + 262 0044 7047 bx lr + 263 .LVL22: + 264 .L31: +1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 265 .loc 1 1253 5 is_stmt 1 view .LVU75 + 266 0046 032B cmp r3, #3 + 267 0048 03D8 bhi .L18 + 268 004a DFE803F0 tbb [pc, r3] + 269 .L20: + 270 004e 14 .byte (.L25-.L20)/2 + 271 004f 04 .byte (.L21-.L20)/2 + 272 0050 14 .byte (.L25-.L20)/2 + 273 0051 0A .byte (.L19-.L20)/2 + 274 .p2align 1 + 275 .L18: + 276 0052 0020 movs r0, #0 + 277 .LVL23: +1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 278 .loc 1 1253 5 is_stmt 0 view .LVU76 + 279 0054 7047 bx lr + 280 .LVL24: + 281 .L21: +1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 282 .loc 1 1260 7 is_stmt 1 view .LVU77 +1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 283 .loc 1 1260 22 is_stmt 0 view .LVU78 + 284 0056 C36A ldr r3, [r0, #44] + 285 .LVL25: +1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 286 .loc 1 1260 10 view .LVU79 + 287 0058 13F0807F tst r3, #16777216 + 288 005c 0DD1 bne .L26 +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tmp = hdma->Init.FIFOThreshold; + 289 .loc 1 1222 21 view .LVU80 + 290 005e 0020 movs r0, #0 + 291 .LVL26: +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tmp = hdma->Init.FIFOThreshold; + 292 .loc 1 1222 21 view .LVU81 + ARM GAS /tmp/ccjAMZS2.s page 29 + + + 293 0060 7047 bx lr + 294 .LVL27: + 295 .L19: +1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 296 .loc 1 1266 7 is_stmt 1 view .LVU82 +1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 297 .loc 1 1266 21 is_stmt 0 view .LVU83 + 298 0062 C36A ldr r3, [r0, #44] + 299 .LVL28: +1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 300 .loc 1 1266 10 view .LVU84 + 301 0064 B3F1C07F cmp r3, #25165824 + 302 0068 09D0 beq .L27 +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tmp = hdma->Init.FIFOThreshold; + 303 .loc 1 1222 21 view .LVU85 + 304 006a 0020 movs r0, #0 + 305 .LVL29: +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tmp = hdma->Init.FIFOThreshold; + 306 .loc 1 1222 21 view .LVU86 + 307 006c 7047 bx lr + 308 .LVL30: + 309 .L23: +1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 310 .loc 1 1234 16 view .LVU87 + 311 006e 0120 movs r0, #1 + 312 .LVL31: +1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 313 .loc 1 1234 16 view .LVU88 + 314 0070 7047 bx lr + 315 .LVL32: + 316 .L24: +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 317 .loc 1 1240 16 view .LVU89 + 318 0072 0120 movs r0, #1 + 319 .LVL33: +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 320 .loc 1 1240 16 view .LVU90 + 321 0074 7047 bx lr + 322 .LVL34: + 323 .L25: +1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 324 .loc 1 1257 14 view .LVU91 + 325 0076 0120 movs r0, #1 + 326 .LVL35: +1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 327 .loc 1 1257 14 view .LVU92 + 328 0078 7047 bx lr + 329 .LVL36: + 330 .L26: +1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 331 .loc 1 1262 16 view .LVU93 + 332 007a 0120 movs r0, #1 + 333 .LVL37: +1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 334 .loc 1 1262 16 view .LVU94 + 335 007c 7047 bx lr + 336 .LVL38: + ARM GAS /tmp/ccjAMZS2.s page 30 + + + 337 .L27: +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 338 .loc 1 1268 16 view .LVU95 + 339 007e 0120 movs r0, #1 + 340 .LVL39: +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 341 .loc 1 1268 16 view .LVU96 + 342 0080 7047 bx lr + 343 .LVL40: + 344 .L28: +1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 345 .loc 1 1284 14 view .LVU97 + 346 0082 0120 movs r0, #1 + 347 .LVL41: +1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 348 .loc 1 1284 14 view .LVU98 + 349 0084 7047 bx lr + 350 .LVL42: + 351 .L29: +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 352 .loc 1 1279 5 view .LVU99 + 353 0086 0020 movs r0, #0 + 354 .LVL43: +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 355 .loc 1 1279 5 view .LVU100 + 356 0088 7047 bx lr + 357 .LVL44: + 358 .L30: +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { +1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** status = HAL_ERROR; + 359 .loc 1 1289 16 view .LVU101 + 360 008a 0120 movs r0, #1 + 361 .LVL45: +1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** default: +1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; +1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } +1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** +1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return status; + 362 .loc 1 1297 3 is_stmt 1 view .LVU102 +1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 363 .loc 1 1298 1 is_stmt 0 view .LVU103 + 364 008c 7047 bx lr + 365 .cfi_endproc + 366 .LFE155: + 368 .section .text.HAL_DMA_Init,"ax",%progbits + 369 .align 1 + 370 .global HAL_DMA_Init + 371 .syntax unified + 372 .thumb + 373 .thumb_func + 375 HAL_DMA_Init: + 376 .LVL46: + 377 .LFB141: + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tmp = 0U; + ARM GAS /tmp/ccjAMZS2.s page 31 + + + 378 .loc 1 172 1 is_stmt 1 view -0 + 379 .cfi_startproc + 380 @ args = 0, pretend = 0, frame = 0 + 381 @ frame_needed = 0, uses_anonymous_args = 0 + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tmp = 0U; + 382 .loc 1 172 1 is_stmt 0 view .LVU105 + 383 0000 70B5 push {r4, r5, r6, lr} + 384 .LCFI6: + 385 .cfi_def_cfa_offset 16 + 386 .cfi_offset 4, -16 + 387 .cfi_offset 5, -12 + 388 .cfi_offset 6, -8 + 389 .cfi_offset 14, -4 + 390 0002 0446 mov r4, r0 + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tickstart = HAL_GetTick(); + 391 .loc 1 173 3 is_stmt 1 view .LVU106 + 392 .LVL47: + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** DMA_Base_Registers *regs; + 393 .loc 1 174 3 view .LVU107 + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** DMA_Base_Registers *regs; + 394 .loc 1 174 24 is_stmt 0 view .LVU108 + 395 0004 FFF7FEFF bl HAL_GetTick + 396 .LVL48: + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 397 .loc 1 175 3 is_stmt 1 view .LVU109 + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 398 .loc 1 178 3 view .LVU110 + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 399 .loc 1 178 5 is_stmt 0 view .LVU111 + 400 0008 002C cmp r4, #0 + 401 000a 5CD0 beq .L38 + 402 000c 0546 mov r5, r0 + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_CHANNEL(hdma->Init.Channel)); + 403 .loc 1 184 3 is_stmt 1 view .LVU112 + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + 404 .loc 1 185 3 view .LVU113 + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + 405 .loc 1 186 3 view .LVU114 + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + 406 .loc 1 187 3 view .LVU115 + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + 407 .loc 1 188 3 view .LVU116 + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + 408 .loc 1 189 3 view .LVU117 + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_MODE(hdma->Init.Mode)); + 409 .loc 1 190 3 view .LVU118 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + 410 .loc 1 191 3 view .LVU119 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); + 411 .loc 1 192 3 view .LVU120 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* Check the memory burst, peripheral burst and FIFO threshold parameters only + 412 .loc 1 193 3 view .LVU121 + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 413 .loc 1 196 3 view .LVU122 + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); + 414 .loc 1 198 5 view .LVU123 + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); + ARM GAS /tmp/ccjAMZS2.s page 32 + + + 415 .loc 1 199 5 view .LVU124 + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 416 .loc 1 200 5 view .LVU125 + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 417 .loc 1 204 3 view .LVU126 + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 418 .loc 1 204 15 is_stmt 0 view .LVU127 + 419 000e 0223 movs r3, #2 + 420 0010 84F83530 strb r3, [r4, #53] + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 421 .loc 1 207 3 is_stmt 1 view .LVU128 + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 422 .loc 1 207 3 view .LVU129 + 423 0014 0023 movs r3, #0 + 424 0016 84F83430 strb r3, [r4, #52] + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 425 .loc 1 207 3 view .LVU130 + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 426 .loc 1 211 3 view .LVU131 + 427 001a 2268 ldr r2, [r4] + 428 001c 1368 ldr r3, [r2] + 429 001e 23F00103 bic r3, r3, #1 + 430 0022 1360 str r3, [r2] + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 431 .loc 1 214 3 view .LVU132 + 432 .LVL49: + 433 .L34: + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 434 .loc 1 214 44 view .LVU133 + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 435 .loc 1 214 14 is_stmt 0 view .LVU134 + 436 0024 2368 ldr r3, [r4] + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 437 .loc 1 214 24 view .LVU135 + 438 0026 1A68 ldr r2, [r3] + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 439 .loc 1 214 44 view .LVU136 + 440 0028 12F0010F tst r2, #1 + 441 002c 0AD0 beq .L40 + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 442 .loc 1 217 5 is_stmt 1 view .LVU137 + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 443 .loc 1 217 9 is_stmt 0 view .LVU138 + 444 002e FFF7FEFF bl HAL_GetTick + 445 .LVL50: + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 446 .loc 1 217 23 discriminator 1 view .LVU139 + 447 0032 431B subs r3, r0, r5 + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 448 .loc 1 217 7 discriminator 1 view .LVU140 + 449 0034 052B cmp r3, #5 + 450 0036 F5D9 bls .L34 + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 451 .loc 1 220 7 is_stmt 1 view .LVU141 + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 452 .loc 1 220 23 is_stmt 0 view .LVU142 + 453 0038 2023 movs r3, #32 + ARM GAS /tmp/ccjAMZS2.s page 33 + + + 454 003a 6365 str r3, [r4, #84] + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 455 .loc 1 223 7 is_stmt 1 view .LVU143 + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 456 .loc 1 223 19 is_stmt 0 view .LVU144 + 457 003c 0320 movs r0, #3 + 458 003e 84F83500 strb r0, [r4, #53] + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 459 .loc 1 225 7 is_stmt 1 view .LVU145 + 460 .LVL51: + 461 .L33: + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 462 .loc 1 303 1 is_stmt 0 view .LVU146 + 463 0042 70BD pop {r4, r5, r6, pc} + 464 .LVL52: + 465 .L40: + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 466 .loc 1 230 3 is_stmt 1 view .LVU147 + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 467 .loc 1 230 7 is_stmt 0 view .LVU148 + 468 0044 1A68 ldr r2, [r3] + 469 .LVL53: + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + 470 .loc 1 233 3 is_stmt 1 view .LVU149 + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + 471 .loc 1 233 7 is_stmt 0 view .LVU150 + 472 0046 2149 ldr r1, .L43 + 473 0048 1140 ands r1, r1, r2 + 474 .LVL54: + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 475 .loc 1 239 3 is_stmt 1 view .LVU151 + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 476 .loc 1 239 21 is_stmt 0 view .LVU152 + 477 004a 6268 ldr r2, [r4, #4] + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 478 .loc 1 239 54 view .LVU153 + 479 004c A068 ldr r0, [r4, #8] + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 480 .loc 1 239 42 view .LVU154 + 481 004e 0243 orrs r2, r2, r0 + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 482 .loc 1 240 21 view .LVU155 + 483 0050 E068 ldr r0, [r4, #12] + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 484 .loc 1 239 72 view .LVU156 + 485 0052 0243 orrs r2, r2, r0 + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 486 .loc 1 240 54 view .LVU157 + 487 0054 2069 ldr r0, [r4, #16] + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 488 .loc 1 240 42 view .LVU158 + 489 0056 0243 orrs r2, r2, r0 + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Init.Mode | hdma->Init.Priority; + 490 .loc 1 241 21 view .LVU159 + 491 0058 6069 ldr r0, [r4, #20] + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 492 .loc 1 240 72 view .LVU160 + ARM GAS /tmp/ccjAMZS2.s page 34 + + + 493 005a 0243 orrs r2, r2, r0 + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Init.Mode | hdma->Init.Priority; + 494 .loc 1 241 54 view .LVU161 + 495 005c A069 ldr r0, [r4, #24] + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Init.Mode | hdma->Init.Priority; + 496 .loc 1 241 42 view .LVU162 + 497 005e 0243 orrs r2, r2, r0 + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 498 .loc 1 242 21 view .LVU163 + 499 0060 E069 ldr r0, [r4, #28] + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Init.Mode | hdma->Init.Priority; + 500 .loc 1 241 72 view .LVU164 + 501 0062 0243 orrs r2, r2, r0 + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 502 .loc 1 242 54 view .LVU165 + 503 0064 206A ldr r0, [r4, #32] + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 504 .loc 1 242 42 view .LVU166 + 505 0066 0243 orrs r2, r2, r0 + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 506 .loc 1 239 7 view .LVU167 + 507 0068 0A43 orrs r2, r2, r1 + 508 .LVL55: + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 509 .loc 1 245 3 is_stmt 1 view .LVU168 + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 510 .loc 1 245 16 is_stmt 0 view .LVU169 + 511 006a 616A ldr r1, [r4, #36] + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 512 .loc 1 245 5 view .LVU170 + 513 006c 0429 cmp r1, #4 + 514 006e 1ED0 beq .L41 + 515 .L36: + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 516 .loc 1 252 3 is_stmt 1 view .LVU171 + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 517 .loc 1 252 22 is_stmt 0 view .LVU172 + 518 0070 1A60 str r2, [r3] + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 519 .loc 1 255 3 is_stmt 1 view .LVU173 + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 520 .loc 1 255 13 is_stmt 0 view .LVU174 + 521 0072 2668 ldr r6, [r4] + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 522 .loc 1 255 7 view .LVU175 + 523 0074 7569 ldr r5, [r6, #20] + 524 .LVL56: + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 525 .loc 1 258 3 is_stmt 1 view .LVU176 + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 526 .loc 1 258 7 is_stmt 0 view .LVU177 + 527 0076 25F00705 bic r5, r5, #7 + 528 .LVL57: + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 529 .loc 1 261 3 is_stmt 1 view .LVU178 + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 530 .loc 1 261 20 is_stmt 0 view .LVU179 + ARM GAS /tmp/ccjAMZS2.s page 35 + + + 531 007a 636A ldr r3, [r4, #36] + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 532 .loc 1 261 7 view .LVU180 + 533 007c 1D43 orrs r5, r5, r3 + 534 .LVL58: + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 535 .loc 1 264 3 is_stmt 1 view .LVU181 + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 536 .loc 1 264 5 is_stmt 0 view .LVU182 + 537 007e 042B cmp r3, #4 + 538 0080 07D1 bne .L37 + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 539 .loc 1 267 5 is_stmt 1 view .LVU183 + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 540 .loc 1 267 22 is_stmt 0 view .LVU184 + 541 0082 A36A ldr r3, [r4, #40] + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 542 .loc 1 267 9 view .LVU185 + 543 0084 1D43 orrs r5, r5, r3 + 544 .LVL59: + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 545 .loc 1 271 5 is_stmt 1 view .LVU186 + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 546 .loc 1 271 19 is_stmt 0 view .LVU187 + 547 0086 E36A ldr r3, [r4, #44] + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 548 .loc 1 271 8 view .LVU188 + 549 0088 1BB1 cbz r3, .L37 + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 550 .loc 1 273 7 is_stmt 1 view .LVU189 + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 551 .loc 1 273 11 is_stmt 0 view .LVU190 + 552 008a 2046 mov r0, r4 + 553 008c FFF7FEFF bl DMA_CheckFifoParam + 554 .LVL60: + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 555 .loc 1 273 10 discriminator 1 view .LVU191 + 556 0090 90B9 cbnz r0, .L42 + 557 .L37: + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 558 .loc 1 287 3 is_stmt 1 view .LVU192 + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 559 .loc 1 287 23 is_stmt 0 view .LVU193 + 560 0092 7561 str r5, [r6, #20] + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 561 .loc 1 291 3 is_stmt 1 view .LVU194 + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 562 .loc 1 291 32 is_stmt 0 view .LVU195 + 563 0094 2046 mov r0, r4 + 564 0096 FFF7FEFF bl DMA_CalcBaseAndBitshift + 565 .LVL61: + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 566 .loc 1 294 3 is_stmt 1 view .LVU196 + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 567 .loc 1 294 29 is_stmt 0 view .LVU197 + 568 009a E26D ldr r2, [r4, #92] + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + ARM GAS /tmp/ccjAMZS2.s page 36 + + + 569 .loc 1 294 22 view .LVU198 + 570 009c 3F23 movs r3, #63 + 571 009e 9340 lsls r3, r3, r2 + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 572 .loc 1 294 14 view .LVU199 + 573 00a0 8360 str r3, [r0, #8] + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 574 .loc 1 297 3 is_stmt 1 view .LVU200 + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 575 .loc 1 297 19 is_stmt 0 view .LVU201 + 576 00a2 0020 movs r0, #0 + 577 .LVL62: + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 578 .loc 1 297 19 view .LVU202 + 579 00a4 6065 str r0, [r4, #84] + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 580 .loc 1 300 3 is_stmt 1 view .LVU203 + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 581 .loc 1 300 15 is_stmt 0 view .LVU204 + 582 00a6 0123 movs r3, #1 + 583 00a8 84F83530 strb r3, [r4, #53] + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 584 .loc 1 302 3 is_stmt 1 view .LVU205 + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 585 .loc 1 302 10 is_stmt 0 view .LVU206 + 586 00ac C9E7 b .L33 + 587 .LVL63: + 588 .L41: + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 589 .loc 1 248 5 is_stmt 1 view .LVU207 + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 590 .loc 1 248 23 is_stmt 0 view .LVU208 + 591 00ae E16A ldr r1, [r4, #44] + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 592 .loc 1 248 45 view .LVU209 + 593 00b0 206B ldr r0, [r4, #48] + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 594 .loc 1 248 33 view .LVU210 + 595 00b2 0143 orrs r1, r1, r0 + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 596 .loc 1 248 9 view .LVU211 + 597 00b4 0A43 orrs r2, r2, r1 + 598 .LVL64: + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 599 .loc 1 248 9 view .LVU212 + 600 00b6 DBE7 b .L36 + 601 .LVL65: + 602 .L42: + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 603 .loc 1 276 9 is_stmt 1 view .LVU213 + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 604 .loc 1 276 25 is_stmt 0 view .LVU214 + 605 00b8 4023 movs r3, #64 + 606 00ba 6365 str r3, [r4, #84] + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 607 .loc 1 279 9 is_stmt 1 view .LVU215 + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + ARM GAS /tmp/ccjAMZS2.s page 37 + + + 608 .loc 1 279 21 is_stmt 0 view .LVU216 + 609 00bc 0023 movs r3, #0 + 610 00be 84F83530 strb r3, [r4, #53] + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 611 .loc 1 281 9 is_stmt 1 view .LVU217 + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 612 .loc 1 281 16 is_stmt 0 view .LVU218 + 613 00c2 0120 movs r0, #1 + 614 00c4 BDE7 b .L33 + 615 .LVL66: + 616 .L38: + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 617 .loc 1 180 12 view .LVU219 + 618 00c6 0120 movs r0, #1 + 619 .LVL67: + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 620 .loc 1 180 12 view .LVU220 + 621 00c8 BBE7 b .L33 + 622 .L44: + 623 00ca 00BF .align 2 + 624 .L43: + 625 00cc 3F8010E0 .word -535789505 + 626 .cfi_endproc + 627 .LFE141: + 629 .section .text.HAL_DMA_DeInit,"ax",%progbits + 630 .align 1 + 631 .global HAL_DMA_DeInit + 632 .syntax unified + 633 .thumb + 634 .thumb_func + 636 HAL_DMA_DeInit: + 637 .LVL68: + 638 .LFB142: + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** DMA_Base_Registers *regs; + 639 .loc 1 312 1 is_stmt 1 view -0 + 640 .cfi_startproc + 641 @ args = 0, pretend = 0, frame = 0 + 642 @ frame_needed = 0, uses_anonymous_args = 0 + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 643 .loc 1 313 3 view .LVU222 + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 644 .loc 1 316 3 view .LVU223 + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 645 .loc 1 316 5 is_stmt 0 view .LVU224 + 646 0000 0028 cmp r0, #0 + 647 0002 2DD0 beq .L47 + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** DMA_Base_Registers *regs; + 648 .loc 1 312 1 view .LVU225 + 649 0004 38B5 push {r3, r4, r5, lr} + 650 .LCFI7: + 651 .cfi_def_cfa_offset 16 + 652 .cfi_offset 3, -16 + 653 .cfi_offset 4, -12 + 654 .cfi_offset 5, -8 + 655 .cfi_offset 14, -4 + 656 0006 0546 mov r5, r0 + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + ARM GAS /tmp/ccjAMZS2.s page 38 + + + 657 .loc 1 322 3 is_stmt 1 view .LVU226 + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 658 .loc 1 322 10 is_stmt 0 view .LVU227 + 659 0008 90F83500 ldrb r0, [r0, #53] @ zero_extendqisi2 + 660 .LVL69: + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 661 .loc 1 322 10 view .LVU228 + 662 000c C0B2 uxtb r0, r0 + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 663 .loc 1 322 5 view .LVU229 + 664 000e 0228 cmp r0, #2 + 665 0010 25D0 beq .L46 + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 666 .loc 1 329 3 is_stmt 1 view .LVU230 + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 667 .loc 1 332 3 view .LVU231 + 668 0012 2A68 ldr r2, [r5] + 669 0014 1368 ldr r3, [r2] + 670 0016 23F00103 bic r3, r3, #1 + 671 001a 1360 str r3, [r2] + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 672 .loc 1 335 3 view .LVU232 + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 673 .loc 1 335 7 is_stmt 0 view .LVU233 + 674 001c 2B68 ldr r3, [r5] + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 675 .loc 1 335 24 view .LVU234 + 676 001e 0024 movs r4, #0 + 677 0020 1C60 str r4, [r3] + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 678 .loc 1 338 3 is_stmt 1 view .LVU235 + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 679 .loc 1 338 7 is_stmt 0 view .LVU236 + 680 0022 2B68 ldr r3, [r5] + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 681 .loc 1 338 24 view .LVU237 + 682 0024 5C60 str r4, [r3, #4] + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 683 .loc 1 341 3 is_stmt 1 view .LVU238 + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 684 .loc 1 341 7 is_stmt 0 view .LVU239 + 685 0026 2B68 ldr r3, [r5] + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 686 .loc 1 341 24 view .LVU240 + 687 0028 9C60 str r4, [r3, #8] + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 688 .loc 1 344 3 is_stmt 1 view .LVU241 + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 689 .loc 1 344 7 is_stmt 0 view .LVU242 + 690 002a 2B68 ldr r3, [r5] + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 691 .loc 1 344 24 view .LVU243 + 692 002c DC60 str r4, [r3, #12] + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 693 .loc 1 347 3 is_stmt 1 view .LVU244 + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 694 .loc 1 347 7 is_stmt 0 view .LVU245 + ARM GAS /tmp/ccjAMZS2.s page 39 + + + 695 002e 2B68 ldr r3, [r5] + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 696 .loc 1 347 24 view .LVU246 + 697 0030 1C61 str r4, [r3, #16] + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 698 .loc 1 350 3 is_stmt 1 view .LVU247 + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 699 .loc 1 350 7 is_stmt 0 view .LVU248 + 700 0032 2B68 ldr r3, [r5] + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 701 .loc 1 350 24 view .LVU249 + 702 0034 2122 movs r2, #33 + 703 0036 5A61 str r2, [r3, #20] + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 704 .loc 1 353 3 is_stmt 1 view .LVU250 + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 705 .loc 1 353 32 is_stmt 0 view .LVU251 + 706 0038 2846 mov r0, r5 + 707 003a FFF7FEFF bl DMA_CalcBaseAndBitshift + 708 .LVL70: + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 709 .loc 1 356 3 is_stmt 1 view .LVU252 + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 710 .loc 1 356 29 is_stmt 0 view .LVU253 + 711 003e EA6D ldr r2, [r5, #92] + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 712 .loc 1 356 22 view .LVU254 + 713 0040 3F23 movs r3, #63 + 714 0042 9340 lsls r3, r3, r2 + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 715 .loc 1 356 14 view .LVU255 + 716 0044 8360 str r3, [r0, #8] + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 717 .loc 1 359 3 is_stmt 1 view .LVU256 + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 718 .loc 1 359 26 is_stmt 0 view .LVU257 + 719 0046 EC63 str r4, [r5, #60] + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferM1CpltCallback = NULL; + 720 .loc 1 360 3 is_stmt 1 view .LVU258 + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferM1CpltCallback = NULL; + 721 .loc 1 360 30 is_stmt 0 view .LVU259 + 722 0048 2C64 str r4, [r5, #64] + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferM1HalfCpltCallback = NULL; + 723 .loc 1 361 3 is_stmt 1 view .LVU260 + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferM1HalfCpltCallback = NULL; + 724 .loc 1 361 28 is_stmt 0 view .LVU261 + 725 004a 6C64 str r4, [r5, #68] + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 726 .loc 1 362 3 is_stmt 1 view .LVU262 + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 727 .loc 1 362 32 is_stmt 0 view .LVU263 + 728 004c AC64 str r4, [r5, #72] + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 729 .loc 1 363 3 is_stmt 1 view .LVU264 + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 730 .loc 1 363 27 is_stmt 0 view .LVU265 + 731 004e EC64 str r4, [r5, #76] + ARM GAS /tmp/ccjAMZS2.s page 40 + + + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 732 .loc 1 364 3 is_stmt 1 view .LVU266 + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 733 .loc 1 364 27 is_stmt 0 view .LVU267 + 734 0050 2C65 str r4, [r5, #80] + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 735 .loc 1 367 3 is_stmt 1 view .LVU268 + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 736 .loc 1 367 19 is_stmt 0 view .LVU269 + 737 0052 6C65 str r4, [r5, #84] + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 738 .loc 1 370 3 is_stmt 1 view .LVU270 + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 739 .loc 1 370 15 is_stmt 0 view .LVU271 + 740 0054 85F83540 strb r4, [r5, #53] + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 741 .loc 1 373 3 is_stmt 1 view .LVU272 + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 742 .loc 1 373 3 view .LVU273 + 743 0058 85F83440 strb r4, [r5, #52] + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 744 .loc 1 373 3 view .LVU274 + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 745 .loc 1 375 3 view .LVU275 + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 746 .loc 1 375 10 is_stmt 0 view .LVU276 + 747 005c 2046 mov r0, r4 + 748 .LVL71: + 749 .L46: + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 750 .loc 1 376 1 view .LVU277 + 751 005e 38BD pop {r3, r4, r5, pc} + 752 .LVL72: + 753 .L47: + 754 .LCFI8: + 755 .cfi_def_cfa_offset 0 + 756 .cfi_restore 3 + 757 .cfi_restore 4 + 758 .cfi_restore 5 + 759 .cfi_restore 14 + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 760 .loc 1 318 12 view .LVU278 + 761 0060 0120 movs r0, #1 + 762 .LVL73: + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 763 .loc 1 376 1 view .LVU279 + 764 0062 7047 bx lr + 765 .cfi_endproc + 766 .LFE142: + 768 .section .text.HAL_DMA_Start,"ax",%progbits + 769 .align 1 + 770 .global HAL_DMA_Start + 771 .syntax unified + 772 .thumb + 773 .thumb_func + 775 HAL_DMA_Start: + 776 .LVL74: + ARM GAS /tmp/ccjAMZS2.s page 41 + + + 777 .LFB143: + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 778 .loc 1 410 1 is_stmt 1 view -0 + 779 .cfi_startproc + 780 @ args = 0, pretend = 0, frame = 0 + 781 @ frame_needed = 0, uses_anonymous_args = 0 + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 782 .loc 1 410 1 is_stmt 0 view .LVU281 + 783 0000 38B5 push {r3, r4, r5, lr} + 784 .LCFI9: + 785 .cfi_def_cfa_offset 16 + 786 .cfi_offset 3, -16 + 787 .cfi_offset 4, -12 + 788 .cfi_offset 5, -8 + 789 .cfi_offset 14, -4 + 790 0002 0446 mov r4, r0 + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 791 .loc 1 411 3 is_stmt 1 view .LVU282 + 792 .LVL75: + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 793 .loc 1 414 3 view .LVU283 + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 794 .loc 1 417 3 view .LVU284 + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 795 .loc 1 417 3 view .LVU285 + 796 0004 90F83400 ldrb r0, [r0, #52] @ zero_extendqisi2 + 797 .LVL76: + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 798 .loc 1 417 3 is_stmt 0 view .LVU286 + 799 0008 0128 cmp r0, #1 + 800 000a 1BD0 beq .L55 + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 801 .loc 1 417 3 is_stmt 1 discriminator 2 view .LVU287 + 802 000c 0120 movs r0, #1 + 803 000e 84F83400 strb r0, [r4, #52] + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 804 .loc 1 417 3 discriminator 2 view .LVU288 + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 805 .loc 1 419 3 view .LVU289 + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 806 .loc 1 419 33 is_stmt 0 view .LVU290 + 807 0012 94F83500 ldrb r0, [r4, #53] @ zero_extendqisi2 + 808 0016 C0B2 uxtb r0, r0 + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 809 .loc 1 419 5 view .LVU291 + 810 0018 0128 cmp r0, #1 + 811 001a 04D0 beq .L57 + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 812 .loc 1 436 5 is_stmt 1 view .LVU292 + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 813 .loc 1 436 5 view .LVU293 + 814 001c 0023 movs r3, #0 + 815 .LVL77: + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 816 .loc 1 436 5 is_stmt 0 view .LVU294 + 817 001e 84F83430 strb r3, [r4, #52] + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + ARM GAS /tmp/ccjAMZS2.s page 42 + + + 818 .loc 1 436 5 is_stmt 1 view .LVU295 + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 819 .loc 1 439 5 view .LVU296 + 820 .LVL78: + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 821 .loc 1 439 12 is_stmt 0 view .LVU297 + 822 0022 0220 movs r0, #2 + 823 .LVL79: + 824 .L53: + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 825 .loc 1 442 1 view .LVU298 + 826 0024 38BD pop {r3, r4, r5, pc} + 827 .LVL80: + 828 .L57: + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 829 .loc 1 422 5 is_stmt 1 view .LVU299 + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 830 .loc 1 422 17 is_stmt 0 view .LVU300 + 831 0026 0220 movs r0, #2 + 832 0028 84F83500 strb r0, [r4, #53] + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 833 .loc 1 425 5 is_stmt 1 view .LVU301 + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 834 .loc 1 425 21 is_stmt 0 view .LVU302 + 835 002c 0025 movs r5, #0 + 836 002e 6565 str r5, [r4, #84] + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 837 .loc 1 428 5 is_stmt 1 view .LVU303 + 838 0030 2046 mov r0, r4 + 839 0032 FFF7FEFF bl DMA_SetConfig + 840 .LVL81: + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 841 .loc 1 431 5 view .LVU304 + 842 0036 2268 ldr r2, [r4] + 843 0038 1368 ldr r3, [r2] + 844 003a 43F00103 orr r3, r3, #1 + 845 003e 1360 str r3, [r2] + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 846 .loc 1 411 21 is_stmt 0 view .LVU305 + 847 0040 2846 mov r0, r5 + 848 0042 EFE7 b .L53 + 849 .LVL82: + 850 .L55: + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 851 .loc 1 417 3 discriminator 1 view .LVU306 + 852 0044 0220 movs r0, #2 + 853 0046 EDE7 b .L53 + 854 .cfi_endproc + 855 .LFE143: + 857 .section .text.HAL_DMA_Start_IT,"ax",%progbits + 858 .align 1 + 859 .global HAL_DMA_Start_IT + 860 .syntax unified + 861 .thumb + 862 .thumb_func + 864 HAL_DMA_Start_IT: + 865 .LVL83: + ARM GAS /tmp/ccjAMZS2.s page 43 + + + 866 .LFB144: + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 867 .loc 1 454 1 is_stmt 1 view -0 + 868 .cfi_startproc + 869 @ args = 0, pretend = 0, frame = 0 + 870 @ frame_needed = 0, uses_anonymous_args = 0 + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 871 .loc 1 454 1 is_stmt 0 view .LVU308 + 872 0000 38B5 push {r3, r4, r5, lr} + 873 .LCFI10: + 874 .cfi_def_cfa_offset 16 + 875 .cfi_offset 3, -16 + 876 .cfi_offset 4, -12 + 877 .cfi_offset 5, -8 + 878 .cfi_offset 14, -4 + 879 0002 0446 mov r4, r0 + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 880 .loc 1 455 3 is_stmt 1 view .LVU309 + 881 .LVL84: + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 882 .loc 1 458 3 view .LVU310 + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 883 .loc 1 458 56 is_stmt 0 view .LVU311 + 884 0004 856D ldr r5, [r0, #88] + 885 .LVL85: + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 886 .loc 1 461 3 is_stmt 1 view .LVU312 + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 887 .loc 1 464 3 view .LVU313 + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 888 .loc 1 464 3 view .LVU314 + 889 0006 90F83400 ldrb r0, [r0, #52] @ zero_extendqisi2 + 890 .LVL86: + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 891 .loc 1 464 3 is_stmt 0 view .LVU315 + 892 000a 0128 cmp r0, #1 + 893 000c 30D0 beq .L62 + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 894 .loc 1 464 3 is_stmt 1 discriminator 2 view .LVU316 + 895 000e 0120 movs r0, #1 + 896 0010 84F83400 strb r0, [r4, #52] + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 897 .loc 1 464 3 discriminator 2 view .LVU317 + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 898 .loc 1 466 3 view .LVU318 + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 899 .loc 1 466 33 is_stmt 0 view .LVU319 + 900 0014 94F83500 ldrb r0, [r4, #53] @ zero_extendqisi2 + 901 0018 C0B2 uxtb r0, r0 + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 902 .loc 1 466 5 view .LVU320 + 903 001a 0128 cmp r0, #1 + 904 001c 04D0 beq .L64 + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 905 .loc 1 495 5 is_stmt 1 view .LVU321 + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 906 .loc 1 495 5 view .LVU322 + ARM GAS /tmp/ccjAMZS2.s page 44 + + + 907 001e 0023 movs r3, #0 + 908 .LVL87: + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 909 .loc 1 495 5 is_stmt 0 view .LVU323 + 910 0020 84F83430 strb r3, [r4, #52] + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 911 .loc 1 495 5 is_stmt 1 view .LVU324 + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 912 .loc 1 498 5 view .LVU325 + 913 .LVL88: + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 914 .loc 1 498 12 is_stmt 0 view .LVU326 + 915 0024 0220 movs r0, #2 + 916 .LVL89: + 917 .L59: + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 918 .loc 1 502 1 view .LVU327 + 919 0026 38BD pop {r3, r4, r5, pc} + 920 .LVL90: + 921 .L64: + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 922 .loc 1 469 5 is_stmt 1 view .LVU328 + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 923 .loc 1 469 17 is_stmt 0 view .LVU329 + 924 0028 0220 movs r0, #2 + 925 002a 84F83500 strb r0, [r4, #53] + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 926 .loc 1 472 5 is_stmt 1 view .LVU330 + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 927 .loc 1 472 21 is_stmt 0 view .LVU331 + 928 002e 0020 movs r0, #0 + 929 0030 6065 str r0, [r4, #84] + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 930 .loc 1 475 5 is_stmt 1 view .LVU332 + 931 0032 2046 mov r0, r4 + 932 0034 FFF7FEFF bl DMA_SetConfig + 933 .LVL91: + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 934 .loc 1 478 5 view .LVU333 + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 935 .loc 1 478 31 is_stmt 0 view .LVU334 + 936 0038 E26D ldr r2, [r4, #92] + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 937 .loc 1 478 24 view .LVU335 + 938 003a 3F23 movs r3, #63 + 939 003c 9340 lsls r3, r3, r2 + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 940 .loc 1 478 16 view .LVU336 + 941 003e AB60 str r3, [r5, #8] + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->FCR |= DMA_IT_FE; + 942 .loc 1 481 5 is_stmt 1 view .LVU337 + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->FCR |= DMA_IT_FE; + 943 .loc 1 481 9 is_stmt 0 view .LVU338 + 944 0040 2268 ldr r2, [r4] + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->FCR |= DMA_IT_FE; + 945 .loc 1 481 19 view .LVU339 + 946 0042 1368 ldr r3, [r2] + ARM GAS /tmp/ccjAMZS2.s page 45 + + + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->FCR |= DMA_IT_FE; + 947 .loc 1 481 25 view .LVU340 + 948 0044 43F01603 orr r3, r3, #22 + 949 0048 1360 str r3, [r2] + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 950 .loc 1 482 5 is_stmt 1 view .LVU341 + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 951 .loc 1 482 9 is_stmt 0 view .LVU342 + 952 004a 2268 ldr r2, [r4] + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 953 .loc 1 482 19 view .LVU343 + 954 004c 5369 ldr r3, [r2, #20] + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 955 .loc 1 482 25 view .LVU344 + 956 004e 43F08003 orr r3, r3, #128 + 957 0052 5361 str r3, [r2, #20] + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 958 .loc 1 484 5 is_stmt 1 view .LVU345 + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 959 .loc 1 484 12 is_stmt 0 view .LVU346 + 960 0054 236C ldr r3, [r4, #64] + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 961 .loc 1 484 7 view .LVU347 + 962 0056 23B1 cbz r3, .L61 + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 963 .loc 1 486 7 is_stmt 1 view .LVU348 + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 964 .loc 1 486 11 is_stmt 0 view .LVU349 + 965 0058 2268 ldr r2, [r4] + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 966 .loc 1 486 21 view .LVU350 + 967 005a 1368 ldr r3, [r2] + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 968 .loc 1 486 27 view .LVU351 + 969 005c 43F00803 orr r3, r3, #8 + 970 0060 1360 str r3, [r2] + 971 .L61: + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 972 .loc 1 490 5 is_stmt 1 view .LVU352 + 973 0062 2268 ldr r2, [r4] + 974 0064 1368 ldr r3, [r2] + 975 0066 43F00103 orr r3, r3, #1 + 976 006a 1360 str r3, [r2] + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 977 .loc 1 455 21 is_stmt 0 view .LVU353 + 978 006c 0020 movs r0, #0 + 979 006e DAE7 b .L59 + 980 .LVL92: + 981 .L62: + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 982 .loc 1 464 3 discriminator 1 view .LVU354 + 983 0070 0220 movs r0, #2 + 984 0072 D8E7 b .L59 + 985 .cfi_endproc + 986 .LFE144: + 988 .section .text.HAL_DMA_Abort,"ax",%progbits + 989 .align 1 + ARM GAS /tmp/ccjAMZS2.s page 46 + + + 990 .global HAL_DMA_Abort + 991 .syntax unified + 992 .thumb + 993 .thumb_func + 995 HAL_DMA_Abort: + 996 .LVL93: + 997 .LFB145: + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* calculate DMA base and stream number */ + 998 .loc 1 517 1 is_stmt 1 view -0 + 999 .cfi_startproc + 1000 @ args = 0, pretend = 0, frame = 0 + 1001 @ frame_needed = 0, uses_anonymous_args = 0 + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** /* calculate DMA base and stream number */ + 1002 .loc 1 517 1 is_stmt 0 view .LVU356 + 1003 0000 70B5 push {r4, r5, r6, lr} + 1004 .LCFI11: + 1005 .cfi_def_cfa_offset 16 + 1006 .cfi_offset 4, -16 + 1007 .cfi_offset 5, -12 + 1008 .cfi_offset 6, -8 + 1009 .cfi_offset 14, -4 + 1010 0002 0446 mov r4, r0 + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1011 .loc 1 519 3 is_stmt 1 view .LVU357 + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1012 .loc 1 519 56 is_stmt 0 view .LVU358 + 1013 0004 866D ldr r6, [r0, #88] + 1014 .LVL94: + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1015 .loc 1 521 3 is_stmt 1 view .LVU359 + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1016 .loc 1 521 24 is_stmt 0 view .LVU360 + 1017 0006 FFF7FEFF bl HAL_GetTick + 1018 .LVL95: + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1019 .loc 1 523 3 is_stmt 1 view .LVU361 + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1020 .loc 1 523 10 is_stmt 0 view .LVU362 + 1021 000a 94F83530 ldrb r3, [r4, #53] @ zero_extendqisi2 + 1022 000e DBB2 uxtb r3, r3 + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1023 .loc 1 523 5 view .LVU363 + 1024 0010 022B cmp r3, #2 + 1025 0012 06D0 beq .L66 + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1026 .loc 1 525 5 is_stmt 1 view .LVU364 + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1027 .loc 1 525 21 is_stmt 0 view .LVU365 + 1028 0014 8023 movs r3, #128 + 1029 0016 6365 str r3, [r4, #84] + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1030 .loc 1 528 5 is_stmt 1 view .LVU366 + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1031 .loc 1 528 5 view .LVU367 + 1032 0018 0023 movs r3, #0 + 1033 001a 84F83430 strb r3, [r4, #52] + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + ARM GAS /tmp/ccjAMZS2.s page 47 + + + 1034 .loc 1 528 5 view .LVU368 + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1035 .loc 1 530 5 view .LVU369 + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1036 .loc 1 530 12 is_stmt 0 view .LVU370 + 1037 001e 0120 movs r0, #1 + 1038 .LVL96: + 1039 .L67: + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1040 .loc 1 576 1 view .LVU371 + 1041 0020 70BD pop {r4, r5, r6, pc} + 1042 .LVL97: + 1043 .L66: + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1044 .loc 1 576 1 view .LVU372 + 1045 0022 0546 mov r5, r0 + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->FCR &= ~(DMA_IT_FE); + 1046 .loc 1 535 5 is_stmt 1 view .LVU373 + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->FCR &= ~(DMA_IT_FE); + 1047 .loc 1 535 9 is_stmt 0 view .LVU374 + 1048 0024 2268 ldr r2, [r4] + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->FCR &= ~(DMA_IT_FE); + 1049 .loc 1 535 19 view .LVU375 + 1050 0026 1368 ldr r3, [r2] + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->FCR &= ~(DMA_IT_FE); + 1051 .loc 1 535 25 view .LVU376 + 1052 0028 23F01603 bic r3, r3, #22 + 1053 002c 1360 str r3, [r2] + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1054 .loc 1 536 5 is_stmt 1 view .LVU377 + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1055 .loc 1 536 9 is_stmt 0 view .LVU378 + 1056 002e 2268 ldr r2, [r4] + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1057 .loc 1 536 19 view .LVU379 + 1058 0030 5369 ldr r3, [r2, #20] + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1059 .loc 1 536 25 view .LVU380 + 1060 0032 23F08003 bic r3, r3, #128 + 1061 0036 5361 str r3, [r2, #20] + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1062 .loc 1 538 5 is_stmt 1 view .LVU381 + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1063 .loc 1 538 13 is_stmt 0 view .LVU382 + 1064 0038 236C ldr r3, [r4, #64] + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1065 .loc 1 538 7 view .LVU383 + 1066 003a E3B1 cbz r3, .L73 + 1067 .L68: + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1068 .loc 1 540 7 is_stmt 1 view .LVU384 + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1069 .loc 1 540 11 is_stmt 0 view .LVU385 + 1070 003c 2268 ldr r2, [r4] + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1071 .loc 1 540 21 view .LVU386 + 1072 003e 1368 ldr r3, [r2] + ARM GAS /tmp/ccjAMZS2.s page 48 + + + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1073 .loc 1 540 27 view .LVU387 + 1074 0040 23F00803 bic r3, r3, #8 + 1075 0044 1360 str r3, [r2] + 1076 .L69: + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1077 .loc 1 544 5 is_stmt 1 view .LVU388 + 1078 0046 2268 ldr r2, [r4] + 1079 0048 1368 ldr r3, [r2] + 1080 004a 23F00103 bic r3, r3, #1 + 1081 004e 1360 str r3, [r2] + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1082 .loc 1 547 5 view .LVU389 + 1083 .LVL98: + 1084 .L70: + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1085 .loc 1 547 46 view .LVU390 + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1086 .loc 1 547 16 is_stmt 0 view .LVU391 + 1087 0050 2368 ldr r3, [r4] + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1088 .loc 1 547 26 view .LVU392 + 1089 0052 1B68 ldr r3, [r3] + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1090 .loc 1 547 46 view .LVU393 + 1091 0054 13F0010F tst r3, #1 + 1092 0058 11D0 beq .L74 + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1093 .loc 1 550 7 is_stmt 1 view .LVU394 + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1094 .loc 1 550 11 is_stmt 0 view .LVU395 + 1095 005a FFF7FEFF bl HAL_GetTick + 1096 .LVL99: + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1097 .loc 1 550 25 discriminator 1 view .LVU396 + 1098 005e 431B subs r3, r0, r5 + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1099 .loc 1 550 9 discriminator 1 view .LVU397 + 1100 0060 052B cmp r3, #5 + 1101 0062 F5D9 bls .L70 + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1102 .loc 1 553 9 is_stmt 1 view .LVU398 + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1103 .loc 1 553 25 is_stmt 0 view .LVU399 + 1104 0064 2023 movs r3, #32 + 1105 0066 6365 str r3, [r4, #84] + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1106 .loc 1 556 9 is_stmt 1 view .LVU400 + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1107 .loc 1 556 21 is_stmt 0 view .LVU401 + 1108 0068 0320 movs r0, #3 + 1109 006a 84F83500 strb r0, [r4, #53] + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1110 .loc 1 559 9 is_stmt 1 view .LVU402 + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1111 .loc 1 559 9 view .LVU403 + 1112 006e 0023 movs r3, #0 + ARM GAS /tmp/ccjAMZS2.s page 49 + + + 1113 0070 84F83430 strb r3, [r4, #52] + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1114 .loc 1 559 9 view .LVU404 + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1115 .loc 1 561 9 view .LVU405 + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1116 .loc 1 561 16 is_stmt 0 view .LVU406 + 1117 0074 D4E7 b .L67 + 1118 .LVL100: + 1119 .L73: + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1120 .loc 1 538 53 discriminator 1 view .LVU407 + 1121 0076 A36C ldr r3, [r4, #72] + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1122 .loc 1 538 45 discriminator 1 view .LVU408 + 1123 0078 002B cmp r3, #0 + 1124 007a DFD1 bne .L68 + 1125 007c E3E7 b .L69 + 1126 .LVL101: + 1127 .L74: + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1128 .loc 1 566 5 is_stmt 1 view .LVU409 + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1129 .loc 1 566 31 is_stmt 0 view .LVU410 + 1130 007e E26D ldr r2, [r4, #92] + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1131 .loc 1 566 24 view .LVU411 + 1132 0080 3F23 movs r3, #63 + 1133 0082 9340 lsls r3, r3, r2 + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1134 .loc 1 566 16 view .LVU412 + 1135 0084 B360 str r3, [r6, #8] + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1136 .loc 1 569 5 is_stmt 1 view .LVU413 + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1137 .loc 1 569 17 is_stmt 0 view .LVU414 + 1138 0086 0123 movs r3, #1 + 1139 0088 84F83530 strb r3, [r4, #53] + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1140 .loc 1 572 5 is_stmt 1 view .LVU415 + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1141 .loc 1 572 5 view .LVU416 + 1142 008c 0020 movs r0, #0 + 1143 008e 84F83400 strb r0, [r4, #52] + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1144 .loc 1 572 5 view .LVU417 + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1145 .loc 1 575 3 view .LVU418 + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1146 .loc 1 575 10 is_stmt 0 view .LVU419 + 1147 0092 C5E7 b .L67 + 1148 .cfi_endproc + 1149 .LFE145: + 1151 .section .text.HAL_DMA_Abort_IT,"ax",%progbits + 1152 .align 1 + 1153 .global HAL_DMA_Abort_IT + 1154 .syntax unified + ARM GAS /tmp/ccjAMZS2.s page 50 + + + 1155 .thumb + 1156 .thumb_func + 1158 HAL_DMA_Abort_IT: + 1159 .LVL102: + 1160 .LFB146: + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** if(hdma->State != HAL_DMA_STATE_BUSY) + 1161 .loc 1 585 1 is_stmt 1 view -0 + 1162 .cfi_startproc + 1163 @ args = 0, pretend = 0, frame = 0 + 1164 @ frame_needed = 0, uses_anonymous_args = 0 + 1165 @ link register save eliminated. + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1166 .loc 1 586 3 view .LVU421 + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1167 .loc 1 586 10 is_stmt 0 view .LVU422 + 1168 0000 90F83530 ldrb r3, [r0, #53] @ zero_extendqisi2 + 1169 0004 DBB2 uxtb r3, r3 + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1170 .loc 1 586 5 view .LVU423 + 1171 0006 022B cmp r3, #2 + 1172 0008 03D0 beq .L76 + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_ERROR; + 1173 .loc 1 588 5 is_stmt 1 view .LVU424 + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_ERROR; + 1174 .loc 1 588 21 is_stmt 0 view .LVU425 + 1175 000a 8023 movs r3, #128 + 1176 000c 4365 str r3, [r0, #84] + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1177 .loc 1 589 5 is_stmt 1 view .LVU426 + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1178 .loc 1 589 12 is_stmt 0 view .LVU427 + 1179 000e 0120 movs r0, #1 + 1180 .LVL103: + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1181 .loc 1 589 12 view .LVU428 + 1182 0010 7047 bx lr + 1183 .LVL104: + 1184 .L76: + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1185 .loc 1 594 5 is_stmt 1 view .LVU429 + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1186 .loc 1 594 17 is_stmt 0 view .LVU430 + 1187 0012 0523 movs r3, #5 + 1188 0014 80F83530 strb r3, [r0, #53] + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1189 .loc 1 597 5 is_stmt 1 view .LVU431 + 1190 0018 0268 ldr r2, [r0] + 1191 001a 1368 ldr r3, [r2] + 1192 001c 23F00103 bic r3, r3, #1 + 1193 0020 1360 str r3, [r2] + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1194 .loc 1 600 3 view .LVU432 + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1195 .loc 1 600 10 is_stmt 0 view .LVU433 + 1196 0022 0020 movs r0, #0 + 1197 .LVL105: + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + ARM GAS /tmp/ccjAMZS2.s page 51 + + + 1198 .loc 1 601 1 view .LVU434 + 1199 0024 7047 bx lr + 1200 .cfi_endproc + 1201 .LFE146: + 1203 .section .text.HAL_DMA_PollForTransfer,"ax",%progbits + 1204 .align 1 + 1205 .global HAL_DMA_PollForTransfer + 1206 .syntax unified + 1207 .thumb + 1208 .thumb_func + 1210 HAL_DMA_PollForTransfer: + 1211 .LVL106: + 1212 .LFB147: + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 1213 .loc 1 615 1 is_stmt 1 view -0 + 1214 .cfi_startproc + 1215 @ args = 0, pretend = 0, frame = 0 + 1216 @ frame_needed = 0, uses_anonymous_args = 0 + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 1217 .loc 1 615 1 is_stmt 0 view .LVU436 + 1218 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, r10, lr} + 1219 .LCFI12: + 1220 .cfi_def_cfa_offset 32 + 1221 .cfi_offset 4, -32 + 1222 .cfi_offset 5, -28 + 1223 .cfi_offset 6, -24 + 1224 .cfi_offset 7, -20 + 1225 .cfi_offset 8, -16 + 1226 .cfi_offset 9, -12 + 1227 .cfi_offset 10, -8 + 1228 .cfi_offset 14, -4 + 1229 0004 0446 mov r4, r0 + 1230 0006 8846 mov r8, r1 + 1231 0008 1646 mov r6, r2 + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t mask_cpltlevel; + 1232 .loc 1 616 3 is_stmt 1 view .LVU437 + 1233 .LVL107: + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tickstart = HAL_GetTick(); + 1234 .loc 1 617 3 view .LVU438 + 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tmpisr; + 1235 .loc 1 618 3 view .LVU439 + 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tmpisr; + 1236 .loc 1 618 24 is_stmt 0 view .LVU440 + 1237 000a FFF7FEFF bl HAL_GetTick + 1238 .LVL108: + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1239 .loc 1 619 3 is_stmt 1 view .LVU441 + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1240 .loc 1 622 3 view .LVU442 + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1241 .loc 1 624 3 view .LVU443 + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1242 .loc 1 624 32 is_stmt 0 view .LVU444 + 1243 000e 94F83530 ldrb r3, [r4, #53] @ zero_extendqisi2 + 1244 0012 DBB2 uxtb r3, r3 + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1245 .loc 1 624 5 view .LVU445 + ARM GAS /tmp/ccjAMZS2.s page 52 + + + 1246 0014 022B cmp r3, #2 + 1247 0016 07D0 beq .L79 + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 1248 .loc 1 627 5 is_stmt 1 view .LVU446 + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 1249 .loc 1 627 21 is_stmt 0 view .LVU447 + 1250 0018 8023 movs r3, #128 + 1251 001a 6365 str r3, [r4, #84] + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_ERROR; + 1252 .loc 1 628 5 is_stmt 1 view .LVU448 + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_ERROR; + 1253 .loc 1 628 5 view .LVU449 + 1254 001c 0023 movs r3, #0 + 1255 001e 84F83430 strb r3, [r4, #52] + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_ERROR; + 1256 .loc 1 628 5 view .LVU450 + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1257 .loc 1 629 5 view .LVU451 + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1258 .loc 1 629 12 is_stmt 0 view .LVU452 + 1259 0022 0120 movs r0, #1 + 1260 .LVL109: + 1261 .L80: + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1262 .loc 1 743 1 view .LVU453 + 1263 0024 BDE8F087 pop {r4, r5, r6, r7, r8, r9, r10, pc} + 1264 .LVL110: + 1265 .L79: + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1266 .loc 1 743 1 view .LVU454 + 1267 0028 8146 mov r9, r0 + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1268 .loc 1 633 3 is_stmt 1 view .LVU455 + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1269 .loc 1 633 12 is_stmt 0 view .LVU456 + 1270 002a 2368 ldr r3, [r4] + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1271 .loc 1 633 22 view .LVU457 + 1272 002c 1B68 ldr r3, [r3] + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1273 .loc 1 633 6 view .LVU458 + 1274 002e 13F4807F tst r3, #256 + 1275 0032 3BD1 bne .L95 + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1276 .loc 1 640 3 is_stmt 1 view .LVU459 + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1277 .loc 1 640 5 is_stmt 0 view .LVU460 + 1278 0034 B8F1000F cmp r8, #0 + 1279 0038 3DD1 bne .L82 + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1280 .loc 1 643 5 is_stmt 1 view .LVU461 + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1281 .loc 1 643 46 is_stmt 0 view .LVU462 + 1282 003a E36D ldr r3, [r4, #92] + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1283 .loc 1 643 20 view .LVU463 + 1284 003c 4FF0200A mov r10, #32 + ARM GAS /tmp/ccjAMZS2.s page 53 + + + 1285 0040 0AFA03FA lsl r10, r10, r3 + 1286 .LVL111: + 1287 .L83: + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** tmpisr = regs->ISR; + 1288 .loc 1 651 3 is_stmt 1 view .LVU464 + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** tmpisr = regs->ISR; + 1289 .loc 1 651 36 is_stmt 0 view .LVU465 + 1290 0044 A76D ldr r7, [r4, #88] + 1291 .LVL112: + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1292 .loc 1 652 3 is_stmt 1 view .LVU466 + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1293 .loc 1 652 10 is_stmt 0 view .LVU467 + 1294 0046 3B68 ldr r3, [r7] + 1295 .LVL113: + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1296 .loc 1 654 3 is_stmt 1 view .LVU468 + 1297 .L84: + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1298 .loc 1 654 46 view .LVU469 + 1299 0048 1AEA030F tst r10, r3 + 1300 004c 43D1 bne .L90 + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1301 .loc 1 654 55 is_stmt 0 discriminator 1 view .LVU470 + 1302 004e 636D ldr r3, [r4, #84] + 1303 .LVL114: + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1304 .loc 1 654 46 discriminator 1 view .LVU471 + 1305 0050 13F0010F tst r3, #1 + 1306 0054 3FD1 bne .L90 + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1307 .loc 1 657 5 is_stmt 1 view .LVU472 + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1308 .loc 1 657 7 is_stmt 0 view .LVU473 + 1309 0056 B6F1FF3F cmp r6, #-1 + 1310 005a 07D0 beq .L85 + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1311 .loc 1 659 7 is_stmt 1 view .LVU474 + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1312 .loc 1 659 9 is_stmt 0 view .LVU475 + 1313 005c 002E cmp r6, #0 + 1314 005e 30D0 beq .L86 + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1315 .loc 1 659 28 discriminator 1 view .LVU476 + 1316 0060 FFF7FEFF bl HAL_GetTick + 1317 .LVL115: + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1318 .loc 1 659 42 discriminator 1 view .LVU477 + 1319 0064 A0EB0900 sub r0, r0, r9 + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1320 .loc 1 659 24 discriminator 1 view .LVU478 + 1321 0068 B042 cmp r0, r6 + 1322 006a 2AD8 bhi .L86 + 1323 .L85: + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1324 .loc 1 675 5 is_stmt 1 view .LVU479 + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + ARM GAS /tmp/ccjAMZS2.s page 54 + + + 1325 .loc 1 675 12 is_stmt 0 view .LVU480 + 1326 006c 3B68 ldr r3, [r7] + 1327 .LVL116: + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1328 .loc 1 677 5 is_stmt 1 view .LVU481 + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1329 .loc 1 677 43 is_stmt 0 view .LVU482 + 1330 006e E16D ldr r1, [r4, #92] + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1331 .loc 1 677 36 view .LVU483 + 1332 0070 0822 movs r2, #8 + 1333 0072 8A40 lsls r2, r2, r1 + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1334 .loc 1 677 7 view .LVU484 + 1335 0074 1A42 tst r2, r3 + 1336 0076 04D0 beq .L87 + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1337 .loc 1 680 7 is_stmt 1 view .LVU485 + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1338 .loc 1 680 11 is_stmt 0 view .LVU486 + 1339 0078 616D ldr r1, [r4, #84] + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1340 .loc 1 680 23 view .LVU487 + 1341 007a 41F00101 orr r1, r1, #1 + 1342 007e 6165 str r1, [r4, #84] + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1343 .loc 1 683 7 is_stmt 1 view .LVU488 + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1344 .loc 1 683 18 is_stmt 0 view .LVU489 + 1345 0080 BA60 str r2, [r7, #8] + 1346 .L87: + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1347 .loc 1 686 5 is_stmt 1 view .LVU490 + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1348 .loc 1 686 43 is_stmt 0 view .LVU491 + 1349 0082 E16D ldr r1, [r4, #92] + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1350 .loc 1 686 36 view .LVU492 + 1351 0084 0122 movs r2, #1 + 1352 0086 8A40 lsls r2, r2, r1 + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1353 .loc 1 686 7 view .LVU493 + 1354 0088 1A42 tst r2, r3 + 1355 008a 04D0 beq .L88 + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1356 .loc 1 689 7 is_stmt 1 view .LVU494 + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1357 .loc 1 689 11 is_stmt 0 view .LVU495 + 1358 008c 616D ldr r1, [r4, #84] + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1359 .loc 1 689 23 view .LVU496 + 1360 008e 41F00201 orr r1, r1, #2 + 1361 0092 6165 str r1, [r4, #84] + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1362 .loc 1 692 7 is_stmt 1 view .LVU497 + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1363 .loc 1 692 18 is_stmt 0 view .LVU498 + ARM GAS /tmp/ccjAMZS2.s page 55 + + + 1364 0094 BA60 str r2, [r7, #8] + 1365 .L88: + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1366 .loc 1 695 5 is_stmt 1 view .LVU499 + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1367 .loc 1 695 44 is_stmt 0 view .LVU500 + 1368 0096 E26D ldr r2, [r4, #92] + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1369 .loc 1 695 37 view .LVU501 + 1370 0098 0425 movs r5, #4 + 1371 009a 9540 lsls r5, r5, r2 + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1372 .loc 1 695 7 view .LVU502 + 1373 009c 1D42 tst r5, r3 + 1374 009e D3D0 beq .L84 + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1375 .loc 1 698 7 is_stmt 1 view .LVU503 + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1376 .loc 1 698 11 is_stmt 0 view .LVU504 + 1377 00a0 626D ldr r2, [r4, #84] + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1378 .loc 1 698 23 view .LVU505 + 1379 00a2 42F00402 orr r2, r2, #4 + 1380 00a6 6265 str r2, [r4, #84] + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1381 .loc 1 701 7 is_stmt 1 view .LVU506 + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1382 .loc 1 701 18 is_stmt 0 view .LVU507 + 1383 00a8 BD60 str r5, [r7, #8] + 1384 00aa CDE7 b .L84 + 1385 .LVL117: + 1386 .L95: + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_ERROR; + 1387 .loc 1 635 5 is_stmt 1 view .LVU508 + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return HAL_ERROR; + 1388 .loc 1 635 21 is_stmt 0 view .LVU509 + 1389 00ac 4FF48073 mov r3, #256 + 1390 00b0 6365 str r3, [r4, #84] + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1391 .loc 1 636 5 is_stmt 1 view .LVU510 + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1392 .loc 1 636 12 is_stmt 0 view .LVU511 + 1393 00b2 0120 movs r0, #1 + 1394 .LVL118: + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1395 .loc 1 636 12 view .LVU512 + 1396 00b4 B6E7 b .L80 + 1397 .LVL119: + 1398 .L82: + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1399 .loc 1 648 5 is_stmt 1 view .LVU513 + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1400 .loc 1 648 46 is_stmt 0 view .LVU514 + 1401 00b6 E36D ldr r3, [r4, #92] + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1402 .loc 1 648 20 view .LVU515 + 1403 00b8 4FF0100A mov r10, #16 + ARM GAS /tmp/ccjAMZS2.s page 56 + + + 1404 00bc 0AFA03FA lsl r10, r10, r3 + 1405 .LVL120: + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1406 .loc 1 648 20 view .LVU516 + 1407 00c0 C0E7 b .L83 + 1408 .LVL121: + 1409 .L86: + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1410 .loc 1 662 9 is_stmt 1 view .LVU517 + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1411 .loc 1 662 25 is_stmt 0 view .LVU518 + 1412 00c2 2023 movs r3, #32 + 1413 00c4 6365 str r3, [r4, #84] + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1414 .loc 1 665 9 is_stmt 1 view .LVU519 + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1415 .loc 1 665 21 is_stmt 0 view .LVU520 + 1416 00c6 0123 movs r3, #1 + 1417 00c8 84F83530 strb r3, [r4, #53] + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1418 .loc 1 668 9 is_stmt 1 view .LVU521 + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1419 .loc 1 668 9 view .LVU522 + 1420 00cc 0023 movs r3, #0 + 1421 00ce 84F83430 strb r3, [r4, #52] + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1422 .loc 1 668 9 view .LVU523 + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1423 .loc 1 670 9 view .LVU524 + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1424 .loc 1 670 16 is_stmt 0 view .LVU525 + 1425 00d2 0320 movs r0, #3 + 1426 00d4 A6E7 b .L80 + 1427 .L90: + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1428 .loc 1 705 3 is_stmt 1 view .LVU526 + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1429 .loc 1 705 10 is_stmt 0 view .LVU527 + 1430 00d6 636D ldr r3, [r4, #84] + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1431 .loc 1 705 5 view .LVU528 + 1432 00d8 1BB1 cbz r3, .L92 + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1433 .loc 1 707 5 is_stmt 1 view .LVU529 + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1434 .loc 1 707 13 is_stmt 0 view .LVU530 + 1435 00da 636D ldr r3, [r4, #84] + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1436 .loc 1 707 7 view .LVU531 + 1437 00dc 13F0010F tst r3, #1 + 1438 00e0 0ED1 bne .L96 + 1439 .L92: + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1440 .loc 1 725 3 is_stmt 1 view .LVU532 + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1441 .loc 1 725 5 is_stmt 0 view .LVU533 + 1442 00e2 B8F1000F cmp r8, #0 + ARM GAS /tmp/ccjAMZS2.s page 57 + + + 1443 00e6 19D1 bne .L93 + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1444 .loc 1 728 5 is_stmt 1 view .LVU534 + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1445 .loc 1 728 63 is_stmt 0 view .LVU535 + 1446 00e8 E26D ldr r2, [r4, #92] + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1447 .loc 1 728 56 view .LVU536 + 1448 00ea 3023 movs r3, #48 + 1449 00ec 9340 lsls r3, r3, r2 + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1450 .loc 1 728 16 view .LVU537 + 1451 00ee BB60 str r3, [r7, #8] + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1452 .loc 1 730 5 is_stmt 1 view .LVU538 + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1453 .loc 1 730 17 is_stmt 0 view .LVU539 + 1454 00f0 0123 movs r3, #1 + 1455 00f2 84F83530 strb r3, [r4, #53] + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1456 .loc 1 733 5 is_stmt 1 view .LVU540 + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1457 .loc 1 733 5 view .LVU541 + 1458 00f6 0023 movs r3, #0 + 1459 00f8 84F83430 strb r3, [r4, #52] + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1460 .loc 1 733 5 view .LVU542 + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1461 .loc 1 742 10 is_stmt 0 view .LVU543 + 1462 00fc 4046 mov r0, r8 + 1463 00fe 91E7 b .L80 + 1464 .L96: + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1465 .loc 1 709 7 is_stmt 1 view .LVU544 + 1466 0100 2046 mov r0, r4 + 1467 0102 FFF7FEFF bl HAL_DMA_Abort + 1468 .LVL122: + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1469 .loc 1 712 7 view .LVU545 + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1470 .loc 1 712 65 is_stmt 0 view .LVU546 + 1471 0106 E26D ldr r2, [r4, #92] + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1472 .loc 1 712 58 view .LVU547 + 1473 0108 3023 movs r3, #48 + 1474 010a 9340 lsls r3, r3, r2 + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1475 .loc 1 712 18 view .LVU548 + 1476 010c BB60 str r3, [r7, #8] + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1477 .loc 1 715 7 is_stmt 1 view .LVU549 + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1478 .loc 1 715 18 is_stmt 0 view .LVU550 + 1479 010e 0120 movs r0, #1 + 1480 0110 84F83500 strb r0, [r4, #53] + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1481 .loc 1 718 7 is_stmt 1 view .LVU551 + ARM GAS /tmp/ccjAMZS2.s page 58 + + + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1482 .loc 1 718 7 view .LVU552 + 1483 0114 0023 movs r3, #0 + 1484 0116 84F83430 strb r3, [r4, #52] + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1485 .loc 1 718 7 view .LVU553 + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1486 .loc 1 720 7 view .LVU554 + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1487 .loc 1 720 14 is_stmt 0 view .LVU555 + 1488 011a 83E7 b .L80 + 1489 .L93: + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1490 .loc 1 739 5 is_stmt 1 view .LVU556 + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1491 .loc 1 739 44 is_stmt 0 view .LVU557 + 1492 011c E26D ldr r2, [r4, #92] + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1493 .loc 1 739 37 view .LVU558 + 1494 011e 1023 movs r3, #16 + 1495 0120 9340 lsls r3, r3, r2 + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1496 .loc 1 739 16 view .LVU559 + 1497 0122 BB60 str r3, [r7, #8] + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1498 .loc 1 742 10 view .LVU560 + 1499 0124 0020 movs r0, #0 + 1500 0126 7DE7 b .L80 + 1501 .cfi_endproc + 1502 .LFE147: + 1504 .section .text.HAL_DMA_IRQHandler,"ax",%progbits + 1505 .align 1 + 1506 .global HAL_DMA_IRQHandler + 1507 .syntax unified + 1508 .thumb + 1509 .thumb_func + 1511 HAL_DMA_IRQHandler: + 1512 .LVL123: + 1513 .LFB148: + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tmpisr; + 1514 .loc 1 752 1 is_stmt 1 view -0 + 1515 .cfi_startproc + 1516 @ args = 0, pretend = 0, frame = 8 + 1517 @ frame_needed = 0, uses_anonymous_args = 0 + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t tmpisr; + 1518 .loc 1 752 1 is_stmt 0 view .LVU562 + 1519 0000 F0B5 push {r4, r5, r6, r7, lr} + 1520 .LCFI13: + 1521 .cfi_def_cfa_offset 20 + 1522 .cfi_offset 4, -20 + 1523 .cfi_offset 5, -16 + 1524 .cfi_offset 6, -12 + 1525 .cfi_offset 7, -8 + 1526 .cfi_offset 14, -4 + 1527 0002 83B0 sub sp, sp, #12 + 1528 .LCFI14: + 1529 .cfi_def_cfa_offset 32 + ARM GAS /tmp/ccjAMZS2.s page 59 + + + 1530 0004 0446 mov r4, r0 + 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** __IO uint32_t count = 0; + 1531 .loc 1 753 3 is_stmt 1 view .LVU563 + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t timeout = SystemCoreClock / 9600; + 1532 .loc 1 754 3 view .LVU564 + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** uint32_t timeout = SystemCoreClock / 9600; + 1533 .loc 1 754 17 is_stmt 0 view .LVU565 + 1534 0006 0023 movs r3, #0 + 1535 0008 0193 str r3, [sp, #4] + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1536 .loc 1 755 3 is_stmt 1 view .LVU566 + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1537 .loc 1 755 38 is_stmt 0 view .LVU567 + 1538 000a 724B ldr r3, .L120 + 1539 000c 1D68 ldr r5, [r3] + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1540 .loc 1 755 12 view .LVU568 + 1541 000e 724B ldr r3, .L120+4 + 1542 0010 A3FB0535 umull r3, r5, r3, r5 + 1543 0014 AD0A lsrs r5, r5, #10 + 1544 .LVL124: + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1545 .loc 1 758 3 is_stmt 1 view .LVU569 + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1546 .loc 1 758 56 is_stmt 0 view .LVU570 + 1547 0016 876D ldr r7, [r0, #88] + 1548 .LVL125: + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1549 .loc 1 760 3 is_stmt 1 view .LVU571 + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1550 .loc 1 760 10 is_stmt 0 view .LVU572 + 1551 0018 3E68 ldr r6, [r7] + 1552 .LVL126: + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1553 .loc 1 763 3 is_stmt 1 view .LVU573 + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1554 .loc 1 763 42 is_stmt 0 view .LVU574 + 1555 001a C26D ldr r2, [r0, #92] + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1556 .loc 1 763 35 view .LVU575 + 1557 001c 0823 movs r3, #8 + 1558 001e 9340 lsls r3, r3, r2 + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1559 .loc 1 763 6 view .LVU576 + 1560 0020 3342 tst r3, r6 + 1561 0022 10D0 beq .L98 + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1562 .loc 1 765 5 is_stmt 1 view .LVU577 + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1563 .loc 1 765 8 is_stmt 0 view .LVU578 + 1564 0024 0368 ldr r3, [r0] + 1565 0026 1A68 ldr r2, [r3] + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1566 .loc 1 765 7 view .LVU579 + 1567 0028 12F0040F tst r2, #4 + 1568 002c 0BD0 beq .L98 + 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + ARM GAS /tmp/ccjAMZS2.s page 60 + + + 1569 .loc 1 768 7 is_stmt 1 view .LVU580 + 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1570 .loc 1 768 21 is_stmt 0 view .LVU581 + 1571 002e 1A68 ldr r2, [r3] + 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1572 .loc 1 768 27 view .LVU582 + 1573 0030 22F00402 bic r2, r2, #4 + 1574 0034 1A60 str r2, [r3] + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1575 .loc 1 771 7 is_stmt 1 view .LVU583 + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1576 .loc 1 771 44 is_stmt 0 view .LVU584 + 1577 0036 C26D ldr r2, [r0, #92] + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1578 .loc 1 771 37 view .LVU585 + 1579 0038 0823 movs r3, #8 + 1580 003a 9340 lsls r3, r3, r2 + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1581 .loc 1 771 18 view .LVU586 + 1582 003c BB60 str r3, [r7, #8] + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1583 .loc 1 774 7 is_stmt 1 view .LVU587 + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1584 .loc 1 774 11 is_stmt 0 view .LVU588 + 1585 003e 436D ldr r3, [r0, #84] + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1586 .loc 1 774 23 view .LVU589 + 1587 0040 43F00103 orr r3, r3, #1 + 1588 0044 4365 str r3, [r0, #84] + 1589 .L98: + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1590 .loc 1 778 3 is_stmt 1 view .LVU590 + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1591 .loc 1 778 42 is_stmt 0 view .LVU591 + 1592 0046 E26D ldr r2, [r4, #92] + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1593 .loc 1 778 35 view .LVU592 + 1594 0048 0123 movs r3, #1 + 1595 004a 9340 lsls r3, r3, r2 + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1596 .loc 1 778 6 view .LVU593 + 1597 004c 3342 tst r3, r6 + 1598 004e 09D0 beq .L99 + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1599 .loc 1 780 5 is_stmt 1 view .LVU594 + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1600 .loc 1 780 8 is_stmt 0 view .LVU595 + 1601 0050 2268 ldr r2, [r4] + 1602 0052 5269 ldr r2, [r2, #20] + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1603 .loc 1 780 7 view .LVU596 + 1604 0054 12F0800F tst r2, #128 + 1605 0058 04D0 beq .L99 + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1606 .loc 1 783 7 is_stmt 1 view .LVU597 + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1607 .loc 1 783 18 is_stmt 0 view .LVU598 + ARM GAS /tmp/ccjAMZS2.s page 61 + + + 1608 005a BB60 str r3, [r7, #8] + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1609 .loc 1 786 7 is_stmt 1 view .LVU599 + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1610 .loc 1 786 11 is_stmt 0 view .LVU600 + 1611 005c 636D ldr r3, [r4, #84] + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1612 .loc 1 786 23 view .LVU601 + 1613 005e 43F00203 orr r3, r3, #2 + 1614 0062 6365 str r3, [r4, #84] + 1615 .L99: + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1616 .loc 1 790 3 is_stmt 1 view .LVU602 + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1617 .loc 1 790 43 is_stmt 0 view .LVU603 + 1618 0064 E26D ldr r2, [r4, #92] + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1619 .loc 1 790 36 view .LVU604 + 1620 0066 0423 movs r3, #4 + 1621 0068 9340 lsls r3, r3, r2 + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1622 .loc 1 790 6 view .LVU605 + 1623 006a 3342 tst r3, r6 + 1624 006c 09D0 beq .L100 + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1625 .loc 1 792 5 is_stmt 1 view .LVU606 + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1626 .loc 1 792 8 is_stmt 0 view .LVU607 + 1627 006e 2268 ldr r2, [r4] + 1628 0070 1268 ldr r2, [r2] + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1629 .loc 1 792 7 view .LVU608 + 1630 0072 12F0020F tst r2, #2 + 1631 0076 04D0 beq .L100 + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1632 .loc 1 795 7 is_stmt 1 view .LVU609 + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1633 .loc 1 795 18 is_stmt 0 view .LVU610 + 1634 0078 BB60 str r3, [r7, #8] + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1635 .loc 1 798 7 is_stmt 1 view .LVU611 + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1636 .loc 1 798 11 is_stmt 0 view .LVU612 + 1637 007a 636D ldr r3, [r4, #84] + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1638 .loc 1 798 23 view .LVU613 + 1639 007c 43F00403 orr r3, r3, #4 + 1640 0080 6365 str r3, [r4, #84] + 1641 .L100: + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1642 .loc 1 802 3 is_stmt 1 view .LVU614 + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1643 .loc 1 802 42 is_stmt 0 view .LVU615 + 1644 0082 E26D ldr r2, [r4, #92] + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1645 .loc 1 802 35 view .LVU616 + 1646 0084 1023 movs r3, #16 + ARM GAS /tmp/ccjAMZS2.s page 62 + + + 1647 0086 9340 lsls r3, r3, r2 + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1648 .loc 1 802 6 view .LVU617 + 1649 0088 3342 tst r3, r6 + 1650 008a 24D0 beq .L101 + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1651 .loc 1 804 5 is_stmt 1 view .LVU618 + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1652 .loc 1 804 8 is_stmt 0 view .LVU619 + 1653 008c 2268 ldr r2, [r4] + 1654 008e 1268 ldr r2, [r2] + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1655 .loc 1 804 7 view .LVU620 + 1656 0090 12F0080F tst r2, #8 + 1657 0094 1FD0 beq .L101 + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1658 .loc 1 807 7 is_stmt 1 view .LVU621 + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1659 .loc 1 807 18 is_stmt 0 view .LVU622 + 1660 0096 BB60 str r3, [r7, #8] + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1661 .loc 1 810 7 is_stmt 1 view .LVU623 + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1662 .loc 1 810 16 is_stmt 0 view .LVU624 + 1663 0098 2368 ldr r3, [r4] + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1664 .loc 1 810 26 view .LVU625 + 1665 009a 1A68 ldr r2, [r3] + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1666 .loc 1 810 9 view .LVU626 + 1667 009c 12F4802F tst r2, #262144 + 1668 00a0 0DD0 beq .L102 + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1669 .loc 1 813 9 is_stmt 1 view .LVU627 + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1670 .loc 1 813 27 is_stmt 0 view .LVU628 + 1671 00a2 1B68 ldr r3, [r3] + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1672 .loc 1 813 11 view .LVU629 + 1673 00a4 13F4002F tst r3, #524288 + 1674 00a8 04D1 bne .L103 + 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1675 .loc 1 815 11 is_stmt 1 view .LVU630 + 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1676 .loc 1 815 18 is_stmt 0 view .LVU631 + 1677 00aa 236C ldr r3, [r4, #64] + 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1678 .loc 1 815 13 view .LVU632 + 1679 00ac 9BB1 cbz r3, .L101 + 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1680 .loc 1 818 13 is_stmt 1 view .LVU633 + 1681 00ae 2046 mov r0, r4 + 1682 .LVL127: + 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1683 .loc 1 818 13 is_stmt 0 view .LVU634 + 1684 00b0 9847 blx r3 + 1685 .LVL128: + ARM GAS /tmp/ccjAMZS2.s page 63 + + + 1686 00b2 10E0 b .L101 + 1687 .LVL129: + 1688 .L103: + 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1689 .loc 1 824 11 is_stmt 1 view .LVU635 + 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1690 .loc 1 824 18 is_stmt 0 view .LVU636 + 1691 00b4 A36C ldr r3, [r4, #72] + 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1692 .loc 1 824 13 view .LVU637 + 1693 00b6 73B1 cbz r3, .L101 + 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1694 .loc 1 827 13 is_stmt 1 view .LVU638 + 1695 00b8 2046 mov r0, r4 + 1696 .LVL130: + 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1697 .loc 1 827 13 is_stmt 0 view .LVU639 + 1698 00ba 9847 blx r3 + 1699 .LVL131: + 1700 00bc 0BE0 b .L101 + 1701 .LVL132: + 1702 .L102: + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1703 .loc 1 834 9 is_stmt 1 view .LVU640 + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1704 .loc 1 834 27 is_stmt 0 view .LVU641 + 1705 00be 1A68 ldr r2, [r3] + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1706 .loc 1 834 11 view .LVU642 + 1707 00c0 12F4807F tst r2, #256 + 1708 00c4 03D1 bne .L104 + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1709 .loc 1 837 11 is_stmt 1 view .LVU643 + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1710 .loc 1 837 25 is_stmt 0 view .LVU644 + 1711 00c6 1A68 ldr r2, [r3] + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1712 .loc 1 837 31 view .LVU645 + 1713 00c8 22F00802 bic r2, r2, #8 + 1714 00cc 1A60 str r2, [r3] + 1715 .L104: + 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1716 .loc 1 840 9 is_stmt 1 view .LVU646 + 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1717 .loc 1 840 16 is_stmt 0 view .LVU647 + 1718 00ce 236C ldr r3, [r4, #64] + 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1719 .loc 1 840 11 view .LVU648 + 1720 00d0 0BB1 cbz r3, .L101 + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1721 .loc 1 843 11 is_stmt 1 view .LVU649 + 1722 00d2 2046 mov r0, r4 + 1723 .LVL133: + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1724 .loc 1 843 11 is_stmt 0 view .LVU650 + 1725 00d4 9847 blx r3 + 1726 .LVL134: + ARM GAS /tmp/ccjAMZS2.s page 64 + + + 1727 .L101: + 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1728 .loc 1 849 3 is_stmt 1 view .LVU651 + 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1729 .loc 1 849 42 is_stmt 0 view .LVU652 + 1730 00d6 E26D ldr r2, [r4, #92] + 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1731 .loc 1 849 35 view .LVU653 + 1732 00d8 2023 movs r3, #32 + 1733 00da 9340 lsls r3, r3, r2 + 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1734 .loc 1 849 6 view .LVU654 + 1735 00dc 3342 tst r3, r6 + 1736 00de 55D0 beq .L105 + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1737 .loc 1 851 5 is_stmt 1 view .LVU655 + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1738 .loc 1 851 8 is_stmt 0 view .LVU656 + 1739 00e0 2268 ldr r2, [r4] + 1740 00e2 1268 ldr r2, [r2] + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1741 .loc 1 851 7 view .LVU657 + 1742 00e4 12F0100F tst r2, #16 + 1743 00e8 50D0 beq .L105 + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1744 .loc 1 854 7 is_stmt 1 view .LVU658 + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1745 .loc 1 854 18 is_stmt 0 view .LVU659 + 1746 00ea BB60 str r3, [r7, #8] + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1747 .loc 1 856 7 is_stmt 1 view .LVU660 + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1748 .loc 1 856 37 is_stmt 0 view .LVU661 + 1749 00ec 94F83530 ldrb r3, [r4, #53] @ zero_extendqisi2 + 1750 00f0 DBB2 uxtb r3, r3 + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1751 .loc 1 856 9 view .LVU662 + 1752 00f2 052B cmp r3, #5 + 1753 00f4 0ED0 beq .L118 + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1754 .loc 1 883 7 is_stmt 1 view .LVU663 + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1755 .loc 1 883 16 is_stmt 0 view .LVU664 + 1756 00f6 2368 ldr r3, [r4] + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1757 .loc 1 883 26 view .LVU665 + 1758 00f8 1A68 ldr r2, [r3] + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1759 .loc 1 883 9 view .LVU666 + 1760 00fa 12F4802F tst r2, #262144 + 1761 00fe 33D0 beq .L111 + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1762 .loc 1 886 9 is_stmt 1 view .LVU667 + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1763 .loc 1 886 27 is_stmt 0 view .LVU668 + 1764 0100 1B68 ldr r3, [r3] + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + ARM GAS /tmp/ccjAMZS2.s page 65 + + + 1765 .loc 1 886 11 view .LVU669 + 1766 0102 13F4002F tst r3, #524288 + 1767 0106 2AD1 bne .L112 + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1768 .loc 1 888 11 is_stmt 1 view .LVU670 + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1769 .loc 1 888 18 is_stmt 0 view .LVU671 + 1770 0108 636C ldr r3, [r4, #68] + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1771 .loc 1 888 13 view .LVU672 + 1772 010a 002B cmp r3, #0 + 1773 010c 3ED0 beq .L105 + 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1774 .loc 1 891 13 is_stmt 1 view .LVU673 + 1775 010e 2046 mov r0, r4 + 1776 0110 9847 blx r3 + 1777 .LVL135: + 1778 0112 3BE0 b .L105 + 1779 .L118: + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->FCR &= ~(DMA_IT_FE); + 1780 .loc 1 859 9 view .LVU674 + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->FCR &= ~(DMA_IT_FE); + 1781 .loc 1 859 13 is_stmt 0 view .LVU675 + 1782 0114 2268 ldr r2, [r4] + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->FCR &= ~(DMA_IT_FE); + 1783 .loc 1 859 23 view .LVU676 + 1784 0116 1368 ldr r3, [r2] + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->Instance->FCR &= ~(DMA_IT_FE); + 1785 .loc 1 859 29 view .LVU677 + 1786 0118 23F01603 bic r3, r3, #22 + 1787 011c 1360 str r3, [r2] + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1788 .loc 1 860 9 is_stmt 1 view .LVU678 + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1789 .loc 1 860 13 is_stmt 0 view .LVU679 + 1790 011e 2268 ldr r2, [r4] + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1791 .loc 1 860 23 view .LVU680 + 1792 0120 5369 ldr r3, [r2, #20] + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1793 .loc 1 860 29 view .LVU681 + 1794 0122 23F08003 bic r3, r3, #128 + 1795 0126 5361 str r3, [r2, #20] + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1796 .loc 1 862 9 is_stmt 1 view .LVU682 + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1797 .loc 1 862 17 is_stmt 0 view .LVU683 + 1798 0128 236C ldr r3, [r4, #64] + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1799 .loc 1 862 11 view .LVU684 + 1800 012a A3B1 cbz r3, .L119 + 1801 .L107: + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1802 .loc 1 864 11 is_stmt 1 view .LVU685 + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1803 .loc 1 864 15 is_stmt 0 view .LVU686 + 1804 012c 2268 ldr r2, [r4] + ARM GAS /tmp/ccjAMZS2.s page 66 + + + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1805 .loc 1 864 25 view .LVU687 + 1806 012e 1368 ldr r3, [r2] + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1807 .loc 1 864 31 view .LVU688 + 1808 0130 23F00803 bic r3, r3, #8 + 1809 0134 1360 str r3, [r2] + 1810 .L108: + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1811 .loc 1 868 9 is_stmt 1 view .LVU689 + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1812 .loc 1 868 35 is_stmt 0 view .LVU690 + 1813 0136 E26D ldr r2, [r4, #92] + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1814 .loc 1 868 28 view .LVU691 + 1815 0138 3F23 movs r3, #63 + 1816 013a 9340 lsls r3, r3, r2 + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1817 .loc 1 868 20 view .LVU692 + 1818 013c BB60 str r3, [r7, #8] + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1819 .loc 1 871 9 is_stmt 1 view .LVU693 + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1820 .loc 1 871 21 is_stmt 0 view .LVU694 + 1821 013e 0123 movs r3, #1 + 1822 0140 84F83530 strb r3, [r4, #53] + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1823 .loc 1 874 9 is_stmt 1 view .LVU695 + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1824 .loc 1 874 9 view .LVU696 + 1825 0144 0023 movs r3, #0 + 1826 0146 84F83430 strb r3, [r4, #52] + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1827 .loc 1 874 9 view .LVU697 + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1828 .loc 1 876 9 view .LVU698 + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1829 .loc 1 876 16 is_stmt 0 view .LVU699 + 1830 014a 236D ldr r3, [r4, #80] + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1831 .loc 1 876 11 view .LVU700 + 1832 014c 002B cmp r3, #0 + 1833 014e 3FD0 beq .L97 + 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1834 .loc 1 878 11 is_stmt 1 view .LVU701 + 1835 0150 2046 mov r0, r4 + 1836 0152 9847 blx r3 + 1837 .LVL136: + 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1838 .loc 1 880 9 view .LVU702 + 1839 0154 3CE0 b .L97 + 1840 .L119: + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1841 .loc 1 862 57 is_stmt 0 discriminator 1 view .LVU703 + 1842 0156 A36C ldr r3, [r4, #72] + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1843 .loc 1 862 49 discriminator 1 view .LVU704 + ARM GAS /tmp/ccjAMZS2.s page 67 + + + 1844 0158 002B cmp r3, #0 + 1845 015a E7D1 bne .L107 + 1846 015c EBE7 b .L108 + 1847 .L112: + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1848 .loc 1 897 11 is_stmt 1 view .LVU705 + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1849 .loc 1 897 18 is_stmt 0 view .LVU706 + 1850 015e E36B ldr r3, [r4, #60] + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1851 .loc 1 897 13 view .LVU707 + 1852 0160 A3B1 cbz r3, .L105 + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1853 .loc 1 900 13 is_stmt 1 view .LVU708 + 1854 0162 2046 mov r0, r4 + 1855 0164 9847 blx r3 + 1856 .LVL137: + 1857 0166 11E0 b .L105 + 1858 .L111: + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1859 .loc 1 907 9 view .LVU709 + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1860 .loc 1 907 27 is_stmt 0 view .LVU710 + 1861 0168 1A68 ldr r2, [r3] + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1862 .loc 1 907 11 view .LVU711 + 1863 016a 12F4807F tst r2, #256 + 1864 016e 09D1 bne .L113 + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1865 .loc 1 910 11 is_stmt 1 view .LVU712 + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1866 .loc 1 910 25 is_stmt 0 view .LVU713 + 1867 0170 1A68 ldr r2, [r3] + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1868 .loc 1 910 31 view .LVU714 + 1869 0172 22F01002 bic r2, r2, #16 + 1870 0176 1A60 str r2, [r3] + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1871 .loc 1 913 11 is_stmt 1 view .LVU715 + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1872 .loc 1 913 23 is_stmt 0 view .LVU716 + 1873 0178 0123 movs r3, #1 + 1874 017a 84F83530 strb r3, [r4, #53] + 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1875 .loc 1 916 11 is_stmt 1 view .LVU717 + 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1876 .loc 1 916 11 view .LVU718 + 1877 017e 0023 movs r3, #0 + 1878 0180 84F83430 strb r3, [r4, #52] + 1879 .L113: + 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1880 .loc 1 916 11 discriminator 1 view .LVU719 + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1881 .loc 1 920 9 view .LVU720 + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1882 .loc 1 920 16 is_stmt 0 view .LVU721 + 1883 0184 E36B ldr r3, [r4, #60] + ARM GAS /tmp/ccjAMZS2.s page 68 + + + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1884 .loc 1 920 11 view .LVU722 + 1885 0186 0BB1 cbz r3, .L105 + 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1886 .loc 1 923 11 is_stmt 1 view .LVU723 + 1887 0188 2046 mov r0, r4 + 1888 018a 9847 blx r3 + 1889 .LVL138: + 1890 .L105: + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1891 .loc 1 930 3 view .LVU724 + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1892 .loc 1 930 10 is_stmt 0 view .LVU725 + 1893 018c 636D ldr r3, [r4, #84] + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1894 .loc 1 930 5 view .LVU726 + 1895 018e FBB1 cbz r3, .L97 + 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1896 .loc 1 932 5 is_stmt 1 view .LVU727 + 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1897 .loc 1 932 13 is_stmt 0 view .LVU728 + 1898 0190 636D ldr r3, [r4, #84] + 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1899 .loc 1 932 7 view .LVU729 + 1900 0192 13F0010F tst r3, #1 + 1901 0196 17D0 beq .L114 + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1902 .loc 1 934 7 is_stmt 1 view .LVU730 + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1903 .loc 1 934 19 is_stmt 0 view .LVU731 + 1904 0198 0523 movs r3, #5 + 1905 019a 84F83530 strb r3, [r4, #53] + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1906 .loc 1 937 7 is_stmt 1 view .LVU732 + 1907 019e 2268 ldr r2, [r4] + 1908 01a0 1368 ldr r3, [r2] + 1909 01a2 23F00103 bic r3, r3, #1 + 1910 01a6 1360 str r3, [r2] + 1911 .L116: + 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1912 .loc 1 939 7 view .LVU733 + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1913 .loc 1 941 9 view .LVU734 + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1914 .loc 1 941 13 is_stmt 0 view .LVU735 + 1915 01a8 019B ldr r3, [sp, #4] + 1916 01aa 0133 adds r3, r3, #1 + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1917 .loc 1 941 12 view .LVU736 + 1918 01ac 0193 str r3, [sp, #4] + 1919 01ae AB42 cmp r3, r5 + 1920 01b0 04D8 bhi .L115 + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1921 .loc 1 946 48 is_stmt 1 view .LVU737 + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1922 .loc 1 946 18 is_stmt 0 view .LVU738 + 1923 01b2 2368 ldr r3, [r4] + ARM GAS /tmp/ccjAMZS2.s page 69 + + + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1924 .loc 1 946 28 view .LVU739 + 1925 01b4 1B68 ldr r3, [r3] + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1926 .loc 1 946 48 view .LVU740 + 1927 01b6 13F0010F tst r3, #1 + 1928 01ba F5D1 bne .L116 + 1929 .L115: + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1930 .loc 1 949 7 is_stmt 1 view .LVU741 + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1931 .loc 1 949 19 is_stmt 0 view .LVU742 + 1932 01bc 0123 movs r3, #1 + 1933 01be 84F83530 strb r3, [r4, #53] + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1934 .loc 1 952 7 is_stmt 1 view .LVU743 + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1935 .loc 1 952 7 view .LVU744 + 1936 01c2 0023 movs r3, #0 + 1937 01c4 84F83430 strb r3, [r4, #52] + 1938 .L114: + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1939 .loc 1 952 7 discriminator 1 view .LVU745 + 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1940 .loc 1 956 5 view .LVU746 + 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1941 .loc 1 956 12 is_stmt 0 view .LVU747 + 1942 01c8 E36C ldr r3, [r4, #76] + 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1943 .loc 1 956 7 view .LVU748 + 1944 01ca 0BB1 cbz r3, .L97 + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 1945 .loc 1 959 7 is_stmt 1 view .LVU749 + 1946 01cc 2046 mov r0, r4 + 1947 01ce 9847 blx r3 + 1948 .LVL139: + 1949 .L97: + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1950 .loc 1 962 1 is_stmt 0 view .LVU750 + 1951 01d0 03B0 add sp, sp, #12 + 1952 .LCFI15: + 1953 .cfi_def_cfa_offset 20 + 1954 @ sp needed + 1955 01d2 F0BD pop {r4, r5, r6, r7, pc} + 1956 .LVL140: + 1957 .L121: + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1958 .loc 1 962 1 view .LVU751 + 1959 .align 2 + 1960 .L120: + 1961 01d4 00000000 .word SystemCoreClock + 1962 01d8 B5814E1B .word 458129845 + 1963 .cfi_endproc + 1964 .LFE148: + 1966 .section .text.HAL_DMA_RegisterCallback,"ax",%progbits + 1967 .align 1 + 1968 .global HAL_DMA_RegisterCallback + ARM GAS /tmp/ccjAMZS2.s page 70 + + + 1969 .syntax unified + 1970 .thumb + 1971 .thumb_func + 1973 HAL_DMA_RegisterCallback: + 1974 .LVL141: + 1975 .LFB149: + 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1976 .loc 1 975 1 is_stmt 1 view -0 + 1977 .cfi_startproc + 1978 @ args = 0, pretend = 0, frame = 0 + 1979 @ frame_needed = 0, uses_anonymous_args = 0 + 1980 @ link register save eliminated. + 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1981 .loc 1 975 1 is_stmt 0 view .LVU753 + 1982 0000 0346 mov r3, r0 + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1983 .loc 1 977 3 is_stmt 1 view .LVU754 + 1984 .LVL142: + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1985 .loc 1 980 3 view .LVU755 + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1986 .loc 1 980 3 view .LVU756 + 1987 0002 90F83400 ldrb r0, [r0, #52] @ zero_extendqisi2 + 1988 .LVL143: + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1989 .loc 1 980 3 is_stmt 0 view .LVU757 + 1990 0006 0128 cmp r0, #1 + 1991 0008 25D0 beq .L132 + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1992 .loc 1 980 3 is_stmt 1 discriminator 2 view .LVU758 + 1993 000a 0120 movs r0, #1 + 1994 000c 83F83400 strb r0, [r3, #52] + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 1995 .loc 1 980 3 discriminator 2 view .LVU759 + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1996 .loc 1 982 3 view .LVU760 + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 1997 .loc 1 982 33 is_stmt 0 view .LVU761 + 1998 0010 93F83500 ldrb r0, [r3, #53] @ zero_extendqisi2 + 1999 0014 C0B2 uxtb r0, r0 + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 2000 .loc 1 982 5 view .LVU762 + 2001 0016 0128 cmp r0, #1 + 2002 0018 04D0 beq .L135 +1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 2003 .loc 1 1019 12 view .LVU763 + 2004 001a 0120 movs r0, #1 + 2005 .L124: + 2006 .LVL144: +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2007 .loc 1 1023 3 is_stmt 1 view .LVU764 +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2008 .loc 1 1023 3 view .LVU765 + 2009 001c 0022 movs r2, #0 + 2010 .LVL145: +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2011 .loc 1 1023 3 is_stmt 0 view .LVU766 + ARM GAS /tmp/ccjAMZS2.s page 71 + + + 2012 001e 83F83420 strb r2, [r3, #52] +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2013 .loc 1 1023 3 is_stmt 1 view .LVU767 +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 2014 .loc 1 1025 3 view .LVU768 +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 2015 .loc 1 1025 10 is_stmt 0 view .LVU769 + 2016 0022 7047 bx lr + 2017 .LVL146: + 2018 .L135: + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 2019 .loc 1 984 5 is_stmt 1 view .LVU770 + 2020 0024 0529 cmp r1, #5 + 2021 0026 F9D8 bhi .L124 + 2022 0028 DFE801F0 tbb [pc, r1] + 2023 .L126: + 2024 002c 03 .byte (.L131-.L126)/2 + 2025 002d 06 .byte (.L130-.L126)/2 + 2026 002e 09 .byte (.L129-.L126)/2 + 2027 002f 0C .byte (.L128-.L126)/2 + 2028 0030 0F .byte (.L127-.L126)/2 + 2029 0031 12 .byte (.L125-.L126)/2 + 2030 .p2align 1 + 2031 .L131: + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2032 .loc 1 987 7 view .LVU771 + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2033 .loc 1 987 30 is_stmt 0 view .LVU772 + 2034 0032 DA63 str r2, [r3, #60] + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2035 .loc 1 988 7 is_stmt 1 view .LVU773 + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2036 .loc 1 977 21 is_stmt 0 view .LVU774 + 2037 0034 0846 mov r0, r1 + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2038 .loc 1 988 7 view .LVU775 + 2039 0036 F1E7 b .L124 + 2040 .L130: + 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2041 .loc 1 991 7 is_stmt 1 view .LVU776 + 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2042 .loc 1 991 34 is_stmt 0 view .LVU777 + 2043 0038 1A64 str r2, [r3, #64] + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2044 .loc 1 992 7 is_stmt 1 view .LVU778 + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2045 .loc 1 977 21 is_stmt 0 view .LVU779 + 2046 003a 0020 movs r0, #0 + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2047 .loc 1 992 7 view .LVU780 + 2048 003c EEE7 b .L124 + 2049 .L129: + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2050 .loc 1 995 7 is_stmt 1 view .LVU781 + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2051 .loc 1 995 32 is_stmt 0 view .LVU782 + 2052 003e 5A64 str r2, [r3, #68] + ARM GAS /tmp/ccjAMZS2.s page 72 + + + 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2053 .loc 1 996 7 is_stmt 1 view .LVU783 + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2054 .loc 1 977 21 is_stmt 0 view .LVU784 + 2055 0040 0020 movs r0, #0 + 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2056 .loc 1 996 7 view .LVU785 + 2057 0042 EBE7 b .L124 + 2058 .L128: + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2059 .loc 1 999 7 is_stmt 1 view .LVU786 + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2060 .loc 1 999 36 is_stmt 0 view .LVU787 + 2061 0044 9A64 str r2, [r3, #72] +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2062 .loc 1 1000 7 is_stmt 1 view .LVU788 + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2063 .loc 1 977 21 is_stmt 0 view .LVU789 + 2064 0046 0020 movs r0, #0 +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2065 .loc 1 1000 7 view .LVU790 + 2066 0048 E8E7 b .L124 + 2067 .L127: +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2068 .loc 1 1003 7 is_stmt 1 view .LVU791 +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2069 .loc 1 1003 31 is_stmt 0 view .LVU792 + 2070 004a DA64 str r2, [r3, #76] +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2071 .loc 1 1004 7 is_stmt 1 view .LVU793 + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2072 .loc 1 977 21 is_stmt 0 view .LVU794 + 2073 004c 0020 movs r0, #0 +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2074 .loc 1 1004 7 view .LVU795 + 2075 004e E5E7 b .L124 + 2076 .L125: +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2077 .loc 1 1007 7 is_stmt 1 view .LVU796 +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2078 .loc 1 1007 31 is_stmt 0 view .LVU797 + 2079 0050 1A65 str r2, [r3, #80] +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2080 .loc 1 1008 7 is_stmt 1 view .LVU798 + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2081 .loc 1 977 21 is_stmt 0 view .LVU799 + 2082 0052 0020 movs r0, #0 +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2083 .loc 1 1008 7 view .LVU800 + 2084 0054 E2E7 b .L124 + 2085 .L132: + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2086 .loc 1 980 3 discriminator 1 view .LVU801 + 2087 0056 0220 movs r0, #2 +1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2088 .loc 1 1026 1 view .LVU802 + 2089 0058 7047 bx lr + ARM GAS /tmp/ccjAMZS2.s page 73 + + + 2090 .cfi_endproc + 2091 .LFE149: + 2093 .section .text.HAL_DMA_UnRegisterCallback,"ax",%progbits + 2094 .align 1 + 2095 .global HAL_DMA_UnRegisterCallback + 2096 .syntax unified + 2097 .thumb + 2098 .thumb_func + 2100 HAL_DMA_UnRegisterCallback: + 2101 .LVL147: + 2102 .LFB150: +1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 2103 .loc 1 1037 1 is_stmt 1 view -0 + 2104 .cfi_startproc + 2105 @ args = 0, pretend = 0, frame = 0 + 2106 @ frame_needed = 0, uses_anonymous_args = 0 + 2107 @ link register save eliminated. +1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 2108 .loc 1 1037 1 is_stmt 0 view .LVU804 + 2109 0000 0346 mov r3, r0 +1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2110 .loc 1 1038 3 is_stmt 1 view .LVU805 + 2111 .LVL148: +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2112 .loc 1 1041 3 view .LVU806 +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2113 .loc 1 1041 3 view .LVU807 + 2114 0002 90F83420 ldrb r2, [r0, #52] @ zero_extendqisi2 + 2115 0006 012A cmp r2, #1 + 2116 0008 2FD0 beq .L147 +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2117 .loc 1 1041 3 discriminator 2 view .LVU808 + 2118 000a 0122 movs r2, #1 + 2119 000c 80F83420 strb r2, [r0, #52] +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2120 .loc 1 1041 3 discriminator 2 view .LVU809 +1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 2121 .loc 1 1043 3 view .LVU810 +1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 2122 .loc 1 1043 33 is_stmt 0 view .LVU811 + 2123 0010 90F83500 ldrb r0, [r0, #53] @ zero_extendqisi2 + 2124 .LVL149: +1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 2125 .loc 1 1043 33 view .LVU812 + 2126 0014 C0B2 uxtb r0, r0 +1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 2127 .loc 1 1043 5 view .LVU813 + 2128 0016 9042 cmp r0, r2 + 2129 0018 04D0 beq .L150 +1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 2130 .loc 1 1087 12 view .LVU814 + 2131 001a 0120 movs r0, #1 + 2132 .L138: + 2133 .LVL150: +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2134 .loc 1 1091 3 is_stmt 1 view .LVU815 +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + ARM GAS /tmp/ccjAMZS2.s page 74 + + + 2135 .loc 1 1091 3 view .LVU816 + 2136 001c 0022 movs r2, #0 + 2137 001e 83F83420 strb r2, [r3, #52] +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2138 .loc 1 1091 3 view .LVU817 +1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 2139 .loc 1 1093 3 view .LVU818 +1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 2140 .loc 1 1093 10 is_stmt 0 view .LVU819 + 2141 0022 7047 bx lr + 2142 .LVL151: + 2143 .L150: +1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** { + 2144 .loc 1 1045 5 is_stmt 1 view .LVU820 + 2145 0024 0629 cmp r1, #6 + 2146 0026 F9D8 bhi .L138 + 2147 0028 DFE801F0 tbb [pc, r1] + 2148 .L140: + 2149 002c 04 .byte (.L146-.L140)/2 + 2150 002d 08 .byte (.L145-.L140)/2 + 2151 002e 0B .byte (.L144-.L140)/2 + 2152 002f 0E .byte (.L143-.L140)/2 + 2153 0030 11 .byte (.L142-.L140)/2 + 2154 0031 14 .byte (.L141-.L140)/2 + 2155 0032 17 .byte (.L139-.L140)/2 + 2156 0033 00 .p2align 1 + 2157 .L146: +1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2158 .loc 1 1048 7 view .LVU821 +1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2159 .loc 1 1048 30 is_stmt 0 view .LVU822 + 2160 0034 0022 movs r2, #0 + 2161 0036 DA63 str r2, [r3, #60] +1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2162 .loc 1 1049 7 is_stmt 1 view .LVU823 +1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2163 .loc 1 1038 21 is_stmt 0 view .LVU824 + 2164 0038 0846 mov r0, r1 +1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2165 .loc 1 1049 7 view .LVU825 + 2166 003a EFE7 b .L138 + 2167 .L145: +1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2168 .loc 1 1052 7 is_stmt 1 view .LVU826 +1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2169 .loc 1 1052 34 is_stmt 0 view .LVU827 + 2170 003c 0020 movs r0, #0 + 2171 003e 1864 str r0, [r3, #64] +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2172 .loc 1 1053 7 is_stmt 1 view .LVU828 + 2173 0040 ECE7 b .L138 + 2174 .L144: +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2175 .loc 1 1056 7 view .LVU829 +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2176 .loc 1 1056 32 is_stmt 0 view .LVU830 + 2177 0042 0020 movs r0, #0 + ARM GAS /tmp/ccjAMZS2.s page 75 + + + 2178 0044 5864 str r0, [r3, #68] +1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2179 .loc 1 1057 7 is_stmt 1 view .LVU831 + 2180 0046 E9E7 b .L138 + 2181 .L143: +1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2182 .loc 1 1060 7 view .LVU832 +1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2183 .loc 1 1060 36 is_stmt 0 view .LVU833 + 2184 0048 0020 movs r0, #0 + 2185 004a 9864 str r0, [r3, #72] +1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2186 .loc 1 1061 7 is_stmt 1 view .LVU834 + 2187 004c E6E7 b .L138 + 2188 .L142: +1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2189 .loc 1 1064 7 view .LVU835 +1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2190 .loc 1 1064 31 is_stmt 0 view .LVU836 + 2191 004e 0020 movs r0, #0 + 2192 0050 D864 str r0, [r3, #76] +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2193 .loc 1 1065 7 is_stmt 1 view .LVU837 + 2194 0052 E3E7 b .L138 + 2195 .L141: +1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2196 .loc 1 1068 7 view .LVU838 +1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2197 .loc 1 1068 31 is_stmt 0 view .LVU839 + 2198 0054 0020 movs r0, #0 + 2199 0056 1865 str r0, [r3, #80] +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2200 .loc 1 1069 7 is_stmt 1 view .LVU840 + 2201 0058 E0E7 b .L138 + 2202 .L139: +1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 2203 .loc 1 1072 7 view .LVU841 +1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 2204 .loc 1 1072 30 is_stmt 0 view .LVU842 + 2205 005a 0020 movs r0, #0 + 2206 005c D863 str r0, [r3, #60] +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferM1CpltCallback = NULL; + 2207 .loc 1 1073 7 is_stmt 1 view .LVU843 +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferM1CpltCallback = NULL; + 2208 .loc 1 1073 34 is_stmt 0 view .LVU844 + 2209 005e 1864 str r0, [r3, #64] +1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferM1HalfCpltCallback = NULL; + 2210 .loc 1 1074 7 is_stmt 1 view .LVU845 +1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferM1HalfCpltCallback = NULL; + 2211 .loc 1 1074 32 is_stmt 0 view .LVU846 + 2212 0060 5864 str r0, [r3, #68] +1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 2213 .loc 1 1075 7 is_stmt 1 view .LVU847 +1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 2214 .loc 1 1075 36 is_stmt 0 view .LVU848 + 2215 0062 9864 str r0, [r3, #72] +1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + ARM GAS /tmp/ccjAMZS2.s page 76 + + + 2216 .loc 1 1076 7 is_stmt 1 view .LVU849 +1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 2217 .loc 1 1076 31 is_stmt 0 view .LVU850 + 2218 0064 D864 str r0, [r3, #76] +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2219 .loc 1 1077 7 is_stmt 1 view .LVU851 +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** break; + 2220 .loc 1 1077 31 is_stmt 0 view .LVU852 + 2221 0066 1865 str r0, [r3, #80] +1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2222 .loc 1 1078 7 is_stmt 1 view .LVU853 + 2223 0068 D8E7 b .L138 + 2224 .LVL152: + 2225 .L147: +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2226 .loc 1 1041 3 is_stmt 0 discriminator 1 view .LVU854 + 2227 006a 0220 movs r0, #2 + 2228 .LVL153: +1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2229 .loc 1 1094 1 view .LVU855 + 2230 006c 7047 bx lr + 2231 .cfi_endproc + 2232 .LFE150: + 2234 .section .text.HAL_DMA_GetState,"ax",%progbits + 2235 .align 1 + 2236 .global HAL_DMA_GetState + 2237 .syntax unified + 2238 .thumb + 2239 .thumb_func + 2241 HAL_DMA_GetState: + 2242 .LVL154: + 2243 .LFB151: +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return hdma->State; + 2244 .loc 1 1122 1 is_stmt 1 view -0 + 2245 .cfi_startproc + 2246 @ args = 0, pretend = 0, frame = 0 + 2247 @ frame_needed = 0, uses_anonymous_args = 0 + 2248 @ link register save eliminated. +1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 2249 .loc 1 1123 3 view .LVU857 +1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 2250 .loc 1 1123 14 is_stmt 0 view .LVU858 + 2251 0000 90F83500 ldrb r0, [r0, #53] @ zero_extendqisi2 + 2252 .LVL155: +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2253 .loc 1 1124 1 view .LVU859 + 2254 0004 7047 bx lr + 2255 .cfi_endproc + 2256 .LFE151: + 2258 .section .text.HAL_DMA_GetError,"ax",%progbits + 2259 .align 1 + 2260 .global HAL_DMA_GetError + 2261 .syntax unified + 2262 .thumb + 2263 .thumb_func + 2265 HAL_DMA_GetError: + 2266 .LVL156: + ARM GAS /tmp/ccjAMZS2.s page 77 + + + 2267 .LFB152: +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** return hdma->ErrorCode; + 2268 .loc 1 1133 1 is_stmt 1 view -0 + 2269 .cfi_startproc + 2270 @ args = 0, pretend = 0, frame = 0 + 2271 @ frame_needed = 0, uses_anonymous_args = 0 + 2272 @ link register save eliminated. +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 2273 .loc 1 1134 3 view .LVU861 +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** } + 2274 .loc 1 1134 14 is_stmt 0 view .LVU862 + 2275 0000 406D ldr r0, [r0, #84] + 2276 .LVL157: +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c **** + 2277 .loc 1 1135 1 view .LVU863 + 2278 0002 7047 bx lr + 2279 .cfi_endproc + 2280 .LFE152: + 2282 .section .rodata.flagBitshiftOffset.0,"a" + 2283 .align 2 + 2286 flagBitshiftOffset.0: + 2287 0000 00061016 .ascii "\000\006\020\026\000\006\020\026" + 2287 00061016 + 2288 .text + 2289 .Letext0: + 2290 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 2291 .file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 2292 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + 2293 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 2294 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h" + 2295 .file 7 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h" + 2296 .file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h" + ARM GAS /tmp/ccjAMZS2.s page 78 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_dma.c + /tmp/ccjAMZS2.s:20 .text.DMA_SetConfig:00000000 $t + /tmp/ccjAMZS2.s:25 .text.DMA_SetConfig:00000000 DMA_SetConfig + /tmp/ccjAMZS2.s:99 .text.DMA_CalcBaseAndBitshift:00000000 $t + /tmp/ccjAMZS2.s:104 .text.DMA_CalcBaseAndBitshift:00000000 DMA_CalcBaseAndBitshift + /tmp/ccjAMZS2.s:173 .text.DMA_CalcBaseAndBitshift:00000034 $d + /tmp/ccjAMZS2.s:2286 .rodata.flagBitshiftOffset.0:00000000 flagBitshiftOffset.0 + /tmp/ccjAMZS2.s:179 .text.DMA_CheckFifoParam:00000000 $t + /tmp/ccjAMZS2.s:184 .text.DMA_CheckFifoParam:00000000 DMA_CheckFifoParam + /tmp/ccjAMZS2.s:270 .text.DMA_CheckFifoParam:0000004e $d + /tmp/ccjAMZS2.s:274 .text.DMA_CheckFifoParam:00000052 $t + /tmp/ccjAMZS2.s:369 .text.HAL_DMA_Init:00000000 $t + /tmp/ccjAMZS2.s:375 .text.HAL_DMA_Init:00000000 HAL_DMA_Init + /tmp/ccjAMZS2.s:625 .text.HAL_DMA_Init:000000cc $d + /tmp/ccjAMZS2.s:630 .text.HAL_DMA_DeInit:00000000 $t + /tmp/ccjAMZS2.s:636 .text.HAL_DMA_DeInit:00000000 HAL_DMA_DeInit + /tmp/ccjAMZS2.s:769 .text.HAL_DMA_Start:00000000 $t + /tmp/ccjAMZS2.s:775 .text.HAL_DMA_Start:00000000 HAL_DMA_Start + /tmp/ccjAMZS2.s:858 .text.HAL_DMA_Start_IT:00000000 $t + /tmp/ccjAMZS2.s:864 .text.HAL_DMA_Start_IT:00000000 HAL_DMA_Start_IT + /tmp/ccjAMZS2.s:989 .text.HAL_DMA_Abort:00000000 $t + /tmp/ccjAMZS2.s:995 .text.HAL_DMA_Abort:00000000 HAL_DMA_Abort + /tmp/ccjAMZS2.s:1152 .text.HAL_DMA_Abort_IT:00000000 $t + /tmp/ccjAMZS2.s:1158 .text.HAL_DMA_Abort_IT:00000000 HAL_DMA_Abort_IT + /tmp/ccjAMZS2.s:1204 .text.HAL_DMA_PollForTransfer:00000000 $t + /tmp/ccjAMZS2.s:1210 .text.HAL_DMA_PollForTransfer:00000000 HAL_DMA_PollForTransfer + /tmp/ccjAMZS2.s:1505 .text.HAL_DMA_IRQHandler:00000000 $t + /tmp/ccjAMZS2.s:1511 .text.HAL_DMA_IRQHandler:00000000 HAL_DMA_IRQHandler + /tmp/ccjAMZS2.s:1961 .text.HAL_DMA_IRQHandler:000001d4 $d + /tmp/ccjAMZS2.s:1967 .text.HAL_DMA_RegisterCallback:00000000 $t + /tmp/ccjAMZS2.s:1973 .text.HAL_DMA_RegisterCallback:00000000 HAL_DMA_RegisterCallback + /tmp/ccjAMZS2.s:2024 .text.HAL_DMA_RegisterCallback:0000002c $d + /tmp/ccjAMZS2.s:2030 .text.HAL_DMA_RegisterCallback:00000032 $t + /tmp/ccjAMZS2.s:2094 .text.HAL_DMA_UnRegisterCallback:00000000 $t + /tmp/ccjAMZS2.s:2100 .text.HAL_DMA_UnRegisterCallback:00000000 HAL_DMA_UnRegisterCallback + /tmp/ccjAMZS2.s:2149 .text.HAL_DMA_UnRegisterCallback:0000002c $d + /tmp/ccjAMZS2.s:2235 .text.HAL_DMA_GetState:00000000 $t + /tmp/ccjAMZS2.s:2241 .text.HAL_DMA_GetState:00000000 HAL_DMA_GetState + /tmp/ccjAMZS2.s:2259 .text.HAL_DMA_GetError:00000000 $t + /tmp/ccjAMZS2.s:2265 .text.HAL_DMA_GetError:00000000 HAL_DMA_GetError + /tmp/ccjAMZS2.s:2283 .rodata.flagBitshiftOffset.0:00000000 $d + /tmp/ccjAMZS2.s:2156 .text.HAL_DMA_UnRegisterCallback:00000033 $d + /tmp/ccjAMZS2.s:2156 .text.HAL_DMA_UnRegisterCallback:00000034 $t + +UNDEFINED SYMBOLS +HAL_GetTick +SystemCoreClock diff --git a/build/stm32f7xx_hal_dma.o b/build/stm32f7xx_hal_dma.o new file mode 100644 index 0000000000000000000000000000000000000000..ac02e0d6c6a5f36d131324a4a6f456cd16a290ed GIT binary patch literal 26424 zcmc(nd3;pW`Ty^oJ9n~@gh|4_OcKCAl1W%1paHTGKtUh`MMRTHX2JxrISIJbB`V-X zty}BXRx4Vqwsomm>sG&3)cS2TwDw!KuXU@bt*uzGZmoVlpL3o&b7z41TmJao7boxY zJm=Pq5@WSXYo9HvofBqYOly;YUi^At*rN+W1g-DgM3qtgxyO)GEn zMmyRrh}M?b!&daVHY@saTh$}|%dF`2$iLL~$w=OP;JtYZGmp9XbF_hE+RoqIuKsORKQyvO!0qkKW+;}PTMciwTw9jxwxE$4S#`7^UDbJ$bn8P2-L z2=p)e#g_d2L+6(6)A^r#@c6mYhMB+jBcn9~cGF+7%BJtrRwc^HDzjev!=J4E1>S

S=f#DbVF2;*Q z7EeQFLuiY4=9J+HZ8M_Vx~A_>vpcp-Zt#|+?b`#swPoTx0TsvPKid}4xi@>3lw4JN zL7Ne1iNM?JF@eW z>e`*3%&QGFEqIi@wg7#0`6u%XvvlIHi9VQTT&-#|OTELo?>vD8k9t(^7}FyW-5&O5 zgX+)HruRoYfxnK>&(0q0sp_jepmb7!0OI0hqB99`Gduz$!}7b@v4xku~MmENh- z2)v9sUmW3h@9N<=BIc@B?)8-UhKHmt=b5sa0J#6lzu5%#cMG6bC`K60F|74Pm} z=54yDX^a{vC;GIc=pX&l{tM4*Dv2Vd14HK?z3;&fjNC>0-s)MsKaiREnf2LiJx50; z{MpKF*w@j+sF&<};DaxhqzxOvDi!}tf5|ZJuAlYd(a|@0(u*&tolx%`4)xUSH_cGw zp|&@AOqb51bZ_=}r+>3{a{X_I+k5Kwdp+%uN85fqviiW#KnGg#zzFNkQ*}Q+!fQra zuC6dE@cogFo{9J9SaMXf{%Rrq9+}8bL;c4vhkYs=4K5~h!!L632nOU z;kJez&eDd+n?0to%@{6@Hh1~=59NA?A8zYFsmJO-sW)EghbK?G)T>Gv&)oWHIG3gA zxl?hjT1O5HRgN0w_!yPmeI?yD;JUwdS>Ee=x(8G)>vhD1v9tCuu5`pz(w(JB-s}k| zpXRs6m8A z*~q@XjJ&mVkBVosM4F)@%|oQ_v3+Z+j=H1ga~a>U!?s$lbR=9?%^S?Q=2dsrdtX#D z7W46=eMvr~<<{N%ALYH{{_~ETXvxYm9qYvfSb46BuRLbJD29et&&*G8cQE%`zKrZ# z|H~ceO&^R*2pfUFjcmlauzkeEe8GrvcG9h9F-o(m)`x`w6%vqJgX7LbmdIh~4 zS3ttEPdt0mvvNikj5Um6dVhb!2#gEAhrb)b@8a*Z;dk)&#qe9yM_y;XV_bMc_}cJ` z;c<}{Rc-X%zpS>0_aMWUH-_onEW_|XGz_o#fX^_piy?hiYn0mg<4I4u(t@owtrlh; zGkppr(|0uCv3cwFc$?DjNZL z?XKQIBW)E_X$wcQ#5B`8fxD10s;D-+Hv*aCtnZl_Q{XC3+|A6)0 z;>g~tHFYSz)sfS)Uts;;cjWBsHp;g-a$Z&w{oU@!1;!{=Z~efu?gMkuOx2cen@y-D z_m_y-$XmCx1^XONy7$M>iG_WHIY^5!_+#Y$3!Q1^4kPQyt;1gnJph$mZmn{iG6xeA z#%g<%n}w`tSl#GoyV@FpG`h-HmBG{euR`+8$yOa#V))0yqpw;-um2O4E)+4{U(bH6 z5i#5U2Z~EX%=14;v0lUi|Cbb(ia5@HGCdz7;v|0?OIL{)@Ou%PuUW)t{u9uVzV#xO z`UfbUBx1Q?J!#bBvc6eTell&S~-sZbF&xFqZ0&IPkPGuhR&HrZx_Vp((j14(jVlxH;TB%e-_2>P0<%ci~kxL@0p@!%m)95Y~rmVZZZnI zypRgLW6VNCGM0a!D?)t*-V6xVV^H{R^Jq;GG^4Z4{){cij9am;*)U_y)#slBN9KTt zUjOqjF$YCVH>@sHY;LpWLOtI62wu~Fn`x@ce8T%QebPHYT{kE(E<^I1ZJ2MNU}77B zL1}FTgc_FOm{iSEp7Iv*N*j-!Ekv3;*wb&APkYtG>xE(gk}>5hR(!j6w5p6J)5$2F zUyBm${&sH--5-mz6lqd~#dl~==OKSK($o!X;E%lHxFFdG3P)fEgWKgDg(AZ!M|y;3 zeix35RNT9~K{__q6rF)WST0gcUR(4MwY$8{N^G9!=OwVqyP4t_C^~>-6q{*if!XcV z9R-a+HGAf_@zA?<4eOy;i-eOV(^m*X%8P{uWOY(HGP=DX?@&e4E?C}%RP;6koD$;YWvx2rt%-2vGm=C)PpqbUW9TgGSkg9owW~V1H1f?)KpUP*_oo?v#EM_-+AKIId zCjJBh&IxgeeHMx*sa&mQN(MOuCJo(4~8(7$#GYCXM4X-lCPq zK~YPk>gcUnc^edas8oH}tNZYmQ0zsTnSpJnKX#)+6Z%({zMqKyezC zs(~50E#HD-H`2^ZiFW2Gl0l6n$eMf2#86;P7{7zHIR)mr#=WMB^HXR)LYk;nj=g3R zd%Xx&V`-_@kG^1wT{5=%EM$%Wx)214qAohEuNV*lznrg0Yf?^}m ztOYoYYogPuN0=wDSFdx0yBsEcur(iKeQJrj&Qu+A6|~<#(&1ibHZX{Xp}2=i74CKB z1}ev7W21?r!@bVzq4HEHHY4e9Z_wdB1H}_avyOyCa%AOPbmqGvp^TQi^asmSJ= z)f~FgQCO&vbfXvQMsJ29f;4L}&f|TCjoyZQnYjah%{voA#Le58Fg44S*E{FZ>35;H z9;rgzbbh3ki{~Ief)rHK;m1nXgvncj6jU?&F4f@|Lf(lqle17w>^YLDyd0UGaDNLL zA;U21dgz=8Ib95Mv^hN|Kg-IQn6utD+H5xSaM5|D8ChA2p~OvljA7**m34I1!mJhf zxM$2T2)kOrCw8biZJx_+Np=l-FWod(krX0%j-h-u&#pQ-_@BtPG@ za#R>%QILz)vQ>r5U``d9M`ZKVv9@aEI0-ZEVSLb7lI`@$5!oy9+1d#~xYe;!HQMx> zwVBt{D@PNt^NhF4)g7aROQxHI#n?I|L?=kE67+w6d+|9 zA6g$7Ge55S*tn7M6kSXNkle+TXCdKiq8!OxOu11P6HO__lv{K$aePWKSAJhN-^crbun>fN-^cLbTM&GN-^ajB!otskL0eK z@(v^v6T4E1DPN?EiAz$7Deua^Vr6^A{^7IOUXAm=g8M#8;b=e?xv|Fad@$FT7NDaSO(m?Z>HaL-)I zdW@1LQ6AIls(}?`=7E{%&SR%3>4A@DPUo^RZ#uuWiXZN91JEL@bh23I z70X2r9OB^8g-#+SAbE^IFG&X~d`quplxIjeNvG~|h)D+nLr)OwCwEUI*-1G}Y3BP1 zQ=Y1OYYnjl39%F1DjQ$UpoKym*xln`Ad?iUZX{hJ#hJ^?97sAC4B{d-s%+e4!i<+L zhK`^|)l84>G0OV9X5`fIm7&l+H55kf%t-bT@&)8?;0^fz$&aGcLw%UzZs^e%;y#sa zAs*6N;xVlyUeH?N1voa17J_vgdKf3f4Ub1o4lZ!|?DdWcpUUIP6B0`KA_5m3o5hcl zY?iy6d2EH*0D>k6irVBu+pJYKC^3x-h4L>^}ez z^M!~bR#6rxRK*Awk3yN2M&sxk5j2%;Q|!BdcMx}zdJD(TJEu+HaE?>_LYAWtJ`;+hJs zg;!4Sg7rvjZ6nwudGZ(}+^LBzD!Z1@>q#^5W2IeBJgBnG#8X;J=m=diJpLmk&eLhi zP;LDff@!R01lqsL>3Vv4M%&`A9M^-lAi4TyH$?W2zUov)ZMvAN(W2VPGRw$#gf-NN zGs~-w$JH8YwlT{)3=iJYd2G~Bn|fw_B721n$|du^QU61@KU+ovBKDY{=ZrGY`HUXP zY>ahnkHiKl*R`ygJEv*>>8H0YuUpxwwUz5)9Y*E0fmmgCS9|5=j*iMutf!*4uQyT= z3AJ}s&Yl~b6P#Vy)!Wg%EgUf%R}HJytyovt7}?&{5rN-?>&g`=mWQkqMussk*fV!d zC&P(`x?96Np3`TldP6M(ctN#mF;u}7o84*0C>pq+v2_<(Ig%j|@J zZ5BhaVuvWg9m6ye72Pfs71`xDbAG_C4cOVNU{$_76Pm)Hio%Di?VD{M1+ER+lW9?E zo4$P3y1-rt_2i%@Ey?wh8E8R%zMYLi2AoG90bjAN6U~@rkAavOunVp2H32BBJmei! zKUC>H3)N)tB%d{@#!hQaobvN?VF2~ifNv1z9+4>7sGXI&oV7reXJrQhGXi#wH97!k zy3XezZ%Dr1&vy=J3eZk#jGe1WmY6kTPO{5Q zI|m|03&GeJI}XiQ!{arBb{Y{te~yJN4a`?uj2^X~Gw9v=>ACC`-E*4rRR0_quxFuh zMfUQk_K`*ZE}u3Ter8CwBU`O{i6b$Jwdq-;UC*`)5-Kzg5pj4j82B_5TsosER>P6W z;Ac4`6DtCCQ2@1I7EcP;<5?qW z<}AqYEmnbNTQ{5=4B&~sd(QsUgKo*!<6zEWAeljW4q|$-orNcSM!>_oQY{~|m4 zFb$f3*eqX>Jw-T4sGDD8PZU{Gb%5#!-Tv8Tut0TzS!8EhO}I?0qXH=t?m9~*Tw$T< z3!&i%?hSZ|jnSHya@FsR zS7I+v5tkgcvdKx6O=D%Php22S+@QnrFb1*;VQEln(jqnS9ci%&It|N!noETNUVpZ) zmeHOp(OMb7lz4Y|b*EHGxW#fYR_O^<Ren6ay_dx6aRVrNt^s+m3uw?Ew0T7ygMIv5=l zu>Dy0adEI!m{FW9yg{HRFgc|S=#$Knl*#`-?h5SbMfu7;B2R-=X;GZMRz4Bw(8X|Wm+)Lg7?{aEi*K(%%Ws=zI+fE%z9HT@8# zvp&GS%Fd{=7xGf@S-k;!HgjyPRZJmBMPIAct_^|n>5R}97@ z3)^DZS}fUUXA~$U=1rBaPSt`4tMr`E`wz#bJw{!bSfxua_htuE?!V8a=?PhUn41Rf zZPPh9r>WbNzT@eYIPElb=S;)uf%SeH=BCAAvy0IrQJzX=E|t8ein52wd@8y4h_Z{y zu~c$t6=j6Vi7Cnul^7XyFSNqE?_yJtywTg8t{YWU$d2_K!$10-tF{%{R=I8xbeX6Q z?OB7a+bQj-JXCusoi-q&<3>iu>dtU4k%o)f=>(_UPE(!MIaICiStqd>)v3*RBVFA% zxUiU&DNTIORaT_R)CaOvb*&qkmNvK6)vs=DX>F))UD0SXcEutcgI#^ShGVjBFcceX zUD2Wx>yKNxy5ZQRjY?=)v1;k+^)1Fa^*N`ZFBWO&?(5iUtci8?#kvO1Fd9+Ay1`f^ z)YIB>Mt`I+(rMu1UtKsHiwq3JD_GInH5eC~Bb&SMsVUYF>h5k2!C5?vmb#Xut<6jM zt6chB9_kHuM;y1bs$akE#JIU?7_?0dYgRgKqtUX+U`rR=4n+H6g8}|3nOaw)Rv#Pp zftC-(YiN!PL}J?`;VPrG_2Bxq!PA1)L8G%fw7I@(a3I>%Ik>vBb09KkZ0L-{md0Xz zi6&9AYIZ|^_h7u0_@PPHK+MpcRUaCNIGuD{V@tEq-PgN05boR7-W}0-rEr2*y{vji z4W!W!4fXa$y5S7r8>)BX_G==suKp-L4zJ`$vF$t^y`n-i2GKVI9Ps!j??Zl`#wb?C zKi0ZFPCNe8oKfBx#I^zVFeSou=8tn$T|35vGp#b(*AuDijD$m#t5&ROsca5~yZY8d z`v&`ZyE5arfgMG2qH4XJC#?Z75^mPuN7K%lTHTWYV zzO=b{b+a0qRkN3ex;v9bV_WY)*XG_xIM5Ld#p0dR7*TzBs3JAnluNmcqWF5j;G~#4 z2eZOyAlTH}(p-1kI$U=8>WB<{f5!I@s_Bi#g zQ?o=j-O;U#Y>#v|^!4<2M-r3WDQsH5a%Cc5xW`z^rIQq8OIJ^%Z`+`;D$-NGEjED6 zZ2UZbKwtX3+j`m~F+)#1UF`UG=KqSu)ET0B6cUCmN0mr*k%^70_f8D>T3UxLP z3_6!i!nx||hG?W?Yg1QeA7(+QC+=W!g{zC#bE{L!fDR_q-Jve?-mtS=B)h__OkTV?`nF-}qSnUHV5qJe^RtI@ zIk6yeayq@J`#RZDuPrNj!;#Ys6&hn~iDD^^_H~C18n2A>ZXS%r1Hr1m%U4e*)zMCu z8cAKzA6Ii_JLqa+7jd<5g42s3JICofJujP=)-|4p6-ZB|SY-2n(Gwcj+S-AIvYWHi zSa#g{K*Q|$0sSRmU{2MXxwEUP76vMMI{LRQ>cHv|IlZE1KIFkDCLP!beP{pn>Wc8} zBPn+Gg$66|J>w!=*kLF_v5x2>d;__Cex#zOtg}BD?hjOK#=kHYjLwQVfr{0TI>YFk ziUECN9Dv-ptykS73-p(mlIk&dk&n z82l3dOB~pOoRx!L-A!`7;syCFZ(UCM4$n?=b>`kDbBwwy_2AYq;kUnaIo=)Sx=d9_ zU(RtEGJMGE9QbD3!boB}Y6)R2>Rfp>?s6JLUXJ&&Kz$}FejN)%woimdbm|yt0jxU{EhlQ_~3tcjw zK5#tgr5wqlo&hEdEW=K*x7AYy+H;rYcZ zZlgcWEf31+?>HoVX#2#IHa;jy92S0Ap6oAOo&T%238P3H79Lr`5 zWqD3Yc}~jtc`4<2Ddql@a(_yBeoA?MN_k;Qd7)}Ae~F=wNF@WzVtJhc2Jv zh_H7b7G_7X$8jm=yH^AD&-fJk@osl0pO8|{AD1K!3-g8JpEy$Ik9#F!eNz&q$XUkJ z6uBrxE=iH6r^rXB`sc>Ay8Vgyo!Z`+aZ6?_^(;Q2vWzmL3nGVyYo#CamCp>FgR|p& zB$ji%^kaUi{{(|P*G50)BY)7sa;}Gd%)h%u<{IcX^5mC2`dPCdn&+jQ>z?1pH%3I} z8pql98D!^R{h83yKi4-u#=k^lu5W&f|6-B3zWFh}t3~Ge=I4*f4z+Wih8;gYt;P4F zlyF}^XqPfAe25P@!K#0^#fpExb3S}I_kGz>J0dn4_~4NwIiEWjjo#`x#qkddjw1EW z>*!s(xYQ4-j)}83i|=Ecf`79)jBkz{+xTaw1?Xo_rG8GFiHjo$ncPk08pgLsEMrFr zc`avRndF=$Ic~J)_>x@l$TlH9z#EzM`qx~ZCT;J56Rvz7{C;G#km~?tUeTUv{5G6C zQtlhj^O|8f;~?vVoX3<`3y&9`B;-6}`G9bj@Jiux!oLZ>5Kcwhsy^Wg;U;0bFe>a7 zZWDe(_)X!rh4%;_7d|h1P54*gKZRMidT&kFYm|04WA__2`xtC;6o*b0yt!d&4PVX?4MxLCMKxJkHGc&6}T;kCls zgbxV!3i%&mS^rzYzYB}8kWjx;c#?3d@O0rW;Z-DlEpUzS7SZ2LViMjb{F&(Yiu_CA z%fi=$Z5)`@%!iFBN>nS{Sh zB>Zm`o+-Ro_)QXa*9mVD{g22B{GTb|W1@eSg#B~E---TBvdl2v5%PccvR?jYZrWQ| zD9B6_`mtmw{(qFPRP^&m*ewt)68%cy2GMU4c8I>8oQC_D@I29forJ$Dgx?bVt-^am zf4}e{(LW{fv%u6LiiiuJ0#-yki>T8W8vo{;|@-Xpxr)8%5tNJVo^F!p))|5cxFWS)#v4&Gd10>q_iSSF&XX6K_9&8Kqgast*rjYPAOXQ$%uIQJD+#p;o`WBHl2u~*A zzf*WB3BTu%xcQwg+(n|^%ccC=BHtvuRrL3We82D^(LW{fv%=>^|BA?e5WX$?{URR_ z^8b7?E*m#=#*rb+ArWVQM0o`{)-YxZt4Y`|k@90jUM*}9eVfQ(VVCH)iF}6e9MNAQ z@@2xSM1P~mdxW=>i02_Gf11SR;y;DYlZfvnDgUF$?+X7W`p-oELTKUtn$b@oiFOx} ze(Y0(GfDX6e^g}oQ6euE9w%%To~enZk2~JB1euuM>Vpc#H6M;e*0Qguf6zE&RRk72%u0cZB~C zekSDa^Vkmj222spyA;O@1Hx&-dBO!kJS0^14Z?N86NIM-)jkgO#6;dMnvuMyrL+#^)`P560GWWKzG@joeiM);DDZ&P9U+rmEy_X`gQN69{Lv~av|vT(X^ zrf{~9?>OK-k}n7$`62}Jc;QAN-?u=0ukbwKPT_9h_M6xbNE|yi<6W@TbCug})F!E#zBAc>cS>r2Q@Q zpNsxWp^y7T=+%A~94&I8aFQ?}JVIC|o$nQ933G+TLbV@8JryF)7V_mH ztY7Va!4pM3Sr`^Zg?&P`ABO#zBA+ANDZE&Cx$tTs-&?}^?iAiDd_c%on6UiU!WV=u z3g0KOPySH&neYo?4)=p7_Y21hCkv}d>}wYa>x4^%CkmbYZ&>80@C@PELcY6%{;n5( zPpJ02(Em{6yM;d$J}i7fsP@6I=bKHqZ+%JlhVYNVPlf*ydb#g|eY&tnI9*sStP<7= z8-;4$i}TgK7i<-Mhmdbdq5mP_g~CgPHwe}K7Ixnk`3|Al-$MVG$b88P{k2a~cZD|#`MwsG|6KT#@LA!@!qB4H^LSe12 zQP?8fAmm$O=x>|wEa8ywa^cm&8-zCs?-Kq*$QR7e->-x(2wxPwE__>ffW+sKPlWt0 zu9Uq(JeE~*o{+DeVR^Z5u5i9^v9MmaLbyuEx76_btwO$rhMz~y5$+ORBIH|XSbnqc z2f`l-`Gy*n|3>(-@HOE(!aoZ?5Pl^5rx1@Ul%F(Vme4O8Bb+QO5|#?fg?u{><2gpS zR=8fcN!TXbEZi!L3AYO`6kaOCZPW1Jc`cubaF4_%J=~uKNVKJtMEzAH`dNK1kNHqb z8Q0Zv66@F+66^2=66<*ziTh-f#Qvh6gtODhGORCT1^$qz*DFjX@dwjKQN@Kg3Mhjr zKE%T(VvH+5A}&;+h$_^4Ef=b|5htGuFkTfu;#HqZ!CLAOccXAQiTGCvRlCrR7RsP% zA1d2K8Ehj_X;>H~(Y|h>YB$cwazV?{hstJWrzI7|*5XE5>mfiF#H4;UR_UKloPt0a^72 z;!y2`tlEil+88fn)h@(!mdHaS;=4)YTS&zDh{%tVi1$U2UnLRu0g*o;5x$RXLzpCZ3YSkv9r8*w~h zt{B0Nz8>}aFxOd~_}Lqb>Y7&tLxY2{uJ&z%aQlCL;8HL!MfovJ9lQ?R2bKYK6yY!J z@UdJSsdg;maRd@B->yxZUHa4-m+b2$Ef z0fpON)a4Ji@VLJ>k$3x>WF`KGG<`b$UPIpPuOI&Mpkx1$PJH~{)9vqW_?rQpb2$D+ z!^my-U$Em^?i`LC-~Z~acL??JUc`Fyk(_$xrugGzde!BRc04Lm{9Oxw9C!M|?J4e$ z_Yt1%TyL);vk|g$IPvj~!EU=FaewV~j6lb3cZ%IDuycIV+_Bq}V#m+_PV8>j{9-#O@m$M2DG_w!BY7e3=*zf3}M`gtV9UoQsX3nvKJ zIsW*4uak$`=pKX5zMOb+IAtFpYO*CjDb*hjTdo z`2Ds!zVuCcZ%cm&A?|OX_^T2JFW^~B7sk#x=#Qx}#ct8jdTmd&TbmMJ7Init.Direction == DMA_MEMORY_TO_MEMORY) + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** status = HAL_ERROR; + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** else + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Process Locked */ + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_LOCK(hdma); + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** if(HAL_DMA_STATE_READY == hdma->State) + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Change DMA peripheral state */ + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->State = HAL_DMA_STATE_BUSY; + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Enable the double buffer mode */ + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Configure DMA Stream destination address */ + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->Instance->M1AR = SecondMemAddress; + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Configure the source, destination address and the data length */ + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Enable the peripheral */ + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_ENABLE(hdma); + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** else + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Return error status */ + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** status = HAL_BUSY; + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** return status; + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + ARM GAS /tmp/ccwTmXyh.s page 4 + + + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /** + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * the configuration information for the specified DMA Stream. + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @param SrcAddress The source memory Buffer address + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @param DstAddress The destination memory Buffer address + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @param DataLength The length of data to be transferred from source to destination + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @retval HAL status + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** */ + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint3 + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Check the parameters */ + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Memory-to-memory transfer not supported in double buffering mode */ + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** return HAL_ERROR; + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Process locked */ + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_LOCK(hdma); + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** if(HAL_DMA_STATE_READY == hdma->State) + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Change DMA peripheral state */ + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->State = HAL_DMA_STATE_BUSY; + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Initialize the error code */ + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Enable the Double buffer mode */ + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Configure DMA Stream destination address */ + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->Instance->M1AR = SecondMemAddress; + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Configure the source, destination address and the data length */ + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Clear all flags */ + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Enable Common interrupts*/ + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->Instance->FCR |= DMA_IT_FE; + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + ARM GAS /tmp/ccwTmXyh.s page 5 + + + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->Instance->CR |= DMA_IT_HT; + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Enable the peripheral */ + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_ENABLE(hdma); + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** else + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Process unlocked */ + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_UNLOCK(hdma); + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Return error status */ + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** status = HAL_BUSY; + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** return status; + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /** + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @brief Change the memory0 or memory1 address on the fly. + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * the configuration information for the specified DMA Stream. + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @param Address The new address + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @param memory the memory to be changed, This parameter can be one of + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * the following values: + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * MEMORY0 / + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * MEMORY1 + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @note The MEMORY0 address can be changed only when the current transfer use + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * MEMORY1 and the MEMORY1 address can be changed only when the current + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * transfer use MEMORY0. + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @retval HAL status + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** */ + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryT + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** if(memory == MEMORY0) + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* change the memory0 address */ + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->Instance->M0AR = Address; + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** else + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* change the memory1 address */ + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->Instance->M1AR = Address; + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** return HAL_OK; + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /** + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @} + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** */ + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /** + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @} + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** */ + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /** @addtogroup DMAEx_Private_Functions + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @{ + ARM GAS /tmp/ccwTmXyh.s page 6 + + + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** */ + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /** + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @brief Set the DMA Transfer parameter. + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * the configuration information for the specified DMA Stream. + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @param SrcAddress The source memory Buffer address + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @param DstAddress The destination memory Buffer address + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @param DataLength The length of data to be transferred from source to destination + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** * @retval HAL status + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** */ + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddr + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 28 .loc 1 272 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .loc 1 272 1 is_stmt 0 view .LVU1 + 34 0000 10B4 push {r4} + 35 .LCFI0: + 36 .cfi_def_cfa_offset 4 + 37 .cfi_offset 4, -4 + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Configure DMA Stream data length */ + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->Instance->NDTR = DataLength; + 38 .loc 1 274 3 is_stmt 1 view .LVU2 + 39 .loc 1 274 24 is_stmt 0 view .LVU3 + 40 0002 0468 ldr r4, [r0] + 41 0004 6360 str r3, [r4, #4] + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Peripheral to Memory */ + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + 42 .loc 1 277 3 is_stmt 1 view .LVU4 + 43 .loc 1 277 17 is_stmt 0 view .LVU5 + 44 0006 8368 ldr r3, [r0, #8] + 45 .LVL1: + 46 .loc 1 277 5 view .LVU6 + 47 0008 402B cmp r3, #64 + 48 000a 06D0 beq .L5 + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Configure DMA Stream destination address */ + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->Instance->PAR = DstAddress; + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Configure DMA Stream source address */ + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->Instance->M0AR = SrcAddress; + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Memory to Peripheral */ + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** else + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Configure DMA Stream source address */ + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->Instance->PAR = SrcAddress; + 49 .loc 1 289 5 is_stmt 1 view .LVU7 + 50 .loc 1 289 9 is_stmt 0 view .LVU8 + 51 000c 0368 ldr r3, [r0] + 52 .loc 1 289 25 view .LVU9 + 53 000e 9960 str r1, [r3, #8] + 54 .LVL2: + ARM GAS /tmp/ccwTmXyh.s page 7 + + + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** /* Configure DMA Stream destination address */ + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->Instance->M0AR = DstAddress; + 55 .loc 1 292 5 is_stmt 1 view .LVU10 + 56 .loc 1 292 9 is_stmt 0 view .LVU11 + 57 0010 0368 ldr r3, [r0] + 58 .loc 1 292 26 view .LVU12 + 59 0012 DA60 str r2, [r3, #12] + 60 .L1: + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 61 .loc 1 294 1 view .LVU13 + 62 0014 5DF8044B ldr r4, [sp], #4 + 63 .LCFI1: + 64 .cfi_remember_state + 65 .cfi_restore 4 + 66 .cfi_def_cfa_offset 0 + 67 0018 7047 bx lr + 68 .LVL3: + 69 .L5: + 70 .LCFI2: + 71 .cfi_restore_state + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 72 .loc 1 280 5 is_stmt 1 view .LVU14 + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 73 .loc 1 280 9 is_stmt 0 view .LVU15 + 74 001a 0368 ldr r3, [r0] + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 75 .loc 1 280 25 view .LVU16 + 76 001c 9A60 str r2, [r3, #8] + 77 .LVL4: + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 78 .loc 1 283 5 is_stmt 1 view .LVU17 + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 79 .loc 1 283 9 is_stmt 0 view .LVU18 + 80 001e 0368 ldr r3, [r0] + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 81 .loc 1 283 26 view .LVU19 + 82 0020 D960 str r1, [r3, #12] + 83 0022 F7E7 b .L1 + 84 .cfi_endproc + 85 .LFE144: + 87 .section .text.HAL_DMAEx_MultiBufferStart,"ax",%progbits + 88 .align 1 + 89 .global HAL_DMAEx_MultiBufferStart + 90 .syntax unified + 91 .thumb + 92 .thumb_func + 94 HAL_DMAEx_MultiBufferStart: + 95 .LVL5: + 96 .LFB141: + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 97 .loc 1 103 1 is_stmt 1 view -0 + 98 .cfi_startproc + 99 @ args = 4, pretend = 0, frame = 0 + 100 @ frame_needed = 0, uses_anonymous_args = 0 + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** HAL_StatusTypeDef status = HAL_OK; + ARM GAS /tmp/ccwTmXyh.s page 8 + + + 101 .loc 1 103 1 is_stmt 0 view .LVU21 + 102 0000 38B5 push {r3, r4, r5, lr} + 103 .LCFI3: + 104 .cfi_def_cfa_offset 16 + 105 .cfi_offset 3, -16 + 106 .cfi_offset 4, -12 + 107 .cfi_offset 5, -8 + 108 .cfi_offset 14, -4 + 109 0002 0446 mov r4, r0 + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 110 .loc 1 104 3 is_stmt 1 view .LVU22 + 111 .LVL6: + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 112 .loc 1 107 3 view .LVU23 + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 113 .loc 1 110 3 view .LVU24 + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 114 .loc 1 110 17 is_stmt 0 view .LVU25 + 115 0004 8068 ldr r0, [r0, #8] + 116 .LVL7: + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 117 .loc 1 110 6 view .LVU26 + 118 0006 8028 cmp r0, #128 + 119 0008 0DD0 beq .L12 + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 120 .loc 1 118 5 is_stmt 1 view .LVU27 + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 121 .loc 1 118 5 view .LVU28 + 122 000a 94F83400 ldrb r0, [r4, #52] @ zero_extendqisi2 + 123 000e 0128 cmp r0, #1 + 124 0010 23D0 beq .L9 + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 125 .loc 1 118 5 discriminator 2 view .LVU29 + 126 0012 0120 movs r0, #1 + 127 0014 84F83400 strb r0, [r4, #52] + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 128 .loc 1 118 5 discriminator 2 view .LVU30 + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 129 .loc 1 120 5 view .LVU31 + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 130 .loc 1 120 35 is_stmt 0 view .LVU32 + 131 0018 94F83500 ldrb r0, [r4, #53] @ zero_extendqisi2 + 132 001c C0B2 uxtb r0, r0 + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 133 .loc 1 120 7 view .LVU33 + 134 001e 0128 cmp r0, #1 + 135 0020 06D0 beq .L13 + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 136 .loc 1 140 14 view .LVU34 + 137 0022 0220 movs r0, #2 + 138 .LVL8: + 139 .L8: + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 140 .loc 1 144 1 view .LVU35 + 141 0024 38BD pop {r3, r4, r5, pc} + 142 .LVL9: + 143 .L12: + ARM GAS /tmp/ccwTmXyh.s page 9 + + + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** status = HAL_ERROR; + 144 .loc 1 112 5 is_stmt 1 view .LVU36 + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** status = HAL_ERROR; + 145 .loc 1 112 21 is_stmt 0 view .LVU37 + 146 0026 4FF48073 mov r3, #256 + 147 .LVL10: + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** status = HAL_ERROR; + 148 .loc 1 112 21 view .LVU38 + 149 002a 6365 str r3, [r4, #84] + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 150 .loc 1 113 5 is_stmt 1 view .LVU39 + 151 .LVL11: + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 152 .loc 1 113 12 is_stmt 0 view .LVU40 + 153 002c 0120 movs r0, #1 + 154 002e F9E7 b .L8 + 155 .LVL12: + 156 .L13: + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 157 .loc 1 123 7 is_stmt 1 view .LVU41 + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 158 .loc 1 123 19 is_stmt 0 view .LVU42 + 159 0030 0220 movs r0, #2 + 160 0032 84F83500 strb r0, [r4, #53] + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 161 .loc 1 126 7 is_stmt 1 view .LVU43 + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 162 .loc 1 126 11 is_stmt 0 view .LVU44 + 163 0036 2568 ldr r5, [r4] + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 164 .loc 1 126 21 view .LVU45 + 165 0038 2868 ldr r0, [r5] + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 166 .loc 1 126 26 view .LVU46 + 167 003a 40F48020 orr r0, r0, #262144 + 168 003e 2860 str r0, [r5] + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 169 .loc 1 129 7 is_stmt 1 view .LVU47 + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 170 .loc 1 129 11 is_stmt 0 view .LVU48 + 171 0040 2068 ldr r0, [r4] + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 172 .loc 1 129 28 view .LVU49 + 173 0042 0361 str r3, [r0, #16] + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 174 .loc 1 132 7 is_stmt 1 view .LVU50 + 175 0044 049B ldr r3, [sp, #16] + 176 .LVL13: + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 177 .loc 1 132 7 is_stmt 0 view .LVU51 + 178 0046 2046 mov r0, r4 + 179 .LVL14: + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 180 .loc 1 132 7 view .LVU52 + 181 0048 FFF7FEFF bl DMA_MultiBufferSetConfig + 182 .LVL15: + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + ARM GAS /tmp/ccwTmXyh.s page 10 + + + 183 .loc 1 135 7 is_stmt 1 view .LVU53 + 184 004c 2268 ldr r2, [r4] + 185 004e 1368 ldr r3, [r2] + 186 0050 43F00103 orr r3, r3, #1 + 187 0054 1360 str r3, [r2] + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 188 .loc 1 104 21 is_stmt 0 view .LVU54 + 189 0056 0020 movs r0, #0 + 190 0058 E4E7 b .L8 + 191 .LVL16: + 192 .L9: + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 193 .loc 1 118 5 discriminator 1 view .LVU55 + 194 005a 0220 movs r0, #2 + 195 005c E2E7 b .L8 + 196 .cfi_endproc + 197 .LFE141: + 199 .section .text.HAL_DMAEx_MultiBufferStart_IT,"ax",%progbits + 200 .align 1 + 201 .global HAL_DMAEx_MultiBufferStart_IT + 202 .syntax unified + 203 .thumb + 204 .thumb_func + 206 HAL_DMAEx_MultiBufferStart_IT: + 207 .LVL17: + 208 .LFB142: + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 209 .loc 1 157 1 is_stmt 1 view -0 + 210 .cfi_startproc + 211 @ args = 4, pretend = 0, frame = 0 + 212 @ frame_needed = 0, uses_anonymous_args = 0 + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 213 .loc 1 157 1 is_stmt 0 view .LVU57 + 214 0000 38B5 push {r3, r4, r5, lr} + 215 .LCFI4: + 216 .cfi_def_cfa_offset 16 + 217 .cfi_offset 3, -16 + 218 .cfi_offset 4, -12 + 219 .cfi_offset 5, -8 + 220 .cfi_offset 14, -4 + 221 0002 0446 mov r4, r0 + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 222 .loc 1 158 3 is_stmt 1 view .LVU58 + 223 .LVL18: + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 224 .loc 1 161 3 view .LVU59 + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 225 .loc 1 164 3 view .LVU60 + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 226 .loc 1 164 17 is_stmt 0 view .LVU61 + 227 0004 8068 ldr r0, [r0, #8] + 228 .LVL19: + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 229 .loc 1 164 6 view .LVU62 + 230 0006 8028 cmp r0, #128 + 231 0008 11D0 beq .L302 + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + ARM GAS /tmp/ccwTmXyh.s page 11 + + + 232 .loc 1 171 3 is_stmt 1 view .LVU63 + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 233 .loc 1 171 3 view .LVU64 + 234 000a 94F83400 ldrb r0, [r4, #52] @ zero_extendqisi2 + 235 000e 0128 cmp r0, #1 + 236 0010 00F06587 beq .L60 + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 237 .loc 1 171 3 discriminator 2 view .LVU65 + 238 0014 0120 movs r0, #1 + 239 0016 84F83400 strb r0, [r4, #52] + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 240 .loc 1 171 3 discriminator 2 view .LVU66 + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 241 .loc 1 173 3 view .LVU67 + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 242 .loc 1 173 33 is_stmt 0 view .LVU68 + 243 001a 94F83500 ldrb r0, [r4, #53] @ zero_extendqisi2 + 244 001e C0B2 uxtb r0, r0 + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 245 .loc 1 173 5 view .LVU69 + 246 0020 0128 cmp r0, #1 + 247 0022 09D0 beq .L303 + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 248 .loc 1 212 5 is_stmt 1 view .LVU70 + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 249 .loc 1 212 5 view .LVU71 + 250 0024 0023 movs r3, #0 + 251 .LVL20: + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 252 .loc 1 212 5 is_stmt 0 view .LVU72 + 253 0026 84F83430 strb r3, [r4, #52] + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 254 .loc 1 212 5 is_stmt 1 view .LVU73 + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 255 .loc 1 215 5 view .LVU74 + 256 .LVL21: + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 257 .loc 1 215 12 is_stmt 0 view .LVU75 + 258 002a 0220 movs r0, #2 + 259 .LVL22: + 260 .L16: + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 261 .loc 1 218 1 view .LVU76 + 262 002c 38BD pop {r3, r4, r5, pc} + 263 .LVL23: + 264 .L302: + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** return HAL_ERROR; + 265 .loc 1 166 5 is_stmt 1 view .LVU77 + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** return HAL_ERROR; + 266 .loc 1 166 21 is_stmt 0 view .LVU78 + 267 002e 4FF48073 mov r3, #256 + 268 .LVL24: + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** return HAL_ERROR; + 269 .loc 1 166 21 view .LVU79 + 270 0032 6365 str r3, [r4, #84] + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 271 .loc 1 167 5 is_stmt 1 view .LVU80 + ARM GAS /tmp/ccwTmXyh.s page 12 + + + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 272 .loc 1 167 12 is_stmt 0 view .LVU81 + 273 0034 0120 movs r0, #1 + 274 0036 F9E7 b .L16 + 275 .LVL25: + 276 .L303: + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 277 .loc 1 176 5 is_stmt 1 view .LVU82 + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 278 .loc 1 176 17 is_stmt 0 view .LVU83 + 279 0038 0220 movs r0, #2 + 280 003a 84F83500 strb r0, [r4, #53] + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 281 .loc 1 179 5 is_stmt 1 view .LVU84 + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 282 .loc 1 179 21 is_stmt 0 view .LVU85 + 283 003e 0020 movs r0, #0 + 284 0040 6065 str r0, [r4, #84] + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 285 .loc 1 182 5 is_stmt 1 view .LVU86 + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 286 .loc 1 182 9 is_stmt 0 view .LVU87 + 287 0042 2568 ldr r5, [r4] + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 288 .loc 1 182 19 view .LVU88 + 289 0044 2868 ldr r0, [r5] + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 290 .loc 1 182 24 view .LVU89 + 291 0046 40F48020 orr r0, r0, #262144 + 292 004a 2860 str r0, [r5] + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 293 .loc 1 185 5 is_stmt 1 view .LVU90 + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 294 .loc 1 185 9 is_stmt 0 view .LVU91 + 295 004c 2068 ldr r0, [r4] + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 296 .loc 1 185 26 view .LVU92 + 297 004e 0361 str r3, [r0, #16] + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 298 .loc 1 188 5 is_stmt 1 view .LVU93 + 299 0050 049B ldr r3, [sp, #16] + 300 .LVL26: + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 301 .loc 1 188 5 is_stmt 0 view .LVU94 + 302 0052 2046 mov r0, r4 + 303 .LVL27: + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 304 .loc 1 188 5 view .LVU95 + 305 0054 FFF7FEFF bl DMA_MultiBufferSetConfig + 306 .LVL28: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 307 .loc 1 191 5 is_stmt 1 view .LVU96 + 308 0058 2368 ldr r3, [r4] + 309 005a A54A ldr r2, .L325 + 310 005c 9342 cmp r3, r2 + 311 005e 40F29880 bls .L18 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + ARM GAS /tmp/ccwTmXyh.s page 13 + + + 312 .loc 1 191 5 is_stmt 0 discriminator 1 view .LVU97 + 313 0062 A2F58962 sub r2, r2, #1096 + 314 0066 9342 cmp r3, r2 + 315 0068 31D0 beq .L61 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 316 .loc 1 191 5 discriminator 3 view .LVU98 + 317 006a 02F58062 add r2, r2, #1024 + 318 006e 9342 cmp r3, r2 + 319 0070 74D0 beq .L62 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 320 .loc 1 191 5 discriminator 5 view .LVU99 + 321 0072 A2F56872 sub r2, r2, #928 + 322 0076 9342 cmp r3, r2 + 323 0078 72D0 beq .L63 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 324 .loc 1 191 5 discriminator 7 view .LVU100 + 325 007a 02F58062 add r2, r2, #1024 + 326 007e 9342 cmp r3, r2 + 327 0080 70D0 beq .L64 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 328 .loc 1 191 5 discriminator 9 view .LVU101 + 329 0082 A2F58962 sub r2, r2, #1096 + 330 0086 9342 cmp r3, r2 + 331 0088 6ED0 beq .L65 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 332 .loc 1 191 5 discriminator 11 view .LVU102 + 333 008a 02F58062 add r2, r2, #1024 + 334 008e 9342 cmp r3, r2 + 335 0090 6DD0 beq .L66 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 336 .loc 1 191 5 discriminator 13 view .LVU103 + 337 0092 A2F56872 sub r2, r2, #928 + 338 0096 9342 cmp r3, r2 + 339 0098 6CD0 beq .L67 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 340 .loc 1 191 5 discriminator 15 view .LVU104 + 341 009a 02F58062 add r2, r2, #1024 + 342 009e 9342 cmp r3, r2 + 343 00a0 6BD0 beq .L68 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 344 .loc 1 191 5 discriminator 17 view .LVU105 + 345 00a2 A2F58962 sub r2, r2, #1096 + 346 00a6 9342 cmp r3, r2 + 347 00a8 6AD0 beq .L69 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 348 .loc 1 191 5 discriminator 19 view .LVU106 + 349 00aa 02F58062 add r2, r2, #1024 + 350 00ae 9342 cmp r3, r2 + 351 00b0 69D0 beq .L70 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 352 .loc 1 191 5 discriminator 21 view .LVU107 + 353 00b2 A2F56872 sub r2, r2, #928 + 354 00b6 9342 cmp r3, r2 + 355 00b8 68D0 beq .L71 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 356 .loc 1 191 5 discriminator 23 view .LVU108 + 357 00ba 02F58062 add r2, r2, #1024 + ARM GAS /tmp/ccwTmXyh.s page 14 + + + 358 00be 9342 cmp r3, r2 + 359 00c0 02D0 beq .L304 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 360 .loc 1 191 5 discriminator 26 view .LVU109 + 361 00c2 4FF00062 mov r2, #134217728 + 362 00c6 03E0 b .L19 + 363 .L304: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 364 .loc 1 191 5 discriminator 25 view .LVU110 + 365 00c8 4FF40012 mov r2, #2097152 + 366 00cc 00E0 b .L19 + 367 .L61: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 368 .loc 1 191 5 discriminator 4 view .LVU111 + 369 00ce 2022 movs r2, #32 + 370 .L19: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 371 .loc 1 191 5 discriminator 50 view .LVU112 + 372 00d0 884B ldr r3, .L325+4 + 373 00d2 DA60 str r2, [r3, #12] + 374 .LVL29: + 375 .L20: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 376 .loc 1 192 5 is_stmt 1 view .LVU113 + 377 00d4 2368 ldr r3, [r4] + 378 00d6 864A ldr r2, .L325 + 379 00d8 9342 cmp r3, r2 + 380 00da 40F2CC81 bls .L26 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 381 .loc 1 192 5 is_stmt 0 discriminator 1 view .LVU114 + 382 00de A2F58962 sub r2, r2, #1096 + 383 00e2 9342 cmp r3, r2 + 384 00e4 00F06581 beq .L109 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 385 .loc 1 192 5 discriminator 3 view .LVU115 + 386 00e8 02F58062 add r2, r2, #1024 + 387 00ec 9342 cmp r3, r2 + 388 00ee 00F0A781 beq .L110 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 389 .loc 1 192 5 discriminator 5 view .LVU116 + 390 00f2 A2F56872 sub r2, r2, #928 + 391 00f6 9342 cmp r3, r2 + 392 00f8 00F0A481 beq .L111 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 393 .loc 1 192 5 discriminator 7 view .LVU117 + 394 00fc 02F58062 add r2, r2, #1024 + 395 0100 9342 cmp r3, r2 + 396 0102 00F0A181 beq .L112 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 397 .loc 1 192 5 discriminator 9 view .LVU118 + 398 0106 A2F58962 sub r2, r2, #1096 + 399 010a 9342 cmp r3, r2 + 400 010c 00F09E81 beq .L113 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 401 .loc 1 192 5 discriminator 11 view .LVU119 + 402 0110 02F58062 add r2, r2, #1024 + 403 0114 9342 cmp r3, r2 + ARM GAS /tmp/ccwTmXyh.s page 15 + + + 404 0116 00F09C81 beq .L114 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 405 .loc 1 192 5 discriminator 13 view .LVU120 + 406 011a A2F56872 sub r2, r2, #928 + 407 011e 9342 cmp r3, r2 + 408 0120 00F09A81 beq .L115 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 409 .loc 1 192 5 discriminator 15 view .LVU121 + 410 0124 02F58062 add r2, r2, #1024 + 411 0128 9342 cmp r3, r2 + 412 012a 00F09881 beq .L116 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 413 .loc 1 192 5 discriminator 17 view .LVU122 + 414 012e A2F58962 sub r2, r2, #1096 + 415 0132 9342 cmp r3, r2 + 416 0134 00F09681 beq .L117 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 417 .loc 1 192 5 discriminator 19 view .LVU123 + 418 0138 02F58062 add r2, r2, #1024 + 419 013c 9342 cmp r3, r2 + 420 013e 00F09481 beq .L118 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 421 .loc 1 192 5 discriminator 21 view .LVU124 + 422 0142 A2F56872 sub r2, r2, #928 + 423 0146 9342 cmp r3, r2 + 424 0148 00F09281 beq .L119 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 425 .loc 1 192 5 discriminator 23 view .LVU125 + 426 014c 02F58062 add r2, r2, #1024 + 427 0150 9342 cmp r3, r2 + 428 0152 00F02B81 beq .L305 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 429 .loc 1 192 5 discriminator 26 view .LVU126 + 430 0156 4FF08062 mov r2, #67108864 + 431 015a 2BE1 b .L27 + 432 .LVL30: + 433 .L62: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 434 .loc 1 191 5 discriminator 6 view .LVU127 + 435 015c 2022 movs r2, #32 + 436 015e B7E7 b .L19 + 437 .L63: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 438 .loc 1 191 5 discriminator 8 view .LVU128 + 439 0160 2022 movs r2, #32 + 440 0162 B5E7 b .L19 + 441 .L64: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 442 .loc 1 191 5 discriminator 10 view .LVU129 + 443 0164 2022 movs r2, #32 + 444 0166 B3E7 b .L19 + 445 .L65: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 446 .loc 1 191 5 discriminator 12 view .LVU130 + 447 0168 4FF40062 mov r2, #2048 + 448 016c B0E7 b .L19 + 449 .L66: + ARM GAS /tmp/ccwTmXyh.s page 16 + + + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 450 .loc 1 191 5 discriminator 14 view .LVU131 + 451 016e 4FF40062 mov r2, #2048 + 452 0172 ADE7 b .L19 + 453 .L67: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 454 .loc 1 191 5 discriminator 16 view .LVU132 + 455 0174 4FF40062 mov r2, #2048 + 456 0178 AAE7 b .L19 + 457 .L68: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 458 .loc 1 191 5 discriminator 18 view .LVU133 + 459 017a 4FF40062 mov r2, #2048 + 460 017e A7E7 b .L19 + 461 .L69: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 462 .loc 1 191 5 discriminator 20 view .LVU134 + 463 0180 4FF40012 mov r2, #2097152 + 464 0184 A4E7 b .L19 + 465 .L70: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 466 .loc 1 191 5 discriminator 22 view .LVU135 + 467 0186 4FF40012 mov r2, #2097152 + 468 018a A1E7 b .L19 + 469 .L71: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 470 .loc 1 191 5 discriminator 24 view .LVU136 + 471 018c 4FF40012 mov r2, #2097152 + 472 0190 9EE7 b .L19 + 473 .L18: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 474 .loc 1 191 5 discriminator 2 view .LVU137 + 475 0192 594A ldr r2, .L325+8 + 476 0194 9342 cmp r3, r2 + 477 0196 53D9 bls .L21 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 478 .loc 1 191 5 discriminator 51 view .LVU138 + 479 0198 A83A subs r2, r2, #168 + 480 019a 9342 cmp r3, r2 + 481 019c 31D0 beq .L73 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 482 .loc 1 191 5 discriminator 53 view .LVU139 + 483 019e 02F58062 add r2, r2, #1024 + 484 01a2 9342 cmp r3, r2 + 485 01a4 31D0 beq .L74 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 486 .loc 1 191 5 discriminator 55 view .LVU140 + 487 01a6 A2F56872 sub r2, r2, #928 + 488 01aa 9342 cmp r3, r2 + 489 01ac 2FD0 beq .L75 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 490 .loc 1 191 5 discriminator 57 view .LVU141 + 491 01ae 02F58062 add r2, r2, #1024 + 492 01b2 9342 cmp r3, r2 + 493 01b4 2DD0 beq .L76 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 494 .loc 1 191 5 discriminator 59 view .LVU142 + ARM GAS /tmp/ccwTmXyh.s page 17 + + + 495 01b6 A2F58962 sub r2, r2, #1096 + 496 01ba 9342 cmp r3, r2 + 497 01bc 2BD0 beq .L77 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 498 .loc 1 191 5 discriminator 61 view .LVU143 + 499 01be 02F58062 add r2, r2, #1024 + 500 01c2 9342 cmp r3, r2 + 501 01c4 2AD0 beq .L78 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 502 .loc 1 191 5 discriminator 63 view .LVU144 + 503 01c6 A2F56872 sub r2, r2, #928 + 504 01ca 9342 cmp r3, r2 + 505 01cc 29D0 beq .L79 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 506 .loc 1 191 5 discriminator 65 view .LVU145 + 507 01ce 02F58062 add r2, r2, #1024 + 508 01d2 9342 cmp r3, r2 + 509 01d4 28D0 beq .L80 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 510 .loc 1 191 5 discriminator 67 view .LVU146 + 511 01d6 A2F58962 sub r2, r2, #1096 + 512 01da 9342 cmp r3, r2 + 513 01dc 27D0 beq .L81 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 514 .loc 1 191 5 discriminator 69 view .LVU147 + 515 01de 02F58062 add r2, r2, #1024 + 516 01e2 9342 cmp r3, r2 + 517 01e4 26D0 beq .L82 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 518 .loc 1 191 5 discriminator 71 view .LVU148 + 519 01e6 A2F56872 sub r2, r2, #928 + 520 01ea 9342 cmp r3, r2 + 521 01ec 25D0 beq .L83 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 522 .loc 1 191 5 discriminator 73 view .LVU149 + 523 01ee 02F58062 add r2, r2, #1024 + 524 01f2 9342 cmp r3, r2 + 525 01f4 02D0 beq .L306 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 526 .loc 1 191 5 discriminator 76 view .LVU150 + 527 01f6 4FF00062 mov r2, #134217728 + 528 01fa 03E0 b .L22 + 529 .L306: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 530 .loc 1 191 5 discriminator 75 view .LVU151 + 531 01fc 4FF40012 mov r2, #2097152 + 532 0200 00E0 b .L22 + 533 .L73: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 534 .loc 1 191 5 discriminator 54 view .LVU152 + 535 0202 2022 movs r2, #32 + 536 .L22: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 537 .loc 1 191 5 discriminator 100 view .LVU153 + 538 0204 3B4B ldr r3, .L325+4 + 539 0206 9A60 str r2, [r3, #8] + 540 .LVL31: + ARM GAS /tmp/ccwTmXyh.s page 18 + + + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 541 .loc 1 191 5 discriminator 100 view .LVU154 + 542 0208 64E7 b .L20 + 543 .LVL32: + 544 .L74: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 545 .loc 1 191 5 discriminator 56 view .LVU155 + 546 020a 2022 movs r2, #32 + 547 020c FAE7 b .L22 + 548 .L75: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 549 .loc 1 191 5 discriminator 58 view .LVU156 + 550 020e 2022 movs r2, #32 + 551 0210 F8E7 b .L22 + 552 .L76: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 553 .loc 1 191 5 discriminator 60 view .LVU157 + 554 0212 2022 movs r2, #32 + 555 0214 F6E7 b .L22 + 556 .L77: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 557 .loc 1 191 5 discriminator 62 view .LVU158 + 558 0216 4FF40062 mov r2, #2048 + 559 021a F3E7 b .L22 + 560 .L78: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 561 .loc 1 191 5 discriminator 64 view .LVU159 + 562 021c 4FF40062 mov r2, #2048 + 563 0220 F0E7 b .L22 + 564 .L79: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 565 .loc 1 191 5 discriminator 66 view .LVU160 + 566 0222 4FF40062 mov r2, #2048 + 567 0226 EDE7 b .L22 + 568 .L80: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 569 .loc 1 191 5 discriminator 68 view .LVU161 + 570 0228 4FF40062 mov r2, #2048 + 571 022c EAE7 b .L22 + 572 .L81: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 573 .loc 1 191 5 discriminator 70 view .LVU162 + 574 022e 4FF40012 mov r2, #2097152 + 575 0232 E7E7 b .L22 + 576 .L82: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 577 .loc 1 191 5 discriminator 72 view .LVU163 + 578 0234 4FF40012 mov r2, #2097152 + 579 0238 E4E7 b .L22 + 580 .L83: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 581 .loc 1 191 5 discriminator 74 view .LVU164 + 582 023a 4FF40012 mov r2, #2097152 + 583 023e E1E7 b .L22 + 584 .L21: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 585 .loc 1 191 5 discriminator 52 view .LVU165 + ARM GAS /tmp/ccwTmXyh.s page 19 + + + 586 0240 2E4A ldr r2, .L325+12 + 587 0242 9342 cmp r3, r2 + 588 0244 5ED9 bls .L23 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 589 .loc 1 191 5 discriminator 102 view .LVU166 + 590 0246 483A subs r2, r2, #72 + 591 0248 9342 cmp r3, r2 + 592 024a 31D0 beq .L85 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 593 .loc 1 191 5 discriminator 104 view .LVU167 + 594 024c 02F58062 add r2, r2, #1024 + 595 0250 9342 cmp r3, r2 + 596 0252 31D0 beq .L86 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 597 .loc 1 191 5 discriminator 106 view .LVU168 + 598 0254 A2F56872 sub r2, r2, #928 + 599 0258 9342 cmp r3, r2 + 600 025a 2FD0 beq .L87 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 601 .loc 1 191 5 discriminator 108 view .LVU169 + 602 025c 02F58062 add r2, r2, #1024 + 603 0260 9342 cmp r3, r2 + 604 0262 2DD0 beq .L88 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 605 .loc 1 191 5 discriminator 110 view .LVU170 + 606 0264 A2F58962 sub r2, r2, #1096 + 607 0268 9342 cmp r3, r2 + 608 026a 2BD0 beq .L89 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 609 .loc 1 191 5 discriminator 112 view .LVU171 + 610 026c 02F58062 add r2, r2, #1024 + 611 0270 9342 cmp r3, r2 + 612 0272 2AD0 beq .L90 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 613 .loc 1 191 5 discriminator 114 view .LVU172 + 614 0274 A2F56872 sub r2, r2, #928 + 615 0278 9342 cmp r3, r2 + 616 027a 29D0 beq .L91 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 617 .loc 1 191 5 discriminator 116 view .LVU173 + 618 027c 02F58062 add r2, r2, #1024 + 619 0280 9342 cmp r3, r2 + 620 0282 28D0 beq .L92 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 621 .loc 1 191 5 discriminator 118 view .LVU174 + 622 0284 A2F58962 sub r2, r2, #1096 + 623 0288 9342 cmp r3, r2 + 624 028a 27D0 beq .L93 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 625 .loc 1 191 5 discriminator 120 view .LVU175 + 626 028c 02F58062 add r2, r2, #1024 + 627 0290 9342 cmp r3, r2 + 628 0292 26D0 beq .L94 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 629 .loc 1 191 5 discriminator 122 view .LVU176 + 630 0294 A2F56872 sub r2, r2, #928 + 631 0298 9342 cmp r3, r2 + ARM GAS /tmp/ccwTmXyh.s page 20 + + + 632 029a 25D0 beq .L95 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 633 .loc 1 191 5 discriminator 124 view .LVU177 + 634 029c 02F58062 add r2, r2, #1024 + 635 02a0 9342 cmp r3, r2 + 636 02a2 02D0 beq .L307 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 637 .loc 1 191 5 discriminator 127 view .LVU178 + 638 02a4 4FF00063 mov r3, #134217728 + 639 02a8 03E0 b .L24 + 640 .L307: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 641 .loc 1 191 5 discriminator 126 view .LVU179 + 642 02aa 4FF40013 mov r3, #2097152 + 643 02ae 00E0 b .L24 + 644 .L85: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 645 .loc 1 191 5 discriminator 105 view .LVU180 + 646 02b0 2023 movs r3, #32 + 647 .L24: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 648 .loc 1 191 5 discriminator 151 view .LVU181 + 649 02b2 134A ldr r2, .L325+16 + 650 02b4 D360 str r3, [r2, #12] + 651 .LVL33: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 652 .loc 1 191 5 discriminator 151 view .LVU182 + 653 02b6 0DE7 b .L20 + 654 .LVL34: + 655 .L86: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 656 .loc 1 191 5 discriminator 107 view .LVU183 + 657 02b8 2023 movs r3, #32 + 658 02ba FAE7 b .L24 + 659 .L87: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 660 .loc 1 191 5 discriminator 109 view .LVU184 + 661 02bc 2023 movs r3, #32 + 662 02be F8E7 b .L24 + 663 .L88: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 664 .loc 1 191 5 discriminator 111 view .LVU185 + 665 02c0 2023 movs r3, #32 + 666 02c2 F6E7 b .L24 + 667 .L89: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 668 .loc 1 191 5 discriminator 113 view .LVU186 + 669 02c4 4FF40063 mov r3, #2048 + 670 02c8 F3E7 b .L24 + 671 .L90: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 672 .loc 1 191 5 discriminator 115 view .LVU187 + 673 02ca 4FF40063 mov r3, #2048 + 674 02ce F0E7 b .L24 + 675 .L91: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 676 .loc 1 191 5 discriminator 117 view .LVU188 + ARM GAS /tmp/ccwTmXyh.s page 21 + + + 677 02d0 4FF40063 mov r3, #2048 + 678 02d4 EDE7 b .L24 + 679 .L92: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 680 .loc 1 191 5 discriminator 119 view .LVU189 + 681 02d6 4FF40063 mov r3, #2048 + 682 02da EAE7 b .L24 + 683 .L93: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 684 .loc 1 191 5 discriminator 121 view .LVU190 + 685 02dc 4FF40013 mov r3, #2097152 + 686 02e0 E7E7 b .L24 + 687 .L94: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 688 .loc 1 191 5 discriminator 123 view .LVU191 + 689 02e2 4FF40013 mov r3, #2097152 + 690 02e6 E4E7 b .L24 + 691 .L95: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 692 .loc 1 191 5 discriminator 125 view .LVU192 + 693 02e8 4FF40013 mov r3, #2097152 + 694 02ec E1E7 b .L24 + 695 .L326: + 696 02ee 00BF .align 2 + 697 .L325: + 698 02f0 58640240 .word 1073898584 + 699 02f4 00640240 .word 1073898496 + 700 02f8 B8600240 .word 1073897656 + 701 02fc 58600240 .word 1073897560 + 702 0300 00600240 .word 1073897472 + 703 .L23: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 704 .loc 1 191 5 discriminator 103 view .LVU193 + 705 0304 B14A ldr r2, .L327 + 706 0306 9342 cmp r3, r2 + 707 0308 31D0 beq .L97 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 708 .loc 1 191 5 discriminator 153 view .LVU194 + 709 030a 02F58062 add r2, r2, #1024 + 710 030e 9342 cmp r3, r2 + 711 0310 31D0 beq .L98 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 712 .loc 1 191 5 discriminator 155 view .LVU195 + 713 0312 A2F56872 sub r2, r2, #928 + 714 0316 9342 cmp r3, r2 + 715 0318 2FD0 beq .L99 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 716 .loc 1 191 5 discriminator 157 view .LVU196 + 717 031a 02F58062 add r2, r2, #1024 + 718 031e 9342 cmp r3, r2 + 719 0320 2DD0 beq .L100 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 720 .loc 1 191 5 discriminator 159 view .LVU197 + 721 0322 A2F58962 sub r2, r2, #1096 + 722 0326 9342 cmp r3, r2 + 723 0328 2BD0 beq .L101 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + ARM GAS /tmp/ccwTmXyh.s page 22 + + + 724 .loc 1 191 5 discriminator 161 view .LVU198 + 725 032a 02F58062 add r2, r2, #1024 + 726 032e 9342 cmp r3, r2 + 727 0330 2AD0 beq .L102 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 728 .loc 1 191 5 discriminator 163 view .LVU199 + 729 0332 A2F56872 sub r2, r2, #928 + 730 0336 9342 cmp r3, r2 + 731 0338 29D0 beq .L103 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 732 .loc 1 191 5 discriminator 165 view .LVU200 + 733 033a 02F58062 add r2, r2, #1024 + 734 033e 9342 cmp r3, r2 + 735 0340 28D0 beq .L104 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 736 .loc 1 191 5 discriminator 167 view .LVU201 + 737 0342 A2F58962 sub r2, r2, #1096 + 738 0346 9342 cmp r3, r2 + 739 0348 27D0 beq .L105 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 740 .loc 1 191 5 discriminator 169 view .LVU202 + 741 034a 02F58062 add r2, r2, #1024 + 742 034e 9342 cmp r3, r2 + 743 0350 26D0 beq .L106 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 744 .loc 1 191 5 discriminator 171 view .LVU203 + 745 0352 A2F56872 sub r2, r2, #928 + 746 0356 9342 cmp r3, r2 + 747 0358 25D0 beq .L107 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 748 .loc 1 191 5 discriminator 173 view .LVU204 + 749 035a 02F58062 add r2, r2, #1024 + 750 035e 9342 cmp r3, r2 + 751 0360 02D0 beq .L308 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 752 .loc 1 191 5 discriminator 176 view .LVU205 + 753 0362 4FF00063 mov r3, #134217728 + 754 0366 03E0 b .L25 + 755 .L308: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 756 .loc 1 191 5 discriminator 175 view .LVU206 + 757 0368 4FF40013 mov r3, #2097152 + 758 036c 00E0 b .L25 + 759 .L97: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 760 .loc 1 191 5 discriminator 154 view .LVU207 + 761 036e 2023 movs r3, #32 + 762 .L25: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 763 .loc 1 191 5 discriminator 200 view .LVU208 + 764 0370 974A ldr r2, .L327+4 + 765 0372 9360 str r3, [r2, #8] + 766 .LVL35: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 767 .loc 1 191 5 discriminator 200 view .LVU209 + 768 0374 AEE6 b .L20 + 769 .LVL36: + ARM GAS /tmp/ccwTmXyh.s page 23 + + + 770 .L98: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 771 .loc 1 191 5 discriminator 156 view .LVU210 + 772 0376 2023 movs r3, #32 + 773 0378 FAE7 b .L25 + 774 .L99: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 775 .loc 1 191 5 discriminator 158 view .LVU211 + 776 037a 2023 movs r3, #32 + 777 037c F8E7 b .L25 + 778 .L100: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 779 .loc 1 191 5 discriminator 160 view .LVU212 + 780 037e 2023 movs r3, #32 + 781 0380 F6E7 b .L25 + 782 .L101: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 783 .loc 1 191 5 discriminator 162 view .LVU213 + 784 0382 4FF40063 mov r3, #2048 + 785 0386 F3E7 b .L25 + 786 .L102: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 787 .loc 1 191 5 discriminator 164 view .LVU214 + 788 0388 4FF40063 mov r3, #2048 + 789 038c F0E7 b .L25 + 790 .L103: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 791 .loc 1 191 5 discriminator 166 view .LVU215 + 792 038e 4FF40063 mov r3, #2048 + 793 0392 EDE7 b .L25 + 794 .L104: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 795 .loc 1 191 5 discriminator 168 view .LVU216 + 796 0394 4FF40063 mov r3, #2048 + 797 0398 EAE7 b .L25 + 798 .L105: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 799 .loc 1 191 5 discriminator 170 view .LVU217 + 800 039a 4FF40013 mov r3, #2097152 + 801 039e E7E7 b .L25 + 802 .L106: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 803 .loc 1 191 5 discriminator 172 view .LVU218 + 804 03a0 4FF40013 mov r3, #2097152 + 805 03a4 E4E7 b .L25 + 806 .L107: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + 807 .loc 1 191 5 discriminator 174 view .LVU219 + 808 03a6 4FF40013 mov r3, #2097152 + 809 03aa E1E7 b .L25 + 810 .LVL37: + 811 .L305: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 812 .loc 1 192 5 discriminator 25 view .LVU220 + 813 03ac 4FF48012 mov r2, #1048576 + 814 03b0 00E0 b .L27 + 815 .L109: + ARM GAS /tmp/ccwTmXyh.s page 24 + + + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 816 .loc 1 192 5 discriminator 4 view .LVU221 + 817 03b2 1022 movs r2, #16 + 818 .L27: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 819 .loc 1 192 5 discriminator 50 view .LVU222 + 820 03b4 874B ldr r3, .L327+8 + 821 03b6 DA60 str r2, [r3, #12] + 822 .L28: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 823 .loc 1 193 5 is_stmt 1 view .LVU223 + 824 03b8 2368 ldr r3, [r4] + 825 03ba 874A ldr r2, .L327+12 + 826 03bc 9342 cmp r3, r2 + 827 03be 40F2CD81 bls .L34 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 828 .loc 1 193 5 is_stmt 0 discriminator 1 view .LVU224 + 829 03c2 A2F58962 sub r2, r2, #1096 + 830 03c6 9342 cmp r3, r2 + 831 03c8 00F06681 beq .L157 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 832 .loc 1 193 5 discriminator 3 view .LVU225 + 833 03cc 02F58062 add r2, r2, #1024 + 834 03d0 9342 cmp r3, r2 + 835 03d2 00F0A881 beq .L158 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 836 .loc 1 193 5 discriminator 5 view .LVU226 + 837 03d6 A2F56872 sub r2, r2, #928 + 838 03da 9342 cmp r3, r2 + 839 03dc 00F0A581 beq .L159 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 840 .loc 1 193 5 discriminator 7 view .LVU227 + 841 03e0 02F58062 add r2, r2, #1024 + 842 03e4 9342 cmp r3, r2 + 843 03e6 00F0A281 beq .L160 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 844 .loc 1 193 5 discriminator 9 view .LVU228 + 845 03ea A2F58962 sub r2, r2, #1096 + 846 03ee 9342 cmp r3, r2 + 847 03f0 00F09F81 beq .L161 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 848 .loc 1 193 5 discriminator 11 view .LVU229 + 849 03f4 02F58062 add r2, r2, #1024 + 850 03f8 9342 cmp r3, r2 + 851 03fa 00F09D81 beq .L162 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 852 .loc 1 193 5 discriminator 13 view .LVU230 + 853 03fe A2F56872 sub r2, r2, #928 + 854 0402 9342 cmp r3, r2 + 855 0404 00F09B81 beq .L163 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 856 .loc 1 193 5 discriminator 15 view .LVU231 + 857 0408 02F58062 add r2, r2, #1024 + 858 040c 9342 cmp r3, r2 + 859 040e 00F09981 beq .L164 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 860 .loc 1 193 5 discriminator 17 view .LVU232 + ARM GAS /tmp/ccwTmXyh.s page 25 + + + 861 0412 A2F58962 sub r2, r2, #1096 + 862 0416 9342 cmp r3, r2 + 863 0418 00F09781 beq .L165 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 864 .loc 1 193 5 discriminator 19 view .LVU233 + 865 041c 02F58062 add r2, r2, #1024 + 866 0420 9342 cmp r3, r2 + 867 0422 00F09581 beq .L166 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 868 .loc 1 193 5 discriminator 21 view .LVU234 + 869 0426 A2F56872 sub r2, r2, #928 + 870 042a 9342 cmp r3, r2 + 871 042c 00F09381 beq .L167 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 872 .loc 1 193 5 discriminator 23 view .LVU235 + 873 0430 02F58062 add r2, r2, #1024 + 874 0434 9342 cmp r3, r2 + 875 0436 00F02C81 beq .L309 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 876 .loc 1 193 5 discriminator 26 view .LVU236 + 877 043a 4FF00072 mov r2, #33554432 + 878 043e 2CE1 b .L35 + 879 .L110: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 880 .loc 1 192 5 discriminator 6 view .LVU237 + 881 0440 1022 movs r2, #16 + 882 0442 B7E7 b .L27 + 883 .L111: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 884 .loc 1 192 5 discriminator 8 view .LVU238 + 885 0444 1022 movs r2, #16 + 886 0446 B5E7 b .L27 + 887 .L112: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 888 .loc 1 192 5 discriminator 10 view .LVU239 + 889 0448 1022 movs r2, #16 + 890 044a B3E7 b .L27 + 891 .L113: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 892 .loc 1 192 5 discriminator 12 view .LVU240 + 893 044c 4FF48062 mov r2, #1024 + 894 0450 B0E7 b .L27 + 895 .L114: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 896 .loc 1 192 5 discriminator 14 view .LVU241 + 897 0452 4FF48062 mov r2, #1024 + 898 0456 ADE7 b .L27 + 899 .L115: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 900 .loc 1 192 5 discriminator 16 view .LVU242 + 901 0458 4FF48062 mov r2, #1024 + 902 045c AAE7 b .L27 + 903 .L116: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 904 .loc 1 192 5 discriminator 18 view .LVU243 + 905 045e 4FF48062 mov r2, #1024 + 906 0462 A7E7 b .L27 + ARM GAS /tmp/ccwTmXyh.s page 26 + + + 907 .L117: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 908 .loc 1 192 5 discriminator 20 view .LVU244 + 909 0464 4FF48012 mov r2, #1048576 + 910 0468 A4E7 b .L27 + 911 .L118: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 912 .loc 1 192 5 discriminator 22 view .LVU245 + 913 046a 4FF48012 mov r2, #1048576 + 914 046e A1E7 b .L27 + 915 .L119: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 916 .loc 1 192 5 discriminator 24 view .LVU246 + 917 0470 4FF48012 mov r2, #1048576 + 918 0474 9EE7 b .L27 + 919 .L26: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 920 .loc 1 192 5 discriminator 2 view .LVU247 + 921 0476 594A ldr r2, .L327+16 + 922 0478 9342 cmp r3, r2 + 923 047a 53D9 bls .L29 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 924 .loc 1 192 5 discriminator 51 view .LVU248 + 925 047c A83A subs r2, r2, #168 + 926 047e 9342 cmp r3, r2 + 927 0480 31D0 beq .L121 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 928 .loc 1 192 5 discriminator 53 view .LVU249 + 929 0482 02F58062 add r2, r2, #1024 + 930 0486 9342 cmp r3, r2 + 931 0488 31D0 beq .L122 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 932 .loc 1 192 5 discriminator 55 view .LVU250 + 933 048a A2F56872 sub r2, r2, #928 + 934 048e 9342 cmp r3, r2 + 935 0490 2FD0 beq .L123 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 936 .loc 1 192 5 discriminator 57 view .LVU251 + 937 0492 02F58062 add r2, r2, #1024 + 938 0496 9342 cmp r3, r2 + 939 0498 2DD0 beq .L124 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 940 .loc 1 192 5 discriminator 59 view .LVU252 + 941 049a A2F58962 sub r2, r2, #1096 + 942 049e 9342 cmp r3, r2 + 943 04a0 2BD0 beq .L125 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 944 .loc 1 192 5 discriminator 61 view .LVU253 + 945 04a2 02F58062 add r2, r2, #1024 + 946 04a6 9342 cmp r3, r2 + 947 04a8 2AD0 beq .L126 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 948 .loc 1 192 5 discriminator 63 view .LVU254 + 949 04aa A2F56872 sub r2, r2, #928 + 950 04ae 9342 cmp r3, r2 + 951 04b0 29D0 beq .L127 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + ARM GAS /tmp/ccwTmXyh.s page 27 + + + 952 .loc 1 192 5 discriminator 65 view .LVU255 + 953 04b2 02F58062 add r2, r2, #1024 + 954 04b6 9342 cmp r3, r2 + 955 04b8 28D0 beq .L128 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 956 .loc 1 192 5 discriminator 67 view .LVU256 + 957 04ba A2F58962 sub r2, r2, #1096 + 958 04be 9342 cmp r3, r2 + 959 04c0 27D0 beq .L129 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 960 .loc 1 192 5 discriminator 69 view .LVU257 + 961 04c2 02F58062 add r2, r2, #1024 + 962 04c6 9342 cmp r3, r2 + 963 04c8 26D0 beq .L130 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 964 .loc 1 192 5 discriminator 71 view .LVU258 + 965 04ca A2F56872 sub r2, r2, #928 + 966 04ce 9342 cmp r3, r2 + 967 04d0 25D0 beq .L131 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 968 .loc 1 192 5 discriminator 73 view .LVU259 + 969 04d2 02F58062 add r2, r2, #1024 + 970 04d6 9342 cmp r3, r2 + 971 04d8 02D0 beq .L310 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 972 .loc 1 192 5 discriminator 76 view .LVU260 + 973 04da 4FF08062 mov r2, #67108864 + 974 04de 03E0 b .L30 + 975 .L310: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 976 .loc 1 192 5 discriminator 75 view .LVU261 + 977 04e0 4FF48012 mov r2, #1048576 + 978 04e4 00E0 b .L30 + 979 .L121: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 980 .loc 1 192 5 discriminator 54 view .LVU262 + 981 04e6 1022 movs r2, #16 + 982 .L30: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 983 .loc 1 192 5 discriminator 100 view .LVU263 + 984 04e8 3A4B ldr r3, .L327+8 + 985 04ea 9A60 str r2, [r3, #8] + 986 04ec 64E7 b .L28 + 987 .L122: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 988 .loc 1 192 5 discriminator 56 view .LVU264 + 989 04ee 1022 movs r2, #16 + 990 04f0 FAE7 b .L30 + 991 .L123: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 992 .loc 1 192 5 discriminator 58 view .LVU265 + 993 04f2 1022 movs r2, #16 + 994 04f4 F8E7 b .L30 + 995 .L124: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 996 .loc 1 192 5 discriminator 60 view .LVU266 + 997 04f6 1022 movs r2, #16 + ARM GAS /tmp/ccwTmXyh.s page 28 + + + 998 04f8 F6E7 b .L30 + 999 .L125: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1000 .loc 1 192 5 discriminator 62 view .LVU267 + 1001 04fa 4FF48062 mov r2, #1024 + 1002 04fe F3E7 b .L30 + 1003 .L126: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1004 .loc 1 192 5 discriminator 64 view .LVU268 + 1005 0500 4FF48062 mov r2, #1024 + 1006 0504 F0E7 b .L30 + 1007 .L127: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1008 .loc 1 192 5 discriminator 66 view .LVU269 + 1009 0506 4FF48062 mov r2, #1024 + 1010 050a EDE7 b .L30 + 1011 .L128: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1012 .loc 1 192 5 discriminator 68 view .LVU270 + 1013 050c 4FF48062 mov r2, #1024 + 1014 0510 EAE7 b .L30 + 1015 .L129: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1016 .loc 1 192 5 discriminator 70 view .LVU271 + 1017 0512 4FF48012 mov r2, #1048576 + 1018 0516 E7E7 b .L30 + 1019 .L130: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1020 .loc 1 192 5 discriminator 72 view .LVU272 + 1021 0518 4FF48012 mov r2, #1048576 + 1022 051c E4E7 b .L30 + 1023 .L131: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1024 .loc 1 192 5 discriminator 74 view .LVU273 + 1025 051e 4FF48012 mov r2, #1048576 + 1026 0522 E1E7 b .L30 + 1027 .L29: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1028 .loc 1 192 5 discriminator 52 view .LVU274 + 1029 0524 2E4A ldr r2, .L327+20 + 1030 0526 9342 cmp r3, r2 + 1031 0528 5FD9 bls .L31 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1032 .loc 1 192 5 discriminator 102 view .LVU275 + 1033 052a 483A subs r2, r2, #72 + 1034 052c 9342 cmp r3, r2 + 1035 052e 31D0 beq .L133 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1036 .loc 1 192 5 discriminator 104 view .LVU276 + 1037 0530 02F58062 add r2, r2, #1024 + 1038 0534 9342 cmp r3, r2 + 1039 0536 31D0 beq .L134 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1040 .loc 1 192 5 discriminator 106 view .LVU277 + 1041 0538 A2F56872 sub r2, r2, #928 + 1042 053c 9342 cmp r3, r2 + 1043 053e 2FD0 beq .L135 + ARM GAS /tmp/ccwTmXyh.s page 29 + + + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1044 .loc 1 192 5 discriminator 108 view .LVU278 + 1045 0540 02F58062 add r2, r2, #1024 + 1046 0544 9342 cmp r3, r2 + 1047 0546 2DD0 beq .L136 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1048 .loc 1 192 5 discriminator 110 view .LVU279 + 1049 0548 A2F58962 sub r2, r2, #1096 + 1050 054c 9342 cmp r3, r2 + 1051 054e 2BD0 beq .L137 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1052 .loc 1 192 5 discriminator 112 view .LVU280 + 1053 0550 02F58062 add r2, r2, #1024 + 1054 0554 9342 cmp r3, r2 + 1055 0556 2AD0 beq .L138 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1056 .loc 1 192 5 discriminator 114 view .LVU281 + 1057 0558 A2F56872 sub r2, r2, #928 + 1058 055c 9342 cmp r3, r2 + 1059 055e 29D0 beq .L139 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1060 .loc 1 192 5 discriminator 116 view .LVU282 + 1061 0560 02F58062 add r2, r2, #1024 + 1062 0564 9342 cmp r3, r2 + 1063 0566 28D0 beq .L140 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1064 .loc 1 192 5 discriminator 118 view .LVU283 + 1065 0568 A2F58962 sub r2, r2, #1096 + 1066 056c 9342 cmp r3, r2 + 1067 056e 27D0 beq .L141 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1068 .loc 1 192 5 discriminator 120 view .LVU284 + 1069 0570 02F58062 add r2, r2, #1024 + 1070 0574 9342 cmp r3, r2 + 1071 0576 26D0 beq .L142 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1072 .loc 1 192 5 discriminator 122 view .LVU285 + 1073 0578 A2F56872 sub r2, r2, #928 + 1074 057c 9342 cmp r3, r2 + 1075 057e 31D0 beq .L143 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1076 .loc 1 192 5 discriminator 124 view .LVU286 + 1077 0580 02F58062 add r2, r2, #1024 + 1078 0584 9342 cmp r3, r2 + 1079 0586 02D0 beq .L311 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1080 .loc 1 192 5 discriminator 127 view .LVU287 + 1081 0588 4FF08063 mov r3, #67108864 + 1082 058c 03E0 b .L32 + 1083 .L311: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1084 .loc 1 192 5 discriminator 126 view .LVU288 + 1085 058e 4FF48013 mov r3, #1048576 + 1086 0592 00E0 b .L32 + 1087 .L133: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1088 .loc 1 192 5 discriminator 105 view .LVU289 + ARM GAS /tmp/ccwTmXyh.s page 30 + + + 1089 0594 1023 movs r3, #16 + 1090 .L32: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1091 .loc 1 192 5 discriminator 151 view .LVU290 + 1092 0596 0E4A ldr r2, .L327+4 + 1093 0598 D360 str r3, [r2, #12] + 1094 059a 0DE7 b .L28 + 1095 .L134: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1096 .loc 1 192 5 discriminator 107 view .LVU291 + 1097 059c 1023 movs r3, #16 + 1098 059e FAE7 b .L32 + 1099 .L135: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1100 .loc 1 192 5 discriminator 109 view .LVU292 + 1101 05a0 1023 movs r3, #16 + 1102 05a2 F8E7 b .L32 + 1103 .L136: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1104 .loc 1 192 5 discriminator 111 view .LVU293 + 1105 05a4 1023 movs r3, #16 + 1106 05a6 F6E7 b .L32 + 1107 .L137: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1108 .loc 1 192 5 discriminator 113 view .LVU294 + 1109 05a8 4FF48063 mov r3, #1024 + 1110 05ac F3E7 b .L32 + 1111 .L138: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1112 .loc 1 192 5 discriminator 115 view .LVU295 + 1113 05ae 4FF48063 mov r3, #1024 + 1114 05b2 F0E7 b .L32 + 1115 .L139: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1116 .loc 1 192 5 discriminator 117 view .LVU296 + 1117 05b4 4FF48063 mov r3, #1024 + 1118 05b8 EDE7 b .L32 + 1119 .L140: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1120 .loc 1 192 5 discriminator 119 view .LVU297 + 1121 05ba 4FF48063 mov r3, #1024 + 1122 05be EAE7 b .L32 + 1123 .L141: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1124 .loc 1 192 5 discriminator 121 view .LVU298 + 1125 05c0 4FF48013 mov r3, #1048576 + 1126 05c4 E7E7 b .L32 + 1127 .L142: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1128 .loc 1 192 5 discriminator 123 view .LVU299 + 1129 05c6 4FF48013 mov r3, #1048576 + 1130 05ca E4E7 b .L32 + 1131 .L328: + 1132 .align 2 + 1133 .L327: + 1134 05cc 10600240 .word 1073897488 + 1135 05d0 00600240 .word 1073897472 + ARM GAS /tmp/ccwTmXyh.s page 31 + + + 1136 05d4 00640240 .word 1073898496 + 1137 05d8 58640240 .word 1073898584 + 1138 05dc B8600240 .word 1073897656 + 1139 05e0 58600240 .word 1073897560 + 1140 .L143: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1141 .loc 1 192 5 discriminator 125 view .LVU300 + 1142 05e4 4FF48013 mov r3, #1048576 + 1143 05e8 D5E7 b .L32 + 1144 .L31: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1145 .loc 1 192 5 discriminator 103 view .LVU301 + 1146 05ea B24A ldr r2, .L329 + 1147 05ec 9342 cmp r3, r2 + 1148 05ee 31D0 beq .L145 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1149 .loc 1 192 5 discriminator 153 view .LVU302 + 1150 05f0 02F58062 add r2, r2, #1024 + 1151 05f4 9342 cmp r3, r2 + 1152 05f6 31D0 beq .L146 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1153 .loc 1 192 5 discriminator 155 view .LVU303 + 1154 05f8 A2F56872 sub r2, r2, #928 + 1155 05fc 9342 cmp r3, r2 + 1156 05fe 2FD0 beq .L147 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1157 .loc 1 192 5 discriminator 157 view .LVU304 + 1158 0600 02F58062 add r2, r2, #1024 + 1159 0604 9342 cmp r3, r2 + 1160 0606 2DD0 beq .L148 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1161 .loc 1 192 5 discriminator 159 view .LVU305 + 1162 0608 A2F58962 sub r2, r2, #1096 + 1163 060c 9342 cmp r3, r2 + 1164 060e 2BD0 beq .L149 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1165 .loc 1 192 5 discriminator 161 view .LVU306 + 1166 0610 02F58062 add r2, r2, #1024 + 1167 0614 9342 cmp r3, r2 + 1168 0616 2AD0 beq .L150 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1169 .loc 1 192 5 discriminator 163 view .LVU307 + 1170 0618 A2F56872 sub r2, r2, #928 + 1171 061c 9342 cmp r3, r2 + 1172 061e 29D0 beq .L151 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1173 .loc 1 192 5 discriminator 165 view .LVU308 + 1174 0620 02F58062 add r2, r2, #1024 + 1175 0624 9342 cmp r3, r2 + 1176 0626 28D0 beq .L152 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1177 .loc 1 192 5 discriminator 167 view .LVU309 + 1178 0628 A2F58962 sub r2, r2, #1096 + 1179 062c 9342 cmp r3, r2 + 1180 062e 27D0 beq .L153 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1181 .loc 1 192 5 discriminator 169 view .LVU310 + ARM GAS /tmp/ccwTmXyh.s page 32 + + + 1182 0630 02F58062 add r2, r2, #1024 + 1183 0634 9342 cmp r3, r2 + 1184 0636 26D0 beq .L154 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1185 .loc 1 192 5 discriminator 171 view .LVU311 + 1186 0638 A2F56872 sub r2, r2, #928 + 1187 063c 9342 cmp r3, r2 + 1188 063e 25D0 beq .L155 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1189 .loc 1 192 5 discriminator 173 view .LVU312 + 1190 0640 02F58062 add r2, r2, #1024 + 1191 0644 9342 cmp r3, r2 + 1192 0646 02D0 beq .L312 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1193 .loc 1 192 5 discriminator 176 view .LVU313 + 1194 0648 4FF08063 mov r3, #67108864 + 1195 064c 03E0 b .L33 + 1196 .L312: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1197 .loc 1 192 5 discriminator 175 view .LVU314 + 1198 064e 4FF48013 mov r3, #1048576 + 1199 0652 00E0 b .L33 + 1200 .L145: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1201 .loc 1 192 5 discriminator 154 view .LVU315 + 1202 0654 1023 movs r3, #16 + 1203 .L33: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1204 .loc 1 192 5 discriminator 200 view .LVU316 + 1205 0656 984A ldr r2, .L329+4 + 1206 0658 9360 str r3, [r2, #8] + 1207 065a ADE6 b .L28 + 1208 .L146: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1209 .loc 1 192 5 discriminator 156 view .LVU317 + 1210 065c 1023 movs r3, #16 + 1211 065e FAE7 b .L33 + 1212 .L147: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1213 .loc 1 192 5 discriminator 158 view .LVU318 + 1214 0660 1023 movs r3, #16 + 1215 0662 F8E7 b .L33 + 1216 .L148: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1217 .loc 1 192 5 discriminator 160 view .LVU319 + 1218 0664 1023 movs r3, #16 + 1219 0666 F6E7 b .L33 + 1220 .L149: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1221 .loc 1 192 5 discriminator 162 view .LVU320 + 1222 0668 4FF48063 mov r3, #1024 + 1223 066c F3E7 b .L33 + 1224 .L150: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1225 .loc 1 192 5 discriminator 164 view .LVU321 + 1226 066e 4FF48063 mov r3, #1024 + 1227 0672 F0E7 b .L33 + ARM GAS /tmp/ccwTmXyh.s page 33 + + + 1228 .L151: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1229 .loc 1 192 5 discriminator 166 view .LVU322 + 1230 0674 4FF48063 mov r3, #1024 + 1231 0678 EDE7 b .L33 + 1232 .L152: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1233 .loc 1 192 5 discriminator 168 view .LVU323 + 1234 067a 4FF48063 mov r3, #1024 + 1235 067e EAE7 b .L33 + 1236 .L153: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1237 .loc 1 192 5 discriminator 170 view .LVU324 + 1238 0680 4FF48013 mov r3, #1048576 + 1239 0684 E7E7 b .L33 + 1240 .L154: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1241 .loc 1 192 5 discriminator 172 view .LVU325 + 1242 0686 4FF48013 mov r3, #1048576 + 1243 068a E4E7 b .L33 + 1244 .L155: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + 1245 .loc 1 192 5 discriminator 174 view .LVU326 + 1246 068c 4FF48013 mov r3, #1048576 + 1247 0690 E1E7 b .L33 + 1248 .L309: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1249 .loc 1 193 5 discriminator 25 view .LVU327 + 1250 0692 4FF40022 mov r2, #524288 + 1251 0696 00E0 b .L35 + 1252 .L157: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1253 .loc 1 193 5 discriminator 4 view .LVU328 + 1254 0698 0822 movs r2, #8 + 1255 .L35: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1256 .loc 1 193 5 discriminator 50 view .LVU329 + 1257 069a 884B ldr r3, .L329+8 + 1258 069c DA60 str r2, [r3, #12] + 1259 .L36: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1260 .loc 1 194 5 is_stmt 1 view .LVU330 + 1261 069e 2368 ldr r3, [r4] + 1262 06a0 874A ldr r2, .L329+12 + 1263 06a2 9342 cmp r3, r2 + 1264 06a4 40F2CE81 bls .L42 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1265 .loc 1 194 5 is_stmt 0 discriminator 1 view .LVU331 + 1266 06a8 A2F58962 sub r2, r2, #1096 + 1267 06ac 9342 cmp r3, r2 + 1268 06ae 00F06781 beq .L205 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1269 .loc 1 194 5 discriminator 3 view .LVU332 + 1270 06b2 02F58062 add r2, r2, #1024 + 1271 06b6 9342 cmp r3, r2 + 1272 06b8 00F0A981 beq .L206 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + ARM GAS /tmp/ccwTmXyh.s page 34 + + + 1273 .loc 1 194 5 discriminator 5 view .LVU333 + 1274 06bc A2F56872 sub r2, r2, #928 + 1275 06c0 9342 cmp r3, r2 + 1276 06c2 00F0A681 beq .L207 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1277 .loc 1 194 5 discriminator 7 view .LVU334 + 1278 06c6 02F58062 add r2, r2, #1024 + 1279 06ca 9342 cmp r3, r2 + 1280 06cc 00F0A381 beq .L208 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1281 .loc 1 194 5 discriminator 9 view .LVU335 + 1282 06d0 A2F58962 sub r2, r2, #1096 + 1283 06d4 9342 cmp r3, r2 + 1284 06d6 00F0A081 beq .L209 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1285 .loc 1 194 5 discriminator 11 view .LVU336 + 1286 06da 02F58062 add r2, r2, #1024 + 1287 06de 9342 cmp r3, r2 + 1288 06e0 00F09E81 beq .L210 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1289 .loc 1 194 5 discriminator 13 view .LVU337 + 1290 06e4 A2F56872 sub r2, r2, #928 + 1291 06e8 9342 cmp r3, r2 + 1292 06ea 00F09C81 beq .L211 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1293 .loc 1 194 5 discriminator 15 view .LVU338 + 1294 06ee 02F58062 add r2, r2, #1024 + 1295 06f2 9342 cmp r3, r2 + 1296 06f4 00F09A81 beq .L212 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1297 .loc 1 194 5 discriminator 17 view .LVU339 + 1298 06f8 A2F58962 sub r2, r2, #1096 + 1299 06fc 9342 cmp r3, r2 + 1300 06fe 00F09881 beq .L213 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1301 .loc 1 194 5 discriminator 19 view .LVU340 + 1302 0702 02F58062 add r2, r2, #1024 + 1303 0706 9342 cmp r3, r2 + 1304 0708 00F09681 beq .L214 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1305 .loc 1 194 5 discriminator 21 view .LVU341 + 1306 070c A2F56872 sub r2, r2, #928 + 1307 0710 9342 cmp r3, r2 + 1308 0712 00F09481 beq .L215 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1309 .loc 1 194 5 discriminator 23 view .LVU342 + 1310 0716 02F58062 add r2, r2, #1024 + 1311 071a 9342 cmp r3, r2 + 1312 071c 00F02D81 beq .L313 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1313 .loc 1 194 5 discriminator 26 view .LVU343 + 1314 0720 4FF08072 mov r2, #16777216 + 1315 0724 2DE1 b .L43 + 1316 .L158: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1317 .loc 1 193 5 discriminator 6 view .LVU344 + 1318 0726 0822 movs r2, #8 + ARM GAS /tmp/ccwTmXyh.s page 35 + + + 1319 0728 B7E7 b .L35 + 1320 .L159: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1321 .loc 1 193 5 discriminator 8 view .LVU345 + 1322 072a 0822 movs r2, #8 + 1323 072c B5E7 b .L35 + 1324 .L160: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1325 .loc 1 193 5 discriminator 10 view .LVU346 + 1326 072e 0822 movs r2, #8 + 1327 0730 B3E7 b .L35 + 1328 .L161: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1329 .loc 1 193 5 discriminator 12 view .LVU347 + 1330 0732 4FF40072 mov r2, #512 + 1331 0736 B0E7 b .L35 + 1332 .L162: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1333 .loc 1 193 5 discriminator 14 view .LVU348 + 1334 0738 4FF40072 mov r2, #512 + 1335 073c ADE7 b .L35 + 1336 .L163: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1337 .loc 1 193 5 discriminator 16 view .LVU349 + 1338 073e 4FF40072 mov r2, #512 + 1339 0742 AAE7 b .L35 + 1340 .L164: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1341 .loc 1 193 5 discriminator 18 view .LVU350 + 1342 0744 4FF40072 mov r2, #512 + 1343 0748 A7E7 b .L35 + 1344 .L165: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1345 .loc 1 193 5 discriminator 20 view .LVU351 + 1346 074a 4FF40022 mov r2, #524288 + 1347 074e A4E7 b .L35 + 1348 .L166: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1349 .loc 1 193 5 discriminator 22 view .LVU352 + 1350 0750 4FF40022 mov r2, #524288 + 1351 0754 A1E7 b .L35 + 1352 .L167: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1353 .loc 1 193 5 discriminator 24 view .LVU353 + 1354 0756 4FF40022 mov r2, #524288 + 1355 075a 9EE7 b .L35 + 1356 .L34: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1357 .loc 1 193 5 discriminator 2 view .LVU354 + 1358 075c 594A ldr r2, .L329+16 + 1359 075e 9342 cmp r3, r2 + 1360 0760 53D9 bls .L37 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1361 .loc 1 193 5 discriminator 51 view .LVU355 + 1362 0762 A83A subs r2, r2, #168 + 1363 0764 9342 cmp r3, r2 + 1364 0766 31D0 beq .L169 + ARM GAS /tmp/ccwTmXyh.s page 36 + + + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1365 .loc 1 193 5 discriminator 53 view .LVU356 + 1366 0768 02F58062 add r2, r2, #1024 + 1367 076c 9342 cmp r3, r2 + 1368 076e 31D0 beq .L170 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1369 .loc 1 193 5 discriminator 55 view .LVU357 + 1370 0770 A2F56872 sub r2, r2, #928 + 1371 0774 9342 cmp r3, r2 + 1372 0776 2FD0 beq .L171 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1373 .loc 1 193 5 discriminator 57 view .LVU358 + 1374 0778 02F58062 add r2, r2, #1024 + 1375 077c 9342 cmp r3, r2 + 1376 077e 2DD0 beq .L172 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1377 .loc 1 193 5 discriminator 59 view .LVU359 + 1378 0780 A2F58962 sub r2, r2, #1096 + 1379 0784 9342 cmp r3, r2 + 1380 0786 2BD0 beq .L173 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1381 .loc 1 193 5 discriminator 61 view .LVU360 + 1382 0788 02F58062 add r2, r2, #1024 + 1383 078c 9342 cmp r3, r2 + 1384 078e 2AD0 beq .L174 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1385 .loc 1 193 5 discriminator 63 view .LVU361 + 1386 0790 A2F56872 sub r2, r2, #928 + 1387 0794 9342 cmp r3, r2 + 1388 0796 29D0 beq .L175 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1389 .loc 1 193 5 discriminator 65 view .LVU362 + 1390 0798 02F58062 add r2, r2, #1024 + 1391 079c 9342 cmp r3, r2 + 1392 079e 28D0 beq .L176 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1393 .loc 1 193 5 discriminator 67 view .LVU363 + 1394 07a0 A2F58962 sub r2, r2, #1096 + 1395 07a4 9342 cmp r3, r2 + 1396 07a6 27D0 beq .L177 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1397 .loc 1 193 5 discriminator 69 view .LVU364 + 1398 07a8 02F58062 add r2, r2, #1024 + 1399 07ac 9342 cmp r3, r2 + 1400 07ae 26D0 beq .L178 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1401 .loc 1 193 5 discriminator 71 view .LVU365 + 1402 07b0 A2F56872 sub r2, r2, #928 + 1403 07b4 9342 cmp r3, r2 + 1404 07b6 25D0 beq .L179 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1405 .loc 1 193 5 discriminator 73 view .LVU366 + 1406 07b8 02F58062 add r2, r2, #1024 + 1407 07bc 9342 cmp r3, r2 + 1408 07be 02D0 beq .L314 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1409 .loc 1 193 5 discriminator 76 view .LVU367 + ARM GAS /tmp/ccwTmXyh.s page 37 + + + 1410 07c0 4FF00072 mov r2, #33554432 + 1411 07c4 03E0 b .L38 + 1412 .L314: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1413 .loc 1 193 5 discriminator 75 view .LVU368 + 1414 07c6 4FF40022 mov r2, #524288 + 1415 07ca 00E0 b .L38 + 1416 .L169: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1417 .loc 1 193 5 discriminator 54 view .LVU369 + 1418 07cc 0822 movs r2, #8 + 1419 .L38: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1420 .loc 1 193 5 discriminator 100 view .LVU370 + 1421 07ce 3B4B ldr r3, .L329+8 + 1422 07d0 9A60 str r2, [r3, #8] + 1423 07d2 64E7 b .L36 + 1424 .L170: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1425 .loc 1 193 5 discriminator 56 view .LVU371 + 1426 07d4 0822 movs r2, #8 + 1427 07d6 FAE7 b .L38 + 1428 .L171: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1429 .loc 1 193 5 discriminator 58 view .LVU372 + 1430 07d8 0822 movs r2, #8 + 1431 07da F8E7 b .L38 + 1432 .L172: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1433 .loc 1 193 5 discriminator 60 view .LVU373 + 1434 07dc 0822 movs r2, #8 + 1435 07de F6E7 b .L38 + 1436 .L173: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1437 .loc 1 193 5 discriminator 62 view .LVU374 + 1438 07e0 4FF40072 mov r2, #512 + 1439 07e4 F3E7 b .L38 + 1440 .L174: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1441 .loc 1 193 5 discriminator 64 view .LVU375 + 1442 07e6 4FF40072 mov r2, #512 + 1443 07ea F0E7 b .L38 + 1444 .L175: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1445 .loc 1 193 5 discriminator 66 view .LVU376 + 1446 07ec 4FF40072 mov r2, #512 + 1447 07f0 EDE7 b .L38 + 1448 .L176: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1449 .loc 1 193 5 discriminator 68 view .LVU377 + 1450 07f2 4FF40072 mov r2, #512 + 1451 07f6 EAE7 b .L38 + 1452 .L177: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1453 .loc 1 193 5 discriminator 70 view .LVU378 + 1454 07f8 4FF40022 mov r2, #524288 + 1455 07fc E7E7 b .L38 + ARM GAS /tmp/ccwTmXyh.s page 38 + + + 1456 .L178: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1457 .loc 1 193 5 discriminator 72 view .LVU379 + 1458 07fe 4FF40022 mov r2, #524288 + 1459 0802 E4E7 b .L38 + 1460 .L179: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1461 .loc 1 193 5 discriminator 74 view .LVU380 + 1462 0804 4FF40022 mov r2, #524288 + 1463 0808 E1E7 b .L38 + 1464 .L37: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1465 .loc 1 193 5 discriminator 52 view .LVU381 + 1466 080a 2F4A ldr r2, .L329+20 + 1467 080c 9342 cmp r3, r2 + 1468 080e 60D9 bls .L39 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1469 .loc 1 193 5 discriminator 102 view .LVU382 + 1470 0810 483A subs r2, r2, #72 + 1471 0812 9342 cmp r3, r2 + 1472 0814 31D0 beq .L181 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1473 .loc 1 193 5 discriminator 104 view .LVU383 + 1474 0816 02F58062 add r2, r2, #1024 + 1475 081a 9342 cmp r3, r2 + 1476 081c 31D0 beq .L182 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1477 .loc 1 193 5 discriminator 106 view .LVU384 + 1478 081e A2F56872 sub r2, r2, #928 + 1479 0822 9342 cmp r3, r2 + 1480 0824 2FD0 beq .L183 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1481 .loc 1 193 5 discriminator 108 view .LVU385 + 1482 0826 02F58062 add r2, r2, #1024 + 1483 082a 9342 cmp r3, r2 + 1484 082c 2DD0 beq .L184 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1485 .loc 1 193 5 discriminator 110 view .LVU386 + 1486 082e A2F58962 sub r2, r2, #1096 + 1487 0832 9342 cmp r3, r2 + 1488 0834 2BD0 beq .L185 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1489 .loc 1 193 5 discriminator 112 view .LVU387 + 1490 0836 02F58062 add r2, r2, #1024 + 1491 083a 9342 cmp r3, r2 + 1492 083c 2AD0 beq .L186 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1493 .loc 1 193 5 discriminator 114 view .LVU388 + 1494 083e A2F56872 sub r2, r2, #928 + 1495 0842 9342 cmp r3, r2 + 1496 0844 29D0 beq .L187 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1497 .loc 1 193 5 discriminator 116 view .LVU389 + 1498 0846 02F58062 add r2, r2, #1024 + 1499 084a 9342 cmp r3, r2 + 1500 084c 28D0 beq .L188 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + ARM GAS /tmp/ccwTmXyh.s page 39 + + + 1501 .loc 1 193 5 discriminator 118 view .LVU390 + 1502 084e A2F58962 sub r2, r2, #1096 + 1503 0852 9342 cmp r3, r2 + 1504 0854 27D0 beq .L189 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1505 .loc 1 193 5 discriminator 120 view .LVU391 + 1506 0856 02F58062 add r2, r2, #1024 + 1507 085a 9342 cmp r3, r2 + 1508 085c 26D0 beq .L190 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1509 .loc 1 193 5 discriminator 122 view .LVU392 + 1510 085e A2F56872 sub r2, r2, #928 + 1511 0862 9342 cmp r3, r2 + 1512 0864 32D0 beq .L191 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1513 .loc 1 193 5 discriminator 124 view .LVU393 + 1514 0866 02F58062 add r2, r2, #1024 + 1515 086a 9342 cmp r3, r2 + 1516 086c 02D0 beq .L315 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1517 .loc 1 193 5 discriminator 127 view .LVU394 + 1518 086e 4FF00073 mov r3, #33554432 + 1519 0872 03E0 b .L40 + 1520 .L315: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1521 .loc 1 193 5 discriminator 126 view .LVU395 + 1522 0874 4FF40023 mov r3, #524288 + 1523 0878 00E0 b .L40 + 1524 .L181: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1525 .loc 1 193 5 discriminator 105 view .LVU396 + 1526 087a 0823 movs r3, #8 + 1527 .L40: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1528 .loc 1 193 5 discriminator 151 view .LVU397 + 1529 087c 0E4A ldr r2, .L329+4 + 1530 087e D360 str r3, [r2, #12] + 1531 0880 0DE7 b .L36 + 1532 .L182: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1533 .loc 1 193 5 discriminator 107 view .LVU398 + 1534 0882 0823 movs r3, #8 + 1535 0884 FAE7 b .L40 + 1536 .L183: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1537 .loc 1 193 5 discriminator 109 view .LVU399 + 1538 0886 0823 movs r3, #8 + 1539 0888 F8E7 b .L40 + 1540 .L184: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1541 .loc 1 193 5 discriminator 111 view .LVU400 + 1542 088a 0823 movs r3, #8 + 1543 088c F6E7 b .L40 + 1544 .L185: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1545 .loc 1 193 5 discriminator 113 view .LVU401 + 1546 088e 4FF40073 mov r3, #512 + ARM GAS /tmp/ccwTmXyh.s page 40 + + + 1547 0892 F3E7 b .L40 + 1548 .L186: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1549 .loc 1 193 5 discriminator 115 view .LVU402 + 1550 0894 4FF40073 mov r3, #512 + 1551 0898 F0E7 b .L40 + 1552 .L187: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1553 .loc 1 193 5 discriminator 117 view .LVU403 + 1554 089a 4FF40073 mov r3, #512 + 1555 089e EDE7 b .L40 + 1556 .L188: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1557 .loc 1 193 5 discriminator 119 view .LVU404 + 1558 08a0 4FF40073 mov r3, #512 + 1559 08a4 EAE7 b .L40 + 1560 .L189: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1561 .loc 1 193 5 discriminator 121 view .LVU405 + 1562 08a6 4FF40023 mov r3, #524288 + 1563 08aa E7E7 b .L40 + 1564 .L190: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1565 .loc 1 193 5 discriminator 123 view .LVU406 + 1566 08ac 4FF40023 mov r3, #524288 + 1567 08b0 E4E7 b .L40 + 1568 .L330: + 1569 08b2 00BF .align 2 + 1570 .L329: + 1571 08b4 10600240 .word 1073897488 + 1572 08b8 00600240 .word 1073897472 + 1573 08bc 00640240 .word 1073898496 + 1574 08c0 58640240 .word 1073898584 + 1575 08c4 B8600240 .word 1073897656 + 1576 08c8 58600240 .word 1073897560 + 1577 .L191: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1578 .loc 1 193 5 discriminator 125 view .LVU407 + 1579 08cc 4FF40023 mov r3, #524288 + 1580 08d0 D4E7 b .L40 + 1581 .L39: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1582 .loc 1 193 5 discriminator 103 view .LVU408 + 1583 08d2 B24A ldr r2, .L331 + 1584 08d4 9342 cmp r3, r2 + 1585 08d6 31D0 beq .L193 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1586 .loc 1 193 5 discriminator 153 view .LVU409 + 1587 08d8 02F58062 add r2, r2, #1024 + 1588 08dc 9342 cmp r3, r2 + 1589 08de 31D0 beq .L194 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1590 .loc 1 193 5 discriminator 155 view .LVU410 + 1591 08e0 A2F56872 sub r2, r2, #928 + 1592 08e4 9342 cmp r3, r2 + 1593 08e6 2FD0 beq .L195 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + ARM GAS /tmp/ccwTmXyh.s page 41 + + + 1594 .loc 1 193 5 discriminator 157 view .LVU411 + 1595 08e8 02F58062 add r2, r2, #1024 + 1596 08ec 9342 cmp r3, r2 + 1597 08ee 2DD0 beq .L196 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1598 .loc 1 193 5 discriminator 159 view .LVU412 + 1599 08f0 A2F58962 sub r2, r2, #1096 + 1600 08f4 9342 cmp r3, r2 + 1601 08f6 2BD0 beq .L197 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1602 .loc 1 193 5 discriminator 161 view .LVU413 + 1603 08f8 02F58062 add r2, r2, #1024 + 1604 08fc 9342 cmp r3, r2 + 1605 08fe 2AD0 beq .L198 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1606 .loc 1 193 5 discriminator 163 view .LVU414 + 1607 0900 A2F56872 sub r2, r2, #928 + 1608 0904 9342 cmp r3, r2 + 1609 0906 29D0 beq .L199 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1610 .loc 1 193 5 discriminator 165 view .LVU415 + 1611 0908 02F58062 add r2, r2, #1024 + 1612 090c 9342 cmp r3, r2 + 1613 090e 28D0 beq .L200 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1614 .loc 1 193 5 discriminator 167 view .LVU416 + 1615 0910 A2F58962 sub r2, r2, #1096 + 1616 0914 9342 cmp r3, r2 + 1617 0916 27D0 beq .L201 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1618 .loc 1 193 5 discriminator 169 view .LVU417 + 1619 0918 02F58062 add r2, r2, #1024 + 1620 091c 9342 cmp r3, r2 + 1621 091e 26D0 beq .L202 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1622 .loc 1 193 5 discriminator 171 view .LVU418 + 1623 0920 A2F56872 sub r2, r2, #928 + 1624 0924 9342 cmp r3, r2 + 1625 0926 25D0 beq .L203 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1626 .loc 1 193 5 discriminator 173 view .LVU419 + 1627 0928 02F58062 add r2, r2, #1024 + 1628 092c 9342 cmp r3, r2 + 1629 092e 02D0 beq .L316 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1630 .loc 1 193 5 discriminator 176 view .LVU420 + 1631 0930 4FF00073 mov r3, #33554432 + 1632 0934 03E0 b .L41 + 1633 .L316: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1634 .loc 1 193 5 discriminator 175 view .LVU421 + 1635 0936 4FF40023 mov r3, #524288 + 1636 093a 00E0 b .L41 + 1637 .L193: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1638 .loc 1 193 5 discriminator 154 view .LVU422 + 1639 093c 0823 movs r3, #8 + ARM GAS /tmp/ccwTmXyh.s page 42 + + + 1640 .L41: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1641 .loc 1 193 5 discriminator 200 view .LVU423 + 1642 093e 984A ldr r2, .L331+4 + 1643 0940 9360 str r3, [r2, #8] + 1644 0942 ACE6 b .L36 + 1645 .L194: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1646 .loc 1 193 5 discriminator 156 view .LVU424 + 1647 0944 0823 movs r3, #8 + 1648 0946 FAE7 b .L41 + 1649 .L195: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1650 .loc 1 193 5 discriminator 158 view .LVU425 + 1651 0948 0823 movs r3, #8 + 1652 094a F8E7 b .L41 + 1653 .L196: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1654 .loc 1 193 5 discriminator 160 view .LVU426 + 1655 094c 0823 movs r3, #8 + 1656 094e F6E7 b .L41 + 1657 .L197: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1658 .loc 1 193 5 discriminator 162 view .LVU427 + 1659 0950 4FF40073 mov r3, #512 + 1660 0954 F3E7 b .L41 + 1661 .L198: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1662 .loc 1 193 5 discriminator 164 view .LVU428 + 1663 0956 4FF40073 mov r3, #512 + 1664 095a F0E7 b .L41 + 1665 .L199: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1666 .loc 1 193 5 discriminator 166 view .LVU429 + 1667 095c 4FF40073 mov r3, #512 + 1668 0960 EDE7 b .L41 + 1669 .L200: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1670 .loc 1 193 5 discriminator 168 view .LVU430 + 1671 0962 4FF40073 mov r3, #512 + 1672 0966 EAE7 b .L41 + 1673 .L201: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1674 .loc 1 193 5 discriminator 170 view .LVU431 + 1675 0968 4FF40023 mov r3, #524288 + 1676 096c E7E7 b .L41 + 1677 .L202: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1678 .loc 1 193 5 discriminator 172 view .LVU432 + 1679 096e 4FF40023 mov r3, #524288 + 1680 0972 E4E7 b .L41 + 1681 .L203: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + 1682 .loc 1 193 5 discriminator 174 view .LVU433 + 1683 0974 4FF40023 mov r3, #524288 + 1684 0978 E1E7 b .L41 + 1685 .L313: + ARM GAS /tmp/ccwTmXyh.s page 43 + + + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1686 .loc 1 194 5 discriminator 25 view .LVU434 + 1687 097a 4FF48022 mov r2, #262144 + 1688 097e 00E0 b .L43 + 1689 .L205: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1690 .loc 1 194 5 discriminator 4 view .LVU435 + 1691 0980 0422 movs r2, #4 + 1692 .L43: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1693 .loc 1 194 5 discriminator 50 view .LVU436 + 1694 0982 884B ldr r3, .L331+8 + 1695 0984 DA60 str r2, [r3, #12] + 1696 .L44: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 1697 .loc 1 195 5 is_stmt 1 view .LVU437 + 1698 0986 2368 ldr r3, [r4] + 1699 0988 874A ldr r2, .L331+12 + 1700 098a 9342 cmp r3, r2 + 1701 098c 40F2A181 bls .L50 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 1702 .loc 1 195 5 is_stmt 0 discriminator 1 view .LVU438 + 1703 0990 A2F58962 sub r2, r2, #1096 + 1704 0994 9342 cmp r3, r2 + 1705 0996 00F06781 beq .L253 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 1706 .loc 1 195 5 discriminator 3 view .LVU439 + 1707 099a 02F58062 add r2, r2, #1024 + 1708 099e 9342 cmp r3, r2 + 1709 09a0 00F08081 beq .L254 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 1710 .loc 1 195 5 discriminator 5 view .LVU440 + 1711 09a4 A2F56872 sub r2, r2, #928 + 1712 09a8 9342 cmp r3, r2 + 1713 09aa 00F07D81 beq .L255 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 1714 .loc 1 195 5 discriminator 7 view .LVU441 + 1715 09ae 02F58062 add r2, r2, #1024 + 1716 09b2 9342 cmp r3, r2 + 1717 09b4 00F07A81 beq .L256 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 1718 .loc 1 195 5 discriminator 9 view .LVU442 + 1719 09b8 A2F58962 sub r2, r2, #1096 + 1720 09bc 9342 cmp r3, r2 + 1721 09be 00F07781 beq .L257 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 1722 .loc 1 195 5 discriminator 11 view .LVU443 + 1723 09c2 02F58062 add r2, r2, #1024 + 1724 09c6 9342 cmp r3, r2 + 1725 09c8 00F07481 beq .L258 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 1726 .loc 1 195 5 discriminator 13 view .LVU444 + 1727 09cc A2F56872 sub r2, r2, #928 + 1728 09d0 9342 cmp r3, r2 + 1729 09d2 00F07181 beq .L259 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 1730 .loc 1 195 5 discriminator 15 view .LVU445 + ARM GAS /tmp/ccwTmXyh.s page 44 + + + 1731 09d6 02F58062 add r2, r2, #1024 + 1732 09da 9342 cmp r3, r2 + 1733 09dc 00F06E81 beq .L260 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 1734 .loc 1 195 5 discriminator 17 view .LVU446 + 1735 09e0 A2F58962 sub r2, r2, #1096 + 1736 09e4 9342 cmp r3, r2 + 1737 09e6 00F06B81 beq .L261 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 1738 .loc 1 195 5 discriminator 19 view .LVU447 + 1739 09ea 02F58062 add r2, r2, #1024 + 1740 09ee 9342 cmp r3, r2 + 1741 09f0 00F06981 beq .L262 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 1742 .loc 1 195 5 discriminator 21 view .LVU448 + 1743 09f4 A2F56872 sub r2, r2, #928 + 1744 09f8 9342 cmp r3, r2 + 1745 09fa 00F06781 beq .L263 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 1746 .loc 1 195 5 discriminator 23 view .LVU449 + 1747 09fe 02F58062 add r2, r2, #1024 + 1748 0a02 9342 cmp r3, r2 + 1749 0a04 00F02D81 beq .L317 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 1750 .loc 1 195 5 discriminator 26 view .LVU450 + 1751 0a08 4FF48002 mov r2, #4194304 + 1752 0a0c 2DE1 b .L51 + 1753 .L206: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1754 .loc 1 194 5 discriminator 6 view .LVU451 + 1755 0a0e 0422 movs r2, #4 + 1756 0a10 B7E7 b .L43 + 1757 .L207: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1758 .loc 1 194 5 discriminator 8 view .LVU452 + 1759 0a12 0422 movs r2, #4 + 1760 0a14 B5E7 b .L43 + 1761 .L208: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1762 .loc 1 194 5 discriminator 10 view .LVU453 + 1763 0a16 0422 movs r2, #4 + 1764 0a18 B3E7 b .L43 + 1765 .L209: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1766 .loc 1 194 5 discriminator 12 view .LVU454 + 1767 0a1a 4FF48072 mov r2, #256 + 1768 0a1e B0E7 b .L43 + 1769 .L210: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1770 .loc 1 194 5 discriminator 14 view .LVU455 + 1771 0a20 4FF48072 mov r2, #256 + 1772 0a24 ADE7 b .L43 + 1773 .L211: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1774 .loc 1 194 5 discriminator 16 view .LVU456 + 1775 0a26 4FF48072 mov r2, #256 + 1776 0a2a AAE7 b .L43 + ARM GAS /tmp/ccwTmXyh.s page 45 + + + 1777 .L212: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1778 .loc 1 194 5 discriminator 18 view .LVU457 + 1779 0a2c 4FF48072 mov r2, #256 + 1780 0a30 A7E7 b .L43 + 1781 .L213: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1782 .loc 1 194 5 discriminator 20 view .LVU458 + 1783 0a32 4FF48022 mov r2, #262144 + 1784 0a36 A4E7 b .L43 + 1785 .L214: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1786 .loc 1 194 5 discriminator 22 view .LVU459 + 1787 0a38 4FF48022 mov r2, #262144 + 1788 0a3c A1E7 b .L43 + 1789 .L215: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1790 .loc 1 194 5 discriminator 24 view .LVU460 + 1791 0a3e 4FF48022 mov r2, #262144 + 1792 0a42 9EE7 b .L43 + 1793 .L42: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1794 .loc 1 194 5 discriminator 2 view .LVU461 + 1795 0a44 594A ldr r2, .L331+16 + 1796 0a46 9342 cmp r3, r2 + 1797 0a48 53D9 bls .L45 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1798 .loc 1 194 5 discriminator 51 view .LVU462 + 1799 0a4a A83A subs r2, r2, #168 + 1800 0a4c 9342 cmp r3, r2 + 1801 0a4e 31D0 beq .L217 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1802 .loc 1 194 5 discriminator 53 view .LVU463 + 1803 0a50 02F58062 add r2, r2, #1024 + 1804 0a54 9342 cmp r3, r2 + 1805 0a56 31D0 beq .L218 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1806 .loc 1 194 5 discriminator 55 view .LVU464 + 1807 0a58 A2F56872 sub r2, r2, #928 + 1808 0a5c 9342 cmp r3, r2 + 1809 0a5e 2FD0 beq .L219 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1810 .loc 1 194 5 discriminator 57 view .LVU465 + 1811 0a60 02F58062 add r2, r2, #1024 + 1812 0a64 9342 cmp r3, r2 + 1813 0a66 2DD0 beq .L220 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1814 .loc 1 194 5 discriminator 59 view .LVU466 + 1815 0a68 A2F58962 sub r2, r2, #1096 + 1816 0a6c 9342 cmp r3, r2 + 1817 0a6e 2BD0 beq .L221 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1818 .loc 1 194 5 discriminator 61 view .LVU467 + 1819 0a70 02F58062 add r2, r2, #1024 + 1820 0a74 9342 cmp r3, r2 + 1821 0a76 2AD0 beq .L222 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + ARM GAS /tmp/ccwTmXyh.s page 46 + + + 1822 .loc 1 194 5 discriminator 63 view .LVU468 + 1823 0a78 A2F56872 sub r2, r2, #928 + 1824 0a7c 9342 cmp r3, r2 + 1825 0a7e 29D0 beq .L223 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1826 .loc 1 194 5 discriminator 65 view .LVU469 + 1827 0a80 02F58062 add r2, r2, #1024 + 1828 0a84 9342 cmp r3, r2 + 1829 0a86 28D0 beq .L224 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1830 .loc 1 194 5 discriminator 67 view .LVU470 + 1831 0a88 A2F58962 sub r2, r2, #1096 + 1832 0a8c 9342 cmp r3, r2 + 1833 0a8e 27D0 beq .L225 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1834 .loc 1 194 5 discriminator 69 view .LVU471 + 1835 0a90 02F58062 add r2, r2, #1024 + 1836 0a94 9342 cmp r3, r2 + 1837 0a96 26D0 beq .L226 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1838 .loc 1 194 5 discriminator 71 view .LVU472 + 1839 0a98 A2F56872 sub r2, r2, #928 + 1840 0a9c 9342 cmp r3, r2 + 1841 0a9e 25D0 beq .L227 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1842 .loc 1 194 5 discriminator 73 view .LVU473 + 1843 0aa0 02F58062 add r2, r2, #1024 + 1844 0aa4 9342 cmp r3, r2 + 1845 0aa6 02D0 beq .L318 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1846 .loc 1 194 5 discriminator 76 view .LVU474 + 1847 0aa8 4FF08072 mov r2, #16777216 + 1848 0aac 03E0 b .L46 + 1849 .L318: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1850 .loc 1 194 5 discriminator 75 view .LVU475 + 1851 0aae 4FF48022 mov r2, #262144 + 1852 0ab2 00E0 b .L46 + 1853 .L217: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1854 .loc 1 194 5 discriminator 54 view .LVU476 + 1855 0ab4 0422 movs r2, #4 + 1856 .L46: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1857 .loc 1 194 5 discriminator 100 view .LVU477 + 1858 0ab6 3B4B ldr r3, .L331+8 + 1859 0ab8 9A60 str r2, [r3, #8] + 1860 0aba 64E7 b .L44 + 1861 .L218: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1862 .loc 1 194 5 discriminator 56 view .LVU478 + 1863 0abc 0422 movs r2, #4 + 1864 0abe FAE7 b .L46 + 1865 .L219: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1866 .loc 1 194 5 discriminator 58 view .LVU479 + 1867 0ac0 0422 movs r2, #4 + ARM GAS /tmp/ccwTmXyh.s page 47 + + + 1868 0ac2 F8E7 b .L46 + 1869 .L220: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1870 .loc 1 194 5 discriminator 60 view .LVU480 + 1871 0ac4 0422 movs r2, #4 + 1872 0ac6 F6E7 b .L46 + 1873 .L221: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1874 .loc 1 194 5 discriminator 62 view .LVU481 + 1875 0ac8 4FF48072 mov r2, #256 + 1876 0acc F3E7 b .L46 + 1877 .L222: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1878 .loc 1 194 5 discriminator 64 view .LVU482 + 1879 0ace 4FF48072 mov r2, #256 + 1880 0ad2 F0E7 b .L46 + 1881 .L223: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1882 .loc 1 194 5 discriminator 66 view .LVU483 + 1883 0ad4 4FF48072 mov r2, #256 + 1884 0ad8 EDE7 b .L46 + 1885 .L224: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1886 .loc 1 194 5 discriminator 68 view .LVU484 + 1887 0ada 4FF48072 mov r2, #256 + 1888 0ade EAE7 b .L46 + 1889 .L225: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1890 .loc 1 194 5 discriminator 70 view .LVU485 + 1891 0ae0 4FF48022 mov r2, #262144 + 1892 0ae4 E7E7 b .L46 + 1893 .L226: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1894 .loc 1 194 5 discriminator 72 view .LVU486 + 1895 0ae6 4FF48022 mov r2, #262144 + 1896 0aea E4E7 b .L46 + 1897 .L227: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1898 .loc 1 194 5 discriminator 74 view .LVU487 + 1899 0aec 4FF48022 mov r2, #262144 + 1900 0af0 E1E7 b .L46 + 1901 .L45: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1902 .loc 1 194 5 discriminator 52 view .LVU488 + 1903 0af2 2F4A ldr r2, .L331+20 + 1904 0af4 9342 cmp r3, r2 + 1905 0af6 60D9 bls .L47 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1906 .loc 1 194 5 discriminator 102 view .LVU489 + 1907 0af8 483A subs r2, r2, #72 + 1908 0afa 9342 cmp r3, r2 + 1909 0afc 31D0 beq .L229 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1910 .loc 1 194 5 discriminator 104 view .LVU490 + 1911 0afe 02F58062 add r2, r2, #1024 + 1912 0b02 9342 cmp r3, r2 + 1913 0b04 31D0 beq .L230 + ARM GAS /tmp/ccwTmXyh.s page 48 + + + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1914 .loc 1 194 5 discriminator 106 view .LVU491 + 1915 0b06 A2F56872 sub r2, r2, #928 + 1916 0b0a 9342 cmp r3, r2 + 1917 0b0c 2FD0 beq .L231 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1918 .loc 1 194 5 discriminator 108 view .LVU492 + 1919 0b0e 02F58062 add r2, r2, #1024 + 1920 0b12 9342 cmp r3, r2 + 1921 0b14 2DD0 beq .L232 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1922 .loc 1 194 5 discriminator 110 view .LVU493 + 1923 0b16 A2F58962 sub r2, r2, #1096 + 1924 0b1a 9342 cmp r3, r2 + 1925 0b1c 2BD0 beq .L233 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1926 .loc 1 194 5 discriminator 112 view .LVU494 + 1927 0b1e 02F58062 add r2, r2, #1024 + 1928 0b22 9342 cmp r3, r2 + 1929 0b24 2AD0 beq .L234 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1930 .loc 1 194 5 discriminator 114 view .LVU495 + 1931 0b26 A2F56872 sub r2, r2, #928 + 1932 0b2a 9342 cmp r3, r2 + 1933 0b2c 29D0 beq .L235 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1934 .loc 1 194 5 discriminator 116 view .LVU496 + 1935 0b2e 02F58062 add r2, r2, #1024 + 1936 0b32 9342 cmp r3, r2 + 1937 0b34 28D0 beq .L236 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1938 .loc 1 194 5 discriminator 118 view .LVU497 + 1939 0b36 A2F58962 sub r2, r2, #1096 + 1940 0b3a 9342 cmp r3, r2 + 1941 0b3c 27D0 beq .L237 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1942 .loc 1 194 5 discriminator 120 view .LVU498 + 1943 0b3e 02F58062 add r2, r2, #1024 + 1944 0b42 9342 cmp r3, r2 + 1945 0b44 26D0 beq .L238 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1946 .loc 1 194 5 discriminator 122 view .LVU499 + 1947 0b46 A2F56872 sub r2, r2, #928 + 1948 0b4a 9342 cmp r3, r2 + 1949 0b4c 32D0 beq .L239 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1950 .loc 1 194 5 discriminator 124 view .LVU500 + 1951 0b4e 02F58062 add r2, r2, #1024 + 1952 0b52 9342 cmp r3, r2 + 1953 0b54 02D0 beq .L319 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1954 .loc 1 194 5 discriminator 127 view .LVU501 + 1955 0b56 4FF08073 mov r3, #16777216 + 1956 0b5a 03E0 b .L48 + 1957 .L319: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1958 .loc 1 194 5 discriminator 126 view .LVU502 + ARM GAS /tmp/ccwTmXyh.s page 49 + + + 1959 0b5c 4FF48023 mov r3, #262144 + 1960 0b60 00E0 b .L48 + 1961 .L229: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1962 .loc 1 194 5 discriminator 105 view .LVU503 + 1963 0b62 0423 movs r3, #4 + 1964 .L48: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1965 .loc 1 194 5 discriminator 151 view .LVU504 + 1966 0b64 0E4A ldr r2, .L331+4 + 1967 0b66 D360 str r3, [r2, #12] + 1968 0b68 0DE7 b .L44 + 1969 .L230: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1970 .loc 1 194 5 discriminator 107 view .LVU505 + 1971 0b6a 0423 movs r3, #4 + 1972 0b6c FAE7 b .L48 + 1973 .L231: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1974 .loc 1 194 5 discriminator 109 view .LVU506 + 1975 0b6e 0423 movs r3, #4 + 1976 0b70 F8E7 b .L48 + 1977 .L232: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1978 .loc 1 194 5 discriminator 111 view .LVU507 + 1979 0b72 0423 movs r3, #4 + 1980 0b74 F6E7 b .L48 + 1981 .L233: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1982 .loc 1 194 5 discriminator 113 view .LVU508 + 1983 0b76 4FF48073 mov r3, #256 + 1984 0b7a F3E7 b .L48 + 1985 .L234: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1986 .loc 1 194 5 discriminator 115 view .LVU509 + 1987 0b7c 4FF48073 mov r3, #256 + 1988 0b80 F0E7 b .L48 + 1989 .L235: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1990 .loc 1 194 5 discriminator 117 view .LVU510 + 1991 0b82 4FF48073 mov r3, #256 + 1992 0b86 EDE7 b .L48 + 1993 .L236: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1994 .loc 1 194 5 discriminator 119 view .LVU511 + 1995 0b88 4FF48073 mov r3, #256 + 1996 0b8c EAE7 b .L48 + 1997 .L237: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 1998 .loc 1 194 5 discriminator 121 view .LVU512 + 1999 0b8e 4FF48023 mov r3, #262144 + 2000 0b92 E7E7 b .L48 + 2001 .L238: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2002 .loc 1 194 5 discriminator 123 view .LVU513 + 2003 0b94 4FF48023 mov r3, #262144 + 2004 0b98 E4E7 b .L48 + ARM GAS /tmp/ccwTmXyh.s page 50 + + + 2005 .L332: + 2006 0b9a 00BF .align 2 + 2007 .L331: + 2008 0b9c 10600240 .word 1073897488 + 2009 0ba0 00600240 .word 1073897472 + 2010 0ba4 00640240 .word 1073898496 + 2011 0ba8 58640240 .word 1073898584 + 2012 0bac B8600240 .word 1073897656 + 2013 0bb0 58600240 .word 1073897560 + 2014 .L239: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2015 .loc 1 194 5 discriminator 125 view .LVU514 + 2016 0bb4 4FF48023 mov r3, #262144 + 2017 0bb8 D4E7 b .L48 + 2018 .L47: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2019 .loc 1 194 5 discriminator 103 view .LVU515 + 2020 0bba 994A ldr r2, .L333 + 2021 0bbc 9342 cmp r3, r2 + 2022 0bbe 31D0 beq .L241 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2023 .loc 1 194 5 discriminator 153 view .LVU516 + 2024 0bc0 02F58062 add r2, r2, #1024 + 2025 0bc4 9342 cmp r3, r2 + 2026 0bc6 31D0 beq .L242 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2027 .loc 1 194 5 discriminator 155 view .LVU517 + 2028 0bc8 A2F56872 sub r2, r2, #928 + 2029 0bcc 9342 cmp r3, r2 + 2030 0bce 2FD0 beq .L243 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2031 .loc 1 194 5 discriminator 157 view .LVU518 + 2032 0bd0 02F58062 add r2, r2, #1024 + 2033 0bd4 9342 cmp r3, r2 + 2034 0bd6 2DD0 beq .L244 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2035 .loc 1 194 5 discriminator 159 view .LVU519 + 2036 0bd8 A2F58962 sub r2, r2, #1096 + 2037 0bdc 9342 cmp r3, r2 + 2038 0bde 2BD0 beq .L245 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2039 .loc 1 194 5 discriminator 161 view .LVU520 + 2040 0be0 02F58062 add r2, r2, #1024 + 2041 0be4 9342 cmp r3, r2 + 2042 0be6 2AD0 beq .L246 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2043 .loc 1 194 5 discriminator 163 view .LVU521 + 2044 0be8 A2F56872 sub r2, r2, #928 + 2045 0bec 9342 cmp r3, r2 + 2046 0bee 29D0 beq .L247 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2047 .loc 1 194 5 discriminator 165 view .LVU522 + 2048 0bf0 02F58062 add r2, r2, #1024 + 2049 0bf4 9342 cmp r3, r2 + 2050 0bf6 28D0 beq .L248 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2051 .loc 1 194 5 discriminator 167 view .LVU523 + ARM GAS /tmp/ccwTmXyh.s page 51 + + + 2052 0bf8 A2F58962 sub r2, r2, #1096 + 2053 0bfc 9342 cmp r3, r2 + 2054 0bfe 27D0 beq .L249 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2055 .loc 1 194 5 discriminator 169 view .LVU524 + 2056 0c00 02F58062 add r2, r2, #1024 + 2057 0c04 9342 cmp r3, r2 + 2058 0c06 26D0 beq .L250 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2059 .loc 1 194 5 discriminator 171 view .LVU525 + 2060 0c08 A2F56872 sub r2, r2, #928 + 2061 0c0c 9342 cmp r3, r2 + 2062 0c0e 25D0 beq .L251 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2063 .loc 1 194 5 discriminator 173 view .LVU526 + 2064 0c10 02F58062 add r2, r2, #1024 + 2065 0c14 9342 cmp r3, r2 + 2066 0c16 02D0 beq .L320 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2067 .loc 1 194 5 discriminator 176 view .LVU527 + 2068 0c18 4FF08073 mov r3, #16777216 + 2069 0c1c 03E0 b .L49 + 2070 .L320: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2071 .loc 1 194 5 discriminator 175 view .LVU528 + 2072 0c1e 4FF48023 mov r3, #262144 + 2073 0c22 00E0 b .L49 + 2074 .L241: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2075 .loc 1 194 5 discriminator 154 view .LVU529 + 2076 0c24 0423 movs r3, #4 + 2077 .L49: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2078 .loc 1 194 5 discriminator 200 view .LVU530 + 2079 0c26 7F4A ldr r2, .L333+4 + 2080 0c28 9360 str r3, [r2, #8] + 2081 0c2a ACE6 b .L44 + 2082 .L242: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2083 .loc 1 194 5 discriminator 156 view .LVU531 + 2084 0c2c 0423 movs r3, #4 + 2085 0c2e FAE7 b .L49 + 2086 .L243: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2087 .loc 1 194 5 discriminator 158 view .LVU532 + 2088 0c30 0423 movs r3, #4 + 2089 0c32 F8E7 b .L49 + 2090 .L244: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2091 .loc 1 194 5 discriminator 160 view .LVU533 + 2092 0c34 0423 movs r3, #4 + 2093 0c36 F6E7 b .L49 + 2094 .L245: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2095 .loc 1 194 5 discriminator 162 view .LVU534 + 2096 0c38 4FF48073 mov r3, #256 + 2097 0c3c F3E7 b .L49 + ARM GAS /tmp/ccwTmXyh.s page 52 + + + 2098 .L246: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2099 .loc 1 194 5 discriminator 164 view .LVU535 + 2100 0c3e 4FF48073 mov r3, #256 + 2101 0c42 F0E7 b .L49 + 2102 .L247: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2103 .loc 1 194 5 discriminator 166 view .LVU536 + 2104 0c44 4FF48073 mov r3, #256 + 2105 0c48 EDE7 b .L49 + 2106 .L248: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2107 .loc 1 194 5 discriminator 168 view .LVU537 + 2108 0c4a 4FF48073 mov r3, #256 + 2109 0c4e EAE7 b .L49 + 2110 .L249: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2111 .loc 1 194 5 discriminator 170 view .LVU538 + 2112 0c50 4FF48023 mov r3, #262144 + 2113 0c54 E7E7 b .L49 + 2114 .L250: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2115 .loc 1 194 5 discriminator 172 view .LVU539 + 2116 0c56 4FF48023 mov r3, #262144 + 2117 0c5a E4E7 b .L49 + 2118 .L251: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + 2119 .loc 1 194 5 discriminator 174 view .LVU540 + 2120 0c5c 4FF48023 mov r3, #262144 + 2121 0c60 E1E7 b .L49 + 2122 .L317: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2123 .loc 1 195 5 discriminator 25 view .LVU541 + 2124 0c62 4FF48032 mov r2, #65536 + 2125 0c66 00E0 b .L51 + 2126 .L253: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2127 .loc 1 195 5 discriminator 4 view .LVU542 + 2128 0c68 0122 movs r2, #1 + 2129 .L51: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2130 .loc 1 195 5 discriminator 50 view .LVU543 + 2131 0c6a 6F4B ldr r3, .L333+8 + 2132 0c6c DA60 str r2, [r3, #12] + 2133 .L52: + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->Instance->FCR |= DMA_IT_FE; + 2134 .loc 1 198 5 is_stmt 1 view .LVU544 + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->Instance->FCR |= DMA_IT_FE; + 2135 .loc 1 198 9 is_stmt 0 view .LVU545 + 2136 0c6e 2268 ldr r2, [r4] + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->Instance->FCR |= DMA_IT_FE; + 2137 .loc 1 198 19 view .LVU546 + 2138 0c70 1368 ldr r3, [r2] + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** hdma->Instance->FCR |= DMA_IT_FE; + 2139 .loc 1 198 25 view .LVU547 + 2140 0c72 43F01603 orr r3, r3, #22 + 2141 0c76 1360 str r3, [r2] + ARM GAS /tmp/ccwTmXyh.s page 53 + + + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2142 .loc 1 199 5 is_stmt 1 view .LVU548 + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2143 .loc 1 199 9 is_stmt 0 view .LVU549 + 2144 0c78 2268 ldr r2, [r4] + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2145 .loc 1 199 19 view .LVU550 + 2146 0c7a 5369 ldr r3, [r2, #20] + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2147 .loc 1 199 25 view .LVU551 + 2148 0c7c 43F08003 orr r3, r3, #128 + 2149 0c80 5361 str r3, [r2, #20] + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 2150 .loc 1 201 5 is_stmt 1 view .LVU552 + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 2151 .loc 1 201 13 is_stmt 0 view .LVU553 + 2152 0c82 236C ldr r3, [r4, #64] + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 2153 .loc 1 201 7 view .LVU554 + 2154 0c84 002B cmp r3, #0 + 2155 0c86 00F02581 beq .L321 + 2156 .L58: + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 2157 .loc 1 203 7 is_stmt 1 view .LVU555 + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 2158 .loc 1 203 11 is_stmt 0 view .LVU556 + 2159 0c8a 2268 ldr r2, [r4] + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 2160 .loc 1 203 21 view .LVU557 + 2161 0c8c 1368 ldr r3, [r2] + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 2162 .loc 1 203 27 view .LVU558 + 2163 0c8e 43F00803 orr r3, r3, #8 + 2164 0c92 1360 str r3, [r2] + 2165 .L59: + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 2166 .loc 1 207 5 is_stmt 1 view .LVU559 + 2167 0c94 2268 ldr r2, [r4] + 2168 0c96 1368 ldr r3, [r2] + 2169 0c98 43F00103 orr r3, r3, #1 + 2170 0c9c 1360 str r3, [r2] + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2171 .loc 1 158 21 is_stmt 0 view .LVU560 + 2172 0c9e 0020 movs r0, #0 + 2173 0ca0 FFF7C4B9 b .L16 + 2174 .L254: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2175 .loc 1 195 5 discriminator 6 view .LVU561 + 2176 0ca4 0122 movs r2, #1 + 2177 0ca6 E0E7 b .L51 + 2178 .L255: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2179 .loc 1 195 5 discriminator 8 view .LVU562 + 2180 0ca8 0122 movs r2, #1 + 2181 0caa DEE7 b .L51 + 2182 .L256: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + ARM GAS /tmp/ccwTmXyh.s page 54 + + + 2183 .loc 1 195 5 discriminator 10 view .LVU563 + 2184 0cac 0122 movs r2, #1 + 2185 0cae DCE7 b .L51 + 2186 .L257: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2187 .loc 1 195 5 discriminator 12 view .LVU564 + 2188 0cb0 4022 movs r2, #64 + 2189 0cb2 DAE7 b .L51 + 2190 .L258: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2191 .loc 1 195 5 discriminator 14 view .LVU565 + 2192 0cb4 4022 movs r2, #64 + 2193 0cb6 D8E7 b .L51 + 2194 .L259: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2195 .loc 1 195 5 discriminator 16 view .LVU566 + 2196 0cb8 4022 movs r2, #64 + 2197 0cba D6E7 b .L51 + 2198 .L260: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2199 .loc 1 195 5 discriminator 18 view .LVU567 + 2200 0cbc 4022 movs r2, #64 + 2201 0cbe D4E7 b .L51 + 2202 .L261: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2203 .loc 1 195 5 discriminator 20 view .LVU568 + 2204 0cc0 4FF48032 mov r2, #65536 + 2205 0cc4 D1E7 b .L51 + 2206 .L262: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2207 .loc 1 195 5 discriminator 22 view .LVU569 + 2208 0cc6 4FF48032 mov r2, #65536 + 2209 0cca CEE7 b .L51 + 2210 .L263: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2211 .loc 1 195 5 discriminator 24 view .LVU570 + 2212 0ccc 4FF48032 mov r2, #65536 + 2213 0cd0 CBE7 b .L51 + 2214 .L50: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2215 .loc 1 195 5 discriminator 2 view .LVU571 + 2216 0cd2 564A ldr r2, .L333+12 + 2217 0cd4 9342 cmp r3, r2 + 2218 0cd6 4FD9 bls .L53 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2219 .loc 1 195 5 discriminator 51 view .LVU572 + 2220 0cd8 A83A subs r2, r2, #168 + 2221 0cda 9342 cmp r3, r2 + 2222 0cdc 31D0 beq .L265 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2223 .loc 1 195 5 discriminator 53 view .LVU573 + 2224 0cde 02F58062 add r2, r2, #1024 + 2225 0ce2 9342 cmp r3, r2 + 2226 0ce4 31D0 beq .L266 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2227 .loc 1 195 5 discriminator 55 view .LVU574 + 2228 0ce6 A2F56872 sub r2, r2, #928 + ARM GAS /tmp/ccwTmXyh.s page 55 + + + 2229 0cea 9342 cmp r3, r2 + 2230 0cec 2FD0 beq .L267 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2231 .loc 1 195 5 discriminator 57 view .LVU575 + 2232 0cee 02F58062 add r2, r2, #1024 + 2233 0cf2 9342 cmp r3, r2 + 2234 0cf4 2DD0 beq .L268 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2235 .loc 1 195 5 discriminator 59 view .LVU576 + 2236 0cf6 A2F58962 sub r2, r2, #1096 + 2237 0cfa 9342 cmp r3, r2 + 2238 0cfc 2BD0 beq .L269 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2239 .loc 1 195 5 discriminator 61 view .LVU577 + 2240 0cfe 02F58062 add r2, r2, #1024 + 2241 0d02 9342 cmp r3, r2 + 2242 0d04 29D0 beq .L270 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2243 .loc 1 195 5 discriminator 63 view .LVU578 + 2244 0d06 A2F56872 sub r2, r2, #928 + 2245 0d0a 9342 cmp r3, r2 + 2246 0d0c 27D0 beq .L271 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2247 .loc 1 195 5 discriminator 65 view .LVU579 + 2248 0d0e 02F58062 add r2, r2, #1024 + 2249 0d12 9342 cmp r3, r2 + 2250 0d14 25D0 beq .L272 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2251 .loc 1 195 5 discriminator 67 view .LVU580 + 2252 0d16 A2F58962 sub r2, r2, #1096 + 2253 0d1a 9342 cmp r3, r2 + 2254 0d1c 23D0 beq .L273 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2255 .loc 1 195 5 discriminator 69 view .LVU581 + 2256 0d1e 02F58062 add r2, r2, #1024 + 2257 0d22 9342 cmp r3, r2 + 2258 0d24 22D0 beq .L274 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2259 .loc 1 195 5 discriminator 71 view .LVU582 + 2260 0d26 A2F56872 sub r2, r2, #928 + 2261 0d2a 9342 cmp r3, r2 + 2262 0d2c 21D0 beq .L275 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2263 .loc 1 195 5 discriminator 73 view .LVU583 + 2264 0d2e 02F58062 add r2, r2, #1024 + 2265 0d32 9342 cmp r3, r2 + 2266 0d34 02D0 beq .L322 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2267 .loc 1 195 5 discriminator 76 view .LVU584 + 2268 0d36 4FF48002 mov r2, #4194304 + 2269 0d3a 03E0 b .L54 + 2270 .L322: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2271 .loc 1 195 5 discriminator 75 view .LVU585 + 2272 0d3c 4FF48032 mov r2, #65536 + 2273 0d40 00E0 b .L54 + 2274 .L265: + ARM GAS /tmp/ccwTmXyh.s page 56 + + + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2275 .loc 1 195 5 discriminator 54 view .LVU586 + 2276 0d42 0122 movs r2, #1 + 2277 .L54: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2278 .loc 1 195 5 discriminator 100 view .LVU587 + 2279 0d44 384B ldr r3, .L333+8 + 2280 0d46 9A60 str r2, [r3, #8] + 2281 0d48 91E7 b .L52 + 2282 .L266: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2283 .loc 1 195 5 discriminator 56 view .LVU588 + 2284 0d4a 0122 movs r2, #1 + 2285 0d4c FAE7 b .L54 + 2286 .L267: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2287 .loc 1 195 5 discriminator 58 view .LVU589 + 2288 0d4e 0122 movs r2, #1 + 2289 0d50 F8E7 b .L54 + 2290 .L268: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2291 .loc 1 195 5 discriminator 60 view .LVU590 + 2292 0d52 0122 movs r2, #1 + 2293 0d54 F6E7 b .L54 + 2294 .L269: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2295 .loc 1 195 5 discriminator 62 view .LVU591 + 2296 0d56 4022 movs r2, #64 + 2297 0d58 F4E7 b .L54 + 2298 .L270: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2299 .loc 1 195 5 discriminator 64 view .LVU592 + 2300 0d5a 4022 movs r2, #64 + 2301 0d5c F2E7 b .L54 + 2302 .L271: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2303 .loc 1 195 5 discriminator 66 view .LVU593 + 2304 0d5e 4022 movs r2, #64 + 2305 0d60 F0E7 b .L54 + 2306 .L272: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2307 .loc 1 195 5 discriminator 68 view .LVU594 + 2308 0d62 4022 movs r2, #64 + 2309 0d64 EEE7 b .L54 + 2310 .L273: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2311 .loc 1 195 5 discriminator 70 view .LVU595 + 2312 0d66 4FF48032 mov r2, #65536 + 2313 0d6a EBE7 b .L54 + 2314 .L274: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2315 .loc 1 195 5 discriminator 72 view .LVU596 + 2316 0d6c 4FF48032 mov r2, #65536 + 2317 0d70 E8E7 b .L54 + 2318 .L275: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2319 .loc 1 195 5 discriminator 74 view .LVU597 + ARM GAS /tmp/ccwTmXyh.s page 57 + + + 2320 0d72 4FF48032 mov r2, #65536 + 2321 0d76 E5E7 b .L54 + 2322 .L53: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2323 .loc 1 195 5 discriminator 52 view .LVU598 + 2324 0d78 2D4A ldr r2, .L333+16 + 2325 0d7a 9342 cmp r3, r2 + 2326 0d7c 5AD9 bls .L55 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2327 .loc 1 195 5 discriminator 102 view .LVU599 + 2328 0d7e 483A subs r2, r2, #72 + 2329 0d80 9342 cmp r3, r2 + 2330 0d82 31D0 beq .L277 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2331 .loc 1 195 5 discriminator 104 view .LVU600 + 2332 0d84 02F58062 add r2, r2, #1024 + 2333 0d88 9342 cmp r3, r2 + 2334 0d8a 31D0 beq .L278 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2335 .loc 1 195 5 discriminator 106 view .LVU601 + 2336 0d8c A2F56872 sub r2, r2, #928 + 2337 0d90 9342 cmp r3, r2 + 2338 0d92 2FD0 beq .L279 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2339 .loc 1 195 5 discriminator 108 view .LVU602 + 2340 0d94 02F58062 add r2, r2, #1024 + 2341 0d98 9342 cmp r3, r2 + 2342 0d9a 2DD0 beq .L280 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2343 .loc 1 195 5 discriminator 110 view .LVU603 + 2344 0d9c A2F58962 sub r2, r2, #1096 + 2345 0da0 9342 cmp r3, r2 + 2346 0da2 2BD0 beq .L281 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2347 .loc 1 195 5 discriminator 112 view .LVU604 + 2348 0da4 02F58062 add r2, r2, #1024 + 2349 0da8 9342 cmp r3, r2 + 2350 0daa 29D0 beq .L282 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2351 .loc 1 195 5 discriminator 114 view .LVU605 + 2352 0dac A2F56872 sub r2, r2, #928 + 2353 0db0 9342 cmp r3, r2 + 2354 0db2 27D0 beq .L283 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2355 .loc 1 195 5 discriminator 116 view .LVU606 + 2356 0db4 02F58062 add r2, r2, #1024 + 2357 0db8 9342 cmp r3, r2 + 2358 0dba 25D0 beq .L284 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2359 .loc 1 195 5 discriminator 118 view .LVU607 + 2360 0dbc A2F58962 sub r2, r2, #1096 + 2361 0dc0 9342 cmp r3, r2 + 2362 0dc2 23D0 beq .L285 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2363 .loc 1 195 5 discriminator 120 view .LVU608 + 2364 0dc4 02F58062 add r2, r2, #1024 + 2365 0dc8 9342 cmp r3, r2 + ARM GAS /tmp/ccwTmXyh.s page 58 + + + 2366 0dca 22D0 beq .L286 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2367 .loc 1 195 5 discriminator 122 view .LVU609 + 2368 0dcc A2F56872 sub r2, r2, #928 + 2369 0dd0 9342 cmp r3, r2 + 2370 0dd2 21D0 beq .L287 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2371 .loc 1 195 5 discriminator 124 view .LVU610 + 2372 0dd4 02F58062 add r2, r2, #1024 + 2373 0dd8 9342 cmp r3, r2 + 2374 0dda 02D0 beq .L323 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2375 .loc 1 195 5 discriminator 127 view .LVU611 + 2376 0ddc 4FF48003 mov r3, #4194304 + 2377 0de0 03E0 b .L56 + 2378 .L323: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2379 .loc 1 195 5 discriminator 126 view .LVU612 + 2380 0de2 4FF48033 mov r3, #65536 + 2381 0de6 00E0 b .L56 + 2382 .L277: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2383 .loc 1 195 5 discriminator 105 view .LVU613 + 2384 0de8 0123 movs r3, #1 + 2385 .L56: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2386 .loc 1 195 5 discriminator 151 view .LVU614 + 2387 0dea 0E4A ldr r2, .L333+4 + 2388 0dec D360 str r3, [r2, #12] + 2389 0dee 3EE7 b .L52 + 2390 .L278: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2391 .loc 1 195 5 discriminator 107 view .LVU615 + 2392 0df0 0123 movs r3, #1 + 2393 0df2 FAE7 b .L56 + 2394 .L279: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2395 .loc 1 195 5 discriminator 109 view .LVU616 + 2396 0df4 0123 movs r3, #1 + 2397 0df6 F8E7 b .L56 + 2398 .L280: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2399 .loc 1 195 5 discriminator 111 view .LVU617 + 2400 0df8 0123 movs r3, #1 + 2401 0dfa F6E7 b .L56 + 2402 .L281: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2403 .loc 1 195 5 discriminator 113 view .LVU618 + 2404 0dfc 4023 movs r3, #64 + 2405 0dfe F4E7 b .L56 + 2406 .L282: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2407 .loc 1 195 5 discriminator 115 view .LVU619 + 2408 0e00 4023 movs r3, #64 + 2409 0e02 F2E7 b .L56 + 2410 .L283: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + ARM GAS /tmp/ccwTmXyh.s page 59 + + + 2411 .loc 1 195 5 discriminator 117 view .LVU620 + 2412 0e04 4023 movs r3, #64 + 2413 0e06 F0E7 b .L56 + 2414 .L284: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2415 .loc 1 195 5 discriminator 119 view .LVU621 + 2416 0e08 4023 movs r3, #64 + 2417 0e0a EEE7 b .L56 + 2418 .L285: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2419 .loc 1 195 5 discriminator 121 view .LVU622 + 2420 0e0c 4FF48033 mov r3, #65536 + 2421 0e10 EBE7 b .L56 + 2422 .L286: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2423 .loc 1 195 5 discriminator 123 view .LVU623 + 2424 0e12 4FF48033 mov r3, #65536 + 2425 0e16 E8E7 b .L56 + 2426 .L287: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2427 .loc 1 195 5 discriminator 125 view .LVU624 + 2428 0e18 4FF48033 mov r3, #65536 + 2429 0e1c E5E7 b .L56 + 2430 .L334: + 2431 0e1e 00BF .align 2 + 2432 .L333: + 2433 0e20 10600240 .word 1073897488 + 2434 0e24 00600240 .word 1073897472 + 2435 0e28 00640240 .word 1073898496 + 2436 0e2c B8600240 .word 1073897656 + 2437 0e30 58600240 .word 1073897560 + 2438 .L55: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2439 .loc 1 195 5 discriminator 103 view .LVU625 + 2440 0e34 2B4A ldr r2, .L335 + 2441 0e36 9342 cmp r3, r2 + 2442 0e38 31D0 beq .L289 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2443 .loc 1 195 5 discriminator 153 view .LVU626 + 2444 0e3a 02F58062 add r2, r2, #1024 + 2445 0e3e 9342 cmp r3, r2 + 2446 0e40 31D0 beq .L290 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2447 .loc 1 195 5 discriminator 155 view .LVU627 + 2448 0e42 A2F56872 sub r2, r2, #928 + 2449 0e46 9342 cmp r3, r2 + 2450 0e48 2FD0 beq .L291 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2451 .loc 1 195 5 discriminator 157 view .LVU628 + 2452 0e4a 02F58062 add r2, r2, #1024 + 2453 0e4e 9342 cmp r3, r2 + 2454 0e50 2DD0 beq .L292 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2455 .loc 1 195 5 discriminator 159 view .LVU629 + 2456 0e52 A2F58962 sub r2, r2, #1096 + 2457 0e56 9342 cmp r3, r2 + 2458 0e58 2BD0 beq .L293 + ARM GAS /tmp/ccwTmXyh.s page 60 + + + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2459 .loc 1 195 5 discriminator 161 view .LVU630 + 2460 0e5a 02F58062 add r2, r2, #1024 + 2461 0e5e 9342 cmp r3, r2 + 2462 0e60 29D0 beq .L294 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2463 .loc 1 195 5 discriminator 163 view .LVU631 + 2464 0e62 A2F56872 sub r2, r2, #928 + 2465 0e66 9342 cmp r3, r2 + 2466 0e68 27D0 beq .L295 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2467 .loc 1 195 5 discriminator 165 view .LVU632 + 2468 0e6a 02F58062 add r2, r2, #1024 + 2469 0e6e 9342 cmp r3, r2 + 2470 0e70 25D0 beq .L296 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2471 .loc 1 195 5 discriminator 167 view .LVU633 + 2472 0e72 A2F58962 sub r2, r2, #1096 + 2473 0e76 9342 cmp r3, r2 + 2474 0e78 23D0 beq .L297 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2475 .loc 1 195 5 discriminator 169 view .LVU634 + 2476 0e7a 02F58062 add r2, r2, #1024 + 2477 0e7e 9342 cmp r3, r2 + 2478 0e80 22D0 beq .L298 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2479 .loc 1 195 5 discriminator 171 view .LVU635 + 2480 0e82 A2F56872 sub r2, r2, #928 + 2481 0e86 9342 cmp r3, r2 + 2482 0e88 21D0 beq .L299 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2483 .loc 1 195 5 discriminator 173 view .LVU636 + 2484 0e8a 02F58062 add r2, r2, #1024 + 2485 0e8e 9342 cmp r3, r2 + 2486 0e90 02D0 beq .L324 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2487 .loc 1 195 5 discriminator 176 view .LVU637 + 2488 0e92 4FF48003 mov r3, #4194304 + 2489 0e96 03E0 b .L57 + 2490 .L324: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2491 .loc 1 195 5 discriminator 175 view .LVU638 + 2492 0e98 4FF48033 mov r3, #65536 + 2493 0e9c 00E0 b .L57 + 2494 .L289: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2495 .loc 1 195 5 discriminator 154 view .LVU639 + 2496 0e9e 0123 movs r3, #1 + 2497 .L57: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2498 .loc 1 195 5 discriminator 200 view .LVU640 + 2499 0ea0 114A ldr r2, .L335+4 + 2500 0ea2 9360 str r3, [r2, #8] + 2501 0ea4 E3E6 b .L52 + 2502 .L290: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2503 .loc 1 195 5 discriminator 156 view .LVU641 + ARM GAS /tmp/ccwTmXyh.s page 61 + + + 2504 0ea6 0123 movs r3, #1 + 2505 0ea8 FAE7 b .L57 + 2506 .L291: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2507 .loc 1 195 5 discriminator 158 view .LVU642 + 2508 0eaa 0123 movs r3, #1 + 2509 0eac F8E7 b .L57 + 2510 .L292: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2511 .loc 1 195 5 discriminator 160 view .LVU643 + 2512 0eae 0123 movs r3, #1 + 2513 0eb0 F6E7 b .L57 + 2514 .L293: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2515 .loc 1 195 5 discriminator 162 view .LVU644 + 2516 0eb2 4023 movs r3, #64 + 2517 0eb4 F4E7 b .L57 + 2518 .L294: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2519 .loc 1 195 5 discriminator 164 view .LVU645 + 2520 0eb6 4023 movs r3, #64 + 2521 0eb8 F2E7 b .L57 + 2522 .L295: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2523 .loc 1 195 5 discriminator 166 view .LVU646 + 2524 0eba 4023 movs r3, #64 + 2525 0ebc F0E7 b .L57 + 2526 .L296: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2527 .loc 1 195 5 discriminator 168 view .LVU647 + 2528 0ebe 4023 movs r3, #64 + 2529 0ec0 EEE7 b .L57 + 2530 .L297: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2531 .loc 1 195 5 discriminator 170 view .LVU648 + 2532 0ec2 4FF48033 mov r3, #65536 + 2533 0ec6 EBE7 b .L57 + 2534 .L298: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2535 .loc 1 195 5 discriminator 172 view .LVU649 + 2536 0ec8 4FF48033 mov r3, #65536 + 2537 0ecc E8E7 b .L57 + 2538 .L299: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2539 .loc 1 195 5 discriminator 174 view .LVU650 + 2540 0ece 4FF48033 mov r3, #65536 + 2541 0ed2 E5E7 b .L57 + 2542 .L321: + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 2543 .loc 1 201 53 discriminator 1 view .LVU651 + 2544 0ed4 A36C ldr r3, [r4, #72] + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 2545 .loc 1 201 45 discriminator 1 view .LVU652 + 2546 0ed6 002B cmp r3, #0 + 2547 0ed8 7FF4D7AE bne .L58 + 2548 0edc DAE6 b .L59 + 2549 .LVL38: + ARM GAS /tmp/ccwTmXyh.s page 62 + + + 2550 .L60: + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2551 .loc 1 171 3 discriminator 1 view .LVU653 + 2552 0ede 0220 movs r0, #2 + 2553 0ee0 FFF7A4B8 b .L16 + 2554 .L336: + 2555 .align 2 + 2556 .L335: + 2557 0ee4 10600240 .word 1073897488 + 2558 0ee8 00600240 .word 1073897472 + 2559 .cfi_endproc + 2560 .LFE142: + 2562 .section .text.HAL_DMAEx_ChangeMemory,"ax",%progbits + 2563 .align 1 + 2564 .global HAL_DMAEx_ChangeMemory + 2565 .syntax unified + 2566 .thumb + 2567 .thumb_func + 2569 HAL_DMAEx_ChangeMemory: + 2570 .LVL39: + 2571 .LFB143: + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** if(memory == MEMORY0) + 2572 .loc 1 235 1 is_stmt 1 view -0 + 2573 .cfi_startproc + 2574 @ args = 0, pretend = 0, frame = 0 + 2575 @ frame_needed = 0, uses_anonymous_args = 0 + 2576 @ link register save eliminated. + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 2577 .loc 1 236 3 view .LVU655 + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** { + 2578 .loc 1 236 5 is_stmt 0 view .LVU656 + 2579 0000 1AB9 cbnz r2, .L338 + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 2580 .loc 1 239 5 is_stmt 1 view .LVU657 + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 2581 .loc 1 239 9 is_stmt 0 view .LVU658 + 2582 0002 0368 ldr r3, [r0] + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 2583 .loc 1 239 26 view .LVU659 + 2584 0004 D960 str r1, [r3, #12] + 2585 .L339: + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 2586 .loc 1 247 3 is_stmt 1 view .LVU660 + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2587 .loc 1 248 1 is_stmt 0 view .LVU661 + 2588 0006 0020 movs r0, #0 + 2589 .LVL40: + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** + 2590 .loc 1 248 1 view .LVU662 + 2591 0008 7047 bx lr + 2592 .LVL41: + 2593 .L338: + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 2594 .loc 1 244 5 is_stmt 1 view .LVU663 + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 2595 .loc 1 244 9 is_stmt 0 view .LVU664 + 2596 000a 0368 ldr r3, [r0] + ARM GAS /tmp/ccwTmXyh.s page 63 + + + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c **** } + 2597 .loc 1 244 26 view .LVU665 + 2598 000c 1961 str r1, [r3, #16] + 2599 000e FAE7 b .L339 + 2600 .cfi_endproc + 2601 .LFE143: + 2603 .text + 2604 .Letext0: + 2605 .file 2 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 2606 .file 3 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 2607 .file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 2608 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h" + 2609 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h" + ARM GAS /tmp/ccwTmXyh.s page 64 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_dma_ex.c + /tmp/ccwTmXyh.s:20 .text.DMA_MultiBufferSetConfig:00000000 $t + /tmp/ccwTmXyh.s:25 .text.DMA_MultiBufferSetConfig:00000000 DMA_MultiBufferSetConfig + /tmp/ccwTmXyh.s:88 .text.HAL_DMAEx_MultiBufferStart:00000000 $t + /tmp/ccwTmXyh.s:94 .text.HAL_DMAEx_MultiBufferStart:00000000 HAL_DMAEx_MultiBufferStart + /tmp/ccwTmXyh.s:200 .text.HAL_DMAEx_MultiBufferStart_IT:00000000 $t + /tmp/ccwTmXyh.s:206 .text.HAL_DMAEx_MultiBufferStart_IT:00000000 HAL_DMAEx_MultiBufferStart_IT + /tmp/ccwTmXyh.s:698 .text.HAL_DMAEx_MultiBufferStart_IT:000002f0 $d + /tmp/ccwTmXyh.s:705 .text.HAL_DMAEx_MultiBufferStart_IT:00000304 $t + /tmp/ccwTmXyh.s:1134 .text.HAL_DMAEx_MultiBufferStart_IT:000005cc $d + /tmp/ccwTmXyh.s:1142 .text.HAL_DMAEx_MultiBufferStart_IT:000005e4 $t + /tmp/ccwTmXyh.s:1571 .text.HAL_DMAEx_MultiBufferStart_IT:000008b4 $d + /tmp/ccwTmXyh.s:1579 .text.HAL_DMAEx_MultiBufferStart_IT:000008cc $t + /tmp/ccwTmXyh.s:2008 .text.HAL_DMAEx_MultiBufferStart_IT:00000b9c $d + /tmp/ccwTmXyh.s:2016 .text.HAL_DMAEx_MultiBufferStart_IT:00000bb4 $t + /tmp/ccwTmXyh.s:2433 .text.HAL_DMAEx_MultiBufferStart_IT:00000e20 $d + /tmp/ccwTmXyh.s:2440 .text.HAL_DMAEx_MultiBufferStart_IT:00000e34 $t + /tmp/ccwTmXyh.s:2557 .text.HAL_DMAEx_MultiBufferStart_IT:00000ee4 $d + /tmp/ccwTmXyh.s:2563 .text.HAL_DMAEx_ChangeMemory:00000000 $t + /tmp/ccwTmXyh.s:2569 .text.HAL_DMAEx_ChangeMemory:00000000 HAL_DMAEx_ChangeMemory + +NO UNDEFINED SYMBOLS diff --git a/build/stm32f7xx_hal_dma_ex.o b/build/stm32f7xx_hal_dma_ex.o new file mode 100644 index 0000000000000000000000000000000000000000..858c163a3d949e6d258045e96643b0f8c4e0d96d GIT binary patch literal 17248 zcmeHP3v^Z0ncnA~dv9*Ixgq2s4-v1qAW_K81CWP+d4U8H6B1~#wI(;o4L2n(Z*CN{ z)T6dzZKrivR8XT7MSN9jty*=~)afi;tJBdAt*sSj>PTxz7qzpn#iD&V-?z_yPEI1U zr8C$yv$~h(|IYvad;k02dw*x=oO2Iey{cigVHnCOhAL5Gno_T<)SkdX4JGOfHB;q1 z?oV~LUze(y7u;{AZfiGFueN{e9sjz)3(eH+&wKRsrY1o!)*Oa8Ixs5R7?G@|d0`ruup=A=qeRY$F8NqaP9Cj56qSHE}c z5APMH3R1O446~qJMc+WpACD^K#GfMZ)sf`&<9o>7uVU!2{CNGSXnXSbeZ^AuuH8{n z^~+t>-EZH}v7@G9zwd1enAv~#+o|-9nzZPH(CP0Ny-)nTqHhuZ$3^cEe@b-U{-z_U z!+gEzsLEHbM~gqR?$!2K>hE;lFI;2C#+a_Ldsj#9gN^;GBYR!j9=G0Iu5HAvce`ub z<<`5^wcYI2`=V=`cTLj~t7G25Xz|xaqs33)_}VD)>v&YlhqZiA%ljzv_iDLE%ezJ| zM((W#?q4=GXB9H$G8uEJ%*i~_&lUeUqL+w&uIOire~#!A=j{A-x3_m8%irL52gk2< zZoks>t| zJ9W05I@?a2ZGq0VKxbQUa8y0JsmoWTa6HxStJ;J^;rJ@X;PCU5%(W-`oojcrKXT|V z%N|!bIG$I0z2^A!n&U6Joa}b_cfZTYdtKYzZoS>E?M}De9j@&*x86?Ic8gnYhijV; zj;r+igL&Y19yp$-Ic{l=TOH)M)j^J19pt#BId0{X<5vC$#c@mT3-+8X(;UwO$MeAP zJk4>dgRHSS$QrAItg$-C8cTEB$|q~Ae4FEKr-b7U>v%<4nk5!Eo)^p29M1#C^T6>u z&2dX}+|nGkG{-H?aZ7XD0>|@&&*V3G?r)q_yO1YD#OAm&? z@(@@avUl>d-pSKsxk{7eDy?_&V!e|W>z%y#gJQW#>%CFWnZ1*T!154S9Hgp8LUbKX~r9cXQ2iOY_{)JhwE@EzNUF^W6Htcy4KySm3!|c|ebgv^4aa|sRu#XB;}sk) zaQv6f?B`nkOv|5+mLkiKoYZdn7iDScEEiz@H49gc8epLT z78+n-RSa3ikYx;6#&nhobe0QrmJ5D5VXt-WC+3|5^ZutVn%BNWT#zTIkavsGKd!233W=Hr!S?l5V z`Lo`H*JlL3NALwML}8Wly2)-xLz&w#@%}~T4RGX?2gC~7ovHY>M?Iy+KL??zEe zB2833D(ZY?zD2zq)921npxbyD!wFx)0fcuVni2jgPJQ7#n9XnjTKK~a9F8*guz8>F zN_hNimHQlOwg+y=y9heg6gWM@JARCVEj8^zXiv%&p{Z68|+S|%`vEL;XsTQHQhLyDUFPUdox$57uli}+m{`0 zq>l04g7FtPrs}LmS{ZLTf=$LTRi{3ZqAdgc%PPMz4-7SS)Mw?ExJ4xHk&_7F?PPO|=+TMoF$+1)IzJ<17OzmYj>{L@a)jOfz zg5&fCR5(tm%9vuz$t?(*xu@rD3{Ejxj64j$H(Q0nD`5n|PE%&?vhexgrQ!MlZbFI> zkP0ENs=x?`Q6aE2Y`~KhQD(?i>kF1(6AQt>0Px#}Y>B81V6ER+84kl|cfuIq5;U0^ z#$G3}(K+oA38iyk?A!vw%+=Nvs53NL6F4_MHJC?q zhbfW9a%qM41chVtshe~f-4+NbF=*u{9u(6@`L;})OrHv*-HTG>ufjSBNN=z z?a(LShaI|QTxcP{Sm>5|m`u@(|;jW}A8y-rR_4ag>ZSL$WOQics z`v>}yrO8A`Pg%u+cxAkztVe1(F^}6R!YMVB>040Q&2&_j(E0Ye3NiEwfj}^(PiI5}Mlm!qz5M+yT>XYI7Wa^{4-swIS+pX{l2vn%L@ZB zM9*3t$TbV&0b@4fwnqa+K_iaSvjREv2F*$FK!HBHAP@!?MFYqpD`;yoc^V5wqrnO^ zG!vTw0mR0gLVQ9tBgXr(F@uYAHk%}yvk*P7JZR318^LHWUZfK+Voa-HLRv6o$L)DS zBFGq(D)fvLL<7?}&QI{GH!q(iz1sMOc9}&OfiL`fTD9)=;daSV+-Lk)rrGBllADQw&n1DKZq7Q*5QUlHwB-S5thFZF`n0)4$V* zYRR6rFq=M}4NzQ0F~pj~6jxAeqqvGoT_8{NJR@FaJgt%)npauhZY? za)Lie|7*L8d-tU8Hdi?JQd(OXi0}q58eHkz0iMoVtSa8|HQ9H3L30i-@QL>^{F9wW zkxx-baf{DGTSHMtv6|x4-ol*V?+`m4rnrJ)8^s59^KxRQ@TO*;zJ&qJVv~d`Z9%cbpVT?Vhn8A{O5yTyNAUIQQ$MsV|T~9jM znduqmS9}!Qcu_-B?YdQUTG>$FxTbBNQI+^He z+pujgS(ofqL#csuCdwbe@EBR$)s;>T4e21d?uP0OtJ+#twXWKr+pbCUcl9QnrtG(7 zW9!ArX~rgArzfSRbrXW>hHY(ZGCu02?qqsZIz5oCP4xD5Bs#Y!S{f^A2YWNF$sR;a zVkqhKeNo+p7S)>U9O&TeY>Vakw|rQ#0I+G+Hx>bVk*t68-(jUIi_aRQ3Hmh)|EWT5i1NWV&ZC z#Yg0Z0Susl&OiDzjkzzI@Ko$POgp(@R2YhPdfEN(kk>M{W)20U^>IegR=+`&r3U(v zW!=fHL|J2f^MwEr+Dm2| zIE~&#PiATd`n!8JdpJP~Y);y1qUwe+4&fR!yBf<8(anY|aaKuFWL!4(MOwjhNSM|2 ztD71J@SX;GT_TgH?!^rCaW2#oQn;v71HD~}l^c@% zn=>grdDR`b_T6i0?2;IlAFsamEgZ*2YCE~u7cA3uM=e`Nb=}44!izRWYbzEWE{wNy$lfN0pmz`V>n+o@ zDRp6O?XqY|#iC_8xpcC(qO|gyiJ9UJlgh#I9tz&Jd?Gg|qWDvWQ}}kTI@kXxW8I|Z za#eNM>*E{0>fF5R{GT#E?ZZ#|ULW5UdVTD}DSU%iT>+8cyE$dd#c5#is?tUkjAS)t z`zD3*{e?!6G1Z)AOgCm2GmTkBF<);^C|;9az4e~gZSqx}r{K?$N8{T_ysh&T6R+vK z`SVTa>F_fO=fLNAGsvL12Mu>F2F4cq^M8^-p(;nCUt zasINSi|v2GqticvpXTgh`ycn{^hf0_E`Cnb`7QM5^uOWJC6ESFWltDSw%3jMm^4B6 zt~lpQe?{TeG1X-EoF}H5GC{|Wa-L$UB9F%UQzz)BP0**S#jtSw$kTkRm;D=!{U$pf z;~x}1`IwLKO?-Rn{GFO@?@-6xH)nS_`@(Vl5d9Gs|3=A%f`;SvT>S&Vq%8Y~Bw`Tx z`DWPHsqaku^hzDb86i$5o}ttn;w*XV5Bmb~FB7a5D0qwD9fErV?-P7P@L9nZ1pi&|upqysVLu^U`^2e& zXA3S8tP^Y%>=3+6&=R~+@L9nFg8wOaNbns&1HVZ4u&)FJvx(U33W&(3Sg=B{O0a>5 zdd-3#7JDZVm*Zx^jM%RxqW*P)pAq}5g8Kv?BVzk_Qt%lf+C3-!e-r&B!B@oo6VXQn z-xT{X(SIw5OJ9#GOhnwtg7`2&+s_m|CRif&1)?t&Tuwxu8^xa>V*gDF_7D+&K>SyV z{z<{>#Qp`*zbLpoB zL4N4Ocv}Up7Ubt|wCnFSfjdRl`xx}QMSo22NkM)j#dZe-Ul)8s@TlNBg1BMR^-b<4 zXjdRORdAMIvEaFaalw^>HG+EoL!3_0w+QO}5cVrXze?~r!RrO}K8boeMA!Qy^xdNC zeG>XZqVr=f=KZ|ji-O-3JRtZZL4M{%9=|21_fhD-7oA^y(O)DuQ!pyXFTm(uA*lCP z=xapZBzTEnr{HG6D+I3+1$m)T z_X`#ZP7^#+FebP_aIxS@!5YD}f)@#1D%c^&uiV(*HouO zE%;5r=LPkB3~pA&?Kg-QmFu*Gi0hrjyHBBt?pNvqwx{jQvGp!5Eh^&3QQCL(@H^j;$Kiw|w<%OpC0nY4{5=M2w# z85QT#nTmJdeN&u<_z54o<9IBytBlx8TpJzLzJ5Sh!Z+f+g1FEJ!Rno)7FYu^xRaeCEVb|H*puQHO23 z{mzE&6sKR_OMB~Wg3jj-r#SWa0TQ2_s>JaoZqk{@3>=`W{@YAFgTou|Dd>Erb_y;j zT?Qe&@s4`p;nBg3w+rXqczf~q#p}o^PJU0rzbU&7#455=awt{pB3zJVCZhVcX95t!Ku0x@mS9(j*s^q-gs{!UKMPdmnk?n zB(8554V*Sm)i)3??pa^QmxU8=y!k7XilRQ_72t5Line)); + 51 .loc 1 155 3 is_stmt 1 view .LVU7 + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + 52 .loc 1 156 3 view .LVU8 + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Assign line number to handle */ + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** hexti->Line = pExtiConfig->Line; + 53 .loc 1 159 3 view .LVU9 + 54 .loc 1 159 28 is_stmt 0 view .LVU10 + 55 000c 0968 ldr r1, [r1] + 56 .LVL1: + 57 .loc 1 159 15 view .LVU11 + 58 000e 0160 str r1, [r0] + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Compute line mask */ + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + 59 .loc 1 162 3 is_stmt 1 view .LVU12 + 60 .loc 1 162 11 is_stmt 0 view .LVU13 + 61 0010 01F01F00 and r0, r1, #31 + 62 .LVL2: + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** maskline = (1uL << linepos); + 63 .loc 1 163 3 is_stmt 1 view .LVU14 + 64 .loc 1 163 12 is_stmt 0 view .LVU15 + 65 0014 0122 movs r2, #1 + ARM GAS /tmp/ccq3Qi7K.s page 5 + + + 66 0016 8240 lsls r2, r2, r0 + 67 .LVL3: + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Configure triggers for configurable lines */ + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + 68 .loc 1 166 3 is_stmt 1 view .LVU16 + 69 .loc 1 166 6 is_stmt 0 view .LVU17 + 70 0018 11F0007F tst r1, #33554432 + 71 001c 15D0 beq .L3 + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + 72 .loc 1 168 5 is_stmt 1 view .LVU18 + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Configure rising trigger */ + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Mask or set line */ + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + 73 .loc 1 172 5 view .LVU19 + 74 .loc 1 172 21 is_stmt 0 view .LVU20 + 75 001e 9C68 ldr r4, [r3, #8] + 76 .loc 1 172 8 view .LVU21 + 77 0020 14F0010F tst r4, #1 + 78 0024 24D0 beq .L4 + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** EXTI->RTSR |= maskline; + 79 .loc 1 174 7 is_stmt 1 view .LVU22 + 80 .loc 1 174 11 is_stmt 0 view .LVU23 + 81 0026 294D ldr r5, .L17 + 82 0028 AC68 ldr r4, [r5, #8] + 83 .loc 1 174 18 view .LVU24 + 84 002a 1443 orrs r4, r4, r2 + 85 002c AC60 str r4, [r5, #8] + 86 .L5: + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** else + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** EXTI->RTSR &= ~maskline; + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Configure falling trigger */ + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Mask or set line */ + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + 87 .loc 1 183 5 is_stmt 1 view .LVU25 + 88 .loc 1 183 21 is_stmt 0 view .LVU26 + 89 002e 9C68 ldr r4, [r3, #8] + 90 .loc 1 183 8 view .LVU27 + 91 0030 14F0020F tst r4, #2 + 92 0034 22D0 beq .L6 + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** EXTI->FTSR |= maskline; + 93 .loc 1 185 7 is_stmt 1 view .LVU28 + 94 .loc 1 185 11 is_stmt 0 view .LVU29 + 95 0036 254D ldr r5, .L17 + 96 0038 EC68 ldr r4, [r5, #12] + 97 .loc 1 185 18 view .LVU30 + 98 003a 1443 orrs r4, r4, r2 + 99 003c EC60 str r4, [r5, #12] + 100 .L7: + ARM GAS /tmp/ccq3Qi7K.s page 6 + + + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** else + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** EXTI->FTSR &= ~maskline; + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Configure gpio port selection in case of gpio exti line */ + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + 101 .loc 1 194 5 is_stmt 1 view .LVU31 + 102 .loc 1 194 28 is_stmt 0 view .LVU32 + 103 003e 1C68 ldr r4, [r3] + 104 0040 04F0C06C and ip, r4, #100663296 + 105 .loc 1 194 8 view .LVU33 + 106 0044 BCF1C06F cmp ip, #100663296 + 107 0048 1ED0 beq .L16 + 108 .LVL4: + 109 .L3: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PIN(linepos)); + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** regval = SYSCFG->EXTICR[linepos >> 2u]; + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Configure interrupt mode : read current mode */ + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Mask or set line */ + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + 110 .loc 1 208 3 is_stmt 1 view .LVU34 + 111 .loc 1 208 19 is_stmt 0 view .LVU35 + 112 004a 5968 ldr r1, [r3, #4] + 113 .loc 1 208 6 view .LVU36 + 114 004c 11F0010F tst r1, #1 + 115 0050 2DD0 beq .L8 + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** EXTI->IMR |= maskline; + 116 .loc 1 210 5 is_stmt 1 view .LVU37 + 117 .loc 1 210 9 is_stmt 0 view .LVU38 + 118 0052 1E48 ldr r0, .L17 + 119 0054 0168 ldr r1, [r0] + 120 .loc 1 210 15 view .LVU39 + 121 0056 1143 orrs r1, r1, r2 + 122 0058 0160 str r1, [r0] + 123 .L9: + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** else + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** EXTI->IMR &= ~maskline; + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Configure event mode : read current mode */ + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Mask or set line */ + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + ARM GAS /tmp/ccq3Qi7K.s page 7 + + + 124 .loc 1 219 3 is_stmt 1 view .LVU40 + 125 .loc 1 219 19 is_stmt 0 view .LVU41 + 126 005a 5B68 ldr r3, [r3, #4] + 127 .LVL5: + 128 .loc 1 219 6 view .LVU42 + 129 005c 13F0020F tst r3, #2 + 130 0060 2BD0 beq .L10 + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** EXTI->EMR |= maskline; + 131 .loc 1 221 5 is_stmt 1 view .LVU43 + 132 .loc 1 221 9 is_stmt 0 view .LVU44 + 133 0062 1A49 ldr r1, .L17 + 134 0064 4B68 ldr r3, [r1, #4] + 135 .loc 1 221 15 view .LVU45 + 136 0066 1343 orrs r3, r3, r2 + 137 0068 4B60 str r3, [r1, #4] + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** else + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** EXTI->EMR &= ~maskline; + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** return HAL_OK; + 138 .loc 1 228 10 view .LVU46 + 139 006a 0020 movs r0, #0 + 140 .L2: + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 141 .loc 1 229 1 view .LVU47 + 142 006c 70BC pop {r4, r5, r6} + 143 .LCFI1: + 144 .cfi_remember_state + 145 .cfi_restore 6 + 146 .cfi_restore 5 + 147 .cfi_restore 4 + 148 .cfi_def_cfa_offset 0 + 149 006e 7047 bx lr + 150 .LVL6: + 151 .L4: + 152 .LCFI2: + 153 .cfi_restore_state + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 154 .loc 1 178 7 is_stmt 1 view .LVU48 + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 155 .loc 1 178 11 is_stmt 0 view .LVU49 + 156 0070 164D ldr r5, .L17 + 157 0072 AC68 ldr r4, [r5, #8] + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 158 .loc 1 178 18 view .LVU50 + 159 0074 24EA0204 bic r4, r4, r2 + 160 0078 AC60 str r4, [r5, #8] + 161 007a D8E7 b .L5 + 162 .L6: + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 163 .loc 1 189 7 is_stmt 1 view .LVU51 + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 164 .loc 1 189 11 is_stmt 0 view .LVU52 + 165 007c 134D ldr r5, .L17 + ARM GAS /tmp/ccq3Qi7K.s page 8 + + + 166 007e EC68 ldr r4, [r5, #12] + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 167 .loc 1 189 18 view .LVU53 + 168 0080 24EA0204 bic r4, r4, r2 + 169 0084 EC60 str r4, [r5, #12] + 170 0086 DAE7 b .L7 + 171 .L16: + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PIN(linepos)); + 172 .loc 1 196 7 is_stmt 1 view .LVU54 + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 173 .loc 1 197 7 view .LVU55 + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 174 .loc 1 199 7 view .LVU56 + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 175 .loc 1 199 39 is_stmt 0 view .LVU57 + 176 0088 8008 lsrs r0, r0, #2 + 177 .LVL7: + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 178 .loc 1 199 14 view .LVU58 + 179 008a 114E ldr r6, .L17+4 + 180 008c 0230 adds r0, r0, #2 + 181 008e 56F82040 ldr r4, [r6, r0, lsl #2] + 182 .LVL8: + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 183 .loc 1 200 7 is_stmt 1 view .LVU59 + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 184 .loc 1 200 80 is_stmt 0 view .LVU60 + 185 0092 01F00301 and r1, r1, #3 + 186 .LVL9: + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 187 .loc 1 200 69 view .LVU61 + 188 0096 8900 lsls r1, r1, #2 + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 189 .loc 1 200 40 view .LVU62 + 190 0098 0F25 movs r5, #15 + 191 009a 8D40 lsls r5, r5, r1 + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 192 .loc 1 200 14 view .LVU63 + 193 009c 24EA0504 bic r4, r4, r5 + 194 .LVL10: + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 195 .loc 1 201 7 is_stmt 1 view .LVU64 + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 196 .loc 1 201 39 is_stmt 0 view .LVU65 + 197 00a0 DD68 ldr r5, [r3, #12] + 198 00a2 05FA01F1 lsl r1, r5, r1 + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 199 .loc 1 201 14 view .LVU66 + 200 00a6 2143 orrs r1, r1, r4 + 201 .LVL11: + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 202 .loc 1 202 7 is_stmt 1 view .LVU67 + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 203 .loc 1 202 37 is_stmt 0 view .LVU68 + 204 00a8 46F82010 str r1, [r6, r0, lsl #2] + 205 00ac CDE7 b .L3 + 206 .LVL12: + ARM GAS /tmp/ccq3Qi7K.s page 9 + + + 207 .L8: + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 208 .loc 1 214 5 is_stmt 1 view .LVU69 + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 209 .loc 1 214 9 is_stmt 0 view .LVU70 + 210 00ae 0748 ldr r0, .L17 + 211 00b0 0168 ldr r1, [r0] + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 212 .loc 1 214 15 view .LVU71 + 213 00b2 21EA0201 bic r1, r1, r2 + 214 00b6 0160 str r1, [r0] + 215 00b8 CFE7 b .L9 + 216 .LVL13: + 217 .L10: + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 218 .loc 1 225 5 is_stmt 1 view .LVU72 + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 219 .loc 1 225 9 is_stmt 0 view .LVU73 + 220 00ba 0449 ldr r1, .L17 + 221 00bc 4B68 ldr r3, [r1, #4] + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 222 .loc 1 225 15 view .LVU74 + 223 00be 23EA0203 bic r3, r3, r2 + 224 00c2 4B60 str r3, [r1, #4] + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 225 .loc 1 228 10 view .LVU75 + 226 00c4 0020 movs r0, #0 + 227 00c6 D1E7 b .L2 + 228 .LVL14: + 229 .L11: + 230 .LCFI3: + 231 .cfi_def_cfa_offset 0 + 232 .cfi_restore 4 + 233 .cfi_restore 5 + 234 .cfi_restore 6 + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 235 .loc 1 151 12 view .LVU76 + 236 00c8 0120 movs r0, #1 + 237 .LVL15: + 238 .loc 1 229 1 view .LVU77 + 239 00ca 7047 bx lr + 240 .L18: + 241 .align 2 + 242 .L17: + 243 00cc 003C0140 .word 1073822720 + 244 00d0 00380140 .word 1073821696 + 245 .cfi_endproc + 246 .LFE141: + 248 .section .text.HAL_EXTI_GetConfigLine,"ax",%progbits + 249 .align 1 + 250 .global HAL_EXTI_GetConfigLine + 251 .syntax unified + 252 .thumb + 253 .thumb_func + 255 HAL_EXTI_GetConfigLine: + 256 .LVL16: + 257 .LFB142: + ARM GAS /tmp/ccq3Qi7K.s page 10 + + + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /** + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @brief Get configuration of a dedicated Exti line. + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @param hexti Exti handle. + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @param pExtiConfig Pointer on structure to store Exti configuration. + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @retval HAL Status. + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** */ + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 258 .loc 1 238 1 is_stmt 1 view -0 + 259 .cfi_startproc + 260 @ args = 0, pretend = 0, frame = 0 + 261 @ frame_needed = 0, uses_anonymous_args = 0 + 262 @ link register save eliminated. + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** uint32_t regval; + 263 .loc 1 239 3 view .LVU79 + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** uint32_t linepos; + 264 .loc 1 240 3 view .LVU80 + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** uint32_t maskline; + 265 .loc 1 241 3 view .LVU81 + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Check null pointer */ + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** if ((hexti == NULL) || (pExtiConfig == NULL)) + 266 .loc 1 244 3 view .LVU82 + 267 .loc 1 244 6 is_stmt 0 view .LVU83 + 268 0000 0029 cmp r1, #0 + 269 0002 18BF it ne + 270 0004 0028 cmpne r0, #0 + 271 0006 44D0 beq .L26 + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** uint32_t regval; + 272 .loc 1 238 1 view .LVU84 + 273 0008 10B4 push {r4} + 274 .LCFI4: + 275 .cfi_def_cfa_offset 4 + 276 .cfi_offset 4, -4 + 277 000a 0B46 mov r3, r1 + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** return HAL_ERROR; + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Check the parameter */ + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 278 .loc 1 250 3 is_stmt 1 view .LVU85 + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Store handle line number to configuration structure */ + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** pExtiConfig->Line = hexti->Line; + 279 .loc 1 253 3 view .LVU86 + 280 .loc 1 253 28 is_stmt 0 view .LVU87 + 281 000c 0468 ldr r4, [r0] + 282 .loc 1 253 21 view .LVU88 + 283 000e 0C60 str r4, [r1] + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Compute line mask */ + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + 284 .loc 1 256 3 is_stmt 1 view .LVU89 + 285 .loc 1 256 11 is_stmt 0 view .LVU90 + 286 0010 04F01F0C and ip, r4, #31 + ARM GAS /tmp/ccq3Qi7K.s page 11 + + + 287 .LVL17: + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** maskline = (1uL << linepos); + 288 .loc 1 257 3 is_stmt 1 view .LVU91 + 289 .loc 1 257 12 is_stmt 0 view .LVU92 + 290 0014 0122 movs r2, #1 + 291 0016 02FA0CF2 lsl r2, r2, ip + 292 .LVL18: + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* 1] Get core mode : interrupt */ + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Check if selected line is enable */ + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** if ((EXTI->IMR & maskline) != 0x00u) + 293 .loc 1 262 3 is_stmt 1 view .LVU93 + 294 .loc 1 262 12 is_stmt 0 view .LVU94 + 295 001a 2148 ldr r0, .L34 + 296 .LVL19: + 297 .loc 1 262 12 view .LVU95 + 298 001c 0068 ldr r0, [r0] + 299 .loc 1 262 6 view .LVU96 + 300 001e 1042 tst r0, r2 + 301 0020 24D0 beq .L21 + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + 302 .loc 1 264 5 is_stmt 1 view .LVU97 + 303 .loc 1 264 23 is_stmt 0 view .LVU98 + 304 0022 0121 movs r1, #1 + 305 .LVL20: + 306 .loc 1 264 23 view .LVU99 + 307 0024 5960 str r1, [r3, #4] + 308 .L22: + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** else + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** pExtiConfig->Mode = EXTI_MODE_NONE; + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Get event mode */ + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Check if selected line is enable */ + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** if ((EXTI->EMR & maskline) != 0x00u) + 309 .loc 1 273 3 is_stmt 1 view .LVU100 + 310 .loc 1 273 12 is_stmt 0 view .LVU101 + 311 0026 1E48 ldr r0, .L34 + 312 0028 4068 ldr r0, [r0, #4] + 313 .loc 1 273 6 view .LVU102 + 314 002a 1042 tst r0, r2 + 315 002c 03D0 beq .L23 + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** pExtiConfig->Mode |= EXTI_MODE_EVENT; + 316 .loc 1 275 5 is_stmt 1 view .LVU103 + 317 .loc 1 275 16 is_stmt 0 view .LVU104 + 318 002e 5868 ldr r0, [r3, #4] + 319 .loc 1 275 23 view .LVU105 + 320 0030 40F00200 orr r0, r0, #2 + 321 0034 5860 str r0, [r3, #4] + 322 .L23: + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + ARM GAS /tmp/ccq3Qi7K.s page 12 + + + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Get default Trigger and GPIOSel configuration */ + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + 323 .loc 1 279 3 is_stmt 1 view .LVU106 + 324 .loc 1 279 24 is_stmt 0 view .LVU107 + 325 0036 0021 movs r1, #0 + 326 0038 9960 str r1, [r3, #8] + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** pExtiConfig->GPIOSel = 0x00u; + 327 .loc 1 280 3 is_stmt 1 view .LVU108 + 328 .loc 1 280 24 is_stmt 0 view .LVU109 + 329 003a D960 str r1, [r3, #12] + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* 2] Get trigger for configurable lines : rising */ + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + 330 .loc 1 283 3 is_stmt 1 view .LVU110 + 331 .loc 1 283 6 is_stmt 0 view .LVU111 + 332 003c 14F0007F tst r4, #33554432 + 333 0040 29D0 beq .L27 + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Check if configuration of selected line is enable */ + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** if ((EXTI->RTSR & maskline) != 0x00u) + 334 .loc 1 286 5 is_stmt 1 view .LVU112 + 335 .loc 1 286 14 is_stmt 0 view .LVU113 + 336 0042 1749 ldr r1, .L34 + 337 0044 8968 ldr r1, [r1, #8] + 338 .loc 1 286 8 view .LVU114 + 339 0046 1142 tst r1, r2 + 340 0048 01D0 beq .L24 + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + 341 .loc 1 288 7 is_stmt 1 view .LVU115 + 342 .loc 1 288 28 is_stmt 0 view .LVU116 + 343 004a 0121 movs r1, #1 + 344 004c 9960 str r1, [r3, #8] + 345 .L24: + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Get falling configuration */ + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Check if configuration of selected line is enable */ + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** if ((EXTI->FTSR & maskline) != 0x00u) + 346 .loc 1 293 5 is_stmt 1 view .LVU117 + 347 .loc 1 293 14 is_stmt 0 view .LVU118 + 348 004e 1449 ldr r1, .L34 + 349 0050 C968 ldr r1, [r1, #12] + 350 .loc 1 293 8 view .LVU119 + 351 0052 1142 tst r1, r2 + 352 0054 03D0 beq .L25 + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + 353 .loc 1 295 7 is_stmt 1 view .LVU120 + 354 .loc 1 295 18 is_stmt 0 view .LVU121 + 355 0056 9A68 ldr r2, [r3, #8] + 356 .LVL21: + 357 .loc 1 295 28 view .LVU122 + 358 0058 42F00202 orr r2, r2, #2 + 359 005c 9A60 str r2, [r3, #8] + 360 .L25: + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + ARM GAS /tmp/ccq3Qi7K.s page 13 + + + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Get Gpio port selection for gpio lines */ + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + 361 .loc 1 299 5 is_stmt 1 view .LVU123 + 362 .loc 1 299 28 is_stmt 0 view .LVU124 + 363 005e 04F0C062 and r2, r4, #100663296 + 364 .loc 1 299 8 view .LVU125 + 365 0062 B2F1C06F cmp r2, #100663296 + 366 0066 04D0 beq .L33 + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PIN(linepos)); + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** regval = SYSCFG->EXTICR[linepos >> 2u]; + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EX + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** return HAL_OK; + 367 .loc 1 308 10 view .LVU126 + 368 0068 0020 movs r0, #0 + 369 006a 15E0 b .L20 + 370 .LVL22: + 371 .L21: + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 372 .loc 1 268 5 is_stmt 1 view .LVU127 + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 373 .loc 1 268 23 is_stmt 0 view .LVU128 + 374 006c 0021 movs r1, #0 + 375 .LVL23: + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 376 .loc 1 268 23 view .LVU129 + 377 006e 5960 str r1, [r3, #4] + 378 0070 D9E7 b .L22 + 379 .LVL24: + 380 .L33: + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 381 .loc 1 301 7 is_stmt 1 view .LVU130 + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EX + 382 .loc 1 303 7 view .LVU131 + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EX + 383 .loc 1 303 39 is_stmt 0 view .LVU132 + 384 0072 4FEA9C01 lsr r1, ip, #2 + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EX + 385 .loc 1 303 14 view .LVU133 + 386 0076 0231 adds r1, r1, #2 + 387 0078 0A4A ldr r2, .L34+4 + 388 007a 52F82110 ldr r1, [r2, r1, lsl #2] + 389 .LVL25: + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 390 .loc 1 304 7 is_stmt 1 view .LVU134 + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 391 .loc 1 304 78 is_stmt 0 view .LVU135 + 392 007e 04F00302 and r2, r4, #3 + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 393 .loc 1 304 67 view .LVU136 + 394 0082 9200 lsls r2, r2, #2 + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + ARM GAS /tmp/ccq3Qi7K.s page 14 + + + 395 .loc 1 304 38 view .LVU137 + 396 0084 21FA02F2 lsr r2, r1, r2 + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 397 .loc 1 304 89 view .LVU138 + 398 0088 02F00F02 and r2, r2, #15 + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 399 .loc 1 304 28 view .LVU139 + 400 008c DA60 str r2, [r3, #12] + 401 .loc 1 308 10 view .LVU140 + 402 008e 0020 movs r0, #0 + 403 0090 02E0 b .L20 + 404 .LVL26: + 405 .L26: + 406 .LCFI5: + 407 .cfi_def_cfa_offset 0 + 408 .cfi_restore 4 + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 409 .loc 1 246 12 view .LVU141 + 410 0092 0120 movs r0, #1 + 411 .LVL27: + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 412 .loc 1 309 1 view .LVU142 + 413 0094 7047 bx lr + 414 .LVL28: + 415 .L27: + 416 .LCFI6: + 417 .cfi_def_cfa_offset 4 + 418 .cfi_offset 4, -4 + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 419 .loc 1 308 10 view .LVU143 + 420 0096 0020 movs r0, #0 + 421 .LVL29: + 422 .L20: + 423 .loc 1 309 1 view .LVU144 + 424 0098 5DF8044B ldr r4, [sp], #4 + 425 .LCFI7: + 426 .cfi_restore 4 + 427 .cfi_def_cfa_offset 0 + 428 009c 7047 bx lr + 429 .L35: + 430 009e 00BF .align 2 + 431 .L34: + 432 00a0 003C0140 .word 1073822720 + 433 00a4 00380140 .word 1073821696 + 434 .cfi_endproc + 435 .LFE142: + 437 .section .text.HAL_EXTI_ClearConfigLine,"ax",%progbits + 438 .align 1 + 439 .global HAL_EXTI_ClearConfigLine + 440 .syntax unified + 441 .thumb + 442 .thumb_func + 444 HAL_EXTI_ClearConfigLine: + 445 .LVL30: + 446 .LFB143: + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /** + ARM GAS /tmp/ccq3Qi7K.s page 15 + + + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @brief Clear whole configuration of a dedicated Exti line. + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @param hexti Exti handle. + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @retval HAL Status. + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** */ + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 447 .loc 1 317 1 is_stmt 1 view -0 + 448 .cfi_startproc + 449 @ args = 0, pretend = 0, frame = 0 + 450 @ frame_needed = 0, uses_anonymous_args = 0 + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** uint32_t regval; + 451 .loc 1 318 3 view .LVU146 + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** uint32_t linepos; + 452 .loc 1 319 3 view .LVU147 + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** uint32_t maskline; + 453 .loc 1 320 3 view .LVU148 + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Check null pointer */ + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** if (hexti == NULL) + 454 .loc 1 323 3 view .LVU149 + 455 .loc 1 323 6 is_stmt 0 view .LVU150 + 456 0000 0028 cmp r0, #0 + 457 0002 37D0 beq .L38 + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** uint32_t regval; + 458 .loc 1 317 1 view .LVU151 + 459 0004 10B5 push {r4, lr} + 460 .LCFI8: + 461 .cfi_def_cfa_offset 8 + 462 .cfi_offset 4, -8 + 463 .cfi_offset 14, -4 + 464 0006 8446 mov ip, r0 + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** return HAL_ERROR; + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Check the parameter */ + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 465 .loc 1 329 3 is_stmt 1 view .LVU152 + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* compute line mask */ + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** linepos = (hexti->Line & EXTI_PIN_MASK); + 466 .loc 1 332 3 view .LVU153 + 467 .loc 1 332 19 is_stmt 0 view .LVU154 + 468 0008 0468 ldr r4, [r0] + 469 .loc 1 332 11 view .LVU155 + 470 000a 04F01F00 and r0, r4, #31 + 471 .LVL31: + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** maskline = (1uL << linepos); + 472 .loc 1 333 3 is_stmt 1 view .LVU156 + 473 .loc 1 333 12 is_stmt 0 view .LVU157 + 474 000e 0123 movs r3, #1 + 475 0010 8340 lsls r3, r3, r0 + 476 .LVL32: + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* 1] Clear interrupt mode */ + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** EXTI->IMR = (EXTI->IMR & ~maskline); + 477 .loc 1 336 3 is_stmt 1 view .LVU158 + ARM GAS /tmp/ccq3Qi7K.s page 16 + + + 478 .loc 1 336 20 is_stmt 0 view .LVU159 + 479 0012 1A4A ldr r2, .L46 + 480 0014 1168 ldr r1, [r2] + 481 .loc 1 336 28 view .LVU160 + 482 0016 6FEA030E mvn lr, r3 + 483 .loc 1 336 26 view .LVU161 + 484 001a 21EA0301 bic r1, r1, r3 + 485 .loc 1 336 13 view .LVU162 + 486 001e 1160 str r1, [r2] + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* 2] Clear event mode */ + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** EXTI->EMR = (EXTI->EMR & ~maskline); + 487 .loc 1 339 3 is_stmt 1 view .LVU163 + 488 .loc 1 339 20 is_stmt 0 view .LVU164 + 489 0020 5168 ldr r1, [r2, #4] + 490 .loc 1 339 26 view .LVU165 + 491 0022 21EA0303 bic r3, r1, r3 + 492 .LVL33: + 493 .loc 1 339 13 view .LVU166 + 494 0026 5360 str r3, [r2, #4] + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* 3] Clear triggers in case of configurable lines */ + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** if ((hexti->Line & EXTI_CONFIG) != 0x00u) + 495 .loc 1 342 3 is_stmt 1 view .LVU167 + 496 .loc 1 342 13 is_stmt 0 view .LVU168 + 497 0028 DCF80030 ldr r3, [ip] + 498 .loc 1 342 6 view .LVU169 + 499 002c 13F0007F tst r3, #33554432 + 500 0030 22D0 beq .L39 + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** EXTI->RTSR = (EXTI->RTSR & ~maskline); + 501 .loc 1 344 5 is_stmt 1 view .LVU170 + 502 .loc 1 344 23 is_stmt 0 view .LVU171 + 503 0032 9368 ldr r3, [r2, #8] + 504 .loc 1 344 30 view .LVU172 + 505 0034 0EEA0303 and r3, lr, r3 + 506 .loc 1 344 16 view .LVU173 + 507 0038 9360 str r3, [r2, #8] + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** EXTI->FTSR = (EXTI->FTSR & ~maskline); + 508 .loc 1 345 5 is_stmt 1 view .LVU174 + 509 .loc 1 345 23 is_stmt 0 view .LVU175 + 510 003a D368 ldr r3, [r2, #12] + 511 .loc 1 345 30 view .LVU176 + 512 003c 0EEA0303 and r3, lr, r3 + 513 .loc 1 345 16 view .LVU177 + 514 0040 D360 str r3, [r2, #12] + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Get Gpio port selection for gpio lines */ + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + 515 .loc 1 348 5 is_stmt 1 view .LVU178 + 516 .loc 1 348 15 is_stmt 0 view .LVU179 + 517 0042 DCF80030 ldr r3, [ip] + 518 .loc 1 348 22 view .LVU180 + 519 0046 03F0C063 and r3, r3, #100663296 + 520 .loc 1 348 8 view .LVU181 + 521 004a B3F1C06F cmp r3, #100663296 + 522 004e 01D0 beq .L45 + ARM GAS /tmp/ccq3Qi7K.s page 17 + + + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PIN(linepos)); + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** regval = SYSCFG->EXTICR[linepos >> 2u]; + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** return HAL_OK; + 523 .loc 1 358 10 view .LVU182 + 524 0050 0020 movs r0, #0 + 525 .LVL34: + 526 .loc 1 358 10 view .LVU183 + 527 0052 12E0 b .L37 + 528 .LVL35: + 529 .L45: + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 530 .loc 1 350 7 is_stmt 1 view .LVU184 + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 531 .loc 1 352 7 view .LVU185 + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 532 .loc 1 352 39 is_stmt 0 view .LVU186 + 533 0054 8008 lsrs r0, r0, #2 + 534 .LVL36: + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 535 .loc 1 352 14 view .LVU187 + 536 0056 0A49 ldr r1, .L46+4 + 537 0058 0230 adds r0, r0, #2 + 538 005a 51F82030 ldr r3, [r1, r0, lsl #2] + 539 .LVL37: + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 540 .loc 1 353 7 is_stmt 1 view .LVU188 + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 541 .loc 1 353 80 is_stmt 0 view .LVU189 + 542 005e 04F00304 and r4, r4, #3 + 543 .LVL38: + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 544 .loc 1 353 69 view .LVU190 + 545 0062 A400 lsls r4, r4, #2 + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 546 .loc 1 353 40 view .LVU191 + 547 0064 0F22 movs r2, #15 + 548 0066 A240 lsls r2, r2, r4 + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 549 .loc 1 353 14 view .LVU192 + 550 0068 23EA0203 bic r3, r3, r2 + 551 .LVL39: + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 552 .loc 1 354 7 is_stmt 1 view .LVU193 + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 553 .loc 1 354 37 is_stmt 0 view .LVU194 + 554 006c 41F82030 str r3, [r1, r0, lsl #2] + 555 .loc 1 358 10 view .LVU195 + 556 0070 0020 movs r0, #0 + 557 0072 02E0 b .L37 + 558 .LVL40: + ARM GAS /tmp/ccq3Qi7K.s page 18 + + + 559 .L38: + 560 .LCFI9: + 561 .cfi_def_cfa_offset 0 + 562 .cfi_restore 4 + 563 .cfi_restore 14 + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 564 .loc 1 325 12 view .LVU196 + 565 0074 0120 movs r0, #1 + 566 .LVL41: + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 567 .loc 1 359 1 view .LVU197 + 568 0076 7047 bx lr + 569 .LVL42: + 570 .L39: + 571 .LCFI10: + 572 .cfi_def_cfa_offset 8 + 573 .cfi_offset 4, -8 + 574 .cfi_offset 14, -4 + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 575 .loc 1 358 10 view .LVU198 + 576 0078 0020 movs r0, #0 + 577 .LVL43: + 578 .L37: + 579 .loc 1 359 1 view .LVU199 + 580 007a 10BD pop {r4, pc} + 581 .L47: + 582 .align 2 + 583 .L46: + 584 007c 003C0140 .word 1073822720 + 585 0080 00380140 .word 1073821696 + 586 .cfi_endproc + 587 .LFE143: + 589 .section .text.HAL_EXTI_RegisterCallback,"ax",%progbits + 590 .align 1 + 591 .global HAL_EXTI_RegisterCallback + 592 .syntax unified + 593 .thumb + 594 .thumb_func + 596 HAL_EXTI_RegisterCallback: + 597 .LVL44: + 598 .LFB144: + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /** + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @brief Register callback for a dedicated Exti line. + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @param hexti Exti handle. + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @param CallbackID User callback identifier. + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @param pPendingCbfn function pointer to be stored as callback. + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @retval HAL Status. + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** */ + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef Callb + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 599 .loc 1 370 1 is_stmt 1 view -0 + 600 .cfi_startproc + 601 @ args = 0, pretend = 0, frame = 0 + 602 @ frame_needed = 0, uses_anonymous_args = 0 + 603 @ link register save eliminated. + ARM GAS /tmp/ccq3Qi7K.s page 19 + + + 604 .loc 1 370 1 is_stmt 0 view .LVU201 + 605 0000 0346 mov r3, r0 + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** HAL_StatusTypeDef status = HAL_OK; + 606 .loc 1 371 3 is_stmt 1 view .LVU202 + 607 .LVL45: + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** switch (CallbackID) + 608 .loc 1 373 3 view .LVU203 + 609 0002 0846 mov r0, r1 + 610 .LVL46: + 611 .loc 1 373 3 is_stmt 0 view .LVU204 + 612 0004 09B9 cbnz r1, .L50 + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** case HAL_EXTI_COMMON_CB_ID: + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** hexti->PendingCallback = pPendingCbfn; + 613 .loc 1 376 7 is_stmt 1 view .LVU205 + 614 .loc 1 376 30 is_stmt 0 view .LVU206 + 615 0006 5A60 str r2, [r3, #4] + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** break; + 616 .loc 1 377 7 is_stmt 1 view .LVU207 + 617 0008 7047 bx lr + 618 .L50: + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** default: + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** status = HAL_ERROR; + 619 .loc 1 380 14 is_stmt 0 view .LVU208 + 620 000a 0120 movs r0, #1 + 621 .LVL47: + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** break; + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** return status; + 622 .loc 1 384 3 is_stmt 1 view .LVU209 + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 623 .loc 1 385 1 is_stmt 0 view .LVU210 + 624 000c 7047 bx lr + 625 .cfi_endproc + 626 .LFE144: + 628 .section .text.HAL_EXTI_GetHandle,"ax",%progbits + 629 .align 1 + 630 .global HAL_EXTI_GetHandle + 631 .syntax unified + 632 .thumb + 633 .thumb_func + 635 HAL_EXTI_GetHandle: + 636 .LVL48: + 637 .LFB145: + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /** + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @brief Store line number as handle private field. + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @param hexti Exti handle. + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @param ExtiLine Exti line number. + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * This parameter can be from 0 to @ref EXTI_LINE_NB. + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @retval HAL Status. + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** */ + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + ARM GAS /tmp/ccq3Qi7K.s page 20 + + + 638 .loc 1 395 1 is_stmt 1 view -0 + 639 .cfi_startproc + 640 @ args = 0, pretend = 0, frame = 0 + 641 @ frame_needed = 0, uses_anonymous_args = 0 + 642 @ link register save eliminated. + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Check the parameters */ + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** assert_param(IS_EXTI_LINE(ExtiLine)); + 643 .loc 1 397 3 view .LVU212 + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Check null pointer */ + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** if (hexti == NULL) + 644 .loc 1 400 3 view .LVU213 + 645 .loc 1 400 6 is_stmt 0 view .LVU214 + 646 0000 10B1 cbz r0, .L53 + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** return HAL_ERROR; + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** else + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Store line number as handle private field */ + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** hexti->Line = ExtiLine; + 647 .loc 1 407 5 is_stmt 1 view .LVU215 + 648 .loc 1 407 17 is_stmt 0 view .LVU216 + 649 0002 0160 str r1, [r0] + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** return HAL_OK; + 650 .loc 1 409 5 is_stmt 1 view .LVU217 + 651 .loc 1 409 12 is_stmt 0 view .LVU218 + 652 0004 0020 movs r0, #0 + 653 .LVL49: + 654 .loc 1 409 12 view .LVU219 + 655 0006 7047 bx lr + 656 .LVL50: + 657 .L53: + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 658 .loc 1 402 12 view .LVU220 + 659 0008 0120 movs r0, #1 + 660 .LVL51: + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 661 .loc 1 411 1 view .LVU221 + 662 000a 7047 bx lr + 663 .cfi_endproc + 664 .LFE145: + 666 .section .text.HAL_EXTI_IRQHandler,"ax",%progbits + 667 .align 1 + 668 .global HAL_EXTI_IRQHandler + 669 .syntax unified + 670 .thumb + 671 .thumb_func + 673 HAL_EXTI_IRQHandler: + 674 .LVL52: + 675 .LFB146: + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /** + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @} + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** */ + ARM GAS /tmp/ccq3Qi7K.s page 21 + + + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /** @addtogroup EXTI_Exported_Functions_Group2 + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @brief EXTI IO functions. + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** @verbatim + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** =============================================================================== + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** ##### IO operation functions ##### + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** =============================================================================== + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** @endverbatim + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @{ + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** */ + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /** + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @brief Handle EXTI interrupt request. + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @param hexti Exti handle. + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @retval none. + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** */ + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 676 .loc 1 435 1 is_stmt 1 view -0 + 677 .cfi_startproc + 678 @ args = 0, pretend = 0, frame = 0 + 679 @ frame_needed = 0, uses_anonymous_args = 0 + 680 .loc 1 435 1 is_stmt 0 view .LVU223 + 681 0000 08B5 push {r3, lr} + 682 .LCFI11: + 683 .cfi_def_cfa_offset 8 + 684 .cfi_offset 3, -8 + 685 .cfi_offset 14, -4 + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** uint32_t regval; + 686 .loc 1 436 3 is_stmt 1 view .LVU224 + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** uint32_t maskline; + 687 .loc 1 437 3 view .LVU225 + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Compute line mask */ + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + 688 .loc 1 440 3 view .LVU226 + 689 .loc 1 440 28 is_stmt 0 view .LVU227 + 690 0002 0368 ldr r3, [r0] + 691 .loc 1 440 35 view .LVU228 + 692 0004 03F01F02 and r2, r3, #31 + 693 .loc 1 440 12 view .LVU229 + 694 0008 0123 movs r3, #1 + 695 000a 9340 lsls r3, r3, r2 + 696 .LVL53: + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Get pending bit */ + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** regval = (EXTI->PR & maskline); + 697 .loc 1 443 3 is_stmt 1 view .LVU230 + 698 .loc 1 443 17 is_stmt 0 view .LVU231 + 699 000c 044A ldr r2, .L57 + 700 000e 5269 ldr r2, [r2, #20] + 701 .LVL54: + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** if (regval != 0x00u) + 702 .loc 1 444 3 is_stmt 1 view .LVU232 + 703 .loc 1 444 6 is_stmt 0 view .LVU233 + ARM GAS /tmp/ccq3Qi7K.s page 22 + + + 704 0010 1A42 tst r2, r3 + 705 0012 04D0 beq .L54 + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Clear pending bit */ + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** EXTI->PR = maskline; + 706 .loc 1 447 5 is_stmt 1 view .LVU234 + 707 .loc 1 447 14 is_stmt 0 view .LVU235 + 708 0014 024A ldr r2, .L57 + 709 .LVL55: + 710 .loc 1 447 14 view .LVU236 + 711 0016 5361 str r3, [r2, #20] + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Call callback */ + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** if (hexti->PendingCallback != NULL) + 712 .loc 1 450 5 is_stmt 1 view .LVU237 + 713 .loc 1 450 14 is_stmt 0 view .LVU238 + 714 0018 4368 ldr r3, [r0, #4] + 715 .LVL56: + 716 .loc 1 450 8 view .LVU239 + 717 001a 03B1 cbz r3, .L54 + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** hexti->PendingCallback(); + 718 .loc 1 452 7 is_stmt 1 view .LVU240 + 719 001c 9847 blx r3 + 720 .LVL57: + 721 .L54: + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 722 .loc 1 455 1 is_stmt 0 view .LVU241 + 723 001e 08BD pop {r3, pc} + 724 .L58: + 725 .align 2 + 726 .L57: + 727 0020 003C0140 .word 1073822720 + 728 .cfi_endproc + 729 .LFE146: + 731 .section .text.HAL_EXTI_GetPending,"ax",%progbits + 732 .align 1 + 733 .global HAL_EXTI_GetPending + 734 .syntax unified + 735 .thumb + 736 .thumb_func + 738 HAL_EXTI_GetPending: + 739 .LVL58: + 740 .LFB147: + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /** + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @brief Get interrupt pending bit of a dedicated line. + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @param hexti Exti handle. + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @param Edge Specify which pending edge as to be checked. + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * This parameter can be one of the following values: + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @arg @ref EXTI_TRIGGER_RISING_FALLING + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * This parameter is kept for compatibility with other series. + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @retval 1 if interrupt is pending else 0. + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** */ + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) + ARM GAS /tmp/ccq3Qi7K.s page 23 + + + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 741 .loc 1 467 1 is_stmt 1 view -0 + 742 .cfi_startproc + 743 @ args = 0, pretend = 0, frame = 0 + 744 @ frame_needed = 0, uses_anonymous_args = 0 + 745 @ link register save eliminated. + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** uint32_t regval; + 746 .loc 1 468 3 view .LVU243 + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** uint32_t linepos; + 747 .loc 1 469 3 view .LVU244 + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** uint32_t maskline; + 748 .loc 1 470 3 view .LVU245 + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Check parameters */ + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 749 .loc 1 473 3 view .LVU246 + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + 750 .loc 1 474 3 view .LVU247 + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** assert_param(IS_EXTI_PENDING_EDGE(Edge)); + 751 .loc 1 475 3 view .LVU248 + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Compute line mask */ + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** linepos = (hexti->Line & EXTI_PIN_MASK); + 752 .loc 1 478 3 view .LVU249 + 753 .loc 1 478 19 is_stmt 0 view .LVU250 + 754 0000 0368 ldr r3, [r0] + 755 .loc 1 478 11 view .LVU251 + 756 0002 03F01F03 and r3, r3, #31 + 757 .LVL59: + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** maskline = (1uL << linepos); + 758 .loc 1 479 3 is_stmt 1 view .LVU252 + 759 .loc 1 479 12 is_stmt 0 view .LVU253 + 760 0006 0122 movs r2, #1 + 761 0008 9A40 lsls r2, r2, r3 + 762 .LVL60: + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* return 1 if bit is set else 0 */ + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** regval = ((EXTI->PR & maskline) >> linepos); + 763 .loc 1 482 3 is_stmt 1 view .LVU254 + 764 .loc 1 482 18 is_stmt 0 view .LVU255 + 765 000a 0249 ldr r1, .L60 + 766 .LVL61: + 767 .loc 1 482 18 view .LVU256 + 768 000c 4869 ldr r0, [r1, #20] + 769 .LVL62: + 770 .loc 1 482 23 view .LVU257 + 771 000e 1040 ands r0, r0, r2 + 772 .LVL63: + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** return regval; + 773 .loc 1 483 3 is_stmt 1 view .LVU258 + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 774 .loc 1 484 1 is_stmt 0 view .LVU259 + 775 0010 D840 lsrs r0, r0, r3 + 776 .LVL64: + 777 .loc 1 484 1 view .LVU260 + 778 0012 7047 bx lr + 779 .L61: + ARM GAS /tmp/ccq3Qi7K.s page 24 + + + 780 .align 2 + 781 .L60: + 782 0014 003C0140 .word 1073822720 + 783 .cfi_endproc + 784 .LFE147: + 786 .section .text.HAL_EXTI_ClearPending,"ax",%progbits + 787 .align 1 + 788 .global HAL_EXTI_ClearPending + 789 .syntax unified + 790 .thumb + 791 .thumb_func + 793 HAL_EXTI_ClearPending: + 794 .LVL65: + 795 .LFB148: + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /** + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @brief Clear interrupt pending bit of a dedicated line. + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @param hexti Exti handle. + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @param Edge Specify which pending edge as to be clear. + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * This parameter can be one of the following values: + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @arg @ref EXTI_TRIGGER_RISING_FALLING + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * This parameter is kept for compatibility with other series. + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @retval None. + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** */ + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 796 .loc 1 496 1 is_stmt 1 view -0 + 797 .cfi_startproc + 798 @ args = 0, pretend = 0, frame = 0 + 799 @ frame_needed = 0, uses_anonymous_args = 0 + 800 @ link register save eliminated. + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** uint32_t maskline; + 801 .loc 1 497 3 view .LVU262 + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Check parameters */ + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 802 .loc 1 500 3 view .LVU263 + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + 803 .loc 1 501 3 view .LVU264 + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** assert_param(IS_EXTI_PENDING_EDGE(Edge)); + 804 .loc 1 502 3 view .LVU265 + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Compute line mask */ + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + 805 .loc 1 505 3 view .LVU266 + 806 .loc 1 505 28 is_stmt 0 view .LVU267 + 807 0000 0268 ldr r2, [r0] + 808 .loc 1 505 35 view .LVU268 + 809 0002 02F01F02 and r2, r2, #31 + 810 .loc 1 505 12 view .LVU269 + 811 0006 0123 movs r3, #1 + 812 0008 9340 lsls r3, r3, r2 + 813 .LVL66: + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Clear Pending bit */ + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** EXTI->PR = maskline; + 814 .loc 1 508 3 is_stmt 1 view .LVU270 + ARM GAS /tmp/ccq3Qi7K.s page 25 + + + 815 .loc 1 508 12 is_stmt 0 view .LVU271 + 816 000a 014A ldr r2, .L63 + 817 000c 5361 str r3, [r2, #20] + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 818 .loc 1 509 1 view .LVU272 + 819 000e 7047 bx lr + 820 .L64: + 821 .align 2 + 822 .L63: + 823 0010 003C0140 .word 1073822720 + 824 .cfi_endproc + 825 .LFE148: + 827 .section .text.HAL_EXTI_GenerateSWI,"ax",%progbits + 828 .align 1 + 829 .global HAL_EXTI_GenerateSWI + 830 .syntax unified + 831 .thumb + 832 .thumb_func + 834 HAL_EXTI_GenerateSWI: + 835 .LVL67: + 836 .LFB149: + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /** + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @brief Generate a software interrupt for a dedicated line. + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @param hexti Exti handle. + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** * @retval None. + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** */ + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** { + 837 .loc 1 517 1 is_stmt 1 view -0 + 838 .cfi_startproc + 839 @ args = 0, pretend = 0, frame = 0 + 840 @ frame_needed = 0, uses_anonymous_args = 0 + 841 @ link register save eliminated. + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** uint32_t maskline; + 842 .loc 1 518 3 view .LVU274 + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Check parameters */ + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 843 .loc 1 521 3 view .LVU275 + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + 844 .loc 1 522 3 view .LVU276 + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Compute line mask */ + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + 845 .loc 1 525 3 view .LVU277 + 846 .loc 1 525 28 is_stmt 0 view .LVU278 + 847 0000 0268 ldr r2, [r0] + 848 .loc 1 525 35 view .LVU279 + 849 0002 02F01F02 and r2, r2, #31 + 850 .loc 1 525 12 view .LVU280 + 851 0006 0123 movs r3, #1 + 852 0008 9340 lsls r3, r3, r2 + 853 .LVL68: + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** /* Generate Software interrupt */ + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** EXTI->SWIER = maskline; + ARM GAS /tmp/ccq3Qi7K.s page 26 + + + 854 .loc 1 528 3 is_stmt 1 view .LVU281 + 855 .loc 1 528 15 is_stmt 0 view .LVU282 + 856 000a 014A ldr r2, .L66 + 857 000c 1361 str r3, [r2, #16] + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c **** } + 858 .loc 1 529 1 view .LVU283 + 859 000e 7047 bx lr + 860 .L67: + 861 .align 2 + 862 .L66: + 863 0010 003C0140 .word 1073822720 + 864 .cfi_endproc + 865 .LFE149: + 867 .text + 868 .Letext0: + 869 .file 2 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 870 .file 3 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 871 .file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 872 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h" + ARM GAS /tmp/ccq3Qi7K.s page 27 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_exti.c + /tmp/ccq3Qi7K.s:20 .text.HAL_EXTI_SetConfigLine:00000000 $t + /tmp/ccq3Qi7K.s:26 .text.HAL_EXTI_SetConfigLine:00000000 HAL_EXTI_SetConfigLine + /tmp/ccq3Qi7K.s:243 .text.HAL_EXTI_SetConfigLine:000000cc $d + /tmp/ccq3Qi7K.s:249 .text.HAL_EXTI_GetConfigLine:00000000 $t + /tmp/ccq3Qi7K.s:255 .text.HAL_EXTI_GetConfigLine:00000000 HAL_EXTI_GetConfigLine + /tmp/ccq3Qi7K.s:432 .text.HAL_EXTI_GetConfigLine:000000a0 $d + /tmp/ccq3Qi7K.s:438 .text.HAL_EXTI_ClearConfigLine:00000000 $t + /tmp/ccq3Qi7K.s:444 .text.HAL_EXTI_ClearConfigLine:00000000 HAL_EXTI_ClearConfigLine + /tmp/ccq3Qi7K.s:584 .text.HAL_EXTI_ClearConfigLine:0000007c $d + /tmp/ccq3Qi7K.s:590 .text.HAL_EXTI_RegisterCallback:00000000 $t + /tmp/ccq3Qi7K.s:596 .text.HAL_EXTI_RegisterCallback:00000000 HAL_EXTI_RegisterCallback + /tmp/ccq3Qi7K.s:629 .text.HAL_EXTI_GetHandle:00000000 $t + /tmp/ccq3Qi7K.s:635 .text.HAL_EXTI_GetHandle:00000000 HAL_EXTI_GetHandle + /tmp/ccq3Qi7K.s:667 .text.HAL_EXTI_IRQHandler:00000000 $t + /tmp/ccq3Qi7K.s:673 .text.HAL_EXTI_IRQHandler:00000000 HAL_EXTI_IRQHandler + /tmp/ccq3Qi7K.s:727 .text.HAL_EXTI_IRQHandler:00000020 $d + /tmp/ccq3Qi7K.s:732 .text.HAL_EXTI_GetPending:00000000 $t + /tmp/ccq3Qi7K.s:738 .text.HAL_EXTI_GetPending:00000000 HAL_EXTI_GetPending + /tmp/ccq3Qi7K.s:782 .text.HAL_EXTI_GetPending:00000014 $d + /tmp/ccq3Qi7K.s:787 .text.HAL_EXTI_ClearPending:00000000 $t + /tmp/ccq3Qi7K.s:793 .text.HAL_EXTI_ClearPending:00000000 HAL_EXTI_ClearPending + /tmp/ccq3Qi7K.s:823 .text.HAL_EXTI_ClearPending:00000010 $d + /tmp/ccq3Qi7K.s:828 .text.HAL_EXTI_GenerateSWI:00000000 $t + /tmp/ccq3Qi7K.s:834 .text.HAL_EXTI_GenerateSWI:00000000 HAL_EXTI_GenerateSWI + /tmp/ccq3Qi7K.s:863 .text.HAL_EXTI_GenerateSWI:00000010 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32f7xx_hal_exti.o b/build/stm32f7xx_hal_exti.o new file mode 100644 index 0000000000000000000000000000000000000000..3ce278d335dff6eadcd06bd8ab403057791896c4 GIT binary patch literal 12992 zcmb_idw5)Bng70X=1eBZgqH=MCMd-tN!xapOKH{RHK5N%5NU9H7a9#HI`_6l2&P>AY z{;^+j=J&mq?|t9z_MYoC9T)7>S}U(;wN_;*rH(fmiL=4LS`|?%m0Gv#3AMI=Zu+6( zorOs~pyyXAz3Rhl74zzvnz_4^)$_WnVQyXbeaY(BeFLPevQ=}dyI%(V@<44eFn@gf zu~WyVR?HnpRzSCLZpAL0tcdA>cPFc$d-mM&u06@B*q#9unSN}#a|tXpoU{V>4gBmx z6|AuS^1#ne91c}nXf*r&86F7CuMF!|)*InJ*6mWs^7e)~ zU3Xw$#jZBg?YT>mZS$78WI)y3Iq#_<1gH4_SqS;Dmlo_O+g#D(LBsDeH(w2SSJF_9IqBihA{-PzULcS`~2< z=CXoVJN#Vd>DPw7K)vfdI--i$A2u#-M#WYEdM!N6);C!8Ux=Z=-(WOcp!+}t*60VI zQL+a=s^p9K(IwZ=XUQ7;+R9#ueg@uQe++VI;xy_Xvq>Q&P&t6Q(_}vmC=EFq3JcJ# z>@vulbHi~cU~tQxA-S=*kcR66s$5qDsAgB=$2rgb72B3O=NHB^ZMS9G#@TkekbyG# zbYen=%ATP24k5$J{vPRF_L(qLsc#0M16B~AR5cFkYNfvdQPm@^q=|&?sSZJ=gO+QC z$}ANDu7OHDNS#-8t`!SWxmI4)&90TI4}k~8wm2H=eXh|{+8A95Rt=5T=xMrsP8Vsa zu`I*Ez&?iNOH5$T=~kMILhyDRON`;?bURxdz;O|d>gyTS^RD?LU>qj%4>bN0m-+W# ze2GlcyPvwu$H90EhgzyHq=5&dUkzYAi$kBtMDc)*GK$y0J%z({_>gO61^m?FaBV;A zGB<;9E)H~Z8;9aXU1b&*I4X>Tojg0>b@E2NndakYz$H|5H^aG6?~X%L?}LqpXyXc> zjZ(33YsSVEdOK|}0ep!z9;1ybbU)Xp-dB}&Eu^^abZ>Ppxih+k3;t;wPvKC@^q%`JP7Of&e~T;`|1_!yaH@Y`JGZ@_pFhdM)7 z;8(wr9iL;MD;Vy_;d8lJ1+Q$S%ge#M2*>gxjOdjElz$cU=W(2A*1)S~h5Z%u>*Sdz z<_)hB167LSOcTT@!`lM783&d(cU!IgBqO;g8_DyaZ-Ih#qqxaL@k=m%io=cKCKE+7 zB5AQ@BO~qYRNJZx;f+Gqr8LZO9#ZYiI6>CTeN|YUP$*!vNijZ=_ zpaIBTMxj_V45f;+?y6$T;yRdaD#lt3=&i-Y(01KYRy%j1l6>fQLB%# zPJMX6uM`ZuF!RE6HG4fhBDb`qt~S`<*16Vm%2}Y`fIyYSyTQno;0US|B3qu*LH24n z4vZUthAfrhS#3dK?C?ck9DZLeZNwaN8ug1o<`issS|YgfkQof-PWGD?EY*CJC{u-6 zrZ5H$4KeN3L&QVECms<#V3FdRe>T+WGQvSq?IF;FzYm^CXhI_8JwUg4rU#zLjhhpS zo)Y%saGjC2J!YAG>eBv?T0~VB8aL^9|P51|f^lh$~Kr4PR$VCg6D|QuO+*JDrlP;G)yXdVK zF?1O)&FAd#4`x*Np_VDtsJRv{%Qm|#BlcCe>@UHgRWE^2II86;)o_&6lq(_7oJeT$ z4p%~8P$EGsQ~VRa9$_-V#A&x~@cY6iJ}-R0g2Mh_0ti&~k1**UxMBjW_{AU>Ev4XM zPzf9t3@U-KnbwlwNI&X|2^rra_QHlCNHc{)bqt4A`w91(YL14Rt#=zi51riTRtX$k zM_s|4f|`_NKzhS8c`U}uWWlZA751KmZdsTGSlCULunQ(zvP!co99R|)UCJFz*8e~3 z9l)iDtxAyNEdAHg5{2h1%y+y3+mRYOm`Keu_3iIo-@0?-p+o(eTEBtdIi6%J*GwEU638Ri{#oR{2 zi4m|dLAh*W%kY(>m1CySzDaAxuBxi4ae_hZX#4%U9Xn`;qhQp6Q5FGN?-ZkI2b-L* z!4{+I1h+16YQP9ZoPyw1qf;4moS%VhPKc}=@zF7L@}ENGXHaSN9&ch7%g|OY8D%;?Hsg-+s|faDeLTI#EfN-isDOh*!3IYMt1O+<`x|XEsCKuB6I|m| zpoJ4$WoFmDG6G+Pk-R1k*y2StQ#~e~gVACdbF{eU9MG6u&R)GcrwnNoLa4{H3IFPQ zjv;Wba=UVqTvYV1q6N#pg#BjW+yQ^n^Q*V5DY^o{#1N8o@(k$OeRwC^i-<9C)S>)3{L;d)JXb$@l-AcMlSFJUu(3%oxVv z3>vBci;@+j&*hbWCRm^@9I*q?w(k$nw^{(8=XuHM}`o& zO7c{oI(xeI_9e!}o0%@pQ#T%>cK5gvkH;CFo|?&eiH#@XDc>~r?(ge$o9v2D4v#0i zhMa)?UELjfFWRrhrzS@unPB)Nx3{COqxa&D9a+0wz584PsVvX<^7_o-L7!;1{i41D zDwP;L7$48}k!Cq8X7L%13*BZ%H*=m}^qh9VQ${Psf8J1*3McCsw(0s0C`;*D-9j7Zqo0A(lhODJ#&3YRbF#?*PEnS_g`N&fZkpj zx)wHa^mt9`Z^t(I^!64o;Tt!nXSZg$K*ti*a*FEsaCCFb9~8+7+pCFUD9 zAZ8VEA5~&LuNIm;t;92^n}y~+s#JyQUZJ^vDls456q-G$RK@C<92!;@&7}=#)i9jR zhl`xQ7hY6kvSe5curUe1Xq!}XtV%@Ze-iu`!T%7%RjTpB z{6v4Pf_$q&`jFstf_DktBltzZ`ve~p_`ei9F<=AXpKoz2 zOj?cLD&a?o&}$XkDEyevoq`t#{}Q43D%C)-6!Se+V2%5YG zyCXWO8W}SZS6ud{!pA!17f^Q0% z{EmHX@;mS>8|{I0g6jku1mp#3)m`B4GsC4y%O)(P?h1IpV3I|WT% z2mfNBFBOanCIqJi(}Eumyhf1UCNO{9F8EnNlkdSdc^-Jb@V_DWsNj==-xW0Z9s0i! z`uBpb2>wk_Lx+C(Q3x?C$j=~1ZxDQ^;5NaXg1ZGT6?~6iLU2s*O2MlI`AG%soBR#@ zjL=5~`FRE9-xPd8@Sg>LAoz?RKfR#-2|<&0SK!M9<}dJ&dd>Vrh}Z{fiO3htL@1p{ zME+_cB2VrjqEQc#Nt*~e7&e2La$}G80$dly5A5<fD1WZ zY#L_&uZ2^MC2Z~w*@o-hU$CrAslzYzkfu$^*Q1Pu&!Dhe|5rWkw|u|PgXa}&6H~hI z>(>i`;F|V|r#AwIU+-%mxJSI=>3swYzaH=RuzfPc>+cux^x7d{j`518$Ll%2y&eb} zJSCv#_h)%}Y3O0wWs0Zw$2`4{L$5lcm9j@{(d0O-rBR>a~$pQ$(m=6*WLIx=Oci61VY{$dxbI{x9917 z8lSOn4|>JZ`@HCR{NvF3caH$lFUwKr`R8LA@p=74lT3WvUkGQ~G{Vm@B$8H-0MaiD w5lb#pUW8sb8sd_`ocrmw90z^+x~E=-!f(Ozif50{t^9gCaUb`Dka^Yr23^=xy#N3J literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_hal_flash.d b/build/stm32f7xx_hal_flash.d new file mode 100644 index 0000000..772e730 --- /dev/null +++ b/build/stm32f7xx_hal_flash.d @@ -0,0 +1,68 @@ +build/stm32f7xx_hal_flash.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/build/stm32f7xx_hal_flash.lst b/build/stm32f7xx_hal_flash.lst new file mode 100644 index 0000000..fd45f26 --- /dev/null +++ b/build/stm32f7xx_hal_flash.lst @@ -0,0 +1,3466 @@ +ARM GAS /tmp/ccfS03PQ.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_hal_flash.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c" + 19 .section .text.FLASH_Program_DoubleWord,"ax",%progbits + 20 .align 1 + 21 .syntax unified + 22 .thumb + 23 .thumb_func + 25 FLASH_Program_DoubleWord: + 26 .LVL0: + 27 .LFB153: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @file stm32f7xx_hal_flash.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief FLASH HAL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * functionalities of the internal FLASH memory: + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * + Program operations functions + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * + Memory Control functions + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * + Peripheral Errors functions + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** @verbatim + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** ============================================================================== + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** ##### FLASH peripheral features ##### + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** ============================================================================== + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** to the Flash memory. It implements the erase and program Flash memory operations + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** and the read and write protection mechanisms. + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** [..] The Flash memory interface accelerates code execution with a system of instruction + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** prefetch and cache lines. + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** [..] The FLASH main features are: + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (+) Flash memory read operations + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (+) Flash memory program/erase operations + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (+) Read / write protections + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (+) Prefetch on I-Code + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (+) 64 cache lines of 128 bits on I-Code + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (+) 8 cache lines of 128 bits on D-Code + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + ARM GAS /tmp/ccfS03PQ.s page 2 + + + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** ##### How to use this driver ##### + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** ============================================================================== + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** [..] + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** This driver provides functions and macros to configure and program the FLASH + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** memory of all STM32F7xx devices. + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (#) FLASH Memory IO Programming functions: + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_FLASH_Lock() functions + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (++) Program functions: byte, half word, word and double word + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (++) There Two modes of programming : + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (+++) Polling mode using HAL_FLASH_Program() function + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (+++) Interrupt mode using HAL_FLASH_Program_IT() function + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (#) Interrupts and flags management functions : + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (++) Wait for last FLASH operation according to its status + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (++) Get error flag status by calling HAL_SetErrorCode() + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** [..] + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** In addition to these functions, this driver includes a set of macros allowing + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** to handle the following operations: + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (+) Set the latency + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (+) Enable/Disable the prefetch buffer + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (+) Enable/Disable the Instruction cache and the Data cache + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (+) Reset the Instruction cache and the Data cache + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (+) Enable/Disable the FLASH interrupts + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (+) Monitor the FLASH flags status + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** [..] + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (@) For any Flash memory program operation (erase or program), the CPU clock frequency + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (HCLK) must be at least 1MHz. + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (@) The contents of the Flash memory are not guaranteed if a device reset occurs during + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** a Flash memory operation. + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (@) Any attempt to read the Flash memory while it is being written or erased, causes the + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** bus to stall. Read operations are processed correctly once the program operation has + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** completed. This means that code or data fetches cannot be performed while a write/erase + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** operation is ongoing. + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** @endverbatim + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** ****************************************************************************** + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @attention + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * Copyright (c) 2017 STMicroelectronics. + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * All rights reserved. + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * This software is licensed under terms that can be found in the LICENSE file in + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * the root directory of this software component. + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** ****************************************************************************** + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Includes ------------------------------------------------------------------*/ + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** #include "stm32f7xx_hal.h" + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** @addtogroup STM32F7xx_HAL_Driver + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @{ + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + ARM GAS /tmp/ccfS03PQ.s page 3 + + + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** @defgroup FLASH FLASH + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief FLASH HAL module driver + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @{ + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** #ifdef HAL_FLASH_MODULE_ENABLED + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Private typedef -----------------------------------------------------------*/ + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Private define ------------------------------------------------------------*/ + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** @addtogroup FLASH_Private_Constants + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @{ + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** #define SECTOR_MASK ((uint32_t)0xFFFFFF07U) + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** #define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */ + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @} + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Private macro -------------------------------------------------------------*/ + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Private variables ---------------------------------------------------------*/ + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** @addtogroup FLASH_Private_Variables + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @{ + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Variable used for Erase sectors under interruption */ + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH_ProcessTypeDef pFlash; + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @} + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Private function prototypes -----------------------------------------------*/ + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** @addtogroup FLASH_Private_Functions + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @{ + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Program operations */ + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void FLASH_Program_Word(uint32_t Address, uint32_t Data); + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void FLASH_Program_Byte(uint32_t Address, uint8_t Data); + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void FLASH_SetErrorCode(void); + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @} + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Exported functions --------------------------------------------------------*/ + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions FLASH Exported Functions + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @{ + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief Programming operation functions + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** @verbatim + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** =============================================================================== + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** ##### Programming operation functions ##### + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** =============================================================================== + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** [..] + ARM GAS /tmp/ccfS03PQ.s page 4 + + + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** This subsection provides a set of functions allowing to manage the FLASH + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** program operations. + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** @endverbatim + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @{ + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief Program byte, halfword, word or double word at a specified address + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @param TypeProgram Indicate the way to program at a specified address. + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * This parameter can be a value of @ref FLASH_Type_Program + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @param Address specifies the address to be programmed. + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @param Data specifies the data to be programmed + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @retval HAL_StatusTypeDef HAL Status + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_ERROR; + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Process Locked */ + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __HAL_LOCK(&pFlash); + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Check the parameters */ + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Wait for last operation to be completed */ + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** if(status == HAL_OK) + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** switch(TypeProgram) + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** case FLASH_TYPEPROGRAM_BYTE : + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /*Program byte (8-bit) at a specified address.*/ + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH_Program_Byte(Address, (uint8_t) Data); + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** case FLASH_TYPEPROGRAM_HALFWORD : + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /*Program halfword (16-bit) at a specified address.*/ + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH_Program_HalfWord(Address, (uint16_t) Data); + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** case FLASH_TYPEPROGRAM_WORD : + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /*Program word (32-bit) at a specified address.*/ + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH_Program_Word(Address, (uint32_t) Data); + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** case FLASH_TYPEPROGRAM_DOUBLEWORD : + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /*Program double word (64-bit) at a specified address.*/ + ARM GAS /tmp/ccfS03PQ.s page 5 + + + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH_Program_DoubleWord(Address, Data); + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** default : + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Wait for last operation to be completed */ + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* If the program operation is completed, disable the PG Bit */ + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR &= (~FLASH_CR_PG); + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Process Unlocked */ + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __HAL_UNLOCK(&pFlash); + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** return status; + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief Program byte, halfword, word or double word at a specified address with interrupt ena + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @param TypeProgram Indicate the way to program at a specified address. + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * This parameter can be a value of @ref FLASH_Type_Program + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @param Address specifies the address to be programmed. + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @param Data specifies the data to be programmed + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @retval HAL Status + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_OK; + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Process Locked */ + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __HAL_LOCK(&pFlash); + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Check the parameters */ + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Enable End of FLASH Operation interrupt */ + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Enable Error source interrupt */ + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Clear pending flags (if any) */ + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\ + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.Address = Address; + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** switch(TypeProgram) + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** case FLASH_TYPEPROGRAM_BYTE : + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /*Program byte (8-bit) at a specified address.*/ + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH_Program_Byte(Address, (uint8_t) Data); + ARM GAS /tmp/ccfS03PQ.s page 6 + + + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** case FLASH_TYPEPROGRAM_HALFWORD : + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /*Program halfword (16-bit) at a specified address.*/ + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH_Program_HalfWord(Address, (uint16_t) Data); + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** case FLASH_TYPEPROGRAM_WORD : + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /*Program word (32-bit) at a specified address.*/ + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH_Program_Word(Address, (uint32_t) Data); + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** case FLASH_TYPEPROGRAM_DOUBLEWORD : + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /*Program double word (64-bit) at a specified address.*/ + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH_Program_DoubleWord(Address, Data); + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** default : + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** return status; + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief This function handles FLASH interrupt request. + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @retval None + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** void HAL_FLASH_IRQHandler(void) + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** uint32_t temp = 0; + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* If the program operation is completed, disable the PG Bit */ + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR &= (~FLASH_CR_PG); + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* If the erase operation is completed, disable the SER Bit */ + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR &= (~FLASH_CR_SER); + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR &= SECTOR_MASK; + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* if the erase operation is completed, disable the MER Bit */ + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR &= (~FLASH_MER_BIT); + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Check FLASH End of Operation flag */ + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Clear FLASH End of Operation pending bit */ + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** switch (pFlash.ProcedureOnGoing) + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** case FLASH_PROC_SECTERASE : + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + ARM GAS /tmp/ccfS03PQ.s page 7 + + + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Nb of sector to erased can be decreased */ + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.NbSectorsToErase--; + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Check if there are still sectors to erase */ + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** if(pFlash.NbSectorsToErase != 0) + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** temp = pFlash.Sector; + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Indicate user which sector has been erased */ + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(temp); + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Increment sector number */ + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** temp = ++pFlash.Sector; + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH_Erase_Sector(temp, pFlash.VoltageForErase); + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** else + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* No more sectors to Erase, user callback can be called.*/ + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Reset Sector and stop Erase sectors procedure */ + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.Sector = temp = 0xFFFFFFFFU; + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(temp); + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Sector Erase procedure is completed */ + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** case FLASH_PROC_MASSERASE : + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* MassErase ended. Return the selected bank : in this product we don't have Banks */ + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(0); + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* MAss Erase procedure is completed */ + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** case FLASH_PROC_PROGRAM : + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /*Program ended. Return the selected address*/ + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(pFlash.Address); + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Programming procedure is completed */ + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** default : + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Check FLASH operation error flags */ + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET) + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** switch (pFlash.ProcedureOnGoing) + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** case FLASH_PROC_SECTERASE : + ARM GAS /tmp/ccfS03PQ.s page 8 + + + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* return the faulty sector */ + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** temp = pFlash.Sector; + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.Sector = 0xFFFFFFFFU; + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** case FLASH_PROC_MASSERASE : + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* No return in case of Mass Erase */ + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** temp = 0; + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** case FLASH_PROC_PROGRAM : + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /*return the faulty address*/ + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** temp = pFlash.Address; + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** default : + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /*Save the Error code*/ + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH_SetErrorCode(); + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* FLASH error interrupt user callback */ + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_FLASH_OperationErrorCallback(temp); + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /*Stop the procedure ongoing */ + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Disable End of FLASH Operation interrupt */ + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP); + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Disable Error source interrupt */ + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR); + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Process Unlocked */ + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __HAL_UNLOCK(&pFlash); + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief FLASH end of operation interrupt callback + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * all the selected sectors have been erased) + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * - Program : Address which was selected for data program + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * - Mass Erase : No return value expected + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @retval None + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + ARM GAS /tmp/ccfS03PQ.s page 9 + + + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** UNUSED(ReturnValue); + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief FLASH operation error interrupt callback + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * all the selected sectors have been erased) + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * - Program : Address which was selected for data program + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * - Mass Erase : No return value expected + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @retval None + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** UNUSED(ReturnValue); + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** the HAL_FLASH_OperationErrorCallback could be implemented in the user file + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @} + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief management functions + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** @verbatim + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** =============================================================================== + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** ##### Peripheral Control functions ##### + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** =============================================================================== + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** [..] + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** This subsection provides a set of functions allowing to control the FLASH + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** memory operations. + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** @endverbatim + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @{ + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief Unlock the FLASH control register access + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @retval HAL Status + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Unlock(void) + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_OK; + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Authorize the FLASH Registers access */ + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** WRITE_REG(FLASH->KEYR, FLASH_KEY1); + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** WRITE_REG(FLASH->KEYR, FLASH_KEY2); + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + ARM GAS /tmp/ccfS03PQ.s page 10 + + + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Verify Flash is unlocked */ + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** status = HAL_ERROR; + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** return status; + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief Locks the FLASH control register access + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @retval HAL Status + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Lock(void) + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Set the LOCK Bit to lock the FLASH Registers access */ + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR |= FLASH_CR_LOCK; + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** return HAL_OK; + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief Unlock the FLASH Option Control Registers access. + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @retval HAL Status + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Authorizes the Option Byte register programming */ + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->OPTKEYR = FLASH_OPT_KEY1; + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->OPTKEYR = FLASH_OPT_KEY2; + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** else + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** return HAL_ERROR; + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** return HAL_OK; + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief Lock the FLASH Option Control Registers access. + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @retval HAL Status + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** return HAL_OK; + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief Launch the option byte loading. + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @retval HAL Status + ARM GAS /tmp/ccfS03PQ.s page 11 + + + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Set the OPTSTRT bit in OPTCR register */ + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT; + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Wait for last operation to be completed */ + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @} + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief Peripheral Errors functions + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** @verbatim + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** =============================================================================== + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** ##### Peripheral Errors functions ##### + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** =============================================================================== + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** [..] + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** This subsection permits to get in run-time Errors of the FLASH peripheral. + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** @endverbatim + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @{ + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief Get the specific FLASH error flag. + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @retval FLASH_ErrorCode: The returned value can be: + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @arg FLASH_ERROR_ERS: FLASH Erasing Sequence error flag + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @arg FLASH_ERROR_WRP: FLASH Write protected error flag + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @arg FLASH_ERROR_OPERATION: FLASH operation Error flag + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** uint32_t HAL_FLASH_GetError(void) + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** return pFlash.ErrorCode; + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @} + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief Wait for a FLASH operation to complete. + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @param Timeout maximum flash operationtimeout + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @retval HAL Status + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** uint32_t tickstart = 0; + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Clear Error Code */ + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + ARM GAS /tmp/ccfS03PQ.s page 12 + + + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** Even if the FLASH operation fails, the BUSY flag will be reset and an error + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** flag will be set */ + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Get tick */ + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** tickstart = HAL_GetTick(); + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** if(Timeout != HAL_MAX_DELAY) + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** return HAL_TIMEOUT; + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET) + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /*Save the error code*/ + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH_SetErrorCode(); + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** return HAL_ERROR; + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Check FLASH End of Operation flag */ + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Clear FLASH End of Operation pending bit */ + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* If there is an error flag set */ + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** return HAL_OK; + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief Program a double word (64-bit) at a specified address. + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @note This function must be used when the device voltage range is from + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * 2.7V to 3.6V and an External Vpp is present. + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @note If an erase and a program operations are requested simultaneously, + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * the erase operation is performed before the program one. + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @param Address specifies the address to be programmed. + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @param Data specifies the data to be programmed. + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @retval None + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 28 .loc 1 652 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .loc 1 652 1 is_stmt 0 view .LVU1 + ARM GAS /tmp/ccfS03PQ.s page 13 + + + 34 0000 10B4 push {r4} + 35 .LCFI0: + 36 .cfi_def_cfa_offset 4 + 37 .cfi_offset 4, -4 + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Check the parameters */ + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** assert_param(IS_FLASH_ADDRESS(Address)); + 38 .loc 1 654 3 is_stmt 1 view .LVU2 + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* If the previous operation is completed, proceed to program the new data */ + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR &= CR_PSIZE_MASK; + 39 .loc 1 657 3 view .LVU3 + 40 .loc 1 657 8 is_stmt 0 view .LVU4 + 41 0002 0B49 ldr r1, .L3 + 42 0004 0C69 ldr r4, [r1, #16] + 43 .loc 1 657 13 view .LVU5 + 44 0006 24F44074 bic r4, r4, #768 + 45 000a 0C61 str r4, [r1, #16] + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; + 46 .loc 1 658 3 is_stmt 1 view .LVU6 + 47 .loc 1 658 8 is_stmt 0 view .LVU7 + 48 000c 0C69 ldr r4, [r1, #16] + 49 .loc 1 658 13 view .LVU8 + 50 000e 44F44074 orr r4, r4, #768 + 51 0012 0C61 str r4, [r1, #16] + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR |= FLASH_CR_PG; + 52 .loc 1 659 3 is_stmt 1 view .LVU9 + 53 .loc 1 659 8 is_stmt 0 view .LVU10 + 54 0014 0C69 ldr r4, [r1, #16] + 55 .loc 1 659 13 view .LVU11 + 56 0016 44F00104 orr r4, r4, #1 + 57 001a 0C61 str r4, [r1, #16] + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Program first word */ + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** *(__IO uint32_t*)Address = (uint32_t)Data; + 58 .loc 1 662 3 is_stmt 1 view .LVU12 + 59 .loc 1 662 28 is_stmt 0 view .LVU13 + 60 001c 0260 str r2, [r0] + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Barrier to ensure programming is performed in 2 steps, in right order + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** (independently of compiler optimization behavior) */ + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __ISB(); + 61 .loc 1 665 3 is_stmt 1 view .LVU14 + 62 .LBB12: + 63 .LBI12: + 64 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + ARM GAS /tmp/ccfS03PQ.s page 14 + + + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + ARM GAS /tmp/ccfS03PQ.s page 15 + + + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + ARM GAS /tmp/ccfS03PQ.s page 16 + + + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccfS03PQ.s page 17 + + + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccfS03PQ.s page 18 + + + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + ARM GAS /tmp/ccfS03PQ.s page 19 + + + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccfS03PQ.s page 20 + + + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + ARM GAS /tmp/ccfS03PQ.s page 21 + + + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccfS03PQ.s page 22 + + + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccfS03PQ.s page 23 + + + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccfS03PQ.s page 24 + + + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + ARM GAS /tmp/ccfS03PQ.s page 25 + + + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + ARM GAS /tmp/ccfS03PQ.s page 26 + + + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccfS03PQ.s page 27 + + + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccfS03PQ.s page 28 + + + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 65 .loc 2 866 27 view .LVU15 + 66 .LBB13: + ARM GAS /tmp/ccfS03PQ.s page 29 + + + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 67 .loc 2 868 3 view .LVU16 + 68 .syntax unified + 69 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 70 001e BFF36F8F isb 0xF + 71 @ 0 "" 2 + 72 .thumb + 73 .syntax unified + 74 .LBE13: + 75 .LBE12: + 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Program second word */ + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32); + 76 .loc 1 668 3 view .LVU17 + 77 .loc 1 668 32 is_stmt 0 view .LVU18 + 78 0022 4360 str r3, [r0, #4] + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Data synchronous Barrier (DSB) Just after the write operation + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** This will force the CPU to respect the sequence of instruction (no optimization).*/ + 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __DSB(); + 79 .loc 1 672 3 is_stmt 1 view .LVU19 + 80 .LBB14: + 81 .LBI14: + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 82 .loc 2 877 27 view .LVU20 + 83 .LBB15: + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 84 .loc 2 879 3 view .LVU21 + 85 .syntax unified + 86 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 87 0024 BFF34F8F dsb 0xF + 88 @ 0 "" 2 + 89 .thumb + 90 .syntax unified + 91 .LBE15: + 92 .LBE14: + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 93 .loc 1 673 1 is_stmt 0 view .LVU22 + 94 0028 5DF8044B ldr r4, [sp], #4 + 95 .LCFI1: + 96 .cfi_restore 4 + 97 .cfi_def_cfa_offset 0 + 98 002c 7047 bx lr + 99 .L4: + 100 002e 00BF .align 2 + 101 .L3: + 102 0030 003C0240 .word 1073888256 + ARM GAS /tmp/ccfS03PQ.s page 30 + + + 103 .cfi_endproc + 104 .LFE153: + 106 .section .text.FLASH_Program_Word,"ax",%progbits + 107 .align 1 + 108 .syntax unified + 109 .thumb + 110 .thumb_func + 112 FLASH_Program_Word: + 113 .LVL1: + 114 .LFB154: + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief Program word (32-bit) at a specified address. + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @note This function must be used when the device voltage range is from + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * 2.7V to 3.3V. + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @note If an erase and a program operations are requested simultaneously, + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * the erase operation is performed before the program one. + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @param Address specifies the address to be programmed. + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @param Data specifies the data to be programmed. + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @retval None + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void FLASH_Program_Word(uint32_t Address, uint32_t Data) + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 115 .loc 1 689 1 is_stmt 1 view -0 + 116 .cfi_startproc + 117 @ args = 0, pretend = 0, frame = 0 + 118 @ frame_needed = 0, uses_anonymous_args = 0 + 119 @ link register save eliminated. + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Check the parameters */ + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** assert_param(IS_FLASH_ADDRESS(Address)); + 120 .loc 1 691 3 view .LVU24 + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* If the previous operation is completed, proceed to program the new data */ + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR &= CR_PSIZE_MASK; + 121 .loc 1 694 3 view .LVU25 + 122 .loc 1 694 8 is_stmt 0 view .LVU26 + 123 0000 084B ldr r3, .L6 + 124 0002 1A69 ldr r2, [r3, #16] + 125 .loc 1 694 13 view .LVU27 + 126 0004 22F44072 bic r2, r2, #768 + 127 0008 1A61 str r2, [r3, #16] + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR |= FLASH_PSIZE_WORD; + 128 .loc 1 695 3 is_stmt 1 view .LVU28 + 129 .loc 1 695 8 is_stmt 0 view .LVU29 + 130 000a 1A69 ldr r2, [r3, #16] + 131 .loc 1 695 13 view .LVU30 + 132 000c 42F40072 orr r2, r2, #512 + 133 0010 1A61 str r2, [r3, #16] + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR |= FLASH_CR_PG; + 134 .loc 1 696 3 is_stmt 1 view .LVU31 + 135 .loc 1 696 8 is_stmt 0 view .LVU32 + 136 0012 1A69 ldr r2, [r3, #16] + 137 .loc 1 696 13 view .LVU33 + 138 0014 42F00102 orr r2, r2, #1 + ARM GAS /tmp/ccfS03PQ.s page 31 + + + 139 0018 1A61 str r2, [r3, #16] + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** *(__IO uint32_t*)Address = Data; + 140 .loc 1 698 3 is_stmt 1 view .LVU34 + 141 .loc 1 698 28 is_stmt 0 view .LVU35 + 142 001a 0160 str r1, [r0] + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Data synchronous Barrier (DSB) Just after the write operation + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** This will force the CPU to respect the sequence of instruction (no optimization).*/ + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __DSB(); + 143 .loc 1 702 3 is_stmt 1 view .LVU36 + 144 .LBB16: + 145 .LBI16: + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 146 .loc 2 877 27 view .LVU37 + 147 .LBB17: + 148 .loc 2 879 3 view .LVU38 + 149 .syntax unified + 150 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 151 001c BFF34F8F dsb 0xF + 152 @ 0 "" 2 + 153 .thumb + 154 .syntax unified + 155 .LBE17: + 156 .LBE16: + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 157 .loc 1 703 1 is_stmt 0 view .LVU39 + 158 0020 7047 bx lr + 159 .L7: + 160 0022 00BF .align 2 + 161 .L6: + 162 0024 003C0240 .word 1073888256 + 163 .cfi_endproc + 164 .LFE154: + 166 .section .text.FLASH_Program_HalfWord,"ax",%progbits + 167 .align 1 + 168 .syntax unified + 169 .thumb + 170 .thumb_func + 172 FLASH_Program_HalfWord: + 173 .LVL2: + 174 .LFB155: + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief Program a half-word (16-bit) at a specified address. + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @note This function must be used when the device voltage range is from + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * 2.1V to 3.6V. + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @note If an erase and a program operations are requested simultaneously, + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * the erase operation is performed before the program one. + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @param Address specifies the address to be programmed. + 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @param Data specifies the data to be programmed. + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @retval None + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + ARM GAS /tmp/ccfS03PQ.s page 32 + + + 175 .loc 1 718 1 is_stmt 1 view -0 + 176 .cfi_startproc + 177 @ args = 0, pretend = 0, frame = 0 + 178 @ frame_needed = 0, uses_anonymous_args = 0 + 179 @ link register save eliminated. + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Check the parameters */ + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** assert_param(IS_FLASH_ADDRESS(Address)); + 180 .loc 1 720 3 view .LVU41 + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* If the previous operation is completed, proceed to program the new data */ + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR &= CR_PSIZE_MASK; + 181 .loc 1 723 3 view .LVU42 + 182 .loc 1 723 8 is_stmt 0 view .LVU43 + 183 0000 084B ldr r3, .L9 + 184 0002 1A69 ldr r2, [r3, #16] + 185 .loc 1 723 13 view .LVU44 + 186 0004 22F44072 bic r2, r2, #768 + 187 0008 1A61 str r2, [r3, #16] + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR |= FLASH_PSIZE_HALF_WORD; + 188 .loc 1 724 3 is_stmt 1 view .LVU45 + 189 .loc 1 724 8 is_stmt 0 view .LVU46 + 190 000a 1A69 ldr r2, [r3, #16] + 191 .loc 1 724 13 view .LVU47 + 192 000c 42F48072 orr r2, r2, #256 + 193 0010 1A61 str r2, [r3, #16] + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR |= FLASH_CR_PG; + 194 .loc 1 725 3 is_stmt 1 view .LVU48 + 195 .loc 1 725 8 is_stmt 0 view .LVU49 + 196 0012 1A69 ldr r2, [r3, #16] + 197 .loc 1 725 13 view .LVU50 + 198 0014 42F00102 orr r2, r2, #1 + 199 0018 1A61 str r2, [r3, #16] + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** *(__IO uint16_t*)Address = Data; + 200 .loc 1 727 3 is_stmt 1 view .LVU51 + 201 .loc 1 727 28 is_stmt 0 view .LVU52 + 202 001a 0180 strh r1, [r0] @ movhi + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Data synchronous Barrier (DSB) Just after the write operation + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** This will force the CPU to respect the sequence of instruction (no optimization).*/ + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __DSB(); + 203 .loc 1 731 3 is_stmt 1 view .LVU53 + 204 .LBB18: + 205 .LBI18: + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 206 .loc 2 877 27 view .LVU54 + 207 .LBB19: + 208 .loc 2 879 3 view .LVU55 + 209 .syntax unified + 210 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 211 001c BFF34F8F dsb 0xF + 212 @ 0 "" 2 + 213 .thumb + 214 .syntax unified + 215 .LBE19: + 216 .LBE18: + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + ARM GAS /tmp/ccfS03PQ.s page 33 + + + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 217 .loc 1 733 1 is_stmt 0 view .LVU56 + 218 0020 7047 bx lr + 219 .L10: + 220 0022 00BF .align 2 + 221 .L9: + 222 0024 003C0240 .word 1073888256 + 223 .cfi_endproc + 224 .LFE155: + 226 .section .text.FLASH_Program_Byte,"ax",%progbits + 227 .align 1 + 228 .syntax unified + 229 .thumb + 230 .thumb_func + 232 FLASH_Program_Byte: + 233 .LVL3: + 234 .LFB156: + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief Program byte (8-bit) at a specified address. + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @note This function must be used when the device voltage range is from + 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * 1.7V to 3.6V. + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @note If an erase and a program operations are requested simultaneously, + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * the erase operation is performed before the program one. + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @param Address specifies the address to be programmed. + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @param Data specifies the data to be programmed. + 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @retval None + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void FLASH_Program_Byte(uint32_t Address, uint8_t Data) + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 235 .loc 1 748 1 is_stmt 1 view -0 + 236 .cfi_startproc + 237 @ args = 0, pretend = 0, frame = 0 + 238 @ frame_needed = 0, uses_anonymous_args = 0 + 239 @ link register save eliminated. + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Check the parameters */ + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** assert_param(IS_FLASH_ADDRESS(Address)); + 240 .loc 1 750 3 view .LVU58 + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* If the previous operation is completed, proceed to program the new data */ + 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR &= CR_PSIZE_MASK; + 241 .loc 1 753 3 view .LVU59 + 242 .loc 1 753 8 is_stmt 0 view .LVU60 + 243 0000 074B ldr r3, .L12 + 244 0002 1A69 ldr r2, [r3, #16] + 245 .loc 1 753 13 view .LVU61 + 246 0004 22F44072 bic r2, r2, #768 + 247 0008 1A61 str r2, [r3, #16] + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR |= FLASH_PSIZE_BYTE; + 248 .loc 1 754 3 is_stmt 1 view .LVU62 + 249 .loc 1 754 8 is_stmt 0 view .LVU63 + 250 000a 1A69 ldr r2, [r3, #16] + 251 .loc 1 754 13 view .LVU64 + 252 000c 1A61 str r2, [r3, #16] + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR |= FLASH_CR_PG; + ARM GAS /tmp/ccfS03PQ.s page 34 + + + 253 .loc 1 755 3 is_stmt 1 view .LVU65 + 254 .loc 1 755 8 is_stmt 0 view .LVU66 + 255 000e 1A69 ldr r2, [r3, #16] + 256 .loc 1 755 13 view .LVU67 + 257 0010 42F00102 orr r2, r2, #1 + 258 0014 1A61 str r2, [r3, #16] + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** *(__IO uint8_t*)Address = Data; + 259 .loc 1 757 3 is_stmt 1 view .LVU68 + 260 .loc 1 757 27 is_stmt 0 view .LVU69 + 261 0016 0170 strb r1, [r0] + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Data synchronous Barrier (DSB) Just after the write operation + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** This will force the CPU to respect the sequence of instruction (no optimization).*/ + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __DSB(); + 262 .loc 1 761 3 is_stmt 1 view .LVU70 + 263 .LBB20: + 264 .LBI20: + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 265 .loc 2 877 27 view .LVU71 + 266 .LBB21: + 267 .loc 2 879 3 view .LVU72 + 268 .syntax unified + 269 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 270 0018 BFF34F8F dsb 0xF + 271 @ 0 "" 2 + 272 .thumb + 273 .syntax unified + 274 .LBE21: + 275 .LBE20: + 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 276 .loc 1 762 1 is_stmt 0 view .LVU73 + 277 001c 7047 bx lr + 278 .L13: + 279 001e 00BF .align 2 + 280 .L12: + 281 0020 003C0240 .word 1073888256 + 282 .cfi_endproc + 283 .LFE156: + 285 .section .text.FLASH_SetErrorCode,"ax",%progbits + 286 .align 1 + 287 .syntax unified + 288 .thumb + 289 .thumb_func + 291 FLASH_SetErrorCode: + 292 .LFB157: + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /** + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @brief Set the specific FLASH error flag. + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** * @retval None + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** */ + 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** static void FLASH_SetErrorCode(void) + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 293 .loc 1 769 1 is_stmt 1 view -0 + 294 .cfi_startproc + 295 @ args = 0, pretend = 0, frame = 0 + 296 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccfS03PQ.s page 35 + + + 297 @ link register save eliminated. + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET) + 298 .loc 1 770 3 view .LVU75 + 299 .loc 1 770 6 is_stmt 0 view .LVU76 + 300 0000 1A4B ldr r3, .L20 + 301 0002 DB68 ldr r3, [r3, #12] + 302 .loc 1 770 5 view .LVU77 + 303 0004 13F0020F tst r3, #2 + 304 0008 04D0 beq .L15 + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION; + 305 .loc 1 772 5 is_stmt 1 view .LVU78 + 306 .loc 1 772 11 is_stmt 0 view .LVU79 + 307 000a 194A ldr r2, .L20+4 + 308 000c 9369 ldr r3, [r2, #24] + 309 .loc 1 772 22 view .LVU80 + 310 000e 43F02003 orr r3, r3, #32 + 311 0012 9361 str r3, [r2, #24] + 312 .L15: + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) + 313 .loc 1 775 3 is_stmt 1 view .LVU81 + 314 .loc 1 775 6 is_stmt 0 view .LVU82 + 315 0014 154B ldr r3, .L20 + 316 0016 DB68 ldr r3, [r3, #12] + 317 .loc 1 775 5 view .LVU83 + 318 0018 13F0100F tst r3, #16 + 319 001c 04D0 beq .L16 + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + 320 .loc 1 777 4 is_stmt 1 view .LVU84 + 321 .loc 1 777 10 is_stmt 0 view .LVU85 + 322 001e 144A ldr r2, .L20+4 + 323 0020 9369 ldr r3, [r2, #24] + 324 .loc 1 777 21 view .LVU86 + 325 0022 43F01003 orr r3, r3, #16 + 326 0026 9361 str r3, [r2, #24] + 327 .L16: + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) + 328 .loc 1 780 3 is_stmt 1 view .LVU87 + 329 .loc 1 780 6 is_stmt 0 view .LVU88 + 330 0028 104B ldr r3, .L20 + 331 002a DB68 ldr r3, [r3, #12] + 332 .loc 1 780 5 view .LVU89 + 333 002c 13F0200F tst r3, #32 + 334 0030 04D0 beq .L17 + 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; + 335 .loc 1 782 4 is_stmt 1 view .LVU90 + 336 .loc 1 782 10 is_stmt 0 view .LVU91 + 337 0032 0F4A ldr r2, .L20+4 + 338 0034 9369 ldr r3, [r2, #24] + 339 .loc 1 782 21 view .LVU92 + 340 0036 43F00803 orr r3, r3, #8 + ARM GAS /tmp/ccfS03PQ.s page 36 + + + 341 003a 9361 str r3, [r2, #24] + 342 .L17: + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET) + 343 .loc 1 785 3 is_stmt 1 view .LVU93 + 344 .loc 1 785 6 is_stmt 0 view .LVU94 + 345 003c 0B4B ldr r3, .L20 + 346 003e DB68 ldr r3, [r3, #12] + 347 .loc 1 785 5 view .LVU95 + 348 0040 13F0400F tst r3, #64 + 349 0044 04D0 beq .L18 + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP; + 350 .loc 1 787 5 is_stmt 1 view .LVU96 + 351 .loc 1 787 11 is_stmt 0 view .LVU97 + 352 0046 0A4A ldr r2, .L20+4 + 353 0048 9369 ldr r3, [r2, #24] + 354 .loc 1 787 22 view .LVU98 + 355 004a 43F00403 orr r3, r3, #4 + 356 004e 9361 str r3, [r2, #24] + 357 .L18: + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ERSERR) != RESET) + 358 .loc 1 790 3 is_stmt 1 view .LVU99 + 359 .loc 1 790 6 is_stmt 0 view .LVU100 + 360 0050 064B ldr r3, .L20 + 361 0052 DB68 ldr r3, [r3, #12] + 362 .loc 1 790 5 view .LVU101 + 363 0054 13F0800F tst r3, #128 + 364 0058 04D0 beq .L19 + 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS; + 365 .loc 1 792 5 is_stmt 1 view .LVU102 + 366 .loc 1 792 11 is_stmt 0 view .LVU103 + 367 005a 054A ldr r2, .L20+4 + 368 005c 9369 ldr r3, [r2, #24] + 369 .loc 1 792 22 view .LVU104 + 370 005e 43F00203 orr r3, r3, #2 + 371 0062 9361 str r3, [r2, #24] + 372 .L19: + 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** #if defined (FLASH_OPTCR2_PCROP) + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** #endif /* FLASH_OPTCR2_PCROP */ + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Clear error programming flags */ + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); + 373 .loc 1 803 3 is_stmt 1 view .LVU105 + 374 0064 014B ldr r3, .L20 + 375 0066 F222 movs r2, #242 + 376 0068 DA60 str r2, [r3, #12] + ARM GAS /tmp/ccfS03PQ.s page 37 + + + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 377 .loc 1 804 1 is_stmt 0 view .LVU106 + 378 006a 7047 bx lr + 379 .L21: + 380 .align 2 + 381 .L20: + 382 006c 003C0240 .word 1073888256 + 383 0070 00000000 .word pFlash + 384 .cfi_endproc + 385 .LFE157: + 387 .section .text.HAL_FLASH_Program_IT,"ax",%progbits + 388 .align 1 + 389 .global HAL_FLASH_Program_IT + 390 .syntax unified + 391 .thumb + 392 .thumb_func + 394 HAL_FLASH_Program_IT: + 395 .LVL4: + 396 .LFB142: + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_OK; + 397 .loc 1 232 1 is_stmt 1 view -0 + 398 .cfi_startproc + 399 @ args = 0, pretend = 0, frame = 0 + 400 @ frame_needed = 0, uses_anonymous_args = 0 + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_OK; + 401 .loc 1 232 1 is_stmt 0 view .LVU108 + 402 0000 70B5 push {r4, r5, r6, lr} + 403 .LCFI2: + 404 .cfi_def_cfa_offset 16 + 405 .cfi_offset 4, -16 + 406 .cfi_offset 5, -12 + 407 .cfi_offset 6, -8 + 408 .cfi_offset 14, -4 + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 409 .loc 1 233 3 is_stmt 1 view .LVU109 + 410 .LVL5: + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 411 .loc 1 236 3 view .LVU110 + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 412 .loc 1 236 3 view .LVU111 + 413 0002 1A4C ldr r4, .L32 + 414 0004 247D ldrb r4, [r4, #20] @ zero_extendqisi2 + 415 0006 012C cmp r4, #1 + 416 0008 2CD0 beq .L29 + 417 000a 8446 mov ip, r0 + 418 000c 0846 mov r0, r1 + 419 .LVL6: + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 420 .loc 1 236 3 discriminator 2 view .LVU112 + 421 000e 174D ldr r5, .L32 + 422 0010 0121 movs r1, #1 + 423 .LVL7: + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 424 .loc 1 236 3 is_stmt 0 discriminator 2 view .LVU113 + 425 0012 2975 strb r1, [r5, #20] + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 426 .loc 1 236 3 is_stmt 1 discriminator 2 view .LVU114 + ARM GAS /tmp/ccfS03PQ.s page 38 + + + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 427 .loc 1 239 3 view .LVU115 + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 428 .loc 1 242 3 view .LVU116 + 429 0014 164C ldr r4, .L32+4 + 430 0016 2669 ldr r6, [r4, #16] + 431 0018 46F08076 orr r6, r6, #16777216 + 432 001c 2661 str r6, [r4, #16] + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 433 .loc 1 245 3 view .LVU117 + 434 001e 2669 ldr r6, [r4, #16] + 435 0020 46F00076 orr r6, r6, #33554432 + 436 0024 2661 str r6, [r4, #16] + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); + 437 .loc 1 248 3 view .LVU118 + 438 0026 F321 movs r1, #243 + 439 0028 E160 str r1, [r4, #12] + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.Address = Address; + 440 .loc 1 251 3 view .LVU119 + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.Address = Address; + 441 .loc 1 251 27 is_stmt 0 view .LVU120 + 442 002a 0321 movs r1, #3 + 443 002c 2970 strb r1, [r5] + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 444 .loc 1 252 3 is_stmt 1 view .LVU121 + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 445 .loc 1 252 18 is_stmt 0 view .LVU122 + 446 002e 2861 str r0, [r5, #16] + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 447 .loc 1 254 3 is_stmt 1 view .LVU123 + 448 0030 BCF1030F cmp ip, #3 + 449 0034 18D8 bhi .L30 + 450 0036 DFE80CF0 tbb [pc, ip] + 451 .L25: + 452 003a 02 .byte (.L28-.L25)/2 + 453 003b 07 .byte (.L27-.L25)/2 + 454 003c 0C .byte (.L26-.L25)/2 + 455 003d 11 .byte (.L24-.L25)/2 + 456 .p2align 1 + 457 .L28: + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 458 .loc 1 259 7 view .LVU124 + 459 003e D1B2 uxtb r1, r2 + 460 0040 FFF7FEFF bl FLASH_Program_Byte + 461 .LVL8: + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 462 .loc 1 260 7 view .LVU125 + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 463 .loc 1 286 10 is_stmt 0 view .LVU126 + 464 0044 0020 movs r0, #0 + 465 .L23: + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 466 .loc 1 287 1 view .LVU127 + 467 0046 70BD pop {r4, r5, r6, pc} + 468 .LVL9: + 469 .L27: + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + ARM GAS /tmp/ccfS03PQ.s page 39 + + + 470 .loc 1 266 7 is_stmt 1 view .LVU128 + 471 0048 91B2 uxth r1, r2 + 472 004a FFF7FEFF bl FLASH_Program_HalfWord + 473 .LVL10: + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 474 .loc 1 267 7 view .LVU129 + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 475 .loc 1 286 10 is_stmt 0 view .LVU130 + 476 004e 0020 movs r0, #0 + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 477 .loc 1 267 7 view .LVU131 + 478 0050 F9E7 b .L23 + 479 .LVL11: + 480 .L26: + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 481 .loc 1 273 7 is_stmt 1 view .LVU132 + 482 0052 1146 mov r1, r2 + 483 0054 FFF7FEFF bl FLASH_Program_Word + 484 .LVL12: + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 485 .loc 1 274 7 view .LVU133 + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 486 .loc 1 286 10 is_stmt 0 view .LVU134 + 487 0058 0020 movs r0, #0 + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 488 .loc 1 274 7 view .LVU135 + 489 005a F4E7 b .L23 + 490 .LVL13: + 491 .L24: + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 492 .loc 1 280 7 is_stmt 1 view .LVU136 + 493 005c FFF7FEFF bl FLASH_Program_DoubleWord + 494 .LVL14: + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 495 .loc 1 281 7 view .LVU137 + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 496 .loc 1 286 10 is_stmt 0 view .LVU138 + 497 0060 0020 movs r0, #0 + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 498 .loc 1 281 7 view .LVU139 + 499 0062 F0E7 b .L23 + 500 .LVL15: + 501 .L29: + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 502 .loc 1 236 3 discriminator 1 view .LVU140 + 503 0064 0220 movs r0, #2 + 504 .LVL16: + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 505 .loc 1 236 3 discriminator 1 view .LVU141 + 506 0066 EEE7 b .L23 + 507 .LVL17: + 508 .L30: + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 509 .loc 1 254 3 view .LVU142 + 510 0068 0020 movs r0, #0 + 511 .LVL18: + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + ARM GAS /tmp/ccfS03PQ.s page 40 + + + 512 .loc 1 254 3 view .LVU143 + 513 006a ECE7 b .L23 + 514 .L33: + 515 .align 2 + 516 .L32: + 517 006c 00000000 .word pFlash + 518 0070 003C0240 .word 1073888256 + 519 .cfi_endproc + 520 .LFE142: + 522 .section .text.HAL_FLASH_EndOfOperationCallback,"ax",%progbits + 523 .align 1 + 524 .weak HAL_FLASH_EndOfOperationCallback + 525 .syntax unified + 526 .thumb + 527 .thumb_func + 529 HAL_FLASH_EndOfOperationCallback: + 530 .LVL19: + 531 .LFB144: + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + 532 .loc 1 429 1 is_stmt 1 view -0 + 533 .cfi_startproc + 534 @ args = 0, pretend = 0, frame = 0 + 535 @ frame_needed = 0, uses_anonymous_args = 0 + 536 @ link register save eliminated. + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 537 .loc 1 431 3 view .LVU145 + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 538 .loc 1 435 1 is_stmt 0 view .LVU146 + 539 0000 7047 bx lr + 540 .cfi_endproc + 541 .LFE144: + 543 .section .text.HAL_FLASH_OperationErrorCallback,"ax",%progbits + 544 .align 1 + 545 .weak HAL_FLASH_OperationErrorCallback + 546 .syntax unified + 547 .thumb + 548 .thumb_func + 550 HAL_FLASH_OperationErrorCallback: + 551 .LVL20: + 552 .LFB145: + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + 553 .loc 1 447 1 is_stmt 1 view -0 + 554 .cfi_startproc + 555 @ args = 0, pretend = 0, frame = 0 + 556 @ frame_needed = 0, uses_anonymous_args = 0 + 557 @ link register save eliminated. + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 558 .loc 1 449 3 view .LVU148 + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 559 .loc 1 453 1 is_stmt 0 view .LVU149 + 560 0000 7047 bx lr + 561 .cfi_endproc + 562 .LFE145: + 564 .section .text.HAL_FLASH_IRQHandler,"ax",%progbits + 565 .align 1 + 566 .global HAL_FLASH_IRQHandler + 567 .syntax unified + ARM GAS /tmp/ccfS03PQ.s page 41 + + + 568 .thumb + 569 .thumb_func + 571 HAL_FLASH_IRQHandler: + 572 .LFB143: + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** uint32_t temp = 0; + 573 .loc 1 294 1 is_stmt 1 view -0 + 574 .cfi_startproc + 575 @ args = 0, pretend = 0, frame = 0 + 576 @ frame_needed = 0, uses_anonymous_args = 0 + 577 0000 38B5 push {r3, r4, r5, lr} + 578 .LCFI3: + 579 .cfi_def_cfa_offset 16 + 580 .cfi_offset 3, -16 + 581 .cfi_offset 4, -12 + 582 .cfi_offset 5, -8 + 583 .cfi_offset 14, -4 + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 584 .loc 1 295 3 view .LVU151 + 585 .LVL21: + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 586 .loc 1 298 3 view .LVU152 + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 587 .loc 1 298 8 is_stmt 0 view .LVU153 + 588 0002 3E4B ldr r3, .L48 + 589 0004 1A69 ldr r2, [r3, #16] + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 590 .loc 1 298 13 view .LVU154 + 591 0006 22F00102 bic r2, r2, #1 + 592 000a 1A61 str r2, [r3, #16] + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR &= SECTOR_MASK; + 593 .loc 1 301 3 is_stmt 1 view .LVU155 + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR &= SECTOR_MASK; + 594 .loc 1 301 8 is_stmt 0 view .LVU156 + 595 000c 1A69 ldr r2, [r3, #16] + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->CR &= SECTOR_MASK; + 596 .loc 1 301 13 view .LVU157 + 597 000e 22F00202 bic r2, r2, #2 + 598 0012 1A61 str r2, [r3, #16] + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 599 .loc 1 302 3 is_stmt 1 view .LVU158 + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 600 .loc 1 302 8 is_stmt 0 view .LVU159 + 601 0014 1A69 ldr r2, [r3, #16] + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 602 .loc 1 302 13 view .LVU160 + 603 0016 22F0F802 bic r2, r2, #248 + 604 001a 1A61 str r2, [r3, #16] + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 605 .loc 1 305 3 is_stmt 1 view .LVU161 + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 606 .loc 1 305 8 is_stmt 0 view .LVU162 + 607 001c 1969 ldr r1, [r3, #16] + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 608 .loc 1 305 13 view .LVU163 + 609 001e 384A ldr r2, .L48+4 + 610 0020 0A40 ands r2, r2, r1 + 611 0022 1A61 str r2, [r3, #16] + ARM GAS /tmp/ccfS03PQ.s page 42 + + + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 612 .loc 1 308 3 is_stmt 1 view .LVU164 + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 613 .loc 1 308 6 is_stmt 0 view .LVU165 + 614 0024 DC68 ldr r4, [r3, #12] + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 615 .loc 1 308 5 view .LVU166 + 616 0026 14F00104 ands r4, r4, #1 + 617 002a 2DD0 beq .L37 + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 618 .loc 1 311 5 is_stmt 1 view .LVU167 + 619 002c 0122 movs r2, #1 + 620 002e DA60 str r2, [r3, #12] + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 621 .loc 1 313 5 view .LVU168 + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 622 .loc 1 313 19 is_stmt 0 view .LVU169 + 623 0030 344B ldr r3, .L48+8 + 624 0032 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 625 0034 DBB2 uxtb r3, r3 + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 626 .loc 1 313 5 view .LVU170 + 627 0036 022B cmp r3, #2 + 628 0038 1FD0 beq .L38 + 629 003a 032B cmp r3, #3 + 630 003c 4FD0 beq .L39 + 631 003e 9342 cmp r3, r2 + 632 0040 55D1 bne .L45 + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 633 .loc 1 318 9 is_stmt 1 view .LVU171 + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 634 .loc 1 318 15 is_stmt 0 view .LVU172 + 635 0042 304B ldr r3, .L48+8 + 636 0044 5A68 ldr r2, [r3, #4] + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 637 .loc 1 318 32 view .LVU173 + 638 0046 013A subs r2, r2, #1 + 639 0048 5A60 str r2, [r3, #4] + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 640 .loc 1 321 9 is_stmt 1 view .LVU174 + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 641 .loc 1 321 18 is_stmt 0 view .LVU175 + 642 004a 5B68 ldr r3, [r3, #4] + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 643 .loc 1 321 11 view .LVU176 + 644 004c 5BB1 cbz r3, .L40 + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Indicate user which sector has been erased */ + 645 .loc 1 323 11 is_stmt 1 view .LVU177 + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Indicate user which sector has been erased */ + 646 .loc 1 323 16 is_stmt 0 view .LVU178 + 647 004e 2D4D ldr r5, .L48+8 + 648 0050 E868 ldr r0, [r5, #12] + 649 .LVL22: + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 650 .loc 1 325 11 is_stmt 1 view .LVU179 + 651 0052 FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 652 .LVL23: + ARM GAS /tmp/ccfS03PQ.s page 43 + + + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH_Erase_Sector(temp, pFlash.VoltageForErase); + 653 .loc 1 328 11 view .LVU180 + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH_Erase_Sector(temp, pFlash.VoltageForErase); + 654 .loc 1 328 26 is_stmt 0 view .LVU181 + 655 0056 EC68 ldr r4, [r5, #12] + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH_Erase_Sector(temp, pFlash.VoltageForErase); + 656 .loc 1 328 18 view .LVU182 + 657 0058 0134 adds r4, r4, #1 + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH_Erase_Sector(temp, pFlash.VoltageForErase); + 658 .loc 1 328 16 view .LVU183 + 659 005a EC60 str r4, [r5, #12] + 660 .LVL24: + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 661 .loc 1 329 11 is_stmt 1 view .LVU184 + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 662 .loc 1 329 42 is_stmt 0 view .LVU185 + 663 005c 297A ldrb r1, [r5, #8] @ zero_extendqisi2 + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 664 .loc 1 329 11 view .LVU186 + 665 005e 2046 mov r0, r4 + 666 0060 FFF7FEFF bl FLASH_Erase_Sector + 667 .LVL25: + 668 0064 10E0 b .L37 + 669 .LVL26: + 670 .L40: + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 671 .loc 1 335 11 is_stmt 1 view .LVU187 + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 672 .loc 1 335 25 is_stmt 0 view .LVU188 + 673 0066 274D ldr r5, .L48+8 + 674 0068 4FF0FF34 mov r4, #-1 + 675 006c EC60 str r4, [r5, #12] + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Sector Erase procedure is completed */ + 676 .loc 1 337 11 is_stmt 1 view .LVU189 + 677 006e 2046 mov r0, r4 + 678 0070 FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 679 .LVL27: + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 680 .loc 1 339 11 view .LVU190 + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 681 .loc 1 339 35 is_stmt 0 view .LVU191 + 682 0074 0023 movs r3, #0 + 683 0076 2B70 strb r3, [r5] + 684 0078 06E0 b .L37 + 685 .LVL28: + 686 .L38: + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* MAss Erase procedure is completed */ + 687 .loc 1 348 9 is_stmt 1 view .LVU192 + 688 007a 0020 movs r0, #0 + 689 007c FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 690 .LVL29: + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 691 .loc 1 350 9 view .LVU193 + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 692 .loc 1 350 33 is_stmt 0 view .LVU194 + 693 0080 0020 movs r0, #0 + 694 0082 204B ldr r3, .L48+8 + ARM GAS /tmp/ccfS03PQ.s page 44 + + + 695 0084 1870 strb r0, [r3] + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 696 .loc 1 351 9 is_stmt 1 view .LVU195 + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 697 .loc 1 295 12 is_stmt 0 view .LVU196 + 698 0086 0446 mov r4, r0 + 699 .LVL30: + 700 .L37: + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 701 .loc 1 369 3 is_stmt 1 view .LVU197 + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 702 .loc 1 369 6 is_stmt 0 view .LVU198 + 703 0088 1C4B ldr r3, .L48 + 704 008a DB68 ldr r3, [r3, #12] + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 705 .loc 1 369 5 view .LVU199 + 706 008c 13F0F20F tst r3, #242 + 707 0090 15D0 beq .L41 + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 708 .loc 1 371 5 is_stmt 1 view .LVU200 + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 709 .loc 1 371 19 is_stmt 0 view .LVU201 + 710 0092 1C4B ldr r3, .L48+8 + 711 0094 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 712 0096 DBB2 uxtb r3, r3 + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 713 .loc 1 371 5 view .LVU202 + 714 0098 022B cmp r3, #2 + 715 009a 2DD0 beq .L46 + 716 009c 032B cmp r3, #3 + 717 009e 28D0 beq .L43 + 718 00a0 012B cmp r3, #1 + 719 00a2 04D1 bne .L42 + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.Sector = 0xFFFFFFFFU; + 720 .loc 1 376 9 is_stmt 1 view .LVU203 + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** pFlash.Sector = 0xFFFFFFFFU; + 721 .loc 1 376 14 is_stmt 0 view .LVU204 + 722 00a4 174B ldr r3, .L48+8 + 723 00a6 DC68 ldr r4, [r3, #12] + 724 .LVL31: + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 725 .loc 1 377 9 is_stmt 1 view .LVU205 + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 726 .loc 1 377 23 is_stmt 0 view .LVU206 + 727 00a8 4FF0FF32 mov r2, #-1 + 728 00ac DA60 str r2, [r3, #12] + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 729 .loc 1 378 9 is_stmt 1 view .LVU207 + 730 .LVL32: + 731 .L42: + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 732 .loc 1 396 5 view .LVU208 + 733 00ae FFF7FEFF bl FLASH_SetErrorCode + 734 .LVL33: + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 735 .loc 1 399 5 view .LVU209 + 736 00b2 2046 mov r0, r4 + ARM GAS /tmp/ccfS03PQ.s page 45 + + + 737 00b4 FFF7FEFF bl HAL_FLASH_OperationErrorCallback + 738 .LVL34: + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 739 .loc 1 402 5 view .LVU210 + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 740 .loc 1 402 29 is_stmt 0 view .LVU211 + 741 00b8 124B ldr r3, .L48+8 + 742 00ba 0022 movs r2, #0 + 743 00bc 1A70 strb r2, [r3] + 744 .L41: + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 745 .loc 1 405 3 is_stmt 1 view .LVU212 + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 746 .loc 1 405 12 is_stmt 0 view .LVU213 + 747 00be 114B ldr r3, .L48+8 + 748 00c0 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 749 .loc 1 405 5 view .LVU214 + 750 00c2 5BB9 cbnz r3, .L36 + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 751 .loc 1 408 5 is_stmt 1 view .LVU215 + 752 00c4 0D4B ldr r3, .L48 + 753 00c6 1A69 ldr r2, [r3, #16] + 754 00c8 22F08072 bic r2, r2, #16777216 + 755 00cc 1A61 str r2, [r3, #16] + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 756 .loc 1 411 5 view .LVU216 + 757 00ce 1A69 ldr r2, [r3, #16] + 758 00d0 22F00072 bic r2, r2, #33554432 + 759 00d4 1A61 str r2, [r3, #16] + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 760 .loc 1 414 5 view .LVU217 + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 761 .loc 1 414 5 view .LVU218 + 762 00d6 0B4B ldr r3, .L48+8 + 763 00d8 0022 movs r2, #0 + 764 00da 1A75 strb r2, [r3, #20] + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 765 .loc 1 414 5 discriminator 1 view .LVU219 + 766 .L36: + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 767 .loc 1 417 1 is_stmt 0 view .LVU220 + 768 00dc 38BD pop {r3, r4, r5, pc} + 769 .LVL35: + 770 .L39: + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Programming procedure is completed */ + 771 .loc 1 358 9 is_stmt 1 view .LVU221 + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Programming procedure is completed */ + 772 .loc 1 358 48 is_stmt 0 view .LVU222 + 773 00de 094C ldr r4, .L48+8 + 774 00e0 2069 ldr r0, [r4, #16] + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Programming procedure is completed */ + 775 .loc 1 358 9 view .LVU223 + 776 00e2 FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 777 .LVL36: + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 778 .loc 1 360 9 is_stmt 1 view .LVU224 + ARM GAS /tmp/ccfS03PQ.s page 46 + + + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 779 .loc 1 360 33 is_stmt 0 view .LVU225 + 780 00e6 0020 movs r0, #0 + 781 00e8 2070 strb r0, [r4] + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 782 .loc 1 361 9 is_stmt 1 view .LVU226 + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 783 .loc 1 295 12 is_stmt 0 view .LVU227 + 784 00ea 0446 mov r4, r0 + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 785 .loc 1 361 9 view .LVU228 + 786 00ec CCE7 b .L37 + 787 .L45: + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 788 .loc 1 313 5 view .LVU229 + 789 00ee 0024 movs r4, #0 + 790 00f0 CAE7 b .L37 + 791 .LVL37: + 792 .L43: + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 793 .loc 1 389 9 is_stmt 1 view .LVU230 + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 794 .loc 1 389 14 is_stmt 0 view .LVU231 + 795 00f2 044B ldr r3, .L48+8 + 796 00f4 1C69 ldr r4, [r3, #16] + 797 .LVL38: + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 798 .loc 1 390 9 is_stmt 1 view .LVU232 + 799 00f6 DAE7 b .L42 + 800 .L46: + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 801 .loc 1 383 14 is_stmt 0 view .LVU233 + 802 00f8 0024 movs r4, #0 + 803 .LVL39: + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 804 .loc 1 383 14 view .LVU234 + 805 00fa D8E7 b .L42 + 806 .L49: + 807 .align 2 + 808 .L48: + 809 00fc 003C0240 .word 1073888256 + 810 0100 FB7FFFFF .word -32773 + 811 0104 00000000 .word pFlash + 812 .cfi_endproc + 813 .LFE143: + 815 .section .text.HAL_FLASH_Unlock,"ax",%progbits + 816 .align 1 + 817 .global HAL_FLASH_Unlock + 818 .syntax unified + 819 .thumb + 820 .thumb_func + 822 HAL_FLASH_Unlock: + 823 .LFB146: + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_OK; + 824 .loc 1 479 1 is_stmt 1 view -0 + 825 .cfi_startproc + 826 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccfS03PQ.s page 47 + + + 827 @ frame_needed = 0, uses_anonymous_args = 0 + 828 @ link register save eliminated. + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 829 .loc 1 480 3 view .LVU236 + 830 .LVL40: + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 831 .loc 1 482 3 view .LVU237 + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 832 .loc 1 482 6 is_stmt 0 view .LVU238 + 833 0000 094B ldr r3, .L55 + 834 0002 1B69 ldr r3, [r3, #16] + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 835 .loc 1 482 5 view .LVU239 + 836 0004 002B cmp r3, #0 + 837 0006 01DB blt .L54 + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 838 .loc 1 480 21 view .LVU240 + 839 0008 0020 movs r0, #0 + 840 000a 7047 bx lr + 841 .L54: + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** WRITE_REG(FLASH->KEYR, FLASH_KEY2); + 842 .loc 1 485 5 is_stmt 1 view .LVU241 + 843 000c 064B ldr r3, .L55 + 844 000e 074A ldr r2, .L55+4 + 845 0010 5A60 str r2, [r3, #4] + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 846 .loc 1 486 5 view .LVU242 + 847 0012 02F18832 add r2, r2, #-2004318072 + 848 0016 5A60 str r2, [r3, #4] + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 849 .loc 1 489 5 view .LVU243 + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 850 .loc 1 489 8 is_stmt 0 view .LVU244 + 851 0018 1B69 ldr r3, [r3, #16] + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 852 .loc 1 489 7 view .LVU245 + 853 001a 002B cmp r3, #0 + 854 001c 01DB blt .L53 + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 855 .loc 1 480 21 view .LVU246 + 856 001e 0020 movs r0, #0 + 857 0020 7047 bx lr + 858 .L53: + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 859 .loc 1 491 14 view .LVU247 + 860 0022 0120 movs r0, #1 + 861 .LVL41: + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 862 .loc 1 495 3 is_stmt 1 view .LVU248 + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 863 .loc 1 496 1 is_stmt 0 view .LVU249 + 864 0024 7047 bx lr + 865 .L56: + 866 0026 00BF .align 2 + 867 .L55: + 868 0028 003C0240 .word 1073888256 + 869 002c 23016745 .word 1164378403 + ARM GAS /tmp/ccfS03PQ.s page 48 + + + 870 .cfi_endproc + 871 .LFE146: + 873 .section .text.HAL_FLASH_Lock,"ax",%progbits + 874 .align 1 + 875 .global HAL_FLASH_Lock + 876 .syntax unified + 877 .thumb + 878 .thumb_func + 880 HAL_FLASH_Lock: + 881 .LFB147: + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Set the LOCK Bit to lock the FLASH Registers access */ + 882 .loc 1 503 1 is_stmt 1 view -0 + 883 .cfi_startproc + 884 @ args = 0, pretend = 0, frame = 0 + 885 @ frame_needed = 0, uses_anonymous_args = 0 + 886 @ link register save eliminated. + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 887 .loc 1 505 3 view .LVU251 + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 888 .loc 1 505 8 is_stmt 0 view .LVU252 + 889 0000 034A ldr r2, .L58 + 890 0002 1369 ldr r3, [r2, #16] + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 891 .loc 1 505 13 view .LVU253 + 892 0004 43F00043 orr r3, r3, #-2147483648 + 893 0008 1361 str r3, [r2, #16] + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 894 .loc 1 507 3 is_stmt 1 view .LVU254 + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 895 .loc 1 508 1 is_stmt 0 view .LVU255 + 896 000a 0020 movs r0, #0 + 897 000c 7047 bx lr + 898 .L59: + 899 000e 00BF .align 2 + 900 .L58: + 901 0010 003C0240 .word 1073888256 + 902 .cfi_endproc + 903 .LFE147: + 905 .section .text.HAL_FLASH_OB_Unlock,"ax",%progbits + 906 .align 1 + 907 .global HAL_FLASH_OB_Unlock + 908 .syntax unified + 909 .thumb + 910 .thumb_func + 912 HAL_FLASH_OB_Unlock: + 913 .LFB148: + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) + 914 .loc 1 515 1 is_stmt 1 view -0 + 915 .cfi_startproc + 916 @ args = 0, pretend = 0, frame = 0 + 917 @ frame_needed = 0, uses_anonymous_args = 0 + 918 @ link register save eliminated. + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 919 .loc 1 516 3 view .LVU257 + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 920 .loc 1 516 12 is_stmt 0 view .LVU258 + 921 0000 074B ldr r3, .L63 + ARM GAS /tmp/ccfS03PQ.s page 49 + + + 922 0002 5B69 ldr r3, [r3, #20] + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 923 .loc 1 516 5 view .LVU259 + 924 0004 13F0010F tst r3, #1 + 925 0008 07D0 beq .L62 + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->OPTKEYR = FLASH_OPT_KEY2; + 926 .loc 1 519 5 is_stmt 1 view .LVU260 + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** FLASH->OPTKEYR = FLASH_OPT_KEY2; + 927 .loc 1 519 20 is_stmt 0 view .LVU261 + 928 000a 054B ldr r3, .L63 + 929 000c 054A ldr r2, .L63+4 + 930 000e 9A60 str r2, [r3, #8] + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 931 .loc 1 520 5 is_stmt 1 view .LVU262 + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 932 .loc 1 520 20 is_stmt 0 view .LVU263 + 933 0010 02F14432 add r2, r2, #1145324612 + 934 0014 9A60 str r2, [r3, #8] + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 935 .loc 1 527 3 is_stmt 1 view .LVU264 + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 936 .loc 1 527 10 is_stmt 0 view .LVU265 + 937 0016 0020 movs r0, #0 + 938 0018 7047 bx lr + 939 .L62: + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 940 .loc 1 524 12 view .LVU266 + 941 001a 0120 movs r0, #1 + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 942 .loc 1 528 1 view .LVU267 + 943 001c 7047 bx lr + 944 .L64: + 945 001e 00BF .align 2 + 946 .L63: + 947 0020 003C0240 .word 1073888256 + 948 0024 3B2A1908 .word 135866939 + 949 .cfi_endproc + 950 .LFE148: + 952 .section .text.HAL_FLASH_OB_Lock,"ax",%progbits + 953 .align 1 + 954 .global HAL_FLASH_OB_Lock + 955 .syntax unified + 956 .thumb + 957 .thumb_func + 959 HAL_FLASH_OB_Lock: + 960 .LFB149: + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + 961 .loc 1 535 1 is_stmt 1 view -0 + 962 .cfi_startproc + 963 @ args = 0, pretend = 0, frame = 0 + 964 @ frame_needed = 0, uses_anonymous_args = 0 + 965 @ link register save eliminated. + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 966 .loc 1 537 3 view .LVU269 + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 967 .loc 1 537 8 is_stmt 0 view .LVU270 + 968 0000 034A ldr r2, .L66 + ARM GAS /tmp/ccfS03PQ.s page 50 + + + 969 0002 5369 ldr r3, [r2, #20] + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 970 .loc 1 537 16 view .LVU271 + 971 0004 43F00103 orr r3, r3, #1 + 972 0008 5361 str r3, [r2, #20] + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 973 .loc 1 539 3 is_stmt 1 view .LVU272 + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 974 .loc 1 540 1 is_stmt 0 view .LVU273 + 975 000a 0020 movs r0, #0 + 976 000c 7047 bx lr + 977 .L67: + 978 000e 00BF .align 2 + 979 .L66: + 980 0010 003C0240 .word 1073888256 + 981 .cfi_endproc + 982 .LFE149: + 984 .section .text.HAL_FLASH_GetError,"ax",%progbits + 985 .align 1 + 986 .global HAL_FLASH_GetError + 987 .syntax unified + 988 .thumb + 989 .thumb_func + 991 HAL_FLASH_GetError: + 992 .LFB151: + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** return pFlash.ErrorCode; + 993 .loc 1 583 1 is_stmt 1 view -0 + 994 .cfi_startproc + 995 @ args = 0, pretend = 0, frame = 0 + 996 @ frame_needed = 0, uses_anonymous_args = 0 + 997 @ link register save eliminated. + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 998 .loc 1 584 4 view .LVU275 + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 999 .loc 1 584 17 is_stmt 0 view .LVU276 + 1000 0000 014B ldr r3, .L69 + 1001 0002 9869 ldr r0, [r3, #24] + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1002 .loc 1 585 1 view .LVU277 + 1003 0004 7047 bx lr + 1004 .L70: + 1005 0006 00BF .align 2 + 1006 .L69: + 1007 0008 00000000 .word pFlash + 1008 .cfi_endproc + 1009 .LFE151: + 1011 .section .text.FLASH_WaitForLastOperation,"ax",%progbits + 1012 .align 1 + 1013 .global FLASH_WaitForLastOperation + 1014 .syntax unified + 1015 .thumb + 1016 .thumb_func + 1018 FLASH_WaitForLastOperation: + 1019 .LVL42: + 1020 .LFB152: + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** uint32_t tickstart = 0; + 1021 .loc 1 597 1 is_stmt 1 view -0 + ARM GAS /tmp/ccfS03PQ.s page 51 + + + 1022 .cfi_startproc + 1023 @ args = 0, pretend = 0, frame = 0 + 1024 @ frame_needed = 0, uses_anonymous_args = 0 + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** uint32_t tickstart = 0; + 1025 .loc 1 597 1 is_stmt 0 view .LVU279 + 1026 0000 38B5 push {r3, r4, r5, lr} + 1027 .LCFI4: + 1028 .cfi_def_cfa_offset 16 + 1029 .cfi_offset 3, -16 + 1030 .cfi_offset 4, -12 + 1031 .cfi_offset 5, -8 + 1032 .cfi_offset 14, -4 + 1033 0002 0446 mov r4, r0 + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1034 .loc 1 598 3 is_stmt 1 view .LVU280 + 1035 .LVL43: + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1036 .loc 1 601 3 view .LVU281 + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1037 .loc 1 601 20 is_stmt 0 view .LVU282 + 1038 0004 154B ldr r3, .L82 + 1039 0006 0022 movs r2, #0 + 1040 0008 9A61 str r2, [r3, #24] + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1041 .loc 1 607 3 is_stmt 1 view .LVU283 + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1042 .loc 1 607 15 is_stmt 0 view .LVU284 + 1043 000a FFF7FEFF bl HAL_GetTick + 1044 .LVL44: + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1045 .loc 1 607 15 view .LVU285 + 1046 000e 0546 mov r5, r0 + 1047 .LVL45: + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1048 .loc 1 609 3 is_stmt 1 view .LVU286 + 1049 .L73: + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1050 .loc 1 609 46 view .LVU287 + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1051 .loc 1 609 9 is_stmt 0 view .LVU288 + 1052 0010 134B ldr r3, .L82+4 + 1053 0012 DB68 ldr r3, [r3, #12] + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1054 .loc 1 609 46 view .LVU289 + 1055 0014 13F4803F tst r3, #65536 + 1056 0018 0AD0 beq .L80 + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1057 .loc 1 611 5 is_stmt 1 view .LVU290 + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1058 .loc 1 611 7 is_stmt 0 view .LVU291 + 1059 001a B4F1FF3F cmp r4, #-1 + 1060 001e F7D0 beq .L73 + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1061 .loc 1 613 7 is_stmt 1 view .LVU292 + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1062 .loc 1 613 9 is_stmt 0 view .LVU293 + 1063 0020 24B1 cbz r4, .L74 + ARM GAS /tmp/ccfS03PQ.s page 52 + + + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1064 .loc 1 613 28 discriminator 1 view .LVU294 + 1065 0022 FFF7FEFF bl HAL_GetTick + 1066 .LVL46: + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1067 .loc 1 613 42 discriminator 1 view .LVU295 + 1068 0026 401B subs r0, r0, r5 + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1069 .loc 1 613 24 discriminator 1 view .LVU296 + 1070 0028 A042 cmp r0, r4 + 1071 002a F1D9 bls .L73 + 1072 .L74: + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 1073 .loc 1 615 9 is_stmt 1 view .LVU297 + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 1074 .loc 1 615 16 is_stmt 0 view .LVU298 + 1075 002c 0320 movs r0, #3 + 1076 002e 0DE0 b .L75 + 1077 .L80: + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1078 .loc 1 620 3 is_stmt 1 view .LVU299 + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1079 .loc 1 620 6 is_stmt 0 view .LVU300 + 1080 0030 0B4B ldr r3, .L82+4 + 1081 0032 DB68 ldr r3, [r3, #12] + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1082 .loc 1 620 5 view .LVU301 + 1083 0034 13F0F20F tst r3, #242 + 1084 0038 09D1 bne .L81 + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1085 .loc 1 628 3 is_stmt 1 view .LVU302 + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1086 .loc 1 628 7 is_stmt 0 view .LVU303 + 1087 003a 094B ldr r3, .L82+4 + 1088 003c DB68 ldr r3, [r3, #12] + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1089 .loc 1 628 6 view .LVU304 + 1090 003e 13F0010F tst r3, #1 + 1091 0042 08D0 beq .L78 + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 1092 .loc 1 631 5 is_stmt 1 view .LVU305 + 1093 0044 064B ldr r3, .L82+4 + 1094 0046 0122 movs r2, #1 + 1095 0048 DA60 str r2, [r3, #12] + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1096 .loc 1 635 10 is_stmt 0 view .LVU306 + 1097 004a 0020 movs r0, #0 + 1098 .L75: + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1099 .loc 1 637 1 view .LVU307 + 1100 004c 38BD pop {r3, r4, r5, pc} + 1101 .LVL47: + 1102 .L81: + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** return HAL_ERROR; + 1103 .loc 1 623 5 is_stmt 1 view .LVU308 + 1104 004e FFF7FEFF bl FLASH_SetErrorCode + 1105 .LVL48: + ARM GAS /tmp/ccfS03PQ.s page 53 + + + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 1106 .loc 1 624 5 view .LVU309 + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 1107 .loc 1 624 12 is_stmt 0 view .LVU310 + 1108 0052 0120 movs r0, #1 + 1109 0054 FAE7 b .L75 + 1110 .L78: + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1111 .loc 1 635 10 view .LVU311 + 1112 0056 0020 movs r0, #0 + 1113 0058 F8E7 b .L75 + 1114 .L83: + 1115 005a 00BF .align 2 + 1116 .L82: + 1117 005c 00000000 .word pFlash + 1118 0060 003C0240 .word 1073888256 + 1119 .cfi_endproc + 1120 .LFE152: + 1122 .section .text.HAL_FLASH_Program,"ax",%progbits + 1123 .align 1 + 1124 .global HAL_FLASH_Program + 1125 .syntax unified + 1126 .thumb + 1127 .thumb_func + 1129 HAL_FLASH_Program: + 1130 .LVL49: + 1131 .LFB141: + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_ERROR; + 1132 .loc 1 163 1 is_stmt 1 view -0 + 1133 .cfi_startproc + 1134 @ args = 0, pretend = 0, frame = 0 + 1135 @ frame_needed = 0, uses_anonymous_args = 0 + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_ERROR; + 1136 .loc 1 163 1 is_stmt 0 view .LVU313 + 1137 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 1138 .LCFI5: + 1139 .cfi_def_cfa_offset 24 + 1140 .cfi_offset 3, -24 + 1141 .cfi_offset 4, -20 + 1142 .cfi_offset 5, -16 + 1143 .cfi_offset 6, -12 + 1144 .cfi_offset 7, -8 + 1145 .cfi_offset 14, -4 + 1146 0002 1646 mov r6, r2 + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1147 .loc 1 164 3 is_stmt 1 view .LVU314 + 1148 .LVL50: + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1149 .loc 1 167 3 view .LVU315 + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1150 .loc 1 167 3 view .LVU316 + 1151 0004 1B4A ldr r2, .L96 + 1152 .LVL51: + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1153 .loc 1 167 3 is_stmt 0 view .LVU317 + 1154 0006 127D ldrb r2, [r2, #20] @ zero_extendqisi2 + 1155 0008 012A cmp r2, #1 + ARM GAS /tmp/ccfS03PQ.s page 54 + + + 1156 000a 31D0 beq .L93 + 1157 000c 0446 mov r4, r0 + 1158 000e 0D46 mov r5, r1 + 1159 0010 1F46 mov r7, r3 + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1160 .loc 1 167 3 is_stmt 1 discriminator 2 view .LVU318 + 1161 0012 184B ldr r3, .L96 + 1162 0014 0122 movs r2, #1 + 1163 0016 1A75 strb r2, [r3, #20] + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1164 .loc 1 167 3 discriminator 2 view .LVU319 + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1165 .loc 1 170 3 view .LVU320 + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1166 .loc 1 173 3 view .LVU321 + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1167 .loc 1 173 12 is_stmt 0 view .LVU322 + 1168 0018 4CF25030 movw r0, #50000 + 1169 .LVL52: + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1170 .loc 1 173 12 view .LVU323 + 1171 001c FFF7FEFF bl FLASH_WaitForLastOperation + 1172 .LVL53: + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1173 .loc 1 175 3 is_stmt 1 view .LVU324 + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1174 .loc 1 175 5 is_stmt 0 view .LVU325 + 1175 0020 90B9 cbnz r0, .L86 + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** { + 1176 .loc 1 177 5 is_stmt 1 view .LVU326 + 1177 0022 032C cmp r4, #3 + 1178 0024 07D8 bhi .L87 + 1179 0026 DFE804F0 tbb [pc, r4] + 1180 .L89: + 1181 002a 02 .byte (.L92-.L89)/2 + 1182 002b 13 .byte (.L91-.L89)/2 + 1183 002c 18 .byte (.L90-.L89)/2 + 1184 002d 1D .byte (.L88-.L89)/2 + 1185 .p2align 1 + 1186 .L92: + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 1187 .loc 1 182 9 view .LVU327 + 1188 002e F1B2 uxtb r1, r6 + 1189 0030 2846 mov r0, r5 + 1190 .LVL54: + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 1191 .loc 1 182 9 is_stmt 0 view .LVU328 + 1192 0032 FFF7FEFF bl FLASH_Program_Byte + 1193 .LVL55: + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 1194 .loc 1 183 9 is_stmt 1 view .LVU329 + 1195 .L87: + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1196 .loc 1 210 5 view .LVU330 + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1197 .loc 1 210 14 is_stmt 0 view .LVU331 + 1198 0036 4CF25030 movw r0, #50000 + ARM GAS /tmp/ccfS03PQ.s page 55 + + + 1199 003a FFF7FEFF bl FLASH_WaitForLastOperation + 1200 .LVL56: + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 1201 .loc 1 213 5 is_stmt 1 view .LVU332 + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 1202 .loc 1 213 10 is_stmt 0 view .LVU333 + 1203 003e 0E4A ldr r2, .L96+4 + 1204 0040 1369 ldr r3, [r2, #16] + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 1205 .loc 1 213 15 view .LVU334 + 1206 0042 23F00103 bic r3, r3, #1 + 1207 0046 1361 str r3, [r2, #16] + 1208 .L86: + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1209 .loc 1 217 3 is_stmt 1 view .LVU335 + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1210 .loc 1 217 3 view .LVU336 + 1211 0048 0A4B ldr r3, .L96 + 1212 004a 0022 movs r2, #0 + 1213 004c 1A75 strb r2, [r3, #20] + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1214 .loc 1 217 3 view .LVU337 + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 1215 .loc 1 219 3 view .LVU338 + 1216 .LVL57: + 1217 .L85: + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1218 .loc 1 220 1 is_stmt 0 view .LVU339 + 1219 004e F8BD pop {r3, r4, r5, r6, r7, pc} + 1220 .LVL58: + 1221 .L91: + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 1222 .loc 1 189 9 is_stmt 1 view .LVU340 + 1223 0050 B1B2 uxth r1, r6 + 1224 0052 2846 mov r0, r5 + 1225 .LVL59: + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 1226 .loc 1 189 9 is_stmt 0 view .LVU341 + 1227 0054 FFF7FEFF bl FLASH_Program_HalfWord + 1228 .LVL60: + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 1229 .loc 1 190 9 is_stmt 1 view .LVU342 + 1230 0058 EDE7 b .L87 + 1231 .LVL61: + 1232 .L90: + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 1233 .loc 1 196 9 view .LVU343 + 1234 005a 3146 mov r1, r6 + 1235 005c 2846 mov r0, r5 + 1236 .LVL62: + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 1237 .loc 1 196 9 is_stmt 0 view .LVU344 + 1238 005e FFF7FEFF bl FLASH_Program_Word + 1239 .LVL63: + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 1240 .loc 1 197 9 is_stmt 1 view .LVU345 + 1241 0062 E8E7 b .L87 + ARM GAS /tmp/ccfS03PQ.s page 56 + + + 1242 .LVL64: + 1243 .L88: + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 1244 .loc 1 203 9 view .LVU346 + 1245 0064 3246 mov r2, r6 + 1246 0066 3B46 mov r3, r7 + 1247 0068 2846 mov r0, r5 + 1248 .LVL65: + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** break; + 1249 .loc 1 203 9 is_stmt 0 view .LVU347 + 1250 006a FFF7FEFF bl FLASH_Program_DoubleWord + 1251 .LVL66: + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 1252 .loc 1 204 9 is_stmt 1 view .LVU348 + 1253 006e E2E7 b .L87 + 1254 .LVL67: + 1255 .L93: + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1256 .loc 1 167 3 is_stmt 0 discriminator 1 view .LVU349 + 1257 0070 0220 movs r0, #2 + 1258 .LVL68: + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1259 .loc 1 167 3 discriminator 1 view .LVU350 + 1260 0072 ECE7 b .L85 + 1261 .L97: + 1262 .align 2 + 1263 .L96: + 1264 0074 00000000 .word pFlash + 1265 0078 003C0240 .word 1073888256 + 1266 .cfi_endproc + 1267 .LFE141: + 1269 .section .text.HAL_FLASH_OB_Launch,"ax",%progbits + 1270 .align 1 + 1271 .global HAL_FLASH_OB_Launch + 1272 .syntax unified + 1273 .thumb + 1274 .thumb_func + 1276 HAL_FLASH_OB_Launch: + 1277 .LFB150: + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** /* Set the OPTSTRT bit in OPTCR register */ + 1278 .loc 1 547 1 is_stmt 1 view -0 + 1279 .cfi_startproc + 1280 @ args = 0, pretend = 0, frame = 0 + 1281 @ frame_needed = 0, uses_anonymous_args = 0 + 1282 0000 08B5 push {r3, lr} + 1283 .LCFI6: + 1284 .cfi_def_cfa_offset 8 + 1285 .cfi_offset 3, -8 + 1286 .cfi_offset 14, -4 + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1287 .loc 1 549 3 view .LVU352 + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1288 .loc 1 549 8 is_stmt 0 view .LVU353 + 1289 0002 054A ldr r2, .L100 + 1290 0004 5369 ldr r3, [r2, #20] + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1291 .loc 1 549 16 view .LVU354 + ARM GAS /tmp/ccfS03PQ.s page 57 + + + 1292 0006 43F00203 orr r3, r3, #2 + 1293 000a 5361 str r3, [r2, #20] + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 1294 .loc 1 552 3 is_stmt 1 view .LVU355 + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** } + 1295 .loc 1 552 10 is_stmt 0 view .LVU356 + 1296 000c 4CF25030 movw r0, #50000 + 1297 0010 FFF7FEFF bl FLASH_WaitForLastOperation + 1298 .LVL69: + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c **** + 1299 .loc 1 553 1 view .LVU357 + 1300 0014 08BD pop {r3, pc} + 1301 .L101: + 1302 0016 00BF .align 2 + 1303 .L100: + 1304 0018 003C0240 .word 1073888256 + 1305 .cfi_endproc + 1306 .LFE150: + 1308 .global pFlash + 1309 .section .bss.pFlash,"aw",%nobits + 1310 .align 2 + 1313 pFlash: + 1314 0000 00000000 .space 28 + 1314 00000000 + 1314 00000000 + 1314 00000000 + 1314 00000000 + 1315 .text + 1316 .Letext0: + 1317 .file 3 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 1318 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 1319 .file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + 1320 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 1321 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h" + 1322 .file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h" + 1323 .file 9 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h" + ARM GAS /tmp/ccfS03PQ.s page 58 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_flash.c + /tmp/ccfS03PQ.s:20 .text.FLASH_Program_DoubleWord:00000000 $t + /tmp/ccfS03PQ.s:25 .text.FLASH_Program_DoubleWord:00000000 FLASH_Program_DoubleWord + /tmp/ccfS03PQ.s:102 .text.FLASH_Program_DoubleWord:00000030 $d + /tmp/ccfS03PQ.s:107 .text.FLASH_Program_Word:00000000 $t + /tmp/ccfS03PQ.s:112 .text.FLASH_Program_Word:00000000 FLASH_Program_Word + /tmp/ccfS03PQ.s:162 .text.FLASH_Program_Word:00000024 $d + /tmp/ccfS03PQ.s:167 .text.FLASH_Program_HalfWord:00000000 $t + /tmp/ccfS03PQ.s:172 .text.FLASH_Program_HalfWord:00000000 FLASH_Program_HalfWord + /tmp/ccfS03PQ.s:222 .text.FLASH_Program_HalfWord:00000024 $d + /tmp/ccfS03PQ.s:227 .text.FLASH_Program_Byte:00000000 $t + /tmp/ccfS03PQ.s:232 .text.FLASH_Program_Byte:00000000 FLASH_Program_Byte + /tmp/ccfS03PQ.s:281 .text.FLASH_Program_Byte:00000020 $d + /tmp/ccfS03PQ.s:286 .text.FLASH_SetErrorCode:00000000 $t + /tmp/ccfS03PQ.s:291 .text.FLASH_SetErrorCode:00000000 FLASH_SetErrorCode + /tmp/ccfS03PQ.s:382 .text.FLASH_SetErrorCode:0000006c $d + /tmp/ccfS03PQ.s:1313 .bss.pFlash:00000000 pFlash + /tmp/ccfS03PQ.s:388 .text.HAL_FLASH_Program_IT:00000000 $t + /tmp/ccfS03PQ.s:394 .text.HAL_FLASH_Program_IT:00000000 HAL_FLASH_Program_IT + /tmp/ccfS03PQ.s:452 .text.HAL_FLASH_Program_IT:0000003a $d + /tmp/ccfS03PQ.s:456 .text.HAL_FLASH_Program_IT:0000003e $t + /tmp/ccfS03PQ.s:517 .text.HAL_FLASH_Program_IT:0000006c $d + /tmp/ccfS03PQ.s:523 .text.HAL_FLASH_EndOfOperationCallback:00000000 $t + /tmp/ccfS03PQ.s:529 .text.HAL_FLASH_EndOfOperationCallback:00000000 HAL_FLASH_EndOfOperationCallback + /tmp/ccfS03PQ.s:544 .text.HAL_FLASH_OperationErrorCallback:00000000 $t + /tmp/ccfS03PQ.s:550 .text.HAL_FLASH_OperationErrorCallback:00000000 HAL_FLASH_OperationErrorCallback + /tmp/ccfS03PQ.s:565 .text.HAL_FLASH_IRQHandler:00000000 $t + /tmp/ccfS03PQ.s:571 .text.HAL_FLASH_IRQHandler:00000000 HAL_FLASH_IRQHandler + /tmp/ccfS03PQ.s:809 .text.HAL_FLASH_IRQHandler:000000fc $d + /tmp/ccfS03PQ.s:816 .text.HAL_FLASH_Unlock:00000000 $t + /tmp/ccfS03PQ.s:822 .text.HAL_FLASH_Unlock:00000000 HAL_FLASH_Unlock + /tmp/ccfS03PQ.s:868 .text.HAL_FLASH_Unlock:00000028 $d + /tmp/ccfS03PQ.s:874 .text.HAL_FLASH_Lock:00000000 $t + /tmp/ccfS03PQ.s:880 .text.HAL_FLASH_Lock:00000000 HAL_FLASH_Lock + /tmp/ccfS03PQ.s:901 .text.HAL_FLASH_Lock:00000010 $d + /tmp/ccfS03PQ.s:906 .text.HAL_FLASH_OB_Unlock:00000000 $t + /tmp/ccfS03PQ.s:912 .text.HAL_FLASH_OB_Unlock:00000000 HAL_FLASH_OB_Unlock + /tmp/ccfS03PQ.s:947 .text.HAL_FLASH_OB_Unlock:00000020 $d + /tmp/ccfS03PQ.s:953 .text.HAL_FLASH_OB_Lock:00000000 $t + /tmp/ccfS03PQ.s:959 .text.HAL_FLASH_OB_Lock:00000000 HAL_FLASH_OB_Lock + /tmp/ccfS03PQ.s:980 .text.HAL_FLASH_OB_Lock:00000010 $d + /tmp/ccfS03PQ.s:985 .text.HAL_FLASH_GetError:00000000 $t + /tmp/ccfS03PQ.s:991 .text.HAL_FLASH_GetError:00000000 HAL_FLASH_GetError + /tmp/ccfS03PQ.s:1007 .text.HAL_FLASH_GetError:00000008 $d + /tmp/ccfS03PQ.s:1012 .text.FLASH_WaitForLastOperation:00000000 $t + /tmp/ccfS03PQ.s:1018 .text.FLASH_WaitForLastOperation:00000000 FLASH_WaitForLastOperation + /tmp/ccfS03PQ.s:1117 .text.FLASH_WaitForLastOperation:0000005c $d + /tmp/ccfS03PQ.s:1123 .text.HAL_FLASH_Program:00000000 $t + /tmp/ccfS03PQ.s:1129 .text.HAL_FLASH_Program:00000000 HAL_FLASH_Program + /tmp/ccfS03PQ.s:1181 .text.HAL_FLASH_Program:0000002a $d + /tmp/ccfS03PQ.s:1185 .text.HAL_FLASH_Program:0000002e $t + /tmp/ccfS03PQ.s:1264 .text.HAL_FLASH_Program:00000074 $d + /tmp/ccfS03PQ.s:1270 .text.HAL_FLASH_OB_Launch:00000000 $t + /tmp/ccfS03PQ.s:1276 .text.HAL_FLASH_OB_Launch:00000000 HAL_FLASH_OB_Launch + /tmp/ccfS03PQ.s:1304 .text.HAL_FLASH_OB_Launch:00000018 $d + /tmp/ccfS03PQ.s:1310 .bss.pFlash:00000000 $d + ARM GAS /tmp/ccfS03PQ.s page 59 + + + +UNDEFINED SYMBOLS +FLASH_Erase_Sector +HAL_GetTick diff --git a/build/stm32f7xx_hal_flash.o b/build/stm32f7xx_hal_flash.o new file mode 100644 index 0000000000000000000000000000000000000000..3f1eb60a995828b9b89c9337f426e7b40b3eedbc GIT binary patch literal 17536 zcmc&*dwd*Ky+1Rvvzug-G|i(;lay}K^xbTdKInr!lBP+Urfou!wm_@NCfPKByxeS{ zD32l)tJO=jD#{0WRQ+&OyjBFkt5iOK__)+t#E%c~BIv~;FIxlwQG37NGr!rLT~fH8 z`_Db?%=i2r=l3}0%$YN@lWQBdHW`MY++wKtDoKI6R!i(<8s@7SRju;w2{vaBR=!pj z&yHjdZglaq;meMg-9Pxt=#33Hx8C@^H+?N*o74}~8nZ5=rDU+;wYpeIq-1czYs$gX zhFKCZwC?13`@MSmY17pUcq+bUl$Hb3(HGuD*iU;pm;?9*l-d+OtN zpMB$>XH{tIflo>8ty5E*9NufE96Wu>483wng8NVd)Ki?bT1H1^epjB z;EchQTe9j(BEKCd#28hbG!XH!mePGs-EA(Kb<$eYdh*DI9go+vTryy+zNCBi!0vBV zZF_!z-d-9omc7)y;DaF@L*6sf&!~_SSE!|U%-2+=`{>mvMJLO| zLlr#CKWQxTJwCnVw*zRuIBB=oTW*GhjZ1Fsraam9f`v0OtSudA zYgiqgwnoe62elor85E@P(R-#vjc3s!X@)EwjyiaN|!FoxR~@Rmo8SBFCie`YSa2E z+++m|re)t^Y=M*DK8RFyM`NclkiGA9@I=Eu&)7$eC!nB$JQ+bQ-)1n3x}~gM5dOv1 zg`Or$jN8~Gi`v1JFl{Jn38L{Yw+9^U`VMr4)bbd6xM?@UNjwUrEq;PQp7MJS)dKK z6}{h4Tuo!fh0`9uY%gY&r!rRF!Za)_WrQch+U&j&Ov>zko^B5XW6|8*0v~)+X-wd9Zv2ib*yqK@ zHq?v?PXO%NTgiM70n98!jhUZkv{_kg57Sr!W18k^K^+<^Ge+6Y^oZQCEi-1a)nAQd zqHe2M#%&Zm?Ge?8!6qBo{t+n{&lp9#x*vkzI1Uvuu3@9&hBG6XB_sF%8Wb&dB)ZRx zHmDw>g}c&JZ%L@$Ww@&4#>-TlWBB0<*9*?i0*#e^#BnKW^97XH)2+b_JSFbO@QMwQ+T7RRaLepHxp*pbmj=^sU3%{J~p)i{;x zK$_<=W&9BOmA}{0TF!~@gZX6~mHOH|wTZk>!U3m8rM^H+_ytZT}R-6we1MPK~<^)6+nwLX; zov82gsxu3w^XYe}_dvqFxGP;UlUEiK=7>(9KJPeA=CD<2So4YykJ-a27t}eq1wkvf zG{C3XEV73ihg?0ZAZ7 zSs4!5T(AM>O3Gef=*JRULzO8dA2qyxamp#?UH|nx( z+JH8NVZ%+p!)L=HJJF)KfIg?qRJ8@|#{CcNzh=6J`G6JV~FAxiVS0~Ugk zF1V_&NxfQcR2MsSA90!R0g2+(?E@F>@)AO+ydXWc*Hg26v|jCanKsE1_!L+oG4xsT;{z&gJj|QE`{2>o6;bW(ZJvy zK)RMRC%h_b;@=!L&WYj;kxRWd#Dvl$6>bC&9HBv1 z_YgMY$Wni?URMj=sCh%(Mq1zc)gA(~@`_3C!eOXA1ZL_LljgP+Vgkp=D<cBFWb zAxV1KK`%6oMmVPwKPWeA)~V+9imRxv^F*3HutPXZReKw82@d4E4&X%7M$erN_Y%PS zohtiS=7k#%O@OP*EjT+q=)ft<1m~w=rO+HQ78l(ZUF5>WQsaOs6m;#mH15B;Fhmx1 z0!x_#iSsh4x$Ry2|A=P@dofGJkfCY3jjak^#WGtQ#>Uv-<#U!^(t4PVOvLYM|JZ^@6beFR8>!m$Et@0d#d;L_Etw?!&M`rBhjj8q-U_Y zc4>G?xVCywG*jDej9xz28-=%|!-P#&bJ9@Y7~9Yajf>UKrx4R(}m zC|l1l>yV8{A=~m-6xkW5r_Lj)%A9n)|~A#?NaL}23i&R4D0@D!gfdtDz)H* z2w>N``JpZ1u151D$WjI4!UW8q(&+O;PAJ*qkQPJ*gwUSP?ozGzX6?WjtwFt>7K~Cj%z;9g^(sY4g z2dv?cf3BvoNyR}`LwC9zD8&mY6BDB&L&Q6NAH6L?4YIyM`^o{u=RBO<%{a1$Fbl#QHEM zJ?6ILvfeIaQdmWZmcK#I>g+|fQJH4@b8J_rM>3E8C$s%1bbJN&RG2cV)2{qq_?!t{ zT_mnHaC~X0!VYt&3_Bb~Bs<}9%MOWl65{2STI_S3+6 zq)=xY6{uRV5J$qWv(RU0U42w8u<9bi&&hB4^)d)Tf3c$EA7HM$_}kab|~XUzqROo<1MtY zy}h+vv9@FT*4BoW#*M0JYkkM&uC~}{Z?tbB7VW%pEV?n;uXQ?`w>7rz=oFQXXuL5N z8;v!L;#Nx&PRrH}U0Wj)BfSG^0=KvGmvzNeJUTpoA$L~N5{pUFyLC}q*~iLwZ);)k-Z^(qLV~rE2B^J6eI82aAiEI;)r`Z9*M=( z#z;J(4R^#N@riM_8&lit8jbZO&GaHKSFd_tbU0ewAMJ}&Z)`l&( zrAshQDcqf-L-EMoXwzt{F%}t*YOUJyp_QCsjU#=n{jFoncyM&2Au=@76G@H-hj?3k zM@M6OeMcjd_(W`EXJlx?nd)+_ zBtzn?=bX@~rdZtG-NUv zRMInYqaJ3@9CIg^(`;8{Fpgf{8X1o#`VyB_GcK#tS-Lqg)UT~DBxdQ_NnZZAT=0|M zSQ9t9ymlJeYt^RhJ3d*gXQrr44GpV9^J|x{))B{|L$y^) z7Nm!d%`zXZ&Z6KBeN}FDj{da^EM53ORiEoSVC;A#mkjqojCDR-y&KJkF0VWe+WTNm zx;{7WfbS#L4d%ZXDZ1Red)t!sw&jB(+FtKFV0|RLEgvSmZ41-r^tjXIZ0q&a2ioh) z`_Rb;(fZut>-`7pkN9q|KFU~V&n?ug&&{}={Q6oD5k9WrR~S_76^&Kfls_l1Ez``( z$oCZ*MaFci*qC9I;D@O5j0!$3rWG&Cr_P-9it!fTOX4|9KLRCq_ysvpXT`#U+4K~S zPnCeCm1Q_g$d>}$hjYC42bC-q9<@^2+ls$vus!?Ogq-a;51hhBvt+UG9wW8AUo}IV zZ0}EN&-Wk6VyQq{`+(|(nC>n}`bIr6ZF=6vDYaf){pp}mqc zdnMXlQj1q#vRHV%MSID@)g)OgH8V+|W+}dKOcu*C^U1aJZ~0z%^2&7NbCW`?pPUJf zJej#e^IMx_vGA+^4MH-~sfhoRK=*pe$MtelXs%2ZnC}m#&^hYAh35L6kNNx-Xt!{l zWrI(9T$A!KfBD@GX^wP0JT4ZRk>}%IU5dOwwF}KFD<7?*LicHUn%WQAE%f&Zkza*+ zKIX%%LNmX7u9lN;AuHqVJ=u8<=<@7cDm`0dy|3}?Xk>TamDr-B?p*Yq++n3Wt;j|t zxy5qr-~l7aJjXUOsgT$`F!QcJ^2*pyxBKfl&ZrRW?@O$LY(5f5zoT!hkHolR>5_edhMj~gGM*8&1p}X zbAtG9L@cED5VtG!d*S;qSJ`Tn`9_Cwt}#UVBi0LU7Hkz{ z9F*@B)cphcgF;^`_-VnL1RoLng&CXvjx`);#HBBcMJ9l4hia4>hOD|&_@Kn zAb7jrzY9Jn_^9Axf=>v(Eckc9py~K85nLd+QgD+XzjkAP^a_4}i1D~W=o+^8}I3y822BF@1cRY9jJ$B4RPxBDkFhe;0|oSLnThL&Cp8=no0*7ycokZxsBD z@b4hP&({RME%<%G9}yAH6T}tBNAM{k;(1Qwr-gn^@Gar{0*+pWU=9)XiiIu{EEoP_ zp=$(}6XAD@V4vWXf=2|uA$Xj)3E!CsVmWoL7eVf6c>VBxK;*uX$omR$F%k2>MsTGd zrncte)~2yjaJOKWU|evY;C{gaf`ktf<1!$g8TrJ{yru6dBIx*za+?S_NjND;P(U{5`0wfmx50U zJ}dZ~;Ol~K2`bC6%TFL_zfiDPP~Z2!pDpx4L46+te>rK~pZTFA+wT(W738<=iZ)2{Qi`3esWH% z5S%MmC0Hw1FW4x^zgA$oHo;wjy9N0zE9KV-9u)k9;1R)_1n(65y5QY{-x1_@u(WqV z@Hc|`eh5CliKX1annVl=P7$0YSRz<1I7e`?V2$7k!3zX82=YT@+Q)LO%=)x-5&NAG z`PdinS&{oMy)I&Zrq@M`XC3*tZ|Z$;$oWc$*ZD={&rzzIh{gj%+~3EDxc}?*5&MY! zq_N%}BqEN(L@u^O#D;Frm_bB5di@6Gkw#pFg2hC{S0)%DBF;)dgrMiGUf&V7&I577 zwT@rs6T+Vqkp|Wgk;g{C%|zt0Rj`c+qn&~}U*xxkG_ae9Jo^L(h{$(HaEu7&aY5Z5 z$p0$R!2Lu7b3pJqu4m|v(?sO2*CpitITJMU{u2@T4)MA`ey{xYG$J^1-DOh!2MZH4EZ$7Evt+G8?7;^oI=Lj4LPj2|<+!jzXGNn!F; zg6DmR(=I7G$6JwfwR5~1nar8zElIi+dFzqR)~`p>naP(VlSrHviEc=ylXz*8jO<-r zpCpx%7NoD#WU}OI6pngW-aBc{zG%eU61ti#G;owb{x*oXs?%y#3Cbm zqnJF*!_jyrXJ~LF>RQC?Q{mpx;o&HLZuPY4#}C#}s&C&Gj>O}!!JdgY%>HjnDHJi~ z^?ibEc)fcImLFZpai$)YA6?S*C}Ww2BLl~K=`Ds%x?itNENi;7r0ETSp6`hC+12B^ z_L6L*z>uHMb4W7$@9I9Q6Y7BT-S97O67zlXzX zuMNax_U?n8*Io$rm*--Dj2dw8O0%~Z zgLVQux48CN()8ZKZ+DFWU3>hiU9Y_i z>@Bz!F^>uyuD#(jdw+&K>bb?WH<)Jc^RSl(A?;P-aP3{2X75_=!6xbF52e}rS4@_J zutR%uJ@yWXJ@=aZGX^&=t^XJ!_o+lz?`*kq4**LS%6NP!Ex!2`cy^#b3iDv$Us8Je zuVz&;--VF7`SOoKG55xFBb*M;c78i>Y1cFns)_Ol^lnEU*dnSH9JH5*gFfB4jH>Ee Zpw!*25zuZGTiq1BI{a|(pvQr$_djgCB9Q<9 literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_hal_flash_ex.d b/build/stm32f7xx_hal_flash_ex.d new file mode 100644 index 0000000..40280ee --- /dev/null +++ b/build/stm32f7xx_hal_flash_ex.d @@ -0,0 +1,68 @@ +build/stm32f7xx_hal_flash_ex.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/build/stm32f7xx_hal_flash_ex.lst b/build/stm32f7xx_hal_flash_ex.lst new file mode 100644 index 0000000..e5cf593 --- /dev/null +++ b/build/stm32f7xx_hal_flash_ex.lst @@ -0,0 +1,3759 @@ +ARM GAS /tmp/cc9TanaG.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_hal_flash_ex.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c" + 19 .section .text.FLASH_MassErase,"ax",%progbits + 20 .align 1 + 21 .syntax unified + 22 .thumb + 23 .thumb_func + 25 FLASH_MassErase: + 26 .LVL0: + 27 .LFB145: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @file stm32f7xx_hal_flash_ex.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Extended FLASH HAL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * functionalities of the FLASH extension peripheral: + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + Extended programming operations functions + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** @verbatim + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** ============================================================================== + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** ##### Flash Extension features ##### + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** ============================================================================== + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** [..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** devices contains the following additional features + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** capability (RWW) + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** (+) Dual bank memory organization + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** (+) Dual boot mode + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** ##### How to use this driver ##### + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** ============================================================================== + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** [..] This driver provides functions to configure and program the FLASH memory + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** of all STM32F7xx devices. It includes + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** (#) FLASH Memory Erase functions: + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_FLASH_Lock() functions + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** (++) Erase function: Erase sector, erase all sectors + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** (++) There are two modes of erase : + ARM GAS /tmp/cc9TanaG.s page 2 + + + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** (+++) Polling Mode using HAL_FLASHEx_Erase() + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to : + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** (++) Set/Reset the write protection + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** (++) Set the Read protection Level + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** (++) Set the BOR level + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** (++) Program the user Option Bytes + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** @endverbatim + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** ****************************************************************************** + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @attention + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * Copyright (c) 2017 STMicroelectronics. + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * All rights reserved. + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This software is licensed under terms that can be found in the LICENSE file in + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * the root directory of this software component. + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** ****************************************************************************** + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Includes ------------------------------------------------------------------*/ + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #include "stm32f7xx_hal.h" + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** @addtogroup STM32F7xx_HAL_Driver + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @{ + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** @defgroup FLASHEx FLASHEx + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief FLASH HAL Extension module driver + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @{ + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #ifdef HAL_FLASH_MODULE_ENABLED + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Private define ------------------------------------------------------------*/ + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** @addtogroup FLASHEx_Private_Constants + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @{ + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #define SECTOR_MASK 0xFFFFFF07U + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #define FLASH_TIMEOUT_VALUE 50000U/* 50 s */ + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @} + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Private macro -------------------------------------------------------------*/ + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Private variables ---------------------------------------------------------*/ + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** @addtogroup FLASHEx_Private_Variables + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @{ + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** extern FLASH_ProcessTypeDef pFlash; + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @} + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + ARM GAS /tmp/cc9TanaG.s page 3 + + + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** @addtogroup FLASHEx_Private_Functions + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @{ + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Option bytes control */ + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector); + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector); + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level); + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level); + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address); + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetUser(void); + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetWRP(void); + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint8_t FLASH_OB_GetRDP(void); + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetBOR(void); + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption); + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR_nDBANK) + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks); + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot) + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #else + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static void FLASH_MassErase(uint8_t VoltageRange); + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #endif /* FLASH_OPTCR_nDBANK */ + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR2_PCROP) + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_PCROP_Config(uint32_t PCROPSector); + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp); + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetPCROP(void); + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetPCROPRDP(void); + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #endif /* FLASH_OPTCR2_PCROP */ + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @} + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Exported functions --------------------------------------------------------*/ + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @{ + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Extended IO operation functions + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** @verbatim + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** =============================================================================== + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** ##### Extended programming operation functions ##### + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** =============================================================================== + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** [..] + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** This subsection provides a set of functions allowing to manage the Extension FLASH + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** programming operations Operations. + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** @endverbatim + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @{ + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + ARM GAS /tmp/cc9TanaG.s page 4 + + + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Perform a mass erase or erase the specified FLASH memory sectors + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * contains the configuration information for the erasing. + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param[out] SectorError pointer to variable that + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * contains the configuration information on faulty sector in case of error + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * (0xFFFFFFFF means that all the sectors have been correctly erased) + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval HAL Status + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t index = 0; + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Process Locked */ + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** __HAL_LOCK(&pFlash); + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Check the parameters */ + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if(status == HAL_OK) + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /*Initialization of SectorError variable*/ + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** *SectorError = 0xFFFFFFFFU; + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /*Mass erase to be done*/ + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR_nDBANK) + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #else + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #endif /* FLASH_OPTCR_nDBANK */ + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* if the erase operation is completed, disable the MER Bit */ + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR &= (~FLASH_MER_BIT); + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** else + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Check the parameters */ + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Erase by sector by sector to be done*/ + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++ + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange); + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + ARM GAS /tmp/cc9TanaG.s page 5 + + + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* If the erase operation is completed, disable the SER Bit and SNB Bits */ + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if(status != HAL_OK) + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* In case of error, stop erase procedure and return the faulty sector*/ + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** *SectorError = index; + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** break; + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Process Unlocked */ + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** return status; + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enable + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * contains the configuration information for the erasing. + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval HAL Status + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Process Locked */ + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** __HAL_LOCK(&pFlash); + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Check the parameters */ + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Enable End of FLASH Operation interrupt */ + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Enable Error source interrupt */ + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Clear pending flags (if any) */ + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\ + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /*Mass erase to be done*/ + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR_nDBANK) + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #else + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #endif /* FLASH_OPTCR_nDBANK */ + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** else + ARM GAS /tmp/cc9TanaG.s page 6 + + + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Erase by sector to be done*/ + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Check the parameters */ + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE; + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pFlash.NbSectorsToErase = pEraseInit->NbSectors; + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pFlash.Sector = pEraseInit->Sector; + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange; + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /*Erase 1st sector and wait for IT*/ + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange); + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** return status; + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Program option bytes + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param pOBInit pointer to an FLASH_OBInitStruct structure that + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * contains the configuration information for the programming. + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval HAL Status + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Process Locked */ + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** __HAL_LOCK(&pFlash); + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Check the parameters */ + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Write protection configuration */ + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_WRPSTATE(pOBInit->WRPState)); + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if(pOBInit->WRPState == OB_WRPSTATE_ENABLE) + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /*Enable of Write protection on the selected Sector*/ + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** status = FLASH_OB_EnableWRP(pOBInit->WRPSector); + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** else + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /*Disable of Write protection on the selected Sector*/ + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** status = FLASH_OB_DisableWRP(pOBInit->WRPSector); + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Read protection configuration */ + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + ARM GAS /tmp/cc9TanaG.s page 7 + + + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* USER configuration */ + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR_nDBANK) + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->USERConfig & OB_IWDG_SW, + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->USERConfig & OB_STOP_NO_RST, + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->USERConfig & OB_STDBY_NO_RST, + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE, + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE, + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK, + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE); + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #else + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->USERConfig & OB_IWDG_SW, + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->USERConfig & OB_STOP_NO_RST, + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->USERConfig & OB_STDBY_NO_RST, + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE, + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE); + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #endif /* FLASH_OPTCR_nDBANK */ + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* BOR Level configuration */ + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel); + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Boot 0 Address configuration */ + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0) + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0); + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Boot 1 Address configuration */ + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1) + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1); + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR2_PCROP) + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* PCROP configuration */ + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP) + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** status = FLASH_OB_PCROP_Config(pOBInit->PCROPSector); + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* PCROP_RDP configuration */ + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_PCROP_RDP) == OPTIONBYTE_PCROP_RDP) + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** status = FLASH_OB_PCROP_RDP_Config(pOBInit->PCROPRdp); + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #endif /* FLASH_OPTCR2_PCROP */ + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Process Unlocked */ + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + ARM GAS /tmp/cc9TanaG.s page 8 + + + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** return status; + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Get the Option byte configuration + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param pOBInit pointer to an FLASH_OBInitStruct structure that + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * contains the configuration information for the programming. + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval None + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1; + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /*Get WRP*/ + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->WRPSector = FLASH_OB_GetWRP(); + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /*Get RDP Level*/ + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->RDPLevel = FLASH_OB_GetRDP(); + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /*Get USER*/ + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->USERConfig = FLASH_OB_GetUser(); + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /*Get BOR Level*/ + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->BORLevel = FLASH_OB_GetBOR(); + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /*Get Boot Address when Boot pin = 0 */ + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0); + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /*Get Boot Address when Boot pin = 1 */ + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1); + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR2_PCROP) + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /*Get PCROP Sectors */ + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->PCROPSector = FLASH_OB_GetPCROP(); + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /*Get PCROP_RDP Value */ + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->PCROPRdp = FLASH_OB_GetPCROPRDP(); + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #endif /* FLASH_OPTCR2_PCROP */ + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @} + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR_nDBANK) + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Full erase of FLASH memory sectors + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param VoltageRange The device voltage range which defines the erase parallelism. + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * the operation will be done by byte (8-bit) + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * the operation will be done by half word (16-bit) + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * the operation will be done by word (32-bit) + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + ARM GAS /tmp/cc9TanaG.s page 9 + + + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * the operation will be done by double word (64-bit) + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param Banks Banks to be erased + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg FLASH_BANK_1: Bank1 to be erased + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg FLASH_BANK_2: Bank2 to be erased + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval HAL Status + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 28 .loc 1 441 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .loc 1 441 1 is_stmt 0 view .LVU1 + 34 0000 0346 mov r3, r0 + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Check the parameters */ + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_VOLTAGERANGE(VoltageRange)); + 35 .loc 1 443 3 is_stmt 1 view .LVU2 + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_FLASH_BANK(Banks)); + 36 .loc 1 444 3 view .LVU3 + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* if the previous operation is completed, proceed to erase all sectors */ + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR &= CR_PSIZE_MASK; + 37 .loc 1 447 3 view .LVU4 + 38 .loc 1 447 8 is_stmt 0 view .LVU5 + 39 0002 1248 ldr r0, .L7 + 40 .LVL1: + 41 .loc 1 447 8 view .LVU6 + 42 0004 0269 ldr r2, [r0, #16] + 43 .loc 1 447 13 view .LVU7 + 44 0006 22F44072 bic r2, r2, #768 + 45 000a 0261 str r2, [r0, #16] + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if(Banks == FLASH_BANK_BOTH) + 46 .loc 1 448 3 is_stmt 1 view .LVU8 + 47 .loc 1 448 5 is_stmt 0 view .LVU9 + 48 000c 0329 cmp r1, #3 + 49 000e 10D0 beq .L5 + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* bank1 & bank2 will be erased*/ + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR |= FLASH_MER_BIT; + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** else if(Banks == FLASH_BANK_2) + 50 .loc 1 453 8 is_stmt 1 view .LVU10 + 51 .loc 1 453 10 is_stmt 0 view .LVU11 + 52 0010 0229 cmp r1, #2 + 53 0012 15D0 beq .L6 + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /*Only bank2 will be erased*/ + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR |= FLASH_CR_MER2; + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** else + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /*Only bank1 will be erased*/ + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR |= FLASH_CR_MER1; + ARM GAS /tmp/cc9TanaG.s page 10 + + + 54 .loc 1 461 5 is_stmt 1 view .LVU12 + 55 .loc 1 461 10 is_stmt 0 view .LVU13 + 56 0014 0D49 ldr r1, .L7 + 57 .LVL2: + 58 .loc 1 461 10 view .LVU14 + 59 0016 0A69 ldr r2, [r1, #16] + 60 .loc 1 461 15 view .LVU15 + 61 0018 42F00402 orr r2, r2, #4 + 62 001c 0A61 str r2, [r1, #16] + 63 .L3: + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8); + 64 .loc 1 463 3 is_stmt 1 view .LVU16 + 65 .loc 1 463 8 is_stmt 0 view .LVU17 + 66 001e 0B4A ldr r2, .L7 + 67 0020 1069 ldr r0, [r2, #16] + 68 .loc 1 463 13 view .LVU18 + 69 0022 40EA0320 orr r0, r0, r3, lsl #8 + 70 0026 40F48030 orr r0, r0, #65536 + 71 002a 1061 str r0, [r2, #16] + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Data synchronous Barrier (DSB) Just after the write operation + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** This will force the CPU to respect the sequence of instruction (no optimization).*/ + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** __DSB(); + 72 .loc 1 466 3 is_stmt 1 view .LVU19 + 73 .LBB6: + 74 .LBI6: + 75 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + ARM GAS /tmp/cc9TanaG.s page 11 + + + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + ARM GAS /tmp/cc9TanaG.s page 12 + + + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cc9TanaG.s page 13 + + + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + ARM GAS /tmp/cc9TanaG.s page 14 + + + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + ARM GAS /tmp/cc9TanaG.s page 15 + + + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/cc9TanaG.s page 16 + + + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + ARM GAS /tmp/cc9TanaG.s page 17 + + + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cc9TanaG.s page 18 + + + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/cc9TanaG.s page 19 + + + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/cc9TanaG.s page 20 + + + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + ARM GAS /tmp/cc9TanaG.s page 21 + + + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/cc9TanaG.s page 22 + + + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cc9TanaG.s page 23 + + + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + ARM GAS /tmp/cc9TanaG.s page 24 + + + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + ARM GAS /tmp/cc9TanaG.s page 25 + + + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 76 .loc 2 877 27 view .LVU20 + 77 .LBB7: + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 78 .loc 2 879 3 view .LVU21 + 79 .syntax unified + 80 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 81 002c BFF34F8F dsb 0xF + ARM GAS /tmp/cc9TanaG.s page 26 + + + 82 @ 0 "" 2 + 83 .thumb + 84 .syntax unified + 85 .LBE7: + 86 .LBE6: + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 87 .loc 1 467 1 is_stmt 0 view .LVU22 + 88 0030 7047 bx lr + 89 .LVL3: + 90 .L5: + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 91 .loc 1 451 5 is_stmt 1 view .LVU23 + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 92 .loc 1 451 10 is_stmt 0 view .LVU24 + 93 0032 0146 mov r1, r0 + 94 .LVL4: + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 95 .loc 1 451 10 view .LVU25 + 96 0034 0069 ldr r0, [r0, #16] + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 97 .loc 1 451 15 view .LVU26 + 98 0036 48F20402 movw r2, #32772 + 99 003a 0243 orrs r2, r2, r0 + 100 003c 0A61 str r2, [r1, #16] + 101 003e EEE7 b .L3 + 102 .LVL5: + 103 .L6: + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 104 .loc 1 456 5 is_stmt 1 view .LVU27 + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 105 .loc 1 456 10 is_stmt 0 view .LVU28 + 106 0040 0249 ldr r1, .L7 + 107 .LVL6: + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 108 .loc 1 456 10 view .LVU29 + 109 0042 0A69 ldr r2, [r1, #16] + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 110 .loc 1 456 15 view .LVU30 + 111 0044 42F40042 orr r2, r2, #32768 + 112 0048 0A61 str r2, [r1, #16] + 113 004a E8E7 b .L3 + 114 .L8: + 115 .align 2 + 116 .L7: + 117 004c 003C0240 .word 1073888256 + 118 .cfi_endproc + 119 .LFE145: + 121 .section .text.FLASH_OB_GetWRP,"ax",%progbits + 122 .align 1 + 123 .syntax unified + 124 .thumb + 125 .thumb_func + 127 FLASH_OB_GetWRP: + 128 .LFB147: + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Erase the specified FLASH memory sector + ARM GAS /tmp/cc9TanaG.s page 27 + + + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param Sector FLASH sector to erase + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * The value of this parameter depend on device used within the same series + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param VoltageRange The device voltage range which defines the erase parallelism. + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * the operation will be done by byte (8-bit) + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * the operation will be done by half word (16-bit) + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * the operation will be done by word (32-bit) + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * the operation will be done by double word (64-bit) + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval None + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t tmp_psize = 0; + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Check the parameters */ + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_FLASH_SECTOR(Sector)); + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_VOLTAGERANGE(VoltageRange)); + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if(VoltageRange == FLASH_VOLTAGE_RANGE_1) + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** tmp_psize = FLASH_PSIZE_BYTE; + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** tmp_psize = FLASH_PSIZE_HALF_WORD; + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** tmp_psize = FLASH_PSIZE_WORD; + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** else + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */ + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if(Sector > FLASH_SECTOR_11) + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** Sector += 4; + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* If the previous operation is completed, proceed to erase the sector */ + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR &= CR_PSIZE_MASK; + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR |= tmp_psize; + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR |= FLASH_CR_STRT; + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Data synchronous Barrier (DSB) Just after the write operation + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** This will force the CPU to respect the sequence of instruction (no optimization).*/ + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** __DSB(); + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + ARM GAS /tmp/cc9TanaG.s page 28 + + + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Return the FLASH Write Protection Option Bytes value. + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval uint32_t FLASH Write Protection Option Bytes value + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetWRP(void) + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 129 .loc 1 534 1 is_stmt 1 view -0 + 130 .cfi_startproc + 131 @ args = 0, pretend = 0, frame = 0 + 132 @ frame_needed = 0, uses_anonymous_args = 0 + 133 @ link register save eliminated. + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Return the FLASH write protection Register value */ + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000)); + 134 .loc 1 536 3 view .LVU32 + 135 .loc 1 536 27 is_stmt 0 view .LVU33 + 136 0000 024B ldr r3, .L10 + 137 0002 5B69 ldr r3, [r3, #20] + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 138 .loc 1 537 1 view .LVU34 + 139 0004 0248 ldr r0, .L10+4 + 140 0006 1840 ands r0, r0, r3 + 141 0008 7047 bx lr + 142 .L11: + 143 000a 00BF .align 2 + 144 .L10: + 145 000c 003C0240 .word 1073888256 + 146 0010 0000FF0F .word 268369920 + 147 .cfi_endproc + 148 .LFE147: + 150 .section .text.FLASH_OB_GetUser,"ax",%progbits + 151 .align 1 + 152 .syntax unified + 153 .thumb + 154 .thumb_func + 156 FLASH_OB_GetUser: + 157 .LFB149: + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param Wwdg Selects the IWDG mode + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_WWDG_SW: Software WWDG selected + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_WWDG_HW: Hardware WWDG selected + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param Iwdg Selects the WWDG mode + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_IWDG_SW: Software IWDG selected + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_IWDG_HW: Hardware IWDG selected + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param Stop Reset event when entering STOP mode. + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_STOP_NO_RST: No reset generated when entering in STOP + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_STOP_RST: Reset generated when entering in STOP + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param Stdby Reset event when entering Standby mode. + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param Iwdgstop Independent watchdog counter freeze in Stop mode. + ARM GAS /tmp/cc9TanaG.s page 29 + + + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param Iwdgstdby Independent watchdog counter freeze in standby mode. + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param NDBank Flash Single Bank mode enabled. + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank) + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mo + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param NDBoot Flash Dual boot mode disable. + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval HAL Status + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot) + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t useroptionmask = 0x00; + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t useroptionvalue = 0x00; + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Check the parameters */ + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_WWDG_SOURCE(Wwdg)); + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_IWDG_SOURCE(Iwdg)); + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_STOP_SOURCE(Stop)); + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_STDBY_SOURCE(Stdby)); + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop)); + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby)); + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_NDBANK(NDBank)); + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_NDBOOT(NDBoot)); + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if(status == HAL_OK) + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \ + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \ + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK); + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank); + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Update User Option Byte */ + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue); + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** return status; + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Return the FLASH User Option Byte value. + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), + ARM GAS /tmp/cc9TanaG.s page 30 + + + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31). + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetUser(void) + 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 158 .loc 1 618 1 is_stmt 1 view -0 + 159 .cfi_startproc + 160 @ args = 0, pretend = 0, frame = 0 + 161 @ frame_needed = 0, uses_anonymous_args = 0 + 162 @ link register save eliminated. + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Return the User Option Byte */ + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U)); + 163 .loc 1 620 3 view .LVU36 + 164 .loc 1 620 27 is_stmt 0 view .LVU37 + 165 0000 024B ldr r3, .L13 + 166 0002 5B69 ldr r3, [r3, #20] + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 167 .loc 1 621 1 view .LVU38 + 168 0004 0248 ldr r0, .L13+4 + 169 0006 1840 ands r0, r0, r3 + 170 0008 7047 bx lr + 171 .L14: + 172 000a 00BF .align 2 + 173 .L13: + 174 000c 003C0240 .word 1073888256 + 175 0010 F00000F0 .word -268435216 + 176 .cfi_endproc + 177 .LFE149: + 179 .section .text.FLASH_OB_BOR_LevelConfig,"ax",%progbits + 180 .align 1 + 181 .syntax unified + 182 .thumb + 183 .thumb_func + 185 FLASH_OB_BOR_LevelConfig: + 186 .LVL7: + 187 .LFB153: + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #else + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Full erase of FLASH memory sectors + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param VoltageRange The device voltage range which defines the erase parallelism. + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * the operation will be done by byte (8-bit) + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * the operation will be done by half word (16-bit) + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * the operation will be done by word (32-bit) + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * the operation will be done by double word (64-bit) + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval HAL Status + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static void FLASH_MassErase(uint8_t VoltageRange) + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Check the parameters */ + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_VOLTAGERANGE(VoltageRange)); + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + ARM GAS /tmp/cc9TanaG.s page 31 + + + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* if the previous operation is completed, proceed to erase all sectors */ + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR &= CR_PSIZE_MASK; + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR |= FLASH_CR_MER; + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8); + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Data synchronous Barrier (DSB) Just after the write operation + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** This will force the CPU to respect the sequence of instruction (no optimization).*/ + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** __DSB(); + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Erase the specified FLASH memory sector + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param Sector FLASH sector to erase + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * The value of this parameter depend on device used within the same series + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param VoltageRange The device voltage range which defines the erase parallelism. + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * the operation will be done by byte (8-bit) + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * the operation will be done by half word (16-bit) + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * the operation will be done by word (32-bit) + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External + 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * the operation will be done by double word (64-bit) + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval None + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t tmp_psize = 0; + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Check the parameters */ + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_FLASH_SECTOR(Sector)); + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_VOLTAGERANGE(VoltageRange)); + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if(VoltageRange == FLASH_VOLTAGE_RANGE_1) + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** tmp_psize = FLASH_PSIZE_BYTE; + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** tmp_psize = FLASH_PSIZE_HALF_WORD; + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** tmp_psize = FLASH_PSIZE_WORD; + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** else + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* If the previous operation is completed, proceed to erase the sector */ + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR &= CR_PSIZE_MASK; + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR |= tmp_psize; + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR &= SECTOR_MASK; + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR |= FLASH_CR_STRT; + ARM GAS /tmp/cc9TanaG.s page 32 + + + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Data synchronous Barrier (DSB) Just after the write operation + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** This will force the CPU to respect the sequence of instruction (no optimization).*/ + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** __DSB(); + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Return the FLASH Write Protection Option Bytes value. + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval uint32_t FLASH Write Protection Option Bytes value + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetWRP(void) + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Return the FLASH write protection Register value */ + 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** return ((uint32_t)(FLASH->OPTCR & 0x00FF0000)); + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param Wwdg Selects the IWDG mode + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_WWDG_SW: Software WWDG selected + 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_WWDG_HW: Hardware WWDG selected + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param Iwdg Selects the WWDG mode + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_IWDG_SW: Software IWDG selected + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_IWDG_HW: Hardware IWDG selected + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param Stop Reset event when entering STOP mode. + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_STOP_NO_RST: No reset generated when entering in STOP + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_STOP_RST: Reset generated when entering in STOP + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param Stdby Reset event when entering Standby mode. + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param Iwdgstop Independent watchdog counter freeze in Stop mode. + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP + 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param Iwdgstdby Independent watchdog counter freeze in standby mode. + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval HAL Status + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t useroptionmask = 0x00; + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t useroptionvalue = 0x00; + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Check the parameters */ + 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_WWDG_SOURCE(Wwdg)); + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_IWDG_SOURCE(Iwdg)); + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_STOP_SOURCE(Stop)); + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_STDBY_SOURCE(Stdby)); + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop)); + ARM GAS /tmp/cc9TanaG.s page 33 + + + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby)); + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if(status == HAL_OK) + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \ + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY); + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby); + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Update User Option Byte */ + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue); + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** return status; + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Return the FLASH User Option Byte value. + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), + 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31). + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetUser(void) + 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Return the User Option Byte */ + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** return ((uint32_t)(FLASH->OPTCR & 0xC00000F0U)); + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #endif /* FLASH_OPTCR_nDBANK */ + 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Enable the write protection of the desired bank1 or bank2 sectors + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @note When the memory read protection level is selected (RDP level = 1), + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * it is not possible to program or erase the flash sector i if CortexM7 + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param WRPSector specifies the sector(s) to be write protected. + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for S + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode f + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_WRP_SECTOR_All + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval HAL FLASH State + 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector) + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Check the parameters */ + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_WRP_SECTOR(WRPSector)); + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + ARM GAS /tmp/cc9TanaG.s page 34 + + + 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if(status == HAL_OK) + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /*Write protection enabled on sectors */ + 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->OPTCR &= (~WRPSector); + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** return status; + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Disable the write protection of the desired bank1 or bank 2 sectors + 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @note When the memory read protection level is selected (RDP level = 1), + 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * it is not possible to program or erase the flash sector i if CortexM4 + 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param WRPSector specifies the sector(s) to be write protected. + 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for S + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode f + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_WRP_Sector_All + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval HAL Status + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector) + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Check the parameters */ + 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_WRP_SECTOR(WRPSector)); + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if(status == HAL_OK) + 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Write protection disabled on sectors */ + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->OPTCR |= (WRPSector); + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** return status; + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Set the read protection level. + 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param Level specifies the read protection level. + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_RDP_LEVEL_0: No protection + 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_RDP_LEVEL_1: Read protection of the memory + 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_RDP_LEVEL_2: Full chip protection + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 + 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval HAL Status + ARM GAS /tmp/cc9TanaG.s page 35 + + + 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level) + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Check the parameters */ + 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_RDP_LEVEL(Level)); + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if(status == HAL_OK) + 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level; + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** return status; + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Set the BOR Level. + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param Level specifies the Option Bytes BOR Reset Level. + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval HAL Status + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level) + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 188 .loc 1 902 1 is_stmt 1 view -0 + 189 .cfi_startproc + 190 @ args = 0, pretend = 0, frame = 0 + 191 @ frame_needed = 0, uses_anonymous_args = 0 + 192 @ link register save eliminated. + 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Check the parameters */ + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_BOR_LEVEL(Level)); + 193 .loc 1 904 3 view .LVU40 + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Set the BOR Level */ + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level); + 194 .loc 1 907 3 view .LVU41 + 195 0000 034A ldr r2, .L16 + 196 0002 5369 ldr r3, [r2, #20] + 197 0004 23F00C03 bic r3, r3, #12 + 198 0008 1843 orrs r0, r0, r3 + 199 .LVL8: + 200 .loc 1 907 3 is_stmt 0 view .LVU42 + 201 000a 5061 str r0, [r2, #20] + 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** return HAL_OK; + 202 .loc 1 909 3 is_stmt 1 view .LVU43 + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 203 .loc 1 911 1 is_stmt 0 view .LVU44 + 204 000c 0020 movs r0, #0 + ARM GAS /tmp/cc9TanaG.s page 36 + + + 205 000e 7047 bx lr + 206 .L17: + 207 .align 2 + 208 .L16: + 209 0010 003C0240 .word 1073888256 + 210 .cfi_endproc + 211 .LFE153: + 213 .section .text.FLASH_OB_GetRDP,"ax",%progbits + 214 .align 1 + 215 .syntax unified + 216 .thumb + 217 .thumb_func + 219 FLASH_OB_GetRDP: + 220 .LFB155: + 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Configure Boot base address. + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param BootOption specifies Boot base address depending from Boot pin = 0 or pin = 1 + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param Address specifies Boot base address + 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) + 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) + 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000) + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000) + 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000) + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000) + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval HAL Status + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address) + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Check the parameters */ + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_BOOT_ADDRESS(Address)); + 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if(status == HAL_OK) + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if(BootOption == OPTIONBYTE_BOOTADDR_0) + 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address); + 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** else + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16)); + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** return status; + ARM GAS /tmp/cc9TanaG.s page 37 + + + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Returns the FLASH Read Protection level. + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval FlagStatus FLASH ReadOut Protection Status: + 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_RDP_LEVEL_0: No protection + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_RDP_LEVEL_1: Read protection of the memory + 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OB_RDP_LEVEL_2: Full chip protection + 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint8_t FLASH_OB_GetRDP(void) + 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 221 .loc 1 966 1 is_stmt 1 view -0 + 222 .cfi_startproc + 223 @ args = 0, pretend = 0, frame = 0 + 224 @ frame_needed = 0, uses_anonymous_args = 0 + 225 @ link register save eliminated. + 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint8_t readstatus = OB_RDP_LEVEL_0; + 226 .loc 1 967 3 view .LVU46 + 227 .LVL9: + 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0) + 228 .loc 1 969 3 view .LVU47 + 229 .loc 1 969 8 is_stmt 0 view .LVU48 + 230 0000 054B ldr r3, .L21 + 231 0002 587D ldrb r0, [r3, #21] @ zero_extendqisi2 + 232 0004 C0B2 uxtb r0, r0 + 233 .loc 1 969 6 view .LVU49 + 234 0006 AA28 cmp r0, #170 + 235 0008 04D0 beq .L19 + 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** readstatus = OB_RDP_LEVEL_0; + 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2) + 236 .loc 1 973 8 is_stmt 1 view .LVU50 + 237 .loc 1 973 13 is_stmt 0 view .LVU51 + 238 000a 587D ldrb r0, [r3, #21] @ zero_extendqisi2 + 239 000c C0B2 uxtb r0, r0 + 240 .loc 1 973 11 view .LVU52 + 241 000e CC28 cmp r0, #204 + 242 0010 00D0 beq .L19 + 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** readstatus = OB_RDP_LEVEL_2; + 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** else + 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** readstatus = OB_RDP_LEVEL_1; + 243 .loc 1 979 16 view .LVU53 + 244 0012 5520 movs r0, #85 + 245 .L19: + 246 .LVL10: + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** return readstatus; + 247 .loc 1 982 3 is_stmt 1 view .LVU54 + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 248 .loc 1 983 1 is_stmt 0 view .LVU55 + ARM GAS /tmp/cc9TanaG.s page 38 + + + 249 0014 7047 bx lr + 250 .L22: + 251 0016 00BF .align 2 + 252 .L21: + 253 0018 003C0240 .word 1073888256 + 254 .cfi_endproc + 255 .LFE155: + 257 .section .text.FLASH_OB_GetBOR,"ax",%progbits + 258 .align 1 + 259 .syntax unified + 260 .thumb + 261 .thumb_func + 263 FLASH_OB_GetBOR: + 264 .LFB156: + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Returns the FLASH BOR level. + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval uint32_t The FLASH BOR level: + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetBOR(void) + 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 265 .loc 1 994 1 is_stmt 1 view -0 + 266 .cfi_startproc + 267 @ args = 0, pretend = 0, frame = 0 + 268 @ frame_needed = 0, uses_anonymous_args = 0 + 269 @ link register save eliminated. + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Return the FLASH BOR level */ + 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** return ((uint32_t)(FLASH->OPTCR & 0x0C)); + 270 .loc 1 996 3 view .LVU57 + 271 .loc 1 996 27 is_stmt 0 view .LVU58 + 272 0000 024B ldr r3, .L24 + 273 0002 5869 ldr r0, [r3, #20] + 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 274 .loc 1 997 1 view .LVU59 + 275 0004 00F00C00 and r0, r0, #12 + 276 0008 7047 bx lr + 277 .L25: + 278 000a 00BF .align 2 + 279 .L24: + 280 000c 003C0240 .word 1073888256 + 281 .cfi_endproc + 282 .LFE156: + 284 .section .text.FLASH_OB_GetBootAddress,"ax",%progbits + 285 .align 1 + 286 .syntax unified + 287 .thumb + 288 .thumb_func + 290 FLASH_OB_GetBootAddress: + 291 .LVL11: + 292 .LFB157: + 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @brief Configure Boot base address. + ARM GAS /tmp/cc9TanaG.s page 39 + + +1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * +1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @param BootOption specifies Boot base address depending from Boot pin = 0 or pin = 1 +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * This parameter can be one of the following values: +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 +1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 +1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * @retval uint32_t Boot Base Address: +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) +1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000) +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000) +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000) +1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000) +1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** * - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) +1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** */ +1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption) +1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 293 .loc 1 1017 1 is_stmt 1 view -0 + 294 .cfi_startproc + 295 @ args = 0, pretend = 0, frame = 0 + 296 @ frame_needed = 0, uses_anonymous_args = 0 + 297 @ link register save eliminated. +1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t Address = 0; + 298 .loc 1 1018 3 view .LVU61 +1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /* Return the Boot base Address */ +1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if(BootOption == OPTIONBYTE_BOOTADDR_0) + 299 .loc 1 1021 3 view .LVU62 + 300 .loc 1 1021 5 is_stmt 0 view .LVU63 + 301 0000 1028 cmp r0, #16 + 302 0002 03D0 beq .L29 +1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0; +1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** else +1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { +1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** Address = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16); + 303 .loc 1 1027 3 is_stmt 1 view .LVU64 + 304 .loc 1 1027 20 is_stmt 0 view .LVU65 + 305 0004 034B ldr r3, .L30 + 306 0006 9869 ldr r0, [r3, #24] + 307 .LVL12: + 308 .loc 1 1027 55 view .LVU66 + 309 0008 000C lsrs r0, r0, #16 + 310 .LVL13: +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } +1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** return Address; + 311 .loc 1 1030 3 is_stmt 1 view .LVU67 +1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 312 .loc 1 1031 1 is_stmt 0 view .LVU68 + 313 000a 7047 bx lr + 314 .LVL14: + 315 .L29: +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 316 .loc 1 1023 5 is_stmt 1 view .LVU69 +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + ARM GAS /tmp/cc9TanaG.s page 40 + + + 317 .loc 1 1023 20 is_stmt 0 view .LVU70 + 318 000c 014B ldr r3, .L30 + 319 000e 9869 ldr r0, [r3, #24] + 320 .LVL15: +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 321 .loc 1 1023 13 view .LVU71 + 322 0010 80B2 uxth r0, r0 + 323 .LVL16: +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 324 .loc 1 1023 13 view .LVU72 + 325 0012 7047 bx lr + 326 .L31: + 327 .align 2 + 328 .L30: + 329 0014 003C0240 .word 1073888256 + 330 .cfi_endproc + 331 .LFE157: + 333 .section .text.FLASH_OB_EnableWRP,"ax",%progbits + 334 .align 1 + 335 .syntax unified + 336 .thumb + 337 .thumb_func + 339 FLASH_OB_EnableWRP: + 340 .LVL17: + 341 .LFB150: + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 342 .loc 1 807 1 is_stmt 1 view -0 + 343 .cfi_startproc + 344 @ args = 0, pretend = 0, frame = 0 + 345 @ frame_needed = 0, uses_anonymous_args = 0 + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 346 .loc 1 807 1 is_stmt 0 view .LVU74 + 347 0000 10B5 push {r4, lr} + 348 .LCFI0: + 349 .cfi_def_cfa_offset 8 + 350 .cfi_offset 4, -8 + 351 .cfi_offset 14, -4 + 352 0002 0446 mov r4, r0 + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 353 .loc 1 808 3 is_stmt 1 view .LVU75 + 354 .LVL18: + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 355 .loc 1 811 3 view .LVU76 + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 356 .loc 1 814 3 view .LVU77 + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 357 .loc 1 814 12 is_stmt 0 view .LVU78 + 358 0004 4CF25030 movw r0, #50000 + 359 .LVL19: + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 360 .loc 1 814 12 view .LVU79 + 361 0008 FFF7FEFF bl FLASH_WaitForLastOperation + 362 .LVL20: + 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 363 .loc 1 816 3 is_stmt 1 view .LVU80 + 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 364 .loc 1 816 5 is_stmt 0 view .LVU81 + ARM GAS /tmp/cc9TanaG.s page 41 + + + 365 000c 20B9 cbnz r0, .L33 + 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 366 .loc 1 819 5 is_stmt 1 view .LVU82 + 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 367 .loc 1 819 10 is_stmt 0 view .LVU83 + 368 000e 034A ldr r2, .L35 + 369 0010 5369 ldr r3, [r2, #20] + 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 370 .loc 1 819 18 view .LVU84 + 371 0012 23EA0403 bic r3, r3, r4 + 372 0016 5361 str r3, [r2, #20] + 373 .L33: + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 374 .loc 1 822 3 is_stmt 1 view .LVU85 + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 375 .loc 1 823 1 is_stmt 0 view .LVU86 + 376 0018 10BD pop {r4, pc} + 377 .LVL21: + 378 .L36: + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 379 .loc 1 823 1 view .LVU87 + 380 001a 00BF .align 2 + 381 .L35: + 382 001c 003C0240 .word 1073888256 + 383 .cfi_endproc + 384 .LFE150: + 386 .section .text.FLASH_OB_DisableWRP,"ax",%progbits + 387 .align 1 + 388 .syntax unified + 389 .thumb + 390 .thumb_func + 392 FLASH_OB_DisableWRP: + 393 .LVL22: + 394 .LFB151: + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 395 .loc 1 843 1 is_stmt 1 view -0 + 396 .cfi_startproc + 397 @ args = 0, pretend = 0, frame = 0 + 398 @ frame_needed = 0, uses_anonymous_args = 0 + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 399 .loc 1 843 1 is_stmt 0 view .LVU89 + 400 0000 10B5 push {r4, lr} + 401 .LCFI1: + 402 .cfi_def_cfa_offset 8 + 403 .cfi_offset 4, -8 + 404 .cfi_offset 14, -4 + 405 0002 0446 mov r4, r0 + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 406 .loc 1 844 3 is_stmt 1 view .LVU90 + 407 .LVL23: + 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 408 .loc 1 847 3 view .LVU91 + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 409 .loc 1 850 3 view .LVU92 + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 410 .loc 1 850 12 is_stmt 0 view .LVU93 + 411 0004 4CF25030 movw r0, #50000 + ARM GAS /tmp/cc9TanaG.s page 42 + + + 412 .LVL24: + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 413 .loc 1 850 12 view .LVU94 + 414 0008 FFF7FEFF bl FLASH_WaitForLastOperation + 415 .LVL25: + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 416 .loc 1 852 3 is_stmt 1 view .LVU95 + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 417 .loc 1 852 5 is_stmt 0 view .LVU96 + 418 000c 18B9 cbnz r0, .L38 + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 419 .loc 1 855 5 is_stmt 1 view .LVU97 + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 420 .loc 1 855 10 is_stmt 0 view .LVU98 + 421 000e 024A ldr r2, .L40 + 422 0010 5369 ldr r3, [r2, #20] + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 423 .loc 1 855 18 view .LVU99 + 424 0012 2343 orrs r3, r3, r4 + 425 0014 5361 str r3, [r2, #20] + 426 .L38: + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 427 .loc 1 858 3 is_stmt 1 view .LVU100 + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 428 .loc 1 859 1 is_stmt 0 view .LVU101 + 429 0016 10BD pop {r4, pc} + 430 .LVL26: + 431 .L41: + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 432 .loc 1 859 1 view .LVU102 + 433 .align 2 + 434 .L40: + 435 0018 003C0240 .word 1073888256 + 436 .cfi_endproc + 437 .LFE151: + 439 .section .text.FLASH_OB_RDP_LevelConfig,"ax",%progbits + 440 .align 1 + 441 .syntax unified + 442 .thumb + 443 .thumb_func + 445 FLASH_OB_RDP_LevelConfig: + 446 .LVL27: + 447 .LFB152: + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 448 .loc 1 874 1 is_stmt 1 view -0 + 449 .cfi_startproc + 450 @ args = 0, pretend = 0, frame = 0 + 451 @ frame_needed = 0, uses_anonymous_args = 0 + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 452 .loc 1 874 1 is_stmt 0 view .LVU104 + 453 0000 10B5 push {r4, lr} + 454 .LCFI2: + 455 .cfi_def_cfa_offset 8 + 456 .cfi_offset 4, -8 + 457 .cfi_offset 14, -4 + 458 0002 0446 mov r4, r0 + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + ARM GAS /tmp/cc9TanaG.s page 43 + + + 459 .loc 1 875 3 is_stmt 1 view .LVU105 + 460 .LVL28: + 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 461 .loc 1 878 3 view .LVU106 + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 462 .loc 1 881 3 view .LVU107 + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 463 .loc 1 881 12 is_stmt 0 view .LVU108 + 464 0004 4CF25030 movw r0, #50000 + 465 .LVL29: + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 466 .loc 1 881 12 view .LVU109 + 467 0008 FFF7FEFF bl FLASH_WaitForLastOperation + 468 .LVL30: + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 469 .loc 1 883 3 is_stmt 1 view .LVU110 + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 470 .loc 1 883 5 is_stmt 0 view .LVU111 + 471 000c 08B9 cbnz r0, .L43 + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 472 .loc 1 885 5 is_stmt 1 view .LVU112 + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 473 .loc 1 885 41 is_stmt 0 view .LVU113 + 474 000e 014B ldr r3, .L45 + 475 0010 5C75 strb r4, [r3, #21] + 476 .L43: + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 477 .loc 1 888 3 is_stmt 1 view .LVU114 + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 478 .loc 1 889 1 is_stmt 0 view .LVU115 + 479 0012 10BD pop {r4, pc} + 480 .LVL31: + 481 .L46: + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 482 .loc 1 889 1 view .LVU116 + 483 .align 2 + 484 .L45: + 485 0014 003C0240 .word 1073888256 + 486 .cfi_endproc + 487 .LFE152: + 489 .section .text.FLASH_OB_UserConfig,"ax",%progbits + 490 .align 1 + 491 .syntax unified + 492 .thumb + 493 .thumb_func + 495 FLASH_OB_UserConfig: + 496 .LVL32: + 497 .LFB148: + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t useroptionmask = 0x00; + 498 .loc 1 578 1 is_stmt 1 view -0 + 499 .cfi_startproc + 500 @ args = 16, pretend = 0, frame = 0 + 501 @ frame_needed = 0, uses_anonymous_args = 0 + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t useroptionmask = 0x00; + 502 .loc 1 578 1 is_stmt 0 view .LVU118 + 503 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 504 .LCFI3: + ARM GAS /tmp/cc9TanaG.s page 44 + + + 505 .cfi_def_cfa_offset 24 + 506 .cfi_offset 3, -24 + 507 .cfi_offset 4, -20 + 508 .cfi_offset 5, -16 + 509 .cfi_offset 6, -12 + 510 .cfi_offset 7, -8 + 511 .cfi_offset 14, -4 + 512 0002 0746 mov r7, r0 + 513 0004 0C46 mov r4, r1 + 514 0006 1646 mov r6, r2 + 515 0008 1D46 mov r5, r3 + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t useroptionvalue = 0x00; + 516 .loc 1 579 3 is_stmt 1 view .LVU119 + 517 .LVL33: + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 518 .loc 1 580 3 view .LVU120 + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 519 .loc 1 582 3 view .LVU121 + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_IWDG_SOURCE(Iwdg)); + 520 .loc 1 585 3 view .LVU122 + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_STOP_SOURCE(Stop)); + 521 .loc 1 586 3 view .LVU123 + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_STDBY_SOURCE(Stdby)); + 522 .loc 1 587 3 view .LVU124 + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop)); + 523 .loc 1 588 3 view .LVU125 + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby)); + 524 .loc 1 589 3 view .LVU126 + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_NDBANK(NDBank)); + 525 .loc 1 590 3 view .LVU127 + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_OB_NDBOOT(NDBoot)); + 526 .loc 1 591 3 view .LVU128 + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 527 .loc 1 592 3 view .LVU129 + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 528 .loc 1 595 3 view .LVU130 + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 529 .loc 1 595 12 is_stmt 0 view .LVU131 + 530 000a 4CF25030 movw r0, #50000 + 531 .LVL34: + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 532 .loc 1 595 12 view .LVU132 + 533 000e FFF7FEFF bl FLASH_WaitForLastOperation + 534 .LVL35: + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 535 .loc 1 597 3 is_stmt 1 view .LVU133 + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 536 .loc 1 597 5 is_stmt 0 view .LVU134 + 537 0012 98B9 cbnz r0, .L48 + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \ + 538 .loc 1 599 5 is_stmt 1 view .LVU135 + 539 .LVL36: + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 540 .loc 1 603 5 view .LVU136 + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 541 .loc 1 603 29 is_stmt 0 view .LVU137 + 542 0014 44EA0701 orr r1, r4, r7 + ARM GAS /tmp/cc9TanaG.s page 45 + + + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 543 .loc 1 603 36 view .LVU138 + 544 0018 41EA0602 orr r2, r1, r6 + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 545 .loc 1 603 43 view .LVU139 + 546 001c 42EA0503 orr r3, r2, r5 + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 547 .loc 1 603 51 view .LVU140 + 548 0020 069A ldr r2, [sp, #24] + 549 0022 1343 orrs r3, r3, r2 + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 550 .loc 1 603 62 view .LVU141 + 551 0024 079A ldr r2, [sp, #28] + 552 0026 1343 orrs r3, r3, r2 + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 553 .loc 1 603 74 view .LVU142 + 554 0028 099A ldr r2, [sp, #36] + 555 002a 1343 orrs r3, r3, r2 + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 556 .loc 1 603 21 view .LVU143 + 557 002c 089A ldr r2, [sp, #32] + 558 002e 1343 orrs r3, r3, r2 + 559 .LVL37: + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 560 .loc 1 606 5 is_stmt 1 view .LVU144 + 561 0030 0349 ldr r1, .L50 + 562 0032 4C69 ldr r4, [r1, #20] + 563 .LVL38: + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 564 .loc 1 606 5 is_stmt 0 view .LVU145 + 565 0034 034A ldr r2, .L50+4 + 566 0036 2240 ands r2, r2, r4 + 567 0038 1A43 orrs r2, r2, r3 + 568 003a 4A61 str r2, [r1, #20] + 569 .LVL39: + 570 .L48: + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 571 .loc 1 609 3 is_stmt 1 view .LVU146 + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 572 .loc 1 610 1 is_stmt 0 view .LVU147 + 573 003c F8BD pop {r3, r4, r5, r6, r7, pc} + 574 .LVL40: + 575 .L51: + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 576 .loc 1 610 1 view .LVU148 + 577 003e 00BF .align 2 + 578 .L50: + 579 0040 003C0240 .word 1073888256 + 580 0044 0FFFFF0F .word 268435215 + 581 .cfi_endproc + 582 .LFE148: + 584 .section .text.FLASH_OB_BootAddressConfig,"ax",%progbits + 585 .align 1 + 586 .syntax unified + 587 .thumb + 588 .thumb_func + 590 FLASH_OB_BootAddressConfig: + ARM GAS /tmp/cc9TanaG.s page 46 + + + 591 .LVL41: + 592 .LFB154: + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 593 .loc 1 933 1 is_stmt 1 view -0 + 594 .cfi_startproc + 595 @ args = 0, pretend = 0, frame = 0 + 596 @ frame_needed = 0, uses_anonymous_args = 0 + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 597 .loc 1 933 1 is_stmt 0 view .LVU150 + 598 0000 38B5 push {r3, r4, r5, lr} + 599 .LCFI4: + 600 .cfi_def_cfa_offset 16 + 601 .cfi_offset 3, -16 + 602 .cfi_offset 4, -12 + 603 .cfi_offset 5, -8 + 604 .cfi_offset 14, -4 + 605 0002 0446 mov r4, r0 + 606 0004 0D46 mov r5, r1 + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 607 .loc 1 934 3 is_stmt 1 view .LVU151 + 608 .LVL42: + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 609 .loc 1 937 3 view .LVU152 + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 610 .loc 1 940 3 view .LVU153 + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 611 .loc 1 940 12 is_stmt 0 view .LVU154 + 612 0006 4CF25030 movw r0, #50000 + 613 .LVL43: + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 614 .loc 1 940 12 view .LVU155 + 615 000a FFF7FEFF bl FLASH_WaitForLastOperation + 616 .LVL44: + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 617 .loc 1 942 3 is_stmt 1 view .LVU156 + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 618 .loc 1 942 5 is_stmt 0 view .LVU157 + 619 000e 38B9 cbnz r0, .L53 + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 620 .loc 1 944 5 is_stmt 1 view .LVU158 + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 621 .loc 1 944 7 is_stmt 0 view .LVU159 + 622 0010 102C cmp r4, #16 + 623 0012 06D0 beq .L56 + 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 624 .loc 1 950 7 is_stmt 1 view .LVU160 + 625 0014 064A ldr r2, .L57 + 626 0016 9369 ldr r3, [r2, #24] + 627 0018 9BB2 uxth r3, r3 + 628 001a 43EA0543 orr r3, r3, r5, lsl #16 + 629 001e 9361 str r3, [r2, #24] + 630 .L53: + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 631 .loc 1 954 3 view .LVU161 + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 632 .loc 1 955 1 is_stmt 0 view .LVU162 + 633 0020 38BD pop {r3, r4, r5, pc} + ARM GAS /tmp/cc9TanaG.s page 47 + + + 634 .LVL45: + 635 .L56: + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 636 .loc 1 946 7 is_stmt 1 view .LVU163 + 637 0022 034A ldr r2, .L57 + 638 0024 9369 ldr r3, [r2, #24] + 639 0026 6FF30F03 bfc r3, #0, #16 + 640 002a 2B43 orrs r3, r3, r5 + 641 002c 9361 str r3, [r2, #24] + 642 002e F7E7 b .L53 + 643 .L58: + 644 .align 2 + 645 .L57: + 646 0030 003C0240 .word 1073888256 + 647 .cfi_endproc + 648 .LFE154: + 650 .section .text.HAL_FLASHEx_OBProgram,"ax",%progbits + 651 .align 1 + 652 .global HAL_FLASHEx_OBProgram + 653 .syntax unified + 654 .thumb + 655 .thumb_func + 657 HAL_FLASHEx_OBProgram: + 658 .LVL46: + 659 .LFB143: + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 660 .loc 1 286 1 view -0 + 661 .cfi_startproc + 662 @ args = 0, pretend = 0, frame = 0 + 663 @ frame_needed = 0, uses_anonymous_args = 0 + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 664 .loc 1 287 3 view .LVU165 + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 665 .loc 1 290 3 view .LVU166 + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 666 .loc 1 290 3 view .LVU167 + 667 0000 2F4B ldr r3, .L80 + 668 0002 1B7D ldrb r3, [r3, #20] @ zero_extendqisi2 + 669 0004 012B cmp r3, #1 + 670 0006 58D0 beq .L68 + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 671 .loc 1 286 1 is_stmt 0 view .LVU168 + 672 0008 10B5 push {r4, lr} + 673 .LCFI5: + 674 .cfi_def_cfa_offset 8 + 675 .cfi_offset 4, -8 + 676 .cfi_offset 14, -4 + 677 000a 84B0 sub sp, sp, #16 + 678 .LCFI6: + 679 .cfi_def_cfa_offset 24 + 680 000c 0446 mov r4, r0 + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 681 .loc 1 290 3 is_stmt 1 discriminator 2 view .LVU169 + 682 000e 2C4B ldr r3, .L80 + 683 0010 0122 movs r2, #1 + 684 0012 1A75 strb r2, [r3, #20] + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + ARM GAS /tmp/cc9TanaG.s page 48 + + + 685 .loc 1 290 3 discriminator 2 view .LVU170 + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 686 .loc 1 293 3 view .LVU171 + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 687 .loc 1 296 3 view .LVU172 + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 688 .loc 1 296 14 is_stmt 0 view .LVU173 + 689 0014 0368 ldr r3, [r0] + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 690 .loc 1 296 5 view .LVU174 + 691 0016 13F0010F tst r3, #1 + 692 001a 0AD0 beq .L69 + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** if(pOBInit->WRPState == OB_WRPSTATE_ENABLE) + 693 .loc 1 298 5 is_stmt 1 view .LVU175 + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 694 .loc 1 299 5 view .LVU176 + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 695 .loc 1 299 15 is_stmt 0 view .LVU177 + 696 001c 4368 ldr r3, [r0, #4] + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 697 .loc 1 299 7 view .LVU178 + 698 001e 9342 cmp r3, r2 + 699 0020 03D0 beq .L74 + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 700 .loc 1 307 7 is_stmt 1 view .LVU179 + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 701 .loc 1 307 16 is_stmt 0 view .LVU180 + 702 0022 8068 ldr r0, [r0, #8] + 703 .LVL47: + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 704 .loc 1 307 16 view .LVU181 + 705 0024 FFF7FEFF bl FLASH_OB_DisableWRP + 706 .LVL48: + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 707 .loc 1 307 16 view .LVU182 + 708 0028 04E0 b .L61 + 709 .LVL49: + 710 .L74: + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 711 .loc 1 302 7 is_stmt 1 view .LVU183 + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 712 .loc 1 302 16 is_stmt 0 view .LVU184 + 713 002a 8068 ldr r0, [r0, #8] + 714 .LVL50: + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 715 .loc 1 302 16 view .LVU185 + 716 002c FFF7FEFF bl FLASH_OB_EnableWRP + 717 .LVL51: + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 718 .loc 1 302 16 view .LVU186 + 719 0030 00E0 b .L61 + 720 .LVL52: + 721 .L69: + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 722 .loc 1 287 21 view .LVU187 + 723 0032 0120 movs r0, #1 + 724 .LVL53: + ARM GAS /tmp/cc9TanaG.s page 49 + + + 725 .L61: + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 726 .loc 1 312 3 is_stmt 1 view .LVU188 + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 727 .loc 1 312 14 is_stmt 0 view .LVU189 + 728 0034 2368 ldr r3, [r4] + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 729 .loc 1 312 5 view .LVU190 + 730 0036 13F0020F tst r3, #2 + 731 003a 14D1 bne .L75 + 732 .L63: + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 733 .loc 1 318 3 is_stmt 1 view .LVU191 + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 734 .loc 1 318 14 is_stmt 0 view .LVU192 + 735 003c 2368 ldr r3, [r4] + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 736 .loc 1 318 5 view .LVU193 + 737 003e 13F0040F tst r3, #4 + 738 0042 14D1 bne .L76 + 739 .L64: + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 740 .loc 1 340 3 is_stmt 1 view .LVU194 + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 741 .loc 1 340 14 is_stmt 0 view .LVU195 + 742 0044 2368 ldr r3, [r4] + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 743 .loc 1 340 5 view .LVU196 + 744 0046 13F0080F tst r3, #8 + 745 004a 28D1 bne .L77 + 746 .L65: + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 747 .loc 1 346 3 is_stmt 1 view .LVU197 + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 748 .loc 1 346 14 is_stmt 0 view .LVU198 + 749 004c 2368 ldr r3, [r4] + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 750 .loc 1 346 5 view .LVU199 + 751 004e 13F0100F tst r3, #16 + 752 0052 28D1 bne .L78 + 753 .L66: + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 754 .loc 1 352 3 is_stmt 1 view .LVU200 + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 755 .loc 1 352 14 is_stmt 0 view .LVU201 + 756 0054 2368 ldr r3, [r4] + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 757 .loc 1 352 5 view .LVU202 + 758 0056 13F0200F tst r3, #32 + 759 005a 29D1 bne .L79 + 760 .L67: + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 761 .loc 1 372 3 is_stmt 1 view .LVU203 + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 762 .loc 1 372 3 view .LVU204 + 763 005c 184B ldr r3, .L80 + 764 005e 0022 movs r2, #0 + ARM GAS /tmp/cc9TanaG.s page 50 + + + 765 0060 1A75 strb r2, [r3, #20] + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 766 .loc 1 372 3 view .LVU205 + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 767 .loc 1 374 3 view .LVU206 + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 768 .loc 1 375 1 is_stmt 0 view .LVU207 + 769 0062 04B0 add sp, sp, #16 + 770 .LCFI7: + 771 .cfi_remember_state + 772 .cfi_def_cfa_offset 8 + 773 @ sp needed + 774 0064 10BD pop {r4, pc} + 775 .LVL54: + 776 .L75: + 777 .LCFI8: + 778 .cfi_restore_state + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 779 .loc 1 314 5 is_stmt 1 view .LVU208 + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 780 .loc 1 314 14 is_stmt 0 view .LVU209 + 781 0066 207B ldrb r0, [r4, #12] @ zero_extendqisi2 + 782 .LVL55: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 783 .loc 1 314 14 view .LVU210 + 784 0068 FFF7FEFF bl FLASH_OB_RDP_LevelConfig + 785 .LVL56: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 786 .loc 1 314 14 view .LVU211 + 787 006c E6E7 b .L63 + 788 .L76: + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->USERConfig & OB_IWDG_SW, + 789 .loc 1 321 5 is_stmt 1 view .LVU212 + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->USERConfig & OB_IWDG_SW, + 790 .loc 1 321 41 is_stmt 0 view .LVU213 + 791 006e 6069 ldr r0, [r4, #20] + 792 .LVL57: + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->USERConfig & OB_IWDG_SW, + 793 .loc 1 321 14 view .LVU214 + 794 0070 00F08053 and r3, r0, #268435456 + 795 0074 0393 str r3, [sp, #12] + 796 0076 00F00053 and r3, r0, #536870912 + 797 007a 0293 str r3, [sp, #8] + 798 007c 00F08043 and r3, r0, #1073741824 + 799 0080 0193 str r3, [sp, #4] + 800 0082 00F00043 and r3, r0, #-2147483648 + 801 0086 0093 str r3, [sp] + 802 0088 00F08003 and r3, r0, #128 + 803 008c 00F04002 and r2, r0, #64 + 804 0090 00F02001 and r1, r0, #32 + 805 0094 00F01000 and r0, r0, #16 + 806 0098 FFF7FEFF bl FLASH_OB_UserConfig + 807 .LVL58: + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->USERConfig & OB_IWDG_SW, + 808 .loc 1 321 14 view .LVU215 + 809 009c D2E7 b .L64 + 810 .L77: + ARM GAS /tmp/cc9TanaG.s page 51 + + + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 811 .loc 1 342 5 is_stmt 1 view .LVU216 + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 812 .loc 1 342 14 is_stmt 0 view .LVU217 + 813 009e 207C ldrb r0, [r4, #16] @ zero_extendqisi2 + 814 .LVL59: + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 815 .loc 1 342 14 view .LVU218 + 816 00a0 FFF7FEFF bl FLASH_OB_BOR_LevelConfig + 817 .LVL60: + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 818 .loc 1 342 14 view .LVU219 + 819 00a4 D2E7 b .L65 + 820 .L78: + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 821 .loc 1 348 5 is_stmt 1 view .LVU220 + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 822 .loc 1 348 14 is_stmt 0 view .LVU221 + 823 00a6 A169 ldr r1, [r4, #24] + 824 00a8 1020 movs r0, #16 + 825 .LVL61: + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 826 .loc 1 348 14 view .LVU222 + 827 00aa FFF7FEFF bl FLASH_OB_BootAddressConfig + 828 .LVL62: + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 829 .loc 1 348 14 view .LVU223 + 830 00ae D1E7 b .L66 + 831 .L79: + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 832 .loc 1 354 5 is_stmt 1 view .LVU224 + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 833 .loc 1 354 14 is_stmt 0 view .LVU225 + 834 00b0 E169 ldr r1, [r4, #28] + 835 00b2 2020 movs r0, #32 + 836 .LVL63: + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 837 .loc 1 354 14 view .LVU226 + 838 00b4 FFF7FEFF bl FLASH_OB_BootAddressConfig + 839 .LVL64: + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 840 .loc 1 354 14 view .LVU227 + 841 00b8 D0E7 b .L67 + 842 .LVL65: + 843 .L68: + 844 .LCFI9: + 845 .cfi_def_cfa_offset 0 + 846 .cfi_restore 4 + 847 .cfi_restore 14 + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 848 .loc 1 290 3 discriminator 1 view .LVU228 + 849 00ba 0220 movs r0, #2 + 850 .LVL66: + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 851 .loc 1 375 1 view .LVU229 + 852 00bc 7047 bx lr + 853 .L81: + ARM GAS /tmp/cc9TanaG.s page 52 + + + 854 00be 00BF .align 2 + 855 .L80: + 856 00c0 00000000 .word pFlash + 857 .cfi_endproc + 858 .LFE143: + 860 .section .text.HAL_FLASHEx_OBGetConfig,"ax",%progbits + 861 .align 1 + 862 .global HAL_FLASHEx_OBGetConfig + 863 .syntax unified + 864 .thumb + 865 .thumb_func + 867 HAL_FLASHEx_OBGetConfig: + 868 .LVL67: + 869 .LFB144: + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + 870 .loc 1 385 1 is_stmt 1 view -0 + 871 .cfi_startproc + 872 @ args = 0, pretend = 0, frame = 0 + 873 @ frame_needed = 0, uses_anonymous_args = 0 + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + 874 .loc 1 385 1 is_stmt 0 view .LVU231 + 875 0000 10B5 push {r4, lr} + 876 .LCFI10: + 877 .cfi_def_cfa_offset 8 + 878 .cfi_offset 4, -8 + 879 .cfi_offset 14, -4 + 880 0002 0446 mov r4, r0 + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1; + 881 .loc 1 386 3 is_stmt 1 view .LVU232 + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1; + 882 .loc 1 386 23 is_stmt 0 view .LVU233 + 883 0004 3F23 movs r3, #63 + 884 0006 0360 str r3, [r0] + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 885 .loc 1 390 3 is_stmt 1 view .LVU234 + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 886 .loc 1 390 24 is_stmt 0 view .LVU235 + 887 0008 FFF7FEFF bl FLASH_OB_GetWRP + 888 .LVL68: + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 889 .loc 1 390 22 discriminator 1 view .LVU236 + 890 000c A060 str r0, [r4, #8] + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 891 .loc 1 393 3 is_stmt 1 view .LVU237 + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 892 .loc 1 393 23 is_stmt 0 view .LVU238 + 893 000e FFF7FEFF bl FLASH_OB_GetRDP + 894 .LVL69: + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 895 .loc 1 393 21 discriminator 1 view .LVU239 + 896 0012 E060 str r0, [r4, #12] + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 897 .loc 1 396 3 is_stmt 1 view .LVU240 + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 898 .loc 1 396 25 is_stmt 0 view .LVU241 + 899 0014 FFF7FEFF bl FLASH_OB_GetUser + 900 .LVL70: + ARM GAS /tmp/cc9TanaG.s page 53 + + + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 901 .loc 1 396 23 discriminator 1 view .LVU242 + 902 0018 6061 str r0, [r4, #20] + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 903 .loc 1 399 3 is_stmt 1 view .LVU243 + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 904 .loc 1 399 23 is_stmt 0 view .LVU244 + 905 001a FFF7FEFF bl FLASH_OB_GetBOR + 906 .LVL71: + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 907 .loc 1 399 21 discriminator 1 view .LVU245 + 908 001e 2061 str r0, [r4, #16] + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 909 .loc 1 402 3 is_stmt 1 view .LVU246 + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 910 .loc 1 402 24 is_stmt 0 view .LVU247 + 911 0020 1020 movs r0, #16 + 912 0022 FFF7FEFF bl FLASH_OB_GetBootAddress + 913 .LVL72: + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 914 .loc 1 402 22 discriminator 1 view .LVU248 + 915 0026 A061 str r0, [r4, #24] + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 916 .loc 1 405 3 is_stmt 1 view .LVU249 + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 917 .loc 1 405 24 is_stmt 0 view .LVU250 + 918 0028 2020 movs r0, #32 + 919 002a FFF7FEFF bl FLASH_OB_GetBootAddress + 920 .LVL73: + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 921 .loc 1 405 22 discriminator 1 view .LVU251 + 922 002e E061 str r0, [r4, #28] + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 923 .loc 1 414 1 view .LVU252 + 924 0030 10BD pop {r4, pc} + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** /** + 925 .loc 1 414 1 view .LVU253 + 926 .cfi_endproc + 927 .LFE144: + 929 .section .text.FLASH_Erase_Sector,"ax",%progbits + 930 .align 1 + 931 .global FLASH_Erase_Sector + 932 .syntax unified + 933 .thumb + 934 .thumb_func + 936 FLASH_Erase_Sector: + 937 .LVL74: + 938 .LFB146: + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t tmp_psize = 0; + 939 .loc 1 487 1 is_stmt 1 view -0 + 940 .cfi_startproc + 941 @ args = 0, pretend = 0, frame = 0 + 942 @ frame_needed = 0, uses_anonymous_args = 0 + 943 @ link register save eliminated. + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 944 .loc 1 488 3 view .LVU255 + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** assert_param(IS_VOLTAGERANGE(VoltageRange)); + ARM GAS /tmp/cc9TanaG.s page 54 + + + 945 .loc 1 491 3 view .LVU256 + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 946 .loc 1 492 3 view .LVU257 + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 947 .loc 1 494 3 view .LVU258 + 948 0000 0129 cmp r1, #1 + 949 0002 05D0 beq .L87 + 950 0004 0229 cmp r1, #2 + 951 0006 06D0 beq .L88 + 952 0008 39B1 cbz r1, .L85 + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t tmp_psize = 0; + 953 .loc 1 487 1 is_stmt 0 view .LVU259 + 954 000a 4FF44071 mov r1, #768 + 955 .LVL75: + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t tmp_psize = 0; + 956 .loc 1 487 1 view .LVU260 + 957 000e 04E0 b .L85 + 958 .LVL76: + 959 .L87: + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t tmp_psize = 0; + 960 .loc 1 487 1 view .LVU261 + 961 0010 4FF48071 mov r1, #256 + 962 .LVL77: + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t tmp_psize = 0; + 963 .loc 1 487 1 view .LVU262 + 964 0014 01E0 b .L85 + 965 .LVL78: + 966 .L88: + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t tmp_psize = 0; + 967 .loc 1 487 1 view .LVU263 + 968 0016 4FF40071 mov r1, #512 + 969 .LVL79: + 970 .L85: + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 971 .loc 1 512 3 is_stmt 1 view .LVU264 + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 972 .loc 1 512 5 is_stmt 0 view .LVU265 + 973 001a 0B28 cmp r0, #11 + 974 001c 00D9 bls .L86 + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 975 .loc 1 514 5 is_stmt 1 view .LVU266 + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 976 .loc 1 514 12 is_stmt 0 view .LVU267 + 977 001e 0430 adds r0, r0, #4 + 978 .LVL80: + 979 .L86: + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR |= tmp_psize; + 980 .loc 1 518 3 is_stmt 1 view .LVU268 + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR |= tmp_psize; + 981 .loc 1 518 8 is_stmt 0 view .LVU269 + 982 0020 0C4B ldr r3, .L90 + 983 0022 1A69 ldr r2, [r3, #16] + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR |= tmp_psize; + 984 .loc 1 518 13 view .LVU270 + 985 0024 22F44072 bic r2, r2, #768 + 986 0028 1A61 str r2, [r3, #16] + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); + ARM GAS /tmp/cc9TanaG.s page 55 + + + 987 .loc 1 519 3 is_stmt 1 view .LVU271 + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); + 988 .loc 1 519 8 is_stmt 0 view .LVU272 + 989 002a 1A69 ldr r2, [r3, #16] + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); + 990 .loc 1 519 13 view .LVU273 + 991 002c 0A43 orrs r2, r2, r1 + 992 002e 1A61 str r2, [r3, #16] + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); + 993 .loc 1 520 3 is_stmt 1 view .LVU274 + 994 0030 1A69 ldr r2, [r3, #16] + 995 0032 22F0F802 bic r2, r2, #248 + 996 0036 1A61 str r2, [r3, #16] + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR |= FLASH_CR_STRT; + 997 .loc 1 521 3 view .LVU275 + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR |= FLASH_CR_STRT; + 998 .loc 1 521 8 is_stmt 0 view .LVU276 + 999 0038 1A69 ldr r2, [r3, #16] + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH->CR |= FLASH_CR_STRT; + 1000 .loc 1 521 13 view .LVU277 + 1001 003a 42EAC002 orr r2, r2, r0, lsl #3 + 1002 003e 42F00202 orr r2, r2, #2 + 1003 0042 1A61 str r2, [r3, #16] + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1004 .loc 1 522 3 is_stmt 1 view .LVU278 + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1005 .loc 1 522 8 is_stmt 0 view .LVU279 + 1006 0044 1A69 ldr r2, [r3, #16] + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1007 .loc 1 522 13 view .LVU280 + 1008 0046 42F48032 orr r2, r2, #65536 + 1009 004a 1A61 str r2, [r3, #16] + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 1010 .loc 1 526 3 is_stmt 1 view .LVU281 + 1011 .LBB8: + 1012 .LBI8: + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1013 .loc 2 877 27 view .LVU282 + 1014 .LBB9: + 1015 .loc 2 879 3 view .LVU283 + 1016 .syntax unified + 1017 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1018 004c BFF34F8F dsb 0xF + 1019 @ 0 "" 2 + 1020 .thumb + 1021 .syntax unified + 1022 .LBE9: + 1023 .LBE8: + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1024 .loc 1 527 1 is_stmt 0 view .LVU284 + 1025 0050 7047 bx lr + 1026 .L91: + 1027 0052 00BF .align 2 + 1028 .L90: + 1029 0054 003C0240 .word 1073888256 + 1030 .cfi_endproc + 1031 .LFE146: + ARM GAS /tmp/cc9TanaG.s page 56 + + + 1033 .section .text.HAL_FLASHEx_Erase,"ax",%progbits + 1034 .align 1 + 1035 .global HAL_FLASHEx_Erase + 1036 .syntax unified + 1037 .thumb + 1038 .thumb_func + 1040 HAL_FLASHEx_Erase: + 1041 .LVL81: + 1042 .LFB141: + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 1043 .loc 1 157 1 is_stmt 1 view -0 + 1044 .cfi_startproc + 1045 @ args = 0, pretend = 0, frame = 0 + 1046 @ frame_needed = 0, uses_anonymous_args = 0 + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** uint32_t index = 0; + 1047 .loc 1 158 3 view .LVU286 + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1048 .loc 1 159 3 view .LVU287 + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1049 .loc 1 162 3 view .LVU288 + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1050 .loc 1 162 3 view .LVU289 + 1051 0000 224B ldr r3, .L106 + 1052 0002 1B7D ldrb r3, [r3, #20] @ zero_extendqisi2 + 1053 0004 012B cmp r3, #1 + 1054 0006 3DD0 beq .L99 + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 1055 .loc 1 157 1 is_stmt 0 view .LVU290 + 1056 0008 70B5 push {r4, r5, r6, lr} + 1057 .LCFI11: + 1058 .cfi_def_cfa_offset 16 + 1059 .cfi_offset 4, -16 + 1060 .cfi_offset 5, -12 + 1061 .cfi_offset 6, -8 + 1062 .cfi_offset 14, -4 + 1063 000a 0446 mov r4, r0 + 1064 000c 0E46 mov r6, r1 + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1065 .loc 1 162 3 is_stmt 1 discriminator 2 view .LVU291 + 1066 000e 1F4B ldr r3, .L106 + 1067 0010 0122 movs r2, #1 + 1068 0012 1A75 strb r2, [r3, #20] + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1069 .loc 1 162 3 discriminator 2 view .LVU292 + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1070 .loc 1 165 3 view .LVU293 + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1071 .loc 1 168 3 view .LVU294 + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1072 .loc 1 168 12 is_stmt 0 view .LVU295 + 1073 0014 4CF25030 movw r0, #50000 + 1074 .LVL82: + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1075 .loc 1 168 12 view .LVU296 + 1076 0018 FFF7FEFF bl FLASH_WaitForLastOperation + 1077 .LVL83: + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + ARM GAS /tmp/cc9TanaG.s page 57 + + + 1078 .loc 1 170 3 is_stmt 1 view .LVU297 + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 1079 .loc 1 170 5 is_stmt 0 view .LVU298 + 1080 001c 0146 mov r1, r0 + 1081 001e 60BB cbnz r0, .L94 + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1082 .loc 1 173 5 is_stmt 1 view .LVU299 + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1083 .loc 1 173 18 is_stmt 0 view .LVU300 + 1084 0020 4FF0FF33 mov r3, #-1 + 1085 0024 3360 str r3, [r6] + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 1086 .loc 1 175 5 is_stmt 1 view .LVU301 + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 1087 .loc 1 175 18 is_stmt 0 view .LVU302 + 1088 0026 2368 ldr r3, [r4] + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 1089 .loc 1 175 7 view .LVU303 + 1090 0028 012B cmp r3, #1 + 1091 002a 16D0 beq .L104 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1092 .loc 1 193 7 is_stmt 1 view .LVU304 + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 1093 .loc 1 196 7 view .LVU305 + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 1094 .loc 1 196 17 is_stmt 0 view .LVU306 + 1095 002c A568 ldr r5, [r4, #8] + 1096 .LVL84: + 1097 .L96: + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 1098 .loc 1 196 45 is_stmt 1 discriminator 1 view .LVU307 + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 1099 .loc 1 196 58 is_stmt 0 discriminator 1 view .LVU308 + 1100 002e E368 ldr r3, [r4, #12] + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 1101 .loc 1 196 82 discriminator 1 view .LVU309 + 1102 0030 A268 ldr r2, [r4, #8] + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 1103 .loc 1 196 70 discriminator 1 view .LVU310 + 1104 0032 1344 add r3, r3, r2 + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 1105 .loc 1 196 45 discriminator 1 view .LVU311 + 1106 0034 AB42 cmp r3, r5 + 1107 0036 20D9 bls .L94 + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1108 .loc 1 198 9 is_stmt 1 view .LVU312 + 1109 0038 217C ldrb r1, [r4, #16] @ zero_extendqisi2 + 1110 .LVL85: + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1111 .loc 1 198 9 is_stmt 0 view .LVU313 + 1112 003a 2846 mov r0, r5 + 1113 003c FFF7FEFF bl FLASH_Erase_Sector + 1114 .LVL86: + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1115 .loc 1 201 9 is_stmt 1 view .LVU314 + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1116 .loc 1 201 18 is_stmt 0 view .LVU315 + ARM GAS /tmp/cc9TanaG.s page 58 + + + 1117 0040 4CF25030 movw r0, #50000 + 1118 0044 FFF7FEFF bl FLASH_WaitForLastOperation + 1119 .LVL87: + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1120 .loc 1 204 9 is_stmt 1 view .LVU316 + 1121 0048 114A ldr r2, .L106+4 + 1122 004a 1369 ldr r3, [r2, #16] + 1123 004c 23F0FA03 bic r3, r3, #250 + 1124 0050 1361 str r3, [r2, #16] + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 1125 .loc 1 206 9 view .LVU317 + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 1126 .loc 1 206 11 is_stmt 0 view .LVU318 + 1127 0052 0146 mov r1, r0 + 1128 0054 80B9 cbnz r0, .L105 + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 1129 .loc 1 196 98 is_stmt 1 discriminator 2 view .LVU319 + 1130 0056 0135 adds r5, r5, #1 + 1131 .LVL88: + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 1132 .loc 1 196 98 is_stmt 0 discriminator 2 view .LVU320 + 1133 0058 E9E7 b .L96 + 1134 .LVL89: + 1135 .L104: + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #else + 1136 .loc 1 179 7 is_stmt 1 view .LVU321 + 1137 005a 6168 ldr r1, [r4, #4] + 1138 005c 207C ldrb r0, [r4, #16] @ zero_extendqisi2 + 1139 .LVL90: + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #else + 1140 .loc 1 179 7 is_stmt 0 view .LVU322 + 1141 005e FFF7FEFF bl FLASH_MassErase + 1142 .LVL91: + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1143 .loc 1 185 7 is_stmt 1 view .LVU323 + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1144 .loc 1 185 16 is_stmt 0 view .LVU324 + 1145 0062 4CF25030 movw r0, #50000 + 1146 0066 FFF7FEFF bl FLASH_WaitForLastOperation + 1147 .LVL92: + 1148 006a 0146 mov r1, r0 + 1149 .LVL93: + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 1150 .loc 1 188 7 is_stmt 1 view .LVU325 + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 1151 .loc 1 188 12 is_stmt 0 view .LVU326 + 1152 006c 084A ldr r2, .L106+4 + 1153 006e 1069 ldr r0, [r2, #16] + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 1154 .loc 1 188 17 view .LVU327 + 1155 0070 084B ldr r3, .L106+8 + 1156 0072 0340 ands r3, r3, r0 + 1157 0074 1361 str r3, [r2, #16] + 1158 0076 00E0 b .L94 + 1159 .LVL94: + 1160 .L105: + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** break; + ARM GAS /tmp/cc9TanaG.s page 59 + + + 1161 .loc 1 209 11 is_stmt 1 view .LVU328 + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** break; + 1162 .loc 1 209 24 is_stmt 0 view .LVU329 + 1163 0078 3560 str r5, [r6] + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 1164 .loc 1 210 11 is_stmt 1 view .LVU330 + 1165 .LVL95: + 1166 .L94: + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1167 .loc 1 217 3 view .LVU331 + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1168 .loc 1 217 3 view .LVU332 + 1169 007a 044B ldr r3, .L106 + 1170 007c 0022 movs r2, #0 + 1171 007e 1A75 strb r2, [r3, #20] + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1172 .loc 1 217 3 view .LVU333 + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 1173 .loc 1 219 3 view .LVU334 + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1174 .loc 1 220 1 is_stmt 0 view .LVU335 + 1175 0080 0846 mov r0, r1 + 1176 0082 70BD pop {r4, r5, r6, pc} + 1177 .LVL96: + 1178 .L99: + 1179 .LCFI12: + 1180 .cfi_def_cfa_offset 0 + 1181 .cfi_restore 4 + 1182 .cfi_restore 5 + 1183 .cfi_restore 6 + 1184 .cfi_restore 14 + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1185 .loc 1 162 3 discriminator 1 view .LVU336 + 1186 0084 0221 movs r1, #2 + 1187 .LVL97: + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1188 .loc 1 220 1 view .LVU337 + 1189 0086 0846 mov r0, r1 + 1190 .LVL98: + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1191 .loc 1 220 1 view .LVU338 + 1192 0088 7047 bx lr + 1193 .L107: + 1194 008a 00BF .align 2 + 1195 .L106: + 1196 008c 00000000 .word pFlash + 1197 0090 003C0240 .word 1073888256 + 1198 0094 FB7FFFFF .word -32773 + 1199 .cfi_endproc + 1200 .LFE141: + 1202 .section .text.HAL_FLASHEx_Erase_IT,"ax",%progbits + 1203 .align 1 + 1204 .global HAL_FLASHEx_Erase_IT + 1205 .syntax unified + 1206 .thumb + 1207 .thumb_func + 1209 HAL_FLASHEx_Erase_IT: + ARM GAS /tmp/cc9TanaG.s page 60 + + + 1210 .LVL99: + 1211 .LFB142: + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1212 .loc 1 230 1 is_stmt 1 view -0 + 1213 .cfi_startproc + 1214 @ args = 0, pretend = 0, frame = 0 + 1215 @ frame_needed = 0, uses_anonymous_args = 0 + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1216 .loc 1 230 1 is_stmt 0 view .LVU340 + 1217 0000 08B5 push {r3, lr} + 1218 .LCFI13: + 1219 .cfi_def_cfa_offset 8 + 1220 .cfi_offset 3, -8 + 1221 .cfi_offset 14, -4 + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1222 .loc 1 231 3 is_stmt 1 view .LVU341 + 1223 .LVL100: + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1224 .loc 1 234 3 view .LVU342 + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1225 .loc 1 234 3 view .LVU343 + 1226 0002 174B ldr r3, .L114 + 1227 0004 1B7D ldrb r3, [r3, #20] @ zero_extendqisi2 + 1228 0006 012B cmp r3, #1 + 1229 0008 27D0 beq .L111 + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1230 .loc 1 234 3 discriminator 2 view .LVU344 + 1231 000a 154B ldr r3, .L114 + 1232 000c 0122 movs r2, #1 + 1233 000e 1A75 strb r2, [r3, #20] + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1234 .loc 1 234 3 discriminator 2 view .LVU345 + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1235 .loc 1 237 3 view .LVU346 + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1236 .loc 1 240 3 view .LVU347 + 1237 0010 144B ldr r3, .L114+4 + 1238 0012 1A69 ldr r2, [r3, #16] + 1239 0014 42F08072 orr r2, r2, #16777216 + 1240 0018 1A61 str r2, [r3, #16] + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1241 .loc 1 243 3 view .LVU348 + 1242 001a 1A69 ldr r2, [r3, #16] + 1243 001c 42F00072 orr r2, r2, #33554432 + 1244 0020 1A61 str r2, [r3, #16] + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); + 1245 .loc 1 246 3 view .LVU349 + 1246 0022 F322 movs r2, #243 + 1247 0024 DA60 str r2, [r3, #12] + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 1248 .loc 1 249 3 view .LVU350 + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 1249 .loc 1 249 16 is_stmt 0 view .LVU351 + 1250 0026 0368 ldr r3, [r0] + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** { + 1251 .loc 1 249 5 view .LVU352 + 1252 0028 012B cmp r3, #1 + ARM GAS /tmp/cc9TanaG.s page 61 + + + 1253 002a 0DD0 beq .L113 + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1254 .loc 1 264 5 is_stmt 1 view .LVU353 + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pFlash.NbSectorsToErase = pEraseInit->NbSectors; + 1255 .loc 1 266 5 view .LVU354 + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pFlash.NbSectorsToErase = pEraseInit->NbSectors; + 1256 .loc 1 266 29 is_stmt 0 view .LVU355 + 1257 002c 0C4B ldr r3, .L114 + 1258 002e 0122 movs r2, #1 + 1259 0030 1A70 strb r2, [r3] + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pFlash.Sector = pEraseInit->Sector; + 1260 .loc 1 267 5 is_stmt 1 view .LVU356 + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pFlash.Sector = pEraseInit->Sector; + 1261 .loc 1 267 41 is_stmt 0 view .LVU357 + 1262 0032 C268 ldr r2, [r0, #12] + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pFlash.Sector = pEraseInit->Sector; + 1263 .loc 1 267 29 view .LVU358 + 1264 0034 5A60 str r2, [r3, #4] + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange; + 1265 .loc 1 268 5 is_stmt 1 view .LVU359 + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange; + 1266 .loc 1 268 31 is_stmt 0 view .LVU360 + 1267 0036 8268 ldr r2, [r0, #8] + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange; + 1268 .loc 1 268 19 view .LVU361 + 1269 0038 DA60 str r2, [r3, #12] + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1270 .loc 1 269 5 is_stmt 1 view .LVU362 + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1271 .loc 1 269 30 is_stmt 0 view .LVU363 + 1272 003a 017C ldrb r1, [r0, #16] @ zero_extendqisi2 + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1273 .loc 1 269 28 view .LVU364 + 1274 003c 1972 strb r1, [r3, #8] + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 1275 .loc 1 272 5 is_stmt 1 view .LVU365 + 1276 003e 8068 ldr r0, [r0, #8] + 1277 .LVL101: + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 1278 .loc 1 272 5 is_stmt 0 view .LVU366 + 1279 0040 FFF7FEFF bl FLASH_Erase_Sector + 1280 .LVL102: + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 1281 .loc 1 275 10 view .LVU367 + 1282 0044 0020 movs r0, #0 + 1283 .L109: + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1284 .loc 1 276 1 view .LVU368 + 1285 0046 08BD pop {r3, pc} + 1286 .LVL103: + 1287 .L113: + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR_nDBANK) + 1288 .loc 1 252 5 is_stmt 1 view .LVU369 + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #if defined (FLASH_OPTCR_nDBANK) + 1289 .loc 1 252 29 is_stmt 0 view .LVU370 + 1290 0048 054B ldr r3, .L114 + 1291 004a 0222 movs r2, #2 + ARM GAS /tmp/cc9TanaG.s page 62 + + + 1292 004c 1A70 strb r2, [r3] + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #else + 1293 .loc 1 254 5 is_stmt 1 view .LVU371 + 1294 004e 4168 ldr r1, [r0, #4] + 1295 0050 007C ldrb r0, [r0, #16] @ zero_extendqisi2 + 1296 .LVL104: + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** #else + 1297 .loc 1 254 5 is_stmt 0 view .LVU372 + 1298 0052 FFF7FEFF bl FLASH_MassErase + 1299 .LVL105: + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** } + 1300 .loc 1 275 10 view .LVU373 + 1301 0056 0020 movs r0, #0 + 1302 0058 F5E7 b .L109 + 1303 .LVL106: + 1304 .L111: + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1305 .loc 1 234 3 discriminator 1 view .LVU374 + 1306 005a 0220 movs r0, #2 + 1307 .LVL107: + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c **** + 1308 .loc 1 234 3 discriminator 1 view .LVU375 + 1309 005c F3E7 b .L109 + 1310 .L115: + 1311 005e 00BF .align 2 + 1312 .L114: + 1313 0060 00000000 .word pFlash + 1314 0064 003C0240 .word 1073888256 + 1315 .cfi_endproc + 1316 .LFE142: + 1318 .text + 1319 .Letext0: + 1320 .file 3 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 1321 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 1322 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 1323 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h" + 1324 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h" + ARM GAS /tmp/cc9TanaG.s page 63 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_flash_ex.c + /tmp/cc9TanaG.s:20 .text.FLASH_MassErase:00000000 $t + /tmp/cc9TanaG.s:25 .text.FLASH_MassErase:00000000 FLASH_MassErase + /tmp/cc9TanaG.s:117 .text.FLASH_MassErase:0000004c $d + /tmp/cc9TanaG.s:122 .text.FLASH_OB_GetWRP:00000000 $t + /tmp/cc9TanaG.s:127 .text.FLASH_OB_GetWRP:00000000 FLASH_OB_GetWRP + /tmp/cc9TanaG.s:145 .text.FLASH_OB_GetWRP:0000000c $d + /tmp/cc9TanaG.s:151 .text.FLASH_OB_GetUser:00000000 $t + /tmp/cc9TanaG.s:156 .text.FLASH_OB_GetUser:00000000 FLASH_OB_GetUser + /tmp/cc9TanaG.s:174 .text.FLASH_OB_GetUser:0000000c $d + /tmp/cc9TanaG.s:180 .text.FLASH_OB_BOR_LevelConfig:00000000 $t + /tmp/cc9TanaG.s:185 .text.FLASH_OB_BOR_LevelConfig:00000000 FLASH_OB_BOR_LevelConfig + /tmp/cc9TanaG.s:209 .text.FLASH_OB_BOR_LevelConfig:00000010 $d + /tmp/cc9TanaG.s:214 .text.FLASH_OB_GetRDP:00000000 $t + /tmp/cc9TanaG.s:219 .text.FLASH_OB_GetRDP:00000000 FLASH_OB_GetRDP + /tmp/cc9TanaG.s:253 .text.FLASH_OB_GetRDP:00000018 $d + /tmp/cc9TanaG.s:258 .text.FLASH_OB_GetBOR:00000000 $t + /tmp/cc9TanaG.s:263 .text.FLASH_OB_GetBOR:00000000 FLASH_OB_GetBOR + /tmp/cc9TanaG.s:280 .text.FLASH_OB_GetBOR:0000000c $d + /tmp/cc9TanaG.s:285 .text.FLASH_OB_GetBootAddress:00000000 $t + /tmp/cc9TanaG.s:290 .text.FLASH_OB_GetBootAddress:00000000 FLASH_OB_GetBootAddress + /tmp/cc9TanaG.s:329 .text.FLASH_OB_GetBootAddress:00000014 $d + /tmp/cc9TanaG.s:334 .text.FLASH_OB_EnableWRP:00000000 $t + /tmp/cc9TanaG.s:339 .text.FLASH_OB_EnableWRP:00000000 FLASH_OB_EnableWRP + /tmp/cc9TanaG.s:382 .text.FLASH_OB_EnableWRP:0000001c $d + /tmp/cc9TanaG.s:387 .text.FLASH_OB_DisableWRP:00000000 $t + /tmp/cc9TanaG.s:392 .text.FLASH_OB_DisableWRP:00000000 FLASH_OB_DisableWRP + /tmp/cc9TanaG.s:435 .text.FLASH_OB_DisableWRP:00000018 $d + /tmp/cc9TanaG.s:440 .text.FLASH_OB_RDP_LevelConfig:00000000 $t + /tmp/cc9TanaG.s:445 .text.FLASH_OB_RDP_LevelConfig:00000000 FLASH_OB_RDP_LevelConfig + /tmp/cc9TanaG.s:485 .text.FLASH_OB_RDP_LevelConfig:00000014 $d + /tmp/cc9TanaG.s:490 .text.FLASH_OB_UserConfig:00000000 $t + /tmp/cc9TanaG.s:495 .text.FLASH_OB_UserConfig:00000000 FLASH_OB_UserConfig + /tmp/cc9TanaG.s:579 .text.FLASH_OB_UserConfig:00000040 $d + /tmp/cc9TanaG.s:585 .text.FLASH_OB_BootAddressConfig:00000000 $t + /tmp/cc9TanaG.s:590 .text.FLASH_OB_BootAddressConfig:00000000 FLASH_OB_BootAddressConfig + /tmp/cc9TanaG.s:646 .text.FLASH_OB_BootAddressConfig:00000030 $d + /tmp/cc9TanaG.s:651 .text.HAL_FLASHEx_OBProgram:00000000 $t + /tmp/cc9TanaG.s:657 .text.HAL_FLASHEx_OBProgram:00000000 HAL_FLASHEx_OBProgram + /tmp/cc9TanaG.s:856 .text.HAL_FLASHEx_OBProgram:000000c0 $d + /tmp/cc9TanaG.s:861 .text.HAL_FLASHEx_OBGetConfig:00000000 $t + /tmp/cc9TanaG.s:867 .text.HAL_FLASHEx_OBGetConfig:00000000 HAL_FLASHEx_OBGetConfig + /tmp/cc9TanaG.s:930 .text.FLASH_Erase_Sector:00000000 $t + /tmp/cc9TanaG.s:936 .text.FLASH_Erase_Sector:00000000 FLASH_Erase_Sector + /tmp/cc9TanaG.s:1029 .text.FLASH_Erase_Sector:00000054 $d + /tmp/cc9TanaG.s:1034 .text.HAL_FLASHEx_Erase:00000000 $t + /tmp/cc9TanaG.s:1040 .text.HAL_FLASHEx_Erase:00000000 HAL_FLASHEx_Erase + /tmp/cc9TanaG.s:1196 .text.HAL_FLASHEx_Erase:0000008c $d + /tmp/cc9TanaG.s:1203 .text.HAL_FLASHEx_Erase_IT:00000000 $t + /tmp/cc9TanaG.s:1209 .text.HAL_FLASHEx_Erase_IT:00000000 HAL_FLASHEx_Erase_IT + /tmp/cc9TanaG.s:1313 .text.HAL_FLASHEx_Erase_IT:00000060 $d + +UNDEFINED SYMBOLS +FLASH_WaitForLastOperation +pFlash diff --git a/build/stm32f7xx_hal_flash_ex.o b/build/stm32f7xx_hal_flash_ex.o new file mode 100644 index 0000000000000000000000000000000000000000..8899e7e770b94b8000691f04300b9fc9160e3fba GIT binary patch literal 20680 zcmchfdwf;ZnfKS;`<#=L%gH?uLV!a60VO91S3%H|gakssgoJ3kwBaNKbZWI7YxNb|I<*zXX~&s~t-ab#@wJvpoxT}C(fYo_{C;ac`<#6? zq3!$r@$L`%eAn}=XFcm#m%a8nJ7;rC!`4Q_FqCr`YKcloN`;$rj(?@b5>=zBmDO0d z*-TWNj*gl!Yia(ZxwK?5)RdK|oAQ}ivFt7RiReiy96i0SIzRTUQ!Sq!*<>`T#O8N= zrdgjA``rnXwx?BHR_r$?)Os^&HeZu4HR_bh?S2v~9l(nTjv0y64Dy?sg zsW7Zz>u>J7`Gu#xw8S?_zPvmo>JbbnSg&%W8XsB<#^ncJT9H7;v5 zD#|9T{-P-(FKe>C|A9Jda$i5&>N{>z9XG-YkZwnao>z z{3~>SZkQZFOu3EobbmVY#c165jh3miD^~1W&~IEcWAbnN-{}8*f6>Or>%u>szjsL^ zqjhWxwiIFh{@yBz8IAj%GgiHIBGzyBhGStg266QSo2_V3OdVgf)2Dko*f{dMIUk># z*E}%4KD_1Z+2AuXb!3YtOLR=dXkXpbzERzxDFvRY_}NYiafK#xXfg7g{;PN1+W)hi z#@<<@GWOx%^ZsTNdA0pYkBkbxi*Y!0B30KrnM#?uVxMt|U#XmLV1>BM)@Zf!VFojP z2({_UP!?bWpQdC4zDt)VuXg<0@%8ZA)4DirjsbYx%fCK&lvIdU+g z9p2b>rCr@Ru}X=h}yC;42JJtY&4** z>{<9w**KMv-HNoCU5B)#tal;!msxWGr^s?+08(}qt+Q9cm!Ygv2*JO~+MY5CM2tf; z>qU;r{&##B*(=z;*^eR(&ohC*3Trove6-9d53J2x0C%BB@DaFV-s4cBb3z6@1UAgG z`^pyzp>=`F=JlbtxgZ$&4vlLiHz)KXdaV~RKlB8A1RCZsU~@rn$YR+|l3S{*G8S$! zpJesL8I_s0vHGt<%BafG1BmKJ5p>215q-M8j5Q(#Lxs#;Ct^ljb3;D=K4?7^%=g+H4Wg7iwhgHW7oN7g<58h&iE)nAZayON=c16!3{S1|b^jT{*)AC=S_-86##s`$wQuzkbuj4FQNM*gLXa0vs zpP}*r*1pkJE`Y0fIPD&5H1)LG3`HHz8HMnbHqOO&LSvLn(_^K^c9bxFZ3N(5sZN}n zjhAO2G_HuqsbFZg!0KZ-3%M{sxtvqozo7uJ_Mo8C3HS2qf^=a2fj74<43La{37IM{u`FaM?1x35#dKo?Pqne5D8nQvN+F#);&w&XiMmc+o16j^Xi}SO5E)rat=3IaT z*RcW=#C2>$)eK%WR6#U@VWsB!xE#+jev40Ij!~3cOpd}Z0RP5|$q?ok4Gf_V+ADC{ z131sn19$?8f5Tb61m$>bm$PlW63YjW;1W@O5Q)dBc@zn*QFFe61XsAHQUM+jl@nmt zcnOxqo2kh9VQ~{W-I#$SK;2EWJEZ5- zI@ng@oWtdbGy5*G zvoV>B0%K8bQMQ#kJGUcHV6++esKH#Qva>IR5*v>h%F11reM$D(?4}~@JXR^fF9wJ| zP-J9h!@$2b+dxi6NLfK!Y%01Kd!8T^bbx$YktrUv0=p!iacOoo^6X0J1N(R@w;a2x z9Py3HsSk-O9SeQuu5<-=S@7Hk`L<}bw<`o!)Ml|ce zI&Fdr+R1AwG6T=np(Bc<0v)U9iX%z8G#|KwP2)Wv-e=r(tAW0*K`b-xzSU4>*8O#8 zL1{8vRIxZGEudL*R83KvailJr>dx$|{8yq+%G{Nt+0UNFms5Q?s#kXPbDT)nFLU!S z(j3uw>4l|loZ{hRF8V&%YA1KT^qd|S>7@$y&~PjlxD{fw(A||`y`9F)bPh}|Y?WIH zE?`;el=ZG!dZzk}Iz&0&&L+5;xw9ea16OYHKxgCYP4yv?#o?LYibyp{H&EkKA5LlB zbuE?or9({c%5>S#kaniJS#zbGW>9GdYeg}FCWhLPmJK1K)!PZ%qQkK;6lS8rwWtGi zv<_XKi=lJ6VGVl8F(KVSvYiN+9qTz@nU>ivglj%4`INl9=Jirfg5b?F8#_mxibh zHkSu&*j&dJUbWu!!EQ&?M5|6FJH%zAldKyKh~+q)dU>f)UTJ3&QJn5<%5^wVnqWQd zY>3H&k>kR^Y1cB{CCT+3Arq|FvnFx`>4D@tp$D?pPM4B>q9?yDdh)29#^?Eug~&qf z#DzM!gIH#335hAyC#~!gx<{nMH+8a=V1>FX3s5l=z(*NQfN>!K~szr z@kv`tu<-dRM3z2g;}dh7u$^2%++k~pq!Z6_>>BRmA6v>{&w(Q&+C?j|PA9jsw?1lX zIh?y~E%9fzmav1^POxTr1N339c8FFVbj)>vWJepSgP=RAQ*Jv_zEU^tgW3!q`nFEm z*Em_s4;)^yRXp--=&b^iVUeBuQjytS9-PKJj@r;Ooyks-4+#5(4q7GQjl+?h`u=~! zvjktUEY*&_H;oT-LwGEx2OYApaWrvbd~~d;eaE&H%Ny71-rcpic59cdt!f|bQI0|V zw)Up>s-~fyfr;L@s+t%Ztr|#lSMBQQsfvvbRt^mh#Vg~n?nG71ipcUvO;tiH)5~v+ z-` zFzv;Yd89G#q}XZ{gu<6ph@akgAJq5;KaKnIX0TpeNZ|>WUtdnv5epAG@Tatjq7r{F zV1)glFr*EBKeWNX3V#;p53DA`{ygSgN;`ijg5)(m(?8q#oCOEPKErPWtY7Voz}y-M zCkyxkA92!V0Hc_y`Y%z$D)!HYH>1i7rsci$2l8&uV7Zb&XP^RA7Ms4blE;`^RIGyx ztOu6+L#QD;;?G}+kQbmxk*CP(+MyFjdXVpHcO|+%tiVctF?_9I+qEOMb$3`RLy<5Z zOu5_lg@E0)RV5|}g5UcS3f9;K&9oZdI$yyG|5DUw1*R?a zZJ!si{{Y`+wTT% z`z!nz2o$4n9g9J*ZVH>3X=NWWIf^BmQ;mKLf4VXQQGTw6uUv%U4+kzS^5-Fy5ytGy z$Lx&2(QHYTST}I0TC>7p4WTZTv}UYN2`;@WX%(+G))(veFvj%}+M^18V6pDX+;Fgy zgI}U6&>0udBtjD>#kdVC8ulC34^`MR>GsKmSLL6nhi19I6r8~#_Vl8EN5~7T9}1Pbw1Koe^`oLiYqP4!bN9C zawS`0g!P)r+h0RlTT7c_s^jvlE%nU}8&%`h+V;&|t)s&|@!pBi_>Mgz@s065QMc4} zZA^^Cx(DJ{wzcYVJDRpNv~=u9=A+=Q(b!>1MSwtCo@R#PATqR&_0H zTjMvz2h;@Wytr#zjSr4=jf^G!EUpl;?N1l0>uA49wU769@6n=eTf^?ImO3;}ytlOO zXl}TwP1Ow#k2BcnWU59@Ac$dI?TxX4iMZWXHgoH6&-IF-G>pc^;>oSbv>OQQWvZsR z!Q1->4t4u@YY4&$Njn`hi_1Kz>K`7ASM|kvV^!OlT6a{n#d;IN zt^LE}!$XOluJ(y;w52cB6Ym<0^~Of4HpPeHqcQY*S8IKp#~7NfvEjb)n_{EV=HB56 z%rTXmg)Kvyh7&`()WpzOV%Jc-H{8=78#kZYxWh^n?I6S&FHimABVq%dRG8HA=R_nd^G`;!<*Cy#~|| zW1BCl4yv%j8foO7JJn*01v*>d;;nD1QJXIB2-nxF3ESTQ!pp0duc)c6UK_3)>=~KZ z(1WEdzPoa84dn6uiNS8L5Bk258&_5K)~u#DFdQ4N#FvN-n8&?P#72AiH{k2VjcekS zgBSIUM0!WUmAmk-7Z*ieUpnH*Jj6ruzDI z;UzVz*6FB6;{!F7%a?kaU_aP7iv#zhy}3Cd{h-JFRWHX8Kz_yhzmfS>&~4AJgl?H% zNu95aNUAW-+T7r6=DkLmo_?m&v%I5szIH;TABfcEmhKPS=D*!{hjl0Y(bhRuB2k;0 zzu$M8bvyGGIvL|7>SLofb@`;dBx4TW9(1&q4#{nc7a`SKV z-EQ51x^9N6WB&+eZeRS04PW~iOKlB=7{72TV=`Ve1OU5AAy(COs^DvEs8Z1q`d8vKk^Q-REej2iMD?sX;YF+F=45h z9{ZV|{8^s-S=!%@q}8lsiV6IV#baNl?e9rirH_tAk!5^lxa%;@;grGQ;(~C#iG3nqcer$2Vcq?=5Bjl%9z;ruoxb zEoZCfHnsO)=V-XI)4$Qo+IB8;F?Q5*wIg{C&%)GOMq-L`Y_l-cIObVZ_TOf*aA|*u z@(TN}GUN-8%@*;GrBD0CCCl|R3ri8Nr7Zj%qJo@f|DA~B+RJ*^llWWUMv?iage=@b z`b6e+O8-&Hu;X83n7%x~r&tFB;|Br>g5dBHAMycNk-;wjpTfM2N7;18}JiM z68YUC_X)2T{Y@f&Ot_DPpU+7CAu^=YBf=*{{~TGV)bqk`lMVREFNykoEb?o@^mC z;rE0;5dM~IviC2%ujqXQSj77_$ZsFyVj*|ml(|hHzX^XJbdY$4y9p}bgFC0rroD>TgKixuP!VW+T5*dyd?F}#oL7v3$@ z`y=T2h79w+EPPscMEFm_mxVtN{#bZI_*>yS!uN!H*@pgS2833M0bR!gWHvyFh=9LcWGWS?_be8$_NE?iKD6-YNWZ z;b(-O73%#C{5&l37llsU|LE(fc5%upMZwse{eA9^c;~ZhJuv8cpE)?=5B-%%Xn}p56HsKY*j|gKzzOcmd zdjA97Bl3Mhy$^!^b0U9U_yr+fZescG3x6j3cj24Dw}ex|)4~shXN7@G+h3NjKv*Iy z7lws=k&5+SDr^*P5pEZD2tOi>3HyZuLQGF(*2^<B-+_4>?cvlfN+FFyT^sQNwj~ja32}9e;G@5 z8<5c-zaY{64@k7Tg!g^4dj*O1>iq}WcPnMI?|BmKd5=VU`1&i`5tsYw^CaT_fJD5n zp~D$x2kK&cFO!H%uYZU`_xBd*Z{+Fzg{=D*aq0eq3>P{+-G7jE{~=D@UywVQk9c+e zK-T?(xOIO(*8PF_Z=)ULPm*ZIL6HxWXwTCkA0g4Mmqnf=F+OjLJVm0NLG~N`<&bD^ zwaEMr9N6y7B5x(p{!WpvB{@DK?<1pd8X4O&I3DW;$471UJ1P9xdR#^LM`ji2#_t9q zR7C9O!l?(|Zf)v!JLhWklW&jO`~2IJElRG+Nga@d*B+?XgHb8=ofA^*g3% za=p*Xr!jFoIiDu?+-K-1Blm;tmOAI>80X7RJvDbXFYVd+^hNEb=zk!O&(n2wZ@hbA zS65=FZy2Mm)3NUE(fEz-+=1a9w-_7c5412v*zIj%vd*VEH_j>GJfLxB# zIh=YQg~DC$&mreKMxbN&b&nm_snTieSl;c=2O&I--A|yy@~fhfcQMyGq$4=-XBS;B zv8MgBhay9``qI;>8iI(?AXtzJ^sE4fBn<=oAUT$V>w^g4$ecT9Yu&6rpaR= zGTvh#ayWT;uye;(3V)js5dHBl?~cED9)D%I_OlqTKR)+yd^7JcT)cayskhQo?@sI$ zj!V7sUG+vi{uZIr4%4w5PF?Fg{-X8vUYPAzfYWJ5yT{)#_`A<>20H#)JpLx(FCUro zhiy~RU)TmssDw2qH{2h=U$K9 z$P(L+*N*>jj1vR%4#4g{mxA^3;NKVB^Ps;W)m}c6b>jOh>@YP)bRm2!xiI~Db6k@! uO&-_6j?Y}GpxK6#{xCIko$!}D4#MDbjuU8|WC7A{yWNdSeZf_MWB1>;j8VA& literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_hal_gpio.d b/build/stm32f7xx_hal_gpio.d new file mode 100644 index 0000000..c6376b7 --- /dev/null +++ b/build/stm32f7xx_hal_gpio.d @@ -0,0 +1,68 @@ +build/stm32f7xx_hal_gpio.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/build/stm32f7xx_hal_gpio.lst b/build/stm32f7xx_hal_gpio.lst new file mode 100644 index 0000000..041ee9a --- /dev/null +++ b/build/stm32f7xx_hal_gpio.lst @@ -0,0 +1,1814 @@ +ARM GAS /tmp/ccXhcUUd.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_hal_gpio.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c" + 19 .section .text.HAL_GPIO_Init,"ax",%progbits + 20 .align 1 + 21 .global HAL_GPIO_Init + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 HAL_GPIO_Init: + 27 .LVL0: + 28 .LFB141: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @file stm32f7xx_hal_gpio.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @brief GPIO HAL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * functionalities of the General Purpose Input/Output (GPIO) peripheral: + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * + IO operation functions + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** ****************************************************************************** + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @attention + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * Copyright (c) 2017 STMicroelectronics. + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * All rights reserved. + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * This software is licensed under terms that can be found in the LICENSE file + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * in the root directory of this software component. + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** ****************************************************************************** + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** @verbatim + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** ============================================================================== + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** ##### GPIO Peripheral features ##### + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** ============================================================================== + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** [..] + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** in several modes: + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (+) Input mode + ARM GAS /tmp/ccXhcUUd.s page 2 + + + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (+) Analog mode + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (+) Output mode + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (+) Alternate function mode + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (+) External interrupt/event lines + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** [..] + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** During and just after reset, the alternate functions and external interrupt + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** lines are not active and the I/O ports are configured in input floating mode. + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** [..] + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** All GPIO pins have weak internal pull-up and pull-down resistors, which can be + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** activated or not. + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** [..] + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** In Output or Alternate mode, each IO can be configured on open-drain or push-pull + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** type and the IO speed can be selected depending on the VDD value. + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** [..] + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** All ports have external interrupt/event capability. To use external interrupt + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** lines, the port must be configured in input mode. All available GPIO pins are + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** [..] + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** The external interrupt/event controller consists of up to 23 edge detectors + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (16 lines are connected to GPIO) for generating event/interrupt requests (each + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** input line can be independently configured to select the type (interrupt or event) + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** and the corresponding trigger event (rising or falling or both). Each line can + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** also be masked independently. + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** ##### How to use this driver ##### + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** ============================================================================== + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** [..] + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** structure. + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (++) In case of Output or alternate function mode selection: the speed is + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** configured through "Speed" member from GPIO_InitTypeDef structure. + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (++) In alternate mode is selection, the alternate function connected to the IO + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** is configured through "Alternate" member from GPIO_InitTypeDef structure. + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (++) Analog mode is required when a pin is to be used as ADC channel + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** or DAC output. + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (++) In case of external interrupt/event selection the "Mode" member from + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIO_InitTypeDef structure select the type (interrupt or event) and + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** the corresponding trigger event (rising or falling or both). + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** HAL_NVIC_EnableIRQ(). + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (#) To set/reset the level of a pin configured in output mode use + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + ARM GAS /tmp/ccXhcUUd.s page 3 + + + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (#) During and just after reset, the alternate functions are not + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** active and the GPIO pins are configured in input floating mode (except JTAG + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** pins). + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** priority over the GPIO function. + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** The HSE has priority over the GPIO function. + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** @endverbatim + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** ****************************************************************************** + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** */ + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Includes ------------------------------------------------------------------*/ + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** #include "stm32f7xx_hal.h" + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** @addtogroup STM32F7xx_HAL_Driver + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @{ + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** */ + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** @defgroup GPIO GPIO + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @brief GPIO HAL module driver + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @{ + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** */ + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** #ifdef HAL_GPIO_MODULE_ENABLED + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Private typedef -----------------------------------------------------------*/ + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Private define ------------------------------------------------------------*/ + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** @addtogroup GPIO_Private_Constants GPIO Private Constants + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @{ + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** */ + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** #define GPIO_NUMBER ((uint32_t)16U) + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @} + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** */ + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Private macro -------------------------------------------------------------*/ + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Private variables ---------------------------------------------------------*/ + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Private function prototypes -----------------------------------------------*/ + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Private functions ---------------------------------------------------------*/ + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Exported functions --------------------------------------------------------*/ + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** @defgroup GPIO_Exported_Functions GPIO Exported Functions + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @{ + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** */ + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @brief Initialization and Configuration functions + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** @verbatim + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** =============================================================================== + ARM GAS /tmp/ccXhcUUd.s page 4 + + + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** ##### Initialization and de-initialization functions ##### + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** =============================================================================== + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** [..] + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** This section provides functions allowing to initialize and de-initialize the GPIOs + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** to be ready for use. + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** @endverbatim + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @{ + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** */ + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * the configuration information for the specified GPIO peripheral. + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @retval None + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** */ + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 29 .loc 1 163 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 8 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** uint32_t position = 0x00; + 33 .loc 1 164 3 view .LVU1 + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** uint32_t ioposition = 0x00; + 34 .loc 1 165 3 view .LVU2 + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** uint32_t iocurrent = 0x00; + 35 .loc 1 166 3 view .LVU3 + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** uint32_t temp = 0x00; + 36 .loc 1 167 3 view .LVU4 + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Check the parameters */ + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + 37 .loc 1 170 3 view .LVU5 + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + 38 .loc 1 171 3 view .LVU6 + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + 39 .loc 1 172 3 view .LVU7 + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Configure the port pins */ + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** for (position = 0; position < GPIO_NUMBER; position++) + 40 .loc 1 175 3 view .LVU8 + 41 .loc 1 175 17 is_stmt 0 view .LVU9 + 42 0000 0023 movs r3, #0 + 43 .LVL1: + 44 .loc 1 175 31 is_stmt 1 discriminator 1 view .LVU10 + 45 0002 0F2B cmp r3, #15 + 46 0004 00F2F480 bhi .L26 + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** uint32_t position = 0x00; + 47 .loc 1 163 1 is_stmt 0 view .LVU11 + 48 0008 70B5 push {r4, r5, r6, lr} + 49 .LCFI0: + 50 .cfi_def_cfa_offset 16 + 51 .cfi_offset 4, -16 + 52 .cfi_offset 5, -12 + 53 .cfi_offset 6, -8 + ARM GAS /tmp/ccXhcUUd.s page 5 + + + 54 .cfi_offset 14, -4 + 55 000a 82B0 sub sp, sp, #8 + 56 .LCFI1: + 57 .cfi_def_cfa_offset 24 + 58 000c 66E0 b .L12 + 59 .LVL2: + 60 .L28: + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Get the IO position */ + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** ioposition = ((uint32_t)0x01) << position; + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Get the current IO position */ + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if (iocurrent == ioposition) + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /*--------------------- GPIO Mode Configuration ------------------------*/ + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* In case of Output or Alternate function mode selection */ + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_ + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Check the Speed parameter */ + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + 61 .loc 1 189 9 is_stmt 1 view .LVU12 + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Configure the IO Speed */ + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp = GPIOx->OSPEEDR; + 62 .loc 1 191 9 view .LVU13 + 63 .loc 1 191 14 is_stmt 0 view .LVU14 + 64 000e 8568 ldr r5, [r0, #8] + 65 .LVL3: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + 66 .loc 1 192 9 is_stmt 1 view .LVU15 + 67 .loc 1 192 55 is_stmt 0 view .LVU16 + 68 0010 4FEA430E lsl lr, r3, #1 + 69 .loc 1 192 42 view .LVU17 + 70 0014 0324 movs r4, #3 + 71 0016 04FA0EF4 lsl r4, r4, lr + 72 .loc 1 192 14 view .LVU18 + 73 001a 25EA0405 bic r5, r5, r4 + 74 .LVL4: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= (GPIO_Init->Speed << (position * 2)); + 75 .loc 1 193 9 is_stmt 1 view .LVU19 + 76 .loc 1 193 27 is_stmt 0 view .LVU20 + 77 001e CC68 ldr r4, [r1, #12] + 78 .loc 1 193 35 view .LVU21 + 79 0020 04FA0EF4 lsl r4, r4, lr + 80 .loc 1 193 14 view .LVU22 + 81 0024 2C43 orrs r4, r4, r5 + 82 .LVL5: + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->OSPEEDR = temp; + 83 .loc 1 194 9 is_stmt 1 view .LVU23 + 84 .loc 1 194 24 is_stmt 0 view .LVU24 + 85 0026 8460 str r4, [r0, #8] + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Configure the IO Output Type */ + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp = GPIOx->OTYPER; + 86 .loc 1 197 9 is_stmt 1 view .LVU25 + 87 .loc 1 197 14 is_stmt 0 view .LVU26 + 88 0028 4468 ldr r4, [r0, #4] + ARM GAS /tmp/ccXhcUUd.s page 6 + + + 89 .LVL6: + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp &= ~(GPIO_OTYPER_OT_0 << position) ; + 90 .loc 1 198 9 is_stmt 1 view .LVU27 + 91 .loc 1 198 14 is_stmt 0 view .LVU28 + 92 002a 24EA0204 bic r4, r4, r2 + 93 .LVL7: + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 94 .loc 1 199 9 is_stmt 1 view .LVU29 + 95 .loc 1 199 29 is_stmt 0 view .LVU30 + 96 002e 4A68 ldr r2, [r1, #4] + 97 .LVL8: + 98 .loc 1 199 51 view .LVU31 + 99 0030 C2F30012 ubfx r2, r2, #4, #1 + 100 .loc 1 199 71 view .LVU32 + 101 0034 9A40 lsls r2, r2, r3 + 102 .loc 1 199 14 view .LVU33 + 103 0036 2243 orrs r2, r2, r4 + 104 .LVL9: + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->OTYPER = temp; + 105 .loc 1 200 9 is_stmt 1 view .LVU34 + 106 .loc 1 200 23 is_stmt 0 view .LVU35 + 107 0038 4260 str r2, [r0, #4] + 108 003a 5DE0 b .L4 + 109 .LVL10: + 110 .L29: + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Check the Pull parameter */ + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Activate the Pull-up or Pull down resistor for the current IO */ + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp = GPIOx->PUPDR; + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2)); + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* In case of Alternate function mode selection */ + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Check the Alternate function parameter */ + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + 111 .loc 1 219 9 is_stmt 1 view .LVU36 + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Configure Alternate function mapped with the current IO */ + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp = GPIOx->AFR[position >> 3]; + 112 .loc 1 222 9 view .LVU37 + 113 .loc 1 222 36 is_stmt 0 view .LVU38 + 114 003c DC08 lsrs r4, r3, #3 + 115 .loc 1 222 14 view .LVU39 + 116 003e 0834 adds r4, r4, #8 + 117 0040 50F82420 ldr r2, [r0, r4, lsl #2] + 118 .LVL11: + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + 119 .loc 1 223 9 is_stmt 1 view .LVU40 + ARM GAS /tmp/ccXhcUUd.s page 7 + + + 120 .loc 1 223 37 is_stmt 0 view .LVU41 + 121 0044 03F00705 and r5, r3, #7 + 122 .loc 1 223 75 view .LVU42 + 123 0048 AD00 lsls r5, r5, #2 + 124 .loc 1 223 33 view .LVU43 + 125 004a 4FF00F0E mov lr, #15 + 126 004e 0EFA05FE lsl lr, lr, r5 + 127 .loc 1 223 14 view .LVU44 + 128 0052 22EA0E0E bic lr, r2, lr + 129 .LVL12: + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); + 130 .loc 1 224 9 is_stmt 1 view .LVU45 + 131 .loc 1 224 38 is_stmt 0 view .LVU46 + 132 0056 0A69 ldr r2, [r1, #16] + 133 .loc 1 224 51 view .LVU47 + 134 0058 AA40 lsls r2, r2, r5 + 135 .loc 1 224 14 view .LVU48 + 136 005a 42EA0E02 orr r2, r2, lr + 137 .LVL13: + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->AFR[position >> 3] = temp; + 138 .loc 1 225 9 is_stmt 1 view .LVU49 + 139 .loc 1 225 35 is_stmt 0 view .LVU50 + 140 005e 40F82420 str r2, [r0, r4, lsl #2] + 141 0062 5DE0 b .L6 + 142 .LVL14: + 143 .L30: + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp = GPIOx->MODER; + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp &= ~(GPIO_MODER_MODER0 << (position * 2)); + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->MODER = temp; + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /*--------------------- EXTI Mode Configuration ------------------------*/ + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Configure the External Interrupt or event for the current IO */ + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Enable SYSCFG Clock */ + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp = SYSCFG->EXTICR[position >> 2]; + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 144 .loc 1 243 29 discriminator 19 view .LVU51 + 145 0064 0922 movs r2, #9 + 146 0066 00E0 b .L7 + 147 .L13: + 148 .loc 1 243 18 discriminator 2 view .LVU52 + 149 0068 0022 movs r2, #0 + 150 .L7: + 151 .loc 1 243 52 discriminator 40 view .LVU53 + 152 006a 02FA0EF2 lsl r2, r2, lr + 153 .loc 1 243 14 discriminator 40 view .LVU54 + 154 006e 2A43 orrs r2, r2, r5 + 155 .LVL15: + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + ARM GAS /tmp/ccXhcUUd.s page 8 + + + 156 .loc 1 244 9 is_stmt 1 view .LVU55 + 157 .loc 1 244 39 is_stmt 0 view .LVU56 + 158 0070 0234 adds r4, r4, #2 + 159 0072 604D ldr r5, .L31 + 160 0074 45F82420 str r2, [r5, r4, lsl #2] + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Clear Rising Falling edge configuration */ + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp = EXTI->RTSR; + 161 .loc 1 247 9 is_stmt 1 view .LVU57 + 162 .loc 1 247 14 is_stmt 0 view .LVU58 + 163 0078 5F4A ldr r2, .L31+4 + 164 .LVL16: + 165 .loc 1 247 14 view .LVU59 + 166 007a 9468 ldr r4, [r2, #8] + 167 .LVL17: + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp &= ~((uint32_t)iocurrent); + 168 .loc 1 248 9 is_stmt 1 view .LVU60 + 169 .loc 1 248 17 is_stmt 0 view .LVU61 + 170 007c 6FEA0C02 mvn r2, ip + 171 .loc 1 248 14 view .LVU62 + 172 0080 24EA0C05 bic r5, r4, ip + 173 .LVL18: + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + 174 .loc 1 249 9 is_stmt 1 view .LVU63 + 175 .loc 1 249 12 is_stmt 0 view .LVU64 + 176 0084 4E68 ldr r6, [r1, #4] + 177 0086 16F4801F tst r6, #1048576 + 178 008a 01D0 beq .L8 + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= iocurrent; + 179 .loc 1 251 11 is_stmt 1 view .LVU65 + 180 .loc 1 251 16 is_stmt 0 view .LVU66 + 181 008c 4CEA0405 orr r5, ip, r4 + 182 .LVL19: + 183 .L8: + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** EXTI->RTSR = temp; + 184 .loc 1 253 9 is_stmt 1 view .LVU67 + 185 .loc 1 253 20 is_stmt 0 view .LVU68 + 186 0090 594C ldr r4, .L31+4 + 187 0092 A560 str r5, [r4, #8] + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp = EXTI->FTSR; + 188 .loc 1 255 9 is_stmt 1 view .LVU69 + 189 .loc 1 255 14 is_stmt 0 view .LVU70 + 190 0094 E468 ldr r4, [r4, #12] + 191 .LVL20: + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp &= ~((uint32_t)iocurrent); + 192 .loc 1 256 9 is_stmt 1 view .LVU71 + 193 .loc 1 256 14 is_stmt 0 view .LVU72 + 194 0096 02EA0405 and r5, r2, r4 + 195 .LVL21: + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + 196 .loc 1 257 9 is_stmt 1 view .LVU73 + 197 .loc 1 257 12 is_stmt 0 view .LVU74 + 198 009a 4E68 ldr r6, [r1, #4] + 199 009c 16F4001F tst r6, #2097152 + ARM GAS /tmp/ccXhcUUd.s page 9 + + + 200 00a0 01D0 beq .L9 + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= iocurrent; + 201 .loc 1 259 11 is_stmt 1 view .LVU75 + 202 .loc 1 259 16 is_stmt 0 view .LVU76 + 203 00a2 4CEA0405 orr r5, ip, r4 + 204 .LVL22: + 205 .L9: + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** EXTI->FTSR = temp; + 206 .loc 1 261 9 is_stmt 1 view .LVU77 + 207 .loc 1 261 20 is_stmt 0 view .LVU78 + 208 00a6 544C ldr r4, .L31+4 + 209 00a8 E560 str r5, [r4, #12] + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp = EXTI->EMR; + 210 .loc 1 263 9 is_stmt 1 view .LVU79 + 211 .loc 1 263 14 is_stmt 0 view .LVU80 + 212 00aa 6468 ldr r4, [r4, #4] + 213 .LVL23: + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp &= ~((uint32_t)iocurrent); + 214 .loc 1 264 9 is_stmt 1 view .LVU81 + 215 .loc 1 264 14 is_stmt 0 view .LVU82 + 216 00ac 02EA0405 and r5, r2, r4 + 217 .LVL24: + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + 218 .loc 1 265 9 is_stmt 1 view .LVU83 + 219 .loc 1 265 12 is_stmt 0 view .LVU84 + 220 00b0 4E68 ldr r6, [r1, #4] + 221 00b2 16F4003F tst r6, #131072 + 222 00b6 01D0 beq .L10 + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= iocurrent; + 223 .loc 1 267 11 is_stmt 1 view .LVU85 + 224 .loc 1 267 16 is_stmt 0 view .LVU86 + 225 00b8 4CEA0405 orr r5, ip, r4 + 226 .LVL25: + 227 .L10: + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** EXTI->EMR = temp; + 228 .loc 1 269 9 is_stmt 1 view .LVU87 + 229 .loc 1 269 19 is_stmt 0 view .LVU88 + 230 00bc 4E4C ldr r4, .L31+4 + 231 00be 6560 str r5, [r4, #4] + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Clear EXTI line configuration */ + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp = EXTI->IMR; + 232 .loc 1 272 9 is_stmt 1 view .LVU89 + 233 .loc 1 272 14 is_stmt 0 view .LVU90 + 234 00c0 2468 ldr r4, [r4] + 235 .LVL26: + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp &= ~((uint32_t)iocurrent); + 236 .loc 1 273 9 is_stmt 1 view .LVU91 + 237 .loc 1 273 14 is_stmt 0 view .LVU92 + 238 00c2 2240 ands r2, r2, r4 + 239 .LVL27: + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) + ARM GAS /tmp/ccXhcUUd.s page 10 + + + 240 .loc 1 274 9 is_stmt 1 view .LVU93 + 241 .loc 1 274 23 is_stmt 0 view .LVU94 + 242 00c4 4D68 ldr r5, [r1, #4] + 243 .loc 1 274 12 view .LVU95 + 244 00c6 15F4803F tst r5, #65536 + 245 00ca 01D0 beq .L11 + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= iocurrent; + 246 .loc 1 276 11 is_stmt 1 view .LVU96 + 247 .loc 1 276 16 is_stmt 0 view .LVU97 + 248 00cc 4CEA0402 orr r2, ip, r4 + 249 .LVL28: + 250 .L11: + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** EXTI->IMR = temp; + 251 .loc 1 278 9 is_stmt 1 view .LVU98 + 252 .loc 1 278 19 is_stmt 0 view .LVU99 + 253 00d0 494C ldr r4, .L31+4 + 254 00d2 2260 str r2, [r4] + 255 .LVL29: + 256 .L3: + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 257 .loc 1 175 54 is_stmt 1 discriminator 2 view .LVU100 + 258 00d4 0133 adds r3, r3, #1 + 259 .LVL30: + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 260 .loc 1 175 31 discriminator 1 view .LVU101 + 261 00d6 0F2B cmp r3, #15 + 262 00d8 00F28880 bhi .L27 + 263 .LVL31: + 264 .L12: + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Get the current IO position */ + 265 .loc 1 178 5 view .LVU102 + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Get the current IO position */ + 266 .loc 1 178 16 is_stmt 0 view .LVU103 + 267 00dc 0122 movs r2, #1 + 268 00de 9A40 lsls r2, r2, r3 + 269 .LVL32: + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 270 .loc 1 180 5 is_stmt 1 view .LVU104 + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 271 .loc 1 180 37 is_stmt 0 view .LVU105 + 272 00e0 0C68 ldr r4, [r1] + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 273 .loc 1 180 15 view .LVU106 + 274 00e2 04EA020C and ip, r4, r2 + 275 .LVL33: + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 276 .loc 1 182 5 is_stmt 1 view .LVU107 + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 277 .loc 1 182 8 is_stmt 0 view .LVU108 + 278 00e6 32EA0404 bics r4, r2, r4 + 279 00ea F3D1 bne .L3 + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 280 .loc 1 186 7 is_stmt 1 view .LVU109 + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 281 .loc 1 186 22 is_stmt 0 view .LVU110 + ARM GAS /tmp/ccXhcUUd.s page 11 + + + 282 00ec 4C68 ldr r4, [r1, #4] + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 283 .loc 1 186 29 view .LVU111 + 284 00ee 04F00304 and r4, r4, #3 + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 285 .loc 1 186 58 view .LVU112 + 286 00f2 013C subs r4, r4, #1 + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 287 .loc 1 186 10 view .LVU113 + 288 00f4 012C cmp r4, #1 + 289 00f6 8AD9 bls .L28 + 290 .LVL34: + 291 .L4: + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 292 .loc 1 203 7 is_stmt 1 view .LVU114 + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 293 .loc 1 203 21 is_stmt 0 view .LVU115 + 294 00f8 4A68 ldr r2, [r1, #4] + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 295 .loc 1 203 28 view .LVU116 + 296 00fa 02F00302 and r2, r2, #3 + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 297 .loc 1 203 10 view .LVU117 + 298 00fe 032A cmp r2, #3 + 299 0100 09D0 beq .L5 + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 300 .loc 1 206 9 is_stmt 1 view .LVU118 + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + 301 .loc 1 209 9 view .LVU119 + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + 302 .loc 1 209 14 is_stmt 0 view .LVU120 + 303 0102 C468 ldr r4, [r0, #12] + 304 .LVL35: + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2)); + 305 .loc 1 210 9 is_stmt 1 view .LVU121 + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2)); + 306 .loc 1 210 50 is_stmt 0 view .LVU122 + 307 0104 5D00 lsls r5, r3, #1 + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2)); + 308 .loc 1 210 37 view .LVU123 + 309 0106 0322 movs r2, #3 + 310 0108 AA40 lsls r2, r2, r5 + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2)); + 311 .loc 1 210 14 view .LVU124 + 312 010a 24EA0204 bic r4, r4, r2 + 313 .LVL36: + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 314 .loc 1 211 9 is_stmt 1 view .LVU125 + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 315 .loc 1 211 28 is_stmt 0 view .LVU126 + 316 010e 8A68 ldr r2, [r1, #8] + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 317 .loc 1 211 36 view .LVU127 + 318 0110 AA40 lsls r2, r2, r5 + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 319 .loc 1 211 14 view .LVU128 + 320 0112 2243 orrs r2, r2, r4 + ARM GAS /tmp/ccXhcUUd.s page 12 + + + 321 .LVL37: + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 322 .loc 1 212 9 is_stmt 1 view .LVU129 + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 323 .loc 1 212 22 is_stmt 0 view .LVU130 + 324 0114 C260 str r2, [r0, #12] + 325 .LVL38: + 326 .L5: + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 327 .loc 1 216 7 is_stmt 1 view .LVU131 + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 328 .loc 1 216 21 is_stmt 0 view .LVU132 + 329 0116 4A68 ldr r2, [r1, #4] + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 330 .loc 1 216 28 view .LVU133 + 331 0118 02F00302 and r2, r2, #3 + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 332 .loc 1 216 10 view .LVU134 + 333 011c 022A cmp r2, #2 + 334 011e 8DD0 beq .L29 + 335 .L6: + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp &= ~(GPIO_MODER_MODER0 << (position * 2)); + 336 .loc 1 229 7 is_stmt 1 view .LVU135 + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp &= ~(GPIO_MODER_MODER0 << (position * 2)); + 337 .loc 1 229 12 is_stmt 0 view .LVU136 + 338 0120 0468 ldr r4, [r0] + 339 .LVL39: + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + 340 .loc 1 230 7 is_stmt 1 view .LVU137 + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + 341 .loc 1 230 48 is_stmt 0 view .LVU138 + 342 0122 4FEA430E lsl lr, r3, #1 + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + 343 .loc 1 230 35 view .LVU139 + 344 0126 0322 movs r2, #3 + 345 0128 02FA0EF2 lsl r2, r2, lr + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + 346 .loc 1 230 12 view .LVU140 + 347 012c 24EA0204 bic r4, r4, r2 + 348 .LVL40: + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->MODER = temp; + 349 .loc 1 231 7 is_stmt 1 view .LVU141 + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->MODER = temp; + 350 .loc 1 231 26 is_stmt 0 view .LVU142 + 351 0130 4A68 ldr r2, [r1, #4] + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->MODER = temp; + 352 .loc 1 231 33 view .LVU143 + 353 0132 02F00302 and r2, r2, #3 + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->MODER = temp; + 354 .loc 1 231 46 view .LVU144 + 355 0136 02FA0EF2 lsl r2, r2, lr + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->MODER = temp; + 356 .loc 1 231 12 view .LVU145 + 357 013a 2243 orrs r2, r2, r4 + 358 .LVL41: + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 359 .loc 1 232 7 is_stmt 1 view .LVU146 + ARM GAS /tmp/ccXhcUUd.s page 13 + + + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 360 .loc 1 232 20 is_stmt 0 view .LVU147 + 361 013c 0260 str r2, [r0] + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 362 .loc 1 236 7 is_stmt 1 view .LVU148 + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 363 .loc 1 236 21 is_stmt 0 view .LVU149 + 364 013e 4A68 ldr r2, [r1, #4] + 365 .LVL42: + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 366 .loc 1 236 10 view .LVU150 + 367 0140 12F4403F tst r2, #196608 + 368 0144 C6D0 beq .L3 + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 369 .loc 1 239 9 is_stmt 1 view .LVU151 + 370 .LBB2: + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 371 .loc 1 239 9 view .LVU152 + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 372 .loc 1 239 9 view .LVU153 + 373 0146 2D4A ldr r2, .L31+8 + 374 0148 546C ldr r4, [r2, #68] + 375 014a 44F48044 orr r4, r4, #16384 + 376 014e 5464 str r4, [r2, #68] + 377 .LVL43: + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 378 .loc 1 239 9 view .LVU154 + 379 0150 526C ldr r2, [r2, #68] + 380 0152 02F48042 and r2, r2, #16384 + 381 0156 0192 str r2, [sp, #4] + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 382 .loc 1 239 9 view .LVU155 + 383 0158 019A ldr r2, [sp, #4] + 384 .LBE2: + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 385 .loc 1 239 9 view .LVU156 + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); + 386 .loc 1 241 9 view .LVU157 + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); + 387 .loc 1 241 40 is_stmt 0 view .LVU158 + 388 015a 9C08 lsrs r4, r3, #2 + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); + 389 .loc 1 241 14 view .LVU159 + 390 015c A51C adds r5, r4, #2 + 391 015e 254A ldr r2, .L31 + 392 0160 52F82550 ldr r5, [r2, r5, lsl #2] + 393 .LVL44: + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 394 .loc 1 242 9 is_stmt 1 view .LVU160 + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 395 .loc 1 242 54 is_stmt 0 view .LVU161 + 396 0164 03F0030E and lr, r3, #3 + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 397 .loc 1 242 42 view .LVU162 + 398 0168 4FEA8E0E lsl lr, lr, #2 + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 399 .loc 1 242 36 view .LVU163 + ARM GAS /tmp/ccXhcUUd.s page 14 + + + 400 016c 0F22 movs r2, #15 + 401 016e 02FA0EF2 lsl r2, r2, lr + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + 402 .loc 1 242 14 view .LVU164 + 403 0172 25EA0205 bic r5, r5, r2 + 404 .LVL45: + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 405 .loc 1 243 9 is_stmt 1 view .LVU165 + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 406 .loc 1 243 18 is_stmt 0 view .LVU166 + 407 0176 224A ldr r2, .L31+12 + 408 0178 9042 cmp r0, r2 + 409 017a 3FF475AF beq .L13 + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 410 .loc 1 243 29 discriminator 1 view .LVU167 + 411 017e 02F58062 add r2, r2, #1024 + 412 0182 9042 cmp r0, r2 + 413 0184 22D0 beq .L14 + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 414 .loc 1 243 29 discriminator 3 view .LVU168 + 415 0186 02F58062 add r2, r2, #1024 + 416 018a 9042 cmp r0, r2 + 417 018c 20D0 beq .L15 + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 418 .loc 1 243 29 discriminator 5 view .LVU169 + 419 018e 02F58062 add r2, r2, #1024 + 420 0192 9042 cmp r0, r2 + 421 0194 1ED0 beq .L16 + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 422 .loc 1 243 29 discriminator 7 view .LVU170 + 423 0196 02F58062 add r2, r2, #1024 + 424 019a 9042 cmp r0, r2 + 425 019c 1CD0 beq .L17 + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 426 .loc 1 243 29 discriminator 9 view .LVU171 + 427 019e 02F58062 add r2, r2, #1024 + 428 01a2 9042 cmp r0, r2 + 429 01a4 1AD0 beq .L18 + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 430 .loc 1 243 29 discriminator 11 view .LVU172 + 431 01a6 02F58062 add r2, r2, #1024 + 432 01aa 9042 cmp r0, r2 + 433 01ac 18D0 beq .L19 + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 434 .loc 1 243 29 discriminator 13 view .LVU173 + 435 01ae 02F58062 add r2, r2, #1024 + 436 01b2 9042 cmp r0, r2 + 437 01b4 16D0 beq .L20 + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 438 .loc 1 243 29 discriminator 15 view .LVU174 + 439 01b6 02F58062 add r2, r2, #1024 + 440 01ba 9042 cmp r0, r2 + 441 01bc 14D0 beq .L21 + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 442 .loc 1 243 29 discriminator 17 view .LVU175 + 443 01be 02F58062 add r2, r2, #1024 + 444 01c2 9042 cmp r0, r2 + ARM GAS /tmp/ccXhcUUd.s page 15 + + + 445 01c4 3FF44EAF beq .L30 + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 446 .loc 1 243 29 discriminator 20 view .LVU176 + 447 01c8 0A22 movs r2, #10 + 448 01ca 4EE7 b .L7 + 449 .L14: + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 450 .loc 1 243 29 discriminator 4 view .LVU177 + 451 01cc 0122 movs r2, #1 + 452 .LVL46: + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 453 .loc 1 243 29 discriminator 4 view .LVU178 + 454 01ce 4CE7 b .L7 + 455 .LVL47: + 456 .L15: + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 457 .loc 1 243 29 discriminator 6 view .LVU179 + 458 01d0 0222 movs r2, #2 + 459 01d2 4AE7 b .L7 + 460 .L16: + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 461 .loc 1 243 29 discriminator 8 view .LVU180 + 462 01d4 0322 movs r2, #3 + 463 01d6 48E7 b .L7 + 464 .L17: + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 465 .loc 1 243 29 discriminator 10 view .LVU181 + 466 01d8 0422 movs r2, #4 + 467 01da 46E7 b .L7 + 468 .L18: + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 469 .loc 1 243 29 discriminator 12 view .LVU182 + 470 01dc 0522 movs r2, #5 + 471 01de 44E7 b .L7 + 472 .L19: + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 473 .loc 1 243 29 discriminator 14 view .LVU183 + 474 01e0 0622 movs r2, #6 + 475 01e2 42E7 b .L7 + 476 .L20: + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 477 .loc 1 243 29 discriminator 16 view .LVU184 + 478 01e4 0722 movs r2, #7 + 479 01e6 40E7 b .L7 + 480 .L21: + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] = temp; + 481 .loc 1 243 29 discriminator 18 view .LVU185 + 482 01e8 0822 movs r2, #8 + 483 01ea 3EE7 b .L7 + 484 .LVL48: + 485 .L27: + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 486 .loc 1 282 1 view .LVU186 + 487 01ec 02B0 add sp, sp, #8 + ARM GAS /tmp/ccXhcUUd.s page 16 + + + 488 .LCFI2: + 489 .cfi_def_cfa_offset 16 + 490 @ sp needed + 491 01ee 70BD pop {r4, r5, r6, pc} + 492 .LVL49: + 493 .L26: + 494 .LCFI3: + 495 .cfi_def_cfa_offset 0 + 496 .cfi_restore 4 + 497 .cfi_restore 5 + 498 .cfi_restore 6 + 499 .cfi_restore 14 + 500 .loc 1 282 1 view .LVU187 + 501 01f0 7047 bx lr + 502 .L32: + 503 01f2 00BF .align 2 + 504 .L31: + 505 01f4 00380140 .word 1073821696 + 506 01f8 003C0140 .word 1073822720 + 507 01fc 00380240 .word 1073887232 + 508 0200 00000240 .word 1073872896 + 509 .cfi_endproc + 510 .LFE141: + 512 .section .text.HAL_GPIO_DeInit,"ax",%progbits + 513 .align 1 + 514 .global HAL_GPIO_DeInit + 515 .syntax unified + 516 .thumb + 517 .thumb_func + 519 HAL_GPIO_DeInit: + 520 .LVL50: + 521 .LFB142: + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @brief De-initializes the GPIOx peripheral registers to their default reset values. + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @param GPIO_Pin specifies the port bit to be written. + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * This parameter can be one of GPIO_PIN_x where x can be (0..15). + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @retval None + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** */ + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 522 .loc 1 292 1 is_stmt 1 view -0 + 523 .cfi_startproc + 524 @ args = 0, pretend = 0, frame = 0 + 525 @ frame_needed = 0, uses_anonymous_args = 0 + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** uint32_t position; + 526 .loc 1 293 3 view .LVU189 + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** uint32_t ioposition = 0x00; + 527 .loc 1 294 3 view .LVU190 + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** uint32_t iocurrent = 0x00; + 528 .loc 1 295 3 view .LVU191 + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** uint32_t tmp = 0x00; + 529 .loc 1 296 3 view .LVU192 + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Check the parameters */ + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + ARM GAS /tmp/ccXhcUUd.s page 17 + + + 530 .loc 1 299 3 view .LVU193 + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Configure the port pins */ + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** for (position = 0; position < GPIO_NUMBER; position++) + 531 .loc 1 302 3 view .LVU194 + 532 .loc 1 302 17 is_stmt 0 view .LVU195 + 533 0000 0023 movs r3, #0 + 534 .LVL51: + 535 .loc 1 302 31 is_stmt 1 discriminator 1 view .LVU196 + 536 0002 0F2B cmp r3, #15 + 537 0004 00F29B80 bhi .L52 + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** uint32_t position; + 538 .loc 1 292 1 is_stmt 0 view .LVU197 + 539 0008 F0B5 push {r4, r5, r6, r7, lr} + 540 .LCFI4: + 541 .cfi_def_cfa_offset 20 + 542 .cfi_offset 4, -20 + 543 .cfi_offset 5, -16 + 544 .cfi_offset 6, -12 + 545 .cfi_offset 7, -8 + 546 .cfi_offset 14, -4 + 547 000a 2DE0 b .L38 + 548 .LVL52: + 549 .L55: + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Get the IO position */ + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** ioposition = ((uint32_t)0x01) << position; + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Get the current IO position */ + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** iocurrent = (GPIO_Pin) & ioposition; + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if (iocurrent == ioposition) + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /*------------------------- EXTI Mode Configuration --------------------*/ + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** tmp = SYSCFG->EXTICR[position >> 2]; + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if (tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)))) + 550 .loc 1 314 30 discriminator 19 view .LVU198 + 551 000c 0925 movs r5, #9 + 552 000e 00E0 b .L36 + 553 .L39: + 554 .loc 1 314 19 discriminator 2 view .LVU199 + 555 0010 0025 movs r5, #0 + 556 .L36: + 557 .loc 1 314 53 discriminator 40 view .LVU200 + 558 0012 05FA0CF5 lsl r5, r5, ip + 559 .loc 1 314 10 discriminator 40 view .LVU201 + 560 0016 A542 cmp r5, r4 + 561 0018 75D0 beq .L53 + 562 .LVL53: + 563 .L37: + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Clear EXTI line configuration */ + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** EXTI->IMR &= ~((uint32_t)iocurrent); + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** EXTI->EMR &= ~((uint32_t)iocurrent); + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Clear Rising Falling edge configuration */ + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** EXTI->FTSR &= ~((uint32_t)iocurrent); + ARM GAS /tmp/ccXhcUUd.s page 18 + + + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** EXTI->RTSR &= ~((uint32_t)iocurrent); + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Configure the External Interrupt or event for the current IO */ + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] &= ~tmp; + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /*------------------------- GPIO Mode Configuration --------------------*/ + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Configure IO Direction in Input Floating Mode */ + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2)); + 564 .loc 1 330 7 is_stmt 1 view .LVU202 + 565 .loc 1 330 12 is_stmt 0 view .LVU203 + 566 001a 0468 ldr r4, [r0] + 567 .loc 1 330 56 view .LVU204 + 568 001c 5D00 lsls r5, r3, #1 + 569 .loc 1 330 43 view .LVU205 + 570 001e 4FF0030C mov ip, #3 + 571 0022 0CFA05FC lsl ip, ip, r5 + 572 .loc 1 330 20 view .LVU206 + 573 0026 24EA0C04 bic r4, r4, ip + 574 002a 0460 str r4, [r0] + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Configure the default Alternate Function in current IO */ + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) + 575 .loc 1 333 7 is_stmt 1 view .LVU207 + 576 .loc 1 333 17 is_stmt 0 view .LVU208 + 577 002c 4FEAD30E lsr lr, r3, #3 + 578 0030 0EF1080E add lr, lr, #8 + 579 0034 50F82E40 ldr r4, [r0, lr, lsl #2] + 580 .loc 1 333 56 view .LVU209 + 581 0038 03F00706 and r6, r3, #7 + 582 .loc 1 333 94 view .LVU210 + 583 003c B600 lsls r6, r6, #2 + 584 .loc 1 333 52 view .LVU211 + 585 003e 0F25 movs r5, #15 + 586 0040 B540 lsls r5, r5, r6 + 587 .loc 1 333 33 view .LVU212 + 588 0042 24EA0504 bic r4, r4, r5 + 589 0046 40F82E40 str r4, [r0, lr, lsl #2] + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + 590 .loc 1 336 7 is_stmt 1 view .LVU213 + 591 .loc 1 336 12 is_stmt 0 view .LVU214 + 592 004a C468 ldr r4, [r0, #12] + 593 .loc 1 336 20 view .LVU215 + 594 004c 24EA0C04 bic r4, r4, ip + 595 0050 C460 str r4, [r0, #12] + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Configure the default value IO Output Type */ + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; + 596 .loc 1 339 7 is_stmt 1 view .LVU216 + 597 .loc 1 339 12 is_stmt 0 view .LVU217 + 598 0052 4468 ldr r4, [r0, #4] + 599 .loc 1 339 22 view .LVU218 + 600 0054 24EA0202 bic r2, r4, r2 + 601 .LVL54: + 602 .loc 1 339 22 view .LVU219 + ARM GAS /tmp/ccXhcUUd.s page 19 + + + 603 0058 4260 str r2, [r0, #4] + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Configure the default value for IO Speed */ + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + 604 .loc 1 342 7 is_stmt 1 view .LVU220 + 605 .loc 1 342 12 is_stmt 0 view .LVU221 + 606 005a 8268 ldr r2, [r0, #8] + 607 .loc 1 342 22 view .LVU222 + 608 005c 22EA0C02 bic r2, r2, ip + 609 0060 8260 str r2, [r0, #8] + 610 .L35: + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 611 .loc 1 302 54 is_stmt 1 discriminator 2 view .LVU223 + 612 0062 0133 adds r3, r3, #1 + 613 .LVL55: + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 614 .loc 1 302 31 discriminator 1 view .LVU224 + 615 0064 0F2B cmp r3, #15 + 616 0066 69D8 bhi .L54 + 617 .LVL56: + 618 .L38: + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Get the current IO position */ + 619 .loc 1 305 5 view .LVU225 + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Get the current IO position */ + 620 .loc 1 305 16 is_stmt 0 view .LVU226 + 621 0068 0122 movs r2, #1 + 622 006a 9A40 lsls r2, r2, r3 + 623 .LVL57: + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 624 .loc 1 307 5 is_stmt 1 view .LVU227 + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 625 .loc 1 307 15 is_stmt 0 view .LVU228 + 626 006c 02EA0106 and r6, r2, r1 + 627 .LVL58: + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 628 .loc 1 309 5 is_stmt 1 view .LVU229 + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 629 .loc 1 309 8 is_stmt 0 view .LVU230 + 630 0070 32EA0104 bics r4, r2, r1 + 631 0074 F5D1 bne .L35 + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); + 632 .loc 1 312 7 is_stmt 1 view .LVU231 + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); + 633 .loc 1 312 37 is_stmt 0 view .LVU232 + 634 0076 4FEA930E lsr lr, r3, #2 + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); + 635 .loc 1 312 11 view .LVU233 + 636 007a 0EF10205 add r5, lr, #2 + 637 007e 304C ldr r4, .L56 + 638 0080 54F82540 ldr r4, [r4, r5, lsl #2] + 639 .LVL59: + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if (tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)))) + 640 .loc 1 313 7 is_stmt 1 view .LVU234 + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if (tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)))) + 641 .loc 1 313 50 is_stmt 0 view .LVU235 + 642 0084 03F0030C and ip, r3, #3 + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if (tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)))) + ARM GAS /tmp/ccXhcUUd.s page 20 + + + 643 .loc 1 313 38 view .LVU236 + 644 0088 4FEA8C0C lsl ip, ip, #2 + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if (tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)))) + 645 .loc 1 313 32 view .LVU237 + 646 008c 0F25 movs r5, #15 + 647 008e 05FA0CF7 lsl r7, r5, ip + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if (tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)))) + 648 .loc 1 313 11 view .LVU238 + 649 0092 3C40 ands r4, r4, r7 + 650 .LVL60: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 651 .loc 1 314 7 is_stmt 1 view .LVU239 + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 652 .loc 1 314 19 is_stmt 0 view .LVU240 + 653 0094 2B4D ldr r5, .L56+4 + 654 0096 A842 cmp r0, r5 + 655 0098 BAD0 beq .L39 + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 656 .loc 1 314 30 discriminator 1 view .LVU241 + 657 009a 05F58065 add r5, r5, #1024 + 658 009e A842 cmp r0, r5 + 659 00a0 21D0 beq .L40 + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 660 .loc 1 314 30 discriminator 3 view .LVU242 + 661 00a2 05F58065 add r5, r5, #1024 + 662 00a6 A842 cmp r0, r5 + 663 00a8 1FD0 beq .L41 + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 664 .loc 1 314 30 discriminator 5 view .LVU243 + 665 00aa 05F58065 add r5, r5, #1024 + 666 00ae A842 cmp r0, r5 + 667 00b0 1DD0 beq .L42 + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 668 .loc 1 314 30 discriminator 7 view .LVU244 + 669 00b2 05F58065 add r5, r5, #1024 + 670 00b6 A842 cmp r0, r5 + 671 00b8 1BD0 beq .L43 + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 672 .loc 1 314 30 discriminator 9 view .LVU245 + 673 00ba 05F58065 add r5, r5, #1024 + 674 00be A842 cmp r0, r5 + 675 00c0 19D0 beq .L44 + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 676 .loc 1 314 30 discriminator 11 view .LVU246 + 677 00c2 05F58065 add r5, r5, #1024 + 678 00c6 A842 cmp r0, r5 + 679 00c8 17D0 beq .L45 + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 680 .loc 1 314 30 discriminator 13 view .LVU247 + 681 00ca 05F58065 add r5, r5, #1024 + 682 00ce A842 cmp r0, r5 + 683 00d0 15D0 beq .L46 + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 684 .loc 1 314 30 discriminator 15 view .LVU248 + 685 00d2 05F58065 add r5, r5, #1024 + 686 00d6 A842 cmp r0, r5 + 687 00d8 13D0 beq .L47 + ARM GAS /tmp/ccXhcUUd.s page 21 + + + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 688 .loc 1 314 30 discriminator 17 view .LVU249 + 689 00da 05F58065 add r5, r5, #1024 + 690 00de A842 cmp r0, r5 + 691 00e0 94D0 beq .L55 + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 692 .loc 1 314 30 discriminator 20 view .LVU250 + 693 00e2 0A25 movs r5, #10 + 694 00e4 95E7 b .L36 + 695 .L40: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 696 .loc 1 314 30 discriminator 4 view .LVU251 + 697 00e6 0125 movs r5, #1 + 698 00e8 93E7 b .L36 + 699 .L41: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 700 .loc 1 314 30 discriminator 6 view .LVU252 + 701 00ea 0225 movs r5, #2 + 702 00ec 91E7 b .L36 + 703 .L42: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 704 .loc 1 314 30 discriminator 8 view .LVU253 + 705 00ee 0325 movs r5, #3 + 706 00f0 8FE7 b .L36 + 707 .L43: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 708 .loc 1 314 30 discriminator 10 view .LVU254 + 709 00f2 0425 movs r5, #4 + 710 00f4 8DE7 b .L36 + 711 .L44: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 712 .loc 1 314 30 discriminator 12 view .LVU255 + 713 00f6 0525 movs r5, #5 + 714 00f8 8BE7 b .L36 + 715 .L45: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 716 .loc 1 314 30 discriminator 14 view .LVU256 + 717 00fa 0625 movs r5, #6 + 718 00fc 89E7 b .L36 + 719 .L46: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 720 .loc 1 314 30 discriminator 16 view .LVU257 + 721 00fe 0725 movs r5, #7 + 722 0100 87E7 b .L36 + 723 .L47: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 724 .loc 1 314 30 discriminator 18 view .LVU258 + 725 0102 0825 movs r5, #8 + 726 0104 85E7 b .L36 + 727 .L53: + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** EXTI->EMR &= ~((uint32_t)iocurrent); + 728 .loc 1 317 9 is_stmt 1 view .LVU259 + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** EXTI->EMR &= ~((uint32_t)iocurrent); + 729 .loc 1 317 13 is_stmt 0 view .LVU260 + 730 0106 104C ldr r4, .L56+8 + 731 .LVL61: + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** EXTI->EMR &= ~((uint32_t)iocurrent); + ARM GAS /tmp/ccXhcUUd.s page 22 + + + 732 .loc 1 317 13 view .LVU261 + 733 0108 2568 ldr r5, [r4] + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** EXTI->EMR &= ~((uint32_t)iocurrent); + 734 .loc 1 317 19 view .LVU262 + 735 010a 25EA0605 bic r5, r5, r6 + 736 010e 2560 str r5, [r4] + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 737 .loc 1 318 9 is_stmt 1 view .LVU263 + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 738 .loc 1 318 13 is_stmt 0 view .LVU264 + 739 0110 6568 ldr r5, [r4, #4] + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 740 .loc 1 318 19 view .LVU265 + 741 0112 25EA0605 bic r5, r5, r6 + 742 0116 6560 str r5, [r4, #4] + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** EXTI->RTSR &= ~((uint32_t)iocurrent); + 743 .loc 1 321 9 is_stmt 1 view .LVU266 + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** EXTI->RTSR &= ~((uint32_t)iocurrent); + 744 .loc 1 321 13 is_stmt 0 view .LVU267 + 745 0118 E568 ldr r5, [r4, #12] + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** EXTI->RTSR &= ~((uint32_t)iocurrent); + 746 .loc 1 321 20 view .LVU268 + 747 011a 25EA0605 bic r5, r5, r6 + 748 011e E560 str r5, [r4, #12] + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 749 .loc 1 322 9 is_stmt 1 view .LVU269 + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 750 .loc 1 322 13 is_stmt 0 view .LVU270 + 751 0120 A568 ldr r5, [r4, #8] + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 752 .loc 1 322 20 view .LVU271 + 753 0122 25EA0605 bic r5, r5, r6 + 754 0126 A560 str r5, [r4, #8] + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2] &= ~tmp; + 755 .loc 1 325 9 is_stmt 1 view .LVU272 + 756 .LVL62: + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 757 .loc 1 326 9 view .LVU273 + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 758 .loc 1 326 23 is_stmt 0 view .LVU274 + 759 0128 054E ldr r6, .L56 + 760 .LVL63: + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 761 .loc 1 326 23 view .LVU275 + 762 012a 0EF10204 add r4, lr, #2 + 763 012e 56F82450 ldr r5, [r6, r4, lsl #2] + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 764 .loc 1 326 39 view .LVU276 + 765 0132 25EA0705 bic r5, r5, r7 + 766 0136 46F82450 str r5, [r6, r4, lsl #2] + 767 013a 6EE7 b .L37 + 768 .LVL64: + 769 .L54: + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 770 .loc 1 345 1 view .LVU277 + ARM GAS /tmp/ccXhcUUd.s page 23 + + + 771 013c F0BD pop {r4, r5, r6, r7, pc} + 772 .LVL65: + 773 .L52: + 774 .LCFI5: + 775 .cfi_def_cfa_offset 0 + 776 .cfi_restore 4 + 777 .cfi_restore 5 + 778 .cfi_restore 6 + 779 .cfi_restore 7 + 780 .cfi_restore 14 + 781 .loc 1 345 1 view .LVU278 + 782 013e 7047 bx lr + 783 .L57: + 784 .align 2 + 785 .L56: + 786 0140 00380140 .word 1073821696 + 787 0144 00000240 .word 1073872896 + 788 0148 003C0140 .word 1073822720 + 789 .cfi_endproc + 790 .LFE142: + 792 .section .text.HAL_GPIO_ReadPin,"ax",%progbits + 793 .align 1 + 794 .global HAL_GPIO_ReadPin + 795 .syntax unified + 796 .thumb + 797 .thumb_func + 799 HAL_GPIO_ReadPin: + 800 .LVL66: + 801 .LFB143: + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @} + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** */ + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @brief GPIO Read and Write + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** @verbatim + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** =============================================================================== + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** ##### IO operation functions ##### + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** =============================================================================== + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** @endverbatim + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @{ + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** */ + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @brief Reads the specified input port pin. + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @param GPIO_Pin specifies the port bit to read. + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @retval The input port pin value. + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** */ + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 802 .loc 1 371 1 is_stmt 1 view -0 + 803 .cfi_startproc + ARM GAS /tmp/ccXhcUUd.s page 24 + + + 804 @ args = 0, pretend = 0, frame = 0 + 805 @ frame_needed = 0, uses_anonymous_args = 0 + 806 @ link register save eliminated. + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIO_PinState bitstatus; + 807 .loc 1 372 3 view .LVU280 + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Check the parameters */ + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 808 .loc 1 375 3 view .LVU281 + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + 809 .loc 1 377 3 view .LVU282 + 810 .loc 1 377 13 is_stmt 0 view .LVU283 + 811 0000 0369 ldr r3, [r0, #16] + 812 .loc 1 377 6 view .LVU284 + 813 0002 1942 tst r1, r3 + 814 0004 01D0 beq .L60 + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** bitstatus = GPIO_PIN_SET; + 815 .loc 1 379 15 view .LVU285 + 816 0006 0120 movs r0, #1 + 817 .LVL67: + 818 .loc 1 379 15 view .LVU286 + 819 0008 7047 bx lr + 820 .LVL68: + 821 .L60: + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** else + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** bitstatus = GPIO_PIN_RESET; + 822 .loc 1 383 15 view .LVU287 + 823 000a 0020 movs r0, #0 + 824 .LVL69: + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** return bitstatus; + 825 .loc 1 385 3 is_stmt 1 view .LVU288 + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 826 .loc 1 386 1 is_stmt 0 view .LVU289 + 827 000c 7047 bx lr + 828 .cfi_endproc + 829 .LFE143: + 831 .section .text.HAL_GPIO_WritePin,"ax",%progbits + 832 .align 1 + 833 .global HAL_GPIO_WritePin + 834 .syntax unified + 835 .thumb + 836 .thumb_func + 838 HAL_GPIO_WritePin: + 839 .LVL70: + 840 .LFB144: + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @brief Sets or clears the selected data port bit. + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @note This function uses GPIOx_BSRR register to allow atomic read/modify + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * accesses. In this way, there is no risk of an IRQ occurring between + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * the read and the modify access. + ARM GAS /tmp/ccXhcUUd.s page 25 + + + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @param GPIO_Pin specifies the port bit to be written. + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @param PinState specifies the value to be written to the selected bit. + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * This parameter can be one of the GPIO_PinState enum values: + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @arg GPIO_PIN_RESET: to clear the port pin + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @arg GPIO_PIN_SET: to set the port pin + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @retval None + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** */ + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 841 .loc 1 405 1 is_stmt 1 view -0 + 842 .cfi_startproc + 843 @ args = 0, pretend = 0, frame = 0 + 844 @ frame_needed = 0, uses_anonymous_args = 0 + 845 @ link register save eliminated. + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Check the parameters */ + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 846 .loc 1 407 3 view .LVU291 + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** assert_param(IS_GPIO_PIN_ACTION(PinState)); + 847 .loc 1 408 3 view .LVU292 + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if (PinState != GPIO_PIN_RESET) + 848 .loc 1 410 3 view .LVU293 + 849 .loc 1 410 6 is_stmt 0 view .LVU294 + 850 0000 0AB1 cbz r2, .L62 + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->BSRR = GPIO_Pin; + 851 .loc 1 412 5 is_stmt 1 view .LVU295 + 852 .loc 1 412 17 is_stmt 0 view .LVU296 + 853 0002 8161 str r1, [r0, #24] + 854 0004 7047 bx lr + 855 .L62: + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** else + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; + 856 .loc 1 416 5 is_stmt 1 view .LVU297 + 857 .loc 1 416 38 is_stmt 0 view .LVU298 + 858 0006 0904 lsls r1, r1, #16 + 859 .LVL71: + 860 .loc 1 416 17 view .LVU299 + 861 0008 8161 str r1, [r0, #24] + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 862 .loc 1 418 1 view .LVU300 + 863 000a 7047 bx lr + 864 .cfi_endproc + 865 .LFE144: + 867 .section .text.HAL_GPIO_TogglePin,"ax",%progbits + 868 .align 1 + 869 .global HAL_GPIO_TogglePin + 870 .syntax unified + 871 .thumb + 872 .thumb_func + 874 HAL_GPIO_TogglePin: + ARM GAS /tmp/ccXhcUUd.s page 26 + + + 875 .LVL72: + 876 .LFB145: + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @brief Toggles the specified GPIO pins. + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @param GPIOx Where x can be (A..I) to select the GPIO peripheral. + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @param GPIO_Pin Specifies the pins to be toggled. + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @retval None + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** */ + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 877 .loc 1 428 1 is_stmt 1 view -0 + 878 .cfi_startproc + 879 @ args = 0, pretend = 0, frame = 0 + 880 @ frame_needed = 0, uses_anonymous_args = 0 + 881 @ link register save eliminated. + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** uint32_t odr; + 882 .loc 1 429 3 view .LVU302 + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Check the parameters */ + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 883 .loc 1 432 3 view .LVU303 + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* get current Output Data Register value */ + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** odr = GPIOx->ODR; + 884 .loc 1 435 3 view .LVU304 + 885 .loc 1 435 7 is_stmt 0 view .LVU305 + 886 0000 4369 ldr r3, [r0, #20] + 887 .LVL73: + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Set selected pins that were at low level, and reset ones that were high */ + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); + 888 .loc 1 438 3 is_stmt 1 view .LVU306 + 889 .loc 1 438 23 is_stmt 0 view .LVU307 + 890 0002 01EA0302 and r2, r1, r3 + 891 .loc 1 438 59 view .LVU308 + 892 0006 21EA0301 bic r1, r1, r3 + 893 .LVL74: + 894 .loc 1 438 51 view .LVU309 + 895 000a 41EA0241 orr r1, r1, r2, lsl #16 + 896 .loc 1 438 15 view .LVU310 + 897 000e 8161 str r1, [r0, #24] + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 898 .loc 1 439 1 view .LVU311 + 899 0010 7047 bx lr + 900 .cfi_endproc + 901 .LFE145: + 903 .section .text.HAL_GPIO_LockPin,"ax",%progbits + 904 .align 1 + 905 .global HAL_GPIO_LockPin + 906 .syntax unified + 907 .thumb + 908 .thumb_func + 910 HAL_GPIO_LockPin: + 911 .LVL75: + 912 .LFB146: + ARM GAS /tmp/ccXhcUUd.s page 27 + + + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @brief Locks GPIO Pins configuration registers. + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @note The configuration of the locked GPIO pins can no longer be modified + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * until the next reset. + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F7 family + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @param GPIO_Pin specifies the port bit to be locked. + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @retval None + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** */ + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 913 .loc 1 453 1 is_stmt 1 view -0 + 914 .cfi_startproc + 915 @ args = 0, pretend = 0, frame = 8 + 916 @ frame_needed = 0, uses_anonymous_args = 0 + 917 @ link register save eliminated. + 918 .loc 1 453 1 is_stmt 0 view .LVU313 + 919 0000 82B0 sub sp, sp, #8 + 920 .LCFI6: + 921 .cfi_def_cfa_offset 8 + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** __IO uint32_t tmp = GPIO_LCKR_LCKK; + 922 .loc 1 454 3 is_stmt 1 view .LVU314 + 923 .loc 1 454 17 is_stmt 0 view .LVU315 + 924 0002 4FF48033 mov r3, #65536 + 925 0006 0193 str r3, [sp, #4] + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Check the parameters */ + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 926 .loc 1 457 3 is_stmt 1 view .LVU316 + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Apply lock key write sequence */ + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** tmp |= GPIO_Pin; + 927 .loc 1 460 3 view .LVU317 + 928 .loc 1 460 7 is_stmt 0 view .LVU318 + 929 0008 019B ldr r3, [sp, #4] + 930 000a 0B43 orrs r3, r3, r1 + 931 000c 0193 str r3, [sp, #4] + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->LCKR = tmp; + 932 .loc 1 462 3 is_stmt 1 view .LVU319 + 933 .loc 1 462 15 is_stmt 0 view .LVU320 + 934 000e 019B ldr r3, [sp, #4] + 935 0010 C361 str r3, [r0, #28] + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->LCKR = GPIO_Pin; + 936 .loc 1 464 3 is_stmt 1 view .LVU321 + 937 .loc 1 464 15 is_stmt 0 view .LVU322 + 938 0012 C161 str r1, [r0, #28] + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** GPIOx->LCKR = tmp; + 939 .loc 1 466 3 is_stmt 1 view .LVU323 + 940 .loc 1 466 15 is_stmt 0 view .LVU324 + 941 0014 019B ldr r3, [sp, #4] + 942 0016 C361 str r3, [r0, #28] + ARM GAS /tmp/ccXhcUUd.s page 28 + + + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Read LCKR register. This read is mandatory to complete key lock sequence */ + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** tmp = GPIOx->LCKR; + 943 .loc 1 468 3 is_stmt 1 view .LVU325 + 944 .loc 1 468 14 is_stmt 0 view .LVU326 + 945 0018 C369 ldr r3, [r0, #28] + 946 .loc 1 468 7 view .LVU327 + 947 001a 0193 str r3, [sp, #4] + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Read again in order to confirm lock is active */ + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) + 948 .loc 1 471 3 is_stmt 1 view .LVU328 + 949 .loc 1 471 13 is_stmt 0 view .LVU329 + 950 001c C369 ldr r3, [r0, #28] + 951 .loc 1 471 6 view .LVU330 + 952 001e 13F4803F tst r3, #65536 + 953 0022 02D0 beq .L67 + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** return HAL_OK; + 954 .loc 1 473 12 view .LVU331 + 955 0024 0020 movs r0, #0 + 956 .LVL76: + 957 .L66: + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** else + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** return HAL_ERROR; + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 958 .loc 1 479 1 view .LVU332 + 959 0026 02B0 add sp, sp, #8 + 960 .LCFI7: + 961 .cfi_remember_state + 962 .cfi_def_cfa_offset 0 + 963 @ sp needed + 964 0028 7047 bx lr + 965 .LVL77: + 966 .L67: + 967 .LCFI8: + 968 .cfi_restore_state + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 969 .loc 1 477 12 view .LVU333 + 970 002a 0120 movs r0, #1 + 971 .LVL78: + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 972 .loc 1 477 12 view .LVU334 + 973 002c FBE7 b .L66 + 974 .cfi_endproc + 975 .LFE146: + 977 .section .text.HAL_GPIO_EXTI_Callback,"ax",%progbits + 978 .align 1 + 979 .weak HAL_GPIO_EXTI_Callback + 980 .syntax unified + 981 .thumb + 982 .thumb_func + 984 HAL_GPIO_EXTI_Callback: + 985 .LVL79: + 986 .LFB148: + ARM GAS /tmp/ccXhcUUd.s page 29 + + + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @brief This function handles EXTI interrupt request. + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @param GPIO_Pin Specifies the pins connected EXTI line + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @retval None + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** */ + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* EXTI line interrupt detected */ + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** HAL_GPIO_EXTI_Callback(GPIO_Pin); + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /** + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @brief EXTI line detection callbacks. + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @param GPIO_Pin Specifies the pins connected EXTI line + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** * @retval None + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** */ + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 987 .loc 1 502 1 is_stmt 1 view -0 + 988 .cfi_startproc + 989 @ args = 0, pretend = 0, frame = 0 + 990 @ frame_needed = 0, uses_anonymous_args = 0 + 991 @ link register save eliminated. + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* Prevent unused argument(s) compilation warning */ + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** UNUSED(GPIO_Pin); + 992 .loc 1 504 3 view .LVU336 + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* NOTE: This function Should not be modified, when the callback is needed, + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** the HAL_GPIO_EXTI_Callback could be implemented in the user file + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** */ + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 993 .loc 1 509 1 is_stmt 0 view .LVU337 + 994 0000 7047 bx lr + 995 .cfi_endproc + 996 .LFE148: + 998 .section .text.HAL_GPIO_EXTI_IRQHandler,"ax",%progbits + 999 .align 1 + 1000 .global HAL_GPIO_EXTI_IRQHandler + 1001 .syntax unified + 1002 .thumb + 1003 .thumb_func + 1005 HAL_GPIO_EXTI_IRQHandler: + 1006 .LVL80: + 1007 .LFB147: + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* EXTI line interrupt detected */ + 1008 .loc 1 487 1 is_stmt 1 view -0 + 1009 .cfi_startproc + 1010 @ args = 0, pretend = 0, frame = 0 + 1011 @ frame_needed = 0, uses_anonymous_args = 0 + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** /* EXTI line interrupt detected */ + 1012 .loc 1 487 1 is_stmt 0 view .LVU339 + 1013 0000 08B5 push {r3, lr} + ARM GAS /tmp/ccXhcUUd.s page 30 + + + 1014 .LCFI9: + 1015 .cfi_def_cfa_offset 8 + 1016 .cfi_offset 3, -8 + 1017 .cfi_offset 14, -4 + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 1018 .loc 1 489 3 is_stmt 1 view .LVU340 + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 1019 .loc 1 489 7 is_stmt 0 view .LVU341 + 1020 0002 054B ldr r3, .L74 + 1021 0004 5B69 ldr r3, [r3, #20] + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** { + 1022 .loc 1 489 6 view .LVU342 + 1023 0006 0342 tst r3, r0 + 1024 0008 00D1 bne .L73 + 1025 .LVL81: + 1026 .L70: + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 1027 .loc 1 494 1 view .LVU343 + 1028 000a 08BD pop {r3, pc} + 1029 .LVL82: + 1030 .L73: + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** HAL_GPIO_EXTI_Callback(GPIO_Pin); + 1031 .loc 1 491 5 is_stmt 1 view .LVU344 + 1032 000c 024B ldr r3, .L74 + 1033 000e 5861 str r0, [r3, #20] + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** } + 1034 .loc 1 492 5 view .LVU345 + 1035 0010 FFF7FEFF bl HAL_GPIO_EXTI_Callback + 1036 .LVL83: + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c **** + 1037 .loc 1 494 1 is_stmt 0 view .LVU346 + 1038 0014 F9E7 b .L70 + 1039 .L75: + 1040 0016 00BF .align 2 + 1041 .L74: + 1042 0018 003C0140 .word 1073822720 + 1043 .cfi_endproc + 1044 .LFE147: + 1046 .text + 1047 .Letext0: + 1048 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 1049 .file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 1050 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + 1051 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 1052 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h" + ARM GAS /tmp/ccXhcUUd.s page 31 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_gpio.c + /tmp/ccXhcUUd.s:20 .text.HAL_GPIO_Init:00000000 $t + /tmp/ccXhcUUd.s:26 .text.HAL_GPIO_Init:00000000 HAL_GPIO_Init + /tmp/ccXhcUUd.s:505 .text.HAL_GPIO_Init:000001f4 $d + /tmp/ccXhcUUd.s:513 .text.HAL_GPIO_DeInit:00000000 $t + /tmp/ccXhcUUd.s:519 .text.HAL_GPIO_DeInit:00000000 HAL_GPIO_DeInit + /tmp/ccXhcUUd.s:786 .text.HAL_GPIO_DeInit:00000140 $d + /tmp/ccXhcUUd.s:793 .text.HAL_GPIO_ReadPin:00000000 $t + /tmp/ccXhcUUd.s:799 .text.HAL_GPIO_ReadPin:00000000 HAL_GPIO_ReadPin + /tmp/ccXhcUUd.s:832 .text.HAL_GPIO_WritePin:00000000 $t + /tmp/ccXhcUUd.s:838 .text.HAL_GPIO_WritePin:00000000 HAL_GPIO_WritePin + /tmp/ccXhcUUd.s:868 .text.HAL_GPIO_TogglePin:00000000 $t + /tmp/ccXhcUUd.s:874 .text.HAL_GPIO_TogglePin:00000000 HAL_GPIO_TogglePin + /tmp/ccXhcUUd.s:904 .text.HAL_GPIO_LockPin:00000000 $t + /tmp/ccXhcUUd.s:910 .text.HAL_GPIO_LockPin:00000000 HAL_GPIO_LockPin + /tmp/ccXhcUUd.s:978 .text.HAL_GPIO_EXTI_Callback:00000000 $t + /tmp/ccXhcUUd.s:984 .text.HAL_GPIO_EXTI_Callback:00000000 HAL_GPIO_EXTI_Callback + /tmp/ccXhcUUd.s:999 .text.HAL_GPIO_EXTI_IRQHandler:00000000 $t + /tmp/ccXhcUUd.s:1005 .text.HAL_GPIO_EXTI_IRQHandler:00000000 HAL_GPIO_EXTI_IRQHandler + /tmp/ccXhcUUd.s:1042 .text.HAL_GPIO_EXTI_IRQHandler:00000018 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32f7xx_hal_gpio.o b/build/stm32f7xx_hal_gpio.o new file mode 100644 index 0000000000000000000000000000000000000000..20a862d4c7bda58db85b983e98daa1b8b7b93471 GIT binary patch literal 14484 zcmbW73v?XCm4>Ukr$;lR(dg;7j7Kk9*l6_flL+f=Tef5gNd^-hk}QoZEwZE?jSM6Z z4A{gFhd^u+0&JWR%(4&ySwdcW5>CL&vU?I@V3Uw68+;A{ohaGFU^_OC!2W;r?a^rP z$!1eW-Cx~Xw{BJ4s;-`H^^MJ~8w|rxZZcGq4{p;?d6T;%HFnS zXnQsv8XB7pn#I#Wd+X5LQ+t*e$6C?iWvxege=}qvN39ZVck3Iy12fuM$98LLw6}Pu zu&!-r&Z#|)&TMHd>@})6ru}=2!h7q2L!N0fST*hOoP4o$$aBK-7&XQPxBqhUka@x~ zt>yk>M~ALdR^cOc9N+Cjk6>)i^g5;H^3NXgI1$mkcOt-g97|!N3A>zAb+ykOE8E;X z(sXK1Q};mUh%o-OIHPFSJ#={rK1+Dpl_X%}w3v!V9Xy%O0I%O7ap0WxzO?e78OxcA^Q{KXc zskFknDPQ6GDf5Z(AB=BQPph>?ovOjH)~r(shh78s?K$yO*>Qgf=BmVgH+cF;!z4z3 zCFa!%2H&;c$4q%Vz3tO4heB`pLLFx#b(nYWw^e4zQ;41Ise|SyR!Puv)LAWNL+{N) zg_z@;^^6R^!uc?#4R6)7;W_SeUeE*nz zdQbG>h63Rd;bP$;;R4}2;T&PE@X)b9$=y>%$-ybJLVzVVHI56_Lm#vJ zAXz`7Dl&hNFnsG^hYJV!$^~m!9Am|m3vNf=a~*9wX%9eUd+g!SxbjlL#9HRczQDKGa;Yl^1L-V3-<7lc9jLzC z74uYj3mUOjm=;_2vXOEqq#K?k$oopIant`(8*?kGz=trmCS2JQD5D&AWnZ9? z_LHt0^tUvj@!hVR3R7fV=gRs1`VFxEgqh7QnnhuiZqneB zrnM3ZU$J$Q>EDRq2VS6`Tikle-_h2nti7)63H&$9_nFz3!q_bG1%AsI-D+m*i7A@z zZ)`w2pLXr@0}pW=`&~Kg#EF%4oGj&GtLZ0kvTif2SJ|0E*8iCP{pg;*5x)ND)>VOD z(CUOMdjj91{FW>G{EaQJf7_LVfnTt1CtW!!@Fm)xa^<{0JwtHXmFEX~X#Xd7Ect;0 z9P1gkJRJB8$8y${ivz>7f5*(e2XZVKE$du2&`n*uObmSM^I?g%Vlx#`N?fhSpRx$^eFr&;c? zWUj6V{FeT0x4bv7hVk&a@<8A&+NZhg4F#^EKc8DZ?r-cuy#1~m58OxlfNOtk;BMNd zJLOi<9wRV8MbK63H3G}nVuq{OZv-BpMaWegFap;zW|^+yPD7>lP?K$0!{~i5&ET%# zx!-sKo-&?82UMu5xf}a{>GODDDHirJB=9)hiXf%P32 zW#)M!{#sk9td8MP<*f)hYg=W%1oz%*5k1+XsOeoTqA&Z$EL|sJFgp{Tyfq?b@lu1l z-kOG5`s8gg2GL4J2qh|m`-P#b1+2Ew+Jb@{<8t=%w2^@#bd|>q%J>Hq<#O&(Qnrii zPoh}sFAB9guII2;NXlh zFRFhR<3e#2g>OLn5DusPqeg>n|Kj=aUE|7l&Tv-ZUDvAx9&UO$#_#FnQR!6<1P)+7 z9OY`Sj~dJ9)#z~g_^7dl{?6h!g=68^Kuj5r89Igq@W&9r=`s%WkT?xOMW??=I6Y)6 zO?G<7SWTyEQI}g??pzM%kg=7aH#*fK<7#M)n31U`1C}ZzE-TX9(Z`GkUG9V>SD!Qb zn6cg&eg4Sadh67XbHd`u^ezrpQ4DFtVS7-D^Mv2o=$6t}LiVMxSIR7{+ zmN?^n8+HDGBfp8PH;HS7U9&i?j z2XC{-9 zsDXjYDBZTtlaA|20of-Z>SD} zJ4QgAv`(w@ൄpYW>SxnGNaxuh2N^Y$bTDC?mck-GM(E}ezOQAtC1gp5sRG=4> zFK~(pdPy#ZI4f}=hPs&GwyI4HXFM}@>@G_U)itAZatspc6Nz|yr2b4L$Gn4JlgT}! zOcxjz!Ob(d7@{P%6o#&fWPQ#cxgPV3d>+XSlX^E{+tkUKgNnl>ZIT9ueJCZdO;c6q zIo^)Ep*o2H9JZ>QP{oIt9TM@z;=?1z)@ZMt1Uo`Ql+5(0;xLSK!iIK^l-%e-lpE?2 zf(?6BO#QuDc-ZZPPj`YEw;$BpSWL}0?3e4VTtcurZgsb7GsfrY9k)}q?xc_Qs(UX= ze7c41Qfa|Zm!8WNT_jJG#LscaG&1|Dh?uP7$ezW4`6gaKcf^p{V>lQ}&Oh_NpDAXRotH_U8OOONJ-K6S z-cVP(39uTn=c?^Y3T*yg$!#YKwVX|48?hFLp}L70o$YJ_E^)F1f3X|tDuN3P;UKuO z47H8;grg;{$C0Mus;YQW6;j~xfOp~xI=hXy*U=JRceKP4j+S`F(Go`;E%Bc^+v!1M z@^o~%iMcx4SqL~+T{ltZXo(ISCOSL-a&FM=b49fq-np)@>hxLX9EIK_C^LpkT(eBv z8JQvur2fp0XHn~Q%se+6roY9{LtZ{)sRHI6S4A<;T`2W`}@oLV!O&l$3~-N(Y_tS<(1Wusz_z|@M!q-W>&@K~gu{hf#p z;H^t!h~W~O)v$sByKkaWil}`IL(nW?7eiki zwl|_$SR2mMhE{H5j$Mqb)?Q?nAiE`E7r@_U?R}|JPZyWlMUWPwYq?fVjh%yx8Nu6c z(^Cq2!s){@Soyte?1R%5N2L2#ZU>P~_qN(u+NQ$J6S`w_`}?=r^V^7 zhwT8zUO6Yxa23=gGA-qHKBQtuPCV!(&0CyQ6|OQOIyh;V;0lx%L9BsQxxEk)CL{ty z1d0M3Gq*ar;rG@W#`ewOJi8Q@x`{3JYGkoSiWAEu2MSJ|u^A_eC!414Qp8>g5S1S&xytTHPc<(A6eSFYwYt- zG1ruPU6yt4PWV;ivpW#hFvylaQdsG$WZDi zdKss`6hJH?JA;=^F6Z?k=ACS<&SHSBR%dH-xv<0bvdsv6?)I>mHY@aR>(I~1({-_% zWLAWWZOdDTZ6((40J5$*&#b`|SVq0L&y`md%BypxDUcdCXaywV*W z8y}k(jt`HGs*cH#5!KP!+EUfkxM5?b8W|hi8P+Gh+OO|usO;?O?o?e}jVNsB>g-e# zLu0Xcn59jPTUe)(jaEBdX0z>EoSy3rw&9h3TZfv2{o0EY9`E8Z8MoN)a$wsl|}JBH&E zTCK{5#&$)^2crXh<|M_M{2EG&UU9kxPW2f2c2}`_7?GEeJIaJhy%?~xbTo9-XBBPe#*1jZer7k((s}Ww zzR`h^XpC!28w`*2PsUAH-IFEK4#ES0O#pRP+=Fbkb@j@jV^=*3Xw)N+4p zo%1IYez%pM<7ZC4VjMd!X>O`WXtTc-4<@FToZPFq=u_1s;Vn1D%OR|cJ+@>Ueu4vIC^c_t~HS3LzBC9fP>Hv zj_+PoHc+{m;>cKEybQl{FT#o%fTAzfKXeg(0q^xJd&41g0KU7JH$dp-N`@2@+I`p|sytx#5dNFDvx=Uza0v1+#IYHD`AwSt?^jK+aN`DRNed>^|%|YHQZYVEx&>vu3R_mM={4$Jv=lc(m2;O&NY( z7de>E<;YX!+Rwp!T_`fwcn;=ci^yExIf(z2BD1GCh&SI(us+v#4&r;0$XwTji03^b zb6w{ke&>3u>{rEcRXi}W#pw+$ag&e@FCn}4;e;Y_b4zGuekmkW?oXVAV)pHAwmRvS zgno0D0;PNzg%<+|DPv)thkq6b=Li{X69X+F7dtPCX;&@fj4kDQ;U;0b@DkzW!eQa4 z@Dsw%3SSn!E<7pB#e}e(T4B48{}iKsOn6wxe}++iOgJS>!z5BaPq;>SrSKNvLE)3a zXN4~dUl;Q80s6DBt&q9GB4M?#QP?Hy7fuLo5grtNP57knS>emV*M%pA7Pcw2UnHy+ zHVL;02Zj7E8SQTqJ}7)r_?+;^!k2`v2wxLg*zV{jM_3@N5Y`DlF67uhcQtAu|?qW-AxM&T{O+e!F4NMZ~9qVPe{KPh~ggr8@H&x`(-!Z%55 zIn%;3qPK9{V7)Y9kVJcngv&&~LRcmGkCC{g)CwD=yiLll5MC|3M#?`a+#~t}BHt;z zTl8NQ`H1k_!tV=zM53SnPGT;8B79NG|4Yh$D?B4)pE+KyFr9>-xgswVE)o55kt4!t z(XSV|LAa4bKeh<@k0<(N;(Efe*VOwZWbUKXmkKWs>irRVen!UfjY8ggD0d3={s>v` zhghF6>cLM4KP9|Xc)RfP!Y>HFA^d0I_k{fFg#Laad{Ov{@Kxbi66^YXp~d|Ya+;7I zK~OFc@}mZ>W4<&e`Oz4;QOFM#xK8i2!5wU{)6yc;RnJX?-Q`g67uT|$`Rpe z;f2C_VY9GR*de@Bc)5_Dbnv3e@ID27P?#lLBwQj~DqJpHC0r+L7Pbhxh1-Sw!kt2X ziNbbo5q?JaIpG(C_X@u%JR;;*E3E%J;Yr~c;Riz6@bC*Wgn7dG!X?5Y;c{U_xJtNA zsPEgzH;K%z!q`r`@Cu>6pChmD=it?%=LcT2-!0VlcjWc`9o#Sa1HyyCFABdbd_ee5 z!pDT)5`I_swD4J>{vCk)3nKqa_)Fn&;ctY$7oHHF5xytHZC06hDAM~qbja%KCro0W zDkZW1Rgl;x*OJ(G>qz{r*+gQWXJTA1eVVugwI6*yfuQ}vAD^G;SGNPdeAb}knsN+3IF={5By!t-xu(+ zmqdNtFMQ9X`vu!N`i0y?!rzd{BP9G@EAsUu{O=d}0Eu?)5&3=+?R`t+?~-WusL0Qg zj9+Bpx?SaLCQ!txjA;_zp%zc1%pD2o;gUQ;>cFOVP=5Sc=wt8cR_pp2<@5 zGf!qI1@7}%ihA}_S_JQa&SjAFyrxYCqB|yc_6&~>j$w>C-?w8&EV^4Im5z+{CyRZt zzR{gg1cFUCbv~*Y86J(g9uY|u=^xv*i?1n@Y7NHvcEPB=vn|pWkH?00Ovd5%uT6_! zh-IgrHCcyiGdbZFrBeaUw8Pe|Q>q=yn3mzdQu{yccul0X%Xb8B!X=!X z8g_15Gx4;6nvXhCj}iPPTcVtfNwo?TsRN!;NW=O^gjIUWPv2N z>@?(Lf7{`&6nhB$VQWbE!~ZL1`RhmU`1{OFuD^LHc6VSh(z#Jfa_#u;Ai3Q=d_e>| zw#)sN<7Ic3ruh33HoNW6yUF#(capRGVbk3NBl_d~x&GFr_MXU&%@sy z7||c9B>Zhj@wX29;Uni5FMoq4_it0BGl%pyH_6|n;*a+Xrq^+yzTr+jWEAUTM~dC^ zVdok|u}-cX-@!2NrW0YMUU3D`bWKmGB^9b|A$sj literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_hal_i2c.d b/build/stm32f7xx_hal_i2c.d new file mode 100644 index 0000000..ae9362f --- /dev/null +++ b/build/stm32f7xx_hal_i2c.d @@ -0,0 +1,68 @@ +build/stm32f7xx_hal_i2c.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/build/stm32f7xx_hal_i2c.lst b/build/stm32f7xx_hal_i2c.lst new file mode 100644 index 0000000..d173320 --- /dev/null +++ b/build/stm32f7xx_hal_i2c.lst @@ -0,0 +1,28773 @@ +ARM GAS /tmp/ccSHpINd.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_hal_i2c.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c" + 19 .section .text.I2C_Flush_TXDR,"ax",%progbits + 20 .align 1 + 21 .syntax unified + 22 .thumb + 23 .thumb_func + 25 I2C_Flush_TXDR: + 26 .LVL0: + 27 .LFB206: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @file stm32f7xx_hal_i2c.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief I2C HAL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * functionalities of the Inter Integrated Circuit (I2C) peripheral: + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * + IO operation functions + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * + Peripheral State and Errors functions + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ****************************************************************************** + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @attention + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * Copyright (c) 2017 STMicroelectronics. + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * All rights reserved. + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * This software is licensed under terms that can be found in the LICENSE file + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in the root directory of this software component. + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ****************************************************************************** + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** @verbatim + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ============================================================================== + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ##### How to use this driver ##### + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ============================================================================== + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** The I2C HAL driver can be used as follows: + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (#) Declare a I2C_HandleTypeDef handle structure, for example: + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_HandleTypeDef hi2c; + ARM GAS /tmp/ccSHpINd.s page 2 + + + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (##) Enable the I2Cx interface clock + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (##) I2C pins configuration + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+++) Enable the clock for the I2C GPIOs + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+++) Configure I2C pins as alternate function open-drain + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (##) NVIC configuration if you need to use interrupt process + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+++) Configure the I2Cx interrupt priority + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+++) Enable the NVIC I2C IRQ Channel + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (##) DMA Configuration if you need to use DMA process + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+++) Declare a DMA_HandleTypeDef handle structure for + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** the transmit or receive stream + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+++) Enable the DMAx interface clock using + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+++) Configure the DMA handle parameters + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+++) Configure the DMA Tx or Rx stream + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** the DMA Tx or Rx stream + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addres + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level H + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceRead + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** *** Polling mode IO operation *** + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ================================= + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit( + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** *** Polling mode IO MEM operation *** + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ===================================== + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_W + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_ + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** *** Interrupt mode IO operation *** + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** =================================== + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Trans + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receiv + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmi + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_ + ARM GAS /tmp/ccSHpINd.s page 3 + + + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_ErrorCallback() + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Ab + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** This action will inform Master to generate a Stop condition to discard the communication + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** *** Interrupt mode or DMA mode IO sequential operation *** + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ========================================================== + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (@) These interfaces allow to manage a sequential transfer with a repeated start condition + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** when a direction change during transfer + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) A specific option field manage the different steps of a sequential transfer + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfac + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** no sequential mode + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start con + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** and data to transfer without a final stop condition + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** start condition, address and data to transfer without a final stop cond + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** an then permit a call the same master sequential interface several time + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_D + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** and with new data to transfer if the direction change or manage only th + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** transfer + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if no direction change and without a final stop condition in both cases + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** and with new data to transfer if the direction change or manage only th + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** transfer + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if no direction change and with a final stop condition in both cases + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a re + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** after several call of the same master sequential interface several time + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (link with option I2C_FIRST_AND_NEXT_FRAME). + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** Usage can, transfer several bytes one by one using + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_Master_Seq_Transmit_IT + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_IT + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Transmit_DMA + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_DMA + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** Receive sequence permit to call the opposite interface Receive or Tra + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** without stopping the communication and so generate a restart conditio + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart c + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** each call of the same master sequential + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** interface. + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** Usage can, transfer several bytes one by one with a restart with slave + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** each bytes using + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_Master_Seq_Transmit_IT + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_IT + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Transmit_DMA + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_DMA + ARM GAS /tmp/ccSHpINd.s page 4 + + + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** generation of STOP condition. + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Different sequential I2C interfaces are listed below: + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA() + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is execut + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltC + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2 + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_DisableListen_IT() + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code to check the Address Match Code and the transmission direction reques + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (Write/Read). + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_ListenCpltCallback() + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA() + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is execute + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCa + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA() + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed a + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_ErrorCallback() + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** This action will inform Master to generate a Stop condition to discard the communication + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** *** Interrupt mode IO MEM operation *** + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ======================================= + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_Mem_Write_IT() + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_Mem_Read_IT() + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_ErrorCallback() + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** *** DMA mode IO operation *** + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ============================== + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_Master_Transmit_DMA() + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + ARM GAS /tmp/ccSHpINd.s page 5 + + + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_Master_Receive_DMA() + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_Slave_Transmit_DMA() + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_Slave_Receive_DMA() + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_ErrorCallback() + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Ab + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** This action will inform Master to generate a Stop condition to discard the communication + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** *** DMA mode IO MEM operation *** + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ================================= + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_Mem_Write_DMA() + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_Mem_Read_DMA() + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_ErrorCallback() + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** *** I2C HAL driver macros list *** + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ================================== + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** Below the list of most used macros in I2C HAL driver. + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** *** Callback registration *** + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ============================================= + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** allows the user to configure dynamically the driver callbacks. + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to register an interrupt callback. + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** Function HAL_I2C_RegisterCallback() allows to register following callbacks: + ARM GAS /tmp/ccSHpINd.s page 6 + + + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) MasterRxCpltCallback : callback for Master reception end of transfer. + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) ListenCpltCallback : callback for end of listen mode. + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) MemRxCpltCallback : callback for Memory reception end of transfer. + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) ErrorCallback : callback for error detection. + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) AbortCpltCallback : callback for abort completion process. + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) MspInitCallback : callback for Msp Init. + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) MspDeInitCallback : callback for Msp DeInit. + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** This function takes as parameters the HAL peripheral handle, the Callback ID + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** and a pointer to the user callback function. + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCall + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** Use function HAL_I2C_UnRegisterCallback to reset a callback to the default + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** weak function. + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** and the Callback ID. + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** This function allows to reset following callbacks: + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) MasterRxCpltCallback : callback for Master reception end of transfer. + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) ListenCpltCallback : callback for end of listen mode. + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) MemRxCpltCallback : callback for Memory reception end of transfer. + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) ErrorCallback : callback for error detection. + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) AbortCpltCallback : callback for abort completion process. + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) MspInitCallback : callback for Msp Init. + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) MspDeInitCallback : callback for Msp DeInit. + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** all callbacks are set to the corresponding weak functions: + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** Exception done for MspInit and MspDeInit functions that are + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** these callbacks are null (not registered beforehand). + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** Exception done MspInit/MspDeInit functions that can be registered/unregistered + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** Then, the user first registers the MspInit/MspDeInit user callbacks + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** or HAL_I2C_Init() function. + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** not defined, the callback registration feature is not available and all callbacks + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** are set to the corresponding weak functions. + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] + ARM GAS /tmp/ccSHpINd.s page 7 + + + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (@) You can refer to the I2C HAL driver header file for more useful macros + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** @endverbatim + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Includes ------------------------------------------------------------------*/ + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #include "stm32f7xx_hal.h" + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @addtogroup STM32F7xx_HAL_Driver + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @{ + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @defgroup I2C I2C + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief I2C HAL module driver + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @{ + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #ifdef HAL_I2C_MODULE_ENABLED + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private typedef -----------------------------------------------------------*/ + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private define ------------------------------------------------------------*/ + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @defgroup I2C_Private_Define I2C Private Define + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @{ + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define MAX_NBYTE_SIZE 255U + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define SLAVE_ADDR_SHIFT 7U + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define SLAVE_ADDR_MSK 0x06U + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private define for @ref PreviousState usage */ + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*!< Mask State define, keep only RX and TX bits */ + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*!< Default Value */ + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_MASTER)) + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*!< Master Busy TX, combinaison of State LSB and Mode enum */ + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_MASTER)) + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*!< Master Busy RX, combinaison of State LSB and Mode enum */ + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_SLAVE)) + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + ARM GAS /tmp/ccSHpINd.s page 8 + + + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_SLAVE)) + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_MEM)) + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_MEM)) + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private define to centralize the enable/disable of Interrupts */ + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** @ref I2C_XFER_LISTEN_IT */ + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** @ref I2C_XFER_LISTEN_IT */ + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2 + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** and @ref I2C_XFER_RX_IT */ + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of glo + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** and NACK treatment */ + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evene + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private define Sequential Transfer Options default/reset value */ + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_NO_OPTION_FRAME (0xFFFF0000U) + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @} + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private macros ------------------------------------------------------------*/ + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @addtogroup I2C_Private_Macro + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @{ + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Macro to get remaining data to transfer on DMA side */ + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @} + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private variables ---------------------------------------------------------*/ + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private function prototypes -----------------------------------------------*/ + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @defgroup I2C_Private_Functions I2C Private Functions + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @{ + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private functions to handle DMA transfer */ + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMAError(DMA_HandleTypeDef *hdma); + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private functions to handle IT transfer */ + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); + ARM GAS /tmp/ccSHpINd.s page 9 + + + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private functions to handle IT transfer */ + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t MemAddress, uint16_t MemAddSize, uint32_t + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t Tickstart); + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t MemAddress, uint16_t MemAddSize, uint32_t T + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t Tickstart); + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private functions for I2C transfer IRQ handler */ + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t ITSources); + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t ITSources); + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t ITSources); + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t ITSources); + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t ITSources); + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t ITSources); + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private functions to handle flags during polling transfer */ + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagSta + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t Timeout, uint32_t Tickstart); + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t Tickstart); + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t Tickstart); + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t Tickstart); + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t Tickstart); + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private functions to centralize the enable/disable of Interrupts */ + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private function to treat different error callback */ + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private function to flush TXDR register */ + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private function to handle start, restart or stop a transfer */ + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t Request); + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Private function to Convert Specific options */ + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** + ARM GAS /tmp/ccSHpINd.s page 10 + + + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @} + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Exported functions --------------------------------------------------------*/ + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions I2C Exported Functions + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @{ + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Initialization and Configuration functions + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** @verbatim + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** =============================================================================== + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ##### Initialization and de-initialization functions ##### + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** =============================================================================== + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] This subsection provides a set of functions allowing to initialize and + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** deinitialize the I2Cx peripheral: + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) User must Implement HAL_I2C_MspInit() function in which he configures + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Call the function HAL_I2C_Init() to configure the selected device with + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** the selected configuration: + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) Clock Timing + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) Own Address 1 + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) Addressing mode (Master, Slave) + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) Dual Addressing mode + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) Own Address 2 + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) Own Address 2 Mask + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) General call mode + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) Nostretch mode + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (+) Call the function HAL_I2C_DeInit() to restore the default configuration + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** of the selected I2Cx peripheral. + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** @endverbatim + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @{ + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Initializes the I2C according to the specified parameters + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in the I2C_InitTypeDef and initialize the associated handle. + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c == NULL) + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + ARM GAS /tmp/ccSHpINd.s page 11 + + + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_RESET) + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Allocate lock resource and initialize it */ + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Lock = HAL_UNLOCKED; + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Init the I2C Callback settings */ + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->MspInitCallback == NULL) + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MspInitCallback(hi2c); + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_MspInit(hi2c); + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable the selected I2C peripheral */ + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_DISABLE(hi2c); + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Configure I2Cx: Frequency range */ + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Own Address1 before set the Own Address1 configuration */ + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Configure I2Cx: Own Address1 and ack own address1 mode */ + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + ARM GAS /tmp/ccSHpINd.s page 12 + + + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else /* I2C_ADDRESSINGMODE_10BIT */ + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Configure I2Cx: Addressing Master mode */ + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear the I2C ADD10 bit */ + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Own Address2 before set the Own Address2 configuration */ + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Configure I2Cx: Dual mode and Own Address2 */ + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Configure I2Cx: Generalcall and NoStretch mode */ + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable the selected I2C peripheral */ + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_ENABLE(hi2c); + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief DeInitialize the I2C peripheral. + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c == NULL) + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ + ARM GAS /tmp/ccSHpINd.s page 13 + + + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable the I2C Peripheral Clock */ + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_DISABLE(hi2c); + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->MspDeInitCallback == NULL) + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MspDeInitCallback(hi2c); + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_MspDeInit(hi2c); + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_RESET; + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Release Lock */ + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Initialize the I2C MSP. + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(hi2c); + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** the HAL_I2C_MspInit could be implemented in the user file + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief DeInitialize the I2C MSP. + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(hi2c); + ARM GAS /tmp/ccSHpINd.s page 14 + + + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** the HAL_I2C_MspDeInit could be implemented in the user file + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Register a User I2C Callback + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * To be used instead of the weak predefined callback + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RES + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param CallbackID ID of the callback to be registered + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * This parameter can be one of the following values: + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pCallback pointer to the Callback function + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status + 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef Callb + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** pI2C_CallbackTypeDef pCallback) + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (pCallback == NULL) + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update the error code */ + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** switch (CallbackID) + 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MasterTxCpltCallback = pCallback; + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MasterRxCpltCallback = pCallback; + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback = pCallback; + ARM GAS /tmp/ccSHpINd.s page 15 + + + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback = pCallback; + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_LISTEN_COMPLETE_CB_ID : + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ListenCpltCallback = pCallback; + 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MemTxCpltCallback = pCallback; + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MemRxCpltCallback = pCallback; + 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_ERROR_CB_ID : + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCallback = pCallback; + 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_ABORT_CB_ID : + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->AbortCpltCallback = pCallback; + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MspInitCallback = pCallback; + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MspDeInitCallback = pCallback; + 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** default : + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update the error code */ + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Return error status */ + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** status = HAL_ERROR; + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if (HAL_I2C_STATE_RESET == hi2c->State) + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** switch (CallbackID) + 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MspInitCallback = pCallback; + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MspDeInitCallback = pCallback; + 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** default : + 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update the error code */ + ARM GAS /tmp/ccSHpINd.s page 16 + + + 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Return error status */ + 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** status = HAL_ERROR; + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update the error code */ + 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Return error status */ + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** status = HAL_ERROR; + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return status; + 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Unregister an I2C Callback + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * I2C callback is redirected to the weak predefined callback + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_R + 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param CallbackID ID of the callback to be unregistered + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * This parameter can be one of the following values: + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * This parameter can be one of the following values: + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef Cal + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) + 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** switch (CallbackID) + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallb + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallb + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + ARM GAS /tmp/ccSHpINd.s page 17 + + + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallba + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallba + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_LISTEN_COMPLETE_CB_ID : + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallbac + 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_ERROR_CB_ID : + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_ABORT_CB_ID : + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback + 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit + 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** default : + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update the error code */ + 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Return error status */ + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** status = HAL_ERROR; + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if (HAL_I2C_STATE_RESET == hi2c->State) + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** switch (CallbackID) + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit + 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + ARM GAS /tmp/ccSHpINd.s page 18 + + + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** default : + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update the error code */ + 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Return error status */ + 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** status = HAL_ERROR; + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update the error code */ + 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Return error status */ + 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** status = HAL_ERROR; + 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return status; + 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** + 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Register the Slave Address Match I2C Callback + 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. + 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pCallback pointer to the Address Match Callback function + 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status + 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pC + 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (pCallback == NULL) + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update the error code */ + 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->AddrCallback = pCallback; + 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else + 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update the error code */ + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Return error status */ + 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** status = HAL_ERROR; + 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return status; +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + ARM GAS /tmp/ccSHpINd.s page 19 + + +1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief UnRegister the Slave Address Match I2C Callback +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined cal +1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) +1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ +1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update the error code */ +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; +1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Return error status */ +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** status = HAL_ERROR; +1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return status; +1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @} +1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions +1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Data transfers functions +1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * +1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** @verbatim +1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** =============================================================================== +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ##### IO operation functions ##### +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** =============================================================================== +1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] +1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** This subsection provides a set of functions allowing to manage the I2C data +1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** transfers. +1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (#) There are two modes of transfer: +1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) Blocking mode : The communication is performed in the polling mode. +1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** The status of all data processing is returned by the same function +1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** after finishing transfer. +1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) No-Blocking mode : The communication is performed using Interrupts +1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** or DMA. These functions return the status of the transfer startup. +1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** The end of the data processing will be indicated through the +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when +1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** using DMA mode. +1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (#) Blocking mode functions are : +1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Master_Transmit() + ARM GAS /tmp/ccSHpINd.s page 20 + + +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Master_Receive() +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Transmit() +1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Receive() +1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Mem_Write() +1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Mem_Read() +1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_IsDeviceReady() +1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (#) No-Blocking mode functions with Interrupt are : +1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Master_Transmit_IT() +1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Master_Receive_IT() +1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Transmit_IT() +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Receive_IT() +1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Mem_Write_IT() +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Mem_Read_IT() +1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Transmit_IT() +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Receive_IT() +1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Transmit_IT() +1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Receive_IT() +1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_EnableListen_IT() +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_DisableListen_IT() +1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Master_Abort_IT() +1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (#) No-Blocking mode functions with DMA are : +1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Master_Transmit_DMA() +1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Master_Receive_DMA() +1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Transmit_DMA() +1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Receive_DMA() +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Mem_Write_DMA() +1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Mem_Read_DMA() +1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Transmit_DMA() +1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Receive_DMA() +1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Transmit_DMA() +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Receive_DMA() +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: +1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_MasterTxCpltCallback() +1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_MasterRxCpltCallback() +1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_SlaveTxCpltCallback() +1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_SlaveRxCpltCallback() +1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_MemTxCpltCallback() +1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_MemRxCpltCallback() +1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_AddrCallback() +1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_ListenCpltCallback() +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_ErrorCallback() +1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (++) HAL_I2C_AbortCpltCallback() +1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** @endverbatim +1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @{ +1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Transmits in master mode an amount of data in blocking mode. +1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer + ARM GAS /tmp/ccSHpINd.s page 21 + + +1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Timeout Timeout duration +1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pD +1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t Size, uint32_t Timeout) +1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; +1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tickstart = HAL_GetTick(); +1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; +1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Preload TX register */ +1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Write data to TXDR */ +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address */ +1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + ARM GAS /tmp/ccSHpINd.s page 22 + + +1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, +1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); +1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address */ +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, +1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); +1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** while (hi2c->XferCount > 0U) +1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Write data to TXDR */ +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until TCR flag is set */ +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) +1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, +1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_NO_STARTSTOP); +1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_NO_STARTSTOP); +1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until STOPF flag is set */ +1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 23 + + +1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear STOP Flag */ +1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Receives in master mode an amount of data in blocking mode. +1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Timeout Timeout duration +1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pDa +1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t Size, uint32_t Timeout) +1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; +1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tickstart = HAL_GetTick(); +1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK +1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + ARM GAS /tmp/ccSHpINd.s page 24 + + +1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address */ +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = 1U; +1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, +1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_READ); +1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_READ); +1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** while (hi2c->XferCount > 0U) +1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until RXNE flag is set */ +1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Read data from RXDR */ +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until TCR flag is set */ +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) +1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, +1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_NO_STARTSTOP); +1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_NO_STARTSTOP); +1338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + ARM GAS /tmp/ccSHpINd.s page 25 + + +1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until STOPF flag is set */ +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear STOP Flag */ +1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +1370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Transmits in slave mode an amount of data in blocking mode. +1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +1373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Timeout Timeout duration +1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, +1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t Timeout) +1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; +1382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t tmpXferCount; +1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef error; +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tickstart = HAL_GetTick(); +1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + ARM GAS /tmp/ccSHpINd.s page 26 + + +1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; +1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Preload TX data if no stretch enable */ +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) +1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Preload TX register */ +1414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Write data to TXDR */ +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until ADDR flag is set */ +1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) +1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Flush TX register */ +1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear ADDR flag */ +1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If 10bit addressing mode is selected */ +1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) +1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until ADDR flag is set */ +1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) +1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Flush TX register */ +1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +1449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear ADDR flag */ +1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +1455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 27 + + +1457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until DIR flag is set Transmitter mode */ +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) +1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Flush TX register */ +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** while (hi2c->XferCount > 0U) +1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Write data to TXDR */ +1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until AF flag is set */ +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart); +1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (error != HAL_OK) +1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check that I2C transfer finished */ +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ +1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Mean XferCount == 0 */ +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpXferCount = hi2c->XferCount; +1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset ErrorCode to NONE */ +1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +1511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Flush TX register */ +1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); + ARM GAS /tmp/ccSHpINd.s page 28 + + +1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear AF flag */ +1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +1517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until STOP flag is set */ +1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear STOP flag */ +1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until BUSY flag is reset */ +1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) +1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +1549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +1551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Receive in slave mode an amount of data in blocking mode +1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Timeout Timeout duration +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +1564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +1565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, +1566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t Timeout) +1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; +1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + ARM GAS /tmp/ccSHpINd.s page 29 + + +1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tickstart = HAL_GetTick(); +1582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; +1592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until ADDR flag is set */ +1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) +1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear ADDR flag */ +1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until DIR flag is reset Receiver mode */ +1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) +1609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** while (hi2c->XferCount > 0U) +1616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until RXNE flag is set */ +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Store Last receive data if any */ +1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) +1625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Read data from RXDR */ +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + ARM GAS /tmp/ccSHpINd.s page 30 + + +1628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Read data from RXDR */ +1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +1641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +1644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +1646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +1647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until STOP flag is set */ +1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear STOP flag */ +1658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +1659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until BUSY flag is reset */ +1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) +1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +1666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +1678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +1682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 31 + + +1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt +1687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +1693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +1695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t +1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t Size) +1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; +1699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +1703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +1717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +1726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +1729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address */ +1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ +1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Preload TX register */ +1736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Write data to TXDR */ +1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +1741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 32 + + +1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +1743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, +1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); +1747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +1749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, +1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); +1752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +1755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* possible to enable all of these */ +1763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +1764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +1765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +1768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +1770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +1772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +1776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt +1777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +1779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +1782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +1783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +1784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +1785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t * +1786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t Size) +1787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; +1789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +1793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +1795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); + ARM GAS /tmp/ccSHpINd.s page 33 + + +1799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = 1U; +1813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +1816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +1819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address */ +1822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ +1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ +1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +1831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, RXI interrupt */ +1833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* possible to enable all of these */ +1834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +1835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +1836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); +1837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +1839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +1841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +1843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +1847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt +1848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +1850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +1853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +1854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 34 + + +1856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +1869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +1874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Preload TX data if no stretch enable */ +1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) +1877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Preload TX register */ +1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Write data to TXDR */ +1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +1881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +1883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +1884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +1886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +1887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +1890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +1895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +1897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* possible to enable all of these */ +1898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +1899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); +1901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +1903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +1905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +1907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +1911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt +1912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + ARM GAS /tmp/ccSHpINd.s page 35 + + +1913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +1915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +1917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +1918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +1919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +1938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +1940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, RXI interrupt */ +1947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* possible to enable all of these */ +1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +1949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +1950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); +1951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +1955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +1957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +1961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Transmit in master mode an amount of data in non-blocking mode with DMA +1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +1967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +1969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + ARM GAS /tmp/ccSHpINd.s page 36 + + +1970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t +1971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t Size) +1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; +1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +1975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t sizetoxfer = 0U; +1976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +1980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +1982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +1983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +1996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +2006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +2009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Preload TX register */ +2011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Write data to TXDR */ +2012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** sizetoxfer = hi2c->XferSize; +2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +2020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +2023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +2025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ + ARM GAS /tmp/ccSHpINd.s page 37 + + +2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; +2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the DMA error callback */ +2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +2035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable the DMA stream */ +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, +2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address */ +2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART +2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), +2060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode, I2C_GENERATE_START_WRITE); +2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update XferCount value */ +2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +2064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +2072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable DMA Request */ +2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ + ARM GAS /tmp/ccSHpINd.s page 38 + + +2084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +2095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +2096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address */ +2098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set NBYTES to write and generate START condition */ +2099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE, +2100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); +2101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +2108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +2109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* possible to enable all of these */ +2110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +2111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +2112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +2113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +2124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Receive in master mode an amount of data in non-blocking mode with DMA +2125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +2127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +2130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t +2134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t Size) +2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; +2137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 39 + + +2141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +2144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +2151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +2154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +2158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = 1U; +2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +2168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +2171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +2173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; +2176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the DMA error callback */ +2178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +2179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +2182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +2183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable the DMA stream */ +2185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)p +2186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); +2187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +2191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +2195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ + ARM GAS /tmp/ccSHpINd.s page 40 + + +2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address */ +2206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART * +2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_ +2208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update XferCount value */ +2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +2211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +2218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +2219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +2220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable DMA Request */ +2222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +2223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +2227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +2232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +2243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address */ +2245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set NBYTES to read and generate START condition */ +2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +2247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_READ); +2248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ + ARM GAS /tmp/ccSHpINd.s page 41 + + +2255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, RXI interrupt */ +2256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* possible to enable all of these */ +2257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +2258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +2259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); +2260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +2263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +2271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA +2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +2276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +2277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +2278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size +2279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +2293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +2294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +2297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; +2302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Preload TX data if no stretch enable */ +2304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) +2305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Preload TX register */ +2307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Write data to TXDR */ +2308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +2309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; + ARM GAS /tmp/ccSHpINd.s page 42 + + +2312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +2314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +2315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount != 0U) +2318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +2320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; +2323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the DMA error callback */ +2325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +2326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +2329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +2330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable the DMA stream */ +2332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, +2333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, +2334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); +2335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +2339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +2343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +2352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +2362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, ADDR interrupts */ +2363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +2364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable DMA Request */ +2366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +2367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else + ARM GAS /tmp/ccSHpINd.s page 43 + + +2369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +2371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +2375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +2376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +2386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +2387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +2394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, ADDR interrupts */ +2395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +2396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +2399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +2407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Receive in slave mode an amount of data in non-blocking mode with DMA +2408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +2410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +2411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +2412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +2413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +2414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +2415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ + ARM GAS /tmp/ccSHpINd.s page 44 + + +2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +2429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +2430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +2433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +2435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; +2438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +2440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; +2443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the DMA error callback */ +2445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +2446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +2449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +2450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable the DMA stream */ +2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pDa +2453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); +2454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +2458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +2471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +2473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +2474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +2481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, ADDR interrupts */ +2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + ARM GAS /tmp/ccSHpINd.s page 45 + + +2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable DMA Request */ +2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +2486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +2490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +2494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +2495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +2503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +2507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +2511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Write an amount of data in blocking mode to a specific memory address +2512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +2514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param MemAddress Internal memory address +2517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +2519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +2520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Timeout Timeout duration +2521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +2522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +2523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddre +2524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Ti +2525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; +2527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ +2529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ + ARM GAS /tmp/ccSHpINd.s page 46 + + +2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK +2546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +2551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +2555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +2557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; +2558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL +2561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ +2568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTST +2572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS +2577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** do +2580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +2582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +2583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Write data to TXDR */ +2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +2589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +2592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +2594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +2595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + ARM GAS /tmp/ccSHpINd.s page 47 + + +2597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until TCR flag is set */ +2599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) +2600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, +2608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_NO_STARTSTOP); +2609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +2614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_NO_STARTSTOP); +2615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } while (hi2c->XferCount > 0U); +2619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +2621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +2622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +2623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear STOP Flag */ +2628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +2629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +2631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +2632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +2640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +2644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +2648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Read an amount of data in blocking mode from a specific memory address +2649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +2651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param MemAddress Internal memory address + ARM GAS /tmp/ccSHpINd.s page 48 + + +2654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +2656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +2657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Timeout Timeout duration +2658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +2659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +2660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddres +2661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Tim +2662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; +2664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ +2666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK +2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +2688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +2692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +2694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; +2695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_ +2698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address */ +2705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +2706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = 1U; +2709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, +2710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_READ); + ARM GAS /tmp/ccSHpINd.s page 49 + + +2711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +2716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_READ); +2717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** do +2720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until RXNE flag is set */ +2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) +2723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Read data from RXDR */ +2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +2729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +2731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +2732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +2734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +2735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +2737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until TCR flag is set */ +2739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) +2740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = 1U; +2747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, +2748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_NO_STARTSTOP); +2749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_NO_STARTSTOP); +2755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } while (hi2c->XferCount > 0U); +2758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +2760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +2762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear STOP Flag */ +2767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + ARM GAS /tmp/ccSHpINd.s page 50 + + +2768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +2770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +2779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +2783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +2786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory addres +2787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +2789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param MemAddress Internal memory address +2792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +2794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +2795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +2796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +2797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAd +2798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +2799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ +2801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +2814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +2817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +2820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +2824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = 0U; + ARM GAS /tmp/ccSHpINd.s page 51 + + +2825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +2827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Mem_ISR_IT; +2829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Devaddress = DevAddress; +2830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +2832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) +2833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prefetch Memory Address */ +2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +2836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset Memaddress content */ +2838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Memaddress = 0xFFFFFFFFU; +2839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +2841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ +2844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); +2845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare Memaddress buffer for LSB part */ +2847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); +2848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_W +2851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +2858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +2860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* possible to enable all of these */ +2861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +2863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +2864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +2870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +2874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory addre +2875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +2877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param MemAddress Internal memory address +2880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer + ARM GAS /tmp/ccSHpINd.s page 52 + + +2882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +2883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +2884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +2885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAdd +2886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +2887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ +2889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +2902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +2905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +2908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +2912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +2914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Mem_ISR_IT; +2916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Devaddress = DevAddress; +2917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +2919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) +2920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prefetch Memory Address */ +2922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +2923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset Memaddress content */ +2925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Memaddress = 0xFFFFFFFFU; +2926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ +2931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); +2932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare Memaddress buffer for LSB part */ +2934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); +2935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_ +2938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 53 + + +2939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +2940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +2945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +2947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* possible to enable all of these */ +2948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +2950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +2951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +2953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +2955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +2957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +2961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address +2962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +2964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param MemAddress Internal memory address +2967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +2969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +2970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +2971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +2972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemA +2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +2974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ +2978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +2986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +2990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +2991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +2992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +2993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 54 + + +2996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +3001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +3003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +3004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Mem_ISR_DMA; +3005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Devaddress = DevAddress; +3006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +3017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) +3018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prefetch Memory Address */ +3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +3021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset Memaddress content */ +3023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Memaddress = 0xFFFFFFFFU; +3024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +3026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ +3029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); +3030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare Memaddress buffer for LSB part */ +3032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); +3033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +3036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +3038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; +3039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the DMA error callback */ +3041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +3042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +3044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +3046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable the DMA stream */ +3048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TX +3049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); +3050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 55 + + +3053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +3054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +3059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +3061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +3064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +3067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +3069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START +3070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +3072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +3077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +3078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* possible to enable all of these */ +3079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +3080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +3081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +3082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +3090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +3091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +3096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +3099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +3103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. +3108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. + ARM GAS /tmp/ccSHpINd.s page 56 + + +3110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param MemAddress Internal memory address +3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +3114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +3115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be read +3116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +3117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +3118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAd +3119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +3120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +3122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ +3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +3125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +3129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +3131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +3132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +3135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +3137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +3143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +3144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +3147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +3150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Mem_ISR_DMA; +3151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Devaddress = DevAddress; +3152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +3163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) +3164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prefetch Memory Address */ +3166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + ARM GAS /tmp/ccSHpINd.s page 57 + + +3167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset Memaddress content */ +3169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Memaddress = 0xFFFFFFFFU; +3170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +3172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ +3175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); +3176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare Memaddress buffer for LSB part */ +3178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); +3179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +3182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +3184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; +3185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the DMA error callback */ +3187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +3188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +3190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +3191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +3192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable the DMA stream */ +3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pDa +3195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); +3196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +3200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +3204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +3205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +3207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +3210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +3213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +3215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_STAR +3216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +3218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +3223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + ARM GAS /tmp/ccSHpINd.s page 58 + + +3224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* possible to enable all of these */ +3225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +3226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +3227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +3228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +3232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +3236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +3237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +3239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +3242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +3245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +3249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +3253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Checks if target device is ready for communication. +3254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @note This function is used with Memory devices +3255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +3257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Trials Number of trials +3260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Timeout Timeout duration +3261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +3262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +3263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Tria +3264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t Timeout) +3265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; +3267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __IO uint32_t I2C_Trials = 0UL; +3269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** FlagStatus tmp1; +3271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** FlagStatus tmp2; +3272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +3276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +3278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ + ARM GAS /tmp/ccSHpINd.s page 59 + + +3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY; +3284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** do +3287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Generate Start */ +3289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); +3290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +3292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until STOPF flag is set or a NACK flag is set*/ +3293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tickstart = HAL_GetTick(); +3294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); +3296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); +3297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** while ((tmp1 == RESET) && (tmp2 == RESET)) +3299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +3301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) +3303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +3305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +3308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +3309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +3311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +3314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); +3318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); +3319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check if the NACKF flag has not been set */ +3322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) +3323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +3325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) +3326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +3328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear STOP Flag */ +3331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +3332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Device is ready */ +3334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +3337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + ARM GAS /tmp/ccSHpINd.s page 60 + + +3338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +3340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +3344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) +3345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +3347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear NACK Flag */ +3350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +3351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear STOP Flag, auto generated with autoend*/ +3353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Trials */ +3357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Trials++; +3358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } while (I2C_Trials < Trials); +3359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +3361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +3364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +3365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +3367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +3370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +3374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +3378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Inte +3379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +3382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +3385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +3386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +3388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +3389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint +3390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t Size, uint32_t XferOptions) +3391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; +3393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_WRITE; +3394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t sizetoxfer = 0U; + ARM GAS /tmp/ccSHpINd.s page 61 + + +3395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ +3397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +3402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +3405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +3406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +3409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +3411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +3413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ +3415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +3419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \ +3427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (XferOptions == I2C_FIRST_AND_LAST_FRAME))) +3428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Preload TX register */ +3430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Write data to TXDR */ +3431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +3432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +3434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +3435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** sizetoxfer = hi2c->XferSize; +3437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +3438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +3439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, +3442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** do not generate Restart Condition */ +3443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +3444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ +3445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) +3446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; +3448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ + ARM GAS /tmp/ccSHpINd.s page 62 + + +3452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); +3453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ +3455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) +3456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to write */ +3462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) +3463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); +3465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); +3469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +3477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +3478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* possible to enable all of these */ +3479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +3480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +3481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +3482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +3484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +3488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +3492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. +3493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +3496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +3499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +3500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +3502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +3503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin +3504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t Size, uint32_t XferOptions) +3505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; +3507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_WRITE; +3508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + ARM GAS /tmp/ccSHpINd.s page 63 + + +3509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t sizetoxfer = 0U; +3510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ +3512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +3520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +3521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +3524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +3526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +3528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ +3530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +3534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \ +3542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (XferOptions == I2C_FIRST_AND_LAST_FRAME))) +3543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Preload TX register */ +3545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Write data to TXDR */ +3546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +3547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +3549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +3550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** sizetoxfer = hi2c->XferSize; +3552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +3553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +3554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, +3557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** do not generate Restart Condition */ +3558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +3559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ +3560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) +3561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; +3563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 64 + + +3566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ +3567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); +3568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ +3570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) +3571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +3577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +3579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +3581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; +3582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the DMA error callback */ +3584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +3585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +3587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +3588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +3589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable the DMA stream */ +3591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, +3592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); +3593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +3597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +3601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +3602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +3604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +3607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +3610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to write */ +3612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) +3613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); +3615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); +3619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update XferCount value */ +3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; + ARM GAS /tmp/ccSHpINd.s page 65 + + +3623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +3625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +3630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +3631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +3632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable DMA Request */ +3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +3635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +3639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +3643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +3644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +3646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +3649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +3654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +3655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address */ +3657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set NBYTES to write and generate START condition */ +3658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) +3659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); +3661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); +3665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +3668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +3673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +3674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* possible to enable all of these */ +3675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +3676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +3677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +3678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 66 + + +3680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +3681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +3685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +3689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Inter +3690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +3693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +3696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +3697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +3699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +3700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8 +3701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t Size, uint32_t XferOptions) +3702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; +3704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_READ; +3705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ +3707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +3712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +3715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +3716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +3719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +3721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +3723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ +3725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +3729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, + ARM GAS /tmp/ccSHpINd.s page 67 + + +3737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** do not generate Restart Condition */ +3738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +3739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ +3740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) +3741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; +3743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ +3747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); +3748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ +3750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) +3751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to read */ +3757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); +3758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +3760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +3765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); +3766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +3768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +3772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +3776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA +3777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +3780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +3783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +3784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +3786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +3787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint +3788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t Size, uint32_t XferOptions) +3789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; +3791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_READ; +3792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 68 + + +3794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ +3795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +3800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +3803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +3804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +3807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +3809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +3811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ +3813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +3817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, +3825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** do not generate Restart Condition */ +3826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +3827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ +3828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) +3829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; +3831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ +3835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); +3836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ +3838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) +3839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +3845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +3847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +3849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; +3850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 69 + + +3851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the DMA error callback */ +3852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +3853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +3855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +3856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +3857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable the DMA stream */ +3859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)p +3860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); +3861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +3865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +3869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +3870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +3872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +3875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +3878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to read */ +3880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); +3881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update XferCount value */ +3883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +3884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +3886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +3891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +3892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +3893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable DMA Request */ +3895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +3896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +3900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +3904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +3905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +3907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + ARM GAS /tmp/ccSHpINd.s page 70 + + +3908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +3910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +3915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +3916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Slave Address */ +3918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set NBYTES to read and generate START condition */ +3919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +3920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_READ); +3921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +3923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +3928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, RXI interrupt */ +3929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* possible to enable all of these */ +3930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +3931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +3932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); +3933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +3936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +3938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +3940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +3944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode wit +3945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +3948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +3949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +3950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +3952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +3953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t S +3954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t XferOptions) +3955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ +3957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** FlagStatus tmp; +3958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ +3960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +3963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) + ARM GAS /tmp/ccSHpINd.s page 71 + + +3965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +3967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +3968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +3969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +3971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); +3972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +3977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* and then toggle the HAL slave RX state to TX state */ +3978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) +3979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable associated Interrupts */ +3981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +3982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +3984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) +3985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +3987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +3989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +3991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; +3993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +3994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Abort DMA RX */ +3995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) +3996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +3997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +3998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); +3999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; +4005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +4006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +4007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +4009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +4010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +4012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +4013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +4014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +4015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +4016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +4017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); +4019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) +4020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ + ARM GAS /tmp/ccSHpINd.s page 72 + + +4022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +4023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +4024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +4027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +4030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +4031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +4032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* REnable ADDR interrupt */ +4033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); +4034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +4036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +4038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +4040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode wit +4045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +4046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +4049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +4050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +4051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +4052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t +4054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t XferOptions) +4055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ +4057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** FlagStatus tmp; +4058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +4059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ +4061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +4062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +4064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +4066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +4068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +4069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +4075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); +4076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +4078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* and then toggle the HAL slave RX state to TX state */ + ARM GAS /tmp/ccSHpINd.s page 73 + + +4079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) +4080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable associated Interrupts */ +4082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +4083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) +4085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +4087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +4088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +4090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +4092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +4093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; +4094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Abort DMA RX */ +4096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) +4097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +4099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); +4100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) +4105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) +4107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +4109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +4111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +4112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +4114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +4115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; +4116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Abort DMA TX */ +4118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) +4119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +4121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); +4122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +4127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Nothing to do */ +4129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; +4132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +4133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +4134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable Address Acknowledge */ + ARM GAS /tmp/ccSHpINd.s page 74 + + +4136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +4137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +4139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +4140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +4141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +4142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +4143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; +4144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +4146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +4148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; +4149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the DMA error callback */ +4151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +4152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +4154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +4155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +4156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable the DMA stream */ +4158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TX +4159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); +4160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +4162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +4164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +4165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +4168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +4169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +4171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +4174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +4177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update XferCount value */ +4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +4180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset XferSize */ +4182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = 0; +4183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +4185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +4187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +4188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +4191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +4192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 75 + + +4193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +4194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +4197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); +4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) +4201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +4203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +4204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +4205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +4208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable DMA Request */ +4211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +4212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +4214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +4215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +4216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, ADDR interrupts */ +4217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +4218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +4220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +4222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +4224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with +4229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +4230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +4233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +4234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +4235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +4236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Si +4238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t XferOptions) +4239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ +4241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** FlagStatus tmp; +4242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ +4244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +4245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +4247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +4249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 76 + + +4250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +4251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +4252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +4255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); +4256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +4258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +4261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* and then toggle the HAL slave TX state to RX state */ +4262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) +4263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable associated Interrupts */ +4265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +4266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) +4268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +4270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +4273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +4275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +4276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; +4277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Abort DMA TX */ +4279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) +4280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +4282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); +4283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; +4289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +4290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +4291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +4293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +4294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +4296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +4297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +4299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +4300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +4301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); +4303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) +4304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +4306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ + ARM GAS /tmp/ccSHpINd.s page 77 + + +4307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +4308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +4311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +4314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +4315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +4316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* REnable ADDR interrupt */ +4317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); +4318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +4320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +4322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +4324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with +4329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +4330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param pData Pointer to data buffer +4333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Amount of data to be sent +4334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +4335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +4336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t S +4338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t XferOptions) +4339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ +4341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** FlagStatus tmp; +4342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +4343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ +4345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +4346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +4348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +4350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +4352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +4353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +4356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); +4357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +4362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* and then toggle the HAL slave TX state to RX state */ +4363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + ARM GAS /tmp/ccSHpINd.s page 78 + + +4364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable associated Interrupts */ +4366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +4367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) +4369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +4371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +4372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +4374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +4376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +4377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; +4378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Abort DMA TX */ +4380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) +4381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); +4384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) +4389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) +4391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +4393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +4395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +4396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +4398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +4399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; +4400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Abort DMA RX */ +4402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) +4403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +4405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); +4406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +4411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Nothing to do */ +4413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; +4416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +4417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +4418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable Address Acknowledge */ +4420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + ARM GAS /tmp/ccSHpINd.s page 79 + + +4421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare transfer parameters */ +4423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +4424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; +4425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +4426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +4427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; +4428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +4430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +4432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; +4433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the DMA error callback */ +4435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +4436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +4438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +4439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +4440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable the DMA stream */ +4442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, +4443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)pData, hi2c->XferSize); +4444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +4446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +4448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +4449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +4452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +4453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +4455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +4458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +4461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update XferCount value */ +4463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +4464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset XferSize */ +4466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = 0; +4467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +4469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C state */ +4471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +4472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update I2C error code */ +4475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +4476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ + ARM GAS /tmp/ccSHpINd.s page 80 + + +4478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +4481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); +4484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) +4485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +4487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +4488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +4489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +4492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable DMA Request */ +4495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +4496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +4498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +4499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +4500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* REnable ADDR interrupt */ +4501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); +4502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +4504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +4506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +4508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Enable the Address listen mode with Interrupt. +4513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +4516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +4518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +4520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +4522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +4523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable the Address Match interrupt */ +4525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +4526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +4528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +4530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +4532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 81 + + +4535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Disable the Address listen mode with Interrupt. +4537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C +4539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +4540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +4542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ +4544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmp; +4545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Address listen mode only if a transfer is not ongoing */ +4547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_LISTEN) +4548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; +4550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); +4551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +4552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; +4554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable the Address Match interrupt */ +4556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +4557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +4559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +4561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_BUSY; +4563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. +4568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +4571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +4572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +4573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +4575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; +4577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM)) +4579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +4581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Interrupts and Store Previous state */ +4584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX) +4585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +4587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; +4588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +4590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + ARM GAS /tmp/ccSHpINd.s page 82 + + +4592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; +4593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +4595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Do nothing */ +4597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set State at HAL_I2C_STATE_ABORT */ +4600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_ABORT; +4601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ +4603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfe +4604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); +4605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +4607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +4610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +4611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** process unlock */ +4612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +4613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +4615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +4617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wrong usage of abort function */ +4619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* This function should be used only in case of abort monitored by master device */ +4620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +4621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @} +4626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks +4629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @{ +4630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief This function handles I2C event interrupt request. +4634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +4637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */ +4639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Get current IT Flags and IT sources value */ +4641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); +4642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); +4643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C events treatment -------------------------------------*/ +4645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferISR != NULL) +4646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR(hi2c, itflags, itsources); +4648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + ARM GAS /tmp/ccSHpINd.s page 83 + + +4649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief This function handles I2C error interrupt request. +4653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +4656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +4658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); +4660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); +4661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmperror; +4662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C Bus error interrupt occurred ------------------------------------*/ +4664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ +4665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) +4666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; +4668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear BERR flag */ +4670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); +4671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ +4674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ +4675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) +4676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; +4678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear OVR flag */ +4680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); +4681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ +4684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ +4685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) +4686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; +4688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear ARLO flag */ +4690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); +4691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Store current volatile hi2c->ErrorCode, misra rule */ +4694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmperror = hi2c->ErrorCode; +4695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the Error Callback in case of Error detected */ +4697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_ +4698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITError(hi2c, tmperror); +4700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Master Tx Transfer completed callback. +4705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + ARM GAS /tmp/ccSHpINd.s page 84 + + +4706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +4708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +4710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(hi2c); +4713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** the HAL_I2C_MasterTxCpltCallback could be implemented in the user file +4716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Master Rx Transfer completed callback. +4721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +4724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +4726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(hi2c); +4729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** the HAL_I2C_MasterRxCpltCallback could be implemented in the user file +4732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @brief Slave Tx Transfer completed callback. +4736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +4739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +4741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(hi2c); +4744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file +4747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Slave Rx Transfer completed callback. +4752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +4755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +4757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(hi2c); +4760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + ARM GAS /tmp/ccSHpINd.s page 85 + + +4763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Slave Address Match callback. +4768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFE +4771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param AddrMatchCode Address Match Code +4772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +4773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrM +4775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(hi2c); +4778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(TransferDirection); +4779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(AddrMatchCode); +4780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** the HAL_I2C_AddrCallback() could be implemented in the user file +4783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Listen Complete callback. +4788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +4791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +4793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(hi2c); +4796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** the HAL_I2C_ListenCpltCallback() could be implemented in the user file +4799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Memory Tx Transfer completed callback. +4804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +4807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +4809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(hi2c); +4812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** the HAL_I2C_MemTxCpltCallback could be implemented in the user file +4815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Memory Rx Transfer completed callback. + ARM GAS /tmp/ccSHpINd.s page 86 + + +4820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +4823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +4825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(hi2c); +4828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** the HAL_I2C_MemRxCpltCallback could be implemented in the user file +4831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief I2C error callback. +4836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +4839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +4841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(hi2c); +4844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** the HAL_I2C_ErrorCallback could be implemented in the user file +4847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief I2C abort callback. +4852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +4855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +4857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(hi2c); +4860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** the HAL_I2C_AbortCpltCallback could be implemented in the user file +4863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @} +4868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions +4871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Peripheral State, Mode and Error functions +4872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * +4873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** @verbatim +4874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** =============================================================================== +4875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ##### Peripheral State, Mode and Error functions ##### +4876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** =============================================================================== + ARM GAS /tmp/ccSHpINd.s page 87 + + +4877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** [..] +4878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** This subsection permit to get in run-time the status of the peripheral +4879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** and the data flow. +4880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** @endverbatim +4882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @{ +4883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Return the I2C handle state. +4887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL state +4890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c) +4892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Return I2C handle state */ +4894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return hi2c->State; +4895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Returns the I2C Master, Slave, Memory or no mode. +4899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for I2C module +4901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL mode +4902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c) +4904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return hi2c->Mode; +4906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Return the I2C error code. +4910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval I2C Error Code +4913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c) +4915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return hi2c->ErrorCode; +4917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @} +4921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @} +4925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** @addtogroup I2C_Private_Functions +4928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @{ +4929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +4932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. +4933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + ARM GAS /tmp/ccSHpINd.s page 88 + + +4934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +4935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +4936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +4937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +4938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +4939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, +4940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t ITSources) +4941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t devaddress; +4943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; +4944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +4946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ +4949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) +4950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear NACK Flag */ +4952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +4953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set corresponding Error Code */ +4955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* No need to generate STOP, it is automatically done */ +4956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Error callback will be send during stop flag treatment */ +4957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +4958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Flush TX register */ +4960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +4961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ +4963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) +4964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Remove RXNE flag on temporary variable as read done */ +4966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpITFlags &= ~I2C_FLAG_RXNE; +4967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Read data from RXDR */ +4969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +4970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +4972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +4973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +4975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +4976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \ +4978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ +4979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))) +4980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Write data to TXDR */ +4982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount != 0U) +4983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Write data to TXDR */ +4985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +4986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +4988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +4989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +4990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + ARM GAS /tmp/ccSHpINd.s page 89 + + +4991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +4992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +4994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ +4995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) +4996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +4998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +4999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); +5000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +5002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Errata workaround 170323 */ +5004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) +5005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = 1U; +5007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +5011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_START +5013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +5017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) +5018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, +5020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions, I2C_NO_STARTSTOP); +5021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, +5025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); +5026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call TxCpltCallback() if no stop mode is set */ +5032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +5033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +5035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); +5036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wrong size Status regarding TCR flag event */ +5040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +5042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ +5046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) +5047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 90 + + +5048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +5049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +5051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Generate a stop condition in case of no transfer option */ +5053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) +5054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Generate Stop */ +5056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; +5057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +5061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); +5062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wrong size Status regarding TC flag event */ +5068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +5070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Nothing to do */ +5075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ +5078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) +5079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Master complete process */ +5081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITMasterCplt(hi2c, tmpITFlags); +5082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +5085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +5088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +5091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. +5092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +5094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +5096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +5097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +5098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, +5099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t ITSources) +5100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t direction = I2C_GENERATE_START_WRITE; +5102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; +5103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ + ARM GAS /tmp/ccSHpINd.s page 91 + + +5105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +5106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ +5108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) +5109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear NACK Flag */ +5111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set corresponding Error Code */ +5114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* No need to generate STOP, it is automatically done */ +5115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Error callback will be send during stop flag treatment */ +5116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +5117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Flush TX register */ +5119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +5120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ +5122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) +5123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Remove RXNE flag on temporary variable as read done */ +5125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpITFlags &= ~I2C_FLAG_RXNE; +5126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Read data from RXDR */ +5128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +5129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +5131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +5132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +5134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +5135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ +5137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) +5138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->Memaddress == 0xFFFFFFFFU) +5140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Write data to TXDR */ +5142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +5143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +5145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +5146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +5148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +5149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Write LSB part of Memory Address */ +5153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = hi2c->Memaddress; +5154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset Memaddress content */ +5156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Memaddress = 0xFFFFFFFFU; +5157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ +5160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) +5161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 92 + + +5162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +5163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +5165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Errata workaround 170323 */ +5167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) +5168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = 1U; +5170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +5174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, +5176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, I2C_NO_STARTSTOP); +5177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +5181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, +5182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); +5183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wrong size Status regarding TCR flag event */ +5188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +5190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ +5193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) +5194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Interrupt related to address step */ +5196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +5197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK and RXI interrupts */ +5199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); +5200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +5202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** direction = I2C_GENERATE_START_READ; +5204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +5207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Errata workaround 170323 */ +5209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) +5210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = 1U; +5212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +5216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + ARM GAS /tmp/ccSHpINd.s page 93 + + +5219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, +5220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, direction); +5221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +5225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set NBYTES to write and generate RESTART */ +5227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, +5228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, direction); +5229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Nothing to do */ +5234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ +5237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) +5238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Master complete process */ +5240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITMasterCplt(hi2c, tmpITFlags); +5241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +5244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +5247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +5250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. +5251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +5253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +5255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +5256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +5257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, +5258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t ITSources) +5259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; +5261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; +5262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process locked */ +5264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +5265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check if STOPF is set */ +5267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ +5268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) +5269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Slave complete process */ +5271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITSlaveCplt(hi2c, tmpITFlags); +5272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ +5274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) +5275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 94 + + +5276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check that I2C transfer finished */ +5277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ +5278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Mean XferCount == 0*/ +5279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* So clear Flag NACKF only */ +5280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +5281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) +5283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for +5284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** Warning[Pa134]: left and right operands are identical */ +5285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Listen complete process */ +5287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITListenCplt(hi2c, tmpITFlags); +5288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME) +5290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear NACK Flag */ +5292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Flush TX register */ +5295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +5296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Last Byte is Transmitted */ +5298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +5299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +5300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear NACK Flag */ +5304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ +5310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear NACK Flag */ +5311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +5314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +5315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) +5317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +5320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ +5324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) +5325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > 0U) +5327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Read data from RXDR */ +5329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +5330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +5332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; + ARM GAS /tmp/ccSHpINd.s page 95 + + +5333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +5335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +5336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->XferCount == 0U) && \ +5339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) +5340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +5342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +5343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ +5346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) +5347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITAddrCplt(hi2c, tmpITFlags); +5349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ +5351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) +5352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Write data to TXDR only if XferCount not reach "0" */ +5354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* A TXIS flag can be set, during STOP treatment */ +5355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check if all Data have already been sent */ +5356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ +5357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > 0U) +5358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Write data to TXDR */ +5360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +5361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +5363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +5364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +5366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +5367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) +5371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Last Byte is Transmitted */ +5373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +5374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +5375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Nothing to do */ +5381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +5384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +5387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** + ARM GAS /tmp/ccSHpINd.s page 96 + + +5390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. +5391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +5393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +5395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +5396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +5397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, +5398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t ITSources) +5399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t devaddress; +5401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; +5402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +5404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +5405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ +5407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) +5408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear NACK Flag */ +5410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set corresponding Error Code */ +5413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +5414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* No need to generate STOP, it is automatically done */ +5416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* But enable STOP interrupt, to treat it */ +5417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Error callback will be send during stop flag treatment */ +5418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +5419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Flush TX register */ +5421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +5422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ +5424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) +5425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable TC interrupt */ +5427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); +5428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount != 0U) +5430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Recover Slave address */ +5432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); +5433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare the new XferSize to transfer */ +5435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +5436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Errata workaround 170323 */ +5438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) +5439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = 1U; +5441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +5445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + ARM GAS /tmp/ccSHpINd.s page 97 + + +5447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +5451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) +5452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +5454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +5458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the new XferSize in Nbytes register */ +5462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); +5463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update XferCount value */ +5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +5466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable DMA Request */ +5468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +5469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +5471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +5475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call TxCpltCallback() if no stop mode is set */ +5480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +5481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +5483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); +5484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wrong size Status regarding TCR flag event */ +5488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +5490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ +5494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) +5495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +5497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +5499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Generate a stop condition in case of no transfer option */ +5501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) +5502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Generate Stop */ + ARM GAS /tmp/ccSHpINd.s page 98 + + +5504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; +5505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +5509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); +5510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wrong size Status regarding TC flag event */ +5516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +5518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ +5521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) +5522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Master complete process */ +5524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITMasterCplt(hi2c, ITFlags); +5525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Nothing to do */ +5529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +5532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +5535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +5538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. +5539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +5541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +5543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +5544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +5545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, +5546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t ITSources) +5547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t direction = I2C_GENERATE_START_WRITE; +5549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Locked */ +5551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +5552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ +5554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) +5555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear NACK Flag */ +5557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set corresponding Error Code */ +5560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + ARM GAS /tmp/ccSHpINd.s page 99 + + +5561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* No need to generate STOP, it is automatically done */ +5563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* But enable STOP interrupt, to treat it */ +5564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Error callback will be send during stop flag treatment */ +5565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +5566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Flush TX register */ +5568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +5569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ +5571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) +5572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Write LSB part of Memory Address */ +5574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = hi2c->Memaddress; +5575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset Memaddress content */ +5577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Memaddress = 0xFFFFFFFFU; +5578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ +5580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) +5581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Interrupt related to address step */ +5583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +5584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable only Error interrupt */ +5586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +5587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount != 0U) +5589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prepare the new XferSize to transfer */ +5591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +5592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Errata workaround 170323 */ +5594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) +5595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = 1U; +5597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +5601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, +5603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, I2C_NO_STARTSTOP); +5604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +5608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, +5609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); +5610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update XferCount value */ +5613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +5614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable DMA Request */ +5616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +5617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 100 + + +5618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +5619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +5623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wrong size Status regarding TCR flag event */ +5628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +5630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ +5633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) +5634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Interrupt related to address step */ +5636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +5637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable only Error and NACK interrupt for data transfer */ +5639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +5640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +5642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** direction = I2C_GENERATE_START_READ; +5644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +5647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Errata workaround 170323 */ +5649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) +5650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = 1U; +5652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +5656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +5659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, +5660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, direction); +5661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +5665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set NBYTES to write and generate RESTART */ +5667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, +5668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, direction); +5669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update XferCount value */ +5672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +5673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable DMA Request */ + ARM GAS /tmp/ccSHpINd.s page 101 + + +5675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +5676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +5678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +5682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ +5685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) +5686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Master complete process */ +5688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITMasterCplt(hi2c, ITFlags); +5689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Nothing to do */ +5693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +5696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +5699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +5702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. +5703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +5705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +5707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +5708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +5709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, +5710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t ITSources) +5711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; +5713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t treatdmanack = 0U; +5714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate; +5715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process locked */ +5717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_LOCK(hi2c); +5718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check if STOPF is set */ +5720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ +5721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) +5722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Slave complete process */ +5724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITSlaveCplt(hi2c, ITFlags); +5725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ +5727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) +5728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check that I2C transfer finished */ +5730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ +5731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Mean XferCount == 0 */ + ARM GAS /tmp/ccSHpINd.s page 102 + + +5732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* So clear Flag NACKF only */ +5733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || +5734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) +5735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Split check of hdmarx, for MISRA compliance */ +5737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +5738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) +5740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) +5742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** treatdmanack = 1U; +5744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Split check of hdmatx, for MISRA compliance */ +5749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +5750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) +5752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) +5754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** treatdmanack = 1U; +5756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (treatdmanack == 1U) +5761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) +5763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for +5764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** Warning[Pa134]: left and right operands are identical */ +5765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Listen complete process */ +5767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITListenCplt(hi2c, ITFlags); +5768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAM +5770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear NACK Flag */ +5772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Flush TX register */ +5775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +5776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Last Byte is Transmitted */ +5778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +5779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +5780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear NACK Flag */ +5784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 103 + + +5789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ +5790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear NACK Flag */ +5791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +5794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +5795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ +5797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpstate = hi2c->State; +5798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) +5800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) +5802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; +5804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN +5806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; +5808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Do nothing */ +5812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +5816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Only Clear NACK Flag, no DMA treatment is pending */ +5822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ +5826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) +5827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITAddrCplt(hi2c, ITFlags); +5829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Nothing to do */ +5833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +5836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +5839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +5842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Master sends target device address followed by internal memory address for write reques +5843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +5845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value + ARM GAS /tmp/ccSHpINd.s page 104 + + +5846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +5847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param MemAddress Internal memory address +5848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +5849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Timeout Timeout duration +5850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Tickstart Tick start value +5851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +5852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +5853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, +5854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t MemAddress, uint16_t MemAddSize, uint32_t +5855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t Tickstart) +5856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRI +5858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +5861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +5863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +5866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) +5867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Memory Address */ +5869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +5870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +5872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send MSB of Memory Address */ +5875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); +5876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +5879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +5881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send LSB of Memory Address */ +5884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +5885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until TCR flag is set */ +5888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) +5889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +5891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +5894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +5897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Master sends target device address followed by internal memory address for read request +5898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +5900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +5901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +5902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param MemAddress Internal memory address + ARM GAS /tmp/ccSHpINd.s page 105 + + +5903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +5904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Timeout Timeout duration +5905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Tickstart Tick start value +5906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +5907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +5908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, +5909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t MemAddress, uint16_t MemAddSize, uint32_t T +5910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t Tickstart) +5911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WR +5913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +5916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +5918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +5921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) +5922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send Memory Address */ +5924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +5925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +5927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +5928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send MSB of Memory Address */ +5930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); +5931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +5934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +5936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Send LSB of Memory Address */ +5939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +5940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until TC flag is set */ +5943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) +5944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +5946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +5949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +5950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +5952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief I2C Address complete process callback. +5953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c I2C handle. +5954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +5956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +5957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +5958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint8_t transferdirection; + ARM GAS /tmp/ccSHpINd.s page 106 + + +5960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t slaveaddrcode; +5961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t ownadd1code; +5962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t ownadd2code; +5963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +5965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(ITFlags); +5966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* In case of Listen state, need to inform upper layer of address match code event */ +5968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +5969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** transferdirection = I2C_GET_DIR(hi2c); +5971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); +5972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); +5973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); +5974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If 10bits addressing mode is selected */ +5976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) +5977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) +5979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** slaveaddrcode = ownadd1code; +5981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->AddrEventCount++; +5982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->AddrEventCount == 2U) +5983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +5984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset Address Event counter */ +5985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->AddrEventCount = 0U; +5986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear ADDR flag */ +5988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +5989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +5991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +5993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call Slave Addr callback */ +5994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +5996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else +5997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +5998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** slaveaddrcode = ownadd2code; +6004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable ADDR Interrupts */ +6006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +6007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +6009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call Slave Addr callback */ +6012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +6014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else +6015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +6016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + ARM GAS /tmp/ccSHpINd.s page 107 + + +6017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* else 7 bits addressing mode is selected */ +6020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable ADDR Interrupts */ +6023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +6024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +6026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call Slave Addr callback */ +6029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +6031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else +6032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +6033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Else clear address flag only */ +6037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear ADDR flag */ +6040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +6041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +6043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +6048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief I2C Master sequential complete process. +6049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c I2C handle. +6050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +6051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +6052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) +6053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset I2C handle mode */ +6055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* No Generate Stop, to permit restart mode */ +6058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ +6059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX) +6060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; +6063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; +6064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Interrupts */ +6066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +6067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +6069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MasterTxCpltCallback(hi2c); + ARM GAS /tmp/ccSHpINd.s page 108 + + +6074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else +6075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_MasterTxCpltCallback(hi2c); +6076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ +6079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; +6083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; +6084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Interrupts */ +6086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +6087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +6089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MasterRxCpltCallback(hi2c); +6094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else +6095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_MasterRxCpltCallback(hi2c); +6096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +6101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief I2C Slave sequential complete process. +6102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c I2C handle. +6103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +6104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +6105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) +6106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); +6108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset I2C handle mode */ +6110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If a DMA is ongoing, Update handle size context */ +6113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) +6114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable DMA Request */ +6116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +6117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) +6119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable DMA Request */ +6121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +6122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Do nothing */ +6126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) +6129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + ARM GAS /tmp/ccSHpINd.s page 109 + + +6131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +6132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; +6133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Interrupts */ +6135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +6136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +6138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback(hi2c); +6143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else +6144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_SlaveTxCpltCallback(hi2c); +6145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) +6149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ +6151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +6152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; +6153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Interrupts */ +6155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +6156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +6158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback(hi2c); +6163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else +6164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_SlaveRxCpltCallback(hi2c); +6165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Nothing to do */ +6170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +6174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief I2C Master complete process. +6175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c I2C handle. +6176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +6177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +6178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +6179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +6180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmperror; +6182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; +6183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __IO uint32_t tmpreg; +6184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear STOP Flag */ +6186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +6187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 110 + + +6188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Interrupts and Store Previous state */ +6189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX) +6190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +6192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; +6193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +6195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +6197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; +6198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Do nothing */ +6202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +6205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +6206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset handle parameters */ +6208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; +6209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +6210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) +6212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear NACK Flag */ +6214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +6215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set acknowledge error code */ +6217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +6218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Fetch Last receive data if any */ +6221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) +6222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Read data from RXDR */ +6224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpreg = (uint8_t)hi2c->Instance->RXDR; +6225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(tmpreg); +6226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Flush TX register */ +6229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +6230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Store current volatile hi2c->ErrorCode, misra rule */ +6232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmperror = hi2c->ErrorCode; +6233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) +6236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +6239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ +6241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) +6242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + ARM GAS /tmp/ccSHpINd.s page 111 + + +6245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MEM) +6247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +6251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MemTxCpltCallback(hi2c); +6256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else +6257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_MemTxCpltCallback(hi2c); +6258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +6265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MasterTxCpltCallback(hi2c); +6270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else +6271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_MasterTxCpltCallback(hi2c); +6272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ +6276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +6277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +6280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MEM) +6282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +6286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MemRxCpltCallback(hi2c); +6291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else +6292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_MemRxCpltCallback(hi2c); +6293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +6300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 112 + + +6302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->MasterRxCpltCallback(hi2c); +6305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else +6306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_MasterRxCpltCallback(hi2c); +6307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Nothing to do */ +6313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +6317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief I2C Slave complete process. +6318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c I2C handle. +6319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +6320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +6321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +6322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +6323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); +6325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; +6326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; +6327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; +6328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear STOP Flag */ +6330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +6331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Interrupts and Store Previous state */ +6333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) +6334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); +6336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; +6337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) +6339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); +6341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; +6342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if (tmpstate == HAL_I2C_STATE_LISTEN) +6344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); +6346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +6347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Do nothing */ +6351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Address Acknowledge */ +6354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +6355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +6357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +6358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 113 + + +6359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Flush TX register */ +6360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +6361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If a DMA is ongoing, Update handle size context */ +6363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) +6364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable DMA Request */ +6366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +6367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +6369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); +6371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) +6374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable DMA Request */ +6376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +6377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +6379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); +6381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Do nothing */ +6386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Store Last receive data if any */ +6389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) +6390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Remove RXNE flag on temporary variable as read done */ +6392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpITFlags &= ~I2C_FLAG_RXNE; +6393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Read data from RXDR */ +6395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +6396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +6398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +6399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->XferSize > 0U)) +6401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +6403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +6404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* All data are not transferred, so set error code accordingly */ +6408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount != 0U) +6409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +6411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +6412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ +6415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + ARM GAS /tmp/ccSHpINd.s page 114 + + +6416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check that I2C transfer finished */ +6418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ +6419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Mean XferCount == 0*/ +6420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* So clear Flag NACKF only */ +6421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +6422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) +6424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for +6425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** Warning[Pa134]: left and right operands are identical */ +6426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Listen complete process */ +6428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITListenCplt(hi2c, tmpITFlags); +6429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME) +6431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear NACK Flag */ +6433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +6434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Flush TX register */ +6436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +6437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Last Byte is Transmitted */ +6439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +6440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +6441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear NACK Flag */ +6445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +6446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ +6451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear NACK Flag */ +6452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +6453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +6455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +6456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) +6458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +6461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; +6467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) +6469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +6472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 115 + + +6473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +6474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_LISTEN) +6475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Listen complete process */ +6477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITListenCplt(hi2c, tmpITFlags); +6478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) +6481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ +6483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +6484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +6486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +6488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +6490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +6493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ListenCpltCallback(hi2c); +6495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else +6496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_ListenCpltCallback(hi2c); +6497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +6501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +6504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +6506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback(hi2c); +6511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else +6512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_SlaveRxCpltCallback(hi2c); +6513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +6519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +6521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback(hi2c); +6526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else +6527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_SlaveTxCpltCallback(hi2c); +6528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + ARM GAS /tmp/ccSHpINd.s page 116 + + +6530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +6533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief I2C Listen complete process. +6534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c I2C handle. +6535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +6536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +6537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +6538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +6539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset handle parameters */ +6541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +6542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +6543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; +6546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Store Last receive data if any */ +6548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) +6549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Read data from RXDR */ +6551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +6552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Increment Buffer pointer */ +6554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr++; +6555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->XferSize > 0U)) +6557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; +6559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; +6560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +6562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +6563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable all Interrupts*/ +6567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); +6568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear NACK Flag */ +6570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +6571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +6573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +6576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ListenCpltCallback(hi2c); +6578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else +6579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_ListenCpltCallback(hi2c); +6580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +6584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief I2C interrupts error process. +6585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c I2C handle. +6586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param ErrorCode Error code to handle. + ARM GAS /tmp/ccSHpINd.s page 117 + + +6587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +6588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +6589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +6590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; +6592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmppreviousstate; +6594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset handle parameters */ +6596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +6598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = 0U; +6599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set new error code */ +6601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= ErrorCode; +6602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Interrupts */ +6604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((tmpstate == HAL_I2C_STATE_LISTEN) || +6605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || +6606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) +6607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable all interrupts, except interrupts related to LISTEN state */ +6609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); +6610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* keep HAL_I2C_STATE_LISTEN if set */ +6612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +6613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +6614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable all interrupts */ +6618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); +6619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Flush TX register */ +6621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +6622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If state is an abort treatment on going, don't change state */ +6624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* This change will be do later */ +6625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State != HAL_I2C_STATE_ABORT) +6626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set HAL_I2C_STATE_READY */ +6628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check if a STOPF is detected */ +6631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) +6632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) +6634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +6636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +6637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear STOP Flag */ +6640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +6641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + ARM GAS /tmp/ccSHpINd.s page 118 + + +6644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; +6645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Abort DMA TX transfer if any */ +6648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmppreviousstate = hi2c->PreviousState; +6649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ +6651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) +6652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) +6654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +6656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) +6659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +6661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +6662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; +6663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +6665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Abort DMA TX */ +6668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) +6669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +6671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); +6672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); +6677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Abort DMA RX transfer if any */ +6680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ +6681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) +6682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) +6684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +6686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) +6689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +6691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +6692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; +6693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +6695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Abort DMA RX */ +6698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) +6699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + ARM GAS /tmp/ccSHpINd.s page 119 + + +6701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); +6702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); +6707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); +6712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +6716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief I2C Error callback treatment. +6717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c I2C handle. +6718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +6719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +6720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +6721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_ABORT) +6723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +6726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +6728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->AbortCpltCallback(hi2c); +6733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else +6734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_AbortCpltCallback(hi2c); +6735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +6740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +6742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCallback(hi2c); +6747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #else +6748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_ErrorCallback(hi2c); +6749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +6754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief I2C Tx data register flush process. +6755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c I2C handle. +6756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +6757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ + ARM GAS /tmp/ccSHpINd.s page 120 + + +6758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +6759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 28 .loc 1 6759 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. +6760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If a pending TXIS flag is set */ +6761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Write a dummy data in TXDR to clear it */ +6762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + 33 .loc 1 6762 3 view .LVU1 + 34 .loc 1 6762 7 is_stmt 0 view .LVU2 + 35 0000 0368 ldr r3, [r0] + 36 0002 9A69 ldr r2, [r3, #24] + 37 .loc 1 6762 6 view .LVU3 + 38 0004 12F0020F tst r2, #2 + 39 0008 01D0 beq .L2 +6763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->TXDR = 0x00U; + 40 .loc 1 6764 5 is_stmt 1 view .LVU4 + 41 .loc 1 6764 26 is_stmt 0 view .LVU5 + 42 000a 0022 movs r2, #0 + 43 000c 9A62 str r2, [r3, #40] + 44 .L2: +6765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Flush TX register if not empty */ +6768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + 45 .loc 1 6768 3 is_stmt 1 view .LVU6 + 46 .loc 1 6768 7 is_stmt 0 view .LVU7 + 47 000e 0368 ldr r3, [r0] + 48 0010 9A69 ldr r2, [r3, #24] + 49 .loc 1 6768 6 view .LVU8 + 50 0012 12F0010F tst r2, #1 + 51 0016 03D1 bne .L1 +6769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + 52 .loc 1 6770 5 is_stmt 1 view .LVU9 + 53 0018 9A69 ldr r2, [r3, #24] + 54 001a 42F00102 orr r2, r2, #1 + 55 001e 9A61 str r2, [r3, #24] + 56 .L1: +6771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 57 .loc 1 6772 1 is_stmt 0 view .LVU10 + 58 0020 7047 bx lr + 59 .cfi_endproc + 60 .LFE206: + 62 .section .text.I2C_TransferConfig,"ax",%progbits + 63 .align 1 + 64 .syntax unified + 65 .thumb + 66 .thumb_func + 68 I2C_TransferConfig: + 69 .LVL1: + 70 .LFB218: +6773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 121 + + +6774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +6775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief DMA I2C master transmit process complete callback. +6776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hdma DMA handle +6777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +6778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +6779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +6780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); +6783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable DMA Request */ +6785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +6786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If last transfer, enable STOP interrupt */ +6788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +6789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable STOP interrupt */ +6791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +6792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* else prepare a new DMA transfer and enable TCReload interrupt */ +6794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update Buffer pointer */ +6797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr += hi2c->XferSize; +6798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the XferSize to transfer */ +6800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +6801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +6803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +6807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable the DMA stream */ +6810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, +6811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) +6812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +6815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable TC interrupts */ +6819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); +6820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +6826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief DMA I2C slave transmit process complete callback. +6827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hdma DMA handle +6828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +6829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +6830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) + ARM GAS /tmp/ccSHpINd.s page 122 + + +6831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); +6834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; +6835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) +6837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable DMA Request */ +6839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +6840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Last Byte is Transmitted */ +6842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +6843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +6844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* No specific action, Master fully manage the generation of STOP condition */ +6848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Mean that this generation can arrive at any time, at the end or during DMA process */ +6849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* So STOP condition should be manage through Interrupt treatment */ +6850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +6855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief DMA I2C master receive process complete callback. +6856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hdma DMA handle +6857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +6858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +6859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +6860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); +6863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable DMA Request */ +6865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +6866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* If last transfer, enable STOP interrupt */ +6868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +6869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable STOP interrupt */ +6871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +6872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* else prepare a new DMA transfer and enable TCReload interrupt */ +6874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update Buffer pointer */ +6877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr += hi2c->XferSize; +6878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Set the XferSize to transfer */ +6880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +6881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Errata workaround 170323 */ +6883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) +6884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = 1U; +6886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else + ARM GAS /tmp/ccSHpINd.s page 123 + + +6888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +6890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +6895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable the DMA stream */ +6898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, +6899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) +6900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +6903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable TC interrupts */ +6907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); +6908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +6914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief DMA I2C slave receive process complete callback. +6915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hdma DMA handle +6916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +6917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +6918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +6919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); +6922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; +6923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \ +6925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) +6926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable DMA Request */ +6928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +6929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +6931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +6932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +6934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* No specific action, Master fully manage the generation of STOP condition */ +6936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Mean that this generation can arrive at any time, at the end or during DMA process */ +6937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* So STOP condition should be manage through Interrupt treatment */ +6938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +6943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief DMA I2C communication error callback. +6944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hdma DMA handle + ARM GAS /tmp/ccSHpINd.s page 124 + + +6945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +6946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +6947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMAError(DMA_HandleTypeDef *hdma) +6948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t treatdmaerror = 0U; +6950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); +6952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +6954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) +6956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** treatdmaerror = 1U; +6958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +6962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) +6964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** treatdmaerror = 1U; +6966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform * +6970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U)) +6971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable Acknowledge */ +6973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +6974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +6977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +6982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief DMA I2C communication abort callback +6983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * (To be called at end of DMA Abort procedure). +6984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hdma DMA handle. +6985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +6986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +6987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +6988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); +6991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +6992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset AbortCpltCallback */ +6993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +6994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +6996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +6997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +6998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +6999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +7000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 125 + + +7002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); +7003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +7007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout. It waits +7008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * until a flag is no longer in the specified status. +7009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +7010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +7011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Flag Specifies the I2C flag to check. +7012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Status The actual Flag status (SET or RESET). +7013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Timeout Timeout duration +7014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Tickstart Tick start value +7015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +7016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +7017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagSta +7018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t Timeout, uint32_t Tickstart) +7019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) +7021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check if an error is detected */ +7023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) +7024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +7026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check for the Timeout */ +7029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +7030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +7032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) +7034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +7036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +7037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +7038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +7040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +7041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +7042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +7047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +7050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. +7051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +7052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +7053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Timeout Timeout duration +7054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Tickstart Tick start value +7055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +7056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +7057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, +7058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t Tickstart) + ARM GAS /tmp/ccSHpINd.s page 126 + + +7059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) +7061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check if an error is detected */ +7063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) +7064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +7066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check for the Timeout */ +7069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +7070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +7072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) +7074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +7076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +7077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +7078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +7080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +7081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +7083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +7088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +7091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. +7092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +7093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +7094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Timeout Timeout duration +7095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Tickstart Tick start value +7096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +7097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +7098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, +7099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t Tickstart) +7100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) +7102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check if an error is detected */ +7104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) +7105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +7107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check for the Timeout */ +7110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +7111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) +7113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +7115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + ARM GAS /tmp/ccSHpINd.s page 127 + + +7116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +7117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +7119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +7120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; +7122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_OK; +7126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +7129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. +7130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +7131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +7132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Timeout Timeout duration +7133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Tickstart Tick start value +7134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +7135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +7136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, +7137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t Tickstart) +7138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; +7140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) +7142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check if an error is detected */ +7144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) +7145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** status = HAL_ERROR; +7147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check if a STOPF is detected */ +7150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK)) +7151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check if an RXNE is pending */ +7153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Store Last receive data if any */ +7154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) +7155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Return HAL_OK */ +7157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* The Reading of data from RXDR will be done in caller function */ +7158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** status = HAL_OK; +7159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check a no-acknowledge have been detected */ +7162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) +7163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +7165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_AF; +7166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear STOP Flag */ +7168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +7169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +7171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +7172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 128 + + +7173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +7174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +7175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +7177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +7178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** status = HAL_ERROR; +7180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +7182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +7184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check for the Timeout */ +7188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) +7189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) +7191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +7193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +7194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +7196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +7197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** status = HAL_ERROR; +7199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return status; +7203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +7206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief This function handles errors detection during an I2C Communication. +7207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +7208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +7209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Timeout Timeout duration +7210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Tickstart Tick start value +7211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval HAL status +7212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +7213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Ti +7214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; +7216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t itflag = hi2c->Instance->ISR; +7217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t error_code = 0; +7218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart = Tickstart; +7219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmp1; +7220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_ModeTypeDef tmp2; +7221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) +7223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear NACKF Flag */ +7225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +7226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Wait until STOP Flag is set or timeout occurred */ +7228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* AutoEnd should be initiate after AF */ +7229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) + ARM GAS /tmp/ccSHpINd.s page 129 + + +7230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check for the Timeout */ +7232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +7233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) +7235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); +7237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmp2 = hi2c->Mode; +7238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* In case of I2C still busy, try to regenerate a STOP manually */ +7240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ +7241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmp1 != I2C_CR2_STOP) && \ +7242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmp2 != HAL_I2C_MODE_SLAVE)) +7243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Generate Stop */ +7245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; +7246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Update Tick with new reference */ +7248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tickstart = HAL_GetTick(); +7249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) +7252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check for the Timeout */ +7254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) +7255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** error_code |= HAL_I2C_ERROR_TIMEOUT; +7257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** status = HAL_ERROR; +7259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** break; +7261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* In case STOP Flag is detected, clear it */ +7268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (status == HAL_OK) +7269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear STOP Flag */ +7271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +7272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** error_code |= HAL_I2C_ERROR_AF; +7275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** status = HAL_ERROR; +7277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Refresh Content of Status register */ +7280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** itflag = hi2c->Instance->ISR; +7281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Then verify if an additional errors occurs */ +7283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check if a Bus error occurred */ +7284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) +7285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** error_code |= HAL_I2C_ERROR_BERR; + ARM GAS /tmp/ccSHpINd.s page 130 + + +7287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear BERR flag */ +7289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); +7290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** status = HAL_ERROR; +7292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check if an Over-Run/Under-Run error occurred */ +7295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) +7296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** error_code |= HAL_I2C_ERROR_OVR; +7298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear OVR flag */ +7300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); +7301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** status = HAL_ERROR; +7303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check if an Arbitration Loss error occurred */ +7306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) +7307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** error_code |= HAL_I2C_ERROR_ARLO; +7309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear ARLO flag */ +7311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); +7312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** status = HAL_ERROR; +7314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (status != HAL_OK) +7317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Flush TX register */ +7319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +7320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +7322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +7323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= error_code; +7325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +7326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +7327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Process Unlocked */ +7329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +7330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return status; +7333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +7336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag ar +7337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c I2C handle. +7338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param DevAddress Specifies the slave address to be programmed. +7339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Size Specifies the number of bytes to be programmed. +7340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * This parameter must be a value between 0 and 255. +7341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Mode New state of the I2C START condition generation. +7342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * This parameter can be one of the following values: +7343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref I2C_RELOAD_MODE Enable Reload mode . + ARM GAS /tmp/ccSHpINd.s page 131 + + +7344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. +7345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. +7346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param Request New state of the I2C START condition generation. +7347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * This parameter can be one of the following values: +7348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. +7349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). +7350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. +7351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. +7352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +7353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +7354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t +7355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t Request) +7356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 71 .loc 1 7356 1 is_stmt 1 view -0 + 72 .cfi_startproc + 73 @ args = 4, pretend = 0, frame = 0 + 74 @ frame_needed = 0, uses_anonymous_args = 0 + 75 @ link register save eliminated. + 76 .loc 1 7356 1 is_stmt 0 view .LVU12 + 77 0000 10B4 push {r4} + 78 .LCFI0: + 79 .cfi_def_cfa_offset 4 + 80 .cfi_offset 4, -4 + 81 0002 019C ldr r4, [sp, #4] +7357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ +7358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 82 .loc 1 7358 3 is_stmt 1 view .LVU13 +7359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_TRANSFER_MODE(Mode)); + 83 .loc 1 7359 3 view .LVU14 +7360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_TRANSFER_REQUEST(Request)); + 84 .loc 1 7360 3 view .LVU15 +7361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ +7363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + 85 .loc 1 7363 3 view .LVU16 + 86 .loc 1 7363 52 is_stmt 0 view .LVU17 + 87 0004 C1F30901 ubfx r1, r1, #0, #10 + 88 .LVL2: + 89 .loc 1 7363 68 view .LVU18 + 90 0008 41EA0241 orr r1, r1, r2, lsl #16 +7364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + 91 .loc 1 7364 88 view .LVU19 + 92 000c 1943 orrs r1, r1, r3 +7363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + 93 .loc 1 7363 19 view .LVU20 + 94 000e 2143 orrs r1, r1, r4 +7363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + 95 .loc 1 7363 12 view .LVU21 + 96 0010 21F00041 bic r1, r1, #-2147483648 + 97 .LVL3: +7365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); +7366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* update CR2 register */ +7368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** MODIFY_REG(hi2c->Instance->CR2, \ + 98 .loc 1 7368 3 is_stmt 1 view .LVU22 + 99 0014 0268 ldr r2, [r0] + 100 .LVL4: + ARM GAS /tmp/ccSHpINd.s page 132 + + + 101 .loc 1 7368 3 is_stmt 0 view .LVU23 + 102 0016 5368 ldr r3, [r2, #4] + 103 .LVL5: + 104 .loc 1 7368 3 view .LVU24 + 105 0018 640D lsrs r4, r4, #21 + 106 001a 04F48064 and r4, r4, #1024 + 107 001e 44F07F74 orr r4, r4, #66846720 + 108 0022 44F45834 orr r4, r4, #221184 + 109 0026 44F47F74 orr r4, r4, #1020 + 110 002a 44F00304 orr r4, r4, #3 + 111 002e 23EA0403 bic r3, r3, r4 + 112 0032 0B43 orrs r3, r3, r1 + 113 0034 5360 str r3, [r2, #4] +7369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ +7370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ +7371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_CR2_START | I2C_CR2_STOP)), tmp); +7372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 114 .loc 1 7372 1 view .LVU25 + 115 0036 5DF8044B ldr r4, [sp], #4 + 116 .LCFI1: + 117 .cfi_restore 4 + 118 .cfi_def_cfa_offset 0 + 119 .LVL6: + 120 .loc 1 7372 1 view .LVU26 + 121 003a 7047 bx lr + 122 .cfi_endproc + 123 .LFE218: + 125 .section .text.I2C_Enable_IRQ,"ax",%progbits + 126 .align 1 + 127 .syntax unified + 128 .thumb + 129 .thumb_func + 131 I2C_Enable_IRQ: + 132 .LVL7: + 133 .LFB219: +7373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +7375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Manage the enabling of Interrupts. +7376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +7377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +7378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. +7379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +7380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +7381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +7382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 134 .loc 1 7382 1 is_stmt 1 view -0 + 135 .cfi_startproc + 136 @ args = 0, pretend = 0, frame = 0 + 137 @ frame_needed = 0, uses_anonymous_args = 0 + 138 @ link register save eliminated. +7383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpisr = 0U; + 139 .loc 1 7383 3 view .LVU28 +7384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ + 140 .loc 1 7385 3 view .LVU29 + 141 .loc 1 7385 12 is_stmt 0 view .LVU30 + 142 0000 436B ldr r3, [r0, #52] + ARM GAS /tmp/ccSHpINd.s page 133 + + + 143 .loc 1 7385 6 view .LVU31 + 144 0002 234A ldr r2, .L24 + 145 0004 9342 cmp r3, r2 + 146 0006 1FD0 beq .L7 + 147 .loc 1 7385 45 discriminator 1 view .LVU32 + 148 0008 224A ldr r2, .L24+4 + 149 000a 9342 cmp r3, r2 + 150 000c 1CD0 beq .L7 +7386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ + 151 .loc 1 7386 44 view .LVU33 + 152 000e 224A ldr r2, .L24+8 + 153 0010 9342 cmp r3, r2 + 154 0012 19D0 beq .L7 +7387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (hi2c->XferISR != I2C_Mem_ISR_DMA)) +7388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + 155 .loc 1 7389 5 is_stmt 1 view .LVU34 + 156 .loc 1 7389 8 is_stmt 0 view .LVU35 + 157 0014 11F4004F tst r1, #32768 + 158 0018 11D1 bne .L18 +7383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 159 .loc 1 7383 12 view .LVU36 + 160 001a 0023 movs r3, #0 + 161 .L8: + 162 .LVL8: +7390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, STOP, NACK and ADDR interrupts */ +7392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; +7393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + 163 .loc 1 7395 5 is_stmt 1 view .LVU37 + 164 .loc 1 7395 8 is_stmt 0 view .LVU38 + 165 001c 11F0010F tst r1, #1 + 166 0020 01D0 beq .L9 +7396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK and TXI interrupts */ +7398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + 167 .loc 1 7398 7 is_stmt 1 view .LVU39 + 168 .loc 1 7398 14 is_stmt 0 view .LVU40 + 169 0022 43F0F203 orr r3, r3, #242 + 170 .LVL9: + 171 .L9: +7399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + 172 .loc 1 7401 5 is_stmt 1 view .LVU41 + 173 .loc 1 7401 8 is_stmt 0 view .LVU42 + 174 0026 11F0020F tst r1, #2 + 175 002a 01D0 beq .L10 +7402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK and RXI interrupts */ +7404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + 176 .loc 1 7404 7 is_stmt 1 view .LVU43 + 177 .loc 1 7404 14 is_stmt 0 view .LVU44 + 178 002c 43F0F403 orr r3, r3, #244 + 179 .LVL10: + ARM GAS /tmp/ccSHpINd.s page 134 + + + 180 .L10: +7405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_ERROR_IT) + 181 .loc 1 7407 5 is_stmt 1 view .LVU45 + 182 .loc 1 7407 8 is_stmt 0 view .LVU46 + 183 0030 1029 cmp r1, #16 + 184 0032 06D0 beq .L20 + 185 .L11: +7408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +7410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; +7411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_CPLT_IT) + 186 .loc 1 7413 5 is_stmt 1 view .LVU47 + 187 .loc 1 7413 8 is_stmt 0 view .LVU48 + 188 0034 2029 cmp r1, #32 + 189 0036 1BD1 bne .L12 +7414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable STOP interrupts */ +7416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI; + 190 .loc 1 7416 7 is_stmt 1 view .LVU49 + 191 .loc 1 7416 14 is_stmt 0 view .LVU50 + 192 0038 43F02003 orr r3, r3, #32 + 193 .LVL11: + 194 .loc 1 7416 14 view .LVU51 + 195 003c 18E0 b .L12 + 196 .LVL12: + 197 .L18: +7392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 198 .loc 1 7392 14 view .LVU52 + 199 003e B823 movs r3, #184 + 200 0040 ECE7 b .L8 + 201 .LVL13: + 202 .L20: +7410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 203 .loc 1 7410 7 is_stmt 1 view .LVU53 +7410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 204 .loc 1 7410 14 is_stmt 0 view .LVU54 + 205 0042 43F09003 orr r3, r3, #144 + 206 .LVL14: +7410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 207 .loc 1 7410 14 view .LVU55 + 208 0046 F5E7 b .L11 + 209 .LVL15: + 210 .L7: +7417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +7421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + 211 .loc 1 7422 5 is_stmt 1 view .LVU56 + 212 .loc 1 7422 8 is_stmt 0 view .LVU57 + 213 0048 11F4004F tst r1, #32768 + 214 004c 15D1 bne .L19 + ARM GAS /tmp/ccSHpINd.s page 135 + + +7383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 215 .loc 1 7383 12 view .LVU58 + 216 004e 0023 movs r3, #0 + 217 .L13: + 218 .LVL16: +7423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, STOP, NACK and ADDR interrupts */ +7425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; +7426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + 219 .loc 1 7428 5 is_stmt 1 view .LVU59 + 220 .loc 1 7428 8 is_stmt 0 view .LVU60 + 221 0050 11F0010F tst r1, #1 + 222 0054 01D0 beq .L14 +7429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK and TXI interrupts */ +7431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + 223 .loc 1 7431 7 is_stmt 1 view .LVU61 + 224 .loc 1 7431 14 is_stmt 0 view .LVU62 + 225 0056 43F0F203 orr r3, r3, #242 + 226 .LVL17: + 227 .L14: +7432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + 228 .loc 1 7434 5 is_stmt 1 view .LVU63 + 229 .loc 1 7434 8 is_stmt 0 view .LVU64 + 230 005a 11F0020F tst r1, #2 + 231 005e 01D0 beq .L15 +7435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK and RXI interrupts */ +7437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + 232 .loc 1 7437 7 is_stmt 1 view .LVU65 + 233 .loc 1 7437 14 is_stmt 0 view .LVU66 + 234 0060 43F0F403 orr r3, r3, #244 + 235 .LVL18: + 236 .L15: +7438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_ERROR_IT) + 237 .loc 1 7440 5 is_stmt 1 view .LVU67 + 238 .loc 1 7440 8 is_stmt 0 view .LVU68 + 239 0064 1029 cmp r1, #16 + 240 0066 0AD0 beq .L21 + 241 .L16: +7441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +7443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; +7444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_CPLT_IT) + 242 .loc 1 7446 5 is_stmt 1 view .LVU69 + 243 .loc 1 7446 8 is_stmt 0 view .LVU70 + 244 0068 2029 cmp r1, #32 + 245 006a 0BD0 beq .L22 + 246 .L17: + ARM GAS /tmp/ccSHpINd.s page 136 + + +7447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable STOP interrupts */ +7449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); +7450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_RELOAD_IT) + 247 .loc 1 7452 5 is_stmt 1 view .LVU71 + 248 .loc 1 7452 8 is_stmt 0 view .LVU72 + 249 006c 4029 cmp r1, #64 + 250 006e 0CD0 beq .L23 + 251 .L12: +7453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable TC interrupts */ +7455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI; +7456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable interrupts only at the end */ +7460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* to avoid the risk of I2C interrupt handle execution before */ +7461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* all interrupts requested done */ +7462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_ENABLE_IT(hi2c, tmpisr); + 252 .loc 1 7462 3 is_stmt 1 view .LVU73 + 253 0070 0168 ldr r1, [r0] + 254 .LVL19: + 255 .loc 1 7462 3 is_stmt 0 view .LVU74 + 256 0072 0A68 ldr r2, [r1] + 257 0074 1343 orrs r3, r3, r2 + 258 .LVL20: + 259 .loc 1 7462 3 view .LVU75 + 260 0076 0B60 str r3, [r1] +7463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 261 .loc 1 7463 1 view .LVU76 + 262 0078 7047 bx lr + 263 .LVL21: + 264 .L19: +7425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 265 .loc 1 7425 14 view .LVU77 + 266 007a B823 movs r3, #184 + 267 007c E8E7 b .L13 + 268 .LVL22: + 269 .L21: +7443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 270 .loc 1 7443 7 is_stmt 1 view .LVU78 +7443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 271 .loc 1 7443 14 is_stmt 0 view .LVU79 + 272 007e 43F09003 orr r3, r3, #144 + 273 .LVL23: +7443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 274 .loc 1 7443 14 view .LVU80 + 275 0082 F1E7 b .L16 + 276 .L22: +7449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 277 .loc 1 7449 7 is_stmt 1 view .LVU81 +7449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 278 .loc 1 7449 14 is_stmt 0 view .LVU82 + 279 0084 43F06003 orr r3, r3, #96 + 280 .LVL24: + ARM GAS /tmp/ccSHpINd.s page 137 + + +7449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 281 .loc 1 7449 14 view .LVU83 + 282 0088 F0E7 b .L17 + 283 .L23: +7455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 284 .loc 1 7455 7 is_stmt 1 view .LVU84 +7455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 285 .loc 1 7455 14 is_stmt 0 view .LVU85 + 286 008a 43F04003 orr r3, r3, #64 + 287 .LVL25: +7455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 288 .loc 1 7455 14 view .LVU86 + 289 008e EFE7 b .L12 + 290 .L25: + 291 .align 2 + 292 .L24: + 293 0090 00000000 .word I2C_Master_ISR_DMA + 294 0094 00000000 .word I2C_Slave_ISR_DMA + 295 0098 00000000 .word I2C_Mem_ISR_DMA + 296 .cfi_endproc + 297 .LFE219: + 299 .section .text.I2C_Disable_IRQ,"ax",%progbits + 300 .align 1 + 301 .syntax unified + 302 .thumb + 303 .thumb_func + 305 I2C_Disable_IRQ: + 306 .LVL26: + 307 .LFB220: +7464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +7466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Manage the disabling of Interrupts. +7467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +7468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * the configuration information for the specified I2C. +7469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. +7470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +7471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +7472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +7473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 308 .loc 1 7473 1 is_stmt 1 view -0 + 309 .cfi_startproc + 310 @ args = 0, pretend = 0, frame = 0 + 311 @ frame_needed = 0, uses_anonymous_args = 0 + 312 @ link register save eliminated. +7474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpisr = 0U; + 313 .loc 1 7474 3 view .LVU88 +7475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + 314 .loc 1 7476 3 view .LVU89 + 315 .loc 1 7476 6 is_stmt 0 view .LVU90 + 316 0000 11F0010F tst r1, #1 + 317 0004 09D0 beq .L33 +7477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable TC and TXI interrupts */ +7479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + 318 .loc 1 7479 5 is_stmt 1 view .LVU91 + 319 .LVL27: + ARM GAS /tmp/ccSHpINd.s page 138 + + +7480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + 320 .loc 1 7481 5 view .LVU92 + 321 .loc 1 7481 24 is_stmt 0 view .LVU93 + 322 0006 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 323 .loc 1 7481 8 view .LVU94 + 324 000a 03F02803 and r3, r3, #40 + 325 000e 282B cmp r3, #40 + 326 0010 01D0 beq .L36 +7482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable NACK and STOP interrupts */ +7484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 327 .loc 1 7484 14 view .LVU95 + 328 0012 F223 movs r3, #242 + 329 0014 02E0 b .L27 + 330 .L36: +7479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 331 .loc 1 7479 12 view .LVU96 + 332 0016 4223 movs r3, #66 + 333 0018 00E0 b .L27 + 334 .LVL28: + 335 .L33: +7474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 336 .loc 1 7474 12 view .LVU97 + 337 001a 0023 movs r3, #0 + 338 .LVL29: + 339 .L27: +7485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + 340 .loc 1 7488 3 is_stmt 1 view .LVU98 + 341 .loc 1 7488 6 is_stmt 0 view .LVU99 + 342 001c 11F0020F tst r1, #2 + 343 0020 09D0 beq .L28 +7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable TC and RXI interrupts */ +7491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + 344 .loc 1 7491 5 is_stmt 1 view .LVU100 + 345 .loc 1 7491 12 is_stmt 0 view .LVU101 + 346 0022 43F0440C orr ip, r3, #68 + 347 .LVL30: +7492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + 348 .loc 1 7493 5 is_stmt 1 view .LVU102 + 349 .loc 1 7493 24 is_stmt 0 view .LVU103 + 350 0026 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2 + 351 .loc 1 7493 8 view .LVU104 + 352 002a 02F02802 and r2, r2, #40 + 353 002e 282A cmp r2, #40 + 354 0030 10D0 beq .L35 +7494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable NACK and STOP interrupts */ +7496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 355 .loc 1 7496 7 is_stmt 1 view .LVU105 + 356 .loc 1 7496 14 is_stmt 0 view .LVU106 + 357 0032 43F0F403 orr r3, r3, #244 + ARM GAS /tmp/ccSHpINd.s page 139 + + + 358 .LVL31: + 359 .L28: +7497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + 360 .loc 1 7500 3 is_stmt 1 view .LVU107 + 361 .loc 1 7500 6 is_stmt 0 view .LVU108 + 362 0036 11F4004F tst r1, #32768 + 363 003a 0DD1 bne .L37 + 364 .L29: +7501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable ADDR, NACK and STOP interrupts */ +7503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; +7504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_ERROR_IT) + 365 .loc 1 7506 3 is_stmt 1 view .LVU109 + 366 .loc 1 7506 6 is_stmt 0 view .LVU110 + 367 003c 1029 cmp r1, #16 + 368 003e 0ED0 beq .L38 + 369 .L30: +7507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +7509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; +7510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_CPLT_IT) + 370 .loc 1 7512 3 is_stmt 1 view .LVU111 + 371 .loc 1 7512 6 is_stmt 0 view .LVU112 + 372 0040 2029 cmp r1, #32 + 373 0042 0FD0 beq .L39 + 374 .L31: +7513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable STOP interrupts */ +7515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI; +7516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_RELOAD_IT) + 375 .loc 1 7518 3 is_stmt 1 view .LVU113 + 376 .loc 1 7518 6 is_stmt 0 view .LVU114 + 377 0044 4029 cmp r1, #64 + 378 0046 10D0 beq .L40 + 379 .L32: +7519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Enable TC interrupts */ +7521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI; +7522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Disable interrupts only at the end */ +7525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* to avoid a breaking situation like at "t" time */ +7526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* all disable interrupts request are not done */ +7527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __HAL_I2C_DISABLE_IT(hi2c, tmpisr); + 380 .loc 1 7527 3 is_stmt 1 view .LVU115 + 381 0048 0168 ldr r1, [r0] + 382 .LVL32: + 383 .loc 1 7527 3 is_stmt 0 view .LVU116 + ARM GAS /tmp/ccSHpINd.s page 140 + + + 384 004a 0A68 ldr r2, [r1] + 385 004c 22EA0303 bic r3, r2, r3 + 386 .LVL33: + 387 .loc 1 7527 3 view .LVU117 + 388 0050 0B60 str r3, [r1] +7528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 389 .loc 1 7528 1 view .LVU118 + 390 0052 7047 bx lr + 391 .LVL34: + 392 .L35: +7491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 393 .loc 1 7491 12 view .LVU119 + 394 0054 6346 mov r3, ip + 395 0056 EEE7 b .L28 + 396 .LVL35: + 397 .L37: +7503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 398 .loc 1 7503 5 is_stmt 1 view .LVU120 +7503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 399 .loc 1 7503 12 is_stmt 0 view .LVU121 + 400 0058 43F0B803 orr r3, r3, #184 + 401 .LVL36: +7503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 402 .loc 1 7503 12 view .LVU122 + 403 005c EEE7 b .L29 + 404 .L38: +7509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 405 .loc 1 7509 5 is_stmt 1 view .LVU123 +7509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 406 .loc 1 7509 12 is_stmt 0 view .LVU124 + 407 005e 43F09003 orr r3, r3, #144 + 408 .LVL37: +7509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 409 .loc 1 7509 12 view .LVU125 + 410 0062 EDE7 b .L30 + 411 .L39: +7515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 412 .loc 1 7515 5 is_stmt 1 view .LVU126 +7515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 413 .loc 1 7515 12 is_stmt 0 view .LVU127 + 414 0064 43F02003 orr r3, r3, #32 + 415 .LVL38: +7515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 416 .loc 1 7515 12 view .LVU128 + 417 0068 ECE7 b .L31 + 418 .L40: +7521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 419 .loc 1 7521 5 is_stmt 1 view .LVU129 +7521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 420 .loc 1 7521 12 is_stmt 0 view .LVU130 + 421 006a 43F04003 orr r3, r3, #64 + 422 .LVL39: +7521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 423 .loc 1 7521 12 view .LVU131 + 424 006e EBE7 b .L32 + 425 .cfi_endproc + 426 .LFE220: + ARM GAS /tmp/ccSHpINd.s page 141 + + + 428 .section .text.I2C_ConvertOtherXferOptions,"ax",%progbits + 429 .align 1 + 430 .syntax unified + 431 .thumb + 432 .thumb_func + 434 I2C_ConvertOtherXferOptions: + 435 .LVL40: + 436 .LFB221: +7529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** +7530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** +7531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. +7532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @param hi2c I2C handle. +7533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** * @retval None +7534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** */ +7535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +7536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 437 .loc 1 7536 1 is_stmt 1 view -0 + 438 .cfi_startproc + 439 @ args = 0, pretend = 0, frame = 0 + 440 @ frame_needed = 0, uses_anonymous_args = 0 + 441 @ link register save eliminated. +7537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* if user set XferOptions to I2C_OTHER_FRAME */ +7538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* it request implicitly to generate a restart condition */ +7539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* set XferOptions to I2C_FIRST_FRAME */ +7540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferOptions == I2C_OTHER_FRAME) + 442 .loc 1 7540 3 view .LVU133 + 443 .loc 1 7540 11 is_stmt 0 view .LVU134 + 444 0000 C36A ldr r3, [r0, #44] + 445 .loc 1 7540 6 view .LVU135 + 446 0002 AA2B cmp r3, #170 + 447 0004 04D0 beq .L44 +7541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_FIRST_FRAME; +7543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ +7545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* it request implicitly to generate a restart condition */ +7546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* then generate a stop condition at the end of transfer */ +7547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ +7548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + 448 .loc 1 7548 8 is_stmt 1 view .LVU136 + 449 .loc 1 7548 16 is_stmt 0 view .LVU137 + 450 0006 C36A ldr r3, [r0, #44] + 451 .loc 1 7548 11 view .LVU138 + 452 0008 B3F52A4F cmp r3, #43520 + 453 000c 03D0 beq .L45 + 454 .L41: +7549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; +7551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** else +7553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { +7554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Nothing to do */ +7555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } +7556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 455 .loc 1 7556 1 view .LVU139 + 456 000e 7047 bx lr + 457 .L44: + ARM GAS /tmp/ccSHpINd.s page 142 + + +7542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 458 .loc 1 7542 5 is_stmt 1 view .LVU140 +7542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 459 .loc 1 7542 23 is_stmt 0 view .LVU141 + 460 0010 0023 movs r3, #0 + 461 0012 C362 str r3, [r0, #44] + 462 0014 7047 bx lr + 463 .L45: +7550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 464 .loc 1 7550 5 is_stmt 1 view .LVU142 +7550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 465 .loc 1 7550 23 is_stmt 0 view .LVU143 + 466 0016 4FF00073 mov r3, #33554432 + 467 001a C362 str r3, [r0, #44] +7555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 468 .loc 1 7555 3 is_stmt 1 view .LVU144 + 469 .loc 1 7556 1 is_stmt 0 view .LVU145 + 470 001c F7E7 b .L41 + 471 .cfi_endproc + 472 .LFE221: + 474 .section .text.I2C_IsErrorOccurred,"ax",%progbits + 475 .align 1 + 476 .syntax unified + 477 .thumb + 478 .thumb_func + 480 I2C_IsErrorOccurred: + 481 .LVL41: + 482 .LFB217: +7214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 483 .loc 1 7214 1 is_stmt 1 view -0 + 484 .cfi_startproc + 485 @ args = 0, pretend = 0, frame = 0 + 486 @ frame_needed = 0, uses_anonymous_args = 0 +7214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 487 .loc 1 7214 1 is_stmt 0 view .LVU147 + 488 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 489 .LCFI2: + 490 .cfi_def_cfa_offset 24 + 491 .cfi_offset 4, -24 + 492 .cfi_offset 5, -20 + 493 .cfi_offset 6, -16 + 494 .cfi_offset 7, -12 + 495 .cfi_offset 8, -8 + 496 .cfi_offset 14, -4 + 497 0004 0446 mov r4, r0 +7215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t itflag = hi2c->Instance->ISR; + 498 .loc 1 7215 3 is_stmt 1 view .LVU148 + 499 .LVL42: +7216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t error_code = 0; + 500 .loc 1 7216 3 view .LVU149 +7216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t error_code = 0; + 501 .loc 1 7216 27 is_stmt 0 view .LVU150 + 502 0006 0368 ldr r3, [r0] +7216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t error_code = 0; + 503 .loc 1 7216 12 view .LVU151 + 504 0008 9E69 ldr r6, [r3, #24] + 505 .LVL43: + ARM GAS /tmp/ccSHpINd.s page 143 + + +7217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart = Tickstart; + 506 .loc 1 7217 3 is_stmt 1 view .LVU152 +7218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmp1; + 507 .loc 1 7218 3 view .LVU153 +7219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_ModeTypeDef tmp2; + 508 .loc 1 7219 3 view .LVU154 +7220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 509 .loc 1 7220 3 view .LVU155 +7222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 510 .loc 1 7222 3 view .LVU156 +7222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 511 .loc 1 7222 6 is_stmt 0 view .LVU157 + 512 000a 16F01006 ands r6, r6, #16 + 513 .LVL44: +7222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 514 .loc 1 7222 6 view .LVU158 + 515 000e 7ED0 beq .L63 + 516 0010 0D46 mov r5, r1 + 517 0012 9046 mov r8, r2 +7225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 518 .loc 1 7225 5 is_stmt 1 view .LVU159 + 519 0014 1022 movs r2, #16 + 520 .LVL45: +7225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 521 .loc 1 7225 5 is_stmt 0 view .LVU160 + 522 0016 DA61 str r2, [r3, #28] +7229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 523 .loc 1 7229 5 is_stmt 1 view .LVU161 +7217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart = Tickstart; + 524 .loc 1 7217 12 is_stmt 0 view .LVU162 + 525 0018 0026 movs r6, #0 +7215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t itflag = hi2c->Instance->ISR; + 526 .loc 1 7215 21 view .LVU163 + 527 001a 3746 mov r7, r6 + 528 .LVL46: + 529 .L49: +7229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 530 .loc 1 7229 64 is_stmt 1 view .LVU164 +7229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 531 .loc 1 7229 13 is_stmt 0 view .LVU165 + 532 001c 2368 ldr r3, [r4] + 533 001e 9869 ldr r0, [r3, #24] +7229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 534 .loc 1 7229 64 view .LVU166 + 535 0020 10F0200F tst r0, #32 + 536 0024 32D1 bne .L55 +7229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 537 .loc 1 7229 64 discriminator 1 view .LVU167 + 538 0026 8FBB cbnz r7, .L55 +7232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 539 .loc 1 7232 7 is_stmt 1 view .LVU168 +7232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 540 .loc 1 7232 10 is_stmt 0 view .LVU169 + 541 0028 B5F1FF3F cmp r5, #-1 + 542 002c F6D0 beq .L49 +7234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 543 .loc 1 7234 9 is_stmt 1 view .LVU170 + ARM GAS /tmp/ccSHpINd.s page 144 + + +7234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 544 .loc 1 7234 15 is_stmt 0 view .LVU171 + 545 002e FFF7FEFF bl HAL_GetTick + 546 .LVL47: +7234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 547 .loc 1 7234 29 discriminator 1 view .LVU172 + 548 0032 A0EB0800 sub r0, r0, r8 +7234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 549 .loc 1 7234 12 discriminator 1 view .LVU173 + 550 0036 A842 cmp r0, r5 + 551 0038 01D8 bhi .L50 +7234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 552 .loc 1 7234 53 discriminator 1 view .LVU174 + 553 003a 002D cmp r5, #0 + 554 003c EED1 bne .L49 + 555 .L50: +7236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmp2 = hi2c->Mode; + 556 .loc 1 7236 11 is_stmt 1 view .LVU175 +7236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmp2 = hi2c->Mode; + 557 .loc 1 7236 33 is_stmt 0 view .LVU176 + 558 003e 2168 ldr r1, [r4] +7236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmp2 = hi2c->Mode; + 559 .loc 1 7236 43 view .LVU177 + 560 0040 4A68 ldr r2, [r1, #4] +7236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmp2 = hi2c->Mode; + 561 .loc 1 7236 16 view .LVU178 + 562 0042 02F48042 and r2, r2, #16384 + 563 .LVL48: +7237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 564 .loc 1 7237 11 is_stmt 1 view .LVU179 +7237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 565 .loc 1 7237 16 is_stmt 0 view .LVU180 + 566 0046 94F84230 ldrb r3, [r4, #66] @ zero_extendqisi2 + 567 004a DBB2 uxtb r3, r3 + 568 .LVL49: +7240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmp1 != I2C_CR2_STOP) && \ + 569 .loc 1 7240 11 is_stmt 1 view .LVU181 +7240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmp1 != I2C_CR2_STOP) && \ + 570 .loc 1 7240 16 is_stmt 0 view .LVU182 + 571 004c 8869 ldr r0, [r1, #24] +7240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmp1 != I2C_CR2_STOP) && \ + 572 .loc 1 7240 14 view .LVU183 + 573 004e 10F4004F tst r0, #32768 + 574 0052 04D0 beq .L53 +7242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 575 .loc 1 7242 21 view .LVU184 + 576 0054 203B subs r3, r3, #32 + 577 .LVL50: +7242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 578 .loc 1 7242 21 view .LVU185 + 579 0056 18BF it ne + 580 0058 0123 movne r3, #1 + 581 .LVL51: +7241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmp2 != HAL_I2C_MODE_SLAVE)) + 582 .loc 1 7241 38 view .LVU186 + 583 005a 02B9 cbnz r2, .L53 + 584 005c 73B9 cbnz r3, .L65 + ARM GAS /tmp/ccSHpINd.s page 145 + + + 585 .LVL52: + 586 .L53: +7251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 587 .loc 1 7251 59 is_stmt 1 view .LVU187 +7251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 588 .loc 1 7251 18 is_stmt 0 view .LVU188 + 589 005e 2368 ldr r3, [r4] + 590 0060 9B69 ldr r3, [r3, #24] +7251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 591 .loc 1 7251 59 view .LVU189 + 592 0062 13F0200F tst r3, #32 + 593 0066 D9D1 bne .L49 +7254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 594 .loc 1 7254 13 is_stmt 1 view .LVU190 +7254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 595 .loc 1 7254 18 is_stmt 0 view .LVU191 + 596 0068 FFF7FEFF bl HAL_GetTick + 597 .LVL53: +7254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 598 .loc 1 7254 32 discriminator 1 view .LVU192 + 599 006c A0EB0800 sub r0, r0, r8 +7254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 600 .loc 1 7254 16 discriminator 1 view .LVU193 + 601 0070 1928 cmp r0, #25 + 602 0072 F4D9 bls .L53 +7256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 603 .loc 1 7256 15 is_stmt 1 view .LVU194 +7256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 604 .loc 1 7256 26 is_stmt 0 view .LVU195 + 605 0074 46F02006 orr r6, r6, #32 + 606 .LVL54: +7258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 607 .loc 1 7258 15 is_stmt 1 view .LVU196 +7260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 608 .loc 1 7260 15 view .LVU197 +7258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 609 .loc 1 7258 22 is_stmt 0 view .LVU198 + 610 0078 0127 movs r7, #1 +7260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 611 .loc 1 7260 15 view .LVU199 + 612 007a CFE7 b .L49 + 613 .LVL55: + 614 .L65: +7245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 615 .loc 1 7245 13 is_stmt 1 view .LVU200 +7245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 616 .loc 1 7245 27 is_stmt 0 view .LVU201 + 617 007c 4B68 ldr r3, [r1, #4] +7245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 618 .loc 1 7245 33 view .LVU202 + 619 007e 43F48043 orr r3, r3, #16384 + 620 0082 4B60 str r3, [r1, #4] +7248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 621 .loc 1 7248 13 is_stmt 1 view .LVU203 +7248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 622 .loc 1 7248 25 is_stmt 0 view .LVU204 + 623 0084 FFF7FEFF bl HAL_GetTick + ARM GAS /tmp/ccSHpINd.s page 146 + + + 624 .LVL56: +7248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 625 .loc 1 7248 25 view .LVU205 + 626 0088 8046 mov r8, r0 + 627 .LVL57: +7248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 628 .loc 1 7248 25 view .LVU206 + 629 008a E8E7 b .L53 + 630 .LVL58: + 631 .L55: +7268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 632 .loc 1 7268 5 is_stmt 1 view .LVU207 +7268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 633 .loc 1 7268 8 is_stmt 0 view .LVU208 + 634 008c 0FB9 cbnz r7, .L57 +7271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 635 .loc 1 7271 7 is_stmt 1 view .LVU209 + 636 008e 2022 movs r2, #32 + 637 0090 DA61 str r2, [r3, #28] + 638 .L57: +7274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 639 .loc 1 7274 5 view .LVU210 +7274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 640 .loc 1 7274 16 is_stmt 0 view .LVU211 + 641 0092 46F00406 orr r6, r6, #4 + 642 .LVL59: +7276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 643 .loc 1 7276 5 is_stmt 1 view .LVU212 +7276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 644 .loc 1 7276 12 is_stmt 0 view .LVU213 + 645 0096 0125 movs r5, #1 + 646 .LVL60: + 647 .L47: +7280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 648 .loc 1 7280 3 is_stmt 1 view .LVU214 +7280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 649 .loc 1 7280 16 is_stmt 0 view .LVU215 + 650 0098 2268 ldr r2, [r4] +7280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 651 .loc 1 7280 10 view .LVU216 + 652 009a 9369 ldr r3, [r2, #24] + 653 .LVL61: +7284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 654 .loc 1 7284 3 is_stmt 1 view .LVU217 +7284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 655 .loc 1 7284 6 is_stmt 0 view .LVU218 + 656 009c 13F4807F tst r3, #256 + 657 00a0 05D0 beq .L58 +7286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 658 .loc 1 7286 5 is_stmt 1 view .LVU219 +7286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 659 .loc 1 7286 16 is_stmt 0 view .LVU220 + 660 00a2 46F00106 orr r6, r6, #1 + 661 .LVL62: +7289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 662 .loc 1 7289 5 is_stmt 1 view .LVU221 + 663 00a6 4FF48071 mov r1, #256 + ARM GAS /tmp/ccSHpINd.s page 147 + + + 664 00aa D161 str r1, [r2, #28] +7291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 665 .loc 1 7291 5 view .LVU222 + 666 .LVL63: +7291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 667 .loc 1 7291 12 is_stmt 0 view .LVU223 + 668 00ac 0125 movs r5, #1 + 669 .LVL64: + 670 .L58: +7295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 671 .loc 1 7295 3 is_stmt 1 view .LVU224 +7295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 672 .loc 1 7295 6 is_stmt 0 view .LVU225 + 673 00ae 13F4806F tst r3, #1024 + 674 00b2 06D0 beq .L59 +7297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 675 .loc 1 7297 5 is_stmt 1 view .LVU226 +7297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 676 .loc 1 7297 16 is_stmt 0 view .LVU227 + 677 00b4 46F00806 orr r6, r6, #8 + 678 .LVL65: +7300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 679 .loc 1 7300 5 is_stmt 1 view .LVU228 + 680 00b8 2268 ldr r2, [r4] + 681 00ba 4FF48061 mov r1, #1024 + 682 00be D161 str r1, [r2, #28] +7302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 683 .loc 1 7302 5 view .LVU229 + 684 .LVL66: +7302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 685 .loc 1 7302 12 is_stmt 0 view .LVU230 + 686 00c0 0125 movs r5, #1 + 687 .LVL67: + 688 .L59: +7306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 689 .loc 1 7306 3 is_stmt 1 view .LVU231 +7306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 690 .loc 1 7306 6 is_stmt 0 view .LVU232 + 691 00c2 13F4007F tst r3, #512 + 692 00c6 24D0 beq .L60 +7308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 693 .loc 1 7308 5 is_stmt 1 view .LVU233 +7308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 694 .loc 1 7308 16 is_stmt 0 view .LVU234 + 695 00c8 46F00206 orr r6, r6, #2 + 696 .LVL68: +7311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 697 .loc 1 7311 5 is_stmt 1 view .LVU235 + 698 00cc 2368 ldr r3, [r4] + 699 .LVL69: +7311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 700 .loc 1 7311 5 is_stmt 0 view .LVU236 + 701 00ce 4FF40072 mov r2, #512 + 702 00d2 DA61 str r2, [r3, #28] +7313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 703 .loc 1 7313 5 is_stmt 1 view .LVU237 + 704 .LVL70: + ARM GAS /tmp/ccSHpINd.s page 148 + + +7316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 705 .loc 1 7316 3 view .LVU238 +7313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 706 .loc 1 7313 12 is_stmt 0 view .LVU239 + 707 00d4 0125 movs r5, #1 + 708 .LVL71: + 709 .L61: +7319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 710 .loc 1 7319 5 is_stmt 1 view .LVU240 + 711 00d6 2046 mov r0, r4 + 712 00d8 FFF7FEFF bl I2C_Flush_TXDR + 713 .LVL72: +7322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 714 .loc 1 7322 5 view .LVU241 + 715 00dc 2268 ldr r2, [r4] + 716 00de 5368 ldr r3, [r2, #4] + 717 00e0 23F0FF73 bic r3, r3, #33423360 + 718 00e4 23F48B33 bic r3, r3, #71168 + 719 00e8 23F4FF73 bic r3, r3, #510 + 720 00ec 23F00103 bic r3, r3, #1 + 721 00f0 5360 str r3, [r2, #4] +7324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 722 .loc 1 7324 5 view .LVU242 +7324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 723 .loc 1 7324 9 is_stmt 0 view .LVU243 + 724 00f2 636C ldr r3, [r4, #68] +7324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 725 .loc 1 7324 21 view .LVU244 + 726 00f4 3343 orrs r3, r3, r6 + 727 00f6 6364 str r3, [r4, #68] +7325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 728 .loc 1 7325 5 is_stmt 1 view .LVU245 +7325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 729 .loc 1 7325 17 is_stmt 0 view .LVU246 + 730 00f8 2023 movs r3, #32 + 731 00fa 84F84130 strb r3, [r4, #65] +7326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 732 .loc 1 7326 5 is_stmt 1 view .LVU247 +7326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 733 .loc 1 7326 16 is_stmt 0 view .LVU248 + 734 00fe 0023 movs r3, #0 + 735 0100 84F84230 strb r3, [r4, #66] +7329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 736 .loc 1 7329 5 is_stmt 1 view .LVU249 +7329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 737 .loc 1 7329 5 view .LVU250 + 738 0104 84F84030 strb r3, [r4, #64] + 739 .L62: +7329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 740 .loc 1 7329 5 discriminator 1 view .LVU251 +7332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 741 .loc 1 7332 3 view .LVU252 +7333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 742 .loc 1 7333 1 is_stmt 0 view .LVU253 + 743 0108 2846 mov r0, r5 + 744 010a BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 745 .LVL73: + ARM GAS /tmp/ccSHpINd.s page 149 + + + 746 .L63: +7215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t itflag = hi2c->Instance->ISR; + 747 .loc 1 7215 21 view .LVU254 + 748 010e 0025 movs r5, #0 + 749 0110 C2E7 b .L47 + 750 .LVL74: + 751 .L60: +7316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 752 .loc 1 7316 3 is_stmt 1 view .LVU255 +7316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 753 .loc 1 7316 6 is_stmt 0 view .LVU256 + 754 0112 002D cmp r5, #0 + 755 0114 F8D0 beq .L62 + 756 0116 DEE7 b .L61 + 757 .cfi_endproc + 758 .LFE217: + 760 .section .text.I2C_WaitOnTXISFlagUntilTimeout,"ax",%progbits + 761 .align 1 + 762 .syntax unified + 763 .thumb + 764 .thumb_func + 766 I2C_WaitOnTXISFlagUntilTimeout: + 767 .LVL75: + 768 .LFB214: +7059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + 769 .loc 1 7059 1 is_stmt 1 view -0 + 770 .cfi_startproc + 771 @ args = 0, pretend = 0, frame = 0 + 772 @ frame_needed = 0, uses_anonymous_args = 0 +7059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + 773 .loc 1 7059 1 is_stmt 0 view .LVU258 + 774 0000 70B5 push {r4, r5, r6, lr} + 775 .LCFI3: + 776 .cfi_def_cfa_offset 16 + 777 .cfi_offset 4, -16 + 778 .cfi_offset 5, -12 + 779 .cfi_offset 6, -8 + 780 .cfi_offset 14, -4 + 781 0002 0446 mov r4, r0 + 782 0004 0D46 mov r5, r1 + 783 0006 1646 mov r6, r2 +7060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 784 .loc 1 7060 3 is_stmt 1 view .LVU259 + 785 .LVL76: + 786 .L69: +7060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 787 .loc 1 7060 50 view .LVU260 +7060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 788 .loc 1 7060 10 is_stmt 0 view .LVU261 + 789 0008 2368 ldr r3, [r4] + 790 000a 9B69 ldr r3, [r3, #24] +7060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 791 .loc 1 7060 50 view .LVU262 + 792 000c 13F0020F tst r3, #2 + 793 0010 22D1 bne .L74 +7063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 794 .loc 1 7063 5 is_stmt 1 view .LVU263 + ARM GAS /tmp/ccSHpINd.s page 150 + + +7063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 795 .loc 1 7063 9 is_stmt 0 view .LVU264 + 796 0012 3246 mov r2, r6 + 797 0014 2946 mov r1, r5 + 798 0016 2046 mov r0, r4 + 799 0018 FFF7FEFF bl I2C_IsErrorOccurred + 800 .LVL77: +7063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 801 .loc 1 7063 8 discriminator 1 view .LVU265 + 802 001c F0B9 cbnz r0, .L72 +7069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 803 .loc 1 7069 5 is_stmt 1 view .LVU266 +7069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 804 .loc 1 7069 8 is_stmt 0 view .LVU267 + 805 001e B5F1FF3F cmp r5, #-1 + 806 0022 F1D0 beq .L69 +7071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 807 .loc 1 7071 7 is_stmt 1 view .LVU268 +7071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 808 .loc 1 7071 13 is_stmt 0 view .LVU269 + 809 0024 FFF7FEFF bl HAL_GetTick + 810 .LVL78: +7071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 811 .loc 1 7071 27 discriminator 1 view .LVU270 + 812 0028 801B subs r0, r0, r6 +7071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 813 .loc 1 7071 10 discriminator 1 view .LVU271 + 814 002a A842 cmp r0, r5 + 815 002c 01D8 bhi .L70 +7071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 816 .loc 1 7071 51 discriminator 1 view .LVU272 + 817 002e 002D cmp r5, #0 + 818 0030 EAD1 bne .L69 + 819 .L70: +7073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 820 .loc 1 7073 9 is_stmt 1 view .LVU273 +7073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 821 .loc 1 7073 14 is_stmt 0 view .LVU274 + 822 0032 2368 ldr r3, [r4] + 823 0034 9B69 ldr r3, [r3, #24] +7073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 824 .loc 1 7073 12 view .LVU275 + 825 0036 13F0020F tst r3, #2 + 826 003a E5D1 bne .L69 +7075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 827 .loc 1 7075 11 is_stmt 1 view .LVU276 +7075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 828 .loc 1 7075 15 is_stmt 0 view .LVU277 + 829 003c 636C ldr r3, [r4, #68] +7075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 830 .loc 1 7075 27 view .LVU278 + 831 003e 43F02003 orr r3, r3, #32 + 832 0042 6364 str r3, [r4, #68] +7076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 833 .loc 1 7076 11 is_stmt 1 view .LVU279 +7076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 834 .loc 1 7076 23 is_stmt 0 view .LVU280 + ARM GAS /tmp/ccSHpINd.s page 151 + + + 835 0044 2023 movs r3, #32 + 836 0046 84F84130 strb r3, [r4, #65] +7077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 837 .loc 1 7077 11 is_stmt 1 view .LVU281 +7077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 838 .loc 1 7077 22 is_stmt 0 view .LVU282 + 839 004a 0023 movs r3, #0 + 840 004c 84F84230 strb r3, [r4, #66] +7080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 841 .loc 1 7080 11 is_stmt 1 view .LVU283 +7080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 842 .loc 1 7080 11 view .LVU284 + 843 0050 84F84030 strb r3, [r4, #64] +7080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 844 .loc 1 7080 11 view .LVU285 +7082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 845 .loc 1 7082 11 view .LVU286 +7082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 846 .loc 1 7082 18 is_stmt 0 view .LVU287 + 847 0054 0120 movs r0, #1 + 848 0056 00E0 b .L68 + 849 .L74: +7087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 850 .loc 1 7087 10 view .LVU288 + 851 0058 0020 movs r0, #0 + 852 .L68: +7088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 853 .loc 1 7088 1 view .LVU289 + 854 005a 70BD pop {r4, r5, r6, pc} + 855 .LVL79: + 856 .L72: +7065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 857 .loc 1 7065 14 view .LVU290 + 858 005c 0120 movs r0, #1 + 859 005e FCE7 b .L68 + 860 .cfi_endproc + 861 .LFE214: + 863 .section .text.I2C_WaitOnFlagUntilTimeout,"ax",%progbits + 864 .align 1 + 865 .syntax unified + 866 .thumb + 867 .thumb_func + 869 I2C_WaitOnFlagUntilTimeout: + 870 .LVL80: + 871 .LFB213: +7019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 872 .loc 1 7019 1 is_stmt 1 view -0 + 873 .cfi_startproc + 874 @ args = 4, pretend = 0, frame = 0 + 875 @ frame_needed = 0, uses_anonymous_args = 0 +7019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 876 .loc 1 7019 1 is_stmt 0 view .LVU292 + 877 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr} + 878 .LCFI4: + 879 .cfi_def_cfa_offset 32 + 880 .cfi_offset 3, -32 + 881 .cfi_offset 4, -28 + ARM GAS /tmp/ccSHpINd.s page 152 + + + 882 .cfi_offset 5, -24 + 883 .cfi_offset 6, -20 + 884 .cfi_offset 7, -16 + 885 .cfi_offset 8, -12 + 886 .cfi_offset 9, -8 + 887 .cfi_offset 14, -4 + 888 0004 0546 mov r5, r0 + 889 0006 8846 mov r8, r1 + 890 0008 1746 mov r7, r2 + 891 000a 1E46 mov r6, r3 + 892 000c DDF82090 ldr r9, [sp, #32] +7020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 893 .loc 1 7020 3 is_stmt 1 view .LVU293 + 894 .LVL81: + 895 .L78: +7020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 896 .loc 1 7020 41 view .LVU294 +7020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 897 .loc 1 7020 10 is_stmt 0 view .LVU295 + 898 0010 2B68 ldr r3, [r5] + 899 0012 9C69 ldr r4, [r3, #24] + 900 0014 38EA0404 bics r4, r8, r4 + 901 0018 0CBF ite eq + 902 001a 0123 moveq r3, #1 + 903 001c 0023 movne r3, #0 +7020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 904 .loc 1 7020 41 view .LVU296 + 905 001e BB42 cmp r3, r7 + 906 0020 27D1 bne .L83 +7023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 907 .loc 1 7023 5 is_stmt 1 view .LVU297 +7023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 908 .loc 1 7023 9 is_stmt 0 view .LVU298 + 909 0022 4A46 mov r2, r9 + 910 0024 3146 mov r1, r6 + 911 0026 2846 mov r0, r5 + 912 0028 FFF7FEFF bl I2C_IsErrorOccurred + 913 .LVL82: +7023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 914 .loc 1 7023 8 discriminator 1 view .LVU299 + 915 002c 20BB cbnz r0, .L81 +7029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 916 .loc 1 7029 5 is_stmt 1 view .LVU300 +7029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 917 .loc 1 7029 8 is_stmt 0 view .LVU301 + 918 002e B6F1FF3F cmp r6, #-1 + 919 0032 EDD0 beq .L78 +7031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 920 .loc 1 7031 7 is_stmt 1 view .LVU302 +7031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 921 .loc 1 7031 13 is_stmt 0 view .LVU303 + 922 0034 FFF7FEFF bl HAL_GetTick + 923 .LVL83: +7031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 924 .loc 1 7031 27 discriminator 1 view .LVU304 + 925 0038 A0EB0900 sub r0, r0, r9 +7031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 153 + + + 926 .loc 1 7031 10 discriminator 1 view .LVU305 + 927 003c B042 cmp r0, r6 + 928 003e 01D8 bhi .L79 +7031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 929 .loc 1 7031 51 discriminator 1 view .LVU306 + 930 0040 002E cmp r6, #0 + 931 0042 E5D1 bne .L78 + 932 .L79: +7033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 933 .loc 1 7033 9 is_stmt 1 view .LVU307 +7033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 934 .loc 1 7033 14 is_stmt 0 view .LVU308 + 935 0044 2B68 ldr r3, [r5] + 936 0046 9B69 ldr r3, [r3, #24] + 937 0048 38EA0303 bics r3, r8, r3 + 938 004c 0CBF ite eq + 939 004e 0123 moveq r3, #1 + 940 0050 0023 movne r3, #0 +7033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 941 .loc 1 7033 12 view .LVU309 + 942 0052 BB42 cmp r3, r7 + 943 0054 DCD1 bne .L78 +7035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 944 .loc 1 7035 11 is_stmt 1 view .LVU310 +7035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 945 .loc 1 7035 15 is_stmt 0 view .LVU311 + 946 0056 6B6C ldr r3, [r5, #68] +7035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 947 .loc 1 7035 27 view .LVU312 + 948 0058 43F02003 orr r3, r3, #32 + 949 005c 6B64 str r3, [r5, #68] +7036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 950 .loc 1 7036 11 is_stmt 1 view .LVU313 +7036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 951 .loc 1 7036 23 is_stmt 0 view .LVU314 + 952 005e 2023 movs r3, #32 + 953 0060 85F84130 strb r3, [r5, #65] +7037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 954 .loc 1 7037 11 is_stmt 1 view .LVU315 +7037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 955 .loc 1 7037 22 is_stmt 0 view .LVU316 + 956 0064 0023 movs r3, #0 + 957 0066 85F84230 strb r3, [r5, #66] +7040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 958 .loc 1 7040 11 is_stmt 1 view .LVU317 +7040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 959 .loc 1 7040 11 view .LVU318 + 960 006a 85F84030 strb r3, [r5, #64] +7040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 961 .loc 1 7040 11 view .LVU319 +7041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 962 .loc 1 7041 11 view .LVU320 +7041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 963 .loc 1 7041 18 is_stmt 0 view .LVU321 + 964 006e 0120 movs r0, #1 + 965 0070 00E0 b .L77 + 966 .L83: + ARM GAS /tmp/ccSHpINd.s page 154 + + +7046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 967 .loc 1 7046 10 view .LVU322 + 968 0072 0020 movs r0, #0 + 969 .L77: +7047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 970 .loc 1 7047 1 view .LVU323 + 971 0074 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} + 972 .LVL84: + 973 .L81: +7025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 974 .loc 1 7025 14 view .LVU324 + 975 0078 0120 movs r0, #1 + 976 007a FBE7 b .L77 + 977 .cfi_endproc + 978 .LFE213: + 980 .section .text.I2C_RequestMemoryWrite,"ax",%progbits + 981 .align 1 + 982 .syntax unified + 983 .thumb + 984 .thumb_func + 986 I2C_RequestMemoryWrite: + 987 .LVL85: + 988 .LFB196: +5856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRI + 989 .loc 1 5856 1 is_stmt 1 view -0 + 990 .cfi_startproc + 991 @ args = 8, pretend = 0, frame = 0 + 992 @ frame_needed = 0, uses_anonymous_args = 0 +5856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRI + 993 .loc 1 5856 1 is_stmt 0 view .LVU326 + 994 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 995 .LCFI5: + 996 .cfi_def_cfa_offset 24 + 997 .cfi_offset 4, -24 + 998 .cfi_offset 5, -20 + 999 .cfi_offset 6, -16 + 1000 .cfi_offset 7, -12 + 1001 .cfi_offset 8, -8 + 1002 .cfi_offset 14, -4 + 1003 0004 82B0 sub sp, sp, #8 + 1004 .LCFI6: + 1005 .cfi_def_cfa_offset 32 + 1006 0006 0446 mov r4, r0 + 1007 0008 9046 mov r8, r2 + 1008 000a 1D46 mov r5, r3 + 1009 000c 089E ldr r6, [sp, #32] + 1010 000e 099F ldr r7, [sp, #36] +5857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1011 .loc 1 5857 3 is_stmt 1 view .LVU327 + 1012 0010 194B ldr r3, .L93 + 1013 .LVL86: +5857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1014 .loc 1 5857 3 is_stmt 0 view .LVU328 + 1015 0012 0093 str r3, [sp] + 1016 0014 4FF08073 mov r3, #16777216 + 1017 0018 EAB2 uxtb r2, r5 + 1018 .LVL87: + ARM GAS /tmp/ccSHpINd.s page 155 + + +5857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1019 .loc 1 5857 3 view .LVU329 + 1020 001a FFF7FEFF bl I2C_TransferConfig + 1021 .LVL88: +5860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1022 .loc 1 5860 3 is_stmt 1 view .LVU330 +5860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1023 .loc 1 5860 7 is_stmt 0 view .LVU331 + 1024 001e 3A46 mov r2, r7 + 1025 0020 3146 mov r1, r6 + 1026 0022 2046 mov r0, r4 + 1027 0024 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 1028 .LVL89: +5860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1029 .loc 1 5860 6 discriminator 1 view .LVU332 + 1030 0028 F8B9 cbnz r0, .L88 +5866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1031 .loc 1 5866 3 is_stmt 1 view .LVU333 +5866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1032 .loc 1 5866 6 is_stmt 0 view .LVU334 + 1033 002a 012D cmp r5, #1 + 1034 002c 0ED1 bne .L86 +5869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1035 .loc 1 5869 5 is_stmt 1 view .LVU335 +5869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1036 .loc 1 5869 9 is_stmt 0 view .LVU336 + 1037 002e 2368 ldr r3, [r4] +5869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1038 .loc 1 5869 28 view .LVU337 + 1039 0030 5FFA88F2 uxtb r2, r8 +5869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1040 .loc 1 5869 26 view .LVU338 + 1041 0034 9A62 str r2, [r3, #40] + 1042 .L87: +5888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1043 .loc 1 5888 3 is_stmt 1 view .LVU339 +5888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1044 .loc 1 5888 7 is_stmt 0 view .LVU340 + 1045 0036 0097 str r7, [sp] + 1046 0038 3346 mov r3, r6 + 1047 003a 0022 movs r2, #0 + 1048 003c 8021 movs r1, #128 + 1049 003e 2046 mov r0, r4 + 1050 0040 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1051 .LVL90: +5888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1052 .loc 1 5888 6 discriminator 1 view .LVU341 + 1053 0044 A8B9 cbnz r0, .L92 + 1054 .L85: +5894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1055 .loc 1 5894 1 view .LVU342 + 1056 0046 02B0 add sp, sp, #8 + 1057 .LCFI7: + 1058 .cfi_remember_state + 1059 .cfi_def_cfa_offset 24 + 1060 @ sp needed + 1061 0048 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + ARM GAS /tmp/ccSHpINd.s page 156 + + + 1062 .LVL91: + 1063 .L86: + 1064 .LCFI8: + 1065 .cfi_restore_state +5875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1066 .loc 1 5875 5 is_stmt 1 view .LVU343 +5875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1067 .loc 1 5875 9 is_stmt 0 view .LVU344 + 1068 004c 2368 ldr r3, [r4] +5875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1069 .loc 1 5875 28 view .LVU345 + 1070 004e 4FEA1822 lsr r2, r8, #8 +5875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1071 .loc 1 5875 26 view .LVU346 + 1072 0052 9A62 str r2, [r3, #40] +5878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1073 .loc 1 5878 5 is_stmt 1 view .LVU347 +5878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1074 .loc 1 5878 9 is_stmt 0 view .LVU348 + 1075 0054 3A46 mov r2, r7 + 1076 0056 3146 mov r1, r6 + 1077 0058 2046 mov r0, r4 + 1078 005a FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 1079 .LVL92: +5878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1080 .loc 1 5878 8 discriminator 1 view .LVU349 + 1081 005e 30B9 cbnz r0, .L89 +5884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1082 .loc 1 5884 5 is_stmt 1 view .LVU350 +5884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1083 .loc 1 5884 9 is_stmt 0 view .LVU351 + 1084 0060 2368 ldr r3, [r4] +5884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1085 .loc 1 5884 28 view .LVU352 + 1086 0062 5FFA88F2 uxtb r2, r8 +5884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1087 .loc 1 5884 26 view .LVU353 + 1088 0066 9A62 str r2, [r3, #40] + 1089 0068 E5E7 b .L87 + 1090 .L88: +5862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1091 .loc 1 5862 12 view .LVU354 + 1092 006a 0120 movs r0, #1 + 1093 006c EBE7 b .L85 + 1094 .L89: +5880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1095 .loc 1 5880 14 view .LVU355 + 1096 006e 0120 movs r0, #1 + 1097 0070 E9E7 b .L85 + 1098 .L92: +5890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1099 .loc 1 5890 12 view .LVU356 + 1100 0072 0120 movs r0, #1 + 1101 0074 E7E7 b .L85 + 1102 .L94: + 1103 0076 00BF .align 2 + 1104 .L93: + ARM GAS /tmp/ccSHpINd.s page 157 + + + 1105 0078 00200080 .word -2147475456 + 1106 .cfi_endproc + 1107 .LFE196: + 1109 .section .text.I2C_RequestMemoryRead,"ax",%progbits + 1110 .align 1 + 1111 .syntax unified + 1112 .thumb + 1113 .thumb_func + 1115 I2C_RequestMemoryRead: + 1116 .LVL93: + 1117 .LFB197: +5911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WR + 1118 .loc 1 5911 1 is_stmt 1 view -0 + 1119 .cfi_startproc + 1120 @ args = 8, pretend = 0, frame = 0 + 1121 @ frame_needed = 0, uses_anonymous_args = 0 +5911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WR + 1122 .loc 1 5911 1 is_stmt 0 view .LVU358 + 1123 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 1124 .LCFI9: + 1125 .cfi_def_cfa_offset 24 + 1126 .cfi_offset 4, -24 + 1127 .cfi_offset 5, -20 + 1128 .cfi_offset 6, -16 + 1129 .cfi_offset 7, -12 + 1130 .cfi_offset 8, -8 + 1131 .cfi_offset 14, -4 + 1132 0004 82B0 sub sp, sp, #8 + 1133 .LCFI10: + 1134 .cfi_def_cfa_offset 32 + 1135 0006 0446 mov r4, r0 + 1136 0008 9046 mov r8, r2 + 1137 000a 1D46 mov r5, r3 + 1138 000c 089E ldr r6, [sp, #32] + 1139 000e 099F ldr r7, [sp, #36] +5912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1140 .loc 1 5912 3 is_stmt 1 view .LVU359 + 1141 0010 184B ldr r3, .L104 + 1142 .LVL94: +5912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1143 .loc 1 5912 3 is_stmt 0 view .LVU360 + 1144 0012 0093 str r3, [sp] + 1145 0014 0023 movs r3, #0 + 1146 0016 EAB2 uxtb r2, r5 + 1147 .LVL95: +5912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1148 .loc 1 5912 3 view .LVU361 + 1149 0018 FFF7FEFF bl I2C_TransferConfig + 1150 .LVL96: +5915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1151 .loc 1 5915 3 is_stmt 1 view .LVU362 +5915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1152 .loc 1 5915 7 is_stmt 0 view .LVU363 + 1153 001c 3A46 mov r2, r7 + 1154 001e 3146 mov r1, r6 + 1155 0020 2046 mov r0, r4 + 1156 0022 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + ARM GAS /tmp/ccSHpINd.s page 158 + + + 1157 .LVL97: +5915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1158 .loc 1 5915 6 discriminator 1 view .LVU364 + 1159 0026 F8B9 cbnz r0, .L99 +5921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1160 .loc 1 5921 3 is_stmt 1 view .LVU365 +5921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1161 .loc 1 5921 6 is_stmt 0 view .LVU366 + 1162 0028 012D cmp r5, #1 + 1163 002a 0ED1 bne .L97 +5924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1164 .loc 1 5924 5 is_stmt 1 view .LVU367 +5924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1165 .loc 1 5924 9 is_stmt 0 view .LVU368 + 1166 002c 2368 ldr r3, [r4] +5924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1167 .loc 1 5924 28 view .LVU369 + 1168 002e 5FFA88F2 uxtb r2, r8 +5924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1169 .loc 1 5924 26 view .LVU370 + 1170 0032 9A62 str r2, [r3, #40] + 1171 .L98: +5943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1172 .loc 1 5943 3 is_stmt 1 view .LVU371 +5943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1173 .loc 1 5943 7 is_stmt 0 view .LVU372 + 1174 0034 0097 str r7, [sp] + 1175 0036 3346 mov r3, r6 + 1176 0038 0022 movs r2, #0 + 1177 003a 4021 movs r1, #64 + 1178 003c 2046 mov r0, r4 + 1179 003e FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1180 .LVL98: +5943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1181 .loc 1 5943 6 discriminator 1 view .LVU373 + 1182 0042 A8B9 cbnz r0, .L103 + 1183 .L96: +5949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1184 .loc 1 5949 1 view .LVU374 + 1185 0044 02B0 add sp, sp, #8 + 1186 .LCFI11: + 1187 .cfi_remember_state + 1188 .cfi_def_cfa_offset 24 + 1189 @ sp needed + 1190 0046 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 1191 .LVL99: + 1192 .L97: + 1193 .LCFI12: + 1194 .cfi_restore_state +5930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1195 .loc 1 5930 5 is_stmt 1 view .LVU375 +5930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1196 .loc 1 5930 9 is_stmt 0 view .LVU376 + 1197 004a 2368 ldr r3, [r4] +5930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1198 .loc 1 5930 28 view .LVU377 + 1199 004c 4FEA1822 lsr r2, r8, #8 + ARM GAS /tmp/ccSHpINd.s page 159 + + +5930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1200 .loc 1 5930 26 view .LVU378 + 1201 0050 9A62 str r2, [r3, #40] +5933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1202 .loc 1 5933 5 is_stmt 1 view .LVU379 +5933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1203 .loc 1 5933 9 is_stmt 0 view .LVU380 + 1204 0052 3A46 mov r2, r7 + 1205 0054 3146 mov r1, r6 + 1206 0056 2046 mov r0, r4 + 1207 0058 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 1208 .LVL100: +5933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1209 .loc 1 5933 8 discriminator 1 view .LVU381 + 1210 005c 30B9 cbnz r0, .L100 +5939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1211 .loc 1 5939 5 is_stmt 1 view .LVU382 +5939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1212 .loc 1 5939 9 is_stmt 0 view .LVU383 + 1213 005e 2368 ldr r3, [r4] +5939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1214 .loc 1 5939 28 view .LVU384 + 1215 0060 5FFA88F2 uxtb r2, r8 +5939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1216 .loc 1 5939 26 view .LVU385 + 1217 0064 9A62 str r2, [r3, #40] + 1218 0066 E5E7 b .L98 + 1219 .L99: +5917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1220 .loc 1 5917 12 view .LVU386 + 1221 0068 0120 movs r0, #1 + 1222 006a EBE7 b .L96 + 1223 .L100: +5935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1224 .loc 1 5935 14 view .LVU387 + 1225 006c 0120 movs r0, #1 + 1226 006e E9E7 b .L96 + 1227 .L103: +5945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1228 .loc 1 5945 12 view .LVU388 + 1229 0070 0120 movs r0, #1 + 1230 0072 E7E7 b .L96 + 1231 .L105: + 1232 .align 2 + 1233 .L104: + 1234 0074 00200080 .word -2147475456 + 1235 .cfi_endproc + 1236 .LFE197: + 1238 .section .text.I2C_WaitOnSTOPFlagUntilTimeout,"ax",%progbits + 1239 .align 1 + 1240 .syntax unified + 1241 .thumb + 1242 .thumb_func + 1244 I2C_WaitOnSTOPFlagUntilTimeout: + 1245 .LVL101: + 1246 .LFB215: +7100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + ARM GAS /tmp/ccSHpINd.s page 160 + + + 1247 .loc 1 7100 1 is_stmt 1 view -0 + 1248 .cfi_startproc + 1249 @ args = 0, pretend = 0, frame = 0 + 1250 @ frame_needed = 0, uses_anonymous_args = 0 +7100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 1251 .loc 1 7100 1 is_stmt 0 view .LVU390 + 1252 0000 70B5 push {r4, r5, r6, lr} + 1253 .LCFI13: + 1254 .cfi_def_cfa_offset 16 + 1255 .cfi_offset 4, -16 + 1256 .cfi_offset 5, -12 + 1257 .cfi_offset 6, -8 + 1258 .cfi_offset 14, -4 + 1259 0002 0446 mov r4, r0 + 1260 0004 0D46 mov r5, r1 + 1261 0006 1646 mov r6, r2 +7101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1262 .loc 1 7101 3 is_stmt 1 view .LVU391 +7101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1263 .loc 1 7101 9 is_stmt 0 view .LVU392 + 1264 0008 04E0 b .L107 + 1265 .LVL102: + 1266 .L109: +7112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1267 .loc 1 7112 7 is_stmt 1 view .LVU393 +7112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1268 .loc 1 7112 12 is_stmt 0 view .LVU394 + 1269 000a 2368 ldr r3, [r4] + 1270 000c 9B69 ldr r3, [r3, #24] +7112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1271 .loc 1 7112 10 view .LVU395 + 1272 000e 13F0200F tst r3, #32 + 1273 0012 12D0 beq .L113 + 1274 .L107: +7101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1275 .loc 1 7101 51 is_stmt 1 view .LVU396 +7101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1276 .loc 1 7101 10 is_stmt 0 view .LVU397 + 1277 0014 2368 ldr r3, [r4] + 1278 0016 9B69 ldr r3, [r3, #24] +7101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1279 .loc 1 7101 51 view .LVU398 + 1280 0018 13F0200F tst r3, #32 + 1281 001c 1BD1 bne .L114 +7104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1282 .loc 1 7104 5 is_stmt 1 view .LVU399 +7104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1283 .loc 1 7104 9 is_stmt 0 view .LVU400 + 1284 001e 3246 mov r2, r6 + 1285 0020 2946 mov r1, r5 + 1286 0022 2046 mov r0, r4 + 1287 0024 FFF7FEFF bl I2C_IsErrorOccurred + 1288 .LVL103: +7104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1289 .loc 1 7104 8 discriminator 1 view .LVU401 + 1290 0028 B8B9 cbnz r0, .L111 +7110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 161 + + + 1291 .loc 1 7110 5 is_stmt 1 view .LVU402 +7110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1292 .loc 1 7110 11 is_stmt 0 view .LVU403 + 1293 002a FFF7FEFF bl HAL_GetTick + 1294 .LVL104: +7110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1295 .loc 1 7110 25 discriminator 1 view .LVU404 + 1296 002e 801B subs r0, r0, r6 +7110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1297 .loc 1 7110 8 discriminator 1 view .LVU405 + 1298 0030 A842 cmp r0, r5 + 1299 0032 EAD8 bhi .L109 +7110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1300 .loc 1 7110 49 discriminator 1 view .LVU406 + 1301 0034 002D cmp r5, #0 + 1302 0036 EDD1 bne .L107 + 1303 0038 E7E7 b .L109 + 1304 .L113: +7114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1305 .loc 1 7114 9 is_stmt 1 view .LVU407 +7114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1306 .loc 1 7114 13 is_stmt 0 view .LVU408 + 1307 003a 636C ldr r3, [r4, #68] +7114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1308 .loc 1 7114 25 view .LVU409 + 1309 003c 43F02003 orr r3, r3, #32 + 1310 0040 6364 str r3, [r4, #68] +7115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1311 .loc 1 7115 9 is_stmt 1 view .LVU410 +7115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1312 .loc 1 7115 21 is_stmt 0 view .LVU411 + 1313 0042 2023 movs r3, #32 + 1314 0044 84F84130 strb r3, [r4, #65] +7116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1315 .loc 1 7116 9 is_stmt 1 view .LVU412 +7116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1316 .loc 1 7116 20 is_stmt 0 view .LVU413 + 1317 0048 0023 movs r3, #0 + 1318 004a 84F84230 strb r3, [r4, #66] +7119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1319 .loc 1 7119 9 is_stmt 1 view .LVU414 +7119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1320 .loc 1 7119 9 view .LVU415 + 1321 004e 84F84030 strb r3, [r4, #64] +7119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1322 .loc 1 7119 9 view .LVU416 +7121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1323 .loc 1 7121 9 view .LVU417 +7121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1324 .loc 1 7121 16 is_stmt 0 view .LVU418 + 1325 0052 0120 movs r0, #1 + 1326 0054 00E0 b .L108 + 1327 .L114: +7125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1328 .loc 1 7125 10 view .LVU419 + 1329 0056 0020 movs r0, #0 + 1330 .L108: + ARM GAS /tmp/ccSHpINd.s page 162 + + +7126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1331 .loc 1 7126 1 view .LVU420 + 1332 0058 70BD pop {r4, r5, r6, pc} + 1333 .LVL105: + 1334 .L111: +7106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1335 .loc 1 7106 14 view .LVU421 + 1336 005a 0120 movs r0, #1 + 1337 005c FCE7 b .L108 + 1338 .cfi_endproc + 1339 .LFE215: + 1341 .section .text.I2C_WaitOnRXNEFlagUntilTimeout,"ax",%progbits + 1342 .align 1 + 1343 .syntax unified + 1344 .thumb + 1345 .thumb_func + 1347 I2C_WaitOnRXNEFlagUntilTimeout: + 1348 .LVL106: + 1349 .LFB216: +7138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 1350 .loc 1 7138 1 is_stmt 1 view -0 + 1351 .cfi_startproc + 1352 @ args = 0, pretend = 0, frame = 0 + 1353 @ frame_needed = 0, uses_anonymous_args = 0 +7138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 1354 .loc 1 7138 1 is_stmt 0 view .LVU423 + 1355 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 1356 .LCFI14: + 1357 .cfi_def_cfa_offset 24 + 1358 .cfi_offset 3, -24 + 1359 .cfi_offset 4, -20 + 1360 .cfi_offset 5, -16 + 1361 .cfi_offset 6, -12 + 1362 .cfi_offset 7, -8 + 1363 .cfi_offset 14, -4 + 1364 0002 0446 mov r4, r0 + 1365 0004 0E46 mov r6, r1 + 1366 0006 1746 mov r7, r2 +7139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1367 .loc 1 7139 3 is_stmt 1 view .LVU424 + 1368 .LVL107: +7141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1369 .loc 1 7141 3 view .LVU425 +7139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1370 .loc 1 7139 21 is_stmt 0 view .LVU426 + 1371 0008 0025 movs r5, #0 +7141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1372 .loc 1 7141 9 view .LVU427 + 1373 000a 18E0 b .L116 + 1374 .LVL108: + 1375 .L119: +7183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1376 .loc 1 7183 9 is_stmt 1 view .LVU428 +7183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1377 .loc 1 7183 25 is_stmt 0 view .LVU429 + 1378 000c 0023 movs r3, #0 + 1379 000e 6364 str r3, [r4, #68] + ARM GAS /tmp/ccSHpINd.s page 163 + + + 1380 .LVL109: + 1381 .L118: +7188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1382 .loc 1 7188 5 is_stmt 1 view .LVU430 +7188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1383 .loc 1 7188 12 is_stmt 0 view .LVU431 + 1384 0010 FFF7FEFF bl HAL_GetTick + 1385 .LVL110: +7188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1386 .loc 1 7188 26 discriminator 1 view .LVU432 + 1387 0014 C01B subs r0, r0, r7 +7188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1388 .loc 1 7188 8 discriminator 1 view .LVU433 + 1389 0016 B042 cmp r0, r6 + 1390 0018 00D8 bhi .L120 +7188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1391 .loc 1 7188 50 discriminator 2 view .LVU434 + 1392 001a 86B9 cbnz r6, .L116 + 1393 .L120: +7188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1394 .loc 1 7188 70 discriminator 3 view .LVU435 + 1395 001c 7DB9 cbnz r5, .L116 +7190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1396 .loc 1 7190 7 is_stmt 1 view .LVU436 +7190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1397 .loc 1 7190 12 is_stmt 0 view .LVU437 + 1398 001e 2368 ldr r3, [r4] + 1399 0020 9B69 ldr r3, [r3, #24] +7190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1400 .loc 1 7190 10 view .LVU438 + 1401 0022 13F0040F tst r3, #4 + 1402 0026 0AD1 bne .L116 +7192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1403 .loc 1 7192 9 is_stmt 1 view .LVU439 +7192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1404 .loc 1 7192 13 is_stmt 0 view .LVU440 + 1405 0028 636C ldr r3, [r4, #68] +7192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1406 .loc 1 7192 25 view .LVU441 + 1407 002a 43F02003 orr r3, r3, #32 + 1408 002e 6364 str r3, [r4, #68] +7193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1409 .loc 1 7193 9 is_stmt 1 view .LVU442 +7193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1410 .loc 1 7193 21 is_stmt 0 view .LVU443 + 1411 0030 2023 movs r3, #32 + 1412 0032 84F84130 strb r3, [r4, #65] +7196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1413 .loc 1 7196 9 is_stmt 1 view .LVU444 +7196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1414 .loc 1 7196 9 view .LVU445 + 1415 0036 0023 movs r3, #0 + 1416 0038 84F84030 strb r3, [r4, #64] +7196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1417 .loc 1 7196 9 view .LVU446 +7198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1418 .loc 1 7198 9 view .LVU447 + ARM GAS /tmp/ccSHpINd.s page 164 + + + 1419 .LVL111: +7198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1420 .loc 1 7198 16 is_stmt 0 view .LVU448 + 1421 003c 0125 movs r5, #1 + 1422 .LVL112: + 1423 .L116: +7141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1424 .loc 1 7141 61 is_stmt 1 view .LVU449 +7141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1425 .loc 1 7141 11 is_stmt 0 view .LVU450 + 1426 003e 2368 ldr r3, [r4] + 1427 0040 9B69 ldr r3, [r3, #24] +7141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1428 .loc 1 7141 61 view .LVU451 + 1429 0042 13F0040F tst r3, #4 + 1430 0046 2ED1 bne .L122 +7141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1431 .loc 1 7141 61 discriminator 1 view .LVU452 + 1432 0048 6DBB cbnz r5, .L122 +7144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1433 .loc 1 7144 5 is_stmt 1 view .LVU453 +7144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1434 .loc 1 7144 9 is_stmt 0 view .LVU454 + 1435 004a 3A46 mov r2, r7 + 1436 004c 3146 mov r1, r6 + 1437 004e 2046 mov r0, r4 + 1438 0050 FFF7FEFF bl I2C_IsErrorOccurred + 1439 .LVL113: +7144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1440 .loc 1 7144 8 discriminator 1 view .LVU455 + 1441 0054 00B1 cbz r0, .L117 +7146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1442 .loc 1 7146 14 view .LVU456 + 1443 0056 0125 movs r5, #1 + 1444 .LVL114: + 1445 .L117: +7150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1446 .loc 1 7150 5 is_stmt 1 view .LVU457 +7150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1447 .loc 1 7150 10 is_stmt 0 view .LVU458 + 1448 0058 2368 ldr r3, [r4] + 1449 005a 9A69 ldr r2, [r3, #24] +7150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1450 .loc 1 7150 8 view .LVU459 + 1451 005c 12F0200F tst r2, #32 + 1452 0060 D6D0 beq .L118 +7150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1453 .loc 1 7150 59 discriminator 1 view .LVU460 + 1454 0062 002D cmp r5, #0 + 1455 0064 D4D1 bne .L118 +7154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1456 .loc 1 7154 7 is_stmt 1 view .LVU461 +7154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1457 .loc 1 7154 12 is_stmt 0 view .LVU462 + 1458 0066 9A69 ldr r2, [r3, #24] +7158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1459 .loc 1 7158 9 is_stmt 1 view .LVU463 + ARM GAS /tmp/ccSHpINd.s page 165 + + +7162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1460 .loc 1 7162 7 view .LVU464 +7162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1461 .loc 1 7162 11 is_stmt 0 view .LVU465 + 1462 0068 9A69 ldr r2, [r3, #24] +7162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1463 .loc 1 7162 10 view .LVU466 + 1464 006a 12F0100F tst r2, #16 + 1465 006e CDD0 beq .L119 +7164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_AF; + 1466 .loc 1 7164 9 is_stmt 1 view .LVU467 + 1467 0070 1022 movs r2, #16 + 1468 0072 DA61 str r2, [r3, #28] +7165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1469 .loc 1 7165 9 view .LVU468 +7165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1470 .loc 1 7165 25 is_stmt 0 view .LVU469 + 1471 0074 0423 movs r3, #4 + 1472 0076 6364 str r3, [r4, #68] +7168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1473 .loc 1 7168 9 is_stmt 1 view .LVU470 + 1474 0078 2368 ldr r3, [r4] + 1475 007a 2022 movs r2, #32 + 1476 007c DA61 str r2, [r3, #28] +7171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1477 .loc 1 7171 9 view .LVU471 + 1478 007e 2168 ldr r1, [r4] + 1479 0080 4B68 ldr r3, [r1, #4] + 1480 0082 23F0FF73 bic r3, r3, #33423360 + 1481 0086 23F48B33 bic r3, r3, #71168 + 1482 008a 23F4FF73 bic r3, r3, #510 + 1483 008e 23F00103 bic r3, r3, #1 + 1484 0092 4B60 str r3, [r1, #4] +7173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1485 .loc 1 7173 9 view .LVU472 +7173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1486 .loc 1 7173 21 is_stmt 0 view .LVU473 + 1487 0094 84F84120 strb r2, [r4, #65] +7174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1488 .loc 1 7174 9 is_stmt 1 view .LVU474 +7174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1489 .loc 1 7174 20 is_stmt 0 view .LVU475 + 1490 0098 0023 movs r3, #0 + 1491 009a 84F84230 strb r3, [r4, #66] +7177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1492 .loc 1 7177 9 is_stmt 1 view .LVU476 +7177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1493 .loc 1 7177 9 view .LVU477 + 1494 009e 84F84030 strb r3, [r4, #64] +7177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1495 .loc 1 7177 9 view .LVU478 +7179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1496 .loc 1 7179 9 view .LVU479 + 1497 .LVL115: +7179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1498 .loc 1 7179 16 is_stmt 0 view .LVU480 + 1499 00a2 0125 movs r5, #1 + ARM GAS /tmp/ccSHpINd.s page 166 + + + 1500 00a4 B4E7 b .L118 + 1501 .LVL116: + 1502 .L122: +7202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1503 .loc 1 7202 3 is_stmt 1 view .LVU481 +7203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1504 .loc 1 7203 1 is_stmt 0 view .LVU482 + 1505 00a6 2846 mov r0, r5 + 1506 00a8 F8BD pop {r3, r4, r5, r6, r7, pc} +7203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1507 .loc 1 7203 1 view .LVU483 + 1508 .cfi_endproc + 1509 .LFE216: + 1511 .section .text.HAL_I2C_MspInit,"ax",%progbits + 1512 .align 1 + 1513 .weak HAL_I2C_MspInit + 1514 .syntax unified + 1515 .thumb + 1516 .thumb_func + 1518 HAL_I2C_MspInit: + 1519 .LVL117: + 1520 .LFB143: + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 1521 .loc 1 697 1 is_stmt 1 view -0 + 1522 .cfi_startproc + 1523 @ args = 0, pretend = 0, frame = 0 + 1524 @ frame_needed = 0, uses_anonymous_args = 0 + 1525 @ link register save eliminated. + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1526 .loc 1 699 3 view .LVU485 + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1527 .loc 1 704 1 is_stmt 0 view .LVU486 + 1528 0000 7047 bx lr + 1529 .cfi_endproc + 1530 .LFE143: + 1532 .section .text.HAL_I2C_Init,"ax",%progbits + 1533 .align 1 + 1534 .global HAL_I2C_Init + 1535 .syntax unified + 1536 .thumb + 1537 .thumb_func + 1539 HAL_I2C_Init: + 1540 .LVL118: + 1541 .LFB141: + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 1542 .loc 1 536 1 is_stmt 1 view -0 + 1543 .cfi_startproc + 1544 @ args = 0, pretend = 0, frame = 0 + 1545 @ frame_needed = 0, uses_anonymous_args = 0 + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1546 .loc 1 538 3 view .LVU488 + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1547 .loc 1 538 6 is_stmt 0 view .LVU489 + 1548 0000 0028 cmp r0, #0 + 1549 0002 5DD0 beq .L134 + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 1550 .loc 1 536 1 view .LVU490 + ARM GAS /tmp/ccSHpINd.s page 167 + + + 1551 0004 10B5 push {r4, lr} + 1552 .LCFI15: + 1553 .cfi_def_cfa_offset 8 + 1554 .cfi_offset 4, -8 + 1555 .cfi_offset 14, -4 + 1556 0006 0446 mov r4, r0 + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + 1557 .loc 1 544 3 is_stmt 1 view .LVU491 + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + 1558 .loc 1 545 3 view .LVU492 + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + 1559 .loc 1 546 3 view .LVU493 + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + 1560 .loc 1 547 3 view .LVU494 + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + 1561 .loc 1 548 3 view .LVU495 + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + 1562 .loc 1 549 3 view .LVU496 + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + 1563 .loc 1 550 3 view .LVU497 + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1564 .loc 1 551 3 view .LVU498 + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1565 .loc 1 553 3 view .LVU499 + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1566 .loc 1 553 11 is_stmt 0 view .LVU500 + 1567 0008 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1568 .loc 1 553 6 view .LVU501 + 1569 000c 002B cmp r3, #0 + 1570 000e 46D0 beq .L139 + 1571 .LVL119: + 1572 .L129: + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1573 .loc 1 584 3 is_stmt 1 view .LVU502 + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1574 .loc 1 584 15 is_stmt 0 view .LVU503 + 1575 0010 2423 movs r3, #36 + 1576 0012 84F84130 strb r3, [r4, #65] + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1577 .loc 1 587 3 is_stmt 1 view .LVU504 + 1578 0016 2268 ldr r2, [r4] + 1579 0018 1368 ldr r3, [r2] + 1580 001a 23F00103 bic r3, r3, #1 + 1581 001e 1360 str r3, [r2] + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1582 .loc 1 591 3 view .LVU505 + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1583 .loc 1 591 39 is_stmt 0 view .LVU506 + 1584 0020 6368 ldr r3, [r4, #4] + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1585 .loc 1 591 7 view .LVU507 + 1586 0022 2268 ldr r2, [r4] + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1587 .loc 1 591 47 view .LVU508 + 1588 0024 23F07063 bic r3, r3, #251658240 + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 168 + + + 1589 .loc 1 591 27 view .LVU509 + 1590 0028 1361 str r3, [r2, #16] + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1591 .loc 1 595 3 is_stmt 1 view .LVU510 + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1592 .loc 1 595 7 is_stmt 0 view .LVU511 + 1593 002a 2268 ldr r2, [r4] + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1594 .loc 1 595 17 view .LVU512 + 1595 002c 9368 ldr r3, [r2, #8] + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1596 .loc 1 595 24 view .LVU513 + 1597 002e 23F40043 bic r3, r3, #32768 + 1598 0032 9360 str r3, [r2, #8] + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1599 .loc 1 598 3 is_stmt 1 view .LVU514 + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1600 .loc 1 598 17 is_stmt 0 view .LVU515 + 1601 0034 E368 ldr r3, [r4, #12] + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1602 .loc 1 598 6 view .LVU516 + 1603 0036 012B cmp r3, #1 + 1604 0038 36D0 beq .L140 + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1605 .loc 1 604 5 is_stmt 1 view .LVU517 + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1606 .loc 1 604 75 is_stmt 0 view .LVU518 + 1607 003a A368 ldr r3, [r4, #8] + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1608 .loc 1 604 9 view .LVU519 + 1609 003c 2268 ldr r2, [r4] + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1610 .loc 1 604 63 view .LVU520 + 1611 003e 43F40443 orr r3, r3, #33792 + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1612 .loc 1 604 26 view .LVU521 + 1613 0042 9360 str r3, [r2, #8] + 1614 .L131: + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1615 .loc 1 609 3 is_stmt 1 view .LVU522 + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1616 .loc 1 609 17 is_stmt 0 view .LVU523 + 1617 0044 E368 ldr r3, [r4, #12] + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1618 .loc 1 609 6 view .LVU524 + 1619 0046 022B cmp r3, #2 + 1620 0048 34D0 beq .L141 + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1621 .loc 1 616 5 is_stmt 1 view .LVU525 + 1622 004a 2268 ldr r2, [r4] + 1623 004c 5368 ldr r3, [r2, #4] + 1624 004e 23F40063 bic r3, r3, #2048 + 1625 0052 5360 str r3, [r2, #4] + 1626 .L133: + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1627 .loc 1 619 3 view .LVU526 + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 169 + + + 1628 .loc 1 619 7 is_stmt 0 view .LVU527 + 1629 0054 2268 ldr r2, [r4] + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1630 .loc 1 619 17 view .LVU528 + 1631 0056 5168 ldr r1, [r2, #4] + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1632 .loc 1 619 23 view .LVU529 + 1633 0058 1A4B ldr r3, .L142 + 1634 005a 0B43 orrs r3, r3, r1 + 1635 005c 5360 str r3, [r2, #4] + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1636 .loc 1 623 3 is_stmt 1 view .LVU530 + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1637 .loc 1 623 7 is_stmt 0 view .LVU531 + 1638 005e 2268 ldr r2, [r4] + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1639 .loc 1 623 17 view .LVU532 + 1640 0060 D368 ldr r3, [r2, #12] + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1641 .loc 1 623 24 view .LVU533 + 1642 0062 23F40043 bic r3, r3, #32768 + 1643 0066 D360 str r3, [r2, #12] + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 1644 .loc 1 626 3 is_stmt 1 view .LVU534 + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 1645 .loc 1 626 37 is_stmt 0 view .LVU535 + 1646 0068 2369 ldr r3, [r4, #16] + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 1647 .loc 1 626 66 view .LVU536 + 1648 006a 6269 ldr r2, [r4, #20] + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 1649 .loc 1 626 54 view .LVU537 + 1650 006c 1343 orrs r3, r3, r2 + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1651 .loc 1 627 38 view .LVU538 + 1652 006e A169 ldr r1, [r4, #24] + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 1653 .loc 1 626 7 view .LVU539 + 1654 0070 2268 ldr r2, [r4] + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 1655 .loc 1 626 79 view .LVU540 + 1656 0072 43EA0123 orr r3, r3, r1, lsl #8 + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 1657 .loc 1 626 24 view .LVU541 + 1658 0076 D360 str r3, [r2, #12] + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1659 .loc 1 631 3 is_stmt 1 view .LVU542 + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1660 .loc 1 631 36 is_stmt 0 view .LVU543 + 1661 0078 E369 ldr r3, [r4, #28] + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1662 .loc 1 631 65 view .LVU544 + 1663 007a 216A ldr r1, [r4, #32] + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1664 .loc 1 631 7 view .LVU545 + 1665 007c 2268 ldr r2, [r4] + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 170 + + + 1666 .loc 1 631 53 view .LVU546 + 1667 007e 0B43 orrs r3, r3, r1 + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1668 .loc 1 631 23 view .LVU547 + 1669 0080 1360 str r3, [r2] + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1670 .loc 1 634 3 is_stmt 1 view .LVU548 + 1671 0082 2268 ldr r2, [r4] + 1672 0084 1368 ldr r3, [r2] + 1673 0086 43F00103 orr r3, r3, #1 + 1674 008a 1360 str r3, [r2] + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1675 .loc 1 636 3 view .LVU549 + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1676 .loc 1 636 19 is_stmt 0 view .LVU550 + 1677 008c 0020 movs r0, #0 + 1678 008e 6064 str r0, [r4, #68] + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 1679 .loc 1 637 3 is_stmt 1 view .LVU551 + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 1680 .loc 1 637 15 is_stmt 0 view .LVU552 + 1681 0090 2023 movs r3, #32 + 1682 0092 84F84130 strb r3, [r4, #65] + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1683 .loc 1 638 3 is_stmt 1 view .LVU553 + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1684 .loc 1 638 23 is_stmt 0 view .LVU554 + 1685 0096 2063 str r0, [r4, #48] + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1686 .loc 1 639 3 is_stmt 1 view .LVU555 + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1687 .loc 1 639 14 is_stmt 0 view .LVU556 + 1688 0098 84F84200 strb r0, [r4, #66] + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1689 .loc 1 641 3 is_stmt 1 view .LVU557 + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1690 .loc 1 642 1 is_stmt 0 view .LVU558 + 1691 009c 10BD pop {r4, pc} + 1692 .LVL120: + 1693 .L139: + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1694 .loc 1 556 5 is_stmt 1 view .LVU559 + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1695 .loc 1 556 16 is_stmt 0 view .LVU560 + 1696 009e 80F84030 strb r3, [r0, #64] + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 1697 .loc 1 580 5 is_stmt 1 view .LVU561 + 1698 00a2 FFF7FEFF bl HAL_I2C_MspInit + 1699 .LVL121: + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 1700 .loc 1 580 5 is_stmt 0 view .LVU562 + 1701 00a6 B3E7 b .L129 + 1702 .L140: + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1703 .loc 1 600 5 is_stmt 1 view .LVU563 + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1704 .loc 1 600 56 is_stmt 0 view .LVU564 + ARM GAS /tmp/ccSHpINd.s page 171 + + + 1705 00a8 A368 ldr r3, [r4, #8] + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1706 .loc 1 600 9 view .LVU565 + 1707 00aa 2268 ldr r2, [r4] + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1708 .loc 1 600 44 view .LVU566 + 1709 00ac 43F40043 orr r3, r3, #32768 + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1710 .loc 1 600 26 view .LVU567 + 1711 00b0 9360 str r3, [r2, #8] + 1712 00b2 C7E7 b .L131 + 1713 .L141: + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1714 .loc 1 611 5 is_stmt 1 view .LVU568 + 1715 00b4 2268 ldr r2, [r4] + 1716 00b6 5368 ldr r3, [r2, #4] + 1717 00b8 43F40063 orr r3, r3, #2048 + 1718 00bc 5360 str r3, [r2, #4] + 1719 00be C9E7 b .L133 + 1720 .LVL122: + 1721 .L134: + 1722 .LCFI16: + 1723 .cfi_def_cfa_offset 0 + 1724 .cfi_restore 4 + 1725 .cfi_restore 14 + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1726 .loc 1 540 12 is_stmt 0 view .LVU569 + 1727 00c0 0120 movs r0, #1 + 1728 .LVL123: + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1729 .loc 1 642 1 view .LVU570 + 1730 00c2 7047 bx lr + 1731 .L143: + 1732 .align 2 + 1733 .L142: + 1734 00c4 00800002 .word 33587200 + 1735 .cfi_endproc + 1736 .LFE141: + 1738 .section .text.HAL_I2C_MspDeInit,"ax",%progbits + 1739 .align 1 + 1740 .weak HAL_I2C_MspDeInit + 1741 .syntax unified + 1742 .thumb + 1743 .thumb_func + 1745 HAL_I2C_MspDeInit: + 1746 .LVL124: + 1747 .LFB144: + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 1748 .loc 1 713 1 is_stmt 1 view -0 + 1749 .cfi_startproc + 1750 @ args = 0, pretend = 0, frame = 0 + 1751 @ frame_needed = 0, uses_anonymous_args = 0 + 1752 @ link register save eliminated. + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1753 .loc 1 715 3 view .LVU572 + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1754 .loc 1 720 1 is_stmt 0 view .LVU573 + ARM GAS /tmp/ccSHpINd.s page 172 + + + 1755 0000 7047 bx lr + 1756 .cfi_endproc + 1757 .LFE144: + 1759 .section .text.HAL_I2C_DeInit,"ax",%progbits + 1760 .align 1 + 1761 .global HAL_I2C_DeInit + 1762 .syntax unified + 1763 .thumb + 1764 .thumb_func + 1766 HAL_I2C_DeInit: + 1767 .LVL125: + 1768 .LFB142: + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 1769 .loc 1 651 1 is_stmt 1 view -0 + 1770 .cfi_startproc + 1771 @ args = 0, pretend = 0, frame = 0 + 1772 @ frame_needed = 0, uses_anonymous_args = 0 + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1773 .loc 1 653 3 view .LVU575 + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1774 .loc 1 653 6 is_stmt 0 view .LVU576 + 1775 0000 A8B1 cbz r0, .L147 + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 1776 .loc 1 651 1 view .LVU577 + 1777 0002 10B5 push {r4, lr} + 1778 .LCFI17: + 1779 .cfi_def_cfa_offset 8 + 1780 .cfi_offset 4, -8 + 1781 .cfi_offset 14, -4 + 1782 0004 0446 mov r4, r0 + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1783 .loc 1 659 3 is_stmt 1 view .LVU578 + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1784 .loc 1 661 3 view .LVU579 + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1785 .loc 1 661 15 is_stmt 0 view .LVU580 + 1786 0006 2423 movs r3, #36 + 1787 0008 80F84130 strb r3, [r0, #65] + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1788 .loc 1 664 3 is_stmt 1 view .LVU581 + 1789 000c 0268 ldr r2, [r0] + 1790 000e 1368 ldr r3, [r2] + 1791 0010 23F00103 bic r3, r3, #1 + 1792 0014 1360 str r3, [r2] + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 1793 .loc 1 676 3 view .LVU582 + 1794 0016 FFF7FEFF bl HAL_I2C_MspDeInit + 1795 .LVL126: + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_RESET; + 1796 .loc 1 679 3 view .LVU583 + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_RESET; + 1797 .loc 1 679 19 is_stmt 0 view .LVU584 + 1798 001a 0020 movs r0, #0 + 1799 001c 6064 str r0, [r4, #68] + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 1800 .loc 1 680 3 is_stmt 1 view .LVU585 + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + ARM GAS /tmp/ccSHpINd.s page 173 + + + 1801 .loc 1 680 15 is_stmt 0 view .LVU586 + 1802 001e 84F84100 strb r0, [r4, #65] + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1803 .loc 1 681 3 is_stmt 1 view .LVU587 + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1804 .loc 1 681 23 is_stmt 0 view .LVU588 + 1805 0022 2063 str r0, [r4, #48] + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1806 .loc 1 682 3 is_stmt 1 view .LVU589 + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1807 .loc 1 682 14 is_stmt 0 view .LVU590 + 1808 0024 84F84200 strb r0, [r4, #66] + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1809 .loc 1 685 3 is_stmt 1 view .LVU591 + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1810 .loc 1 685 3 view .LVU592 + 1811 0028 84F84000 strb r0, [r4, #64] + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1812 .loc 1 685 3 view .LVU593 + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1813 .loc 1 687 3 view .LVU594 + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1814 .loc 1 688 1 is_stmt 0 view .LVU595 + 1815 002c 10BD pop {r4, pc} + 1816 .LVL127: + 1817 .L147: + 1818 .LCFI18: + 1819 .cfi_def_cfa_offset 0 + 1820 .cfi_restore 4 + 1821 .cfi_restore 14 + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1822 .loc 1 655 12 view .LVU596 + 1823 002e 0120 movs r0, #1 + 1824 .LVL128: + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1825 .loc 1 688 1 view .LVU597 + 1826 0030 7047 bx lr + 1827 .cfi_endproc + 1828 .LFE142: + 1830 .section .text.HAL_I2C_Master_Transmit,"ax",%progbits + 1831 .align 1 + 1832 .global HAL_I2C_Master_Transmit + 1833 .syntax unified + 1834 .thumb + 1835 .thumb_func + 1837 HAL_I2C_Master_Transmit: + 1838 .LVL129: + 1839 .LFB145: +1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; + 1840 .loc 1 1121 1 is_stmt 1 view -0 + 1841 .cfi_startproc + 1842 @ args = 4, pretend = 0, frame = 0 + 1843 @ frame_needed = 0, uses_anonymous_args = 0 +1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; + 1844 .loc 1 1121 1 is_stmt 0 view .LVU599 + 1845 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, r10, lr} + 1846 .LCFI19: + ARM GAS /tmp/ccSHpINd.s page 174 + + + 1847 .cfi_def_cfa_offset 32 + 1848 .cfi_offset 4, -32 + 1849 .cfi_offset 5, -28 + 1850 .cfi_offset 6, -24 + 1851 .cfi_offset 7, -20 + 1852 .cfi_offset 8, -16 + 1853 .cfi_offset 9, -12 + 1854 .cfi_offset 10, -8 + 1855 .cfi_offset 14, -4 + 1856 0004 82B0 sub sp, sp, #8 + 1857 .LCFI20: + 1858 .cfi_def_cfa_offset 40 + 1859 0006 0F46 mov r7, r1 + 1860 0008 0A9E ldr r6, [sp, #40] +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; + 1861 .loc 1 1122 3 is_stmt 1 view .LVU600 +1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1862 .loc 1 1123 3 view .LVU601 +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1863 .loc 1 1125 3 view .LVU602 +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1864 .loc 1 1125 11 is_stmt 0 view .LVU603 + 1865 000a 90F84110 ldrb r1, [r0, #65] @ zero_extendqisi2 + 1866 .LVL130: +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1867 .loc 1 1125 11 view .LVU604 + 1868 000e C9B2 uxtb r1, r1 +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1869 .loc 1 1125 6 view .LVU605 + 1870 0010 2029 cmp r1, #32 + 1871 0012 40F0B780 bne .L162 + 1872 0016 0446 mov r4, r0 + 1873 0018 9046 mov r8, r2 + 1874 001a 9946 mov r9, r3 +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1875 .loc 1 1128 5 is_stmt 1 view .LVU606 +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1876 .loc 1 1128 5 view .LVU607 + 1877 001c 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 1878 .LVL131: +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1879 .loc 1 1128 5 is_stmt 0 view .LVU608 + 1880 0020 012B cmp r3, #1 + 1881 0022 00F0B380 beq .L163 +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1882 .loc 1 1128 5 is_stmt 1 discriminator 2 view .LVU609 + 1883 0026 4FF0010A mov r10, #1 + 1884 002a 80F840A0 strb r10, [r0, #64] +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1885 .loc 1 1128 5 discriminator 2 view .LVU610 +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1886 .loc 1 1131 5 view .LVU611 +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1887 .loc 1 1131 17 is_stmt 0 view .LVU612 + 1888 002e FFF7FEFF bl HAL_GetTick + 1889 .LVL132: +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 175 + + + 1890 .loc 1 1131 17 view .LVU613 + 1891 0032 0546 mov r5, r0 + 1892 .LVL133: +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1893 .loc 1 1133 5 is_stmt 1 view .LVU614 +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1894 .loc 1 1133 9 is_stmt 0 view .LVU615 + 1895 0034 0090 str r0, [sp] + 1896 0036 1923 movs r3, #25 + 1897 0038 5246 mov r2, r10 + 1898 003a 4FF40041 mov r1, #32768 + 1899 003e 2046 mov r0, r4 + 1900 .LVL134: +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1901 .loc 1 1133 9 view .LVU616 + 1902 0040 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1903 .LVL135: +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1904 .loc 1 1133 8 discriminator 1 view .LVU617 + 1905 0044 0028 cmp r0, #0 + 1906 0046 40F0A380 bne .L164 +1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 1907 .loc 1 1138 5 is_stmt 1 view .LVU618 +1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 1908 .loc 1 1138 21 is_stmt 0 view .LVU619 + 1909 004a 2123 movs r3, #33 + 1910 004c 84F84130 strb r3, [r4, #65] +1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 1911 .loc 1 1139 5 is_stmt 1 view .LVU620 +1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 1912 .loc 1 1139 21 is_stmt 0 view .LVU621 + 1913 0050 1023 movs r3, #16 + 1914 0052 84F84230 strb r3, [r4, #66] +1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1915 .loc 1 1140 5 is_stmt 1 view .LVU622 +1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1916 .loc 1 1140 21 is_stmt 0 view .LVU623 + 1917 0056 0023 movs r3, #0 + 1918 0058 6364 str r3, [r4, #68] +1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 1919 .loc 1 1143 5 is_stmt 1 view .LVU624 +1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 1920 .loc 1 1143 21 is_stmt 0 view .LVU625 + 1921 005a C4F82480 str r8, [r4, #36] +1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 1922 .loc 1 1144 5 is_stmt 1 view .LVU626 +1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 1923 .loc 1 1144 21 is_stmt 0 view .LVU627 + 1924 005e A4F82A90 strh r9, [r4, #42] @ movhi +1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1925 .loc 1 1145 5 is_stmt 1 view .LVU628 +1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1926 .loc 1 1145 21 is_stmt 0 view .LVU629 + 1927 0062 6363 str r3, [r4, #52] +1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1928 .loc 1 1147 5 is_stmt 1 view .LVU630 +1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 176 + + + 1929 .loc 1 1147 13 is_stmt 0 view .LVU631 + 1930 0064 638D ldrh r3, [r4, #42] + 1931 0066 9BB2 uxth r3, r3 +1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1932 .loc 1 1147 8 view .LVU632 + 1933 0068 FF2B cmp r3, #255 + 1934 006a 1ED9 bls .L154 +1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 1935 .loc 1 1149 7 is_stmt 1 view .LVU633 +1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 1936 .loc 1 1149 22 is_stmt 0 view .LVU634 + 1937 006c FF23 movs r3, #255 + 1938 006e 2385 strh r3, [r4, #40] @ movhi +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1939 .loc 1 1150 7 is_stmt 1 view .LVU635 + 1940 .LVL136: +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1941 .loc 1 1150 16 is_stmt 0 view .LVU636 + 1942 0070 4FF08073 mov r3, #16777216 + 1943 .LVL137: + 1944 .L155: +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1945 .loc 1 1158 5 is_stmt 1 view .LVU637 +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1946 .loc 1 1158 13 is_stmt 0 view .LVU638 + 1947 0074 228D ldrh r2, [r4, #40] +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 1948 .loc 1 1158 8 view .LVU639 + 1949 0076 EAB1 cbz r2, .L156 +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1950 .loc 1 1162 7 is_stmt 1 view .LVU640 +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1951 .loc 1 1162 11 is_stmt 0 view .LVU641 + 1952 0078 2268 ldr r2, [r4] +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1953 .loc 1 1162 30 view .LVU642 + 1954 007a 98F80010 ldrb r1, [r8] @ zero_extendqisi2 +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1955 .loc 1 1162 28 view .LVU643 + 1956 007e 9162 str r1, [r2, #40] +1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1957 .loc 1 1165 7 is_stmt 1 view .LVU644 +1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1958 .loc 1 1165 11 is_stmt 0 view .LVU645 + 1959 0080 626A ldr r2, [r4, #36] +1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1960 .loc 1 1165 21 view .LVU646 + 1961 0082 0132 adds r2, r2, #1 + 1962 0084 6262 str r2, [r4, #36] +1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 1963 .loc 1 1167 7 is_stmt 1 view .LVU647 +1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 1964 .loc 1 1167 11 is_stmt 0 view .LVU648 + 1965 0086 628D ldrh r2, [r4, #42] + 1966 0088 92B2 uxth r2, r2 +1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 1967 .loc 1 1167 22 view .LVU649 + ARM GAS /tmp/ccSHpINd.s page 177 + + + 1968 008a 013A subs r2, r2, #1 + 1969 008c 92B2 uxth r2, r2 + 1970 008e 6285 strh r2, [r4, #42] @ movhi +1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1971 .loc 1 1168 7 is_stmt 1 view .LVU650 +1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1972 .loc 1 1168 11 is_stmt 0 view .LVU651 + 1973 0090 228D ldrh r2, [r4, #40] +1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 1974 .loc 1 1168 21 view .LVU652 + 1975 0092 013A subs r2, r2, #1 + 1976 0094 92B2 uxth r2, r2 + 1977 0096 2285 strh r2, [r4, #40] @ movhi +1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 1978 .loc 1 1172 7 is_stmt 1 view .LVU653 + 1979 0098 0132 adds r2, r2, #1 + 1980 009a 4149 ldr r1, .L170 + 1981 009c 0091 str r1, [sp] + 1982 009e D2B2 uxtb r2, r2 + 1983 00a0 3946 mov r1, r7 + 1984 00a2 2046 mov r0, r4 + 1985 00a4 FFF7FEFF bl I2C_TransferConfig + 1986 .LVL138: +1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 1987 .loc 1 1172 7 is_stmt 0 view .LVU654 + 1988 00a8 18E0 b .L158 + 1989 .LVL139: + 1990 .L154: +1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 1991 .loc 1 1154 7 is_stmt 1 view .LVU655 +1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 1992 .loc 1 1154 28 is_stmt 0 view .LVU656 + 1993 00aa 638D ldrh r3, [r4, #42] +1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 1994 .loc 1 1154 22 view .LVU657 + 1995 00ac 2385 strh r3, [r4, #40] @ movhi +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1996 .loc 1 1155 7 is_stmt 1 view .LVU658 + 1997 .LVL140: +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 1998 .loc 1 1155 16 is_stmt 0 view .LVU659 + 1999 00ae 4FF00073 mov r3, #33554432 + 2000 00b2 DFE7 b .L155 + 2001 .LVL141: + 2002 .L156: +1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 2003 .loc 1 1179 7 is_stmt 1 view .LVU660 + 2004 00b4 3A49 ldr r1, .L170 + 2005 00b6 0091 str r1, [sp] + 2006 00b8 D2B2 uxtb r2, r2 + 2007 00ba 3946 mov r1, r7 + 2008 00bc 2046 mov r0, r4 + 2009 00be FFF7FEFF bl I2C_TransferConfig + 2010 .LVL142: +1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 2011 .loc 1 1179 7 is_stmt 0 view .LVU661 + 2012 00c2 0BE0 b .L158 + ARM GAS /tmp/ccSHpINd.s page 178 + + + 2013 .L160: +1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 2014 .loc 1 1215 11 is_stmt 1 view .LVU662 +1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 2015 .loc 1 1215 32 is_stmt 0 view .LVU663 + 2016 00c4 628D ldrh r2, [r4, #42] + 2017 00c6 92B2 uxth r2, r2 +1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 2018 .loc 1 1215 26 view .LVU664 + 2019 00c8 2285 strh r2, [r4, #40] @ movhi +1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 2020 .loc 1 1216 11 is_stmt 1 view .LVU665 + 2021 00ca 0023 movs r3, #0 + 2022 00cc 0093 str r3, [sp] + 2023 00ce 4FF00073 mov r3, #33554432 + 2024 00d2 D2B2 uxtb r2, r2 + 2025 00d4 3946 mov r1, r7 + 2026 00d6 2046 mov r0, r4 + 2027 00d8 FFF7FEFF bl I2C_TransferConfig + 2028 .LVL143: + 2029 .L158: +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2030 .loc 1 1183 28 view .LVU666 +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2031 .loc 1 1183 16 is_stmt 0 view .LVU667 + 2032 00dc 638D ldrh r3, [r4, #42] + 2033 00de 9BB2 uxth r3, r3 +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2034 .loc 1 1183 28 view .LVU668 + 2035 00e0 002B cmp r3, #0 + 2036 00e2 33D0 beq .L169 +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2037 .loc 1 1186 7 is_stmt 1 view .LVU669 +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2038 .loc 1 1186 11 is_stmt 0 view .LVU670 + 2039 00e4 2A46 mov r2, r5 + 2040 00e6 3146 mov r1, r6 + 2041 00e8 2046 mov r0, r4 + 2042 00ea FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 2043 .LVL144: +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2044 .loc 1 1186 10 discriminator 1 view .LVU671 + 2045 00ee 0028 cmp r0, #0 + 2046 00f0 50D1 bne .L165 +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2047 .loc 1 1191 7 is_stmt 1 view .LVU672 +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2048 .loc 1 1191 35 is_stmt 0 view .LVU673 + 2049 00f2 626A ldr r2, [r4, #36] +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2050 .loc 1 1191 11 view .LVU674 + 2051 00f4 2368 ldr r3, [r4] +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2052 .loc 1 1191 30 view .LVU675 + 2053 00f6 1278 ldrb r2, [r2] @ zero_extendqisi2 +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2054 .loc 1 1191 28 view .LVU676 + ARM GAS /tmp/ccSHpINd.s page 179 + + + 2055 00f8 9A62 str r2, [r3, #40] +1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2056 .loc 1 1194 7 is_stmt 1 view .LVU677 +1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2057 .loc 1 1194 11 is_stmt 0 view .LVU678 + 2058 00fa 636A ldr r3, [r4, #36] +1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2059 .loc 1 1194 21 view .LVU679 + 2060 00fc 0133 adds r3, r3, #1 + 2061 00fe 6362 str r3, [r4, #36] +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 2062 .loc 1 1196 7 is_stmt 1 view .LVU680 +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 2063 .loc 1 1196 11 is_stmt 0 view .LVU681 + 2064 0100 638D ldrh r3, [r4, #42] + 2065 0102 9BB2 uxth r3, r3 +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 2066 .loc 1 1196 22 view .LVU682 + 2067 0104 013B subs r3, r3, #1 + 2068 0106 9BB2 uxth r3, r3 + 2069 0108 6385 strh r3, [r4, #42] @ movhi +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2070 .loc 1 1197 7 is_stmt 1 view .LVU683 +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2071 .loc 1 1197 11 is_stmt 0 view .LVU684 + 2072 010a 238D ldrh r3, [r4, #40] +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2073 .loc 1 1197 21 view .LVU685 + 2074 010c 013B subs r3, r3, #1 + 2075 010e 9BB2 uxth r3, r3 + 2076 0110 2385 strh r3, [r4, #40] @ movhi +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2077 .loc 1 1199 7 is_stmt 1 view .LVU686 +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2078 .loc 1 1199 16 is_stmt 0 view .LVU687 + 2079 0112 628D ldrh r2, [r4, #42] + 2080 0114 92B2 uxth r2, r2 +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2081 .loc 1 1199 10 view .LVU688 + 2082 0116 002A cmp r2, #0 + 2083 0118 E0D0 beq .L158 +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2084 .loc 1 1199 35 discriminator 1 view .LVU689 + 2085 011a 002B cmp r3, #0 + 2086 011c DED1 bne .L158 +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2087 .loc 1 1202 9 is_stmt 1 view .LVU690 +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2088 .loc 1 1202 13 is_stmt 0 view .LVU691 + 2089 011e 0095 str r5, [sp] + 2090 0120 3346 mov r3, r6 + 2091 0122 0022 movs r2, #0 + 2092 0124 8021 movs r1, #128 + 2093 0126 2046 mov r0, r4 + 2094 0128 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2095 .LVL145: +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 180 + + + 2096 .loc 1 1202 12 discriminator 1 view .LVU692 + 2097 012c A0BB cbnz r0, .L166 +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2098 .loc 1 1207 9 is_stmt 1 view .LVU693 +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2099 .loc 1 1207 17 is_stmt 0 view .LVU694 + 2100 012e 638D ldrh r3, [r4, #42] + 2101 0130 9BB2 uxth r3, r3 +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2102 .loc 1 1207 12 view .LVU695 + 2103 0132 FF2B cmp r3, #255 + 2104 0134 C6D9 bls .L160 +1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 2105 .loc 1 1209 11 is_stmt 1 view .LVU696 +1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 2106 .loc 1 1209 26 is_stmt 0 view .LVU697 + 2107 0136 FF22 movs r2, #255 + 2108 0138 2285 strh r2, [r4, #40] @ movhi +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 2109 .loc 1 1210 11 is_stmt 1 view .LVU698 + 2110 013a 0023 movs r3, #0 + 2111 013c 0093 str r3, [sp] + 2112 013e 4FF08073 mov r3, #16777216 + 2113 0142 3946 mov r1, r7 + 2114 0144 2046 mov r0, r4 + 2115 0146 FFF7FEFF bl I2C_TransferConfig + 2116 .LVL146: + 2117 014a C7E7 b .L158 + 2118 .L169: +1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2119 .loc 1 1224 5 view .LVU699 +1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2120 .loc 1 1224 9 is_stmt 0 view .LVU700 + 2121 014c 2A46 mov r2, r5 + 2122 014e 3146 mov r1, r6 + 2123 0150 2046 mov r0, r4 + 2124 0152 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 2125 .LVL147: +1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2126 .loc 1 1224 8 discriminator 1 view .LVU701 + 2127 0156 08BB cbnz r0, .L167 +1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2128 .loc 1 1230 5 is_stmt 1 view .LVU702 + 2129 0158 2368 ldr r3, [r4] + 2130 015a 2022 movs r2, #32 + 2131 015c DA61 str r2, [r3, #28] +1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2132 .loc 1 1233 5 view .LVU703 + 2133 015e 2168 ldr r1, [r4] + 2134 0160 4B68 ldr r3, [r1, #4] + 2135 0162 23F0FF73 bic r3, r3, #33423360 + 2136 0166 23F48B33 bic r3, r3, #71168 + 2137 016a 23F4FF73 bic r3, r3, #510 + 2138 016e 23F00103 bic r3, r3, #1 + 2139 0172 4B60 str r3, [r1, #4] +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2140 .loc 1 1235 5 view .LVU704 + ARM GAS /tmp/ccSHpINd.s page 181 + + +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2141 .loc 1 1235 17 is_stmt 0 view .LVU705 + 2142 0174 84F84120 strb r2, [r4, #65] +1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2143 .loc 1 1236 5 is_stmt 1 view .LVU706 +1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2144 .loc 1 1236 17 is_stmt 0 view .LVU707 + 2145 0178 0023 movs r3, #0 + 2146 017a 84F84230 strb r3, [r4, #66] +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2147 .loc 1 1239 5 is_stmt 1 view .LVU708 +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2148 .loc 1 1239 5 view .LVU709 + 2149 017e 84F84030 strb r3, [r4, #64] +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2150 .loc 1 1239 5 view .LVU710 +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2151 .loc 1 1241 5 view .LVU711 +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2152 .loc 1 1241 12 is_stmt 0 view .LVU712 + 2153 0182 00E0 b .L153 + 2154 .LVL148: + 2155 .L162: +1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2156 .loc 1 1245 12 view .LVU713 + 2157 0184 0220 movs r0, #2 + 2158 .LVL149: + 2159 .L153: +1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2160 .loc 1 1247 1 view .LVU714 + 2161 0186 02B0 add sp, sp, #8 + 2162 .LCFI21: + 2163 .cfi_remember_state + 2164 .cfi_def_cfa_offset 32 + 2165 @ sp needed + 2166 0188 BDE8F087 pop {r4, r5, r6, r7, r8, r9, r10, pc} + 2167 .LVL150: + 2168 .L163: + 2169 .LCFI22: + 2170 .cfi_restore_state +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2171 .loc 1 1128 5 discriminator 1 view .LVU715 + 2172 018c 0220 movs r0, #2 + 2173 .LVL151: +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2174 .loc 1 1128 5 discriminator 1 view .LVU716 + 2175 018e FAE7 b .L153 + 2176 .LVL152: + 2177 .L164: +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2178 .loc 1 1135 14 view .LVU717 + 2179 0190 0120 movs r0, #1 + 2180 0192 F8E7 b .L153 + 2181 .LVL153: + 2182 .L165: +1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2183 .loc 1 1188 16 view .LVU718 + ARM GAS /tmp/ccSHpINd.s page 182 + + + 2184 0194 0120 movs r0, #1 + 2185 0196 F6E7 b .L153 + 2186 .L166: +1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2187 .loc 1 1204 18 view .LVU719 + 2188 0198 0120 movs r0, #1 + 2189 019a F4E7 b .L153 + 2190 .L167: +1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2191 .loc 1 1226 14 view .LVU720 + 2192 019c 0120 movs r0, #1 + 2193 019e F2E7 b .L153 + 2194 .L171: + 2195 .align 2 + 2196 .L170: + 2197 01a0 00200080 .word -2147475456 + 2198 .cfi_endproc + 2199 .LFE145: + 2201 .section .text.HAL_I2C_Master_Receive,"ax",%progbits + 2202 .align 1 + 2203 .global HAL_I2C_Master_Receive + 2204 .syntax unified + 2205 .thumb + 2206 .thumb_func + 2208 HAL_I2C_Master_Receive: + 2209 .LVL154: + 2210 .LFB146: +1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; + 2211 .loc 1 1262 1 is_stmt 1 view -0 + 2212 .cfi_startproc + 2213 @ args = 4, pretend = 0, frame = 0 + 2214 @ frame_needed = 0, uses_anonymous_args = 0 +1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; + 2215 .loc 1 1262 1 is_stmt 0 view .LVU722 + 2216 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, r10, lr} + 2217 .LCFI23: + 2218 .cfi_def_cfa_offset 32 + 2219 .cfi_offset 4, -32 + 2220 .cfi_offset 5, -28 + 2221 .cfi_offset 6, -24 + 2222 .cfi_offset 7, -20 + 2223 .cfi_offset 8, -16 + 2224 .cfi_offset 9, -12 + 2225 .cfi_offset 10, -8 + 2226 .cfi_offset 14, -4 + 2227 0004 82B0 sub sp, sp, #8 + 2228 .LCFI24: + 2229 .cfi_def_cfa_offset 40 + 2230 0006 0F46 mov r7, r1 + 2231 0008 0A9E ldr r6, [sp, #40] +1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2232 .loc 1 1263 3 is_stmt 1 view .LVU723 +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2233 .loc 1 1265 3 view .LVU724 +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2234 .loc 1 1265 11 is_stmt 0 view .LVU725 + 2235 000a 90F84110 ldrb r1, [r0, #65] @ zero_extendqisi2 + ARM GAS /tmp/ccSHpINd.s page 183 + + + 2236 .LVL155: +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2237 .loc 1 1265 11 view .LVU726 + 2238 000e C9B2 uxtb r1, r1 +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2239 .loc 1 1265 6 view .LVU727 + 2240 0010 2029 cmp r1, #32 + 2241 0012 40F0A380 bne .L180 + 2242 0016 0446 mov r4, r0 + 2243 0018 9046 mov r8, r2 + 2244 001a 9946 mov r9, r3 +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2245 .loc 1 1268 5 is_stmt 1 view .LVU728 +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2246 .loc 1 1268 5 view .LVU729 + 2247 001c 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 2248 .LVL156: +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2249 .loc 1 1268 5 is_stmt 0 view .LVU730 + 2250 0020 012B cmp r3, #1 + 2251 0022 00F09F80 beq .L181 +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2252 .loc 1 1268 5 is_stmt 1 discriminator 2 view .LVU731 + 2253 0026 4FF0010A mov r10, #1 + 2254 002a 80F840A0 strb r10, [r0, #64] +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2255 .loc 1 1268 5 discriminator 2 view .LVU732 +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2256 .loc 1 1271 5 view .LVU733 +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2257 .loc 1 1271 17 is_stmt 0 view .LVU734 + 2258 002e FFF7FEFF bl HAL_GetTick + 2259 .LVL157: +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2260 .loc 1 1271 17 view .LVU735 + 2261 0032 0546 mov r5, r0 + 2262 .LVL158: +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2263 .loc 1 1273 5 is_stmt 1 view .LVU736 +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2264 .loc 1 1273 9 is_stmt 0 view .LVU737 + 2265 0034 0090 str r0, [sp] + 2266 0036 1923 movs r3, #25 + 2267 0038 5246 mov r2, r10 + 2268 003a 4FF40041 mov r1, #32768 + 2269 003e 2046 mov r0, r4 + 2270 .LVL159: +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2271 .loc 1 1273 9 view .LVU738 + 2272 0040 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2273 .LVL160: +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2274 .loc 1 1273 8 discriminator 1 view .LVU739 + 2275 0044 0028 cmp r0, #0 + 2276 0046 40F08F80 bne .L182 +1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 2277 .loc 1 1278 5 is_stmt 1 view .LVU740 + ARM GAS /tmp/ccSHpINd.s page 184 + + +1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 2278 .loc 1 1278 21 is_stmt 0 view .LVU741 + 2279 004a 2223 movs r3, #34 + 2280 004c 84F84130 strb r3, [r4, #65] +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2281 .loc 1 1279 5 is_stmt 1 view .LVU742 +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2282 .loc 1 1279 21 is_stmt 0 view .LVU743 + 2283 0050 1023 movs r3, #16 + 2284 0052 84F84230 strb r3, [r4, #66] +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2285 .loc 1 1280 5 is_stmt 1 view .LVU744 +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2286 .loc 1 1280 21 is_stmt 0 view .LVU745 + 2287 0056 0023 movs r3, #0 + 2288 0058 6364 str r3, [r4, #68] +1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 2289 .loc 1 1283 5 is_stmt 1 view .LVU746 +1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 2290 .loc 1 1283 21 is_stmt 0 view .LVU747 + 2291 005a C4F82480 str r8, [r4, #36] +1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2292 .loc 1 1284 5 is_stmt 1 view .LVU748 +1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2293 .loc 1 1284 21 is_stmt 0 view .LVU749 + 2294 005e A4F82A90 strh r9, [r4, #42] @ movhi +1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2295 .loc 1 1285 5 is_stmt 1 view .LVU750 +1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2296 .loc 1 1285 21 is_stmt 0 view .LVU751 + 2297 0062 6363 str r3, [r4, #52] +1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2298 .loc 1 1289 5 is_stmt 1 view .LVU752 +1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2299 .loc 1 1289 13 is_stmt 0 view .LVU753 + 2300 0064 638D ldrh r3, [r4, #42] + 2301 0066 9BB2 uxth r3, r3 +1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2302 .loc 1 1289 8 view .LVU754 + 2303 0068 FF2B cmp r3, #255 + 2304 006a 0BD9 bls .L174 +1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 2305 .loc 1 1291 7 is_stmt 1 view .LVU755 +1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 2306 .loc 1 1291 22 is_stmt 0 view .LVU756 + 2307 006c 5246 mov r2, r10 + 2308 006e A4F828A0 strh r10, [r4, #40] @ movhi +1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 2309 .loc 1 1292 7 is_stmt 1 view .LVU757 + 2310 0072 414B ldr r3, .L188 + 2311 0074 0093 str r3, [sp] + 2312 0076 4FF08073 mov r3, #16777216 + 2313 007a 3946 mov r1, r7 + 2314 007c 2046 mov r0, r4 + 2315 007e FFF7FEFF bl I2C_TransferConfig + 2316 .LVL161: + 2317 0082 18E0 b .L176 + ARM GAS /tmp/ccSHpINd.s page 185 + + + 2318 .L174: +1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 2319 .loc 1 1297 7 view .LVU758 +1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 2320 .loc 1 1297 28 is_stmt 0 view .LVU759 + 2321 0084 628D ldrh r2, [r4, #42] + 2322 0086 92B2 uxth r2, r2 +1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 2323 .loc 1 1297 22 view .LVU760 + 2324 0088 2285 strh r2, [r4, #40] @ movhi +1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 2325 .loc 1 1298 7 is_stmt 1 view .LVU761 + 2326 008a 3B4B ldr r3, .L188 + 2327 008c 0093 str r3, [sp] + 2328 008e 4FF00073 mov r3, #33554432 + 2329 0092 D2B2 uxtb r2, r2 + 2330 0094 3946 mov r1, r7 + 2331 0096 2046 mov r0, r4 + 2332 0098 FFF7FEFF bl I2C_TransferConfig + 2333 .LVL162: + 2334 009c 0BE0 b .L176 + 2335 .L178: +1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 2336 .loc 1 1335 11 view .LVU762 +1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 2337 .loc 1 1335 32 is_stmt 0 view .LVU763 + 2338 009e 628D ldrh r2, [r4, #42] + 2339 00a0 92B2 uxth r2, r2 +1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 2340 .loc 1 1335 26 view .LVU764 + 2341 00a2 2285 strh r2, [r4, #40] @ movhi +1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 2342 .loc 1 1336 11 is_stmt 1 view .LVU765 + 2343 00a4 0023 movs r3, #0 + 2344 00a6 0093 str r3, [sp] + 2345 00a8 4FF00073 mov r3, #33554432 + 2346 00ac D2B2 uxtb r2, r2 + 2347 00ae 3946 mov r1, r7 + 2348 00b0 2046 mov r0, r4 + 2349 00b2 FFF7FEFF bl I2C_TransferConfig + 2350 .LVL163: + 2351 .L176: +1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2352 .loc 1 1302 28 view .LVU766 +1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2353 .loc 1 1302 16 is_stmt 0 view .LVU767 + 2354 00b6 638D ldrh r3, [r4, #42] + 2355 00b8 9BB2 uxth r3, r3 +1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2356 .loc 1 1302 28 view .LVU768 + 2357 00ba 002B cmp r3, #0 + 2358 00bc 32D0 beq .L187 +1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2359 .loc 1 1305 7 is_stmt 1 view .LVU769 +1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2360 .loc 1 1305 11 is_stmt 0 view .LVU770 + 2361 00be 2A46 mov r2, r5 + ARM GAS /tmp/ccSHpINd.s page 186 + + + 2362 00c0 3146 mov r1, r6 + 2363 00c2 2046 mov r0, r4 + 2364 00c4 FFF7FEFF bl I2C_WaitOnRXNEFlagUntilTimeout + 2365 .LVL164: +1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2366 .loc 1 1305 10 discriminator 1 view .LVU771 + 2367 00c8 0028 cmp r0, #0 + 2368 00ca 4FD1 bne .L183 +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2369 .loc 1 1311 7 is_stmt 1 view .LVU772 +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2370 .loc 1 1311 38 is_stmt 0 view .LVU773 + 2371 00cc 2368 ldr r3, [r4] +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2372 .loc 1 1311 48 view .LVU774 + 2373 00ce 5A6A ldr r2, [r3, #36] +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2374 .loc 1 1311 12 view .LVU775 + 2375 00d0 636A ldr r3, [r4, #36] +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2376 .loc 1 1311 23 view .LVU776 + 2377 00d2 1A70 strb r2, [r3] +1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2378 .loc 1 1314 7 is_stmt 1 view .LVU777 +1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2379 .loc 1 1314 11 is_stmt 0 view .LVU778 + 2380 00d4 636A ldr r3, [r4, #36] +1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2381 .loc 1 1314 21 view .LVU779 + 2382 00d6 0133 adds r3, r3, #1 + 2383 00d8 6362 str r3, [r4, #36] +1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 2384 .loc 1 1316 7 is_stmt 1 view .LVU780 +1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 2385 .loc 1 1316 11 is_stmt 0 view .LVU781 + 2386 00da 228D ldrh r2, [r4, #40] +1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 2387 .loc 1 1316 21 view .LVU782 + 2388 00dc 013A subs r2, r2, #1 + 2389 00de 92B2 uxth r2, r2 + 2390 00e0 2285 strh r2, [r4, #40] @ movhi +1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2391 .loc 1 1317 7 is_stmt 1 view .LVU783 +1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2392 .loc 1 1317 11 is_stmt 0 view .LVU784 + 2393 00e2 638D ldrh r3, [r4, #42] + 2394 00e4 9BB2 uxth r3, r3 +1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2395 .loc 1 1317 22 view .LVU785 + 2396 00e6 013B subs r3, r3, #1 + 2397 00e8 9BB2 uxth r3, r3 + 2398 00ea 6385 strh r3, [r4, #42] @ movhi +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2399 .loc 1 1319 7 is_stmt 1 view .LVU786 +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2400 .loc 1 1319 16 is_stmt 0 view .LVU787 + 2401 00ec 638D ldrh r3, [r4, #42] + ARM GAS /tmp/ccSHpINd.s page 187 + + + 2402 00ee 9BB2 uxth r3, r3 +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2403 .loc 1 1319 10 view .LVU788 + 2404 00f0 002B cmp r3, #0 + 2405 00f2 E0D0 beq .L176 +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2406 .loc 1 1319 35 discriminator 1 view .LVU789 + 2407 00f4 002A cmp r2, #0 + 2408 00f6 DED1 bne .L176 +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2409 .loc 1 1322 9 is_stmt 1 view .LVU790 +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2410 .loc 1 1322 13 is_stmt 0 view .LVU791 + 2411 00f8 0095 str r5, [sp] + 2412 00fa 3346 mov r3, r6 + 2413 00fc 8021 movs r1, #128 + 2414 00fe 2046 mov r0, r4 + 2415 0100 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2416 .LVL165: +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2417 .loc 1 1322 12 discriminator 1 view .LVU792 + 2418 0104 A0BB cbnz r0, .L184 +1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2419 .loc 1 1327 9 is_stmt 1 view .LVU793 +1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2420 .loc 1 1327 17 is_stmt 0 view .LVU794 + 2421 0106 638D ldrh r3, [r4, #42] + 2422 0108 9BB2 uxth r3, r3 +1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2423 .loc 1 1327 12 view .LVU795 + 2424 010a FF2B cmp r3, #255 + 2425 010c C7D9 bls .L178 +1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 2426 .loc 1 1329 11 is_stmt 1 view .LVU796 +1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 2427 .loc 1 1329 26 is_stmt 0 view .LVU797 + 2428 010e FF22 movs r2, #255 + 2429 0110 2285 strh r2, [r4, #40] @ movhi +1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 2430 .loc 1 1330 11 is_stmt 1 view .LVU798 + 2431 0112 0023 movs r3, #0 + 2432 0114 0093 str r3, [sp] + 2433 0116 4FF08073 mov r3, #16777216 + 2434 011a 3946 mov r1, r7 + 2435 011c 2046 mov r0, r4 + 2436 011e FFF7FEFF bl I2C_TransferConfig + 2437 .LVL166: + 2438 0122 C8E7 b .L176 + 2439 .L187: +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2440 .loc 1 1344 5 view .LVU799 +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2441 .loc 1 1344 9 is_stmt 0 view .LVU800 + 2442 0124 2A46 mov r2, r5 + 2443 0126 3146 mov r1, r6 + 2444 0128 2046 mov r0, r4 + 2445 012a FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + ARM GAS /tmp/ccSHpINd.s page 188 + + + 2446 .LVL167: +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2447 .loc 1 1344 8 discriminator 1 view .LVU801 + 2448 012e 08BB cbnz r0, .L185 +1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2449 .loc 1 1350 5 is_stmt 1 view .LVU802 + 2450 0130 2368 ldr r3, [r4] + 2451 0132 2022 movs r2, #32 + 2452 0134 DA61 str r2, [r3, #28] +1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2453 .loc 1 1353 5 view .LVU803 + 2454 0136 2168 ldr r1, [r4] + 2455 0138 4B68 ldr r3, [r1, #4] + 2456 013a 23F0FF73 bic r3, r3, #33423360 + 2457 013e 23F48B33 bic r3, r3, #71168 + 2458 0142 23F4FF73 bic r3, r3, #510 + 2459 0146 23F00103 bic r3, r3, #1 + 2460 014a 4B60 str r3, [r1, #4] +1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2461 .loc 1 1355 5 view .LVU804 +1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2462 .loc 1 1355 17 is_stmt 0 view .LVU805 + 2463 014c 84F84120 strb r2, [r4, #65] +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2464 .loc 1 1356 5 is_stmt 1 view .LVU806 +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2465 .loc 1 1356 17 is_stmt 0 view .LVU807 + 2466 0150 0023 movs r3, #0 + 2467 0152 84F84230 strb r3, [r4, #66] +1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2468 .loc 1 1359 5 is_stmt 1 view .LVU808 +1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2469 .loc 1 1359 5 view .LVU809 + 2470 0156 84F84030 strb r3, [r4, #64] +1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2471 .loc 1 1359 5 view .LVU810 +1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2472 .loc 1 1361 5 view .LVU811 +1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2473 .loc 1 1361 12 is_stmt 0 view .LVU812 + 2474 015a 00E0 b .L173 + 2475 .LVL168: + 2476 .L180: +1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2477 .loc 1 1365 12 view .LVU813 + 2478 015c 0220 movs r0, #2 + 2479 .LVL169: + 2480 .L173: +1367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2481 .loc 1 1367 1 view .LVU814 + 2482 015e 02B0 add sp, sp, #8 + 2483 .LCFI25: + 2484 .cfi_remember_state + 2485 .cfi_def_cfa_offset 32 + 2486 @ sp needed + 2487 0160 BDE8F087 pop {r4, r5, r6, r7, r8, r9, r10, pc} + 2488 .LVL170: + ARM GAS /tmp/ccSHpINd.s page 189 + + + 2489 .L181: + 2490 .LCFI26: + 2491 .cfi_restore_state +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2492 .loc 1 1268 5 discriminator 1 view .LVU815 + 2493 0164 0220 movs r0, #2 + 2494 .LVL171: +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2495 .loc 1 1268 5 discriminator 1 view .LVU816 + 2496 0166 FAE7 b .L173 + 2497 .LVL172: + 2498 .L182: +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2499 .loc 1 1275 14 view .LVU817 + 2500 0168 0120 movs r0, #1 + 2501 016a F8E7 b .L173 + 2502 .L183: +1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2503 .loc 1 1307 16 view .LVU818 + 2504 016c 0120 movs r0, #1 + 2505 016e F6E7 b .L173 + 2506 .L184: +1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2507 .loc 1 1324 18 view .LVU819 + 2508 0170 0120 movs r0, #1 + 2509 0172 F4E7 b .L173 + 2510 .L185: +1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2511 .loc 1 1346 14 view .LVU820 + 2512 0174 0120 movs r0, #1 + 2513 0176 F2E7 b .L173 + 2514 .L189: + 2515 .align 2 + 2516 .L188: + 2517 0178 00240080 .word -2147474432 + 2518 .cfi_endproc + 2519 .LFE146: + 2521 .section .text.HAL_I2C_Slave_Transmit,"ax",%progbits + 2522 .align 1 + 2523 .global HAL_I2C_Slave_Transmit + 2524 .syntax unified + 2525 .thumb + 2526 .thumb_func + 2528 HAL_I2C_Slave_Transmit: + 2529 .LVL173: + 2530 .LFB147: +1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; + 2531 .loc 1 1380 1 is_stmt 1 view -0 + 2532 .cfi_startproc + 2533 @ args = 0, pretend = 0, frame = 0 + 2534 @ frame_needed = 0, uses_anonymous_args = 0 +1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; + 2535 .loc 1 1380 1 is_stmt 0 view .LVU822 + 2536 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 2537 .LCFI27: + 2538 .cfi_def_cfa_offset 24 + 2539 .cfi_offset 4, -24 + ARM GAS /tmp/ccSHpINd.s page 190 + + + 2540 .cfi_offset 5, -20 + 2541 .cfi_offset 6, -16 + 2542 .cfi_offset 7, -12 + 2543 .cfi_offset 8, -8 + 2544 .cfi_offset 14, -4 + 2545 0004 82B0 sub sp, sp, #8 + 2546 .LCFI28: + 2547 .cfi_def_cfa_offset 32 + 2548 0006 1D46 mov r5, r3 +1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t tmpXferCount; + 2549 .loc 1 1381 3 is_stmt 1 view .LVU823 +1382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef error; + 2550 .loc 1 1382 3 view .LVU824 +1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2551 .loc 1 1383 3 view .LVU825 +1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2552 .loc 1 1385 3 view .LVU826 +1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2553 .loc 1 1385 11 is_stmt 0 view .LVU827 + 2554 0008 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 2555 .LVL174: +1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2556 .loc 1 1385 11 view .LVU828 + 2557 000c DBB2 uxtb r3, r3 +1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2558 .loc 1 1385 6 view .LVU829 + 2559 000e 202B cmp r3, #32 + 2560 0010 40F0EA80 bne .L205 + 2561 0014 0446 mov r4, r0 + 2562 0016 0F46 mov r7, r1 + 2563 0018 9046 mov r8, r2 +1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2564 .loc 1 1387 5 is_stmt 1 view .LVU830 +1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2565 .loc 1 1387 8 is_stmt 0 view .LVU831 + 2566 001a 002A cmp r2, #0 + 2567 001c 18BF it ne + 2568 001e 0029 cmpne r1, #0 + 2569 0020 55D0 beq .L208 +1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2570 .loc 1 1393 5 is_stmt 1 view .LVU832 +1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2571 .loc 1 1393 5 view .LVU833 + 2572 0022 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 2573 0026 012B cmp r3, #1 + 2574 0028 00F0E280 beq .L206 +1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2575 .loc 1 1393 5 discriminator 2 view .LVU834 + 2576 002c 0123 movs r3, #1 + 2577 002e 80F84030 strb r3, [r0, #64] +1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2578 .loc 1 1393 5 discriminator 2 view .LVU835 +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2579 .loc 1 1396 5 view .LVU836 +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2580 .loc 1 1396 17 is_stmt 0 view .LVU837 + 2581 0032 FFF7FEFF bl HAL_GetTick + ARM GAS /tmp/ccSHpINd.s page 191 + + + 2582 .LVL175: +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2583 .loc 1 1396 17 view .LVU838 + 2584 0036 0646 mov r6, r0 + 2585 .LVL176: +1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 2586 .loc 1 1398 5 is_stmt 1 view .LVU839 +1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 2587 .loc 1 1398 21 is_stmt 0 view .LVU840 + 2588 0038 2123 movs r3, #33 + 2589 003a 84F84130 strb r3, [r4, #65] +1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2590 .loc 1 1399 5 is_stmt 1 view .LVU841 +1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2591 .loc 1 1399 21 is_stmt 0 view .LVU842 + 2592 003e 2023 movs r3, #32 + 2593 0040 84F84230 strb r3, [r4, #66] +1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2594 .loc 1 1400 5 is_stmt 1 view .LVU843 +1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2595 .loc 1 1400 21 is_stmt 0 view .LVU844 + 2596 0044 0023 movs r3, #0 + 2597 0046 6364 str r3, [r4, #68] +1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 2598 .loc 1 1403 5 is_stmt 1 view .LVU845 +1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 2599 .loc 1 1403 21 is_stmt 0 view .LVU846 + 2600 0048 6762 str r7, [r4, #36] +1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2601 .loc 1 1404 5 is_stmt 1 view .LVU847 +1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2602 .loc 1 1404 21 is_stmt 0 view .LVU848 + 2603 004a A4F82A80 strh r8, [r4, #42] @ movhi +1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2604 .loc 1 1405 5 is_stmt 1 view .LVU849 +1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2605 .loc 1 1405 21 is_stmt 0 view .LVU850 + 2606 004e 6363 str r3, [r4, #52] +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2607 .loc 1 1408 5 is_stmt 1 view .LVU851 +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2608 .loc 1 1408 9 is_stmt 0 view .LVU852 + 2609 0050 2268 ldr r2, [r4] +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2610 .loc 1 1408 19 view .LVU853 + 2611 0052 5368 ldr r3, [r2, #4] +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2612 .loc 1 1408 25 view .LVU854 + 2613 0054 23F40043 bic r3, r3, #32768 + 2614 0058 5360 str r3, [r2, #4] +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2615 .loc 1 1411 5 is_stmt 1 view .LVU855 +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2616 .loc 1 1411 19 is_stmt 0 view .LVU856 + 2617 005a 236A ldr r3, [r4, #32] +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2618 .loc 1 1411 8 view .LVU857 + ARM GAS /tmp/ccSHpINd.s page 192 + + + 2619 005c B3F5003F cmp r3, #131072 + 2620 0060 3AD0 beq .L209 + 2621 .L193: +1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2622 .loc 1 1424 5 is_stmt 1 view .LVU858 +1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2623 .loc 1 1424 9 is_stmt 0 view .LVU859 + 2624 0062 0096 str r6, [sp] + 2625 0064 2B46 mov r3, r5 + 2626 0066 0022 movs r2, #0 + 2627 0068 0821 movs r1, #8 + 2628 006a 2046 mov r0, r4 + 2629 .LVL177: +1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2630 .loc 1 1424 9 view .LVU860 + 2631 006c FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2632 .LVL178: +1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2633 .loc 1 1424 8 discriminator 1 view .LVU861 + 2634 0070 0028 cmp r0, #0 + 2635 0072 3ED1 bne .L210 +1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2636 .loc 1 1436 5 is_stmt 1 view .LVU862 + 2637 0074 2368 ldr r3, [r4] + 2638 0076 0822 movs r2, #8 + 2639 0078 DA61 str r2, [r3, #28] +1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2640 .loc 1 1439 5 view .LVU863 +1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2641 .loc 1 1439 19 is_stmt 0 view .LVU864 + 2642 007a E368 ldr r3, [r4, #12] +1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2643 .loc 1 1439 8 view .LVU865 + 2644 007c 022B cmp r3, #2 + 2645 007e 42D0 beq .L211 + 2646 .L195: +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2647 .loc 1 1458 5 is_stmt 1 view .LVU866 +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2648 .loc 1 1458 9 is_stmt 0 view .LVU867 + 2649 0080 0096 str r6, [sp] + 2650 0082 2B46 mov r3, r5 + 2651 0084 0022 movs r2, #0 + 2652 0086 4FF48031 mov r1, #65536 + 2653 008a 2046 mov r0, r4 + 2654 008c FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2655 .LVL179: +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2656 .loc 1 1458 8 discriminator 1 view .LVU868 + 2657 0090 0028 cmp r0, #0 + 2658 0092 4ED1 bne .L212 + 2659 .L197: +1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2660 .loc 1 1469 28 is_stmt 1 view .LVU869 +1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2661 .loc 1 1469 16 is_stmt 0 view .LVU870 + 2662 0094 628D ldrh r2, [r4, #42] + ARM GAS /tmp/ccSHpINd.s page 193 + + + 2663 0096 92B2 uxth r2, r2 +1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2664 .loc 1 1469 28 view .LVU871 + 2665 0098 002A cmp r2, #0 + 2666 009a 5BD0 beq .L213 +1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2667 .loc 1 1472 7 is_stmt 1 view .LVU872 +1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2668 .loc 1 1472 11 is_stmt 0 view .LVU873 + 2669 009c 3246 mov r2, r6 + 2670 009e 2946 mov r1, r5 + 2671 00a0 2046 mov r0, r4 + 2672 00a2 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 2673 .LVL180: +1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2674 .loc 1 1472 10 discriminator 1 view .LVU874 + 2675 00a6 0028 cmp r0, #0 + 2676 00a8 4DD1 bne .L214 +1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2677 .loc 1 1480 7 is_stmt 1 view .LVU875 +1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2678 .loc 1 1480 35 is_stmt 0 view .LVU876 + 2679 00aa 626A ldr r2, [r4, #36] +1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2680 .loc 1 1480 11 view .LVU877 + 2681 00ac 2368 ldr r3, [r4] +1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2682 .loc 1 1480 30 view .LVU878 + 2683 00ae 1278 ldrb r2, [r2] @ zero_extendqisi2 +1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2684 .loc 1 1480 28 view .LVU879 + 2685 00b0 9A62 str r2, [r3, #40] +1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2686 .loc 1 1483 7 is_stmt 1 view .LVU880 +1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2687 .loc 1 1483 11 is_stmt 0 view .LVU881 + 2688 00b2 636A ldr r3, [r4, #36] +1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2689 .loc 1 1483 21 view .LVU882 + 2690 00b4 0133 adds r3, r3, #1 + 2691 00b6 6362 str r3, [r4, #36] +1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2692 .loc 1 1485 7 is_stmt 1 view .LVU883 +1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2693 .loc 1 1485 11 is_stmt 0 view .LVU884 + 2694 00b8 B4F82AC0 ldrh ip, [r4, #42] + 2695 00bc 1FFA8CFC uxth ip, ip +1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2696 .loc 1 1485 22 view .LVU885 + 2697 00c0 0CF1FF3C add ip, ip, #-1 + 2698 00c4 1FFA8CFC uxth ip, ip + 2699 00c8 A4F82AC0 strh ip, [r4, #42] @ movhi + 2700 00cc E2E7 b .L197 + 2701 .LVL181: + 2702 .L208: +1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 2703 .loc 1 1389 7 is_stmt 1 view .LVU886 + ARM GAS /tmp/ccSHpINd.s page 194 + + +1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 2704 .loc 1 1389 23 is_stmt 0 view .LVU887 + 2705 00ce 4FF40073 mov r3, #512 + 2706 00d2 4364 str r3, [r0, #68] +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2707 .loc 1 1390 7 is_stmt 1 view .LVU888 +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2708 .loc 1 1390 15 is_stmt 0 view .LVU889 + 2709 00d4 0120 movs r0, #1 + 2710 .LVL182: +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2711 .loc 1 1390 15 view .LVU890 + 2712 00d6 88E0 b .L191 + 2713 .LVL183: + 2714 .L209: +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2715 .loc 1 1415 7 is_stmt 1 view .LVU891 +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2716 .loc 1 1415 35 is_stmt 0 view .LVU892 + 2717 00d8 626A ldr r2, [r4, #36] +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2718 .loc 1 1415 11 view .LVU893 + 2719 00da 2368 ldr r3, [r4] +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2720 .loc 1 1415 30 view .LVU894 + 2721 00dc 1278 ldrb r2, [r2] @ zero_extendqisi2 +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2722 .loc 1 1415 28 view .LVU895 + 2723 00de 9A62 str r2, [r3, #40] +1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2724 .loc 1 1418 7 is_stmt 1 view .LVU896 +1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2725 .loc 1 1418 11 is_stmt 0 view .LVU897 + 2726 00e0 636A ldr r3, [r4, #36] +1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2727 .loc 1 1418 21 view .LVU898 + 2728 00e2 0133 adds r3, r3, #1 + 2729 00e4 6362 str r3, [r4, #36] +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2730 .loc 1 1420 7 is_stmt 1 view .LVU899 +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2731 .loc 1 1420 11 is_stmt 0 view .LVU900 + 2732 00e6 638D ldrh r3, [r4, #42] + 2733 00e8 9BB2 uxth r3, r3 +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2734 .loc 1 1420 22 view .LVU901 + 2735 00ea 013B subs r3, r3, #1 + 2736 00ec 9BB2 uxth r3, r3 + 2737 00ee 6385 strh r3, [r4, #42] @ movhi + 2738 00f0 B7E7 b .L193 + 2739 .LVL184: + 2740 .L210: +1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2741 .loc 1 1427 7 is_stmt 1 view .LVU902 +1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2742 .loc 1 1427 11 is_stmt 0 view .LVU903 + 2743 00f2 2268 ldr r2, [r4] + ARM GAS /tmp/ccSHpINd.s page 195 + + +1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2744 .loc 1 1427 21 view .LVU904 + 2745 00f4 5368 ldr r3, [r2, #4] +1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2746 .loc 1 1427 27 view .LVU905 + 2747 00f6 43F40043 orr r3, r3, #32768 + 2748 00fa 5360 str r3, [r2, #4] +1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2749 .loc 1 1430 7 is_stmt 1 view .LVU906 + 2750 00fc 2046 mov r0, r4 + 2751 00fe FFF7FEFF bl I2C_Flush_TXDR + 2752 .LVL185: +1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2753 .loc 1 1432 7 view .LVU907 +1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2754 .loc 1 1432 14 is_stmt 0 view .LVU908 + 2755 0102 0120 movs r0, #1 + 2756 0104 71E0 b .L191 + 2757 .L211: +1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2758 .loc 1 1442 7 is_stmt 1 view .LVU909 +1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2759 .loc 1 1442 11 is_stmt 0 view .LVU910 + 2760 0106 0096 str r6, [sp] + 2761 0108 2B46 mov r3, r5 + 2762 010a 0022 movs r2, #0 + 2763 010c 0821 movs r1, #8 + 2764 010e 2046 mov r0, r4 + 2765 0110 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2766 .LVL186: +1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2767 .loc 1 1442 10 discriminator 1 view .LVU911 + 2768 0114 18B9 cbnz r0, .L215 +1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2769 .loc 1 1454 7 is_stmt 1 view .LVU912 + 2770 0116 2368 ldr r3, [r4] + 2771 0118 0822 movs r2, #8 + 2772 011a DA61 str r2, [r3, #28] + 2773 011c B0E7 b .L195 + 2774 .L215: +1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2775 .loc 1 1445 9 view .LVU913 +1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2776 .loc 1 1445 13 is_stmt 0 view .LVU914 + 2777 011e 2268 ldr r2, [r4] +1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2778 .loc 1 1445 23 view .LVU915 + 2779 0120 5368 ldr r3, [r2, #4] +1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2780 .loc 1 1445 29 view .LVU916 + 2781 0122 43F40043 orr r3, r3, #32768 + 2782 0126 5360 str r3, [r2, #4] +1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2783 .loc 1 1448 9 is_stmt 1 view .LVU917 + 2784 0128 2046 mov r0, r4 + 2785 012a FFF7FEFF bl I2C_Flush_TXDR + 2786 .LVL187: + ARM GAS /tmp/ccSHpINd.s page 196 + + +1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2787 .loc 1 1450 9 view .LVU918 +1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2788 .loc 1 1450 16 is_stmt 0 view .LVU919 + 2789 012e 0120 movs r0, #1 + 2790 0130 5BE0 b .L191 + 2791 .L212: +1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2792 .loc 1 1461 7 is_stmt 1 view .LVU920 +1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2793 .loc 1 1461 11 is_stmt 0 view .LVU921 + 2794 0132 2268 ldr r2, [r4] +1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2795 .loc 1 1461 21 view .LVU922 + 2796 0134 5368 ldr r3, [r2, #4] +1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2797 .loc 1 1461 27 view .LVU923 + 2798 0136 43F40043 orr r3, r3, #32768 + 2799 013a 5360 str r3, [r2, #4] +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2800 .loc 1 1464 7 is_stmt 1 view .LVU924 + 2801 013c 2046 mov r0, r4 + 2802 013e FFF7FEFF bl I2C_Flush_TXDR + 2803 .LVL188: +1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2804 .loc 1 1466 7 view .LVU925 +1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2805 .loc 1 1466 14 is_stmt 0 view .LVU926 + 2806 0142 0120 movs r0, #1 + 2807 0144 51E0 b .L191 + 2808 .L214: +1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 2809 .loc 1 1475 9 is_stmt 1 view .LVU927 +1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 2810 .loc 1 1475 13 is_stmt 0 view .LVU928 + 2811 0146 2268 ldr r2, [r4] +1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 2812 .loc 1 1475 23 view .LVU929 + 2813 0148 5368 ldr r3, [r2, #4] +1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 2814 .loc 1 1475 29 view .LVU930 + 2815 014a 43F40043 orr r3, r3, #32768 + 2816 014e 5360 str r3, [r2, #4] +1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2817 .loc 1 1476 9 is_stmt 1 view .LVU931 +1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2818 .loc 1 1476 16 is_stmt 0 view .LVU932 + 2819 0150 0120 movs r0, #1 + 2820 0152 4AE0 b .L191 + 2821 .L213: +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2822 .loc 1 1489 5 is_stmt 1 view .LVU933 +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2823 .loc 1 1489 13 is_stmt 0 view .LVU934 + 2824 0154 0096 str r6, [sp] + 2825 0156 2B46 mov r3, r5 + 2826 0158 1021 movs r1, #16 + ARM GAS /tmp/ccSHpINd.s page 197 + + + 2827 015a 2046 mov r0, r4 + 2828 015c FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2829 .LVL189: +1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2830 .loc 1 1491 5 is_stmt 1 view .LVU935 +1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2831 .loc 1 1491 8 is_stmt 0 view .LVU936 + 2832 0160 E8B1 cbz r0, .L200 +1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) + 2833 .loc 1 1497 7 is_stmt 1 view .LVU937 +1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) + 2834 .loc 1 1497 20 is_stmt 0 view .LVU938 + 2835 0162 638D ldrh r3, [r4, #42] + 2836 0164 9BB2 uxth r3, r3 + 2837 .LVL190: +1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2838 .loc 1 1498 7 is_stmt 1 view .LVU939 +1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2839 .loc 1 1498 16 is_stmt 0 view .LVU940 + 2840 0166 626C ldr r2, [r4, #68] +1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2841 .loc 1 1498 10 view .LVU941 + 2842 0168 042A cmp r2, #4 + 2843 016a 11D1 bne .L201 +1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2844 .loc 1 1498 49 discriminator 1 view .LVU942 + 2845 016c 83B9 cbnz r3, .L201 +1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2846 .loc 1 1501 9 is_stmt 1 view .LVU943 +1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2847 .loc 1 1501 25 is_stmt 0 view .LVU944 + 2848 016e 6364 str r3, [r4, #68] + 2849 .LVL191: + 2850 .L202: +1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2851 .loc 1 1532 5 is_stmt 1 view .LVU945 +1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2852 .loc 1 1532 9 is_stmt 0 view .LVU946 + 2853 0170 0096 str r6, [sp] + 2854 0172 2B46 mov r3, r5 + 2855 0174 0122 movs r2, #1 + 2856 0176 4FF40041 mov r1, #32768 + 2857 017a 2046 mov r0, r4 + 2858 017c FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2859 .LVL192: +1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2860 .loc 1 1532 8 discriminator 1 view .LVU947 + 2861 0180 20B3 cbz r0, .L204 +1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 2862 .loc 1 1535 7 is_stmt 1 view .LVU948 +1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 2863 .loc 1 1535 11 is_stmt 0 view .LVU949 + 2864 0182 2268 ldr r2, [r4] +1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 2865 .loc 1 1535 21 view .LVU950 + 2866 0184 5368 ldr r3, [r2, #4] +1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + ARM GAS /tmp/ccSHpINd.s page 198 + + + 2867 .loc 1 1535 27 view .LVU951 + 2868 0186 43F40043 orr r3, r3, #32768 + 2869 018a 5360 str r3, [r2, #4] +1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2870 .loc 1 1536 7 is_stmt 1 view .LVU952 +1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2871 .loc 1 1536 14 is_stmt 0 view .LVU953 + 2872 018c 0120 movs r0, #1 + 2873 018e 2CE0 b .L191 + 2874 .LVL193: + 2875 .L201: +1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 2876 .loc 1 1506 9 is_stmt 1 view .LVU954 +1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 2877 .loc 1 1506 13 is_stmt 0 view .LVU955 + 2878 0190 2268 ldr r2, [r4] +1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 2879 .loc 1 1506 23 view .LVU956 + 2880 0192 5368 ldr r3, [r2, #4] + 2881 .LVL194: +1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 2882 .loc 1 1506 29 view .LVU957 + 2883 0194 43F40043 orr r3, r3, #32768 + 2884 0198 5360 str r3, [r2, #4] +1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2885 .loc 1 1507 9 is_stmt 1 view .LVU958 +1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2886 .loc 1 1507 16 is_stmt 0 view .LVU959 + 2887 019a 0120 movs r0, #1 + 2888 .LVL195: +1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2889 .loc 1 1507 16 view .LVU960 + 2890 019c 25E0 b .L191 + 2891 .LVL196: + 2892 .L200: +1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2893 .loc 1 1513 7 is_stmt 1 view .LVU961 + 2894 019e 2046 mov r0, r4 + 2895 .LVL197: +1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2896 .loc 1 1513 7 is_stmt 0 view .LVU962 + 2897 01a0 FFF7FEFF bl I2C_Flush_TXDR + 2898 .LVL198: +1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2899 .loc 1 1516 7 is_stmt 1 view .LVU963 + 2900 01a4 2368 ldr r3, [r4] + 2901 01a6 1022 movs r2, #16 + 2902 01a8 DA61 str r2, [r3, #28] +1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2903 .loc 1 1519 7 view .LVU964 +1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2904 .loc 1 1519 11 is_stmt 0 view .LVU965 + 2905 01aa 3246 mov r2, r6 + 2906 01ac 2946 mov r1, r5 + 2907 01ae 2046 mov r0, r4 + 2908 01b0 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 2909 .LVL199: + ARM GAS /tmp/ccSHpINd.s page 199 + + +1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 2910 .loc 1 1519 10 discriminator 1 view .LVU966 + 2911 01b4 18B9 cbnz r0, .L216 +1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2912 .loc 1 1528 7 is_stmt 1 view .LVU967 + 2913 01b6 2368 ldr r3, [r4] + 2914 01b8 2022 movs r2, #32 + 2915 01ba DA61 str r2, [r3, #28] + 2916 01bc D8E7 b .L202 + 2917 .L216: +1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2918 .loc 1 1522 9 view .LVU968 +1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2919 .loc 1 1522 13 is_stmt 0 view .LVU969 + 2920 01be 2268 ldr r2, [r4] +1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2921 .loc 1 1522 23 view .LVU970 + 2922 01c0 5368 ldr r3, [r2, #4] +1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2923 .loc 1 1522 29 view .LVU971 + 2924 01c2 43F40043 orr r3, r3, #32768 + 2925 01c6 5360 str r3, [r2, #4] +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2926 .loc 1 1524 9 is_stmt 1 view .LVU972 +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2927 .loc 1 1524 16 is_stmt 0 view .LVU973 + 2928 01c8 0120 movs r0, #1 + 2929 01ca 0EE0 b .L191 + 2930 .L204: +1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2931 .loc 1 1540 5 is_stmt 1 view .LVU974 +1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2932 .loc 1 1540 9 is_stmt 0 view .LVU975 + 2933 01cc 2268 ldr r2, [r4] +1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2934 .loc 1 1540 19 view .LVU976 + 2935 01ce 5368 ldr r3, [r2, #4] +1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2936 .loc 1 1540 25 view .LVU977 + 2937 01d0 43F40043 orr r3, r3, #32768 + 2938 01d4 5360 str r3, [r2, #4] +1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2939 .loc 1 1542 5 is_stmt 1 view .LVU978 +1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2940 .loc 1 1542 17 is_stmt 0 view .LVU979 + 2941 01d6 2023 movs r3, #32 + 2942 01d8 84F84130 strb r3, [r4, #65] +1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2943 .loc 1 1543 5 is_stmt 1 view .LVU980 +1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2944 .loc 1 1543 17 is_stmt 0 view .LVU981 + 2945 01dc 0023 movs r3, #0 + 2946 01de 84F84230 strb r3, [r4, #66] +1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2947 .loc 1 1546 5 is_stmt 1 view .LVU982 +1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2948 .loc 1 1546 5 view .LVU983 + ARM GAS /tmp/ccSHpINd.s page 200 + + + 2949 01e2 84F84030 strb r3, [r4, #64] +1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2950 .loc 1 1546 5 view .LVU984 +1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2951 .loc 1 1548 5 view .LVU985 +1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2952 .loc 1 1548 12 is_stmt 0 view .LVU986 + 2953 01e6 00E0 b .L191 + 2954 .LVL200: + 2955 .L205: +1552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 2956 .loc 1 1552 12 view .LVU987 + 2957 01e8 0220 movs r0, #2 + 2958 .LVL201: + 2959 .L191: +1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2960 .loc 1 1554 1 view .LVU988 + 2961 01ea 02B0 add sp, sp, #8 + 2962 .LCFI29: + 2963 .cfi_remember_state + 2964 .cfi_def_cfa_offset 24 + 2965 @ sp needed + 2966 01ec BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 2967 .LVL202: + 2968 .L206: + 2969 .LCFI30: + 2970 .cfi_restore_state +1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2971 .loc 1 1393 5 discriminator 1 view .LVU989 + 2972 01f0 0220 movs r0, #2 + 2973 .LVL203: +1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 2974 .loc 1 1393 5 discriminator 1 view .LVU990 + 2975 01f2 FAE7 b .L191 + 2976 .cfi_endproc + 2977 .LFE147: + 2979 .section .text.HAL_I2C_Slave_Receive,"ax",%progbits + 2980 .align 1 + 2981 .global HAL_I2C_Slave_Receive + 2982 .syntax unified + 2983 .thumb + 2984 .thumb_func + 2986 HAL_I2C_Slave_Receive: + 2987 .LVL204: + 2988 .LFB148: +1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; + 2989 .loc 1 1567 1 is_stmt 1 view -0 + 2990 .cfi_startproc + 2991 @ args = 0, pretend = 0, frame = 0 + 2992 @ frame_needed = 0, uses_anonymous_args = 0 +1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; + 2993 .loc 1 1567 1 is_stmt 0 view .LVU992 + 2994 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 2995 .LCFI31: + 2996 .cfi_def_cfa_offset 24 + 2997 .cfi_offset 4, -24 + 2998 .cfi_offset 5, -20 + ARM GAS /tmp/ccSHpINd.s page 201 + + + 2999 .cfi_offset 6, -16 + 3000 .cfi_offset 7, -12 + 3001 .cfi_offset 8, -8 + 3002 .cfi_offset 14, -4 + 3003 0004 82B0 sub sp, sp, #8 + 3004 .LCFI32: + 3005 .cfi_def_cfa_offset 32 + 3006 0006 1D46 mov r5, r3 +1568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3007 .loc 1 1568 3 is_stmt 1 view .LVU993 +1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3008 .loc 1 1570 3 view .LVU994 +1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3009 .loc 1 1570 11 is_stmt 0 view .LVU995 + 3010 0008 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 3011 .LVL205: +1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3012 .loc 1 1570 11 view .LVU996 + 3013 000c DBB2 uxtb r3, r3 +1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3014 .loc 1 1570 6 view .LVU997 + 3015 000e 202B cmp r3, #32 + 3016 0010 40F0B280 bne .L227 + 3017 0014 0446 mov r4, r0 + 3018 0016 0F46 mov r7, r1 + 3019 0018 9046 mov r8, r2 +1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3020 .loc 1 1572 5 is_stmt 1 view .LVU998 +1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3021 .loc 1 1572 8 is_stmt 0 view .LVU999 + 3022 001a 002A cmp r2, #0 + 3023 001c 18BF it ne + 3024 001e 0029 cmpne r1, #0 + 3025 0020 2BD0 beq .L230 +1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3026 .loc 1 1578 5 is_stmt 1 view .LVU1000 +1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3027 .loc 1 1578 5 view .LVU1001 + 3028 0022 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 3029 0026 012B cmp r3, #1 + 3030 0028 00F0AA80 beq .L228 +1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3031 .loc 1 1578 5 discriminator 2 view .LVU1002 + 3032 002c 0123 movs r3, #1 + 3033 002e 80F84030 strb r3, [r0, #64] +1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3034 .loc 1 1578 5 discriminator 2 view .LVU1003 +1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3035 .loc 1 1581 5 view .LVU1004 +1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3036 .loc 1 1581 17 is_stmt 0 view .LVU1005 + 3037 0032 FFF7FEFF bl HAL_GetTick + 3038 .LVL206: +1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3039 .loc 1 1581 17 view .LVU1006 + 3040 0036 0646 mov r6, r0 + 3041 .LVL207: + ARM GAS /tmp/ccSHpINd.s page 202 + + +1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3042 .loc 1 1583 5 is_stmt 1 view .LVU1007 +1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3043 .loc 1 1583 21 is_stmt 0 view .LVU1008 + 3044 0038 2223 movs r3, #34 + 3045 003a 84F84130 strb r3, [r4, #65] +1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3046 .loc 1 1584 5 is_stmt 1 view .LVU1009 +1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3047 .loc 1 1584 21 is_stmt 0 view .LVU1010 + 3048 003e 2023 movs r3, #32 + 3049 0040 84F84230 strb r3, [r4, #66] +1585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3050 .loc 1 1585 5 is_stmt 1 view .LVU1011 +1585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3051 .loc 1 1585 21 is_stmt 0 view .LVU1012 + 3052 0044 0022 movs r2, #0 + 3053 0046 6264 str r2, [r4, #68] +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3054 .loc 1 1588 5 is_stmt 1 view .LVU1013 +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3055 .loc 1 1588 21 is_stmt 0 view .LVU1014 + 3056 0048 6762 str r7, [r4, #36] +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3057 .loc 1 1589 5 is_stmt 1 view .LVU1015 +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3058 .loc 1 1589 21 is_stmt 0 view .LVU1016 + 3059 004a A4F82A80 strh r8, [r4, #42] @ movhi +1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 3060 .loc 1 1590 5 is_stmt 1 view .LVU1017 +1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 3061 .loc 1 1590 26 is_stmt 0 view .LVU1018 + 3062 004e 638D ldrh r3, [r4, #42] +1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 3063 .loc 1 1590 20 view .LVU1019 + 3064 0050 2385 strh r3, [r4, #40] @ movhi +1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3065 .loc 1 1591 5 is_stmt 1 view .LVU1020 +1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3066 .loc 1 1591 21 is_stmt 0 view .LVU1021 + 3067 0052 6263 str r2, [r4, #52] +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3068 .loc 1 1594 5 is_stmt 1 view .LVU1022 +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3069 .loc 1 1594 9 is_stmt 0 view .LVU1023 + 3070 0054 2168 ldr r1, [r4] +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3071 .loc 1 1594 19 view .LVU1024 + 3072 0056 4B68 ldr r3, [r1, #4] +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3073 .loc 1 1594 25 view .LVU1025 + 3074 0058 23F40043 bic r3, r3, #32768 + 3075 005c 4B60 str r3, [r1, #4] +1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3076 .loc 1 1597 5 is_stmt 1 view .LVU1026 +1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3077 .loc 1 1597 9 is_stmt 0 view .LVU1027 + ARM GAS /tmp/ccSHpINd.s page 203 + + + 3078 005e 0090 str r0, [sp] + 3079 0060 2B46 mov r3, r5 + 3080 0062 0821 movs r1, #8 + 3081 0064 2046 mov r0, r4 + 3082 .LVL208: +1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3083 .loc 1 1597 9 view .LVU1028 + 3084 0066 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 3085 .LVL209: +1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3086 .loc 1 1597 8 discriminator 1 view .LVU1029 + 3087 006a 58B1 cbz r0, .L220 +1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 3088 .loc 1 1600 7 is_stmt 1 view .LVU1030 +1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 3089 .loc 1 1600 11 is_stmt 0 view .LVU1031 + 3090 006c 2268 ldr r2, [r4] +1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 3091 .loc 1 1600 21 view .LVU1032 + 3092 006e 5368 ldr r3, [r2, #4] +1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 3093 .loc 1 1600 27 view .LVU1033 + 3094 0070 43F40043 orr r3, r3, #32768 + 3095 0074 5360 str r3, [r2, #4] +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3096 .loc 1 1601 7 is_stmt 1 view .LVU1034 +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3097 .loc 1 1601 14 is_stmt 0 view .LVU1035 + 3098 0076 0120 movs r0, #1 + 3099 0078 7FE0 b .L218 + 3100 .LVL210: + 3101 .L230: +1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 3102 .loc 1 1574 7 is_stmt 1 view .LVU1036 +1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 3103 .loc 1 1574 23 is_stmt 0 view .LVU1037 + 3104 007a 4FF40073 mov r3, #512 + 3105 007e 4364 str r3, [r0, #68] +1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3106 .loc 1 1575 7 is_stmt 1 view .LVU1038 +1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3107 .loc 1 1575 15 is_stmt 0 view .LVU1039 + 3108 0080 0120 movs r0, #1 + 3109 .LVL211: +1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3110 .loc 1 1575 15 view .LVU1040 + 3111 0082 7AE0 b .L218 + 3112 .LVL212: + 3113 .L220: +1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3114 .loc 1 1605 5 is_stmt 1 view .LVU1041 + 3115 0084 2368 ldr r3, [r4] + 3116 0086 0822 movs r2, #8 + 3117 0088 DA61 str r2, [r3, #28] +1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3118 .loc 1 1608 5 view .LVU1042 +1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 204 + + + 3119 .loc 1 1608 9 is_stmt 0 view .LVU1043 + 3120 008a 0096 str r6, [sp] + 3121 008c 2B46 mov r3, r5 + 3122 008e 0122 movs r2, #1 + 3123 0090 4FF48031 mov r1, #65536 + 3124 0094 2046 mov r0, r4 + 3125 0096 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 3126 .LVL213: +1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3127 .loc 1 1608 8 discriminator 1 view .LVU1044 + 3128 009a F0B9 cbnz r0, .L231 + 3129 .L221: +1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3130 .loc 1 1615 28 is_stmt 1 view .LVU1045 +1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3131 .loc 1 1615 16 is_stmt 0 view .LVU1046 + 3132 009c 638D ldrh r3, [r4, #42] + 3133 009e 9BB2 uxth r3, r3 +1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3134 .loc 1 1615 28 view .LVU1047 + 3135 00a0 002B cmp r3, #0 + 3136 00a2 3BD0 beq .L232 +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3137 .loc 1 1618 7 is_stmt 1 view .LVU1048 +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3138 .loc 1 1618 11 is_stmt 0 view .LVU1049 + 3139 00a4 3246 mov r2, r6 + 3140 00a6 2946 mov r1, r5 + 3141 00a8 2046 mov r0, r4 + 3142 00aa FFF7FEFF bl I2C_WaitOnRXNEFlagUntilTimeout + 3143 .LVL214: +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3144 .loc 1 1618 10 discriminator 1 view .LVU1050 + 3145 00ae D8B9 cbnz r0, .L233 +1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3146 .loc 1 1640 7 is_stmt 1 view .LVU1051 +1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3147 .loc 1 1640 38 is_stmt 0 view .LVU1052 + 3148 00b0 2368 ldr r3, [r4] +1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3149 .loc 1 1640 48 view .LVU1053 + 3150 00b2 5A6A ldr r2, [r3, #36] +1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3151 .loc 1 1640 12 view .LVU1054 + 3152 00b4 636A ldr r3, [r4, #36] +1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3153 .loc 1 1640 23 view .LVU1055 + 3154 00b6 1A70 strb r2, [r3] +1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3155 .loc 1 1643 7 is_stmt 1 view .LVU1056 +1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3156 .loc 1 1643 11 is_stmt 0 view .LVU1057 + 3157 00b8 636A ldr r3, [r4, #36] +1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3158 .loc 1 1643 21 view .LVU1058 + 3159 00ba 0133 adds r3, r3, #1 + 3160 00bc 6362 str r3, [r4, #36] + ARM GAS /tmp/ccSHpINd.s page 205 + + +1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 3161 .loc 1 1645 7 is_stmt 1 view .LVU1059 +1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 3162 .loc 1 1645 11 is_stmt 0 view .LVU1060 + 3163 00be B4F82AC0 ldrh ip, [r4, #42] + 3164 00c2 1FFA8CFC uxth ip, ip +1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 3165 .loc 1 1645 22 view .LVU1061 + 3166 00c6 0CF1FF3C add ip, ip, #-1 + 3167 00ca 1FFA8CFC uxth ip, ip + 3168 00ce A4F82AC0 strh ip, [r4, #42] @ movhi +1646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3169 .loc 1 1646 7 is_stmt 1 view .LVU1062 +1646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3170 .loc 1 1646 11 is_stmt 0 view .LVU1063 + 3171 00d2 238D ldrh r3, [r4, #40] +1646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3172 .loc 1 1646 21 view .LVU1064 + 3173 00d4 013B subs r3, r3, #1 + 3174 00d6 2385 strh r3, [r4, #40] @ movhi + 3175 00d8 E0E7 b .L221 + 3176 .L231: +1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 3177 .loc 1 1611 7 is_stmt 1 view .LVU1065 +1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 3178 .loc 1 1611 11 is_stmt 0 view .LVU1066 + 3179 00da 2268 ldr r2, [r4] +1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 3180 .loc 1 1611 21 view .LVU1067 + 3181 00dc 5368 ldr r3, [r2, #4] +1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 3182 .loc 1 1611 27 view .LVU1068 + 3183 00de 43F40043 orr r3, r3, #32768 + 3184 00e2 5360 str r3, [r2, #4] +1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3185 .loc 1 1612 7 is_stmt 1 view .LVU1069 +1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3186 .loc 1 1612 14 is_stmt 0 view .LVU1070 + 3187 00e4 0120 movs r0, #1 + 3188 00e6 48E0 b .L218 + 3189 .L233: +1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3190 .loc 1 1621 9 is_stmt 1 view .LVU1071 +1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3191 .loc 1 1621 13 is_stmt 0 view .LVU1072 + 3192 00e8 2268 ldr r2, [r4] +1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3193 .loc 1 1621 23 view .LVU1073 + 3194 00ea 5368 ldr r3, [r2, #4] +1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3195 .loc 1 1621 29 view .LVU1074 + 3196 00ec 43F40043 orr r3, r3, #32768 + 3197 00f0 5360 str r3, [r2, #4] +1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3198 .loc 1 1624 9 is_stmt 1 view .LVU1075 +1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3199 .loc 1 1624 13 is_stmt 0 view .LVU1076 + ARM GAS /tmp/ccSHpINd.s page 206 + + + 3200 00f2 2368 ldr r3, [r4] + 3201 00f4 9A69 ldr r2, [r3, #24] +1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3202 .loc 1 1624 12 view .LVU1077 + 3203 00f6 12F0040F tst r2, #4 + 3204 00fa 0DD0 beq .L223 +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3205 .loc 1 1627 11 is_stmt 1 view .LVU1078 +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3206 .loc 1 1627 52 is_stmt 0 view .LVU1079 + 3207 00fc 5A6A ldr r2, [r3, #36] +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3208 .loc 1 1627 16 view .LVU1080 + 3209 00fe 636A ldr r3, [r4, #36] +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3210 .loc 1 1627 27 view .LVU1081 + 3211 0100 1A70 strb r2, [r3] +1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3212 .loc 1 1630 11 is_stmt 1 view .LVU1082 +1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3213 .loc 1 1630 15 is_stmt 0 view .LVU1083 + 3214 0102 636A ldr r3, [r4, #36] +1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3215 .loc 1 1630 25 view .LVU1084 + 3216 0104 0133 adds r3, r3, #1 + 3217 0106 6362 str r3, [r4, #36] +1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 3218 .loc 1 1632 11 is_stmt 1 view .LVU1085 +1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 3219 .loc 1 1632 15 is_stmt 0 view .LVU1086 + 3220 0108 638D ldrh r3, [r4, #42] + 3221 010a 9BB2 uxth r3, r3 +1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 3222 .loc 1 1632 26 view .LVU1087 + 3223 010c 013B subs r3, r3, #1 + 3224 010e 9BB2 uxth r3, r3 + 3225 0110 6385 strh r3, [r4, #42] @ movhi +1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3226 .loc 1 1633 11 is_stmt 1 view .LVU1088 +1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3227 .loc 1 1633 15 is_stmt 0 view .LVU1089 + 3228 0112 238D ldrh r3, [r4, #40] +1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3229 .loc 1 1633 25 view .LVU1090 + 3230 0114 013B subs r3, r3, #1 + 3231 0116 2385 strh r3, [r4, #40] @ movhi + 3232 .L223: +1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3233 .loc 1 1636 9 is_stmt 1 view .LVU1091 +1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3234 .loc 1 1636 16 is_stmt 0 view .LVU1092 + 3235 0118 0120 movs r0, #1 + 3236 011a 2EE0 b .L218 + 3237 .L232: +1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3238 .loc 1 1650 5 is_stmt 1 view .LVU1093 +1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 207 + + + 3239 .loc 1 1650 9 is_stmt 0 view .LVU1094 + 3240 011c 3246 mov r2, r6 + 3241 011e 2946 mov r1, r5 + 3242 0120 2046 mov r0, r4 + 3243 0122 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 3244 .LVL215: +1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3245 .loc 1 1650 8 discriminator 1 view .LVU1095 + 3246 0126 30B1 cbz r0, .L225 +1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 3247 .loc 1 1653 7 is_stmt 1 view .LVU1096 +1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 3248 .loc 1 1653 11 is_stmt 0 view .LVU1097 + 3249 0128 2268 ldr r2, [r4] +1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 3250 .loc 1 1653 21 view .LVU1098 + 3251 012a 5368 ldr r3, [r2, #4] +1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 3252 .loc 1 1653 27 view .LVU1099 + 3253 012c 43F40043 orr r3, r3, #32768 + 3254 0130 5360 str r3, [r2, #4] +1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3255 .loc 1 1654 7 is_stmt 1 view .LVU1100 +1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3256 .loc 1 1654 14 is_stmt 0 view .LVU1101 + 3257 0132 0120 movs r0, #1 + 3258 0134 21E0 b .L218 + 3259 .L225: +1658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3260 .loc 1 1658 5 is_stmt 1 view .LVU1102 + 3261 0136 2368 ldr r3, [r4] + 3262 0138 2022 movs r2, #32 + 3263 013a DA61 str r2, [r3, #28] +1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3264 .loc 1 1661 5 view .LVU1103 +1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3265 .loc 1 1661 9 is_stmt 0 view .LVU1104 + 3266 013c 0096 str r6, [sp] + 3267 013e 2B46 mov r3, r5 + 3268 0140 0122 movs r2, #1 + 3269 0142 4FF40041 mov r1, #32768 + 3270 0146 2046 mov r0, r4 + 3271 0148 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 3272 .LVL216: +1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3273 .loc 1 1661 8 discriminator 1 view .LVU1105 + 3274 014c 30B1 cbz r0, .L226 +1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 3275 .loc 1 1664 7 is_stmt 1 view .LVU1106 +1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 3276 .loc 1 1664 11 is_stmt 0 view .LVU1107 + 3277 014e 2268 ldr r2, [r4] +1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 3278 .loc 1 1664 21 view .LVU1108 + 3279 0150 5368 ldr r3, [r2, #4] +1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 3280 .loc 1 1664 27 view .LVU1109 + ARM GAS /tmp/ccSHpINd.s page 208 + + + 3281 0152 43F40043 orr r3, r3, #32768 + 3282 0156 5360 str r3, [r2, #4] +1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3283 .loc 1 1665 7 is_stmt 1 view .LVU1110 +1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3284 .loc 1 1665 14 is_stmt 0 view .LVU1111 + 3285 0158 0120 movs r0, #1 + 3286 015a 0EE0 b .L218 + 3287 .L226: +1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3288 .loc 1 1669 5 is_stmt 1 view .LVU1112 +1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3289 .loc 1 1669 9 is_stmt 0 view .LVU1113 + 3290 015c 2268 ldr r2, [r4] +1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3291 .loc 1 1669 19 view .LVU1114 + 3292 015e 5368 ldr r3, [r2, #4] +1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3293 .loc 1 1669 25 view .LVU1115 + 3294 0160 43F40043 orr r3, r3, #32768 + 3295 0164 5360 str r3, [r2, #4] +1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3296 .loc 1 1671 5 is_stmt 1 view .LVU1116 +1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3297 .loc 1 1671 17 is_stmt 0 view .LVU1117 + 3298 0166 2023 movs r3, #32 + 3299 0168 84F84130 strb r3, [r4, #65] +1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3300 .loc 1 1672 5 is_stmt 1 view .LVU1118 +1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3301 .loc 1 1672 17 is_stmt 0 view .LVU1119 + 3302 016c 0023 movs r3, #0 + 3303 016e 84F84230 strb r3, [r4, #66] +1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3304 .loc 1 1675 5 is_stmt 1 view .LVU1120 +1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3305 .loc 1 1675 5 view .LVU1121 + 3306 0172 84F84030 strb r3, [r4, #64] +1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3307 .loc 1 1675 5 view .LVU1122 +1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3308 .loc 1 1677 5 view .LVU1123 +1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3309 .loc 1 1677 12 is_stmt 0 view .LVU1124 + 3310 0176 00E0 b .L218 + 3311 .LVL217: + 3312 .L227: +1681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3313 .loc 1 1681 12 view .LVU1125 + 3314 0178 0220 movs r0, #2 + 3315 .LVL218: + 3316 .L218: +1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3317 .loc 1 1683 1 view .LVU1126 + 3318 017a 02B0 add sp, sp, #8 + 3319 .LCFI33: + 3320 .cfi_remember_state + ARM GAS /tmp/ccSHpINd.s page 209 + + + 3321 .cfi_def_cfa_offset 24 + 3322 @ sp needed + 3323 017c BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 3324 .LVL219: + 3325 .L228: + 3326 .LCFI34: + 3327 .cfi_restore_state +1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3328 .loc 1 1578 5 discriminator 1 view .LVU1127 + 3329 0180 0220 movs r0, #2 + 3330 .LVL220: +1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3331 .loc 1 1578 5 discriminator 1 view .LVU1128 + 3332 0182 FAE7 b .L218 + 3333 .cfi_endproc + 3334 .LFE148: + 3336 .section .text.HAL_I2C_Master_Transmit_IT,"ax",%progbits + 3337 .align 1 + 3338 .global HAL_I2C_Master_Transmit_IT + 3339 .syntax unified + 3340 .thumb + 3341 .thumb_func + 3343 HAL_I2C_Master_Transmit_IT: + 3344 .LVL221: + 3345 .LFB149: +1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; + 3346 .loc 1 1697 1 is_stmt 1 view -0 + 3347 .cfi_startproc + 3348 @ args = 0, pretend = 0, frame = 0 + 3349 @ frame_needed = 0, uses_anonymous_args = 0 +1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; + 3350 .loc 1 1697 1 is_stmt 0 view .LVU1130 + 3351 0000 30B5 push {r4, r5, lr} + 3352 .LCFI35: + 3353 .cfi_def_cfa_offset 12 + 3354 .cfi_offset 4, -12 + 3355 .cfi_offset 5, -8 + 3356 .cfi_offset 14, -4 + 3357 0002 83B0 sub sp, sp, #12 + 3358 .LCFI36: + 3359 .cfi_def_cfa_offset 24 + 3360 0004 0446 mov r4, r0 +1698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3361 .loc 1 1698 3 is_stmt 1 view .LVU1131 +1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3362 .loc 1 1700 3 view .LVU1132 +1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3363 .loc 1 1700 11 is_stmt 0 view .LVU1133 + 3364 0006 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 3365 .LVL222: +1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3366 .loc 1 1700 11 view .LVU1134 + 3367 000a C0B2 uxtb r0, r0 +1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3368 .loc 1 1700 6 view .LVU1135 + 3369 000c 2028 cmp r0, #32 + 3370 000e 4ED1 bne .L240 + ARM GAS /tmp/ccSHpINd.s page 210 + + +1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3371 .loc 1 1702 5 is_stmt 1 view .LVU1136 +1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3372 .loc 1 1702 9 is_stmt 0 view .LVU1137 + 3373 0010 2068 ldr r0, [r4] + 3374 0012 8569 ldr r5, [r0, #24] +1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3375 .loc 1 1702 8 view .LVU1138 + 3376 0014 15F4004F tst r5, #32768 + 3377 0018 4BD1 bne .L241 +1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3378 .loc 1 1708 5 is_stmt 1 view .LVU1139 +1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3379 .loc 1 1708 5 view .LVU1140 + 3380 001a 94F84050 ldrb r5, [r4, #64] @ zero_extendqisi2 + 3381 001e 012D cmp r5, #1 + 3382 0020 49D0 beq .L242 +1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3383 .loc 1 1708 5 discriminator 2 view .LVU1141 + 3384 0022 0125 movs r5, #1 + 3385 0024 84F84050 strb r5, [r4, #64] +1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3386 .loc 1 1708 5 discriminator 2 view .LVU1142 +1710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3387 .loc 1 1710 5 view .LVU1143 +1710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3388 .loc 1 1710 23 is_stmt 0 view .LVU1144 + 3389 0028 2125 movs r5, #33 + 3390 002a 84F84150 strb r5, [r4, #65] +1711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3391 .loc 1 1711 5 is_stmt 1 view .LVU1145 +1711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3392 .loc 1 1711 23 is_stmt 0 view .LVU1146 + 3393 002e 1025 movs r5, #16 + 3394 0030 84F84250 strb r5, [r4, #66] +1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3395 .loc 1 1712 5 is_stmt 1 view .LVU1147 +1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3396 .loc 1 1712 23 is_stmt 0 view .LVU1148 + 3397 0034 0025 movs r5, #0 + 3398 0036 6564 str r5, [r4, #68] +1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3399 .loc 1 1715 5 is_stmt 1 view .LVU1149 +1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3400 .loc 1 1715 23 is_stmt 0 view .LVU1150 + 3401 0038 6262 str r2, [r4, #36] +1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3402 .loc 1 1716 5 is_stmt 1 view .LVU1151 +1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3403 .loc 1 1716 23 is_stmt 0 view .LVU1152 + 3404 003a 6385 strh r3, [r4, #42] @ movhi +1717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3405 .loc 1 1717 5 is_stmt 1 view .LVU1153 +1717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3406 .loc 1 1717 23 is_stmt 0 view .LVU1154 + 3407 003c 1F4B ldr r3, .L244 + 3408 .LVL223: + ARM GAS /tmp/ccSHpINd.s page 211 + + +1717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3409 .loc 1 1717 23 view .LVU1155 + 3410 003e E362 str r3, [r4, #44] + 3411 .LVL224: +1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3412 .loc 1 1718 5 is_stmt 1 view .LVU1156 +1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3413 .loc 1 1718 23 is_stmt 0 view .LVU1157 + 3414 0040 1F4B ldr r3, .L244+4 + 3415 0042 6363 str r3, [r4, #52] +1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3416 .loc 1 1720 5 is_stmt 1 view .LVU1158 +1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3417 .loc 1 1720 13 is_stmt 0 view .LVU1159 + 3418 0044 638D ldrh r3, [r4, #42] + 3419 0046 9BB2 uxth r3, r3 +1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3420 .loc 1 1720 8 view .LVU1160 + 3421 0048 FF2B cmp r3, #255 + 3422 004a 24D9 bls .L236 +1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3423 .loc 1 1722 7 is_stmt 1 view .LVU1161 +1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3424 .loc 1 1722 22 is_stmt 0 view .LVU1162 + 3425 004c FF23 movs r3, #255 + 3426 004e 2385 strh r3, [r4, #40] @ movhi +1723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3427 .loc 1 1723 7 is_stmt 1 view .LVU1163 + 3428 .LVL225: +1723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3429 .loc 1 1723 16 is_stmt 0 view .LVU1164 + 3430 0050 4FF08073 mov r3, #16777216 + 3431 .LVL226: + 3432 .L237: +1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3433 .loc 1 1733 5 is_stmt 1 view .LVU1165 +1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3434 .loc 1 1733 13 is_stmt 0 view .LVU1166 + 3435 0054 258D ldrh r5, [r4, #40] +1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3436 .loc 1 1733 8 view .LVU1167 + 3437 0056 1DB3 cbz r5, .L238 +1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3438 .loc 1 1737 7 is_stmt 1 view .LVU1168 +1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3439 .loc 1 1737 30 is_stmt 0 view .LVU1169 + 3440 0058 1278 ldrb r2, [r2] @ zero_extendqisi2 + 3441 .LVL227: +1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3442 .loc 1 1737 28 view .LVU1170 + 3443 005a 8262 str r2, [r0, #40] + 3444 .LVL228: +1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3445 .loc 1 1740 7 is_stmt 1 view .LVU1171 +1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3446 .loc 1 1740 11 is_stmt 0 view .LVU1172 + 3447 005c 626A ldr r2, [r4, #36] + ARM GAS /tmp/ccSHpINd.s page 212 + + +1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3448 .loc 1 1740 21 view .LVU1173 + 3449 005e 0132 adds r2, r2, #1 + 3450 0060 6262 str r2, [r4, #36] +1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 3451 .loc 1 1742 7 is_stmt 1 view .LVU1174 +1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 3452 .loc 1 1742 11 is_stmt 0 view .LVU1175 + 3453 0062 628D ldrh r2, [r4, #42] + 3454 0064 92B2 uxth r2, r2 +1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 3455 .loc 1 1742 22 view .LVU1176 + 3456 0066 013A subs r2, r2, #1 + 3457 0068 92B2 uxth r2, r2 + 3458 006a 6285 strh r2, [r4, #42] @ movhi +1743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3459 .loc 1 1743 7 is_stmt 1 view .LVU1177 +1743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3460 .loc 1 1743 11 is_stmt 0 view .LVU1178 + 3461 006c 228D ldrh r2, [r4, #40] +1743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3462 .loc 1 1743 21 view .LVU1179 + 3463 006e 013A subs r2, r2, #1 + 3464 0070 92B2 uxth r2, r2 + 3465 0072 2285 strh r2, [r4, #40] @ movhi +1745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 3466 .loc 1 1745 7 is_stmt 1 view .LVU1180 + 3467 0074 0132 adds r2, r2, #1 + 3468 0076 1348 ldr r0, .L244+8 + 3469 0078 0090 str r0, [sp] + 3470 007a D2B2 uxtb r2, r2 + 3471 007c 2046 mov r0, r4 + 3472 007e FFF7FEFF bl I2C_TransferConfig + 3473 .LVL229: + 3474 .L239: +1755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3475 .loc 1 1755 5 view .LVU1181 +1755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3476 .loc 1 1755 5 view .LVU1182 + 3477 0082 0025 movs r5, #0 + 3478 0084 84F84050 strb r5, [r4, #64] +1755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3479 .loc 1 1755 5 view .LVU1183 +1765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3480 .loc 1 1765 5 view .LVU1184 + 3481 0088 0121 movs r1, #1 + 3482 008a 2046 mov r0, r4 + 3483 008c FFF7FEFF bl I2C_Enable_IRQ + 3484 .LVL230: +1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3485 .loc 1 1767 5 view .LVU1185 +1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3486 .loc 1 1767 12 is_stmt 0 view .LVU1186 + 3487 0090 2846 mov r0, r5 + 3488 .LVL231: + 3489 .L235: +1773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 213 + + + 3490 .loc 1 1773 1 view .LVU1187 + 3491 0092 03B0 add sp, sp, #12 + 3492 .LCFI37: + 3493 .cfi_remember_state + 3494 .cfi_def_cfa_offset 12 + 3495 @ sp needed + 3496 0094 30BD pop {r4, r5, pc} + 3497 .LVL232: + 3498 .L236: + 3499 .LCFI38: + 3500 .cfi_restore_state +1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3501 .loc 1 1727 7 is_stmt 1 view .LVU1188 +1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3502 .loc 1 1727 28 is_stmt 0 view .LVU1189 + 3503 0096 638D ldrh r3, [r4, #42] +1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3504 .loc 1 1727 22 view .LVU1190 + 3505 0098 2385 strh r3, [r4, #40] @ movhi +1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3506 .loc 1 1728 7 is_stmt 1 view .LVU1191 + 3507 .LVL233: +1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3508 .loc 1 1728 16 is_stmt 0 view .LVU1192 + 3509 009a 4FF00073 mov r3, #33554432 + 3510 009e D9E7 b .L237 + 3511 .LVL234: + 3512 .L238: +1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 3513 .loc 1 1750 7 is_stmt 1 view .LVU1193 + 3514 00a0 084A ldr r2, .L244+8 + 3515 .LVL235: +1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 3516 .loc 1 1750 7 is_stmt 0 view .LVU1194 + 3517 00a2 0092 str r2, [sp] + 3518 .LVL236: +1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 3519 .loc 1 1750 7 view .LVU1195 + 3520 00a4 EAB2 uxtb r2, r5 + 3521 00a6 2046 mov r0, r4 + 3522 00a8 FFF7FEFF bl I2C_TransferConfig + 3523 .LVL237: +1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 3524 .loc 1 1750 7 view .LVU1196 + 3525 00ac E9E7 b .L239 + 3526 .LVL238: + 3527 .L240: +1771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3528 .loc 1 1771 12 view .LVU1197 + 3529 00ae 0220 movs r0, #2 + 3530 00b0 EFE7 b .L235 + 3531 .L241: +1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3532 .loc 1 1704 14 view .LVU1198 + 3533 00b2 0220 movs r0, #2 + 3534 00b4 EDE7 b .L235 + 3535 .L242: + ARM GAS /tmp/ccSHpINd.s page 214 + + +1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3536 .loc 1 1708 5 discriminator 1 view .LVU1199 + 3537 00b6 0220 movs r0, #2 + 3538 00b8 EBE7 b .L235 + 3539 .L245: + 3540 00ba 00BF .align 2 + 3541 .L244: + 3542 00bc 0000FFFF .word -65536 + 3543 00c0 00000000 .word I2C_Master_ISR_IT + 3544 00c4 00200080 .word -2147475456 + 3545 .cfi_endproc + 3546 .LFE149: + 3548 .section .text.HAL_I2C_Master_Receive_IT,"ax",%progbits + 3549 .align 1 + 3550 .global HAL_I2C_Master_Receive_IT + 3551 .syntax unified + 3552 .thumb + 3553 .thumb_func + 3555 HAL_I2C_Master_Receive_IT: + 3556 .LVL239: + 3557 .LFB150: +1787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; + 3558 .loc 1 1787 1 is_stmt 1 view -0 + 3559 .cfi_startproc + 3560 @ args = 0, pretend = 0, frame = 0 + 3561 @ frame_needed = 0, uses_anonymous_args = 0 +1787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; + 3562 .loc 1 1787 1 is_stmt 0 view .LVU1201 + 3563 0000 30B5 push {r4, r5, lr} + 3564 .LCFI39: + 3565 .cfi_def_cfa_offset 12 + 3566 .cfi_offset 4, -12 + 3567 .cfi_offset 5, -8 + 3568 .cfi_offset 14, -4 + 3569 0002 83B0 sub sp, sp, #12 + 3570 .LCFI40: + 3571 .cfi_def_cfa_offset 24 + 3572 0004 0446 mov r4, r0 +1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3573 .loc 1 1788 3 is_stmt 1 view .LVU1202 +1790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3574 .loc 1 1790 3 view .LVU1203 +1790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3575 .loc 1 1790 11 is_stmt 0 view .LVU1204 + 3576 0006 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 3577 .LVL240: +1790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3578 .loc 1 1790 11 view .LVU1205 + 3579 000a C0B2 uxtb r0, r0 +1790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3580 .loc 1 1790 6 view .LVU1206 + 3581 000c 2028 cmp r0, #32 + 3582 000e 37D1 bne .L250 +1792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3583 .loc 1 1792 5 is_stmt 1 view .LVU1207 +1792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3584 .loc 1 1792 9 is_stmt 0 view .LVU1208 + ARM GAS /tmp/ccSHpINd.s page 215 + + + 3585 0010 2068 ldr r0, [r4] + 3586 0012 8069 ldr r0, [r0, #24] +1792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3587 .loc 1 1792 8 view .LVU1209 + 3588 0014 10F4004F tst r0, #32768 + 3589 0018 34D1 bne .L251 +1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3590 .loc 1 1798 5 is_stmt 1 view .LVU1210 +1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3591 .loc 1 1798 5 view .LVU1211 + 3592 001a 94F84000 ldrb r0, [r4, #64] @ zero_extendqisi2 + 3593 001e 0128 cmp r0, #1 + 3594 0020 32D0 beq .L252 +1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3595 .loc 1 1798 5 discriminator 2 view .LVU1212 + 3596 0022 0120 movs r0, #1 + 3597 0024 84F84000 strb r0, [r4, #64] +1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3598 .loc 1 1798 5 discriminator 2 view .LVU1213 +1800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3599 .loc 1 1800 5 view .LVU1214 +1800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3600 .loc 1 1800 23 is_stmt 0 view .LVU1215 + 3601 0028 2220 movs r0, #34 + 3602 002a 84F84100 strb r0, [r4, #65] +1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3603 .loc 1 1801 5 is_stmt 1 view .LVU1216 +1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3604 .loc 1 1801 23 is_stmt 0 view .LVU1217 + 3605 002e 1020 movs r0, #16 + 3606 0030 84F84200 strb r0, [r4, #66] +1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3607 .loc 1 1802 5 is_stmt 1 view .LVU1218 +1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3608 .loc 1 1802 23 is_stmt 0 view .LVU1219 + 3609 0034 0020 movs r0, #0 + 3610 0036 6064 str r0, [r4, #68] +1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3611 .loc 1 1805 5 is_stmt 1 view .LVU1220 +1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3612 .loc 1 1805 23 is_stmt 0 view .LVU1221 + 3613 0038 6262 str r2, [r4, #36] +1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3614 .loc 1 1806 5 is_stmt 1 view .LVU1222 +1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3615 .loc 1 1806 23 is_stmt 0 view .LVU1223 + 3616 003a 6385 strh r3, [r4, #42] @ movhi +1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3617 .loc 1 1807 5 is_stmt 1 view .LVU1224 +1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3618 .loc 1 1807 23 is_stmt 0 view .LVU1225 + 3619 003c 134B ldr r3, .L254 + 3620 .LVL241: +1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3621 .loc 1 1807 23 view .LVU1226 + 3622 003e E362 str r3, [r4, #44] + 3623 .LVL242: + ARM GAS /tmp/ccSHpINd.s page 216 + + +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3624 .loc 1 1808 5 is_stmt 1 view .LVU1227 +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3625 .loc 1 1808 23 is_stmt 0 view .LVU1228 + 3626 0040 134B ldr r3, .L254+4 + 3627 0042 6363 str r3, [r4, #52] +1810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3628 .loc 1 1810 5 is_stmt 1 view .LVU1229 +1810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3629 .loc 1 1810 13 is_stmt 0 view .LVU1230 + 3630 0044 638D ldrh r3, [r4, #42] + 3631 0046 9BB2 uxth r3, r3 +1810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3632 .loc 1 1810 8 view .LVU1231 + 3633 0048 FF2B cmp r3, #255 + 3634 004a 14D9 bls .L248 +1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3635 .loc 1 1812 7 is_stmt 1 view .LVU1232 +1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3636 .loc 1 1812 22 is_stmt 0 view .LVU1233 + 3637 004c 0123 movs r3, #1 + 3638 004e 2385 strh r3, [r4, #40] @ movhi +1813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3639 .loc 1 1813 7 is_stmt 1 view .LVU1234 + 3640 .LVL243: +1813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3641 .loc 1 1813 16 is_stmt 0 view .LVU1235 + 3642 0050 4FF08073 mov r3, #16777216 + 3643 .LVL244: + 3644 .L249: +1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3645 .loc 1 1823 5 is_stmt 1 view .LVU1236 + 3646 0054 0F4A ldr r2, .L254+8 + 3647 .LVL245: +1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3648 .loc 1 1823 5 is_stmt 0 view .LVU1237 + 3649 0056 0092 str r2, [sp] + 3650 .LVL246: +1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3651 .loc 1 1823 5 view .LVU1238 + 3652 0058 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 3653 005c 2046 mov r0, r4 + 3654 005e FFF7FEFF bl I2C_TransferConfig + 3655 .LVL247: +1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3656 .loc 1 1826 5 is_stmt 1 view .LVU1239 +1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3657 .loc 1 1826 5 view .LVU1240 + 3658 0062 0025 movs r5, #0 + 3659 0064 84F84050 strb r5, [r4, #64] +1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3660 .loc 1 1826 5 view .LVU1241 +1836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3661 .loc 1 1836 5 view .LVU1242 + 3662 0068 0221 movs r1, #2 + 3663 006a 2046 mov r0, r4 + 3664 006c FFF7FEFF bl I2C_Enable_IRQ + ARM GAS /tmp/ccSHpINd.s page 217 + + + 3665 .LVL248: +1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3666 .loc 1 1838 5 view .LVU1243 +1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3667 .loc 1 1838 12 is_stmt 0 view .LVU1244 + 3668 0070 2846 mov r0, r5 + 3669 .LVL249: + 3670 .L247: +1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3671 .loc 1 1844 1 view .LVU1245 + 3672 0072 03B0 add sp, sp, #12 + 3673 .LCFI41: + 3674 .cfi_remember_state + 3675 .cfi_def_cfa_offset 12 + 3676 @ sp needed + 3677 0074 30BD pop {r4, r5, pc} + 3678 .LVL250: + 3679 .L248: + 3680 .LCFI42: + 3681 .cfi_restore_state +1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3682 .loc 1 1817 7 is_stmt 1 view .LVU1246 +1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3683 .loc 1 1817 28 is_stmt 0 view .LVU1247 + 3684 0076 638D ldrh r3, [r4, #42] +1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3685 .loc 1 1817 22 view .LVU1248 + 3686 0078 2385 strh r3, [r4, #40] @ movhi +1818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3687 .loc 1 1818 7 is_stmt 1 view .LVU1249 + 3688 .LVL251: +1818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3689 .loc 1 1818 16 is_stmt 0 view .LVU1250 + 3690 007a 4FF00073 mov r3, #33554432 + 3691 007e E9E7 b .L249 + 3692 .LVL252: + 3693 .L250: +1842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3694 .loc 1 1842 12 view .LVU1251 + 3695 0080 0220 movs r0, #2 + 3696 0082 F6E7 b .L247 + 3697 .L251: +1794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3698 .loc 1 1794 14 view .LVU1252 + 3699 0084 0220 movs r0, #2 + 3700 0086 F4E7 b .L247 + 3701 .L252: +1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3702 .loc 1 1798 5 discriminator 1 view .LVU1253 + 3703 0088 0220 movs r0, #2 + 3704 008a F2E7 b .L247 + 3705 .L255: + 3706 .align 2 + 3707 .L254: + 3708 008c 0000FFFF .word -65536 + 3709 0090 00000000 .word I2C_Master_ISR_IT + 3710 0094 00240080 .word -2147474432 + ARM GAS /tmp/ccSHpINd.s page 218 + + + 3711 .cfi_endproc + 3712 .LFE150: + 3714 .section .text.HAL_I2C_Slave_Transmit_IT,"ax",%progbits + 3715 .align 1 + 3716 .global HAL_I2C_Slave_Transmit_IT + 3717 .syntax unified + 3718 .thumb + 3719 .thumb_func + 3721 HAL_I2C_Slave_Transmit_IT: + 3722 .LVL253: + 3723 .LFB151: +1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3724 .loc 1 1855 1 is_stmt 1 view -0 + 3725 .cfi_startproc + 3726 @ args = 0, pretend = 0, frame = 0 + 3727 @ frame_needed = 0, uses_anonymous_args = 0 +1856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3728 .loc 1 1856 3 view .LVU1255 +1856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3729 .loc 1 1856 11 is_stmt 0 view .LVU1256 + 3730 0000 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 3731 0004 DBB2 uxtb r3, r3 +1856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3732 .loc 1 1856 6 view .LVU1257 + 3733 0006 202B cmp r3, #32 + 3734 0008 38D1 bne .L259 +1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3735 .loc 1 1859 5 is_stmt 1 view .LVU1258 +1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3736 .loc 1 1859 5 view .LVU1259 + 3737 000a 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 3738 000e 012B cmp r3, #1 + 3739 0010 36D0 beq .L260 +1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3740 .loc 1 1855 1 is_stmt 0 view .LVU1260 + 3741 0012 10B5 push {r4, lr} + 3742 .LCFI43: + 3743 .cfi_def_cfa_offset 8 + 3744 .cfi_offset 4, -8 + 3745 .cfi_offset 14, -4 +1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3746 .loc 1 1859 5 is_stmt 1 discriminator 2 view .LVU1261 + 3747 0014 0123 movs r3, #1 + 3748 0016 80F84030 strb r3, [r0, #64] +1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3749 .loc 1 1859 5 discriminator 2 view .LVU1262 +1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3750 .loc 1 1861 5 view .LVU1263 +1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3751 .loc 1 1861 23 is_stmt 0 view .LVU1264 + 3752 001a 2123 movs r3, #33 + 3753 001c 80F84130 strb r3, [r0, #65] +1862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3754 .loc 1 1862 5 is_stmt 1 view .LVU1265 +1862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3755 .loc 1 1862 23 is_stmt 0 view .LVU1266 + 3756 0020 2023 movs r3, #32 + ARM GAS /tmp/ccSHpINd.s page 219 + + + 3757 0022 80F84230 strb r3, [r0, #66] +1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3758 .loc 1 1863 5 is_stmt 1 view .LVU1267 +1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3759 .loc 1 1863 23 is_stmt 0 view .LVU1268 + 3760 0026 0023 movs r3, #0 + 3761 0028 4364 str r3, [r0, #68] +1866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3762 .loc 1 1866 5 is_stmt 1 view .LVU1269 +1866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3763 .loc 1 1866 9 is_stmt 0 view .LVU1270 + 3764 002a 0468 ldr r4, [r0] +1866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3765 .loc 1 1866 19 view .LVU1271 + 3766 002c 6368 ldr r3, [r4, #4] +1866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3767 .loc 1 1866 25 view .LVU1272 + 3768 002e 23F40043 bic r3, r3, #32768 + 3769 0032 6360 str r3, [r4, #4] +1869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3770 .loc 1 1869 5 is_stmt 1 view .LVU1273 +1869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3771 .loc 1 1869 23 is_stmt 0 view .LVU1274 + 3772 0034 4162 str r1, [r0, #36] +1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3773 .loc 1 1870 5 is_stmt 1 view .LVU1275 +1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3774 .loc 1 1870 23 is_stmt 0 view .LVU1276 + 3775 0036 4285 strh r2, [r0, #42] @ movhi +1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3776 .loc 1 1871 5 is_stmt 1 view .LVU1277 +1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3777 .loc 1 1871 29 is_stmt 0 view .LVU1278 + 3778 0038 438D ldrh r3, [r0, #42] +1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3779 .loc 1 1871 23 view .LVU1279 + 3780 003a 0385 strh r3, [r0, #40] @ movhi +1872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 3781 .loc 1 1872 5 is_stmt 1 view .LVU1280 +1872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 3782 .loc 1 1872 23 is_stmt 0 view .LVU1281 + 3783 003c 114B ldr r3, .L266 + 3784 003e C362 str r3, [r0, #44] +1873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3785 .loc 1 1873 5 is_stmt 1 view .LVU1282 +1873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3786 .loc 1 1873 23 is_stmt 0 view .LVU1283 + 3787 0040 114B ldr r3, .L266+4 + 3788 0042 4363 str r3, [r0, #52] +1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3789 .loc 1 1876 5 is_stmt 1 view .LVU1284 +1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3790 .loc 1 1876 19 is_stmt 0 view .LVU1285 + 3791 0044 036A ldr r3, [r0, #32] +1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3792 .loc 1 1876 8 view .LVU1286 + 3793 0046 B3F5003F cmp r3, #131072 + ARM GAS /tmp/ccSHpINd.s page 220 + + + 3794 004a 08D0 beq .L265 + 3795 .LVL254: + 3796 .L258: +1890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3797 .loc 1 1890 5 is_stmt 1 view .LVU1287 +1890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3798 .loc 1 1890 5 view .LVU1288 + 3799 004c 0024 movs r4, #0 + 3800 004e 80F84040 strb r4, [r0, #64] +1890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3801 .loc 1 1890 5 view .LVU1289 +1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3802 .loc 1 1900 5 view .LVU1290 + 3803 0052 48F20101 movw r1, #32769 + 3804 .LVL255: +1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3805 .loc 1 1900 5 is_stmt 0 view .LVU1291 + 3806 0056 FFF7FEFF bl I2C_Enable_IRQ + 3807 .LVL256: +1902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3808 .loc 1 1902 5 is_stmt 1 view .LVU1292 +1902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3809 .loc 1 1902 12 is_stmt 0 view .LVU1293 + 3810 005a 2046 mov r0, r4 +1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3811 .loc 1 1908 1 view .LVU1294 + 3812 005c 10BD pop {r4, pc} + 3813 .LVL257: + 3814 .L265: +1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3815 .loc 1 1880 7 is_stmt 1 view .LVU1295 +1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3816 .loc 1 1880 11 is_stmt 0 view .LVU1296 + 3817 005e 0368 ldr r3, [r0] +1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3818 .loc 1 1880 30 view .LVU1297 + 3819 0060 0A78 ldrb r2, [r1] @ zero_extendqisi2 + 3820 .LVL258: +1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3821 .loc 1 1880 28 view .LVU1298 + 3822 0062 9A62 str r2, [r3, #40] +1883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3823 .loc 1 1883 7 is_stmt 1 view .LVU1299 +1883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3824 .loc 1 1883 11 is_stmt 0 view .LVU1300 + 3825 0064 436A ldr r3, [r0, #36] +1883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3826 .loc 1 1883 21 view .LVU1301 + 3827 0066 0133 adds r3, r3, #1 + 3828 0068 4362 str r3, [r0, #36] +1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 3829 .loc 1 1885 7 is_stmt 1 view .LVU1302 +1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 3830 .loc 1 1885 11 is_stmt 0 view .LVU1303 + 3831 006a 438D ldrh r3, [r0, #42] + 3832 006c 9BB2 uxth r3, r3 +1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + ARM GAS /tmp/ccSHpINd.s page 221 + + + 3833 .loc 1 1885 22 view .LVU1304 + 3834 006e 013B subs r3, r3, #1 + 3835 0070 9BB2 uxth r3, r3 + 3836 0072 4385 strh r3, [r0, #42] @ movhi +1886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3837 .loc 1 1886 7 is_stmt 1 view .LVU1305 +1886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3838 .loc 1 1886 11 is_stmt 0 view .LVU1306 + 3839 0074 038D ldrh r3, [r0, #40] +1886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3840 .loc 1 1886 21 view .LVU1307 + 3841 0076 013B subs r3, r3, #1 + 3842 0078 0385 strh r3, [r0, #40] @ movhi + 3843 007a E7E7 b .L258 + 3844 .LVL259: + 3845 .L259: + 3846 .LCFI44: + 3847 .cfi_def_cfa_offset 0 + 3848 .cfi_restore 4 + 3849 .cfi_restore 14 +1906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3850 .loc 1 1906 12 view .LVU1308 + 3851 007c 0220 movs r0, #2 + 3852 .LVL260: +1906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3853 .loc 1 1906 12 view .LVU1309 + 3854 007e 7047 bx lr + 3855 .LVL261: + 3856 .L260: +1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3857 .loc 1 1859 5 discriminator 1 view .LVU1310 + 3858 0080 0220 movs r0, #2 + 3859 .LVL262: +1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3860 .loc 1 1908 1 view .LVU1311 + 3861 0082 7047 bx lr + 3862 .L267: + 3863 .align 2 + 3864 .L266: + 3865 0084 0000FFFF .word -65536 + 3866 0088 00000000 .word I2C_Slave_ISR_IT + 3867 .cfi_endproc + 3868 .LFE151: + 3870 .section .text.HAL_I2C_Slave_Receive_IT,"ax",%progbits + 3871 .align 1 + 3872 .global HAL_I2C_Slave_Receive_IT + 3873 .syntax unified + 3874 .thumb + 3875 .thumb_func + 3877 HAL_I2C_Slave_Receive_IT: + 3878 .LVL263: + 3879 .LFB152: +1919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3880 .loc 1 1919 1 is_stmt 1 view -0 + 3881 .cfi_startproc + 3882 @ args = 0, pretend = 0, frame = 0 + 3883 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccSHpINd.s page 222 + + +1919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3884 .loc 1 1919 1 is_stmt 0 view .LVU1313 + 3885 0000 38B5 push {r3, r4, r5, lr} + 3886 .LCFI45: + 3887 .cfi_def_cfa_offset 16 + 3888 .cfi_offset 3, -16 + 3889 .cfi_offset 4, -12 + 3890 .cfi_offset 5, -8 + 3891 .cfi_offset 14, -4 +1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3892 .loc 1 1920 3 is_stmt 1 view .LVU1314 +1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3893 .loc 1 1920 11 is_stmt 0 view .LVU1315 + 3894 0002 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 3895 0006 DBB2 uxtb r3, r3 +1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 3896 .loc 1 1920 6 view .LVU1316 + 3897 0008 202B cmp r3, #32 + 3898 000a 23D1 bne .L270 +1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3899 .loc 1 1923 5 is_stmt 1 view .LVU1317 +1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3900 .loc 1 1923 5 view .LVU1318 + 3901 000c 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 3902 0010 012B cmp r3, #1 + 3903 0012 21D0 beq .L271 +1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3904 .loc 1 1923 5 discriminator 2 view .LVU1319 + 3905 0014 0123 movs r3, #1 + 3906 0016 80F84030 strb r3, [r0, #64] +1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3907 .loc 1 1923 5 discriminator 2 view .LVU1320 +1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3908 .loc 1 1925 5 view .LVU1321 +1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3909 .loc 1 1925 23 is_stmt 0 view .LVU1322 + 3910 001a 2223 movs r3, #34 + 3911 001c 80F84130 strb r3, [r0, #65] +1926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3912 .loc 1 1926 5 is_stmt 1 view .LVU1323 +1926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3913 .loc 1 1926 23 is_stmt 0 view .LVU1324 + 3914 0020 2023 movs r3, #32 + 3915 0022 80F84230 strb r3, [r0, #66] +1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3916 .loc 1 1927 5 is_stmt 1 view .LVU1325 +1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3917 .loc 1 1927 23 is_stmt 0 view .LVU1326 + 3918 0026 0024 movs r4, #0 + 3919 0028 4464 str r4, [r0, #68] +1930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3920 .loc 1 1930 5 is_stmt 1 view .LVU1327 +1930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3921 .loc 1 1930 9 is_stmt 0 view .LVU1328 + 3922 002a 0568 ldr r5, [r0] +1930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3923 .loc 1 1930 19 view .LVU1329 + ARM GAS /tmp/ccSHpINd.s page 223 + + + 3924 002c 6B68 ldr r3, [r5, #4] +1930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3925 .loc 1 1930 25 view .LVU1330 + 3926 002e 23F40043 bic r3, r3, #32768 + 3927 0032 6B60 str r3, [r5, #4] +1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3928 .loc 1 1933 5 is_stmt 1 view .LVU1331 +1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 3929 .loc 1 1933 23 is_stmt 0 view .LVU1332 + 3930 0034 4162 str r1, [r0, #36] +1934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3931 .loc 1 1934 5 is_stmt 1 view .LVU1333 +1934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3932 .loc 1 1934 23 is_stmt 0 view .LVU1334 + 3933 0036 4285 strh r2, [r0, #42] @ movhi +1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3934 .loc 1 1935 5 is_stmt 1 view .LVU1335 +1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3935 .loc 1 1935 29 is_stmt 0 view .LVU1336 + 3936 0038 438D ldrh r3, [r0, #42] +1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3937 .loc 1 1935 23 view .LVU1337 + 3938 003a 0385 strh r3, [r0, #40] @ movhi +1936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 3939 .loc 1 1936 5 is_stmt 1 view .LVU1338 +1936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 3940 .loc 1 1936 23 is_stmt 0 view .LVU1339 + 3941 003c 074B ldr r3, .L273 + 3942 003e C362 str r3, [r0, #44] +1937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3943 .loc 1 1937 5 is_stmt 1 view .LVU1340 +1937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3944 .loc 1 1937 23 is_stmt 0 view .LVU1341 + 3945 0040 074B ldr r3, .L273+4 + 3946 0042 4363 str r3, [r0, #52] +1940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3947 .loc 1 1940 5 is_stmt 1 view .LVU1342 +1940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3948 .loc 1 1940 5 view .LVU1343 + 3949 0044 80F84040 strb r4, [r0, #64] +1940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3950 .loc 1 1940 5 view .LVU1344 +1950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3951 .loc 1 1950 5 view .LVU1345 + 3952 0048 48F20201 movw r1, #32770 + 3953 .LVL264: +1950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3954 .loc 1 1950 5 is_stmt 0 view .LVU1346 + 3955 004c FFF7FEFF bl I2C_Enable_IRQ + 3956 .LVL265: +1952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3957 .loc 1 1952 5 is_stmt 1 view .LVU1347 +1952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3958 .loc 1 1952 12 is_stmt 0 view .LVU1348 + 3959 0050 2046 mov r0, r4 + 3960 .L269: +1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 224 + + + 3961 .loc 1 1958 1 view .LVU1349 + 3962 0052 38BD pop {r3, r4, r5, pc} + 3963 .LVL266: + 3964 .L270: +1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3965 .loc 1 1956 12 view .LVU1350 + 3966 0054 0220 movs r0, #2 + 3967 .LVL267: +1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 3968 .loc 1 1956 12 view .LVU1351 + 3969 0056 FCE7 b .L269 + 3970 .LVL268: + 3971 .L271: +1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3972 .loc 1 1923 5 discriminator 1 view .LVU1352 + 3973 0058 0220 movs r0, #2 + 3974 .LVL269: +1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 3975 .loc 1 1923 5 discriminator 1 view .LVU1353 + 3976 005a FAE7 b .L269 + 3977 .L274: + 3978 .align 2 + 3979 .L273: + 3980 005c 0000FFFF .word -65536 + 3981 0060 00000000 .word I2C_Slave_ISR_IT + 3982 .cfi_endproc + 3983 .LFE152: + 3985 .section .text.HAL_I2C_Master_Transmit_DMA,"ax",%progbits + 3986 .align 1 + 3987 .global HAL_I2C_Master_Transmit_DMA + 3988 .syntax unified + 3989 .thumb + 3990 .thumb_func + 3992 HAL_I2C_Master_Transmit_DMA: + 3993 .LVL270: + 3994 .LFB153: +1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; + 3995 .loc 1 1972 1 is_stmt 1 view -0 + 3996 .cfi_startproc + 3997 @ args = 0, pretend = 0, frame = 0 + 3998 @ frame_needed = 0, uses_anonymous_args = 0 +1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; + 3999 .loc 1 1972 1 is_stmt 0 view .LVU1355 + 4000 0000 70B5 push {r4, r5, r6, lr} + 4001 .LCFI46: + 4002 .cfi_def_cfa_offset 16 + 4003 .cfi_offset 4, -16 + 4004 .cfi_offset 5, -12 + 4005 .cfi_offset 6, -8 + 4006 .cfi_offset 14, -4 + 4007 0002 82B0 sub sp, sp, #8 + 4008 .LCFI47: + 4009 .cfi_def_cfa_offset 24 + 4010 0004 0446 mov r4, r0 +1973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 4011 .loc 1 1973 3 is_stmt 1 view .LVU1356 +1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t sizetoxfer = 0U; + ARM GAS /tmp/ccSHpINd.s page 225 + + + 4012 .loc 1 1974 3 view .LVU1357 +1975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4013 .loc 1 1975 3 view .LVU1358 + 4014 .LVL271: +1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4015 .loc 1 1977 3 view .LVU1359 +1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4016 .loc 1 1977 11 is_stmt 0 view .LVU1360 + 4017 0006 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 4018 .LVL272: +1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4019 .loc 1 1977 11 view .LVU1361 + 4020 000a C0B2 uxtb r0, r0 +1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4021 .loc 1 1977 6 view .LVU1362 + 4022 000c 2028 cmp r0, #32 + 4023 000e 40F09D80 bne .L285 + 4024 0012 0D46 mov r5, r1 +1979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4025 .loc 1 1979 5 is_stmt 1 view .LVU1363 +1979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4026 .loc 1 1979 9 is_stmt 0 view .LVU1364 + 4027 0014 2068 ldr r0, [r4] + 4028 0016 8169 ldr r1, [r0, #24] + 4029 .LVL273: +1979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4030 .loc 1 1979 8 view .LVU1365 + 4031 0018 11F40041 ands r1, r1, #32768 + 4032 001c 40F09980 bne .L286 +1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4033 .loc 1 1985 5 is_stmt 1 view .LVU1366 +1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4034 .loc 1 1985 5 view .LVU1367 + 4035 0020 94F84060 ldrb r6, [r4, #64] @ zero_extendqisi2 + 4036 0024 012E cmp r6, #1 + 4037 0026 00F09680 beq .L287 +1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4038 .loc 1 1985 5 discriminator 2 view .LVU1368 + 4039 002a 0126 movs r6, #1 + 4040 002c 84F84060 strb r6, [r4, #64] +1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4041 .loc 1 1985 5 discriminator 2 view .LVU1369 +1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 4042 .loc 1 1987 5 view .LVU1370 +1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 4043 .loc 1 1987 23 is_stmt 0 view .LVU1371 + 4044 0030 2126 movs r6, #33 + 4045 0032 84F84160 strb r6, [r4, #65] +1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4046 .loc 1 1988 5 is_stmt 1 view .LVU1372 +1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4047 .loc 1 1988 23 is_stmt 0 view .LVU1373 + 4048 0036 1026 movs r6, #16 + 4049 0038 84F84260 strb r6, [r4, #66] +1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4050 .loc 1 1989 5 is_stmt 1 view .LVU1374 +1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 226 + + + 4051 .loc 1 1989 23 is_stmt 0 view .LVU1375 + 4052 003c 0026 movs r6, #0 + 4053 003e 6664 str r6, [r4, #68] +1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 4054 .loc 1 1992 5 is_stmt 1 view .LVU1376 +1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 4055 .loc 1 1992 23 is_stmt 0 view .LVU1377 + 4056 0040 6262 str r2, [r4, #36] +1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4057 .loc 1 1993 5 is_stmt 1 view .LVU1378 +1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4058 .loc 1 1993 23 is_stmt 0 view .LVU1379 + 4059 0042 6385 strh r3, [r4, #42] @ movhi +1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 4060 .loc 1 1994 5 is_stmt 1 view .LVU1380 +1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 4061 .loc 1 1994 23 is_stmt 0 view .LVU1381 + 4062 0044 454B ldr r3, .L291 + 4063 .LVL274: +1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 4064 .loc 1 1994 23 view .LVU1382 + 4065 0046 E362 str r3, [r4, #44] + 4066 .LVL275: +1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4067 .loc 1 1995 5 is_stmt 1 view .LVU1383 +1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4068 .loc 1 1995 23 is_stmt 0 view .LVU1384 + 4069 0048 454B ldr r3, .L291+4 + 4070 004a 6363 str r3, [r4, #52] +1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4071 .loc 1 1997 5 is_stmt 1 view .LVU1385 +1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4072 .loc 1 1997 13 is_stmt 0 view .LVU1386 + 4073 004c 638D ldrh r3, [r4, #42] + 4074 004e 9BB2 uxth r3, r3 +1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4075 .loc 1 1997 8 view .LVU1387 + 4076 0050 FF2B cmp r3, #255 + 4077 0052 37D9 bls .L277 +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 4078 .loc 1 1999 7 is_stmt 1 view .LVU1388 +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 4079 .loc 1 1999 22 is_stmt 0 view .LVU1389 + 4080 0054 FF23 movs r3, #255 + 4081 0056 2385 strh r3, [r4, #40] @ movhi +2000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4082 .loc 1 2000 7 is_stmt 1 view .LVU1390 + 4083 .LVL276: +2000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4084 .loc 1 2000 16 is_stmt 0 view .LVU1391 + 4085 0058 4FF08076 mov r6, #16777216 + 4086 .LVL277: + 4087 .L278: +2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4088 .loc 1 2008 5 is_stmt 1 view .LVU1392 +2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4089 .loc 1 2008 13 is_stmt 0 view .LVU1393 + ARM GAS /tmp/ccSHpINd.s page 227 + + + 4090 005c 238D ldrh r3, [r4, #40] +2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4091 .loc 1 2008 8 view .LVU1394 + 4092 005e 63B1 cbz r3, .L279 +2012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4093 .loc 1 2012 7 is_stmt 1 view .LVU1395 +2012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4094 .loc 1 2012 30 is_stmt 0 view .LVU1396 + 4095 0060 1378 ldrb r3, [r2] @ zero_extendqisi2 +2012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4096 .loc 1 2012 28 view .LVU1397 + 4097 0062 8362 str r3, [r0, #40] +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4098 .loc 1 2015 7 is_stmt 1 view .LVU1398 +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4099 .loc 1 2015 11 is_stmt 0 view .LVU1399 + 4100 0064 636A ldr r3, [r4, #36] +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4101 .loc 1 2015 21 view .LVU1400 + 4102 0066 0133 adds r3, r3, #1 + 4103 0068 6362 str r3, [r4, #36] +2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 4104 .loc 1 2017 7 is_stmt 1 view .LVU1401 +2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 4105 .loc 1 2017 24 is_stmt 0 view .LVU1402 + 4106 006a 218D ldrh r1, [r4, #40] + 4107 .LVL278: +2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 4108 .loc 1 2018 7 is_stmt 1 view .LVU1403 +2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 4109 .loc 1 2018 11 is_stmt 0 view .LVU1404 + 4110 006c 638D ldrh r3, [r4, #42] + 4111 006e 9BB2 uxth r3, r3 +2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 4112 .loc 1 2018 22 view .LVU1405 + 4113 0070 013B subs r3, r3, #1 + 4114 0072 9BB2 uxth r3, r3 + 4115 0074 6385 strh r3, [r4, #42] @ movhi +2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4116 .loc 1 2019 7 is_stmt 1 view .LVU1406 +2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4117 .loc 1 2019 21 is_stmt 0 view .LVU1407 + 4118 0076 4B1E subs r3, r1, #1 + 4119 0078 2385 strh r3, [r4, #40] @ movhi + 4120 .LVL279: + 4121 .L279: +2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4122 .loc 1 2022 5 is_stmt 1 view .LVU1408 +2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4123 .loc 1 2022 13 is_stmt 0 view .LVU1409 + 4124 007a 238D ldrh r3, [r4, #40] +2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4125 .loc 1 2022 8 view .LVU1410 + 4126 007c 002B cmp r3, #0 + 4127 007e 51D0 beq .L280 +2024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4128 .loc 1 2024 7 is_stmt 1 view .LVU1411 + ARM GAS /tmp/ccSHpINd.s page 228 + + +2024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4129 .loc 1 2024 15 is_stmt 0 view .LVU1412 + 4130 0080 A36B ldr r3, [r4, #56] +2024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4131 .loc 1 2024 10 view .LVU1413 + 4132 0082 23B3 cbz r3, .L281 +2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4133 .loc 1 2027 9 is_stmt 1 view .LVU1414 +2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4134 .loc 1 2027 40 is_stmt 0 view .LVU1415 + 4135 0084 374A ldr r2, .L291+8 + 4136 .LVL280: +2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4137 .loc 1 2027 40 view .LVU1416 + 4138 0086 DA63 str r2, [r3, #60] +2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4139 .loc 1 2030 9 is_stmt 1 view .LVU1417 +2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4140 .loc 1 2030 13 is_stmt 0 view .LVU1418 + 4141 0088 A36B ldr r3, [r4, #56] +2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4142 .loc 1 2030 41 view .LVU1419 + 4143 008a 374A ldr r2, .L291+12 + 4144 008c DA64 str r2, [r3, #76] +2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 4145 .loc 1 2033 9 is_stmt 1 view .LVU1420 +2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 4146 .loc 1 2033 13 is_stmt 0 view .LVU1421 + 4147 008e A26B ldr r2, [r4, #56] +2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 4148 .loc 1 2033 44 view .LVU1422 + 4149 0090 0023 movs r3, #0 + 4150 0092 1364 str r3, [r2, #64] +2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4151 .loc 1 2034 9 is_stmt 1 view .LVU1423 +2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4152 .loc 1 2034 13 is_stmt 0 view .LVU1424 + 4153 0094 A26B ldr r2, [r4, #56] +2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4154 .loc 1 2034 41 view .LVU1425 + 4155 0096 1365 str r3, [r2, #80] +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + 4156 .loc 1 2037 9 is_stmt 1 view .LVU1426 +2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4157 .loc 1 2038 57 is_stmt 0 view .LVU1427 + 4158 0098 2268 ldr r2, [r4] +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + 4159 .loc 1 2037 25 view .LVU1428 + 4160 009a 238D ldrh r3, [r4, #40] + 4161 009c 2832 adds r2, r2, #40 + 4162 009e 616A ldr r1, [r4, #36] + 4163 .LVL281: +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + 4164 .loc 1 2037 25 view .LVU1429 + 4165 00a0 A06B ldr r0, [r4, #56] + 4166 00a2 FFF7FEFF bl HAL_DMA_Start_IT + 4167 .LVL282: + ARM GAS /tmp/ccSHpINd.s page 229 + + +2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4168 .loc 1 2055 7 is_stmt 1 view .LVU1430 +2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4169 .loc 1 2055 10 is_stmt 0 view .LVU1431 + 4170 00a6 00B3 cbz r0, .L290 +2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4171 .loc 1 2080 9 is_stmt 1 view .LVU1432 +2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4172 .loc 1 2080 25 is_stmt 0 view .LVU1433 + 4173 00a8 2023 movs r3, #32 + 4174 00aa 84F84130 strb r3, [r4, #65] +2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4175 .loc 1 2081 9 is_stmt 1 view .LVU1434 +2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4176 .loc 1 2081 25 is_stmt 0 view .LVU1435 + 4177 00ae 0022 movs r2, #0 + 4178 00b0 84F84220 strb r2, [r4, #66] +2084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4179 .loc 1 2084 9 is_stmt 1 view .LVU1436 +2084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4180 .loc 1 2084 13 is_stmt 0 view .LVU1437 + 4181 00b4 636C ldr r3, [r4, #68] +2084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4182 .loc 1 2084 25 view .LVU1438 + 4183 00b6 43F01003 orr r3, r3, #16 + 4184 00ba 6364 str r3, [r4, #68] +2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4185 .loc 1 2087 9 is_stmt 1 view .LVU1439 +2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4186 .loc 1 2087 9 view .LVU1440 + 4187 00bc 84F84020 strb r2, [r4, #64] +2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4188 .loc 1 2087 9 view .LVU1441 +2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4189 .loc 1 2089 9 view .LVU1442 +2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4190 .loc 1 2089 16 is_stmt 0 view .LVU1443 + 4191 00c0 0120 movs r0, #1 + 4192 .LVL283: +2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4193 .loc 1 2089 16 view .LVU1444 + 4194 00c2 44E0 b .L276 + 4195 .LVL284: + 4196 .L277: +2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 4197 .loc 1 2004 7 is_stmt 1 view .LVU1445 +2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 4198 .loc 1 2004 28 is_stmt 0 view .LVU1446 + 4199 00c4 638D ldrh r3, [r4, #42] +2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 4200 .loc 1 2004 22 view .LVU1447 + 4201 00c6 2385 strh r3, [r4, #40] @ movhi +2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4202 .loc 1 2005 7 is_stmt 1 view .LVU1448 + 4203 .LVL285: +2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4204 .loc 1 2005 16 is_stmt 0 view .LVU1449 + ARM GAS /tmp/ccSHpINd.s page 230 + + + 4205 00c8 4FF00076 mov r6, #33554432 + 4206 00cc C6E7 b .L278 + 4207 .LVL286: + 4208 .L281: +2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4209 .loc 1 2043 9 is_stmt 1 view .LVU1450 +2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4210 .loc 1 2043 25 is_stmt 0 view .LVU1451 + 4211 00ce 2023 movs r3, #32 + 4212 00d0 84F84130 strb r3, [r4, #65] +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4213 .loc 1 2044 9 is_stmt 1 view .LVU1452 +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4214 .loc 1 2044 25 is_stmt 0 view .LVU1453 + 4215 00d4 0022 movs r2, #0 + 4216 .LVL287: +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4217 .loc 1 2044 25 view .LVU1454 + 4218 00d6 84F84220 strb r2, [r4, #66] +2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4219 .loc 1 2047 9 is_stmt 1 view .LVU1455 +2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4220 .loc 1 2047 13 is_stmt 0 view .LVU1456 + 4221 00da 636C ldr r3, [r4, #68] +2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4222 .loc 1 2047 25 view .LVU1457 + 4223 00dc 43F08003 orr r3, r3, #128 + 4224 00e0 6364 str r3, [r4, #68] +2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4225 .loc 1 2050 9 is_stmt 1 view .LVU1458 +2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4226 .loc 1 2050 9 view .LVU1459 + 4227 00e2 84F84020 strb r2, [r4, #64] +2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4228 .loc 1 2050 9 view .LVU1460 +2052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4229 .loc 1 2052 9 view .LVU1461 +2052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4230 .loc 1 2052 16 is_stmt 0 view .LVU1462 + 4231 00e6 0120 movs r0, #1 + 4232 00e8 31E0 b .L276 + 4233 .LVL288: + 4234 .L290: +2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode, I2C_GENERATE_START_WRITE); + 4235 .loc 1 2059 9 is_stmt 1 view .LVU1463 +2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode, I2C_GENERATE_START_WRITE); + 4236 .loc 1 2059 60 is_stmt 0 view .LVU1464 + 4237 00ea 228D ldrh r2, [r4, #40] +2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode, I2C_GENERATE_START_WRITE); + 4238 .loc 1 2059 9 view .LVU1465 + 4239 00ec 0132 adds r2, r2, #1 + 4240 00ee 1F4B ldr r3, .L291+16 + 4241 00f0 0093 str r3, [sp] + 4242 00f2 3346 mov r3, r6 + 4243 00f4 D2B2 uxtb r2, r2 + 4244 00f6 2946 mov r1, r5 + 4245 00f8 2046 mov r0, r4 + ARM GAS /tmp/ccSHpINd.s page 231 + + + 4246 .LVL289: +2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode, I2C_GENERATE_START_WRITE); + 4247 .loc 1 2059 9 view .LVU1466 + 4248 00fa FFF7FEFF bl I2C_TransferConfig + 4249 .LVL290: +2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4250 .loc 1 2063 9 is_stmt 1 view .LVU1467 +2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4251 .loc 1 2063 13 is_stmt 0 view .LVU1468 + 4252 00fe 638D ldrh r3, [r4, #42] + 4253 0100 9BB2 uxth r3, r3 +2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4254 .loc 1 2063 32 view .LVU1469 + 4255 0102 228D ldrh r2, [r4, #40] +2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4256 .loc 1 2063 25 view .LVU1470 + 4257 0104 9B1A subs r3, r3, r2 + 4258 0106 9BB2 uxth r3, r3 + 4259 0108 6385 strh r3, [r4, #42] @ movhi +2066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4260 .loc 1 2066 9 is_stmt 1 view .LVU1471 +2066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4261 .loc 1 2066 9 view .LVU1472 + 4262 010a 0023 movs r3, #0 + 4263 010c 84F84030 strb r3, [r4, #64] +2066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4264 .loc 1 2066 9 view .LVU1473 +2072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4265 .loc 1 2072 9 view .LVU1474 + 4266 0110 1021 movs r1, #16 + 4267 0112 2046 mov r0, r4 + 4268 0114 FFF7FEFF bl I2C_Enable_IRQ + 4269 .LVL291: +2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4270 .loc 1 2075 9 view .LVU1475 +2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4271 .loc 1 2075 13 is_stmt 0 view .LVU1476 + 4272 0118 2268 ldr r2, [r4] +2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4273 .loc 1 2075 23 view .LVU1477 + 4274 011a 1368 ldr r3, [r2] +2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4275 .loc 1 2075 29 view .LVU1478 + 4276 011c 43F48043 orr r3, r3, #16384 + 4277 0120 1360 str r3, [r2] + 4278 0122 11E0 b .L284 + 4279 .LVL292: + 4280 .L280: +2095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4281 .loc 1 2095 7 is_stmt 1 view .LVU1479 +2095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4282 .loc 1 2095 21 is_stmt 0 view .LVU1480 + 4283 0124 124B ldr r3, .L291+20 + 4284 0126 6363 str r3, [r4, #52] +2099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 4285 .loc 1 2099 7 is_stmt 1 view .LVU1481 + 4286 0128 104B ldr r3, .L291+16 + ARM GAS /tmp/ccSHpINd.s page 232 + + + 4287 012a 0093 str r3, [sp] + 4288 012c 4FF00073 mov r3, #33554432 + 4289 0130 CAB2 uxtb r2, r1 + 4290 .LVL293: +2099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 4291 .loc 1 2099 7 is_stmt 0 view .LVU1482 + 4292 0132 2946 mov r1, r5 + 4293 .LVL294: +2099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 4294 .loc 1 2099 7 view .LVU1483 + 4295 0134 2046 mov r0, r4 + 4296 0136 FFF7FEFF bl I2C_TransferConfig + 4297 .LVL295: +2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4298 .loc 1 2103 7 is_stmt 1 view .LVU1484 +2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4299 .loc 1 2103 7 view .LVU1485 + 4300 013a 0023 movs r3, #0 + 4301 013c 84F84030 strb r3, [r4, #64] +2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4302 .loc 1 2103 7 view .LVU1486 +2112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4303 .loc 1 2112 7 view .LVU1487 + 4304 0140 0121 movs r1, #1 + 4305 0142 2046 mov r0, r4 + 4306 0144 FFF7FEFF bl I2C_Enable_IRQ + 4307 .LVL296: + 4308 .L284: +2115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4309 .loc 1 2115 5 view .LVU1488 +2115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4310 .loc 1 2115 12 is_stmt 0 view .LVU1489 + 4311 0148 0020 movs r0, #0 + 4312 014a 00E0 b .L276 + 4313 .LVL297: + 4314 .L285: +2119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4315 .loc 1 2119 12 view .LVU1490 + 4316 014c 0220 movs r0, #2 + 4317 .LVL298: + 4318 .L276: +2121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4319 .loc 1 2121 1 view .LVU1491 + 4320 014e 02B0 add sp, sp, #8 + 4321 .LCFI48: + 4322 .cfi_remember_state + 4323 .cfi_def_cfa_offset 16 + 4324 @ sp needed + 4325 0150 70BD pop {r4, r5, r6, pc} + 4326 .LVL299: + 4327 .L286: + 4328 .LCFI49: + 4329 .cfi_restore_state +1981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4330 .loc 1 1981 14 view .LVU1492 + 4331 0152 0220 movs r0, #2 + 4332 0154 FBE7 b .L276 + ARM GAS /tmp/ccSHpINd.s page 233 + + + 4333 .L287: +1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4334 .loc 1 1985 5 discriminator 1 view .LVU1493 + 4335 0156 0220 movs r0, #2 + 4336 0158 F9E7 b .L276 + 4337 .L292: + 4338 015a 00BF .align 2 + 4339 .L291: + 4340 015c 0000FFFF .word -65536 + 4341 0160 00000000 .word I2C_Master_ISR_DMA + 4342 0164 00000000 .word I2C_DMAMasterTransmitCplt + 4343 0168 00000000 .word I2C_DMAError + 4344 016c 00200080 .word -2147475456 + 4345 0170 00000000 .word I2C_Master_ISR_IT + 4346 .cfi_endproc + 4347 .LFE153: + 4349 .section .text.HAL_I2C_Master_Receive_DMA,"ax",%progbits + 4350 .align 1 + 4351 .global HAL_I2C_Master_Receive_DMA + 4352 .syntax unified + 4353 .thumb + 4354 .thumb_func + 4356 HAL_I2C_Master_Receive_DMA: + 4357 .LVL300: + 4358 .LFB154: +2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; + 4359 .loc 1 2135 1 is_stmt 1 view -0 + 4360 .cfi_startproc + 4361 @ args = 0, pretend = 0, frame = 0 + 4362 @ frame_needed = 0, uses_anonymous_args = 0 +2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; + 4363 .loc 1 2135 1 is_stmt 0 view .LVU1495 + 4364 0000 70B5 push {r4, r5, r6, lr} + 4365 .LCFI50: + 4366 .cfi_def_cfa_offset 16 + 4367 .cfi_offset 4, -16 + 4368 .cfi_offset 5, -12 + 4369 .cfi_offset 6, -8 + 4370 .cfi_offset 14, -4 + 4371 0002 82B0 sub sp, sp, #8 + 4372 .LCFI51: + 4373 .cfi_def_cfa_offset 24 + 4374 0004 0446 mov r4, r0 +2136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 4375 .loc 1 2136 3 is_stmt 1 view .LVU1496 +2137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4376 .loc 1 2137 3 view .LVU1497 +2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4377 .loc 1 2139 3 view .LVU1498 +2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4378 .loc 1 2139 11 is_stmt 0 view .LVU1499 + 4379 0006 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 4380 .LVL301: +2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4381 .loc 1 2139 11 view .LVU1500 + 4382 000a C0B2 uxtb r0, r0 +2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 234 + + + 4383 .loc 1 2139 6 view .LVU1501 + 4384 000c 2028 cmp r0, #32 + 4385 000e 40F08C80 bne .L302 + 4386 0012 0D46 mov r5, r1 +2141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4387 .loc 1 2141 5 is_stmt 1 view .LVU1502 +2141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4388 .loc 1 2141 9 is_stmt 0 view .LVU1503 + 4389 0014 2168 ldr r1, [r4] + 4390 .LVL302: +2141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4391 .loc 1 2141 9 view .LVU1504 + 4392 0016 8969 ldr r1, [r1, #24] +2141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4393 .loc 1 2141 8 view .LVU1505 + 4394 0018 11F4004F tst r1, #32768 + 4395 001c 40F08880 bne .L303 +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4396 .loc 1 2147 5 is_stmt 1 view .LVU1506 +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4397 .loc 1 2147 5 view .LVU1507 + 4398 0020 94F84010 ldrb r1, [r4, #64] @ zero_extendqisi2 + 4399 0024 0129 cmp r1, #1 + 4400 0026 00F08580 beq .L304 +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4401 .loc 1 2147 5 discriminator 2 view .LVU1508 + 4402 002a 0121 movs r1, #1 + 4403 002c 84F84010 strb r1, [r4, #64] +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4404 .loc 1 2147 5 discriminator 2 view .LVU1509 +2149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 4405 .loc 1 2149 5 view .LVU1510 +2149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 4406 .loc 1 2149 23 is_stmt 0 view .LVU1511 + 4407 0030 2221 movs r1, #34 + 4408 0032 84F84110 strb r1, [r4, #65] +2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4409 .loc 1 2150 5 is_stmt 1 view .LVU1512 +2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4410 .loc 1 2150 23 is_stmt 0 view .LVU1513 + 4411 0036 1021 movs r1, #16 + 4412 0038 84F84210 strb r1, [r4, #66] +2151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4413 .loc 1 2151 5 is_stmt 1 view .LVU1514 +2151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4414 .loc 1 2151 23 is_stmt 0 view .LVU1515 + 4415 003c 0021 movs r1, #0 + 4416 003e 6164 str r1, [r4, #68] +2154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 4417 .loc 1 2154 5 is_stmt 1 view .LVU1516 +2154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 4418 .loc 1 2154 23 is_stmt 0 view .LVU1517 + 4419 0040 6262 str r2, [r4, #36] +2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4420 .loc 1 2155 5 is_stmt 1 view .LVU1518 +2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4421 .loc 1 2155 23 is_stmt 0 view .LVU1519 + ARM GAS /tmp/ccSHpINd.s page 235 + + + 4422 0042 6385 strh r3, [r4, #42] @ movhi +2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 4423 .loc 1 2156 5 is_stmt 1 view .LVU1520 +2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 4424 .loc 1 2156 23 is_stmt 0 view .LVU1521 + 4425 0044 3C4B ldr r3, .L308 + 4426 .LVL303: +2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 4427 .loc 1 2156 23 view .LVU1522 + 4428 0046 E362 str r3, [r4, #44] + 4429 .LVL304: +2157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4430 .loc 1 2157 5 is_stmt 1 view .LVU1523 +2157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4431 .loc 1 2157 23 is_stmt 0 view .LVU1524 + 4432 0048 3C4B ldr r3, .L308+4 + 4433 004a 6363 str r3, [r4, #52] +2159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4434 .loc 1 2159 5 is_stmt 1 view .LVU1525 +2159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4435 .loc 1 2159 13 is_stmt 0 view .LVU1526 + 4436 004c 638D ldrh r3, [r4, #42] + 4437 004e 9BB2 uxth r3, r3 +2159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4438 .loc 1 2159 8 view .LVU1527 + 4439 0050 FF2B cmp r3, #255 + 4440 0052 27D9 bls .L295 +2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 4441 .loc 1 2161 7 is_stmt 1 view .LVU1528 +2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 4442 .loc 1 2161 22 is_stmt 0 view .LVU1529 + 4443 0054 0123 movs r3, #1 + 4444 0056 2385 strh r3, [r4, #40] @ movhi +2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4445 .loc 1 2162 7 is_stmt 1 view .LVU1530 + 4446 .LVL305: +2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4447 .loc 1 2162 16 is_stmt 0 view .LVU1531 + 4448 0058 4FF08076 mov r6, #16777216 + 4449 .LVL306: + 4450 .L296: +2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4451 .loc 1 2170 5 is_stmt 1 view .LVU1532 +2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4452 .loc 1 2170 13 is_stmt 0 view .LVU1533 + 4453 005c 218D ldrh r1, [r4, #40] +2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4454 .loc 1 2170 8 view .LVU1534 + 4455 005e 0029 cmp r1, #0 + 4456 0060 4FD0 beq .L297 +2172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4457 .loc 1 2172 7 is_stmt 1 view .LVU1535 +2172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4458 .loc 1 2172 15 is_stmt 0 view .LVU1536 + 4459 0062 E36B ldr r3, [r4, #60] +2172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4460 .loc 1 2172 10 view .LVU1537 + ARM GAS /tmp/ccSHpINd.s page 236 + + + 4461 0064 1BB3 cbz r3, .L298 +2175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4462 .loc 1 2175 9 is_stmt 1 view .LVU1538 +2175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4463 .loc 1 2175 40 is_stmt 0 view .LVU1539 + 4464 0066 3649 ldr r1, .L308+8 + 4465 0068 D963 str r1, [r3, #60] +2178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4466 .loc 1 2178 9 is_stmt 1 view .LVU1540 +2178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4467 .loc 1 2178 13 is_stmt 0 view .LVU1541 + 4468 006a E36B ldr r3, [r4, #60] +2178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4469 .loc 1 2178 41 view .LVU1542 + 4470 006c 3549 ldr r1, .L308+12 + 4471 006e D964 str r1, [r3, #76] +2181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 4472 .loc 1 2181 9 is_stmt 1 view .LVU1543 +2181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 4473 .loc 1 2181 13 is_stmt 0 view .LVU1544 + 4474 0070 E16B ldr r1, [r4, #60] +2181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 4475 .loc 1 2181 44 view .LVU1545 + 4476 0072 0023 movs r3, #0 + 4477 0074 0B64 str r3, [r1, #64] +2182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4478 .loc 1 2182 9 is_stmt 1 view .LVU1546 +2182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4479 .loc 1 2182 13 is_stmt 0 view .LVU1547 + 4480 0076 E16B ldr r1, [r4, #60] +2182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4481 .loc 1 2182 41 view .LVU1548 + 4482 0078 0B65 str r3, [r1, #80] +2185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 4483 .loc 1 2185 9 is_stmt 1 view .LVU1549 +2185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 4484 .loc 1 2185 71 is_stmt 0 view .LVU1550 + 4485 007a 2168 ldr r1, [r4] +2185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 4486 .loc 1 2185 25 view .LVU1551 + 4487 007c 238D ldrh r3, [r4, #40] + 4488 007e 2431 adds r1, r1, #36 + 4489 0080 E06B ldr r0, [r4, #60] + 4490 0082 FFF7FEFF bl HAL_DMA_Start_IT + 4491 .LVL307: +2203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4492 .loc 1 2203 7 is_stmt 1 view .LVU1552 +2203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4493 .loc 1 2203 10 is_stmt 0 view .LVU1553 + 4494 0086 00B3 cbz r0, .L307 +2227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4495 .loc 1 2227 9 is_stmt 1 view .LVU1554 +2227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4496 .loc 1 2227 25 is_stmt 0 view .LVU1555 + 4497 0088 2023 movs r3, #32 + 4498 008a 84F84130 strb r3, [r4, #65] +2228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 237 + + + 4499 .loc 1 2228 9 is_stmt 1 view .LVU1556 +2228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4500 .loc 1 2228 25 is_stmt 0 view .LVU1557 + 4501 008e 0022 movs r2, #0 + 4502 0090 84F84220 strb r2, [r4, #66] +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4503 .loc 1 2231 9 is_stmt 1 view .LVU1558 +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4504 .loc 1 2231 13 is_stmt 0 view .LVU1559 + 4505 0094 636C ldr r3, [r4, #68] +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4506 .loc 1 2231 25 view .LVU1560 + 4507 0096 43F01003 orr r3, r3, #16 + 4508 009a 6364 str r3, [r4, #68] +2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4509 .loc 1 2234 9 is_stmt 1 view .LVU1561 +2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4510 .loc 1 2234 9 view .LVU1562 + 4511 009c 84F84020 strb r2, [r4, #64] +2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4512 .loc 1 2234 9 view .LVU1563 +2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4513 .loc 1 2236 9 view .LVU1564 +2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4514 .loc 1 2236 16 is_stmt 0 view .LVU1565 + 4515 00a0 0120 movs r0, #1 + 4516 .LVL308: +2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4517 .loc 1 2236 16 view .LVU1566 + 4518 00a2 43E0 b .L294 + 4519 .LVL309: + 4520 .L295: +2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 4521 .loc 1 2166 7 is_stmt 1 view .LVU1567 +2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 4522 .loc 1 2166 28 is_stmt 0 view .LVU1568 + 4523 00a4 638D ldrh r3, [r4, #42] +2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 4524 .loc 1 2166 22 view .LVU1569 + 4525 00a6 2385 strh r3, [r4, #40] @ movhi +2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4526 .loc 1 2167 7 is_stmt 1 view .LVU1570 + 4527 .LVL310: +2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4528 .loc 1 2167 16 is_stmt 0 view .LVU1571 + 4529 00a8 4FF00076 mov r6, #33554432 + 4530 00ac D6E7 b .L296 + 4531 .LVL311: + 4532 .L298: +2191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4533 .loc 1 2191 9 is_stmt 1 view .LVU1572 +2191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4534 .loc 1 2191 25 is_stmt 0 view .LVU1573 + 4535 00ae 2023 movs r3, #32 + 4536 00b0 84F84130 strb r3, [r4, #65] +2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4537 .loc 1 2192 9 is_stmt 1 view .LVU1574 + ARM GAS /tmp/ccSHpINd.s page 238 + + +2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4538 .loc 1 2192 25 is_stmt 0 view .LVU1575 + 4539 00b4 0022 movs r2, #0 + 4540 .LVL312: +2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4541 .loc 1 2192 25 view .LVU1576 + 4542 00b6 84F84220 strb r2, [r4, #66] +2195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4543 .loc 1 2195 9 is_stmt 1 view .LVU1577 +2195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4544 .loc 1 2195 13 is_stmt 0 view .LVU1578 + 4545 00ba 636C ldr r3, [r4, #68] +2195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4546 .loc 1 2195 25 view .LVU1579 + 4547 00bc 43F08003 orr r3, r3, #128 + 4548 00c0 6364 str r3, [r4, #68] +2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4549 .loc 1 2198 9 is_stmt 1 view .LVU1580 +2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4550 .loc 1 2198 9 view .LVU1581 + 4551 00c2 84F84020 strb r2, [r4, #64] +2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4552 .loc 1 2198 9 view .LVU1582 +2200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4553 .loc 1 2200 9 view .LVU1583 +2200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4554 .loc 1 2200 16 is_stmt 0 view .LVU1584 + 4555 00c6 0120 movs r0, #1 + 4556 00c8 30E0 b .L294 + 4557 .LVL313: + 4558 .L307: +2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4559 .loc 1 2207 9 is_stmt 1 view .LVU1585 + 4560 00ca 1F4B ldr r3, .L308+16 + 4561 00cc 0093 str r3, [sp] + 4562 00ce 3346 mov r3, r6 + 4563 00d0 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 4564 00d4 2946 mov r1, r5 + 4565 00d6 2046 mov r0, r4 + 4566 .LVL314: +2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4567 .loc 1 2207 9 is_stmt 0 view .LVU1586 + 4568 00d8 FFF7FEFF bl I2C_TransferConfig + 4569 .LVL315: +2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4570 .loc 1 2210 9 is_stmt 1 view .LVU1587 +2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4571 .loc 1 2210 13 is_stmt 0 view .LVU1588 + 4572 00dc 638D ldrh r3, [r4, #42] + 4573 00de 9BB2 uxth r3, r3 +2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4574 .loc 1 2210 32 view .LVU1589 + 4575 00e0 228D ldrh r2, [r4, #40] +2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4576 .loc 1 2210 25 view .LVU1590 + 4577 00e2 9B1A subs r3, r3, r2 + 4578 00e4 9BB2 uxth r3, r3 + ARM GAS /tmp/ccSHpINd.s page 239 + + + 4579 00e6 6385 strh r3, [r4, #42] @ movhi +2213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4580 .loc 1 2213 9 is_stmt 1 view .LVU1591 +2213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4581 .loc 1 2213 9 view .LVU1592 + 4582 00e8 0023 movs r3, #0 + 4583 00ea 84F84030 strb r3, [r4, #64] +2213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4584 .loc 1 2213 9 view .LVU1593 +2219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4585 .loc 1 2219 9 view .LVU1594 + 4586 00ee 1021 movs r1, #16 + 4587 00f0 2046 mov r0, r4 + 4588 00f2 FFF7FEFF bl I2C_Enable_IRQ + 4589 .LVL316: +2222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4590 .loc 1 2222 9 view .LVU1595 +2222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4591 .loc 1 2222 13 is_stmt 0 view .LVU1596 + 4592 00f6 2268 ldr r2, [r4] +2222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4593 .loc 1 2222 23 view .LVU1597 + 4594 00f8 1368 ldr r3, [r2] +2222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4595 .loc 1 2222 29 view .LVU1598 + 4596 00fa 43F40043 orr r3, r3, #32768 + 4597 00fe 1360 str r3, [r2] + 4598 0100 11E0 b .L301 + 4599 .LVL317: + 4600 .L297: +2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4601 .loc 1 2242 7 is_stmt 1 view .LVU1599 +2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4602 .loc 1 2242 21 is_stmt 0 view .LVU1600 + 4603 0102 124B ldr r3, .L308+20 + 4604 0104 6363 str r3, [r4, #52] +2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 4605 .loc 1 2246 7 is_stmt 1 view .LVU1601 + 4606 0106 104B ldr r3, .L308+16 + 4607 0108 0093 str r3, [sp] + 4608 010a 4FF00073 mov r3, #33554432 + 4609 010e CAB2 uxtb r2, r1 + 4610 .LVL318: +2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 4611 .loc 1 2246 7 is_stmt 0 view .LVU1602 + 4612 0110 2946 mov r1, r5 + 4613 0112 2046 mov r0, r4 + 4614 0114 FFF7FEFF bl I2C_TransferConfig + 4615 .LVL319: +2250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4616 .loc 1 2250 7 is_stmt 1 view .LVU1603 +2250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4617 .loc 1 2250 7 view .LVU1604 + 4618 0118 0023 movs r3, #0 + 4619 011a 84F84030 strb r3, [r4, #64] +2250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4620 .loc 1 2250 7 view .LVU1605 + ARM GAS /tmp/ccSHpINd.s page 240 + + +2259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4621 .loc 1 2259 7 view .LVU1606 + 4622 011e 0221 movs r1, #2 + 4623 0120 2046 mov r0, r4 + 4624 0122 FFF7FEFF bl I2C_Enable_IRQ + 4625 .LVL320: + 4626 .L301: +2262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4627 .loc 1 2262 5 view .LVU1607 +2262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4628 .loc 1 2262 12 is_stmt 0 view .LVU1608 + 4629 0126 0020 movs r0, #0 + 4630 0128 00E0 b .L294 + 4631 .LVL321: + 4632 .L302: +2266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4633 .loc 1 2266 12 view .LVU1609 + 4634 012a 0220 movs r0, #2 + 4635 .LVL322: + 4636 .L294: +2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4637 .loc 1 2268 1 view .LVU1610 + 4638 012c 02B0 add sp, sp, #8 + 4639 .LCFI52: + 4640 .cfi_remember_state + 4641 .cfi_def_cfa_offset 16 + 4642 @ sp needed + 4643 012e 70BD pop {r4, r5, r6, pc} + 4644 .LVL323: + 4645 .L303: + 4646 .LCFI53: + 4647 .cfi_restore_state +2143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4648 .loc 1 2143 14 view .LVU1611 + 4649 0130 0220 movs r0, #2 + 4650 0132 FBE7 b .L294 + 4651 .L304: +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4652 .loc 1 2147 5 discriminator 1 view .LVU1612 + 4653 0134 0220 movs r0, #2 + 4654 0136 F9E7 b .L294 + 4655 .L309: + 4656 .align 2 + 4657 .L308: + 4658 0138 0000FFFF .word -65536 + 4659 013c 00000000 .word I2C_Master_ISR_DMA + 4660 0140 00000000 .word I2C_DMAMasterReceiveCplt + 4661 0144 00000000 .word I2C_DMAError + 4662 0148 00240080 .word -2147474432 + 4663 014c 00000000 .word I2C_Master_ISR_IT + 4664 .cfi_endproc + 4665 .LFE154: + 4667 .section .text.HAL_I2C_Slave_Transmit_DMA,"ax",%progbits + 4668 .align 1 + 4669 .global HAL_I2C_Slave_Transmit_DMA + 4670 .syntax unified + 4671 .thumb + ARM GAS /tmp/ccSHpINd.s page 241 + + + 4672 .thumb_func + 4674 HAL_I2C_Slave_Transmit_DMA: + 4675 .LVL324: + 4676 .LFB155: +2279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 4677 .loc 1 2279 1 is_stmt 1 view -0 + 4678 .cfi_startproc + 4679 @ args = 0, pretend = 0, frame = 0 + 4680 @ frame_needed = 0, uses_anonymous_args = 0 +2280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4681 .loc 1 2280 3 view .LVU1614 +2282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4682 .loc 1 2282 3 view .LVU1615 +2282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4683 .loc 1 2282 11 is_stmt 0 view .LVU1616 + 4684 0000 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 4685 0004 DBB2 uxtb r3, r3 +2282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4686 .loc 1 2282 6 view .LVU1617 + 4687 0006 202B cmp r3, #32 + 4688 0008 40F08D80 bne .L319 +2279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 4689 .loc 1 2279 1 view .LVU1618 + 4690 000c 10B5 push {r4, lr} + 4691 .LCFI54: + 4692 .cfi_def_cfa_offset 8 + 4693 .cfi_offset 4, -8 + 4694 .cfi_offset 14, -4 + 4695 000e 0446 mov r4, r0 +2284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4696 .loc 1 2284 5 is_stmt 1 view .LVU1619 +2284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4697 .loc 1 2284 8 is_stmt 0 view .LVU1620 + 4698 0010 002A cmp r2, #0 + 4699 0012 18BF it ne + 4700 0014 0029 cmpne r1, #0 + 4701 0016 42D0 beq .L326 +2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4702 .loc 1 2290 5 is_stmt 1 view .LVU1621 +2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4703 .loc 1 2290 5 view .LVU1622 + 4704 0018 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 4705 001c 012B cmp r3, #1 + 4706 001e 00F08480 beq .L320 +2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4707 .loc 1 2290 5 discriminator 2 view .LVU1623 + 4708 0022 0123 movs r3, #1 + 4709 0024 80F84030 strb r3, [r0, #64] +2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4710 .loc 1 2290 5 discriminator 2 view .LVU1624 +2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 4711 .loc 1 2292 5 view .LVU1625 +2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 4712 .loc 1 2292 23 is_stmt 0 view .LVU1626 + 4713 0028 2123 movs r3, #33 + 4714 002a 80F84130 strb r3, [r0, #65] +2293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + ARM GAS /tmp/ccSHpINd.s page 242 + + + 4715 .loc 1 2293 5 is_stmt 1 view .LVU1627 +2293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4716 .loc 1 2293 23 is_stmt 0 view .LVU1628 + 4717 002e 2023 movs r3, #32 + 4718 0030 80F84230 strb r3, [r0, #66] +2294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4719 .loc 1 2294 5 is_stmt 1 view .LVU1629 +2294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4720 .loc 1 2294 23 is_stmt 0 view .LVU1630 + 4721 0034 0023 movs r3, #0 + 4722 0036 4364 str r3, [r0, #68] +2297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 4723 .loc 1 2297 5 is_stmt 1 view .LVU1631 +2297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 4724 .loc 1 2297 23 is_stmt 0 view .LVU1632 + 4725 0038 4162 str r1, [r0, #36] +2298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 4726 .loc 1 2298 5 is_stmt 1 view .LVU1633 +2298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 4727 .loc 1 2298 23 is_stmt 0 view .LVU1634 + 4728 003a 4285 strh r2, [r0, #42] @ movhi +2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4729 .loc 1 2299 5 is_stmt 1 view .LVU1635 +2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4730 .loc 1 2299 29 is_stmt 0 view .LVU1636 + 4731 003c 438D ldrh r3, [r0, #42] +2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4732 .loc 1 2299 23 view .LVU1637 + 4733 003e 0385 strh r3, [r0, #40] @ movhi +2300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 4734 .loc 1 2300 5 is_stmt 1 view .LVU1638 +2300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 4735 .loc 1 2300 23 is_stmt 0 view .LVU1639 + 4736 0040 3B4B ldr r3, .L329 + 4737 0042 C362 str r3, [r0, #44] +2301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4738 .loc 1 2301 5 is_stmt 1 view .LVU1640 +2301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4739 .loc 1 2301 23 is_stmt 0 view .LVU1641 + 4740 0044 3B4B ldr r3, .L329+4 + 4741 0046 4363 str r3, [r0, #52] +2304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4742 .loc 1 2304 5 is_stmt 1 view .LVU1642 +2304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4743 .loc 1 2304 19 is_stmt 0 view .LVU1643 + 4744 0048 036A ldr r3, [r0, #32] +2304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4745 .loc 1 2304 8 view .LVU1644 + 4746 004a B3F5003F cmp r3, #131072 + 4747 004e 2BD0 beq .L327 + 4748 .LVL325: + 4749 .L313: +2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4750 .loc 1 2317 5 is_stmt 1 view .LVU1645 +2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4751 .loc 1 2317 13 is_stmt 0 view .LVU1646 + 4752 0050 638D ldrh r3, [r4, #42] + ARM GAS /tmp/ccSHpINd.s page 243 + + + 4753 0052 9BB2 uxth r3, r3 +2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4754 .loc 1 2317 8 view .LVU1647 + 4755 0054 002B cmp r3, #0 + 4756 0056 57D0 beq .L314 +2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4757 .loc 1 2319 7 is_stmt 1 view .LVU1648 +2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4758 .loc 1 2319 15 is_stmt 0 view .LVU1649 + 4759 0058 A36B ldr r3, [r4, #56] +2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4760 .loc 1 2319 10 view .LVU1650 + 4761 005a 002B cmp r3, #0 + 4762 005c 33D0 beq .L315 +2322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4763 .loc 1 2322 9 is_stmt 1 view .LVU1651 +2322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4764 .loc 1 2322 40 is_stmt 0 view .LVU1652 + 4765 005e 364A ldr r2, .L329+8 + 4766 0060 DA63 str r2, [r3, #60] +2325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4767 .loc 1 2325 9 is_stmt 1 view .LVU1653 +2325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4768 .loc 1 2325 13 is_stmt 0 view .LVU1654 + 4769 0062 A36B ldr r3, [r4, #56] +2325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4770 .loc 1 2325 41 view .LVU1655 + 4771 0064 354A ldr r2, .L329+12 + 4772 0066 DA64 str r2, [r3, #76] +2328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 4773 .loc 1 2328 9 is_stmt 1 view .LVU1656 +2328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 4774 .loc 1 2328 13 is_stmt 0 view .LVU1657 + 4775 0068 A26B ldr r2, [r4, #56] +2328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 4776 .loc 1 2328 44 view .LVU1658 + 4777 006a 0023 movs r3, #0 + 4778 006c 1364 str r3, [r2, #64] +2329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4779 .loc 1 2329 9 is_stmt 1 view .LVU1659 +2329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4780 .loc 1 2329 13 is_stmt 0 view .LVU1660 + 4781 006e A26B ldr r2, [r4, #56] +2329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4782 .loc 1 2329 41 view .LVU1661 + 4783 0070 1365 str r3, [r2, #80] +2332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + 4784 .loc 1 2332 9 is_stmt 1 view .LVU1662 +2333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 4785 .loc 1 2333 83 is_stmt 0 view .LVU1663 + 4786 0072 2268 ldr r2, [r4] +2332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + 4787 .loc 1 2332 25 view .LVU1664 + 4788 0074 238D ldrh r3, [r4, #40] + 4789 0076 2832 adds r2, r2, #40 + 4790 0078 616A ldr r1, [r4, #36] + 4791 .LVL326: + ARM GAS /tmp/ccSHpINd.s page 244 + + +2332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + 4792 .loc 1 2332 25 view .LVU1665 + 4793 007a A06B ldr r0, [r4, #56] + 4794 .LVL327: +2332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + 4795 .loc 1 2332 25 view .LVU1666 + 4796 007c FFF7FEFF bl HAL_DMA_Start_IT + 4797 .LVL328: +2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4798 .loc 1 2351 7 is_stmt 1 view .LVU1667 +2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 4799 .loc 1 2351 10 is_stmt 0 view .LVU1668 + 4800 0080 78B3 cbz r0, .L328 +2371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4801 .loc 1 2371 9 is_stmt 1 view .LVU1669 +2371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4802 .loc 1 2371 25 is_stmt 0 view .LVU1670 + 4803 0082 2823 movs r3, #40 + 4804 0084 84F84130 strb r3, [r4, #65] +2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4805 .loc 1 2372 9 is_stmt 1 view .LVU1671 +2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4806 .loc 1 2372 25 is_stmt 0 view .LVU1672 + 4807 0088 0022 movs r2, #0 + 4808 008a 84F84220 strb r2, [r4, #66] +2375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4809 .loc 1 2375 9 is_stmt 1 view .LVU1673 +2375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4810 .loc 1 2375 13 is_stmt 0 view .LVU1674 + 4811 008e 636C ldr r3, [r4, #68] +2375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4812 .loc 1 2375 25 view .LVU1675 + 4813 0090 43F01003 orr r3, r3, #16 + 4814 0094 6364 str r3, [r4, #68] +2378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4815 .loc 1 2378 9 is_stmt 1 view .LVU1676 +2378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4816 .loc 1 2378 9 view .LVU1677 + 4817 0096 84F84020 strb r2, [r4, #64] +2378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4818 .loc 1 2378 9 view .LVU1678 +2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4819 .loc 1 2380 9 view .LVU1679 +2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4820 .loc 1 2380 16 is_stmt 0 view .LVU1680 + 4821 009a 0120 movs r0, #1 + 4822 .LVL329: +2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4823 .loc 1 2380 16 view .LVU1681 + 4824 009c 03E0 b .L311 + 4825 .LVL330: + 4826 .L326: +2286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 4827 .loc 1 2286 7 is_stmt 1 view .LVU1682 +2286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 4828 .loc 1 2286 23 is_stmt 0 view .LVU1683 + 4829 009e 4FF40073 mov r3, #512 + ARM GAS /tmp/ccSHpINd.s page 245 + + + 4830 00a2 4364 str r3, [r0, #68] +2287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4831 .loc 1 2287 7 is_stmt 1 view .LVU1684 +2287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4832 .loc 1 2287 15 is_stmt 0 view .LVU1685 + 4833 00a4 0120 movs r0, #1 + 4834 .LVL331: + 4835 .L311: +2404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4836 .loc 1 2404 1 view .LVU1686 + 4837 00a6 10BD pop {r4, pc} + 4838 .LVL332: + 4839 .L327: +2308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4840 .loc 1 2308 7 is_stmt 1 view .LVU1687 +2308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4841 .loc 1 2308 11 is_stmt 0 view .LVU1688 + 4842 00a8 0368 ldr r3, [r0] +2308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4843 .loc 1 2308 30 view .LVU1689 + 4844 00aa 0A78 ldrb r2, [r1] @ zero_extendqisi2 + 4845 .LVL333: +2308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4846 .loc 1 2308 28 view .LVU1690 + 4847 00ac 9A62 str r2, [r3, #40] +2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4848 .loc 1 2311 7 is_stmt 1 view .LVU1691 +2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4849 .loc 1 2311 11 is_stmt 0 view .LVU1692 + 4850 00ae 436A ldr r3, [r0, #36] +2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4851 .loc 1 2311 21 view .LVU1693 + 4852 00b0 0133 adds r3, r3, #1 + 4853 00b2 4362 str r3, [r0, #36] +2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 4854 .loc 1 2313 7 is_stmt 1 view .LVU1694 +2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 4855 .loc 1 2313 11 is_stmt 0 view .LVU1695 + 4856 00b4 438D ldrh r3, [r0, #42] + 4857 00b6 9BB2 uxth r3, r3 +2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 4858 .loc 1 2313 22 view .LVU1696 + 4859 00b8 013B subs r3, r3, #1 + 4860 00ba 9BB2 uxth r3, r3 + 4861 00bc 4385 strh r3, [r0, #42] @ movhi +2314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4862 .loc 1 2314 7 is_stmt 1 view .LVU1697 +2314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4863 .loc 1 2314 11 is_stmt 0 view .LVU1698 + 4864 00be 038D ldrh r3, [r0, #40] +2314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4865 .loc 1 2314 21 view .LVU1699 + 4866 00c0 013B subs r3, r3, #1 + 4867 00c2 0385 strh r3, [r0, #40] @ movhi + 4868 00c4 C4E7 b .L313 + 4869 .L315: +2339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + ARM GAS /tmp/ccSHpINd.s page 246 + + + 4870 .loc 1 2339 9 is_stmt 1 view .LVU1700 +2339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4871 .loc 1 2339 25 is_stmt 0 view .LVU1701 + 4872 00c6 2823 movs r3, #40 + 4873 00c8 84F84130 strb r3, [r4, #65] +2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4874 .loc 1 2340 9 is_stmt 1 view .LVU1702 +2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4875 .loc 1 2340 25 is_stmt 0 view .LVU1703 + 4876 00cc 0022 movs r2, #0 + 4877 00ce 84F84220 strb r2, [r4, #66] +2343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4878 .loc 1 2343 9 is_stmt 1 view .LVU1704 +2343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4879 .loc 1 2343 13 is_stmt 0 view .LVU1705 + 4880 00d2 636C ldr r3, [r4, #68] +2343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4881 .loc 1 2343 25 view .LVU1706 + 4882 00d4 43F08003 orr r3, r3, #128 + 4883 00d8 6364 str r3, [r4, #68] +2346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4884 .loc 1 2346 9 is_stmt 1 view .LVU1707 +2346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4885 .loc 1 2346 9 view .LVU1708 + 4886 00da 84F84020 strb r2, [r4, #64] +2346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4887 .loc 1 2346 9 view .LVU1709 +2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4888 .loc 1 2348 9 view .LVU1710 +2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4889 .loc 1 2348 16 is_stmt 0 view .LVU1711 + 4890 00de 0120 movs r0, #1 + 4891 .LVL334: +2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4892 .loc 1 2348 16 view .LVU1712 + 4893 00e0 E1E7 b .L311 + 4894 .LVL335: + 4895 .L328: +2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4896 .loc 1 2354 9 is_stmt 1 view .LVU1713 +2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4897 .loc 1 2354 13 is_stmt 0 view .LVU1714 + 4898 00e2 2268 ldr r2, [r4] +2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4899 .loc 1 2354 23 view .LVU1715 + 4900 00e4 5368 ldr r3, [r2, #4] +2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4901 .loc 1 2354 29 view .LVU1716 + 4902 00e6 23F40043 bic r3, r3, #32768 + 4903 00ea 5360 str r3, [r2, #4] +2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4904 .loc 1 2357 9 is_stmt 1 view .LVU1717 +2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4905 .loc 1 2357 9 view .LVU1718 + 4906 00ec 0023 movs r3, #0 + 4907 00ee 84F84030 strb r3, [r4, #64] +2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 247 + + + 4908 .loc 1 2357 9 view .LVU1719 +2363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4909 .loc 1 2363 9 view .LVU1720 + 4910 00f2 4FF40041 mov r1, #32768 + 4911 00f6 2046 mov r0, r4 + 4912 .LVL336: +2363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4913 .loc 1 2363 9 is_stmt 0 view .LVU1721 + 4914 00f8 FFF7FEFF bl I2C_Enable_IRQ + 4915 .LVL337: +2366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4916 .loc 1 2366 9 is_stmt 1 view .LVU1722 +2366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4917 .loc 1 2366 13 is_stmt 0 view .LVU1723 + 4918 00fc 2268 ldr r2, [r4] +2366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4919 .loc 1 2366 23 view .LVU1724 + 4920 00fe 1368 ldr r3, [r2] +2366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4921 .loc 1 2366 29 view .LVU1725 + 4922 0100 43F48043 orr r3, r3, #16384 + 4923 0104 1360 str r3, [r2] + 4924 0106 0CE0 b .L318 + 4925 .LVL338: + 4926 .L314: +2386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4927 .loc 1 2386 7 is_stmt 1 view .LVU1726 +2386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4928 .loc 1 2386 11 is_stmt 0 view .LVU1727 + 4929 0108 2268 ldr r2, [r4] +2386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4930 .loc 1 2386 21 view .LVU1728 + 4931 010a 5368 ldr r3, [r2, #4] +2386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4932 .loc 1 2386 27 view .LVU1729 + 4933 010c 23F40043 bic r3, r3, #32768 + 4934 0110 5360 str r3, [r2, #4] +2389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4935 .loc 1 2389 7 is_stmt 1 view .LVU1730 +2389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4936 .loc 1 2389 7 view .LVU1731 + 4937 0112 0023 movs r3, #0 + 4938 0114 84F84030 strb r3, [r4, #64] +2389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4939 .loc 1 2389 7 view .LVU1732 +2395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4940 .loc 1 2395 7 view .LVU1733 + 4941 0118 4FF40041 mov r1, #32768 + 4942 .LVL339: +2395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4943 .loc 1 2395 7 is_stmt 0 view .LVU1734 + 4944 011c 2046 mov r0, r4 + 4945 .LVL340: +2395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4946 .loc 1 2395 7 view .LVU1735 + 4947 011e FFF7FEFF bl I2C_Enable_IRQ + 4948 .LVL341: + ARM GAS /tmp/ccSHpINd.s page 248 + + + 4949 .L318: +2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4950 .loc 1 2398 5 is_stmt 1 view .LVU1736 +2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4951 .loc 1 2398 12 is_stmt 0 view .LVU1737 + 4952 0122 0020 movs r0, #0 + 4953 0124 BFE7 b .L311 + 4954 .LVL342: + 4955 .L319: + 4956 .LCFI55: + 4957 .cfi_def_cfa_offset 0 + 4958 .cfi_restore 4 + 4959 .cfi_restore 14 +2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 4960 .loc 1 2402 12 view .LVU1738 + 4961 0126 0220 movs r0, #2 + 4962 .LVL343: +2404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4963 .loc 1 2404 1 view .LVU1739 + 4964 0128 7047 bx lr + 4965 .LVL344: + 4966 .L320: + 4967 .LCFI56: + 4968 .cfi_def_cfa_offset 8 + 4969 .cfi_offset 4, -8 + 4970 .cfi_offset 14, -4 +2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4971 .loc 1 2290 5 discriminator 1 view .LVU1740 + 4972 012a 0220 movs r0, #2 + 4973 .LVL345: +2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 4974 .loc 1 2290 5 discriminator 1 view .LVU1741 + 4975 012c BBE7 b .L311 + 4976 .L330: + 4977 012e 00BF .align 2 + 4978 .L329: + 4979 0130 0000FFFF .word -65536 + 4980 0134 00000000 .word I2C_Slave_ISR_DMA + 4981 0138 00000000 .word I2C_DMASlaveTransmitCplt + 4982 013c 00000000 .word I2C_DMAError + 4983 .cfi_endproc + 4984 .LFE155: + 4986 .section .text.HAL_I2C_Slave_Receive_DMA,"ax",%progbits + 4987 .align 1 + 4988 .global HAL_I2C_Slave_Receive_DMA + 4989 .syntax unified + 4990 .thumb + 4991 .thumb_func + 4993 HAL_I2C_Slave_Receive_DMA: + 4994 .LVL346: + 4995 .LFB156: +2415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 4996 .loc 1 2415 1 is_stmt 1 view -0 + 4997 .cfi_startproc + 4998 @ args = 0, pretend = 0, frame = 0 + 4999 @ frame_needed = 0, uses_anonymous_args = 0 +2415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + ARM GAS /tmp/ccSHpINd.s page 249 + + + 5000 .loc 1 2415 1 is_stmt 0 view .LVU1743 + 5001 0000 38B5 push {r3, r4, r5, lr} + 5002 .LCFI57: + 5003 .cfi_def_cfa_offset 16 + 5004 .cfi_offset 3, -16 + 5005 .cfi_offset 4, -12 + 5006 .cfi_offset 5, -8 + 5007 .cfi_offset 14, -4 +2416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5008 .loc 1 2416 3 is_stmt 1 view .LVU1744 +2418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5009 .loc 1 2418 3 view .LVU1745 +2418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5010 .loc 1 2418 11 is_stmt 0 view .LVU1746 + 5011 0002 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 5012 0006 DBB2 uxtb r3, r3 +2418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5013 .loc 1 2418 6 view .LVU1747 + 5014 0008 202B cmp r3, #32 + 5015 000a 65D1 bne .L337 + 5016 000c 0446 mov r4, r0 +2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5017 .loc 1 2420 5 is_stmt 1 view .LVU1748 +2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5018 .loc 1 2420 8 is_stmt 0 view .LVU1749 + 5019 000e 002A cmp r2, #0 + 5020 0010 18BF it ne + 5021 0012 0029 cmpne r1, #0 + 5022 0014 3AD0 beq .L341 +2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5023 .loc 1 2426 5 is_stmt 1 view .LVU1750 +2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5024 .loc 1 2426 5 view .LVU1751 + 5025 0016 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 5026 001a 012B cmp r3, #1 + 5027 001c 5FD0 beq .L338 +2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5028 .loc 1 2426 5 discriminator 2 view .LVU1752 + 5029 001e 0123 movs r3, #1 + 5030 0020 80F84030 strb r3, [r0, #64] +2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5031 .loc 1 2426 5 discriminator 2 view .LVU1753 +2428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 5032 .loc 1 2428 5 view .LVU1754 +2428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 5033 .loc 1 2428 23 is_stmt 0 view .LVU1755 + 5034 0024 2223 movs r3, #34 + 5035 0026 80F84130 strb r3, [r0, #65] +2429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5036 .loc 1 2429 5 is_stmt 1 view .LVU1756 +2429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5037 .loc 1 2429 23 is_stmt 0 view .LVU1757 + 5038 002a 2023 movs r3, #32 + 5039 002c 80F84230 strb r3, [r0, #66] +2430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5040 .loc 1 2430 5 is_stmt 1 view .LVU1758 +2430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 250 + + + 5041 .loc 1 2430 23 is_stmt 0 view .LVU1759 + 5042 0030 0023 movs r3, #0 + 5043 0032 4364 str r3, [r0, #68] +2433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 5044 .loc 1 2433 5 is_stmt 1 view .LVU1760 +2433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 5045 .loc 1 2433 23 is_stmt 0 view .LVU1761 + 5046 0034 4162 str r1, [r0, #36] +2434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 5047 .loc 1 2434 5 is_stmt 1 view .LVU1762 +2434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 5048 .loc 1 2434 23 is_stmt 0 view .LVU1763 + 5049 0036 4285 strh r2, [r0, #42] @ movhi +2435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5050 .loc 1 2435 5 is_stmt 1 view .LVU1764 +2435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5051 .loc 1 2435 29 is_stmt 0 view .LVU1765 + 5052 0038 438D ldrh r3, [r0, #42] +2435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5053 .loc 1 2435 23 view .LVU1766 + 5054 003a 0385 strh r3, [r0, #40] @ movhi +2436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 5055 .loc 1 2436 5 is_stmt 1 view .LVU1767 +2436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 5056 .loc 1 2436 23 is_stmt 0 view .LVU1768 + 5057 003c 294B ldr r3, .L343 + 5058 003e C362 str r3, [r0, #44] +2437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5059 .loc 1 2437 5 is_stmt 1 view .LVU1769 +2437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5060 .loc 1 2437 23 is_stmt 0 view .LVU1770 + 5061 0040 294B ldr r3, .L343+4 + 5062 0042 4363 str r3, [r0, #52] +2439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5063 .loc 1 2439 5 is_stmt 1 view .LVU1771 +2439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5064 .loc 1 2439 13 is_stmt 0 view .LVU1772 + 5065 0044 C36B ldr r3, [r0, #60] +2439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5066 .loc 1 2439 8 view .LVU1773 + 5067 0046 33B3 cbz r3, .L334 +2442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5068 .loc 1 2442 7 is_stmt 1 view .LVU1774 +2442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5069 .loc 1 2442 38 is_stmt 0 view .LVU1775 + 5070 0048 284A ldr r2, .L343+8 + 5071 .LVL347: +2442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5072 .loc 1 2442 38 view .LVU1776 + 5073 004a DA63 str r2, [r3, #60] +2445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5074 .loc 1 2445 7 is_stmt 1 view .LVU1777 +2445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5075 .loc 1 2445 11 is_stmt 0 view .LVU1778 + 5076 004c C36B ldr r3, [r0, #60] +2445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5077 .loc 1 2445 39 view .LVU1779 + ARM GAS /tmp/ccSHpINd.s page 251 + + + 5078 004e 284A ldr r2, .L343+12 + 5079 0050 DA64 str r2, [r3, #76] +2448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 5080 .loc 1 2448 7 is_stmt 1 view .LVU1780 +2448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 5081 .loc 1 2448 11 is_stmt 0 view .LVU1781 + 5082 0052 C26B ldr r2, [r0, #60] +2448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 5083 .loc 1 2448 42 view .LVU1782 + 5084 0054 0023 movs r3, #0 + 5085 0056 1364 str r3, [r2, #64] +2449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5086 .loc 1 2449 7 is_stmt 1 view .LVU1783 +2449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5087 .loc 1 2449 11 is_stmt 0 view .LVU1784 + 5088 0058 C26B ldr r2, [r0, #60] +2449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5089 .loc 1 2449 39 view .LVU1785 + 5090 005a 1365 str r3, [r2, #80] +2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 5091 .loc 1 2452 7 is_stmt 1 view .LVU1786 +2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 5092 .loc 1 2452 69 is_stmt 0 view .LVU1787 + 5093 005c 0068 ldr r0, [r0] + 5094 .LVL348: +2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 5095 .loc 1 2452 23 view .LVU1788 + 5096 005e 238D ldrh r3, [r4, #40] + 5097 0060 0A46 mov r2, r1 + 5098 0062 00F12401 add r1, r0, #36 + 5099 .LVL349: +2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 5100 .loc 1 2452 23 view .LVU1789 + 5101 0066 E06B ldr r0, [r4, #60] + 5102 0068 FFF7FEFF bl HAL_DMA_Start_IT + 5103 .LVL350: +2470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5104 .loc 1 2470 5 is_stmt 1 view .LVU1790 +2470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5105 .loc 1 2470 8 is_stmt 0 view .LVU1791 + 5106 006c 0546 mov r5, r0 + 5107 006e 00B3 cbz r0, .L342 +2490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5108 .loc 1 2490 7 is_stmt 1 view .LVU1792 +2490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5109 .loc 1 2490 23 is_stmt 0 view .LVU1793 + 5110 0070 2823 movs r3, #40 + 5111 0072 84F84130 strb r3, [r4, #65] +2491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5112 .loc 1 2491 7 is_stmt 1 view .LVU1794 +2491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5113 .loc 1 2491 23 is_stmt 0 view .LVU1795 + 5114 0076 0022 movs r2, #0 + 5115 0078 84F84220 strb r2, [r4, #66] +2494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5116 .loc 1 2494 7 is_stmt 1 view .LVU1796 +2494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 252 + + + 5117 .loc 1 2494 11 is_stmt 0 view .LVU1797 + 5118 007c 636C ldr r3, [r4, #68] +2494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5119 .loc 1 2494 23 view .LVU1798 + 5120 007e 43F01003 orr r3, r3, #16 + 5121 0082 6364 str r3, [r4, #68] +2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5122 .loc 1 2497 7 is_stmt 1 view .LVU1799 +2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5123 .loc 1 2497 7 view .LVU1800 + 5124 0084 84F84020 strb r2, [r4, #64] +2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5125 .loc 1 2497 7 view .LVU1801 +2499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5126 .loc 1 2499 7 view .LVU1802 +2499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5127 .loc 1 2499 14 is_stmt 0 view .LVU1803 + 5128 0088 0125 movs r5, #1 + 5129 008a 26E0 b .L332 + 5130 .LVL351: + 5131 .L341: +2422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 5132 .loc 1 2422 7 is_stmt 1 view .LVU1804 +2422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 5133 .loc 1 2422 23 is_stmt 0 view .LVU1805 + 5134 008c 4FF40073 mov r3, #512 + 5135 0090 4364 str r3, [r0, #68] +2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5136 .loc 1 2423 7 is_stmt 1 view .LVU1806 +2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5137 .loc 1 2423 15 is_stmt 0 view .LVU1807 + 5138 0092 0125 movs r5, #1 + 5139 0094 21E0 b .L332 + 5140 .L334: +2458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5141 .loc 1 2458 7 is_stmt 1 view .LVU1808 +2458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5142 .loc 1 2458 23 is_stmt 0 view .LVU1809 + 5143 0096 2823 movs r3, #40 + 5144 0098 80F84130 strb r3, [r0, #65] +2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5145 .loc 1 2459 7 is_stmt 1 view .LVU1810 +2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5146 .loc 1 2459 23 is_stmt 0 view .LVU1811 + 5147 009c 0022 movs r2, #0 + 5148 .LVL352: +2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5149 .loc 1 2459 23 view .LVU1812 + 5150 009e 80F84220 strb r2, [r0, #66] +2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5151 .loc 1 2462 7 is_stmt 1 view .LVU1813 +2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5152 .loc 1 2462 11 is_stmt 0 view .LVU1814 + 5153 00a2 436C ldr r3, [r0, #68] +2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5154 .loc 1 2462 23 view .LVU1815 + 5155 00a4 43F08003 orr r3, r3, #128 + ARM GAS /tmp/ccSHpINd.s page 253 + + + 5156 00a8 4364 str r3, [r0, #68] +2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5157 .loc 1 2465 7 is_stmt 1 view .LVU1816 +2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5158 .loc 1 2465 7 view .LVU1817 + 5159 00aa 80F84020 strb r2, [r0, #64] +2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5160 .loc 1 2465 7 view .LVU1818 +2467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5161 .loc 1 2467 7 view .LVU1819 +2467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5162 .loc 1 2467 14 is_stmt 0 view .LVU1820 + 5163 00ae 0125 movs r5, #1 + 5164 00b0 13E0 b .L332 + 5165 .LVL353: + 5166 .L342: +2473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5167 .loc 1 2473 7 is_stmt 1 view .LVU1821 +2473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5168 .loc 1 2473 11 is_stmt 0 view .LVU1822 + 5169 00b2 2268 ldr r2, [r4] +2473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5170 .loc 1 2473 21 view .LVU1823 + 5171 00b4 5368 ldr r3, [r2, #4] +2473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5172 .loc 1 2473 27 view .LVU1824 + 5173 00b6 23F40043 bic r3, r3, #32768 + 5174 00ba 5360 str r3, [r2, #4] +2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5175 .loc 1 2476 7 is_stmt 1 view .LVU1825 +2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5176 .loc 1 2476 7 view .LVU1826 + 5177 00bc 0023 movs r3, #0 + 5178 00be 84F84030 strb r3, [r4, #64] +2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5179 .loc 1 2476 7 view .LVU1827 +2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5180 .loc 1 2482 7 view .LVU1828 + 5181 00c2 4FF40041 mov r1, #32768 + 5182 00c6 2046 mov r0, r4 + 5183 .LVL354: +2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5184 .loc 1 2482 7 is_stmt 0 view .LVU1829 + 5185 00c8 FFF7FEFF bl I2C_Enable_IRQ + 5186 .LVL355: +2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5187 .loc 1 2485 7 is_stmt 1 view .LVU1830 +2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5188 .loc 1 2485 11 is_stmt 0 view .LVU1831 + 5189 00cc 2268 ldr r2, [r4] +2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5190 .loc 1 2485 21 view .LVU1832 + 5191 00ce 1368 ldr r3, [r2] +2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5192 .loc 1 2485 27 view .LVU1833 + 5193 00d0 43F40043 orr r3, r3, #32768 + 5194 00d4 1360 str r3, [r2] + ARM GAS /tmp/ccSHpINd.s page 254 + + +2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5195 .loc 1 2502 5 is_stmt 1 view .LVU1834 +2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5196 .loc 1 2502 12 is_stmt 0 view .LVU1835 + 5197 00d6 00E0 b .L332 + 5198 .LVL356: + 5199 .L337: +2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5200 .loc 1 2506 12 view .LVU1836 + 5201 00d8 0225 movs r5, #2 + 5202 .LVL357: + 5203 .L332: +2508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5204 .loc 1 2508 1 view .LVU1837 + 5205 00da 2846 mov r0, r5 + 5206 00dc 38BD pop {r3, r4, r5, pc} + 5207 .LVL358: + 5208 .L338: +2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5209 .loc 1 2426 5 discriminator 1 view .LVU1838 + 5210 00de 0225 movs r5, #2 + 5211 00e0 FBE7 b .L332 + 5212 .L344: + 5213 00e2 00BF .align 2 + 5214 .L343: + 5215 00e4 0000FFFF .word -65536 + 5216 00e8 00000000 .word I2C_Slave_ISR_DMA + 5217 00ec 00000000 .word I2C_DMASlaveReceiveCplt + 5218 00f0 00000000 .word I2C_DMAError + 5219 .cfi_endproc + 5220 .LFE156: + 5222 .section .text.HAL_I2C_Mem_Write,"ax",%progbits + 5223 .align 1 + 5224 .global HAL_I2C_Mem_Write + 5225 .syntax unified + 5226 .thumb + 5227 .thumb_func + 5229 HAL_I2C_Mem_Write: + 5230 .LVL359: + 5231 .LFB157: +2525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; + 5232 .loc 1 2525 1 is_stmt 1 view -0 + 5233 .cfi_startproc + 5234 @ args = 12, pretend = 0, frame = 0 + 5235 @ frame_needed = 0, uses_anonymous_args = 0 +2525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; + 5236 .loc 1 2525 1 is_stmt 0 view .LVU1840 + 5237 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 5238 .LCFI58: + 5239 .cfi_def_cfa_offset 36 + 5240 .cfi_offset 4, -36 + 5241 .cfi_offset 5, -32 + 5242 .cfi_offset 6, -28 + 5243 .cfi_offset 7, -24 + 5244 .cfi_offset 8, -20 + 5245 .cfi_offset 9, -16 + 5246 .cfi_offset 10, -12 + ARM GAS /tmp/ccSHpINd.s page 255 + + + 5247 .cfi_offset 11, -8 + 5248 .cfi_offset 14, -4 + 5249 0004 83B0 sub sp, sp, #12 + 5250 .LCFI59: + 5251 .cfi_def_cfa_offset 48 + 5252 0006 0D46 mov r5, r1 + 5253 0008 BDF834A0 ldrh r10, [sp, #52] + 5254 000c 0E9F ldr r7, [sp, #56] +2526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5255 .loc 1 2526 3 is_stmt 1 view .LVU1841 +2529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5256 .loc 1 2529 3 view .LVU1842 +2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5257 .loc 1 2531 3 view .LVU1843 +2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5258 .loc 1 2531 11 is_stmt 0 view .LVU1844 + 5259 000e 90F84110 ldrb r1, [r0, #65] @ zero_extendqisi2 + 5260 .LVL360: +2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5261 .loc 1 2531 11 view .LVU1845 + 5262 0012 C9B2 uxtb r1, r1 +2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5263 .loc 1 2531 6 view .LVU1846 + 5264 0014 2029 cmp r1, #32 + 5265 0016 40F0BC80 bne .L354 + 5266 001a 0446 mov r4, r0 + 5267 001c 9046 mov r8, r2 + 5268 001e 9946 mov r9, r3 +2533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5269 .loc 1 2533 5 is_stmt 1 view .LVU1847 +2533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5270 .loc 1 2533 8 is_stmt 0 view .LVU1848 + 5271 0020 0C9B ldr r3, [sp, #48] + 5272 .LVL361: +2533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5273 .loc 1 2533 8 view .LVU1849 + 5274 0022 BAF1000F cmp r10, #0 + 5275 0026 18BF it ne + 5276 0028 002B cmpne r3, #0 + 5277 002a 16D0 beq .L361 +2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5278 .loc 1 2540 5 is_stmt 1 view .LVU1850 +2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5279 .loc 1 2540 5 view .LVU1851 + 5280 002c 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 5281 0030 012B cmp r3, #1 + 5282 0032 00F0B280 beq .L355 +2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5283 .loc 1 2540 5 discriminator 2 view .LVU1852 + 5284 0036 4FF0010B mov fp, #1 + 5285 003a 80F840B0 strb fp, [r0, #64] +2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5286 .loc 1 2540 5 discriminator 2 view .LVU1853 +2543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5287 .loc 1 2543 5 view .LVU1854 +2543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5288 .loc 1 2543 17 is_stmt 0 view .LVU1855 + ARM GAS /tmp/ccSHpINd.s page 256 + + + 5289 003e FFF7FEFF bl HAL_GetTick + 5290 .LVL362: +2543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5291 .loc 1 2543 17 view .LVU1856 + 5292 0042 0646 mov r6, r0 + 5293 .LVL363: +2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5294 .loc 1 2545 5 is_stmt 1 view .LVU1857 +2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5295 .loc 1 2545 9 is_stmt 0 view .LVU1858 + 5296 0044 0090 str r0, [sp] + 5297 0046 1923 movs r3, #25 + 5298 0048 5A46 mov r2, fp + 5299 004a 4FF40041 mov r1, #32768 + 5300 004e 2046 mov r0, r4 + 5301 .LVL364: +2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5302 .loc 1 2545 9 view .LVU1859 + 5303 0050 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 5304 .LVL365: +2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5305 .loc 1 2545 8 discriminator 1 view .LVU1860 + 5306 0054 30B1 cbz r0, .L362 +2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5307 .loc 1 2547 14 view .LVU1861 + 5308 0056 0120 movs r0, #1 + 5309 0058 9CE0 b .L346 + 5310 .LVL366: + 5311 .L361: +2535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 5312 .loc 1 2535 7 is_stmt 1 view .LVU1862 +2535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 5313 .loc 1 2535 23 is_stmt 0 view .LVU1863 + 5314 005a 4FF40073 mov r3, #512 + 5315 005e 4364 str r3, [r0, #68] +2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5316 .loc 1 2536 7 is_stmt 1 view .LVU1864 +2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5317 .loc 1 2536 15 is_stmt 0 view .LVU1865 + 5318 0060 0120 movs r0, #1 + 5319 .LVL367: +2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5320 .loc 1 2536 15 view .LVU1866 + 5321 0062 97E0 b .L346 + 5322 .LVL368: + 5323 .L362: +2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5324 .loc 1 2550 5 is_stmt 1 view .LVU1867 +2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5325 .loc 1 2550 21 is_stmt 0 view .LVU1868 + 5326 0064 2123 movs r3, #33 + 5327 0066 84F84130 strb r3, [r4, #65] +2551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5328 .loc 1 2551 5 is_stmt 1 view .LVU1869 +2551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5329 .loc 1 2551 21 is_stmt 0 view .LVU1870 + 5330 006a 4023 movs r3, #64 + ARM GAS /tmp/ccSHpINd.s page 257 + + + 5331 006c 84F84230 strb r3, [r4, #66] +2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5332 .loc 1 2552 5 is_stmt 1 view .LVU1871 +2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5333 .loc 1 2552 21 is_stmt 0 view .LVU1872 + 5334 0070 0023 movs r3, #0 + 5335 0072 6364 str r3, [r4, #68] +2555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 5336 .loc 1 2555 5 is_stmt 1 view .LVU1873 +2555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 5337 .loc 1 2555 21 is_stmt 0 view .LVU1874 + 5338 0074 0C9A ldr r2, [sp, #48] + 5339 0076 6262 str r2, [r4, #36] +2556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 5340 .loc 1 2556 5 is_stmt 1 view .LVU1875 +2556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 5341 .loc 1 2556 21 is_stmt 0 view .LVU1876 + 5342 0078 A4F82AA0 strh r10, [r4, #42] @ movhi +2557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5343 .loc 1 2557 5 is_stmt 1 view .LVU1877 +2557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5344 .loc 1 2557 21 is_stmt 0 view .LVU1878 + 5345 007c 6363 str r3, [r4, #52] +2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5346 .loc 1 2560 5 is_stmt 1 view .LVU1879 +2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5347 .loc 1 2560 9 is_stmt 0 view .LVU1880 + 5348 007e 0196 str r6, [sp, #4] + 5349 0080 0097 str r7, [sp] + 5350 0082 4B46 mov r3, r9 + 5351 0084 4246 mov r2, r8 + 5352 0086 2946 mov r1, r5 + 5353 0088 2046 mov r0, r4 + 5354 008a FFF7FEFF bl I2C_RequestMemoryWrite + 5355 .LVL369: +2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5356 .loc 1 2560 8 discriminator 1 view .LVU1881 + 5357 008e 70B9 cbnz r0, .L363 +2568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5358 .loc 1 2568 5 is_stmt 1 view .LVU1882 +2568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5359 .loc 1 2568 13 is_stmt 0 view .LVU1883 + 5360 0090 638D ldrh r3, [r4, #42] + 5361 0092 9BB2 uxth r3, r3 +2568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5362 .loc 1 2568 8 view .LVU1884 + 5363 0094 FF2B cmp r3, #255 + 5364 0096 0FD9 bls .L349 +2570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTST + 5365 .loc 1 2570 7 is_stmt 1 view .LVU1885 +2570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTST + 5366 .loc 1 2570 22 is_stmt 0 view .LVU1886 + 5367 0098 FF22 movs r2, #255 + 5368 009a 2285 strh r2, [r4, #40] @ movhi +2571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5369 .loc 1 2571 7 is_stmt 1 view .LVU1887 + 5370 009c 0023 movs r3, #0 + ARM GAS /tmp/ccSHpINd.s page 258 + + + 5371 009e 0093 str r3, [sp] + 5372 00a0 4FF08073 mov r3, #16777216 + 5373 00a4 2946 mov r1, r5 + 5374 00a6 2046 mov r0, r4 + 5375 00a8 FFF7FEFF bl I2C_TransferConfig + 5376 .LVL370: + 5377 00ac 21E0 b .L353 + 5378 .L363: +2563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 5379 .loc 1 2563 7 view .LVU1888 +2563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 5380 .loc 1 2563 7 view .LVU1889 + 5381 00ae 0023 movs r3, #0 + 5382 00b0 84F84030 strb r3, [r4, #64] +2563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 5383 .loc 1 2563 7 view .LVU1890 +2564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5384 .loc 1 2564 7 view .LVU1891 +2564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5385 .loc 1 2564 14 is_stmt 0 view .LVU1892 + 5386 00b4 5846 mov r0, fp + 5387 00b6 6DE0 b .L346 + 5388 .L349: +2575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS + 5389 .loc 1 2575 7 is_stmt 1 view .LVU1893 +2575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS + 5390 .loc 1 2575 28 is_stmt 0 view .LVU1894 + 5391 00b8 628D ldrh r2, [r4, #42] + 5392 00ba 92B2 uxth r2, r2 +2575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS + 5393 .loc 1 2575 22 view .LVU1895 + 5394 00bc 2285 strh r2, [r4, #40] @ movhi +2576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5395 .loc 1 2576 7 is_stmt 1 view .LVU1896 + 5396 00be 0023 movs r3, #0 + 5397 00c0 0093 str r3, [sp] + 5398 00c2 4FF00073 mov r3, #33554432 + 5399 00c6 D2B2 uxtb r2, r2 + 5400 00c8 2946 mov r1, r5 + 5401 00ca 2046 mov r0, r4 + 5402 00cc FFF7FEFF bl I2C_TransferConfig + 5403 .LVL371: + 5404 00d0 0FE0 b .L353 + 5405 .L352: +2612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5406 .loc 1 2612 11 view .LVU1897 +2612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5407 .loc 1 2612 32 is_stmt 0 view .LVU1898 + 5408 00d2 628D ldrh r2, [r4, #42] + 5409 00d4 92B2 uxth r2, r2 +2612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5410 .loc 1 2612 26 view .LVU1899 + 5411 00d6 2285 strh r2, [r4, #40] @ movhi +2613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 5412 .loc 1 2613 11 is_stmt 1 view .LVU1900 + 5413 00d8 0023 movs r3, #0 + 5414 00da 0093 str r3, [sp] + ARM GAS /tmp/ccSHpINd.s page 259 + + + 5415 00dc 4FF00073 mov r3, #33554432 + 5416 00e0 D2B2 uxtb r2, r2 + 5417 00e2 2946 mov r1, r5 + 5418 00e4 2046 mov r0, r4 + 5419 00e6 FFF7FEFF bl I2C_TransferConfig + 5420 .LVL372: + 5421 .L351: +2618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5422 .loc 1 2618 30 view .LVU1901 +2618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5423 .loc 1 2618 18 is_stmt 0 view .LVU1902 + 5424 00ea 638D ldrh r3, [r4, #42] + 5425 00ec 9BB2 uxth r3, r3 +2618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5426 .loc 1 2618 30 view .LVU1903 + 5427 00ee 002B cmp r3, #0 + 5428 00f0 33D0 beq .L364 + 5429 .L353: +2579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5430 .loc 1 2579 5 is_stmt 1 view .LVU1904 +2582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5431 .loc 1 2582 7 view .LVU1905 +2582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5432 .loc 1 2582 11 is_stmt 0 view .LVU1906 + 5433 00f2 3246 mov r2, r6 + 5434 00f4 3946 mov r1, r7 + 5435 00f6 2046 mov r0, r4 + 5436 00f8 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 5437 .LVL373: +2582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5438 .loc 1 2582 10 discriminator 1 view .LVU1907 + 5439 00fc 0028 cmp r0, #0 + 5440 00fe 4ED1 bne .L357 +2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5441 .loc 1 2588 7 is_stmt 1 view .LVU1908 +2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5442 .loc 1 2588 35 is_stmt 0 view .LVU1909 + 5443 0100 626A ldr r2, [r4, #36] +2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5444 .loc 1 2588 11 view .LVU1910 + 5445 0102 2368 ldr r3, [r4] +2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5446 .loc 1 2588 30 view .LVU1911 + 5447 0104 1278 ldrb r2, [r2] @ zero_extendqisi2 +2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5448 .loc 1 2588 28 view .LVU1912 + 5449 0106 9A62 str r2, [r3, #40] +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5450 .loc 1 2591 7 is_stmt 1 view .LVU1913 +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5451 .loc 1 2591 11 is_stmt 0 view .LVU1914 + 5452 0108 636A ldr r3, [r4, #36] +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5453 .loc 1 2591 21 view .LVU1915 + 5454 010a 0133 adds r3, r3, #1 + 5455 010c 6362 str r3, [r4, #36] +2593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + ARM GAS /tmp/ccSHpINd.s page 260 + + + 5456 .loc 1 2593 7 is_stmt 1 view .LVU1916 +2593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 5457 .loc 1 2593 11 is_stmt 0 view .LVU1917 + 5458 010e 638D ldrh r3, [r4, #42] + 5459 0110 9BB2 uxth r3, r3 +2593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 5460 .loc 1 2593 22 view .LVU1918 + 5461 0112 013B subs r3, r3, #1 + 5462 0114 9BB2 uxth r3, r3 + 5463 0116 6385 strh r3, [r4, #42] @ movhi +2594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5464 .loc 1 2594 7 is_stmt 1 view .LVU1919 +2594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5465 .loc 1 2594 11 is_stmt 0 view .LVU1920 + 5466 0118 238D ldrh r3, [r4, #40] +2594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5467 .loc 1 2594 21 view .LVU1921 + 5468 011a 013B subs r3, r3, #1 + 5469 011c 9BB2 uxth r3, r3 + 5470 011e 2385 strh r3, [r4, #40] @ movhi +2596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5471 .loc 1 2596 7 is_stmt 1 view .LVU1922 +2596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5472 .loc 1 2596 16 is_stmt 0 view .LVU1923 + 5473 0120 628D ldrh r2, [r4, #42] + 5474 0122 92B2 uxth r2, r2 +2596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5475 .loc 1 2596 10 view .LVU1924 + 5476 0124 002A cmp r2, #0 + 5477 0126 E0D0 beq .L351 +2596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5478 .loc 1 2596 35 discriminator 1 view .LVU1925 + 5479 0128 002B cmp r3, #0 + 5480 012a DED1 bne .L351 +2599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5481 .loc 1 2599 9 is_stmt 1 view .LVU1926 +2599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5482 .loc 1 2599 13 is_stmt 0 view .LVU1927 + 5483 012c 0096 str r6, [sp] + 5484 012e 3B46 mov r3, r7 + 5485 0130 0022 movs r2, #0 + 5486 0132 8021 movs r1, #128 + 5487 0134 2046 mov r0, r4 + 5488 0136 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 5489 .LVL374: +2599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5490 .loc 1 2599 12 discriminator 1 view .LVU1928 + 5491 013a 90BB cbnz r0, .L358 +2604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5492 .loc 1 2604 9 is_stmt 1 view .LVU1929 +2604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5493 .loc 1 2604 17 is_stmt 0 view .LVU1930 + 5494 013c 638D ldrh r3, [r4, #42] + 5495 013e 9BB2 uxth r3, r3 +2604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5496 .loc 1 2604 12 view .LVU1931 + 5497 0140 FF2B cmp r3, #255 + ARM GAS /tmp/ccSHpINd.s page 261 + + + 5498 0142 C6D9 bls .L352 +2606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 5499 .loc 1 2606 11 is_stmt 1 view .LVU1932 +2606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 5500 .loc 1 2606 26 is_stmt 0 view .LVU1933 + 5501 0144 FF22 movs r2, #255 + 5502 0146 2285 strh r2, [r4, #40] @ movhi +2607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 5503 .loc 1 2607 11 is_stmt 1 view .LVU1934 + 5504 0148 0023 movs r3, #0 + 5505 014a 0093 str r3, [sp] + 5506 014c 4FF08073 mov r3, #16777216 + 5507 0150 2946 mov r1, r5 + 5508 0152 2046 mov r0, r4 + 5509 0154 FFF7FEFF bl I2C_TransferConfig + 5510 .LVL375: + 5511 0158 C7E7 b .L351 + 5512 .L364: +2622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5513 .loc 1 2622 5 view .LVU1935 +2622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5514 .loc 1 2622 9 is_stmt 0 view .LVU1936 + 5515 015a 3246 mov r2, r6 + 5516 015c 3946 mov r1, r7 + 5517 015e 2046 mov r0, r4 + 5518 0160 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 5519 .LVL376: +2622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5520 .loc 1 2622 8 discriminator 1 view .LVU1937 + 5521 0164 F8B9 cbnz r0, .L359 +2628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5522 .loc 1 2628 5 is_stmt 1 view .LVU1938 + 5523 0166 2368 ldr r3, [r4] + 5524 0168 2022 movs r2, #32 + 5525 016a DA61 str r2, [r3, #28] +2631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5526 .loc 1 2631 5 view .LVU1939 + 5527 016c 2168 ldr r1, [r4] + 5528 016e 4B68 ldr r3, [r1, #4] + 5529 0170 23F0FF73 bic r3, r3, #33423360 + 5530 0174 23F48B33 bic r3, r3, #71168 + 5531 0178 23F4FF73 bic r3, r3, #510 + 5532 017c 23F00103 bic r3, r3, #1 + 5533 0180 4B60 str r3, [r1, #4] +2633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5534 .loc 1 2633 5 view .LVU1940 +2633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5535 .loc 1 2633 17 is_stmt 0 view .LVU1941 + 5536 0182 84F84120 strb r2, [r4, #65] +2634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5537 .loc 1 2634 5 is_stmt 1 view .LVU1942 +2634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5538 .loc 1 2634 17 is_stmt 0 view .LVU1943 + 5539 0186 0023 movs r3, #0 + 5540 0188 84F84230 strb r3, [r4, #66] +2637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5541 .loc 1 2637 5 is_stmt 1 view .LVU1944 + ARM GAS /tmp/ccSHpINd.s page 262 + + +2637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5542 .loc 1 2637 5 view .LVU1945 + 5543 018c 84F84030 strb r3, [r4, #64] +2637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5544 .loc 1 2637 5 view .LVU1946 +2639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5545 .loc 1 2639 5 view .LVU1947 +2639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5546 .loc 1 2639 12 is_stmt 0 view .LVU1948 + 5547 0190 00E0 b .L346 + 5548 .LVL377: + 5549 .L354: +2643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5550 .loc 1 2643 12 view .LVU1949 + 5551 0192 0220 movs r0, #2 + 5552 .LVL378: + 5553 .L346: +2645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5554 .loc 1 2645 1 view .LVU1950 + 5555 0194 03B0 add sp, sp, #12 + 5556 .LCFI60: + 5557 .cfi_remember_state + 5558 .cfi_def_cfa_offset 36 + 5559 @ sp needed + 5560 0196 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 5561 .LVL379: + 5562 .L355: + 5563 .LCFI61: + 5564 .cfi_restore_state +2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5565 .loc 1 2540 5 discriminator 1 view .LVU1951 + 5566 019a 0220 movs r0, #2 + 5567 .LVL380: +2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5568 .loc 1 2540 5 discriminator 1 view .LVU1952 + 5569 019c FAE7 b .L346 + 5570 .LVL381: + 5571 .L357: +2584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5572 .loc 1 2584 16 view .LVU1953 + 5573 019e 0120 movs r0, #1 + 5574 01a0 F8E7 b .L346 + 5575 .L358: +2601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5576 .loc 1 2601 18 view .LVU1954 + 5577 01a2 0120 movs r0, #1 + 5578 01a4 F6E7 b .L346 + 5579 .L359: +2624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5580 .loc 1 2624 14 view .LVU1955 + 5581 01a6 0120 movs r0, #1 + 5582 01a8 F4E7 b .L346 + 5583 .cfi_endproc + 5584 .LFE157: + 5586 .section .text.HAL_I2C_Mem_Read,"ax",%progbits + 5587 .align 1 + 5588 .global HAL_I2C_Mem_Read + ARM GAS /tmp/ccSHpINd.s page 263 + + + 5589 .syntax unified + 5590 .thumb + 5591 .thumb_func + 5593 HAL_I2C_Mem_Read: + 5594 .LVL382: + 5595 .LFB158: +2662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; + 5596 .loc 1 2662 1 is_stmt 1 view -0 + 5597 .cfi_startproc + 5598 @ args = 12, pretend = 0, frame = 0 + 5599 @ frame_needed = 0, uses_anonymous_args = 0 +2662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; + 5600 .loc 1 2662 1 is_stmt 0 view .LVU1957 + 5601 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 5602 .LCFI62: + 5603 .cfi_def_cfa_offset 36 + 5604 .cfi_offset 4, -36 + 5605 .cfi_offset 5, -32 + 5606 .cfi_offset 6, -28 + 5607 .cfi_offset 7, -24 + 5608 .cfi_offset 8, -20 + 5609 .cfi_offset 9, -16 + 5610 .cfi_offset 10, -12 + 5611 .cfi_offset 11, -8 + 5612 .cfi_offset 14, -4 + 5613 0004 83B0 sub sp, sp, #12 + 5614 .LCFI63: + 5615 .cfi_def_cfa_offset 48 + 5616 0006 0D46 mov r5, r1 + 5617 0008 BDF834A0 ldrh r10, [sp, #52] + 5618 000c 0E9F ldr r7, [sp, #56] +2663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5619 .loc 1 2663 3 is_stmt 1 view .LVU1958 +2666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5620 .loc 1 2666 3 view .LVU1959 +2668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5621 .loc 1 2668 3 view .LVU1960 +2668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5622 .loc 1 2668 11 is_stmt 0 view .LVU1961 + 5623 000e 90F84110 ldrb r1, [r0, #65] @ zero_extendqisi2 + 5624 .LVL383: +2668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5625 .loc 1 2668 11 view .LVU1962 + 5626 0012 C9B2 uxtb r1, r1 +2668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5627 .loc 1 2668 6 view .LVU1963 + 5628 0014 2029 cmp r1, #32 + 5629 0016 40F0BD80 bne .L374 + 5630 001a 0446 mov r4, r0 + 5631 001c 9046 mov r8, r2 + 5632 001e 9946 mov r9, r3 +2670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5633 .loc 1 2670 5 is_stmt 1 view .LVU1964 +2670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5634 .loc 1 2670 8 is_stmt 0 view .LVU1965 + 5635 0020 0C9B ldr r3, [sp, #48] + 5636 .LVL384: + ARM GAS /tmp/ccSHpINd.s page 264 + + +2670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5637 .loc 1 2670 8 view .LVU1966 + 5638 0022 BAF1000F cmp r10, #0 + 5639 0026 18BF it ne + 5640 0028 002B cmpne r3, #0 + 5641 002a 16D0 beq .L381 +2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5642 .loc 1 2677 5 is_stmt 1 view .LVU1967 +2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5643 .loc 1 2677 5 view .LVU1968 + 5644 002c 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 5645 0030 012B cmp r3, #1 + 5646 0032 00F0B380 beq .L375 +2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5647 .loc 1 2677 5 discriminator 2 view .LVU1969 + 5648 0036 4FF0010B mov fp, #1 + 5649 003a 80F840B0 strb fp, [r0, #64] +2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5650 .loc 1 2677 5 discriminator 2 view .LVU1970 +2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5651 .loc 1 2680 5 view .LVU1971 +2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5652 .loc 1 2680 17 is_stmt 0 view .LVU1972 + 5653 003e FFF7FEFF bl HAL_GetTick + 5654 .LVL385: +2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5655 .loc 1 2680 17 view .LVU1973 + 5656 0042 0646 mov r6, r0 + 5657 .LVL386: +2682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5658 .loc 1 2682 5 is_stmt 1 view .LVU1974 +2682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5659 .loc 1 2682 9 is_stmt 0 view .LVU1975 + 5660 0044 0090 str r0, [sp] + 5661 0046 1923 movs r3, #25 + 5662 0048 5A46 mov r2, fp + 5663 004a 4FF40041 mov r1, #32768 + 5664 004e 2046 mov r0, r4 + 5665 .LVL387: +2682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5666 .loc 1 2682 9 view .LVU1976 + 5667 0050 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 5668 .LVL388: +2682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5669 .loc 1 2682 8 discriminator 1 view .LVU1977 + 5670 0054 30B1 cbz r0, .L382 +2684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5671 .loc 1 2684 14 view .LVU1978 + 5672 0056 0120 movs r0, #1 + 5673 0058 9DE0 b .L366 + 5674 .LVL389: + 5675 .L381: +2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 5676 .loc 1 2672 7 is_stmt 1 view .LVU1979 +2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 5677 .loc 1 2672 23 is_stmt 0 view .LVU1980 + 5678 005a 4FF40073 mov r3, #512 + ARM GAS /tmp/ccSHpINd.s page 265 + + + 5679 005e 4364 str r3, [r0, #68] +2673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5680 .loc 1 2673 7 is_stmt 1 view .LVU1981 +2673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5681 .loc 1 2673 15 is_stmt 0 view .LVU1982 + 5682 0060 0120 movs r0, #1 + 5683 .LVL390: +2673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5684 .loc 1 2673 15 view .LVU1983 + 5685 0062 98E0 b .L366 + 5686 .LVL391: + 5687 .L382: +2687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5688 .loc 1 2687 5 is_stmt 1 view .LVU1984 +2687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5689 .loc 1 2687 21 is_stmt 0 view .LVU1985 + 5690 0064 2223 movs r3, #34 + 5691 0066 84F84130 strb r3, [r4, #65] +2688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5692 .loc 1 2688 5 is_stmt 1 view .LVU1986 +2688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5693 .loc 1 2688 21 is_stmt 0 view .LVU1987 + 5694 006a 4023 movs r3, #64 + 5695 006c 84F84230 strb r3, [r4, #66] +2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5696 .loc 1 2689 5 is_stmt 1 view .LVU1988 +2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5697 .loc 1 2689 21 is_stmt 0 view .LVU1989 + 5698 0070 0023 movs r3, #0 + 5699 0072 6364 str r3, [r4, #68] +2692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 5700 .loc 1 2692 5 is_stmt 1 view .LVU1990 +2692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 5701 .loc 1 2692 21 is_stmt 0 view .LVU1991 + 5702 0074 0C9A ldr r2, [sp, #48] + 5703 0076 6262 str r2, [r4, #36] +2693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 5704 .loc 1 2693 5 is_stmt 1 view .LVU1992 +2693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 5705 .loc 1 2693 21 is_stmt 0 view .LVU1993 + 5706 0078 A4F82AA0 strh r10, [r4, #42] @ movhi +2694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5707 .loc 1 2694 5 is_stmt 1 view .LVU1994 +2694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5708 .loc 1 2694 21 is_stmt 0 view .LVU1995 + 5709 007c 6363 str r3, [r4, #52] +2697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5710 .loc 1 2697 5 is_stmt 1 view .LVU1996 +2697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5711 .loc 1 2697 9 is_stmt 0 view .LVU1997 + 5712 007e 0196 str r6, [sp, #4] + 5713 0080 0097 str r7, [sp] + 5714 0082 4B46 mov r3, r9 + 5715 0084 4246 mov r2, r8 + 5716 0086 2946 mov r1, r5 + 5717 0088 2046 mov r0, r4 + 5718 008a FFF7FEFF bl I2C_RequestMemoryRead + ARM GAS /tmp/ccSHpINd.s page 266 + + + 5719 .LVL392: +2697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5720 .loc 1 2697 8 discriminator 1 view .LVU1998 + 5721 008e 70B9 cbnz r0, .L383 +2706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5722 .loc 1 2706 5 is_stmt 1 view .LVU1999 +2706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5723 .loc 1 2706 13 is_stmt 0 view .LVU2000 + 5724 0090 638D ldrh r3, [r4, #42] + 5725 0092 9BB2 uxth r3, r3 +2706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5726 .loc 1 2706 8 view .LVU2001 + 5727 0094 FF2B cmp r3, #255 + 5728 0096 0FD9 bls .L369 +2708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 5729 .loc 1 2708 7 is_stmt 1 view .LVU2002 +2708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 5730 .loc 1 2708 22 is_stmt 0 view .LVU2003 + 5731 0098 0122 movs r2, #1 + 5732 009a 2285 strh r2, [r4, #40] @ movhi +2709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 5733 .loc 1 2709 7 is_stmt 1 view .LVU2004 + 5734 009c 434B ldr r3, .L385 + 5735 009e 0093 str r3, [sp] + 5736 00a0 4FF08073 mov r3, #16777216 + 5737 00a4 2946 mov r1, r5 + 5738 00a6 2046 mov r0, r4 + 5739 00a8 FFF7FEFF bl I2C_TransferConfig + 5740 .LVL393: + 5741 00ac 21E0 b .L373 + 5742 .L383: +2700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 5743 .loc 1 2700 7 view .LVU2005 +2700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 5744 .loc 1 2700 7 view .LVU2006 + 5745 00ae 0023 movs r3, #0 + 5746 00b0 84F84030 strb r3, [r4, #64] +2700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 5747 .loc 1 2700 7 view .LVU2007 +2701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5748 .loc 1 2701 7 view .LVU2008 +2701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5749 .loc 1 2701 14 is_stmt 0 view .LVU2009 + 5750 00b4 5846 mov r0, fp + 5751 00b6 6EE0 b .L366 + 5752 .L369: +2714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5753 .loc 1 2714 7 is_stmt 1 view .LVU2010 +2714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5754 .loc 1 2714 28 is_stmt 0 view .LVU2011 + 5755 00b8 628D ldrh r2, [r4, #42] + 5756 00ba 92B2 uxth r2, r2 +2714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5757 .loc 1 2714 22 view .LVU2012 + 5758 00bc 2285 strh r2, [r4, #40] @ movhi +2715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 5759 .loc 1 2715 7 is_stmt 1 view .LVU2013 + ARM GAS /tmp/ccSHpINd.s page 267 + + + 5760 00be 3B4B ldr r3, .L385 + 5761 00c0 0093 str r3, [sp] + 5762 00c2 4FF00073 mov r3, #33554432 + 5763 00c6 D2B2 uxtb r2, r2 + 5764 00c8 2946 mov r1, r5 + 5765 00ca 2046 mov r0, r4 + 5766 00cc FFF7FEFF bl I2C_TransferConfig + 5767 .LVL394: + 5768 00d0 0FE0 b .L373 + 5769 .L372: +2752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5770 .loc 1 2752 11 view .LVU2014 +2752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5771 .loc 1 2752 32 is_stmt 0 view .LVU2015 + 5772 00d2 628D ldrh r2, [r4, #42] + 5773 00d4 92B2 uxth r2, r2 +2752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5774 .loc 1 2752 26 view .LVU2016 + 5775 00d6 2285 strh r2, [r4, #40] @ movhi +2753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 5776 .loc 1 2753 11 is_stmt 1 view .LVU2017 + 5777 00d8 0023 movs r3, #0 + 5778 00da 0093 str r3, [sp] + 5779 00dc 4FF00073 mov r3, #33554432 + 5780 00e0 D2B2 uxtb r2, r2 + 5781 00e2 2946 mov r1, r5 + 5782 00e4 2046 mov r0, r4 + 5783 00e6 FFF7FEFF bl I2C_TransferConfig + 5784 .LVL395: + 5785 .L371: +2757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5786 .loc 1 2757 30 view .LVU2018 +2757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5787 .loc 1 2757 18 is_stmt 0 view .LVU2019 + 5788 00ea 638D ldrh r3, [r4, #42] + 5789 00ec 9BB2 uxth r3, r3 +2757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5790 .loc 1 2757 30 view .LVU2020 + 5791 00ee 002B cmp r3, #0 + 5792 00f0 34D0 beq .L384 + 5793 .L373: +2719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5794 .loc 1 2719 5 is_stmt 1 view .LVU2021 +2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5795 .loc 1 2722 7 view .LVU2022 +2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5796 .loc 1 2722 11 is_stmt 0 view .LVU2023 + 5797 00f2 0096 str r6, [sp] + 5798 00f4 3B46 mov r3, r7 + 5799 00f6 0022 movs r2, #0 + 5800 00f8 0421 movs r1, #4 + 5801 00fa 2046 mov r0, r4 + 5802 00fc FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 5803 .LVL396: +2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5804 .loc 1 2722 10 discriminator 1 view .LVU2024 + 5805 0100 0028 cmp r0, #0 + ARM GAS /tmp/ccSHpINd.s page 268 + + + 5806 0102 4DD1 bne .L377 +2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5807 .loc 1 2728 7 is_stmt 1 view .LVU2025 +2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5808 .loc 1 2728 38 is_stmt 0 view .LVU2026 + 5809 0104 2368 ldr r3, [r4] +2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5810 .loc 1 2728 48 view .LVU2027 + 5811 0106 5A6A ldr r2, [r3, #36] +2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5812 .loc 1 2728 12 view .LVU2028 + 5813 0108 636A ldr r3, [r4, #36] +2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5814 .loc 1 2728 23 view .LVU2029 + 5815 010a 1A70 strb r2, [r3] +2731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5816 .loc 1 2731 7 is_stmt 1 view .LVU2030 +2731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5817 .loc 1 2731 11 is_stmt 0 view .LVU2031 + 5818 010c 636A ldr r3, [r4, #36] +2731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5819 .loc 1 2731 21 view .LVU2032 + 5820 010e 0133 adds r3, r3, #1 + 5821 0110 6362 str r3, [r4, #36] +2733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 5822 .loc 1 2733 7 is_stmt 1 view .LVU2033 +2733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 5823 .loc 1 2733 11 is_stmt 0 view .LVU2034 + 5824 0112 228D ldrh r2, [r4, #40] +2733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 5825 .loc 1 2733 21 view .LVU2035 + 5826 0114 013A subs r2, r2, #1 + 5827 0116 92B2 uxth r2, r2 + 5828 0118 2285 strh r2, [r4, #40] @ movhi +2734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5829 .loc 1 2734 7 is_stmt 1 view .LVU2036 +2734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5830 .loc 1 2734 11 is_stmt 0 view .LVU2037 + 5831 011a 638D ldrh r3, [r4, #42] + 5832 011c 9BB2 uxth r3, r3 +2734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5833 .loc 1 2734 22 view .LVU2038 + 5834 011e 013B subs r3, r3, #1 + 5835 0120 9BB2 uxth r3, r3 + 5836 0122 6385 strh r3, [r4, #42] @ movhi +2736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5837 .loc 1 2736 7 is_stmt 1 view .LVU2039 +2736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5838 .loc 1 2736 16 is_stmt 0 view .LVU2040 + 5839 0124 638D ldrh r3, [r4, #42] + 5840 0126 9BB2 uxth r3, r3 +2736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5841 .loc 1 2736 10 view .LVU2041 + 5842 0128 002B cmp r3, #0 + 5843 012a DED0 beq .L371 +2736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5844 .loc 1 2736 35 discriminator 1 view .LVU2042 + ARM GAS /tmp/ccSHpINd.s page 269 + + + 5845 012c 002A cmp r2, #0 + 5846 012e DCD1 bne .L371 +2739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5847 .loc 1 2739 9 is_stmt 1 view .LVU2043 +2739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5848 .loc 1 2739 13 is_stmt 0 view .LVU2044 + 5849 0130 0096 str r6, [sp] + 5850 0132 3B46 mov r3, r7 + 5851 0134 8021 movs r1, #128 + 5852 0136 2046 mov r0, r4 + 5853 0138 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 5854 .LVL397: +2739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5855 .loc 1 2739 12 discriminator 1 view .LVU2045 + 5856 013c 90BB cbnz r0, .L378 +2744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5857 .loc 1 2744 9 is_stmt 1 view .LVU2046 +2744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5858 .loc 1 2744 17 is_stmt 0 view .LVU2047 + 5859 013e 638D ldrh r3, [r4, #42] + 5860 0140 9BB2 uxth r3, r3 +2744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5861 .loc 1 2744 12 view .LVU2048 + 5862 0142 FF2B cmp r3, #255 + 5863 0144 C5D9 bls .L372 +2746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + 5864 .loc 1 2746 11 is_stmt 1 view .LVU2049 +2746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + 5865 .loc 1 2746 26 is_stmt 0 view .LVU2050 + 5866 0146 0122 movs r2, #1 + 5867 0148 2285 strh r2, [r4, #40] @ movhi +2747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 5868 .loc 1 2747 11 is_stmt 1 view .LVU2051 + 5869 014a 0023 movs r3, #0 + 5870 014c 0093 str r3, [sp] + 5871 014e 4FF08073 mov r3, #16777216 + 5872 0152 2946 mov r1, r5 + 5873 0154 2046 mov r0, r4 + 5874 0156 FFF7FEFF bl I2C_TransferConfig + 5875 .LVL398: + 5876 015a C6E7 b .L371 + 5877 .L384: +2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5878 .loc 1 2761 5 view .LVU2052 +2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5879 .loc 1 2761 9 is_stmt 0 view .LVU2053 + 5880 015c 3246 mov r2, r6 + 5881 015e 3946 mov r1, r7 + 5882 0160 2046 mov r0, r4 + 5883 0162 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 5884 .LVL399: +2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5885 .loc 1 2761 8 discriminator 1 view .LVU2054 + 5886 0166 F8B9 cbnz r0, .L379 +2767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5887 .loc 1 2767 5 is_stmt 1 view .LVU2055 + 5888 0168 2368 ldr r3, [r4] + ARM GAS /tmp/ccSHpINd.s page 270 + + + 5889 016a 2022 movs r2, #32 + 5890 016c DA61 str r2, [r3, #28] +2770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5891 .loc 1 2770 5 view .LVU2056 + 5892 016e 2168 ldr r1, [r4] + 5893 0170 4B68 ldr r3, [r1, #4] + 5894 0172 23F0FF73 bic r3, r3, #33423360 + 5895 0176 23F48B33 bic r3, r3, #71168 + 5896 017a 23F4FF73 bic r3, r3, #510 + 5897 017e 23F00103 bic r3, r3, #1 + 5898 0182 4B60 str r3, [r1, #4] +2772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5899 .loc 1 2772 5 view .LVU2057 +2772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5900 .loc 1 2772 17 is_stmt 0 view .LVU2058 + 5901 0184 84F84120 strb r2, [r4, #65] +2773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5902 .loc 1 2773 5 is_stmt 1 view .LVU2059 +2773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5903 .loc 1 2773 17 is_stmt 0 view .LVU2060 + 5904 0188 0023 movs r3, #0 + 5905 018a 84F84230 strb r3, [r4, #66] +2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5906 .loc 1 2776 5 is_stmt 1 view .LVU2061 +2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5907 .loc 1 2776 5 view .LVU2062 + 5908 018e 84F84030 strb r3, [r4, #64] +2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5909 .loc 1 2776 5 view .LVU2063 +2778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5910 .loc 1 2778 5 view .LVU2064 +2778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5911 .loc 1 2778 12 is_stmt 0 view .LVU2065 + 5912 0192 00E0 b .L366 + 5913 .LVL400: + 5914 .L374: +2782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5915 .loc 1 2782 12 view .LVU2066 + 5916 0194 0220 movs r0, #2 + 5917 .LVL401: + 5918 .L366: +2784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /** + 5919 .loc 1 2784 1 view .LVU2067 + 5920 0196 03B0 add sp, sp, #12 + 5921 .LCFI64: + 5922 .cfi_remember_state + 5923 .cfi_def_cfa_offset 36 + 5924 @ sp needed + 5925 0198 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 5926 .LVL402: + 5927 .L375: + 5928 .LCFI65: + 5929 .cfi_restore_state +2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5930 .loc 1 2677 5 discriminator 1 view .LVU2068 + 5931 019c 0220 movs r0, #2 + 5932 .LVL403: + ARM GAS /tmp/ccSHpINd.s page 271 + + +2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5933 .loc 1 2677 5 discriminator 1 view .LVU2069 + 5934 019e FAE7 b .L366 + 5935 .LVL404: + 5936 .L377: +2724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5937 .loc 1 2724 16 view .LVU2070 + 5938 01a0 0120 movs r0, #1 + 5939 01a2 F8E7 b .L366 + 5940 .L378: +2741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5941 .loc 1 2741 18 view .LVU2071 + 5942 01a4 0120 movs r0, #1 + 5943 01a6 F6E7 b .L366 + 5944 .L379: +2763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 5945 .loc 1 2763 14 view .LVU2072 + 5946 01a8 0120 movs r0, #1 + 5947 01aa F4E7 b .L366 + 5948 .L386: + 5949 .align 2 + 5950 .L385: + 5951 01ac 00240080 .word -2147474432 + 5952 .cfi_endproc + 5953 .LFE158: + 5955 .section .text.HAL_I2C_Mem_Write_IT,"ax",%progbits + 5956 .align 1 + 5957 .global HAL_I2C_Mem_Write_IT + 5958 .syntax unified + 5959 .thumb + 5960 .thumb_func + 5962 HAL_I2C_Mem_Write_IT: + 5963 .LVL405: + 5964 .LFB159: +2799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ + 5965 .loc 1 2799 1 is_stmt 1 view -0 + 5966 .cfi_startproc + 5967 @ args = 8, pretend = 0, frame = 0 + 5968 @ frame_needed = 0, uses_anonymous_args = 0 +2799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ + 5969 .loc 1 2799 1 is_stmt 0 view .LVU2074 + 5970 0000 70B5 push {r4, r5, r6, lr} + 5971 .LCFI66: + 5972 .cfi_def_cfa_offset 16 + 5973 .cfi_offset 4, -16 + 5974 .cfi_offset 5, -12 + 5975 .cfi_offset 6, -8 + 5976 .cfi_offset 14, -4 + 5977 0002 82B0 sub sp, sp, #8 + 5978 .LCFI67: + 5979 .cfi_def_cfa_offset 24 + 5980 0004 0446 mov r4, r0 + 5981 0006 1D46 mov r5, r3 + 5982 0008 BDF81C30 ldrh r3, [sp, #28] + 5983 .LVL406: +2801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 5984 .loc 1 2801 3 is_stmt 1 view .LVU2075 + ARM GAS /tmp/ccSHpINd.s page 272 + + +2803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5985 .loc 1 2803 3 view .LVU2076 +2803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5986 .loc 1 2803 11 is_stmt 0 view .LVU2077 + 5987 000c 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 5988 .LVL407: +2803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5989 .loc 1 2803 11 view .LVU2078 + 5990 0010 C0B2 uxtb r0, r0 +2803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5991 .loc 1 2803 6 view .LVU2079 + 5992 0012 2028 cmp r0, #32 + 5993 0014 43D1 bne .L392 +2805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5994 .loc 1 2805 5 is_stmt 1 view .LVU2080 +2805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 5995 .loc 1 2805 8 is_stmt 0 view .LVU2081 + 5996 0016 0698 ldr r0, [sp, #24] + 5997 0018 002B cmp r3, #0 + 5998 001a 18BF it ne + 5999 001c 0028 cmpne r0, #0 + 6000 001e 33D0 beq .L396 +2811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6001 .loc 1 2811 5 is_stmt 1 view .LVU2082 +2811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6002 .loc 1 2811 9 is_stmt 0 view .LVU2083 + 6003 0020 2068 ldr r0, [r4] + 6004 0022 8669 ldr r6, [r0, #24] +2811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6005 .loc 1 2811 8 view .LVU2084 + 6006 0024 16F4004F tst r6, #32768 + 6007 0028 3CD1 bne .L393 +2817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6008 .loc 1 2817 5 is_stmt 1 view .LVU2085 +2817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6009 .loc 1 2817 5 view .LVU2086 + 6010 002a 94F84060 ldrb r6, [r4, #64] @ zero_extendqisi2 + 6011 002e 012E cmp r6, #1 + 6012 0030 3AD0 beq .L394 +2817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6013 .loc 1 2817 5 discriminator 2 view .LVU2087 + 6014 0032 0126 movs r6, #1 + 6015 0034 84F84060 strb r6, [r4, #64] +2817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6016 .loc 1 2817 5 discriminator 2 view .LVU2088 +2819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 6017 .loc 1 2819 5 view .LVU2089 +2819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 6018 .loc 1 2819 23 is_stmt 0 view .LVU2090 + 6019 0038 2126 movs r6, #33 + 6020 003a 84F84160 strb r6, [r4, #65] +2820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6021 .loc 1 2820 5 is_stmt 1 view .LVU2091 +2820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6022 .loc 1 2820 23 is_stmt 0 view .LVU2092 + 6023 003e 4026 movs r6, #64 + 6024 0040 84F84260 strb r6, [r4, #66] + ARM GAS /tmp/ccSHpINd.s page 273 + + +2821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6025 .loc 1 2821 5 is_stmt 1 view .LVU2093 +2821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6026 .loc 1 2821 23 is_stmt 0 view .LVU2094 + 6027 0044 0026 movs r6, #0 + 6028 0046 6664 str r6, [r4, #68] +2824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 6029 .loc 1 2824 5 is_stmt 1 view .LVU2095 +2824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 6030 .loc 1 2824 23 is_stmt 0 view .LVU2096 + 6031 0048 2685 strh r6, [r4, #40] @ movhi +2825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 6032 .loc 1 2825 5 is_stmt 1 view .LVU2097 +2825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 6033 .loc 1 2825 23 is_stmt 0 view .LVU2098 + 6034 004a 069E ldr r6, [sp, #24] + 6035 004c 6662 str r6, [r4, #36] +2826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 6036 .loc 1 2826 5 is_stmt 1 view .LVU2099 +2826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 6037 .loc 1 2826 23 is_stmt 0 view .LVU2100 + 6038 004e 6385 strh r3, [r4, #42] @ movhi +2827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Mem_ISR_IT; + 6039 .loc 1 2827 5 is_stmt 1 view .LVU2101 +2827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Mem_ISR_IT; + 6040 .loc 1 2827 23 is_stmt 0 view .LVU2102 + 6041 0050 164B ldr r3, .L398 + 6042 0052 E362 str r3, [r4, #44] +2828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Devaddress = DevAddress; + 6043 .loc 1 2828 5 is_stmt 1 view .LVU2103 +2828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Devaddress = DevAddress; + 6044 .loc 1 2828 23 is_stmt 0 view .LVU2104 + 6045 0054 164B ldr r3, .L398+4 + 6046 0056 6363 str r3, [r4, #52] +2829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6047 .loc 1 2829 5 is_stmt 1 view .LVU2105 +2829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6048 .loc 1 2829 23 is_stmt 0 view .LVU2106 + 6049 0058 E164 str r1, [r4, #76] +2832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6050 .loc 1 2832 5 is_stmt 1 view .LVU2107 +2832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6051 .loc 1 2832 8 is_stmt 0 view .LVU2108 + 6052 005a 012D cmp r5, #1 + 6053 005c 19D0 beq .L397 +2844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6054 .loc 1 2844 7 is_stmt 1 view .LVU2109 +2844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6055 .loc 1 2844 30 is_stmt 0 view .LVU2110 + 6056 005e 130A lsrs r3, r2, #8 +2844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6057 .loc 1 2844 28 view .LVU2111 + 6058 0060 8362 str r3, [r0, #40] +2847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6059 .loc 1 2847 7 is_stmt 1 view .LVU2112 +2847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6060 .loc 1 2847 26 is_stmt 0 view .LVU2113 + ARM GAS /tmp/ccSHpINd.s page 274 + + + 6061 0062 D2B2 uxtb r2, r2 + 6062 .LVL408: +2847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6063 .loc 1 2847 24 view .LVU2114 + 6064 0064 2265 str r2, [r4, #80] + 6065 .L391: +2850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6066 .loc 1 2850 5 is_stmt 1 view .LVU2115 + 6067 0066 134B ldr r3, .L398+8 + 6068 0068 0093 str r3, [sp] + 6069 006a 4FF08073 mov r3, #16777216 + 6070 006e EAB2 uxtb r2, r5 + 6071 0070 2046 mov r0, r4 + 6072 0072 FFF7FEFF bl I2C_TransferConfig + 6073 .LVL409: +2853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6074 .loc 1 2853 5 view .LVU2116 +2853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6075 .loc 1 2853 5 view .LVU2117 + 6076 0076 0025 movs r5, #0 + 6077 .LVL410: +2853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6078 .loc 1 2853 5 is_stmt 0 view .LVU2118 + 6079 0078 84F84050 strb r5, [r4, #64] +2853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6080 .loc 1 2853 5 is_stmt 1 view .LVU2119 +2863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6081 .loc 1 2863 5 view .LVU2120 + 6082 007c 0121 movs r1, #1 + 6083 007e 2046 mov r0, r4 + 6084 0080 FFF7FEFF bl I2C_Enable_IRQ + 6085 .LVL411: +2865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6086 .loc 1 2865 5 view .LVU2121 +2865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6087 .loc 1 2865 12 is_stmt 0 view .LVU2122 + 6088 0084 2846 mov r0, r5 + 6089 0086 0BE0 b .L388 + 6090 .LVL412: + 6091 .L396: +2807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 6092 .loc 1 2807 7 is_stmt 1 view .LVU2123 +2807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 6093 .loc 1 2807 23 is_stmt 0 view .LVU2124 + 6094 0088 4FF40073 mov r3, #512 + 6095 008c 6364 str r3, [r4, #68] +2808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6096 .loc 1 2808 7 is_stmt 1 view .LVU2125 +2808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6097 .loc 1 2808 15 is_stmt 0 view .LVU2126 + 6098 008e 0120 movs r0, #1 + 6099 0090 06E0 b .L388 + 6100 .L397: +2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6101 .loc 1 2835 7 is_stmt 1 view .LVU2127 +2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6102 .loc 1 2835 30 is_stmt 0 view .LVU2128 + ARM GAS /tmp/ccSHpINd.s page 275 + + + 6103 0092 D2B2 uxtb r2, r2 + 6104 .LVL413: +2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6105 .loc 1 2835 28 view .LVU2129 + 6106 0094 8262 str r2, [r0, #40] +2838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6107 .loc 1 2838 7 is_stmt 1 view .LVU2130 +2838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6108 .loc 1 2838 24 is_stmt 0 view .LVU2131 + 6109 0096 4FF0FF33 mov r3, #-1 + 6110 009a 2365 str r3, [r4, #80] + 6111 009c E3E7 b .L391 + 6112 .LVL414: + 6113 .L392: +2869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6114 .loc 1 2869 12 view .LVU2132 + 6115 009e 0220 movs r0, #2 + 6116 .LVL415: + 6117 .L388: +2871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6118 .loc 1 2871 1 view .LVU2133 + 6119 00a0 02B0 add sp, sp, #8 + 6120 .LCFI68: + 6121 .cfi_remember_state + 6122 .cfi_def_cfa_offset 16 + 6123 @ sp needed + 6124 00a2 70BD pop {r4, r5, r6, pc} + 6125 .LVL416: + 6126 .L393: + 6127 .LCFI69: + 6128 .cfi_restore_state +2813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6129 .loc 1 2813 14 view .LVU2134 + 6130 00a4 0220 movs r0, #2 + 6131 00a6 FBE7 b .L388 + 6132 .L394: +2817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6133 .loc 1 2817 5 discriminator 1 view .LVU2135 + 6134 00a8 0220 movs r0, #2 + 6135 00aa F9E7 b .L388 + 6136 .L399: + 6137 .align 2 + 6138 .L398: + 6139 00ac 0000FFFF .word -65536 + 6140 00b0 00000000 .word I2C_Mem_ISR_IT + 6141 00b4 00200080 .word -2147475456 + 6142 .cfi_endproc + 6143 .LFE159: + 6145 .section .text.HAL_I2C_Mem_Read_IT,"ax",%progbits + 6146 .align 1 + 6147 .global HAL_I2C_Mem_Read_IT + 6148 .syntax unified + 6149 .thumb + 6150 .thumb_func + 6152 HAL_I2C_Mem_Read_IT: + 6153 .LVL417: + 6154 .LFB160: + ARM GAS /tmp/ccSHpINd.s page 276 + + +2887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ + 6155 .loc 1 2887 1 is_stmt 1 view -0 + 6156 .cfi_startproc + 6157 @ args = 8, pretend = 0, frame = 0 + 6158 @ frame_needed = 0, uses_anonymous_args = 0 +2887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Check the parameters */ + 6159 .loc 1 2887 1 is_stmt 0 view .LVU2137 + 6160 0000 70B5 push {r4, r5, r6, lr} + 6161 .LCFI70: + 6162 .cfi_def_cfa_offset 16 + 6163 .cfi_offset 4, -16 + 6164 .cfi_offset 5, -12 + 6165 .cfi_offset 6, -8 + 6166 .cfi_offset 14, -4 + 6167 0002 82B0 sub sp, sp, #8 + 6168 .LCFI71: + 6169 .cfi_def_cfa_offset 24 + 6170 0004 0446 mov r4, r0 + 6171 0006 1D46 mov r5, r3 + 6172 0008 BDF81C30 ldrh r3, [sp, #28] + 6173 .LVL418: +2889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6174 .loc 1 2889 3 is_stmt 1 view .LVU2138 +2891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6175 .loc 1 2891 3 view .LVU2139 +2891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6176 .loc 1 2891 11 is_stmt 0 view .LVU2140 + 6177 000c 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 6178 .LVL419: +2891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6179 .loc 1 2891 11 view .LVU2141 + 6180 0010 C0B2 uxtb r0, r0 +2891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6181 .loc 1 2891 6 view .LVU2142 + 6182 0012 2028 cmp r0, #32 + 6183 0014 41D1 bne .L405 +2893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6184 .loc 1 2893 5 is_stmt 1 view .LVU2143 +2893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6185 .loc 1 2893 8 is_stmt 0 view .LVU2144 + 6186 0016 0698 ldr r0, [sp, #24] + 6187 0018 002B cmp r3, #0 + 6188 001a 18BF it ne + 6189 001c 0028 cmpne r0, #0 + 6190 001e 31D0 beq .L409 +2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6191 .loc 1 2899 5 is_stmt 1 view .LVU2145 +2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6192 .loc 1 2899 9 is_stmt 0 view .LVU2146 + 6193 0020 2068 ldr r0, [r4] + 6194 0022 8669 ldr r6, [r0, #24] +2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6195 .loc 1 2899 8 view .LVU2147 + 6196 0024 16F4004F tst r6, #32768 + 6197 0028 3AD1 bne .L406 +2905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6198 .loc 1 2905 5 is_stmt 1 view .LVU2148 + ARM GAS /tmp/ccSHpINd.s page 277 + + +2905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6199 .loc 1 2905 5 view .LVU2149 + 6200 002a 94F84060 ldrb r6, [r4, #64] @ zero_extendqisi2 + 6201 002e 012E cmp r6, #1 + 6202 0030 38D0 beq .L407 +2905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6203 .loc 1 2905 5 discriminator 2 view .LVU2150 + 6204 0032 0126 movs r6, #1 + 6205 0034 84F84060 strb r6, [r4, #64] +2905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6206 .loc 1 2905 5 discriminator 2 view .LVU2151 +2907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 6207 .loc 1 2907 5 view .LVU2152 +2907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 6208 .loc 1 2907 23 is_stmt 0 view .LVU2153 + 6209 0038 2226 movs r6, #34 + 6210 003a 84F84160 strb r6, [r4, #65] +2908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6211 .loc 1 2908 5 is_stmt 1 view .LVU2154 +2908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6212 .loc 1 2908 23 is_stmt 0 view .LVU2155 + 6213 003e 4026 movs r6, #64 + 6214 0040 84F84260 strb r6, [r4, #66] +2909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6215 .loc 1 2909 5 is_stmt 1 view .LVU2156 +2909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6216 .loc 1 2909 23 is_stmt 0 view .LVU2157 + 6217 0044 0026 movs r6, #0 + 6218 0046 6664 str r6, [r4, #68] +2912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 6219 .loc 1 2912 5 is_stmt 1 view .LVU2158 +2912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 6220 .loc 1 2912 23 is_stmt 0 view .LVU2159 + 6221 0048 069E ldr r6, [sp, #24] + 6222 004a 6662 str r6, [r4, #36] +2913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 6223 .loc 1 2913 5 is_stmt 1 view .LVU2160 +2913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 6224 .loc 1 2913 23 is_stmt 0 view .LVU2161 + 6225 004c 6385 strh r3, [r4, #42] @ movhi +2914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Mem_ISR_IT; + 6226 .loc 1 2914 5 is_stmt 1 view .LVU2162 +2914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Mem_ISR_IT; + 6227 .loc 1 2914 23 is_stmt 0 view .LVU2163 + 6228 004e 164B ldr r3, .L411 + 6229 0050 E362 str r3, [r4, #44] +2915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Devaddress = DevAddress; + 6230 .loc 1 2915 5 is_stmt 1 view .LVU2164 +2915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Devaddress = DevAddress; + 6231 .loc 1 2915 23 is_stmt 0 view .LVU2165 + 6232 0052 164B ldr r3, .L411+4 + 6233 0054 6363 str r3, [r4, #52] +2916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6234 .loc 1 2916 5 is_stmt 1 view .LVU2166 +2916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6235 .loc 1 2916 23 is_stmt 0 view .LVU2167 + 6236 0056 E164 str r1, [r4, #76] + ARM GAS /tmp/ccSHpINd.s page 278 + + +2919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6237 .loc 1 2919 5 is_stmt 1 view .LVU2168 +2919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6238 .loc 1 2919 8 is_stmt 0 view .LVU2169 + 6239 0058 012D cmp r5, #1 + 6240 005a 18D0 beq .L410 +2931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6241 .loc 1 2931 7 is_stmt 1 view .LVU2170 +2931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6242 .loc 1 2931 30 is_stmt 0 view .LVU2171 + 6243 005c 130A lsrs r3, r2, #8 +2931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6244 .loc 1 2931 28 view .LVU2172 + 6245 005e 8362 str r3, [r0, #40] +2934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6246 .loc 1 2934 7 is_stmt 1 view .LVU2173 +2934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6247 .loc 1 2934 26 is_stmt 0 view .LVU2174 + 6248 0060 D2B2 uxtb r2, r2 + 6249 .LVL420: +2934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6250 .loc 1 2934 24 view .LVU2175 + 6251 0062 2265 str r2, [r4, #80] + 6252 .L404: +2937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6253 .loc 1 2937 5 is_stmt 1 view .LVU2176 + 6254 0064 124B ldr r3, .L411+8 + 6255 0066 0093 str r3, [sp] + 6256 0068 0023 movs r3, #0 + 6257 006a EAB2 uxtb r2, r5 + 6258 006c 2046 mov r0, r4 + 6259 006e FFF7FEFF bl I2C_TransferConfig + 6260 .LVL421: +2940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6261 .loc 1 2940 5 view .LVU2177 +2940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6262 .loc 1 2940 5 view .LVU2178 + 6263 0072 0025 movs r5, #0 + 6264 .LVL422: +2940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6265 .loc 1 2940 5 is_stmt 0 view .LVU2179 + 6266 0074 84F84050 strb r5, [r4, #64] +2940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6267 .loc 1 2940 5 is_stmt 1 view .LVU2180 +2950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6268 .loc 1 2950 5 view .LVU2181 + 6269 0078 0121 movs r1, #1 + 6270 007a 2046 mov r0, r4 + 6271 007c FFF7FEFF bl I2C_Enable_IRQ + 6272 .LVL423: +2952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6273 .loc 1 2952 5 view .LVU2182 +2952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6274 .loc 1 2952 12 is_stmt 0 view .LVU2183 + 6275 0080 2846 mov r0, r5 + 6276 0082 0BE0 b .L401 + 6277 .LVL424: + ARM GAS /tmp/ccSHpINd.s page 279 + + + 6278 .L409: +2895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 6279 .loc 1 2895 7 is_stmt 1 view .LVU2184 +2895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 6280 .loc 1 2895 23 is_stmt 0 view .LVU2185 + 6281 0084 4FF40073 mov r3, #512 + 6282 0088 6364 str r3, [r4, #68] +2896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6283 .loc 1 2896 7 is_stmt 1 view .LVU2186 +2896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6284 .loc 1 2896 15 is_stmt 0 view .LVU2187 + 6285 008a 0120 movs r0, #1 + 6286 008c 06E0 b .L401 + 6287 .L410: +2922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6288 .loc 1 2922 7 is_stmt 1 view .LVU2188 +2922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6289 .loc 1 2922 30 is_stmt 0 view .LVU2189 + 6290 008e D2B2 uxtb r2, r2 + 6291 .LVL425: +2922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6292 .loc 1 2922 28 view .LVU2190 + 6293 0090 8262 str r2, [r0, #40] +2925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6294 .loc 1 2925 7 is_stmt 1 view .LVU2191 +2925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6295 .loc 1 2925 24 is_stmt 0 view .LVU2192 + 6296 0092 4FF0FF33 mov r3, #-1 + 6297 0096 2365 str r3, [r4, #80] + 6298 0098 E4E7 b .L404 + 6299 .LVL426: + 6300 .L405: +2956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6301 .loc 1 2956 12 view .LVU2193 + 6302 009a 0220 movs r0, #2 + 6303 .LVL427: + 6304 .L401: +2958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6305 .loc 1 2958 1 view .LVU2194 + 6306 009c 02B0 add sp, sp, #8 + 6307 .LCFI72: + 6308 .cfi_remember_state + 6309 .cfi_def_cfa_offset 16 + 6310 @ sp needed + 6311 009e 70BD pop {r4, r5, r6, pc} + 6312 .LVL428: + 6313 .L406: + 6314 .LCFI73: + 6315 .cfi_restore_state +2901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6316 .loc 1 2901 14 view .LVU2195 + 6317 00a0 0220 movs r0, #2 + 6318 00a2 FBE7 b .L401 + 6319 .L407: +2905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6320 .loc 1 2905 5 discriminator 1 view .LVU2196 + 6321 00a4 0220 movs r0, #2 + ARM GAS /tmp/ccSHpINd.s page 280 + + + 6322 00a6 F9E7 b .L401 + 6323 .L412: + 6324 .align 2 + 6325 .L411: + 6326 00a8 0000FFFF .word -65536 + 6327 00ac 00000000 .word I2C_Mem_ISR_IT + 6328 00b0 00200080 .word -2147475456 + 6329 .cfi_endproc + 6330 .LFE160: + 6332 .section .text.HAL_I2C_Mem_Write_DMA,"ax",%progbits + 6333 .align 1 + 6334 .global HAL_I2C_Mem_Write_DMA + 6335 .syntax unified + 6336 .thumb + 6337 .thumb_func + 6339 HAL_I2C_Mem_Write_DMA: + 6340 .LVL429: + 6341 .LFB161: +2974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 6342 .loc 1 2974 1 is_stmt 1 view -0 + 6343 .cfi_startproc + 6344 @ args = 8, pretend = 0, frame = 0 + 6345 @ frame_needed = 0, uses_anonymous_args = 0 +2974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 6346 .loc 1 2974 1 is_stmt 0 view .LVU2198 + 6347 0000 F0B5 push {r4, r5, r6, r7, lr} + 6348 .LCFI74: + 6349 .cfi_def_cfa_offset 20 + 6350 .cfi_offset 4, -20 + 6351 .cfi_offset 5, -16 + 6352 .cfi_offset 6, -12 + 6353 .cfi_offset 7, -8 + 6354 .cfi_offset 14, -4 + 6355 0002 83B0 sub sp, sp, #12 + 6356 .LCFI75: + 6357 .cfi_def_cfa_offset 32 + 6358 0004 0446 mov r4, r0 + 6359 0006 0E46 mov r6, r1 + 6360 0008 1F46 mov r7, r3 + 6361 000a 0899 ldr r1, [sp, #32] + 6362 .LVL430: +2974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 6363 .loc 1 2974 1 view .LVU2199 + 6364 000c BDF82430 ldrh r3, [sp, #36] + 6365 .LVL431: +2975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6366 .loc 1 2975 3 is_stmt 1 view .LVU2200 +2978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6367 .loc 1 2978 3 view .LVU2201 +2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6368 .loc 1 2980 3 view .LVU2202 +2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6369 .loc 1 2980 11 is_stmt 0 view .LVU2203 + 6370 0010 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 6371 .LVL432: +2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6372 .loc 1 2980 11 view .LVU2204 + ARM GAS /tmp/ccSHpINd.s page 281 + + + 6373 0014 C0B2 uxtb r0, r0 +2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6374 .loc 1 2980 6 view .LVU2205 + 6375 0016 2028 cmp r0, #32 + 6376 0018 7AD1 bne .L423 +2982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6377 .loc 1 2982 5 is_stmt 1 view .LVU2206 +2982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6378 .loc 1 2982 8 is_stmt 0 view .LVU2207 + 6379 001a 002B cmp r3, #0 + 6380 001c 18BF it ne + 6381 001e 0029 cmpne r1, #0 + 6382 0020 49D0 beq .L428 +2988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6383 .loc 1 2988 5 is_stmt 1 view .LVU2208 +2988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6384 .loc 1 2988 9 is_stmt 0 view .LVU2209 + 6385 0022 2068 ldr r0, [r4] + 6386 0024 8569 ldr r5, [r0, #24] +2988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6387 .loc 1 2988 8 view .LVU2210 + 6388 0026 15F4004F tst r5, #32768 + 6389 002a 75D1 bne .L424 +2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6390 .loc 1 2994 5 is_stmt 1 view .LVU2211 +2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6391 .loc 1 2994 5 view .LVU2212 + 6392 002c 94F84050 ldrb r5, [r4, #64] @ zero_extendqisi2 + 6393 0030 012D cmp r5, #1 + 6394 0032 73D0 beq .L425 +2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6395 .loc 1 2994 5 discriminator 2 view .LVU2213 + 6396 0034 0125 movs r5, #1 + 6397 0036 84F84050 strb r5, [r4, #64] +2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6398 .loc 1 2994 5 discriminator 2 view .LVU2214 +2996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 6399 .loc 1 2996 5 view .LVU2215 +2996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 6400 .loc 1 2996 23 is_stmt 0 view .LVU2216 + 6401 003a 2125 movs r5, #33 + 6402 003c 84F84150 strb r5, [r4, #65] +2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6403 .loc 1 2997 5 is_stmt 1 view .LVU2217 +2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6404 .loc 1 2997 23 is_stmt 0 view .LVU2218 + 6405 0040 4025 movs r5, #64 + 6406 0042 84F84250 strb r5, [r4, #66] +2998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6407 .loc 1 2998 5 is_stmt 1 view .LVU2219 +2998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6408 .loc 1 2998 23 is_stmt 0 view .LVU2220 + 6409 0046 0025 movs r5, #0 + 6410 0048 6564 str r5, [r4, #68] +3001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 6411 .loc 1 3001 5 is_stmt 1 view .LVU2221 +3001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + ARM GAS /tmp/ccSHpINd.s page 282 + + + 6412 .loc 1 3001 23 is_stmt 0 view .LVU2222 + 6413 004a 6162 str r1, [r4, #36] +3002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 6414 .loc 1 3002 5 is_stmt 1 view .LVU2223 +3002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 6415 .loc 1 3002 23 is_stmt 0 view .LVU2224 + 6416 004c 6385 strh r3, [r4, #42] @ movhi +3003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Mem_ISR_DMA; + 6417 .loc 1 3003 5 is_stmt 1 view .LVU2225 +3003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Mem_ISR_DMA; + 6418 .loc 1 3003 23 is_stmt 0 view .LVU2226 + 6419 004e 344B ldr r3, .L431 + 6420 0050 E362 str r3, [r4, #44] +3004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Devaddress = DevAddress; + 6421 .loc 1 3004 5 is_stmt 1 view .LVU2227 +3004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Devaddress = DevAddress; + 6422 .loc 1 3004 23 is_stmt 0 view .LVU2228 + 6423 0052 344B ldr r3, .L431+4 + 6424 0054 6363 str r3, [r4, #52] +3005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6425 .loc 1 3005 5 is_stmt 1 view .LVU2229 +3005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6426 .loc 1 3005 23 is_stmt 0 view .LVU2230 + 6427 0056 E664 str r6, [r4, #76] +3007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6428 .loc 1 3007 5 is_stmt 1 view .LVU2231 +3007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6429 .loc 1 3007 13 is_stmt 0 view .LVU2232 + 6430 0058 638D ldrh r3, [r4, #42] + 6431 005a 9BB2 uxth r3, r3 +3007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6432 .loc 1 3007 8 view .LVU2233 + 6433 005c FF2B cmp r3, #255 + 6434 005e 2FD9 bls .L416 +3009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6435 .loc 1 3009 7 is_stmt 1 view .LVU2234 +3009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6436 .loc 1 3009 22 is_stmt 0 view .LVU2235 + 6437 0060 FF23 movs r3, #255 + 6438 0062 2385 strh r3, [r4, #40] @ movhi + 6439 .L417: +3017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6440 .loc 1 3017 5 is_stmt 1 view .LVU2236 +3017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6441 .loc 1 3017 8 is_stmt 0 view .LVU2237 + 6442 0064 012F cmp r7, #1 + 6443 0066 2ED0 beq .L429 +3029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6444 .loc 1 3029 7 is_stmt 1 view .LVU2238 +3029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6445 .loc 1 3029 30 is_stmt 0 view .LVU2239 + 6446 0068 130A lsrs r3, r2, #8 +3029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6447 .loc 1 3029 28 view .LVU2240 + 6448 006a 8362 str r3, [r0, #40] +3032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6449 .loc 1 3032 7 is_stmt 1 view .LVU2241 + ARM GAS /tmp/ccSHpINd.s page 283 + + +3032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6450 .loc 1 3032 26 is_stmt 0 view .LVU2242 + 6451 006c D2B2 uxtb r2, r2 + 6452 .LVL433: +3032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6453 .loc 1 3032 24 view .LVU2243 + 6454 006e 2265 str r2, [r4, #80] + 6455 .L419: +3035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6456 .loc 1 3035 5 is_stmt 1 view .LVU2244 +3035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6457 .loc 1 3035 13 is_stmt 0 view .LVU2245 + 6458 0070 A36B ldr r3, [r4, #56] +3035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6459 .loc 1 3035 8 view .LVU2246 + 6460 0072 002B cmp r3, #0 + 6461 0074 2DD0 beq .L420 +3038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6462 .loc 1 3038 7 is_stmt 1 view .LVU2247 +3038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6463 .loc 1 3038 38 is_stmt 0 view .LVU2248 + 6464 0076 2C4A ldr r2, .L431+8 + 6465 0078 DA63 str r2, [r3, #60] +3041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6466 .loc 1 3041 7 is_stmt 1 view .LVU2249 +3041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6467 .loc 1 3041 11 is_stmt 0 view .LVU2250 + 6468 007a A36B ldr r3, [r4, #56] +3041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6469 .loc 1 3041 39 view .LVU2251 + 6470 007c 2B4A ldr r2, .L431+12 + 6471 007e DA64 str r2, [r3, #76] +3044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 6472 .loc 1 3044 7 is_stmt 1 view .LVU2252 +3044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 6473 .loc 1 3044 11 is_stmt 0 view .LVU2253 + 6474 0080 A26B ldr r2, [r4, #56] +3044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 6475 .loc 1 3044 42 view .LVU2254 + 6476 0082 0023 movs r3, #0 + 6477 0084 1364 str r3, [r2, #64] +3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6478 .loc 1 3045 7 is_stmt 1 view .LVU2255 +3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6479 .loc 1 3045 11 is_stmt 0 view .LVU2256 + 6480 0086 A26B ldr r2, [r4, #56] +3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6481 .loc 1 3045 39 view .LVU2257 + 6482 0088 1365 str r3, [r2, #80] +3048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 6483 .loc 1 3048 7 is_stmt 1 view .LVU2258 +3048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 6484 .loc 1 3048 86 is_stmt 0 view .LVU2259 + 6485 008a 2268 ldr r2, [r4] +3048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 6486 .loc 1 3048 23 view .LVU2260 + 6487 008c 238D ldrh r3, [r4, #40] + ARM GAS /tmp/ccSHpINd.s page 284 + + + 6488 008e 2832 adds r2, r2, #40 + 6489 0090 A06B ldr r0, [r4, #56] + 6490 0092 FFF7FEFF bl HAL_DMA_Start_IT + 6491 .LVL434: +3066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6492 .loc 1 3066 5 is_stmt 1 view .LVU2261 +3066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6493 .loc 1 3066 8 is_stmt 0 view .LVU2262 + 6494 0096 0546 mov r5, r0 + 6495 0098 48B3 cbz r0, .L430 +3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6496 .loc 1 3086 7 is_stmt 1 view .LVU2263 +3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6497 .loc 1 3086 23 is_stmt 0 view .LVU2264 + 6498 009a 2023 movs r3, #32 + 6499 009c 84F84130 strb r3, [r4, #65] +3087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6500 .loc 1 3087 7 is_stmt 1 view .LVU2265 +3087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6501 .loc 1 3087 23 is_stmt 0 view .LVU2266 + 6502 00a0 0022 movs r2, #0 + 6503 00a2 84F84220 strb r2, [r4, #66] +3090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6504 .loc 1 3090 7 is_stmt 1 view .LVU2267 +3090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6505 .loc 1 3090 11 is_stmt 0 view .LVU2268 + 6506 00a6 636C ldr r3, [r4, #68] +3090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6507 .loc 1 3090 23 view .LVU2269 + 6508 00a8 43F01003 orr r3, r3, #16 + 6509 00ac 6364 str r3, [r4, #68] +3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6510 .loc 1 3093 7 is_stmt 1 view .LVU2270 +3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6511 .loc 1 3093 7 view .LVU2271 + 6512 00ae 84F84020 strb r2, [r4, #64] +3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6513 .loc 1 3093 7 view .LVU2272 +3095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6514 .loc 1 3095 7 view .LVU2273 +3095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6515 .loc 1 3095 14 is_stmt 0 view .LVU2274 + 6516 00b2 0125 movs r5, #1 + 6517 00b4 2DE0 b .L414 + 6518 .LVL435: + 6519 .L428: +2984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 6520 .loc 1 2984 7 is_stmt 1 view .LVU2275 +2984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 6521 .loc 1 2984 23 is_stmt 0 view .LVU2276 + 6522 00b6 4FF40073 mov r3, #512 + 6523 00ba 6364 str r3, [r4, #68] +2985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6524 .loc 1 2985 7 is_stmt 1 view .LVU2277 +2985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6525 .loc 1 2985 15 is_stmt 0 view .LVU2278 + 6526 00bc 0125 movs r5, #1 + ARM GAS /tmp/ccSHpINd.s page 285 + + + 6527 00be 28E0 b .L414 + 6528 .L416: +3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6529 .loc 1 3013 7 is_stmt 1 view .LVU2279 +3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6530 .loc 1 3013 28 is_stmt 0 view .LVU2280 + 6531 00c0 638D ldrh r3, [r4, #42] +3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6532 .loc 1 3013 22 view .LVU2281 + 6533 00c2 2385 strh r3, [r4, #40] @ movhi + 6534 00c4 CEE7 b .L417 + 6535 .L429: +3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6536 .loc 1 3020 7 is_stmt 1 view .LVU2282 +3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6537 .loc 1 3020 30 is_stmt 0 view .LVU2283 + 6538 00c6 D2B2 uxtb r2, r2 + 6539 .LVL436: +3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6540 .loc 1 3020 28 view .LVU2284 + 6541 00c8 8262 str r2, [r0, #40] +3023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6542 .loc 1 3023 7 is_stmt 1 view .LVU2285 +3023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6543 .loc 1 3023 24 is_stmt 0 view .LVU2286 + 6544 00ca 4FF0FF33 mov r3, #-1 + 6545 00ce 2365 str r3, [r4, #80] + 6546 00d0 CEE7 b .L419 + 6547 .L420: +3054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6548 .loc 1 3054 7 is_stmt 1 view .LVU2287 +3054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6549 .loc 1 3054 23 is_stmt 0 view .LVU2288 + 6550 00d2 2023 movs r3, #32 + 6551 00d4 84F84130 strb r3, [r4, #65] +3055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6552 .loc 1 3055 7 is_stmt 1 view .LVU2289 +3055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6553 .loc 1 3055 23 is_stmt 0 view .LVU2290 + 6554 00d8 0022 movs r2, #0 + 6555 00da 84F84220 strb r2, [r4, #66] +3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6556 .loc 1 3058 7 is_stmt 1 view .LVU2291 +3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6557 .loc 1 3058 11 is_stmt 0 view .LVU2292 + 6558 00de 636C ldr r3, [r4, #68] +3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6559 .loc 1 3058 23 view .LVU2293 + 6560 00e0 43F08003 orr r3, r3, #128 + 6561 00e4 6364 str r3, [r4, #68] +3061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6562 .loc 1 3061 7 is_stmt 1 view .LVU2294 +3061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6563 .loc 1 3061 7 view .LVU2295 + 6564 00e6 84F84020 strb r2, [r4, #64] +3061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6565 .loc 1 3061 7 view .LVU2296 + ARM GAS /tmp/ccSHpINd.s page 286 + + +3063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6566 .loc 1 3063 7 view .LVU2297 +3063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6567 .loc 1 3063 14 is_stmt 0 view .LVU2298 + 6568 00ea 0125 movs r5, #1 + 6569 00ec 11E0 b .L414 + 6570 .LVL437: + 6571 .L430: +3069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6572 .loc 1 3069 7 is_stmt 1 view .LVU2299 + 6573 00ee 104B ldr r3, .L431+16 + 6574 00f0 0093 str r3, [sp] + 6575 00f2 4FF08073 mov r3, #16777216 + 6576 00f6 FAB2 uxtb r2, r7 + 6577 00f8 3146 mov r1, r6 + 6578 00fa 2046 mov r0, r4 + 6579 .LVL438: +3069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6580 .loc 1 3069 7 is_stmt 0 view .LVU2300 + 6581 00fc FFF7FEFF bl I2C_TransferConfig + 6582 .LVL439: +3072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6583 .loc 1 3072 7 is_stmt 1 view .LVU2301 +3072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6584 .loc 1 3072 7 view .LVU2302 + 6585 0100 0023 movs r3, #0 + 6586 0102 84F84030 strb r3, [r4, #64] +3072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6587 .loc 1 3072 7 view .LVU2303 +3081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6588 .loc 1 3081 7 view .LVU2304 + 6589 0106 0121 movs r1, #1 + 6590 0108 2046 mov r0, r4 + 6591 010a FFF7FEFF bl I2C_Enable_IRQ + 6592 .LVL440: +3098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6593 .loc 1 3098 5 view .LVU2305 +3098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6594 .loc 1 3098 12 is_stmt 0 view .LVU2306 + 6595 010e 00E0 b .L414 + 6596 .LVL441: + 6597 .L423: +3102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6598 .loc 1 3102 12 view .LVU2307 + 6599 0110 0225 movs r5, #2 + 6600 .LVL442: + 6601 .L414: +3104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6602 .loc 1 3104 1 view .LVU2308 + 6603 0112 2846 mov r0, r5 + 6604 0114 03B0 add sp, sp, #12 + 6605 .LCFI76: + 6606 .cfi_remember_state + 6607 .cfi_def_cfa_offset 20 + 6608 @ sp needed + 6609 0116 F0BD pop {r4, r5, r6, r7, pc} + 6610 .LVL443: + ARM GAS /tmp/ccSHpINd.s page 287 + + + 6611 .L424: + 6612 .LCFI77: + 6613 .cfi_restore_state +2990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6614 .loc 1 2990 14 view .LVU2309 + 6615 0118 0225 movs r5, #2 + 6616 011a FAE7 b .L414 + 6617 .L425: +2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6618 .loc 1 2994 5 discriminator 1 view .LVU2310 + 6619 011c 0225 movs r5, #2 + 6620 011e F8E7 b .L414 + 6621 .L432: + 6622 .align 2 + 6623 .L431: + 6624 0120 0000FFFF .word -65536 + 6625 0124 00000000 .word I2C_Mem_ISR_DMA + 6626 0128 00000000 .word I2C_DMAMasterTransmitCplt + 6627 012c 00000000 .word I2C_DMAError + 6628 0130 00200080 .word -2147475456 + 6629 .cfi_endproc + 6630 .LFE161: + 6632 .section .text.HAL_I2C_Mem_Read_DMA,"ax",%progbits + 6633 .align 1 + 6634 .global HAL_I2C_Mem_Read_DMA + 6635 .syntax unified + 6636 .thumb + 6637 .thumb_func + 6639 HAL_I2C_Mem_Read_DMA: + 6640 .LVL444: + 6641 .LFB162: +3120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 6642 .loc 1 3120 1 is_stmt 1 view -0 + 6643 .cfi_startproc + 6644 @ args = 8, pretend = 0, frame = 0 + 6645 @ frame_needed = 0, uses_anonymous_args = 0 +3120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 6646 .loc 1 3120 1 is_stmt 0 view .LVU2312 + 6647 0000 F0B5 push {r4, r5, r6, r7, lr} + 6648 .LCFI78: + 6649 .cfi_def_cfa_offset 20 + 6650 .cfi_offset 4, -20 + 6651 .cfi_offset 5, -16 + 6652 .cfi_offset 6, -12 + 6653 .cfi_offset 7, -8 + 6654 .cfi_offset 14, -4 + 6655 0002 83B0 sub sp, sp, #12 + 6656 .LCFI79: + 6657 .cfi_def_cfa_offset 32 + 6658 0004 0446 mov r4, r0 + 6659 0006 1F46 mov r7, r3 + 6660 0008 089D ldr r5, [sp, #32] + 6661 000a BDF82430 ldrh r3, [sp, #36] + 6662 .LVL445: +3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6663 .loc 1 3121 3 is_stmt 1 view .LVU2313 +3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 288 + + + 6664 .loc 1 3124 3 view .LVU2314 +3126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6665 .loc 1 3126 3 view .LVU2315 +3126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6666 .loc 1 3126 11 is_stmt 0 view .LVU2316 + 6667 000e 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 6668 .LVL446: +3126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6669 .loc 1 3126 11 view .LVU2317 + 6670 0012 C0B2 uxtb r0, r0 +3126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6671 .loc 1 3126 6 view .LVU2318 + 6672 0014 2028 cmp r0, #32 + 6673 0016 7BD1 bne .L443 + 6674 0018 0E46 mov r6, r1 +3128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6675 .loc 1 3128 5 is_stmt 1 view .LVU2319 +3128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6676 .loc 1 3128 8 is_stmt 0 view .LVU2320 + 6677 001a 002B cmp r3, #0 + 6678 001c 18BF it ne + 6679 001e 002D cmpne r5, #0 + 6680 0020 4AD0 beq .L448 +3134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6681 .loc 1 3134 5 is_stmt 1 view .LVU2321 +3134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6682 .loc 1 3134 9 is_stmt 0 view .LVU2322 + 6683 0022 2168 ldr r1, [r4] + 6684 .LVL447: +3134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6685 .loc 1 3134 9 view .LVU2323 + 6686 0024 8869 ldr r0, [r1, #24] +3134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6687 .loc 1 3134 8 view .LVU2324 + 6688 0026 10F4004F tst r0, #32768 + 6689 002a 75D1 bne .L444 +3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6690 .loc 1 3140 5 is_stmt 1 view .LVU2325 +3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6691 .loc 1 3140 5 view .LVU2326 + 6692 002c 94F84000 ldrb r0, [r4, #64] @ zero_extendqisi2 + 6693 0030 0128 cmp r0, #1 + 6694 0032 73D0 beq .L445 +3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6695 .loc 1 3140 5 discriminator 2 view .LVU2327 + 6696 0034 0120 movs r0, #1 + 6697 0036 84F84000 strb r0, [r4, #64] +3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6698 .loc 1 3140 5 discriminator 2 view .LVU2328 +3142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 6699 .loc 1 3142 5 view .LVU2329 +3142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 6700 .loc 1 3142 23 is_stmt 0 view .LVU2330 + 6701 003a 2220 movs r0, #34 + 6702 003c 84F84100 strb r0, [r4, #65] +3143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6703 .loc 1 3143 5 is_stmt 1 view .LVU2331 + ARM GAS /tmp/ccSHpINd.s page 289 + + +3143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6704 .loc 1 3143 23 is_stmt 0 view .LVU2332 + 6705 0040 4020 movs r0, #64 + 6706 0042 84F84200 strb r0, [r4, #66] +3144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6707 .loc 1 3144 5 is_stmt 1 view .LVU2333 +3144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6708 .loc 1 3144 23 is_stmt 0 view .LVU2334 + 6709 0046 0020 movs r0, #0 + 6710 0048 6064 str r0, [r4, #68] +3147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 6711 .loc 1 3147 5 is_stmt 1 view .LVU2335 +3147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 6712 .loc 1 3147 23 is_stmt 0 view .LVU2336 + 6713 004a 6562 str r5, [r4, #36] +3148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 6714 .loc 1 3148 5 is_stmt 1 view .LVU2337 +3148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 6715 .loc 1 3148 23 is_stmt 0 view .LVU2338 + 6716 004c 6385 strh r3, [r4, #42] @ movhi +3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Mem_ISR_DMA; + 6717 .loc 1 3149 5 is_stmt 1 view .LVU2339 +3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Mem_ISR_DMA; + 6718 .loc 1 3149 23 is_stmt 0 view .LVU2340 + 6719 004e 344B ldr r3, .L451 + 6720 0050 E362 str r3, [r4, #44] +3150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Devaddress = DevAddress; + 6721 .loc 1 3150 5 is_stmt 1 view .LVU2341 +3150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Devaddress = DevAddress; + 6722 .loc 1 3150 23 is_stmt 0 view .LVU2342 + 6723 0052 344B ldr r3, .L451+4 + 6724 0054 6363 str r3, [r4, #52] +3151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6725 .loc 1 3151 5 is_stmt 1 view .LVU2343 +3151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6726 .loc 1 3151 23 is_stmt 0 view .LVU2344 + 6727 0056 E664 str r6, [r4, #76] +3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6728 .loc 1 3153 5 is_stmt 1 view .LVU2345 +3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6729 .loc 1 3153 13 is_stmt 0 view .LVU2346 + 6730 0058 638D ldrh r3, [r4, #42] + 6731 005a 9BB2 uxth r3, r3 +3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6732 .loc 1 3153 8 view .LVU2347 + 6733 005c FF2B cmp r3, #255 + 6734 005e 30D9 bls .L436 +3155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6735 .loc 1 3155 7 is_stmt 1 view .LVU2348 +3155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6736 .loc 1 3155 22 is_stmt 0 view .LVU2349 + 6737 0060 FF23 movs r3, #255 + 6738 0062 2385 strh r3, [r4, #40] @ movhi + 6739 .L437: +3163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6740 .loc 1 3163 5 is_stmt 1 view .LVU2350 +3163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 290 + + + 6741 .loc 1 3163 8 is_stmt 0 view .LVU2351 + 6742 0064 012F cmp r7, #1 + 6743 0066 2FD0 beq .L449 +3175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6744 .loc 1 3175 7 is_stmt 1 view .LVU2352 +3175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6745 .loc 1 3175 30 is_stmt 0 view .LVU2353 + 6746 0068 130A lsrs r3, r2, #8 +3175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6747 .loc 1 3175 28 view .LVU2354 + 6748 006a 8B62 str r3, [r1, #40] +3178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6749 .loc 1 3178 7 is_stmt 1 view .LVU2355 +3178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6750 .loc 1 3178 26 is_stmt 0 view .LVU2356 + 6751 006c D2B2 uxtb r2, r2 + 6752 .LVL448: +3178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6753 .loc 1 3178 24 view .LVU2357 + 6754 006e 2265 str r2, [r4, #80] + 6755 .L439: +3181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6756 .loc 1 3181 5 is_stmt 1 view .LVU2358 +3181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6757 .loc 1 3181 13 is_stmt 0 view .LVU2359 + 6758 0070 E36B ldr r3, [r4, #60] +3181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6759 .loc 1 3181 8 view .LVU2360 + 6760 0072 002B cmp r3, #0 + 6761 0074 2ED0 beq .L440 +3184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6762 .loc 1 3184 7 is_stmt 1 view .LVU2361 +3184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6763 .loc 1 3184 38 is_stmt 0 view .LVU2362 + 6764 0076 2C4A ldr r2, .L451+8 + 6765 0078 DA63 str r2, [r3, #60] +3187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6766 .loc 1 3187 7 is_stmt 1 view .LVU2363 +3187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6767 .loc 1 3187 11 is_stmt 0 view .LVU2364 + 6768 007a E36B ldr r3, [r4, #60] +3187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6769 .loc 1 3187 39 view .LVU2365 + 6770 007c 2B4A ldr r2, .L451+12 + 6771 007e DA64 str r2, [r3, #76] +3190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 6772 .loc 1 3190 7 is_stmt 1 view .LVU2366 +3190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 6773 .loc 1 3190 11 is_stmt 0 view .LVU2367 + 6774 0080 E26B ldr r2, [r4, #60] +3190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 6775 .loc 1 3190 42 view .LVU2368 + 6776 0082 0023 movs r3, #0 + 6777 0084 1364 str r3, [r2, #64] +3191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6778 .loc 1 3191 7 is_stmt 1 view .LVU2369 +3191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 291 + + + 6779 .loc 1 3191 11 is_stmt 0 view .LVU2370 + 6780 0086 E26B ldr r2, [r4, #60] +3191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6781 .loc 1 3191 39 view .LVU2371 + 6782 0088 1365 str r3, [r2, #80] +3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 6783 .loc 1 3194 7 is_stmt 1 view .LVU2372 +3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 6784 .loc 1 3194 69 is_stmt 0 view .LVU2373 + 6785 008a 2168 ldr r1, [r4] +3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 6786 .loc 1 3194 23 view .LVU2374 + 6787 008c 238D ldrh r3, [r4, #40] + 6788 008e 2A46 mov r2, r5 + 6789 0090 2431 adds r1, r1, #36 + 6790 0092 E06B ldr r0, [r4, #60] + 6791 0094 FFF7FEFF bl HAL_DMA_Start_IT + 6792 .LVL449: +3212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6793 .loc 1 3212 5 is_stmt 1 view .LVU2375 +3212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6794 .loc 1 3212 8 is_stmt 0 view .LVU2376 + 6795 0098 0546 mov r5, r0 + 6796 009a 48B3 cbz r0, .L450 +3232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6797 .loc 1 3232 7 is_stmt 1 view .LVU2377 +3232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6798 .loc 1 3232 23 is_stmt 0 view .LVU2378 + 6799 009c 2023 movs r3, #32 + 6800 009e 84F84130 strb r3, [r4, #65] +3233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6801 .loc 1 3233 7 is_stmt 1 view .LVU2379 +3233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6802 .loc 1 3233 23 is_stmt 0 view .LVU2380 + 6803 00a2 0022 movs r2, #0 + 6804 00a4 84F84220 strb r2, [r4, #66] +3236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6805 .loc 1 3236 7 is_stmt 1 view .LVU2381 +3236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6806 .loc 1 3236 11 is_stmt 0 view .LVU2382 + 6807 00a8 636C ldr r3, [r4, #68] +3236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6808 .loc 1 3236 23 view .LVU2383 + 6809 00aa 43F01003 orr r3, r3, #16 + 6810 00ae 6364 str r3, [r4, #68] +3239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6811 .loc 1 3239 7 is_stmt 1 view .LVU2384 +3239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6812 .loc 1 3239 7 view .LVU2385 + 6813 00b0 84F84020 strb r2, [r4, #64] +3239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6814 .loc 1 3239 7 view .LVU2386 +3241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6815 .loc 1 3241 7 view .LVU2387 +3241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6816 .loc 1 3241 14 is_stmt 0 view .LVU2388 + 6817 00b4 0125 movs r5, #1 + ARM GAS /tmp/ccSHpINd.s page 292 + + + 6818 00b6 2CE0 b .L434 + 6819 .LVL450: + 6820 .L448: +3130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 6821 .loc 1 3130 7 is_stmt 1 view .LVU2389 +3130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 6822 .loc 1 3130 23 is_stmt 0 view .LVU2390 + 6823 00b8 4FF40073 mov r3, #512 + 6824 00bc 6364 str r3, [r4, #68] +3131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6825 .loc 1 3131 7 is_stmt 1 view .LVU2391 +3131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6826 .loc 1 3131 15 is_stmt 0 view .LVU2392 + 6827 00be 0125 movs r5, #1 + 6828 00c0 27E0 b .L434 + 6829 .LVL451: + 6830 .L436: +3159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6831 .loc 1 3159 7 is_stmt 1 view .LVU2393 +3159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6832 .loc 1 3159 28 is_stmt 0 view .LVU2394 + 6833 00c2 638D ldrh r3, [r4, #42] +3159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6834 .loc 1 3159 22 view .LVU2395 + 6835 00c4 2385 strh r3, [r4, #40] @ movhi + 6836 00c6 CDE7 b .L437 + 6837 .L449: +3166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6838 .loc 1 3166 7 is_stmt 1 view .LVU2396 +3166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6839 .loc 1 3166 30 is_stmt 0 view .LVU2397 + 6840 00c8 D2B2 uxtb r2, r2 + 6841 .LVL452: +3166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6842 .loc 1 3166 28 view .LVU2398 + 6843 00ca 8A62 str r2, [r1, #40] +3169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6844 .loc 1 3169 7 is_stmt 1 view .LVU2399 +3169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6845 .loc 1 3169 24 is_stmt 0 view .LVU2400 + 6846 00cc 4FF0FF33 mov r3, #-1 + 6847 00d0 2365 str r3, [r4, #80] + 6848 00d2 CDE7 b .L439 + 6849 .L440: +3200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6850 .loc 1 3200 7 is_stmt 1 view .LVU2401 +3200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6851 .loc 1 3200 23 is_stmt 0 view .LVU2402 + 6852 00d4 2023 movs r3, #32 + 6853 00d6 84F84130 strb r3, [r4, #65] +3201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6854 .loc 1 3201 7 is_stmt 1 view .LVU2403 +3201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6855 .loc 1 3201 23 is_stmt 0 view .LVU2404 + 6856 00da 0022 movs r2, #0 + 6857 00dc 84F84220 strb r2, [r4, #66] +3204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 293 + + + 6858 .loc 1 3204 7 is_stmt 1 view .LVU2405 +3204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6859 .loc 1 3204 11 is_stmt 0 view .LVU2406 + 6860 00e0 636C ldr r3, [r4, #68] +3204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6861 .loc 1 3204 23 view .LVU2407 + 6862 00e2 43F08003 orr r3, r3, #128 + 6863 00e6 6364 str r3, [r4, #68] +3207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6864 .loc 1 3207 7 is_stmt 1 view .LVU2408 +3207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6865 .loc 1 3207 7 view .LVU2409 + 6866 00e8 84F84020 strb r2, [r4, #64] +3207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6867 .loc 1 3207 7 view .LVU2410 +3209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6868 .loc 1 3209 7 view .LVU2411 +3209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6869 .loc 1 3209 14 is_stmt 0 view .LVU2412 + 6870 00ec 0125 movs r5, #1 + 6871 00ee 10E0 b .L434 + 6872 .LVL453: + 6873 .L450: +3215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6874 .loc 1 3215 7 is_stmt 1 view .LVU2413 + 6875 00f0 0F4B ldr r3, .L451+16 + 6876 00f2 0093 str r3, [sp] + 6877 00f4 0023 movs r3, #0 + 6878 00f6 FAB2 uxtb r2, r7 + 6879 00f8 3146 mov r1, r6 + 6880 00fa 2046 mov r0, r4 + 6881 .LVL454: +3215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6882 .loc 1 3215 7 is_stmt 0 view .LVU2414 + 6883 00fc FFF7FEFF bl I2C_TransferConfig + 6884 .LVL455: +3218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6885 .loc 1 3218 7 is_stmt 1 view .LVU2415 +3218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6886 .loc 1 3218 7 view .LVU2416 + 6887 0100 0023 movs r3, #0 + 6888 0102 84F84030 strb r3, [r4, #64] +3218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6889 .loc 1 3218 7 view .LVU2417 +3227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6890 .loc 1 3227 7 view .LVU2418 + 6891 0106 0121 movs r1, #1 + 6892 0108 2046 mov r0, r4 + 6893 010a FFF7FEFF bl I2C_Enable_IRQ + 6894 .LVL456: +3244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6895 .loc 1 3244 5 view .LVU2419 +3244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6896 .loc 1 3244 12 is_stmt 0 view .LVU2420 + 6897 010e 00E0 b .L434 + 6898 .LVL457: + 6899 .L443: + ARM GAS /tmp/ccSHpINd.s page 294 + + +3248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6900 .loc 1 3248 12 view .LVU2421 + 6901 0110 0225 movs r5, #2 + 6902 .LVL458: + 6903 .L434: +3250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6904 .loc 1 3250 1 view .LVU2422 + 6905 0112 2846 mov r0, r5 + 6906 0114 03B0 add sp, sp, #12 + 6907 .LCFI80: + 6908 .cfi_remember_state + 6909 .cfi_def_cfa_offset 20 + 6910 @ sp needed + 6911 0116 F0BD pop {r4, r5, r6, r7, pc} + 6912 .LVL459: + 6913 .L444: + 6914 .LCFI81: + 6915 .cfi_restore_state +3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 6916 .loc 1 3136 14 view .LVU2423 + 6917 0118 0225 movs r5, #2 + 6918 011a FAE7 b .L434 + 6919 .L445: +3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6920 .loc 1 3140 5 discriminator 1 view .LVU2424 + 6921 011c 0225 movs r5, #2 + 6922 011e F8E7 b .L434 + 6923 .L452: + 6924 .align 2 + 6925 .L451: + 6926 0120 0000FFFF .word -65536 + 6927 0124 00000000 .word I2C_Mem_ISR_DMA + 6928 0128 00000000 .word I2C_DMAMasterReceiveCplt + 6929 012c 00000000 .word I2C_DMAError + 6930 0130 00200080 .word -2147475456 + 6931 .cfi_endproc + 6932 .LFE162: + 6934 .section .text.HAL_I2C_IsDeviceReady,"ax",%progbits + 6935 .align 1 + 6936 .global HAL_I2C_IsDeviceReady + 6937 .syntax unified + 6938 .thumb + 6939 .thumb_func + 6941 HAL_I2C_IsDeviceReady: + 6942 .LVL460: + 6943 .LFB163: +3265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; + 6944 .loc 1 3265 1 is_stmt 1 view -0 + 6945 .cfi_startproc + 6946 @ args = 0, pretend = 0, frame = 8 + 6947 @ frame_needed = 0, uses_anonymous_args = 0 +3265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tickstart; + 6948 .loc 1 3265 1 is_stmt 0 view .LVU2426 + 6949 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 6950 .LCFI82: + 6951 .cfi_def_cfa_offset 28 + 6952 .cfi_offset 4, -28 + ARM GAS /tmp/ccSHpINd.s page 295 + + + 6953 .cfi_offset 5, -24 + 6954 .cfi_offset 6, -20 + 6955 .cfi_offset 7, -16 + 6956 .cfi_offset 8, -12 + 6957 .cfi_offset 9, -8 + 6958 .cfi_offset 14, -4 + 6959 0004 85B0 sub sp, sp, #20 + 6960 .LCFI83: + 6961 .cfi_def_cfa_offset 48 + 6962 0006 1D46 mov r5, r3 +3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6963 .loc 1 3266 3 is_stmt 1 view .LVU2427 +3268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6964 .loc 1 3268 3 view .LVU2428 +3268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6965 .loc 1 3268 17 is_stmt 0 view .LVU2429 + 6966 0008 0023 movs r3, #0 + 6967 .LVL461: +3268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6968 .loc 1 3268 17 view .LVU2430 + 6969 000a 0393 str r3, [sp, #12] +3270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** FlagStatus tmp2; + 6970 .loc 1 3270 3 is_stmt 1 view .LVU2431 +3271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6971 .loc 1 3271 3 view .LVU2432 +3273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6972 .loc 1 3273 3 view .LVU2433 +3273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6973 .loc 1 3273 11 is_stmt 0 view .LVU2434 + 6974 000c 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 6975 0010 DBB2 uxtb r3, r3 +3273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6976 .loc 1 3273 6 view .LVU2435 + 6977 0012 202B cmp r3, #32 + 6978 0014 40F08380 bne .L463 + 6979 0018 0646 mov r6, r0 + 6980 001a 8846 mov r8, r1 + 6981 001c 9146 mov r9, r2 +3275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6982 .loc 1 3275 5 is_stmt 1 view .LVU2436 +3275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6983 .loc 1 3275 9 is_stmt 0 view .LVU2437 + 6984 001e 0368 ldr r3, [r0] + 6985 0020 9B69 ldr r3, [r3, #24] +3275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 6986 .loc 1 3275 8 view .LVU2438 + 6987 0022 13F4004F tst r3, #32768 + 6988 0026 7CD1 bne .L464 +3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6989 .loc 1 3281 5 is_stmt 1 view .LVU2439 +3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6990 .loc 1 3281 5 view .LVU2440 + 6991 0028 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 6992 002c 012B cmp r3, #1 + 6993 002e 7AD0 beq .L465 +3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6994 .loc 1 3281 5 discriminator 2 view .LVU2441 + ARM GAS /tmp/ccSHpINd.s page 296 + + + 6995 0030 0123 movs r3, #1 + 6996 0032 80F84030 strb r3, [r0, #64] +3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 6997 .loc 1 3281 5 discriminator 2 view .LVU2442 +3283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6998 .loc 1 3283 5 view .LVU2443 +3283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6999 .loc 1 3283 17 is_stmt 0 view .LVU2444 + 7000 0036 2423 movs r3, #36 + 7001 0038 80F84130 strb r3, [r0, #65] +3284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7002 .loc 1 3284 5 is_stmt 1 view .LVU2445 +3284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7003 .loc 1 3284 21 is_stmt 0 view .LVU2446 + 7004 003c 0023 movs r3, #0 + 7005 003e 4364 str r3, [r0, #68] + 7006 .LVL462: + 7007 .L462: +3286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7008 .loc 1 3286 5 is_stmt 1 view .LVU2447 +3289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7009 .loc 1 3289 7 view .LVU2448 +3289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7010 .loc 1 3289 29 is_stmt 0 view .LVU2449 + 7011 0040 F368 ldr r3, [r6, #12] + 7012 0042 012B cmp r3, #1 + 7013 0044 10D0 beq .L469 +3289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7014 .loc 1 3289 29 discriminator 2 view .LVU2450 + 7015 0046 C8F30902 ubfx r2, r8, #0, #10 + 7016 004a 3A4B ldr r3, .L472 + 7017 004c 1343 orrs r3, r3, r2 + 7018 .L456: +3289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7019 .loc 1 3289 11 discriminator 4 view .LVU2451 + 7020 004e 3268 ldr r2, [r6] +3289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7021 .loc 1 3289 27 discriminator 4 view .LVU2452 + 7022 0050 5360 str r3, [r2, #4] +3293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7023 .loc 1 3293 7 is_stmt 1 view .LVU2453 +3293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7024 .loc 1 3293 19 is_stmt 0 view .LVU2454 + 7025 0052 FFF7FEFF bl HAL_GetTick + 7026 .LVL463: + 7027 0056 0746 mov r7, r0 + 7028 .LVL464: +3295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + 7029 .loc 1 3295 7 is_stmt 1 view .LVU2455 +3295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + 7030 .loc 1 3295 14 is_stmt 0 view .LVU2456 + 7031 0058 3268 ldr r2, [r6] + 7032 005a 9369 ldr r3, [r2, #24] + 7033 005c C3F3401C ubfx ip, r3, #5, #1 + 7034 .LVL465: +3296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7035 .loc 1 3296 7 is_stmt 1 view .LVU2457 + ARM GAS /tmp/ccSHpINd.s page 297 + + +3296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7036 .loc 1 3296 14 is_stmt 0 view .LVU2458 + 7037 0060 9369 ldr r3, [r2, #24] + 7038 0062 C3F30013 ubfx r3, r3, #4, #1 + 7039 .LVL466: +3298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7040 .loc 1 3298 7 is_stmt 1 view .LVU2459 +3298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7041 .loc 1 3298 13 is_stmt 0 view .LVU2460 + 7042 0066 0BE0 b .L457 + 7043 .LVL467: + 7044 .L469: +3289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7045 .loc 1 3289 29 discriminator 1 view .LVU2461 + 7046 0068 C8F30902 ubfx r2, r8, #0, #10 + 7047 006c 324B ldr r3, .L472+4 + 7048 006e 1343 orrs r3, r3, r2 + 7049 0070 EDE7 b .L456 + 7050 .LVL468: + 7051 .L458: +3317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + 7052 .loc 1 3317 9 is_stmt 1 view .LVU2462 +3317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + 7053 .loc 1 3317 16 is_stmt 0 view .LVU2463 + 7054 0072 3368 ldr r3, [r6] + 7055 0074 9C69 ldr r4, [r3, #24] + 7056 0076 C4F3401C ubfx ip, r4, #5, #1 + 7057 .LVL469: +3318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7058 .loc 1 3318 9 is_stmt 1 view .LVU2464 +3318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7059 .loc 1 3318 16 is_stmt 0 view .LVU2465 + 7060 007a 9B69 ldr r3, [r3, #24] + 7061 007c C3F30013 ubfx r3, r3, #4, #1 + 7062 .LVL470: + 7063 .L457: +3298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7064 .loc 1 3298 30 is_stmt 1 view .LVU2466 + 7065 0080 5CEA030C orrs ip, ip, r3 + 7066 .LVL471: +3298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7067 .loc 1 3298 30 is_stmt 0 view .LVU2467 + 7068 0084 17D1 bne .L470 +3300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7069 .loc 1 3300 9 is_stmt 1 view .LVU2468 +3300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7070 .loc 1 3300 12 is_stmt 0 view .LVU2469 + 7071 0086 B5F1FF3F cmp r5, #-1 + 7072 008a F2D0 beq .L458 +3302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7073 .loc 1 3302 11 is_stmt 1 view .LVU2470 +3302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7074 .loc 1 3302 17 is_stmt 0 view .LVU2471 + 7075 008c FFF7FEFF bl HAL_GetTick + 7076 .LVL472: +3302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7077 .loc 1 3302 31 discriminator 1 view .LVU2472 + ARM GAS /tmp/ccSHpINd.s page 298 + + + 7078 0090 C01B subs r0, r0, r7 +3302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7079 .loc 1 3302 14 discriminator 1 view .LVU2473 + 7080 0092 A842 cmp r0, r5 + 7081 0094 01D8 bhi .L459 +3302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7082 .loc 1 3302 55 discriminator 1 view .LVU2474 + 7083 0096 002D cmp r5, #0 + 7084 0098 EBD1 bne .L458 + 7085 .L459: +3305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7086 .loc 1 3305 13 is_stmt 1 view .LVU2475 +3305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7087 .loc 1 3305 25 is_stmt 0 view .LVU2476 + 7088 009a 2023 movs r3, #32 + 7089 009c 86F84130 strb r3, [r6, #65] +3308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7090 .loc 1 3308 13 is_stmt 1 view .LVU2477 +3308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7091 .loc 1 3308 17 is_stmt 0 view .LVU2478 + 7092 00a0 736C ldr r3, [r6, #68] +3308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7093 .loc 1 3308 29 view .LVU2479 + 7094 00a2 43F02003 orr r3, r3, #32 + 7095 00a6 7364 str r3, [r6, #68] +3311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7096 .loc 1 3311 13 is_stmt 1 view .LVU2480 +3311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7097 .loc 1 3311 13 view .LVU2481 + 7098 00a8 0023 movs r3, #0 + 7099 00aa 86F84030 strb r3, [r6, #64] +3311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7100 .loc 1 3311 13 view .LVU2482 +3313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7101 .loc 1 3313 13 view .LVU2483 +3313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7102 .loc 1 3313 20 is_stmt 0 view .LVU2484 + 7103 00ae 0120 movs r0, #1 + 7104 .LVL473: + 7105 .L454: +3375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7106 .loc 1 3375 1 view .LVU2485 + 7107 00b0 05B0 add sp, sp, #20 + 7108 .LCFI84: + 7109 .cfi_remember_state + 7110 .cfi_def_cfa_offset 28 + 7111 @ sp needed + 7112 00b2 BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} + 7113 .LVL474: + 7114 .L470: + 7115 .LCFI85: + 7116 .cfi_restore_state +3322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7117 .loc 1 3322 7 is_stmt 1 view .LVU2486 +3322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7118 .loc 1 3322 11 is_stmt 0 view .LVU2487 + 7119 00b6 3368 ldr r3, [r6] + ARM GAS /tmp/ccSHpINd.s page 299 + + + 7120 .LVL475: +3322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7121 .loc 1 3322 11 view .LVU2488 + 7122 00b8 9B69 ldr r3, [r3, #24] +3322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7123 .loc 1 3322 10 view .LVU2489 + 7124 00ba 13F0100F tst r3, #16 + 7125 00be 1DD0 beq .L471 +3344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7126 .loc 1 3344 9 is_stmt 1 view .LVU2490 +3344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7127 .loc 1 3344 13 is_stmt 0 view .LVU2491 + 7128 00c0 0097 str r7, [sp] + 7129 00c2 2B46 mov r3, r5 + 7130 00c4 0022 movs r2, #0 + 7131 00c6 2021 movs r1, #32 + 7132 00c8 3046 mov r0, r6 + 7133 00ca FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 7134 .LVL476: +3344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7135 .loc 1 3344 12 discriminator 1 view .LVU2492 + 7136 00ce 70BB cbnz r0, .L467 +3350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7137 .loc 1 3350 9 is_stmt 1 view .LVU2493 + 7138 00d0 3368 ldr r3, [r6] + 7139 00d2 1022 movs r2, #16 + 7140 00d4 DA61 str r2, [r3, #28] +3353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7141 .loc 1 3353 9 view .LVU2494 + 7142 00d6 3368 ldr r3, [r6] + 7143 00d8 2022 movs r2, #32 + 7144 00da DA61 str r2, [r3, #28] +3357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } while (I2C_Trials < Trials); + 7145 .loc 1 3357 7 view .LVU2495 +3357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } while (I2C_Trials < Trials); + 7146 .loc 1 3357 17 is_stmt 0 view .LVU2496 + 7147 00dc 039B ldr r3, [sp, #12] + 7148 00de 0133 adds r3, r3, #1 + 7149 00e0 0393 str r3, [sp, #12] +3358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7150 .loc 1 3358 25 is_stmt 1 view .LVU2497 + 7151 00e2 039B ldr r3, [sp, #12] + 7152 00e4 4B45 cmp r3, r9 + 7153 00e6 ABD3 bcc .L462 +3361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7154 .loc 1 3361 5 view .LVU2498 +3361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7155 .loc 1 3361 17 is_stmt 0 view .LVU2499 + 7156 00e8 86F84120 strb r2, [r6, #65] +3364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7157 .loc 1 3364 5 is_stmt 1 view .LVU2500 +3364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7158 .loc 1 3364 9 is_stmt 0 view .LVU2501 + 7159 00ec 736C ldr r3, [r6, #68] +3364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7160 .loc 1 3364 21 view .LVU2502 + 7161 00ee 1343 orrs r3, r3, r2 + ARM GAS /tmp/ccSHpINd.s page 300 + + + 7162 00f0 7364 str r3, [r6, #68] +3367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7163 .loc 1 3367 5 is_stmt 1 view .LVU2503 +3367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7164 .loc 1 3367 5 view .LVU2504 + 7165 00f2 0023 movs r3, #0 + 7166 00f4 86F84030 strb r3, [r6, #64] +3367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7167 .loc 1 3367 5 view .LVU2505 +3369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7168 .loc 1 3369 5 view .LVU2506 +3369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7169 .loc 1 3369 12 is_stmt 0 view .LVU2507 + 7170 00f8 0120 movs r0, #1 + 7171 00fa D9E7 b .L454 + 7172 .L471: +3325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7173 .loc 1 3325 9 is_stmt 1 view .LVU2508 +3325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7174 .loc 1 3325 13 is_stmt 0 view .LVU2509 + 7175 00fc 0097 str r7, [sp] + 7176 00fe 2B46 mov r3, r5 + 7177 0100 0022 movs r2, #0 + 7178 0102 2021 movs r1, #32 + 7179 0104 3046 mov r0, r6 + 7180 0106 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 7181 .LVL477: +3325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7182 .loc 1 3325 12 discriminator 1 view .LVU2510 + 7183 010a 70B9 cbnz r0, .L466 +3331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7184 .loc 1 3331 9 is_stmt 1 view .LVU2511 + 7185 010c 3268 ldr r2, [r6] + 7186 010e 2023 movs r3, #32 + 7187 0110 D361 str r3, [r2, #28] +3334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7188 .loc 1 3334 9 view .LVU2512 +3334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7189 .loc 1 3334 21 is_stmt 0 view .LVU2513 + 7190 0112 86F84130 strb r3, [r6, #65] +3337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7191 .loc 1 3337 9 is_stmt 1 view .LVU2514 +3337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7192 .loc 1 3337 9 view .LVU2515 + 7193 0116 0023 movs r3, #0 + 7194 0118 86F84030 strb r3, [r6, #64] +3337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7195 .loc 1 3337 9 view .LVU2516 +3339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7196 .loc 1 3339 9 view .LVU2517 +3339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7197 .loc 1 3339 16 is_stmt 0 view .LVU2518 + 7198 011c C8E7 b .L454 + 7199 .LVL478: + 7200 .L463: +3373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7201 .loc 1 3373 12 view .LVU2519 + ARM GAS /tmp/ccSHpINd.s page 301 + + + 7202 011e 0220 movs r0, #2 + 7203 .LVL479: +3373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7204 .loc 1 3373 12 view .LVU2520 + 7205 0120 C6E7 b .L454 + 7206 .LVL480: + 7207 .L464: +3277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7208 .loc 1 3277 14 view .LVU2521 + 7209 0122 0220 movs r0, #2 + 7210 .LVL481: +3277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7211 .loc 1 3277 14 view .LVU2522 + 7212 0124 C4E7 b .L454 + 7213 .LVL482: + 7214 .L465: +3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7215 .loc 1 3281 5 discriminator 1 view .LVU2523 + 7216 0126 0220 movs r0, #2 + 7217 .LVL483: +3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7218 .loc 1 3281 5 discriminator 1 view .LVU2524 + 7219 0128 C2E7 b .L454 + 7220 .LVL484: + 7221 .L466: +3327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7222 .loc 1 3327 18 view .LVU2525 + 7223 012a 0120 movs r0, #1 + 7224 012c C0E7 b .L454 + 7225 .L467: +3346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7226 .loc 1 3346 18 view .LVU2526 + 7227 012e 0120 movs r0, #1 + 7228 0130 BEE7 b .L454 + 7229 .L473: + 7230 0132 00BF .align 2 + 7231 .L472: + 7232 0134 00280002 .word 33564672 + 7233 0138 00200002 .word 33562624 + 7234 .cfi_endproc + 7235 .LFE163: + 7237 .section .text.HAL_I2C_Master_Seq_Transmit_IT,"ax",%progbits + 7238 .align 1 + 7239 .global HAL_I2C_Master_Seq_Transmit_IT + 7240 .syntax unified + 7241 .thumb + 7242 .thumb_func + 7244 HAL_I2C_Master_Seq_Transmit_IT: + 7245 .LVL485: + 7246 .LFB164: +3391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; + 7247 .loc 1 3391 1 is_stmt 1 view -0 + 7248 .cfi_startproc + 7249 @ args = 4, pretend = 0, frame = 0 + 7250 @ frame_needed = 0, uses_anonymous_args = 0 +3391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; + 7251 .loc 1 3391 1 is_stmt 0 view .LVU2528 + ARM GAS /tmp/ccSHpINd.s page 302 + + + 7252 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 7253 .LCFI86: + 7254 .cfi_def_cfa_offset 24 + 7255 .cfi_offset 4, -24 + 7256 .cfi_offset 5, -20 + 7257 .cfi_offset 6, -16 + 7258 .cfi_offset 7, -12 + 7259 .cfi_offset 8, -8 + 7260 .cfi_offset 14, -4 + 7261 0004 82B0 sub sp, sp, #8 + 7262 .LCFI87: + 7263 .cfi_def_cfa_offset 32 + 7264 0006 0446 mov r4, r0 + 7265 0008 089E ldr r6, [sp, #32] +3392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_WRITE; + 7266 .loc 1 3392 3 is_stmt 1 view .LVU2529 +3393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t sizetoxfer = 0U; + 7267 .loc 1 3393 3 view .LVU2530 + 7268 .LVL486: +3394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7269 .loc 1 3394 3 view .LVU2531 +3397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7270 .loc 1 3397 3 view .LVU2532 +3399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7271 .loc 1 3399 3 view .LVU2533 +3399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7272 .loc 1 3399 11 is_stmt 0 view .LVU2534 + 7273 000a 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 7274 .LVL487: +3399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7275 .loc 1 3399 11 view .LVU2535 + 7276 000e C0B2 uxtb r0, r0 +3399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7277 .loc 1 3399 6 view .LVU2536 + 7278 0010 2028 cmp r0, #32 + 7279 0012 73D1 bne .L483 + 7280 0014 0D46 mov r5, r1 +3402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7281 .loc 1 3402 5 is_stmt 1 view .LVU2537 +3402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7282 .loc 1 3402 5 view .LVU2538 + 7283 0016 94F84010 ldrb r1, [r4, #64] @ zero_extendqisi2 + 7284 .LVL488: +3402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7285 .loc 1 3402 5 is_stmt 0 view .LVU2539 + 7286 001a 0129 cmp r1, #1 + 7287 001c 70D0 beq .L484 +3402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7288 .loc 1 3402 5 is_stmt 1 discriminator 2 view .LVU2540 + 7289 001e 0121 movs r1, #1 + 7290 0020 84F84010 strb r1, [r4, #64] +3402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7291 .loc 1 3402 5 discriminator 2 view .LVU2541 +3404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 7292 .loc 1 3404 5 view .LVU2542 +3404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 7293 .loc 1 3404 21 is_stmt 0 view .LVU2543 + ARM GAS /tmp/ccSHpINd.s page 303 + + + 7294 0024 2121 movs r1, #33 + 7295 0026 84F84110 strb r1, [r4, #65] +3405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7296 .loc 1 3405 5 is_stmt 1 view .LVU2544 +3405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7297 .loc 1 3405 21 is_stmt 0 view .LVU2545 + 7298 002a 1021 movs r1, #16 + 7299 002c 84F84210 strb r1, [r4, #66] +3406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7300 .loc 1 3406 5 is_stmt 1 view .LVU2546 +3406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7301 .loc 1 3406 21 is_stmt 0 view .LVU2547 + 7302 0030 0021 movs r1, #0 + 7303 0032 6164 str r1, [r4, #68] +3409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 7304 .loc 1 3409 5 is_stmt 1 view .LVU2548 +3409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 7305 .loc 1 3409 23 is_stmt 0 view .LVU2549 + 7306 0034 6262 str r2, [r4, #36] +3410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7307 .loc 1 3410 5 is_stmt 1 view .LVU2550 +3410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7308 .loc 1 3410 23 is_stmt 0 view .LVU2551 + 7309 0036 6385 strh r3, [r4, #42] @ movhi +3411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 7310 .loc 1 3411 5 is_stmt 1 view .LVU2552 +3411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 7311 .loc 1 3411 23 is_stmt 0 view .LVU2553 + 7312 0038 E662 str r6, [r4, #44] +3412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7313 .loc 1 3412 5 is_stmt 1 view .LVU2554 +3412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7314 .loc 1 3412 23 is_stmt 0 view .LVU2555 + 7315 003a 324B ldr r3, .L490 + 7316 .LVL489: +3412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7317 .loc 1 3412 23 view .LVU2556 + 7318 003c 6363 str r3, [r4, #52] +3415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7319 .loc 1 3415 5 is_stmt 1 view .LVU2557 +3415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7320 .loc 1 3415 13 is_stmt 0 view .LVU2558 + 7321 003e 638D ldrh r3, [r4, #42] + 7322 0040 9BB2 uxth r3, r3 +3415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7323 .loc 1 3415 8 view .LVU2559 + 7324 0042 FF2B cmp r3, #255 + 7325 0044 1BD9 bls .L476 +3417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 7326 .loc 1 3417 7 is_stmt 1 view .LVU2560 +3417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 7327 .loc 1 3417 22 is_stmt 0 view .LVU2561 + 7328 0046 FF23 movs r3, #255 + 7329 0048 2385 strh r3, [r4, #40] @ movhi +3418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7330 .loc 1 3418 7 is_stmt 1 view .LVU2562 + 7331 .LVL490: + ARM GAS /tmp/ccSHpINd.s page 304 + + +3418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7332 .loc 1 3418 16 is_stmt 0 view .LVU2563 + 7333 004a 4FF08077 mov r7, #16777216 + 7334 .LVL491: + 7335 .L477: +3426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + 7336 .loc 1 3426 5 is_stmt 1 view .LVU2564 +3426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + 7337 .loc 1 3426 14 is_stmt 0 view .LVU2565 + 7338 004e 238D ldrh r3, [r4, #40] +3426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + 7339 .loc 1 3426 8 view .LVU2566 + 7340 0050 CBB1 cbz r3, .L485 +3426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + 7341 .loc 1 3426 31 discriminator 1 view .LVU2567 + 7342 0052 B6F1007F cmp r6, #33554432 + 7343 0056 18BF it ne + 7344 0058 002E cmpne r6, #0 + 7345 005a 3FD1 bne .L486 +3431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7346 .loc 1 3431 7 is_stmt 1 view .LVU2568 +3431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7347 .loc 1 3431 11 is_stmt 0 view .LVU2569 + 7348 005c 2368 ldr r3, [r4] +3431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7349 .loc 1 3431 30 view .LVU2570 + 7350 005e 1278 ldrb r2, [r2] @ zero_extendqisi2 + 7351 .LVL492: +3431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7352 .loc 1 3431 28 view .LVU2571 + 7353 0060 9A62 str r2, [r3, #40] + 7354 .LVL493: +3434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7355 .loc 1 3434 7 is_stmt 1 view .LVU2572 +3434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7356 .loc 1 3434 11 is_stmt 0 view .LVU2573 + 7357 0062 636A ldr r3, [r4, #36] +3434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7358 .loc 1 3434 21 view .LVU2574 + 7359 0064 0133 adds r3, r3, #1 + 7360 0066 6362 str r3, [r4, #36] +3436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 7361 .loc 1 3436 7 is_stmt 1 view .LVU2575 +3436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 7362 .loc 1 3436 24 is_stmt 0 view .LVU2576 + 7363 0068 B4F82880 ldrh r8, [r4, #40] + 7364 .LVL494: +3437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 7365 .loc 1 3437 7 is_stmt 1 view .LVU2577 +3437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 7366 .loc 1 3437 11 is_stmt 0 view .LVU2578 + 7367 006c 638D ldrh r3, [r4, #42] + 7368 006e 9BB2 uxth r3, r3 +3437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 7369 .loc 1 3437 22 view .LVU2579 + 7370 0070 013B subs r3, r3, #1 + 7371 0072 9BB2 uxth r3, r3 + ARM GAS /tmp/ccSHpINd.s page 305 + + + 7372 0074 6385 strh r3, [r4, #42] @ movhi +3438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7373 .loc 1 3438 7 is_stmt 1 view .LVU2580 +3438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7374 .loc 1 3438 21 is_stmt 0 view .LVU2581 + 7375 0076 08F1FF33 add r3, r8, #-1 + 7376 007a 2385 strh r3, [r4, #40] @ movhi + 7377 007c 05E0 b .L478 + 7378 .LVL495: + 7379 .L476: +3422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7380 .loc 1 3422 7 is_stmt 1 view .LVU2582 +3422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7381 .loc 1 3422 28 is_stmt 0 view .LVU2583 + 7382 007e 638D ldrh r3, [r4, #42] +3422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7383 .loc 1 3422 22 view .LVU2584 + 7384 0080 2385 strh r3, [r4, #40] @ movhi +3423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7385 .loc 1 3423 7 is_stmt 1 view .LVU2585 +3423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7386 .loc 1 3423 16 is_stmt 0 view .LVU2586 + 7387 0082 E76A ldr r7, [r4, #44] + 7388 .LVL496: +3423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7389 .loc 1 3423 16 view .LVU2587 + 7390 0084 E3E7 b .L477 + 7391 .L485: +3394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7392 .loc 1 3394 12 view .LVU2588 + 7393 0086 4FF00008 mov r8, #0 + 7394 .LVL497: + 7395 .L478: +3444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 7396 .loc 1 3444 5 is_stmt 1 view .LVU2589 +3444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 7397 .loc 1 3444 14 is_stmt 0 view .LVU2590 + 7398 008a 236B ldr r3, [r4, #48] +3444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 7399 .loc 1 3444 8 view .LVU2591 + 7400 008c 112B cmp r3, #17 + 7401 008e 04D1 bne .L479 +3444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 7402 .loc 1 3444 59 discriminator 1 view .LVU2592 + 7403 0090 B6F52A4F cmp r6, #43520 + 7404 0094 18BF it ne + 7405 0096 AA2E cmpne r6, #170 + 7406 0098 23D1 bne .L487 + 7407 .L479: +3452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7408 .loc 1 3452 7 is_stmt 1 view .LVU2593 + 7409 009a 2046 mov r0, r4 + 7410 009c FFF7FEFF bl I2C_ConvertOtherXferOptions + 7411 .LVL498: +3455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7412 .loc 1 3455 7 view .LVU2594 +3455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 306 + + + 7413 .loc 1 3455 15 is_stmt 0 view .LVU2595 + 7414 00a0 638D ldrh r3, [r4, #42] + 7415 00a2 9BB2 uxth r3, r3 +3455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7416 .loc 1 3455 10 view .LVU2596 + 7417 00a4 FF2B cmp r3, #255 + 7418 00a6 1ED8 bhi .L488 +3457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7419 .loc 1 3457 9 is_stmt 1 view .LVU2597 +3457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7420 .loc 1 3457 18 is_stmt 0 view .LVU2598 + 7421 00a8 E76A ldr r7, [r4, #44] + 7422 .LVL499: +3393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t sizetoxfer = 0U; + 7423 .loc 1 3393 12 view .LVU2599 + 7424 00aa 174B ldr r3, .L490+4 + 7425 .L480: + 7426 .LVL500: +3462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7427 .loc 1 3462 5 is_stmt 1 view .LVU2600 +3462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7428 .loc 1 3462 8 is_stmt 0 view .LVU2601 + 7429 00ac B6F1007F cmp r6, #33554432 + 7430 00b0 18BF it ne + 7431 00b2 002E cmpne r6, #0 + 7432 00b4 19D1 bne .L481 +3464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7433 .loc 1 3464 7 is_stmt 1 view .LVU2602 + 7434 00b6 0093 str r3, [sp] + 7435 00b8 3B46 mov r3, r7 + 7436 .LVL501: +3464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7437 .loc 1 3464 7 is_stmt 0 view .LVU2603 + 7438 00ba 5FFA88F2 uxtb r2, r8 + 7439 00be 2946 mov r1, r5 + 7440 00c0 2046 mov r0, r4 + 7441 00c2 FFF7FEFF bl I2C_TransferConfig + 7442 .LVL502: + 7443 .L482: +3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7444 .loc 1 3472 5 is_stmt 1 view .LVU2604 +3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7445 .loc 1 3472 5 view .LVU2605 + 7446 00c6 0025 movs r5, #0 + 7447 .LVL503: +3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7448 .loc 1 3472 5 is_stmt 0 view .LVU2606 + 7449 00c8 84F84050 strb r5, [r4, #64] +3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7450 .loc 1 3472 5 is_stmt 1 view .LVU2607 +3481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7451 .loc 1 3481 5 view .LVU2608 + 7452 00cc 0121 movs r1, #1 + 7453 00ce 2046 mov r0, r4 + 7454 00d0 FFF7FEFF bl I2C_Enable_IRQ + 7455 .LVL504: +3483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + ARM GAS /tmp/ccSHpINd.s page 307 + + + 7456 .loc 1 3483 5 view .LVU2609 +3483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7457 .loc 1 3483 12 is_stmt 0 view .LVU2610 + 7458 00d4 2846 mov r0, r5 + 7459 .LVL505: + 7460 .L475: +3489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7461 .loc 1 3489 1 view .LVU2611 + 7462 00d6 02B0 add sp, sp, #8 + 7463 .LCFI88: + 7464 .cfi_remember_state + 7465 .cfi_def_cfa_offset 24 + 7466 @ sp needed + 7467 00d8 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 7468 .LVL506: + 7469 .L486: + 7470 .LCFI89: + 7471 .cfi_restore_state +3394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7472 .loc 1 3394 12 view .LVU2612 + 7473 00dc 4FF00008 mov r8, #0 + 7474 00e0 D3E7 b .L478 + 7475 .LVL507: + 7476 .L487: +3447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7477 .loc 1 3447 19 view .LVU2613 + 7478 00e2 0023 movs r3, #0 + 7479 00e4 E2E7 b .L480 + 7480 .L488: +3393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t sizetoxfer = 0U; + 7481 .loc 1 3393 12 view .LVU2614 + 7482 00e6 084B ldr r3, .L490+4 + 7483 00e8 E0E7 b .L480 + 7484 .LVL508: + 7485 .L481: +3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7486 .loc 1 3468 7 is_stmt 1 view .LVU2615 + 7487 00ea 0093 str r3, [sp] + 7488 00ec 3B46 mov r3, r7 + 7489 .LVL509: +3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7490 .loc 1 3468 7 is_stmt 0 view .LVU2616 + 7491 00ee 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 7492 00f2 2946 mov r1, r5 + 7493 00f4 2046 mov r0, r4 + 7494 00f6 FFF7FEFF bl I2C_TransferConfig + 7495 .LVL510: +3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7496 .loc 1 3468 7 view .LVU2617 + 7497 00fa E4E7 b .L482 + 7498 .LVL511: + 7499 .L483: +3487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7500 .loc 1 3487 12 view .LVU2618 + 7501 00fc 0220 movs r0, #2 + 7502 00fe EAE7 b .L475 + 7503 .LVL512: + ARM GAS /tmp/ccSHpINd.s page 308 + + + 7504 .L484: +3402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7505 .loc 1 3402 5 discriminator 1 view .LVU2619 + 7506 0100 0220 movs r0, #2 + 7507 0102 E8E7 b .L475 + 7508 .L491: + 7509 .align 2 + 7510 .L490: + 7511 0104 00000000 .word I2C_Master_ISR_IT + 7512 0108 00200080 .word -2147475456 + 7513 .cfi_endproc + 7514 .LFE164: + 7516 .section .text.HAL_I2C_Master_Seq_Transmit_DMA,"ax",%progbits + 7517 .align 1 + 7518 .global HAL_I2C_Master_Seq_Transmit_DMA + 7519 .syntax unified + 7520 .thumb + 7521 .thumb_func + 7523 HAL_I2C_Master_Seq_Transmit_DMA: + 7524 .LVL513: + 7525 .LFB165: +3505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; + 7526 .loc 1 3505 1 is_stmt 1 view -0 + 7527 .cfi_startproc + 7528 @ args = 4, pretend = 0, frame = 0 + 7529 @ frame_needed = 0, uses_anonymous_args = 0 +3505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; + 7530 .loc 1 3505 1 is_stmt 0 view .LVU2621 + 7531 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 7532 .LCFI90: + 7533 .cfi_def_cfa_offset 28 + 7534 .cfi_offset 4, -28 + 7535 .cfi_offset 5, -24 + 7536 .cfi_offset 6, -20 + 7537 .cfi_offset 7, -16 + 7538 .cfi_offset 8, -12 + 7539 .cfi_offset 9, -8 + 7540 .cfi_offset 14, -4 + 7541 0004 83B0 sub sp, sp, #12 + 7542 .LCFI91: + 7543 .cfi_def_cfa_offset 40 + 7544 0006 0446 mov r4, r0 + 7545 0008 0A9E ldr r6, [sp, #40] +3506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_WRITE; + 7546 .loc 1 3506 3 is_stmt 1 view .LVU2622 +3507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 7547 .loc 1 3507 3 view .LVU2623 + 7548 .LVL514: +3508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t sizetoxfer = 0U; + 7549 .loc 1 3508 3 view .LVU2624 +3509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7550 .loc 1 3509 3 view .LVU2625 +3512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7551 .loc 1 3512 3 view .LVU2626 +3514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7552 .loc 1 3514 3 view .LVU2627 +3514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 309 + + + 7553 .loc 1 3514 11 is_stmt 0 view .LVU2628 + 7554 000a 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 7555 .LVL515: +3514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7556 .loc 1 3514 11 view .LVU2629 + 7557 000e C0B2 uxtb r0, r0 +3514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7558 .loc 1 3514 6 view .LVU2630 + 7559 0010 2028 cmp r0, #32 + 7560 0012 40F0D780 bne .L508 + 7561 0016 0D46 mov r5, r1 +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7562 .loc 1 3517 5 is_stmt 1 view .LVU2631 +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7563 .loc 1 3517 5 view .LVU2632 + 7564 0018 94F84010 ldrb r1, [r4, #64] @ zero_extendqisi2 + 7565 .LVL516: +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7566 .loc 1 3517 5 is_stmt 0 view .LVU2633 + 7567 001c 0129 cmp r1, #1 + 7568 001e 00F0D580 beq .L509 +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7569 .loc 1 3517 5 is_stmt 1 discriminator 2 view .LVU2634 + 7570 0022 0121 movs r1, #1 + 7571 0024 84F84010 strb r1, [r4, #64] +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7572 .loc 1 3517 5 discriminator 2 view .LVU2635 +3519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 7573 .loc 1 3519 5 view .LVU2636 +3519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 7574 .loc 1 3519 21 is_stmt 0 view .LVU2637 + 7575 0028 2121 movs r1, #33 + 7576 002a 84F84110 strb r1, [r4, #65] +3520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7577 .loc 1 3520 5 is_stmt 1 view .LVU2638 +3520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7578 .loc 1 3520 21 is_stmt 0 view .LVU2639 + 7579 002e 1021 movs r1, #16 + 7580 0030 84F84210 strb r1, [r4, #66] +3521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7581 .loc 1 3521 5 is_stmt 1 view .LVU2640 +3521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7582 .loc 1 3521 21 is_stmt 0 view .LVU2641 + 7583 0034 0021 movs r1, #0 + 7584 0036 6164 str r1, [r4, #68] +3524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 7585 .loc 1 3524 5 is_stmt 1 view .LVU2642 +3524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 7586 .loc 1 3524 23 is_stmt 0 view .LVU2643 + 7587 0038 6262 str r2, [r4, #36] +3525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7588 .loc 1 3525 5 is_stmt 1 view .LVU2644 +3525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7589 .loc 1 3525 23 is_stmt 0 view .LVU2645 + 7590 003a 6385 strh r3, [r4, #42] @ movhi +3526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 7591 .loc 1 3526 5 is_stmt 1 view .LVU2646 + ARM GAS /tmp/ccSHpINd.s page 310 + + +3526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 7592 .loc 1 3526 23 is_stmt 0 view .LVU2647 + 7593 003c E662 str r6, [r4, #44] +3527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7594 .loc 1 3527 5 is_stmt 1 view .LVU2648 +3527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7595 .loc 1 3527 23 is_stmt 0 view .LVU2649 + 7596 003e 644B ldr r3, .L516 + 7597 .LVL517: +3527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7598 .loc 1 3527 23 view .LVU2650 + 7599 0040 6363 str r3, [r4, #52] +3530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7600 .loc 1 3530 5 is_stmt 1 view .LVU2651 +3530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7601 .loc 1 3530 13 is_stmt 0 view .LVU2652 + 7602 0042 638D ldrh r3, [r4, #42] + 7603 0044 9BB2 uxth r3, r3 +3530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7604 .loc 1 3530 8 view .LVU2653 + 7605 0046 FF2B cmp r3, #255 + 7606 0048 1BD9 bls .L494 +3532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 7607 .loc 1 3532 7 is_stmt 1 view .LVU2654 +3532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 7608 .loc 1 3532 22 is_stmt 0 view .LVU2655 + 7609 004a FF23 movs r3, #255 + 7610 004c 2385 strh r3, [r4, #40] @ movhi +3533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7611 .loc 1 3533 7 is_stmt 1 view .LVU2656 + 7612 .LVL518: +3533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7613 .loc 1 3533 16 is_stmt 0 view .LVU2657 + 7614 004e 4FF08077 mov r7, #16777216 + 7615 .LVL519: + 7616 .L495: +3541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + 7617 .loc 1 3541 5 is_stmt 1 view .LVU2658 +3541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + 7618 .loc 1 3541 14 is_stmt 0 view .LVU2659 + 7619 0052 238D ldrh r3, [r4, #40] +3541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + 7620 .loc 1 3541 8 view .LVU2660 + 7621 0054 CBB1 cbz r3, .L510 +3541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + 7622 .loc 1 3541 31 discriminator 1 view .LVU2661 + 7623 0056 B6F1007F cmp r6, #33554432 + 7624 005a 18BF it ne + 7625 005c 002E cmpne r6, #0 + 7626 005e 29D1 bne .L511 +3546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7627 .loc 1 3546 7 is_stmt 1 view .LVU2662 +3546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7628 .loc 1 3546 11 is_stmt 0 view .LVU2663 + 7629 0060 2368 ldr r3, [r4] +3546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7630 .loc 1 3546 30 view .LVU2664 + ARM GAS /tmp/ccSHpINd.s page 311 + + + 7631 0062 1278 ldrb r2, [r2] @ zero_extendqisi2 + 7632 .LVL520: +3546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7633 .loc 1 3546 28 view .LVU2665 + 7634 0064 9A62 str r2, [r3, #40] + 7635 .LVL521: +3549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7636 .loc 1 3549 7 is_stmt 1 view .LVU2666 +3549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7637 .loc 1 3549 11 is_stmt 0 view .LVU2667 + 7638 0066 636A ldr r3, [r4, #36] +3549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7639 .loc 1 3549 21 view .LVU2668 + 7640 0068 0133 adds r3, r3, #1 + 7641 006a 6362 str r3, [r4, #36] +3551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 7642 .loc 1 3551 7 is_stmt 1 view .LVU2669 +3551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 7643 .loc 1 3551 24 is_stmt 0 view .LVU2670 + 7644 006c B4F82880 ldrh r8, [r4, #40] + 7645 .LVL522: +3552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 7646 .loc 1 3552 7 is_stmt 1 view .LVU2671 +3552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 7647 .loc 1 3552 11 is_stmt 0 view .LVU2672 + 7648 0070 638D ldrh r3, [r4, #42] + 7649 0072 9BB2 uxth r3, r3 +3552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 7650 .loc 1 3552 22 view .LVU2673 + 7651 0074 013B subs r3, r3, #1 + 7652 0076 9BB2 uxth r3, r3 + 7653 0078 6385 strh r3, [r4, #42] @ movhi +3553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7654 .loc 1 3553 7 is_stmt 1 view .LVU2674 +3553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7655 .loc 1 3553 21 is_stmt 0 view .LVU2675 + 7656 007a 08F1FF33 add r3, r8, #-1 + 7657 007e 2385 strh r3, [r4, #40] @ movhi + 7658 0080 05E0 b .L496 + 7659 .LVL523: + 7660 .L494: +3537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7661 .loc 1 3537 7 is_stmt 1 view .LVU2676 +3537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7662 .loc 1 3537 28 is_stmt 0 view .LVU2677 + 7663 0082 638D ldrh r3, [r4, #42] +3537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7664 .loc 1 3537 22 view .LVU2678 + 7665 0084 2385 strh r3, [r4, #40] @ movhi +3538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7666 .loc 1 3538 7 is_stmt 1 view .LVU2679 +3538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7667 .loc 1 3538 16 is_stmt 0 view .LVU2680 + 7668 0086 E76A ldr r7, [r4, #44] + 7669 .LVL524: +3538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7670 .loc 1 3538 16 view .LVU2681 + ARM GAS /tmp/ccSHpINd.s page 312 + + + 7671 0088 E3E7 b .L495 + 7672 .L510: +3509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7673 .loc 1 3509 12 view .LVU2682 + 7674 008a 4FF00008 mov r8, #0 + 7675 .LVL525: + 7676 .L496: +3559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 7677 .loc 1 3559 5 is_stmt 1 view .LVU2683 +3559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 7678 .loc 1 3559 14 is_stmt 0 view .LVU2684 + 7679 008e 236B ldr r3, [r4, #48] +3559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 7680 .loc 1 3559 8 view .LVU2685 + 7681 0090 112B cmp r3, #17 + 7682 0092 04D1 bne .L497 +3559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 7683 .loc 1 3559 59 discriminator 1 view .LVU2686 + 7684 0094 B6F52A4F cmp r6, #43520 + 7685 0098 18BF it ne + 7686 009a AA2E cmpne r6, #170 + 7687 009c 0DD1 bne .L512 + 7688 .L497: +3567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7689 .loc 1 3567 7 is_stmt 1 view .LVU2687 + 7690 009e 2046 mov r0, r4 + 7691 00a0 FFF7FEFF bl I2C_ConvertOtherXferOptions + 7692 .LVL526: +3570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7693 .loc 1 3570 7 view .LVU2688 +3570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7694 .loc 1 3570 15 is_stmt 0 view .LVU2689 + 7695 00a4 638D ldrh r3, [r4, #42] + 7696 00a6 9BB2 uxth r3, r3 +3570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7697 .loc 1 3570 10 view .LVU2690 + 7698 00a8 FF2B cmp r3, #255 + 7699 00aa 09D8 bhi .L513 +3572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7700 .loc 1 3572 9 is_stmt 1 view .LVU2691 +3572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7701 .loc 1 3572 18 is_stmt 0 view .LVU2692 + 7702 00ac E76A ldr r7, [r4, #44] + 7703 .LVL527: +3507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 7704 .loc 1 3507 12 view .LVU2693 + 7705 00ae DFF83091 ldr r9, .L516+16 + 7706 00b2 07E0 b .L498 + 7707 .LVL528: + 7708 .L511: +3509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7709 .loc 1 3509 12 view .LVU2694 + 7710 00b4 4FF00008 mov r8, #0 + 7711 00b8 E9E7 b .L496 + 7712 .LVL529: + 7713 .L512: +3562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + ARM GAS /tmp/ccSHpINd.s page 313 + + + 7714 .loc 1 3562 19 view .LVU2695 + 7715 00ba 4FF00009 mov r9, #0 + 7716 00be 01E0 b .L498 + 7717 .L513: +3507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 7718 .loc 1 3507 12 view .LVU2696 + 7719 00c0 DFF81C91 ldr r9, .L516+16 + 7720 .L498: + 7721 .LVL530: +3576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7722 .loc 1 3576 5 is_stmt 1 view .LVU2697 +3576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7723 .loc 1 3576 13 is_stmt 0 view .LVU2698 + 7724 00c4 228D ldrh r2, [r4, #40] +3576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7725 .loc 1 3576 8 view .LVU2699 + 7726 00c6 002A cmp r2, #0 + 7727 00c8 5AD0 beq .L499 +3578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7728 .loc 1 3578 7 is_stmt 1 view .LVU2700 +3578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7729 .loc 1 3578 15 is_stmt 0 view .LVU2701 + 7730 00ca A36B ldr r3, [r4, #56] +3578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7731 .loc 1 3578 10 view .LVU2702 + 7732 00cc FBB1 cbz r3, .L500 +3581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7733 .loc 1 3581 9 is_stmt 1 view .LVU2703 +3581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7734 .loc 1 3581 40 is_stmt 0 view .LVU2704 + 7735 00ce 414A ldr r2, .L516+4 + 7736 00d0 DA63 str r2, [r3, #60] +3584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7737 .loc 1 3584 9 is_stmt 1 view .LVU2705 +3584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7738 .loc 1 3584 13 is_stmt 0 view .LVU2706 + 7739 00d2 A36B ldr r3, [r4, #56] +3584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7740 .loc 1 3584 41 view .LVU2707 + 7741 00d4 404A ldr r2, .L516+8 + 7742 00d6 DA64 str r2, [r3, #76] +3587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 7743 .loc 1 3587 9 is_stmt 1 view .LVU2708 +3587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 7744 .loc 1 3587 13 is_stmt 0 view .LVU2709 + 7745 00d8 A26B ldr r2, [r4, #56] +3587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 7746 .loc 1 3587 44 view .LVU2710 + 7747 00da 0023 movs r3, #0 + 7748 00dc 1364 str r3, [r2, #64] +3588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7749 .loc 1 3588 9 is_stmt 1 view .LVU2711 +3588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7750 .loc 1 3588 13 is_stmt 0 view .LVU2712 + 7751 00de A26B ldr r2, [r4, #56] +3588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7752 .loc 1 3588 41 view .LVU2713 + ARM GAS /tmp/ccSHpINd.s page 314 + + + 7753 00e0 1365 str r3, [r2, #80] +3591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + 7754 .loc 1 3591 9 is_stmt 1 view .LVU2714 +3592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7755 .loc 1 3592 57 is_stmt 0 view .LVU2715 + 7756 00e2 2268 ldr r2, [r4] +3591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + 7757 .loc 1 3591 25 view .LVU2716 + 7758 00e4 238D ldrh r3, [r4, #40] + 7759 00e6 2832 adds r2, r2, #40 + 7760 00e8 616A ldr r1, [r4, #36] + 7761 00ea A06B ldr r0, [r4, #56] + 7762 00ec FFF7FEFF bl HAL_DMA_Start_IT + 7763 .LVL531: +3609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7764 .loc 1 3609 7 is_stmt 1 view .LVU2717 +3609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7765 .loc 1 3609 10 is_stmt 0 view .LVU2718 + 7766 00f0 D8B1 cbz r0, .L501 +3639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7767 .loc 1 3639 9 is_stmt 1 view .LVU2719 +3639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7768 .loc 1 3639 25 is_stmt 0 view .LVU2720 + 7769 00f2 2023 movs r3, #32 + 7770 00f4 84F84130 strb r3, [r4, #65] +3640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7771 .loc 1 3640 9 is_stmt 1 view .LVU2721 +3640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7772 .loc 1 3640 25 is_stmt 0 view .LVU2722 + 7773 00f8 0022 movs r2, #0 + 7774 00fa 84F84220 strb r2, [r4, #66] +3643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7775 .loc 1 3643 9 is_stmt 1 view .LVU2723 +3643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7776 .loc 1 3643 13 is_stmt 0 view .LVU2724 + 7777 00fe 636C ldr r3, [r4, #68] +3643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7778 .loc 1 3643 25 view .LVU2725 + 7779 0100 43F01003 orr r3, r3, #16 + 7780 0104 6364 str r3, [r4, #68] +3646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7781 .loc 1 3646 9 is_stmt 1 view .LVU2726 +3646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7782 .loc 1 3646 9 view .LVU2727 + 7783 0106 84F84020 strb r2, [r4, #64] +3646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7784 .loc 1 3646 9 view .LVU2728 +3648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7785 .loc 1 3648 9 view .LVU2729 +3648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7786 .loc 1 3648 16 is_stmt 0 view .LVU2730 + 7787 010a 0120 movs r0, #1 + 7788 .LVL532: +3648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7789 .loc 1 3648 16 view .LVU2731 + 7790 010c 5BE0 b .L493 + 7791 .LVL533: + ARM GAS /tmp/ccSHpINd.s page 315 + + + 7792 .L500: +3597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7793 .loc 1 3597 9 is_stmt 1 view .LVU2732 +3597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7794 .loc 1 3597 25 is_stmt 0 view .LVU2733 + 7795 010e 2023 movs r3, #32 + 7796 0110 84F84130 strb r3, [r4, #65] +3598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7797 .loc 1 3598 9 is_stmt 1 view .LVU2734 +3598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7798 .loc 1 3598 25 is_stmt 0 view .LVU2735 + 7799 0114 0022 movs r2, #0 + 7800 0116 84F84220 strb r2, [r4, #66] +3601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7801 .loc 1 3601 9 is_stmt 1 view .LVU2736 +3601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7802 .loc 1 3601 13 is_stmt 0 view .LVU2737 + 7803 011a 636C ldr r3, [r4, #68] +3601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7804 .loc 1 3601 25 view .LVU2738 + 7805 011c 43F08003 orr r3, r3, #128 + 7806 0120 6364 str r3, [r4, #68] +3604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7807 .loc 1 3604 9 is_stmt 1 view .LVU2739 +3604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7808 .loc 1 3604 9 view .LVU2740 + 7809 0122 84F84020 strb r2, [r4, #64] +3604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7810 .loc 1 3604 9 view .LVU2741 +3606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7811 .loc 1 3606 9 view .LVU2742 +3606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7812 .loc 1 3606 16 is_stmt 0 view .LVU2743 + 7813 0126 0120 movs r0, #1 + 7814 0128 4DE0 b .L493 + 7815 .LVL534: + 7816 .L501: +3612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7817 .loc 1 3612 9 is_stmt 1 view .LVU2744 +3612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7818 .loc 1 3612 12 is_stmt 0 view .LVU2745 + 7819 012a B6F1007F cmp r6, #33554432 + 7820 012e 18BF it ne + 7821 0130 002E cmpne r6, #0 + 7822 0132 1BD1 bne .L503 +3614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7823 .loc 1 3614 11 is_stmt 1 view .LVU2746 + 7824 0134 CDF80090 str r9, [sp] + 7825 0138 3B46 mov r3, r7 + 7826 013a 5FFA88F2 uxtb r2, r8 + 7827 013e 2946 mov r1, r5 + 7828 0140 2046 mov r0, r4 + 7829 .LVL535: +3614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7830 .loc 1 3614 11 is_stmt 0 view .LVU2747 + 7831 0142 FFF7FEFF bl I2C_TransferConfig + 7832 .LVL536: + ARM GAS /tmp/ccSHpINd.s page 316 + + + 7833 .L504: +3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7834 .loc 1 3622 9 is_stmt 1 view .LVU2748 +3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7835 .loc 1 3622 13 is_stmt 0 view .LVU2749 + 7836 0146 638D ldrh r3, [r4, #42] + 7837 0148 9BB2 uxth r3, r3 +3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7838 .loc 1 3622 32 view .LVU2750 + 7839 014a 228D ldrh r2, [r4, #40] +3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7840 .loc 1 3622 25 view .LVU2751 + 7841 014c 9B1A subs r3, r3, r2 + 7842 014e 9BB2 uxth r3, r3 + 7843 0150 6385 strh r3, [r4, #42] @ movhi +3625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7844 .loc 1 3625 9 is_stmt 1 view .LVU2752 +3625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7845 .loc 1 3625 9 view .LVU2753 + 7846 0152 0023 movs r3, #0 + 7847 0154 84F84030 strb r3, [r4, #64] +3625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7848 .loc 1 3625 9 view .LVU2754 +3631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7849 .loc 1 3631 9 view .LVU2755 + 7850 0158 1021 movs r1, #16 + 7851 015a 2046 mov r0, r4 + 7852 015c FFF7FEFF bl I2C_Enable_IRQ + 7853 .LVL537: +3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7854 .loc 1 3634 9 view .LVU2756 +3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7855 .loc 1 3634 13 is_stmt 0 view .LVU2757 + 7856 0160 2268 ldr r2, [r4] +3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7857 .loc 1 3634 23 view .LVU2758 + 7858 0162 1368 ldr r3, [r2] +3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7859 .loc 1 3634 29 view .LVU2759 + 7860 0164 43F48043 orr r3, r3, #16384 + 7861 0168 1360 str r3, [r2] + 7862 016a 20E0 b .L505 + 7863 .LVL538: + 7864 .L503: +3618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7865 .loc 1 3618 11 is_stmt 1 view .LVU2760 + 7866 016c CDF80090 str r9, [sp] + 7867 0170 3B46 mov r3, r7 + 7868 0172 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 7869 0176 2946 mov r1, r5 + 7870 0178 2046 mov r0, r4 + 7871 .LVL539: +3618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7872 .loc 1 3618 11 is_stmt 0 view .LVU2761 + 7873 017a FFF7FEFF bl I2C_TransferConfig + 7874 .LVL540: + 7875 017e E2E7 b .L504 + ARM GAS /tmp/ccSHpINd.s page 317 + + + 7876 .LVL541: + 7877 .L499: +3654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7878 .loc 1 3654 7 is_stmt 1 view .LVU2762 +3654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7879 .loc 1 3654 21 is_stmt 0 view .LVU2763 + 7880 0180 164B ldr r3, .L516+12 + 7881 0182 6363 str r3, [r4, #52] +3658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7882 .loc 1 3658 7 is_stmt 1 view .LVU2764 +3658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7883 .loc 1 3658 10 is_stmt 0 view .LVU2765 + 7884 0184 B6F1007F cmp r6, #33554432 + 7885 0188 18BF it ne + 7886 018a 002E cmpne r6, #0 + 7887 018c 11D1 bne .L506 +3660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7888 .loc 1 3660 9 is_stmt 1 view .LVU2766 + 7889 018e CDF80090 str r9, [sp] + 7890 0192 3B46 mov r3, r7 + 7891 0194 5FFA88F2 uxtb r2, r8 + 7892 0198 2946 mov r1, r5 + 7893 019a 2046 mov r0, r4 + 7894 019c FFF7FEFF bl I2C_TransferConfig + 7895 .LVL542: + 7896 .L507: +3668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7897 .loc 1 3668 7 view .LVU2767 +3668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7898 .loc 1 3668 7 view .LVU2768 + 7899 01a0 0023 movs r3, #0 + 7900 01a2 84F84030 strb r3, [r4, #64] +3668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7901 .loc 1 3668 7 view .LVU2769 +3677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7902 .loc 1 3677 7 view .LVU2770 + 7903 01a6 0121 movs r1, #1 + 7904 01a8 2046 mov r0, r4 + 7905 01aa FFF7FEFF bl I2C_Enable_IRQ + 7906 .LVL543: + 7907 .L505: +3680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7908 .loc 1 3680 5 view .LVU2771 +3680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7909 .loc 1 3680 12 is_stmt 0 view .LVU2772 + 7910 01ae 0020 movs r0, #0 + 7911 01b0 09E0 b .L493 + 7912 .L506: +3664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7913 .loc 1 3664 9 is_stmt 1 view .LVU2773 + 7914 01b2 CDF80090 str r9, [sp] + 7915 01b6 3B46 mov r3, r7 + 7916 01b8 D2B2 uxtb r2, r2 + 7917 01ba 2946 mov r1, r5 + 7918 01bc 2046 mov r0, r4 + 7919 01be FFF7FEFF bl I2C_TransferConfig + 7920 .LVL544: + ARM GAS /tmp/ccSHpINd.s page 318 + + + 7921 01c2 EDE7 b .L507 + 7922 .LVL545: + 7923 .L508: +3684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 7924 .loc 1 3684 12 is_stmt 0 view .LVU2774 + 7925 01c4 0220 movs r0, #2 + 7926 .LVL546: + 7927 .L493: +3686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7928 .loc 1 3686 1 view .LVU2775 + 7929 01c6 03B0 add sp, sp, #12 + 7930 .LCFI92: + 7931 .cfi_remember_state + 7932 .cfi_def_cfa_offset 28 + 7933 @ sp needed + 7934 01c8 BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} + 7935 .LVL547: + 7936 .L509: + 7937 .LCFI93: + 7938 .cfi_restore_state +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7939 .loc 1 3517 5 discriminator 1 view .LVU2776 + 7940 01cc 0220 movs r0, #2 + 7941 01ce FAE7 b .L493 + 7942 .L517: + 7943 .align 2 + 7944 .L516: + 7945 01d0 00000000 .word I2C_Master_ISR_DMA + 7946 01d4 00000000 .word I2C_DMAMasterTransmitCplt + 7947 01d8 00000000 .word I2C_DMAError + 7948 01dc 00000000 .word I2C_Master_ISR_IT + 7949 01e0 00200080 .word -2147475456 + 7950 .cfi_endproc + 7951 .LFE165: + 7953 .section .text.HAL_I2C_Master_Seq_Receive_IT,"ax",%progbits + 7954 .align 1 + 7955 .global HAL_I2C_Master_Seq_Receive_IT + 7956 .syntax unified + 7957 .thumb + 7958 .thumb_func + 7960 HAL_I2C_Master_Seq_Receive_IT: + 7961 .LVL548: + 7962 .LFB166: +3702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; + 7963 .loc 1 3702 1 is_stmt 1 view -0 + 7964 .cfi_startproc + 7965 @ args = 4, pretend = 0, frame = 0 + 7966 @ frame_needed = 0, uses_anonymous_args = 0 +3702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; + 7967 .loc 1 3702 1 is_stmt 0 view .LVU2778 + 7968 0000 70B5 push {r4, r5, r6, lr} + 7969 .LCFI94: + 7970 .cfi_def_cfa_offset 16 + 7971 .cfi_offset 4, -16 + 7972 .cfi_offset 5, -12 + 7973 .cfi_offset 6, -8 + 7974 .cfi_offset 14, -4 + ARM GAS /tmp/ccSHpINd.s page 319 + + + 7975 0002 82B0 sub sp, sp, #8 + 7976 .LCFI95: + 7977 .cfi_def_cfa_offset 24 + 7978 0004 0446 mov r4, r0 + 7979 0006 0D46 mov r5, r1 + 7980 0008 0699 ldr r1, [sp, #24] + 7981 .LVL549: +3703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_READ; + 7982 .loc 1 3703 3 is_stmt 1 view .LVU2779 +3704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7983 .loc 1 3704 3 view .LVU2780 +3707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7984 .loc 1 3707 3 view .LVU2781 +3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7985 .loc 1 3709 3 view .LVU2782 +3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7986 .loc 1 3709 11 is_stmt 0 view .LVU2783 + 7987 000a 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 7988 .LVL550: +3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7989 .loc 1 3709 11 view .LVU2784 + 7990 000e C0B2 uxtb r0, r0 +3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 7991 .loc 1 3709 6 view .LVU2785 + 7992 0010 2028 cmp r0, #32 + 7993 0012 46D1 bne .L524 +3712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7994 .loc 1 3712 5 is_stmt 1 view .LVU2786 +3712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7995 .loc 1 3712 5 view .LVU2787 + 7996 0014 94F84000 ldrb r0, [r4, #64] @ zero_extendqisi2 + 7997 0018 0128 cmp r0, #1 + 7998 001a 44D0 beq .L525 +3712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 7999 .loc 1 3712 5 discriminator 2 view .LVU2788 + 8000 001c 0120 movs r0, #1 + 8001 001e 84F84000 strb r0, [r4, #64] +3712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8002 .loc 1 3712 5 discriminator 2 view .LVU2789 +3714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 8003 .loc 1 3714 5 view .LVU2790 +3714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 8004 .loc 1 3714 21 is_stmt 0 view .LVU2791 + 8005 0022 2220 movs r0, #34 + 8006 0024 84F84100 strb r0, [r4, #65] +3715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8007 .loc 1 3715 5 is_stmt 1 view .LVU2792 +3715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8008 .loc 1 3715 21 is_stmt 0 view .LVU2793 + 8009 0028 1020 movs r0, #16 + 8010 002a 84F84200 strb r0, [r4, #66] +3716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8011 .loc 1 3716 5 is_stmt 1 view .LVU2794 +3716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8012 .loc 1 3716 21 is_stmt 0 view .LVU2795 + 8013 002e 0020 movs r0, #0 + 8014 0030 6064 str r0, [r4, #68] + ARM GAS /tmp/ccSHpINd.s page 320 + + +3719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 8015 .loc 1 3719 5 is_stmt 1 view .LVU2796 +3719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 8016 .loc 1 3719 23 is_stmt 0 view .LVU2797 + 8017 0032 6262 str r2, [r4, #36] +3720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8018 .loc 1 3720 5 is_stmt 1 view .LVU2798 +3720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8019 .loc 1 3720 23 is_stmt 0 view .LVU2799 + 8020 0034 6385 strh r3, [r4, #42] @ movhi +3721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 8021 .loc 1 3721 5 is_stmt 1 view .LVU2800 +3721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 8022 .loc 1 3721 23 is_stmt 0 view .LVU2801 + 8023 0036 E162 str r1, [r4, #44] +3722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8024 .loc 1 3722 5 is_stmt 1 view .LVU2802 +3722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8025 .loc 1 3722 23 is_stmt 0 view .LVU2803 + 8026 0038 1C4B ldr r3, .L529 + 8027 .LVL551: +3722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8028 .loc 1 3722 23 view .LVU2804 + 8029 003a 6363 str r3, [r4, #52] +3725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8030 .loc 1 3725 5 is_stmt 1 view .LVU2805 +3725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8031 .loc 1 3725 13 is_stmt 0 view .LVU2806 + 8032 003c 638D ldrh r3, [r4, #42] + 8033 003e 9BB2 uxth r3, r3 +3725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8034 .loc 1 3725 8 view .LVU2807 + 8035 0040 FF2B cmp r3, #255 + 8036 0042 26D9 bls .L520 +3727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 8037 .loc 1 3727 7 is_stmt 1 view .LVU2808 +3727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 8038 .loc 1 3727 22 is_stmt 0 view .LVU2809 + 8039 0044 FF23 movs r3, #255 + 8040 0046 2385 strh r3, [r4, #40] @ movhi +3728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8041 .loc 1 3728 7 is_stmt 1 view .LVU2810 + 8042 .LVL552: +3728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8043 .loc 1 3728 16 is_stmt 0 view .LVU2811 + 8044 0048 4FF08076 mov r6, #16777216 + 8045 .LVL553: + 8046 .L521: +3739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 8047 .loc 1 3739 5 is_stmt 1 view .LVU2812 +3739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 8048 .loc 1 3739 14 is_stmt 0 view .LVU2813 + 8049 004c 236B ldr r3, [r4, #48] +3739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 8050 .loc 1 3739 8 view .LVU2814 + 8051 004e 122B cmp r3, #18 + 8052 0050 04D1 bne .L522 + ARM GAS /tmp/ccSHpINd.s page 321 + + +3739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 8053 .loc 1 3739 59 discriminator 1 view .LVU2815 + 8054 0052 B1F52A4F cmp r1, #43520 + 8055 0056 18BF it ne + 8056 0058 AA29 cmpne r1, #170 + 8057 005a 1ED1 bne .L526 + 8058 .L522: +3747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8059 .loc 1 3747 7 is_stmt 1 view .LVU2816 + 8060 005c 2046 mov r0, r4 + 8061 005e FFF7FEFF bl I2C_ConvertOtherXferOptions + 8062 .LVL554: +3750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8063 .loc 1 3750 7 view .LVU2817 +3750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8064 .loc 1 3750 15 is_stmt 0 view .LVU2818 + 8065 0062 638D ldrh r3, [r4, #42] + 8066 0064 9BB2 uxth r3, r3 +3750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8067 .loc 1 3750 10 view .LVU2819 + 8068 0066 FF2B cmp r3, #255 + 8069 0068 19D8 bhi .L527 +3752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8070 .loc 1 3752 9 is_stmt 1 view .LVU2820 +3752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8071 .loc 1 3752 18 is_stmt 0 view .LVU2821 + 8072 006a E66A ldr r6, [r4, #44] + 8073 .LVL555: +3704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8074 .loc 1 3704 12 view .LVU2822 + 8075 006c 104B ldr r3, .L529+4 + 8076 .L523: + 8077 .LVL556: +3757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8078 .loc 1 3757 5 is_stmt 1 view .LVU2823 + 8079 006e 0093 str r3, [sp] + 8080 0070 3346 mov r3, r6 + 8081 .LVL557: +3757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8082 .loc 1 3757 5 is_stmt 0 view .LVU2824 + 8083 0072 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 8084 0076 2946 mov r1, r5 + 8085 0078 2046 mov r0, r4 + 8086 007a FFF7FEFF bl I2C_TransferConfig + 8087 .LVL558: +3760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8088 .loc 1 3760 5 is_stmt 1 view .LVU2825 +3760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8089 .loc 1 3760 5 view .LVU2826 + 8090 007e 0025 movs r5, #0 + 8091 .LVL559: +3760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8092 .loc 1 3760 5 is_stmt 0 view .LVU2827 + 8093 0080 84F84050 strb r5, [r4, #64] +3760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8094 .loc 1 3760 5 is_stmt 1 view .LVU2828 +3765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 322 + + + 8095 .loc 1 3765 5 view .LVU2829 + 8096 0084 0221 movs r1, #2 + 8097 0086 2046 mov r0, r4 + 8098 0088 FFF7FEFF bl I2C_Enable_IRQ + 8099 .LVL560: +3767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8100 .loc 1 3767 5 view .LVU2830 +3767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8101 .loc 1 3767 12 is_stmt 0 view .LVU2831 + 8102 008c 2846 mov r0, r5 + 8103 .LVL561: + 8104 .L519: +3773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8105 .loc 1 3773 1 view .LVU2832 + 8106 008e 02B0 add sp, sp, #8 + 8107 .LCFI96: + 8108 .cfi_remember_state + 8109 .cfi_def_cfa_offset 16 + 8110 @ sp needed + 8111 0090 70BD pop {r4, r5, r6, pc} + 8112 .LVL562: + 8113 .L520: + 8114 .LCFI97: + 8115 .cfi_restore_state +3732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 8116 .loc 1 3732 7 is_stmt 1 view .LVU2833 +3732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 8117 .loc 1 3732 28 is_stmt 0 view .LVU2834 + 8118 0092 638D ldrh r3, [r4, #42] +3732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 8119 .loc 1 3732 22 view .LVU2835 + 8120 0094 2385 strh r3, [r4, #40] @ movhi +3733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8121 .loc 1 3733 7 is_stmt 1 view .LVU2836 +3733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8122 .loc 1 3733 16 is_stmt 0 view .LVU2837 + 8123 0096 E66A ldr r6, [r4, #44] + 8124 .LVL563: +3733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8125 .loc 1 3733 16 view .LVU2838 + 8126 0098 D8E7 b .L521 + 8127 .L526: +3742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8128 .loc 1 3742 19 view .LVU2839 + 8129 009a 0023 movs r3, #0 + 8130 009c E7E7 b .L523 + 8131 .LVL564: + 8132 .L527: +3704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8133 .loc 1 3704 12 view .LVU2840 + 8134 009e 044B ldr r3, .L529+4 + 8135 00a0 E5E7 b .L523 + 8136 .LVL565: + 8137 .L524: +3771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8138 .loc 1 3771 12 view .LVU2841 + 8139 00a2 0220 movs r0, #2 + ARM GAS /tmp/ccSHpINd.s page 323 + + + 8140 00a4 F3E7 b .L519 + 8141 .L525: +3712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8142 .loc 1 3712 5 discriminator 1 view .LVU2842 + 8143 00a6 0220 movs r0, #2 + 8144 00a8 F1E7 b .L519 + 8145 .L530: + 8146 00aa 00BF .align 2 + 8147 .L529: + 8148 00ac 00000000 .word I2C_Master_ISR_IT + 8149 00b0 00240080 .word -2147474432 + 8150 .cfi_endproc + 8151 .LFE166: + 8153 .section .text.HAL_I2C_Master_Seq_Receive_DMA,"ax",%progbits + 8154 .align 1 + 8155 .global HAL_I2C_Master_Seq_Receive_DMA + 8156 .syntax unified + 8157 .thumb + 8158 .thumb_func + 8160 HAL_I2C_Master_Seq_Receive_DMA: + 8161 .LVL566: + 8162 .LFB167: +3789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; + 8163 .loc 1 3789 1 is_stmt 1 view -0 + 8164 .cfi_startproc + 8165 @ args = 4, pretend = 0, frame = 0 + 8166 @ frame_needed = 0, uses_anonymous_args = 0 +3789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; + 8167 .loc 1 3789 1 is_stmt 0 view .LVU2844 + 8168 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 8169 .LCFI98: + 8170 .cfi_def_cfa_offset 24 + 8171 .cfi_offset 4, -24 + 8172 .cfi_offset 5, -20 + 8173 .cfi_offset 6, -16 + 8174 .cfi_offset 7, -12 + 8175 .cfi_offset 8, -8 + 8176 .cfi_offset 14, -4 + 8177 0004 82B0 sub sp, sp, #8 + 8178 .LCFI99: + 8179 .cfi_def_cfa_offset 32 + 8180 0006 0446 mov r4, r0 + 8181 0008 1546 mov r5, r2 + 8182 000a 089A ldr r2, [sp, #32] + 8183 .LVL567: +3790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_READ; + 8184 .loc 1 3790 3 is_stmt 1 view .LVU2845 +3791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 8185 .loc 1 3791 3 view .LVU2846 +3792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8186 .loc 1 3792 3 view .LVU2847 +3795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8187 .loc 1 3795 3 view .LVU2848 +3797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8188 .loc 1 3797 3 view .LVU2849 +3797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8189 .loc 1 3797 11 is_stmt 0 view .LVU2850 + ARM GAS /tmp/ccSHpINd.s page 324 + + + 8190 000c 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 8191 .LVL568: +3797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8192 .loc 1 3797 11 view .LVU2851 + 8193 0010 C0B2 uxtb r0, r0 +3797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8194 .loc 1 3797 6 view .LVU2852 + 8195 0012 2028 cmp r0, #32 + 8196 0014 40F09D80 bne .L542 + 8197 0018 0E46 mov r6, r1 +3800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8198 .loc 1 3800 5 is_stmt 1 view .LVU2853 +3800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8199 .loc 1 3800 5 view .LVU2854 + 8200 001a 94F84010 ldrb r1, [r4, #64] @ zero_extendqisi2 + 8201 .LVL569: +3800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8202 .loc 1 3800 5 is_stmt 0 view .LVU2855 + 8203 001e 0129 cmp r1, #1 + 8204 0020 00F09B80 beq .L543 +3800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8205 .loc 1 3800 5 is_stmt 1 discriminator 2 view .LVU2856 + 8206 0024 0121 movs r1, #1 + 8207 0026 84F84010 strb r1, [r4, #64] +3800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8208 .loc 1 3800 5 discriminator 2 view .LVU2857 +3802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 8209 .loc 1 3802 5 view .LVU2858 +3802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 8210 .loc 1 3802 21 is_stmt 0 view .LVU2859 + 8211 002a 2221 movs r1, #34 + 8212 002c 84F84110 strb r1, [r4, #65] +3803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8213 .loc 1 3803 5 is_stmt 1 view .LVU2860 +3803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8214 .loc 1 3803 21 is_stmt 0 view .LVU2861 + 8215 0030 1021 movs r1, #16 + 8216 0032 84F84210 strb r1, [r4, #66] +3804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8217 .loc 1 3804 5 is_stmt 1 view .LVU2862 +3804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8218 .loc 1 3804 21 is_stmt 0 view .LVU2863 + 8219 0036 0021 movs r1, #0 + 8220 0038 6164 str r1, [r4, #68] +3807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 8221 .loc 1 3807 5 is_stmt 1 view .LVU2864 +3807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 8222 .loc 1 3807 23 is_stmt 0 view .LVU2865 + 8223 003a 6562 str r5, [r4, #36] +3808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8224 .loc 1 3808 5 is_stmt 1 view .LVU2866 +3808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8225 .loc 1 3808 23 is_stmt 0 view .LVU2867 + 8226 003c 6385 strh r3, [r4, #42] @ movhi +3809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 8227 .loc 1 3809 5 is_stmt 1 view .LVU2868 +3809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + ARM GAS /tmp/ccSHpINd.s page 325 + + + 8228 .loc 1 3809 23 is_stmt 0 view .LVU2869 + 8229 003e E262 str r2, [r4, #44] +3810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8230 .loc 1 3810 5 is_stmt 1 view .LVU2870 +3810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8231 .loc 1 3810 23 is_stmt 0 view .LVU2871 + 8232 0040 474B ldr r3, .L549 + 8233 .LVL570: +3810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8234 .loc 1 3810 23 view .LVU2872 + 8235 0042 6363 str r3, [r4, #52] +3813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8236 .loc 1 3813 5 is_stmt 1 view .LVU2873 +3813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8237 .loc 1 3813 13 is_stmt 0 view .LVU2874 + 8238 0044 638D ldrh r3, [r4, #42] + 8239 0046 9BB2 uxth r3, r3 +3813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8240 .loc 1 3813 8 view .LVU2875 + 8241 0048 FF2B cmp r3, #255 + 8242 004a 3AD9 bls .L533 +3815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 8243 .loc 1 3815 7 is_stmt 1 view .LVU2876 +3815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 8244 .loc 1 3815 22 is_stmt 0 view .LVU2877 + 8245 004c FF23 movs r3, #255 + 8246 004e 2385 strh r3, [r4, #40] @ movhi +3816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8247 .loc 1 3816 7 is_stmt 1 view .LVU2878 + 8248 .LVL571: +3816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8249 .loc 1 3816 16 is_stmt 0 view .LVU2879 + 8250 0050 4FF08077 mov r7, #16777216 + 8251 .LVL572: + 8252 .L534: +3827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 8253 .loc 1 3827 5 is_stmt 1 view .LVU2880 +3827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 8254 .loc 1 3827 14 is_stmt 0 view .LVU2881 + 8255 0054 236B ldr r3, [r4, #48] +3827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 8256 .loc 1 3827 8 view .LVU2882 + 8257 0056 122B cmp r3, #18 + 8258 0058 04D1 bne .L535 +3827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 8259 .loc 1 3827 59 discriminator 1 view .LVU2883 + 8260 005a B2F52A4F cmp r2, #43520 + 8261 005e 18BF it ne + 8262 0060 AA2A cmpne r2, #170 + 8263 0062 32D1 bne .L544 + 8264 .L535: +3835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8265 .loc 1 3835 7 is_stmt 1 view .LVU2884 + 8266 0064 2046 mov r0, r4 + 8267 0066 FFF7FEFF bl I2C_ConvertOtherXferOptions + 8268 .LVL573: +3838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 326 + + + 8269 .loc 1 3838 7 view .LVU2885 +3838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8270 .loc 1 3838 15 is_stmt 0 view .LVU2886 + 8271 006a 638D ldrh r3, [r4, #42] + 8272 006c 9BB2 uxth r3, r3 +3838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8273 .loc 1 3838 10 view .LVU2887 + 8274 006e FF2B cmp r3, #255 + 8275 0070 2ED8 bhi .L545 +3840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8276 .loc 1 3840 9 is_stmt 1 view .LVU2888 +3840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8277 .loc 1 3840 18 is_stmt 0 view .LVU2889 + 8278 0072 E76A ldr r7, [r4, #44] + 8279 .LVL574: +3791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 8280 .loc 1 3791 12 view .LVU2890 + 8281 0074 DFF8F880 ldr r8, .L549+16 + 8282 .L536: + 8283 .LVL575: +3844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8284 .loc 1 3844 5 is_stmt 1 view .LVU2891 +3844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8285 .loc 1 3844 13 is_stmt 0 view .LVU2892 + 8286 0078 228D ldrh r2, [r4, #40] +3844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8287 .loc 1 3844 8 view .LVU2893 + 8288 007a 002A cmp r2, #0 + 8289 007c 55D0 beq .L537 +3846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8290 .loc 1 3846 7 is_stmt 1 view .LVU2894 +3846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8291 .loc 1 3846 15 is_stmt 0 view .LVU2895 + 8292 007e E36B ldr r3, [r4, #60] +3846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8293 .loc 1 3846 10 view .LVU2896 + 8294 0080 4BB3 cbz r3, .L538 +3849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8295 .loc 1 3849 9 is_stmt 1 view .LVU2897 +3849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8296 .loc 1 3849 40 is_stmt 0 view .LVU2898 + 8297 0082 384A ldr r2, .L549+4 + 8298 0084 DA63 str r2, [r3, #60] +3852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8299 .loc 1 3852 9 is_stmt 1 view .LVU2899 +3852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8300 .loc 1 3852 13 is_stmt 0 view .LVU2900 + 8301 0086 E36B ldr r3, [r4, #60] +3852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8302 .loc 1 3852 41 view .LVU2901 + 8303 0088 374A ldr r2, .L549+8 + 8304 008a DA64 str r2, [r3, #76] +3855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 8305 .loc 1 3855 9 is_stmt 1 view .LVU2902 +3855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 8306 .loc 1 3855 13 is_stmt 0 view .LVU2903 + 8307 008c E26B ldr r2, [r4, #60] + ARM GAS /tmp/ccSHpINd.s page 327 + + +3855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 8308 .loc 1 3855 44 view .LVU2904 + 8309 008e 0023 movs r3, #0 + 8310 0090 1364 str r3, [r2, #64] +3856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8311 .loc 1 3856 9 is_stmt 1 view .LVU2905 +3856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8312 .loc 1 3856 13 is_stmt 0 view .LVU2906 + 8313 0092 E26B ldr r2, [r4, #60] +3856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8314 .loc 1 3856 41 view .LVU2907 + 8315 0094 1365 str r3, [r2, #80] +3859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 8316 .loc 1 3859 9 is_stmt 1 view .LVU2908 +3859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 8317 .loc 1 3859 71 is_stmt 0 view .LVU2909 + 8318 0096 2168 ldr r1, [r4] +3859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 8319 .loc 1 3859 25 view .LVU2910 + 8320 0098 238D ldrh r3, [r4, #40] + 8321 009a 2A46 mov r2, r5 + 8322 009c 2431 adds r1, r1, #36 + 8323 009e E06B ldr r0, [r4, #60] + 8324 00a0 FFF7FEFF bl HAL_DMA_Start_IT + 8325 .LVL576: +3877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8326 .loc 1 3877 7 is_stmt 1 view .LVU2911 +3877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8327 .loc 1 3877 10 is_stmt 0 view .LVU2912 + 8328 00a4 28B3 cbz r0, .L548 +3900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8329 .loc 1 3900 9 is_stmt 1 view .LVU2913 +3900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8330 .loc 1 3900 25 is_stmt 0 view .LVU2914 + 8331 00a6 2023 movs r3, #32 + 8332 00a8 84F84130 strb r3, [r4, #65] +3901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8333 .loc 1 3901 9 is_stmt 1 view .LVU2915 +3901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8334 .loc 1 3901 25 is_stmt 0 view .LVU2916 + 8335 00ac 0022 movs r2, #0 + 8336 00ae 84F84220 strb r2, [r4, #66] +3904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8337 .loc 1 3904 9 is_stmt 1 view .LVU2917 +3904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8338 .loc 1 3904 13 is_stmt 0 view .LVU2918 + 8339 00b2 636C ldr r3, [r4, #68] +3904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8340 .loc 1 3904 25 view .LVU2919 + 8341 00b4 43F01003 orr r3, r3, #16 + 8342 00b8 6364 str r3, [r4, #68] +3907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8343 .loc 1 3907 9 is_stmt 1 view .LVU2920 +3907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8344 .loc 1 3907 9 view .LVU2921 + 8345 00ba 84F84020 strb r2, [r4, #64] +3907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 328 + + + 8346 .loc 1 3907 9 view .LVU2922 +3909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8347 .loc 1 3909 9 view .LVU2923 +3909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8348 .loc 1 3909 16 is_stmt 0 view .LVU2924 + 8349 00be 0120 movs r0, #1 + 8350 .LVL577: +3909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8351 .loc 1 3909 16 view .LVU2925 + 8352 00c0 48E0 b .L532 + 8353 .LVL578: + 8354 .L533: +3820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 8355 .loc 1 3820 7 is_stmt 1 view .LVU2926 +3820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 8356 .loc 1 3820 28 is_stmt 0 view .LVU2927 + 8357 00c2 638D ldrh r3, [r4, #42] +3820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 8358 .loc 1 3820 22 view .LVU2928 + 8359 00c4 2385 strh r3, [r4, #40] @ movhi +3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8360 .loc 1 3821 7 is_stmt 1 view .LVU2929 +3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8361 .loc 1 3821 16 is_stmt 0 view .LVU2930 + 8362 00c6 E76A ldr r7, [r4, #44] + 8363 .LVL579: +3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8364 .loc 1 3821 16 view .LVU2931 + 8365 00c8 C4E7 b .L534 + 8366 .L544: +3830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8367 .loc 1 3830 19 view .LVU2932 + 8368 00ca 4FF00008 mov r8, #0 + 8369 00ce D3E7 b .L536 + 8370 .L545: +3791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 8371 .loc 1 3791 12 view .LVU2933 + 8372 00d0 DFF89C80 ldr r8, .L549+16 + 8373 00d4 D0E7 b .L536 + 8374 .LVL580: + 8375 .L538: +3865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8376 .loc 1 3865 9 is_stmt 1 view .LVU2934 +3865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8377 .loc 1 3865 25 is_stmt 0 view .LVU2935 + 8378 00d6 2023 movs r3, #32 + 8379 00d8 84F84130 strb r3, [r4, #65] +3866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8380 .loc 1 3866 9 is_stmt 1 view .LVU2936 +3866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8381 .loc 1 3866 25 is_stmt 0 view .LVU2937 + 8382 00dc 0022 movs r2, #0 + 8383 00de 84F84220 strb r2, [r4, #66] +3869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8384 .loc 1 3869 9 is_stmt 1 view .LVU2938 +3869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8385 .loc 1 3869 13 is_stmt 0 view .LVU2939 + ARM GAS /tmp/ccSHpINd.s page 329 + + + 8386 00e2 636C ldr r3, [r4, #68] +3869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8387 .loc 1 3869 25 view .LVU2940 + 8388 00e4 43F08003 orr r3, r3, #128 + 8389 00e8 6364 str r3, [r4, #68] +3872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8390 .loc 1 3872 9 is_stmt 1 view .LVU2941 +3872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8391 .loc 1 3872 9 view .LVU2942 + 8392 00ea 84F84020 strb r2, [r4, #64] +3872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8393 .loc 1 3872 9 view .LVU2943 +3874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8394 .loc 1 3874 9 view .LVU2944 +3874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8395 .loc 1 3874 16 is_stmt 0 view .LVU2945 + 8396 00ee 0120 movs r0, #1 + 8397 00f0 30E0 b .L532 + 8398 .LVL581: + 8399 .L548: +3880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8400 .loc 1 3880 9 is_stmt 1 view .LVU2946 + 8401 00f2 CDF80080 str r8, [sp] + 8402 00f6 3B46 mov r3, r7 + 8403 00f8 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 8404 00fc 3146 mov r1, r6 + 8405 00fe 2046 mov r0, r4 + 8406 .LVL582: +3880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8407 .loc 1 3880 9 is_stmt 0 view .LVU2947 + 8408 0100 FFF7FEFF bl I2C_TransferConfig + 8409 .LVL583: +3883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8410 .loc 1 3883 9 is_stmt 1 view .LVU2948 +3883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8411 .loc 1 3883 13 is_stmt 0 view .LVU2949 + 8412 0104 638D ldrh r3, [r4, #42] + 8413 0106 9BB2 uxth r3, r3 +3883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8414 .loc 1 3883 32 view .LVU2950 + 8415 0108 228D ldrh r2, [r4, #40] +3883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8416 .loc 1 3883 25 view .LVU2951 + 8417 010a 9B1A subs r3, r3, r2 + 8418 010c 9BB2 uxth r3, r3 + 8419 010e 6385 strh r3, [r4, #42] @ movhi +3886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8420 .loc 1 3886 9 is_stmt 1 view .LVU2952 +3886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8421 .loc 1 3886 9 view .LVU2953 + 8422 0110 0023 movs r3, #0 + 8423 0112 84F84030 strb r3, [r4, #64] +3886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8424 .loc 1 3886 9 view .LVU2954 +3892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8425 .loc 1 3892 9 view .LVU2955 + 8426 0116 1021 movs r1, #16 + ARM GAS /tmp/ccSHpINd.s page 330 + + + 8427 0118 2046 mov r0, r4 + 8428 011a FFF7FEFF bl I2C_Enable_IRQ + 8429 .LVL584: +3895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8430 .loc 1 3895 9 view .LVU2956 +3895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8431 .loc 1 3895 13 is_stmt 0 view .LVU2957 + 8432 011e 2268 ldr r2, [r4] +3895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8433 .loc 1 3895 23 view .LVU2958 + 8434 0120 1368 ldr r3, [r2] +3895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8435 .loc 1 3895 29 view .LVU2959 + 8436 0122 43F40043 orr r3, r3, #32768 + 8437 0126 1360 str r3, [r2] + 8438 0128 11E0 b .L541 + 8439 .LVL585: + 8440 .L537: +3915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8441 .loc 1 3915 7 is_stmt 1 view .LVU2960 +3915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8442 .loc 1 3915 21 is_stmt 0 view .LVU2961 + 8443 012a 104B ldr r3, .L549+12 + 8444 012c 6363 str r3, [r4, #52] +3919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 8445 .loc 1 3919 7 is_stmt 1 view .LVU2962 + 8446 012e 104B ldr r3, .L549+16 + 8447 0130 0093 str r3, [sp] + 8448 0132 4FF00073 mov r3, #33554432 + 8449 0136 D2B2 uxtb r2, r2 + 8450 0138 3146 mov r1, r6 + 8451 013a 2046 mov r0, r4 + 8452 013c FFF7FEFF bl I2C_TransferConfig + 8453 .LVL586: +3923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8454 .loc 1 3923 7 view .LVU2963 +3923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8455 .loc 1 3923 7 view .LVU2964 + 8456 0140 0023 movs r3, #0 + 8457 0142 84F84030 strb r3, [r4, #64] +3923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8458 .loc 1 3923 7 view .LVU2965 +3932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8459 .loc 1 3932 7 view .LVU2966 + 8460 0146 0221 movs r1, #2 + 8461 0148 2046 mov r0, r4 + 8462 014a FFF7FEFF bl I2C_Enable_IRQ + 8463 .LVL587: + 8464 .L541: +3935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8465 .loc 1 3935 5 view .LVU2967 +3935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8466 .loc 1 3935 12 is_stmt 0 view .LVU2968 + 8467 014e 0020 movs r0, #0 + 8468 0150 00E0 b .L532 + 8469 .LVL588: + 8470 .L542: + ARM GAS /tmp/ccSHpINd.s page 331 + + +3939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8471 .loc 1 3939 12 view .LVU2969 + 8472 0152 0220 movs r0, #2 + 8473 .LVL589: + 8474 .L532: +3941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8475 .loc 1 3941 1 view .LVU2970 + 8476 0154 02B0 add sp, sp, #8 + 8477 .LCFI100: + 8478 .cfi_remember_state + 8479 .cfi_def_cfa_offset 24 + 8480 @ sp needed + 8481 0156 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 8482 .LVL590: + 8483 .L543: + 8484 .LCFI101: + 8485 .cfi_restore_state +3800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8486 .loc 1 3800 5 discriminator 1 view .LVU2971 + 8487 015a 0220 movs r0, #2 + 8488 015c FAE7 b .L532 + 8489 .L550: + 8490 015e 00BF .align 2 + 8491 .L549: + 8492 0160 00000000 .word I2C_Master_ISR_DMA + 8493 0164 00000000 .word I2C_DMAMasterReceiveCplt + 8494 0168 00000000 .word I2C_DMAError + 8495 016c 00000000 .word I2C_Master_ISR_IT + 8496 0170 00240080 .word -2147474432 + 8497 .cfi_endproc + 8498 .LFE167: + 8500 .section .text.HAL_I2C_Slave_Seq_Transmit_IT,"ax",%progbits + 8501 .align 1 + 8502 .global HAL_I2C_Slave_Seq_Transmit_IT + 8503 .syntax unified + 8504 .thumb + 8505 .thumb_func + 8507 HAL_I2C_Slave_Seq_Transmit_IT: + 8508 .LVL591: + 8509 .LFB168: +3955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ + 8510 .loc 1 3955 1 is_stmt 1 view -0 + 8511 .cfi_startproc + 8512 @ args = 0, pretend = 0, frame = 0 + 8513 @ frame_needed = 0, uses_anonymous_args = 0 +3955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ + 8514 .loc 1 3955 1 is_stmt 0 view .LVU2973 + 8515 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 8516 .LCFI102: + 8517 .cfi_def_cfa_offset 24 + 8518 .cfi_offset 3, -24 + 8519 .cfi_offset 4, -20 + 8520 .cfi_offset 5, -16 + 8521 .cfi_offset 6, -12 + 8522 .cfi_offset 7, -8 + 8523 .cfi_offset 14, -4 + 8524 0002 0446 mov r4, r0 + ARM GAS /tmp/ccSHpINd.s page 332 + + +3957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8525 .loc 1 3957 3 is_stmt 1 view .LVU2974 +3960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8526 .loc 1 3960 3 view .LVU2975 +3962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8527 .loc 1 3962 3 view .LVU2976 +3962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8528 .loc 1 3962 22 is_stmt 0 view .LVU2977 + 8529 0004 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 8530 .LVL592: +3962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8531 .loc 1 3962 6 view .LVU2978 + 8532 0008 00F02800 and r0, r0, #40 + 8533 000c 2828 cmp r0, #40 + 8534 000e 60D1 bne .L556 + 8535 0010 0F46 mov r7, r1 + 8536 0012 1646 mov r6, r2 + 8537 0014 1D46 mov r5, r3 +3964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8538 .loc 1 3964 5 is_stmt 1 view .LVU2979 +3964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8539 .loc 1 3964 8 is_stmt 0 view .LVU2980 + 8540 0016 002A cmp r2, #0 + 8541 0018 18BF it ne + 8542 001a 0029 cmpne r1, #0 + 8543 001c 04D1 bne .L553 +3966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 8544 .loc 1 3966 7 is_stmt 1 view .LVU2981 +3966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 8545 .loc 1 3966 23 is_stmt 0 view .LVU2982 + 8546 001e 4FF40073 mov r3, #512 + 8547 .LVL593: +3966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 8548 .loc 1 3966 23 view .LVU2983 + 8549 0022 6364 str r3, [r4, #68] +3967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8550 .loc 1 3967 7 is_stmt 1 view .LVU2984 +3967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8551 .loc 1 3967 15 is_stmt 0 view .LVU2985 + 8552 0024 0120 movs r0, #1 + 8553 0026 55E0 b .L552 + 8554 .LVL594: + 8555 .L553: +3971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8556 .loc 1 3971 5 is_stmt 1 view .LVU2986 + 8557 0028 48F20101 movw r1, #32769 + 8558 .LVL595: +3971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8559 .loc 1 3971 5 is_stmt 0 view .LVU2987 + 8560 002c 2046 mov r0, r4 + 8561 002e FFF7FEFF bl I2C_Disable_IRQ + 8562 .LVL596: +3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8563 .loc 1 3974 5 is_stmt 1 view .LVU2988 +3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8564 .loc 1 3974 5 view .LVU2989 + 8565 0032 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + ARM GAS /tmp/ccSHpINd.s page 333 + + + 8566 0036 012B cmp r3, #1 + 8567 0038 4DD0 beq .L557 +3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8568 .loc 1 3974 5 discriminator 2 view .LVU2990 + 8569 003a 0123 movs r3, #1 + 8570 003c 84F84030 strb r3, [r4, #64] +3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8571 .loc 1 3974 5 discriminator 2 view .LVU2991 +3978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8572 .loc 1 3978 5 view .LVU2992 +3978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8573 .loc 1 3978 13 is_stmt 0 view .LVU2993 + 8574 0040 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 8575 0044 DBB2 uxtb r3, r3 +3978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8576 .loc 1 3978 8 view .LVU2994 + 8577 0046 2A2B cmp r3, #42 + 8578 0048 28D0 beq .L559 + 8579 .L554: +4004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8580 .loc 1 4004 5 is_stmt 1 view .LVU2995 +4004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8581 .loc 1 4004 21 is_stmt 0 view .LVU2996 + 8582 004a 2923 movs r3, #41 + 8583 004c 84F84130 strb r3, [r4, #65] +4005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8584 .loc 1 4005 5 is_stmt 1 view .LVU2997 +4005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8585 .loc 1 4005 21 is_stmt 0 view .LVU2998 + 8586 0050 2023 movs r3, #32 + 8587 0052 84F84230 strb r3, [r4, #66] +4006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8588 .loc 1 4006 5 is_stmt 1 view .LVU2999 +4006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8589 .loc 1 4006 21 is_stmt 0 view .LVU3000 + 8590 0056 0023 movs r3, #0 + 8591 0058 6364 str r3, [r4, #68] +4009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8592 .loc 1 4009 5 is_stmt 1 view .LVU3001 +4009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8593 .loc 1 4009 9 is_stmt 0 view .LVU3002 + 8594 005a 2268 ldr r2, [r4] +4009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8595 .loc 1 4009 19 view .LVU3003 + 8596 005c 5368 ldr r3, [r2, #4] +4009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8597 .loc 1 4009 25 view .LVU3004 + 8598 005e 23F40043 bic r3, r3, #32768 + 8599 0062 5360 str r3, [r2, #4] +4012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 8600 .loc 1 4012 5 is_stmt 1 view .LVU3005 +4012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 8601 .loc 1 4012 23 is_stmt 0 view .LVU3006 + 8602 0064 6762 str r7, [r4, #36] +4013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8603 .loc 1 4013 5 is_stmt 1 view .LVU3007 +4013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + ARM GAS /tmp/ccSHpINd.s page 334 + + + 8604 .loc 1 4013 23 is_stmt 0 view .LVU3008 + 8605 0066 6685 strh r6, [r4, #42] @ movhi +4014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8606 .loc 1 4014 5 is_stmt 1 view .LVU3009 +4014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8607 .loc 1 4014 29 is_stmt 0 view .LVU3010 + 8608 0068 638D ldrh r3, [r4, #42] +4014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8609 .loc 1 4014 23 view .LVU3011 + 8610 006a 2385 strh r3, [r4, #40] @ movhi +4015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 8611 .loc 1 4015 5 is_stmt 1 view .LVU3012 +4015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 8612 .loc 1 4015 23 is_stmt 0 view .LVU3013 + 8613 006c E562 str r5, [r4, #44] +4016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8614 .loc 1 4016 5 is_stmt 1 view .LVU3014 +4016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8615 .loc 1 4016 23 is_stmt 0 view .LVU3015 + 8616 006e 1B4B ldr r3, .L560 + 8617 0070 6363 str r3, [r4, #52] +4018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + 8618 .loc 1 4018 5 is_stmt 1 view .LVU3016 +4018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + 8619 .loc 1 4018 11 is_stmt 0 view .LVU3017 + 8620 0072 2268 ldr r2, [r4] + 8621 0074 9369 ldr r3, [r2, #24] + 8622 0076 03F00803 and r3, r3, #8 + 8623 .LVL597: +4019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8624 .loc 1 4019 5 is_stmt 1 view .LVU3018 +4019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8625 .loc 1 4019 10 is_stmt 0 view .LVU3019 + 8626 007a 9169 ldr r1, [r2, #24] +4019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8627 .loc 1 4019 8 view .LVU3020 + 8628 007c 11F4803F tst r1, #65536 + 8629 0080 02D0 beq .L555 +4019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8630 .loc 1 4019 54 discriminator 1 view .LVU3021 + 8631 0082 0BB1 cbz r3, .L555 +4023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8632 .loc 1 4023 7 is_stmt 1 view .LVU3022 + 8633 0084 0823 movs r3, #8 + 8634 .LVL598: +4023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8635 .loc 1 4023 7 is_stmt 0 view .LVU3023 + 8636 0086 D361 str r3, [r2, #28] + 8637 .L555: +4027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8638 .loc 1 4027 5 is_stmt 1 view .LVU3024 +4027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8639 .loc 1 4027 5 view .LVU3025 + 8640 0088 0025 movs r5, #0 + 8641 .LVL599: +4027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8642 .loc 1 4027 5 is_stmt 0 view .LVU3026 + ARM GAS /tmp/ccSHpINd.s page 335 + + + 8643 008a 84F84050 strb r5, [r4, #64] +4027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8644 .loc 1 4027 5 is_stmt 1 view .LVU3027 +4033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8645 .loc 1 4033 5 view .LVU3028 + 8646 008e 48F20101 movw r1, #32769 + 8647 0092 2046 mov r0, r4 + 8648 0094 FFF7FEFF bl I2C_Enable_IRQ + 8649 .LVL600: +4035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8650 .loc 1 4035 5 view .LVU3029 +4035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8651 .loc 1 4035 12 is_stmt 0 view .LVU3030 + 8652 0098 2846 mov r0, r5 + 8653 009a 1BE0 b .L552 + 8654 .LVL601: + 8655 .L559: +3981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8656 .loc 1 3981 7 is_stmt 1 view .LVU3031 + 8657 009c 0221 movs r1, #2 + 8658 009e 2046 mov r0, r4 + 8659 00a0 FFF7FEFF bl I2C_Disable_IRQ + 8660 .LVL602: +3984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8661 .loc 1 3984 7 view .LVU3032 +3984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8662 .loc 1 3984 16 is_stmt 0 view .LVU3033 + 8663 00a4 2368 ldr r3, [r4] +3984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8664 .loc 1 3984 26 view .LVU3034 + 8665 00a6 1A68 ldr r2, [r3] +3984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8666 .loc 1 3984 10 view .LVU3035 + 8667 00a8 12F4004F tst r2, #32768 + 8668 00ac CDD0 beq .L554 +3986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8669 .loc 1 3986 9 is_stmt 1 view .LVU3036 +3986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8670 .loc 1 3986 23 is_stmt 0 view .LVU3037 + 8671 00ae 1A68 ldr r2, [r3] +3986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8672 .loc 1 3986 29 view .LVU3038 + 8673 00b0 22F40042 bic r2, r2, #32768 + 8674 00b4 1A60 str r2, [r3] +3988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8675 .loc 1 3988 9 is_stmt 1 view .LVU3039 +3988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8676 .loc 1 3988 17 is_stmt 0 view .LVU3040 + 8677 00b6 E36B ldr r3, [r4, #60] +3988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8678 .loc 1 3988 12 view .LVU3041 + 8679 00b8 002B cmp r3, #0 + 8680 00ba C6D0 beq .L554 +3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8681 .loc 1 3992 11 is_stmt 1 view .LVU3042 +3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8682 .loc 1 3992 43 is_stmt 0 view .LVU3043 + ARM GAS /tmp/ccSHpINd.s page 336 + + + 8683 00bc 084A ldr r2, .L560+4 + 8684 00be 1A65 str r2, [r3, #80] +3995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8685 .loc 1 3995 11 is_stmt 1 view .LVU3044 +3995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8686 .loc 1 3995 15 is_stmt 0 view .LVU3045 + 8687 00c0 E06B ldr r0, [r4, #60] + 8688 00c2 FFF7FEFF bl HAL_DMA_Abort_IT + 8689 .LVL603: +3995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8690 .loc 1 3995 14 discriminator 1 view .LVU3046 + 8691 00c6 0028 cmp r0, #0 + 8692 00c8 BFD0 beq .L554 +3998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8693 .loc 1 3998 13 is_stmt 1 view .LVU3047 +3998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8694 .loc 1 3998 17 is_stmt 0 view .LVU3048 + 8695 00ca E06B ldr r0, [r4, #60] +3998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8696 .loc 1 3998 25 view .LVU3049 + 8697 00cc 036D ldr r3, [r0, #80] +3998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8698 .loc 1 3998 13 view .LVU3050 + 8699 00ce 9847 blx r3 + 8700 .LVL604: + 8701 00d0 BBE7 b .L554 + 8702 .LVL605: + 8703 .L556: +4039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8704 .loc 1 4039 12 view .LVU3051 + 8705 00d2 0120 movs r0, #1 + 8706 .LVL606: + 8707 .L552: +4041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8708 .loc 1 4041 1 view .LVU3052 + 8709 00d4 F8BD pop {r3, r4, r5, r6, r7, pc} + 8710 .LVL607: + 8711 .L557: +3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8712 .loc 1 3974 5 discriminator 1 view .LVU3053 + 8713 00d6 0220 movs r0, #2 + 8714 00d8 FCE7 b .L552 + 8715 .L561: + 8716 00da 00BF .align 2 + 8717 .L560: + 8718 00dc 00000000 .word I2C_Slave_ISR_IT + 8719 00e0 00000000 .word I2C_DMAAbort + 8720 .cfi_endproc + 8721 .LFE168: + 8723 .section .text.HAL_I2C_Slave_Seq_Transmit_DMA,"ax",%progbits + 8724 .align 1 + 8725 .global HAL_I2C_Slave_Seq_Transmit_DMA + 8726 .syntax unified + 8727 .thumb + 8728 .thumb_func + 8730 HAL_I2C_Slave_Seq_Transmit_DMA: + 8731 .LVL608: + ARM GAS /tmp/ccSHpINd.s page 337 + + + 8732 .LFB169: +4055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ + 8733 .loc 1 4055 1 is_stmt 1 view -0 + 8734 .cfi_startproc + 8735 @ args = 0, pretend = 0, frame = 0 + 8736 @ frame_needed = 0, uses_anonymous_args = 0 +4055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ + 8737 .loc 1 4055 1 is_stmt 0 view .LVU3055 + 8738 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 8739 .LCFI103: + 8740 .cfi_def_cfa_offset 24 + 8741 .cfi_offset 3, -24 + 8742 .cfi_offset 4, -20 + 8743 .cfi_offset 5, -16 + 8744 .cfi_offset 6, -12 + 8745 .cfi_offset 7, -8 + 8746 .cfi_offset 14, -4 + 8747 0002 0446 mov r4, r0 +4057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 8748 .loc 1 4057 3 is_stmt 1 view .LVU3056 +4058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8749 .loc 1 4058 3 view .LVU3057 +4061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8750 .loc 1 4061 3 view .LVU3058 +4063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8751 .loc 1 4063 3 view .LVU3059 +4063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8752 .loc 1 4063 22 is_stmt 0 view .LVU3060 + 8753 0004 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 8754 .LVL609: +4063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8755 .loc 1 4063 6 view .LVU3061 + 8756 0008 00F02800 and r0, r0, #40 + 8757 000c 2828 cmp r0, #40 + 8758 000e 40F0C080 bne .L572 + 8759 0012 0F46 mov r7, r1 + 8760 0014 1646 mov r6, r2 + 8761 0016 1D46 mov r5, r3 +4065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8762 .loc 1 4065 5 is_stmt 1 view .LVU3062 +4065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8763 .loc 1 4065 8 is_stmt 0 view .LVU3063 + 8764 0018 002A cmp r2, #0 + 8765 001a 18BF it ne + 8766 001c 0029 cmpne r1, #0 + 8767 001e 4FD0 beq .L576 +4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8768 .loc 1 4072 5 is_stmt 1 view .LVU3064 +4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8769 .loc 1 4072 5 view .LVU3065 + 8770 0020 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 8771 .LVL610: +4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8772 .loc 1 4072 5 is_stmt 0 view .LVU3066 + 8773 0024 012B cmp r3, #1 + 8774 0026 00F0B780 beq .L573 +4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 338 + + + 8775 .loc 1 4072 5 is_stmt 1 discriminator 2 view .LVU3067 + 8776 002a 0123 movs r3, #1 + 8777 002c 84F84030 strb r3, [r4, #64] +4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8778 .loc 1 4072 5 discriminator 2 view .LVU3068 +4075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8779 .loc 1 4075 5 view .LVU3069 + 8780 0030 48F20101 movw r1, #32769 + 8781 .LVL611: +4075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8782 .loc 1 4075 5 is_stmt 0 view .LVU3070 + 8783 0034 2046 mov r0, r4 + 8784 0036 FFF7FEFF bl I2C_Disable_IRQ + 8785 .LVL612: +4079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8786 .loc 1 4079 5 is_stmt 1 view .LVU3071 +4079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8787 .loc 1 4079 13 is_stmt 0 view .LVU3072 + 8788 003a 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 8789 003e DBB2 uxtb r3, r3 +4079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8790 .loc 1 4079 8 view .LVU3073 + 8791 0040 2A2B cmp r3, #42 + 8792 0042 42D0 beq .L577 +4104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8793 .loc 1 4104 10 is_stmt 1 view .LVU3074 +4104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8794 .loc 1 4104 18 is_stmt 0 view .LVU3075 + 8795 0044 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 8796 0048 DBB2 uxtb r3, r3 +4104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8797 .loc 1 4104 13 view .LVU3076 + 8798 004a 292B cmp r3, #41 + 8799 004c 59D0 beq .L578 + 8800 .L566: +4129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8801 .loc 1 4129 5 is_stmt 1 view .LVU3077 +4131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8802 .loc 1 4131 5 view .LVU3078 +4131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8803 .loc 1 4131 21 is_stmt 0 view .LVU3079 + 8804 004e 2923 movs r3, #41 + 8805 0050 84F84130 strb r3, [r4, #65] +4132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8806 .loc 1 4132 5 is_stmt 1 view .LVU3080 +4132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8807 .loc 1 4132 21 is_stmt 0 view .LVU3081 + 8808 0054 2023 movs r3, #32 + 8809 0056 84F84230 strb r3, [r4, #66] +4133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8810 .loc 1 4133 5 is_stmt 1 view .LVU3082 +4133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8811 .loc 1 4133 21 is_stmt 0 view .LVU3083 + 8812 005a 0023 movs r3, #0 + 8813 005c 6364 str r3, [r4, #68] +4136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8814 .loc 1 4136 5 is_stmt 1 view .LVU3084 + ARM GAS /tmp/ccSHpINd.s page 339 + + +4136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8815 .loc 1 4136 9 is_stmt 0 view .LVU3085 + 8816 005e 2268 ldr r2, [r4] +4136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8817 .loc 1 4136 19 view .LVU3086 + 8818 0060 5368 ldr r3, [r2, #4] +4136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8819 .loc 1 4136 25 view .LVU3087 + 8820 0062 23F40043 bic r3, r3, #32768 + 8821 0066 5360 str r3, [r2, #4] +4139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 8822 .loc 1 4139 5 is_stmt 1 view .LVU3088 +4139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 8823 .loc 1 4139 23 is_stmt 0 view .LVU3089 + 8824 0068 6762 str r7, [r4, #36] +4140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8825 .loc 1 4140 5 is_stmt 1 view .LVU3090 +4140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8826 .loc 1 4140 23 is_stmt 0 view .LVU3091 + 8827 006a 6685 strh r6, [r4, #42] @ movhi +4141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8828 .loc 1 4141 5 is_stmt 1 view .LVU3092 +4141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8829 .loc 1 4141 29 is_stmt 0 view .LVU3093 + 8830 006c 638D ldrh r3, [r4, #42] +4141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8831 .loc 1 4141 23 view .LVU3094 + 8832 006e 2385 strh r3, [r4, #40] @ movhi +4142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 8833 .loc 1 4142 5 is_stmt 1 view .LVU3095 +4142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 8834 .loc 1 4142 23 is_stmt 0 view .LVU3096 + 8835 0070 E562 str r5, [r4, #44] +4143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8836 .loc 1 4143 5 is_stmt 1 view .LVU3097 +4143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8837 .loc 1 4143 23 is_stmt 0 view .LVU3098 + 8838 0072 4A4B ldr r3, .L579 + 8839 0074 6363 str r3, [r4, #52] +4145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8840 .loc 1 4145 5 is_stmt 1 view .LVU3099 +4145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8841 .loc 1 4145 13 is_stmt 0 view .LVU3100 + 8842 0076 A36B ldr r3, [r4, #56] +4145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8843 .loc 1 4145 8 view .LVU3101 + 8844 0078 002B cmp r3, #0 + 8845 007a 59D0 beq .L567 +4148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8846 .loc 1 4148 7 is_stmt 1 view .LVU3102 +4148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8847 .loc 1 4148 38 is_stmt 0 view .LVU3103 + 8848 007c 484A ldr r2, .L579+4 + 8849 007e DA63 str r2, [r3, #60] +4151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8850 .loc 1 4151 7 is_stmt 1 view .LVU3104 +4151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 340 + + + 8851 .loc 1 4151 11 is_stmt 0 view .LVU3105 + 8852 0080 A36B ldr r3, [r4, #56] +4151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8853 .loc 1 4151 39 view .LVU3106 + 8854 0082 484A ldr r2, .L579+8 + 8855 0084 DA64 str r2, [r3, #76] +4154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 8856 .loc 1 4154 7 is_stmt 1 view .LVU3107 +4154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 8857 .loc 1 4154 11 is_stmt 0 view .LVU3108 + 8858 0086 A26B ldr r2, [r4, #56] +4154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 8859 .loc 1 4154 42 view .LVU3109 + 8860 0088 0023 movs r3, #0 + 8861 008a 1364 str r3, [r2, #64] +4155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8862 .loc 1 4155 7 is_stmt 1 view .LVU3110 +4155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8863 .loc 1 4155 11 is_stmt 0 view .LVU3111 + 8864 008c A26B ldr r2, [r4, #56] +4155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8865 .loc 1 4155 39 view .LVU3112 + 8866 008e 1365 str r3, [r2, #80] +4158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 8867 .loc 1 4158 7 is_stmt 1 view .LVU3113 +4158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 8868 .loc 1 4158 86 is_stmt 0 view .LVU3114 + 8869 0090 2268 ldr r2, [r4] +4158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize); + 8870 .loc 1 4158 23 view .LVU3115 + 8871 0092 238D ldrh r3, [r4, #40] + 8872 0094 2832 adds r2, r2, #40 + 8873 0096 3946 mov r1, r7 + 8874 0098 A06B ldr r0, [r4, #56] + 8875 009a FFF7FEFF bl HAL_DMA_Start_IT + 8876 .LVL613: +4176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8877 .loc 1 4176 5 is_stmt 1 view .LVU3116 +4176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8878 .loc 1 4176 8 is_stmt 0 view .LVU3117 + 8879 009e 0546 mov r5, r0 + 8880 .LVL614: +4176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8881 .loc 1 4176 8 view .LVU3118 + 8882 00a0 0028 cmp r0, #0 + 8883 00a2 53D0 beq .L568 +4187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8884 .loc 1 4187 7 is_stmt 1 view .LVU3119 +4187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8885 .loc 1 4187 23 is_stmt 0 view .LVU3120 + 8886 00a4 2823 movs r3, #40 + 8887 00a6 84F84130 strb r3, [r4, #65] +4188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8888 .loc 1 4188 7 is_stmt 1 view .LVU3121 +4188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8889 .loc 1 4188 23 is_stmt 0 view .LVU3122 + 8890 00aa 0022 movs r2, #0 + ARM GAS /tmp/ccSHpINd.s page 341 + + + 8891 00ac 84F84220 strb r2, [r4, #66] +4191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8892 .loc 1 4191 7 is_stmt 1 view .LVU3123 +4191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8893 .loc 1 4191 11 is_stmt 0 view .LVU3124 + 8894 00b0 636C ldr r3, [r4, #68] +4191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8895 .loc 1 4191 23 view .LVU3125 + 8896 00b2 43F01003 orr r3, r3, #16 + 8897 00b6 6364 str r3, [r4, #68] +4194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8898 .loc 1 4194 7 is_stmt 1 view .LVU3126 +4194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8899 .loc 1 4194 7 view .LVU3127 + 8900 00b8 84F84020 strb r2, [r4, #64] +4194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8901 .loc 1 4194 7 view .LVU3128 +4196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8902 .loc 1 4196 7 view .LVU3129 +4196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8903 .loc 1 4196 14 is_stmt 0 view .LVU3130 + 8904 00bc 0125 movs r5, #1 + 8905 00be 69E0 b .L563 + 8906 .LVL615: + 8907 .L576: +4067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 8908 .loc 1 4067 7 is_stmt 1 view .LVU3131 +4067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 8909 .loc 1 4067 23 is_stmt 0 view .LVU3132 + 8910 00c0 4FF40073 mov r3, #512 + 8911 .LVL616: +4067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 8912 .loc 1 4067 23 view .LVU3133 + 8913 00c4 6364 str r3, [r4, #68] +4068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8914 .loc 1 4068 7 is_stmt 1 view .LVU3134 +4068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8915 .loc 1 4068 15 is_stmt 0 view .LVU3135 + 8916 00c6 0125 movs r5, #1 + 8917 .LVL617: +4068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8918 .loc 1 4068 15 view .LVU3136 + 8919 00c8 64E0 b .L563 + 8920 .LVL618: + 8921 .L577: +4082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8922 .loc 1 4082 7 is_stmt 1 view .LVU3137 + 8923 00ca 0221 movs r1, #2 + 8924 00cc 2046 mov r0, r4 + 8925 00ce FFF7FEFF bl I2C_Disable_IRQ + 8926 .LVL619: +4084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8927 .loc 1 4084 7 view .LVU3138 +4084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8928 .loc 1 4084 16 is_stmt 0 view .LVU3139 + 8929 00d2 2368 ldr r3, [r4] +4084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 342 + + + 8930 .loc 1 4084 26 view .LVU3140 + 8931 00d4 1A68 ldr r2, [r3] +4084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8932 .loc 1 4084 10 view .LVU3141 + 8933 00d6 12F4004F tst r2, #32768 + 8934 00da B8D0 beq .L566 +4087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8935 .loc 1 4087 9 is_stmt 1 view .LVU3142 +4087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8936 .loc 1 4087 17 is_stmt 0 view .LVU3143 + 8937 00dc E26B ldr r2, [r4, #60] +4087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8938 .loc 1 4087 12 view .LVU3144 + 8939 00de 002A cmp r2, #0 + 8940 00e0 B5D0 beq .L566 +4089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8941 .loc 1 4089 11 is_stmt 1 view .LVU3145 +4089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8942 .loc 1 4089 25 is_stmt 0 view .LVU3146 + 8943 00e2 1A68 ldr r2, [r3] +4089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8944 .loc 1 4089 31 view .LVU3147 + 8945 00e4 22F40042 bic r2, r2, #32768 + 8946 00e8 1A60 str r2, [r3] +4093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8947 .loc 1 4093 11 is_stmt 1 view .LVU3148 +4093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8948 .loc 1 4093 15 is_stmt 0 view .LVU3149 + 8949 00ea E36B ldr r3, [r4, #60] +4093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8950 .loc 1 4093 43 view .LVU3150 + 8951 00ec 2E4A ldr r2, .L579+12 + 8952 00ee 1A65 str r2, [r3, #80] +4096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8953 .loc 1 4096 11 is_stmt 1 view .LVU3151 +4096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8954 .loc 1 4096 15 is_stmt 0 view .LVU3152 + 8955 00f0 E06B ldr r0, [r4, #60] + 8956 00f2 FFF7FEFF bl HAL_DMA_Abort_IT + 8957 .LVL620: +4096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8958 .loc 1 4096 14 discriminator 1 view .LVU3153 + 8959 00f6 0028 cmp r0, #0 + 8960 00f8 A9D0 beq .L566 +4099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8961 .loc 1 4099 13 is_stmt 1 view .LVU3154 +4099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8962 .loc 1 4099 17 is_stmt 0 view .LVU3155 + 8963 00fa E06B ldr r0, [r4, #60] +4099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8964 .loc 1 4099 25 view .LVU3156 + 8965 00fc 036D ldr r3, [r0, #80] +4099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 8966 .loc 1 4099 13 view .LVU3157 + 8967 00fe 9847 blx r3 + 8968 .LVL621: + 8969 0100 A5E7 b .L566 + ARM GAS /tmp/ccSHpINd.s page 343 + + + 8970 .L578: +4106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8971 .loc 1 4106 7 is_stmt 1 view .LVU3158 +4106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8972 .loc 1 4106 16 is_stmt 0 view .LVU3159 + 8973 0102 2368 ldr r3, [r4] +4106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8974 .loc 1 4106 26 view .LVU3160 + 8975 0104 1A68 ldr r2, [r3] +4106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8976 .loc 1 4106 10 view .LVU3161 + 8977 0106 12F4804F tst r2, #16384 + 8978 010a A0D0 beq .L566 +4108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8979 .loc 1 4108 9 is_stmt 1 view .LVU3162 +4108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8980 .loc 1 4108 23 is_stmt 0 view .LVU3163 + 8981 010c 1A68 ldr r2, [r3] +4108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8982 .loc 1 4108 29 view .LVU3164 + 8983 010e 22F48042 bic r2, r2, #16384 + 8984 0112 1A60 str r2, [r3] +4111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8985 .loc 1 4111 9 is_stmt 1 view .LVU3165 +4111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8986 .loc 1 4111 17 is_stmt 0 view .LVU3166 + 8987 0114 A36B ldr r3, [r4, #56] +4111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8988 .loc 1 4111 12 view .LVU3167 + 8989 0116 002B cmp r3, #0 + 8990 0118 99D0 beq .L566 +4115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8991 .loc 1 4115 11 is_stmt 1 view .LVU3168 +4115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 8992 .loc 1 4115 43 is_stmt 0 view .LVU3169 + 8993 011a 234A ldr r2, .L579+12 + 8994 011c 1A65 str r2, [r3, #80] +4118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8995 .loc 1 4118 11 is_stmt 1 view .LVU3170 +4118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 8996 .loc 1 4118 15 is_stmt 0 view .LVU3171 + 8997 011e A06B ldr r0, [r4, #56] + 8998 0120 FFF7FEFF bl HAL_DMA_Abort_IT + 8999 .LVL622: +4118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9000 .loc 1 4118 14 discriminator 1 view .LVU3172 + 9001 0124 0028 cmp r0, #0 + 9002 0126 92D0 beq .L566 +4121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9003 .loc 1 4121 13 is_stmt 1 view .LVU3173 +4121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9004 .loc 1 4121 17 is_stmt 0 view .LVU3174 + 9005 0128 A06B ldr r0, [r4, #56] +4121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9006 .loc 1 4121 25 view .LVU3175 + 9007 012a 036D ldr r3, [r0, #80] +4121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + ARM GAS /tmp/ccSHpINd.s page 344 + + + 9008 .loc 1 4121 13 view .LVU3176 + 9009 012c 9847 blx r3 + 9010 .LVL623: + 9011 012e 8EE7 b .L566 + 9012 .L567: +4164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9013 .loc 1 4164 7 is_stmt 1 view .LVU3177 +4164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9014 .loc 1 4164 23 is_stmt 0 view .LVU3178 + 9015 0130 2823 movs r3, #40 + 9016 0132 84F84130 strb r3, [r4, #65] +4165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9017 .loc 1 4165 7 is_stmt 1 view .LVU3179 +4165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9018 .loc 1 4165 23 is_stmt 0 view .LVU3180 + 9019 0136 0022 movs r2, #0 + 9020 0138 84F84220 strb r2, [r4, #66] +4168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9021 .loc 1 4168 7 is_stmt 1 view .LVU3181 +4168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9022 .loc 1 4168 11 is_stmt 0 view .LVU3182 + 9023 013c 636C ldr r3, [r4, #68] +4168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9024 .loc 1 4168 23 view .LVU3183 + 9025 013e 43F08003 orr r3, r3, #128 + 9026 0142 6364 str r3, [r4, #68] +4171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9027 .loc 1 4171 7 is_stmt 1 view .LVU3184 +4171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9028 .loc 1 4171 7 view .LVU3185 + 9029 0144 84F84020 strb r2, [r4, #64] +4171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9030 .loc 1 4171 7 view .LVU3186 +4173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9031 .loc 1 4173 7 view .LVU3187 +4173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9032 .loc 1 4173 14 is_stmt 0 view .LVU3188 + 9033 0148 0125 movs r5, #1 + 9034 .LVL624: +4173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9035 .loc 1 4173 14 view .LVU3189 + 9036 014a 23E0 b .L563 + 9037 .LVL625: + 9038 .L568: +4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9039 .loc 1 4179 7 is_stmt 1 view .LVU3190 +4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9040 .loc 1 4179 11 is_stmt 0 view .LVU3191 + 9041 014c 638D ldrh r3, [r4, #42] + 9042 014e 9BB2 uxth r3, r3 +4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9043 .loc 1 4179 30 view .LVU3192 + 9044 0150 228D ldrh r2, [r4, #40] +4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9045 .loc 1 4179 23 view .LVU3193 + 9046 0152 9B1A subs r3, r3, r2 + 9047 0154 9BB2 uxth r3, r3 + ARM GAS /tmp/ccSHpINd.s page 345 + + + 9048 0156 6385 strh r3, [r4, #42] @ movhi +4182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9049 .loc 1 4182 7 is_stmt 1 view .LVU3194 +4182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9050 .loc 1 4182 22 is_stmt 0 view .LVU3195 + 9051 0158 0023 movs r3, #0 + 9052 015a 2385 strh r3, [r4, #40] @ movhi +4199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + 9053 .loc 1 4199 5 is_stmt 1 view .LVU3196 +4199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + 9054 .loc 1 4199 11 is_stmt 0 view .LVU3197 + 9055 015c 2268 ldr r2, [r4] + 9056 015e 9369 ldr r3, [r2, #24] + 9057 0160 03F00803 and r3, r3, #8 + 9058 .LVL626: +4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9059 .loc 1 4200 5 is_stmt 1 view .LVU3198 +4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9060 .loc 1 4200 10 is_stmt 0 view .LVU3199 + 9061 0164 9169 ldr r1, [r2, #24] +4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9062 .loc 1 4200 8 view .LVU3200 + 9063 0166 11F4803F tst r1, #65536 + 9064 016a 0DD1 bne .L570 + 9065 .LVL627: + 9066 .L571: +4208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9067 .loc 1 4208 5 is_stmt 1 view .LVU3201 +4208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9068 .loc 1 4208 5 view .LVU3202 + 9069 016c 0023 movs r3, #0 + 9070 016e 84F84030 strb r3, [r4, #64] +4208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9071 .loc 1 4208 5 view .LVU3203 +4211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9072 .loc 1 4211 5 view .LVU3204 +4211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9073 .loc 1 4211 9 is_stmt 0 view .LVU3205 + 9074 0172 2268 ldr r2, [r4] +4211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9075 .loc 1 4211 19 view .LVU3206 + 9076 0174 1368 ldr r3, [r2] +4211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9077 .loc 1 4211 25 view .LVU3207 + 9078 0176 43F48043 orr r3, r3, #16384 + 9079 017a 1360 str r3, [r2] +4217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9080 .loc 1 4217 5 is_stmt 1 view .LVU3208 + 9081 017c 4FF40041 mov r1, #32768 + 9082 0180 2046 mov r0, r4 + 9083 .LVL628: +4217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9084 .loc 1 4217 5 is_stmt 0 view .LVU3209 + 9085 0182 FFF7FEFF bl I2C_Enable_IRQ + 9086 .LVL629: +4219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9087 .loc 1 4219 5 is_stmt 1 view .LVU3210 + ARM GAS /tmp/ccSHpINd.s page 346 + + +4219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9088 .loc 1 4219 12 is_stmt 0 view .LVU3211 + 9089 0186 05E0 b .L563 + 9090 .LVL630: + 9091 .L570: +4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9092 .loc 1 4200 54 discriminator 1 view .LVU3212 + 9093 0188 002B cmp r3, #0 + 9094 018a EFD0 beq .L571 +4204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9095 .loc 1 4204 7 is_stmt 1 view .LVU3213 + 9096 018c 0823 movs r3, #8 + 9097 .LVL631: +4204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9098 .loc 1 4204 7 is_stmt 0 view .LVU3214 + 9099 018e D361 str r3, [r2, #28] + 9100 0190 ECE7 b .L571 + 9101 .LVL632: + 9102 .L572: +4223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9103 .loc 1 4223 12 view .LVU3215 + 9104 0192 0125 movs r5, #1 + 9105 .LVL633: + 9106 .L563: +4225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9107 .loc 1 4225 1 view .LVU3216 + 9108 0194 2846 mov r0, r5 + 9109 0196 F8BD pop {r3, r4, r5, r6, r7, pc} + 9110 .LVL634: + 9111 .L573: +4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9112 .loc 1 4072 5 discriminator 1 view .LVU3217 + 9113 0198 0225 movs r5, #2 + 9114 .LVL635: +4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9115 .loc 1 4072 5 discriminator 1 view .LVU3218 + 9116 019a FBE7 b .L563 + 9117 .L580: + 9118 .align 2 + 9119 .L579: + 9120 019c 00000000 .word I2C_Slave_ISR_DMA + 9121 01a0 00000000 .word I2C_DMASlaveTransmitCplt + 9122 01a4 00000000 .word I2C_DMAError + 9123 01a8 00000000 .word I2C_DMAAbort + 9124 .cfi_endproc + 9125 .LFE169: + 9127 .section .text.HAL_I2C_Slave_Seq_Receive_IT,"ax",%progbits + 9128 .align 1 + 9129 .global HAL_I2C_Slave_Seq_Receive_IT + 9130 .syntax unified + 9131 .thumb + 9132 .thumb_func + 9134 HAL_I2C_Slave_Seq_Receive_IT: + 9135 .LVL636: + 9136 .LFB170: +4239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ + 9137 .loc 1 4239 1 is_stmt 1 view -0 + ARM GAS /tmp/ccSHpINd.s page 347 + + + 9138 .cfi_startproc + 9139 @ args = 0, pretend = 0, frame = 0 + 9140 @ frame_needed = 0, uses_anonymous_args = 0 +4239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ + 9141 .loc 1 4239 1 is_stmt 0 view .LVU3220 + 9142 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 9143 .LCFI104: + 9144 .cfi_def_cfa_offset 24 + 9145 .cfi_offset 3, -24 + 9146 .cfi_offset 4, -20 + 9147 .cfi_offset 5, -16 + 9148 .cfi_offset 6, -12 + 9149 .cfi_offset 7, -8 + 9150 .cfi_offset 14, -4 + 9151 0002 0446 mov r4, r0 +4241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9152 .loc 1 4241 3 is_stmt 1 view .LVU3221 +4244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9153 .loc 1 4244 3 view .LVU3222 +4246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9154 .loc 1 4246 3 view .LVU3223 +4246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9155 .loc 1 4246 22 is_stmt 0 view .LVU3224 + 9156 0004 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 9157 .LVL637: +4246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9158 .loc 1 4246 6 view .LVU3225 + 9159 0008 00F02800 and r0, r0, #40 + 9160 000c 2828 cmp r0, #40 + 9161 000e 60D1 bne .L586 + 9162 0010 0F46 mov r7, r1 + 9163 0012 1646 mov r6, r2 + 9164 0014 1D46 mov r5, r3 +4248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9165 .loc 1 4248 5 is_stmt 1 view .LVU3226 +4248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9166 .loc 1 4248 8 is_stmt 0 view .LVU3227 + 9167 0016 002A cmp r2, #0 + 9168 0018 18BF it ne + 9169 001a 0029 cmpne r1, #0 + 9170 001c 04D1 bne .L583 +4250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 9171 .loc 1 4250 7 is_stmt 1 view .LVU3228 +4250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 9172 .loc 1 4250 23 is_stmt 0 view .LVU3229 + 9173 001e 4FF40073 mov r3, #512 + 9174 .LVL638: +4250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 9175 .loc 1 4250 23 view .LVU3230 + 9176 0022 6364 str r3, [r4, #68] +4251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9177 .loc 1 4251 7 is_stmt 1 view .LVU3231 +4251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9178 .loc 1 4251 15 is_stmt 0 view .LVU3232 + 9179 0024 0120 movs r0, #1 + 9180 0026 55E0 b .L582 + 9181 .LVL639: + ARM GAS /tmp/ccSHpINd.s page 348 + + + 9182 .L583: +4255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9183 .loc 1 4255 5 is_stmt 1 view .LVU3233 + 9184 0028 48F20201 movw r1, #32770 + 9185 .LVL640: +4255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9186 .loc 1 4255 5 is_stmt 0 view .LVU3234 + 9187 002c 2046 mov r0, r4 + 9188 002e FFF7FEFF bl I2C_Disable_IRQ + 9189 .LVL641: +4258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9190 .loc 1 4258 5 is_stmt 1 view .LVU3235 +4258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9191 .loc 1 4258 5 view .LVU3236 + 9192 0032 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 9193 0036 012B cmp r3, #1 + 9194 0038 4DD0 beq .L587 +4258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9195 .loc 1 4258 5 discriminator 2 view .LVU3237 + 9196 003a 0123 movs r3, #1 + 9197 003c 84F84030 strb r3, [r4, #64] +4258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9198 .loc 1 4258 5 discriminator 2 view .LVU3238 +4262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9199 .loc 1 4262 5 view .LVU3239 +4262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9200 .loc 1 4262 13 is_stmt 0 view .LVU3240 + 9201 0040 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 9202 0044 DBB2 uxtb r3, r3 +4262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9203 .loc 1 4262 8 view .LVU3241 + 9204 0046 292B cmp r3, #41 + 9205 0048 28D0 beq .L589 + 9206 .L584: +4288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 9207 .loc 1 4288 5 is_stmt 1 view .LVU3242 +4288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 9208 .loc 1 4288 21 is_stmt 0 view .LVU3243 + 9209 004a 2A23 movs r3, #42 + 9210 004c 84F84130 strb r3, [r4, #65] +4289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 9211 .loc 1 4289 5 is_stmt 1 view .LVU3244 +4289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 9212 .loc 1 4289 21 is_stmt 0 view .LVU3245 + 9213 0050 2023 movs r3, #32 + 9214 0052 84F84230 strb r3, [r4, #66] +4290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9215 .loc 1 4290 5 is_stmt 1 view .LVU3246 +4290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9216 .loc 1 4290 21 is_stmt 0 view .LVU3247 + 9217 0056 0023 movs r3, #0 + 9218 0058 6364 str r3, [r4, #68] +4293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9219 .loc 1 4293 5 is_stmt 1 view .LVU3248 +4293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9220 .loc 1 4293 9 is_stmt 0 view .LVU3249 + 9221 005a 2268 ldr r2, [r4] + ARM GAS /tmp/ccSHpINd.s page 349 + + +4293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9222 .loc 1 4293 19 view .LVU3250 + 9223 005c 5368 ldr r3, [r2, #4] +4293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9224 .loc 1 4293 25 view .LVU3251 + 9225 005e 23F40043 bic r3, r3, #32768 + 9226 0062 5360 str r3, [r2, #4] +4296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 9227 .loc 1 4296 5 is_stmt 1 view .LVU3252 +4296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 9228 .loc 1 4296 23 is_stmt 0 view .LVU3253 + 9229 0064 6762 str r7, [r4, #36] +4297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 9230 .loc 1 4297 5 is_stmt 1 view .LVU3254 +4297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 9231 .loc 1 4297 23 is_stmt 0 view .LVU3255 + 9232 0066 6685 strh r6, [r4, #42] @ movhi +4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 9233 .loc 1 4298 5 is_stmt 1 view .LVU3256 +4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 9234 .loc 1 4298 29 is_stmt 0 view .LVU3257 + 9235 0068 638D ldrh r3, [r4, #42] +4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 9236 .loc 1 4298 23 view .LVU3258 + 9237 006a 2385 strh r3, [r4, #40] @ movhi +4299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 9238 .loc 1 4299 5 is_stmt 1 view .LVU3259 +4299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 9239 .loc 1 4299 23 is_stmt 0 view .LVU3260 + 9240 006c E562 str r5, [r4, #44] +4300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9241 .loc 1 4300 5 is_stmt 1 view .LVU3261 +4300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9242 .loc 1 4300 23 is_stmt 0 view .LVU3262 + 9243 006e 1B4B ldr r3, .L590 + 9244 0070 6363 str r3, [r4, #52] +4302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + 9245 .loc 1 4302 5 is_stmt 1 view .LVU3263 +4302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + 9246 .loc 1 4302 11 is_stmt 0 view .LVU3264 + 9247 0072 2268 ldr r2, [r4] + 9248 0074 9369 ldr r3, [r2, #24] + 9249 0076 03F00803 and r3, r3, #8 + 9250 .LVL642: +4303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9251 .loc 1 4303 5 is_stmt 1 view .LVU3265 +4303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9252 .loc 1 4303 10 is_stmt 0 view .LVU3266 + 9253 007a 9169 ldr r1, [r2, #24] +4303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9254 .loc 1 4303 8 view .LVU3267 + 9255 007c 11F4803F tst r1, #65536 + 9256 0080 02D1 bne .L585 +4303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9257 .loc 1 4303 55 discriminator 1 view .LVU3268 + 9258 0082 0BB1 cbz r3, .L585 +4307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + ARM GAS /tmp/ccSHpINd.s page 350 + + + 9259 .loc 1 4307 7 is_stmt 1 view .LVU3269 + 9260 0084 0823 movs r3, #8 + 9261 .LVL643: +4307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9262 .loc 1 4307 7 is_stmt 0 view .LVU3270 + 9263 0086 D361 str r3, [r2, #28] + 9264 .L585: +4311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9265 .loc 1 4311 5 is_stmt 1 view .LVU3271 +4311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9266 .loc 1 4311 5 view .LVU3272 + 9267 0088 0025 movs r5, #0 + 9268 .LVL644: +4311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9269 .loc 1 4311 5 is_stmt 0 view .LVU3273 + 9270 008a 84F84050 strb r5, [r4, #64] +4311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9271 .loc 1 4311 5 is_stmt 1 view .LVU3274 +4317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9272 .loc 1 4317 5 view .LVU3275 + 9273 008e 48F20201 movw r1, #32770 + 9274 0092 2046 mov r0, r4 + 9275 0094 FFF7FEFF bl I2C_Enable_IRQ + 9276 .LVL645: +4319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9277 .loc 1 4319 5 view .LVU3276 +4319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9278 .loc 1 4319 12 is_stmt 0 view .LVU3277 + 9279 0098 2846 mov r0, r5 + 9280 009a 1BE0 b .L582 + 9281 .LVL646: + 9282 .L589: +4265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9283 .loc 1 4265 7 is_stmt 1 view .LVU3278 + 9284 009c 0121 movs r1, #1 + 9285 009e 2046 mov r0, r4 + 9286 00a0 FFF7FEFF bl I2C_Disable_IRQ + 9287 .LVL647: +4267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9288 .loc 1 4267 7 view .LVU3279 +4267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9289 .loc 1 4267 16 is_stmt 0 view .LVU3280 + 9290 00a4 2368 ldr r3, [r4] +4267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9291 .loc 1 4267 26 view .LVU3281 + 9292 00a6 1A68 ldr r2, [r3] +4267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9293 .loc 1 4267 10 view .LVU3282 + 9294 00a8 12F4804F tst r2, #16384 + 9295 00ac CDD0 beq .L584 +4269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9296 .loc 1 4269 9 is_stmt 1 view .LVU3283 +4269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9297 .loc 1 4269 23 is_stmt 0 view .LVU3284 + 9298 00ae 1A68 ldr r2, [r3] +4269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9299 .loc 1 4269 29 view .LVU3285 + ARM GAS /tmp/ccSHpINd.s page 351 + + + 9300 00b0 22F48042 bic r2, r2, #16384 + 9301 00b4 1A60 str r2, [r3] +4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9302 .loc 1 4272 9 is_stmt 1 view .LVU3286 +4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9303 .loc 1 4272 17 is_stmt 0 view .LVU3287 + 9304 00b6 A36B ldr r3, [r4, #56] +4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9305 .loc 1 4272 12 view .LVU3288 + 9306 00b8 002B cmp r3, #0 + 9307 00ba C6D0 beq .L584 +4276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9308 .loc 1 4276 11 is_stmt 1 view .LVU3289 +4276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9309 .loc 1 4276 43 is_stmt 0 view .LVU3290 + 9310 00bc 084A ldr r2, .L590+4 + 9311 00be 1A65 str r2, [r3, #80] +4279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9312 .loc 1 4279 11 is_stmt 1 view .LVU3291 +4279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9313 .loc 1 4279 15 is_stmt 0 view .LVU3292 + 9314 00c0 A06B ldr r0, [r4, #56] + 9315 00c2 FFF7FEFF bl HAL_DMA_Abort_IT + 9316 .LVL648: +4279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9317 .loc 1 4279 14 discriminator 1 view .LVU3293 + 9318 00c6 0028 cmp r0, #0 + 9319 00c8 BFD0 beq .L584 +4282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9320 .loc 1 4282 13 is_stmt 1 view .LVU3294 +4282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9321 .loc 1 4282 17 is_stmt 0 view .LVU3295 + 9322 00ca A06B ldr r0, [r4, #56] +4282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9323 .loc 1 4282 25 view .LVU3296 + 9324 00cc 036D ldr r3, [r0, #80] +4282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9325 .loc 1 4282 13 view .LVU3297 + 9326 00ce 9847 blx r3 + 9327 .LVL649: + 9328 00d0 BBE7 b .L584 + 9329 .LVL650: + 9330 .L586: +4323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9331 .loc 1 4323 12 view .LVU3298 + 9332 00d2 0120 movs r0, #1 + 9333 .LVL651: + 9334 .L582: +4325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9335 .loc 1 4325 1 view .LVU3299 + 9336 00d4 F8BD pop {r3, r4, r5, r6, r7, pc} + 9337 .LVL652: + 9338 .L587: +4258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9339 .loc 1 4258 5 discriminator 1 view .LVU3300 + 9340 00d6 0220 movs r0, #2 + 9341 00d8 FCE7 b .L582 + ARM GAS /tmp/ccSHpINd.s page 352 + + + 9342 .L591: + 9343 00da 00BF .align 2 + 9344 .L590: + 9345 00dc 00000000 .word I2C_Slave_ISR_IT + 9346 00e0 00000000 .word I2C_DMAAbort + 9347 .cfi_endproc + 9348 .LFE170: + 9350 .section .text.HAL_I2C_Slave_Seq_Receive_DMA,"ax",%progbits + 9351 .align 1 + 9352 .global HAL_I2C_Slave_Seq_Receive_DMA + 9353 .syntax unified + 9354 .thumb + 9355 .thumb_func + 9357 HAL_I2C_Slave_Seq_Receive_DMA: + 9358 .LVL653: + 9359 .LFB171: +4339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ + 9360 .loc 1 4339 1 is_stmt 1 view -0 + 9361 .cfi_startproc + 9362 @ args = 0, pretend = 0, frame = 0 + 9363 @ frame_needed = 0, uses_anonymous_args = 0 +4339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ + 9364 .loc 1 4339 1 is_stmt 0 view .LVU3302 + 9365 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 9366 .LCFI105: + 9367 .cfi_def_cfa_offset 24 + 9368 .cfi_offset 3, -24 + 9369 .cfi_offset 4, -20 + 9370 .cfi_offset 5, -16 + 9371 .cfi_offset 6, -12 + 9372 .cfi_offset 7, -8 + 9373 .cfi_offset 14, -4 + 9374 0002 0446 mov r4, r0 +4341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 9375 .loc 1 4341 3 is_stmt 1 view .LVU3303 +4342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9376 .loc 1 4342 3 view .LVU3304 +4345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9377 .loc 1 4345 3 view .LVU3305 +4347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9378 .loc 1 4347 3 view .LVU3306 +4347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9379 .loc 1 4347 22 is_stmt 0 view .LVU3307 + 9380 0004 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 9381 .LVL654: +4347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9382 .loc 1 4347 6 view .LVU3308 + 9383 0008 00F02800 and r0, r0, #40 + 9384 000c 2828 cmp r0, #40 + 9385 000e 40F0C080 bne .L602 + 9386 0012 0F46 mov r7, r1 + 9387 0014 1646 mov r6, r2 + 9388 0016 1D46 mov r5, r3 +4349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9389 .loc 1 4349 5 is_stmt 1 view .LVU3309 +4349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9390 .loc 1 4349 8 is_stmt 0 view .LVU3310 + ARM GAS /tmp/ccSHpINd.s page 353 + + + 9391 0018 002A cmp r2, #0 + 9392 001a 18BF it ne + 9393 001c 0029 cmpne r1, #0 + 9394 001e 04D1 bne .L594 +4351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 9395 .loc 1 4351 7 is_stmt 1 view .LVU3311 +4351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 9396 .loc 1 4351 23 is_stmt 0 view .LVU3312 + 9397 0020 4FF40073 mov r3, #512 + 9398 .LVL655: +4351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return HAL_ERROR; + 9399 .loc 1 4351 23 view .LVU3313 + 9400 0024 6364 str r3, [r4, #68] +4352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9401 .loc 1 4352 7 is_stmt 1 view .LVU3314 +4352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9402 .loc 1 4352 15 is_stmt 0 view .LVU3315 + 9403 0026 0125 movs r5, #1 + 9404 .LVL656: +4352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9405 .loc 1 4352 15 view .LVU3316 + 9406 0028 B4E0 b .L593 + 9407 .LVL657: + 9408 .L594: +4356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9409 .loc 1 4356 5 is_stmt 1 view .LVU3317 + 9410 002a 48F20201 movw r1, #32770 + 9411 .LVL658: +4356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9412 .loc 1 4356 5 is_stmt 0 view .LVU3318 + 9413 002e 2046 mov r0, r4 + 9414 0030 FFF7FEFF bl I2C_Disable_IRQ + 9415 .LVL659: +4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9416 .loc 1 4359 5 is_stmt 1 view .LVU3319 +4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9417 .loc 1 4359 5 view .LVU3320 + 9418 0034 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 9419 0038 012B cmp r3, #1 + 9420 003a 00F0AD80 beq .L603 +4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9421 .loc 1 4359 5 discriminator 2 view .LVU3321 + 9422 003e 0123 movs r3, #1 + 9423 0040 84F84030 strb r3, [r4, #64] +4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9424 .loc 1 4359 5 discriminator 2 view .LVU3322 +4363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9425 .loc 1 4363 5 view .LVU3323 +4363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9426 .loc 1 4363 13 is_stmt 0 view .LVU3324 + 9427 0044 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 9428 0048 DBB2 uxtb r3, r3 +4363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9429 .loc 1 4363 8 view .LVU3325 + 9430 004a 292B cmp r3, #41 + 9431 004c 3DD0 beq .L606 +4388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 354 + + + 9432 .loc 1 4388 10 is_stmt 1 view .LVU3326 +4388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9433 .loc 1 4388 18 is_stmt 0 view .LVU3327 + 9434 004e 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 9435 0052 DBB2 uxtb r3, r3 +4388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9436 .loc 1 4388 13 view .LVU3328 + 9437 0054 2A2B cmp r3, #42 + 9438 0056 54D0 beq .L607 + 9439 .L596: +4413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9440 .loc 1 4413 5 is_stmt 1 view .LVU3329 +4415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 9441 .loc 1 4415 5 view .LVU3330 +4415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 9442 .loc 1 4415 21 is_stmt 0 view .LVU3331 + 9443 0058 2A23 movs r3, #42 + 9444 005a 84F84130 strb r3, [r4, #65] +4416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 9445 .loc 1 4416 5 is_stmt 1 view .LVU3332 +4416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 9446 .loc 1 4416 21 is_stmt 0 view .LVU3333 + 9447 005e 2023 movs r3, #32 + 9448 0060 84F84230 strb r3, [r4, #66] +4417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9449 .loc 1 4417 5 is_stmt 1 view .LVU3334 +4417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9450 .loc 1 4417 21 is_stmt 0 view .LVU3335 + 9451 0064 0023 movs r3, #0 + 9452 0066 6364 str r3, [r4, #68] +4420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9453 .loc 1 4420 5 is_stmt 1 view .LVU3336 +4420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9454 .loc 1 4420 9 is_stmt 0 view .LVU3337 + 9455 0068 2268 ldr r2, [r4] +4420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9456 .loc 1 4420 19 view .LVU3338 + 9457 006a 5368 ldr r3, [r2, #4] +4420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9458 .loc 1 4420 25 view .LVU3339 + 9459 006c 23F40043 bic r3, r3, #32768 + 9460 0070 5360 str r3, [r2, #4] +4423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 9461 .loc 1 4423 5 is_stmt 1 view .LVU3340 +4423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = Size; + 9462 .loc 1 4423 23 is_stmt 0 view .LVU3341 + 9463 0072 6762 str r7, [r4, #36] +4424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 9464 .loc 1 4424 5 is_stmt 1 view .LVU3342 +4424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 9465 .loc 1 4424 23 is_stmt 0 view .LVU3343 + 9466 0074 6685 strh r6, [r4, #42] @ movhi +4425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 9467 .loc 1 4425 5 is_stmt 1 view .LVU3344 +4425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 9468 .loc 1 4425 29 is_stmt 0 view .LVU3345 + 9469 0076 638D ldrh r3, [r4, #42] + ARM GAS /tmp/ccSHpINd.s page 355 + + +4425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 9470 .loc 1 4425 23 view .LVU3346 + 9471 0078 2385 strh r3, [r4, #40] @ movhi +4426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 9472 .loc 1 4426 5 is_stmt 1 view .LVU3347 +4426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 9473 .loc 1 4426 23 is_stmt 0 view .LVU3348 + 9474 007a E562 str r5, [r4, #44] +4427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9475 .loc 1 4427 5 is_stmt 1 view .LVU3349 +4427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9476 .loc 1 4427 23 is_stmt 0 view .LVU3350 + 9477 007c 474B ldr r3, .L608 + 9478 007e 6363 str r3, [r4, #52] +4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9479 .loc 1 4429 5 is_stmt 1 view .LVU3351 +4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9480 .loc 1 4429 13 is_stmt 0 view .LVU3352 + 9481 0080 E36B ldr r3, [r4, #60] +4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9482 .loc 1 4429 8 view .LVU3353 + 9483 0082 002B cmp r3, #0 + 9484 0084 54D0 beq .L597 +4432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9485 .loc 1 4432 7 is_stmt 1 view .LVU3354 +4432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9486 .loc 1 4432 38 is_stmt 0 view .LVU3355 + 9487 0086 464A ldr r2, .L608+4 + 9488 0088 DA63 str r2, [r3, #60] +4435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9489 .loc 1 4435 7 is_stmt 1 view .LVU3356 +4435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9490 .loc 1 4435 11 is_stmt 0 view .LVU3357 + 9491 008a E36B ldr r3, [r4, #60] +4435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9492 .loc 1 4435 39 view .LVU3358 + 9493 008c 454A ldr r2, .L608+8 + 9494 008e DA64 str r2, [r3, #76] +4438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 9495 .loc 1 4438 7 is_stmt 1 view .LVU3359 +4438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 9496 .loc 1 4438 11 is_stmt 0 view .LVU3360 + 9497 0090 E26B ldr r2, [r4, #60] +4438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 9498 .loc 1 4438 42 view .LVU3361 + 9499 0092 0023 movs r3, #0 + 9500 0094 1364 str r3, [r2, #64] +4439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9501 .loc 1 4439 7 is_stmt 1 view .LVU3362 +4439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9502 .loc 1 4439 11 is_stmt 0 view .LVU3363 + 9503 0096 E26B ldr r2, [r4, #60] +4439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9504 .loc 1 4439 39 view .LVU3364 + 9505 0098 1365 str r3, [r2, #80] +4442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)pData, hi2c->XferSize); + 9506 .loc 1 4442 7 is_stmt 1 view .LVU3365 + ARM GAS /tmp/ccSHpINd.s page 356 + + +4442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)pData, hi2c->XferSize); + 9507 .loc 1 4442 69 is_stmt 0 view .LVU3366 + 9508 009a 2168 ldr r1, [r4] +4442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (uint32_t)pData, hi2c->XferSize); + 9509 .loc 1 4442 23 view .LVU3367 + 9510 009c 238D ldrh r3, [r4, #40] + 9511 009e 3A46 mov r2, r7 + 9512 00a0 2431 adds r1, r1, #36 + 9513 00a2 E06B ldr r0, [r4, #60] + 9514 00a4 FFF7FEFF bl HAL_DMA_Start_IT + 9515 .LVL660: +4460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9516 .loc 1 4460 5 is_stmt 1 view .LVU3368 +4460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9517 .loc 1 4460 8 is_stmt 0 view .LVU3369 + 9518 00a8 0546 mov r5, r0 + 9519 .LVL661: +4460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9520 .loc 1 4460 8 view .LVU3370 + 9521 00aa 0028 cmp r0, #0 + 9522 00ac 4ED0 beq .L598 +4471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9523 .loc 1 4471 7 is_stmt 1 view .LVU3371 +4471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9524 .loc 1 4471 23 is_stmt 0 view .LVU3372 + 9525 00ae 2823 movs r3, #40 + 9526 00b0 84F84130 strb r3, [r4, #65] +4472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9527 .loc 1 4472 7 is_stmt 1 view .LVU3373 +4472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9528 .loc 1 4472 23 is_stmt 0 view .LVU3374 + 9529 00b4 0022 movs r2, #0 + 9530 00b6 84F84220 strb r2, [r4, #66] +4475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9531 .loc 1 4475 7 is_stmt 1 view .LVU3375 +4475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9532 .loc 1 4475 11 is_stmt 0 view .LVU3376 + 9533 00ba 636C ldr r3, [r4, #68] +4475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9534 .loc 1 4475 23 view .LVU3377 + 9535 00bc 43F01003 orr r3, r3, #16 + 9536 00c0 6364 str r3, [r4, #68] +4478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9537 .loc 1 4478 7 is_stmt 1 view .LVU3378 +4478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9538 .loc 1 4478 7 view .LVU3379 + 9539 00c2 84F84020 strb r2, [r4, #64] +4478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9540 .loc 1 4478 7 view .LVU3380 +4480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9541 .loc 1 4480 7 view .LVU3381 +4480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9542 .loc 1 4480 14 is_stmt 0 view .LVU3382 + 9543 00c6 0125 movs r5, #1 + 9544 00c8 64E0 b .L593 + 9545 .LVL662: + 9546 .L606: + ARM GAS /tmp/ccSHpINd.s page 357 + + +4366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9547 .loc 1 4366 7 is_stmt 1 view .LVU3383 + 9548 00ca 0121 movs r1, #1 + 9549 00cc 2046 mov r0, r4 + 9550 00ce FFF7FEFF bl I2C_Disable_IRQ + 9551 .LVL663: +4368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9552 .loc 1 4368 7 view .LVU3384 +4368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9553 .loc 1 4368 16 is_stmt 0 view .LVU3385 + 9554 00d2 2368 ldr r3, [r4] +4368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9555 .loc 1 4368 26 view .LVU3386 + 9556 00d4 1A68 ldr r2, [r3] +4368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9557 .loc 1 4368 10 view .LVU3387 + 9558 00d6 12F4804F tst r2, #16384 + 9559 00da BDD0 beq .L596 +4371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9560 .loc 1 4371 9 is_stmt 1 view .LVU3388 +4371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9561 .loc 1 4371 17 is_stmt 0 view .LVU3389 + 9562 00dc A26B ldr r2, [r4, #56] +4371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9563 .loc 1 4371 12 view .LVU3390 + 9564 00de 002A cmp r2, #0 + 9565 00e0 BAD0 beq .L596 +4373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9566 .loc 1 4373 11 is_stmt 1 view .LVU3391 +4373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9567 .loc 1 4373 25 is_stmt 0 view .LVU3392 + 9568 00e2 1A68 ldr r2, [r3] +4373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9569 .loc 1 4373 31 view .LVU3393 + 9570 00e4 22F48042 bic r2, r2, #16384 + 9571 00e8 1A60 str r2, [r3] +4377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9572 .loc 1 4377 11 is_stmt 1 view .LVU3394 +4377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9573 .loc 1 4377 15 is_stmt 0 view .LVU3395 + 9574 00ea A36B ldr r3, [r4, #56] +4377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9575 .loc 1 4377 43 view .LVU3396 + 9576 00ec 2E4A ldr r2, .L608+12 + 9577 00ee 1A65 str r2, [r3, #80] +4380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9578 .loc 1 4380 11 is_stmt 1 view .LVU3397 +4380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9579 .loc 1 4380 15 is_stmt 0 view .LVU3398 + 9580 00f0 A06B ldr r0, [r4, #56] + 9581 00f2 FFF7FEFF bl HAL_DMA_Abort_IT + 9582 .LVL664: +4380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9583 .loc 1 4380 14 discriminator 1 view .LVU3399 + 9584 00f6 0028 cmp r0, #0 + 9585 00f8 AED0 beq .L596 +4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + ARM GAS /tmp/ccSHpINd.s page 358 + + + 9586 .loc 1 4383 13 is_stmt 1 view .LVU3400 +4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9587 .loc 1 4383 17 is_stmt 0 view .LVU3401 + 9588 00fa A06B ldr r0, [r4, #56] +4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9589 .loc 1 4383 25 view .LVU3402 + 9590 00fc 036D ldr r3, [r0, #80] +4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9591 .loc 1 4383 13 view .LVU3403 + 9592 00fe 9847 blx r3 + 9593 .LVL665: + 9594 0100 AAE7 b .L596 + 9595 .L607: +4390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9596 .loc 1 4390 7 is_stmt 1 view .LVU3404 +4390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9597 .loc 1 4390 16 is_stmt 0 view .LVU3405 + 9598 0102 2368 ldr r3, [r4] +4390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9599 .loc 1 4390 26 view .LVU3406 + 9600 0104 1A68 ldr r2, [r3] +4390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9601 .loc 1 4390 10 view .LVU3407 + 9602 0106 12F4004F tst r2, #32768 + 9603 010a A5D0 beq .L596 +4392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9604 .loc 1 4392 9 is_stmt 1 view .LVU3408 +4392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9605 .loc 1 4392 23 is_stmt 0 view .LVU3409 + 9606 010c 1A68 ldr r2, [r3] +4392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9607 .loc 1 4392 29 view .LVU3410 + 9608 010e 22F40042 bic r2, r2, #32768 + 9609 0112 1A60 str r2, [r3] +4395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9610 .loc 1 4395 9 is_stmt 1 view .LVU3411 +4395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9611 .loc 1 4395 17 is_stmt 0 view .LVU3412 + 9612 0114 E36B ldr r3, [r4, #60] +4395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9613 .loc 1 4395 12 view .LVU3413 + 9614 0116 002B cmp r3, #0 + 9615 0118 9ED0 beq .L596 +4399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9616 .loc 1 4399 11 is_stmt 1 view .LVU3414 +4399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9617 .loc 1 4399 43 is_stmt 0 view .LVU3415 + 9618 011a 234A ldr r2, .L608+12 + 9619 011c 1A65 str r2, [r3, #80] +4402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9620 .loc 1 4402 11 is_stmt 1 view .LVU3416 +4402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9621 .loc 1 4402 15 is_stmt 0 view .LVU3417 + 9622 011e E06B ldr r0, [r4, #60] + 9623 0120 FFF7FEFF bl HAL_DMA_Abort_IT + 9624 .LVL666: +4402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 359 + + + 9625 .loc 1 4402 14 discriminator 1 view .LVU3418 + 9626 0124 0028 cmp r0, #0 + 9627 0126 97D0 beq .L596 +4405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9628 .loc 1 4405 13 is_stmt 1 view .LVU3419 +4405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9629 .loc 1 4405 17 is_stmt 0 view .LVU3420 + 9630 0128 E06B ldr r0, [r4, #60] +4405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9631 .loc 1 4405 25 view .LVU3421 + 9632 012a 036D ldr r3, [r0, #80] +4405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9633 .loc 1 4405 13 view .LVU3422 + 9634 012c 9847 blx r3 + 9635 .LVL667: + 9636 012e 93E7 b .L596 + 9637 .L597: +4448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9638 .loc 1 4448 7 is_stmt 1 view .LVU3423 +4448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9639 .loc 1 4448 23 is_stmt 0 view .LVU3424 + 9640 0130 2823 movs r3, #40 + 9641 0132 84F84130 strb r3, [r4, #65] +4449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9642 .loc 1 4449 7 is_stmt 1 view .LVU3425 +4449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9643 .loc 1 4449 23 is_stmt 0 view .LVU3426 + 9644 0136 0022 movs r2, #0 + 9645 0138 84F84220 strb r2, [r4, #66] +4452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9646 .loc 1 4452 7 is_stmt 1 view .LVU3427 +4452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9647 .loc 1 4452 11 is_stmt 0 view .LVU3428 + 9648 013c 636C ldr r3, [r4, #68] +4452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9649 .loc 1 4452 23 view .LVU3429 + 9650 013e 43F08003 orr r3, r3, #128 + 9651 0142 6364 str r3, [r4, #68] +4455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9652 .loc 1 4455 7 is_stmt 1 view .LVU3430 +4455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9653 .loc 1 4455 7 view .LVU3431 + 9654 0144 84F84020 strb r2, [r4, #64] +4455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9655 .loc 1 4455 7 view .LVU3432 +4457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9656 .loc 1 4457 7 view .LVU3433 +4457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9657 .loc 1 4457 14 is_stmt 0 view .LVU3434 + 9658 0148 0125 movs r5, #1 + 9659 .LVL668: +4457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9660 .loc 1 4457 14 view .LVU3435 + 9661 014a 23E0 b .L593 + 9662 .LVL669: + 9663 .L598: +4463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 360 + + + 9664 .loc 1 4463 7 is_stmt 1 view .LVU3436 +4463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9665 .loc 1 4463 11 is_stmt 0 view .LVU3437 + 9666 014c 638D ldrh r3, [r4, #42] + 9667 014e 9BB2 uxth r3, r3 +4463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9668 .loc 1 4463 30 view .LVU3438 + 9669 0150 228D ldrh r2, [r4, #40] +4463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9670 .loc 1 4463 23 view .LVU3439 + 9671 0152 9B1A subs r3, r3, r2 + 9672 0154 9BB2 uxth r3, r3 + 9673 0156 6385 strh r3, [r4, #42] @ movhi +4466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9674 .loc 1 4466 7 is_stmt 1 view .LVU3440 +4466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9675 .loc 1 4466 22 is_stmt 0 view .LVU3441 + 9676 0158 0023 movs r3, #0 + 9677 015a 2385 strh r3, [r4, #40] @ movhi +4483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + 9678 .loc 1 4483 5 is_stmt 1 view .LVU3442 +4483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + 9679 .loc 1 4483 11 is_stmt 0 view .LVU3443 + 9680 015c 2268 ldr r2, [r4] + 9681 015e 9369 ldr r3, [r2, #24] + 9682 0160 03F00803 and r3, r3, #8 + 9683 .LVL670: +4484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9684 .loc 1 4484 5 is_stmt 1 view .LVU3444 +4484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9685 .loc 1 4484 10 is_stmt 0 view .LVU3445 + 9686 0164 9169 ldr r1, [r2, #24] +4484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9687 .loc 1 4484 8 view .LVU3446 + 9688 0166 11F4803F tst r1, #65536 + 9689 016a 0DD0 beq .L600 + 9690 .LVL671: + 9691 .L601: +4492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9692 .loc 1 4492 5 is_stmt 1 view .LVU3447 +4492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9693 .loc 1 4492 5 view .LVU3448 + 9694 016c 0023 movs r3, #0 + 9695 016e 84F84030 strb r3, [r4, #64] +4492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9696 .loc 1 4492 5 view .LVU3449 +4495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9697 .loc 1 4495 5 view .LVU3450 +4495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9698 .loc 1 4495 9 is_stmt 0 view .LVU3451 + 9699 0172 2268 ldr r2, [r4] +4495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9700 .loc 1 4495 19 view .LVU3452 + 9701 0174 1368 ldr r3, [r2] +4495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9702 .loc 1 4495 25 view .LVU3453 + 9703 0176 43F40043 orr r3, r3, #32768 + ARM GAS /tmp/ccSHpINd.s page 361 + + + 9704 017a 1360 str r3, [r2] +4501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9705 .loc 1 4501 5 is_stmt 1 view .LVU3454 + 9706 017c 48F20201 movw r1, #32770 + 9707 0180 2046 mov r0, r4 + 9708 .LVL672: +4501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9709 .loc 1 4501 5 is_stmt 0 view .LVU3455 + 9710 0182 FFF7FEFF bl I2C_Enable_IRQ + 9711 .LVL673: +4503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9712 .loc 1 4503 5 is_stmt 1 view .LVU3456 +4503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9713 .loc 1 4503 12 is_stmt 0 view .LVU3457 + 9714 0186 05E0 b .L593 + 9715 .LVL674: + 9716 .L600: +4484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9717 .loc 1 4484 55 discriminator 1 view .LVU3458 + 9718 0188 002B cmp r3, #0 + 9719 018a EFD0 beq .L601 +4488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9720 .loc 1 4488 7 is_stmt 1 view .LVU3459 + 9721 018c 0823 movs r3, #8 + 9722 .LVL675: +4488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9723 .loc 1 4488 7 is_stmt 0 view .LVU3460 + 9724 018e D361 str r3, [r2, #28] + 9725 0190 ECE7 b .L601 + 9726 .LVL676: + 9727 .L602: +4507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9728 .loc 1 4507 12 view .LVU3461 + 9729 0192 0125 movs r5, #1 + 9730 .LVL677: + 9731 .L593: +4509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9732 .loc 1 4509 1 view .LVU3462 + 9733 0194 2846 mov r0, r5 + 9734 0196 F8BD pop {r3, r4, r5, r6, r7, pc} + 9735 .LVL678: + 9736 .L603: +4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9737 .loc 1 4359 5 discriminator 1 view .LVU3463 + 9738 0198 0225 movs r5, #2 + 9739 .LVL679: +4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9740 .loc 1 4359 5 discriminator 1 view .LVU3464 + 9741 019a FBE7 b .L593 + 9742 .L609: + 9743 .align 2 + 9744 .L608: + 9745 019c 00000000 .word I2C_Slave_ISR_DMA + 9746 01a0 00000000 .word I2C_DMASlaveReceiveCplt + 9747 01a4 00000000 .word I2C_DMAError + 9748 01a8 00000000 .word I2C_DMAAbort + 9749 .cfi_endproc + ARM GAS /tmp/ccSHpINd.s page 362 + + + 9750 .LFE171: + 9752 .section .text.HAL_I2C_EnableListen_IT,"ax",%progbits + 9753 .align 1 + 9754 .global HAL_I2C_EnableListen_IT + 9755 .syntax unified + 9756 .thumb + 9757 .thumb_func + 9759 HAL_I2C_EnableListen_IT: + 9760 .LVL680: + 9761 .LFB172: +4518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 9762 .loc 1 4518 1 is_stmt 1 view -0 + 9763 .cfi_startproc + 9764 @ args = 0, pretend = 0, frame = 0 + 9765 @ frame_needed = 0, uses_anonymous_args = 0 +4518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 9766 .loc 1 4518 1 is_stmt 0 view .LVU3466 + 9767 0000 08B5 push {r3, lr} + 9768 .LCFI106: + 9769 .cfi_def_cfa_offset 8 + 9770 .cfi_offset 3, -8 + 9771 .cfi_offset 14, -4 +4519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9772 .loc 1 4519 3 is_stmt 1 view .LVU3467 +4519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9773 .loc 1 4519 11 is_stmt 0 view .LVU3468 + 9774 0002 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 9775 0006 DBB2 uxtb r3, r3 +4519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9776 .loc 1 4519 6 view .LVU3469 + 9777 0008 202B cmp r3, #32 + 9778 000a 01D0 beq .L614 +4531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9779 .loc 1 4531 12 view .LVU3470 + 9780 000c 0220 movs r0, #2 + 9781 .LVL681: + 9782 .L611: +4533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9783 .loc 1 4533 1 view .LVU3471 + 9784 000e 08BD pop {r3, pc} + 9785 .LVL682: + 9786 .L614: +4521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 9787 .loc 1 4521 5 is_stmt 1 view .LVU3472 +4521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 9788 .loc 1 4521 17 is_stmt 0 view .LVU3473 + 9789 0010 2823 movs r3, #40 + 9790 0012 80F84130 strb r3, [r0, #65] +4522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9791 .loc 1 4522 5 is_stmt 1 view .LVU3474 +4522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9792 .loc 1 4522 19 is_stmt 0 view .LVU3475 + 9793 0016 044B ldr r3, .L615 + 9794 0018 4363 str r3, [r0, #52] +4525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9795 .loc 1 4525 5 is_stmt 1 view .LVU3476 + 9796 001a 4FF40041 mov r1, #32768 + ARM GAS /tmp/ccSHpINd.s page 363 + + + 9797 001e FFF7FEFF bl I2C_Enable_IRQ + 9798 .LVL683: +4527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9799 .loc 1 4527 5 view .LVU3477 +4527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9800 .loc 1 4527 12 is_stmt 0 view .LVU3478 + 9801 0022 0020 movs r0, #0 + 9802 0024 F3E7 b .L611 + 9803 .L616: + 9804 0026 00BF .align 2 + 9805 .L615: + 9806 0028 00000000 .word I2C_Slave_ISR_IT + 9807 .cfi_endproc + 9808 .LFE172: + 9810 .section .text.HAL_I2C_DisableListen_IT,"ax",%progbits + 9811 .align 1 + 9812 .global HAL_I2C_DisableListen_IT + 9813 .syntax unified + 9814 .thumb + 9815 .thumb_func + 9817 HAL_I2C_DisableListen_IT: + 9818 .LVL684: + 9819 .LFB173: +4542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ + 9820 .loc 1 4542 1 is_stmt 1 view -0 + 9821 .cfi_startproc + 9822 @ args = 0, pretend = 0, frame = 0 + 9823 @ frame_needed = 0, uses_anonymous_args = 0 +4544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9824 .loc 1 4544 3 view .LVU3480 +4547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9825 .loc 1 4547 3 view .LVU3481 +4547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9826 .loc 1 4547 11 is_stmt 0 view .LVU3482 + 9827 0000 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 9828 0004 DBB2 uxtb r3, r3 +4547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9829 .loc 1 4547 6 view .LVU3483 + 9830 0006 282B cmp r3, #40 + 9831 0008 01D0 beq .L624 +4562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9832 .loc 1 4562 12 view .LVU3484 + 9833 000a 0220 movs r0, #2 + 9834 .LVL685: +4564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9835 .loc 1 4564 1 view .LVU3485 + 9836 000c 7047 bx lr + 9837 .LVL686: + 9838 .L624: +4542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ + 9839 .loc 1 4542 1 view .LVU3486 + 9840 000e 10B5 push {r4, lr} + 9841 .LCFI107: + 9842 .cfi_def_cfa_offset 8 + 9843 .cfi_offset 4, -8 + 9844 .cfi_offset 14, -4 +4549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + ARM GAS /tmp/ccSHpINd.s page 364 + + + 9845 .loc 1 4549 5 is_stmt 1 view .LVU3487 +4549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + 9846 .loc 1 4549 26 is_stmt 0 view .LVU3488 + 9847 0010 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2 + 9848 .LVL687: +4550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9849 .loc 1 4550 5 is_stmt 1 view .LVU3489 +4550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9850 .loc 1 4550 48 is_stmt 0 view .LVU3490 + 9851 0014 90F84230 ldrb r3, [r0, #66] @ zero_extendqisi2 +4550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9852 .loc 1 4550 31 view .LVU3491 + 9853 0018 02F00302 and r2, r2, #3 + 9854 .LVL688: +4550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9855 .loc 1 4550 31 view .LVU3492 + 9856 001c 1343 orrs r3, r3, r2 +4550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9857 .loc 1 4550 25 view .LVU3493 + 9858 001e 0363 str r3, [r0, #48] +4551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9859 .loc 1 4551 5 is_stmt 1 view .LVU3494 +4551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9860 .loc 1 4551 17 is_stmt 0 view .LVU3495 + 9861 0020 2023 movs r3, #32 + 9862 0022 80F84130 strb r3, [r0, #65] +4552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 9863 .loc 1 4552 5 is_stmt 1 view .LVU3496 +4552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 9864 .loc 1 4552 16 is_stmt 0 view .LVU3497 + 9865 0026 0024 movs r4, #0 + 9866 0028 80F84240 strb r4, [r0, #66] +4553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9867 .loc 1 4553 5 is_stmt 1 view .LVU3498 +4553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9868 .loc 1 4553 19 is_stmt 0 view .LVU3499 + 9869 002c 4463 str r4, [r0, #52] +4556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9870 .loc 1 4556 5 is_stmt 1 view .LVU3500 + 9871 002e 4FF40041 mov r1, #32768 + 9872 0032 FFF7FEFF bl I2C_Disable_IRQ + 9873 .LVL689: +4558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9874 .loc 1 4558 5 view .LVU3501 +4558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9875 .loc 1 4558 12 is_stmt 0 view .LVU3502 + 9876 0036 2046 mov r0, r4 +4564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9877 .loc 1 4564 1 view .LVU3503 + 9878 0038 10BD pop {r4, pc} + 9879 .cfi_endproc + 9880 .LFE173: + 9882 .section .text.HAL_I2C_Master_Abort_IT,"ax",%progbits + 9883 .align 1 + 9884 .global HAL_I2C_Master_Abort_IT + 9885 .syntax unified + 9886 .thumb + ARM GAS /tmp/ccSHpINd.s page 365 + + + 9887 .thumb_func + 9889 HAL_I2C_Master_Abort_IT: + 9890 .LVL690: + 9891 .LFB174: +4575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; + 9892 .loc 1 4575 1 is_stmt 1 view -0 + 9893 .cfi_startproc + 9894 @ args = 0, pretend = 0, frame = 0 + 9895 @ frame_needed = 0, uses_anonymous_args = 0 +4576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9896 .loc 1 4576 3 view .LVU3505 +4576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9897 .loc 1 4576 23 is_stmt 0 view .LVU3506 + 9898 0000 90F84230 ldrb r3, [r0, #66] @ zero_extendqisi2 + 9899 0004 DBB2 uxtb r3, r3 + 9900 .LVL691: +4578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9901 .loc 1 4578 3 is_stmt 1 view .LVU3507 +4578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9902 .loc 1 4578 6 is_stmt 0 view .LVU3508 + 9903 0006 402B cmp r3, #64 + 9904 0008 18BF it ne + 9905 000a 102B cmpne r3, #16 + 9906 000c 36D1 bne .L629 +4575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; + 9907 .loc 1 4575 1 view .LVU3509 + 9908 000e 30B5 push {r4, r5, lr} + 9909 .LCFI108: + 9910 .cfi_def_cfa_offset 12 + 9911 .cfi_offset 4, -12 + 9912 .cfi_offset 5, -8 + 9913 .cfi_offset 14, -4 + 9914 0010 83B0 sub sp, sp, #12 + 9915 .LCFI109: + 9916 .cfi_def_cfa_offset 24 + 9917 0012 0446 mov r4, r0 + 9918 0014 0D46 mov r5, r1 +4581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9919 .loc 1 4581 5 is_stmt 1 view .LVU3510 +4581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9920 .loc 1 4581 5 view .LVU3511 + 9921 0016 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 9922 .LVL692: +4581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9923 .loc 1 4581 5 is_stmt 0 view .LVU3512 + 9924 001a 012B cmp r3, #1 + 9925 001c 30D0 beq .L630 +4581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9926 .loc 1 4581 5 is_stmt 1 discriminator 2 view .LVU3513 + 9927 001e 0123 movs r3, #1 + 9928 0020 80F84030 strb r3, [r0, #64] +4581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9929 .loc 1 4581 5 discriminator 2 view .LVU3514 +4584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9930 .loc 1 4584 5 view .LVU3515 +4584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9931 .loc 1 4584 13 is_stmt 0 view .LVU3516 + ARM GAS /tmp/ccSHpINd.s page 366 + + + 9932 0024 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 9933 0028 DBB2 uxtb r3, r3 +4584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9934 .loc 1 4584 8 view .LVU3517 + 9935 002a 212B cmp r3, #33 + 9936 002c 1AD0 beq .L635 +4589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9937 .loc 1 4589 10 is_stmt 1 view .LVU3518 +4589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9938 .loc 1 4589 18 is_stmt 0 view .LVU3519 + 9939 002e 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 9940 0032 DBB2 uxtb r3, r3 +4589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 9941 .loc 1 4589 13 view .LVU3520 + 9942 0034 222B cmp r3, #34 + 9943 0036 1BD0 beq .L636 + 9944 .LVL693: + 9945 .L628: +4597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9946 .loc 1 4597 5 is_stmt 1 view .LVU3521 +4600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9947 .loc 1 4600 5 view .LVU3522 +4600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9948 .loc 1 4600 17 is_stmt 0 view .LVU3523 + 9949 0038 6023 movs r3, #96 + 9950 003a 84F84130 strb r3, [r4, #65] +4604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9951 .loc 1 4604 5 is_stmt 1 view .LVU3524 + 9952 003e 114B ldr r3, .L637 + 9953 0040 0093 str r3, [sp] + 9954 0042 4FF00073 mov r3, #33554432 + 9955 0046 0122 movs r2, #1 + 9956 0048 2946 mov r1, r5 + 9957 004a 2046 mov r0, r4 + 9958 004c FFF7FEFF bl I2C_TransferConfig + 9959 .LVL694: +4607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9960 .loc 1 4607 5 view .LVU3525 +4607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9961 .loc 1 4607 5 view .LVU3526 + 9962 0050 0025 movs r5, #0 + 9963 .LVL695: +4607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9964 .loc 1 4607 5 is_stmt 0 view .LVU3527 + 9965 0052 84F84050 strb r5, [r4, #64] +4607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9966 .loc 1 4607 5 is_stmt 1 view .LVU3528 +4612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9967 .loc 1 4612 5 view .LVU3529 + 9968 0056 2021 movs r1, #32 + 9969 0058 2046 mov r0, r4 + 9970 005a FFF7FEFF bl I2C_Enable_IRQ + 9971 .LVL696: +4614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9972 .loc 1 4614 5 view .LVU3530 +4614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9973 .loc 1 4614 12 is_stmt 0 view .LVU3531 + ARM GAS /tmp/ccSHpINd.s page 367 + + + 9974 005e 2846 mov r0, r5 + 9975 .L626: +4622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 9976 .loc 1 4622 1 view .LVU3532 + 9977 0060 03B0 add sp, sp, #12 + 9978 .LCFI110: + 9979 .cfi_remember_state + 9980 .cfi_def_cfa_offset 12 + 9981 @ sp needed + 9982 0062 30BD pop {r4, r5, pc} + 9983 .LVL697: + 9984 .L635: + 9985 .LCFI111: + 9986 .cfi_restore_state +4586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 9987 .loc 1 4586 7 is_stmt 1 view .LVU3533 + 9988 0064 0121 movs r1, #1 + 9989 .LVL698: +4586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 9990 .loc 1 4586 7 is_stmt 0 view .LVU3534 + 9991 0066 FFF7FEFF bl I2C_Disable_IRQ + 9992 .LVL699: +4587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9993 .loc 1 4587 7 is_stmt 1 view .LVU3535 +4587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 9994 .loc 1 4587 27 is_stmt 0 view .LVU3536 + 9995 006a 1123 movs r3, #17 + 9996 006c 2363 str r3, [r4, #48] + 9997 006e E3E7 b .L628 + 9998 .LVL700: + 9999 .L636: +4591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 10000 .loc 1 4591 7 is_stmt 1 view .LVU3537 + 10001 0070 0221 movs r1, #2 + 10002 .LVL701: +4591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 10003 .loc 1 4591 7 is_stmt 0 view .LVU3538 + 10004 0072 FFF7FEFF bl I2C_Disable_IRQ + 10005 .LVL702: +4592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10006 .loc 1 4592 7 is_stmt 1 view .LVU3539 +4592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10007 .loc 1 4592 27 is_stmt 0 view .LVU3540 + 10008 0076 1223 movs r3, #18 + 10009 0078 2363 str r3, [r4, #48] + 10010 007a DDE7 b .L628 + 10011 .LVL703: + 10012 .L629: + 10013 .LCFI112: + 10014 .cfi_def_cfa_offset 0 + 10015 .cfi_restore 4 + 10016 .cfi_restore 5 + 10017 .cfi_restore 14 +4620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10018 .loc 1 4620 12 view .LVU3541 + 10019 007c 0120 movs r0, #1 + 10020 .LVL704: + ARM GAS /tmp/ccSHpINd.s page 368 + + +4622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10021 .loc 1 4622 1 view .LVU3542 + 10022 007e 7047 bx lr + 10023 .LVL705: + 10024 .L630: + 10025 .LCFI113: + 10026 .cfi_def_cfa_offset 24 + 10027 .cfi_offset 4, -12 + 10028 .cfi_offset 5, -8 + 10029 .cfi_offset 14, -4 +4581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10030 .loc 1 4581 5 discriminator 1 view .LVU3543 + 10031 0080 0220 movs r0, #2 + 10032 .LVL706: +4581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10033 .loc 1 4581 5 discriminator 1 view .LVU3544 + 10034 0082 EDE7 b .L626 + 10035 .L638: + 10036 .align 2 + 10037 .L637: + 10038 0084 00400080 .word -2147467264 + 10039 .cfi_endproc + 10040 .LFE174: + 10042 .section .text.HAL_I2C_EV_IRQHandler,"ax",%progbits + 10043 .align 1 + 10044 .global HAL_I2C_EV_IRQHandler + 10045 .syntax unified + 10046 .thumb + 10047 .thumb_func + 10049 HAL_I2C_EV_IRQHandler: + 10050 .LVL707: + 10051 .LFB175: +4639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Get current IT Flags and IT sources value */ + 10052 .loc 1 4639 1 is_stmt 1 view -0 + 10053 .cfi_startproc + 10054 @ args = 0, pretend = 0, frame = 0 + 10055 @ frame_needed = 0, uses_anonymous_args = 0 +4639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Get current IT Flags and IT sources value */ + 10056 .loc 1 4639 1 is_stmt 0 view .LVU3546 + 10057 0000 08B5 push {r3, lr} + 10058 .LCFI114: + 10059 .cfi_def_cfa_offset 8 + 10060 .cfi_offset 3, -8 + 10061 .cfi_offset 14, -4 +4641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 10062 .loc 1 4641 3 is_stmt 1 view .LVU3547 +4641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 10063 .loc 1 4641 24 is_stmt 0 view .LVU3548 + 10064 0002 0368 ldr r3, [r0] +4641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 10065 .loc 1 4641 12 view .LVU3549 + 10066 0004 9969 ldr r1, [r3, #24] + 10067 .LVL708: +4642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10068 .loc 1 4642 3 is_stmt 1 view .LVU3550 +4642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10069 .loc 1 4642 12 is_stmt 0 view .LVU3551 + ARM GAS /tmp/ccSHpINd.s page 369 + + + 10070 0006 1A68 ldr r2, [r3] + 10071 .LVL709: +4645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10072 .loc 1 4645 3 is_stmt 1 view .LVU3552 +4645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10073 .loc 1 4645 11 is_stmt 0 view .LVU3553 + 10074 0008 436B ldr r3, [r0, #52] +4645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10075 .loc 1 4645 6 view .LVU3554 + 10076 000a 03B1 cbz r3, .L639 +4647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10077 .loc 1 4647 5 is_stmt 1 view .LVU3555 + 10078 000c 9847 blx r3 + 10079 .LVL710: + 10080 .L639: +4649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10081 .loc 1 4649 1 is_stmt 0 view .LVU3556 + 10082 000e 08BD pop {r3, pc} + 10083 .cfi_endproc + 10084 .LFE175: + 10086 .section .text.HAL_I2C_MasterTxCpltCallback,"ax",%progbits + 10087 .align 1 + 10088 .weak HAL_I2C_MasterTxCpltCallback + 10089 .syntax unified + 10090 .thumb + 10091 .thumb_func + 10093 HAL_I2C_MasterTxCpltCallback: + 10094 .LVL711: + 10095 .LFB177: +4710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10096 .loc 1 4710 1 is_stmt 1 view -0 + 10097 .cfi_startproc + 10098 @ args = 0, pretend = 0, frame = 0 + 10099 @ frame_needed = 0, uses_anonymous_args = 0 + 10100 @ link register save eliminated. +4712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10101 .loc 1 4712 3 view .LVU3558 +4717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10102 .loc 1 4717 1 is_stmt 0 view .LVU3559 + 10103 0000 7047 bx lr + 10104 .cfi_endproc + 10105 .LFE177: + 10107 .section .text.HAL_I2C_MasterRxCpltCallback,"ax",%progbits + 10108 .align 1 + 10109 .weak HAL_I2C_MasterRxCpltCallback + 10110 .syntax unified + 10111 .thumb + 10112 .thumb_func + 10114 HAL_I2C_MasterRxCpltCallback: + 10115 .LVL712: + 10116 .LFB178: +4726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10117 .loc 1 4726 1 is_stmt 1 view -0 + 10118 .cfi_startproc + 10119 @ args = 0, pretend = 0, frame = 0 + 10120 @ frame_needed = 0, uses_anonymous_args = 0 + 10121 @ link register save eliminated. + ARM GAS /tmp/ccSHpINd.s page 370 + + +4728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10122 .loc 1 4728 3 view .LVU3561 +4733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10123 .loc 1 4733 1 is_stmt 0 view .LVU3562 + 10124 0000 7047 bx lr + 10125 .cfi_endproc + 10126 .LFE178: + 10128 .section .text.I2C_ITMasterSeqCplt,"ax",%progbits + 10129 .align 1 + 10130 .syntax unified + 10131 .thumb + 10132 .thumb_func + 10134 I2C_ITMasterSeqCplt: + 10135 .LVL713: + 10136 .LFB199: +6053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset I2C handle mode */ + 10137 .loc 1 6053 1 is_stmt 1 view -0 + 10138 .cfi_startproc + 10139 @ args = 0, pretend = 0, frame = 0 + 10140 @ frame_needed = 0, uses_anonymous_args = 0 +6053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset I2C handle mode */ + 10141 .loc 1 6053 1 is_stmt 0 view .LVU3564 + 10142 0000 38B5 push {r3, r4, r5, lr} + 10143 .LCFI115: + 10144 .cfi_def_cfa_offset 16 + 10145 .cfi_offset 3, -16 + 10146 .cfi_offset 4, -12 + 10147 .cfi_offset 5, -8 + 10148 .cfi_offset 14, -4 + 10149 0002 0446 mov r4, r0 +6055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10150 .loc 1 6055 3 is_stmt 1 view .LVU3565 +6055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10151 .loc 1 6055 14 is_stmt 0 view .LVU3566 + 10152 0004 0023 movs r3, #0 + 10153 0006 80F84230 strb r3, [r0, #66] +6059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10154 .loc 1 6059 3 is_stmt 1 view .LVU3567 +6059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10155 .loc 1 6059 11 is_stmt 0 view .LVU3568 + 10156 000a 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 10157 000e DBB2 uxtb r3, r3 +6059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10158 .loc 1 6059 6 view .LVU3569 + 10159 0010 212B cmp r3, #33 + 10160 0012 0FD0 beq .L648 +6081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 10161 .loc 1 6081 5 is_stmt 1 view .LVU3570 +6081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 10162 .loc 1 6081 25 is_stmt 0 view .LVU3571 + 10163 0014 2023 movs r3, #32 + 10164 0016 80F84130 strb r3, [r0, #65] +6082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 10165 .loc 1 6082 5 is_stmt 1 view .LVU3572 +6082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 10166 .loc 1 6082 25 is_stmt 0 view .LVU3573 + 10167 001a 1223 movs r3, #18 + ARM GAS /tmp/ccSHpINd.s page 371 + + + 10168 001c 0363 str r3, [r0, #48] +6083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10169 .loc 1 6083 5 is_stmt 1 view .LVU3574 +6083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10170 .loc 1 6083 25 is_stmt 0 view .LVU3575 + 10171 001e 0025 movs r5, #0 + 10172 0020 4563 str r5, [r0, #52] +6086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10173 .loc 1 6086 5 is_stmt 1 view .LVU3576 + 10174 0022 0221 movs r1, #2 + 10175 0024 FFF7FEFF bl I2C_Disable_IRQ + 10176 .LVL714: +6089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10177 .loc 1 6089 5 view .LVU3577 +6089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10178 .loc 1 6089 5 view .LVU3578 + 10179 0028 84F84050 strb r5, [r4, #64] +6089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10180 .loc 1 6089 5 view .LVU3579 +6095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10181 .loc 1 6095 5 view .LVU3580 + 10182 002c 2046 mov r0, r4 + 10183 002e FFF7FEFF bl HAL_I2C_MasterRxCpltCallback + 10184 .LVL715: + 10185 .L644: +6098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10186 .loc 1 6098 1 is_stmt 0 view .LVU3581 + 10187 0032 38BD pop {r3, r4, r5, pc} + 10188 .LVL716: + 10189 .L648: +6061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 10190 .loc 1 6061 5 is_stmt 1 view .LVU3582 +6061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 10191 .loc 1 6061 25 is_stmt 0 view .LVU3583 + 10192 0034 2023 movs r3, #32 + 10193 0036 80F84130 strb r3, [r0, #65] +6062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 10194 .loc 1 6062 5 is_stmt 1 view .LVU3584 +6062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 10195 .loc 1 6062 25 is_stmt 0 view .LVU3585 + 10196 003a 1123 movs r3, #17 + 10197 003c 0363 str r3, [r0, #48] +6063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10198 .loc 1 6063 5 is_stmt 1 view .LVU3586 +6063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10199 .loc 1 6063 25 is_stmt 0 view .LVU3587 + 10200 003e 0025 movs r5, #0 + 10201 0040 4563 str r5, [r0, #52] +6066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10202 .loc 1 6066 5 is_stmt 1 view .LVU3588 + 10203 0042 0121 movs r1, #1 + 10204 0044 FFF7FEFF bl I2C_Disable_IRQ + 10205 .LVL717: +6069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10206 .loc 1 6069 5 view .LVU3589 +6069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10207 .loc 1 6069 5 view .LVU3590 + ARM GAS /tmp/ccSHpINd.s page 372 + + + 10208 0048 84F84050 strb r5, [r4, #64] +6069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10209 .loc 1 6069 5 view .LVU3591 +6075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10210 .loc 1 6075 5 view .LVU3592 + 10211 004c 2046 mov r0, r4 + 10212 004e FFF7FEFF bl HAL_I2C_MasterTxCpltCallback + 10213 .LVL718: + 10214 0052 EEE7 b .L644 + 10215 .cfi_endproc + 10216 .LFE199: + 10218 .section .text.HAL_I2C_SlaveTxCpltCallback,"ax",%progbits + 10219 .align 1 + 10220 .weak HAL_I2C_SlaveTxCpltCallback + 10221 .syntax unified + 10222 .thumb + 10223 .thumb_func + 10225 HAL_I2C_SlaveTxCpltCallback: + 10226 .LVL719: + 10227 .LFB179: +4741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10228 .loc 1 4741 1 view -0 + 10229 .cfi_startproc + 10230 @ args = 0, pretend = 0, frame = 0 + 10231 @ frame_needed = 0, uses_anonymous_args = 0 + 10232 @ link register save eliminated. +4743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10233 .loc 1 4743 3 view .LVU3594 +4748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10234 .loc 1 4748 1 is_stmt 0 view .LVU3595 + 10235 0000 7047 bx lr + 10236 .cfi_endproc + 10237 .LFE179: + 10239 .section .text.HAL_I2C_SlaveRxCpltCallback,"ax",%progbits + 10240 .align 1 + 10241 .weak HAL_I2C_SlaveRxCpltCallback + 10242 .syntax unified + 10243 .thumb + 10244 .thumb_func + 10246 HAL_I2C_SlaveRxCpltCallback: + 10247 .LVL720: + 10248 .LFB180: +4757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10249 .loc 1 4757 1 is_stmt 1 view -0 + 10250 .cfi_startproc + 10251 @ args = 0, pretend = 0, frame = 0 + 10252 @ frame_needed = 0, uses_anonymous_args = 0 + 10253 @ link register save eliminated. +4759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10254 .loc 1 4759 3 view .LVU3597 +4764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10255 .loc 1 4764 1 is_stmt 0 view .LVU3598 + 10256 0000 7047 bx lr + 10257 .cfi_endproc + 10258 .LFE180: + 10260 .section .text.I2C_ITSlaveSeqCplt,"ax",%progbits + 10261 .align 1 + ARM GAS /tmp/ccSHpINd.s page 373 + + + 10262 .syntax unified + 10263 .thumb + 10264 .thumb_func + 10266 I2C_ITSlaveSeqCplt: + 10267 .LVL721: + 10268 .LFB200: +6106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 10269 .loc 1 6106 1 is_stmt 1 view -0 + 10270 .cfi_startproc + 10271 @ args = 0, pretend = 0, frame = 0 + 10272 @ frame_needed = 0, uses_anonymous_args = 0 +6106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 10273 .loc 1 6106 1 is_stmt 0 view .LVU3600 + 10274 0000 10B5 push {r4, lr} + 10275 .LCFI116: + 10276 .cfi_def_cfa_offset 8 + 10277 .cfi_offset 4, -8 + 10278 .cfi_offset 14, -4 + 10279 0002 0446 mov r4, r0 +6107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10280 .loc 1 6107 3 is_stmt 1 view .LVU3601 +6107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10281 .loc 1 6107 26 is_stmt 0 view .LVU3602 + 10282 0004 0368 ldr r3, [r0] +6107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10283 .loc 1 6107 12 view .LVU3603 + 10284 0006 1A68 ldr r2, [r3] + 10285 .LVL722: +6110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10286 .loc 1 6110 3 is_stmt 1 view .LVU3604 +6110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10287 .loc 1 6110 14 is_stmt 0 view .LVU3605 + 10288 0008 0021 movs r1, #0 + 10289 000a 80F84210 strb r1, [r0, #66] +6113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10290 .loc 1 6113 3 is_stmt 1 view .LVU3606 +6113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10291 .loc 1 6113 6 is_stmt 0 view .LVU3607 + 10292 000e 12F4804F tst r2, #16384 + 10293 0012 0ED0 beq .L652 +6116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10294 .loc 1 6116 5 is_stmt 1 view .LVU3608 +6116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10295 .loc 1 6116 19 is_stmt 0 view .LVU3609 + 10296 0014 1A68 ldr r2, [r3] + 10297 .LVL723: +6116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10298 .loc 1 6116 25 view .LVU3610 + 10299 0016 22F48042 bic r2, r2, #16384 + 10300 001a 1A60 str r2, [r3] + 10301 .L653: +6126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10302 .loc 1 6126 3 is_stmt 1 view .LVU3611 +6128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10303 .loc 1 6128 3 view .LVU3612 +6128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10304 .loc 1 6128 11 is_stmt 0 view .LVU3613 + ARM GAS /tmp/ccSHpINd.s page 374 + + + 10305 001c 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 10306 0020 DBB2 uxtb r3, r3 +6128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10307 .loc 1 6128 6 view .LVU3614 + 10308 0022 292B cmp r3, #41 + 10309 0024 0DD0 beq .L657 +6148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10310 .loc 1 6148 8 is_stmt 1 view .LVU3615 +6148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10311 .loc 1 6148 16 is_stmt 0 view .LVU3616 + 10312 0026 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 10313 002a DBB2 uxtb r3, r3 +6148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10314 .loc 1 6148 11 view .LVU3617 + 10315 002c 2A2B cmp r3, #42 + 10316 002e 18D0 beq .L658 + 10317 .LVL724: + 10318 .L651: +6171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10319 .loc 1 6171 1 view .LVU3618 + 10320 0030 10BD pop {r4, pc} + 10321 .LVL725: + 10322 .L652: +6118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10323 .loc 1 6118 8 is_stmt 1 view .LVU3619 +6118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10324 .loc 1 6118 11 is_stmt 0 view .LVU3620 + 10325 0032 12F4004F tst r2, #32768 + 10326 0036 F1D0 beq .L653 +6121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10327 .loc 1 6121 5 is_stmt 1 view .LVU3621 +6121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10328 .loc 1 6121 19 is_stmt 0 view .LVU3622 + 10329 0038 1A68 ldr r2, [r3] + 10330 .LVL726: +6121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10331 .loc 1 6121 25 view .LVU3623 + 10332 003a 22F40042 bic r2, r2, #32768 + 10333 003e 1A60 str r2, [r3] + 10334 0040 ECE7 b .L653 + 10335 .L657: +6131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 10336 .loc 1 6131 5 is_stmt 1 view .LVU3624 +6131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 10337 .loc 1 6131 25 is_stmt 0 view .LVU3625 + 10338 0042 2823 movs r3, #40 + 10339 0044 84F84130 strb r3, [r4, #65] +6132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10340 .loc 1 6132 5 is_stmt 1 view .LVU3626 +6132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10341 .loc 1 6132 25 is_stmt 0 view .LVU3627 + 10342 0048 2123 movs r3, #33 + 10343 004a 2363 str r3, [r4, #48] +6135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10344 .loc 1 6135 5 is_stmt 1 view .LVU3628 + 10345 004c 0121 movs r1, #1 + 10346 004e 2046 mov r0, r4 + ARM GAS /tmp/ccSHpINd.s page 375 + + + 10347 .LVL727: +6135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10348 .loc 1 6135 5 is_stmt 0 view .LVU3629 + 10349 0050 FFF7FEFF bl I2C_Disable_IRQ + 10350 .LVL728: +6138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10351 .loc 1 6138 5 is_stmt 1 view .LVU3630 +6138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10352 .loc 1 6138 5 view .LVU3631 + 10353 0054 0023 movs r3, #0 + 10354 0056 84F84030 strb r3, [r4, #64] +6138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10355 .loc 1 6138 5 view .LVU3632 +6144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10356 .loc 1 6144 5 view .LVU3633 + 10357 005a 2046 mov r0, r4 + 10358 005c FFF7FEFF bl HAL_I2C_SlaveTxCpltCallback + 10359 .LVL729: + 10360 0060 E6E7 b .L651 + 10361 .LVL730: + 10362 .L658: +6151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 10363 .loc 1 6151 5 view .LVU3634 +6151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 10364 .loc 1 6151 25 is_stmt 0 view .LVU3635 + 10365 0062 2823 movs r3, #40 + 10366 0064 84F84130 strb r3, [r4, #65] +6152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10367 .loc 1 6152 5 is_stmt 1 view .LVU3636 +6152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10368 .loc 1 6152 25 is_stmt 0 view .LVU3637 + 10369 0068 2223 movs r3, #34 + 10370 006a 2363 str r3, [r4, #48] +6155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10371 .loc 1 6155 5 is_stmt 1 view .LVU3638 + 10372 006c 0221 movs r1, #2 + 10373 006e 2046 mov r0, r4 + 10374 .LVL731: +6155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10375 .loc 1 6155 5 is_stmt 0 view .LVU3639 + 10376 0070 FFF7FEFF bl I2C_Disable_IRQ + 10377 .LVL732: +6158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10378 .loc 1 6158 5 is_stmt 1 view .LVU3640 +6158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10379 .loc 1 6158 5 view .LVU3641 + 10380 0074 0023 movs r3, #0 + 10381 0076 84F84030 strb r3, [r4, #64] +6158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10382 .loc 1 6158 5 view .LVU3642 +6164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10383 .loc 1 6164 5 view .LVU3643 + 10384 007a 2046 mov r0, r4 + 10385 007c FFF7FEFF bl HAL_I2C_SlaveRxCpltCallback + 10386 .LVL733: +6170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10387 .loc 1 6170 3 view .LVU3644 + ARM GAS /tmp/ccSHpINd.s page 376 + + +6171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10388 .loc 1 6171 1 is_stmt 0 view .LVU3645 + 10389 0080 D6E7 b .L651 + 10390 .cfi_endproc + 10391 .LFE200: + 10393 .section .text.I2C_DMASlaveTransmitCplt,"ax",%progbits + 10394 .align 1 + 10395 .syntax unified + 10396 .thumb + 10397 .thumb_func + 10399 I2C_DMASlaveTransmitCplt: + 10400 .LVL734: + 10401 .LFB208: +6831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 10402 .loc 1 6831 1 is_stmt 1 view -0 + 10403 .cfi_startproc + 10404 @ args = 0, pretend = 0, frame = 0 + 10405 @ frame_needed = 0, uses_anonymous_args = 0 +6831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 10406 .loc 1 6831 1 is_stmt 0 view .LVU3647 + 10407 0000 08B5 push {r3, lr} + 10408 .LCFI117: + 10409 .cfi_def_cfa_offset 8 + 10410 .cfi_offset 3, -8 + 10411 .cfi_offset 14, -4 +6833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 10412 .loc 1 6833 3 is_stmt 1 view .LVU3648 +6833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 10413 .loc 1 6833 22 is_stmt 0 view .LVU3649 + 10414 0002 806B ldr r0, [r0, #56] + 10415 .LVL735: +6834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10416 .loc 1 6834 3 is_stmt 1 view .LVU3650 +6834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10417 .loc 1 6834 12 is_stmt 0 view .LVU3651 + 10418 0004 C36A ldr r3, [r0, #44] + 10419 .LVL736: +6836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10420 .loc 1 6836 3 is_stmt 1 view .LVU3652 +6836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10421 .loc 1 6836 6 is_stmt 0 view .LVU3653 + 10422 0006 002B cmp r3, #0 + 10423 0008 18BF it ne + 10424 000a B3F1807F cmpne r3, #16777216 + 10425 000e 00D0 beq .L662 + 10426 .LVL737: + 10427 .L659: +6851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10428 .loc 1 6851 1 view .LVU3654 + 10429 0010 08BD pop {r3, pc} + 10430 .LVL738: + 10431 .L662: +6839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10432 .loc 1 6839 5 is_stmt 1 view .LVU3655 +6839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10433 .loc 1 6839 9 is_stmt 0 view .LVU3656 + 10434 0012 0268 ldr r2, [r0] + ARM GAS /tmp/ccSHpINd.s page 377 + + +6839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10435 .loc 1 6839 19 view .LVU3657 + 10436 0014 1368 ldr r3, [r2] + 10437 .LVL739: +6839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10438 .loc 1 6839 25 view .LVU3658 + 10439 0016 23F48043 bic r3, r3, #16384 + 10440 001a 1360 str r3, [r2] +6843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10441 .loc 1 6843 5 is_stmt 1 view .LVU3659 + 10442 001c FFF7FEFF bl I2C_ITSlaveSeqCplt + 10443 .LVL740: +6850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10444 .loc 1 6850 3 view .LVU3660 +6851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10445 .loc 1 6851 1 is_stmt 0 view .LVU3661 + 10446 0020 F6E7 b .L659 + 10447 .cfi_endproc + 10448 .LFE208: + 10450 .section .text.I2C_DMASlaveReceiveCplt,"ax",%progbits + 10451 .align 1 + 10452 .syntax unified + 10453 .thumb + 10454 .thumb_func + 10456 I2C_DMASlaveReceiveCplt: + 10457 .LVL741: + 10458 .LFB210: +6919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 10459 .loc 1 6919 1 is_stmt 1 view -0 + 10460 .cfi_startproc + 10461 @ args = 0, pretend = 0, frame = 0 + 10462 @ frame_needed = 0, uses_anonymous_args = 0 +6919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 10463 .loc 1 6919 1 is_stmt 0 view .LVU3663 + 10464 0000 08B5 push {r3, lr} + 10465 .LCFI118: + 10466 .cfi_def_cfa_offset 8 + 10467 .cfi_offset 3, -8 + 10468 .cfi_offset 14, -4 +6921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 10469 .loc 1 6921 3 is_stmt 1 view .LVU3664 +6921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 10470 .loc 1 6921 22 is_stmt 0 view .LVU3665 + 10471 0002 806B ldr r0, [r0, #56] + 10472 .LVL742: +6922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10473 .loc 1 6922 3 is_stmt 1 view .LVU3666 +6922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10474 .loc 1 6922 12 is_stmt 0 view .LVU3667 + 10475 0004 C26A ldr r2, [r0, #44] + 10476 .LVL743: +6924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 10477 .loc 1 6924 3 is_stmt 1 view .LVU3668 +6924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 10478 .loc 1 6924 8 is_stmt 0 view .LVU3669 + 10479 0006 C36B ldr r3, [r0, #60] + 10480 0008 1B68 ldr r3, [r3] + ARM GAS /tmp/ccSHpINd.s page 378 + + + 10481 000a 5B68 ldr r3, [r3, #4] +6924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 10482 .loc 1 6924 6 view .LVU3670 + 10483 000c 13B9 cbnz r3, .L663 +6924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 10484 .loc 1 6924 53 discriminator 1 view .LVU3671 + 10485 000e 12F5803F cmn r2, #65536 + 10486 0012 00D1 bne .L666 + 10487 .LVL744: + 10488 .L663: +6939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10489 .loc 1 6939 1 view .LVU3672 + 10490 0014 08BD pop {r3, pc} + 10491 .LVL745: + 10492 .L666: +6928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10493 .loc 1 6928 5 is_stmt 1 view .LVU3673 +6928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10494 .loc 1 6928 9 is_stmt 0 view .LVU3674 + 10495 0016 0268 ldr r2, [r0] + 10496 .LVL746: +6928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10497 .loc 1 6928 19 view .LVU3675 + 10498 0018 1368 ldr r3, [r2] +6928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10499 .loc 1 6928 25 view .LVU3676 + 10500 001a 23F40043 bic r3, r3, #32768 + 10501 001e 1360 str r3, [r2] +6931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10502 .loc 1 6931 5 is_stmt 1 view .LVU3677 + 10503 0020 FFF7FEFF bl I2C_ITSlaveSeqCplt + 10504 .LVL747: +6938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10505 .loc 1 6938 3 view .LVU3678 +6939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10506 .loc 1 6939 1 is_stmt 0 view .LVU3679 + 10507 0024 F6E7 b .L663 + 10508 .cfi_endproc + 10509 .LFE210: + 10511 .section .text.HAL_I2C_AddrCallback,"ax",%progbits + 10512 .align 1 + 10513 .weak HAL_I2C_AddrCallback + 10514 .syntax unified + 10515 .thumb + 10516 .thumb_func + 10518 HAL_I2C_AddrCallback: + 10519 .LVL748: + 10520 .LFB181: +4775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10521 .loc 1 4775 1 is_stmt 1 view -0 + 10522 .cfi_startproc + 10523 @ args = 0, pretend = 0, frame = 0 + 10524 @ frame_needed = 0, uses_anonymous_args = 0 + 10525 @ link register save eliminated. +4777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(TransferDirection); + 10526 .loc 1 4777 3 view .LVU3681 +4778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(AddrMatchCode); + ARM GAS /tmp/ccSHpINd.s page 379 + + + 10527 .loc 1 4778 3 view .LVU3682 +4779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10528 .loc 1 4779 3 view .LVU3683 +4784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10529 .loc 1 4784 1 is_stmt 0 view .LVU3684 + 10530 0000 7047 bx lr + 10531 .cfi_endproc + 10532 .LFE181: + 10534 .section .text.I2C_ITAddrCplt,"ax",%progbits + 10535 .align 1 + 10536 .syntax unified + 10537 .thumb + 10538 .thumb_func + 10540 I2C_ITAddrCplt: + 10541 .LVL749: + 10542 .LFB198: +5958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint8_t transferdirection; + 10543 .loc 1 5958 1 is_stmt 1 view -0 + 10544 .cfi_startproc + 10545 @ args = 0, pretend = 0, frame = 0 + 10546 @ frame_needed = 0, uses_anonymous_args = 0 +5958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint8_t transferdirection; + 10547 .loc 1 5958 1 is_stmt 0 view .LVU3686 + 10548 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 10549 .LCFI119: + 10550 .cfi_def_cfa_offset 24 + 10551 .cfi_offset 3, -24 + 10552 .cfi_offset 4, -20 + 10553 .cfi_offset 5, -16 + 10554 .cfi_offset 6, -12 + 10555 .cfi_offset 7, -8 + 10556 .cfi_offset 14, -4 + 10557 0002 0446 mov r4, r0 +5959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t slaveaddrcode; + 10558 .loc 1 5959 3 is_stmt 1 view .LVU3687 +5960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t ownadd1code; + 10559 .loc 1 5960 3 view .LVU3688 +5961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t ownadd2code; + 10560 .loc 1 5961 3 view .LVU3689 +5962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10561 .loc 1 5962 3 view .LVU3690 +5965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10562 .loc 1 5965 3 view .LVU3691 +5968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10563 .loc 1 5968 3 view .LVU3692 +5968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10564 .loc 1 5968 22 is_stmt 0 view .LVU3693 + 10565 0004 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 +5968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10566 .loc 1 5968 6 view .LVU3694 + 10567 0008 03F02803 and r3, r3, #40 + 10568 000c 282B cmp r3, #40 + 10569 000e 06D0 beq .L674 +6040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10570 .loc 1 6040 5 is_stmt 1 view .LVU3695 + 10571 0010 0368 ldr r3, [r0] + 10572 0012 0822 movs r2, #8 + ARM GAS /tmp/ccSHpINd.s page 380 + + + 10573 0014 DA61 str r2, [r3, #28] +6043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10574 .loc 1 6043 5 view .LVU3696 +6043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10575 .loc 1 6043 5 view .LVU3697 + 10576 0016 0023 movs r3, #0 + 10577 0018 80F84030 strb r3, [r0, #64] +6043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10578 .loc 1 6043 5 discriminator 1 view .LVU3698 + 10579 .LVL750: + 10580 .L668: +6045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10581 .loc 1 6045 1 is_stmt 0 view .LVU3699 + 10582 001c F8BD pop {r3, r4, r5, r6, r7, pc} + 10583 .LVL751: + 10584 .L674: +5970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + 10585 .loc 1 5970 5 is_stmt 1 view .LVU3700 +5970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + 10586 .loc 1 5970 25 is_stmt 0 view .LVU3701 + 10587 001e 0368 ldr r3, [r0] + 10588 0020 9E69 ldr r6, [r3, #24] +5970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + 10589 .loc 1 5970 23 view .LVU3702 + 10590 0022 C6F30046 ubfx r6, r6, #16, #1 + 10591 .LVL752: +5971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + 10592 .loc 1 5971 5 is_stmt 1 view .LVU3703 +5971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + 10593 .loc 1 5971 25 is_stmt 0 view .LVU3704 + 10594 0026 9A69 ldr r2, [r3, #24] + 10595 0028 120C lsrs r2, r2, #16 +5971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + 10596 .loc 1 5971 23 view .LVU3705 + 10597 002a 02F0FE05 and r5, r2, #254 + 10598 .LVL753: +5972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + 10599 .loc 1 5972 5 is_stmt 1 view .LVU3706 +5972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + 10600 .loc 1 5972 25 is_stmt 0 view .LVU3707 + 10601 002e 9A68 ldr r2, [r3, #8] +5972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + 10602 .loc 1 5972 23 view .LVU3708 + 10603 0030 C2F30902 ubfx r2, r2, #0, #10 + 10604 .LVL754: +5973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10605 .loc 1 5973 5 is_stmt 1 view .LVU3709 +5973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10606 .loc 1 5973 25 is_stmt 0 view .LVU3710 + 10607 0034 DF68 ldr r7, [r3, #12] +5973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10608 .loc 1 5973 23 view .LVU3711 + 10609 0036 07F0FE07 and r7, r7, #254 + 10610 .LVL755: +5976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10611 .loc 1 5976 5 is_stmt 1 view .LVU3712 +5976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 381 + + + 10612 .loc 1 5976 19 is_stmt 0 view .LVU3713 + 10613 003a C168 ldr r1, [r0, #12] + 10614 .LVL756: +5976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10615 .loc 1 5976 8 view .LVU3714 + 10616 003c 0229 cmp r1, #2 + 10617 003e 22D1 bne .L670 +5978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10618 .loc 1 5978 7 is_stmt 1 view .LVU3715 +5978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10619 .loc 1 5978 44 is_stmt 0 view .LVU3716 + 10620 0040 85EAD215 eor r5, r5, r2, lsr #7 + 10621 .LVL757: +5978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10622 .loc 1 5978 10 view .LVU3717 + 10623 0044 15F0060F tst r5, #6 + 10624 0048 10D1 bne .L671 +5980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->AddrEventCount++; + 10625 .loc 1 5980 9 is_stmt 1 view .LVU3718 + 10626 .LVL758: +5981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->AddrEventCount == 2U) + 10627 .loc 1 5981 9 view .LVU3719 +5981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->AddrEventCount == 2U) + 10628 .loc 1 5981 13 is_stmt 0 view .LVU3720 + 10629 004a 816C ldr r1, [r0, #72] +5981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->AddrEventCount == 2U) + 10630 .loc 1 5981 29 view .LVU3721 + 10631 004c 0131 adds r1, r1, #1 + 10632 004e 8164 str r1, [r0, #72] +5982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10633 .loc 1 5982 9 is_stmt 1 view .LVU3722 +5982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10634 .loc 1 5982 17 is_stmt 0 view .LVU3723 + 10635 0050 816C ldr r1, [r0, #72] +5982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10636 .loc 1 5982 12 view .LVU3724 + 10637 0052 0229 cmp r1, #2 + 10638 0054 E2D1 bne .L668 +5985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10639 .loc 1 5985 11 is_stmt 1 view .LVU3725 +5985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10640 .loc 1 5985 32 is_stmt 0 view .LVU3726 + 10641 0056 0021 movs r1, #0 + 10642 0058 8164 str r1, [r0, #72] +5988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10643 .loc 1 5988 11 is_stmt 1 view .LVU3727 + 10644 005a 0820 movs r0, #8 + 10645 .LVL759: +5988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10646 .loc 1 5988 11 is_stmt 0 view .LVU3728 + 10647 005c D861 str r0, [r3, #28] +5991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10648 .loc 1 5991 11 is_stmt 1 view .LVU3729 +5991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10649 .loc 1 5991 11 view .LVU3730 + 10650 005e 84F84010 strb r1, [r4, #64] +5991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 382 + + + 10651 .loc 1 5991 11 view .LVU3731 +5997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10652 .loc 1 5997 11 view .LVU3732 + 10653 0062 3146 mov r1, r6 + 10654 0064 2046 mov r0, r4 + 10655 0066 FFF7FEFF bl HAL_I2C_AddrCallback + 10656 .LVL760: +5997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10657 .loc 1 5997 11 is_stmt 0 view .LVU3733 + 10658 006a D7E7 b .L668 + 10659 .LVL761: + 10660 .L671: +6003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10661 .loc 1 6003 9 is_stmt 1 view .LVU3734 +6006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10662 .loc 1 6006 9 view .LVU3735 + 10663 006c 4FF40041 mov r1, #32768 + 10664 0070 FFF7FEFF bl I2C_Disable_IRQ + 10665 .LVL762: +6009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10666 .loc 1 6009 9 view .LVU3736 +6009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10667 .loc 1 6009 9 view .LVU3737 + 10668 0074 0023 movs r3, #0 + 10669 0076 84F84030 strb r3, [r4, #64] +6009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10670 .loc 1 6009 9 view .LVU3738 +6015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10671 .loc 1 6015 9 view .LVU3739 + 10672 007a 3A46 mov r2, r7 + 10673 007c 3146 mov r1, r6 + 10674 007e 2046 mov r0, r4 + 10675 0080 FFF7FEFF bl HAL_I2C_AddrCallback + 10676 .LVL763: + 10677 0084 CAE7 b .L668 + 10678 .LVL764: + 10679 .L670: +6023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10680 .loc 1 6023 7 view .LVU3740 + 10681 0086 4FF40041 mov r1, #32768 + 10682 008a FFF7FEFF bl I2C_Disable_IRQ + 10683 .LVL765: +6026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10684 .loc 1 6026 7 view .LVU3741 +6026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10685 .loc 1 6026 7 view .LVU3742 + 10686 008e 0023 movs r3, #0 + 10687 0090 84F84030 strb r3, [r4, #64] +6026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10688 .loc 1 6026 7 view .LVU3743 +6032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10689 .loc 1 6032 7 view .LVU3744 + 10690 0094 2A46 mov r2, r5 + 10691 0096 3146 mov r1, r6 + 10692 0098 2046 mov r0, r4 + 10693 009a FFF7FEFF bl HAL_I2C_AddrCallback + 10694 .LVL766: + ARM GAS /tmp/ccSHpINd.s page 383 + + + 10695 009e BDE7 b .L668 + 10696 .cfi_endproc + 10697 .LFE198: + 10699 .section .text.HAL_I2C_ListenCpltCallback,"ax",%progbits + 10700 .align 1 + 10701 .weak HAL_I2C_ListenCpltCallback + 10702 .syntax unified + 10703 .thumb + 10704 .thumb_func + 10706 HAL_I2C_ListenCpltCallback: + 10707 .LVL767: + 10708 .LFB182: +4793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10709 .loc 1 4793 1 view -0 + 10710 .cfi_startproc + 10711 @ args = 0, pretend = 0, frame = 0 + 10712 @ frame_needed = 0, uses_anonymous_args = 0 + 10713 @ link register save eliminated. +4795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10714 .loc 1 4795 3 view .LVU3746 +4800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10715 .loc 1 4800 1 is_stmt 0 view .LVU3747 + 10716 0000 7047 bx lr + 10717 .cfi_endproc + 10718 .LFE182: + 10720 .section .text.I2C_ITListenCplt,"ax",%progbits + 10721 .align 1 + 10722 .syntax unified + 10723 .thumb + 10724 .thumb_func + 10726 I2C_ITListenCplt: + 10727 .LVL768: + 10728 .LFB203: +6539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset handle parameters */ + 10729 .loc 1 6539 1 is_stmt 1 view -0 + 10730 .cfi_startproc + 10731 @ args = 0, pretend = 0, frame = 0 + 10732 @ frame_needed = 0, uses_anonymous_args = 0 +6539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Reset handle parameters */ + 10733 .loc 1 6539 1 is_stmt 0 view .LVU3749 + 10734 0000 10B5 push {r4, lr} + 10735 .LCFI120: + 10736 .cfi_def_cfa_offset 8 + 10737 .cfi_offset 4, -8 + 10738 .cfi_offset 14, -4 + 10739 0002 0446 mov r4, r0 +6541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10740 .loc 1 6541 3 is_stmt 1 view .LVU3750 +6541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10741 .loc 1 6541 21 is_stmt 0 view .LVU3751 + 10742 0004 174B ldr r3, .L679 + 10743 0006 C362 str r3, [r0, #44] +6542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 10744 .loc 1 6542 3 is_stmt 1 view .LVU3752 +6542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 10745 .loc 1 6542 23 is_stmt 0 view .LVU3753 + 10746 0008 0023 movs r3, #0 + ARM GAS /tmp/ccSHpINd.s page 384 + + + 10747 000a 0363 str r3, [r0, #48] +6543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 10748 .loc 1 6543 3 is_stmt 1 view .LVU3754 +6543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 10749 .loc 1 6543 15 is_stmt 0 view .LVU3755 + 10750 000c 2022 movs r2, #32 + 10751 000e 80F84120 strb r2, [r0, #65] +6544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 10752 .loc 1 6544 3 is_stmt 1 view .LVU3756 +6544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 10753 .loc 1 6544 14 is_stmt 0 view .LVU3757 + 10754 0012 80F84230 strb r3, [r0, #66] +6545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10755 .loc 1 6545 3 is_stmt 1 view .LVU3758 +6545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10756 .loc 1 6545 17 is_stmt 0 view .LVU3759 + 10757 0016 4363 str r3, [r0, #52] +6548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10758 .loc 1 6548 3 is_stmt 1 view .LVU3760 +6548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10759 .loc 1 6548 6 is_stmt 0 view .LVU3761 + 10760 0018 11F0040F tst r1, #4 + 10761 001c 13D0 beq .L677 +6551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10762 .loc 1 6551 5 is_stmt 1 view .LVU3762 +6551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10763 .loc 1 6551 36 is_stmt 0 view .LVU3763 + 10764 001e 0368 ldr r3, [r0] +6551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10765 .loc 1 6551 46 view .LVU3764 + 10766 0020 5A6A ldr r2, [r3, #36] +6551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10767 .loc 1 6551 10 view .LVU3765 + 10768 0022 436A ldr r3, [r0, #36] +6551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10769 .loc 1 6551 21 view .LVU3766 + 10770 0024 1A70 strb r2, [r3] +6554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10771 .loc 1 6554 5 is_stmt 1 view .LVU3767 +6554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10772 .loc 1 6554 9 is_stmt 0 view .LVU3768 + 10773 0026 436A ldr r3, [r0, #36] +6554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10774 .loc 1 6554 19 view .LVU3769 + 10775 0028 0133 adds r3, r3, #1 + 10776 002a 4362 str r3, [r0, #36] +6556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10777 .loc 1 6556 5 is_stmt 1 view .LVU3770 +6556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10778 .loc 1 6556 14 is_stmt 0 view .LVU3771 + 10779 002c 038D ldrh r3, [r0, #40] +6556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10780 .loc 1 6556 8 view .LVU3772 + 10781 002e 53B1 cbz r3, .L677 +6558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 10782 .loc 1 6558 7 is_stmt 1 view .LVU3773 +6558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + ARM GAS /tmp/ccSHpINd.s page 385 + + + 10783 .loc 1 6558 21 is_stmt 0 view .LVU3774 + 10784 0030 013B subs r3, r3, #1 + 10785 0032 0385 strh r3, [r0, #40] @ movhi +6559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10786 .loc 1 6559 7 is_stmt 1 view .LVU3775 +6559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10787 .loc 1 6559 11 is_stmt 0 view .LVU3776 + 10788 0034 438D ldrh r3, [r0, #42] + 10789 0036 9BB2 uxth r3, r3 +6559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10790 .loc 1 6559 22 view .LVU3777 + 10791 0038 013B subs r3, r3, #1 + 10792 003a 9BB2 uxth r3, r3 + 10793 003c 4385 strh r3, [r0, #42] @ movhi +6562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10794 .loc 1 6562 7 is_stmt 1 view .LVU3778 +6562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10795 .loc 1 6562 11 is_stmt 0 view .LVU3779 + 10796 003e 436C ldr r3, [r0, #68] +6562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 10797 .loc 1 6562 23 view .LVU3780 + 10798 0040 43F00403 orr r3, r3, #4 + 10799 0044 4364 str r3, [r0, #68] + 10800 .L677: +6567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10801 .loc 1 6567 3 is_stmt 1 view .LVU3781 + 10802 0046 48F20301 movw r1, #32771 + 10803 .LVL769: +6567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10804 .loc 1 6567 3 is_stmt 0 view .LVU3782 + 10805 004a 2046 mov r0, r4 + 10806 .LVL770: +6567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10807 .loc 1 6567 3 view .LVU3783 + 10808 004c FFF7FEFF bl I2C_Disable_IRQ + 10809 .LVL771: +6570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10810 .loc 1 6570 3 is_stmt 1 view .LVU3784 + 10811 0050 2368 ldr r3, [r4] + 10812 0052 1022 movs r2, #16 + 10813 0054 DA61 str r2, [r3, #28] +6573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10814 .loc 1 6573 3 view .LVU3785 +6573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10815 .loc 1 6573 3 view .LVU3786 + 10816 0056 0023 movs r3, #0 + 10817 0058 84F84030 strb r3, [r4, #64] +6573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10818 .loc 1 6573 3 view .LVU3787 +6579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10819 .loc 1 6579 3 view .LVU3788 + 10820 005c 2046 mov r0, r4 + 10821 005e FFF7FEFF bl HAL_I2C_ListenCpltCallback + 10822 .LVL772: +6581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10823 .loc 1 6581 1 is_stmt 0 view .LVU3789 + 10824 0062 10BD pop {r4, pc} + ARM GAS /tmp/ccSHpINd.s page 386 + + + 10825 .LVL773: + 10826 .L680: +6581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10827 .loc 1 6581 1 view .LVU3790 + 10828 .align 2 + 10829 .L679: + 10830 0064 0000FFFF .word -65536 + 10831 .cfi_endproc + 10832 .LFE203: + 10834 .section .text.HAL_I2C_MemTxCpltCallback,"ax",%progbits + 10835 .align 1 + 10836 .weak HAL_I2C_MemTxCpltCallback + 10837 .syntax unified + 10838 .thumb + 10839 .thumb_func + 10841 HAL_I2C_MemTxCpltCallback: + 10842 .LVL774: + 10843 .LFB183: +4809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10844 .loc 1 4809 1 is_stmt 1 view -0 + 10845 .cfi_startproc + 10846 @ args = 0, pretend = 0, frame = 0 + 10847 @ frame_needed = 0, uses_anonymous_args = 0 + 10848 @ link register save eliminated. +4811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10849 .loc 1 4811 3 view .LVU3792 +4816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10850 .loc 1 4816 1 is_stmt 0 view .LVU3793 + 10851 0000 7047 bx lr + 10852 .cfi_endproc + 10853 .LFE183: + 10855 .section .text.HAL_I2C_MemRxCpltCallback,"ax",%progbits + 10856 .align 1 + 10857 .weak HAL_I2C_MemRxCpltCallback + 10858 .syntax unified + 10859 .thumb + 10860 .thumb_func + 10862 HAL_I2C_MemRxCpltCallback: + 10863 .LVL775: + 10864 .LFB184: +4825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10865 .loc 1 4825 1 is_stmt 1 view -0 + 10866 .cfi_startproc + 10867 @ args = 0, pretend = 0, frame = 0 + 10868 @ frame_needed = 0, uses_anonymous_args = 0 + 10869 @ link register save eliminated. +4827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10870 .loc 1 4827 3 view .LVU3795 +4832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10871 .loc 1 4832 1 is_stmt 0 view .LVU3796 + 10872 0000 7047 bx lr + 10873 .cfi_endproc + 10874 .LFE184: + 10876 .section .text.HAL_I2C_ErrorCallback,"ax",%progbits + 10877 .align 1 + 10878 .weak HAL_I2C_ErrorCallback + 10879 .syntax unified + ARM GAS /tmp/ccSHpINd.s page 387 + + + 10880 .thumb + 10881 .thumb_func + 10883 HAL_I2C_ErrorCallback: + 10884 .LVL776: + 10885 .LFB185: +4841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10886 .loc 1 4841 1 is_stmt 1 view -0 + 10887 .cfi_startproc + 10888 @ args = 0, pretend = 0, frame = 0 + 10889 @ frame_needed = 0, uses_anonymous_args = 0 + 10890 @ link register save eliminated. +4843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10891 .loc 1 4843 3 view .LVU3798 +4848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10892 .loc 1 4848 1 is_stmt 0 view .LVU3799 + 10893 0000 7047 bx lr + 10894 .cfi_endproc + 10895 .LFE185: + 10897 .section .text.HAL_I2C_AbortCpltCallback,"ax",%progbits + 10898 .align 1 + 10899 .weak HAL_I2C_AbortCpltCallback + 10900 .syntax unified + 10901 .thumb + 10902 .thumb_func + 10904 HAL_I2C_AbortCpltCallback: + 10905 .LVL777: + 10906 .LFB186: +4857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10907 .loc 1 4857 1 is_stmt 1 view -0 + 10908 .cfi_startproc + 10909 @ args = 0, pretend = 0, frame = 0 + 10910 @ frame_needed = 0, uses_anonymous_args = 0 + 10911 @ link register save eliminated. +4859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10912 .loc 1 4859 3 view .LVU3801 +4864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10913 .loc 1 4864 1 is_stmt 0 view .LVU3802 + 10914 0000 7047 bx lr + 10915 .cfi_endproc + 10916 .LFE186: + 10918 .section .text.I2C_TreatErrorCallback,"ax",%progbits + 10919 .align 1 + 10920 .syntax unified + 10921 .thumb + 10922 .thumb_func + 10924 I2C_TreatErrorCallback: + 10925 .LVL778: + 10926 .LFB205: +6721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_ABORT) + 10927 .loc 1 6721 1 is_stmt 1 view -0 + 10928 .cfi_startproc + 10929 @ args = 0, pretend = 0, frame = 0 + 10930 @ frame_needed = 0, uses_anonymous_args = 0 +6721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_ABORT) + 10931 .loc 1 6721 1 is_stmt 0 view .LVU3804 + 10932 0000 08B5 push {r3, lr} + 10933 .LCFI121: + ARM GAS /tmp/ccSHpINd.s page 388 + + + 10934 .cfi_def_cfa_offset 8 + 10935 .cfi_offset 3, -8 + 10936 .cfi_offset 14, -4 +6722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10937 .loc 1 6722 3 is_stmt 1 view .LVU3805 +6722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10938 .loc 1 6722 11 is_stmt 0 view .LVU3806 + 10939 0002 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 10940 0006 DBB2 uxtb r3, r3 +6722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 10941 .loc 1 6722 6 view .LVU3807 + 10942 0008 602B cmp r3, #96 + 10943 000a 06D0 beq .L689 +6739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10944 .loc 1 6739 5 is_stmt 1 view .LVU3808 +6739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10945 .loc 1 6739 25 is_stmt 0 view .LVU3809 + 10946 000c 0023 movs r3, #0 + 10947 000e 0363 str r3, [r0, #48] +6742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10948 .loc 1 6742 5 is_stmt 1 view .LVU3810 +6742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10949 .loc 1 6742 5 view .LVU3811 + 10950 0010 80F84030 strb r3, [r0, #64] +6742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10951 .loc 1 6742 5 view .LVU3812 +6748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10952 .loc 1 6748 5 view .LVU3813 + 10953 0014 FFF7FEFF bl HAL_I2C_ErrorCallback + 10954 .LVL779: + 10955 .L685: +6751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10956 .loc 1 6751 1 is_stmt 0 view .LVU3814 + 10957 0018 08BD pop {r3, pc} + 10958 .LVL780: + 10959 .L689: +6724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10960 .loc 1 6724 5 is_stmt 1 view .LVU3815 +6724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10961 .loc 1 6724 17 is_stmt 0 view .LVU3816 + 10962 001a 2023 movs r3, #32 + 10963 001c 80F84130 strb r3, [r0, #65] +6725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10964 .loc 1 6725 5 is_stmt 1 view .LVU3817 +6725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10965 .loc 1 6725 25 is_stmt 0 view .LVU3818 + 10966 0020 0023 movs r3, #0 + 10967 0022 0363 str r3, [r0, #48] +6728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10968 .loc 1 6728 5 is_stmt 1 view .LVU3819 +6728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10969 .loc 1 6728 5 view .LVU3820 + 10970 0024 80F84030 strb r3, [r0, #64] +6728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 10971 .loc 1 6728 5 view .LVU3821 +6734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10972 .loc 1 6734 5 view .LVU3822 + ARM GAS /tmp/ccSHpINd.s page 389 + + + 10973 0028 FFF7FEFF bl HAL_I2C_AbortCpltCallback + 10974 .LVL781: +6734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10975 .loc 1 6734 5 is_stmt 0 view .LVU3823 + 10976 002c F4E7 b .L685 + 10977 .cfi_endproc + 10978 .LFE205: + 10980 .section .text.I2C_ITError,"ax",%progbits + 10981 .align 1 + 10982 .syntax unified + 10983 .thumb + 10984 .thumb_func + 10986 I2C_ITError: + 10987 .LVL782: + 10988 .LFB204: +6590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; + 10989 .loc 1 6590 1 is_stmt 1 view -0 + 10990 .cfi_startproc + 10991 @ args = 0, pretend = 0, frame = 0 + 10992 @ frame_needed = 0, uses_anonymous_args = 0 +6590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; + 10993 .loc 1 6590 1 is_stmt 0 view .LVU3825 + 10994 0000 10B5 push {r4, lr} + 10995 .LCFI122: + 10996 .cfi_def_cfa_offset 8 + 10997 .cfi_offset 4, -8 + 10998 .cfi_offset 14, -4 + 10999 0002 0446 mov r4, r0 +6591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11000 .loc 1 6591 3 is_stmt 1 view .LVU3826 +6591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11001 .loc 1 6591 24 is_stmt 0 view .LVU3827 + 11002 0004 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 11003 .LVL783: +6593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11004 .loc 1 6593 3 is_stmt 1 view .LVU3828 +6596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 11005 .loc 1 6596 3 view .LVU3829 +6596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 11006 .loc 1 6596 23 is_stmt 0 view .LVU3830 + 11007 0008 0022 movs r2, #0 + 11008 000a 80F84220 strb r2, [r0, #66] +6597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = 0U; + 11009 .loc 1 6597 3 is_stmt 1 view .LVU3831 +6597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = 0U; + 11010 .loc 1 6597 23 is_stmt 0 view .LVU3832 + 11011 000e 4548 ldr r0, .L703 + 11012 .LVL784: +6597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount = 0U; + 11013 .loc 1 6597 23 view .LVU3833 + 11014 0010 E062 str r0, [r4, #44] +6598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11015 .loc 1 6598 3 is_stmt 1 view .LVU3834 +6598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11016 .loc 1 6598 23 is_stmt 0 view .LVU3835 + 11017 0012 6285 strh r2, [r4, #42] @ movhi +6601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 390 + + + 11018 .loc 1 6601 3 is_stmt 1 view .LVU3836 +6601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11019 .loc 1 6601 7 is_stmt 0 view .LVU3837 + 11020 0014 626C ldr r2, [r4, #68] +6601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11021 .loc 1 6601 19 view .LVU3838 + 11022 0016 0A43 orrs r2, r2, r1 + 11023 0018 6264 str r2, [r4, #68] +6604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + 11024 .loc 1 6604 3 is_stmt 1 view .LVU3839 +6605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + 11025 .loc 1 6605 50 is_stmt 0 view .LVU3840 + 11026 001a 283B subs r3, r3, #40 + 11027 .LVL785: +6605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + 11028 .loc 1 6605 50 view .LVU3841 + 11029 001c DBB2 uxtb r3, r3 + 11030 .LVL786: +6604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + 11031 .loc 1 6604 6 view .LVU3842 + 11032 001e 022B cmp r3, #2 + 11033 0020 2DD8 bhi .L691 +6609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11034 .loc 1 6609 5 is_stmt 1 view .LVU3843 + 11035 0022 0321 movs r1, #3 + 11036 .LVL787: +6609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11037 .loc 1 6609 5 is_stmt 0 view .LVU3844 + 11038 0024 2046 mov r0, r4 + 11039 0026 FFF7FEFF bl I2C_Disable_IRQ + 11040 .LVL788: +6612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 11041 .loc 1 6612 5 is_stmt 1 view .LVU3845 +6612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 11042 .loc 1 6612 25 is_stmt 0 view .LVU3846 + 11043 002a 2823 movs r3, #40 + 11044 002c 84F84130 strb r3, [r4, #65] +6613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11045 .loc 1 6613 5 is_stmt 1 view .LVU3847 +6613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11046 .loc 1 6613 25 is_stmt 0 view .LVU3848 + 11047 0030 3D4B ldr r3, .L703+4 + 11048 0032 6363 str r3, [r4, #52] + 11049 .L692: +6648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11050 .loc 1 6648 3 is_stmt 1 view .LVU3849 +6648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11051 .loc 1 6648 20 is_stmt 0 view .LVU3850 + 11052 0034 236B ldr r3, [r4, #48] + 11053 .LVL789: +6650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + 11054 .loc 1 6650 3 is_stmt 1 view .LVU3851 +6650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + 11055 .loc 1 6650 12 is_stmt 0 view .LVU3852 + 11056 0036 A26B ldr r2, [r4, #56] +6650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + 11057 .loc 1 6650 6 view .LVU3853 + ARM GAS /tmp/ccSHpINd.s page 391 + + + 11058 0038 002A cmp r2, #0 + 11059 003a 49D0 beq .L695 +6650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + 11060 .loc 1 6650 30 discriminator 1 view .LVU3854 + 11061 003c 212B cmp r3, #33 + 11062 003e 18BF it ne + 11063 0040 112B cmpne r3, #17 + 11064 0042 45D1 bne .L695 +6653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11065 .loc 1 6653 5 is_stmt 1 view .LVU3855 +6653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11066 .loc 1 6653 14 is_stmt 0 view .LVU3856 + 11067 0044 2368 ldr r3, [r4] + 11068 .LVL790: +6653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11069 .loc 1 6653 24 view .LVU3857 + 11070 0046 1A68 ldr r2, [r3] +6653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11071 .loc 1 6653 8 view .LVU3858 + 11072 0048 12F4804F tst r2, #16384 + 11073 004c 03D0 beq .L696 +6655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11074 .loc 1 6655 7 is_stmt 1 view .LVU3859 +6655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11075 .loc 1 6655 21 is_stmt 0 view .LVU3860 + 11076 004e 1A68 ldr r2, [r3] +6655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11077 .loc 1 6655 27 view .LVU3861 + 11078 0050 22F48042 bic r2, r2, #16384 + 11079 0054 1A60 str r2, [r3] + 11080 .L696: +6658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11081 .loc 1 6658 5 is_stmt 1 view .LVU3862 +6658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11082 .loc 1 6658 9 is_stmt 0 view .LVU3863 + 11083 0056 A06B ldr r0, [r4, #56] + 11084 0058 FFF7FEFF bl HAL_DMA_GetState + 11085 .LVL791: +6658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11086 .loc 1 6658 8 discriminator 1 view .LVU3864 + 11087 005c 0128 cmp r0, #1 + 11088 005e 33D0 beq .L697 +6662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11089 .loc 1 6662 7 is_stmt 1 view .LVU3865 +6662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11090 .loc 1 6662 11 is_stmt 0 view .LVU3866 + 11091 0060 A36B ldr r3, [r4, #56] +6662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11092 .loc 1 6662 39 view .LVU3867 + 11093 0062 324A ldr r2, .L703+8 + 11094 0064 1A65 str r2, [r3, #80] +6665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11095 .loc 1 6665 7 is_stmt 1 view .LVU3868 +6665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11096 .loc 1 6665 7 view .LVU3869 + 11097 0066 0023 movs r3, #0 + 11098 0068 84F84030 strb r3, [r4, #64] + ARM GAS /tmp/ccSHpINd.s page 392 + + +6665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11099 .loc 1 6665 7 view .LVU3870 +6668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11100 .loc 1 6668 7 view .LVU3871 +6668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11101 .loc 1 6668 11 is_stmt 0 view .LVU3872 + 11102 006c A06B ldr r0, [r4, #56] + 11103 006e FFF7FEFF bl HAL_DMA_Abort_IT + 11104 .LVL792: +6668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11105 .loc 1 6668 10 discriminator 1 view .LVU3873 + 11106 0072 0028 cmp r0, #0 + 11107 0074 55D0 beq .L690 +6671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11108 .loc 1 6671 9 is_stmt 1 view .LVU3874 +6671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11109 .loc 1 6671 13 is_stmt 0 view .LVU3875 + 11110 0076 A06B ldr r0, [r4, #56] +6671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11111 .loc 1 6671 21 view .LVU3876 + 11112 0078 036D ldr r3, [r0, #80] +6671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11113 .loc 1 6671 9 view .LVU3877 + 11114 007a 9847 blx r3 + 11115 .LVL793: + 11116 007c 51E0 b .L690 + 11117 .LVL794: + 11118 .L691: +6618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11119 .loc 1 6618 5 is_stmt 1 view .LVU3878 + 11120 007e 48F20301 movw r1, #32771 + 11121 .LVL795: +6618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11122 .loc 1 6618 5 is_stmt 0 view .LVU3879 + 11123 0082 2046 mov r0, r4 + 11124 0084 FFF7FEFF bl I2C_Disable_IRQ + 11125 .LVL796: +6621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11126 .loc 1 6621 5 is_stmt 1 view .LVU3880 + 11127 0088 2046 mov r0, r4 + 11128 008a FFF7FEFF bl I2C_Flush_TXDR + 11129 .LVL797: +6625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11130 .loc 1 6625 5 view .LVU3881 +6625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11131 .loc 1 6625 13 is_stmt 0 view .LVU3882 + 11132 008e 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11133 0092 DBB2 uxtb r3, r3 +6625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11134 .loc 1 6625 8 view .LVU3883 + 11135 0094 602B cmp r3, #96 + 11136 0096 14D0 beq .L693 +6628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11137 .loc 1 6628 7 is_stmt 1 view .LVU3884 +6628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11138 .loc 1 6628 27 is_stmt 0 view .LVU3885 + 11139 0098 2023 movs r3, #32 + ARM GAS /tmp/ccSHpINd.s page 393 + + + 11140 009a 84F84130 strb r3, [r4, #65] +6631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11141 .loc 1 6631 7 is_stmt 1 view .LVU3886 +6631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11142 .loc 1 6631 11 is_stmt 0 view .LVU3887 + 11143 009e 2368 ldr r3, [r4] + 11144 00a0 9A69 ldr r2, [r3, #24] +6631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11145 .loc 1 6631 10 view .LVU3888 + 11146 00a2 12F0200F tst r2, #32 + 11147 00a6 0CD0 beq .L693 +6633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11148 .loc 1 6633 9 is_stmt 1 view .LVU3889 +6633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11149 .loc 1 6633 13 is_stmt 0 view .LVU3890 + 11150 00a8 9A69 ldr r2, [r3, #24] +6633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11151 .loc 1 6633 12 view .LVU3891 + 11152 00aa 12F0100F tst r2, #16 + 11153 00ae 05D0 beq .L694 +6635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 11154 .loc 1 6635 11 is_stmt 1 view .LVU3892 + 11155 00b0 1022 movs r2, #16 + 11156 00b2 DA61 str r2, [r3, #28] +6636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11157 .loc 1 6636 11 view .LVU3893 +6636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11158 .loc 1 6636 15 is_stmt 0 view .LVU3894 + 11159 00b4 636C ldr r3, [r4, #68] +6636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11160 .loc 1 6636 27 view .LVU3895 + 11161 00b6 43F00403 orr r3, r3, #4 + 11162 00ba 6364 str r3, [r4, #68] + 11163 .L694: +6640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11164 .loc 1 6640 9 is_stmt 1 view .LVU3896 + 11165 00bc 2368 ldr r3, [r4] + 11166 00be 2022 movs r2, #32 + 11167 00c0 DA61 str r2, [r3, #28] + 11168 .L693: +6644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11169 .loc 1 6644 5 view .LVU3897 +6644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11170 .loc 1 6644 25 is_stmt 0 view .LVU3898 + 11171 00c2 0023 movs r3, #0 + 11172 00c4 6363 str r3, [r4, #52] + 11173 00c6 B5E7 b .L692 + 11174 .LVL798: + 11175 .L697: +6676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11176 .loc 1 6676 7 is_stmt 1 view .LVU3899 + 11177 00c8 2046 mov r0, r4 + 11178 00ca FFF7FEFF bl I2C_TreatErrorCallback + 11179 .LVL799: + 11180 00ce 28E0 b .L690 + 11181 .LVL800: + 11182 .L695: + ARM GAS /tmp/ccSHpINd.s page 394 + + +6680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + 11183 .loc 1 6680 8 view .LVU3900 +6680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + 11184 .loc 1 6680 17 is_stmt 0 view .LVU3901 + 11185 00d0 E26B ldr r2, [r4, #60] +6680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + 11186 .loc 1 6680 11 view .LVU3902 + 11187 00d2 1AB3 cbz r2, .L699 +6680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + 11188 .loc 1 6680 35 discriminator 1 view .LVU3903 + 11189 00d4 222B cmp r3, #34 + 11190 00d6 18BF it ne + 11191 00d8 122B cmpne r3, #18 + 11192 00da 1FD1 bne .L699 +6683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11193 .loc 1 6683 5 is_stmt 1 view .LVU3904 +6683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11194 .loc 1 6683 14 is_stmt 0 view .LVU3905 + 11195 00dc 2368 ldr r3, [r4] + 11196 .LVL801: +6683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11197 .loc 1 6683 24 view .LVU3906 + 11198 00de 1A68 ldr r2, [r3] +6683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11199 .loc 1 6683 8 view .LVU3907 + 11200 00e0 12F4004F tst r2, #32768 + 11201 00e4 03D0 beq .L700 +6685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11202 .loc 1 6685 7 is_stmt 1 view .LVU3908 +6685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11203 .loc 1 6685 21 is_stmt 0 view .LVU3909 + 11204 00e6 1A68 ldr r2, [r3] +6685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11205 .loc 1 6685 27 view .LVU3910 + 11206 00e8 22F40042 bic r2, r2, #32768 + 11207 00ec 1A60 str r2, [r3] + 11208 .L700: +6688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11209 .loc 1 6688 5 is_stmt 1 view .LVU3911 +6688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11210 .loc 1 6688 9 is_stmt 0 view .LVU3912 + 11211 00ee E06B ldr r0, [r4, #60] + 11212 00f0 FFF7FEFF bl HAL_DMA_GetState + 11213 .LVL802: +6688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11214 .loc 1 6688 8 discriminator 1 view .LVU3913 + 11215 00f4 0128 cmp r0, #1 + 11216 00f6 0DD0 beq .L701 +6692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11217 .loc 1 6692 7 is_stmt 1 view .LVU3914 +6692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11218 .loc 1 6692 11 is_stmt 0 view .LVU3915 + 11219 00f8 E36B ldr r3, [r4, #60] +6692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11220 .loc 1 6692 39 view .LVU3916 + 11221 00fa 0C4A ldr r2, .L703+8 + 11222 00fc 1A65 str r2, [r3, #80] + ARM GAS /tmp/ccSHpINd.s page 395 + + +6695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11223 .loc 1 6695 7 is_stmt 1 view .LVU3917 +6695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11224 .loc 1 6695 7 view .LVU3918 + 11225 00fe 0023 movs r3, #0 + 11226 0100 84F84030 strb r3, [r4, #64] +6695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11227 .loc 1 6695 7 view .LVU3919 +6698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11228 .loc 1 6698 7 view .LVU3920 +6698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11229 .loc 1 6698 11 is_stmt 0 view .LVU3921 + 11230 0104 E06B ldr r0, [r4, #60] + 11231 0106 FFF7FEFF bl HAL_DMA_Abort_IT + 11232 .LVL803: +6698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11233 .loc 1 6698 10 discriminator 1 view .LVU3922 + 11234 010a 50B1 cbz r0, .L690 +6701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11235 .loc 1 6701 9 is_stmt 1 view .LVU3923 +6701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11236 .loc 1 6701 13 is_stmt 0 view .LVU3924 + 11237 010c E06B ldr r0, [r4, #60] +6701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11238 .loc 1 6701 21 view .LVU3925 + 11239 010e 036D ldr r3, [r0, #80] +6701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11240 .loc 1 6701 9 view .LVU3926 + 11241 0110 9847 blx r3 + 11242 .LVL804: + 11243 0112 06E0 b .L690 + 11244 .L701: +6706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11245 .loc 1 6706 7 is_stmt 1 view .LVU3927 + 11246 0114 2046 mov r0, r4 + 11247 0116 FFF7FEFF bl I2C_TreatErrorCallback + 11248 .LVL805: + 11249 011a 02E0 b .L690 + 11250 .LVL806: + 11251 .L699: +6711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11252 .loc 1 6711 5 view .LVU3928 + 11253 011c 2046 mov r0, r4 + 11254 011e FFF7FEFF bl I2C_TreatErrorCallback + 11255 .LVL807: + 11256 .L690: +6713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11257 .loc 1 6713 1 is_stmt 0 view .LVU3929 + 11258 0122 10BD pop {r4, pc} + 11259 .LVL808: + 11260 .L704: +6713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11261 .loc 1 6713 1 view .LVU3930 + 11262 .align 2 + 11263 .L703: + 11264 0124 0000FFFF .word -65536 + 11265 0128 00000000 .word I2C_Slave_ISR_IT + ARM GAS /tmp/ccSHpINd.s page 396 + + + 11266 012c 00000000 .word I2C_DMAAbort + 11267 .cfi_endproc + 11268 .LFE204: + 11270 .section .text.I2C_ITSlaveCplt,"ax",%progbits + 11271 .align 1 + 11272 .syntax unified + 11273 .thumb + 11274 .thumb_func + 11276 I2C_ITSlaveCplt: + 11277 .LVL809: + 11278 .LFB202: +6323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 11279 .loc 1 6323 1 is_stmt 1 view -0 + 11280 .cfi_startproc + 11281 @ args = 0, pretend = 0, frame = 0 + 11282 @ frame_needed = 0, uses_anonymous_args = 0 +6323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 11283 .loc 1 6323 1 is_stmt 0 view .LVU3932 + 11284 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 11285 .LCFI123: + 11286 .cfi_def_cfa_offset 24 + 11287 .cfi_offset 3, -24 + 11288 .cfi_offset 4, -20 + 11289 .cfi_offset 5, -16 + 11290 .cfi_offset 6, -12 + 11291 .cfi_offset 7, -8 + 11292 .cfi_offset 14, -4 + 11293 0002 0446 mov r4, r0 + 11294 0004 0D46 mov r5, r1 +6324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 11295 .loc 1 6324 3 is_stmt 1 view .LVU3933 +6324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 11296 .loc 1 6324 26 is_stmt 0 view .LVU3934 + 11297 0006 0268 ldr r2, [r0] +6324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 11298 .loc 1 6324 12 view .LVU3935 + 11299 0008 1668 ldr r6, [r2] + 11300 .LVL810: +6325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 11301 .loc 1 6325 3 is_stmt 1 view .LVU3936 +6326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; + 11302 .loc 1 6326 3 view .LVU3937 +6326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; + 11303 .loc 1 6326 12 is_stmt 0 view .LVU3938 + 11304 000a C76A ldr r7, [r0, #44] + 11305 .LVL811: +6327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11306 .loc 1 6327 3 is_stmt 1 view .LVU3939 +6327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11307 .loc 1 6327 24 is_stmt 0 view .LVU3940 + 11308 000c 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 11309 .LVL812: +6330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11310 .loc 1 6330 3 is_stmt 1 view .LVU3941 + 11311 0010 2021 movs r1, #32 + 11312 .LVL813: +6330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 397 + + + 11313 .loc 1 6330 3 is_stmt 0 view .LVU3942 + 11314 0012 D161 str r1, [r2, #28] +6333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11315 .loc 1 6333 3 is_stmt 1 view .LVU3943 + 11316 0014 213B subs r3, r3, #33 + 11317 .LVL814: +6333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11318 .loc 1 6333 3 is_stmt 0 view .LVU3944 + 11319 0016 092B cmp r3, #9 + 11320 0018 0CD8 bhi .L706 + 11321 001a DFE803F0 tbb [pc, r3] + 11322 .L708: + 11323 001e 05 .byte (.L709-.L708)/2 + 11324 001f 7A .byte (.L707-.L708)/2 + 11325 0020 0B .byte (.L706-.L708)/2 + 11326 0021 0B .byte (.L706-.L708)/2 + 11327 0022 0B .byte (.L706-.L708)/2 + 11328 0023 0B .byte (.L706-.L708)/2 + 11329 0024 0B .byte (.L706-.L708)/2 + 11330 0025 81 .byte (.L710-.L708)/2 + 11331 0026 05 .byte (.L709-.L708)/2 + 11332 0027 7A .byte (.L707-.L708)/2 + 11333 .p2align 1 + 11334 .L709: +6335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 11335 .loc 1 6335 5 is_stmt 1 view .LVU3945 + 11336 0028 48F20101 movw r1, #32769 + 11337 002c FFF7FEFF bl I2C_Disable_IRQ + 11338 .LVL815: +6336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11339 .loc 1 6336 5 view .LVU3946 +6336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11340 .loc 1 6336 25 is_stmt 0 view .LVU3947 + 11341 0030 2123 movs r3, #33 + 11342 0032 2363 str r3, [r4, #48] + 11343 .L706: +6351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11344 .loc 1 6351 3 is_stmt 1 view .LVU3948 +6354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11345 .loc 1 6354 3 view .LVU3949 +6354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11346 .loc 1 6354 7 is_stmt 0 view .LVU3950 + 11347 0034 2268 ldr r2, [r4] +6354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11348 .loc 1 6354 17 view .LVU3951 + 11349 0036 5368 ldr r3, [r2, #4] +6354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11350 .loc 1 6354 23 view .LVU3952 + 11351 0038 43F40043 orr r3, r3, #32768 + 11352 003c 5360 str r3, [r2, #4] +6357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11353 .loc 1 6357 3 is_stmt 1 view .LVU3953 + 11354 003e 2268 ldr r2, [r4] + 11355 0040 5368 ldr r3, [r2, #4] + 11356 0042 23F0FF73 bic r3, r3, #33423360 + 11357 0046 23F48B33 bic r3, r3, #71168 + 11358 004a 23F4FF73 bic r3, r3, #510 + ARM GAS /tmp/ccSHpINd.s page 398 + + + 11359 004e 23F00103 bic r3, r3, #1 + 11360 0052 5360 str r3, [r2, #4] +6360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11361 .loc 1 6360 3 view .LVU3954 + 11362 0054 2046 mov r0, r4 + 11363 0056 FFF7FEFF bl I2C_Flush_TXDR + 11364 .LVL816: +6363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11365 .loc 1 6363 3 view .LVU3955 +6363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11366 .loc 1 6363 6 is_stmt 0 view .LVU3956 + 11367 005a 16F4804F tst r6, #16384 + 11368 005e 66D0 beq .L711 +6366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11369 .loc 1 6366 5 is_stmt 1 view .LVU3957 +6366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11370 .loc 1 6366 9 is_stmt 0 view .LVU3958 + 11371 0060 2268 ldr r2, [r4] +6366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11372 .loc 1 6366 19 view .LVU3959 + 11373 0062 1368 ldr r3, [r2] +6366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11374 .loc 1 6366 25 view .LVU3960 + 11375 0064 23F48043 bic r3, r3, #16384 + 11376 0068 1360 str r3, [r2] +6368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11377 .loc 1 6368 5 is_stmt 1 view .LVU3961 +6368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11378 .loc 1 6368 13 is_stmt 0 view .LVU3962 + 11379 006a A36B ldr r3, [r4, #56] +6368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11380 .loc 1 6368 8 view .LVU3963 + 11381 006c 1BB1 cbz r3, .L712 +6370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11382 .loc 1 6370 7 is_stmt 1 view .LVU3964 +6370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11383 .loc 1 6370 35 is_stmt 0 view .LVU3965 + 11384 006e 1B68 ldr r3, [r3] + 11385 0070 5B68 ldr r3, [r3, #4] +6370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11386 .loc 1 6370 25 view .LVU3966 + 11387 0072 9BB2 uxth r3, r3 +6370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11388 .loc 1 6370 23 view .LVU3967 + 11389 0074 6385 strh r3, [r4, #42] @ movhi + 11390 .L712: +6386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11391 .loc 1 6386 3 is_stmt 1 view .LVU3968 +6389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11392 .loc 1 6389 3 view .LVU3969 +6389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11393 .loc 1 6389 6 is_stmt 0 view .LVU3970 + 11394 0076 15F0040F tst r5, #4 + 11395 007a 11D0 beq .L713 +6392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11396 .loc 1 6392 5 is_stmt 1 view .LVU3971 +6392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 399 + + + 11397 .loc 1 6392 16 is_stmt 0 view .LVU3972 + 11398 007c 25F00405 bic r5, r5, #4 + 11399 .LVL817: +6395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11400 .loc 1 6395 5 is_stmt 1 view .LVU3973 +6395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11401 .loc 1 6395 36 is_stmt 0 view .LVU3974 + 11402 0080 2368 ldr r3, [r4] +6395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11403 .loc 1 6395 46 view .LVU3975 + 11404 0082 5A6A ldr r2, [r3, #36] +6395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11405 .loc 1 6395 10 view .LVU3976 + 11406 0084 636A ldr r3, [r4, #36] +6395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11407 .loc 1 6395 21 view .LVU3977 + 11408 0086 1A70 strb r2, [r3] +6398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11409 .loc 1 6398 5 is_stmt 1 view .LVU3978 +6398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11410 .loc 1 6398 9 is_stmt 0 view .LVU3979 + 11411 0088 636A ldr r3, [r4, #36] +6398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11412 .loc 1 6398 19 view .LVU3980 + 11413 008a 0133 adds r3, r3, #1 + 11414 008c 6362 str r3, [r4, #36] +6400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11415 .loc 1 6400 5 is_stmt 1 view .LVU3981 +6400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11416 .loc 1 6400 14 is_stmt 0 view .LVU3982 + 11417 008e 238D ldrh r3, [r4, #40] +6400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11418 .loc 1 6400 8 view .LVU3983 + 11419 0090 33B1 cbz r3, .L713 +6402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 11420 .loc 1 6402 7 is_stmt 1 view .LVU3984 +6402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 11421 .loc 1 6402 21 is_stmt 0 view .LVU3985 + 11422 0092 013B subs r3, r3, #1 + 11423 0094 2385 strh r3, [r4, #40] @ movhi +6403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11424 .loc 1 6403 7 is_stmt 1 view .LVU3986 +6403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11425 .loc 1 6403 11 is_stmt 0 view .LVU3987 + 11426 0096 638D ldrh r3, [r4, #42] + 11427 0098 9BB2 uxth r3, r3 +6403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11428 .loc 1 6403 22 view .LVU3988 + 11429 009a 013B subs r3, r3, #1 + 11430 009c 9BB2 uxth r3, r3 + 11431 009e 6385 strh r3, [r4, #42] @ movhi + 11432 .L713: +6408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11433 .loc 1 6408 3 is_stmt 1 view .LVU3989 +6408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11434 .loc 1 6408 11 is_stmt 0 view .LVU3990 + 11435 00a0 638D ldrh r3, [r4, #42] + ARM GAS /tmp/ccSHpINd.s page 400 + + + 11436 00a2 9BB2 uxth r3, r3 +6408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11437 .loc 1 6408 6 view .LVU3991 + 11438 00a4 1BB1 cbz r3, .L714 +6411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11439 .loc 1 6411 5 is_stmt 1 view .LVU3992 +6411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11440 .loc 1 6411 9 is_stmt 0 view .LVU3993 + 11441 00a6 636C ldr r3, [r4, #68] +6411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11442 .loc 1 6411 21 view .LVU3994 + 11443 00a8 43F00403 orr r3, r3, #4 + 11444 00ac 6364 str r3, [r4, #68] + 11445 .L714: +6414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + 11446 .loc 1 6414 3 is_stmt 1 view .LVU3995 +6414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + 11447 .loc 1 6414 6 is_stmt 0 view .LVU3996 + 11448 00ae 15F0100F tst r5, #16 + 11449 00b2 13D0 beq .L715 +6414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + 11450 .loc 1 6414 58 discriminator 1 view .LVU3997 + 11451 00b4 16F0100F tst r6, #16 + 11452 00b8 10D0 beq .L715 +6421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11453 .loc 1 6421 5 is_stmt 1 view .LVU3998 +6421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11454 .loc 1 6421 13 is_stmt 0 view .LVU3999 + 11455 00ba 638D ldrh r3, [r4, #42] + 11456 00bc 9BB2 uxth r3, r3 +6421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11457 .loc 1 6421 8 view .LVU4000 + 11458 00be 002B cmp r3, #0 + 11459 00c0 5AD1 bne .L716 +6423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 11460 .loc 1 6423 7 is_stmt 1 view .LVU4001 +6423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 11461 .loc 1 6423 16 is_stmt 0 view .LVU4002 + 11462 00c2 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11463 00c6 DBB2 uxtb r3, r3 +6423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 11464 .loc 1 6423 10 view .LVU4003 + 11465 00c8 282B cmp r3, #40 + 11466 00ca 40D0 beq .L725 + 11467 .L717: +6430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11468 .loc 1 6430 12 is_stmt 1 view .LVU4004 +6430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11469 .loc 1 6430 21 is_stmt 0 view .LVU4005 + 11470 00cc 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11471 00d0 DBB2 uxtb r3, r3 +6430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11472 .loc 1 6430 15 view .LVU4006 + 11473 00d2 292B cmp r3, #41 + 11474 00d4 43D0 beq .L726 + 11475 .L718: +6445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + ARM GAS /tmp/ccSHpINd.s page 401 + + + 11476 .loc 1 6445 9 is_stmt 1 view .LVU4007 + 11477 00d6 2368 ldr r3, [r4] + 11478 00d8 1022 movs r2, #16 + 11479 00da DA61 str r2, [r3, #28] + 11480 .L715: +6465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 11481 .loc 1 6465 3 view .LVU4008 +6465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferISR = NULL; + 11482 .loc 1 6465 14 is_stmt 0 view .LVU4009 + 11483 00dc 0023 movs r3, #0 + 11484 00de 84F84230 strb r3, [r4, #66] +6466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11485 .loc 1 6466 3 is_stmt 1 view .LVU4010 +6466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11486 .loc 1 6466 17 is_stmt 0 view .LVU4011 + 11487 00e2 6363 str r3, [r4, #52] +6468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11488 .loc 1 6468 3 is_stmt 1 view .LVU4012 +6468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11489 .loc 1 6468 11 is_stmt 0 view .LVU4013 + 11490 00e4 636C ldr r3, [r4, #68] +6468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11491 .loc 1 6468 6 view .LVU4014 + 11492 00e6 002B cmp r3, #0 + 11493 00e8 57D1 bne .L727 +6480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11494 .loc 1 6480 8 is_stmt 1 view .LVU4015 +6480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11495 .loc 1 6480 16 is_stmt 0 view .LVU4016 + 11496 00ea E36A ldr r3, [r4, #44] +6480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11497 .loc 1 6480 11 view .LVU4017 + 11498 00ec 13F5803F cmn r3, #65536 + 11499 00f0 61D1 bne .L728 +6500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11500 .loc 1 6500 8 is_stmt 1 view .LVU4018 +6500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11501 .loc 1 6500 16 is_stmt 0 view .LVU4019 + 11502 00f2 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11503 00f6 DBB2 uxtb r3, r3 +6500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11504 .loc 1 6500 11 view .LVU4020 + 11505 00f8 222B cmp r3, #34 + 11506 00fa 6CD0 beq .L729 +6517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11507 .loc 1 6517 5 is_stmt 1 view .LVU4021 +6517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11508 .loc 1 6517 17 is_stmt 0 view .LVU4022 + 11509 00fc 2023 movs r3, #32 + 11510 00fe 84F84130 strb r3, [r4, #65] +6518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11511 .loc 1 6518 5 is_stmt 1 view .LVU4023 +6518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11512 .loc 1 6518 25 is_stmt 0 view .LVU4024 + 11513 0102 0023 movs r3, #0 + 11514 0104 2363 str r3, [r4, #48] +6521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 402 + + + 11515 .loc 1 6521 5 is_stmt 1 view .LVU4025 +6521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11516 .loc 1 6521 5 view .LVU4026 + 11517 0106 84F84030 strb r3, [r4, #64] +6521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11518 .loc 1 6521 5 view .LVU4027 +6527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11519 .loc 1 6527 5 view .LVU4028 + 11520 010a 2046 mov r0, r4 + 11521 010c FFF7FEFF bl HAL_I2C_SlaveTxCpltCallback + 11522 .LVL818: +6530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11523 .loc 1 6530 1 is_stmt 0 view .LVU4029 + 11524 0110 60E0 b .L705 + 11525 .LVL819: + 11526 .L707: +6340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 11527 .loc 1 6340 5 is_stmt 1 view .LVU4030 + 11528 0112 48F20201 movw r1, #32770 + 11529 0116 FFF7FEFF bl I2C_Disable_IRQ + 11530 .LVL820: +6341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11531 .loc 1 6341 5 view .LVU4031 +6341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11532 .loc 1 6341 25 is_stmt 0 view .LVU4032 + 11533 011a 2223 movs r3, #34 + 11534 011c 2363 str r3, [r4, #48] + 11535 011e 89E7 b .L706 + 11536 .LVL821: + 11537 .L710: +6345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11538 .loc 1 6345 5 is_stmt 1 view .LVU4033 + 11539 0120 48F20301 movw r1, #32771 + 11540 0124 FFF7FEFF bl I2C_Disable_IRQ + 11541 .LVL822: +6346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11542 .loc 1 6346 5 view .LVU4034 +6346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11543 .loc 1 6346 25 is_stmt 0 view .LVU4035 + 11544 0128 0023 movs r3, #0 + 11545 012a 2363 str r3, [r4, #48] + 11546 012c 82E7 b .L706 + 11547 .L711: +6373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11548 .loc 1 6373 8 is_stmt 1 view .LVU4036 +6373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11549 .loc 1 6373 11 is_stmt 0 view .LVU4037 + 11550 012e 16F4004F tst r6, #32768 + 11551 0132 A0D0 beq .L712 +6376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11552 .loc 1 6376 5 is_stmt 1 view .LVU4038 +6376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11553 .loc 1 6376 9 is_stmt 0 view .LVU4039 + 11554 0134 2268 ldr r2, [r4] +6376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11555 .loc 1 6376 19 view .LVU4040 + 11556 0136 1368 ldr r3, [r2] + ARM GAS /tmp/ccSHpINd.s page 403 + + +6376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11557 .loc 1 6376 25 view .LVU4041 + 11558 0138 23F40043 bic r3, r3, #32768 + 11559 013c 1360 str r3, [r2] +6378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11560 .loc 1 6378 5 is_stmt 1 view .LVU4042 +6378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11561 .loc 1 6378 13 is_stmt 0 view .LVU4043 + 11562 013e E36B ldr r3, [r4, #60] +6378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11563 .loc 1 6378 8 view .LVU4044 + 11564 0140 002B cmp r3, #0 + 11565 0142 98D0 beq .L712 +6380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11566 .loc 1 6380 7 is_stmt 1 view .LVU4045 +6380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11567 .loc 1 6380 35 is_stmt 0 view .LVU4046 + 11568 0144 1B68 ldr r3, [r3] + 11569 0146 5B68 ldr r3, [r3, #4] +6380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11570 .loc 1 6380 25 view .LVU4047 + 11571 0148 9BB2 uxth r3, r3 +6380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11572 .loc 1 6380 23 view .LVU4048 + 11573 014a 6385 strh r3, [r4, #42] @ movhi + 11574 014c 93E7 b .L712 + 11575 .LVL823: + 11576 .L725: +6423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 11577 .loc 1 6423 49 discriminator 1 view .LVU4049 + 11578 014e B7F1007F cmp r7, #33554432 + 11579 0152 BBD1 bne .L717 +6428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11580 .loc 1 6428 9 is_stmt 1 view .LVU4050 + 11581 0154 2946 mov r1, r5 + 11582 0156 2046 mov r0, r4 + 11583 0158 FFF7FEFF bl I2C_ITListenCplt + 11584 .LVL824: + 11585 015c BEE7 b .L715 + 11586 .L726: +6430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11587 .loc 1 6430 62 is_stmt 0 discriminator 1 view .LVU4051 + 11588 015e 17F5803F cmn r7, #65536 + 11589 0162 B8D0 beq .L718 +6433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11590 .loc 1 6433 9 is_stmt 1 view .LVU4052 + 11591 0164 2368 ldr r3, [r4] + 11592 0166 1022 movs r2, #16 + 11593 0168 DA61 str r2, [r3, #28] +6436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11594 .loc 1 6436 9 view .LVU4053 + 11595 016a 2046 mov r0, r4 + 11596 016c FFF7FEFF bl I2C_Flush_TXDR + 11597 .LVL825: +6440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11598 .loc 1 6440 9 view .LVU4054 + 11599 0170 2046 mov r0, r4 + ARM GAS /tmp/ccSHpINd.s page 404 + + + 11600 0172 FFF7FEFF bl I2C_ITSlaveSeqCplt + 11601 .LVL826: + 11602 0176 B1E7 b .L715 + 11603 .L716: +6452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11604 .loc 1 6452 7 view .LVU4055 + 11605 0178 2368 ldr r3, [r4] + 11606 017a 1022 movs r2, #16 + 11607 017c DA61 str r2, [r3, #28] +6455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11608 .loc 1 6455 7 view .LVU4056 +6455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11609 .loc 1 6455 11 is_stmt 0 view .LVU4057 + 11610 017e 636C ldr r3, [r4, #68] +6455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11611 .loc 1 6455 23 view .LVU4058 + 11612 0180 43F00403 orr r3, r3, #4 + 11613 0184 6364 str r3, [r4, #68] +6457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11614 .loc 1 6457 7 is_stmt 1 view .LVU4059 +6457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11615 .loc 1 6457 10 is_stmt 0 view .LVU4060 + 11616 0186 B7F1807F cmp r7, #16777216 + 11617 018a 18BF it ne + 11618 018c 002F cmpne r7, #0 + 11619 018e A5D1 bne .L715 +6460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11620 .loc 1 6460 9 is_stmt 1 view .LVU4061 +6460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11621 .loc 1 6460 31 is_stmt 0 view .LVU4062 + 11622 0190 616C ldr r1, [r4, #68] +6460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11623 .loc 1 6460 9 view .LVU4063 + 11624 0192 2046 mov r0, r4 + 11625 0194 FFF7FEFF bl I2C_ITError + 11626 .LVL827: + 11627 0198 A0E7 b .L715 + 11628 .L727: +6471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11629 .loc 1 6471 5 is_stmt 1 view .LVU4064 +6471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11630 .loc 1 6471 27 is_stmt 0 view .LVU4065 + 11631 019a 616C ldr r1, [r4, #68] +6471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11632 .loc 1 6471 5 view .LVU4066 + 11633 019c 2046 mov r0, r4 + 11634 019e FFF7FEFF bl I2C_ITError + 11635 .LVL828: +6474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11636 .loc 1 6474 5 is_stmt 1 view .LVU4067 +6474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11637 .loc 1 6474 13 is_stmt 0 view .LVU4068 + 11638 01a2 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11639 01a6 DBB2 uxtb r3, r3 +6474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11640 .loc 1 6474 8 view .LVU4069 + 11641 01a8 282B cmp r3, #40 + ARM GAS /tmp/ccSHpINd.s page 405 + + + 11642 01aa 13D1 bne .L705 +6477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11643 .loc 1 6477 7 is_stmt 1 view .LVU4070 + 11644 01ac 2946 mov r1, r5 + 11645 01ae 2046 mov r0, r4 + 11646 01b0 FFF7FEFF bl I2C_ITListenCplt + 11647 .LVL829: + 11648 01b4 0EE0 b .L705 + 11649 .L728: +6483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11650 .loc 1 6483 5 view .LVU4071 + 11651 01b6 2046 mov r0, r4 + 11652 01b8 FFF7FEFF bl I2C_ITSlaveSeqCplt + 11653 .LVL830: +6485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 11654 .loc 1 6485 5 view .LVU4072 +6485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 11655 .loc 1 6485 23 is_stmt 0 view .LVU4073 + 11656 01bc 0B4B ldr r3, .L730 + 11657 01be E362 str r3, [r4, #44] +6486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11658 .loc 1 6486 5 is_stmt 1 view .LVU4074 +6486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11659 .loc 1 6486 17 is_stmt 0 view .LVU4075 + 11660 01c0 2023 movs r3, #32 + 11661 01c2 84F84130 strb r3, [r4, #65] +6487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11662 .loc 1 6487 5 is_stmt 1 view .LVU4076 +6487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11663 .loc 1 6487 25 is_stmt 0 view .LVU4077 + 11664 01c6 0023 movs r3, #0 + 11665 01c8 2363 str r3, [r4, #48] +6490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11666 .loc 1 6490 5 is_stmt 1 view .LVU4078 +6490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11667 .loc 1 6490 5 view .LVU4079 + 11668 01ca 84F84030 strb r3, [r4, #64] +6490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11669 .loc 1 6490 5 view .LVU4080 +6496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11670 .loc 1 6496 5 view .LVU4081 + 11671 01ce 2046 mov r0, r4 + 11672 01d0 FFF7FEFF bl HAL_I2C_ListenCpltCallback + 11673 .LVL831: + 11674 .L705: +6530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11675 .loc 1 6530 1 is_stmt 0 view .LVU4082 + 11676 01d4 F8BD pop {r3, r4, r5, r6, r7, pc} + 11677 .LVL832: + 11678 .L729: +6502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11679 .loc 1 6502 5 is_stmt 1 view .LVU4083 +6502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11680 .loc 1 6502 17 is_stmt 0 view .LVU4084 + 11681 01d6 2023 movs r3, #32 + 11682 01d8 84F84130 strb r3, [r4, #65] +6503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 406 + + + 11683 .loc 1 6503 5 is_stmt 1 view .LVU4085 +6503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11684 .loc 1 6503 25 is_stmt 0 view .LVU4086 + 11685 01dc 0023 movs r3, #0 + 11686 01de 2363 str r3, [r4, #48] +6506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11687 .loc 1 6506 5 is_stmt 1 view .LVU4087 +6506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11688 .loc 1 6506 5 view .LVU4088 + 11689 01e0 84F84030 strb r3, [r4, #64] +6506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11690 .loc 1 6506 5 view .LVU4089 +6512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11691 .loc 1 6512 5 view .LVU4090 + 11692 01e4 2046 mov r0, r4 + 11693 01e6 FFF7FEFF bl HAL_I2C_SlaveRxCpltCallback + 11694 .LVL833: + 11695 01ea F3E7 b .L705 + 11696 .L731: + 11697 .align 2 + 11698 .L730: + 11699 01ec 0000FFFF .word -65536 + 11700 .cfi_endproc + 11701 .LFE202: + 11703 .section .text.I2C_Slave_ISR_IT,"ax",%progbits + 11704 .align 1 + 11705 .syntax unified + 11706 .thumb + 11707 .thumb_func + 11709 I2C_Slave_ISR_IT: + 11710 .LVL834: + 11711 .LFB192: +5259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 11712 .loc 1 5259 1 view -0 + 11713 .cfi_startproc + 11714 @ args = 0, pretend = 0, frame = 0 + 11715 @ frame_needed = 0, uses_anonymous_args = 0 +5259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 11716 .loc 1 5259 1 is_stmt 0 view .LVU4092 + 11717 0000 10B5 push {r4, lr} + 11718 .LCFI124: + 11719 .cfi_def_cfa_offset 8 + 11720 .cfi_offset 4, -8 + 11721 .cfi_offset 14, -4 + 11722 0002 0446 mov r4, r0 +5260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 11723 .loc 1 5260 3 is_stmt 1 view .LVU4093 +5260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 11724 .loc 1 5260 12 is_stmt 0 view .LVU4094 + 11725 0004 C06A ldr r0, [r0, #44] + 11726 .LVL835: +5261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11727 .loc 1 5261 3 is_stmt 1 view .LVU4095 +5264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11728 .loc 1 5264 3 view .LVU4096 +5264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11729 .loc 1 5264 3 view .LVU4097 + ARM GAS /tmp/ccSHpINd.s page 407 + + + 11730 0006 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 11731 000a 012B cmp r3, #1 + 11732 000c 00F09B80 beq .L744 +5264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11733 .loc 1 5264 3 discriminator 2 view .LVU4098 + 11734 0010 0123 movs r3, #1 + 11735 0012 84F84030 strb r3, [r4, #64] +5264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11736 .loc 1 5264 3 discriminator 2 view .LVU4099 +5267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 11737 .loc 1 5267 3 view .LVU4100 +5267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 11738 .loc 1 5267 6 is_stmt 0 view .LVU4101 + 11739 0016 11F0200F tst r1, #32 + 11740 001a 02D0 beq .L734 +5267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 11741 .loc 1 5267 61 discriminator 1 view .LVU4102 + 11742 001c 12F0200F tst r2, #32 + 11743 0020 16D1 bne .L746 + 11744 .L734: +5273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 11745 .loc 1 5273 8 is_stmt 1 view .LVU4103 +5273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 11746 .loc 1 5273 11 is_stmt 0 view .LVU4104 + 11747 0022 11F0100F tst r1, #16 + 11748 0026 3FD0 beq .L736 +5273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 11749 .loc 1 5273 63 discriminator 1 view .LVU4105 + 11750 0028 12F0100F tst r2, #16 + 11751 002c 3CD0 beq .L736 +5280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11752 .loc 1 5280 5 is_stmt 1 view .LVU4106 +5280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11753 .loc 1 5280 13 is_stmt 0 view .LVU4107 + 11754 002e 638D ldrh r3, [r4, #42] + 11755 0030 9BB2 uxth r3, r3 +5280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11756 .loc 1 5280 8 view .LVU4108 + 11757 0032 43BB cbnz r3, .L737 +5282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 11758 .loc 1 5282 7 is_stmt 1 view .LVU4109 +5282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 11759 .loc 1 5282 16 is_stmt 0 view .LVU4110 + 11760 0034 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11761 0038 DBB2 uxtb r3, r3 +5282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 11762 .loc 1 5282 10 view .LVU4111 + 11763 003a 282B cmp r3, #40 + 11764 003c 0FD0 beq .L747 + 11765 .L738: +5289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11766 .loc 1 5289 12 is_stmt 1 view .LVU4112 +5289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11767 .loc 1 5289 21 is_stmt 0 view .LVU4113 + 11768 003e 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11769 0042 DBB2 uxtb r3, r3 +5289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 408 + + + 11770 .loc 1 5289 15 view .LVU4114 + 11771 0044 292B cmp r3, #41 + 11772 0046 11D0 beq .L748 + 11773 .L739: +5304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11774 .loc 1 5304 9 is_stmt 1 view .LVU4115 + 11775 0048 2368 ldr r3, [r4] + 11776 004a 1022 movs r2, #16 + 11777 .LVL836: +5304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11778 .loc 1 5304 9 is_stmt 0 view .LVU4116 + 11779 004c DA61 str r2, [r3, #28] + 11780 004e 02E0 b .L735 + 11781 .LVL837: + 11782 .L746: +5271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11783 .loc 1 5271 5 is_stmt 1 view .LVU4117 + 11784 0050 2046 mov r0, r4 + 11785 .LVL838: +5271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11786 .loc 1 5271 5 is_stmt 0 view .LVU4118 + 11787 0052 FFF7FEFF bl I2C_ITSlaveCplt + 11788 .LVL839: + 11789 .L735: +5381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11790 .loc 1 5381 3 is_stmt 1 view .LVU4119 +5384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11791 .loc 1 5384 3 view .LVU4120 +5384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11792 .loc 1 5384 3 view .LVU4121 + 11793 0056 0020 movs r0, #0 + 11794 0058 84F84000 strb r0, [r4, #64] +5384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11795 .loc 1 5384 3 view .LVU4122 +5386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11796 .loc 1 5386 3 view .LVU4123 + 11797 .L733: +5387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11798 .loc 1 5387 1 is_stmt 0 view .LVU4124 + 11799 005c 10BD pop {r4, pc} + 11800 .LVL840: + 11801 .L747: +5282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 11802 .loc 1 5282 49 discriminator 1 view .LVU4125 + 11803 005e B0F1007F cmp r0, #33554432 + 11804 0062 ECD1 bne .L738 +5287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11805 .loc 1 5287 9 is_stmt 1 view .LVU4126 + 11806 0064 2046 mov r0, r4 + 11807 .LVL841: +5287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11808 .loc 1 5287 9 is_stmt 0 view .LVU4127 + 11809 0066 FFF7FEFF bl I2C_ITListenCplt + 11810 .LVL842: +5287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11811 .loc 1 5287 9 view .LVU4128 + 11812 006a F4E7 b .L735 + ARM GAS /tmp/ccSHpINd.s page 409 + + + 11813 .LVL843: + 11814 .L748: +5289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11815 .loc 1 5289 62 discriminator 1 view .LVU4129 + 11816 006c 10F5803F cmn r0, #65536 + 11817 0070 EAD0 beq .L739 +5292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11818 .loc 1 5292 9 is_stmt 1 view .LVU4130 + 11819 0072 2368 ldr r3, [r4] + 11820 0074 1022 movs r2, #16 + 11821 .LVL844: +5292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11822 .loc 1 5292 9 is_stmt 0 view .LVU4131 + 11823 0076 DA61 str r2, [r3, #28] +5295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11824 .loc 1 5295 9 is_stmt 1 view .LVU4132 + 11825 0078 2046 mov r0, r4 + 11826 .LVL845: +5295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11827 .loc 1 5295 9 is_stmt 0 view .LVU4133 + 11828 007a FFF7FEFF bl I2C_Flush_TXDR + 11829 .LVL846: +5299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11830 .loc 1 5299 9 is_stmt 1 view .LVU4134 + 11831 007e 2046 mov r0, r4 + 11832 0080 FFF7FEFF bl I2C_ITSlaveSeqCplt + 11833 .LVL847: + 11834 0084 E7E7 b .L735 + 11835 .LVL848: + 11836 .L737: +5311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11837 .loc 1 5311 7 view .LVU4135 + 11838 0086 2368 ldr r3, [r4] + 11839 0088 1022 movs r2, #16 + 11840 .LVL849: +5311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11841 .loc 1 5311 7 is_stmt 0 view .LVU4136 + 11842 008a DA61 str r2, [r3, #28] +5314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11843 .loc 1 5314 7 is_stmt 1 view .LVU4137 +5314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11844 .loc 1 5314 11 is_stmt 0 view .LVU4138 + 11845 008c 636C ldr r3, [r4, #68] +5314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11846 .loc 1 5314 23 view .LVU4139 + 11847 008e 43F00403 orr r3, r3, #4 + 11848 0092 6364 str r3, [r4, #68] +5316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11849 .loc 1 5316 7 is_stmt 1 view .LVU4140 +5316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11850 .loc 1 5316 10 is_stmt 0 view .LVU4141 + 11851 0094 B0F1807F cmp r0, #16777216 + 11852 0098 18BF it ne + 11853 009a 0028 cmpne r0, #0 + 11854 009c DBD1 bne .L735 +5319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11855 .loc 1 5319 9 is_stmt 1 view .LVU4142 + ARM GAS /tmp/ccSHpINd.s page 410 + + +5319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11856 .loc 1 5319 31 is_stmt 0 view .LVU4143 + 11857 009e 616C ldr r1, [r4, #68] + 11858 .LVL850: +5319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11859 .loc 1 5319 9 view .LVU4144 + 11860 00a0 2046 mov r0, r4 + 11861 .LVL851: +5319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11862 .loc 1 5319 9 view .LVU4145 + 11863 00a2 FFF7FEFF bl I2C_ITError + 11864 .LVL852: + 11865 00a6 D6E7 b .L735 + 11866 .LVL853: + 11867 .L736: +5323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 11868 .loc 1 5323 8 is_stmt 1 view .LVU4146 +5323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 11869 .loc 1 5323 11 is_stmt 0 view .LVU4147 + 11870 00a8 11F0040F tst r1, #4 + 11871 00ac 1FD0 beq .L740 +5323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 11872 .loc 1 5323 65 discriminator 1 view .LVU4148 + 11873 00ae 12F0040F tst r2, #4 + 11874 00b2 1CD0 beq .L740 +5326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11875 .loc 1 5326 5 is_stmt 1 view .LVU4149 +5326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11876 .loc 1 5326 13 is_stmt 0 view .LVU4150 + 11877 00b4 638D ldrh r3, [r4, #42] + 11878 00b6 9BB2 uxth r3, r3 +5326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11879 .loc 1 5326 8 view .LVU4151 + 11880 00b8 73B1 cbz r3, .L741 +5329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11881 .loc 1 5329 7 is_stmt 1 view .LVU4152 +5329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11882 .loc 1 5329 38 is_stmt 0 view .LVU4153 + 11883 00ba 2368 ldr r3, [r4] +5329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11884 .loc 1 5329 48 view .LVU4154 + 11885 00bc 5A6A ldr r2, [r3, #36] + 11886 .LVL854: +5329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11887 .loc 1 5329 12 view .LVU4155 + 11888 00be 636A ldr r3, [r4, #36] +5329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11889 .loc 1 5329 23 view .LVU4156 + 11890 00c0 1A70 strb r2, [r3] +5332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11891 .loc 1 5332 7 is_stmt 1 view .LVU4157 +5332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11892 .loc 1 5332 11 is_stmt 0 view .LVU4158 + 11893 00c2 636A ldr r3, [r4, #36] +5332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11894 .loc 1 5332 21 view .LVU4159 + 11895 00c4 0133 adds r3, r3, #1 + ARM GAS /tmp/ccSHpINd.s page 411 + + + 11896 00c6 6362 str r3, [r4, #36] +5334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 11897 .loc 1 5334 7 is_stmt 1 view .LVU4160 +5334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 11898 .loc 1 5334 11 is_stmt 0 view .LVU4161 + 11899 00c8 238D ldrh r3, [r4, #40] +5334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 11900 .loc 1 5334 21 view .LVU4162 + 11901 00ca 013B subs r3, r3, #1 + 11902 00cc 2385 strh r3, [r4, #40] @ movhi +5335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11903 .loc 1 5335 7 is_stmt 1 view .LVU4163 +5335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11904 .loc 1 5335 11 is_stmt 0 view .LVU4164 + 11905 00ce 638D ldrh r3, [r4, #42] + 11906 00d0 9BB2 uxth r3, r3 +5335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11907 .loc 1 5335 22 view .LVU4165 + 11908 00d2 013B subs r3, r3, #1 + 11909 00d4 9BB2 uxth r3, r3 + 11910 00d6 6385 strh r3, [r4, #42] @ movhi + 11911 .L741: +5338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 11912 .loc 1 5338 5 is_stmt 1 view .LVU4166 +5338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 11913 .loc 1 5338 14 is_stmt 0 view .LVU4167 + 11914 00d8 638D ldrh r3, [r4, #42] + 11915 00da 9BB2 uxth r3, r3 +5338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 11916 .loc 1 5338 8 view .LVU4168 + 11917 00dc 002B cmp r3, #0 + 11918 00de BAD1 bne .L735 +5338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 11919 .loc 1 5338 33 discriminator 1 view .LVU4169 + 11920 00e0 10F5803F cmn r0, #65536 + 11921 00e4 B7D0 beq .L735 +5342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11922 .loc 1 5342 7 is_stmt 1 view .LVU4170 + 11923 00e6 2046 mov r0, r4 + 11924 .LVL855: +5342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11925 .loc 1 5342 7 is_stmt 0 view .LVU4171 + 11926 00e8 FFF7FEFF bl I2C_ITSlaveSeqCplt + 11927 .LVL856: +5342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11928 .loc 1 5342 7 view .LVU4172 + 11929 00ec B3E7 b .L735 + 11930 .LVL857: + 11931 .L740: +5345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 11932 .loc 1 5345 8 is_stmt 1 view .LVU4173 +5345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 11933 .loc 1 5345 11 is_stmt 0 view .LVU4174 + 11934 00ee 11F0080F tst r1, #8 + 11935 00f2 02D0 beq .L742 +5345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 11936 .loc 1 5345 65 discriminator 1 view .LVU4175 + ARM GAS /tmp/ccSHpINd.s page 412 + + + 11937 00f4 12F0080F tst r2, #8 + 11938 00f8 18D1 bne .L749 + 11939 .L742: +5350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 11940 .loc 1 5350 8 is_stmt 1 view .LVU4176 +5350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 11941 .loc 1 5350 11 is_stmt 0 view .LVU4177 + 11942 00fa 11F0020F tst r1, #2 + 11943 00fe AAD0 beq .L735 +5350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 11944 .loc 1 5350 65 discriminator 1 view .LVU4178 + 11945 0100 12F0020F tst r2, #2 + 11946 0104 A7D0 beq .L735 +5357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11947 .loc 1 5357 5 is_stmt 1 view .LVU4179 +5357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11948 .loc 1 5357 13 is_stmt 0 view .LVU4180 + 11949 0106 638D ldrh r3, [r4, #42] + 11950 0108 9BB2 uxth r3, r3 +5357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11951 .loc 1 5357 8 view .LVU4181 + 11952 010a 9BB1 cbz r3, .L743 +5360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11953 .loc 1 5360 7 is_stmt 1 view .LVU4182 +5360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11954 .loc 1 5360 35 is_stmt 0 view .LVU4183 + 11955 010c 626A ldr r2, [r4, #36] + 11956 .LVL858: +5360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11957 .loc 1 5360 11 view .LVU4184 + 11958 010e 2368 ldr r3, [r4] +5360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11959 .loc 1 5360 30 view .LVU4185 + 11960 0110 1278 ldrb r2, [r2] @ zero_extendqisi2 +5360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11961 .loc 1 5360 28 view .LVU4186 + 11962 0112 9A62 str r2, [r3, #40] +5363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11963 .loc 1 5363 7 is_stmt 1 view .LVU4187 +5363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11964 .loc 1 5363 11 is_stmt 0 view .LVU4188 + 11965 0114 636A ldr r3, [r4, #36] +5363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 11966 .loc 1 5363 21 view .LVU4189 + 11967 0116 0133 adds r3, r3, #1 + 11968 0118 6362 str r3, [r4, #36] +5365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 11969 .loc 1 5365 7 is_stmt 1 view .LVU4190 +5365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 11970 .loc 1 5365 11 is_stmt 0 view .LVU4191 + 11971 011a 638D ldrh r3, [r4, #42] + 11972 011c 9BB2 uxth r3, r3 +5365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize--; + 11973 .loc 1 5365 22 view .LVU4192 + 11974 011e 013B subs r3, r3, #1 + 11975 0120 9BB2 uxth r3, r3 + 11976 0122 6385 strh r3, [r4, #42] @ movhi + ARM GAS /tmp/ccSHpINd.s page 413 + + +5366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11977 .loc 1 5366 7 is_stmt 1 view .LVU4193 +5366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11978 .loc 1 5366 11 is_stmt 0 view .LVU4194 + 11979 0124 238D ldrh r3, [r4, #40] +5366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11980 .loc 1 5366 21 view .LVU4195 + 11981 0126 013B subs r3, r3, #1 + 11982 0128 2385 strh r3, [r4, #40] @ movhi + 11983 012a 94E7 b .L735 + 11984 .LVL859: + 11985 .L749: +5348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11986 .loc 1 5348 5 is_stmt 1 view .LVU4196 + 11987 012c 2046 mov r0, r4 + 11988 .LVL860: +5348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11989 .loc 1 5348 5 is_stmt 0 view .LVU4197 + 11990 012e FFF7FEFF bl I2C_ITAddrCplt + 11991 .LVL861: +5348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 11992 .loc 1 5348 5 view .LVU4198 + 11993 0132 90E7 b .L735 + 11994 .LVL862: + 11995 .L743: +5370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11996 .loc 1 5370 7 is_stmt 1 view .LVU4199 +5370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 11997 .loc 1 5370 10 is_stmt 0 view .LVU4200 + 11998 0134 0028 cmp r0, #0 + 11999 0136 18BF it ne + 12000 0138 B0F1807F cmpne r0, #16777216 + 12001 013c 8BD1 bne .L735 +5374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12002 .loc 1 5374 9 is_stmt 1 view .LVU4201 + 12003 013e 2046 mov r0, r4 + 12004 .LVL863: +5374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12005 .loc 1 5374 9 is_stmt 0 view .LVU4202 + 12006 0140 FFF7FEFF bl I2C_ITSlaveSeqCplt + 12007 .LVL864: +5374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12008 .loc 1 5374 9 view .LVU4203 + 12009 0144 87E7 b .L735 + 12010 .LVL865: + 12011 .L744: +5264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12012 .loc 1 5264 3 discriminator 1 view .LVU4204 + 12013 0146 0220 movs r0, #2 + 12014 .LVL866: +5264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12015 .loc 1 5264 3 discriminator 1 view .LVU4205 + 12016 0148 88E7 b .L733 + 12017 .cfi_endproc + 12018 .LFE192: + 12020 .section .text.I2C_ITMasterCplt,"ax",%progbits + 12021 .align 1 + ARM GAS /tmp/ccSHpINd.s page 414 + + + 12022 .syntax unified + 12023 .thumb + 12024 .thumb_func + 12026 I2C_ITMasterCplt: + 12027 .LVL867: + 12028 .LFB201: +6180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmperror; + 12029 .loc 1 6180 1 is_stmt 1 view -0 + 12030 .cfi_startproc + 12031 @ args = 0, pretend = 0, frame = 8 + 12032 @ frame_needed = 0, uses_anonymous_args = 0 +6180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmperror; + 12033 .loc 1 6180 1 is_stmt 0 view .LVU4207 + 12034 0000 30B5 push {r4, r5, lr} + 12035 .LCFI125: + 12036 .cfi_def_cfa_offset 12 + 12037 .cfi_offset 4, -12 + 12038 .cfi_offset 5, -8 + 12039 .cfi_offset 14, -4 + 12040 0002 83B0 sub sp, sp, #12 + 12041 .LCFI126: + 12042 .cfi_def_cfa_offset 24 + 12043 0004 0446 mov r4, r0 + 12044 0006 0D46 mov r5, r1 +6181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 12045 .loc 1 6181 3 is_stmt 1 view .LVU4208 +6182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** __IO uint32_t tmpreg; + 12046 .loc 1 6182 3 view .LVU4209 + 12047 .LVL868: +6183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12048 .loc 1 6183 3 view .LVU4210 +6186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12049 .loc 1 6186 3 view .LVU4211 + 12050 0008 0368 ldr r3, [r0] + 12051 000a 2022 movs r2, #32 + 12052 000c DA61 str r2, [r3, #28] +6189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12053 .loc 1 6189 3 view .LVU4212 +6189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12054 .loc 1 6189 11 is_stmt 0 view .LVU4213 + 12055 000e 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 12056 0012 DBB2 uxtb r3, r3 +6189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12057 .loc 1 6189 6 view .LVU4214 + 12058 0014 212B cmp r3, #33 + 12059 0016 33D0 beq .L762 +6194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12060 .loc 1 6194 8 is_stmt 1 view .LVU4215 +6194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12061 .loc 1 6194 16 is_stmt 0 view .LVU4216 + 12062 0018 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 12063 001c DBB2 uxtb r3, r3 +6194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12064 .loc 1 6194 11 view .LVU4217 + 12065 001e 222B cmp r3, #34 + 12066 0020 34D0 beq .L763 + 12067 .LVL869: + ARM GAS /tmp/ccSHpINd.s page 415 + + + 12068 .L752: +6202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12069 .loc 1 6202 3 is_stmt 1 view .LVU4218 +6205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12070 .loc 1 6205 3 view .LVU4219 + 12071 0022 2268 ldr r2, [r4] + 12072 0024 5368 ldr r3, [r2, #4] + 12073 0026 23F0FF73 bic r3, r3, #33423360 + 12074 002a 23F48B33 bic r3, r3, #71168 + 12075 002e 23F4FF73 bic r3, r3, #510 + 12076 0032 23F00103 bic r3, r3, #1 + 12077 0036 5360 str r3, [r2, #4] +6208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 12078 .loc 1 6208 3 view .LVU4220 +6208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 12079 .loc 1 6208 23 is_stmt 0 view .LVU4221 + 12080 0038 0023 movs r3, #0 + 12081 003a 6363 str r3, [r4, #52] +6209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12082 .loc 1 6209 3 is_stmt 1 view .LVU4222 +6209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12083 .loc 1 6209 23 is_stmt 0 view .LVU4223 + 12084 003c A3F58033 sub r3, r3, #65536 + 12085 0040 E362 str r3, [r4, #44] +6211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12086 .loc 1 6211 3 is_stmt 1 view .LVU4224 +6211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12087 .loc 1 6211 6 is_stmt 0 view .LVU4225 + 12088 0042 15F0100F tst r5, #16 + 12089 0046 06D0 beq .L753 +6214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12090 .loc 1 6214 5 is_stmt 1 view .LVU4226 + 12091 0048 2368 ldr r3, [r4] + 12092 004a 1022 movs r2, #16 + 12093 004c DA61 str r2, [r3, #28] +6217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12094 .loc 1 6217 5 view .LVU4227 +6217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12095 .loc 1 6217 9 is_stmt 0 view .LVU4228 + 12096 004e 636C ldr r3, [r4, #68] +6217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12097 .loc 1 6217 21 view .LVU4229 + 12098 0050 43F00403 orr r3, r3, #4 + 12099 0054 6364 str r3, [r4, #68] + 12100 .L753: +6221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12101 .loc 1 6221 3 is_stmt 1 view .LVU4230 +6221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12102 .loc 1 6221 12 is_stmt 0 view .LVU4231 + 12103 0056 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 12104 005a DBB2 uxtb r3, r3 +6221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12105 .loc 1 6221 6 view .LVU4232 + 12106 005c 602B cmp r3, #96 + 12107 005e 1BD0 beq .L764 + 12108 .L754: +6229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 416 + + + 12109 .loc 1 6229 3 is_stmt 1 view .LVU4233 + 12110 0060 2046 mov r0, r4 + 12111 0062 FFF7FEFF bl I2C_Flush_TXDR + 12112 .LVL870: +6232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12113 .loc 1 6232 3 view .LVU4234 +6232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12114 .loc 1 6232 12 is_stmt 0 view .LVU4235 + 12115 0066 626C ldr r2, [r4, #68] + 12116 .LVL871: +6235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12117 .loc 1 6235 3 is_stmt 1 view .LVU4236 +6235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12118 .loc 1 6235 12 is_stmt 0 view .LVU4237 + 12119 0068 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 12120 006c DBB2 uxtb r3, r3 +6235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12121 .loc 1 6235 6 view .LVU4238 + 12122 006e 602B cmp r3, #96 + 12123 0070 00D0 beq .L755 +6235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12124 .loc 1 6235 44 discriminator 1 view .LVU4239 + 12125 0072 D2B1 cbz r2, .L756 + 12126 .L755: +6238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12127 .loc 1 6238 5 is_stmt 1 view .LVU4240 +6238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12128 .loc 1 6238 27 is_stmt 0 view .LVU4241 + 12129 0074 616C ldr r1, [r4, #68] +6238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12130 .loc 1 6238 5 view .LVU4242 + 12131 0076 2046 mov r0, r4 + 12132 0078 FFF7FEFF bl I2C_ITError + 12133 .LVL872: + 12134 .L750: +6314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12135 .loc 1 6314 1 view .LVU4243 + 12136 007c 03B0 add sp, sp, #12 + 12137 .LCFI127: + 12138 .cfi_remember_state + 12139 .cfi_def_cfa_offset 12 + 12140 @ sp needed + 12141 007e 30BD pop {r4, r5, pc} + 12142 .LVL873: + 12143 .L762: + 12144 .LCFI128: + 12145 .cfi_restore_state +6191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 12146 .loc 1 6191 5 is_stmt 1 view .LVU4244 + 12147 0080 0121 movs r1, #1 + 12148 .LVL874: +6191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 12149 .loc 1 6191 5 is_stmt 0 view .LVU4245 + 12150 0082 FFF7FEFF bl I2C_Disable_IRQ + 12151 .LVL875: +6192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12152 .loc 1 6192 5 is_stmt 1 view .LVU4246 + ARM GAS /tmp/ccSHpINd.s page 417 + + +6192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12153 .loc 1 6192 25 is_stmt 0 view .LVU4247 + 12154 0086 1123 movs r3, #17 + 12155 0088 2363 str r3, [r4, #48] + 12156 008a CAE7 b .L752 + 12157 .LVL876: + 12158 .L763: +6196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 12159 .loc 1 6196 5 is_stmt 1 view .LVU4248 + 12160 008c 0221 movs r1, #2 + 12161 .LVL877: +6196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 12162 .loc 1 6196 5 is_stmt 0 view .LVU4249 + 12163 008e FFF7FEFF bl I2C_Disable_IRQ + 12164 .LVL878: +6197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12165 .loc 1 6197 5 is_stmt 1 view .LVU4250 +6197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12166 .loc 1 6197 25 is_stmt 0 view .LVU4251 + 12167 0092 1223 movs r3, #18 + 12168 0094 2363 str r3, [r4, #48] + 12169 0096 C4E7 b .L752 + 12170 .L764: +6221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12171 .loc 1 6221 44 discriminator 1 view .LVU4252 + 12172 0098 15F0040F tst r5, #4 + 12173 009c E0D0 beq .L754 +6224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(tmpreg); + 12174 .loc 1 6224 5 is_stmt 1 view .LVU4253 +6224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(tmpreg); + 12175 .loc 1 6224 27 is_stmt 0 view .LVU4254 + 12176 009e 2368 ldr r3, [r4] +6224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(tmpreg); + 12177 .loc 1 6224 37 view .LVU4255 + 12178 00a0 5B6A ldr r3, [r3, #36] + 12179 00a2 DBB2 uxtb r3, r3 +6224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** UNUSED(tmpreg); + 12180 .loc 1 6224 12 view .LVU4256 + 12181 00a4 0193 str r3, [sp, #4] +6225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12182 .loc 1 6225 5 is_stmt 1 view .LVU4257 + 12183 00a6 019B ldr r3, [sp, #4] + 12184 00a8 DAE7 b .L754 + 12185 .LVL879: + 12186 .L756: +6241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12187 .loc 1 6241 8 view .LVU4258 +6241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12188 .loc 1 6241 16 is_stmt 0 view .LVU4259 + 12189 00aa 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 12190 00ae DBB2 uxtb r3, r3 +6241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12191 .loc 1 6241 11 view .LVU4260 + 12192 00b0 212B cmp r3, #33 + 12193 00b2 17D0 beq .L765 +6276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12194 .loc 1 6276 8 is_stmt 1 view .LVU4261 + ARM GAS /tmp/ccSHpINd.s page 418 + + +6276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12195 .loc 1 6276 16 is_stmt 0 view .LVU4262 + 12196 00b4 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 12197 00b8 DBB2 uxtb r3, r3 +6276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12198 .loc 1 6276 11 view .LVU4263 + 12199 00ba 222B cmp r3, #34 + 12200 00bc DED1 bne .L750 +6278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 12201 .loc 1 6278 5 is_stmt 1 view .LVU4264 +6278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 12202 .loc 1 6278 17 is_stmt 0 view .LVU4265 + 12203 00be 2023 movs r3, #32 + 12204 00c0 84F84130 strb r3, [r4, #65] +6279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12205 .loc 1 6279 5 is_stmt 1 view .LVU4266 +6279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12206 .loc 1 6279 25 is_stmt 0 view .LVU4267 + 12207 00c4 0023 movs r3, #0 + 12208 00c6 2363 str r3, [r4, #48] +6281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12209 .loc 1 6281 5 is_stmt 1 view .LVU4268 +6281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12210 .loc 1 6281 13 is_stmt 0 view .LVU4269 + 12211 00c8 94F84230 ldrb r3, [r4, #66] @ zero_extendqisi2 + 12212 00cc DBB2 uxtb r3, r3 +6281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12213 .loc 1 6281 8 view .LVU4270 + 12214 00ce 402B cmp r3, #64 + 12215 00d0 24D0 beq .L766 +6297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12216 .loc 1 6297 7 is_stmt 1 view .LVU4271 +6297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12217 .loc 1 6297 18 is_stmt 0 view .LVU4272 + 12218 00d2 0023 movs r3, #0 + 12219 00d4 84F84230 strb r3, [r4, #66] +6300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12220 .loc 1 6300 7 is_stmt 1 view .LVU4273 +6300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12221 .loc 1 6300 7 view .LVU4274 + 12222 00d8 84F84030 strb r3, [r4, #64] +6300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12223 .loc 1 6300 7 view .LVU4275 +6306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 12224 .loc 1 6306 7 view .LVU4276 + 12225 00dc 2046 mov r0, r4 + 12226 00de FFF7FEFF bl HAL_I2C_MasterRxCpltCallback + 12227 .LVL880: +6313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12228 .loc 1 6313 3 view .LVU4277 +6314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12229 .loc 1 6314 1 is_stmt 0 view .LVU4278 + 12230 00e2 CBE7 b .L750 + 12231 .LVL881: + 12232 .L765: +6243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 12233 .loc 1 6243 5 is_stmt 1 view .LVU4279 + ARM GAS /tmp/ccSHpINd.s page 419 + + +6243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 12234 .loc 1 6243 17 is_stmt 0 view .LVU4280 + 12235 00e4 2023 movs r3, #32 + 12236 00e6 84F84130 strb r3, [r4, #65] +6244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12237 .loc 1 6244 5 is_stmt 1 view .LVU4281 +6244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12238 .loc 1 6244 25 is_stmt 0 view .LVU4282 + 12239 00ea 0023 movs r3, #0 + 12240 00ec 2363 str r3, [r4, #48] +6246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12241 .loc 1 6246 5 is_stmt 1 view .LVU4283 +6246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12242 .loc 1 6246 13 is_stmt 0 view .LVU4284 + 12243 00ee 94F84230 ldrb r3, [r4, #66] @ zero_extendqisi2 + 12244 00f2 DBB2 uxtb r3, r3 +6246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12245 .loc 1 6246 8 view .LVU4285 + 12246 00f4 402B cmp r3, #64 + 12247 00f6 08D0 beq .L767 +6262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12248 .loc 1 6262 7 is_stmt 1 view .LVU4286 +6262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12249 .loc 1 6262 18 is_stmt 0 view .LVU4287 + 12250 00f8 0023 movs r3, #0 + 12251 00fa 84F84230 strb r3, [r4, #66] +6265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12252 .loc 1 6265 7 is_stmt 1 view .LVU4288 +6265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12253 .loc 1 6265 7 view .LVU4289 + 12254 00fe 84F84030 strb r3, [r4, #64] +6265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12255 .loc 1 6265 7 view .LVU4290 +6271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 12256 .loc 1 6271 7 view .LVU4291 + 12257 0102 2046 mov r0, r4 + 12258 0104 FFF7FEFF bl HAL_I2C_MasterTxCpltCallback + 12259 .LVL882: +6271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 12260 .loc 1 6271 7 is_stmt 0 view .LVU4292 + 12261 0108 B8E7 b .L750 + 12262 .LVL883: + 12263 .L767: +6248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12264 .loc 1 6248 7 is_stmt 1 view .LVU4293 +6248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12265 .loc 1 6248 18 is_stmt 0 view .LVU4294 + 12266 010a 0023 movs r3, #0 + 12267 010c 84F84230 strb r3, [r4, #66] +6251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12268 .loc 1 6251 7 is_stmt 1 view .LVU4295 +6251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12269 .loc 1 6251 7 view .LVU4296 + 12270 0110 84F84030 strb r3, [r4, #64] +6251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12271 .loc 1 6251 7 view .LVU4297 +6257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + ARM GAS /tmp/ccSHpINd.s page 420 + + + 12272 .loc 1 6257 7 view .LVU4298 + 12273 0114 2046 mov r0, r4 + 12274 0116 FFF7FEFF bl HAL_I2C_MemTxCpltCallback + 12275 .LVL884: +6257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 12276 .loc 1 6257 7 is_stmt 0 view .LVU4299 + 12277 011a AFE7 b .L750 + 12278 .LVL885: + 12279 .L766: +6283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12280 .loc 1 6283 7 is_stmt 1 view .LVU4300 +6283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12281 .loc 1 6283 18 is_stmt 0 view .LVU4301 + 12282 011c 0023 movs r3, #0 + 12283 011e 84F84230 strb r3, [r4, #66] +6286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12284 .loc 1 6286 7 is_stmt 1 view .LVU4302 +6286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12285 .loc 1 6286 7 view .LVU4303 + 12286 0122 84F84030 strb r3, [r4, #64] +6286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12287 .loc 1 6286 7 view .LVU4304 +6292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 12288 .loc 1 6292 7 view .LVU4305 + 12289 0126 2046 mov r0, r4 + 12290 0128 FFF7FEFF bl HAL_I2C_MemRxCpltCallback + 12291 .LVL886: +6292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 12292 .loc 1 6292 7 is_stmt 0 view .LVU4306 + 12293 012c A6E7 b .L750 + 12294 .cfi_endproc + 12295 .LFE201: + 12297 .section .text.I2C_Master_ISR_IT,"ax",%progbits + 12298 .align 1 + 12299 .syntax unified + 12300 .thumb + 12301 .thumb_func + 12303 I2C_Master_ISR_IT: + 12304 .LVL887: + 12305 .LFB190: +4941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t devaddress; + 12306 .loc 1 4941 1 is_stmt 1 view -0 + 12307 .cfi_startproc + 12308 @ args = 0, pretend = 0, frame = 0 + 12309 @ frame_needed = 0, uses_anonymous_args = 0 +4942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 12310 .loc 1 4942 3 view .LVU4308 +4943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12311 .loc 1 4943 3 view .LVU4309 +4946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12312 .loc 1 4946 3 view .LVU4310 +4946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12313 .loc 1 4946 3 view .LVU4311 + 12314 0000 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 12315 0004 012B cmp r3, #1 + 12316 0006 00F0CF80 beq .L784 +4941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t devaddress; + ARM GAS /tmp/ccSHpINd.s page 421 + + + 12317 .loc 1 4941 1 is_stmt 0 view .LVU4312 + 12318 000a 70B5 push {r4, r5, r6, lr} + 12319 .LCFI129: + 12320 .cfi_def_cfa_offset 16 + 12321 .cfi_offset 4, -16 + 12322 .cfi_offset 5, -12 + 12323 .cfi_offset 6, -8 + 12324 .cfi_offset 14, -4 + 12325 000c 82B0 sub sp, sp, #8 + 12326 .LCFI130: + 12327 .cfi_def_cfa_offset 24 + 12328 000e 0446 mov r4, r0 + 12329 0010 0D46 mov r5, r1 + 12330 0012 1646 mov r6, r2 +4946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12331 .loc 1 4946 3 is_stmt 1 discriminator 2 view .LVU4313 + 12332 0014 0123 movs r3, #1 + 12333 0016 80F84030 strb r3, [r0, #64] +4946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12334 .loc 1 4946 3 discriminator 2 view .LVU4314 +4948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 12335 .loc 1 4948 3 view .LVU4315 +4948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 12336 .loc 1 4948 6 is_stmt 0 view .LVU4316 + 12337 001a 11F0100F tst r1, #16 + 12338 001e 02D0 beq .L770 +4948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 12339 .loc 1 4948 58 discriminator 1 view .LVU4317 + 12340 0020 12F0100F tst r2, #16 + 12341 0024 22D1 bne .L789 + 12342 .L770: +4962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 12343 .loc 1 4962 8 is_stmt 1 view .LVU4318 +4962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 12344 .loc 1 4962 11 is_stmt 0 view .LVU4319 + 12345 0026 15F0040F tst r5, #4 + 12346 002a 29D0 beq .L772 +4962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 12347 .loc 1 4962 65 discriminator 1 view .LVU4320 + 12348 002c 16F0040F tst r6, #4 + 12349 0030 26D0 beq .L772 +4966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12350 .loc 1 4966 5 is_stmt 1 view .LVU4321 +4966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12351 .loc 1 4966 16 is_stmt 0 view .LVU4322 + 12352 0032 25F00405 bic r5, r5, #4 + 12353 .LVL888: +4969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12354 .loc 1 4969 5 is_stmt 1 view .LVU4323 +4969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12355 .loc 1 4969 36 is_stmt 0 view .LVU4324 + 12356 0036 2368 ldr r3, [r4] +4969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12357 .loc 1 4969 46 view .LVU4325 + 12358 0038 5A6A ldr r2, [r3, #36] + 12359 .LVL889: +4969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 422 + + + 12360 .loc 1 4969 10 view .LVU4326 + 12361 003a 636A ldr r3, [r4, #36] +4969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12362 .loc 1 4969 21 view .LVU4327 + 12363 003c 1A70 strb r2, [r3] +4972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12364 .loc 1 4972 5 is_stmt 1 view .LVU4328 +4972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12365 .loc 1 4972 9 is_stmt 0 view .LVU4329 + 12366 003e 636A ldr r3, [r4, #36] +4972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12367 .loc 1 4972 19 view .LVU4330 + 12368 0040 0133 adds r3, r3, #1 + 12369 0042 6362 str r3, [r4, #36] +4974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 12370 .loc 1 4974 5 is_stmt 1 view .LVU4331 +4974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 12371 .loc 1 4974 9 is_stmt 0 view .LVU4332 + 12372 0044 238D ldrh r3, [r4, #40] +4974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 12373 .loc 1 4974 19 view .LVU4333 + 12374 0046 013B subs r3, r3, #1 + 12375 0048 2385 strh r3, [r4, #40] @ movhi +4975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12376 .loc 1 4975 5 is_stmt 1 view .LVU4334 +4975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12377 .loc 1 4975 9 is_stmt 0 view .LVU4335 + 12378 004a 638D ldrh r3, [r4, #42] + 12379 004c 9BB2 uxth r3, r3 +4975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12380 .loc 1 4975 20 view .LVU4336 + 12381 004e 013B subs r3, r3, #1 + 12382 0050 9BB2 uxth r3, r3 + 12383 0052 6385 strh r3, [r4, #42] @ movhi + 12384 .LVL890: + 12385 .L771: +5075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12386 .loc 1 5075 3 is_stmt 1 view .LVU4337 +5077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 12387 .loc 1 5077 3 view .LVU4338 +5077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 12388 .loc 1 5077 6 is_stmt 0 view .LVU4339 + 12389 0054 15F0200F tst r5, #32 + 12390 0058 03D0 beq .L783 +5077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 12391 .loc 1 5077 61 discriminator 1 view .LVU4340 + 12392 005a 16F0200F tst r6, #32 + 12393 005e 40F09E80 bne .L790 + 12394 .L783: +5085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12395 .loc 1 5085 3 is_stmt 1 view .LVU4341 +5085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12396 .loc 1 5085 3 view .LVU4342 + 12397 0062 0020 movs r0, #0 + 12398 0064 84F84000 strb r0, [r4, #64] +5085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12399 .loc 1 5085 3 view .LVU4343 + ARM GAS /tmp/ccSHpINd.s page 423 + + +5087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12400 .loc 1 5087 3 view .LVU4344 +5088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12401 .loc 1 5088 1 is_stmt 0 view .LVU4345 + 12402 0068 02B0 add sp, sp, #8 + 12403 .LCFI131: + 12404 .cfi_remember_state + 12405 .cfi_def_cfa_offset 16 + 12406 @ sp needed + 12407 006a 70BD pop {r4, r5, r6, pc} + 12408 .LVL891: + 12409 .L789: + 12410 .LCFI132: + 12411 .cfi_restore_state +4952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12412 .loc 1 4952 5 is_stmt 1 view .LVU4346 + 12413 006c 0368 ldr r3, [r0] + 12414 006e 1022 movs r2, #16 + 12415 .LVL892: +4952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12416 .loc 1 4952 5 is_stmt 0 view .LVU4347 + 12417 0070 DA61 str r2, [r3, #28] +4957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12418 .loc 1 4957 5 is_stmt 1 view .LVU4348 +4957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12419 .loc 1 4957 9 is_stmt 0 view .LVU4349 + 12420 0072 436C ldr r3, [r0, #68] +4957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12421 .loc 1 4957 21 view .LVU4350 + 12422 0074 43F00403 orr r3, r3, #4 + 12423 0078 4364 str r3, [r0, #68] +4960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12424 .loc 1 4960 5 is_stmt 1 view .LVU4351 + 12425 007a FFF7FEFF bl I2C_Flush_TXDR + 12426 .LVL893: +4960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12427 .loc 1 4960 5 is_stmt 0 view .LVU4352 + 12428 007e E9E7 b .L771 + 12429 .LVL894: + 12430 .L772: +4977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + 12431 .loc 1 4977 8 is_stmt 1 view .LVU4353 + 12432 0080 C5F38013 ubfx r3, r5, #6, #1 +4977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + 12433 .loc 1 4977 11 is_stmt 0 view .LVU4354 + 12434 0084 15F0400F tst r5, #64 + 12435 0088 19D1 bne .L773 +4977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + 12436 .loc 1 4977 63 discriminator 1 view .LVU4355 + 12437 008a 15F0020F tst r5, #2 + 12438 008e 16D0 beq .L773 +4978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))) + 12439 .loc 1 4978 66 view .LVU4356 + 12440 0090 16F0020F tst r6, #2 + 12441 0094 13D0 beq .L773 +4982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12442 .loc 1 4982 5 is_stmt 1 view .LVU4357 + ARM GAS /tmp/ccSHpINd.s page 424 + + +4982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12443 .loc 1 4982 13 is_stmt 0 view .LVU4358 + 12444 0096 638D ldrh r3, [r4, #42] + 12445 0098 9BB2 uxth r3, r3 +4982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12446 .loc 1 4982 8 view .LVU4359 + 12447 009a 002B cmp r3, #0 + 12448 009c DAD0 beq .L771 +4985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12449 .loc 1 4985 7 is_stmt 1 view .LVU4360 +4985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12450 .loc 1 4985 35 is_stmt 0 view .LVU4361 + 12451 009e 626A ldr r2, [r4, #36] + 12452 .LVL895: +4985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12453 .loc 1 4985 11 view .LVU4362 + 12454 00a0 2368 ldr r3, [r4] +4985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12455 .loc 1 4985 30 view .LVU4363 + 12456 00a2 1278 ldrb r2, [r2] @ zero_extendqisi2 +4985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12457 .loc 1 4985 28 view .LVU4364 + 12458 00a4 9A62 str r2, [r3, #40] +4988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12459 .loc 1 4988 7 is_stmt 1 view .LVU4365 +4988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12460 .loc 1 4988 11 is_stmt 0 view .LVU4366 + 12461 00a6 636A ldr r3, [r4, #36] +4988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12462 .loc 1 4988 21 view .LVU4367 + 12463 00a8 0133 adds r3, r3, #1 + 12464 00aa 6362 str r3, [r4, #36] +4990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 12465 .loc 1 4990 7 is_stmt 1 view .LVU4368 +4990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 12466 .loc 1 4990 11 is_stmt 0 view .LVU4369 + 12467 00ac 238D ldrh r3, [r4, #40] +4990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 12468 .loc 1 4990 21 view .LVU4370 + 12469 00ae 013B subs r3, r3, #1 + 12470 00b0 2385 strh r3, [r4, #40] @ movhi +4991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12471 .loc 1 4991 7 is_stmt 1 view .LVU4371 +4991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12472 .loc 1 4991 11 is_stmt 0 view .LVU4372 + 12473 00b2 638D ldrh r3, [r4, #42] + 12474 00b4 9BB2 uxth r3, r3 +4991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12475 .loc 1 4991 22 view .LVU4373 + 12476 00b6 013B subs r3, r3, #1 + 12477 00b8 9BB2 uxth r3, r3 + 12478 00ba 6385 strh r3, [r4, #42] @ movhi + 12479 00bc CAE7 b .L771 + 12480 .LVL896: + 12481 .L773: +4994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12482 .loc 1 4994 8 is_stmt 1 view .LVU4374 + ARM GAS /tmp/ccSHpINd.s page 425 + + +4994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12483 .loc 1 4994 11 is_stmt 0 view .LVU4375 + 12484 00be 15F0800F tst r5, #128 + 12485 00c2 4AD0 beq .L774 +4994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12486 .loc 1 4994 64 discriminator 1 view .LVU4376 + 12487 00c4 16F0400F tst r6, #64 + 12488 00c8 47D0 beq .L774 +4997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12489 .loc 1 4997 5 is_stmt 1 view .LVU4377 +4997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12490 .loc 1 4997 14 is_stmt 0 view .LVU4378 + 12491 00ca 638D ldrh r3, [r4, #42] + 12492 00cc 9BB2 uxth r3, r3 +4997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12493 .loc 1 4997 8 view .LVU4379 + 12494 00ce 002B cmp r3, #0 + 12495 00d0 35D0 beq .L775 +4997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12496 .loc 1 4997 41 discriminator 1 view .LVU4380 + 12497 00d2 238D ldrh r3, [r4, #40] +4997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12498 .loc 1 4997 33 discriminator 1 view .LVU4381 + 12499 00d4 002B cmp r3, #0 + 12500 00d6 32D1 bne .L775 +4999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12501 .loc 1 4999 7 is_stmt 1 view .LVU4382 +4999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12502 .loc 1 4999 35 is_stmt 0 view .LVU4383 + 12503 00d8 2268 ldr r2, [r4] + 12504 .LVL897: +4999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12505 .loc 1 4999 45 view .LVU4384 + 12506 00da 5168 ldr r1, [r2, #4] + 12507 .LVL898: +4999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12508 .loc 1 4999 18 view .LVU4385 + 12509 00dc C1F30901 ubfx r1, r1, #0, #10 + 12510 .LVL899: +5001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12511 .loc 1 5001 7 is_stmt 1 view .LVU4386 +5001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12512 .loc 1 5001 15 is_stmt 0 view .LVU4387 + 12513 00e0 638D ldrh r3, [r4, #42] + 12514 00e2 9BB2 uxth r3, r3 +5001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12515 .loc 1 5001 10 view .LVU4388 + 12516 00e4 FF2B cmp r3, #255 + 12517 00e6 12D9 bls .L776 +5004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12518 .loc 1 5004 9 is_stmt 1 view .LVU4389 +5004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12519 .loc 1 5004 13 is_stmt 0 view .LVU4390 + 12520 00e8 9369 ldr r3, [r2, #24] +5004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12521 .loc 1 5004 12 view .LVU4391 + 12522 00ea 13F4803F tst r3, #65536 + ARM GAS /tmp/ccSHpINd.s page 426 + + + 12523 00ee 0BD0 beq .L777 +5006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12524 .loc 1 5006 11 is_stmt 1 view .LVU4392 +5006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12525 .loc 1 5006 26 is_stmt 0 view .LVU4393 + 12526 00f0 0123 movs r3, #1 + 12527 00f2 2385 strh r3, [r4, #40] @ movhi + 12528 .L778: +5012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12529 .loc 1 5012 9 is_stmt 1 view .LVU4394 + 12530 00f4 0023 movs r3, #0 + 12531 00f6 0093 str r3, [sp] + 12532 00f8 4FF08073 mov r3, #16777216 + 12533 00fc 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 12534 0100 2046 mov r0, r4 + 12535 .LVL900: +5012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12536 .loc 1 5012 9 is_stmt 0 view .LVU4395 + 12537 0102 FFF7FEFF bl I2C_TransferConfig + 12538 .LVL901: +5012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12539 .loc 1 5012 9 view .LVU4396 + 12540 0106 A5E7 b .L771 + 12541 .LVL902: + 12542 .L777: +5010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12543 .loc 1 5010 11 is_stmt 1 view .LVU4397 +5010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12544 .loc 1 5010 26 is_stmt 0 view .LVU4398 + 12545 0108 FF23 movs r3, #255 + 12546 010a 2385 strh r3, [r4, #40] @ movhi + 12547 010c F2E7 b .L778 + 12548 .L776: +5016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 12549 .loc 1 5016 9 is_stmt 1 view .LVU4399 +5016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 12550 .loc 1 5016 30 is_stmt 0 view .LVU4400 + 12551 010e 628D ldrh r2, [r4, #42] + 12552 0110 92B2 uxth r2, r2 +5016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 12553 .loc 1 5016 24 view .LVU4401 + 12554 0112 2285 strh r2, [r4, #40] @ movhi +5017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12555 .loc 1 5017 9 is_stmt 1 view .LVU4402 +5017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12556 .loc 1 5017 17 is_stmt 0 view .LVU4403 + 12557 0114 E36A ldr r3, [r4, #44] +5017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12558 .loc 1 5017 12 view .LVU4404 + 12559 0116 13F5803F cmn r3, #65536 + 12560 011a 07D0 beq .L779 +5019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions, I2C_NO_STARTSTOP); + 12561 .loc 1 5019 11 is_stmt 1 view .LVU4405 +5020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12562 .loc 1 5020 34 is_stmt 0 view .LVU4406 + 12563 011c E36A ldr r3, [r4, #44] +5019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions, I2C_NO_STARTSTOP); + ARM GAS /tmp/ccSHpINd.s page 427 + + + 12564 .loc 1 5019 11 view .LVU4407 + 12565 011e 0020 movs r0, #0 + 12566 .LVL903: +5019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions, I2C_NO_STARTSTOP); + 12567 .loc 1 5019 11 view .LVU4408 + 12568 0120 0090 str r0, [sp] + 12569 0122 D2B2 uxtb r2, r2 + 12570 0124 2046 mov r0, r4 + 12571 0126 FFF7FEFF bl I2C_TransferConfig + 12572 .LVL904: +5019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferOptions, I2C_NO_STARTSTOP); + 12573 .loc 1 5019 11 view .LVU4409 + 12574 012a 93E7 b .L771 + 12575 .LVL905: + 12576 .L779: +5024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 12577 .loc 1 5024 11 is_stmt 1 view .LVU4410 + 12578 012c 0023 movs r3, #0 + 12579 012e 0093 str r3, [sp] + 12580 0130 4FF00073 mov r3, #33554432 + 12581 0134 D2B2 uxtb r2, r2 + 12582 0136 2046 mov r0, r4 + 12583 .LVL906: +5024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 12584 .loc 1 5024 11 is_stmt 0 view .LVU4411 + 12585 0138 FFF7FEFF bl I2C_TransferConfig + 12586 .LVL907: +5024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 12587 .loc 1 5024 11 view .LVU4412 + 12588 013c 8AE7 b .L771 + 12589 .LVL908: + 12590 .L775: +5032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12591 .loc 1 5032 7 is_stmt 1 view .LVU4413 +5032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12592 .loc 1 5032 11 is_stmt 0 view .LVU4414 + 12593 013e 2368 ldr r3, [r4] + 12594 0140 5B68 ldr r3, [r3, #4] +5032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12595 .loc 1 5032 10 view .LVU4415 + 12596 0142 13F0007F tst r3, #33554432 + 12597 0146 03D1 bne .L780 +5035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12598 .loc 1 5035 9 is_stmt 1 view .LVU4416 + 12599 0148 2046 mov r0, r4 + 12600 .LVL909: +5035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12601 .loc 1 5035 9 is_stmt 0 view .LVU4417 + 12602 014a FFF7FEFF bl I2C_ITMasterSeqCplt + 12603 .LVL910: +5035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12604 .loc 1 5035 9 view .LVU4418 + 12605 014e 81E7 b .L771 + 12606 .LVL911: + 12607 .L780: +5041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12608 .loc 1 5041 9 is_stmt 1 view .LVU4419 + ARM GAS /tmp/ccSHpINd.s page 428 + + + 12609 0150 4021 movs r1, #64 + 12610 .LVL912: +5041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12611 .loc 1 5041 9 is_stmt 0 view .LVU4420 + 12612 0152 2046 mov r0, r4 + 12613 .LVL913: +5041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12614 .loc 1 5041 9 view .LVU4421 + 12615 0154 FFF7FEFF bl I2C_ITError + 12616 .LVL914: +5041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12617 .loc 1 5041 9 view .LVU4422 + 12618 0158 7CE7 b .L771 + 12619 .LVL915: + 12620 .L774: +5045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12621 .loc 1 5045 8 is_stmt 1 view .LVU4423 +5045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12622 .loc 1 5045 11 is_stmt 0 view .LVU4424 + 12623 015a 002B cmp r3, #0 + 12624 015c 3FF47AAF beq .L771 +5045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12625 .loc 1 5045 63 discriminator 1 view .LVU4425 + 12626 0160 16F0400F tst r6, #64 + 12627 0164 3FF476AF beq .L771 +5048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12628 .loc 1 5048 5 is_stmt 1 view .LVU4426 +5048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12629 .loc 1 5048 13 is_stmt 0 view .LVU4427 + 12630 0168 638D ldrh r3, [r4, #42] + 12631 016a 9BB2 uxth r3, r3 +5048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12632 .loc 1 5048 8 view .LVU4428 + 12633 016c 93B9 cbnz r3, .L781 +5050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12634 .loc 1 5050 7 is_stmt 1 view .LVU4429 +5050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12635 .loc 1 5050 11 is_stmt 0 view .LVU4430 + 12636 016e 2368 ldr r3, [r4] + 12637 0170 5A68 ldr r2, [r3, #4] + 12638 .LVL916: +5050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12639 .loc 1 5050 10 view .LVU4431 + 12640 0172 12F0007F tst r2, #33554432 + 12641 0176 7FF46DAF bne .L771 +5053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12642 .loc 1 5053 9 is_stmt 1 view .LVU4432 +5053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12643 .loc 1 5053 17 is_stmt 0 view .LVU4433 + 12644 017a E26A ldr r2, [r4, #44] +5053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12645 .loc 1 5053 12 view .LVU4434 + 12646 017c 12F5803F cmn r2, #65536 + 12647 0180 04D1 bne .L782 +5056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12648 .loc 1 5056 11 is_stmt 1 view .LVU4435 +5056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + ARM GAS /tmp/ccSHpINd.s page 429 + + + 12649 .loc 1 5056 25 is_stmt 0 view .LVU4436 + 12650 0182 5A68 ldr r2, [r3, #4] +5056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12651 .loc 1 5056 31 view .LVU4437 + 12652 0184 42F48042 orr r2, r2, #16384 + 12653 0188 5A60 str r2, [r3, #4] + 12654 018a 63E7 b .L771 + 12655 .L782: +5061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12656 .loc 1 5061 11 is_stmt 1 view .LVU4438 + 12657 018c 2046 mov r0, r4 + 12658 .LVL917: +5061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12659 .loc 1 5061 11 is_stmt 0 view .LVU4439 + 12660 018e FFF7FEFF bl I2C_ITMasterSeqCplt + 12661 .LVL918: +5061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12662 .loc 1 5061 11 view .LVU4440 + 12663 0192 5FE7 b .L771 + 12664 .LVL919: + 12665 .L781: +5069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12666 .loc 1 5069 7 is_stmt 1 view .LVU4441 + 12667 0194 4021 movs r1, #64 + 12668 .LVL920: +5069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12669 .loc 1 5069 7 is_stmt 0 view .LVU4442 + 12670 0196 2046 mov r0, r4 + 12671 .LVL921: +5069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12672 .loc 1 5069 7 view .LVU4443 + 12673 0198 FFF7FEFF bl I2C_ITError + 12674 .LVL922: +5069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12675 .loc 1 5069 7 view .LVU4444 + 12676 019c 5AE7 b .L771 + 12677 .LVL923: + 12678 .L790: +5081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12679 .loc 1 5081 5 is_stmt 1 view .LVU4445 + 12680 019e 2946 mov r1, r5 + 12681 01a0 2046 mov r0, r4 + 12682 01a2 FFF7FEFF bl I2C_ITMasterCplt + 12683 .LVL924: + 12684 01a6 5CE7 b .L783 + 12685 .LVL925: + 12686 .L784: + 12687 .LCFI133: + 12688 .cfi_def_cfa_offset 0 + 12689 .cfi_restore 4 + 12690 .cfi_restore 5 + 12691 .cfi_restore 6 + 12692 .cfi_restore 14 +4946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12693 .loc 1 4946 3 is_stmt 0 discriminator 1 view .LVU4446 + 12694 01a8 0220 movs r0, #2 + 12695 .LVL926: + ARM GAS /tmp/ccSHpINd.s page 430 + + +5088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12696 .loc 1 5088 1 view .LVU4447 + 12697 01aa 7047 bx lr + 12698 .cfi_endproc + 12699 .LFE190: + 12701 .section .text.I2C_Mem_ISR_DMA,"ax",%progbits + 12702 .align 1 + 12703 .syntax unified + 12704 .thumb + 12705 .thumb_func + 12707 I2C_Mem_ISR_DMA: + 12708 .LVL927: + 12709 .LFB194: +5547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t direction = I2C_GENERATE_START_WRITE; + 12710 .loc 1 5547 1 is_stmt 1 view -0 + 12711 .cfi_startproc + 12712 @ args = 0, pretend = 0, frame = 0 + 12713 @ frame_needed = 0, uses_anonymous_args = 0 +5548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12714 .loc 1 5548 3 view .LVU4449 +5551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12715 .loc 1 5551 3 view .LVU4450 +5551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12716 .loc 1 5551 3 view .LVU4451 + 12717 0000 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 12718 0004 012B cmp r3, #1 + 12719 0006 00F0DC80 beq .L810 +5547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t direction = I2C_GENERATE_START_WRITE; + 12720 .loc 1 5547 1 is_stmt 0 view .LVU4452 + 12721 000a 10B5 push {r4, lr} + 12722 .LCFI134: + 12723 .cfi_def_cfa_offset 8 + 12724 .cfi_offset 4, -8 + 12725 .cfi_offset 14, -4 + 12726 000c 82B0 sub sp, sp, #8 + 12727 .LCFI135: + 12728 .cfi_def_cfa_offset 16 + 12729 000e 0446 mov r4, r0 +5551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12730 .loc 1 5551 3 is_stmt 1 discriminator 2 view .LVU4453 + 12731 0010 0123 movs r3, #1 + 12732 0012 80F84030 strb r3, [r0, #64] +5551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12733 .loc 1 5551 3 discriminator 2 view .LVU4454 +5553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 12734 .loc 1 5553 3 view .LVU4455 +5553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 12735 .loc 1 5553 6 is_stmt 0 view .LVU4456 + 12736 0016 11F0100F tst r1, #16 + 12737 001a 02D0 beq .L793 +5553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 12738 .loc 1 5553 55 discriminator 1 view .LVU4457 + 12739 001c 12F0100F tst r2, #16 + 12740 0020 10D1 bne .L816 + 12741 .L793: +5570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 12742 .loc 1 5570 8 is_stmt 1 view .LVU4458 + ARM GAS /tmp/ccSHpINd.s page 431 + + +5570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 12743 .loc 1 5570 11 is_stmt 0 view .LVU4459 + 12744 0022 11F0020F tst r1, #2 + 12745 0026 1BD0 beq .L795 +5570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 12746 .loc 1 5570 62 discriminator 1 view .LVU4460 + 12747 0028 12F0020F tst r2, #2 + 12748 002c 18D0 beq .L795 +5574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12749 .loc 1 5574 5 is_stmt 1 view .LVU4461 +5574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12750 .loc 1 5574 9 is_stmt 0 view .LVU4462 + 12751 002e 2368 ldr r3, [r4] +5574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12752 .loc 1 5574 32 view .LVU4463 + 12753 0030 226D ldr r2, [r4, #80] + 12754 .LVL928: +5574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12755 .loc 1 5574 26 view .LVU4464 + 12756 0032 9A62 str r2, [r3, #40] +5577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12757 .loc 1 5577 5 is_stmt 1 view .LVU4465 +5577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12758 .loc 1 5577 22 is_stmt 0 view .LVU4466 + 12759 0034 4FF0FF33 mov r3, #-1 + 12760 0038 2365 str r3, [r4, #80] + 12761 .LVL929: + 12762 .L794: +5693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12763 .loc 1 5693 3 is_stmt 1 view .LVU4467 +5696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12764 .loc 1 5696 3 view .LVU4468 +5696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12765 .loc 1 5696 3 view .LVU4469 + 12766 003a 0020 movs r0, #0 + 12767 003c 84F84000 strb r0, [r4, #64] +5696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12768 .loc 1 5696 3 view .LVU4470 +5698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12769 .loc 1 5698 3 view .LVU4471 +5699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12770 .loc 1 5699 1 is_stmt 0 view .LVU4472 + 12771 0040 02B0 add sp, sp, #8 + 12772 .LCFI136: + 12773 .cfi_remember_state + 12774 .cfi_def_cfa_offset 8 + 12775 @ sp needed + 12776 0042 10BD pop {r4, pc} + 12777 .LVL930: + 12778 .L816: + 12779 .LCFI137: + 12780 .cfi_restore_state +5557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12781 .loc 1 5557 5 is_stmt 1 view .LVU4473 + 12782 0044 0368 ldr r3, [r0] + 12783 0046 1022 movs r2, #16 + 12784 .LVL931: + ARM GAS /tmp/ccSHpINd.s page 432 + + +5557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12785 .loc 1 5557 5 is_stmt 0 view .LVU4474 + 12786 0048 DA61 str r2, [r3, #28] +5560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12787 .loc 1 5560 5 is_stmt 1 view .LVU4475 +5560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12788 .loc 1 5560 9 is_stmt 0 view .LVU4476 + 12789 004a 436C ldr r3, [r0, #68] +5560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12790 .loc 1 5560 21 view .LVU4477 + 12791 004c 43F00403 orr r3, r3, #4 + 12792 0050 4364 str r3, [r0, #68] +5565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12793 .loc 1 5565 5 is_stmt 1 view .LVU4478 + 12794 0052 2021 movs r1, #32 + 12795 .LVL932: +5565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12796 .loc 1 5565 5 is_stmt 0 view .LVU4479 + 12797 0054 FFF7FEFF bl I2C_Enable_IRQ + 12798 .LVL933: +5568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12799 .loc 1 5568 5 is_stmt 1 view .LVU4480 + 12800 0058 2046 mov r0, r4 + 12801 005a FFF7FEFF bl I2C_Flush_TXDR + 12802 .LVL934: + 12803 005e ECE7 b .L794 + 12804 .LVL935: + 12805 .L795: +5579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12806 .loc 1 5579 8 view .LVU4481 +5579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12807 .loc 1 5579 11 is_stmt 0 view .LVU4482 + 12808 0060 11F0800F tst r1, #128 + 12809 0064 02D0 beq .L796 +5579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12810 .loc 1 5579 61 discriminator 1 view .LVU4483 + 12811 0066 12F0400F tst r2, #64 + 12812 006a 0FD1 bne .L817 + 12813 .L796: +5632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12814 .loc 1 5632 8 is_stmt 1 view .LVU4484 +5632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12815 .loc 1 5632 11 is_stmt 0 view .LVU4485 + 12816 006c 11F0400F tst r1, #64 + 12817 0070 02D0 beq .L803 +5632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12818 .loc 1 5632 60 discriminator 1 view .LVU4486 + 12819 0072 12F0400F tst r2, #64 + 12820 0076 58D1 bne .L818 + 12821 .L803: +5684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 12822 .loc 1 5684 8 is_stmt 1 view .LVU4487 +5684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 12823 .loc 1 5684 11 is_stmt 0 view .LVU4488 + 12824 0078 11F0200F tst r1, #32 + 12825 007c DDD0 beq .L794 +5684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + ARM GAS /tmp/ccSHpINd.s page 433 + + + 12826 .loc 1 5684 63 discriminator 1 view .LVU4489 + 12827 007e 12F0200F tst r2, #32 + 12828 0082 DAD0 beq .L794 +5688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12829 .loc 1 5688 5 is_stmt 1 view .LVU4490 + 12830 0084 2046 mov r0, r4 + 12831 .LVL936: +5688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12832 .loc 1 5688 5 is_stmt 0 view .LVU4491 + 12833 0086 FFF7FEFF bl I2C_ITMasterCplt + 12834 .LVL937: +5688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12835 .loc 1 5688 5 view .LVU4492 + 12836 008a D6E7 b .L794 + 12837 .LVL938: + 12838 .L817: +5583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12839 .loc 1 5583 5 is_stmt 1 view .LVU4493 + 12840 008c 0121 movs r1, #1 + 12841 .LVL939: +5583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12842 .loc 1 5583 5 is_stmt 0 view .LVU4494 + 12843 008e 2046 mov r0, r4 + 12844 .LVL940: +5583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12845 .loc 1 5583 5 view .LVU4495 + 12846 0090 FFF7FEFF bl I2C_Disable_IRQ + 12847 .LVL941: +5586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12848 .loc 1 5586 5 is_stmt 1 view .LVU4496 + 12849 0094 1021 movs r1, #16 + 12850 0096 2046 mov r0, r4 + 12851 0098 FFF7FEFF bl I2C_Enable_IRQ + 12852 .LVL942: +5588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12853 .loc 1 5588 5 view .LVU4497 +5588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12854 .loc 1 5588 13 is_stmt 0 view .LVU4498 + 12855 009c 638D ldrh r3, [r4, #42] + 12856 009e 9BB2 uxth r3, r3 +5588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12857 .loc 1 5588 8 view .LVU4499 + 12858 00a0 002B cmp r3, #0 + 12859 00a2 3DD0 beq .L797 +5591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12860 .loc 1 5591 7 is_stmt 1 view .LVU4500 +5591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12861 .loc 1 5591 15 is_stmt 0 view .LVU4501 + 12862 00a4 638D ldrh r3, [r4, #42] + 12863 00a6 9BB2 uxth r3, r3 +5591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12864 .loc 1 5591 10 view .LVU4502 + 12865 00a8 FF2B cmp r3, #255 + 12866 00aa 25D9 bls .L798 +5594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12867 .loc 1 5594 9 is_stmt 1 view .LVU4503 +5594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 434 + + + 12868 .loc 1 5594 13 is_stmt 0 view .LVU4504 + 12869 00ac 2368 ldr r3, [r4] + 12870 00ae 9B69 ldr r3, [r3, #24] +5594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12871 .loc 1 5594 12 view .LVU4505 + 12872 00b0 13F4803F tst r3, #65536 + 12873 00b4 1DD0 beq .L799 +5596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12874 .loc 1 5596 11 is_stmt 1 view .LVU4506 +5596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12875 .loc 1 5596 26 is_stmt 0 view .LVU4507 + 12876 00b6 0123 movs r3, #1 + 12877 00b8 2385 strh r3, [r4, #40] @ movhi + 12878 .L800: +5602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 12879 .loc 1 5602 9 is_stmt 1 view .LVU4508 +5602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 12880 .loc 1 5602 48 is_stmt 0 view .LVU4509 + 12881 00ba E16C ldr r1, [r4, #76] +5602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 12882 .loc 1 5602 9 view .LVU4510 + 12883 00bc 0023 movs r3, #0 + 12884 00be 0093 str r3, [sp] + 12885 00c0 4FF08073 mov r3, #16777216 + 12886 00c4 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 12887 00c8 89B2 uxth r1, r1 + 12888 00ca 2046 mov r0, r4 + 12889 00cc FFF7FEFF bl I2C_TransferConfig + 12890 .LVL943: + 12891 .L801: +5613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12892 .loc 1 5613 7 is_stmt 1 view .LVU4511 +5613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12893 .loc 1 5613 11 is_stmt 0 view .LVU4512 + 12894 00d0 638D ldrh r3, [r4, #42] + 12895 00d2 9BB2 uxth r3, r3 +5613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12896 .loc 1 5613 30 view .LVU4513 + 12897 00d4 228D ldrh r2, [r4, #40] +5613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12898 .loc 1 5613 23 view .LVU4514 + 12899 00d6 9B1A subs r3, r3, r2 + 12900 00d8 9BB2 uxth r3, r3 + 12901 00da 6385 strh r3, [r4, #42] @ movhi +5616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12902 .loc 1 5616 7 is_stmt 1 view .LVU4515 +5616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12903 .loc 1 5616 15 is_stmt 0 view .LVU4516 + 12904 00dc 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 12905 00e0 DBB2 uxtb r3, r3 +5616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12906 .loc 1 5616 10 view .LVU4517 + 12907 00e2 222B cmp r3, #34 + 12908 00e4 16D0 beq .L819 +5622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12909 .loc 1 5622 9 is_stmt 1 view .LVU4518 +5622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + ARM GAS /tmp/ccSHpINd.s page 435 + + + 12910 .loc 1 5622 13 is_stmt 0 view .LVU4519 + 12911 00e6 2268 ldr r2, [r4] +5622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12912 .loc 1 5622 23 view .LVU4520 + 12913 00e8 1368 ldr r3, [r2] +5622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12914 .loc 1 5622 29 view .LVU4521 + 12915 00ea 43F48043 orr r3, r3, #16384 + 12916 00ee 1360 str r3, [r2] + 12917 00f0 A3E7 b .L794 + 12918 .L799: +5600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12919 .loc 1 5600 11 is_stmt 1 view .LVU4522 +5600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12920 .loc 1 5600 26 is_stmt 0 view .LVU4523 + 12921 00f2 FF23 movs r3, #255 + 12922 00f4 2385 strh r3, [r4, #40] @ movhi + 12923 00f6 E0E7 b .L800 + 12924 .L798: +5607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + 12925 .loc 1 5607 9 is_stmt 1 view .LVU4524 +5607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + 12926 .loc 1 5607 30 is_stmt 0 view .LVU4525 + 12927 00f8 628D ldrh r2, [r4, #42] + 12928 00fa 92B2 uxth r2, r2 +5607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + 12929 .loc 1 5607 24 view .LVU4526 + 12930 00fc 2285 strh r2, [r4, #40] @ movhi +5608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 12931 .loc 1 5608 9 is_stmt 1 view .LVU4527 +5608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 12932 .loc 1 5608 48 is_stmt 0 view .LVU4528 + 12933 00fe E16C ldr r1, [r4, #76] +5608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 12934 .loc 1 5608 9 view .LVU4529 + 12935 0100 0023 movs r3, #0 + 12936 0102 0093 str r3, [sp] + 12937 0104 4FF00073 mov r3, #33554432 + 12938 0108 D2B2 uxtb r2, r2 + 12939 010a 89B2 uxth r1, r1 + 12940 010c 2046 mov r0, r4 + 12941 010e FFF7FEFF bl I2C_TransferConfig + 12942 .LVL944: + 12943 0112 DDE7 b .L801 + 12944 .L819: +5618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12945 .loc 1 5618 9 is_stmt 1 view .LVU4530 +5618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12946 .loc 1 5618 13 is_stmt 0 view .LVU4531 + 12947 0114 2268 ldr r2, [r4] +5618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12948 .loc 1 5618 23 view .LVU4532 + 12949 0116 1368 ldr r3, [r2] +5618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12950 .loc 1 5618 29 view .LVU4533 + 12951 0118 43F40043 orr r3, r3, #32768 + 12952 011c 1360 str r3, [r2] + ARM GAS /tmp/ccSHpINd.s page 436 + + + 12953 011e 8CE7 b .L794 + 12954 .L797: +5629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 12955 .loc 1 5629 7 is_stmt 1 view .LVU4534 + 12956 0120 4021 movs r1, #64 + 12957 0122 2046 mov r0, r4 + 12958 0124 FFF7FEFF bl I2C_ITError + 12959 .LVL945: + 12960 0128 87E7 b .L794 + 12961 .LVL946: + 12962 .L818: +5636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12963 .loc 1 5636 5 view .LVU4535 + 12964 012a 0121 movs r1, #1 + 12965 .LVL947: +5636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12966 .loc 1 5636 5 is_stmt 0 view .LVU4536 + 12967 012c 2046 mov r0, r4 + 12968 .LVL948: +5636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12969 .loc 1 5636 5 view .LVU4537 + 12970 012e FFF7FEFF bl I2C_Disable_IRQ + 12971 .LVL949: +5639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12972 .loc 1 5639 5 is_stmt 1 view .LVU4538 + 12973 0132 1021 movs r1, #16 + 12974 0134 2046 mov r0, r4 + 12975 0136 FFF7FEFF bl I2C_Enable_IRQ + 12976 .LVL950: +5641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12977 .loc 1 5641 5 view .LVU4539 +5641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12978 .loc 1 5641 13 is_stmt 0 view .LVU4540 + 12979 013a 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 12980 013e DBB2 uxtb r3, r3 +5641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12981 .loc 1 5641 8 view .LVU4541 + 12982 0140 222B cmp r3, #34 + 12983 0142 26D0 beq .L811 +5548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 12984 .loc 1 5548 12 view .LVU4542 + 12985 0144 2048 ldr r0, .L821 + 12986 .L804: + 12987 .LVL951: +5646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12988 .loc 1 5646 5 is_stmt 1 view .LVU4543 +5646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12989 .loc 1 5646 13 is_stmt 0 view .LVU4544 + 12990 0146 638D ldrh r3, [r4, #42] + 12991 0148 9BB2 uxth r3, r3 +5646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12992 .loc 1 5646 8 view .LVU4545 + 12993 014a FF2B cmp r3, #255 + 12994 014c 26D9 bls .L805 +5649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12995 .loc 1 5649 7 is_stmt 1 view .LVU4546 +5649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 437 + + + 12996 .loc 1 5649 11 is_stmt 0 view .LVU4547 + 12997 014e 2368 ldr r3, [r4] + 12998 0150 9B69 ldr r3, [r3, #24] +5649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 12999 .loc 1 5649 10 view .LVU4548 + 13000 0152 13F4803F tst r3, #65536 + 13001 0156 1ED0 beq .L806 +5651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13002 .loc 1 5651 9 is_stmt 1 view .LVU4549 +5651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13003 .loc 1 5651 24 is_stmt 0 view .LVU4550 + 13004 0158 0123 movs r3, #1 + 13005 015a 2385 strh r3, [r4, #40] @ movhi + 13006 .L807: +5659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, direction); + 13007 .loc 1 5659 7 is_stmt 1 view .LVU4551 +5659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, direction); + 13008 .loc 1 5659 46 is_stmt 0 view .LVU4552 + 13009 015c E16C ldr r1, [r4, #76] +5659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, direction); + 13010 .loc 1 5659 7 view .LVU4553 + 13011 015e 0090 str r0, [sp] + 13012 0160 4FF08073 mov r3, #16777216 + 13013 0164 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 13014 0168 89B2 uxth r1, r1 + 13015 016a 2046 mov r0, r4 + 13016 .LVL952: +5659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, direction); + 13017 .loc 1 5659 7 view .LVU4554 + 13018 016c FFF7FEFF bl I2C_TransferConfig + 13019 .LVL953: + 13020 .L808: +5672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13021 .loc 1 5672 5 is_stmt 1 view .LVU4555 +5672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13022 .loc 1 5672 9 is_stmt 0 view .LVU4556 + 13023 0170 638D ldrh r3, [r4, #42] + 13024 0172 9BB2 uxth r3, r3 +5672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13025 .loc 1 5672 28 view .LVU4557 + 13026 0174 228D ldrh r2, [r4, #40] +5672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13027 .loc 1 5672 21 view .LVU4558 + 13028 0176 9B1A subs r3, r3, r2 + 13029 0178 9BB2 uxth r3, r3 + 13030 017a 6385 strh r3, [r4, #42] @ movhi +5675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13031 .loc 1 5675 5 is_stmt 1 view .LVU4559 +5675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13032 .loc 1 5675 13 is_stmt 0 view .LVU4560 + 13033 017c 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 13034 0180 DBB2 uxtb r3, r3 +5675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13035 .loc 1 5675 8 view .LVU4561 + 13036 0182 222B cmp r3, #34 + 13037 0184 17D0 beq .L820 +5681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + ARM GAS /tmp/ccSHpINd.s page 438 + + + 13038 .loc 1 5681 7 is_stmt 1 view .LVU4562 +5681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13039 .loc 1 5681 11 is_stmt 0 view .LVU4563 + 13040 0186 2268 ldr r2, [r4] +5681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13041 .loc 1 5681 21 view .LVU4564 + 13042 0188 1368 ldr r3, [r2] +5681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13043 .loc 1 5681 27 view .LVU4565 + 13044 018a 43F48043 orr r3, r3, #16384 + 13045 018e 1360 str r3, [r2] + 13046 0190 53E7 b .L794 + 13047 .LVL954: + 13048 .L811: +5643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13049 .loc 1 5643 17 view .LVU4566 + 13050 0192 0E48 ldr r0, .L821+4 + 13051 0194 D7E7 b .L804 + 13052 .LVL955: + 13053 .L806: +5655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13054 .loc 1 5655 9 is_stmt 1 view .LVU4567 +5655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13055 .loc 1 5655 24 is_stmt 0 view .LVU4568 + 13056 0196 FF23 movs r3, #255 + 13057 0198 2385 strh r3, [r4, #40] @ movhi + 13058 019a DFE7 b .L807 + 13059 .L805: +5664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13060 .loc 1 5664 7 is_stmt 1 view .LVU4569 +5664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13061 .loc 1 5664 28 is_stmt 0 view .LVU4570 + 13062 019c 628D ldrh r2, [r4, #42] + 13063 019e 92B2 uxth r2, r2 +5664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13064 .loc 1 5664 22 view .LVU4571 + 13065 01a0 2285 strh r2, [r4, #40] @ movhi +5667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, direction); + 13066 .loc 1 5667 7 is_stmt 1 view .LVU4572 +5667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, direction); + 13067 .loc 1 5667 46 is_stmt 0 view .LVU4573 + 13068 01a2 E16C ldr r1, [r4, #76] +5667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, direction); + 13069 .loc 1 5667 7 view .LVU4574 + 13070 01a4 0090 str r0, [sp] + 13071 01a6 4FF00073 mov r3, #33554432 + 13072 01aa D2B2 uxtb r2, r2 + 13073 01ac 89B2 uxth r1, r1 + 13074 01ae 2046 mov r0, r4 + 13075 .LVL956: +5667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, direction); + 13076 .loc 1 5667 7 view .LVU4575 + 13077 01b0 FFF7FEFF bl I2C_TransferConfig + 13078 .LVL957: +5667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, direction); + 13079 .loc 1 5667 7 view .LVU4576 + 13080 01b4 DCE7 b .L808 + ARM GAS /tmp/ccSHpINd.s page 439 + + + 13081 .L820: +5677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13082 .loc 1 5677 7 is_stmt 1 view .LVU4577 +5677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13083 .loc 1 5677 11 is_stmt 0 view .LVU4578 + 13084 01b6 2268 ldr r2, [r4] +5677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13085 .loc 1 5677 21 view .LVU4579 + 13086 01b8 1368 ldr r3, [r2] +5677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13087 .loc 1 5677 27 view .LVU4580 + 13088 01ba 43F40043 orr r3, r3, #32768 + 13089 01be 1360 str r3, [r2] + 13090 01c0 3BE7 b .L794 + 13091 .LVL958: + 13092 .L810: + 13093 .LCFI138: + 13094 .cfi_def_cfa_offset 0 + 13095 .cfi_restore 4 + 13096 .cfi_restore 14 +5551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13097 .loc 1 5551 3 discriminator 1 view .LVU4581 + 13098 01c2 0220 movs r0, #2 + 13099 .LVL959: +5699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13100 .loc 1 5699 1 view .LVU4582 + 13101 01c4 7047 bx lr + 13102 .L822: + 13103 01c6 00BF .align 2 + 13104 .L821: + 13105 01c8 00200080 .word -2147475456 + 13106 01cc 00240080 .word -2147474432 + 13107 .cfi_endproc + 13108 .LFE194: + 13110 .section .text.I2C_Slave_ISR_DMA,"ax",%progbits + 13111 .align 1 + 13112 .syntax unified + 13113 .thumb + 13114 .thumb_func + 13116 I2C_Slave_ISR_DMA: + 13117 .LVL960: + 13118 .LFB195: +5711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 13119 .loc 1 5711 1 is_stmt 1 view -0 + 13120 .cfi_startproc + 13121 @ args = 0, pretend = 0, frame = 0 + 13122 @ frame_needed = 0, uses_anonymous_args = 0 +5711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 13123 .loc 1 5711 1 is_stmt 0 view .LVU4584 + 13124 0000 70B5 push {r4, r5, r6, lr} + 13125 .LCFI139: + 13126 .cfi_def_cfa_offset 16 + 13127 .cfi_offset 4, -16 + 13128 .cfi_offset 5, -12 + 13129 .cfi_offset 6, -8 + 13130 .cfi_offset 14, -4 + 13131 0002 0446 mov r4, r0 + ARM GAS /tmp/ccSHpINd.s page 440 + + +5712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t treatdmanack = 0U; + 13132 .loc 1 5712 3 is_stmt 1 view .LVU4585 +5712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t treatdmanack = 0U; + 13133 .loc 1 5712 12 is_stmt 0 view .LVU4586 + 13134 0004 C06A ldr r0, [r0, #44] + 13135 .LVL961: +5713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate; + 13136 .loc 1 5713 3 is_stmt 1 view .LVU4587 +5714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13137 .loc 1 5714 3 view .LVU4588 +5717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13138 .loc 1 5717 3 view .LVU4589 +5717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13139 .loc 1 5717 3 view .LVU4590 + 13140 0006 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 13141 000a 012B cmp r3, #1 + 13142 000c 00F08880 beq .L840 +5717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13143 .loc 1 5717 3 discriminator 2 view .LVU4591 + 13144 0010 0123 movs r3, #1 + 13145 0012 84F84030 strb r3, [r4, #64] +5717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13146 .loc 1 5717 3 discriminator 2 view .LVU4592 +5720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 13147 .loc 1 5720 3 view .LVU4593 +5720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 13148 .loc 1 5720 6 is_stmt 0 view .LVU4594 + 13149 0016 11F0200F tst r1, #32 + 13150 001a 02D0 beq .L825 +5720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 13151 .loc 1 5720 58 discriminator 1 view .LVU4595 + 13152 001c 12F0200F tst r2, #32 + 13153 0020 19D1 bne .L845 + 13154 .L825: +5726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 13155 .loc 1 5726 8 is_stmt 1 view .LVU4596 +5726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 13156 .loc 1 5726 11 is_stmt 0 view .LVU4597 + 13157 0022 11F0100F tst r1, #16 + 13158 0026 6DD0 beq .L827 +5726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 13159 .loc 1 5726 60 discriminator 1 view .LVU4598 + 13160 0028 12F0100F tst r2, #16 + 13161 002c 6AD0 beq .L827 +5733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + 13162 .loc 1 5733 5 is_stmt 1 view .LVU4599 + 13163 002e C2F38036 ubfx r6, r2, #14, #1 +5733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + 13164 .loc 1 5733 8 is_stmt 0 view .LVU4600 + 13165 0032 12F4804F tst r2, #16384 + 13166 0036 02D1 bne .L828 +5733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + 13167 .loc 1 5733 68 discriminator 1 view .LVU4601 + 13168 0038 12F4004F tst r2, #32768 + 13169 003c 5ED0 beq .L829 + 13170 .L828: +5737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 441 + + + 13171 .loc 1 5737 7 is_stmt 1 view .LVU4602 +5737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13172 .loc 1 5737 15 is_stmt 0 view .LVU4603 + 13173 003e E36B ldr r3, [r4, #60] +5737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13174 .loc 1 5737 10 view .LVU4604 + 13175 0040 6BB1 cbz r3, .L841 +5739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13176 .loc 1 5739 9 is_stmt 1 view .LVU4605 + 13177 0042 C2F3C035 ubfx r5, r2, #15, #1 +5739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13178 .loc 1 5739 12 is_stmt 0 view .LVU4606 + 13179 0046 12F4004F tst r2, #32768 + 13180 004a 09D0 beq .L830 +5741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13181 .loc 1 5741 11 is_stmt 1 view .LVU4607 +5741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13182 .loc 1 5741 15 is_stmt 0 view .LVU4608 + 13183 004c 1B68 ldr r3, [r3] + 13184 004e 5B68 ldr r3, [r3, #4] +5741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13185 .loc 1 5741 14 view .LVU4609 + 13186 0050 33B3 cbz r3, .L842 +5713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate; + 13187 .loc 1 5713 12 view .LVU4610 + 13188 0052 0025 movs r5, #0 + 13189 0054 04E0 b .L830 + 13190 .L845: +5724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13191 .loc 1 5724 5 is_stmt 1 view .LVU4611 + 13192 0056 2046 mov r0, r4 + 13193 .LVL962: +5724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13194 .loc 1 5724 5 is_stmt 0 view .LVU4612 + 13195 0058 FFF7FEFF bl I2C_ITSlaveCplt + 13196 .LVL963: +5724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13197 .loc 1 5724 5 view .LVU4613 + 13198 005c 58E0 b .L826 + 13199 .LVL964: + 13200 .L841: +5713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate; + 13201 .loc 1 5713 12 view .LVU4614 + 13202 005e 0025 movs r5, #0 + 13203 .L830: + 13204 .LVL965: +5749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13205 .loc 1 5749 7 is_stmt 1 view .LVU4615 +5749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13206 .loc 1 5749 15 is_stmt 0 view .LVU4616 + 13207 0060 A36B ldr r3, [r4, #56] +5749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13208 .loc 1 5749 10 view .LVU4617 + 13209 0062 1BB1 cbz r3, .L831 +5751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13210 .loc 1 5751 9 is_stmt 1 view .LVU4618 +5751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 442 + + + 13211 .loc 1 5751 12 is_stmt 0 view .LVU4619 + 13212 0064 16B1 cbz r6, .L831 +5753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13213 .loc 1 5753 11 is_stmt 1 view .LVU4620 +5753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13214 .loc 1 5753 15 is_stmt 0 view .LVU4621 + 13215 0066 1B68 ldr r3, [r3] + 13216 0068 5B68 ldr r3, [r3, #4] +5753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13217 .loc 1 5753 14 view .LVU4622 + 13218 006a DBB1 cbz r3, .L832 + 13219 .L831: +5760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13220 .loc 1 5760 7 is_stmt 1 view .LVU4623 +5760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13221 .loc 1 5760 10 is_stmt 0 view .LVU4624 + 13222 006c D5B9 cbnz r5, .L832 +5791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13223 .loc 1 5791 9 is_stmt 1 view .LVU4625 + 13224 006e 2368 ldr r3, [r4] + 13225 0070 1022 movs r2, #16 + 13226 .LVL966: +5791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13227 .loc 1 5791 9 is_stmt 0 view .LVU4626 + 13228 0072 DA61 str r2, [r3, #28] +5794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13229 .loc 1 5794 9 is_stmt 1 view .LVU4627 +5794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13230 .loc 1 5794 13 is_stmt 0 view .LVU4628 + 13231 0074 636C ldr r3, [r4, #68] +5794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13232 .loc 1 5794 25 view .LVU4629 + 13233 0076 43F00403 orr r3, r3, #4 + 13234 007a 6364 str r3, [r4, #68] +5797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13235 .loc 1 5797 9 is_stmt 1 view .LVU4630 +5797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13236 .loc 1 5797 18 is_stmt 0 view .LVU4631 + 13237 007c 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 13238 0080 DBB2 uxtb r3, r3 + 13239 .LVL967: +5799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13240 .loc 1 5799 9 is_stmt 1 view .LVU4632 +5799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13241 .loc 1 5799 12 is_stmt 0 view .LVU4633 + 13242 0082 B0F1807F cmp r0, #16777216 + 13243 0086 18BF it ne + 13244 0088 0028 cmpne r0, #0 + 13245 008a 41D1 bne .L826 +5801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13246 .loc 1 5801 11 is_stmt 1 view .LVU4634 + 13247 008c 213B subs r3, r3, #33 + 13248 .LVL968: +5801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13249 .loc 1 5801 11 is_stmt 0 view .LVU4635 + 13250 008e 092B cmp r3, #9 + 13251 0090 2CD8 bhi .L836 + ARM GAS /tmp/ccSHpINd.s page 443 + + + 13252 0092 DFE803F0 tbb [pc, r3] + 13253 .L838: + 13254 0096 29 .byte (.L839-.L838)/2 + 13255 0097 30 .byte (.L837-.L838)/2 + 13256 0098 2B .byte (.L836-.L838)/2 + 13257 0099 2B .byte (.L836-.L838)/2 + 13258 009a 2B .byte (.L836-.L838)/2 + 13259 009b 2B .byte (.L836-.L838)/2 + 13260 009c 2B .byte (.L836-.L838)/2 + 13261 009d 2B .byte (.L836-.L838)/2 + 13262 009e 29 .byte (.L839-.L838)/2 + 13263 009f 30 .byte (.L837-.L838)/2 + 13264 .LVL969: + 13265 .p2align 1 + 13266 .L842: +5743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13267 .loc 1 5743 26 view .LVU4636 + 13268 00a0 0125 movs r5, #1 + 13269 00a2 DDE7 b .L830 + 13270 .LVL970: + 13271 .L832: +5762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 13272 .loc 1 5762 9 is_stmt 1 view .LVU4637 +5762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 13273 .loc 1 5762 18 is_stmt 0 view .LVU4638 + 13274 00a4 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 13275 00a8 DBB2 uxtb r3, r3 +5762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 13276 .loc 1 5762 12 view .LVU4639 + 13277 00aa 282B cmp r3, #40 + 13278 00ac 08D0 beq .L846 + 13279 .L834: +5769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13280 .loc 1 5769 14 is_stmt 1 view .LVU4640 +5769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13281 .loc 1 5769 23 is_stmt 0 view .LVU4641 + 13282 00ae 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 13283 00b2 DBB2 uxtb r3, r3 +5769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13284 .loc 1 5769 17 view .LVU4642 + 13285 00b4 292B cmp r3, #41 + 13286 00b6 0AD0 beq .L847 + 13287 .L835: +5784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13288 .loc 1 5784 11 is_stmt 1 view .LVU4643 + 13289 00b8 2368 ldr r3, [r4] + 13290 00ba 1022 movs r2, #16 + 13291 .LVL971: +5784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13292 .loc 1 5784 11 is_stmt 0 view .LVU4644 + 13293 00bc DA61 str r2, [r3, #28] + 13294 00be 27E0 b .L826 + 13295 .LVL972: + 13296 .L846: +5762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 13297 .loc 1 5762 51 discriminator 1 view .LVU4645 + 13298 00c0 B0F1007F cmp r0, #33554432 + ARM GAS /tmp/ccSHpINd.s page 444 + + + 13299 00c4 F3D1 bne .L834 +5767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13300 .loc 1 5767 11 is_stmt 1 view .LVU4646 + 13301 00c6 2046 mov r0, r4 + 13302 .LVL973: +5767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13303 .loc 1 5767 11 is_stmt 0 view .LVU4647 + 13304 00c8 FFF7FEFF bl I2C_ITListenCplt + 13305 .LVL974: +5767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13306 .loc 1 5767 11 view .LVU4648 + 13307 00cc 20E0 b .L826 + 13308 .LVL975: + 13309 .L847: +5769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13310 .loc 1 5769 64 discriminator 1 view .LVU4649 + 13311 00ce 10F5803F cmn r0, #65536 + 13312 00d2 F1D0 beq .L835 +5772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13313 .loc 1 5772 11 is_stmt 1 view .LVU4650 + 13314 00d4 2368 ldr r3, [r4] + 13315 00d6 1022 movs r2, #16 + 13316 .LVL976: +5772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13317 .loc 1 5772 11 is_stmt 0 view .LVU4651 + 13318 00d8 DA61 str r2, [r3, #28] +5775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13319 .loc 1 5775 11 is_stmt 1 view .LVU4652 + 13320 00da 2046 mov r0, r4 + 13321 .LVL977: +5775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13322 .loc 1 5775 11 is_stmt 0 view .LVU4653 + 13323 00dc FFF7FEFF bl I2C_Flush_TXDR + 13324 .LVL978: +5779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13325 .loc 1 5779 11 is_stmt 1 view .LVU4654 + 13326 00e0 2046 mov r0, r4 + 13327 00e2 FFF7FEFF bl I2C_ITSlaveSeqCplt + 13328 .LVL979: + 13329 00e6 13E0 b .L826 + 13330 .LVL980: + 13331 .L839: +5803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13332 .loc 1 5803 13 view .LVU4655 +5803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13333 .loc 1 5803 33 is_stmt 0 view .LVU4656 + 13334 00e8 2123 movs r3, #33 + 13335 .LVL981: +5803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13336 .loc 1 5803 33 view .LVU4657 + 13337 00ea 2363 str r3, [r4, #48] + 13338 .L836: +5812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13339 .loc 1 5812 11 is_stmt 1 view .LVU4658 +5815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13340 .loc 1 5815 11 view .LVU4659 +5815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + ARM GAS /tmp/ccSHpINd.s page 445 + + + 13341 .loc 1 5815 33 is_stmt 0 view .LVU4660 + 13342 00ec 616C ldr r1, [r4, #68] + 13343 .LVL982: +5815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13344 .loc 1 5815 11 view .LVU4661 + 13345 00ee 2046 mov r0, r4 + 13346 .LVL983: +5815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13347 .loc 1 5815 11 view .LVU4662 + 13348 00f0 FFF7FEFF bl I2C_ITError + 13349 .LVL984: + 13350 00f4 0CE0 b .L826 + 13351 .LVL985: + 13352 .L837: +5807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13353 .loc 1 5807 13 is_stmt 1 view .LVU4663 +5807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13354 .loc 1 5807 33 is_stmt 0 view .LVU4664 + 13355 00f6 2223 movs r3, #34 + 13356 .LVL986: +5807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13357 .loc 1 5807 33 view .LVU4665 + 13358 00f8 2363 str r3, [r4, #48] + 13359 00fa F7E7 b .L836 + 13360 .LVL987: + 13361 .L829: +5822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13362 .loc 1 5822 7 is_stmt 1 view .LVU4666 + 13363 00fc 2368 ldr r3, [r4] + 13364 00fe 1022 movs r2, #16 + 13365 .LVL988: +5822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13366 .loc 1 5822 7 is_stmt 0 view .LVU4667 + 13367 0100 DA61 str r2, [r3, #28] + 13368 0102 05E0 b .L826 + 13369 .LVL989: + 13370 .L827: +5825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 13371 .loc 1 5825 8 is_stmt 1 view .LVU4668 +5825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 13372 .loc 1 5825 11 is_stmt 0 view .LVU4669 + 13373 0104 11F0080F tst r1, #8 + 13374 0108 02D0 beq .L826 +5825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 13375 .loc 1 5825 62 discriminator 1 view .LVU4670 + 13376 010a 12F0080F tst r2, #8 + 13377 010e 03D1 bne .L848 + 13378 .LVL990: + 13379 .L826: +5833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13380 .loc 1 5833 3 is_stmt 1 view .LVU4671 +5836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13381 .loc 1 5836 3 view .LVU4672 +5836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13382 .loc 1 5836 3 view .LVU4673 + 13383 0110 0020 movs r0, #0 + 13384 0112 84F84000 strb r0, [r4, #64] + ARM GAS /tmp/ccSHpINd.s page 446 + + +5836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13385 .loc 1 5836 3 view .LVU4674 +5838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13386 .loc 1 5838 3 view .LVU4675 + 13387 .L824: +5839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13388 .loc 1 5839 1 is_stmt 0 view .LVU4676 + 13389 0116 70BD pop {r4, r5, r6, pc} + 13390 .LVL991: + 13391 .L848: +5828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13392 .loc 1 5828 5 is_stmt 1 view .LVU4677 + 13393 0118 2046 mov r0, r4 + 13394 .LVL992: +5828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13395 .loc 1 5828 5 is_stmt 0 view .LVU4678 + 13396 011a FFF7FEFF bl I2C_ITAddrCplt + 13397 .LVL993: +5828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13398 .loc 1 5828 5 view .LVU4679 + 13399 011e F7E7 b .L826 + 13400 .LVL994: + 13401 .L840: +5717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13402 .loc 1 5717 3 discriminator 1 view .LVU4680 + 13403 0120 0220 movs r0, #2 + 13404 .LVL995: +5717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13405 .loc 1 5717 3 discriminator 1 view .LVU4681 + 13406 0122 F8E7 b .L824 + 13407 .cfi_endproc + 13408 .LFE195: + 13410 .section .text.I2C_Master_ISR_DMA,"ax",%progbits + 13411 .align 1 + 13412 .syntax unified + 13413 .thumb + 13414 .thumb_func + 13416 I2C_Master_ISR_DMA: + 13417 .LVL996: + 13418 .LFB193: +5399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t devaddress; + 13419 .loc 1 5399 1 is_stmt 1 view -0 + 13420 .cfi_startproc + 13421 @ args = 0, pretend = 0, frame = 0 + 13422 @ frame_needed = 0, uses_anonymous_args = 0 +5400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t xfermode; + 13423 .loc 1 5400 3 view .LVU4683 +5401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13424 .loc 1 5401 3 view .LVU4684 +5404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13425 .loc 1 5404 3 view .LVU4685 +5404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13426 .loc 1 5404 3 view .LVU4686 + 13427 0000 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 13428 0004 012B cmp r3, #1 + 13429 0006 00F0A380 beq .L863 +5399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint16_t devaddress; + ARM GAS /tmp/ccSHpINd.s page 447 + + + 13430 .loc 1 5399 1 is_stmt 0 view .LVU4687 + 13431 000a 10B5 push {r4, lr} + 13432 .LCFI140: + 13433 .cfi_def_cfa_offset 8 + 13434 .cfi_offset 4, -8 + 13435 .cfi_offset 14, -4 + 13436 000c 82B0 sub sp, sp, #8 + 13437 .LCFI141: + 13438 .cfi_def_cfa_offset 16 + 13439 000e 0446 mov r4, r0 +5404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13440 .loc 1 5404 3 is_stmt 1 discriminator 2 view .LVU4688 + 13441 0010 0123 movs r3, #1 + 13442 0012 80F84030 strb r3, [r0, #64] +5404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13443 .loc 1 5404 3 discriminator 2 view .LVU4689 +5406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 13444 .loc 1 5406 3 view .LVU4690 +5406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 13445 .loc 1 5406 6 is_stmt 0 view .LVU4691 + 13446 0016 11F0100F tst r1, #16 + 13447 001a 02D0 beq .L851 +5406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 13448 .loc 1 5406 55 discriminator 1 view .LVU4692 + 13449 001c 12F0100F tst r2, #16 + 13450 0020 1FD1 bne .L869 + 13451 .L851: +5423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 13452 .loc 1 5423 8 is_stmt 1 view .LVU4693 +5423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 13453 .loc 1 5423 11 is_stmt 0 view .LVU4694 + 13454 0022 11F0800F tst r1, #128 + 13455 0026 69D0 beq .L853 +5423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 13456 .loc 1 5423 61 discriminator 1 view .LVU4695 + 13457 0028 12F0400F tst r2, #64 + 13458 002c 66D0 beq .L853 +5427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13459 .loc 1 5427 5 is_stmt 1 view .LVU4696 + 13460 002e 2268 ldr r2, [r4] + 13461 .LVL997: +5427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13462 .loc 1 5427 5 is_stmt 0 view .LVU4697 + 13463 0030 1368 ldr r3, [r2] + 13464 0032 23F04003 bic r3, r3, #64 + 13465 0036 1360 str r3, [r2] +5429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13466 .loc 1 5429 5 is_stmt 1 view .LVU4698 +5429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13467 .loc 1 5429 13 is_stmt 0 view .LVU4699 + 13468 0038 638D ldrh r3, [r4, #42] + 13469 003a 9BB2 uxth r3, r3 +5429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13470 .loc 1 5429 8 view .LVU4700 + 13471 003c 002B cmp r3, #0 + 13472 003e 4FD0 beq .L854 +5432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 448 + + + 13473 .loc 1 5432 7 is_stmt 1 view .LVU4701 +5432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13474 .loc 1 5432 35 is_stmt 0 view .LVU4702 + 13475 0040 2268 ldr r2, [r4] +5432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13476 .loc 1 5432 45 view .LVU4703 + 13477 0042 5168 ldr r1, [r2, #4] + 13478 .LVL998: +5432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13479 .loc 1 5432 18 view .LVU4704 + 13480 0044 C1F30901 ubfx r1, r1, #0, #10 + 13481 .LVL999: +5435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13482 .loc 1 5435 7 is_stmt 1 view .LVU4705 +5435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13483 .loc 1 5435 15 is_stmt 0 view .LVU4706 + 13484 0048 638D ldrh r3, [r4, #42] + 13485 004a 9BB2 uxth r3, r3 +5435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13486 .loc 1 5435 10 view .LVU4707 + 13487 004c FF2B cmp r3, #255 + 13488 004e 1FD9 bls .L855 +5438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13489 .loc 1 5438 9 is_stmt 1 view .LVU4708 +5438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13490 .loc 1 5438 13 is_stmt 0 view .LVU4709 + 13491 0050 9369 ldr r3, [r2, #24] +5438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13492 .loc 1 5438 12 view .LVU4710 + 13493 0052 13F4803F tst r3, #65536 + 13494 0056 16D0 beq .L856 +5440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13495 .loc 1 5440 11 is_stmt 1 view .LVU4711 +5440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13496 .loc 1 5440 26 is_stmt 0 view .LVU4712 + 13497 0058 0123 movs r3, #1 + 13498 005a 2385 strh r3, [r4, #40] @ movhi +5446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13499 .loc 1 5446 18 view .LVU4713 + 13500 005c 4FF08073 mov r3, #16777216 + 13501 0060 1DE0 b .L857 + 13502 .LVL1000: + 13503 .L869: +5410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13504 .loc 1 5410 5 is_stmt 1 view .LVU4714 + 13505 0062 0368 ldr r3, [r0] + 13506 0064 1022 movs r2, #16 + 13507 .LVL1001: +5410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13508 .loc 1 5410 5 is_stmt 0 view .LVU4715 + 13509 0066 DA61 str r2, [r3, #28] +5413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13510 .loc 1 5413 5 is_stmt 1 view .LVU4716 +5413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13511 .loc 1 5413 9 is_stmt 0 view .LVU4717 + 13512 0068 436C ldr r3, [r0, #68] +5413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 449 + + + 13513 .loc 1 5413 21 view .LVU4718 + 13514 006a 43F00403 orr r3, r3, #4 + 13515 006e 4364 str r3, [r0, #68] +5418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13516 .loc 1 5418 5 is_stmt 1 view .LVU4719 + 13517 0070 2021 movs r1, #32 + 13518 .LVL1002: +5418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13519 .loc 1 5418 5 is_stmt 0 view .LVU4720 + 13520 0072 FFF7FEFF bl I2C_Enable_IRQ + 13521 .LVL1003: +5421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13522 .loc 1 5421 5 is_stmt 1 view .LVU4721 + 13523 0076 2046 mov r0, r4 + 13524 0078 FFF7FEFF bl I2C_Flush_TXDR + 13525 .LVL1004: + 13526 .L852: +5529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13527 .loc 1 5529 3 view .LVU4722 +5532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13528 .loc 1 5532 3 view .LVU4723 +5532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13529 .loc 1 5532 3 view .LVU4724 + 13530 007c 0020 movs r0, #0 + 13531 007e 84F84000 strb r0, [r4, #64] +5532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13532 .loc 1 5532 3 view .LVU4725 +5534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13533 .loc 1 5534 3 view .LVU4726 +5535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13534 .loc 1 5535 1 is_stmt 0 view .LVU4727 + 13535 0082 02B0 add sp, sp, #8 + 13536 .LCFI142: + 13537 .cfi_remember_state + 13538 .cfi_def_cfa_offset 8 + 13539 @ sp needed + 13540 0084 10BD pop {r4, pc} + 13541 .LVL1005: + 13542 .L856: + 13543 .LCFI143: + 13544 .cfi_restore_state +5444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13545 .loc 1 5444 11 is_stmt 1 view .LVU4728 +5444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13546 .loc 1 5444 26 is_stmt 0 view .LVU4729 + 13547 0086 FF23 movs r3, #255 + 13548 0088 2385 strh r3, [r4, #40] @ movhi +5446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13549 .loc 1 5446 18 view .LVU4730 + 13550 008a 4FF08073 mov r3, #16777216 + 13551 008e 06E0 b .L857 + 13552 .L855: +5450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 13553 .loc 1 5450 9 is_stmt 1 view .LVU4731 +5450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 13554 .loc 1 5450 30 is_stmt 0 view .LVU4732 + 13555 0090 638D ldrh r3, [r4, #42] + ARM GAS /tmp/ccSHpINd.s page 450 + + +5450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 13556 .loc 1 5450 24 view .LVU4733 + 13557 0092 2385 strh r3, [r4, #40] @ movhi +5451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13558 .loc 1 5451 9 is_stmt 1 view .LVU4734 +5451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13559 .loc 1 5451 17 is_stmt 0 view .LVU4735 + 13560 0094 E36A ldr r3, [r4, #44] +5451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13561 .loc 1 5451 12 view .LVU4736 + 13562 0096 13F5803F cmn r3, #65536 + 13563 009a 18D0 beq .L864 +5453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13564 .loc 1 5453 11 is_stmt 1 view .LVU4737 +5453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13565 .loc 1 5453 20 is_stmt 0 view .LVU4738 + 13566 009c E36A ldr r3, [r4, #44] + 13567 .LVL1006: + 13568 .L857: +5462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13569 .loc 1 5462 7 is_stmt 1 view .LVU4739 + 13570 009e 0022 movs r2, #0 + 13571 00a0 0092 str r2, [sp] + 13572 00a2 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 13573 00a6 2046 mov r0, r4 + 13574 .LVL1007: +5462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13575 .loc 1 5462 7 is_stmt 0 view .LVU4740 + 13576 00a8 FFF7FEFF bl I2C_TransferConfig + 13577 .LVL1008: +5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13578 .loc 1 5465 7 is_stmt 1 view .LVU4741 +5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13579 .loc 1 5465 11 is_stmt 0 view .LVU4742 + 13580 00ac 638D ldrh r3, [r4, #42] + 13581 00ae 9BB2 uxth r3, r3 +5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13582 .loc 1 5465 30 view .LVU4743 + 13583 00b0 228D ldrh r2, [r4, #40] +5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13584 .loc 1 5465 23 view .LVU4744 + 13585 00b2 9B1A subs r3, r3, r2 + 13586 00b4 9BB2 uxth r3, r3 + 13587 00b6 6385 strh r3, [r4, #42] @ movhi +5468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13588 .loc 1 5468 7 is_stmt 1 view .LVU4745 +5468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13589 .loc 1 5468 15 is_stmt 0 view .LVU4746 + 13590 00b8 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 13591 00bc DBB2 uxtb r3, r3 +5468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13592 .loc 1 5468 10 view .LVU4747 + 13593 00be 222B cmp r3, #34 + 13594 00c0 08D0 beq .L870 +5474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13595 .loc 1 5474 9 is_stmt 1 view .LVU4748 +5474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + ARM GAS /tmp/ccSHpINd.s page 451 + + + 13596 .loc 1 5474 13 is_stmt 0 view .LVU4749 + 13597 00c2 2268 ldr r2, [r4] +5474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13598 .loc 1 5474 23 view .LVU4750 + 13599 00c4 1368 ldr r3, [r2] +5474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13600 .loc 1 5474 29 view .LVU4751 + 13601 00c6 43F48043 orr r3, r3, #16384 + 13602 00ca 1360 str r3, [r2] + 13603 00cc D6E7 b .L852 + 13604 .LVL1009: + 13605 .L864: +5457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13606 .loc 1 5457 20 view .LVU4752 + 13607 00ce 4FF00073 mov r3, #33554432 + 13608 00d2 E4E7 b .L857 + 13609 .LVL1010: + 13610 .L870: +5470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13611 .loc 1 5470 9 is_stmt 1 view .LVU4753 +5470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13612 .loc 1 5470 13 is_stmt 0 view .LVU4754 + 13613 00d4 2268 ldr r2, [r4] +5470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13614 .loc 1 5470 23 view .LVU4755 + 13615 00d6 1368 ldr r3, [r2] +5470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13616 .loc 1 5470 29 view .LVU4756 + 13617 00d8 43F40043 orr r3, r3, #32768 + 13618 00dc 1360 str r3, [r2] + 13619 00de CDE7 b .L852 + 13620 .LVL1011: + 13621 .L854: +5480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13622 .loc 1 5480 7 is_stmt 1 view .LVU4757 +5480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13623 .loc 1 5480 11 is_stmt 0 view .LVU4758 + 13624 00e0 2368 ldr r3, [r4] + 13625 00e2 5B68 ldr r3, [r3, #4] +5480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13626 .loc 1 5480 10 view .LVU4759 + 13627 00e4 13F0007F tst r3, #33554432 + 13628 00e8 03D1 bne .L859 +5483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13629 .loc 1 5483 9 is_stmt 1 view .LVU4760 + 13630 00ea 2046 mov r0, r4 + 13631 .LVL1012: +5483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13632 .loc 1 5483 9 is_stmt 0 view .LVU4761 + 13633 00ec FFF7FEFF bl I2C_ITMasterSeqCplt + 13634 .LVL1013: +5483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13635 .loc 1 5483 9 view .LVU4762 + 13636 00f0 C4E7 b .L852 + 13637 .LVL1014: + 13638 .L859: +5489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + ARM GAS /tmp/ccSHpINd.s page 452 + + + 13639 .loc 1 5489 9 is_stmt 1 view .LVU4763 + 13640 00f2 4021 movs r1, #64 + 13641 .LVL1015: +5489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13642 .loc 1 5489 9 is_stmt 0 view .LVU4764 + 13643 00f4 2046 mov r0, r4 + 13644 .LVL1016: +5489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13645 .loc 1 5489 9 view .LVU4765 + 13646 00f6 FFF7FEFF bl I2C_ITError + 13647 .LVL1017: + 13648 00fa BFE7 b .L852 + 13649 .LVL1018: + 13650 .L853: +5493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 13651 .loc 1 5493 8 is_stmt 1 view .LVU4766 +5493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 13652 .loc 1 5493 11 is_stmt 0 view .LVU4767 + 13653 00fc 11F0400F tst r1, #64 + 13654 0100 1CD0 beq .L860 +5493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 13655 .loc 1 5493 60 discriminator 1 view .LVU4768 + 13656 0102 12F0400F tst r2, #64 + 13657 0106 19D0 beq .L860 +5496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13658 .loc 1 5496 5 is_stmt 1 view .LVU4769 +5496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13659 .loc 1 5496 13 is_stmt 0 view .LVU4770 + 13660 0108 638D ldrh r3, [r4, #42] + 13661 010a 9BB2 uxth r3, r3 +5496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13662 .loc 1 5496 8 view .LVU4771 + 13663 010c 8BB9 cbnz r3, .L861 +5498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13664 .loc 1 5498 7 is_stmt 1 view .LVU4772 +5498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13665 .loc 1 5498 11 is_stmt 0 view .LVU4773 + 13666 010e 2368 ldr r3, [r4] + 13667 0110 5A68 ldr r2, [r3, #4] + 13668 .LVL1019: +5498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13669 .loc 1 5498 10 view .LVU4774 + 13670 0112 12F0007F tst r2, #33554432 + 13671 0116 B1D1 bne .L852 +5501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13672 .loc 1 5501 9 is_stmt 1 view .LVU4775 +5501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13673 .loc 1 5501 17 is_stmt 0 view .LVU4776 + 13674 0118 E26A ldr r2, [r4, #44] +5501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13675 .loc 1 5501 12 view .LVU4777 + 13676 011a 12F5803F cmn r2, #65536 + 13677 011e 04D1 bne .L862 +5504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13678 .loc 1 5504 11 is_stmt 1 view .LVU4778 +5504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13679 .loc 1 5504 25 is_stmt 0 view .LVU4779 + ARM GAS /tmp/ccSHpINd.s page 453 + + + 13680 0120 5A68 ldr r2, [r3, #4] +5504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13681 .loc 1 5504 31 view .LVU4780 + 13682 0122 42F48042 orr r2, r2, #16384 + 13683 0126 5A60 str r2, [r3, #4] + 13684 0128 A8E7 b .L852 + 13685 .L862: +5509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13686 .loc 1 5509 11 is_stmt 1 view .LVU4781 + 13687 012a 2046 mov r0, r4 + 13688 .LVL1020: +5509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13689 .loc 1 5509 11 is_stmt 0 view .LVU4782 + 13690 012c FFF7FEFF bl I2C_ITMasterSeqCplt + 13691 .LVL1021: +5509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13692 .loc 1 5509 11 view .LVU4783 + 13693 0130 A4E7 b .L852 + 13694 .LVL1022: + 13695 .L861: +5517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13696 .loc 1 5517 7 is_stmt 1 view .LVU4784 + 13697 0132 4021 movs r1, #64 + 13698 .LVL1023: +5517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13699 .loc 1 5517 7 is_stmt 0 view .LVU4785 + 13700 0134 2046 mov r0, r4 + 13701 .LVL1024: +5517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13702 .loc 1 5517 7 view .LVU4786 + 13703 0136 FFF7FEFF bl I2C_ITError + 13704 .LVL1025: +5517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13705 .loc 1 5517 7 view .LVU4787 + 13706 013a 9FE7 b .L852 + 13707 .LVL1026: + 13708 .L860: +5520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 13709 .loc 1 5520 8 is_stmt 1 view .LVU4788 +5520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 13710 .loc 1 5520 11 is_stmt 0 view .LVU4789 + 13711 013c 11F0200F tst r1, #32 + 13712 0140 9CD0 beq .L852 +5520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 13713 .loc 1 5520 63 discriminator 1 view .LVU4790 + 13714 0142 12F0200F tst r2, #32 + 13715 0146 99D0 beq .L852 +5524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13716 .loc 1 5524 5 is_stmt 1 view .LVU4791 + 13717 0148 2046 mov r0, r4 + 13718 .LVL1027: +5524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13719 .loc 1 5524 5 is_stmt 0 view .LVU4792 + 13720 014a FFF7FEFF bl I2C_ITMasterCplt + 13721 .LVL1028: +5524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13722 .loc 1 5524 5 view .LVU4793 + ARM GAS /tmp/ccSHpINd.s page 454 + + + 13723 014e 95E7 b .L852 + 13724 .LVL1029: + 13725 .L863: + 13726 .LCFI144: + 13727 .cfi_def_cfa_offset 0 + 13728 .cfi_restore 4 + 13729 .cfi_restore 14 +5404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13730 .loc 1 5404 3 discriminator 1 view .LVU4794 + 13731 0150 0220 movs r0, #2 + 13732 .LVL1030: +5535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13733 .loc 1 5535 1 view .LVU4795 + 13734 0152 7047 bx lr + 13735 .cfi_endproc + 13736 .LFE193: + 13738 .section .text.I2C_DMAError,"ax",%progbits + 13739 .align 1 + 13740 .syntax unified + 13741 .thumb + 13742 .thumb_func + 13744 I2C_DMAError: + 13745 .LVL1031: + 13746 .LFB211: +6948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t treatdmaerror = 0U; + 13747 .loc 1 6948 1 is_stmt 1 view -0 + 13748 .cfi_startproc + 13749 @ args = 0, pretend = 0, frame = 0 + 13750 @ frame_needed = 0, uses_anonymous_args = 0 +6948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t treatdmaerror = 0U; + 13751 .loc 1 6948 1 is_stmt 0 view .LVU4797 + 13752 0000 38B5 push {r3, r4, r5, lr} + 13753 .LCFI145: + 13754 .cfi_def_cfa_offset 16 + 13755 .cfi_offset 3, -16 + 13756 .cfi_offset 4, -12 + 13757 .cfi_offset 5, -8 + 13758 .cfi_offset 14, -4 +6949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 13759 .loc 1 6949 3 is_stmt 1 view .LVU4798 + 13760 .LVL1032: +6951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13761 .loc 1 6951 3 view .LVU4799 +6951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13762 .loc 1 6951 22 is_stmt 0 view .LVU4800 + 13763 0002 846B ldr r4, [r0, #56] + 13764 .LVL1033: +6953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13765 .loc 1 6953 3 is_stmt 1 view .LVU4801 +6953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13766 .loc 1 6953 11 is_stmt 0 view .LVU4802 + 13767 0004 A36B ldr r3, [r4, #56] +6953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13768 .loc 1 6953 6 view .LVU4803 + 13769 0006 7BB1 cbz r3, .L875 +6955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13770 .loc 1 6955 5 is_stmt 1 view .LVU4804 + ARM GAS /tmp/ccSHpINd.s page 455 + + +6955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13771 .loc 1 6955 9 is_stmt 0 view .LVU4805 + 13772 0008 1B68 ldr r3, [r3] + 13773 000a 5B68 ldr r3, [r3, #4] +6955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13774 .loc 1 6955 8 view .LVU4806 + 13775 000c 73B1 cbz r3, .L876 +6949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 13776 .loc 1 6949 12 view .LVU4807 + 13777 000e 0025 movs r5, #0 + 13778 .L872: + 13779 .LVL1034: +6961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13780 .loc 1 6961 3 is_stmt 1 view .LVU4808 +6961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13781 .loc 1 6961 11 is_stmt 0 view .LVU4809 + 13782 0010 E36B ldr r3, [r4, #60] +6961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13783 .loc 1 6961 6 view .LVU4810 + 13784 0012 1BB1 cbz r3, .L873 +6963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13785 .loc 1 6963 5 is_stmt 1 view .LVU4811 +6963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13786 .loc 1 6963 9 is_stmt 0 view .LVU4812 + 13787 0014 1B68 ldr r3, [r3] + 13788 0016 5B68 ldr r3, [r3, #4] +6963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13789 .loc 1 6963 8 view .LVU4813 + 13790 0018 03B9 cbnz r3, .L873 +6965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13791 .loc 1 6965 21 view .LVU4814 + 13792 001a 0125 movs r5, #1 + 13793 .LVL1035: + 13794 .L873: +6970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13795 .loc 1 6970 3 is_stmt 1 view .LVU4815 +6970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13796 .loc 1 6970 10 is_stmt 0 view .LVU4816 + 13797 001c FFF7FEFF bl HAL_DMA_GetError + 13798 .LVL1036: +6970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13799 .loc 1 6970 6 discriminator 1 view .LVU4817 + 13800 0020 0228 cmp r0, #2 + 13801 0022 00D0 beq .L871 +6970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13802 .loc 1 6970 55 discriminator 1 view .LVU4818 + 13803 0024 25B9 cbnz r5, .L879 + 13804 .L871: +6978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13805 .loc 1 6978 1 view .LVU4819 + 13806 0026 38BD pop {r3, r4, r5, pc} + 13807 .LVL1037: + 13808 .L875: +6949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 13809 .loc 1 6949 12 view .LVU4820 + 13810 0028 0025 movs r5, #0 + 13811 002a F1E7 b .L872 + ARM GAS /tmp/ccSHpINd.s page 456 + + + 13812 .L876: +6957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13813 .loc 1 6957 21 view .LVU4821 + 13814 002c 0125 movs r5, #1 + 13815 002e EFE7 b .L872 + 13816 .LVL1038: + 13817 .L879: +6973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13818 .loc 1 6973 5 is_stmt 1 view .LVU4822 +6973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13819 .loc 1 6973 9 is_stmt 0 view .LVU4823 + 13820 0030 2268 ldr r2, [r4] +6973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13821 .loc 1 6973 19 view .LVU4824 + 13822 0032 5368 ldr r3, [r2, #4] +6973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13823 .loc 1 6973 25 view .LVU4825 + 13824 0034 43F40043 orr r3, r3, #32768 + 13825 0038 5360 str r3, [r2, #4] +6976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13826 .loc 1 6976 5 is_stmt 1 view .LVU4826 + 13827 003a 1021 movs r1, #16 + 13828 003c 2046 mov r0, r4 + 13829 003e FFF7FEFF bl I2C_ITError + 13830 .LVL1039: +6978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13831 .loc 1 6978 1 is_stmt 0 view .LVU4827 + 13832 0042 F0E7 b .L871 + 13833 .cfi_endproc + 13834 .LFE211: + 13836 .section .text.I2C_DMAMasterTransmitCplt,"ax",%progbits + 13837 .align 1 + 13838 .syntax unified + 13839 .thumb + 13840 .thumb_func + 13842 I2C_DMAMasterTransmitCplt: + 13843 .LVL1040: + 13844 .LFB207: +6780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 13845 .loc 1 6780 1 is_stmt 1 view -0 + 13846 .cfi_startproc + 13847 @ args = 0, pretend = 0, frame = 0 + 13848 @ frame_needed = 0, uses_anonymous_args = 0 +6780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 13849 .loc 1 6780 1 is_stmt 0 view .LVU4829 + 13850 0000 10B5 push {r4, lr} + 13851 .LCFI146: + 13852 .cfi_def_cfa_offset 8 + 13853 .cfi_offset 4, -8 + 13854 .cfi_offset 14, -4 +6782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13855 .loc 1 6782 3 is_stmt 1 view .LVU4830 +6782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13856 .loc 1 6782 22 is_stmt 0 view .LVU4831 + 13857 0002 846B ldr r4, [r0, #56] + 13858 .LVL1041: +6785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + ARM GAS /tmp/ccSHpINd.s page 457 + + + 13859 .loc 1 6785 3 is_stmt 1 view .LVU4832 +6785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13860 .loc 1 6785 7 is_stmt 0 view .LVU4833 + 13861 0004 2268 ldr r2, [r4] +6785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13862 .loc 1 6785 17 view .LVU4834 + 13863 0006 1368 ldr r3, [r2] +6785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13864 .loc 1 6785 23 view .LVU4835 + 13865 0008 23F48043 bic r3, r3, #16384 + 13866 000c 1360 str r3, [r2] +6788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13867 .loc 1 6788 3 is_stmt 1 view .LVU4836 +6788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13868 .loc 1 6788 11 is_stmt 0 view .LVU4837 + 13869 000e 638D ldrh r3, [r4, #42] + 13870 0010 9BB2 uxth r3, r3 +6788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13871 .loc 1 6788 6 view .LVU4838 + 13872 0012 ABB1 cbz r3, .L887 +6797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13873 .loc 1 6797 5 is_stmt 1 view .LVU4839 +6797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13874 .loc 1 6797 9 is_stmt 0 view .LVU4840 + 13875 0014 616A ldr r1, [r4, #36] +6797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13876 .loc 1 6797 27 view .LVU4841 + 13877 0016 238D ldrh r3, [r4, #40] +6797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13878 .loc 1 6797 20 view .LVU4842 + 13879 0018 1944 add r1, r1, r3 + 13880 001a 6162 str r1, [r4, #36] +6800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13881 .loc 1 6800 5 is_stmt 1 view .LVU4843 +6800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13882 .loc 1 6800 13 is_stmt 0 view .LVU4844 + 13883 001c 638D ldrh r3, [r4, #42] + 13884 001e 9BB2 uxth r3, r3 +6800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13885 .loc 1 6800 8 view .LVU4845 + 13886 0020 FF2B cmp r3, #255 + 13887 0022 12D9 bls .L883 +6802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13888 .loc 1 6802 7 is_stmt 1 view .LVU4846 +6802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13889 .loc 1 6802 22 is_stmt 0 view .LVU4847 + 13890 0024 FF23 movs r3, #255 + 13891 0026 2385 strh r3, [r4, #40] @ movhi + 13892 .L884: +6810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13893 .loc 1 6810 5 is_stmt 1 view .LVU4848 +6810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13894 .loc 1 6810 81 is_stmt 0 view .LVU4849 + 13895 0028 2268 ldr r2, [r4] +6810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13896 .loc 1 6810 9 view .LVU4850 + 13897 002a 238D ldrh r3, [r4, #40] + ARM GAS /tmp/ccSHpINd.s page 458 + + + 13898 002c 2832 adds r2, r2, #40 + 13899 002e A06B ldr r0, [r4, #56] + 13900 .LVL1042: +6810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13901 .loc 1 6810 9 view .LVU4851 + 13902 0030 FFF7FEFF bl HAL_DMA_Start_IT + 13903 .LVL1043: +6810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13904 .loc 1 6810 8 discriminator 1 view .LVU4852 + 13905 0034 60B1 cbz r0, .L885 +6814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13906 .loc 1 6814 7 is_stmt 1 view .LVU4853 + 13907 0036 1021 movs r1, #16 + 13908 0038 2046 mov r0, r4 + 13909 003a FFF7FEFF bl I2C_ITError + 13910 .LVL1044: + 13911 .L880: +6822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13912 .loc 1 6822 1 is_stmt 0 view .LVU4854 + 13913 003e 10BD pop {r4, pc} + 13914 .LVL1045: + 13915 .L887: +6791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13916 .loc 1 6791 5 is_stmt 1 view .LVU4855 + 13917 0040 2021 movs r1, #32 + 13918 0042 2046 mov r0, r4 + 13919 .LVL1046: +6791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13920 .loc 1 6791 5 is_stmt 0 view .LVU4856 + 13921 0044 FFF7FEFF bl I2C_Enable_IRQ + 13922 .LVL1047: + 13923 0048 F9E7 b .L880 + 13924 .LVL1048: + 13925 .L883: +6806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13926 .loc 1 6806 7 is_stmt 1 view .LVU4857 +6806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13927 .loc 1 6806 28 is_stmt 0 view .LVU4858 + 13928 004a 638D ldrh r3, [r4, #42] +6806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13929 .loc 1 6806 22 view .LVU4859 + 13930 004c 2385 strh r3, [r4, #40] @ movhi + 13931 004e EBE7 b .L884 + 13932 .LVL1049: + 13933 .L885: +6819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 13934 .loc 1 6819 7 is_stmt 1 view .LVU4860 + 13935 0050 4021 movs r1, #64 + 13936 0052 2046 mov r0, r4 + 13937 0054 FFF7FEFF bl I2C_Enable_IRQ + 13938 .LVL1050: +6822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13939 .loc 1 6822 1 is_stmt 0 view .LVU4861 + 13940 0058 F1E7 b .L880 + 13941 .cfi_endproc + 13942 .LFE207: + 13944 .section .text.I2C_DMAMasterReceiveCplt,"ax",%progbits + ARM GAS /tmp/ccSHpINd.s page 459 + + + 13945 .align 1 + 13946 .syntax unified + 13947 .thumb + 13948 .thumb_func + 13950 I2C_DMAMasterReceiveCplt: + 13951 .LVL1051: + 13952 .LFB209: +6860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 13953 .loc 1 6860 1 is_stmt 1 view -0 + 13954 .cfi_startproc + 13955 @ args = 0, pretend = 0, frame = 0 + 13956 @ frame_needed = 0, uses_anonymous_args = 0 +6860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 13957 .loc 1 6860 1 is_stmt 0 view .LVU4863 + 13958 0000 10B5 push {r4, lr} + 13959 .LCFI147: + 13960 .cfi_def_cfa_offset 8 + 13961 .cfi_offset 4, -8 + 13962 .cfi_offset 14, -4 +6862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13963 .loc 1 6862 3 is_stmt 1 view .LVU4864 +6862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13964 .loc 1 6862 22 is_stmt 0 view .LVU4865 + 13965 0002 846B ldr r4, [r0, #56] + 13966 .LVL1052: +6865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13967 .loc 1 6865 3 is_stmt 1 view .LVU4866 +6865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13968 .loc 1 6865 7 is_stmt 0 view .LVU4867 + 13969 0004 2268 ldr r2, [r4] +6865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13970 .loc 1 6865 17 view .LVU4868 + 13971 0006 1368 ldr r3, [r2] +6865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13972 .loc 1 6865 23 view .LVU4869 + 13973 0008 23F40043 bic r3, r3, #32768 + 13974 000c 1360 str r3, [r2] +6868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13975 .loc 1 6868 3 is_stmt 1 view .LVU4870 +6868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13976 .loc 1 6868 11 is_stmt 0 view .LVU4871 + 13977 000e 638D ldrh r3, [r4, #42] + 13978 0010 9BB2 uxth r3, r3 +6868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13979 .loc 1 6868 6 view .LVU4872 + 13980 0012 7BB1 cbz r3, .L896 +6877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13981 .loc 1 6877 5 is_stmt 1 view .LVU4873 +6877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13982 .loc 1 6877 9 is_stmt 0 view .LVU4874 + 13983 0014 626A ldr r2, [r4, #36] +6877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13984 .loc 1 6877 27 view .LVU4875 + 13985 0016 238D ldrh r3, [r4, #40] +6877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 13986 .loc 1 6877 20 view .LVU4876 + 13987 0018 1A44 add r2, r2, r3 + ARM GAS /tmp/ccSHpINd.s page 460 + + + 13988 001a 6262 str r2, [r4, #36] +6880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13989 .loc 1 6880 5 is_stmt 1 view .LVU4877 +6880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13990 .loc 1 6880 13 is_stmt 0 view .LVU4878 + 13991 001c 638D ldrh r3, [r4, #42] + 13992 001e 9BB2 uxth r3, r3 +6880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13993 .loc 1 6880 8 view .LVU4879 + 13994 0020 FF2B cmp r3, #255 + 13995 0022 0FD9 bls .L891 +6883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13996 .loc 1 6883 7 is_stmt 1 view .LVU4880 +6883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 13997 .loc 1 6883 11 is_stmt 0 view .LVU4881 + 13998 0024 2368 ldr r3, [r4] + 13999 0026 9B69 ldr r3, [r3, #24] +6883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14000 .loc 1 6883 10 view .LVU4882 + 14001 0028 13F4803F tst r3, #65536 + 14002 002c 07D0 beq .L892 +6885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14003 .loc 1 6885 9 is_stmt 1 view .LVU4883 +6885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14004 .loc 1 6885 24 is_stmt 0 view .LVU4884 + 14005 002e 0123 movs r3, #1 + 14006 0030 2385 strh r3, [r4, #40] @ movhi + 14007 0032 09E0 b .L893 + 14008 .L896: +6871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14009 .loc 1 6871 5 is_stmt 1 view .LVU4885 + 14010 0034 2021 movs r1, #32 + 14011 0036 2046 mov r0, r4 + 14012 .LVL1053: +6871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14013 .loc 1 6871 5 is_stmt 0 view .LVU4886 + 14014 0038 FFF7FEFF bl I2C_Enable_IRQ + 14015 .LVL1054: + 14016 003c 0FE0 b .L888 + 14017 .LVL1055: + 14018 .L892: +6889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14019 .loc 1 6889 9 is_stmt 1 view .LVU4887 +6889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14020 .loc 1 6889 24 is_stmt 0 view .LVU4888 + 14021 003e FF23 movs r3, #255 + 14022 0040 2385 strh r3, [r4, #40] @ movhi + 14023 0042 01E0 b .L893 + 14024 .L891: +6894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14025 .loc 1 6894 7 is_stmt 1 view .LVU4889 +6894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14026 .loc 1 6894 28 is_stmt 0 view .LVU4890 + 14027 0044 638D ldrh r3, [r4, #42] +6894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14028 .loc 1 6894 22 view .LVU4891 + 14029 0046 2385 strh r3, [r4, #40] @ movhi + ARM GAS /tmp/ccSHpINd.s page 461 + + + 14030 .L893: +6898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 14031 .loc 1 6898 5 is_stmt 1 view .LVU4892 +6898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 14032 .loc 1 6898 55 is_stmt 0 view .LVU4893 + 14033 0048 2168 ldr r1, [r4] +6898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 14034 .loc 1 6898 9 view .LVU4894 + 14035 004a 238D ldrh r3, [r4, #40] + 14036 004c 2431 adds r1, r1, #36 + 14037 004e E06B ldr r0, [r4, #60] + 14038 .LVL1056: +6898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 14039 .loc 1 6898 9 view .LVU4895 + 14040 0050 FFF7FEFF bl HAL_DMA_Start_IT + 14041 .LVL1057: +6898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 14042 .loc 1 6898 8 discriminator 1 view .LVU4896 + 14043 0054 20B1 cbz r0, .L894 +6902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14044 .loc 1 6902 7 is_stmt 1 view .LVU4897 + 14045 0056 1021 movs r1, #16 + 14046 0058 2046 mov r0, r4 + 14047 005a FFF7FEFF bl I2C_ITError + 14048 .LVL1058: + 14049 .L888: +6910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14050 .loc 1 6910 1 is_stmt 0 view .LVU4898 + 14051 005e 10BD pop {r4, pc} + 14052 .LVL1059: + 14053 .L894: +6907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14054 .loc 1 6907 7 is_stmt 1 view .LVU4899 + 14055 0060 4021 movs r1, #64 + 14056 0062 2046 mov r0, r4 + 14057 0064 FFF7FEFF bl I2C_Enable_IRQ + 14058 .LVL1060: +6910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14059 .loc 1 6910 1 is_stmt 0 view .LVU4900 + 14060 0068 F9E7 b .L888 + 14061 .cfi_endproc + 14062 .LFE209: + 14064 .section .text.I2C_Mem_ISR_IT,"ax",%progbits + 14065 .align 1 + 14066 .syntax unified + 14067 .thumb + 14068 .thumb_func + 14070 I2C_Mem_ISR_IT: + 14071 .LVL1061: + 14072 .LFB191: +5100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t direction = I2C_GENERATE_START_WRITE; + 14073 .loc 1 5100 1 is_stmt 1 view -0 + 14074 .cfi_startproc + 14075 @ args = 0, pretend = 0, frame = 0 + 14076 @ frame_needed = 0, uses_anonymous_args = 0 +5101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 14077 .loc 1 5101 3 view .LVU4902 + ARM GAS /tmp/ccSHpINd.s page 462 + + +5102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14078 .loc 1 5102 3 view .LVU4903 +5105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14079 .loc 1 5105 3 view .LVU4904 +5105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14080 .loc 1 5105 3 view .LVU4905 + 14081 0000 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 14082 0004 012B cmp r3, #1 + 14083 0006 00F0D580 beq .L914 +5100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t direction = I2C_GENERATE_START_WRITE; + 14084 .loc 1 5100 1 is_stmt 0 view .LVU4906 + 14085 000a 70B5 push {r4, r5, r6, lr} + 14086 .LCFI148: + 14087 .cfi_def_cfa_offset 16 + 14088 .cfi_offset 4, -16 + 14089 .cfi_offset 5, -12 + 14090 .cfi_offset 6, -8 + 14091 .cfi_offset 14, -4 + 14092 000c 82B0 sub sp, sp, #8 + 14093 .LCFI149: + 14094 .cfi_def_cfa_offset 24 + 14095 000e 0446 mov r4, r0 + 14096 0010 0D46 mov r5, r1 + 14097 0012 1646 mov r6, r2 +5105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14098 .loc 1 5105 3 is_stmt 1 discriminator 2 view .LVU4907 + 14099 0014 0123 movs r3, #1 + 14100 0016 80F84030 strb r3, [r0, #64] +5105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14101 .loc 1 5105 3 discriminator 2 view .LVU4908 +5107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 14102 .loc 1 5107 3 view .LVU4909 +5107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 14103 .loc 1 5107 6 is_stmt 0 view .LVU4910 + 14104 001a 11F0100F tst r1, #16 + 14105 001e 02D0 beq .L899 +5107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 14106 .loc 1 5107 58 discriminator 1 view .LVU4911 + 14107 0020 12F0100F tst r2, #16 + 14108 0024 22D1 bne .L920 + 14109 .L899: +5121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 14110 .loc 1 5121 8 is_stmt 1 view .LVU4912 +5121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 14111 .loc 1 5121 11 is_stmt 0 view .LVU4913 + 14112 0026 15F0040F tst r5, #4 + 14113 002a 29D0 beq .L901 +5121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 14114 .loc 1 5121 65 discriminator 1 view .LVU4914 + 14115 002c 16F0040F tst r6, #4 + 14116 0030 26D0 beq .L901 +5125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14117 .loc 1 5125 5 is_stmt 1 view .LVU4915 +5125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14118 .loc 1 5125 16 is_stmt 0 view .LVU4916 + 14119 0032 25F00405 bic r5, r5, #4 + 14120 .LVL1062: + ARM GAS /tmp/ccSHpINd.s page 463 + + +5128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14121 .loc 1 5128 5 is_stmt 1 view .LVU4917 +5128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14122 .loc 1 5128 36 is_stmt 0 view .LVU4918 + 14123 0036 2368 ldr r3, [r4] +5128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14124 .loc 1 5128 46 view .LVU4919 + 14125 0038 5A6A ldr r2, [r3, #36] + 14126 .LVL1063: +5128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14127 .loc 1 5128 10 view .LVU4920 + 14128 003a 636A ldr r3, [r4, #36] +5128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14129 .loc 1 5128 21 view .LVU4921 + 14130 003c 1A70 strb r2, [r3] +5131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14131 .loc 1 5131 5 is_stmt 1 view .LVU4922 +5131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14132 .loc 1 5131 9 is_stmt 0 view .LVU4923 + 14133 003e 636A ldr r3, [r4, #36] +5131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14134 .loc 1 5131 19 view .LVU4924 + 14135 0040 0133 adds r3, r3, #1 + 14136 0042 6362 str r3, [r4, #36] +5133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 14137 .loc 1 5133 5 is_stmt 1 view .LVU4925 +5133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 14138 .loc 1 5133 9 is_stmt 0 view .LVU4926 + 14139 0044 238D ldrh r3, [r4, #40] +5133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 14140 .loc 1 5133 19 view .LVU4927 + 14141 0046 013B subs r3, r3, #1 + 14142 0048 2385 strh r3, [r4, #40] @ movhi +5134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14143 .loc 1 5134 5 is_stmt 1 view .LVU4928 +5134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14144 .loc 1 5134 9 is_stmt 0 view .LVU4929 + 14145 004a 638D ldrh r3, [r4, #42] + 14146 004c 9BB2 uxth r3, r3 +5134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14147 .loc 1 5134 20 view .LVU4930 + 14148 004e 013B subs r3, r3, #1 + 14149 0050 9BB2 uxth r3, r3 + 14150 0052 6385 strh r3, [r4, #42] @ movhi + 14151 .LVL1064: + 14152 .L900: +5234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14153 .loc 1 5234 3 is_stmt 1 view .LVU4931 +5236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 14154 .loc 1 5236 3 view .LVU4932 +5236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 14155 .loc 1 5236 6 is_stmt 0 view .LVU4933 + 14156 0054 15F0200F tst r5, #32 + 14157 0058 03D0 beq .L913 +5236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 14158 .loc 1 5236 61 discriminator 1 view .LVU4934 + 14159 005a 16F0200F tst r6, #32 + ARM GAS /tmp/ccSHpINd.s page 464 + + + 14160 005e 40F0A480 bne .L921 + 14161 .L913: +5244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14162 .loc 1 5244 3 is_stmt 1 view .LVU4935 +5244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14163 .loc 1 5244 3 view .LVU4936 + 14164 0062 0020 movs r0, #0 + 14165 0064 84F84000 strb r0, [r4, #64] +5244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14166 .loc 1 5244 3 view .LVU4937 +5246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14167 .loc 1 5246 3 view .LVU4938 +5247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14168 .loc 1 5247 1 is_stmt 0 view .LVU4939 + 14169 0068 02B0 add sp, sp, #8 + 14170 .LCFI150: + 14171 .cfi_remember_state + 14172 .cfi_def_cfa_offset 16 + 14173 @ sp needed + 14174 006a 70BD pop {r4, r5, r6, pc} + 14175 .LVL1065: + 14176 .L920: + 14177 .LCFI151: + 14178 .cfi_restore_state +5111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14179 .loc 1 5111 5 is_stmt 1 view .LVU4940 + 14180 006c 0368 ldr r3, [r0] + 14181 006e 1022 movs r2, #16 + 14182 .LVL1066: +5111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14183 .loc 1 5111 5 is_stmt 0 view .LVU4941 + 14184 0070 DA61 str r2, [r3, #28] +5116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14185 .loc 1 5116 5 is_stmt 1 view .LVU4942 +5116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14186 .loc 1 5116 9 is_stmt 0 view .LVU4943 + 14187 0072 436C ldr r3, [r0, #68] +5116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14188 .loc 1 5116 21 view .LVU4944 + 14189 0074 43F00403 orr r3, r3, #4 + 14190 0078 4364 str r3, [r0, #68] +5119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14191 .loc 1 5119 5 is_stmt 1 view .LVU4945 + 14192 007a FFF7FEFF bl I2C_Flush_TXDR + 14193 .LVL1067: +5119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14194 .loc 1 5119 5 is_stmt 0 view .LVU4946 + 14195 007e E9E7 b .L900 + 14196 .LVL1068: + 14197 .L901: +5136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 14198 .loc 1 5136 8 is_stmt 1 view .LVU4947 +5136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 14199 .loc 1 5136 11 is_stmt 0 view .LVU4948 + 14200 0080 15F0020F tst r5, #2 + 14201 0084 1DD0 beq .L902 +5136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + ARM GAS /tmp/ccSHpINd.s page 465 + + + 14202 .loc 1 5136 65 discriminator 1 view .LVU4949 + 14203 0086 16F0020F tst r6, #2 + 14204 008a 1AD0 beq .L902 +5139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14205 .loc 1 5139 5 is_stmt 1 view .LVU4950 +5139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14206 .loc 1 5139 13 is_stmt 0 view .LVU4951 + 14207 008c 236D ldr r3, [r4, #80] +5139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14208 .loc 1 5139 8 view .LVU4952 + 14209 008e B3F1FF3F cmp r3, #-1 + 14210 0092 06D0 beq .L922 +5153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14211 .loc 1 5153 7 is_stmt 1 view .LVU4953 +5153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14212 .loc 1 5153 11 is_stmt 0 view .LVU4954 + 14213 0094 2368 ldr r3, [r4] +5153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14214 .loc 1 5153 34 view .LVU4955 + 14215 0096 226D ldr r2, [r4, #80] + 14216 .LVL1069: +5153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14217 .loc 1 5153 28 view .LVU4956 + 14218 0098 9A62 str r2, [r3, #40] +5156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14219 .loc 1 5156 7 is_stmt 1 view .LVU4957 +5156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14220 .loc 1 5156 24 is_stmt 0 view .LVU4958 + 14221 009a 4FF0FF33 mov r3, #-1 + 14222 009e 2365 str r3, [r4, #80] + 14223 00a0 D8E7 b .L900 + 14224 .LVL1070: + 14225 .L922: +5142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14226 .loc 1 5142 7 is_stmt 1 view .LVU4959 +5142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14227 .loc 1 5142 35 is_stmt 0 view .LVU4960 + 14228 00a2 626A ldr r2, [r4, #36] + 14229 .LVL1071: +5142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14230 .loc 1 5142 11 view .LVU4961 + 14231 00a4 2368 ldr r3, [r4] +5142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14232 .loc 1 5142 30 view .LVU4962 + 14233 00a6 1278 ldrb r2, [r2] @ zero_extendqisi2 +5142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14234 .loc 1 5142 28 view .LVU4963 + 14235 00a8 9A62 str r2, [r3, #40] +5145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14236 .loc 1 5145 7 is_stmt 1 view .LVU4964 +5145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14237 .loc 1 5145 11 is_stmt 0 view .LVU4965 + 14238 00aa 636A ldr r3, [r4, #36] +5145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14239 .loc 1 5145 21 view .LVU4966 + 14240 00ac 0133 adds r3, r3, #1 + 14241 00ae 6362 str r3, [r4, #36] + ARM GAS /tmp/ccSHpINd.s page 466 + + +5147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 14242 .loc 1 5147 7 is_stmt 1 view .LVU4967 +5147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 14243 .loc 1 5147 11 is_stmt 0 view .LVU4968 + 14244 00b0 238D ldrh r3, [r4, #40] +5147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** hi2c->XferCount--; + 14245 .loc 1 5147 21 view .LVU4969 + 14246 00b2 013B subs r3, r3, #1 + 14247 00b4 2385 strh r3, [r4, #40] @ movhi +5148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14248 .loc 1 5148 7 is_stmt 1 view .LVU4970 +5148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14249 .loc 1 5148 11 is_stmt 0 view .LVU4971 + 14250 00b6 638D ldrh r3, [r4, #42] + 14251 00b8 9BB2 uxth r3, r3 +5148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14252 .loc 1 5148 22 view .LVU4972 + 14253 00ba 013B subs r3, r3, #1 + 14254 00bc 9BB2 uxth r3, r3 + 14255 00be 6385 strh r3, [r4, #42] @ movhi + 14256 00c0 C8E7 b .L900 + 14257 .LVL1072: + 14258 .L902: +5159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 14259 .loc 1 5159 8 is_stmt 1 view .LVU4973 +5159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 14260 .loc 1 5159 11 is_stmt 0 view .LVU4974 + 14261 00c2 15F0800F tst r5, #128 + 14262 00c6 34D0 beq .L904 +5159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 14263 .loc 1 5159 64 discriminator 1 view .LVU4975 + 14264 00c8 16F0400F tst r6, #64 + 14265 00cc 31D0 beq .L904 +5162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14266 .loc 1 5162 5 is_stmt 1 view .LVU4976 +5162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14267 .loc 1 5162 14 is_stmt 0 view .LVU4977 + 14268 00ce 638D ldrh r3, [r4, #42] + 14269 00d0 9BB2 uxth r3, r3 +5162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14270 .loc 1 5162 8 view .LVU4978 + 14271 00d2 4BB3 cbz r3, .L905 +5162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14272 .loc 1 5162 41 discriminator 1 view .LVU4979 + 14273 00d4 238D ldrh r3, [r4, #40] +5162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14274 .loc 1 5162 33 discriminator 1 view .LVU4980 + 14275 00d6 3BBB cbnz r3, .L905 +5164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14276 .loc 1 5164 7 is_stmt 1 view .LVU4981 +5164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14277 .loc 1 5164 15 is_stmt 0 view .LVU4982 + 14278 00d8 638D ldrh r3, [r4, #42] + 14279 00da 9BB2 uxth r3, r3 +5164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14280 .loc 1 5164 10 view .LVU4983 + 14281 00dc FF2B cmp r3, #255 + ARM GAS /tmp/ccSHpINd.s page 467 + + + 14282 00de 15D9 bls .L906 +5167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14283 .loc 1 5167 9 is_stmt 1 view .LVU4984 +5167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14284 .loc 1 5167 13 is_stmt 0 view .LVU4985 + 14285 00e0 2368 ldr r3, [r4] + 14286 00e2 9B69 ldr r3, [r3, #24] +5167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14287 .loc 1 5167 12 view .LVU4986 + 14288 00e4 13F4803F tst r3, #65536 + 14289 00e8 0DD0 beq .L907 +5169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14290 .loc 1 5169 11 is_stmt 1 view .LVU4987 +5169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14291 .loc 1 5169 26 is_stmt 0 view .LVU4988 + 14292 00ea 0123 movs r3, #1 + 14293 00ec 2385 strh r3, [r4, #40] @ movhi + 14294 .L908: +5175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 14295 .loc 1 5175 9 is_stmt 1 view .LVU4989 +5175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 14296 .loc 1 5175 48 is_stmt 0 view .LVU4990 + 14297 00ee E16C ldr r1, [r4, #76] + 14298 .LVL1073: +5175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 14299 .loc 1 5175 9 view .LVU4991 + 14300 00f0 0023 movs r3, #0 + 14301 00f2 0093 str r3, [sp] + 14302 00f4 4FF08073 mov r3, #16777216 + 14303 00f8 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 14304 .LVL1074: +5175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 14305 .loc 1 5175 9 view .LVU4992 + 14306 00fc 89B2 uxth r1, r1 + 14307 00fe 2046 mov r0, r4 + 14308 .LVL1075: +5175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 14309 .loc 1 5175 9 view .LVU4993 + 14310 0100 FFF7FEFF bl I2C_TransferConfig + 14311 .LVL1076: + 14312 0104 A6E7 b .L900 + 14313 .LVL1077: + 14314 .L907: +5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14315 .loc 1 5173 11 is_stmt 1 view .LVU4994 +5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14316 .loc 1 5173 26 is_stmt 0 view .LVU4995 + 14317 0106 FF23 movs r3, #255 + 14318 0108 2385 strh r3, [r4, #40] @ movhi + 14319 010a F0E7 b .L908 + 14320 .L906: +5180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + 14321 .loc 1 5180 9 is_stmt 1 view .LVU4996 +5180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + 14322 .loc 1 5180 30 is_stmt 0 view .LVU4997 + 14323 010c 628D ldrh r2, [r4, #42] + 14324 .LVL1078: + ARM GAS /tmp/ccSHpINd.s page 468 + + +5180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + 14325 .loc 1 5180 30 view .LVU4998 + 14326 010e 92B2 uxth r2, r2 +5180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + 14327 .loc 1 5180 24 view .LVU4999 + 14328 0110 2285 strh r2, [r4, #40] @ movhi +5181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 14329 .loc 1 5181 9 is_stmt 1 view .LVU5000 +5181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 14330 .loc 1 5181 48 is_stmt 0 view .LVU5001 + 14331 0112 E16C ldr r1, [r4, #76] + 14332 .LVL1079: +5181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 14333 .loc 1 5181 9 view .LVU5002 + 14334 0114 0023 movs r3, #0 + 14335 0116 0093 str r3, [sp] + 14336 0118 4FF00073 mov r3, #33554432 + 14337 011c D2B2 uxtb r2, r2 + 14338 011e 89B2 uxth r1, r1 + 14339 0120 2046 mov r0, r4 + 14340 .LVL1080: +5181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 14341 .loc 1 5181 9 view .LVU5003 + 14342 0122 FFF7FEFF bl I2C_TransferConfig + 14343 .LVL1081: + 14344 0126 95E7 b .L900 + 14345 .LVL1082: + 14346 .L905: +5189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14347 .loc 1 5189 7 is_stmt 1 view .LVU5004 + 14348 0128 4021 movs r1, #64 + 14349 .LVL1083: +5189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14350 .loc 1 5189 7 is_stmt 0 view .LVU5005 + 14351 012a 2046 mov r0, r4 + 14352 .LVL1084: +5189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14353 .loc 1 5189 7 view .LVU5006 + 14354 012c FFF7FEFF bl I2C_ITError + 14355 .LVL1085: +5189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14356 .loc 1 5189 7 view .LVU5007 + 14357 0130 90E7 b .L900 + 14358 .LVL1086: + 14359 .L904: +5192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 14360 .loc 1 5192 8 is_stmt 1 view .LVU5008 +5192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 14361 .loc 1 5192 11 is_stmt 0 view .LVU5009 + 14362 0132 15F0400F tst r5, #64 + 14363 0136 8DD0 beq .L900 +5192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 14364 .loc 1 5192 63 discriminator 1 view .LVU5010 + 14365 0138 16F0400F tst r6, #64 + 14366 013c 8AD0 beq .L900 +5196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14367 .loc 1 5196 5 is_stmt 1 view .LVU5011 + ARM GAS /tmp/ccSHpINd.s page 469 + + + 14368 013e 0121 movs r1, #1 + 14369 .LVL1087: +5196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14370 .loc 1 5196 5 is_stmt 0 view .LVU5012 + 14371 0140 2046 mov r0, r4 + 14372 .LVL1088: +5196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14373 .loc 1 5196 5 view .LVU5013 + 14374 0142 FFF7FEFF bl I2C_Disable_IRQ + 14375 .LVL1089: +5199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14376 .loc 1 5199 5 is_stmt 1 view .LVU5014 + 14377 0146 0221 movs r1, #2 + 14378 0148 2046 mov r0, r4 + 14379 014a FFF7FEFF bl I2C_Enable_IRQ + 14380 .LVL1090: +5201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14381 .loc 1 5201 5 view .LVU5015 +5201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14382 .loc 1 5201 13 is_stmt 0 view .LVU5016 + 14383 014e 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 14384 0152 DBB2 uxtb r3, r3 +5201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14385 .loc 1 5201 8 view .LVU5017 + 14386 0154 222B cmp r3, #34 + 14387 0156 16D0 beq .L915 +5101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 14388 .loc 1 5101 12 view .LVU5018 + 14389 0158 1748 ldr r0, .L923 + 14390 .L909: + 14391 .LVL1091: +5206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14392 .loc 1 5206 5 is_stmt 1 view .LVU5019 +5206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14393 .loc 1 5206 13 is_stmt 0 view .LVU5020 + 14394 015a 638D ldrh r3, [r4, #42] + 14395 015c 9BB2 uxth r3, r3 +5206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14396 .loc 1 5206 8 view .LVU5021 + 14397 015e FF2B cmp r3, #255 + 14398 0160 16D9 bls .L910 +5209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14399 .loc 1 5209 7 is_stmt 1 view .LVU5022 +5209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14400 .loc 1 5209 11 is_stmt 0 view .LVU5023 + 14401 0162 2368 ldr r3, [r4] + 14402 0164 9B69 ldr r3, [r3, #24] +5209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14403 .loc 1 5209 10 view .LVU5024 + 14404 0166 13F4803F tst r3, #65536 + 14405 016a 0ED0 beq .L911 +5211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14406 .loc 1 5211 9 is_stmt 1 view .LVU5025 +5211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14407 .loc 1 5211 24 is_stmt 0 view .LVU5026 + 14408 016c 0123 movs r3, #1 + 14409 016e 2385 strh r3, [r4, #40] @ movhi + ARM GAS /tmp/ccSHpINd.s page 470 + + + 14410 .L912: +5219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, direction); + 14411 .loc 1 5219 7 is_stmt 1 view .LVU5027 +5219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, direction); + 14412 .loc 1 5219 46 is_stmt 0 view .LVU5028 + 14413 0170 E16C ldr r1, [r4, #76] +5219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, direction); + 14414 .loc 1 5219 7 view .LVU5029 + 14415 0172 0090 str r0, [sp] + 14416 0174 4FF08073 mov r3, #16777216 + 14417 0178 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 14418 017c 89B2 uxth r1, r1 + 14419 017e 2046 mov r0, r4 + 14420 .LVL1092: +5219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, direction); + 14421 .loc 1 5219 7 view .LVU5030 + 14422 0180 FFF7FEFF bl I2C_TransferConfig + 14423 .LVL1093: +5219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_RELOAD_MODE, direction); + 14424 .loc 1 5219 7 view .LVU5031 + 14425 0184 66E7 b .L900 + 14426 .LVL1094: + 14427 .L915: +5203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14428 .loc 1 5203 17 view .LVU5032 + 14429 0186 0D48 ldr r0, .L923+4 + 14430 0188 E7E7 b .L909 + 14431 .LVL1095: + 14432 .L911: +5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14433 .loc 1 5215 9 is_stmt 1 view .LVU5033 +5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14434 .loc 1 5215 24 is_stmt 0 view .LVU5034 + 14435 018a FF23 movs r3, #255 + 14436 018c 2385 strh r3, [r4, #40] @ movhi + 14437 018e EFE7 b .L912 + 14438 .L910: +5224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14439 .loc 1 5224 7 is_stmt 1 view .LVU5035 +5224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14440 .loc 1 5224 28 is_stmt 0 view .LVU5036 + 14441 0190 628D ldrh r2, [r4, #42] + 14442 0192 92B2 uxth r2, r2 +5224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14443 .loc 1 5224 22 view .LVU5037 + 14444 0194 2285 strh r2, [r4, #40] @ movhi +5227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, direction); + 14445 .loc 1 5227 7 is_stmt 1 view .LVU5038 +5227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, direction); + 14446 .loc 1 5227 46 is_stmt 0 view .LVU5039 + 14447 0196 E16C ldr r1, [r4, #76] +5227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, direction); + 14448 .loc 1 5227 7 view .LVU5040 + 14449 0198 0090 str r0, [sp] + 14450 019a 4FF00073 mov r3, #33554432 + 14451 019e D2B2 uxtb r2, r2 + 14452 01a0 89B2 uxth r1, r1 + ARM GAS /tmp/ccSHpINd.s page 471 + + + 14453 01a2 2046 mov r0, r4 + 14454 .LVL1096: +5227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, direction); + 14455 .loc 1 5227 7 view .LVU5041 + 14456 01a4 FFF7FEFF bl I2C_TransferConfig + 14457 .LVL1097: +5227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** I2C_AUTOEND_MODE, direction); + 14458 .loc 1 5227 7 view .LVU5042 + 14459 01a8 54E7 b .L900 + 14460 .LVL1098: + 14461 .L921: +5240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14462 .loc 1 5240 5 is_stmt 1 view .LVU5043 + 14463 01aa 2946 mov r1, r5 + 14464 01ac 2046 mov r0, r4 + 14465 01ae FFF7FEFF bl I2C_ITMasterCplt + 14466 .LVL1099: + 14467 01b2 56E7 b .L913 + 14468 .LVL1100: + 14469 .L914: + 14470 .LCFI152: + 14471 .cfi_def_cfa_offset 0 + 14472 .cfi_restore 4 + 14473 .cfi_restore 5 + 14474 .cfi_restore 6 + 14475 .cfi_restore 14 +5105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14476 .loc 1 5105 3 is_stmt 0 discriminator 1 view .LVU5044 + 14477 01b4 0220 movs r0, #2 + 14478 .LVL1101: +5247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14479 .loc 1 5247 1 view .LVU5045 + 14480 01b6 7047 bx lr + 14481 .L924: + 14482 .align 2 + 14483 .L923: + 14484 01b8 00200080 .word -2147475456 + 14485 01bc 00240080 .word -2147474432 + 14486 .cfi_endproc + 14487 .LFE191: + 14489 .section .text.HAL_I2C_ER_IRQHandler,"ax",%progbits + 14490 .align 1 + 14491 .global HAL_I2C_ER_IRQHandler + 14492 .syntax unified + 14493 .thumb + 14494 .thumb_func + 14496 HAL_I2C_ER_IRQHandler: + 14497 .LVL1102: + 14498 .LFB176: +4658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); + 14499 .loc 1 4658 1 is_stmt 1 view -0 + 14500 .cfi_startproc + 14501 @ args = 0, pretend = 0, frame = 0 + 14502 @ frame_needed = 0, uses_anonymous_args = 0 +4658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); + 14503 .loc 1 4658 1 is_stmt 0 view .LVU5047 + 14504 0000 10B5 push {r4, lr} + ARM GAS /tmp/ccSHpINd.s page 472 + + + 14505 .LCFI153: + 14506 .cfi_def_cfa_offset 8 + 14507 .cfi_offset 4, -8 + 14508 .cfi_offset 14, -4 +4659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 14509 .loc 1 4659 3 is_stmt 1 view .LVU5048 +4659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 14510 .loc 1 4659 24 is_stmt 0 view .LVU5049 + 14511 0002 0268 ldr r2, [r0] +4659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 14512 .loc 1 4659 12 view .LVU5050 + 14513 0004 9369 ldr r3, [r2, #24] + 14514 .LVL1103: +4660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmperror; + 14515 .loc 1 4660 3 is_stmt 1 view .LVU5051 +4660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** uint32_t tmperror; + 14516 .loc 1 4660 12 is_stmt 0 view .LVU5052 + 14517 0006 1168 ldr r1, [r2] + 14518 .LVL1104: +4661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14519 .loc 1 4661 3 is_stmt 1 view .LVU5053 +4664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 14520 .loc 1 4664 3 view .LVU5054 +4664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 14521 .loc 1 4664 6 is_stmt 0 view .LVU5055 + 14522 0008 13F4807F tst r3, #256 + 14523 000c 09D0 beq .L926 +4664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 14524 .loc 1 4664 57 discriminator 1 view .LVU5056 + 14525 000e 11F0800F tst r1, #128 + 14526 0012 06D0 beq .L926 +4667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14527 .loc 1 4667 5 is_stmt 1 view .LVU5057 +4667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14528 .loc 1 4667 9 is_stmt 0 view .LVU5058 + 14529 0014 446C ldr r4, [r0, #68] +4667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14530 .loc 1 4667 21 view .LVU5059 + 14531 0016 44F00104 orr r4, r4, #1 + 14532 001a 4464 str r4, [r0, #68] +4670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14533 .loc 1 4670 5 is_stmt 1 view .LVU5060 + 14534 001c 4FF48074 mov r4, #256 + 14535 0020 D461 str r4, [r2, #28] + 14536 .L926: +4674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 14537 .loc 1 4674 3 view .LVU5061 +4674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 14538 .loc 1 4674 6 is_stmt 0 view .LVU5062 + 14539 0022 13F4806F tst r3, #1024 + 14540 0026 0AD0 beq .L927 +4674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 14541 .loc 1 4674 56 discriminator 1 view .LVU5063 + 14542 0028 11F0800F tst r1, #128 + 14543 002c 07D0 beq .L927 +4677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14544 .loc 1 4677 5 is_stmt 1 view .LVU5064 + ARM GAS /tmp/ccSHpINd.s page 473 + + +4677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14545 .loc 1 4677 9 is_stmt 0 view .LVU5065 + 14546 002e 426C ldr r2, [r0, #68] +4677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14547 .loc 1 4677 21 view .LVU5066 + 14548 0030 42F00802 orr r2, r2, #8 + 14549 0034 4264 str r2, [r0, #68] +4680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14550 .loc 1 4680 5 is_stmt 1 view .LVU5067 + 14551 0036 0268 ldr r2, [r0] + 14552 0038 4FF48064 mov r4, #1024 + 14553 003c D461 str r4, [r2, #28] + 14554 .L927: +4684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 14555 .loc 1 4684 3 view .LVU5068 +4684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 14556 .loc 1 4684 6 is_stmt 0 view .LVU5069 + 14557 003e 13F4007F tst r3, #512 + 14558 0042 0AD0 beq .L928 +4684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 14559 .loc 1 4684 57 discriminator 1 view .LVU5070 + 14560 0044 11F0800F tst r1, #128 + 14561 0048 07D0 beq .L928 +4687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14562 .loc 1 4687 5 is_stmt 1 view .LVU5071 +4687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14563 .loc 1 4687 9 is_stmt 0 view .LVU5072 + 14564 004a 436C ldr r3, [r0, #68] + 14565 .LVL1105: +4687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14566 .loc 1 4687 21 view .LVU5073 + 14567 004c 43F00203 orr r3, r3, #2 + 14568 0050 4364 str r3, [r0, #68] +4690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14569 .loc 1 4690 5 is_stmt 1 view .LVU5074 + 14570 0052 0368 ldr r3, [r0] + 14571 0054 4FF40072 mov r2, #512 + 14572 0058 DA61 str r2, [r3, #28] + 14573 .L928: +4694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14574 .loc 1 4694 3 view .LVU5075 +4694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14575 .loc 1 4694 12 is_stmt 0 view .LVU5076 + 14576 005a 416C ldr r1, [r0, #68] + 14577 .LVL1106: +4697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14578 .loc 1 4697 3 is_stmt 1 view .LVU5077 +4697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14579 .loc 1 4697 6 is_stmt 0 view .LVU5078 + 14580 005c 11F00B0F tst r1, #11 + 14581 0060 00D1 bne .L931 + 14582 .LVL1107: + 14583 .L925: +4701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14584 .loc 1 4701 1 view .LVU5079 + 14585 0062 10BD pop {r4, pc} + 14586 .LVL1108: + ARM GAS /tmp/ccSHpINd.s page 474 + + + 14587 .L931: +4699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14588 .loc 1 4699 5 is_stmt 1 view .LVU5080 + 14589 0064 FFF7FEFF bl I2C_ITError + 14590 .LVL1109: +4701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14591 .loc 1 4701 1 is_stmt 0 view .LVU5081 + 14592 0068 FBE7 b .L925 + 14593 .cfi_endproc + 14594 .LFE176: + 14596 .section .text.I2C_DMAAbort,"ax",%progbits + 14597 .align 1 + 14598 .syntax unified + 14599 .thumb + 14600 .thumb_func + 14602 I2C_DMAAbort: + 14603 .LVL1110: + 14604 .LFB212: +6988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 14605 .loc 1 6988 1 is_stmt 1 view -0 + 14606 .cfi_startproc + 14607 @ args = 0, pretend = 0, frame = 0 + 14608 @ frame_needed = 0, uses_anonymous_args = 0 +6988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 14609 .loc 1 6988 1 is_stmt 0 view .LVU5083 + 14610 0000 08B5 push {r3, lr} + 14611 .LCFI154: + 14612 .cfi_def_cfa_offset 8 + 14613 .cfi_offset 3, -8 + 14614 .cfi_offset 14, -4 +6990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14615 .loc 1 6990 3 is_stmt 1 view .LVU5084 +6990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14616 .loc 1 6990 22 is_stmt 0 view .LVU5085 + 14617 0002 806B ldr r0, [r0, #56] + 14618 .LVL1111: +6993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14619 .loc 1 6993 3 is_stmt 1 view .LVU5086 +6993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14620 .loc 1 6993 11 is_stmt 0 view .LVU5087 + 14621 0004 836B ldr r3, [r0, #56] +6993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14622 .loc 1 6993 6 view .LVU5088 + 14623 0006 0BB1 cbz r3, .L933 +6995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14624 .loc 1 6995 5 is_stmt 1 view .LVU5089 +6995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14625 .loc 1 6995 37 is_stmt 0 view .LVU5090 + 14626 0008 0022 movs r2, #0 + 14627 000a 1A65 str r2, [r3, #80] + 14628 .L933: +6997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14629 .loc 1 6997 3 is_stmt 1 view .LVU5091 +6997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + 14630 .loc 1 6997 11 is_stmt 0 view .LVU5092 + 14631 000c C36B ldr r3, [r0, #60] +6997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** { + ARM GAS /tmp/ccSHpINd.s page 475 + + + 14632 .loc 1 6997 6 view .LVU5093 + 14633 000e 0BB1 cbz r3, .L934 +6999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14634 .loc 1 6999 5 is_stmt 1 view .LVU5094 +6999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14635 .loc 1 6999 37 is_stmt 0 view .LVU5095 + 14636 0010 0022 movs r2, #0 + 14637 0012 1A65 str r2, [r3, #80] + 14638 .L934: +7002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14639 .loc 1 7002 3 is_stmt 1 view .LVU5096 + 14640 0014 FFF7FEFF bl I2C_TreatErrorCallback + 14641 .LVL1112: +7003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14642 .loc 1 7003 1 is_stmt 0 view .LVU5097 + 14643 0018 08BD pop {r3, pc} + 14644 .cfi_endproc + 14645 .LFE212: + 14647 .section .text.HAL_I2C_GetState,"ax",%progbits + 14648 .align 1 + 14649 .global HAL_I2C_GetState + 14650 .syntax unified + 14651 .thumb + 14652 .thumb_func + 14654 HAL_I2C_GetState: + 14655 .LVL1113: + 14656 .LFB187: +4892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** /* Return I2C handle state */ + 14657 .loc 1 4892 1 is_stmt 1 view -0 + 14658 .cfi_startproc + 14659 @ args = 0, pretend = 0, frame = 0 + 14660 @ frame_needed = 0, uses_anonymous_args = 0 + 14661 @ link register save eliminated. +4894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14662 .loc 1 4894 3 view .LVU5099 +4894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14663 .loc 1 4894 14 is_stmt 0 view .LVU5100 + 14664 0000 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 14665 .LVL1114: +4895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14666 .loc 1 4895 1 view .LVU5101 + 14667 0004 7047 bx lr + 14668 .cfi_endproc + 14669 .LFE187: + 14671 .section .text.HAL_I2C_GetMode,"ax",%progbits + 14672 .align 1 + 14673 .global HAL_I2C_GetMode + 14674 .syntax unified + 14675 .thumb + 14676 .thumb_func + 14678 HAL_I2C_GetMode: + 14679 .LVL1115: + 14680 .LFB188: +4904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return hi2c->Mode; + 14681 .loc 1 4904 1 is_stmt 1 view -0 + 14682 .cfi_startproc + 14683 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccSHpINd.s page 476 + + + 14684 @ frame_needed = 0, uses_anonymous_args = 0 + 14685 @ link register save eliminated. +4905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14686 .loc 1 4905 3 view .LVU5103 +4905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14687 .loc 1 4905 14 is_stmt 0 view .LVU5104 + 14688 0000 90F84200 ldrb r0, [r0, #66] @ zero_extendqisi2 + 14689 .LVL1116: +4906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14690 .loc 1 4906 1 view .LVU5105 + 14691 0004 7047 bx lr + 14692 .cfi_endproc + 14693 .LFE188: + 14695 .section .text.HAL_I2C_GetError,"ax",%progbits + 14696 .align 1 + 14697 .global HAL_I2C_GetError + 14698 .syntax unified + 14699 .thumb + 14700 .thumb_func + 14702 HAL_I2C_GetError: + 14703 .LVL1117: + 14704 .LFB189: +4915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** return hi2c->ErrorCode; + 14705 .loc 1 4915 1 is_stmt 1 view -0 + 14706 .cfi_startproc + 14707 @ args = 0, pretend = 0, frame = 0 + 14708 @ frame_needed = 0, uses_anonymous_args = 0 + 14709 @ link register save eliminated. +4916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14710 .loc 1 4916 3 view .LVU5107 +4916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** } + 14711 .loc 1 4916 14 is_stmt 0 view .LVU5108 + 14712 0000 406C ldr r0, [r0, #68] + 14713 .LVL1118: +4917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c **** + 14714 .loc 1 4917 1 view .LVU5109 + 14715 0002 7047 bx lr + 14716 .cfi_endproc + 14717 .LFE189: + 14719 .text + 14720 .Letext0: + 14721 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 14722 .file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 14723 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + 14724 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 14725 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h" + 14726 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h" + 14727 .file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h" + ARM GAS /tmp/ccSHpINd.s page 477 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_i2c.c + /tmp/ccSHpINd.s:20 .text.I2C_Flush_TXDR:00000000 $t + /tmp/ccSHpINd.s:25 .text.I2C_Flush_TXDR:00000000 I2C_Flush_TXDR + /tmp/ccSHpINd.s:63 .text.I2C_TransferConfig:00000000 $t + /tmp/ccSHpINd.s:68 .text.I2C_TransferConfig:00000000 I2C_TransferConfig + /tmp/ccSHpINd.s:126 .text.I2C_Enable_IRQ:00000000 $t + /tmp/ccSHpINd.s:131 .text.I2C_Enable_IRQ:00000000 I2C_Enable_IRQ + /tmp/ccSHpINd.s:293 .text.I2C_Enable_IRQ:00000090 $d + /tmp/ccSHpINd.s:13416 .text.I2C_Master_ISR_DMA:00000000 I2C_Master_ISR_DMA + /tmp/ccSHpINd.s:13116 .text.I2C_Slave_ISR_DMA:00000000 I2C_Slave_ISR_DMA + /tmp/ccSHpINd.s:12707 .text.I2C_Mem_ISR_DMA:00000000 I2C_Mem_ISR_DMA + /tmp/ccSHpINd.s:300 .text.I2C_Disable_IRQ:00000000 $t + /tmp/ccSHpINd.s:305 .text.I2C_Disable_IRQ:00000000 I2C_Disable_IRQ + /tmp/ccSHpINd.s:429 .text.I2C_ConvertOtherXferOptions:00000000 $t + /tmp/ccSHpINd.s:434 .text.I2C_ConvertOtherXferOptions:00000000 I2C_ConvertOtherXferOptions + /tmp/ccSHpINd.s:475 .text.I2C_IsErrorOccurred:00000000 $t + /tmp/ccSHpINd.s:480 .text.I2C_IsErrorOccurred:00000000 I2C_IsErrorOccurred + /tmp/ccSHpINd.s:761 .text.I2C_WaitOnTXISFlagUntilTimeout:00000000 $t + /tmp/ccSHpINd.s:766 .text.I2C_WaitOnTXISFlagUntilTimeout:00000000 I2C_WaitOnTXISFlagUntilTimeout + /tmp/ccSHpINd.s:864 .text.I2C_WaitOnFlagUntilTimeout:00000000 $t + /tmp/ccSHpINd.s:869 .text.I2C_WaitOnFlagUntilTimeout:00000000 I2C_WaitOnFlagUntilTimeout + /tmp/ccSHpINd.s:981 .text.I2C_RequestMemoryWrite:00000000 $t + /tmp/ccSHpINd.s:986 .text.I2C_RequestMemoryWrite:00000000 I2C_RequestMemoryWrite + /tmp/ccSHpINd.s:1105 .text.I2C_RequestMemoryWrite:00000078 $d + /tmp/ccSHpINd.s:1110 .text.I2C_RequestMemoryRead:00000000 $t + /tmp/ccSHpINd.s:1115 .text.I2C_RequestMemoryRead:00000000 I2C_RequestMemoryRead + /tmp/ccSHpINd.s:1234 .text.I2C_RequestMemoryRead:00000074 $d + /tmp/ccSHpINd.s:1239 .text.I2C_WaitOnSTOPFlagUntilTimeout:00000000 $t + /tmp/ccSHpINd.s:1244 .text.I2C_WaitOnSTOPFlagUntilTimeout:00000000 I2C_WaitOnSTOPFlagUntilTimeout + /tmp/ccSHpINd.s:1342 .text.I2C_WaitOnRXNEFlagUntilTimeout:00000000 $t + /tmp/ccSHpINd.s:1347 .text.I2C_WaitOnRXNEFlagUntilTimeout:00000000 I2C_WaitOnRXNEFlagUntilTimeout + /tmp/ccSHpINd.s:1512 .text.HAL_I2C_MspInit:00000000 $t + /tmp/ccSHpINd.s:1518 .text.HAL_I2C_MspInit:00000000 HAL_I2C_MspInit + /tmp/ccSHpINd.s:1533 .text.HAL_I2C_Init:00000000 $t + /tmp/ccSHpINd.s:1539 .text.HAL_I2C_Init:00000000 HAL_I2C_Init + /tmp/ccSHpINd.s:1734 .text.HAL_I2C_Init:000000c4 $d + /tmp/ccSHpINd.s:1739 .text.HAL_I2C_MspDeInit:00000000 $t + /tmp/ccSHpINd.s:1745 .text.HAL_I2C_MspDeInit:00000000 HAL_I2C_MspDeInit + /tmp/ccSHpINd.s:1760 .text.HAL_I2C_DeInit:00000000 $t + /tmp/ccSHpINd.s:1766 .text.HAL_I2C_DeInit:00000000 HAL_I2C_DeInit + /tmp/ccSHpINd.s:1831 .text.HAL_I2C_Master_Transmit:00000000 $t + /tmp/ccSHpINd.s:1837 .text.HAL_I2C_Master_Transmit:00000000 HAL_I2C_Master_Transmit + /tmp/ccSHpINd.s:2197 .text.HAL_I2C_Master_Transmit:000001a0 $d + /tmp/ccSHpINd.s:2202 .text.HAL_I2C_Master_Receive:00000000 $t + /tmp/ccSHpINd.s:2208 .text.HAL_I2C_Master_Receive:00000000 HAL_I2C_Master_Receive + /tmp/ccSHpINd.s:2517 .text.HAL_I2C_Master_Receive:00000178 $d + /tmp/ccSHpINd.s:2522 .text.HAL_I2C_Slave_Transmit:00000000 $t + /tmp/ccSHpINd.s:2528 .text.HAL_I2C_Slave_Transmit:00000000 HAL_I2C_Slave_Transmit + /tmp/ccSHpINd.s:2980 .text.HAL_I2C_Slave_Receive:00000000 $t + /tmp/ccSHpINd.s:2986 .text.HAL_I2C_Slave_Receive:00000000 HAL_I2C_Slave_Receive + /tmp/ccSHpINd.s:3337 .text.HAL_I2C_Master_Transmit_IT:00000000 $t + /tmp/ccSHpINd.s:3343 .text.HAL_I2C_Master_Transmit_IT:00000000 HAL_I2C_Master_Transmit_IT + /tmp/ccSHpINd.s:3542 .text.HAL_I2C_Master_Transmit_IT:000000bc $d + /tmp/ccSHpINd.s:12303 .text.I2C_Master_ISR_IT:00000000 I2C_Master_ISR_IT + /tmp/ccSHpINd.s:3549 .text.HAL_I2C_Master_Receive_IT:00000000 $t + /tmp/ccSHpINd.s:3555 .text.HAL_I2C_Master_Receive_IT:00000000 HAL_I2C_Master_Receive_IT + ARM GAS /tmp/ccSHpINd.s page 478 + + + /tmp/ccSHpINd.s:3708 .text.HAL_I2C_Master_Receive_IT:0000008c $d + /tmp/ccSHpINd.s:3715 .text.HAL_I2C_Slave_Transmit_IT:00000000 $t + /tmp/ccSHpINd.s:3721 .text.HAL_I2C_Slave_Transmit_IT:00000000 HAL_I2C_Slave_Transmit_IT + /tmp/ccSHpINd.s:3865 .text.HAL_I2C_Slave_Transmit_IT:00000084 $d + /tmp/ccSHpINd.s:11709 .text.I2C_Slave_ISR_IT:00000000 I2C_Slave_ISR_IT + /tmp/ccSHpINd.s:3871 .text.HAL_I2C_Slave_Receive_IT:00000000 $t + /tmp/ccSHpINd.s:3877 .text.HAL_I2C_Slave_Receive_IT:00000000 HAL_I2C_Slave_Receive_IT + /tmp/ccSHpINd.s:3980 .text.HAL_I2C_Slave_Receive_IT:0000005c $d + /tmp/ccSHpINd.s:3986 .text.HAL_I2C_Master_Transmit_DMA:00000000 $t + /tmp/ccSHpINd.s:3992 .text.HAL_I2C_Master_Transmit_DMA:00000000 HAL_I2C_Master_Transmit_DMA + /tmp/ccSHpINd.s:4340 .text.HAL_I2C_Master_Transmit_DMA:0000015c $d + /tmp/ccSHpINd.s:13842 .text.I2C_DMAMasterTransmitCplt:00000000 I2C_DMAMasterTransmitCplt + /tmp/ccSHpINd.s:13744 .text.I2C_DMAError:00000000 I2C_DMAError + /tmp/ccSHpINd.s:4350 .text.HAL_I2C_Master_Receive_DMA:00000000 $t + /tmp/ccSHpINd.s:4356 .text.HAL_I2C_Master_Receive_DMA:00000000 HAL_I2C_Master_Receive_DMA + /tmp/ccSHpINd.s:4658 .text.HAL_I2C_Master_Receive_DMA:00000138 $d + /tmp/ccSHpINd.s:13950 .text.I2C_DMAMasterReceiveCplt:00000000 I2C_DMAMasterReceiveCplt + /tmp/ccSHpINd.s:4668 .text.HAL_I2C_Slave_Transmit_DMA:00000000 $t + /tmp/ccSHpINd.s:4674 .text.HAL_I2C_Slave_Transmit_DMA:00000000 HAL_I2C_Slave_Transmit_DMA + /tmp/ccSHpINd.s:4979 .text.HAL_I2C_Slave_Transmit_DMA:00000130 $d + /tmp/ccSHpINd.s:10399 .text.I2C_DMASlaveTransmitCplt:00000000 I2C_DMASlaveTransmitCplt + /tmp/ccSHpINd.s:4987 .text.HAL_I2C_Slave_Receive_DMA:00000000 $t + /tmp/ccSHpINd.s:4993 .text.HAL_I2C_Slave_Receive_DMA:00000000 HAL_I2C_Slave_Receive_DMA + /tmp/ccSHpINd.s:5215 .text.HAL_I2C_Slave_Receive_DMA:000000e4 $d + /tmp/ccSHpINd.s:10456 .text.I2C_DMASlaveReceiveCplt:00000000 I2C_DMASlaveReceiveCplt + /tmp/ccSHpINd.s:5223 .text.HAL_I2C_Mem_Write:00000000 $t + /tmp/ccSHpINd.s:5229 .text.HAL_I2C_Mem_Write:00000000 HAL_I2C_Mem_Write + /tmp/ccSHpINd.s:5587 .text.HAL_I2C_Mem_Read:00000000 $t + /tmp/ccSHpINd.s:5593 .text.HAL_I2C_Mem_Read:00000000 HAL_I2C_Mem_Read + /tmp/ccSHpINd.s:5951 .text.HAL_I2C_Mem_Read:000001ac $d + /tmp/ccSHpINd.s:5956 .text.HAL_I2C_Mem_Write_IT:00000000 $t + /tmp/ccSHpINd.s:5962 .text.HAL_I2C_Mem_Write_IT:00000000 HAL_I2C_Mem_Write_IT + /tmp/ccSHpINd.s:6139 .text.HAL_I2C_Mem_Write_IT:000000ac $d + /tmp/ccSHpINd.s:14070 .text.I2C_Mem_ISR_IT:00000000 I2C_Mem_ISR_IT + /tmp/ccSHpINd.s:6146 .text.HAL_I2C_Mem_Read_IT:00000000 $t + /tmp/ccSHpINd.s:6152 .text.HAL_I2C_Mem_Read_IT:00000000 HAL_I2C_Mem_Read_IT + /tmp/ccSHpINd.s:6326 .text.HAL_I2C_Mem_Read_IT:000000a8 $d + /tmp/ccSHpINd.s:6333 .text.HAL_I2C_Mem_Write_DMA:00000000 $t + /tmp/ccSHpINd.s:6339 .text.HAL_I2C_Mem_Write_DMA:00000000 HAL_I2C_Mem_Write_DMA + /tmp/ccSHpINd.s:6624 .text.HAL_I2C_Mem_Write_DMA:00000120 $d + /tmp/ccSHpINd.s:6633 .text.HAL_I2C_Mem_Read_DMA:00000000 $t + /tmp/ccSHpINd.s:6639 .text.HAL_I2C_Mem_Read_DMA:00000000 HAL_I2C_Mem_Read_DMA + /tmp/ccSHpINd.s:6926 .text.HAL_I2C_Mem_Read_DMA:00000120 $d + /tmp/ccSHpINd.s:6935 .text.HAL_I2C_IsDeviceReady:00000000 $t + /tmp/ccSHpINd.s:6941 .text.HAL_I2C_IsDeviceReady:00000000 HAL_I2C_IsDeviceReady + /tmp/ccSHpINd.s:7232 .text.HAL_I2C_IsDeviceReady:00000134 $d + /tmp/ccSHpINd.s:7238 .text.HAL_I2C_Master_Seq_Transmit_IT:00000000 $t + /tmp/ccSHpINd.s:7244 .text.HAL_I2C_Master_Seq_Transmit_IT:00000000 HAL_I2C_Master_Seq_Transmit_IT + /tmp/ccSHpINd.s:7511 .text.HAL_I2C_Master_Seq_Transmit_IT:00000104 $d + /tmp/ccSHpINd.s:7517 .text.HAL_I2C_Master_Seq_Transmit_DMA:00000000 $t + /tmp/ccSHpINd.s:7523 .text.HAL_I2C_Master_Seq_Transmit_DMA:00000000 HAL_I2C_Master_Seq_Transmit_DMA + /tmp/ccSHpINd.s:7945 .text.HAL_I2C_Master_Seq_Transmit_DMA:000001d0 $d + /tmp/ccSHpINd.s:7954 .text.HAL_I2C_Master_Seq_Receive_IT:00000000 $t + /tmp/ccSHpINd.s:7960 .text.HAL_I2C_Master_Seq_Receive_IT:00000000 HAL_I2C_Master_Seq_Receive_IT + /tmp/ccSHpINd.s:8148 .text.HAL_I2C_Master_Seq_Receive_IT:000000ac $d + /tmp/ccSHpINd.s:8154 .text.HAL_I2C_Master_Seq_Receive_DMA:00000000 $t + /tmp/ccSHpINd.s:8160 .text.HAL_I2C_Master_Seq_Receive_DMA:00000000 HAL_I2C_Master_Seq_Receive_DMA + ARM GAS /tmp/ccSHpINd.s page 479 + + + /tmp/ccSHpINd.s:8492 .text.HAL_I2C_Master_Seq_Receive_DMA:00000160 $d + /tmp/ccSHpINd.s:8501 .text.HAL_I2C_Slave_Seq_Transmit_IT:00000000 $t + /tmp/ccSHpINd.s:8507 .text.HAL_I2C_Slave_Seq_Transmit_IT:00000000 HAL_I2C_Slave_Seq_Transmit_IT + /tmp/ccSHpINd.s:8718 .text.HAL_I2C_Slave_Seq_Transmit_IT:000000dc $d + /tmp/ccSHpINd.s:14602 .text.I2C_DMAAbort:00000000 I2C_DMAAbort + /tmp/ccSHpINd.s:8724 .text.HAL_I2C_Slave_Seq_Transmit_DMA:00000000 $t + /tmp/ccSHpINd.s:8730 .text.HAL_I2C_Slave_Seq_Transmit_DMA:00000000 HAL_I2C_Slave_Seq_Transmit_DMA + /tmp/ccSHpINd.s:9120 .text.HAL_I2C_Slave_Seq_Transmit_DMA:0000019c $d + /tmp/ccSHpINd.s:9128 .text.HAL_I2C_Slave_Seq_Receive_IT:00000000 $t + /tmp/ccSHpINd.s:9134 .text.HAL_I2C_Slave_Seq_Receive_IT:00000000 HAL_I2C_Slave_Seq_Receive_IT + /tmp/ccSHpINd.s:9345 .text.HAL_I2C_Slave_Seq_Receive_IT:000000dc $d + /tmp/ccSHpINd.s:9351 .text.HAL_I2C_Slave_Seq_Receive_DMA:00000000 $t + /tmp/ccSHpINd.s:9357 .text.HAL_I2C_Slave_Seq_Receive_DMA:00000000 HAL_I2C_Slave_Seq_Receive_DMA + /tmp/ccSHpINd.s:9745 .text.HAL_I2C_Slave_Seq_Receive_DMA:0000019c $d + /tmp/ccSHpINd.s:9753 .text.HAL_I2C_EnableListen_IT:00000000 $t + /tmp/ccSHpINd.s:9759 .text.HAL_I2C_EnableListen_IT:00000000 HAL_I2C_EnableListen_IT + /tmp/ccSHpINd.s:9806 .text.HAL_I2C_EnableListen_IT:00000028 $d + /tmp/ccSHpINd.s:9811 .text.HAL_I2C_DisableListen_IT:00000000 $t + /tmp/ccSHpINd.s:9817 .text.HAL_I2C_DisableListen_IT:00000000 HAL_I2C_DisableListen_IT + /tmp/ccSHpINd.s:9883 .text.HAL_I2C_Master_Abort_IT:00000000 $t + /tmp/ccSHpINd.s:9889 .text.HAL_I2C_Master_Abort_IT:00000000 HAL_I2C_Master_Abort_IT + /tmp/ccSHpINd.s:10038 .text.HAL_I2C_Master_Abort_IT:00000084 $d + /tmp/ccSHpINd.s:10043 .text.HAL_I2C_EV_IRQHandler:00000000 $t + /tmp/ccSHpINd.s:10049 .text.HAL_I2C_EV_IRQHandler:00000000 HAL_I2C_EV_IRQHandler + /tmp/ccSHpINd.s:10087 .text.HAL_I2C_MasterTxCpltCallback:00000000 $t + /tmp/ccSHpINd.s:10093 .text.HAL_I2C_MasterTxCpltCallback:00000000 HAL_I2C_MasterTxCpltCallback + /tmp/ccSHpINd.s:10108 .text.HAL_I2C_MasterRxCpltCallback:00000000 $t + /tmp/ccSHpINd.s:10114 .text.HAL_I2C_MasterRxCpltCallback:00000000 HAL_I2C_MasterRxCpltCallback + /tmp/ccSHpINd.s:10129 .text.I2C_ITMasterSeqCplt:00000000 $t + /tmp/ccSHpINd.s:10134 .text.I2C_ITMasterSeqCplt:00000000 I2C_ITMasterSeqCplt + /tmp/ccSHpINd.s:10219 .text.HAL_I2C_SlaveTxCpltCallback:00000000 $t + /tmp/ccSHpINd.s:10225 .text.HAL_I2C_SlaveTxCpltCallback:00000000 HAL_I2C_SlaveTxCpltCallback + /tmp/ccSHpINd.s:10240 .text.HAL_I2C_SlaveRxCpltCallback:00000000 $t + /tmp/ccSHpINd.s:10246 .text.HAL_I2C_SlaveRxCpltCallback:00000000 HAL_I2C_SlaveRxCpltCallback + /tmp/ccSHpINd.s:10261 .text.I2C_ITSlaveSeqCplt:00000000 $t + /tmp/ccSHpINd.s:10266 .text.I2C_ITSlaveSeqCplt:00000000 I2C_ITSlaveSeqCplt + /tmp/ccSHpINd.s:10394 .text.I2C_DMASlaveTransmitCplt:00000000 $t + /tmp/ccSHpINd.s:10451 .text.I2C_DMASlaveReceiveCplt:00000000 $t + /tmp/ccSHpINd.s:10512 .text.HAL_I2C_AddrCallback:00000000 $t + /tmp/ccSHpINd.s:10518 .text.HAL_I2C_AddrCallback:00000000 HAL_I2C_AddrCallback + /tmp/ccSHpINd.s:10535 .text.I2C_ITAddrCplt:00000000 $t + /tmp/ccSHpINd.s:10540 .text.I2C_ITAddrCplt:00000000 I2C_ITAddrCplt + /tmp/ccSHpINd.s:10700 .text.HAL_I2C_ListenCpltCallback:00000000 $t + /tmp/ccSHpINd.s:10706 .text.HAL_I2C_ListenCpltCallback:00000000 HAL_I2C_ListenCpltCallback + /tmp/ccSHpINd.s:10721 .text.I2C_ITListenCplt:00000000 $t + /tmp/ccSHpINd.s:10726 .text.I2C_ITListenCplt:00000000 I2C_ITListenCplt + /tmp/ccSHpINd.s:10830 .text.I2C_ITListenCplt:00000064 $d + /tmp/ccSHpINd.s:10835 .text.HAL_I2C_MemTxCpltCallback:00000000 $t + /tmp/ccSHpINd.s:10841 .text.HAL_I2C_MemTxCpltCallback:00000000 HAL_I2C_MemTxCpltCallback + /tmp/ccSHpINd.s:10856 .text.HAL_I2C_MemRxCpltCallback:00000000 $t + /tmp/ccSHpINd.s:10862 .text.HAL_I2C_MemRxCpltCallback:00000000 HAL_I2C_MemRxCpltCallback + /tmp/ccSHpINd.s:10877 .text.HAL_I2C_ErrorCallback:00000000 $t + /tmp/ccSHpINd.s:10883 .text.HAL_I2C_ErrorCallback:00000000 HAL_I2C_ErrorCallback + /tmp/ccSHpINd.s:10898 .text.HAL_I2C_AbortCpltCallback:00000000 $t + /tmp/ccSHpINd.s:10904 .text.HAL_I2C_AbortCpltCallback:00000000 HAL_I2C_AbortCpltCallback + /tmp/ccSHpINd.s:10919 .text.I2C_TreatErrorCallback:00000000 $t + /tmp/ccSHpINd.s:10924 .text.I2C_TreatErrorCallback:00000000 I2C_TreatErrorCallback + ARM GAS /tmp/ccSHpINd.s page 480 + + + /tmp/ccSHpINd.s:10981 .text.I2C_ITError:00000000 $t + /tmp/ccSHpINd.s:10986 .text.I2C_ITError:00000000 I2C_ITError + /tmp/ccSHpINd.s:11264 .text.I2C_ITError:00000124 $d + /tmp/ccSHpINd.s:11271 .text.I2C_ITSlaveCplt:00000000 $t + /tmp/ccSHpINd.s:11276 .text.I2C_ITSlaveCplt:00000000 I2C_ITSlaveCplt + /tmp/ccSHpINd.s:11323 .text.I2C_ITSlaveCplt:0000001e $d + /tmp/ccSHpINd.s:11333 .text.I2C_ITSlaveCplt:00000028 $t + /tmp/ccSHpINd.s:11699 .text.I2C_ITSlaveCplt:000001ec $d + /tmp/ccSHpINd.s:11704 .text.I2C_Slave_ISR_IT:00000000 $t + /tmp/ccSHpINd.s:12021 .text.I2C_ITMasterCplt:00000000 $t + /tmp/ccSHpINd.s:12026 .text.I2C_ITMasterCplt:00000000 I2C_ITMasterCplt + /tmp/ccSHpINd.s:12298 .text.I2C_Master_ISR_IT:00000000 $t + /tmp/ccSHpINd.s:12702 .text.I2C_Mem_ISR_DMA:00000000 $t + /tmp/ccSHpINd.s:13105 .text.I2C_Mem_ISR_DMA:000001c8 $d + /tmp/ccSHpINd.s:13111 .text.I2C_Slave_ISR_DMA:00000000 $t + /tmp/ccSHpINd.s:13254 .text.I2C_Slave_ISR_DMA:00000096 $d + /tmp/ccSHpINd.s:13265 .text.I2C_Slave_ISR_DMA:000000a0 $t + /tmp/ccSHpINd.s:13411 .text.I2C_Master_ISR_DMA:00000000 $t + /tmp/ccSHpINd.s:13739 .text.I2C_DMAError:00000000 $t + /tmp/ccSHpINd.s:13837 .text.I2C_DMAMasterTransmitCplt:00000000 $t + /tmp/ccSHpINd.s:13945 .text.I2C_DMAMasterReceiveCplt:00000000 $t + /tmp/ccSHpINd.s:14065 .text.I2C_Mem_ISR_IT:00000000 $t + /tmp/ccSHpINd.s:14484 .text.I2C_Mem_ISR_IT:000001b8 $d + /tmp/ccSHpINd.s:14490 .text.HAL_I2C_ER_IRQHandler:00000000 $t + /tmp/ccSHpINd.s:14496 .text.HAL_I2C_ER_IRQHandler:00000000 HAL_I2C_ER_IRQHandler + /tmp/ccSHpINd.s:14597 .text.I2C_DMAAbort:00000000 $t + /tmp/ccSHpINd.s:14648 .text.HAL_I2C_GetState:00000000 $t + /tmp/ccSHpINd.s:14654 .text.HAL_I2C_GetState:00000000 HAL_I2C_GetState + /tmp/ccSHpINd.s:14672 .text.HAL_I2C_GetMode:00000000 $t + /tmp/ccSHpINd.s:14678 .text.HAL_I2C_GetMode:00000000 HAL_I2C_GetMode + /tmp/ccSHpINd.s:14696 .text.HAL_I2C_GetError:00000000 $t + /tmp/ccSHpINd.s:14702 .text.HAL_I2C_GetError:00000000 HAL_I2C_GetError + +UNDEFINED SYMBOLS +HAL_GetTick +HAL_DMA_Start_IT +HAL_DMA_Abort_IT +HAL_DMA_GetState +HAL_DMA_GetError diff --git a/build/stm32f7xx_hal_i2c.o b/build/stm32f7xx_hal_i2c.o new file mode 100644 index 0000000000000000000000000000000000000000..e29b98a98fd928c006b8564c653324462f49876c GIT binary patch literal 148608 zcmeFa33!#&wLkp6=NyudgycXNLc(xz5-NP~Adjo;oMn!9qQWmPRNo^x~M@OTuzL*#dGyzf41e&05$ zxNoP8ajQB%3-%QWsyg=t!=uvTkx_+hRh^Mwe*5;~k2|V5*9AZCV4DHmw#h`Bta!z! z?6}>U*_v0C)wpuz_Tmqv?Oyyg20QUv5&T<+V;f?Q-#fl;|FrU8XKAps%#MFn9B8jB zw%RFM0CiQJ)3Z?@33QeQN=JuL-WQ}KecHmKaxi8t#th4t(LKQ+M{TbD6eDd9@^@YE z6Z}Sk)S)8yQODEE9x4mPpI)}@^U?EzaagDL>86!4=XYAGo^JZGv zurr)?NxV<>y6SNB^~Ki6Z&eq!-nKN{8Oa^jcEgj8?mcka7x4pM{_DWTk20(WD(zRT zBR*{_YMs*>*cYq3Wq)P)8(Xhl8itgicw}<^Q+9D+$EqF0t#>ZXLl3XDIV}g5?t87e zGm>T>_J@wStyTMCRdX9z7pwlTBX>sxBUg8Z((Dn@)|;2+?TcO7D_-4cr_J9NJG*VM zJpz>Prh$@?7HtJ>vC^zdOF#>x6@zA-^E&t<)$B8hcq#5Yu&Q|9wd0HT0e9NL`o`uJ zq}d>mQ1(~f)%yYH{+Reg2!pz2}OZ|#q) zD{Ec9bmE>+C>xfuil3}JtZh#9*y>WzBl6^981EBf{odAQT7S%6+R7l?L_~no=FPU{ zGV*e0w_3DY4eeG#I~{rFhx@OvBmYD+((9LR4#C$$t26HIy*o2Lu~mDv(r%M5 zvTC}2hkZm2G&}vPt3SJ=$@=m5YAYHm(z*wB1UA!Vu=<{S%wn%qIsC3I{?cJbJ_7s| z(9vN%Wksx5^4R$p+bTYkkt_cFkuk30(NMb+mHpyQuF&V*?K>nM;nzKg@lV=1Iu6C3 z`w=fW@TN5)AM?1mg?;QQ++1nBdex4L%{&O@W~PV@cxQyl5y~CYcIK0w9jz^_;Yu0F zeI;%k@kgwWEQND_ALkqmVVvSt&Y7atxm_ZCZX+T*;zhVU;*pNh>is*pK3b*Uj)x&J zS0SscI$k2PA=;XUUhH6AV{>a1xs}a%i!l#di}zVoH#ff5YL^`yzXvr{`$AFcM)uUJ z+FCcbxUL$j%QTIBtF)r?o>-AsEi7vYeg4e;lGvvGqt`VzH?O^O>w&UiuN^2ZUd?$G zUAt#XwDq?AR`|xIre*fHrlzK~H*K{i-L$o7b#yIpbhSNh+HC8_7q=c`=3ah#^IEpH zR=v|PDWN8-ovov*tzynvYn9iA<633of@y$)-u_xcT zwRv^%TH@l>?9Ce89=FQgZnJ*mpW_>!R85|J?LgESFSg2&@VO3eoQx+AJrb?C|3ljNffhv1_dV$p;6DC@Pl>P`DgH%>Dvprc#9vGHV~ z`)zzM>yJyY{(P*SCogMWRp^&&!x2e^Zz@xFLBoAp|Uo- zu{Baw(YXhf&&B+(M(00ejaq=Si_VgFV>afU&egPPoekVqE3vOOw|u7wb0OB;Y*q-Y z3&l8tSjSC@Tep^BAIUJQxm7w9Hp;*%_FikCtkTqCcOUD_wG-MjLQjc%d$3h{d{SIL zvVZih;a^?%b@tu^Q;0G8u6H{yXIE9V*paK-yPE}%J1Yw$)Di8-+3krk=3@n?gqu_F zp3-hsCSUtnAI*-;k>0{a-w(IY<4r3*}QgaGsvqcFX>X8vBUZaeD-Iv6>?MPOAyyx3b0>aYjp1Q}gQKbKh$k zKG)fIO5A;C#M+_T`dx5&4|`7DENk71Tg^<9{%sSdrPaaBq-0+J_5rY$IC5cK<5`F6*~B(ozmCQUNY}3-IXy)1 z%ayCDCDht1=a=TjX-$=@tJVfr_nrH6Q{TB&%|ThgGU8SV*1d{ZpV>Cg2a)RV&R}aM zcGxQHuvJY}W{0g>9YhocS9d^`l`{#BJQE*vq$xJi6vb7Rs9%@WUiRYHMSjl>bT+9r^i>nxYfC%QKIPDI}3Quv9KpqlsoIMoIG*w%xmo1 z-VeHk%?|$?x2^Kq&i)k9wQ?ma{7+c;AO3h}%rhbGiIQ!89c*6IdJSzpzoPSM+B|HJ zvN~7C>>|h%j^cM(IE>%QuvN5JY(51xpW@p5FlP>&U$oX5H9!8|^1^LL&wj1>z2!&E zey!!tuxb{5v(6}jRZGUUAJnE*u1#O*!KUTyYERC&L$#=NP>VV<7S@szpwFVtJf#tt zFkgwBSyIutHpX+lo9zRe6||}+l_+lo?bqFTPZB{^m6>R?3Q`F8}ryg#AQ}ndrNGM zI^2@Fx7LV}j&w@FW2TWl4t+ty@fSd_qU;# zTSLk*v*e^&)s}XfRfhRgIzAq0y=v(|>~&Lk*2C#yQrv&GsBq5~BUh*0y#(jhf!ON? zVz2vii+#l4cwXieO)qYZo{?uP@0>QRq;qMOc()n1y0rEew_e^fzw^NO;xpdEIvCiT zVo#B0e>@8%%011Md#o$>BqR4kBX?BJM4sGTrOtPy?gy#)9MgYBwcRsnYMI~fLFP`m z59Cx2ugfpoOc(fwCjz zEN34%#+9FY;t}z~Wlt{(Yv$AY@%2RCU*%+7_r%V%W1QBWp{iRyCctIqpO`0SXSUUJ2F zc`p;r9U8ZO%%@3_qH=jxvhvCC@@!pN<62dzaXEj{a)~8xe`77gk z#xF{7#{ZycoO{AAbZ%AOD_;BCEsyQBF2!0p<~ZyN-ZR@r_Ls&uZ}qut#$K#%(5{ST<;`)AQgq>*mSTd_Uvt70K(X zzSm)|FLhYO?{;L&ZSP3kzyTm zZmzFxiFA86IHf(g&O7rT-|l##u^4de(~~t zh}bO}v7?41cxdpeA1vdJFg_vXG)|pcWN9^bdp@7~VA-pP(~geN+`mABzXSHly#S)S z&$C0-1FAFbaHQtbkQ_HM@9gF_&OPAWrkSqnlN{NDQRfR%b6gSXAlVJq%5q zry(yU?Zb}Mox3~V{7RJI{*{zqbG{9wt*y>dtF*MSEf;UnvBSvwgHRiv`SSF(pq)?9 zbfv;7fj4i*V|U@Rnp>~}zp-_6S!sNf%rVX;KAUT9;nQQi34f<)$!dE4FHMDzo8Jor zJ2Qee;#o`VxIjE>O9obQjTmo~((1x?N0Z{#g4TZ6*?u1{XpQc(DhnF9n?D=Rm{V|u zd5%*0RJ?t8@XXt0K8baIzdT{%eN$7SjuoA|Vty^>$5kT>?-o@jPYOr7O7Kw6QDr9` zlAd#*Cr@c7#b?Rtgx@aD)sCrl&S_R@eLVTegZpf4#8UUn(bB~t+vAAS(U1DD6wP{Vh&kf81f?sQ|phrvgbS(N{giW1xq49EErs{qMzNTVgyqqc9$Ab4PHj zsqyGoQ{&OG=2OO+-#i}OSvTSl%sOX$Cq{p6V$_MpV@+g^E^9a>jk!j0_B6z+Wv!dh z6}X*;%Z_f-H#7LcOV-+QbCTEo zi^>Y{G>juf%L?O-66Jm69&W9&qlqWQht}uQ=FjjhNA_y)2v(OOTn~wP~VZlY8B=C@y_Y)rO*D|s>U}#*@4b~ z^}3^VH||*Pw5E6dEB!xP1EZpCtM|M(U_fVDZn*8T753Q6S}t1=81-(ORdiWPM&#AS zuw2+VA^eGN$~E$2t@XY_`b|=e_sz#n*xRyb??HH0jQeAA1kZG*Md;J2=DwYw+&oBp z^0F#?{h)8gf@|xy@QqlNxyw|o=JVeWp8wAJENE6yKE+yPtCB`>yP`e%aMazU<=FEkAmKSc}4B$Ju0f?5q@e!S& zUWv~`i`R}v#1!MC=iGjoE8OB(XaK&3%ZuaN)!eXoyK^#bB)Vc&xaX@XeCa1&wZi6= z<;~5_EASSm?Y(7rn0bp0f3$3c@rebEc-~N{8)d&_gmK1S(?O52M6Sy___TAQ(TOvc zyWnkcN2{AV9>;zD$u?*G{8h&wjJVxMqy6je7VKV>(9!F0tQ>d_aOAyhi&rSe#ttXv z=$GgAn`1ngg{OQPSBX08$J}7FB~r1&U|w;4>{{lW1aKDuXGM8md~+Cx^UK45ZGBsq+4(aDJ^OP;EQcW#FMADjEpzK$@o-;+Z7jwJ0jtM;XDxZ1zc z!S!S~qzL5>5h+$}Nsg4RablG{(Z(?!kE;#0p_dHNDqkq^A*`2 z%v%M1ZEefW#&~1wh4IxjWgmt49m*Yj{UeSoVJSHw={fmqZYllgWrgL)}dc?>WY*ee{Y!;@xIHs z8P;>Y^wd^sFkf(T=(H{knh3nCqr&WBKj^T^j@x(P!<6l~edj++Id0|`Q?32Lf9bw6 zAAWZkPaL7PlUpmXmz~_$Y~uQKw~v!MoE7U-ME1&=j<4RtTX?=nN%m7%=2D@|rF=wM z^vpY&^sS8J1HL2Y`sVl`A}2-F=3~stn0UM*Hy1rsnEWE-Be`#(*GTT`Ci-9LaL#1T z_Z;f6W5o*x%0|2<-%{flz)-RHpI10<#%S|v%-b2Zah|g2T!`Xruy?<_N4(N*yyEo1 zuRxt1-ol%Ee8G%2_j!%ixpw$oK|cBFJ91|I zNo0J-lM%i6C4AE-;bie5?h|;1$7f?I#GZd=Q;Rq&{IoWnEe@Bn z#i;T!Nu%&Z{99&?DlN-!_n1txG9K2>UFGj4@+0kB;rE(4jVS%i!+ZMTW@m-OR}?6H zX?B`k?cPohY||)Rxl`MH32W_l*Qa~BiTUBMQ7m^UY*dkJPBr*@8+Y%733K= zil4%KtiUcy%?8W7y4GDkwzMU$9uJt+W0Tu{1KLM&*UP-U-OSq`Nd!)O^vdP;EWb!1 zW7QUG1iogHd~k<7f~#_%)QXSTF>$9gVlSTN{0;It--?}!;P(%|Cjc@O$XWgxZ@3#9j_o>eC9U1d*i9Y zTeV;9=z0HpUiQBUvj2^h2${RBcySZ7`8)Nwxy;Qkvlf4eqqMc>Y>T&pd-lk?%9@}%I3N%#q5q&I}X8%o~>dLWQ~R}PS!@$EiD zY2Rfj(5pNPDAa2qQAV%N(k&}E9Y29F`BTv@(DB=~?GmY5BqbuzRONtn{inD|nCHcMW-pt&EwFIk?Fwhtg}Nq5fW{oRN_Z zErRzsrS#)TN; ztl&*fIh65oFEqQ^DQ9FHgXY0ooN{)?YqY?RoN_qhZpwYDQ|_NWyB>1<*eU0y&!$|r zIprZ4MnTxLqf9ZB zGdGOlF{YT2^Bg)#n_`ODIp0R_X~&sjIA;U2Nvkx){yDcH{?cZcVt&r&&?{|@DGtdA zLBF))O)&yi6zfc}Bxe}MU0{l(IaOpn#S{;>f|EE>W1z)TIBki&80uuL0m;g`6te|3 zf@*=RIUonKK1TF~vfhR5dRf7C4t8c>3~EAbmAe%_YfQT)T!;FcwVKf#YH(Eu;+VC@l-1u;)LxR>Sr&3BzgP+?HmXf4xNlb@N61+{JLeKIPc_AGPClecpJs~va~d&z zx)&c$AO_NBnc5*%a5=f>2Cu~UCaBZTv`>UcSzmx;W!(#vB3bl9N!CB1eo$y==&TC-Hp1&@kbYsXAG!#!AE(!w?Hkx@fBaZkLm+ZE>ua=*WSxcI z3M=@1%6WURmF>uxTL;F5^zGrF!`Tuo=}!!2-iemAQ!0Uy7r1HbegOXN*q|&$*wLf6f%kb521Y>AxQMnshZG=dVyR z{ddDJ0aKuOV$N)~eZdr`NR+0xnJBH0C{2H9ShGkqO=f2L%fs%JVx`1V`k%}|({pyx z@UNNTteh*T!W*VIFJ}i;c*_)P5I|g%!=c5{p}#CsFG0XO`C&BX@dx!A(JUO=fx6&k zOy2abgQN_22ZVw4Mn>=Tfq^!e?Mw`qN4-!}3fre$9LSTN?eR{H^y>Y9ky4~x>M$Pf zFrsE6C(c@Q&Y5n1$E_J;e~H-1cqvmy&Hpt-vA;XC4?41}VSvEJmc0?|gI_^Rpk@jS zHdUt7`Awvj8~&As|0|cjd}z7y7t|`_ar8PGN-F$5j9`x&D&am0q=_WwPlQDF%R^L# z^`KCO6QF>~@bZu&{e8YXWGegI3iug7`~1@o>2n_l?*ptMF*LWIFnvw|Wf3&A-*r2E zV#s*Y=}Nc(oR#eKYA{_1D7ckYdt%7K#UO42;b9WFw1apC{q;5ouamfh13fup6p6i| zNH4(9bI)99*-xuXWgv_KSi`2`$39|6fw&cUD<2(9MU}k=#wrklA2DPaxK~n#&-54WRHOECP193X+51$^aDRQjf7p zJPw3!k(i0Vw8ts&QV`A~@kow7UWvOw_!Wu#moV%JLk4kGcprpz!0>S(GRlUpa57h$ zOyo^udSOv1vTFk8B0p?7#cwb4?C=n%A&!3qe4%z|FPuj^l!96UP&>32ou5!0SxaC4vH6PK!#DE!W7xHf%B2C3w#gsVb6<$eS)0^ z>U(H!XCZJ^uqRY7IoBbsRj?;iuu&k4AW;N+QU#j}!c0K4)C_H-FK_tsWcc$T;~3Oa zMr+s_&Yc^5ax{Xv6n)q?yK>y9a;ydQ8i2}iqss9x2tOrJNTs60R}pkO(o0c}pCPmTg%EQz~N0I`+F zzmq_yCs9IsS>aT2-T=b2B#Ok#3MJmRfberb^l)%c;>j45mZQxa$6*^8&SgX-9x{U- zoLi_%Ndd@hXm8&_Y1tF1j^G;mIr4h}g)-+(C>%%?hGB#ufZ_RQcO(MV8uB7cWEY$6 zrh_sT^>!a@71~{~c6Sn}wSdAWX`2y+vKHMB!Uhs$jKg${cR+XxFg$|JI>8;OMCK-U zc0ez?0t4r9ilmu=M}p-uG_ucj2Tm)TNIeE3Q2GIMjNUrNG!Tv@@glI>nJP^)2&V&v zm!Pvx^YAldIJ^99f!b;rD3_t$?hOm7a=$G&hGRSk>VE)qj28;TR(nDC8z4Fb?YR8M zF_st984+tZXBs!PC?^p${LIe+EhDX_t*>1Lp7tW)iqcsqPmQOrq{jfw~Q#V_c$R zj6_hB0ESOMJJE0|GSu*okkM5J8b)WKg4X%eUlD+HB8yCo%O1$6z=ps{VK4FN&aIHK zs9WKZ0<#rbLmq{Ac7@>_gWir|tWpY{mlXxyVo)yz^&~))L48A!WnBmk4BGqe!OyKx zUzUG~5aje~K~*9dA2+baor5(%$}x5CC*eLU3OdBj!H08*--G%bpn#`y@K3%3{iS2d z9RRWLPHaQ=Q-kw)_N)c*ctGKLG_(J6uz2TtAe;?|jz+WlP*H#ZT(j8Yt>LGlf@hoI z=ODw=Q1oiUI@8Y@%nHV===G?gA5U?stmq4%(TLymXv6n`CY|zOgLGPe47q;faYdqr zrt%;-Z{rMKV{F0z-U!j{L46&YtQkC(HhC7*U4Vku>83S1^cL%%&1bb_~I-wKd6mwSpv7a;G)_gf}%?Gs#paX8rKaK<51H$cqLY{f; zNAktqUx2WW#D8Ug_^1;5AnrKxb>2Lt#3Mi`BT;<#c)s{>76=u9Xt`11zeI`JV3rN* zb1KpLueq98(J+L57%F|@qtVv1KmdAR%?oA)(74nP2RTIg^HdVyk+DML34&|?c@SVF zYB<&mx5kQ|4;p9qNj}7)I`&@S`Q9s!Lb-RaVtk$!1XILT za1M#$ypc+L4umHGC0EeRhvn--q8nF4ml$t+2LqabigF95H7@eet}?E?UTC%USSxyy zA^nFTjkBWfg7iAHd(_u513L98wyaWqg!D`&o#{7 zcWGoEXGLPDNbuSgtoZgOBU=M%AH-mG-vN$nn+8qb9B%{l*A%1F^!!p%&(U$Hpv5}e z3f&SYvxV;bGDqq_qbXez?WKuk7%?`o78A%W!}h4bGh>i!21kK90-(V&W00Ju?gHUQ zfWmwXWzQUxwHWRH0>XPFHewO7XAR0e6GRK~yPw249B#G}CxJKtQ20GY)Ep(A0YWn% zx(ux*L#=20D&QRL+4wc7!L+tw_}gQ{{*NSfbL^HCn-jv%Jm?fY>?(9n8o;B*?VH{!MzK#lj-z z6llDu5XF@~h4F$F(@PS}$2mxqPxCkQ?sn1XsHgeXB-CfbQkm~G)0ZoN*N-*q9du$J z?=xQsf-w`JZSNQit>mzO{J>d!6f_3Z(Ey#9#}AY{(Gn2mk+>OFu}>Iy6!l+#SQ!t{ z?YCy2EOTeU(~W?_y^PXYCH?_~r%9AOxo)8B$s?fDP(YN9=UHSCL{aIj={IKT_2I5eo?Lk+8(AwZr{f+h4>^kWb3IjsSV%h2B5KE!d_fC01Vw6{Th0-#PCFklh= z^AfloC8vb(zyU{-`0`L(nE-{?qhRL`kPYUVVU~3TpzwEnKpd=|d<2B8fav+)q)uV< z<;Yme8?AU*@o zHR6*zG186^IIjWJNS`Wk_DEdq08vNz?+RKzj++&tN=79D0;0F6$%(4{%6!A*wydbb8Ezu|tsr8%p?eW>Yb>Jj#z;Z1v7p1xSI zkU{_oyboPygpbRcz(T(=9CiVCr}7a3euSODmGQ8=0rE-?ba`RIrbiYzO%KbP%BIJn z*)eQ7!sc^ryD)E{ydCs6;-efLuQ0EIjat#5g^fnqqbcP6etPW+fW%R5Km&cgw7=gZ zp8N2+XQVxknGcg#d52Th5BnYMvX12Jel>~pFD~n=zFtqy0_*chth`5Suh08fM^eG< zNvyngDC_oqlU)I3(SY|QvGPu*toQXhN?8X#2z!IEYB5x|YX`s1A@1vU`k5@&LFuD< zBXdhqN4!aDN4NBIUWbje`(%Rk$|P3a_LTKXA1j}H+UF&)@~)?>=k+_*)#M_c3eQMl zEq7VZa9IztEn0nSKh7g;-GCe5WBVbllCqwT?I-uc$3cAYm~hNMEmW&`Z^SO>uSKSz;1H~&>`RM zJC!yZa|8$kx$eE)_jr1CCkQ_W6t+{@_P+AwYV;V)2Y@_`@ydJk^3_Sve1KluWuk2%z6u>}2l^d!FEaQgI}R+pwvqC-#Qr?$`oqBcR}HhTYz9 z{WeU!>p-}iM0vluH{4A3ya~b|N#vIR_Ge+a5sod#>;S0lpNDh!>gZDt_5ccZ2f+D7 zSl;ms8H=3<5S?HQaw zg$zBO*sC?#zL^rQ_1WWnw5@?K_Kyy8?6Ed14n z$HySNPomi4`mj7+n9Se-s6B2}dprTcc7Qx+Vw9bTQ4@uX-i972`#D{!Hld2GuJu>Z z0?(p?ibKP`Sy1NX+(eJJVNCnpQb)s=b7wGIKL>R$Ks9_hw}BcKjmJS2pc=lM+d>W3 zf^aE`qTwsK^2Q(t|9u3aYWP~NczhR#zXYhqU(Xefe+t3}fGDR96*vK+_|&#zR`hOE z(c?{0Rm;aBuE#I(vtw2sn#Zje?XfZh)z9|XgC36_1>z5JB+?mhcCO5TYEUZyYLByX zWd@uDLJNuF@w0Pf2K)+y$4C@=oRcdvpbsYaKS5M`oTv7<4#YJ8*WYLe=X$6LBq zIUc{*UquVJ9v@`~a-qy`b3Biqi|D@xW7_{1?P&Ph9P#)^pmqRswf${Q1D)IVTe!~v zRPEp9EM*wffp7weqW14{CX@3*5LS{XYX2^0&LtrJ0fgTI^t$*$jx2hggYY*J{{;^F z4@x{@B2))xY{YXUHf{jnT7W#HJRbqj458IPR+Q>9D845&K8Lg1)BoKr9}jx`D4-re zBahTB02`lra2h@CXR|A;Xay>`eZ1$d(Du%W6g$WBe8wji$%J)8w}dhn$UfI+@kb!% z&!L3<1-597sdIBAralLCFF-ARZjL;W8+;7r7(gw4ZcZyLz5s-|B#On)%aO-)KLg=D z62;=@<;v*9qLmkzlr8_m>#t=E`ocqi%@gVAaeI76YPJA?Jy z5x79CX2S3LU~U96jd!%4nc;Vd>E+x03S)I&`;CTeO&7Mhu7mx;40ey7nTMI(rk6x< z-FX5*aqh@wG#~48Xf|4%2Xoj5aKuoD9@|IOkDZ|I0H{Nc?IY{QUqE<+L~-b`ePsPO zb}AkU0MwyV`^ft76bL&=6o*djBkRZKAnXOGLo3uHLyyDz7Jxc*ni88pXdqF1SE#15i+xBONtf0^*qygM#+6aR51lang5+9dzTdAT)z1 z0-3#taK1*vs+stLD3SyI#Pt&mN7)4-=)FG63mY0^F$T3K@hm3BSf3?f^B}1A0@N7m zvm|VO55jXKiZRw_HBy^CGw}Y3M0uTaSJpTZuK@94fEwejteG^%4iFwCQH*g{)`{eN z3xwAIYK#q8VvJxluACqazZD#^0y-8bfuJcZ;5>xG1}ZPfy0d`=GuktJHsA(&IL5Q{ zdCC+U%*c{Q8|Q+$5}-Diku{t0t_R^J62%5HvQ8uMpCEifqS&B1tDMBMXIj>BfZCus zYX)s_KM41bC^o3hl6~p7AUp?%o`Yuea{!_^TBdvj7>R*1g@?!Yfg+z|dLG^mzK_tg zz2DXDlS~Qs@w2dG093nAG9}zk0il*e(e9H>3HK*J_!)_!-KUun?&Y&_#098!pJqz9 zF9D&6MA7ckObPcjAY28AVrLia-tDSg7w=t}TECa6UyDz_&4}QK(78SLXbdafYsr+a znf?XprvTNjC9|47Idcw{9f0cBl6eY=4}-9QMA7ez%p*vQ%*7{G0M+k|%u0H1F$mu# zQS>__Q{E7-2H`RiW!*d@b1@gw2SKm>xR8B;D~jXr z+F+&?!>Sj!2&8&@wyb)voxJ?!EB(

ATDcr-1J}OC;Kac#?A8f}EP7jr8xcyc|5; z*Hu?{Y2iLLbq=Y~JzEO_vk>j zlflM;$0V@HgBUfNqZWpbECDmW7WQn00byTsghg>$FO2p^Z*R&x1omF@K)jxZX9=k{ zdQaq`@+44a12m-G=slBx@;nH;Nt7w`M(|Mo> z`Xvb4NtBR!v$vem+d+7fLnHu5P?~sW;`VC!=S2 zLcQRrJQx*pUR zKx5#n-t!p)UxV;5i4p^6^_Eq4^?Y1D0lG1+>@6GPKSB5$5M6;0xG@gJ0MOp|mND`> zR3&T;&QrdQ97yy*h8O7-(5j>c#J{*=evl!5Q*bV*rvg;W4>D>fW??OE>i`w=gACdJ zw}bEyK*jtpL&QA14$o%+!(&FwC_P7^elPNxFI_}1`ED|$yl(~|+5(@vHIR1>y0!c9 zY9=#tfy#RmsMiB@W-iF6ITPb;2Vpabaw1!haR!y>T@MSAD7Idh@hx(025}QWF9M4) zWNHm)z~Kg>?%QOwzp)aLC}jkPtsk}MXR)Ek-qTHGu zSI*l&SOXY-ANrEB-M^5b1^)rBc56ZX@`;9`^8KKb%SsFKdk6M0)nC!Yf_gHX)y0Bi zxe;6+g0U{~S+E6i?S-WFi>?JPNtdVXLr=uBD}Wm7lJpa3tTiB9PNGECCFyc9d;x^# z0TE0l$8Fvl3*2zzp)*Eb3a#v^zR|Bk18Wh8HN4n_Z%C7c;s6MrlPJ<} zNRx%)v{UeS9-z{1Op}G;497FuwthZX??4-}zTsyLR!k`&Ghdr=o;u9G05ku@?Vo;Tb0T49T>f~NE3EL1 z>(xi*p`L@eGMS@K@<6cZr$K1l)XNL{eQ0|Ww6t4zvX&dBT?eJsh6DmR)BaKKyBLGOTJKh0fgTG)TU?jlAzxQ!p9`O0d?&qz2w`7!yB=4 z0t)AG^ZQOOSx0L?m;>;v&xt@S51;1KG_~~^b!0us&+1s;|6qmIy${ShV13`u>{&M& zfQ9%$&|0_NiuMPM18jF`Sk_X@GR8Fjoy&@kRSm7(M{5L)U8cbgt|RS=q)>?&uJL}Z zZrmN+WQLjPGV2F#j3svnPg8`)FENwtk3(K~`~Y2iA8xQunC^tf#~}%iUxT_6psUKq zp?O^CqKmQG0W@Yl4lQQPG=k7TqQuN6q4DH=5`=9e$~^oeB!8s%H3<6w8Z&;vIb5@r85 zJ=8=`k88$>2%w&B3{9Y?*MhK`MDcWEsOl0BUjX4Z0QGc}dU_uSpOPq_LN+ULL<>&* zfUfTU7M_;5#_G=f4;TlX>Ss1@uHZ%8rFI*p%X(sZ(=a`d%#`?T)u&+Na`Jovn``>$ z;l|bb66$^THJ`uvsU-bf1eds)n%M2)?}a`1d!#)Z?y;W_B!1bn6#eQqHqQsf@t7=M zHpQ_#*xQp>Z*f_-2h88FBZ`7Su&yzGU=PKuae&j|E&FxwYZR>s$k#S1>}!iGS0xYkv-gpYKrdkfImL5N95#X1#=2>7NqsX z4jWFx1H}^fVJe9D*98Vz!JJ81le3P=nw^I)&yKQ)dKm^77>A6kEHLysCd)=mdLJv8 zp~cyG6Jd@F5ZD3gmC)PtC9Fj+c0ao!^T(CKJ{bQRimPn^k`*Kn(jKpbdGU_J$E36&UAjy& zT@D4eYtevm5A$=+&Jz(F{^8eLZd-lru~037EF8>i(Hc+#nKxEKrl>=v`o;dPw4+;9 zmy!fA(QZVti4s&FnOK`pcUX!#N8VDE2KS0YrX;mSr>-@!mZh$R2@&vKnuDxu)e_rm% z4une<7)~Y9G3${_O6Q;qVTdjS_+@2zy;kE_64rq($uH7W)IubpN&rxo>}p!^MT7giPWMiI8Fko`>$z9`^WApo@`=0gSKIaZf61QgqL`mG8Ko`E zn%H$+Lf59+>6JR90912Uuww=c@dW_eI+5rHLLR$;_*NwoQNw^Wb^|dlwosbr7lur{ z3ji|FZUDK7{|Eq?=oLeDOvB+F1;Bz@U&2CWVPiwvh3kP{kZirj?uIv1l*9&9#!-r+ zpmFNK7HS)EJBjTF0!%Egk?bO(>m*x4MEz}Rk<%%7L2y$wa;E`6ru}}XS^TZnI!As+@xNSP=>JtDPdm#L^6 zwH`;p80<_r>O77F1NfzA1b2cIW<$|Mu!e{%ej_Jv$TF!Mo)ifjbzUC{Qur4vMhv8g z0BJHk&^WLK5n22bC4r;X<5;8}klUFZ+DjeL1=5Q<+ntpqVZl!5x!&tJL3)nD&H~nr zf>nbXNp_Rp&IO=CL)s!C(F)Lzh%6$Ie*Ep57pxtmjQDkvzyIl=Civ0i!sQBij6qZi z@Q=ZAxmFXg7k@R1k{nBNL>h$a3^AL-DNZjWJKgwwC7Tla_J@&lBSND)J&+v4KqJAH zN;;5bg#N(Lb0AQ$X7TH$G~|>+_G>OHNlTdDp36|3N*s1KQJU5ear*m3V!1}EiP($3 z8by=nQr7lhktnKDiNK~NWXO`bf3*mG1lE2)CJ2yo6D^_~_2i)4ur|BZ$oMV7^*WU} z4u3f^7>lR^;1`Q!b$<=foTO@&YXE3X#DV;+Q8bB~v$hALjX`yHQkp45lswm1E|Z>X zh}cVN5fW`u&fOx#taj`wD_04aATbg7yXzN2N-DuG&UQqX0E8WXJOLk$tTO^PqC zdrlLGNfeXp0wVV7cN5DeNH+_J*rUH1ElkP;*74lE1-xKJp8zwGa(KI|97&Yuo?5^y zDU4q;kBO)}++HL{P3kO#2r^Vv3ewE{_{|#v4d%@zX57)##4*ih6OTbBJ-HwX9+;Jg z>@X|QYRT3RT_@QFB5s}FC1SVTx&Y4xgtOM`Rh)3SQi-(J1w_{?l}LN_nGrNe47iH` z*bN>6`m<)=2TB(~>iBV{#!VfkMwwDkFDc+;fHMG;3!Wp2N%r3sk3GY@0G;;8bAXho z98{Q(Xq;plh-#Ed)TC6Rl}aVLT&ehV6Nk_c!oRYtH|8GpNghriSJ-Xt%N&M0XBE%{ z$uWRH9W%CAvzfL~E5w zv{AB@N|SFq9Y-#{9Kb)HS)Kxb(}^|${M9I$G!l3t05>y3kpjX=Hk|2FTEI1MsbuRY zv`Ts+(MF*rMKDe3V^&B4eq46BvRE9J>AsaTJ-Y`lB!#mpssmVMs?2tAU23L0-S)LHCX;70M$gh0RC#0 z)mU{2#xkALSg!)mn&@kQzctIKV>MC8QP;F)S&dbfU@TMZ8LKYASf)CH)@m%@;>Q7< z#GqLOK>W}M&uf+j$Q3>3Y2%hQvh~THga6%iE}icL0qZ% zF!6LlC*CbmTpT8jYaY~tC+;#Z3lY1)>P5sI2UMa)$um(~j!F5U{8jXR` z1CgHJYKSNjs6@|5wuXp8N{n@Reu9otCKa{T5mg$STL)#<<4G-1BfwwH@-+agBt#V6 zU(K?5s+Nf2`>R>zn_{#kq8|Qg$Kt3)Xb@El_hWvd165VNpvZqn5YTh4|0~z(Q2Z0fWMmMzX8yi zh?@GVS>C7BL{!;d&GM0=KrIn<_gAw#L92;q1b;Ql$7?kat>LeBqTrCGXSoPjN90<- zOc9osXf=_mgQ;e@pGYBZx?CMhHOt3nHIb`>srGcJOVGhodpgu%7+>N-LBXILhe!$sFC6dH;cQMBKdno?&^ZRuipA zs%H6OttO&={?;sS1fX*w&PjhY%O3$yP4sC}HOsml))FzU{HmtX~3*R9MTL+G)t8) z)GXEeiDs$Fhnl6><|slLDgfw#)I`eCYVoD`KEqRI3B-=m~RVq=bQi)P;s+G!1 zL}4)+(PK&_+69ov{)XG9sv*Zu%I{w;Jbh|CeHKukPEo0rNcCAj)L*2jB~pDB5RFzU z5qA^ZM2ISsO7xIYiKvrb0+y*5)-w$C4U(R@>xk4j3yD?&u*wj{B)gF4Hp$iz=|o&e zv`MK%yCu7jh}$K4AX3E_68RPwReT|l9u4Z8qXC}BQSlj~P8|`o1JzT~T}1-uKRMA+ z&M}k9@NYStGV?L%t%m3d0H?uKz-s^w8}pk02t}g%0c3LoaM+xYgH9$TJ{nZ`g-A`j zfJo#2e>GmzYzrKzlVT$qLQpAUPJQHiTml|YBjgkR%oqgCzH#~{%RvC+zz0Mbl5HT0 zD3wUpfCi$8N+p^q*#@FHN+seU%bcbgluE>i0F~%^r4rquRHECIN<`JcOZ1RZiD-;} zXF;Lm{;fsjO*DiviB!`CL`g?vEFV<34gg*v)pP;TjY=g_O&1W|s#K!8CA)x#+WMCo zmZ@@5I8mFP(>GaaHliymA4Ga)SxEG{Qi)XYg`VQ>xf%-v6+cl#tRqsz7ZRPLR3cS; zA<>;mB~lkJ^ptd$8Vrim4(KK9wHZM8r|oD6#@}Skl8LG3HGv%8WL@|_;BwV`fv0(w zorH@mXCqJu&{NE_9;`$>TKx~Oa#Su?#O9Qefozx51PVqbY6191X8Ai>O~hXO)hL=o zk>>#tKEL2-rwTE_FeK@iwO;=T9F*9RJgoUHlH(6VC^ZpTx))0sef_g5B_>3w8Ay8T z2NnpBO-xad&v)!YI_3U>p%ce6FZgOh2kJ3RL@g8`Vs}_2iS+hYL&UQLs6^*UR-V0Z zI8cc$Q7Tak;5Pxwmjf^W5oJOn{C1mEoLVB91&bjOMUsB;RFQ9;SY9I4wL~i70-|%2 zN~9t#Aku+-#@FaB5axPv#59XvH-(X-`-!;(B2S-nN!*8_ptBwO_2>3{lvWe57k@R1 zCiMp%0?2>@;|nql6eK*f4xomT5Ff7jl#*~bNJ2!R{X?-_q}4?1#b1r0oBX43zre`( zZl%d^c#K4(TS_-h9V2|TL^sJYdm@pp;I%~DokbAyyqIO}k&n2$r179&dm+;P7JB{F zu|Kwz{&0a!^?tHTk06vtr}adol9dnfMk6adnXk)P*5T`k9#T%C-vIoaEbH-Q0TCti zS9=oICs@FYLkrviK>3Ylv3?WPvguK@JIEBW#<8?Hu{XCPB_*-YjEV2TF6%>&ov z0Az{S5W^9vRcrih{qgWVDh?74Wa)O2Gw!(U0=+2N6N&z)RH9b^Vk{F6ENhP`<6*3{ ztRvF?7JB{Fu|Kwz{thV~qS9SGkuMT-kb0su!mxm7J;3i)mQ{uYo(%N~IvE#wI`PSc zNf!cN1xVpMzXKQ!2XO#dx^)0Yn*e|lh;~W#L?R81S|SaCL!YX(XwywP26RkVqFs_* zNTg%cd1EC{V|Q6FZu6FfIy66MDgg)107M%lyMSmH!0$1Zp84z!ogj;Ry*7%O*p#$Ll_j1Y5)y@kcI!Cll*nxZj|tK7N@dm>~0`ytZ6K#AVv4VqSY%yB2*Lo zB&nKZ6{!xnq{I_3d`{%H!!F5)@!HiVH8KXdQLq~1MwdlHViwBt02&g^T@Sz$hTDMH zGqU)V6fl_PISb%8lKFE0kdKJZ{pcyG%RwDBWZh&u=%3d^IKQ8VRA^gD{5#DLA%5S` z-40B~=S{Mt^rrJ&x_nFdjBqU=dRDTvL~MI-*Ls7uAPX-NEdd0qb4!RX2lyS%vYNAw z$PFM94=g_cKu<)J$=}+Ov5qp*4E}1zENG3!DN+S!a0!vywFw!o>-vPQO|{o`mxy8& z7Z!)5>mqXk#-l_UQOwZ{SY)mS;=sPILH!Z+45}qmB36ufWj)Ce)v0m@cFN%NrB39t zWsI89K$V(Z0d%2e9o~?WF_MxDI4TR+1e#nKxqy z;=r68#Ef|4Wk-8e^AX}V4V{?UfG2`%Ldro2OC*sh+>lW177B!~mWZo7ZZAY%1N;Hc zGV1XES|aVSo6U=?&PP>sjmS0uI0c9=0r;boe%90|+ zr%1bcBDb9hV6R=50Dcqf3|eBfZSs$y9)QEf{HFl05&Z)|HV#E`9X1ptB|e1Zm@5DbI${-D{u6R* z44GI}Sj3@eb#gn_M-)3l9YW;Fn!Q!JxVW77G0hJl<`*Fly&TydQw3@f$wZqayO4-I zNTisTm@E&I2wg}Nk*xb!q@Od2suHax8Y$U@M5Rh4qHw;g4W0W^1@f2)L@LoDA`UC# zn8P2-Tx7sWq&+SIW6D$kDkcGu_IVPKtECBePs@|M?(4knPePl7M2{m>h*W?sla>;- z3RlfJKsxw|-asdMy}O4$@X6PE+V0c~QDo@jpJ!l=m$>OEPkjv88vqc7eQ(z+e%%y6 zj-gC!R>A(n17SSSBgFZd?@v6z(A^G9rXMikg@`QO?D=Fa5l;EbHkD@~(Qc&@g{A#M zqJENL52BJ10k%tSP!|UI<9Y(_w^6}6^zH}S%R1FU31maqOERotWA^iTQJlu$8fZ3OtMS=O#= zk?STkfev>Px!s$I%kny{Cb|P4-J5Ebb@aM~(M|P6RO{$<$R#C>(R!kD0XT~hkzGdU zX5wx{Jtr$Mc~ebX)`1=(HasC@-IQV`iu-;74!VhWljg(3oZ<&@pRNK8U`&zD0}cBk z(bWLIe^}lKKs6CZ^H)2gqZ&2cq!!TOJ|ee!;{cX#(P|>brQdx{oTBwcRJo&@*52qn zyYB+Dh5LwTho0QWF6lC->s0PDJRu)X2+iEY0^H%hG?ei2aGR{@7nc*S*L(@_W5=oWN>`AKxEWNV1ny{K!>Wh~#V)kGXQ<)qeKTmF)nO<+7n zP`~#vY`19|YTz~^6?hR*i&BYH;6AZ9fcYIoJXV)DA zDzvB{=;g$BXugE_Aw&1~k({3fLXV+!6FNbZ5UFKrh}gY9v{fqwy{c5A*Of~2HozY= zEORh)h2L%yZ!Xwkh?YyXj)((0F~dJeWLYJsbtLdtd!p1Ph+(J1bRv^!=VIeB@yk?2mBW4eN-NZ`LK$3)L~#ERjq;OKBW>pAlU|@cFEQdWnc)*eWGEKts&B@eM8dKo}&39 zg5|@t5fPEh5%)v3#h=wvJVKfdgZY zX*FtbvLM<7kftyRR{)kD(`usM0Qjg=urrEb4WJwrdE{@1-7qxOo{V)2!}6roEK_dC zfiY61YEW?=A({n%9HWWdfz18E8>l{EAXDuPty1Mmk4%dcoP5uZBxt63fgKx-mO;ji|js-sj?++Xb& z;+qGCJCO0bH&A`TK&ILo=nw*fD#QQJ1HAx1#2_%3;~+_aaUaOL0dUzKpszHGUrC8i zu+u=}2IV}#-iSOFVh+dNNhW4LAk(rFWWZWSIdV9fBtOCS$6t%|*7cux09n#}{6b)& z27q|PTzObtsMSP^lB!ugS*wXSkiRvGUD7;IpbilS3|K2m5(YL03J%Qfz>43bqypC^ zv@`3v*Dhgg>5m?`Y7=uqMm~f1IztCanfMSIrXe~F;8%|2OSGCO2Jlz2d^rHEi8zqI z8pWifX09c2hcd=snH{7w2D_m(F=>e0w#FbVH)%Byl@>WnwPS>&DHi}6?L{2Yy!>lb z=W0Hm_^(MirDSNY)4)% z2{8dqNmKEQy@sd)z`cez1`t`yn!&Q_khErS-ERQsR>GWWB>#SLOe?TrAmgU)%zFzs zxH}Nvs`+eUu05m!B_yAD$&%8%Y;c)W))KKhzlmA?sa6yHBB`2X?K;IgM4cpE0_uoP z1<((~?oh@LEdK<6SR>j5ASg=JScKG<3G@E**smEEYr;O16RMa-|YofKK3Hq6;Nk zL&WaIpJv5oncwen-2vjr-G&7^HJ_r_dc&T`VXp*W(h=#fCwjxyCJbwqC=RP*^$;hj zVx2eEB5$lZZ>&Y$Sak_wnKjEBt4nZXi`??qS*2M3f-g-(ehC29AyPvx^oCyOSeO8LffnG|AQwu`_?9uuQEO z@j&c9Wu)Xt$F)Rkf;X*1WcTkDs7;wvEcxbM#aiTvRhJ-^S>V}utBg}eq+%^f)prC$ zY|lj6^+{gW_3WB$MMksggE1j-C_XcE^y&Kia02)%0I(5}4zs|MD;DG1Ev-Bia z0^+M>n2Sq^uhV>lc$1-nC1vt?^h&V8IYd`UwuXqE_&v(<^;%8D{txC+Hi1VSalWBP zRjfsxSak_v8IQ7a&Ij!7L@L(7JgQxve#l@QPh}#>Dbrj`3?3#f3ryT0 zm>2_0)P?CbMRKuXw#AgsHGDM&R~Wp{)IVg(n+@J>=nM^}35M?ADW;rl@cRZk{LXmq zYjgSIE@qRyfwZ^5>X!!AoCxl0ti& z$uJSoMKQaqTxt!{q%W_YUs|2o65QIiSJ_uL#GDlhKj@tm3!B7h#ELh1JTjcyIKD<}W{- zlcz9YZoZS!BB~eeiXS$ znd7b;gBr)0=|e5$a9pfjmoBQSFefjDqpO%$yhp-M&G8kj>9d!%DmW)l4J4Vj$wRA zEGyn9634aue76|TD7KS4yS~t-Q6n|EvTu1A6wiydSAN2(tXPv)vB9qN_2qSNzV8e* z7>KhZ8@l(2HL=^7jK{lIu5!{HKHoBTolB1 zaIp>`_Cfl6LaQVBR*S@%gvYHYvVQe`kZ<|O4m0}WDZBb6+B4Quxm83xUAwsGYgt6o zEIo$RKovhLwv&&)jv+7B%S*LYa2uQT^3?#ot#-1u7~r~xv8i0^#s_8PH+J=2rlI2jxd{^j3Fr6we!@ zj5y=yt0q*{_$KuE+c_`RLNy-`8<|ni$T4qKv8;|NK{&t2mBIUosbgCcrq!{D-mzYI zkSu~3u6pXR*|CiJIXyp_o1*`Y+|uAmMR7C?~P2|tm*wJ+$H?(^C4m2;?f!;}Esj-4KjMZ)%4|mCn zY0#<>db!NC$Vj!Pr0o3INFlUlYnv#586E5J8TlBLRn*vxv;pyO59{Gsu>lyXNSo%g zRf6qZ1<1hfZfO=N`kpTO+H$Gs&8uvLQYvsctQ{}Z*!CqZh?ZFWYDY~v@kaR>O>kRG z_NKA)J4Vd!88w`PbXm(EdhM^V%eCfrMc6vujf^lpXhy7)Jl4#M70B3`n=&ZH z4tcR=X2b?LGoz`%X2Ct>P&+R+i0 z80+p$O*-nia*(_=fHCVtI0uX{;;9ox_q1&WDS>&_(1X zlW7XuE7ndvWkf7_i|k(}?N5Ht|)GeP$kj#PB$_6$=y~6u`p+YRc4w2 z*1+>KX<|lorbfoBeJo2u*`c4(d2QO&4YvQy z&DwtJW*u;vZx3s$HnF;4hfSGHu>ZE3pm(gJ>ZOP5xEqGmG=b|3z6ZF@@RvUpE*z99mf4+9Gezz2@XTT**5x+FEx|-P55!OmfYlg^w~q9N zB4X}0)uT_Qn}z?P9%;`ln)YHE@4mA}JEw{;Cea_OuQb&|S$<|0Qde%3Hz>WncaF>U zDXr>yYN!d|Us;c))>jWqbQ2}HUr|EHY`;jC8RX5nb+AEhlR*!A3Q$*5gsl$L(G%-@ zH_^Bu;MZ=6XR|OTZO~b(CnuM*gk$lZ8O7bEuYb2ooPptrbcqY<`z|pcy-W1)6>f9< zP-mycI6KwYwT+o4|L~n)A#$5^`mW$T_Skxc@K4EVUXAdyslS!A>~>DPv9L~6R#8|d z%Rjg3F-NUAIlr2fK+_^^0gcfrNQNONynBTTX7gyz?AjSi*q7aA@4Ho@G%6y? zn|fN^s3;SYC8?EBl6!KrUTx(1b=>xv3bh80k94KZj<^38jhSw12BkNt8{93`LNdHI z&VA$hMW;wJwj88ZR%-OPb*YCmBr_<#O>rnb9hq&Mpxz{U~Fo9rLP12cZ{!$g?06# z%k}`>GEHQ4?Jc-p$!bAiYi~1h?pd*2tg}t-wPn6+;C8W(-lv{*YHM+u)V7QD*Rx0S z*7n>P=K6*kwEzR(1Jyu2fy@GcvN)Mh&JtMrL>Juxn zRPw6y%xhWFS`9Bn&Bi&6Uq2|J#$()^rKjWgw7mFW_1)T9hG|bUo~6h9wi;;P9hn?y z4KhaBOAQk(oNho}18aNE#>xM|7LK-(YQeY6UpCSnsvOmfwb3-TJ3~D#Z(keTQEeN^ zIHd*ui#Cc^k;Cn5o%r}_8fR6?pyy;X&Idb~8FUR}<{_)Unxj`W3-Ik9c-v+DwD@*Y znmzrbHA$fjob79pDSq6zM$uB;??KzHLRzibXmROebbJ@&A~lK`XIA2}o!)C@sQrj*z z!qveT<;U!ue`^#rPOWKuqxi+Y>Pk;KX76k_N!4?cx^a4|N!2c;kxMG&XxQE^6UoP( zMD3?)TN&D+$Z9!lH{rS!`Pp?dDtJpHU%`u;q#HB$fMAxaB=yX?txX~AIx5>$scgFk zL8Wf*L0m&6o@o9Sw)Q!)u(4aH(4b19NK5>IkY;> z?XtJBHEp<${4{Y@<{m6S8{p8j&%;V*W68vG|aKZ(`5wtY0qvgfd4^i{$8 zjsM5CpFQEG8O1~kE=g}eJ&b3xVCJq-t5efjaC&A7+Sb7T@QtI>5*tSiLv3+yYuD(D zCcXvdqz}Lz*tq>=ezoslUHCtFEK4lZ6Xq`=C)h4wu(Vm3wo>s!^&_`wrbQ}8GyH5*iOUrs;>oI;2CEw1z_sq_GT6v`De|@17h5C;RyJV}v?y*&2 z^`yVe!pe8Gg*|Ua6}H^oDr6YhL>o{1Uu)xS6?dzxciVDje%e-Z`|;{09otn&OnZMh z1MVe{nw@L{)b67TwcQio$y-l=+T}?;0rZJhwz`|TR$|KhtGTtetut9UhC65{fQc|C zJV~#oX{UM_bK&M@)!EYIa>JU51^$0B7XRDZ$*)vgJL!$i|D1Lz|99KzzUIE2_H1n1 zq4wUcZED4D`?}k(nTcZyepS-L76e)ix~-8|U7^MpchsPU_5b#6Yon$Xn|`UbC-g69 z-Kmgpi9O|nJ5O_)leOb}I<|_3^NRGUvo^1F?Qnu6+}d_E^xD9X7u(fK^|h?D^}U@9 zF;Cjt)<=8cYg^J;;XunuxTo8$%=6FUVN?I8k$l_KaZs%0U>CZ%90@YY11-X3nf_^u+Dz)~ag1Z9nSxEf2qR zPuucP^)4KfGC1x{qFzLWvz$TG*%Xp+Z_{m^IdhQT7qJ%Z;g%=$!okk-!+PNI!)m(P zKNhd>(@E{rW@WwbLfM{1VIQr_!!Z_H_(Y($$K?{W)$b}>TOj$_@eI3k{Z7d$&aC5c zi8^*~ZU4Vr$M>$t8xZ)@vAudWx4kw0aqeNkeAii}N<)jTtOCq$8j z3*8BW#v5YE_r)(CS(KeQt9`$7qW5Hs&%%sd{{Q;HX)orsXY5RLW2cW+nRW<4*fD)? zfA6%#0AsU}Jy+BVr{{+csss2jGa_o0{?XDG`oM@)`advYwzuFqhoU8u-st}?_TjX> zyksBNa%?;LuzK0$TkYlLX^^=J)`?a1u*ZY#*bTB?{_kz;otoa0-G-}g$Zyqs?QnJK zr0+Mad`tFF@3lurXIc-%(2ljGpxMzj&M50mn!1rYkH`ywroMKaz0lHqTiyKMd^?bs zr2O%em}Y+4uG2)+*JeuF`)=<})wFjVy4iGR0aV*#^2fQUs|9oUK(~^0FSPw4L9e>& zYVW$MVyi3rWgGBr!C+H~-&dD2_(Hef`=9I_h7H6t7+M^Xt$$f)l0f=N1?0$ z9hD{R>&mxDgIqhS#dJ2s^l80PXQs1s;v~J357kz!e^2MSY&hSd=&4Stg-BY@`tV3w zy=CP^-kP4&=Kn=w(k-?BYD{MKg0wOD@3q{&8k657Dy^C^Su>t#$!uz9pEPCu$WYRh z{f`}@(FaU7%C>iip0pxAvmw%I|NlqB(e>7C4aZNaAC8x{^TRRuQoNpye!1yE`|^2i z+OQKG_O4zJgKl{hd98kTJH0h)?Dxm@)~sIGz`}{~n5BsrcI^mT!?$CvRF3jhwj-^++67psYO(0x` z_u!2gYsAj7THy>`JyGuL!bi>c;N<6e;m&&hmzX2>=JitMWrR(dp_MH?s=IAV+e*+4 z7N_zjb=)-GRwpUiMvC)(d#f=yM9)Bfzb%JL3NV^(S#0N&%}l!^3_8u}CLF6pTen$d zdlu?#Q8T47NIJV%T0 z+RYX>sYYw-`&HP$E|FN@PoMJ!$HG3<#B~hUKiawpG(9eRm{5FO;XFV@UdWwze}S^j5oFt{7uVqYjV|SqEDoMwBhM{ zirarp9>=lA;cg11gH}4|-^dLqx61SfjolKb&>hd!qDBLzojO^3jQn_XhOt$uS{uSCbTg`%CEw>4S%8G3sTG}$bMbt)VD)-UV;zTO7wjEUQ)N**7yOHDjG z+U*F7Hu2WgZQUf_rs@`$UMK5prR6#+J}`PSauitj66n8{4)U!d)xHgdD zt(A`MKB{Wd4TT1)-YVOUqFFjKZ!&AG{0?M{D}H+2<4*kybhWM1iPk=DA2snv)6)%S z|0ckelQy{ByHtBl^m{F8MLjyIsC(L#h(XDR3R~cN^UNVw*DqbSbbV2GQS4Disn(WR zj16|Vmu1(D!dl~9uhIE@ciP@!_jeNi7c=ZnGWiVKC4krj-+wZ9-fk@PZ95=k65Hr% zg{#RnG>{uWZk{-0PnU63cY}O?rB!!XG%|IUWpm1crkfArUpb}xsdAns&O~3J#b{6uQ|={{)2+= zuTd)f-IsxUZdw=>$0)^{lkD6*=lniwsnQmA;+zqBi8e{F1{xfBzjMi)X54BCTofT zzA0+ylC4$gplVvC?Y3IR?TUmYS_!FT!!LsTCbpe#_keuOoS}(CRbzLEUG3Pto%-o7F{=)W?Cn0_ivuwkX5SCnP5xG&W!s`FvAp~Wg$EzaR4dvqWQ%=e7osRM-$(R zv?8b_gW)>5-E-~RWOH)D^M={4ZdFKcLEUH@?Cq`#Fo-_TE}`q@E5U}R?}u7!{6iaW z%JZ5Pes$|djbGi`XBWgy1Y2ENpbmO=w-MeZR?BV=kUb3~nSKPDRx>*)XP(??O$D;` zwmYEIEEW!Py+=8?U0r88LupeXoU0c_$!JWWEs=CZWF7sFj+&KJw{}{2iffAO_`=oN@c!QAa3xi#;>_yjKEhDhDHiYe?mZ=&a?*+upkPG9J6T?LX{^>}Yy*fDm zYCBc1Mwc=mV_sLE7?(rsTLYNktWy>K%l@di(pE9GG>_RZA8c*!n~@>W#rFm`GAxL< zbNcFlTras}xn}A7r0Zu;H$k~=Slj+-g*eo`Ki74~+B~n}xvdOC-PU>2;vM4Umif*u zD{i@{8}j*fVa1I`e=#pq9?GAV-4YZf-_`RbAw$|>20ODnvEgoGVqOS*5m}JyNt4Z`d)`n*5AsKG{5$G&J^xGjScp&w^t`+A^u zQ^mE=nEfYDa|Ssw}PXEkPg5Til~p=#Wr&s`^3Z zqU)({k*QLB!umnt=3ItZ@N*?iWviH48luDfn9`);)|E=zzm4~eVKuFLIrT!#+bU^Y z8Ca7RyLM@xml;H>8TEC7)YN7O2XkB73oE~f^oMbsk+TcjwmP)8ed>@ z>)Fz&kDDu857vT8d39fBVAt>K`svx(0~=kb>A8N`Y)q_;opextsI7&eK5LO>tr;#Y z@-Aw77hNrNX{%@kM;ITTJ_Z)6$0jDcldGTbPTyr~gKRc;o5PTCqhYA=lra|U8eqa~ z`Ii~aUTkHya(i1l%+RR`)u{D4*X8{148zaThOx?jsXDWrPs_C%ON0HGu=e%)QP?+s zp-*)cpGJNBi-FcST;Mt~=eYgoQ=MwRA~{ZymQj6duu~_yUD{eG%`m3zU~bDWCKfyy zriB&Bv6^_Z!c|+@$&1;rXyae)q%Fa@uWjcA^-VTzDd;N1J@BPDHfgI_u!HN$?h7OG z6X#K~IxC=#J~ZiTEus|x)2F()tuwa%9-d!$_)Tn{_-E4OV~?vPb#g@}vuBaXXt*nb zz7x2q#9s`z;~bOZp|(Br+4wbks-w&C$rid)!_Ca5oNi=TGddWii`Ui0W%61+jRK9GF; zN-W6QChyHN1yqjtx0gbRIoKJ$trtUi{xQJ}w713ScBHx)w%nAvrB9shOC`)o_?gp= zSPXYdlj=rbYErl9^ISiDe!RWYryg~~h1T2u<+Nx$TW@o>S{G%0|H=*R{e0**9Bdt> zVz39{pB($AnkQ*KwJ$l?t)Tl=?>OE$ZX@LQWSX>p1?m4Vv__!fc=9L~=R$N(Hv1tC>s$mP~RRvY^7Z%$8dIl4QOz!FY zjb1dOvT{M?gjur|S5}tI4oXTa^r+H`+4IVZ4_jC^ysSL1Z+J89xY9*cWtAmE4p>lG zRWiER>BmkOw&#f9!Po_}4i09Q9a=hjwsNy5m{wj^Ic&k=3ZI$L#V#){4~r`n%{{Q9 zY<8Z$m@Sx6Ra&)pQ82D-zI}^ZS{kFLOirYrl9ZUgjO+}ZI%S_=sS>FyJ7jU$qN-qz z@l*4L74Dknzhf@1XOEt}3VZbEpVxiWADUOh{ylBt?DF-%5Rs1y~m%7Q5>t_?FQRH`m1$CR=| zN)m%ISs1I_;d2*RgN&W4K~`a%-;|?^eXxusbb~1wNh&X8^GmE7WyGr9RkF8wOIfDY zkK{z1GL}b7o;+c4FmFM{fqCwK8AH`tJeicwK}J!C!}V4(Jj#med{&Z)mHKkW1&bF= zaTQ`-iYv=XtDNP@Xn_fPnh~2@abPgI*b?+TBGoQKhEAC5?T$+)t*=!j2SB0+jGHig zM9KIG<3}WO?W@+RG9yuoDp^f|>qV2N4WArLEUTQmaL#az?;-PKvgVh`U@bH;Sg@o* zhOXx<>%eN~%Cc0=s9X9{N51(UJ>?E-o*hSXCJmTlY~1P|tAv-W!5BDy`<%t((tvKtCdF-jfG2oukL^ zk!n-OyKt^w~O(&B7M3V)IQ-YbPy<R^rrkrmEOQf?7tWihj| zcu}HszL%P9ur;8YoDv0g)0fv??Doc2>EYZ(=_jPr^oTj#QIq;omZs|O4 z?M)oFXrZ&is)UmHR!HlgRZHpH&RQl*>+Qfn;yQq>WI=yJF@)IS~P|Tb@tZbR4J7u9JkFYh9`B2_cQTlO| zunXoqy4b2WIgU*=LaXJ>)s8L56J<+Om9i7*?g)4u27SSpNoP;R*j`f&DBe$ zZ>&QJ-NdqCW+;)l^3Qvf!=fl;Q~!w`o0nZW0yfGM|}^lIVO9aZUzJYxA_Zu6SCaH(N7S+wojO zx*27}IM?k`Ju&rUmm0H5r(n*4`DF#=WwT2Q#*Lm>TrjzG_S^*%=PamNP%(E_$&|$h zEGnxkFP&9ZQdv5?w6efIa#X1uCk`7L@hnZrq6OtudH_v(uCUxp89QXJ5w1sR-q-rs z)vCI-uXACa-Q2@;W!b#K?mfFipRDcM>FsB% z{?wn|SS-(}SKrB|w?F$mgJ$lN|DXM?!H}F9tFvZ2lw%qToA|Te-bk12H#pMeR+4v4 zcoyw9IfmvmTOD5$JEq3k@Yrnqz)X5tGv#MUPQ%qT)`Z8HTb|^^-*SBznv=Jx*6NyT z;>X0+);Km?XMWlzJc!;;M*Kr^@=ELEG#gqs-QQ9dSJdB3=Px}!`^#T?e$vZgzZWtj zr`f9b>e!kZ$AoJwFX?5sZ;ns*Z@&vNET`6L`ODrfCwS;7$x;95Y1{9O4E6q}n)hy! z6MvVuddyp0Yfa5#;%j5a)>s!Fr+A0tbk4rNPEOv?y7HLr-+rq^byuDLYZLxECn6WW z+q#`pkJ;b43X*%e-__Ooy))rAFD+iHgCRNfR)=d`ZkuI~s*_W1NZlaa&zTWFOTCwj zesY5RjPZ3-Wp$HYZ?j$ahO27$R5JR9{T51Ed#d@eFRPQ&P&v>~&FWv`PhX7`^>&Z9eV9c(U?NNR%VppZ!)$q+Z5V=dZV`m&U0cZ@pq& zot(z1!Swk4%3pflvEK?AnzM7}h#r#DBYUqpIXkQD>3;3^Z6dbAQlFdXXX$?5t3KY& z+3)yx)AL$Q*+(YIo*t+5oodp*B9VUjSbxveXQpjPcemfDiQ0~I_x~h(W2Kq+vpzE< zr`9UJlv!NMzu{kS|mvsLf)AZ4J)9d>J=P$FpqW;t4o#W#* zTfS9Uqv8IQoF1?J#!+?U=;8W{FL!#rzpADmrN?K#jimToKJyfJ;xFInQ|)~OHa5M# zTOS>nnv2z4E8MWi-ele4k*Ctf&@;}jOGjp8dYznFL+WPVYX&iMEz#bko0{L#<0#IE zW0{YmZ0k6Ns}Sk-G`+mjo!i#^!+z5#Q4i^5wBLNHwv3nfGN#9!9!I*~ekUr?X6bDm zm;SHh8WzreoUhb=V<*V!q>r&(M|2+-#Ov1_S3A2-t=t-ovzlb>7&gmlp4B32=d4y) zZI$2XU%IMB@b#bR?z%^kF6zf~Y;>mnLi;(Lw7*b4oYN#tw%=W|v1_r|7|WKN{uc(Z zi2qn%X?+3)Les{nz8?{(@kpJZ5L~82c@!oQVIN;BEO+)NZYtE%)@lFlZR@ z-!S+!!+%3pze|&W%!;S}!XP&iJ~zl!VwRqT$(FmdPgOEVZt|0T2xXNs%hx#QOn6&M zXJ=S#^WQY$ziF@s{%w7oE%)@lP`xoT{`8r};%gppZ|?H@P%;wxImFao80-}Bzf;Ol zpF*wRGt*1AzUJO4;@--ocY#%y`?Fq?`U``+i2pp_9!dXsDbM;8YSd+>Z=*2v7i!g& z>E1r&s83n!jy4Z(ME3nM?JG<~FBz>h@Q}e$|#Q!eN z|LUawUHH9ct>0DV>|jaK#Xf{u?PjLe&4r(l^wll-$@|Zb_|NzLll7S&tkY)`ZEna8 z)&v(L4|nn^izfLOYE_h(eh(L4zhrzpg6j!y^Fem7HW}7Fg!)m<%<$S^mcBzrAh-Ms&#uib)Q$j^OZcCaq#Vjn`y0-529T=*-JzKW8cy#Ij_{{x->yk!0cM*I(s z_#YhcKRDulXvF_e=ii=J{NK>T2S@#uUc~=!=f6hMzxATjUl@#x_#f%~+uY>;MkYQu zhQX+a|548WHA!EilAr8D7>tSdALIPbOvXPZ;(u(!|5)dLOVZcapmw$&AGVIk4o*zE z*oQC}9|=F+g+Di$-uQ_Bi4p%3Bk4_y_@5l{KRFWrDLmTJG6$PyY*pSrPwH`&AZkkJ_gL zBkl*LN3Z3^Yqy*0CZW|dQaVQ_H7{or6M@mWmSayR=tI~nBQ zb_IjX&@HSu*~`k@%NH z;*ZY%heg~E3pOOm>(W0g65q0j|LFSVh=}_UF8_}u^A~+ySP}8R!udZvnW}fcAWcqw z)Q3<{7n$vKRJya=S4G^T>yI@N_cf95Ya{N_^~bu1`#P8Z+mhvt&dw{=#ND2@Qh#A^N=neDFgP_LpB9nNh{$I}ih`cEx zUl?4d{+Rf)r>AS_pQdiB=aajUACsJ`=aI)V+;_kuj==%QXS(=12g{Ld&7Q0E`RT}J^K!M`-i%!3;>!=7 zkev9l@@>I=qI2&N{D?f*$vuPI8a}_@$!~7ZJLraNd)v8Mj}An>-pT!f3COoO|GNdV zk#BZ#QLq%*)?~TCz~H0|d2nzsvh5w`21A3}k?T2mc<>7Hdrlr1{Dkb|9~Cs!mV}%F zU*0i6ALRF3`eTDBk`sSc{@J+O8aY?%p;a0FCk7W}xK9r5LAEEA+@Lsk3EB2Ja)Z5s zFOiRR^0c6)Hi|4imR7EwQd%ObTc|(n8|;=L&j|L;kV}F^8S>0veTIBsa7l)IP;hUC zJU@6fL#_zE&5#!awQKtP`TQ&l+DT6QS)O}Gz0Y-Th4sRh6HKN`I~?17whP0#xy11X^OSnctCzsuQ`!Lt z^TC-;cXG(&Z5?qlx9CZ1)A@I`)t)FyIdAnU*PJpA7yDyHTdCdQf>b=!zIsnNS9|Q& zoYQJXue(i?su&ciAMY#i0zP^0M=q(eE=g}3I7s*9;;b&XbBG2=oJ2{b?~gZF?h($BqnH(v{`Ty``;=T$NeF(=MFC5|m* z9BGzgd85xH-rt$cfR)N>?mJJp+rCo}qVm&_Elb|H~;hiE!B zvMeFdPQaxu9$0-wQcn0ar%2LUJ0;RicS)WJN|lX+l^KeyjtyBj8%!AmNuDo?rr><0 zD>DxTMyl0Lv?SUnBYuC9C&M{CQtHOs6Gh#+&C*@d1N+*`h?~IjRn7H;>QCDxN|K7L znw)Iyn4Xd7!QMoaTOF29I8bai+S99R>-zwy4iq`Olo{2wPRv=6w-L}4X&d1(PM9T9 zN?Dfb4yJD-6?M98q~Q$ERx$aLyV1k%)}F~zz?L5r-iReKxb^u$tG$eHD8?m@t0Vh( zG$(J+zw8EqTX|<|!nbv0_6|W{&!2UE3fvR9aW(QQM$PHXjM`LckKUdUP411Xk3pR} zxVH>~!6xVVecC#bU3j^-HN9lp`7`%v$Sz(*vWv+-`Sp`=qRG-#hzZ_nG-qzWc&qVy?#B0y67XMX7<;&hBn!izm zPn5&uqka%vVg6L^`^4-KL9jov%dgyBzmVQ`)appK^=$Uoz`d_Cc_y+ekG{bE7xSn1 z8e4jD?`xDi9C@Z_{cN^ziu#qYI0zORmCn%?UhyQ_=^K+3kBd+7xbjH0=K_mouyLA? z-{KidJj;nkRqw*Pc2PKc-mv~{d;QtkmUHna+#LKrhX0R5^Y@u?W)OU3l)r&uvj61; z!Eq+HOV#5)OjbTWfG&Ntv#SUBFIKwdZuMa8Qf+*lwjJMZ7O{2TWoz5|G_(%cpQ zN~6kqy_h{W2rAIKdXfGb^rx6!_3h$SxH=Y(+}n#b{%w3%J9RUv{HJb@f3-)#|77#8 zN;m;NZp;e;CFyvs$vXzY14gC)j8W20S@bd4*hx{Lod@i)- zQj6yvz=2&laQNcl}=RA5OZ~&n>*GC%L=vCHD(RKTtSJzlBl$tRI;? z2HDy-+0RuUiGDuM^oq~f)yCAP!n=4SyLxDv6>L#DHqPEQu2KIH>&X3VqsspjvKt@r zpJ(ZcN0YwQgZ1AFj5A~hjVkXIM#cB(RUBmZ(AZ`2^4h^!*3e`N&=k(V3WWN9ZxyetUvpo?EdCE;(S z=_Ma$Ow_kzmoLe#pS1Jmt?G2la`~^*DNAo)y?-@zP)CEN!l?FGjo!s4d;Yk|_j!9_ z{#2FDpS(J~vr}@HldBguj?`Y=h{xGs#Z%Axt9&k;@@3=I@;l9Vv*sJ4{8buN-cyYa z2Eiui<`4P14R;$KbyThojH)L$ZXc!J%byz;if^UmL-9F#ulUSPnrvr{>TLG**yICD zFaJx8@^`dR`8x@|X;k~!__lU)sAo?da^DWH-*VjpyvC;@1(a zppN7-jgl`iJ}q}kNBzw8C*|iDlcnE4KF-AbA4bKSLprWL6^|>I^4-_;ipSNf{JHuQ zU3;sZ9<%VOr!7XM^R7|#@Rd>VI6I;Gas62FxO$PlE6iQ-d}dVso!ygvYj=}fx{_Ua zm2cO7yJY!!L;4;TPMv5s(sAQK@h8gN&-9Wf;?LEC!p%mXXxD&ptE;>Gxb)?3sL3jS z!mh2v{StVcQTcN5$-lh1ejFFGzf?apeisCqN*rz9++;hUk^M~&bTEGF`?u+P;cn$I zc?cW@CqNqq=Dr`a{${d`JL3v?3cMA*3_pamlz;QDFFSRd088Kkcs|?=?}ct&QTR`h ze}eIBA769W8g_tPVNYo9t1KUr;Xbee9sy5)=fJDr?eH=9GW-C34{L-zokp-78~}&G z(QpEs3ipM!|7`hP1XsfKa1*>1-UV&n*}}aBKZZZSnl-$8Q`iCahQr_@X#2(%-+AyF zcqe=uz6w8rKf;IUr!~W<;AdiL< z&`&e!-wZg@sPG3F74Kni4f=KPB=lz^Z-N)2-;8_{ybb+B$dAES;T!OuMy30ev6=2_ zz@Ko>uI=4(jLK&&+!1{{+{BXMy1=_xKj|cgl&vUw=3?uBJU0dqaTYr5l%&4id+T{GAjP#;HgHXd!bQ__)FoH zMx}cb?)M@;2p>cL0`e>H4fG!)e-6Jv{|B;uNXo@u)2Q?tA@2xxHYz_waHLWGCKx{m zf+=usqw-mb`+Vd>;GyV`Mm`1}Z&W;|;l9cEy4IQSGNaI0bzP@+>&VsQ4>!UuJwu z>nXU(sPs<6{Ve43;6>=KL%tE-YE(SW!q?!puuhKLtzC_mtDJBrqtfeudm(ZkxEuPB z$YbCH^!p;0z}ZH{UxE7);~PP+46ZOLy>+;shI|&(wFsBbtB|jQHyIVrUGPQtC5$)l z;Tjk-isEVpKfW;eH45 zJ@7&FPa{7MUqSyK@<;G<^gkp24sFlD(%lKRhuz^QI0G((hry%a>F{!+%5%N(#vr&E z-e&wt`z1!XKZX1pd>Q>ekw1i=85K`WJ&+ii85O>b@nQ8d*v0sjo=0#Wgggw6LSKwL z4ep12F7kX>iT+6Bqv2Zg8)}Q47Wg=P6Mkt_ett4uqICnb2UaVGJ>!~tQ{)z~HTtf|1+ceK@r;9|@Njs% z@jLCi7|+wb1U%QM^e!`g7X&vV-vaM6%Kr=SBbcSNwdr$>-)VdquML9Mu$@uycE`Ox z@&Gs#{dnZbaBuXpkPn3O&@V+^4v#{ABJ#=bbo3V?Uk0x>DxVL-*WfR(K~wME&8Twq zH+GQygF}oe*PgiVjl3_MiGCjPLbw?HQOIlHap+G+J{z8o{%YjS@MiS)AwLBFZd5)4 z?Fk$6;8-}oR6Ym65_mkk!l?56&G=#v+z#(HD*U6kKacz}+=Bii&O=zmAf z(uR=Bhf(R|A~%IQq3?v;74|@1ggh9IFe;z>!1?efcpAJC-eFX_j~br~f+yh9MwRbX z+}}t37=D5N7vw)+*uuxxz^L$zU^DdXkvqfgMy0z4+!ro~r@`ys)9@=;M{9Ho-wqbR zz2O3*%D3G3s`hc=YNPUZ67FXsZ-N)2-;8_{ybb+B$dAD%(Z7oP27DL&7s%hhAC1b- z4%*l>c7TK66gVFq1-wz=jeY%{vBqw^zr2w6+Rd4 zh`t?iC)f>rKjb1f#HjpCg>&H%@ML%?yd6FX-!!URpBmo@f-m8>M&;{w+-vKZ$K?7j z*QjuLLLhzq2CX=6qXy6pTprf@Gkfg{1Vn`?ftid1L0Jo@_B&q z8NFwK2N_kKD%@8huZHW;pN4!E+=Tur{%Y8%E{lYnYqoC9EW&A7%o`Y|p|J0~*ehGg=Ut2af`xCV%Y++P99gXt83oJxG(D;$| z>EQ(Q`x@oH1eT*;V7yEFws0l-li}IMJM^9iUXA`P_^|P|Aox3c3H^ugE8{KNuYy@^ zB`g2Aa3|ySTDQP%=m)@&#;f(d0q%{y94>~(!1cz9f?y-O0R0W{4&w!S4-B6`zXiT; zJSPY~hCiUM*-m=pyP@$cz1M(k(D#J98{gBs35OX~@8fXa2YEku0Qw5#O1K35D&)2B z1oUSjp9?QED&1>v|C{j)&CBp^qw?`6?$0B?47Z^F2>CPkHTvI?v)cQ3;zq^4lTr23 z*?6kn+rS=1rMDaIBaz3z3F!AlE`hVrFGQ|_hZze0*;_B?x|ozZ;d0 znp%^Ydn2Rd9bsqK4Hg;|ev(oC_cyMWU4rFCgEy%bz(z);(;B%Q><#Fx z8e9ZVfM*yL&n3oV^nMjyV^n@`!TkZ`N8l6aUq*f%zK#AfFj{q1a^eGzyhQ4F$R{wBjGxu;yK;8Lg!ZCCZqCu1@1Q^-v;kS|99jk;dAKU zM1B{3i2hsTAK`E4YwhCGs|R;5Dqk&;+rW23Mj#0eJ&F4gH14m%^*i--3Jxychiw$WOx;j4JO(@N3wryVvgu_lL*B zOW@y)s+X6Hhw8mJeAB3U`v~{%kbi=|qpzLs{ndxLM#a|(xh?F3z8CVYun7Gqy^lOoihZ~G4*Cp_A_)nNs;PabfT%>g(Y-&{b^KkEm+ynMOKLmLM z9D{x@k{lUl!U={k6$gANx^k>0K(O(I#Lw^VIJ@7%J%JC2QBFyUH^<9l>pMJ)L zdS3+x8^4l0HOhT2k{lUl!U={k6$gANx^rs=81vjC;3i&#C6Z(6RAB2yge*yUw z_=a(zo|9mkLNE6-D*q#l^MhbC9B2G02=>N(7V?2`9{Q!o%i&SzPeeW$o{s(^k?RCRQ~(p zJ_30(9FKlF^8RoZ`US{~;8OIfk&lHZqCX4yJa`fM>yU4Rw;Gktf5Kmk%74w?;;bO3 z3mX`f|K`T;w2y?`1?HpQ4S66OhJFI_6gUn2Y~(p`KKjFukAO#`KMDC1cn125kuQhW zpuY|IE_lCD<$4_c2)p+2`u*TKcs+a_X7}~}3g9^7cRK%QEYnuq&R+b6F-2gT=s$4DM z7tLWcH{uq9N z{ukswVA$WM+Y0V#RDOmV_t8BLIM%5A>}8bu0m$X>VDw9nm%)|jPe9%PPeXqp@}=-9 z<32jq0iS{&8kO#M#;JO*27fauU-8|%d#+J(Q@9iQPRLzh5A;RIgW(ADlaQyv>FCRm z4}uHOFGF4dR~wbj6X9*}S@=6_yt~hL8{Hq zMtG)C`MDK71HUyYzri4Ju)aYO)-o!;xkkCSLT(E?q3?yfD=b1k3VAG?gnmEdQdo|@ z68TWL%&7dVhMVCQ_#50=e$3w%x9;KX^2}68;^258KLCS@^+5 z)yHUKZ$1CO>F5uJRYpDgE`@8*pAIiJYE5@JyxOSx{2T7~BR>ouH_HDO+&?zz+3a)p zwNc@J#68@@%Qay=qx{DMF<0k(;0~|}>;ScW==_a>V_`9z21{WX)FYz{cL-bxm%~+X zEj$UH0?&fy!5fWrwQmjYhWEo~;fqjB4E8UuEewhb>`y*clFj?w*nS?}=>RXJz5{ zg45vvupF*{tKf0a-BVKd(~!@C7r;y4)o?R>06qergwMkFpu5+k_`gK{7S@O<-`bO| z1slS~ururi-F+wd-xYZb91o|$ec(K}5W0I$3cn2bba*zr2wn!Sg*U+4p}PmAcpgH2 z3_b&2fd4egSbqrZd$&yf7S@!(H@Pm%g-u}>*d6wU{otN(0^AEuhjWcP1;Ko{7#;>s zgeSu@;kj@#yb0a`?}5+47vUE8HvH1qO67&W!arf7n%;d!*b26V?p~L|_eUNKhr@l~ zesDIN0~f$Wa6Q}z&xV`e4e)R9Zs_iVDId?8{6P@B2;YG3!0+MD(7xK;{MUf3U|U#d zd|mg~-~c!T?gRIOv*8@L6fTFW;97V&yc)WDUP|v)4Lw8?G@~y~E!e^norzQ6-$p3^NLU$ia z?se<=cynP>*b(jm3t=BP2~LGG;7qs#E`#n~meM;0`9yd!yuheM^Cj>a=?jDx>&qqE49&LP5<%B1}Q{dUq-NTZ<%aGlDEXg+_-vXb5FTpq9 zJMbg;8T=Oh2>*cgT`rcd+OR(C471)dJi zgBQXp;5G13_yl|oz69TZ@4%1XXYgD2Bm4updta)b9U7{hE(wAruqA8*2f!iF-3OEZ zvB*>4-f(|-0Gtcw!z#EG9uL<;caKc*pN)K_@jQK>FZ>(49X<OKrFVYy$hh{%|lH4)=r;;9hV#EQMuo9$W~Qz-7?gGgE$!K|T*&2;KcM zxx4#i;$7(PgO9=|;QR1ns4sJM<*fnh!UnJ@YysQA4sbU(5RQPO;Y3&r%ivtN)Yw7y z8sKVpEZhK3h3=l4{9k~41-u5{2Ook@z^9?R|EBQn{+swY`mbSwMm|4{pu6uTf31)^ zz%FnPxF?(p_k#PuQg{SB3a*1E!VBT0@LG5Syx-VH_p#uU@LBjOd;`7@KZak!?_ur6 zKEC>}F>D6iy*Z`l?#+pP(eDPQ!5MHCJP=mEO1J^Kdv%KM9OU!iW$-Ha2z(qq2Va7p zz%Sqr@E2G|8-sR_C=HZ-NiP zN8wZOIruL80Dca?hFML0`C_mhYzXsUdpH&D182h7unI1PE8r@)5uO1z!HeLH@D_MC zydORbUxZuW+wd#+9sCvk2^;L_%i9RHfURIY>z#pKy_or~~-k(@odq&p3>%$JP z3+w@V!vSyz90SKgcW>}Hy=OI9JQyy3OW-oN3a*9g;YN54JRiDyhKlzI%+#d8Eg&P!ChcJ>;wBlcOOyd4o9wphr%PEyO$_` zCnLN2iIUGnz5reiZ-#fmd!f6psBq6CzXsog?!Kbjzd`;P{toN6@b$0*>0H;Gytvcr-i)x_g)Me+sg@e<|7BzZ5S+e-(Tay8D!J z{}}mm_#ONS{t3gKeZK0z9M}Xlhk39)>|MxF*s;4F9$boX=Re=+i5a3x#~kB95w>F{jm z?&&I?OOdaE*TY-ko$vwp2z(Mg3txfm{;uL}*xuJiW9aVZO5Yl}0QQ3Jey-dHB9DNh z;Y3&r-F;p8clUM0a`XqmL*Qb#9Ik|G;qmYkcse`}UI=f1e}f;uPvFmyZgXmFZ8>@fp91s4adP^I1QG-S@0lO0T;u=pu0z` zbXOxE57)!f;o0zZcsKkzd=k3*#ES0?8CR8*YM^ z!YkqR@Md@?ycfFr&&uE9$j`zT;THHd{1AQ$zkxr%-=Vt~t$1s7_VrZ{HiA3CR^1aaAtG4<0$aj1aDed>eXlwk1;@fU#*cI_3@(C8pt~pjp3Y5}ES>|;hquBz z;REmy_!4{#y8Gjb=Y8ZqVc5;b-xxN7U10(23wMK~jc4dwGMozcf%D-Za4B34Plsp2 ztKnvNkMUG}9|n9JJ_TQbufccW2k;B{4g3ZE0ps0${B>YH>8CR8*YNP!Mosd#`U_-58s6E z!e8JYFjnCG*M`kuOV}QEhJ%eKXg?W_g%jayI0w3W?()9~`2@HDo&nE+7s1QmweSXb zKYSQ&fp5bP;ivE$_yhbMy8H0TS78rdo<7jshnIdZ@*Z$cxG!|~;pML!`5<@*TnyJh zcOPE|y!@>|UIovE7r@J*yC*OIHzMBx?}qooXQ8_%FaMt*e+7SpzryUE zKEH8TAMOBmhlAiqI0jCFQ{fCa6S{l#%7?pGFD^sB0v-d8gC|3GuU`HyMZOZ=0q=p& z8jsQWQ}_ma2YwHKhCwgyzXogrJHT$R2iz6z4u`^#a2%Wjr@_248_&VA$K2wf_=22O%gVFj#&hruJ@YIrPM4>!V#;pOli_yGJnd=kC@Ux9DIf5Q5GeR+0( z&EU?k9qa`2VNci}4uJ0a2vk3lkf*^Ja27leE`iJ732+0v*tkOX$lzvp6LjB0AoqKb zAB9iA=i$rnQ}`ux-$S7A?t2Kt9d`BUHGw<$az05}AWf@9${I0Mdt z2f{^g30x01!n5Hfc&%}H5ZnN7hj+t=;osr2@J09rdx2A2<`vhE;GWTme_XjqnV34ZI%S3h#tZz^CE6@B{b-{07$A&6lqpbl=OM`fP#R z26lk%`xxZzzK=m1i+&>98}18d!2_ZD9)`oTE-_hL3y+5z;TiCJcrm;hZiWxSN8wZO zIruUB9DWCXf`7trcb}g+FbD1i2f`6>G@Jyd!ZPT--$CVDh+G9%!(-uk=)T`U{x3$p z99{=+gbzUXeGc;f7V<##d4|alGVK2BV90-TPF>pMb z3ipAfunaCX9;)Amg6{hxB(Fg}5uOasg6F|Y;g#@ict3m${sX=bKZaky@8GZSPuO6f z&tD_h0=9w!;1Dg$1xL+zk$aBj5qheZPdt?Y>_^bl)!_9)bH&a2-4mo(0c?m%uCF z_3&o+5_}E53qOFL!>{4b@OM~aurGft*bp{`JHghlz_>{7x!~?_5ZnXq38%olVF{cC z*TUoBDe!c79=s6V0RIN>g7?8k;S=z6_!j&CegeOS-^1TvFvOR$Icy2r!_Ke(_JYIU z9&kLI4Cli`;8M68u7Ydf8Sor<5xfju3vYlA!N=g!@Ok(N`~rRte}=(OU+x;PE^GkX z!j7;zEQBNB7&r+|g)`txxWKrO?*$Q;A+LaI;qh=IJOiE&FNU|mJK+QH5%>;t-vgrb zK12Qr{s@1C*~5JP;;=s40XBm>!=Z2_90w=CQdkD(!G&-oTn&$h>*4wEVt5<83qA-R zg-^lf;1}>4_zV04<_`DeZ37rk1zZKsg%`lfq5D1;<>OA|d*LI{eV>cmUqgNq{tEwu@jZNb>cAGT z73=`J!2WOm91cgpX>bNS1TKcl;Yzp`9uF^vSHqj&t?&u>G<+Gp4nH-P>w6mDkMLI* zj`Hp`VFTC*?gU%IUT{}95Dta=!V*{x4}yooBjFmj4xRf$5^gDU*7I+7I06qer zg3rO%;G6Idm_5eFTN~DgjbSs`8n%PGzILS(_OR>!)7ag>M^W8t93K=lBHE}>!M8?= z3W_megs4%2yqG9RgdjoDypV-NLlTqaO;Axm!J-8VHC(aAm|j3dsiMV-HD0k|eQBhi z_>Ri8T&0#;>P;=`eg3n*lT3~qyz^oC=Ioq(=A4-`XWx=tJRJw&IXDD|V+qD^Dqe^4 zaUm|jWw;vG;FI_?zJXiuJ=~6e!O!ta{0a{kss5Je?{4sL?1{(W3D_S`!?W;goPbwh z8J1%;*5UPdBhJT#xEPmW6RyI?@Cn?6ui~HaE&KpK#%`k${XYzQVsA{tzIZC0j)U+V z9D>7f98SPuEW_D&6W)e*;1XPhE3g4KU^8yQS8+S;z+Jc-yIz{;e+s5z4;+9QI2g~x z3vmRF!ppGOyh@+Dg_T%?cj4W*9Ph&>T!oL}6Zkv)J-&!9=K-;>G5;Ah;AS$1AWDCu0@X;`MkV-i^P+`|tr=j~nm> zdUFkXN|aV(Cv_;dUv z{s%sUkK)Vt8g9XDxE*)k9&E+$aR18_{X7zn!gL&n*_eYD;Uzc@CtxMk;0&CN^|%6? za1}m=PvA579R30Sh;QIld>=o;zngmO@=yE*yNpjubVku6> z>3BWfjPvn9T#1k3;RV#;^i!!#i*ZF2fbrfGhD~d>o&`XYqM_1GnN% z+=c(Z|HbZCC;Fd?N8vHp2T#JY%=7j6s5k_N<0!lgC*V~W!wOu8cj8j4$NTX?d72m_{xEF)cM1NDTJNCho@H9LFvoISk zF|+i&t~egA#7Q^>tFaDe<4t%k-jDx@58-d{N!)qj>{ z3pI3B0qwOEVO@lITV^|%5b#Fh9cK8~;BW_$-fz&+TC-{Jmc^cN4q z6R|&@iG%TcybwoXJ{FmS^m$l#Emq?UoQ=Q0d+=A-h^ui8uEX`%VxFPzS;F^lJMP3? zm=a6W?~X^}QFuJ|!Txv}W?~jzfJ5=XK>1(ja|+A@f}od~5(H`HA$r}@JVNhRn?3ct zn5HV_n8)bzWXReIus&KiACE=dhUC|BFq9 z*PEKx8qD+cJ;Y{?K4;CmP=D8I>iJHynHL0`Og;Z?G4u6#xu#wN*ly}M#ZFU?Eq0rl zOIl5hsqlL@ChPB?yQqAP`fpBE|IHfp->g&r&FSjDIZORF=cxbYP3pgSi~4Wgrr*Oe z7pni}BK6<=x%zM3t^S)!)qnFI_1|2s{+suz|K@$_zuBPvn~mzf*`)rPE7gBK3{+q9<|7MH& zZ*Erq&8_Oc`L_CRzN`M5@2mgjhw8uik@|1$Q2)(O)qhh5XMy>d`fu)1yR2y%hg~tn z)PLPE)zrA`fxS$P&toyo)Hv;n{Y+KT5Dd*QHEuQZLbFVb-)zh=Ptf1*VXmq1JQDLw zjq3s|G!;G(i%pI5GAuVW-Yc=j)W+jD)71E%gL6$aY91~ybv`V@#iq`SrC4v~=yT|> z!MsqPuZ^qB5&HaCTx;sQS%>RQoj)6}*;FSt;wDq))2rBG>b%;5+f1Eb@8Nc{M4#7y zJ58N$yKuLu^KK8enmYgXV$elporhg9#jMfs$5d12We@CS>ij$w(@dSGeX*Z8N5>yC zOr5uxm}TCg7Eurm6FP z4$d_-56r^_rsji1xY%sa@yB|zQO6$}Odb3tTxDv$cm&s)nm5+rdQW-#>y=}G8=8f?4088|Go7!sg#JDs$S>Lm*Hru=~xR0EwzpMDEtkK`6 zs1M=!f3nnhKckMe00%=v1lmJN$e3TY_M9y2`ideolR}^Z2}hQs?hI>Z6^v zZ<}}P_@5=0>ibPhou7xO?{;4HHSg8!Or3|1m<{@TX0tH}J}`B@g@6C0^K9#2l~?O~ zo3+pEyc%Jy34(9TwffwLv*qLZ`zZ4%eQt@lUf-W=>O2X*pH=5a&vR7Pc~NFQukZ2J zzPIxr{C-J||9@Pdvc~(^A+jY1t{y5k>$nYJEmyv)&tcOsv2omFYW!Yw zvHU0qrjL{wuc1EACAi$%EL^JPaX1b zeSvudj|Wx1%*s7^Jg9Qq%Dr^|PkkMNaQr?(S-UJ8$LeC3x5d=hXr;W@)R;)?l33r@ z?9Y6z{2VI}V18D)*vcC3mDH~>H8vJeUTkJEpQ?U?m3556c~a$Yp471n=QWkXc}>SA zoQG5n=OLXR;ryX;IDh2u_($dNyw~}%bU)>)TyN@Ft*5-f)G^vZd7G(Yu$%H8Q#-ep zo$t0ibDa7~d6+pt`=5#$SrTm^bOY^(NkmaYCI&TM1&M=TprG zamq7I%?pbuFEtx9ZYVdIjoROo*O^Uv+)nvbQ}f1l$~(-}8sC)nnwm#a4wBYhbB)eB z$^%TDBw3WRP0cU)lnYGFGsTp{?}yTSQ$sm!YTlVkIlO<+{Ii(yQd9HLD$0+T&j&#> z<&EZxYCq*2rsk(s%6rY%G)_~b+Mj0XWX`2L($u_FLpg44)%i$yv8j1%9p&|==Cc;c zTTIPsJ1OrnHNOQ1OKq>K`H{vKNVMH9t_UF*Og)p*+{rd>EwH z&6*l7DV6csgyrt1cx+}oNG~gimjvmhb#+0yU6GzQaA?tp%4v1wMFoY!#zd|xs4c0g zn;fehT3t1{VoH!+8>?);#qg?<(#lv--k8fGw-{DYm*iUAetN7nK000=t1VRC=$d#% zb(J>XAuz9Qcx`QU?dVC9rq$NQ%DlDXODf`{s|pJ9#*U~gnKG^_UQt<4F*Q~_O&#hG zlc@LumBz%bn-;5!kBUvLuAMc$wjv($QaV%^6DvvHoUsL?^M7DViRO$cyma{YD~5YN zcgV;hI|8HXYVxWoqP=lz5?A|`hs8Rn-sy@_C3W#wZBcksrzYJJHO9my#VV#pcZqAt z*vgXWv3(^ZDs&#;wV^1lAhP4#RysB#d7X|e*;gGJle~)Go?)Yg{BVPkSMpl4uS%{- z$?IrT7WrecZP#d>Hyop@!kcx{Q*PP$+Qf}JZD6_a9CWme}qaBS?l zw!za$I}&5GL&fBq$SWn4ZDd0b+`9a*81 zxGMS1WA@!w753VY((2lH7}8-{8GgCV=eZ?SWtFj7ruDYr6&{&_nL}$T<3md-D@#iz zU7NJZ7_Ul)**UKu(E{ye3-SWOU9rzigf)I(3t^qM4RqMN_H1GscF(3cFwusjRX7+) zS~;YwthRj*bhvR|LAdh!Jxd&uj{DBLWqTEGuV_Bl=RVPTe~)xLs&=>9-rx@F!hx`l zW);-NO5)-Da(jT+?r?47oVPo(yn=8yC)vH>^+kDO$8;RRi5n%xMv_}GY?I#1rb}DV z@vO1H_HBKCT_o}QD|Jn>Ug_$@&D>pRl9smB=`eme>@wHjq_fL#?U=|Z*x`oC4v&{N zJ}!#I$Hq(SAxwuutE)#9i?D6;+d~^{_DfxumqTHa0zRI1|@YR!@o+ zOLXc?iSghqQRDm9R8~}J!-=(e@EN2}s-8MER>h;6#PySFOQx#QkTIjuOXBg`iqdIu z#s0sSV^mX5fdf4a2^T#z?y%_TXt$K8A~5&(_&;vMzdv{)6@Ol>K|#?W615 z;-D4JP|bN zV%xBK)_&WC(Yy>5^fb6_aob(!)oW0_5po_&vcFWUf%%hOZA4(*$(_ND1M zYhO2AT>JEtt3&(VR6wz=bBoJ+Syx2++n~HuU1xdSb#ZxL>1S(>+s}h^p!Kx9ZE<;D z>Y8ZY+DM*WI&90c@3W8Q+3OI|Ja;^fQl)5KbELo4PS?I{FV9}DnAz64L_I5Jd3oC- zc}GO@CVF|RlxJheEv~bXROuD?Ay}Z;&-j5@B4|#cO z?RAYLc^kcY>r`)3q@K0UmS%6eY1*!h^G02I>*D(HmX|k210vaW|KZiUQS}BY$1UzQ zfAhB6FS6ZZRoQLVUjJ9sw()1Lr!?6WEUq6ZsuvwE8OqC5okm^kymNW!US5GZJ10rr zDPG>pNM2ebZ?u=!qDI(z9B$F-aJj_GYgS&d)->wUM;F&Vd!HcM-;H`rbzYJ@dtV{i z-?Z8;K?Zq!BYBIxyxc>RkAp>CUcU0u$U7;L_oSDXs*}53>)qmx$8Ws68s)k9w4W-w z{=V(ytx}#|#%o(#-c~Pff%4pZbxI`f8!s>OM~T;-U7*YRmzP%`$+P<)*S<8(PtoI1 zue^BVc(^=!JvMqgRw>VoKfM*vmN&x7>wb9RcL@CUUFhZQj^x>KcI~^?%bTdlEGJ3( zrg(W-b?xKD&QF)O*vng?_jmTV#!=6Ti@dyY<=Js<)WseHxICNRqx;XkC(`CHx9Bj0 zi@h!#-G7Ufm#;OJH%J$k*W%@6YjRv0$+LR4yz1p`kK|=(z03RD%iDF7UQ-Se692ip zzj%2W8U$`U>#dr$yl%Qdw7*TNv@S{BfvOknZ*C;d9>=)$_4D!yH7RE%>2F^zuUL6* zJ~%&;m+R#%Iy!mYFfVU$BrhkDH^s|q)&oboPj-t|hsz`{uUUC%T4TreLS3w$rsCjs zFK@5z47w-DyVc9vt~@vXhDGx1eF(d`?l!_DMRx`}lH}R@7SZF8GOc}n9-&)mb=bal zygd7!r)0gDz5 zqyB~oiT_;Q$*LFa?>6PR@iH=!H`dE*Ro){>+Be$EOPSu@zDpx{_C8LuzfFCUx6j`9 ziMFp$d9HodZ`a=ky}Sh{CU4*UUfzO8`^H4_Uh(oW^~A;Q58UGR-%DQJHsz(Nk{#ay zU0nPA>g5$H&*lra?8guPyQ`CW_Inf2_AOSuTU_I$Yu}e%`!XW!D~Yu4$b&lO z9nnAWxX(qpydSAvw7>bvOHrjpT_#2H26=gz$~(!0NtZX!%PWlJ#Ugq3eqpq~S18YA zSgiZG&Z}qNd(vPPSX{koZ@b0Xu6AMAk8P`IZ@UY$ zU3XqytIBS>_WotGzvaqvZMRJKv%Rkwt#?f)^}6aHMeBv%XW|+c$xHL-QwDpqk0GH${beINBVo6u5;}b70XIA_1 zxFM3)MT5X@uIVUT)}5)})rsV}_I=~!H7HMA3HP6V{i5yo9_Qt4%hddwB(JyXMaN%@ z@^Z+#Ig)pdmp4EU>W68)TU`4Fd3mYVx1Ybas^d3kBdOH-vr zUFPfJ@}_xte^lNzTJIK@cb%7)6Un<>m0e!FmzSyE4{MI>KdWcUQZKJqd2YNc)Owfq z8!vB9R`T|(@$yzFPlr70@6RH6Z+LlEpRLcD)_S+N{=Vkrt&QZ}smiW>JG?ym9Bnri zEz{-w+pBkDC-n~R)^R+~Q$4rOqImdiA4T zPkbBo^WD0*eq?!hzn-hdr>^m;=khN0>MhjZywdJaSzNsl-gfiXX#Ue3xovluE^fOM zyu2Mdb-$WqyW_mP=G6Vd-=ViW{rXZ{UZs~e?{ocbPm;WHFE9Vd{esj3675?a$-B|Z z>+ywt$8wY^u(reIzo>N=g;_Ce$s|wa4 literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_hal_i2c_ex.d b/build/stm32f7xx_hal_i2c_ex.d new file mode 100644 index 0000000..144e88a --- /dev/null +++ b/build/stm32f7xx_hal_i2c_ex.d @@ -0,0 +1,68 @@ +build/stm32f7xx_hal_i2c_ex.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/build/stm32f7xx_hal_i2c_ex.lst b/build/stm32f7xx_hal_i2c_ex.lst new file mode 100644 index 0000000..63a41bb --- /dev/null +++ b/build/stm32f7xx_hal_i2c_ex.lst @@ -0,0 +1,634 @@ +ARM GAS /tmp/ccmx4Y0c.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_hal_i2c_ex.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c" + 19 .section .text.HAL_I2CEx_ConfigAnalogFilter,"ax",%progbits + 20 .align 1 + 21 .global HAL_I2CEx_ConfigAnalogFilter + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 HAL_I2CEx_ConfigAnalogFilter: + 27 .LVL0: + 28 .LFB141: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @file stm32f7xx_hal_i2c_ex.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @brief I2C Extended HAL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * functionalities of I2C Extended peripheral: + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * + Filter Mode Functions + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * + FastModePlus Functions + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** ****************************************************************************** + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @attention + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * Copyright (c) 2017 STMicroelectronics. + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * All rights reserved. + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * This software is licensed under terms that can be found in the LICENSE file + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * in the root directory of this software component. + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** ****************************************************************************** + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** @verbatim + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** ============================================================================== + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** ##### I2C peripheral Extended features ##### + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** ============================================================================== + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** [..] Comparing to other previous devices, the I2C interface for STM32F7xx + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** devices contains the following additional features + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** (+) Possibility to disable or enable Analog Noise Filter + ARM GAS /tmp/ccmx4Y0c.s page 2 + + + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** (+) Use of a configured Digital Noise Filter + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** (+) Disable or enable Fast Mode Plus + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** ##### How to use this driver ##### + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** ============================================================================== + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** [..] This driver provides functions to: + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** (#) Configure the enable or disable of fast mode plus driving capability using the functions : + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** (++) HAL_I2CEx_EnableFastModePlus() + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** (++) HAL_I2CEx_DisableFastModePlus() + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** @endverbatim + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** */ + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Includes ------------------------------------------------------------------*/ + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** #include "stm32f7xx_hal.h" + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /** @addtogroup STM32F7xx_HAL_Driver + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @{ + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** */ + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /** @defgroup I2CEx I2CEx + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @brief I2C Extended HAL module driver + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @{ + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** */ + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** #ifdef HAL_I2C_MODULE_ENABLED + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Private define ------------------------------------------------------------*/ + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Private macro -------------------------------------------------------------*/ + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Private variables ---------------------------------------------------------*/ + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Private functions ---------------------------------------------------------*/ + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @{ + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** */ + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @brief Filter Mode Functions + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** @verbatim + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** =============================================================================== + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** ##### Filter Mode Functions ##### + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** =============================================================================== + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** [..] This section provides functions allowing to: + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** (+) Configure Noise Filters + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** @endverbatim + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @{ + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** */ + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /** + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @brief Configure I2C Analog noise filter. + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + ARM GAS /tmp/ccmx4Y0c.s page 3 + + + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @param AnalogFilter New state of the Analog filter. + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @retval HAL status + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** */ + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** { + 29 .loc 1 92 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 34 .loc 1 92 1 is_stmt 0 view .LVU1 + 35 0000 0346 mov r3, r0 + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Check the parameters */ + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 36 .loc 1 94 3 is_stmt 1 view .LVU2 + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + 37 .loc 1 95 3 view .LVU3 + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 38 .loc 1 97 3 view .LVU4 + 39 .loc 1 97 11 is_stmt 0 view .LVU5 + 40 0002 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2 + 41 0006 D2B2 uxtb r2, r2 + 42 .loc 1 97 6 view .LVU6 + 43 0008 202A cmp r2, #32 + 44 000a 23D1 bne .L3 + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** { + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Process Locked */ + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 45 .loc 1 100 5 is_stmt 1 view .LVU7 + 46 .loc 1 100 5 view .LVU8 + 47 000c 90F84020 ldrb r2, [r0, #64] @ zero_extendqisi2 + 48 0010 012A cmp r2, #1 + 49 0012 21D0 beq .L4 + 50 .loc 1 100 5 discriminator 2 view .LVU9 + 51 0014 0122 movs r2, #1 + 52 0016 80F84020 strb r2, [r0, #64] + 53 .loc 1 100 5 discriminator 2 view .LVU10 + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 54 .loc 1 102 5 view .LVU11 + 55 .loc 1 102 17 is_stmt 0 view .LVU12 + 56 001a 2422 movs r2, #36 + 57 001c 80F84120 strb r2, [r0, #65] + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 58 .loc 1 105 5 is_stmt 1 view .LVU13 + 59 0020 0068 ldr r0, [r0] + 60 .LVL1: + 61 .loc 1 105 5 is_stmt 0 view .LVU14 + 62 0022 0268 ldr r2, [r0] + 63 0024 22F00102 bic r2, r2, #1 + 64 0028 0260 str r2, [r0] + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Reset I2Cx ANOFF bit */ + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + ARM GAS /tmp/ccmx4Y0c.s page 4 + + + 65 .loc 1 108 5 is_stmt 1 view .LVU15 + 66 .loc 1 108 9 is_stmt 0 view .LVU16 + 67 002a 1868 ldr r0, [r3] + 68 .loc 1 108 19 view .LVU17 + 69 002c 0268 ldr r2, [r0] + 70 .loc 1 108 25 view .LVU18 + 71 002e 22F48052 bic r2, r2, #4096 + 72 0032 0260 str r2, [r0] + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Set analog filter bit*/ + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** hi2c->Instance->CR1 |= AnalogFilter; + 73 .loc 1 111 5 is_stmt 1 view .LVU19 + 74 .loc 1 111 9 is_stmt 0 view .LVU20 + 75 0034 1868 ldr r0, [r3] + 76 .loc 1 111 19 view .LVU21 + 77 0036 0268 ldr r2, [r0] + 78 .loc 1 111 25 view .LVU22 + 79 0038 1143 orrs r1, r1, r2 + 80 .LVL2: + 81 .loc 1 111 25 view .LVU23 + 82 003a 0160 str r1, [r0] + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 83 .loc 1 113 5 is_stmt 1 view .LVU24 + 84 003c 1968 ldr r1, [r3] + 85 003e 0A68 ldr r2, [r1] + 86 0040 42F00102 orr r2, r2, #1 + 87 0044 0A60 str r2, [r1] + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 88 .loc 1 115 5 view .LVU25 + 89 .loc 1 115 17 is_stmt 0 view .LVU26 + 90 0046 2022 movs r2, #32 + 91 0048 83F84120 strb r2, [r3, #65] + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Process Unlocked */ + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 92 .loc 1 118 5 is_stmt 1 view .LVU27 + 93 .loc 1 118 5 view .LVU28 + 94 004c 0020 movs r0, #0 + 95 004e 83F84000 strb r0, [r3, #64] + 96 .loc 1 118 5 view .LVU29 + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** return HAL_OK; + 97 .loc 1 120 5 view .LVU30 + 98 .loc 1 120 12 is_stmt 0 view .LVU31 + 99 0052 7047 bx lr + 100 .LVL3: + 101 .L3: + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** } + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** else + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** { + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** return HAL_BUSY; + 102 .loc 1 124 12 view .LVU32 + 103 0054 0220 movs r0, #2 + 104 .LVL4: + 105 .loc 1 124 12 view .LVU33 + ARM GAS /tmp/ccmx4Y0c.s page 5 + + + 106 0056 7047 bx lr + 107 .LVL5: + 108 .L4: + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 109 .loc 1 100 5 discriminator 1 view .LVU34 + 110 0058 0220 movs r0, #2 + 111 .LVL6: + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** } + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** } + 112 .loc 1 126 1 view .LVU35 + 113 005a 7047 bx lr + 114 .cfi_endproc + 115 .LFE141: + 117 .section .text.HAL_I2CEx_ConfigDigitalFilter,"ax",%progbits + 118 .align 1 + 119 .global HAL_I2CEx_ConfigDigitalFilter + 120 .syntax unified + 121 .thumb + 122 .thumb_func + 124 HAL_I2CEx_ConfigDigitalFilter: + 125 .LVL7: + 126 .LFB142: + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /** + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @brief Configure I2C Digital noise filter. + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @retval HAL status + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** */ + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** { + 127 .loc 1 136 1 is_stmt 1 view -0 + 128 .cfi_startproc + 129 @ args = 0, pretend = 0, frame = 0 + 130 @ frame_needed = 0, uses_anonymous_args = 0 + 131 @ link register save eliminated. + 132 .loc 1 136 1 is_stmt 0 view .LVU37 + 133 0000 0346 mov r3, r0 + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** uint32_t tmpreg; + 134 .loc 1 137 3 is_stmt 1 view .LVU38 + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Check the parameters */ + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 135 .loc 1 140 3 view .LVU39 + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + 136 .loc 1 141 3 view .LVU40 + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 137 .loc 1 143 3 view .LVU41 + 138 .loc 1 143 11 is_stmt 0 view .LVU42 + 139 0002 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2 + 140 0006 D2B2 uxtb r2, r2 + 141 .loc 1 143 6 view .LVU43 + 142 0008 202A cmp r2, #32 + 143 000a 21D1 bne .L7 + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** { + ARM GAS /tmp/ccmx4Y0c.s page 6 + + + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Process Locked */ + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 144 .loc 1 146 5 is_stmt 1 view .LVU44 + 145 .loc 1 146 5 view .LVU45 + 146 000c 90F84020 ldrb r2, [r0, #64] @ zero_extendqisi2 + 147 0010 012A cmp r2, #1 + 148 0012 1FD0 beq .L8 + 149 .loc 1 146 5 discriminator 2 view .LVU46 + 150 0014 0122 movs r2, #1 + 151 0016 80F84020 strb r2, [r0, #64] + 152 .loc 1 146 5 discriminator 2 view .LVU47 + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 153 .loc 1 148 5 view .LVU48 + 154 .loc 1 148 17 is_stmt 0 view .LVU49 + 155 001a 2422 movs r2, #36 + 156 001c 80F84120 strb r2, [r0, #65] + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 157 .loc 1 151 5 is_stmt 1 view .LVU50 + 158 0020 0068 ldr r0, [r0] + 159 .LVL8: + 160 .loc 1 151 5 is_stmt 0 view .LVU51 + 161 0022 0268 ldr r2, [r0] + 162 0024 22F00102 bic r2, r2, #1 + 163 0028 0260 str r2, [r0] + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Get the old register value */ + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** tmpreg = hi2c->Instance->CR1; + 164 .loc 1 154 5 is_stmt 1 view .LVU52 + 165 .loc 1 154 18 is_stmt 0 view .LVU53 + 166 002a 1868 ldr r0, [r3] + 167 .loc 1 154 12 view .LVU54 + 168 002c 0268 ldr r2, [r0] + 169 .LVL9: + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Reset I2Cx DNF bits [11:8] */ + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** tmpreg &= ~(I2C_CR1_DNF); + 170 .loc 1 157 5 is_stmt 1 view .LVU55 + 171 .loc 1 157 12 is_stmt 0 view .LVU56 + 172 002e 22F47062 bic r2, r2, #3840 + 173 .LVL10: + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Set I2Cx DNF coefficient */ + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** tmpreg |= DigitalFilter << 8U; + 174 .loc 1 160 5 is_stmt 1 view .LVU57 + 175 .loc 1 160 12 is_stmt 0 view .LVU58 + 176 0032 42EA0122 orr r2, r2, r1, lsl #8 + 177 .LVL11: + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Store the new register value */ + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** hi2c->Instance->CR1 = tmpreg; + 178 .loc 1 163 5 is_stmt 1 view .LVU59 + 179 .loc 1 163 25 is_stmt 0 view .LVU60 + 180 0036 0260 str r2, [r0] + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + ARM GAS /tmp/ccmx4Y0c.s page 7 + + + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 181 .loc 1 165 5 is_stmt 1 view .LVU61 + 182 0038 1968 ldr r1, [r3] + 183 .LVL12: + 184 .loc 1 165 5 is_stmt 0 view .LVU62 + 185 003a 0A68 ldr r2, [r1] + 186 .LVL13: + 187 .loc 1 165 5 view .LVU63 + 188 003c 42F00102 orr r2, r2, #1 + 189 0040 0A60 str r2, [r1] + 190 .LVL14: + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 191 .loc 1 167 5 is_stmt 1 view .LVU64 + 192 .loc 1 167 17 is_stmt 0 view .LVU65 + 193 0042 2022 movs r2, #32 + 194 0044 83F84120 strb r2, [r3, #65] + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Process Unlocked */ + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 195 .loc 1 170 5 is_stmt 1 view .LVU66 + 196 .loc 1 170 5 view .LVU67 + 197 0048 0020 movs r0, #0 + 198 004a 83F84000 strb r0, [r3, #64] + 199 .loc 1 170 5 view .LVU68 + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** return HAL_OK; + 200 .loc 1 172 5 view .LVU69 + 201 .loc 1 172 12 is_stmt 0 view .LVU70 + 202 004e 7047 bx lr + 203 .LVL15: + 204 .L7: + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** } + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** else + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** { + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** return HAL_BUSY; + 205 .loc 1 176 12 view .LVU71 + 206 0050 0220 movs r0, #2 + 207 .LVL16: + 208 .loc 1 176 12 view .LVU72 + 209 0052 7047 bx lr + 210 .LVL17: + 211 .L8: + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 212 .loc 1 146 5 discriminator 1 view .LVU73 + 213 0054 0220 movs r0, #2 + 214 .LVL18: + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** } + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** } + 215 .loc 1 178 1 view .LVU74 + 216 0056 7047 bx lr + 217 .cfi_endproc + 218 .LFE142: + 220 .section .text.HAL_I2CEx_EnableFastModePlus,"ax",%progbits + 221 .align 1 + 222 .global HAL_I2CEx_EnableFastModePlus + 223 .syntax unified + ARM GAS /tmp/ccmx4Y0c.s page 8 + + + 224 .thumb + 225 .thumb_func + 227 HAL_I2CEx_EnableFastModePlus: + 228 .LVL19: + 229 .LFB143: + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /** + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @} + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** */ + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** #if (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2 + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @brief Fast Mode Plus Functions + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** @verbatim + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** =============================================================================== + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** ##### Fast Mode Plus Functions ##### + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** =============================================================================== + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** [..] This section provides functions allowing to: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** (+) Configure Fast Mode Plus + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** @endverbatim + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @{ + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** */ + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /** + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @brief Enable the I2C fast mode plus driving capability. + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @param ConfigFastModePlus Selects the pin. + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * This parameter can be one of the @ref I2CEx_FastModePlus values + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @note For I2C1, fast mode plus driving capability can be enabled on all selected + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * on each one of the following pins PB6, PB7, PB8 and PB9. + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @note For all I2C2 pins fast mode plus driving capability can be enabled + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C2 parameter. + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @note For all I2C3 pins fast mode plus driving capability can be enabled + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C3 parameter. + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @note For all I2C4 pins fast mode plus driving capability can be enabled + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C4 parameter. + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @retval None + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** */ + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** { + 230 .loc 1 216 1 is_stmt 1 view -0 + 231 .cfi_startproc + 232 @ args = 0, pretend = 0, frame = 8 + 233 @ frame_needed = 0, uses_anonymous_args = 0 + 234 @ link register save eliminated. + 235 .loc 1 216 1 is_stmt 0 view .LVU76 + 236 0000 82B0 sub sp, sp, #8 + 237 .LCFI0: + 238 .cfi_def_cfa_offset 8 + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Check the parameter */ + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + 239 .loc 1 218 3 is_stmt 1 view .LVU77 + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Enable SYSCFG clock */ + ARM GAS /tmp/ccmx4Y0c.s page 9 + + + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 240 .loc 1 221 3 view .LVU78 + 241 .LBB2: + 242 .loc 1 221 3 view .LVU79 + 243 .loc 1 221 3 view .LVU80 + 244 0002 084B ldr r3, .L11 + 245 0004 5A6C ldr r2, [r3, #68] + 246 0006 42F48042 orr r2, r2, #16384 + 247 000a 5A64 str r2, [r3, #68] + 248 .loc 1 221 3 view .LVU81 + 249 000c 5B6C ldr r3, [r3, #68] + 250 000e 03F48043 and r3, r3, #16384 + 251 0012 0193 str r3, [sp, #4] + 252 .loc 1 221 3 view .LVU82 + 253 0014 019B ldr r3, [sp, #4] + 254 .LBE2: + 255 .loc 1 221 3 view .LVU83 + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Enable fast mode plus driving capability for selected pin */ + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** SET_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus); + 256 .loc 1 224 3 view .LVU84 + 257 0016 044A ldr r2, .L11+4 + 258 0018 5368 ldr r3, [r2, #4] + 259 001a 0343 orrs r3, r3, r0 + 260 001c 5360 str r3, [r2, #4] + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** } + 261 .loc 1 225 1 is_stmt 0 view .LVU85 + 262 001e 02B0 add sp, sp, #8 + 263 .LCFI1: + 264 .cfi_def_cfa_offset 0 + 265 @ sp needed + 266 0020 7047 bx lr + 267 .L12: + 268 0022 00BF .align 2 + 269 .L11: + 270 0024 00380240 .word 1073887232 + 271 0028 00380140 .word 1073821696 + 272 .cfi_endproc + 273 .LFE143: + 275 .section .text.HAL_I2CEx_DisableFastModePlus,"ax",%progbits + 276 .align 1 + 277 .global HAL_I2CEx_DisableFastModePlus + 278 .syntax unified + 279 .thumb + 280 .thumb_func + 282 HAL_I2CEx_DisableFastModePlus: + 283 .LVL20: + 284 .LFB144: + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /** + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @brief Disable the I2C fast mode plus driving capability. + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @param ConfigFastModePlus Selects the pin. + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * This parameter can be one of the @ref I2CEx_FastModePlus values + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @note For I2C1, fast mode plus driving capability can be disabled on all selected + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * on each one of the following pins PB6, PB7, PB8 and PB9. + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + ARM GAS /tmp/ccmx4Y0c.s page 10 + + + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @note For all I2C2 pins fast mode plus driving capability can be disabled + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C2 parameter. + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @note For all I2C3 pins fast mode plus driving capability can be disabled + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C3 parameter. + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @note For all I2C4 pins fast mode plus driving capability can be disabled + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C4 parameter. + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** * @retval None + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** */ + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** { + 285 .loc 1 245 1 is_stmt 1 view -0 + 286 .cfi_startproc + 287 @ args = 0, pretend = 0, frame = 8 + 288 @ frame_needed = 0, uses_anonymous_args = 0 + 289 @ link register save eliminated. + 290 .loc 1 245 1 is_stmt 0 view .LVU87 + 291 0000 82B0 sub sp, sp, #8 + 292 .LCFI2: + 293 .cfi_def_cfa_offset 8 + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Check the parameter */ + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + 294 .loc 1 247 3 is_stmt 1 view .LVU88 + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Enable SYSCFG clock */ + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 295 .loc 1 250 3 view .LVU89 + 296 .LBB3: + 297 .loc 1 250 3 view .LVU90 + 298 .loc 1 250 3 view .LVU91 + 299 0002 084B ldr r3, .L15 + 300 0004 5A6C ldr r2, [r3, #68] + 301 0006 42F48042 orr r2, r2, #16384 + 302 000a 5A64 str r2, [r3, #68] + 303 .loc 1 250 3 view .LVU92 + 304 000c 5B6C ldr r3, [r3, #68] + 305 000e 03F48043 and r3, r3, #16384 + 306 0012 0193 str r3, [sp, #4] + 307 .loc 1 250 3 view .LVU93 + 308 0014 019B ldr r3, [sp, #4] + 309 .LBE3: + 310 .loc 1 250 3 view .LVU94 + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** /* Disable fast mode plus driving capability for selected pin */ + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus); + 311 .loc 1 253 3 view .LVU95 + 312 0016 044A ldr r2, .L15+4 + 313 0018 5368 ldr r3, [r2, #4] + 314 001a 23EA0003 bic r3, r3, r0 + 315 001e 5360 str r3, [r2, #4] + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c **** } + 316 .loc 1 254 1 is_stmt 0 view .LVU96 + 317 0020 02B0 add sp, sp, #8 + 318 .LCFI3: + 319 .cfi_def_cfa_offset 0 + 320 @ sp needed + 321 0022 7047 bx lr + ARM GAS /tmp/ccmx4Y0c.s page 11 + + + 322 .L16: + 323 .align 2 + 324 .L15: + 325 0024 00380240 .word 1073887232 + 326 0028 00380140 .word 1073821696 + 327 .cfi_endproc + 328 .LFE144: + 330 .text + 331 .Letext0: + 332 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 333 .file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 334 .file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 335 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h" + 336 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h" + ARM GAS /tmp/ccmx4Y0c.s page 12 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_i2c_ex.c + /tmp/ccmx4Y0c.s:20 .text.HAL_I2CEx_ConfigAnalogFilter:00000000 $t + /tmp/ccmx4Y0c.s:26 .text.HAL_I2CEx_ConfigAnalogFilter:00000000 HAL_I2CEx_ConfigAnalogFilter + /tmp/ccmx4Y0c.s:118 .text.HAL_I2CEx_ConfigDigitalFilter:00000000 $t + /tmp/ccmx4Y0c.s:124 .text.HAL_I2CEx_ConfigDigitalFilter:00000000 HAL_I2CEx_ConfigDigitalFilter + /tmp/ccmx4Y0c.s:221 .text.HAL_I2CEx_EnableFastModePlus:00000000 $t + /tmp/ccmx4Y0c.s:227 .text.HAL_I2CEx_EnableFastModePlus:00000000 HAL_I2CEx_EnableFastModePlus + /tmp/ccmx4Y0c.s:270 .text.HAL_I2CEx_EnableFastModePlus:00000024 $d + /tmp/ccmx4Y0c.s:276 .text.HAL_I2CEx_DisableFastModePlus:00000000 $t + /tmp/ccmx4Y0c.s:282 .text.HAL_I2CEx_DisableFastModePlus:00000000 HAL_I2CEx_DisableFastModePlus + /tmp/ccmx4Y0c.s:325 .text.HAL_I2CEx_DisableFastModePlus:00000024 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32f7xx_hal_i2c_ex.o b/build/stm32f7xx_hal_i2c_ex.o new file mode 100644 index 0000000000000000000000000000000000000000..7e37030263ff752b1436ce4bf3a22c7ddf60956f GIT binary patch literal 11256 zcmb7K4Rl+@m7e#WB-_uHpB>wYLxQ8&P7@&hPar@7mL(-Iv11`AoRH8}WJ|KN$dXr* zLqcKsEk7;YKm$!7?WR59x4VUwrH7yHDJ*mkrKjDc&~CO%S;r4sE|nh`MVHA%0sW zITbg(y6UH3=#Hum$m^QxE~0ej`A%XwSHkIfweuD*ji;fmceh4KK&!5Tfbmz<+_(5L zupCLLSoI~CFAZOgG=sL3-Lp1JFbVJQXvUk6tn?>y&GWdXI zQ18{9#x;7)K6GntAv@RUs^6O6s81NzE81Z`U5)n7>y3wKz8%%($q6?p+9O;vAySqzHiUzEt-aO(shf496GZiDW1n7=fgXI&Cyd*aGSU6Q z__CrM=8tKT`xRYn{xi|HE4t47FPh99if%A>V(E>qD7v|3IE=v_P;_g}FgfX~ie75| zC+Xj*XpgDWWbaaRr};5W?x3PqiQ4_-ov-P}cWEBC8*k|~U&YMiTK=~Z6Xv(jYW!Z& z4s$zcy`$*r8s9L6@jr^LGY4o|M-|;*`e^BnDZ1Hwl7{iFqFc?|$eaJG)?}%zG+@9T|U$8`0MRpua#=Y(qSHNQyxeW2(y=0oI$4;8)6yodDvp!!>H zS|tCGY9BQ3Bl(XN?KdAHd0}vWo6Q`#Su;51f@V9l>xzz;)1+@Gdb{~JwL1)sxl7Du z(s!!%UFJesW|yMl<})N;rTR;m*N{J}Rr_>}kHVlv(M9v8ByTGDJ?1WwueIBaj;l5E z8|3gh#kgKGFCz`NV%(&e_tKE+72_7oe25s9V%(~U+9k9KjfSxo#`J1O2b@+{rBP0C ztkhnFLH7-45pE|MH1`0iy1Rxtrny6CwehzQQY!u038{jm6Ye8u*Dz%C;8<(Cf`9Ecw@@yuntvjIMT+d{kH3COC&u6m1dK;s04l&tm z9VOiWldaa{BzysrORW#d)F_i4s|T}khM4TMe5AXL$yL^Kn1*vFldFZ%fmu0s=`Psd z2|JUT0Tb?C=_3zK*gcG9-F=u=%RK^v4)@>C2!(Mv^*yCO4{(rH!*i(Za^Bo<421P- zC_BHnjOxg=R-PR6r8aVw-r=y`rjhMyBe&@tYpe~Ba^BWPA+C3E z8uuN`>oEkqW4-kl4f_C-gVsAl-pQojdX+jl$mC|rN#xg=9I+0OsY6T#tsl`$zS(9U z2NCNj>i2M)y^7ndi>UP;CNB|<4mv^>IGS)c3DHb9@R~8mM#qP^8%Jr%_vtpL8O`+` zS5M9Ts92Zd=IUeD3#$!oaLvZYE9l6zj$5m(^(1^QlXcb+Ou=;?lMU7y^y2a|*=%jb zj9jzv@i2zy+RUv>g%Kd-EyibHlGoTZrM(Zzoy1MJaS4z60JJ*YuVGZn-2vEdcYhXU zSGk`+{WSMqp!IZj9-Ljm_$764x$y|J9b`vY-LLgQzVz1ExLz2_EwPMTU{ttC@GS>}-)t+RAmh<{>o zy^K=V&p1j4Wt6&JY;$7tdWTo;OxG{kHb`4x?p^wsFti8kX=vhblnoP}B(v(k>a;AtUN z(+x#?9%73^R6Ev1`dY9Rors0F7CRuSoiJqJ-*yF=xB)KEj?9`MGg_0WOdMG~uZfpu zO`M{oU|zeiNsb@dVmmJVN}*+8Wk~_+pxx-FdYs#qv`B?8S$+i9gSeK;k=-l<_zlpn z;lh-!!CX$&w!w+o&e;wwK^t{o8{g?8<1Lt34X!0Gknx=%GM)e(#RW#AwxYhN)~H`n zzs=RCg|r3?OYao5wda8ew=Tp1b58BKwP)83Hz88j3IZn!z}GHK8*b9Tt6Gkxo?1MS zG- z(VP>-4Y2}2 zr)wY7y9M6YX%FMl{Q30mM841yj*JfUZ#-+yp6F)pNYv)`g!2=kXQq(v$)v}7CMPC( zV)?1AY%ZJVO2o#~J$(b+{oQ>%>Fh*iCY}(=ly5XV9PaTacBdy2usdtIXLyd}yq!Ww zh(d8{pg&2&NyReJbpJ#&v8Q{2MqDVy@n+hcB8RcmnUDhmnY&Ugo=AcXm(F2N#pYw9 z6PqoZnsCbHFkTXxOLH2o_NHcMEo!dyPN%C+!&|a`0o~R&I~&1vy3TibT%*n!)SEoc z#UA3!Qbe}zP?8#y>RehUxGnJlZ5rCIE>-gk`Fv4TFO3Sm=?{e?ArVaE)6*&11*3_n zp_zQ4C=HOaY+nXKp|OzUk$>eh;h_@479u}JL))Vx!{JC^tC+!X`_7Eore>E#dOJ8W zLOu{%bKzn>QJhGTdj-{FQ$w*rf>t9@D2QMzk0qJyrx+_H)HG;%LhAX``NTvqoy&?; zd@7dTBjw?vz}U8k@TVu!#aL!zI#W#KMTIYA+9}O36bJ_*w%aSD>`@J8v{k)y@=UOT;_= zq-5bs#j@E%MuaE?N--zX&GgVrG8ru9%gpr2MV7m}d_&n0OG&0OP~?tPD@37JiYx@I z9a(C6rRb3$)c$mn|6m0fZ|7_@U z`tu^mg+vM=EQ8R_5~YD_C);(cclnaRb9U3m1_fU_eGMl3&(+JJ|m-Df4brp`!CcgLqa zU6c5WUlz+JyZSv{W1y08q=v47ofZqAlQUVFB1=3m+K2NH$IXwWw_M;M%FA(t$|cXIJ%z}N~II*O$)N*R0h6yr0l(ie6bC*HQLDq$hE)pnsc z^p0c6OJ_WBDo*df_6U7&x1Dbv#A1`rcaCRO-`aCz4CNDGJ1wYFCAx@0%3?r008Yef1b#q37cViSO;hEk@7aLR*Qd^Q=JEsBpQfMr(Al zdV!-^Yta@Nt=eMk6m6;2rnS@4{+v?Ia)@_6E^jvILA$IN{C1*P_{6KK67e&MXszJP zzQ+*Tz(>x?c6@RvD~52*X?NjwLVQRo$>3$TtQewdj(pV|d3=H?D~7=LhO%Pdg{-_7 z0x$Sw#jwBTl{kj5N_DCjqHzw5?*e7T5G`dC$(OG%(ThYIB*@G3p0@!0JC|vShXwH0 z#Y|H?EP#J@SJ0T>C!F4$MbQ~od13y8k~d1J@#IG)`;7gBlwmi{_ryV~q&MJ03?W=V zULquK5H2Q!t5y)gB{VnU4=~dEJ<(pq&5UD=5yo-GNyf_=uVVZ%$oMMbQAPvXi|jTr zb}$Yw`WVBE6O0AM>lpVl9%lSI#%CB`WPFwJD5HVxEBj|0VDvFY7!!=U8E<5~lktAW z?=$`bA0*no6Fa?2RI88rFgoayC&tyn*v{C;ILJ80_-Bk$j8`zy513@?k1@y?Wy~^O$#@InLB?+}KF;_f#v_ccF}};_z_)K2PZMK1V;|!n zb9#rzi-|BVpWzcc=t5cz;ke#Xs=aYD>L#YjKM6J21G`5!d> zLP7k`Gv3U2E932q2N@4BKEn7I8X7n)9zmE|A z3`TkWfIgGya~Qph0Y>_>#&ND z7L5??avg!#HqxKeM1Ga}kjK$2_2#bY8t(5wLdXx$c?Nm<`IqcVJ^X4W^)8GX(?LQSM0a8DR53OVEaq)YsT$thilUp|v_$tfzE*V;qkHb7PQ?d<`9&(9 zhUUu5^Gq~XWWFb(ZoDdV#}nf-lhJfGnZrP3JvKg$S6flmn#oO+ld*g(JDI?2X7x|z zWYXD$vIuvG?up!#{0LR1mCVPcAmj~=cE^gve0qGQ2($l>LeJw^Ry>K?h1ROPV2Nc} zjyuWWQ9_ova@0m;B`%7uPm@~>nYsO{-$u|>dNZMC#Bw>>^V>;)iy9wIx?JwJps5d4 zDE6s*1y{LTGl==*e!z01LuC+hk0CFrLN=&8feTwf4C10vhZlh3ycfw2)Gy(WaVZ^C z#c{lve6Nh5s=t~e_ig+G0{!!WDysUgV3hakz^3~K8fg#GTaW7ZP1KbRs=|+aLHke@ z)%H3V<@WAgVeenENB;w%?0tl~(m_>R0eh>c!bP>609|hHC$KjN9@&FR$zB5#ln&V9 zZZsCvqJma!b*PlvtNV-)9<-A^9AzbYOCd)(y|}2fF2HjREdUp4ql^BpvRv-1Q|#EC zD@VDHpbroob>2z&jC0II$S%iJLD shurgE(z_O2)NcbW>Qn7CRK=cCg}9w6T$DZXQMp_O&iaHvj+t literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_hal_msp.d b/build/stm32f7xx_hal_msp.d new file mode 100644 index 0000000..be49416 --- /dev/null +++ b/build/stm32f7xx_hal_msp.d @@ -0,0 +1,92 @@ +build/stm32f7xx_hal_msp.o: Src/stm32f7xx_hal_msp.c Inc/main.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h +Inc/main.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h: diff --git a/build/stm32f7xx_hal_msp.lst b/build/stm32f7xx_hal_msp.lst new file mode 100644 index 0000000..3edf55b --- /dev/null +++ b/build/stm32f7xx_hal_msp.lst @@ -0,0 +1,2263 @@ +ARM GAS /tmp/cc5mtMNQ.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_hal_msp.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Src/stm32f7xx_hal_msp.c" + 19 .section .text.HAL_MspInit,"ax",%progbits + 20 .align 1 + 21 .global HAL_MspInit + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 HAL_MspInit: + 27 .LFB1183: + 1:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN Header */ + 2:Src/stm32f7xx_hal_msp.c **** /** + 3:Src/stm32f7xx_hal_msp.c **** ****************************************************************************** + 4:Src/stm32f7xx_hal_msp.c **** * @file stm32f7xx_hal_msp.c + 5:Src/stm32f7xx_hal_msp.c **** * @brief This file provides code for the MSP Initialization + 6:Src/stm32f7xx_hal_msp.c **** * and de-Initialization codes. + 7:Src/stm32f7xx_hal_msp.c **** ****************************************************************************** + 8:Src/stm32f7xx_hal_msp.c **** * @attention + 9:Src/stm32f7xx_hal_msp.c **** * + 10:Src/stm32f7xx_hal_msp.c **** * Copyright (c) 2023 STMicroelectronics. + 11:Src/stm32f7xx_hal_msp.c **** * All rights reserved. + 12:Src/stm32f7xx_hal_msp.c **** * + 13:Src/stm32f7xx_hal_msp.c **** * This software is licensed under terms that can be found in the LICENSE file + 14:Src/stm32f7xx_hal_msp.c **** * in the root directory of this software component. + 15:Src/stm32f7xx_hal_msp.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 16:Src/stm32f7xx_hal_msp.c **** * + 17:Src/stm32f7xx_hal_msp.c **** ****************************************************************************** + 18:Src/stm32f7xx_hal_msp.c **** */ + 19:Src/stm32f7xx_hal_msp.c **** /* USER CODE END Header */ + 20:Src/stm32f7xx_hal_msp.c **** + 21:Src/stm32f7xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/ + 22:Src/stm32f7xx_hal_msp.c **** #include "main.h" + 23:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN Includes */ + 24:Src/stm32f7xx_hal_msp.c **** + 25:Src/stm32f7xx_hal_msp.c **** /* USER CODE END Includes */ + 26:Src/stm32f7xx_hal_msp.c **** + 27:Src/stm32f7xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/ + 28:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TD */ + 29:Src/stm32f7xx_hal_msp.c **** + 30:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TD */ + 31:Src/stm32f7xx_hal_msp.c **** + ARM GAS /tmp/cc5mtMNQ.s page 2 + + + 32:Src/stm32f7xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/ + 33:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN Define */ + 34:Src/stm32f7xx_hal_msp.c **** + 35:Src/stm32f7xx_hal_msp.c **** /* USER CODE END Define */ + 36:Src/stm32f7xx_hal_msp.c **** + 37:Src/stm32f7xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/ + 38:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN Macro */ + 39:Src/stm32f7xx_hal_msp.c **** + 40:Src/stm32f7xx_hal_msp.c **** /* USER CODE END Macro */ + 41:Src/stm32f7xx_hal_msp.c **** + 42:Src/stm32f7xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/ + 43:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN PV */ + 44:Src/stm32f7xx_hal_msp.c **** + 45:Src/stm32f7xx_hal_msp.c **** /* USER CODE END PV */ + 46:Src/stm32f7xx_hal_msp.c **** + 47:Src/stm32f7xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/ + 48:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN PFP */ + 49:Src/stm32f7xx_hal_msp.c **** + 50:Src/stm32f7xx_hal_msp.c **** /* USER CODE END PFP */ + 51:Src/stm32f7xx_hal_msp.c **** + 52:Src/stm32f7xx_hal_msp.c **** /* External functions --------------------------------------------------------*/ + 53:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN ExternalFunctions */ + 54:Src/stm32f7xx_hal_msp.c **** + 55:Src/stm32f7xx_hal_msp.c **** /* USER CODE END ExternalFunctions */ + 56:Src/stm32f7xx_hal_msp.c **** + 57:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN 0 */ + 58:Src/stm32f7xx_hal_msp.c **** + 59:Src/stm32f7xx_hal_msp.c **** /* USER CODE END 0 */ + 60:Src/stm32f7xx_hal_msp.c **** + 61:Src/stm32f7xx_hal_msp.c **** void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + 62:Src/stm32f7xx_hal_msp.c **** /** + 63:Src/stm32f7xx_hal_msp.c **** * Initializes the Global MSP. + 64:Src/stm32f7xx_hal_msp.c **** */ + 65:Src/stm32f7xx_hal_msp.c **** void HAL_MspInit(void) + 66:Src/stm32f7xx_hal_msp.c **** { + 28 .loc 1 66 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 8 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 0000 82B0 sub sp, sp, #8 + 34 .LCFI0: + 35 .cfi_def_cfa_offset 8 + 67:Src/stm32f7xx_hal_msp.c **** + 68:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN MspInit 0 */ + 69:Src/stm32f7xx_hal_msp.c **** + 70:Src/stm32f7xx_hal_msp.c **** /* USER CODE END MspInit 0 */ + 71:Src/stm32f7xx_hal_msp.c **** + 72:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 36 .loc 1 72 3 view .LVU1 + 37 .LBB2: + 38 .loc 1 72 3 view .LVU2 + 39 .loc 1 72 3 view .LVU3 + 40 0002 0A4B ldr r3, .L3 + 41 0004 1A6C ldr r2, [r3, #64] + 42 0006 42F08052 orr r2, r2, #268435456 + 43 000a 1A64 str r2, [r3, #64] + ARM GAS /tmp/cc5mtMNQ.s page 3 + + + 44 .loc 1 72 3 view .LVU4 + 45 000c 1A6C ldr r2, [r3, #64] + 46 000e 02F08052 and r2, r2, #268435456 + 47 0012 0092 str r2, [sp] + 48 .loc 1 72 3 view .LVU5 + 49 0014 009A ldr r2, [sp] + 50 .LBE2: + 51 .loc 1 72 3 view .LVU6 + 73:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 52 .loc 1 73 3 view .LVU7 + 53 .LBB3: + 54 .loc 1 73 3 view .LVU8 + 55 .loc 1 73 3 view .LVU9 + 56 0016 5A6C ldr r2, [r3, #68] + 57 0018 42F48042 orr r2, r2, #16384 + 58 001c 5A64 str r2, [r3, #68] + 59 .loc 1 73 3 view .LVU10 + 60 001e 5B6C ldr r3, [r3, #68] + 61 0020 03F48043 and r3, r3, #16384 + 62 0024 0193 str r3, [sp, #4] + 63 .loc 1 73 3 view .LVU11 + 64 0026 019B ldr r3, [sp, #4] + 65 .LBE3: + 66 .loc 1 73 3 view .LVU12 + 74:Src/stm32f7xx_hal_msp.c **** + 75:Src/stm32f7xx_hal_msp.c **** /* System interrupt init*/ + 76:Src/stm32f7xx_hal_msp.c **** + 77:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN MspInit 1 */ + 78:Src/stm32f7xx_hal_msp.c **** + 79:Src/stm32f7xx_hal_msp.c **** /* USER CODE END MspInit 1 */ + 80:Src/stm32f7xx_hal_msp.c **** } + 67 .loc 1 80 1 is_stmt 0 view .LVU13 + 68 0028 02B0 add sp, sp, #8 + 69 .LCFI1: + 70 .cfi_def_cfa_offset 0 + 71 @ sp needed + 72 002a 7047 bx lr + 73 .L4: + 74 .align 2 + 75 .L3: + 76 002c 00380240 .word 1073887232 + 77 .cfi_endproc + 78 .LFE1183: + 80 .section .text.HAL_ADC_MspInit,"ax",%progbits + 81 .align 1 + 82 .global HAL_ADC_MspInit + 83 .syntax unified + 84 .thumb + 85 .thumb_func + 87 HAL_ADC_MspInit: + 88 .LVL0: + 89 .LFB1184: + 81:Src/stm32f7xx_hal_msp.c **** + 82:Src/stm32f7xx_hal_msp.c **** /** + 83:Src/stm32f7xx_hal_msp.c **** * @brief ADC MSP Initialization + 84:Src/stm32f7xx_hal_msp.c **** * This function configures the hardware resources used in this example + 85:Src/stm32f7xx_hal_msp.c **** * @param hadc: ADC handle pointer + ARM GAS /tmp/cc5mtMNQ.s page 4 + + + 86:Src/stm32f7xx_hal_msp.c **** * @retval None + 87:Src/stm32f7xx_hal_msp.c **** */ + 88:Src/stm32f7xx_hal_msp.c **** void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) + 89:Src/stm32f7xx_hal_msp.c **** { + 90 .loc 1 89 1 is_stmt 1 view -0 + 91 .cfi_startproc + 92 @ args = 0, pretend = 0, frame = 48 + 93 @ frame_needed = 0, uses_anonymous_args = 0 + 94 .loc 1 89 1 is_stmt 0 view .LVU15 + 95 0000 30B5 push {r4, r5, lr} + 96 .LCFI2: + 97 .cfi_def_cfa_offset 12 + 98 .cfi_offset 4, -12 + 99 .cfi_offset 5, -8 + 100 .cfi_offset 14, -4 + 101 0002 8DB0 sub sp, sp, #52 + 102 .LCFI3: + 103 .cfi_def_cfa_offset 64 + 90:Src/stm32f7xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; + 104 .loc 1 90 3 is_stmt 1 view .LVU16 + 105 .loc 1 90 20 is_stmt 0 view .LVU17 + 106 0004 0023 movs r3, #0 + 107 0006 0793 str r3, [sp, #28] + 108 0008 0893 str r3, [sp, #32] + 109 000a 0993 str r3, [sp, #36] + 110 000c 0A93 str r3, [sp, #40] + 111 000e 0B93 str r3, [sp, #44] + 91:Src/stm32f7xx_hal_msp.c **** if(hadc->Instance==ADC1) + 112 .loc 1 91 3 is_stmt 1 view .LVU18 + 113 .loc 1 91 10 is_stmt 0 view .LVU19 + 114 0010 0368 ldr r3, [r0] + 115 .loc 1 91 5 view .LVU20 + 116 0012 384A ldr r2, .L11 + 117 0014 9342 cmp r3, r2 + 118 0016 04D0 beq .L9 + 92:Src/stm32f7xx_hal_msp.c **** { + 93:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspInit 0 */ + 94:Src/stm32f7xx_hal_msp.c **** + 95:Src/stm32f7xx_hal_msp.c **** /* USER CODE END ADC1_MspInit 0 */ + 96:Src/stm32f7xx_hal_msp.c **** /* Peripheral clock enable */ + 97:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_ADC1_CLK_ENABLE(); + 98:Src/stm32f7xx_hal_msp.c **** + 99:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); + 100:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 101:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 102:Src/stm32f7xx_hal_msp.c **** /**ADC1 GPIO Configuration + 103:Src/stm32f7xx_hal_msp.c **** PC0 ------> ADC1_IN10 + 104:Src/stm32f7xx_hal_msp.c **** PC1 ------> ADC1_IN11 + 105:Src/stm32f7xx_hal_msp.c **** PA2 ------> ADC1_IN2 + 106:Src/stm32f7xx_hal_msp.c **** PB0 ------> ADC1_IN8 + 107:Src/stm32f7xx_hal_msp.c **** PB1 ------> ADC1_IN9 + 108:Src/stm32f7xx_hal_msp.c **** */ + 109:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + 110:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 111:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 112:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 113:Src/stm32f7xx_hal_msp.c **** + ARM GAS /tmp/cc5mtMNQ.s page 5 + + + 114:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_2; + 115:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 116:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 117:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 118:Src/stm32f7xx_hal_msp.c **** + 119:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + 120:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 121:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 122:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 123:Src/stm32f7xx_hal_msp.c **** + 124:Src/stm32f7xx_hal_msp.c **** /* ADC1 interrupt Init */ + 125:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_SetPriority(ADC_IRQn, 0, 0); + 126:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(ADC_IRQn); + 127:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspInit 1 */ + 128:Src/stm32f7xx_hal_msp.c **** + 129:Src/stm32f7xx_hal_msp.c **** /* USER CODE END ADC1_MspInit 1 */ + 130:Src/stm32f7xx_hal_msp.c **** } + 131:Src/stm32f7xx_hal_msp.c **** else if(hadc->Instance==ADC3) + 119 .loc 1 131 8 is_stmt 1 view .LVU21 + 120 .loc 1 131 10 is_stmt 0 view .LVU22 + 121 0018 374A ldr r2, .L11+4 + 122 001a 9342 cmp r3, r2 + 123 001c 46D0 beq .L10 + 124 .LVL1: + 125 .L5: + 132:Src/stm32f7xx_hal_msp.c **** { + 133:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN ADC3_MspInit 0 */ + 134:Src/stm32f7xx_hal_msp.c **** + 135:Src/stm32f7xx_hal_msp.c **** /* USER CODE END ADC3_MspInit 0 */ + 136:Src/stm32f7xx_hal_msp.c **** /* Peripheral clock enable */ + 137:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_ADC3_CLK_ENABLE(); + 138:Src/stm32f7xx_hal_msp.c **** + 139:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOF_CLK_ENABLE(); + 140:Src/stm32f7xx_hal_msp.c **** /**ADC3 GPIO Configuration + 141:Src/stm32f7xx_hal_msp.c **** PF5 ------> ADC3_IN15 + 142:Src/stm32f7xx_hal_msp.c **** */ + 143:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_5; + 144:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 145:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 146:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + 147:Src/stm32f7xx_hal_msp.c **** + 148:Src/stm32f7xx_hal_msp.c **** /* ADC3 interrupt Init */ + 149:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_SetPriority(ADC_IRQn, 0, 0); + 150:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(ADC_IRQn); + 151:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN ADC3_MspInit 1 */ + 152:Src/stm32f7xx_hal_msp.c **** + 153:Src/stm32f7xx_hal_msp.c **** /* USER CODE END ADC3_MspInit 1 */ + 154:Src/stm32f7xx_hal_msp.c **** } + 155:Src/stm32f7xx_hal_msp.c **** + 156:Src/stm32f7xx_hal_msp.c **** } + 126 .loc 1 156 1 view .LVU23 + 127 001e 0DB0 add sp, sp, #52 + 128 .LCFI4: + 129 .cfi_remember_state + 130 .cfi_def_cfa_offset 12 + 131 @ sp needed + 132 0020 30BD pop {r4, r5, pc} + ARM GAS /tmp/cc5mtMNQ.s page 6 + + + 133 .LVL2: + 134 .L9: + 135 .LCFI5: + 136 .cfi_restore_state + 97:Src/stm32f7xx_hal_msp.c **** + 137 .loc 1 97 5 is_stmt 1 view .LVU24 + 138 .LBB4: + 97:Src/stm32f7xx_hal_msp.c **** + 139 .loc 1 97 5 view .LVU25 + 97:Src/stm32f7xx_hal_msp.c **** + 140 .loc 1 97 5 view .LVU26 + 141 0022 364B ldr r3, .L11+8 + 142 0024 5A6C ldr r2, [r3, #68] + 143 0026 42F48072 orr r2, r2, #256 + 144 002a 5A64 str r2, [r3, #68] + 97:Src/stm32f7xx_hal_msp.c **** + 145 .loc 1 97 5 view .LVU27 + 146 002c 5A6C ldr r2, [r3, #68] + 147 002e 02F48072 and r2, r2, #256 + 148 0032 0192 str r2, [sp, #4] + 97:Src/stm32f7xx_hal_msp.c **** + 149 .loc 1 97 5 view .LVU28 + 150 0034 019A ldr r2, [sp, #4] + 151 .LBE4: + 97:Src/stm32f7xx_hal_msp.c **** + 152 .loc 1 97 5 view .LVU29 + 99:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 153 .loc 1 99 5 view .LVU30 + 154 .LBB5: + 99:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 155 .loc 1 99 5 view .LVU31 + 99:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 156 .loc 1 99 5 view .LVU32 + 157 0036 1A6B ldr r2, [r3, #48] + 158 0038 42F00402 orr r2, r2, #4 + 159 003c 1A63 str r2, [r3, #48] + 99:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 160 .loc 1 99 5 view .LVU33 + 161 003e 1A6B ldr r2, [r3, #48] + 162 0040 02F00402 and r2, r2, #4 + 163 0044 0292 str r2, [sp, #8] + 99:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 164 .loc 1 99 5 view .LVU34 + 165 0046 029A ldr r2, [sp, #8] + 166 .LBE5: + 99:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 167 .loc 1 99 5 view .LVU35 + 100:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 168 .loc 1 100 5 view .LVU36 + 169 .LBB6: + 100:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 170 .loc 1 100 5 view .LVU37 + 100:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 171 .loc 1 100 5 view .LVU38 + 172 0048 1A6B ldr r2, [r3, #48] + 173 004a 42F00102 orr r2, r2, #1 + 174 004e 1A63 str r2, [r3, #48] + ARM GAS /tmp/cc5mtMNQ.s page 7 + + + 100:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 175 .loc 1 100 5 view .LVU39 + 176 0050 1A6B ldr r2, [r3, #48] + 177 0052 02F00102 and r2, r2, #1 + 178 0056 0392 str r2, [sp, #12] + 100:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 179 .loc 1 100 5 view .LVU40 + 180 0058 039A ldr r2, [sp, #12] + 181 .LBE6: + 100:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 182 .loc 1 100 5 view .LVU41 + 101:Src/stm32f7xx_hal_msp.c **** /**ADC1 GPIO Configuration + 183 .loc 1 101 5 view .LVU42 + 184 .LBB7: + 101:Src/stm32f7xx_hal_msp.c **** /**ADC1 GPIO Configuration + 185 .loc 1 101 5 view .LVU43 + 101:Src/stm32f7xx_hal_msp.c **** /**ADC1 GPIO Configuration + 186 .loc 1 101 5 view .LVU44 + 187 005a 1A6B ldr r2, [r3, #48] + 188 005c 42F00202 orr r2, r2, #2 + 189 0060 1A63 str r2, [r3, #48] + 101:Src/stm32f7xx_hal_msp.c **** /**ADC1 GPIO Configuration + 190 .loc 1 101 5 view .LVU45 + 191 0062 1B6B ldr r3, [r3, #48] + 192 0064 03F00203 and r3, r3, #2 + 193 0068 0493 str r3, [sp, #16] + 101:Src/stm32f7xx_hal_msp.c **** /**ADC1 GPIO Configuration + 194 .loc 1 101 5 view .LVU46 + 195 006a 049B ldr r3, [sp, #16] + 196 .LBE7: + 101:Src/stm32f7xx_hal_msp.c **** /**ADC1 GPIO Configuration + 197 .loc 1 101 5 view .LVU47 + 109:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 198 .loc 1 109 5 view .LVU48 + 109:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 199 .loc 1 109 25 is_stmt 0 view .LVU49 + 200 006c 0324 movs r4, #3 + 201 006e 0794 str r4, [sp, #28] + 110:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 202 .loc 1 110 5 is_stmt 1 view .LVU50 + 110:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 203 .loc 1 110 26 is_stmt 0 view .LVU51 + 204 0070 0894 str r4, [sp, #32] + 111:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 205 .loc 1 111 5 is_stmt 1 view .LVU52 + 112:Src/stm32f7xx_hal_msp.c **** + 206 .loc 1 112 5 view .LVU53 + 207 0072 07A9 add r1, sp, #28 + 208 0074 2248 ldr r0, .L11+12 + 209 .LVL3: + 112:Src/stm32f7xx_hal_msp.c **** + 210 .loc 1 112 5 is_stmt 0 view .LVU54 + 211 0076 FFF7FEFF bl HAL_GPIO_Init + 212 .LVL4: + 114:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 213 .loc 1 114 5 is_stmt 1 view .LVU55 + 114:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + ARM GAS /tmp/cc5mtMNQ.s page 8 + + + 214 .loc 1 114 25 is_stmt 0 view .LVU56 + 215 007a 0423 movs r3, #4 + 216 007c 0793 str r3, [sp, #28] + 115:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 217 .loc 1 115 5 is_stmt 1 view .LVU57 + 115:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 218 .loc 1 115 26 is_stmt 0 view .LVU58 + 219 007e 0894 str r4, [sp, #32] + 116:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 220 .loc 1 116 5 is_stmt 1 view .LVU59 + 116:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 221 .loc 1 116 26 is_stmt 0 view .LVU60 + 222 0080 0025 movs r5, #0 + 223 0082 0995 str r5, [sp, #36] + 117:Src/stm32f7xx_hal_msp.c **** + 224 .loc 1 117 5 is_stmt 1 view .LVU61 + 225 0084 07A9 add r1, sp, #28 + 226 0086 1F48 ldr r0, .L11+16 + 227 0088 FFF7FEFF bl HAL_GPIO_Init + 228 .LVL5: + 119:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 229 .loc 1 119 5 view .LVU62 + 119:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 230 .loc 1 119 25 is_stmt 0 view .LVU63 + 231 008c 0794 str r4, [sp, #28] + 120:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 232 .loc 1 120 5 is_stmt 1 view .LVU64 + 120:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 233 .loc 1 120 26 is_stmt 0 view .LVU65 + 234 008e 0894 str r4, [sp, #32] + 121:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 235 .loc 1 121 5 is_stmt 1 view .LVU66 + 121:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 236 .loc 1 121 26 is_stmt 0 view .LVU67 + 237 0090 0995 str r5, [sp, #36] + 122:Src/stm32f7xx_hal_msp.c **** + 238 .loc 1 122 5 is_stmt 1 view .LVU68 + 239 0092 07A9 add r1, sp, #28 + 240 0094 1C48 ldr r0, .L11+20 + 241 0096 FFF7FEFF bl HAL_GPIO_Init + 242 .LVL6: + 125:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(ADC_IRQn); + 243 .loc 1 125 5 view .LVU69 + 244 009a 2A46 mov r2, r5 + 245 009c 2946 mov r1, r5 + 246 009e 1220 movs r0, #18 + 247 00a0 FFF7FEFF bl HAL_NVIC_SetPriority + 248 .LVL7: + 126:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspInit 1 */ + 249 .loc 1 126 5 view .LVU70 + 250 00a4 1220 movs r0, #18 + 251 00a6 FFF7FEFF bl HAL_NVIC_EnableIRQ + 252 .LVL8: + 253 00aa B8E7 b .L5 + 254 .LVL9: + 255 .L10: + 137:Src/stm32f7xx_hal_msp.c **** + ARM GAS /tmp/cc5mtMNQ.s page 9 + + + 256 .loc 1 137 5 view .LVU71 + 257 .LBB8: + 137:Src/stm32f7xx_hal_msp.c **** + 258 .loc 1 137 5 view .LVU72 + 137:Src/stm32f7xx_hal_msp.c **** + 259 .loc 1 137 5 view .LVU73 + 260 00ac 134B ldr r3, .L11+8 + 261 00ae 5A6C ldr r2, [r3, #68] + 262 00b0 42F48062 orr r2, r2, #1024 + 263 00b4 5A64 str r2, [r3, #68] + 137:Src/stm32f7xx_hal_msp.c **** + 264 .loc 1 137 5 view .LVU74 + 265 00b6 5A6C ldr r2, [r3, #68] + 266 00b8 02F48062 and r2, r2, #1024 + 267 00bc 0592 str r2, [sp, #20] + 137:Src/stm32f7xx_hal_msp.c **** + 268 .loc 1 137 5 view .LVU75 + 269 00be 059A ldr r2, [sp, #20] + 270 .LBE8: + 137:Src/stm32f7xx_hal_msp.c **** + 271 .loc 1 137 5 view .LVU76 + 139:Src/stm32f7xx_hal_msp.c **** /**ADC3 GPIO Configuration + 272 .loc 1 139 5 view .LVU77 + 273 .LBB9: + 139:Src/stm32f7xx_hal_msp.c **** /**ADC3 GPIO Configuration + 274 .loc 1 139 5 view .LVU78 + 139:Src/stm32f7xx_hal_msp.c **** /**ADC3 GPIO Configuration + 275 .loc 1 139 5 view .LVU79 + 276 00c0 1A6B ldr r2, [r3, #48] + 277 00c2 42F02002 orr r2, r2, #32 + 278 00c6 1A63 str r2, [r3, #48] + 139:Src/stm32f7xx_hal_msp.c **** /**ADC3 GPIO Configuration + 279 .loc 1 139 5 view .LVU80 + 280 00c8 1B6B ldr r3, [r3, #48] + 281 00ca 03F02003 and r3, r3, #32 + 282 00ce 0693 str r3, [sp, #24] + 139:Src/stm32f7xx_hal_msp.c **** /**ADC3 GPIO Configuration + 283 .loc 1 139 5 view .LVU81 + 284 00d0 069B ldr r3, [sp, #24] + 285 .LBE9: + 139:Src/stm32f7xx_hal_msp.c **** /**ADC3 GPIO Configuration + 286 .loc 1 139 5 view .LVU82 + 143:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 287 .loc 1 143 5 view .LVU83 + 143:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 288 .loc 1 143 25 is_stmt 0 view .LVU84 + 289 00d2 2023 movs r3, #32 + 290 00d4 0793 str r3, [sp, #28] + 144:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 291 .loc 1 144 5 is_stmt 1 view .LVU85 + 144:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 292 .loc 1 144 26 is_stmt 0 view .LVU86 + 293 00d6 0323 movs r3, #3 + 294 00d8 0893 str r3, [sp, #32] + 145:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + 295 .loc 1 145 5 is_stmt 1 view .LVU87 + 146:Src/stm32f7xx_hal_msp.c **** + ARM GAS /tmp/cc5mtMNQ.s page 10 + + + 296 .loc 1 146 5 view .LVU88 + 297 00da 07A9 add r1, sp, #28 + 298 00dc 0B48 ldr r0, .L11+24 + 299 .LVL10: + 146:Src/stm32f7xx_hal_msp.c **** + 300 .loc 1 146 5 is_stmt 0 view .LVU89 + 301 00de FFF7FEFF bl HAL_GPIO_Init + 302 .LVL11: + 149:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(ADC_IRQn); + 303 .loc 1 149 5 is_stmt 1 view .LVU90 + 304 00e2 0022 movs r2, #0 + 305 00e4 1146 mov r1, r2 + 306 00e6 1220 movs r0, #18 + 307 00e8 FFF7FEFF bl HAL_NVIC_SetPriority + 308 .LVL12: + 150:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN ADC3_MspInit 1 */ + 309 .loc 1 150 5 view .LVU91 + 310 00ec 1220 movs r0, #18 + 311 00ee FFF7FEFF bl HAL_NVIC_EnableIRQ + 312 .LVL13: + 313 .loc 1 156 1 is_stmt 0 view .LVU92 + 314 00f2 94E7 b .L5 + 315 .L12: + 316 .align 2 + 317 .L11: + 318 00f4 00200140 .word 1073815552 + 319 00f8 00220140 .word 1073816064 + 320 00fc 00380240 .word 1073887232 + 321 0100 00080240 .word 1073874944 + 322 0104 00000240 .word 1073872896 + 323 0108 00040240 .word 1073873920 + 324 010c 00140240 .word 1073878016 + 325 .cfi_endproc + 326 .LFE1184: + 328 .section .text.HAL_ADC_MspDeInit,"ax",%progbits + 329 .align 1 + 330 .global HAL_ADC_MspDeInit + 331 .syntax unified + 332 .thumb + 333 .thumb_func + 335 HAL_ADC_MspDeInit: + 336 .LVL14: + 337 .LFB1185: + 157:Src/stm32f7xx_hal_msp.c **** + 158:Src/stm32f7xx_hal_msp.c **** /** + 159:Src/stm32f7xx_hal_msp.c **** * @brief ADC MSP De-Initialization + 160:Src/stm32f7xx_hal_msp.c **** * This function freeze the hardware resources used in this example + 161:Src/stm32f7xx_hal_msp.c **** * @param hadc: ADC handle pointer + 162:Src/stm32f7xx_hal_msp.c **** * @retval None + 163:Src/stm32f7xx_hal_msp.c **** */ + 164:Src/stm32f7xx_hal_msp.c **** void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) + 165:Src/stm32f7xx_hal_msp.c **** { + 338 .loc 1 165 1 is_stmt 1 view -0 + 339 .cfi_startproc + 340 @ args = 0, pretend = 0, frame = 0 + 341 @ frame_needed = 0, uses_anonymous_args = 0 + 342 .loc 1 165 1 is_stmt 0 view .LVU94 + ARM GAS /tmp/cc5mtMNQ.s page 11 + + + 343 0000 08B5 push {r3, lr} + 344 .LCFI6: + 345 .cfi_def_cfa_offset 8 + 346 .cfi_offset 3, -8 + 347 .cfi_offset 14, -4 + 166:Src/stm32f7xx_hal_msp.c **** if(hadc->Instance==ADC1) + 348 .loc 1 166 3 is_stmt 1 view .LVU95 + 349 .loc 1 166 10 is_stmt 0 view .LVU96 + 350 0002 0368 ldr r3, [r0] + 351 .loc 1 166 5 view .LVU97 + 352 0004 124A ldr r2, .L19 + 353 0006 9342 cmp r3, r2 + 354 0008 03D0 beq .L17 + 167:Src/stm32f7xx_hal_msp.c **** { + 168:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspDeInit 0 */ + 169:Src/stm32f7xx_hal_msp.c **** + 170:Src/stm32f7xx_hal_msp.c **** /* USER CODE END ADC1_MspDeInit 0 */ + 171:Src/stm32f7xx_hal_msp.c **** /* Peripheral clock disable */ + 172:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_ADC1_CLK_DISABLE(); + 173:Src/stm32f7xx_hal_msp.c **** + 174:Src/stm32f7xx_hal_msp.c **** /**ADC1 GPIO Configuration + 175:Src/stm32f7xx_hal_msp.c **** PC0 ------> ADC1_IN10 + 176:Src/stm32f7xx_hal_msp.c **** PC1 ------> ADC1_IN11 + 177:Src/stm32f7xx_hal_msp.c **** PA2 ------> ADC1_IN2 + 178:Src/stm32f7xx_hal_msp.c **** PB0 ------> ADC1_IN8 + 179:Src/stm32f7xx_hal_msp.c **** PB1 ------> ADC1_IN9 + 180:Src/stm32f7xx_hal_msp.c **** */ + 181:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0|GPIO_PIN_1); + 182:Src/stm32f7xx_hal_msp.c **** + 183:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2); + 184:Src/stm32f7xx_hal_msp.c **** + 185:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_1); + 186:Src/stm32f7xx_hal_msp.c **** + 187:Src/stm32f7xx_hal_msp.c **** /* ADC1 interrupt DeInit */ + 188:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN ADC1:ADC_IRQn disable */ + 189:Src/stm32f7xx_hal_msp.c **** /** + 190:Src/stm32f7xx_hal_msp.c **** * Uncomment the line below to disable the "ADC_IRQn" interrupt + 191:Src/stm32f7xx_hal_msp.c **** * Be aware, disabling shared interrupt may affect other IPs + 192:Src/stm32f7xx_hal_msp.c **** */ + 193:Src/stm32f7xx_hal_msp.c **** /* HAL_NVIC_DisableIRQ(ADC_IRQn); */ + 194:Src/stm32f7xx_hal_msp.c **** /* USER CODE END ADC1:ADC_IRQn disable */ + 195:Src/stm32f7xx_hal_msp.c **** + 196:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspDeInit 1 */ + 197:Src/stm32f7xx_hal_msp.c **** + 198:Src/stm32f7xx_hal_msp.c **** /* USER CODE END ADC1_MspDeInit 1 */ + 199:Src/stm32f7xx_hal_msp.c **** } + 200:Src/stm32f7xx_hal_msp.c **** else if(hadc->Instance==ADC3) + 355 .loc 1 200 8 is_stmt 1 view .LVU98 + 356 .loc 1 200 10 is_stmt 0 view .LVU99 + 357 000a 124A ldr r2, .L19+4 + 358 000c 9342 cmp r3, r2 + 359 000e 13D0 beq .L18 + 360 .LVL15: + 361 .L13: + 201:Src/stm32f7xx_hal_msp.c **** { + 202:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN ADC3_MspDeInit 0 */ + 203:Src/stm32f7xx_hal_msp.c **** + ARM GAS /tmp/cc5mtMNQ.s page 12 + + + 204:Src/stm32f7xx_hal_msp.c **** /* USER CODE END ADC3_MspDeInit 0 */ + 205:Src/stm32f7xx_hal_msp.c **** /* Peripheral clock disable */ + 206:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_ADC3_CLK_DISABLE(); + 207:Src/stm32f7xx_hal_msp.c **** + 208:Src/stm32f7xx_hal_msp.c **** /**ADC3 GPIO Configuration + 209:Src/stm32f7xx_hal_msp.c **** PF5 ------> ADC3_IN15 + 210:Src/stm32f7xx_hal_msp.c **** */ + 211:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOF, GPIO_PIN_5); + 212:Src/stm32f7xx_hal_msp.c **** + 213:Src/stm32f7xx_hal_msp.c **** /* ADC3 interrupt DeInit */ + 214:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN ADC3:ADC_IRQn disable */ + 215:Src/stm32f7xx_hal_msp.c **** /** + 216:Src/stm32f7xx_hal_msp.c **** * Uncomment the line below to disable the "ADC_IRQn" interrupt + 217:Src/stm32f7xx_hal_msp.c **** * Be aware, disabling shared interrupt may affect other IPs + 218:Src/stm32f7xx_hal_msp.c **** */ + 219:Src/stm32f7xx_hal_msp.c **** /* HAL_NVIC_DisableIRQ(ADC_IRQn); */ + 220:Src/stm32f7xx_hal_msp.c **** /* USER CODE END ADC3:ADC_IRQn disable */ + 221:Src/stm32f7xx_hal_msp.c **** + 222:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN ADC3_MspDeInit 1 */ + 223:Src/stm32f7xx_hal_msp.c **** + 224:Src/stm32f7xx_hal_msp.c **** /* USER CODE END ADC3_MspDeInit 1 */ + 225:Src/stm32f7xx_hal_msp.c **** } + 226:Src/stm32f7xx_hal_msp.c **** + 227:Src/stm32f7xx_hal_msp.c **** } + 362 .loc 1 227 1 view .LVU100 + 363 0010 08BD pop {r3, pc} + 364 .LVL16: + 365 .L17: + 172:Src/stm32f7xx_hal_msp.c **** + 366 .loc 1 172 5 is_stmt 1 view .LVU101 + 367 0012 02F58C32 add r2, r2, #71680 + 368 0016 536C ldr r3, [r2, #68] + 369 0018 23F48073 bic r3, r3, #256 + 370 001c 5364 str r3, [r2, #68] + 181:Src/stm32f7xx_hal_msp.c **** + 371 .loc 1 181 5 view .LVU102 + 372 001e 0321 movs r1, #3 + 373 0020 0D48 ldr r0, .L19+8 + 374 .LVL17: + 181:Src/stm32f7xx_hal_msp.c **** + 375 .loc 1 181 5 is_stmt 0 view .LVU103 + 376 0022 FFF7FEFF bl HAL_GPIO_DeInit + 377 .LVL18: + 183:Src/stm32f7xx_hal_msp.c **** + 378 .loc 1 183 5 is_stmt 1 view .LVU104 + 379 0026 0421 movs r1, #4 + 380 0028 0C48 ldr r0, .L19+12 + 381 002a FFF7FEFF bl HAL_GPIO_DeInit + 382 .LVL19: + 185:Src/stm32f7xx_hal_msp.c **** + 383 .loc 1 185 5 view .LVU105 + 384 002e 0321 movs r1, #3 + 385 0030 0B48 ldr r0, .L19+16 + 386 0032 FFF7FEFF bl HAL_GPIO_DeInit + 387 .LVL20: + 388 0036 EBE7 b .L13 + 389 .LVL21: + ARM GAS /tmp/cc5mtMNQ.s page 13 + + + 390 .L18: + 206:Src/stm32f7xx_hal_msp.c **** + 391 .loc 1 206 5 view .LVU106 + 392 0038 02F58B32 add r2, r2, #71168 + 393 003c 536C ldr r3, [r2, #68] + 394 003e 23F48063 bic r3, r3, #1024 + 395 0042 5364 str r3, [r2, #68] + 211:Src/stm32f7xx_hal_msp.c **** + 396 .loc 1 211 5 view .LVU107 + 397 0044 2021 movs r1, #32 + 398 0046 0748 ldr r0, .L19+20 + 399 .LVL22: + 211:Src/stm32f7xx_hal_msp.c **** + 400 .loc 1 211 5 is_stmt 0 view .LVU108 + 401 0048 FFF7FEFF bl HAL_GPIO_DeInit + 402 .LVL23: + 403 .loc 1 227 1 view .LVU109 + 404 004c E0E7 b .L13 + 405 .L20: + 406 004e 00BF .align 2 + 407 .L19: + 408 0050 00200140 .word 1073815552 + 409 0054 00220140 .word 1073816064 + 410 0058 00080240 .word 1073874944 + 411 005c 00000240 .word 1073872896 + 412 0060 00040240 .word 1073873920 + 413 0064 00140240 .word 1073878016 + 414 .cfi_endproc + 415 .LFE1185: + 417 .section .text.HAL_SD_MspInit,"ax",%progbits + 418 .align 1 + 419 .global HAL_SD_MspInit + 420 .syntax unified + 421 .thumb + 422 .thumb_func + 424 HAL_SD_MspInit: + 425 .LVL24: + 426 .LFB1186: + 228:Src/stm32f7xx_hal_msp.c **** + 229:Src/stm32f7xx_hal_msp.c **** /** + 230:Src/stm32f7xx_hal_msp.c **** * @brief SD MSP Initialization + 231:Src/stm32f7xx_hal_msp.c **** * This function configures the hardware resources used in this example + 232:Src/stm32f7xx_hal_msp.c **** * @param hsd: SD handle pointer + 233:Src/stm32f7xx_hal_msp.c **** * @retval None + 234:Src/stm32f7xx_hal_msp.c **** */ + 235:Src/stm32f7xx_hal_msp.c **** void HAL_SD_MspInit(SD_HandleTypeDef* hsd) + 236:Src/stm32f7xx_hal_msp.c **** { + 427 .loc 1 236 1 is_stmt 1 view -0 + 428 .cfi_startproc + 429 @ args = 0, pretend = 0, frame = 176 + 430 @ frame_needed = 0, uses_anonymous_args = 0 + 431 .loc 1 236 1 is_stmt 0 view .LVU111 + 432 0000 F0B5 push {r4, r5, r6, r7, lr} + 433 .LCFI7: + 434 .cfi_def_cfa_offset 20 + 435 .cfi_offset 4, -20 + 436 .cfi_offset 5, -16 + ARM GAS /tmp/cc5mtMNQ.s page 14 + + + 437 .cfi_offset 6, -12 + 438 .cfi_offset 7, -8 + 439 .cfi_offset 14, -4 + 440 0002 ADB0 sub sp, sp, #180 + 441 .LCFI8: + 442 .cfi_def_cfa_offset 200 + 443 0004 0446 mov r4, r0 + 237:Src/stm32f7xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; + 444 .loc 1 237 3 is_stmt 1 view .LVU112 + 445 .loc 1 237 20 is_stmt 0 view .LVU113 + 446 0006 0021 movs r1, #0 + 447 0008 2791 str r1, [sp, #156] + 448 000a 2891 str r1, [sp, #160] + 449 000c 2991 str r1, [sp, #164] + 450 000e 2A91 str r1, [sp, #168] + 451 0010 2B91 str r1, [sp, #172] + 238:Src/stm32f7xx_hal_msp.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 452 .loc 1 238 3 is_stmt 1 view .LVU114 + 453 .loc 1 238 28 is_stmt 0 view .LVU115 + 454 0012 9022 movs r2, #144 + 455 0014 03A8 add r0, sp, #12 + 456 .LVL25: + 457 .loc 1 238 28 view .LVU116 + 458 0016 FFF7FEFF bl memset + 459 .LVL26: + 239:Src/stm32f7xx_hal_msp.c **** if(hsd->Instance==SDMMC1) + 460 .loc 1 239 3 is_stmt 1 view .LVU117 + 461 .loc 1 239 9 is_stmt 0 view .LVU118 + 462 001a 2268 ldr r2, [r4] + 463 .loc 1 239 5 view .LVU119 + 464 001c 224B ldr r3, .L27 + 465 001e 9A42 cmp r2, r3 + 466 0020 01D0 beq .L25 + 467 .LVL27: + 468 .L21: + 240:Src/stm32f7xx_hal_msp.c **** { + 241:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN SDMMC1_MspInit 0 */ + 242:Src/stm32f7xx_hal_msp.c **** + 243:Src/stm32f7xx_hal_msp.c **** /* USER CODE END SDMMC1_MspInit 0 */ + 244:Src/stm32f7xx_hal_msp.c **** + 245:Src/stm32f7xx_hal_msp.c **** /** Initializes the peripherals clock + 246:Src/stm32f7xx_hal_msp.c **** */ + 247:Src/stm32f7xx_hal_msp.c **** PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1|RCC_PERIPHCLK_CLK48; + 248:Src/stm32f7xx_hal_msp.c **** PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; + 249:Src/stm32f7xx_hal_msp.c **** PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_CLK48; + 250:Src/stm32f7xx_hal_msp.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 251:Src/stm32f7xx_hal_msp.c **** { + 252:Src/stm32f7xx_hal_msp.c **** Error_Handler(); + 253:Src/stm32f7xx_hal_msp.c **** } + 254:Src/stm32f7xx_hal_msp.c **** + 255:Src/stm32f7xx_hal_msp.c **** /* Peripheral clock enable */ + 256:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_SDMMC1_CLK_ENABLE(); + 257:Src/stm32f7xx_hal_msp.c **** + 258:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); + 259:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); + 260:Src/stm32f7xx_hal_msp.c **** /**SDMMC1 GPIO Configuration + 261:Src/stm32f7xx_hal_msp.c **** PC8 ------> SDMMC1_D0 + ARM GAS /tmp/cc5mtMNQ.s page 15 + + + 262:Src/stm32f7xx_hal_msp.c **** PC9 ------> SDMMC1_D1 + 263:Src/stm32f7xx_hal_msp.c **** PC10 ------> SDMMC1_D2 + 264:Src/stm32f7xx_hal_msp.c **** PC11 ------> SDMMC1_D3 + 265:Src/stm32f7xx_hal_msp.c **** PC12 ------> SDMMC1_CK + 266:Src/stm32f7xx_hal_msp.c **** PD2 ------> SDMMC1_CMD + 267:Src/stm32f7xx_hal_msp.c **** */ + 268:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + 269:Src/stm32f7xx_hal_msp.c **** |GPIO_PIN_12; + 270:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 271:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 272:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 273:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1; + 274:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 275:Src/stm32f7xx_hal_msp.c **** + 276:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_2; + 277:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 278:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 279:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 280:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1; + 281:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 282:Src/stm32f7xx_hal_msp.c **** + 283:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN SDMMC1_MspInit 1 */ + 284:Src/stm32f7xx_hal_msp.c **** + 285:Src/stm32f7xx_hal_msp.c **** /* USER CODE END SDMMC1_MspInit 1 */ + 286:Src/stm32f7xx_hal_msp.c **** + 287:Src/stm32f7xx_hal_msp.c **** } + 288:Src/stm32f7xx_hal_msp.c **** + 289:Src/stm32f7xx_hal_msp.c **** } + 469 .loc 1 289 1 view .LVU120 + 470 0022 2DB0 add sp, sp, #180 + 471 .LCFI9: + 472 .cfi_remember_state + 473 .cfi_def_cfa_offset 20 + 474 @ sp needed + 475 0024 F0BD pop {r4, r5, r6, r7, pc} + 476 .LVL28: + 477 .L25: + 478 .LCFI10: + 479 .cfi_restore_state + 247:Src/stm32f7xx_hal_msp.c **** PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; + 480 .loc 1 247 5 is_stmt 1 view .LVU121 + 247:Src/stm32f7xx_hal_msp.c **** PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; + 481 .loc 1 247 46 is_stmt 0 view .LVU122 + 482 0026 4FF42003 mov r3, #10485760 + 483 002a 0393 str r3, [sp, #12] + 248:Src/stm32f7xx_hal_msp.c **** PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_CLK48; + 484 .loc 1 248 5 is_stmt 1 view .LVU123 + 249:Src/stm32f7xx_hal_msp.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 485 .loc 1 249 5 view .LVU124 + 250:Src/stm32f7xx_hal_msp.c **** { + 486 .loc 1 250 5 view .LVU125 + 250:Src/stm32f7xx_hal_msp.c **** { + 487 .loc 1 250 9 is_stmt 0 view .LVU126 + 488 002c 03A8 add r0, sp, #12 + 489 002e FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig + 490 .LVL29: + 250:Src/stm32f7xx_hal_msp.c **** { + ARM GAS /tmp/cc5mtMNQ.s page 16 + + + 491 .loc 1 250 8 discriminator 1 view .LVU127 + 492 0032 0028 cmp r0, #0 + 493 0034 35D1 bne .L26 + 494 .L23: + 256:Src/stm32f7xx_hal_msp.c **** + 495 .loc 1 256 5 is_stmt 1 view .LVU128 + 496 .LBB10: + 256:Src/stm32f7xx_hal_msp.c **** + 497 .loc 1 256 5 view .LVU129 + 256:Src/stm32f7xx_hal_msp.c **** + 498 .loc 1 256 5 view .LVU130 + 499 0036 1D4B ldr r3, .L27+4 + 500 0038 5A6C ldr r2, [r3, #68] + 501 003a 42F40062 orr r2, r2, #2048 + 502 003e 5A64 str r2, [r3, #68] + 256:Src/stm32f7xx_hal_msp.c **** + 503 .loc 1 256 5 view .LVU131 + 504 0040 5A6C ldr r2, [r3, #68] + 505 0042 02F40062 and r2, r2, #2048 + 506 0046 0092 str r2, [sp] + 256:Src/stm32f7xx_hal_msp.c **** + 507 .loc 1 256 5 view .LVU132 + 508 0048 009A ldr r2, [sp] + 509 .LBE10: + 256:Src/stm32f7xx_hal_msp.c **** + 510 .loc 1 256 5 view .LVU133 + 258:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); + 511 .loc 1 258 5 view .LVU134 + 512 .LBB11: + 258:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); + 513 .loc 1 258 5 view .LVU135 + 258:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); + 514 .loc 1 258 5 view .LVU136 + 515 004a 1A6B ldr r2, [r3, #48] + 516 004c 42F00402 orr r2, r2, #4 + 517 0050 1A63 str r2, [r3, #48] + 258:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); + 518 .loc 1 258 5 view .LVU137 + 519 0052 1A6B ldr r2, [r3, #48] + 520 0054 02F00402 and r2, r2, #4 + 521 0058 0192 str r2, [sp, #4] + 258:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); + 522 .loc 1 258 5 view .LVU138 + 523 005a 019A ldr r2, [sp, #4] + 524 .LBE11: + 258:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE(); + 525 .loc 1 258 5 view .LVU139 + 259:Src/stm32f7xx_hal_msp.c **** /**SDMMC1 GPIO Configuration + 526 .loc 1 259 5 view .LVU140 + 527 .LBB12: + 259:Src/stm32f7xx_hal_msp.c **** /**SDMMC1 GPIO Configuration + 528 .loc 1 259 5 view .LVU141 + 259:Src/stm32f7xx_hal_msp.c **** /**SDMMC1 GPIO Configuration + 529 .loc 1 259 5 view .LVU142 + 530 005c 1A6B ldr r2, [r3, #48] + 531 005e 42F00802 orr r2, r2, #8 + 532 0062 1A63 str r2, [r3, #48] + ARM GAS /tmp/cc5mtMNQ.s page 17 + + + 259:Src/stm32f7xx_hal_msp.c **** /**SDMMC1 GPIO Configuration + 533 .loc 1 259 5 view .LVU143 + 534 0064 1B6B ldr r3, [r3, #48] + 535 0066 03F00803 and r3, r3, #8 + 536 006a 0293 str r3, [sp, #8] + 259:Src/stm32f7xx_hal_msp.c **** /**SDMMC1 GPIO Configuration + 537 .loc 1 259 5 view .LVU144 + 538 006c 029B ldr r3, [sp, #8] + 539 .LBE12: + 259:Src/stm32f7xx_hal_msp.c **** /**SDMMC1 GPIO Configuration + 540 .loc 1 259 5 view .LVU145 + 268:Src/stm32f7xx_hal_msp.c **** |GPIO_PIN_12; + 541 .loc 1 268 5 view .LVU146 + 268:Src/stm32f7xx_hal_msp.c **** |GPIO_PIN_12; + 542 .loc 1 268 25 is_stmt 0 view .LVU147 + 543 006e 4FF4F853 mov r3, #7936 + 544 0072 2793 str r3, [sp, #156] + 270:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 545 .loc 1 270 5 is_stmt 1 view .LVU148 + 270:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 546 .loc 1 270 26 is_stmt 0 view .LVU149 + 547 0074 0227 movs r7, #2 + 548 0076 2897 str r7, [sp, #160] + 271:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 549 .loc 1 271 5 is_stmt 1 view .LVU150 + 271:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 550 .loc 1 271 26 is_stmt 0 view .LVU151 + 551 0078 0026 movs r6, #0 + 552 007a 2996 str r6, [sp, #164] + 272:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1; + 553 .loc 1 272 5 is_stmt 1 view .LVU152 + 272:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1; + 554 .loc 1 272 27 is_stmt 0 view .LVU153 + 555 007c 0325 movs r5, #3 + 556 007e 2A95 str r5, [sp, #168] + 273:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 557 .loc 1 273 5 is_stmt 1 view .LVU154 + 273:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 558 .loc 1 273 31 is_stmt 0 view .LVU155 + 559 0080 0C24 movs r4, #12 + 560 .LVL30: + 273:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 561 .loc 1 273 31 view .LVU156 + 562 0082 2B94 str r4, [sp, #172] + 274:Src/stm32f7xx_hal_msp.c **** + 563 .loc 1 274 5 is_stmt 1 view .LVU157 + 564 0084 27A9 add r1, sp, #156 + 565 0086 0A48 ldr r0, .L27+8 + 566 0088 FFF7FEFF bl HAL_GPIO_Init + 567 .LVL31: + 276:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 568 .loc 1 276 5 view .LVU158 + 276:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 569 .loc 1 276 25 is_stmt 0 view .LVU159 + 570 008c 0423 movs r3, #4 + 571 008e 2793 str r3, [sp, #156] + 277:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + ARM GAS /tmp/cc5mtMNQ.s page 18 + + + 572 .loc 1 277 5 is_stmt 1 view .LVU160 + 277:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 573 .loc 1 277 26 is_stmt 0 view .LVU161 + 574 0090 2897 str r7, [sp, #160] + 278:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 575 .loc 1 278 5 is_stmt 1 view .LVU162 + 278:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 576 .loc 1 278 26 is_stmt 0 view .LVU163 + 577 0092 2996 str r6, [sp, #164] + 279:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1; + 578 .loc 1 279 5 is_stmt 1 view .LVU164 + 279:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1; + 579 .loc 1 279 27 is_stmt 0 view .LVU165 + 580 0094 2A95 str r5, [sp, #168] + 280:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 581 .loc 1 280 5 is_stmt 1 view .LVU166 + 280:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + 582 .loc 1 280 31 is_stmt 0 view .LVU167 + 583 0096 2B94 str r4, [sp, #172] + 281:Src/stm32f7xx_hal_msp.c **** + 584 .loc 1 281 5 is_stmt 1 view .LVU168 + 585 0098 27A9 add r1, sp, #156 + 586 009a 0648 ldr r0, .L27+12 + 587 009c FFF7FEFF bl HAL_GPIO_Init + 588 .LVL32: + 589 .loc 1 289 1 is_stmt 0 view .LVU169 + 590 00a0 BFE7 b .L21 + 591 .LVL33: + 592 .L26: + 252:Src/stm32f7xx_hal_msp.c **** } + 593 .loc 1 252 7 is_stmt 1 view .LVU170 + 594 00a2 FFF7FEFF bl Error_Handler + 595 .LVL34: + 596 00a6 C6E7 b .L23 + 597 .L28: + 598 .align 2 + 599 .L27: + 600 00a8 002C0140 .word 1073818624 + 601 00ac 00380240 .word 1073887232 + 602 00b0 00080240 .word 1073874944 + 603 00b4 000C0240 .word 1073875968 + 604 .cfi_endproc + 605 .LFE1186: + 607 .section .text.HAL_SD_MspDeInit,"ax",%progbits + 608 .align 1 + 609 .global HAL_SD_MspDeInit + 610 .syntax unified + 611 .thumb + 612 .thumb_func + 614 HAL_SD_MspDeInit: + 615 .LVL35: + 616 .LFB1187: + 290:Src/stm32f7xx_hal_msp.c **** + 291:Src/stm32f7xx_hal_msp.c **** /** + 292:Src/stm32f7xx_hal_msp.c **** * @brief SD MSP De-Initialization + 293:Src/stm32f7xx_hal_msp.c **** * This function freeze the hardware resources used in this example + 294:Src/stm32f7xx_hal_msp.c **** * @param hsd: SD handle pointer + ARM GAS /tmp/cc5mtMNQ.s page 19 + + + 295:Src/stm32f7xx_hal_msp.c **** * @retval None + 296:Src/stm32f7xx_hal_msp.c **** */ + 297:Src/stm32f7xx_hal_msp.c **** void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) + 298:Src/stm32f7xx_hal_msp.c **** { + 617 .loc 1 298 1 view -0 + 618 .cfi_startproc + 619 @ args = 0, pretend = 0, frame = 0 + 620 @ frame_needed = 0, uses_anonymous_args = 0 + 621 .loc 1 298 1 is_stmt 0 view .LVU172 + 622 0000 08B5 push {r3, lr} + 623 .LCFI11: + 624 .cfi_def_cfa_offset 8 + 625 .cfi_offset 3, -8 + 626 .cfi_offset 14, -4 + 299:Src/stm32f7xx_hal_msp.c **** if(hsd->Instance==SDMMC1) + 627 .loc 1 299 3 is_stmt 1 view .LVU173 + 628 .loc 1 299 9 is_stmt 0 view .LVU174 + 629 0002 0268 ldr r2, [r0] + 630 .loc 1 299 5 view .LVU175 + 631 0004 094B ldr r3, .L33 + 632 0006 9A42 cmp r2, r3 + 633 0008 00D0 beq .L32 + 634 .LVL36: + 635 .L29: + 300:Src/stm32f7xx_hal_msp.c **** { + 301:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN SDMMC1_MspDeInit 0 */ + 302:Src/stm32f7xx_hal_msp.c **** + 303:Src/stm32f7xx_hal_msp.c **** /* USER CODE END SDMMC1_MspDeInit 0 */ + 304:Src/stm32f7xx_hal_msp.c **** /* Peripheral clock disable */ + 305:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_SDMMC1_CLK_DISABLE(); + 306:Src/stm32f7xx_hal_msp.c **** + 307:Src/stm32f7xx_hal_msp.c **** /**SDMMC1 GPIO Configuration + 308:Src/stm32f7xx_hal_msp.c **** PC8 ------> SDMMC1_D0 + 309:Src/stm32f7xx_hal_msp.c **** PC9 ------> SDMMC1_D1 + 310:Src/stm32f7xx_hal_msp.c **** PC10 ------> SDMMC1_D2 + 311:Src/stm32f7xx_hal_msp.c **** PC11 ------> SDMMC1_D3 + 312:Src/stm32f7xx_hal_msp.c **** PC12 ------> SDMMC1_CK + 313:Src/stm32f7xx_hal_msp.c **** PD2 ------> SDMMC1_CMD + 314:Src/stm32f7xx_hal_msp.c **** */ + 315:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + 316:Src/stm32f7xx_hal_msp.c **** |GPIO_PIN_12); + 317:Src/stm32f7xx_hal_msp.c **** + 318:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + 319:Src/stm32f7xx_hal_msp.c **** + 320:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN SDMMC1_MspDeInit 1 */ + 321:Src/stm32f7xx_hal_msp.c **** + 322:Src/stm32f7xx_hal_msp.c **** /* USER CODE END SDMMC1_MspDeInit 1 */ + 323:Src/stm32f7xx_hal_msp.c **** } + 324:Src/stm32f7xx_hal_msp.c **** + 325:Src/stm32f7xx_hal_msp.c **** } + 636 .loc 1 325 1 view .LVU176 + 637 000a 08BD pop {r3, pc} + 638 .LVL37: + 639 .L32: + 305:Src/stm32f7xx_hal_msp.c **** + 640 .loc 1 305 5 is_stmt 1 view .LVU177 + 641 000c 084A ldr r2, .L33+4 + ARM GAS /tmp/cc5mtMNQ.s page 20 + + + 642 000e 536C ldr r3, [r2, #68] + 643 0010 23F40063 bic r3, r3, #2048 + 644 0014 5364 str r3, [r2, #68] + 315:Src/stm32f7xx_hal_msp.c **** |GPIO_PIN_12); + 645 .loc 1 315 5 view .LVU178 + 646 0016 4FF4F851 mov r1, #7936 + 647 001a 0648 ldr r0, .L33+8 + 648 .LVL38: + 315:Src/stm32f7xx_hal_msp.c **** |GPIO_PIN_12); + 649 .loc 1 315 5 is_stmt 0 view .LVU179 + 650 001c FFF7FEFF bl HAL_GPIO_DeInit + 651 .LVL39: + 318:Src/stm32f7xx_hal_msp.c **** + 652 .loc 1 318 5 is_stmt 1 view .LVU180 + 653 0020 0421 movs r1, #4 + 654 0022 0548 ldr r0, .L33+12 + 655 0024 FFF7FEFF bl HAL_GPIO_DeInit + 656 .LVL40: + 657 .loc 1 325 1 is_stmt 0 view .LVU181 + 658 0028 EFE7 b .L29 + 659 .L34: + 660 002a 00BF .align 2 + 661 .L33: + 662 002c 002C0140 .word 1073818624 + 663 0030 00380240 .word 1073887232 + 664 0034 00080240 .word 1073874944 + 665 0038 000C0240 .word 1073875968 + 666 .cfi_endproc + 667 .LFE1187: + 669 .section .text.HAL_TIM_Base_MspInit,"ax",%progbits + 670 .align 1 + 671 .global HAL_TIM_Base_MspInit + 672 .syntax unified + 673 .thumb + 674 .thumb_func + 676 HAL_TIM_Base_MspInit: + 677 .LVL41: + 678 .LFB1188: + 326:Src/stm32f7xx_hal_msp.c **** + 327:Src/stm32f7xx_hal_msp.c **** /** + 328:Src/stm32f7xx_hal_msp.c **** * @brief TIM_Base MSP Initialization + 329:Src/stm32f7xx_hal_msp.c **** * This function configures the hardware resources used in this example + 330:Src/stm32f7xx_hal_msp.c **** * @param htim_base: TIM_Base handle pointer + 331:Src/stm32f7xx_hal_msp.c **** * @retval None + 332:Src/stm32f7xx_hal_msp.c **** */ + 333:Src/stm32f7xx_hal_msp.c **** void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) + 334:Src/stm32f7xx_hal_msp.c **** { + 679 .loc 1 334 1 is_stmt 1 view -0 + 680 .cfi_startproc + 681 @ args = 0, pretend = 0, frame = 16 + 682 @ frame_needed = 0, uses_anonymous_args = 0 + 683 .loc 1 334 1 is_stmt 0 view .LVU183 + 684 0000 00B5 push {lr} + 685 .LCFI12: + 686 .cfi_def_cfa_offset 4 + 687 .cfi_offset 14, -4 + 688 0002 85B0 sub sp, sp, #20 + ARM GAS /tmp/cc5mtMNQ.s page 21 + + + 689 .LCFI13: + 690 .cfi_def_cfa_offset 24 + 335:Src/stm32f7xx_hal_msp.c **** if(htim_base->Instance==TIM4) + 691 .loc 1 335 3 is_stmt 1 view .LVU184 + 692 .loc 1 335 15 is_stmt 0 view .LVU185 + 693 0004 0368 ldr r3, [r0] + 694 .loc 1 335 5 view .LVU186 + 695 0006 294A ldr r2, .L45 + 696 0008 9342 cmp r3, r2 + 697 000a 0BD0 beq .L41 + 336:Src/stm32f7xx_hal_msp.c **** { + 337:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 0 */ + 338:Src/stm32f7xx_hal_msp.c **** + 339:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM4_MspInit 0 */ + 340:Src/stm32f7xx_hal_msp.c **** /* Peripheral clock enable */ + 341:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_TIM4_CLK_ENABLE(); + 342:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 1 */ + 343:Src/stm32f7xx_hal_msp.c **** + 344:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM4_MspInit 1 */ + 345:Src/stm32f7xx_hal_msp.c **** } + 346:Src/stm32f7xx_hal_msp.c **** else if(htim_base->Instance==TIM8) + 698 .loc 1 346 8 is_stmt 1 view .LVU187 + 699 .loc 1 346 10 is_stmt 0 view .LVU188 + 700 000c 284A ldr r2, .L45+4 + 701 000e 9342 cmp r3, r2 + 702 0010 13D0 beq .L42 + 347:Src/stm32f7xx_hal_msp.c **** { + 348:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM8_MspInit 0 */ + 349:Src/stm32f7xx_hal_msp.c **** + 350:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM8_MspInit 0 */ + 351:Src/stm32f7xx_hal_msp.c **** /* Peripheral clock enable */ + 352:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_TIM8_CLK_ENABLE(); + 353:Src/stm32f7xx_hal_msp.c **** /* TIM8 interrupt Init */ + 354:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_SetPriority(TIM8_UP_TIM13_IRQn, 0, 0); + 355:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn); + 356:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM8_MspInit 1 */ + 357:Src/stm32f7xx_hal_msp.c **** + 358:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM8_MspInit 1 */ + 359:Src/stm32f7xx_hal_msp.c **** } + 360:Src/stm32f7xx_hal_msp.c **** else if(htim_base->Instance==TIM10) + 703 .loc 1 360 8 is_stmt 1 view .LVU189 + 704 .loc 1 360 10 is_stmt 0 view .LVU190 + 705 0012 284A ldr r2, .L45+8 + 706 0014 9342 cmp r3, r2 + 707 0016 23D0 beq .L43 + 361:Src/stm32f7xx_hal_msp.c **** { + 362:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM10_MspInit 0 */ + 363:Src/stm32f7xx_hal_msp.c **** + 364:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM10_MspInit 0 */ + 365:Src/stm32f7xx_hal_msp.c **** /* Peripheral clock enable */ + 366:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_TIM10_CLK_ENABLE(); + 367:Src/stm32f7xx_hal_msp.c **** /* TIM10 interrupt Init */ + 368:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_SetPriority(TIM1_UP_TIM10_IRQn, 0, 0); + 369:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn); + 370:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM10_MspInit 1 */ + 371:Src/stm32f7xx_hal_msp.c **** + 372:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM10_MspInit 1 */ + ARM GAS /tmp/cc5mtMNQ.s page 22 + + + 373:Src/stm32f7xx_hal_msp.c **** } + 374:Src/stm32f7xx_hal_msp.c **** else if(htim_base->Instance==TIM11) + 708 .loc 1 374 8 is_stmt 1 view .LVU191 + 709 .loc 1 374 10 is_stmt 0 view .LVU192 + 710 0018 274A ldr r2, .L45+12 + 711 001a 9342 cmp r3, r2 + 712 001c 33D0 beq .L44 + 713 .LVL42: + 714 .L35: + 375:Src/stm32f7xx_hal_msp.c **** { + 376:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM11_MspInit 0 */ + 377:Src/stm32f7xx_hal_msp.c **** + 378:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM11_MspInit 0 */ + 379:Src/stm32f7xx_hal_msp.c **** /* Peripheral clock enable */ + 380:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_TIM11_CLK_ENABLE(); + 381:Src/stm32f7xx_hal_msp.c **** /* TIM11 interrupt Init */ + 382:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM11_IRQn, 0, 0); + 383:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM11_IRQn); + 384:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM11_MspInit 1 */ + 385:Src/stm32f7xx_hal_msp.c **** + 386:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM11_MspInit 1 */ + 387:Src/stm32f7xx_hal_msp.c **** } + 388:Src/stm32f7xx_hal_msp.c **** + 389:Src/stm32f7xx_hal_msp.c **** } + 715 .loc 1 389 1 view .LVU193 + 716 001e 05B0 add sp, sp, #20 + 717 .LCFI14: + 718 .cfi_remember_state + 719 .cfi_def_cfa_offset 4 + 720 @ sp needed + 721 0020 5DF804FB ldr pc, [sp], #4 + 722 .LVL43: + 723 .L41: + 724 .LCFI15: + 725 .cfi_restore_state + 341:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 1 */ + 726 .loc 1 341 5 is_stmt 1 view .LVU194 + 727 .LBB13: + 341:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 1 */ + 728 .loc 1 341 5 view .LVU195 + 341:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 1 */ + 729 .loc 1 341 5 view .LVU196 + 730 0024 254B ldr r3, .L45+16 + 731 0026 1A6C ldr r2, [r3, #64] + 732 0028 42F00402 orr r2, r2, #4 + 733 002c 1A64 str r2, [r3, #64] + 341:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 1 */ + 734 .loc 1 341 5 view .LVU197 + 735 002e 1B6C ldr r3, [r3, #64] + 736 0030 03F00403 and r3, r3, #4 + 737 0034 0093 str r3, [sp] + 341:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 1 */ + 738 .loc 1 341 5 view .LVU198 + 739 0036 009B ldr r3, [sp] + 740 .LBE13: + 341:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 1 */ + 741 .loc 1 341 5 view .LVU199 + ARM GAS /tmp/cc5mtMNQ.s page 23 + + + 742 0038 F1E7 b .L35 + 743 .L42: + 352:Src/stm32f7xx_hal_msp.c **** /* TIM8 interrupt Init */ + 744 .loc 1 352 5 view .LVU200 + 745 .LBB14: + 352:Src/stm32f7xx_hal_msp.c **** /* TIM8 interrupt Init */ + 746 .loc 1 352 5 view .LVU201 + 352:Src/stm32f7xx_hal_msp.c **** /* TIM8 interrupt Init */ + 747 .loc 1 352 5 view .LVU202 + 748 003a 204B ldr r3, .L45+16 + 749 003c 5A6C ldr r2, [r3, #68] + 750 003e 42F00202 orr r2, r2, #2 + 751 0042 5A64 str r2, [r3, #68] + 352:Src/stm32f7xx_hal_msp.c **** /* TIM8 interrupt Init */ + 752 .loc 1 352 5 view .LVU203 + 753 0044 5B6C ldr r3, [r3, #68] + 754 0046 03F00203 and r3, r3, #2 + 755 004a 0193 str r3, [sp, #4] + 352:Src/stm32f7xx_hal_msp.c **** /* TIM8 interrupt Init */ + 756 .loc 1 352 5 view .LVU204 + 757 004c 019B ldr r3, [sp, #4] + 758 .LBE14: + 352:Src/stm32f7xx_hal_msp.c **** /* TIM8 interrupt Init */ + 759 .loc 1 352 5 view .LVU205 + 354:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn); + 760 .loc 1 354 5 view .LVU206 + 761 004e 0022 movs r2, #0 + 762 0050 1146 mov r1, r2 + 763 0052 2C20 movs r0, #44 + 764 .LVL44: + 354:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn); + 765 .loc 1 354 5 is_stmt 0 view .LVU207 + 766 0054 FFF7FEFF bl HAL_NVIC_SetPriority + 767 .LVL45: + 355:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM8_MspInit 1 */ + 768 .loc 1 355 5 is_stmt 1 view .LVU208 + 769 0058 2C20 movs r0, #44 + 770 005a FFF7FEFF bl HAL_NVIC_EnableIRQ + 771 .LVL46: + 772 005e DEE7 b .L35 + 773 .LVL47: + 774 .L43: + 366:Src/stm32f7xx_hal_msp.c **** /* TIM10 interrupt Init */ + 775 .loc 1 366 5 view .LVU209 + 776 .LBB15: + 366:Src/stm32f7xx_hal_msp.c **** /* TIM10 interrupt Init */ + 777 .loc 1 366 5 view .LVU210 + 366:Src/stm32f7xx_hal_msp.c **** /* TIM10 interrupt Init */ + 778 .loc 1 366 5 view .LVU211 + 779 0060 164B ldr r3, .L45+16 + 780 0062 5A6C ldr r2, [r3, #68] + 781 0064 42F40032 orr r2, r2, #131072 + 782 0068 5A64 str r2, [r3, #68] + 366:Src/stm32f7xx_hal_msp.c **** /* TIM10 interrupt Init */ + 783 .loc 1 366 5 view .LVU212 + 784 006a 5B6C ldr r3, [r3, #68] + 785 006c 03F40033 and r3, r3, #131072 + ARM GAS /tmp/cc5mtMNQ.s page 24 + + + 786 0070 0293 str r3, [sp, #8] + 366:Src/stm32f7xx_hal_msp.c **** /* TIM10 interrupt Init */ + 787 .loc 1 366 5 view .LVU213 + 788 0072 029B ldr r3, [sp, #8] + 789 .LBE15: + 366:Src/stm32f7xx_hal_msp.c **** /* TIM10 interrupt Init */ + 790 .loc 1 366 5 view .LVU214 + 368:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn); + 791 .loc 1 368 5 view .LVU215 + 792 0074 0022 movs r2, #0 + 793 0076 1146 mov r1, r2 + 794 0078 1920 movs r0, #25 + 795 .LVL48: + 368:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn); + 796 .loc 1 368 5 is_stmt 0 view .LVU216 + 797 007a FFF7FEFF bl HAL_NVIC_SetPriority + 798 .LVL49: + 369:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM10_MspInit 1 */ + 799 .loc 1 369 5 is_stmt 1 view .LVU217 + 800 007e 1920 movs r0, #25 + 801 0080 FFF7FEFF bl HAL_NVIC_EnableIRQ + 802 .LVL50: + 803 0084 CBE7 b .L35 + 804 .LVL51: + 805 .L44: + 380:Src/stm32f7xx_hal_msp.c **** /* TIM11 interrupt Init */ + 806 .loc 1 380 5 view .LVU218 + 807 .LBB16: + 380:Src/stm32f7xx_hal_msp.c **** /* TIM11 interrupt Init */ + 808 .loc 1 380 5 view .LVU219 + 380:Src/stm32f7xx_hal_msp.c **** /* TIM11 interrupt Init */ + 809 .loc 1 380 5 view .LVU220 + 810 0086 0D4B ldr r3, .L45+16 + 811 0088 5A6C ldr r2, [r3, #68] + 812 008a 42F48022 orr r2, r2, #262144 + 813 008e 5A64 str r2, [r3, #68] + 380:Src/stm32f7xx_hal_msp.c **** /* TIM11 interrupt Init */ + 814 .loc 1 380 5 view .LVU221 + 815 0090 5B6C ldr r3, [r3, #68] + 816 0092 03F48023 and r3, r3, #262144 + 817 0096 0393 str r3, [sp, #12] + 380:Src/stm32f7xx_hal_msp.c **** /* TIM11 interrupt Init */ + 818 .loc 1 380 5 view .LVU222 + 819 0098 039B ldr r3, [sp, #12] + 820 .LBE16: + 380:Src/stm32f7xx_hal_msp.c **** /* TIM11 interrupt Init */ + 821 .loc 1 380 5 view .LVU223 + 382:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM11_IRQn); + 822 .loc 1 382 5 view .LVU224 + 823 009a 0022 movs r2, #0 + 824 009c 1146 mov r1, r2 + 825 009e 1A20 movs r0, #26 + 826 .LVL52: + 382:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM11_IRQn); + 827 .loc 1 382 5 is_stmt 0 view .LVU225 + 828 00a0 FFF7FEFF bl HAL_NVIC_SetPriority + 829 .LVL53: + ARM GAS /tmp/cc5mtMNQ.s page 25 + + + 383:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM11_MspInit 1 */ + 830 .loc 1 383 5 is_stmt 1 view .LVU226 + 831 00a4 1A20 movs r0, #26 + 832 00a6 FFF7FEFF bl HAL_NVIC_EnableIRQ + 833 .LVL54: + 834 .loc 1 389 1 is_stmt 0 view .LVU227 + 835 00aa B8E7 b .L35 + 836 .L46: + 837 .align 2 + 838 .L45: + 839 00ac 00080040 .word 1073743872 + 840 00b0 00040140 .word 1073808384 + 841 00b4 00440140 .word 1073824768 + 842 00b8 00480140 .word 1073825792 + 843 00bc 00380240 .word 1073887232 + 844 .cfi_endproc + 845 .LFE1188: + 847 .section .text.HAL_TIM_MspPostInit,"ax",%progbits + 848 .align 1 + 849 .global HAL_TIM_MspPostInit + 850 .syntax unified + 851 .thumb + 852 .thumb_func + 854 HAL_TIM_MspPostInit: + 855 .LVL55: + 856 .LFB1189: + 390:Src/stm32f7xx_hal_msp.c **** + 391:Src/stm32f7xx_hal_msp.c **** void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) + 392:Src/stm32f7xx_hal_msp.c **** { + 857 .loc 1 392 1 is_stmt 1 view -0 + 858 .cfi_startproc + 859 @ args = 0, pretend = 0, frame = 32 + 860 @ frame_needed = 0, uses_anonymous_args = 0 + 861 .loc 1 392 1 is_stmt 0 view .LVU229 + 862 0000 00B5 push {lr} + 863 .LCFI16: + 864 .cfi_def_cfa_offset 4 + 865 .cfi_offset 14, -4 + 866 0002 89B0 sub sp, sp, #36 + 867 .LCFI17: + 868 .cfi_def_cfa_offset 40 + 393:Src/stm32f7xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; + 869 .loc 1 393 3 is_stmt 1 view .LVU230 + 870 .loc 1 393 20 is_stmt 0 view .LVU231 + 871 0004 0023 movs r3, #0 + 872 0006 0393 str r3, [sp, #12] + 873 0008 0493 str r3, [sp, #16] + 874 000a 0593 str r3, [sp, #20] + 875 000c 0693 str r3, [sp, #24] + 876 000e 0793 str r3, [sp, #28] + 394:Src/stm32f7xx_hal_msp.c **** if(htim->Instance==TIM4) + 877 .loc 1 394 3 is_stmt 1 view .LVU232 + 878 .loc 1 394 10 is_stmt 0 view .LVU233 + 879 0010 0368 ldr r3, [r0] + 880 .loc 1 394 5 view .LVU234 + 881 0012 1A4A ldr r2, .L53 + 882 0014 9342 cmp r3, r2 + ARM GAS /tmp/cc5mtMNQ.s page 26 + + + 883 0016 05D0 beq .L51 + 395:Src/stm32f7xx_hal_msp.c **** { + 396:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspPostInit 0 */ + 397:Src/stm32f7xx_hal_msp.c **** + 398:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM4_MspPostInit 0 */ + 399:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 400:Src/stm32f7xx_hal_msp.c **** /**TIM4 GPIO Configuration + 401:Src/stm32f7xx_hal_msp.c **** PB8 ------> TIM4_CH3 + 402:Src/stm32f7xx_hal_msp.c **** */ + 403:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_8; + 404:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 405:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 406:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 407:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; + 408:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 409:Src/stm32f7xx_hal_msp.c **** + 410:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspPostInit 1 */ + 411:Src/stm32f7xx_hal_msp.c **** + 412:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM4_MspPostInit 1 */ + 413:Src/stm32f7xx_hal_msp.c **** } + 414:Src/stm32f7xx_hal_msp.c **** else if(htim->Instance==TIM11) + 884 .loc 1 414 8 is_stmt 1 view .LVU235 + 885 .loc 1 414 10 is_stmt 0 view .LVU236 + 886 0018 194A ldr r2, .L53+4 + 887 001a 9342 cmp r3, r2 + 888 001c 17D0 beq .L52 + 889 .LVL56: + 890 .L47: + 415:Src/stm32f7xx_hal_msp.c **** { + 416:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM11_MspPostInit 0 */ + 417:Src/stm32f7xx_hal_msp.c **** + 418:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM11_MspPostInit 0 */ + 419:Src/stm32f7xx_hal_msp.c **** + 420:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 421:Src/stm32f7xx_hal_msp.c **** /**TIM11 GPIO Configuration + 422:Src/stm32f7xx_hal_msp.c **** PB9 ------> TIM11_CH1 + 423:Src/stm32f7xx_hal_msp.c **** */ + 424:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_9; + 425:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 426:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 427:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 428:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF3_TIM11; + 429:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 430:Src/stm32f7xx_hal_msp.c **** + 431:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM11_MspPostInit 1 */ + 432:Src/stm32f7xx_hal_msp.c **** + 433:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM11_MspPostInit 1 */ + 434:Src/stm32f7xx_hal_msp.c **** } + 435:Src/stm32f7xx_hal_msp.c **** + 436:Src/stm32f7xx_hal_msp.c **** } + 891 .loc 1 436 1 view .LVU237 + 892 001e 09B0 add sp, sp, #36 + 893 .LCFI18: + 894 .cfi_remember_state + 895 .cfi_def_cfa_offset 4 + 896 @ sp needed + 897 0020 5DF804FB ldr pc, [sp], #4 + ARM GAS /tmp/cc5mtMNQ.s page 27 + + + 898 .LVL57: + 899 .L51: + 900 .LCFI19: + 901 .cfi_restore_state + 399:Src/stm32f7xx_hal_msp.c **** /**TIM4 GPIO Configuration + 902 .loc 1 399 5 is_stmt 1 view .LVU238 + 903 .LBB17: + 399:Src/stm32f7xx_hal_msp.c **** /**TIM4 GPIO Configuration + 904 .loc 1 399 5 view .LVU239 + 399:Src/stm32f7xx_hal_msp.c **** /**TIM4 GPIO Configuration + 905 .loc 1 399 5 view .LVU240 + 906 0024 174B ldr r3, .L53+8 + 907 0026 1A6B ldr r2, [r3, #48] + 908 0028 42F00202 orr r2, r2, #2 + 909 002c 1A63 str r2, [r3, #48] + 399:Src/stm32f7xx_hal_msp.c **** /**TIM4 GPIO Configuration + 910 .loc 1 399 5 view .LVU241 + 911 002e 1B6B ldr r3, [r3, #48] + 912 0030 03F00203 and r3, r3, #2 + 913 0034 0193 str r3, [sp, #4] + 399:Src/stm32f7xx_hal_msp.c **** /**TIM4 GPIO Configuration + 914 .loc 1 399 5 view .LVU242 + 915 0036 019B ldr r3, [sp, #4] + 916 .LBE17: + 399:Src/stm32f7xx_hal_msp.c **** /**TIM4 GPIO Configuration + 917 .loc 1 399 5 view .LVU243 + 403:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 918 .loc 1 403 5 view .LVU244 + 403:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 919 .loc 1 403 25 is_stmt 0 view .LVU245 + 920 0038 4FF48073 mov r3, #256 + 921 003c 0393 str r3, [sp, #12] + 404:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 922 .loc 1 404 5 is_stmt 1 view .LVU246 + 404:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 923 .loc 1 404 26 is_stmt 0 view .LVU247 + 924 003e 0223 movs r3, #2 + 925 0040 0493 str r3, [sp, #16] + 405:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 926 .loc 1 405 5 is_stmt 1 view .LVU248 + 406:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; + 927 .loc 1 406 5 view .LVU249 + 407:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 928 .loc 1 407 5 view .LVU250 + 407:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 929 .loc 1 407 31 is_stmt 0 view .LVU251 + 930 0042 0793 str r3, [sp, #28] + 408:Src/stm32f7xx_hal_msp.c **** + 931 .loc 1 408 5 is_stmt 1 view .LVU252 + 932 0044 03A9 add r1, sp, #12 + 933 0046 1048 ldr r0, .L53+12 + 934 .LVL58: + 408:Src/stm32f7xx_hal_msp.c **** + 935 .loc 1 408 5 is_stmt 0 view .LVU253 + 936 0048 FFF7FEFF bl HAL_GPIO_Init + 937 .LVL59: + 938 004c E7E7 b .L47 + ARM GAS /tmp/cc5mtMNQ.s page 28 + + + 939 .LVL60: + 940 .L52: + 420:Src/stm32f7xx_hal_msp.c **** /**TIM11 GPIO Configuration + 941 .loc 1 420 5 is_stmt 1 view .LVU254 + 942 .LBB18: + 420:Src/stm32f7xx_hal_msp.c **** /**TIM11 GPIO Configuration + 943 .loc 1 420 5 view .LVU255 + 420:Src/stm32f7xx_hal_msp.c **** /**TIM11 GPIO Configuration + 944 .loc 1 420 5 view .LVU256 + 945 004e 0D4B ldr r3, .L53+8 + 946 0050 1A6B ldr r2, [r3, #48] + 947 0052 42F00202 orr r2, r2, #2 + 948 0056 1A63 str r2, [r3, #48] + 420:Src/stm32f7xx_hal_msp.c **** /**TIM11 GPIO Configuration + 949 .loc 1 420 5 view .LVU257 + 950 0058 1B6B ldr r3, [r3, #48] + 951 005a 03F00203 and r3, r3, #2 + 952 005e 0293 str r3, [sp, #8] + 420:Src/stm32f7xx_hal_msp.c **** /**TIM11 GPIO Configuration + 953 .loc 1 420 5 view .LVU258 + 954 0060 029B ldr r3, [sp, #8] + 955 .LBE18: + 420:Src/stm32f7xx_hal_msp.c **** /**TIM11 GPIO Configuration + 956 .loc 1 420 5 view .LVU259 + 424:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 957 .loc 1 424 5 view .LVU260 + 424:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 958 .loc 1 424 25 is_stmt 0 view .LVU261 + 959 0062 4FF40073 mov r3, #512 + 960 0066 0393 str r3, [sp, #12] + 425:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 961 .loc 1 425 5 is_stmt 1 view .LVU262 + 425:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 962 .loc 1 425 26 is_stmt 0 view .LVU263 + 963 0068 0223 movs r3, #2 + 964 006a 0493 str r3, [sp, #16] + 426:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 965 .loc 1 426 5 is_stmt 1 view .LVU264 + 427:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF3_TIM11; + 966 .loc 1 427 5 view .LVU265 + 428:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 967 .loc 1 428 5 view .LVU266 + 428:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 968 .loc 1 428 31 is_stmt 0 view .LVU267 + 969 006c 0323 movs r3, #3 + 970 006e 0793 str r3, [sp, #28] + 429:Src/stm32f7xx_hal_msp.c **** + 971 .loc 1 429 5 is_stmt 1 view .LVU268 + 972 0070 03A9 add r1, sp, #12 + 973 0072 0548 ldr r0, .L53+12 + 974 .LVL61: + 429:Src/stm32f7xx_hal_msp.c **** + 975 .loc 1 429 5 is_stmt 0 view .LVU269 + 976 0074 FFF7FEFF bl HAL_GPIO_Init + 977 .LVL62: + 978 .loc 1 436 1 view .LVU270 + 979 0078 D1E7 b .L47 + ARM GAS /tmp/cc5mtMNQ.s page 29 + + + 980 .L54: + 981 007a 00BF .align 2 + 982 .L53: + 983 007c 00080040 .word 1073743872 + 984 0080 00480140 .word 1073825792 + 985 0084 00380240 .word 1073887232 + 986 0088 00040240 .word 1073873920 + 987 .cfi_endproc + 988 .LFE1189: + 990 .section .text.HAL_TIM_Base_MspDeInit,"ax",%progbits + 991 .align 1 + 992 .global HAL_TIM_Base_MspDeInit + 993 .syntax unified + 994 .thumb + 995 .thumb_func + 997 HAL_TIM_Base_MspDeInit: + 998 .LVL63: + 999 .LFB1190: + 437:Src/stm32f7xx_hal_msp.c **** /** + 438:Src/stm32f7xx_hal_msp.c **** * @brief TIM_Base MSP De-Initialization + 439:Src/stm32f7xx_hal_msp.c **** * This function freeze the hardware resources used in this example + 440:Src/stm32f7xx_hal_msp.c **** * @param htim_base: TIM_Base handle pointer + 441:Src/stm32f7xx_hal_msp.c **** * @retval None + 442:Src/stm32f7xx_hal_msp.c **** */ + 443:Src/stm32f7xx_hal_msp.c **** void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) + 444:Src/stm32f7xx_hal_msp.c **** { + 1000 .loc 1 444 1 is_stmt 1 view -0 + 1001 .cfi_startproc + 1002 @ args = 0, pretend = 0, frame = 0 + 1003 @ frame_needed = 0, uses_anonymous_args = 0 + 1004 .loc 1 444 1 is_stmt 0 view .LVU272 + 1005 0000 08B5 push {r3, lr} + 1006 .LCFI20: + 1007 .cfi_def_cfa_offset 8 + 1008 .cfi_offset 3, -8 + 1009 .cfi_offset 14, -4 + 445:Src/stm32f7xx_hal_msp.c **** if(htim_base->Instance==TIM4) + 1010 .loc 1 445 3 is_stmt 1 view .LVU273 + 1011 .loc 1 445 15 is_stmt 0 view .LVU274 + 1012 0002 0368 ldr r3, [r0] + 1013 .loc 1 445 5 view .LVU275 + 1014 0004 184A ldr r2, .L65 + 1015 0006 9342 cmp r3, r2 + 1016 0008 09D0 beq .L61 + 446:Src/stm32f7xx_hal_msp.c **** { + 447:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspDeInit 0 */ + 448:Src/stm32f7xx_hal_msp.c **** + 449:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM4_MspDeInit 0 */ + 450:Src/stm32f7xx_hal_msp.c **** /* Peripheral clock disable */ + 451:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_TIM4_CLK_DISABLE(); + 452:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspDeInit 1 */ + 453:Src/stm32f7xx_hal_msp.c **** + 454:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM4_MspDeInit 1 */ + 455:Src/stm32f7xx_hal_msp.c **** } + 456:Src/stm32f7xx_hal_msp.c **** else if(htim_base->Instance==TIM8) + 1017 .loc 1 456 8 is_stmt 1 view .LVU276 + 1018 .loc 1 456 10 is_stmt 0 view .LVU277 + ARM GAS /tmp/cc5mtMNQ.s page 30 + + + 1019 000a 184A ldr r2, .L65+4 + 1020 000c 9342 cmp r3, r2 + 1021 000e 0DD0 beq .L62 + 457:Src/stm32f7xx_hal_msp.c **** { + 458:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM8_MspDeInit 0 */ + 459:Src/stm32f7xx_hal_msp.c **** + 460:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM8_MspDeInit 0 */ + 461:Src/stm32f7xx_hal_msp.c **** /* Peripheral clock disable */ + 462:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_TIM8_CLK_DISABLE(); + 463:Src/stm32f7xx_hal_msp.c **** + 464:Src/stm32f7xx_hal_msp.c **** /* TIM8 interrupt DeInit */ + 465:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_DisableIRQ(TIM8_UP_TIM13_IRQn); + 466:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM8_MspDeInit 1 */ + 467:Src/stm32f7xx_hal_msp.c **** + 468:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM8_MspDeInit 1 */ + 469:Src/stm32f7xx_hal_msp.c **** } + 470:Src/stm32f7xx_hal_msp.c **** else if(htim_base->Instance==TIM10) + 1022 .loc 1 470 8 is_stmt 1 view .LVU278 + 1023 .loc 1 470 10 is_stmt 0 view .LVU279 + 1024 0010 174A ldr r2, .L65+8 + 1025 0012 9342 cmp r3, r2 + 1026 0014 14D0 beq .L63 + 471:Src/stm32f7xx_hal_msp.c **** { + 472:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM10_MspDeInit 0 */ + 473:Src/stm32f7xx_hal_msp.c **** + 474:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM10_MspDeInit 0 */ + 475:Src/stm32f7xx_hal_msp.c **** /* Peripheral clock disable */ + 476:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_TIM10_CLK_DISABLE(); + 477:Src/stm32f7xx_hal_msp.c **** + 478:Src/stm32f7xx_hal_msp.c **** /* TIM10 interrupt DeInit */ + 479:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_DisableIRQ(TIM1_UP_TIM10_IRQn); + 480:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM10_MspDeInit 1 */ + 481:Src/stm32f7xx_hal_msp.c **** + 482:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM10_MspDeInit 1 */ + 483:Src/stm32f7xx_hal_msp.c **** } + 484:Src/stm32f7xx_hal_msp.c **** else if(htim_base->Instance==TIM11) + 1027 .loc 1 484 8 is_stmt 1 view .LVU280 + 1028 .loc 1 484 10 is_stmt 0 view .LVU281 + 1029 0016 174A ldr r2, .L65+12 + 1030 0018 9342 cmp r3, r2 + 1031 001a 1BD0 beq .L64 + 1032 .LVL64: + 1033 .L55: + 485:Src/stm32f7xx_hal_msp.c **** { + 486:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM11_MspDeInit 0 */ + 487:Src/stm32f7xx_hal_msp.c **** + 488:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM11_MspDeInit 0 */ + 489:Src/stm32f7xx_hal_msp.c **** /* Peripheral clock disable */ + 490:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_TIM11_CLK_DISABLE(); + 491:Src/stm32f7xx_hal_msp.c **** + 492:Src/stm32f7xx_hal_msp.c **** /* TIM11 interrupt DeInit */ + 493:Src/stm32f7xx_hal_msp.c **** HAL_NVIC_DisableIRQ(TIM1_TRG_COM_TIM11_IRQn); + 494:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM11_MspDeInit 1 */ + 495:Src/stm32f7xx_hal_msp.c **** + 496:Src/stm32f7xx_hal_msp.c **** /* USER CODE END TIM11_MspDeInit 1 */ + 497:Src/stm32f7xx_hal_msp.c **** } + 498:Src/stm32f7xx_hal_msp.c **** + ARM GAS /tmp/cc5mtMNQ.s page 31 + + + 499:Src/stm32f7xx_hal_msp.c **** } + 1034 .loc 1 499 1 view .LVU282 + 1035 001c 08BD pop {r3, pc} + 1036 .LVL65: + 1037 .L61: + 451:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspDeInit 1 */ + 1038 .loc 1 451 5 is_stmt 1 view .LVU283 + 1039 001e 02F50C32 add r2, r2, #143360 + 1040 0022 136C ldr r3, [r2, #64] + 1041 0024 23F00403 bic r3, r3, #4 + 1042 0028 1364 str r3, [r2, #64] + 1043 002a F7E7 b .L55 + 1044 .L62: + 462:Src/stm32f7xx_hal_msp.c **** + 1045 .loc 1 462 5 view .LVU284 + 1046 002c 02F59A32 add r2, r2, #78848 + 1047 0030 536C ldr r3, [r2, #68] + 1048 0032 23F00203 bic r3, r3, #2 + 1049 0036 5364 str r3, [r2, #68] + 465:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM8_MspDeInit 1 */ + 1050 .loc 1 465 5 view .LVU285 + 1051 0038 2C20 movs r0, #44 + 1052 .LVL66: + 465:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM8_MspDeInit 1 */ + 1053 .loc 1 465 5 is_stmt 0 view .LVU286 + 1054 003a FFF7FEFF bl HAL_NVIC_DisableIRQ + 1055 .LVL67: + 1056 003e EDE7 b .L55 + 1057 .LVL68: + 1058 .L63: + 476:Src/stm32f7xx_hal_msp.c **** + 1059 .loc 1 476 5 is_stmt 1 view .LVU287 + 1060 0040 02F57442 add r2, r2, #62464 + 1061 0044 536C ldr r3, [r2, #68] + 1062 0046 23F40033 bic r3, r3, #131072 + 1063 004a 5364 str r3, [r2, #68] + 479:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM10_MspDeInit 1 */ + 1064 .loc 1 479 5 view .LVU288 + 1065 004c 1920 movs r0, #25 + 1066 .LVL69: + 479:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM10_MspDeInit 1 */ + 1067 .loc 1 479 5 is_stmt 0 view .LVU289 + 1068 004e FFF7FEFF bl HAL_NVIC_DisableIRQ + 1069 .LVL70: + 1070 0052 E3E7 b .L55 + 1071 .LVL71: + 1072 .L64: + 490:Src/stm32f7xx_hal_msp.c **** + 1073 .loc 1 490 5 is_stmt 1 view .LVU290 + 1074 0054 02F57042 add r2, r2, #61440 + 1075 0058 536C ldr r3, [r2, #68] + 1076 005a 23F48023 bic r3, r3, #262144 + 1077 005e 5364 str r3, [r2, #68] + 493:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM11_MspDeInit 1 */ + 1078 .loc 1 493 5 view .LVU291 + 1079 0060 1A20 movs r0, #26 + 1080 .LVL72: + ARM GAS /tmp/cc5mtMNQ.s page 32 + + + 493:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN TIM11_MspDeInit 1 */ + 1081 .loc 1 493 5 is_stmt 0 view .LVU292 + 1082 0062 FFF7FEFF bl HAL_NVIC_DisableIRQ + 1083 .LVL73: + 1084 .loc 1 499 1 view .LVU293 + 1085 0066 D9E7 b .L55 + 1086 .L66: + 1087 .align 2 + 1088 .L65: + 1089 0068 00080040 .word 1073743872 + 1090 006c 00040140 .word 1073808384 + 1091 0070 00440140 .word 1073824768 + 1092 0074 00480140 .word 1073825792 + 1093 .cfi_endproc + 1094 .LFE1190: + 1096 .section .text.HAL_UART_MspInit,"ax",%progbits + 1097 .align 1 + 1098 .global HAL_UART_MspInit + 1099 .syntax unified + 1100 .thumb + 1101 .thumb_func + 1103 HAL_UART_MspInit: + 1104 .LVL74: + 1105 .LFB1191: + 500:Src/stm32f7xx_hal_msp.c **** + 501:Src/stm32f7xx_hal_msp.c **** /** + 502:Src/stm32f7xx_hal_msp.c **** * @brief UART MSP Initialization + 503:Src/stm32f7xx_hal_msp.c **** * This function configures the hardware resources used in this example + 504:Src/stm32f7xx_hal_msp.c **** * @param huart: UART handle pointer + 505:Src/stm32f7xx_hal_msp.c **** * @retval None + 506:Src/stm32f7xx_hal_msp.c **** */ + 507:Src/stm32f7xx_hal_msp.c **** void HAL_UART_MspInit(UART_HandleTypeDef* huart) + 508:Src/stm32f7xx_hal_msp.c **** { + 1106 .loc 1 508 1 is_stmt 1 view -0 + 1107 .cfi_startproc + 1108 @ args = 0, pretend = 0, frame = 176 + 1109 @ frame_needed = 0, uses_anonymous_args = 0 + 1110 .loc 1 508 1 is_stmt 0 view .LVU295 + 1111 0000 10B5 push {r4, lr} + 1112 .LCFI21: + 1113 .cfi_def_cfa_offset 8 + 1114 .cfi_offset 4, -8 + 1115 .cfi_offset 14, -4 + 1116 0002 ACB0 sub sp, sp, #176 + 1117 .LCFI22: + 1118 .cfi_def_cfa_offset 184 + 1119 0004 0446 mov r4, r0 + 509:Src/stm32f7xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; + 1120 .loc 1 509 3 is_stmt 1 view .LVU296 + 1121 .loc 1 509 20 is_stmt 0 view .LVU297 + 1122 0006 0021 movs r1, #0 + 1123 0008 2791 str r1, [sp, #156] + 1124 000a 2891 str r1, [sp, #160] + 1125 000c 2991 str r1, [sp, #164] + 1126 000e 2A91 str r1, [sp, #168] + 1127 0010 2B91 str r1, [sp, #172] + 510:Src/stm32f7xx_hal_msp.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + ARM GAS /tmp/cc5mtMNQ.s page 33 + + + 1128 .loc 1 510 3 is_stmt 1 view .LVU298 + 1129 .loc 1 510 28 is_stmt 0 view .LVU299 + 1130 0012 9022 movs r2, #144 + 1131 0014 03A8 add r0, sp, #12 + 1132 .LVL75: + 1133 .loc 1 510 28 view .LVU300 + 1134 0016 FFF7FEFF bl memset + 1135 .LVL76: + 511:Src/stm32f7xx_hal_msp.c **** if(huart->Instance==UART8) + 1136 .loc 1 511 3 is_stmt 1 view .LVU301 + 1137 .loc 1 511 11 is_stmt 0 view .LVU302 + 1138 001a 2268 ldr r2, [r4] + 1139 .loc 1 511 5 view .LVU303 + 1140 001c 174B ldr r3, .L73 + 1141 001e 9A42 cmp r2, r3 + 1142 0020 01D0 beq .L71 + 1143 .L67: + 512:Src/stm32f7xx_hal_msp.c **** { + 513:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN UART8_MspInit 0 */ + 514:Src/stm32f7xx_hal_msp.c **** + 515:Src/stm32f7xx_hal_msp.c **** /* USER CODE END UART8_MspInit 0 */ + 516:Src/stm32f7xx_hal_msp.c **** + 517:Src/stm32f7xx_hal_msp.c **** /** Initializes the peripherals clock + 518:Src/stm32f7xx_hal_msp.c **** */ + 519:Src/stm32f7xx_hal_msp.c **** PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8; + 520:Src/stm32f7xx_hal_msp.c **** PeriphClkInitStruct.Uart8ClockSelection = RCC_UART8CLKSOURCE_PCLK1; + 521:Src/stm32f7xx_hal_msp.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 522:Src/stm32f7xx_hal_msp.c **** { + 523:Src/stm32f7xx_hal_msp.c **** Error_Handler(); + 524:Src/stm32f7xx_hal_msp.c **** } + 525:Src/stm32f7xx_hal_msp.c **** + 526:Src/stm32f7xx_hal_msp.c **** /* Peripheral clock enable */ + 527:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_UART8_CLK_ENABLE(); + 528:Src/stm32f7xx_hal_msp.c **** + 529:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_GPIOE_CLK_ENABLE(); + 530:Src/stm32f7xx_hal_msp.c **** /**UART8 GPIO Configuration + 531:Src/stm32f7xx_hal_msp.c **** PE0 ------> UART8_RX + 532:Src/stm32f7xx_hal_msp.c **** PE1 ------> UART8_TX + 533:Src/stm32f7xx_hal_msp.c **** */ + 534:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + 535:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 536:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 537:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 538:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF8_UART8; + 539:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 540:Src/stm32f7xx_hal_msp.c **** + 541:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN UART8_MspInit 1 */ + 542:Src/stm32f7xx_hal_msp.c **** + 543:Src/stm32f7xx_hal_msp.c **** /* USER CODE END UART8_MspInit 1 */ + 544:Src/stm32f7xx_hal_msp.c **** + 545:Src/stm32f7xx_hal_msp.c **** } + 546:Src/stm32f7xx_hal_msp.c **** + 547:Src/stm32f7xx_hal_msp.c **** } + 1144 .loc 1 547 1 view .LVU304 + 1145 0022 2CB0 add sp, sp, #176 + 1146 .LCFI23: + 1147 .cfi_remember_state + ARM GAS /tmp/cc5mtMNQ.s page 34 + + + 1148 .cfi_def_cfa_offset 8 + 1149 @ sp needed + 1150 0024 10BD pop {r4, pc} + 1151 .LVL77: + 1152 .L71: + 1153 .LCFI24: + 1154 .cfi_restore_state + 519:Src/stm32f7xx_hal_msp.c **** PeriphClkInitStruct.Uart8ClockSelection = RCC_UART8CLKSOURCE_PCLK1; + 1155 .loc 1 519 5 is_stmt 1 view .LVU305 + 519:Src/stm32f7xx_hal_msp.c **** PeriphClkInitStruct.Uart8ClockSelection = RCC_UART8CLKSOURCE_PCLK1; + 1156 .loc 1 519 46 is_stmt 0 view .LVU306 + 1157 0026 4FF40053 mov r3, #8192 + 1158 002a 0393 str r3, [sp, #12] + 520:Src/stm32f7xx_hal_msp.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 1159 .loc 1 520 5 is_stmt 1 view .LVU307 + 521:Src/stm32f7xx_hal_msp.c **** { + 1160 .loc 1 521 5 view .LVU308 + 521:Src/stm32f7xx_hal_msp.c **** { + 1161 .loc 1 521 9 is_stmt 0 view .LVU309 + 1162 002c 03A8 add r0, sp, #12 + 1163 002e FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig + 1164 .LVL78: + 521:Src/stm32f7xx_hal_msp.c **** { + 1165 .loc 1 521 8 discriminator 1 view .LVU310 + 1166 0032 00BB cbnz r0, .L72 + 1167 .L69: + 527:Src/stm32f7xx_hal_msp.c **** + 1168 .loc 1 527 5 is_stmt 1 view .LVU311 + 1169 .LBB19: + 527:Src/stm32f7xx_hal_msp.c **** + 1170 .loc 1 527 5 view .LVU312 + 527:Src/stm32f7xx_hal_msp.c **** + 1171 .loc 1 527 5 view .LVU313 + 1172 0034 124B ldr r3, .L73+4 + 1173 0036 1A6C ldr r2, [r3, #64] + 1174 0038 42F00042 orr r2, r2, #-2147483648 + 1175 003c 1A64 str r2, [r3, #64] + 527:Src/stm32f7xx_hal_msp.c **** + 1176 .loc 1 527 5 view .LVU314 + 1177 003e 1A6C ldr r2, [r3, #64] + 1178 0040 02F00042 and r2, r2, #-2147483648 + 1179 0044 0192 str r2, [sp, #4] + 527:Src/stm32f7xx_hal_msp.c **** + 1180 .loc 1 527 5 view .LVU315 + 1181 0046 019A ldr r2, [sp, #4] + 1182 .LBE19: + 527:Src/stm32f7xx_hal_msp.c **** + 1183 .loc 1 527 5 view .LVU316 + 529:Src/stm32f7xx_hal_msp.c **** /**UART8 GPIO Configuration + 1184 .loc 1 529 5 view .LVU317 + 1185 .LBB20: + 529:Src/stm32f7xx_hal_msp.c **** /**UART8 GPIO Configuration + 1186 .loc 1 529 5 view .LVU318 + 529:Src/stm32f7xx_hal_msp.c **** /**UART8 GPIO Configuration + 1187 .loc 1 529 5 view .LVU319 + 1188 0048 1A6B ldr r2, [r3, #48] + 1189 004a 42F01002 orr r2, r2, #16 + ARM GAS /tmp/cc5mtMNQ.s page 35 + + + 1190 004e 1A63 str r2, [r3, #48] + 529:Src/stm32f7xx_hal_msp.c **** /**UART8 GPIO Configuration + 1191 .loc 1 529 5 view .LVU320 + 1192 0050 1B6B ldr r3, [r3, #48] + 1193 0052 03F01003 and r3, r3, #16 + 1194 0056 0293 str r3, [sp, #8] + 529:Src/stm32f7xx_hal_msp.c **** /**UART8 GPIO Configuration + 1195 .loc 1 529 5 view .LVU321 + 1196 0058 029B ldr r3, [sp, #8] + 1197 .LBE20: + 529:Src/stm32f7xx_hal_msp.c **** /**UART8 GPIO Configuration + 1198 .loc 1 529 5 view .LVU322 + 534:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 1199 .loc 1 534 5 view .LVU323 + 534:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 1200 .loc 1 534 25 is_stmt 0 view .LVU324 + 1201 005a 0323 movs r3, #3 + 1202 005c 2793 str r3, [sp, #156] + 535:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 1203 .loc 1 535 5 is_stmt 1 view .LVU325 + 535:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 1204 .loc 1 535 26 is_stmt 0 view .LVU326 + 1205 005e 0222 movs r2, #2 + 1206 0060 2892 str r2, [sp, #160] + 536:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 1207 .loc 1 536 5 is_stmt 1 view .LVU327 + 536:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 1208 .loc 1 536 26 is_stmt 0 view .LVU328 + 1209 0062 0022 movs r2, #0 + 1210 0064 2992 str r2, [sp, #164] + 537:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF8_UART8; + 1211 .loc 1 537 5 is_stmt 1 view .LVU329 + 537:Src/stm32f7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF8_UART8; + 1212 .loc 1 537 27 is_stmt 0 view .LVU330 + 1213 0066 2A93 str r3, [sp, #168] + 538:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 1214 .loc 1 538 5 is_stmt 1 view .LVU331 + 538:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + 1215 .loc 1 538 31 is_stmt 0 view .LVU332 + 1216 0068 0823 movs r3, #8 + 1217 006a 2B93 str r3, [sp, #172] + 539:Src/stm32f7xx_hal_msp.c **** + 1218 .loc 1 539 5 is_stmt 1 view .LVU333 + 1219 006c 27A9 add r1, sp, #156 + 1220 006e 0548 ldr r0, .L73+8 + 1221 0070 FFF7FEFF bl HAL_GPIO_Init + 1222 .LVL79: + 1223 .loc 1 547 1 is_stmt 0 view .LVU334 + 1224 0074 D5E7 b .L67 + 1225 .L72: + 523:Src/stm32f7xx_hal_msp.c **** } + 1226 .loc 1 523 7 is_stmt 1 view .LVU335 + 1227 0076 FFF7FEFF bl Error_Handler + 1228 .LVL80: + 1229 007a DBE7 b .L69 + 1230 .L74: + 1231 .align 2 + ARM GAS /tmp/cc5mtMNQ.s page 36 + + + 1232 .L73: + 1233 007c 007C0040 .word 1073773568 + 1234 0080 00380240 .word 1073887232 + 1235 0084 00100240 .word 1073876992 + 1236 .cfi_endproc + 1237 .LFE1191: + 1239 .section .text.HAL_UART_MspDeInit,"ax",%progbits + 1240 .align 1 + 1241 .global HAL_UART_MspDeInit + 1242 .syntax unified + 1243 .thumb + 1244 .thumb_func + 1246 HAL_UART_MspDeInit: + 1247 .LVL81: + 1248 .LFB1192: + 548:Src/stm32f7xx_hal_msp.c **** + 549:Src/stm32f7xx_hal_msp.c **** /** + 550:Src/stm32f7xx_hal_msp.c **** * @brief UART MSP De-Initialization + 551:Src/stm32f7xx_hal_msp.c **** * This function freeze the hardware resources used in this example + 552:Src/stm32f7xx_hal_msp.c **** * @param huart: UART handle pointer + 553:Src/stm32f7xx_hal_msp.c **** * @retval None + 554:Src/stm32f7xx_hal_msp.c **** */ + 555:Src/stm32f7xx_hal_msp.c **** void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) + 556:Src/stm32f7xx_hal_msp.c **** { + 1249 .loc 1 556 1 view -0 + 1250 .cfi_startproc + 1251 @ args = 0, pretend = 0, frame = 0 + 1252 @ frame_needed = 0, uses_anonymous_args = 0 + 1253 .loc 1 556 1 is_stmt 0 view .LVU337 + 1254 0000 08B5 push {r3, lr} + 1255 .LCFI25: + 1256 .cfi_def_cfa_offset 8 + 1257 .cfi_offset 3, -8 + 1258 .cfi_offset 14, -4 + 557:Src/stm32f7xx_hal_msp.c **** if(huart->Instance==UART8) + 1259 .loc 1 557 3 is_stmt 1 view .LVU338 + 1260 .loc 1 557 11 is_stmt 0 view .LVU339 + 1261 0002 0268 ldr r2, [r0] + 1262 .loc 1 557 5 view .LVU340 + 1263 0004 064B ldr r3, .L79 + 1264 0006 9A42 cmp r2, r3 + 1265 0008 00D0 beq .L78 + 1266 .LVL82: + 1267 .L75: + 558:Src/stm32f7xx_hal_msp.c **** { + 559:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN UART8_MspDeInit 0 */ + 560:Src/stm32f7xx_hal_msp.c **** + 561:Src/stm32f7xx_hal_msp.c **** /* USER CODE END UART8_MspDeInit 0 */ + 562:Src/stm32f7xx_hal_msp.c **** /* Peripheral clock disable */ + 563:Src/stm32f7xx_hal_msp.c **** __HAL_RCC_UART8_CLK_DISABLE(); + 564:Src/stm32f7xx_hal_msp.c **** + 565:Src/stm32f7xx_hal_msp.c **** /**UART8 GPIO Configuration + 566:Src/stm32f7xx_hal_msp.c **** PE0 ------> UART8_RX + 567:Src/stm32f7xx_hal_msp.c **** PE1 ------> UART8_TX + 568:Src/stm32f7xx_hal_msp.c **** */ + 569:Src/stm32f7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOE, GPIO_PIN_0|GPIO_PIN_1); + 570:Src/stm32f7xx_hal_msp.c **** + ARM GAS /tmp/cc5mtMNQ.s page 37 + + + 571:Src/stm32f7xx_hal_msp.c **** /* USER CODE BEGIN UART8_MspDeInit 1 */ + 572:Src/stm32f7xx_hal_msp.c **** + 573:Src/stm32f7xx_hal_msp.c **** /* USER CODE END UART8_MspDeInit 1 */ + 574:Src/stm32f7xx_hal_msp.c **** } + 575:Src/stm32f7xx_hal_msp.c **** + 576:Src/stm32f7xx_hal_msp.c **** } + 1268 .loc 1 576 1 view .LVU341 + 1269 000a 08BD pop {r3, pc} + 1270 .LVL83: + 1271 .L78: + 563:Src/stm32f7xx_hal_msp.c **** + 1272 .loc 1 563 5 is_stmt 1 view .LVU342 + 1273 000c 054A ldr r2, .L79+4 + 1274 000e 136C ldr r3, [r2, #64] + 1275 0010 23F00043 bic r3, r3, #-2147483648 + 1276 0014 1364 str r3, [r2, #64] + 569:Src/stm32f7xx_hal_msp.c **** + 1277 .loc 1 569 5 view .LVU343 + 1278 0016 0321 movs r1, #3 + 1279 0018 0348 ldr r0, .L79+8 + 1280 .LVL84: + 569:Src/stm32f7xx_hal_msp.c **** + 1281 .loc 1 569 5 is_stmt 0 view .LVU344 + 1282 001a FFF7FEFF bl HAL_GPIO_DeInit + 1283 .LVL85: + 1284 .loc 1 576 1 view .LVU345 + 1285 001e F4E7 b .L75 + 1286 .L80: + 1287 .align 2 + 1288 .L79: + 1289 0020 007C0040 .word 1073773568 + 1290 0024 00380240 .word 1073887232 + 1291 0028 00100240 .word 1073876992 + 1292 .cfi_endproc + 1293 .LFE1192: + 1295 .text + 1296 .Letext0: + 1297 .file 2 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 1298 .file 3 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 1299 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + 1300 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 1301 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h" + 1302 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h" + 1303 .file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h" + 1304 .file 9 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h" + 1305 .file 10 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h" + 1306 .file 11 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h" + 1307 .file 12 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h" + 1308 .file 13 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h" + 1309 .file 14 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h" + 1310 .file 15 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h" + 1311 .file 16 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h" + 1312 .file 17 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h" + 1313 .file 18 "Inc/main.h" + 1314 .file 19 "" + ARM GAS /tmp/cc5mtMNQ.s page 38 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_msp.c + /tmp/cc5mtMNQ.s:20 .text.HAL_MspInit:00000000 $t + /tmp/cc5mtMNQ.s:26 .text.HAL_MspInit:00000000 HAL_MspInit + /tmp/cc5mtMNQ.s:76 .text.HAL_MspInit:0000002c $d + /tmp/cc5mtMNQ.s:81 .text.HAL_ADC_MspInit:00000000 $t + /tmp/cc5mtMNQ.s:87 .text.HAL_ADC_MspInit:00000000 HAL_ADC_MspInit + /tmp/cc5mtMNQ.s:318 .text.HAL_ADC_MspInit:000000f4 $d + /tmp/cc5mtMNQ.s:329 .text.HAL_ADC_MspDeInit:00000000 $t + /tmp/cc5mtMNQ.s:335 .text.HAL_ADC_MspDeInit:00000000 HAL_ADC_MspDeInit + /tmp/cc5mtMNQ.s:408 .text.HAL_ADC_MspDeInit:00000050 $d + /tmp/cc5mtMNQ.s:418 .text.HAL_SD_MspInit:00000000 $t + /tmp/cc5mtMNQ.s:424 .text.HAL_SD_MspInit:00000000 HAL_SD_MspInit + /tmp/cc5mtMNQ.s:600 .text.HAL_SD_MspInit:000000a8 $d + /tmp/cc5mtMNQ.s:608 .text.HAL_SD_MspDeInit:00000000 $t + /tmp/cc5mtMNQ.s:614 .text.HAL_SD_MspDeInit:00000000 HAL_SD_MspDeInit + /tmp/cc5mtMNQ.s:662 .text.HAL_SD_MspDeInit:0000002c $d + /tmp/cc5mtMNQ.s:670 .text.HAL_TIM_Base_MspInit:00000000 $t + /tmp/cc5mtMNQ.s:676 .text.HAL_TIM_Base_MspInit:00000000 HAL_TIM_Base_MspInit + /tmp/cc5mtMNQ.s:839 .text.HAL_TIM_Base_MspInit:000000ac $d + /tmp/cc5mtMNQ.s:848 .text.HAL_TIM_MspPostInit:00000000 $t + /tmp/cc5mtMNQ.s:854 .text.HAL_TIM_MspPostInit:00000000 HAL_TIM_MspPostInit + /tmp/cc5mtMNQ.s:983 .text.HAL_TIM_MspPostInit:0000007c $d + /tmp/cc5mtMNQ.s:991 .text.HAL_TIM_Base_MspDeInit:00000000 $t + /tmp/cc5mtMNQ.s:997 .text.HAL_TIM_Base_MspDeInit:00000000 HAL_TIM_Base_MspDeInit + /tmp/cc5mtMNQ.s:1089 .text.HAL_TIM_Base_MspDeInit:00000068 $d + /tmp/cc5mtMNQ.s:1097 .text.HAL_UART_MspInit:00000000 $t + /tmp/cc5mtMNQ.s:1103 .text.HAL_UART_MspInit:00000000 HAL_UART_MspInit + /tmp/cc5mtMNQ.s:1233 .text.HAL_UART_MspInit:0000007c $d + /tmp/cc5mtMNQ.s:1240 .text.HAL_UART_MspDeInit:00000000 $t + /tmp/cc5mtMNQ.s:1246 .text.HAL_UART_MspDeInit:00000000 HAL_UART_MspDeInit + /tmp/cc5mtMNQ.s:1289 .text.HAL_UART_MspDeInit:00000020 $d + +UNDEFINED SYMBOLS +HAL_GPIO_Init +HAL_NVIC_SetPriority +HAL_NVIC_EnableIRQ +HAL_GPIO_DeInit +memset +HAL_RCCEx_PeriphCLKConfig +Error_Handler +HAL_NVIC_DisableIRQ diff --git a/build/stm32f7xx_hal_msp.o b/build/stm32f7xx_hal_msp.o new file mode 100644 index 0000000000000000000000000000000000000000..2270d73beef04f5a5c57cd54e412796f7299e17c GIT binary patch literal 32220 zcmcJ2d3;pW`S-c^&YjF8lgmsJB_QC01PEJJmS_P{vOfaIN zRq6^B2=29N>w?v`XsfmEt$SUHRqNVC+e#O;Shd!={l3q+&zane^zHlm`S|Kdfk^FfAOV@THPmRcrQ!4^;lU#T%x8(YEJF! z+N>Z++UI)?W!sjtu_bNhUQ@ObykHE);PmaFabC=PTg}xgH>70Gg^ML-*&a!Av{)gubMLUeVOxyN6pF|_iZsTu< z^p7sFrP`w%!Mrrd{rw^FP_nI*b`Ib5{R6IAkvD5k;hx!h=IoifXZLhtKlOHc*Ys6a zS7`_5A2|F#^M^sh7`4kq;lk&qN)HJ3fM}z!9X}RobUf@6kD-t1*EE0lujs5%eOBQW zV&?42jTv(;^A*h9H|y4PyEpl>MhmZ)efgZrsLUi1z?ml2F;q6nsOohReNKL7U6(YANW>^K+Y)N_)WB&F>0 z(}yzcD4Nc*As_ygQj?{WeZJ?A@Cd{N`d*Ds9sA&}i!fJ=QP-$B>K;Xubxnrl=D|rg zPdwT!HGEM$n!BWW_@MZJ^AoocE`tv&8sOk;kRgq?W=cDmZ*}WS03%KJ@W^Y z4al-{@}nKLA71^6AN+US{vYFZqKw;l2mFXz5lzPJeOYo$MU|bAM3stBKgXzF#;AcP z)TbBj71L+$oipmmpF28>`~Q-R#n%ssGvNc8vwk}c-5iJJO6sc!Wn+FC(z_pylYJ{6 zGhEQ&(l+D5_gT6S$L7kCaVOoAcCiUrSK7nKvxcdC0cpKdg6rOZ5QDB~vV=&uCS(dR z?D}S!5L;azx`jBy_3fjCIMcP(CB$~u;v6B)Hfw#*Z9WZ2&HO28HShP3(zVd(GT(uu zX-+bPaGOiBg-A2c@e1KFe>hPHuelWGbn|@3XP8wJV6iy~t!J7iqTDjm(c%R26`1HZ z&w)Jw^F6eZWoAQ9ws{8RbIjSW?I`oRFyUx3=V&1&ni15>H9zzVG0B_?`N`&V)IG+$ z57tgGTj7$a=3Lk|&8&k}$C?MBEolA#R^^#<(AIRb4jS^!hoP;&JP-EFFe_l;O!G3h za+djB)G9Pjg#OuP8+td#`~^zpn%~Y4VxGAUwdR{cXtBurA@mfRFT=tT^Ey~tYMy5a zQDz>1&T?}Ibr+cXaJ|sH4_;klzKpty%{tgnVg426$C)M2aJ=~glz+|K3O_F~--HcI z&8s1^%-jMmonT%A?sD@Ka4XGY&{mcCK1LyA{vAH4HXlQ;Ys`;PUTfy!dWG2w&2{Fj z=uy4-b!b~@ZifA<%wpKkU~YgP8c|<}Ci4;WB5b|_nbqbGagLbx;v6-LAk$*DL(dxX zO~|e_PeI*v=FKQsZ=Q>`PBfo|g&WK;d~%Z6f_68Wdm(eOS&i#c%*UXo)tm>PY%&FU z5i@VYb-Vco^tZ#TLrL8HK1Qn3Tn25M&9l%-mw5wfb(7-^9d6rSRp0*2?xD#mHSTL!F%GctQ)<#TM+O6n{*JXD1B}6)vUyM&i37XYJdKs>- zR&<(3Bc3m;Kkj`2qn;U!2>r=`RFf|b-JbF4!|KF4IP^)8XWWO9o20g(rp3})7~z>MdaEXZsi@>fh2T9xF#7nq!9 z)e`w4lO@(FB41*1f%O^Ynf_}gE37VZ`pZl%v3`N^(O+S5xpg*iUuCk|+Ck)NOx9&q z!;06LY7p+15fSH;2WPcwKJ!-4r2dR~Pl^gpNQy1+MS9Db?j27fcy2Nf9(tfVRNyrNqIGfDlg6umw$ zm*^K1y%DJs-hWZin?RRgRa10_$T~zx@nyrtG=!0+(N@Uy9c?uV%@DRo!feFeMicJ$ zk)&NW86>THTsL9mVQF)gb_q$Z#KaNi2>hy<3n@vMk7H^Y!o2}A!klMxKuA?7)9$1y z@4^OQ2C@90fl<0%Xj}n?&+lI8b)gCCRm>H4gU?<$gmn*$aEF<6SqF%0VbWvmCvpRm zKH>fuY;m8WKWJ-g_pT+4zeNY#@ubFo6WN{AsKaD;e^TQH(wG?2*bN)qr|Etu^6hq? z=`F*`XSI>g_N2z&p}X#{Pa^Yi|7&dpx_3;Xw)OlRs{-NUzJP@btkuN5gvml{Baz=^ za-Nlj78?9qW)!j^PvUZby zf68QsRY2tZOmnrh; zcuz(`w=z-aDPtjF4H3DJNte}x5%(yK9_z1gh(~GkS=DIXbAoEX3ZTcHDkgKJt)3bt zbFEKcx@RSmQ>hCSb$M(IP(UtqlrAA9yp+b_8bt&7kP&*-tEvTlV{ zhE_e7<=rC5CDwD85}qrVTyFh{I(Ze7)zE(77tCc|#g zsl->}t?-@(7g!dY>^+{HF09?q>0QdC%ksj9UN!a}>rzCmSB<^T(uq`q?YCB=Yu?pd zH^;gTdC{xVX0CN2jPtI`rj(D}x%C_@@~XiOT2sl4Q@Cz{WkJf@#$=&&9chkpT|`DH zy5>Dq|0#6%>byVq{*!t_BkFx@I$f&~^*)hDoum;Rrj9+8XS;HNwHTw~eR}$5l3O9i z+xu*uJ>E;?czb`z!pr3_c%Nso8t$ZfYPgo1njjCouAc`*IWD@n_vNOSct?;lt=C~? z`q-qq1(njrCfz>~x9MY(?k@B=T{+%o?M8^DFJ}k%ts999Dc1`3T%!g*fd>MJiWrh#}rulss>o%`M983`I0?dkxujxBb*+Uw9 z!Hko6J97o;+_=UI{)v?{2N=LGGEQ()~wWM-Vp+(PSA>evqE&a)nczcS7b+L2NsVR!s^a_e%;-;CWs@}{0&of(Q&i;TU&nGn+R zJ2FG{AonquK={!1-5tjGWn8DXp^h)tSLA(!I=>tz-`E0?4QKnt7Ko#WJGMZ~rD>t2 zw9o3L`K}_%Z>^yity4pREK8MF8m)j_dt>ICuW6ryG+(29Z5|KzXl9K1U|x$38Ri{u zr%PlB%t~LmX8aPe9;%?~AE#-h7;w{%VHW0g1d3+Xk^e;2F6!1&&6ohbhlEs}kfz0{ zPQPsPZdBCF3&~L;YY0_+D>NfSbx26nY1FhksLuUpM>Ai-SvTLq*=44o&mJ>~v)?=p z=b(8ll;BbBd+2~~jb@yNdJ`IaCu?4M@*AMs;oGFmA_CDBpyj|9(`J(M5ncgWKYeZ5 zOlppvE&LfC@U?5RTBUq2KWm!YcC&CWF>t zgkN&eW$4trIi`08z z<_rGj$(*z@Uz$qSDrsfDJcY)BlGa|tYUZoc$QgQmflOMNuTNbgg&Snj%KXg~`CvFd zY<)sz{%*=jn4;%LWDd)GbE=);T4WB(`~wTGw`Nk0|HQ%@tPpkM5OX(L#ni*U9Q(O! zcaudoW0`*|uwXsXl9hqoa^}0~z0!;>i=H@S{+-DlneZ~-pK2$(0h#bJKVUK;*U`+6 zrrOhB#5#?J^y9pDWJ70K?G$gHN>Xl~X?v6TgGD26`qv2CWlTj4u_F{)%2qXyH=b<@Tie{5g|~ zNNu3(#%MeqXk{5!TKpAv%%65J*$C9GIQ<`!r3vnOHS+qQHgf zI2yq7PiVQHN~P+_+Uw|iz@*YQRH>|B*P5!OBjVD22Yvrc>Z2>PM>j3gv;y$8xjH>p z#TQX@!lBhp!FOCoA$Nc^pNK+~2I(^mr=3ucr-e-)ebtz!t=7s(-w;M+nszVpf%Ylv zft0VVJ=x zA%cAIPjCvB;j{`>&$9LEo_V4m!ezVdGOb<&JGltZ%RN!NxhV962YSNMVo{b{E37j^3@{`;f z6?c;;XaI*ivK(A{fDrRU+3 zwDH!Y6>F3gT_XQ@C?GqZNOCtRZjZ>{1P+bdpOV}@#T^j&=Yw-KJ_g#hdw-_lCPcw{ zaPFrrfQxQmWK@)BC8FRIaA`U&OmaoRcCHbz%d~oDg&kZWu9%|WMwUO9i&i@1gWqF$ z9`R|~Su~)t*>6k0orr+f{*AgbyM{W5HJgYNP)dovAP5nfm2cYG5wRXQK1RAYRs;)~ zYY&i5ax~1V99I-um|5B{Xjc8rp0f8q_8Zh#K^|tkZ0v8dsI8Y#_%uGV<&1roCv3}X zIbq-9`TFSg{6$cJs1?0IN$2Q$T13J1%$$twI{ib;88?F|=lU$|Tx4JEM%zbS zC@yz_{uwIG(XkL~H_oN&Ruo3@DVPZf8jt>@R(m{%$8|3#>t^t$T6)0^MoX`otbrG8F*uo*}=>Pk-q`8dhj_t$&52IEb?y$ z<6(R*PckoJW{b!t#;@@CQIdHHGuMj(O2Rax2f?)cVf&X-S#rGJO)`b;EMig)pqlCM zi(S+9u&j9_n3M))+f1zrlT;suTm)xP@IA084=hn^QScV4J29z_2Zq{uht+LW^3FN` z4^{>vv??0DPbt4w+QU}@<{20zjn=Mw9n{hIJP5)bn>s_@+3pz;bBR%ikIkrO#+g{m zHEki%$ZrrEw5A5M8CG_NVI5}u(q;+*&q4`aR_1|oHLX6IRAl6VRg9Y0@ML6+sm{z4 zhDRx?NXPyU1xd|RFo7$Wwk>#!E-Qen&nA9=D!E@x|o$ z=uz4%AK5t3l;-C;9KelETHr8h3L2eUq@CcCc0yv7Z;7mbOp)M1_>Btj!q9lR`fOWr zYO^V_!!|pG z=GwL(CdpSzd>1UY?9oQt(m?^Pi?bxov#$|FUp=5+Xd+AiFN<{Xf$@=;{c*|1;yR)y z+iU{T;$(wN9?sT~BB^B$VF5mdIO`sbE+~T&gYZJd0FFCo?!g`clF>wqlkIGW_DH18 z$xpqWf&yqGz!qkl`9vRYvk8{t0(rNU= zpwWR`z<)gci{a!_^ow8F!AT5{G#QS#7nrOcjV zUwa5?2SVlQ=#Vr~)G7NQ89GQm9poN5Xt?O0Xrtp{dA8>;U5+q)A>%wo1^++vcDu>j z$Dq5q_9=E78V(SdhHacv}-V=SkNj(8`eFiPV! z54N|r#!1&#IGYE$`;S!K(HlEbajc^~wYaCJb*Q7a_bcVpqoIyeX(~;0_a3QuI5tRK z9A_ewAHfoo9zh36(a%&3)L?u6U_y1jH`d(;8SJl@v<-LnB<6SbEt9clYWPB$u8g1I zrq!6KY3o-8vo&qy${-%GO~M-=nl>i$iogxJX}F8c9EqFp>bYi`LDSgCyeXFjhfwwJcseqmGQ?&;xST5v3aap3!-wK z@=el{$~UGhnMaZ&2q#3$G`De5P|q0GhgqE78-?F-~vTAs6C=pG> z5^+&k9cr!b>rS+sJ`k^tcZ%q0yy1yc8J)^Sw7Rt}*4NP!SNzIwRcTFAL_|WNR$HmF zc2hN8%CCwIcSJ~cDAWjLwDdIew{KAzLX}OWtyTit1P*R^NvOG9f}eP*T&e88(Nj${NCC1^QCf8chtwW4#M)ebkZ^fTjrQ z#D<1M!vGR?sjMH3_r%*1-Ti%{zARMMS`)ErwT$2$s)qR1cn>$`P+Ve**qsfFaD1?P zpese$X4{$6kCytz)=*t#Q&UaDxSrIs)U~c#wI-a@R$mr{wuT1aYQ~5d?i=df+!yZ% z(qCzi5!JRlF5xt1M;qh4w2Idb_sRamdTbNA(ACzq*ic+VM(8z6G6`c?Wv z_jPt}7BF;yt(;`4)g+%~%pbCca0qlKcRyJsJB+9e zL2Z3sXTOTNn)NO9Jd)^OSxN^ZBQ;y&eR2|r#@NsnijLCOnzeSHD~A*PkvJ^w2oFjS z%`Gch>!PhS;nLRnrZFe3sf-|eXD~CI}`%?!EDM+R|6337$ ziz#oQYo&IIASPxHb88|Iyn`JXp+-af!usZY`ujEq$Cz9l9tDvd(})p1%I#6V=EYPhpAoEQ{MZG+97 zk5*hb6p{YYD!htMyp{`Z9@xN7+p(&GiDkr9zO}YXmd}agSA4f zJ8~6@tY;PB*kE_!bgXubjaU_Azo{S1s|1Wq9dt(zW&hyza=F?xRz_Eeh8EbW)|E9w zvCZ+?*lFymV6cah0b}n$II%`!-KnP2Xn$p_BQ?=* zsi1S2JeSM!0y#v=ThNu7?BNE^%Kd#{k1419;)l3l~oNj*gI`mkQyuKNx2=# z(SdlpBN-OsH*Rvthz-iP!I)tIkJt9}pGJ{C*xzGs_ zX~Dw5o3nOoTI5_>nBu!oSFEou&Ra2TKx--+TbpZZVQXtkWtF|AV+)9WlsdXR)-5}Q zM(gTpWrf!I(8!2vXhBLtU3f4dy}zcZp*ggwrW)()R|CCfMD8tmS_Zo}Q`VKcXVrb_ zN4f2DE=Mv=tXo&T!X9S1q&bsjS!*(B(yhQ(w&9MQ0NLXV4A~aqwkEQ+rn*$lAG>;D}7Q@ezz?(hbez2C`eOI?;F{JlNeYGd9hT$~HVWMW8OV(xcrt&PVL!-Mt;XLF>5cFN*N zi?+x5$nVmrb*ITmkm#|)wxfTT)_s{euq@hxN&81Nhr?@m?>}z9&T$DN3ao< zw@acq8m_6q0!cQJ!b;o%ZH@EfOD1IHRgy@(Bctqr?7JYj1ktQ7U4&_mCe@vm+F!`q zt}5J9VfDcc^-!{1Doc(R?JNKVSch+Ld2dvJqh2i(ePj8h~&5KnZ| z-8Anp1d7Y)v;bp>+e9_lOQibbqRN|a&IEE5lQ}`IWb$f3vZ`$vFA5ZSD*EtTV=y6a zlhL2jR?e#IN^B)k0^2dHoY18JCU&>liSqq*a*LwILyfYU)Zu!LZ+j2J%eP#MXc>}Q zDK*B8*eH?zXIDz91aQseAdQ06oMdIyoJRIroBd=nMb7B}8>idQg6ted1 z2gR-Oxx9-^-K0QaMXOTia5LYg$e|mbFO@o(Qq+B0OQf%$(J zHle&C(K9TxnH(m$L?ss`;*8&n%6X~o%BV?RFy&kv_v}mFncJ=kUpzWqin zlF!qWD7rrOTupUR?mHBrBvWQ(sG+7Zf)!jnS=vG_$FrW{_5?qNh}cH8w#qLJy8Bvr z#X@KCL}F-cy<68m*wGO0+nnf{VGq~vs#4P= zH-f9zR8}KS$2-Q(%C|1*5%;l1$76dY`e{8erFrA;{IG)SFo$axn_#n1_jmTxvZ^=-@ zZjk5NKuhwTwz_+eA1PAo$z&?=W#RtQXcgXSFUNz!eZ1Y5_aw))stgorUW4q>SY6*7wM~fe zEjKz>UB5O$0oC3jpGl0}*1)!kaXTm8=2eGUA`N_3KRie~{;^CIiS=#45;4@@Gb|st zVjj}wku$W6O2-#$5_Kq+a6|~m0;JHP0eJxty zNT&NT*&#WksoP=a4zoTwA|0hVmVC%C7L#gQz^2OnsJtS#Iq1%~d}1$A$)Tdfp}8+! zg~_eFvv+X=C$&%D4;aN151|`w!FPD z<8?I}4I$yzhS%6UdW>$boXNX`P-rBKMA@Etk3@UUwY+N9mkp(C2$B)Qx#HI7gW~V+Jx8EH55(i$LJJa%I ziX8dXuYIC74=OEBiv9 zs!nf1R9ZPZ%x}2PH!hI%pVY$XRt^+6>(kp3sy@B4qmGAhQE9oT-CVTmszSR?KD`;m z{6fWd>ZP|Wl-?k&)j@AxpnQk4=pM4jLtPqY6TO+C>Q)?ZI&v^wxvpz;8}CD0-X2 zCGh&X<8X;wP-AbCjJ>HsLI%F@A1`l8`45vC@Irv&Fz~05xb#;B z$`4tHuf@1lhaVR;iU1P5A%*S*P4&sg^ryIIr|`eYe99qNh_7#_@NY_?A4;L01x@-X zw`3vS=xs2fAC`2c_<(83Az6r*G%$%zIU@`4FpUU4$o?|sQ|`#Z_=lLLIhRGFd!#3S z1^5FSd*7!Xs!*2aZztpqgy`f-Aot8)dBj8_NBFj5{C6BlJ>#D-s%Ck=PEy!y9pTH^ z@!#c<+_(oxRDeB@y}MLORUzo)qh(c=a?eV|vJZ|g=BP~F1|)r<3b-5gyMF1#_FKk; zm&4zL*ApTbZze>3rtzinKXdteTt1z!94}`xmNC{b(wmy;3-K3kgp0=7`4-X8_Z>n6 zH?2FQr+~4A5baZ3Q~UJ7E79jLeLd64KG`1hC8!*DJRyRUUiKwyV@$PYfaSLm!j8#= zu)__+A2Gblt~CFW9XQqGYAXqwSme}Rq|^Y8yF*u>lsgB>|i{Vk?bKo zWDnt)jOQ|5$apE^KE|sVuV*B`P<_hbgm*I1d?)%r#zz@{!FZ7I*Nks4zQy=wMjC(8 zLu(x2zZq$g6HR|@Lg-`6V$5Zv`A_@;#yN~7jEfkTFjg_ruaQ!{CdL*<`jI3m-^AF- z*uyx;IKoIjJ3#XIyJCs-Cyzw$X1tv7Ta4dfq@Q;pxgRk8nDJi5hZ!Gde1`E?jP&cV zRR6b(e`NeC<6*{sGJeLW>vla4qs5rRIGHiXIFoT6V;N%wqx`u)*ip^&O2#lF{aP;B zxskDrv5T>fF~PWv@f^nU8Fw=7WxSH{+l)6devk10f6>MT}Q6-okh{P^0GHzr17UK(ye_+f?x8!ejCV5robfG24YvT)Zh$e5F~WE& z<4+kU`)v6d##M|F#!ZYvjHff6&G-$*os2g#-p=?V#wQtHW_+9RBSsUqB4qbu#@UP& zj4K$|G4?Q?!FVy_RgC)?f5P}U<4cTxWc+{;ZztP+V+=ADGcIFnWZcNOg>f6>MT}Q6 z-okh{qx@ZE^z%ig|G@YUM!ak-?Z{%B&REX4j*8Lwsh0pop)zhHco@z0DOGrF-+ zqy8SnSio4$SjD)SaT8-d<95a$Fh0WgE5NwrXyNaDsNJcI^BBLzxRUWi#xBMY z#$AlxV!VywUtv7NXk^>%PGg+UxP);P;|9iV#?u)`8Lwizj`1eO+ZgX){0ZX& zjE^$@mhoN2&loduZ2KlN&StD&T*0`Gv4`;t#)}!RV%*R86UN6GUt;_t;|Gj7HtaMm z0mdL>3u8Cq2;&8emowhP_+!RL8Gpz4C&s@qzR&nE;}?v_;>LsQn88SYT}^ZuW0dhk z##Y8o#tRsCF^)1`#dsa#O^mlO-pTkB|s2E@nXiS822;&gz<64ml*%Z_yMDi8%)w4U<@)AGoHYhVEj7c zZHzx-e3|iGMgtF!NN*8iC1WFFJ7XW?rHuO-A7uP3;}?u+Q=m79zqej+W*yNtJU`GZXVobhQc{|(ch zGiISK)h}i|o)C722;sXGjH?J?*Ba)>n2s}^N(lMwjC&aO6GGn|goyRK7=KC#eUC8z zmrTFF_zIW*nGp5fVf={8-P7#ybjEB#v{S%zCF4dej}s#2bu;!7qW#mDe;(5pFzzIT z{BFjp2%-ObO#guKCtUs{)6X!z#N}@@{a3~hxZH&wb|L-K85c1|89N!zW86oG_OB(x zntB7{O@!#jeT)w=KFa*J7%AqcemWucNETxjA?nX!oXc232>BBjn+Z`b%D9os`>1P<T0mhw- z`x&1igx==~aqsaGN~$MioKKjw1xbh}Ti5(a*S$zFCYVT)v#?YQ{z` zKbh$mE{{WW6a36?U}>4lyL*&X^a;V!v5WarV#rW zuOx&&zQgp*j6WoV{6kDX!uTYYzs~qOMu9`e*y8qEB5qS8Vmm6akZ~SkIpbo+6^yGG zBaCYq`v{Q}1{t?8Zf887@nXhN#w!@FWBe}TJ&gA=KEn6}{Jd`hBx|&fw$3uBD(^1BD#?6d1O{G8FH+wIEdaFEYsdI}@` zqz>6Ni;;eojPhWJaTQ}T<2uHZ7~2`?|I4C!{ftA5^n+$peg&g^jt2TWOy9{UpP!-p z0j7V(_&noFjBhZ?=Vp*U%=CwhpE7>QIMG1+$j|aQ88Dw|`J4>2d_D%G-;^Xd`Gb_e zCZAgzt%R za~b9HKG3_EzLxO@#{G=9Gty6SQC@zM@gSpoE{O6snEpNEUl`wIq@RMO`ttc9kbcFB z=*f(Ej58P)G9JgcoUxj*g>gM&D`Pt&{q_{);jo94{xtJgg%`-Ut&SkFF;S;)H|rq5BfiWvN%@ZxAwnLqAl> zc4WI~2ir>7UXT#&6);LWAT0AdP}+m`7Z4vP?SdUkhz2evggw=a($1g|4MYRy(0qe^ zO@y!~o8lApY#@Xk(`ek#KK&>h_4jE)v=bq}LH`|u&@cao73hPA(C4uKz>{`@mUcqF z^bhD3l0!RPEZ;+j_I5M9j}YzdXZm(RD1VaaX9!`(pP7D#5cbILg`nR>c@%aP5P~iw z41!-Ybb4DtmKU?CfC3x#Ut~6puL{WQxul%DiN3G7mSTBSs zBaKC|L}IYJZ8!n7|BC~+n-n7QdsnKqfKHAB(?A}1IFlTvfjm;>h)2gPd_4I4H@SI` zNo|+rggP*-Dz;Ar@nm{ z0LoqJQ2KVEz^N|*eSVaYKBSSPKFSkLeFvfMVU(#u>D!M2r@kG~N8>^I@CZJs?`d2+ z_0fOvvJ++MQ2L%gfm7d)9rodoc2eJ8aP8DL1q#Tg>QMUrgaW6&N1-nlWn>@HVp1RN zkDdDVLBWOKt3&Cd{j^ix8_*Yo5b4XthvaB{X2AD27OeY^x;ut zQXhSvPWseQ2YqknD{73lEJdGd1L6hwp7bHjC-pU@=qs8n#8nt$b*Q#BrN})o7r#kL z6N3*Ww-Fakzs&0s^nY{8c4;|Le(6uq*H=1z9w~iWQuOUac3KZT)DK$ImA-RR^!*z8 zNKPF}-}V%Je}um4Aw>G{2qdX*Uy8n>GW>uoZEE;X`gW)2+kuH1h79Qo;-l=lp7p65 zbxj4n+nEFbK1d&ZZcCB#_=f{WIL~-)iw+{cmt5SkebxCv2 ODVG?=vk%2|$o&s^^n!5! literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_hal_pwr.d b/build/stm32f7xx_hal_pwr.d new file mode 100644 index 0000000..94a6e4e --- /dev/null +++ b/build/stm32f7xx_hal_pwr.d @@ -0,0 +1,68 @@ +build/stm32f7xx_hal_pwr.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/build/stm32f7xx_hal_pwr.lst b/build/stm32f7xx_hal_pwr.lst new file mode 100644 index 0000000..c6b6bf8 --- /dev/null +++ b/build/stm32f7xx_hal_pwr.lst @@ -0,0 +1,2379 @@ +ARM GAS /tmp/ccO7avbH.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_hal_pwr.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c" + 19 .section .text.HAL_PWR_DeInit,"ax",%progbits + 20 .align 1 + 21 .global HAL_PWR_DeInit + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 HAL_PWR_DeInit: + 27 .LFB141: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @file stm32f7xx_hal_pwr.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief PWR HAL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral: + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * + Peripheral Control functions + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** ****************************************************************************** + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @attention + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * Copyright (c) 2017 STMicroelectronics. + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * All rights reserved. + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * This software is licensed under terms that can be found in the LICENSE file + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * in the root directory of this software component. + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** ****************************************************************************** + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/ + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** #include "stm32f7xx_hal.h" + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** @addtogroup STM32F7xx_HAL_Driver + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @{ + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** @defgroup PWR PWR + ARM GAS /tmp/ccO7avbH.s page 2 + + + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief PWR HAL module driver + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @{ + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/ + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/ + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** @addtogroup PWR_Private_Constants + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @{ + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @{ + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** #define PVD_MODE_IT ((uint32_t)0x00010000U) + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** #define PVD_MODE_EVT ((uint32_t)0x00020000U) + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** #define PVD_RISING_EDGE ((uint32_t)0x00000001U) + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** #define PVD_FALLING_EDGE ((uint32_t)0x00000002U) + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @} + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @{ + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** #define PWR_EWUP_MASK ((uint32_t)0x00003F00) + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @} + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @} + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/ + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/ + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/ + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Private functions ---------------------------------------------------------*/ + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @{ + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief Initialization and de-initialization functions + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** @verbatim + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** =============================================================================== + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** ##### Initialization and de-initialization functions ##### + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** =============================================================================== + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** [..] + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** After reset, the backup domain (RTC registers, RTC backup data + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** registers and backup SRAM) is protected against possible unwanted + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** write accesses. + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** To enable access to the RTC Domain and RTC registers, proceed as follows: + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) Enable the Power Controller (PWR) APB1 interface clock using the + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __HAL_RCC_PWR_CLK_ENABLE() macro. + ARM GAS /tmp/ccO7avbH.s page 3 + + + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** @endverbatim + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @{ + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief Deinitializes the HAL PWR peripheral registers to their default reset values. + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @retval None + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_DeInit(void) + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 28 .loc 1 100 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET(); + 33 .loc 1 101 3 view .LVU1 + 34 0000 044B ldr r3, .L2 + 35 0002 1A6A ldr r2, [r3, #32] + 36 0004 42F08052 orr r2, r2, #268435456 + 37 0008 1A62 str r2, [r3, #32] + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET(); + 38 .loc 1 102 3 view .LVU2 + 39 000a 1A6A ldr r2, [r3, #32] + 40 000c 22F08052 bic r2, r2, #268435456 + 41 0010 1A62 str r2, [r3, #32] + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 42 .loc 1 103 1 is_stmt 0 view .LVU3 + 43 0012 7047 bx lr + 44 .L3: + 45 .align 2 + 46 .L2: + 47 0014 00380240 .word 1073887232 + 48 .cfi_endproc + 49 .LFE141: + 51 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits + 52 .align 1 + 53 .global HAL_PWR_EnableBkUpAccess + 54 .syntax unified + 55 .thumb + 56 .thumb_func + 58 HAL_PWR_EnableBkUpAccess: + 59 .LFB142: + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief Enables access to the backup domain (RTC registers, RTC + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * backup data registers and backup SRAM). + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @retval None + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void) + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 60 .loc 1 113 1 is_stmt 1 view -0 + 61 .cfi_startproc + ARM GAS /tmp/ccO7avbH.s page 4 + + + 62 @ args = 0, pretend = 0, frame = 0 + 63 @ frame_needed = 0, uses_anonymous_args = 0 + 64 @ link register save eliminated. + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Enable access to RTC and backup registers */ + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** SET_BIT(PWR->CR1, PWR_CR1_DBP); + 65 .loc 1 115 3 view .LVU5 + 66 0000 024A ldr r2, .L5 + 67 0002 1368 ldr r3, [r2] + 68 0004 43F48073 orr r3, r3, #256 + 69 0008 1360 str r3, [r2] + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 70 .loc 1 116 1 is_stmt 0 view .LVU6 + 71 000a 7047 bx lr + 72 .L6: + 73 .align 2 + 74 .L5: + 75 000c 00700040 .word 1073770496 + 76 .cfi_endproc + 77 .LFE142: + 79 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits + 80 .align 1 + 81 .global HAL_PWR_DisableBkUpAccess + 82 .syntax unified + 83 .thumb + 84 .thumb_func + 86 HAL_PWR_DisableBkUpAccess: + 87 .LFB143: + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief Disables access to the backup domain (RTC registers, RTC + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * backup data registers and backup SRAM). + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @retval None + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void) + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 88 .loc 1 126 1 is_stmt 1 view -0 + 89 .cfi_startproc + 90 @ args = 0, pretend = 0, frame = 0 + 91 @ frame_needed = 0, uses_anonymous_args = 0 + 92 @ link register save eliminated. + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Disable access to RTC and backup registers */ + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); + 93 .loc 1 128 2 view .LVU8 + 94 0000 024A ldr r2, .L8 + 95 0002 1368 ldr r3, [r2] + 96 0004 23F48073 bic r3, r3, #256 + 97 0008 1360 str r3, [r2] + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 98 .loc 1 129 1 is_stmt 0 view .LVU9 + 99 000a 7047 bx lr + 100 .L9: + 101 .align 2 + 102 .L8: + 103 000c 00700040 .word 1073770496 + 104 .cfi_endproc + ARM GAS /tmp/ccO7avbH.s page 5 + + + 105 .LFE143: + 107 .section .text.HAL_PWR_ConfigPVD,"ax",%progbits + 108 .align 1 + 109 .global HAL_PWR_ConfigPVD + 110 .syntax unified + 111 .thumb + 112 .thumb_func + 114 HAL_PWR_ConfigPVD: + 115 .LVL0: + 116 .LFB144: + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @} + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief Low Power modes configuration functions + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** @verbatim + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** =============================================================================== + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** ##### Peripheral Control functions ##### + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** =============================================================================== + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** *** PVD configuration *** + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** ========================= + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** [..] + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) The PVD is used to monitor the VDD power supply by comparing it to a + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** than the PVD threshold. This event is internally connected to the EXTI + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** line16 and can generate an interrupt if enabled. This is done through + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) The PVD is stopped in Standby mode. + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** *** Wake-up pin configuration *** + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** ================================ + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** [..] + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) Wake-up pin is used to wake up the system from Standby mode. This pin is + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** forced in input pull-down configuration and is active on rising edges. + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) There are up to 6 Wake-up pin in the STM32F7 devices family + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** *** Low Power modes configuration *** + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** ===================================== + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** [..] + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** The devices feature 3 low-power modes: + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running. + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) Stop mode: all clocks are stopped, regulator running, regulator + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** in low power mode + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) Standby mode: 1.2V domain powered off. + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** *** Sleep mode *** + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** ================== + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** [..] + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) Entry: + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLE + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** functions with + ARM GAS /tmp/ccO7avbH.s page 6 + + + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** -@@- The Regulator parameter is not used for the STM32F7 family + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** and is kept as parameter just to maintain compatibility with the + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** lower power families (STM32L). + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) Exit: + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** Any peripheral interrupt acknowledged by the nested vectored interrupt + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** controller (NVIC) can wake up the device from Sleep mode. + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** *** Stop mode *** + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** ================= + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** [..] + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** and the HSE RC oscillators are disabled. Internal SRAM and register contents + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** are preserved. + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** The voltage regulator can be configured either in normal or low-power mode. + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** To minimize the consumption In Stop mode, FLASH can be powered off before + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function. + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** It can be switched on again by software after exiting the Stop mode using + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** the HAL_PWREx_DisableFlashPowerDown() function. + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) Entry: + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** function with: + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (++) Main regulator ON. + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (++) Low Power regulator ON. + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) Exit: + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** *** Standby mode *** + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** ==================== + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** [..] + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** The Standby mode allows to achieve the lowest power consumption. It is based + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** on the Cortex-M7 deep sleep mode, with the voltage regulator disabled. + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** the HSE oscillator are also switched off. SRAM and register contents are lost + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** except for the RTC registers, RTC backup registers, backup SRAM and Standby + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** circuitry. + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** The voltage regulator is OFF. + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (++) Entry: + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (++) Exit: + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset. + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** *** Auto-wakeup (AWU) from low-power mode *** + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** ============================================= + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** [..] + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** Wakeup event, a tamper event or a time-stamp event, without depending on + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** an external interrupt (Auto-wakeup mode). + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + ARM GAS /tmp/ccO7avbH.s page 7 + + + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (+) RTC auto-wakeup (AWU) from the Stop and Standby modes + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** is necessary to configure the RTC to detect the tamper or time stamp event using the + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** @endverbatim + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @{ + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * information for the PVD. + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @note Refer to the electrical characteristics of your device datasheet for + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * more details about the voltage threshold corresponding to each + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * detection level. + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @retval None + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 117 .loc 1 260 1 is_stmt 1 view -0 + 118 .cfi_startproc + 119 @ args = 0, pretend = 0, frame = 0 + 120 @ frame_needed = 0, uses_anonymous_args = 0 + 121 @ link register save eliminated. + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Check the parameters */ + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + 122 .loc 1 262 3 view .LVU11 + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + 123 .loc 1 263 3 view .LVU12 + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Set PLS[7:5] bits according to PVDLevel value */ + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); + 124 .loc 1 266 3 view .LVU13 + 125 0000 1E4A ldr r2, .L15 + 126 0002 1368 ldr r3, [r2] + 127 0004 23F0E003 bic r3, r3, #224 + 128 0008 0168 ldr r1, [r0] + 129 000a 0B43 orrs r3, r3, r1 + 130 000c 1360 str r3, [r2] + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + 131 .loc 1 269 3 view .LVU14 + 132 000e 1C4B ldr r3, .L15+4 + 133 0010 5A68 ldr r2, [r3, #4] + 134 0012 22F48032 bic r2, r2, #65536 + 135 0016 5A60 str r2, [r3, #4] + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_IT(); + 136 .loc 1 270 3 view .LVU15 + ARM GAS /tmp/ccO7avbH.s page 8 + + + 137 0018 1A68 ldr r2, [r3] + 138 001a 22F48032 bic r2, r2, #65536 + 139 001e 1A60 str r2, [r3] + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + 140 .loc 1 271 3 view .LVU16 + 141 0020 9A68 ldr r2, [r3, #8] + 142 0022 22F48032 bic r2, r2, #65536 + 143 0026 9A60 str r2, [r3, #8] + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + 144 .loc 1 272 3 view .LVU17 + 145 0028 DA68 ldr r2, [r3, #12] + 146 002a 22F48032 bic r2, r2, #65536 + 147 002e DA60 str r2, [r3, #12] + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Configure interrupt mode */ + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + 148 .loc 1 275 3 view .LVU18 + 149 .loc 1 275 17 is_stmt 0 view .LVU19 + 150 0030 4368 ldr r3, [r0, #4] + 151 .loc 1 275 5 view .LVU20 + 152 0032 13F4803F tst r3, #65536 + 153 0036 04D0 beq .L11 + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT(); + 154 .loc 1 277 5 is_stmt 1 view .LVU21 + 155 0038 114A ldr r2, .L15+4 + 156 003a 1368 ldr r3, [r2] + 157 003c 43F48033 orr r3, r3, #65536 + 158 0040 1360 str r3, [r2] + 159 .L11: + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Configure event mode */ + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + 160 .loc 1 281 3 view .LVU22 + 161 .loc 1 281 17 is_stmt 0 view .LVU23 + 162 0042 4368 ldr r3, [r0, #4] + 163 .loc 1 281 5 view .LVU24 + 164 0044 13F4003F tst r3, #131072 + 165 0048 04D0 beq .L12 + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + 166 .loc 1 283 5 is_stmt 1 view .LVU25 + 167 004a 0D4A ldr r2, .L15+4 + 168 004c 5368 ldr r3, [r2, #4] + 169 004e 43F48033 orr r3, r3, #65536 + 170 0052 5360 str r3, [r2, #4] + 171 .L12: + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Configure the edge */ + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + 172 .loc 1 287 3 view .LVU26 + 173 .loc 1 287 17 is_stmt 0 view .LVU27 + 174 0054 4368 ldr r3, [r0, #4] + 175 .loc 1 287 5 view .LVU28 + 176 0056 13F0010F tst r3, #1 + ARM GAS /tmp/ccO7avbH.s page 9 + + + 177 005a 04D0 beq .L13 + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + 178 .loc 1 289 5 is_stmt 1 view .LVU29 + 179 005c 084A ldr r2, .L15+4 + 180 005e 9368 ldr r3, [r2, #8] + 181 0060 43F48033 orr r3, r3, #65536 + 182 0064 9360 str r3, [r2, #8] + 183 .L13: + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + 184 .loc 1 292 3 view .LVU30 + 185 .loc 1 292 17 is_stmt 0 view .LVU31 + 186 0066 4368 ldr r3, [r0, #4] + 187 .loc 1 292 5 view .LVU32 + 188 0068 13F0020F tst r3, #2 + 189 006c 04D0 beq .L10 + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + 190 .loc 1 294 5 is_stmt 1 view .LVU33 + 191 006e 044A ldr r2, .L15+4 + 192 0070 D368 ldr r3, [r2, #12] + 193 0072 43F48033 orr r3, r3, #65536 + 194 0076 D360 str r3, [r2, #12] + 195 .L10: + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 196 .loc 1 296 1 is_stmt 0 view .LVU34 + 197 0078 7047 bx lr + 198 .L16: + 199 007a 00BF .align 2 + 200 .L15: + 201 007c 00700040 .word 1073770496 + 202 0080 003C0140 .word 1073822720 + 203 .cfi_endproc + 204 .LFE144: + 206 .section .text.HAL_PWR_EnablePVD,"ax",%progbits + 207 .align 1 + 208 .global HAL_PWR_EnablePVD + 209 .syntax unified + 210 .thumb + 211 .thumb_func + 213 HAL_PWR_EnablePVD: + 214 .LFB145: + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief Enables the Power Voltage Detector(PVD). + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @retval None + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_EnablePVD(void) + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 215 .loc 1 303 1 is_stmt 1 view -0 + 216 .cfi_startproc + 217 @ args = 0, pretend = 0, frame = 0 + 218 @ frame_needed = 0, uses_anonymous_args = 0 + 219 @ link register save eliminated. + ARM GAS /tmp/ccO7avbH.s page 10 + + + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Enable the power voltage detector */ + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** SET_BIT(PWR->CR1, PWR_CR1_PVDE); + 220 .loc 1 305 2 view .LVU36 + 221 0000 024A ldr r2, .L18 + 222 0002 1368 ldr r3, [r2] + 223 0004 43F01003 orr r3, r3, #16 + 224 0008 1360 str r3, [r2] + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 225 .loc 1 306 1 is_stmt 0 view .LVU37 + 226 000a 7047 bx lr + 227 .L19: + 228 .align 2 + 229 .L18: + 230 000c 00700040 .word 1073770496 + 231 .cfi_endproc + 232 .LFE145: + 234 .section .text.HAL_PWR_DisablePVD,"ax",%progbits + 235 .align 1 + 236 .global HAL_PWR_DisablePVD + 237 .syntax unified + 238 .thumb + 239 .thumb_func + 241 HAL_PWR_DisablePVD: + 242 .LFB146: + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief Disables the Power Voltage Detector(PVD). + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @retval None + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_DisablePVD(void) + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 243 .loc 1 313 1 is_stmt 1 view -0 + 244 .cfi_startproc + 245 @ args = 0, pretend = 0, frame = 0 + 246 @ frame_needed = 0, uses_anonymous_args = 0 + 247 @ link register save eliminated. + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Disable the power voltage detector */ + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE); + 248 .loc 1 315 2 view .LVU39 + 249 0000 024A ldr r2, .L21 + 250 0002 1368 ldr r3, [r2] + 251 0004 23F01003 bic r3, r3, #16 + 252 0008 1360 str r3, [r2] + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 253 .loc 1 316 1 is_stmt 0 view .LVU40 + 254 000a 7047 bx lr + 255 .L22: + 256 .align 2 + 257 .L21: + 258 000c 00700040 .word 1073770496 + 259 .cfi_endproc + 260 .LFE146: + 262 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits + 263 .align 1 + 264 .global HAL_PWR_EnableWakeUpPin + 265 .syntax unified + 266 .thumb + ARM GAS /tmp/ccO7avbH.s page 11 + + + 267 .thumb_func + 269 HAL_PWR_EnableWakeUpPin: + 270 .LVL1: + 271 .LFB147: + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief Enable the WakeUp PINx functionality. + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable. + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * This parameter can be one of the following legacy values, which sets the default polari + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * detection on high level (rising edge): + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_P + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * or one of the following value where the user can explicitly states the enabled pin and + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * the chosen polarity + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @retval None + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 272 .loc 1 336 1 is_stmt 1 view -0 + 273 .cfi_startproc + 274 @ args = 0, pretend = 0, frame = 0 + 275 @ frame_needed = 0, uses_anonymous_args = 0 + 276 @ link register save eliminated. + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); + 277 .loc 1 337 3 view .LVU42 + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Enable wake-up pin */ + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity)); + 278 .loc 1 340 3 view .LVU43 + 279 0000 064A ldr r2, .L24 + 280 0002 D368 ldr r3, [r2, #12] + 281 0004 00F47C51 and r1, r0, #16128 + 282 0008 0B43 orrs r3, r3, r1 + 283 000a D360 str r3, [r2, #12] + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Specifies the Wake-Up pin polarity for the event detection + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** (rising or falling edge) */ + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06)); + 284 .loc 1 344 3 view .LVU44 + 285 000c 9368 ldr r3, [r2, #8] + 286 000e 23EA0103 bic r3, r3, r1 + 287 0012 43EA9010 orr r0, r3, r0, lsr #6 + 288 .LVL2: + 289 .loc 1 344 3 is_stmt 0 view .LVU45 + 290 0016 9060 str r0, [r2, #8] + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 291 .loc 1 345 1 view .LVU46 + 292 0018 7047 bx lr + 293 .L25: + 294 001a 00BF .align 2 + 295 .L24: + ARM GAS /tmp/ccO7avbH.s page 12 + + + 296 001c 00700040 .word 1073770496 + 297 .cfi_endproc + 298 .LFE147: + 300 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits + 301 .align 1 + 302 .global HAL_PWR_DisableWakeUpPin + 303 .syntax unified + 304 .thumb + 305 .thumb_func + 307 HAL_PWR_DisableWakeUpPin: + 308 .LVL3: + 309 .LFB148: + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief Disables the WakeUp PINx functionality. + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * This parameter can be one of the following values: + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1 + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN2 + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN3 + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN4 + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN5 + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN6 + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @retval None + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 310 .loc 1 360 1 is_stmt 1 view -0 + 311 .cfi_startproc + 312 @ args = 0, pretend = 0, frame = 0 + 313 @ frame_needed = 0, uses_anonymous_args = 0 + 314 @ link register save eliminated. + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + 315 .loc 1 361 3 view .LVU48 + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** CLEAR_BIT(PWR->CSR2, WakeUpPinx); + 316 .loc 1 363 3 view .LVU49 + 317 0000 024A ldr r2, .L27 + 318 0002 D368 ldr r3, [r2, #12] + 319 0004 23EA0003 bic r3, r3, r0 + 320 0008 D360 str r3, [r2, #12] + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 321 .loc 1 364 1 is_stmt 0 view .LVU50 + 322 000a 7047 bx lr + 323 .L28: + 324 .align 2 + 325 .L27: + 326 000c 00700040 .word 1073770496 + 327 .cfi_endproc + 328 .LFE148: + 330 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits + 331 .align 1 + 332 .global HAL_PWR_EnterSLEEPMode + 333 .syntax unified + 334 .thumb + 335 .thumb_func + 337 HAL_PWR_EnterSLEEPMode: + ARM GAS /tmp/ccO7avbH.s page 13 + + + 338 .LVL4: + 339 .LFB149: + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief Enters Sleep mode. + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @note In Sleep mode, the systick is stopped to avoid exit from this mode with + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * systick interrupt when used as time base for Timeout + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in SLEEP mode. + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * This parameter can be one of the following values: + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @note This parameter is not used for the STM32F7 family and is kept as parameter + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * just to maintain compatibility with the lower power families. + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * This parameter can be one of the following values: + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @retval None + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 340 .loc 1 387 1 is_stmt 1 view -0 + 341 .cfi_startproc + 342 @ args = 0, pretend = 0, frame = 0 + 343 @ frame_needed = 0, uses_anonymous_args = 0 + 344 @ link register save eliminated. + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Check the parameters */ + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator)); + 345 .loc 1 389 3 view .LVU52 + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + 346 .loc 1 390 3 view .LVU53 + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Prevent unused argument(s) compilation warning */ + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** UNUSED(Regulator); + 347 .loc 1 393 3 view .LVU54 + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */ + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 348 .loc 1 396 3 view .LVU55 + 349 0000 084A ldr r2, .L33 + 350 0002 1369 ldr r3, [r2, #16] + 351 0004 23F00403 bic r3, r3, #4 + 352 0008 1361 str r3, [r2, #16] + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Ensure that all instructions done before entering SLEEP mode */ + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __DSB(); + 353 .loc 1 399 3 view .LVU56 + 354 .LBB10: + 355 .LBI10: + 356 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + ARM GAS /tmp/ccO7avbH.s page 14 + + + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + ARM GAS /tmp/ccO7avbH.s page 15 + + + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccO7avbH.s page 16 + + + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccO7avbH.s page 17 + + + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + ARM GAS /tmp/ccO7avbH.s page 18 + + + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccO7avbH.s page 19 + + + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + ARM GAS /tmp/ccO7avbH.s page 20 + + + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/ccO7avbH.s page 21 + + + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + ARM GAS /tmp/ccO7avbH.s page 22 + + + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + ARM GAS /tmp/ccO7avbH.s page 23 + + + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + ARM GAS /tmp/ccO7avbH.s page 24 + + + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + ARM GAS /tmp/ccO7avbH.s page 25 + + + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + ARM GAS /tmp/ccO7avbH.s page 26 + + + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + ARM GAS /tmp/ccO7avbH.s page 27 + + + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + ARM GAS /tmp/ccO7avbH.s page 28 + + + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccO7avbH.s page 29 + + + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 357 .loc 2 877 27 view .LVU57 + 358 .LBB11: + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 359 .loc 2 879 3 view .LVU58 + 360 .syntax unified + 361 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 362 000a BFF34F8F dsb 0xF + 363 @ 0 "" 2 + 364 .thumb + 365 .syntax unified + 366 .LBE11: + 367 .LBE10: + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __ISB(); + 368 .loc 1 400 3 view .LVU59 + 369 .LBB12: + 370 .LBI12: + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 371 .loc 2 866 27 view .LVU60 + 372 .LBB13: + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 373 .loc 2 868 3 view .LVU61 + 374 .syntax unified + 375 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 376 000e BFF36F8F isb 0xF + 377 @ 0 "" 2 + 378 .thumb + 379 .syntax unified + 380 .LBE13: + 381 .LBE12: + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/ + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + 382 .loc 1 403 3 view .LVU62 + 383 .loc 1 403 5 is_stmt 0 view .LVU63 + 384 0012 0129 cmp r1, #1 + 385 0014 03D0 beq .L32 + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + ARM GAS /tmp/ccO7avbH.s page 30 + + + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Request Wait For Interrupt */ + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __WFI(); + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** else + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Request Wait For Event */ + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __SEV(); + 386 .loc 1 411 5 is_stmt 1 view .LVU64 + 387 .syntax unified + 388 @ 411 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c" 1 + 389 0016 40BF sev + 390 @ 0 "" 2 + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __WFE(); + 391 .loc 1 412 5 view .LVU65 + 392 @ 412 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c" 1 + 393 0018 20BF wfe + 394 @ 0 "" 2 + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __WFE(); + 395 .loc 1 413 5 view .LVU66 + 396 @ 413 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c" 1 + 397 001a 20BF wfe + 398 @ 0 "" 2 + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 399 .loc 1 415 1 is_stmt 0 view .LVU67 + 400 .thumb + 401 .syntax unified + 402 001c 7047 bx lr + 403 .L32: + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 404 .loc 1 406 5 is_stmt 1 view .LVU68 + 405 .syntax unified + 406 @ 406 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c" 1 + 407 001e 30BF wfi + 408 @ 0 "" 2 + 409 .thumb + 410 .syntax unified + 411 0020 7047 bx lr + 412 .L34: + 413 0022 00BF .align 2 + 414 .L33: + 415 0024 00ED00E0 .word -536810240 + 416 .cfi_endproc + 417 .LFE149: + 419 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits + 420 .align 1 + 421 .global HAL_PWR_EnterSTOPMode + 422 .syntax unified + 423 .thumb + 424 .thumb_func + 426 HAL_PWR_EnterSTOPMode: + 427 .LVL5: + 428 .LFB150: + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief Enters Stop mode. + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode. + ARM GAS /tmp/ccO7avbH.s page 31 + + + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * the HSI RC oscillator is selected as system clock. + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode, an additional + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * startup delay is incurred when waking up from Stop mode. + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * By keeping the internal regulator ON during Stop mode, the consumption + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * is higher although the startup time is reduced. + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in Stop mode. + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * This parameter can be one of the following values: + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * This parameter can be one of the following values: + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @retval None + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 429 .loc 1 437 1 view -0 + 430 .cfi_startproc + 431 @ args = 0, pretend = 0, frame = 0 + 432 @ frame_needed = 0, uses_anonymous_args = 0 + 433 @ link register save eliminated. + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** uint32_t tmpreg = 0; + 434 .loc 1 438 3 view .LVU70 + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Check the parameters */ + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator)); + 435 .loc 1 441 3 view .LVU71 + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + 436 .loc 1 442 3 view .LVU72 + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Select the regulator state in Stop mode ---------------------------------*/ + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** tmpreg = PWR->CR1; + 437 .loc 1 445 3 view .LVU73 + 438 .loc 1 445 10 is_stmt 0 view .LVU74 + 439 0000 0D4A ldr r2, .L39 + 440 0002 1368 ldr r3, [r2] + 441 .LVL6: + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Clear PDDS and LPDS bits */ + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS); + 442 .loc 1 447 3 is_stmt 1 view .LVU75 + 443 .loc 1 447 10 is_stmt 0 view .LVU76 + 444 0004 23F00303 bic r3, r3, #3 + 445 .LVL7: + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */ + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** tmpreg |= Regulator; + 446 .loc 1 450 3 is_stmt 1 view .LVU77 + 447 .loc 1 450 10 is_stmt 0 view .LVU78 + 448 0008 0343 orrs r3, r3, r0 + 449 .LVL8: + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Store the new value */ + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** PWR->CR1 = tmpreg; + 450 .loc 1 453 3 is_stmt 1 view .LVU79 + 451 .loc 1 453 12 is_stmt 0 view .LVU80 + ARM GAS /tmp/ccO7avbH.s page 32 + + + 452 000a 1360 str r3, [r2] + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + 453 .loc 1 456 3 is_stmt 1 view .LVU81 + 454 .loc 1 456 6 is_stmt 0 view .LVU82 + 455 000c 0B4A ldr r2, .L39+4 + 456 000e 1369 ldr r3, [r2, #16] + 457 .LVL9: + 458 .loc 1 456 12 view .LVU83 + 459 0010 43F00403 orr r3, r3, #4 + 460 0014 1361 str r3, [r2, #16] + 461 .LVL10: + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Ensure that all instructions done before entering STOP mode */ + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __DSB(); + 462 .loc 1 459 3 is_stmt 1 view .LVU84 + 463 .LBB14: + 464 .LBI14: + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 465 .loc 2 877 27 view .LVU85 + 466 .LBB15: + 467 .loc 2 879 3 view .LVU86 + 468 .syntax unified + 469 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 470 0016 BFF34F8F dsb 0xF + 471 @ 0 "" 2 + 472 .thumb + 473 .syntax unified + 474 .LBE15: + 475 .LBE14: + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __ISB(); + 476 .loc 1 460 3 view .LVU87 + 477 .LBB16: + 478 .LBI16: + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 479 .loc 2 866 27 view .LVU88 + 480 .LBB17: + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 481 .loc 2 868 3 view .LVU89 + 482 .syntax unified + 483 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 484 001a BFF36F8F isb 0xF + 485 @ 0 "" 2 + 486 .thumb + 487 .syntax unified + 488 .LBE17: + 489 .LBE16: + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Select Stop mode entry --------------------------------------------------*/ + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** if(STOPEntry == PWR_STOPENTRY_WFI) + 490 .loc 1 463 3 view .LVU90 + 491 .loc 1 463 5 is_stmt 0 view .LVU91 + 492 001e 0129 cmp r1, #1 + 493 0020 08D0 beq .L38 + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Request Wait For Interrupt */ + ARM GAS /tmp/ccO7avbH.s page 33 + + + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __WFI(); + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** else + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Request Wait For Event */ + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __SEV(); + 494 .loc 1 471 5 is_stmt 1 view .LVU92 + 495 .syntax unified + 496 @ 471 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c" 1 + 497 0022 40BF sev + 498 @ 0 "" 2 + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __WFE(); + 499 .loc 1 472 5 view .LVU93 + 500 @ 472 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c" 1 + 501 0024 20BF wfe + 502 @ 0 "" 2 + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __WFE(); + 503 .loc 1 473 5 view .LVU94 + 504 @ 473 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c" 1 + 505 0026 20BF wfe + 506 @ 0 "" 2 + 507 .thumb + 508 .syntax unified + 509 .L37: + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Reset SLEEPDEEP bit of Cortex System Control Register */ + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + 510 .loc 1 476 3 view .LVU95 + 511 .loc 1 476 6 is_stmt 0 view .LVU96 + 512 0028 044A ldr r2, .L39+4 + 513 002a 1369 ldr r3, [r2, #16] + 514 .loc 1 476 12 view .LVU97 + 515 002c 23F00403 bic r3, r3, #4 + 516 0030 1361 str r3, [r2, #16] + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 517 .loc 1 477 1 view .LVU98 + 518 0032 7047 bx lr + 519 .L38: + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 520 .loc 1 466 5 is_stmt 1 view .LVU99 + 521 .syntax unified + 522 @ 466 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c" 1 + 523 0034 30BF wfi + 524 @ 0 "" 2 + 525 .thumb + 526 .syntax unified + 527 0036 F7E7 b .L37 + 528 .L40: + 529 .align 2 + 530 .L39: + 531 0038 00700040 .word 1073770496 + 532 003c 00ED00E0 .word -536810240 + 533 .cfi_endproc + 534 .LFE150: + 536 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits + 537 .align 1 + 538 .global HAL_PWR_EnterSTANDBYMode + ARM GAS /tmp/ccO7avbH.s page 34 + + + 539 .syntax unified + 540 .thumb + 541 .thumb_func + 543 HAL_PWR_EnterSTANDBYMode: + 544 .LFB151: + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief Enters Standby mode. + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @note In Standby mode, all I/O pins are high impedance except for: + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * - Reset pad (still available) + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * Alarm out, or RTC clock calibration out. + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * - WKUP pins if enabled. + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @retval None + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void) + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 545 .loc 1 490 1 view -0 + 546 .cfi_startproc + 547 @ args = 0, pretend = 0, frame = 0 + 548 @ frame_needed = 0, uses_anonymous_args = 0 + 549 @ link register save eliminated. + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Select Standby mode */ + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** PWR->CR1 |= PWR_CR1_PDDS; + 550 .loc 1 492 3 view .LVU101 + 551 .loc 1 492 6 is_stmt 0 view .LVU102 + 552 0000 054A ldr r2, .L42 + 553 0002 1368 ldr r3, [r2] + 554 .loc 1 492 12 view .LVU103 + 555 0004 43F00203 orr r3, r3, #2 + 556 0008 1360 str r3, [r2] + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + 557 .loc 1 495 3 is_stmt 1 view .LVU104 + 558 .loc 1 495 6 is_stmt 0 view .LVU105 + 559 000a 044A ldr r2, .L42+4 + 560 000c 1369 ldr r3, [r2, #16] + 561 .loc 1 495 12 view .LVU106 + 562 000e 43F00403 orr r3, r3, #4 + 563 0012 1361 str r3, [r2, #16] + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */ + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** #if defined ( __CC_ARM) + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __force_stores(); + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** #endif + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Request Wait For Interrupt */ + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __WFI(); + 564 .loc 1 502 3 is_stmt 1 view .LVU107 + 565 .syntax unified + 566 @ 502 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c" 1 + 567 0014 30BF wfi + 568 @ 0 "" 2 + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 569 .loc 1 503 1 is_stmt 0 view .LVU108 + 570 .thumb + ARM GAS /tmp/ccO7avbH.s page 35 + + + 571 .syntax unified + 572 0016 7047 bx lr + 573 .L43: + 574 .align 2 + 575 .L42: + 576 0018 00700040 .word 1073770496 + 577 001c 00ED00E0 .word -536810240 + 578 .cfi_endproc + 579 .LFE151: + 581 .section .text.HAL_PWR_PVDCallback,"ax",%progbits + 582 .align 1 + 583 .weak HAL_PWR_PVDCallback + 584 .syntax unified + 585 .thumb + 586 .thumb_func + 588 HAL_PWR_PVDCallback: + 589 .LFB153: + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief This function handles the PWR PVD interrupt request. + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @note This API should be called under the PVD_IRQHandler(). + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @retval None + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_PVD_IRQHandler(void) + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Check PWR Exti flag */ + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* PWR PVD interrupt user callback */ + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** HAL_PWR_PVDCallback(); + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Clear PWR Exti pending bit */ + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief PWR PVD interrupt callback + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @retval None + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** __weak void HAL_PWR_PVDCallback(void) + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 590 .loc 1 528 1 is_stmt 1 view -0 + 591 .cfi_startproc + 592 @ args = 0, pretend = 0, frame = 0 + 593 @ frame_needed = 0, uses_anonymous_args = 0 + 594 @ link register save eliminated. + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** the HAL_PWR_PVDCallback could be implemented in the user file + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 595 .loc 1 532 1 view .LVU110 + 596 0000 7047 bx lr + 597 .cfi_endproc + 598 .LFE153: + 600 .section .text.HAL_PWR_PVD_IRQHandler,"ax",%progbits + 601 .align 1 + ARM GAS /tmp/ccO7avbH.s page 36 + + + 602 .global HAL_PWR_PVD_IRQHandler + 603 .syntax unified + 604 .thumb + 605 .thumb_func + 607 HAL_PWR_PVD_IRQHandler: + 608 .LFB152: + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Check PWR Exti flag */ + 609 .loc 1 511 1 view -0 + 610 .cfi_startproc + 611 @ args = 0, pretend = 0, frame = 0 + 612 @ frame_needed = 0, uses_anonymous_args = 0 + 613 0000 08B5 push {r3, lr} + 614 .LCFI0: + 615 .cfi_def_cfa_offset 8 + 616 .cfi_offset 3, -8 + 617 .cfi_offset 14, -4 + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 618 .loc 1 513 3 view .LVU112 + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 619 .loc 1 513 6 is_stmt 0 view .LVU113 + 620 0002 064B ldr r3, .L49 + 621 0004 5B69 ldr r3, [r3, #20] + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 622 .loc 1 513 5 view .LVU114 + 623 0006 13F4803F tst r3, #65536 + 624 000a 00D1 bne .L48 + 625 .L45: + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 626 .loc 1 521 1 view .LVU115 + 627 000c 08BD pop {r3, pc} + 628 .L48: + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 629 .loc 1 516 5 is_stmt 1 view .LVU116 + 630 000e FFF7FEFF bl HAL_PWR_PVDCallback + 631 .LVL11: + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 632 .loc 1 519 5 view .LVU117 + 633 0012 024B ldr r3, .L49 + 634 0014 4FF48032 mov r2, #65536 + 635 0018 5A61 str r2, [r3, #20] + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 636 .loc 1 521 1 is_stmt 0 view .LVU118 + 637 001a F7E7 b .L45 + 638 .L50: + 639 .align 2 + 640 .L49: + 641 001c 003C0140 .word 1073822720 + 642 .cfi_endproc + 643 .LFE152: + 645 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits + 646 .align 1 + 647 .global HAL_PWR_EnableSleepOnExit + 648 .syntax unified + 649 .thumb + 650 .thumb_func + 652 HAL_PWR_EnableSleepOnExit: + 653 .LFB154: + ARM GAS /tmp/ccO7avbH.s page 37 + + + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run only on + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * interruptions handling. + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @retval None + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void) + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 654 .loc 1 543 1 is_stmt 1 view -0 + 655 .cfi_startproc + 656 @ args = 0, pretend = 0, frame = 0 + 657 @ frame_needed = 0, uses_anonymous_args = 0 + 658 @ link register save eliminated. + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */ + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); + 659 .loc 1 545 3 view .LVU120 + 660 0000 024A ldr r2, .L52 + 661 0002 1369 ldr r3, [r2, #16] + 662 0004 43F00203 orr r3, r3, #2 + 663 0008 1361 str r3, [r2, #16] + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 664 .loc 1 546 1 is_stmt 0 view .LVU121 + 665 000a 7047 bx lr + 666 .L53: + 667 .align 2 + 668 .L52: + 669 000c 00ED00E0 .word -536810240 + 670 .cfi_endproc + 671 .LFE154: + 673 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits + 674 .align 1 + 675 .global HAL_PWR_DisableSleepOnExit + 676 .syntax unified + 677 .thumb + 678 .thumb_func + 680 HAL_PWR_DisableSleepOnExit: + 681 .LFB155: + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @retval None + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void) + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 682 .loc 1 555 1 is_stmt 1 view -0 + 683 .cfi_startproc + 684 @ args = 0, pretend = 0, frame = 0 + 685 @ frame_needed = 0, uses_anonymous_args = 0 + 686 @ link register save eliminated. + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); + 687 .loc 1 557 3 view .LVU123 + ARM GAS /tmp/ccO7avbH.s page 38 + + + 688 0000 024A ldr r2, .L55 + 689 0002 1369 ldr r3, [r2, #16] + 690 0004 23F00203 bic r3, r3, #2 + 691 0008 1361 str r3, [r2, #16] + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 692 .loc 1 558 1 is_stmt 0 view .LVU124 + 693 000a 7047 bx lr + 694 .L56: + 695 .align 2 + 696 .L55: + 697 000c 00ED00E0 .word -536810240 + 698 .cfi_endproc + 699 .LFE155: + 701 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits + 702 .align 1 + 703 .global HAL_PWR_EnableSEVOnPend + 704 .syntax unified + 705 .thumb + 706 .thumb_func + 708 HAL_PWR_EnableSEVOnPend: + 709 .LFB156: + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief Enables CORTEX M4 SEVONPEND bit. + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @retval None + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void) + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 710 .loc 1 567 1 is_stmt 1 view -0 + 711 .cfi_startproc + 712 @ args = 0, pretend = 0, frame = 0 + 713 @ frame_needed = 0, uses_anonymous_args = 0 + 714 @ link register save eliminated. + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */ + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); + 715 .loc 1 569 3 view .LVU126 + 716 0000 024A ldr r2, .L58 + 717 0002 1369 ldr r3, [r2, #16] + 718 0004 43F01003 orr r3, r3, #16 + 719 0008 1361 str r3, [r2, #16] + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 720 .loc 1 570 1 is_stmt 0 view .LVU127 + 721 000a 7047 bx lr + 722 .L59: + 723 .align 2 + 724 .L58: + 725 000c 00ED00E0 .word -536810240 + 726 .cfi_endproc + 727 .LFE156: + 729 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits + 730 .align 1 + 731 .global HAL_PWR_DisableSEVOnPend + 732 .syntax unified + 733 .thumb + 734 .thumb_func + ARM GAS /tmp/ccO7avbH.s page 39 + + + 736 HAL_PWR_DisableSEVOnPend: + 737 .LFB157: + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /** + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @brief Disables CORTEX M4 SEVONPEND bit. + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** * @retval None + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** */ + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void) + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** { + 738 .loc 1 579 1 is_stmt 1 view -0 + 739 .cfi_startproc + 740 @ args = 0, pretend = 0, frame = 0 + 741 @ frame_needed = 0, uses_anonymous_args = 0 + 742 @ link register save eliminated. + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */ + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); + 743 .loc 1 581 3 view .LVU129 + 744 0000 024A ldr r2, .L61 + 745 0002 1369 ldr r3, [r2, #16] + 746 0004 23F01003 bic r3, r3, #16 + 747 0008 1361 str r3, [r2, #16] + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c **** } + 748 .loc 1 582 1 is_stmt 0 view .LVU130 + 749 000a 7047 bx lr + 750 .L62: + 751 .align 2 + 752 .L61: + 753 000c 00ED00E0 .word -536810240 + 754 .cfi_endproc + 755 .LFE157: + 757 .text + 758 .Letext0: + 759 .file 3 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 760 .file 4 "Drivers/CMSIS/Include/core_cm7.h" + 761 .file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 762 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h" + 763 .file 7 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + ARM GAS /tmp/ccO7avbH.s page 40 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_pwr.c + /tmp/ccO7avbH.s:20 .text.HAL_PWR_DeInit:00000000 $t + /tmp/ccO7avbH.s:26 .text.HAL_PWR_DeInit:00000000 HAL_PWR_DeInit + /tmp/ccO7avbH.s:47 .text.HAL_PWR_DeInit:00000014 $d + /tmp/ccO7avbH.s:52 .text.HAL_PWR_EnableBkUpAccess:00000000 $t + /tmp/ccO7avbH.s:58 .text.HAL_PWR_EnableBkUpAccess:00000000 HAL_PWR_EnableBkUpAccess + /tmp/ccO7avbH.s:75 .text.HAL_PWR_EnableBkUpAccess:0000000c $d + /tmp/ccO7avbH.s:80 .text.HAL_PWR_DisableBkUpAccess:00000000 $t + /tmp/ccO7avbH.s:86 .text.HAL_PWR_DisableBkUpAccess:00000000 HAL_PWR_DisableBkUpAccess + /tmp/ccO7avbH.s:103 .text.HAL_PWR_DisableBkUpAccess:0000000c $d + /tmp/ccO7avbH.s:108 .text.HAL_PWR_ConfigPVD:00000000 $t + /tmp/ccO7avbH.s:114 .text.HAL_PWR_ConfigPVD:00000000 HAL_PWR_ConfigPVD + /tmp/ccO7avbH.s:201 .text.HAL_PWR_ConfigPVD:0000007c $d + /tmp/ccO7avbH.s:207 .text.HAL_PWR_EnablePVD:00000000 $t + /tmp/ccO7avbH.s:213 .text.HAL_PWR_EnablePVD:00000000 HAL_PWR_EnablePVD + /tmp/ccO7avbH.s:230 .text.HAL_PWR_EnablePVD:0000000c $d + /tmp/ccO7avbH.s:235 .text.HAL_PWR_DisablePVD:00000000 $t + /tmp/ccO7avbH.s:241 .text.HAL_PWR_DisablePVD:00000000 HAL_PWR_DisablePVD + /tmp/ccO7avbH.s:258 .text.HAL_PWR_DisablePVD:0000000c $d + /tmp/ccO7avbH.s:263 .text.HAL_PWR_EnableWakeUpPin:00000000 $t + /tmp/ccO7avbH.s:269 .text.HAL_PWR_EnableWakeUpPin:00000000 HAL_PWR_EnableWakeUpPin + /tmp/ccO7avbH.s:296 .text.HAL_PWR_EnableWakeUpPin:0000001c $d + /tmp/ccO7avbH.s:301 .text.HAL_PWR_DisableWakeUpPin:00000000 $t + /tmp/ccO7avbH.s:307 .text.HAL_PWR_DisableWakeUpPin:00000000 HAL_PWR_DisableWakeUpPin + /tmp/ccO7avbH.s:326 .text.HAL_PWR_DisableWakeUpPin:0000000c $d + /tmp/ccO7avbH.s:331 .text.HAL_PWR_EnterSLEEPMode:00000000 $t + /tmp/ccO7avbH.s:337 .text.HAL_PWR_EnterSLEEPMode:00000000 HAL_PWR_EnterSLEEPMode + /tmp/ccO7avbH.s:415 .text.HAL_PWR_EnterSLEEPMode:00000024 $d + /tmp/ccO7avbH.s:420 .text.HAL_PWR_EnterSTOPMode:00000000 $t + /tmp/ccO7avbH.s:426 .text.HAL_PWR_EnterSTOPMode:00000000 HAL_PWR_EnterSTOPMode + /tmp/ccO7avbH.s:531 .text.HAL_PWR_EnterSTOPMode:00000038 $d + /tmp/ccO7avbH.s:537 .text.HAL_PWR_EnterSTANDBYMode:00000000 $t + /tmp/ccO7avbH.s:543 .text.HAL_PWR_EnterSTANDBYMode:00000000 HAL_PWR_EnterSTANDBYMode + /tmp/ccO7avbH.s:576 .text.HAL_PWR_EnterSTANDBYMode:00000018 $d + /tmp/ccO7avbH.s:582 .text.HAL_PWR_PVDCallback:00000000 $t + /tmp/ccO7avbH.s:588 .text.HAL_PWR_PVDCallback:00000000 HAL_PWR_PVDCallback + /tmp/ccO7avbH.s:601 .text.HAL_PWR_PVD_IRQHandler:00000000 $t + /tmp/ccO7avbH.s:607 .text.HAL_PWR_PVD_IRQHandler:00000000 HAL_PWR_PVD_IRQHandler + /tmp/ccO7avbH.s:641 .text.HAL_PWR_PVD_IRQHandler:0000001c $d + /tmp/ccO7avbH.s:646 .text.HAL_PWR_EnableSleepOnExit:00000000 $t + /tmp/ccO7avbH.s:652 .text.HAL_PWR_EnableSleepOnExit:00000000 HAL_PWR_EnableSleepOnExit + /tmp/ccO7avbH.s:669 .text.HAL_PWR_EnableSleepOnExit:0000000c $d + /tmp/ccO7avbH.s:674 .text.HAL_PWR_DisableSleepOnExit:00000000 $t + /tmp/ccO7avbH.s:680 .text.HAL_PWR_DisableSleepOnExit:00000000 HAL_PWR_DisableSleepOnExit + /tmp/ccO7avbH.s:697 .text.HAL_PWR_DisableSleepOnExit:0000000c $d + /tmp/ccO7avbH.s:702 .text.HAL_PWR_EnableSEVOnPend:00000000 $t + /tmp/ccO7avbH.s:708 .text.HAL_PWR_EnableSEVOnPend:00000000 HAL_PWR_EnableSEVOnPend + /tmp/ccO7avbH.s:725 .text.HAL_PWR_EnableSEVOnPend:0000000c $d + /tmp/ccO7avbH.s:730 .text.HAL_PWR_DisableSEVOnPend:00000000 $t + /tmp/ccO7avbH.s:736 .text.HAL_PWR_DisableSEVOnPend:00000000 HAL_PWR_DisableSEVOnPend + /tmp/ccO7avbH.s:753 .text.HAL_PWR_DisableSEVOnPend:0000000c $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32f7xx_hal_pwr.o b/build/stm32f7xx_hal_pwr.o new file mode 100644 index 0000000000000000000000000000000000000000..ba000d53000221e0987df28b80a9cd992903d417 GIT binary patch literal 13612 zcmd5?d6ZmLoxZQ$d)2SgOS-$VFIY*3qyzSvkOX8&cXcOSNw+DwIve10S9e!0(3{oO z5N3kLkQsxb#DOE~aBw-!8IC&Wco=aV)T0Mf6a;373?c}MAZmbMSQO^_?)%+ZUOMWZ zbCas?{+9b&?)L7x)$i@-+GbgnGR0DLDo-i(y#_6DH)^O;>mhe`F1xbr#G#&L1Iw;l zt#Nw0+7j9t+7TIzojf!X=?6WnG+kRjp9OjCi6?Dqv@90sU$OJD(bXppwOrP}Oyjct zPiXu^|6>{->yM2_P9D0%d9d2IyCI@E3Y>}^NqX9lB$|CwEP%PRM|x_7SLg|QYQ~yS{8e_|K`!!=Pf(-{IRNIIU6C!YoAxPwhEix zj>uT;3CE74?s<9FP4~P!b(6K;esJqOQT&_U-h>Z)|4uzwp>wxw8=04(O)SvHlQvGy z9$TM!R>zI@F8km_2ys)xZ>_B}FUa9XdH)&SdHERoO#RgR)?26Ed@Hnb7kfAbJAUqH z2^%SBqYcIju@}=Z_C=9APam77R7lSQ$9kWmRQXdNZg4fH=qu!v)PoUnO1_V|6tcn} zAQf_Nx5;#ulJeYx06T-`cEge()SV>xmiLd;3YDyYEBkfS?Tt&1Qk=n;`yT2zB`e`R z?6_l-Syl3dkaMq9`UEt+9n|}QRdYSHYL#~ZY&bu(YILhw$6HMLM~3#iOGw{u=jv?Go>1p!1-SukpS~dp|XFowq6s`XNKV-Rq$I zVM8~0my&+O&>Ow|=q~5K4ZX$tJJSDS=nK8~(BGq0jfXfwwOhTOW@Htk(Jo&tg3PYt>w+>3(kw<&Rr6t(wky?d-pwoAw7vW4*}#2}2+BZe+Z_ z@M*jDkmdas19;L8(5^jVdCTeHDZ@Bwd2Mv@ORMHmxUg$)w7esX@oA%R$nmh7h9}MF+jyH@PoD+ue zg5w=$kG*IZCmio3HhIY~PCDL|^zyP*^KPB~tB$vWO->q(W3G1ZUmYczVwFm7`_tW@Q^Y8an#y)3=FX43zx>uqPGuN#d!Ts5x`Z8)*ZnoudjxT8Mr zdem*GYNn;!muZI#E#WfM5?i?yG)RV)Y&H@{x$7t)V;+|2W&SNL-FgQhEe znmdiAT~+>R=J|$Ye-w7KvD=N%QWZPu_nB?xcA)DSSs@x|-rTugp>uFZ*FO8n^ z)>7?hLpzYSDEApdd)~Q}|H{zis{Bs+{dLG*2x}F$xW5aP-dLjTD)$dYO?h!ff5Om? zS4uN48rmz3#S!jHhA#KIVaW2l;g6{=m~J%!ok zo-*>NcbrkaYUnjy1KYnAs{Sx~BUD@Gy+(hp8+ntL1>b$c&>Owu)c=#Aw|HAf|JnGv z&>N@zn?}CXyO;8}4Bf7G6j#~euhY}d1>&h^xoo@7=NSQF!S?_e7ZE2M1PkWI;(dYcb?Hd;BjuaWxiZ*nvHZ& zZW!1!|CNji!@#D=`R!I31~$!4k}=;fj#;YwHI8DnZBM{@Wr;Neg_7H>yD(qo{}arq zs$@qmPI4j7`4Y%#FWgxAG=wz?$imI#{@|*b>tQCmQAkJGmFWENrqDN_8nO06*J=xe zp#y{XgsxLo#A<|&wdpi=3nH=3IgR}!y5BnMGXT3CbHPL5W@T12hq3bfdGk@Y-n-X-j<&?I|VsZxvgFt)p_vzfM)Sp4@sxrHYV z>(V7(Cw#@yy|5PbC_YQC!ydYb0)8!H+q++#RmAdaNq!hM_g8tn6Yi@$6cJIekIdJIc;4i%0PAI8PDWwHm^rhe=fu zvC3TNx#yQzQ1B}JW+3B{Ey$!449}PQjCqz7k5IL26>K$@;W#X=bQ^5ouvnJ2Sm{_7 zmzBYq9}HX0uY;2nXjz4d$4a%dL9|q;ktlTVj3UyYE-Bafz{$GuYOBWDI`7uDa-|kD zSf@$CkkHJ+8xC8l+G<91(Hv?tK()o#RM}NJ{t&z^*;vR3-`$3;UAj^=M|!NUww2NO zzOw!9Uc|kusHv~Hd_D$&oxLI#H1a44dSye-!MgG&?C65Q#cRfO`c)(9*SYF-q0BFs zIM8VNB#|q@Qb__AD-H_!wF%Y2q8GDD5Tf|ZQ!m@EsP(6sPATrLy4;3u-v!P3g%gm4 z)>#Z5@yQ%*_|X8Ln*qyK{q6f^)ua*?zG;6Z6gBn#DIPw`ZM6wYJ7m34S)p)~fI7xP zS?!sztJ9g8#$<2zhL&xc4;<+0Z0+jvxsA!ppfU=v?qodK7@r&*pB+l8#@U%n zj-iOoi$+i!veFfeyc zH#mxEnP>Z2%EgIV&jb5uWw~}_ziWkehOnzydC3V%7C^8+Aow!`p}7Rthu9*r@S6QQ zcXqqgVas)+;fr1SiZj$N&-1PDWub79`#WK5PA^|Qli&fmk1V`0yw9~(g`6U5&uZCR zK_9mLpch{5gxux!6Pk1^`_l&-G~*$|_~O9^*9}|YO{-R+Q&yvHUlR?vMQ-k*a%5p- zp*s)R+uzOoH1TcH11Y<8x;ceC14n?-mPM z6K&01iH>*nsMgN5BrZbQWAW}ituZw|H8~RH&CA}@Rq5T+iLuE8K2Hl~Cuhb+CeuS& zBi0pf?@_VD?s&UO>}l^xU!5LT+y@eSd-~ePW>N#=>14;AU6YCQ* zrZNa(XKdScyl6?KMJ4yfJ9-oi_Fg-kZch)Z?8I~?J(Ba&F_}$gl3g7giS8-vFvzQ= zCy9%Vzql=6hiW{15f288_O`yWy=}iX8_25ds@>DAgM;ar8I|bjV#q2Ui??=l?N)8u zTG6N5@YaBY{ZLF}^if~D=hDv9vWZjwds^qyuGh|8^pRNB+Kt4Ga@PGz#uBIC$1 z-jb9=nOnSvbB1Zgdt=?GcXu;!JrEd@%(Z$X{2A8Q*Pd+4g#4qF{W3F~yuC^&x+nlRy z;g}{crnxTGlRw$Xcg<}aK7Rzb3ZdBzP2{=3&lB?u^I$iIlcUM$E{k}B&X$T~O-JiT@PFuF$5+_v#}L)DLUPsYdz_a+3{3% zDx;Fg7&e8rc1}rufw14VpxZeG{S}hz#a&M0=+s2IaX3AcYV3|DdK-IELt|5k(W&gz z7SqXr#e{6;SBp~HW3daObd{OkgmMzlCmXM#B`(zRFsMs=K+PzFUPWO1eu!^Sl~ofwj+nSp1lL5kmaZs-zpU2oLNZXSZm%%e74PlZb7kevRzm}<8@k(S3dvzTNBlADICyu z1LKP$aY3tI~jeX+R&> zDFwyGJ7sbI%+vZSayodaE+{r`*^Bkd0`|=-vERtXj4IYI*ZOO6HVbDQ`@bTfU!nE4 z#lF(62SE@1u$N0Dtt;YO%o6x?z zO5Zh5?#ExF5+e8Mh`OqXUZ8lto!7^B&2^|>lT~Yma?e9~sGFy`|9C7ovKWCp=I4;) zk4;85e_}P9f^)ZF1s}wQFRJ+`v=Ic}Y>L_D92?-C{>D;x+&0SK6~2fVwjW`#;9z4U zbDVjMNE+o%gobaLx!JDL5neLBY=mep&Flf)5Gem0ibEBgp43<7*LY6YLQj5X=Z37W`+y z&j@~5@VkN!3I0+rgvCKW5y3Tr=Lv2T^(UL*K^!CM9YP4I5Pdj%gAd{*$3 zU_a-6{AD;r~$ZXM(>X!tQf|FA>r1l;9hJ9*%M3R|r-Mt{@_gvxzH}S}(Xs z_#J}#g#RwVl;EV`jNmnbhl#NJK_Y%fyh-pj;s3kfSBQ(1`nuq~!he{EydD*NLio=T zafJD;;48v^lZZ`}zv&RmiSWOWh)s8?;9B8dB-la35i~BC6#nHz^j)9enDF0C#9Epa ze2?&N5X82r#~sU9qu$@^{AW4m1Ez`|hjRp51UCsHWG!zM+($(JTp>6pI3kE;r9zv< zKH}mTh;c`W$O|rY{!K*m3m!ST|F#lgx08tRNf0sq+Fw+ue$utrSBVIEnh0YDh*$@Q zh*&2_iC9O+h*)PV>>r&!&?Aj6-4DPj(ufN~s8Pp@@!@%y;}j(#&NYH{L@4X$AFzou z;-)L2&Ij@15vlXoN<<#*f}O;uQeA=xBJ%1L)cGPm-M_$o^5JwyaFmFA#|5W}$U7^j z`vdtOBn>=7L~ut0JNP_9KlBkj^dAxVe}ss9pCBUNQ^W=6A3leW*V~E6OF!q34}YR& z9uXUe_}hqxcQ+C7UPnZnA0;9_{y_-ixsQl=U|NMPmid8r)(DNJIxeVax$aNI*DiD? z5pnhkt@{h{4hcOD{-$9Hjb(hdzCD!6^a)rK+ zh&&$=`Z%#psTYJkK}6nv5}F5L=3h>P|0*K-VTI69;zlSp%v?K>O$`9E86QVY4R>x? z)xaAv)i8j|?FKR$az{G@F4;9=;oJXLg#j@EBe!lyh~#VZ2yw&evyD5CggM_uS3% zVum-A9+(~J8=D-S!Yt7B)WAR{eYMiT`<(Hq!9p^XNllKVF;(*IPv?w}O{R@S%r(_8 zI5jbm#`ShVtKm#)0!pnt-3_U1HZwLbn}ylGz3^=tQ(V7auob6zVZk<{%PM?R58Hz- zK|RV?*5Tvf^VjsaKL`CT0nZdiDy_gmJ?_g@MhR&2`cW^``0WhXtHkx?ryw`Q_-zl^dmQ$TL5cRbrx<&e2khMmd(<<<*yDS7QGDys z&k)ic9{)Le69Ib{V=x{!n+^1gy|IA3gE&ARg`D;lr|Q0qSAD&Tq>2 zITFy@finvCI#Z0^M*{I>p;t$t6#8ZPP#``BXA+Yyjx)LVZigPyo7Ro+bsIXD?*OJ4 z(?qD|%7f60VqP)ER($9eU8VcDpu5zGC~O)dkee!wY`HxgRkZ*c_MHU|jNbnNJr^a~ literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_hal_pwr_ex.d b/build/stm32f7xx_hal_pwr_ex.d new file mode 100644 index 0000000..67f3677 --- /dev/null +++ b/build/stm32f7xx_hal_pwr_ex.d @@ -0,0 +1,68 @@ +build/stm32f7xx_hal_pwr_ex.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/build/stm32f7xx_hal_pwr_ex.lst b/build/stm32f7xx_hal_pwr_ex.lst new file mode 100644 index 0000000..acebe03 --- /dev/null +++ b/build/stm32f7xx_hal_pwr_ex.lst @@ -0,0 +1,1648 @@ +ARM GAS /tmp/ccuaURzG.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_hal_pwr_ex.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c" + 19 .section .text.HAL_PWREx_EnableBkUpReg,"ax",%progbits + 20 .align 1 + 21 .global HAL_PWREx_EnableBkUpReg + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 HAL_PWREx_EnableBkUpReg: + 27 .LFB141: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @file stm32f7xx_hal_pwr_ex.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @brief Extended PWR HAL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * functionalities of PWR extension peripheral: + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * + Peripheral Extended features functions + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** ****************************************************************************** + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @attention + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * Copyright (c) 2017 STMicroelectronics. + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * All rights reserved. + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * This software is licensed under terms that can be found in the LICENSE file + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * in the root directory of this software component. + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** ****************************************************************************** + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Includes ------------------------------------------------------------------*/ + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** #include "stm32f7xx_hal.h" + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** @addtogroup STM32F7xx_HAL_Driver + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @{ + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** @defgroup PWREx PWREx + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @brief PWR HAL module driver + ARM GAS /tmp/ccuaURzG.s page 2 + + + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @{ + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** #ifdef HAL_PWR_MODULE_ENABLED + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Private define ------------------------------------------------------------*/ + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** @addtogroup PWREx_Private_Constants + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @{ + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** #define PWR_OVERDRIVE_TIMEOUT_VALUE 1000 + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** #define PWR_UDERDRIVE_TIMEOUT_VALUE 1000 + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** #define PWR_BKPREG_TIMEOUT_VALUE 1000 + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** #define PWR_VOSRDY_TIMEOUT_VALUE 1000 + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @} + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Private macro -------------------------------------------------------------*/ + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Private variables ---------------------------------------------------------*/ + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Private functions ---------------------------------------------------------*/ + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions PWREx Exported Functions + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @{ + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @brief Peripheral Extended features functions + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** @verbatim + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** =============================================================================== + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** ##### Peripheral extended features functions ##### + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** =============================================================================== + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** *** Main and Backup Regulators configuration *** + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** ================================================ + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** [..] + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** retained even in Standby or VBAT mode when the low power backup regulator + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** is enabled. It can be considered as an internal EEPROM when VBAT is + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** always present. You can use the HAL_PWREx_EnableBkUpReg() function to + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** enable the low power backup regulator. + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** (+) When the backup domain is supplied by VDD (analog switch connected to VDD) + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** the backup SRAM is powered from VDD which replaces the VBAT power supply to + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** save battery life. + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** (+) The backup SRAM is not mass erased by a tamper event. It is read + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** protected to prevent confidential data, such as cryptographic private + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** key, from being accessed. The backup SRAM can be erased only through + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** the Flash interface when a protection level change from level 1 to + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** level 0 is requested. + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** -@- Refer to the description of Read protection (RDP) in the Flash + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** programming manual. + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + ARM GAS /tmp/ccuaURzG.s page 3 + + + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** (+) The main internal regulator can be configured to have a tradeoff between + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** performance and power consumption when the device does not operate at + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** macro which configure VOS bit in PWR_CR register + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** Refer to the product datasheets for more details. + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** *** FLASH Power Down configuration **** + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** ======================================= + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** [..] + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** (+) By setting the FPDS bit in the PWR_CR register by using the + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** down mode when the device enters Stop mode. When the Flash memory + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** is in power down mode, an additional startup delay is incurred when + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** waking up from Stop mode. + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** *** Over-Drive and Under-Drive configuration **** + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** ================================================= + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** [..] + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** (+) In Run mode: the main regulator has 2 operating modes available: + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** (++) Normal mode: The CPU and core logic operate at maximum frequency at a given + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** voltage scaling (scale 1, scale 2 or scale 3) + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** higher frequency than the normal mode for a given voltage scaling (scale 1, + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mod + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** the sequence described in Reference manual. + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** (+) In Stop mode: the main regulator or low power regulator supplies a low power + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** voltage to the 1.2V domain, thus preserving the content of registers + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** and internal SRAM. 2 operating modes are available: + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** available when the main regulator or the low power regulator is used in Scale 3 or + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** low voltage mode. + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** available when the main regulator or the low power regulator is in low voltage mode. + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** @endverbatim + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @{ + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @brief Enables the Backup Regulator. + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @retval HAL status + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 28 .loc 1 135 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 0000 10B5 push {r4, lr} + 33 .LCFI0: + 34 .cfi_def_cfa_offset 8 + 35 .cfi_offset 4, -8 + 36 .cfi_offset 14, -4 + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** uint32_t tickstart = 0; + ARM GAS /tmp/ccuaURzG.s page 4 + + + 37 .loc 1 136 3 view .LVU1 + 38 .LVL0: + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Enable Backup regulator */ + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** PWR->CSR1 |= PWR_CSR1_BRE; + 39 .loc 1 139 3 view .LVU2 + 40 .loc 1 139 6 is_stmt 0 view .LVU3 + 41 0002 0D4B ldr r3, .L8 + 42 0004 5A68 ldr r2, [r3, #4] + 43 .loc 1 139 13 view .LVU4 + 44 0006 42F40072 orr r2, r2, #512 + 45 000a 5A60 str r2, [r3, #4] + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Workaround for the following hardware bug: */ + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */ + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** PWR->CSR1 |= PWR_CSR1_EIWUP; + 46 .loc 1 143 3 is_stmt 1 view .LVU5 + 47 .loc 1 143 6 is_stmt 0 view .LVU6 + 48 000c 5A68 ldr r2, [r3, #4] + 49 .loc 1 143 13 view .LVU7 + 50 000e 42F48072 orr r2, r2, #256 + 51 0012 5A60 str r2, [r3, #4] + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Get tick */ + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick(); + 52 .loc 1 146 3 is_stmt 1 view .LVU8 + 53 .loc 1 146 15 is_stmt 0 view .LVU9 + 54 0014 FFF7FEFF bl HAL_GetTick + 55 .LVL1: + 56 0018 0446 mov r4, r0 + 57 .LVL2: + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Wait till Backup regulator ready flag is set */ + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET) + 58 .loc 1 149 3 is_stmt 1 view .LVU10 + 59 .L2: + 60 .loc 1 149 42 view .LVU11 + 61 .loc 1 149 9 is_stmt 0 view .LVU12 + 62 001a 074B ldr r3, .L8 + 63 001c 5B68 ldr r3, [r3, #4] + 64 .loc 1 149 42 view .LVU13 + 65 001e 13F0080F tst r3, #8 + 66 0022 07D1 bne .L7 + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) + 67 .loc 1 151 5 is_stmt 1 view .LVU14 + 68 .loc 1 151 9 is_stmt 0 view .LVU15 + 69 0024 FFF7FEFF bl HAL_GetTick + 70 .LVL3: + 71 .loc 1 151 23 discriminator 1 view .LVU16 + 72 0028 001B subs r0, r0, r4 + 73 .loc 1 151 7 discriminator 1 view .LVU17 + 74 002a B0F57A7F cmp r0, #1000 + 75 002e F4D9 bls .L2 + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** return HAL_TIMEOUT; + 76 .loc 1 153 14 view .LVU18 + ARM GAS /tmp/ccuaURzG.s page 5 + + + 77 0030 0320 movs r0, #3 + 78 0032 00E0 b .L3 + 79 .L7: + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** return HAL_OK; + 80 .loc 1 156 10 view .LVU19 + 81 0034 0020 movs r0, #0 + 82 .L3: + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 83 .loc 1 157 1 view .LVU20 + 84 0036 10BD pop {r4, pc} + 85 .LVL4: + 86 .L9: + 87 .loc 1 157 1 view .LVU21 + 88 .align 2 + 89 .L8: + 90 0038 00700040 .word 1073770496 + 91 .cfi_endproc + 92 .LFE141: + 94 .section .text.HAL_PWREx_DisableBkUpReg,"ax",%progbits + 95 .align 1 + 96 .global HAL_PWREx_DisableBkUpReg + 97 .syntax unified + 98 .thumb + 99 .thumb_func + 101 HAL_PWREx_DisableBkUpReg: + 102 .LFB142: + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @brief Disables the Backup Regulator. + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @retval HAL status + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 103 .loc 1 164 1 is_stmt 1 view -0 + 104 .cfi_startproc + 105 @ args = 0, pretend = 0, frame = 0 + 106 @ frame_needed = 0, uses_anonymous_args = 0 + 107 0000 10B5 push {r4, lr} + 108 .LCFI1: + 109 .cfi_def_cfa_offset 8 + 110 .cfi_offset 4, -8 + 111 .cfi_offset 14, -4 + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** uint32_t tickstart = 0; + 112 .loc 1 165 3 view .LVU23 + 113 .LVL5: + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Disable Backup regulator */ + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE); + 114 .loc 1 168 3 view .LVU24 + 115 .loc 1 168 6 is_stmt 0 view .LVU25 + 116 0002 0D4B ldr r3, .L17 + 117 0004 5A68 ldr r2, [r3, #4] + 118 .loc 1 168 13 view .LVU26 + 119 0006 22F40072 bic r2, r2, #512 + 120 000a 5A60 str r2, [r3, #4] + ARM GAS /tmp/ccuaURzG.s page 6 + + + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Workaround for the following hardware bug: */ + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */ + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** PWR->CSR1 |= PWR_CSR1_EIWUP; + 121 .loc 1 172 3 is_stmt 1 view .LVU27 + 122 .loc 1 172 6 is_stmt 0 view .LVU28 + 123 000c 5A68 ldr r2, [r3, #4] + 124 .loc 1 172 13 view .LVU29 + 125 000e 42F48072 orr r2, r2, #256 + 126 0012 5A60 str r2, [r3, #4] + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Get tick */ + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick(); + 127 .loc 1 175 3 is_stmt 1 view .LVU30 + 128 .loc 1 175 15 is_stmt 0 view .LVU31 + 129 0014 FFF7FEFF bl HAL_GetTick + 130 .LVL6: + 131 0018 0446 mov r4, r0 + 132 .LVL7: + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Wait till Backup regulator ready flag is set */ + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET) + 133 .loc 1 178 3 is_stmt 1 view .LVU32 + 134 .L11: + 135 .loc 1 178 42 view .LVU33 + 136 .loc 1 178 9 is_stmt 0 view .LVU34 + 137 001a 074B ldr r3, .L17 + 138 001c 5B68 ldr r3, [r3, #4] + 139 .loc 1 178 42 view .LVU35 + 140 001e 13F0080F tst r3, #8 + 141 0022 07D0 beq .L16 + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) + 142 .loc 1 180 5 is_stmt 1 view .LVU36 + 143 .loc 1 180 9 is_stmt 0 view .LVU37 + 144 0024 FFF7FEFF bl HAL_GetTick + 145 .LVL8: + 146 .loc 1 180 23 discriminator 1 view .LVU38 + 147 0028 001B subs r0, r0, r4 + 148 .loc 1 180 7 discriminator 1 view .LVU39 + 149 002a B0F57A7F cmp r0, #1000 + 150 002e F4D9 bls .L11 + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** return HAL_TIMEOUT; + 151 .loc 1 182 14 view .LVU40 + 152 0030 0320 movs r0, #3 + 153 0032 00E0 b .L12 + 154 .L16: + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** return HAL_OK; + 155 .loc 1 185 10 view .LVU41 + 156 0034 0020 movs r0, #0 + 157 .L12: + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 158 .loc 1 186 1 view .LVU42 + 159 0036 10BD pop {r4, pc} + ARM GAS /tmp/ccuaURzG.s page 7 + + + 160 .LVL9: + 161 .L18: + 162 .loc 1 186 1 view .LVU43 + 163 .align 2 + 164 .L17: + 165 0038 00700040 .word 1073770496 + 166 .cfi_endproc + 167 .LFE142: + 169 .section .text.HAL_PWREx_EnableFlashPowerDown,"ax",%progbits + 170 .align 1 + 171 .global HAL_PWREx_EnableFlashPowerDown + 172 .syntax unified + 173 .thumb + 174 .thumb_func + 176 HAL_PWREx_EnableFlashPowerDown: + 177 .LFB143: + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @brief Enables the Flash Power Down in Stop mode. + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @retval None + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableFlashPowerDown(void) + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 178 .loc 1 193 1 is_stmt 1 view -0 + 179 .cfi_startproc + 180 @ args = 0, pretend = 0, frame = 0 + 181 @ frame_needed = 0, uses_anonymous_args = 0 + 182 @ link register save eliminated. + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Enable the Flash Power Down */ + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** PWR->CR1 |= PWR_CR1_FPDS; + 183 .loc 1 195 3 view .LVU45 + 184 .loc 1 195 6 is_stmt 0 view .LVU46 + 185 0000 024A ldr r2, .L20 + 186 0002 1368 ldr r3, [r2] + 187 .loc 1 195 12 view .LVU47 + 188 0004 43F40073 orr r3, r3, #512 + 189 0008 1360 str r3, [r2] + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 190 .loc 1 196 1 view .LVU48 + 191 000a 7047 bx lr + 192 .L21: + 193 .align 2 + 194 .L20: + 195 000c 00700040 .word 1073770496 + 196 .cfi_endproc + 197 .LFE143: + 199 .section .text.HAL_PWREx_DisableFlashPowerDown,"ax",%progbits + 200 .align 1 + 201 .global HAL_PWREx_DisableFlashPowerDown + 202 .syntax unified + 203 .thumb + 204 .thumb_func + 206 HAL_PWREx_DisableFlashPowerDown: + 207 .LFB144: + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @brief Disables the Flash Power Down in Stop mode. + ARM GAS /tmp/ccuaURzG.s page 8 + + + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @retval None + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableFlashPowerDown(void) + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 208 .loc 1 203 1 is_stmt 1 view -0 + 209 .cfi_startproc + 210 @ args = 0, pretend = 0, frame = 0 + 211 @ frame_needed = 0, uses_anonymous_args = 0 + 212 @ link register save eliminated. + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Disable the Flash Power Down */ + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS); + 213 .loc 1 205 3 view .LVU50 + 214 .loc 1 205 6 is_stmt 0 view .LVU51 + 215 0000 024A ldr r2, .L23 + 216 0002 1368 ldr r3, [r2] + 217 .loc 1 205 12 view .LVU52 + 218 0004 23F40073 bic r3, r3, #512 + 219 0008 1360 str r3, [r2] + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 220 .loc 1 206 1 view .LVU53 + 221 000a 7047 bx lr + 222 .L24: + 223 .align 2 + 224 .L23: + 225 000c 00700040 .word 1073770496 + 226 .cfi_endproc + 227 .LFE144: + 229 .section .text.HAL_PWREx_EnableMainRegulatorLowVoltage,"ax",%progbits + 230 .align 1 + 231 .global HAL_PWREx_EnableMainRegulatorLowVoltage + 232 .syntax unified + 233 .thumb + 234 .thumb_func + 236 HAL_PWREx_EnableMainRegulatorLowVoltage: + 237 .LFB145: + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @brief Enables Main Regulator low voltage mode. + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @retval None + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableMainRegulatorLowVoltage(void) + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 238 .loc 1 213 1 is_stmt 1 view -0 + 239 .cfi_startproc + 240 @ args = 0, pretend = 0, frame = 0 + 241 @ frame_needed = 0, uses_anonymous_args = 0 + 242 @ link register save eliminated. + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Enable Main regulator low voltage */ + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** PWR->CR1 |= PWR_CR1_MRUDS; + 243 .loc 1 215 3 view .LVU55 + 244 .loc 1 215 6 is_stmt 0 view .LVU56 + 245 0000 024A ldr r2, .L26 + 246 0002 1368 ldr r3, [r2] + 247 .loc 1 215 12 view .LVU57 + 248 0004 43F40063 orr r3, r3, #2048 + 249 0008 1360 str r3, [r2] + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + ARM GAS /tmp/ccuaURzG.s page 9 + + + 250 .loc 1 216 1 view .LVU58 + 251 000a 7047 bx lr + 252 .L27: + 253 .align 2 + 254 .L26: + 255 000c 00700040 .word 1073770496 + 256 .cfi_endproc + 257 .LFE145: + 259 .section .text.HAL_PWREx_DisableMainRegulatorLowVoltage,"ax",%progbits + 260 .align 1 + 261 .global HAL_PWREx_DisableMainRegulatorLowVoltage + 262 .syntax unified + 263 .thumb + 264 .thumb_func + 266 HAL_PWREx_DisableMainRegulatorLowVoltage: + 267 .LFB146: + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @brief Disables Main Regulator low voltage mode. + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @retval None + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableMainRegulatorLowVoltage(void) + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 268 .loc 1 223 1 is_stmt 1 view -0 + 269 .cfi_startproc + 270 @ args = 0, pretend = 0, frame = 0 + 271 @ frame_needed = 0, uses_anonymous_args = 0 + 272 @ link register save eliminated. + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Disable Main regulator low voltage */ + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS); + 273 .loc 1 225 3 view .LVU60 + 274 .loc 1 225 6 is_stmt 0 view .LVU61 + 275 0000 024A ldr r2, .L29 + 276 0002 1368 ldr r3, [r2] + 277 .loc 1 225 12 view .LVU62 + 278 0004 23F40063 bic r3, r3, #2048 + 279 0008 1360 str r3, [r2] + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 280 .loc 1 226 1 view .LVU63 + 281 000a 7047 bx lr + 282 .L30: + 283 .align 2 + 284 .L29: + 285 000c 00700040 .word 1073770496 + 286 .cfi_endproc + 287 .LFE146: + 289 .section .text.HAL_PWREx_EnableLowRegulatorLowVoltage,"ax",%progbits + 290 .align 1 + 291 .global HAL_PWREx_EnableLowRegulatorLowVoltage + 292 .syntax unified + 293 .thumb + 294 .thumb_func + 296 HAL_PWREx_EnableLowRegulatorLowVoltage: + 297 .LFB147: + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @brief Enables Low Power Regulator low voltage mode. + ARM GAS /tmp/ccuaURzG.s page 10 + + + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @retval None + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableLowRegulatorLowVoltage(void) + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 298 .loc 1 233 1 is_stmt 1 view -0 + 299 .cfi_startproc + 300 @ args = 0, pretend = 0, frame = 0 + 301 @ frame_needed = 0, uses_anonymous_args = 0 + 302 @ link register save eliminated. + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Enable low power regulator */ + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** PWR->CR1 |= PWR_CR1_LPUDS; + 303 .loc 1 235 3 view .LVU65 + 304 .loc 1 235 6 is_stmt 0 view .LVU66 + 305 0000 024A ldr r2, .L32 + 306 0002 1368 ldr r3, [r2] + 307 .loc 1 235 12 view .LVU67 + 308 0004 43F48063 orr r3, r3, #1024 + 309 0008 1360 str r3, [r2] + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 310 .loc 1 236 1 view .LVU68 + 311 000a 7047 bx lr + 312 .L33: + 313 .align 2 + 314 .L32: + 315 000c 00700040 .word 1073770496 + 316 .cfi_endproc + 317 .LFE147: + 319 .section .text.HAL_PWREx_DisableLowRegulatorLowVoltage,"ax",%progbits + 320 .align 1 + 321 .global HAL_PWREx_DisableLowRegulatorLowVoltage + 322 .syntax unified + 323 .thumb + 324 .thumb_func + 326 HAL_PWREx_DisableLowRegulatorLowVoltage: + 327 .LFB148: + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @brief Disables Low Power Regulator low voltage mode. + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @retval None + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableLowRegulatorLowVoltage(void) + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 328 .loc 1 243 1 is_stmt 1 view -0 + 329 .cfi_startproc + 330 @ args = 0, pretend = 0, frame = 0 + 331 @ frame_needed = 0, uses_anonymous_args = 0 + 332 @ link register save eliminated. + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Disable low power regulator */ + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS); + 333 .loc 1 245 3 view .LVU70 + 334 .loc 1 245 6 is_stmt 0 view .LVU71 + 335 0000 024A ldr r2, .L35 + 336 0002 1368 ldr r3, [r2] + 337 .loc 1 245 12 view .LVU72 + 338 0004 23F48063 bic r3, r3, #1024 + 339 0008 1360 str r3, [r2] + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + ARM GAS /tmp/ccuaURzG.s page 11 + + + 340 .loc 1 246 1 view .LVU73 + 341 000a 7047 bx lr + 342 .L36: + 343 .align 2 + 344 .L35: + 345 000c 00700040 .word 1073770496 + 346 .cfi_endproc + 347 .LFE148: + 349 .section .text.HAL_PWREx_EnableOverDrive,"ax",%progbits + 350 .align 1 + 351 .global HAL_PWREx_EnableOverDrive + 352 .syntax unified + 353 .thumb + 354 .thumb_func + 356 HAL_PWREx_EnableOverDrive: + 357 .LFB149: + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @brief Activates the Over-Drive mode. + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @note This mode allows the CPU and the core logic to operate at a higher frequency + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @note It is recommended to enter or exit Over-drive mode when the application is not running + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * critical tasks and when the system clock source is either HSI or HSE. + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * During the Over-drive switch activation, no peripheral clocks should be enabled. + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * The peripheral clocks must be enabled once the Over-drive mode is activated. + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @retval HAL status + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 358 .loc 1 259 1 is_stmt 1 view -0 + 359 .cfi_startproc + 360 @ args = 0, pretend = 0, frame = 8 + 361 @ frame_needed = 0, uses_anonymous_args = 0 + 362 0000 10B5 push {r4, lr} + 363 .LCFI2: + 364 .cfi_def_cfa_offset 8 + 365 .cfi_offset 4, -8 + 366 .cfi_offset 14, -4 + 367 0002 82B0 sub sp, sp, #8 + 368 .LCFI3: + 369 .cfi_def_cfa_offset 16 + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** uint32_t tickstart = 0; + 370 .loc 1 260 3 view .LVU75 + 371 .LVL10: + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 372 .loc 1 262 3 view .LVU76 + 373 .LBB2: + 374 .loc 1 262 3 view .LVU77 + 375 .loc 1 262 3 view .LVU78 + 376 0004 1B4B ldr r3, .L48 + 377 0006 1A6C ldr r2, [r3, #64] + 378 0008 42F08052 orr r2, r2, #268435456 + 379 000c 1A64 str r2, [r3, #64] + 380 .loc 1 262 3 view .LVU79 + 381 000e 1B6C ldr r3, [r3, #64] + 382 0010 03F08053 and r3, r3, #268435456 + ARM GAS /tmp/ccuaURzG.s page 12 + + + 383 0014 0193 str r3, [sp, #4] + 384 .loc 1 262 3 view .LVU80 + 385 0016 019B ldr r3, [sp, #4] + 386 .LBE2: + 387 .loc 1 262 3 view .LVU81 + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Enable the Over-drive to extend the clock frequency to 216 MHz */ + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** __HAL_PWR_OVERDRIVE_ENABLE(); + 388 .loc 1 265 3 view .LVU82 + 389 0018 174A ldr r2, .L48+4 + 390 001a 1368 ldr r3, [r2] + 391 001c 43F48033 orr r3, r3, #65536 + 392 0020 1360 str r3, [r2] + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Get tick */ + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick(); + 393 .loc 1 268 3 view .LVU83 + 394 .loc 1 268 15 is_stmt 0 view .LVU84 + 395 0022 FFF7FEFF bl HAL_GetTick + 396 .LVL11: + 397 0026 0446 mov r4, r0 + 398 .LVL12: + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) + 399 .loc 1 270 3 is_stmt 1 view .LVU85 + 400 .L38: + 401 .loc 1 270 9 view .LVU86 + 402 .loc 1 270 10 is_stmt 0 view .LVU87 + 403 0028 134B ldr r3, .L48+4 + 404 002a 5B68 ldr r3, [r3, #4] + 405 .loc 1 270 9 view .LVU88 + 406 002c 13F4803F tst r3, #65536 + 407 0030 08D1 bne .L46 + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + 408 .loc 1 272 5 is_stmt 1 view .LVU89 + 409 .loc 1 272 9 is_stmt 0 view .LVU90 + 410 0032 FFF7FEFF bl HAL_GetTick + 411 .LVL13: + 412 .loc 1 272 23 discriminator 1 view .LVU91 + 413 0036 001B subs r0, r0, r4 + 414 .loc 1 272 7 discriminator 1 view .LVU92 + 415 0038 B0F57A7F cmp r0, #1000 + 416 003c F4D9 bls .L38 + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** return HAL_TIMEOUT; + 417 .loc 1 274 14 view .LVU93 + 418 003e 0320 movs r0, #3 + 419 .L39: + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Enable the Over-drive switch */ + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** __HAL_PWR_OVERDRIVESWITCHING_ENABLE(); + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Get tick */ + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick(); + ARM GAS /tmp/ccuaURzG.s page 13 + + + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** return HAL_TIMEOUT; + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** return HAL_OK; + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 420 .loc 1 292 1 view .LVU94 + 421 0040 02B0 add sp, sp, #8 + 422 .LCFI4: + 423 .cfi_remember_state + 424 .cfi_def_cfa_offset 8 + 425 @ sp needed + 426 0042 10BD pop {r4, pc} + 427 .LVL14: + 428 .L46: + 429 .LCFI5: + 430 .cfi_restore_state + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 431 .loc 1 279 3 is_stmt 1 view .LVU95 + 432 0044 0C4A ldr r2, .L48+4 + 433 0046 1368 ldr r3, [r2] + 434 0048 43F40033 orr r3, r3, #131072 + 435 004c 1360 str r3, [r2] + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 436 .loc 1 282 3 view .LVU96 + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 437 .loc 1 282 15 is_stmt 0 view .LVU97 + 438 004e FFF7FEFF bl HAL_GetTick + 439 .LVL15: + 440 0052 0446 mov r4, r0 + 441 .LVL16: + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 442 .loc 1 284 3 is_stmt 1 view .LVU98 + 443 .L41: + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 444 .loc 1 284 9 view .LVU99 + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 445 .loc 1 284 10 is_stmt 0 view .LVU100 + 446 0054 084B ldr r3, .L48+4 + 447 0056 5B68 ldr r3, [r3, #4] + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 448 .loc 1 284 9 view .LVU101 + 449 0058 13F4003F tst r3, #131072 + 450 005c 07D1 bne .L47 + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 451 .loc 1 286 5 is_stmt 1 view .LVU102 + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 452 .loc 1 286 9 is_stmt 0 view .LVU103 + 453 005e FFF7FEFF bl HAL_GetTick + 454 .LVL17: + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 455 .loc 1 286 23 discriminator 1 view .LVU104 + 456 0062 001B subs r0, r0, r4 + ARM GAS /tmp/ccuaURzG.s page 14 + + + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 457 .loc 1 286 7 discriminator 1 view .LVU105 + 458 0064 B0F57A7F cmp r0, #1000 + 459 0068 F4D9 bls .L41 + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 460 .loc 1 288 14 view .LVU106 + 461 006a 0320 movs r0, #3 + 462 006c E8E7 b .L39 + 463 .L47: + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 464 .loc 1 291 10 view .LVU107 + 465 006e 0020 movs r0, #0 + 466 0070 E6E7 b .L39 + 467 .L49: + 468 0072 00BF .align 2 + 469 .L48: + 470 0074 00380240 .word 1073887232 + 471 0078 00700040 .word 1073770496 + 472 .cfi_endproc + 473 .LFE149: + 475 .section .text.HAL_PWREx_DisableOverDrive,"ax",%progbits + 476 .align 1 + 477 .global HAL_PWREx_DisableOverDrive + 478 .syntax unified + 479 .thumb + 480 .thumb_func + 482 HAL_PWREx_DisableOverDrive: + 483 .LFB150: + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @brief Deactivates the Over-Drive mode. + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @note This mode allows the CPU and the core logic to operate at a higher frequency + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @note It is recommended to enter or exit Over-drive mode when the application is not running + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * critical tasks and when the system clock source is either HSI or HSE. + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * During the Over-drive switch activation, no peripheral clocks should be enabled. + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * The peripheral clocks must be enabled once the Over-drive mode is activated. + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @retval HAL status + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 484 .loc 1 305 1 is_stmt 1 view -0 + 485 .cfi_startproc + 486 @ args = 0, pretend = 0, frame = 8 + 487 @ frame_needed = 0, uses_anonymous_args = 0 + 488 0000 10B5 push {r4, lr} + 489 .LCFI6: + 490 .cfi_def_cfa_offset 8 + 491 .cfi_offset 4, -8 + 492 .cfi_offset 14, -4 + 493 0002 82B0 sub sp, sp, #8 + 494 .LCFI7: + 495 .cfi_def_cfa_offset 16 + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** uint32_t tickstart = 0; + 496 .loc 1 306 3 view .LVU109 + 497 .LVL18: + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + ARM GAS /tmp/ccuaURzG.s page 15 + + + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 498 .loc 1 308 3 view .LVU110 + 499 .LBB3: + 500 .loc 1 308 3 view .LVU111 + 501 .loc 1 308 3 view .LVU112 + 502 0004 1B4B ldr r3, .L61 + 503 0006 1A6C ldr r2, [r3, #64] + 504 0008 42F08052 orr r2, r2, #268435456 + 505 000c 1A64 str r2, [r3, #64] + 506 .loc 1 308 3 view .LVU113 + 507 000e 1B6C ldr r3, [r3, #64] + 508 0010 03F08053 and r3, r3, #268435456 + 509 0014 0193 str r3, [sp, #4] + 510 .loc 1 308 3 view .LVU114 + 511 0016 019B ldr r3, [sp, #4] + 512 .LBE3: + 513 .loc 1 308 3 view .LVU115 + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Disable the Over-drive switch */ + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** __HAL_PWR_OVERDRIVESWITCHING_DISABLE(); + 514 .loc 1 311 3 view .LVU116 + 515 0018 174A ldr r2, .L61+4 + 516 001a 1368 ldr r3, [r2] + 517 001c 23F40033 bic r3, r3, #131072 + 518 0020 1360 str r3, [r2] + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Get tick */ + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick(); + 519 .loc 1 314 3 view .LVU117 + 520 .loc 1 314 15 is_stmt 0 view .LVU118 + 521 0022 FFF7FEFF bl HAL_GetTick + 522 .LVL19: + 523 0026 0446 mov r4, r0 + 524 .LVL20: + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) + 525 .loc 1 316 3 is_stmt 1 view .LVU119 + 526 .L51: + 527 .loc 1 316 9 view .LVU120 + 528 0028 134B ldr r3, .L61+4 + 529 002a 5B68 ldr r3, [r3, #4] + 530 002c 13F4003F tst r3, #131072 + 531 0030 08D0 beq .L59 + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + 532 .loc 1 318 5 view .LVU121 + 533 .loc 1 318 9 is_stmt 0 view .LVU122 + 534 0032 FFF7FEFF bl HAL_GetTick + 535 .LVL21: + 536 .loc 1 318 23 discriminator 1 view .LVU123 + 537 0036 001B subs r0, r0, r4 + 538 .loc 1 318 7 discriminator 1 view .LVU124 + 539 0038 B0F57A7F cmp r0, #1000 + 540 003c F4D9 bls .L51 + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** return HAL_TIMEOUT; + 541 .loc 1 320 14 view .LVU125 + ARM GAS /tmp/ccuaURzG.s page 16 + + + 542 003e 0320 movs r0, #3 + 543 .L52: + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Disable the Over-drive */ + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** __HAL_PWR_OVERDRIVE_DISABLE(); + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Get tick */ + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick(); + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** return HAL_TIMEOUT; + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** return HAL_OK; + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 544 .loc 1 339 1 view .LVU126 + 545 0040 02B0 add sp, sp, #8 + 546 .LCFI8: + 547 .cfi_remember_state + 548 .cfi_def_cfa_offset 8 + 549 @ sp needed + 550 0042 10BD pop {r4, pc} + 551 .LVL22: + 552 .L59: + 553 .LCFI9: + 554 .cfi_restore_state + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 555 .loc 1 325 3 is_stmt 1 view .LVU127 + 556 0044 0C4A ldr r2, .L61+4 + 557 0046 1368 ldr r3, [r2] + 558 0048 23F48033 bic r3, r3, #65536 + 559 004c 1360 str r3, [r2] + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 560 .loc 1 328 3 view .LVU128 + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 561 .loc 1 328 15 is_stmt 0 view .LVU129 + 562 004e FFF7FEFF bl HAL_GetTick + 563 .LVL23: + 564 0052 0446 mov r4, r0 + 565 .LVL24: + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 566 .loc 1 330 3 is_stmt 1 view .LVU130 + 567 .L54: + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 568 .loc 1 330 9 view .LVU131 + 569 0054 084B ldr r3, .L61+4 + 570 0056 5B68 ldr r3, [r3, #4] + 571 0058 13F4803F tst r3, #65536 + 572 005c 07D0 beq .L60 + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 573 .loc 1 332 5 view .LVU132 + ARM GAS /tmp/ccuaURzG.s page 17 + + + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 574 .loc 1 332 9 is_stmt 0 view .LVU133 + 575 005e FFF7FEFF bl HAL_GetTick + 576 .LVL25: + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 577 .loc 1 332 23 discriminator 1 view .LVU134 + 578 0062 001B subs r0, r0, r4 + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 579 .loc 1 332 7 discriminator 1 view .LVU135 + 580 0064 B0F57A7F cmp r0, #1000 + 581 0068 F4D9 bls .L54 + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 582 .loc 1 334 14 view .LVU136 + 583 006a 0320 movs r0, #3 + 584 006c E8E7 b .L52 + 585 .L60: + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 586 .loc 1 338 10 view .LVU137 + 587 006e 0020 movs r0, #0 + 588 0070 E6E7 b .L52 + 589 .L62: + 590 0072 00BF .align 2 + 591 .L61: + 592 0074 00380240 .word 1073887232 + 593 0078 00700040 .word 1073770496 + 594 .cfi_endproc + 595 .LFE150: + 597 .section .text.HAL_PWREx_EnterUnderDriveSTOPMode,"ax",%progbits + 598 .align 1 + 599 .global HAL_PWREx_EnterUnderDriveSTOPMode + 600 .syntax unified + 601 .thumb + 602 .thumb_func + 604 HAL_PWREx_EnterUnderDriveSTOPMode: + 605 .LVL26: + 606 .LFB151: + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @brief Enters in Under-Drive STOP mode. + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @note This mode can be selected only when the Under-Drive is already active + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @note This mode is enabled only with STOP low power mode. + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * mode is only available when the main regulator or the low power regulator + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * is in low voltage mode + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @note If the Under-drive mode was enabled, it is automatically disabled after + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * exiting Stop mode. + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * When the voltage regulator operates in Under-drive mode, an additional + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * startup delay is induced when waking up from Stop mode. + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode. + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * the HSI RC oscillator is selected as system clock. + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * + ARM GAS /tmp/ccuaURzG.s page 18 + + + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @note When the voltage regulator operates in low power mode, an additional + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * startup delay is incurred when waking up from Stop mode. + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * By keeping the internal regulator ON during Stop mode, the consumption + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * is higher although the startup time is reduced. + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @param Regulator specifies the regulator state in STOP mode. + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * This parameter can be one of the following values: + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * and Flash memory in power-down when the device is in Stop under-drive mode + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * and Flash memory in power-down when the device is in Stop under-drive mode + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * This parameter can be one of the following values: + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @retval None + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry) + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 607 .loc 1 379 1 is_stmt 1 view -0 + 608 .cfi_startproc + 609 @ args = 0, pretend = 0, frame = 8 + 610 @ frame_needed = 0, uses_anonymous_args = 0 + 611 .loc 1 379 1 is_stmt 0 view .LVU139 + 612 0000 70B5 push {r4, r5, r6, lr} + 613 .LCFI10: + 614 .cfi_def_cfa_offset 16 + 615 .cfi_offset 4, -16 + 616 .cfi_offset 5, -12 + 617 .cfi_offset 6, -8 + 618 .cfi_offset 14, -4 + 619 0002 82B0 sub sp, sp, #8 + 620 .LCFI11: + 621 .cfi_def_cfa_offset 24 + 622 0004 0646 mov r6, r0 + 623 0006 0D46 mov r5, r1 + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** uint32_t tempreg = 0; + 624 .loc 1 380 3 is_stmt 1 view .LVU140 + 625 .LVL27: + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** uint32_t tickstart = 0; + 626 .loc 1 381 3 view .LVU141 + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Check the parameters */ + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator)); + 627 .loc 1 384 3 view .LVU142 + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + 628 .loc 1 385 3 view .LVU143 + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Enable Power ctrl clock */ + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 629 .loc 1 388 3 view .LVU144 + 630 .LBB4: + 631 .loc 1 388 3 view .LVU145 + 632 .loc 1 388 3 view .LVU146 + 633 0008 1E4B ldr r3, .L73 + 634 000a 1A6C ldr r2, [r3, #64] + 635 000c 42F08052 orr r2, r2, #268435456 + ARM GAS /tmp/ccuaURzG.s page 19 + + + 636 0010 1A64 str r2, [r3, #64] + 637 .loc 1 388 3 view .LVU147 + 638 0012 1B6C ldr r3, [r3, #64] + 639 0014 03F08053 and r3, r3, #268435456 + 640 0018 0193 str r3, [sp, #4] + 641 .loc 1 388 3 view .LVU148 + 642 001a 019B ldr r3, [sp, #4] + 643 .LBE4: + 644 .loc 1 388 3 view .LVU149 + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Enable the Under-drive Mode ---------------------------------------------*/ + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Clear Under-drive flag */ + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** __HAL_PWR_CLEAR_ODRUDR_FLAG(); + 645 .loc 1 391 3 view .LVU150 + 646 001c 1A4B ldr r3, .L73+4 + 647 001e 5968 ldr r1, [r3, #4] + 648 .LVL28: + 649 .loc 1 391 3 is_stmt 0 view .LVU151 + 650 0020 1A4A ldr r2, .L73+8 + 651 0022 0A43 orrs r2, r2, r1 + 652 0024 5A60 str r2, [r3, #4] + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Enable the Under-drive */ + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** __HAL_PWR_UNDERDRIVE_ENABLE(); + 653 .loc 1 394 3 is_stmt 1 view .LVU152 + 654 0026 1A68 ldr r2, [r3] + 655 0028 42F44022 orr r2, r2, #786432 + 656 002c 1A60 str r2, [r3] + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Get tick */ + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick(); + 657 .loc 1 397 3 view .LVU153 + 658 .loc 1 397 15 is_stmt 0 view .LVU154 + 659 002e FFF7FEFF bl HAL_GetTick + 660 .LVL29: + 661 .loc 1 397 15 view .LVU155 + 662 0032 0446 mov r4, r0 + 663 .LVL30: + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Wait for UnderDrive mode is ready */ + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY)) + 664 .loc 1 400 3 is_stmt 1 view .LVU156 + 665 .L64: + 666 .loc 1 400 9 view .LVU157 + 667 0034 144B ldr r3, .L73+4 + 668 0036 5B68 ldr r3, [r3, #4] + 669 0038 03F44023 and r3, r3, #786432 + 670 003c B3F5402F cmp r3, #786432 + 671 0040 07D1 bne .L71 + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE) + 672 .loc 1 402 5 view .LVU158 + 673 .loc 1 402 9 is_stmt 0 view .LVU159 + 674 0042 FFF7FEFF bl HAL_GetTick + 675 .LVL31: + 676 .loc 1 402 23 discriminator 1 view .LVU160 + 677 0046 001B subs r0, r0, r4 + 678 .loc 1 402 7 discriminator 1 view .LVU161 + ARM GAS /tmp/ccuaURzG.s page 20 + + + 679 0048 B0F57A7F cmp r0, #1000 + 680 004c F2D9 bls .L64 + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** return HAL_TIMEOUT; + 681 .loc 1 404 14 view .LVU162 + 682 004e 0320 movs r0, #3 + 683 0050 13E0 b .L65 + 684 .L71: + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Select the regulator state in STOP mode ---------------------------------*/ + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** tempreg = PWR->CR1; + 685 .loc 1 409 3 is_stmt 1 view .LVU163 + 686 .loc 1 409 11 is_stmt 0 view .LVU164 + 687 0052 0D4A ldr r2, .L73+4 + 688 0054 1168 ldr r1, [r2] + 689 .LVL32: + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */ + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS); + 690 .loc 1 411 3 is_stmt 1 view .LVU165 + 691 .loc 1 411 11 is_stmt 0 view .LVU166 + 692 0056 0E4B ldr r3, .L73+12 + 693 0058 0B40 ands r3, r3, r1 + 694 .LVL33: + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** tempreg |= Regulator; + 695 .loc 1 414 3 is_stmt 1 view .LVU167 + 696 .loc 1 414 11 is_stmt 0 view .LVU168 + 697 005a 3343 orrs r3, r3, r6 + 698 .LVL34: + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Store the new value */ + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** PWR->CR1 = tempreg; + 699 .loc 1 417 3 is_stmt 1 view .LVU169 + 700 .loc 1 417 12 is_stmt 0 view .LVU170 + 701 005c 1360 str r3, [r2] + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + 702 .loc 1 420 3 is_stmt 1 view .LVU171 + 703 .loc 1 420 6 is_stmt 0 view .LVU172 + 704 005e 0D4A ldr r2, .L73+16 + 705 0060 1369 ldr r3, [r2, #16] + 706 .LVL35: + 707 .loc 1 420 12 view .LVU173 + 708 0062 43F00403 orr r3, r3, #4 + 709 0066 1361 str r3, [r2, #16] + 710 .LVL36: + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Select STOP mode entry --------------------------------------------------*/ + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** if(STOPEntry == PWR_SLEEPENTRY_WFI) + 711 .loc 1 423 3 is_stmt 1 view .LVU174 + 712 .loc 1 423 5 is_stmt 0 view .LVU175 + 713 0068 012D cmp r5, #1 + 714 006a 08D0 beq .L72 + ARM GAS /tmp/ccuaURzG.s page 21 + + + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Request Wait For Interrupt */ + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** __WFI(); + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** else + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Request Wait For Event */ + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** __WFE(); + 715 .loc 1 431 5 is_stmt 1 view .LVU176 + 716 .syntax unified + 717 @ 431 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c" 1 + 718 006c 20BF wfe + 719 @ 0 "" 2 + 720 .thumb + 721 .syntax unified + 722 .L68: + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Reset SLEEPDEEP bit of Cortex System Control Register */ + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + 723 .loc 1 434 3 view .LVU177 + 724 .loc 1 434 6 is_stmt 0 view .LVU178 + 725 006e 094A ldr r2, .L73+16 + 726 0070 1369 ldr r3, [r2, #16] + 727 .loc 1 434 12 view .LVU179 + 728 0072 23F00403 bic r3, r3, #4 + 729 0076 1361 str r3, [r2, #16] + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** return HAL_OK; + 730 .loc 1 436 3 is_stmt 1 view .LVU180 + 731 .loc 1 436 10 is_stmt 0 view .LVU181 + 732 0078 0020 movs r0, #0 + 733 .LVL37: + 734 .L65: + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 735 .loc 1 437 1 view .LVU182 + 736 007a 02B0 add sp, sp, #8 + 737 .LCFI12: + 738 .cfi_remember_state + 739 .cfi_def_cfa_offset 16 + 740 @ sp needed + 741 007c 70BD pop {r4, r5, r6, pc} + 742 .LVL38: + 743 .L72: + 744 .LCFI13: + 745 .cfi_restore_state + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 746 .loc 1 426 5 is_stmt 1 view .LVU183 + 747 .syntax unified + 748 @ 426 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c" 1 + 749 007e 30BF wfi + 750 @ 0 "" 2 + 751 .thumb + 752 .syntax unified + 753 0080 F5E7 b .L68 + 754 .L74: + 755 0082 00BF .align 2 + 756 .L73: + ARM GAS /tmp/ccuaURzG.s page 22 + + + 757 0084 00380240 .word 1073887232 + 758 0088 00700040 .word 1073770496 + 759 008c 00010C00 .word 786688 + 760 0090 FCF3FFFF .word -3076 + 761 0094 00ED00E0 .word -536810240 + 762 .cfi_endproc + 763 .LFE151: + 765 .section .text.HAL_PWREx_GetVoltageRange,"ax",%progbits + 766 .align 1 + 767 .global HAL_PWREx_GetVoltageRange + 768 .syntax unified + 769 .thumb + 770 .thumb_func + 772 HAL_PWREx_GetVoltageRange: + 773 .LFB152: + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @brief Returns Voltage Scaling Range. + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1 + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetVoltageRange(void) + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 774 .loc 1 445 1 view -0 + 775 .cfi_startproc + 776 @ args = 0, pretend = 0, frame = 0 + 777 @ frame_needed = 0, uses_anonymous_args = 0 + 778 @ link register save eliminated. + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** return (PWR->CR1 & PWR_CR1_VOS); + 779 .loc 1 446 3 view .LVU185 + 780 .loc 1 446 15 is_stmt 0 view .LVU186 + 781 0000 024B ldr r3, .L76 + 782 0002 1868 ldr r0, [r3] + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 783 .loc 1 447 1 view .LVU187 + 784 0004 00F44040 and r0, r0, #49152 + 785 0008 7047 bx lr + 786 .L77: + 787 000a 00BF .align 2 + 788 .L76: + 789 000c 00700040 .word 1073770496 + 790 .cfi_endproc + 791 .LFE152: + 793 .section .text.HAL_PWREx_ControlVoltageScaling,"ax",%progbits + 794 .align 1 + 795 .global HAL_PWREx_ControlVoltageScaling + 796 .syntax unified + 797 .thumb + 798 .thumb_func + 800 HAL_PWREx_ControlVoltageScaling: + 801 .LVL39: + 802 .LFB153: + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /** + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @brief Configures the main internal regulator output voltage. + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @param VoltageScaling specifies the regulator output voltage to achieve + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * a tradeoff between performance and power consumption. + ARM GAS /tmp/ccuaURzG.s page 23 + + + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * This parameter can be one of the following values: + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * typical output voltage at 1.4 V, + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * system frequency up to 216 MHz. + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * typical output voltage at 1.2 V, + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * system frequency up to 180 MHz. + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode, + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * typical output voltage at 1.00 V, + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * system frequency up to 151 MHz. + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @note To update the system clock frequency(SYSCLK): + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig(). + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * - Call the HAL_RCC_OscConfig() to configure the PLL. + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale. + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * - Set the new system clock frequency using the HAL_RCC_ClockConfig(). + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @note The scale can be modified only when the HSI or HSE clock source is selected + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * as system clock source, otherwise the API returns HAL_ERROR. + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * value in the PWR_CR1 register are not taken in account. + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @note The new voltage scale is active only when the PLL is ON. + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** * @retval HAL Status + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** */ + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 803 .loc 1 477 1 is_stmt 1 view -0 + 804 .cfi_startproc + 805 @ args = 0, pretend = 0, frame = 8 + 806 @ frame_needed = 0, uses_anonymous_args = 0 + 807 .loc 1 477 1 is_stmt 0 view .LVU189 + 808 0000 30B5 push {r4, r5, lr} + 809 .LCFI14: + 810 .cfi_def_cfa_offset 12 + 811 .cfi_offset 4, -12 + 812 .cfi_offset 5, -8 + 813 .cfi_offset 14, -4 + 814 0002 83B0 sub sp, sp, #12 + 815 .LCFI15: + 816 .cfi_def_cfa_offset 24 + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** uint32_t tickstart = 0; + 817 .loc 1 478 3 is_stmt 1 view .LVU190 + 818 .LVL40: + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling)); + 819 .loc 1 480 3 view .LVU191 + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Enable Power ctrl clock */ + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 820 .loc 1 483 3 view .LVU192 + 821 .LBB5: + 822 .loc 1 483 3 view .LVU193 + 823 .loc 1 483 3 view .LVU194 + 824 0004 2C4B ldr r3, .L94 + 825 0006 1A6C ldr r2, [r3, #64] + 826 0008 42F08052 orr r2, r2, #268435456 + 827 000c 1A64 str r2, [r3, #64] + 828 .loc 1 483 3 view .LVU195 + ARM GAS /tmp/ccuaURzG.s page 24 + + + 829 000e 1A6C ldr r2, [r3, #64] + 830 0010 02F08052 and r2, r2, #268435456 + 831 0014 0092 str r2, [sp] + 832 .loc 1 483 3 view .LVU196 + 833 0016 009A ldr r2, [sp] + 834 .LBE5: + 835 .loc 1 483 3 view .LVU197 + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Check if the PLL is used as system clock or not */ + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + 836 .loc 1 486 3 view .LVU198 + 837 .loc 1 486 6 is_stmt 0 view .LVU199 + 838 0018 9B68 ldr r3, [r3, #8] + 839 001a 03F00C03 and r3, r3, #12 + 840 .loc 1 486 5 view .LVU200 + 841 001e 082B cmp r3, #8 + 842 0020 46D0 beq .L86 + 843 0022 0546 mov r5, r0 + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Disable the main PLL */ + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** __HAL_RCC_PLL_DISABLE(); + 844 .loc 1 489 5 is_stmt 1 view .LVU201 + 845 0024 244A ldr r2, .L94 + 846 0026 1368 ldr r3, [r2] + 847 0028 23F08073 bic r3, r3, #16777216 + 848 002c 1360 str r3, [r2] + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Get Start Tick */ + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick(); + 849 .loc 1 492 5 view .LVU202 + 850 .loc 1 492 17 is_stmt 0 view .LVU203 + 851 002e FFF7FEFF bl HAL_GetTick + 852 .LVL41: + 853 .loc 1 492 17 view .LVU204 + 854 0032 0446 mov r4, r0 + 855 .LVL42: + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Wait till PLL is disabled */ + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 856 .loc 1 494 5 is_stmt 1 view .LVU205 + 857 .L80: + 858 .loc 1 494 47 view .LVU206 + 859 .loc 1 494 11 is_stmt 0 view .LVU207 + 860 0034 204B ldr r3, .L94 + 861 0036 1B68 ldr r3, [r3] + 862 .loc 1 494 47 view .LVU208 + 863 0038 13F0007F tst r3, #33554432 + 864 003c 06D0 beq .L91 + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 865 .loc 1 496 7 is_stmt 1 view .LVU209 + 866 .loc 1 496 11 is_stmt 0 view .LVU210 + 867 003e FFF7FEFF bl HAL_GetTick + 868 .LVL43: + 869 .loc 1 496 25 discriminator 1 view .LVU211 + 870 0042 031B subs r3, r0, r4 + 871 .loc 1 496 9 discriminator 1 view .LVU212 + 872 0044 022B cmp r3, #2 + ARM GAS /tmp/ccuaURzG.s page 25 + + + 873 0046 F5D9 bls .L80 + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** return HAL_TIMEOUT; + 874 .loc 1 498 16 view .LVU213 + 875 0048 0320 movs r0, #3 + 876 004a 32E0 b .L79 + 877 .L91: + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Set Range */ + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); + 878 .loc 1 503 5 is_stmt 1 view .LVU214 + 879 .LBB6: + 880 .loc 1 503 5 view .LVU215 + 881 .loc 1 503 5 view .LVU216 + 882 004c 1B4A ldr r2, .L94+4 + 883 004e 1368 ldr r3, [r2] + 884 0050 23F44043 bic r3, r3, #49152 + 885 0054 2B43 orrs r3, r3, r5 + 886 0056 1360 str r3, [r2] + 887 .loc 1 503 5 view .LVU217 + 888 0058 1368 ldr r3, [r2] + 889 005a 03F44043 and r3, r3, #49152 + 890 005e 0193 str r3, [sp, #4] + 891 .loc 1 503 5 view .LVU218 + 892 0060 019B ldr r3, [sp, #4] + 893 .LBE6: + 894 .loc 1 503 5 view .LVU219 + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Enable the main PLL */ + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** __HAL_RCC_PLL_ENABLE(); + 895 .loc 1 506 5 view .LVU220 + 896 0062 02F5E432 add r2, r2, #116736 + 897 0066 1368 ldr r3, [r2] + 898 0068 43F08073 orr r3, r3, #16777216 + 899 006c 1360 str r3, [r2] + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Get Start Tick */ + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick(); + 900 .loc 1 509 5 view .LVU221 + 901 .loc 1 509 17 is_stmt 0 view .LVU222 + 902 006e FFF7FEFF bl HAL_GetTick + 903 .LVL44: + 904 0072 0446 mov r4, r0 + 905 .LVL45: + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Wait till PLL is ready */ + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 906 .loc 1 511 5 is_stmt 1 view .LVU223 + 907 .L82: + 908 .loc 1 511 47 view .LVU224 + 909 .loc 1 511 11 is_stmt 0 view .LVU225 + 910 0074 104B ldr r3, .L94 + 911 0076 1B68 ldr r3, [r3] + 912 .loc 1 511 47 view .LVU226 + 913 0078 13F0007F tst r3, #33554432 + 914 007c 06D1 bne .L92 + ARM GAS /tmp/ccuaURzG.s page 26 + + + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 915 .loc 1 513 7 is_stmt 1 view .LVU227 + 916 .loc 1 513 11 is_stmt 0 view .LVU228 + 917 007e FFF7FEFF bl HAL_GetTick + 918 .LVL46: + 919 .loc 1 513 25 discriminator 1 view .LVU229 + 920 0082 001B subs r0, r0, r4 + 921 .loc 1 513 9 discriminator 1 view .LVU230 + 922 0084 0228 cmp r0, #2 + 923 0086 F5D9 bls .L82 + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** return HAL_TIMEOUT; + 924 .loc 1 515 16 view .LVU231 + 925 0088 0320 movs r0, #3 + 926 008a 12E0 b .L79 + 927 .L92: + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** /* Get Start Tick */ + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** tickstart = HAL_GetTick(); + 928 .loc 1 520 5 is_stmt 1 view .LVU232 + 929 .loc 1 520 17 is_stmt 0 view .LVU233 + 930 008c FFF7FEFF bl HAL_GetTick + 931 .LVL47: + 932 0090 0446 mov r4, r0 + 933 .LVL48: + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) + 934 .loc 1 521 5 is_stmt 1 view .LVU234 + 935 .L84: + 936 .loc 1 521 48 view .LVU235 + 937 .loc 1 521 12 is_stmt 0 view .LVU236 + 938 0092 0A4B ldr r3, .L94+4 + 939 0094 5B68 ldr r3, [r3, #4] + 940 .loc 1 521 48 view .LVU237 + 941 0096 13F4804F tst r3, #16384 + 942 009a 07D1 bne .L93 + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) + 943 .loc 1 523 7 is_stmt 1 view .LVU238 + 944 .loc 1 523 11 is_stmt 0 view .LVU239 + 945 009c FFF7FEFF bl HAL_GetTick + 946 .LVL49: + 947 .loc 1 523 25 discriminator 1 view .LVU240 + 948 00a0 001B subs r0, r0, r4 + 949 .loc 1 523 9 discriminator 1 view .LVU241 + 950 00a2 B0F57A7F cmp r0, #1000 + 951 00a6 F4D9 bls .L84 + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** return HAL_TIMEOUT; + 952 .loc 1 525 16 view .LVU242 + 953 00a8 0320 movs r0, #3 + 954 00aa 02E0 b .L79 + 955 .L93: + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + ARM GAS /tmp/ccuaURzG.s page 27 + + + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** else + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** { + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** return HAL_ERROR; + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** return HAL_OK; + 956 .loc 1 533 10 view .LVU243 + 957 00ac 0020 movs r0, #0 + 958 00ae 00E0 b .L79 + 959 .LVL50: + 960 .L86: + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 961 .loc 1 531 12 view .LVU244 + 962 00b0 0120 movs r0, #1 + 963 .LVL51: + 964 .L79: + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c **** } + 965 .loc 1 534 1 view .LVU245 + 966 00b2 03B0 add sp, sp, #12 + 967 .LCFI16: + 968 .cfi_def_cfa_offset 12 + 969 @ sp needed + 970 00b4 30BD pop {r4, r5, pc} + 971 .L95: + 972 00b6 00BF .align 2 + 973 .L94: + 974 00b8 00380240 .word 1073887232 + 975 00bc 00700040 .word 1073770496 + 976 .cfi_endproc + 977 .LFE153: + 979 .text + 980 .Letext0: + 981 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 982 .file 3 "Drivers/CMSIS/Include/core_cm7.h" + 983 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 984 .file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + 985 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 986 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h" + ARM GAS /tmp/ccuaURzG.s page 28 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_pwr_ex.c + /tmp/ccuaURzG.s:20 .text.HAL_PWREx_EnableBkUpReg:00000000 $t + /tmp/ccuaURzG.s:26 .text.HAL_PWREx_EnableBkUpReg:00000000 HAL_PWREx_EnableBkUpReg + /tmp/ccuaURzG.s:90 .text.HAL_PWREx_EnableBkUpReg:00000038 $d + /tmp/ccuaURzG.s:95 .text.HAL_PWREx_DisableBkUpReg:00000000 $t + /tmp/ccuaURzG.s:101 .text.HAL_PWREx_DisableBkUpReg:00000000 HAL_PWREx_DisableBkUpReg + /tmp/ccuaURzG.s:165 .text.HAL_PWREx_DisableBkUpReg:00000038 $d + /tmp/ccuaURzG.s:170 .text.HAL_PWREx_EnableFlashPowerDown:00000000 $t + /tmp/ccuaURzG.s:176 .text.HAL_PWREx_EnableFlashPowerDown:00000000 HAL_PWREx_EnableFlashPowerDown + /tmp/ccuaURzG.s:195 .text.HAL_PWREx_EnableFlashPowerDown:0000000c $d + /tmp/ccuaURzG.s:200 .text.HAL_PWREx_DisableFlashPowerDown:00000000 $t + /tmp/ccuaURzG.s:206 .text.HAL_PWREx_DisableFlashPowerDown:00000000 HAL_PWREx_DisableFlashPowerDown + /tmp/ccuaURzG.s:225 .text.HAL_PWREx_DisableFlashPowerDown:0000000c $d + /tmp/ccuaURzG.s:230 .text.HAL_PWREx_EnableMainRegulatorLowVoltage:00000000 $t + /tmp/ccuaURzG.s:236 .text.HAL_PWREx_EnableMainRegulatorLowVoltage:00000000 HAL_PWREx_EnableMainRegulatorLowVoltage + /tmp/ccuaURzG.s:255 .text.HAL_PWREx_EnableMainRegulatorLowVoltage:0000000c $d + /tmp/ccuaURzG.s:260 .text.HAL_PWREx_DisableMainRegulatorLowVoltage:00000000 $t + /tmp/ccuaURzG.s:266 .text.HAL_PWREx_DisableMainRegulatorLowVoltage:00000000 HAL_PWREx_DisableMainRegulatorLowVoltage + /tmp/ccuaURzG.s:285 .text.HAL_PWREx_DisableMainRegulatorLowVoltage:0000000c $d + /tmp/ccuaURzG.s:290 .text.HAL_PWREx_EnableLowRegulatorLowVoltage:00000000 $t + /tmp/ccuaURzG.s:296 .text.HAL_PWREx_EnableLowRegulatorLowVoltage:00000000 HAL_PWREx_EnableLowRegulatorLowVoltage + /tmp/ccuaURzG.s:315 .text.HAL_PWREx_EnableLowRegulatorLowVoltage:0000000c $d + /tmp/ccuaURzG.s:320 .text.HAL_PWREx_DisableLowRegulatorLowVoltage:00000000 $t + /tmp/ccuaURzG.s:326 .text.HAL_PWREx_DisableLowRegulatorLowVoltage:00000000 HAL_PWREx_DisableLowRegulatorLowVoltage + /tmp/ccuaURzG.s:345 .text.HAL_PWREx_DisableLowRegulatorLowVoltage:0000000c $d + /tmp/ccuaURzG.s:350 .text.HAL_PWREx_EnableOverDrive:00000000 $t + /tmp/ccuaURzG.s:356 .text.HAL_PWREx_EnableOverDrive:00000000 HAL_PWREx_EnableOverDrive + /tmp/ccuaURzG.s:470 .text.HAL_PWREx_EnableOverDrive:00000074 $d + /tmp/ccuaURzG.s:476 .text.HAL_PWREx_DisableOverDrive:00000000 $t + /tmp/ccuaURzG.s:482 .text.HAL_PWREx_DisableOverDrive:00000000 HAL_PWREx_DisableOverDrive + /tmp/ccuaURzG.s:592 .text.HAL_PWREx_DisableOverDrive:00000074 $d + /tmp/ccuaURzG.s:598 .text.HAL_PWREx_EnterUnderDriveSTOPMode:00000000 $t + /tmp/ccuaURzG.s:604 .text.HAL_PWREx_EnterUnderDriveSTOPMode:00000000 HAL_PWREx_EnterUnderDriveSTOPMode + /tmp/ccuaURzG.s:757 .text.HAL_PWREx_EnterUnderDriveSTOPMode:00000084 $d + /tmp/ccuaURzG.s:766 .text.HAL_PWREx_GetVoltageRange:00000000 $t + /tmp/ccuaURzG.s:772 .text.HAL_PWREx_GetVoltageRange:00000000 HAL_PWREx_GetVoltageRange + /tmp/ccuaURzG.s:789 .text.HAL_PWREx_GetVoltageRange:0000000c $d + /tmp/ccuaURzG.s:794 .text.HAL_PWREx_ControlVoltageScaling:00000000 $t + /tmp/ccuaURzG.s:800 .text.HAL_PWREx_ControlVoltageScaling:00000000 HAL_PWREx_ControlVoltageScaling + /tmp/ccuaURzG.s:974 .text.HAL_PWREx_ControlVoltageScaling:000000b8 $d + +UNDEFINED SYMBOLS +HAL_GetTick diff --git a/build/stm32f7xx_hal_pwr_ex.o b/build/stm32f7xx_hal_pwr_ex.o new file mode 100644 index 0000000000000000000000000000000000000000..9ee62bede494d0ec810d80d1d42a09c346f6fa6b GIT binary patch literal 16236 zcmd5@33MFAnXaDh8MRK!l8k(Xj4cO?L$|?(*jUm?!om_3I?R<9c_fW2ExH(uuwhMb zj3Fi`5W*D*EJs2T^5RWk$$^8Hux|+=#2i^*;{^u@I0S;hHco(q{l4nIW=3tvkhi<< zZ9TWX`v3atzv}4fp7y1UElrkXDN`&}s#26vyO-&f;1Ug`>Ns_*%D*pn^|=G}2UPsr zb;QlU4-Wn91E(ot^?3t@``j5BPmosgwjaFs(gV-gVYNqv^LMB*RqOR#c%;6&rt2Fx zy>K9MK#do!8#|4|U5TeivSe%{o}{d2d-KW+pRC{Z7~&2!*ivlYZuOy z926lg`#^2U4-eK>q{sF)M!RrN?&&iJ@>XZp)T+i)w2iGf!bP(_Jhn(<$afJKOyPk+@S!*NnN9E z`uc#qFUNL|Z`u`XTEscAZ}YertMKZ1n33wzkj{ZUFL3-pcv!t>o}N3kk>lZEAtQ-! zqyqz{A>%UB0W*}q_qH{Y|onXo231Dx*x%y+fN3ftQ&ccjMn{Vb&ddL22| zcO0d1&cL6AnlbrLz|FWAoPd*YKh|Qva?iI3p=Zbp1hhK)|fa_~b=aBw7{GVTf3|88YI52fz)XtjS~6w(?p5NrGf4l^(5}0b^kat3$?S-NXX(3Ng8>8B07#2rLR?B5uAnVU;{|6%Cm z?vEJXGgg7iw3O7k8z}#*iFcLTh&0;I8M?*2hW`DhRj^RYx4C)r=eJe?(-$aN=l+HE zcUuK@nohV^Q~!UN{u?tRorwQ=LvM1oQ2qsvwo5i!?sht`$8*pw*=o7-XyJE;vCVRe z>B5Uv!I>~&mweH3e?=c(G7_5|cL60{whE$JVyol6N-MuNR(3k>8)Up<7!Nz{ellJ) zj7J>zc~Y+Osq{~V@v`GyPsW>uvDb0G!Wi}$#_NuIDRsPM82cReF?M;|Fb+8GN=odv3NFy$ z|JiZt8QcLQaaGX0ml-=~7}o~f?UZ=OFm4FC-=)$+hH-Py#Y$E7pAF--pxaCoO{WXPRlL;C?V2GIYzwOpC38oU0BQx@D

E1$n z?-_cD`!wa>H#Bw|(tkDfmb+i0{NGG_t^0Gfe_-eay|f)=i@jCugUp&`OWNDqZ_?j@ zp*!6h+21zw*?QqSjxF(h%0+kO1Wo%oH_HAYL-*-L?qnEy1Mc^kPuH}MWkx!X?@U7{ z^pbb7jQmFTvy{*F+V$?Wm<&>_)#S?JR z9mu`)yp==dmvCKzYZmmV*|`1$D@XAVZM|gKdeK}xpk}q8r3Y6IlzOd)Ebsn%^^hvA zM#~2DE3P*cs@9w>rgD|3+$I$@+j*5E4qxyL+{hlcaO=)zTWAA{ZG1$!eHUm{ay;1Z9?W6Zl?&f=V#k858t z#;qm;=`l7zgrTVd>lXaAD$|_Y1jcdDXZ<6b^sH2SRyKk=f-9NlwUF>Kxx`pWsN!Qp zdGSf6(rzj}Qi0vq8EC*~_eZq5KWW$T?1m8j`{{NcPudOrop$F~pQGKkLr7L?sODHZ zX?U-n`wFD2=l$H>9F3>_T$i$s`nji&yK^#kuJsvm??}z}w*(wrLFyfblO=Yf#oq>l1l}*>>K%yspqptKG`S zN((Gf+1aOpiDi3~vhz;K{$%#a+0BL66i!rx;4vCPB8Q2VQD|icAs0M3+k$|b>vaR! zT(}GoWrE>)?H(h`vYHDin!NzJDzdRA#gy)YdlWQgr!?j{)~VUq(B?VAo-;~eWIlT4 zqvEnMvs|srG5#*jX)auzgZW)<2@{&hoQZW=8@j$ehe`^AX`Ti`_tzu-q9up(W@RH) z1s1y;HK`fF6<@i09PNhJGB@d>Zt=M|PweS25Eti9 z+XIt>1(O-qB^tRWqMk#%*Q?Ja?)2(#?eJ0smZjPV+jX^z@B@!a*oiAk?Y9rAV-Hmx zQn!NCh4VV?QZ&jp6#-RwE0Grz6B4@GN${#|gljx5!K=0rJSRGh6VwK7vP=SQs< z>B3_A@6=T4kFjIW$bD2ab_^cLUMcR{wpxL-2dwwkcrbab}X zR5vZ%xUqXxT}!vet>}pNs)~v6c*W3QPsRG)-il~^xNKx}BvuxS_6$~3)s$D4S5*v- z^bSq*#gtJMY3*q4sA!&&+Yq~Our~&4DT9YePU#BNDK(xLuBq;)lLOJA?y(K=?%2li zUdAz==)>Ee@&QaH)jJxGb@vW01%+F;^f?K=z`#07D)Et8XJ4!zY@{nGMYhLMK|Jwt z(klB3%L>{HW(7kbE0|jzv_rLCHH_-Y;0$ny$63KlRF5kU21BRnYBAncS>?eDLO7Ur zYA~xRXe|f_0vM8%_B;MhweO_%BJFQZdC*!BuqPRR^vKOmAG!JYBRB6oa`W3qZr&1r z=M_bkb@u7uS?5WbkytC3g*0a#AlF$_%2?QayG3loK-l>i#${wTG`6zIq^yue(=JnjoYD`V7BgFDOe>~63o&3 z5;G4tUxOhlbW+ex<6(kA%vyjZd!jtRog+0(AF$zAp&kaSA`qI?w%hjHt|$_xwVmMd z(8}|IGwFFSv@lpTg9Ah15@=p1i-WP0l(zY=0Kmer5p9%MI=r+&mg(F-t6JI`&uCY5tLi)O#+UnHeOJdhsv*+cy0$K&Dh5V}V-@|e zzGy{jb6aOcd$ezGv~6HCF*-8X+ubqIGaifgM|)%4@n~N(UU6D%Bo>b*M&sRWk$Rsn zINjr;{fQ0HcuWnAj;s&sKNBP4gX>3PePO=Qj$-4N19H> zKzP$s*W3!9PB;cOLpJr1hT3k?1Z^#l&q?6gEdauDMtaZOcht_+NSnO#lKbhZ?&TF_O*=- zmC0IFvX*MCN%EE?YbPdaCnal3leJ}O$@V6O8PjA!^{nhz#W!{wGCj~<&N;y_HCnxy zUE}2~fs~9VqH#27;VzYkd6O1P6ywbd%L1;^IYG8+$Y4s-XXtc;J^`~e)!mre%r$#8 zwzp#*r20ojM-uVTA(~;)RBhct6fJvyojnK zA{|-Bs;BEbFT}iR92|G*O0=+zRXpePBf6y#p(7#=CH7tZexB{;~4Dv2fXX{OiL8)n8T} zE?Wbtzb~4ImW{`H6N958@vf0R*}ytF*R-{c z;uzV{5y38zO0{eR)6C=g1}-~q#c|k{VbrJ!+T$0YhL`RsRaj0kV(rlpEbdf`H!)MY zDe|uqjzF3_u#ENcjI?pXS;aYlsanN9)yg*o)M=5(DdEzp6Hn2@5|0g4l~o_>A0r+j z`R?EY6ub=Hl$VpMipZ40hl091cWdCw*0lWecMp7M_}`}I8)txg$Pj<(^76a0^4z-Y z4{Hyn_2 zPxA08K3QkQ#skIdNgPMb1HCNCt43X z^vP%XF7`{eN|F|F8`m6PRjeDbMC*v(eCKKWdq zd~TX{%IEpy^R#>-DTNoYX~o9l_+)?bee&k<+v{Yj0-t<=mfxDxS&*!;Vq>*V)?eiF zKYf)`ewI&umX`lfQtPZ_&C_4(qv!Z&zCB45TmPJqP9L2jP_tFoM=$izi+ps6k3L3G zBUjCGTm@JU{N2J7X0skwsy(F66Pj%WnBNyqqBGS^ljtn<&?Gur{c#eVgC9dY{hq#D zrGGSl4EL-8%#TiK_vm~zD)bGyy+B<(seh5;ujlxu-_jOfd?vpNNZq0rCDfw6!)_tw zY{OfNIlZNBGrmJ@s$t3#bE;YT`A*cScCY(%$C;Fz==pF#PvJE8+{5&JsGR@ydYFdP zoj27q-2ovbG5!5~>hqbtmuBHNS-Xpj}@NvNx1osJAxb5qB1xo~%2sR3?6-O1)mUnQE!Ka9@`;6coBK&+y=ywH!IA)SxKnx>p!MQ~E zxk%b8g_j%&Sl=`yZHAL9ES=#Rw`X0f5CPMx` z!JiSK=hs3%EBHIX*8~p|A@^4zj$9Uw$;50T_=Ut`{Jbr=K={WJanmUiTq^vPL~QmE z!B*jS5%ZKfN3d7;=M!<%9u>Su_?Htg23HDxiHP{Gm-gF*{-)q}iIBfn@IfN{|0NN7 zz^?_LB0|q|(*Cm0dj;PhLjD~=+$QvV$F`-Br+m(Tp3#UrBNOKfE)pyitQBk!TrH^Y zW9X;vW59ET9~F!V@|z~=zgqA{L4K}7{+)t%3w~elhk`#5{F>3I0NGm*CTazZHBz zke?}Wo$MEUPmm9rGco$7#h8gl@hVf;b^P(!DU43leI+bqpOJ6U)zYt$JxZNQtOB%-gh6o zPmYns`evd3djA2!l#XBTLm;#t*gtvx=RT_afqlIn0mI~DKi2yaQ2PgAeclFYKjGIB z$^o^%@NYS3U@Z}T>ir9-{SPbELOxK(0lzy*19d#`|5K!a>xhV>Pq2mS3vqmh2>)Hq zBlyivR+%@wF5qX3H2l-^9e&+G8vZ;)q(3$=?0wTlyZri^_J)bDhpsAshY6hz*wgWX z*73rwjt8`k2llo9ptb+-L;DMQfO_ChLiBAU(l4R65#ispLf=4ypLYsZg0Z)RCX@{n8)ur0*9$;`6>=SaeVG)IU|0 z{LlYW$%xj}n}Df=rh6ygchUc5U@Bcxza!9+eX*X2_1%Lb{iB#6x*qN6iN`MVCW*%x z8tqLdqjCPEAk)Z`IGlrDiDE`0=AkO@9UUHy;di1mtNrolFof#bTg#(~M0~JkA_27@ zz089sroReFmnFWg*a~!6fWMTpJyP#wQq{mVmc_VSTpuRKJ;HC7`=Ke0RJf;P;;I!o zTh7i8ld$dj4vWzc7S29@x^8 z`McStZ`(BbZt&?_m!^+-G~@BFK7BkZ@;+dS@o$Gu-{!ROEr77m_XnT8o1t&2amxiC zqRI8acR)LhQPD>-6a4hNTm`$8;4?3LA7||He+^QfDLiZ8XOd(wZ8bi9JE89pOi=2> ztuU!C;@5{k_>EBlIaBTO$<-m)SIi$iBzHy&E7aP_t2vOhBxQssjw-?igI*Ks}C*X`? zifOytr|((l8-Nh?g>e~u{Qo!XQ;CZuf@G{Tn}$o)4i0^ZdC literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_hal_rcc.d b/build/stm32f7xx_hal_rcc.d new file mode 100644 index 0000000..5c669ec --- /dev/null +++ b/build/stm32f7xx_hal_rcc.d @@ -0,0 +1,68 @@ +build/stm32f7xx_hal_rcc.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/build/stm32f7xx_hal_rcc.lst b/build/stm32f7xx_hal_rcc.lst new file mode 100644 index 0000000..2fc710f --- /dev/null +++ b/build/stm32f7xx_hal_rcc.lst @@ -0,0 +1,5244 @@ +ARM GAS /tmp/ccemvyj9.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_hal_rcc.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c" + 19 .section .text.HAL_RCC_DeInit,"ax",%progbits + 20 .align 1 + 21 .global HAL_RCC_DeInit + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 HAL_RCC_DeInit: + 27 .LFB141: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @file stm32f7xx_hal_rcc.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief RCC HAL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * functionalities of the Reset and Clock Control (RCC) peripheral: + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * + Peripheral Control functions + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** @verbatim + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ============================================================================== + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ##### RCC specific features ##### + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ============================================================================== + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** [..] + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** After reset the device is running from Internal High Speed oscillator + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** and I-Cache are disabled, and all peripherals are off except internal + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** SRAM, Flash and JTAG. + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** all peripherals mapped on these buses are running at HSI speed. + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) All GPIOs are in input floating state, except the JTAG pins which + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** are assigned to be used for debug purpose. + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** [..] + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** Once the device started from reset, the user application has to: + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) Configure the clock source to be used to drive the System clock + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (if the application needs higher frequency/performance) + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) Configure the System clock frequency and Flash settings + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) Configure the AHB and APB buses prescalers + ARM GAS /tmp/ccemvyj9.s page 2 + + + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) Enable the clock for the peripheral(s) to be used + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) Configure the clock source(s) for peripherals which clocks are not + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ##### RCC Limitations ##### + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ============================================================================== + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** [..] + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** A delay between an RCC peripheral clock enable and the effective peripheral + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** enabling should be taken into account in order to manage the peripheral read/write + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** from/to registers. + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) This delay depends on the peripheral mapping. + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** after the clock enable bit is set on the hardware register + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** after the clock enable bit is set on the hardware register + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** [..] + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** Implemented Workaround: + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+) For AHB & APB peripherals, a dummy read to the peripheral register has been + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** @endverbatim + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ****************************************************************************** + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @attention + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * Copyright (c) 2017 STMicroelectronics. + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * All rights reserved. + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * This software is licensed under terms that can be found in the LICENSE file in + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * the root directory of this software component. + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ****************************************************************************** + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Includes ------------------------------------------------------------------*/ + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #include "stm32f7xx_hal.h" + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @addtogroup STM32F7xx_HAL_Driver + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @{ + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @defgroup RCC RCC + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief RCC HAL module driver + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @{ + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #ifdef HAL_RCC_MODULE_ENABLED + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Private typedef -----------------------------------------------------------*/ + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Private define ------------------------------------------------------------*/ + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Private macro -------------------------------------------------------------*/ + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @defgroup RCC_Private_Macros RCC Private Macros + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @{ + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #define MCO1_GPIO_PORT GPIOA + ARM GAS /tmp/ccemvyj9.s page 3 + + + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #define MCO1_PIN GPIO_PIN_8 + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #define MCO2_GPIO_PORT GPIOC + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #define MCO2_PIN GPIO_PIN_9 + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @} + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Private variables ---------------------------------------------------------*/ + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @defgroup RCC_Private_Variables RCC Private Variables + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @{ + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @} + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Private function prototypes -----------------------------------------------*/ + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Exported functions ---------------------------------------------------------*/ + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions RCC Exported Functions + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @{ + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Initialization and Configuration functions + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** @verbatim + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** =============================================================================== + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ##### Initialization and de-initialization functions ##### + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** =============================================================================== + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** [..] + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** This section provides functions allowing to configure the internal/external oscillators + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** and APB2). + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** [..] Internal/external clock and PLL configuration + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** the PLL as System clock source. + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** clock source. + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** through the PLL as System clock source. Can be used also as RTC clock source. + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (#) PLL (clocked by HSI or HSE), featuring two different output clocks: + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (++) The first output is used to generate the high speed system clock (up to 216 MHz) + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS() + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** and if a HSE clock failure occurs(HSE used directly or through PLL as System + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** clock source), the System clock is automatically switched to HSI and an interrupt + ARM GAS /tmp/ccemvyj9.s page 4 + + + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** is generated if enabled. The interrupt is linked to the Cortex-M7 NMI + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (Non-Maskable Interrupt) exception vector. + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** clock (through a configurable prescaler) on PA8 pin. + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** clock (through a configurable prescaler) on PC9 pin. + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** [..] System, AHB and APB buses clocks configuration + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HSE and PLL. + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** The AHB clock (HCLK) is derived from System clock through configurable + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** prescaler and used to clock the CPU, memory and peripherals mapped + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** from AHB clock through configurable prescalers and used to clock + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** the peripherals mapped on these buses. You can use + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** from an external clock mapped on the I2S_CKIN pin. + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) o + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** from an external clock mapped on the I2S_CKIN pin. + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE() + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** macros to configure this clock. + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** to work correctly, while the SDIO require a frequency equal or lower than + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** to 48. This clock is derived of the main PLL through PLLQ divider. + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (+@) IWDG clock which is always the LSI clock. + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** @endverbatim + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @{ + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Resets the RCC clock configuration to the default reset state. + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note The default reset state of the clock configuration is given below: + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * - HSI ON and used as system clock source + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * - HSE, PLL, PLLI2S and PLLSAI OFF + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * - AHB, APB1 and APB2 prescaler set to 1. + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * - CSS, MCO1 and MCO2 OFF + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * - All interrupts disabled + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note This function doesn't modify the configuration of the + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * - Peripheral clocks + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * - LSI, LSE and RTC clocks + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval None + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_DeInit(void) + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 28 .loc 1 197 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 0000 38B5 push {r3, r4, r5, lr} + ARM GAS /tmp/ccemvyj9.s page 5 + + + 33 .LCFI0: + 34 .cfi_def_cfa_offset 16 + 35 .cfi_offset 3, -16 + 36 .cfi_offset 4, -12 + 37 .cfi_offset 5, -8 + 38 .cfi_offset 14, -4 + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t tickstart; + 39 .loc 1 198 3 view .LVU1 + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick */ + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 40 .loc 1 201 3 view .LVU2 + 41 .loc 1 201 15 is_stmt 0 view .LVU3 + 42 0002 FFF7FEFF bl HAL_GetTick + 43 .LVL0: + 44 0006 0446 mov r4, r0 + 45 .LVL1: + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Set HSION bit to the reset value */ + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** SET_BIT(RCC->CR, RCC_CR_HSION); + 46 .loc 1 204 3 is_stmt 1 view .LVU4 + 47 0008 4E4A ldr r2, .L28 + 48 000a 1368 ldr r3, [r2] + 49 000c 43F00103 orr r3, r3, #1 + 50 0010 1360 str r3, [r2] + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till HSI is ready */ + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + 51 .loc 1 207 3 view .LVU5 + 52 .LVL2: + 53 .L2: + 54 .loc 1 207 43 view .LVU6 + 55 .loc 1 207 10 is_stmt 0 view .LVU7 + 56 0012 4C4B ldr r3, .L28 + 57 0014 1B68 ldr r3, [r3] + 58 .loc 1 207 43 view .LVU8 + 59 0016 13F0020F tst r3, #2 + 60 001a 06D1 bne .L22 + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 61 .loc 1 209 5 is_stmt 1 view .LVU9 + 62 .loc 1 209 10 is_stmt 0 view .LVU10 + 63 001c FFF7FEFF bl HAL_GetTick + 64 .LVL3: + 65 .loc 1 209 24 discriminator 1 view .LVU11 + 66 0020 001B subs r0, r0, r4 + 67 .loc 1 209 8 discriminator 1 view .LVU12 + 68 0022 0228 cmp r0, #2 + 69 0024 F5D9 bls .L2 + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; + 70 .loc 1 211 14 view .LVU13 + 71 0026 0320 movs r0, #3 + 72 .L3: + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + ARM GAS /tmp/ccemvyj9.s page 6 + + + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Set HSITRIM[4:0] bits to the reset value */ + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** SET_BIT(RCC->CR, RCC_CR_HSITRIM_4); + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick */ + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Reset CFGR register */ + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** CLEAR_REG(RCC->CFGR); + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till clock switch is ready */ + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick */ + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Clear HSEON, HSEBYP and CSSON bits */ + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON); + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till HSE is disabled */ + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick */ + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Clear PLLON bit */ + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till PLL is disabled */ + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick */ + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Reset PLLI2SON bit */ + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till PLLI2S is disabled */ + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + ARM GAS /tmp/ccemvyj9.s page 7 + + + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick */ + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Reset PLLSAI bit */ + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till PLLSAI is disabled */ + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET) + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */ + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Reset PLLI2SCFGR register to default value */ + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Reset PLLSAICFGR register to default value */ + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Disable all interrupts */ + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | R + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Clear all interrupt flags */ + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Clear LSION bit */ + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Reset all CSR flags */ + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** SET_BIT(RCC->CSR, RCC_CSR_RMVF); + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Update the SystemCoreClock global variable */ + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** SystemCoreClock = HSI_VALUE; + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Adapt Systick interrupt period */ + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (HAL_InitTick(uwTickPrio) != HAL_OK) + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_OK; + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 73 .loc 1 326 1 view .LVU14 + 74 0028 38BD pop {r3, r4, r5, pc} + ARM GAS /tmp/ccemvyj9.s page 8 + + + 75 .LVL4: + 76 .L22: + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 77 .loc 1 216 3 is_stmt 1 view .LVU15 + 78 002a 464D ldr r5, .L28 + 79 002c 2B68 ldr r3, [r5] + 80 002e 43F08003 orr r3, r3, #128 + 81 0032 2B60 str r3, [r5] + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 82 .loc 1 219 3 view .LVU16 + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 83 .loc 1 219 15 is_stmt 0 view .LVU17 + 84 0034 FFF7FEFF bl HAL_GetTick + 85 .LVL5: + 86 0038 0446 mov r4, r0 + 87 .LVL6: + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 88 .loc 1 222 3 is_stmt 1 view .LVU18 + 89 003a 0023 movs r3, #0 + 90 003c AB60 str r3, [r5, #8] + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 91 .loc 1 225 3 view .LVU19 + 92 .LVL7: + 93 .L5: + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 94 .loc 1 225 44 view .LVU20 + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 95 .loc 1 225 10 is_stmt 0 view .LVU21 + 96 003e 414B ldr r3, .L28 + 97 0040 9B68 ldr r3, [r3, #8] + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 98 .loc 1 225 44 view .LVU22 + 99 0042 13F00C0F tst r3, #12 + 100 0046 08D0 beq .L23 + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 101 .loc 1 227 5 is_stmt 1 view .LVU23 + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 102 .loc 1 227 10 is_stmt 0 view .LVU24 + 103 0048 FFF7FEFF bl HAL_GetTick + 104 .LVL8: + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 105 .loc 1 227 24 discriminator 1 view .LVU25 + 106 004c 001B subs r0, r0, r4 + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 107 .loc 1 227 8 discriminator 1 view .LVU26 + 108 004e 41F28833 movw r3, #5000 + 109 0052 9842 cmp r0, r3 + 110 0054 F3D9 bls .L5 + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 111 .loc 1 229 14 view .LVU27 + 112 0056 0320 movs r0, #3 + 113 0058 E6E7 b .L3 + 114 .L23: + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 115 .loc 1 234 3 is_stmt 1 view .LVU28 + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 116 .loc 1 234 15 is_stmt 0 view .LVU29 + ARM GAS /tmp/ccemvyj9.s page 9 + + + 117 005a FFF7FEFF bl HAL_GetTick + 118 .LVL9: + 119 005e 0446 mov r4, r0 + 120 .LVL10: + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 121 .loc 1 237 3 is_stmt 1 view .LVU30 + 122 0060 384A ldr r2, .L28 + 123 0062 1368 ldr r3, [r2] + 124 0064 23F45023 bic r3, r3, #851968 + 125 0068 1360 str r3, [r2] + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 126 .loc 1 240 3 view .LVU31 + 127 .LVL11: + 128 .L7: + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 129 .loc 1 240 43 view .LVU32 + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 130 .loc 1 240 10 is_stmt 0 view .LVU33 + 131 006a 364B ldr r3, .L28 + 132 006c 1B68 ldr r3, [r3] + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 133 .loc 1 240 43 view .LVU34 + 134 006e 13F4003F tst r3, #131072 + 135 0072 06D0 beq .L24 + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 136 .loc 1 242 5 is_stmt 1 view .LVU35 + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 137 .loc 1 242 10 is_stmt 0 view .LVU36 + 138 0074 FFF7FEFF bl HAL_GetTick + 139 .LVL12: + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 140 .loc 1 242 24 discriminator 1 view .LVU37 + 141 0078 001B subs r0, r0, r4 + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 142 .loc 1 242 8 discriminator 1 view .LVU38 + 143 007a 6428 cmp r0, #100 + 144 007c F5D9 bls .L7 + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 145 .loc 1 244 14 view .LVU39 + 146 007e 0320 movs r0, #3 + 147 0080 D2E7 b .L3 + 148 .L24: + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 149 .loc 1 249 3 is_stmt 1 view .LVU40 + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 150 .loc 1 249 15 is_stmt 0 view .LVU41 + 151 0082 FFF7FEFF bl HAL_GetTick + 152 .LVL13: + 153 0086 0446 mov r4, r0 + 154 .LVL14: + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 155 .loc 1 252 3 is_stmt 1 view .LVU42 + 156 0088 2E4A ldr r2, .L28 + 157 008a 1368 ldr r3, [r2] + 158 008c 23F08073 bic r3, r3, #16777216 + 159 0090 1360 str r3, [r2] + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + ARM GAS /tmp/ccemvyj9.s page 10 + + + 160 .loc 1 255 3 view .LVU43 + 161 .LVL15: + 162 .L9: + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 163 .loc 1 255 43 view .LVU44 + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 164 .loc 1 255 10 is_stmt 0 view .LVU45 + 165 0092 2C4B ldr r3, .L28 + 166 0094 1B68 ldr r3, [r3] + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 167 .loc 1 255 43 view .LVU46 + 168 0096 13F0007F tst r3, #33554432 + 169 009a 06D0 beq .L25 + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 170 .loc 1 257 5 is_stmt 1 view .LVU47 + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 171 .loc 1 257 10 is_stmt 0 view .LVU48 + 172 009c FFF7FEFF bl HAL_GetTick + 173 .LVL16: + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 174 .loc 1 257 24 discriminator 1 view .LVU49 + 175 00a0 001B subs r0, r0, r4 + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 176 .loc 1 257 8 discriminator 1 view .LVU50 + 177 00a2 0228 cmp r0, #2 + 178 00a4 F5D9 bls .L9 + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 179 .loc 1 259 14 view .LVU51 + 180 00a6 0320 movs r0, #3 + 181 00a8 BEE7 b .L3 + 182 .L25: + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 183 .loc 1 264 3 is_stmt 1 view .LVU52 + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 184 .loc 1 264 15 is_stmt 0 view .LVU53 + 185 00aa FFF7FEFF bl HAL_GetTick + 186 .LVL17: + 187 00ae 0446 mov r4, r0 + 188 .LVL18: + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 189 .loc 1 267 3 is_stmt 1 view .LVU54 + 190 00b0 244A ldr r2, .L28 + 191 00b2 1368 ldr r3, [r2] + 192 00b4 23F08063 bic r3, r3, #67108864 + 193 00b8 1360 str r3, [r2] + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 194 .loc 1 270 3 view .LVU55 + 195 .LVL19: + 196 .L11: + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 197 .loc 1 270 46 view .LVU56 + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 198 .loc 1 270 10 is_stmt 0 view .LVU57 + 199 00ba 224B ldr r3, .L28 + 200 00bc 1B68 ldr r3, [r3] + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 201 .loc 1 270 46 view .LVU58 + ARM GAS /tmp/ccemvyj9.s page 11 + + + 202 00be 13F0006F tst r3, #134217728 + 203 00c2 06D0 beq .L26 + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 204 .loc 1 272 5 is_stmt 1 view .LVU59 + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 205 .loc 1 272 10 is_stmt 0 view .LVU60 + 206 00c4 FFF7FEFF bl HAL_GetTick + 207 .LVL20: + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 208 .loc 1 272 24 discriminator 1 view .LVU61 + 209 00c8 001B subs r0, r0, r4 + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 210 .loc 1 272 8 discriminator 1 view .LVU62 + 211 00ca 6428 cmp r0, #100 + 212 00cc F5D9 bls .L11 + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 213 .loc 1 274 14 view .LVU63 + 214 00ce 0320 movs r0, #3 + 215 00d0 AAE7 b .L3 + 216 .L26: + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 217 .loc 1 279 3 is_stmt 1 view .LVU64 + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 218 .loc 1 279 15 is_stmt 0 view .LVU65 + 219 00d2 FFF7FEFF bl HAL_GetTick + 220 .LVL21: + 221 00d6 0446 mov r4, r0 + 222 .LVL22: + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 223 .loc 1 282 3 is_stmt 1 view .LVU66 + 224 00d8 1A4A ldr r2, .L28 + 225 00da 1368 ldr r3, [r2] + 226 00dc 23F08053 bic r3, r3, #268435456 + 227 00e0 1360 str r3, [r2] + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 228 .loc 1 285 3 view .LVU67 + 229 .LVL23: + 230 .L13: + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 231 .loc 1 285 46 view .LVU68 + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 232 .loc 1 285 10 is_stmt 0 view .LVU69 + 233 00e2 184B ldr r3, .L28 + 234 00e4 1B68 ldr r3, [r3] + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 235 .loc 1 285 46 view .LVU70 + 236 00e6 13F0005F tst r3, #536870912 + 237 00ea 06D0 beq .L27 + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 238 .loc 1 287 5 is_stmt 1 view .LVU71 + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 239 .loc 1 287 10 is_stmt 0 view .LVU72 + 240 00ec FFF7FEFF bl HAL_GetTick + 241 .LVL24: + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 242 .loc 1 287 24 discriminator 1 view .LVU73 + 243 00f0 001B subs r0, r0, r4 + ARM GAS /tmp/ccemvyj9.s page 12 + + + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 244 .loc 1 287 8 discriminator 1 view .LVU74 + 245 00f2 6428 cmp r0, #100 + 246 00f4 F5D9 bls .L13 + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 247 .loc 1 289 14 view .LVU75 + 248 00f6 0320 movs r0, #3 + 249 00f8 96E7 b .L3 + 250 .L27: + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 251 .loc 1 294 3 is_stmt 1 view .LVU76 + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 252 .loc 1 294 16 is_stmt 0 view .LVU77 + 253 00fa 124B ldr r3, .L28 + 254 00fc 124A ldr r2, .L28+4 + 255 00fe 5A60 str r2, [r3, #4] + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 256 .loc 1 297 3 is_stmt 1 view .LVU78 + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 257 .loc 1 297 19 is_stmt 0 view .LVU79 + 258 0100 103A subs r2, r2, #16 + 259 0102 C3F88420 str r2, [r3, #132] + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 260 .loc 1 300 3 is_stmt 1 view .LVU80 + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 261 .loc 1 300 19 is_stmt 0 view .LVU81 + 262 0106 C3F88820 str r2, [r3, #136] + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 263 .loc 1 303 3 is_stmt 1 view .LVU82 + 264 010a DA68 ldr r2, [r3, #12] + 265 010c 22F4FE42 bic r2, r2, #32512 + 266 0110 DA60 str r2, [r3, #12] + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 267 .loc 1 306 3 view .LVU83 + 268 0112 DA68 ldr r2, [r3, #12] + 269 0114 42F47F02 orr r2, r2, #16711680 + 270 0118 DA60 str r2, [r3, #12] + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 271 .loc 1 309 3 view .LVU84 + 272 011a 5A6F ldr r2, [r3, #116] + 273 011c 22F00102 bic r2, r2, #1 + 274 0120 5A67 str r2, [r3, #116] + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 275 .loc 1 312 3 view .LVU85 + 276 0122 5A6F ldr r2, [r3, #116] + 277 0124 42F08072 orr r2, r2, #16777216 + 278 0128 5A67 str r2, [r3, #116] + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 279 .loc 1 315 3 view .LVU86 + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 280 .loc 1 315 19 is_stmt 0 view .LVU87 + 281 012a 084B ldr r3, .L28+8 + 282 012c 084A ldr r2, .L28+12 + 283 012e 1A60 str r2, [r3] + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 284 .loc 1 318 3 is_stmt 1 view .LVU88 + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + ARM GAS /tmp/ccemvyj9.s page 13 + + + 285 .loc 1 318 7 is_stmt 0 view .LVU89 + 286 0130 084B ldr r3, .L28+16 + 287 0132 1868 ldr r0, [r3] + 288 0134 FFF7FEFF bl HAL_InitTick + 289 .LVL25: + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 290 .loc 1 318 6 discriminator 1 view .LVU90 + 291 0138 0028 cmp r0, #0 + 292 013a 3FF475AF beq .L3 + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 293 .loc 1 320 12 view .LVU91 + 294 013e 0120 movs r0, #1 + 295 0140 72E7 b .L3 + 296 .L29: + 297 0142 00BF .align 2 + 298 .L28: + 299 0144 00380240 .word 1073887232 + 300 0148 10300024 .word 603992080 + 301 014c 00000000 .word SystemCoreClock + 302 0150 0024F400 .word 16000000 + 303 0154 00000000 .word uwTickPrio + 304 .cfi_endproc + 305 .LFE141: + 307 .section .text.HAL_RCC_OscConfig,"ax",%progbits + 308 .align 1 + 309 .global HAL_RCC_OscConfig + 310 .syntax unified + 311 .thumb + 312 .thumb_func + 314 HAL_RCC_OscConfig: + 315 .LVL26: + 316 .LFB142: + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Initializes the RCC Oscillators according to the specified parameters in the + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * RCC_OscInitTypeDef. + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * contains the configuration information for the RCC Oscillators. + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note The PLL is not disabled when used as system clock. + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * supported by this function. User should request a transition to LSE Off + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * first and then LSE On or LSE Bypass. + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * supported by this function. User should request a transition to HSE Off + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * first and then HSE On or HSE Bypass. + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval HAL status + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 317 .loc 1 343 1 is_stmt 1 view -0 + 318 .cfi_startproc + 319 @ args = 0, pretend = 0, frame = 8 + 320 @ frame_needed = 0, uses_anonymous_args = 0 + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t tickstart; + 321 .loc 1 344 3 view .LVU93 + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t pll_config; + 322 .loc 1 345 3 view .LVU94 + ARM GAS /tmp/ccemvyj9.s page 14 + + + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** FlagStatus pwrclkchanged = RESET; + 323 .loc 1 346 3 view .LVU95 + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check Null pointer */ + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (RCC_OscInitStruct == NULL) + 324 .loc 1 349 3 view .LVU96 + 325 .loc 1 349 6 is_stmt 0 view .LVU97 + 326 0000 0028 cmp r0, #0 + 327 0002 00F00682 beq .L82 + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t tickstart; + 328 .loc 1 343 1 view .LVU98 + 329 0006 70B5 push {r4, r5, r6, lr} + 330 .LCFI1: + 331 .cfi_def_cfa_offset 16 + 332 .cfi_offset 4, -16 + 333 .cfi_offset 5, -12 + 334 .cfi_offset 6, -8 + 335 .cfi_offset 14, -4 + 336 0008 82B0 sub sp, sp, #8 + 337 .LCFI2: + 338 .cfi_def_cfa_offset 24 + 339 000a 0446 mov r4, r0 + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the parameters */ + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + 340 .loc 1 355 3 is_stmt 1 view .LVU99 + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /*------------------------------- HSE Configuration ------------------------*/ + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 341 .loc 1 358 3 view .LVU100 + 342 .loc 1 358 26 is_stmt 0 view .LVU101 + 343 000c 0368 ldr r3, [r0] + 344 .loc 1 358 6 view .LVU102 + 345 000e 13F0010F tst r3, #1 + 346 0012 29D0 beq .L32 + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the parameters */ + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + 347 .loc 1 361 5 is_stmt 1 view .LVU103 + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */ + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + 348 .loc 1 363 5 view .LVU104 + 349 .loc 1 363 10 is_stmt 0 view .LVU105 + 350 0014 954B ldr r3, .L124 + 351 0016 9B68 ldr r3, [r3, #8] + 352 0018 03F00C03 and r3, r3, #12 + 353 .loc 1 363 8 view .LVU106 + 354 001c 042B cmp r3, #4 + 355 001e 1AD0 beq .L33 + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & R + 356 .loc 1 364 14 view .LVU107 + 357 0020 924B ldr r3, .L124 + 358 0022 9B68 ldr r3, [r3, #8] + 359 0024 03F00C03 and r3, r3, #12 + ARM GAS /tmp/ccemvyj9.s page 15 + + + 360 .loc 1 364 9 view .LVU108 + 361 0028 082B cmp r3, #8 + 362 002a 0FD0 beq .L110 + 363 .L34: + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Set the new HSE configuration ---------------------------------------*/ + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 364 .loc 1 374 7 is_stmt 1 view .LVU109 + 365 .loc 1 374 7 view .LVU110 + 366 002c 6368 ldr r3, [r4, #4] + 367 002e B3F5803F cmp r3, #65536 + 368 0032 40D0 beq .L111 + 369 .loc 1 374 7 discriminator 2 view .LVU111 + 370 0034 002B cmp r3, #0 + 371 0036 54D1 bne .L37 + 372 .loc 1 374 7 discriminator 4 view .LVU112 + 373 0038 8C4B ldr r3, .L124 + 374 003a 1A68 ldr r2, [r3] + 375 003c 22F48032 bic r2, r2, #65536 + 376 0040 1A60 str r2, [r3] + 377 .loc 1 374 7 discriminator 4 view .LVU113 + 378 0042 1A68 ldr r2, [r3] + 379 0044 22F48022 bic r2, r2, #262144 + 380 0048 1A60 str r2, [r3] + 381 004a 39E0 b .L36 + 382 .L110: + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & R + 383 .loc 1 364 87 is_stmt 0 discriminator 1 view .LVU114 + 384 004c 874B ldr r3, .L124 + 385 004e 5B68 ldr r3, [r3, #4] + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & R + 386 .loc 1 364 79 discriminator 1 view .LVU115 + 387 0050 13F4800F tst r3, #4194304 + 388 0054 EAD0 beq .L34 + 389 .L33: + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 390 .loc 1 366 7 is_stmt 1 view .LVU116 + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 391 .loc 1 366 12 is_stmt 0 view .LVU117 + 392 0056 854B ldr r3, .L124 + 393 0058 1B68 ldr r3, [r3] + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 394 .loc 1 366 10 view .LVU118 + 395 005a 13F4003F tst r3, #131072 + 396 005e 03D0 beq .L32 + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 397 .loc 1 366 79 discriminator 1 view .LVU119 + 398 0060 6368 ldr r3, [r4, #4] + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 399 .loc 1 366 58 discriminator 1 view .LVU120 + ARM GAS /tmp/ccemvyj9.s page 16 + + + 400 0062 002B cmp r3, #0 + 401 0064 00F0D781 beq .L112 + 402 .LVL27: + 403 .L32: + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the HSE State */ + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till HSE is ready */ + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till HSE is bypassed or disabled */ + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /*----------------------------- HSI Configuration --------------------------*/ + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 404 .loc 1 408 3 is_stmt 1 view .LVU121 + 405 .loc 1 408 26 is_stmt 0 view .LVU122 + 406 0068 2368 ldr r3, [r4] + 407 .loc 1 408 6 view .LVU123 + 408 006a 13F0020F tst r3, #2 + 409 006e 74D0 beq .L44 + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the parameters */ + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + 410 .loc 1 411 5 is_stmt 1 view .LVU124 + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + 411 .loc 1 412 5 view .LVU125 + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock * + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + 412 .loc 1 415 5 view .LVU126 + 413 .loc 1 415 10 is_stmt 0 view .LVU127 + 414 0070 7E4B ldr r3, .L124 + 415 0072 9B68 ldr r3, [r3, #8] + ARM GAS /tmp/ccemvyj9.s page 17 + + + 416 .loc 1 415 8 view .LVU128 + 417 0074 13F00C0F tst r3, #12 + 418 0078 5ED0 beq .L45 + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & R + 419 .loc 1 416 14 view .LVU129 + 420 007a 7C4B ldr r3, .L124 + 421 007c 9B68 ldr r3, [r3, #8] + 422 007e 03F00C03 and r3, r3, #12 + 423 .loc 1 416 9 view .LVU130 + 424 0082 082B cmp r3, #8 + 425 0084 53D0 beq .L113 + 426 .L46: + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* When HSI is used as system clock it will not disabled */ + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Otherwise, just the calibration is allowed */ + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the HSI State */ + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) + 427 .loc 1 433 7 is_stmt 1 view .LVU131 + 428 .loc 1 433 29 is_stmt 0 view .LVU132 + 429 0086 E368 ldr r3, [r4, #12] + 430 .loc 1 433 10 view .LVU133 + 431 0088 002B cmp r3, #0 + 432 008a 00F08980 beq .L48 + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Enable the Internal High Speed oscillator (HSI). */ + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_HSI_ENABLE(); + 433 .loc 1 436 9 is_stmt 1 view .LVU134 + 434 008e 774A ldr r2, .L124 + 435 0090 1368 ldr r3, [r2] + 436 0092 43F00103 orr r3, r3, #1 + 437 0096 1360 str r3, [r2] + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 438 .loc 1 439 9 view .LVU135 + 439 .loc 1 439 21 is_stmt 0 view .LVU136 + 440 0098 FFF7FEFF bl HAL_GetTick + 441 .LVL28: + 442 009c 0546 mov r5, r0 + 443 .LVL29: + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till HSI is ready */ + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 444 .loc 1 442 9 is_stmt 1 view .LVU137 + 445 .L49: + ARM GAS /tmp/ccemvyj9.s page 18 + + + 446 .loc 1 442 52 view .LVU138 + 447 .loc 1 442 16 is_stmt 0 view .LVU139 + 448 009e 734B ldr r3, .L124 + 449 00a0 1B68 ldr r3, [r3] + 450 .loc 1 442 52 view .LVU140 + 451 00a2 13F0020F tst r3, #2 + 452 00a6 72D1 bne .L114 + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 453 .loc 1 444 11 is_stmt 1 view .LVU141 + 454 .loc 1 444 16 is_stmt 0 view .LVU142 + 455 00a8 FFF7FEFF bl HAL_GetTick + 456 .LVL30: + 457 .loc 1 444 30 discriminator 1 view .LVU143 + 458 00ac 401B subs r0, r0, r5 + 459 .loc 1 444 14 discriminator 1 view .LVU144 + 460 00ae 0228 cmp r0, #2 + 461 00b0 F5D9 bls .L49 + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; + 462 .loc 1 446 20 view .LVU145 + 463 00b2 0320 movs r0, #3 + 464 00b4 B4E1 b .L31 + 465 .LVL31: + 466 .L111: + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 467 .loc 1 374 7 is_stmt 1 discriminator 1 view .LVU146 + 468 00b6 6D4A ldr r2, .L124 + 469 00b8 1368 ldr r3, [r2] + 470 00ba 43F48033 orr r3, r3, #65536 + 471 00be 1360 str r3, [r2] + 472 .L36: + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 473 .loc 1 374 7 discriminator 10 view .LVU147 + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 474 .loc 1 377 7 view .LVU148 + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 475 .loc 1 377 28 is_stmt 0 view .LVU149 + 476 00c0 6368 ldr r3, [r4, #4] + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 477 .loc 1 377 10 view .LVU150 + 478 00c2 2BB3 cbz r3, .L39 + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 479 .loc 1 380 9 is_stmt 1 view .LVU151 + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 480 .loc 1 380 21 is_stmt 0 view .LVU152 + 481 00c4 FFF7FEFF bl HAL_GetTick + 482 .LVL32: + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 483 .loc 1 380 21 view .LVU153 + 484 00c8 0546 mov r5, r0 + 485 .LVL33: + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 486 .loc 1 383 9 is_stmt 1 view .LVU154 + 487 .L40: + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 488 .loc 1 383 52 view .LVU155 + ARM GAS /tmp/ccemvyj9.s page 19 + + + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 489 .loc 1 383 16 is_stmt 0 view .LVU156 + 490 00ca 684B ldr r3, .L124 + 491 00cc 1B68 ldr r3, [r3] + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 492 .loc 1 383 52 view .LVU157 + 493 00ce 13F4003F tst r3, #131072 + 494 00d2 C9D1 bne .L32 + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 495 .loc 1 385 11 is_stmt 1 view .LVU158 + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 496 .loc 1 385 16 is_stmt 0 view .LVU159 + 497 00d4 FFF7FEFF bl HAL_GetTick + 498 .LVL34: + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 499 .loc 1 385 30 discriminator 1 view .LVU160 + 500 00d8 401B subs r0, r0, r5 + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 501 .loc 1 385 14 discriminator 1 view .LVU161 + 502 00da 6428 cmp r0, #100 + 503 00dc F5D9 bls .L40 + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 504 .loc 1 387 20 view .LVU162 + 505 00de 0320 movs r0, #3 + 506 00e0 9EE1 b .L31 + 507 .LVL35: + 508 .L37: + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 509 .loc 1 374 7 is_stmt 1 discriminator 5 view .LVU163 + 510 00e2 B3F5A02F cmp r3, #327680 + 511 00e6 09D0 beq .L115 + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 512 .loc 1 374 7 discriminator 8 view .LVU164 + 513 00e8 604B ldr r3, .L124 + 514 00ea 1A68 ldr r2, [r3] + 515 00ec 22F48032 bic r2, r2, #65536 + 516 00f0 1A60 str r2, [r3] + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 517 .loc 1 374 7 discriminator 8 view .LVU165 + 518 00f2 1A68 ldr r2, [r3] + 519 00f4 22F48022 bic r2, r2, #262144 + 520 00f8 1A60 str r2, [r3] + 521 00fa E1E7 b .L36 + 522 .L115: + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 523 .loc 1 374 7 discriminator 7 view .LVU166 + 524 00fc 5B4B ldr r3, .L124 + 525 00fe 1A68 ldr r2, [r3] + 526 0100 42F48022 orr r2, r2, #262144 + 527 0104 1A60 str r2, [r3] + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 528 .loc 1 374 7 discriminator 7 view .LVU167 + 529 0106 1A68 ldr r2, [r3] + 530 0108 42F48032 orr r2, r2, #65536 + 531 010c 1A60 str r2, [r3] + 532 010e D7E7 b .L36 + 533 .L39: + ARM GAS /tmp/ccemvyj9.s page 20 + + + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 534 .loc 1 394 9 view .LVU168 + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 535 .loc 1 394 21 is_stmt 0 view .LVU169 + 536 0110 FFF7FEFF bl HAL_GetTick + 537 .LVL36: + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 538 .loc 1 394 21 view .LVU170 + 539 0114 0546 mov r5, r0 + 540 .LVL37: + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 541 .loc 1 397 9 is_stmt 1 view .LVU171 + 542 .L42: + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 543 .loc 1 397 52 view .LVU172 + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 544 .loc 1 397 16 is_stmt 0 view .LVU173 + 545 0116 554B ldr r3, .L124 + 546 0118 1B68 ldr r3, [r3] + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 547 .loc 1 397 52 view .LVU174 + 548 011a 13F4003F tst r3, #131072 + 549 011e A3D0 beq .L32 + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 550 .loc 1 399 11 is_stmt 1 view .LVU175 + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 551 .loc 1 399 16 is_stmt 0 view .LVU176 + 552 0120 FFF7FEFF bl HAL_GetTick + 553 .LVL38: + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 554 .loc 1 399 30 discriminator 1 view .LVU177 + 555 0124 401B subs r0, r0, r5 + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 556 .loc 1 399 14 discriminator 1 view .LVU178 + 557 0126 6428 cmp r0, #100 + 558 0128 F5D9 bls .L42 + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 559 .loc 1 401 20 view .LVU179 + 560 012a 0320 movs r0, #3 + 561 012c 78E1 b .L31 + 562 .LVL39: + 563 .L113: + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 564 .loc 1 416 87 discriminator 1 view .LVU180 + 565 012e 4F4B ldr r3, .L124 + 566 0130 5B68 ldr r3, [r3, #4] + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 567 .loc 1 416 79 discriminator 1 view .LVU181 + 568 0132 13F4800F tst r3, #4194304 + 569 0136 A6D1 bne .L46 + 570 .L45: + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 571 .loc 1 419 7 is_stmt 1 view .LVU182 + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 572 .loc 1 419 12 is_stmt 0 view .LVU183 + 573 0138 4C4B ldr r3, .L124 + 574 013a 1B68 ldr r3, [r3] + ARM GAS /tmp/ccemvyj9.s page 21 + + + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 575 .loc 1 419 10 view .LVU184 + 576 013c 13F0020F tst r3, #2 + 577 0140 03D0 beq .L47 + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 578 .loc 1 419 79 discriminator 1 view .LVU185 + 579 0142 E368 ldr r3, [r4, #12] + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 580 .loc 1 419 58 discriminator 1 view .LVU186 + 581 0144 012B cmp r3, #1 + 582 0146 40F06881 bne .L86 + 583 .L47: + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 584 .loc 1 427 9 is_stmt 1 view .LVU187 + 585 014a 484A ldr r2, .L124 + 586 014c 1368 ldr r3, [r2] + 587 014e 23F0F803 bic r3, r3, #248 + 588 0152 2169 ldr r1, [r4, #16] + 589 0154 43EAC103 orr r3, r3, r1, lsl #3 + 590 0158 1360 str r3, [r2] + 591 .L44: + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Disable the Internal High Speed oscillator (HSI). */ + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_HSI_DISABLE(); + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till HSI is ready */ + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /*------------------------------ LSI Configuration -------------------------*/ + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 592 .loc 1 473 3 view .LVU188 + 593 .loc 1 473 26 is_stmt 0 view .LVU189 + 594 015a 2368 ldr r3, [r4] + 595 .loc 1 473 6 view .LVU190 + 596 015c 13F0080F tst r3, #8 + 597 0160 46D0 beq .L53 + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the parameters */ + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + ARM GAS /tmp/ccemvyj9.s page 22 + + + 598 .loc 1 476 5 is_stmt 1 view .LVU191 + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the LSI State */ + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) + 599 .loc 1 479 5 view .LVU192 + 600 .loc 1 479 27 is_stmt 0 view .LVU193 + 601 0162 6369 ldr r3, [r4, #20] + 602 .loc 1 479 8 view .LVU194 + 603 0164 83B3 cbz r3, .L54 + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Enable the Internal Low Speed oscillator (LSI). */ + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_LSI_ENABLE(); + 604 .loc 1 482 7 is_stmt 1 view .LVU195 + 605 0166 414A ldr r2, .L124 + 606 0168 536F ldr r3, [r2, #116] + 607 016a 43F00103 orr r3, r3, #1 + 608 016e 5367 str r3, [r2, #116] + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 609 .loc 1 485 7 view .LVU196 + 610 .loc 1 485 19 is_stmt 0 view .LVU197 + 611 0170 FFF7FEFF bl HAL_GetTick + 612 .LVL40: + 613 0174 0546 mov r5, r0 + 614 .LVL41: + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till LSI is ready */ + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 615 .loc 1 488 7 is_stmt 1 view .LVU198 + 616 .L55: + 617 .loc 1 488 50 view .LVU199 + 618 .loc 1 488 14 is_stmt 0 view .LVU200 + 619 0176 3D4B ldr r3, .L124 + 620 0178 5B6F ldr r3, [r3, #116] + 621 .loc 1 488 50 view .LVU201 + 622 017a 13F0020F tst r3, #2 + 623 017e 37D1 bne .L53 + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 624 .loc 1 490 9 is_stmt 1 view .LVU202 + 625 .loc 1 490 14 is_stmt 0 view .LVU203 + 626 0180 FFF7FEFF bl HAL_GetTick + 627 .LVL42: + 628 .loc 1 490 28 discriminator 1 view .LVU204 + 629 0184 401B subs r0, r0, r5 + 630 .loc 1 490 12 discriminator 1 view .LVU205 + 631 0186 0228 cmp r0, #2 + 632 0188 F5D9 bls .L55 + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; + 633 .loc 1 492 18 view .LVU206 + 634 018a 0320 movs r0, #3 + 635 018c 48E1 b .L31 + 636 .L114: + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 637 .loc 1 451 9 is_stmt 1 view .LVU207 + ARM GAS /tmp/ccemvyj9.s page 23 + + + 638 018e 374A ldr r2, .L124 + 639 0190 1368 ldr r3, [r2] + 640 0192 23F0F803 bic r3, r3, #248 + 641 0196 2169 ldr r1, [r4, #16] + 642 0198 43EAC103 orr r3, r3, r1, lsl #3 + 643 019c 1360 str r3, [r2] + 644 019e DCE7 b .L44 + 645 .LVL43: + 646 .L48: + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 647 .loc 1 456 9 view .LVU208 + 648 01a0 324A ldr r2, .L124 + 649 01a2 1368 ldr r3, [r2] + 650 01a4 23F00103 bic r3, r3, #1 + 651 01a8 1360 str r3, [r2] + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 652 .loc 1 459 9 view .LVU209 + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 653 .loc 1 459 21 is_stmt 0 view .LVU210 + 654 01aa FFF7FEFF bl HAL_GetTick + 655 .LVL44: + 656 01ae 0546 mov r5, r0 + 657 .LVL45: + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 658 .loc 1 462 9 is_stmt 1 view .LVU211 + 659 .L51: + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 660 .loc 1 462 52 view .LVU212 + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 661 .loc 1 462 16 is_stmt 0 view .LVU213 + 662 01b0 2E4B ldr r3, .L124 + 663 01b2 1B68 ldr r3, [r3] + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 664 .loc 1 462 52 view .LVU214 + 665 01b4 13F0020F tst r3, #2 + 666 01b8 CFD0 beq .L44 + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 667 .loc 1 464 11 is_stmt 1 view .LVU215 + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 668 .loc 1 464 16 is_stmt 0 view .LVU216 + 669 01ba FFF7FEFF bl HAL_GetTick + 670 .LVL46: + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 671 .loc 1 464 30 discriminator 1 view .LVU217 + 672 01be 401B subs r0, r0, r5 + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 673 .loc 1 464 14 discriminator 1 view .LVU218 + 674 01c0 0228 cmp r0, #2 + 675 01c2 F5D9 bls .L51 + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 676 .loc 1 466 20 view .LVU219 + 677 01c4 0320 movs r0, #3 + 678 01c6 2BE1 b .L31 + 679 .LVL47: + 680 .L54: + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + ARM GAS /tmp/ccemvyj9.s page 24 + + + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Disable the Internal Low Speed oscillator (LSI). */ + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_LSI_DISABLE(); + 681 .loc 1 499 7 is_stmt 1 view .LVU220 + 682 01c8 284A ldr r2, .L124 + 683 01ca 536F ldr r3, [r2, #116] + 684 01cc 23F00103 bic r3, r3, #1 + 685 01d0 5367 str r3, [r2, #116] + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 686 .loc 1 502 7 view .LVU221 + 687 .loc 1 502 19 is_stmt 0 view .LVU222 + 688 01d2 FFF7FEFF bl HAL_GetTick + 689 .LVL48: + 690 01d6 0546 mov r5, r0 + 691 .LVL49: + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till LSI is ready */ + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 692 .loc 1 505 7 is_stmt 1 view .LVU223 + 693 .L57: + 694 .loc 1 505 50 view .LVU224 + 695 .loc 1 505 14 is_stmt 0 view .LVU225 + 696 01d8 244B ldr r3, .L124 + 697 01da 5B6F ldr r3, [r3, #116] + 698 .loc 1 505 50 view .LVU226 + 699 01dc 13F0020F tst r3, #2 + 700 01e0 06D0 beq .L53 + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 701 .loc 1 507 9 is_stmt 1 view .LVU227 + 702 .loc 1 507 14 is_stmt 0 view .LVU228 + 703 01e2 FFF7FEFF bl HAL_GetTick + 704 .LVL50: + 705 .loc 1 507 28 discriminator 1 view .LVU229 + 706 01e6 401B subs r0, r0, r5 + 707 .loc 1 507 12 discriminator 1 view .LVU230 + 708 01e8 0228 cmp r0, #2 + 709 01ea F5D9 bls .L57 + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; + 710 .loc 1 509 18 view .LVU231 + 711 01ec 0320 movs r0, #3 + 712 01ee 17E1 b .L31 + 713 .LVL51: + 714 .L53: + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /*------------------------------ LSE Configuration -------------------------*/ + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 715 .loc 1 515 3 is_stmt 1 view .LVU232 + 716 .loc 1 515 26 is_stmt 0 view .LVU233 + ARM GAS /tmp/ccemvyj9.s page 25 + + + 717 01f0 2368 ldr r3, [r4] + 718 .loc 1 515 6 view .LVU234 + 719 01f2 13F0040F tst r3, #4 + 720 01f6 7DD0 beq .L59 + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the parameters */ + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + 721 .loc 1 518 5 is_stmt 1 view .LVU235 + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Update LSE configuration in Backup Domain control register */ + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Requires to enable write access to Backup Domain of necessary */ + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + 722 .loc 1 522 5 view .LVU236 + 723 .loc 1 522 9 is_stmt 0 view .LVU237 + 724 01f8 1C4B ldr r3, .L124 + 725 01fa 1B6C ldr r3, [r3, #64] + 726 .loc 1 522 8 view .LVU238 + 727 01fc 13F0805F tst r3, #268435456 + 728 0200 1ED1 bne .L91 + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Enable Power Clock*/ + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 729 .loc 1 525 7 is_stmt 1 view .LVU239 + 730 .LBB4: + 731 .loc 1 525 7 view .LVU240 + 732 .loc 1 525 7 view .LVU241 + 733 0202 1A4B ldr r3, .L124 + 734 0204 1A6C ldr r2, [r3, #64] + 735 0206 42F08052 orr r2, r2, #268435456 + 736 020a 1A64 str r2, [r3, #64] + 737 .loc 1 525 7 view .LVU242 + 738 020c 1B6C ldr r3, [r3, #64] + 739 020e 03F08053 and r3, r3, #268435456 + 740 0212 0193 str r3, [sp, #4] + 741 .loc 1 525 7 view .LVU243 + 742 0214 019B ldr r3, [sp, #4] + 743 .LBE4: + 744 .loc 1 525 7 view .LVU244 + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** pwrclkchanged = SET; + 745 .loc 1 526 7 view .LVU245 + 746 .LVL52: + 747 .loc 1 526 21 is_stmt 0 view .LVU246 + 748 0216 0125 movs r5, #1 + 749 .LVL53: + 750 .L60: + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 751 .loc 1 529 5 is_stmt 1 view .LVU247 + 752 .loc 1 529 9 is_stmt 0 view .LVU248 + 753 0218 154B ldr r3, .L124+4 + 754 021a 1B68 ldr r3, [r3] + 755 .loc 1 529 8 view .LVU249 + 756 021c 13F4807F tst r3, #256 + 757 0220 10D0 beq .L116 + 758 .L61: + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + ARM GAS /tmp/ccemvyj9.s page 26 + + + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Enable write access to Backup domain */ + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** PWR->CR1 |= PWR_CR1_DBP; + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait for Backup domain Write protection disable */ + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Set the new LSE configuration -----------------------------------------*/ + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 759 .loc 1 547 5 is_stmt 1 view .LVU250 + 760 .loc 1 547 5 view .LVU251 + 761 0222 A368 ldr r3, [r4, #8] + 762 0224 012B cmp r3, #1 + 763 0226 25D0 beq .L117 + 764 .loc 1 547 5 discriminator 2 view .LVU252 + 765 0228 002B cmp r3, #0 + 766 022a 3BD1 bne .L66 + 767 .loc 1 547 5 discriminator 4 view .LVU253 + 768 022c 0F4B ldr r3, .L124 + 769 022e 1A6F ldr r2, [r3, #112] + 770 0230 22F00102 bic r2, r2, #1 + 771 0234 1A67 str r2, [r3, #112] + 772 .loc 1 547 5 discriminator 4 view .LVU254 + 773 0236 1A6F ldr r2, [r3, #112] + 774 0238 22F00402 bic r2, r2, #4 + 775 023c 1A67 str r2, [r3, #112] + 776 023e 1EE0 b .L65 + 777 .LVL54: + 778 .L91: + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 779 .loc 1 346 14 is_stmt 0 view .LVU255 + 780 0240 0025 movs r5, #0 + 781 0242 E9E7 b .L60 + 782 .LVL55: + 783 .L116: + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 784 .loc 1 532 7 is_stmt 1 view .LVU256 + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 785 .loc 1 532 10 is_stmt 0 view .LVU257 + 786 0244 0A4A ldr r2, .L124+4 + 787 0246 1368 ldr r3, [r2] + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 788 .loc 1 532 16 view .LVU258 + 789 0248 43F48073 orr r3, r3, #256 + 790 024c 1360 str r3, [r2] + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 791 .loc 1 535 7 is_stmt 1 view .LVU259 + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 792 .loc 1 535 19 is_stmt 0 view .LVU260 + ARM GAS /tmp/ccemvyj9.s page 27 + + + 793 024e FFF7FEFF bl HAL_GetTick + 794 .LVL56: + 795 0252 0646 mov r6, r0 + 796 .LVL57: + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 797 .loc 1 537 7 is_stmt 1 view .LVU261 + 798 .L62: + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 799 .loc 1 537 14 view .LVU262 + 800 0254 064B ldr r3, .L124+4 + 801 0256 1B68 ldr r3, [r3] + 802 0258 13F4807F tst r3, #256 + 803 025c E1D1 bne .L61 + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 804 .loc 1 539 9 view .LVU263 + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 805 .loc 1 539 14 is_stmt 0 view .LVU264 + 806 025e FFF7FEFF bl HAL_GetTick + 807 .LVL58: + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 808 .loc 1 539 28 discriminator 1 view .LVU265 + 809 0262 801B subs r0, r0, r6 + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 810 .loc 1 539 12 discriminator 1 view .LVU266 + 811 0264 6428 cmp r0, #100 + 812 0266 F5D9 bls .L62 + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 813 .loc 1 541 18 view .LVU267 + 814 0268 0320 movs r0, #3 + 815 026a D9E0 b .L31 + 816 .L125: + 817 .align 2 + 818 .L124: + 819 026c 00380240 .word 1073887232 + 820 0270 00700040 .word 1073770496 + 821 .LVL59: + 822 .L117: + 823 .loc 1 547 5 is_stmt 1 discriminator 1 view .LVU268 + 824 0274 724A ldr r2, .L126 + 825 0276 136F ldr r3, [r2, #112] + 826 0278 43F00103 orr r3, r3, #1 + 827 027c 1367 str r3, [r2, #112] + 828 .L65: + 829 .loc 1 547 5 discriminator 10 view .LVU269 + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the LSE State */ + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + 830 .loc 1 549 5 view .LVU270 + 831 .loc 1 549 27 is_stmt 0 view .LVU271 + 832 027e A368 ldr r3, [r4, #8] + 833 .loc 1 549 8 view .LVU272 + 834 0280 33B3 cbz r3, .L68 + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 835 .loc 1 552 7 is_stmt 1 view .LVU273 + 836 .loc 1 552 19 is_stmt 0 view .LVU274 + 837 0282 FFF7FEFF bl HAL_GetTick + ARM GAS /tmp/ccemvyj9.s page 28 + + + 838 .LVL60: + 839 0286 0646 mov r6, r0 + 840 .LVL61: + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till LSE is ready */ + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 841 .loc 1 555 7 is_stmt 1 view .LVU275 + 842 .L69: + 843 .loc 1 555 50 view .LVU276 + 844 .loc 1 555 14 is_stmt 0 view .LVU277 + 845 0288 6D4B ldr r3, .L126 + 846 028a 1B6F ldr r3, [r3, #112] + 847 .loc 1 555 50 view .LVU278 + 848 028c 13F0020F tst r3, #2 + 849 0290 2FD1 bne .L71 + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 850 .loc 1 557 9 is_stmt 1 view .LVU279 + 851 .loc 1 557 14 is_stmt 0 view .LVU280 + 852 0292 FFF7FEFF bl HAL_GetTick + 853 .LVL62: + 854 .loc 1 557 28 discriminator 1 view .LVU281 + 855 0296 801B subs r0, r0, r6 + 856 .loc 1 557 12 discriminator 1 view .LVU282 + 857 0298 41F28833 movw r3, #5000 + 858 029c 9842 cmp r0, r3 + 859 029e F3D9 bls .L69 + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; + 860 .loc 1 559 18 view .LVU283 + 861 02a0 0320 movs r0, #3 + 862 02a2 BDE0 b .L31 + 863 .LVL63: + 864 .L66: + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the LSE State */ + 865 .loc 1 547 5 is_stmt 1 discriminator 5 view .LVU284 + 866 02a4 052B cmp r3, #5 + 867 02a6 09D0 beq .L118 + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the LSE State */ + 868 .loc 1 547 5 discriminator 8 view .LVU285 + 869 02a8 654B ldr r3, .L126 + 870 02aa 1A6F ldr r2, [r3, #112] + 871 02ac 22F00102 bic r2, r2, #1 + 872 02b0 1A67 str r2, [r3, #112] + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the LSE State */ + 873 .loc 1 547 5 discriminator 8 view .LVU286 + 874 02b2 1A6F ldr r2, [r3, #112] + 875 02b4 22F00402 bic r2, r2, #4 + 876 02b8 1A67 str r2, [r3, #112] + 877 02ba E0E7 b .L65 + 878 .L118: + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the LSE State */ + 879 .loc 1 547 5 discriminator 7 view .LVU287 + 880 02bc 604B ldr r3, .L126 + 881 02be 1A6F ldr r2, [r3, #112] + 882 02c0 42F00402 orr r2, r2, #4 + 883 02c4 1A67 str r2, [r3, #112] + ARM GAS /tmp/ccemvyj9.s page 29 + + + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the LSE State */ + 884 .loc 1 547 5 discriminator 7 view .LVU288 + 885 02c6 1A6F ldr r2, [r3, #112] + 886 02c8 42F00102 orr r2, r2, #1 + 887 02cc 1A67 str r2, [r3, #112] + 888 02ce D6E7 b .L65 + 889 .L68: + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 890 .loc 1 566 7 view .LVU289 + 891 .loc 1 566 19 is_stmt 0 view .LVU290 + 892 02d0 FFF7FEFF bl HAL_GetTick + 893 .LVL64: + 894 02d4 0646 mov r6, r0 + 895 .LVL65: + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till LSE is ready */ + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 896 .loc 1 569 7 is_stmt 1 view .LVU291 + 897 .L72: + 898 .loc 1 569 50 view .LVU292 + 899 .loc 1 569 14 is_stmt 0 view .LVU293 + 900 02d6 5A4B ldr r3, .L126 + 901 02d8 1B6F ldr r3, [r3, #112] + 902 .loc 1 569 50 view .LVU294 + 903 02da 13F0020F tst r3, #2 + 904 02de 08D0 beq .L71 + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 905 .loc 1 571 9 is_stmt 1 view .LVU295 + 906 .loc 1 571 14 is_stmt 0 view .LVU296 + 907 02e0 FFF7FEFF bl HAL_GetTick + 908 .LVL66: + 909 .loc 1 571 28 discriminator 1 view .LVU297 + 910 02e4 801B subs r0, r0, r6 + 911 .loc 1 571 12 discriminator 1 view .LVU298 + 912 02e6 41F28833 movw r3, #5000 + 913 02ea 9842 cmp r0, r3 + 914 02ec F3D9 bls .L72 + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; + 915 .loc 1 573 18 view .LVU299 + 916 02ee 0320 movs r0, #3 + 917 02f0 96E0 b .L31 + 918 .L71: + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Restore clock configuration if changed */ + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (pwrclkchanged == SET) + 919 .loc 1 579 5 is_stmt 1 view .LVU300 + ARM GAS /tmp/ccemvyj9.s page 30 + + + 920 .loc 1 579 8 is_stmt 0 view .LVU301 + 921 02f2 FDB9 cbnz r5, .L119 + 922 .LVL67: + 923 .L59: + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_PWR_CLK_DISABLE(); + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /*-------------------------------- PLL Configuration -----------------------*/ + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the parameters */ + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + 924 .loc 1 586 3 is_stmt 1 view .LVU302 + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 925 .loc 1 587 3 view .LVU303 + 926 .loc 1 587 30 is_stmt 0 view .LVU304 + 927 02f4 A369 ldr r3, [r4, #24] + 928 .loc 1 587 6 view .LVU305 + 929 02f6 002B cmp r3, #0 + 930 02f8 00F09180 beq .L95 + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check if the PLL is used as system clock or not */ + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 931 .loc 1 590 5 is_stmt 1 view .LVU306 + 932 .loc 1 590 9 is_stmt 0 view .LVU307 + 933 02fc 504A ldr r2, .L126 + 934 02fe 9268 ldr r2, [r2, #8] + 935 0300 02F00C02 and r2, r2, #12 + 936 .loc 1 590 8 view .LVU308 + 937 0304 082A cmp r2, #8 + 938 0306 59D0 beq .L74 + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 939 .loc 1 592 7 is_stmt 1 view .LVU309 + 940 .loc 1 592 10 is_stmt 0 view .LVU310 + 941 0308 022B cmp r3, #2 + 942 030a 19D0 beq .L120 + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the parameters */ + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR) + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #endif + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Disable the main PLL. */ + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_PLL_DISABLE(); + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till PLL is ready */ + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + ARM GAS /tmp/ccemvyj9.s page 31 + + + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Configure the main PLL clock source, multiplication and division factors. */ + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR) + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLM, + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLN, + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLP, + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLQ, + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLR); + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #else + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLM, + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLN, + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLP, + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLQ); + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #endif + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Enable the main PLL. */ + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_PLL_ENABLE(); + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till PLL is ready */ + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Disable the main PLL. */ + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_PLL_DISABLE(); + 943 .loc 1 653 9 is_stmt 1 view .LVU311 + 944 030c 4C4A ldr r2, .L126 + 945 030e 1368 ldr r3, [r2] + 946 0310 23F08073 bic r3, r3, #16777216 + 947 0314 1360 str r3, [r2] + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 948 .loc 1 656 9 view .LVU312 + 949 .loc 1 656 21 is_stmt 0 view .LVU313 + 950 0316 FFF7FEFF bl HAL_GetTick + 951 .LVL68: + 952 031a 0446 mov r4, r0 + 953 .LVL69: + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Wait till PLL is ready */ + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + ARM GAS /tmp/ccemvyj9.s page 32 + + + 954 .loc 1 659 9 is_stmt 1 view .LVU314 + 955 .L80: + 956 .loc 1 659 52 view .LVU315 + 957 .loc 1 659 16 is_stmt 0 view .LVU316 + 958 031c 484B ldr r3, .L126 + 959 031e 1B68 ldr r3, [r3] + 960 .loc 1 659 52 view .LVU317 + 961 0320 13F0007F tst r3, #33554432 + 962 0324 48D0 beq .L121 + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 963 .loc 1 661 11 is_stmt 1 view .LVU318 + 964 .loc 1 661 16 is_stmt 0 view .LVU319 + 965 0326 FFF7FEFF bl HAL_GetTick + 966 .LVL70: + 967 .loc 1 661 30 discriminator 1 view .LVU320 + 968 032a 001B subs r0, r0, r4 + 969 .loc 1 661 14 discriminator 1 view .LVU321 + 970 032c 0228 cmp r0, #2 + 971 032e F5D9 bls .L80 + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; + 972 .loc 1 663 20 view .LVU322 + 973 0330 0320 movs r0, #3 + 974 0332 75E0 b .L31 + 975 .LVL71: + 976 .L119: + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 977 .loc 1 581 7 is_stmt 1 view .LVU323 + 978 0334 424A ldr r2, .L126 + 979 0336 136C ldr r3, [r2, #64] + 980 0338 23F08053 bic r3, r3, #268435456 + 981 033c 1364 str r3, [r2, #64] + 982 033e D9E7 b .L59 + 983 .LVL72: + 984 .L120: + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + 985 .loc 1 595 9 view .LVU324 + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + 986 .loc 1 596 9 view .LVU325 + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + 987 .loc 1 597 9 view .LVU326 + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + 988 .loc 1 598 9 view .LVU327 + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR) + 989 .loc 1 599 9 view .LVU328 + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #endif + 990 .loc 1 601 9 view .LVU329 + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 991 .loc 1 605 9 view .LVU330 + 992 0340 3F4A ldr r2, .L126 + 993 0342 1368 ldr r3, [r2] + 994 0344 23F08073 bic r3, r3, #16777216 + 995 0348 1360 str r3, [r2] + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 996 .loc 1 608 9 view .LVU331 + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + ARM GAS /tmp/ccemvyj9.s page 33 + + + 997 .loc 1 608 21 is_stmt 0 view .LVU332 + 998 034a FFF7FEFF bl HAL_GetTick + 999 .LVL73: + 1000 034e 0546 mov r5, r0 + 1001 .LVL74: + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1002 .loc 1 611 9 is_stmt 1 view .LVU333 + 1003 .L76: + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1004 .loc 1 611 52 view .LVU334 + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1005 .loc 1 611 16 is_stmt 0 view .LVU335 + 1006 0350 3B4B ldr r3, .L126 + 1007 0352 1B68 ldr r3, [r3] + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1008 .loc 1 611 52 view .LVU336 + 1009 0354 13F0007F tst r3, #33554432 + 1010 0358 06D0 beq .L122 + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1011 .loc 1 613 11 is_stmt 1 view .LVU337 + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1012 .loc 1 613 16 is_stmt 0 view .LVU338 + 1013 035a FFF7FEFF bl HAL_GetTick + 1014 .LVL75: + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1015 .loc 1 613 30 discriminator 1 view .LVU339 + 1016 035e 401B subs r0, r0, r5 + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1017 .loc 1 613 14 discriminator 1 view .LVU340 + 1018 0360 0228 cmp r0, #2 + 1019 0362 F5D9 bls .L76 + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1020 .loc 1 615 20 view .LVU341 + 1021 0364 0320 movs r0, #3 + 1022 0366 5BE0 b .L31 + 1023 .L122: + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLM, + 1024 .loc 1 621 9 is_stmt 1 view .LVU342 + 1025 0368 E369 ldr r3, [r4, #28] + 1026 036a 226A ldr r2, [r4, #32] + 1027 036c 1343 orrs r3, r3, r2 + 1028 036e 626A ldr r2, [r4, #36] + 1029 0370 43EA8213 orr r3, r3, r2, lsl #6 + 1030 0374 A26A ldr r2, [r4, #40] + 1031 0376 5208 lsrs r2, r2, #1 + 1032 0378 013A subs r2, r2, #1 + 1033 037a 43EA0243 orr r3, r3, r2, lsl #16 + 1034 037e E26A ldr r2, [r4, #44] + 1035 0380 43EA0263 orr r3, r3, r2, lsl #24 + 1036 0384 226B ldr r2, [r4, #48] + 1037 0386 43EA0273 orr r3, r3, r2, lsl #28 + 1038 038a 2D4A ldr r2, .L126 + 1039 038c 5360 str r3, [r2, #4] + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1040 .loc 1 636 9 view .LVU343 + 1041 038e 1368 ldr r3, [r2] + 1042 0390 43F08073 orr r3, r3, #16777216 + ARM GAS /tmp/ccemvyj9.s page 34 + + + 1043 0394 1360 str r3, [r2] + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1044 .loc 1 639 9 view .LVU344 + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1045 .loc 1 639 21 is_stmt 0 view .LVU345 + 1046 0396 FFF7FEFF bl HAL_GetTick + 1047 .LVL76: + 1048 039a 0446 mov r4, r0 + 1049 .LVL77: + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1050 .loc 1 642 9 is_stmt 1 view .LVU346 + 1051 .L78: + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1052 .loc 1 642 52 view .LVU347 + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1053 .loc 1 642 16 is_stmt 0 view .LVU348 + 1054 039c 284B ldr r3, .L126 + 1055 039e 1B68 ldr r3, [r3] + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1056 .loc 1 642 52 view .LVU349 + 1057 03a0 13F0007F tst r3, #33554432 + 1058 03a4 06D1 bne .L123 + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1059 .loc 1 644 11 is_stmt 1 view .LVU350 + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1060 .loc 1 644 16 is_stmt 0 view .LVU351 + 1061 03a6 FFF7FEFF bl HAL_GetTick + 1062 .LVL78: + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1063 .loc 1 644 30 discriminator 1 view .LVU352 + 1064 03aa 001B subs r0, r0, r4 + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1065 .loc 1 644 14 discriminator 1 view .LVU353 + 1066 03ac 0228 cmp r0, #2 + 1067 03ae F5D9 bls .L78 + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1068 .loc 1 646 20 view .LVU354 + 1069 03b0 0320 movs r0, #3 + 1070 03b2 35E0 b .L31 + 1071 .L123: + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Do not return HAL_ERROR if request repeats the current configuration */ + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** pll_config = RCC->PLLCFGR; + 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR) + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PL + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PL + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #else + ARM GAS /tmp/ccemvyj9.s page 35 + + + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PL + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #endif + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_OK; + 1072 .loc 1 693 10 view .LVU355 + 1073 03b4 0020 movs r0, #0 + 1074 03b6 33E0 b .L31 + 1075 .L121: + 1076 .loc 1 693 10 view .LVU356 + 1077 03b8 0020 movs r0, #0 + 1078 03ba 31E0 b .L31 + 1079 .LVL79: + 1080 .L74: + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR) + 1081 .loc 1 671 7 is_stmt 1 view .LVU357 + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR) + 1082 .loc 1 671 18 is_stmt 0 view .LVU358 + 1083 03bc 204A ldr r2, .L126 + 1084 03be 5268 ldr r2, [r2, #4] + 1085 .LVL80: + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 1086 .loc 1 673 7 is_stmt 1 view .LVU359 + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 1087 .loc 1 673 10 is_stmt 0 view .LVU360 + 1088 03c0 012B cmp r3, #1 + 1089 03c2 2FD0 beq .L99 + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 1090 .loc 1 674 12 view .LVU361 + 1091 03c4 02F48003 and r3, r2, #4194304 + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 1092 .loc 1 674 78 view .LVU362 + 1093 03c8 E169 ldr r1, [r4, #28] + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 1094 .loc 1 673 62 discriminator 1 view .LVU363 + 1095 03ca 8B42 cmp r3, r1 + 1096 03cc 2CD1 bne .L100 + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PL + 1097 .loc 1 675 12 view .LVU364 + 1098 03ce 02F03F03 and r3, r2, #63 + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PL + 1099 .loc 1 675 76 view .LVU365 + 1100 03d2 216A ldr r1, [r4, #32] + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 1101 .loc 1 674 90 view .LVU366 + 1102 03d4 8B42 cmp r3, r1 + 1103 03d6 29D1 bne .L101 + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) + 1104 .loc 1 676 77 view .LVU367 + ARM GAS /tmp/ccemvyj9.s page 36 + + + 1105 03d8 616A ldr r1, [r4, #36] + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PL + 1106 .loc 1 675 83 view .LVU368 + 1107 03da 47F6C073 movw r3, #32704 + 1108 03de 1340 ands r3, r3, r2 + 1109 03e0 B3EB811F cmp r3, r1, lsl #6 + 1110 03e4 24D1 bne .L102 + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL + 1111 .loc 1 677 12 view .LVU369 + 1112 03e6 02F44031 and r1, r2, #196608 + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL + 1113 .loc 1 677 80 view .LVU370 + 1114 03ea A36A ldr r3, [r4, #40] + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL + 1115 .loc 1 677 87 view .LVU371 + 1116 03ec 5B08 lsrs r3, r3, #1 + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL + 1117 .loc 1 677 94 view .LVU372 + 1118 03ee 013B subs r3, r3, #1 + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) + 1119 .loc 1 676 109 view .LVU373 + 1120 03f0 B1EB034F cmp r1, r3, lsl #16 + 1121 03f4 1ED1 bne .L103 + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PL + 1122 .loc 1 678 12 view .LVU374 + 1123 03f6 02F07063 and r3, r2, #251658240 + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PL + 1124 .loc 1 678 77 view .LVU375 + 1125 03fa E16A ldr r1, [r4, #44] + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PL + 1126 .loc 1 677 126 view .LVU376 + 1127 03fc B3EB016F cmp r3, r1, lsl #24 + 1128 0400 1AD1 bne .L104 + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #else + 1129 .loc 1 679 12 view .LVU377 + 1130 0402 02F0E042 and r2, r2, #1879048192 + 1131 .LVL81: + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #else + 1132 .loc 1 679 77 view .LVU378 + 1133 0406 236B ldr r3, [r4, #48] + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PL + 1134 .loc 1 678 109 view .LVU379 + 1135 0408 B2EB037F cmp r2, r3, lsl #28 + 1136 040c 16D1 bne .L105 + 1137 .loc 1 693 10 view .LVU380 + 1138 040e 0020 movs r0, #0 + 1139 0410 06E0 b .L31 + 1140 .LVL82: + 1141 .L82: + 1142 .LCFI3: + 1143 .cfi_def_cfa_offset 0 + 1144 .cfi_restore 4 + 1145 .cfi_restore 5 + 1146 .cfi_restore 6 + 1147 .cfi_restore 14 + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1148 .loc 1 351 12 view .LVU381 + ARM GAS /tmp/ccemvyj9.s page 37 + + + 1149 0412 0120 movs r0, #1 + 1150 .LVL83: + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1151 .loc 1 694 1 view .LVU382 + 1152 0414 7047 bx lr + 1153 .LVL84: + 1154 .L112: + 1155 .LCFI4: + 1156 .cfi_def_cfa_offset 24 + 1157 .cfi_offset 4, -16 + 1158 .cfi_offset 5, -12 + 1159 .cfi_offset 6, -8 + 1160 .cfi_offset 14, -4 + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1161 .loc 1 368 16 view .LVU383 + 1162 0416 0120 movs r0, #1 + 1163 .LVL85: + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1164 .loc 1 368 16 view .LVU384 + 1165 0418 02E0 b .L31 + 1166 .L86: + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1167 .loc 1 421 16 view .LVU385 + 1168 041a 0120 movs r0, #1 + 1169 041c 00E0 b .L31 + 1170 .LVL86: + 1171 .L95: + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1172 .loc 1 693 10 view .LVU386 + 1173 041e 0020 movs r0, #0 + 1174 .LVL87: + 1175 .L31: + 1176 .loc 1 694 1 view .LVU387 + 1177 0420 02B0 add sp, sp, #8 + 1178 .LCFI5: + 1179 .cfi_remember_state + 1180 .cfi_def_cfa_offset 16 + 1181 @ sp needed + 1182 0422 70BD pop {r4, r5, r6, pc} + 1183 .LVL88: + 1184 .L99: + 1185 .LCFI6: + 1186 .cfi_restore_state + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1187 .loc 1 689 16 view .LVU388 + 1188 0424 0120 movs r0, #1 + 1189 0426 FBE7 b .L31 + 1190 .L100: + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1191 .loc 1 689 16 view .LVU389 + 1192 0428 0120 movs r0, #1 + 1193 042a F9E7 b .L31 + 1194 .L101: + 1195 042c 0120 movs r0, #1 + 1196 042e F7E7 b .L31 + 1197 .L102: + 1198 0430 0120 movs r0, #1 + ARM GAS /tmp/ccemvyj9.s page 38 + + + 1199 0432 F5E7 b .L31 + 1200 .L103: + 1201 0434 0120 movs r0, #1 + 1202 0436 F3E7 b .L31 + 1203 .L104: + 1204 0438 0120 movs r0, #1 + 1205 043a F1E7 b .L31 + 1206 .LVL89: + 1207 .L105: + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1208 .loc 1 689 16 view .LVU390 + 1209 043c 0120 movs r0, #1 + 1210 043e EFE7 b .L31 + 1211 .L127: + 1212 .align 2 + 1213 .L126: + 1214 0440 00380240 .word 1073887232 + 1215 .cfi_endproc + 1216 .LFE142: + 1218 .section .text.HAL_RCC_MCOConfig,"ax",%progbits + 1219 .align 1 + 1220 .global HAL_RCC_MCOConfig + 1221 .syntax unified + 1222 .thumb + 1223 .thumb_func + 1225 HAL_RCC_MCOConfig: + 1226 .LVL90: + 1227 .LFB144: + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * parameters in the RCC_ClkInitStruct. + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * contains the configuration information for the RCC peripheral. + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @param FLatency FLASH Latency, this parameter depend on device selected + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * and updated by HAL_RCC_GetHCLKFreq() function called within this function + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note The HSI is used (enabled by hardware) as system clock source after + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * startup from Reset, wake-up from STOP and STANDBY mode, or in case + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * of failure of the HSE used directly or indirectly as system clock + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * (if the Clock Security System CSS is enabled). + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note A switch from one clock source to another occurs only if the target + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * clock source is ready (clock stable after startup delay or PLL locked). + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * If a clock source which is not yet ready is selected, the switch will + 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * occur when the clock source will be ready. + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * You can use HAL_RCC_GetClockConfig() function to know which clock is + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * currently used as system clock source. + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note Depending on the device voltage range, the software has to set correctly + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * (for more details refer to section above "Initialization/de-initialization functions") + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval None + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ + 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + ARM GAS /tmp/ccemvyj9.s page 39 + + + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t tickstart = 0; + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check Null pointer */ + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (RCC_ClkInitStruct == NULL) + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the parameters */ + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_FLASH_LATENCY(FLatency)); + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** must be correctly programmed according to the frequency of the CPU clock + 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** (HCLK) and the supply voltage of the device. */ + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Increasing the CPU frequency */ + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (FLatency > __HAL_FLASH_GET_LATENCY()) + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_FLASH_SET_LATENCY(FLatency); + 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check that the new number of wait states is taken into account to access the Flash + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** memory by reading the FLASH_ACR register */ + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (__HAL_FLASH_GET_LATENCY() != FLatency) + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /*-------------------------- HCLK Configuration --------------------------*/ + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Set the highest APBx dividers in order to ensure that we do not go through + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** a non-spec phase whatever we decrease or increase HCLK. */ + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Set the new HCLK clock divider */ + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /*------------------------- SYSCLK Configuration ---------------------------*/ + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* HSE is selected as System Clock Source */ + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + ARM GAS /tmp/ccemvyj9.s page 40 + + + 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the HSE ready flag */ + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* PLL is selected as System Clock Source */ + 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the PLL ready flag */ + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* HSI is selected as System Clock Source */ + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the HSI ready flag */ + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get Start Tick*/ + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_TIMEOUT; + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Decreasing the number of wait states because of lower CPU frequency */ + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (FLatency < __HAL_FLASH_GET_LATENCY()) + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_FLASH_SET_LATENCY(FLatency); + 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check that the new number of wait states is taken into account to access the Flash + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** memory by reading the FLASH_ACR register */ + 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (__HAL_FLASH_GET_LATENCY() != FLatency) + 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_ERROR; + 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /*-------------------------- PCLK1 Configuration ---------------------------*/ + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + ARM GAS /tmp/ccemvyj9.s page 41 + + + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /*-------------------------- PCLK2 Configuration ---------------------------*/ + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Update the SystemCoreClock global variable */ + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_C + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Configure the source of time base considering new system clocks settings*/ + 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_InitTick(uwTickPrio); + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return HAL_OK; + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @} + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief RCC clocks control functions + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** @verbatim + 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** =============================================================================== + 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** ##### Peripheral Control functions ##### + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** =============================================================================== + 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** [..] + 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** This subsection provides a set of functions allowing to control the RCC Clocks + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** frequencies. + 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** @endverbatim + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @{ + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** + 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note PA8/PC9 should be configured in alternate function mode. + 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @param RCC_MCOx specifies the output direction for the clock source. + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * This parameter can be one of the following values: + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). + 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @param RCC_MCOSource specifies the clock source to output. + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * This parameter can be one of the following values: + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source + 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @param RCC_MCODiv specifies the MCOx prescaler. + ARM GAS /tmp/ccemvyj9.s page 42 + + + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * This parameter can be one of the following values: + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCODIV_1: no division applied to MCOx clock + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval None + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ + 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1228 .loc 1 904 1 is_stmt 1 view -0 + 1229 .cfi_startproc + 1230 @ args = 0, pretend = 0, frame = 32 + 1231 @ frame_needed = 0, uses_anonymous_args = 0 + 1232 .loc 1 904 1 is_stmt 0 view .LVU392 + 1233 0000 70B5 push {r4, r5, r6, lr} + 1234 .LCFI7: + 1235 .cfi_def_cfa_offset 16 + 1236 .cfi_offset 4, -16 + 1237 .cfi_offset 5, -12 + 1238 .cfi_offset 6, -8 + 1239 .cfi_offset 14, -4 + 1240 0002 88B0 sub sp, sp, #32 + 1241 .LCFI8: + 1242 .cfi_def_cfa_offset 48 + 1243 0004 0C46 mov r4, r1 + 1244 0006 1546 mov r5, r2 + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitTypeDef GPIO_InitStruct; + 1245 .loc 1 905 3 is_stmt 1 view .LVU393 + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check the parameters */ + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_MCO(RCC_MCOx)); + 1246 .loc 1 907 3 view .LVU394 + 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + 1247 .loc 1 908 3 view .LVU395 + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* RCC_MCO1 */ + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (RCC_MCOx == RCC_MCO1) + 1248 .loc 1 910 3 view .LVU396 + 1249 .loc 1 910 6 is_stmt 0 view .LVU397 + 1250 0008 F8B9 cbnz r0, .L129 + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + 1251 .loc 1 912 5 is_stmt 1 view .LVU398 + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* MCO1 Clock Enable */ + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MCO1_CLK_ENABLE(); + 1252 .loc 1 915 5 view .LVU399 + 1253 .LBB5: + 1254 .loc 1 915 5 view .LVU400 + 1255 .loc 1 915 5 view .LVU401 + 1256 000a 204E ldr r6, .L132 + 1257 000c 336B ldr r3, [r6, #48] + 1258 000e 43F00103 orr r3, r3, #1 + 1259 0012 3363 str r3, [r6, #48] + 1260 .loc 1 915 5 view .LVU402 + 1261 0014 336B ldr r3, [r6, #48] + 1262 0016 03F00103 and r3, r3, #1 + 1263 001a 0193 str r3, [sp, #4] + ARM GAS /tmp/ccemvyj9.s page 43 + + + 1264 .loc 1 915 5 view .LVU403 + 1265 001c 019B ldr r3, [sp, #4] + 1266 .LBE5: + 1267 .loc 1 915 5 view .LVU404 + 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Configure the MCO1 pin in alternate function mode */ + 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Pin = MCO1_PIN; + 1268 .loc 1 918 5 view .LVU405 + 1269 .loc 1 918 25 is_stmt 0 view .LVU406 + 1270 001e 4FF48073 mov r3, #256 + 1271 0022 0393 str r3, [sp, #12] + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 1272 .loc 1 919 5 is_stmt 1 view .LVU407 + 1273 .loc 1 919 26 is_stmt 0 view .LVU408 + 1274 0024 0223 movs r3, #2 + 1275 0026 0493 str r3, [sp, #16] + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + 1276 .loc 1 920 5 is_stmt 1 view .LVU409 + 1277 .loc 1 920 27 is_stmt 0 view .LVU410 + 1278 0028 0323 movs r3, #3 + 1279 002a 0693 str r3, [sp, #24] + 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 1280 .loc 1 921 5 is_stmt 1 view .LVU411 + 1281 .loc 1 921 26 is_stmt 0 view .LVU412 + 1282 002c 0023 movs r3, #0 + 1283 002e 0593 str r3, [sp, #20] + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + 1284 .loc 1 922 5 is_stmt 1 view .LVU413 + 1285 .loc 1 922 31 is_stmt 0 view .LVU414 + 1286 0030 0793 str r3, [sp, #28] + 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); + 1287 .loc 1 923 5 is_stmt 1 view .LVU415 + 1288 0032 03A9 add r1, sp, #12 + 1289 .LVL91: + 1290 .loc 1 923 5 is_stmt 0 view .LVU416 + 1291 0034 1648 ldr r0, .L132+4 + 1292 .LVL92: + 1293 .loc 1 923 5 view .LVU417 + 1294 0036 FFF7FEFF bl HAL_GPIO_Init + 1295 .LVL93: + 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */ + 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); + 1296 .loc 1 926 5 is_stmt 1 view .LVU418 + 1297 003a B368 ldr r3, [r6, #8] + 1298 003c 23F0EC63 bic r3, r3, #123731968 + 1299 0040 2543 orrs r5, r5, r4 + 1300 .LVL94: + 1301 .loc 1 926 5 is_stmt 0 view .LVU419 + 1302 0042 1D43 orrs r5, r5, r3 + 1303 0044 B560 str r5, [r6, #8] + 1304 .LVL95: + 1305 .L128: + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); + ARM GAS /tmp/ccemvyj9.s page 44 + + + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* MCO2 Clock Enable */ + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MCO2_CLK_ENABLE(); + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Configure the MCO2 pin in alternate function mode */ + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Pin = MCO2_PIN; + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */ + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3))); + 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1306 .loc 1 946 1 view .LVU420 + 1307 0046 08B0 add sp, sp, #32 + 1308 .LCFI9: + 1309 .cfi_remember_state + 1310 .cfi_def_cfa_offset 16 + 1311 @ sp needed + 1312 0048 70BD pop {r4, r5, r6, pc} + 1313 .LVL96: + 1314 .L129: + 1315 .LCFI10: + 1316 .cfi_restore_state + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1317 .loc 1 930 5 is_stmt 1 view .LVU421 + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1318 .loc 1 933 5 view .LVU422 + 1319 .LBB6: + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1320 .loc 1 933 5 view .LVU423 + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1321 .loc 1 933 5 view .LVU424 + 1322 004a 104E ldr r6, .L132 + 1323 004c 336B ldr r3, [r6, #48] + 1324 004e 43F00403 orr r3, r3, #4 + 1325 0052 3363 str r3, [r6, #48] + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1326 .loc 1 933 5 view .LVU425 + 1327 0054 336B ldr r3, [r6, #48] + 1328 0056 03F00403 and r3, r3, #4 + 1329 005a 0293 str r3, [sp, #8] + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1330 .loc 1 933 5 view .LVU426 + 1331 005c 029B ldr r3, [sp, #8] + 1332 .LBE6: + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1333 .loc 1 933 5 view .LVU427 + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 1334 .loc 1 936 5 view .LVU428 + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 1335 .loc 1 936 25 is_stmt 0 view .LVU429 + 1336 005e 4FF40073 mov r3, #512 + 1337 0062 0393 str r3, [sp, #12] + ARM GAS /tmp/ccemvyj9.s page 45 + + + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + 1338 .loc 1 937 5 is_stmt 1 view .LVU430 + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + 1339 .loc 1 937 26 is_stmt 0 view .LVU431 + 1340 0064 0223 movs r3, #2 + 1341 0066 0493 str r3, [sp, #16] + 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 1342 .loc 1 938 5 is_stmt 1 view .LVU432 + 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 1343 .loc 1 938 27 is_stmt 0 view .LVU433 + 1344 0068 0323 movs r3, #3 + 1345 006a 0693 str r3, [sp, #24] + 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + 1346 .loc 1 939 5 is_stmt 1 view .LVU434 + 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + 1347 .loc 1 939 26 is_stmt 0 view .LVU435 + 1348 006c 0023 movs r3, #0 + 1349 006e 0593 str r3, [sp, #20] + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); + 1350 .loc 1 940 5 is_stmt 1 view .LVU436 + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); + 1351 .loc 1 940 31 is_stmt 0 view .LVU437 + 1352 0070 0793 str r3, [sp, #28] + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1353 .loc 1 941 5 is_stmt 1 view .LVU438 + 1354 0072 03A9 add r1, sp, #12 + 1355 .LVL97: + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1356 .loc 1 941 5 is_stmt 0 view .LVU439 + 1357 0074 0748 ldr r0, .L132+8 + 1358 .LVL98: + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1359 .loc 1 941 5 view .LVU440 + 1360 0076 FFF7FEFF bl HAL_GPIO_Init + 1361 .LVL99: + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1362 .loc 1 944 5 is_stmt 1 view .LVU441 + 1363 007a B368 ldr r3, [r6, #8] + 1364 007c 23F07843 bic r3, r3, #-134217728 + 1365 0080 44EAC504 orr r4, r4, r5, lsl #3 + 1366 .LVL100: + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1367 .loc 1 944 5 is_stmt 0 view .LVU442 + 1368 0084 1C43 orrs r4, r4, r3 + 1369 0086 B460 str r4, [r6, #8] + 1370 .loc 1 946 1 view .LVU443 + 1371 0088 DDE7 b .L128 + 1372 .L133: + 1373 008a 00BF .align 2 + 1374 .L132: + 1375 008c 00380240 .word 1073887232 + 1376 0090 00000240 .word 1073872896 + 1377 0094 00080240 .word 1073874944 + 1378 .cfi_endproc + 1379 .LFE144: + 1381 .section .text.HAL_RCC_EnableCSS,"ax",%progbits + 1382 .align 1 + ARM GAS /tmp/ccemvyj9.s page 46 + + + 1383 .global HAL_RCC_EnableCSS + 1384 .syntax unified + 1385 .thumb + 1386 .thumb_func + 1388 HAL_RCC_EnableCSS: + 1389 .LFB145: + 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Enables the Clock Security System. + 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note If a failure is detected on the HSE oscillator clock, this oscillator + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * is automatically disabled and an interrupt is generated to inform the + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * software about the failure (Clock Security System Interrupt, CSSI), + 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * allowing the MCU to perform rescue operations. The CSSI is linked to + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector. + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval None + 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ + 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** void HAL_RCC_EnableCSS(void) + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1390 .loc 1 958 1 is_stmt 1 view -0 + 1391 .cfi_startproc + 1392 @ args = 0, pretend = 0, frame = 0 + 1393 @ frame_needed = 0, uses_anonymous_args = 0 + 1394 @ link register save eliminated. + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** SET_BIT(RCC->CR, RCC_CR_CSSON); + 1395 .loc 1 959 3 view .LVU445 + 1396 0000 024A ldr r2, .L135 + 1397 0002 1368 ldr r3, [r2] + 1398 0004 43F40023 orr r3, r3, #524288 + 1399 0008 1360 str r3, [r2] + 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1400 .loc 1 960 1 is_stmt 0 view .LVU446 + 1401 000a 7047 bx lr + 1402 .L136: + 1403 .align 2 + 1404 .L135: + 1405 000c 00380240 .word 1073887232 + 1406 .cfi_endproc + 1407 .LFE145: + 1409 .section .text.HAL_RCC_DisableCSS,"ax",%progbits + 1410 .align 1 + 1411 .global HAL_RCC_DisableCSS + 1412 .syntax unified + 1413 .thumb + 1414 .thumb_func + 1416 HAL_RCC_DisableCSS: + 1417 .LFB146: + 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** + 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Disables the Clock Security System. + 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval None + 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ + 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** void HAL_RCC_DisableCSS(void) + 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1418 .loc 1 967 1 is_stmt 1 view -0 + 1419 .cfi_startproc + 1420 @ args = 0, pretend = 0, frame = 0 + 1421 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccemvyj9.s page 47 + + + 1422 @ link register save eliminated. + 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_CSSON); + 1423 .loc 1 968 3 view .LVU448 + 1424 0000 024A ldr r2, .L138 + 1425 0002 1368 ldr r3, [r2] + 1426 0004 23F40023 bic r3, r3, #524288 + 1427 0008 1360 str r3, [r2] + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1428 .loc 1 969 1 is_stmt 0 view .LVU449 + 1429 000a 7047 bx lr + 1430 .L139: + 1431 .align 2 + 1432 .L138: + 1433 000c 00380240 .word 1073887232 + 1434 .cfi_endproc + 1435 .LFE146: + 1437 .global __aeabi_uldivmod + 1438 .section .text.HAL_RCC_GetSysClockFreq,"ax",%progbits + 1439 .align 1 + 1440 .global HAL_RCC_GetSysClockFreq + 1441 .syntax unified + 1442 .thumb + 1443 .thumb_func + 1445 HAL_RCC_GetSysClockFreq: + 1446 .LFB147: + 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** + 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Returns the SYSCLK frequency + 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * + 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note The system frequency computed by this function is not the real + 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * frequency in the chip. It is calculated based on the predefined + 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * constant and the selected clock source: + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors. + 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * 16 MHz) but the real value may vary depending on the variations + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * in voltage and temperature. + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * 25 MHz), user has to ensure that HSE_VALUE is same as the real + 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * frequency of the crystal used. Otherwise, this function may + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * have wrong result. + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * + 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note The result of this function could be not correct when using fractional + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * value for HSE crystal. + 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note This function can be used by the user application to compute the + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * baudrate for the communication peripherals or configure other parameters. + 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note Each time SYSCLK changes, this function must be called to update the + 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * right SYSCLK value. Otherwise, any configuration based on this function will be incorre + 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * + 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval SYSCLK frequency +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ +1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t HAL_RCC_GetSysClockFreq(void) + ARM GAS /tmp/ccemvyj9.s page 48 + + +1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1447 .loc 1 1002 1 is_stmt 1 view -0 + 1448 .cfi_startproc + 1449 @ args = 0, pretend = 0, frame = 0 + 1450 @ frame_needed = 0, uses_anonymous_args = 0 + 1451 0000 08B5 push {r3, lr} + 1452 .LCFI11: + 1453 .cfi_def_cfa_offset 8 + 1454 .cfi_offset 3, -8 + 1455 .cfi_offset 14, -4 +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t pllm = 0, pllvco = 0, pllp = 0; + 1456 .loc 1 1003 3 view .LVU451 + 1457 .LVL101: +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t sysclockfreq = 0; + 1458 .loc 1 1004 3 view .LVU452 +1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get SYSCLK source -------------------------------------------------------*/ +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** switch (RCC->CFGR & RCC_CFGR_SWS) + 1459 .loc 1 1007 3 view .LVU453 + 1460 .loc 1 1007 14 is_stmt 0 view .LVU454 + 1461 0002 264B ldr r3, .L147 + 1462 0004 9B68 ldr r3, [r3, #8] + 1463 .loc 1 1007 21 view .LVU455 + 1464 0006 03F00C03 and r3, r3, #12 + 1465 .loc 1 1007 3 view .LVU456 + 1466 000a 042B cmp r3, #4 + 1467 000c 41D0 beq .L144 + 1468 000e 082B cmp r3, #8 + 1469 0010 41D1 bne .L145 +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ +1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** sysclockfreq = HSI_VALUE; +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** break; +1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ +1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** sysclockfreq = HSE_VALUE; +1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** break; +1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */ +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN +1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** SYSCLK = PLL_VCO / PLLP */ +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + 1470 .loc 1 1023 7 is_stmt 1 view .LVU457 + 1471 .loc 1 1023 17 is_stmt 0 view .LVU458 + 1472 0012 224B ldr r3, .L147 + 1473 0014 5A68 ldr r2, [r3, #4] + 1474 .loc 1 1023 12 view .LVU459 + 1475 0016 02F03F02 and r2, r2, #63 + 1476 .LVL102: +1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) + 1477 .loc 1 1024 7 is_stmt 1 view .LVU460 + 1478 .loc 1 1024 11 is_stmt 0 view .LVU461 + 1479 001a 5B68 ldr r3, [r3, #4] + 1480 .loc 1 1024 10 view .LVU462 + ARM GAS /tmp/ccemvyj9.s page 49 + + + 1481 001c 13F4800F tst r3, #4194304 + 1482 0020 12D0 beq .L142 +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* HSE used as PLL clock source */ +1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) + 1483 .loc 1 1027 9 is_stmt 1 view .LVU463 + 1484 .loc 1 1027 70 is_stmt 0 view .LVU464 + 1485 0022 1E4B ldr r3, .L147 + 1486 0024 5968 ldr r1, [r3, #4] + 1487 .loc 1 1027 55 view .LVU465 + 1488 0026 C1F38811 ubfx r1, r1, #6, #9 + 1489 .loc 1 1027 52 view .LVU466 + 1490 002a 1D48 ldr r0, .L147+4 + 1491 .loc 1 1027 128 view .LVU467 + 1492 002c 0023 movs r3, #0 + 1493 002e A1FB0001 umull r0, r1, r1, r0 + 1494 0032 FFF7FEFF bl __aeabi_uldivmod + 1495 .LVL103: + 1496 .L143: +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* HSI used as PLL clock source */ +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) +1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2); + 1497 .loc 1 1034 7 is_stmt 1 view .LVU468 + 1498 .loc 1 1034 21 is_stmt 0 view .LVU469 + 1499 0036 194B ldr r3, .L147 + 1500 0038 5B68 ldr r3, [r3, #4] + 1501 .loc 1 1034 51 view .LVU470 + 1502 003a C3F30143 ubfx r3, r3, #16, #2 + 1503 .loc 1 1034 76 view .LVU471 + 1504 003e 0133 adds r3, r3, #1 + 1505 .loc 1 1034 12 view .LVU472 + 1506 0040 5B00 lsls r3, r3, #1 + 1507 .LVL104: +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** sysclockfreq = pllvco / pllp; + 1508 .loc 1 1036 7 is_stmt 1 view .LVU473 + 1509 .loc 1 1036 20 is_stmt 0 view .LVU474 + 1510 0042 B0FBF3F0 udiv r0, r0, r3 + 1511 .LVL105: +1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** break; + 1512 .loc 1 1037 7 is_stmt 1 view .LVU475 + 1513 .L140: +1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** default: +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** sysclockfreq = HSI_VALUE; +1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** break; +1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return sysclockfreq; +1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1514 .loc 1 1046 1 is_stmt 0 view .LVU476 + 1515 0046 08BD pop {r3, pc} + ARM GAS /tmp/ccemvyj9.s page 50 + + + 1516 .LVL106: + 1517 .L142: +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1518 .loc 1 1032 9 is_stmt 1 view .LVU477 +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1519 .loc 1 1032 70 is_stmt 0 view .LVU478 + 1520 0048 144B ldr r3, .L147 + 1521 004a 5868 ldr r0, [r3, #4] +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1522 .loc 1 1032 55 view .LVU479 + 1523 004c C0F38810 ubfx r0, r0, #6, #9 +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1524 .loc 1 1032 52 view .LVU480 + 1525 0050 4FEA401C lsl ip, r0, #5 + 1526 0054 BCEB000C subs ip, ip, r0 + 1527 0058 6EEB0E0E sbc lr, lr, lr + 1528 005c 4FEA8E13 lsl r3, lr, #6 + 1529 0060 43EA9C63 orr r3, r3, ip, lsr #26 + 1530 0064 4FEA8C11 lsl r1, ip, #6 + 1531 0068 B1EB0C01 subs r1, r1, ip + 1532 006c 63EB0E03 sbc r3, r3, lr + 1533 0070 DB00 lsls r3, r3, #3 + 1534 0072 43EA5173 orr r3, r3, r1, lsr #29 + 1535 0076 C900 lsls r1, r1, #3 + 1536 0078 11EB000C adds ip, r1, r0 + 1537 007c 43F10003 adc r3, r3, #0 + 1538 0080 9902 lsls r1, r3, #10 +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1539 .loc 1 1032 128 view .LVU481 + 1540 0082 0023 movs r3, #0 + 1541 0084 4FEA8C20 lsl r0, ip, #10 + 1542 0088 41EA9C51 orr r1, r1, ip, lsr #22 + 1543 008c FFF7FEFF bl __aeabi_uldivmod + 1544 .LVL107: +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1545 .loc 1 1032 128 view .LVU482 + 1546 0090 D1E7 b .L143 + 1547 .LVL108: + 1548 .L144: +1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** break; + 1549 .loc 1 1016 20 view .LVU483 + 1550 0092 0348 ldr r0, .L147+4 + 1551 0094 D7E7 b .L140 + 1552 .L145: +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1553 .loc 1 1007 3 view .LVU484 + 1554 0096 0348 ldr r0, .L147+8 + 1555 .LVL109: +1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1556 .loc 1 1045 3 is_stmt 1 view .LVU485 +1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1557 .loc 1 1045 10 is_stmt 0 view .LVU486 + 1558 0098 D5E7 b .L140 + 1559 .L148: + 1560 009a 00BF .align 2 + 1561 .L147: + 1562 009c 00380240 .word 1073887232 + ARM GAS /tmp/ccemvyj9.s page 51 + + + 1563 00a0 40787D01 .word 25000000 + 1564 00a4 0024F400 .word 16000000 + 1565 .cfi_endproc + 1566 .LFE147: + 1568 .section .text.HAL_RCC_ClockConfig,"ax",%progbits + 1569 .align 1 + 1570 .global HAL_RCC_ClockConfig + 1571 .syntax unified + 1572 .thumb + 1573 .thumb_func + 1575 HAL_RCC_ClockConfig: + 1576 .LVL110: + 1577 .LFB143: + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t tickstart = 0; + 1578 .loc 1 723 1 is_stmt 1 view -0 + 1579 .cfi_startproc + 1580 @ args = 0, pretend = 0, frame = 0 + 1581 @ frame_needed = 0, uses_anonymous_args = 0 + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1582 .loc 1 724 3 view .LVU488 + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1583 .loc 1 727 3 view .LVU489 + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1584 .loc 1 727 6 is_stmt 0 view .LVU490 + 1585 0000 0028 cmp r0, #0 + 1586 0002 00F0A080 beq .L164 + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t tickstart = 0; + 1587 .loc 1 723 1 view .LVU491 + 1588 0006 70B5 push {r4, r5, r6, lr} + 1589 .LCFI12: + 1590 .cfi_def_cfa_offset 16 + 1591 .cfi_offset 4, -16 + 1592 .cfi_offset 5, -12 + 1593 .cfi_offset 6, -8 + 1594 .cfi_offset 14, -4 + 1595 0008 0D46 mov r5, r1 + 1596 000a 0446 mov r4, r0 + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** assert_param(IS_FLASH_LATENCY(FLatency)); + 1597 .loc 1 733 3 is_stmt 1 view .LVU492 + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1598 .loc 1 734 3 view .LVU493 + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1599 .loc 1 741 3 view .LVU494 + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1600 .loc 1 741 18 is_stmt 0 view .LVU495 + 1601 000c 524B ldr r3, .L177 + 1602 000e 1B68 ldr r3, [r3] + 1603 0010 03F00F03 and r3, r3, #15 + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1604 .loc 1 741 6 view .LVU496 + 1605 0014 8B42 cmp r3, r1 + 1606 0016 0BD2 bcs .L151 + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1607 .loc 1 744 5 is_stmt 1 view .LVU497 + 1608 0018 4F4A ldr r2, .L177 + 1609 001a 1368 ldr r3, [r2] + 1610 001c 23F00F03 bic r3, r3, #15 + ARM GAS /tmp/ccemvyj9.s page 52 + + + 1611 0020 0B43 orrs r3, r3, r1 + 1612 0022 1360 str r3, [r2] + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1613 .loc 1 748 5 view .LVU498 + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1614 .loc 1 748 9 is_stmt 0 view .LVU499 + 1615 0024 1368 ldr r3, [r2] + 1616 0026 03F00F03 and r3, r3, #15 + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1617 .loc 1 748 8 view .LVU500 + 1618 002a 8B42 cmp r3, r1 + 1619 002c 40F08D80 bne .L165 + 1620 .L151: + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1621 .loc 1 755 3 is_stmt 1 view .LVU501 + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1622 .loc 1 755 26 is_stmt 0 view .LVU502 + 1623 0030 2368 ldr r3, [r4] + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1624 .loc 1 755 6 view .LVU503 + 1625 0032 13F0020F tst r3, #2 + 1626 0036 17D0 beq .L152 + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1627 .loc 1 759 5 is_stmt 1 view .LVU504 + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1628 .loc 1 759 8 is_stmt 0 view .LVU505 + 1629 0038 13F0040F tst r3, #4 + 1630 003c 04D0 beq .L153 + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1631 .loc 1 761 7 is_stmt 1 view .LVU506 + 1632 003e 474A ldr r2, .L177+4 + 1633 0040 9368 ldr r3, [r2, #8] + 1634 0042 43F4E053 orr r3, r3, #7168 + 1635 0046 9360 str r3, [r2, #8] + 1636 .L153: + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1637 .loc 1 764 5 view .LVU507 + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1638 .loc 1 764 28 is_stmt 0 view .LVU508 + 1639 0048 2368 ldr r3, [r4] + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1640 .loc 1 764 8 view .LVU509 + 1641 004a 13F0080F tst r3, #8 + 1642 004e 04D0 beq .L154 + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1643 .loc 1 766 7 is_stmt 1 view .LVU510 + 1644 0050 424A ldr r2, .L177+4 + 1645 0052 9368 ldr r3, [r2, #8] + 1646 0054 43F46043 orr r3, r3, #57344 + 1647 0058 9360 str r3, [r2, #8] + 1648 .L154: + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 1649 .loc 1 770 5 view .LVU511 + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1650 .loc 1 771 5 view .LVU512 + 1651 005a 404A ldr r2, .L177+4 + 1652 005c 9368 ldr r3, [r2, #8] + ARM GAS /tmp/ccemvyj9.s page 53 + + + 1653 005e 23F0F003 bic r3, r3, #240 + 1654 0062 A168 ldr r1, [r4, #8] + 1655 .LVL111: + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1656 .loc 1 771 5 is_stmt 0 view .LVU513 + 1657 0064 0B43 orrs r3, r3, r1 + 1658 0066 9360 str r3, [r2, #8] + 1659 .L152: + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1660 .loc 1 775 3 is_stmt 1 view .LVU514 + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1661 .loc 1 775 26 is_stmt 0 view .LVU515 + 1662 0068 2368 ldr r3, [r4] + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1663 .loc 1 775 6 view .LVU516 + 1664 006a 13F0010F tst r3, #1 + 1665 006e 31D0 beq .L155 + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1666 .loc 1 777 5 is_stmt 1 view .LVU517 + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1667 .loc 1 780 5 view .LVU518 + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1668 .loc 1 780 26 is_stmt 0 view .LVU519 + 1669 0070 6368 ldr r3, [r4, #4] + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1670 .loc 1 780 8 view .LVU520 + 1671 0072 012B cmp r3, #1 + 1672 0074 20D0 beq .L175 + 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1673 .loc 1 789 10 is_stmt 1 view .LVU521 + 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1674 .loc 1 789 13 is_stmt 0 view .LVU522 + 1675 0076 022B cmp r3, #2 + 1676 0078 25D0 beq .L176 + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1677 .loc 1 801 7 is_stmt 1 view .LVU523 + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1678 .loc 1 801 11 is_stmt 0 view .LVU524 + 1679 007a 384A ldr r2, .L177+4 + 1680 007c 1268 ldr r2, [r2] + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1681 .loc 1 801 10 view .LVU525 + 1682 007e 12F0020F tst r2, #2 + 1683 0082 64D0 beq .L168 + 1684 .L157: + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1685 .loc 1 807 5 is_stmt 1 view .LVU526 + 1686 0084 3549 ldr r1, .L177+4 + 1687 0086 8A68 ldr r2, [r1, #8] + 1688 0088 22F00302 bic r2, r2, #3 + 1689 008c 1343 orrs r3, r3, r2 + 1690 008e 8B60 str r3, [r1, #8] + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1691 .loc 1 810 5 view .LVU527 + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1692 .loc 1 810 17 is_stmt 0 view .LVU528 + 1693 0090 FFF7FEFF bl HAL_GetTick + ARM GAS /tmp/ccemvyj9.s page 54 + + + 1694 .LVL112: + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1695 .loc 1 810 17 view .LVU529 + 1696 0094 0646 mov r6, r0 + 1697 .LVL113: + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1698 .loc 1 812 5 is_stmt 1 view .LVU530 + 1699 .L159: + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1700 .loc 1 812 42 view .LVU531 + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1701 .loc 1 812 12 is_stmt 0 view .LVU532 + 1702 0096 314B ldr r3, .L177+4 + 1703 0098 9B68 ldr r3, [r3, #8] + 1704 009a 03F00C03 and r3, r3, #12 + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1705 .loc 1 812 63 view .LVU533 + 1706 009e 6268 ldr r2, [r4, #4] + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1707 .loc 1 812 42 view .LVU534 + 1708 00a0 B3EB820F cmp r3, r2, lsl #2 + 1709 00a4 16D0 beq .L155 + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1710 .loc 1 814 7 is_stmt 1 view .LVU535 + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1711 .loc 1 814 12 is_stmt 0 view .LVU536 + 1712 00a6 FFF7FEFF bl HAL_GetTick + 1713 .LVL114: + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1714 .loc 1 814 26 discriminator 1 view .LVU537 + 1715 00aa 801B subs r0, r0, r6 + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1716 .loc 1 814 10 discriminator 1 view .LVU538 + 1717 00ac 41F28833 movw r3, #5000 + 1718 00b0 9842 cmp r0, r3 + 1719 00b2 F0D9 bls .L159 + 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1720 .loc 1 816 16 view .LVU539 + 1721 00b4 0320 movs r0, #3 + 1722 00b6 45E0 b .L150 + 1723 .LVL115: + 1724 .L175: + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1725 .loc 1 783 7 is_stmt 1 view .LVU540 + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1726 .loc 1 783 11 is_stmt 0 view .LVU541 + 1727 00b8 284A ldr r2, .L177+4 + 1728 00ba 1268 ldr r2, [r2] + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1729 .loc 1 783 10 view .LVU542 + 1730 00bc 12F4003F tst r2, #131072 + 1731 00c0 E0D1 bne .L157 + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1732 .loc 1 785 16 view .LVU543 + 1733 00c2 0120 movs r0, #1 + 1734 .LVL116: + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + ARM GAS /tmp/ccemvyj9.s page 55 + + + 1735 .loc 1 785 16 view .LVU544 + 1736 00c4 3EE0 b .L150 + 1737 .LVL117: + 1738 .L176: + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1739 .loc 1 792 7 is_stmt 1 view .LVU545 + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1740 .loc 1 792 11 is_stmt 0 view .LVU546 + 1741 00c6 254A ldr r2, .L177+4 + 1742 00c8 1268 ldr r2, [r2] + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1743 .loc 1 792 10 view .LVU547 + 1744 00ca 12F0007F tst r2, #33554432 + 1745 00ce D9D1 bne .L157 + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1746 .loc 1 794 16 view .LVU548 + 1747 00d0 0120 movs r0, #1 + 1748 .LVL118: + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1749 .loc 1 794 16 view .LVU549 + 1750 00d2 37E0 b .L150 + 1751 .LVL119: + 1752 .L155: + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1753 .loc 1 822 3 is_stmt 1 view .LVU550 + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1754 .loc 1 822 18 is_stmt 0 view .LVU551 + 1755 00d4 204B ldr r3, .L177 + 1756 00d6 1B68 ldr r3, [r3] + 1757 00d8 03F00F03 and r3, r3, #15 + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1758 .loc 1 822 6 view .LVU552 + 1759 00dc AB42 cmp r3, r5 + 1760 00de 0AD9 bls .L161 + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1761 .loc 1 825 5 is_stmt 1 view .LVU553 + 1762 00e0 1D4A ldr r2, .L177 + 1763 00e2 1368 ldr r3, [r2] + 1764 00e4 23F00F03 bic r3, r3, #15 + 1765 00e8 2B43 orrs r3, r3, r5 + 1766 00ea 1360 str r3, [r2] + 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1767 .loc 1 829 5 view .LVU554 + 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1768 .loc 1 829 9 is_stmt 0 view .LVU555 + 1769 00ec 1368 ldr r3, [r2] + 1770 00ee 03F00F03 and r3, r3, #15 + 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1771 .loc 1 829 8 view .LVU556 + 1772 00f2 AB42 cmp r3, r5 + 1773 00f4 2DD1 bne .L170 + 1774 .L161: + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1775 .loc 1 836 3 is_stmt 1 view .LVU557 + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1776 .loc 1 836 26 is_stmt 0 view .LVU558 + 1777 00f6 2368 ldr r3, [r4] + ARM GAS /tmp/ccemvyj9.s page 56 + + + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1778 .loc 1 836 6 view .LVU559 + 1779 00f8 13F0040F tst r3, #4 + 1780 00fc 06D0 beq .L162 + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 1781 .loc 1 838 5 is_stmt 1 view .LVU560 + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1782 .loc 1 839 5 view .LVU561 + 1783 00fe 174A ldr r2, .L177+4 + 1784 0100 9368 ldr r3, [r2, #8] + 1785 0102 23F4E053 bic r3, r3, #7168 + 1786 0106 E168 ldr r1, [r4, #12] + 1787 0108 0B43 orrs r3, r3, r1 + 1788 010a 9360 str r3, [r2, #8] + 1789 .L162: + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1790 .loc 1 843 3 view .LVU562 + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1791 .loc 1 843 26 is_stmt 0 view .LVU563 + 1792 010c 2368 ldr r3, [r4] + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1793 .loc 1 843 6 view .LVU564 + 1794 010e 13F0080F tst r3, #8 + 1795 0112 07D0 beq .L163 + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + 1796 .loc 1 845 5 is_stmt 1 view .LVU565 + 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1797 .loc 1 846 5 view .LVU566 + 1798 0114 114A ldr r2, .L177+4 + 1799 0116 9368 ldr r3, [r2, #8] + 1800 0118 23F46043 bic r3, r3, #57344 + 1801 011c 2169 ldr r1, [r4, #16] + 1802 011e 43EAC103 orr r3, r3, r1, lsl #3 + 1803 0122 9360 str r3, [r2, #8] + 1804 .L163: + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1805 .loc 1 850 3 view .LVU567 + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1806 .loc 1 850 21 is_stmt 0 view .LVU568 + 1807 0124 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1808 .LVL120: + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1809 .loc 1 850 68 discriminator 1 view .LVU569 + 1810 0128 0C4B ldr r3, .L177+4 + 1811 012a 9B68 ldr r3, [r3, #8] + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1812 .loc 1 850 92 discriminator 1 view .LVU570 + 1813 012c C3F30313 ubfx r3, r3, #4, #4 + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1814 .loc 1 850 63 discriminator 1 view .LVU571 + 1815 0130 0B4A ldr r2, .L177+8 + 1816 0132 D35C ldrb r3, [r2, r3] @ zero_extendqisi2 + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1817 .loc 1 850 47 discriminator 1 view .LVU572 + 1818 0134 D840 lsrs r0, r0, r3 + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1819 .loc 1 850 19 discriminator 1 view .LVU573 + ARM GAS /tmp/ccemvyj9.s page 57 + + + 1820 0136 0B4B ldr r3, .L177+12 + 1821 0138 1860 str r0, [r3] + 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1822 .loc 1 853 3 is_stmt 1 view .LVU574 + 1823 013a 0B4B ldr r3, .L177+16 + 1824 013c 1868 ldr r0, [r3] + 1825 013e FFF7FEFF bl HAL_InitTick + 1826 .LVL121: + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1827 .loc 1 855 3 view .LVU575 + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1828 .loc 1 855 10 is_stmt 0 view .LVU576 + 1829 0142 0020 movs r0, #0 + 1830 .L150: + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1831 .loc 1 856 1 view .LVU577 + 1832 0144 70BD pop {r4, r5, r6, pc} + 1833 .LVL122: + 1834 .L164: + 1835 .LCFI13: + 1836 .cfi_def_cfa_offset 0 + 1837 .cfi_restore 4 + 1838 .cfi_restore 5 + 1839 .cfi_restore 6 + 1840 .cfi_restore 14 + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1841 .loc 1 729 12 view .LVU578 + 1842 0146 0120 movs r0, #1 + 1843 .LVL123: + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 1844 .loc 1 856 1 view .LVU579 + 1845 0148 7047 bx lr + 1846 .LVL124: + 1847 .L165: + 1848 .LCFI14: + 1849 .cfi_def_cfa_offset 16 + 1850 .cfi_offset 4, -16 + 1851 .cfi_offset 5, -12 + 1852 .cfi_offset 6, -8 + 1853 .cfi_offset 14, -4 + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1854 .loc 1 750 14 view .LVU580 + 1855 014a 0120 movs r0, #1 + 1856 .LVL125: + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1857 .loc 1 750 14 view .LVU581 + 1858 014c FAE7 b .L150 + 1859 .LVL126: + 1860 .L168: + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1861 .loc 1 803 16 view .LVU582 + 1862 014e 0120 movs r0, #1 + 1863 .LVL127: + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1864 .loc 1 803 16 view .LVU583 + 1865 0150 F8E7 b .L150 + 1866 .LVL128: + ARM GAS /tmp/ccemvyj9.s page 58 + + + 1867 .L170: + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1868 .loc 1 831 14 view .LVU584 + 1869 0152 0120 movs r0, #1 + 1870 0154 F6E7 b .L150 + 1871 .L178: + 1872 0156 00BF .align 2 + 1873 .L177: + 1874 0158 003C0240 .word 1073888256 + 1875 015c 00380240 .word 1073887232 + 1876 0160 00000000 .word AHBPrescTable + 1877 0164 00000000 .word SystemCoreClock + 1878 0168 00000000 .word uwTickPrio + 1879 .cfi_endproc + 1880 .LFE143: + 1882 .section .text.HAL_RCC_GetHCLKFreq,"ax",%progbits + 1883 .align 1 + 1884 .global HAL_RCC_GetHCLKFreq + 1885 .syntax unified + 1886 .thumb + 1887 .thumb_func + 1889 HAL_RCC_GetHCLKFreq: + 1890 .LFB148: +1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** +1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Returns the HCLK frequency +1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note Each time HCLK changes, this function must be called to update the +1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * right HCLK value. Otherwise, any configuration based on this function will be incorrect +1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval HCLK frequency +1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ +1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t HAL_RCC_GetHCLKFreq(void) +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1891 .loc 1 1056 1 is_stmt 1 view -0 + 1892 .cfi_startproc + 1893 @ args = 0, pretend = 0, frame = 0 + 1894 @ frame_needed = 0, uses_anonymous_args = 0 + 1895 @ link register save eliminated. +1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return SystemCoreClock; + 1896 .loc 1 1057 3 view .LVU586 +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1897 .loc 1 1058 1 is_stmt 0 view .LVU587 + 1898 0000 014B ldr r3, .L180 + 1899 0002 1868 ldr r0, [r3] + 1900 0004 7047 bx lr + 1901 .L181: + 1902 0006 00BF .align 2 + 1903 .L180: + 1904 0008 00000000 .word SystemCoreClock + 1905 .cfi_endproc + 1906 .LFE148: + 1908 .section .text.HAL_RCC_GetPCLK1Freq,"ax",%progbits + 1909 .align 1 + 1910 .global HAL_RCC_GetPCLK1Freq + 1911 .syntax unified + 1912 .thumb + 1913 .thumb_func + ARM GAS /tmp/ccemvyj9.s page 59 + + + 1915 HAL_RCC_GetPCLK1Freq: + 1916 .LFB149: +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** +1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Returns the PCLK1 frequency +1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note Each time PCLK1 changes, this function must be called to update the +1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * right PCLK1 value. Otherwise, any configuration based on this function will be incorrec +1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval PCLK1 frequency +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ +1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t HAL_RCC_GetPCLK1Freq(void) +1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1917 .loc 1 1067 1 is_stmt 1 view -0 + 1918 .cfi_startproc + 1919 @ args = 0, pretend = 0, frame = 0 + 1920 @ frame_needed = 0, uses_anonymous_args = 0 + 1921 0000 08B5 push {r3, lr} + 1922 .LCFI15: + 1923 .cfi_def_cfa_offset 8 + 1924 .cfi_offset 3, -8 + 1925 .cfi_offset 14, -4 +1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos + 1926 .loc 1 1069 3 view .LVU589 + 1927 .loc 1 1069 11 is_stmt 0 view .LVU590 + 1928 0002 FFF7FEFF bl HAL_RCC_GetHCLKFreq + 1929 .LVL129: + 1930 .loc 1 1069 54 discriminator 1 view .LVU591 + 1931 0006 044B ldr r3, .L184 + 1932 0008 9B68 ldr r3, [r3, #8] + 1933 .loc 1 1069 79 discriminator 1 view .LVU592 + 1934 000a C3F38223 ubfx r3, r3, #10, #3 + 1935 .loc 1 1069 49 discriminator 1 view .LVU593 + 1936 000e 034A ldr r2, .L184+4 + 1937 0010 D35C ldrb r3, [r2, r3] @ zero_extendqisi2 +1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1938 .loc 1 1070 1 view .LVU594 + 1939 0012 D840 lsrs r0, r0, r3 + 1940 0014 08BD pop {r3, pc} + 1941 .L185: + 1942 0016 00BF .align 2 + 1943 .L184: + 1944 0018 00380240 .word 1073887232 + 1945 001c 00000000 .word APBPrescTable + 1946 .cfi_endproc + 1947 .LFE149: + 1949 .section .text.HAL_RCC_GetPCLK2Freq,"ax",%progbits + 1950 .align 1 + 1951 .global HAL_RCC_GetPCLK2Freq + 1952 .syntax unified + 1953 .thumb + 1954 .thumb_func + 1956 HAL_RCC_GetPCLK2Freq: + 1957 .LFB150: +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Returns the PCLK2 frequency +1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note Each time PCLK2 changes, this function must be called to update the + ARM GAS /tmp/ccemvyj9.s page 60 + + +1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * right PCLK2 value. Otherwise, any configuration based on this function will be incorrec +1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval PCLK2 frequency +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ +1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** uint32_t HAL_RCC_GetPCLK2Freq(void) +1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 1958 .loc 1 1079 1 is_stmt 1 view -0 + 1959 .cfi_startproc + 1960 @ args = 0, pretend = 0, frame = 0 + 1961 @ frame_needed = 0, uses_anonymous_args = 0 + 1962 0000 08B5 push {r3, lr} + 1963 .LCFI16: + 1964 .cfi_def_cfa_offset 8 + 1965 .cfi_offset 3, -8 + 1966 .cfi_offset 14, -4 +1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ +1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos + 1967 .loc 1 1081 3 view .LVU596 + 1968 .loc 1 1081 11 is_stmt 0 view .LVU597 + 1969 0002 FFF7FEFF bl HAL_RCC_GetHCLKFreq + 1970 .LVL130: + 1971 .loc 1 1081 54 discriminator 1 view .LVU598 + 1972 0006 044B ldr r3, .L188 + 1973 0008 9B68 ldr r3, [r3, #8] + 1974 .loc 1 1081 79 discriminator 1 view .LVU599 + 1975 000a C3F34233 ubfx r3, r3, #13, #3 + 1976 .loc 1 1081 49 discriminator 1 view .LVU600 + 1977 000e 034A ldr r2, .L188+4 + 1978 0010 D35C ldrb r3, [r2, r3] @ zero_extendqisi2 +1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 1979 .loc 1 1082 1 view .LVU601 + 1980 0012 D840 lsrs r0, r0, r3 + 1981 0014 08BD pop {r3, pc} + 1982 .L189: + 1983 0016 00BF .align 2 + 1984 .L188: + 1985 0018 00380240 .word 1073887232 + 1986 001c 00000000 .word APBPrescTable + 1987 .cfi_endproc + 1988 .LFE150: + 1990 .section .text.HAL_RCC_GetOscConfig,"ax",%progbits + 1991 .align 1 + 1992 .global HAL_RCC_GetOscConfig + 1993 .syntax unified + 1994 .thumb + 1995 .thumb_func + 1997 HAL_RCC_GetOscConfig: + 1998 .LVL131: + 1999 .LFB151: +1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Configures the RCC_OscInitStruct according to the internal +1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * RCC configuration registers. +1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that +1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * will be configured. +1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval None +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) + ARM GAS /tmp/ccemvyj9.s page 61 + + +1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 2000 .loc 1 1092 1 is_stmt 1 view -0 + 2001 .cfi_startproc + 2002 @ args = 0, pretend = 0, frame = 0 + 2003 @ frame_needed = 0, uses_anonymous_args = 0 + 2004 @ link register save eliminated. +1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Set all possible values for the Oscillator type parameter ---------------*/ +1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLA + 2005 .loc 1 1094 3 view .LVU603 + 2006 .loc 1 1094 37 is_stmt 0 view .LVU604 + 2007 0000 0F23 movs r3, #15 + 2008 0002 0360 str r3, [r0] +1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the HSE configuration -----------------------------------------------*/ +1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + 2009 .loc 1 1097 3 is_stmt 1 view .LVU605 + 2010 .loc 1 1097 11 is_stmt 0 view .LVU606 + 2011 0004 354B ldr r3, .L203 + 2012 0006 1B68 ldr r3, [r3] + 2013 .loc 1 1097 6 view .LVU607 + 2014 0008 13F4802F tst r3, #262144 + 2015 000c 46D0 beq .L191 +1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + 2016 .loc 1 1099 5 is_stmt 1 view .LVU608 + 2017 .loc 1 1099 33 is_stmt 0 view .LVU609 + 2018 000e 4FF4A023 mov r3, #327680 + 2019 0012 4360 str r3, [r0, #4] + 2020 .L192: +1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) +1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_ON; +1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else +1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_OFF; +1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the HSI configuration -----------------------------------------------*/ +1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + 2021 .loc 1 1111 3 is_stmt 1 view .LVU610 + 2022 .loc 1 1111 11 is_stmt 0 view .LVU611 + 2023 0014 314B ldr r3, .L203 + 2024 0016 1B68 ldr r3, [r3] + 2025 .loc 1 1111 6 view .LVU612 + 2026 0018 13F0010F tst r3, #1 + 2027 001c 4AD0 beq .L194 +1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->HSIState = RCC_HSI_ON; + 2028 .loc 1 1113 5 is_stmt 1 view .LVU613 + 2029 .loc 1 1113 33 is_stmt 0 view .LVU614 + 2030 001e 0123 movs r3, #1 + 2031 0020 C360 str r3, [r0, #12] + 2032 .L195: +1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else + ARM GAS /tmp/ccemvyj9.s page 62 + + +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->HSIState = RCC_HSI_OFF; +1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_ + 2033 .loc 1 1120 3 is_stmt 1 view .LVU615 + 2034 .loc 1 1120 59 is_stmt 0 view .LVU616 + 2035 0022 2E4A ldr r2, .L203 + 2036 0024 1368 ldr r3, [r2] + 2037 .loc 1 1120 44 view .LVU617 + 2038 0026 C3F3C403 ubfx r3, r3, #3, #5 + 2039 .loc 1 1120 42 view .LVU618 + 2040 002a 0361 str r3, [r0, #16] +1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the LSE configuration -----------------------------------------------*/ +1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + 2041 .loc 1 1123 3 is_stmt 1 view .LVU619 + 2042 .loc 1 1123 11 is_stmt 0 view .LVU620 + 2043 002c 136F ldr r3, [r2, #112] + 2044 .loc 1 1123 6 view .LVU621 + 2045 002e 13F0040F tst r3, #4 + 2046 0032 42D0 beq .L196 +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + 2047 .loc 1 1125 5 is_stmt 1 view .LVU622 + 2048 .loc 1 1125 33 is_stmt 0 view .LVU623 + 2049 0034 0523 movs r3, #5 + 2050 0036 8360 str r3, [r0, #8] + 2051 .L197: +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_ON; +1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else +1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_OFF; +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the LSI configuration -----------------------------------------------*/ +1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + 2052 .loc 1 1137 3 is_stmt 1 view .LVU624 + 2053 .loc 1 1137 11 is_stmt 0 view .LVU625 + 2054 0038 284B ldr r3, .L203 + 2055 003a 5B6F ldr r3, [r3, #116] + 2056 .loc 1 1137 6 view .LVU626 + 2057 003c 13F0010F tst r3, #1 + 2058 0040 46D0 beq .L199 +1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->LSIState = RCC_LSI_ON; + 2059 .loc 1 1139 5 is_stmt 1 view .LVU627 + 2060 .loc 1 1139 33 is_stmt 0 view .LVU628 + 2061 0042 0123 movs r3, #1 + 2062 0044 4361 str r3, [r0, #20] + 2063 .L200: +1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else + ARM GAS /tmp/ccemvyj9.s page 63 + + +1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->LSIState = RCC_LSI_OFF; +1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the PLL configuration -----------------------------------------------*/ +1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + 2064 .loc 1 1147 3 is_stmt 1 view .LVU629 + 2065 .loc 1 1147 11 is_stmt 0 view .LVU630 + 2066 0046 254B ldr r3, .L203 + 2067 0048 1B68 ldr r3, [r3] + 2068 .loc 1 1147 6 view .LVU631 + 2069 004a 13F0807F tst r3, #16777216 + 2070 004e 42D0 beq .L201 +1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + 2071 .loc 1 1149 5 is_stmt 1 view .LVU632 + 2072 .loc 1 1149 37 is_stmt 0 view .LVU633 + 2073 0050 0223 movs r3, #2 + 2074 0052 8361 str r3, [r0, #24] + 2075 .L202: +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** else +1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; +1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + 2076 .loc 1 1155 3 is_stmt 1 view .LVU634 + 2077 .loc 1 1155 52 is_stmt 0 view .LVU635 + 2078 0054 214A ldr r2, .L203 + 2079 0056 5368 ldr r3, [r2, #4] + 2080 .loc 1 1155 38 view .LVU636 + 2081 0058 03F48003 and r3, r3, #4194304 + 2082 .loc 1 1155 36 view .LVU637 + 2083 005c C361 str r3, [r0, #28] +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); + 2084 .loc 1 1156 3 is_stmt 1 view .LVU638 + 2085 .loc 1 1156 47 is_stmt 0 view .LVU639 + 2086 005e 5368 ldr r3, [r2, #4] + 2087 .loc 1 1156 33 view .LVU640 + 2088 0060 03F03F03 and r3, r3, #63 + 2089 .loc 1 1156 31 view .LVU641 + 2090 0064 0362 str r3, [r0, #32] +1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Po + 2091 .loc 1 1157 3 is_stmt 1 view .LVU642 + 2092 .loc 1 1157 48 is_stmt 0 view .LVU643 + 2093 0066 5368 ldr r3, [r2, #4] + 2094 .loc 1 1157 33 view .LVU644 + 2095 0068 C3F38813 ubfx r3, r3, #6, #9 + 2096 .loc 1 1157 31 view .LVU645 + 2097 006c 4362 str r3, [r0, #36] +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0 + 2098 .loc 1 1158 3 is_stmt 1 view .LVU646 + 2099 .loc 1 1158 50 is_stmt 0 view .LVU647 + 2100 006e 5368 ldr r3, [r2, #4] + 2101 .loc 1 1158 60 view .LVU648 + 2102 0070 03F44033 and r3, r3, #196608 + 2103 .loc 1 1158 80 view .LVU649 + ARM GAS /tmp/ccemvyj9.s page 64 + + + 2104 0074 03F58033 add r3, r3, #65536 + 2105 .loc 1 1158 33 view .LVU650 + 2106 0078 DB0B lsrs r3, r3, #15 + 2107 .loc 1 1158 31 view .LVU651 + 2108 007a 8362 str r3, [r0, #40] +1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Po + 2109 .loc 1 1159 3 is_stmt 1 view .LVU652 + 2110 .loc 1 1159 48 is_stmt 0 view .LVU653 + 2111 007c 5368 ldr r3, [r2, #4] + 2112 .loc 1 1159 33 view .LVU654 + 2113 007e C3F30363 ubfx r3, r3, #24, #4 + 2114 .loc 1 1159 31 view .LVU655 + 2115 0082 C362 str r3, [r0, #44] +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #if defined (RCC_PLLCFGR_PLLR) +1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PL + 2116 .loc 1 1161 3 is_stmt 1 view .LVU656 + 2117 .loc 1 1161 48 is_stmt 0 view .LVU657 + 2118 0084 5368 ldr r3, [r2, #4] + 2119 .loc 1 1161 58 view .LVU658 + 2120 0086 03F0E043 and r3, r3, #1879048192 + 2121 .LVL132: + 2122 .LBB7: + 2123 .LBI7: + 2124 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccemvyj9.s page 65 + + + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + ARM GAS /tmp/ccemvyj9.s page 66 + + + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + ARM GAS /tmp/ccemvyj9.s page 67 + + + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccemvyj9.s page 68 + + + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccemvyj9.s page 69 + + + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + ARM GAS /tmp/ccemvyj9.s page 70 + + + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccemvyj9.s page 71 + + + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + ARM GAS /tmp/ccemvyj9.s page 72 + + + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + ARM GAS /tmp/ccemvyj9.s page 73 + + + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + ARM GAS /tmp/ccemvyj9.s page 74 + + + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccemvyj9.s page 75 + + + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + ARM GAS /tmp/ccemvyj9.s page 76 + + + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + ARM GAS /tmp/ccemvyj9.s page 77 + + + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + ARM GAS /tmp/ccemvyj9.s page 78 + + + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccemvyj9.s page 79 + + + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 881:Drivers/CMSIS/Include/cmsis_gcc.h **** + 882:Drivers/CMSIS/Include/cmsis_gcc.h **** + 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier + 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. + 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) + ARM GAS /tmp/ccemvyj9.s page 80 + + + 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); + 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 892:Drivers/CMSIS/Include/cmsis_gcc.h **** + 893:Drivers/CMSIS/Include/cmsis_gcc.h **** + 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) + 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 + 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) + 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); + 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 906:Drivers/CMSIS/Include/cmsis_gcc.h **** + 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 911:Drivers/CMSIS/Include/cmsis_gcc.h **** + 912:Drivers/CMSIS/Include/cmsis_gcc.h **** + 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes + 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) + 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 922:Drivers/CMSIS/Include/cmsis_gcc.h **** + 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 926:Drivers/CMSIS/Include/cmsis_gcc.h **** + 927:Drivers/CMSIS/Include/cmsis_gcc.h **** + 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam + 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); + 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; + 940:Drivers/CMSIS/Include/cmsis_gcc.h **** + 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 945:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccemvyj9.s page 81 + + + 946:Drivers/CMSIS/Include/cmsis_gcc.h **** + 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) + 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v + 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate + 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate + 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value + 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) + 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; + 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) + 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; + 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); + 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 963:Drivers/CMSIS/Include/cmsis_gcc.h **** + 964:Drivers/CMSIS/Include/cmsis_gcc.h **** + 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint + 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. + 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula + 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. + 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break + 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) + 973:Drivers/CMSIS/Include/cmsis_gcc.h **** + 974:Drivers/CMSIS/Include/cmsis_gcc.h **** + 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value + 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. + 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) + 2125 .loc 2 981 31 is_stmt 1 view .LVU659 + 2126 .LBB8: + 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 2127 .loc 2 983 3 view .LVU660 + 984:Drivers/CMSIS/Include/cmsis_gcc.h **** + 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 2128 .loc 2 988 4 view .LVU661 + 2129 008a 4FF0E042 mov r2, #1879048192 + 2130 .syntax unified + 2131 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2132 008e 92FAA2F2 rbit r2, r2 + 2133 @ 0 "" 2 + 2134 .LVL133: + 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + 991:Drivers/CMSIS/Include/cmsis_gcc.h **** + 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ + ARM GAS /tmp/ccemvyj9.s page 82 + + + 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) + 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; + 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; + 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; + 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ +1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 2135 .loc 2 1001 3 view .LVU662 + 2136 .loc 2 1001 3 is_stmt 0 view .LVU663 + 2137 .thumb + 2138 .syntax unified + 2139 .LBE8: + 2140 .LBE7: + 2141 .loc 1 1161 33 discriminator 2 view .LVU664 + 2142 0092 B2FA82F2 clz r2, r2 + 2143 0096 D340 lsrs r3, r3, r2 + 2144 .loc 1 1161 31 discriminator 2 view .LVU665 + 2145 0098 0363 str r3, [r0, #48] +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** #endif +1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 2146 .loc 1 1163 1 view .LVU666 + 2147 009a 7047 bx lr + 2148 .L191: +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 2149 .loc 1 1101 8 is_stmt 1 view .LVU667 +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 2150 .loc 1 1101 16 is_stmt 0 view .LVU668 + 2151 009c 0F4B ldr r3, .L203 + 2152 009e 1B68 ldr r3, [r3] +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 2153 .loc 1 1101 11 view .LVU669 + 2154 00a0 13F4803F tst r3, #65536 + 2155 00a4 03D0 beq .L193 +1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 2156 .loc 1 1103 5 is_stmt 1 view .LVU670 +1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 2157 .loc 1 1103 33 is_stmt 0 view .LVU671 + 2158 00a6 4FF48033 mov r3, #65536 + 2159 00aa 4360 str r3, [r0, #4] + 2160 00ac B2E7 b .L192 + 2161 .L193: +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 2162 .loc 1 1107 5 is_stmt 1 view .LVU672 +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 2163 .loc 1 1107 33 is_stmt 0 view .LVU673 + 2164 00ae 0023 movs r3, #0 + 2165 00b0 4360 str r3, [r0, #4] + 2166 00b2 AFE7 b .L192 + 2167 .L194: +1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 2168 .loc 1 1117 5 is_stmt 1 view .LVU674 +1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 2169 .loc 1 1117 33 is_stmt 0 view .LVU675 + 2170 00b4 0023 movs r3, #0 + 2171 00b6 C360 str r3, [r0, #12] + ARM GAS /tmp/ccemvyj9.s page 83 + + + 2172 00b8 B3E7 b .L195 + 2173 .L196: +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 2174 .loc 1 1127 8 is_stmt 1 view .LVU676 +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 2175 .loc 1 1127 16 is_stmt 0 view .LVU677 + 2176 00ba 084B ldr r3, .L203 + 2177 00bc 1B6F ldr r3, [r3, #112] +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 2178 .loc 1 1127 11 view .LVU678 + 2179 00be 13F0010F tst r3, #1 + 2180 00c2 02D0 beq .L198 +1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 2181 .loc 1 1129 5 is_stmt 1 view .LVU679 +1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 2182 .loc 1 1129 33 is_stmt 0 view .LVU680 + 2183 00c4 0123 movs r3, #1 + 2184 00c6 8360 str r3, [r0, #8] + 2185 00c8 B6E7 b .L197 + 2186 .L198: +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 2187 .loc 1 1133 5 is_stmt 1 view .LVU681 +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 2188 .loc 1 1133 33 is_stmt 0 view .LVU682 + 2189 00ca 0023 movs r3, #0 + 2190 00cc 8360 str r3, [r0, #8] + 2191 00ce B3E7 b .L197 + 2192 .L199: +1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 2193 .loc 1 1143 5 is_stmt 1 view .LVU683 +1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 2194 .loc 1 1143 33 is_stmt 0 view .LVU684 + 2195 00d0 0023 movs r3, #0 + 2196 00d2 4361 str r3, [r0, #20] + 2197 00d4 B7E7 b .L200 + 2198 .L201: +1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 2199 .loc 1 1153 5 is_stmt 1 view .LVU685 +1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 2200 .loc 1 1153 37 is_stmt 0 view .LVU686 + 2201 00d6 0123 movs r3, #1 + 2202 00d8 8361 str r3, [r0, #24] + 2203 00da BBE7 b .L202 + 2204 .L204: + 2205 .align 2 + 2206 .L203: + 2207 00dc 00380240 .word 1073887232 + 2208 .cfi_endproc + 2209 .LFE151: + 2211 .section .text.HAL_RCC_GetClockConfig,"ax",%progbits + 2212 .align 1 + 2213 .global HAL_RCC_GetClockConfig + 2214 .syntax unified + 2215 .thumb + 2216 .thumb_func + 2218 HAL_RCC_GetClockConfig: + 2219 .LVL134: + ARM GAS /tmp/ccemvyj9.s page 84 + + + 2220 .LFB152: +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief Configures the RCC_ClkInitStruct according to the internal +1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * RCC configuration registers. +1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that +1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * will be configured. +1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @param pFLatency Pointer on the Flash Latency. +1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval None +1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ +1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 2221 .loc 1 1174 1 is_stmt 1 view -0 + 2222 .cfi_startproc + 2223 @ args = 0, pretend = 0, frame = 0 + 2224 @ frame_needed = 0, uses_anonymous_args = 0 + 2225 @ link register save eliminated. +1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Set all possible values for the Clock type parameter --------------------*/ +1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | + 2226 .loc 1 1176 3 view .LVU688 + 2227 .loc 1 1176 32 is_stmt 0 view .LVU689 + 2228 0000 0F23 movs r3, #15 + 2229 0002 0360 str r3, [r0] +1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the SYSCLK configuration --------------------------------------------*/ +1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + 2230 .loc 1 1179 3 is_stmt 1 view .LVU690 + 2231 .loc 1 1179 51 is_stmt 0 view .LVU691 + 2232 0004 0B4B ldr r3, .L206 + 2233 0006 9A68 ldr r2, [r3, #8] + 2234 .loc 1 1179 37 view .LVU692 + 2235 0008 02F00302 and r2, r2, #3 + 2236 .loc 1 1179 35 view .LVU693 + 2237 000c 4260 str r2, [r0, #4] +1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the HCLK configuration ----------------------------------------------*/ +1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + 2238 .loc 1 1182 3 is_stmt 1 view .LVU694 + 2239 .loc 1 1182 52 is_stmt 0 view .LVU695 + 2240 000e 9A68 ldr r2, [r3, #8] + 2241 .loc 1 1182 38 view .LVU696 + 2242 0010 02F0F002 and r2, r2, #240 + 2243 .loc 1 1182 36 view .LVU697 + 2244 0014 8260 str r2, [r0, #8] +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the APB1 configuration ----------------------------------------------*/ +1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + 2245 .loc 1 1185 3 is_stmt 1 view .LVU698 + 2246 .loc 1 1185 53 is_stmt 0 view .LVU699 + 2247 0016 9A68 ldr r2, [r3, #8] + 2248 .loc 1 1185 39 view .LVU700 + 2249 0018 02F4E052 and r2, r2, #7168 + 2250 .loc 1 1185 37 view .LVU701 + 2251 001c C260 str r2, [r0, #12] +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the APB2 configuration ----------------------------------------------*/ +1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); + ARM GAS /tmp/ccemvyj9.s page 85 + + + 2252 .loc 1 1188 3 is_stmt 1 view .LVU702 + 2253 .loc 1 1188 54 is_stmt 0 view .LVU703 + 2254 001e 9B68 ldr r3, [r3, #8] + 2255 .loc 1 1188 39 view .LVU704 + 2256 0020 DB08 lsrs r3, r3, #3 + 2257 0022 03F4E053 and r3, r3, #7168 + 2258 .loc 1 1188 37 view .LVU705 + 2259 0026 0361 str r3, [r0, #16] +1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Get the Flash Wait State (Latency) configuration ------------------------*/ +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); + 2260 .loc 1 1191 3 is_stmt 1 view .LVU706 + 2261 .loc 1 1191 32 is_stmt 0 view .LVU707 + 2262 0028 034B ldr r3, .L206+4 + 2263 002a 1B68 ldr r3, [r3] + 2264 .loc 1 1191 16 view .LVU708 + 2265 002c 03F00F03 and r3, r3, #15 + 2266 .loc 1 1191 14 view .LVU709 + 2267 0030 0B60 str r3, [r1] +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 2268 .loc 1 1192 1 view .LVU710 + 2269 0032 7047 bx lr + 2270 .L207: + 2271 .align 2 + 2272 .L206: + 2273 0034 00380240 .word 1073887232 + 2274 0038 003C0240 .word 1073888256 + 2275 .cfi_endproc + 2276 .LFE152: + 2278 .section .text.HAL_RCC_CSSCallback,"ax",%progbits + 2279 .align 1 + 2280 .weak HAL_RCC_CSSCallback + 2281 .syntax unified + 2282 .thumb + 2283 .thumb_func + 2285 HAL_RCC_CSSCallback: + 2286 .LFB154: +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** +1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief This function handles the RCC CSS interrupt request. +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @note This API should be called under the NMI_Handler(). +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval None +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** void HAL_RCC_NMI_IRQHandler(void) +1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check RCC CSSF flag */ +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** if (__HAL_RCC_GET_IT(RCC_IT_CSS)) +1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { +1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* RCC Clock Security System interrupt user callback */ +1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** HAL_RCC_CSSCallback(); +1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Clear RCC CSS pending bit */ +1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __HAL_RCC_CLEAR_IT(RCC_IT_CSS); +1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } +1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** +1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /** + ARM GAS /tmp/ccemvyj9.s page 86 + + +1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @brief RCC Clock Security System interrupt callback +1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** * @retval None +1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ +1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** __weak void HAL_RCC_CSSCallback(void) +1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 2287 .loc 1 1217 1 is_stmt 1 view -0 + 2288 .cfi_startproc + 2289 @ args = 0, pretend = 0, frame = 0 + 2290 @ frame_needed = 0, uses_anonymous_args = 0 + 2291 @ link register save eliminated. +1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** the HAL_RCC_CSSCallback could be implemented in the user file +1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** */ +1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 2292 .loc 1 1221 1 view .LVU712 + 2293 0000 7047 bx lr + 2294 .cfi_endproc + 2295 .LFE154: + 2297 .section .text.HAL_RCC_NMI_IRQHandler,"ax",%progbits + 2298 .align 1 + 2299 .global HAL_RCC_NMI_IRQHandler + 2300 .syntax unified + 2301 .thumb + 2302 .thumb_func + 2304 HAL_RCC_NMI_IRQHandler: + 2305 .LFB153: +1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** /* Check RCC CSSF flag */ + 2306 .loc 1 1200 1 view -0 + 2307 .cfi_startproc + 2308 @ args = 0, pretend = 0, frame = 0 + 2309 @ frame_needed = 0, uses_anonymous_args = 0 + 2310 0000 08B5 push {r3, lr} + 2311 .LCFI17: + 2312 .cfi_def_cfa_offset 8 + 2313 .cfi_offset 3, -8 + 2314 .cfi_offset 14, -4 +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 2315 .loc 1 1202 3 view .LVU714 +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 2316 .loc 1 1202 7 is_stmt 0 view .LVU715 + 2317 0002 064B ldr r3, .L213 + 2318 0004 DB68 ldr r3, [r3, #12] +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** { + 2319 .loc 1 1202 6 view .LVU716 + 2320 0006 13F0800F tst r3, #128 + 2321 000a 00D1 bne .L212 + 2322 .L209: +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 2323 .loc 1 1210 1 view .LVU717 + 2324 000c 08BD pop {r3, pc} + 2325 .L212: +1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 2326 .loc 1 1205 5 is_stmt 1 view .LVU718 + 2327 000e FFF7FEFF bl HAL_RCC_CSSCallback + 2328 .LVL135: +1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** } + 2329 .loc 1 1208 5 view .LVU719 + ARM GAS /tmp/ccemvyj9.s page 87 + + + 2330 0012 024B ldr r3, .L213 + 2331 0014 8022 movs r2, #128 + 2332 0016 9A73 strb r2, [r3, #14] +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c **** + 2333 .loc 1 1210 1 is_stmt 0 view .LVU720 + 2334 0018 F8E7 b .L209 + 2335 .L214: + 2336 001a 00BF .align 2 + 2337 .L213: + 2338 001c 00380240 .word 1073887232 + 2339 .cfi_endproc + 2340 .LFE153: + 2342 .text + 2343 .Letext0: + 2344 .file 3 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 2345 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h" + 2346 .file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 2347 .file 6 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + 2348 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 2349 .file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h" + 2350 .file 9 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h" + 2351 .file 10 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h" + 2352 .file 11 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h" + ARM GAS /tmp/ccemvyj9.s page 88 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_rcc.c + /tmp/ccemvyj9.s:20 .text.HAL_RCC_DeInit:00000000 $t + /tmp/ccemvyj9.s:26 .text.HAL_RCC_DeInit:00000000 HAL_RCC_DeInit + /tmp/ccemvyj9.s:299 .text.HAL_RCC_DeInit:00000144 $d + /tmp/ccemvyj9.s:308 .text.HAL_RCC_OscConfig:00000000 $t + /tmp/ccemvyj9.s:314 .text.HAL_RCC_OscConfig:00000000 HAL_RCC_OscConfig + /tmp/ccemvyj9.s:819 .text.HAL_RCC_OscConfig:0000026c $d + /tmp/ccemvyj9.s:824 .text.HAL_RCC_OscConfig:00000274 $t + /tmp/ccemvyj9.s:1214 .text.HAL_RCC_OscConfig:00000440 $d + /tmp/ccemvyj9.s:1219 .text.HAL_RCC_MCOConfig:00000000 $t + /tmp/ccemvyj9.s:1225 .text.HAL_RCC_MCOConfig:00000000 HAL_RCC_MCOConfig + /tmp/ccemvyj9.s:1375 .text.HAL_RCC_MCOConfig:0000008c $d + /tmp/ccemvyj9.s:1382 .text.HAL_RCC_EnableCSS:00000000 $t + /tmp/ccemvyj9.s:1388 .text.HAL_RCC_EnableCSS:00000000 HAL_RCC_EnableCSS + /tmp/ccemvyj9.s:1405 .text.HAL_RCC_EnableCSS:0000000c $d + /tmp/ccemvyj9.s:1410 .text.HAL_RCC_DisableCSS:00000000 $t + /tmp/ccemvyj9.s:1416 .text.HAL_RCC_DisableCSS:00000000 HAL_RCC_DisableCSS + /tmp/ccemvyj9.s:1433 .text.HAL_RCC_DisableCSS:0000000c $d + /tmp/ccemvyj9.s:1439 .text.HAL_RCC_GetSysClockFreq:00000000 $t + /tmp/ccemvyj9.s:1445 .text.HAL_RCC_GetSysClockFreq:00000000 HAL_RCC_GetSysClockFreq + /tmp/ccemvyj9.s:1562 .text.HAL_RCC_GetSysClockFreq:0000009c $d + /tmp/ccemvyj9.s:1569 .text.HAL_RCC_ClockConfig:00000000 $t + /tmp/ccemvyj9.s:1575 .text.HAL_RCC_ClockConfig:00000000 HAL_RCC_ClockConfig + /tmp/ccemvyj9.s:1874 .text.HAL_RCC_ClockConfig:00000158 $d + /tmp/ccemvyj9.s:1883 .text.HAL_RCC_GetHCLKFreq:00000000 $t + /tmp/ccemvyj9.s:1889 .text.HAL_RCC_GetHCLKFreq:00000000 HAL_RCC_GetHCLKFreq + /tmp/ccemvyj9.s:1904 .text.HAL_RCC_GetHCLKFreq:00000008 $d + /tmp/ccemvyj9.s:1909 .text.HAL_RCC_GetPCLK1Freq:00000000 $t + /tmp/ccemvyj9.s:1915 .text.HAL_RCC_GetPCLK1Freq:00000000 HAL_RCC_GetPCLK1Freq + /tmp/ccemvyj9.s:1944 .text.HAL_RCC_GetPCLK1Freq:00000018 $d + /tmp/ccemvyj9.s:1950 .text.HAL_RCC_GetPCLK2Freq:00000000 $t + /tmp/ccemvyj9.s:1956 .text.HAL_RCC_GetPCLK2Freq:00000000 HAL_RCC_GetPCLK2Freq + /tmp/ccemvyj9.s:1985 .text.HAL_RCC_GetPCLK2Freq:00000018 $d + /tmp/ccemvyj9.s:1991 .text.HAL_RCC_GetOscConfig:00000000 $t + /tmp/ccemvyj9.s:1997 .text.HAL_RCC_GetOscConfig:00000000 HAL_RCC_GetOscConfig + /tmp/ccemvyj9.s:2207 .text.HAL_RCC_GetOscConfig:000000dc $d + /tmp/ccemvyj9.s:2212 .text.HAL_RCC_GetClockConfig:00000000 $t + /tmp/ccemvyj9.s:2218 .text.HAL_RCC_GetClockConfig:00000000 HAL_RCC_GetClockConfig + /tmp/ccemvyj9.s:2273 .text.HAL_RCC_GetClockConfig:00000034 $d + /tmp/ccemvyj9.s:2279 .text.HAL_RCC_CSSCallback:00000000 $t + /tmp/ccemvyj9.s:2285 .text.HAL_RCC_CSSCallback:00000000 HAL_RCC_CSSCallback + /tmp/ccemvyj9.s:2298 .text.HAL_RCC_NMI_IRQHandler:00000000 $t + /tmp/ccemvyj9.s:2304 .text.HAL_RCC_NMI_IRQHandler:00000000 HAL_RCC_NMI_IRQHandler + /tmp/ccemvyj9.s:2338 .text.HAL_RCC_NMI_IRQHandler:0000001c $d + +UNDEFINED SYMBOLS +HAL_GetTick +HAL_InitTick +SystemCoreClock +uwTickPrio +HAL_GPIO_Init +__aeabi_uldivmod +AHBPrescTable +APBPrescTable diff --git a/build/stm32f7xx_hal_rcc.o b/build/stm32f7xx_hal_rcc.o new file mode 100644 index 0000000000000000000000000000000000000000..b0227be143df2ed3be6f9506267f0b3545eb07e9 GIT binary patch literal 24432 zcmc(nd3;sXx%b!J`|OjG-|!9dash_y(H z6Ao=vs?|!>YTIk|)>^4{c%{{9)qAhCLA}yyhoH8+g0@kxT5aq5`>p-#lXDK(tMB{A zyFcuF*Ym7rJ?mM+UVAuuvu9;Zg<%-V-3&ELjY>)tuh%*De2rNutmdi34}bLDKR@zR ztgQ-ml#Lixu(_ssQb%yaO!XdSj+$i7diOV0Xz`(nHMy`Dv~ruB5-R)t=922$Ve3!z z4LPyBx=^HQ1cx*mb*hj=%fFF4M7V2sTe}?3!ZjZaEgH4pePyPFwoK`&WdXcz<8$ z<&LaV|15pE`Q?t%Q+v#pn>Ti6jTq*}tsA>bM+SR0ZuM3Bsxq5>)e|~&TW75}HSj$n z)O$?*Of5Ex)ACi0?$(@BPWR7JBi_9|5AS`@Q(>WxjMUjfH>0<#5x?ch%^bQ((!Si( zq1KLr?+&gg9#XlDhp(^BL>z;Kna!G6naxXvudd#No*PU(K6It@p@lLkSB)I`Lbe{O z{-MicBrY8Ke8h9Z&}-W2n!$_F8_wu5cDtfa_lcR>tH-!l#`p(Ex6|&_U{SESwIlbS zW7{Eh{)gB){d~vKgYVvzmpIgXTD(V(ZGx`!)F5KlL|cyNQL!u5iLZO~94MaT_}X=} zR$BP&!|v>}5WA6EJks%nNfzx5o;#hV$Ji8I~UTl|<&uy4<6)P(yZ94LMSSGn?F=8-J8hc~W-| zO|G8Q6&x9CntC|1I*Y_CvE5+v~LE+{OrT2)tP#( zWo{)sX6DwZ!)nGG$C8}Uz%juXy%k<5dsMe>PJrM-}&01$A!(x8BoHq({$N zvAued?vXqxGkSy`8n$y2huTl8d-xc}6my<&kOugY9zSozM)Bqx?}L*@z1=eWk00OD z$vJuBU|rQs9p;GN^v&5YWadsBs?mMTW1H>pR8;D|R(mRCC2;zBV7Rm@*o8HqA=vht zV=H3H*cE3>nb>~cH2hj;*0x~T=51xi_Xh9YR_`;GmK`_CUWIJ7W?h88ee!0QN(tYBta0`Z2s0e$(aHy&tW0N;zo*J}{c3xLH_pmv#!kWJAy3*N)TehwG>tlVv z;)5r?FfHe>d8)YJo^6|a#@XLLVbxBBT~F)LZ3j;n-I+)amu6q|&2db>^WqFK0IcG{)YWM?C)YfiT!Qte>ui6?Rj|LgZ_$f74QEzw6^FX&hw(y zqKhn$bE)>!V4t<$%=YZJvc3CNw!J@LzxADrO7`(Vtfg5?Ht22~Oh?L(|R(|{!p2=lDX#Sn7aY~uR%4ZgvdS0sRU~|tZ#z{H*)Tr!x_^ilE zS2E0F<_fPnZ))Oh#E2`}Hxqbhk z#=@rTZDrkNs%+$kN{$~mm!1zFvnr2Z|8HqW@vhy5;yR5r`mVvAhsRWSD(W#OtdUgf zy3*w5YxUeqwUWz%m^qHNc;t(N&RRQuh)23-XjRpItd+wJ`(;J)43%n4bJ_mpVx+Q1 zMyzjiBtv33Beei)wvijc5iw(EaaEurfOV>EXu;}hJF-SBGgx+=9OVVlcbhv7p4gk3 zp^p*wNE^YKb>;9Zmd2TM_^=ULK0HJFQhR;_Y0+><+Hrqr(r>0nJ8~oKxW9DXVP~cC z4vlAwi2rCLMqg^e&{(Z)E^}7f{W>N;B6{Ma6-=&r;euZmCs$8s#_pU2L!8B&*B@Zk zzK{K{?BivaCtQ=FHUlLvTYg5B&$;H%UiW5O+Nr4 zQ0=L^vdfwa^f7IuRt*{1Pc-vt;)#<_T2@OCtDh&ebjZ%Wym^*hyA7N>jO?^@*_To8N$^rX4{2-B#Myw?V|VW8R|(AiF?L@*{unB;9xgpg#!_t<2~EHeH#b#z zo<=(HA-M9KJ)U|oVbIz^g7O@vNeBLTmW`+0Fp?(Q1!m$^2s62)tX|ng=GbeIVP-4; zJy6>7UD@N`OnHGT`;r@AzR(r@$t=Cd71R8K@M14^<#hk+EWN~)C#W$~s90)RW55K~ z$@-+F_I{+3X4ySvVi_9bznRW@-NMRWMY+$FJ^owhtKXG<{)d=9;L85w)#V6orz@u= z*HXUNmDBxRmfz*d6Z}(H{t{Q7oLo`?`_GwU8KRjTQe!3{D*IB?;@~Hx*~4by?a-hP z3Y7h-TTc1^idkj9=E@%A7b^R8SN8coWd0vr*{{arGLS!+Rvo-0eZ_vuOne&CMfdGr zTr=grnpPvO?D1buH*dSLFS%?r!hOe;{r*Fko%TsrPV+wnpY|zNPWN}QHSfCe1pntS z&+NaNdZL-xll`kHzvt$M{Hs|1`>vehzk>OHGsk`h-DYOb^6z9kAGrDX{!G^Yp)1e# z=d%94yYgcHmstKEZhg!A0owo5%`f(6)BYn@F83EvR+iLP>3@O4WmqzE>-?GYXS#Bu z-=@9g%Ip2#VZO(b_FdpVpY6BZ{AT~Xl)bLp=08aL1h>8p|0%}jbMt$W%Xlaxx^ln& z5bcv(`(6H*X`k%mTiJt#zl9a}UBwlKe=|#raTWUve=@r`#Z_Ey_|vIKbrm-lYRn8e z8EaXLHYLGmLnn9-7=J-qQ=f)AmDaGb5vzuk#f&?x7m;E5Ja3I!C(JZvBeK+Upi-$7 z$Tw1N$IzLn1<+W^x&=s>Ynd<_JJ~lc@m?eX=fc>R=hsVDwhBx{F<+sGp1@A#E)dZd zxRl~z5&eOyD4s21THrd0%SB8N+(5BJ#0knW5Q}f6xq#KrPb^HF2{|x;m=foUkqSJA zZb@7uq9^bpxJX7^%P=h%u>1L{H!{m?SL}(HA&|`jVE2=nwo3^(8G65f$8u z3X+yvUt!E&Mdis)%ef=n@H6WV35GEREf}Z&WFw_AJX~-yJd9<$u^m>)hk|;V7^Sr2 zu&W8iD=N+G~d6dD-iL=~JOB#$?W*JXmb{W&6EK#%Wfa%5q?3XvJ(dzC+ z))(ny9{M}`Zf2jb^k_c}?RT+f|C^)CV4s}CeuB!C_yfx^UE@%+*#6m3KpNEA|;DsJzBX=gc&3yx=Uj zR8z6Pj?S2|h?)B>n*(d!*r?8`LgGRSFmrOh<>szeGdZ>vX3;d{&NAw3wA3t~Wtg9IfX~=YW8j>O#H85uI@eo^tejecoKg`MMMxk%c{nW+=0sjX46v zudrvQve_@1dho^}os50bS75<|Y|?#hViw$gn=_^qiP^|P3|F$~dB$iA) zCh8G|_OsbdT;(QsveH>Ex{24_1g{5l)*Lsn)=gaKCcfq-?vn%#lV7n{pB(M!^$6oi zbcn$Qs#eK)AVv|@wlD$h@;BmtP68=%_GjSuJR1yn;2>C${1_RNC_reDU(vx zdB+;{MjEtcj!I5m4keC}3}vM(O+Gt$N%HC-?i$WgguOt+D|VP@IFGCj8p!fZM^+xD zN#gvdk}Len5K~gnNKS?`dr2})lgB8_=ZLF=i*fk)plM@oQymt zAo@t1g(8ztT^bTTCdNu7h?oWe@u?fYN`g{rM3EjgR`}gU&P1RrHqO>9%t%E~u*KtJ zjaCO8vk74pU6yLBm=Pu7p6MTJ1dQUOua+VwGvZ}5$BP`+IO&?bh8k-WAUXLAW^_Qa zDY)#7^byy#sZ&s<-uO|e&5G71Z?MltFHEylLD2O6uoS}?nm?MJ9_xB_P)Fy+kQE!b zBdsn%yu(yZi+;R z5t`|bi!e8OR!J0d!-m@>v=8ZVpBEh(j)3T>l*(g6m-(+QPT?fi8n2XaPwE=9JElgdAO(CwrDAD|C@MmgcFS>W?YTbp;lsVnsTI8(28LKA7q%S%hYE zOh(nmiv+4k7WXPYpH4R*7^zStWYX@wq!6$s>Ybz5Msoos@Sv*#x~rXG1*WHXm9;ol7|FY9u1gjZx?QjwNx0PBs#edc+c{Gi*zs z!>AJMbVIEpBDI*KwOry@5_Anq{Ecirq}Z2ag&xh_X=Ig?*5qXk`#4hQUnKS;5B*8} zNGBVKCmk*El%pk{ceDhnG*lx|sgrdCgNW{O$~8_lu~sJ=3EsS+T7uES6`Y>7wLycS zA)E@=5ssU438!qNgE(KImF*UgQajBoRb-3q>?CN}sbs*T z(-X)HC#{(!dNRjJr;)tIL)i%t$Dbh40UJb2Jff40#M6$Jc-7GoLBtMQVlu9O(3`}3 z?9rn^`GAv6JQ|lxnGHf|B3&oz2sSa=5#?m!E< zqlJXi8|(fPN$$`RPH(KsfOGE95@DTOw-ewFEpeBleGuRdE%A(_{WZWHT4Kb}HezaV zhnDEq$@BIB+@U4D>1ba9xI;^vahfHj)=VM?9*v zF$c?IPLshb)ej})#bgS=Yqry*Nb`!#c^0< zJ}BYl)TdNPOQV1Of7Cm63?CbQ4J|N@4^zhAAk~X0WTU*db7y;RUtUAwnxevrMZ0!2 zRhHB=IoiC2-d5!rl&xu4-H^9>M{CzWTf52|=fD^SwY4>`rFZ+h9o;+H=e4(N z?#wGF3Kxb8@;b#bwtRW}&d%0$)HYgS#HVX{#!yhPQhoi~iwd_e$c~n-rry@pa4Uvc zwQle0>}x_K;SP3tUw<2Zr9m2pPv0ed{q5VEA_bwvc#F6Yo?;ZIiMpP)_ARi&oq5EI zTYXbI%bzLdOzN#Yo!w{9J1RUU$D?sh6YELCu&wFi>{Ku4U9ri|HS8p$bHldnU9OW8 zl<6_TwvPzeDfxKFeo}>CZQZmdw8<@5V9#|*&i&YuH7HZ$+JB;&{-5l_PCVg{jVC`g zo=<3>=Jb>ujA6kVY!O`o^1SS?D%-!@0mH8&i2B}us*kpUFlyo&dy}1 z5c+*Zy6$*im7S7jCsx@BUMmUbAk$-3;g2WGKkM!DS%KHux!$g2Dh#vbHh#sjlfsT> znZ1-5dZ^|si*k>;ImW)QopO%&9~-u(uxQ9mO1X%4_{-55r1YKhB=)`pKr7F#KeHQa|{;rH^iW%lKzK{v_`cLIf_l}h+ zUBS*-apulR^p@jiq43_Q{uyUaLK}P`6w2PD2bHA@4Lb$uLbhnRPEJOEXrP}6*@1jy zSm%dt{&d~vwWfzZRV9{pepIX(s8kOnLNtu^RiU6BJR6-Z8R*o&GCh0PtM2Sc@mfE; zY(1yePtXKThcu^?IIlUAQZNHHp1GMe8|>}E-=y{FQGNBvyQ;>f4@B0lhg<)N9_|Dy zxc*alL!bB%xaFN0w5KBB97j$U@Bqr!O~m+|gUYGsJB$_Qh#9iete@--g{%c3WZhswJKav39lpc# z#H>|UCm6a@tJ8z&dbzT_S>yC98)r{Mj_o~1Pet3Cr>6nQRg9dbIo%ryc?-N%s5YGo zvDFj)zjCnNHu6nhOmK%1xRBb0cY|rgWIXk88E-ISI#xd($K%4brTaOp${q{ZPazNM zoVyCz6-X`$bMYI*;ho@Z(!*F3X4m_v$g z$YbJ2x1PNWKGJQ^cue#$RbImb$LKTDx(k;+)0kRj<2@^%*DA%pz;*Iyt8MRE-3}}c zNy~H!W=Nf8Rvc&M6hPDPZbI}G*3CE+5ljfxu#=0x8DTry={(&7A*Tnj?FGo28Dcg& zcA-c-(z11VoD);HIL6iRSfY_(8ZniAkCkTOAi&t5L^+P6Nd;IJmg^<8qNb(4eMjph ziZ?v2U0s`7S}#&HW!3enqN`QS|g8|qfpE4-&b>vq+1ac^taMXenzJGQpBu|!>OdtYl~%jT|j8m-}< zwW_wR5wB(;S;s%;@=v{5Q(F#CUEMpjhV-9-9etf!ceJ;K_}*FFx;nfcRnxH2sfIDv z_O-6w(b?b7-#gHX;3`WCYU)<5tyd*o{q4Ow7)+E^<0U=qF?~`ab8Q;fbJ01t(uzZOIJ6l+J?H7E78g|-MGutrAIr1)$P=U z^l)`u6xH-fw^w3%O!sktT2;5YwkgV(#n+V8Vi28n#FWv-Zp&%ura4a)Iyzd#)HA4)ph8V!U}dnWL)%2$D!KP>O|}e zo1VQG7^idl(OG@{ExkC*5O()KZ)>}r+xlpN73oG&q^ERIA*VDNwz9sy76;M)@FXSg zw8sZ{dg1ma=7sd;z{TvNy57!iE-u^oXJ>17#1IWcH|ze@ZRA+#&UZbPx3iyh=uy*y zeS;B`cDc52raeUsq%^mXT(x#xsH|X7$a$g@D$Fk|D#*`Y5}LQYwP)a*R!sf&UGugt zg52LRuzfSQ1^O*LI~UArD_BUetGlIt9v%vvgQcboik9Bij&tz1Xy>B#dE0Zh^n}}b zLi4ubU)#kky<6rLhUV2m+S1n2-!iYSy_Ks(ALK0qJ9Ijt(<@y}v(c1Fv{&~D)^RK- zZX=^xSXz!HmuvZA3?2J~$0(0g39aY-rkuIW1>L!4PJ>XQ20}*a84TN>Q@aL8jvXyL#-++TN;{Guwbbk^WOHZf_a6r z<0k+fQt>J1N7!%=`}q{SAQ1fn2%m74q@-Q$xx%{A{F0&O!`9vSw6#1X?F!G8)>X(W zNts}I%oO$HFP?g?G-ZOTu1HErD@hKyg+M-?g-_R@Bqe{dwsD`v(v(kZ3G&HqR7~cbZak6dV*Rp?Xul!IuHTQ-N5?e``)HX@jH6{f1^hTaB?ZXT zb3z$2k+c`BoVP}K$0V#tG?RP*Pr5PA7;jC$dtjNyWMit4g|@|S(JGI6`=jW5+_goE zc!cUc$9B|s`7|!yqsGN(JbEsaN8Dh*qc#gaBgfi%wLRZ-b~Y!UKf|~(=T>pVjn~c4 zwD5CjtUsUjcYVal7fCT;;YX}k`y_2Y+W$#$_Q`Sf$#M30t0QW&Fp{zU{o0=IVmaGr zO_VK_5@(;H?cHAq@OF)qb6{bX$NEpx_M@$If46Y$19A2NZ9jUv^2eFc&BDx!^`9PR zA3ZY}e@2{rhPMB0#AQY##e}8C$Jvk9_VXiF<0C1@enOo6Xyi`*#JK#4+TY}emx+;- zV?QZQ<|hTCo26e}jFv;A0#cTK7j;x+$>+7M#!_dwNlgnMb472K;!!)gS!#}AL_AzL z<^lXXF=sSeuW1Y8`az;<5a?!*yCeD`n zB9-aL6>I#JZPZ1YdzL-@bUb>6to^$8Ad&NO>_tDXMxw6B|J9j4<^s^IKl(BU7a38v zoUTRmB~p}b^x7cyPBqTNxulL#p59f$a{^jRk9Z2XRnF(bJikd?xX z!hRv=F!K)x?-M>Ld|vpba6aZl5+)4il6ek(@h9;MG>-}TxmW0xe^KN#mP39>*drVi z-Y5Kt@Oj~@!nK%`EPtVJuka?}kZ@R-fzvDP&k|M%HwteNep|@3A*sZ9JBlo%T&~ph z!W*O=-xl&U-=vlJ4W2}QG=t_UrP@gJO9zR5;rWCz!cs{X1da=S={im3*(qr)Uk*ba zu1$E1n+R&GkmnN0T!l>x>I`xLUSSq}k&y2N(5^(tai?4>Y!q%4b_qWx+#|e6_*Efa z5ul&n2^HH1d6saoaEp*HkuaZMa*+pxPY7QSz9tN!gJ_p6)bCe7zDVTjga?E_7d|h1 zM~KJe+D|~pH`M93P*^JDmxk1D7WNAF3U3nLEqqA$bK&#CSB38g@kGq2U&!~Ibp66o z;bvj4@N(f-gx?ZAB78>pns7w;PvKbnc+Psp3-KPUma~O(ge!z=g`W|22`?31E4)qk z9pO)fzZCvfctZGrFcA}(@yrsQBdif_5^fV-BD_ZUUE!m`{}R3|JTBx1h^z-c)oSJn z%Y_ZX3&>m?r^0Qb?<40ab+PbL5(od4BHuv5|83+frM@n_PxL<)z9jquIYX(}gd?K2 zun$fqBvIc~;Y?w!a0!X}E66OoKPX%)`Rhe)C1KY?PQ&Y0!d)c%?-lurB<#LM zVllcyc(3RmCNuC=uJ90v@=r_t3nCv8{#Nw=TjV!|Z;SpPBJ&F>`tg#eKOl03a1x1n zbA)*$>=u(jyt5^&5PdC)i<}1GXGFh+#9KPsggZ#oyG!z~5P6^Qi=w|xgi}O6TjY7dLK5{Z6s{mqzE0!~!p*{qg#E(Z!mET|7TzlShVVY&LE)pqUkINQ z9uW=;-w?hd{7~q@37T<_5oQRd3FnY#$3hZo;!@#q68%&u`3)kUFT8++eYn4^Yy{?@l z)Yl(a=Wywx^=n8N@uOODgYYxL?IhN#&k8RQ?iPNL%uwn^;cddN3wcka*DK-U!e0oV z6%Gmc{|3@aBFqqG3iE}$E~Y(RM$s%5@=J2+tA+d$k@8ky zx3Ew6IpJl(tAy7I?;ywEcoy=yneqd|M})kNrvB%`r-aW5d40|Ng?9>h|HAtCQ6Kqz;lo0{4Nd)HLVlo0`4yqQeuexe zk>3)&Eqq`2cOk#!WO;rSPfi!k5Y83m3l|B`7M2ND3He=o`5?iPMQxKDV!@PP0xAwP~~Jbx6vDI5{L zC;U)|w@9?TS2#vERyaX8S(q*42j#3MEG!f*5$gK^Ayb;S0he!ru#D73z<>QU6;a zE8ZVK_6U=OsX~6D%=~=eV&O8OzRy8^rO35HecuE9CXt(jTZH=l2l<~Bc|fS|docFb zPzG-l-Yn#Yz|=o3cjG(=_Bz+Ur&LkQrDj@)Nw(npBI54>Tw^G zBSaNCuDQZ|67k{Dkfx3sg_ltVi%G;=F03RGca5-)MEv^s5UAUQN-m%tY$nm3Hem;e zc6ABA!|MgKZxYWFKHM*I9MPX`NV7lreJA6;g+zbO<$V$2{W|X-5Z@yt;yXqnE`8sC zICi6hSpOeL)UU5oQLpZ&MKXS*9%08kT|eC-`U&^xxzW$q&zL*fUDZDmlYu`MuwW)K*mTrudPPc5{+}pm>87@bIw|k<+mR`Q;CIjkN zoUZBW+|llO#Eekk*6!`w+wn$MRIOWjTeicfq<&4frN6(obMrty+m9(y*xhL%_E7qAeIkREOHJKyO756px0O0 zvA)&Vqy6#sEcYulWNBM+CH8242a0jM3?2RPeBt_QM>^Wy5Z0Yrp>sDkz7{B={asMv ztnc*4xLkj{$Bp*afy%HnMK;&p&2e_SKF02$IJ+c<;quYA`ox%Ft&Gq+ZD5CxS0RGr-^vC{j z{qZ-YXn%Z$8A86hx&HhxiuU(t$>?|lVC?$KgB|`w=KV7td*kdpJXc29x#_#&?0m2bMcKLj4!|zD9ltFZ?Pr|w zBK`8X_;X#%f53+~NwK9SW<@W;*LGm&V2hmVsLBg}-rU=;u_}MaOrb(YfBF zznmz4)5IUwRc>EJA|1!DyRk0rbK>mo$92g}*GOz=wY7h$(6Dq!{tx1zZC{Od;B zI}7=4|M53IoI84SA^fRX;{5LF%C2h?rjczBcKleB=K(%%q(80;>=XA~grpk8L&$qv VCy?DFe^ZUNdlT_BMpfY2{T~kO(1ZX0 literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_hal_rcc_ex.d b/build/stm32f7xx_hal_rcc_ex.d new file mode 100644 index 0000000..09ed78a --- /dev/null +++ b/build/stm32f7xx_hal_rcc_ex.d @@ -0,0 +1,68 @@ +build/stm32f7xx_hal_rcc_ex.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/build/stm32f7xx_hal_rcc_ex.lst b/build/stm32f7xx_hal_rcc_ex.lst new file mode 100644 index 0000000..8afc25b --- /dev/null +++ b/build/stm32f7xx_hal_rcc_ex.lst @@ -0,0 +1,4544 @@ +ARM GAS /tmp/ccgN7hfx.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_hal_rcc_ex.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c" + 19 .section .text.HAL_RCCEx_PeriphCLKConfig,"ax",%progbits + 20 .align 1 + 21 .global HAL_RCCEx_PeriphCLKConfig + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 HAL_RCCEx_PeriphCLKConfig: + 27 .LVL0: + 28 .LFB141: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @file stm32f7xx_hal_rcc_ex.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @brief Extension RCC HAL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * functionalities RCC extension peripheral: + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * + Extended Peripheral Control functions + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** ****************************************************************************** + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @attention + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * Copyright (c) 2017 STMicroelectronics. + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * All rights reserved. + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * This software is licensed under terms that can be found in the LICENSE file in + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * the root directory of this software component. + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** ****************************************************************************** + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Includes ------------------------------------------------------------------*/ + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #include "stm32f7xx_hal.h" + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** @addtogroup STM32F7xx_HAL_Driver + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @{ + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** @defgroup RCCEx RCCEx + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @brief RCCEx HAL module driver + ARM GAS /tmp/ccgN7hfx.s page 2 + + + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @{ + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #ifdef HAL_RCC_MODULE_ENABLED + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Private define ------------------------------------------------------------*/ + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_Defines RCCEx Private Defines + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @{ + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @} + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Private macro -------------------------------------------------------------*/ + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_Macros RCCEx Private Macros + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @{ + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @} + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_Macros RCCEx Private Macros + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @{ + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @} + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Private variables ---------------------------------------------------------*/ + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Private functions ---------------------------------------------------------*/ + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @{ + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @brief Extended Peripheral Control functions + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** @verbatim + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** =============================================================================== + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** ##### Extended Peripheral Control functions ##### + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** =============================================================================== + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** [..] + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** This subsection provides a set of functions allowing to control the RCC Clocks + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequencies. + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** [..] + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** select the RTC clock source; in this case the Backup domain will be reset in + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** order to modify the RTC Clock source, as consequence RTC registers (including + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** the backup registers) and RCC_BDCR register will be set to their reset values. + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** @endverbatim + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @{ + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ + ARM GAS /tmp/ccgN7hfx.s page 3 + + + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** defined (STM32F750xx) + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @brief Initializes the RCC extended peripherals clocks according to the specified + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * parameters in the RCC_PeriphCLKInitTypeDef. + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * contains the configuration information for the Extended Peripherals + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * the RTC clock source; in this case the Backup domain will be reset in + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * order to modify the RTC Clock source, as consequence RTC registers (including + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * the backup registers) are set to their reset values. + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @retval HAL status + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 29 .loc 1 106 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 8 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 .loc 1 106 1 is_stmt 0 view .LVU1 + 34 0000 F0B5 push {r4, r5, r6, r7, lr} + 35 .LCFI0: + 36 .cfi_def_cfa_offset 20 + 37 .cfi_offset 4, -20 + 38 .cfi_offset 5, -16 + 39 .cfi_offset 6, -12 + 40 .cfi_offset 7, -8 + 41 .cfi_offset 14, -4 + 42 0002 83B0 sub sp, sp, #12 + 43 .LCFI1: + 44 .cfi_def_cfa_offset 32 + 45 0004 0446 mov r4, r0 + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t tickstart = 0; + 46 .loc 1 107 3 is_stmt 1 view .LVU2 + 47 .LVL1: + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t tmpreg0 = 0; + 48 .loc 1 108 3 view .LVU3 + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t tmpreg1 = 0; + 49 .loc 1 109 3 view .LVU4 + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t plli2sused = 0; + 50 .loc 1 110 3 view .LVU5 + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t pllsaiused = 0; + 51 .loc 1 111 3 view .LVU6 + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + 52 .loc 1 114 3 view .LVU7 + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*----------------------------------- I2S configuration ----------------------------------*/ + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + 53 .loc 1 117 3 view .LVU8 + 54 .loc 1 117 21 is_stmt 0 view .LVU9 + 55 0006 0668 ldr r6, [r0] + ARM GAS /tmp/ccgN7hfx.s page 4 + + + 56 .loc 1 117 5 view .LVU10 + 57 0008 16F00106 ands r6, r6, #1 + 58 000c 0DD0 beq .L2 + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + 59 .loc 1 120 5 is_stmt 1 view .LVU11 + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure I2S Clock source */ + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + 60 .loc 1 123 5 view .LVU12 + 61 .loc 1 123 5 view .LVU13 + 62 000e B54B ldr r3, .L87 + 63 0010 9A68 ldr r2, [r3, #8] + 64 0012 22F40002 bic r2, r2, #8388608 + 65 0016 9A60 str r2, [r3, #8] + 66 .loc 1 123 5 view .LVU14 + 67 0018 9A68 ldr r2, [r3, #8] + 68 001a 416B ldr r1, [r0, #52] + 69 001c 0A43 orrs r2, r2, r1 + 70 001e 9A60 str r2, [r3, #8] + 71 .loc 1 123 5 view .LVU15 + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable the PLLI2S when it's used as clock source for I2S */ + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) + 72 .loc 1 126 5 view .LVU16 + 73 .loc 1 126 21 is_stmt 0 view .LVU17 + 74 0020 436B ldr r3, [r0, #52] + 75 .loc 1 126 7 view .LVU18 + 76 0022 002B cmp r3, #0 + 77 0024 00F06781 beq .L59 + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t pllsaiused = 0; + 78 .loc 1 110 12 view .LVU19 + 79 0028 0026 movs r6, #0 + 80 .L2: + 81 .LVL2: + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** plli2sused = 1; + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*------------------------------------ SAI1 configuration --------------------------------------* + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) + 82 .loc 1 133 3 is_stmt 1 view .LVU20 + 83 .loc 1 133 21 is_stmt 0 view .LVU21 + 84 002a 2568 ldr r5, [r4] + 85 .loc 1 133 5 view .LVU22 + 86 002c 15F40025 ands r5, r5, #524288 + 87 0030 11D0 beq .L3 + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + 88 .loc 1 136 5 is_stmt 1 view .LVU23 + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure SAI1 Clock source */ + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + 89 .loc 1 139 5 view .LVU24 + ARM GAS /tmp/ccgN7hfx.s page 5 + + + 90 0032 AC4A ldr r2, .L87 + 91 0034 D2F88C30 ldr r3, [r2, #140] + 92 0038 23F44013 bic r3, r3, #3145728 + 93 003c E16B ldr r1, [r4, #60] + 94 003e 0B43 orrs r3, r3, r1 + 95 0040 C2F88C30 str r3, [r2, #140] + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable the PLLI2S when it's used as clock source for SAI */ + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) + 96 .loc 1 141 5 view .LVU25 + 97 .loc 1 141 21 is_stmt 0 view .LVU26 + 98 0044 E36B ldr r3, [r4, #60] + 99 .loc 1 141 7 view .LVU27 + 100 0046 B3F5801F cmp r3, #1048576 + 101 004a 00F05681 beq .L75 + 102 .LVL3: + 103 .L4: + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** plli2sused = 1; + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable the PLLSAI when it's used as clock source for SAI */ + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) + 104 .loc 1 146 5 is_stmt 1 view .LVU28 + 105 .loc 1 146 7 is_stmt 0 view .LVU29 + 106 004e 002B cmp r3, #0 + 107 0050 00F05581 beq .L61 + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 108 .loc 1 111 12 view .LVU30 + 109 0054 0025 movs r5, #0 + 110 .L3: + 111 .LVL4: + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** pllsaiused = 1; + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*------------------------------------ SAI2 configuration --------------------------------------* + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) + 112 .loc 1 153 3 is_stmt 1 view .LVU31 + 113 .loc 1 153 21 is_stmt 0 view .LVU32 + 114 0056 2368 ldr r3, [r4] + 115 .loc 1 153 5 view .LVU33 + 116 0058 13F4801F tst r3, #1048576 + 117 005c 0FD0 beq .L5 + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); + 118 .loc 1 156 5 is_stmt 1 view .LVU34 + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure SAI2 Clock source */ + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); + 119 .loc 1 159 5 view .LVU35 + 120 005e A14A ldr r2, .L87 + 121 0060 D2F88C30 ldr r3, [r2, #140] + 122 0064 23F44003 bic r3, r3, #12582912 + 123 0068 216C ldr r1, [r4, #64] + 124 006a 0B43 orrs r3, r3, r1 + 125 006c C2F88C30 str r3, [r2, #140] + ARM GAS /tmp/ccgN7hfx.s page 6 + + + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable the PLLI2S when it's used as clock source for SAI */ + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) + 126 .loc 1 162 5 view .LVU36 + 127 .loc 1 162 21 is_stmt 0 view .LVU37 + 128 0070 236C ldr r3, [r4, #64] + 129 .loc 1 162 7 view .LVU38 + 130 0072 B3F5800F cmp r3, #4194304 + 131 0076 00F04481 beq .L76 + 132 .LVL5: + 133 .L6: + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** plli2sused = 1; + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable the PLLSAI when it's used as clock source for SAI */ + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) + 134 .loc 1 167 5 is_stmt 1 view .LVU39 + 135 .loc 1 167 7 is_stmt 0 view .LVU40 + 136 007a 03B9 cbnz r3, .L5 + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** pllsaiused = 1; + 137 .loc 1 169 18 view .LVU41 + 138 007c 0125 movs r5, #1 + 139 .LVL6: + 140 .L5: + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- SPDIF-RX Configuration --------------------------------- + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + 141 .loc 1 174 3 is_stmt 1 view .LVU42 + 142 .loc 1 174 21 is_stmt 0 view .LVU43 + 143 007e 2368 ldr r3, [r4] + 144 .loc 1 174 5 view .LVU44 + 145 0080 13F0807F tst r3, #16777216 + 146 0084 00D0 beq .L7 + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** plli2sused = 1; + 147 .loc 1 176 18 view .LVU45 + 148 0086 0126 movs r6, #1 + 149 .LVL7: + 150 .L7: + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*------------------------------------ RTC configuration --------------------------------------*/ + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + 151 .loc 1 180 3 is_stmt 1 view .LVU46 + 152 .loc 1 180 5 is_stmt 0 view .LVU47 + 153 0088 13F0200F tst r3, #32 + 154 008c 40F03B81 bne .L77 + 155 .LVL8: + 156 .L8: + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check for RTC Parameters used to output RTCCLK */ + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable Power Clock*/ + ARM GAS /tmp/ccgN7hfx.s page 7 + + + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable write access to Backup domain */ + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PWR->CR1 |= PWR_CR1_DBP; + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get Start Tick*/ + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait for Backup domain Write protection disable */ + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while((PWR->CR1 & PWR_CR1_DBP) == RESET) + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Reset the Backup domain only if the RTC Clock source selection is modified */ + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL) + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Store the content of BDCR register before the reset of Backup Domain */ + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* RTC Clock selection can be changed only if the Backup Domain is reset */ + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_FORCE(); + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_RELEASE(); + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Restore the Content of BDCR register */ + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC->BDCR = tmpreg0; + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get Start Tick*/ + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait till LSE is ready */ + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 157 .loc 1 234 5 is_stmt 1 discriminator 5 view .LVU48 + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*------------------------------------ TIM configuration --------------------------------------*/ + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + 158 .loc 1 238 3 view .LVU49 + 159 .loc 1 238 21 is_stmt 0 view .LVU50 + 160 0090 2368 ldr r3, [r4] + ARM GAS /tmp/ccgN7hfx.s page 8 + + + 161 .loc 1 238 5 view .LVU51 + 162 0092 13F0100F tst r3, #16 + 163 0096 0CD0 beq .L17 + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); + 164 .loc 1 241 5 is_stmt 1 view .LVU52 + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure Timer Prescaler */ + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + 165 .loc 1 244 5 view .LVU53 + 166 .loc 1 244 5 view .LVU54 + 167 0098 924B ldr r3, .L87 + 168 009a D3F88C20 ldr r2, [r3, #140] + 169 009e 22F08072 bic r2, r2, #16777216 + 170 00a2 C3F88C20 str r2, [r3, #140] + 171 .loc 1 244 5 view .LVU55 + 172 00a6 D3F88C20 ldr r2, [r3, #140] + 173 00aa A16B ldr r1, [r4, #56] + 174 00ac 0A43 orrs r2, r2, r1 + 175 00ae C3F88C20 str r2, [r3, #140] + 176 .L17: + 177 .loc 1 244 5 discriminator 1 view .LVU56 + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- I2C1 Configuration -----------------------------------*/ + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 178 .loc 1 248 3 view .LVU57 + 179 .loc 1 248 21 is_stmt 0 view .LVU58 + 180 00b2 2368 ldr r3, [r4] + 181 .loc 1 248 5 view .LVU59 + 182 00b4 13F4804F tst r3, #16384 + 183 00b8 08D0 beq .L18 + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + 184 .loc 1 251 5 is_stmt 1 view .LVU60 + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the I2C1 clock source */ + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 185 .loc 1 254 5 view .LVU61 + 186 00ba 8A4A ldr r2, .L87 + 187 00bc D2F89030 ldr r3, [r2, #144] + 188 00c0 23F44033 bic r3, r3, #196608 + 189 00c4 616E ldr r1, [r4, #100] + 190 00c6 0B43 orrs r3, r3, r1 + 191 00c8 C2F89030 str r3, [r2, #144] + 192 .L18: + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- I2C2 Configuration -----------------------------------*/ + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + 193 .loc 1 258 3 view .LVU62 + 194 .loc 1 258 21 is_stmt 0 view .LVU63 + 195 00cc 2368 ldr r3, [r4] + 196 .loc 1 258 5 view .LVU64 + 197 00ce 13F4004F tst r3, #32768 + ARM GAS /tmp/ccgN7hfx.s page 9 + + + 198 00d2 08D0 beq .L19 + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + 199 .loc 1 261 5 is_stmt 1 view .LVU65 + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the I2C2 clock source */ + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + 200 .loc 1 264 5 view .LVU66 + 201 00d4 834A ldr r2, .L87 + 202 00d6 D2F89030 ldr r3, [r2, #144] + 203 00da 23F44023 bic r3, r3, #786432 + 204 00de A16E ldr r1, [r4, #104] + 205 00e0 0B43 orrs r3, r3, r1 + 206 00e2 C2F89030 str r3, [r2, #144] + 207 .L19: + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- I2C3 Configuration -----------------------------------*/ + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + 208 .loc 1 268 3 view .LVU67 + 209 .loc 1 268 21 is_stmt 0 view .LVU68 + 210 00e6 2368 ldr r3, [r4] + 211 .loc 1 268 5 view .LVU69 + 212 00e8 13F4803F tst r3, #65536 + 213 00ec 08D0 beq .L20 + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + 214 .loc 1 271 5 is_stmt 1 view .LVU70 + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the I2C3 clock source */ + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + 215 .loc 1 274 5 view .LVU71 + 216 00ee 7D4A ldr r2, .L87 + 217 00f0 D2F89030 ldr r3, [r2, #144] + 218 00f4 23F44013 bic r3, r3, #3145728 + 219 00f8 E16E ldr r1, [r4, #108] + 220 00fa 0B43 orrs r3, r3, r1 + 221 00fc C2F89030 str r3, [r2, #144] + 222 .L20: + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- I2C4 Configuration -----------------------------------*/ + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) + 223 .loc 1 278 3 view .LVU72 + 224 .loc 1 278 21 is_stmt 0 view .LVU73 + 225 0100 2368 ldr r3, [r4] + 226 .loc 1 278 5 view .LVU74 + 227 0102 13F4003F tst r3, #131072 + 228 0106 08D0 beq .L21 + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); + 229 .loc 1 281 5 is_stmt 1 view .LVU75 + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the I2C4 clock source */ + ARM GAS /tmp/ccgN7hfx.s page 10 + + + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); + 230 .loc 1 284 5 view .LVU76 + 231 0108 764A ldr r2, .L87 + 232 010a D2F89030 ldr r3, [r2, #144] + 233 010e 23F44003 bic r3, r3, #12582912 + 234 0112 216F ldr r1, [r4, #112] + 235 0114 0B43 orrs r3, r3, r1 + 236 0116 C2F89030 str r3, [r2, #144] + 237 .L21: + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- USART1 Configuration ----------------------------------- + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 238 .loc 1 288 3 view .LVU77 + 239 .loc 1 288 21 is_stmt 0 view .LVU78 + 240 011a 2368 ldr r3, [r4] + 241 .loc 1 288 5 view .LVU79 + 242 011c 13F0400F tst r3, #64 + 243 0120 08D0 beq .L22 + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + 244 .loc 1 291 5 is_stmt 1 view .LVU80 + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the USART1 clock source */ + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 245 .loc 1 294 5 view .LVU81 + 246 0122 704A ldr r2, .L87 + 247 0124 D2F89030 ldr r3, [r2, #144] + 248 0128 23F00303 bic r3, r3, #3 + 249 012c 616C ldr r1, [r4, #68] + 250 012e 0B43 orrs r3, r3, r1 + 251 0130 C2F89030 str r3, [r2, #144] + 252 .L22: + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- USART2 Configuration ----------------------------------- + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 253 .loc 1 298 3 view .LVU82 + 254 .loc 1 298 21 is_stmt 0 view .LVU83 + 255 0134 2368 ldr r3, [r4] + 256 .loc 1 298 5 view .LVU84 + 257 0136 13F0800F tst r3, #128 + 258 013a 08D0 beq .L23 + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + 259 .loc 1 301 5 is_stmt 1 view .LVU85 + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the USART2 clock source */ + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 260 .loc 1 304 5 view .LVU86 + 261 013c 694A ldr r2, .L87 + 262 013e D2F89030 ldr r3, [r2, #144] + 263 0142 23F00C03 bic r3, r3, #12 + 264 0146 A16C ldr r1, [r4, #72] + 265 0148 0B43 orrs r3, r3, r1 + ARM GAS /tmp/ccgN7hfx.s page 11 + + + 266 014a C2F89030 str r3, [r2, #144] + 267 .L23: + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- USART3 Configuration ----------------------------------- + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + 268 .loc 1 308 3 view .LVU87 + 269 .loc 1 308 21 is_stmt 0 view .LVU88 + 270 014e 2368 ldr r3, [r4] + 271 .loc 1 308 5 view .LVU89 + 272 0150 13F4807F tst r3, #256 + 273 0154 08D0 beq .L24 + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + 274 .loc 1 311 5 is_stmt 1 view .LVU90 + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the USART3 clock source */ + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + 275 .loc 1 314 5 view .LVU91 + 276 0156 634A ldr r2, .L87 + 277 0158 D2F89030 ldr r3, [r2, #144] + 278 015c 23F03003 bic r3, r3, #48 + 279 0160 E16C ldr r1, [r4, #76] + 280 0162 0B43 orrs r3, r3, r1 + 281 0164 C2F89030 str r3, [r2, #144] + 282 .L24: + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- UART4 Configuration -----------------------------------* + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + 283 .loc 1 318 3 view .LVU92 + 284 .loc 1 318 21 is_stmt 0 view .LVU93 + 285 0168 2368 ldr r3, [r4] + 286 .loc 1 318 5 view .LVU94 + 287 016a 13F4007F tst r3, #512 + 288 016e 08D0 beq .L25 + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); + 289 .loc 1 321 5 is_stmt 1 view .LVU95 + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the UART4 clock source */ + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); + 290 .loc 1 324 5 view .LVU96 + 291 0170 5C4A ldr r2, .L87 + 292 0172 D2F89030 ldr r3, [r2, #144] + 293 0176 23F0C003 bic r3, r3, #192 + 294 017a 216D ldr r1, [r4, #80] + 295 017c 0B43 orrs r3, r3, r1 + 296 017e C2F89030 str r3, [r2, #144] + 297 .L25: + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- UART5 Configuration -----------------------------------* + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + 298 .loc 1 328 3 view .LVU97 + ARM GAS /tmp/ccgN7hfx.s page 12 + + + 299 .loc 1 328 21 is_stmt 0 view .LVU98 + 300 0182 2368 ldr r3, [r4] + 301 .loc 1 328 5 view .LVU99 + 302 0184 13F4806F tst r3, #1024 + 303 0188 08D0 beq .L26 + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); + 304 .loc 1 331 5 is_stmt 1 view .LVU100 + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the UART5 clock source */ + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); + 305 .loc 1 334 5 view .LVU101 + 306 018a 564A ldr r2, .L87 + 307 018c D2F89030 ldr r3, [r2, #144] + 308 0190 23F44073 bic r3, r3, #768 + 309 0194 616D ldr r1, [r4, #84] + 310 0196 0B43 orrs r3, r3, r1 + 311 0198 C2F89030 str r3, [r2, #144] + 312 .L26: + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- USART6 Configuration ----------------------------------- + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) + 313 .loc 1 338 3 view .LVU102 + 314 .loc 1 338 21 is_stmt 0 view .LVU103 + 315 019c 2368 ldr r3, [r4] + 316 .loc 1 338 5 view .LVU104 + 317 019e 13F4006F tst r3, #2048 + 318 01a2 08D0 beq .L27 + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); + 319 .loc 1 341 5 is_stmt 1 view .LVU105 + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the USART6 clock source */ + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); + 320 .loc 1 344 5 view .LVU106 + 321 01a4 4F4A ldr r2, .L87 + 322 01a6 D2F89030 ldr r3, [r2, #144] + 323 01aa 23F44063 bic r3, r3, #3072 + 324 01ae A16D ldr r1, [r4, #88] + 325 01b0 0B43 orrs r3, r3, r1 + 326 01b2 C2F89030 str r3, [r2, #144] + 327 .L27: + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- UART7 Configuration -----------------------------------* + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) + 328 .loc 1 348 3 view .LVU107 + 329 .loc 1 348 21 is_stmt 0 view .LVU108 + 330 01b6 2368 ldr r3, [r4] + 331 .loc 1 348 5 view .LVU109 + 332 01b8 13F4805F tst r3, #4096 + 333 01bc 08D0 beq .L28 + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + ARM GAS /tmp/ccgN7hfx.s page 13 + + + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); + 334 .loc 1 351 5 is_stmt 1 view .LVU110 + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the UART7 clock source */ + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); + 335 .loc 1 354 5 view .LVU111 + 336 01be 494A ldr r2, .L87 + 337 01c0 D2F89030 ldr r3, [r2, #144] + 338 01c4 23F44053 bic r3, r3, #12288 + 339 01c8 E16D ldr r1, [r4, #92] + 340 01ca 0B43 orrs r3, r3, r1 + 341 01cc C2F89030 str r3, [r2, #144] + 342 .L28: + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- UART8 Configuration -----------------------------------* + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) + 343 .loc 1 358 3 view .LVU112 + 344 .loc 1 358 21 is_stmt 0 view .LVU113 + 345 01d0 2368 ldr r3, [r4] + 346 .loc 1 358 5 view .LVU114 + 347 01d2 13F4005F tst r3, #8192 + 348 01d6 08D0 beq .L29 + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); + 349 .loc 1 361 5 is_stmt 1 view .LVU115 + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the UART8 clock source */ + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); + 350 .loc 1 364 5 view .LVU116 + 351 01d8 424A ldr r2, .L87 + 352 01da D2F89030 ldr r3, [r2, #144] + 353 01de 23F44043 bic r3, r3, #49152 + 354 01e2 216E ldr r1, [r4, #96] + 355 01e4 0B43 orrs r3, r3, r1 + 356 01e6 C2F89030 str r3, [r2, #144] + 357 .L29: + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*--------------------------------------- CEC Configuration -----------------------------------*/ + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + 358 .loc 1 368 3 view .LVU117 + 359 .loc 1 368 21 is_stmt 0 view .LVU118 + 360 01ea 2368 ldr r3, [r4] + 361 .loc 1 368 5 view .LVU119 + 362 01ec 13F4800F tst r3, #4194304 + 363 01f0 08D0 beq .L30 + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + 364 .loc 1 371 5 is_stmt 1 view .LVU120 + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the CEC clock source */ + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + 365 .loc 1 374 5 view .LVU121 + 366 01f2 3C4A ldr r2, .L87 + ARM GAS /tmp/ccgN7hfx.s page 14 + + + 367 01f4 D2F89030 ldr r3, [r2, #144] + 368 01f8 23F08063 bic r3, r3, #67108864 + 369 01fc A16F ldr r1, [r4, #120] + 370 01fe 0B43 orrs r3, r3, r1 + 371 0200 C2F89030 str r3, [r2, #144] + 372 .L30: + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- CK48 Configuration -----------------------------------*/ + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + 373 .loc 1 378 3 view .LVU122 + 374 .loc 1 378 21 is_stmt 0 view .LVU123 + 375 0204 2368 ldr r3, [r4] + 376 .loc 1 378 5 view .LVU124 + 377 0206 13F4001F tst r3, #2097152 + 378 020a 0DD0 beq .L31 + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); + 379 .loc 1 381 5 is_stmt 1 view .LVU125 + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the CLK48 source */ + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + 380 .loc 1 384 5 view .LVU126 + 381 020c 354A ldr r2, .L87 + 382 020e D2F89030 ldr r3, [r2, #144] + 383 0212 23F00063 bic r3, r3, #134217728 + 384 0216 E16F ldr r1, [r4, #124] + 385 0218 0B43 orrs r3, r3, r1 + 386 021a C2F89030 str r3, [r2, #144] + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable the PLLSAI when it's used as clock source for CK48 */ + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) + 387 .loc 1 387 5 view .LVU127 + 388 .loc 1 387 21 is_stmt 0 view .LVU128 + 389 021e E36F ldr r3, [r4, #124] + 390 .loc 1 387 7 view .LVU129 + 391 0220 B3F1006F cmp r3, #134217728 + 392 0224 00F0D580 beq .L78 + 393 .LVL9: + 394 .L31: + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** pllsaiused = 1; + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- LTDC Configuration -----------------------------------*/ + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + 395 .loc 1 395 3 is_stmt 1 view .LVU130 + 396 .loc 1 395 21 is_stmt 0 view .LVU131 + 397 0228 2368 ldr r3, [r4] + 398 .loc 1 395 5 view .LVU132 + 399 022a 13F0080F tst r3, #8 + 400 022e 00D0 beq .L32 + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** pllsaiused = 1; + ARM GAS /tmp/ccgN7hfx.s page 15 + + + 401 .loc 1 397 16 view .LVU133 + 402 0230 0125 movs r5, #1 + 403 .LVL10: + 404 .L32: + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- LPTIM1 Configuration ----------------------------------- + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + 405 .loc 1 402 3 is_stmt 1 view .LVU134 + 406 .loc 1 402 5 is_stmt 0 view .LVU135 + 407 0232 13F4802F tst r3, #262144 + 408 0236 08D0 beq .L33 + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); + 409 .loc 1 405 5 is_stmt 1 view .LVU136 + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the LTPIM1 clock source */ + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + 410 .loc 1 408 5 view .LVU137 + 411 0238 2A4A ldr r2, .L87 + 412 023a D2F89030 ldr r3, [r2, #144] + 413 023e 23F04073 bic r3, r3, #50331648 + 414 0242 616F ldr r1, [r4, #116] + 415 0244 0B43 orrs r3, r3, r1 + 416 0246 C2F89030 str r3, [r2, #144] + 417 .L33: + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*------------------------------------- SDMMC1 Configuration ------------------------------------ + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) + 418 .loc 1 412 3 view .LVU138 + 419 .loc 1 412 21 is_stmt 0 view .LVU139 + 420 024a 2368 ldr r3, [r4] + 421 .loc 1 412 5 view .LVU140 + 422 024c 13F4000F tst r3, #8388608 + 423 0250 09D0 beq .L34 + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); + 424 .loc 1 415 5 is_stmt 1 view .LVU141 + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the SDMMC1 clock source */ + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); + 425 .loc 1 418 5 view .LVU142 + 426 0252 244A ldr r2, .L87 + 427 0254 D2F89030 ldr r3, [r2, #144] + 428 0258 23F08053 bic r3, r3, #268435456 + 429 025c D4F88010 ldr r1, [r4, #128] + 430 0260 0B43 orrs r3, r3, r1 + 431 0262 C2F89030 str r3, [r2, #144] + 432 .L34: + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*------------------------------------- SDMMC2 Configuration ------------------------------------ + ARM GAS /tmp/ccgN7hfx.s page 16 + + + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) + 433 .loc 1 423 3 view .LVU143 + 434 .loc 1 423 21 is_stmt 0 view .LVU144 + 435 0266 2368 ldr r3, [r4] + 436 .loc 1 423 5 view .LVU145 + 437 0268 13F0806F tst r3, #67108864 + 438 026c 09D0 beq .L35 + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); + 439 .loc 1 426 5 is_stmt 1 view .LVU146 + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the SDMMC2 clock source */ + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); + 440 .loc 1 429 5 view .LVU147 + 441 026e 1D4A ldr r2, .L87 + 442 0270 D2F89030 ldr r3, [r2, #144] + 443 0274 23F00053 bic r3, r3, #536870912 + 444 0278 D4F88410 ldr r1, [r4, #132] + 445 027c 0B43 orrs r3, r3, r1 + 446 027e C2F89030 str r3, [r2, #144] + 447 .L35: + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*------------------------------------- DFSDM1 Configuration ------------------------------------ + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) + 448 .loc 1 433 3 view .LVU148 + 449 .loc 1 433 21 is_stmt 0 view .LVU149 + 450 0282 2368 ldr r3, [r4] + 451 .loc 1 433 5 view .LVU150 + 452 0284 13F0006F tst r3, #134217728 + 453 0288 09D0 beq .L36 + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); + 454 .loc 1 436 5 is_stmt 1 view .LVU151 + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the DFSDM1 interface clock source */ + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); + 455 .loc 1 439 5 view .LVU152 + 456 028a 164A ldr r2, .L87 + 457 028c D2F88C30 ldr r3, [r2, #140] + 458 0290 23F00073 bic r3, r3, #33554432 + 459 0294 D4F88810 ldr r1, [r4, #136] + 460 0298 0B43 orrs r3, r3, r1 + 461 029a C2F88C30 str r3, [r2, #140] + 462 .L36: + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*------------------------------------- DFSDM AUDIO Configuration ------------------------------- + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_A + 463 .loc 1 443 3 view .LVU153 + 464 .loc 1 443 21 is_stmt 0 view .LVU154 + 465 029e 2368 ldr r3, [r4] + 466 .loc 1 443 5 view .LVU155 + 467 02a0 13F0805F tst r3, #268435456 + 468 02a4 09D0 beq .L37 + ARM GAS /tmp/ccgN7hfx.s page 17 + + + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); + 469 .loc 1 446 5 is_stmt 1 view .LVU156 + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the DFSDM interface clock source */ + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); + 470 .loc 1 449 5 view .LVU157 + 471 02a6 0F4A ldr r2, .L87 + 472 02a8 D2F88C30 ldr r3, [r2, #140] + 473 02ac 23F08063 bic r3, r3, #67108864 + 474 02b0 D4F88C10 ldr r1, [r4, #140] + 475 02b4 0B43 orrs r3, r3, r1 + 476 02b6 C2F88C30 str r3, [r2, #140] + 477 .L37: + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF- + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERI + 478 .loc 1 455 3 view .LVU158 + 479 .loc 1 455 5 is_stmt 0 view .LVU159 + 480 02ba 26B9 cbnz r6, .L38 + 481 .loc 1 455 42 discriminator 1 view .LVU160 + 482 02bc 2368 ldr r3, [r4] + 483 .loc 1 455 24 discriminator 1 view .LVU161 + 484 02be 13F0007F tst r3, #33554432 + 485 02c2 00F00681 beq .L39 + 486 .L38: + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Disable the PLLI2S */ + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLI2S_DISABLE(); + 487 .loc 1 458 5 is_stmt 1 view .LVU162 + 488 02c6 074A ldr r2, .L87 + 489 02c8 1368 ldr r3, [r2] + 490 02ca 23F08063 bic r3, r3, #67108864 + 491 02ce 1360 str r3, [r2] + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get Start Tick*/ + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 492 .loc 1 461 5 view .LVU163 + 493 .loc 1 461 17 is_stmt 0 view .LVU164 + 494 02d0 FFF7FEFF bl HAL_GetTick + 495 .LVL11: + 496 02d4 0646 mov r6, r0 + 497 .LVL12: + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait till PLLI2S is disabled */ + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + 498 .loc 1 464 5 is_stmt 1 view .LVU165 + 499 .L40: + 500 .loc 1 464 51 view .LVU166 + 501 .loc 1 464 11 is_stmt 0 view .LVU167 + 502 02d6 034B ldr r3, .L87 + 503 02d8 1B68 ldr r3, [r3] + 504 .loc 1 464 51 view .LVU168 + ARM GAS /tmp/ccgN7hfx.s page 18 + + + 505 02da 13F0006F tst r3, #134217728 + 506 02de 7AD0 beq .L79 + 507 02e0 02E0 b .L88 + 508 .L89: + 509 02e2 00BF .align 2 + 510 .L87: + 511 02e4 00380240 .word 1073887232 + 512 .L88: + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + 513 .loc 1 466 7 is_stmt 1 view .LVU169 + 514 .loc 1 466 11 is_stmt 0 view .LVU170 + 515 02e8 FFF7FEFF bl HAL_GetTick + 516 .LVL13: + 517 .loc 1 466 25 discriminator 1 view .LVU171 + 518 02ec 801B subs r0, r0, r6 + 519 .loc 1 466 9 discriminator 1 view .LVU172 + 520 02ee 6428 cmp r0, #100 + 521 02f0 F1D9 bls .L40 + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* return in case of Timeout detected */ + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 522 .loc 1 469 16 view .LVU173 + 523 02f2 0320 movs r0, #3 + 524 02f4 F0E0 b .L10 + 525 .LVL14: + 526 .L59: + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 527 .loc 1 128 18 view .LVU174 + 528 02f6 0126 movs r6, #1 + 529 02f8 97E6 b .L2 + 530 .LVL15: + 531 .L75: + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 532 .loc 1 143 18 view .LVU175 + 533 02fa 0126 movs r6, #1 + 534 .LVL16: + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 535 .loc 1 143 18 view .LVU176 + 536 02fc A7E6 b .L4 + 537 .LVL17: + 538 .L61: + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 539 .loc 1 148 18 view .LVU177 + 540 02fe 0125 movs r5, #1 + 541 0300 A9E6 b .L3 + 542 .LVL18: + 543 .L76: + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 544 .loc 1 164 18 view .LVU178 + 545 0302 0126 movs r6, #1 + 546 .LVL19: + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 547 .loc 1 164 18 view .LVU179 + 548 0304 B9E6 b .L6 + 549 .LVL20: + 550 .L77: + ARM GAS /tmp/ccgN7hfx.s page 19 + + + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 551 .loc 1 183 5 is_stmt 1 view .LVU180 + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 552 .loc 1 186 5 view .LVU181 + 553 .LBB2: + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 554 .loc 1 186 5 view .LVU182 + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 555 .loc 1 186 5 view .LVU183 + 556 0306 7F4B ldr r3, .L90 + 557 0308 1A6C ldr r2, [r3, #64] + 558 030a 42F08052 orr r2, r2, #268435456 + 559 030e 1A64 str r2, [r3, #64] + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 560 .loc 1 186 5 view .LVU184 + 561 0310 1B6C ldr r3, [r3, #64] + 562 0312 03F08053 and r3, r3, #268435456 + 563 0316 0193 str r3, [sp, #4] + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 564 .loc 1 186 5 view .LVU185 + 565 0318 019B ldr r3, [sp, #4] + 566 .LBE2: + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 567 .loc 1 186 5 view .LVU186 + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 568 .loc 1 189 5 view .LVU187 + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 569 .loc 1 189 8 is_stmt 0 view .LVU188 + 570 031a 7B4A ldr r2, .L90+4 + 571 031c 1368 ldr r3, [r2] + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 572 .loc 1 189 14 view .LVU189 + 573 031e 43F48073 orr r3, r3, #256 + 574 0322 1360 str r3, [r2] + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 575 .loc 1 192 5 is_stmt 1 view .LVU190 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 576 .loc 1 192 17 is_stmt 0 view .LVU191 + 577 0324 FFF7FEFF bl HAL_GetTick + 578 .LVL21: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 579 .loc 1 192 17 view .LVU192 + 580 0328 0746 mov r7, r0 + 581 .LVL22: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 582 .loc 1 195 5 is_stmt 1 view .LVU193 + 583 .L9: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 584 .loc 1 195 36 view .LVU194 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 585 .loc 1 195 15 is_stmt 0 view .LVU195 + 586 032a 774B ldr r3, .L90+4 + 587 032c 1B68 ldr r3, [r3] + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 588 .loc 1 195 36 view .LVU196 + 589 032e 13F4807F tst r3, #256 + 590 0332 06D1 bne .L80 + ARM GAS /tmp/ccgN7hfx.s page 20 + + + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 591 .loc 1 197 7 is_stmt 1 view .LVU197 + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 592 .loc 1 197 11 is_stmt 0 view .LVU198 + 593 0334 FFF7FEFF bl HAL_GetTick + 594 .LVL23: + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 595 .loc 1 197 25 discriminator 1 view .LVU199 + 596 0338 C01B subs r0, r0, r7 + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 597 .loc 1 197 9 discriminator 1 view .LVU200 + 598 033a 6428 cmp r0, #100 + 599 033c F5D9 bls .L9 + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 600 .loc 1 199 16 view .LVU201 + 601 033e 0320 movs r0, #3 + 602 0340 CAE0 b .L10 + 603 .L80: + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 604 .loc 1 204 5 is_stmt 1 view .LVU202 + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 605 .loc 1 204 19 is_stmt 0 view .LVU203 + 606 0342 704B ldr r3, .L90 + 607 0344 1B6F ldr r3, [r3, #112] + 608 .LVL24: + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 609 .loc 1 206 5 is_stmt 1 view .LVU204 + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 610 .loc 1 206 7 is_stmt 0 view .LVU205 + 611 0346 13F44073 ands r3, r3, #768 + 612 .LVL25: + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 613 .loc 1 206 7 view .LVU206 + 614 034a 15D0 beq .L12 + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 615 .loc 1 206 62 discriminator 1 view .LVU207 + 616 034c 226B ldr r2, [r4, #48] + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 617 .loc 1 206 82 discriminator 1 view .LVU208 + 618 034e 02F44072 and r2, r2, #768 + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 619 .loc 1 206 33 discriminator 1 view .LVU209 + 620 0352 9A42 cmp r2, r3 + 621 0354 10D0 beq .L12 + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 622 .loc 1 209 7 is_stmt 1 view .LVU210 + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 623 .loc 1 209 21 is_stmt 0 view .LVU211 + 624 0356 6B4B ldr r3, .L90 + 625 .LVL26: + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 626 .loc 1 209 21 view .LVU212 + 627 0358 1A6F ldr r2, [r3, #112] + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 628 .loc 1 209 15 view .LVU213 + 629 035a 22F44072 bic r2, r2, #768 + 630 .LVL27: + ARM GAS /tmp/ccgN7hfx.s page 21 + + + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_RELEASE(); + 631 .loc 1 212 7 is_stmt 1 view .LVU214 + 632 035e 196F ldr r1, [r3, #112] + 633 0360 41F48031 orr r1, r1, #65536 + 634 0364 1967 str r1, [r3, #112] + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 635 .loc 1 213 7 view .LVU215 + 636 0366 196F ldr r1, [r3, #112] + 637 0368 21F48031 bic r1, r1, #65536 + 638 036c 1967 str r1, [r3, #112] + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 639 .loc 1 216 7 view .LVU216 + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 640 .loc 1 216 17 is_stmt 0 view .LVU217 + 641 036e 1A67 str r2, [r3, #112] + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 642 .loc 1 219 7 is_stmt 1 view .LVU218 + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 643 .loc 1 219 11 is_stmt 0 view .LVU219 + 644 0370 1B6F ldr r3, [r3, #112] + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 645 .loc 1 219 10 view .LVU220 + 646 0372 13F0010F tst r3, #1 + 647 0376 12D1 bne .L81 + 648 .LVL28: + 649 .L12: + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 650 .loc 1 234 5 is_stmt 1 view .LVU221 + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 651 .loc 1 234 5 view .LVU222 + 652 0378 236B ldr r3, [r4, #48] + 653 037a 03F44072 and r2, r3, #768 + 654 037e B2F5407F cmp r2, #768 + 655 0382 1DD0 beq .L82 + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 656 .loc 1 234 5 is_stmt 0 discriminator 2 view .LVU223 + 657 0384 5F4A ldr r2, .L90 + 658 0386 9368 ldr r3, [r2, #8] + 659 0388 23F4F813 bic r3, r3, #2031616 + 660 038c 9360 str r3, [r2, #8] + 661 .L16: + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 662 .loc 1 234 5 is_stmt 1 discriminator 4 view .LVU224 + 663 038e 5D49 ldr r1, .L90 + 664 0390 0B6F ldr r3, [r1, #112] + 665 0392 226B ldr r2, [r4, #48] + 666 0394 C2F30B02 ubfx r2, r2, #0, #12 + 667 0398 1343 orrs r3, r3, r2 + 668 039a 0B67 str r3, [r1, #112] + 669 039c 78E6 b .L8 + 670 .LVL29: + 671 .L81: + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 672 .loc 1 222 9 view .LVU225 + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 673 .loc 1 222 21 is_stmt 0 view .LVU226 + 674 039e FFF7FEFF bl HAL_GetTick + ARM GAS /tmp/ccgN7hfx.s page 22 + + + 675 .LVL30: + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 676 .loc 1 222 21 view .LVU227 + 677 03a2 0746 mov r7, r0 + 678 .LVL31: + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 679 .loc 1 225 9 is_stmt 1 view .LVU228 + 680 .L13: + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 681 .loc 1 225 51 view .LVU229 + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 682 .loc 1 225 15 is_stmt 0 view .LVU230 + 683 03a4 574B ldr r3, .L90 + 684 03a6 1B6F ldr r3, [r3, #112] + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 685 .loc 1 225 51 view .LVU231 + 686 03a8 13F0020F tst r3, #2 + 687 03ac E4D1 bne .L12 + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 688 .loc 1 227 11 is_stmt 1 view .LVU232 + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 689 .loc 1 227 15 is_stmt 0 view .LVU233 + 690 03ae FFF7FEFF bl HAL_GetTick + 691 .LVL32: + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 692 .loc 1 227 29 discriminator 1 view .LVU234 + 693 03b2 C01B subs r0, r0, r7 + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 694 .loc 1 227 13 discriminator 1 view .LVU235 + 695 03b4 41F28833 movw r3, #5000 + 696 03b8 9842 cmp r0, r3 + 697 03ba F3D9 bls .L13 + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 698 .loc 1 229 20 view .LVU236 + 699 03bc 0320 movs r0, #3 + 700 03be 8BE0 b .L10 + 701 .LVL33: + 702 .L82: + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 703 .loc 1 234 5 discriminator 1 view .LVU237 + 704 03c0 5048 ldr r0, .L90 + 705 03c2 8268 ldr r2, [r0, #8] + 706 03c4 22F4F812 bic r2, r2, #2031616 + 707 03c8 5049 ldr r1, .L90+8 + 708 03ca 1940 ands r1, r1, r3 + 709 03cc 0A43 orrs r2, r2, r1 + 710 03ce 8260 str r2, [r0, #8] + 711 03d0 DDE7 b .L16 + 712 .LVL34: + 713 .L78: + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 714 .loc 1 389 18 view .LVU238 + 715 03d2 0125 movs r5, #1 + 716 .LVL35: + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 717 .loc 1 389 18 view .LVU239 + 718 03d4 28E7 b .L31 + ARM GAS /tmp/ccgN7hfx.s page 23 + + + 719 .LVL36: + 720 .L79: + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* check for common PLLI2S Parameters */ + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + 721 .loc 1 474 5 is_stmt 1 view .LVU240 + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (Peri + 722 .loc 1 477 5 view .LVU241 + 723 .loc 1 477 25 is_stmt 0 view .LVU242 + 724 03d6 2368 ldr r3, [r4] + 725 .loc 1 477 7 view .LVU243 + 726 03d8 13F0010F tst r3, #1 + 727 03dc 13D0 beq .L42 + 728 .loc 1 477 109 discriminator 1 view .LVU244 + 729 03de 636B ldr r3, [r4, #52] + 730 .loc 1 477 92 discriminator 1 view .LVU245 + 731 03e0 8BB9 cbnz r3, .L42 + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* check for Parameters */ + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + 732 .loc 1 480 7 is_stmt 1 view .LVU246 + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + 733 .loc 1 483 7 view .LVU247 + 734 .loc 1 483 22 is_stmt 0 view .LVU248 + 735 03e2 484A ldr r2, .L90 + 736 03e4 D2F88430 ldr r3, [r2, #132] + 737 .LVL37: + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + 738 .loc 1 484 7 is_stmt 1 view .LVU249 + 739 .loc 1 484 22 is_stmt 0 view .LVU250 + 740 03e8 D2F88410 ldr r1, [r2, #132] + 741 .LVL38: + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the PLLI2S division factors */ + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI + 742 .loc 1 488 7 is_stmt 1 view .LVU251 + 743 03ec 6068 ldr r0, [r4, #4] + 744 03ee 03F44033 and r3, r3, #196608 + 745 .LVL39: + 746 .loc 1 488 7 is_stmt 0 view .LVU252 + 747 03f2 43EA8013 orr r3, r3, r0, lsl #6 + 748 03f6 01F07061 and r1, r1, #251658240 + 749 .LVL40: + 750 .loc 1 488 7 view .LVU253 + 751 03fa 0B43 orrs r3, r3, r1 + 752 03fc A168 ldr r1, [r4, #8] + 753 03fe 43EA0173 orr r3, r3, r1, lsl #28 + 754 0402 C2F88430 str r3, [r2, #132] + 755 .LVL41: + 756 .L42: + ARM GAS /tmp/ccgN7hfx.s page 24 + + + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (Pe + 757 .loc 1 492 5 is_stmt 1 view .LVU254 + 758 .loc 1 492 25 is_stmt 0 view .LVU255 + 759 0406 2368 ldr r3, [r4] + 760 .loc 1 492 7 view .LVU256 + 761 0408 13F4002F tst r3, #524288 + 762 040c 03D0 beq .L43 + 763 .loc 1 492 111 discriminator 1 view .LVU257 + 764 040e E26B ldr r2, [r4, #60] + 765 .loc 1 492 94 discriminator 1 view .LVU258 + 766 0410 B2F5801F cmp r2, #1048576 + 767 0414 06D0 beq .L44 + 768 .L43: + 769 .loc 1 492 162 discriminator 3 view .LVU259 + 770 0416 13F4801F tst r3, #1048576 + 771 041a 1ED0 beq .L45 + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe + 772 .loc 1 493 111 view .LVU260 + 773 041c 236C ldr r3, [r4, #64] + 774 .loc 1 493 94 view .LVU261 + 775 041e B3F5800F cmp r3, #4194304 + 776 0422 1AD1 bne .L45 + 777 .L44: + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check for PLLI2S Parameters */ + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + 778 .loc 1 496 7 is_stmt 1 view .LVU262 + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check for PLLI2S/DIVQ parameters */ + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + 779 .loc 1 498 7 view .LVU263 + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + 780 .loc 1 501 7 view .LVU264 + 781 .loc 1 501 22 is_stmt 0 view .LVU265 + 782 0424 374A ldr r2, .L90 + 783 0426 D2F88430 ldr r3, [r2, #132] + 784 .LVL42: + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + 785 .loc 1 502 7 is_stmt 1 view .LVU266 + 786 .loc 1 502 22 is_stmt 0 view .LVU267 + 787 042a D2F88410 ldr r1, [r2, #132] + 788 .LVL43: + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the PLLI2S division factors */ + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ + 789 .loc 1 507 7 is_stmt 1 view .LVU268 + 790 042e 6068 ldr r0, [r4, #4] + 791 0430 03F44033 and r3, r3, #196608 + 792 .LVL44: + 793 .loc 1 507 7 is_stmt 0 view .LVU269 + 794 0434 43EA8013 orr r3, r3, r0, lsl #6 + ARM GAS /tmp/ccgN7hfx.s page 25 + + + 795 0438 E068 ldr r0, [r4, #12] + 796 043a 43EA0063 orr r3, r3, r0, lsl #24 + 797 043e 01F0E041 and r1, r1, #1879048192 + 798 .LVL45: + 799 .loc 1 507 7 view .LVU270 + 800 0442 0B43 orrs r3, r3, r1 + 801 0444 C2F88430 str r3, [r2, #132] + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + 802 .loc 1 510 7 is_stmt 1 view .LVU271 + 803 0448 D2F88C30 ldr r3, [r2, #140] + 804 044c 23F01F03 bic r3, r3, #31 + 805 0450 616A ldr r1, [r4, #36] + 806 0452 0139 subs r1, r1, #1 + 807 0454 0B43 orrs r3, r3, r1 + 808 0456 C2F88C30 str r3, [r2, #140] + 809 .LVL46: + 810 .L45: + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX ---------------- + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + 811 .loc 1 514 5 view .LVU272 + 812 .loc 1 514 23 is_stmt 0 view .LVU273 + 813 045a 2368 ldr r3, [r4] + 814 .loc 1 514 7 view .LVU274 + 815 045c 13F0807F tst r3, #16777216 + 816 0460 11D0 beq .L46 + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* check for Parameters */ + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + 817 .loc 1 517 7 is_stmt 1 view .LVU275 + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configur + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + 818 .loc 1 520 7 view .LVU276 + 819 .loc 1 520 22 is_stmt 0 view .LVU277 + 820 0462 284A ldr r2, .L90 + 821 0464 D2F88400 ldr r0, [r2, #132] + 822 .LVL47: + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + 823 .loc 1 521 7 is_stmt 1 view .LVU278 + 824 .loc 1 521 22 is_stmt 0 view .LVU279 + 825 0468 D2F88410 ldr r1, [r2, #132] + 826 .LVL48: + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the PLLI2S division factors */ + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg + 827 .loc 1 525 7 is_stmt 1 view .LVU280 + 828 046c 6668 ldr r6, [r4, #4] + 829 .LVL49: + 830 .loc 1 525 7 is_stmt 0 view .LVU281 + 831 046e 2369 ldr r3, [r4, #16] + 832 0470 1B04 lsls r3, r3, #16 + 833 0472 43EA8613 orr r3, r3, r6, lsl #6 + ARM GAS /tmp/ccgN7hfx.s page 26 + + + 834 0476 00F07060 and r0, r0, #251658240 + 835 .LVL50: + 836 .loc 1 525 7 view .LVU282 + 837 047a 0343 orrs r3, r3, r0 + 838 047c 01F0E041 and r1, r1, #1879048192 + 839 .LVL51: + 840 .loc 1 525 7 view .LVU283 + 841 0480 0B43 orrs r3, r3, r1 + 842 0482 C2F88430 str r3, [r2, #132] + 843 .LVL52: + 844 .L46: + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*----------------- In Case of PLLI2S is just selected -----------------*/ + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + 845 .loc 1 529 5 is_stmt 1 view .LVU284 + 846 .loc 1 529 22 is_stmt 0 view .LVU285 + 847 0486 2368 ldr r3, [r4] + 848 .loc 1 529 7 view .LVU286 + 849 0488 13F0007F tst r3, #33554432 + 850 048c 0DD0 beq .L47 + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check for Parameters */ + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + 851 .loc 1 532 7 is_stmt 1 view .LVU287 + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + 852 .loc 1 533 7 view .LVU288 + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + 853 .loc 1 534 7 view .LVU289 + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the PLLI2S division factors */ + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, Periph + 854 .loc 1 539 7 view .LVU290 + 855 048e 6268 ldr r2, [r4, #4] + 856 0490 2369 ldr r3, [r4, #16] + 857 0492 1B04 lsls r3, r3, #16 + 858 0494 43EA8213 orr r3, r3, r2, lsl #6 + 859 0498 E268 ldr r2, [r4, #12] + 860 049a 43EA0263 orr r3, r3, r2, lsl #24 + 861 049e A268 ldr r2, [r4, #8] + 862 04a0 43EA0273 orr r3, r3, r2, lsl #28 + 863 04a4 174A ldr r2, .L90 + 864 04a6 C2F88430 str r3, [r2, #132] + 865 .L47: + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable the PLLI2S */ + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLI2S_ENABLE(); + 866 .loc 1 543 5 view .LVU291 + 867 04aa 164A ldr r2, .L90 + 868 04ac 1368 ldr r3, [r2] + 869 04ae 43F08063 orr r3, r3, #67108864 + 870 04b2 1360 str r3, [r2] + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get Start Tick*/ + ARM GAS /tmp/ccgN7hfx.s page 27 + + + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 871 .loc 1 546 5 view .LVU292 + 872 .loc 1 546 17 is_stmt 0 view .LVU293 + 873 04b4 FFF7FEFF bl HAL_GetTick + 874 .LVL53: + 875 04b8 0646 mov r6, r0 + 876 .LVL54: + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait till PLLI2S is ready */ + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 877 .loc 1 549 5 is_stmt 1 view .LVU294 + 878 .L48: + 879 .loc 1 549 51 view .LVU295 + 880 .loc 1 549 11 is_stmt 0 view .LVU296 + 881 04ba 124B ldr r3, .L90 + 882 04bc 1B68 ldr r3, [r3] + 883 .loc 1 549 51 view .LVU297 + 884 04be 13F0006F tst r3, #134217728 + 885 04c2 06D1 bne .L39 + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + 886 .loc 1 551 7 is_stmt 1 view .LVU298 + 887 .loc 1 551 11 is_stmt 0 view .LVU299 + 888 04c4 FFF7FEFF bl HAL_GetTick + 889 .LVL55: + 890 .loc 1 551 25 discriminator 1 view .LVU300 + 891 04c8 801B subs r0, r0, r6 + 892 .loc 1 551 9 discriminator 1 view .LVU301 + 893 04ca 6428 cmp r0, #100 + 894 04cc F5D9 bls .L48 + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* return in case of Timeout detected */ + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 895 .loc 1 554 16 view .LVU302 + 896 04ce 0320 movs r0, #3 + 897 04d0 02E0 b .L10 + 898 .LVL56: + 899 .L39: + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(pllsaiused == 1) + 900 .loc 1 561 3 is_stmt 1 view .LVU303 + 901 .loc 1 561 5 is_stmt 0 view .LVU304 + 902 04d2 012D cmp r5, #1 + 903 04d4 02D0 beq .L83 + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Disable PLLSAI Clock */ + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLSAI_DISABLE(); + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get Start Tick*/ + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait till PLLSAI is disabled */ + ARM GAS /tmp/ccgN7hfx.s page 28 + + + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* return in case of Timeout detected */ + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the PLLSAI division factors */ + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (Pe + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* check for PLLSAIQ Parameter */ + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* check for PLLSAI/DIVQ Parameter */ + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuratio + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAI + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*----------------- In Case of PLLSAI is selected as source clock for CLK48 ------------------- + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* In Case of PLLI2S is selected as source clock for CK48 */ + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (P + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* check for Parameters */ + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the PLLSAI division factors */ + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*---------------------------- LTDC configuration -------------------------------*/ + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LT + ARM GAS /tmp/ccgN7hfx.s page 29 + + + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLS + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable PLLSAI Clock */ + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLSAI_ENABLE(); + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get Start Tick*/ + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait till PLLSAI is ready */ + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* return in case of Timeout detected */ + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_OK; + 904 .loc 1 656 10 view .LVU305 + 905 04d6 0020 movs r0, #0 + 906 .LVL57: + 907 .L10: + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 908 .loc 1 657 1 view .LVU306 + 909 04d8 03B0 add sp, sp, #12 + 910 .LCFI2: + 911 .cfi_remember_state + 912 .cfi_def_cfa_offset 20 + 913 @ sp needed + 914 04da F0BD pop {r4, r5, r6, r7, pc} + 915 .LVL58: + 916 .L83: + 917 .LCFI3: + 918 .cfi_restore_state + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 919 .loc 1 564 5 is_stmt 1 view .LVU307 + 920 04dc 094A ldr r2, .L90 + 921 04de 1368 ldr r3, [r2] + 922 04e0 23F08053 bic r3, r3, #268435456 + 923 04e4 1360 str r3, [r2] + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 924 .loc 1 567 5 view .LVU308 + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 925 .loc 1 567 17 is_stmt 0 view .LVU309 + 926 04e6 FFF7FEFF bl HAL_GetTick + ARM GAS /tmp/ccgN7hfx.s page 30 + + + 927 .LVL59: + 928 04ea 0546 mov r5, r0 + 929 .LVL60: + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 930 .loc 1 570 5 is_stmt 1 view .LVU310 + 931 .L50: + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 932 .loc 1 570 39 view .LVU311 + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 933 .loc 1 570 11 is_stmt 0 view .LVU312 + 934 04ec 054B ldr r3, .L90 + 935 04ee 1B68 ldr r3, [r3] + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 936 .loc 1 570 39 view .LVU313 + 937 04f0 13F0005F tst r3, #536870912 + 938 04f4 0CD0 beq .L84 + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 939 .loc 1 572 7 is_stmt 1 view .LVU314 + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 940 .loc 1 572 11 is_stmt 0 view .LVU315 + 941 04f6 FFF7FEFF bl HAL_GetTick + 942 .LVL61: + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 943 .loc 1 572 25 discriminator 1 view .LVU316 + 944 04fa 401B subs r0, r0, r5 + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 945 .loc 1 572 9 discriminator 1 view .LVU317 + 946 04fc 6428 cmp r0, #100 + 947 04fe F5D9 bls .L50 + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 948 .loc 1 575 16 view .LVU318 + 949 0500 0320 movs r0, #3 + 950 0502 E9E7 b .L10 + 951 .L91: + 952 .align 2 + 953 .L90: + 954 0504 00380240 .word 1073887232 + 955 0508 00700040 .word 1073770496 + 956 050c FFFCFF0F .word 268434687 + 957 .L84: + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 958 .loc 1 580 5 is_stmt 1 view .LVU319 + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe + 959 .loc 1 583 5 view .LVU320 + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe + 960 .loc 1 583 25 is_stmt 0 view .LVU321 + 961 0510 2368 ldr r3, [r4] + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe + 962 .loc 1 583 7 view .LVU322 + 963 0512 13F4002F tst r3, #524288 + 964 0516 01D0 beq .L52 + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe + 965 .loc 1 583 111 discriminator 1 view .LVU323 + 966 0518 E26B ldr r2, [r4, #60] + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe + 967 .loc 1 583 94 discriminator 1 view .LVU324 + 968 051a 22B1 cbz r2, .L53 + ARM GAS /tmp/ccgN7hfx.s page 31 + + + 969 .L52: + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe + 970 .loc 1 583 162 discriminator 3 view .LVU325 + 971 051c 13F4801F tst r3, #1048576 + 972 0520 1DD0 beq .L54 + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 973 .loc 1 584 111 view .LVU326 + 974 0522 236C ldr r3, [r4, #64] + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 975 .loc 1 584 94 view .LVU327 + 976 0524 DBB9 cbnz r3, .L54 + 977 .L53: + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* check for PLLSAI/DIVQ Parameter */ + 978 .loc 1 587 7 is_stmt 1 view .LVU328 + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 979 .loc 1 589 7 view .LVU329 + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + 980 .loc 1 592 7 view .LVU330 + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + 981 .loc 1 592 22 is_stmt 0 view .LVU331 + 982 0526 354A ldr r2, .L92 + 983 0528 D2F88830 ldr r3, [r2, #136] + 984 .LVL62: + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + 985 .loc 1 593 7 is_stmt 1 view .LVU332 + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + 986 .loc 1 593 22 is_stmt 0 view .LVU333 + 987 052c D2F88810 ldr r1, [r2, #136] + 988 .LVL63: + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 989 .loc 1 597 7 is_stmt 1 view .LVU334 + 990 0530 6069 ldr r0, [r4, #20] + 991 0532 03F44033 and r3, r3, #196608 + 992 .LVL64: + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 993 .loc 1 597 7 is_stmt 0 view .LVU335 + 994 0536 43EA8013 orr r3, r3, r0, lsl #6 + 995 053a A069 ldr r0, [r4, #24] + 996 053c 43EA0063 orr r3, r3, r0, lsl #24 + 997 0540 01F0E041 and r1, r1, #1879048192 + 998 .LVL65: + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 999 .loc 1 597 7 view .LVU336 + 1000 0544 0B43 orrs r3, r3, r1 + 1001 0546 C2F88830 str r3, [r2, #136] + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1002 .loc 1 600 7 is_stmt 1 view .LVU337 + 1003 054a D2F88C30 ldr r3, [r2, #140] + 1004 054e 23F4F853 bic r3, r3, #7936 + 1005 0552 A16A ldr r1, [r4, #40] + 1006 0554 0139 subs r1, r1, #1 + 1007 0556 43EA0123 orr r3, r3, r1, lsl #8 + 1008 055a C2F88C30 str r3, [r2, #140] + 1009 .LVL66: + 1010 .L54: + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1011 .loc 1 605 5 view .LVU338 + ARM GAS /tmp/ccgN7hfx.s page 32 + + + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1012 .loc 1 605 24 is_stmt 0 view .LVU339 + 1013 055e 2368 ldr r3, [r4] + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1014 .loc 1 605 7 view .LVU340 + 1015 0560 13F4001F tst r3, #2097152 + 1016 0564 03D0 beq .L55 + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1017 .loc 1 605 112 discriminator 1 view .LVU341 + 1018 0566 E36F ldr r3, [r4, #124] + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1019 .loc 1 605 95 discriminator 1 view .LVU342 + 1020 0568 B3F1006F cmp r3, #134217728 + 1021 056c 31D0 beq .L85 + 1022 .LVL67: + 1023 .L55: + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1024 .loc 1 621 5 is_stmt 1 view .LVU343 + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1025 .loc 1 621 23 is_stmt 0 view .LVU344 + 1026 056e 2368 ldr r3, [r4] + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1027 .loc 1 621 7 view .LVU345 + 1028 0570 13F0080F tst r3, #8 + 1029 0574 19D0 beq .L56 + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); + 1030 .loc 1 623 7 is_stmt 1 view .LVU346 + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1031 .loc 1 624 7 view .LVU347 + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + 1032 .loc 1 627 7 view .LVU348 + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + 1033 .loc 1 627 22 is_stmt 0 view .LVU349 + 1034 0576 214A ldr r2, .L92 + 1035 0578 D2F88810 ldr r1, [r2, #136] + 1036 .LVL68: + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1037 .loc 1 628 7 is_stmt 1 view .LVU350 + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1038 .loc 1 628 22 is_stmt 0 view .LVU351 + 1039 057c D2F88830 ldr r3, [r2, #136] + 1040 .LVL69: + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1041 .loc 1 633 7 is_stmt 1 view .LVU352 + 1042 0580 6069 ldr r0, [r4, #20] + 1043 0582 03F44033 and r3, r3, #196608 + 1044 .LVL70: + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1045 .loc 1 633 7 is_stmt 0 view .LVU353 + 1046 0586 43EA8013 orr r3, r3, r0, lsl #6 + 1047 058a 01F07061 and r1, r1, #251658240 + 1048 .LVL71: + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1049 .loc 1 633 7 view .LVU354 + 1050 058e 0B43 orrs r3, r3, r1 + 1051 0590 E169 ldr r1, [r4, #28] + 1052 0592 43EA0173 orr r3, r3, r1, lsl #28 + ARM GAS /tmp/ccgN7hfx.s page 33 + + + 1053 0596 C2F88830 str r3, [r2, #136] + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1054 .loc 1 636 7 is_stmt 1 view .LVU355 + 1055 059a D2F88C30 ldr r3, [r2, #140] + 1056 059e 23F44033 bic r3, r3, #196608 + 1057 05a2 E16A ldr r1, [r4, #44] + 1058 05a4 0B43 orrs r3, r3, r1 + 1059 05a6 C2F88C30 str r3, [r2, #140] + 1060 .LVL72: + 1061 .L56: + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1062 .loc 1 641 5 view .LVU356 + 1063 05aa 144A ldr r2, .L92 + 1064 05ac 1368 ldr r3, [r2] + 1065 05ae 43F08053 orr r3, r3, #268435456 + 1066 05b2 1360 str r3, [r2] + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1067 .loc 1 644 5 view .LVU357 + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1068 .loc 1 644 17 is_stmt 0 view .LVU358 + 1069 05b4 FFF7FEFF bl HAL_GetTick + 1070 .LVL73: + 1071 05b8 0446 mov r4, r0 + 1072 .LVL74: + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1073 .loc 1 647 5 is_stmt 1 view .LVU359 + 1074 .L57: + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1075 .loc 1 647 39 view .LVU360 + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1076 .loc 1 647 11 is_stmt 0 view .LVU361 + 1077 05ba 104B ldr r3, .L92 + 1078 05bc 1B68 ldr r3, [r3] + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1079 .loc 1 647 39 view .LVU362 + 1080 05be 13F0005F tst r3, #536870912 + 1081 05c2 19D1 bne .L86 + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1082 .loc 1 649 7 is_stmt 1 view .LVU363 + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1083 .loc 1 649 11 is_stmt 0 view .LVU364 + 1084 05c4 FFF7FEFF bl HAL_GetTick + 1085 .LVL75: + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1086 .loc 1 649 25 discriminator 1 view .LVU365 + 1087 05c8 001B subs r0, r0, r4 + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1088 .loc 1 649 9 discriminator 1 view .LVU366 + 1089 05ca 6428 cmp r0, #100 + 1090 05cc F5D9 bls .L57 + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1091 .loc 1 652 16 view .LVU367 + 1092 05ce 0320 movs r0, #3 + 1093 05d0 82E7 b .L10 + 1094 .LVL76: + 1095 .L85: + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 + ARM GAS /tmp/ccgN7hfx.s page 34 + + + 1096 .loc 1 608 7 is_stmt 1 view .LVU368 + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + 1097 .loc 1 610 7 view .LVU369 + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + 1098 .loc 1 610 22 is_stmt 0 view .LVU370 + 1099 05d2 0A4A ldr r2, .L92 + 1100 05d4 D2F88800 ldr r0, [r2, #136] + 1101 .LVL77: + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1102 .loc 1 611 7 is_stmt 1 view .LVU371 + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1103 .loc 1 611 22 is_stmt 0 view .LVU372 + 1104 05d8 D2F88810 ldr r1, [r2, #136] + 1105 .LVL78: + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1106 .loc 1 616 7 is_stmt 1 view .LVU373 + 1107 05dc 6569 ldr r5, [r4, #20] + 1108 .LVL79: + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1109 .loc 1 616 7 is_stmt 0 view .LVU374 + 1110 05de 236A ldr r3, [r4, #32] + 1111 05e0 1B04 lsls r3, r3, #16 + 1112 05e2 43EA8513 orr r3, r3, r5, lsl #6 + 1113 05e6 00F07060 and r0, r0, #251658240 + 1114 .LVL80: + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1115 .loc 1 616 7 view .LVU375 + 1116 05ea 0343 orrs r3, r3, r0 + 1117 05ec 01F0E041 and r1, r1, #1879048192 + 1118 .LVL81: + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1119 .loc 1 616 7 view .LVU376 + 1120 05f0 0B43 orrs r3, r3, r1 + 1121 05f2 C2F88830 str r3, [r2, #136] + 1122 05f6 BAE7 b .L55 + 1123 .LVL82: + 1124 .L86: + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1125 .loc 1 656 10 view .LVU377 + 1126 05f8 0020 movs r0, #0 + 1127 05fa 6DE7 b .L10 + 1128 .L93: + 1129 .align 2 + 1130 .L92: + 1131 05fc 00380240 .word 1073887232 + 1132 .cfi_endproc + 1133 .LFE141: + 1135 .section .text.HAL_RCCEx_GetPeriphCLKConfig,"ax",%progbits + 1136 .align 1 + 1137 .global HAL_RCCEx_GetPeriphCLKConfig + 1138 .syntax unified + 1139 .thumb + 1140 .thumb_func + 1142 HAL_RCCEx_GetPeriphCLKConfig: + 1143 .LVL83: + 1144 .LFB142: + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccgN7hfx.s page 35 + + + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * RCC configuration registers. + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @param PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @retval None + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) + 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1145 .loc 1 666 1 is_stmt 1 view -0 + 1146 .cfi_startproc + 1147 @ args = 0, pretend = 0, frame = 0 + 1148 @ frame_needed = 0, uses_anonymous_args = 0 + 1149 @ link register save eliminated. + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t tempreg = 0; + 1150 .loc 1 667 3 view .LVU379 + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Set all possible values for the extended clock type parameter------------*/ + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ + 1151 .loc 1 671 3 view .LVU380 + 1152 .loc 1 671 39 is_stmt 0 view .LVU381 + 1153 0000 5F4B ldr r3, .L97 + 1154 0002 0360 str r3, [r0] + 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\ + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2 |\ + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1_AUDIO; + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #else + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\ + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_CLK48; + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the PLLI2S Clock configuration -----------------------------------------------*/ + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI + 1155 .loc 1 698 3 is_stmt 1 view .LVU382 + 1156 .loc 1 698 50 is_stmt 0 view .LVU383 + 1157 0004 5F4B ldr r3, .L97+4 + 1158 0006 D3F88420 ldr r2, [r3, #132] + 1159 .loc 1 698 35 view .LVU384 + 1160 000a C2F38812 ubfx r2, r2, #6, #9 + 1161 .loc 1 698 33 view .LVU385 + ARM GAS /tmp/ccgN7hfx.s page 36 + + + 1162 000e 4260 str r2, [r0, #4] + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI + 1163 .loc 1 699 3 is_stmt 1 view .LVU386 + 1164 .loc 1 699 50 is_stmt 0 view .LVU387 + 1165 0010 D3F88420 ldr r2, [r3, #132] + 1166 .loc 1 699 35 view .LVU388 + 1167 0014 C2F30142 ubfx r2, r2, #16, #2 + 1168 .loc 1 699 33 view .LVU389 + 1169 0018 0261 str r2, [r0, #16] + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI + 1170 .loc 1 700 3 is_stmt 1 view .LVU390 + 1171 .loc 1 700 50 is_stmt 0 view .LVU391 + 1172 001a D3F88420 ldr r2, [r3, #132] + 1173 .loc 1 700 35 view .LVU392 + 1174 001e C2F30362 ubfx r2, r2, #24, #4 + 1175 .loc 1 700 33 view .LVU393 + 1176 0022 C260 str r2, [r0, #12] + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI + 1177 .loc 1 701 3 is_stmt 1 view .LVU394 + 1178 .loc 1 701 50 is_stmt 0 view .LVU395 + 1179 0024 D3F88420 ldr r2, [r3, #132] + 1180 .loc 1 701 35 view .LVU396 + 1181 0028 C2F30272 ubfx r2, r2, #28, #3 + 1182 .loc 1 701 33 view .LVU397 + 1183 002c 8260 str r2, [r0, #8] + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the PLLSAI Clock configuration -----------------------------------------------*/ + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLS + 1184 .loc 1 704 3 is_stmt 1 view .LVU398 + 1185 .loc 1 704 50 is_stmt 0 view .LVU399 + 1186 002e D3F88820 ldr r2, [r3, #136] + 1187 .loc 1 704 35 view .LVU400 + 1188 0032 C2F38812 ubfx r2, r2, #6, #9 + 1189 .loc 1 704 33 view .LVU401 + 1190 0036 4261 str r2, [r0, #20] + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLS + 1191 .loc 1 705 3 is_stmt 1 view .LVU402 + 1192 .loc 1 705 50 is_stmt 0 view .LVU403 + 1193 0038 D3F88820 ldr r2, [r3, #136] + 1194 .loc 1 705 35 view .LVU404 + 1195 003c C2F30142 ubfx r2, r2, #16, #2 + 1196 .loc 1 705 33 view .LVU405 + 1197 0040 0262 str r2, [r0, #32] + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLS + 1198 .loc 1 706 3 is_stmt 1 view .LVU406 + 1199 .loc 1 706 50 is_stmt 0 view .LVU407 + 1200 0042 D3F88820 ldr r2, [r3, #136] + 1201 .loc 1 706 35 view .LVU408 + 1202 0046 C2F30362 ubfx r2, r2, #24, #4 + 1203 .loc 1 706 33 view .LVU409 + 1204 004a 8261 str r2, [r0, #24] + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLS + 1205 .loc 1 707 3 is_stmt 1 view .LVU410 + 1206 .loc 1 707 50 is_stmt 0 view .LVU411 + 1207 004c D3F88820 ldr r2, [r3, #136] + 1208 .loc 1 707 35 view .LVU412 + 1209 0050 C2F30272 ubfx r2, r2, #28, #3 + ARM GAS /tmp/ccgN7hfx.s page 37 + + + 1210 .loc 1 707 33 view .LVU413 + 1211 0054 C261 str r2, [r0, #28] + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/ + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_ + 1212 .loc 1 710 3 is_stmt 1 view .LVU414 + 1213 .loc 1 710 46 is_stmt 0 view .LVU415 + 1214 0056 D3F88C20 ldr r2, [r3, #140] + 1215 .loc 1 710 31 view .LVU416 + 1216 005a 02F01F02 and r2, r2, #31 + 1217 .loc 1 710 29 view .LVU417 + 1218 005e 4262 str r2, [r0, #36] + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_ + 1219 .loc 1 711 3 is_stmt 1 view .LVU418 + 1220 .loc 1 711 46 is_stmt 0 view .LVU419 + 1221 0060 D3F88C20 ldr r2, [r3, #140] + 1222 .loc 1 711 31 view .LVU420 + 1223 0064 C2F30422 ubfx r2, r2, #8, #5 + 1224 .loc 1 711 29 view .LVU421 + 1225 0068 8262 str r2, [r0, #40] + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> RCC_DCKCFGR1_ + 1226 .loc 1 712 3 is_stmt 1 view .LVU422 + 1227 .loc 1 712 46 is_stmt 0 view .LVU423 + 1228 006a D3F88C20 ldr r2, [r3, #140] + 1229 .loc 1 712 31 view .LVU424 + 1230 006e C2F30142 ubfx r2, r2, #16, #2 + 1231 .loc 1 712 29 view .LVU425 + 1232 0072 C262 str r2, [r0, #44] + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the SAI1 clock configuration ----------------------------------------------*/ + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); + 1233 .loc 1 715 3 is_stmt 1 view .LVU426 + 1234 .loc 1 715 39 is_stmt 0 view .LVU427 + 1235 0074 D3F88C20 ldr r2, [r3, #140] + 1236 0078 02F44012 and r2, r2, #3145728 + 1237 .loc 1 715 37 view .LVU428 + 1238 007c C263 str r2, [r0, #60] + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the SAI2 clock configuration ----------------------------------------------*/ + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); + 1239 .loc 1 718 3 is_stmt 1 view .LVU429 + 1240 .loc 1 718 39 is_stmt 0 view .LVU430 + 1241 007e D3F88C20 ldr r2, [r3, #140] + 1242 0082 02F44002 and r2, r2, #12582912 + 1243 .loc 1 718 37 view .LVU431 + 1244 0086 0264 str r2, [r0, #64] + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the I2S clock configuration ------------------------------------------*/ + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE(); + 1245 .loc 1 721 3 is_stmt 1 view .LVU432 + 1246 .loc 1 721 38 is_stmt 0 view .LVU433 + 1247 0088 9A68 ldr r2, [r3, #8] + 1248 008a 02F40002 and r2, r2, #8388608 + 1249 .loc 1 721 36 view .LVU434 + 1250 008e 4263 str r2, [r0, #52] + 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the I2C1 clock configuration ------------------------------------------*/ + ARM GAS /tmp/ccgN7hfx.s page 38 + + + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + 1251 .loc 1 724 3 is_stmt 1 view .LVU435 + 1252 .loc 1 724 39 is_stmt 0 view .LVU436 + 1253 0090 D3F89020 ldr r2, [r3, #144] + 1254 0094 02F44032 and r2, r2, #196608 + 1255 .loc 1 724 37 view .LVU437 + 1256 0098 4266 str r2, [r0, #100] + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the I2C2 clock configuration ------------------------------------------*/ + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); + 1257 .loc 1 727 3 is_stmt 1 view .LVU438 + 1258 .loc 1 727 39 is_stmt 0 view .LVU439 + 1259 009a D3F89020 ldr r2, [r3, #144] + 1260 009e 02F44022 and r2, r2, #786432 + 1261 .loc 1 727 37 view .LVU440 + 1262 00a2 8266 str r2, [r0, #104] + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the I2C3 clock configuration ------------------------------------------*/ + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); + 1263 .loc 1 730 3 is_stmt 1 view .LVU441 + 1264 .loc 1 730 39 is_stmt 0 view .LVU442 + 1265 00a4 D3F89020 ldr r2, [r3, #144] + 1266 00a8 02F44012 and r2, r2, #3145728 + 1267 .loc 1 730 37 view .LVU443 + 1268 00ac C266 str r2, [r0, #108] + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the I2C4 clock configuration ------------------------------------------*/ + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); + 1269 .loc 1 733 3 is_stmt 1 view .LVU444 + 1270 .loc 1 733 39 is_stmt 0 view .LVU445 + 1271 00ae D3F89020 ldr r2, [r3, #144] + 1272 00b2 02F44002 and r2, r2, #12582912 + 1273 .loc 1 733 37 view .LVU446 + 1274 00b6 0267 str r2, [r0, #112] + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the USART1 clock configuration ------------------------------------------*/ + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + 1275 .loc 1 736 3 is_stmt 1 view .LVU447 + 1276 .loc 1 736 41 is_stmt 0 view .LVU448 + 1277 00b8 D3F89020 ldr r2, [r3, #144] + 1278 00bc 02F00302 and r2, r2, #3 + 1279 .loc 1 736 39 view .LVU449 + 1280 00c0 4264 str r2, [r0, #68] + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the USART2 clock configuration ------------------------------------------*/ + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); + 1281 .loc 1 739 3 is_stmt 1 view .LVU450 + 1282 .loc 1 739 41 is_stmt 0 view .LVU451 + 1283 00c2 D3F89020 ldr r2, [r3, #144] + 1284 00c6 02F00C02 and r2, r2, #12 + 1285 .loc 1 739 39 view .LVU452 + 1286 00ca 8264 str r2, [r0, #72] + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the USART3 clock configuration ------------------------------------------*/ + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); + 1287 .loc 1 742 3 is_stmt 1 view .LVU453 + 1288 .loc 1 742 41 is_stmt 0 view .LVU454 + ARM GAS /tmp/ccgN7hfx.s page 39 + + + 1289 00cc D3F89020 ldr r2, [r3, #144] + 1290 00d0 02F03002 and r2, r2, #48 + 1291 .loc 1 742 39 view .LVU455 + 1292 00d4 C264 str r2, [r0, #76] + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the UART4 clock configuration ------------------------------------------*/ + 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); + 1293 .loc 1 745 3 is_stmt 1 view .LVU456 + 1294 .loc 1 745 40 is_stmt 0 view .LVU457 + 1295 00d6 D3F89020 ldr r2, [r3, #144] + 1296 00da 02F0C002 and r2, r2, #192 + 1297 .loc 1 745 38 view .LVU458 + 1298 00de 0265 str r2, [r0, #80] + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the UART5 clock configuration ------------------------------------------*/ + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); + 1299 .loc 1 748 3 is_stmt 1 view .LVU459 + 1300 .loc 1 748 40 is_stmt 0 view .LVU460 + 1301 00e0 D3F89020 ldr r2, [r3, #144] + 1302 00e4 02F44072 and r2, r2, #768 + 1303 .loc 1 748 38 view .LVU461 + 1304 00e8 4265 str r2, [r0, #84] + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the USART6 clock configuration ------------------------------------------*/ + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); + 1305 .loc 1 751 3 is_stmt 1 view .LVU462 + 1306 .loc 1 751 41 is_stmt 0 view .LVU463 + 1307 00ea D3F89020 ldr r2, [r3, #144] + 1308 00ee 02F44062 and r2, r2, #3072 + 1309 .loc 1 751 39 view .LVU464 + 1310 00f2 8265 str r2, [r0, #88] + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the UART7 clock configuration ------------------------------------------*/ + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); + 1311 .loc 1 754 3 is_stmt 1 view .LVU465 + 1312 .loc 1 754 40 is_stmt 0 view .LVU466 + 1313 00f4 D3F89020 ldr r2, [r3, #144] + 1314 00f8 02F44052 and r2, r2, #12288 + 1315 .loc 1 754 38 view .LVU467 + 1316 00fc C265 str r2, [r0, #92] + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the UART8 clock configuration ------------------------------------------*/ + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); + 1317 .loc 1 757 3 is_stmt 1 view .LVU468 + 1318 .loc 1 757 40 is_stmt 0 view .LVU469 + 1319 00fe D3F89020 ldr r2, [r3, #144] + 1320 0102 02F44042 and r2, r2, #49152 + 1321 .loc 1 757 38 view .LVU470 + 1322 0106 0266 str r2, [r0, #96] + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the LPTIM1 clock configuration ------------------------------------------*/ + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + 1323 .loc 1 760 3 is_stmt 1 view .LVU471 + 1324 .loc 1 760 41 is_stmt 0 view .LVU472 + 1325 0108 D3F89020 ldr r2, [r3, #144] + 1326 010c 02F04072 and r2, r2, #50331648 + 1327 .loc 1 760 39 view .LVU473 + ARM GAS /tmp/ccgN7hfx.s page 40 + + + 1328 0110 4267 str r2, [r0, #116] + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the CEC clock configuration -----------------------------------------------*/ + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); + 1329 .loc 1 763 3 is_stmt 1 view .LVU474 + 1330 .loc 1 763 38 is_stmt 0 view .LVU475 + 1331 0112 D3F89020 ldr r2, [r3, #144] + 1332 0116 02F08062 and r2, r2, #67108864 + 1333 .loc 1 763 36 view .LVU476 + 1334 011a 8267 str r2, [r0, #120] + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the CK48 clock configuration -----------------------------------------------*/ + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + 1335 .loc 1 766 3 is_stmt 1 view .LVU477 + 1336 .loc 1 766 40 is_stmt 0 view .LVU478 + 1337 011c D3F89020 ldr r2, [r3, #144] + 1338 0120 02F00062 and r2, r2, #134217728 + 1339 .loc 1 766 38 view .LVU479 + 1340 0124 C267 str r2, [r0, #124] + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the SDMMC1 clock configuration -----------------------------------------------*/ + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); + 1341 .loc 1 769 3 is_stmt 1 view .LVU480 + 1342 .loc 1 769 41 is_stmt 0 view .LVU481 + 1343 0126 D3F89020 ldr r2, [r3, #144] + 1344 012a 02F08052 and r2, r2, #268435456 + 1345 .loc 1 769 39 view .LVU482 + 1346 012e C0F88020 str r2, [r0, #128] + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the SDMMC2 clock configuration -----------------------------------------------*/ + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); + 1347 .loc 1 773 3 is_stmt 1 view .LVU483 + 1348 .loc 1 773 41 is_stmt 0 view .LVU484 + 1349 0132 D3F89020 ldr r2, [r3, #144] + 1350 0136 02F00052 and r2, r2, #536870912 + 1351 .loc 1 773 39 view .LVU485 + 1352 013a C0F88420 str r2, [r0, #132] + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the DFSDM clock configuration -----------------------------------------------*/ + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); + 1353 .loc 1 776 3 is_stmt 1 view .LVU486 + 1354 .loc 1 776 41 is_stmt 0 view .LVU487 + 1355 013e D3F88C20 ldr r2, [r3, #140] + 1356 0142 02F00072 and r2, r2, #33554432 + 1357 .loc 1 776 39 view .LVU488 + 1358 0146 C0F88820 str r2, [r0, #136] + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/ + 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); + 1359 .loc 1 779 3 is_stmt 1 view .LVU489 + 1360 .loc 1 779 46 is_stmt 0 view .LVU490 + 1361 014a D3F88C20 ldr r2, [r3, #140] + 1362 014e 02F08062 and r2, r2, #67108864 + 1363 .loc 1 779 44 view .LVU491 + 1364 0152 C0F88C20 str r2, [r0, #140] + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + ARM GAS /tmp/ccgN7hfx.s page 41 + + + 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the RTC Clock configuration -----------------------------------------------*/ + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + 1365 .loc 1 783 3 is_stmt 1 view .LVU492 + 1366 .loc 1 783 17 is_stmt 0 view .LVU493 + 1367 0156 9968 ldr r1, [r3, #8] + 1368 .loc 1 783 11 view .LVU494 + 1369 0158 01F4F811 and r1, r1, #2031616 + 1370 .LVL84: + 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + 1371 .loc 1 784 3 is_stmt 1 view .LVU495 + 1372 .loc 1 784 65 is_stmt 0 view .LVU496 + 1373 015c 1A6F ldr r2, [r3, #112] + 1374 .loc 1 784 72 view .LVU497 + 1375 015e 02F44072 and r2, r2, #768 + 1376 .loc 1 784 38 view .LVU498 + 1377 0162 0A43 orrs r2, r2, r1 + 1378 .loc 1 784 36 view .LVU499 + 1379 0164 0263 str r2, [r0, #48] + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the TIM Prescaler configuration --------------------------------------------*/ + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET) + 1380 .loc 1 787 3 is_stmt 1 view .LVU500 + 1381 .loc 1 787 11 is_stmt 0 view .LVU501 + 1382 0166 D3F88C30 ldr r3, [r3, #140] + 1383 .loc 1 787 6 view .LVU502 + 1384 016a 13F0807F tst r3, #16777216 + 1385 016e 02D1 bne .L95 + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + 1386 .loc 1 789 5 is_stmt 1 view .LVU503 + 1387 .loc 1 789 37 is_stmt 0 view .LVU504 + 1388 0170 0023 movs r3, #0 + 1389 0172 8363 str r3, [r0, #56] + 1390 0174 7047 bx lr + 1391 .L95: + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** else + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + 1392 .loc 1 793 5 is_stmt 1 view .LVU505 + 1393 .loc 1 793 37 is_stmt 0 view .LVU506 + 1394 0176 4FF08073 mov r3, #16777216 + 1395 017a 8363 str r3, [r0, #56] + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1396 .loc 1 795 1 view .LVU507 + 1397 017c 7047 bx lr + 1398 .L98: + 1399 017e 00BF .align 2 + 1400 .L97: + 1401 0180 F1FFFF1C .word 486539249 + 1402 0184 00380240 .word 1073887232 + 1403 .cfi_endproc + 1404 .LFE142: + 1406 .section .text.HAL_RCCEx_GetPeriphCLKFreq,"ax",%progbits + 1407 .align 1 + ARM GAS /tmp/ccgN7hfx.s page 42 + + + 1408 .global HAL_RCCEx_GetPeriphCLKFreq + 1409 .syntax unified + 1410 .thumb + 1411 .thumb_func + 1413 HAL_RCCEx_GetPeriphCLKFreq: + 1414 .LVL85: + 1415 .LFB143: + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @brief Initializes the RCC extended peripherals clocks according to the specified + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * parameters in the RCC_PeriphCLKInitTypeDef. + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * contains the configuration information for the Extended Peripherals + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * clocks(I2S, SAI, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). + 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * + 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * the RTC clock source; in this case the Backup domain will be reset in + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * order to modify the RTC Clock source, as consequence RTC registers (including + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * the backup registers) are set to their reset values. + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @retval HAL status + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t tickstart = 0; + 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t tmpreg0 = 0; + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t plli2sused = 0; + 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t pllsaiused = 0; + 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*----------------------------------- I2S configuration ----------------------------------*/ + 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure I2S Clock source */ + 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable the PLLI2S when it's used as clock source for I2S */ + 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** plli2sused = 1; + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*------------------------------------ SAI1 configuration --------------------------------------* + 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure SAI1 Clock source */ + ARM GAS /tmp/ccgN7hfx.s page 43 + + + 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable the PLLI2S when it's used as clock source for SAI */ + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) + 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** plli2sused = 1; + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable the PLLSAI when it's used as clock source for SAI */ + 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** pllsaiused = 1; + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*------------------------------------ SAI2 configuration --------------------------------------* + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure SAI2 Clock source */ + 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); + 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable the PLLI2S when it's used as clock source for SAI */ + 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) + 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** plli2sused = 1; + 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable the PLLSAI when it's used as clock source for SAI */ + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** pllsaiused = 1; + 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*------------------------------------ RTC configuration --------------------------------------*/ + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check for RTC Parameters used to output RTCCLK */ + 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable Power Clock*/ + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable write access to Backup domain */ + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PWR->CR1 |= PWR_CR1_DBP; + 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get Start Tick*/ + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait for Backup domain Write protection disable */ + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while((PWR->CR1 & PWR_CR1_DBP) == RESET) + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccgN7hfx.s page 44 + + + 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Reset the Backup domain only if the RTC Clock source selection is modified */ + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL) + 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Store the content of BDCR register before the reset of Backup Domain */ + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* RTC Clock selection can be changed only if the Backup Domain is reset */ + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_FORCE(); + 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_RELEASE(); + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Restore the Content of BDCR register */ + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC->BDCR = tmpreg0; + 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get Start Tick*/ + 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait till LSE is ready */ + 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*------------------------------------ TIM configuration --------------------------------------*/ + 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure Timer Prescaler */ + 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- I2C1 Configuration -----------------------------------*/ + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the I2C1 clock source */ + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- I2C2 Configuration -----------------------------------*/ + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + ARM GAS /tmp/ccgN7hfx.s page 45 + + + 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the I2C2 clock source */ + 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- I2C3 Configuration -----------------------------------*/ + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the I2C3 clock source */ + 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- USART1 Configuration ----------------------------------- + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the USART1 clock source */ + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- USART2 Configuration ----------------------------------- + 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the USART2 clock source */ + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- USART3 Configuration ----------------------------------- + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ +1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the USART3 clock source */ +1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); +1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- UART4 Configuration -----------------------------------* +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) +1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); +1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the UART4 clock source */ +1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); +1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccgN7hfx.s page 46 + + +1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- UART5 Configuration -----------------------------------* +1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ +1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the UART5 clock source */ +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); +1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- USART6 Configuration ----------------------------------- +1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); +1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the USART6 clock source */ +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); +1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- UART7 Configuration -----------------------------------* +1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ +1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); +1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the UART7 clock source */ +1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); +1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- UART8 Configuration -----------------------------------* +1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) +1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ +1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the UART8 clock source */ +1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- CK48 Configuration -----------------------------------*/ +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) +1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ +1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); +1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the CLK48 source */ +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); +1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable the PLLSAI when it's used as clock source for CK48 */ +1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** pllsaiused = 1; +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccgN7hfx.s page 47 + + +1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- LPTIM1 Configuration ----------------------------------- +1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) +1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ +1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); +1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the LTPIM1 clock source */ +1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); +1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*------------------------------------- SDMMC1 Configuration ------------------------------------ +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) +1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ +1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); +1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the SDMMC1 clock source */ +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); +1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*------------------------------------- SDMMC2 Configuration ------------------------------------ +1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) +1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the parameters */ +1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); +1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the SDMMC2 clock source */ +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); +1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ +1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */ +1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERI +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Disable the PLLI2S */ +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLI2S_DISABLE(); +1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get Start Tick*/ +1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait till PLLI2S is disabled */ +1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) +1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* return in case of Timeout detected */ +1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; +1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* check for common PLLI2S Parameters */ +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (Peri +1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* check for Parameters */ + ARM GAS /tmp/ccgN7hfx.s page 48 + + +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); +1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuratio +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the PLLI2S division factors */ +1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ +1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ +1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, PeriphClkInit->PLLI2S.PLLI2S +1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ +1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (Pe +1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe +1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check for PLLI2S Parameters */ +1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); +1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check for PLLI2S/DIVQ parameters */ +1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); +1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI +1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); +1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the PLLI2S division factors */ +1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ +1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg0 +1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ +1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*----------------- In Case of PLLI2S is just selected -----------------*/ +1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check for Parameters */ +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); +1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); +1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the PLLI2S division factors */ +1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ +1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, Periph +1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable the PLLI2S */ +1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLI2S_ENABLE(); +1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get Start Tick*/ +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); +1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait till PLLI2S is ready */ +1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) +1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) +1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* return in case of Timeout detected */ +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; +1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccgN7hfx.s page 49 + + +1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(pllsaiused == 1) +1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Disable PLLSAI Clock */ +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLSAI_DISABLE(); +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get Start Tick*/ +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); +1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait till PLLSAI is disabled */ +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) +1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) +1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* return in case of Timeout detected */ +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; +1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check the PLLSAI division factors */ +1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); +1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ +1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (Pe +1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (Pe +1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* check for PLLSAIQ Parameter */ +1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); +1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* check for PLLSAI/DIVQ Parameter */ +1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuratio +1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); +1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ +1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ +1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ +1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAI +1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ +1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /*----------------- In Case of PLLSAI is selected as source clock for CLK48 ------------------- +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* In Case of PLLI2S is selected as source clock for CK48 */ +1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (P +1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* check for Parameters */ +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); +1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the PLLSAI division factors */ +1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ + ARM GAS /tmp/ccgN7hfx.s page 50 + + +1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ +1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg +1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable PLLSAI Clock */ +1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLSAI_ENABLE(); +1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get Start Tick*/ +1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); +1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait till PLLSAI is ready */ +1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) +1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) +1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* return in case of Timeout detected */ +1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; +1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_OK; +1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** +1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal +1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * RCC configuration registers. +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @param PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure +1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @retval None +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ +1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t tempreg = 0; +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Set all possible values for the extended clock type parameter------------*/ +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ +1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ +1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ +1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ +1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ +1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ +1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ +1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2; +1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the PLLI2S Clock configuration -----------------------------------------------*/ +1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI +1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI +1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI +1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the PLLSAI Clock configuration -----------------------------------------------*/ +1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLS +1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLS +1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLS +1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/ +1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_ + ARM GAS /tmp/ccgN7hfx.s page 51 + + +1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_ +1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the SAI1 clock configuration ----------------------------------------------*/ +1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); +1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the SAI2 clock configuration ----------------------------------------------*/ +1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); +1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the I2S clock configuration ------------------------------------------*/ +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE(); +1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the I2C1 clock configuration ------------------------------------------*/ +1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); +1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the I2C2 clock configuration ------------------------------------------*/ +1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); +1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the I2C3 clock configuration ------------------------------------------*/ +1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); +1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the USART1 clock configuration ------------------------------------------*/ +1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); +1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the USART2 clock configuration ------------------------------------------*/ +1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); +1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the USART3 clock configuration ------------------------------------------*/ +1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); +1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the UART4 clock configuration ------------------------------------------*/ +1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); +1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the UART5 clock configuration ------------------------------------------*/ +1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); +1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the USART6 clock configuration ------------------------------------------*/ +1338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); +1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the UART7 clock configuration ------------------------------------------*/ +1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); +1342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the UART8 clock configuration ------------------------------------------*/ +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); +1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the LPTIM1 clock configuration ------------------------------------------*/ +1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); +1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the CK48 clock configuration -----------------------------------------------*/ +1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); +1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the SDMMC1 clock configuration -----------------------------------------------*/ +1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); +1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the SDMMC2 clock configuration -----------------------------------------------*/ +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); +1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the RTC Clock configuration -----------------------------------------------*/ + ARM GAS /tmp/ccgN7hfx.s page 52 + + +1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); +1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); +1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Get the TIM Prescaler configuration --------------------------------------------*/ +1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET) +1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; +1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** else +1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; +1370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ +1373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** +1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @brief Return the peripheral clock frequency for a given peripheral(SAI..) +1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @note Return 0 if peripheral clock identifier not managed by this API +1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @param PeriphClk Peripheral clock identifier +1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * This parameter can be one of the following values: +1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock +1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock +1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @retval Frequency in KHz +1382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ +1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1416 .loc 1 1384 1 is_stmt 1 view -0 + 1417 .cfi_startproc + 1418 @ args = 0, pretend = 0, frame = 0 + 1419 @ frame_needed = 0, uses_anonymous_args = 0 + 1420 @ link register save eliminated. + 1421 .loc 1 1384 1 is_stmt 0 view .LVU509 + 1422 0000 0346 mov r3, r0 +1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t tmpreg = 0; + 1423 .loc 1 1385 3 is_stmt 1 view .LVU510 + 1424 .LVL86: +1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* This variable is used to store the SAI clock frequency (value in Hz) */ +1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t frequency = 0; + 1425 .loc 1 1387 3 view .LVU511 +1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* This variable is used to store the VCO Input (value in Hz) */ +1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t vcoinput = 0; + 1426 .loc 1 1389 3 view .LVU512 +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* This variable is used to store the SAI clock source */ +1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t saiclocksource = 0; + 1427 .loc 1 1391 3 view .LVU513 +1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if (PeriphClk == RCC_PERIPHCLK_SAI1) + 1428 .loc 1 1393 3 view .LVU514 + 1429 .loc 1 1393 6 is_stmt 0 view .LVU515 + 1430 0002 B0F5002F cmp r0, #524288 + 1431 0006 04D0 beq .L123 +1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* This variable is used to store the VCO Input (value in Hz) */ + 1432 .loc 1 1387 12 view .LVU516 + 1433 0008 0020 movs r0, #0 + 1434 .LVL87: + 1435 .L100: +1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccgN7hfx.s page 53 + + +1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** saiclocksource = RCC->DCKCFGR1; +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** saiclocksource &= RCC_DCKCFGR1_SAI1SEL; +1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** switch (saiclocksource) +1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** case 0: /* PLLSAI is the clock source for SAI1 */ +1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the PLLSAI division factor */ +1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ +1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) +1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* In Case the PLL Source is HSI (Internal Clock) */ +1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); +1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** else +1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* In Case the PLL Source is HSE (External Clock) */ +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); +1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ +1414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; +1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); +1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; +1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */ +1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the PLLI2S division factor */ +1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ +1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) +1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* In Case the PLL Source is HSI (Internal Clock) */ +1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); +1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** else +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* In Case the PLL Source is HSE (External Clock) */ +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); +1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ +1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ +1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); +1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ +1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); +1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); +1446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; +1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */ +1449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = EXTERNAL_CLOCK_VALUE; +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; + ARM GAS /tmp/ccgN7hfx.s page 54 + + +1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx +1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/ +1455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) +1457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* In Case the main PLL Source is HSI */ +1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** else +1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* In Case the main PLL Source is HSE */ +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = HSE_VALUE; +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; +1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** default : +1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; +1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if (PeriphClk == RCC_PERIPHCLK_SAI2) + 1436 .loc 1 1476 3 is_stmt 1 view .LVU517 + 1437 .loc 1 1476 6 is_stmt 0 view .LVU518 + 1438 000a B3F5801F cmp r3, #1048576 + 1439 000e 71D0 beq .L124 + 1440 .LVL88: + 1441 .L99: +1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** saiclocksource = RCC->DCKCFGR1; +1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** saiclocksource &= RCC_DCKCFGR1_SAI2SEL; +1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** switch (saiclocksource) +1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** case 0: /* PLLSAI is the clock source for SAI*/ +1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the PLLSAI division factor */ +1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) +1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* In Case the PLL Source is HSI (Internal Clock) */ +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); +1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** else +1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* In Case the PLL Source is HSE (External Clock) */ +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); +1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ +1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ +1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); +1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ +1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); + ARM GAS /tmp/ccgN7hfx.s page 55 + + +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); +1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; +1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */ +1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the PLLI2S division factor */ +1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ +1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) +1511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* In Case the PLL Source is HSI (Internal Clock) */ +1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); +1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** else +1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* In Case the PLL Source is HSE (External Clock) */ +1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); +1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ +1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ +1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); +1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); +1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); +1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */ +1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = EXTERNAL_CLOCK_VALUE; +1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; +1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx +1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */ +1538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) +1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* In Case the main PLL Source is HSI */ +1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** else +1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* In Case the main PLL Source is HSE */ +1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = HSE_VALUE; +1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +1552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** default : +1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; +1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return frequency; + ARM GAS /tmp/ccgN7hfx.s page 56 + + +1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1442 .loc 1 1560 1 view .LVU519 + 1443 0010 7047 bx lr + 1444 .LVL89: + 1445 .L123: +1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** saiclocksource &= RCC_DCKCFGR1_SAI1SEL; + 1446 .loc 1 1395 5 is_stmt 1 view .LVU520 +1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** saiclocksource &= RCC_DCKCFGR1_SAI1SEL; + 1447 .loc 1 1395 20 is_stmt 0 view .LVU521 + 1448 0012 704A ldr r2, .L129 + 1449 0014 D2F88C20 ldr r2, [r2, #140] + 1450 .LVL90: +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** switch (saiclocksource) + 1451 .loc 1 1396 5 is_stmt 1 view .LVU522 +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** switch (saiclocksource) + 1452 .loc 1 1396 20 is_stmt 0 view .LVU523 + 1453 0018 02F44012 and r2, r2, #3145728 + 1454 .LVL91: +1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1455 .loc 1 1397 5 is_stmt 1 view .LVU524 + 1456 001c B2F5001F cmp r2, #2097152 + 1457 0020 64D0 beq .L119 + 1458 0022 26D8 bhi .L101 + 1459 0024 8AB3 cbz r2, .L102 + 1460 0026 B2F5801F cmp r2, #1048576 + 1461 002a 20D1 bne .L125 +1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1462 .loc 1 1427 9 view .LVU525 +1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1463 .loc 1 1427 16 is_stmt 0 view .LVU526 + 1464 002c 694A ldr r2, .L129 + 1465 .LVL92: +1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1466 .loc 1 1427 16 view .LVU527 + 1467 002e 5268 ldr r2, [r2, #4] +1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1468 .loc 1 1427 11 view .LVU528 + 1469 0030 12F4800F tst r2, #4194304 + 1470 0034 52D1 bne .L107 +1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1471 .loc 1 1430 11 is_stmt 1 view .LVU529 +1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1472 .loc 1 1430 49 is_stmt 0 view .LVU530 + 1473 0036 674A ldr r2, .L129 + 1474 0038 5168 ldr r1, [r2, #4] +1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1475 .loc 1 1430 35 view .LVU531 + 1476 003a 01F03F01 and r1, r1, #63 +1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1477 .loc 1 1430 20 view .LVU532 + 1478 003e 664A ldr r2, .L129+4 + 1479 0040 B2FBF1FC udiv ip, r2, r1 + 1480 .LVL93: + 1481 .L108: +1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); + 1482 .loc 1 1440 9 is_stmt 1 view .LVU533 +1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); + ARM GAS /tmp/ccgN7hfx.s page 57 + + + 1483 .loc 1 1440 22 is_stmt 0 view .LVU534 + 1484 0044 634A ldr r2, .L129 + 1485 0046 D2F88410 ldr r1, [r2, #132] +1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); + 1486 .loc 1 1440 16 view .LVU535 + 1487 004a C1F30361 ubfx r1, r1, #24, #4 + 1488 .LVL94: +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1489 .loc 1 1441 9 is_stmt 1 view .LVU536 +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1490 .loc 1 1441 38 is_stmt 0 view .LVU537 + 1491 004e D2F88400 ldr r0, [r2, #132] + 1492 .LVL95: +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1493 .loc 1 1441 77 view .LVU538 + 1494 0052 C0F38810 ubfx r0, r0, #6, #9 +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1495 .loc 1 1441 31 view .LVU539 + 1496 0056 0CFB00F0 mul r0, ip, r0 +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1497 .loc 1 1441 19 view .LVU540 + 1498 005a B0FBF1F0 udiv r0, r0, r1 + 1499 .LVL96: +1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); + 1500 .loc 1 1444 9 is_stmt 1 view .LVU541 +1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); + 1501 .loc 1 1444 23 is_stmt 0 view .LVU542 + 1502 005e D2F88C20 ldr r2, [r2, #140] +1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); + 1503 .loc 1 1444 34 view .LVU543 + 1504 0062 02F01F02 and r2, r2, #31 +1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); + 1505 .loc 1 1444 16 view .LVU544 + 1506 0066 0132 adds r2, r2, #1 + 1507 .LVL97: +1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; + 1508 .loc 1 1445 9 is_stmt 1 view .LVU545 +1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; + 1509 .loc 1 1445 19 is_stmt 0 view .LVU546 + 1510 0068 B0FBF2F0 udiv r0, r0, r2 + 1511 .LVL98: +1446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1512 .loc 1 1446 9 is_stmt 1 view .LVU547 + 1513 006c CDE7 b .L100 + 1514 .LVL99: + 1515 .L125: +1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1516 .loc 1 1397 5 is_stmt 0 view .LVU548 + 1517 006e 0020 movs r0, #0 + 1518 .LVL100: +1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1519 .loc 1 1397 5 view .LVU549 + 1520 0070 CBE7 b .L100 + 1521 .LVL101: + 1522 .L101: +1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1523 .loc 1 1397 5 view .LVU550 + ARM GAS /tmp/ccgN7hfx.s page 58 + + + 1524 0072 B2F5401F cmp r2, #3145728 + 1525 0076 06D1 bne .L126 +1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1526 .loc 1 1456 9 is_stmt 1 view .LVU551 +1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1527 .loc 1 1456 16 is_stmt 0 view .LVU552 + 1528 0078 564A ldr r2, .L129 + 1529 .LVL102: +1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1530 .loc 1 1456 16 view .LVU553 + 1531 007a 5268 ldr r2, [r2, #4] +1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1532 .loc 1 1456 11 view .LVU554 + 1533 007c 12F4800F tst r2, #4194304 + 1534 0080 36D1 bne .L120 +1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1535 .loc 1 1459 21 view .LVU555 + 1536 0082 5548 ldr r0, .L129+4 + 1537 .LVL103: +1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1538 .loc 1 1459 21 view .LVU556 + 1539 0084 C1E7 b .L100 + 1540 .LVL104: + 1541 .L126: +1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1542 .loc 1 1397 5 view .LVU557 + 1543 0086 0020 movs r0, #0 + 1544 .LVL105: +1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1545 .loc 1 1397 5 view .LVU558 + 1546 0088 BFE7 b .L100 + 1547 .LVL106: + 1548 .L102: +1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1549 .loc 1 1403 9 is_stmt 1 view .LVU559 +1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1550 .loc 1 1403 16 is_stmt 0 view .LVU560 + 1551 008a 524A ldr r2, .L129 + 1552 .LVL107: +1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1553 .loc 1 1403 16 view .LVU561 + 1554 008c 5268 ldr r2, [r2, #4] +1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1555 .loc 1 1403 11 view .LVU562 + 1556 008e 12F4800F tst r2, #4194304 + 1557 0092 1BD1 bne .L105 +1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1558 .loc 1 1406 11 is_stmt 1 view .LVU563 +1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1559 .loc 1 1406 49 is_stmt 0 view .LVU564 + 1560 0094 4F4A ldr r2, .L129 + 1561 0096 5168 ldr r1, [r2, #4] +1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1562 .loc 1 1406 35 view .LVU565 + 1563 0098 01F03F01 and r1, r1, #63 +1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1564 .loc 1 1406 20 view .LVU566 + ARM GAS /tmp/ccgN7hfx.s page 59 + + + 1565 009c 4E4A ldr r2, .L129+4 + 1566 009e B2FBF1FC udiv ip, r2, r1 + 1567 .LVL108: + 1568 .L106: +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); + 1569 .loc 1 1415 9 is_stmt 1 view .LVU567 +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); + 1570 .loc 1 1415 22 is_stmt 0 view .LVU568 + 1571 00a2 4C4A ldr r2, .L129 + 1572 00a4 D2F88810 ldr r1, [r2, #136] +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); + 1573 .loc 1 1415 16 view .LVU569 + 1574 00a8 C1F30361 ubfx r1, r1, #24, #4 + 1575 .LVL109: +1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1576 .loc 1 1416 9 is_stmt 1 view .LVU570 +1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1577 .loc 1 1416 38 is_stmt 0 view .LVU571 + 1578 00ac D2F88800 ldr r0, [r2, #136] + 1579 .LVL110: +1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1580 .loc 1 1416 77 view .LVU572 + 1581 00b0 C0F38810 ubfx r0, r0, #6, #9 +1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1582 .loc 1 1416 31 view .LVU573 + 1583 00b4 0CFB00F0 mul r0, ip, r0 +1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1584 .loc 1 1416 19 view .LVU574 + 1585 00b8 B0FBF1F0 udiv r0, r0, r1 + 1586 .LVL111: +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); + 1587 .loc 1 1419 9 is_stmt 1 view .LVU575 +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); + 1588 .loc 1 1419 24 is_stmt 0 view .LVU576 + 1589 00bc D2F88C20 ldr r2, [r2, #140] +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); + 1590 .loc 1 1419 62 view .LVU577 + 1591 00c0 C2F30422 ubfx r2, r2, #8, #5 +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); + 1592 .loc 1 1419 16 view .LVU578 + 1593 00c4 0132 adds r2, r2, #1 + 1594 .LVL112: +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; + 1595 .loc 1 1420 9 is_stmt 1 view .LVU579 +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; + 1596 .loc 1 1420 19 is_stmt 0 view .LVU580 + 1597 00c6 B0FBF2F0 udiv r0, r0, r2 + 1598 .LVL113: +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1599 .loc 1 1421 9 is_stmt 1 view .LVU581 + 1600 00ca 9EE7 b .L100 + 1601 .LVL114: + 1602 .L105: +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1603 .loc 1 1411 11 view .LVU582 +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1604 .loc 1 1411 50 is_stmt 0 view .LVU583 + ARM GAS /tmp/ccgN7hfx.s page 60 + + + 1605 00cc 414A ldr r2, .L129 + 1606 00ce 5168 ldr r1, [r2, #4] +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1607 .loc 1 1411 36 view .LVU584 + 1608 00d0 01F03F01 and r1, r1, #63 +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1609 .loc 1 1411 20 view .LVU585 + 1610 00d4 414A ldr r2, .L129+8 + 1611 00d6 B2FBF1FC udiv ip, r2, r1 + 1612 .LVL115: +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1613 .loc 1 1411 20 view .LVU586 + 1614 00da E2E7 b .L106 + 1615 .LVL116: + 1616 .L107: +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1617 .loc 1 1435 11 is_stmt 1 view .LVU587 +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1618 .loc 1 1435 50 is_stmt 0 view .LVU588 + 1619 00dc 3D4A ldr r2, .L129 + 1620 00de 5168 ldr r1, [r2, #4] +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1621 .loc 1 1435 36 view .LVU589 + 1622 00e0 01F03F01 and r1, r1, #63 +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1623 .loc 1 1435 20 view .LVU590 + 1624 00e4 3D4A ldr r2, .L129+8 + 1625 00e6 B2FBF1FC udiv ip, r2, r1 + 1626 .LVL117: +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1627 .loc 1 1435 20 view .LVU591 + 1628 00ea ABE7 b .L108 + 1629 .LVL118: + 1630 .L119: +1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; + 1631 .loc 1 1450 19 view .LVU592 + 1632 00ec 3C48 ldr r0, .L129+12 + 1633 .LVL119: +1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; + 1634 .loc 1 1450 19 view .LVU593 + 1635 00ee 8CE7 b .L100 + 1636 .LVL120: + 1637 .L120: +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1638 .loc 1 1464 21 view .LVU594 + 1639 00f0 3A48 ldr r0, .L129+8 + 1640 .LVL121: +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1641 .loc 1 1464 21 view .LVU595 + 1642 00f2 8AE7 b .L100 + 1643 .LVL122: + 1644 .L124: +1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** saiclocksource &= RCC_DCKCFGR1_SAI2SEL; + 1645 .loc 1 1478 5 is_stmt 1 view .LVU596 +1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** saiclocksource &= RCC_DCKCFGR1_SAI2SEL; + 1646 .loc 1 1478 20 is_stmt 0 view .LVU597 + 1647 00f4 374B ldr r3, .L129 + ARM GAS /tmp/ccgN7hfx.s page 61 + + + 1648 .LVL123: +1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** saiclocksource &= RCC_DCKCFGR1_SAI2SEL; + 1649 .loc 1 1478 20 view .LVU598 + 1650 00f6 D3F88C30 ldr r3, [r3, #140] + 1651 .LVL124: +1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** switch (saiclocksource) + 1652 .loc 1 1479 5 is_stmt 1 view .LVU599 +1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** switch (saiclocksource) + 1653 .loc 1 1479 20 is_stmt 0 view .LVU600 + 1654 00fa 03F44003 and r3, r3, #12582912 + 1655 .LVL125: +1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1656 .loc 1 1480 5 is_stmt 1 view .LVU601 + 1657 00fe B3F5000F cmp r3, #8388608 + 1658 0102 62D0 beq .L121 + 1659 0104 25D8 bhi .L110 + 1660 0106 7BB3 cbz r3, .L111 + 1661 0108 B3F5800F cmp r3, #4194304 + 1662 010c 20D1 bne .L127 +1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1663 .loc 1 1510 9 view .LVU602 +1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1664 .loc 1 1510 16 is_stmt 0 view .LVU603 + 1665 010e 314B ldr r3, .L129 + 1666 .LVL126: +1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1667 .loc 1 1510 16 view .LVU604 + 1668 0110 5B68 ldr r3, [r3, #4] +1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1669 .loc 1 1510 11 view .LVU605 + 1670 0112 13F4800F tst r3, #4194304 + 1671 0116 50D1 bne .L116 +1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1672 .loc 1 1513 11 is_stmt 1 view .LVU606 +1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1673 .loc 1 1513 49 is_stmt 0 view .LVU607 + 1674 0118 2E4B ldr r3, .L129 + 1675 011a 5B68 ldr r3, [r3, #4] +1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1676 .loc 1 1513 35 view .LVU608 + 1677 011c 03F03F03 and r3, r3, #63 +1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1678 .loc 1 1513 20 view .LVU609 + 1679 0120 2D49 ldr r1, .L129+4 + 1680 0122 B1FBF3F1 udiv r1, r1, r3 + 1681 .LVL127: + 1682 .L117: +1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); + 1683 .loc 1 1523 9 is_stmt 1 view .LVU610 +1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); + 1684 .loc 1 1523 22 is_stmt 0 view .LVU611 + 1685 0126 2B4B ldr r3, .L129 + 1686 0128 D3F88420 ldr r2, [r3, #132] +1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); + 1687 .loc 1 1523 16 view .LVU612 + 1688 012c C2F30362 ubfx r2, r2, #24, #4 + 1689 .LVL128: + ARM GAS /tmp/ccgN7hfx.s page 62 + + +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1690 .loc 1 1524 9 is_stmt 1 view .LVU613 +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1691 .loc 1 1524 38 is_stmt 0 view .LVU614 + 1692 0130 D3F88400 ldr r0, [r3, #132] + 1693 .LVL129: +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1694 .loc 1 1524 77 view .LVU615 + 1695 0134 C0F38810 ubfx r0, r0, #6, #9 +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1696 .loc 1 1524 31 view .LVU616 + 1697 0138 01FB00F0 mul r0, r1, r0 +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1698 .loc 1 1524 19 view .LVU617 + 1699 013c B0FBF2F0 udiv r0, r0, r2 + 1700 .LVL130: +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); + 1701 .loc 1 1527 9 is_stmt 1 view .LVU618 +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); + 1702 .loc 1 1527 23 is_stmt 0 view .LVU619 + 1703 0140 D3F88C30 ldr r3, [r3, #140] +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); + 1704 .loc 1 1527 34 view .LVU620 + 1705 0144 03F01F03 and r3, r3, #31 +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); + 1706 .loc 1 1527 16 view .LVU621 + 1707 0148 0133 adds r3, r3, #1 + 1708 .LVL131: +1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; + 1709 .loc 1 1528 9 is_stmt 1 view .LVU622 +1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; + 1710 .loc 1 1528 19 is_stmt 0 view .LVU623 + 1711 014a B0FBF3F0 udiv r0, r0, r3 + 1712 .LVL132: +1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1713 .loc 1 1529 9 is_stmt 1 view .LVU624 + 1714 014e 7047 bx lr + 1715 .LVL133: + 1716 .L127: +1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1717 .loc 1 1529 9 is_stmt 0 view .LVU625 + 1718 0150 7047 bx lr + 1719 .L110: +1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1720 .loc 1 1480 5 view .LVU626 + 1721 0152 B3F5400F cmp r3, #12582912 + 1722 0156 06D1 bne .L128 +1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1723 .loc 1 1539 9 is_stmt 1 view .LVU627 +1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1724 .loc 1 1539 16 is_stmt 0 view .LVU628 + 1725 0158 1E4B ldr r3, .L129 + 1726 .LVL134: +1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1727 .loc 1 1539 16 view .LVU629 + 1728 015a 5B68 ldr r3, [r3, #4] +1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccgN7hfx.s page 63 + + + 1729 .loc 1 1539 11 view .LVU630 + 1730 015c 13F4800F tst r3, #4194304 + 1731 0160 35D1 bne .L122 +1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1732 .loc 1 1542 21 view .LVU631 + 1733 0162 1D48 ldr r0, .L129+4 + 1734 .LVL135: +1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1735 .loc 1 1542 21 view .LVU632 + 1736 0164 7047 bx lr + 1737 .LVL136: + 1738 .L128: +1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1739 .loc 1 1542 21 view .LVU633 + 1740 0166 7047 bx lr + 1741 .L111: +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1742 .loc 1 1486 9 is_stmt 1 view .LVU634 +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1743 .loc 1 1486 16 is_stmt 0 view .LVU635 + 1744 0168 1A4B ldr r3, .L129 + 1745 .LVL137: +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1746 .loc 1 1486 16 view .LVU636 + 1747 016a 5B68 ldr r3, [r3, #4] +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1748 .loc 1 1486 11 view .LVU637 + 1749 016c 13F4800F tst r3, #4194304 + 1750 0170 1BD1 bne .L114 +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1751 .loc 1 1489 11 is_stmt 1 view .LVU638 +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1752 .loc 1 1489 49 is_stmt 0 view .LVU639 + 1753 0172 184B ldr r3, .L129 + 1754 0174 5B68 ldr r3, [r3, #4] +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1755 .loc 1 1489 35 view .LVU640 + 1756 0176 03F03F03 and r3, r3, #63 +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1757 .loc 1 1489 20 view .LVU641 + 1758 017a 1749 ldr r1, .L129+4 + 1759 017c B1FBF3F1 udiv r1, r1, r3 + 1760 .LVL138: + 1761 .L115: +1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); + 1762 .loc 1 1498 9 is_stmt 1 view .LVU642 +1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); + 1763 .loc 1 1498 22 is_stmt 0 view .LVU643 + 1764 0180 144B ldr r3, .L129 + 1765 0182 D3F88820 ldr r2, [r3, #136] +1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); + 1766 .loc 1 1498 16 view .LVU644 + 1767 0186 C2F30362 ubfx r2, r2, #24, #4 + 1768 .LVL139: +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1769 .loc 1 1499 9 is_stmt 1 view .LVU645 +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccgN7hfx.s page 64 + + + 1770 .loc 1 1499 38 is_stmt 0 view .LVU646 + 1771 018a D3F88800 ldr r0, [r3, #136] + 1772 .LVL140: +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1773 .loc 1 1499 77 view .LVU647 + 1774 018e C0F38810 ubfx r0, r0, #6, #9 +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1775 .loc 1 1499 31 view .LVU648 + 1776 0192 01FB00F0 mul r0, r1, r0 +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1777 .loc 1 1499 19 view .LVU649 + 1778 0196 B0FBF2F0 udiv r0, r0, r2 + 1779 .LVL141: +1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); + 1780 .loc 1 1502 9 is_stmt 1 view .LVU650 +1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); + 1781 .loc 1 1502 24 is_stmt 0 view .LVU651 + 1782 019a D3F88C30 ldr r3, [r3, #140] +1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); + 1783 .loc 1 1502 62 view .LVU652 + 1784 019e C3F30423 ubfx r3, r3, #8, #5 +1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** frequency = frequency/(tmpreg); + 1785 .loc 1 1502 16 view .LVU653 + 1786 01a2 0133 adds r3, r3, #1 + 1787 .LVL142: +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; + 1788 .loc 1 1503 9 is_stmt 1 view .LVU654 +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; + 1789 .loc 1 1503 19 is_stmt 0 view .LVU655 + 1790 01a4 B0FBF3F0 udiv r0, r0, r3 + 1791 .LVL143: +1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1792 .loc 1 1504 9 is_stmt 1 view .LVU656 + 1793 01a8 7047 bx lr + 1794 .LVL144: + 1795 .L114: +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1796 .loc 1 1494 11 view .LVU657 +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1797 .loc 1 1494 50 is_stmt 0 view .LVU658 + 1798 01aa 0A4B ldr r3, .L129 + 1799 01ac 5B68 ldr r3, [r3, #4] +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1800 .loc 1 1494 36 view .LVU659 + 1801 01ae 03F03F03 and r3, r3, #63 +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1802 .loc 1 1494 20 view .LVU660 + 1803 01b2 0A49 ldr r1, .L129+8 + 1804 01b4 B1FBF3F1 udiv r1, r1, r3 + 1805 .LVL145: +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1806 .loc 1 1494 20 view .LVU661 + 1807 01b8 E2E7 b .L115 + 1808 .LVL146: + 1809 .L116: +1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1810 .loc 1 1518 11 is_stmt 1 view .LVU662 + ARM GAS /tmp/ccgN7hfx.s page 65 + + +1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1811 .loc 1 1518 50 is_stmt 0 view .LVU663 + 1812 01ba 064B ldr r3, .L129 + 1813 01bc 5B68 ldr r3, [r3, #4] +1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1814 .loc 1 1518 36 view .LVU664 + 1815 01be 03F03F03 and r3, r3, #63 +1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1816 .loc 1 1518 20 view .LVU665 + 1817 01c2 0649 ldr r1, .L129+8 + 1818 01c4 B1FBF3F1 udiv r1, r1, r3 + 1819 .LVL147: +1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1820 .loc 1 1518 20 view .LVU666 + 1821 01c8 ADE7 b .L117 + 1822 .LVL148: + 1823 .L121: +1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; + 1824 .loc 1 1533 19 view .LVU667 + 1825 01ca 0548 ldr r0, .L129+12 + 1826 .LVL149: +1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** break; + 1827 .loc 1 1533 19 view .LVU668 + 1828 01cc 7047 bx lr + 1829 .LVL150: + 1830 .L122: +1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1831 .loc 1 1547 21 view .LVU669 + 1832 01ce 0348 ldr r0, .L129+8 + 1833 .LVL151: +1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1834 .loc 1 1559 3 is_stmt 1 view .LVU670 +1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1835 .loc 1 1559 10 is_stmt 0 view .LVU671 + 1836 01d0 1EE7 b .L99 + 1837 .L130: + 1838 01d2 00BF .align 2 + 1839 .L129: + 1840 01d4 00380240 .word 1073887232 + 1841 01d8 0024F400 .word 16000000 + 1842 01dc 40787D01 .word 25000000 + 1843 01e0 0080BB00 .word 12288000 + 1844 .cfi_endproc + 1845 .LFE143: + 1847 .section .text.HAL_RCCEx_EnablePLLI2S,"ax",%progbits + 1848 .align 1 + 1849 .global HAL_RCCEx_EnablePLLI2S + 1850 .syntax unified + 1851 .thumb + 1852 .thumb_func + 1854 HAL_RCCEx_EnablePLLI2S: + 1855 .LVL152: + 1856 .LFB144: +1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @} +1564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ + ARM GAS /tmp/ccgN7hfx.s page 66 + + +1565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions +1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @brief Extended Clock management functions +1568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * +1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** @verbatim +1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** =============================================================================== +1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** ##### Extended clock management functions ##### +1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** =============================================================================== +1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** [..] +1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** This subsection provides a set of functions allowing to control the +1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** activation or deactivation of PLLI2S, PLLSAI. +1576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** @endverbatim +1577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @{ +1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ +1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** +1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @brief Enable PLLI2S. +1582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that +1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * contains the configuration information for the PLLI2S +1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @retval HAL status +1585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ +1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) +1587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1857 .loc 1 1587 1 is_stmt 1 view -0 + 1858 .cfi_startproc + 1859 @ args = 0, pretend = 0, frame = 0 + 1860 @ frame_needed = 0, uses_anonymous_args = 0 + 1861 .loc 1 1587 1 is_stmt 0 view .LVU673 + 1862 0000 38B5 push {r3, r4, r5, lr} + 1863 .LCFI4: + 1864 .cfi_def_cfa_offset 16 + 1865 .cfi_offset 3, -16 + 1866 .cfi_offset 4, -12 + 1867 .cfi_offset 5, -8 + 1868 .cfi_offset 14, -4 + 1869 0002 0546 mov r5, r0 +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t tickstart; + 1870 .loc 1 1588 3 is_stmt 1 view .LVU674 +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check for parameters */ +1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN)); + 1871 .loc 1 1591 3 view .LVU675 +1592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR)); + 1872 .loc 1 1592 3 view .LVU676 +1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ)); + 1873 .loc 1 1593 3 view .LVU677 +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined(RCC_PLLI2SCFGR_PLLI2SP) +1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP)); + 1874 .loc 1 1595 3 view .LVU678 +1596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* RCC_PLLI2SCFGR_PLLI2SP */ +1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Disable the PLLI2S */ +1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLI2S_DISABLE(); + 1875 .loc 1 1599 3 view .LVU679 + 1876 0004 1B4A ldr r2, .L142 + 1877 0006 1368 ldr r3, [r2] + 1878 0008 23F08063 bic r3, r3, #67108864 + ARM GAS /tmp/ccgN7hfx.s page 67 + + + 1879 000c 1360 str r3, [r2] +1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait till PLLI2S is disabled */ +1602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 1880 .loc 1 1602 3 view .LVU680 + 1881 .loc 1 1602 15 is_stmt 0 view .LVU681 + 1882 000e FFF7FEFF bl HAL_GetTick + 1883 .LVL153: + 1884 .loc 1 1602 15 view .LVU682 + 1885 0012 0446 mov r4, r0 + 1886 .LVL154: +1603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + 1887 .loc 1 1603 3 is_stmt 1 view .LVU683 + 1888 .L132: + 1889 .loc 1 1603 48 view .LVU684 + 1890 .loc 1 1603 9 is_stmt 0 view .LVU685 + 1891 0014 174B ldr r3, .L142 + 1892 0016 1B68 ldr r3, [r3] + 1893 .loc 1 1603 48 view .LVU686 + 1894 0018 13F0006F tst r3, #134217728 + 1895 001c 06D0 beq .L140 +1604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + 1896 .loc 1 1605 5 is_stmt 1 view .LVU687 + 1897 .loc 1 1605 9 is_stmt 0 view .LVU688 + 1898 001e FFF7FEFF bl HAL_GetTick + 1899 .LVL155: + 1900 .loc 1 1605 23 discriminator 1 view .LVU689 + 1901 0022 001B subs r0, r0, r4 + 1902 .loc 1 1605 7 discriminator 1 view .LVU690 + 1903 0024 6428 cmp r0, #100 + 1904 0026 F5D9 bls .L132 +1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* return in case of Timeout detected */ +1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 1905 .loc 1 1608 14 view .LVU691 + 1906 0028 0320 movs r0, #3 + 1907 .L133: +1609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the PLLI2S division factors */ +1613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx +1614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ +1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ +1616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ +1617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #else +1619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ +1620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* I2SPCLK = PLLI2S_VCO / PLLI2SP */ +1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ +1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ +1623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit +1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ +1625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable the PLLI2S */ +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLI2S_ENABLE(); + ARM GAS /tmp/ccgN7hfx.s page 68 + + +1628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait till PLLI2S is ready */ +1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); +1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) +1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) +1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* return in case of Timeout detected */ +1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; +1637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_OK; +1641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1908 .loc 1 1641 1 view .LVU692 + 1909 002a 38BD pop {r3, r4, r5, pc} + 1910 .LVL156: + 1911 .L140: +1623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ + 1912 .loc 1 1623 3 is_stmt 1 view .LVU693 + 1913 002c 2A68 ldr r2, [r5] + 1914 002e EB68 ldr r3, [r5, #12] + 1915 0030 1B04 lsls r3, r3, #16 + 1916 0032 43EA8213 orr r3, r3, r2, lsl #6 + 1917 0036 AA68 ldr r2, [r5, #8] + 1918 0038 43EA0263 orr r3, r3, r2, lsl #24 + 1919 003c 6A68 ldr r2, [r5, #4] + 1920 003e 43EA0273 orr r3, r3, r2, lsl #28 + 1921 0042 0C4A ldr r2, .L142 + 1922 0044 C2F88430 str r3, [r2, #132] +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 1923 .loc 1 1627 3 view .LVU694 + 1924 0048 1368 ldr r3, [r2] + 1925 004a 43F08063 orr r3, r3, #67108864 + 1926 004e 1360 str r3, [r2] +1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 1927 .loc 1 1630 3 view .LVU695 +1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 1928 .loc 1 1630 15 is_stmt 0 view .LVU696 + 1929 0050 FFF7FEFF bl HAL_GetTick + 1930 .LVL157: + 1931 0054 0446 mov r4, r0 + 1932 .LVL158: +1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1933 .loc 1 1631 3 is_stmt 1 view .LVU697 + 1934 .L135: +1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1935 .loc 1 1631 48 view .LVU698 +1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1936 .loc 1 1631 9 is_stmt 0 view .LVU699 + 1937 0056 074B ldr r3, .L142 + 1938 0058 1B68 ldr r3, [r3] +1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1939 .loc 1 1631 48 view .LVU700 + 1940 005a 13F0006F tst r3, #134217728 + 1941 005e 06D1 bne .L141 +1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccgN7hfx.s page 69 + + + 1942 .loc 1 1633 5 is_stmt 1 view .LVU701 +1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1943 .loc 1 1633 9 is_stmt 0 view .LVU702 + 1944 0060 FFF7FEFF bl HAL_GetTick + 1945 .LVL159: +1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1946 .loc 1 1633 23 discriminator 1 view .LVU703 + 1947 0064 001B subs r0, r0, r4 +1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1948 .loc 1 1633 7 discriminator 1 view .LVU704 + 1949 0066 6428 cmp r0, #100 + 1950 0068 F5D9 bls .L135 +1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1951 .loc 1 1636 14 view .LVU705 + 1952 006a 0320 movs r0, #3 + 1953 006c DDE7 b .L133 + 1954 .L141: +1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 1955 .loc 1 1640 9 view .LVU706 + 1956 006e 0020 movs r0, #0 + 1957 0070 DBE7 b .L133 + 1958 .L143: + 1959 0072 00BF .align 2 + 1960 .L142: + 1961 0074 00380240 .word 1073887232 + 1962 .cfi_endproc + 1963 .LFE144: + 1965 .section .text.HAL_RCCEx_DisablePLLI2S,"ax",%progbits + 1966 .align 1 + 1967 .global HAL_RCCEx_DisablePLLI2S + 1968 .syntax unified + 1969 .thumb + 1970 .thumb_func + 1972 HAL_RCCEx_DisablePLLI2S: + 1973 .LFB145: +1642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** +1644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @brief Disable PLLI2S. +1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @retval HAL status +1646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ +1647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) +1648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 1974 .loc 1 1648 1 is_stmt 1 view -0 + 1975 .cfi_startproc + 1976 @ args = 0, pretend = 0, frame = 0 + 1977 @ frame_needed = 0, uses_anonymous_args = 0 + 1978 0000 10B5 push {r4, lr} + 1979 .LCFI5: + 1980 .cfi_def_cfa_offset 8 + 1981 .cfi_offset 4, -8 + 1982 .cfi_offset 14, -4 +1649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t tickstart; + 1983 .loc 1 1649 3 view .LVU708 +1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Disable the PLLI2S */ +1652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLI2S_DISABLE(); + 1984 .loc 1 1652 3 view .LVU709 + ARM GAS /tmp/ccgN7hfx.s page 70 + + + 1985 0002 0B4A ldr r2, .L151 + 1986 0004 1368 ldr r3, [r2] + 1987 0006 23F08063 bic r3, r3, #67108864 + 1988 000a 1360 str r3, [r2] +1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait till PLLI2S is disabled */ +1655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 1989 .loc 1 1655 3 view .LVU710 + 1990 .loc 1 1655 15 is_stmt 0 view .LVU711 + 1991 000c FFF7FEFF bl HAL_GetTick + 1992 .LVL160: + 1993 0010 0446 mov r4, r0 + 1994 .LVL161: +1656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + 1995 .loc 1 1656 3 is_stmt 1 view .LVU712 + 1996 .L145: + 1997 .loc 1 1656 45 view .LVU713 + 1998 .loc 1 1656 9 is_stmt 0 view .LVU714 + 1999 0012 074B ldr r3, .L151 + 2000 0014 1B68 ldr r3, [r3] + 2001 .loc 1 1656 45 view .LVU715 + 2002 0016 13F0006F tst r3, #134217728 + 2003 001a 06D0 beq .L150 +1657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + 2004 .loc 1 1658 5 is_stmt 1 view .LVU716 + 2005 .loc 1 1658 9 is_stmt 0 view .LVU717 + 2006 001c FFF7FEFF bl HAL_GetTick + 2007 .LVL162: + 2008 .loc 1 1658 23 discriminator 1 view .LVU718 + 2009 0020 001B subs r0, r0, r4 + 2010 .loc 1 1658 7 discriminator 1 view .LVU719 + 2011 0022 6428 cmp r0, #100 + 2012 0024 F5D9 bls .L145 +1659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* return in case of Timeout detected */ +1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 2013 .loc 1 1661 14 view .LVU720 + 2014 0026 0320 movs r0, #3 + 2015 0028 00E0 b .L146 + 2016 .L150: +1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_OK; + 2017 .loc 1 1665 10 view .LVU721 + 2018 002a 0020 movs r0, #0 + 2019 .L146: +1666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 2020 .loc 1 1666 1 view .LVU722 + 2021 002c 10BD pop {r4, pc} + 2022 .LVL163: + 2023 .L152: + 2024 .loc 1 1666 1 view .LVU723 + 2025 002e 00BF .align 2 + 2026 .L151: + 2027 0030 00380240 .word 1073887232 + ARM GAS /tmp/ccgN7hfx.s page 71 + + + 2028 .cfi_endproc + 2029 .LFE145: + 2031 .section .text.HAL_RCCEx_EnablePLLSAI,"ax",%progbits + 2032 .align 1 + 2033 .global HAL_RCCEx_EnablePLLSAI + 2034 .syntax unified + 2035 .thumb + 2036 .thumb_func + 2038 HAL_RCCEx_EnablePLLSAI: + 2039 .LVL164: + 2040 .LFB146: +1667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** +1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @brief Enable PLLSAI. +1670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @param PLLSAIInit pointer to an RCC_PLLSAIInitTypeDef structure that +1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * contains the configuration information for the PLLSAI +1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @retval HAL status +1673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ +1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit) +1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 2041 .loc 1 1675 1 is_stmt 1 view -0 + 2042 .cfi_startproc + 2043 @ args = 0, pretend = 0, frame = 0 + 2044 @ frame_needed = 0, uses_anonymous_args = 0 + 2045 .loc 1 1675 1 is_stmt 0 view .LVU725 + 2046 0000 38B5 push {r3, r4, r5, lr} + 2047 .LCFI6: + 2048 .cfi_def_cfa_offset 16 + 2049 .cfi_offset 3, -16 + 2050 .cfi_offset 4, -12 + 2051 .cfi_offset 5, -8 + 2052 .cfi_offset 14, -4 + 2053 0002 0546 mov r5, r0 +1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t tickstart; + 2054 .loc 1 1676 3 is_stmt 1 view .LVU726 +1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Check for parameters */ +1679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN)); + 2055 .loc 1 1679 3 view .LVU727 +1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ)); + 2056 .loc 1 1680 3 view .LVU728 +1681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP)); + 2057 .loc 1 1681 3 view .LVU729 +1682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined(RCC_PLLSAICFGR_PLLSAIR) +1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR)); + 2058 .loc 1 1683 3 view .LVU730 +1684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* RCC_PLLSAICFGR_PLLSAIR */ +1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Disable the PLLSAI */ +1687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLSAI_DISABLE(); + 2059 .loc 1 1687 3 view .LVU731 + 2060 0004 1B4A ldr r2, .L164 + 2061 0006 1368 ldr r3, [r2] + 2062 0008 23F08053 bic r3, r3, #268435456 + 2063 000c 1360 str r3, [r2] +1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait till PLLSAI is disabled */ + ARM GAS /tmp/ccgN7hfx.s page 72 + + +1690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 2064 .loc 1 1690 3 view .LVU732 + 2065 .loc 1 1690 15 is_stmt 0 view .LVU733 + 2066 000e FFF7FEFF bl HAL_GetTick + 2067 .LVL165: + 2068 .loc 1 1690 15 view .LVU734 + 2069 0012 0446 mov r4, r0 + 2070 .LVL166: +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + 2071 .loc 1 1691 3 is_stmt 1 view .LVU735 + 2072 .L154: + 2073 .loc 1 1691 37 view .LVU736 + 2074 .loc 1 1691 9 is_stmt 0 view .LVU737 + 2075 0014 174B ldr r3, .L164 + 2076 0016 1B68 ldr r3, [r3] + 2077 .loc 1 1691 37 view .LVU738 + 2078 0018 13F0005F tst r3, #536870912 + 2079 001c 06D0 beq .L162 +1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + 2080 .loc 1 1693 5 is_stmt 1 view .LVU739 + 2081 .loc 1 1693 9 is_stmt 0 view .LVU740 + 2082 001e FFF7FEFF bl HAL_GetTick + 2083 .LVL167: + 2084 .loc 1 1693 23 discriminator 1 view .LVU741 + 2085 0022 001B subs r0, r0, r4 + 2086 .loc 1 1693 7 discriminator 1 view .LVU742 + 2087 0024 6428 cmp r0, #100 + 2088 0026 F5D9 bls .L154 +1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* return in case of Timeout detected */ +1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 2089 .loc 1 1696 14 view .LVU743 + 2090 0028 0320 movs r0, #3 + 2091 .L155: +1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Configure the PLLSAI division factors */ +1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx +1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ +1703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ +1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ +1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ); +1706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #else +1707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ +1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ +1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ +1710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ +1711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \ +1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); +1713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** #endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ +1714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Enable the PLLSAI */ +1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLSAI_ENABLE(); +1717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait till PLLSAI is ready */ + ARM GAS /tmp/ccgN7hfx.s page 73 + + +1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); +1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) +1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) +1723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* return in case of Timeout detected */ +1725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; +1726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_OK; +1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 2092 .loc 1 1730 1 view .LVU744 + 2093 002a 38BD pop {r3, r4, r5, pc} + 2094 .LVL168: + 2095 .L162: +1711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); + 2096 .loc 1 1711 3 is_stmt 1 view .LVU745 + 2097 002c 2A68 ldr r2, [r5] + 2098 002e EB68 ldr r3, [r5, #12] + 2099 0030 1B04 lsls r3, r3, #16 + 2100 0032 43EA8213 orr r3, r3, r2, lsl #6 + 2101 0036 6A68 ldr r2, [r5, #4] + 2102 0038 43EA0263 orr r3, r3, r2, lsl #24 + 2103 003c AA68 ldr r2, [r5, #8] + 2104 003e 43EA0273 orr r3, r3, r2, lsl #28 + 2105 0042 0C4A ldr r2, .L164 + 2106 0044 C2F88830 str r3, [r2, #136] +1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** + 2107 .loc 1 1716 3 view .LVU746 + 2108 0048 1368 ldr r3, [r2] + 2109 004a 43F08053 orr r3, r3, #268435456 + 2110 004e 1360 str r3, [r2] +1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + 2111 .loc 1 1719 3 view .LVU747 +1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + 2112 .loc 1 1719 15 is_stmt 0 view .LVU748 + 2113 0050 FFF7FEFF bl HAL_GetTick + 2114 .LVL169: + 2115 0054 0446 mov r4, r0 + 2116 .LVL170: +1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 2117 .loc 1 1720 3 is_stmt 1 view .LVU749 + 2118 .L157: +1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 2119 .loc 1 1720 37 view .LVU750 +1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 2120 .loc 1 1720 9 is_stmt 0 view .LVU751 + 2121 0056 074B ldr r3, .L164 + 2122 0058 1B68 ldr r3, [r3] +1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 2123 .loc 1 1720 37 view .LVU752 + 2124 005a 13F0005F tst r3, #536870912 + 2125 005e 06D1 bne .L163 +1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 2126 .loc 1 1722 5 is_stmt 1 view .LVU753 +1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccgN7hfx.s page 74 + + + 2127 .loc 1 1722 9 is_stmt 0 view .LVU754 + 2128 0060 FFF7FEFF bl HAL_GetTick + 2129 .LVL171: +1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 2130 .loc 1 1722 23 discriminator 1 view .LVU755 + 2131 0064 001B subs r0, r0, r4 +1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 2132 .loc 1 1722 7 discriminator 1 view .LVU756 + 2133 0066 6428 cmp r0, #100 + 2134 0068 F5D9 bls .L157 +1725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 2135 .loc 1 1725 14 view .LVU757 + 2136 006a 0320 movs r0, #3 + 2137 006c DDE7 b .L155 + 2138 .L163: +1729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 2139 .loc 1 1729 9 view .LVU758 + 2140 006e 0020 movs r0, #0 + 2141 0070 DBE7 b .L155 + 2142 .L165: + 2143 0072 00BF .align 2 + 2144 .L164: + 2145 0074 00380240 .word 1073887232 + 2146 .cfi_endproc + 2147 .LFE146: + 2149 .section .text.HAL_RCCEx_DisablePLLSAI,"ax",%progbits + 2150 .align 1 + 2151 .global HAL_RCCEx_DisablePLLSAI + 2152 .syntax unified + 2153 .thumb + 2154 .thumb_func + 2156 HAL_RCCEx_DisablePLLSAI: + 2157 .LFB147: +1731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /** +1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @brief Disable PLLSAI. +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** * @retval HAL status +1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** */ +1736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void) +1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { + 2158 .loc 1 1737 1 is_stmt 1 view -0 + 2159 .cfi_startproc + 2160 @ args = 0, pretend = 0, frame = 0 + 2161 @ frame_needed = 0, uses_anonymous_args = 0 + 2162 0000 10B5 push {r4, lr} + 2163 .LCFI7: + 2164 .cfi_def_cfa_offset 8 + 2165 .cfi_offset 4, -8 + 2166 .cfi_offset 14, -4 +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** uint32_t tickstart; + 2167 .loc 1 1738 3 view .LVU760 +1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Disable the PLLSAI */ +1741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** __HAL_RCC_PLLSAI_DISABLE(); + 2168 .loc 1 1741 3 view .LVU761 + 2169 0002 0B4A ldr r2, .L173 + 2170 0004 1368 ldr r3, [r2] + ARM GAS /tmp/ccgN7hfx.s page 75 + + + 2171 0006 23F08053 bic r3, r3, #268435456 + 2172 000a 1360 str r3, [r2] +1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* Wait till PLLSAI is disabled */ +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 2173 .loc 1 1744 3 view .LVU762 + 2174 .loc 1 1744 15 is_stmt 0 view .LVU763 + 2175 000c FFF7FEFF bl HAL_GetTick + 2176 .LVL172: + 2177 0010 0446 mov r4, r0 + 2178 .LVL173: +1745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + 2179 .loc 1 1745 3 is_stmt 1 view .LVU764 + 2180 .L167: + 2181 .loc 1 1745 37 view .LVU765 + 2182 .loc 1 1745 9 is_stmt 0 view .LVU766 + 2183 0012 074B ldr r3, .L173 + 2184 0014 1B68 ldr r3, [r3] + 2185 .loc 1 1745 37 view .LVU767 + 2186 0016 13F0005F tst r3, #536870912 + 2187 001a 06D0 beq .L172 +1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + 2188 .loc 1 1747 5 is_stmt 1 view .LVU768 + 2189 .loc 1 1747 9 is_stmt 0 view .LVU769 + 2190 001c FFF7FEFF bl HAL_GetTick + 2191 .LVL174: + 2192 .loc 1 1747 23 discriminator 1 view .LVU770 + 2193 0020 001B subs r0, r0, r4 + 2194 .loc 1 1747 7 discriminator 1 view .LVU771 + 2195 0022 6428 cmp r0, #100 + 2196 0024 F5D9 bls .L167 +1748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** { +1749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** /* return in case of Timeout detected */ +1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 2197 .loc 1 1750 14 view .LVU772 + 2198 0026 0320 movs r0, #3 + 2199 0028 00E0 b .L168 + 2200 .L172: +1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } +1753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** return HAL_OK; + 2201 .loc 1 1754 10 view .LVU773 + 2202 002a 0020 movs r0, #0 + 2203 .L168: +1755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c **** } + 2204 .loc 1 1755 1 view .LVU774 + 2205 002c 10BD pop {r4, pc} + 2206 .LVL175: + 2207 .L174: + 2208 .loc 1 1755 1 view .LVU775 + 2209 002e 00BF .align 2 + 2210 .L173: + 2211 0030 00380240 .word 1073887232 + 2212 .cfi_endproc + 2213 .LFE147: + ARM GAS /tmp/ccgN7hfx.s page 76 + + + 2215 .text + 2216 .Letext0: + 2217 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 2218 .file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 2219 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + 2220 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 2221 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h" + 2222 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h" + ARM GAS /tmp/ccgN7hfx.s page 77 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_rcc_ex.c + /tmp/ccgN7hfx.s:20 .text.HAL_RCCEx_PeriphCLKConfig:00000000 $t + /tmp/ccgN7hfx.s:26 .text.HAL_RCCEx_PeriphCLKConfig:00000000 HAL_RCCEx_PeriphCLKConfig + /tmp/ccgN7hfx.s:511 .text.HAL_RCCEx_PeriphCLKConfig:000002e4 $d + /tmp/ccgN7hfx.s:515 .text.HAL_RCCEx_PeriphCLKConfig:000002e8 $t + /tmp/ccgN7hfx.s:954 .text.HAL_RCCEx_PeriphCLKConfig:00000504 $d + /tmp/ccgN7hfx.s:961 .text.HAL_RCCEx_PeriphCLKConfig:00000510 $t + /tmp/ccgN7hfx.s:1131 .text.HAL_RCCEx_PeriphCLKConfig:000005fc $d + /tmp/ccgN7hfx.s:1136 .text.HAL_RCCEx_GetPeriphCLKConfig:00000000 $t + /tmp/ccgN7hfx.s:1142 .text.HAL_RCCEx_GetPeriphCLKConfig:00000000 HAL_RCCEx_GetPeriphCLKConfig + /tmp/ccgN7hfx.s:1401 .text.HAL_RCCEx_GetPeriphCLKConfig:00000180 $d + /tmp/ccgN7hfx.s:1407 .text.HAL_RCCEx_GetPeriphCLKFreq:00000000 $t + /tmp/ccgN7hfx.s:1413 .text.HAL_RCCEx_GetPeriphCLKFreq:00000000 HAL_RCCEx_GetPeriphCLKFreq + /tmp/ccgN7hfx.s:1840 .text.HAL_RCCEx_GetPeriphCLKFreq:000001d4 $d + /tmp/ccgN7hfx.s:1848 .text.HAL_RCCEx_EnablePLLI2S:00000000 $t + /tmp/ccgN7hfx.s:1854 .text.HAL_RCCEx_EnablePLLI2S:00000000 HAL_RCCEx_EnablePLLI2S + /tmp/ccgN7hfx.s:1961 .text.HAL_RCCEx_EnablePLLI2S:00000074 $d + /tmp/ccgN7hfx.s:1966 .text.HAL_RCCEx_DisablePLLI2S:00000000 $t + /tmp/ccgN7hfx.s:1972 .text.HAL_RCCEx_DisablePLLI2S:00000000 HAL_RCCEx_DisablePLLI2S + /tmp/ccgN7hfx.s:2027 .text.HAL_RCCEx_DisablePLLI2S:00000030 $d + /tmp/ccgN7hfx.s:2032 .text.HAL_RCCEx_EnablePLLSAI:00000000 $t + /tmp/ccgN7hfx.s:2038 .text.HAL_RCCEx_EnablePLLSAI:00000000 HAL_RCCEx_EnablePLLSAI + /tmp/ccgN7hfx.s:2145 .text.HAL_RCCEx_EnablePLLSAI:00000074 $d + /tmp/ccgN7hfx.s:2150 .text.HAL_RCCEx_DisablePLLSAI:00000000 $t + /tmp/ccgN7hfx.s:2156 .text.HAL_RCCEx_DisablePLLSAI:00000000 HAL_RCCEx_DisablePLLSAI + /tmp/ccgN7hfx.s:2211 .text.HAL_RCCEx_DisablePLLSAI:00000030 $d + +UNDEFINED SYMBOLS +HAL_GetTick diff --git a/build/stm32f7xx_hal_rcc_ex.o b/build/stm32f7xx_hal_rcc_ex.o new file mode 100644 index 0000000000000000000000000000000000000000..53d04f5635e061176c6daa73873bdd121c59fe14 GIT binary patch literal 20860 zcmdU$33wdUmG5tLsajG?mfC80-`bXC8?alO4F3aRM_CNB|SE5nv343=k3=lT3Id;mL#~EFohPf`Lau8_U511m6FD@2OU)5roY5 z&G)@mpQ?ZNoOAEF=dM+%uD*I{^)kz{lzUiemKv0lN~_iuXRgL9RiLJ+#3R@2OIzk| z9-XlKBl;g%eOvRi0p+`G({0TaTLM+LZK~R$PE(1^+trN1=1~KxaAf~|tDZZ#ySQMW zJalABR@FhI|FC8MiM}Z+v2i=|ZrH903z|a%eN%G#_quuQsjVh&K`Zj+s>G7*_G1?F zCHk&b{nm_7BAi>EID0!a!QAZrudM#n$=%^;iN3CQ5J2d zZ=_MHg5?_5Qn1%!>06x9f2C^)9r0KcEL&ZRJ+&k0Em5AE(cft-3EPh9Ht2d1eXz8M zCEMORXc_3cI-@@(mSX#e$D&}lKr9FBscp%62KqWO`ZpTOKzVo6V^OfIb1kvG9!p<+ zM*m9JQg_5-QLt3Hma3_qmNM!E#**lZ?Hz3CfSNL*f1X%W?1)(Y(6RrR>QISa_i#3#hyR8TWm8Pqg7q468`P!t3u5MXi;d>$M1dgv45GpdID`7m-qV) zt0&cbUpe)C6B=h7d(jRj4qG#BdEJ`v?bofs?}CrLe)a0{t(A$s+VPDOTJ1z%opqCS z`#-^F)j(gj@tMBtQu@T``VZ090r)xrU(X!wTs@&9gi#ySKW&R|puFq0%3%MN)#E#+ zAw906VxX^N+~#o|Q#HqLM&5*#n|G*Siw*ljC(5s$)L*~qrsjfylcAe7UAQuy-T&&A zhp>|U{b=Wu$^B-njz4t9Fdh!0tcqEQ!xbE1`sdh9v7;ATXHp|$clF5rSuCwse^YZo z%Y?M5x4sZkiOx-S)nI8ek|X*XB*%`>tMKoO-ObPLF{@a^XpVa+XVujNwW&7+(js#BGJ{NcyBrY9`)#Iy(53zN_b zFF(eWu?ub772MR~_TgPE-X5S8Z5}vTw--Htel3tbz{;}w%{nUSXFD@;$MsL8zaV`M z`ZHs41YS8NuD|lKBNv9N^8dHS)rsgJB|kE8~wd27;h=KnEiciN`LPv ze*CBkx9N7*ueLYUW3SyAK6rdrUgai}vMPO1ld>BQiq6-y1F2mmAFNCvUxP{64Ld~V z>pFmkvVA)wRqQ(`sRKS=T)cEux~Ya8ZmRa6o2v8~&x!J`O7Yy+ zutQR+;h?LlJ#exQ*CIriP)P4Yn(b6w2hbZP-Pdpcy011{11Cq0@8EtAsPeI$#k|t_ z4yl4`Vx7y^CHlHa_2jXSKc2|>XD{1#LKUT9=JHy4Nq^^ZUU%Rf{q)cYHKnnC#tYZ) z=jsd}YFSm=oHx*yTYG5ps&ksH#A2&y)k7Z~`;b?ioxvX;x1(Hf2afLwW`Cd(`#w09 z(4H_JR_VSE-c9@xqyO`x*n6h<4{a1*ryts|;>XZGd9+qE6ArBt?`yU9YCUI-_g$ax z&M`LL?>Jf^8~ z50$JwpL=a?&7lZVc4DzTXXS$*96xrN%v2k5$h6SXEqphjJz@W`%JzM5Jb~U@zW+pd zuK&=vEq4*_M8vToYC}bTIcor)bX?e*K@_B(e z+S6=l-vxn7*?*2}-xRox{o!}z#=wQlpYGPz9C(=ZWw`dv%&I!{ccv@%1U55&z|Frc za2D&&GIqP5&kDRw2idM-rxn=18b`Q_T~^=*c2SP2*lh)FrXtr>?6FkV)zpl%?EyH; zPPaIZ)4pb%jlLSO9|5SGx~1zeJ$)Hzo1l{%&P=O?Ij%)WYD6oN)`;&T?Hh57oxo{^ zi9Xw|ge5oVUzPa-B!Uma=C95+^FalVP^=L#E%+kE^&(~j4^jL_5wn#&6E*oS^7R^z zvCI*$2OmR({&>>k|DxEE^mvG3N7CbuDfSF{{0&_BFZKP59{2dK$b1v_AZLO9s-(vb zw8OuB9K-h&qy_Il8~r=Sv2I^MelQ>X?Y~YkPY-6Xf*VAf6&y|ROCrt=zCu@D5wSRU z39bJk;@sePT5lC`ez20BZx?Yva4$RK4iU?PoeX2Ih)aSuGv<3lToJs6p1&<(b#MjC z-Ya5F@I_kh7jb=X1z*BjCE@Nl9m77HxA`SS`k>&e-*Ge@vJ=SJ&4xR{*a!+P$~161IlW+4gCOh zThI8lv+1ygapni{aRRN+r^JNHvyS1@y58ew8x)mP{s4YPeb<;PDKsJ7fYUhNZJcwT z+lezj4vU=sG-=GWY{Ht;}@S|0Tx%YtSCXIc)Id?1WN} z9|rHEavS`N%4IdB{z?inpq+-(1V7g}uZCg?&d(V<7tk1MJ-u#r%t)X<^%^|*u2fcf z2I};ofv`q6O!vUhhcjfMpw;5&(fAsQ@5C9h(52QEqg;jzvvG#*M|P{tDCz2TDx*|( z80C+kycee$Yh|;luloG3Dzyur3}QKg8249WSwz9A3B5`2cAu{PEDZbU9Qx5|+$zRf zQy50e;5<^0{{a?jg7(s~f=>Poim&6GsOQxd?de=(oQHGb6nL{*wQeqYdLqvbR@tU? z??Zl@x`oWwu62Fz*@JW9zcQcM-CltF3!IbuX!CfSe}ynvcirQTzKi&Bqso6CU8kqn z+iqeOvTDtIH*vR{c*spWifVM8r`^O`ZsL76@hIA7@<;-ajkF4LLRogsgq#ijkyfo0 zM0o_$bv3?DojOLxRVK4Sy?FJ zoS8*^<_KIpjkq#2ANzIy3c7^dD6*sut-!S_&03U|1)HgsK1R$!k%{n~gG2@sxl#$@ zVuqmj)M2uckrA~x+l_o?_R7$LY%I%&B}!C99z^C;(&=Fz$6D0ax0VLb=L^Vp$QU8`#wH^eO>AD_&O#taEksR@!?bc@|qWd5D>pO&*w8IIq;?&V)3^QVu+E=2pkkQZ+$~jh5JFw8SrrmiV*L z5(%Rv-Zfg{FGfr7!r_e;Dt+h;-4#6KtYU+Gs#v#dt)$6joR&I=XxGVF;y#?rP5y^g zpF@~{@TB1fL>#hfQ6@!+z*Jx2hAB<=C!yD<~5b4!&5lXN^(nMNA zJRxe*gjeGYk73T$wbzsbjV9Ry+-Q=w0lzTGXMui`B-qP-mCeTzcfyN4a9#M+!y9`Z zaxKBhfJqbZ1;pK=CQZN>5HE?E{2fk9T|m4gYVvKPCfwfV-HGY)bNY}p{d~@&NIs4e zVx(2xBzO_NAivYksE{gWHxtWW%x+vlP}=|=`i^_lg=l3FG4+1pK67t~;>^~6k!F|@=Ba0M+vuihm``EgwDVJ4o#=`~Y6Y0L!U@tWPB*ixM4b7;y) zET|YDJLflujwhlc7_6l>5~m_q<{)_@2XT*1o=ccy4e^}O@*lu<-N22HvoShZLp*1+ zZv#BxjA+-**}&GChS#_aM<1}gzc(4&_Cm{+@j!&b9^S^W8N8ciGssmq(^WUR%^rUz zh4XM?=3E49)5+R9fW0R92JkLUmMAYQ8-M4ihMCs1=u(94|n4ODm*^+Xz(TIoJyQpbU|d@9Q|kM+8+?>S`}h)rDt_zq1uWpI1?g z8kR`4I!7ObFKC6d<#!Mg-W+b_aFaY3#i=;;Gypk6WOlrdB-P}HM*R_xhB%Rfcg>s& zNV?8YSMs1=8t8yDvu*?7Ln*4s=e36obYxb|2Cfh@eUkSl)!Gj}lqYglfP<@^2X|c_ zyglJD*WeSfsP)of`oB~D*SO`iRT*mZSs&z#z*^L+4zjhRt7U7vtGlRf{hG4UWoK;L zR==X6y54Au>bhd8sJFYTsI{e`Xmc!96zyu8)85e@pA(NZv=o(;MM@(jMJ?^I*51ar za$QxesasiBv?RW@B^HO@LDxkqQ*sVlDKaV5-P2Z9+Qe|0qpkH_u~>b4TO@|DgQXD< zRwKazZ2!U#j!~nW zQIMRlfAJ{myj4a@4?Ed*=K|!h$Aky%U(rbz9sfEf9i_7E3w5SbJ(+Gw&6GC{ehS5l zleY-cba=p1x-`dcpT5emM-NtE^+0Vk4beIF&4U^KUlx*0xBazldxLCmA=`@%P6_@S z-e%qXslq)h?VQSv2|HsA9RHg0osk?k|6-@iaf|`)ia41jbFjq8v%hy` z#LkU`3+-Tp189fBqbv+~c$AZYvN;j$2_Bg!aHd;MF4WWMa?x-ui;=C&3F!!mIT<3( zB2!zf!Bi7My1#@C3p=@C-A z30(Ubudx6uj(7A|BSe&0)zRbU%2czKJ?2OSha-dUd2sbT273D^c zwH6AEah#WiAHre#y9Co{9$cW$?Eh2|$C?Vk{>IgjK_4^CG?@9RV^)G9*CqR9xMqfv z%`EstGto`Dncr~6nvU%>{Zw!I3DE=>xIM5al-dR8q*eYF$GPtBiZ|VFuaD%X^k$i# zy&14)t-_Nt%NpF+zUp9G3ypSWB0g+g6CzG2QUwc~sS(IijTHIYQo-lWIn-x?6G44b zBF-dJ-=|9jI>timeVE`3SCTW3oX#zEh}M%~_~a=lHq$s8J~;~+W|$0~q$jUO>q&Yt z=*T|ZL#dO@TjEW!3ud!esb2S4VI+&33TRh^of#2lIu&Lw@N?%`%YAG{YRuM1*Yanh3`-L~Dtj*wZ3TkkVAW?=c(dSr-n6S^n$=u4iY|Vr)Wo zrPj}IwW;-Ges+CaV~ajfUzWW!tS2Wn=KRP4?1=W*A&QWli)u&NIrv0yIl2#+Eczeo z1V0t2Vi2^*l{40E55KfVUyE=X<$R8EnWa8wND%L2V~?6TO4kmD3!OQp z@;RSTd7u>Aei*m!-c9fN5uehULgTRTGaOp>G~JrE@XLd(`5fgw(VC}6q_pO9IPtWm zVnt<1biBg4jm+JXb*Vxt;OYOBDj6!!0rh%uz!Pc;v+Vxc_ z0W-9^o@h^Rw_B^3;i{;)qb*+46mN_ctyx*KzNj{e(XVOl=;>&0iPhKjHgw0knxe6I zeOI(G+EuhX-X8CY_H=aB*Hl%eWQL}`yQ8V+(r8!Qw6w9K7c)(VxwN)+U9IYE?{3-L z9&ZfCnxkE+s&&iU)Tzv-vuE+LM+rYlmAAxTer*fm!$4n zcinICbfb6Nsyf=6S~i=84Dq0s69!b1%Q1Bwn?*3BjOpzXj;w4u)tx;pZK*?xjRosQ zZ!C4umSMI6jP6>cXT|Ww8kuS52y0bOTyJH%k(k;`*KJsz-14^QZN)6MB`sTZA@m)R zX6rJGvUX|R(%OwnmtZ%PR7o;bnoN}?Q*)E4dCAo2*aEv#=A_>4hFMv9$z#!_b`EPt z?0P?3E7a{p$ZqInf1H>8X-b_{@mPw6)7|v)^0gbnRV8PH&7+}kX>n;;NpbO+;W=%w&fbMFY^(8Y zbK1^;+|%6K)&Mp^-_*Hv-kipg(C!^1twt!KU9skccli3TYQ0>{E94= za}PeH^U8eM$L|>2gHQb`a)Q^S?X<6j7yT`!YvYr^ikys{)c<$NRFuF$luziCH4{na zjHPqdDF2A`HJQFZMqXOJHOd-ekF~~GM!$=S9uuUsK{Jbc^JPdMBWDGVSH{9nQJKz z{r|lo_H1=bt5zQ}Ujcw?BjGp|?eY z`eb%oI)=?oJ-+J2x(b}46xSCy9m|uPE9BQplphfC1y0I85xy?`i|}ErJ8c(oc2VXS zk~P9jLe5s|IqKx!o1d%Ihj*yx2k#asz7RrkR+5~3zG+Gok_C8AO!Q^KvxF7G6~cAG z^}+^Wi?Cg|UHI?9-wNLl=3ovoj>*DB!nMMSgzdtsgxKD7xjTdp2!AAeR``42pM@U@ zb1RmyE4)b9F1$*3qwoRYkA(kQcvyH$sJ{k--+asy`Y#eL5}qSGS9qZ? zCcId9weUva*M;{9pAa4r9u~eM{79ISX5uIimI^C`HNtu!zXWF7R|Mv>zZG&FP(C5#^@(ywI89h0EEld5ULWFCV!uq}D}_5m zf1}7>5#B<=&t1ar3Lg?aMWVib5{vnH;R__{dsXaz7WrM_dn6Y>F3V&V2|r^=ypY28 zE6FekKc|ZQbdk>zE*AZ2k=F^=lPG_ouu0e<>?2X%Ka;sieOY*i=(cDO@M|^GVF5 zdSOiLEn??;s4TZl$ano%-!74N3%@M-uZet@@SCFFC-TF>$3*`Vk)Ia+QuKV^mG%Bk zc!Wfpe-!?iL>wQ9oStdyLE$*zG~sE&xx$6QWx{pB^Mp~M!ohWtCe+s<$hglmPh!Y1Lx!b^m`!rj6>!dry53-1*OcGUkLk! zuL<7}z9T#?^znLw^?+}lHFJb{LcW_t`>Dbb;XENWkZ*v|uCJS*zHWlgiT*|5D?;8gGXERGcZA1-$3FM_;B*;myL^g?9?SCA?Sopzsml6T$<+ zp9z01d`|cq;VZ%;!Z(C(3y%x+eIVlfNMs-Hiy-qSQsf9Be{(~5zOY=lL|84X5$gLs zAY1cYOR z6NIybvxR307YbJi*9ueb|M=S@*0)or@9!Y*5&0J3?ZR&ezb$+~_>fTF=b`)$Mb`Iq zkoA2X_?qb75WXWkF8o0FvCuE~WdY$x;V2=dgYw~FguXw6f82WM{UA(YUztVXKBJh# zebIapnaWArukm2}u^nlmT3ue>_u)hPg`a%tLG2&@_M?&@_qyL>HpW@|F0Zx_^rfaLHhd{34cMn#mVyjLZY0mzfkH&`33X`xtxTbYLRP5 z_`5*lO(gto6Zr}f{`ZJ{Gl_cc6L}xWeu;En*47hk0DHO&o81&1>-VS#AHu6hLwC1| z;PHBd%E;j3s?=v^srF%>ntfIl{p@VGdXkUD_!Mop3`3u%4VNS7f=|$f%P{C7nWHh@ z(7U<5rM;;G9ih|FhK8>AR#V<+@Kv%`jCMuaH^-&7OpZ@#T3g!Vu19pYio`nF+T!@W zP{(CTHFZVXkg1|}O(fdW)78?@+XJ_M$HC#nG{lotb8v2Y58T@6V=6wG54Sq{NXjnWE*C3DCII+C-+@_o{U#U%C7$@`aWPP0LL;S%PpBcM{>yMq| z&G!V>9RDwH4>#YfDf#X~5L`Fz;pXF-@y6GT_`=ZfWL$21{He9K-mzHQ-ad5wJ%W5* zf4kr>2wfN_iX{ELjI`HZHH^c>$7hyaf46$#!&Z^>_hE{^pL|MuCsX`A>WPofcir|* zMsSSJJx;>k76u}RYa5S*H@>IguMcAvMn1ON^~e7)-7<6$%U6p3x4DO##EY>*@@*WA z{dkyq=OdrD-W7}SyEQ1na2Uer*1I~z-{p87&AH|tFzaJ^iocU9%$yCwiY+$j@1hic z&%j?f?C#?>q2^u2x~3e2(t= zyF&aGL&xI}r(q3ZjkpK>@w_f2Uv8OM`>FYEmVB;$KJp!K1(5af*n@oD_8#`Mm)|0} z@$E%E>@A(T5I#=AU#TmAFzbVK_bw`CbFrb|RA3fP`s4g!o$g+Rq?&z(`K21uJY0YL R?!lX{W|dM8x<*gF{|n6JVi5oU literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_hal_sd.d b/build/stm32f7xx_hal_sd.d new file mode 100644 index 0000000..760d4ac --- /dev/null +++ b/build/stm32f7xx_hal_sd.d @@ -0,0 +1,68 @@ +build/stm32f7xx_hal_sd.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/build/stm32f7xx_hal_sd.lst b/build/stm32f7xx_hal_sd.lst new file mode 100644 index 0000000..9edc03c --- /dev/null +++ b/build/stm32f7xx_hal_sd.lst @@ -0,0 +1,12948 @@ +ARM GAS /tmp/ccMMu31U.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_hal_sd.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c" + 19 .section .text.SD_DMATransmitCplt,"ax",%progbits + 20 .align 1 + 21 .syntax unified + 22 .thumb + 23 .thumb_func + 25 SD_DMATransmitCplt: + 26 .LVL0: + 27 .LFB168: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @file stm32f7xx_hal_sd.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief SD card HAL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * functionalities of the Secure Digital (SD) peripheral: + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * + IO operation functions + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * + Peripheral Control functions + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * + Peripheral State functions + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ****************************************************************************** + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @attention + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * Copyright (c) 2017 STMicroelectronics. + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * All rights reserved. + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * This software is licensed under terms that can be found in the LICENSE file + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * in the root directory of this software component. + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ****************************************************************************** + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** @verbatim + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ============================================================================== + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ##### How to use this driver ##### + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ============================================================================== + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** [..] + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** This driver implements a high level communication layer for read and write from/to + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** the user in HAL_SD_MspInit() function (MSP layer). + ARM GAS /tmp/ccMMu31U.s page 2 + + + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Basically, the MSP layer configuration should be the same as we provide in the + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** examples. + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** You can easily tailor this configuration according to hardware resources. + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** [..] + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** This driver is a generic layered driver for SDMMC memories which uses the HAL + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC driver functions to interface with SD and uSD cards devices. + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** It is used as follows: + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (#)Initialize the SDMMC low level resources by implementing the HAL_SD_MspInit() API: + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (##) SDMMC pins configuration for SD card + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENAB + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** and according to your pin assignment; + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (##) DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA() + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** and HAL_SD_WriteBlocks_DMA() APIs). + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (##) NVIC configuration if you need to use interrupt process when using DMA transfer. + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+++) Configure the SDMMC and DMA interrupt priorities using functions + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ() + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT() + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** and __HAL_SD_DISABLE_IT() inside the communication process. + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT() + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** and __HAL_SD_CLEAR_IT() + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT() + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** and HAL_SD_WriteBlocks_IT() APIs). + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority(); + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT() + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** and __HAL_SD_DISABLE_IT() inside the communication process. + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT() + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** and __HAL_SD_CLEAR_IT() + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (#) At this stage, you can perform SD read/write/erase operations after SD card initialization + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *** SD Card Initialization and configuration *** + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ================================================ + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** [..] + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** To initialize the SD Card, use the HAL_SD_Init() function. It Initializes + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data tra + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** This function provide the following operations: + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (#) Apply the SD Card initialization process at 400KHz and check the SD Card + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** type (Standard Capacity or High Capacity). You can change or adapt this + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** frequency by adjusting the "ClockDiv" field. + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** The SD Card frequency (SDMMC_CK) is computed as follows: + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_CK = SDMMCCLK / (ClockDiv + 2) + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** In initialization mode and according to the SD Card standard, + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** make sure that the SDMMC_CK frequency doesn't exceed 400KHz. + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** This phase of initialization is done through SDMMC_Init() and + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_PowerState_ON() SDMMC low level APIs. + ARM GAS /tmp/ccMMu31U.s page 3 + + + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (#) Initialize the SD card. The API used is HAL_SD_InitCard(). + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** This phase allows the card initialization and identification + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** and check the SD Card type (Standard Capacity or High Capacity) + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** The initialization flow is compatible with SD standard. + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** of plug-off plug-in. + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (#) Configure the SD Card Data transfer frequency. You can change or adapt this + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** frequency by adjusting the "ClockDiv" field. + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** In transfer mode and according to the SD Card standard, make sure that the + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch. + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** To be able to use a frequency higher than 24MHz, you should use the SDMMC + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** peripheral in bypass mode. Refer to the corresponding reference manual + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** for more details. + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (#) Select the corresponding SD Card according to the address read with the step 2. + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (#) Configure the SD Card in wide bus mode: 4-bits data. + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *** SD Card Read operation *** + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ============================== + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** [..] + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** This function support only 512-bytes block length (the block size should be + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** chosen as 512 bytes). + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** You can choose either one block read operation or multiple block read operation + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** by adjusting the "NumberOfBlocks" parameter. + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** After this, you have to ensure that the transfer is done correctly. The check is done + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** through HAL_SD_GetCardState() function for SD card state. + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA(). + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** This function support only 512-bytes block length (the block size should be + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** chosen as 512 bytes). + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** You can choose either one block read operation or multiple block read operation + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** by adjusting the "NumberOfBlocks" parameter. + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** After this, you have to ensure that the transfer is done correctly. The check is done + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** through HAL_SD_GetCardState() function for SD card state. + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** You could also check the DMA transfer process through the SD Rx interrupt event. + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT(). + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** This function support only 512-bytes block length (the block size should be + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** chosen as 512 bytes). + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** You can choose either one block read operation or multiple block read operation + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** by adjusting the "NumberOfBlocks" parameter. + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** After this, you have to ensure that the transfer is done correctly. The check is done + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** through HAL_SD_GetCardState() function for SD card state. + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** You could also check the IT transfer process through the SD Rx interrupt event. + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *** SD Card Write operation *** + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** =============================== + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** [..] + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** This function support only 512-bytes block length (the block size should be + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** chosen as 512 bytes). + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** You can choose either one block read operation or multiple block read operation + ARM GAS /tmp/ccMMu31U.s page 4 + + + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** by adjusting the "NumberOfBlocks" parameter. + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** After this, you have to ensure that the transfer is done correctly. The check is done + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** through HAL_SD_GetCardState() function for SD card state. + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA(). + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** This function support only 512-bytes block length (the block size should be + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** chosen as 512 bytes). + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** You can choose either one block read operation or multiple block read operation + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** by adjusting the "NumberOfBlocks" parameter. + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** After this, you have to ensure that the transfer is done correctly. The check is done + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** through HAL_SD_GetCardState() function for SD card state. + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** You could also check the DMA transfer process through the SD Tx interrupt event. + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT(). + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** This function support only 512-bytes block length (the block size should be + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** chosen as 512 bytes). + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** You can choose either one block read operation or multiple block read operation + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** by adjusting the "NumberOfBlocks" parameter. + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** After this, you have to ensure that the transfer is done correctly. The check is done + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** through HAL_SD_GetCardState() function for SD card state. + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** You could also check the IT transfer process through the SD Tx interrupt event. + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *** SD card status *** + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ====================== + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** [..] + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) The SD Status contains status bits that are related to the SD Memory + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus(). + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *** SD card information *** + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** =========================== + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** [..] + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) To get SD card information, you can use the function HAL_SD_GetCardInfo(). + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** It returns useful information about the SD card such as block size, card type, + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** block number ... + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *** SD card CSD register *** + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ============================ + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register. + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Some of the CSD parameters are useful for card initialization and identification. + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *** SD card CID register *** + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ============================ + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register. + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Some of the CSD parameters are useful for card initialization and identification. + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *** SD HAL driver macros list *** + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ================================== + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** [..] + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Below the list of most used macros in SD HAL driver. + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) __HAL_SD_ENABLE : Enable the SD device + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) __HAL_SD_DISABLE : Disable the SD device + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) __HAL_SD_DMA_ENABLE: Enable the SDMMC DMA transfer + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) __HAL_SD_DMA_DISABLE: Disable the SDMMC DMA transfer + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not + ARM GAS /tmp/ccMMu31U.s page 5 + + + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (@) You can refer to the SD HAL driver header file for more useful macros + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *** Callback registration *** + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ============================================= + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** [..] + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1 + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** allows the user to configure dynamically the driver callbacks. + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Use Functions HAL_SD_RegisterCallback() to register a user callback, + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** it allows to register following callbacks: + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) TxCpltCallback : callback when a transmission transfer is completed. + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) RxCpltCallback : callback when a reception transfer is completed. + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) ErrorCallback : callback when error occurs. + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) AbortCpltCallback : callback when abort is completed. + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) MspInitCallback : SD MspInit. + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) MspDeInitCallback : SD MspDeInit. + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** This function takes as parameters the HAL peripheral handle, the Callback ID + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** and a pointer to the user callback function. + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Use function HAL_SD_UnRegisterCallback() to reset a callback to the default + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** weak (surcharged) function. It allows to reset following callbacks: + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) TxCpltCallback : callback when a transmission transfer is completed. + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) RxCpltCallback : callback when a reception transfer is completed. + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) ErrorCallback : callback when error occurs. + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) AbortCpltCallback : callback when abort is completed. + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) MspInitCallback : SD MspInit. + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (+) MspDeInitCallback : SD MspDeInit. + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** This function) takes as parameters the HAL peripheral handle and the Callback ID. + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** all callbacks are reset to the corresponding legacy weak (surcharged) functions. + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Exception done for MspInit and MspDeInit callbacks that are respectively + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** reset to the legacy weak (surcharged) functions in the HAL_SD_Init + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** and HAL_SD_DeInit only when these callbacks are null (not registered beforehand). + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Callbacks can be registered/unregistered in READY state only. + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** during the Init/DeInit. + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** In that case first register the MspInit/MspDeInit user callbacks + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** using HAL_SD_RegisterCallback before calling HAL_SD_DeInit + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** or HAL_SD_Init function. + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** not defined, the callback registering feature is not available + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** and weak (surcharged) callbacks are used. + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** @endverbatim + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ****************************************************************************** + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Includes ------------------------------------------------------------------*/ + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #include "stm32f7xx_hal.h" + ARM GAS /tmp/ccMMu31U.s page 6 + + + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined(SDMMC1) + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** @addtogroup STM32F7xx_HAL_Driver + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @{ + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** @addtogroup SD + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @{ + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #ifdef HAL_SD_MODULE_ENABLED + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Private typedef -----------------------------------------------------------*/ + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Private define ------------------------------------------------------------*/ + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** @addtogroup SD_Private_Defines + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @{ + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @} + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Private macro -------------------------------------------------------------*/ + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Private variables ---------------------------------------------------------*/ + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Private function prototypes -----------------------------------------------*/ + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Private functions ---------------------------------------------------------*/ + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** @defgroup SD_Private_Functions SD Private Functions + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @{ + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_InitCard(SD_HandleTypeDef *hsd); + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_PowerON(SD_HandleTypeDef *hsd); + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus); + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd); + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd); + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_PowerOFF(SD_HandleTypeDef *hsd); + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_Write_IT(SD_HandleTypeDef *hsd); + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_Read_IT(SD_HandleTypeDef *hsd); + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma); + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMAError(DMA_HandleTypeDef *hdma); + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMATxAbort(DMA_HandleTypeDef *hdma); + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMARxAbort(DMA_HandleTypeDef *hdma); + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @} + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Exported functions --------------------------------------------------------*/ + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** @addtogroup SD_Exported_Functions + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @{ + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** @addtogroup SD_Exported_Functions_Group1 + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Initialization and de-initialization functions + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * + ARM GAS /tmp/ccMMu31U.s page 7 + + + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** @verbatim + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ============================================================================== + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ##### Initialization and de-initialization functions ##### + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ============================================================================== + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** [..] + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** This section provides functions allowing to initialize/de-initialize the SD + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** card device to be ready for use. + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** @endverbatim + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @{ + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Initializes the SD according to the specified parameters in the + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_HandleTypeDef and create the associated handle. + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to the SD handle + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval HAL status + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Check the SD handle allocation */ + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd == NULL) + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Check the parameters */ + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance)); + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** assert_param(IS_SDMMC_CLOCK_EDGE(hsd->Init.ClockEdge)); + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** assert_param(IS_SDMMC_CLOCK_BYPASS(hsd->Init.ClockBypass)); + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave)); + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide)); + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl)); + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv)); + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->State == HAL_SD_STATE_RESET) + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Allocate lock resource and initialize it */ + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Lock = HAL_UNLOCKED; + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Reset Callback pointers in HAL_SD_STATE_RESET only */ + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->TxCpltCallback = HAL_SD_TxCpltCallback; + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->RxCpltCallback = HAL_SD_RxCpltCallback; + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCallback = HAL_SD_ErrorCallback; + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->AbortCpltCallback = HAL_SD_AbortCallback; + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->MspInitCallback == NULL) + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->MspInitCallback = HAL_SD_MspInit; + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Init the low level hardware */ + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->MspInitCallback(hsd); + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_MspInit(hsd); + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + ARM GAS /tmp/ccMMu31U.s page 8 + + + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_BUSY; + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Initialize the Card parameters */ + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if (HAL_SD_InitCard(hsd) != HAL_OK) + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Initialize the error code */ + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode = HAL_SD_ERROR_NONE; + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Initialize the SD operation */ + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Initialize the SD state */ + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_OK; + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Initializes the SD Card. + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @note This function initializes the SD card. It could be used when a card + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** re-initialization is needed. + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval HAL status + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef status; + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_InitTypeDef Init; + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Default SDMMC peripheral configuration for SD card initialization */ + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.BusWide = SDMMC_BUS_WIDE_1B; + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockDiv = SDMMC_INIT_CLK_DIV; + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Initialize SDMMC peripheral interface with default configuration */ + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = SDMMC_Init(hsd->Instance, Init); + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(status != HAL_OK) + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Disable SDMMC Clock */ + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_DISABLE(hsd); + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Set Power State to ON */ + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_PowerState_ON(hsd->Instance); + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Enable SDMMC Clock */ + ARM GAS /tmp/ccMMu31U.s page 9 + + + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_ENABLE(hsd); + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Required power up waiting time before starting the SD initialization sequence */ + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_Delay(2); + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Identify card operating voltage */ + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SD_PowerON(hsd); + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Card initialization */ + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SD_InitCard(hsd); + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Set Block Size for Card */ + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_OK; + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief De-Initializes the SD card. + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval HAL status + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Check the SD handle allocation */ + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd == NULL) + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Check the parameters */ + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance)); + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_BUSY; + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Set SD power state to off */ + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_PowerOFF(hsd); + ARM GAS /tmp/ccMMu31U.s page 10 + + + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->MspDeInitCallback == NULL) + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->MspDeInitCallback = HAL_SD_MspDeInit; + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* DeInit the low level hardware */ + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->MspDeInitCallback(hsd); + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* De-Initialize the MSP layer */ + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_MspDeInit(hsd); + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode = HAL_SD_ERROR_NONE; + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_RESET; + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_OK; + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Initializes the SD MSP. + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval None + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Prevent unused argument(s) compilation warning */ + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** UNUSED(hsd); + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* NOTE : This function should not be modified, when the callback is needed, + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** the HAL_SD_MspInit could be implemented in the user file + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief De-Initialize SD MSP. + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval None + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Prevent unused argument(s) compilation warning */ + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** UNUSED(hsd); + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* NOTE : This function should not be modified, when the callback is needed, + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** the HAL_SD_MspDeInit could be implemented in the user file + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @} + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** @addtogroup SD_Exported_Functions_Group2 + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Data transfer functions + ARM GAS /tmp/ccMMu31U.s page 11 + + + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** @verbatim + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ============================================================================== + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ##### IO operation functions ##### + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ============================================================================== + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** [..] + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** This subsection provides a set of functions allowing to manage the data + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** transfer from/to SD card. + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** @endverbatim + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @{ + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Reads block(s) from a specified address in a card. The Data transfer + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * is managed by polling mode. + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @note This API should be followed by a check on the card state through + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * HAL_SD_GetCardState(). + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param pData: pointer to the buffer that will contain the received data + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param BlockAdd: Block Address from where data is to be read + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param NumberOfBlocks: Number of SD blocks to read + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param Timeout: Specify timeout value + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval HAL status + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint3 + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t tickstart = HAL_GetTick(); + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t count, data, dataremaining; + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t add = BlockAdd; + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint8_t *tempbuff = pData; + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(NULL == pData) + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->State == HAL_SD_STATE_READY) + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode = HAL_SD_ERROR_NONE; + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_BUSY; + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Initialize data control register */ + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Instance->DCTRL = 0U; + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + ARM GAS /tmp/ccMMu31U.s page 12 + + + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** add *= 512U; + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Configure the SD DPSM (Data Path State Machine) */ + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataTimeOut = SDMMC_DATATIMEOUT; + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = NumberOfBlocks * BLOCKSIZE; + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Read block(s) in polling mode */ + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(NumberOfBlocks > 1U) + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK; + 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Read Multi Block command */ + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK; + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Read Single Block command */ + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Poll on SDMMC flags */ + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining = config.DataLength; + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining > 0U)) + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Read data from SDMMC Rx FIFO */ + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** for(count = 0U; count < 8U; count++) + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** data = SDMMC_ReadFIFO(hsd->Instance); + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tempbuff = (uint8_t)(data & 0xFFU); + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + ARM GAS /tmp/ccMMu31U.s page 13 + + + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State= HAL_SD_STATE_READY; + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_TIMEOUT; + 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send stop transmission command in case of multiblock read */ + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->SdCard.CardType != CARD_SECURED) + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send stop transmission command */ + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Get error state */ + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ + ARM GAS /tmp/ccMMu31U.s page 14 + + + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Nothing to do */ + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Empty FIFO if there is still any data */ + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (dataremaining > 0U)) + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** data = SDMMC_ReadFIFO(hsd->Instance); + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tempbuff = (uint8_t)(data & 0xFFU); + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State= HAL_SD_STATE_READY; + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_OK; + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_BUSY; + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Allows to write block(s) to a specified address in a card. The Data + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * transfer is managed by polling mode. + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @note This API should be followed by a check on the card state through + ARM GAS /tmp/ccMMu31U.s page 15 + + + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * HAL_SD_GetCardState(). + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param pData: pointer to the buffer that will contain the data to transmit + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param BlockAdd: Block Address where data will be written + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param NumberOfBlocks: Number of SD blocks to write + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param Timeout: Specify timeout value + 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval HAL status + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; + 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t tickstart = HAL_GetTick(); + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t count, data, dataremaining; + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t add = BlockAdd; + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint8_t *tempbuff = pData; + 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(NULL == pData) + 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->State == HAL_SD_STATE_READY) + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode = HAL_SD_ERROR_NONE; + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_BUSY; + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Initialize data control register */ + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Instance->DCTRL = 0U; + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** add *= 512U; + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Configure the SD DPSM (Data Path State Machine) */ + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataTimeOut = SDMMC_DATATIMEOUT; + 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = NumberOfBlocks * BLOCKSIZE; + 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); + 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Write Blocks in Polling mode */ + 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(NumberOfBlocks > 1U) + 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK; + 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + ARM GAS /tmp/ccMMu31U.s page 16 + + + 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Write Multi Block command */ + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); + 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK; + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Write Single Block command */ + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Write block(s) in polling mode */ + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining = config.DataLength; + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | + 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining > 0U)) + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Write data to SDMMC Tx FIFO */ + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** for(count = 0U; count < 8U; count++) + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** data = (uint32_t)(*tempbuff); + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** data |= ((uint32_t)(*tempbuff) << 8U); + 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** data |= ((uint32_t)(*tempbuff) << 16U); + 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** data |= ((uint32_t)(*tempbuff) << 24U); + 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_WriteFIFO(hsd->Instance, &data); + 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ + 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_TIMEOUT; + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send stop transmission command in case of multiblock write */ + ARM GAS /tmp/ccMMu31U.s page 17 + + + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->SdCard.CardType != CARD_SECURED) + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send stop transmission command */ + 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Get error state */ + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ + 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR)) + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Nothing to do */ + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ + 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_OK; + ARM GAS /tmp/ccMMu31U.s page 18 + + + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_BUSY; + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** + 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Reads block(s) from a specified address in a card. The Data transfer + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * is managed in interrupt mode. + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @note This API should be followed by a check on the card state through + 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * HAL_SD_GetCardState(). + 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @note You could also check the IT transfer process through the SD Rx + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * interrupt event. + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle + 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param pData: Pointer to the buffer that will contain the received data + 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param BlockAdd: Block Address from where data is to be read + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param NumberOfBlocks: Number of blocks to read. + 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval HAL status + 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, ui + 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; + 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t add = BlockAdd; + 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(NULL == pData) + 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->State == HAL_SD_STATE_READY) + 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode = HAL_SD_ERROR_NONE; + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_BUSY; + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Initialize data control register */ + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Instance->DCTRL = 0U; + 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->pRxBuffPtr = pData; + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; + 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DA + 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** add *= 512U; +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + ARM GAS /tmp/ccMMu31U.s page 19 + + +1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Configure the SD DPSM (Data Path State Machine) */ +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataTimeOut = SDMMC_DATATIMEOUT; +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = BLOCKSIZE * NumberOfBlocks; +1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; +1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); +1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Read Blocks in IT mode */ +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(NumberOfBlocks > 1U) +1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT); +1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Read Multi Block command */ +1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); +1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT); +1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Read Single Block command */ +1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ +1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; +1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; +1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_OK; +1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_BUSY; +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Writes block(s) to a specified address in a card. The Data transfer +1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * is managed in interrupt mode. +1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @note This API should be followed by a check on the card state through +1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * HAL_SD_GetCardState(). +1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @note You could also check the IT transfer process through the SD Tx +1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * interrupt event. +1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle +1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param pData: Pointer to the buffer that will contain the data to transmit +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param BlockAdd: Block Address where data will be written +1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param NumberOfBlocks: Number of blocks to write +1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval HAL status +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, u + ARM GAS /tmp/ccMMu31U.s page 20 + + +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; +1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; +1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t add = BlockAdd; +1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(NULL == pData) +1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_PARAM; +1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->State == HAL_SD_STATE_READY) +1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode = HAL_SD_ERROR_NONE; +1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) +1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; +1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_BUSY; +1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Initialize data control register */ +1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Instance->DCTRL = 0U; +1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->pTxBuffPtr = pData; +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; +1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Enable transfer interrupts */ +1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_D +1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->SdCard.CardType != CARD_SDHC_SDXC) +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** add *= 512U; +1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Write Blocks in Polling mode */ +1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(NumberOfBlocks > 1U) +1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT); +1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Write Multi Block command */ +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); +1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT); +1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Write Single Block command */ +1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + ARM GAS /tmp/ccMMu31U.s page 21 + + +1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; +1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Configure the SD DPSM (Data Path State Machine) */ +1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataTimeOut = SDMMC_DATATIMEOUT; +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = BLOCKSIZE * NumberOfBlocks; +1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_OK; +1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_BUSY; +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Reads block(s) from a specified address in a card. The Data transfer +1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * is managed by DMA mode. +1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @note This API should be followed by a check on the card state through +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * HAL_SD_GetCardState(). +1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @note You could also check the DMA transfer process through the SD Rx +1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * interrupt event. +1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer SD handle +1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param pData: Pointer to the buffer that will contain the received data +1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param BlockAdd: Block Address from where data is to be read +1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param NumberOfBlocks: Number of blocks to read. +1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval HAL status +1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, u +1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; +1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; +1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t add = BlockAdd; +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(NULL == pData) +1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_PARAM; +1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->State == HAL_SD_STATE_READY) +1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode = HAL_SD_ERROR_NONE; +1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) +1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; +1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + ARM GAS /tmp/ccMMu31U.s page 22 + + +1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_BUSY; +1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Initialize data control register */ +1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Instance->DCTRL = 0U; +1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DA +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Set the DMA transfer complete callback */ +1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt; +1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Set the DMA error callback */ +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->hdmarx->XferErrorCallback = SD_DMAError; +1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Set the DMA Abort callback */ +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->hdmarx->XferAbortCallback = NULL; +1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Force DMA Direction */ +1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY; +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** MODIFY_REG(hsd->hdmarx->Instance->CR, DMA_SxCR_DIR, hsd->hdmarx->Init.Direction); +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Enable the DMA Channel */ +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BL +1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_DMA; +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Enable SD DMA transfer */ +1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_DMA_ENABLE(hsd); +1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->SdCard.CardType != CARD_SDHC_SDXC) +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** add *= 512U; +1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Configure the SD DPSM (Data Path State Machine) */ +1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataTimeOut = SDMMC_DATATIMEOUT; +1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = BLOCKSIZE * NumberOfBlocks; +1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; +1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; +1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; +1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; +1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); +1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Read Blocks in DMA mode */ +1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(NumberOfBlocks > 1U) +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); +1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Read Multi Block command */ +1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); +1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else + ARM GAS /tmp/ccMMu31U.s page 23 + + +1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA); +1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Read Single Block command */ +1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); +1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; +1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_OK; +1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_BUSY; +1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Writes block(s) to a specified address in a card. The Data transfer +1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * is managed by DMA mode. +1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @note This API should be followed by a check on the card state through +1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * HAL_SD_GetCardState(). +1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @note You could also check the DMA transfer process through the SD Tx +1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * interrupt event. +1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle +1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param pData: Pointer to the buffer that will contain the data to transmit +1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param BlockAdd: Block Address where data will be written +1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param NumberOfBlocks: Number of blocks to write +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval HAL status +1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; +1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t add = BlockAdd; +1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(NULL == pData) +1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_PARAM; +1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->State == HAL_SD_STATE_READY) +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode = HAL_SD_ERROR_NONE; +1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) +1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + ARM GAS /tmp/ccMMu31U.s page 24 + + +1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_BUSY; +1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Initialize data control register */ +1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Instance->DCTRL = 0U; +1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Enable SD Error interrupts */ +1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR)); +1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Set the DMA transfer complete callback */ +1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt; +1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Set the DMA error callback */ +1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->hdmatx->XferErrorCallback = SD_DMAError; +1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Set the DMA Abort callback */ +1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->hdmatx->XferAbortCallback = NULL; +1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->SdCard.CardType != CARD_SDHC_SDXC) +1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** add *= 512U; +1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Write Blocks in Polling mode */ +1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(NumberOfBlocks > 1U) +1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); +1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Write Multi Block command */ +1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); +1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA); +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Write Single Block command */ +1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ +1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; +1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; +1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Enable SDMMC DMA transfer */ +1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_DMA_ENABLE(hsd); +1338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Force DMA Direction */ +1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH; +1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** MODIFY_REG(hsd->hdmatx->Instance->CR, DMA_SxCR_DIR, hsd->hdmatx->Init.Direction); +1342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + ARM GAS /tmp/ccMMu31U.s page 25 + + +1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Enable the DMA Channel */ +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BL +1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR)); +1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_DMA; +1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; +1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Configure the SD DPSM (Data Path State Machine) */ +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataTimeOut = SDMMC_DATATIMEOUT; +1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = BLOCKSIZE * NumberOfBlocks; +1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; +1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; +1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; +1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; +1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); +1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_OK; +1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_BUSY; +1370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Erases the specified memory area of the given SD card. +1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @note This API should be followed by a check on the card state through +1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * HAL_SD_GetCardState(). +1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle +1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param BlockStartAdd: Start Block address +1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param BlockEndAdd: End Block address +1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval HAL status +1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd) +1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; +1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t start_add = BlockStartAdd; +1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t end_add = BlockEndAdd; +1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->State == HAL_SD_STATE_READY) +1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode = HAL_SD_ERROR_NONE; +1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(end_add < start_add) +1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_PARAM; +1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(end_add > (hsd->SdCard.LogBlockNbr)) +1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + ARM GAS /tmp/ccMMu31U.s page 26 + + +1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; +1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_BUSY; +1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Check if the card command class supports erase command */ +1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U) +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ +1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; +1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) +1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED; +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Get start and end block for high capacity cards */ +1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->SdCard.CardType != CARD_SDHC_SDXC) +1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** start_add *= 512U; +1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** end_add *= 512U; +1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->SdCard.CardType != CARD_SECURED) +1434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send CMD32 SD_ERASE_GRP_START with argument as addr */ +1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add); +1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ +1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; +1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send CMD33 SD_ERASE_GRP_END with argument as addr */ +1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add); +1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +1449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; +1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + ARM GAS /tmp/ccMMu31U.s page 27 + + +1457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send CMD38 ERASE */ +1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdErase(hsd->Instance); +1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ +1463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_OK; +1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +1474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_BUSY; +1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief This function handles SD card interrupt request. +1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle +1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval None +1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) +1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; +1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t context = hsd->Context; +1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Check for SDMMC interrupt flags */ +1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) +1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_Read_IT(hsd); +1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET) +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND); +1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ +1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\ +1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_IT_RXFIFOHF); +1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Instance->DCTRL &= ~(SDMMC_DCTRL_DTEN); +1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((context & SD_CONTEXT_IT) != 0U) +1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPL +1508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdStopTransfer(hsd->Instance); +1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +1511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; +1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + ARM GAS /tmp/ccMMu31U.s page 28 + + +1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCallback(hsd); +1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else +1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_ErrorCallback(hsd); +1517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ +1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); +1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; +1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_B +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->RxCpltCallback(hsd); +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else +1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_RxCpltCallback(hsd); +1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->TxCpltCallback(hsd); +1538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else +1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_TxCpltCallback(hsd); +1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +1541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if((context & SD_CONTEXT_DMA) != 0U) +1544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) +1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdStopTransfer(hsd->Instance); +1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +1549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; +1551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +1552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCallback(hsd); +1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else +1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_ErrorCallback(hsd); +1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +1556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_B +1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Disable the DMA transfer for transmit request by setting the DMAEN bit +1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** in the SD DCTRL register */ +1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +1565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->TxCpltCallback(hsd); +1568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else +1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_TxCpltCallback(hsd); +1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + ARM GAS /tmp/ccMMu31U.s page 29 + + +1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Nothing to do */ +1576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0 +1580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_Write_IT(hsd); +1582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | S +1585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Set Error code */ +1587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL) != RESET) +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; +1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT) != RESET) +1592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR) != RESET) +1596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; +1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR) != RESET) +1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; +1602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear All flags */ +1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); +1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Disable all interrupts */ +1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ +1609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); +1610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); +1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((context & SD_CONTEXT_IT) != 0U) +1614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Set the SD state to ready to be able to start again the process */ +1616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +1617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +1619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCallback(hsd); +1620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else +1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_ErrorCallback(hsd); +1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +1623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if((context & SD_CONTEXT_DMA) != 0U) +1625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Abort the SD DMA channel */ +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE + ARM GAS /tmp/ccMMu31U.s page 30 + + +1628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Set the DMA Tx abort callback */ +1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; +1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Abort DMA in IT mode */ +1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) +1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_DMATxAbort(hsd->hdmatx); +1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTI +1638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Set the DMA Rx abort callback */ +1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; +1641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Abort DMA in IT mode */ +1642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) +1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_DMARxAbort(hsd->hdmarx); +1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +1648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode = HAL_SD_ERROR_NONE; +1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +1651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; +1652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->AbortCpltCallback(hsd); +1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else +1655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_AbortCallback(hsd); +1656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +1657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +1660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Nothing to do */ +1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Nothing to do */ +1667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief return the SD state +1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to sd handle +1673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval HAL state +1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) +1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return hsd->State; +1678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +1681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Return the SD error code +1682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd : Pointer to a SD_HandleTypeDef structure that contains +1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * the configuration information. +1684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval SD Error Code + ARM GAS /tmp/ccMMu31U.s page 31 + + +1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd) +1687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return hsd->ErrorCode; +1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Tx Transfer completed callbacks +1693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle +1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval None +1695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) +1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Prevent unused argument(s) compilation warning */ +1699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** UNUSED(hsd); +1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* NOTE : This function should not be modified, when the callback is needed, +1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** the HAL_SD_TxCpltCallback can be implemented in the user file +1703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +1707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Rx Transfer completed callbacks +1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer SD handle +1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval None +1710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd) +1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Prevent unused argument(s) compilation warning */ +1714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** UNUSED(hsd); +1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* NOTE : This function should not be modified, when the callback is needed, +1717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** the HAL_SD_RxCpltCallback can be implemented in the user file +1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief SD error callbacks +1723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer SD handle +1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval None +1725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd) +1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Prevent unused argument(s) compilation warning */ +1729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** UNUSED(hsd); +1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* NOTE : This function should not be modified, when the callback is needed, +1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** the HAL_SD_ErrorCallback can be implemented in the user file +1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief SD Abort callbacks +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer SD handle +1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval None +1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) + ARM GAS /tmp/ccMMu31U.s page 32 + + +1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Prevent unused argument(s) compilation warning */ +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** UNUSED(hsd); +1745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* NOTE : This function should not be modified, when the callback is needed, +1747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** the HAL_SD_AbortCallback can be implemented in the user file +1748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +1752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +1753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Register a User SD Callback +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * To be used instead of the weak (surcharged) predefined callback +1755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd : SD handle +1756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param CallbackID : ID of the callback to be registered +1757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * This parameter can be one of the following values: +1758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID +1759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID +1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID +1761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID +1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID +1763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID +1764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param pCallback : pointer to the Callback function +1765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval status +1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackI +1768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef status = HAL_OK; +1770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(pCallback == NULL) +1772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Update the error code */ +1774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; +1775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +1776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Process locked */ +1779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_LOCK(hsd); +1780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->State == HAL_SD_STATE_READY) +1782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** switch (CallbackID) +1784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** case HAL_SD_TX_CPLT_CB_ID : +1786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->TxCpltCallback = pCallback; +1787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** case HAL_SD_RX_CPLT_CB_ID : +1789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->RxCpltCallback = pCallback; +1790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** case HAL_SD_ERROR_CB_ID : +1792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCallback = pCallback; +1793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** case HAL_SD_ABORT_CB_ID : +1795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->AbortCpltCallback = pCallback; +1796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** case HAL_SD_MSP_INIT_CB_ID : +1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->MspInitCallback = pCallback; + ARM GAS /tmp/ccMMu31U.s page 33 + + +1799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** case HAL_SD_MSP_DEINIT_CB_ID : +1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->MspDeInitCallback = pCallback; +1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** default : +1804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Update the error code */ +1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; +1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* update return status */ +1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if (hsd->State == HAL_SD_STATE_RESET) +1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** switch (CallbackID) +1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** case HAL_SD_MSP_INIT_CB_ID : +1816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->MspInitCallback = pCallback; +1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** case HAL_SD_MSP_DEINIT_CB_ID : +1819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->MspDeInitCallback = pCallback; +1820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** default : +1822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Update the error code */ +1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; +1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* update return status */ +1825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; +1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Update the error code */ +1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; +1833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* update return status */ +1834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; +1835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Release Lock */ +1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_UNLOCK(hsd); +1839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return status; +1840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +1843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Unregister a User SD Callback +1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * SD Callback is redirected to the weak (surcharged) predefined callback +1845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd : SD handle +1846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param CallbackID : ID of the callback to be unregistered +1847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * This parameter can be one of the following values: +1848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID +1849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID +1850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID +1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID +1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID +1853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID +1854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval status +1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ + ARM GAS /tmp/ccMMu31U.s page 34 + + +1856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef Callbac +1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef status = HAL_OK; +1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Process locked */ +1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_LOCK(hsd); +1862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->State == HAL_SD_STATE_READY) +1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** switch (CallbackID) +1866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** case HAL_SD_TX_CPLT_CB_ID : +1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->TxCpltCallback = HAL_SD_TxCpltCallback; +1869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** case HAL_SD_RX_CPLT_CB_ID : +1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->RxCpltCallback = HAL_SD_RxCpltCallback; +1872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** case HAL_SD_ERROR_CB_ID : +1874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCallback = HAL_SD_ErrorCallback; +1875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** case HAL_SD_ABORT_CB_ID : +1877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->AbortCpltCallback = HAL_SD_AbortCallback; +1878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** case HAL_SD_MSP_INIT_CB_ID : +1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->MspInitCallback = HAL_SD_MspInit; +1881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** case HAL_SD_MSP_DEINIT_CB_ID : +1883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->MspDeInitCallback = HAL_SD_MspDeInit; +1884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** default : +1886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Update the error code */ +1887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; +1888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* update return status */ +1889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; +1890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if (hsd->State == HAL_SD_STATE_RESET) +1894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** switch (CallbackID) +1896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** case HAL_SD_MSP_INIT_CB_ID : +1898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->MspInitCallback = HAL_SD_MspInit; +1899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** case HAL_SD_MSP_DEINIT_CB_ID : +1901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->MspDeInitCallback = HAL_SD_MspDeInit; +1902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** default : +1904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Update the error code */ +1905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; +1906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* update return status */ +1907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; +1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +1912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + ARM GAS /tmp/ccMMu31U.s page 35 + + +1913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Update the error code */ +1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; +1915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* update return status */ +1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; +1917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Release Lock */ +1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_UNLOCK(hsd); +1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return status; +1922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +1924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +1926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @} +1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** @addtogroup SD_Exported_Functions_Group3 +1930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief management functions +1931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * +1932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** @verbatim +1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ============================================================================== +1934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ##### Peripheral Control functions ##### +1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ============================================================================== +1936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** [..] +1937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** This subsection provides a set of functions allowing to control the SD card +1938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** operations and get the related information +1939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** @endverbatim +1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @{ +1942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Returns information the information of the card which are stored on +1946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * the CID register. +1947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle +1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that +1949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * contains all CID register parameters +1950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval HAL status +1951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) +1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U); +1955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U); +1957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U)); +1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU); +1961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U); +1963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U)); +1965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U); +1967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U); +1969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + ARM GAS /tmp/ccMMu31U.s page 36 + + +1970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U); +1971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCID->Reserved2 = 1U; +1973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_OK; +1975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +1976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +1978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Returns information the information of the card which are stored on +1979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * the CSD register. +1980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle +1981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that +1982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * contains all CSD register parameters +1983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval HAL status +1984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD) +1986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U); +1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U); +1990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U); +1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U); +1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U); +1996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU); +1998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U); +2000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U); +2002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->PartBlockRead = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U); +2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U); +2006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U); +2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U); +2010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->Reserved2 = 0U; /*!< Reserved */ +2012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->SdCard.CardType == CARD_SDSC) +2014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U)) +2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U); +2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U); +2020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U); +2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U); +2024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U); +2026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + ARM GAS /tmp/ccMMu31U.s page 37 + + +2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ; +2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); +2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); +2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U); +2032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.LogBlockSize = 512U; +2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if(hsd->SdCard.CardType == CARD_SDHC_SDXC) +2035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Byte 7 */ +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U) +2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U); +2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; +2041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.BlockSize = 512U; +2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize; +2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +2045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ +2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +2048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; +2049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U); +2054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U); +2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU); +2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U); +2060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U); +2062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U); +2064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U); +2066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U); +2068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->Reserved3 = 0; +2070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U); +2072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U); +2074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U); +2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U); +2078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U); +2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U); +2082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U); + ARM GAS /tmp/ccMMu31U.s page 38 + + +2084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U); +2086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->Reserved4 = 1; +2088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_OK; +2090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Gets the SD status info. +2094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle +2095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that +2096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * will contain the SD card status information +2097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval HAL status +2098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus) +2100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t sd_status[16]; +2102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; +2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef status = HAL_OK; +2104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SD_SendSDStatus(hsd, sd_status); +2106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ +2109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +2110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; +2111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +2112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; +2113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +2115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U); +2117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U); +2119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF0000 +2121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << +2123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U +2124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU); +2126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U); +2128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U); +2130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU)) +2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U); +2134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U); +2136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Set Block Size for Card */ +2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); +2140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + ARM GAS /tmp/ccMMu31U.s page 39 + + +2141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ +2143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +2144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode = errorstate; +2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return status; +2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Gets the SD card info. +2154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle +2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that +2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * will contain the SD card status information +2157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval HAL status +2158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) +2160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType); +2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); +2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->Class = (uint32_t)(hsd->SdCard.Class); +2164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd); +2165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr); +2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize); +2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr); +2168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize); +2169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_OK; +2171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Enables wide bus operation for the requested card if supported by +2175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * card. +2176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle +2177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param WideMode: Specifies the SD card wide bus mode +2178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * This parameter can be one of the following values: +2179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer +2180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer +2181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer +2182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval HAL status +2183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode) +2185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_InitTypeDef Init; +2187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; +2188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef status = HAL_OK; +2189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Check the parameters */ +2191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** assert_param(IS_SDMMC_BUS_WIDE(WideMode)); +2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Change State */ +2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_BUSY; +2195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->SdCard.CardType != CARD_SECURED) +2197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + ARM GAS /tmp/ccMMu31U.s page 40 + + +2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(WideMode == SDMMC_BUS_WIDE_8B) +2199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; +2201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if(WideMode == SDMMC_BUS_WIDE_4B) +2203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SD_WideBus_Enable(hsd); +2205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; +2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if(WideMode == SDMMC_BUS_WIDE_1B) +2209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SD_WideBus_Disable(hsd); +2211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; +2213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +2215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* WideMode is not a valid argument*/ +2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_PARAM; +2218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +2221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* MMC Card does not support this feature */ +2223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; +2224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->ErrorCode != HAL_SD_ERROR_NONE) +2227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ +2229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; +2232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Configure the SDMMC peripheral */ +2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockEdge = hsd->Init.ClockEdge; +2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockBypass = hsd->Init.ClockBypass; +2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockPowerSave = hsd->Init.ClockPowerSave; +2239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.BusWide = WideMode; +2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; +2241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockDiv = hsd->Init.ClockDiv; +2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_Init(hsd->Instance, Init); +2243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Set Block Size for Card */ +2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); +2247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ +2250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +2251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; +2252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; +2253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + ARM GAS /tmp/ccMMu31U.s page 41 + + +2255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Change State */ +2256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +2257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return status; +2259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Gets the current sd card data state. +2263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: pointer to SD handle +2264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval Card state +2265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) +2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t cardstate; +2269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; +2270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t resp1 = 0; +2271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SD_SendStatus(hsd, &resp1); +2273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; +2276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** cardstate = ((resp1 >> 9U) & 0x0FU); +2279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return (HAL_SD_CardStateTypeDef)cardstate; +2281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Abort the current transfer and disable the SD. +2285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: pointer to a SD_HandleTypeDef structure that contains +2286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * the configuration information for SD module. +2287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval HAL status +2288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) +2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardStateTypeDef CardState; +2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t context = hsd->Context; +2293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* DIsable All interrupts */ +2295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ +2296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); +2297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear All flags */ +2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); +2300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** CLEAR_BIT(hsd->Instance->DCTRL, SDMMC_DCTRL_DTEN); +2302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if ((context & SD_CONTEXT_DMA) != 0U) +2304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Disable the SD DMA request */ +2306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); +2307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Abort the SD DMA Tx channel */ +2309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_ +2310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(HAL_DMA_Abort(hsd->hdmatx) != HAL_OK) + ARM GAS /tmp/ccMMu31U.s page 42 + + +2312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_DMA; +2314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Abort the SD DMA Rx channel */ +2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIP +2318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(HAL_DMA_Abort(hsd->hdmarx) != HAL_OK) +2320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_DMA; +2322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +2325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Nothing to do */ +2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +2331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Initialize the SD operation */ +2333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; +2334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** CardState = HAL_SD_GetCardState(hsd); +2336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) +2337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); +2339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->ErrorCode != HAL_SD_ERROR_NONE) +2341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +2343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_OK; +2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Abort the current transfer and disable the SD (IT mode). +2349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: pointer to a SD_HandleTypeDef structure that contains +2350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * the configuration information for SD module. +2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval HAL status +2352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) +2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardStateTypeDef CardState; +2356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t context = hsd->Context; +2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Disable All interrupts */ +2359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ +2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); +2361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** CLEAR_BIT(hsd->Instance->DCTRL, SDMMC_DCTRL_DTEN); +2363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if ((context & SD_CONTEXT_DMA) != 0U) +2365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Disable the SD DMA request */ +2367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); +2368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + ARM GAS /tmp/ccMMu31U.s page 43 + + +2369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Abort the SD DMA Tx channel */ +2370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_ +2371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; +2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) +2374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->hdmatx = NULL; +2376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Abort the SD DMA Rx channel */ +2379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIP +2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; +2382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) +2383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->hdmarx = NULL; +2385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +2388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Nothing to do */ +2390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* No transfer ongoing on both DMA channels*/ +2393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +2394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear All flags */ +2396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); +2397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** CardState = HAL_SD_GetCardState(hsd); +2399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +2400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; +2401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) +2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); +2404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->ErrorCode != HAL_SD_ERROR_NONE) +2406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; +2408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +2410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +2412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->AbortCpltCallback(hsd); +2413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else +2414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_AbortCallback(hsd); +2415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +2416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_OK; +2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @} +2424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + ARM GAS /tmp/ccMMu31U.s page 44 + + +2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @} +2428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Private function ----------------------------------------------------------*/ +2431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** @addtogroup SD_Private_Functions +2432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @{ +2433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief DMA SD transmit process complete callback +2437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hdma: DMA handle +2438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval None +2439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma) +2441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 28 .loc 1 2441 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. +2442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + 33 .loc 1 2442 3 view .LVU1 + 34 .loc 1 2442 21 is_stmt 0 view .LVU2 + 35 0000 836B ldr r3, [r0, #56] + 36 .LVL1: +2443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Enable DATAEND Interrupt */ +2445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DATAEND)); + 37 .loc 1 2445 3 is_stmt 1 view .LVU3 + 38 0002 1A68 ldr r2, [r3] + 39 0004 D36B ldr r3, [r2, #60] + 40 .LVL2: + 41 .loc 1 2445 3 is_stmt 0 view .LVU4 + 42 0006 43F48073 orr r3, r3, #256 + 43 000a D363 str r3, [r2, #60] + 44 .LVL3: +2446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 45 .loc 1 2446 1 view .LVU5 + 46 000c 7047 bx lr + 47 .cfi_endproc + 48 .LFE168: + 50 .section .text.SD_PowerON,"ax",%progbits + 51 .align 1 + 52 .syntax unified + 53 .thumb + 54 .thumb_func + 56 SD_PowerON: + 57 .LVL4: + 58 .LFB174: +2447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief DMA SD receive process complete callback +2450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hdma: DMA handle +2451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval None +2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) + ARM GAS /tmp/ccMMu31U.s page 45 + + +2454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); +2456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; +2457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send stop command in multiblock write */ +2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA)) +2460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdStopTransfer(hsd->Instance); +2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; +2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +2466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCallback(hsd); +2467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else +2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_ErrorCallback(hsd); +2469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif +2470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Disable the DMA transfer for transmit request by setting the DMAEN bit +2474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** in the SD DCTRL register */ +2475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); +2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ +2478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); +2479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +2481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; +2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +2484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->RxCpltCallback(hsd); +2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else +2486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_RxCpltCallback(hsd); +2487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif +2488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief DMA SD communication error callback +2492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hdma: DMA handle +2493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval None +2494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMAError(DMA_HandleTypeDef *hdma) +2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); +2498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardStateTypeDef CardState; +2499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t RxErrorCode, TxErrorCode; +2500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* if DMA error is FIFO error ignore it */ +2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) +2503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** RxErrorCode = hsd->hdmarx->ErrorCode; +2505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** TxErrorCode = hsd->hdmatx->ErrorCode; +2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE)) +2507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear All flags */ +2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); +2510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + ARM GAS /tmp/ccMMu31U.s page 46 + + +2511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Disable All interrupts */ +2512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ +2513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); +2514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_DMA; +2516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** CardState = HAL_SD_GetCardState(hsd); +2517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) +2518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); +2520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State= HAL_SD_STATE_READY; +2523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; +2524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +2527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCallback(hsd); +2528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else +2529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_ErrorCallback(hsd); +2530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif +2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief DMA SD Tx Abort callback +2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hdma: DMA handle +2537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval None +2538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMATxAbort(DMA_HandleTypeDef *hdma) +2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); +2542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardStateTypeDef CardState; +2543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear All flags */ +2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); +2546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** CardState = HAL_SD_GetCardState(hsd); +2548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +2549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; +2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) +2551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); +2553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->ErrorCode == HAL_SD_ERROR_NONE) +2556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +2558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->AbortCpltCallback(hsd); +2559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else +2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_AbortCallback(hsd); +2561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif +2562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +2564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +2566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCallback(hsd); +2567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else + ARM GAS /tmp/ccMMu31U.s page 47 + + +2568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_ErrorCallback(hsd); +2569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif +2570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief DMA SD Rx Abort callback +2575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hdma: DMA handle +2576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval None +2577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) +2579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); +2581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardStateTypeDef CardState; +2582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear All flags */ +2584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); +2585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** CardState = HAL_SD_GetCardState(hsd); +2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; +2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; +2589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) +2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); +2592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->ErrorCode == HAL_SD_ERROR_NONE) +2595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +2597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->AbortCpltCallback(hsd); +2598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else +2599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_AbortCallback(hsd); +2600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif +2601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +2603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +2605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCallback(hsd); +2606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #else +2607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_ErrorCallback(hsd); +2608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif +2609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Initializes the sd card. +2614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle +2615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval SD Card error state +2616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) +2618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardCSDTypeDef CSD; +2620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; +2621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint16_t sd_rca = 1U; +2622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Check the power State */ +2624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(SDMMC_GetPowerState(hsd->Instance) == 0U) + ARM GAS /tmp/ccMMu31U.s page 48 + + +2625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Power off */ +2627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; +2628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->SdCard.CardType != CARD_SECURED) +2631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send CMD2 ALL_SEND_CID */ +2633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdSendCID(hsd->Instance); +2634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +2637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +2639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Get Card identification number data */ +2641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CID[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); +2642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); +2643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); +2644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); +2645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->SdCard.CardType != CARD_SECURED) +2649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send CMD3 SET_REL_ADDR with argument 0 */ +2651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* SD Card publishes its RCA. */ +2652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca); +2653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +2656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(hsd->SdCard.CardType != CARD_SECURED) +2659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Get the SD card RCA */ +2661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.RelCardAdd = sd_rca; +2662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send CMD9 SEND_CSD with argument as card's RCA */ +2664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); +2665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +2668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +2670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Get Card Specific Data */ +2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); +2673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); +2674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); +2675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); +2676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Get the Card Class */ +2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20U); +2681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + ARM GAS /tmp/ccMMu31U.s page 49 + + +2682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Get CSD parameters */ +2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK) +2684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_UNSUPPORTED_FEATURE; +2686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Select the Card */ +2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16 +2690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +2693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Configure SDMMC peripheral interface */ +2696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_Init(hsd->Instance, hsd->Init); +2697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* All cards are initialized */ +2699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_NONE; +2700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Enquires cards about their operating voltage and configures clock +2704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * controls and stores SD information that will be needed in future +2705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * in the SD handle. +2706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle +2707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval error state +2708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) +2710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 59 .loc 1 2710 1 is_stmt 1 view -0 + 60 .cfi_startproc + 61 @ args = 0, pretend = 0, frame = 8 + 62 @ frame_needed = 0, uses_anonymous_args = 0 + 63 .loc 1 2710 1 is_stmt 0 view .LVU7 + 64 0000 70B5 push {r4, r5, r6, lr} + 65 .LCFI0: + 66 .cfi_def_cfa_offset 16 + 67 .cfi_offset 4, -16 + 68 .cfi_offset 5, -12 + 69 .cfi_offset 6, -8 + 70 .cfi_offset 14, -4 + 71 0002 82B0 sub sp, sp, #8 + 72 .LCFI1: + 73 .cfi_def_cfa_offset 24 + 74 0004 0446 mov r4, r0 +2711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __IO uint32_t count = 0U; + 75 .loc 1 2711 3 is_stmt 1 view .LVU8 + 76 .loc 1 2711 17 is_stmt 0 view .LVU9 + 77 0006 0023 movs r3, #0 + 78 0008 0193 str r3, [sp, #4] +2712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t response = 0U, validvoltage = 0U; + 79 .loc 1 2712 3 is_stmt 1 view .LVU10 + 80 .LVL5: +2713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 81 .loc 1 2713 3 view .LVU11 +2714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* CMD0: GO_IDLE_STATE */ + ARM GAS /tmp/ccMMu31U.s page 50 + + +2716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdGoIdleState(hsd->Instance); + 82 .loc 1 2716 3 view .LVU12 + 83 .loc 1 2716 16 is_stmt 0 view .LVU13 + 84 000a 0068 ldr r0, [r0] + 85 .LVL6: + 86 .loc 1 2716 16 view .LVU14 + 87 000c FFF7FEFF bl SDMMC_CmdGoIdleState + 88 .LVL7: +2717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 89 .loc 1 2717 3 is_stmt 1 view .LVU15 + 90 .loc 1 2717 5 is_stmt 0 view .LVU16 + 91 0010 0546 mov r5, r0 + 92 0012 10B1 cbz r0, .L19 + 93 .LVL8: + 94 .L2: +2718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +2720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ +2723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdOperCond(hsd->Instance); +2724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.CardVersion = CARD_V1_X; +2727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* CMD0: GO_IDLE_STATE */ +2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdGoIdleState(hsd->Instance); +2729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +2732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +2736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.CardVersion = CARD_V2_X; +2738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if( hsd->SdCard.CardVersion == CARD_V2_X) +2741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* SEND CMD55 APP_CMD with RCA as 0 */ +2743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); +2744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_UNSUPPORTED_FEATURE; +2747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* SD CARD */ +2750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ +2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) +2752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* SEND CMD55 APP_CMD with RCA as 0 */ +2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); +2755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +2758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + ARM GAS /tmp/ccMMu31U.s page 51 + + +2760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send CMD41 */ +2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACI +2762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_UNSUPPORTED_FEATURE; +2765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Get command response */ +2768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); +2769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Get operating voltage*/ +2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); +2772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** count++; +2774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(count >= SDMMC_MAX_VOLT_TRIAL) +2777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_INVALID_VOLTRANGE; +2779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ +2782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.CardType = CARD_SDHC_SDXC; +2784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +2786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.CardType = CARD_SDSC; +2788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_NONE; +2792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 95 .loc 1 2792 1 view .LVU17 + 96 0014 2846 mov r0, r5 + 97 0016 02B0 add sp, sp, #8 + 98 .LCFI2: + 99 .cfi_remember_state + 100 .cfi_def_cfa_offset 16 + 101 @ sp needed + 102 0018 70BD pop {r4, r5, r6, pc} + 103 .LVL9: + 104 .L19: + 105 .LCFI3: + 106 .cfi_restore_state +2723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 107 .loc 1 2723 3 is_stmt 1 view .LVU18 +2723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 108 .loc 1 2723 16 is_stmt 0 view .LVU19 + 109 001a 2068 ldr r0, [r4] + 110 .LVL10: +2723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 111 .loc 1 2723 16 view .LVU20 + 112 001c FFF7FEFF bl SDMMC_CmdOperCond + 113 .LVL11: +2724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 114 .loc 1 2724 3 is_stmt 1 view .LVU21 + ARM GAS /tmp/ccMMu31U.s page 52 + + +2724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 115 .loc 1 2724 5 is_stmt 0 view .LVU22 + 116 0020 38B9 cbnz r0, .L20 +2737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 117 .loc 1 2737 5 is_stmt 1 view .LVU23 +2737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 118 .loc 1 2737 29 is_stmt 0 view .LVU24 + 119 0022 0123 movs r3, #1 + 120 0024 A364 str r3, [r4, #72] + 121 .L5: +2740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 122 .loc 1 2740 3 is_stmt 1 view .LVU25 +2740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 123 .loc 1 2740 18 is_stmt 0 view .LVU26 + 124 0026 A36C ldr r3, [r4, #72] +2740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 125 .loc 1 2740 5 view .LVU27 + 126 0028 012B cmp r3, #1 + 127 002a 0BD0 beq .L6 + 128 .L8: +2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 129 .loc 1 2771 52 discriminator 1 view .LVU28 + 130 002c 2E46 mov r6, r5 + 131 002e 2846 mov r0, r5 + 132 .LVL12: +2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 133 .loc 1 2771 52 discriminator 1 view .LVU29 + 134 0030 14E0 b .L7 + 135 .LVL13: + 136 .L20: +2726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* CMD0: GO_IDLE_STATE */ + 137 .loc 1 2726 5 is_stmt 1 view .LVU30 +2726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* CMD0: GO_IDLE_STATE */ + 138 .loc 1 2726 29 is_stmt 0 view .LVU31 + 139 0032 0023 movs r3, #0 + 140 0034 A364 str r3, [r4, #72] +2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 141 .loc 1 2728 5 is_stmt 1 view .LVU32 +2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 142 .loc 1 2728 18 is_stmt 0 view .LVU33 + 143 0036 2068 ldr r0, [r4] + 144 .LVL14: +2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 145 .loc 1 2728 18 view .LVU34 + 146 0038 FFF7FEFF bl SDMMC_CmdGoIdleState + 147 .LVL15: +2729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 148 .loc 1 2729 5 is_stmt 1 view .LVU35 +2729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 149 .loc 1 2729 7 is_stmt 0 view .LVU36 + 150 003c 0028 cmp r0, #0 + 151 003e F2D0 beq .L5 +2731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 152 .loc 1 2731 14 view .LVU37 + 153 0040 0546 mov r5, r0 + 154 0042 E7E7 b .L2 + 155 .L6: + ARM GAS /tmp/ccMMu31U.s page 53 + + +2743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 156 .loc 1 2743 5 is_stmt 1 view .LVU38 +2743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 157 .loc 1 2743 18 is_stmt 0 view .LVU39 + 158 0044 0021 movs r1, #0 + 159 0046 2068 ldr r0, [r4] + 160 .LVL16: +2743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 161 .loc 1 2743 18 view .LVU40 + 162 0048 FFF7FEFF bl SDMMC_CmdAppCommand + 163 .LVL17: +2744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 164 .loc 1 2744 5 is_stmt 1 view .LVU41 +2744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 165 .loc 1 2744 7 is_stmt 0 view .LVU42 + 166 004c 0028 cmp r0, #0 + 167 004e EDD0 beq .L8 +2746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 168 .loc 1 2746 14 view .LVU43 + 169 0050 4FF08055 mov r5, #268435456 + 170 0054 DEE7 b .L2 + 171 .LVL18: + 172 .L9: +2773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 173 .loc 1 2773 5 is_stmt 1 view .LVU44 +2773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 174 .loc 1 2773 10 is_stmt 0 view .LVU45 + 175 0056 019B ldr r3, [sp, #4] + 176 0058 0133 adds r3, r3, #1 + 177 005a 0193 str r3, [sp, #4] + 178 .LVL19: + 179 .L7: +2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 180 .loc 1 2751 40 is_stmt 1 view .LVU46 +2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 181 .loc 1 2751 16 is_stmt 0 view .LVU47 + 182 005c 019A ldr r2, [sp, #4] +2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 183 .loc 1 2751 40 view .LVU48 + 184 005e 4FF6FE73 movw r3, #65534 + 185 0062 9A42 cmp r2, r3 + 186 0064 13D8 bhi .L10 +2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 187 .loc 1 2751 40 discriminator 1 view .LVU49 + 188 0066 96B9 cbnz r6, .L10 +2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 189 .loc 1 2754 5 is_stmt 1 view .LVU50 +2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 190 .loc 1 2754 18 is_stmt 0 view .LVU51 + 191 0068 0021 movs r1, #0 + 192 006a 2068 ldr r0, [r4] + 193 .LVL20: +2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 194 .loc 1 2754 18 view .LVU52 + 195 006c FFF7FEFF bl SDMMC_CmdAppCommand + 196 .LVL21: +2755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + ARM GAS /tmp/ccMMu31U.s page 54 + + + 197 .loc 1 2755 5 is_stmt 1 view .LVU53 +2755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 198 .loc 1 2755 7 is_stmt 0 view .LVU54 + 199 0070 E0B9 cbnz r0, .L15 +2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 200 .loc 1 2761 5 is_stmt 1 view .LVU55 +2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 201 .loc 1 2761 18 is_stmt 0 view .LVU56 + 202 0072 1249 ldr r1, .L21 + 203 0074 2068 ldr r0, [r4] + 204 .LVL22: +2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 205 .loc 1 2761 18 view .LVU57 + 206 0076 FFF7FEFF bl SDMMC_CmdAppOperCommand + 207 .LVL23: +2762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 208 .loc 1 2762 5 is_stmt 1 view .LVU58 +2762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 209 .loc 1 2762 7 is_stmt 0 view .LVU59 + 210 007a 0646 mov r6, r0 + 211 .LVL24: +2762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 212 .loc 1 2762 7 view .LVU60 + 213 007c C0B9 cbnz r0, .L16 +2768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 214 .loc 1 2768 5 is_stmt 1 view .LVU61 +2768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 215 .loc 1 2768 16 is_stmt 0 view .LVU62 + 216 007e 0021 movs r1, #0 + 217 0080 2068 ldr r0, [r4] + 218 .LVL25: +2768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 219 .loc 1 2768 16 view .LVU63 + 220 0082 FFF7FEFF bl SDMMC_GetResponse + 221 .LVL26: +2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 222 .loc 1 2771 5 is_stmt 1 view .LVU64 +2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 223 .loc 1 2771 52 is_stmt 0 view .LVU65 + 224 0086 C30F lsrs r3, r0, #31 + 225 0088 E5D0 beq .L9 +2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 226 .loc 1 2771 52 discriminator 1 view .LVU66 + 227 008a 1E46 mov r6, r3 + 228 .LVL27: +2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 229 .loc 1 2771 52 discriminator 1 view .LVU67 + 230 008c E3E7 b .L9 + 231 .LVL28: + 232 .L10: +2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 233 .loc 1 2776 3 is_stmt 1 view .LVU68 +2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 234 .loc 1 2776 12 is_stmt 0 view .LVU69 + 235 008e 019A ldr r2, [sp, #4] +2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 236 .loc 1 2776 5 view .LVU70 + ARM GAS /tmp/ccMMu31U.s page 55 + + + 237 0090 4FF6FE73 movw r3, #65534 + 238 0094 9A42 cmp r2, r3 + 239 0096 0ED8 bhi .L17 +2781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 240 .loc 1 2781 3 is_stmt 1 view .LVU71 +2781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 241 .loc 1 2781 5 is_stmt 0 view .LVU72 + 242 0098 10F08043 ands r3, r0, #1073741824 + 243 009c 02D0 beq .L12 +2783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 244 .loc 1 2783 5 is_stmt 1 view .LVU73 +2783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 245 .loc 1 2783 26 is_stmt 0 view .LVU74 + 246 009e 0123 movs r3, #1 + 247 00a0 6364 str r3, [r4, #68] + 248 00a2 B7E7 b .L2 + 249 .L12: +2787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 250 .loc 1 2787 5 is_stmt 1 view .LVU75 +2787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 251 .loc 1 2787 26 is_stmt 0 view .LVU76 + 252 00a4 0022 movs r2, #0 + 253 00a6 6264 str r2, [r4, #68] +2791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 254 .loc 1 2791 10 view .LVU77 + 255 00a8 1D46 mov r5, r3 + 256 00aa B3E7 b .L2 + 257 .LVL29: + 258 .L15: +2757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 259 .loc 1 2757 14 view .LVU78 + 260 00ac 0546 mov r5, r0 + 261 00ae B1E7 b .L2 + 262 .LVL30: + 263 .L16: +2764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 264 .loc 1 2764 14 view .LVU79 + 265 00b0 4FF08055 mov r5, #268435456 + 266 00b4 AEE7 b .L2 + 267 .LVL31: + 268 .L17: +2778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 269 .loc 1 2778 12 view .LVU80 + 270 00b6 4FF08075 mov r5, #16777216 + 271 00ba ABE7 b .L2 + 272 .L22: + 273 .align 2 + 274 .L21: + 275 00bc 000010C1 .word -1055916032 + 276 .cfi_endproc + 277 .LFE174: + 279 .section .text.SD_PowerOFF,"ax",%progbits + 280 .align 1 + 281 .syntax unified + 282 .thumb + 283 .thumb_func + 285 SD_PowerOFF: + ARM GAS /tmp/ccMMu31U.s page 56 + + + 286 .LVL32: + 287 .LFB175: +2793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Turns the SDMMC output signals off. +2796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle +2797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval None +2798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_PowerOFF(SD_HandleTypeDef *hsd) +2800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 288 .loc 1 2800 1 is_stmt 1 view -0 + 289 .cfi_startproc + 290 @ args = 0, pretend = 0, frame = 0 + 291 @ frame_needed = 0, uses_anonymous_args = 0 + 292 .loc 1 2800 1 is_stmt 0 view .LVU82 + 293 0000 08B5 push {r3, lr} + 294 .LCFI4: + 295 .cfi_def_cfa_offset 8 + 296 .cfi_offset 3, -8 + 297 .cfi_offset 14, -4 +2801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Set Power State to OFF */ +2802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_PowerState_OFF(hsd->Instance); + 298 .loc 1 2802 3 is_stmt 1 view .LVU83 + 299 .loc 1 2802 9 is_stmt 0 view .LVU84 + 300 0002 0068 ldr r0, [r0] + 301 .LVL33: + 302 .loc 1 2802 9 view .LVU85 + 303 0004 FFF7FEFF bl SDMMC_PowerState_OFF + 304 .LVL34: +2803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 305 .loc 1 2803 1 view .LVU86 + 306 0008 08BD pop {r3, pc} + 307 .cfi_endproc + 308 .LFE175: + 310 .section .text.SD_Read_IT,"ax",%progbits + 311 .align 1 + 312 .syntax unified + 313 .thumb + 314 .thumb_func + 316 SD_Read_IT: + 317 .LVL35: + 318 .LFB181: +2804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Send Status info command. +2807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: pointer to SD handle +2808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param pSDstatus: Pointer to the buffer that will contain the SD card status +2809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * SD Status register) +2810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval error state +2811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) +2813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; +2815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; +2816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t tickstart = HAL_GetTick(); +2817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t count; +2818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t *pData = pSDstatus; + ARM GAS /tmp/ccMMu31U.s page 57 + + +2819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Check SD response */ +2821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) +2822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; +2824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Set block size for card if it is not equal to current block size for card */ +2827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U); +2828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_NONE; +2831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +2832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send CMD55 */ +2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); +2836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_NONE; +2839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +2840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Configure the SD DPSM (Data Path State Machine) */ +2843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataTimeOut = SDMMC_DATATIMEOUT; +2844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = 64U; +2845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B; +2846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; +2847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; +2848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; +2849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); +2850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ +2852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdStatusRegister(hsd->Instance); +2853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_NONE; +2856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +2857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Get status data */ +2860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SD +2861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) +2863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** for(count = 0U; count < 8U; count++) +2865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *pData = SDMMC_ReadFIFO(hsd->Instance); +2867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pData++; +2868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) +2872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_TIMEOUT; +2874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + ARM GAS /tmp/ccMMu31U.s page 58 + + +2876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) +2878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_DATA_TIMEOUT; +2880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) +2882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_DATA_CRC_FAIL; +2884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) +2886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_RX_OVERRUN; +2888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +2890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Nothing to do */ +2892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))) +2895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *pData = SDMMC_ReadFIFO(hsd->Instance); +2897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pData++; +2898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) +2900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_TIMEOUT; +2902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static status flags*/ +2906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); +2907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_NONE; +2909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Returns the current card's status. +2913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle +2914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param pCardStatus: pointer to the buffer that will contain the SD card +2915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * status (Card Status register) +2916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval error state +2917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) +2919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; +2921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(pCardStatus == NULL) +2923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_PARAM; +2925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send Status command */ +2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); +2929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +2932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + ARM GAS /tmp/ccMMu31U.s page 59 + + +2933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Get SD card status */ +2935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); +2936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_NONE; +2938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Enables the SDMMC wide bus mode. +2942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: pointer to SD handle +2943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval error state +2944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) +2946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t scr[2U] = {0U, 0U}; +2948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) +2951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; +2953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Get SCR Register */ +2956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SD_FindSCR(hsd, scr); +2957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +2960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* If requested card supports wide bus operation */ +2963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) +2964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send CMD55 APP_CMD with argument as card's RCA.*/ +2966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); +2967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +2970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ +2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U); +2974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +2975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +2977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_NONE; +2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +2982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; +2984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +2986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +2988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Disables the SDMMC wide bus mode. +2989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle + ARM GAS /tmp/ccMMu31U.s page 60 + + +2990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval error state +2991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +2992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) +2993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t scr[2U] = {0U, 0U}; +2995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; +2996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) +2998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +2999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; +3000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Get SCR Register */ +3003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SD_FindSCR(hsd, scr); +3004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +3005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +3007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* If requested card supports 1 bit mode operation */ +3010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) +3011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send CMD55 APP_CMD with argument as card's RCA */ +3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); +3014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +3015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +3017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ +3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U); +3021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +3022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +3024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_NONE; +3027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +3029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; +3031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +3036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Finds the SD card SCR register value. +3037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: Pointer to SD handle +3038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param pSCR: pointer to the buffer that will contain the SCR value +3039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval error state +3040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +3041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) +3042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; +3044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; +3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t tickstart = HAL_GetTick(); +3046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t index = 0U; + ARM GAS /tmp/ccMMu31U.s page 61 + + +3047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t tempscr[2U] = {0U, 0U}; +3048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t *scr = pSCR; +3049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Set Block Size To 8 Bytes */ +3051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U); +3052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +3053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +3055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send CMD55 APP_CMD with argument as card's RCA */ +3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U)); +3059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +3060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +3062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataTimeOut = SDMMC_DATATIMEOUT; +3065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = 8U; +3066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B; +3067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; +3068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; +3069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; +3070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); +3071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ +3073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** errorstate = SDMMC_CmdSendSCR(hsd->Instance); +3074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) +3075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; +3077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT)) +3080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) +3082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance); +3084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** index++; +3085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXACT)) +3087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** break; +3089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) +3092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_TIMEOUT; +3094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) +3098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); +3100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_DATA_TIMEOUT; +3102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + ARM GAS /tmp/ccMMu31U.s page 62 + + +3104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); +3106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_DATA_CRC_FAIL; +3108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) +3110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); +3112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_RX_OVERRUN; +3114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** else +3116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* No error flag set */ +3118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Clear all the static flags */ +3119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); +3120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\ +3122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); +3123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** scr++; +3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ +3125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); +3126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_SD_ERROR_NONE; +3130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +3133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Wrap up reading in non-blocking mode. +3134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: pointer to a SD_HandleTypeDef structure that contains +3135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * the configuration information. +3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval None +3137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +3138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_Read_IT(SD_HandleTypeDef *hsd) +3139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 319 .loc 1 3139 1 is_stmt 1 view -0 + 320 .cfi_startproc + 321 @ args = 0, pretend = 0, frame = 0 + 322 @ frame_needed = 0, uses_anonymous_args = 0 + 323 .loc 1 3139 1 is_stmt 0 view .LVU88 + 324 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 325 .LCFI5: + 326 .cfi_def_cfa_offset 24 + 327 .cfi_offset 3, -24 + 328 .cfi_offset 4, -20 + 329 .cfi_offset 5, -16 + 330 .cfi_offset 6, -12 + 331 .cfi_offset 7, -8 + 332 .cfi_offset 14, -4 +3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t count, data, dataremaining; + 333 .loc 1 3140 3 is_stmt 1 view .LVU89 +3141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint8_t* tmp; + 334 .loc 1 3141 3 view .LVU90 +3142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp = hsd->pRxBuffPtr; + 335 .loc 1 3143 3 view .LVU91 + ARM GAS /tmp/ccMMu31U.s page 63 + + + 336 .loc 1 3143 7 is_stmt 0 view .LVU92 + 337 0002 846A ldr r4, [r0, #40] + 338 .LVL36: +3144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining = hsd->RxXferSize; + 339 .loc 1 3144 3 is_stmt 1 view .LVU93 + 340 .loc 1 3144 17 is_stmt 0 view .LVU94 + 341 0004 C66A ldr r6, [r0, #44] + 342 .LVL37: +3145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if (dataremaining > 0U) + 343 .loc 1 3146 3 is_stmt 1 view .LVU95 + 344 .loc 1 3146 6 is_stmt 0 view .LVU96 + 345 0006 A6B9 cbnz r6, .L29 + 346 .LVL38: + 347 .L25: +3147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Read data from SDMMC Rx FIFO */ +3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** for(count = 0U; count < 8U; count++) +3150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** data = SDMMC_ReadFIFO(hsd->Instance); +3152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tmp = (uint8_t)(data & 0xFFU); +3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; +3154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; +3155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tmp = (uint8_t)((data >> 8U) & 0xFFU); +3156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; +3157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; +3158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tmp = (uint8_t)((data >> 16U) & 0xFFU); +3159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; +3160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; +3161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tmp = (uint8_t)((data >> 24U) & 0xFFU); +3162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; +3163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; +3164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->pRxBuffPtr = tmp; +3167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->RxXferSize = dataremaining; +3168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 348 .loc 1 3169 1 view .LVU97 + 349 0008 F8BD pop {r3, r4, r5, r6, r7, pc} + 350 .LVL39: + 351 .L28: +3151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tmp = (uint8_t)(data & 0xFFU); + 352 .loc 1 3151 7 is_stmt 1 view .LVU98 +3151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tmp = (uint8_t)(data & 0xFFU); + 353 .loc 1 3151 14 is_stmt 0 view .LVU99 + 354 000a 3868 ldr r0, [r7] + 355 000c FFF7FEFF bl SDMMC_ReadFIFO + 356 .LVL40: +3152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 357 .loc 1 3152 7 is_stmt 1 view .LVU100 +3152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 358 .loc 1 3152 12 is_stmt 0 view .LVU101 + 359 0010 2070 strb r0, [r4] +3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 360 .loc 1 3153 7 is_stmt 1 view .LVU102 + 361 .LVL41: + ARM GAS /tmp/ccMMu31U.s page 64 + + +3154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tmp = (uint8_t)((data >> 8U) & 0xFFU); + 362 .loc 1 3154 7 view .LVU103 +3155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 363 .loc 1 3155 7 view .LVU104 +3155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 364 .loc 1 3155 14 is_stmt 0 view .LVU105 + 365 0012 C0F30723 ubfx r3, r0, #8, #8 +3155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 366 .loc 1 3155 12 view .LVU106 + 367 0016 6370 strb r3, [r4, #1] +3156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 368 .loc 1 3156 7 is_stmt 1 view .LVU107 + 369 .LVL42: +3157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tmp = (uint8_t)((data >> 16U) & 0xFFU); + 370 .loc 1 3157 7 view .LVU108 +3158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 371 .loc 1 3158 7 view .LVU109 +3158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 372 .loc 1 3158 14 is_stmt 0 view .LVU110 + 373 0018 C0F30743 ubfx r3, r0, #16, #8 +3158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 374 .loc 1 3158 12 view .LVU111 + 375 001c A370 strb r3, [r4, #2] +3159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 376 .loc 1 3159 7 is_stmt 1 view .LVU112 + 377 .LVL43: +3160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tmp = (uint8_t)((data >> 24U) & 0xFFU); + 378 .loc 1 3160 7 view .LVU113 +3161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 379 .loc 1 3161 7 view .LVU114 +3161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 380 .loc 1 3161 14 is_stmt 0 view .LVU115 + 381 001e 000E lsrs r0, r0, #24 + 382 .LVL44: +3161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 383 .loc 1 3161 12 view .LVU116 + 384 0020 E070 strb r0, [r4, #3] +3162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 385 .loc 1 3162 7 is_stmt 1 view .LVU117 +3162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 386 .loc 1 3162 10 is_stmt 0 view .LVU118 + 387 0022 0434 adds r4, r4, #4 + 388 .LVL45: +3163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 389 .loc 1 3163 7 is_stmt 1 view .LVU119 +3163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 390 .loc 1 3163 20 is_stmt 0 view .LVU120 + 391 0024 043E subs r6, r6, #4 + 392 .LVL46: +3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 393 .loc 1 3149 38 is_stmt 1 discriminator 3 view .LVU121 + 394 0026 0135 adds r5, r5, #1 + 395 .LVL47: + 396 .L26: +3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 397 .loc 1 3149 27 discriminator 1 view .LVU122 + 398 0028 072D cmp r5, #7 + ARM GAS /tmp/ccMMu31U.s page 65 + + + 399 002a EED9 bls .L28 +3166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->RxXferSize = dataremaining; + 400 .loc 1 3166 5 view .LVU123 +3166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->RxXferSize = dataremaining; + 401 .loc 1 3166 21 is_stmt 0 view .LVU124 + 402 002c BC62 str r4, [r7, #40] +3167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 403 .loc 1 3167 5 is_stmt 1 view .LVU125 +3167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 404 .loc 1 3167 21 is_stmt 0 view .LVU126 + 405 002e FE62 str r6, [r7, #44] + 406 .loc 1 3169 1 view .LVU127 + 407 0030 EAE7 b .L25 + 408 .LVL48: + 409 .L29: + 410 .loc 1 3169 1 view .LVU128 + 411 0032 0746 mov r7, r0 +3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 412 .loc 1 3149 15 view .LVU129 + 413 0034 0025 movs r5, #0 + 414 0036 F7E7 b .L26 + 415 .cfi_endproc + 416 .LFE181: + 418 .section .text.SD_Write_IT,"ax",%progbits + 419 .align 1 + 420 .syntax unified + 421 .thumb + 422 .thumb_func + 424 SD_Write_IT: + 425 .LVL49: + 426 .LFB182: +3170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /** +3172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @brief Wrap up writing in non-blocking mode. +3173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @param hsd: pointer to a SD_HandleTypeDef structure that contains +3174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * the configuration information. +3175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** * @retval None +3176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** */ +3177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** static void SD_Write_IT(SD_HandleTypeDef *hsd) +3178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 427 .loc 1 3178 1 is_stmt 1 view -0 + 428 .cfi_startproc + 429 @ args = 0, pretend = 0, frame = 8 + 430 @ frame_needed = 0, uses_anonymous_args = 0 + 431 .loc 1 3178 1 is_stmt 0 view .LVU131 + 432 0000 F0B5 push {r4, r5, r6, r7, lr} + 433 .LCFI6: + 434 .cfi_def_cfa_offset 20 + 435 .cfi_offset 4, -20 + 436 .cfi_offset 5, -16 + 437 .cfi_offset 6, -12 + 438 .cfi_offset 7, -8 + 439 .cfi_offset 14, -4 + 440 0002 83B0 sub sp, sp, #12 + 441 .LCFI7: + 442 .cfi_def_cfa_offset 32 +3179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t count, data, dataremaining; + ARM GAS /tmp/ccMMu31U.s page 66 + + + 443 .loc 1 3179 3 is_stmt 1 view .LVU132 +3180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint8_t* tmp; + 444 .loc 1 3180 3 view .LVU133 +3181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp = hsd->pTxBuffPtr; + 445 .loc 1 3182 3 view .LVU134 + 446 .loc 1 3182 7 is_stmt 0 view .LVU135 + 447 0004 046A ldr r4, [r0, #32] + 448 .LVL50: +3183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining = hsd->TxXferSize; + 449 .loc 1 3183 3 is_stmt 1 view .LVU136 + 450 .loc 1 3183 17 is_stmt 0 view .LVU137 + 451 0006 466A ldr r6, [r0, #36] + 452 .LVL51: +3184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if (dataremaining > 0U) + 453 .loc 1 3185 3 is_stmt 1 view .LVU138 + 454 .loc 1 3185 6 is_stmt 0 view .LVU139 + 455 0008 DEB9 cbnz r6, .L35 + 456 .LVL52: + 457 .L31: +3186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Write data to SDMMC Tx FIFO */ +3188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** for(count = 0U; count < 8U; count++) +3189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { +3190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** data = (uint32_t)(*tmp); +3191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; +3192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; +3193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** data |= ((uint32_t)(*tmp) << 8U); +3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; +3195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; +3196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** data |= ((uint32_t)(*tmp) << 16U); +3197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; +3198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; +3199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** data |= ((uint32_t)(*tmp) << 24U); +3200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; +3201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; +3202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_WriteFIFO(hsd->Instance, &data); +3203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** +3205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->pTxBuffPtr = tmp; +3206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->TxXferSize = dataremaining; +3207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } +3208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 458 .loc 1 3208 1 view .LVU140 + 459 000a 03B0 add sp, sp, #12 + 460 .LCFI8: + 461 .cfi_remember_state + 462 .cfi_def_cfa_offset 20 + 463 @ sp needed + 464 000c F0BD pop {r4, r5, r6, r7, pc} + 465 .LVL53: + 466 .L34: + 467 .LCFI9: + 468 .cfi_restore_state +3190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 469 .loc 1 3190 7 is_stmt 1 view .LVU141 + ARM GAS /tmp/ccMMu31U.s page 67 + + +3190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 470 .loc 1 3190 25 is_stmt 0 view .LVU142 + 471 000e 2378 ldrb r3, [r4] @ zero_extendqisi2 +3190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 472 .loc 1 3190 12 view .LVU143 + 473 0010 0193 str r3, [sp, #4] +3191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 474 .loc 1 3191 7 is_stmt 1 view .LVU144 + 475 .LVL54: +3192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** data |= ((uint32_t)(*tmp) << 8U); + 476 .loc 1 3192 7 view .LVU145 +3193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 477 .loc 1 3193 7 view .LVU146 +3193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 478 .loc 1 3193 27 is_stmt 0 view .LVU147 + 479 0012 6278 ldrb r2, [r4, #1] @ zero_extendqisi2 +3193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 480 .loc 1 3193 12 view .LVU148 + 481 0014 43EA0223 orr r3, r3, r2, lsl #8 + 482 0018 0193 str r3, [sp, #4] +3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 483 .loc 1 3194 7 is_stmt 1 view .LVU149 + 484 .LVL55: +3195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** data |= ((uint32_t)(*tmp) << 16U); + 485 .loc 1 3195 7 view .LVU150 +3196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 486 .loc 1 3196 7 view .LVU151 +3196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 487 .loc 1 3196 27 is_stmt 0 view .LVU152 + 488 001a A278 ldrb r2, [r4, #2] @ zero_extendqisi2 +3196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 489 .loc 1 3196 12 view .LVU153 + 490 001c 43EA0243 orr r3, r3, r2, lsl #16 + 491 0020 0193 str r3, [sp, #4] +3197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 492 .loc 1 3197 7 is_stmt 1 view .LVU154 + 493 .LVL56: +3198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** data |= ((uint32_t)(*tmp) << 24U); + 494 .loc 1 3198 7 view .LVU155 +3199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 495 .loc 1 3199 7 view .LVU156 +3199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 496 .loc 1 3199 27 is_stmt 0 view .LVU157 + 497 0022 E278 ldrb r2, [r4, #3] @ zero_extendqisi2 +3199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tmp++; + 498 .loc 1 3199 12 view .LVU158 + 499 0024 43EA0263 orr r3, r3, r2, lsl #24 + 500 0028 0193 str r3, [sp, #4] +3200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 501 .loc 1 3200 7 is_stmt 1 view .LVU159 +3200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 502 .loc 1 3200 10 is_stmt 0 view .LVU160 + 503 002a 0434 adds r4, r4, #4 + 504 .LVL57: +3201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_WriteFIFO(hsd->Instance, &data); + 505 .loc 1 3201 7 is_stmt 1 view .LVU161 +3201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_WriteFIFO(hsd->Instance, &data); + ARM GAS /tmp/ccMMu31U.s page 68 + + + 506 .loc 1 3201 20 is_stmt 0 view .LVU162 + 507 002c 043E subs r6, r6, #4 + 508 .LVL58: +3202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 509 .loc 1 3202 7 is_stmt 1 view .LVU163 +3202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 510 .loc 1 3202 13 is_stmt 0 view .LVU164 + 511 002e 01A9 add r1, sp, #4 + 512 0030 3868 ldr r0, [r7] + 513 0032 FFF7FEFF bl SDMMC_WriteFIFO + 514 .LVL59: +3188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 515 .loc 1 3188 38 is_stmt 1 discriminator 3 view .LVU165 + 516 0036 0135 adds r5, r5, #1 + 517 .LVL60: + 518 .L32: +3188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 519 .loc 1 3188 27 discriminator 1 view .LVU166 + 520 0038 072D cmp r5, #7 + 521 003a E8D9 bls .L34 +3205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->TxXferSize = dataremaining; + 522 .loc 1 3205 5 view .LVU167 +3205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->TxXferSize = dataremaining; + 523 .loc 1 3205 21 is_stmt 0 view .LVU168 + 524 003c 3C62 str r4, [r7, #32] +3206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 525 .loc 1 3206 5 is_stmt 1 view .LVU169 +3206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 526 .loc 1 3206 21 is_stmt 0 view .LVU170 + 527 003e 7E62 str r6, [r7, #36] + 528 .loc 1 3208 1 view .LVU171 + 529 0040 E3E7 b .L31 + 530 .LVL61: + 531 .L35: + 532 .loc 1 3208 1 view .LVU172 + 533 0042 0746 mov r7, r0 +3188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 534 .loc 1 3188 15 view .LVU173 + 535 0044 0025 movs r5, #0 + 536 0046 F7E7 b .L32 + 537 .cfi_endproc + 538 .LFE182: + 540 .section .text.SD_SendSDStatus,"ax",%progbits + 541 .align 1 + 542 .syntax unified + 543 .thumb + 544 .thumb_func + 546 SD_SendSDStatus: + 547 .LVL62: + 548 .LFB176: +2813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; + 549 .loc 1 2813 1 is_stmt 1 view -0 + 550 .cfi_startproc + 551 @ args = 0, pretend = 0, frame = 24 + 552 @ frame_needed = 0, uses_anonymous_args = 0 +2813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; + 553 .loc 1 2813 1 is_stmt 0 view .LVU175 + ARM GAS /tmp/ccMMu31U.s page 69 + + + 554 0000 F0B5 push {r4, r5, r6, r7, lr} + 555 .LCFI10: + 556 .cfi_def_cfa_offset 20 + 557 .cfi_offset 4, -20 + 558 .cfi_offset 5, -16 + 559 .cfi_offset 6, -12 + 560 .cfi_offset 7, -8 + 561 .cfi_offset 14, -4 + 562 0002 87B0 sub sp, sp, #28 + 563 .LCFI11: + 564 .cfi_def_cfa_offset 48 + 565 0004 0546 mov r5, r0 + 566 0006 0E46 mov r6, r1 +2814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 567 .loc 1 2814 3 is_stmt 1 view .LVU176 +2815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t tickstart = HAL_GetTick(); + 568 .loc 1 2815 3 view .LVU177 +2816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t count; + 569 .loc 1 2816 3 view .LVU178 +2816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t count; + 570 .loc 1 2816 24 is_stmt 0 view .LVU179 + 571 0008 FFF7FEFF bl HAL_GetTick + 572 .LVL63: +2816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t count; + 573 .loc 1 2816 24 view .LVU180 + 574 000c 0746 mov r7, r0 + 575 .LVL64: +2817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t *pData = pSDstatus; + 576 .loc 1 2817 3 is_stmt 1 view .LVU181 +2818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 577 .loc 1 2818 3 view .LVU182 +2821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 578 .loc 1 2821 3 view .LVU183 +2821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 579 .loc 1 2821 7 is_stmt 0 view .LVU184 + 580 000e 0021 movs r1, #0 + 581 0010 2868 ldr r0, [r5] + 582 .LVL65: +2821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 583 .loc 1 2821 7 view .LVU185 + 584 0012 FFF7FEFF bl SDMMC_GetResponse + 585 .LVL66: +2821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 586 .loc 1 2821 5 discriminator 1 view .LVU186 + 587 0016 10F0007F tst r0, #33554432 + 588 001a 66D1 bne .L48 +2827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 589 .loc 1 2827 3 is_stmt 1 view .LVU187 +2827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 590 .loc 1 2827 16 is_stmt 0 view .LVU188 + 591 001c 4021 movs r1, #64 + 592 001e 2868 ldr r0, [r5] + 593 0020 FFF7FEFF bl SDMMC_CmdBlockLength + 594 .LVL67: +2828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 595 .loc 1 2828 3 is_stmt 1 view .LVU189 +2828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + ARM GAS /tmp/ccMMu31U.s page 70 + + + 596 .loc 1 2828 5 is_stmt 0 view .LVU190 + 597 0024 0346 mov r3, r0 + 598 0026 10B1 cbz r0, .L39 +2830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; + 599 .loc 1 2830 5 is_stmt 1 view .LVU191 +2830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; + 600 .loc 1 2830 8 is_stmt 0 view .LVU192 + 601 0028 AA6B ldr r2, [r5, #56] +2830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; + 602 .loc 1 2830 20 view .LVU193 + 603 002a AA63 str r2, [r5, #56] +2831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 604 .loc 1 2831 5 is_stmt 1 view .LVU194 +2831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 605 .loc 1 2831 12 is_stmt 0 view .LVU195 + 606 002c 5FE0 b .L37 + 607 .L39: +2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 608 .loc 1 2835 3 is_stmt 1 view .LVU196 +2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 609 .loc 1 2835 73 is_stmt 0 view .LVU197 + 610 002e 296D ldr r1, [r5, #80] +2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 611 .loc 1 2835 16 view .LVU198 + 612 0030 0904 lsls r1, r1, #16 + 613 0032 2868 ldr r0, [r5] + 614 .LVL68: +2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 615 .loc 1 2835 16 view .LVU199 + 616 0034 FFF7FEFF bl SDMMC_CmdAppCommand + 617 .LVL69: +2836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 618 .loc 1 2836 3 is_stmt 1 view .LVU200 +2836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 619 .loc 1 2836 5 is_stmt 0 view .LVU201 + 620 0038 0346 mov r3, r0 + 621 003a 10B1 cbz r0, .L40 +2838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; + 622 .loc 1 2838 5 is_stmt 1 view .LVU202 +2838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; + 623 .loc 1 2838 8 is_stmt 0 view .LVU203 + 624 003c AA6B ldr r2, [r5, #56] +2838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; + 625 .loc 1 2838 20 view .LVU204 + 626 003e AA63 str r2, [r5, #56] +2839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 627 .loc 1 2839 5 is_stmt 1 view .LVU205 +2839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 628 .loc 1 2839 12 is_stmt 0 view .LVU206 + 629 0040 55E0 b .L37 + 630 .L40: +2843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = 64U; + 631 .loc 1 2843 3 is_stmt 1 view .LVU207 +2843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = 64U; + 632 .loc 1 2843 24 is_stmt 0 view .LVU208 + 633 0042 4FF0FF33 mov r3, #-1 + 634 0046 0093 str r3, [sp] + ARM GAS /tmp/ccMMu31U.s page 71 + + +2844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B; + 635 .loc 1 2844 3 is_stmt 1 view .LVU209 +2844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B; + 636 .loc 1 2844 24 is_stmt 0 view .LVU210 + 637 0048 4023 movs r3, #64 + 638 004a 0193 str r3, [sp, #4] +2845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + 639 .loc 1 2845 3 is_stmt 1 view .LVU211 +2845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + 640 .loc 1 2845 24 is_stmt 0 view .LVU212 + 641 004c 6023 movs r3, #96 + 642 004e 0293 str r3, [sp, #8] +2846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + 643 .loc 1 2846 3 is_stmt 1 view .LVU213 +2846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + 644 .loc 1 2846 24 is_stmt 0 view .LVU214 + 645 0050 0223 movs r3, #2 + 646 0052 0393 str r3, [sp, #12] +2847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; + 647 .loc 1 2847 3 is_stmt 1 view .LVU215 +2847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; + 648 .loc 1 2847 24 is_stmt 0 view .LVU216 + 649 0054 0023 movs r3, #0 + 650 0056 0493 str r3, [sp, #16] +2848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); + 651 .loc 1 2848 3 is_stmt 1 view .LVU217 +2848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); + 652 .loc 1 2848 24 is_stmt 0 view .LVU218 + 653 0058 0123 movs r3, #1 + 654 005a 0593 str r3, [sp, #20] +2849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 655 .loc 1 2849 3 is_stmt 1 view .LVU219 +2849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 656 .loc 1 2849 9 is_stmt 0 view .LVU220 + 657 005c 6946 mov r1, sp + 658 005e 2868 ldr r0, [r5] + 659 .LVL70: +2849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 660 .loc 1 2849 9 view .LVU221 + 661 0060 FFF7FEFF bl SDMMC_ConfigData + 662 .LVL71: +2852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 663 .loc 1 2852 3 is_stmt 1 view .LVU222 +2852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 664 .loc 1 2852 16 is_stmt 0 view .LVU223 + 665 0064 2868 ldr r0, [r5] + 666 0066 FFF7FEFF bl SDMMC_CmdStatusRegister + 667 .LVL72: +2853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 668 .loc 1 2853 3 is_stmt 1 view .LVU224 +2853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 669 .loc 1 2853 5 is_stmt 0 view .LVU225 + 670 006a 0346 mov r3, r0 + 671 006c 80B1 cbz r0, .L41 +2855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; + 672 .loc 1 2855 5 is_stmt 1 view .LVU226 +2855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; + ARM GAS /tmp/ccMMu31U.s page 72 + + + 673 .loc 1 2855 8 is_stmt 0 view .LVU227 + 674 006e AA6B ldr r2, [r5, #56] +2855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return errorstate; + 675 .loc 1 2855 20 view .LVU228 + 676 0070 AA63 str r2, [r5, #56] +2856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 677 .loc 1 2856 5 is_stmt 1 view .LVU229 +2856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 678 .loc 1 2856 12 is_stmt 0 view .LVU230 + 679 0072 3CE0 b .L37 + 680 .LVL73: + 681 .L44: +2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pData++; + 682 .loc 1 2866 9 is_stmt 1 view .LVU231 +2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pData++; + 683 .loc 1 2866 18 is_stmt 0 view .LVU232 + 684 0074 2868 ldr r0, [r5] + 685 0076 FFF7FEFF bl SDMMC_ReadFIFO + 686 .LVL74: +2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pData++; + 687 .loc 1 2866 16 discriminator 1 view .LVU233 + 688 007a 46F8040B str r0, [r6], #4 + 689 .LVL75: +2867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 690 .loc 1 2867 9 is_stmt 1 view .LVU234 +2864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 691 .loc 1 2864 40 discriminator 3 view .LVU235 + 692 007e 0134 adds r4, r4, #1 + 693 .LVL76: + 694 .L42: +2864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 695 .loc 1 2864 29 discriminator 1 view .LVU236 + 696 0080 072C cmp r4, #7 + 697 0082 F7D9 bls .L44 + 698 .LVL77: + 699 .L43: +2871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 700 .loc 1 2871 5 view .LVU237 +2871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 701 .loc 1 2871 9 is_stmt 0 view .LVU238 + 702 0084 FFF7FEFF bl HAL_GetTick + 703 .LVL78: +2871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 704 .loc 1 2871 23 discriminator 1 view .LVU239 + 705 0088 C01B subs r0, r0, r7 +2871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 706 .loc 1 2871 7 discriminator 1 view .LVU240 + 707 008a B0F1FF3F cmp r0, #-1 + 708 008e 31D0 beq .L49 + 709 .L41: +2860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 710 .loc 1 2860 9 is_stmt 1 view .LVU241 +2860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 711 .loc 1 2860 10 is_stmt 0 view .LVU242 + 712 0090 2B68 ldr r3, [r5] + 713 0092 5C6B ldr r4, [r3, #52] + 714 0094 40F22A42 movw r2, #1066 + ARM GAS /tmp/ccMMu31U.s page 73 + + +2860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 715 .loc 1 2860 9 view .LVU243 + 716 0098 1440 ands r4, r4, r2 + 717 009a 04D1 bne .L55 +2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 718 .loc 1 2862 5 is_stmt 1 view .LVU244 +2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 719 .loc 1 2862 8 is_stmt 0 view .LVU245 + 720 009c 5B6B ldr r3, [r3, #52] +2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 721 .loc 1 2862 7 view .LVU246 + 722 009e 13F4004F tst r3, #32768 + 723 00a2 EFD0 beq .L43 + 724 00a4 ECE7 b .L42 + 725 .L55: +2877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 726 .loc 1 2877 3 is_stmt 1 view .LVU247 +2877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 727 .loc 1 2877 6 is_stmt 0 view .LVU248 + 728 00a6 5A6B ldr r2, [r3, #52] +2877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 729 .loc 1 2877 5 view .LVU249 + 730 00a8 12F0080F tst r2, #8 + 731 00ac 25D1 bne .L50 +2881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 732 .loc 1 2881 8 is_stmt 1 view .LVU250 +2881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 733 .loc 1 2881 11 is_stmt 0 view .LVU251 + 734 00ae 5A6B ldr r2, [r3, #52] +2881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 735 .loc 1 2881 10 view .LVU252 + 736 00b0 12F0020F tst r2, #2 + 737 00b4 23D1 bne .L51 +2885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 738 .loc 1 2885 8 is_stmt 1 view .LVU253 +2885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 739 .loc 1 2885 11 is_stmt 0 view .LVU254 + 740 00b6 5B6B ldr r3, [r3, #52] +2885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 741 .loc 1 2885 10 view .LVU255 + 742 00b8 13F0200F tst r3, #32 + 743 00bc 21D1 bne .L56 + 744 .L46: +2894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 745 .loc 1 2894 11 is_stmt 1 view .LVU256 + 746 00be 2868 ldr r0, [r5] + 747 00c0 436B ldr r3, [r0, #52] + 748 00c2 13F40013 ands r3, r3, #2097152 + 749 00c6 0CD0 beq .L57 +2896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pData++; + 750 .loc 1 2896 5 view .LVU257 +2896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pData++; + 751 .loc 1 2896 14 is_stmt 0 view .LVU258 + 752 00c8 FFF7FEFF bl SDMMC_ReadFIFO + 753 .LVL79: +2896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pData++; + 754 .loc 1 2896 12 discriminator 1 view .LVU259 + ARM GAS /tmp/ccMMu31U.s page 74 + + + 755 00cc 46F8040B str r0, [r6], #4 + 756 .LVL80: +2897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 757 .loc 1 2897 5 is_stmt 1 view .LVU260 +2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 758 .loc 1 2899 5 view .LVU261 +2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 759 .loc 1 2899 9 is_stmt 0 view .LVU262 + 760 00d0 FFF7FEFF bl HAL_GetTick + 761 .LVL81: +2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 762 .loc 1 2899 23 discriminator 1 view .LVU263 + 763 00d4 C01B subs r0, r0, r7 +2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 764 .loc 1 2899 7 discriminator 1 view .LVU264 + 765 00d6 B0F1FF3F cmp r0, #-1 + 766 00da F0D1 bne .L46 +2901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 767 .loc 1 2901 14 view .LVU265 + 768 00dc 4FF00043 mov r3, #-2147483648 + 769 00e0 05E0 b .L37 + 770 .L57: +2906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 771 .loc 1 2906 3 is_stmt 1 view .LVU266 + 772 00e2 40F23A52 movw r2, #1338 + 773 00e6 8263 str r2, [r0, #56] +2908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 774 .loc 1 2908 3 view .LVU267 +2908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 775 .loc 1 2908 10 is_stmt 0 view .LVU268 + 776 00e8 01E0 b .L37 + 777 .LVL82: + 778 .L48: +2823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 779 .loc 1 2823 12 view .LVU269 + 780 00ea 4FF40063 mov r3, #2048 + 781 .LVL83: + 782 .L37: +2909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 783 .loc 1 2909 1 view .LVU270 + 784 00ee 1846 mov r0, r3 + 785 00f0 07B0 add sp, sp, #28 + 786 .LCFI12: + 787 .cfi_remember_state + 788 .cfi_def_cfa_offset 20 + 789 @ sp needed + 790 00f2 F0BD pop {r4, r5, r6, r7, pc} + 791 .LVL84: + 792 .L49: + 793 .LCFI13: + 794 .cfi_restore_state +2873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 795 .loc 1 2873 14 view .LVU271 + 796 00f4 4FF00043 mov r3, #-2147483648 + 797 00f8 F9E7 b .L37 + 798 .L50: +2879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + ARM GAS /tmp/ccMMu31U.s page 75 + + + 799 .loc 1 2879 12 view .LVU272 + 800 00fa 0823 movs r3, #8 + 801 00fc F7E7 b .L37 + 802 .L51: +2883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 803 .loc 1 2883 12 view .LVU273 + 804 00fe 0223 movs r3, #2 + 805 0100 F5E7 b .L37 + 806 .L56: +2887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 807 .loc 1 2887 12 view .LVU274 + 808 0102 2023 movs r3, #32 + 809 0104 F3E7 b .L37 + 810 .cfi_endproc + 811 .LFE176: + 813 .section .text.SD_FindSCR,"ax",%progbits + 814 .align 1 + 815 .syntax unified + 816 .thumb + 817 .thumb_func + 819 SD_FindSCR: + 820 .LVL85: + 821 .LFB180: +3042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; + 822 .loc 1 3042 1 is_stmt 1 view -0 + 823 .cfi_startproc + 824 @ args = 0, pretend = 0, frame = 32 + 825 @ frame_needed = 0, uses_anonymous_args = 0 +3042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; + 826 .loc 1 3042 1 is_stmt 0 view .LVU276 + 827 0000 F0B5 push {r4, r5, r6, r7, lr} + 828 .LCFI14: + 829 .cfi_def_cfa_offset 20 + 830 .cfi_offset 4, -20 + 831 .cfi_offset 5, -16 + 832 .cfi_offset 6, -12 + 833 .cfi_offset 7, -8 + 834 .cfi_offset 14, -4 + 835 0002 89B0 sub sp, sp, #36 + 836 .LCFI15: + 837 .cfi_def_cfa_offset 56 + 838 0004 0446 mov r4, r0 + 839 0006 0F46 mov r7, r1 +3043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 840 .loc 1 3043 3 is_stmt 1 view .LVU277 +3044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t tickstart = HAL_GetTick(); + 841 .loc 1 3044 3 view .LVU278 +3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t index = 0U; + 842 .loc 1 3045 3 view .LVU279 +3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t index = 0U; + 843 .loc 1 3045 24 is_stmt 0 view .LVU280 + 844 0008 FFF7FEFF bl HAL_GetTick + 845 .LVL86: +3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t index = 0U; + 846 .loc 1 3045 24 view .LVU281 + 847 000c 0646 mov r6, r0 + 848 .LVL87: + ARM GAS /tmp/ccMMu31U.s page 76 + + +3046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t tempscr[2U] = {0U, 0U}; + 849 .loc 1 3046 3 is_stmt 1 view .LVU282 +3047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t *scr = pSCR; + 850 .loc 1 3047 3 view .LVU283 +3047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t *scr = pSCR; + 851 .loc 1 3047 12 is_stmt 0 view .LVU284 + 852 000e 0023 movs r3, #0 + 853 0010 0093 str r3, [sp] + 854 0012 0193 str r3, [sp, #4] +3048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 855 .loc 1 3048 3 is_stmt 1 view .LVU285 + 856 .LVL88: +3051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 857 .loc 1 3051 3 view .LVU286 +3051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 858 .loc 1 3051 16 is_stmt 0 view .LVU287 + 859 0014 0821 movs r1, #8 + 860 0016 2068 ldr r0, [r4] + 861 .LVL89: +3051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 862 .loc 1 3051 16 view .LVU288 + 863 0018 FFF7FEFF bl SDMMC_CmdBlockLength + 864 .LVL90: +3052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 865 .loc 1 3052 3 is_stmt 1 view .LVU289 +3052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 866 .loc 1 3052 5 is_stmt 0 view .LVU290 + 867 001c 0546 mov r5, r0 + 868 001e 10B1 cbz r0, .L70 + 869 .LVL91: + 870 .L58: +3130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 871 .loc 1 3130 1 view .LVU291 + 872 0020 2846 mov r0, r5 + 873 0022 09B0 add sp, sp, #36 + 874 .LCFI16: + 875 .cfi_remember_state + 876 .cfi_def_cfa_offset 20 + 877 @ sp needed + 878 0024 F0BD pop {r4, r5, r6, r7, pc} + 879 .LVL92: + 880 .L70: + 881 .LCFI17: + 882 .cfi_restore_state +3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 883 .loc 1 3058 3 is_stmt 1 view .LVU292 +3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 884 .loc 1 3058 74 is_stmt 0 view .LVU293 + 885 0026 216D ldr r1, [r4, #80] +3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 886 .loc 1 3058 16 view .LVU294 + 887 0028 0904 lsls r1, r1, #16 + 888 002a 2068 ldr r0, [r4] + 889 .LVL93: +3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 890 .loc 1 3058 16 view .LVU295 + 891 002c FFF7FEFF bl SDMMC_CmdAppCommand + ARM GAS /tmp/ccMMu31U.s page 77 + + + 892 .LVL94: +3059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 893 .loc 1 3059 3 is_stmt 1 view .LVU296 +3059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 894 .loc 1 3059 5 is_stmt 0 view .LVU297 + 895 0030 0546 mov r5, r0 + 896 0032 0028 cmp r0, #0 + 897 0034 F4D1 bne .L58 +3064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = 8U; + 898 .loc 1 3064 3 is_stmt 1 view .LVU298 +3064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = 8U; + 899 .loc 1 3064 24 is_stmt 0 view .LVU299 + 900 0036 4FF0FF33 mov r3, #-1 + 901 003a 0293 str r3, [sp, #8] +3065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B; + 902 .loc 1 3065 3 is_stmt 1 view .LVU300 +3065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B; + 903 .loc 1 3065 24 is_stmt 0 view .LVU301 + 904 003c 0823 movs r3, #8 + 905 003e 0393 str r3, [sp, #12] +3066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + 906 .loc 1 3066 3 is_stmt 1 view .LVU302 +3066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + 907 .loc 1 3066 24 is_stmt 0 view .LVU303 + 908 0040 3023 movs r3, #48 + 909 0042 0493 str r3, [sp, #16] +3067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + 910 .loc 1 3067 3 is_stmt 1 view .LVU304 +3067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + 911 .loc 1 3067 24 is_stmt 0 view .LVU305 + 912 0044 0223 movs r3, #2 + 913 0046 0593 str r3, [sp, #20] +3068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; + 914 .loc 1 3068 3 is_stmt 1 view .LVU306 +3068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; + 915 .loc 1 3068 24 is_stmt 0 view .LVU307 + 916 0048 0023 movs r3, #0 + 917 004a 0693 str r3, [sp, #24] +3069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); + 918 .loc 1 3069 3 is_stmt 1 view .LVU308 +3069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); + 919 .loc 1 3069 24 is_stmt 0 view .LVU309 + 920 004c 0123 movs r3, #1 + 921 004e 0793 str r3, [sp, #28] +3070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 922 .loc 1 3070 3 is_stmt 1 view .LVU310 +3070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 923 .loc 1 3070 9 is_stmt 0 view .LVU311 + 924 0050 02A9 add r1, sp, #8 + 925 0052 2068 ldr r0, [r4] + 926 .LVL95: +3070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 927 .loc 1 3070 9 view .LVU312 + 928 0054 FFF7FEFF bl SDMMC_ConfigData + 929 .LVL96: +3073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 930 .loc 1 3073 3 is_stmt 1 view .LVU313 + ARM GAS /tmp/ccMMu31U.s page 78 + + +3073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 931 .loc 1 3073 16 is_stmt 0 view .LVU314 + 932 0058 2068 ldr r0, [r4] + 933 005a FFF7FEFF bl SDMMC_CmdSendSCR + 934 .LVL97: +3074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 935 .loc 1 3074 3 is_stmt 1 view .LVU315 +3074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 936 .loc 1 3074 5 is_stmt 0 view .LVU316 + 937 005e 0546 mov r5, r0 + 938 0060 58B1 cbz r0, .L60 + 939 0062 DDE7 b .L58 + 940 .LVL98: + 941 .L71: +3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** index++; + 942 .loc 1 3083 7 is_stmt 1 view .LVU317 +3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** index++; + 943 .loc 1 3083 28 is_stmt 0 view .LVU318 + 944 0064 FFF7FEFF bl SDMMC_ReadFIFO + 945 .LVL99: +3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** index++; + 946 .loc 1 3083 26 discriminator 1 view .LVU319 + 947 0068 4DF82500 str r0, [sp, r5, lsl #2] +3084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 948 .loc 1 3084 7 is_stmt 1 view .LVU320 +3084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 949 .loc 1 3084 12 is_stmt 0 view .LVU321 + 950 006c 0135 adds r5, r5, #1 + 951 .LVL100: + 952 .L62: +3091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 953 .loc 1 3091 5 is_stmt 1 view .LVU322 +3091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 954 .loc 1 3091 9 is_stmt 0 view .LVU323 + 955 006e FFF7FEFF bl HAL_GetTick + 956 .LVL101: +3091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 957 .loc 1 3091 23 discriminator 1 view .LVU324 + 958 0072 831B subs r3, r0, r6 +3091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 959 .loc 1 3091 7 discriminator 1 view .LVU325 + 960 0074 B3F1FF3F cmp r3, #-1 + 961 0078 3FD0 beq .L68 + 962 .LVL102: + 963 .L60: +3079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 964 .loc 1 3079 9 is_stmt 1 view .LVU326 +3079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 965 .loc 1 3079 10 is_stmt 0 view .LVU327 + 966 007a 2068 ldr r0, [r4] + 967 007c 436B ldr r3, [r0, #52] +3079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 968 .loc 1 3079 9 view .LVU328 + 969 007e 13F02A0F tst r3, #42 + 970 0082 07D1 bne .L63 +3081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 971 .loc 1 3081 5 is_stmt 1 view .LVU329 + ARM GAS /tmp/ccMMu31U.s page 79 + + +3081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 972 .loc 1 3081 8 is_stmt 0 view .LVU330 + 973 0084 436B ldr r3, [r0, #52] +3081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 974 .loc 1 3081 7 view .LVU331 + 975 0086 13F4001F tst r3, #2097152 + 976 008a EBD1 bne .L71 +3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 977 .loc 1 3086 10 is_stmt 1 view .LVU332 +3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 978 .loc 1 3086 14 is_stmt 0 view .LVU333 + 979 008c 436B ldr r3, [r0, #52] +3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 980 .loc 1 3086 12 view .LVU334 + 981 008e 13F4005F tst r3, #8192 + 982 0092 ECD1 bne .L62 + 983 .L63: +3097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 984 .loc 1 3097 3 is_stmt 1 view .LVU335 +3097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 985 .loc 1 3097 6 is_stmt 0 view .LVU336 + 986 0094 436B ldr r3, [r0, #52] +3097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 987 .loc 1 3097 5 view .LVU337 + 988 0096 13F0080F tst r3, #8 + 989 009a 25D1 bne .L72 +3103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 990 .loc 1 3103 8 is_stmt 1 view .LVU338 +3103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 991 .loc 1 3103 11 is_stmt 0 view .LVU339 + 992 009c 436B ldr r3, [r0, #52] +3103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 993 .loc 1 3103 10 view .LVU340 + 994 009e 13F0020F tst r3, #2 + 995 00a2 24D1 bne .L73 +3109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 996 .loc 1 3109 8 is_stmt 1 view .LVU341 +3109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 997 .loc 1 3109 11 is_stmt 0 view .LVU342 + 998 00a4 456B ldr r5, [r0, #52] + 999 .LVL103: +3109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1000 .loc 1 3109 10 view .LVU343 + 1001 00a6 15F02005 ands r5, r5, #32 + 1002 00aa 23D1 bne .L74 +3119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1003 .loc 1 3119 5 is_stmt 1 view .LVU344 + 1004 00ac 40F23A53 movw r3, #1338 + 1005 00b0 8363 str r3, [r0, #56] +3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); + 1006 .loc 1 3121 5 view .LVU345 +3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); + 1007 .loc 1 3121 22 is_stmt 0 view .LVU346 + 1008 00b2 019A ldr r2, [sp, #4] +3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); + 1009 .loc 1 3121 86 view .LVU347 + 1010 00b4 1302 lsls r3, r2, #8 + ARM GAS /tmp/ccMMu31U.s page 80 + + + 1011 00b6 03F47F03 and r3, r3, #16711680 +3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); + 1012 .loc 1 3121 52 view .LVU348 + 1013 00ba 43EA0263 orr r3, r3, r2, lsl #24 +3122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** scr++; + 1014 .loc 1 3122 46 view .LVU349 + 1015 00be 110A lsrs r1, r2, #8 + 1016 00c0 01F47F41 and r1, r1, #65280 +3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); + 1017 .loc 1 3121 92 view .LVU350 + 1018 00c4 0B43 orrs r3, r3, r1 +3122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** scr++; + 1019 .loc 1 3122 52 view .LVU351 + 1020 00c6 43EA1263 orr r3, r3, r2, lsr #24 +3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); + 1021 .loc 1 3121 10 view .LVU352 + 1022 00ca 3B60 str r3, [r7] +3123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ + 1023 .loc 1 3123 5 is_stmt 1 view .LVU353 + 1024 .LVL104: +3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); + 1025 .loc 1 3124 5 view .LVU354 +3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); + 1026 .loc 1 3124 22 is_stmt 0 view .LVU355 + 1027 00cc 009A ldr r2, [sp] +3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); + 1028 .loc 1 3124 86 view .LVU356 + 1029 00ce 1302 lsls r3, r2, #8 + 1030 00d0 03F47F03 and r3, r3, #16711680 +3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); + 1031 .loc 1 3124 52 view .LVU357 + 1032 00d4 43EA0263 orr r3, r3, r2, lsl #24 +3125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1033 .loc 1 3125 46 view .LVU358 + 1034 00d8 110A lsrs r1, r2, #8 + 1035 00da 01F47F41 and r1, r1, #65280 +3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); + 1036 .loc 1 3124 92 view .LVU359 + 1037 00de 0B43 orrs r3, r3, r1 +3125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1038 .loc 1 3125 52 view .LVU360 + 1039 00e0 43EA1263 orr r3, r3, r2, lsr #24 +3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); + 1040 .loc 1 3124 10 view .LVU361 + 1041 00e4 7B60 str r3, [r7, #4] +3129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1042 .loc 1 3129 3 is_stmt 1 view .LVU362 +3129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1043 .loc 1 3129 10 is_stmt 0 view .LVU363 + 1044 00e6 9BE7 b .L58 + 1045 .LVL105: + 1046 .L72: +3099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1047 .loc 1 3099 5 is_stmt 1 view .LVU364 + 1048 00e8 0825 movs r5, #8 + 1049 .LVL106: +3099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + ARM GAS /tmp/ccMMu31U.s page 81 + + + 1050 .loc 1 3099 5 is_stmt 0 view .LVU365 + 1051 00ea 8563 str r5, [r0, #56] +3101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1052 .loc 1 3101 5 is_stmt 1 view .LVU366 +3101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1053 .loc 1 3101 12 is_stmt 0 view .LVU367 + 1054 00ec 98E7 b .L58 + 1055 .LVL107: + 1056 .L73: +3105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1057 .loc 1 3105 5 is_stmt 1 view .LVU368 + 1058 00ee 0225 movs r5, #2 + 1059 .LVL108: +3105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1060 .loc 1 3105 5 is_stmt 0 view .LVU369 + 1061 00f0 8563 str r5, [r0, #56] +3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1062 .loc 1 3107 5 is_stmt 1 view .LVU370 +3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1063 .loc 1 3107 12 is_stmt 0 view .LVU371 + 1064 00f2 95E7 b .L58 + 1065 .L74: +3111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1066 .loc 1 3111 5 is_stmt 1 view .LVU372 + 1067 00f4 2025 movs r5, #32 + 1068 00f6 8563 str r5, [r0, #56] +3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1069 .loc 1 3113 5 view .LVU373 +3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1070 .loc 1 3113 12 is_stmt 0 view .LVU374 + 1071 00f8 92E7 b .L58 + 1072 .LVL109: + 1073 .L68: +3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1074 .loc 1 3093 14 view .LVU375 + 1075 00fa 4FF00045 mov r5, #-2147483648 + 1076 .LVL110: +3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1077 .loc 1 3093 14 view .LVU376 + 1078 00fe 8FE7 b .L58 + 1079 .cfi_endproc + 1080 .LFE180: + 1082 .section .text.SD_WideBus_Enable,"ax",%progbits + 1083 .align 1 + 1084 .syntax unified + 1085 .thumb + 1086 .thumb_func + 1088 SD_WideBus_Enable: + 1089 .LVL111: + 1090 .LFB178: +2946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t scr[2U] = {0U, 0U}; + 1091 .loc 1 2946 1 is_stmt 1 view -0 + 1092 .cfi_startproc + 1093 @ args = 0, pretend = 0, frame = 8 + 1094 @ frame_needed = 0, uses_anonymous_args = 0 +2946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t scr[2U] = {0U, 0U}; + 1095 .loc 1 2946 1 is_stmt 0 view .LVU378 + ARM GAS /tmp/ccMMu31U.s page 82 + + + 1096 0000 10B5 push {r4, lr} + 1097 .LCFI18: + 1098 .cfi_def_cfa_offset 8 + 1099 .cfi_offset 4, -8 + 1100 .cfi_offset 14, -4 + 1101 0002 82B0 sub sp, sp, #8 + 1102 .LCFI19: + 1103 .cfi_def_cfa_offset 16 + 1104 0004 0446 mov r4, r0 +2947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 1105 .loc 1 2947 3 is_stmt 1 view .LVU379 +2947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 1106 .loc 1 2947 12 is_stmt 0 view .LVU380 + 1107 0006 0021 movs r1, #0 + 1108 0008 0091 str r1, [sp] + 1109 000a 0191 str r1, [sp, #4] +2948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1110 .loc 1 2948 3 is_stmt 1 view .LVU381 +2950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1111 .loc 1 2950 3 view .LVU382 +2950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1112 .loc 1 2950 7 is_stmt 0 view .LVU383 + 1113 000c 0068 ldr r0, [r0] + 1114 .LVL112: +2950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1115 .loc 1 2950 7 view .LVU384 + 1116 000e FFF7FEFF bl SDMMC_GetResponse + 1117 .LVL113: +2950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1118 .loc 1 2950 5 discriminator 1 view .LVU385 + 1119 0012 10F0007F tst r0, #33554432 + 1120 0016 13D1 bne .L77 +2956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1121 .loc 1 2956 3 is_stmt 1 view .LVU386 +2956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1122 .loc 1 2956 16 is_stmt 0 view .LVU387 + 1123 0018 6946 mov r1, sp + 1124 001a 2046 mov r0, r4 + 1125 001c FFF7FEFF bl SD_FindSCR + 1126 .LVL114: +2957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1127 .loc 1 2957 3 is_stmt 1 view .LVU388 +2957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1128 .loc 1 2957 5 is_stmt 0 view .LVU389 + 1129 0020 80B9 cbnz r0, .L75 +2963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1130 .loc 1 2963 3 is_stmt 1 view .LVU390 +2963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1131 .loc 1 2963 5 is_stmt 0 view .LVU391 + 1132 0022 019B ldr r3, [sp, #4] + 1133 0024 13F4802F tst r3, #262144 + 1134 0028 0ED0 beq .L78 +2966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1135 .loc 1 2966 5 is_stmt 1 view .LVU392 +2966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1136 .loc 1 2966 75 is_stmt 0 view .LVU393 + 1137 002a 216D ldr r1, [r4, #80] + ARM GAS /tmp/ccMMu31U.s page 83 + + +2966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1138 .loc 1 2966 18 view .LVU394 + 1139 002c 0904 lsls r1, r1, #16 + 1140 002e 2068 ldr r0, [r4] + 1141 .LVL115: +2966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1142 .loc 1 2966 18 view .LVU395 + 1143 0030 FFF7FEFF bl SDMMC_CmdAppCommand + 1144 .LVL116: +2967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1145 .loc 1 2967 5 is_stmt 1 view .LVU396 +2967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1146 .loc 1 2967 7 is_stmt 0 view .LVU397 + 1147 0034 30B9 cbnz r0, .L75 +2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1148 .loc 1 2973 5 is_stmt 1 view .LVU398 +2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1149 .loc 1 2973 18 is_stmt 0 view .LVU399 + 1150 0036 0221 movs r1, #2 + 1151 0038 2068 ldr r0, [r4] + 1152 .LVL117: +2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1153 .loc 1 2973 18 view .LVU400 + 1154 003a FFF7FEFF bl SDMMC_CmdBusWidth + 1155 .LVL118: +2974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1156 .loc 1 2974 5 is_stmt 1 view .LVU401 + 1157 003e 01E0 b .L75 + 1158 .LVL119: + 1159 .L77: +2952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1160 .loc 1 2952 12 is_stmt 0 view .LVU402 + 1161 0040 4FF40060 mov r0, #2048 + 1162 .L75: +2985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1163 .loc 1 2985 1 view .LVU403 + 1164 0044 02B0 add sp, sp, #8 + 1165 .LCFI20: + 1166 .cfi_remember_state + 1167 .cfi_def_cfa_offset 8 + 1168 @ sp needed + 1169 0046 10BD pop {r4, pc} + 1170 .LVL120: + 1171 .L78: + 1172 .LCFI21: + 1173 .cfi_restore_state +2983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1174 .loc 1 2983 12 view .LVU404 + 1175 0048 4FF08060 mov r0, #67108864 + 1176 .LVL121: +2983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1177 .loc 1 2983 12 view .LVU405 + 1178 004c FAE7 b .L75 + 1179 .cfi_endproc + 1180 .LFE178: + 1182 .section .text.SD_WideBus_Disable,"ax",%progbits + 1183 .align 1 + ARM GAS /tmp/ccMMu31U.s page 84 + + + 1184 .syntax unified + 1185 .thumb + 1186 .thumb_func + 1188 SD_WideBus_Disable: + 1189 .LVL122: + 1190 .LFB179: +2993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t scr[2U] = {0U, 0U}; + 1191 .loc 1 2993 1 is_stmt 1 view -0 + 1192 .cfi_startproc + 1193 @ args = 0, pretend = 0, frame = 8 + 1194 @ frame_needed = 0, uses_anonymous_args = 0 +2993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t scr[2U] = {0U, 0U}; + 1195 .loc 1 2993 1 is_stmt 0 view .LVU407 + 1196 0000 10B5 push {r4, lr} + 1197 .LCFI22: + 1198 .cfi_def_cfa_offset 8 + 1199 .cfi_offset 4, -8 + 1200 .cfi_offset 14, -4 + 1201 0002 82B0 sub sp, sp, #8 + 1202 .LCFI23: + 1203 .cfi_def_cfa_offset 16 + 1204 0004 0446 mov r4, r0 +2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 1205 .loc 1 2994 3 is_stmt 1 view .LVU408 +2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 1206 .loc 1 2994 12 is_stmt 0 view .LVU409 + 1207 0006 0021 movs r1, #0 + 1208 0008 0091 str r1, [sp] + 1209 000a 0191 str r1, [sp, #4] +2995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1210 .loc 1 2995 3 is_stmt 1 view .LVU410 +2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1211 .loc 1 2997 3 view .LVU411 +2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1212 .loc 1 2997 7 is_stmt 0 view .LVU412 + 1213 000c 0068 ldr r0, [r0] + 1214 .LVL123: +2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1215 .loc 1 2997 7 view .LVU413 + 1216 000e FFF7FEFF bl SDMMC_GetResponse + 1217 .LVL124: +2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1218 .loc 1 2997 5 discriminator 1 view .LVU414 + 1219 0012 10F0007F tst r0, #33554432 + 1220 0016 13D1 bne .L82 +3003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1221 .loc 1 3003 3 is_stmt 1 view .LVU415 +3003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1222 .loc 1 3003 16 is_stmt 0 view .LVU416 + 1223 0018 6946 mov r1, sp + 1224 001a 2046 mov r0, r4 + 1225 001c FFF7FEFF bl SD_FindSCR + 1226 .LVL125: +3004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1227 .loc 1 3004 3 is_stmt 1 view .LVU417 +3004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1228 .loc 1 3004 5 is_stmt 0 view .LVU418 + ARM GAS /tmp/ccMMu31U.s page 85 + + + 1229 0020 80B9 cbnz r0, .L80 +3010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1230 .loc 1 3010 3 is_stmt 1 view .LVU419 +3010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1231 .loc 1 3010 5 is_stmt 0 view .LVU420 + 1232 0022 019B ldr r3, [sp, #4] + 1233 0024 13F4803F tst r3, #65536 + 1234 0028 0ED0 beq .L83 +3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1235 .loc 1 3013 5 is_stmt 1 view .LVU421 +3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1236 .loc 1 3013 75 is_stmt 0 view .LVU422 + 1237 002a 216D ldr r1, [r4, #80] +3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1238 .loc 1 3013 18 view .LVU423 + 1239 002c 0904 lsls r1, r1, #16 + 1240 002e 2068 ldr r0, [r4] + 1241 .LVL126: +3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1242 .loc 1 3013 18 view .LVU424 + 1243 0030 FFF7FEFF bl SDMMC_CmdAppCommand + 1244 .LVL127: +3014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1245 .loc 1 3014 5 is_stmt 1 view .LVU425 +3014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1246 .loc 1 3014 7 is_stmt 0 view .LVU426 + 1247 0034 30B9 cbnz r0, .L80 +3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1248 .loc 1 3020 5 is_stmt 1 view .LVU427 +3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1249 .loc 1 3020 18 is_stmt 0 view .LVU428 + 1250 0036 0021 movs r1, #0 + 1251 0038 2068 ldr r0, [r4] + 1252 .LVL128: +3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1253 .loc 1 3020 18 view .LVU429 + 1254 003a FFF7FEFF bl SDMMC_CmdBusWidth + 1255 .LVL129: +3021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1256 .loc 1 3021 5 is_stmt 1 view .LVU430 + 1257 003e 01E0 b .L80 + 1258 .LVL130: + 1259 .L82: +2999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1260 .loc 1 2999 12 is_stmt 0 view .LVU431 + 1261 0040 4FF40060 mov r0, #2048 + 1262 .L80: +3032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1263 .loc 1 3032 1 view .LVU432 + 1264 0044 02B0 add sp, sp, #8 + 1265 .LCFI24: + 1266 .cfi_remember_state + 1267 .cfi_def_cfa_offset 8 + 1268 @ sp needed + 1269 0046 10BD pop {r4, pc} + 1270 .LVL131: + 1271 .L83: + ARM GAS /tmp/ccMMu31U.s page 86 + + + 1272 .LCFI25: + 1273 .cfi_restore_state +3030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1274 .loc 1 3030 12 view .LVU433 + 1275 0048 4FF08060 mov r0, #67108864 + 1276 .LVL132: +3030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1277 .loc 1 3030 12 view .LVU434 + 1278 004c FAE7 b .L80 + 1279 .cfi_endproc + 1280 .LFE179: + 1282 .section .text.SD_SendStatus,"ax",%progbits + 1283 .align 1 + 1284 .syntax unified + 1285 .thumb + 1286 .thumb_func + 1288 SD_SendStatus: + 1289 .LVL133: + 1290 .LFB177: +2919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 1291 .loc 1 2919 1 is_stmt 1 view -0 + 1292 .cfi_startproc + 1293 @ args = 0, pretend = 0, frame = 0 + 1294 @ frame_needed = 0, uses_anonymous_args = 0 +2919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 1295 .loc 1 2919 1 is_stmt 0 view .LVU436 + 1296 0000 70B5 push {r4, r5, r6, lr} + 1297 .LCFI26: + 1298 .cfi_def_cfa_offset 16 + 1299 .cfi_offset 4, -16 + 1300 .cfi_offset 5, -12 + 1301 .cfi_offset 6, -8 + 1302 .cfi_offset 14, -4 +2920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1303 .loc 1 2920 3 is_stmt 1 view .LVU437 +2922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1304 .loc 1 2922 3 view .LVU438 +2922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1305 .loc 1 2922 5 is_stmt 0 view .LVU439 + 1306 0002 81B1 cbz r1, .L87 + 1307 0004 0446 mov r4, r0 + 1308 0006 0E46 mov r6, r1 +2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1309 .loc 1 2928 3 is_stmt 1 view .LVU440 +2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1310 .loc 1 2928 73 is_stmt 0 view .LVU441 + 1311 0008 016D ldr r1, [r0, #80] + 1312 .LVL134: +2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1313 .loc 1 2928 16 view .LVU442 + 1314 000a 0904 lsls r1, r1, #16 + 1315 000c 0068 ldr r0, [r0] + 1316 .LVL135: +2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1317 .loc 1 2928 16 view .LVU443 + 1318 000e FFF7FEFF bl SDMMC_CmdSendStatus + 1319 .LVL136: + ARM GAS /tmp/ccMMu31U.s page 87 + + +2929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1320 .loc 1 2929 3 is_stmt 1 view .LVU444 +2929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1321 .loc 1 2929 5 is_stmt 0 view .LVU445 + 1322 0012 0546 mov r5, r0 + 1323 0014 08B1 cbz r0, .L89 + 1324 .LVL137: + 1325 .L85: +2938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1326 .loc 1 2938 1 view .LVU446 + 1327 0016 2846 mov r0, r5 + 1328 0018 70BD pop {r4, r5, r6, pc} + 1329 .LVL138: + 1330 .L89: +2935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1331 .loc 1 2935 3 is_stmt 1 view .LVU447 +2935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1332 .loc 1 2935 18 is_stmt 0 view .LVU448 + 1333 001a 0021 movs r1, #0 + 1334 001c 2068 ldr r0, [r4] + 1335 .LVL139: +2935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1336 .loc 1 2935 18 view .LVU449 + 1337 001e FFF7FEFF bl SDMMC_GetResponse + 1338 .LVL140: +2935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1339 .loc 1 2935 16 discriminator 1 view .LVU450 + 1340 0022 3060 str r0, [r6] +2937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1341 .loc 1 2937 3 is_stmt 1 view .LVU451 +2937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1342 .loc 1 2937 10 is_stmt 0 view .LVU452 + 1343 0024 F7E7 b .L85 + 1344 .LVL141: + 1345 .L87: +2924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1346 .loc 1 2924 12 view .LVU453 + 1347 0026 4FF00065 mov r5, #134217728 + 1348 002a F4E7 b .L85 + 1349 .cfi_endproc + 1350 .LFE177: + 1352 .section .text.HAL_SD_MspInit,"ax",%progbits + 1353 .align 1 + 1354 .weak HAL_SD_MspInit + 1355 .syntax unified + 1356 .thumb + 1357 .thumb_func + 1359 HAL_SD_MspInit: + 1360 .LVL142: + 1361 .LFB144: + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Prevent unused argument(s) compilation warning */ + 1362 .loc 1 515 1 is_stmt 1 view -0 + 1363 .cfi_startproc + 1364 @ args = 0, pretend = 0, frame = 0 + 1365 @ frame_needed = 0, uses_anonymous_args = 0 + 1366 @ link register save eliminated. + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + ARM GAS /tmp/ccMMu31U.s page 88 + + + 1367 .loc 1 517 3 view .LVU455 + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1368 .loc 1 522 1 is_stmt 0 view .LVU456 + 1369 0000 7047 bx lr + 1370 .cfi_endproc + 1371 .LFE144: + 1373 .section .text.HAL_SD_MspDeInit,"ax",%progbits + 1374 .align 1 + 1375 .weak HAL_SD_MspDeInit + 1376 .syntax unified + 1377 .thumb + 1378 .thumb_func + 1380 HAL_SD_MspDeInit: + 1381 .LVL143: + 1382 .LFB145: + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Prevent unused argument(s) compilation warning */ + 1383 .loc 1 530 1 is_stmt 1 view -0 + 1384 .cfi_startproc + 1385 @ args = 0, pretend = 0, frame = 0 + 1386 @ frame_needed = 0, uses_anonymous_args = 0 + 1387 @ link register save eliminated. + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1388 .loc 1 532 3 view .LVU458 + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1389 .loc 1 537 1 is_stmt 0 view .LVU459 + 1390 0000 7047 bx lr + 1391 .cfi_endproc + 1392 .LFE145: + 1394 .section .text.HAL_SD_DeInit,"ax",%progbits + 1395 .align 1 + 1396 .global HAL_SD_DeInit + 1397 .syntax unified + 1398 .thumb + 1399 .thumb_func + 1401 HAL_SD_DeInit: + 1402 .LVL144: + 1403 .LFB143: + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Check the SD handle allocation */ + 1404 .loc 1 474 1 is_stmt 1 view -0 + 1405 .cfi_startproc + 1406 @ args = 0, pretend = 0, frame = 0 + 1407 @ frame_needed = 0, uses_anonymous_args = 0 + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1408 .loc 1 476 3 view .LVU461 + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1409 .loc 1 476 5 is_stmt 0 view .LVU462 + 1410 0000 70B1 cbz r0, .L94 + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Check the SD handle allocation */ + 1411 .loc 1 474 1 view .LVU463 + 1412 0002 10B5 push {r4, lr} + 1413 .LCFI27: + 1414 .cfi_def_cfa_offset 8 + 1415 .cfi_offset 4, -8 + 1416 .cfi_offset 14, -4 + 1417 0004 0446 mov r4, r0 + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1418 .loc 1 482 3 is_stmt 1 view .LVU464 + ARM GAS /tmp/ccMMu31U.s page 89 + + + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1419 .loc 1 484 3 view .LVU465 + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1420 .loc 1 484 14 is_stmt 0 view .LVU466 + 1421 0006 0323 movs r3, #3 + 1422 0008 80F83430 strb r3, [r0, #52] + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1423 .loc 1 487 3 is_stmt 1 view .LVU467 + 1424 000c FFF7FEFF bl SD_PowerOFF + 1425 .LVL145: + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + 1426 .loc 1 499 3 view .LVU468 + 1427 0010 2046 mov r0, r4 + 1428 0012 FFF7FEFF bl HAL_SD_MspDeInit + 1429 .LVL146: + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_RESET; + 1430 .loc 1 502 3 view .LVU469 + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_RESET; + 1431 .loc 1 502 18 is_stmt 0 view .LVU470 + 1432 0016 0020 movs r0, #0 + 1433 0018 A063 str r0, [r4, #56] + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1434 .loc 1 503 3 is_stmt 1 view .LVU471 + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1435 .loc 1 503 14 is_stmt 0 view .LVU472 + 1436 001a 84F83400 strb r0, [r4, #52] + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1437 .loc 1 505 3 is_stmt 1 view .LVU473 + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1438 .loc 1 506 1 is_stmt 0 view .LVU474 + 1439 001e 10BD pop {r4, pc} + 1440 .LVL147: + 1441 .L94: + 1442 .LCFI28: + 1443 .cfi_def_cfa_offset 0 + 1444 .cfi_restore 4 + 1445 .cfi_restore 14 + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1446 .loc 1 478 12 view .LVU475 + 1447 0020 0120 movs r0, #1 + 1448 .LVL148: + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1449 .loc 1 506 1 view .LVU476 + 1450 0022 7047 bx lr + 1451 .cfi_endproc + 1452 .LFE143: + 1454 .section .text.HAL_SD_ReadBlocks,"ax",%progbits + 1455 .align 1 + 1456 .global HAL_SD_ReadBlocks + 1457 .syntax unified + 1458 .thumb + 1459 .thumb_func + 1461 HAL_SD_ReadBlocks: + 1462 .LVL149: + 1463 .LFB146: + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; + 1464 .loc 1 571 1 is_stmt 1 view -0 + ARM GAS /tmp/ccMMu31U.s page 90 + + + 1465 .cfi_startproc + 1466 @ args = 4, pretend = 0, frame = 24 + 1467 @ frame_needed = 0, uses_anonymous_args = 0 + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; + 1468 .loc 1 571 1 is_stmt 0 view .LVU478 + 1469 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 1470 .LCFI29: + 1471 .cfi_def_cfa_offset 36 + 1472 .cfi_offset 4, -36 + 1473 .cfi_offset 5, -32 + 1474 .cfi_offset 6, -28 + 1475 .cfi_offset 7, -24 + 1476 .cfi_offset 8, -20 + 1477 .cfi_offset 9, -16 + 1478 .cfi_offset 10, -12 + 1479 .cfi_offset 11, -8 + 1480 .cfi_offset 14, -4 + 1481 0004 87B0 sub sp, sp, #28 + 1482 .LCFI30: + 1483 .cfi_def_cfa_offset 64 + 1484 0006 0546 mov r5, r0 + 1485 0008 0C46 mov r4, r1 + 1486 000a 1646 mov r6, r2 + 1487 000c 9B46 mov fp, r3 + 1488 000e DDF840A0 ldr r10, [sp, #64] + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 1489 .loc 1 572 3 is_stmt 1 view .LVU479 + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t tickstart = HAL_GetTick(); + 1490 .loc 1 573 3 view .LVU480 + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t count, data, dataremaining; + 1491 .loc 1 574 3 view .LVU481 + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t count, data, dataremaining; + 1492 .loc 1 574 24 is_stmt 0 view .LVU482 + 1493 0012 FFF7FEFF bl HAL_GetTick + 1494 .LVL150: + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t add = BlockAdd; + 1495 .loc 1 575 3 is_stmt 1 view .LVU483 + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint8_t *tempbuff = pData; + 1496 .loc 1 576 3 view .LVU484 + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1497 .loc 1 577 3 view .LVU485 + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1498 .loc 1 579 3 view .LVU486 + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1499 .loc 1 579 5 is_stmt 0 view .LVU487 + 1500 0016 002C cmp r4, #0 + 1501 0018 36D0 beq .L122 + 1502 001a 8146 mov r9, r0 + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1503 .loc 1 585 3 is_stmt 1 view .LVU488 + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1504 .loc 1 585 9 is_stmt 0 view .LVU489 + 1505 001c 95F83470 ldrb r7, [r5, #52] @ zero_extendqisi2 + 1506 0020 FFB2 uxtb r7, r7 + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1507 .loc 1 585 5 view .LVU490 + 1508 0022 012F cmp r7, #1 + ARM GAS /tmp/ccMMu31U.s page 91 + + + 1509 0024 40F00481 bne .L102 + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1510 .loc 1 587 5 is_stmt 1 view .LVU491 + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1511 .loc 1 587 20 is_stmt 0 view .LVU492 + 1512 0028 0023 movs r3, #0 + 1513 002a AB63 str r3, [r5, #56] + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1514 .loc 1 589 5 is_stmt 1 view .LVU493 + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1515 .loc 1 589 13 is_stmt 0 view .LVU494 + 1516 002c 06EB0B03 add r3, r6, fp + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1517 .loc 1 589 45 view .LVU495 + 1518 0030 EA6D ldr r2, [r5, #92] + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1519 .loc 1 589 7 view .LVU496 + 1520 0032 9342 cmp r3, r2 + 1521 0034 2ED8 bhi .L123 + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1522 .loc 1 595 5 is_stmt 1 view .LVU497 + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1523 .loc 1 595 16 is_stmt 0 view .LVU498 + 1524 0036 0323 movs r3, #3 + 1525 0038 85F83430 strb r3, [r5, #52] + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1526 .loc 1 598 5 is_stmt 1 view .LVU499 + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1527 .loc 1 598 8 is_stmt 0 view .LVU500 + 1528 003c 2B68 ldr r3, [r5] + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1529 .loc 1 598 26 view .LVU501 + 1530 003e 0022 movs r2, #0 + 1531 0040 DA62 str r2, [r3, #44] + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1532 .loc 1 600 5 is_stmt 1 view .LVU502 + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1533 .loc 1 600 19 is_stmt 0 view .LVU503 + 1534 0042 6B6C ldr r3, [r5, #68] + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1535 .loc 1 600 7 view .LVU504 + 1536 0044 012B cmp r3, #1 + 1537 0046 00D0 beq .L104 + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1538 .loc 1 602 7 is_stmt 1 view .LVU505 + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1539 .loc 1 602 11 is_stmt 0 view .LVU506 + 1540 0048 7602 lsls r6, r6, #9 + 1541 .LVL151: + 1542 .L104: + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = NumberOfBlocks * BLOCKSIZE; + 1543 .loc 1 606 5 is_stmt 1 view .LVU507 + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = NumberOfBlocks * BLOCKSIZE; + 1544 .loc 1 606 26 is_stmt 0 view .LVU508 + 1545 004a 4FF0FF33 mov r3, #-1 + 1546 004e 0093 str r3, [sp] + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + ARM GAS /tmp/ccMMu31U.s page 92 + + + 1547 .loc 1 607 5 is_stmt 1 view .LVU509 + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + 1548 .loc 1 607 43 is_stmt 0 view .LVU510 + 1549 0050 4FEA4B23 lsl r3, fp, #9 + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + 1550 .loc 1 607 26 view .LVU511 + 1551 0054 0193 str r3, [sp, #4] + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + 1552 .loc 1 608 5 is_stmt 1 view .LVU512 + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + 1553 .loc 1 608 26 is_stmt 0 view .LVU513 + 1554 0056 9023 movs r3, #144 + 1555 0058 0293 str r3, [sp, #8] + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + 1556 .loc 1 609 5 is_stmt 1 view .LVU514 + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + 1557 .loc 1 609 26 is_stmt 0 view .LVU515 + 1558 005a 0223 movs r3, #2 + 1559 005c 0393 str r3, [sp, #12] + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; + 1560 .loc 1 610 5 is_stmt 1 view .LVU516 + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; + 1561 .loc 1 610 26 is_stmt 0 view .LVU517 + 1562 005e 0023 movs r3, #0 + 1563 0060 0493 str r3, [sp, #16] + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); + 1564 .loc 1 611 5 is_stmt 1 view .LVU518 + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); + 1565 .loc 1 611 26 is_stmt 0 view .LVU519 + 1566 0062 0123 movs r3, #1 + 1567 0064 0593 str r3, [sp, #20] + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1568 .loc 1 612 5 is_stmt 1 view .LVU520 + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1569 .loc 1 612 11 is_stmt 0 view .LVU521 + 1570 0066 6946 mov r1, sp + 1571 0068 2868 ldr r0, [r5] + 1572 .LVL152: + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1573 .loc 1 612 11 view .LVU522 + 1574 006a FFF7FEFF bl SDMMC_ConfigData + 1575 .LVL153: + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1576 .loc 1 615 5 is_stmt 1 view .LVU523 + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1577 .loc 1 615 7 is_stmt 0 view .LVU524 + 1578 006e BBF1010F cmp fp, #1 + 1579 0072 14D9 bls .L105 + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1580 .loc 1 617 7 is_stmt 1 view .LVU525 + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1581 .loc 1 617 20 is_stmt 0 view .LVU526 + 1582 0074 0223 movs r3, #2 + 1583 0076 2B63 str r3, [r5, #48] + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1584 .loc 1 620 7 is_stmt 1 view .LVU527 + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + ARM GAS /tmp/ccMMu31U.s page 93 + + + 1585 .loc 1 620 20 is_stmt 0 view .LVU528 + 1586 0078 3146 mov r1, r6 + 1587 007a 2868 ldr r0, [r5] + 1588 007c FFF7FEFF bl SDMMC_CmdReadMultiBlock + 1589 .LVL154: + 1590 .L106: + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1591 .loc 1 629 5 is_stmt 1 view .LVU529 + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1592 .loc 1 629 7 is_stmt 0 view .LVU530 + 1593 0080 A0B9 cbnz r0, .L124 + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | + 1594 .loc 1 640 5 is_stmt 1 view .LVU531 + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | + 1595 .loc 1 640 19 is_stmt 0 view .LVU532 + 1596 0082 DDF80480 ldr r8, [sp, #4] + 1597 .LVL155: + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1598 .loc 1 641 5 is_stmt 1 view .LVU533 + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1599 .loc 1 641 10 is_stmt 0 view .LVU534 + 1600 0086 38E0 b .L108 + 1601 .LVL156: + 1602 .L122: + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1603 .loc 1 581 5 is_stmt 1 view .LVU535 + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1604 .loc 1 581 8 is_stmt 0 view .LVU536 + 1605 0088 AB6B ldr r3, [r5, #56] + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1606 .loc 1 581 20 view .LVU537 + 1607 008a 43F00063 orr r3, r3, #134217728 + 1608 008e AB63 str r3, [r5, #56] + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1609 .loc 1 582 5 is_stmt 1 view .LVU538 + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1610 .loc 1 582 12 is_stmt 0 view .LVU539 + 1611 0090 0127 movs r7, #1 + 1612 0092 D2E0 b .L101 + 1613 .L123: + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1614 .loc 1 591 7 is_stmt 1 view .LVU540 + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1615 .loc 1 591 10 is_stmt 0 view .LVU541 + 1616 0094 AB6B ldr r3, [r5, #56] + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1617 .loc 1 591 22 view .LVU542 + 1618 0096 43F00073 orr r3, r3, #33554432 + 1619 009a AB63 str r3, [r5, #56] + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1620 .loc 1 592 7 is_stmt 1 view .LVU543 + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1621 .loc 1 592 14 is_stmt 0 view .LVU544 + 1622 009c CDE0 b .L101 + 1623 .LVL157: + 1624 .L105: + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + ARM GAS /tmp/ccMMu31U.s page 94 + + + 1625 .loc 1 624 7 is_stmt 1 view .LVU545 + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1626 .loc 1 624 20 is_stmt 0 view .LVU546 + 1627 009e 0123 movs r3, #1 + 1628 00a0 2B63 str r3, [r5, #48] + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1629 .loc 1 627 7 is_stmt 1 view .LVU547 + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1630 .loc 1 627 20 is_stmt 0 view .LVU548 + 1631 00a2 3146 mov r1, r6 + 1632 00a4 2868 ldr r0, [r5] + 1633 00a6 FFF7FEFF bl SDMMC_CmdReadSingleBlock + 1634 .LVL158: + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1635 .loc 1 627 20 view .LVU549 + 1636 00aa E9E7 b .L106 + 1637 .L124: + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 1638 .loc 1 632 7 is_stmt 1 view .LVU550 + 1639 00ac 2B68 ldr r3, [r5] + 1640 00ae 654A ldr r2, .L130 + 1641 00b0 9A63 str r2, [r3, #56] + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 1642 .loc 1 633 7 view .LVU551 + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 1643 .loc 1 633 10 is_stmt 0 view .LVU552 + 1644 00b2 AB6B ldr r3, [r5, #56] + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 1645 .loc 1 633 22 view .LVU553 + 1646 00b4 0343 orrs r3, r3, r0 + 1647 00b6 AB63 str r3, [r5, #56] + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 1648 .loc 1 634 7 is_stmt 1 view .LVU554 + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 1649 .loc 1 634 18 is_stmt 0 view .LVU555 + 1650 00b8 0123 movs r3, #1 + 1651 00ba 85F83430 strb r3, [r5, #52] + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1652 .loc 1 635 7 is_stmt 1 view .LVU556 + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1653 .loc 1 635 20 is_stmt 0 view .LVU557 + 1654 00be 0023 movs r3, #0 + 1655 00c0 2B63 str r3, [r5, #48] + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1656 .loc 1 636 7 is_stmt 1 view .LVU558 + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1657 .loc 1 636 14 is_stmt 0 view .LVU559 + 1658 00c2 BAE0 b .L101 + 1659 .LVL159: + 1660 .L111: + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tempbuff = (uint8_t)(data & 0xFFU); + 1661 .loc 1 648 11 is_stmt 1 view .LVU560 + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tempbuff = (uint8_t)(data & 0xFFU); + 1662 .loc 1 648 18 is_stmt 0 view .LVU561 + 1663 00c4 2868 ldr r0, [r5] + 1664 00c6 FFF7FEFF bl SDMMC_ReadFIFO + 1665 .LVL160: + ARM GAS /tmp/ccMMu31U.s page 95 + + + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1666 .loc 1 649 11 is_stmt 1 view .LVU562 + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1667 .loc 1 649 21 is_stmt 0 view .LVU563 + 1668 00ca 2070 strb r0, [r4] + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 1669 .loc 1 650 11 is_stmt 1 view .LVU564 + 1670 .LVL161: + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + 1671 .loc 1 651 11 view .LVU565 + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1672 .loc 1 652 11 view .LVU566 + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1673 .loc 1 652 23 is_stmt 0 view .LVU567 + 1674 00cc C0F30723 ubfx r3, r0, #8, #8 + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1675 .loc 1 652 21 view .LVU568 + 1676 00d0 6370 strb r3, [r4, #1] + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 1677 .loc 1 653 11 is_stmt 1 view .LVU569 + 1678 .LVL162: + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + 1679 .loc 1 654 11 view .LVU570 + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1680 .loc 1 655 11 view .LVU571 + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1681 .loc 1 655 23 is_stmt 0 view .LVU572 + 1682 00d2 C0F30743 ubfx r3, r0, #16, #8 + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1683 .loc 1 655 21 view .LVU573 + 1684 00d6 A370 strb r3, [r4, #2] + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 1685 .loc 1 656 11 is_stmt 1 view .LVU574 + 1686 .LVL163: + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + 1687 .loc 1 657 11 view .LVU575 + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1688 .loc 1 658 11 view .LVU576 + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1689 .loc 1 658 23 is_stmt 0 view .LVU577 + 1690 00d8 000E lsrs r0, r0, #24 + 1691 .LVL164: + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1692 .loc 1 658 21 view .LVU578 + 1693 00da E070 strb r0, [r4, #3] + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 1694 .loc 1 659 11 is_stmt 1 view .LVU579 + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 1695 .loc 1 659 19 is_stmt 0 view .LVU580 + 1696 00dc 0434 adds r4, r4, #4 + 1697 .LVL165: + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1698 .loc 1 660 11 is_stmt 1 view .LVU581 + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1699 .loc 1 660 24 is_stmt 0 view .LVU582 + 1700 00de A8F10408 sub r8, r8, #4 + 1701 .LVL166: + ARM GAS /tmp/ccMMu31U.s page 96 + + + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1702 .loc 1 646 42 is_stmt 1 discriminator 3 view .LVU583 + 1703 00e2 0136 adds r6, r6, #1 + 1704 .LVL167: + 1705 .L110: + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1706 .loc 1 646 31 discriminator 1 view .LVU584 + 1707 00e4 072E cmp r6, #7 + 1708 00e6 EDD9 bls .L111 + 1709 .LVL168: + 1710 .L109: + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1711 .loc 1 664 7 view .LVU585 + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1712 .loc 1 664 12 is_stmt 0 view .LVU586 + 1713 00e8 FFF7FEFF bl HAL_GetTick + 1714 .LVL169: + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1715 .loc 1 664 25 discriminator 1 view .LVU587 + 1716 00ec A0EB0900 sub r0, r0, r9 + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1717 .loc 1 664 9 discriminator 1 view .LVU588 + 1718 00f0 5045 cmp r0, r10 + 1719 00f2 0FD2 bcs .L112 + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1720 .loc 1 664 50 discriminator 1 view .LVU589 + 1721 00f4 BAF1000F cmp r10, #0 + 1722 00f8 0CD0 beq .L112 + 1723 .L108: + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1724 .loc 1 641 11 is_stmt 1 view .LVU590 + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1725 .loc 1 641 12 is_stmt 0 view .LVU591 + 1726 00fa 2868 ldr r0, [r5] + 1727 00fc 466B ldr r6, [r0, #52] + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1728 .loc 1 641 11 view .LVU592 + 1729 00fe 16F49576 ands r6, r6, #298 + 1730 0102 15D1 bne .L125 + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1731 .loc 1 643 7 is_stmt 1 view .LVU593 + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1732 .loc 1 643 10 is_stmt 0 view .LVU594 + 1733 0104 436B ldr r3, [r0, #52] + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1734 .loc 1 643 9 view .LVU595 + 1735 0106 13F4004F tst r3, #32768 + 1736 010a EDD0 beq .L109 + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1737 .loc 1 643 54 discriminator 1 view .LVU596 + 1738 010c B8F1000F cmp r8, #0 + 1739 0110 EAD0 beq .L109 + 1740 0112 E7E7 b .L110 + 1741 .L112: + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; + 1742 .loc 1 667 9 is_stmt 1 view .LVU597 + 1743 0114 2B68 ldr r3, [r5] + ARM GAS /tmp/ccMMu31U.s page 97 + + + 1744 0116 4B4A ldr r2, .L130 + 1745 0118 9A63 str r2, [r3, #56] + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State= HAL_SD_STATE_READY; + 1746 .loc 1 668 9 view .LVU598 + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State= HAL_SD_STATE_READY; + 1747 .loc 1 668 12 is_stmt 0 view .LVU599 + 1748 011a AB6B ldr r3, [r5, #56] + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State= HAL_SD_STATE_READY; + 1749 .loc 1 668 24 view .LVU600 + 1750 011c 43F00043 orr r3, r3, #-2147483648 + 1751 0120 AB63 str r3, [r5, #56] + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 1752 .loc 1 669 9 is_stmt 1 view .LVU601 + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 1753 .loc 1 669 19 is_stmt 0 view .LVU602 + 1754 0122 0123 movs r3, #1 + 1755 0124 85F83430 strb r3, [r5, #52] + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_TIMEOUT; + 1756 .loc 1 670 9 is_stmt 1 view .LVU603 + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_TIMEOUT; + 1757 .loc 1 670 22 is_stmt 0 view .LVU604 + 1758 0128 0023 movs r3, #0 + 1759 012a 2B63 str r3, [r5, #48] + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1760 .loc 1 671 9 is_stmt 1 view .LVU605 + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1761 .loc 1 671 16 is_stmt 0 view .LVU606 + 1762 012c 0327 movs r7, #3 + 1763 012e 84E0 b .L101 + 1764 .L125: + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1765 .loc 1 676 5 is_stmt 1 view .LVU607 + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1766 .loc 1 676 8 is_stmt 0 view .LVU608 + 1767 0130 436B ldr r3, [r0, #52] + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1768 .loc 1 676 7 view .LVU609 + 1769 0132 13F4807F tst r3, #256 + 1770 0136 05D0 beq .L114 + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1771 .loc 1 676 51 discriminator 1 view .LVU610 + 1772 0138 BBF1010F cmp fp, #1 + 1773 013c 02D9 bls .L114 + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1774 .loc 1 678 7 is_stmt 1 view .LVU611 + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1775 .loc 1 678 21 is_stmt 0 view .LVU612 + 1776 013e 6B6C ldr r3, [r5, #68] + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1777 .loc 1 678 9 view .LVU613 + 1778 0140 032B cmp r3, #3 + 1779 0142 38D1 bne .L126 + 1780 .LVL170: + 1781 .L114: + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1782 .loc 1 695 5 is_stmt 1 view .LVU614 + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + ARM GAS /tmp/ccMMu31U.s page 98 + + + 1783 .loc 1 695 8 is_stmt 0 view .LVU615 + 1784 0144 2B68 ldr r3, [r5] + 1785 0146 5A6B ldr r2, [r3, #52] + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1786 .loc 1 695 7 view .LVU616 + 1787 0148 12F0080F tst r2, #8 + 1788 014c 44D1 bne .L127 + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1789 .loc 1 704 10 is_stmt 1 view .LVU617 + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1790 .loc 1 704 13 is_stmt 0 view .LVU618 + 1791 014e 5A6B ldr r2, [r3, #52] + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1792 .loc 1 704 12 view .LVU619 + 1793 0150 12F0020F tst r2, #2 + 1794 0154 4CD1 bne .L128 + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1795 .loc 1 713 10 is_stmt 1 view .LVU620 + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1796 .loc 1 713 13 is_stmt 0 view .LVU621 + 1797 0156 5A6B ldr r2, [r3, #52] + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1798 .loc 1 713 12 view .LVU622 + 1799 0158 12F0200F tst r2, #32 + 1800 015c 54D1 bne .L129 + 1801 .L117: + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1802 .loc 1 728 56 is_stmt 1 view .LVU623 + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1803 .loc 1 728 13 is_stmt 0 view .LVU624 + 1804 015e 2868 ldr r0, [r5] + 1805 0160 436B ldr r3, [r0, #52] + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1806 .loc 1 728 56 view .LVU625 + 1807 0162 13F4001F tst r3, #2097152 + 1808 0166 5BD0 beq .L119 + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1809 .loc 1 728 56 discriminator 1 view .LVU626 + 1810 0168 B8F1000F cmp r8, #0 + 1811 016c 58D0 beq .L119 + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tempbuff = (uint8_t)(data & 0xFFU); + 1812 .loc 1 730 7 is_stmt 1 view .LVU627 + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tempbuff = (uint8_t)(data & 0xFFU); + 1813 .loc 1 730 14 is_stmt 0 view .LVU628 + 1814 016e FFF7FEFF bl SDMMC_ReadFIFO + 1815 .LVL171: + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1816 .loc 1 731 7 is_stmt 1 view .LVU629 + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1817 .loc 1 731 17 is_stmt 0 view .LVU630 + 1818 0172 2070 strb r0, [r4] + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 1819 .loc 1 732 7 is_stmt 1 view .LVU631 + 1820 .LVL172: + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + 1821 .loc 1 733 7 view .LVU632 + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + ARM GAS /tmp/ccMMu31U.s page 99 + + + 1822 .loc 1 734 7 view .LVU633 + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1823 .loc 1 734 19 is_stmt 0 view .LVU634 + 1824 0174 C0F30723 ubfx r3, r0, #8, #8 + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1825 .loc 1 734 17 view .LVU635 + 1826 0178 6370 strb r3, [r4, #1] + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 1827 .loc 1 735 7 is_stmt 1 view .LVU636 + 1828 .LVL173: + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + 1829 .loc 1 736 7 view .LVU637 + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1830 .loc 1 737 7 view .LVU638 + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1831 .loc 1 737 19 is_stmt 0 view .LVU639 + 1832 017a C0F30743 ubfx r3, r0, #16, #8 + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1833 .loc 1 737 17 view .LVU640 + 1834 017e A370 strb r3, [r4, #2] + 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 1835 .loc 1 738 7 is_stmt 1 view .LVU641 + 1836 .LVL174: + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + 1837 .loc 1 739 7 view .LVU642 + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1838 .loc 1 740 7 view .LVU643 + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1839 .loc 1 740 19 is_stmt 0 view .LVU644 + 1840 0180 000E lsrs r0, r0, #24 + 1841 .LVL175: + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 1842 .loc 1 740 17 view .LVU645 + 1843 0182 E070 strb r0, [r4, #3] + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 1844 .loc 1 741 7 is_stmt 1 view .LVU646 + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 1845 .loc 1 741 15 is_stmt 0 view .LVU647 + 1846 0184 0434 adds r4, r4, #4 + 1847 .LVL176: + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1848 .loc 1 742 7 is_stmt 1 view .LVU648 + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1849 .loc 1 742 20 is_stmt 0 view .LVU649 + 1850 0186 A8F10408 sub r8, r8, #4 + 1851 .LVL177: + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1852 .loc 1 744 7 is_stmt 1 view .LVU650 + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1853 .loc 1 744 12 is_stmt 0 view .LVU651 + 1854 018a FFF7FEFF bl HAL_GetTick + 1855 .LVL178: + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1856 .loc 1 744 25 discriminator 1 view .LVU652 + 1857 018e A0EB0900 sub r0, r0, r9 + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1858 .loc 1 744 9 discriminator 1 view .LVU653 + ARM GAS /tmp/ccMMu31U.s page 100 + + + 1859 0192 5045 cmp r0, r10 + 1860 0194 02D2 bcs .L118 + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1861 .loc 1 744 50 discriminator 1 view .LVU654 + 1862 0196 BAF1000F cmp r10, #0 + 1863 019a E0D1 bne .L117 + 1864 .L118: + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; + 1865 .loc 1 747 9 is_stmt 1 view .LVU655 + 1866 019c 2B68 ldr r3, [r5] + 1867 019e 294A ldr r2, .L130 + 1868 01a0 9A63 str r2, [r3, #56] + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State= HAL_SD_STATE_READY; + 1869 .loc 1 748 9 view .LVU656 + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State= HAL_SD_STATE_READY; + 1870 .loc 1 748 12 is_stmt 0 view .LVU657 + 1871 01a2 AB6B ldr r3, [r5, #56] + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State= HAL_SD_STATE_READY; + 1872 .loc 1 748 24 view .LVU658 + 1873 01a4 43F00043 orr r3, r3, #-2147483648 + 1874 01a8 AB63 str r3, [r5, #56] + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 1875 .loc 1 749 9 is_stmt 1 view .LVU659 + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 1876 .loc 1 749 19 is_stmt 0 view .LVU660 + 1877 01aa 0123 movs r3, #1 + 1878 01ac 85F83430 strb r3, [r5, #52] + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1879 .loc 1 750 9 is_stmt 1 view .LVU661 + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1880 .loc 1 750 22 is_stmt 0 view .LVU662 + 1881 01b0 0023 movs r3, #0 + 1882 01b2 2B63 str r3, [r5, #48] + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1883 .loc 1 751 9 is_stmt 1 view .LVU663 + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1884 .loc 1 751 16 is_stmt 0 view .LVU664 + 1885 01b4 41E0 b .L101 + 1886 .LVL179: + 1887 .L126: + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1888 .loc 1 681 9 is_stmt 1 view .LVU665 + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 1889 .loc 1 681 22 is_stmt 0 view .LVU666 + 1890 01b6 FFF7FEFF bl SDMMC_CmdStopTransfer + 1891 .LVL180: + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1892 .loc 1 682 9 is_stmt 1 view .LVU667 + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 1893 .loc 1 682 11 is_stmt 0 view .LVU668 + 1894 01ba 0346 mov r3, r0 + 1895 01bc 0028 cmp r0, #0 + 1896 01be C1D0 beq .L114 + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 1897 .loc 1 685 11 is_stmt 1 view .LVU669 + 1898 01c0 2A68 ldr r2, [r5] + 1899 01c2 2049 ldr r1, .L130 + ARM GAS /tmp/ccMMu31U.s page 101 + + + 1900 01c4 9163 str r1, [r2, #56] + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 1901 .loc 1 686 11 view .LVU670 + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 1902 .loc 1 686 14 is_stmt 0 view .LVU671 + 1903 01c6 AA6B ldr r2, [r5, #56] + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 1904 .loc 1 686 26 view .LVU672 + 1905 01c8 1343 orrs r3, r3, r2 + 1906 01ca AB63 str r3, [r5, #56] + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 1907 .loc 1 687 11 is_stmt 1 view .LVU673 + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 1908 .loc 1 687 22 is_stmt 0 view .LVU674 + 1909 01cc 0123 movs r3, #1 + 1910 01ce 85F83430 strb r3, [r5, #52] + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1911 .loc 1 688 11 is_stmt 1 view .LVU675 + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1912 .loc 1 688 24 is_stmt 0 view .LVU676 + 1913 01d2 0023 movs r3, #0 + 1914 01d4 2B63 str r3, [r5, #48] + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1915 .loc 1 689 11 is_stmt 1 view .LVU677 + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1916 .loc 1 689 18 is_stmt 0 view .LVU678 + 1917 01d6 30E0 b .L101 + 1918 .LVL181: + 1919 .L127: + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + 1920 .loc 1 698 7 is_stmt 1 view .LVU679 + 1921 01d8 1A4A ldr r2, .L130 + 1922 01da 9A63 str r2, [r3, #56] + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 1923 .loc 1 699 7 view .LVU680 + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 1924 .loc 1 699 10 is_stmt 0 view .LVU681 + 1925 01dc AB6B ldr r3, [r5, #56] + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 1926 .loc 1 699 22 view .LVU682 + 1927 01de 43F00803 orr r3, r3, #8 + 1928 01e2 AB63 str r3, [r5, #56] + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 1929 .loc 1 700 7 is_stmt 1 view .LVU683 + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 1930 .loc 1 700 18 is_stmt 0 view .LVU684 + 1931 01e4 0123 movs r3, #1 + 1932 01e6 85F83430 strb r3, [r5, #52] + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1933 .loc 1 701 7 is_stmt 1 view .LVU685 + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1934 .loc 1 701 20 is_stmt 0 view .LVU686 + 1935 01ea 0023 movs r3, #0 + 1936 01ec 2B63 str r3, [r5, #48] + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1937 .loc 1 702 7 is_stmt 1 view .LVU687 + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + ARM GAS /tmp/ccMMu31U.s page 102 + + + 1938 .loc 1 702 14 is_stmt 0 view .LVU688 + 1939 01ee 24E0 b .L101 + 1940 .L128: + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + 1941 .loc 1 707 7 is_stmt 1 view .LVU689 + 1942 01f0 144A ldr r2, .L130 + 1943 01f2 9A63 str r2, [r3, #56] + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 1944 .loc 1 708 7 view .LVU690 + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 1945 .loc 1 708 10 is_stmt 0 view .LVU691 + 1946 01f4 AB6B ldr r3, [r5, #56] + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 1947 .loc 1 708 22 view .LVU692 + 1948 01f6 43F00203 orr r3, r3, #2 + 1949 01fa AB63 str r3, [r5, #56] + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 1950 .loc 1 709 7 is_stmt 1 view .LVU693 + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 1951 .loc 1 709 18 is_stmt 0 view .LVU694 + 1952 01fc 0123 movs r3, #1 + 1953 01fe 85F83430 strb r3, [r5, #52] + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1954 .loc 1 710 7 is_stmt 1 view .LVU695 + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1955 .loc 1 710 20 is_stmt 0 view .LVU696 + 1956 0202 0023 movs r3, #0 + 1957 0204 2B63 str r3, [r5, #48] + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1958 .loc 1 711 7 is_stmt 1 view .LVU697 + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1959 .loc 1 711 14 is_stmt 0 view .LVU698 + 1960 0206 18E0 b .L101 + 1961 .L129: + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; + 1962 .loc 1 716 7 is_stmt 1 view .LVU699 + 1963 0208 0E4A ldr r2, .L130 + 1964 020a 9A63 str r2, [r3, #56] + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 1965 .loc 1 717 7 view .LVU700 + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 1966 .loc 1 717 10 is_stmt 0 view .LVU701 + 1967 020c AB6B ldr r3, [r5, #56] + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 1968 .loc 1 717 22 view .LVU702 + 1969 020e 43F02003 orr r3, r3, #32 + 1970 0212 AB63 str r3, [r5, #56] + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 1971 .loc 1 718 7 is_stmt 1 view .LVU703 + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 1972 .loc 1 718 18 is_stmt 0 view .LVU704 + 1973 0214 0123 movs r3, #1 + 1974 0216 85F83430 strb r3, [r5, #52] + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1975 .loc 1 719 7 is_stmt 1 view .LVU705 + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1976 .loc 1 719 20 is_stmt 0 view .LVU706 + ARM GAS /tmp/ccMMu31U.s page 103 + + + 1977 021a 0023 movs r3, #0 + 1978 021c 2B63 str r3, [r5, #48] + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1979 .loc 1 720 7 is_stmt 1 view .LVU707 + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1980 .loc 1 720 14 is_stmt 0 view .LVU708 + 1981 021e 0CE0 b .L101 + 1982 .L119: + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1983 .loc 1 756 5 is_stmt 1 view .LVU709 + 1984 0220 40F23A53 movw r3, #1338 + 1985 0224 8363 str r3, [r0, #56] + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1986 .loc 1 758 5 view .LVU710 + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 1987 .loc 1 758 16 is_stmt 0 view .LVU711 + 1988 0226 0123 movs r3, #1 + 1989 0228 85F83430 strb r3, [r5, #52] + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1990 .loc 1 760 5 is_stmt 1 view .LVU712 + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 1991 .loc 1 760 12 is_stmt 0 view .LVU713 + 1992 022c 0027 movs r7, #0 + 1993 022e 04E0 b .L101 + 1994 .LVL182: + 1995 .L102: + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1996 .loc 1 764 5 is_stmt 1 view .LVU714 + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1997 .loc 1 764 8 is_stmt 0 view .LVU715 + 1998 0230 AB6B ldr r3, [r5, #56] + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 1999 .loc 1 764 20 view .LVU716 + 2000 0232 43F00053 orr r3, r3, #536870912 + 2001 0236 AB63 str r3, [r5, #56] + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2002 .loc 1 765 5 is_stmt 1 view .LVU717 + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2003 .loc 1 765 12 is_stmt 0 view .LVU718 + 2004 0238 0127 movs r7, #1 + 2005 .LVL183: + 2006 .L101: + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2007 .loc 1 767 1 view .LVU719 + 2008 023a 3846 mov r0, r7 + 2009 023c 07B0 add sp, sp, #28 + 2010 .LCFI31: + 2011 .cfi_def_cfa_offset 36 + 2012 @ sp needed + 2013 023e BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 2014 .LVL184: + 2015 .L131: + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2016 .loc 1 767 1 view .LVU720 + 2017 0242 00BF .align 2 + 2018 .L130: + 2019 0244 FF054000 .word 4195839 + ARM GAS /tmp/ccMMu31U.s page 104 + + + 2020 .cfi_endproc + 2021 .LFE146: + 2023 .section .text.HAL_SD_WriteBlocks,"ax",%progbits + 2024 .align 1 + 2025 .global HAL_SD_WriteBlocks + 2026 .syntax unified + 2027 .thumb + 2028 .thumb_func + 2030 HAL_SD_WriteBlocks: + 2031 .LVL185: + 2032 .LFB147: + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; + 2033 .loc 1 782 1 is_stmt 1 view -0 + 2034 .cfi_startproc + 2035 @ args = 4, pretend = 0, frame = 40 + 2036 @ frame_needed = 0, uses_anonymous_args = 0 + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; + 2037 .loc 1 782 1 is_stmt 0 view .LVU722 + 2038 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 2039 .LCFI32: + 2040 .cfi_def_cfa_offset 36 + 2041 .cfi_offset 4, -36 + 2042 .cfi_offset 5, -32 + 2043 .cfi_offset 6, -28 + 2044 .cfi_offset 7, -24 + 2045 .cfi_offset 8, -20 + 2046 .cfi_offset 9, -16 + 2047 .cfi_offset 10, -12 + 2048 .cfi_offset 11, -8 + 2049 .cfi_offset 14, -4 + 2050 0004 8BB0 sub sp, sp, #44 + 2051 .LCFI33: + 2052 .cfi_def_cfa_offset 80 + 2053 0006 0546 mov r5, r0 + 2054 0008 0C46 mov r4, r1 + 2055 000a 1646 mov r6, r2 + 2056 000c 9B46 mov fp, r3 + 2057 000e DDF850A0 ldr r10, [sp, #80] + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 2058 .loc 1 783 3 is_stmt 1 view .LVU723 + 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t tickstart = HAL_GetTick(); + 2059 .loc 1 784 3 view .LVU724 + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t count, data, dataremaining; + 2060 .loc 1 785 3 view .LVU725 + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t count, data, dataremaining; + 2061 .loc 1 785 24 is_stmt 0 view .LVU726 + 2062 0012 FFF7FEFF bl HAL_GetTick + 2063 .LVL186: + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t add = BlockAdd; + 2064 .loc 1 786 3 is_stmt 1 view .LVU727 + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint8_t *tempbuff = pData; + 2065 .loc 1 787 3 view .LVU728 + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2066 .loc 1 788 3 view .LVU729 + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2067 .loc 1 790 3 view .LVU730 + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + ARM GAS /tmp/ccMMu31U.s page 105 + + + 2068 .loc 1 790 5 is_stmt 0 view .LVU731 + 2069 0016 002C cmp r4, #0 + 2070 0018 37D0 beq .L152 + 2071 001a 8046 mov r8, r0 + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2072 .loc 1 796 3 is_stmt 1 view .LVU732 + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2073 .loc 1 796 9 is_stmt 0 view .LVU733 + 2074 001c 95F83470 ldrb r7, [r5, #52] @ zero_extendqisi2 + 2075 0020 FFB2 uxtb r7, r7 + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2076 .loc 1 796 5 view .LVU734 + 2077 0022 012F cmp r7, #1 + 2078 0024 40F0E180 bne .L135 + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2079 .loc 1 798 5 is_stmt 1 view .LVU735 + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2080 .loc 1 798 20 is_stmt 0 view .LVU736 + 2081 0028 0023 movs r3, #0 + 2082 002a AB63 str r3, [r5, #56] + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2083 .loc 1 800 5 is_stmt 1 view .LVU737 + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2084 .loc 1 800 13 is_stmt 0 view .LVU738 + 2085 002c 06EB0B03 add r3, r6, fp + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2086 .loc 1 800 45 view .LVU739 + 2087 0030 EA6D ldr r2, [r5, #92] + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2088 .loc 1 800 7 view .LVU740 + 2089 0032 9342 cmp r3, r2 + 2090 0034 2FD8 bhi .L153 + 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2091 .loc 1 806 5 is_stmt 1 view .LVU741 + 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2092 .loc 1 806 16 is_stmt 0 view .LVU742 + 2093 0036 0323 movs r3, #3 + 2094 0038 85F83430 strb r3, [r5, #52] + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2095 .loc 1 809 5 is_stmt 1 view .LVU743 + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2096 .loc 1 809 8 is_stmt 0 view .LVU744 + 2097 003c 2B68 ldr r3, [r5] + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2098 .loc 1 809 26 view .LVU745 + 2099 003e 0022 movs r2, #0 + 2100 0040 DA62 str r2, [r3, #44] + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2101 .loc 1 811 5 is_stmt 1 view .LVU746 + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2102 .loc 1 811 19 is_stmt 0 view .LVU747 + 2103 0042 6B6C ldr r3, [r5, #68] + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2104 .loc 1 811 7 view .LVU748 + 2105 0044 012B cmp r3, #1 + 2106 0046 00D0 beq .L137 + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + ARM GAS /tmp/ccMMu31U.s page 106 + + + 2107 .loc 1 813 7 is_stmt 1 view .LVU749 + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2108 .loc 1 813 11 is_stmt 0 view .LVU750 + 2109 0048 7602 lsls r6, r6, #9 + 2110 .LVL187: + 2111 .L137: + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = NumberOfBlocks * BLOCKSIZE; + 2112 .loc 1 817 5 is_stmt 1 view .LVU751 + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = NumberOfBlocks * BLOCKSIZE; + 2113 .loc 1 817 26 is_stmt 0 view .LVU752 + 2114 004a 4FF0FF33 mov r3, #-1 + 2115 004e 0493 str r3, [sp, #16] + 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + 2116 .loc 1 818 5 is_stmt 1 view .LVU753 + 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + 2117 .loc 1 818 43 is_stmt 0 view .LVU754 + 2118 0050 4FEA4B23 lsl r3, fp, #9 + 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + 2119 .loc 1 818 26 view .LVU755 + 2120 0054 0593 str r3, [sp, #20] + 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + 2121 .loc 1 819 5 is_stmt 1 view .LVU756 + 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + 2122 .loc 1 819 26 is_stmt 0 view .LVU757 + 2123 0056 9023 movs r3, #144 + 2124 0058 0693 str r3, [sp, #24] + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + 2125 .loc 1 820 5 is_stmt 1 view .LVU758 + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + 2126 .loc 1 820 26 is_stmt 0 view .LVU759 + 2127 005a 0023 movs r3, #0 + 2128 005c 0793 str r3, [sp, #28] + 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; + 2129 .loc 1 821 5 is_stmt 1 view .LVU760 + 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; + 2130 .loc 1 821 26 is_stmt 0 view .LVU761 + 2131 005e 0893 str r3, [sp, #32] + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); + 2132 .loc 1 822 5 is_stmt 1 view .LVU762 + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); + 2133 .loc 1 822 26 is_stmt 0 view .LVU763 + 2134 0060 0123 movs r3, #1 + 2135 0062 0993 str r3, [sp, #36] + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2136 .loc 1 823 5 is_stmt 1 view .LVU764 + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2137 .loc 1 823 11 is_stmt 0 view .LVU765 + 2138 0064 04A9 add r1, sp, #16 + 2139 0066 2868 ldr r0, [r5] + 2140 .LVL188: + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2141 .loc 1 823 11 view .LVU766 + 2142 0068 FFF7FEFF bl SDMMC_ConfigData + 2143 .LVL189: + 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2144 .loc 1 826 5 is_stmt 1 view .LVU767 + 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + ARM GAS /tmp/ccMMu31U.s page 107 + + + 2145 .loc 1 826 7 is_stmt 0 view .LVU768 + 2146 006c BBF1010F cmp fp, #1 + 2147 0070 16D9 bls .L138 + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2148 .loc 1 828 7 is_stmt 1 view .LVU769 + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2149 .loc 1 828 20 is_stmt 0 view .LVU770 + 2150 0072 2023 movs r3, #32 + 2151 0074 2B63 str r3, [r5, #48] + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2152 .loc 1 831 7 is_stmt 1 view .LVU771 + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2153 .loc 1 831 20 is_stmt 0 view .LVU772 + 2154 0076 3146 mov r1, r6 + 2155 0078 2868 ldr r0, [r5] + 2156 007a FFF7FEFF bl SDMMC_CmdWriteMultiBlock + 2157 .LVL190: + 2158 007e 0190 str r0, [sp, #4] + 2159 .LVL191: + 2160 .L139: + 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2161 .loc 1 840 5 is_stmt 1 view .LVU773 + 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2162 .loc 1 840 7 is_stmt 0 view .LVU774 + 2163 0080 019B ldr r3, [sp, #4] + 2164 0082 ABB9 cbnz r3, .L154 + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | + 2165 .loc 1 851 5 is_stmt 1 view .LVU775 + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | + 2166 .loc 1 851 19 is_stmt 0 view .LVU776 + 2167 0084 DDF81490 ldr r9, [sp, #20] + 2168 .LVL192: + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2169 .loc 1 852 5 is_stmt 1 view .LVU777 + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2170 .loc 1 852 10 is_stmt 0 view .LVU778 + 2171 0088 40E0 b .L141 + 2172 .LVL193: + 2173 .L152: + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2174 .loc 1 792 5 is_stmt 1 view .LVU779 + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2175 .loc 1 792 8 is_stmt 0 view .LVU780 + 2176 008a AB6B ldr r3, [r5, #56] + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2177 .loc 1 792 20 view .LVU781 + 2178 008c 43F00063 orr r3, r3, #134217728 + 2179 0090 AB63 str r3, [r5, #56] + 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2180 .loc 1 793 5 is_stmt 1 view .LVU782 + 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2181 .loc 1 793 12 is_stmt 0 view .LVU783 + 2182 0092 0127 movs r7, #1 + 2183 0094 AEE0 b .L134 + 2184 .L153: + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2185 .loc 1 802 7 is_stmt 1 view .LVU784 + ARM GAS /tmp/ccMMu31U.s page 108 + + + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2186 .loc 1 802 10 is_stmt 0 view .LVU785 + 2187 0096 AB6B ldr r3, [r5, #56] + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2188 .loc 1 802 22 view .LVU786 + 2189 0098 43F00073 orr r3, r3, #33554432 + 2190 009c AB63 str r3, [r5, #56] + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2191 .loc 1 803 7 is_stmt 1 view .LVU787 + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2192 .loc 1 803 14 is_stmt 0 view .LVU788 + 2193 009e A9E0 b .L134 + 2194 .LVL194: + 2195 .L138: + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2196 .loc 1 835 7 is_stmt 1 view .LVU789 + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2197 .loc 1 835 20 is_stmt 0 view .LVU790 + 2198 00a0 1023 movs r3, #16 + 2199 00a2 2B63 str r3, [r5, #48] + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2200 .loc 1 838 7 is_stmt 1 view .LVU791 + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2201 .loc 1 838 20 is_stmt 0 view .LVU792 + 2202 00a4 3146 mov r1, r6 + 2203 00a6 2868 ldr r0, [r5] + 2204 00a8 FFF7FEFF bl SDMMC_CmdWriteSingleBlock + 2205 .LVL195: + 2206 00ac 0190 str r0, [sp, #4] + 2207 .LVL196: + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2208 .loc 1 838 20 view .LVU793 + 2209 00ae E7E7 b .L139 + 2210 .LVL197: + 2211 .L154: + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 2212 .loc 1 843 7 is_stmt 1 view .LVU794 + 2213 00b0 2B68 ldr r3, [r5] + 2214 .LVL198: + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 2215 .loc 1 843 7 is_stmt 0 view .LVU795 + 2216 00b2 524A ldr r2, .L159 + 2217 00b4 9A63 str r2, [r3, #56] + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2218 .loc 1 844 7 is_stmt 1 view .LVU796 + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2219 .loc 1 844 10 is_stmt 0 view .LVU797 + 2220 00b6 AB6B ldr r3, [r5, #56] + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2221 .loc 1 844 22 view .LVU798 + 2222 00b8 019A ldr r2, [sp, #4] + 2223 00ba 1343 orrs r3, r3, r2 + 2224 00bc AB63 str r3, [r5, #56] + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 2225 .loc 1 845 7 is_stmt 1 view .LVU799 + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 2226 .loc 1 845 18 is_stmt 0 view .LVU800 + ARM GAS /tmp/ccMMu31U.s page 109 + + + 2227 00be 0123 movs r3, #1 + 2228 00c0 85F83430 strb r3, [r5, #52] + 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2229 .loc 1 846 7 is_stmt 1 view .LVU801 + 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2230 .loc 1 846 20 is_stmt 0 view .LVU802 + 2231 00c4 0023 movs r3, #0 + 2232 00c6 2B63 str r3, [r5, #48] + 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2233 .loc 1 847 7 is_stmt 1 view .LVU803 + 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2234 .loc 1 847 14 is_stmt 0 view .LVU804 + 2235 00c8 94E0 b .L134 + 2236 .LVL199: + 2237 .L144: + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 2238 .loc 1 859 11 is_stmt 1 view .LVU805 + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 2239 .loc 1 859 29 is_stmt 0 view .LVU806 + 2240 00ca 2378 ldrb r3, [r4] @ zero_extendqisi2 + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 2241 .loc 1 859 16 view .LVU807 + 2242 00cc 0393 str r3, [sp, #12] + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 2243 .loc 1 860 11 is_stmt 1 view .LVU808 + 2244 .LVL200: + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** data |= ((uint32_t)(*tempbuff) << 8U); + 2245 .loc 1 861 11 view .LVU809 + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 2246 .loc 1 862 11 view .LVU810 + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 2247 .loc 1 862 31 is_stmt 0 view .LVU811 + 2248 00ce 6278 ldrb r2, [r4, #1] @ zero_extendqisi2 + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 2249 .loc 1 862 16 view .LVU812 + 2250 00d0 43EA0223 orr r3, r3, r2, lsl #8 + 2251 00d4 0393 str r3, [sp, #12] + 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 2252 .loc 1 863 11 is_stmt 1 view .LVU813 + 2253 .LVL201: + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** data |= ((uint32_t)(*tempbuff) << 16U); + 2254 .loc 1 864 11 view .LVU814 + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 2255 .loc 1 865 11 view .LVU815 + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 2256 .loc 1 865 31 is_stmt 0 view .LVU816 + 2257 00d6 A278 ldrb r2, [r4, #2] @ zero_extendqisi2 + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 2258 .loc 1 865 16 view .LVU817 + 2259 00d8 43EA0243 orr r3, r3, r2, lsl #16 + 2260 00dc 0393 str r3, [sp, #12] + 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 2261 .loc 1 866 11 is_stmt 1 view .LVU818 + 2262 .LVL202: + 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** data |= ((uint32_t)(*tempbuff) << 24U); + 2263 .loc 1 867 11 view .LVU819 + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + ARM GAS /tmp/ccMMu31U.s page 110 + + + 2264 .loc 1 868 11 view .LVU820 + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 2265 .loc 1 868 31 is_stmt 0 view .LVU821 + 2266 00de E278 ldrb r2, [r4, #3] @ zero_extendqisi2 + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** tempbuff++; + 2267 .loc 1 868 16 view .LVU822 + 2268 00e0 43EA0263 orr r3, r3, r2, lsl #24 + 2269 00e4 0393 str r3, [sp, #12] + 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 2270 .loc 1 869 11 is_stmt 1 view .LVU823 + 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** dataremaining--; + 2271 .loc 1 869 19 is_stmt 0 view .LVU824 + 2272 00e6 0434 adds r4, r4, #4 + 2273 .LVL203: + 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_WriteFIFO(hsd->Instance, &data); + 2274 .loc 1 870 11 is_stmt 1 view .LVU825 + 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_WriteFIFO(hsd->Instance, &data); + 2275 .loc 1 870 24 is_stmt 0 view .LVU826 + 2276 00e8 A9F10409 sub r9, r9, #4 + 2277 .LVL204: + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2278 .loc 1 871 11 is_stmt 1 view .LVU827 + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2279 .loc 1 871 17 is_stmt 0 view .LVU828 + 2280 00ec 03A9 add r1, sp, #12 + 2281 00ee 2868 ldr r0, [r5] + 2282 00f0 FFF7FEFF bl SDMMC_WriteFIFO + 2283 .LVL205: + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2284 .loc 1 857 42 is_stmt 1 discriminator 3 view .LVU829 + 2285 00f4 0136 adds r6, r6, #1 + 2286 .LVL206: + 2287 .L143: + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2288 .loc 1 857 31 discriminator 1 view .LVU830 + 2289 00f6 072E cmp r6, #7 + 2290 00f8 E7D9 bls .L144 + 2291 .LVL207: + 2292 .L142: + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2293 .loc 1 875 7 view .LVU831 + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2294 .loc 1 875 12 is_stmt 0 view .LVU832 + 2295 00fa FFF7FEFF bl HAL_GetTick + 2296 .LVL208: + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2297 .loc 1 875 25 discriminator 1 view .LVU833 + 2298 00fe A0EB0800 sub r0, r0, r8 + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2299 .loc 1 875 9 discriminator 1 view .LVU834 + 2300 0102 5045 cmp r0, r10 + 2301 0104 0FD2 bcs .L145 + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2302 .loc 1 875 50 discriminator 1 view .LVU835 + 2303 0106 BAF1000F cmp r10, #0 + 2304 010a 0CD0 beq .L145 + 2305 .L141: + ARM GAS /tmp/ccMMu31U.s page 111 + + + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2306 .loc 1 852 11 is_stmt 1 view .LVU836 + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2307 .loc 1 852 12 is_stmt 0 view .LVU837 + 2308 010c 2868 ldr r0, [r5] + 2309 010e 466B ldr r6, [r0, #52] + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2310 .loc 1 852 11 view .LVU838 + 2311 0110 16F48D76 ands r6, r6, #282 + 2312 0114 15D1 bne .L155 + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2313 .loc 1 854 7 is_stmt 1 view .LVU839 + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2314 .loc 1 854 10 is_stmt 0 view .LVU840 + 2315 0116 436B ldr r3, [r0, #52] + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2316 .loc 1 854 9 view .LVU841 + 2317 0118 13F4804F tst r3, #16384 + 2318 011c EDD0 beq .L142 + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2319 .loc 1 854 54 discriminator 1 view .LVU842 + 2320 011e B9F1000F cmp r9, #0 + 2321 0122 EAD0 beq .L142 + 2322 0124 E7E7 b .L143 + 2323 .L145: + 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 2324 .loc 1 878 9 is_stmt 1 view .LVU843 + 2325 0126 2B68 ldr r3, [r5] + 2326 0128 344A ldr r2, .L159 + 2327 012a 9A63 str r2, [r3, #56] + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2328 .loc 1 879 9 view .LVU844 + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2329 .loc 1 879 12 is_stmt 0 view .LVU845 + 2330 012c AB6B ldr r3, [r5, #56] + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2331 .loc 1 879 24 view .LVU846 + 2332 012e 019A ldr r2, [sp, #4] + 2333 0130 1343 orrs r3, r3, r2 + 2334 0132 AB63 str r3, [r5, #56] + 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 2335 .loc 1 880 9 is_stmt 1 view .LVU847 + 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 2336 .loc 1 880 20 is_stmt 0 view .LVU848 + 2337 0134 0123 movs r3, #1 + 2338 0136 85F83430 strb r3, [r5, #52] + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_TIMEOUT; + 2339 .loc 1 881 9 is_stmt 1 view .LVU849 + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_TIMEOUT; + 2340 .loc 1 881 22 is_stmt 0 view .LVU850 + 2341 013a 0023 movs r3, #0 + 2342 013c 2B63 str r3, [r5, #48] + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2343 .loc 1 882 9 is_stmt 1 view .LVU851 + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2344 .loc 1 882 16 is_stmt 0 view .LVU852 + 2345 013e 0327 movs r7, #3 + ARM GAS /tmp/ccMMu31U.s page 112 + + + 2346 0140 58E0 b .L134 + 2347 .L155: + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2348 .loc 1 887 5 is_stmt 1 view .LVU853 + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2349 .loc 1 887 8 is_stmt 0 view .LVU854 + 2350 0142 436B ldr r3, [r0, #52] + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2351 .loc 1 887 7 view .LVU855 + 2352 0144 13F4807F tst r3, #256 + 2353 0148 05D0 beq .L147 + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2354 .loc 1 887 51 discriminator 1 view .LVU856 + 2355 014a BBF1010F cmp fp, #1 + 2356 014e 02D9 bls .L147 + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2357 .loc 1 889 7 is_stmt 1 view .LVU857 + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2358 .loc 1 889 21 is_stmt 0 view .LVU858 + 2359 0150 6B6C ldr r3, [r5, #68] + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2360 .loc 1 889 9 view .LVU859 + 2361 0152 032B cmp r3, #3 + 2362 0154 18D1 bne .L156 + 2363 .LVL209: + 2364 .L147: + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2365 .loc 1 906 5 is_stmt 1 view .LVU860 + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2366 .loc 1 906 8 is_stmt 0 view .LVU861 + 2367 0156 2B68 ldr r3, [r5] + 2368 0158 5A6B ldr r2, [r3, #52] + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2369 .loc 1 906 7 view .LVU862 + 2370 015a 12F0080F tst r2, #8 + 2371 015e 24D1 bne .L157 + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2372 .loc 1 915 10 is_stmt 1 view .LVU863 + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2373 .loc 1 915 13 is_stmt 0 view .LVU864 + 2374 0160 5A6B ldr r2, [r3, #52] + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2375 .loc 1 915 12 view .LVU865 + 2376 0162 12F0020F tst r2, #2 + 2377 0166 2CD1 bne .L158 + 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2378 .loc 1 924 10 is_stmt 1 view .LVU866 + 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2379 .loc 1 924 13 is_stmt 0 view .LVU867 + 2380 0168 5A6B ldr r2, [r3, #52] + 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2381 .loc 1 924 12 view .LVU868 + 2382 016a 12F0100F tst r2, #16 + 2383 016e 34D0 beq .L150 + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; + 2384 .loc 1 927 7 is_stmt 1 view .LVU869 + 2385 0170 224A ldr r2, .L159 + ARM GAS /tmp/ccMMu31U.s page 113 + + + 2386 0172 9A63 str r2, [r3, #56] + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2387 .loc 1 928 7 view .LVU870 + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2388 .loc 1 928 10 is_stmt 0 view .LVU871 + 2389 0174 AB6B ldr r3, [r5, #56] + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2390 .loc 1 928 22 view .LVU872 + 2391 0176 43F01003 orr r3, r3, #16 + 2392 017a AB63 str r3, [r5, #56] + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 2393 .loc 1 929 7 is_stmt 1 view .LVU873 + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 2394 .loc 1 929 18 is_stmt 0 view .LVU874 + 2395 017c 0123 movs r3, #1 + 2396 017e 85F83430 strb r3, [r5, #52] + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2397 .loc 1 930 7 is_stmt 1 view .LVU875 + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2398 .loc 1 930 20 is_stmt 0 view .LVU876 + 2399 0182 0023 movs r3, #0 + 2400 0184 2B63 str r3, [r5, #48] + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2401 .loc 1 931 7 is_stmt 1 view .LVU877 + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2402 .loc 1 931 14 is_stmt 0 view .LVU878 + 2403 0186 35E0 b .L134 + 2404 .LVL210: + 2405 .L156: + 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 2406 .loc 1 892 9 is_stmt 1 view .LVU879 + 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 2407 .loc 1 892 22 is_stmt 0 view .LVU880 + 2408 0188 FFF7FEFF bl SDMMC_CmdStopTransfer + 2409 .LVL211: + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2410 .loc 1 893 9 is_stmt 1 view .LVU881 + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2411 .loc 1 893 11 is_stmt 0 view .LVU882 + 2412 018c 0346 mov r3, r0 + 2413 018e 0028 cmp r0, #0 + 2414 0190 E1D0 beq .L147 + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 2415 .loc 1 896 11 is_stmt 1 view .LVU883 + 2416 0192 2A68 ldr r2, [r5] + 2417 0194 1949 ldr r1, .L159 + 2418 0196 9163 str r1, [r2, #56] + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2419 .loc 1 897 11 view .LVU884 + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2420 .loc 1 897 14 is_stmt 0 view .LVU885 + 2421 0198 AA6B ldr r2, [r5, #56] + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2422 .loc 1 897 26 view .LVU886 + 2423 019a 1343 orrs r3, r3, r2 + 2424 019c AB63 str r3, [r5, #56] + 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + ARM GAS /tmp/ccMMu31U.s page 114 + + + 2425 .loc 1 898 11 is_stmt 1 view .LVU887 + 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 2426 .loc 1 898 22 is_stmt 0 view .LVU888 + 2427 019e 0123 movs r3, #1 + 2428 01a0 85F83430 strb r3, [r5, #52] + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2429 .loc 1 899 11 is_stmt 1 view .LVU889 + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2430 .loc 1 899 24 is_stmt 0 view .LVU890 + 2431 01a4 0023 movs r3, #0 + 2432 01a6 2B63 str r3, [r5, #48] + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2433 .loc 1 900 11 is_stmt 1 view .LVU891 + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2434 .loc 1 900 18 is_stmt 0 view .LVU892 + 2435 01a8 24E0 b .L134 + 2436 .LVL212: + 2437 .L157: + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + 2438 .loc 1 909 7 is_stmt 1 view .LVU893 + 2439 01aa 144A ldr r2, .L159 + 2440 01ac 9A63 str r2, [r3, #56] + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2441 .loc 1 910 7 view .LVU894 + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2442 .loc 1 910 10 is_stmt 0 view .LVU895 + 2443 01ae AB6B ldr r3, [r5, #56] + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2444 .loc 1 910 22 view .LVU896 + 2445 01b0 43F00803 orr r3, r3, #8 + 2446 01b4 AB63 str r3, [r5, #56] + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 2447 .loc 1 911 7 is_stmt 1 view .LVU897 + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 2448 .loc 1 911 18 is_stmt 0 view .LVU898 + 2449 01b6 0123 movs r3, #1 + 2450 01b8 85F83430 strb r3, [r5, #52] + 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2451 .loc 1 912 7 is_stmt 1 view .LVU899 + 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2452 .loc 1 912 20 is_stmt 0 view .LVU900 + 2453 01bc 0023 movs r3, #0 + 2454 01be 2B63 str r3, [r5, #48] + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2455 .loc 1 913 7 is_stmt 1 view .LVU901 + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2456 .loc 1 913 14 is_stmt 0 view .LVU902 + 2457 01c0 18E0 b .L134 + 2458 .L158: + 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + 2459 .loc 1 918 7 is_stmt 1 view .LVU903 + 2460 01c2 0E4A ldr r2, .L159 + 2461 01c4 9A63 str r2, [r3, #56] + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2462 .loc 1 919 7 view .LVU904 + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2463 .loc 1 919 10 is_stmt 0 view .LVU905 + ARM GAS /tmp/ccMMu31U.s page 115 + + + 2464 01c6 AB6B ldr r3, [r5, #56] + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2465 .loc 1 919 22 view .LVU906 + 2466 01c8 43F00203 orr r3, r3, #2 + 2467 01cc AB63 str r3, [r5, #56] + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 2468 .loc 1 920 7 is_stmt 1 view .LVU907 + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 2469 .loc 1 920 18 is_stmt 0 view .LVU908 + 2470 01ce 0123 movs r3, #1 + 2471 01d0 85F83430 strb r3, [r5, #52] + 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2472 .loc 1 921 7 is_stmt 1 view .LVU909 + 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2473 .loc 1 921 20 is_stmt 0 view .LVU910 + 2474 01d4 0023 movs r3, #0 + 2475 01d6 2B63 str r3, [r5, #48] + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2476 .loc 1 922 7 is_stmt 1 view .LVU911 + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2477 .loc 1 922 14 is_stmt 0 view .LVU912 + 2478 01d8 0CE0 b .L134 + 2479 .L150: + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2480 .loc 1 936 5 is_stmt 1 view .LVU913 + 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2481 .loc 1 939 5 view .LVU914 + 2482 01da 40F23A52 movw r2, #1338 + 2483 01de 9A63 str r2, [r3, #56] + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2484 .loc 1 941 5 view .LVU915 + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2485 .loc 1 941 16 is_stmt 0 view .LVU916 + 2486 01e0 0123 movs r3, #1 + 2487 01e2 85F83430 strb r3, [r5, #52] + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2488 .loc 1 943 5 is_stmt 1 view .LVU917 + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2489 .loc 1 943 12 is_stmt 0 view .LVU918 + 2490 01e6 0027 movs r7, #0 + 2491 01e8 04E0 b .L134 + 2492 .LVL213: + 2493 .L135: + 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2494 .loc 1 947 5 is_stmt 1 view .LVU919 + 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2495 .loc 1 947 8 is_stmt 0 view .LVU920 + 2496 01ea AB6B ldr r3, [r5, #56] + 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2497 .loc 1 947 20 view .LVU921 + 2498 01ec 43F00053 orr r3, r3, #536870912 + 2499 01f0 AB63 str r3, [r5, #56] + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2500 .loc 1 948 5 is_stmt 1 view .LVU922 + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2501 .loc 1 948 12 is_stmt 0 view .LVU923 + 2502 01f2 0127 movs r7, #1 + ARM GAS /tmp/ccMMu31U.s page 116 + + + 2503 .LVL214: + 2504 .L134: + 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2505 .loc 1 950 1 view .LVU924 + 2506 01f4 3846 mov r0, r7 + 2507 01f6 0BB0 add sp, sp, #44 + 2508 .LCFI34: + 2509 .cfi_def_cfa_offset 36 + 2510 @ sp needed + 2511 01f8 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 2512 .LVL215: + 2513 .L160: + 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2514 .loc 1 950 1 view .LVU925 + 2515 .align 2 + 2516 .L159: + 2517 01fc FF054000 .word 4195839 + 2518 .cfi_endproc + 2519 .LFE147: + 2521 .section .text.HAL_SD_ReadBlocks_IT,"ax",%progbits + 2522 .align 1 + 2523 .global HAL_SD_ReadBlocks_IT + 2524 .syntax unified + 2525 .thumb + 2526 .thumb_func + 2528 HAL_SD_ReadBlocks_IT: + 2529 .LVL216: + 2530 .LFB148: + 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; + 2531 .loc 1 966 1 is_stmt 1 view -0 + 2532 .cfi_startproc + 2533 @ args = 0, pretend = 0, frame = 24 + 2534 @ frame_needed = 0, uses_anonymous_args = 0 + 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; + 2535 .loc 1 966 1 is_stmt 0 view .LVU927 + 2536 0000 F0B5 push {r4, r5, r6, r7, lr} + 2537 .LCFI35: + 2538 .cfi_def_cfa_offset 20 + 2539 .cfi_offset 4, -20 + 2540 .cfi_offset 5, -16 + 2541 .cfi_offset 6, -12 + 2542 .cfi_offset 7, -8 + 2543 .cfi_offset 14, -4 + 2544 0002 87B0 sub sp, sp, #28 + 2545 .LCFI36: + 2546 .cfi_def_cfa_offset 48 + 2547 0004 0446 mov r4, r0 + 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 2548 .loc 1 967 3 is_stmt 1 view .LVU928 + 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t add = BlockAdd; + 2549 .loc 1 968 3 view .LVU929 + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2550 .loc 1 969 3 view .LVU930 + 2551 .LVL217: + 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2552 .loc 1 971 3 view .LVU931 + 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + ARM GAS /tmp/ccMMu31U.s page 117 + + + 2553 .loc 1 971 5 is_stmt 0 view .LVU932 + 2554 0006 0029 cmp r1, #0 + 2555 0008 45D0 beq .L171 + 2556 000a 1646 mov r6, r2 + 2557 000c 1F46 mov r7, r3 + 2558 000e 0A46 mov r2, r1 + 2559 .LVL218: + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2560 .loc 1 977 3 is_stmt 1 view .LVU933 + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2561 .loc 1 977 9 is_stmt 0 view .LVU934 + 2562 0010 90F83450 ldrb r5, [r0, #52] @ zero_extendqisi2 + 2563 0014 EDB2 uxtb r5, r5 + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2564 .loc 1 977 5 view .LVU935 + 2565 0016 012D cmp r5, #1 + 2566 0018 4FD1 bne .L168 + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2567 .loc 1 979 5 is_stmt 1 view .LVU936 + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2568 .loc 1 979 20 is_stmt 0 view .LVU937 + 2569 001a 0023 movs r3, #0 + 2570 .LVL219: + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2571 .loc 1 979 20 view .LVU938 + 2572 001c 8363 str r3, [r0, #56] + 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2573 .loc 1 981 5 is_stmt 1 view .LVU939 + 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2574 .loc 1 981 13 is_stmt 0 view .LVU940 + 2575 001e F319 adds r3, r6, r7 + 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2576 .loc 1 981 45 view .LVU941 + 2577 0020 C16D ldr r1, [r0, #92] + 2578 .LVL220: + 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2579 .loc 1 981 7 view .LVU942 + 2580 0022 8B42 cmp r3, r1 + 2581 0024 3DD8 bhi .L172 + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2582 .loc 1 987 5 is_stmt 1 view .LVU943 + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2583 .loc 1 987 16 is_stmt 0 view .LVU944 + 2584 0026 0323 movs r3, #3 + 2585 0028 80F83430 strb r3, [r0, #52] + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2586 .loc 1 990 5 is_stmt 1 view .LVU945 + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2587 .loc 1 990 8 is_stmt 0 view .LVU946 + 2588 002c 0368 ldr r3, [r0] + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2589 .loc 1 990 26 view .LVU947 + 2590 002e 0021 movs r1, #0 + 2591 0030 D962 str r1, [r3, #44] + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; + 2592 .loc 1 992 5 is_stmt 1 view .LVU948 + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; + ARM GAS /tmp/ccMMu31U.s page 118 + + + 2593 .loc 1 992 21 is_stmt 0 view .LVU949 + 2594 0032 8262 str r2, [r0, #40] + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2595 .loc 1 993 5 is_stmt 1 view .LVU950 + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2596 .loc 1 993 33 is_stmt 0 view .LVU951 + 2597 0034 7A02 lsls r2, r7, #9 + 2598 .LVL221: + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2599 .loc 1 993 21 view .LVU952 + 2600 0036 C262 str r2, [r0, #44] + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2601 .loc 1 995 5 is_stmt 1 view .LVU953 + 2602 0038 0168 ldr r1, [r0] + 2603 003a C86B ldr r0, [r1, #60] + 2604 .LVL222: + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2605 .loc 1 995 5 is_stmt 0 view .LVU954 + 2606 003c 48F22A13 movw r3, #33066 + 2607 0040 0343 orrs r3, r3, r0 + 2608 0042 CB63 str r3, [r1, #60] + 2609 .LVL223: + 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2610 .loc 1 997 5 is_stmt 1 view .LVU955 + 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2611 .loc 1 997 19 is_stmt 0 view .LVU956 + 2612 0044 636C ldr r3, [r4, #68] + 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2613 .loc 1 997 7 view .LVU957 + 2614 0046 012B cmp r3, #1 + 2615 0048 00D0 beq .L165 + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2616 .loc 1 999 7 is_stmt 1 view .LVU958 + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2617 .loc 1 999 11 is_stmt 0 view .LVU959 + 2618 004a 7602 lsls r6, r6, #9 + 2619 .LVL224: + 2620 .L165: +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = BLOCKSIZE * NumberOfBlocks; + 2621 .loc 1 1003 5 is_stmt 1 view .LVU960 +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = BLOCKSIZE * NumberOfBlocks; + 2622 .loc 1 1003 26 is_stmt 0 view .LVU961 + 2623 004c 4FF0FF33 mov r3, #-1 + 2624 0050 0093 str r3, [sp] +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + 2625 .loc 1 1004 5 is_stmt 1 view .LVU962 +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + 2626 .loc 1 1004 26 is_stmt 0 view .LVU963 + 2627 0052 0192 str r2, [sp, #4] +1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + 2628 .loc 1 1005 5 is_stmt 1 view .LVU964 +1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + 2629 .loc 1 1005 26 is_stmt 0 view .LVU965 + 2630 0054 9023 movs r3, #144 + 2631 0056 0293 str r3, [sp, #8] +1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + 2632 .loc 1 1006 5 is_stmt 1 view .LVU966 + ARM GAS /tmp/ccMMu31U.s page 119 + + +1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + 2633 .loc 1 1006 26 is_stmt 0 view .LVU967 + 2634 0058 0223 movs r3, #2 + 2635 005a 0393 str r3, [sp, #12] +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; + 2636 .loc 1 1007 5 is_stmt 1 view .LVU968 +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; + 2637 .loc 1 1007 26 is_stmt 0 view .LVU969 + 2638 005c 0023 movs r3, #0 + 2639 005e 0493 str r3, [sp, #16] +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); + 2640 .loc 1 1008 5 is_stmt 1 view .LVU970 +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); + 2641 .loc 1 1008 26 is_stmt 0 view .LVU971 + 2642 0060 0123 movs r3, #1 + 2643 0062 0593 str r3, [sp, #20] +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2644 .loc 1 1009 5 is_stmt 1 view .LVU972 +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2645 .loc 1 1009 11 is_stmt 0 view .LVU973 + 2646 0064 6946 mov r1, sp + 2647 0066 2068 ldr r0, [r4] + 2648 0068 FFF7FEFF bl SDMMC_ConfigData + 2649 .LVL225: +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2650 .loc 1 1012 5 is_stmt 1 view .LVU974 +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2651 .loc 1 1012 7 is_stmt 0 view .LVU975 + 2652 006c 012F cmp r7, #1 + 2653 006e 1DD9 bls .L166 +1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2654 .loc 1 1014 7 is_stmt 1 view .LVU976 +1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2655 .loc 1 1014 20 is_stmt 0 view .LVU977 + 2656 0070 0A23 movs r3, #10 + 2657 0072 2363 str r3, [r4, #48] +1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2658 .loc 1 1017 7 is_stmt 1 view .LVU978 +1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2659 .loc 1 1017 20 is_stmt 0 view .LVU979 + 2660 0074 3146 mov r1, r6 + 2661 0076 2068 ldr r0, [r4] + 2662 0078 FFF7FEFF bl SDMMC_CmdReadMultiBlock + 2663 .LVL226: + 2664 .L167: +1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2665 .loc 1 1026 5 is_stmt 1 view .LVU980 +1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2666 .loc 1 1026 7 is_stmt 0 view .LVU981 + 2667 007c 08B3 cbz r0, .L169 +1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 2668 .loc 1 1029 7 is_stmt 1 view .LVU982 + 2669 007e 2368 ldr r3, [r4] + 2670 0080 114A ldr r2, .L173 + 2671 0082 9A63 str r2, [r3, #56] +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2672 .loc 1 1030 7 view .LVU983 + ARM GAS /tmp/ccMMu31U.s page 120 + + +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2673 .loc 1 1030 10 is_stmt 0 view .LVU984 + 2674 0084 A36B ldr r3, [r4, #56] +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2675 .loc 1 1030 22 view .LVU985 + 2676 0086 0343 orrs r3, r3, r0 + 2677 0088 A363 str r3, [r4, #56] +1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 2678 .loc 1 1031 7 is_stmt 1 view .LVU986 +1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 2679 .loc 1 1031 18 is_stmt 0 view .LVU987 + 2680 008a 0123 movs r3, #1 + 2681 008c 84F83430 strb r3, [r4, #52] +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2682 .loc 1 1032 7 is_stmt 1 view .LVU988 +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2683 .loc 1 1032 20 is_stmt 0 view .LVU989 + 2684 0090 0023 movs r3, #0 + 2685 0092 2363 str r3, [r4, #48] +1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2686 .loc 1 1033 7 is_stmt 1 view .LVU990 +1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2687 .loc 1 1033 14 is_stmt 0 view .LVU991 + 2688 0094 12E0 b .L163 + 2689 .LVL227: + 2690 .L171: + 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2691 .loc 1 973 5 is_stmt 1 view .LVU992 + 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2692 .loc 1 973 8 is_stmt 0 view .LVU993 + 2693 0096 836B ldr r3, [r0, #56] + 2694 .LVL228: + 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2695 .loc 1 973 20 view .LVU994 + 2696 0098 43F00063 orr r3, r3, #134217728 + 2697 009c 8363 str r3, [r0, #56] + 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2698 .loc 1 974 5 is_stmt 1 view .LVU995 + 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2699 .loc 1 974 12 is_stmt 0 view .LVU996 + 2700 009e 0125 movs r5, #1 + 2701 00a0 0CE0 b .L163 + 2702 .LVL229: + 2703 .L172: + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2704 .loc 1 983 7 is_stmt 1 view .LVU997 + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2705 .loc 1 983 10 is_stmt 0 view .LVU998 + 2706 00a2 836B ldr r3, [r0, #56] + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2707 .loc 1 983 22 view .LVU999 + 2708 00a4 43F00073 orr r3, r3, #33554432 + 2709 00a8 8363 str r3, [r0, #56] + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2710 .loc 1 984 7 is_stmt 1 view .LVU1000 + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2711 .loc 1 984 14 is_stmt 0 view .LVU1001 + ARM GAS /tmp/ccMMu31U.s page 121 + + + 2712 00aa 07E0 b .L163 + 2713 .LVL230: + 2714 .L166: +1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2715 .loc 1 1021 7 is_stmt 1 view .LVU1002 +1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2716 .loc 1 1021 20 is_stmt 0 view .LVU1003 + 2717 00ac 0923 movs r3, #9 + 2718 00ae 2363 str r3, [r4, #48] +1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2719 .loc 1 1024 7 is_stmt 1 view .LVU1004 +1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2720 .loc 1 1024 20 is_stmt 0 view .LVU1005 + 2721 00b0 3146 mov r1, r6 + 2722 00b2 2068 ldr r0, [r4] + 2723 00b4 FFF7FEFF bl SDMMC_CmdReadSingleBlock + 2724 .LVL231: +1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2725 .loc 1 1024 20 view .LVU1006 + 2726 00b8 E0E7 b .L167 + 2727 .LVL232: + 2728 .L168: +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2729 .loc 1 1040 12 view .LVU1007 + 2730 00ba 0225 movs r5, #2 + 2731 .LVL233: + 2732 .L163: +1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2733 .loc 1 1042 1 view .LVU1008 + 2734 00bc 2846 mov r0, r5 + 2735 00be 07B0 add sp, sp, #28 + 2736 .LCFI37: + 2737 .cfi_remember_state + 2738 .cfi_def_cfa_offset 20 + 2739 @ sp needed + 2740 00c0 F0BD pop {r4, r5, r6, r7, pc} + 2741 .LVL234: + 2742 .L169: + 2743 .LCFI38: + 2744 .cfi_restore_state +1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2745 .loc 1 1036 12 view .LVU1009 + 2746 00c2 0025 movs r5, #0 + 2747 00c4 FAE7 b .L163 + 2748 .L174: + 2749 00c6 00BF .align 2 + 2750 .L173: + 2751 00c8 FF054000 .word 4195839 + 2752 .cfi_endproc + 2753 .LFE148: + 2755 .section .text.HAL_SD_WriteBlocks_IT,"ax",%progbits + 2756 .align 1 + 2757 .global HAL_SD_WriteBlocks_IT + 2758 .syntax unified + 2759 .thumb + 2760 .thumb_func + 2762 HAL_SD_WriteBlocks_IT: + ARM GAS /tmp/ccMMu31U.s page 122 + + + 2763 .LVL235: + 2764 .LFB149: +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; + 2765 .loc 1 1058 1 is_stmt 1 view -0 + 2766 .cfi_startproc + 2767 @ args = 0, pretend = 0, frame = 24 + 2768 @ frame_needed = 0, uses_anonymous_args = 0 +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; + 2769 .loc 1 1058 1 is_stmt 0 view .LVU1011 + 2770 0000 F0B5 push {r4, r5, r6, r7, lr} + 2771 .LCFI39: + 2772 .cfi_def_cfa_offset 20 + 2773 .cfi_offset 4, -20 + 2774 .cfi_offset 5, -16 + 2775 .cfi_offset 6, -12 + 2776 .cfi_offset 7, -8 + 2777 .cfi_offset 14, -4 + 2778 0002 87B0 sub sp, sp, #28 + 2779 .LCFI40: + 2780 .cfi_def_cfa_offset 48 + 2781 0004 0446 mov r4, r0 +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 2782 .loc 1 1059 3 is_stmt 1 view .LVU1012 +1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t add = BlockAdd; + 2783 .loc 1 1060 3 view .LVU1013 +1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2784 .loc 1 1061 3 view .LVU1014 + 2785 .LVL236: +1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2786 .loc 1 1063 3 view .LVU1015 +1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2787 .loc 1 1063 5 is_stmt 0 view .LVU1016 + 2788 0006 0029 cmp r1, #0 + 2789 0008 33D0 beq .L185 + 2790 000a 0846 mov r0, r1 + 2791 .LVL237: +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2792 .loc 1 1069 3 is_stmt 1 view .LVU1017 +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2793 .loc 1 1069 9 is_stmt 0 view .LVU1018 + 2794 000c 94F83450 ldrb r5, [r4, #52] @ zero_extendqisi2 + 2795 0010 EDB2 uxtb r5, r5 +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2796 .loc 1 1069 5 view .LVU1019 + 2797 0012 012D cmp r5, #1 + 2798 0014 4FD1 bne .L183 +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2799 .loc 1 1071 5 is_stmt 1 view .LVU1020 +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2800 .loc 1 1071 20 is_stmt 0 view .LVU1021 + 2801 0016 0021 movs r1, #0 + 2802 .LVL238: +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2803 .loc 1 1071 20 view .LVU1022 + 2804 0018 A163 str r1, [r4, #56] +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2805 .loc 1 1073 5 is_stmt 1 view .LVU1023 + ARM GAS /tmp/ccMMu31U.s page 123 + + +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2806 .loc 1 1073 13 is_stmt 0 view .LVU1024 + 2807 001a D118 adds r1, r2, r3 +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2808 .loc 1 1073 45 view .LVU1025 + 2809 001c E66D ldr r6, [r4, #92] +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2810 .loc 1 1073 7 view .LVU1026 + 2811 001e B142 cmp r1, r6 + 2812 0020 2DD8 bhi .L186 +1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2813 .loc 1 1079 5 is_stmt 1 view .LVU1027 +1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2814 .loc 1 1079 16 is_stmt 0 view .LVU1028 + 2815 0022 0321 movs r1, #3 + 2816 0024 84F83410 strb r1, [r4, #52] +1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2817 .loc 1 1082 5 is_stmt 1 view .LVU1029 +1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2818 .loc 1 1082 8 is_stmt 0 view .LVU1030 + 2819 0028 2168 ldr r1, [r4] +1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2820 .loc 1 1082 26 view .LVU1031 + 2821 002a 0026 movs r6, #0 + 2822 002c CE62 str r6, [r1, #44] +1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; + 2823 .loc 1 1084 5 is_stmt 1 view .LVU1032 +1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; + 2824 .loc 1 1084 21 is_stmt 0 view .LVU1033 + 2825 002e 2062 str r0, [r4, #32] +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2826 .loc 1 1085 5 is_stmt 1 view .LVU1034 +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2827 .loc 1 1085 33 is_stmt 0 view .LVU1035 + 2828 0030 5E02 lsls r6, r3, #9 +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2829 .loc 1 1085 21 view .LVU1036 + 2830 0032 6662 str r6, [r4, #36] +1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2831 .loc 1 1088 5 is_stmt 1 view .LVU1037 + 2832 0034 2068 ldr r0, [r4] + 2833 .LVL239: +1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2834 .loc 1 1088 5 is_stmt 0 view .LVU1038 + 2835 0036 C76B ldr r7, [r0, #60] + 2836 0038 44F21A11 movw r1, #16666 + 2837 003c 3943 orrs r1, r1, r7 + 2838 003e C163 str r1, [r0, #60] + 2839 .LVL240: +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2840 .loc 1 1090 5 is_stmt 1 view .LVU1039 +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2841 .loc 1 1090 19 is_stmt 0 view .LVU1040 + 2842 0040 616C ldr r1, [r4, #68] +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2843 .loc 1 1090 7 view .LVU1041 + 2844 0042 0129 cmp r1, #1 + ARM GAS /tmp/ccMMu31U.s page 124 + + + 2845 0044 00D0 beq .L179 +1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2846 .loc 1 1092 7 is_stmt 1 view .LVU1042 +1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2847 .loc 1 1092 11 is_stmt 0 view .LVU1043 + 2848 0046 5202 lsls r2, r2, #9 + 2849 .LVL241: + 2850 .L179: +1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2851 .loc 1 1096 5 is_stmt 1 view .LVU1044 +1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2852 .loc 1 1096 7 is_stmt 0 view .LVU1045 + 2853 0048 012B cmp r3, #1 + 2854 004a 1DD9 bls .L180 +1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2855 .loc 1 1098 7 is_stmt 1 view .LVU1046 +1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2856 .loc 1 1098 20 is_stmt 0 view .LVU1047 + 2857 004c 2823 movs r3, #40 + 2858 .LVL242: +1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2859 .loc 1 1098 20 view .LVU1048 + 2860 004e 2363 str r3, [r4, #48] +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2861 .loc 1 1101 7 is_stmt 1 view .LVU1049 +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2862 .loc 1 1101 20 is_stmt 0 view .LVU1050 + 2863 0050 1146 mov r1, r2 + 2864 0052 2068 ldr r0, [r4] + 2865 0054 FFF7FEFF bl SDMMC_CmdWriteMultiBlock + 2866 .LVL243: + 2867 .L181: +1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2868 .loc 1 1110 5 is_stmt 1 view .LVU1051 +1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 2869 .loc 1 1110 7 is_stmt 0 view .LVU1052 + 2870 0058 E8B1 cbz r0, .L182 +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 2871 .loc 1 1113 7 is_stmt 1 view .LVU1053 + 2872 005a 2368 ldr r3, [r4] + 2873 005c 184A ldr r2, .L187 + 2874 005e 9A63 str r2, [r3, #56] +1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2875 .loc 1 1114 7 view .LVU1054 +1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2876 .loc 1 1114 10 is_stmt 0 view .LVU1055 + 2877 0060 A36B ldr r3, [r4, #56] +1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 2878 .loc 1 1114 22 view .LVU1056 + 2879 0062 0343 orrs r3, r3, r0 + 2880 0064 A363 str r3, [r4, #56] +1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 2881 .loc 1 1115 7 is_stmt 1 view .LVU1057 +1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 2882 .loc 1 1115 18 is_stmt 0 view .LVU1058 + 2883 0066 0123 movs r3, #1 + 2884 0068 84F83430 strb r3, [r4, #52] + ARM GAS /tmp/ccMMu31U.s page 125 + + +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2885 .loc 1 1116 7 is_stmt 1 view .LVU1059 +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2886 .loc 1 1116 20 is_stmt 0 view .LVU1060 + 2887 006c 0023 movs r3, #0 + 2888 006e 2363 str r3, [r4, #48] +1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2889 .loc 1 1117 7 is_stmt 1 view .LVU1061 +1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2890 .loc 1 1117 14 is_stmt 0 view .LVU1062 + 2891 0070 22E0 b .L177 + 2892 .LVL244: + 2893 .L185: +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2894 .loc 1 1065 5 is_stmt 1 view .LVU1063 +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2895 .loc 1 1065 8 is_stmt 0 view .LVU1064 + 2896 0072 836B ldr r3, [r0, #56] + 2897 .LVL245: +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2898 .loc 1 1065 20 view .LVU1065 + 2899 0074 43F00063 orr r3, r3, #134217728 + 2900 0078 8363 str r3, [r0, #56] +1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2901 .loc 1 1066 5 is_stmt 1 view .LVU1066 +1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2902 .loc 1 1066 12 is_stmt 0 view .LVU1067 + 2903 007a 0125 movs r5, #1 + 2904 007c 1CE0 b .L177 + 2905 .LVL246: + 2906 .L186: +1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2907 .loc 1 1075 7 is_stmt 1 view .LVU1068 +1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2908 .loc 1 1075 10 is_stmt 0 view .LVU1069 + 2909 007e A36B ldr r3, [r4, #56] + 2910 .LVL247: +1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 2911 .loc 1 1075 22 view .LVU1070 + 2912 0080 43F00073 orr r3, r3, #33554432 + 2913 0084 A363 str r3, [r4, #56] +1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2914 .loc 1 1076 7 is_stmt 1 view .LVU1071 +1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2915 .loc 1 1076 14 is_stmt 0 view .LVU1072 + 2916 0086 17E0 b .L177 + 2917 .LVL248: + 2918 .L180: +1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2919 .loc 1 1105 7 is_stmt 1 view .LVU1073 +1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2920 .loc 1 1105 20 is_stmt 0 view .LVU1074 + 2921 0088 1823 movs r3, #24 + 2922 .LVL249: +1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2923 .loc 1 1105 20 view .LVU1075 + 2924 008a 2363 str r3, [r4, #48] + ARM GAS /tmp/ccMMu31U.s page 126 + + +1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2925 .loc 1 1108 7 is_stmt 1 view .LVU1076 +1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2926 .loc 1 1108 20 is_stmt 0 view .LVU1077 + 2927 008c 1146 mov r1, r2 + 2928 008e 2068 ldr r0, [r4] + 2929 0090 FFF7FEFF bl SDMMC_CmdWriteSingleBlock + 2930 .LVL250: +1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2931 .loc 1 1108 20 view .LVU1078 + 2932 0094 E0E7 b .L181 + 2933 .L182: +1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = BLOCKSIZE * NumberOfBlocks; + 2934 .loc 1 1121 5 is_stmt 1 view .LVU1079 +1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = BLOCKSIZE * NumberOfBlocks; + 2935 .loc 1 1121 26 is_stmt 0 view .LVU1080 + 2936 0096 4FF0FF33 mov r3, #-1 + 2937 009a 0093 str r3, [sp] +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + 2938 .loc 1 1122 5 is_stmt 1 view .LVU1081 +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + 2939 .loc 1 1122 26 is_stmt 0 view .LVU1082 + 2940 009c 0196 str r6, [sp, #4] +1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + 2941 .loc 1 1123 5 is_stmt 1 view .LVU1083 +1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + 2942 .loc 1 1123 26 is_stmt 0 view .LVU1084 + 2943 009e 9023 movs r3, #144 + 2944 00a0 0293 str r3, [sp, #8] +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + 2945 .loc 1 1124 5 is_stmt 1 view .LVU1085 +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + 2946 .loc 1 1124 26 is_stmt 0 view .LVU1086 + 2947 00a2 0025 movs r5, #0 + 2948 00a4 0395 str r5, [sp, #12] +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; + 2949 .loc 1 1125 5 is_stmt 1 view .LVU1087 +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; + 2950 .loc 1 1125 26 is_stmt 0 view .LVU1088 + 2951 00a6 0495 str r5, [sp, #16] +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); + 2952 .loc 1 1126 5 is_stmt 1 view .LVU1089 +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); + 2953 .loc 1 1126 26 is_stmt 0 view .LVU1090 + 2954 00a8 0123 movs r3, #1 + 2955 00aa 0593 str r3, [sp, #20] +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2956 .loc 1 1127 5 is_stmt 1 view .LVU1091 +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2957 .loc 1 1127 11 is_stmt 0 view .LVU1092 + 2958 00ac 6946 mov r1, sp + 2959 00ae 2068 ldr r0, [r4] + 2960 .LVL251: +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2961 .loc 1 1127 11 view .LVU1093 + 2962 00b0 FFF7FEFF bl SDMMC_ConfigData + 2963 .LVL252: + ARM GAS /tmp/ccMMu31U.s page 127 + + +1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2964 .loc 1 1129 5 is_stmt 1 view .LVU1094 +1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2965 .loc 1 1129 12 is_stmt 0 view .LVU1095 + 2966 00b4 00E0 b .L177 + 2967 .LVL253: + 2968 .L183: +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 2969 .loc 1 1133 12 view .LVU1096 + 2970 00b6 0225 movs r5, #2 + 2971 .LVL254: + 2972 .L177: +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2973 .loc 1 1135 1 view .LVU1097 + 2974 00b8 2846 mov r0, r5 + 2975 00ba 07B0 add sp, sp, #28 + 2976 .LCFI41: + 2977 .cfi_def_cfa_offset 20 + 2978 @ sp needed + 2979 00bc F0BD pop {r4, r5, r6, r7, pc} + 2980 .LVL255: + 2981 .L188: +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 2982 .loc 1 1135 1 view .LVU1098 + 2983 00be 00BF .align 2 + 2984 .L187: + 2985 00c0 FF054000 .word 4195839 + 2986 .cfi_endproc + 2987 .LFE149: + 2989 .section .text.HAL_SD_ReadBlocks_DMA,"ax",%progbits + 2990 .align 1 + 2991 .global HAL_SD_ReadBlocks_DMA + 2992 .syntax unified + 2993 .thumb + 2994 .thumb_func + 2996 HAL_SD_ReadBlocks_DMA: + 2997 .LVL256: + 2998 .LFB150: +1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; + 2999 .loc 1 1151 1 is_stmt 1 view -0 + 3000 .cfi_startproc + 3001 @ args = 0, pretend = 0, frame = 24 + 3002 @ frame_needed = 0, uses_anonymous_args = 0 +1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; + 3003 .loc 1 1151 1 is_stmt 0 view .LVU1100 + 3004 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 3005 .LCFI42: + 3006 .cfi_def_cfa_offset 28 + 3007 .cfi_offset 4, -28 + 3008 .cfi_offset 5, -24 + 3009 .cfi_offset 6, -20 + 3010 .cfi_offset 7, -16 + 3011 .cfi_offset 8, -12 + 3012 .cfi_offset 9, -8 + 3013 .cfi_offset 14, -4 + 3014 0004 87B0 sub sp, sp, #28 + 3015 .LCFI43: + ARM GAS /tmp/ccMMu31U.s page 128 + + + 3016 .cfi_def_cfa_offset 56 + 3017 0006 0446 mov r4, r0 +1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 3018 .loc 1 1152 3 is_stmt 1 view .LVU1101 +1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t add = BlockAdd; + 3019 .loc 1 1153 3 view .LVU1102 +1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3020 .loc 1 1154 3 view .LVU1103 + 3021 .LVL257: +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3022 .loc 1 1156 3 view .LVU1104 +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3023 .loc 1 1156 5 is_stmt 0 view .LVU1105 + 3024 0008 91B1 cbz r1, .L200 + 3025 000a 1646 mov r6, r2 + 3026 000c 1F46 mov r7, r3 + 3027 000e 0A46 mov r2, r1 + 3028 .LVL258: +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3029 .loc 1 1162 3 is_stmt 1 view .LVU1106 +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3030 .loc 1 1162 9 is_stmt 0 view .LVU1107 + 3031 0010 90F83450 ldrb r5, [r0, #52] @ zero_extendqisi2 + 3032 0014 EDB2 uxtb r5, r5 +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3033 .loc 1 1162 5 view .LVU1108 + 3034 0016 012D cmp r5, #1 + 3035 0018 7FD1 bne .L197 +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3036 .loc 1 1164 5 is_stmt 1 view .LVU1109 +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3037 .loc 1 1164 20 is_stmt 0 view .LVU1110 + 3038 001a 0023 movs r3, #0 + 3039 .LVL259: +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3040 .loc 1 1164 20 view .LVU1111 + 3041 001c 8363 str r3, [r0, #56] +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3042 .loc 1 1166 5 is_stmt 1 view .LVU1112 +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3043 .loc 1 1166 13 is_stmt 0 view .LVU1113 + 3044 001e F019 adds r0, r6, r7 + 3045 .LVL260: +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3046 .loc 1 1166 45 view .LVU1114 + 3047 0020 E36D ldr r3, [r4, #92] +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3048 .loc 1 1166 7 view .LVU1115 + 3049 0022 9842 cmp r0, r3 + 3050 0024 0AD9 bls .L192 +1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3051 .loc 1 1168 7 is_stmt 1 view .LVU1116 +1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3052 .loc 1 1168 10 is_stmt 0 view .LVU1117 + 3053 0026 A36B ldr r3, [r4, #56] +1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3054 .loc 1 1168 22 view .LVU1118 + ARM GAS /tmp/ccMMu31U.s page 129 + + + 3055 0028 43F00073 orr r3, r3, #33554432 + 3056 002c A363 str r3, [r4, #56] +1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3057 .loc 1 1169 7 is_stmt 1 view .LVU1119 +1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3058 .loc 1 1169 14 is_stmt 0 view .LVU1120 + 3059 002e 75E0 b .L191 + 3060 .LVL261: + 3061 .L200: +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3062 .loc 1 1158 5 is_stmt 1 view .LVU1121 +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3063 .loc 1 1158 8 is_stmt 0 view .LVU1122 + 3064 0030 836B ldr r3, [r0, #56] + 3065 .LVL262: +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3066 .loc 1 1158 20 view .LVU1123 + 3067 0032 43F00063 orr r3, r3, #134217728 + 3068 0036 8363 str r3, [r0, #56] +1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3069 .loc 1 1159 5 is_stmt 1 view .LVU1124 +1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3070 .loc 1 1159 12 is_stmt 0 view .LVU1125 + 3071 0038 0125 movs r5, #1 + 3072 003a 6FE0 b .L191 + 3073 .LVL263: + 3074 .L192: +1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3075 .loc 1 1172 5 is_stmt 1 view .LVU1126 +1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3076 .loc 1 1172 16 is_stmt 0 view .LVU1127 + 3077 003c 0323 movs r3, #3 + 3078 003e 84F83430 strb r3, [r4, #52] +1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3079 .loc 1 1175 5 is_stmt 1 view .LVU1128 +1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3080 .loc 1 1175 8 is_stmt 0 view .LVU1129 + 3081 0042 2168 ldr r1, [r4] + 3082 .LVL264: +1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3083 .loc 1 1175 26 view .LVU1130 + 3084 0044 0023 movs r3, #0 + 3085 0046 CB62 str r3, [r1, #44] +1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3086 .loc 1 1177 5 is_stmt 1 view .LVU1131 + 3087 0048 2068 ldr r0, [r4] + 3088 004a C16B ldr r1, [r0, #60] + 3089 004c 41F49571 orr r1, r1, #298 + 3090 0050 C163 str r1, [r0, #60] +1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3091 .loc 1 1180 5 view .LVU1132 +1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3092 .loc 1 1180 8 is_stmt 0 view .LVU1133 + 3093 0052 216C ldr r1, [r4, #64] +1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3094 .loc 1 1180 35 view .LVU1134 + 3095 0054 3448 ldr r0, .L202 + ARM GAS /tmp/ccMMu31U.s page 130 + + + 3096 0056 C863 str r0, [r1, #60] +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3097 .loc 1 1183 5 is_stmt 1 view .LVU1135 +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3098 .loc 1 1183 8 is_stmt 0 view .LVU1136 + 3099 0058 216C ldr r1, [r4, #64] +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3100 .loc 1 1183 36 view .LVU1137 + 3101 005a 3448 ldr r0, .L202+4 + 3102 005c C864 str r0, [r1, #76] +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3103 .loc 1 1186 5 is_stmt 1 view .LVU1138 +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3104 .loc 1 1186 8 is_stmt 0 view .LVU1139 + 3105 005e 216C ldr r1, [r4, #64] +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3106 .loc 1 1186 36 view .LVU1140 + 3107 0060 0B65 str r3, [r1, #80] +1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** MODIFY_REG(hsd->hdmarx->Instance->CR, DMA_SxCR_DIR, hsd->hdmarx->Init.Direction); + 3108 .loc 1 1189 5 is_stmt 1 view .LVU1141 +1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** MODIFY_REG(hsd->hdmarx->Instance->CR, DMA_SxCR_DIR, hsd->hdmarx->Init.Direction); + 3109 .loc 1 1189 8 is_stmt 0 view .LVU1142 + 3110 0062 216C ldr r1, [r4, #64] +1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** MODIFY_REG(hsd->hdmarx->Instance->CR, DMA_SxCR_DIR, hsd->hdmarx->Init.Direction); + 3111 .loc 1 1189 33 view .LVU1143 + 3112 0064 8B60 str r3, [r1, #8] +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3113 .loc 1 1190 5 is_stmt 1 view .LVU1144 + 3114 0066 206C ldr r0, [r4, #64] + 3115 0068 0168 ldr r1, [r0] + 3116 006a 0B68 ldr r3, [r1] + 3117 006c 23F0C003 bic r3, r3, #192 + 3118 0070 8068 ldr r0, [r0, #8] + 3119 0072 0343 orrs r3, r3, r0 + 3120 0074 0B60 str r3, [r1] +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3121 .loc 1 1193 5 view .LVU1145 +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3122 .loc 1 1193 52 is_stmt 0 view .LVU1146 + 3123 0076 2168 ldr r1, [r4] +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3124 .loc 1 1193 87 view .LVU1147 + 3125 0078 4FEA4729 lsl r9, r7, #9 +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3126 .loc 1 1193 8 view .LVU1148 + 3127 007c 4FEA9903 lsr r3, r9, #2 + 3128 0080 8031 adds r1, r1, #128 + 3129 0082 206C ldr r0, [r4, #64] + 3130 0084 FFF7FEFF bl HAL_DMA_Start_IT + 3131 .LVL265: +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3132 .loc 1 1193 7 discriminator 1 view .LVU1149 + 3133 0088 8046 mov r8, r0 + 3134 008a 0028 cmp r0, #0 + 3135 008c 2ED1 bne .L201 +1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3136 .loc 1 1204 7 is_stmt 1 view .LVU1150 + ARM GAS /tmp/ccMMu31U.s page 131 + + + 3137 008e 2268 ldr r2, [r4] + 3138 0090 D36A ldr r3, [r2, #44] + 3139 0092 43F00803 orr r3, r3, #8 + 3140 0096 D362 str r3, [r2, #44] +1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3141 .loc 1 1206 7 view .LVU1151 +1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3142 .loc 1 1206 21 is_stmt 0 view .LVU1152 + 3143 0098 636C ldr r3, [r4, #68] +1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3144 .loc 1 1206 9 view .LVU1153 + 3145 009a 012B cmp r3, #1 + 3146 009c 00D0 beq .L194 +1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3147 .loc 1 1208 9 is_stmt 1 view .LVU1154 +1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3148 .loc 1 1208 13 is_stmt 0 view .LVU1155 + 3149 009e 7602 lsls r6, r6, #9 + 3150 .LVL266: + 3151 .L194: +1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = BLOCKSIZE * NumberOfBlocks; + 3152 .loc 1 1212 7 is_stmt 1 view .LVU1156 +1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = BLOCKSIZE * NumberOfBlocks; + 3153 .loc 1 1212 28 is_stmt 0 view .LVU1157 + 3154 00a0 4FF0FF33 mov r3, #-1 + 3155 00a4 0093 str r3, [sp] +1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + 3156 .loc 1 1213 7 is_stmt 1 view .LVU1158 +1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + 3157 .loc 1 1213 28 is_stmt 0 view .LVU1159 + 3158 00a6 CDF80490 str r9, [sp, #4] +1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + 3159 .loc 1 1214 7 is_stmt 1 view .LVU1160 +1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + 3160 .loc 1 1214 28 is_stmt 0 view .LVU1161 + 3161 00aa 9023 movs r3, #144 + 3162 00ac 0293 str r3, [sp, #8] +1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + 3163 .loc 1 1215 7 is_stmt 1 view .LVU1162 +1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + 3164 .loc 1 1215 28 is_stmt 0 view .LVU1163 + 3165 00ae 0223 movs r3, #2 + 3166 00b0 0393 str r3, [sp, #12] +1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; + 3167 .loc 1 1216 7 is_stmt 1 view .LVU1164 +1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; + 3168 .loc 1 1216 28 is_stmt 0 view .LVU1165 + 3169 00b2 0023 movs r3, #0 + 3170 00b4 0493 str r3, [sp, #16] +1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); + 3171 .loc 1 1217 7 is_stmt 1 view .LVU1166 +1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); + 3172 .loc 1 1217 28 is_stmt 0 view .LVU1167 + 3173 00b6 0123 movs r3, #1 + 3174 00b8 0593 str r3, [sp, #20] +1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3175 .loc 1 1218 7 is_stmt 1 view .LVU1168 + ARM GAS /tmp/ccMMu31U.s page 132 + + +1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3176 .loc 1 1218 13 is_stmt 0 view .LVU1169 + 3177 00ba 6946 mov r1, sp + 3178 00bc 2068 ldr r0, [r4] + 3179 00be FFF7FEFF bl SDMMC_ConfigData + 3180 .LVL267: +1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3181 .loc 1 1221 7 is_stmt 1 view .LVU1170 +1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3182 .loc 1 1221 9 is_stmt 0 view .LVU1171 + 3183 00c2 012F cmp r7, #1 + 3184 00c4 22D9 bls .L195 +1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3185 .loc 1 1223 9 is_stmt 1 view .LVU1172 +1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3186 .loc 1 1223 22 is_stmt 0 view .LVU1173 + 3187 00c6 8223 movs r3, #130 + 3188 00c8 2363 str r3, [r4, #48] +1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3189 .loc 1 1226 9 is_stmt 1 view .LVU1174 +1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3190 .loc 1 1226 22 is_stmt 0 view .LVU1175 + 3191 00ca 3146 mov r1, r6 + 3192 00cc 2068 ldr r0, [r4] + 3193 00ce FFF7FEFF bl SDMMC_CmdReadMultiBlock + 3194 .LVL268: + 3195 .L196: +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3196 .loc 1 1235 7 is_stmt 1 view .LVU1176 +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3197 .loc 1 1235 9 is_stmt 0 view .LVU1177 + 3198 00d2 38B3 cbz r0, .L198 +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 3199 .loc 1 1238 9 is_stmt 1 view .LVU1178 + 3200 00d4 2368 ldr r3, [r4] + 3201 00d6 164A ldr r2, .L202+8 + 3202 00d8 9A63 str r2, [r3, #56] +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3203 .loc 1 1239 9 view .LVU1179 +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3204 .loc 1 1239 12 is_stmt 0 view .LVU1180 + 3205 00da A36B ldr r3, [r4, #56] +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3206 .loc 1 1239 24 view .LVU1181 + 3207 00dc 0343 orrs r3, r3, r0 + 3208 00de A363 str r3, [r4, #56] +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 3209 .loc 1 1240 9 is_stmt 1 view .LVU1182 +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 3210 .loc 1 1240 20 is_stmt 0 view .LVU1183 + 3211 00e0 0123 movs r3, #1 + 3212 00e2 84F83430 strb r3, [r4, #52] +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3213 .loc 1 1241 9 is_stmt 1 view .LVU1184 +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3214 .loc 1 1241 22 is_stmt 0 view .LVU1185 + 3215 00e6 0023 movs r3, #0 + ARM GAS /tmp/ccMMu31U.s page 133 + + + 3216 00e8 2363 str r3, [r4, #48] +1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3217 .loc 1 1242 9 is_stmt 1 view .LVU1186 +1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3218 .loc 1 1242 16 is_stmt 0 view .LVU1187 + 3219 00ea 17E0 b .L191 + 3220 .LVL269: + 3221 .L201: +1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + 3222 .loc 1 1195 7 is_stmt 1 view .LVU1188 + 3223 00ec 2268 ldr r2, [r4] + 3224 00ee D36B ldr r3, [r2, #60] + 3225 00f0 23F49573 bic r3, r3, #298 + 3226 00f4 D363 str r3, [r2, #60] +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_DMA; + 3227 .loc 1 1196 7 view .LVU1189 + 3228 00f6 2368 ldr r3, [r4] + 3229 00f8 0D4A ldr r2, .L202+8 + 3230 00fa 9A63 str r2, [r3, #56] +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3231 .loc 1 1197 7 view .LVU1190 +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3232 .loc 1 1197 10 is_stmt 0 view .LVU1191 + 3233 00fc A36B ldr r3, [r4, #56] +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3234 .loc 1 1197 22 view .LVU1192 + 3235 00fe 43F08043 orr r3, r3, #1073741824 + 3236 0102 A363 str r3, [r4, #56] +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3237 .loc 1 1198 7 is_stmt 1 view .LVU1193 +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3238 .loc 1 1198 18 is_stmt 0 view .LVU1194 + 3239 0104 0123 movs r3, #1 + 3240 0106 84F83430 strb r3, [r4, #52] +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3241 .loc 1 1199 7 is_stmt 1 view .LVU1195 +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3242 .loc 1 1199 14 is_stmt 0 view .LVU1196 + 3243 010a 07E0 b .L191 + 3244 .LVL270: + 3245 .L195: +1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3246 .loc 1 1230 9 is_stmt 1 view .LVU1197 +1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3247 .loc 1 1230 22 is_stmt 0 view .LVU1198 + 3248 010c 8123 movs r3, #129 + 3249 010e 2363 str r3, [r4, #48] +1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3250 .loc 1 1233 9 is_stmt 1 view .LVU1199 +1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3251 .loc 1 1233 22 is_stmt 0 view .LVU1200 + 3252 0110 3146 mov r1, r6 + 3253 0112 2068 ldr r0, [r4] + 3254 0114 FFF7FEFF bl SDMMC_CmdReadSingleBlock + 3255 .LVL271: +1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3256 .loc 1 1233 22 view .LVU1201 + ARM GAS /tmp/ccMMu31U.s page 134 + + + 3257 0118 DBE7 b .L196 + 3258 .LVL272: + 3259 .L197: +1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3260 .loc 1 1250 12 view .LVU1202 + 3261 011a 0225 movs r5, #2 + 3262 .LVL273: + 3263 .L191: +1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3264 .loc 1 1252 1 view .LVU1203 + 3265 011c 2846 mov r0, r5 + 3266 011e 07B0 add sp, sp, #28 + 3267 .LCFI44: + 3268 .cfi_remember_state + 3269 .cfi_def_cfa_offset 28 + 3270 @ sp needed + 3271 0120 BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} + 3272 .LVL274: + 3273 .L198: + 3274 .LCFI45: + 3275 .cfi_restore_state +1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3276 .loc 1 1245 14 view .LVU1204 + 3277 0124 4546 mov r5, r8 + 3278 0126 F9E7 b .L191 + 3279 .L203: + 3280 .align 2 + 3281 .L202: + 3282 0128 00000000 .word SD_DMAReceiveCplt + 3283 012c 00000000 .word SD_DMAError + 3284 0130 FF054000 .word 4195839 + 3285 .cfi_endproc + 3286 .LFE150: + 3288 .section .text.HAL_SD_WriteBlocks_DMA,"ax",%progbits + 3289 .align 1 + 3290 .global HAL_SD_WriteBlocks_DMA + 3291 .syntax unified + 3292 .thumb + 3293 .thumb_func + 3295 HAL_SD_WriteBlocks_DMA: + 3296 .LVL275: + 3297 .LFB151: +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; + 3298 .loc 1 1268 1 is_stmt 1 view -0 + 3299 .cfi_startproc + 3300 @ args = 0, pretend = 0, frame = 24 + 3301 @ frame_needed = 0, uses_anonymous_args = 0 +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_DataInitTypeDef config; + 3302 .loc 1 1268 1 is_stmt 0 view .LVU1206 + 3303 0000 F0B5 push {r4, r5, r6, r7, lr} + 3304 .LCFI46: + 3305 .cfi_def_cfa_offset 20 + 3306 .cfi_offset 4, -20 + 3307 .cfi_offset 5, -16 + 3308 .cfi_offset 6, -12 + 3309 .cfi_offset 7, -8 + 3310 .cfi_offset 14, -4 + ARM GAS /tmp/ccMMu31U.s page 135 + + + 3311 0002 87B0 sub sp, sp, #28 + 3312 .LCFI47: + 3313 .cfi_def_cfa_offset 48 + 3314 0004 0446 mov r4, r0 +1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 3315 .loc 1 1269 3 is_stmt 1 view .LVU1207 +1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t add = BlockAdd; + 3316 .loc 1 1270 3 view .LVU1208 +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3317 .loc 1 1271 3 view .LVU1209 + 3318 .LVL276: +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3319 .loc 1 1273 3 view .LVU1210 +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3320 .loc 1 1273 5 is_stmt 0 view .LVU1211 + 3321 0006 0029 cmp r1, #0 + 3322 0008 39D0 beq .L215 + 3323 000a 1E46 mov r6, r3 + 3324 000c 0F46 mov r7, r1 +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3325 .loc 1 1279 3 is_stmt 1 view .LVU1212 +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3326 .loc 1 1279 9 is_stmt 0 view .LVU1213 + 3327 000e 90F83450 ldrb r5, [r0, #52] @ zero_extendqisi2 + 3328 0012 EDB2 uxtb r5, r5 +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3329 .loc 1 1279 5 view .LVU1214 + 3330 0014 012D cmp r5, #1 + 3331 0016 40F08180 bne .L213 +1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3332 .loc 1 1281 5 is_stmt 1 view .LVU1215 +1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3333 .loc 1 1281 20 is_stmt 0 view .LVU1216 + 3334 001a 0023 movs r3, #0 + 3335 .LVL277: +1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3336 .loc 1 1281 20 view .LVU1217 + 3337 001c 8363 str r3, [r0, #56] +1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3338 .loc 1 1283 5 is_stmt 1 view .LVU1218 +1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3339 .loc 1 1283 13 is_stmt 0 view .LVU1219 + 3340 001e 9319 adds r3, r2, r6 +1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3341 .loc 1 1283 45 view .LVU1220 + 3342 0020 C16D ldr r1, [r0, #92] + 3343 .LVL278: +1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3344 .loc 1 1283 7 view .LVU1221 + 3345 0022 8B42 cmp r3, r1 + 3346 0024 31D8 bhi .L216 +1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3347 .loc 1 1289 5 is_stmt 1 view .LVU1222 +1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3348 .loc 1 1289 16 is_stmt 0 view .LVU1223 + 3349 0026 0323 movs r3, #3 + 3350 0028 80F83430 strb r3, [r0, #52] + ARM GAS /tmp/ccMMu31U.s page 136 + + +1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3351 .loc 1 1292 5 is_stmt 1 view .LVU1224 +1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3352 .loc 1 1292 8 is_stmt 0 view .LVU1225 + 3353 002c 0368 ldr r3, [r0] +1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3354 .loc 1 1292 26 view .LVU1226 + 3355 002e 0021 movs r1, #0 + 3356 0030 D962 str r1, [r3, #44] +1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3357 .loc 1 1295 5 is_stmt 1 view .LVU1227 + 3358 0032 0068 ldr r0, [r0] + 3359 .LVL279: +1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3360 .loc 1 1295 5 is_stmt 0 view .LVU1228 + 3361 0034 C36B ldr r3, [r0, #60] + 3362 0036 43F01A03 orr r3, r3, #26 + 3363 003a C363 str r3, [r0, #60] +1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3364 .loc 1 1298 5 is_stmt 1 view .LVU1229 +1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3365 .loc 1 1298 8 is_stmt 0 view .LVU1230 + 3366 003c E36B ldr r3, [r4, #60] +1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3367 .loc 1 1298 35 view .LVU1231 + 3368 003e 3948 ldr r0, .L217 + 3369 0040 D863 str r0, [r3, #60] +1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3370 .loc 1 1301 5 is_stmt 1 view .LVU1232 +1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3371 .loc 1 1301 8 is_stmt 0 view .LVU1233 + 3372 0042 E36B ldr r3, [r4, #60] +1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3373 .loc 1 1301 36 view .LVU1234 + 3374 0044 3848 ldr r0, .L217+4 + 3375 0046 D864 str r0, [r3, #76] +1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3376 .loc 1 1304 5 is_stmt 1 view .LVU1235 +1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3377 .loc 1 1304 8 is_stmt 0 view .LVU1236 + 3378 0048 E36B ldr r3, [r4, #60] +1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3379 .loc 1 1304 36 view .LVU1237 + 3380 004a 1965 str r1, [r3, #80] +1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3381 .loc 1 1306 5 is_stmt 1 view .LVU1238 +1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3382 .loc 1 1306 19 is_stmt 0 view .LVU1239 + 3383 004c 636C ldr r3, [r4, #68] +1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3384 .loc 1 1306 7 view .LVU1240 + 3385 004e 012B cmp r3, #1 + 3386 0050 00D0 beq .L208 +1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3387 .loc 1 1308 7 is_stmt 1 view .LVU1241 +1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3388 .loc 1 1308 11 is_stmt 0 view .LVU1242 + ARM GAS /tmp/ccMMu31U.s page 137 + + + 3389 0052 5202 lsls r2, r2, #9 + 3390 .LVL280: + 3391 .L208: +1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3392 .loc 1 1312 5 is_stmt 1 view .LVU1243 +1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3393 .loc 1 1312 7 is_stmt 0 view .LVU1244 + 3394 0054 012E cmp r6, #1 + 3395 0056 1DD9 bls .L209 +1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3396 .loc 1 1314 7 is_stmt 1 view .LVU1245 +1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3397 .loc 1 1314 20 is_stmt 0 view .LVU1246 + 3398 0058 A023 movs r3, #160 + 3399 005a 2363 str r3, [r4, #48] +1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3400 .loc 1 1317 7 is_stmt 1 view .LVU1247 +1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3401 .loc 1 1317 20 is_stmt 0 view .LVU1248 + 3402 005c 1146 mov r1, r2 + 3403 005e 2068 ldr r0, [r4] + 3404 0060 FFF7FEFF bl SDMMC_CmdWriteMultiBlock + 3405 .LVL281: + 3406 .L210: +1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3407 .loc 1 1326 5 is_stmt 1 view .LVU1249 +1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3408 .loc 1 1326 7 is_stmt 0 view .LVU1250 + 3409 0064 E8B1 cbz r0, .L211 +1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 3410 .loc 1 1329 7 is_stmt 1 view .LVU1251 + 3411 0066 2368 ldr r3, [r4] + 3412 0068 304A ldr r2, .L217+8 + 3413 006a 9A63 str r2, [r3, #56] +1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3414 .loc 1 1330 7 view .LVU1252 +1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3415 .loc 1 1330 10 is_stmt 0 view .LVU1253 + 3416 006c A36B ldr r3, [r4, #56] +1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3417 .loc 1 1330 22 view .LVU1254 + 3418 006e 0343 orrs r3, r3, r0 + 3419 0070 A363 str r3, [r4, #56] +1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 3420 .loc 1 1331 7 is_stmt 1 view .LVU1255 +1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 3421 .loc 1 1331 18 is_stmt 0 view .LVU1256 + 3422 0072 0123 movs r3, #1 + 3423 0074 84F83430 strb r3, [r4, #52] +1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3424 .loc 1 1332 7 is_stmt 1 view .LVU1257 +1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3425 .loc 1 1332 20 is_stmt 0 view .LVU1258 + 3426 0078 0023 movs r3, #0 + 3427 007a 2363 str r3, [r4, #48] +1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3428 .loc 1 1333 7 is_stmt 1 view .LVU1259 + ARM GAS /tmp/ccMMu31U.s page 138 + + +1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3429 .loc 1 1333 14 is_stmt 0 view .LVU1260 + 3430 007c 4FE0 b .L206 + 3431 .LVL282: + 3432 .L215: +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3433 .loc 1 1275 5 is_stmt 1 view .LVU1261 +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3434 .loc 1 1275 8 is_stmt 0 view .LVU1262 + 3435 007e 836B ldr r3, [r0, #56] + 3436 .LVL283: +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3437 .loc 1 1275 20 view .LVU1263 + 3438 0080 43F00063 orr r3, r3, #134217728 + 3439 0084 8363 str r3, [r0, #56] +1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3440 .loc 1 1276 5 is_stmt 1 view .LVU1264 +1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3441 .loc 1 1276 12 is_stmt 0 view .LVU1265 + 3442 0086 0125 movs r5, #1 + 3443 0088 49E0 b .L206 + 3444 .LVL284: + 3445 .L216: +1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3446 .loc 1 1285 7 is_stmt 1 view .LVU1266 +1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3447 .loc 1 1285 10 is_stmt 0 view .LVU1267 + 3448 008a 836B ldr r3, [r0, #56] +1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3449 .loc 1 1285 22 view .LVU1268 + 3450 008c 43F00073 orr r3, r3, #33554432 + 3451 0090 8363 str r3, [r0, #56] +1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3452 .loc 1 1286 7 is_stmt 1 view .LVU1269 +1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3453 .loc 1 1286 14 is_stmt 0 view .LVU1270 + 3454 0092 44E0 b .L206 + 3455 .LVL285: + 3456 .L209: +1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3457 .loc 1 1321 7 is_stmt 1 view .LVU1271 +1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3458 .loc 1 1321 20 is_stmt 0 view .LVU1272 + 3459 0094 9023 movs r3, #144 + 3460 0096 2363 str r3, [r4, #48] +1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3461 .loc 1 1324 7 is_stmt 1 view .LVU1273 +1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3462 .loc 1 1324 20 is_stmt 0 view .LVU1274 + 3463 0098 1146 mov r1, r2 + 3464 009a 2068 ldr r0, [r4] + 3465 009c FFF7FEFF bl SDMMC_CmdWriteSingleBlock + 3466 .LVL286: +1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3467 .loc 1 1324 20 view .LVU1275 + 3468 00a0 E0E7 b .L210 + 3469 .L211: + ARM GAS /tmp/ccMMu31U.s page 139 + + +1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3470 .loc 1 1337 5 is_stmt 1 view .LVU1276 + 3471 00a2 2268 ldr r2, [r4] + 3472 00a4 D36A ldr r3, [r2, #44] + 3473 00a6 43F00803 orr r3, r3, #8 + 3474 00aa D362 str r3, [r2, #44] +1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** MODIFY_REG(hsd->hdmatx->Instance->CR, DMA_SxCR_DIR, hsd->hdmatx->Init.Direction); + 3475 .loc 1 1340 5 view .LVU1277 +1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** MODIFY_REG(hsd->hdmatx->Instance->CR, DMA_SxCR_DIR, hsd->hdmatx->Init.Direction); + 3476 .loc 1 1340 8 is_stmt 0 view .LVU1278 + 3477 00ac E36B ldr r3, [r4, #60] +1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** MODIFY_REG(hsd->hdmatx->Instance->CR, DMA_SxCR_DIR, hsd->hdmatx->Init.Direction); + 3478 .loc 1 1340 33 view .LVU1279 + 3479 00ae 4022 movs r2, #64 + 3480 00b0 9A60 str r2, [r3, #8] +1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3481 .loc 1 1341 5 is_stmt 1 view .LVU1280 + 3482 00b2 E16B ldr r1, [r4, #60] + 3483 00b4 0A68 ldr r2, [r1] + 3484 00b6 1368 ldr r3, [r2] + 3485 00b8 23F0C003 bic r3, r3, #192 + 3486 00bc 8968 ldr r1, [r1, #8] + 3487 00be 0B43 orrs r3, r3, r1 + 3488 00c0 1360 str r3, [r2] +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3489 .loc 1 1344 5 view .LVU1281 +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3490 .loc 1 1344 69 is_stmt 0 view .LVU1282 + 3491 00c2 2268 ldr r2, [r4] +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3492 .loc 1 1344 87 view .LVU1283 + 3493 00c4 7602 lsls r6, r6, #9 + 3494 .LVL287: +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3495 .loc 1 1344 8 view .LVU1284 + 3496 00c6 B308 lsrs r3, r6, #2 + 3497 00c8 8032 adds r2, r2, #128 + 3498 00ca 3946 mov r1, r7 + 3499 00cc E06B ldr r0, [r4, #60] + 3500 .LVL288: +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3501 .loc 1 1344 8 view .LVU1285 + 3502 00ce FFF7FEFF bl HAL_DMA_Start_IT + 3503 .LVL289: +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3504 .loc 1 1344 7 discriminator 1 view .LVU1286 + 3505 00d2 0746 mov r7, r0 + 3506 .LVL290: +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3507 .loc 1 1344 7 discriminator 1 view .LVU1287 + 3508 00d4 88B1 cbz r0, .L212 +1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + 3509 .loc 1 1346 7 is_stmt 1 view .LVU1288 + 3510 00d6 2268 ldr r2, [r4] + 3511 00d8 D36B ldr r3, [r2, #60] + 3512 00da 23F01A03 bic r3, r3, #26 + 3513 00de D363 str r3, [r2, #60] + ARM GAS /tmp/ccMMu31U.s page 140 + + +1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_DMA; + 3514 .loc 1 1347 7 view .LVU1289 + 3515 00e0 2368 ldr r3, [r4] + 3516 00e2 124A ldr r2, .L217+8 + 3517 00e4 9A63 str r2, [r3, #56] +1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3518 .loc 1 1348 7 view .LVU1290 +1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3519 .loc 1 1348 10 is_stmt 0 view .LVU1291 + 3520 00e6 A36B ldr r3, [r4, #56] +1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3521 .loc 1 1348 22 view .LVU1292 + 3522 00e8 43F08043 orr r3, r3, #1073741824 + 3523 00ec A363 str r3, [r4, #56] +1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 3524 .loc 1 1349 7 is_stmt 1 view .LVU1293 +1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 3525 .loc 1 1349 18 is_stmt 0 view .LVU1294 + 3526 00ee 0123 movs r3, #1 + 3527 00f0 84F83430 strb r3, [r4, #52] +1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3528 .loc 1 1350 7 is_stmt 1 view .LVU1295 +1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3529 .loc 1 1350 20 is_stmt 0 view .LVU1296 + 3530 00f4 0023 movs r3, #0 + 3531 00f6 2363 str r3, [r4, #48] +1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3532 .loc 1 1351 7 is_stmt 1 view .LVU1297 +1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3533 .loc 1 1351 14 is_stmt 0 view .LVU1298 + 3534 00f8 11E0 b .L206 + 3535 .L212: +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = BLOCKSIZE * NumberOfBlocks; + 3536 .loc 1 1356 7 is_stmt 1 view .LVU1299 +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataLength = BLOCKSIZE * NumberOfBlocks; + 3537 .loc 1 1356 28 is_stmt 0 view .LVU1300 + 3538 00fa 4FF0FF33 mov r3, #-1 + 3539 00fe 0093 str r3, [sp] +1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + 3540 .loc 1 1357 7 is_stmt 1 view .LVU1301 +1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + 3541 .loc 1 1357 28 is_stmt 0 view .LVU1302 + 3542 0100 0196 str r6, [sp, #4] +1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + 3543 .loc 1 1358 7 is_stmt 1 view .LVU1303 +1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + 3544 .loc 1 1358 28 is_stmt 0 view .LVU1304 + 3545 0102 9023 movs r3, #144 + 3546 0104 0293 str r3, [sp, #8] +1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + 3547 .loc 1 1359 7 is_stmt 1 view .LVU1305 +1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + 3548 .loc 1 1359 28 is_stmt 0 view .LVU1306 + 3549 0106 0023 movs r3, #0 + 3550 0108 0393 str r3, [sp, #12] +1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; + 3551 .loc 1 1360 7 is_stmt 1 view .LVU1307 + ARM GAS /tmp/ccMMu31U.s page 141 + + +1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** config.DPSM = SDMMC_DPSM_ENABLE; + 3552 .loc 1 1360 28 is_stmt 0 view .LVU1308 + 3553 010a 0493 str r3, [sp, #16] +1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); + 3554 .loc 1 1361 7 is_stmt 1 view .LVU1309 +1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_ConfigData(hsd->Instance, &config); + 3555 .loc 1 1361 28 is_stmt 0 view .LVU1310 + 3556 010c 0123 movs r3, #1 + 3557 010e 0593 str r3, [sp, #20] +1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3558 .loc 1 1362 7 is_stmt 1 view .LVU1311 +1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3559 .loc 1 1362 13 is_stmt 0 view .LVU1312 + 3560 0110 6946 mov r1, sp + 3561 0112 2068 ldr r0, [r4] + 3562 0114 FFF7FEFF bl SDMMC_ConfigData + 3563 .LVL291: +1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3564 .loc 1 1364 7 is_stmt 1 view .LVU1313 +1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3565 .loc 1 1364 14 is_stmt 0 view .LVU1314 + 3566 0118 3D46 mov r5, r7 + 3567 011a 00E0 b .L206 + 3568 .LVL292: + 3569 .L213: +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3570 .loc 1 1369 12 view .LVU1315 + 3571 011c 0225 movs r5, #2 + 3572 .LVL293: + 3573 .L206: +1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3574 .loc 1 1371 1 view .LVU1316 + 3575 011e 2846 mov r0, r5 + 3576 0120 07B0 add sp, sp, #28 + 3577 .LCFI48: + 3578 .cfi_def_cfa_offset 20 + 3579 @ sp needed + 3580 0122 F0BD pop {r4, r5, r6, r7, pc} + 3581 .LVL294: + 3582 .L218: +1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3583 .loc 1 1371 1 view .LVU1317 + 3584 .align 2 + 3585 .L217: + 3586 0124 00000000 .word SD_DMATransmitCplt + 3587 0128 00000000 .word SD_DMAError + 3588 012c FF054000 .word 4195839 + 3589 .cfi_endproc + 3590 .LFE151: + 3592 .section .text.HAL_SD_Erase,"ax",%progbits + 3593 .align 1 + 3594 .global HAL_SD_Erase + 3595 .syntax unified + 3596 .thumb + 3597 .thumb_func + 3599 HAL_SD_Erase: + 3600 .LVL295: + ARM GAS /tmp/ccMMu31U.s page 142 + + + 3601 .LFB152: +1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 3602 .loc 1 1383 1 is_stmt 1 view -0 + 3603 .cfi_startproc + 3604 @ args = 0, pretend = 0, frame = 0 + 3605 @ frame_needed = 0, uses_anonymous_args = 0 +1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 3606 .loc 1 1383 1 is_stmt 0 view .LVU1319 + 3607 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 3608 .LCFI49: + 3609 .cfi_def_cfa_offset 24 + 3610 .cfi_offset 3, -24 + 3611 .cfi_offset 4, -20 + 3612 .cfi_offset 5, -16 + 3613 .cfi_offset 6, -12 + 3614 .cfi_offset 7, -8 + 3615 .cfi_offset 14, -4 +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t start_add = BlockStartAdd; + 3616 .loc 1 1384 3 is_stmt 1 view .LVU1320 +1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t end_add = BlockEndAdd; + 3617 .loc 1 1385 3 view .LVU1321 + 3618 .LVL296: +1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3619 .loc 1 1386 3 view .LVU1322 +1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3620 .loc 1 1388 3 view .LVU1323 +1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3621 .loc 1 1388 9 is_stmt 0 view .LVU1324 + 3622 0002 90F83450 ldrb r5, [r0, #52] @ zero_extendqisi2 + 3623 0006 EDB2 uxtb r5, r5 +1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3624 .loc 1 1388 5 view .LVU1325 + 3625 0008 012D cmp r5, #1 + 3626 000a 6FD1 bne .L229 + 3627 000c 0446 mov r4, r0 + 3628 000e 0F46 mov r7, r1 + 3629 0010 1646 mov r6, r2 +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3630 .loc 1 1390 5 is_stmt 1 view .LVU1326 +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3631 .loc 1 1390 20 is_stmt 0 view .LVU1327 + 3632 0012 0023 movs r3, #0 + 3633 0014 8363 str r3, [r0, #56] +1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3634 .loc 1 1392 5 is_stmt 1 view .LVU1328 +1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3635 .loc 1 1392 7 is_stmt 0 view .LVU1329 + 3636 0016 9142 cmp r1, r2 + 3637 0018 14D8 bhi .L231 +1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3638 .loc 1 1398 5 is_stmt 1 view .LVU1330 +1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3639 .loc 1 1398 30 is_stmt 0 view .LVU1331 + 3640 001a C36D ldr r3, [r0, #92] +1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3641 .loc 1 1398 7 view .LVU1332 + 3642 001c 9342 cmp r3, r2 + ARM GAS /tmp/ccMMu31U.s page 143 + + + 3643 001e 16D3 bcc .L232 +1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3644 .loc 1 1404 5 is_stmt 1 view .LVU1333 +1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3645 .loc 1 1404 16 is_stmt 0 view .LVU1334 + 3646 0020 0323 movs r3, #3 + 3647 0022 80F83430 strb r3, [r0, #52] +1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3648 .loc 1 1407 5 is_stmt 1 view .LVU1335 +1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3649 .loc 1 1407 21 is_stmt 0 view .LVU1336 + 3650 0026 C36C ldr r3, [r0, #76] +1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3651 .loc 1 1407 7 view .LVU1337 + 3652 0028 13F0200F tst r3, #32 + 3653 002c 14D1 bne .L223 +1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + 3654 .loc 1 1410 7 is_stmt 1 view .LVU1338 + 3655 002e 0368 ldr r3, [r0] + 3656 0030 304A ldr r2, .L235 + 3657 .LVL297: +1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + 3658 .loc 1 1410 7 is_stmt 0 view .LVU1339 + 3659 0032 9A63 str r2, [r3, #56] +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3660 .loc 1 1411 7 is_stmt 1 view .LVU1340 +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3661 .loc 1 1411 10 is_stmt 0 view .LVU1341 + 3662 0034 836B ldr r3, [r0, #56] +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3663 .loc 1 1411 22 view .LVU1342 + 3664 0036 43F08063 orr r3, r3, #67108864 + 3665 003a 8363 str r3, [r0, #56] +1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3666 .loc 1 1412 7 is_stmt 1 view .LVU1343 +1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3667 .loc 1 1412 18 is_stmt 0 view .LVU1344 + 3668 003c 0123 movs r3, #1 + 3669 003e 80F83430 strb r3, [r0, #52] +1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3670 .loc 1 1413 7 is_stmt 1 view .LVU1345 +1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3671 .loc 1 1413 14 is_stmt 0 view .LVU1346 + 3672 0042 54E0 b .L220 + 3673 .LVL298: + 3674 .L231: +1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3675 .loc 1 1394 7 is_stmt 1 view .LVU1347 +1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3676 .loc 1 1394 10 is_stmt 0 view .LVU1348 + 3677 0044 836B ldr r3, [r0, #56] +1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3678 .loc 1 1394 22 view .LVU1349 + 3679 0046 43F00063 orr r3, r3, #134217728 + 3680 004a 8363 str r3, [r0, #56] +1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3681 .loc 1 1395 7 is_stmt 1 view .LVU1350 + ARM GAS /tmp/ccMMu31U.s page 144 + + +1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3682 .loc 1 1395 14 is_stmt 0 view .LVU1351 + 3683 004c 4FE0 b .L220 + 3684 .L232: +1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3685 .loc 1 1400 7 is_stmt 1 view .LVU1352 +1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3686 .loc 1 1400 10 is_stmt 0 view .LVU1353 + 3687 004e 836B ldr r3, [r0, #56] +1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3688 .loc 1 1400 22 view .LVU1354 + 3689 0050 43F00073 orr r3, r3, #33554432 + 3690 0054 8363 str r3, [r0, #56] +1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3691 .loc 1 1401 7 is_stmt 1 view .LVU1355 +1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3692 .loc 1 1401 14 is_stmt 0 view .LVU1356 + 3693 0056 4AE0 b .L220 + 3694 .L223: +1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3695 .loc 1 1416 5 is_stmt 1 view .LVU1357 +1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3696 .loc 1 1416 9 is_stmt 0 view .LVU1358 + 3697 0058 0021 movs r1, #0 + 3698 .LVL299: +1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3699 .loc 1 1416 9 view .LVU1359 + 3700 005a 0068 ldr r0, [r0] + 3701 .LVL300: +1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3702 .loc 1 1416 9 view .LVU1360 + 3703 005c FFF7FEFF bl SDMMC_GetResponse + 3704 .LVL301: +1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3705 .loc 1 1416 7 discriminator 1 view .LVU1361 + 3706 0060 10F0007F tst r0, #33554432 + 3707 0064 15D1 bne .L233 +1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3708 .loc 1 1426 5 is_stmt 1 view .LVU1362 +1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3709 .loc 1 1426 19 is_stmt 0 view .LVU1363 + 3710 0066 636C ldr r3, [r4, #68] +1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3711 .loc 1 1426 7 view .LVU1364 + 3712 0068 012B cmp r3, #1 + 3713 006a 01D0 beq .L225 +1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** end_add *= 512U; + 3714 .loc 1 1428 7 is_stmt 1 view .LVU1365 +1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** end_add *= 512U; + 3715 .loc 1 1428 17 is_stmt 0 view .LVU1366 + 3716 006c 7F02 lsls r7, r7, #9 + 3717 .LVL302: +1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3718 .loc 1 1429 7 is_stmt 1 view .LVU1367 +1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3719 .loc 1 1429 17 is_stmt 0 view .LVU1368 + 3720 006e 7602 lsls r6, r6, #9 + ARM GAS /tmp/ccMMu31U.s page 145 + + + 3721 .LVL303: + 3722 .L225: +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3723 .loc 1 1433 5 is_stmt 1 view .LVU1369 +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3724 .loc 1 1433 7 is_stmt 0 view .LVU1370 + 3725 0070 032B cmp r3, #3 + 3726 0072 1ED0 beq .L226 +1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 3727 .loc 1 1436 7 is_stmt 1 view .LVU1371 +1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 3728 .loc 1 1436 20 is_stmt 0 view .LVU1372 + 3729 0074 3946 mov r1, r7 + 3730 0076 2068 ldr r0, [r4] + 3731 0078 FFF7FEFF bl SDMMC_CmdSDEraseStartAdd + 3732 .LVL304: +1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3733 .loc 1 1437 7 is_stmt 1 view .LVU1373 +1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3734 .loc 1 1437 9 is_stmt 0 view .LVU1374 + 3735 007c A0B1 cbz r0, .L227 +1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 3736 .loc 1 1440 9 is_stmt 1 view .LVU1375 + 3737 007e 2368 ldr r3, [r4] + 3738 0080 1C49 ldr r1, .L235 + 3739 0082 9963 str r1, [r3, #56] +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3740 .loc 1 1441 9 view .LVU1376 +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3741 .loc 1 1441 12 is_stmt 0 view .LVU1377 + 3742 0084 A36B ldr r3, [r4, #56] +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3743 .loc 1 1441 24 view .LVU1378 + 3744 0086 0343 orrs r3, r3, r0 + 3745 0088 A363 str r3, [r4, #56] +1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3746 .loc 1 1442 9 is_stmt 1 view .LVU1379 +1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3747 .loc 1 1442 20 is_stmt 0 view .LVU1380 + 3748 008a 0123 movs r3, #1 + 3749 008c 84F83430 strb r3, [r4, #52] +1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3750 .loc 1 1443 9 is_stmt 1 view .LVU1381 +1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3751 .loc 1 1443 16 is_stmt 0 view .LVU1382 + 3752 0090 2DE0 b .L220 + 3753 .LVL305: + 3754 .L233: +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED; + 3755 .loc 1 1419 7 is_stmt 1 view .LVU1383 + 3756 0092 2368 ldr r3, [r4] + 3757 0094 174A ldr r2, .L235 + 3758 0096 9A63 str r2, [r3, #56] +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3759 .loc 1 1420 7 view .LVU1384 +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3760 .loc 1 1420 10 is_stmt 0 view .LVU1385 + ARM GAS /tmp/ccMMu31U.s page 146 + + + 3761 0098 A36B ldr r3, [r4, #56] +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3762 .loc 1 1420 22 view .LVU1386 + 3763 009a 43F40063 orr r3, r3, #2048 + 3764 009e A363 str r3, [r4, #56] +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3765 .loc 1 1421 7 is_stmt 1 view .LVU1387 +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3766 .loc 1 1421 18 is_stmt 0 view .LVU1388 + 3767 00a0 0123 movs r3, #1 + 3768 00a2 84F83430 strb r3, [r4, #52] +1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3769 .loc 1 1422 7 is_stmt 1 view .LVU1389 +1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3770 .loc 1 1422 14 is_stmt 0 view .LVU1390 + 3771 00a6 22E0 b .L220 + 3772 .LVL306: + 3773 .L227: +1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 3774 .loc 1 1447 7 is_stmt 1 view .LVU1391 +1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 3775 .loc 1 1447 20 is_stmt 0 view .LVU1392 + 3776 00a8 3146 mov r1, r6 + 3777 00aa 2068 ldr r0, [r4] + 3778 .LVL307: +1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 3779 .loc 1 1447 20 view .LVU1393 + 3780 00ac FFF7FEFF bl SDMMC_CmdSDEraseEndAdd + 3781 .LVL308: +1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3782 .loc 1 1448 7 is_stmt 1 view .LVU1394 +1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3783 .loc 1 1448 9 is_stmt 0 view .LVU1395 + 3784 00b0 68B9 cbnz r0, .L234 + 3785 .LVL309: + 3786 .L226: +1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 3787 .loc 1 1459 5 is_stmt 1 view .LVU1396 +1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 3788 .loc 1 1459 18 is_stmt 0 view .LVU1397 + 3789 00b2 2068 ldr r0, [r4] + 3790 00b4 FFF7FEFF bl SDMMC_CmdErase + 3791 .LVL310: +1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3792 .loc 1 1460 5 is_stmt 1 view .LVU1398 +1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3793 .loc 1 1460 7 is_stmt 0 view .LVU1399 + 3794 00b8 98B1 cbz r0, .L228 +1463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 3795 .loc 1 1463 7 is_stmt 1 view .LVU1400 + 3796 00ba 2368 ldr r3, [r4] + 3797 00bc 0D49 ldr r1, .L235 + 3798 00be 9963 str r1, [r3, #56] +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3799 .loc 1 1464 7 view .LVU1401 +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3800 .loc 1 1464 10 is_stmt 0 view .LVU1402 + ARM GAS /tmp/ccMMu31U.s page 147 + + + 3801 00c0 A36B ldr r3, [r4, #56] +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3802 .loc 1 1464 22 view .LVU1403 + 3803 00c2 0343 orrs r3, r3, r0 + 3804 00c4 A363 str r3, [r4, #56] +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3805 .loc 1 1465 7 is_stmt 1 view .LVU1404 +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3806 .loc 1 1465 18 is_stmt 0 view .LVU1405 + 3807 00c6 0123 movs r3, #1 + 3808 00c8 84F83430 strb r3, [r4, #52] +1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3809 .loc 1 1466 7 is_stmt 1 view .LVU1406 +1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3810 .loc 1 1466 14 is_stmt 0 view .LVU1407 + 3811 00cc 0FE0 b .L220 + 3812 .L234: +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 3813 .loc 1 1451 9 is_stmt 1 view .LVU1408 + 3814 00ce 2368 ldr r3, [r4] + 3815 00d0 0849 ldr r1, .L235 + 3816 00d2 9963 str r1, [r3, #56] +1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3817 .loc 1 1452 9 view .LVU1409 +1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3818 .loc 1 1452 12 is_stmt 0 view .LVU1410 + 3819 00d4 A36B ldr r3, [r4, #56] +1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 3820 .loc 1 1452 24 view .LVU1411 + 3821 00d6 0343 orrs r3, r3, r0 + 3822 00d8 A363 str r3, [r4, #56] +1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3823 .loc 1 1453 9 is_stmt 1 view .LVU1412 +1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 3824 .loc 1 1453 20 is_stmt 0 view .LVU1413 + 3825 00da 0123 movs r3, #1 + 3826 00dc 84F83430 strb r3, [r4, #52] +1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3827 .loc 1 1454 9 is_stmt 1 view .LVU1414 +1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3828 .loc 1 1454 16 is_stmt 0 view .LVU1415 + 3829 00e0 05E0 b .L220 + 3830 .L228: +1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3831 .loc 1 1469 5 is_stmt 1 view .LVU1416 +1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3832 .loc 1 1469 16 is_stmt 0 view .LVU1417 + 3833 00e2 0123 movs r3, #1 + 3834 00e4 84F83430 strb r3, [r4, #52] +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3835 .loc 1 1471 5 is_stmt 1 view .LVU1418 +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3836 .loc 1 1471 12 is_stmt 0 view .LVU1419 + 3837 00e8 0025 movs r5, #0 + 3838 00ea 00E0 b .L220 + 3839 .LVL311: + 3840 .L229: + ARM GAS /tmp/ccMMu31U.s page 148 + + +1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3841 .loc 1 1475 12 view .LVU1420 + 3842 00ec 0225 movs r5, #2 + 3843 .LVL312: + 3844 .L220: +1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3845 .loc 1 1477 1 view .LVU1421 + 3846 00ee 2846 mov r0, r5 + 3847 00f0 F8BD pop {r3, r4, r5, r6, r7, pc} + 3848 .L236: + 3849 00f2 00BF .align 2 + 3850 .L235: + 3851 00f4 FF054000 .word 4195839 + 3852 .cfi_endproc + 3853 .LFE152: + 3855 .section .text.HAL_SD_GetState,"ax",%progbits + 3856 .align 1 + 3857 .global HAL_SD_GetState + 3858 .syntax unified + 3859 .thumb + 3860 .thumb_func + 3862 HAL_SD_GetState: + 3863 .LVL313: + 3864 .LFB154: +1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return hsd->State; + 3865 .loc 1 1676 1 is_stmt 1 view -0 + 3866 .cfi_startproc + 3867 @ args = 0, pretend = 0, frame = 0 + 3868 @ frame_needed = 0, uses_anonymous_args = 0 + 3869 @ link register save eliminated. +1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3870 .loc 1 1677 3 view .LVU1423 +1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3871 .loc 1 1677 13 is_stmt 0 view .LVU1424 + 3872 0000 90F83400 ldrb r0, [r0, #52] @ zero_extendqisi2 + 3873 .LVL314: +1678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3874 .loc 1 1678 1 view .LVU1425 + 3875 0004 7047 bx lr + 3876 .cfi_endproc + 3877 .LFE154: + 3879 .section .text.HAL_SD_GetError,"ax",%progbits + 3880 .align 1 + 3881 .global HAL_SD_GetError + 3882 .syntax unified + 3883 .thumb + 3884 .thumb_func + 3886 HAL_SD_GetError: + 3887 .LVL315: + 3888 .LFB155: +1687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return hsd->ErrorCode; + 3889 .loc 1 1687 1 is_stmt 1 view -0 + 3890 .cfi_startproc + 3891 @ args = 0, pretend = 0, frame = 0 + 3892 @ frame_needed = 0, uses_anonymous_args = 0 + 3893 @ link register save eliminated. +1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + ARM GAS /tmp/ccMMu31U.s page 149 + + + 3894 .loc 1 1688 3 view .LVU1427 +1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 3895 .loc 1 1688 13 is_stmt 0 view .LVU1428 + 3896 0000 806B ldr r0, [r0, #56] + 3897 .LVL316: +1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3898 .loc 1 1689 1 view .LVU1429 + 3899 0002 7047 bx lr + 3900 .cfi_endproc + 3901 .LFE155: + 3903 .section .text.HAL_SD_TxCpltCallback,"ax",%progbits + 3904 .align 1 + 3905 .weak HAL_SD_TxCpltCallback + 3906 .syntax unified + 3907 .thumb + 3908 .thumb_func + 3910 HAL_SD_TxCpltCallback: + 3911 .LVL317: + 3912 .LFB156: +1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Prevent unused argument(s) compilation warning */ + 3913 .loc 1 1697 1 is_stmt 1 view -0 + 3914 .cfi_startproc + 3915 @ args = 0, pretend = 0, frame = 0 + 3916 @ frame_needed = 0, uses_anonymous_args = 0 + 3917 @ link register save eliminated. +1699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3918 .loc 1 1699 3 view .LVU1431 +1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3919 .loc 1 1704 1 is_stmt 0 view .LVU1432 + 3920 0000 7047 bx lr + 3921 .cfi_endproc + 3922 .LFE156: + 3924 .section .text.HAL_SD_RxCpltCallback,"ax",%progbits + 3925 .align 1 + 3926 .weak HAL_SD_RxCpltCallback + 3927 .syntax unified + 3928 .thumb + 3929 .thumb_func + 3931 HAL_SD_RxCpltCallback: + 3932 .LVL318: + 3933 .LFB157: +1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Prevent unused argument(s) compilation warning */ + 3934 .loc 1 1712 1 is_stmt 1 view -0 + 3935 .cfi_startproc + 3936 @ args = 0, pretend = 0, frame = 0 + 3937 @ frame_needed = 0, uses_anonymous_args = 0 + 3938 @ link register save eliminated. +1714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3939 .loc 1 1714 3 view .LVU1434 +1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3940 .loc 1 1719 1 is_stmt 0 view .LVU1435 + 3941 0000 7047 bx lr + 3942 .cfi_endproc + 3943 .LFE157: + 3945 .section .text.HAL_SD_ErrorCallback,"ax",%progbits + 3946 .align 1 + 3947 .weak HAL_SD_ErrorCallback + ARM GAS /tmp/ccMMu31U.s page 150 + + + 3948 .syntax unified + 3949 .thumb + 3950 .thumb_func + 3952 HAL_SD_ErrorCallback: + 3953 .LVL319: + 3954 .LFB158: +1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Prevent unused argument(s) compilation warning */ + 3955 .loc 1 1727 1 is_stmt 1 view -0 + 3956 .cfi_startproc + 3957 @ args = 0, pretend = 0, frame = 0 + 3958 @ frame_needed = 0, uses_anonymous_args = 0 + 3959 @ link register save eliminated. +1729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3960 .loc 1 1729 3 view .LVU1437 +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3961 .loc 1 1734 1 is_stmt 0 view .LVU1438 + 3962 0000 7047 bx lr + 3963 .cfi_endproc + 3964 .LFE158: + 3966 .section .text.SD_DMAReceiveCplt,"ax",%progbits + 3967 .align 1 + 3968 .syntax unified + 3969 .thumb + 3970 .thumb_func + 3972 SD_DMAReceiveCplt: + 3973 .LVL320: + 3974 .LFB169: +2454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + 3975 .loc 1 2454 1 is_stmt 1 view -0 + 3976 .cfi_startproc + 3977 @ args = 0, pretend = 0, frame = 0 + 3978 @ frame_needed = 0, uses_anonymous_args = 0 +2454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + 3979 .loc 1 2454 1 is_stmt 0 view .LVU1440 + 3980 0000 10B5 push {r4, lr} + 3981 .LCFI50: + 3982 .cfi_def_cfa_offset 8 + 3983 .cfi_offset 4, -8 + 3984 .cfi_offset 14, -4 +2455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 3985 .loc 1 2455 3 is_stmt 1 view .LVU1441 +2455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 3986 .loc 1 2455 21 is_stmt 0 view .LVU1442 + 3987 0002 846B ldr r4, [r0, #56] + 3988 .LVL321: +2456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3989 .loc 1 2456 3 is_stmt 1 view .LVU1443 +2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3990 .loc 1 2459 3 view .LVU1444 +2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3991 .loc 1 2459 9 is_stmt 0 view .LVU1445 + 3992 0004 236B ldr r3, [r4, #48] +2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 3993 .loc 1 2459 5 view .LVU1446 + 3994 0006 822B cmp r3, #130 + 3995 0008 11D0 beq .L245 + 3996 .LVL322: + ARM GAS /tmp/ccMMu31U.s page 151 + + + 3997 .L243: +2475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3998 .loc 1 2475 3 is_stmt 1 view .LVU1447 +2475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 3999 .loc 1 2475 6 is_stmt 0 view .LVU1448 + 4000 000a 2268 ldr r2, [r4] +2475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4001 .loc 1 2475 16 view .LVU1449 + 4002 000c D36A ldr r3, [r2, #44] +2475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4003 .loc 1 2475 24 view .LVU1450 + 4004 000e 23F00803 bic r3, r3, #8 + 4005 0012 D362 str r3, [r2, #44] +2478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4006 .loc 1 2478 3 is_stmt 1 view .LVU1451 + 4007 0014 2368 ldr r3, [r4] + 4008 0016 40F23A52 movw r2, #1338 + 4009 001a 9A63 str r2, [r3, #56] +2480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 4010 .loc 1 2480 3 view .LVU1452 +2480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 4011 .loc 1 2480 14 is_stmt 0 view .LVU1453 + 4012 001c 0123 movs r3, #1 + 4013 001e 84F83430 strb r3, [r4, #52] +2481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4014 .loc 1 2481 3 is_stmt 1 view .LVU1454 +2481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4015 .loc 1 2481 16 is_stmt 0 view .LVU1455 + 4016 0022 0023 movs r3, #0 + 4017 0024 2363 str r3, [r4, #48] +2486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif + 4018 .loc 1 2486 3 is_stmt 1 view .LVU1456 + 4019 0026 2046 mov r0, r4 + 4020 0028 FFF7FEFF bl HAL_SD_RxCpltCallback + 4021 .LVL323: +2488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4022 .loc 1 2488 1 is_stmt 0 view .LVU1457 + 4023 002c 10BD pop {r4, pc} + 4024 .LVL324: + 4025 .L245: +2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4026 .loc 1 2461 5 is_stmt 1 view .LVU1458 +2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4027 .loc 1 2461 18 is_stmt 0 view .LVU1459 + 4028 002e 2068 ldr r0, [r4] + 4029 .LVL325: +2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4030 .loc 1 2461 18 view .LVU1460 + 4031 0030 FFF7FEFF bl SDMMC_CmdStopTransfer + 4032 .LVL326: +2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4033 .loc 1 2462 5 is_stmt 1 view .LVU1461 +2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4034 .loc 1 2462 7 is_stmt 0 view .LVU1462 + 4035 0034 0346 mov r3, r0 + 4036 0036 0028 cmp r0, #0 + 4037 0038 E7D0 beq .L243 + ARM GAS /tmp/ccMMu31U.s page 152 + + +2464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + 4038 .loc 1 2464 7 is_stmt 1 view .LVU1463 +2464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + 4039 .loc 1 2464 10 is_stmt 0 view .LVU1464 + 4040 003a A26B ldr r2, [r4, #56] +2464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + 4041 .loc 1 2464 22 view .LVU1465 + 4042 003c 1343 orrs r3, r3, r2 + 4043 003e A363 str r3, [r4, #56] +2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif + 4044 .loc 1 2468 7 is_stmt 1 view .LVU1466 + 4045 0040 2046 mov r0, r4 + 4046 .LVL327: +2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif + 4047 .loc 1 2468 7 is_stmt 0 view .LVU1467 + 4048 0042 FFF7FEFF bl HAL_SD_ErrorCallback + 4049 .LVL328: + 4050 0046 E0E7 b .L243 + 4051 .cfi_endproc + 4052 .LFE169: + 4054 .section .text.HAL_SD_AbortCallback,"ax",%progbits + 4055 .align 1 + 4056 .weak HAL_SD_AbortCallback + 4057 .syntax unified + 4058 .thumb + 4059 .thumb_func + 4061 HAL_SD_AbortCallback: + 4062 .LVL329: + 4063 .LFB159: +1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Prevent unused argument(s) compilation warning */ + 4064 .loc 1 1742 1 is_stmt 1 view -0 + 4065 .cfi_startproc + 4066 @ args = 0, pretend = 0, frame = 0 + 4067 @ frame_needed = 0, uses_anonymous_args = 0 + 4068 @ link register save eliminated. +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4069 .loc 1 1744 3 view .LVU1469 +1749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4070 .loc 1 1749 1 is_stmt 0 view .LVU1470 + 4071 0000 7047 bx lr + 4072 .cfi_endproc + 4073 .LFE159: + 4075 .section .text.HAL_SD_GetCardCID,"ax",%progbits + 4076 .align 1 + 4077 .global HAL_SD_GetCardCID + 4078 .syntax unified + 4079 .thumb + 4080 .thumb_func + 4082 HAL_SD_GetCardCID: + 4083 .LVL330: + 4084 .LFB160: +1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U); + 4085 .loc 1 1953 1 is_stmt 1 view -0 + 4086 .cfi_startproc + 4087 @ args = 0, pretend = 0, frame = 0 + 4088 @ frame_needed = 0, uses_anonymous_args = 0 + 4089 @ link register save eliminated. + ARM GAS /tmp/ccMMu31U.s page 153 + + +1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4090 .loc 1 1954 3 view .LVU1472 +1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4091 .loc 1 1954 26 is_stmt 0 view .LVU1473 + 4092 0000 90F87730 ldrb r3, [r0, #119] @ zero_extendqisi2 +1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4093 .loc 1 1954 24 view .LVU1474 + 4094 0004 0B70 strb r3, [r1] +1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4095 .loc 1 1956 3 is_stmt 1 view .LVU1475 +1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4096 .loc 1 1956 43 is_stmt 0 view .LVU1476 + 4097 0006 436F ldr r3, [r0, #116] +1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4098 .loc 1 1956 23 view .LVU1477 + 4099 0008 C3F30F23 ubfx r3, r3, #8, #16 +1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4100 .loc 1 1956 21 view .LVU1478 + 4101 000c 4B80 strh r3, [r1, #2] @ movhi +1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4102 .loc 1 1958 3 is_stmt 1 view .LVU1479 +1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4103 .loc 1 1958 32 is_stmt 0 view .LVU1480 + 4104 000e 426F ldr r2, [r0, #116] +1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4105 .loc 1 1958 71 view .LVU1481 + 4106 0010 836F ldr r3, [r0, #120] +1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4107 .loc 1 1958 90 view .LVU1482 + 4108 0012 1B0A lsrs r3, r3, #8 +1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4109 .loc 1 1958 59 view .LVU1483 + 4110 0014 43EA0263 orr r3, r3, r2, lsl #24 +1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4111 .loc 1 1958 19 view .LVU1484 + 4112 0018 4B60 str r3, [r1, #4] +1960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4113 .loc 1 1960 3 is_stmt 1 view .LVU1485 +1960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4114 .loc 1 1960 21 is_stmt 0 view .LVU1486 + 4115 001a 90F87830 ldrb r3, [r0, #120] @ zero_extendqisi2 +1960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4116 .loc 1 1960 19 view .LVU1487 + 4117 001e 0B72 strb r3, [r1, #8] +1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4118 .loc 1 1962 3 is_stmt 1 view .LVU1488 +1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4119 .loc 1 1962 19 is_stmt 0 view .LVU1489 + 4120 0020 90F87F30 ldrb r3, [r0, #127] @ zero_extendqisi2 +1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4121 .loc 1 1962 17 view .LVU1490 + 4122 0024 4B72 strb r3, [r1, #9] +1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4123 .loc 1 1964 3 is_stmt 1 view .LVU1491 +1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4124 .loc 1 1964 29 is_stmt 0 view .LVU1492 + 4125 0026 C26F ldr r2, [r0, #124] + ARM GAS /tmp/ccMMu31U.s page 154 + + +1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4126 .loc 1 1964 86 view .LVU1493 + 4127 0028 90F88330 ldrb r3, [r0, #131] @ zero_extendqisi2 +1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4128 .loc 1 1964 55 view .LVU1494 + 4129 002c 43EA0223 orr r3, r3, r2, lsl #8 +1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4130 .loc 1 1964 16 view .LVU1495 + 4131 0030 CB60 str r3, [r1, #12] +1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4132 .loc 1 1966 3 is_stmt 1 view .LVU1496 +1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4133 .loc 1 1966 40 is_stmt 0 view .LVU1497 + 4134 0032 D0F88030 ldr r3, [r0, #128] +1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4135 .loc 1 1966 21 view .LVU1498 + 4136 0036 C3F30353 ubfx r3, r3, #20, #4 +1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4137 .loc 1 1966 19 view .LVU1499 + 4138 003a 0B74 strb r3, [r1, #16] +1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4139 .loc 1 1968 3 is_stmt 1 view .LVU1500 +1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4140 .loc 1 1968 44 is_stmt 0 view .LVU1501 + 4141 003c D0F88030 ldr r3, [r0, #128] +1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4142 .loc 1 1968 24 view .LVU1502 + 4143 0040 C3F30B23 ubfx r3, r3, #8, #12 +1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4144 .loc 1 1968 22 view .LVU1503 + 4145 0044 4B82 strh r3, [r1, #18] @ movhi +1970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4146 .loc 1 1970 3 is_stmt 1 view .LVU1504 +1970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4147 .loc 1 1970 38 is_stmt 0 view .LVU1505 + 4148 0046 D0F88030 ldr r3, [r0, #128] +1970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4149 .loc 1 1970 19 view .LVU1506 + 4150 004a C3F34603 ubfx r3, r3, #1, #7 +1970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4151 .loc 1 1970 17 view .LVU1507 + 4152 004e 0B75 strb r3, [r1, #20] +1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4153 .loc 1 1972 3 is_stmt 1 view .LVU1508 +1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4154 .loc 1 1972 19 is_stmt 0 view .LVU1509 + 4155 0050 0123 movs r3, #1 + 4156 0052 4B75 strb r3, [r1, #21] +1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4157 .loc 1 1974 3 is_stmt 1 view .LVU1510 +1975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4158 .loc 1 1975 1 is_stmt 0 view .LVU1511 + 4159 0054 0020 movs r0, #0 + 4160 .LVL331: +1975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4161 .loc 1 1975 1 view .LVU1512 + 4162 0056 7047 bx lr + ARM GAS /tmp/ccMMu31U.s page 155 + + + 4163 .cfi_endproc + 4164 .LFE160: + 4166 .section .text.HAL_SD_GetCardCSD,"ax",%progbits + 4167 .align 1 + 4168 .global HAL_SD_GetCardCSD + 4169 .syntax unified + 4170 .thumb + 4171 .thumb_func + 4173 HAL_SD_GetCardCSD: + 4174 .LVL332: + 4175 .LFB161: +1986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U); + 4176 .loc 1 1986 1 is_stmt 1 view -0 + 4177 .cfi_startproc + 4178 @ args = 0, pretend = 0, frame = 0 + 4179 @ frame_needed = 0, uses_anonymous_args = 0 + 4180 @ link register save eliminated. +1986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U); + 4181 .loc 1 1986 1 is_stmt 0 view .LVU1514 + 4182 0000 0346 mov r3, r0 +1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4183 .loc 1 1987 3 is_stmt 1 view .LVU1515 +1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4184 .loc 1 1987 40 is_stmt 0 view .LVU1516 + 4185 0002 426E ldr r2, [r0, #100] +1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4186 .loc 1 1987 21 view .LVU1517 + 4187 0004 920F lsrs r2, r2, #30 +1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4188 .loc 1 1987 19 view .LVU1518 + 4189 0006 0A70 strb r2, [r1] +1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4190 .loc 1 1989 3 is_stmt 1 view .LVU1519 +1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4191 .loc 1 1989 45 is_stmt 0 view .LVU1520 + 4192 0008 426E ldr r2, [r0, #100] +1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4193 .loc 1 1989 26 view .LVU1521 + 4194 000a C2F38362 ubfx r2, r2, #26, #4 +1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4195 .loc 1 1989 24 view .LVU1522 + 4196 000e 4A70 strb r2, [r1, #1] +1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4197 .loc 1 1991 3 is_stmt 1 view .LVU1523 +1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4198 .loc 1 1991 59 is_stmt 0 view .LVU1524 + 4199 0010 90F86720 ldrb r2, [r0, #103] @ zero_extendqisi2 +1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4200 .loc 1 1991 21 view .LVU1525 + 4201 0014 02F00302 and r2, r2, #3 +1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4202 .loc 1 1991 19 view .LVU1526 + 4203 0018 8A70 strb r2, [r1, #2] +1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4204 .loc 1 1993 3 is_stmt 1 view .LVU1527 +1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4205 .loc 1 1993 16 is_stmt 0 view .LVU1528 + ARM GAS /tmp/ccMMu31U.s page 156 + + + 4206 001a 90F86620 ldrb r2, [r0, #102] @ zero_extendqisi2 +1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4207 .loc 1 1993 14 view .LVU1529 + 4208 001e CA70 strb r2, [r1, #3] +1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4209 .loc 1 1995 3 is_stmt 1 view .LVU1530 +1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4210 .loc 1 1995 16 is_stmt 0 view .LVU1531 + 4211 0020 90F86520 ldrb r2, [r0, #101] @ zero_extendqisi2 +1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4212 .loc 1 1995 14 view .LVU1532 + 4213 0024 0A71 strb r2, [r1, #4] +1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4214 .loc 1 1997 3 is_stmt 1 view .LVU1533 +1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4215 .loc 1 1997 25 is_stmt 0 view .LVU1534 + 4216 0026 90F86420 ldrb r2, [r0, #100] @ zero_extendqisi2 +1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4217 .loc 1 1997 23 view .LVU1535 + 4218 002a 4A71 strb r2, [r1, #5] +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4219 .loc 1 1999 3 is_stmt 1 view .LVU1536 +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4220 .loc 1 1999 47 is_stmt 0 view .LVU1537 + 4221 002c 826E ldr r2, [r0, #104] +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4222 .loc 1 1999 27 view .LVU1538 + 4223 002e 120D lsrs r2, r2, #20 +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4224 .loc 1 1999 25 view .LVU1539 + 4225 0030 CA80 strh r2, [r1, #6] @ movhi +2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4226 .loc 1 2001 3 is_stmt 1 view .LVU1540 +2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4227 .loc 1 2001 60 is_stmt 0 view .LVU1541 + 4228 0032 B0F86A20 ldrh r2, [r0, #106] +2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4229 .loc 1 2001 22 view .LVU1542 + 4230 0036 02F00F02 and r2, r2, #15 +2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4231 .loc 1 2001 20 view .LVU1543 + 4232 003a 0A72 strb r2, [r1, #8] +2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4233 .loc 1 2003 3 is_stmt 1 view .LVU1544 +2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4234 .loc 1 2003 46 is_stmt 0 view .LVU1545 + 4235 003c 826E ldr r2, [r0, #104] +2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4236 .loc 1 2003 27 view .LVU1546 + 4237 003e C2F3C032 ubfx r2, r2, #15, #1 +2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4238 .loc 1 2003 25 view .LVU1547 + 4239 0042 4A72 strb r2, [r1, #9] +2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4240 .loc 1 2005 3 is_stmt 1 view .LVU1548 +2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4241 .loc 1 2005 46 is_stmt 0 view .LVU1549 + ARM GAS /tmp/ccMMu31U.s page 157 + + + 4242 0044 826E ldr r2, [r0, #104] +2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4243 .loc 1 2005 27 view .LVU1550 + 4244 0046 C2F38032 ubfx r2, r2, #14, #1 +2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4245 .loc 1 2005 25 view .LVU1551 + 4246 004a 8A72 strb r2, [r1, #10] +2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4247 .loc 1 2007 3 is_stmt 1 view .LVU1552 +2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4248 .loc 1 2007 46 is_stmt 0 view .LVU1553 + 4249 004c 826E ldr r2, [r0, #104] +2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4250 .loc 1 2007 27 view .LVU1554 + 4251 004e C2F34032 ubfx r2, r2, #13, #1 +2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4252 .loc 1 2007 25 view .LVU1555 + 4253 0052 CA72 strb r2, [r1, #11] +2009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4254 .loc 1 2009 3 is_stmt 1 view .LVU1556 +2009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4255 .loc 1 2009 38 is_stmt 0 view .LVU1557 + 4256 0054 826E ldr r2, [r0, #104] +2009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4257 .loc 1 2009 19 view .LVU1558 + 4258 0056 C2F30032 ubfx r2, r2, #12, #1 +2009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4259 .loc 1 2009 17 view .LVU1559 + 4260 005a 0A73 strb r2, [r1, #12] +2011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4261 .loc 1 2011 3 is_stmt 1 view .LVU1560 +2011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4262 .loc 1 2011 19 is_stmt 0 view .LVU1561 + 4263 005c 0022 movs r2, #0 + 4264 005e 4A73 strb r2, [r1, #13] +2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4265 .loc 1 2013 3 is_stmt 1 view .LVU1562 +2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4266 .loc 1 2013 17 is_stmt 0 view .LVU1563 + 4267 0060 426C ldr r2, [r0, #68] +2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4268 .loc 1 2013 5 view .LVU1564 + 4269 0062 002A cmp r2, #0 + 4270 0064 40F08680 bne .L249 +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4271 .loc 1 2015 5 is_stmt 1 view .LVU1565 +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4272 .loc 1 2015 35 is_stmt 0 view .LVU1566 + 4273 0068 806E ldr r0, [r0, #104] + 4274 .LVL333: +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4275 .loc 1 2015 54 view .LVU1567 + 4276 006a 40F6FC72 movw r2, #4092 + 4277 006e 02EA8002 and r2, r2, r0, lsl #2 +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4278 .loc 1 2015 73 view .LVU1568 + 4279 0072 D86E ldr r0, [r3, #108] + ARM GAS /tmp/ccMMu31U.s page 158 + + +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4280 .loc 1 2015 61 view .LVU1569 + 4281 0074 42EA9072 orr r2, r2, r0, lsr #30 +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4282 .loc 1 2015 22 view .LVU1570 + 4283 0078 0A61 str r2, [r1, #16] +2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4284 .loc 1 2017 5 is_stmt 1 view .LVU1571 +2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4285 .loc 1 2017 51 is_stmt 0 view .LVU1572 + 4286 007a DA6E ldr r2, [r3, #108] +2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4287 .loc 1 2017 32 view .LVU1573 + 4288 007c C2F3C262 ubfx r2, r2, #27, #3 +2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4289 .loc 1 2017 30 view .LVU1574 + 4290 0080 0A75 strb r2, [r1, #20] +2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4291 .loc 1 2019 5 is_stmt 1 view .LVU1575 +2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4292 .loc 1 2019 70 is_stmt 0 view .LVU1576 + 4293 0082 93F86F20 ldrb r2, [r3, #111] @ zero_extendqisi2 +2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4294 .loc 1 2019 32 view .LVU1577 + 4295 0086 02F00702 and r2, r2, #7 +2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4296 .loc 1 2019 30 view .LVU1578 + 4297 008a 4A75 strb r2, [r1, #21] +2021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4298 .loc 1 2021 5 is_stmt 1 view .LVU1579 +2021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4299 .loc 1 2021 51 is_stmt 0 view .LVU1580 + 4300 008c DA6E ldr r2, [r3, #108] +2021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4301 .loc 1 2021 32 view .LVU1581 + 4302 008e C2F34252 ubfx r2, r2, #21, #3 +2021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4303 .loc 1 2021 30 view .LVU1582 + 4304 0092 8A75 strb r2, [r1, #22] +2023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4305 .loc 1 2023 5 is_stmt 1 view .LVU1583 +2023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4306 .loc 1 2023 51 is_stmt 0 view .LVU1584 + 4307 0094 DA6E ldr r2, [r3, #108] +2023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4308 .loc 1 2023 32 view .LVU1585 + 4309 0096 C2F38242 ubfx r2, r2, #18, #3 +2023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4310 .loc 1 2023 30 view .LVU1586 + 4311 009a CA75 strb r2, [r1, #23] +2025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4312 .loc 1 2025 5 is_stmt 1 view .LVU1587 +2025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4313 .loc 1 2025 46 is_stmt 0 view .LVU1588 + 4314 009c DA6E ldr r2, [r3, #108] +2025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4315 .loc 1 2025 27 view .LVU1589 + ARM GAS /tmp/ccMMu31U.s page 159 + + + 4316 009e C2F3C232 ubfx r2, r2, #15, #3 +2025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4317 .loc 1 2025 25 view .LVU1590 + 4318 00a2 0A76 strb r2, [r1, #24] +2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); + 4319 .loc 1 2027 5 is_stmt 1 view .LVU1591 +2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); + 4320 .loc 1 2027 34 is_stmt 0 view .LVU1592 + 4321 00a4 0A69 ldr r2, [r1, #16] +2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); + 4322 .loc 1 2027 47 view .LVU1593 + 4323 00a6 0132 adds r2, r2, #1 +2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); + 4324 .loc 1 2027 27 view .LVU1594 + 4325 00a8 5A65 str r2, [r3, #84] +2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); + 4326 .loc 1 2028 5 is_stmt 1 view .LVU1595 +2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); + 4327 .loc 1 2028 43 is_stmt 0 view .LVU1596 + 4328 00aa 087E ldrb r0, [r1, #24] @ zero_extendqisi2 +2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); + 4329 .loc 1 2028 59 view .LVU1597 + 4330 00ac 00F00700 and r0, r0, #7 +2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); + 4331 .loc 1 2028 68 view .LVU1598 + 4332 00b0 0230 adds r0, r0, #2 +2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); + 4333 .loc 1 2028 26 view .LVU1599 + 4334 00b2 8240 lsls r2, r2, r0 + 4335 00b4 5A65 str r2, [r3, #84] +2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4336 .loc 1 2029 5 is_stmt 1 view .LVU1600 +2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4337 .loc 1 2029 42 is_stmt 0 view .LVU1601 + 4338 00b6 91F808C0 ldrb ip, [r1, #8] @ zero_extendqisi2 +2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4339 .loc 1 2029 55 view .LVU1602 + 4340 00ba 0CF00F0C and ip, ip, #15 +2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4341 .loc 1 2029 34 view .LVU1603 + 4342 00be 0120 movs r0, #1 + 4343 00c0 00FA0CF0 lsl r0, r0, ip +2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4344 .loc 1 2029 27 view .LVU1604 + 4345 00c4 9865 str r0, [r3, #88] +2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.LogBlockSize = 512U; + 4346 .loc 1 2031 5 is_stmt 1 view .LVU1605 +2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.LogBlockSize = 512U; + 4347 .loc 1 2031 82 is_stmt 0 view .LVU1606 + 4348 00c6 400A lsrs r0, r0, #9 +2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.LogBlockSize = 512U; + 4349 .loc 1 2031 55 view .LVU1607 + 4350 00c8 00FB02F2 mul r2, r0, r2 +2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.LogBlockSize = 512U; + 4351 .loc 1 2031 29 view .LVU1608 + 4352 00cc DA65 str r2, [r3, #92] +2032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + ARM GAS /tmp/ccMMu31U.s page 160 + + + 4353 .loc 1 2032 5 is_stmt 1 view .LVU1609 +2032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4354 .loc 1 2032 30 is_stmt 0 view .LVU1610 + 4355 00ce 4FF40072 mov r2, #512 + 4356 00d2 1A66 str r2, [r3, #96] + 4357 .L250: +2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4358 .loc 1 2053 3 is_stmt 1 view .LVU1611 +2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4359 .loc 1 2053 42 is_stmt 0 view .LVU1612 + 4360 00d4 DA6E ldr r2, [r3, #108] +2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4361 .loc 1 2053 23 view .LVU1613 + 4362 00d6 C2F38032 ubfx r2, r2, #14, #1 +2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4363 .loc 1 2053 21 view .LVU1614 + 4364 00da 4A76 strb r2, [r1, #25] +2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4365 .loc 1 2055 3 is_stmt 1 view .LVU1615 +2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4366 .loc 1 2055 41 is_stmt 0 view .LVU1616 + 4367 00dc DA6E ldr r2, [r3, #108] +2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4368 .loc 1 2055 22 view .LVU1617 + 4369 00de C2F3C612 ubfx r2, r2, #7, #7 +2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4370 .loc 1 2055 20 view .LVU1618 + 4371 00e2 8A76 strb r2, [r1, #26] +2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4372 .loc 1 2057 3 is_stmt 1 view .LVU1619 +2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4373 .loc 1 2057 45 is_stmt 0 view .LVU1620 + 4374 00e4 DA6E ldr r2, [r3, #108] +2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4375 .loc 1 2057 27 view .LVU1621 + 4376 00e6 02F07F02 and r2, r2, #127 +2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4377 .loc 1 2057 25 view .LVU1622 + 4378 00ea CA76 strb r2, [r1, #27] +2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4379 .loc 1 2059 3 is_stmt 1 view .LVU1623 +2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4380 .loc 1 2059 48 is_stmt 0 view .LVU1624 + 4381 00ec 1A6F ldr r2, [r3, #112] +2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4382 .loc 1 2059 29 view .LVU1625 + 4383 00ee D20F lsrs r2, r2, #31 +2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4384 .loc 1 2059 27 view .LVU1626 + 4385 00f0 0A77 strb r2, [r1, #28] +2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4386 .loc 1 2061 3 is_stmt 1 view .LVU1627 +2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4387 .loc 1 2061 41 is_stmt 0 view .LVU1628 + 4388 00f2 1A6F ldr r2, [r3, #112] +2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4389 .loc 1 2061 22 view .LVU1629 + ARM GAS /tmp/ccMMu31U.s page 161 + + + 4390 00f4 C2F34172 ubfx r2, r2, #29, #2 +2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4391 .loc 1 2061 20 view .LVU1630 + 4392 00f8 4A77 strb r2, [r1, #29] +2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4393 .loc 1 2063 3 is_stmt 1 view .LVU1631 +2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4394 .loc 1 2063 42 is_stmt 0 view .LVU1632 + 4395 00fa 1A6F ldr r2, [r3, #112] +2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4396 .loc 1 2063 23 view .LVU1633 + 4397 00fc C2F38262 ubfx r2, r2, #26, #3 +2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4398 .loc 1 2063 21 view .LVU1634 + 4399 0100 8A77 strb r2, [r1, #30] +2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4400 .loc 1 2065 3 is_stmt 1 view .LVU1635 +2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4401 .loc 1 2065 43 is_stmt 0 view .LVU1636 + 4402 0102 1A6F ldr r2, [r3, #112] +2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4403 .loc 1 2065 24 view .LVU1637 + 4404 0104 C2F38352 ubfx r2, r2, #22, #4 +2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4405 .loc 1 2065 22 view .LVU1638 + 4406 0108 CA77 strb r2, [r1, #31] +2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4407 .loc 1 2067 3 is_stmt 1 view .LVU1639 +2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4408 .loc 1 2067 50 is_stmt 0 view .LVU1640 + 4409 010a 1A6F ldr r2, [r3, #112] +2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4410 .loc 1 2067 31 view .LVU1641 + 4411 010c C2F34052 ubfx r2, r2, #21, #1 +2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4412 .loc 1 2067 29 view .LVU1642 + 4413 0110 81F82020 strb r2, [r1, #32] +2069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4414 .loc 1 2069 3 is_stmt 1 view .LVU1643 +2069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4415 .loc 1 2069 19 is_stmt 0 view .LVU1644 + 4416 0114 0020 movs r0, #0 + 4417 0116 81F82100 strb r0, [r1, #33] +2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4418 .loc 1 2071 3 is_stmt 1 view .LVU1645 +2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4419 .loc 1 2071 69 is_stmt 0 view .LVU1646 + 4420 011a B3F87220 ldrh r2, [r3, #114] +2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4421 .loc 1 2071 31 view .LVU1647 + 4422 011e 02F00102 and r2, r2, #1 +2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4423 .loc 1 2071 29 view .LVU1648 + 4424 0122 81F82220 strb r2, [r1, #34] +2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4425 .loc 1 2073 3 is_stmt 1 view .LVU1649 +2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + ARM GAS /tmp/ccMMu31U.s page 162 + + + 4426 .loc 1 2073 46 is_stmt 0 view .LVU1650 + 4427 0126 1A6F ldr r2, [r3, #112] +2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4428 .loc 1 2073 27 view .LVU1651 + 4429 0128 C2F3C032 ubfx r2, r2, #15, #1 +2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4430 .loc 1 2073 25 view .LVU1652 + 4431 012c 81F82320 strb r2, [r1, #35] +2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4432 .loc 1 2075 3 is_stmt 1 view .LVU1653 +2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4433 .loc 1 2075 39 is_stmt 0 view .LVU1654 + 4434 0130 1A6F ldr r2, [r3, #112] +2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4435 .loc 1 2075 20 view .LVU1655 + 4436 0132 C2F38032 ubfx r2, r2, #14, #1 +2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4437 .loc 1 2075 18 view .LVU1656 + 4438 0136 81F82420 strb r2, [r1, #36] +2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4439 .loc 1 2077 3 is_stmt 1 view .LVU1657 +2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4440 .loc 1 2077 44 is_stmt 0 view .LVU1658 + 4441 013a 1A6F ldr r2, [r3, #112] +2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4442 .loc 1 2077 25 view .LVU1659 + 4443 013c C2F34032 ubfx r2, r2, #13, #1 +2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4444 .loc 1 2077 23 view .LVU1660 + 4445 0140 81F82520 strb r2, [r1, #37] +2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4446 .loc 1 2079 3 is_stmt 1 view .LVU1661 +2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4447 .loc 1 2079 44 is_stmt 0 view .LVU1662 + 4448 0144 1A6F ldr r2, [r3, #112] +2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4449 .loc 1 2079 25 view .LVU1663 + 4450 0146 C2F30032 ubfx r2, r2, #12, #1 +2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4451 .loc 1 2079 23 view .LVU1664 + 4452 014a 81F82620 strb r2, [r1, #38] +2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4453 .loc 1 2081 3 is_stmt 1 view .LVU1665 +2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4454 .loc 1 2081 41 is_stmt 0 view .LVU1666 + 4455 014e 1A6F ldr r2, [r3, #112] +2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4456 .loc 1 2081 22 view .LVU1667 + 4457 0150 C2F38122 ubfx r2, r2, #10, #2 +2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4458 .loc 1 2081 20 view .LVU1668 + 4459 0154 81F82720 strb r2, [r1, #39] +2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4460 .loc 1 2083 3 is_stmt 1 view .LVU1669 +2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4461 .loc 1 2083 33 is_stmt 0 view .LVU1670 + 4462 0158 1A6F ldr r2, [r3, #112] + ARM GAS /tmp/ccMMu31U.s page 163 + + +2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4463 .loc 1 2083 14 view .LVU1671 + 4464 015a C2F30122 ubfx r2, r2, #8, #2 +2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4465 .loc 1 2083 12 view .LVU1672 + 4466 015e 81F82820 strb r2, [r1, #40] +2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4467 .loc 1 2085 3 is_stmt 1 view .LVU1673 +2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4468 .loc 1 2085 38 is_stmt 0 view .LVU1674 + 4469 0162 1B6F ldr r3, [r3, #112] + 4470 .LVL334: +2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4471 .loc 1 2085 19 view .LVU1675 + 4472 0164 C3F34603 ubfx r3, r3, #1, #7 +2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4473 .loc 1 2085 17 view .LVU1676 + 4474 0168 81F82930 strb r3, [r1, #41] +2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4475 .loc 1 2087 3 is_stmt 1 view .LVU1677 +2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4476 .loc 1 2087 19 is_stmt 0 view .LVU1678 + 4477 016c 0123 movs r3, #1 + 4478 016e 81F82A30 strb r3, [r1, #42] +2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4479 .loc 1 2089 3 is_stmt 1 view .LVU1679 +2090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4480 .loc 1 2090 1 is_stmt 0 view .LVU1680 + 4481 0172 7047 bx lr + 4482 .LVL335: + 4483 .L249: +2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4484 .loc 1 2034 8 is_stmt 1 view .LVU1681 +2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4485 .loc 1 2034 10 is_stmt 0 view .LVU1682 + 4486 0174 012A cmp r2, #1 + 4487 0176 11D1 bne .L251 +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4488 .loc 1 2037 5 is_stmt 1 view .LVU1683 +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4489 .loc 1 2037 35 is_stmt 0 view .LVU1684 + 4490 0178 826E ldr r2, [r0, #104] +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4491 .loc 1 2037 54 view .LVU1685 + 4492 017a 1204 lsls r2, r2, #16 + 4493 017c 02F47C12 and r2, r2, #4128768 +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4494 .loc 1 2037 93 view .LVU1686 + 4495 0180 B0F86E00 ldrh r0, [r0, #110] + 4496 .LVL336: +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4497 .loc 1 2037 62 view .LVU1687 + 4498 0184 0243 orrs r2, r2, r0 +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4499 .loc 1 2037 22 view .LVU1688 + 4500 0186 0A61 str r2, [r1, #16] +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; + ARM GAS /tmp/ccMMu31U.s page 164 + + + 4501 .loc 1 2039 5 is_stmt 1 view .LVU1689 +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; + 4502 .loc 1 2039 34 is_stmt 0 view .LVU1690 + 4503 0188 0A69 ldr r2, [r1, #16] +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; + 4504 .loc 1 2039 47 view .LVU1691 + 4505 018a 0132 adds r2, r2, #1 +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; + 4506 .loc 1 2039 53 view .LVU1692 + 4507 018c 9202 lsls r2, r2, #10 +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; + 4508 .loc 1 2039 26 view .LVU1693 + 4509 018e 5A65 str r2, [r3, #84] +2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.BlockSize = 512U; + 4510 .loc 1 2040 5 is_stmt 1 view .LVU1694 +2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.BlockSize = 512U; + 4511 .loc 1 2040 29 is_stmt 0 view .LVU1695 + 4512 0190 DA65 str r2, [r3, #92] +2041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize; + 4513 .loc 1 2041 5 is_stmt 1 view .LVU1696 +2041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize; + 4514 .loc 1 2041 27 is_stmt 0 view .LVU1697 + 4515 0192 4FF40072 mov r2, #512 + 4516 0196 9A65 str r2, [r3, #88] +2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4517 .loc 1 2042 5 is_stmt 1 view .LVU1698 +2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4518 .loc 1 2042 30 is_stmt 0 view .LVU1699 + 4519 0198 1A66 str r2, [r3, #96] + 4520 019a 9BE7 b .L250 + 4521 .LVL337: + 4522 .L251: +2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + 4523 .loc 1 2047 5 is_stmt 1 view .LVU1700 + 4524 019c 0268 ldr r2, [r0] + 4525 019e 0549 ldr r1, .L253 + 4526 .LVL338: +2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + 4527 .loc 1 2047 5 is_stmt 0 view .LVU1701 + 4528 01a0 9163 str r1, [r2, #56] +2048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 4529 .loc 1 2048 5 is_stmt 1 view .LVU1702 +2048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 4530 .loc 1 2048 8 is_stmt 0 view .LVU1703 + 4531 01a2 826B ldr r2, [r0, #56] +2048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 4532 .loc 1 2048 20 view .LVU1704 + 4533 01a4 42F08052 orr r2, r2, #268435456 + 4534 01a8 8263 str r2, [r0, #56] +2049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 4535 .loc 1 2049 5 is_stmt 1 view .LVU1705 +2049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 4536 .loc 1 2049 16 is_stmt 0 view .LVU1706 + 4537 01aa 0120 movs r0, #1 + 4538 .LVL339: +2049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 4539 .loc 1 2049 16 view .LVU1707 + ARM GAS /tmp/ccMMu31U.s page 165 + + + 4540 01ac 83F83400 strb r0, [r3, #52] +2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4541 .loc 1 2050 5 is_stmt 1 view .LVU1708 +2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4542 .loc 1 2050 12 is_stmt 0 view .LVU1709 + 4543 01b0 7047 bx lr + 4544 .L254: + 4545 01b2 00BF .align 2 + 4546 .L253: + 4547 01b4 FF054000 .word 4195839 + 4548 .cfi_endproc + 4549 .LFE161: + 4551 .section .text.SD_InitCard,"ax",%progbits + 4552 .align 1 + 4553 .syntax unified + 4554 .thumb + 4555 .thumb_func + 4557 SD_InitCard: + 4558 .LVL340: + 4559 .LFB173: +2618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardCSDTypeDef CSD; + 4560 .loc 1 2618 1 is_stmt 1 view -0 + 4561 .cfi_startproc + 4562 @ args = 0, pretend = 0, frame = 48 + 4563 @ frame_needed = 0, uses_anonymous_args = 0 +2618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardCSDTypeDef CSD; + 4564 .loc 1 2618 1 is_stmt 0 view .LVU1711 + 4565 0000 70B5 push {r4, r5, r6, lr} + 4566 .LCFI51: + 4567 .cfi_def_cfa_offset 16 + 4568 .cfi_offset 4, -16 + 4569 .cfi_offset 5, -12 + 4570 .cfi_offset 6, -8 + 4571 .cfi_offset 14, -4 + 4572 0002 90B0 sub sp, sp, #64 + 4573 .LCFI52: + 4574 .cfi_def_cfa_offset 80 + 4575 0004 0446 mov r4, r0 +2619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 4576 .loc 1 2619 3 is_stmt 1 view .LVU1712 +2620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint16_t sd_rca = 1U; + 4577 .loc 1 2620 3 view .LVU1713 +2621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4578 .loc 1 2621 3 view .LVU1714 +2621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4579 .loc 1 2621 12 is_stmt 0 view .LVU1715 + 4580 0006 0123 movs r3, #1 + 4581 0008 ADF81230 strh r3, [sp, #18] @ movhi +2624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4582 .loc 1 2624 3 is_stmt 1 view .LVU1716 +2624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4583 .loc 1 2624 6 is_stmt 0 view .LVU1717 + 4584 000c 0068 ldr r0, [r0] + 4585 .LVL341: +2624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4586 .loc 1 2624 6 view .LVU1718 + 4587 000e FFF7FEFF bl SDMMC_GetPowerState + ARM GAS /tmp/ccMMu31U.s page 166 + + + 4588 .LVL342: +2624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4589 .loc 1 2624 5 discriminator 1 view .LVU1719 + 4590 0012 0028 cmp r0, #0 + 4591 0014 6CD0 beq .L260 +2630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4592 .loc 1 2630 3 is_stmt 1 view .LVU1720 +2630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4593 .loc 1 2630 17 is_stmt 0 view .LVU1721 + 4594 0016 636C ldr r3, [r4, #68] +2630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4595 .loc 1 2630 5 view .LVU1722 + 4596 0018 032B cmp r3, #3 + 4597 001a 45D1 bne .L263 + 4598 .L257: +2648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4599 .loc 1 2648 3 is_stmt 1 view .LVU1723 +2648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4600 .loc 1 2648 17 is_stmt 0 view .LVU1724 + 4601 001c 636C ldr r3, [r4, #68] +2648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4602 .loc 1 2648 5 view .LVU1725 + 4603 001e 032B cmp r3, #3 + 4604 0020 5DD1 bne .L264 + 4605 .L258: +2658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4606 .loc 1 2658 3 is_stmt 1 view .LVU1726 +2658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4607 .loc 1 2658 17 is_stmt 0 view .LVU1727 + 4608 0022 636C ldr r3, [r4, #68] +2658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4609 .loc 1 2658 5 view .LVU1728 + 4610 0024 032B cmp r3, #3 + 4611 0026 1DD0 beq .L259 +2661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4612 .loc 1 2661 5 is_stmt 1 view .LVU1729 +2661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4613 .loc 1 2661 28 is_stmt 0 view .LVU1730 + 4614 0028 BDF81210 ldrh r1, [sp, #18] + 4615 002c 2165 str r1, [r4, #80] +2664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4616 .loc 1 2664 5 is_stmt 1 view .LVU1731 +2664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4617 .loc 1 2664 18 is_stmt 0 view .LVU1732 + 4618 002e 0904 lsls r1, r1, #16 + 4619 0030 2068 ldr r0, [r4] + 4620 0032 FFF7FEFF bl SDMMC_CmdSendCSD + 4621 .LVL343: +2665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4622 .loc 1 2665 5 is_stmt 1 view .LVU1733 +2665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4623 .loc 1 2665 7 is_stmt 0 view .LVU1734 + 4624 0036 0546 mov r5, r0 + 4625 0038 0028 cmp r0, #0 + 4626 003a 5BD1 bne .L255 +2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); + 4627 .loc 1 2672 7 is_stmt 1 view .LVU1735 + ARM GAS /tmp/ccMMu31U.s page 167 + + +2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); + 4628 .loc 1 2672 22 is_stmt 0 view .LVU1736 + 4629 003c 0021 movs r1, #0 + 4630 003e 2068 ldr r0, [r4] + 4631 .LVL344: +2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); + 4632 .loc 1 2672 22 view .LVU1737 + 4633 0040 FFF7FEFF bl SDMMC_GetResponse + 4634 .LVL345: +2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); + 4635 .loc 1 2672 20 discriminator 1 view .LVU1738 + 4636 0044 6066 str r0, [r4, #100] +2673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); + 4637 .loc 1 2673 7 is_stmt 1 view .LVU1739 +2673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); + 4638 .loc 1 2673 22 is_stmt 0 view .LVU1740 + 4639 0046 0421 movs r1, #4 + 4640 0048 2068 ldr r0, [r4] + 4641 004a FFF7FEFF bl SDMMC_GetResponse + 4642 .LVL346: +2673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); + 4643 .loc 1 2673 20 discriminator 1 view .LVU1741 + 4644 004e A066 str r0, [r4, #104] +2674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); + 4645 .loc 1 2674 7 is_stmt 1 view .LVU1742 +2674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); + 4646 .loc 1 2674 22 is_stmt 0 view .LVU1743 + 4647 0050 0821 movs r1, #8 + 4648 0052 2068 ldr r0, [r4] + 4649 0054 FFF7FEFF bl SDMMC_GetResponse + 4650 .LVL347: +2674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); + 4651 .loc 1 2674 20 discriminator 1 view .LVU1744 + 4652 0058 E066 str r0, [r4, #108] +2675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4653 .loc 1 2675 7 is_stmt 1 view .LVU1745 +2675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4654 .loc 1 2675 22 is_stmt 0 view .LVU1746 + 4655 005a 0C21 movs r1, #12 + 4656 005c 2068 ldr r0, [r4] + 4657 005e FFF7FEFF bl SDMMC_GetResponse + 4658 .LVL348: +2675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4659 .loc 1 2675 20 discriminator 1 view .LVU1747 + 4660 0062 2067 str r0, [r4, #112] + 4661 .LVL349: + 4662 .L259: +2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4663 .loc 1 2680 3 is_stmt 1 view .LVU1748 +2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4664 .loc 1 2680 24 is_stmt 0 view .LVU1749 + 4665 0064 0421 movs r1, #4 + 4666 0066 2068 ldr r0, [r4] + 4667 0068 FFF7FEFF bl SDMMC_GetResponse + 4668 .LVL350: +2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4669 .loc 1 2680 70 discriminator 1 view .LVU1750 + ARM GAS /tmp/ccMMu31U.s page 168 + + + 4670 006c 000D lsrs r0, r0, #20 +2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4671 .loc 1 2680 21 discriminator 1 view .LVU1751 + 4672 006e E064 str r0, [r4, #76] +2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4673 .loc 1 2683 3 is_stmt 1 view .LVU1752 +2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4674 .loc 1 2683 7 is_stmt 0 view .LVU1753 + 4675 0070 05A9 add r1, sp, #20 + 4676 0072 2046 mov r0, r4 + 4677 0074 FFF7FEFF bl HAL_SD_GetCardCSD + 4678 .LVL351: +2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4679 .loc 1 2683 6 discriminator 1 view .LVU1754 + 4680 0078 0028 cmp r0, #0 + 4681 007a 3ED1 bne .L261 +2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4682 .loc 1 2689 3 is_stmt 1 view .LVU1755 +2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4683 .loc 1 2689 82 is_stmt 0 view .LVU1756 + 4684 007c 226D ldr r2, [r4, #80] +2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4685 .loc 1 2689 16 view .LVU1757 + 4686 007e 1204 lsls r2, r2, #16 + 4687 0080 0023 movs r3, #0 + 4688 0082 2068 ldr r0, [r4] + 4689 0084 FFF7FEFF bl SDMMC_CmdSelDesel + 4690 .LVL352: +2690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4691 .loc 1 2690 3 is_stmt 1 view .LVU1758 +2690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4692 .loc 1 2690 5 is_stmt 0 view .LVU1759 + 4693 0088 0546 mov r5, r0 + 4694 008a 98BB cbnz r0, .L255 +2696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4695 .loc 1 2696 3 is_stmt 1 view .LVU1760 +2696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4696 .loc 1 2696 9 is_stmt 0 view .LVU1761 + 4697 008c 2346 mov r3, r4 + 4698 008e 53F8106B ldr r6, [r3], #16 + 4699 0092 93E80700 ldm r3, {r0, r1, r2} + 4700 .LVL353: +2696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4701 .loc 1 2696 9 view .LVU1762 + 4702 0096 8DE80700 stm sp, {r0, r1, r2} + 4703 009a 0434 adds r4, r4, #4 + 4704 .LVL354: +2696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4705 .loc 1 2696 9 view .LVU1763 + 4706 009c 94E80E00 ldm r4, {r1, r2, r3} + 4707 00a0 3046 mov r0, r6 + 4708 00a2 FFF7FEFF bl SDMMC_Init + 4709 .LVL355: +2699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4710 .loc 1 2699 3 is_stmt 1 view .LVU1764 +2699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4711 .loc 1 2699 10 is_stmt 0 view .LVU1765 + ARM GAS /tmp/ccMMu31U.s page 169 + + + 4712 00a6 25E0 b .L255 + 4713 .LVL356: + 4714 .L263: +2633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4715 .loc 1 2633 5 is_stmt 1 view .LVU1766 +2633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4716 .loc 1 2633 18 is_stmt 0 view .LVU1767 + 4717 00a8 2068 ldr r0, [r4] + 4718 00aa FFF7FEFF bl SDMMC_CmdSendCID + 4719 .LVL357: +2634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4720 .loc 1 2634 5 is_stmt 1 view .LVU1768 +2634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4721 .loc 1 2634 7 is_stmt 0 view .LVU1769 + 4722 00ae 0546 mov r5, r0 + 4723 00b0 00BB cbnz r0, .L255 +2641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); + 4724 .loc 1 2641 7 is_stmt 1 view .LVU1770 +2641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); + 4725 .loc 1 2641 22 is_stmt 0 view .LVU1771 + 4726 00b2 0021 movs r1, #0 + 4727 00b4 2068 ldr r0, [r4] + 4728 .LVL358: +2641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); + 4729 .loc 1 2641 22 view .LVU1772 + 4730 00b6 FFF7FEFF bl SDMMC_GetResponse + 4731 .LVL359: +2641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); + 4732 .loc 1 2641 20 discriminator 1 view .LVU1773 + 4733 00ba 6067 str r0, [r4, #116] +2642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); + 4734 .loc 1 2642 7 is_stmt 1 view .LVU1774 +2642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); + 4735 .loc 1 2642 22 is_stmt 0 view .LVU1775 + 4736 00bc 0421 movs r1, #4 + 4737 00be 2068 ldr r0, [r4] + 4738 00c0 FFF7FEFF bl SDMMC_GetResponse + 4739 .LVL360: +2642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); + 4740 .loc 1 2642 20 discriminator 1 view .LVU1776 + 4741 00c4 A067 str r0, [r4, #120] +2643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); + 4742 .loc 1 2643 7 is_stmt 1 view .LVU1777 +2643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); + 4743 .loc 1 2643 22 is_stmt 0 view .LVU1778 + 4744 00c6 0821 movs r1, #8 + 4745 00c8 2068 ldr r0, [r4] + 4746 00ca FFF7FEFF bl SDMMC_GetResponse + 4747 .LVL361: +2643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); + 4748 .loc 1 2643 20 discriminator 1 view .LVU1779 + 4749 00ce E067 str r0, [r4, #124] +2644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4750 .loc 1 2644 7 is_stmt 1 view .LVU1780 +2644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4751 .loc 1 2644 22 is_stmt 0 view .LVU1781 + 4752 00d0 0C21 movs r1, #12 + ARM GAS /tmp/ccMMu31U.s page 170 + + + 4753 00d2 2068 ldr r0, [r4] + 4754 00d4 FFF7FEFF bl SDMMC_GetResponse + 4755 .LVL362: +2644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4756 .loc 1 2644 20 discriminator 1 view .LVU1782 + 4757 00d8 C4F88000 str r0, [r4, #128] + 4758 00dc 9EE7 b .L257 + 4759 .LVL363: + 4760 .L264: +2652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4761 .loc 1 2652 5 is_stmt 1 view .LVU1783 +2652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4762 .loc 1 2652 18 is_stmt 0 view .LVU1784 + 4763 00de 0DF11201 add r1, sp, #18 + 4764 00e2 2068 ldr r0, [r4] + 4765 00e4 FFF7FEFF bl SDMMC_CmdSetRelAdd + 4766 .LVL364: +2653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4767 .loc 1 2653 5 is_stmt 1 view .LVU1785 +2653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4768 .loc 1 2653 7 is_stmt 0 view .LVU1786 + 4769 00e8 0546 mov r5, r0 + 4770 00ea 0028 cmp r0, #0 + 4771 00ec 99D0 beq .L258 + 4772 00ee 01E0 b .L255 + 4773 .LVL365: + 4774 .L260: +2627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4775 .loc 1 2627 12 view .LVU1787 + 4776 00f0 4FF08065 mov r5, #67108864 + 4777 .LVL366: + 4778 .L255: +2700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4779 .loc 1 2700 1 view .LVU1788 + 4780 00f4 2846 mov r0, r5 + 4781 00f6 10B0 add sp, sp, #64 + 4782 .LCFI53: + 4783 .cfi_remember_state + 4784 .cfi_def_cfa_offset 16 + 4785 @ sp needed + 4786 00f8 70BD pop {r4, r5, r6, pc} + 4787 .LVL367: + 4788 .L261: + 4789 .LCFI54: + 4790 .cfi_restore_state +2685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4791 .loc 1 2685 12 view .LVU1789 + 4792 00fa 4FF08055 mov r5, #268435456 + 4793 00fe F9E7 b .L255 + 4794 .cfi_endproc + 4795 .LFE173: + 4797 .section .text.HAL_SD_InitCard,"ax",%progbits + 4798 .align 1 + 4799 .global HAL_SD_InitCard + 4800 .syntax unified + 4801 .thumb + 4802 .thumb_func + ARM GAS /tmp/ccMMu31U.s page 171 + + + 4804 HAL_SD_InitCard: + 4805 .LVL368: + 4806 .LFB142: + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 4807 .loc 1 404 1 is_stmt 1 view -0 + 4808 .cfi_startproc + 4809 @ args = 0, pretend = 0, frame = 24 + 4810 @ frame_needed = 0, uses_anonymous_args = 0 + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 4811 .loc 1 404 1 is_stmt 0 view .LVU1791 + 4812 0000 30B5 push {r4, r5, lr} + 4813 .LCFI55: + 4814 .cfi_def_cfa_offset 12 + 4815 .cfi_offset 4, -12 + 4816 .cfi_offset 5, -8 + 4817 .cfi_offset 14, -4 + 4818 0002 8BB0 sub sp, sp, #44 + 4819 .LCFI56: + 4820 .cfi_def_cfa_offset 56 + 4821 0004 0446 mov r4, r0 + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef status; + 4822 .loc 1 405 3 is_stmt 1 view .LVU1792 + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_InitTypeDef Init; + 4823 .loc 1 406 3 view .LVU1793 + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4824 .loc 1 407 3 view .LVU1794 + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; + 4825 .loc 1 410 3 view .LVU1795 + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; + 4826 .loc 1 410 28 is_stmt 0 view .LVU1796 + 4827 0006 0023 movs r3, #0 + 4828 0008 0493 str r3, [sp, #16] + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + 4829 .loc 1 411 3 is_stmt 1 view .LVU1797 + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + 4830 .loc 1 411 28 is_stmt 0 view .LVU1798 + 4831 000a 0593 str r3, [sp, #20] + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.BusWide = SDMMC_BUS_WIDE_1B; + 4832 .loc 1 412 3 is_stmt 1 view .LVU1799 + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.BusWide = SDMMC_BUS_WIDE_1B; + 4833 .loc 1 412 28 is_stmt 0 view .LVU1800 + 4834 000c 0693 str r3, [sp, #24] + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + 4835 .loc 1 413 3 is_stmt 1 view .LVU1801 + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + 4836 .loc 1 413 28 is_stmt 0 view .LVU1802 + 4837 000e 0793 str r3, [sp, #28] + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockDiv = SDMMC_INIT_CLK_DIV; + 4838 .loc 1 414 3 is_stmt 1 view .LVU1803 + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockDiv = SDMMC_INIT_CLK_DIV; + 4839 .loc 1 414 28 is_stmt 0 view .LVU1804 + 4840 0010 0893 str r3, [sp, #32] + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4841 .loc 1 415 3 is_stmt 1 view .LVU1805 + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4842 .loc 1 415 28 is_stmt 0 view .LVU1806 + 4843 0012 7623 movs r3, #118 + ARM GAS /tmp/ccMMu31U.s page 172 + + + 4844 0014 0993 str r3, [sp, #36] + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(status != HAL_OK) + 4845 .loc 1 418 3 is_stmt 1 view .LVU1807 + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(status != HAL_OK) + 4846 .loc 1 418 12 is_stmt 0 view .LVU1808 + 4847 0016 0AAB add r3, sp, #40 + 4848 0018 13E90700 ldmdb r3, {r0, r1, r2} + 4849 .LVL369: + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(status != HAL_OK) + 4850 .loc 1 418 12 view .LVU1809 + 4851 001c 8DE80700 stm sp, {r0, r1, r2} + 4852 0020 04AB add r3, sp, #16 + 4853 0022 0ECB ldm r3, {r1, r2, r3} + 4854 0024 2068 ldr r0, [r4] + 4855 0026 FFF7FEFF bl SDMMC_Init + 4856 .LVL370: + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4857 .loc 1 419 3 is_stmt 1 view .LVU1810 + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4858 .loc 1 419 5 is_stmt 0 view .LVU1811 + 4859 002a 18B1 cbz r0, .L271 + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4860 .loc 1 421 12 view .LVU1812 + 4861 002c 0125 movs r5, #1 + 4862 .LVL371: + 4863 .L266: + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4864 .loc 1 466 1 view .LVU1813 + 4865 002e 2846 mov r0, r5 + 4866 0030 0BB0 add sp, sp, #44 + 4867 .LCFI57: + 4868 .cfi_remember_state + 4869 .cfi_def_cfa_offset 12 + 4870 @ sp needed + 4871 0032 30BD pop {r4, r5, pc} + 4872 .LVL372: + 4873 .L271: + 4874 .LCFI58: + 4875 .cfi_restore_state + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4876 .loc 1 466 1 view .LVU1814 + 4877 0034 0546 mov r5, r0 + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4878 .loc 1 425 3 is_stmt 1 view .LVU1815 + 4879 0036 2268 ldr r2, [r4] + 4880 0038 5368 ldr r3, [r2, #4] + 4881 003a 23F48073 bic r3, r3, #256 + 4882 003e 5360 str r3, [r2, #4] + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4883 .loc 1 428 3 view .LVU1816 + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4884 .loc 1 428 9 is_stmt 0 view .LVU1817 + 4885 0040 2068 ldr r0, [r4] + 4886 .LVL373: + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4887 .loc 1 428 9 view .LVU1818 + 4888 0042 FFF7FEFF bl SDMMC_PowerState_ON + ARM GAS /tmp/ccMMu31U.s page 173 + + + 4889 .LVL374: + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4890 .loc 1 431 3 is_stmt 1 view .LVU1819 + 4891 0046 2268 ldr r2, [r4] + 4892 0048 5368 ldr r3, [r2, #4] + 4893 004a 43F48073 orr r3, r3, #256 + 4894 004e 5360 str r3, [r2, #4] + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 4895 .loc 1 434 3 view .LVU1820 + 4896 0050 0220 movs r0, #2 + 4897 0052 FFF7FEFF bl HAL_Delay + 4898 .LVL375: + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4899 .loc 1 437 3 view .LVU1821 + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4900 .loc 1 437 16 is_stmt 0 view .LVU1822 + 4901 0056 2046 mov r0, r4 + 4902 0058 FFF7FEFF bl SD_PowerON + 4903 .LVL376: + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4904 .loc 1 438 3 is_stmt 1 view .LVU1823 + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4905 .loc 1 438 5 is_stmt 0 view .LVU1824 + 4906 005c 30B1 cbz r0, .L267 + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 4907 .loc 1 440 5 is_stmt 1 view .LVU1825 + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 4908 .loc 1 440 16 is_stmt 0 view .LVU1826 + 4909 005e 0125 movs r5, #1 + 4910 0060 84F83450 strb r5, [r4, #52] + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 4911 .loc 1 441 5 is_stmt 1 view .LVU1827 + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 4912 .loc 1 441 8 is_stmt 0 view .LVU1828 + 4913 0064 A36B ldr r3, [r4, #56] + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 4914 .loc 1 441 20 view .LVU1829 + 4915 0066 0343 orrs r3, r3, r0 + 4916 0068 A363 str r3, [r4, #56] + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4917 .loc 1 442 5 is_stmt 1 view .LVU1830 + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4918 .loc 1 442 12 is_stmt 0 view .LVU1831 + 4919 006a E0E7 b .L266 + 4920 .L267: + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4921 .loc 1 446 3 is_stmt 1 view .LVU1832 + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4922 .loc 1 446 16 is_stmt 0 view .LVU1833 + 4923 006c 2046 mov r0, r4 + 4924 .LVL377: + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4925 .loc 1 446 16 view .LVU1834 + 4926 006e FFF7FEFF bl SD_InitCard + 4927 .LVL378: + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4928 .loc 1 447 3 is_stmt 1 view .LVU1835 + ARM GAS /tmp/ccMMu31U.s page 174 + + + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4929 .loc 1 447 5 is_stmt 0 view .LVU1836 + 4930 0072 30B1 cbz r0, .L268 + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 4931 .loc 1 449 5 is_stmt 1 view .LVU1837 + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 4932 .loc 1 449 16 is_stmt 0 view .LVU1838 + 4933 0074 0125 movs r5, #1 + 4934 0076 84F83450 strb r5, [r4, #52] + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 4935 .loc 1 450 5 is_stmt 1 view .LVU1839 + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 4936 .loc 1 450 8 is_stmt 0 view .LVU1840 + 4937 007a A36B ldr r3, [r4, #56] + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 4938 .loc 1 450 20 view .LVU1841 + 4939 007c 0343 orrs r3, r3, r0 + 4940 007e A363 str r3, [r4, #56] + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4941 .loc 1 451 5 is_stmt 1 view .LVU1842 + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4942 .loc 1 451 12 is_stmt 0 view .LVU1843 + 4943 0080 D5E7 b .L266 + 4944 .L268: + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4945 .loc 1 455 3 is_stmt 1 view .LVU1844 + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4946 .loc 1 455 16 is_stmt 0 view .LVU1845 + 4947 0082 4FF40071 mov r1, #512 + 4948 0086 2068 ldr r0, [r4] + 4949 .LVL379: + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 4950 .loc 1 455 16 view .LVU1846 + 4951 0088 FFF7FEFF bl SDMMC_CmdBlockLength + 4952 .LVL380: + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4953 .loc 1 456 3 is_stmt 1 view .LVU1847 + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4954 .loc 1 456 5 is_stmt 0 view .LVU1848 + 4955 008c 0028 cmp r0, #0 + 4956 008e CED0 beq .L266 + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 4957 .loc 1 459 5 is_stmt 1 view .LVU1849 + 4958 0090 2368 ldr r3, [r4] + 4959 0092 0449 ldr r1, .L272 + 4960 0094 9963 str r1, [r3, #56] + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 4961 .loc 1 460 5 view .LVU1850 + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 4962 .loc 1 460 8 is_stmt 0 view .LVU1851 + 4963 0096 A36B ldr r3, [r4, #56] + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 4964 .loc 1 460 20 view .LVU1852 + 4965 0098 0343 orrs r3, r3, r0 + 4966 009a A363 str r3, [r4, #56] + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 4967 .loc 1 461 5 is_stmt 1 view .LVU1853 + ARM GAS /tmp/ccMMu31U.s page 175 + + + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** return HAL_ERROR; + 4968 .loc 1 461 16 is_stmt 0 view .LVU1854 + 4969 009c 0125 movs r5, #1 + 4970 009e 84F83450 strb r5, [r4, #52] + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4971 .loc 1 462 5 is_stmt 1 view .LVU1855 + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 4972 .loc 1 462 12 is_stmt 0 view .LVU1856 + 4973 00a2 C4E7 b .L266 + 4974 .L273: + 4975 .align 2 + 4976 .L272: + 4977 00a4 FF054000 .word 4195839 + 4978 .cfi_endproc + 4979 .LFE142: + 4981 .section .text.HAL_SD_Init,"ax",%progbits + 4982 .align 1 + 4983 .global HAL_SD_Init + 4984 .syntax unified + 4985 .thumb + 4986 .thumb_func + 4988 HAL_SD_Init: + 4989 .LVL381: + 4990 .LFB141: + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Check the SD handle allocation */ + 4991 .loc 1 336 1 is_stmt 1 view -0 + 4992 .cfi_startproc + 4993 @ args = 0, pretend = 0, frame = 0 + 4994 @ frame_needed = 0, uses_anonymous_args = 0 + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4995 .loc 1 338 3 view .LVU1858 + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 4996 .loc 1 338 5 is_stmt 0 view .LVU1859 + 4997 0000 A8B1 cbz r0, .L277 + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Check the SD handle allocation */ + 4998 .loc 1 336 1 view .LVU1860 + 4999 0002 10B5 push {r4, lr} + 5000 .LCFI59: + 5001 .cfi_def_cfa_offset 8 + 5002 .cfi_offset 4, -8 + 5003 .cfi_offset 14, -4 + 5004 0004 0446 mov r4, r0 + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** assert_param(IS_SDMMC_CLOCK_EDGE(hsd->Init.ClockEdge)); + 5005 .loc 1 344 3 is_stmt 1 view .LVU1861 + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** assert_param(IS_SDMMC_CLOCK_BYPASS(hsd->Init.ClockBypass)); + 5006 .loc 1 345 3 view .LVU1862 + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave)); + 5007 .loc 1 346 3 view .LVU1863 + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide)); + 5008 .loc 1 347 3 view .LVU1864 + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl)); + 5009 .loc 1 348 3 view .LVU1865 + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv)); + 5010 .loc 1 349 3 view .LVU1866 + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5011 .loc 1 350 3 view .LVU1867 + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + ARM GAS /tmp/ccMMu31U.s page 176 + + + 5012 .loc 1 352 3 view .LVU1868 + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5013 .loc 1 352 9 is_stmt 0 view .LVU1869 + 5014 0006 90F83430 ldrb r3, [r0, #52] @ zero_extendqisi2 + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5015 .loc 1 352 5 view .LVU1870 + 5016 000a 63B1 cbz r3, .L283 + 5017 .LVL382: + 5018 .L276: + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5019 .loc 1 376 3 is_stmt 1 view .LVU1871 + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5020 .loc 1 376 14 is_stmt 0 view .LVU1872 + 5021 000c 0323 movs r3, #3 + 5022 000e 84F83430 strb r3, [r4, #52] + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5023 .loc 1 379 3 is_stmt 1 view .LVU1873 + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5024 .loc 1 379 7 is_stmt 0 view .LVU1874 + 5025 0012 2046 mov r0, r4 + 5026 0014 FFF7FEFF bl HAL_SD_InitCard + 5027 .LVL383: + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5028 .loc 1 379 6 discriminator 1 view .LVU1875 + 5029 0018 58B9 cbnz r0, .L278 + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5030 .loc 1 385 3 is_stmt 1 view .LVU1876 + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5031 .loc 1 385 18 is_stmt 0 view .LVU1877 + 5032 001a A063 str r0, [r4, #56] + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5033 .loc 1 388 3 is_stmt 1 view .LVU1878 + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5034 .loc 1 388 16 is_stmt 0 view .LVU1879 + 5035 001c 2063 str r0, [r4, #48] + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5036 .loc 1 391 3 is_stmt 1 view .LVU1880 + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5037 .loc 1 391 14 is_stmt 0 view .LVU1881 + 5038 001e 0123 movs r3, #1 + 5039 0020 84F83430 strb r3, [r4, #52] + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5040 .loc 1 393 3 is_stmt 1 view .LVU1882 + 5041 .L275: + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5042 .loc 1 394 1 is_stmt 0 view .LVU1883 + 5043 0024 10BD pop {r4, pc} + 5044 .LVL384: + 5045 .L283: + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + 5046 .loc 1 355 5 is_stmt 1 view .LVU1884 + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + 5047 .loc 1 355 15 is_stmt 0 view .LVU1885 + 5048 0026 0377 strb r3, [r0, #28] + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + 5049 .loc 1 372 5 is_stmt 1 view .LVU1886 + 5050 0028 FFF7FEFF bl HAL_SD_MspInit + ARM GAS /tmp/ccMMu31U.s page 177 + + + 5051 .LVL385: + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + 5052 .loc 1 372 5 is_stmt 0 view .LVU1887 + 5053 002c EEE7 b .L276 + 5054 .LVL386: + 5055 .L277: + 5056 .LCFI60: + 5057 .cfi_def_cfa_offset 0 + 5058 .cfi_restore 4 + 5059 .cfi_restore 14 + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5060 .loc 1 340 12 view .LVU1888 + 5061 002e 0120 movs r0, #1 + 5062 .LVL387: + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5063 .loc 1 394 1 view .LVU1889 + 5064 0030 7047 bx lr + 5065 .LVL388: + 5066 .L278: + 5067 .LCFI61: + 5068 .cfi_def_cfa_offset 8 + 5069 .cfi_offset 4, -8 + 5070 .cfi_offset 14, -4 + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5071 .loc 1 381 12 view .LVU1890 + 5072 0032 0120 movs r0, #1 + 5073 0034 F6E7 b .L275 + 5074 .cfi_endproc + 5075 .LFE141: + 5077 .section .text.HAL_SD_GetCardStatus,"ax",%progbits + 5078 .align 1 + 5079 .global HAL_SD_GetCardStatus + 5080 .syntax unified + 5081 .thumb + 5082 .thumb_func + 5084 HAL_SD_GetCardStatus: + 5085 .LVL389: + 5086 .LFB162: +2100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t sd_status[16]; + 5087 .loc 1 2100 1 is_stmt 1 view -0 + 5088 .cfi_startproc + 5089 @ args = 0, pretend = 0, frame = 64 + 5090 @ frame_needed = 0, uses_anonymous_args = 0 +2100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t sd_status[16]; + 5091 .loc 1 2100 1 is_stmt 0 view .LVU1892 + 5092 0000 30B5 push {r4, r5, lr} + 5093 .LCFI62: + 5094 .cfi_def_cfa_offset 12 + 5095 .cfi_offset 4, -12 + 5096 .cfi_offset 5, -8 + 5097 .cfi_offset 14, -4 + 5098 0002 91B0 sub sp, sp, #68 + 5099 .LCFI63: + 5100 .cfi_def_cfa_offset 80 + 5101 0004 0546 mov r5, r0 + 5102 0006 0C46 mov r4, r1 +2101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + ARM GAS /tmp/ccMMu31U.s page 178 + + + 5103 .loc 1 2101 3 is_stmt 1 view .LVU1893 +2102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef status = HAL_OK; + 5104 .loc 1 2102 3 view .LVU1894 +2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5105 .loc 1 2103 3 view .LVU1895 + 5106 .LVL390: +2105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 5107 .loc 1 2105 3 view .LVU1896 +2105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 5108 .loc 1 2105 16 is_stmt 0 view .LVU1897 + 5109 0008 6946 mov r1, sp + 5110 .LVL391: +2105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 5111 .loc 1 2105 16 view .LVU1898 + 5112 000a FFF7FEFF bl SD_SendSDStatus + 5113 .LVL392: +2106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5114 .loc 1 2106 3 is_stmt 1 view .LVU1899 +2106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5115 .loc 1 2106 5 is_stmt 0 view .LVU1900 + 5116 000e C0B1 cbz r0, .L285 +2109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 5117 .loc 1 2109 5 is_stmt 1 view .LVU1901 + 5118 0010 2B68 ldr r3, [r5] + 5119 0012 2549 ldr r1, .L289 + 5120 0014 9963 str r1, [r3, #56] +2110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 5121 .loc 1 2110 5 view .LVU1902 +2110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 5122 .loc 1 2110 8 is_stmt 0 view .LVU1903 + 5123 0016 AB6B ldr r3, [r5, #56] +2110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 5124 .loc 1 2110 20 view .LVU1904 + 5125 0018 0343 orrs r3, r3, r0 + 5126 001a AB63 str r3, [r5, #56] +2111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; + 5127 .loc 1 2111 5 is_stmt 1 view .LVU1905 +2111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; + 5128 .loc 1 2111 16 is_stmt 0 view .LVU1906 + 5129 001c 0124 movs r4, #1 + 5130 .LVL393: +2111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; + 5131 .loc 1 2111 16 view .LVU1907 + 5132 001e 85F83440 strb r4, [r5, #52] +2112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5133 .loc 1 2112 5 is_stmt 1 view .LVU1908 + 5134 .LVL394: + 5135 .L286: +2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 5136 .loc 1 2139 3 view .LVU1909 +2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 5137 .loc 1 2139 16 is_stmt 0 view .LVU1910 + 5138 0022 4FF40071 mov r1, #512 + 5139 0026 2868 ldr r0, [r5] + 5140 .LVL395: +2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 5141 .loc 1 2139 16 view .LVU1911 + ARM GAS /tmp/ccMMu31U.s page 179 + + + 5142 0028 FFF7FEFF bl SDMMC_CmdBlockLength + 5143 .LVL396: +2140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5144 .loc 1 2140 3 is_stmt 1 view .LVU1912 +2140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5145 .loc 1 2140 5 is_stmt 0 view .LVU1913 + 5146 002c 30B1 cbz r0, .L287 +2143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode = errorstate; + 5147 .loc 1 2143 5 is_stmt 1 view .LVU1914 + 5148 002e 2A68 ldr r2, [r5] + 5149 0030 1D49 ldr r1, .L289 + 5150 0032 9163 str r1, [r2, #56] +2144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 5151 .loc 1 2144 5 view .LVU1915 +2144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 5152 .loc 1 2144 20 is_stmt 0 view .LVU1916 + 5153 0034 A863 str r0, [r5, #56] +2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; + 5154 .loc 1 2145 5 is_stmt 1 view .LVU1917 +2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; + 5155 .loc 1 2145 16 is_stmt 0 view .LVU1918 + 5156 0036 0124 movs r4, #1 + 5157 .LVL397: +2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; + 5158 .loc 1 2145 16 view .LVU1919 + 5159 0038 85F83440 strb r4, [r5, #52] +2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5160 .loc 1 2146 5 is_stmt 1 view .LVU1920 + 5161 .LVL398: + 5162 .L287: +2149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5163 .loc 1 2149 3 view .LVU1921 +2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5164 .loc 1 2150 1 is_stmt 0 view .LVU1922 + 5165 003c 2046 mov r0, r4 + 5166 .LVL399: +2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5167 .loc 1 2150 1 view .LVU1923 + 5168 003e 11B0 add sp, sp, #68 + 5169 .LCFI64: + 5170 .cfi_remember_state + 5171 .cfi_def_cfa_offset 12 + 5172 @ sp needed + 5173 0040 30BD pop {r4, r5, pc} + 5174 .LVL400: + 5175 .L285: + 5176 .LCFI65: + 5177 .cfi_restore_state +2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5178 .loc 1 2116 5 is_stmt 1 view .LVU1924 +2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5179 .loc 1 2116 49 is_stmt 0 view .LVU1925 + 5180 0042 009A ldr r2, [sp] +2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5181 .loc 1 2116 29 view .LVU1926 + 5182 0044 C2F38113 ubfx r3, r2, #6, #2 +2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + ARM GAS /tmp/ccMMu31U.s page 180 + + + 5183 .loc 1 2116 27 view .LVU1927 + 5184 0048 2370 strb r3, [r4] +2118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5185 .loc 1 2118 5 is_stmt 1 view .LVU1928 +2118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5186 .loc 1 2118 28 is_stmt 0 view .LVU1929 + 5187 004a C2F34013 ubfx r3, r2, #5, #1 +2118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5188 .loc 1 2118 26 view .LVU1930 + 5189 004e 6370 strb r3, [r4, #1] +2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5190 .loc 1 2120 5 is_stmt 1 view .LVU1931 +2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5191 .loc 1 2120 66 is_stmt 0 view .LVU1932 + 5192 0050 130A lsrs r3, r2, #8 +2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5193 .loc 1 2120 25 view .LVU1933 + 5194 0052 23F0FF03 bic r3, r3, #255 + 5195 0056 43EA1263 orr r3, r3, r2, lsr #24 + 5196 005a 9BB2 uxth r3, r3 +2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5197 .loc 1 2120 23 view .LVU1934 + 5198 005c 6380 strh r3, [r4, #2] @ movhi +2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U + 5199 .loc 1 2122 5 is_stmt 1 view .LVU1935 +2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U + 5200 .loc 1 2122 46 is_stmt 0 view .LVU1936 + 5201 005e 019A ldr r2, [sp, #4] +2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U + 5202 .loc 1 2122 98 view .LVU1937 + 5203 0060 1302 lsls r3, r2, #8 + 5204 0062 03F47F03 and r3, r3, #16711680 +2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U + 5205 .loc 1 2122 70 view .LVU1938 + 5206 0066 43EA0263 orr r3, r3, r2, lsl #24 +2123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5207 .loc 1 2123 63 view .LVU1939 + 5208 006a 110A lsrs r1, r2, #8 + 5209 006c 01F47F41 and r1, r1, #65280 +2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U + 5210 .loc 1 2122 105 view .LVU1940 + 5211 0070 0B43 orrs r3, r3, r1 +2123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5212 .loc 1 2123 70 view .LVU1941 + 5213 0072 43EA1263 orr r3, r3, r2, lsr #24 +2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U + 5214 .loc 1 2122 32 view .LVU1942 + 5215 0076 6360 str r3, [r4, #4] +2125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5216 .loc 1 2125 5 is_stmt 1 view .LVU1943 +2125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5217 .loc 1 2125 46 is_stmt 0 view .LVU1944 + 5218 0078 029B ldr r3, [sp, #8] +2125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5219 .loc 1 2125 27 view .LVU1945 + 5220 007a DAB2 uxtb r2, r3 +2125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + ARM GAS /tmp/ccMMu31U.s page 181 + + + 5221 .loc 1 2125 25 view .LVU1946 + 5222 007c 2272 strb r2, [r4, #8] +2127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5223 .loc 1 2127 5 is_stmt 1 view .LVU1947 +2127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5224 .loc 1 2127 32 is_stmt 0 view .LVU1948 + 5225 007e C3F30722 ubfx r2, r3, #8, #8 +2127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5226 .loc 1 2127 30 view .LVU1949 + 5227 0082 6272 strb r2, [r4, #9] +2129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5228 .loc 1 2129 5 is_stmt 1 view .LVU1950 +2129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5229 .loc 1 2129 35 is_stmt 0 view .LVU1951 + 5230 0084 C3F30352 ubfx r2, r3, #20, #4 +2129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5231 .loc 1 2129 33 view .LVU1952 + 5232 0088 A272 strb r2, [r4, #10] +2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5233 .loc 1 2131 5 is_stmt 1 view .LVU1953 +2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5234 .loc 1 2131 67 is_stmt 0 view .LVU1954 + 5235 008a 1B0C lsrs r3, r3, #16 +2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5236 .loc 1 2131 87 view .LVU1955 + 5237 008c 039A ldr r2, [sp, #12] +2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5238 .loc 1 2131 91 view .LVU1956 + 5239 008e D1B2 uxtb r1, r2 +2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5240 .loc 1 2131 26 view .LVU1957 + 5241 0090 23F0FF03 bic r3, r3, #255 + 5242 0094 0B43 orrs r3, r3, r1 +2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5243 .loc 1 2131 24 view .LVU1958 + 5244 0096 A381 strh r3, [r4, #12] @ movhi +2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5245 .loc 1 2133 5 is_stmt 1 view .LVU1959 +2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5246 .loc 1 2133 29 is_stmt 0 view .LVU1960 + 5247 0098 C2F38523 ubfx r3, r2, #10, #6 +2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5248 .loc 1 2133 27 view .LVU1961 + 5249 009c A373 strb r3, [r4, #14] +2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5250 .loc 1 2135 5 is_stmt 1 view .LVU1962 +2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5251 .loc 1 2135 28 is_stmt 0 view .LVU1963 + 5252 009e C2F30122 ubfx r2, r2, #8, #2 +2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5253 .loc 1 2135 26 view .LVU1964 + 5254 00a2 E273 strb r2, [r4, #15] +2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5255 .loc 1 2103 21 view .LVU1965 + 5256 00a4 0024 movs r4, #0 + 5257 .LVL401: +2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + ARM GAS /tmp/ccMMu31U.s page 182 + + + 5258 .loc 1 2103 21 view .LVU1966 + 5259 00a6 BCE7 b .L286 + 5260 .L290: + 5261 .align 2 + 5262 .L289: + 5263 00a8 FF054000 .word 4195839 + 5264 .cfi_endproc + 5265 .LFE162: + 5267 .section .text.HAL_SD_GetCardInfo,"ax",%progbits + 5268 .align 1 + 5269 .global HAL_SD_GetCardInfo + 5270 .syntax unified + 5271 .thumb + 5272 .thumb_func + 5274 HAL_SD_GetCardInfo: + 5275 .LVL402: + 5276 .LFB163: +2160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType); + 5277 .loc 1 2160 1 is_stmt 1 view -0 + 5278 .cfi_startproc + 5279 @ args = 0, pretend = 0, frame = 0 + 5280 @ frame_needed = 0, uses_anonymous_args = 0 + 5281 @ link register save eliminated. +2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); + 5282 .loc 1 2161 3 view .LVU1968 +2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); + 5283 .loc 1 2161 51 is_stmt 0 view .LVU1969 + 5284 0000 436C ldr r3, [r0, #68] +2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); + 5285 .loc 1 2161 27 view .LVU1970 + 5286 0002 0B60 str r3, [r1] +2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->Class = (uint32_t)(hsd->SdCard.Class); + 5287 .loc 1 2162 3 is_stmt 1 view .LVU1971 +2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->Class = (uint32_t)(hsd->SdCard.Class); + 5288 .loc 1 2162 51 is_stmt 0 view .LVU1972 + 5289 0004 836C ldr r3, [r0, #72] +2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->Class = (uint32_t)(hsd->SdCard.Class); + 5290 .loc 1 2162 27 view .LVU1973 + 5291 0006 4B60 str r3, [r1, #4] +2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd); + 5292 .loc 1 2163 3 is_stmt 1 view .LVU1974 +2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd); + 5293 .loc 1 2163 51 is_stmt 0 view .LVU1975 + 5294 0008 C36C ldr r3, [r0, #76] +2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd); + 5295 .loc 1 2163 27 view .LVU1976 + 5296 000a 8B60 str r3, [r1, #8] +2164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr); + 5297 .loc 1 2164 3 is_stmt 1 view .LVU1977 +2164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr); + 5298 .loc 1 2164 51 is_stmt 0 view .LVU1978 + 5299 000c 036D ldr r3, [r0, #80] +2164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr); + 5300 .loc 1 2164 27 view .LVU1979 + 5301 000e CB60 str r3, [r1, #12] +2165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize); + 5302 .loc 1 2165 3 is_stmt 1 view .LVU1980 + ARM GAS /tmp/ccMMu31U.s page 183 + + +2165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize); + 5303 .loc 1 2165 51 is_stmt 0 view .LVU1981 + 5304 0010 436D ldr r3, [r0, #84] +2165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize); + 5305 .loc 1 2165 27 view .LVU1982 + 5306 0012 0B61 str r3, [r1, #16] +2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr); + 5307 .loc 1 2166 3 is_stmt 1 view .LVU1983 +2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr); + 5308 .loc 1 2166 51 is_stmt 0 view .LVU1984 + 5309 0014 836D ldr r3, [r0, #88] +2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr); + 5310 .loc 1 2166 27 view .LVU1985 + 5311 0016 4B61 str r3, [r1, #20] +2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize); + 5312 .loc 1 2167 3 is_stmt 1 view .LVU1986 +2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize); + 5313 .loc 1 2167 51 is_stmt 0 view .LVU1987 + 5314 0018 C36D ldr r3, [r0, #92] +2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize); + 5315 .loc 1 2167 27 view .LVU1988 + 5316 001a 8B61 str r3, [r1, #24] +2168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5317 .loc 1 2168 3 is_stmt 1 view .LVU1989 +2168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5318 .loc 1 2168 51 is_stmt 0 view .LVU1990 + 5319 001c 036E ldr r3, [r0, #96] +2168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5320 .loc 1 2168 27 view .LVU1991 + 5321 001e CB61 str r3, [r1, #28] +2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5322 .loc 1 2170 3 is_stmt 1 view .LVU1992 +2171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5323 .loc 1 2171 1 is_stmt 0 view .LVU1993 + 5324 0020 0020 movs r0, #0 + 5325 .LVL403: +2171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5326 .loc 1 2171 1 view .LVU1994 + 5327 0022 7047 bx lr + 5328 .cfi_endproc + 5329 .LFE163: + 5331 .section .text.HAL_SD_ConfigWideBusOperation,"ax",%progbits + 5332 .align 1 + 5333 .global HAL_SD_ConfigWideBusOperation + 5334 .syntax unified + 5335 .thumb + 5336 .thumb_func + 5338 HAL_SD_ConfigWideBusOperation: + 5339 .LVL404: + 5340 .LFB164: +2185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_InitTypeDef Init; + 5341 .loc 1 2185 1 is_stmt 1 view -0 + 5342 .cfi_startproc + 5343 @ args = 0, pretend = 0, frame = 24 + 5344 @ frame_needed = 0, uses_anonymous_args = 0 +2185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_InitTypeDef Init; + 5345 .loc 1 2185 1 is_stmt 0 view .LVU1996 + ARM GAS /tmp/ccMMu31U.s page 184 + + + 5346 0000 30B5 push {r4, r5, lr} + 5347 .LCFI66: + 5348 .cfi_def_cfa_offset 12 + 5349 .cfi_offset 4, -12 + 5350 .cfi_offset 5, -8 + 5351 .cfi_offset 14, -4 + 5352 0002 8BB0 sub sp, sp, #44 + 5353 .LCFI67: + 5354 .cfi_def_cfa_offset 56 + 5355 0004 0446 mov r4, r0 + 5356 0006 0D46 mov r5, r1 +2186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 5357 .loc 1 2186 3 is_stmt 1 view .LVU1997 +2187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_StatusTypeDef status = HAL_OK; + 5358 .loc 1 2187 3 view .LVU1998 +2188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5359 .loc 1 2188 3 view .LVU1999 + 5360 .LVL405: +2191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5361 .loc 1 2191 3 view .LVU2000 +2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5362 .loc 1 2194 3 view .LVU2001 +2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5363 .loc 1 2194 14 is_stmt 0 view .LVU2002 + 5364 0008 0323 movs r3, #3 + 5365 000a 80F83430 strb r3, [r0, #52] +2196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5366 .loc 1 2196 3 is_stmt 1 view .LVU2003 +2196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5367 .loc 1 2196 17 is_stmt 0 view .LVU2004 + 5368 000e 436C ldr r3, [r0, #68] +2196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5369 .loc 1 2196 5 view .LVU2005 + 5370 0010 032B cmp r3, #3 + 5371 0012 1CD0 beq .L293 +2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5372 .loc 1 2198 5 is_stmt 1 view .LVU2006 +2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5373 .loc 1 2198 7 is_stmt 0 view .LVU2007 + 5374 0014 B1F5805F cmp r1, #4096 + 5375 0018 08D0 beq .L302 +2202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5376 .loc 1 2202 10 is_stmt 1 view .LVU2008 +2202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5377 .loc 1 2202 12 is_stmt 0 view .LVU2009 + 5378 001a B1F5006F cmp r1, #2048 + 5379 001e 0AD0 beq .L303 +2208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5380 .loc 1 2208 10 is_stmt 1 view .LVU2010 +2208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5381 .loc 1 2208 12 is_stmt 0 view .LVU2011 + 5382 0020 79B1 cbz r1, .L304 +2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5383 .loc 1 2217 7 is_stmt 1 view .LVU2012 +2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5384 .loc 1 2217 10 is_stmt 0 view .LVU2013 + 5385 0022 836B ldr r3, [r0, #56] + ARM GAS /tmp/ccMMu31U.s page 185 + + +2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5386 .loc 1 2217 22 view .LVU2014 + 5387 0024 43F00063 orr r3, r3, #134217728 + 5388 0028 8363 str r3, [r0, #56] + 5389 002a 14E0 b .L295 + 5390 .L302: +2200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5391 .loc 1 2200 7 is_stmt 1 view .LVU2015 +2200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5392 .loc 1 2200 10 is_stmt 0 view .LVU2016 + 5393 002c 836B ldr r3, [r0, #56] +2200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5394 .loc 1 2200 22 view .LVU2017 + 5395 002e 43F08053 orr r3, r3, #268435456 + 5396 0032 8363 str r3, [r0, #56] + 5397 0034 0FE0 b .L295 + 5398 .L303: +2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5399 .loc 1 2204 7 is_stmt 1 view .LVU2018 +2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5400 .loc 1 2204 20 is_stmt 0 view .LVU2019 + 5401 0036 FFF7FEFF bl SD_WideBus_Enable + 5402 .LVL406: +2206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5403 .loc 1 2206 7 is_stmt 1 view .LVU2020 +2206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5404 .loc 1 2206 10 is_stmt 0 view .LVU2021 + 5405 003a A36B ldr r3, [r4, #56] +2206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5406 .loc 1 2206 22 view .LVU2022 + 5407 003c 0343 orrs r3, r3, r0 + 5408 003e A363 str r3, [r4, #56] + 5409 0040 09E0 b .L295 + 5410 .LVL407: + 5411 .L304: +2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5412 .loc 1 2210 7 is_stmt 1 view .LVU2023 +2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5413 .loc 1 2210 20 is_stmt 0 view .LVU2024 + 5414 0042 FFF7FEFF bl SD_WideBus_Disable + 5415 .LVL408: +2212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5416 .loc 1 2212 7 is_stmt 1 view .LVU2025 +2212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5417 .loc 1 2212 10 is_stmt 0 view .LVU2026 + 5418 0046 A36B ldr r3, [r4, #56] +2212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5419 .loc 1 2212 22 view .LVU2027 + 5420 0048 0343 orrs r3, r3, r0 + 5421 004a A363 str r3, [r4, #56] + 5422 004c 03E0 b .L295 + 5423 .LVL409: + 5424 .L293: +2223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5425 .loc 1 2223 5 is_stmt 1 view .LVU2028 +2223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5426 .loc 1 2223 8 is_stmt 0 view .LVU2029 + ARM GAS /tmp/ccMMu31U.s page 186 + + + 5427 004e 836B ldr r3, [r0, #56] +2223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5428 .loc 1 2223 20 view .LVU2030 + 5429 0050 43F08053 orr r3, r3, #268435456 + 5430 0054 8363 str r3, [r0, #56] + 5431 .LVL410: + 5432 .L295: +2226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5433 .loc 1 2226 3 is_stmt 1 view .LVU2031 +2226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5434 .loc 1 2226 9 is_stmt 0 view .LVU2032 + 5435 0056 A36B ldr r3, [r4, #56] +2226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5436 .loc 1 2226 5 view .LVU2033 + 5437 0058 C3B1 cbz r3, .L298 +2229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 5438 .loc 1 2229 5 is_stmt 1 view .LVU2034 + 5439 005a 2368 ldr r3, [r4] + 5440 005c 174A ldr r2, .L305 + 5441 005e 9A63 str r2, [r3, #56] +2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; + 5442 .loc 1 2230 5 view .LVU2035 +2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; + 5443 .loc 1 2230 16 is_stmt 0 view .LVU2036 + 5444 0060 0125 movs r5, #1 + 5445 .LVL411: +2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; + 5446 .loc 1 2230 16 view .LVU2037 + 5447 0062 84F83450 strb r5, [r4, #52] +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5448 .loc 1 2231 5 is_stmt 1 view .LVU2038 + 5449 .LVL412: + 5450 .L299: +2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 5451 .loc 1 2246 3 view .LVU2039 +2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 5452 .loc 1 2246 16 is_stmt 0 view .LVU2040 + 5453 0066 4FF40071 mov r1, #512 + 5454 006a 2068 ldr r0, [r4] + 5455 006c FFF7FEFF bl SDMMC_CmdBlockLength + 5456 .LVL413: +2247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5457 .loc 1 2247 3 is_stmt 1 view .LVU2041 +2247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5458 .loc 1 2247 5 is_stmt 0 view .LVU2042 + 5459 0070 30B1 cbz r0, .L300 +2250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->ErrorCode |= errorstate; + 5460 .loc 1 2250 5 is_stmt 1 view .LVU2043 + 5461 0072 2368 ldr r3, [r4] + 5462 0074 1149 ldr r1, .L305 + 5463 0076 9963 str r1, [r3, #56] +2251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; + 5464 .loc 1 2251 5 view .LVU2044 +2251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; + 5465 .loc 1 2251 8 is_stmt 0 view .LVU2045 + 5466 0078 A36B ldr r3, [r4, #56] +2251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** status = HAL_ERROR; + ARM GAS /tmp/ccMMu31U.s page 187 + + + 5467 .loc 1 2251 20 view .LVU2046 + 5468 007a 0343 orrs r3, r3, r0 + 5469 007c A363 str r3, [r4, #56] +2252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5470 .loc 1 2252 5 is_stmt 1 view .LVU2047 + 5471 .LVL414: +2252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5472 .loc 1 2252 12 is_stmt 0 view .LVU2048 + 5473 007e 0125 movs r5, #1 + 5474 .LVL415: + 5475 .L300: +2256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5476 .loc 1 2256 3 is_stmt 1 view .LVU2049 +2256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5477 .loc 1 2256 14 is_stmt 0 view .LVU2050 + 5478 0080 0123 movs r3, #1 + 5479 0082 84F83430 strb r3, [r4, #52] +2258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5480 .loc 1 2258 3 is_stmt 1 view .LVU2051 +2259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5481 .loc 1 2259 1 is_stmt 0 view .LVU2052 + 5482 0086 2846 mov r0, r5 + 5483 .LVL416: +2259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5484 .loc 1 2259 1 view .LVU2053 + 5485 0088 0BB0 add sp, sp, #44 + 5486 .LCFI68: + 5487 .cfi_remember_state + 5488 .cfi_def_cfa_offset 12 + 5489 @ sp needed + 5490 008a 30BD pop {r4, r5, pc} + 5491 .LVL417: + 5492 .L298: + 5493 .LCFI69: + 5494 .cfi_restore_state +2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockBypass = hsd->Init.ClockBypass; + 5495 .loc 1 2236 5 is_stmt 1 view .LVU2054 +2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockBypass = hsd->Init.ClockBypass; + 5496 .loc 1 2236 41 is_stmt 0 view .LVU2055 + 5497 008c 6368 ldr r3, [r4, #4] +2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockBypass = hsd->Init.ClockBypass; + 5498 .loc 1 2236 30 view .LVU2056 + 5499 008e 0493 str r3, [sp, #16] +2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockPowerSave = hsd->Init.ClockPowerSave; + 5500 .loc 1 2237 5 is_stmt 1 view .LVU2057 +2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockPowerSave = hsd->Init.ClockPowerSave; + 5501 .loc 1 2237 41 is_stmt 0 view .LVU2058 + 5502 0090 A368 ldr r3, [r4, #8] +2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockPowerSave = hsd->Init.ClockPowerSave; + 5503 .loc 1 2237 30 view .LVU2059 + 5504 0092 0593 str r3, [sp, #20] +2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.BusWide = WideMode; + 5505 .loc 1 2238 5 is_stmt 1 view .LVU2060 +2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.BusWide = WideMode; + 5506 .loc 1 2238 41 is_stmt 0 view .LVU2061 + 5507 0094 E368 ldr r3, [r4, #12] +2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.BusWide = WideMode; + ARM GAS /tmp/ccMMu31U.s page 188 + + + 5508 .loc 1 2238 30 view .LVU2062 + 5509 0096 0693 str r3, [sp, #24] +2239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; + 5510 .loc 1 2239 5 is_stmt 1 view .LVU2063 +2239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; + 5511 .loc 1 2239 30 is_stmt 0 view .LVU2064 + 5512 0098 0795 str r5, [sp, #28] +2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockDiv = hsd->Init.ClockDiv; + 5513 .loc 1 2240 5 is_stmt 1 view .LVU2065 +2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockDiv = hsd->Init.ClockDiv; + 5514 .loc 1 2240 41 is_stmt 0 view .LVU2066 + 5515 009a 6369 ldr r3, [r4, #20] +2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** Init.ClockDiv = hsd->Init.ClockDiv; + 5516 .loc 1 2240 30 view .LVU2067 + 5517 009c 0893 str r3, [sp, #32] +2241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_Init(hsd->Instance, Init); + 5518 .loc 1 2241 5 is_stmt 1 view .LVU2068 +2241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_Init(hsd->Instance, Init); + 5519 .loc 1 2241 41 is_stmt 0 view .LVU2069 + 5520 009e A369 ldr r3, [r4, #24] +2241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** (void)SDMMC_Init(hsd->Instance, Init); + 5521 .loc 1 2241 30 view .LVU2070 + 5522 00a0 0993 str r3, [sp, #36] +2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5523 .loc 1 2242 5 is_stmt 1 view .LVU2071 +2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5524 .loc 1 2242 11 is_stmt 0 view .LVU2072 + 5525 00a2 0AAB add r3, sp, #40 + 5526 00a4 13E90700 ldmdb r3, {r0, r1, r2} + 5527 00a8 8DE80700 stm sp, {r0, r1, r2} + 5528 00ac 04AB add r3, sp, #16 + 5529 00ae 0ECB ldm r3, {r1, r2, r3} + 5530 00b0 2068 ldr r0, [r4] + 5531 00b2 FFF7FEFF bl SDMMC_Init + 5532 .LVL418: +2188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5533 .loc 1 2188 21 view .LVU2073 + 5534 00b6 0025 movs r5, #0 + 5535 .LVL419: +2188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5536 .loc 1 2188 21 view .LVU2074 + 5537 00b8 D5E7 b .L299 + 5538 .L306: + 5539 00ba 00BF .align 2 + 5540 .L305: + 5541 00bc FF054000 .word 4195839 + 5542 .cfi_endproc + 5543 .LFE164: + 5545 .section .text.HAL_SD_GetCardState,"ax",%progbits + 5546 .align 1 + 5547 .global HAL_SD_GetCardState + 5548 .syntax unified + 5549 .thumb + 5550 .thumb_func + 5552 HAL_SD_GetCardState: + 5553 .LVL420: + 5554 .LFB165: + ARM GAS /tmp/ccMMu31U.s page 189 + + +2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t cardstate; + 5555 .loc 1 2267 1 is_stmt 1 view -0 + 5556 .cfi_startproc + 5557 @ args = 0, pretend = 0, frame = 8 + 5558 @ frame_needed = 0, uses_anonymous_args = 0 +2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t cardstate; + 5559 .loc 1 2267 1 is_stmt 0 view .LVU2076 + 5560 0000 10B5 push {r4, lr} + 5561 .LCFI70: + 5562 .cfi_def_cfa_offset 8 + 5563 .cfi_offset 4, -8 + 5564 .cfi_offset 14, -4 + 5565 0002 82B0 sub sp, sp, #8 + 5566 .LCFI71: + 5567 .cfi_def_cfa_offset 16 + 5568 0004 0446 mov r4, r0 +2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 5569 .loc 1 2268 3 is_stmt 1 view .LVU2077 +2269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t resp1 = 0; + 5570 .loc 1 2269 3 view .LVU2078 +2270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5571 .loc 1 2270 3 view .LVU2079 +2270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5572 .loc 1 2270 12 is_stmt 0 view .LVU2080 + 5573 0006 0023 movs r3, #0 + 5574 0008 0193 str r3, [sp, #4] +2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 5575 .loc 1 2272 3 is_stmt 1 view .LVU2081 +2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 5576 .loc 1 2272 16 is_stmt 0 view .LVU2082 + 5577 000a 01A9 add r1, sp, #4 + 5578 000c FFF7FEFF bl SD_SendStatus + 5579 .LVL421: +2273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5580 .loc 1 2273 3 is_stmt 1 view .LVU2083 +2273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5581 .loc 1 2273 5 is_stmt 0 view .LVU2084 + 5582 0010 10B1 cbz r0, .L308 +2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5583 .loc 1 2275 5 is_stmt 1 view .LVU2085 +2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5584 .loc 1 2275 8 is_stmt 0 view .LVU2086 + 5585 0012 A36B ldr r3, [r4, #56] +2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5586 .loc 1 2275 20 view .LVU2087 + 5587 0014 0343 orrs r3, r3, r0 + 5588 0016 A363 str r3, [r4, #56] + 5589 .L308: +2278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5590 .loc 1 2278 3 is_stmt 1 view .LVU2088 + 5591 .LVL422: +2280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5592 .loc 1 2280 3 view .LVU2089 +2281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5593 .loc 1 2281 1 is_stmt 0 view .LVU2090 + 5594 0018 0198 ldr r0, [sp, #4] + 5595 .LVL423: + ARM GAS /tmp/ccMMu31U.s page 190 + + +2281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5596 .loc 1 2281 1 view .LVU2091 + 5597 001a C0F34320 ubfx r0, r0, #9, #4 + 5598 .LVL424: +2281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5599 .loc 1 2281 1 view .LVU2092 + 5600 001e 02B0 add sp, sp, #8 + 5601 .LCFI72: + 5602 .cfi_def_cfa_offset 8 + 5603 @ sp needed + 5604 0020 10BD pop {r4, pc} +2281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5605 .loc 1 2281 1 view .LVU2093 + 5606 .cfi_endproc + 5607 .LFE165: + 5609 .section .text.SD_DMAError,"ax",%progbits + 5610 .align 1 + 5611 .syntax unified + 5612 .thumb + 5613 .thumb_func + 5615 SD_DMAError: + 5616 .LVL425: + 5617 .LFB170: +2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + 5618 .loc 1 2496 1 is_stmt 1 view -0 + 5619 .cfi_startproc + 5620 @ args = 0, pretend = 0, frame = 0 + 5621 @ frame_needed = 0, uses_anonymous_args = 0 +2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + 5622 .loc 1 2496 1 is_stmt 0 view .LVU2095 + 5623 0000 10B5 push {r4, lr} + 5624 .LCFI73: + 5625 .cfi_def_cfa_offset 8 + 5626 .cfi_offset 4, -8 + 5627 .cfi_offset 14, -4 +2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardStateTypeDef CardState; + 5628 .loc 1 2497 3 is_stmt 1 view .LVU2096 +2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardStateTypeDef CardState; + 5629 .loc 1 2497 21 is_stmt 0 view .LVU2097 + 5630 0002 846B ldr r4, [r0, #56] + 5631 .LVL426: +2498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t RxErrorCode, TxErrorCode; + 5632 .loc 1 2498 3 is_stmt 1 view .LVU2098 +2499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5633 .loc 1 2499 3 view .LVU2099 +2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5634 .loc 1 2502 3 view .LVU2100 +2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5635 .loc 1 2502 6 is_stmt 0 view .LVU2101 + 5636 0004 FFF7FEFF bl HAL_DMA_GetError + 5637 .LVL427: +2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5638 .loc 1 2502 5 discriminator 1 view .LVU2102 + 5639 0008 0228 cmp r0, #2 + 5640 000a 0AD0 beq .L310 +2504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** TxErrorCode = hsd->hdmatx->ErrorCode; + 5641 .loc 1 2504 5 is_stmt 1 view .LVU2103 + ARM GAS /tmp/ccMMu31U.s page 191 + + +2504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** TxErrorCode = hsd->hdmatx->ErrorCode; + 5642 .loc 1 2504 22 is_stmt 0 view .LVU2104 + 5643 000c 236C ldr r3, [r4, #64] +2504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** TxErrorCode = hsd->hdmatx->ErrorCode; + 5644 .loc 1 2504 17 view .LVU2105 + 5645 000e 5A6D ldr r2, [r3, #84] + 5646 .LVL428: +2505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE)) + 5647 .loc 1 2505 5 is_stmt 1 view .LVU2106 +2505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE)) + 5648 .loc 1 2505 22 is_stmt 0 view .LVU2107 + 5649 0010 E36B ldr r3, [r4, #60] +2505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE)) + 5650 .loc 1 2505 17 view .LVU2108 + 5651 0012 5B6D ldr r3, [r3, #84] + 5652 .LVL429: +2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5653 .loc 1 2506 5 is_stmt 1 view .LVU2109 +2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5654 .loc 1 2506 7 is_stmt 0 view .LVU2110 + 5655 0014 012B cmp r3, #1 + 5656 0016 18BF it ne + 5657 0018 012A cmpne r2, #1 + 5658 001a 03D0 beq .L315 + 5659 .LVL430: + 5660 .L312: +2529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif + 5661 .loc 1 2529 5 is_stmt 1 view .LVU2111 + 5662 001c 2046 mov r0, r4 + 5663 001e FFF7FEFF bl HAL_SD_ErrorCallback + 5664 .LVL431: + 5665 .L310: +2532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5666 .loc 1 2532 1 is_stmt 0 view .LVU2112 + 5667 0022 10BD pop {r4, pc} + 5668 .LVL432: + 5669 .L315: +2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5670 .loc 1 2509 7 is_stmt 1 view .LVU2113 + 5671 0024 2368 ldr r3, [r4] + 5672 .LVL433: +2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5673 .loc 1 2509 7 is_stmt 0 view .LVU2114 + 5674 0026 0F4A ldr r2, .L317 + 5675 .LVL434: +2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5676 .loc 1 2509 7 view .LVU2115 + 5677 0028 9A63 str r2, [r3, #56] +2512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + 5678 .loc 1 2512 7 is_stmt 1 view .LVU2116 + 5679 002a 2268 ldr r2, [r4] + 5680 002c D36B ldr r3, [r2, #60] + 5681 002e 23F49D73 bic r3, r3, #314 + 5682 0032 D363 str r3, [r2, #60] +2515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** CardState = HAL_SD_GetCardState(hsd); + 5683 .loc 1 2515 7 view .LVU2117 +2515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** CardState = HAL_SD_GetCardState(hsd); + ARM GAS /tmp/ccMMu31U.s page 192 + + + 5684 .loc 1 2515 10 is_stmt 0 view .LVU2118 + 5685 0034 A36B ldr r3, [r4, #56] +2515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** CardState = HAL_SD_GetCardState(hsd); + 5686 .loc 1 2515 22 view .LVU2119 + 5687 0036 43F08043 orr r3, r3, #1073741824 + 5688 003a A363 str r3, [r4, #56] +2516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + 5689 .loc 1 2516 7 is_stmt 1 view .LVU2120 +2516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + 5690 .loc 1 2516 19 is_stmt 0 view .LVU2121 + 5691 003c 2046 mov r0, r4 + 5692 003e FFF7FEFF bl HAL_SD_GetCardState + 5693 .LVL435: +2517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5694 .loc 1 2517 7 is_stmt 1 view .LVU2122 +2517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5695 .loc 1 2517 47 is_stmt 0 view .LVU2123 + 5696 0042 0538 subs r0, r0, #5 + 5697 .LVL436: +2517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5698 .loc 1 2517 9 view .LVU2124 + 5699 0044 0128 cmp r0, #1 + 5700 0046 05D9 bls .L316 + 5701 .LVL437: + 5702 .L313: +2522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 5703 .loc 1 2522 7 is_stmt 1 view .LVU2125 +2522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 5704 .loc 1 2522 17 is_stmt 0 view .LVU2126 + 5705 0048 0123 movs r3, #1 + 5706 004a 84F83430 strb r3, [r4, #52] +2523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5707 .loc 1 2523 7 is_stmt 1 view .LVU2127 +2523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5708 .loc 1 2523 20 is_stmt 0 view .LVU2128 + 5709 004e 0023 movs r3, #0 + 5710 0050 2363 str r3, [r4, #48] + 5711 0052 E3E7 b .L312 + 5712 .LVL438: + 5713 .L316: +2519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5714 .loc 1 2519 9 is_stmt 1 view .LVU2129 +2519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5715 .loc 1 2519 27 is_stmt 0 view .LVU2130 + 5716 0054 2068 ldr r0, [r4] + 5717 .LVL439: +2519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5718 .loc 1 2519 27 view .LVU2131 + 5719 0056 FFF7FEFF bl SDMMC_CmdStopTransfer + 5720 .LVL440: +2519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5721 .loc 1 2519 12 discriminator 1 view .LVU2132 + 5722 005a A36B ldr r3, [r4, #56] +2519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5723 .loc 1 2519 24 discriminator 1 view .LVU2133 + 5724 005c 0343 orrs r3, r3, r0 + 5725 005e A363 str r3, [r4, #56] + ARM GAS /tmp/ccMMu31U.s page 193 + + + 5726 0060 F2E7 b .L313 + 5727 .L318: + 5728 0062 00BF .align 2 + 5729 .L317: + 5730 0064 FF054000 .word 4195839 + 5731 .cfi_endproc + 5732 .LFE170: + 5734 .section .text.SD_DMATxAbort,"ax",%progbits + 5735 .align 1 + 5736 .syntax unified + 5737 .thumb + 5738 .thumb_func + 5740 SD_DMATxAbort: + 5741 .LVL441: + 5742 .LFB171: +2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + 5743 .loc 1 2540 1 is_stmt 1 view -0 + 5744 .cfi_startproc + 5745 @ args = 0, pretend = 0, frame = 0 + 5746 @ frame_needed = 0, uses_anonymous_args = 0 +2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + 5747 .loc 1 2540 1 is_stmt 0 view .LVU2135 + 5748 0000 10B5 push {r4, lr} + 5749 .LCFI74: + 5750 .cfi_def_cfa_offset 8 + 5751 .cfi_offset 4, -8 + 5752 .cfi_offset 14, -4 +2541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardStateTypeDef CardState; + 5753 .loc 1 2541 3 is_stmt 1 view .LVU2136 +2541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardStateTypeDef CardState; + 5754 .loc 1 2541 21 is_stmt 0 view .LVU2137 + 5755 0002 846B ldr r4, [r0, #56] + 5756 .LVL442: +2542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5757 .loc 1 2542 3 is_stmt 1 view .LVU2138 +2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5758 .loc 1 2545 3 view .LVU2139 + 5759 0004 2368 ldr r3, [r4] + 5760 0006 40F23A52 movw r2, #1338 + 5761 000a 9A63 str r2, [r3, #56] +2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 5762 .loc 1 2547 3 view .LVU2140 +2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 5763 .loc 1 2547 15 is_stmt 0 view .LVU2141 + 5764 000c 2046 mov r0, r4 + 5765 .LVL443: +2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 5766 .loc 1 2547 15 view .LVU2142 + 5767 000e FFF7FEFF bl HAL_SD_GetCardState + 5768 .LVL444: +2548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 5769 .loc 1 2548 3 is_stmt 1 view .LVU2143 +2548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 5770 .loc 1 2548 14 is_stmt 0 view .LVU2144 + 5771 0012 0123 movs r3, #1 + 5772 0014 84F83430 strb r3, [r4, #52] +2549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + ARM GAS /tmp/ccMMu31U.s page 194 + + + 5773 .loc 1 2549 3 is_stmt 1 view .LVU2145 +2549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + 5774 .loc 1 2549 16 is_stmt 0 view .LVU2146 + 5775 0018 0023 movs r3, #0 + 5776 001a 2363 str r3, [r4, #48] +2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5777 .loc 1 2550 3 is_stmt 1 view .LVU2147 +2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5778 .loc 1 2550 43 is_stmt 0 view .LVU2148 + 5779 001c 0538 subs r0, r0, #5 + 5780 .LVL445: +2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5781 .loc 1 2550 5 view .LVU2149 + 5782 001e 0128 cmp r0, #1 + 5783 0020 05D9 bls .L324 + 5784 .LVL446: + 5785 .L320: +2555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5786 .loc 1 2555 3 is_stmt 1 view .LVU2150 +2555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5787 .loc 1 2555 9 is_stmt 0 view .LVU2151 + 5788 0022 A36B ldr r3, [r4, #56] +2555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5789 .loc 1 2555 5 view .LVU2152 + 5790 0024 53B9 cbnz r3, .L321 +2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif + 5791 .loc 1 2560 5 is_stmt 1 view .LVU2153 + 5792 0026 2046 mov r0, r4 + 5793 0028 FFF7FEFF bl HAL_SD_AbortCallback + 5794 .LVL447: + 5795 .L319: +2571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5796 .loc 1 2571 1 is_stmt 0 view .LVU2154 + 5797 002c 10BD pop {r4, pc} + 5798 .LVL448: + 5799 .L324: +2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5800 .loc 1 2552 5 is_stmt 1 view .LVU2155 +2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5801 .loc 1 2552 23 is_stmt 0 view .LVU2156 + 5802 002e 2068 ldr r0, [r4] + 5803 .LVL449: +2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5804 .loc 1 2552 23 view .LVU2157 + 5805 0030 FFF7FEFF bl SDMMC_CmdStopTransfer + 5806 .LVL450: +2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5807 .loc 1 2552 8 discriminator 1 view .LVU2158 + 5808 0034 A36B ldr r3, [r4, #56] +2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5809 .loc 1 2552 20 discriminator 1 view .LVU2159 + 5810 0036 0343 orrs r3, r3, r0 + 5811 0038 A363 str r3, [r4, #56] + 5812 003a F2E7 b .L320 + 5813 .L321: +2568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif + 5814 .loc 1 2568 5 is_stmt 1 view .LVU2160 + ARM GAS /tmp/ccMMu31U.s page 195 + + + 5815 003c 2046 mov r0, r4 + 5816 003e FFF7FEFF bl HAL_SD_ErrorCallback + 5817 .LVL451: +2571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5818 .loc 1 2571 1 is_stmt 0 view .LVU2161 + 5819 0042 F3E7 b .L319 + 5820 .cfi_endproc + 5821 .LFE171: + 5823 .section .text.SD_DMARxAbort,"ax",%progbits + 5824 .align 1 + 5825 .syntax unified + 5826 .thumb + 5827 .thumb_func + 5829 SD_DMARxAbort: + 5830 .LVL452: + 5831 .LFB172: +2579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + 5832 .loc 1 2579 1 is_stmt 1 view -0 + 5833 .cfi_startproc + 5834 @ args = 0, pretend = 0, frame = 0 + 5835 @ frame_needed = 0, uses_anonymous_args = 0 +2579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + 5836 .loc 1 2579 1 is_stmt 0 view .LVU2163 + 5837 0000 10B5 push {r4, lr} + 5838 .LCFI75: + 5839 .cfi_def_cfa_offset 8 + 5840 .cfi_offset 4, -8 + 5841 .cfi_offset 14, -4 +2580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardStateTypeDef CardState; + 5842 .loc 1 2580 3 is_stmt 1 view .LVU2164 +2580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardStateTypeDef CardState; + 5843 .loc 1 2580 21 is_stmt 0 view .LVU2165 + 5844 0002 846B ldr r4, [r0, #56] + 5845 .LVL453: +2581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5846 .loc 1 2581 3 is_stmt 1 view .LVU2166 +2584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5847 .loc 1 2584 3 view .LVU2167 + 5848 0004 2368 ldr r3, [r4] + 5849 0006 40F23A52 movw r2, #1338 + 5850 000a 9A63 str r2, [r3, #56] +2586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 5851 .loc 1 2586 3 view .LVU2168 +2586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 5852 .loc 1 2586 15 is_stmt 0 view .LVU2169 + 5853 000c 2046 mov r0, r4 + 5854 .LVL454: +2586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 5855 .loc 1 2586 15 view .LVU2170 + 5856 000e FFF7FEFF bl HAL_SD_GetCardState + 5857 .LVL455: +2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 5858 .loc 1 2587 3 is_stmt 1 view .LVU2171 +2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 5859 .loc 1 2587 14 is_stmt 0 view .LVU2172 + 5860 0012 0123 movs r3, #1 + 5861 0014 84F83430 strb r3, [r4, #52] + ARM GAS /tmp/ccMMu31U.s page 196 + + +2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + 5862 .loc 1 2588 3 is_stmt 1 view .LVU2173 +2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + 5863 .loc 1 2588 16 is_stmt 0 view .LVU2174 + 5864 0018 0023 movs r3, #0 + 5865 001a 2363 str r3, [r4, #48] +2589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5866 .loc 1 2589 3 is_stmt 1 view .LVU2175 +2589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5867 .loc 1 2589 43 is_stmt 0 view .LVU2176 + 5868 001c 0538 subs r0, r0, #5 + 5869 .LVL456: +2589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5870 .loc 1 2589 5 view .LVU2177 + 5871 001e 0128 cmp r0, #1 + 5872 0020 05D9 bls .L330 + 5873 .LVL457: + 5874 .L326: +2594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5875 .loc 1 2594 3 is_stmt 1 view .LVU2178 +2594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5876 .loc 1 2594 9 is_stmt 0 view .LVU2179 + 5877 0022 A36B ldr r3, [r4, #56] +2594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5878 .loc 1 2594 5 view .LVU2180 + 5879 0024 53B9 cbnz r3, .L327 +2599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif + 5880 .loc 1 2599 5 is_stmt 1 view .LVU2181 + 5881 0026 2046 mov r0, r4 + 5882 0028 FFF7FEFF bl HAL_SD_AbortCallback + 5883 .LVL458: + 5884 .L325: +2610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5885 .loc 1 2610 1 is_stmt 0 view .LVU2182 + 5886 002c 10BD pop {r4, pc} + 5887 .LVL459: + 5888 .L330: +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5889 .loc 1 2591 5 is_stmt 1 view .LVU2183 +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5890 .loc 1 2591 23 is_stmt 0 view .LVU2184 + 5891 002e 2068 ldr r0, [r4] + 5892 .LVL460: +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5893 .loc 1 2591 23 view .LVU2185 + 5894 0030 FFF7FEFF bl SDMMC_CmdStopTransfer + 5895 .LVL461: +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5896 .loc 1 2591 8 discriminator 1 view .LVU2186 + 5897 0034 A36B ldr r3, [r4, #56] +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 5898 .loc 1 2591 20 discriminator 1 view .LVU2187 + 5899 0036 0343 orrs r3, r3, r0 + 5900 0038 A363 str r3, [r4, #56] + 5901 003a F2E7 b .L326 + 5902 .L327: +2607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif + ARM GAS /tmp/ccMMu31U.s page 197 + + + 5903 .loc 1 2607 5 is_stmt 1 view .LVU2188 + 5904 003c 2046 mov r0, r4 + 5905 003e FFF7FEFF bl HAL_SD_ErrorCallback + 5906 .LVL462: +2610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5907 .loc 1 2610 1 is_stmt 0 view .LVU2189 + 5908 0042 F3E7 b .L325 + 5909 .cfi_endproc + 5910 .LFE172: + 5912 .section .text.HAL_SD_IRQHandler,"ax",%progbits + 5913 .align 1 + 5914 .global HAL_SD_IRQHandler + 5915 .syntax unified + 5916 .thumb + 5917 .thumb_func + 5919 HAL_SD_IRQHandler: + 5920 .LVL463: + 5921 .LFB153: +1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 5922 .loc 1 1485 1 is_stmt 1 view -0 + 5923 .cfi_startproc + 5924 @ args = 0, pretend = 0, frame = 0 + 5925 @ frame_needed = 0, uses_anonymous_args = 0 +1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t errorstate; + 5926 .loc 1 1485 1 is_stmt 0 view .LVU2191 + 5927 0000 38B5 push {r3, r4, r5, lr} + 5928 .LCFI76: + 5929 .cfi_def_cfa_offset 16 + 5930 .cfi_offset 3, -16 + 5931 .cfi_offset 4, -12 + 5932 .cfi_offset 5, -8 + 5933 .cfi_offset 14, -4 + 5934 0002 0446 mov r4, r0 +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t context = hsd->Context; + 5935 .loc 1 1486 3 is_stmt 1 view .LVU2192 +1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5936 .loc 1 1487 3 view .LVU2193 +1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5937 .loc 1 1487 12 is_stmt 0 view .LVU2194 + 5938 0004 056B ldr r5, [r0, #48] + 5939 .LVL464: +1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5940 .loc 1 1490 3 is_stmt 1 view .LVU2195 +1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5941 .loc 1 1490 7 is_stmt 0 view .LVU2196 + 5942 0006 0368 ldr r3, [r0] + 5943 0008 5A6B ldr r2, [r3, #52] +1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5944 .loc 1 1490 5 view .LVU2197 + 5945 000a 12F4004F tst r2, #32768 + 5946 000e 02D0 beq .L332 +1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5947 .loc 1 1490 61 discriminator 1 view .LVU2198 + 5948 0010 15F0080F tst r5, #8 + 5949 0014 26D1 bne .L348 + 5950 .L332: +1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + ARM GAS /tmp/ccMMu31U.s page 198 + + + 5951 .loc 1 1495 8 is_stmt 1 view .LVU2199 +1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5952 .loc 1 1495 11 is_stmt 0 view .LVU2200 + 5953 0016 5A6B ldr r2, [r3, #52] +1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5954 .loc 1 1495 10 view .LVU2201 + 5955 0018 12F4807F tst r2, #256 + 5956 001c 58D0 beq .L334 +1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5957 .loc 1 1497 5 is_stmt 1 view .LVU2202 + 5958 001e 4FF48072 mov r2, #256 + 5959 0022 9A63 str r2, [r3, #56] +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\ + 5960 .loc 1 1499 5 view .LVU2203 + 5961 0024 2268 ldr r2, [r4] + 5962 0026 D16B ldr r1, [r2, #60] + 5963 0028 644B ldr r3, .L354 + 5964 002a 0B40 ands r3, r3, r1 + 5965 002c D363 str r3, [r2, #60] +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5966 .loc 1 1503 5 view .LVU2204 +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5967 .loc 1 1503 8 is_stmt 0 view .LVU2205 + 5968 002e 2268 ldr r2, [r4] +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5969 .loc 1 1503 18 view .LVU2206 + 5970 0030 D36A ldr r3, [r2, #44] +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5971 .loc 1 1503 26 view .LVU2207 + 5972 0032 23F00103 bic r3, r3, #1 + 5973 0036 D362 str r3, [r2, #44] +1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5974 .loc 1 1505 5 is_stmt 1 view .LVU2208 +1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5975 .loc 1 1505 7 is_stmt 0 view .LVU2209 + 5976 0038 15F0080F tst r5, #8 + 5977 003c 26D0 beq .L335 +1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5978 .loc 1 1507 7 is_stmt 1 view .LVU2210 +1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5979 .loc 1 1507 9 is_stmt 0 view .LVU2211 + 5980 003e 15F0220F tst r5, #34 + 5981 0042 12D1 bne .L349 + 5982 .LVL465: + 5983 .L336: +1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 5984 .loc 1 1522 7 is_stmt 1 view .LVU2212 + 5985 0044 2368 ldr r3, [r4] + 5986 0046 40F23A52 movw r2, #1338 + 5987 004a 9A63 str r2, [r3, #56] +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 5988 .loc 1 1524 7 view .LVU2213 +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 5989 .loc 1 1524 18 is_stmt 0 view .LVU2214 + 5990 004c 0123 movs r3, #1 + 5991 004e 84F83430 strb r3, [r4, #52] +1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_B + ARM GAS /tmp/ccMMu31U.s page 199 + + + 5992 .loc 1 1525 7 is_stmt 1 view .LVU2215 +1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_B + 5993 .loc 1 1525 20 is_stmt 0 view .LVU2216 + 5994 0052 0023 movs r3, #0 + 5995 0054 2363 str r3, [r4, #48] +1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5996 .loc 1 1526 7 is_stmt 1 view .LVU2217 +1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 5997 .loc 1 1526 9 is_stmt 0 view .LVU2218 + 5998 0056 15F0030F tst r5, #3 + 5999 005a 13D0 beq .L337 +1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + 6000 .loc 1 1531 9 is_stmt 1 view .LVU2219 + 6001 005c 2046 mov r0, r4 + 6002 005e FFF7FEFF bl HAL_SD_RxCpltCallback + 6003 .LVL466: + 6004 0062 01E0 b .L331 + 6005 .LVL467: + 6006 .L348: +1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6007 .loc 1 1492 5 view .LVU2220 + 6008 0064 FFF7FEFF bl SD_Read_IT + 6009 .LVL468: + 6010 .L331: +1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6011 .loc 1 1668 1 is_stmt 0 view .LVU2221 + 6012 0068 38BD pop {r3, r4, r5, pc} + 6013 .LVL469: + 6014 .L349: +1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 6015 .loc 1 1509 9 is_stmt 1 view .LVU2222 +1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 6016 .loc 1 1509 22 is_stmt 0 view .LVU2223 + 6017 006a 2068 ldr r0, [r4] + 6018 .LVL470: +1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 6019 .loc 1 1509 22 view .LVU2224 + 6020 006c FFF7FEFF bl SDMMC_CmdStopTransfer + 6021 .LVL471: +1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6022 .loc 1 1510 9 is_stmt 1 view .LVU2225 +1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6023 .loc 1 1510 11 is_stmt 0 view .LVU2226 + 6024 0070 0346 mov r3, r0 + 6025 0072 0028 cmp r0, #0 + 6026 0074 E6D0 beq .L336 +1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + 6027 .loc 1 1512 11 is_stmt 1 view .LVU2227 +1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + 6028 .loc 1 1512 14 is_stmt 0 view .LVU2228 + 6029 0076 A26B ldr r2, [r4, #56] +1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + 6030 .loc 1 1512 26 view .LVU2229 + 6031 0078 1343 orrs r3, r3, r2 + 6032 007a A363 str r3, [r4, #56] +1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + 6033 .loc 1 1516 11 is_stmt 1 view .LVU2230 + ARM GAS /tmp/ccMMu31U.s page 200 + + + 6034 007c 2046 mov r0, r4 + 6035 .LVL472: +1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + 6036 .loc 1 1516 11 is_stmt 0 view .LVU2231 + 6037 007e FFF7FEFF bl HAL_SD_ErrorCallback + 6038 .LVL473: + 6039 0082 DFE7 b .L336 + 6040 .LVL474: + 6041 .L337: +1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + 6042 .loc 1 1539 9 is_stmt 1 view .LVU2232 + 6043 0084 2046 mov r0, r4 + 6044 0086 FFF7FEFF bl HAL_SD_TxCpltCallback + 6045 .LVL475: + 6046 008a EDE7 b .L331 + 6047 .LVL476: + 6048 .L335: +1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6049 .loc 1 1543 10 view .LVU2233 +1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6050 .loc 1 1543 12 is_stmt 0 view .LVU2234 + 6051 008c 15F0800F tst r5, #128 + 6052 0090 EAD0 beq .L331 +1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6053 .loc 1 1545 7 is_stmt 1 view .LVU2235 +1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6054 .loc 1 1545 9 is_stmt 0 view .LVU2236 + 6055 0092 15F0200F tst r5, #32 + 6056 0096 0ED1 bne .L350 + 6057 .LVL477: + 6058 .L338: +1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6059 .loc 1 1558 7 is_stmt 1 view .LVU2237 +1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6060 .loc 1 1558 9 is_stmt 0 view .LVU2238 + 6061 0098 15F0030F tst r5, #3 + 6062 009c E4D1 bne .L331 +1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6063 .loc 1 1562 9 is_stmt 1 view .LVU2239 +1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6064 .loc 1 1562 12 is_stmt 0 view .LVU2240 + 6065 009e 2268 ldr r2, [r4] +1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6066 .loc 1 1562 22 view .LVU2241 + 6067 00a0 D36A ldr r3, [r2, #44] +1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6068 .loc 1 1562 30 view .LVU2242 + 6069 00a2 23F00803 bic r3, r3, #8 + 6070 00a6 D362 str r3, [r2, #44] +1564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6071 .loc 1 1564 9 is_stmt 1 view .LVU2243 +1564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6072 .loc 1 1564 20 is_stmt 0 view .LVU2244 + 6073 00a8 0123 movs r3, #1 + 6074 00aa 84F83430 strb r3, [r4, #52] +1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + 6075 .loc 1 1569 9 is_stmt 1 view .LVU2245 + ARM GAS /tmp/ccMMu31U.s page 201 + + + 6076 00ae 2046 mov r0, r4 + 6077 00b0 FFF7FEFF bl HAL_SD_TxCpltCallback + 6078 .LVL478: + 6079 00b4 D8E7 b .L331 + 6080 .LVL479: + 6081 .L350: +1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 6082 .loc 1 1547 9 view .LVU2246 +1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 6083 .loc 1 1547 22 is_stmt 0 view .LVU2247 + 6084 00b6 2068 ldr r0, [r4] + 6085 .LVL480: +1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(errorstate != HAL_SD_ERROR_NONE) + 6086 .loc 1 1547 22 view .LVU2248 + 6087 00b8 FFF7FEFF bl SDMMC_CmdStopTransfer + 6088 .LVL481: +1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6089 .loc 1 1548 9 is_stmt 1 view .LVU2249 +1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6090 .loc 1 1548 11 is_stmt 0 view .LVU2250 + 6091 00bc 0346 mov r3, r0 + 6092 00be 0028 cmp r0, #0 + 6093 00c0 EAD0 beq .L338 +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + 6094 .loc 1 1550 11 is_stmt 1 view .LVU2251 +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + 6095 .loc 1 1550 14 is_stmt 0 view .LVU2252 + 6096 00c2 A26B ldr r2, [r4, #56] +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + 6097 .loc 1 1550 26 view .LVU2253 + 6098 00c4 1343 orrs r3, r3, r2 + 6099 00c6 A363 str r3, [r4, #56] +1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + 6100 .loc 1 1554 11 is_stmt 1 view .LVU2254 + 6101 00c8 2046 mov r0, r4 + 6102 .LVL482: +1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + 6103 .loc 1 1554 11 is_stmt 0 view .LVU2255 + 6104 00ca FFF7FEFF bl HAL_SD_ErrorCallback + 6105 .LVL483: + 6106 00ce E3E7 b .L338 + 6107 .LVL484: + 6108 .L334: +1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6109 .loc 1 1579 8 is_stmt 1 view .LVU2256 +1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6110 .loc 1 1579 12 is_stmt 0 view .LVU2257 + 6111 00d0 5A6B ldr r2, [r3, #52] +1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6112 .loc 1 1579 10 view .LVU2258 + 6113 00d2 12F4804F tst r2, #16384 + 6114 00d6 02D0 beq .L339 +1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6115 .loc 1 1579 66 discriminator 1 view .LVU2259 + 6116 00d8 15F0080F tst r5, #8 + 6117 00dc 4AD1 bne .L351 + 6118 .L339: + ARM GAS /tmp/ccMMu31U.s page 202 + + +1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6119 .loc 1 1584 8 is_stmt 1 view .LVU2260 +1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6120 .loc 1 1584 11 is_stmt 0 view .LVU2261 + 6121 00de 5A6B ldr r2, [r3, #52] +1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6122 .loc 1 1584 10 view .LVU2262 + 6123 00e0 12F03A0F tst r2, #58 + 6124 00e4 C0D0 beq .L331 +1587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6125 .loc 1 1587 5 is_stmt 1 view .LVU2263 +1587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6126 .loc 1 1587 8 is_stmt 0 view .LVU2264 + 6127 00e6 5A6B ldr r2, [r3, #52] +1587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6128 .loc 1 1587 7 view .LVU2265 + 6129 00e8 12F0020F tst r2, #2 + 6130 00ec 03D0 beq .L340 +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6131 .loc 1 1589 7 is_stmt 1 view .LVU2266 +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6132 .loc 1 1589 10 is_stmt 0 view .LVU2267 + 6133 00ee A26B ldr r2, [r4, #56] +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6134 .loc 1 1589 22 view .LVU2268 + 6135 00f0 42F00202 orr r2, r2, #2 + 6136 00f4 A263 str r2, [r4, #56] + 6137 .L340: +1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6138 .loc 1 1591 5 is_stmt 1 view .LVU2269 +1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6139 .loc 1 1591 8 is_stmt 0 view .LVU2270 + 6140 00f6 5A6B ldr r2, [r3, #52] +1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6141 .loc 1 1591 7 view .LVU2271 + 6142 00f8 12F0080F tst r2, #8 + 6143 00fc 03D0 beq .L341 +1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6144 .loc 1 1593 7 is_stmt 1 view .LVU2272 +1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6145 .loc 1 1593 10 is_stmt 0 view .LVU2273 + 6146 00fe A26B ldr r2, [r4, #56] +1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6147 .loc 1 1593 22 view .LVU2274 + 6148 0100 42F00802 orr r2, r2, #8 + 6149 0104 A263 str r2, [r4, #56] + 6150 .L341: +1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6151 .loc 1 1595 5 is_stmt 1 view .LVU2275 +1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6152 .loc 1 1595 8 is_stmt 0 view .LVU2276 + 6153 0106 5A6B ldr r2, [r3, #52] +1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6154 .loc 1 1595 7 view .LVU2277 + 6155 0108 12F0200F tst r2, #32 + 6156 010c 03D0 beq .L342 +1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + ARM GAS /tmp/ccMMu31U.s page 203 + + + 6157 .loc 1 1597 7 is_stmt 1 view .LVU2278 +1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6158 .loc 1 1597 10 is_stmt 0 view .LVU2279 + 6159 010e A26B ldr r2, [r4, #56] +1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6160 .loc 1 1597 22 view .LVU2280 + 6161 0110 42F02002 orr r2, r2, #32 + 6162 0114 A263 str r2, [r4, #56] + 6163 .L342: +1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6164 .loc 1 1599 5 is_stmt 1 view .LVU2281 +1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6165 .loc 1 1599 8 is_stmt 0 view .LVU2282 + 6166 0116 5A6B ldr r2, [r3, #52] +1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6167 .loc 1 1599 7 view .LVU2283 + 6168 0118 12F0100F tst r2, #16 + 6169 011c 03D0 beq .L343 +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6170 .loc 1 1601 7 is_stmt 1 view .LVU2284 +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6171 .loc 1 1601 10 is_stmt 0 view .LVU2285 + 6172 011e A26B ldr r2, [r4, #56] +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6173 .loc 1 1601 22 view .LVU2286 + 6174 0120 42F01002 orr r2, r2, #16 + 6175 0124 A263 str r2, [r4, #56] + 6176 .L343: +1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6177 .loc 1 1605 5 is_stmt 1 view .LVU2287 + 6178 0126 40F23A52 movw r2, #1338 + 6179 012a 9A63 str r2, [r3, #56] +1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + 6180 .loc 1 1608 5 view .LVU2288 + 6181 012c 2268 ldr r2, [r4] + 6182 012e D36B ldr r3, [r2, #60] + 6183 0130 23F49D73 bic r3, r3, #314 + 6184 0134 D363 str r3, [r2, #60] +1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6185 .loc 1 1611 5 view .LVU2289 +1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6186 .loc 1 1611 23 is_stmt 0 view .LVU2290 + 6187 0136 2068 ldr r0, [r4] + 6188 .LVL485: +1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6189 .loc 1 1611 23 view .LVU2291 + 6190 0138 FFF7FEFF bl SDMMC_CmdStopTransfer + 6191 .LVL486: +1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6192 .loc 1 1611 8 discriminator 1 view .LVU2292 + 6193 013c A36B ldr r3, [r4, #56] +1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6194 .loc 1 1611 20 discriminator 1 view .LVU2293 + 6195 013e 0343 orrs r3, r3, r0 + 6196 0140 A363 str r3, [r4, #56] +1613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6197 .loc 1 1613 5 is_stmt 1 view .LVU2294 + ARM GAS /tmp/ccMMu31U.s page 204 + + +1613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6198 .loc 1 1613 7 is_stmt 0 view .LVU2295 + 6199 0142 15F0080F tst r5, #8 + 6200 0146 19D1 bne .L352 +1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6201 .loc 1 1624 10 is_stmt 1 view .LVU2296 +1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6202 .loc 1 1624 12 is_stmt 0 view .LVU2297 + 6203 0148 15F0800F tst r5, #128 + 6204 014c 8CD0 beq .L331 +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6205 .loc 1 1627 7 is_stmt 1 view .LVU2298 +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6206 .loc 1 1627 9 is_stmt 0 view .LVU2299 + 6207 014e 15F0300F tst r5, #48 + 6208 0152 1CD1 bne .L353 +1637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6209 .loc 1 1637 12 is_stmt 1 view .LVU2300 +1637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6210 .loc 1 1637 14 is_stmt 0 view .LVU2301 + 6211 0154 15F0030F tst r5, #3 + 6212 0158 26D0 beq .L346 +1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Abort DMA in IT mode */ + 6213 .loc 1 1640 9 is_stmt 1 view .LVU2302 +1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Abort DMA in IT mode */ + 6214 .loc 1 1640 12 is_stmt 0 view .LVU2303 + 6215 015a 236C ldr r3, [r4, #64] +1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Abort DMA in IT mode */ + 6216 .loc 1 1640 40 view .LVU2304 + 6217 015c 184A ldr r2, .L354+4 + 6218 015e 1A65 str r2, [r3, #80] +1642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6219 .loc 1 1642 9 is_stmt 1 view .LVU2305 +1642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6220 .loc 1 1642 12 is_stmt 0 view .LVU2306 + 6221 0160 206C ldr r0, [r4, #64] + 6222 0162 FFF7FEFF bl HAL_DMA_Abort_IT + 6223 .LVL487: +1642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6224 .loc 1 1642 11 discriminator 1 view .LVU2307 + 6225 0166 0028 cmp r0, #0 + 6226 0168 3FF47EAF beq .L331 +1644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6227 .loc 1 1644 11 is_stmt 1 view .LVU2308 + 6228 016c 206C ldr r0, [r4, #64] + 6229 016e FFF7FEFF bl SD_DMARxAbort + 6230 .LVL488: + 6231 0172 79E7 b .L331 + 6232 .LVL489: + 6233 .L351: +1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6234 .loc 1 1581 5 view .LVU2309 + 6235 0174 2046 mov r0, r4 + 6236 .LVL490: +1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6237 .loc 1 1581 5 is_stmt 0 view .LVU2310 + 6238 0176 FFF7FEFF bl SD_Write_IT + ARM GAS /tmp/ccMMu31U.s page 205 + + + 6239 .LVL491: + 6240 017a 75E7 b .L331 + 6241 .L352: +1616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 6242 .loc 1 1616 7 is_stmt 1 view .LVU2311 +1616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 6243 .loc 1 1616 18 is_stmt 0 view .LVU2312 + 6244 017c 0123 movs r3, #1 + 6245 017e 84F83430 strb r3, [r4, #52] +1617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + 6246 .loc 1 1617 7 is_stmt 1 view .LVU2313 +1617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + 6247 .loc 1 1617 20 is_stmt 0 view .LVU2314 + 6248 0182 0023 movs r3, #0 + 6249 0184 2363 str r3, [r4, #48] +1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + 6250 .loc 1 1621 7 is_stmt 1 view .LVU2315 + 6251 0186 2046 mov r0, r4 + 6252 0188 FFF7FEFF bl HAL_SD_ErrorCallback + 6253 .LVL492: + 6254 018c 6CE7 b .L331 + 6255 .L353: +1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Abort DMA in IT mode */ + 6256 .loc 1 1630 9 view .LVU2316 +1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Abort DMA in IT mode */ + 6257 .loc 1 1630 12 is_stmt 0 view .LVU2317 + 6258 018e E36B ldr r3, [r4, #60] +1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** /* Abort DMA in IT mode */ + 6259 .loc 1 1630 40 view .LVU2318 + 6260 0190 0C4A ldr r2, .L354+8 + 6261 0192 1A65 str r2, [r3, #80] +1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6262 .loc 1 1632 9 is_stmt 1 view .LVU2319 +1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6263 .loc 1 1632 12 is_stmt 0 view .LVU2320 + 6264 0194 E06B ldr r0, [r4, #60] + 6265 0196 FFF7FEFF bl HAL_DMA_Abort_IT + 6266 .LVL493: +1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6267 .loc 1 1632 11 discriminator 1 view .LVU2321 + 6268 019a 0028 cmp r0, #0 + 6269 019c 3FF464AF beq .L331 +1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6270 .loc 1 1634 11 is_stmt 1 view .LVU2322 + 6271 01a0 E06B ldr r0, [r4, #60] + 6272 01a2 FFF7FEFF bl SD_DMATxAbort + 6273 .LVL494: + 6274 01a6 5FE7 b .L331 + 6275 .L346: +1649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 6276 .loc 1 1649 9 view .LVU2323 +1649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 6277 .loc 1 1649 24 is_stmt 0 view .LVU2324 + 6278 01a8 0023 movs r3, #0 + 6279 01aa A363 str r3, [r4, #56] +1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 6280 .loc 1 1650 9 is_stmt 1 view .LVU2325 + ARM GAS /tmp/ccMMu31U.s page 206 + + +1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 6281 .loc 1 1650 20 is_stmt 0 view .LVU2326 + 6282 01ac 0122 movs r2, #1 + 6283 01ae 84F83420 strb r2, [r4, #52] +1651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + 6284 .loc 1 1651 9 is_stmt 1 view .LVU2327 +1651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + 6285 .loc 1 1651 22 is_stmt 0 view .LVU2328 + 6286 01b2 2363 str r3, [r4, #48] +1655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + 6287 .loc 1 1655 9 is_stmt 1 view .LVU2329 + 6288 01b4 2046 mov r0, r4 + 6289 01b6 FFF7FEFF bl HAL_SD_AbortCallback + 6290 .LVL495: +1667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6291 .loc 1 1667 3 view .LVU2330 +1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6292 .loc 1 1668 1 is_stmt 0 view .LVU2331 + 6293 01ba 55E7 b .L331 + 6294 .L355: + 6295 .align 2 + 6296 .L354: + 6297 01bc C53EFFFF .word -49467 + 6298 01c0 00000000 .word SD_DMARxAbort + 6299 01c4 00000000 .word SD_DMATxAbort + 6300 .cfi_endproc + 6301 .LFE153: + 6303 .section .text.HAL_SD_Abort,"ax",%progbits + 6304 .align 1 + 6305 .global HAL_SD_Abort + 6306 .syntax unified + 6307 .thumb + 6308 .thumb_func + 6310 HAL_SD_Abort: + 6311 .LVL496: + 6312 .LFB166: +2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardStateTypeDef CardState; + 6313 .loc 1 2290 1 is_stmt 1 view -0 + 6314 .cfi_startproc + 6315 @ args = 0, pretend = 0, frame = 0 + 6316 @ frame_needed = 0, uses_anonymous_args = 0 +2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardStateTypeDef CardState; + 6317 .loc 1 2290 1 is_stmt 0 view .LVU2333 + 6318 0000 10B5 push {r4, lr} + 6319 .LCFI77: + 6320 .cfi_def_cfa_offset 8 + 6321 .cfi_offset 4, -8 + 6322 .cfi_offset 14, -4 + 6323 0002 0446 mov r4, r0 +2291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t context = hsd->Context; + 6324 .loc 1 2291 3 is_stmt 1 view .LVU2334 +2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6325 .loc 1 2292 3 view .LVU2335 +2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6326 .loc 1 2292 12 is_stmt 0 view .LVU2336 + 6327 0004 016B ldr r1, [r0, #48] + 6328 .LVL497: + ARM GAS /tmp/ccMMu31U.s page 207 + + +2295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + 6329 .loc 1 2295 3 is_stmt 1 view .LVU2337 + 6330 0006 0268 ldr r2, [r0] + 6331 0008 D36B ldr r3, [r2, #60] + 6332 000a 23F49D73 bic r3, r3, #314 + 6333 000e D363 str r3, [r2, #60] +2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6334 .loc 1 2299 3 view .LVU2338 + 6335 0010 0368 ldr r3, [r0] + 6336 0012 40F23A52 movw r2, #1338 + 6337 0016 9A63 str r2, [r3, #56] +2301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6338 .loc 1 2301 3 view .LVU2339 + 6339 0018 0268 ldr r2, [r0] + 6340 001a D36A ldr r3, [r2, #44] + 6341 001c 23F00103 bic r3, r3, #1 + 6342 0020 D362 str r3, [r2, #44] +2303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6343 .loc 1 2303 3 view .LVU2340 +2303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6344 .loc 1 2303 6 is_stmt 0 view .LVU2341 + 6345 0022 11F0800F tst r1, #128 + 6346 0026 0AD0 beq .L357 +2306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6347 .loc 1 2306 5 is_stmt 1 view .LVU2342 +2306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6348 .loc 1 2306 8 is_stmt 0 view .LVU2343 + 6349 0028 0268 ldr r2, [r0] +2306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6350 .loc 1 2306 18 view .LVU2344 + 6351 002a D36A ldr r3, [r2, #44] +2306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6352 .loc 1 2306 26 view .LVU2345 + 6353 002c 23F00803 bic r3, r3, #8 + 6354 0030 D362 str r3, [r2, #44] +2309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6355 .loc 1 2309 5 is_stmt 1 view .LVU2346 +2309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6356 .loc 1 2309 8 is_stmt 0 view .LVU2347 + 6357 0032 11F0300F tst r1, #48 + 6358 0036 11D1 bne .L363 +2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6359 .loc 1 2317 10 is_stmt 1 view .LVU2348 +2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6360 .loc 1 2317 13 is_stmt 0 view .LVU2349 + 6361 0038 11F0030F tst r1, #3 + 6362 003c 18D1 bne .L364 + 6363 .LVL498: + 6364 .L357: +2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6365 .loc 1 2327 5 is_stmt 1 view .LVU2350 +2330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6366 .loc 1 2330 3 view .LVU2351 +2330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6367 .loc 1 2330 14 is_stmt 0 view .LVU2352 + 6368 003e 0123 movs r3, #1 + 6369 0040 84F83430 strb r3, [r4, #52] + ARM GAS /tmp/ccMMu31U.s page 208 + + +2333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6370 .loc 1 2333 3 is_stmt 1 view .LVU2353 +2333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6371 .loc 1 2333 16 is_stmt 0 view .LVU2354 + 6372 0044 0023 movs r3, #0 + 6373 0046 2363 str r3, [r4, #48] +2335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + 6374 .loc 1 2335 3 is_stmt 1 view .LVU2355 +2335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + 6375 .loc 1 2335 15 is_stmt 0 view .LVU2356 + 6376 0048 2046 mov r0, r4 + 6377 004a FFF7FEFF bl HAL_SD_GetCardState + 6378 .LVL499: +2336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6379 .loc 1 2336 3 is_stmt 1 view .LVU2357 +2336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6380 .loc 1 2336 43 is_stmt 0 view .LVU2358 + 6381 004e 0538 subs r0, r0, #5 + 6382 .LVL500: +2336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6383 .loc 1 2336 5 view .LVU2359 + 6384 0050 0128 cmp r0, #1 + 6385 0052 17D9 bls .L365 + 6386 .LVL501: + 6387 .L359: +2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6388 .loc 1 2340 3 is_stmt 1 view .LVU2360 +2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6389 .loc 1 2340 9 is_stmt 0 view .LVU2361 + 6390 0054 A36B ldr r3, [r4, #56] +2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6391 .loc 1 2340 5 view .LVU2362 + 6392 0056 D3B9 cbnz r3, .L361 +2344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6393 .loc 1 2344 10 view .LVU2363 + 6394 0058 0020 movs r0, #0 + 6395 .L360: +2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6396 .loc 1 2345 1 view .LVU2364 + 6397 005a 10BD pop {r4, pc} + 6398 .LVL502: + 6399 .L363: +2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6400 .loc 1 2311 7 is_stmt 1 view .LVU2365 +2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6401 .loc 1 2311 10 is_stmt 0 view .LVU2366 + 6402 005c C06B ldr r0, [r0, #60] + 6403 .LVL503: +2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6404 .loc 1 2311 10 view .LVU2367 + 6405 005e FFF7FEFF bl HAL_DMA_Abort + 6406 .LVL504: +2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6407 .loc 1 2311 9 discriminator 1 view .LVU2368 + 6408 0062 0028 cmp r0, #0 + 6409 0064 EBD0 beq .L357 +2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + ARM GAS /tmp/ccMMu31U.s page 209 + + + 6410 .loc 1 2313 9 is_stmt 1 view .LVU2369 +2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6411 .loc 1 2313 12 is_stmt 0 view .LVU2370 + 6412 0066 A36B ldr r3, [r4, #56] +2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6413 .loc 1 2313 24 view .LVU2371 + 6414 0068 43F08043 orr r3, r3, #1073741824 + 6415 006c A363 str r3, [r4, #56] + 6416 006e E6E7 b .L357 + 6417 .LVL505: + 6418 .L364: +2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6419 .loc 1 2319 7 is_stmt 1 view .LVU2372 +2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6420 .loc 1 2319 10 is_stmt 0 view .LVU2373 + 6421 0070 006C ldr r0, [r0, #64] + 6422 .LVL506: +2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6423 .loc 1 2319 10 view .LVU2374 + 6424 0072 FFF7FEFF bl HAL_DMA_Abort + 6425 .LVL507: +2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6426 .loc 1 2319 9 discriminator 1 view .LVU2375 + 6427 0076 0028 cmp r0, #0 + 6428 0078 E1D0 beq .L357 +2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6429 .loc 1 2321 9 is_stmt 1 view .LVU2376 +2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6430 .loc 1 2321 12 is_stmt 0 view .LVU2377 + 6431 007a A36B ldr r3, [r4, #56] +2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6432 .loc 1 2321 24 view .LVU2378 + 6433 007c 43F08043 orr r3, r3, #1073741824 + 6434 0080 A363 str r3, [r4, #56] + 6435 0082 DCE7 b .L357 + 6436 .LVL508: + 6437 .L365: +2338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6438 .loc 1 2338 5 is_stmt 1 view .LVU2379 +2338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6439 .loc 1 2338 22 is_stmt 0 view .LVU2380 + 6440 0084 2068 ldr r0, [r4] + 6441 .LVL509: +2338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6442 .loc 1 2338 22 view .LVU2381 + 6443 0086 FFF7FEFF bl SDMMC_CmdStopTransfer + 6444 .LVL510: +2338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6445 .loc 1 2338 20 discriminator 1 view .LVU2382 + 6446 008a A063 str r0, [r4, #56] + 6447 008c E2E7 b .L359 + 6448 .L361: +2342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6449 .loc 1 2342 12 view .LVU2383 + 6450 008e 0120 movs r0, #1 + 6451 0090 E3E7 b .L360 + 6452 .cfi_endproc + ARM GAS /tmp/ccMMu31U.s page 210 + + + 6453 .LFE166: + 6455 .section .text.HAL_SD_Abort_IT,"ax",%progbits + 6456 .align 1 + 6457 .global HAL_SD_Abort_IT + 6458 .syntax unified + 6459 .thumb + 6460 .thumb_func + 6462 HAL_SD_Abort_IT: + 6463 .LVL511: + 6464 .LFB167: +2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardStateTypeDef CardState; + 6465 .loc 1 2354 1 is_stmt 1 view -0 + 6466 .cfi_startproc + 6467 @ args = 0, pretend = 0, frame = 0 + 6468 @ frame_needed = 0, uses_anonymous_args = 0 +2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** HAL_SD_CardStateTypeDef CardState; + 6469 .loc 1 2354 1 is_stmt 0 view .LVU2385 + 6470 0000 10B5 push {r4, lr} + 6471 .LCFI78: + 6472 .cfi_def_cfa_offset 8 + 6473 .cfi_offset 4, -8 + 6474 .cfi_offset 14, -4 + 6475 0002 0446 mov r4, r0 +2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** uint32_t context = hsd->Context; + 6476 .loc 1 2355 3 is_stmt 1 view .LVU2386 +2356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6477 .loc 1 2356 3 view .LVU2387 +2356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6478 .loc 1 2356 12 is_stmt 0 view .LVU2388 + 6479 0004 026B ldr r2, [r0, #48] + 6480 .LVL512: +2359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + 6481 .loc 1 2359 3 is_stmt 1 view .LVU2389 + 6482 0006 0168 ldr r1, [r0] + 6483 0008 CB6B ldr r3, [r1, #60] + 6484 000a 23F49D73 bic r3, r3, #314 + 6485 000e CB63 str r3, [r1, #60] +2362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6486 .loc 1 2362 3 view .LVU2390 + 6487 0010 0168 ldr r1, [r0] + 6488 0012 CB6A ldr r3, [r1, #44] + 6489 0014 23F00103 bic r3, r3, #1 + 6490 0018 CB62 str r3, [r1, #44] +2364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6491 .loc 1 2364 3 view .LVU2391 +2364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6492 .loc 1 2364 6 is_stmt 0 view .LVU2392 + 6493 001a 12F0800F tst r2, #128 + 6494 001e 22D0 beq .L367 +2367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6495 .loc 1 2367 5 is_stmt 1 view .LVU2393 +2367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6496 .loc 1 2367 8 is_stmt 0 view .LVU2394 + 6497 0020 0168 ldr r1, [r0] +2367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6498 .loc 1 2367 18 view .LVU2395 + 6499 0022 CB6A ldr r3, [r1, #44] + ARM GAS /tmp/ccMMu31U.s page 211 + + +2367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6500 .loc 1 2367 26 view .LVU2396 + 6501 0024 23F00803 bic r3, r3, #8 + 6502 0028 CB62 str r3, [r1, #44] +2370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6503 .loc 1 2370 5 is_stmt 1 view .LVU2397 +2370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6504 .loc 1 2370 8 is_stmt 0 view .LVU2398 + 6505 002a 12F0300F tst r2, #48 + 6506 002e 04D1 bne .L374 +2379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6507 .loc 1 2379 10 is_stmt 1 view .LVU2399 +2379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6508 .loc 1 2379 13 is_stmt 0 view .LVU2400 + 6509 0030 12F0030F tst r2, #3 + 6510 0034 0CD1 bne .L375 +2419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6511 .loc 1 2419 10 view .LVU2401 + 6512 0036 0020 movs r0, #0 + 6513 .LVL513: + 6514 .L369: +2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6515 .loc 1 2420 1 view .LVU2402 + 6516 0038 10BD pop {r4, pc} + 6517 .LVL514: + 6518 .L374: +2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) + 6519 .loc 1 2372 7 is_stmt 1 view .LVU2403 +2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) + 6520 .loc 1 2372 10 is_stmt 0 view .LVU2404 + 6521 003a C36B ldr r3, [r0, #60] +2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) + 6522 .loc 1 2372 38 view .LVU2405 + 6523 003c 184A ldr r2, .L378 + 6524 .LVL515: +2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) + 6525 .loc 1 2372 38 view .LVU2406 + 6526 003e 1A65 str r2, [r3, #80] +2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6527 .loc 1 2373 7 is_stmt 1 view .LVU2407 +2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6528 .loc 1 2373 10 is_stmt 0 view .LVU2408 + 6529 0040 C06B ldr r0, [r0, #60] + 6530 .LVL516: +2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6531 .loc 1 2373 10 view .LVU2409 + 6532 0042 FFF7FEFF bl HAL_DMA_Abort_IT + 6533 .LVL517: +2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6534 .loc 1 2373 9 discriminator 1 view .LVU2410 + 6535 0046 0028 cmp r0, #0 + 6536 0048 F6D0 beq .L369 +2375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6537 .loc 1 2375 9 is_stmt 1 view .LVU2411 +2375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6538 .loc 1 2375 21 is_stmt 0 view .LVU2412 + 6539 004a 0020 movs r0, #0 + ARM GAS /tmp/ccMMu31U.s page 212 + + + 6540 004c E063 str r0, [r4, #60] + 6541 004e F3E7 b .L369 + 6542 .LVL518: + 6543 .L375: +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) + 6544 .loc 1 2381 7 is_stmt 1 view .LVU2413 +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) + 6545 .loc 1 2381 10 is_stmt 0 view .LVU2414 + 6546 0050 036C ldr r3, [r0, #64] +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) + 6547 .loc 1 2381 38 view .LVU2415 + 6548 0052 144A ldr r2, .L378+4 + 6549 .LVL519: +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) + 6550 .loc 1 2381 38 view .LVU2416 + 6551 0054 1A65 str r2, [r3, #80] +2382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6552 .loc 1 2382 7 is_stmt 1 view .LVU2417 +2382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6553 .loc 1 2382 10 is_stmt 0 view .LVU2418 + 6554 0056 006C ldr r0, [r0, #64] + 6555 .LVL520: +2382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6556 .loc 1 2382 10 view .LVU2419 + 6557 0058 FFF7FEFF bl HAL_DMA_Abort_IT + 6558 .LVL521: +2382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6559 .loc 1 2382 9 discriminator 1 view .LVU2420 + 6560 005c 0028 cmp r0, #0 + 6561 005e EBD0 beq .L369 +2384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6562 .loc 1 2384 9 is_stmt 1 view .LVU2421 +2384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6563 .loc 1 2384 21 is_stmt 0 view .LVU2422 + 6564 0060 0020 movs r0, #0 + 6565 0062 2064 str r0, [r4, #64] + 6566 0064 E8E7 b .L369 + 6567 .LVL522: + 6568 .L367: +2396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6569 .loc 1 2396 5 is_stmt 1 view .LVU2423 + 6570 0066 0368 ldr r3, [r0] + 6571 0068 40F23A52 movw r2, #1338 + 6572 .LVL523: +2396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** + 6573 .loc 1 2396 5 is_stmt 0 view .LVU2424 + 6574 006c 9A63 str r2, [r3, #56] +2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 6575 .loc 1 2398 5 is_stmt 1 view .LVU2425 +2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->State = HAL_SD_STATE_READY; + 6576 .loc 1 2398 17 is_stmt 0 view .LVU2426 + 6577 006e FFF7FEFF bl HAL_SD_GetCardState + 6578 .LVL524: +2399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 6579 .loc 1 2399 5 is_stmt 1 view .LVU2427 +2399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** hsd->Context = SD_CONTEXT_NONE; + 6580 .loc 1 2399 16 is_stmt 0 view .LVU2428 + ARM GAS /tmp/ccMMu31U.s page 213 + + + 6581 0072 0123 movs r3, #1 + 6582 0074 84F83430 strb r3, [r4, #52] +2400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + 6583 .loc 1 2400 5 is_stmt 1 view .LVU2429 +2400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + 6584 .loc 1 2400 18 is_stmt 0 view .LVU2430 + 6585 0078 0023 movs r3, #0 + 6586 007a 2363 str r3, [r4, #48] +2401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6587 .loc 1 2401 5 is_stmt 1 view .LVU2431 +2401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6588 .loc 1 2401 45 is_stmt 0 view .LVU2432 + 6589 007c 0538 subs r0, r0, #5 + 6590 .LVL525: +2401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6591 .loc 1 2401 7 view .LVU2433 + 6592 007e 0128 cmp r0, #1 + 6593 0080 03D9 bls .L376 + 6594 .LVL526: + 6595 .L370: +2405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6596 .loc 1 2405 5 is_stmt 1 view .LVU2434 +2405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6597 .loc 1 2405 11 is_stmt 0 view .LVU2435 + 6598 0082 A36B ldr r3, [r4, #56] +2405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** { + 6599 .loc 1 2405 7 view .LVU2436 + 6600 0084 33B1 cbz r3, .L377 +2407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6601 .loc 1 2407 14 view .LVU2437 + 6602 0086 0120 movs r0, #1 + 6603 0088 D6E7 b .L369 + 6604 .LVL527: + 6605 .L376: +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6606 .loc 1 2403 7 is_stmt 1 view .LVU2438 +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6607 .loc 1 2403 24 is_stmt 0 view .LVU2439 + 6608 008a 2068 ldr r0, [r4] + 6609 .LVL528: +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6610 .loc 1 2403 24 view .LVU2440 + 6611 008c FFF7FEFF bl SDMMC_CmdStopTransfer + 6612 .LVL529: +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6613 .loc 1 2403 22 discriminator 1 view .LVU2441 + 6614 0090 A063 str r0, [r4, #56] + 6615 0092 F6E7 b .L370 + 6616 .L377: +2414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + 6617 .loc 1 2414 7 is_stmt 1 view .LVU2442 + 6618 0094 2046 mov r0, r4 + 6619 0096 FFF7FEFF bl HAL_SD_AbortCallback + 6620 .LVL530: +2419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c **** } + 6621 .loc 1 2419 10 is_stmt 0 view .LVU2443 + 6622 009a 0020 movs r0, #0 + ARM GAS /tmp/ccMMu31U.s page 214 + + + 6623 009c CCE7 b .L369 + 6624 .L379: + 6625 009e 00BF .align 2 + 6626 .L378: + 6627 00a0 00000000 .word SD_DMATxAbort + 6628 00a4 00000000 .word SD_DMARxAbort + 6629 .cfi_endproc + 6630 .LFE167: + 6632 .text + 6633 .Letext0: + 6634 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 6635 .file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 6636 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + 6637 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 6638 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h" + 6639 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h" + 6640 .file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h" + 6641 .file 9 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h" + ARM GAS /tmp/ccMMu31U.s page 215 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_sd.c + /tmp/ccMMu31U.s:20 .text.SD_DMATransmitCplt:00000000 $t + /tmp/ccMMu31U.s:25 .text.SD_DMATransmitCplt:00000000 SD_DMATransmitCplt + /tmp/ccMMu31U.s:51 .text.SD_PowerON:00000000 $t + /tmp/ccMMu31U.s:56 .text.SD_PowerON:00000000 SD_PowerON + /tmp/ccMMu31U.s:275 .text.SD_PowerON:000000bc $d + /tmp/ccMMu31U.s:280 .text.SD_PowerOFF:00000000 $t + /tmp/ccMMu31U.s:285 .text.SD_PowerOFF:00000000 SD_PowerOFF + /tmp/ccMMu31U.s:311 .text.SD_Read_IT:00000000 $t + /tmp/ccMMu31U.s:316 .text.SD_Read_IT:00000000 SD_Read_IT + /tmp/ccMMu31U.s:419 .text.SD_Write_IT:00000000 $t + /tmp/ccMMu31U.s:424 .text.SD_Write_IT:00000000 SD_Write_IT + /tmp/ccMMu31U.s:541 .text.SD_SendSDStatus:00000000 $t + /tmp/ccMMu31U.s:546 .text.SD_SendSDStatus:00000000 SD_SendSDStatus + /tmp/ccMMu31U.s:814 .text.SD_FindSCR:00000000 $t + /tmp/ccMMu31U.s:819 .text.SD_FindSCR:00000000 SD_FindSCR + /tmp/ccMMu31U.s:1083 .text.SD_WideBus_Enable:00000000 $t + /tmp/ccMMu31U.s:1088 .text.SD_WideBus_Enable:00000000 SD_WideBus_Enable + /tmp/ccMMu31U.s:1183 .text.SD_WideBus_Disable:00000000 $t + /tmp/ccMMu31U.s:1188 .text.SD_WideBus_Disable:00000000 SD_WideBus_Disable + /tmp/ccMMu31U.s:1283 .text.SD_SendStatus:00000000 $t + /tmp/ccMMu31U.s:1288 .text.SD_SendStatus:00000000 SD_SendStatus + /tmp/ccMMu31U.s:1353 .text.HAL_SD_MspInit:00000000 $t + /tmp/ccMMu31U.s:1359 .text.HAL_SD_MspInit:00000000 HAL_SD_MspInit + /tmp/ccMMu31U.s:1374 .text.HAL_SD_MspDeInit:00000000 $t + /tmp/ccMMu31U.s:1380 .text.HAL_SD_MspDeInit:00000000 HAL_SD_MspDeInit + /tmp/ccMMu31U.s:1395 .text.HAL_SD_DeInit:00000000 $t + /tmp/ccMMu31U.s:1401 .text.HAL_SD_DeInit:00000000 HAL_SD_DeInit + /tmp/ccMMu31U.s:1455 .text.HAL_SD_ReadBlocks:00000000 $t + /tmp/ccMMu31U.s:1461 .text.HAL_SD_ReadBlocks:00000000 HAL_SD_ReadBlocks + /tmp/ccMMu31U.s:2019 .text.HAL_SD_ReadBlocks:00000244 $d + /tmp/ccMMu31U.s:2024 .text.HAL_SD_WriteBlocks:00000000 $t + /tmp/ccMMu31U.s:2030 .text.HAL_SD_WriteBlocks:00000000 HAL_SD_WriteBlocks + /tmp/ccMMu31U.s:2517 .text.HAL_SD_WriteBlocks:000001fc $d + /tmp/ccMMu31U.s:2522 .text.HAL_SD_ReadBlocks_IT:00000000 $t + /tmp/ccMMu31U.s:2528 .text.HAL_SD_ReadBlocks_IT:00000000 HAL_SD_ReadBlocks_IT + /tmp/ccMMu31U.s:2751 .text.HAL_SD_ReadBlocks_IT:000000c8 $d + /tmp/ccMMu31U.s:2756 .text.HAL_SD_WriteBlocks_IT:00000000 $t + /tmp/ccMMu31U.s:2762 .text.HAL_SD_WriteBlocks_IT:00000000 HAL_SD_WriteBlocks_IT + /tmp/ccMMu31U.s:2985 .text.HAL_SD_WriteBlocks_IT:000000c0 $d + /tmp/ccMMu31U.s:2990 .text.HAL_SD_ReadBlocks_DMA:00000000 $t + /tmp/ccMMu31U.s:2996 .text.HAL_SD_ReadBlocks_DMA:00000000 HAL_SD_ReadBlocks_DMA + /tmp/ccMMu31U.s:3282 .text.HAL_SD_ReadBlocks_DMA:00000128 $d + /tmp/ccMMu31U.s:3972 .text.SD_DMAReceiveCplt:00000000 SD_DMAReceiveCplt + /tmp/ccMMu31U.s:5615 .text.SD_DMAError:00000000 SD_DMAError + /tmp/ccMMu31U.s:3289 .text.HAL_SD_WriteBlocks_DMA:00000000 $t + /tmp/ccMMu31U.s:3295 .text.HAL_SD_WriteBlocks_DMA:00000000 HAL_SD_WriteBlocks_DMA + /tmp/ccMMu31U.s:3586 .text.HAL_SD_WriteBlocks_DMA:00000124 $d + /tmp/ccMMu31U.s:3593 .text.HAL_SD_Erase:00000000 $t + /tmp/ccMMu31U.s:3599 .text.HAL_SD_Erase:00000000 HAL_SD_Erase + /tmp/ccMMu31U.s:3851 .text.HAL_SD_Erase:000000f4 $d + /tmp/ccMMu31U.s:3856 .text.HAL_SD_GetState:00000000 $t + /tmp/ccMMu31U.s:3862 .text.HAL_SD_GetState:00000000 HAL_SD_GetState + /tmp/ccMMu31U.s:3880 .text.HAL_SD_GetError:00000000 $t + /tmp/ccMMu31U.s:3886 .text.HAL_SD_GetError:00000000 HAL_SD_GetError + /tmp/ccMMu31U.s:3904 .text.HAL_SD_TxCpltCallback:00000000 $t + ARM GAS /tmp/ccMMu31U.s page 216 + + + /tmp/ccMMu31U.s:3910 .text.HAL_SD_TxCpltCallback:00000000 HAL_SD_TxCpltCallback + /tmp/ccMMu31U.s:3925 .text.HAL_SD_RxCpltCallback:00000000 $t + /tmp/ccMMu31U.s:3931 .text.HAL_SD_RxCpltCallback:00000000 HAL_SD_RxCpltCallback + /tmp/ccMMu31U.s:3946 .text.HAL_SD_ErrorCallback:00000000 $t + /tmp/ccMMu31U.s:3952 .text.HAL_SD_ErrorCallback:00000000 HAL_SD_ErrorCallback + /tmp/ccMMu31U.s:3967 .text.SD_DMAReceiveCplt:00000000 $t + /tmp/ccMMu31U.s:4055 .text.HAL_SD_AbortCallback:00000000 $t + /tmp/ccMMu31U.s:4061 .text.HAL_SD_AbortCallback:00000000 HAL_SD_AbortCallback + /tmp/ccMMu31U.s:4076 .text.HAL_SD_GetCardCID:00000000 $t + /tmp/ccMMu31U.s:4082 .text.HAL_SD_GetCardCID:00000000 HAL_SD_GetCardCID + /tmp/ccMMu31U.s:4167 .text.HAL_SD_GetCardCSD:00000000 $t + /tmp/ccMMu31U.s:4173 .text.HAL_SD_GetCardCSD:00000000 HAL_SD_GetCardCSD + /tmp/ccMMu31U.s:4547 .text.HAL_SD_GetCardCSD:000001b4 $d + /tmp/ccMMu31U.s:4552 .text.SD_InitCard:00000000 $t + /tmp/ccMMu31U.s:4557 .text.SD_InitCard:00000000 SD_InitCard + /tmp/ccMMu31U.s:4798 .text.HAL_SD_InitCard:00000000 $t + /tmp/ccMMu31U.s:4804 .text.HAL_SD_InitCard:00000000 HAL_SD_InitCard + /tmp/ccMMu31U.s:4977 .text.HAL_SD_InitCard:000000a4 $d + /tmp/ccMMu31U.s:4982 .text.HAL_SD_Init:00000000 $t + /tmp/ccMMu31U.s:4988 .text.HAL_SD_Init:00000000 HAL_SD_Init + /tmp/ccMMu31U.s:5078 .text.HAL_SD_GetCardStatus:00000000 $t + /tmp/ccMMu31U.s:5084 .text.HAL_SD_GetCardStatus:00000000 HAL_SD_GetCardStatus + /tmp/ccMMu31U.s:5263 .text.HAL_SD_GetCardStatus:000000a8 $d + /tmp/ccMMu31U.s:5268 .text.HAL_SD_GetCardInfo:00000000 $t + /tmp/ccMMu31U.s:5274 .text.HAL_SD_GetCardInfo:00000000 HAL_SD_GetCardInfo + /tmp/ccMMu31U.s:5332 .text.HAL_SD_ConfigWideBusOperation:00000000 $t + /tmp/ccMMu31U.s:5338 .text.HAL_SD_ConfigWideBusOperation:00000000 HAL_SD_ConfigWideBusOperation + /tmp/ccMMu31U.s:5541 .text.HAL_SD_ConfigWideBusOperation:000000bc $d + /tmp/ccMMu31U.s:5546 .text.HAL_SD_GetCardState:00000000 $t + /tmp/ccMMu31U.s:5552 .text.HAL_SD_GetCardState:00000000 HAL_SD_GetCardState + /tmp/ccMMu31U.s:5610 .text.SD_DMAError:00000000 $t + /tmp/ccMMu31U.s:5730 .text.SD_DMAError:00000064 $d + /tmp/ccMMu31U.s:5735 .text.SD_DMATxAbort:00000000 $t + /tmp/ccMMu31U.s:5740 .text.SD_DMATxAbort:00000000 SD_DMATxAbort + /tmp/ccMMu31U.s:5824 .text.SD_DMARxAbort:00000000 $t + /tmp/ccMMu31U.s:5829 .text.SD_DMARxAbort:00000000 SD_DMARxAbort + /tmp/ccMMu31U.s:5913 .text.HAL_SD_IRQHandler:00000000 $t + /tmp/ccMMu31U.s:5919 .text.HAL_SD_IRQHandler:00000000 HAL_SD_IRQHandler + /tmp/ccMMu31U.s:6297 .text.HAL_SD_IRQHandler:000001bc $d + /tmp/ccMMu31U.s:6304 .text.HAL_SD_Abort:00000000 $t + /tmp/ccMMu31U.s:6310 .text.HAL_SD_Abort:00000000 HAL_SD_Abort + /tmp/ccMMu31U.s:6456 .text.HAL_SD_Abort_IT:00000000 $t + /tmp/ccMMu31U.s:6462 .text.HAL_SD_Abort_IT:00000000 HAL_SD_Abort_IT + /tmp/ccMMu31U.s:6627 .text.HAL_SD_Abort_IT:000000a0 $d + +UNDEFINED SYMBOLS +SDMMC_CmdGoIdleState +SDMMC_CmdOperCond +SDMMC_CmdAppCommand +SDMMC_CmdAppOperCommand +SDMMC_GetResponse +SDMMC_PowerState_OFF +SDMMC_ReadFIFO +SDMMC_WriteFIFO +HAL_GetTick +SDMMC_CmdBlockLength +SDMMC_ConfigData + ARM GAS /tmp/ccMMu31U.s page 217 + + +SDMMC_CmdStatusRegister +SDMMC_CmdSendSCR +SDMMC_CmdBusWidth +SDMMC_CmdSendStatus +SDMMC_CmdReadMultiBlock +SDMMC_CmdReadSingleBlock +SDMMC_CmdStopTransfer +SDMMC_CmdWriteMultiBlock +SDMMC_CmdWriteSingleBlock +HAL_DMA_Start_IT +SDMMC_CmdSDEraseStartAdd +SDMMC_CmdSDEraseEndAdd +SDMMC_CmdErase +SDMMC_GetPowerState +SDMMC_CmdSendCSD +SDMMC_CmdSelDesel +SDMMC_Init +SDMMC_CmdSendCID +SDMMC_CmdSetRelAdd +SDMMC_PowerState_ON +HAL_Delay +HAL_DMA_GetError +HAL_DMA_Abort_IT +HAL_DMA_Abort diff --git a/build/stm32f7xx_hal_sd.o b/build/stm32f7xx_hal_sd.o new file mode 100644 index 0000000000000000000000000000000000000000..6ef4395d795d6647aa7e60530af634745b665951 GIT binary patch literal 75156 zcmeFa34B%6)i=D)J-IhGHzCPQ!aUtf5T+0UDr$gCgc(8-28RkE0|^O9ngm3v5Ws<| zty0uFv<0>GajJq=tF2a?I;hp49n?OxvD!v$wJ2C=Yvud@_g?4Tb1y-Cp7(j*@BMzi z@4&hLz1CiP@3q%nd+mMpxkx>^9sA=dRJOH8H68!>)8pQX)B|}Hp8Xw!#B5SFV4=k?DIR zZGn;YRU8a+pGx^t@0f}=`<)WWucRLCDf9GN*>&|l>{nUq>PJ^R(C@7{(9ins<>#im z`;|(4!vCPsdiozb_TVKOe!AiIM~*!)!2;uTZ%k_aA<6=l-}26&qfE#NL1SvFt6@o^@Nw-u1vDw-U>&J%1$DS$lN( zJ5BAZ=j~UE)@@z)X1Jcq_j@anD`-X3oSCP!NIk5!H6AJ!%7%6CYPqX!P2Yr#32{ck z;jQRfcKG;owWk;@ug&)C@nqY3RCe4RE8DxLxx&agC3=Q;N2N4}PWgSbO~9AI7&5P%aa_H(ubaPD32*-%rh!9LrVKDNOAg`2hMmr#HkN9G;jGe@ORa>|YG7`72TPndnK$IW)Ir z@Zpd*`w;q5y|d1`Dcxfq-DY!)g8}R4wvxoMvUk(!&RnZblJk|dH~0HmJ+phKO zPlaWB*8cO0);1@)HfOHI*4FXh_5*S7Pz%;Kx_K-7nC%^pIVB3#e$0L}9PRIzhkplB zAB?N8vwM!sD4?ZH4^(Jh-6h9nsMN=-P{+I}?;Ku6zfYyFLnIDWr1wfJz{c9ng1o$oJ+_PZPRl;*!;XJ3jsCpD?8*VeTlwy56C9^?JX-dzO$ zzvd+V|Kks=l#EwB*^}y~$&A?d$nTHE^~~(MyQS=~s=K?+8vl|>cimn0%Rb8``A+|& zriO(#)!p4MnjL*un+Z47*LOrKFZpdc~A6CYzi&dU3XVYdX%OG zeIul#-*($7r!PbJo+$pXzGUHtqWDRS8JuIr+T-KQ*i>_zW+H+-_V(ec)#Jy##fpA( zrOS^h#g9(w?Q!|h8$E76ntD<{irYg!^1_dNh$QiQ{D>t9d*bdi@shS5@@mNC8`d?} z&3D6-GOj6hdD6XMPr9=&HAiR< z4yo*&bw`FjvGK~%Sr~7|BD+atzPfJ5x(hu|uCtnc-ZKBgiRpIPb9Hr5k;MAOiBZI? zBG%N=uLiQS5km~^e;~Ul2z%Uy$Z#7pMRY4r$WQCrsiO+~H#f_F)ak z(`%v1{b#@NWv4IGd;JyHM*5L?OWmPif8KbYbjmAsCfZ2NY*OQ1SQlD%o~LnLsOe`d zHAX>&(u=*g*A#`{B&TGLFdZ1JUELO^?Un;csrdp)~NS)7B=J2JL;e zwjg?!{T%xBL`%uh>%RO%U1sZy`9C+G^_i`S4VkT1t_`(XO^Hp}hY#94O?Fx0+RUb9 z@6MaB?A;sfo@t?0MyVb|sr*A(O)qaKJM6b#UKc&azdROq&B;eO>(w2uk(!B79x{OS zhW4TMmh7X~VMmF1{}p`Boc~Jwn=Qi|Oh4fR`J-Rm=Nd=)K*0dL zSmqjm1ttw&E$_R=Rkp7`V#haIinDH7`$kKkDP7zDt4)bz>1(r^HhUiM_Y|I9(bq!j z$5-q+psfQPX`QqatiyQ{l%1>i7ItyYuGRR~tO}QRx$Jf9L1&h?AL5>I2=vorB zyz&%w2}52sv;C=7?ocxh*}C7Hkv(->Q5Xqo!o8OMqt6TbRHh2=y$2tnC9U3Vp3NS6 z(wN@UWiIW59Y-y=F>20F>C0{!YI=wrt~35weNLQcdc^eS29zBXQ#J)<{V_Z*_8&Ty zuJ$@EbOyVAH1X`yJg3uU@ylfTl;x-6L;H;n@%(`yRTGvF5~Lm z-+L?8?c3^1P9OGc*Bm>)AhDyY{i!1<*^7Eg+jq8)3~*n&Xzew}wiG0GUUO_)!J^J5 z+pjscvjF_;=hpTf>nV8Zh+Uo7ZBmKZi*}e)g`K#`%3icdVV9?rT~XThjg&w~Y1@-W zcCK64am}&yA?yoLV{zfL8dYJSOJyzWDs5F0iw|Gc)6-V`_fI-K@Ai0JX)AsAn$AG&YbgEXy1=GA z$J$X}yl3Gia!RYN(72=YS&dH?1~vzpt-`Y#{9D!Gc;zYBQG9m8?qmLgNrzLCtdRO= z(%~B#iUaCjo)2GZz!Oa8h(^}aQ@C(5@uz8506mAdd7j-oqWz_m!1*KEpFC31xlrSd zbysNIS@o>O;;QY(LLn8}ek@ZxaI6!0S)T33vO+9#uyFgaY@O;sDo3Y^k;>I6h158m z+Mc!j*m#|?kje{<#Hdx++mB5su(G!wn^@2>&zcxK1Y5>=j$V|u|5%&ylm%+p$8UJf zZZLhgsbNIp&HbJxFIMUuEv1Kh_w-^zDDO+uCFmkc%k)9t{T)=@4Zu=67psr z%G#I~r?SnQ@mAdM)p3L-0FI# z)u)g3sPFU-`XJ2;m(07d7f(Egdm8d8QgMEP)QW%f7d&_+_Z4`m^zQNP;ZATfc7lPs z)87#-?oNKr)G+LTg_S&Uf5BtkimayUrfi&%RIfF8q{}qz2{A63J{F(^W@n|@H}v%n z#Qk+YeC^Ao7M1rxZ+25$BuePgPxo`}xI;f{Au<%y9Wd*sscrQm`|3gx1yUcg&u8oJ z_w&ii3jMubse%W0>s@oRw&TGAlbUi-zdYmQ;3=z^?VEjX!GVcQqv0uc)LA+wR1rjP z)lE+x*`A)=@#K->^tz7pK=$F|cot5pyZQdQo|8Qr*RA#3{M!9lolhN!&sv91yXw}? zkxBMVhwf+T#IoDAKY8TR?AyAYJYr@2u}kGVs{2^hnz(jn>!P(!Vdb|sKDV}PV`A;j zjf-lZ+IVHH-S%89BaIoaLGsjD1`i$8d*Gv}XFXdwQs)eo}`jen52`Ck9v!##LL$N5i6 z@*&pnmfl;MHP_T_dj5)7l~JJ;N4`XfQivl{e?;*85EQ z0_pFj{)oLyzgqj>Y)L{Hv%h1R`uj|JO~1;SG7>j8J)h>2*B) z&;3e20jRt;!o2^KQQ24bN5sH45&x)@r^RY|4mgcWok> z-kS-2?|MJBWUnwMe^@=_;;OZ@Cjh~;=Ijm-720kPvQ0#;KNc0!|YqEgeg!yP*$bv+pM52pRE#4 zMbGT-I&@s1vIP0xb7+6!cYVme-Jz2bOA|ouj}y*P>cac4}e@ z3}|n2=#0d{qd#5cV81SL=)A=5GXGMCo}9Ra z?O*1UF9=lElqmahhn^8wKs)Sm1>YN*KPX@jH({*2b@e>4T`t4YkkXl z0nFslFuqEuo?8P~@c838;AA4<9dCU?iD#j%O8y6wu#zF9JjrjddS!nIJ-n0cUxRXr z6k6GkOP&GGP|0WG!&3IWXu*4m?MFsxfv+IpJtTs+!a03~Njo9p$yULSNS-2OT(C10 z-%czXk-LGWaU?mWttXQPT{YOp|L#K zalr;Edi5Au*ONUXcqSFyJ!U3q@noM8JV4<+W3zSHnZa?8@?DpCnkI{a*U%#06tXyY zh-GgSvOIVfO@FhH^Mk#t>f1st4)#Gs-(DdrgK@OTEn`fCs0rRk^0qNMp`0gsb?`qi z5q#eh@?4c3$EcDKH`tnnN{8?RyjjpWJuVl7T>>}p{fEbJW`UEg177N|_=1E-KnB;L zBk>V0@uDN~5iiL_bMX-``6g72pCzM}6l{X&Erj#dn1($*36&RSf*$bU{kIs}5>#vJm0Nfc1QMv`lUj0j|nA-Q?M z+u5;8BzJOf18n5KEMz>iKu;9^u22t@;k=>$`md1OnZYCqUzNE)H&hhd3+?=07qU1w zl)~49XiZOc`OvcJa^?R<=r#WqUzeh+6CiNVvTA*DLxaz=p+|)r7W@|*dQ8aS!7d8_ zM92}r-E8-9Ax8%L=$HqE92K0ys-6&XbZ{=UdQ!+SK_7*m5^`*?ntuAUkfC5ZbDt41 zGdPEC^iv_Tg2yTRGa<8s*Hf#X3z-vK&)i=KnHzkF{e4!*alu9o=yO7jA3C?JO!=P| zGB23Rs(vZtgy2ec{{UYr?ABwO) z*ukof2$>KZLh`7PfnXm8;UlRkDR?Ib;qQ{09GuT~KNb=}vzcc2hbI9o46}B?Z+u%l z>3V}>y$IeA#sK6zioV3ZWd|%q8|!`MFlG%QiR^FTGyV@wwjbK-Y~*Z$RQ&5s&Uh!s zDYyyB#{bF5E^)F^@NWp0zHN>!=P*Zf`6_x8|68ZbCRZ6gbHx9~$+_0aaT@z7hAsYA zPWA(_*>|IlzOQ?Rm_Gi})#6|j^j+-e@^>dk*BkkO(vy)D|9x8wI2iHTn29NbLRxE> z6~{gwa@05@EF`wf03-e-C;P0}Y@8yh_*b0lE+-rHzRP;=LF25*`kE_e2FtwYl)1;r zaqRLi#yGy$$$l<2`v#Ui=yZyUkm(dt=oEJd!>uCpJmF>Wk6~6H{pE*Fnc=9xaR?7e z#lPw_Hq*%&vJaJ^6W^u<-*B>5g|o#t)tKV(e{`}phqIZ2E-ku_1h`IopCfd=BZS&7 zrCJX=Cfe`HDMZQm$DEuOogBwR?^3PbJ5|0Pn|-T|?EiGK2Voi+6N%QhAt1#6&dDC{ zWJ95J%%u3&oSYI@&Rv+O@h>dU&qn0_^l;L5;QkKovE3Uxl+~J)#68T%V7!MrbSgeLsWPqQD9CY4 zMbsGi2Ux%=6|H7MrU?33FNL)#O`1rp>cKr1x6!KHXmuMHw~(o|DmPj^48}ubYSqe< zv}(Tw<2l?$wYf&M90ZaPxU*2d;v7@id#TMEi9tQPzyPIGGi0o{@VI2`^hRPnH97$9 z_i^X^4pv8*S)BeagYhEnF?kqr>&?XBoHw4`m7}-Pm~SO&WBwZgAK)H+7$4T34090# z=HVXw5+(m^n46Gp#yw^eCHoVT^i%Tg`D454I+gWy;vly93kW=cI}65Dhr!4lg#^9q zZs-hiTQgNw0a$eC+|@{M^8eiAK{u6k9y6hERud95L{=vftO_p~FoxECmqnI>dmPPK zJJTGC>`y$E7MTa*mEj(zwY%TZw!?J(0n??85NN=ii_(g7vl0m^S)g)5U~%L(XjY}C zTRY3e(1&05r23)RNO0vbB~*4RHQ64c-Yux#%1U?C+n#s|)q4lrKjAj&?Tk_H5~E%U zqa^OIdVf1ny#&;pX??DGg|Oan*wAWpsW%z=m(ip*hSh6KoJRFFf?J0>XA(vZWr{hr zkAv|bZezkGqvIeh0l2fEn&SE$%0hy+bgc4aSjhS$5OHH4-1t-!v7X3qtnx`enuDjBv8s`ZwKRBxQ!cs8i;n|;{ol)+$DaD+qkhZx}Ao2FdesTUAZ0!y7C^$q@!#AkNc0T z3z5*SybB4sa@O+>=U2i}Bj=%g>u&)Q60vHiACmDe)Muvp-vT-${tn#VQdI;j#UWMM zyYXRN=d$oYFg(b&-WlwazAm5x#X@i^aF5Xe^_u~+;oIFhdIIaX!5Fg>0!_F_e}@{} z5E!`=nU8_-0GT>^+-M|uAonSlI%;v1$qGS~t5H@F66EAAMuH}~7rMZb_U=}n%Iy&5 z6NbqNM?yVi_^!D_?RQgjtxQvM7 z_{3#osC{a&-2Ila4FW$i)^w=}u8 zBf(YnpCYmu>fH<8Ma=vW5^Q(~>>%nrEvyN`f_g6qt4LT-?-gM!6IPK5y$u%kLZ}C} zz}i?#3#W;D(hz%LGwTzS$SLB8qy_T1TYd`M$8nF<%Xmg$FvsDqV7!Za^dQt|4GxUF z6jRlUU~wEw9o^0wsniR)b#`0jPDTUeW0d-1gs0;!H>V+}quP;a;vRH+6jfP&Nib7~ zx)qXf!!Sp;za(hg_=H!5+vxUQg4S&t7#HI?rX`psCvfzZaTW5c7g33cxziH#YJEAl=i@fxFx`y9dtmgFc{L3( z!}KK!ij2UWMRoabnRTutayyZrRUbs{;!0W9fTvyhCM4+Zj!RFlR#CkV{1NrO0g;uQ zKdi*4_kq8V(`yH~d>k?A9r0@yehCa7EE)BV`n8+z-1az_xl2WvQq<)rvkpAIamhkZ zF^MaX(1Sj~`YV#wYyRODr!Fr#PClx$-U_Spntu+}*#K@M?$LYDf9pR@%U6N1i%h+I z{N6C{2V+0(G5mrD3J9K#2Bd6MC*Ihuid3|4%l?o--mT> z_s^ux4XCabcitGNnuN zggfVQdgpZiS(Nw`jH9^6oXPH=;!nB>OndkKZKnUHn*Ogq@0Q^<{Xfn0|1vPP;^tAm z;(l=ligI{1vCrs@3Qa~1?cmq|YV#Z_o`&bLrr(LBz#v1}`V;XH*XCmq4RRDxrWa4d zpT=H1ixwZnowJou^ojUtN=!!UdALzO*YkGg&WZzx2(ZR#qiM-=#)Bi4kS=GNM0miOxZk zuEe;NB6{O_;8xhm`q(g6fUyjB zRz0fWA!ybZ21K@^ zW@~-6)7h;Q)0Hl5uXcNY6~DHvU3>dtPBYbA3e*49Ma zrn5axXXl$i-){P~2LfNiZ92QdFn(29Bmz@WV&Oc(tB~r}LSn^Yg%+h1+yK({%n8Ft}2h&S#p= z&p=qu!)-dBX*&OXFmA+cI-l)yUe2#_Oh0QdA1iU2&gUBD7BD(-XRU^AdZe#Kf+HPb zjEEl1DV$W#$U!A?)$_P-L1}AjuG67sY`v&{0Pde~n+`o=&*x|^LsU8wx9QL`ww|3I zg7HT(^=Lk0x9miv7l&}Ng4=ZHXLhvf{@m8C`w;~GhTC-L7lxUKSvLl^erlxp|Aei@ zA@y|SxFthf8K=<03O*4vZV$potwFACVwa-UqfYAwU*#$;3nfk~g%`kre#{Ia>8E~4d&w%aSk8U$3t!cJ?0D2h`Kf`TonQn@X zhv~9$k6z7z&#?8$@G>yw;?6=yH0PGBNYK*tunw)dyIAFJ1&{8uMR=GIx%Yra&$`OR zI|?3;mv1pV>ZP(i1yi5>a2b(Z^(l$b1Wo*U8j_a)xI+nIoXz5Zq=^iag?w zGAOe=+98V}a0YHOD6sj#hLEK-F(1XDRUvs{WgywMl*26Q&nnw=_dZM?3TT!3c;{`nh;qBlby%6=ph~60% z^?3C08}@h;th3`G`l=OKD>15SB1A2Ff-~r^TKYirJaAXy&c#xqcwG7+2-zrw=&E!R zp;7Z6pgO)79jW;ah};Yj>rlAnJ(k{Wz6tIhaGUveou!959#Z(xINAAMZ|NtW8DJFP zHqT7ow9@36DQhAs=Od1O65>mt+?C+)z0o%z4y~+0m3uB&Jj1-(u=M#tCwM%Wd_2Mn zT?Jm$!$ZEc#D+G@T)jCJGF2#JnLYh7OP^KW0L~S-bFnEj zH#t4gP9B-O!WXovtW+O1z&R>0aWz`wh7ueP#gbI2f!M`G%1sO=$)KUz{~NF%fyD zb=Hxbha#g;cM1}ICQ_vls7HaI)Ty;)BWdZDovhUmiS!h7ja|rK0?)96t?@}LI>f8H zG*r|K*Dx&Knv>)xIzDMZdXW|%p09)rNyA3`2+L}wksO&16-+I87`{`Z%h;qy&4NfY{Af1cUTzAY3NGk6+7^i$-wSXh-QJU3_IJc z$b$4JRdS$8crc{dT&G5wXIxa1sCc})HeFXhx|J7I7ept7&4Qt&t)iNqIAE?**`(;) zsD>s-*$)j(89>-Ec7Al8O9@N~URY^xU#v0Cq%(+Ex5y6>xmX~bL7XpqzzG+0QI@JC zP&A;zCyaYZm+I_Q1l9sce99HcU*WLug=$_PG0_wr|50Kk0o!9`tIgZ?GLdD7t$Ufs zH^jwznJ{fI7@5n`7t-)IsjencUAN_`uG^!lW7x1&x4oAMQ(X;G;fuOCwwr0vj6Nq^ z)E~Vi&^B(nkS^5Os|c(m$}W-oh+Pzyfl!QO*jSO?X=CYdNMkX9O)D+8buSa+3~}*Z zCQQQv7>m9@D_Ke#%TxzrMXH0bSRI!yZ7e2Cbtg3zE2TpbDULKB8?;K~QzNvf`AoVm zL@%0%KoRKW&Slz2ERRU6ij^RZhY!byY>q>WY6%58xq`sD!6lq$xP*Gc#b@}U|I#E7 zCIIn2Y)(+&i;^MS9#x<%&&rr4-j3T+E8YgYYm)B+4x8jZ0iT*AKJ~>`Sa$~Q5N=DY zVqcy&Ndl{~)%kIInLs{8m~t++3&(*8>-&inCY?&0FMQ%s;RB*B_6mI`P-K8n34v`a zTR8*CGqhCYY(TL|viij)iO=x$|1AyaKd@nHSpBGk%SuC#0V@$0#@sQ1G=~w{1Xc;t z;&XtD@xf9&09B^Ol~FZX`u&cMY^KJQks6mrSI0?is;Hy_V{oHYf+^{WKkTCJrbcla zJ()i=`~u=plg=RW&=6+f_(xr?$xIRWepGgta82oMFfp|VoFm$B(oNFun`{DWbZ3JV zb>)DXfg9Z_?)-lOi6HH&^H1_+%6^(8r)S;mhMYr97B2- zksd)l@t{fTFo$ILNLSR(N4^f&Z<3L!*wklSsmP;-(1Z$dl|VAGSgZ(vQ((A-0J;kViU15?NG=Aj z5hObRn@#dUzz&lnT&0sM*-@$nS$u}ClMTr+NZ9J)Ud6;eadS+FsK8_}J0}Mz4%}F?FWSq*QNt&&O1HZ>O}IQ760Yl1q>FK*2|~S2uGj^*UMDLFYy>m>UV!wO z@Veo?4LGcmC$&U5ve98bAnJ1UjUsNvBXaa;=AO_6PT?^+LkGJoByH8<)mz8{hX95z z_u%|rs8SOY9mq;JZs70`C~|TuG4}*3m4a!^S4o(UTU)6HiIolk3}2~8an@L>DhH5f zlK2c?8Aut4YD$d5ZK>*THWF@2v&DhBMR`UQbd8X&$;fjDX^tYY39RMhJ!fuI&u4(a zo})BA!x#1P;fA_|B-|d=!AKCk+^XLJ?#Wbl3P>0soPir!5TtDa6#$p8S|=+BjfPA3 zvf&cgU{pUqt4`cpWY8DF4%~VKuRwy)NE5)Qi`_G-RZ*YWxG|tqf&-5vTW&Q;e1uiz-mwERI#j%BoGo3L;I*DU_Q22lWuhYRr6NFNotRc)b zTmtQk4iGr|Axk)@lk|+wxJ=#4BXzHc)V(}X_lii}%USn2+*mva?17%dvh5@Nu*oJI z#O+c1KDYaFO{WU*O$YP>y$htvo;HsObV-h2BW`X`h+A<(1ws#QkD9iZ$mYS0*tK9U zI8j#?C^SLH!98#UVvW3`&SLa17K5*seI`nAa~z5H;MN(ys0#<)Y>+@1s27zTCKxj1 z@qx~VAtkVCw}DCDZn6oi(VY#_btNO6ha1gL2Fx}|N84yaL&%)&WC3YrqKP*(MM$y~ zbaDz)0-Tdv8^A~P1b#Ii!I{vF+ih>sm+0(D!nbs?nsATd68KG&n6-$F?$hk$1WKIT z22rzOHA=cQU`_7J0|I&zIA=dgl=%=P_&!6FRXKjdFKQso!10Bya!8>GLcLDb5Y`(m z!I-&*&}z7Zt8}u4aD(9z9x`0Q!-h-fHC)0>ZP7{s2L@wJ*lf52st+zi!&e7VoP*Hv zQNXh%iBGv`8B;9E>D@*-1`!x#m{Y`!Tm(=x;jcPbLwMhC2`v0sgM@6k&IV$35!!Te z6@d$v+jU6aVX_Hq&7B=-eR)*t68s?j8CN0luu2omz^){$FGW6 zGD&aP^=NAWo`GEZQXQp=WTQm*Vkk6iR_;Uc1>7!oHU7u&Q>QbkD9Qy3ZWw7K%FD#Fbl_(} zc+)6i2!nw1Od`F2eBun@Lu9}!1THip6zF6Pp-3n78N~=xfOtxvN{}V6+L$PdB62Ze zAc_$#*U2gZYjAr|q{ih=jqYre_>3zRc`y>esJ$|xb``bXrv+9LIA7h4MmkCBzmgEv zOFSu}*UBip{%ekAv|2?laiy9-&D@Sgn(g5RG(srG?NQw!B3sh+NwkWzyqqoX!i`b{ zZbaOYq`B@On-Es)bHd(yU8IT-Zd?3`v}v#^szJ$)G*}hY;1}>lR4h*|)l1zCOPFHA z-MA4M3GBGr;Yj!3MmB-ExwA=|m745DfEOnzlp|cPlQo2U443dD!zIw~ zAxmJjCk>IvlPe2|U`aStC#wi-3@1c+#B!bP&LgsAw?C4;6*p=i7^SKlrQDJc?Up;* zxwBFDq?apJEQS!G0wJu5xMD<=s)#E3yqZnxwnQ?b%E~BJzJO1U((UV|ob4eR5^gYD z0-M%tiKmffdytGYTg_&ljFBY$yphDG>$(VO)0m#~rnbt6c%>s7iLhLeT~;%tR}!cX zyqG{GV9Q8FE5Qg~aY(^i-3xsVt38IeY);nu}T zBCW5CYW<`>WLm8z7=xS>Wsm^^6C|}Lj)pXfvB^H+>H&uu+iLd@w%v=we%!D>;eMU0 zCai>^w8$$p5D<<@T@e zw?86*{47eE9qL(x-{7{@1>5#A@wy?l?q%YyhPZey6Q=F6kkS`COurRoWf;4NO5xV^ zd6_;j8v+^AU`?b!d{rdUAigTX2H(c5zbe9n8NM2%!q>?r%WPaYHmZzZ)B0izODJ!#q^clF3O$b;0-<&KQH1}j7{TXGJ<(>2%mq zXGQwy@_#n+wyq%TfuM9`drh+|`CVRo`;S^NM=ocEIH+F-nC4frPP105CcK2(R$I31 zW#Sb>Y~9Pm9}RKwUM9MA8>Q0!!46?wqpZF_>A7X>wldP) zaL>YXEBxIx&M~8EO+;19v52aeV^o#%OwTbUjH>!<&8UhJ5mixws$Qm5#kbv>ecH_=ZOSXAnlSC?>Et_e z?co@`Ik3EF8eaDp(7w#%L7}q*n*_^akmt<2zF|N+j3hNA3vp2J|F^3##Q%z2&%}JN z)!DGT$NE?DAbhDx?><0V<(dmxKpb;>(tauU7b@~ zo7YWUUspG^wsYf@w)VD$DGjyjnx{^io?n)NL)AA(wVcoL5)+>2YXX}RtWM_z4&oquVp`{@;&!zW@%joV5&~i(;_;aa593PV>${z@sAkV25(ONk&cEw+sT7Z?<;?8NOnTfkJPxeO~@4 zUi|1pk;fZlroV}qvb+iGhBYGq+QEE1%3ertw5_a=H^puZc|1|w zct_Nn`gv;RdxxWzB;7PL9O)3VPEJH=NKFU1G+p>#)$|iF_#!koi~|ab!ZqPL7+XE6 z;FNN#fs6EL7I^)jGUx=E+Pbzc$GZTm)DVkncZMGhAcO`WFpCXo!OuhZ0Bf8k&CeRR z`2?RG2+=>isZ_WKt~1q}$DvE{j+Svdh5qCnYC43!$U{d(xlLvYB+%!L#_@DuJ7uBv zCd@QHoHh|f(Sj?P=(7`wyxy~oOPN|RxiSW5C3!X~ESarGEy=!n8=Tty4Q6_>eQuFA zskE>##&zBpYCJq@K*Y?mbj%1F88y9NV#dRW84GEE$Oy1iG4%hM!Ql(+>?l+}LhJ|o z>KX1EKR}0J)^0H?!^3Rt2rz2^`fyId*c)@F{fZ5 zU>cr)wQEbk=HBRI;L!kT(gL{SP(V=R@n<3Sl6 zY=j)H&v4VkkZz8SBaU0nSR)bES-&_O%pSs}VwScF=4B|P>yvs}W$vtq*i>yqinGyp zF(zUcrXa&*B67HhCF<32C{ly-PfCQCqctTma!Pn{up)oj^@6 zCYEQKE}q6>)Z$2^w^77Q#CMZ3Q*T*{v^HkDFjem+%npH0fcj2GnC(IeTZ2K2g-u`? zu=@$VIiK4**x*N4Ae;`vgII`~!7meG0_JekXnxWhMTX~)@f~pv!;Kzwc*g&T3~Zbe znk{27TY_t0tiM`W3uEHL*U%SEEnq`@V3W4UN3l$?D7o$wzU|q(S?^~?BV8Hdu ztYeWGVCWMUG0Y6qyMzPiWW)0B=JN@&vy zQVz^m6cdj>6%*ny!*RgM&oUvrAZGgky*8cDD=M2mz>ex1y+UNuL#OFvPE0aeb2G`! zyp$&j-c_g^t1nmiMm{f`Ez3MK;i?{wT^XNAxVfjbTf%;#7PHJw)5t}1q2|M@ zxku4^kg0m8V?!Hcmxs=BIsdHiK8s5=BGOnVBI(K(!i9s{m6PoY7JB?q`{pAFC%AHW z9Q1}&PwLML1k>QROFqxUS)bw9|J~_bae@cXk^^m3G4^JUq{E1~wQ&nQ>QgWE&V}_j z>LF}o^`4O*c!V3+)}}V|fPh6c#u+kC;tUbKafZcudzCa@PZ3|#(EK@Ih6YDR=D{AZ z`D~f|1uz&R8KIRSd zFnZs~GJbNhjO)_H33T+q;n-kf2YrZaNc?i_JkoWA6_e?xf8XkR7 zlJY!5N$x9GhP9Xw3BF@~xjmG4l|dC^ovDb|vOa#L}BtQR(Ye1Nej z&!;`;3=@%!QOL^o;xwM}Rb=2W-<&ZpxZn|caFG^_jPwNX;XPso+LtCWohtx^O#~S1 zYP2Mqi_}8zf#b?B7lOjVg_b$IW|(K|m^?P$;YRvKneixrV_-b=lcLjLl=QI0Qf@5@ z^ky|Vg z9x9noxk!h~GHx~Cyrv??Y;Hj`$)lUkB6+OIhyDtdUFaRGS4Om%&5FG~!=-BUAH*Zu zcNUtb^UPqpT3v+HIeNK4H2Mk77>r&fgrD-?*URfGm#WUvnk3nc3vojC3mi))*ewF*o#fNUrAYLWlD$)dsXNh_K}^QcFr6Lz2;p(mMk!{ z^xjCnvM@*2d}X1XzoUa#>F(fiik~E?AWVt+07;G>6PADeaz9x3!nU-n2K=gBF zaJWO$xT8xC<>yDm>&Ig^Xn1>xcrD=?>kDHn9>1u#E6Mo=gAGNr(zDNQ#@iy;$^=O) zFMO`#B1q&O1Va;#4IM|&IZ;pW&E!IZS;zRB?;WP2vM2f};xDoK4PMN-%V_1i+;Fyw zQ}zD9%dF|n;N?O;4l8uU^8(K3@qA=j)9Z#FozxP-hN!P&Kbql&kKv(MH3mnJLtY#5h&X1XrsLrT$Ny}URUm&Xv);I+@< z(AoQ8cRX>wu~k2E^GRtcYeyCIVeASLeb`}BWGG%rE|rNEZeS2!JXkUjG3xN}1e9g8 zOYoK08y3=MPFgEAD8tPw4ZI#M9iV&Wr4pV6&D##WYjIwP{&#rAbIuvq2b_pPSK&0m z(J4EIG@lh|3cP>NIeF}jc~6n3HHIEuyJR7Z1cPT6#n`*ho4}J1);Ung1imWg#)Nh^ zR&!q1!V&>Fb<6G+>@9+ z-c8v<@KrLkq+uh!Z>GQV*3epefli?iR4=RTtVccFM$6I_)n`RF#=o9C zZ|RCq*|gI_=9_S#!h*u-(+Ubs4^7!v*Rg3-$V4vgB)x~5t9n%(Bp8m4TV)Yy?<-w~R!9{=mlukCD{QW%=D z3{+!1%sHj2p^oP70^PW&O{c>=rz6^M+9q8Niyd3g*4SQiK}SP*L!-l9fKgMGt?X=W$FPKLR@G2jZ(5?w)zb2sD*R*}4G1fjZtCpn zRy8FhWy*XrP&OkZQG{C+PZG|N`vZd*x128L8ylY+Emw+)XZH|HMe?hjat=N z+1cKW-p}iFRYMnJC!Fe7(hTL?&d&Bu)lpsE1$8!csnv}QolB*Bf8Q?7&o6Gq7QnO2d3fOQ===X^s(Nk>On`$kM1GmPlI z%K@lmUHc}ueRErV!xmMuMH{A!Gm(a^S~<6TnyNB`xVWKB_i=7j)v_wp+TON4q(7pj zPe;|3(oKzxmED~Re<@De#Tmp+oeiCsA>hIWW&pJFENg7+YQV&+-BMLwwyCqTp{;vm zc{xZ`-B5=@^*S(U(RrOqHnpk_{tY_huj-5zFKh3(prW;QJ)5XNhdBAeo~r#2U09E3 zL%)zDjlXP>=4c7=o;7q`T1N)Qn8k68B_-91*a)K*$ECcvOAm|)OQ@ih&e&EhpN|n} zZRk{8^=riER&`c)G&Iy#z`vCq{8$S#8++4?wI=dx>T+Be5wW?Wi5)3vMey1Pqp1#( zZa3_12#eR!tPyLldoX2pv+lI^)aWjX;!Cv_Dlhx2~9Ru>_~%fa?IJPhV{)| z-LR;r>P*S9xeHbu2iZFsKZeJg90PSq9KtgkI&C~1IG*!{u z+EBsu2;ruEQwOI?C8h~J3-#x8{W(L`V>~(=Hr6(`!8%T(tV_4lg&xVORZ)T1*gL$4Q#~yh_Klh?3{<+e3_mjweZ)g$S**iKq_CK-;h%ufD<|a3n>(pL6sT&bYrt2= z^->BK#)K$qZK>#NFpDT;^s*6-t4;MAYt9EW1T3 zp|EFa=-k{;Kiz1*bX})O$g&${IA>J}TWeVdR-yJt_}BejQ0~k-?bb$EyIcpOW_Z%g z>y$M|x1r~qQ!uhpunHZctLwG(92e0%6R6B$&q^X5TT;3VzxAZbwd6=gOsAa*$=+&5 zsBhoI)sH?p?Nm6aQ5wNEVs7j%IvZ*?mezJPV2C>#uyu6Wgq&G(!iLfNL)|53h;+jo z9U~K|cg-@)&<^hJL`5gWgF|QQ##*H}xL9!KwJ$)R*P~CzY;0c7XrPzU0;jl%Rc6XM zgNx81!#qP_U)|ZQx1*f(bnUXmi!d%U9!JR;18q#*P7*+iGq zHMk;j3~I!+ICf=A;g1a)qZgCv3%XFYZY6#c1UpJBP>2cGek)mrb+`~?)NF~`<*>Ik zdYDd~5gsNTfwix(5X@JDEtO*qbP{Hg)s+6KA0k{~mP+g4Dwi2=tnD^MU2SJQRE*ja zA!a#?Fdrry6ICu-1v@y_)-#%0$AhkU)$OkHAZYJG81*MjcUH8s$^+(1+3Ij6W-4u;+w~d@MxIH!#U4k!PImfr1XlR zx3Fdo)#_(9*^x33y0;6`aJU+0m|}N$*bbGKEn5L+)iKw#JY&{rw{*rpyOZ7wX}0rx zT7&2sj%<2~E?ZKrWOo~0AWR5Zp!dU(QSNTbc{69J#0O**u|`lOYyXb=i5fz_efYX zv67=a;22}xNT}lTomMU~>{WC5_!4>e;@(=+H|Ct$)V{G{YGXrv?bIa;Dr=@z)z&w+ zS2neGx3@Ldt*PF$4$BfA&l=Wr*4Ec{PMz1##;M!hxu&wLG)5SlHC^qE-Q3M69n{*o z<&h0DtF_q~IzG1JjG)z7p`G|+mJvRgFPpn$jV^LRG!`qkepG1U+(UflCQkcGJ zl9Mj6FEw^r6-Z8^kB1xqAb;*y{9*Oh^$X#4u7gOp%FOhX znL=*+XK5K{J}gc4gLd1iDUu(>FaH93x9{_3qY+DX#u-aQ)y1EemN^;4H?}ilRWc1i zwfxy!WsOJDd)nM7OO$U={E`Guz@HYEVGXv1+QY2j)(C5qHO9(9d$E_B6{kKp?#{$+_G#I4&-{Au)|$Y(8#qaOZ5uIsXuH%8v8e|rGs590P9{}kY( zxXtBt5*ls%F6ij?;^lYa@<;qxK0Zc1Ax1tyam?7>Of8=fBcB)}pQx6J{Cq7Br*&Pn z8WbZxNS%Xx*3X#jLB9L4RZ5I}ifR#g7V;q9ec37)BOjDMo?w3QnFsmq%U0&2aw>U;~aE$z5bu%QW|76@A{i}>3MQn_2wEa2Sk;_J;kIr{{KYvDjcufBANMWRG zH8LiDr1ppMup5qykslo+KU&M{Uwot`@mEq^m#xOe$dA?XKM%`{4X2o}Rc4HQrj|b# zmdXsLn6OoLjC{71&!a*0m96dsk~IF5uYN3a6VRiI@fo>nl^auEuC9;2v(Q|*PC}!t z#>dEy*YZchQj8jr%T^O&^Y*iSOU#RW%gRp)1%R(ZTt)|DwPggq;;G~q^wSy57o{ZBTdlC_ z{tbS|V(38FHs&|{@fQF)S1J;x#?bR)=r6_4tugdPG4!q&`r9$|y)pDpW9Z+;(C@_1 z{{~GKmyj&1Ur9(r=wWKK&^gFY!}>HyXg-UiVLh4!bT0OPMGV~*Ltg?~s{l+>qt!QK z^7qHk&x-u>s5=eo(;tL>TGN^8Bcb`sk%sjp(X|DmKBGXhJw9ioVZE3xG{-d!>p^jh z{8=${M-079%JZ2c4eP_zLdR)(qS`AoyOE_PsRyIz$?CZ%dW!0cq6^eVLa)~KO;hox znELbCA`S6)I2)3S{hJa)&yJz>ul{$*pA(bc8bfab&Gr~G(=dClj>*3*hW@_D^Z6tV z@%a&<@6q(>>II>5G<~LeL+FE=E>g#Z&eHU3mG0WovVZu4t6CpE8>Ar~of?xrPxASE zkcRkF6O+GA@=bpbe+D={%;E96J|}j6Q35P|o`;tjIr^IvhQir6a(Jv~&dwv>%>X;* z*w*!8HvIZjUNJy8_Jyib-W;ES!r_(sb(7&Z=lbq*ZIP8z?(jLD`*1$Y48I`>b6hXY z-MkYIfN{8nb7c2dTw-1tnBugJ>qX1JhvDItoL5SGRV~cOiDp>JoOXrZf=2i_^^Sh? z?Yu6F7BM!JgE8klZ-jK-K;od7wv_jghGKW*95P%dd9Fk6D8Bo&H=I%JK2nu-UGHg~ zo^Py=Jx>qUpflWcODz%gTyOAQRlB$@QMgv*eAM|0$BBB;$)Zn5!}`dVVK6W;-@%Cf zmP}aQ9I{Fi;RE9cZTwp3n3pWV9rzW3E*O5{Dx&(NIF>1g!vnn8!j~6}q7aGrbYxUG zulaH%+?$veA^K&aD-+WC%OCO*Aacqp>QSC2w^CuGN#_-6d4ucQSh{v8DSeRB-)Ls| z)Ehp0lDACJ1z3yueiz1>XXjCaupsh14i=+G_?@BDV-Dn_avgUGi<+~!z;>*~h|z%^ z=4^p9caMRc=C8sKHhm`FkZZ#l zNt(Yol=MTy>m&6vNj(=5Z!l|o;70RT6a%~Dk2sOr;^HI;Yh^R-)qr8?!c|OPE8cMV6*Qfh~de0MD_ZxIK z>AR#~-tssla`(ugD)1d{*#Rf^QLFoN+{y)B4=6R2At5%%9~81jL_K%J0~} z!kn!J4oH7sWQeE$j*{|-$Ul{cqZ?gcNahdts9Lw9{U}@J&m-brumhh)0}q=&HO28w z7FySPN5pPg&aoThPnNIk1$)=Co}lP~dbg5Bc}!gu_@4L&5LIcvdRFphVtlE`IwB5w zwEwo5zvdLk5I;mc*GvAb#1`>u=z9>f2l7u7!C%OF(TLXTG5J#qK&=Pb(e^?+t0~9! zME)uw^6_5-#PdLO$XaGe12SD}Aa+985lNIPohAPZvN;(#gW-X$SKe4~Qj# z^9A{IOFsRNxL&YTaGN0K74tbyh_?v-Uhv<7gJ=ij=L^miTp@U=;B|uE6MRtc8Npu* z{z>p7LH>eA)_;oNTtPnbk>4P=Ns!NW0+3T_g-L~xJbt%3&x4+_30_`2Zxg8V~`)IV8}f3TYL2*HrxI6*#(F`v(1#6^N< z3pNXG5xiXRdcp4r{y^|4!IuR2?8JHx3-Z~Cbh2046;5Nap3w~Sh9>E_AJ}daD z;M;;93;F^^kHLb|1xp311lJ307Q9sOTEW`{?-zVRuvhR8g6|7{Dwv*V+RqZ4CRi-E zOz=Fxje-{mUMYB!;9Y`06g(t&STKNvmh)kPV42{T1kV?|UhqM|7X^c;+)>9;S zj^HN2s|D{B{H5TBf>yFAKT_}v!LtOn3f>@izu+Ok!-6R((jUPx!F7V?3+@)YPw-(P zHm#2e9wc6XKOiCan&2OZ=;vRA{+r-Y;m4(#{8S>!X9(sBP7ur|qP@99)VGv~I{4?n zh%1RG-zwN4xQPh)?LuEFc!lt<7y2f_y~4j+==%f@3O+6P3nJQmnTY!Ph{Ke6OYm(X z^!ZfKgS`^zcp~J}g&rz6O8AonX9~YautfMvgkCPVQuynHZWL@0{^denDR>PLdfq5_ zkKluXzYu&$@OOfLB0}#EiDQ)dyWl^G=vOMnhL|BZfe86igg#wxHWB5Q3$_S$3tmD* zx!uH(N?j*-BN6rAC-{Ki&xw%#mC&yU{+@{PhXn(8%}Y96Fq?>S1;k7|M+(j)qMfCJ zRf4OCkgpSZyZxXyu@JYef1m7h>kB^BpO8ralI1zdb9%68~ zU_KG@X9zu8uuS;XMAUPxV1wWm!7By7BX~gYX~EY8`vw0c7>8#});m;iqTnpSO2Jwp z^xHse#dDNkClUR*Nb+|HeU;$11#c0&orrqw7y2Q=9}`jUi-Kt$j=cvPw;fXS%RfR$SoDRN^lhs^|lCZ6Wk?uBN63pB{t$bM({2o+W&#% z9~Am&!Cwo$D)>4P^}H+e`+`S=e_UvLxT)7qgnWk3!vseYp~p`yg;c-iOAnA^mT%_3*IGo9}#jt7W#3)r-`Wd6~Q+IKO{o_Uqn1Z92ZO)Vff>T z7brDJuu%AOh}}w+3C@%JFA3HPHWE>Pr_h@Pzasq0g}zeo8Y1ewQSes5hXfxNJVZpj zuM<1*M|=eTOoYCl2;%jproBYS2ZbIiI70a2gq|okm56%F1Q!dg5L`<{eH)4ON_|;y z6A|rSDR{NuwM5A86Z*S?cMAVOp&t?aiSS<_qW(V%eS}zxI3@TmBH9a%GB{Xp1QG3x z6MCZHRN>DNTqOKuf;GZlD|EeJGZF1}3VucK8o`^1Xzvc<8l3wHK0}0lzYu(Z2)REA zen>p`|7q+_;B2b@KaOAf8bgF^V_#yBrAdAoktIU*hAm4aXbz-wcaV1VvY-iHkgluLYwihsrDSh zZ_ROfeN22FuT!2+ua&ZQ(DNQvHMM+AtYd2Vme|33I27uPPf|iK31{E}Q|*1% zY#ItJ$5p2G*G~Kd_nWGJoHz}Cp!_27uXv5}+!efh`LVF6Jf(@tV`a+g5;wqmO|`Eb z_QeF8U@G5C^FE#b$9bl<<6pP}-#1nNBjRnii}HiSNAPRP&k&!(OO$7?=;bS9YJEkq z5>~@nrrOsKn_?^uHPx zzk*4WFC|XK<&PcZDvh9PU0t~+VLI!fIpe4f0g(e{z-X( zYTj~%v6!j)k;Ij;2IUQj@5QE+x5rq@d*kDj4<{aliIhK2JPl`2{yOnOe2elG#H(=| z?!>*O+JA)jIDThpfBl3vuxNF!yeihgXl#ZLVOLZ6dz;#a{cs}X(@p(P%)<95UvKKR z2~$lSufuo@zh(Yq%vD46w7#Ndcm32Q-f3$2y4V2kHC6vX;x^cx@>t^D_&DXGOyz$L zU%(_x!Bjk8YCUOYtj_D|Q+IF7<8I2C8(TwH?7(8gNY`ZnPqJc?;} z63^j9yoNV0Pj)X~0j!MGu@2V9CK!Wl@L}wRu{hXNCmM$C^H;^s5KqDva2CFduj4{o zg==vWrs4to62HL{=sv&I`m^Qm+Ladz;_c`@-&MVG#1*jy*2V@Hjcu_5cEeb7pa0tS z6Hmeya2CFdNw@%);4)l+t8q7eiU;usev9AZS-gOMntJb)Lk|dM0W6FquryY}YFG#B zV=Hu@H!EK!;%+z$pF;Qfv+6xZJO$n7(JG%!JQo+6r9&b2`Lwh#zZS1T8}n=NX54|h z@pC+cXYd?e!E`K~%gbkDfi3TySPrXT4Xld|u(?@5uPdMZ7&Lua-2e2i!$4(fF zy>S3Of#Y#9PRCjJ4!Y0hwcb_4YjG2%;(k1cU*Wg-C+5iGZAX4AgvGHGMq*{W2k*lN zuqAfKp6EXBSGyC5C!qWMU*$82=iq#N1D9elt~2$dz7es%&u~jY(ABUnFAE7plA$}GoRm><0ZU`e_*!!-g<2ep{>6Vy73o^OA*(=+V~K*$FBG& z_QiM{g2T~`+fe?o#FNmC<52lb;yL)HIW!b<<2vMf#Q%faa3}7=FYqj0z+45qeEBc} zi(y%;fOngNHEt4{qAo??%DZ7K#$kV)fKxCD7vK_HhAVLm?l1@FJT7gN?8;x^XC~--@^w_QioX1jplKoQ|__f!S7{FJLmJ;C9@FZhVXC zA0Yl7PvI|k33Z7Pmp=k4U=@ru_1x&j$H?Zyt+2b95DK|*GxBlbfjAXk!nybwF2u!{ zj4Aj&uEP&;EAB=&E=TJ>NPGm(;YCcx>zK>N-)OmfSP`pYZLEjU*aVwnE9_?K^QBnq zhXZgjzKFB%Wpv|&wEP0%CAbV%pc_Y|dK-v0;}>`szsB$IC;SC->AjYzR4c)jZ zm6s&0j&#$-&vJ?10&J_jDcqnL&#@d~En zpP0kOGbxW7uO$l+7spaq3*GoF)w_rIK6K-?I_UYqV%ZM|;AFG8z9)dQ@MTMlKyo}fI2IeZ^?T36=(!5W{9V=sXtcwk>3C3V=?1zJK7$#sMPQWQR z183u__&P4arML(8;UPSVX?PNU#`Aa;ub~^yrtNp**<^8@%e4Jb3f=fM#m$IYV>|4H zeQ_YV@oZY|Sz|l>2o}eB*btjw z40gpw(T#J{cEl48!QnXGY^3j%;tZUPui-!NEp+4GwA>2f)wmD8z@zvzp2X959xvlH zyn(sy^xBsXD`HiwjrA}Zn_xTah~2R#zJSxwjf2y6%_DvT-^6$DU$_d_;tt%6`|%*2 z#M5{lFJtM_-u9M9H$G17apU7;J<1zm6O6%**adrH9~^*B;8+}wui$+AC%%Pl+??96 zocLqhgP-FeJdSC23V+5+colP%(e~HZ>pFDf>lC~3b+Rnw6|e@@##ZRY*QtId;%@jD z#^E3wilcB0F2=XfjjvPQmBj0CBW}Z;_$7XYC-6r+hZiwhS#SGuVL^1`^0eLt#L?)+ z->JMgacAs~y|EvT#L+koC*g8jh3jz>?#2E1C4Pl&e4g6l#^=ealwZUA<-F}HgvGHG z*1+1>0Hd)B_P{>)I40tAI0dKTY@CaW&AR&h2AAV1+<=>L2kyqt@ep3bU-3HX@;q)m zd9VN$#XGPpR>1053p-$EjK$vQ#tCYB+&Dq`6y;CjIGltpU@ zxEZ(LF5HX9F%5sk-!N3c+wPoL0NwaQ?XT*@wXi6{7`3XFO z=kO|C!yJ{p?aqS{SPZM-U3fP(LN~rq>+MV&i@k9m4#5OW#7X!9&NFLj`*9JvagQob zAzq0a(2al8`~$>aq8tCH@)N{o@Ep4FkD7mb6>q(FVmYjWHSk{i8@9mK_#}?RXK)-o zkJB&-7vK_HhU;)6ZpDxBB%Ve$?or$0#y!ewl;6NRt9sj64y&RY|ET&g#4WHbcED~J zi=%K1j>pM39o@J{<)25Kgm2;!T!ZV;jgQoFpAjF%WB3PVtLAN2UMz^WV+nNQBbCpM zkCe43uZNAXDL#m8uoHH}KIq0vD&J7z5jX{>;%uCY@8dfB5Vztd_!+wKky?)%A1QyJ z{0v^eEBFUytM2We{8$J}U}>yr>K28KurWS>Ezymq)O|OeQVynk7$#sMPQWSnhS^<@ zbGQuM_)C?)PrMF4!fp5oeum%UDf|U5VV)Y^`U+t9_{_4DS3oyDQ|*W*z8{-oCo@*x z(?&NwQ*l4yC-6xejbqV`(^UNh#7l4)uE5o}0XO4z+=ZW^8|SIK-xHt0+#$7hjCZ|H z`y5iIG2HkJz5H?GKD3+MctO3?apNtcO`YqDF;%&>srP;zO}$p`Vd}L)UsI2%gG~KT zjxd!h(NsU3XzF=lnyKV-OugSoGWGs+k$InY9Va`FxYFWg-gS2De0HkE4|>Vek4;c3%8~#X5hUZg$b1Y*NQDuc`eKVfNDYn|(r|NHb2a@633O z&ou|=xSNBu{pL_@zp3-b9nF#2eltP&HQD~miFr-^(Z|Bh2vb2ZENK?jc|nXc^;v;- zp;Nog?e|((*VIA{Fxu2{Xo4}OjziDn0 z^``p4CQLQeAGYHzQ~hEu?l;vx4&o70{p2{Nnd&bm@wC|`6grC+O!c2Dm~N^cUB{61 zgI+rR==z!ZRY8lT>u+&7{uWEu@3gbscwrf7K~=G4(k_7ZkOs0 zP5B(boqunp<8g<|b==cU9q%F~q>i)u{ORQD7{XLQRc~ko&nK;GNK5_k3`43vG zZFBuivFmTzM%RB7yZ%#-{-D_P2W>-_Y+6pSdwf#k;)w^DI$jCHiKZGohj^Z;gZoIdSZ#?lJQ^$E4@l3O+wwE}?Y^KL~VmCfp$A1^` zUQ_+x2=Q@K{oyq6SyTNYo%p(`{t=Nws(r;w^^-_qcik=Zm%7AmJhu8x3~>un{bvyI zP*eSACh;6o{b?of8dLxG2Z`OdY4xv@#HY*rDRHu?{uzoI^~|t@xPCHWq~{?2p8H+8DEEt#QT_BASW#9G z4%jvW_p(lZXdcuVat|TOYP#UcCFSdRo!)5Zz|1lmEkP){U3tOQs`f2 zm@5z8a-RRAu32Wf^>|m#^|pwse)`wX4KL)nxtTer|5xRi*P{(=HOmC9V0-h-%muUV zo12%t<@~_nc75BM+8bE6y8!M@6})TNX4!mQJk`6JYIv!4N!2W+VOO`!GB4~Jw^`<8 zz0z%FtGN7g;Fn3WESB|JxLIa#HCek@?JdhYt324BGp<{kS;{{D-{%CfP(SN+Y;U!4 zcQxCa*7FzFwY{lcAbv)te2%nRh+G|#&-?yZY6 zI%RzSeoqhVGuVEtF3P(f*RS75{oJry&MVPRV+X@HU7~!Te!w+Qgg>@y%vg7GirJ7IV{xEWGJ6* zF}m3l@sXaFrJkNbdWquRn^?Pg>lR#ZP6hc@=1=~5^)#0yUu)&FH9ucd<4D)T2l-wP@T=Ias2S3vXpd~fQ0FrR&A z&c46rPkz2PR1nP9SNS@s%(nM7-TZtTbU&DHo+Y?NzO^b2=3A+J{_!Xr$hR*%pE^!^ zmHCt3zC9`k<~yx?kt(zH717Oa-%q+9Y~P8$$oHe_1@q-i&CI8l=Nb9(C|NLHU9HIa zu0Q$h%b`laeAQFc2UW@1r#KT| z{bYf9tyC}AzUb7<_G$P+M*AKQ%lEwUwf0v=JrU{?malcH*H3MG?J-4*x&AyMEZ<&x zpt(i9XT$Q%NzLpp`ZzWt--7Ub`lsBh`Tk_y{e{ff1(yl#H`HiqR((oWj0 z`TpeRTNjouEj2S=1y%O*eHE6kmmXZ~eXBqD`Rw;xg2y90Rj+cu;_ip@s5m6|!O~Lm45Vqc;s@KCR zFln}%?7O(Z_6=3N^;W>-@5@qpybIQ|vF5ITdVap*su$djIoghis$<7jZ)r2OqfU4} zJ=i8|zCZcvy(=tV#MaFI*HD%H{n92Z-(Ka@Tjq?(Z{LGq`C^pMe>}Y>kgrczzMMLr zkdl!tvyb%*%hxfG@7_SZv0?dEDqrP5KEHkQ!|K_!DpLdX{QY9rtPbwyzFKdj>e+s7 zqMN^8J_^e>PftP>HQ%57^==HyH&OZY5a{wXm43dj!}8f!=Rtll>REU+EZ?+1`(mhP z`7ej%i!A1yZ`CX}`RzL&mM=Mw?*Y~H+h^aE4))XdzsQ$I^@96vS0G=DKt4Nn7tEKe ze7mfGNweKlJ}lp9<(s29c05|@X7y})?+?poV{qrH+@G>@=f1FfiQ6)dZ)?@@^VxT} zgYC0xG$#AWsAr*l=R3H)Ny_KHZhDA%);>EY64<;@it<&jX&Jo9pEoot-+twbDdTN# zJ5|+ex4rfqa(@}iaIl#k$8{|I$)9K6DfjQ&ykjjiZmNb~D|6lq)eCM%M4J9TRL}Oa zPC;d?cVSq*{ZFc&23FwTeLXDS{(RZo`8~_0Q&<`KR)*z^9^st_R24V*`BK92RWFb& zv`7cl@^#itv)z8#8kTR)Q{HuPTr&Of^L-eWZ`Wv}l$ zz{X_x>~=J)-fQYC_Ppy)e!U;5=a;9d-g;XZlYjSw?gWoVNnO0d-`+=6*Xminx~w}o z?AmMIl(<~y!Tmt`+iUv&12#KF_3V1ukLms--7KGNmaQ|;jY13b24bYWA!G9M>1iNK Oz4b-1g>u}Y-hTnKmOyj> literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_hal_tim.d b/build/stm32f7xx_hal_tim.d new file mode 100644 index 0000000..b13d58f --- /dev/null +++ b/build/stm32f7xx_hal_tim.d @@ -0,0 +1,68 @@ +build/stm32f7xx_hal_tim.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/build/stm32f7xx_hal_tim.lst b/build/stm32f7xx_hal_tim.lst new file mode 100644 index 0000000..7d80a94 --- /dev/null +++ b/build/stm32f7xx_hal_tim.lst @@ -0,0 +1,29972 @@ +ARM GAS /tmp/ccGFzgX3.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_hal_tim.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c" + 19 .section .text.TIM_OC1_SetConfig,"ax",%progbits + 20 .align 1 + 21 .syntax unified + 22 .thumb + 23 .thumb_func + 25 TIM_OC1_SetConfig: + 26 .LVL0: + 27 .LFB246: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @file stm32f7xx_hal_tim.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM HAL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * functionalities of the Timer (TIM) peripheral: + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM Time Base Initialization + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM Time Base Start + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM Time Base Start Interruption + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM Time Base Start DMA + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM Output Compare/PWM Initialization + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM Output Compare/PWM Channel Configuration + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM Output Compare/PWM Start + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM Output Compare/PWM Start Interruption + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM Output Compare/PWM Start DMA + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM Input Capture Initialization + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM Input Capture Channel Configuration + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM Input Capture Start + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM Input Capture Start Interruption + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM Input Capture Start DMA + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM One Pulse Initialization + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM One Pulse Channel Configuration + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM One Pulse Start + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM Encoder Interface Initialization + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM Encoder Interface Start + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM Encoder Interface Start Interruption + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM Encoder Interface Start DMA + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + Commutation Event configuration with Interruption and DMA + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM OCRef clear configuration + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + TIM External Clock configuration + ARM GAS /tmp/ccGFzgX3.s page 2 + + + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ****************************************************************************** + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @attention + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * Copyright (c) 2017 STMicroelectronics. + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * All rights reserved. + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This software is licensed under terms that can be found in the LICENSE file + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * in the root directory of this software component. + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ****************************************************************************** + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ##### TIMER Generic features ##### + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] The Timer features include: + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (#) 16-bit up, down, up/down auto-reload counter. + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** counter clock frequency either by any factor between 1 and 65536. + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (#) Up to 4 independent channels for: + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) Input Capture + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) Output Compare + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) PWM generation (Edge and Center-aligned Mode) + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) One-pulse mode output + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (#) Synchronization circuit to control the timer with external signals and to interconnect + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** several timers together. + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (#) Supports incremental encoder for positioning purposes + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ##### How to use this driver ##### + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (#) Initialize the TIM low level resources by implementing the following functions + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** depending on the selected feature: + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) Time Base : HAL_TIM_Base_MspInit() + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) Input Capture : HAL_TIM_IC_MspInit() + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) Output Compare : HAL_TIM_OC_MspInit() + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) PWM generation : HAL_TIM_PWM_MspInit() + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (#) Initialize the TIM low level resources : + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (##) TIM pins configuration + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+++) Enable the clock for the TIM GPIOs using the following function: + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_RCC_GPIOx_CLK_ENABLE(); + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (#) The external Clock can be configured, if needed (the default clock is the + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** internal clock from the APBx), using the following function: + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ConfigClockSource, the clock configuration should be done before + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** any start function. + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (#) Configure the TIM in the desired functioning mode using one of the + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Initialization function of this driver: + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Output Compare signal. + ARM GAS /tmp/ccGFzgX3.s page 3 + + + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** PWM signal. + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** external signal. + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** in One Pulse Mode. + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (#) Activate the TIM peripheral using one of the start functions depending from the feature us + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (#) The DMA Burst is managed with the two following functions: + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_DMABurst_WriteStart() + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_DMABurst_ReadStart() + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** *** Callback registration *** + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================= + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** allows the user to configure dynamically the driver callbacks. + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Use Function HAL_TIM_RegisterCallback() to register a callback. + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the Callback ID and a pointer to the user callback function. + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** weak function. + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** and the Callback ID. + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** These functions allow to register/unregister following callbacks: + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Base_MspInitCallback : TIM Base Msp Init Callback. + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) IC_MspInitCallback : TIM IC Msp Init Callback. + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) OC_MspInitCallback : TIM OC Msp Init Callback. + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) TriggerCallback : TIM Trigger Callback. + ARM GAS /tmp/ccGFzgX3.s page 4 + + + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) IC_CaptureCallback : TIM Input Capture Callback. + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) ErrorCallback : TIM Error Callback. + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) CommutationCallback : TIM Commutation Callback. + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) BreakCallback : TIM Break Callback. + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Break2Callback : TIM Break2 Callback. + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** By default, after the Init and when the state is HAL_TIM_STATE_RESET + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** all interrupt callbacks are set to the corresponding weak functions: + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** functionalities in the Init / DeInit only when these callbacks are null + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Exception done MspInit / MspDeInit that can be registered / unregistered + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** In that case first register the MspInit/MspDeInit user callbacks + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** using HAL_TIM_RegisterCallback() before calling DeInit or Init function. + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** not defined, the callback registration feature is not available and all callbacks + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** are set to the corresponding weak functions. + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ****************************************************************************** + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Includes ------------------------------------------------------------------*/ + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #include "stm32f7xx_hal.h" + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @addtogroup STM32F7xx_HAL_Driver + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @{ + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM TIM + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM HAL module driver + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @{ + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #ifdef HAL_TIM_MODULE_ENABLED + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Private typedef -----------------------------------------------------------*/ + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Private define ------------------------------------------------------------*/ + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Private macros ------------------------------------------------------------*/ + ARM GAS /tmp/ccGFzgX3.s page 5 + + + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Private variables ---------------------------------------------------------*/ + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Private function prototypes -----------------------------------------------*/ + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @addtogroup TIM_Private_Functions + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @{ + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t TIM_ICFilter); + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t TIM_ICFilter); + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t TIM_ICFilter); + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** const TIM_SlaveConfigTypeDef *sSlaveConfig); + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @} + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Exported functions --------------------------------------------------------*/ + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions TIM Exported Functions + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @{ + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Time Base functions + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ##### Time Base functions ##### + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** This section provides functions allowing to: + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Initialize and configure the TIM base. + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) De-initialize the TIM base. + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Start the Time Base. + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Stop the Time Base. + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Start the Time Base and enable interrupt. + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Stop the Time Base and disable interrupt. + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Start the Time Base and enable DMA transfer. + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Stop the Time Base and disable DMA transfer. + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @{ + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + ARM GAS /tmp/ccGFzgX3.s page 6 + + + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Initializes the TIM Time base Unit according to the specified + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * parameters in the TIM_HandleTypeDef and initialize the associated handle. + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * requires a timer reset to avoid unexpected direction + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * due to DIR bit readonly in center aligned mode. + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Base handle + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM handle allocation */ + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim == NULL) + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->State == HAL_TIM_STATE_RESET) + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Allocate lock resource and initialize it */ + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Lock = HAL_UNLOCKED; + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset interrupt callbacks to legacy weak callbacks */ + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_ResetCallback(htim); + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->Base_MspInitCallback == NULL) + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC */ + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Base_MspInitCallback(htim); + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC */ + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_Base_MspInit(htim); + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM state */ + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Time Base configuration */ + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Initialize the DMA burst operation state */ + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Initialize the TIM channels state */ + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + ARM GAS /tmp/ccGFzgX3.s page 7 + + + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Initialize the TIM state*/ + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief DeInitializes the TIM Base peripheral + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Base handle + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Peripheral Clock */ + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->Base_MspDeInitCallback == NULL) + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* DeInit the low level hardware */ + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Base_MspDeInitCallback(htim); + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_Base_MspDeInit(htim); + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change the DMA burst operation state */ + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change the TIM channels state */ + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change TIM state */ + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_RESET; + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Release Lock */ + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Initializes the TIM Base MSP. + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Base handle + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 8 + + + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_Base_MspInit could be implemented in the user file + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief DeInitializes TIM Base MSP. + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Base handle + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_Base_MspDeInit could be implemented in the user file + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Starts the TIM Base generation. + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Base handle + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM state */ + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->State != HAL_TIM_STATE_READY) + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM state */ + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + ARM GAS /tmp/ccGFzgX3.s page 9 + + + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Stops the TIM Base generation. + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Base handle + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Peripheral */ + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM state */ + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Starts the TIM Base generation in interrupt mode. + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Base handle + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM state */ + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->State != HAL_TIM_STATE_READY) + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM state */ + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Update interrupt */ + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + ARM GAS /tmp/ccGFzgX3.s page 10 + + + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Stops the TIM Base generation in interrupt mode. + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Base handle + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Update interrupt */ + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Peripheral */ + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM state */ + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Starts the TIM Base generation in DMA mode. + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Base handle + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param pData The source Buffer address. + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Length The length of data to be transferred from memory to peripheral. + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t L + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM state */ + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->State == HAL_TIM_STATE_BUSY) + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_BUSY; + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (htim->State == HAL_TIM_STATE_READY) + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((pData == NULL) || (Length == 0U)) + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 11 + + + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA Period elapsed callbacks */ + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->A + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Update DMA request */ + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Stops the TIM Base generation in DMA mode. + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Base handle + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + ARM GAS /tmp/ccGFzgX3.s page 12 + + + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Update DMA request */ + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Peripheral */ + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM state */ + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @} + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM Output Compare functions + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ##### TIM Output Compare functions ##### + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** This section provides functions allowing to: + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Initialize and configure the TIM Output Compare. + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) De-initialize the TIM Output Compare. + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Start the TIM Output Compare. + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Stop the TIM Output Compare. + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Start the TIM Output Compare and enable interrupt. + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Stop the TIM Output Compare and disable interrupt. + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Start the TIM Output Compare and enable DMA transfer. + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Stop the TIM Output Compare and disable DMA transfer. + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @{ + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Initializes the TIM Output Compare according to the specified + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * parameters in the TIM_HandleTypeDef and initializes the associated handle. + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * requires a timer reset to avoid unexpected direction + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * due to DIR bit readonly in center aligned mode. + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Output Compare handle + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM handle allocation */ + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim == NULL) + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + ARM GAS /tmp/ccGFzgX3.s page 13 + + + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->State == HAL_TIM_STATE_RESET) + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Allocate lock resource and initialize it */ + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Lock = HAL_UNLOCKED; + 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset interrupt callbacks to legacy weak callbacks */ + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_ResetCallback(htim); + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->OC_MspInitCallback == NULL) + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC */ + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OC_MspInitCallback(htim); + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_OC_MspInit(htim); + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM state */ + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Init the base time for the Output Compare */ + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Initialize the DMA burst operation state */ + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Initialize the TIM channels state */ + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Initialize the TIM state*/ + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief DeInitializes the TIM peripheral + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Output Compare handle + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) + 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + ARM GAS /tmp/ccGFzgX3.s page 14 + + + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Peripheral Clock */ + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->OC_MspDeInitCallback == NULL) + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* DeInit the low level hardware */ + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OC_MspDeInitCallback(htim); + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_OC_MspDeInit(htim); + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change the DMA burst operation state */ + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change the TIM channels state */ + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change TIM state */ + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_RESET; + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Release Lock */ + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Initializes the TIM Output Compare MSP. + 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Output Compare handle + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, + 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_OC_MspInit could be implemented in the user file + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief DeInitializes TIM Output Compare MSP. + 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Output Compare handle + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 15 + + + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_OC_MspDeInit could be implemented in the user file + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Starts the TIM Output Compare signal generation. + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Output Compare handle + 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channel to be enabled + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_5: TIM Channel 5 selected + 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_6: TIM Channel 6 selected + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status + 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM channel state */ + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel state */ + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Output compare channel */ + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the main output */ + 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_MOE_ENABLE(htim); + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else + 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 16 + + + 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Stops the TIM Output Compare signal generation. + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Output Compare handle + 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channel to be disabled + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: + 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected + 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_5: TIM Channel 5 selected + 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_6: TIM Channel 6 selected + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status + 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Output compare channel */ + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Main Output */ + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_MOE_DISABLE(htim); + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Peripheral */ + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel state */ + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; + 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Starts the TIM Output Compare signal generation in interrupt mode. + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Output Compare handle + 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channel to be enabled + 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status + 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 17 + + + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM channel state */ + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel state */ + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) + 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 interrupt */ + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: + 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 interrupt */ + 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_3: + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 3 interrupt */ + 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_4: + 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 4 interrupt */ + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (status == HAL_OK) + 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Output compare channel */ + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 18 + + + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the main output */ + 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_MOE_ENABLE(htim); + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ + 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; + 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Stops the TIM Output Compare signal generation in interrupt mode. + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Output Compare handle + 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channel to be disabled + 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: + 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected + 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) + 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 interrupt */ + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 interrupt */ + 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 19 + + +1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_3: +1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 3 interrupt */ +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); +1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_4: +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 4 interrupt */ +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (status == HAL_OK) +1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Output compare channel */ +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); +1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) +1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Main Output */ +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_MOE_DISABLE(htim); +1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Peripheral */ +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel state */ +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Starts the TIM Output Compare signal generation in DMA mode. +1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Output Compare handle +1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channel to be enabled +1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param pData The source Buffer address. +1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Length The length of data to be transferred from memory to TIM peripheral +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *p +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint16_t Length) +1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 20 + + +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; +1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); +1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel state */ +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) +1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_BUSY; +1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) +1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((pData == NULL) || (Length == 0U)) +1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); +1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) +1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: +1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA compare callbacks */ +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; +1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; +1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance-> +1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) +1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 DMA request */ +1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); +1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: +1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA compare callbacks */ +1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; +1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 21 + + +1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; +1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance-> +1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) +1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 DMA request */ +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_3: +1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA compare callbacks */ +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; +1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; +1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance-> +1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) +1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 3 DMA request */ +1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); +1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_4: +1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA compare callbacks */ +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; +1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance-> +1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 4 DMA request */ +1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); +1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + ARM GAS /tmp/ccGFzgX3.s page 22 + + +1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (status == HAL_OK) +1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Output compare channel */ +1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); +1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) +1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the main output */ +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_MOE_ENABLE(htim); +1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) +1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Stops the TIM Output Compare signal generation in DMA mode. +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Output Compare handle +1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channel to be disabled +1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); +1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) +1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: + ARM GAS /tmp/ccGFzgX3.s page 23 + + +1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 DMA request */ +1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); +1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: +1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 DMA request */ +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_3: +1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 3 DMA request */ +1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); +1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); +1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_4: +1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 4 interrupt */ +1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); +1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); +1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (status == HAL_OK) +1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Output compare channel */ +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); +1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Main Output */ +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_MOE_DISABLE(htim); +1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Peripheral */ +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel state */ +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + ARM GAS /tmp/ccGFzgX3.s page 24 + + +1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @} +1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions +1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM PWM functions +1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * +1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim +1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== +1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ##### TIM PWM functions ##### +1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== +1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] +1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** This section provides functions allowing to: +1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Initialize and configure the TIM PWM. +1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) De-initialize the TIM PWM. +1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Start the TIM PWM. +1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Stop the TIM PWM. +1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Start the TIM PWM and enable interrupt. +1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Stop the TIM PWM and disable interrupt. +1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Start the TIM PWM and enable DMA transfer. +1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Stop the TIM PWM and disable DMA transfer. +1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim +1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @{ +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Initializes the TIM PWM Time Base according to the specified +1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * parameters in the TIM_HandleTypeDef and initializes the associated handle. +1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) +1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * requires a timer reset to avoid unexpected direction +1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * due to DIR bit readonly in center aligned mode. +1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM PWM handle +1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM handle allocation */ +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim == NULL) +1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); +1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); +1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); +1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); +1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->State == HAL_TIM_STATE_RESET) +1338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Allocate lock resource and initialize it */ +1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Lock = HAL_UNLOCKED; +1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + ARM GAS /tmp/ccGFzgX3.s page 25 + + +1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset interrupt callbacks to legacy weak callbacks */ +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_ResetCallback(htim); +1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->PWM_MspInitCallback == NULL) +1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; +1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC */ +1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_MspInitCallback(htim); +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ +1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_PWM_MspInit(htim); +1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM state */ +1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Init the base time for the PWM */ +1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); +1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Initialize the DMA burst operation state */ +1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_READY; +1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Initialize the TIM channels state */ +1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); +1370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Initialize the TIM state*/ +1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +1373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief DeInitializes the TIM peripheral +1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM PWM handle +1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +1382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Peripheral Clock */ +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->PWM_MspDeInitCallback == NULL) +1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* DeInit the low level hardware */ +1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_MspDeInitCallback(htim); +1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else + ARM GAS /tmp/ccGFzgX3.s page 26 + + +1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ +1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_PWM_MspDeInit(htim); +1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change the DMA burst operation state */ +1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; +1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change the TIM channels state */ +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); +1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); +1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change TIM state */ +1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_RESET; +1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Release Lock */ +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); +1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Initializes the TIM PWM MSP. +1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM PWM handle +1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); +1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_PWM_MspInit could be implemented in the user file +1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief DeInitializes TIM PWM MSP. +1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM PWM handle +1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); +1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +1446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_PWM_MspDeInit could be implemented in the user file +1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Starts the PWM signal generation. +1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +1455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + ARM GAS /tmp/ccGFzgX3.s page 27 + + +1457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_5: TIM Channel 5 selected +1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_6: TIM Channel 6 selected +1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +1463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; +1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM channel state */ +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) +1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +1474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel state */ +1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); +1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Capture compare channel */ +1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); +1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) +1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the main output */ +1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_MOE_ENABLE(htim); +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) +1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; +1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) +1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Stops the PWM signal generation. +1508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM PWM handle +1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to be disabled +1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +1511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + ARM GAS /tmp/ccGFzgX3.s page 28 + + +1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_5: TIM Channel 5 selected +1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_6: TIM Channel 6 selected +1517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Capture compare channel */ +1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); +1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) +1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Main Output */ +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_MOE_DISABLE(htim); +1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Peripheral */ +1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel state */ +1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +1538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +1541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +1544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Starts the PWM signal generation in interrupt mode. +1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM PWM handle +1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channel to be enabled +1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; +1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); +1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM channel state */ +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) +1564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +1566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel state */ +1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); +1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 29 + + +1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) +1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: +1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 interrupt */ +1576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); +1577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: +1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 interrupt */ +1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); +1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_3: +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 3 interrupt */ +1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); +1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_4: +1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 4 interrupt */ +1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); +1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +1602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +1603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (status == HAL_OK) +1607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Capture compare channel */ +1609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); +1610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) +1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the main output */ +1614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_MOE_ENABLE(htim); +1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) +1619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; +1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) +1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 30 + + +1628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +1629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +1637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Stops the PWM signal generation in interrupt mode. +1638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM PWM handle +1639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to be disabled +1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +1641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +1646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +1647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +1648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +1652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); +1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) +1655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: +1657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 interrupt */ +1659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); +1660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: +1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 interrupt */ +1666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); +1667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_3: +1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 3 interrupt */ +1673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); +1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_4: +1678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 4 interrupt */ +1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); +1681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: + ARM GAS /tmp/ccGFzgX3.s page 31 + + +1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (status == HAL_OK) +1690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Capture compare channel */ +1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); +1693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) +1695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Main Output */ +1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_MOE_DISABLE(htim); +1698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Peripheral */ +1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel state */ +1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Starts the TIM PWM signal generation in DMA mode. +1713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM PWM handle +1714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param pData The source Buffer address. +1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Length The length of data to be transferred from memory to TIM peripheral +1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +1723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t * +1725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint16_t Length) +1726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; +1729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +1731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); +1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel state */ +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) +1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_BUSY; +1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) +1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((pData == NULL) || (Length == 0U)) +1741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 32 + + +1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +1743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +1745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); +1747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +1752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) +1755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: +1757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA compare callbacks */ +1759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; +1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; +1761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +1763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; +1764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance-> +1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) +1768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +1770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +1771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 DMA request */ +1774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); +1775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: +1779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA compare callbacks */ +1781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; +1782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; +1783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +1785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; +1786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance-> +1789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) +1790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +1792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +1793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 DMA request */ +1795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); +1796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 33 + + +1799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_3: +1800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA compare callbacks */ +1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; +1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; +1804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; +1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance-> +1810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) +1811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +1813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Output Capture/Compare 3 request */ +1816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); +1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_4: +1821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA compare callbacks */ +1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; +1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; +1825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +1827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; +1828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance-> +1831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) +1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +1834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +1835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 4 DMA request */ +1837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); +1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +1842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +1843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (status == HAL_OK) +1847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Capture compare channel */ +1849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); +1850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) +1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the main output */ +1854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_MOE_ENABLE(htim); +1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + ARM GAS /tmp/ccGFzgX3.s page 34 + + +1856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge +1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) +1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; +1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) +1862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +1867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +1869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +1873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +1874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +1877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Stops the TIM PWM signal generation in DMA mode. +1878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM PWM handle +1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to be disabled +1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +1881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +1886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +1887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +1888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +1890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +1892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); +1893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) +1895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: +1897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 DMA request */ +1899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); +1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); +1901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: +1905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 DMA request */ +1907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); +1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); +1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_3: + ARM GAS /tmp/ccGFzgX3.s page 35 + + +1913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 3 DMA request */ +1915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); +1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); +1917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_4: +1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 4 interrupt */ +1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); +1924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); +1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +1929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +1930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +1931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (status == HAL_OK) +1934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Capture compare channel */ +1936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); +1937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) +1939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Main Output */ +1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_MOE_DISABLE(htim); +1942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Peripheral */ +1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +1946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel state */ +1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +1949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +1952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @} +1957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions +1960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM Input Capture functions +1961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * +1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim +1963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== +1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ##### TIM Input Capture functions ##### +1965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== +1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] +1967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** This section provides functions allowing to: +1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Initialize and configure the TIM Input Capture. +1969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) De-initialize the TIM Input Capture. + ARM GAS /tmp/ccGFzgX3.s page 36 + + +1970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Start the TIM Input Capture. +1971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Stop the TIM Input Capture. +1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Start the TIM Input Capture and enable interrupt. +1973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Stop the TIM Input Capture and disable interrupt. +1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Start the TIM Input Capture and enable DMA transfer. +1975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Stop the TIM Input Capture and disable DMA transfer. +1976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim +1978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @{ +1979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +1980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +1981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Initializes the TIM Input Capture Time base according to the specified +1982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * parameters in the TIM_HandleTypeDef and initializes the associated handle. +1983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) +1984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * requires a timer reset to avoid unexpected direction +1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * due to DIR bit readonly in center aligned mode. +1986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() +1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Input Capture handle +1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +1990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM handle allocation */ +1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim == NULL) +1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +1996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +1998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +2000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); +2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); +2002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); +2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); +2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->State == HAL_TIM_STATE_RESET) +2006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Allocate lock resource and initialize it */ +2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Lock = HAL_UNLOCKED; +2009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +2011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset interrupt callbacks to legacy weak callbacks */ +2012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_ResetCallback(htim); +2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->IC_MspInitCallback == NULL) +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; +2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC */ +2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_MspInitCallback(htim); +2020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +2021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ +2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_IC_MspInit(htim); +2023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +2024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM state */ + ARM GAS /tmp/ccGFzgX3.s page 37 + + +2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Init the base time for the input capture */ +2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); +2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Initialize the DMA burst operation state */ +2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_READY; +2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Initialize the TIM channels state */ +2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); +2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Initialize the TIM state*/ +2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +2041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +2046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief DeInitializes the TIM peripheral +2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Input Capture handle +2048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +2049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +2054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Peripheral Clock */ +2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->IC_MspDeInitCallback == NULL) +2062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; +2064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* DeInit the low level hardware */ +2066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_MspDeInitCallback(htim); +2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +2068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ +2069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_IC_MspDeInit(htim); +2070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change the DMA burst operation state */ +2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; +2074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change the TIM channels state */ +2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); +2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); +2078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change TIM state */ +2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_RESET; +2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Release Lock */ +2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); + ARM GAS /tmp/ccGFzgX3.s page 38 + + +2084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +2086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Initializes the TIM Input Capture MSP. +2090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Input Capture handle +2091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +2092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +2094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +2096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); +2097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +2099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_IC_MspInit could be implemented in the user file +2100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +2104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief DeInitializes TIM Input Capture MSP. +2105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +2106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +2107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +2109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +2111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); +2112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +2114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_IC_MspDeInit could be implemented in the user file +2115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +2119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Starts the TIM Input Capture measurement. +2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Input Capture handle +2121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +2123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +2126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +2127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +2128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +2130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; +2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); +2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); +2134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +2136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); +2137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM channel state */ +2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) +2140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + ARM GAS /tmp/ccGFzgX3.s page 39 + + +2141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +2143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel state */ +2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); +2148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Input Capture channel */ +2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); +2151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger +2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) +2154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; +2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) +2157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +2159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +2164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +2168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +2171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Stops the TIM Input Capture measurement. +2172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Input Capture handle +2173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to be disabled +2174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +2175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +2178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +2179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +2180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +2182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); +2185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Input Capture channel */ +2187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); +2188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Peripheral */ +2190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +2191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel state */ +2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +2195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +2197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; + ARM GAS /tmp/ccGFzgX3.s page 40 + + +2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +2201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Starts the TIM Input Capture measurement in interrupt mode. +2202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Input Capture handle +2203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +2205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +2208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +2209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +2212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +2214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; +2215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); +2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); +2218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +2220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); +2221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM channel state */ +2223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) +2224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) +2225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +2227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel state */ +2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); +2232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) +2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: +2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 interrupt */ +2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); +2239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: +2243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 interrupt */ +2245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); +2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_3: +2250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 3 interrupt */ +2252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); +2253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + ARM GAS /tmp/ccGFzgX3.s page 41 + + +2255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_4: +2257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 4 interrupt */ +2259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); +2260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +2264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +2265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (status == HAL_OK) +2269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Input Capture channel */ +2271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); +2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge +2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) +2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; +2277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) +2278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +2280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +2283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +2285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +2289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +2293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Stops the TIM Input Capture measurement in interrupt mode. +2294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Input Capture handle +2295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to be disabled +2296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +2297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +2300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +2301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +2302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +2304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +2306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +2308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); +2309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) +2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 42 + + +2312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: +2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 interrupt */ +2315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); +2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: +2320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 interrupt */ +2322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); +2323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_3: +2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 3 interrupt */ +2329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); +2330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_4: +2334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 4 interrupt */ +2336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); +2337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +2341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +2342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (status == HAL_OK) +2346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Input Capture channel */ +2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); +2349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Peripheral */ +2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +2352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel state */ +2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +2356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +2359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +2363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Starts the TIM Input Capture measurement in DMA mode. +2364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Input Capture handle +2365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +2366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +2367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + ARM GAS /tmp/ccGFzgX3.s page 43 + + +2369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +2370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +2371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param pData The destination Buffer address. +2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Length The length of data to be transferred from TIM peripheral to memory. +2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +2374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, +2376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +2378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; +2379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); +2382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +2384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); +2385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); +2386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel state */ +2388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) +2389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) +2390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_BUSY; +2392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) +2394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) +2395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((pData == NULL) || (Length == 0U)) +2397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +2399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +2401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); +2404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +2407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Input Capture channel */ +2412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); +2413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) +2415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: +2417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA capture callbacks */ +2419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; +2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; +2421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; +2424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ + ARM GAS /tmp/ccGFzgX3.s page 44 + + +2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)p +2427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) +2428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +2430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +2431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 DMA request */ +2433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); +2434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: +2438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA capture callbacks */ +2440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; +2441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; +2442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +2444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; +2445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +2447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)p +2448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) +2449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +2451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 DMA request */ +2454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); +2455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_3: +2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA capture callbacks */ +2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; +2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; +2463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; +2466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)p +2469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) +2470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +2472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +2473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 3 DMA request */ +2475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); +2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_4: +2480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA capture callbacks */ +2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + ARM GAS /tmp/ccGFzgX3.s page 45 + + +2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; +2484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +2486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; +2487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +2489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)p +2490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) +2491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +2493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +2494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 4 DMA request */ +2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); +2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +2501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger +2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) +2507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; +2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) +2510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +2512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +2515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +2517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +2520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +2521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +2524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Stops the TIM Input Capture measurement in DMA mode. +2525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Input Capture handle +2526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to be disabled +2527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +2528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +2532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +2533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +2535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +2537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +2539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + ARM GAS /tmp/ccGFzgX3.s page 46 + + +2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); +2541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Input Capture channel */ +2543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); +2544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) +2546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: +2548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 DMA request */ +2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); +2551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); +2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: +2556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 DMA request */ +2558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); +2559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); +2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_3: +2564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 3 DMA request */ +2566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); +2567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); +2568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_4: +2572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 4 DMA request */ +2574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); +2575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); +2576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +2580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +2581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +2582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (status == HAL_OK) +2585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Peripheral */ +2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel state */ +2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +2592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +2595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +2596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + ARM GAS /tmp/ccGFzgX3.s page 47 + + +2597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +2598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @} +2599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions +2602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM One Pulse functions +2603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * +2604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim +2605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== +2606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ##### TIM One Pulse functions ##### +2607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== +2608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] +2609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** This section provides functions allowing to: +2610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Initialize and configure the TIM One Pulse. +2611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) De-initialize the TIM One Pulse. +2612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Start the TIM One Pulse. +2613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Stop the TIM One Pulse. +2614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Start the TIM One Pulse and enable interrupt. +2615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Stop the TIM One Pulse and disable interrupt. +2616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Start the TIM One Pulse and enable DMA transfer. +2617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Stop the TIM One Pulse and disable DMA transfer. +2618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim +2620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @{ +2621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +2623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Initializes the TIM One Pulse Time Base according to the specified +2624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * parameters in the TIM_HandleTypeDef and initializes the associated handle. +2625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) +2626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * requires a timer reset to avoid unexpected direction +2627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * due to DIR bit readonly in center aligned mode. +2628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() +2629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note When the timer instance is initialized in One Pulse mode, timer +2630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * channels 1 and channel 2 are reserved and cannot be used for other +2631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * purpose. +2632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM One Pulse handle +2633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param OnePulseMode Select the One pulse mode. +2634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +2635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. +2636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. +2637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +2638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +2640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM handle allocation */ +2642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim == NULL) +2643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +2645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +2648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +2649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); +2650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); +2651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OPM_MODE(OnePulseMode)); +2652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); +2653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + ARM GAS /tmp/ccGFzgX3.s page 48 + + +2654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->State == HAL_TIM_STATE_RESET) +2656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Allocate lock resource and initialize it */ +2658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Lock = HAL_UNLOCKED; +2659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +2661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset interrupt callbacks to legacy weak callbacks */ +2662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_ResetCallback(htim); +2663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->OnePulse_MspInitCallback == NULL) +2665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; +2667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC */ +2669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OnePulse_MspInitCallback(htim); +2670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +2671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ +2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_OnePulse_MspInit(htim); +2673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +2674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM state */ +2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +2678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the Time base in the One Pulse Mode */ +2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); +2681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the OPM Bit */ +2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CR1 &= ~TIM_CR1_OPM; +2684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the OPM Mode */ +2686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CR1 |= OnePulseMode; +2687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Initialize the DMA burst operation state */ +2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_READY; +2690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Initialize the TIM channels state */ +2692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +2693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +2694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +2695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +2696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Initialize the TIM state*/ +2698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +2699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +2701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +2704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief DeInitializes the TIM One Pulse +2705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM One Pulse handle +2706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +2707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +2709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + ARM GAS /tmp/ccGFzgX3.s page 49 + + +2711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +2712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +2714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Peripheral Clock */ +2716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +2717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +2719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->OnePulse_MspDeInitCallback == NULL) +2720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; +2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* DeInit the low level hardware */ +2724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OnePulse_MspDeInitCallback(htim); +2725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +2726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ +2727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_OnePulse_MspDeInit(htim); +2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +2729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change the DMA burst operation state */ +2731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; +2732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel state */ +2734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); +2735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); +2736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); +2737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); +2738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change TIM state */ +2740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_RESET; +2741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Release Lock */ +2743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); +2744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +2746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +2749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Initializes the TIM One Pulse MSP. +2750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM One Pulse handle +2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +2752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +2756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); +2757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +2759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_OnePulse_MspInit could be implemented in the user file +2760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +2764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief DeInitializes TIM One Pulse MSP. +2765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM One Pulse handle +2766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +2767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + ARM GAS /tmp/ccGFzgX3.s page 50 + + +2768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +2769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); +2772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +2774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file +2775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +2779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Starts the TIM One Pulse signal generation. +2780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note Though OutputChannel parameter is deprecated and ignored by the function +2781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * it has been kept to avoid HAL_TIM API compatibility break. +2782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note The pulse output channel is determined when calling +2783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @ref HAL_TIM_OnePulse_ConfigChannel(). +2784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM One Pulse handle +2785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param OutputChannel See note above +2786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +2787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +2789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); +2791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); +2792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA +2793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA +2794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +2796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(OutputChannel); +2797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM channels state */ +2799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) +2800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) +2801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) +2802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) +2803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +2805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channels state */ +2808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +2809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +2810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +2811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +2812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Capture compare and the Input Capture channels +2814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2 +2815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and +2816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output +2817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together +2818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** No need to enable the counter, it's enabled automatically by hardware +2820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (the counter starts in response to a stimulus and generate a pulse */ +2821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); +2823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); +2824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 51 + + +2825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) +2826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the main output */ +2828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_MOE_ENABLE(htim); +2829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +2832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +2833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +2836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Stops the TIM One Pulse signal generation. +2837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note Though OutputChannel parameter is deprecated and ignored by the function +2838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * it has been kept to avoid HAL_TIM API compatibility break. +2839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note The pulse output channel is determined when calling +2840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @ref HAL_TIM_OnePulse_ConfigChannel(). +2841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM One Pulse handle +2842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param OutputChannel See note above +2843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +2844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +2846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +2848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(OutputChannel); +2849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Capture compare and the Input Capture channels +2851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) +2852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and +2853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output +2854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ +2855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); +2857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); +2858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) +2860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Main Output */ +2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_MOE_DISABLE(htim); +2863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Peripheral */ +2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +2867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channels state */ +2869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +2870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +2871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +2872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +2873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +2875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +2876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +2879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Starts the TIM One Pulse signal generation in interrupt mode. +2880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note Though OutputChannel parameter is deprecated and ignored by the function +2881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * it has been kept to avoid HAL_TIM API compatibility break. + ARM GAS /tmp/ccGFzgX3.s page 52 + + +2882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note The pulse output channel is determined when calling +2883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @ref HAL_TIM_OnePulse_ConfigChannel(). +2884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM One Pulse handle +2885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param OutputChannel See note above +2886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +2887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +2889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); +2891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); +2892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA +2893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA +2894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +2896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(OutputChannel); +2897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM channels state */ +2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) +2900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) +2901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) +2902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) +2903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +2905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channels state */ +2908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +2909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +2910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +2911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +2912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Capture compare and the Input Capture channels +2914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2 +2915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and +2916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output +2917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together +2918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** No need to enable the counter, it's enabled automatically by hardware +2920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (the counter starts in response to a stimulus and generate a pulse */ +2921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 interrupt */ +2923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); +2924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 interrupt */ +2926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); +2927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); +2929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); +2930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) +2932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the main output */ +2934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_MOE_ENABLE(htim); +2935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +2938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; + ARM GAS /tmp/ccGFzgX3.s page 53 + + +2939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +2942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Stops the TIM One Pulse signal generation in interrupt mode. +2943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note Though OutputChannel parameter is deprecated and ignored by the function +2944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * it has been kept to avoid HAL_TIM API compatibility break. +2945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note The pulse output channel is determined when calling +2946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @ref HAL_TIM_OnePulse_ConfigChannel(). +2947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM One Pulse handle +2948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param OutputChannel See note above +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +2950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +2952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +2954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(OutputChannel); +2955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 interrupt */ +2957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); +2958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 interrupt */ +2960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); +2961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Capture compare and the Input Capture channels +2963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) +2964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and +2965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output +2966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ +2967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); +2968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); +2969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) +2971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +2972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Main Output */ +2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_MOE_DISABLE(htim); +2974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Peripheral */ +2977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +2978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channels state */ +2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +2981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +2982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +2983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +2984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +2986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +2987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +2988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +2990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @} +2991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +2992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +2993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions +2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM Encoder functions +2995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * + ARM GAS /tmp/ccGFzgX3.s page 54 + + +2996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim +2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== +2998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ##### TIM Encoder functions ##### +2999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== +3000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] +3001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** This section provides functions allowing to: +3002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Initialize and configure the TIM Encoder. +3003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) De-initialize the TIM Encoder. +3004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Start the TIM Encoder. +3005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Stop the TIM Encoder. +3006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Start the TIM Encoder and enable interrupt. +3007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Stop the TIM Encoder and disable interrupt. +3008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Start the TIM Encoder and enable DMA transfer. +3009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Stop the TIM Encoder and disable DMA transfer. +3010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim +3012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @{ +3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +3014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +3015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Initializes the TIM Encoder Interface and initialize the associated handle. +3016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) +3017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * requires a timer reset to avoid unexpected direction +3018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * due to DIR bit readonly in center aligned mode. +3019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() +3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note Encoder mode and External clock mode 2 are not compatible and must not be selected toge +3021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_Config +3022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa +3023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note When the timer instance is initialized in Encoder mode, timer +3024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * channels 1 and channel 2 are reserved and cannot be used for other +3025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * purpose. +3026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +3027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param sConfig TIM Encoder Interface configuration structure +3028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +3029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +3030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sCon +3031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; +3033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmr1; +3034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccer; +3035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM handle allocation */ +3037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim == NULL) +3038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +3040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +3043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); +3044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); +3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); +3046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); +3047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); +3048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); +3049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); +3050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); +3051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); +3052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + ARM GAS /tmp/ccGFzgX3.s page 55 + + +3053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); +3054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); +3055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); +3056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); +3057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->State == HAL_TIM_STATE_RESET) +3059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Allocate lock resource and initialize it */ +3061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Lock = HAL_UNLOCKED; +3062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset interrupt callbacks to legacy weak callbacks */ +3065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_ResetCallback(htim); +3066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->Encoder_MspInitCallback == NULL) +3068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; +3070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC */ +3072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Encoder_MspInitCallback(htim); +3073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +3074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ +3075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_Encoder_MspInit(htim); +3076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM state */ +3080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +3081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the SMS and ECE bits */ +3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); +3084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the Time base in the Encoder Mode */ +3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); +3087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx SMCR register value */ +3089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR; +3090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CCMR1 register value */ +3092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 = htim->Instance->CCMR1; +3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CCER register value */ +3095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer = htim->Instance->CCER; +3096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the encoder Mode */ +3098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr |= sConfig->EncoderMode; +3099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Capture Compare 1 and the Capture Compare 2 as input */ +3101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); +3102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); +3103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ +3105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); +3106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); +3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); +3108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); +3109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 56 + + +3110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TI1 and the TI2 Polarities */ +3111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); +3112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); +3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); +3114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx SMCR */ +3116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR = tmpsmcr; +3117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCMR1 */ +3119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 = tmpccmr1; +3120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCER */ +3122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCER = tmpccer; +3123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Initialize the DMA burst operation state */ +3125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_READY; +3126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channels state */ +3128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +3129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +3130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +3131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +3132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Initialize the TIM state*/ +3134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +3135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +3137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +3141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief DeInitializes the TIM Encoder interface +3142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +3143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +3144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +3145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +3146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +3148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +3151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Peripheral Clock */ +3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +3154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->Encoder_MspDeInitCallback == NULL) +3157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; +3159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* DeInit the low level hardware */ +3161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Encoder_MspDeInitCallback(htim); +3162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +3163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ +3164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_Encoder_MspDeInit(htim); +3165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 57 + + +3167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change the DMA burst operation state */ +3168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; +3169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channels state */ +3171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); +3172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); +3173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); +3174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); +3175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change TIM state */ +3177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_RESET; +3178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Release Lock */ +3180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); +3181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +3183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +3186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Initializes the TIM Encoder Interface MSP. +3187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +3188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +3189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +3190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +3191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +3193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); +3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +3196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_Encoder_MspInit could be implemented in the user file +3197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +3198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +3201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief DeInitializes TIM Encoder Interface MSP. +3202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +3203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +3204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +3205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +3206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +3208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); +3209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +3211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_Encoder_MspDeInit could be implemented in the user file +3212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +3213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +3216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Starts the TIM Encoder Interface. +3217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +3218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +3219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +3220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +3221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +3222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected +3223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status + ARM GAS /tmp/ccGFzgX3.s page 58 + + +3224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +3225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +3226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); +3228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); +3229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA +3230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA +3231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +3233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); +3234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel(s) state */ +3236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (Channel == TIM_CHANNEL_1) +3237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) +3239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) +3240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +3242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +3246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +3247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (Channel == TIM_CHANNEL_2) +3250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) +3252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) +3253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +3255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +3259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +3260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) +3265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) +3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) +3267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) +3268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +3270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +3274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +3275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +3276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +3277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the encoder interface channels */ + ARM GAS /tmp/ccGFzgX3.s page 59 + + +3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) +3282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: +3284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); +3286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +3287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: +3290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); +3292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +3293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default : +3296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); +3298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); +3299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +3300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Peripheral */ +3303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +3304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +3306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +3307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +3310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Stops the TIM Encoder Interface. +3311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +3312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to be disabled +3313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +3314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +3315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +3316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected +3317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +3318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +3319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +3320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +3322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); +3323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Input Capture channels 1 and 2 +3325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_C +3326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) +3327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: +3329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); +3331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +3332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: +3335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); +3337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + ARM GAS /tmp/ccGFzgX3.s page 60 + + +3338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default : +3341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); +3343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); +3344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +3345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Peripheral */ +3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +3350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel(s) state */ +3352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) +3353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +3356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +3360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +3361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +3362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +3363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +3366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +3367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +3370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Starts the TIM Encoder Interface in interrupt mode. +3371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +3372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +3373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +3374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +3375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +3376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected +3377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +3378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +3379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +3380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); +3382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); +3383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA +3384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA +3385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +3387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); +3388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel(s) state */ +3390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (Channel == TIM_CHANNEL_1) +3391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) +3393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) +3394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 61 + + +3395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +3396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +3400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +3401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (Channel == TIM_CHANNEL_2) +3404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) +3406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) +3407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +3409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +3413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +3414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) +3419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) +3420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) +3421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) +3422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +3424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +3428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +3429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +3430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +3431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the encoder interface channels */ +3435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the capture compare Interrupts 1 and/or 2 */ +3436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) +3437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: +3439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); +3441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); +3442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +3443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: +3446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); +3448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); +3449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +3450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 62 + + +3452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default : +3453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); +3455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); +3456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); +3457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); +3458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +3459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Peripheral */ +3463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +3464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +3466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +3467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +3470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Stops the TIM Encoder Interface in interrupt mode. +3471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to be disabled +3473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +3474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +3475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +3476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected +3477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +3478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +3479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +3480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +3482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); +3483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Input Capture channels 1 and 2 +3485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_C +3486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (Channel == TIM_CHANNEL_1) +3487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); +3489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the capture compare Interrupts 1 */ +3491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); +3492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (Channel == TIM_CHANNEL_2) +3494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); +3496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the capture compare Interrupts 2 */ +3498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); +3499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); +3503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); +3504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the capture compare Interrupts 1 and 2 */ +3506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); +3507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); +3508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + ARM GAS /tmp/ccGFzgX3.s page 63 + + +3509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Peripheral */ +3511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); +3512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel(s) state */ +3514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) +3515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +3518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +3522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +3523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +3524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +3525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +3528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +3529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +3532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Starts the TIM Encoder Interface in DMA mode. +3533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +3534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +3535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +3536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +3537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +3538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected +3539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param pData1 The destination Buffer address for IC1. +3540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param pData2 The destination Buffer address for IC2. +3541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Length The length of data to be transferred from TIM peripheral to memory. +3542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +3543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +3544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pD +3545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t *pData2, uint16_t Length) +3546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); +3548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); +3549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA +3550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA +3551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +3553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); +3554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel(s) state */ +3556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (Channel == TIM_CHANNEL_1) +3557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) +3559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) +3560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_BUSY; +3562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) +3564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) +3565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 64 + + +3566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((pData1 == NULL) || (Length == 0U)) +3567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +3569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +3573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +3574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +3579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (Channel == TIM_CHANNEL_2) +3582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) +3584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) +3585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_BUSY; +3587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) +3589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) +3590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((pData2 == NULL) || (Length == 0U)) +3592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +3594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +3598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +3599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +3604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) +3609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) +3610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) +3611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) +3612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_BUSY; +3614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) +3616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) +3617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) +3618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) +3619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) +3621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + ARM GAS /tmp/ccGFzgX3.s page 65 + + +3623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +3627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +3628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +3629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +3630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +3635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) +3639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: +3641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA capture callbacks */ +3643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; +3644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; +3645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +3647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; +3648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +3650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)p +3651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) +3652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +3654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +3655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Input Capture DMA request */ +3657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); +3658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Capture compare channel */ +3660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); +3661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Peripheral */ +3663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +3664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +3666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: +3669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA capture callbacks */ +3671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; +3672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; +3673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +3675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; +3676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +3677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)p +3678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) +3679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 66 + + +3680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +3681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +3682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Input Capture DMA request */ +3684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); +3685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Capture compare channel */ +3687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); +3688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Peripheral */ +3690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +3691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +3693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +3696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA capture callbacks */ +3698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; +3699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; +3700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +3702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; +3703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +3705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)p +3706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) +3707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +3710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA capture callbacks */ +3713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; +3714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; +3715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +3717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; +3718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +3720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)p +3721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) +3722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +3724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +3725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Input Capture DMA request */ +3728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); +3729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Input Capture DMA request */ +3730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); +3731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Capture compare channel */ +3733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); +3734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); +3735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the Peripheral */ + ARM GAS /tmp/ccGFzgX3.s page 67 + + +3737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); +3738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +3740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +3744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +3745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +3748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Stops the TIM Encoder Interface in DMA mode. +3749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +3750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +3751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +3752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +3753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +3754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected +3755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +3756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +3757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +3758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +3760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); +3761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Input Capture channels 1 and 2 +3763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_C +3764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (Channel == TIM_CHANNEL_1) +3765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); +3767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the capture compare DMA Request 1 */ +3769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); +3770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); +3771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (Channel == TIM_CHANNEL_2) +3773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); +3775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the capture compare DMA Request 2 */ +3777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); +3778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); +3779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); +3783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); +3784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the capture compare DMA Request 1 and 2 */ +3786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); +3787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); +3788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); +3789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); +3790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Peripheral */ +3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + ARM GAS /tmp/ccGFzgX3.s page 68 + + +3794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TIM channel(s) state */ +3796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) +3797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +3800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +3804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +3805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +3806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +3807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +3810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +3811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +3814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @} +3815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +3816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management +3817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM IRQ handler management +3818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * +3819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim +3820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== +3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ##### IRQ handler management ##### +3822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== +3823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] +3824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** This section provides Timer IRQ handler function. +3825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim +3827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @{ +3828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +3829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +3830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief This function handles TIM interrupts requests. +3831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +3832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +3833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +3834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +3835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t itsource = htim->Instance->DIER; +3837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t itflag = htim->Instance->SR; +3838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Capture compare 1 event */ +3840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) +3841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) +3843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); +3846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; +3847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +3848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Input capture event */ +3849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) +3850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 69 + + +3851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_CaptureCallback(htim); +3853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +3854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_IC_CaptureCallback(htim); +3855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Output compare event */ +3858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OC_DelayElapsedCallback(htim); +3862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_PulseFinishedCallback(htim); +3863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +3864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_OC_DelayElapsedCallback(htim); +3865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); +3866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +3869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Capture compare 2 event */ +3873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) +3874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) +3876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); +3878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; +3879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Input capture event */ +3880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) +3881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_CaptureCallback(htim); +3884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +3885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_IC_CaptureCallback(htim); +3886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Output compare event */ +3889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OC_DelayElapsedCallback(htim); +3893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_PulseFinishedCallback(htim); +3894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +3895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_OC_DelayElapsedCallback(htim); +3896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); +3897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +3900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Capture compare 3 event */ +3903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) +3904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) +3906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); + ARM GAS /tmp/ccGFzgX3.s page 70 + + +3908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; +3909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Input capture event */ +3910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) +3911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_CaptureCallback(htim); +3914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +3915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_IC_CaptureCallback(htim); +3916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Output compare event */ +3919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OC_DelayElapsedCallback(htim); +3923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_PulseFinishedCallback(htim); +3924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +3925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_OC_DelayElapsedCallback(htim); +3926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); +3927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +3930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Capture compare 4 event */ +3933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) +3934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) +3936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); +3938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; +3939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Input capture event */ +3940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) +3941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_CaptureCallback(htim); +3944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +3945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_IC_CaptureCallback(htim); +3946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Output compare event */ +3949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +3950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OC_DelayElapsedCallback(htim); +3953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_PulseFinishedCallback(htim); +3954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +3955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_OC_DelayElapsedCallback(htim); +3956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); +3957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +3960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* TIM Update event */ +3963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) +3964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 71 + + +3965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) +3966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); +3968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PeriodElapsedCallback(htim); +3970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +3971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_PeriodElapsedCallback(htim); +3972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* TIM Break input event */ +3976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ +3977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) +3978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) +3980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); +3982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->BreakCallback(htim); +3984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +3985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIMEx_BreakCallback(htim); +3986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +3989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* TIM Break2 input event */ +3990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) +3991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) +3993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +3994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); +3995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Break2Callback(htim); +3997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +3998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIMEx_Break2Callback(htim); +3999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +4000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* TIM Trigger detection event */ +4003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) +4004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) +4006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); +4008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +4009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->TriggerCallback(htim); +4010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +4011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_TriggerCallback(htim); +4012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +4013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* TIM commutation event */ +4016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) +4017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) +4019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); +4021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + ARM GAS /tmp/ccGFzgX3.s page 72 + + +4022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->CommutationCallback(htim); +4023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +4024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIMEx_CommutCallback(htim); +4025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +4026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +4031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @} +4032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +4033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions +4035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM Peripheral Control functions +4036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * +4037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim +4038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== +4039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ##### Peripheral Control functions ##### +4040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== +4041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] +4042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** This section provides functions allowing to: +4043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. +4044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Configure External Clock source. +4045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Configure Complementary channels, break features and dead time. +4046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Configure Master and the Slave synchronization. +4047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) Configure the DMA Burst Mode. +4048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim +4050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @{ +4051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +4052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +4054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Initializes the TIM Output Compare Channels according to the specified +4055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * parameters in the TIM_OC_InitTypeDef. +4056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Output Compare handle +4057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param sConfig TIM Output Compare configuration structure +4058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to configure +4059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +4060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +4061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +4062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +4063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +4064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_5: TIM Channel 5 selected +4065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_6: TIM Channel 6 selected +4066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +4067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +4068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, +4069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** const TIM_OC_InitTypeDef *sConfig, +4070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t Channel) +4071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +4073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +4075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CHANNELS(Channel)); +4076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); +4077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); +4078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 73 + + +4079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Process Locked */ +4080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_LOCK(htim); +4081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) +4083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: +4085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +4087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +4088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the TIM Channel 1 in Output Compare */ +4090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_OC1_SetConfig(htim->Instance, sConfig); +4091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: +4095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +4097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +4098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the TIM Channel 2 in Output Compare */ +4100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_OC2_SetConfig(htim->Instance, sConfig); +4101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_3: +4105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +4107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); +4108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the TIM Channel 3 in Output Compare */ +4110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_OC3_SetConfig(htim->Instance, sConfig); +4111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_4: +4115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +4117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); +4118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the TIM Channel 4 in Output Compare */ +4120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_OC4_SetConfig(htim->Instance, sConfig); +4121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_5: +4125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +4127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); +4128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the TIM Channel 5 in Output Compare */ +4130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_OC5_SetConfig(htim->Instance, sConfig); +4131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_6: +4135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 74 + + +4136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +4137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); +4138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the TIM Channel 6 in Output Compare */ +4140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_OC6_SetConfig(htim->Instance, sConfig); +4141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +4145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +4146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); +4150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +4152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +4155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Initializes the TIM Input Capture Channels according to the specified +4156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * parameters in the TIM_IC_InitTypeDef. +4157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM IC handle +4158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param sConfig TIM Input Capture configuration structure +4159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channel to configure +4160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +4161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +4162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +4163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +4164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +4165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +4166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +4167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConf +4168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +4170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +4172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +4173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); +4174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); +4175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); +4176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); +4177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Process Locked */ +4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_LOCK(htim); +4180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (Channel == TIM_CHANNEL_1) +4182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* TI1 Configuration */ +4184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_TI1_SetConfig(htim->Instance, +4185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, +4186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICSelection, +4187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICFilter); +4188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the IC1PSC Bits */ +4190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; +4191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the IC1PSC value */ + ARM GAS /tmp/ccGFzgX3.s page 75 + + +4193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 |= sConfig->ICPrescaler; +4194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (Channel == TIM_CHANNEL_2) +4196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* TI2 Configuration */ +4198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +4199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_TI2_SetConfig(htim->Instance, +4201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, +4202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICSelection, +4203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICFilter); +4204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the IC2PSC Bits */ +4206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; +4207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the IC2PSC value */ +4209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); +4210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (Channel == TIM_CHANNEL_3) +4212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* TI3 Configuration */ +4214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); +4215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_TI3_SetConfig(htim->Instance, +4217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, +4218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICSelection, +4219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICFilter); +4220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the IC3PSC Bits */ +4222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; +4223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the IC3PSC value */ +4225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR2 |= sConfig->ICPrescaler; +4226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (Channel == TIM_CHANNEL_4) +4228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* TI4 Configuration */ +4230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); +4231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_TI4_SetConfig(htim->Instance, +4233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, +4234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICSelection, +4235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICFilter); +4236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the IC4PSC Bits */ +4238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; +4239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the IC4PSC value */ +4241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); +4242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +4244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +4246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); +4249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 76 + + +4250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +4251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +4254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Initializes the TIM PWM channels according to the specified +4255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * parameters in the TIM_OC_InitTypeDef. +4256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM PWM handle +4257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param sConfig TIM PWM configuration structure +4258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to be configured +4259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +4260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +4261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +4262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +4263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +4264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_5: TIM Channel 5 selected +4265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_6: TIM Channel 6 selected +4266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +4267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +4268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, +4269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** const TIM_OC_InitTypeDef *sConfig, +4270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t Channel) +4271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +4273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +4275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CHANNELS(Channel)); +4276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); +4277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); +4278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); +4279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Process Locked */ +4281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_LOCK(htim); +4282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) +4284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: +4286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +4288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +4289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the Channel 1 in PWM mode */ +4291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_OC1_SetConfig(htim->Instance, sConfig); +4292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Preload enable bit for channel1 */ +4294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; +4295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the Output Fast mode */ +4297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; +4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 |= sConfig->OCFastMode; +4299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: +4303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +4305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +4306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 77 + + +4307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the Channel 2 in PWM mode */ +4308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_OC2_SetConfig(htim->Instance, sConfig); +4309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Preload enable bit for channel2 */ +4311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; +4312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the Output Fast mode */ +4314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; +4315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; +4316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_3: +4320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +4322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); +4323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the Channel 3 in PWM mode */ +4325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_OC3_SetConfig(htim->Instance, sConfig); +4326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Preload enable bit for channel3 */ +4328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; +4329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the Output Fast mode */ +4331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; +4332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR2 |= sConfig->OCFastMode; +4333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_4: +4337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +4339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); +4340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the Channel 4 in PWM mode */ +4342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_OC4_SetConfig(htim->Instance, sConfig); +4343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Preload enable bit for channel4 */ +4345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; +4346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the Output Fast mode */ +4348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; +4349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; +4350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_5: +4354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +4356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); +4357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the Channel 5 in PWM mode */ +4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_OC5_SetConfig(htim->Instance, sConfig); +4360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Preload enable bit for channel5*/ +4362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; +4363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 78 + + +4364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the Output Fast mode */ +4365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; +4366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR3 |= sConfig->OCFastMode; +4367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_6: +4371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +4373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); +4374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the Channel 6 in PWM mode */ +4376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_OC6_SetConfig(htim->Instance, sConfig); +4377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Preload enable bit for channel6 */ +4379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; +4380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the Output Fast mode */ +4382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; +4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; +4384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +4388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +4389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); +4393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +4395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +4398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Initializes the TIM One Pulse Channels according to the specified +4399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * parameters in the TIM_OnePulse_InitTypeDef. +4400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM One Pulse handle +4401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param sConfig TIM One Pulse configuration structure +4402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param OutputChannel TIM output channel to configure +4403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +4404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +4405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +4406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param InputChannel TIM input Channel to configure +4407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +4408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +4409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +4410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note To output a waveform with a minimum delay user can enable the fast +4411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx +4412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * output is forced in response to the edge detection on TIx input, +4413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * without taking in account the comparison. +4414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +4415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +4416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef +4417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t OutputChannel, uint32_t InputChannel) +4418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +4420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_OC_InitTypeDef temp1; + ARM GAS /tmp/ccGFzgX3.s page 79 + + +4421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +4423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); +4424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); +4425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (OutputChannel != InputChannel) +4427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Process Locked */ +4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_LOCK(htim); +4430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +4432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Extract the Output compare configuration from sConfig structure */ +4434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.OCMode = sConfig->OCMode; +4435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.Pulse = sConfig->Pulse; +4436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.OCPolarity = sConfig->OCPolarity; +4437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.OCNPolarity = sConfig->OCNPolarity; +4438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.OCIdleState = sConfig->OCIdleState; +4439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.OCNIdleState = sConfig->OCNIdleState; +4440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (OutputChannel) +4442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: +4444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +4446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_OC1_SetConfig(htim->Instance, &temp1); +4448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: +4452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +4454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_OC2_SetConfig(htim->Instance, &temp1); +4456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +4460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +4461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (status == HAL_OK) +4465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (InputChannel) +4467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: +4469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +4471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, +4473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICSelection, sConfig->ICFilter); +4474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the IC1PSC Bits */ +4476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; +4477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 80 + + +4478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Trigger source */ +4479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR &= ~TIM_SMCR_TS; +4480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_TS_TI1FP1; +4481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Slave Mode */ +4483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR &= ~TIM_SMCR_SMS; +4484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; +4485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: +4489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +4491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, +4493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICSelection, sConfig->ICFilter); +4494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the IC2PSC Bits */ +4496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; +4497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Trigger source */ +4499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR &= ~TIM_SMCR_TS; +4500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_TS_TI2FP2; +4501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Slave Mode */ +4503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR &= ~TIM_SMCR_SMS; +4504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; +4505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +4509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +4510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +4515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); +4517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +4519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +4521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +4523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +4527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral +4528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +4529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write +4530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +4531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CR1 +4532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CR2 +4533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_SMCR +4534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_DIER + ARM GAS /tmp/ccGFzgX3.s page 81 + + +4535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_SR +4536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_EGR +4537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR1 +4538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR2 +4539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCER +4540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CNT +4541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_PSC +4542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_ARR +4543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_RCR +4544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR1 +4545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR2 +4546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR3 +4547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR4 +4548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_BDTR +4549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_OR +4550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR3 +4551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR5 +4552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR6 +4553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_AF1 (*) +4554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_AF2 (*) +4555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * (*) value not defined in all devices +4556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param BurstRequestSrc TIM DMA Request sources +4557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +4558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_UPDATE: TIM update Interrupt source +4559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source +4560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source +4561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source +4562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source +4563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_COM: TIM Commutation DMA source +4564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source +4565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param BurstBuffer The Buffer address. +4566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param BurstLength DMA Burst length. This parameter can be one value +4567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. +4568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note This function should be used only when BurstLength is equal to DMA data transfer length +4569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +4570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +4571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, +4572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t BurstRequestSrc, const uint32_t *BurstBuffer +4573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t BurstLength) +4574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status; +4576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, B +4578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ((BurstLength) >> 8U) + 1U); +4579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +4583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +4586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral +4587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +4588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write +4589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +4590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CR1 +4591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CR2 + ARM GAS /tmp/ccGFzgX3.s page 82 + + +4592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_SMCR +4593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_DIER +4594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_SR +4595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_EGR +4596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR1 +4597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR2 +4598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCER +4599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CNT +4600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_PSC +4601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_ARR +4602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_RCR +4603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR1 +4604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR2 +4605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR3 +4606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR4 +4607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_BDTR +4608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_OR +4609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR3 +4610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR5 +4611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR6 +4612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_AF1 (*) +4613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_AF2 (*) +4614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * (*) value not defined in all devices +4615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param BurstRequestSrc TIM DMA Request sources +4616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +4617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_UPDATE: TIM update Interrupt source +4618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source +4619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source +4620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source +4621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source +4622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_COM: TIM Commutation DMA source +4623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source +4624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param BurstBuffer The Buffer address. +4625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param BurstLength DMA Burst length. This parameter can be one value +4626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. +4627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param DataLength Data length. This parameter can be one value +4628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * between 1 and 0xFFFF. +4629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +4630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +4631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddre +4632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t BurstRequestSrc, const uint32_t *BurstB +4633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t BurstLength, uint32_t DataLength) +4634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +4636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +4638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); +4639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); +4640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); +4641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_LENGTH(BurstLength)); +4642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); +4643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) +4645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_BUSY; +4647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + ARM GAS /tmp/ccGFzgX3.s page 83 + + +4649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((BurstBuffer == NULL) && (BurstLength > 0U)) +4651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +4653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +4655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; +4657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +4660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* nothing to do */ +4662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (BurstRequestSrc) +4665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_UPDATE: +4667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA Period elapsed callbacks */ +4669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; +4670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; +4671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +4673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; +4674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +4676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, +4677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) +4678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +4680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +4681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_CC1: +4685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA compare callbacks */ +4687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; +4688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; +4689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +4691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; +4692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +4694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, +4695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) +4696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +4698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +4699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_CC2: +4703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA compare callbacks */ +4705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + ARM GAS /tmp/ccGFzgX3.s page 84 + + +4706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; +4707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +4709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; +4710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +4712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, +4713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) +4714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +4716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +4717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_CC3: +4721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA compare callbacks */ +4723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; +4724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; +4725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +4727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; +4728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +4730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, +4731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) +4732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +4734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +4735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_CC4: +4739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA compare callbacks */ +4741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; +4742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; +4743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +4745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; +4746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +4748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, +4749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) +4750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +4752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +4753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_COM: +4757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA commutation callbacks */ +4759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; +4760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; +4761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ + ARM GAS /tmp/ccGFzgX3.s page 85 + + +4763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; +4764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +4766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, +4767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) +4768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +4770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +4771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_TRIGGER: +4775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA trigger callbacks */ +4777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; +4778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; +4779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +4781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; +4782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +4784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, +4785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) +4786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +4788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +4789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +4793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +4794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (status == HAL_OK) +4798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the DMA Burst Mode */ +4800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->DCR = (BurstBaseAddress | BurstLength); +4801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM DMA Request */ +4802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); +4803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +4806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +4807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +4810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Stops the TIM DMA Burst mode +4811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +4812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param BurstRequestSrc TIM DMA Request sources to disable +4813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +4814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +4815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +4816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +4818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + ARM GAS /tmp/ccGFzgX3.s page 86 + + +4820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); +4821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Abort the DMA transfer (at least disable the DMA stream) */ +4823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (BurstRequestSrc) +4824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_UPDATE: +4826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); +4828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_CC1: +4831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); +4833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_CC2: +4836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); +4838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_CC3: +4841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); +4843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_CC4: +4846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); +4848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_COM: +4851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); +4853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_TRIGGER: +4856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); +4858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +4861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +4862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +4863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (status == HAL_OK) +4866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Update DMA request */ +4868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); +4869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change the DMA burst operation state */ +4871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_READY; +4872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +4875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +4876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + ARM GAS /tmp/ccGFzgX3.s page 87 + + +4877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +4879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory +4880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +4881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read +4882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +4883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CR1 +4884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CR2 +4885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_SMCR +4886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_DIER +4887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_SR +4888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_EGR +4889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR1 +4890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR2 +4891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCER +4892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CNT +4893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_PSC +4894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_ARR +4895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_RCR +4896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR1 +4897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR2 +4898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR3 +4899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR4 +4900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_BDTR +4901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_OR +4902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR3 +4903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR5 +4904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR6 +4905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_AF1 (*) +4906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_AF2 (*) +4907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * (*) value not defined in all devices +4908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param BurstRequestSrc TIM DMA Request sources +4909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +4910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_UPDATE: TIM update Interrupt source +4911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source +4912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source +4913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source +4914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source +4915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_COM: TIM Commutation DMA source +4916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source +4917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param BurstBuffer The Buffer address. +4918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param BurstLength DMA Burst length. This parameter can be one value +4919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. +4920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note This function should be used only when BurstLength is equal to DMA data transfer length +4921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +4922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +4923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, +4924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint +4925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status; +4927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, Bu +4929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ((BurstLength) >> 8U) + 1U); +4930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +4933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + ARM GAS /tmp/ccGFzgX3.s page 88 + + +4934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +4936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory +4937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +4938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read +4939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +4940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CR1 +4941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CR2 +4942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_SMCR +4943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_DIER +4944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_SR +4945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_EGR +4946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR1 +4947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR2 +4948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCER +4949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CNT +4950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_PSC +4951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_ARR +4952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_RCR +4953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR1 +4954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR2 +4955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR3 +4956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR4 +4957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_BDTR +4958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_OR +4959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR3 +4960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR5 +4961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_CCR6 +4962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_AF1 (*) +4963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMABASE_AF2 (*) +4964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * (*) value not defined in all devices +4965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param BurstRequestSrc TIM DMA Request sources +4966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +4967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_UPDATE: TIM update Interrupt source +4968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source +4969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source +4970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source +4971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source +4972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_COM: TIM Commutation DMA source +4973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source +4974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param BurstBuffer The Buffer address. +4975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param BurstLength DMA Burst length. This parameter can be one value +4976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. +4977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param DataLength Data length. This parameter can be one value +4978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * between 1 and 0xFFFF. +4979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +4980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +4981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddres +4982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t BurstRequestSrc, uint32_t *BurstBuffer, +4983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t BurstLength, uint32_t DataLength) +4984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +4986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +4988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); +4989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); +4990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + ARM GAS /tmp/ccGFzgX3.s page 89 + + +4991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_LENGTH(BurstLength)); +4992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); +4993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +4994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) +4995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +4996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_BUSY; +4997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +4998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) +4999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if ((BurstBuffer == NULL) && (BurstLength > 0U)) +5001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +5003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +5005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; +5007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +5010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* nothing to do */ +5012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (BurstRequestSrc) +5014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_UPDATE: +5016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA Period elapsed callbacks */ +5018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; +5019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; +5020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +5022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; +5023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +5025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_ +5026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) +5027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +5029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +5030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_CC1: +5034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA capture callbacks */ +5036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; +5037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; +5038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +5040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; +5041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +5043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)B +5044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) +5045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +5047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + ARM GAS /tmp/ccGFzgX3.s page 90 + + +5048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_CC2: +5052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA capture callbacks */ +5054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; +5055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; +5056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +5058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; +5059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +5061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)B +5062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) +5063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +5065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +5066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_CC3: +5070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA capture callbacks */ +5072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; +5073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; +5074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +5076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; +5077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +5079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)B +5080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) +5081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +5083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +5084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_CC4: +5088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA capture callbacks */ +5090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; +5091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; +5092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +5094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; +5095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +5097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)B +5098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) +5099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +5101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +5102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + ARM GAS /tmp/ccGFzgX3.s page 91 + + +5105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_COM: +5106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA commutation callbacks */ +5108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; +5109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; +5110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +5112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; +5113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +5115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (ui +5116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) +5117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +5119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +5120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_TRIGGER: +5124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA trigger callbacks */ +5126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; +5127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; +5128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the DMA error callback */ +5130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; +5131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ +5133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32 +5134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) +5135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +5137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +5138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +5142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +5143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (status == HAL_OK) +5147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the DMA Burst Mode */ +5149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->DCR = (BurstBaseAddress | BurstLength); +5150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM DMA Request */ +5152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); +5153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +5156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +5157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Stop the DMA burst reading +5161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle + ARM GAS /tmp/ccGFzgX3.s page 92 + + +5162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param BurstRequestSrc TIM DMA Request sources to disable. +5163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +5164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +5166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +5168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +5170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); +5171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Abort the DMA transfer (at least disable the DMA stream) */ +5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (BurstRequestSrc) +5174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_UPDATE: +5176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); +5178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_CC1: +5181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); +5183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_CC2: +5186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); +5188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_CC3: +5191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); +5193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_CC4: +5196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); +5198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_COM: +5201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); +5203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_DMA_TRIGGER: +5206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); +5208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +5211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +5212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (status == HAL_OK) +5216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the TIM Update DMA request */ +5218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + ARM GAS /tmp/ccGFzgX3.s page 93 + + +5219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change the DMA burst operation state */ +5221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_READY; +5222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +5225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +5226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Generate a software event +5230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +5231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param EventSource specifies the event source. +5232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +5233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source +5234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source +5235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source +5236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source +5237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source +5238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_COM: Timer COM event source +5239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source +5240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source +5241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source +5242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note Basic timers can only generate an update event. +5243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. +5244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant +5245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * only for timer instances supporting break input(s). +5246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +5247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +5250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +5252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +5253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_EVENT_SOURCE(EventSource)); +5254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Process Locked */ +5256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_LOCK(htim); +5257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change the TIM state */ +5259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +5260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the event sources */ +5262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->EGR = EventSource; +5263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Change the TIM state */ +5265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +5266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); +5268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return function status */ +5270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +5271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Configures the OCRef clear feature +5275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle + ARM GAS /tmp/ccGFzgX3.s page 94 + + +5276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that +5277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * contains the OCREF clear feature and parameters for the TIM peripheral. +5278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel specifies the TIM Channel +5279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +5280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 +5281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 +5282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 +5283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 +5284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_5: TIM Channel 5 +5285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_6: TIM Channel 6 +5286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +5287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, +5289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** const TIM_ClearInputConfigTypeDef *sClearInputConfig, +5290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t Channel) +5291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +5293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +5295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); +5296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); +5297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Process Locked */ +5299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_LOCK(htim); +5300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +5302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (sClearInputConfig->ClearInputSource) +5304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CLEARINPUTSOURCE_NONE: +5306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Clear the OCREF clear selection bit and the the ETR Bits */ +5308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)) +5309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CLEARINPUTSOURCE_ETR: +5313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +5315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); +5316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); +5317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); +5318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ +5320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) +5321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +5323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); +5324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +5325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_ETR_SetConfig(htim->Instance, +5328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClearInputConfig->ClearInputPrescaler, +5329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClearInputConfig->ClearInputPolarity, +5330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClearInputConfig->ClearInputFilter); +5331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + ARM GAS /tmp/ccGFzgX3.s page 95 + + +5333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +5335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +5336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (status == HAL_OK) +5340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) +5342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: +5344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) +5346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the OCREF clear feature for Channel 1 */ +5348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); +5349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +5351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the OCREF clear feature for Channel 1 */ +5353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); +5354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: +5358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) +5360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the OCREF clear feature for Channel 2 */ +5362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); +5363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +5365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the OCREF clear feature for Channel 2 */ +5367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); +5368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_3: +5372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) +5374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the OCREF clear feature for Channel 3 */ +5376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); +5377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +5379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the OCREF clear feature for Channel 3 */ +5381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); +5382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_4: +5386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) +5388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the OCREF clear feature for Channel 4 */ + ARM GAS /tmp/ccGFzgX3.s page 96 + + +5390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); +5391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +5393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the OCREF clear feature for Channel 4 */ +5395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); +5396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_5: +5400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) +5402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the OCREF clear feature for Channel 5 */ +5404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); +5405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +5407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the OCREF clear feature for Channel 5 */ +5409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); +5410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_6: +5414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) +5416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the OCREF clear feature for Channel 6 */ +5418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); +5419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +5421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the OCREF clear feature for Channel 6 */ +5423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); +5424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +5428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +5433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); +5435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +5437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Configures the clock source to be used +5441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +5442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that +5443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * contains the clock source information for the TIM peripheral. +5444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +5445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef * + ARM GAS /tmp/ccGFzgX3.s page 97 + + +5447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +5449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; +5450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Process Locked */ +5452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_LOCK(htim); +5453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +5455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +5457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); +5458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ +5460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR; +5461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); +5462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); +5463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR = tmpsmcr; +5464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (sClockSourceConfig->ClockSource) +5466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CLOCKSOURCE_INTERNAL: +5468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +5470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CLOCKSOURCE_ETRMODE1: +5474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ +5476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); +5477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check ETR input conditioning related parameters */ +5479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); +5480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); +5481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); +5482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the ETR Clock source */ +5484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_ETR_SetConfig(htim->Instance, +5485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPrescaler, +5486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, +5487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockFilter); +5488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the External clock mode1 and the ETRF trigger */ +5490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR; +5491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); +5492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx SMCR */ +5493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR = tmpsmcr; +5494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CLOCKSOURCE_ETRMODE2: +5498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ +5500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); +5501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check ETR input conditioning related parameters */ +5503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + ARM GAS /tmp/ccGFzgX3.s page 98 + + +5504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); +5505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); +5506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the ETR Clock source */ +5508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_ETR_SetConfig(htim->Instance, +5509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPrescaler, +5510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, +5511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockFilter); +5512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the External clock mode2 */ +5513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SMCR_ECE; +5514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CLOCKSOURCE_TI1: +5518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check whether or not the timer instance supports external clock mode 1 */ +5520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); +5521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check TI1 input conditioning related parameters */ +5523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); +5524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); +5525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_TI1_ConfigInputStage(htim->Instance, +5527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, +5528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockFilter); +5529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); +5530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CLOCKSOURCE_TI2: +5534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ +5536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); +5537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check TI2 input conditioning related parameters */ +5539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); +5540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); +5541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_TI2_ConfigInputStage(htim->Instance, +5543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, +5544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockFilter); +5545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); +5546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CLOCKSOURCE_TI1ED: +5550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check whether or not the timer instance supports external clock mode 1 */ +5552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); +5553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check TI1 input conditioning related parameters */ +5555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); +5556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); +5557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_TI1_ConfigInputStage(htim->Instance, +5559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, +5560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockFilter); + ARM GAS /tmp/ccGFzgX3.s page 99 + + +5561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); +5562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CLOCKSOURCE_ITR0: +5566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CLOCKSOURCE_ITR1: +5567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CLOCKSOURCE_ITR2: +5568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CLOCKSOURCE_ITR3: +5569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check whether or not the timer instance supports internal trigger input */ +5571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); +5572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); +5574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +5578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +5579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +5582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); +5584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +5586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Selects the signal connected to the TI1 input: direct from CH1_input +5590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * or a XOR combination between CH1_input, CH2_input & CH3_input +5591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle. +5592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TI1_Selection Indicate whether or not channel 1 is connected to the +5593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * output of a XOR gate. +5594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +5595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input +5596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 +5597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * pins are connected to the TI1 input (XOR combination) +5598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +5599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +5601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpcr2; +5603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +5605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); +5606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); +5607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CR2 register value */ +5609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 = htim->Instance->CR2; +5610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the TI1 selection */ +5612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_TI1S; +5613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the TI1 selection */ +5615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 |= TI1_Selection; +5616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMxCR2 */ + ARM GAS /tmp/ccGFzgX3.s page 100 + + +5618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CR2 = tmpcr2; +5619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +5621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Configures the TIM in Slave mode +5625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle. +5626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that +5627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * contains the selected trigger (internal trigger input, filtered +5628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * timer input or external trigger input) and the Slave mode +5629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * (Disable, Reset, Gated, Trigger, External clock mode 1). +5630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +5631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef +5633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +5635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); +5636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); +5637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); +5638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_LOCK(htim); +5640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +5642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) +5644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +5646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); +5647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +5648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable Trigger Interrupt */ +5651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); +5652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable Trigger DMA request */ +5654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); +5655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +5657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); +5659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +5661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Configures the TIM in Slave mode in interrupt mode +5665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle. +5666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that +5667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * contains the selected trigger (internal trigger input, filtered +5668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * timer input or external trigger input) and the Slave mode +5669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * (Disable, Reset, Gated, Trigger, External clock mode 1). +5670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL status +5671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, +5673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** const TIM_SlaveConfigTypeDef *sSlaveConfig) +5674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 101 + + +5675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +5676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); +5677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); +5678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); +5679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_LOCK(htim); +5681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; +5683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) +5685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +5687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); +5688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +5689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable Trigger Interrupt */ +5692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); +5693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable Trigger DMA request */ +5695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); +5696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +5698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); +5700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_OK; +5702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Read the captured value from Capture Compare unit +5706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle. +5707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +5708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +5709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +5710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +5711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +5712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +5713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval Captured value +5714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) +5716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpreg = 0U; +5718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (Channel) +5720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_1: +5722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +5724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +5725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return the capture 1 value */ +5727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpreg = htim->Instance->CCR1; +5728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_2: + ARM GAS /tmp/ccGFzgX3.s page 102 + + +5732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +5734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +5735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return the capture 2 value */ +5737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpreg = htim->Instance->CCR2; +5738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_3: +5743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +5745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); +5746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return the capture 3 value */ +5748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpreg = htim->Instance->CCR3; +5749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_CHANNEL_4: +5754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +5756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); +5757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return the capture 4 value */ +5759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpreg = htim->Instance->CCR4; +5760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +5765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return tmpreg; +5769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @} +5773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions +5776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM Callbacks functions +5777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * +5778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim +5779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== +5780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ##### TIM Callbacks functions ##### +5781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== +5782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] +5783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** This section provides TIM callback functions: +5784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) TIM Period elapsed callback +5785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) TIM Output Compare callback +5786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) TIM Input capture callback +5787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) TIM Trigger callback +5788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (+) TIM Error callback + ARM GAS /tmp/ccGFzgX3.s page 103 + + +5789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim +5791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @{ +5792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Period elapsed callback in non-blocking mode +5796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +5797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +5798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +5800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); +5803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_PeriodElapsedCallback could be implemented in the user file +5806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Period elapsed half complete callback in non-blocking mode +5811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +5812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +5813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +5815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); +5818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file +5821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Output Compare callback in non-blocking mode +5826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM OC handle +5827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +5828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +5830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); +5833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file +5836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Input Capture callback in non-blocking mode +5841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM IC handle +5842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +5843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +5845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 104 + + +5846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); +5848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_IC_CaptureCallback could be implemented in the user file +5851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Input Capture half complete callback in non-blocking mode +5856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM IC handle +5857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +5858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +5860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); +5863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file +5866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief PWM Pulse finished callback in non-blocking mode +5871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +5872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +5873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +5875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); +5878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file +5881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief PWM Pulse finished half complete callback in non-blocking mode +5886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +5887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +5888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +5890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); +5893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file +5896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Hall Trigger detection callback in non-blocking mode +5901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +5902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None + ARM GAS /tmp/ccGFzgX3.s page 105 + + +5903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +5905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); +5908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_TriggerCallback could be implemented in the user file +5911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Hall Trigger detection half complete callback in non-blocking mode +5916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +5917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +5918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +5920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); +5923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file +5926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Timer error callback in non-blocking mode +5931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +5932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +5933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +5935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** UNUSED(htim); +5938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** the HAL_TIM_ErrorCallback could be implemented in the user file +5941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +5945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +5946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Register a User TIM callback to be used instead of the weak predefined callback +5947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim tim handle +5948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param CallbackID ID of the callback to be registered +5949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +5950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID +5951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID +5952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID +5953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID +5954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID +5955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID +5956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID +5957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID +5958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID +5959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + ARM GAS /tmp/ccGFzgX3.s page 106 + + +5960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID +5961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID +5962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID +5963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID +5964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID +5965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID +5966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID +5967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID +5968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID +5969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID +5970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID +5971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID +5972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callb +5973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID +5974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID +5975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID +5976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID +5977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID +5978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param pCallback pointer to the callback function +5979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval status +5980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +5981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef Callb +5982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** pTIM_CallbackTypeDef pCallback) +5983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +5985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (pCallback == NULL) +5987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +5989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +5990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->State == HAL_TIM_STATE_READY) +5992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (CallbackID) +5994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +5995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_BASE_MSPINIT_CB_ID : +5996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Base_MspInitCallback = pCallback; +5997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +5998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +5999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_BASE_MSPDEINIT_CB_ID : +6000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Base_MspDeInitCallback = pCallback; +6001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_IC_MSPINIT_CB_ID : +6004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_MspInitCallback = pCallback; +6005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_IC_MSPDEINIT_CB_ID : +6008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_MspDeInitCallback = pCallback; +6009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_OC_MSPINIT_CB_ID : +6012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OC_MspInitCallback = pCallback; +6013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_OC_MSPDEINIT_CB_ID : +6016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OC_MspDeInitCallback = pCallback; + ARM GAS /tmp/ccGFzgX3.s page 107 + + +6017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_PWM_MSPINIT_CB_ID : +6020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_MspInitCallback = pCallback; +6021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_PWM_MSPDEINIT_CB_ID : +6024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_MspDeInitCallback = pCallback; +6025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : +6028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OnePulse_MspInitCallback = pCallback; +6029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : +6032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OnePulse_MspDeInitCallback = pCallback; +6033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_ENCODER_MSPINIT_CB_ID : +6036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Encoder_MspInitCallback = pCallback; +6037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : +6040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Encoder_MspDeInitCallback = pCallback; +6041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : +6044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->HallSensor_MspInitCallback = pCallback; +6045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : +6048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->HallSensor_MspDeInitCallback = pCallback; +6049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_PERIOD_ELAPSED_CB_ID : +6052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PeriodElapsedCallback = pCallback; +6053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : +6056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PeriodElapsedHalfCpltCallback = pCallback; +6057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_TRIGGER_CB_ID : +6060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->TriggerCallback = pCallback; +6061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_TRIGGER_HALF_CB_ID : +6064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->TriggerHalfCpltCallback = pCallback; +6065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_IC_CAPTURE_CB_ID : +6068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_CaptureCallback = pCallback; +6069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_IC_CAPTURE_HALF_CB_ID : +6072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_CaptureHalfCpltCallback = pCallback; +6073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + ARM GAS /tmp/ccGFzgX3.s page 108 + + +6074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : +6076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OC_DelayElapsedCallback = pCallback; +6077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : +6080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_PulseFinishedCallback = pCallback; +6081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : +6084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_PulseFinishedHalfCpltCallback = pCallback; +6085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_ERROR_CB_ID : +6088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->ErrorCallback = pCallback; +6089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_COMMUTATION_CB_ID : +6092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->CommutationCallback = pCallback; +6093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_COMMUTATION_HALF_CB_ID : +6096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->CommutationHalfCpltCallback = pCallback; +6097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_BREAK_CB_ID : +6100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->BreakCallback = pCallback; +6101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_BREAK2_CB_ID : +6104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Break2Callback = pCallback; +6105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default : +6108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +6109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +6110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (htim->State == HAL_TIM_STATE_RESET) +6114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (CallbackID) +6116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_BASE_MSPINIT_CB_ID : +6118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Base_MspInitCallback = pCallback; +6119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_BASE_MSPDEINIT_CB_ID : +6122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Base_MspDeInitCallback = pCallback; +6123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_IC_MSPINIT_CB_ID : +6126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_MspInitCallback = pCallback; +6127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_IC_MSPDEINIT_CB_ID : +6130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_MspDeInitCallback = pCallback; + ARM GAS /tmp/ccGFzgX3.s page 109 + + +6131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_OC_MSPINIT_CB_ID : +6134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OC_MspInitCallback = pCallback; +6135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_OC_MSPDEINIT_CB_ID : +6138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OC_MspDeInitCallback = pCallback; +6139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_PWM_MSPINIT_CB_ID : +6142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_MspInitCallback = pCallback; +6143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_PWM_MSPDEINIT_CB_ID : +6146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_MspDeInitCallback = pCallback; +6147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : +6150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OnePulse_MspInitCallback = pCallback; +6151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : +6154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OnePulse_MspDeInitCallback = pCallback; +6155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_ENCODER_MSPINIT_CB_ID : +6158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Encoder_MspInitCallback = pCallback; +6159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : +6162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Encoder_MspDeInitCallback = pCallback; +6163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : +6166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->HallSensor_MspInitCallback = pCallback; +6167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : +6170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->HallSensor_MspDeInitCallback = pCallback; +6171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default : +6174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +6175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +6176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +6180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +6182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +6183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +6186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 110 + + +6188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Unregister a TIM callback +6190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * TIM callback is redirected to the weak predefined callback +6191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim tim handle +6192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param CallbackID ID of the callback to be unregistered +6193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +6194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID +6195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID +6196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID +6197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID +6198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID +6199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID +6200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID +6201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID +6202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID +6203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID +6204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID +6205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID +6206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID +6207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID +6208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID +6209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID +6210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID +6211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID +6212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID +6213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID +6214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID +6215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID +6216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callb +6217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID +6218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID +6219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID +6220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID +6221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID +6222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval status +6223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef Cal +6225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +6227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->State == HAL_TIM_STATE_READY) +6229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (CallbackID) +6231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_BASE_MSPINIT_CB_ID : +6233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Base MspInit Callback */ +6234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; +6235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_BASE_MSPDEINIT_CB_ID : +6238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Base Msp DeInit Callback */ +6239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; +6240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_IC_MSPINIT_CB_ID : +6243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak IC Msp Init Callback */ +6244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + ARM GAS /tmp/ccGFzgX3.s page 111 + + +6245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_IC_MSPDEINIT_CB_ID : +6248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak IC Msp DeInit Callback */ +6249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; +6250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_OC_MSPINIT_CB_ID : +6253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak OC Msp Init Callback */ +6254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; +6255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_OC_MSPDEINIT_CB_ID : +6258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak OC Msp DeInit Callback */ +6259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; +6260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_PWM_MSPINIT_CB_ID : +6263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak PWM Msp Init Callback */ +6264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; +6265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_PWM_MSPDEINIT_CB_ID : +6268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak PWM Msp DeInit Callback */ +6269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; +6270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : +6273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak One Pulse Msp Init Callback */ +6274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; +6275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : +6278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak One Pulse Msp DeInit Callback */ +6279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; +6280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_ENCODER_MSPINIT_CB_ID : +6283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Encoder Msp Init Callback */ +6284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; +6285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : +6288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Encoder Msp DeInit Callback */ +6289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; +6290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : +6293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Hall Sensor Msp Init Callback */ +6294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; +6295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : +6298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Hall Sensor Msp DeInit Callback */ +6299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; +6300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 112 + + +6302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_PERIOD_ELAPSED_CB_ID : +6303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Period Elapsed Callback */ +6304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; +6305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : +6308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Period Elapsed half complete Callback */ +6309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; +6310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_TRIGGER_CB_ID : +6313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Trigger Callback */ +6314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->TriggerCallback = HAL_TIM_TriggerCallback; +6315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_TRIGGER_HALF_CB_ID : +6318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Trigger half complete Callback */ +6319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; +6320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_IC_CAPTURE_CB_ID : +6323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak IC Capture Callback */ +6324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; +6325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_IC_CAPTURE_HALF_CB_ID : +6328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak IC Capture half complete Callback */ +6329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; +6330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : +6333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak OC Delay Elapsed Callback */ +6334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; +6335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : +6338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak PWM Pulse Finished Callback */ +6339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; +6340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : +6343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak PWM Pulse Finished half complete Callback */ +6344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; +6345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_ERROR_CB_ID : +6348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Error Callback */ +6349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->ErrorCallback = HAL_TIM_ErrorCallback; +6350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_COMMUTATION_CB_ID : +6353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Commutation Callback */ +6354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->CommutationCallback = HAL_TIMEx_CommutCallback; +6355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_COMMUTATION_HALF_CB_ID : +6358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Commutation half complete Callback */ + ARM GAS /tmp/ccGFzgX3.s page 113 + + +6359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; +6360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_BREAK_CB_ID : +6363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Break Callback */ +6364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->BreakCallback = HAL_TIMEx_BreakCallback; +6365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_BREAK2_CB_ID : +6368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Break2 Callback */ +6369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Break2Callback = HAL_TIMEx_Break2Callback; +6370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default : +6373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +6374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +6375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (htim->State == HAL_TIM_STATE_RESET) +6379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (CallbackID) +6381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_BASE_MSPINIT_CB_ID : +6383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Base MspInit Callback */ +6384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; +6385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_BASE_MSPDEINIT_CB_ID : +6388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Base Msp DeInit Callback */ +6389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; +6390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_IC_MSPINIT_CB_ID : +6393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak IC Msp Init Callback */ +6394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; +6395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_IC_MSPDEINIT_CB_ID : +6398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak IC Msp DeInit Callback */ +6399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; +6400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_OC_MSPINIT_CB_ID : +6403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak OC Msp Init Callback */ +6404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; +6405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_OC_MSPDEINIT_CB_ID : +6408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak OC Msp DeInit Callback */ +6409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; +6410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_PWM_MSPINIT_CB_ID : +6413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak PWM Msp Init Callback */ +6414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; +6415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + ARM GAS /tmp/ccGFzgX3.s page 114 + + +6416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_PWM_MSPDEINIT_CB_ID : +6418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak PWM Msp DeInit Callback */ +6419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; +6420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : +6423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak One Pulse Msp Init Callback */ +6424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; +6425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : +6428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak One Pulse Msp DeInit Callback */ +6429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; +6430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_ENCODER_MSPINIT_CB_ID : +6433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Encoder Msp Init Callback */ +6434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; +6435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : +6438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Encoder Msp DeInit Callback */ +6439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; +6440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : +6443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Hall Sensor Msp Init Callback */ +6444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; +6445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : +6448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Legacy weak Hall Sensor Msp DeInit Callback */ +6449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; +6450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default : +6453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +6454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +6455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +6456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +6459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Return error status */ +6461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +6462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +6465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @} +6470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + ARM GAS /tmp/ccGFzgX3.s page 115 + + +6473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM Peripheral State functions +6474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * +6475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @verbatim +6476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== +6477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ##### Peripheral State functions ##### +6478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ============================================================================== +6479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** [..] +6480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** This subsection permits to get in run-time the status of the peripheral +6481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** and the data flow. +6482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** @endverbatim +6484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @{ +6485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Return the TIM Base handle state. +6489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Base handle +6490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL state +6491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) +6493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return htim->State; +6495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Return the TIM OC handle state. +6499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Output Compare handle +6500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL state +6501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) +6503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return htim->State; +6505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Return the TIM PWM handle state. +6509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +6510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL state +6511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) +6513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return htim->State; +6515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Return the TIM Input Capture handle state. +6519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM IC handle +6520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL state +6521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) +6523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return htim->State; +6525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Return the TIM One Pulse Mode handle state. +6529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM OPM handle + ARM GAS /tmp/ccGFzgX3.s page 116 + + +6530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL state +6531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) +6533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return htim->State; +6535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Return the TIM Encoder Mode handle state. +6539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +6540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval HAL state +6541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) +6543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return htim->State; +6545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Return the TIM Encoder Mode handle state. +6549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +6550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval Active channel +6551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) +6553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return htim->Channel; +6555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Return actual state of the TIM channel. +6559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +6560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel TIM Channel +6561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +6562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 +6563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 +6564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 +6565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 +6566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_5: TIM Channel 5 +6567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_6: TIM Channel 6 +6568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval TIM Channel state +6569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channe +6571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_state; +6573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +6575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +6576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); +6578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return channel_state; +6580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Return actual state of a DMA burst operation. +6584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +6585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval DMA burst state +6586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ + ARM GAS /tmp/ccGFzgX3.s page 117 + + +6587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) +6588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +6590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); +6591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return htim->DMABurstState; +6593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @} +6597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @} +6601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** @defgroup TIM_Private_Functions TIM Private Functions +6604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @{ +6605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM DMA error callback +6609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param hdma pointer to DMA handle. +6610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +6611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void TIM_DMAError(DMA_HandleTypeDef *hdma) +6613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; +6615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (hdma == htim->hdma[TIM_DMA_ID_CC1]) +6617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; +6619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +6620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) +6622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; +6624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +6625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) +6627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; +6629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); +6630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) +6632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; +6634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); +6635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +6637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +6639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +6642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->ErrorCallback(htim); +6643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else + ARM GAS /tmp/ccGFzgX3.s page 118 + + +6644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ErrorCallback(htim); +6645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +6648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM DMA Delay Pulse complete callback. +6652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param hdma pointer to DMA handle. +6653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +6654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +6656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; +6658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (hdma == htim->hdma[TIM_DMA_ID_CC1]) +6660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; +6662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (hdma->Init.Mode == DMA_NORMAL) +6664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +6666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) +6669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; +6671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (hdma->Init.Mode == DMA_NORMAL) +6673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +6675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) +6678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; +6680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (hdma->Init.Mode == DMA_NORMAL) +6682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); +6684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) +6687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; +6689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (hdma->Init.Mode == DMA_NORMAL) +6691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); +6693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +6696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* nothing to do */ +6698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + ARM GAS /tmp/ccGFzgX3.s page 119 + + +6701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_PulseFinishedCallback(htim); +6702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +6703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); +6704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +6707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM DMA Delay Pulse half complete callback. +6711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param hdma pointer to DMA handle. +6712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +6713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +6715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; +6717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (hdma == htim->hdma[TIM_DMA_ID_CC1]) +6719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; +6721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) +6723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; +6725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) +6727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; +6729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) +6731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; +6733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +6735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* nothing to do */ +6737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +6740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PWM_PulseFinishedHalfCpltCallback(htim); +6741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +6742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +6743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +6746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM DMA Capture complete callback. +6750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param hdma pointer to DMA handle. +6751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +6752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +6754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; +6756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + ARM GAS /tmp/ccGFzgX3.s page 120 + + +6758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; +6760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (hdma->Init.Mode == DMA_NORMAL) +6762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +6764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +6765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) +6768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; +6770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (hdma->Init.Mode == DMA_NORMAL) +6772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +6774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +6775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) +6778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; +6780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (hdma->Init.Mode == DMA_NORMAL) +6782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); +6784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); +6785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) +6788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; +6790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (hdma->Init.Mode == DMA_NORMAL) +6792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); +6794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); +6795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +6798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* nothing to do */ +6800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +6803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_CaptureCallback(htim); +6804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +6805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_IC_CaptureCallback(htim); +6806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +6809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM DMA Capture half complete callback. +6813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param hdma pointer to DMA handle. +6814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None + ARM GAS /tmp/ccGFzgX3.s page 121 + + +6815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +6817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; +6819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (hdma == htim->hdma[TIM_DMA_ID_CC1]) +6821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; +6823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) +6825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; +6827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) +6829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; +6831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) +6833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; +6835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +6837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* nothing to do */ +6839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +6842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->IC_CaptureHalfCpltCallback(htim); +6843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +6844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_IC_CaptureHalfCpltCallback(htim); +6845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +6848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM DMA Period Elapse complete callback. +6852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param hdma pointer to DMA handle. +6853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +6854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +6856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; +6858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) +6860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +6862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +6865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PeriodElapsedCallback(htim); +6866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +6867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_PeriodElapsedCallback(htim); +6868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + ARM GAS /tmp/ccGFzgX3.s page 122 + + +6872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM DMA Period Elapse half complete callback. +6873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param hdma pointer to DMA handle. +6874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +6875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +6877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; +6879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +6881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->PeriodElapsedHalfCpltCallback(htim); +6882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +6883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +6884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM DMA Trigger callback. +6889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param hdma pointer to DMA handle. +6890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +6891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +6893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; +6895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) +6897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; +6899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +6902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->TriggerCallback(htim); +6903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +6904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_TriggerCallback(htim); +6905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief TIM DMA Trigger half complete callback. +6910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param hdma pointer to DMA handle. +6911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +6912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +6914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; +6916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +6918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->TriggerHalfCpltCallback(htim); +6919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #else +6920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_TriggerHalfCpltCallback(htim); +6921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Time Base configuration +6926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIMx TIM peripheral +6927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Structure TIM Base configuration structure +6928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None + ARM GAS /tmp/ccGFzgX3.s page 123 + + +6929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +6931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpcr1; +6933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr1 = TIMx->CR1; +6934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set TIM Time Base Unit parameters ---------------------------------------*/ +6936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) +6937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Counter Mode */ +6939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); +6940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr1 |= Structure->CounterMode; +6941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) +6944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the clock division */ +6946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr1 &= ~TIM_CR1_CKD; +6947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr1 |= (uint32_t)Structure->ClockDivision; +6948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the auto-reload preload */ +6951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); +6952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CR1 = tmpcr1; +6954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Autoreload value */ +6956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->ARR = (uint32_t)Structure->Period ; +6957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Prescaler value */ +6959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->PSC = Structure->Prescaler; +6960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) +6962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Repetition Counter value */ +6964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->RCR = Structure->RepetitionCounter; +6965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Generate an update event to reload the Prescaler +6968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** and the repetition counter (only for advanced timer) value immediately */ +6969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->EGR = TIM_EGR_UG; +6970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ +6972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) +6973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +6974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Clear the update flag */ +6975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); +6976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +6978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +6980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Timer Output Compare 1 configuration +6981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +6982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param OC_Config The output configuration structure +6983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +6984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +6985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) + ARM GAS /tmp/ccGFzgX3.s page 124 + + +6986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 28 .loc 1 6986 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .loc 1 6986 1 is_stmt 0 view .LVU1 + 34 0000 70B4 push {r4, r5, r6} + 35 .LCFI0: + 36 .cfi_def_cfa_offset 12 + 37 .cfi_offset 4, -12 + 38 .cfi_offset 5, -8 + 39 .cfi_offset 6, -4 +6987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmrx; + 40 .loc 1 6987 3 is_stmt 1 view .LVU2 +6988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccer; + 41 .loc 1 6988 3 view .LVU3 +6989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpcr2; + 42 .loc 1 6989 3 view .LVU4 +6990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CCER register value */ +6992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer = TIMx->CCER; + 43 .loc 1 6992 3 view .LVU5 + 44 .loc 1 6992 11 is_stmt 0 view .LVU6 + 45 0002 046A ldr r4, [r0, #32] + 46 .LVL1: +6993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Channel 1: Reset the CC1E Bit */ +6995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC1E; + 47 .loc 1 6995 3 is_stmt 1 view .LVU7 + 48 .loc 1 6995 7 is_stmt 0 view .LVU8 + 49 0004 036A ldr r3, [r0, #32] + 50 .loc 1 6995 14 view .LVU9 + 51 0006 23F00103 bic r3, r3, #1 + 52 000a 0362 str r3, [r0, #32] +6996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +6997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CR2 register value */ +6998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 = TIMx->CR2; + 53 .loc 1 6998 3 is_stmt 1 view .LVU10 + 54 .loc 1 6998 10 is_stmt 0 view .LVU11 + 55 000c 4268 ldr r2, [r0, #4] + 56 .LVL2: +6999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CCMR1 register value */ +7001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx = TIMx->CCMR1; + 57 .loc 1 7001 3 is_stmt 1 view .LVU12 + 58 .loc 1 7001 12 is_stmt 0 view .LVU13 + 59 000e 8569 ldr r5, [r0, #24] + 60 .LVL3: +7002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output Compare Mode Bits */ +7004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR1_OC1M; + 61 .loc 1 7004 3 is_stmt 1 view .LVU14 +7005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR1_CC1S; + 62 .loc 1 7005 3 view .LVU15 + 63 .loc 1 7005 12 is_stmt 0 view .LVU16 + 64 0010 124B ldr r3, .L5 + ARM GAS /tmp/ccGFzgX3.s page 125 + + + 65 0012 2B40 ands r3, r3, r5 + 66 .LVL4: +7006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Output Compare Mode */ +7007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx |= OC_Config->OCMode; + 67 .loc 1 7007 3 is_stmt 1 view .LVU17 + 68 .loc 1 7007 24 is_stmt 0 view .LVU18 + 69 0014 0D68 ldr r5, [r1] + 70 .loc 1 7007 12 view .LVU19 + 71 0016 1D43 orrs r5, r5, r3 + 72 .LVL5: +7008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output Polarity level */ +7010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC1P; + 73 .loc 1 7010 3 is_stmt 1 view .LVU20 + 74 .loc 1 7010 11 is_stmt 0 view .LVU21 + 75 0018 24F00204 bic r4, r4, #2 + 76 .LVL6: +7011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output Compare Polarity */ +7012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= OC_Config->OCPolarity; + 77 .loc 1 7012 3 is_stmt 1 view .LVU22 + 78 .loc 1 7012 23 is_stmt 0 view .LVU23 + 79 001c 8B68 ldr r3, [r1, #8] + 80 .loc 1 7012 11 view .LVU24 + 81 001e 2343 orrs r3, r3, r4 + 82 .LVL7: +7013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + 83 .loc 1 7014 3 is_stmt 1 view .LVU25 + 84 .loc 1 7014 7 is_stmt 0 view .LVU26 + 85 0020 0F4C ldr r4, .L5+4 + 86 0022 104E ldr r6, .L5+8 + 87 .loc 1 7014 6 view .LVU27 + 88 0024 B042 cmp r0, r6 + 89 0026 18BF it ne + 90 0028 A042 cmpne r0, r4 + 91 002a 0CBF ite eq + 92 002c 0124 moveq r4, #1 + 93 002e 0024 movne r4, #0 + 94 0030 05D1 bne .L2 +7015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +7016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check parameters */ +7017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + 95 .loc 1 7017 5 is_stmt 1 view .LVU28 +7018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output N Polarity level */ +7020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC1NP; + 96 .loc 1 7020 5 view .LVU29 + 97 .loc 1 7020 13 is_stmt 0 view .LVU30 + 98 0032 23F00803 bic r3, r3, #8 + 99 .LVL8: +7021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output N Polarity */ +7022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= OC_Config->OCNPolarity; + 100 .loc 1 7022 5 is_stmt 1 view .LVU31 + 101 .loc 1 7022 25 is_stmt 0 view .LVU32 + 102 0036 CE68 ldr r6, [r1, #12] + 103 .loc 1 7022 13 view .LVU33 + 104 0038 1E43 orrs r6, r6, r3 + ARM GAS /tmp/ccGFzgX3.s page 126 + + + 105 .LVL9: +7023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output N State */ +7024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC1NE; + 106 .loc 1 7024 5 is_stmt 1 view .LVU34 + 107 .loc 1 7024 13 is_stmt 0 view .LVU35 + 108 003a 26F00403 bic r3, r6, #4 + 109 .LVL10: + 110 .L2: +7025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(TIMx)) + 111 .loc 1 7027 3 is_stmt 1 view .LVU36 + 112 .loc 1 7027 6 is_stmt 0 view .LVU37 + 113 003e 2CB1 cbz r4, .L3 +7028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +7029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check parameters */ +7030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + 114 .loc 1 7030 5 is_stmt 1 view .LVU38 +7031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + 115 .loc 1 7031 5 view .LVU39 +7032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output Compare and Output Compare N IDLE State */ +7034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_OIS1; + 116 .loc 1 7034 5 view .LVU40 + 117 .LVL11: +7035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_OIS1N; + 118 .loc 1 7035 5 view .LVU41 + 119 .loc 1 7035 12 is_stmt 0 view .LVU42 + 120 0040 22F44072 bic r2, r2, #768 + 121 .LVL12: +7036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output Idle state */ +7037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 |= OC_Config->OCIdleState; + 122 .loc 1 7037 5 is_stmt 1 view .LVU43 + 123 .loc 1 7037 24 is_stmt 0 view .LVU44 + 124 0044 4C69 ldr r4, [r1, #20] + 125 .loc 1 7037 12 view .LVU45 + 126 0046 1443 orrs r4, r4, r2 + 127 .LVL13: +7038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output N Idle state */ +7039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 |= OC_Config->OCNIdleState; + 128 .loc 1 7039 5 is_stmt 1 view .LVU46 + 129 .loc 1 7039 24 is_stmt 0 view .LVU47 + 130 0048 8A69 ldr r2, [r1, #24] + 131 .loc 1 7039 12 view .LVU48 + 132 004a 2243 orrs r2, r2, r4 + 133 .LVL14: + 134 .L3: +7040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CR2 */ +7043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CR2 = tmpcr2; + 135 .loc 1 7043 3 is_stmt 1 view .LVU49 + 136 .loc 1 7043 13 is_stmt 0 view .LVU50 + 137 004c 4260 str r2, [r0, #4] +7044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCMR1 */ +7046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCMR1 = tmpccmrx; + ARM GAS /tmp/ccGFzgX3.s page 127 + + + 138 .loc 1 7046 3 is_stmt 1 view .LVU51 + 139 .loc 1 7046 15 is_stmt 0 view .LVU52 + 140 004e 8561 str r5, [r0, #24] +7047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Capture Compare Register value */ +7049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCR1 = OC_Config->Pulse; + 141 .loc 1 7049 3 is_stmt 1 view .LVU53 + 142 .loc 1 7049 25 is_stmt 0 view .LVU54 + 143 0050 4A68 ldr r2, [r1, #4] + 144 .LVL15: + 145 .loc 1 7049 14 view .LVU55 + 146 0052 4263 str r2, [r0, #52] +7050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCER */ +7052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER = tmpccer; + 147 .loc 1 7052 3 is_stmt 1 view .LVU56 + 148 .loc 1 7052 14 is_stmt 0 view .LVU57 + 149 0054 0362 str r3, [r0, #32] +7053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 150 .loc 1 7053 1 view .LVU58 + 151 0056 70BC pop {r4, r5, r6} + 152 .LCFI1: + 153 .cfi_restore 6 + 154 .cfi_restore 5 + 155 .cfi_restore 4 + 156 .cfi_def_cfa_offset 0 + 157 .LVL16: + 158 .loc 1 7053 1 view .LVU59 + 159 0058 7047 bx lr + 160 .L6: + 161 005a 00BF .align 2 + 162 .L5: + 163 005c 8CFFFEFF .word -65652 + 164 0060 00000140 .word 1073807360 + 165 0064 00040140 .word 1073808384 + 166 .cfi_endproc + 167 .LFE246: + 169 .section .text.TIM_OC3_SetConfig,"ax",%progbits + 170 .align 1 + 171 .syntax unified + 172 .thumb + 173 .thumb_func + 175 TIM_OC3_SetConfig: + 176 .LVL17: + 177 .LFB248: +7054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +7056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Timer Output Compare 2 configuration +7057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param OC_Config The output configuration structure +7059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +7060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +7061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +7062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +7063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmrx; +7064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccer; +7065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpcr2; + ARM GAS /tmp/ccGFzgX3.s page 128 + + +7066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CCER register value */ +7068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer = TIMx->CCER; +7069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Channel 2: Reset the CC2E Bit */ +7071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC2E; +7072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CR2 register value */ +7074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 = TIMx->CR2; +7075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CCMR1 register value */ +7077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx = TIMx->CCMR1; +7078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output Compare mode and Capture/Compare selection Bits */ +7080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR1_OC2M; +7081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR1_CC2S; +7082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Output Compare Mode */ +7084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx |= (OC_Config->OCMode << 8U); +7085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output Polarity level */ +7087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC2P; +7088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output Compare Polarity */ +7089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= (OC_Config->OCPolarity << 4U); +7090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) +7092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +7093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); +7094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output N Polarity level */ +7096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC2NP; +7097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output N Polarity */ +7098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= (OC_Config->OCNPolarity << 4U); +7099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output N State */ +7100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC2NE; +7101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(TIMx)) +7104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +7105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check parameters */ +7106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); +7107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); +7108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output Compare and Output Compare N IDLE State */ +7110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_OIS2; +7111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_OIS2N; +7112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output Idle state */ +7113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 |= (OC_Config->OCIdleState << 2U); +7114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output N Idle state */ +7115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 |= (OC_Config->OCNIdleState << 2U); +7116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CR2 */ +7119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CR2 = tmpcr2; +7120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCMR1 */ +7122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCMR1 = tmpccmrx; + ARM GAS /tmp/ccGFzgX3.s page 129 + + +7123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Capture Compare Register value */ +7125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCR2 = OC_Config->Pulse; +7126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCER */ +7128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER = tmpccer; +7129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +7132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Timer Output Compare 3 configuration +7133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param OC_Config The output configuration structure +7135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +7136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +7137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +7138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 178 .loc 1 7138 1 is_stmt 1 view -0 + 179 .cfi_startproc + 180 @ args = 0, pretend = 0, frame = 0 + 181 @ frame_needed = 0, uses_anonymous_args = 0 + 182 @ link register save eliminated. + 183 .loc 1 7138 1 is_stmt 0 view .LVU61 + 184 0000 70B4 push {r4, r5, r6} + 185 .LCFI2: + 186 .cfi_def_cfa_offset 12 + 187 .cfi_offset 4, -12 + 188 .cfi_offset 5, -8 + 189 .cfi_offset 6, -4 +7139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmrx; + 190 .loc 1 7139 3 is_stmt 1 view .LVU62 +7140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccer; + 191 .loc 1 7140 3 view .LVU63 +7141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpcr2; + 192 .loc 1 7141 3 view .LVU64 +7142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CCER register value */ +7144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer = TIMx->CCER; + 193 .loc 1 7144 3 view .LVU65 + 194 .loc 1 7144 11 is_stmt 0 view .LVU66 + 195 0002 036A ldr r3, [r0, #32] + 196 .LVL18: +7145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Channel 3: Reset the CC2E Bit */ +7147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC3E; + 197 .loc 1 7147 3 is_stmt 1 view .LVU67 + 198 .loc 1 7147 7 is_stmt 0 view .LVU68 + 199 0004 026A ldr r2, [r0, #32] + 200 .loc 1 7147 14 view .LVU69 + 201 0006 22F48072 bic r2, r2, #256 + 202 000a 0262 str r2, [r0, #32] +7148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CR2 register value */ +7150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 = TIMx->CR2; + 203 .loc 1 7150 3 is_stmt 1 view .LVU70 + 204 .loc 1 7150 10 is_stmt 0 view .LVU71 + 205 000c 4268 ldr r2, [r0, #4] + 206 .LVL19: + ARM GAS /tmp/ccGFzgX3.s page 130 + + +7151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CCMR2 register value */ +7153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx = TIMx->CCMR2; + 207 .loc 1 7153 3 is_stmt 1 view .LVU72 + 208 .loc 1 7153 12 is_stmt 0 view .LVU73 + 209 000e C569 ldr r5, [r0, #28] + 210 .LVL20: +7154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output Compare mode and Capture/Compare selection Bits */ +7156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR2_OC3M; + 211 .loc 1 7156 3 is_stmt 1 view .LVU74 +7157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR2_CC3S; + 212 .loc 1 7157 3 view .LVU75 + 213 .loc 1 7157 12 is_stmt 0 view .LVU76 + 214 0010 144C ldr r4, .L11 + 215 0012 2C40 ands r4, r4, r5 + 216 .LVL21: +7158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Output Compare Mode */ +7159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx |= OC_Config->OCMode; + 217 .loc 1 7159 3 is_stmt 1 view .LVU77 + 218 .loc 1 7159 24 is_stmt 0 view .LVU78 + 219 0014 0E68 ldr r6, [r1] + 220 .loc 1 7159 12 view .LVU79 + 221 0016 2643 orrs r6, r6, r4 + 222 .LVL22: +7160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output Polarity level */ +7162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC3P; + 223 .loc 1 7162 3 is_stmt 1 view .LVU80 + 224 .loc 1 7162 11 is_stmt 0 view .LVU81 + 225 0018 23F40073 bic r3, r3, #512 + 226 .LVL23: +7163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output Compare Polarity */ +7164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= (OC_Config->OCPolarity << 8U); + 227 .loc 1 7164 3 is_stmt 1 view .LVU82 + 228 .loc 1 7164 24 is_stmt 0 view .LVU83 + 229 001c 8C68 ldr r4, [r1, #8] + 230 .loc 1 7164 11 view .LVU84 + 231 001e 43EA0423 orr r3, r3, r4, lsl #8 + 232 .LVL24: +7165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + 233 .loc 1 7166 3 is_stmt 1 view .LVU85 + 234 .loc 1 7166 7 is_stmt 0 view .LVU86 + 235 0022 114C ldr r4, .L11+4 + 236 0024 114D ldr r5, .L11+8 + 237 .loc 1 7166 6 view .LVU87 + 238 0026 A842 cmp r0, r5 + 239 0028 18BF it ne + 240 002a A042 cmpne r0, r4 + 241 002c 0CBF ite eq + 242 002e 0124 moveq r4, #1 + 243 0030 0024 movne r4, #0 + 244 0032 06D1 bne .L8 +7167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +7168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + 245 .loc 1 7168 5 is_stmt 1 view .LVU88 + ARM GAS /tmp/ccGFzgX3.s page 131 + + +7169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output N Polarity level */ +7171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC3NP; + 246 .loc 1 7171 5 view .LVU89 + 247 .loc 1 7171 13 is_stmt 0 view .LVU90 + 248 0034 23F40063 bic r3, r3, #2048 + 249 .LVL25: +7172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output N Polarity */ +7173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= (OC_Config->OCNPolarity << 8U); + 250 .loc 1 7173 5 is_stmt 1 view .LVU91 + 251 .loc 1 7173 26 is_stmt 0 view .LVU92 + 252 0038 CD68 ldr r5, [r1, #12] + 253 .loc 1 7173 13 view .LVU93 + 254 003a 43EA0523 orr r3, r3, r5, lsl #8 + 255 .LVL26: +7174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output N State */ +7175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC3NE; + 256 .loc 1 7175 5 is_stmt 1 view .LVU94 + 257 .loc 1 7175 13 is_stmt 0 view .LVU95 + 258 003e 23F48063 bic r3, r3, #1024 + 259 .LVL27: + 260 .L8: +7176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(TIMx)) + 261 .loc 1 7178 3 is_stmt 1 view .LVU96 + 262 .loc 1 7178 6 is_stmt 0 view .LVU97 + 263 0042 3CB1 cbz r4, .L9 +7179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +7180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check parameters */ +7181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + 264 .loc 1 7181 5 is_stmt 1 view .LVU98 +7182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + 265 .loc 1 7182 5 view .LVU99 +7183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output Compare and Output Compare N IDLE State */ +7185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_OIS3; + 266 .loc 1 7185 5 view .LVU100 + 267 .LVL28: +7186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_OIS3N; + 268 .loc 1 7186 5 view .LVU101 + 269 .loc 1 7186 12 is_stmt 0 view .LVU102 + 270 0044 22F44052 bic r2, r2, #12288 + 271 .LVL29: +7187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output Idle state */ +7188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 |= (OC_Config->OCIdleState << 4U); + 272 .loc 1 7188 5 is_stmt 1 view .LVU103 + 273 .loc 1 7188 25 is_stmt 0 view .LVU104 + 274 0048 4C69 ldr r4, [r1, #20] + 275 .loc 1 7188 12 view .LVU105 + 276 004a 42EA0412 orr r2, r2, r4, lsl #4 + 277 .LVL30: +7189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output N Idle state */ +7190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 |= (OC_Config->OCNIdleState << 4U); + 278 .loc 1 7190 5 is_stmt 1 view .LVU106 + 279 .loc 1 7190 25 is_stmt 0 view .LVU107 + 280 004e 8C69 ldr r4, [r1, #24] + ARM GAS /tmp/ccGFzgX3.s page 132 + + + 281 .loc 1 7190 12 view .LVU108 + 282 0050 42EA0412 orr r2, r2, r4, lsl #4 + 283 .LVL31: + 284 .L9: +7191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CR2 */ +7194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CR2 = tmpcr2; + 285 .loc 1 7194 3 is_stmt 1 view .LVU109 + 286 .loc 1 7194 13 is_stmt 0 view .LVU110 + 287 0054 4260 str r2, [r0, #4] +7195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCMR2 */ +7197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCMR2 = tmpccmrx; + 288 .loc 1 7197 3 is_stmt 1 view .LVU111 + 289 .loc 1 7197 15 is_stmt 0 view .LVU112 + 290 0056 C661 str r6, [r0, #28] +7198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Capture Compare Register value */ +7200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCR3 = OC_Config->Pulse; + 291 .loc 1 7200 3 is_stmt 1 view .LVU113 + 292 .loc 1 7200 25 is_stmt 0 view .LVU114 + 293 0058 4A68 ldr r2, [r1, #4] + 294 .LVL32: + 295 .loc 1 7200 14 view .LVU115 + 296 005a C263 str r2, [r0, #60] +7201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCER */ +7203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER = tmpccer; + 297 .loc 1 7203 3 is_stmt 1 view .LVU116 + 298 .loc 1 7203 14 is_stmt 0 view .LVU117 + 299 005c 0362 str r3, [r0, #32] +7204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 300 .loc 1 7204 1 view .LVU118 + 301 005e 70BC pop {r4, r5, r6} + 302 .LCFI3: + 303 .cfi_restore 6 + 304 .cfi_restore 5 + 305 .cfi_restore 4 + 306 .cfi_def_cfa_offset 0 + 307 .LVL33: + 308 .loc 1 7204 1 view .LVU119 + 309 0060 7047 bx lr + 310 .L12: + 311 0062 00BF .align 2 + 312 .L11: + 313 0064 8CFFFEFF .word -65652 + 314 0068 00000140 .word 1073807360 + 315 006c 00040140 .word 1073808384 + 316 .cfi_endproc + 317 .LFE248: + 319 .section .text.TIM_OC4_SetConfig,"ax",%progbits + 320 .align 1 + 321 .syntax unified + 322 .thumb + 323 .thumb_func + 325 TIM_OC4_SetConfig: + ARM GAS /tmp/ccGFzgX3.s page 133 + + + 326 .LVL34: + 327 .LFB249: +7205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +7207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Timer Output Compare 4 configuration +7208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param OC_Config The output configuration structure +7210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +7211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +7212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +7213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 328 .loc 1 7213 1 is_stmt 1 view -0 + 329 .cfi_startproc + 330 @ args = 0, pretend = 0, frame = 0 + 331 @ frame_needed = 0, uses_anonymous_args = 0 + 332 @ link register save eliminated. + 333 .loc 1 7213 1 is_stmt 0 view .LVU121 + 334 0000 70B4 push {r4, r5, r6} + 335 .LCFI4: + 336 .cfi_def_cfa_offset 12 + 337 .cfi_offset 4, -12 + 338 .cfi_offset 5, -8 + 339 .cfi_offset 6, -4 +7214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmrx; + 340 .loc 1 7214 3 is_stmt 1 view .LVU122 +7215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccer; + 341 .loc 1 7215 3 view .LVU123 +7216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpcr2; + 342 .loc 1 7216 3 view .LVU124 +7217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CCER register value */ +7219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer = TIMx->CCER; + 343 .loc 1 7219 3 view .LVU125 + 344 .loc 1 7219 11 is_stmt 0 view .LVU126 + 345 0002 036A ldr r3, [r0, #32] + 346 .LVL35: +7220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Channel 4: Reset the CC4E Bit */ +7222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC4E; + 347 .loc 1 7222 3 is_stmt 1 view .LVU127 + 348 .loc 1 7222 7 is_stmt 0 view .LVU128 + 349 0004 026A ldr r2, [r0, #32] + 350 .loc 1 7222 14 view .LVU129 + 351 0006 22F48052 bic r2, r2, #4096 + 352 000a 0262 str r2, [r0, #32] +7223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CR2 register value */ +7225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 = TIMx->CR2; + 353 .loc 1 7225 3 is_stmt 1 view .LVU130 + 354 .loc 1 7225 10 is_stmt 0 view .LVU131 + 355 000c 4468 ldr r4, [r0, #4] + 356 .LVL36: +7226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CCMR2 register value */ +7228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx = TIMx->CCMR2; + 357 .loc 1 7228 3 is_stmt 1 view .LVU132 + 358 .loc 1 7228 12 is_stmt 0 view .LVU133 + ARM GAS /tmp/ccGFzgX3.s page 134 + + + 359 000e C569 ldr r5, [r0, #28] + 360 .LVL37: +7229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output Compare mode and Capture/Compare selection Bits */ +7231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR2_OC4M; + 361 .loc 1 7231 3 is_stmt 1 view .LVU134 +7232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR2_CC4S; + 362 .loc 1 7232 3 view .LVU135 + 363 .loc 1 7232 12 is_stmt 0 view .LVU136 + 364 0010 0D4A ldr r2, .L16 + 365 0012 2A40 ands r2, r2, r5 + 366 .LVL38: +7233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Output Compare Mode */ +7235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx |= (OC_Config->OCMode << 8U); + 367 .loc 1 7235 3 is_stmt 1 view .LVU137 + 368 .loc 1 7235 25 is_stmt 0 view .LVU138 + 369 0014 0D68 ldr r5, [r1] + 370 .loc 1 7235 12 view .LVU139 + 371 0016 42EA0522 orr r2, r2, r5, lsl #8 + 372 .LVL39: +7236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output Polarity level */ +7238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC4P; + 373 .loc 1 7238 3 is_stmt 1 view .LVU140 + 374 .loc 1 7238 11 is_stmt 0 view .LVU141 + 375 001a 23F40053 bic r3, r3, #8192 + 376 .LVL40: +7239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output Compare Polarity */ +7240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= (OC_Config->OCPolarity << 12U); + 377 .loc 1 7240 3 is_stmt 1 view .LVU142 + 378 .loc 1 7240 24 is_stmt 0 view .LVU143 + 379 001e 8D68 ldr r5, [r1, #8] + 380 .loc 1 7240 11 view .LVU144 + 381 0020 43EA0533 orr r3, r3, r5, lsl #12 + 382 .LVL41: +7241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(TIMx)) + 383 .loc 1 7242 3 is_stmt 1 view .LVU145 + 384 .loc 1 7242 6 is_stmt 0 view .LVU146 + 385 0024 094E ldr r6, .L16+4 + 386 0026 0A4D ldr r5, .L16+8 + 387 0028 A842 cmp r0, r5 + 388 002a 18BF it ne + 389 002c B042 cmpne r0, r6 + 390 002e 04D1 bne .L14 +7243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +7244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check parameters */ +7245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + 391 .loc 1 7245 5 is_stmt 1 view .LVU147 +7246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output Compare IDLE State */ +7248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_OIS4; + 392 .loc 1 7248 5 view .LVU148 + 393 .loc 1 7248 12 is_stmt 0 view .LVU149 + 394 0030 24F48044 bic r4, r4, #16384 + 395 .LVL42: + ARM GAS /tmp/ccGFzgX3.s page 135 + + +7249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output Idle state */ +7251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 |= (OC_Config->OCIdleState << 6U); + 396 .loc 1 7251 5 is_stmt 1 view .LVU150 + 397 .loc 1 7251 25 is_stmt 0 view .LVU151 + 398 0034 4D69 ldr r5, [r1, #20] + 399 .loc 1 7251 12 view .LVU152 + 400 0036 44EA8514 orr r4, r4, r5, lsl #6 + 401 .LVL43: + 402 .L14: +7252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CR2 */ +7255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CR2 = tmpcr2; + 403 .loc 1 7255 3 is_stmt 1 view .LVU153 + 404 .loc 1 7255 13 is_stmt 0 view .LVU154 + 405 003a 4460 str r4, [r0, #4] +7256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCMR2 */ +7258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCMR2 = tmpccmrx; + 406 .loc 1 7258 3 is_stmt 1 view .LVU155 + 407 .loc 1 7258 15 is_stmt 0 view .LVU156 + 408 003c C261 str r2, [r0, #28] +7259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Capture Compare Register value */ +7261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCR4 = OC_Config->Pulse; + 409 .loc 1 7261 3 is_stmt 1 view .LVU157 + 410 .loc 1 7261 25 is_stmt 0 view .LVU158 + 411 003e 4A68 ldr r2, [r1, #4] + 412 .LVL44: + 413 .loc 1 7261 14 view .LVU159 + 414 0040 0264 str r2, [r0, #64] + 415 .LVL45: +7262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCER */ +7264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER = tmpccer; + 416 .loc 1 7264 3 is_stmt 1 view .LVU160 + 417 .loc 1 7264 14 is_stmt 0 view .LVU161 + 418 0042 0362 str r3, [r0, #32] +7265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 419 .loc 1 7265 1 view .LVU162 + 420 0044 70BC pop {r4, r5, r6} + 421 .LCFI5: + 422 .cfi_restore 6 + 423 .cfi_restore 5 + 424 .cfi_restore 4 + 425 .cfi_def_cfa_offset 0 + 426 .LVL46: + 427 .loc 1 7265 1 view .LVU163 + 428 0046 7047 bx lr + 429 .L17: + 430 .align 2 + 431 .L16: + 432 0048 FF8CFFFE .word -16806657 + 433 004c 00000140 .word 1073807360 + 434 0050 00040140 .word 1073808384 + 435 .cfi_endproc + ARM GAS /tmp/ccGFzgX3.s page 136 + + + 436 .LFE249: + 438 .section .text.TIM_OC5_SetConfig,"ax",%progbits + 439 .align 1 + 440 .syntax unified + 441 .thumb + 442 .thumb_func + 444 TIM_OC5_SetConfig: + 445 .LVL47: + 446 .LFB250: +7266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +7268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Timer Output Compare 5 configuration +7269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param OC_Config The output configuration structure +7271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +7272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +7273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, +7274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** const TIM_OC_InitTypeDef *OC_Config) +7275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 447 .loc 1 7275 1 is_stmt 1 view -0 + 448 .cfi_startproc + 449 @ args = 0, pretend = 0, frame = 0 + 450 @ frame_needed = 0, uses_anonymous_args = 0 + 451 @ link register save eliminated. + 452 .loc 1 7275 1 is_stmt 0 view .LVU165 + 453 0000 70B4 push {r4, r5, r6} + 454 .LCFI6: + 455 .cfi_def_cfa_offset 12 + 456 .cfi_offset 4, -12 + 457 .cfi_offset 5, -8 + 458 .cfi_offset 6, -4 +7276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmrx; + 459 .loc 1 7276 3 is_stmt 1 view .LVU166 +7277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccer; + 460 .loc 1 7277 3 view .LVU167 +7278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpcr2; + 461 .loc 1 7278 3 view .LVU168 +7279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CCER register value */ +7281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer = TIMx->CCER; + 462 .loc 1 7281 3 view .LVU169 + 463 .loc 1 7281 11 is_stmt 0 view .LVU170 + 464 0002 036A ldr r3, [r0, #32] + 465 .LVL48: +7282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the output: Reset the CCxE Bit */ +7284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC5E; + 466 .loc 1 7284 3 is_stmt 1 view .LVU171 + 467 .loc 1 7284 7 is_stmt 0 view .LVU172 + 468 0004 026A ldr r2, [r0, #32] + 469 .loc 1 7284 14 view .LVU173 + 470 0006 22F48032 bic r2, r2, #65536 + 471 000a 0262 str r2, [r0, #32] +7285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CR2 register value */ +7287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 = TIMx->CR2; + 472 .loc 1 7287 3 is_stmt 1 view .LVU174 + ARM GAS /tmp/ccGFzgX3.s page 137 + + + 473 .loc 1 7287 10 is_stmt 0 view .LVU175 + 474 000c 4468 ldr r4, [r0, #4] + 475 .LVL49: +7288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CCMR1 register value */ +7289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx = TIMx->CCMR3; + 476 .loc 1 7289 3 is_stmt 1 view .LVU176 + 477 .loc 1 7289 12 is_stmt 0 view .LVU177 + 478 000e 426D ldr r2, [r0, #84] + 479 .LVL50: +7290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output Compare Mode Bits */ +7292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx &= ~(TIM_CCMR3_OC5M); + 480 .loc 1 7292 3 is_stmt 1 view .LVU178 + 481 .loc 1 7292 12 is_stmt 0 view .LVU179 + 482 0010 0D4D ldr r5, .L21 + 483 0012 1540 ands r5, r5, r2 + 484 .LVL51: +7293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Output Compare Mode */ +7294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx |= OC_Config->OCMode; + 485 .loc 1 7294 3 is_stmt 1 view .LVU180 + 486 .loc 1 7294 24 is_stmt 0 view .LVU181 + 487 0014 0A68 ldr r2, [r1] + 488 .loc 1 7294 12 view .LVU182 + 489 0016 2A43 orrs r2, r2, r5 + 490 .LVL52: +7295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output Polarity level */ +7297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC5P; + 491 .loc 1 7297 3 is_stmt 1 view .LVU183 + 492 .loc 1 7297 11 is_stmt 0 view .LVU184 + 493 0018 23F40033 bic r3, r3, #131072 + 494 .LVL53: +7298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output Compare Polarity */ +7299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= (OC_Config->OCPolarity << 16U); + 495 .loc 1 7299 3 is_stmt 1 view .LVU185 + 496 .loc 1 7299 24 is_stmt 0 view .LVU186 + 497 001c 8D68 ldr r5, [r1, #8] + 498 .loc 1 7299 11 view .LVU187 + 499 001e 43EA0543 orr r3, r3, r5, lsl #16 + 500 .LVL54: +7300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(TIMx)) + 501 .loc 1 7301 3 is_stmt 1 view .LVU188 + 502 .loc 1 7301 6 is_stmt 0 view .LVU189 + 503 0022 0A4E ldr r6, .L21+4 + 504 0024 0A4D ldr r5, .L21+8 + 505 0026 A842 cmp r0, r5 + 506 0028 18BF it ne + 507 002a B042 cmpne r0, r6 + 508 002c 04D1 bne .L19 +7302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +7303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output Compare IDLE State */ +7304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_OIS5; + 509 .loc 1 7304 5 is_stmt 1 view .LVU190 + 510 .loc 1 7304 12 is_stmt 0 view .LVU191 + 511 002e 24F48034 bic r4, r4, #65536 + 512 .LVL55: + ARM GAS /tmp/ccGFzgX3.s page 138 + + +7305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output Idle state */ +7306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 |= (OC_Config->OCIdleState << 8U); + 513 .loc 1 7306 5 is_stmt 1 view .LVU192 + 514 .loc 1 7306 25 is_stmt 0 view .LVU193 + 515 0032 4D69 ldr r5, [r1, #20] + 516 .loc 1 7306 12 view .LVU194 + 517 0034 44EA0524 orr r4, r4, r5, lsl #8 + 518 .LVL56: + 519 .L19: +7307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CR2 */ +7309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CR2 = tmpcr2; + 520 .loc 1 7309 3 is_stmt 1 view .LVU195 + 521 .loc 1 7309 13 is_stmt 0 view .LVU196 + 522 0038 4460 str r4, [r0, #4] +7310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCMR3 */ +7312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCMR3 = tmpccmrx; + 523 .loc 1 7312 3 is_stmt 1 view .LVU197 + 524 .loc 1 7312 15 is_stmt 0 view .LVU198 + 525 003a 4265 str r2, [r0, #84] +7313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Capture Compare Register value */ +7315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCR5 = OC_Config->Pulse; + 526 .loc 1 7315 3 is_stmt 1 view .LVU199 + 527 .loc 1 7315 25 is_stmt 0 view .LVU200 + 528 003c 4A68 ldr r2, [r1, #4] + 529 .LVL57: + 530 .loc 1 7315 14 view .LVU201 + 531 003e 8265 str r2, [r0, #88] + 532 .LVL58: +7316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCER */ +7318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER = tmpccer; + 533 .loc 1 7318 3 is_stmt 1 view .LVU202 + 534 .loc 1 7318 14 is_stmt 0 view .LVU203 + 535 0040 0362 str r3, [r0, #32] +7319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 536 .loc 1 7319 1 view .LVU204 + 537 0042 70BC pop {r4, r5, r6} + 538 .LCFI7: + 539 .cfi_restore 6 + 540 .cfi_restore 5 + 541 .cfi_restore 4 + 542 .cfi_def_cfa_offset 0 + 543 .LVL59: + 544 .loc 1 7319 1 view .LVU205 + 545 0044 7047 bx lr + 546 .L22: + 547 0046 00BF .align 2 + 548 .L21: + 549 0048 8FFFFEFF .word -65649 + 550 004c 00000140 .word 1073807360 + 551 0050 00040140 .word 1073808384 + 552 .cfi_endproc + 553 .LFE250: + 555 .section .text.TIM_OC6_SetConfig,"ax",%progbits + ARM GAS /tmp/ccGFzgX3.s page 139 + + + 556 .align 1 + 557 .syntax unified + 558 .thumb + 559 .thumb_func + 561 TIM_OC6_SetConfig: + 562 .LVL60: + 563 .LFB251: +7320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +7322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Timer Output Compare 6 configuration +7323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param OC_Config The output configuration structure +7325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +7326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +7327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, +7328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** const TIM_OC_InitTypeDef *OC_Config) +7329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 564 .loc 1 7329 1 is_stmt 1 view -0 + 565 .cfi_startproc + 566 @ args = 0, pretend = 0, frame = 0 + 567 @ frame_needed = 0, uses_anonymous_args = 0 + 568 @ link register save eliminated. + 569 .loc 1 7329 1 is_stmt 0 view .LVU207 + 570 0000 70B4 push {r4, r5, r6} + 571 .LCFI8: + 572 .cfi_def_cfa_offset 12 + 573 .cfi_offset 4, -12 + 574 .cfi_offset 5, -8 + 575 .cfi_offset 6, -4 +7330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmrx; + 576 .loc 1 7330 3 is_stmt 1 view .LVU208 +7331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccer; + 577 .loc 1 7331 3 view .LVU209 +7332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpcr2; + 578 .loc 1 7332 3 view .LVU210 +7333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CCER register value */ +7335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer = TIMx->CCER; + 579 .loc 1 7335 3 view .LVU211 + 580 .loc 1 7335 11 is_stmt 0 view .LVU212 + 581 0002 036A ldr r3, [r0, #32] + 582 .LVL61: +7336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the output: Reset the CCxE Bit */ +7338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC6E; + 583 .loc 1 7338 3 is_stmt 1 view .LVU213 + 584 .loc 1 7338 7 is_stmt 0 view .LVU214 + 585 0004 026A ldr r2, [r0, #32] + 586 .loc 1 7338 14 view .LVU215 + 587 0006 22F48012 bic r2, r2, #1048576 + 588 000a 0262 str r2, [r0, #32] +7339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CR2 register value */ +7341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 = TIMx->CR2; + 589 .loc 1 7341 3 is_stmt 1 view .LVU216 + 590 .loc 1 7341 10 is_stmt 0 view .LVU217 + 591 000c 4468 ldr r4, [r0, #4] + ARM GAS /tmp/ccGFzgX3.s page 140 + + + 592 .LVL62: +7342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx CCMR1 register value */ +7343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx = TIMx->CCMR3; + 593 .loc 1 7343 3 is_stmt 1 view .LVU218 + 594 .loc 1 7343 12 is_stmt 0 view .LVU219 + 595 000e 456D ldr r5, [r0, #84] + 596 .LVL63: +7344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output Compare Mode Bits */ +7346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx &= ~(TIM_CCMR3_OC6M); + 597 .loc 1 7346 3 is_stmt 1 view .LVU220 + 598 .loc 1 7346 12 is_stmt 0 view .LVU221 + 599 0010 0D4A ldr r2, .L26 + 600 0012 2A40 ands r2, r2, r5 + 601 .LVL64: +7347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Output Compare Mode */ +7348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx |= (OC_Config->OCMode << 8U); + 602 .loc 1 7348 3 is_stmt 1 view .LVU222 + 603 .loc 1 7348 25 is_stmt 0 view .LVU223 + 604 0014 0D68 ldr r5, [r1] + 605 .loc 1 7348 12 view .LVU224 + 606 0016 42EA0522 orr r2, r2, r5, lsl #8 + 607 .LVL65: +7349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output Polarity level */ +7351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= (uint32_t)~TIM_CCER_CC6P; + 608 .loc 1 7351 3 is_stmt 1 view .LVU225 + 609 .loc 1 7351 11 is_stmt 0 view .LVU226 + 610 001a 23F40013 bic r3, r3, #2097152 + 611 .LVL66: +7352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output Compare Polarity */ +7353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= (OC_Config->OCPolarity << 20U); + 612 .loc 1 7353 3 is_stmt 1 view .LVU227 + 613 .loc 1 7353 24 is_stmt 0 view .LVU228 + 614 001e 8D68 ldr r5, [r1, #8] + 615 .loc 1 7353 11 view .LVU229 + 616 0020 43EA0553 orr r3, r3, r5, lsl #20 + 617 .LVL67: +7354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(TIMx)) + 618 .loc 1 7355 3 is_stmt 1 view .LVU230 + 619 .loc 1 7355 6 is_stmt 0 view .LVU231 + 620 0024 094E ldr r6, .L26+4 + 621 0026 0A4D ldr r5, .L26+8 + 622 0028 A842 cmp r0, r5 + 623 002a 18BF it ne + 624 002c B042 cmpne r0, r6 + 625 002e 04D1 bne .L24 +7356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +7357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output Compare IDLE State */ +7358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_OIS6; + 626 .loc 1 7358 5 is_stmt 1 view .LVU232 + 627 .loc 1 7358 12 is_stmt 0 view .LVU233 + 628 0030 24F48024 bic r4, r4, #262144 + 629 .LVL68: +7359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output Idle state */ +7360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 |= (OC_Config->OCIdleState << 10U); + ARM GAS /tmp/ccGFzgX3.s page 141 + + + 630 .loc 1 7360 5 is_stmt 1 view .LVU234 + 631 .loc 1 7360 25 is_stmt 0 view .LVU235 + 632 0034 4D69 ldr r5, [r1, #20] + 633 .loc 1 7360 12 view .LVU236 + 634 0036 44EA8524 orr r4, r4, r5, lsl #10 + 635 .LVL69: + 636 .L24: +7361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CR2 */ +7364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CR2 = tmpcr2; + 637 .loc 1 7364 3 is_stmt 1 view .LVU237 + 638 .loc 1 7364 13 is_stmt 0 view .LVU238 + 639 003a 4460 str r4, [r0, #4] +7365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCMR3 */ +7367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCMR3 = tmpccmrx; + 640 .loc 1 7367 3 is_stmt 1 view .LVU239 + 641 .loc 1 7367 15 is_stmt 0 view .LVU240 + 642 003c 4265 str r2, [r0, #84] +7368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Capture Compare Register value */ +7370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCR6 = OC_Config->Pulse; + 643 .loc 1 7370 3 is_stmt 1 view .LVU241 + 644 .loc 1 7370 25 is_stmt 0 view .LVU242 + 645 003e 4A68 ldr r2, [r1, #4] + 646 .LVL70: + 647 .loc 1 7370 14 view .LVU243 + 648 0040 C265 str r2, [r0, #92] + 649 .LVL71: +7371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCER */ +7373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER = tmpccer; + 650 .loc 1 7373 3 is_stmt 1 view .LVU244 + 651 .loc 1 7373 14 is_stmt 0 view .LVU245 + 652 0042 0362 str r3, [r0, #32] +7374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 653 .loc 1 7374 1 view .LVU246 + 654 0044 70BC pop {r4, r5, r6} + 655 .LCFI9: + 656 .cfi_restore 6 + 657 .cfi_restore 5 + 658 .cfi_restore 4 + 659 .cfi_def_cfa_offset 0 + 660 .LVL72: + 661 .loc 1 7374 1 view .LVU247 + 662 0046 7047 bx lr + 663 .L27: + 664 .align 2 + 665 .L26: + 666 0048 FF8FFFFE .word -16805889 + 667 004c 00000140 .word 1073807360 + 668 0050 00040140 .word 1073808384 + 669 .cfi_endproc + 670 .LFE251: + 672 .section .text.TIM_TI1_ConfigInputStage,"ax",%progbits + 673 .align 1 + ARM GAS /tmp/ccGFzgX3.s page 142 + + + 674 .syntax unified + 675 .thumb + 676 .thumb_func + 678 TIM_TI1_ConfigInputStage: + 679 .LVL73: + 680 .LFB254: +7375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +7377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Slave Timer configuration function +7378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param htim TIM handle +7379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param sSlaveConfig Slave timer configuration +7380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +7381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +7382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, +7383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** const TIM_SlaveConfigTypeDef *sSlaveConfig) +7384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +7385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +7386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; +7387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmr1; +7388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccer; +7389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx SMCR register value */ +7391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR; +7392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Trigger Selection Bits */ +7394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr &= ~TIM_SMCR_TS; +7395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Input Trigger source */ +7396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr |= sSlaveConfig->InputTrigger; +7397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the slave mode Bits */ +7399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr &= ~TIM_SMCR_SMS; +7400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the slave mode */ +7401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr |= sSlaveConfig->SlaveMode; +7402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx SMCR */ +7404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR = tmpsmcr; +7405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the trigger prescaler, filter, and polarity */ +7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (sSlaveConfig->InputTrigger) +7408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +7409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_TS_ETRF: +7410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +7411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +7412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); +7413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); +7414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); +7415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); +7416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the ETR Trigger source */ +7417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_ETR_SetConfig(htim->Instance, +7418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sSlaveConfig->TriggerPrescaler, +7419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sSlaveConfig->TriggerPolarity, +7420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sSlaveConfig->TriggerFilter); +7421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +7422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_TS_TI1F_ED: +7425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 143 + + +7426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +7427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +7428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); +7429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) +7431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +7432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; +7433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Channel 1: Reset the CC1E Bit */ +7436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer = htim->Instance->CCER; +7437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCER &= ~TIM_CCER_CC1E; +7438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 = htim->Instance->CCMR1; +7439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the filter */ +7441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_IC1F; +7442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); +7443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCMR1 and CCER registers */ +7445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 = tmpccmr1; +7446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCER = tmpccer; +7447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +7448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_TS_TI1FP1: +7451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +7452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +7453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +7454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); +7455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); +7456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure TI1 Filter and Polarity */ +7458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_TI1_ConfigInputStage(htim->Instance, +7459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sSlaveConfig->TriggerPolarity, +7460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sSlaveConfig->TriggerFilter); +7461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +7462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_TS_TI2FP2: +7465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +7466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +7467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +7468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); +7469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); +7470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure TI2 Filter and Polarity */ +7472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_TI2_ConfigInputStage(htim->Instance, +7473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sSlaveConfig->TriggerPolarity, +7474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sSlaveConfig->TriggerFilter); +7475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +7476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_TS_ITR0: +7479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_TS_ITR1: +7480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_TS_ITR2: +7481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** case TIM_TS_ITR3: +7482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 144 + + +7483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameter */ +7484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +7485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +7486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** default: +7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** status = HAL_ERROR; +7490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; +7491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return status; +7494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +7497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Configure the TI1 as Input. +7498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIMx to select the TIM peripheral. +7499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIM_ICPolarity The Input Polarity. +7500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +7501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICPOLARITY_RISING +7502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICPOLARITY_FALLING +7503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICPOLARITY_BOTHEDGE +7504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIM_ICSelection specifies the input to be used. +7505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +7506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. +7507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. +7508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. +7509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIM_ICFilter Specifies the Input Capture Filter. +7510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F. +7511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +7512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 +7513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * (on channel2 path) is used as the input signal. Therefore CCMR1 must be +7514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * protected against un-initialized filter and polarity values. +7515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +7516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, +7517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t TIM_ICFilter) +7518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +7519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmr1; +7520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccer; +7521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Channel 1: Reset the CC1E Bit */ +7523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer = TIMx->CCER; +7524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC1E; +7525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; +7526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Input */ +7528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) +7529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +7530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_CC1S; +7531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= TIM_ICSelection; +7532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** else +7534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { +7535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= TIM_CCMR1_CC1S_0; +7536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the filter */ +7539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_IC1F; + ARM GAS /tmp/ccGFzgX3.s page 145 + + +7540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); +7541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Polarity and set the CC1E Bit */ +7543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); +7544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); +7545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCMR1 and CCER registers */ +7547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCMR1 = tmpccmr1; +7548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER = tmpccer; +7549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } +7550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +7552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Configure the Polarity and Filter for TI1. +7553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIMx to select the TIM peripheral. +7554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIM_ICPolarity The Input Polarity. +7555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +7556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICPOLARITY_RISING +7557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICPOLARITY_FALLING +7558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICPOLARITY_BOTHEDGE +7559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIM_ICFilter Specifies the Input Capture Filter. +7560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F. +7561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +7562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +7563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil +7564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 681 .loc 1 7564 1 is_stmt 1 view -0 + 682 .cfi_startproc + 683 @ args = 0, pretend = 0, frame = 0 + 684 @ frame_needed = 0, uses_anonymous_args = 0 + 685 @ link register save eliminated. + 686 .loc 1 7564 1 is_stmt 0 view .LVU249 + 687 0000 10B4 push {r4} + 688 .LCFI10: + 689 .cfi_def_cfa_offset 4 + 690 .cfi_offset 4, -4 +7565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmr1; + 691 .loc 1 7565 3 is_stmt 1 view .LVU250 +7566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccer; + 692 .loc 1 7566 3 view .LVU251 +7567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Channel 1: Reset the CC1E Bit */ +7569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer = TIMx->CCER; + 693 .loc 1 7569 3 view .LVU252 + 694 .loc 1 7569 11 is_stmt 0 view .LVU253 + 695 0002 036A ldr r3, [r0, #32] + 696 .LVL74: +7570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC1E; + 697 .loc 1 7570 3 is_stmt 1 view .LVU254 + 698 .loc 1 7570 7 is_stmt 0 view .LVU255 + 699 0004 046A ldr r4, [r0, #32] + 700 .loc 1 7570 14 view .LVU256 + 701 0006 24F00104 bic r4, r4, #1 + 702 000a 0462 str r4, [r0, #32] +7571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; + 703 .loc 1 7571 3 is_stmt 1 view .LVU257 + 704 .loc 1 7571 12 is_stmt 0 view .LVU258 + 705 000c 8469 ldr r4, [r0, #24] + ARM GAS /tmp/ccGFzgX3.s page 146 + + + 706 .LVL75: +7572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the filter */ +7574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_IC1F; + 707 .loc 1 7574 3 is_stmt 1 view .LVU259 + 708 .loc 1 7574 12 is_stmt 0 view .LVU260 + 709 000e 24F0F00C bic ip, r4, #240 + 710 .LVL76: +7575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= (TIM_ICFilter << 4U); + 711 .loc 1 7575 3 is_stmt 1 view .LVU261 + 712 .loc 1 7575 12 is_stmt 0 view .LVU262 + 713 0012 4CEA0212 orr r2, ip, r2, lsl #4 + 714 .LVL77: +7576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Polarity and set the CC1E Bit */ +7578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + 715 .loc 1 7578 3 is_stmt 1 view .LVU263 + 716 .loc 1 7578 11 is_stmt 0 view .LVU264 + 717 0016 23F00A03 bic r3, r3, #10 + 718 .LVL78: +7579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= TIM_ICPolarity; + 719 .loc 1 7579 3 is_stmt 1 view .LVU265 + 720 .loc 1 7579 11 is_stmt 0 view .LVU266 + 721 001a 0B43 orrs r3, r3, r1 + 722 .LVL79: +7580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCMR1 and CCER registers */ +7582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCMR1 = tmpccmr1; + 723 .loc 1 7582 3 is_stmt 1 view .LVU267 + 724 .loc 1 7582 15 is_stmt 0 view .LVU268 + 725 001c 8261 str r2, [r0, #24] +7583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER = tmpccer; + 726 .loc 1 7583 3 is_stmt 1 view .LVU269 + 727 .loc 1 7583 14 is_stmt 0 view .LVU270 + 728 001e 0362 str r3, [r0, #32] +7584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 729 .loc 1 7584 1 view .LVU271 + 730 0020 5DF8044B ldr r4, [sp], #4 + 731 .LCFI11: + 732 .cfi_restore 4 + 733 .cfi_def_cfa_offset 0 + 734 0024 7047 bx lr + 735 .cfi_endproc + 736 .LFE254: + 738 .section .text.TIM_TI2_SetConfig,"ax",%progbits + 739 .align 1 + 740 .syntax unified + 741 .thumb + 742 .thumb_func + 744 TIM_TI2_SetConfig: + 745 .LVL80: + 746 .LFB255: +7585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +7587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Configure the TI2 as Input. +7588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIM_ICPolarity The Input Polarity. + ARM GAS /tmp/ccGFzgX3.s page 147 + + +7590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +7591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICPOLARITY_RISING +7592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICPOLARITY_FALLING +7593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICPOLARITY_BOTHEDGE +7594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIM_ICSelection specifies the input to be used. +7595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +7596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. +7597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. +7598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. +7599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIM_ICFilter Specifies the Input Capture Filter. +7600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F. +7601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +7602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 +7603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * (on channel1 path) is used as the input signal. Therefore CCMR1 must be +7604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * protected against un-initialized filter and polarity values. +7605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +7606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, +7607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t TIM_ICFilter) +7608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 747 .loc 1 7608 1 is_stmt 1 view -0 + 748 .cfi_startproc + 749 @ args = 0, pretend = 0, frame = 0 + 750 @ frame_needed = 0, uses_anonymous_args = 0 + 751 @ link register save eliminated. + 752 .loc 1 7608 1 is_stmt 0 view .LVU273 + 753 0000 30B4 push {r4, r5} + 754 .LCFI12: + 755 .cfi_def_cfa_offset 8 + 756 .cfi_offset 4, -8 + 757 .cfi_offset 5, -4 +7609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmr1; + 758 .loc 1 7609 3 is_stmt 1 view .LVU274 +7610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccer; + 759 .loc 1 7610 3 view .LVU275 +7611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Channel 2: Reset the CC2E Bit */ +7613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer = TIMx->CCER; + 760 .loc 1 7613 3 view .LVU276 + 761 .loc 1 7613 11 is_stmt 0 view .LVU277 + 762 0002 056A ldr r5, [r0, #32] + 763 .LVL81: +7614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC2E; + 764 .loc 1 7614 3 is_stmt 1 view .LVU278 + 765 .loc 1 7614 7 is_stmt 0 view .LVU279 + 766 0004 046A ldr r4, [r0, #32] + 767 .loc 1 7614 14 view .LVU280 + 768 0006 24F01004 bic r4, r4, #16 + 769 000a 0462 str r4, [r0, #32] +7615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; + 770 .loc 1 7615 3 is_stmt 1 view .LVU281 + 771 .loc 1 7615 12 is_stmt 0 view .LVU282 + 772 000c 8469 ldr r4, [r0, #24] + 773 .LVL82: +7616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Input */ +7618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_CC2S; + 774 .loc 1 7618 3 is_stmt 1 view .LVU283 + ARM GAS /tmp/ccGFzgX3.s page 148 + + + 775 .loc 1 7618 12 is_stmt 0 view .LVU284 + 776 000e 24F4407C bic ip, r4, #768 + 777 .LVL83: +7619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= (TIM_ICSelection << 8U); + 778 .loc 1 7619 3 is_stmt 1 view .LVU285 + 779 .loc 1 7619 12 is_stmt 0 view .LVU286 + 780 0012 4CEA022C orr ip, ip, r2, lsl #8 + 781 .LVL84: +7620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the filter */ +7622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_IC2F; + 782 .loc 1 7622 3 is_stmt 1 view .LVU287 + 783 .loc 1 7622 12 is_stmt 0 view .LVU288 + 784 0016 2CF4704C bic ip, ip, #61440 + 785 .LVL85: +7623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + 786 .loc 1 7623 3 is_stmt 1 view .LVU289 + 787 .loc 1 7623 30 is_stmt 0 view .LVU290 + 788 001a 1B03 lsls r3, r3, #12 + 789 .LVL86: + 790 .loc 1 7623 38 view .LVU291 + 791 001c 9BB2 uxth r3, r3 + 792 .loc 1 7623 12 view .LVU292 + 793 001e 43EA0C03 orr r3, r3, ip + 794 .LVL87: +7624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Polarity and set the CC2E Bit */ +7626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + 795 .loc 1 7626 3 is_stmt 1 view .LVU293 + 796 .loc 1 7626 11 is_stmt 0 view .LVU294 + 797 0022 25F0A005 bic r5, r5, #160 + 798 .LVL88: +7627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + 799 .loc 1 7627 3 is_stmt 1 view .LVU295 + 800 .loc 1 7627 31 is_stmt 0 view .LVU296 + 801 0026 0901 lsls r1, r1, #4 + 802 .LVL89: + 803 .loc 1 7627 38 view .LVU297 + 804 0028 01F0A001 and r1, r1, #160 + 805 .loc 1 7627 11 view .LVU298 + 806 002c 2943 orrs r1, r1, r5 + 807 .LVL90: +7628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCMR1 and CCER registers */ +7630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCMR1 = tmpccmr1 ; + 808 .loc 1 7630 3 is_stmt 1 view .LVU299 + 809 .loc 1 7630 15 is_stmt 0 view .LVU300 + 810 002e 8361 str r3, [r0, #24] +7631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER = tmpccer; + 811 .loc 1 7631 3 is_stmt 1 view .LVU301 + 812 .loc 1 7631 14 is_stmt 0 view .LVU302 + 813 0030 0162 str r1, [r0, #32] +7632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 814 .loc 1 7632 1 view .LVU303 + 815 0032 30BC pop {r4, r5} + 816 .LCFI13: + 817 .cfi_restore 5 + ARM GAS /tmp/ccGFzgX3.s page 149 + + + 818 .cfi_restore 4 + 819 .cfi_def_cfa_offset 0 + 820 0034 7047 bx lr + 821 .cfi_endproc + 822 .LFE255: + 824 .section .text.TIM_TI2_ConfigInputStage,"ax",%progbits + 825 .align 1 + 826 .syntax unified + 827 .thumb + 828 .thumb_func + 830 TIM_TI2_ConfigInputStage: + 831 .LVL91: + 832 .LFB256: +7633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +7635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Configure the Polarity and Filter for TI2. +7636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIMx to select the TIM peripheral. +7637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIM_ICPolarity The Input Polarity. +7638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +7639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICPOLARITY_RISING +7640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICPOLARITY_FALLING +7641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICPOLARITY_BOTHEDGE +7642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIM_ICFilter Specifies the Input Capture Filter. +7643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F. +7644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +7645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +7646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil +7647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 833 .loc 1 7647 1 is_stmt 1 view -0 + 834 .cfi_startproc + 835 @ args = 0, pretend = 0, frame = 0 + 836 @ frame_needed = 0, uses_anonymous_args = 0 + 837 @ link register save eliminated. + 838 .loc 1 7647 1 is_stmt 0 view .LVU305 + 839 0000 10B4 push {r4} + 840 .LCFI14: + 841 .cfi_def_cfa_offset 4 + 842 .cfi_offset 4, -4 +7648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmr1; + 843 .loc 1 7648 3 is_stmt 1 view .LVU306 +7649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccer; + 844 .loc 1 7649 3 view .LVU307 +7650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Channel 2: Reset the CC2E Bit */ +7652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer = TIMx->CCER; + 845 .loc 1 7652 3 view .LVU308 + 846 .loc 1 7652 11 is_stmt 0 view .LVU309 + 847 0002 036A ldr r3, [r0, #32] + 848 .LVL92: +7653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC2E; + 849 .loc 1 7653 3 is_stmt 1 view .LVU310 + 850 .loc 1 7653 7 is_stmt 0 view .LVU311 + 851 0004 046A ldr r4, [r0, #32] + 852 .loc 1 7653 14 view .LVU312 + 853 0006 24F01004 bic r4, r4, #16 + 854 000a 0462 str r4, [r0, #32] +7654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; + ARM GAS /tmp/ccGFzgX3.s page 150 + + + 855 .loc 1 7654 3 is_stmt 1 view .LVU313 + 856 .loc 1 7654 12 is_stmt 0 view .LVU314 + 857 000c 8469 ldr r4, [r0, #24] + 858 .LVL93: +7655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the filter */ +7657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_IC2F; + 859 .loc 1 7657 3 is_stmt 1 view .LVU315 + 860 .loc 1 7657 12 is_stmt 0 view .LVU316 + 861 000e 24F4704C bic ip, r4, #61440 + 862 .LVL94: +7658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= (TIM_ICFilter << 12U); + 863 .loc 1 7658 3 is_stmt 1 view .LVU317 + 864 .loc 1 7658 12 is_stmt 0 view .LVU318 + 865 0012 4CEA0232 orr r2, ip, r2, lsl #12 + 866 .LVL95: +7659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Polarity and set the CC2E Bit */ +7661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + 867 .loc 1 7661 3 is_stmt 1 view .LVU319 + 868 .loc 1 7661 11 is_stmt 0 view .LVU320 + 869 0016 23F0A003 bic r3, r3, #160 + 870 .LVL96: +7662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= (TIM_ICPolarity << 4U); + 871 .loc 1 7662 3 is_stmt 1 view .LVU321 + 872 .loc 1 7662 11 is_stmt 0 view .LVU322 + 873 001a 43EA0113 orr r3, r3, r1, lsl #4 + 874 .LVL97: +7663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCMR1 and CCER registers */ +7665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCMR1 = tmpccmr1 ; + 875 .loc 1 7665 3 is_stmt 1 view .LVU323 + 876 .loc 1 7665 15 is_stmt 0 view .LVU324 + 877 001e 8261 str r2, [r0, #24] +7666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER = tmpccer; + 878 .loc 1 7666 3 is_stmt 1 view .LVU325 + 879 .loc 1 7666 14 is_stmt 0 view .LVU326 + 880 0020 0362 str r3, [r0, #32] +7667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 881 .loc 1 7667 1 view .LVU327 + 882 0022 5DF8044B ldr r4, [sp], #4 + 883 .LCFI15: + 884 .cfi_restore 4 + 885 .cfi_def_cfa_offset 0 + 886 0026 7047 bx lr + 887 .cfi_endproc + 888 .LFE256: + 890 .section .text.TIM_TI3_SetConfig,"ax",%progbits + 891 .align 1 + 892 .syntax unified + 893 .thumb + 894 .thumb_func + 896 TIM_TI3_SetConfig: + 897 .LVL98: + 898 .LFB257: +7668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + ARM GAS /tmp/ccGFzgX3.s page 151 + + +7670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Configure the TI3 as Input. +7671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIM_ICPolarity The Input Polarity. +7673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +7674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICPOLARITY_RISING +7675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICPOLARITY_FALLING +7676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICPOLARITY_BOTHEDGE +7677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIM_ICSelection specifies the input to be used. +7678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +7679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. +7680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. +7681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. +7682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIM_ICFilter Specifies the Input Capture Filter. +7683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F. +7684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +7685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 +7686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * (on channel1 path) is used as the input signal. Therefore CCMR2 must be +7687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * protected against un-initialized filter and polarity values. +7688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +7689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, +7690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t TIM_ICFilter) +7691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 899 .loc 1 7691 1 is_stmt 1 view -0 + 900 .cfi_startproc + 901 @ args = 0, pretend = 0, frame = 0 + 902 @ frame_needed = 0, uses_anonymous_args = 0 + 903 @ link register save eliminated. + 904 .loc 1 7691 1 is_stmt 0 view .LVU329 + 905 0000 30B4 push {r4, r5} + 906 .LCFI16: + 907 .cfi_def_cfa_offset 8 + 908 .cfi_offset 4, -8 + 909 .cfi_offset 5, -4 +7692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmr2; + 910 .loc 1 7692 3 is_stmt 1 view .LVU330 +7693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccer; + 911 .loc 1 7693 3 view .LVU331 +7694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Channel 3: Reset the CC3E Bit */ +7696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer = TIMx->CCER; + 912 .loc 1 7696 3 view .LVU332 + 913 .loc 1 7696 11 is_stmt 0 view .LVU333 + 914 0002 056A ldr r5, [r0, #32] + 915 .LVL99: +7697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC3E; + 916 .loc 1 7697 3 is_stmt 1 view .LVU334 + 917 .loc 1 7697 7 is_stmt 0 view .LVU335 + 918 0004 046A ldr r4, [r0, #32] + 919 .loc 1 7697 14 view .LVU336 + 920 0006 24F48074 bic r4, r4, #256 + 921 000a 0462 str r4, [r0, #32] +7698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr2 = TIMx->CCMR2; + 922 .loc 1 7698 3 is_stmt 1 view .LVU337 + 923 .loc 1 7698 12 is_stmt 0 view .LVU338 + 924 000c C469 ldr r4, [r0, #28] + 925 .LVL100: +7699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 152 + + +7700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Input */ +7701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr2 &= ~TIM_CCMR2_CC3S; + 926 .loc 1 7701 3 is_stmt 1 view .LVU339 + 927 .loc 1 7701 12 is_stmt 0 view .LVU340 + 928 000e 24F0030C bic ip, r4, #3 + 929 .LVL101: +7702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr2 |= TIM_ICSelection; + 930 .loc 1 7702 3 is_stmt 1 view .LVU341 + 931 .loc 1 7702 12 is_stmt 0 view .LVU342 + 932 0012 4CEA020C orr ip, ip, r2 + 933 .LVL102: +7703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the filter */ +7705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr2 &= ~TIM_CCMR2_IC3F; + 934 .loc 1 7705 3 is_stmt 1 view .LVU343 + 935 .loc 1 7705 12 is_stmt 0 view .LVU344 + 936 0016 2CF0F00C bic ip, ip, #240 + 937 .LVL103: +7706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + 938 .loc 1 7706 3 is_stmt 1 view .LVU345 + 939 .loc 1 7706 30 is_stmt 0 view .LVU346 + 940 001a 1B01 lsls r3, r3, #4 + 941 .LVL104: + 942 .loc 1 7706 37 view .LVU347 + 943 001c DBB2 uxtb r3, r3 + 944 .loc 1 7706 12 view .LVU348 + 945 001e 43EA0C03 orr r3, r3, ip + 946 .LVL105: +7707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Polarity and set the CC3E Bit */ +7709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + 947 .loc 1 7709 3 is_stmt 1 view .LVU349 + 948 .loc 1 7709 11 is_stmt 0 view .LVU350 + 949 0022 25F42065 bic r5, r5, #2560 + 950 .LVL106: +7710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + 951 .loc 1 7710 3 is_stmt 1 view .LVU351 + 952 .loc 1 7710 31 is_stmt 0 view .LVU352 + 953 0026 0902 lsls r1, r1, #8 + 954 .LVL107: + 955 .loc 1 7710 38 view .LVU353 + 956 0028 01F42061 and r1, r1, #2560 + 957 .loc 1 7710 11 view .LVU354 + 958 002c 2943 orrs r1, r1, r5 + 959 .LVL108: +7711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCMR2 and CCER registers */ +7713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCMR2 = tmpccmr2; + 960 .loc 1 7713 3 is_stmt 1 view .LVU355 + 961 .loc 1 7713 15 is_stmt 0 view .LVU356 + 962 002e C361 str r3, [r0, #28] +7714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER = tmpccer; + 963 .loc 1 7714 3 is_stmt 1 view .LVU357 + 964 .loc 1 7714 14 is_stmt 0 view .LVU358 + 965 0030 0162 str r1, [r0, #32] +7715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 966 .loc 1 7715 1 view .LVU359 + ARM GAS /tmp/ccGFzgX3.s page 153 + + + 967 0032 30BC pop {r4, r5} + 968 .LCFI17: + 969 .cfi_restore 5 + 970 .cfi_restore 4 + 971 .cfi_def_cfa_offset 0 + 972 0034 7047 bx lr + 973 .cfi_endproc + 974 .LFE257: + 976 .section .text.TIM_TI4_SetConfig,"ax",%progbits + 977 .align 1 + 978 .syntax unified + 979 .thumb + 980 .thumb_func + 982 TIM_TI4_SetConfig: + 983 .LVL109: + 984 .LFB258: +7716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +7718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Configure the TI4 as Input. +7719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIM_ICPolarity The Input Polarity. +7721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +7722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICPOLARITY_RISING +7723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICPOLARITY_FALLING +7724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICPOLARITY_BOTHEDGE +7725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIM_ICSelection specifies the input to be used. +7726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +7727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. +7728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. +7729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. +7730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIM_ICFilter Specifies the Input Capture Filter. +7731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F. +7732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 +7733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * (on channel1 path) is used as the input signal. Therefore CCMR2 must be +7734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * protected against un-initialized filter and polarity values. +7735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +7736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +7737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, +7738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t TIM_ICFilter) +7739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 985 .loc 1 7739 1 is_stmt 1 view -0 + 986 .cfi_startproc + 987 @ args = 0, pretend = 0, frame = 0 + 988 @ frame_needed = 0, uses_anonymous_args = 0 + 989 @ link register save eliminated. + 990 .loc 1 7739 1 is_stmt 0 view .LVU361 + 991 0000 30B4 push {r4, r5} + 992 .LCFI18: + 993 .cfi_def_cfa_offset 8 + 994 .cfi_offset 4, -8 + 995 .cfi_offset 5, -4 +7740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmr2; + 996 .loc 1 7740 3 is_stmt 1 view .LVU362 +7741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccer; + 997 .loc 1 7741 3 view .LVU363 +7742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Disable the Channel 4: Reset the CC4E Bit */ + ARM GAS /tmp/ccGFzgX3.s page 154 + + +7744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer = TIMx->CCER; + 998 .loc 1 7744 3 view .LVU364 + 999 .loc 1 7744 11 is_stmt 0 view .LVU365 + 1000 0002 056A ldr r5, [r0, #32] + 1001 .LVL110: +7745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC4E; + 1002 .loc 1 7745 3 is_stmt 1 view .LVU366 + 1003 .loc 1 7745 7 is_stmt 0 view .LVU367 + 1004 0004 046A ldr r4, [r0, #32] + 1005 .loc 1 7745 14 view .LVU368 + 1006 0006 24F48054 bic r4, r4, #4096 + 1007 000a 0462 str r4, [r0, #32] +7746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr2 = TIMx->CCMR2; + 1008 .loc 1 7746 3 is_stmt 1 view .LVU369 + 1009 .loc 1 7746 12 is_stmt 0 view .LVU370 + 1010 000c C469 ldr r4, [r0, #28] + 1011 .LVL111: +7747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Input */ +7749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr2 &= ~TIM_CCMR2_CC4S; + 1012 .loc 1 7749 3 is_stmt 1 view .LVU371 + 1013 .loc 1 7749 12 is_stmt 0 view .LVU372 + 1014 000e 24F4407C bic ip, r4, #768 + 1015 .LVL112: +7750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr2 |= (TIM_ICSelection << 8U); + 1016 .loc 1 7750 3 is_stmt 1 view .LVU373 + 1017 .loc 1 7750 12 is_stmt 0 view .LVU374 + 1018 0012 4CEA022C orr ip, ip, r2, lsl #8 + 1019 .LVL113: +7751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the filter */ +7753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr2 &= ~TIM_CCMR2_IC4F; + 1020 .loc 1 7753 3 is_stmt 1 view .LVU375 + 1021 .loc 1 7753 12 is_stmt 0 view .LVU376 + 1022 0016 2CF4704C bic ip, ip, #61440 + 1023 .LVL114: +7754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + 1024 .loc 1 7754 3 is_stmt 1 view .LVU377 + 1025 .loc 1 7754 30 is_stmt 0 view .LVU378 + 1026 001a 1B03 lsls r3, r3, #12 + 1027 .LVL115: + 1028 .loc 1 7754 38 view .LVU379 + 1029 001c 9BB2 uxth r3, r3 + 1030 .loc 1 7754 12 view .LVU380 + 1031 001e 43EA0C03 orr r3, r3, ip + 1032 .LVL116: +7755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Select the Polarity and set the CC4E Bit */ +7757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + 1033 .loc 1 7757 3 is_stmt 1 view .LVU381 + 1034 .loc 1 7757 11 is_stmt 0 view .LVU382 + 1035 0022 25F42045 bic r5, r5, #40960 + 1036 .LVL117: +7758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + 1037 .loc 1 7758 3 is_stmt 1 view .LVU383 + 1038 .loc 1 7758 31 is_stmt 0 view .LVU384 + 1039 0026 0903 lsls r1, r1, #12 + ARM GAS /tmp/ccGFzgX3.s page 155 + + + 1040 .LVL118: + 1041 .loc 1 7758 39 view .LVU385 + 1042 0028 01F42041 and r1, r1, #40960 + 1043 .loc 1 7758 11 view .LVU386 + 1044 002c 2943 orrs r1, r1, r5 + 1045 .LVL119: +7759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx CCMR2 and CCER registers */ +7761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCMR2 = tmpccmr2; + 1046 .loc 1 7761 3 is_stmt 1 view .LVU387 + 1047 .loc 1 7761 15 is_stmt 0 view .LVU388 + 1048 002e C361 str r3, [r0, #28] +7762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER = tmpccer ; + 1049 .loc 1 7762 3 is_stmt 1 view .LVU389 + 1050 .loc 1 7762 14 is_stmt 0 view .LVU390 + 1051 0030 0162 str r1, [r0, #32] +7763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1052 .loc 1 7763 1 view .LVU391 + 1053 0032 30BC pop {r4, r5} + 1054 .LCFI19: + 1055 .cfi_restore 5 + 1056 .cfi_restore 4 + 1057 .cfi_def_cfa_offset 0 + 1058 0034 7047 bx lr + 1059 .cfi_endproc + 1060 .LFE258: + 1062 .section .text.TIM_ITRx_SetConfig,"ax",%progbits + 1063 .align 1 + 1064 .syntax unified + 1065 .thumb + 1066 .thumb_func + 1068 TIM_ITRx_SetConfig: + 1069 .LVL120: + 1070 .LFB259: +7764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +7766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Selects the Input Trigger source +7767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param InputTriggerSource The Input Trigger source. +7769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +7770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_TS_ITR0: Internal Trigger 0 +7771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_TS_ITR1: Internal Trigger 1 +7772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_TS_ITR2: Internal Trigger 2 +7773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_TS_ITR3: Internal Trigger 3 +7774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_TS_TI1F_ED: TI1 Edge Detector +7775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 +7776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 +7777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_TS_ETRF: External Trigger input +7778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +7779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +7780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +7781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1071 .loc 1 7781 1 is_stmt 1 view -0 + 1072 .cfi_startproc + 1073 @ args = 0, pretend = 0, frame = 0 + 1074 @ frame_needed = 0, uses_anonymous_args = 0 + 1075 @ link register save eliminated. + ARM GAS /tmp/ccGFzgX3.s page 156 + + +7782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 1076 .loc 1 7782 3 view .LVU393 +7783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Get the TIMx SMCR register value */ +7785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr = TIMx->SMCR; + 1077 .loc 1 7785 3 view .LVU394 + 1078 .loc 1 7785 11 is_stmt 0 view .LVU395 + 1079 0000 8368 ldr r3, [r0, #8] + 1080 .LVL121: +7786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the TS Bits */ +7787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr &= ~TIM_SMCR_TS; + 1081 .loc 1 7787 3 is_stmt 1 view .LVU396 + 1082 .loc 1 7787 11 is_stmt 0 view .LVU397 + 1083 0002 23F07003 bic r3, r3, #112 + 1084 .LVL122: +7788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Input Trigger source and the slave mode*/ +7789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + 1085 .loc 1 7789 3 is_stmt 1 view .LVU398 + 1086 .loc 1 7789 11 is_stmt 0 view .LVU399 + 1087 0006 0B43 orrs r3, r3, r1 + 1088 .LVL123: + 1089 .loc 1 7789 11 view .LVU400 + 1090 0008 43F00703 orr r3, r3, #7 + 1091 .LVL124: +7790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx SMCR */ +7791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->SMCR = tmpsmcr; + 1092 .loc 1 7791 3 is_stmt 1 view .LVU401 + 1093 .loc 1 7791 14 is_stmt 0 view .LVU402 + 1094 000c 8360 str r3, [r0, #8] +7792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1095 .loc 1 7792 1 view .LVU403 + 1096 000e 7047 bx lr + 1097 .cfi_endproc + 1098 .LFE259: + 1100 .section .text.HAL_TIM_Base_MspInit,"ax",%progbits + 1101 .align 1 + 1102 .weak HAL_TIM_Base_MspInit + 1103 .syntax unified + 1104 .thumb + 1105 .thumb_func + 1107 HAL_TIM_Base_MspInit: + 1108 .LVL125: + 1109 .LFB143: + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 1110 .loc 1 373 1 is_stmt 1 view -0 + 1111 .cfi_startproc + 1112 @ args = 0, pretend = 0, frame = 0 + 1113 @ frame_needed = 0, uses_anonymous_args = 0 + 1114 @ link register save eliminated. + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1115 .loc 1 375 3 view .LVU405 + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1116 .loc 1 380 1 is_stmt 0 view .LVU406 + 1117 0000 7047 bx lr + 1118 .cfi_endproc + 1119 .LFE143: + 1121 .section .text.HAL_TIM_Base_MspDeInit,"ax",%progbits + ARM GAS /tmp/ccGFzgX3.s page 157 + + + 1122 .align 1 + 1123 .weak HAL_TIM_Base_MspDeInit + 1124 .syntax unified + 1125 .thumb + 1126 .thumb_func + 1128 HAL_TIM_Base_MspDeInit: + 1129 .LVL126: + 1130 .LFB144: + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 1131 .loc 1 388 1 is_stmt 1 view -0 + 1132 .cfi_startproc + 1133 @ args = 0, pretend = 0, frame = 0 + 1134 @ frame_needed = 0, uses_anonymous_args = 0 + 1135 @ link register save eliminated. + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1136 .loc 1 390 3 view .LVU408 + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1137 .loc 1 395 1 is_stmt 0 view .LVU409 + 1138 0000 7047 bx lr + 1139 .cfi_endproc + 1140 .LFE144: + 1142 .section .text.HAL_TIM_Base_DeInit,"ax",%progbits + 1143 .align 1 + 1144 .global HAL_TIM_Base_DeInit + 1145 .syntax unified + 1146 .thumb + 1147 .thumb_func + 1149 HAL_TIM_Base_DeInit: + 1150 .LVL127: + 1151 .LFB142: + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 1152 .loc 1 330 1 is_stmt 1 view -0 + 1153 .cfi_startproc + 1154 @ args = 0, pretend = 0, frame = 0 + 1155 @ frame_needed = 0, uses_anonymous_args = 0 + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 1156 .loc 1 330 1 is_stmt 0 view .LVU411 + 1157 0000 10B5 push {r4, lr} + 1158 .LCFI20: + 1159 .cfi_def_cfa_offset 8 + 1160 .cfi_offset 4, -8 + 1161 .cfi_offset 14, -4 + 1162 0002 0446 mov r4, r0 + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1163 .loc 1 332 3 is_stmt 1 view .LVU412 + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1164 .loc 1 334 3 view .LVU413 + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1165 .loc 1 334 15 is_stmt 0 view .LVU414 + 1166 0004 0223 movs r3, #2 + 1167 0006 80F83D30 strb r3, [r0, #61] + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1168 .loc 1 337 3 is_stmt 1 view .LVU415 + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1169 .loc 1 337 3 view .LVU416 + 1170 000a 0368 ldr r3, [r0] + 1171 000c 196A ldr r1, [r3, #32] + ARM GAS /tmp/ccGFzgX3.s page 158 + + + 1172 000e 41F21112 movw r2, #4369 + 1173 0012 1142 tst r1, r2 + 1174 0014 08D1 bne .L42 + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1175 .loc 1 337 3 discriminator 1 view .LVU417 + 1176 0016 196A ldr r1, [r3, #32] + 1177 0018 40F24442 movw r2, #1092 + 1178 001c 1142 tst r1, r2 + 1179 001e 03D1 bne .L42 + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1180 .loc 1 337 3 discriminator 3 view .LVU418 + 1181 0020 1A68 ldr r2, [r3] + 1182 0022 22F00102 bic r2, r2, #1 + 1183 0026 1A60 str r2, [r3] + 1184 .L42: + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1185 .loc 1 337 3 discriminator 5 view .LVU419 + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 1186 .loc 1 348 3 view .LVU420 + 1187 0028 2046 mov r0, r4 + 1188 .LVL128: + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 1189 .loc 1 348 3 is_stmt 0 view .LVU421 + 1190 002a FFF7FEFF bl HAL_TIM_Base_MspDeInit + 1191 .LVL129: + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1192 .loc 1 352 3 is_stmt 1 view .LVU422 + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1193 .loc 1 352 23 is_stmt 0 view .LVU423 + 1194 002e 0020 movs r0, #0 + 1195 0030 84F84800 strb r0, [r4, #72] + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 1196 .loc 1 355 3 is_stmt 1 view .LVU424 + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 1197 .loc 1 355 3 view .LVU425 + 1198 0034 84F83E00 strb r0, [r4, #62] + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 1199 .loc 1 355 3 view .LVU426 + 1200 0038 84F83F00 strb r0, [r4, #63] + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 1201 .loc 1 355 3 view .LVU427 + 1202 003c 84F84000 strb r0, [r4, #64] + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 1203 .loc 1 355 3 view .LVU428 + 1204 0040 84F84100 strb r0, [r4, #65] + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 1205 .loc 1 355 3 view .LVU429 + 1206 0044 84F84200 strb r0, [r4, #66] + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 1207 .loc 1 355 3 view .LVU430 + 1208 0048 84F84300 strb r0, [r4, #67] + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 1209 .loc 1 355 3 view .LVU431 + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1210 .loc 1 356 3 view .LVU432 + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1211 .loc 1 356 3 view .LVU433 + ARM GAS /tmp/ccGFzgX3.s page 159 + + + 1212 004c 84F84400 strb r0, [r4, #68] + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1213 .loc 1 356 3 view .LVU434 + 1214 0050 84F84500 strb r0, [r4, #69] + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1215 .loc 1 356 3 view .LVU435 + 1216 0054 84F84600 strb r0, [r4, #70] + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1217 .loc 1 356 3 view .LVU436 + 1218 0058 84F84700 strb r0, [r4, #71] + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1219 .loc 1 356 3 view .LVU437 + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1220 .loc 1 359 3 view .LVU438 + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1221 .loc 1 359 15 is_stmt 0 view .LVU439 + 1222 005c 84F83D00 strb r0, [r4, #61] + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1223 .loc 1 362 3 is_stmt 1 view .LVU440 + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1224 .loc 1 362 3 view .LVU441 + 1225 0060 84F83C00 strb r0, [r4, #60] + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1226 .loc 1 362 3 view .LVU442 + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1227 .loc 1 364 3 view .LVU443 + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1228 .loc 1 365 1 is_stmt 0 view .LVU444 + 1229 0064 10BD pop {r4, pc} + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1230 .loc 1 365 1 view .LVU445 + 1231 .cfi_endproc + 1232 .LFE142: + 1234 .section .text.HAL_TIM_Base_Start,"ax",%progbits + 1235 .align 1 + 1236 .global HAL_TIM_Base_Start + 1237 .syntax unified + 1238 .thumb + 1239 .thumb_func + 1241 HAL_TIM_Base_Start: + 1242 .LVL130: + 1243 .LFB145: + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 1244 .loc 1 404 1 is_stmt 1 view -0 + 1245 .cfi_startproc + 1246 @ args = 0, pretend = 0, frame = 0 + 1247 @ frame_needed = 0, uses_anonymous_args = 0 + 1248 @ link register save eliminated. + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1249 .loc 1 405 3 view .LVU447 + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1250 .loc 1 408 3 view .LVU448 + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1251 .loc 1 411 3 view .LVU449 + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1252 .loc 1 411 11 is_stmt 0 view .LVU450 + 1253 0000 90F83D30 ldrb r3, [r0, #61] @ zero_extendqisi2 + ARM GAS /tmp/ccGFzgX3.s page 160 + + + 1254 0004 DBB2 uxtb r3, r3 + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1255 .loc 1 411 6 view .LVU451 + 1256 0006 012B cmp r3, #1 + 1257 0008 35D1 bne .L48 + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1258 .loc 1 417 3 is_stmt 1 view .LVU452 + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1259 .loc 1 417 15 is_stmt 0 view .LVU453 + 1260 000a 0223 movs r3, #2 + 1261 000c 80F83D30 strb r3, [r0, #61] + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1262 .loc 1 420 3 is_stmt 1 view .LVU454 + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1263 .loc 1 420 7 is_stmt 0 view .LVU455 + 1264 0010 0368 ldr r3, [r0] + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1265 .loc 1 420 6 view .LVU456 + 1266 0012 1B4A ldr r2, .L50 + 1267 0014 B3F1804F cmp r3, #1073741824 + 1268 0018 18BF it ne + 1269 001a 9342 cmpne r3, r2 + 1270 001c 1DD0 beq .L46 + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1271 .loc 1 420 7 discriminator 1 view .LVU457 + 1272 001e A2F57C42 sub r2, r2, #64512 + 1273 0022 9342 cmp r3, r2 + 1274 0024 19D0 beq .L46 + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1275 .loc 1 420 7 discriminator 2 view .LVU458 + 1276 0026 02F58062 add r2, r2, #1024 + 1277 002a 9342 cmp r3, r2 + 1278 002c 15D0 beq .L46 + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1279 .loc 1 420 7 discriminator 3 view .LVU459 + 1280 002e 02F58062 add r2, r2, #1024 + 1281 0032 9342 cmp r3, r2 + 1282 0034 11D0 beq .L46 + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1283 .loc 1 420 7 discriminator 4 view .LVU460 + 1284 0036 02F57842 add r2, r2, #63488 + 1285 003a 9342 cmp r3, r2 + 1286 003c 0DD0 beq .L46 + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1287 .loc 1 420 7 discriminator 5 view .LVU461 + 1288 003e 02F57052 add r2, r2, #15360 + 1289 0042 9342 cmp r3, r2 + 1290 0044 09D0 beq .L46 + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1291 .loc 1 420 7 discriminator 6 view .LVU462 + 1292 0046 A2F59432 sub r2, r2, #75776 + 1293 004a 9342 cmp r3, r2 + 1294 004c 05D0 beq .L46 + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1295 .loc 1 430 5 is_stmt 1 view .LVU463 + 1296 004e 1A68 ldr r2, [r3] + 1297 0050 42F00102 orr r2, r2, #1 + ARM GAS /tmp/ccGFzgX3.s page 161 + + + 1298 0054 1A60 str r2, [r3] + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1299 .loc 1 434 10 is_stmt 0 view .LVU464 + 1300 0056 0020 movs r0, #0 + 1301 .LVL131: + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1302 .loc 1 434 10 view .LVU465 + 1303 0058 7047 bx lr + 1304 .LVL132: + 1305 .L46: + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1306 .loc 1 422 5 is_stmt 1 view .LVU466 + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1307 .loc 1 422 29 is_stmt 0 view .LVU467 + 1308 005a 9968 ldr r1, [r3, #8] + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1309 .loc 1 422 13 view .LVU468 + 1310 005c 094A ldr r2, .L50+4 + 1311 005e 0A40 ands r2, r2, r1 + 1312 .LVL133: + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1313 .loc 1 423 5 is_stmt 1 view .LVU469 + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1314 .loc 1 423 8 is_stmt 0 view .LVU470 + 1315 0060 062A cmp r2, #6 + 1316 0062 18BF it ne + 1317 0064 B2F5803F cmpne r2, #65536 + 1318 0068 07D0 beq .L49 + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1319 .loc 1 425 7 is_stmt 1 view .LVU471 + 1320 006a 1A68 ldr r2, [r3] + 1321 .LVL134: + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1322 .loc 1 425 7 is_stmt 0 view .LVU472 + 1323 006c 42F00102 orr r2, r2, #1 + 1324 0070 1A60 str r2, [r3] + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1325 .loc 1 434 10 view .LVU473 + 1326 0072 0020 movs r0, #0 + 1327 .LVL135: + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1328 .loc 1 434 10 view .LVU474 + 1329 0074 7047 bx lr + 1330 .LVL136: + 1331 .L48: + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1332 .loc 1 413 12 view .LVU475 + 1333 0076 0120 movs r0, #1 + 1334 .LVL137: + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1335 .loc 1 413 12 view .LVU476 + 1336 0078 7047 bx lr + 1337 .LVL138: + 1338 .L49: + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1339 .loc 1 434 10 view .LVU477 + 1340 007a 0020 movs r0, #0 + ARM GAS /tmp/ccGFzgX3.s page 162 + + + 1341 .LVL139: + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1342 .loc 1 435 1 view .LVU478 + 1343 007c 7047 bx lr + 1344 .L51: + 1345 007e 00BF .align 2 + 1346 .L50: + 1347 0080 00000140 .word 1073807360 + 1348 0084 07000100 .word 65543 + 1349 .cfi_endproc + 1350 .LFE145: + 1352 .section .text.HAL_TIM_Base_Stop,"ax",%progbits + 1353 .align 1 + 1354 .global HAL_TIM_Base_Stop + 1355 .syntax unified + 1356 .thumb + 1357 .thumb_func + 1359 HAL_TIM_Base_Stop: + 1360 .LVL140: + 1361 .LFB146: + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 1362 .loc 1 443 1 is_stmt 1 view -0 + 1363 .cfi_startproc + 1364 @ args = 0, pretend = 0, frame = 0 + 1365 @ frame_needed = 0, uses_anonymous_args = 0 + 1366 @ link register save eliminated. + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1367 .loc 1 445 3 view .LVU480 + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1368 .loc 1 448 3 view .LVU481 + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1369 .loc 1 448 3 view .LVU482 + 1370 0000 0368 ldr r3, [r0] + 1371 0002 196A ldr r1, [r3, #32] + 1372 0004 41F21112 movw r2, #4369 + 1373 0008 1142 tst r1, r2 + 1374 000a 08D1 bne .L53 + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1375 .loc 1 448 3 discriminator 1 view .LVU483 + 1376 000c 196A ldr r1, [r3, #32] + 1377 000e 40F24442 movw r2, #1092 + 1378 0012 1142 tst r1, r2 + 1379 0014 03D1 bne .L53 + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1380 .loc 1 448 3 discriminator 3 view .LVU484 + 1381 0016 1A68 ldr r2, [r3] + 1382 0018 22F00102 bic r2, r2, #1 + 1383 001c 1A60 str r2, [r3] + 1384 .L53: + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1385 .loc 1 448 3 discriminator 5 view .LVU485 + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1386 .loc 1 451 3 view .LVU486 + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1387 .loc 1 451 15 is_stmt 0 view .LVU487 + 1388 001e 0123 movs r3, #1 + 1389 0020 80F83D30 strb r3, [r0, #61] + ARM GAS /tmp/ccGFzgX3.s page 163 + + + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1390 .loc 1 454 3 is_stmt 1 view .LVU488 + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1391 .loc 1 455 1 is_stmt 0 view .LVU489 + 1392 0024 0020 movs r0, #0 + 1393 .LVL141: + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1394 .loc 1 455 1 view .LVU490 + 1395 0026 7047 bx lr + 1396 .cfi_endproc + 1397 .LFE146: + 1399 .section .text.HAL_TIM_Base_Start_IT,"ax",%progbits + 1400 .align 1 + 1401 .global HAL_TIM_Base_Start_IT + 1402 .syntax unified + 1403 .thumb + 1404 .thumb_func + 1406 HAL_TIM_Base_Start_IT: + 1407 .LVL142: + 1408 .LFB147: + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 1409 .loc 1 463 1 is_stmt 1 view -0 + 1410 .cfi_startproc + 1411 @ args = 0, pretend = 0, frame = 0 + 1412 @ frame_needed = 0, uses_anonymous_args = 0 + 1413 @ link register save eliminated. + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1414 .loc 1 464 3 view .LVU492 + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1415 .loc 1 467 3 view .LVU493 + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1416 .loc 1 470 3 view .LVU494 + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1417 .loc 1 470 11 is_stmt 0 view .LVU495 + 1418 0000 90F83D30 ldrb r3, [r0, #61] @ zero_extendqisi2 + 1419 0004 DBB2 uxtb r3, r3 + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1420 .loc 1 470 6 view .LVU496 + 1421 0006 012B cmp r3, #1 + 1422 0008 3AD1 bne .L58 + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1423 .loc 1 476 3 is_stmt 1 view .LVU497 + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1424 .loc 1 476 15 is_stmt 0 view .LVU498 + 1425 000a 0223 movs r3, #2 + 1426 000c 80F83D30 strb r3, [r0, #61] + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1427 .loc 1 479 3 is_stmt 1 view .LVU499 + 1428 0010 0268 ldr r2, [r0] + 1429 0012 D368 ldr r3, [r2, #12] + 1430 0014 43F00103 orr r3, r3, #1 + 1431 0018 D360 str r3, [r2, #12] + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1432 .loc 1 482 3 view .LVU500 + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1433 .loc 1 482 7 is_stmt 0 view .LVU501 + 1434 001a 0368 ldr r3, [r0] + ARM GAS /tmp/ccGFzgX3.s page 164 + + + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1435 .loc 1 482 6 view .LVU502 + 1436 001c 1A4A ldr r2, .L60 + 1437 001e B3F1804F cmp r3, #1073741824 + 1438 0022 18BF it ne + 1439 0024 9342 cmpne r3, r2 + 1440 0026 1DD0 beq .L56 + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1441 .loc 1 482 7 discriminator 1 view .LVU503 + 1442 0028 A2F57C42 sub r2, r2, #64512 + 1443 002c 9342 cmp r3, r2 + 1444 002e 19D0 beq .L56 + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1445 .loc 1 482 7 discriminator 2 view .LVU504 + 1446 0030 02F58062 add r2, r2, #1024 + 1447 0034 9342 cmp r3, r2 + 1448 0036 15D0 beq .L56 + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1449 .loc 1 482 7 discriminator 3 view .LVU505 + 1450 0038 02F58062 add r2, r2, #1024 + 1451 003c 9342 cmp r3, r2 + 1452 003e 11D0 beq .L56 + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1453 .loc 1 482 7 discriminator 4 view .LVU506 + 1454 0040 02F57842 add r2, r2, #63488 + 1455 0044 9342 cmp r3, r2 + 1456 0046 0DD0 beq .L56 + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1457 .loc 1 482 7 discriminator 5 view .LVU507 + 1458 0048 02F57052 add r2, r2, #15360 + 1459 004c 9342 cmp r3, r2 + 1460 004e 09D0 beq .L56 + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1461 .loc 1 482 7 discriminator 6 view .LVU508 + 1462 0050 A2F59432 sub r2, r2, #75776 + 1463 0054 9342 cmp r3, r2 + 1464 0056 05D0 beq .L56 + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1465 .loc 1 492 5 is_stmt 1 view .LVU509 + 1466 0058 1A68 ldr r2, [r3] + 1467 005a 42F00102 orr r2, r2, #1 + 1468 005e 1A60 str r2, [r3] + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1469 .loc 1 496 10 is_stmt 0 view .LVU510 + 1470 0060 0020 movs r0, #0 + 1471 .LVL143: + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1472 .loc 1 496 10 view .LVU511 + 1473 0062 7047 bx lr + 1474 .LVL144: + 1475 .L56: + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1476 .loc 1 484 5 is_stmt 1 view .LVU512 + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1477 .loc 1 484 29 is_stmt 0 view .LVU513 + 1478 0064 9968 ldr r1, [r3, #8] + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + ARM GAS /tmp/ccGFzgX3.s page 165 + + + 1479 .loc 1 484 13 view .LVU514 + 1480 0066 094A ldr r2, .L60+4 + 1481 0068 0A40 ands r2, r2, r1 + 1482 .LVL145: + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1483 .loc 1 485 5 is_stmt 1 view .LVU515 + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1484 .loc 1 485 8 is_stmt 0 view .LVU516 + 1485 006a 062A cmp r2, #6 + 1486 006c 18BF it ne + 1487 006e B2F5803F cmpne r2, #65536 + 1488 0072 07D0 beq .L59 + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1489 .loc 1 487 7 is_stmt 1 view .LVU517 + 1490 0074 1A68 ldr r2, [r3] + 1491 .LVL146: + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1492 .loc 1 487 7 is_stmt 0 view .LVU518 + 1493 0076 42F00102 orr r2, r2, #1 + 1494 007a 1A60 str r2, [r3] + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1495 .loc 1 496 10 view .LVU519 + 1496 007c 0020 movs r0, #0 + 1497 .LVL147: + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1498 .loc 1 496 10 view .LVU520 + 1499 007e 7047 bx lr + 1500 .LVL148: + 1501 .L58: + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1502 .loc 1 472 12 view .LVU521 + 1503 0080 0120 movs r0, #1 + 1504 .LVL149: + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1505 .loc 1 472 12 view .LVU522 + 1506 0082 7047 bx lr + 1507 .LVL150: + 1508 .L59: + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1509 .loc 1 496 10 view .LVU523 + 1510 0084 0020 movs r0, #0 + 1511 .LVL151: + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1512 .loc 1 497 1 view .LVU524 + 1513 0086 7047 bx lr + 1514 .L61: + 1515 .align 2 + 1516 .L60: + 1517 0088 00000140 .word 1073807360 + 1518 008c 07000100 .word 65543 + 1519 .cfi_endproc + 1520 .LFE147: + 1522 .section .text.HAL_TIM_Base_Stop_IT,"ax",%progbits + 1523 .align 1 + 1524 .global HAL_TIM_Base_Stop_IT + 1525 .syntax unified + 1526 .thumb + ARM GAS /tmp/ccGFzgX3.s page 166 + + + 1527 .thumb_func + 1529 HAL_TIM_Base_Stop_IT: + 1530 .LVL152: + 1531 .LFB148: + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 1532 .loc 1 505 1 is_stmt 1 view -0 + 1533 .cfi_startproc + 1534 @ args = 0, pretend = 0, frame = 0 + 1535 @ frame_needed = 0, uses_anonymous_args = 0 + 1536 @ link register save eliminated. + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1537 .loc 1 507 3 view .LVU526 + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1538 .loc 1 510 3 view .LVU527 + 1539 0000 0268 ldr r2, [r0] + 1540 0002 D368 ldr r3, [r2, #12] + 1541 0004 23F00103 bic r3, r3, #1 + 1542 0008 D360 str r3, [r2, #12] + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1543 .loc 1 513 3 view .LVU528 + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1544 .loc 1 513 3 view .LVU529 + 1545 000a 0368 ldr r3, [r0] + 1546 000c 196A ldr r1, [r3, #32] + 1547 000e 41F21112 movw r2, #4369 + 1548 0012 1142 tst r1, r2 + 1549 0014 08D1 bne .L63 + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1550 .loc 1 513 3 discriminator 1 view .LVU530 + 1551 0016 196A ldr r1, [r3, #32] + 1552 0018 40F24442 movw r2, #1092 + 1553 001c 1142 tst r1, r2 + 1554 001e 03D1 bne .L63 + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1555 .loc 1 513 3 discriminator 3 view .LVU531 + 1556 0020 1A68 ldr r2, [r3] + 1557 0022 22F00102 bic r2, r2, #1 + 1558 0026 1A60 str r2, [r3] + 1559 .L63: + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1560 .loc 1 513 3 discriminator 5 view .LVU532 + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1561 .loc 1 516 3 view .LVU533 + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1562 .loc 1 516 15 is_stmt 0 view .LVU534 + 1563 0028 0123 movs r3, #1 + 1564 002a 80F83D30 strb r3, [r0, #61] + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1565 .loc 1 519 3 is_stmt 1 view .LVU535 + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1566 .loc 1 520 1 is_stmt 0 view .LVU536 + 1567 002e 0020 movs r0, #0 + 1568 .LVL153: + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1569 .loc 1 520 1 view .LVU537 + 1570 0030 7047 bx lr + 1571 .cfi_endproc + ARM GAS /tmp/ccGFzgX3.s page 167 + + + 1572 .LFE148: + 1574 .section .text.HAL_TIM_Base_Start_DMA,"ax",%progbits + 1575 .align 1 + 1576 .global HAL_TIM_Base_Start_DMA + 1577 .syntax unified + 1578 .thumb + 1579 .thumb_func + 1581 HAL_TIM_Base_Start_DMA: + 1582 .LVL154: + 1583 .LFB149: + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 1584 .loc 1 530 1 is_stmt 1 view -0 + 1585 .cfi_startproc + 1586 @ args = 0, pretend = 0, frame = 0 + 1587 @ frame_needed = 0, uses_anonymous_args = 0 + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 1588 .loc 1 530 1 is_stmt 0 view .LVU539 + 1589 0000 38B5 push {r3, r4, r5, lr} + 1590 .LCFI21: + 1591 .cfi_def_cfa_offset 16 + 1592 .cfi_offset 3, -16 + 1593 .cfi_offset 4, -12 + 1594 .cfi_offset 5, -8 + 1595 .cfi_offset 14, -4 + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1596 .loc 1 531 3 is_stmt 1 view .LVU540 + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1597 .loc 1 534 3 view .LVU541 + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1598 .loc 1 537 3 view .LVU542 + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1599 .loc 1 537 11 is_stmt 0 view .LVU543 + 1600 0002 90F83D40 ldrb r4, [r0, #61] @ zero_extendqisi2 + 1601 0006 E4B2 uxtb r4, r4 + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1602 .loc 1 537 6 view .LVU544 + 1603 0008 022C cmp r4, #2 + 1604 000a 58D0 beq .L65 + 1605 000c 0546 mov r5, r0 + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1606 .loc 1 541 8 is_stmt 1 view .LVU545 + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1607 .loc 1 541 16 is_stmt 0 view .LVU546 + 1608 000e 90F83D40 ldrb r4, [r0, #61] @ zero_extendqisi2 + 1609 0012 E4B2 uxtb r4, r4 + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1610 .loc 1 541 11 view .LVU547 + 1611 0014 012C cmp r4, #1 + 1612 0016 51D1 bne .L68 + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1613 .loc 1 543 5 is_stmt 1 view .LVU548 + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1614 .loc 1 543 8 is_stmt 0 view .LVU549 + 1615 0018 002A cmp r2, #0 + 1616 001a 18BF it ne + 1617 001c 0029 cmpne r1, #0 + 1618 001e 4ED0 beq .L65 + ARM GAS /tmp/ccGFzgX3.s page 168 + + + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1619 .loc 1 549 7 is_stmt 1 view .LVU550 + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1620 .loc 1 549 19 is_stmt 0 view .LVU551 + 1621 0020 0223 movs r3, #2 + 1622 0022 80F83D30 strb r3, [r0, #61] + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + 1623 .loc 1 558 3 is_stmt 1 view .LVU552 + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + 1624 .loc 1 558 13 is_stmt 0 view .LVU553 + 1625 0026 036A ldr r3, [r0, #32] + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + 1626 .loc 1 558 51 view .LVU554 + 1627 0028 2748 ldr r0, .L71 + 1628 .LVL155: + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + 1629 .loc 1 558 51 view .LVU555 + 1630 002a D863 str r0, [r3, #60] + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1631 .loc 1 559 3 is_stmt 1 view .LVU556 + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1632 .loc 1 559 13 is_stmt 0 view .LVU557 + 1633 002c 2B6A ldr r3, [r5, #32] + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1634 .loc 1 559 55 view .LVU558 + 1635 002e 2748 ldr r0, .L71+4 + 1636 0030 1864 str r0, [r3, #64] + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1637 .loc 1 562 3 is_stmt 1 view .LVU559 + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1638 .loc 1 562 13 is_stmt 0 view .LVU560 + 1639 0032 2B6A ldr r3, [r5, #32] + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1640 .loc 1 562 52 view .LVU561 + 1641 0034 2648 ldr r0, .L71+8 + 1642 0036 D864 str r0, [r3, #76] + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 1643 .loc 1 565 3 is_stmt 1 view .LVU562 + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 1644 .loc 1 565 87 is_stmt 0 view .LVU563 + 1645 0038 2868 ldr r0, [r5] + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 1646 .loc 1 565 7 view .LVU564 + 1647 003a 1346 mov r3, r2 + 1648 003c 00F12C02 add r2, r0, #44 + 1649 .LVL156: + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 1650 .loc 1 565 7 view .LVU565 + 1651 0040 286A ldr r0, [r5, #32] + 1652 0042 FFF7FEFF bl HAL_DMA_Start_IT + 1653 .LVL157: + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 1654 .loc 1 565 6 discriminator 1 view .LVU566 + 1655 0046 0146 mov r1, r0 + 1656 0048 0028 cmp r0, #0 + 1657 004a 38D1 bne .L65 + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 169 + + + 1658 .loc 1 573 3 is_stmt 1 view .LVU567 + 1659 004c 2A68 ldr r2, [r5] + 1660 004e D368 ldr r3, [r2, #12] + 1661 0050 43F48073 orr r3, r3, #256 + 1662 0054 D360 str r3, [r2, #12] + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1663 .loc 1 576 3 view .LVU568 + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1664 .loc 1 576 7 is_stmt 0 view .LVU569 + 1665 0056 2B68 ldr r3, [r5] + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1666 .loc 1 576 6 view .LVU570 + 1667 0058 1E4A ldr r2, .L71+12 + 1668 005a B3F1804F cmp r3, #1073741824 + 1669 005e 18BF it ne + 1670 0060 9342 cmpne r3, r2 + 1671 0062 1DD0 beq .L66 + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1672 .loc 1 576 7 discriminator 1 view .LVU571 + 1673 0064 A2F57C42 sub r2, r2, #64512 + 1674 0068 9342 cmp r3, r2 + 1675 006a 19D0 beq .L66 + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1676 .loc 1 576 7 discriminator 2 view .LVU572 + 1677 006c 02F58062 add r2, r2, #1024 + 1678 0070 9342 cmp r3, r2 + 1679 0072 15D0 beq .L66 + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1680 .loc 1 576 7 discriminator 3 view .LVU573 + 1681 0074 02F58062 add r2, r2, #1024 + 1682 0078 9342 cmp r3, r2 + 1683 007a 11D0 beq .L66 + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1684 .loc 1 576 7 discriminator 4 view .LVU574 + 1685 007c 02F57842 add r2, r2, #63488 + 1686 0080 9342 cmp r3, r2 + 1687 0082 0DD0 beq .L66 + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1688 .loc 1 576 7 discriminator 5 view .LVU575 + 1689 0084 02F57052 add r2, r2, #15360 + 1690 0088 9342 cmp r3, r2 + 1691 008a 09D0 beq .L66 + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1692 .loc 1 576 7 discriminator 6 view .LVU576 + 1693 008c A2F59432 sub r2, r2, #75776 + 1694 0090 9342 cmp r3, r2 + 1695 0092 05D0 beq .L66 + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1696 .loc 1 586 5 is_stmt 1 view .LVU577 + 1697 0094 1A68 ldr r2, [r3] + 1698 0096 42F00102 orr r2, r2, #1 + 1699 009a 1A60 str r2, [r3] + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1700 .loc 1 590 10 is_stmt 0 view .LVU578 + 1701 009c 0446 mov r4, r0 + 1702 009e 0EE0 b .L65 + 1703 .L66: + ARM GAS /tmp/ccGFzgX3.s page 170 + + + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1704 .loc 1 578 5 is_stmt 1 view .LVU579 + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1705 .loc 1 578 29 is_stmt 0 view .LVU580 + 1706 00a0 9868 ldr r0, [r3, #8] + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1707 .loc 1 578 13 view .LVU581 + 1708 00a2 0D4A ldr r2, .L71+16 + 1709 00a4 0240 ands r2, r2, r0 + 1710 .LVL158: + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1711 .loc 1 579 5 is_stmt 1 view .LVU582 + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 1712 .loc 1 579 8 is_stmt 0 view .LVU583 + 1713 00a6 062A cmp r2, #6 + 1714 00a8 18BF it ne + 1715 00aa B2F5803F cmpne r2, #65536 + 1716 00ae 08D0 beq .L69 + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1717 .loc 1 581 7 is_stmt 1 view .LVU584 + 1718 00b0 1A68 ldr r2, [r3] + 1719 .LVL159: + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1720 .loc 1 581 7 is_stmt 0 view .LVU585 + 1721 00b2 42F00102 orr r2, r2, #1 + 1722 00b6 1A60 str r2, [r3] + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1723 .loc 1 590 10 view .LVU586 + 1724 00b8 0C46 mov r4, r1 + 1725 00ba 00E0 b .L65 + 1726 .LVL160: + 1727 .L68: + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1728 .loc 1 554 12 view .LVU587 + 1729 00bc 0124 movs r4, #1 + 1730 .LVL161: + 1731 .L65: + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1732 .loc 1 591 1 view .LVU588 + 1733 00be 2046 mov r0, r4 + 1734 00c0 38BD pop {r3, r4, r5, pc} + 1735 .LVL162: + 1736 .L69: + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1737 .loc 1 590 10 view .LVU589 + 1738 00c2 0C46 mov r4, r1 + 1739 00c4 FBE7 b .L65 + 1740 .L72: + 1741 00c6 00BF .align 2 + 1742 .L71: + 1743 00c8 00000000 .word TIM_DMAPeriodElapsedCplt + 1744 00cc 00000000 .word TIM_DMAPeriodElapsedHalfCplt + 1745 00d0 00000000 .word TIM_DMAError + 1746 00d4 00000140 .word 1073807360 + 1747 00d8 07000100 .word 65543 + 1748 .cfi_endproc + 1749 .LFE149: + ARM GAS /tmp/ccGFzgX3.s page 171 + + + 1751 .section .text.HAL_TIM_Base_Stop_DMA,"ax",%progbits + 1752 .align 1 + 1753 .global HAL_TIM_Base_Stop_DMA + 1754 .syntax unified + 1755 .thumb + 1756 .thumb_func + 1758 HAL_TIM_Base_Stop_DMA: + 1759 .LVL163: + 1760 .LFB150: + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 1761 .loc 1 599 1 is_stmt 1 view -0 + 1762 .cfi_startproc + 1763 @ args = 0, pretend = 0, frame = 0 + 1764 @ frame_needed = 0, uses_anonymous_args = 0 + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 1765 .loc 1 599 1 is_stmt 0 view .LVU591 + 1766 0000 10B5 push {r4, lr} + 1767 .LCFI22: + 1768 .cfi_def_cfa_offset 8 + 1769 .cfi_offset 4, -8 + 1770 .cfi_offset 14, -4 + 1771 0002 0446 mov r4, r0 + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1772 .loc 1 601 3 is_stmt 1 view .LVU592 + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1773 .loc 1 604 3 view .LVU593 + 1774 0004 0268 ldr r2, [r0] + 1775 0006 D368 ldr r3, [r2, #12] + 1776 0008 23F48073 bic r3, r3, #256 + 1777 000c D360 str r3, [r2, #12] + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1778 .loc 1 606 3 view .LVU594 + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1779 .loc 1 606 9 is_stmt 0 view .LVU595 + 1780 000e 006A ldr r0, [r0, #32] + 1781 .LVL164: + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1782 .loc 1 606 9 view .LVU596 + 1783 0010 FFF7FEFF bl HAL_DMA_Abort_IT + 1784 .LVL165: + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1785 .loc 1 609 3 is_stmt 1 view .LVU597 + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1786 .loc 1 609 3 view .LVU598 + 1787 0014 2368 ldr r3, [r4] + 1788 0016 196A ldr r1, [r3, #32] + 1789 0018 41F21112 movw r2, #4369 + 1790 001c 1142 tst r1, r2 + 1791 001e 08D1 bne .L74 + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1792 .loc 1 609 3 discriminator 1 view .LVU599 + 1793 0020 196A ldr r1, [r3, #32] + 1794 0022 40F24442 movw r2, #1092 + 1795 0026 1142 tst r1, r2 + 1796 0028 03D1 bne .L74 + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1797 .loc 1 609 3 discriminator 3 view .LVU600 + ARM GAS /tmp/ccGFzgX3.s page 172 + + + 1798 002a 1A68 ldr r2, [r3] + 1799 002c 22F00102 bic r2, r2, #1 + 1800 0030 1A60 str r2, [r3] + 1801 .L74: + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1802 .loc 1 609 3 discriminator 5 view .LVU601 + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1803 .loc 1 612 3 view .LVU602 + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1804 .loc 1 612 15 is_stmt 0 view .LVU603 + 1805 0032 0123 movs r3, #1 + 1806 0034 84F83D30 strb r3, [r4, #61] + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1807 .loc 1 615 3 is_stmt 1 view .LVU604 + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1808 .loc 1 616 1 is_stmt 0 view .LVU605 + 1809 0038 0020 movs r0, #0 + 1810 003a 10BD pop {r4, pc} + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1811 .loc 1 616 1 view .LVU606 + 1812 .cfi_endproc + 1813 .LFE150: + 1815 .section .text.HAL_TIM_OC_MspInit,"ax",%progbits + 1816 .align 1 + 1817 .weak HAL_TIM_OC_MspInit + 1818 .syntax unified + 1819 .thumb + 1820 .thumb_func + 1822 HAL_TIM_OC_MspInit: + 1823 .LVL166: + 1824 .LFB153: + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 1825 .loc 1 757 1 is_stmt 1 view -0 + 1826 .cfi_startproc + 1827 @ args = 0, pretend = 0, frame = 0 + 1828 @ frame_needed = 0, uses_anonymous_args = 0 + 1829 @ link register save eliminated. + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1830 .loc 1 759 3 view .LVU608 + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1831 .loc 1 764 1 is_stmt 0 view .LVU609 + 1832 0000 7047 bx lr + 1833 .cfi_endproc + 1834 .LFE153: + 1836 .section .text.HAL_TIM_OC_MspDeInit,"ax",%progbits + 1837 .align 1 + 1838 .weak HAL_TIM_OC_MspDeInit + 1839 .syntax unified + 1840 .thumb + 1841 .thumb_func + 1843 HAL_TIM_OC_MspDeInit: + 1844 .LVL167: + 1845 .LFB154: + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 1846 .loc 1 772 1 is_stmt 1 view -0 + 1847 .cfi_startproc + 1848 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccGFzgX3.s page 173 + + + 1849 @ frame_needed = 0, uses_anonymous_args = 0 + 1850 @ link register save eliminated. + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1851 .loc 1 774 3 view .LVU611 + 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1852 .loc 1 779 1 is_stmt 0 view .LVU612 + 1853 0000 7047 bx lr + 1854 .cfi_endproc + 1855 .LFE154: + 1857 .section .text.HAL_TIM_OC_DeInit,"ax",%progbits + 1858 .align 1 + 1859 .global HAL_TIM_OC_DeInit + 1860 .syntax unified + 1861 .thumb + 1862 .thumb_func + 1864 HAL_TIM_OC_DeInit: + 1865 .LVL168: + 1866 .LFB152: + 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 1867 .loc 1 714 1 is_stmt 1 view -0 + 1868 .cfi_startproc + 1869 @ args = 0, pretend = 0, frame = 0 + 1870 @ frame_needed = 0, uses_anonymous_args = 0 + 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 1871 .loc 1 714 1 is_stmt 0 view .LVU614 + 1872 0000 10B5 push {r4, lr} + 1873 .LCFI23: + 1874 .cfi_def_cfa_offset 8 + 1875 .cfi_offset 4, -8 + 1876 .cfi_offset 14, -4 + 1877 0002 0446 mov r4, r0 + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1878 .loc 1 716 3 is_stmt 1 view .LVU615 + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1879 .loc 1 718 3 view .LVU616 + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1880 .loc 1 718 15 is_stmt 0 view .LVU617 + 1881 0004 0223 movs r3, #2 + 1882 0006 80F83D30 strb r3, [r0, #61] + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1883 .loc 1 721 3 is_stmt 1 view .LVU618 + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1884 .loc 1 721 3 view .LVU619 + 1885 000a 0368 ldr r3, [r0] + 1886 000c 196A ldr r1, [r3, #32] + 1887 000e 41F21112 movw r2, #4369 + 1888 0012 1142 tst r1, r2 + 1889 0014 08D1 bne .L79 + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1890 .loc 1 721 3 discriminator 1 view .LVU620 + 1891 0016 196A ldr r1, [r3, #32] + 1892 0018 40F24442 movw r2, #1092 + 1893 001c 1142 tst r1, r2 + 1894 001e 03D1 bne .L79 + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1895 .loc 1 721 3 discriminator 3 view .LVU621 + 1896 0020 1A68 ldr r2, [r3] + ARM GAS /tmp/ccGFzgX3.s page 174 + + + 1897 0022 22F00102 bic r2, r2, #1 + 1898 0026 1A60 str r2, [r3] + 1899 .L79: + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1900 .loc 1 721 3 discriminator 5 view .LVU622 + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 1901 .loc 1 732 3 view .LVU623 + 1902 0028 2046 mov r0, r4 + 1903 .LVL169: + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 1904 .loc 1 732 3 is_stmt 0 view .LVU624 + 1905 002a FFF7FEFF bl HAL_TIM_OC_MspDeInit + 1906 .LVL170: + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1907 .loc 1 736 3 is_stmt 1 view .LVU625 + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1908 .loc 1 736 23 is_stmt 0 view .LVU626 + 1909 002e 0020 movs r0, #0 + 1910 0030 84F84800 strb r0, [r4, #72] + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 1911 .loc 1 739 3 is_stmt 1 view .LVU627 + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 1912 .loc 1 739 3 view .LVU628 + 1913 0034 84F83E00 strb r0, [r4, #62] + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 1914 .loc 1 739 3 view .LVU629 + 1915 0038 84F83F00 strb r0, [r4, #63] + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 1916 .loc 1 739 3 view .LVU630 + 1917 003c 84F84000 strb r0, [r4, #64] + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 1918 .loc 1 739 3 view .LVU631 + 1919 0040 84F84100 strb r0, [r4, #65] + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 1920 .loc 1 739 3 view .LVU632 + 1921 0044 84F84200 strb r0, [r4, #66] + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 1922 .loc 1 739 3 view .LVU633 + 1923 0048 84F84300 strb r0, [r4, #67] + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 1924 .loc 1 739 3 view .LVU634 + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1925 .loc 1 740 3 view .LVU635 + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1926 .loc 1 740 3 view .LVU636 + 1927 004c 84F84400 strb r0, [r4, #68] + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1928 .loc 1 740 3 view .LVU637 + 1929 0050 84F84500 strb r0, [r4, #69] + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1930 .loc 1 740 3 view .LVU638 + 1931 0054 84F84600 strb r0, [r4, #70] + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1932 .loc 1 740 3 view .LVU639 + 1933 0058 84F84700 strb r0, [r4, #71] + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1934 .loc 1 740 3 view .LVU640 + ARM GAS /tmp/ccGFzgX3.s page 175 + + + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1935 .loc 1 743 3 view .LVU641 + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1936 .loc 1 743 15 is_stmt 0 view .LVU642 + 1937 005c 84F83D00 strb r0, [r4, #61] + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1938 .loc 1 746 3 is_stmt 1 view .LVU643 + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1939 .loc 1 746 3 view .LVU644 + 1940 0060 84F83C00 strb r0, [r4, #60] + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1941 .loc 1 746 3 view .LVU645 + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 1942 .loc 1 748 3 view .LVU646 + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1943 .loc 1 749 1 is_stmt 0 view .LVU647 + 1944 0064 10BD pop {r4, pc} + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1945 .loc 1 749 1 view .LVU648 + 1946 .cfi_endproc + 1947 .LFE152: + 1949 .section .text.HAL_TIM_PWM_MspInit,"ax",%progbits + 1950 .align 1 + 1951 .weak HAL_TIM_PWM_MspInit + 1952 .syntax unified + 1953 .thumb + 1954 .thumb_func + 1956 HAL_TIM_PWM_MspInit: + 1957 .LVL171: + 1958 .LFB163: +1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 1959 .loc 1 1426 1 is_stmt 1 view -0 + 1960 .cfi_startproc + 1961 @ args = 0, pretend = 0, frame = 0 + 1962 @ frame_needed = 0, uses_anonymous_args = 0 + 1963 @ link register save eliminated. +1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1964 .loc 1 1428 3 view .LVU650 +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1965 .loc 1 1433 1 is_stmt 0 view .LVU651 + 1966 0000 7047 bx lr + 1967 .cfi_endproc + 1968 .LFE163: + 1970 .section .text.HAL_TIM_PWM_MspDeInit,"ax",%progbits + 1971 .align 1 + 1972 .weak HAL_TIM_PWM_MspDeInit + 1973 .syntax unified + 1974 .thumb + 1975 .thumb_func + 1977 HAL_TIM_PWM_MspDeInit: + 1978 .LVL172: + 1979 .LFB164: +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 1980 .loc 1 1441 1 is_stmt 1 view -0 + 1981 .cfi_startproc + 1982 @ args = 0, pretend = 0, frame = 0 + 1983 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccGFzgX3.s page 176 + + + 1984 @ link register save eliminated. +1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1985 .loc 1 1443 3 view .LVU653 +1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 1986 .loc 1 1448 1 is_stmt 0 view .LVU654 + 1987 0000 7047 bx lr + 1988 .cfi_endproc + 1989 .LFE164: + 1991 .section .text.HAL_TIM_PWM_DeInit,"ax",%progbits + 1992 .align 1 + 1993 .global HAL_TIM_PWM_DeInit + 1994 .syntax unified + 1995 .thumb + 1996 .thumb_func + 1998 HAL_TIM_PWM_DeInit: + 1999 .LVL173: + 2000 .LFB162: +1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 2001 .loc 1 1383 1 is_stmt 1 view -0 + 2002 .cfi_startproc + 2003 @ args = 0, pretend = 0, frame = 0 + 2004 @ frame_needed = 0, uses_anonymous_args = 0 +1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 2005 .loc 1 1383 1 is_stmt 0 view .LVU656 + 2006 0000 10B5 push {r4, lr} + 2007 .LCFI24: + 2008 .cfi_def_cfa_offset 8 + 2009 .cfi_offset 4, -8 + 2010 .cfi_offset 14, -4 + 2011 0002 0446 mov r4, r0 +1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2012 .loc 1 1385 3 is_stmt 1 view .LVU657 +1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2013 .loc 1 1387 3 view .LVU658 +1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2014 .loc 1 1387 15 is_stmt 0 view .LVU659 + 2015 0004 0223 movs r3, #2 + 2016 0006 80F83D30 strb r3, [r0, #61] +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2017 .loc 1 1390 3 is_stmt 1 view .LVU660 +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2018 .loc 1 1390 3 view .LVU661 + 2019 000a 0368 ldr r3, [r0] + 2020 000c 196A ldr r1, [r3, #32] + 2021 000e 41F21112 movw r2, #4369 + 2022 0012 1142 tst r1, r2 + 2023 0014 08D1 bne .L84 +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2024 .loc 1 1390 3 discriminator 1 view .LVU662 + 2025 0016 196A ldr r1, [r3, #32] + 2026 0018 40F24442 movw r2, #1092 + 2027 001c 1142 tst r1, r2 + 2028 001e 03D1 bne .L84 +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2029 .loc 1 1390 3 discriminator 3 view .LVU663 + 2030 0020 1A68 ldr r2, [r3] + 2031 0022 22F00102 bic r2, r2, #1 + ARM GAS /tmp/ccGFzgX3.s page 177 + + + 2032 0026 1A60 str r2, [r3] + 2033 .L84: +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2034 .loc 1 1390 3 discriminator 5 view .LVU664 +1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 2035 .loc 1 1401 3 view .LVU665 + 2036 0028 2046 mov r0, r4 + 2037 .LVL174: +1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 2038 .loc 1 1401 3 is_stmt 0 view .LVU666 + 2039 002a FFF7FEFF bl HAL_TIM_PWM_MspDeInit + 2040 .LVL175: +1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2041 .loc 1 1405 3 is_stmt 1 view .LVU667 +1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2042 .loc 1 1405 23 is_stmt 0 view .LVU668 + 2043 002e 0020 movs r0, #0 + 2044 0030 84F84800 strb r0, [r4, #72] +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 2045 .loc 1 1408 3 is_stmt 1 view .LVU669 +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 2046 .loc 1 1408 3 view .LVU670 + 2047 0034 84F83E00 strb r0, [r4, #62] +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 2048 .loc 1 1408 3 view .LVU671 + 2049 0038 84F83F00 strb r0, [r4, #63] +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 2050 .loc 1 1408 3 view .LVU672 + 2051 003c 84F84000 strb r0, [r4, #64] +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 2052 .loc 1 1408 3 view .LVU673 + 2053 0040 84F84100 strb r0, [r4, #65] +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 2054 .loc 1 1408 3 view .LVU674 + 2055 0044 84F84200 strb r0, [r4, #66] +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 2056 .loc 1 1408 3 view .LVU675 + 2057 0048 84F84300 strb r0, [r4, #67] +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 2058 .loc 1 1408 3 view .LVU676 +1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2059 .loc 1 1409 3 view .LVU677 +1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2060 .loc 1 1409 3 view .LVU678 + 2061 004c 84F84400 strb r0, [r4, #68] +1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2062 .loc 1 1409 3 view .LVU679 + 2063 0050 84F84500 strb r0, [r4, #69] +1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2064 .loc 1 1409 3 view .LVU680 + 2065 0054 84F84600 strb r0, [r4, #70] +1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2066 .loc 1 1409 3 view .LVU681 + 2067 0058 84F84700 strb r0, [r4, #71] +1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2068 .loc 1 1409 3 view .LVU682 +1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 178 + + + 2069 .loc 1 1412 3 view .LVU683 +1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2070 .loc 1 1412 15 is_stmt 0 view .LVU684 + 2071 005c 84F83D00 strb r0, [r4, #61] +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2072 .loc 1 1415 3 is_stmt 1 view .LVU685 +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2073 .loc 1 1415 3 view .LVU686 + 2074 0060 84F83C00 strb r0, [r4, #60] +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2075 .loc 1 1415 3 view .LVU687 +1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2076 .loc 1 1417 3 view .LVU688 +1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2077 .loc 1 1418 1 is_stmt 0 view .LVU689 + 2078 0064 10BD pop {r4, pc} +1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2079 .loc 1 1418 1 view .LVU690 + 2080 .cfi_endproc + 2081 .LFE162: + 2083 .section .text.HAL_TIM_IC_MspInit,"ax",%progbits + 2084 .align 1 + 2085 .weak HAL_TIM_IC_MspInit + 2086 .syntax unified + 2087 .thumb + 2088 .thumb_func + 2090 HAL_TIM_IC_MspInit: + 2091 .LVL176: + 2092 .LFB173: +2094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 2093 .loc 1 2094 1 is_stmt 1 view -0 + 2094 .cfi_startproc + 2095 @ args = 0, pretend = 0, frame = 0 + 2096 @ frame_needed = 0, uses_anonymous_args = 0 + 2097 @ link register save eliminated. +2096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2098 .loc 1 2096 3 view .LVU692 +2101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2099 .loc 1 2101 1 is_stmt 0 view .LVU693 + 2100 0000 7047 bx lr + 2101 .cfi_endproc + 2102 .LFE173: + 2104 .section .text.HAL_TIM_IC_MspDeInit,"ax",%progbits + 2105 .align 1 + 2106 .weak HAL_TIM_IC_MspDeInit + 2107 .syntax unified + 2108 .thumb + 2109 .thumb_func + 2111 HAL_TIM_IC_MspDeInit: + 2112 .LVL177: + 2113 .LFB174: +2109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 2114 .loc 1 2109 1 is_stmt 1 view -0 + 2115 .cfi_startproc + 2116 @ args = 0, pretend = 0, frame = 0 + 2117 @ frame_needed = 0, uses_anonymous_args = 0 + 2118 @ link register save eliminated. + ARM GAS /tmp/ccGFzgX3.s page 179 + + +2111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2119 .loc 1 2111 3 view .LVU695 +2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2120 .loc 1 2116 1 is_stmt 0 view .LVU696 + 2121 0000 7047 bx lr + 2122 .cfi_endproc + 2123 .LFE174: + 2125 .section .text.HAL_TIM_IC_DeInit,"ax",%progbits + 2126 .align 1 + 2127 .global HAL_TIM_IC_DeInit + 2128 .syntax unified + 2129 .thumb + 2130 .thumb_func + 2132 HAL_TIM_IC_DeInit: + 2133 .LVL178: + 2134 .LFB172: +2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 2135 .loc 1 2051 1 is_stmt 1 view -0 + 2136 .cfi_startproc + 2137 @ args = 0, pretend = 0, frame = 0 + 2138 @ frame_needed = 0, uses_anonymous_args = 0 +2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 2139 .loc 1 2051 1 is_stmt 0 view .LVU698 + 2140 0000 10B5 push {r4, lr} + 2141 .LCFI25: + 2142 .cfi_def_cfa_offset 8 + 2143 .cfi_offset 4, -8 + 2144 .cfi_offset 14, -4 + 2145 0002 0446 mov r4, r0 +2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2146 .loc 1 2053 3 is_stmt 1 view .LVU699 +2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2147 .loc 1 2055 3 view .LVU700 +2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2148 .loc 1 2055 15 is_stmt 0 view .LVU701 + 2149 0004 0223 movs r3, #2 + 2150 0006 80F83D30 strb r3, [r0, #61] +2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2151 .loc 1 2058 3 is_stmt 1 view .LVU702 +2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2152 .loc 1 2058 3 view .LVU703 + 2153 000a 0368 ldr r3, [r0] + 2154 000c 196A ldr r1, [r3, #32] + 2155 000e 41F21112 movw r2, #4369 + 2156 0012 1142 tst r1, r2 + 2157 0014 08D1 bne .L89 +2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2158 .loc 1 2058 3 discriminator 1 view .LVU704 + 2159 0016 196A ldr r1, [r3, #32] + 2160 0018 40F24442 movw r2, #1092 + 2161 001c 1142 tst r1, r2 + 2162 001e 03D1 bne .L89 +2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2163 .loc 1 2058 3 discriminator 3 view .LVU705 + 2164 0020 1A68 ldr r2, [r3] + 2165 0022 22F00102 bic r2, r2, #1 + 2166 0026 1A60 str r2, [r3] + ARM GAS /tmp/ccGFzgX3.s page 180 + + + 2167 .L89: +2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2168 .loc 1 2058 3 discriminator 5 view .LVU706 +2069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 2169 .loc 1 2069 3 view .LVU707 + 2170 0028 2046 mov r0, r4 + 2171 .LVL179: +2069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 2172 .loc 1 2069 3 is_stmt 0 view .LVU708 + 2173 002a FFF7FEFF bl HAL_TIM_IC_MspDeInit + 2174 .LVL180: +2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2175 .loc 1 2073 3 is_stmt 1 view .LVU709 +2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2176 .loc 1 2073 23 is_stmt 0 view .LVU710 + 2177 002e 0020 movs r0, #0 + 2178 0030 84F84800 strb r0, [r4, #72] +2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 2179 .loc 1 2076 3 is_stmt 1 view .LVU711 +2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 2180 .loc 1 2076 3 view .LVU712 + 2181 0034 84F83E00 strb r0, [r4, #62] +2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 2182 .loc 1 2076 3 view .LVU713 + 2183 0038 84F83F00 strb r0, [r4, #63] +2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 2184 .loc 1 2076 3 view .LVU714 + 2185 003c 84F84000 strb r0, [r4, #64] +2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 2186 .loc 1 2076 3 view .LVU715 + 2187 0040 84F84100 strb r0, [r4, #65] +2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 2188 .loc 1 2076 3 view .LVU716 + 2189 0044 84F84200 strb r0, [r4, #66] +2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 2190 .loc 1 2076 3 view .LVU717 + 2191 0048 84F84300 strb r0, [r4, #67] +2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 2192 .loc 1 2076 3 view .LVU718 +2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2193 .loc 1 2077 3 view .LVU719 +2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2194 .loc 1 2077 3 view .LVU720 + 2195 004c 84F84400 strb r0, [r4, #68] +2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2196 .loc 1 2077 3 view .LVU721 + 2197 0050 84F84500 strb r0, [r4, #69] +2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2198 .loc 1 2077 3 view .LVU722 + 2199 0054 84F84600 strb r0, [r4, #70] +2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2200 .loc 1 2077 3 view .LVU723 + 2201 0058 84F84700 strb r0, [r4, #71] +2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2202 .loc 1 2077 3 view .LVU724 +2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2203 .loc 1 2080 3 view .LVU725 + ARM GAS /tmp/ccGFzgX3.s page 181 + + +2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2204 .loc 1 2080 15 is_stmt 0 view .LVU726 + 2205 005c 84F83D00 strb r0, [r4, #61] +2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2206 .loc 1 2083 3 is_stmt 1 view .LVU727 +2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2207 .loc 1 2083 3 view .LVU728 + 2208 0060 84F83C00 strb r0, [r4, #60] +2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2209 .loc 1 2083 3 view .LVU729 +2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2210 .loc 1 2085 3 view .LVU730 +2086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2211 .loc 1 2086 1 is_stmt 0 view .LVU731 + 2212 0064 10BD pop {r4, pc} +2086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2213 .loc 1 2086 1 view .LVU732 + 2214 .cfi_endproc + 2215 .LFE172: + 2217 .section .text.HAL_TIM_OnePulse_MspInit,"ax",%progbits + 2218 .align 1 + 2219 .weak HAL_TIM_OnePulse_MspInit + 2220 .syntax unified + 2221 .thumb + 2222 .thumb_func + 2224 HAL_TIM_OnePulse_MspInit: + 2225 .LVL181: + 2226 .LFB183: +2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 2227 .loc 1 2754 1 is_stmt 1 view -0 + 2228 .cfi_startproc + 2229 @ args = 0, pretend = 0, frame = 0 + 2230 @ frame_needed = 0, uses_anonymous_args = 0 + 2231 @ link register save eliminated. +2756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2232 .loc 1 2756 3 view .LVU734 +2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2233 .loc 1 2761 1 is_stmt 0 view .LVU735 + 2234 0000 7047 bx lr + 2235 .cfi_endproc + 2236 .LFE183: + 2238 .section .text.HAL_TIM_OnePulse_MspDeInit,"ax",%progbits + 2239 .align 1 + 2240 .weak HAL_TIM_OnePulse_MspDeInit + 2241 .syntax unified + 2242 .thumb + 2243 .thumb_func + 2245 HAL_TIM_OnePulse_MspDeInit: + 2246 .LVL182: + 2247 .LFB184: +2769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 2248 .loc 1 2769 1 is_stmt 1 view -0 + 2249 .cfi_startproc + 2250 @ args = 0, pretend = 0, frame = 0 + 2251 @ frame_needed = 0, uses_anonymous_args = 0 + 2252 @ link register save eliminated. +2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 182 + + + 2253 .loc 1 2771 3 view .LVU737 +2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2254 .loc 1 2776 1 is_stmt 0 view .LVU738 + 2255 0000 7047 bx lr + 2256 .cfi_endproc + 2257 .LFE184: + 2259 .section .text.HAL_TIM_OnePulse_DeInit,"ax",%progbits + 2260 .align 1 + 2261 .global HAL_TIM_OnePulse_DeInit + 2262 .syntax unified + 2263 .thumb + 2264 .thumb_func + 2266 HAL_TIM_OnePulse_DeInit: + 2267 .LVL183: + 2268 .LFB182: +2709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 2269 .loc 1 2709 1 is_stmt 1 view -0 + 2270 .cfi_startproc + 2271 @ args = 0, pretend = 0, frame = 0 + 2272 @ frame_needed = 0, uses_anonymous_args = 0 +2709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 2273 .loc 1 2709 1 is_stmt 0 view .LVU740 + 2274 0000 10B5 push {r4, lr} + 2275 .LCFI26: + 2276 .cfi_def_cfa_offset 8 + 2277 .cfi_offset 4, -8 + 2278 .cfi_offset 14, -4 + 2279 0002 0446 mov r4, r0 +2711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2280 .loc 1 2711 3 is_stmt 1 view .LVU741 +2713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2281 .loc 1 2713 3 view .LVU742 +2713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2282 .loc 1 2713 15 is_stmt 0 view .LVU743 + 2283 0004 0223 movs r3, #2 + 2284 0006 80F83D30 strb r3, [r0, #61] +2716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2285 .loc 1 2716 3 is_stmt 1 view .LVU744 +2716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2286 .loc 1 2716 3 view .LVU745 + 2287 000a 0368 ldr r3, [r0] + 2288 000c 196A ldr r1, [r3, #32] + 2289 000e 41F21112 movw r2, #4369 + 2290 0012 1142 tst r1, r2 + 2291 0014 08D1 bne .L94 +2716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2292 .loc 1 2716 3 discriminator 1 view .LVU746 + 2293 0016 196A ldr r1, [r3, #32] + 2294 0018 40F24442 movw r2, #1092 + 2295 001c 1142 tst r1, r2 + 2296 001e 03D1 bne .L94 +2716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2297 .loc 1 2716 3 discriminator 3 view .LVU747 + 2298 0020 1A68 ldr r2, [r3] + 2299 0022 22F00102 bic r2, r2, #1 + 2300 0026 1A60 str r2, [r3] + 2301 .L94: + ARM GAS /tmp/ccGFzgX3.s page 183 + + +2716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2302 .loc 1 2716 3 discriminator 5 view .LVU748 +2727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 2303 .loc 1 2727 3 view .LVU749 + 2304 0028 2046 mov r0, r4 + 2305 .LVL184: +2727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 2306 .loc 1 2727 3 is_stmt 0 view .LVU750 + 2307 002a FFF7FEFF bl HAL_TIM_OnePulse_MspDeInit + 2308 .LVL185: +2731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2309 .loc 1 2731 3 is_stmt 1 view .LVU751 +2731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2310 .loc 1 2731 23 is_stmt 0 view .LVU752 + 2311 002e 0020 movs r0, #0 + 2312 0030 84F84800 strb r0, [r4, #72] +2734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + 2313 .loc 1 2734 3 is_stmt 1 view .LVU753 + 2314 0034 84F83E00 strb r0, [r4, #62] +2735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + 2315 .loc 1 2735 3 view .LVU754 + 2316 0038 84F83F00 strb r0, [r4, #63] +2736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + 2317 .loc 1 2736 3 view .LVU755 + 2318 003c 84F84400 strb r0, [r4, #68] +2737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2319 .loc 1 2737 3 view .LVU756 + 2320 0040 84F84500 strb r0, [r4, #69] +2740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2321 .loc 1 2740 3 view .LVU757 +2740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2322 .loc 1 2740 15 is_stmt 0 view .LVU758 + 2323 0044 84F83D00 strb r0, [r4, #61] +2743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2324 .loc 1 2743 3 is_stmt 1 view .LVU759 +2743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2325 .loc 1 2743 3 view .LVU760 + 2326 0048 84F83C00 strb r0, [r4, #60] +2743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2327 .loc 1 2743 3 view .LVU761 +2745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2328 .loc 1 2745 3 view .LVU762 +2746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2329 .loc 1 2746 1 is_stmt 0 view .LVU763 + 2330 004c 10BD pop {r4, pc} +2746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2331 .loc 1 2746 1 view .LVU764 + 2332 .cfi_endproc + 2333 .LFE182: + 2335 .section .text.HAL_TIM_Encoder_MspInit,"ax",%progbits + 2336 .align 1 + 2337 .weak HAL_TIM_Encoder_MspInit + 2338 .syntax unified + 2339 .thumb + 2340 .thumb_func + 2342 HAL_TIM_Encoder_MspInit: + 2343 .LVL186: + ARM GAS /tmp/ccGFzgX3.s page 184 + + + 2344 .LFB191: +3191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 2345 .loc 1 3191 1 is_stmt 1 view -0 + 2346 .cfi_startproc + 2347 @ args = 0, pretend = 0, frame = 0 + 2348 @ frame_needed = 0, uses_anonymous_args = 0 + 2349 @ link register save eliminated. +3193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2350 .loc 1 3193 3 view .LVU766 +3198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2351 .loc 1 3198 1 is_stmt 0 view .LVU767 + 2352 0000 7047 bx lr + 2353 .cfi_endproc + 2354 .LFE191: + 2356 .section .text.HAL_TIM_Encoder_MspDeInit,"ax",%progbits + 2357 .align 1 + 2358 .weak HAL_TIM_Encoder_MspDeInit + 2359 .syntax unified + 2360 .thumb + 2361 .thumb_func + 2363 HAL_TIM_Encoder_MspDeInit: + 2364 .LVL187: + 2365 .LFB192: +3206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 2366 .loc 1 3206 1 is_stmt 1 view -0 + 2367 .cfi_startproc + 2368 @ args = 0, pretend = 0, frame = 0 + 2369 @ frame_needed = 0, uses_anonymous_args = 0 + 2370 @ link register save eliminated. +3208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2371 .loc 1 3208 3 view .LVU769 +3213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2372 .loc 1 3213 1 is_stmt 0 view .LVU770 + 2373 0000 7047 bx lr + 2374 .cfi_endproc + 2375 .LFE192: + 2377 .section .text.HAL_TIM_Encoder_DeInit,"ax",%progbits + 2378 .align 1 + 2379 .global HAL_TIM_Encoder_DeInit + 2380 .syntax unified + 2381 .thumb + 2382 .thumb_func + 2384 HAL_TIM_Encoder_DeInit: + 2385 .LVL188: + 2386 .LFB190: +3146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 2387 .loc 1 3146 1 is_stmt 1 view -0 + 2388 .cfi_startproc + 2389 @ args = 0, pretend = 0, frame = 0 + 2390 @ frame_needed = 0, uses_anonymous_args = 0 +3146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 2391 .loc 1 3146 1 is_stmt 0 view .LVU772 + 2392 0000 10B5 push {r4, lr} + 2393 .LCFI27: + 2394 .cfi_def_cfa_offset 8 + 2395 .cfi_offset 4, -8 + 2396 .cfi_offset 14, -4 + ARM GAS /tmp/ccGFzgX3.s page 185 + + + 2397 0002 0446 mov r4, r0 +3148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2398 .loc 1 3148 3 is_stmt 1 view .LVU773 +3150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2399 .loc 1 3150 3 view .LVU774 +3150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2400 .loc 1 3150 15 is_stmt 0 view .LVU775 + 2401 0004 0223 movs r3, #2 + 2402 0006 80F83D30 strb r3, [r0, #61] +3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2403 .loc 1 3153 3 is_stmt 1 view .LVU776 +3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2404 .loc 1 3153 3 view .LVU777 + 2405 000a 0368 ldr r3, [r0] + 2406 000c 196A ldr r1, [r3, #32] + 2407 000e 41F21112 movw r2, #4369 + 2408 0012 1142 tst r1, r2 + 2409 0014 08D1 bne .L99 +3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2410 .loc 1 3153 3 discriminator 1 view .LVU778 + 2411 0016 196A ldr r1, [r3, #32] + 2412 0018 40F24442 movw r2, #1092 + 2413 001c 1142 tst r1, r2 + 2414 001e 03D1 bne .L99 +3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2415 .loc 1 3153 3 discriminator 3 view .LVU779 + 2416 0020 1A68 ldr r2, [r3] + 2417 0022 22F00102 bic r2, r2, #1 + 2418 0026 1A60 str r2, [r3] + 2419 .L99: +3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2420 .loc 1 3153 3 discriminator 5 view .LVU780 +3164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 2421 .loc 1 3164 3 view .LVU781 + 2422 0028 2046 mov r0, r4 + 2423 .LVL189: +3164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 2424 .loc 1 3164 3 is_stmt 0 view .LVU782 + 2425 002a FFF7FEFF bl HAL_TIM_Encoder_MspDeInit + 2426 .LVL190: +3168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2427 .loc 1 3168 3 is_stmt 1 view .LVU783 +3168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2428 .loc 1 3168 23 is_stmt 0 view .LVU784 + 2429 002e 0020 movs r0, #0 + 2430 0030 84F84800 strb r0, [r4, #72] +3171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + 2431 .loc 1 3171 3 is_stmt 1 view .LVU785 + 2432 0034 84F83E00 strb r0, [r4, #62] +3172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + 2433 .loc 1 3172 3 view .LVU786 + 2434 0038 84F83F00 strb r0, [r4, #63] +3173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + 2435 .loc 1 3173 3 view .LVU787 + 2436 003c 84F84400 strb r0, [r4, #68] +3174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2437 .loc 1 3174 3 view .LVU788 + ARM GAS /tmp/ccGFzgX3.s page 186 + + + 2438 0040 84F84500 strb r0, [r4, #69] +3177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2439 .loc 1 3177 3 view .LVU789 +3177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2440 .loc 1 3177 15 is_stmt 0 view .LVU790 + 2441 0044 84F83D00 strb r0, [r4, #61] +3180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2442 .loc 1 3180 3 is_stmt 1 view .LVU791 +3180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2443 .loc 1 3180 3 view .LVU792 + 2444 0048 84F83C00 strb r0, [r4, #60] +3180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2445 .loc 1 3180 3 view .LVU793 +3182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2446 .loc 1 3182 3 view .LVU794 +3183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2447 .loc 1 3183 1 is_stmt 0 view .LVU795 + 2448 004c 10BD pop {r4, pc} +3183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2449 .loc 1 3183 1 view .LVU796 + 2450 .cfi_endproc + 2451 .LFE190: + 2453 .section .text.HAL_TIM_DMABurst_MultiWriteStart,"ax",%progbits + 2454 .align 1 + 2455 .global HAL_TIM_DMABurst_MultiWriteStart + 2456 .syntax unified + 2457 .thumb + 2458 .thumb_func + 2460 HAL_TIM_DMABurst_MultiWriteStart: + 2461 .LVL191: + 2462 .LFB205: +4634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 2463 .loc 1 4634 1 is_stmt 1 view -0 + 2464 .cfi_startproc + 2465 @ args = 8, pretend = 0, frame = 0 + 2466 @ frame_needed = 0, uses_anonymous_args = 0 +4634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 2467 .loc 1 4634 1 is_stmt 0 view .LVU798 + 2468 0000 70B5 push {r4, r5, r6, lr} + 2469 .LCFI28: + 2470 .cfi_def_cfa_offset 16 + 2471 .cfi_offset 4, -16 + 2472 .cfi_offset 5, -12 + 2473 .cfi_offset 6, -8 + 2474 .cfi_offset 14, -4 + 2475 0002 0446 mov r4, r0 +4635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2476 .loc 1 4635 3 is_stmt 1 view .LVU799 + 2477 .LVL192: +4638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + 2478 .loc 1 4638 3 view .LVU800 +4639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + 2479 .loc 1 4639 3 view .LVU801 +4640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + 2480 .loc 1 4640 3 view .LVU802 +4641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + 2481 .loc 1 4641 3 view .LVU803 + ARM GAS /tmp/ccGFzgX3.s page 187 + + +4642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2482 .loc 1 4642 3 view .LVU804 +4644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2483 .loc 1 4644 3 view .LVU805 +4644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2484 .loc 1 4644 11 is_stmt 0 view .LVU806 + 2485 0004 90F84800 ldrb r0, [r0, #72] @ zero_extendqisi2 + 2486 .LVL193: +4644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2487 .loc 1 4644 11 view .LVU807 + 2488 0008 C0B2 uxtb r0, r0 +4644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2489 .loc 1 4644 6 view .LVU808 + 2490 000a 0228 cmp r0, #2 + 2491 000c 2FD0 beq .L102 + 2492 000e 0E46 mov r6, r1 + 2493 0010 1546 mov r5, r2 + 2494 0012 1946 mov r1, r3 + 2495 .LVL194: +4648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2496 .loc 1 4648 8 is_stmt 1 view .LVU809 +4648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2497 .loc 1 4648 16 is_stmt 0 view .LVU810 + 2498 0014 94F84800 ldrb r0, [r4, #72] @ zero_extendqisi2 + 2499 0018 C0B2 uxtb r0, r0 +4648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2500 .loc 1 4648 11 view .LVU811 + 2501 001a 0128 cmp r0, #1 + 2502 001c 28D0 beq .L121 + 2503 .LVL195: + 2504 .L103: +4662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2505 .loc 1 4662 3 is_stmt 1 view .LVU812 +4664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2506 .loc 1 4664 3 view .LVU813 + 2507 001e B5F5006F cmp r5, #2048 + 2508 0022 78D0 beq .L104 + 2509 0024 33D8 bhi .L105 + 2510 0026 B5F5007F cmp r5, #512 + 2511 002a 4ED0 beq .L106 + 2512 002c B5F5806F cmp r5, #1024 + 2513 0030 5ED0 beq .L107 + 2514 0032 B5F5807F cmp r5, #256 + 2515 0036 28D1 bne .L122 +4669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + 2516 .loc 1 4669 7 view .LVU814 +4669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + 2517 .loc 1 4669 17 is_stmt 0 view .LVU815 + 2518 0038 236A ldr r3, [r4, #32] +4669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + 2519 .loc 1 4669 55 view .LVU816 + 2520 003a 554A ldr r2, .L125 + 2521 003c DA63 str r2, [r3, #60] +4670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2522 .loc 1 4670 7 is_stmt 1 view .LVU817 +4670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2523 .loc 1 4670 17 is_stmt 0 view .LVU818 + ARM GAS /tmp/ccGFzgX3.s page 188 + + + 2524 003e 236A ldr r3, [r4, #32] +4670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2525 .loc 1 4670 59 view .LVU819 + 2526 0040 544A ldr r2, .L125+4 + 2527 0042 1A64 str r2, [r3, #64] +4673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2528 .loc 1 4673 7 is_stmt 1 view .LVU820 +4673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2529 .loc 1 4673 17 is_stmt 0 view .LVU821 + 2530 0044 236A ldr r3, [r4, #32] +4673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2531 .loc 1 4673 56 view .LVU822 + 2532 0046 544A ldr r2, .L125+8 + 2533 0048 DA64 str r2, [r3, #76] +4676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2534 .loc 1 4676 7 is_stmt 1 view .LVU823 +4677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2535 .loc 1 4677 43 is_stmt 0 view .LVU824 + 2536 004a 2268 ldr r2, [r4] +4676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2537 .loc 1 4676 11 view .LVU825 + 2538 004c 059B ldr r3, [sp, #20] + 2539 004e 4C32 adds r2, r2, #76 + 2540 0050 206A ldr r0, [r4, #32] + 2541 0052 FFF7FEFF bl HAL_DMA_Start_IT + 2542 .LVL196: +4676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2543 .loc 1 4676 10 discriminator 1 view .LVU826 + 2544 0056 0028 cmp r0, #0 + 2545 0058 40F09880 bne .L123 + 2546 .L112: + 2547 .LVL197: +4800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM DMA Request */ + 2548 .loc 1 4800 5 is_stmt 1 view .LVU827 +4800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM DMA Request */ + 2549 .loc 1 4800 9 is_stmt 0 view .LVU828 + 2550 005c 2368 ldr r3, [r4] +4800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM DMA Request */ + 2551 .loc 1 4800 45 view .LVU829 + 2552 005e 049A ldr r2, [sp, #16] + 2553 0060 1643 orrs r6, r6, r2 + 2554 .LVL198: +4800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM DMA Request */ + 2555 .loc 1 4800 25 view .LVU830 + 2556 0062 9E64 str r6, [r3, #72] +4802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2557 .loc 1 4802 5 is_stmt 1 view .LVU831 + 2558 0064 2268 ldr r2, [r4] + 2559 0066 D368 ldr r3, [r2, #12] + 2560 0068 2B43 orrs r3, r3, r5 + 2561 006a D360 str r3, [r2, #12] + 2562 006c 0020 movs r0, #0 + 2563 .LVL199: + 2564 .L102: +4807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2565 .loc 1 4807 1 is_stmt 0 view .LVU832 + 2566 006e 70BD pop {r4, r5, r6, pc} + ARM GAS /tmp/ccGFzgX3.s page 189 + + + 2567 .LVL200: + 2568 .L121: +4650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2569 .loc 1 4650 5 is_stmt 1 view .LVU833 +4650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2570 .loc 1 4650 31 is_stmt 0 view .LVU834 + 2571 0070 049A ldr r2, [sp, #16] + 2572 .LVL201: +4650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2573 .loc 1 4650 31 view .LVU835 + 2574 0072 B3FA83F3 clz r3, r3 + 2575 0076 5B09 lsrs r3, r3, #5 + 2576 0078 002A cmp r2, #0 + 2577 007a 08BF it eq + 2578 007c 0023 moveq r3, #0 +4650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2579 .loc 1 4650 8 view .LVU836 + 2580 007e 002B cmp r3, #0 + 2581 0080 F5D1 bne .L102 +4656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2582 .loc 1 4656 7 is_stmt 1 view .LVU837 +4656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2583 .loc 1 4656 27 is_stmt 0 view .LVU838 + 2584 0082 0223 movs r3, #2 + 2585 0084 84F84830 strb r3, [r4, #72] + 2586 0088 C9E7 b .L103 + 2587 .L122: +4664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2588 .loc 1 4664 3 view .LVU839 + 2589 008a 0120 movs r0, #1 + 2590 008c EFE7 b .L102 + 2591 .L105: + 2592 008e B5F5005F cmp r5, #8192 + 2593 0092 53D0 beq .L109 + 2594 0094 B5F5804F cmp r5, #16384 + 2595 0098 64D0 beq .L110 + 2596 009a B5F5805F cmp r5, #4096 + 2597 009e 12D1 bne .L124 +4741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2598 .loc 1 4741 7 is_stmt 1 view .LVU840 +4741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2599 .loc 1 4741 17 is_stmt 0 view .LVU841 + 2600 00a0 236B ldr r3, [r4, #48] +4741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2601 .loc 1 4741 52 view .LVU842 + 2602 00a2 3E4A ldr r2, .L125+12 + 2603 00a4 DA63 str r2, [r3, #60] +4742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2604 .loc 1 4742 7 is_stmt 1 view .LVU843 +4742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2605 .loc 1 4742 17 is_stmt 0 view .LVU844 + 2606 00a6 236B ldr r3, [r4, #48] +4742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2607 .loc 1 4742 56 view .LVU845 + 2608 00a8 3D4A ldr r2, .L125+16 + 2609 00aa 1A64 str r2, [r3, #64] +4745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 190 + + + 2610 .loc 1 4745 7 is_stmt 1 view .LVU846 +4745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2611 .loc 1 4745 17 is_stmt 0 view .LVU847 + 2612 00ac 236B ldr r3, [r4, #48] +4745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2613 .loc 1 4745 53 view .LVU848 + 2614 00ae 3A4A ldr r2, .L125+8 + 2615 00b0 DA64 str r2, [r3, #76] +4748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2616 .loc 1 4748 7 is_stmt 1 view .LVU849 +4749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2617 .loc 1 4749 43 is_stmt 0 view .LVU850 + 2618 00b2 2268 ldr r2, [r4] +4748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2619 .loc 1 4748 11 view .LVU851 + 2620 00b4 059B ldr r3, [sp, #20] + 2621 00b6 4C32 adds r2, r2, #76 + 2622 00b8 206B ldr r0, [r4, #48] + 2623 00ba FFF7FEFF bl HAL_DMA_Start_IT + 2624 .LVL202: +4748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2625 .loc 1 4748 10 discriminator 1 view .LVU852 + 2626 00be 0028 cmp r0, #0 + 2627 00c0 CCD0 beq .L112 +4752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2628 .loc 1 4752 16 view .LVU853 + 2629 00c2 0120 movs r0, #1 + 2630 00c4 D3E7 b .L102 + 2631 .LVL203: + 2632 .L124: +4664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2633 .loc 1 4664 3 view .LVU854 + 2634 00c6 0120 movs r0, #1 + 2635 00c8 D1E7 b .L102 + 2636 .L106: +4687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2637 .loc 1 4687 7 is_stmt 1 view .LVU855 +4687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2638 .loc 1 4687 17 is_stmt 0 view .LVU856 + 2639 00ca 636A ldr r3, [r4, #36] +4687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2640 .loc 1 4687 52 view .LVU857 + 2641 00cc 334A ldr r2, .L125+12 + 2642 00ce DA63 str r2, [r3, #60] +4688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2643 .loc 1 4688 7 is_stmt 1 view .LVU858 +4688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2644 .loc 1 4688 17 is_stmt 0 view .LVU859 + 2645 00d0 636A ldr r3, [r4, #36] +4688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2646 .loc 1 4688 56 view .LVU860 + 2647 00d2 334A ldr r2, .L125+16 + 2648 00d4 1A64 str r2, [r3, #64] +4691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2649 .loc 1 4691 7 is_stmt 1 view .LVU861 +4691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2650 .loc 1 4691 17 is_stmt 0 view .LVU862 + ARM GAS /tmp/ccGFzgX3.s page 191 + + + 2651 00d6 636A ldr r3, [r4, #36] +4691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2652 .loc 1 4691 53 view .LVU863 + 2653 00d8 2F4A ldr r2, .L125+8 + 2654 00da DA64 str r2, [r3, #76] +4694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2655 .loc 1 4694 7 is_stmt 1 view .LVU864 +4695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2656 .loc 1 4695 43 is_stmt 0 view .LVU865 + 2657 00dc 2268 ldr r2, [r4] +4694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2658 .loc 1 4694 11 view .LVU866 + 2659 00de 059B ldr r3, [sp, #20] + 2660 00e0 4C32 adds r2, r2, #76 + 2661 00e2 606A ldr r0, [r4, #36] + 2662 00e4 FFF7FEFF bl HAL_DMA_Start_IT + 2663 .LVL204: +4694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2664 .loc 1 4694 10 discriminator 1 view .LVU867 + 2665 00e8 0028 cmp r0, #0 + 2666 00ea B7D0 beq .L112 +4698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2667 .loc 1 4698 16 view .LVU868 + 2668 00ec 0120 movs r0, #1 + 2669 00ee BEE7 b .L102 + 2670 .LVL205: + 2671 .L107: +4705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2672 .loc 1 4705 7 is_stmt 1 view .LVU869 +4705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2673 .loc 1 4705 17 is_stmt 0 view .LVU870 + 2674 00f0 A36A ldr r3, [r4, #40] +4705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2675 .loc 1 4705 52 view .LVU871 + 2676 00f2 2A4A ldr r2, .L125+12 + 2677 00f4 DA63 str r2, [r3, #60] +4706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2678 .loc 1 4706 7 is_stmt 1 view .LVU872 +4706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2679 .loc 1 4706 17 is_stmt 0 view .LVU873 + 2680 00f6 A36A ldr r3, [r4, #40] +4706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2681 .loc 1 4706 56 view .LVU874 + 2682 00f8 294A ldr r2, .L125+16 + 2683 00fa 1A64 str r2, [r3, #64] +4709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2684 .loc 1 4709 7 is_stmt 1 view .LVU875 +4709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2685 .loc 1 4709 17 is_stmt 0 view .LVU876 + 2686 00fc A36A ldr r3, [r4, #40] +4709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2687 .loc 1 4709 53 view .LVU877 + 2688 00fe 264A ldr r2, .L125+8 + 2689 0100 DA64 str r2, [r3, #76] +4712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2690 .loc 1 4712 7 is_stmt 1 view .LVU878 +4713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 192 + + + 2691 .loc 1 4713 43 is_stmt 0 view .LVU879 + 2692 0102 2268 ldr r2, [r4] +4712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2693 .loc 1 4712 11 view .LVU880 + 2694 0104 059B ldr r3, [sp, #20] + 2695 0106 4C32 adds r2, r2, #76 + 2696 0108 A06A ldr r0, [r4, #40] + 2697 010a FFF7FEFF bl HAL_DMA_Start_IT + 2698 .LVL206: +4712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2699 .loc 1 4712 10 discriminator 1 view .LVU881 + 2700 010e 0028 cmp r0, #0 + 2701 0110 A4D0 beq .L112 +4716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2702 .loc 1 4716 16 view .LVU882 + 2703 0112 0120 movs r0, #1 + 2704 0114 ABE7 b .L102 + 2705 .LVL207: + 2706 .L104: +4723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2707 .loc 1 4723 7 is_stmt 1 view .LVU883 +4723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2708 .loc 1 4723 17 is_stmt 0 view .LVU884 + 2709 0116 E36A ldr r3, [r4, #44] +4723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2710 .loc 1 4723 52 view .LVU885 + 2711 0118 204A ldr r2, .L125+12 + 2712 011a DA63 str r2, [r3, #60] +4724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2713 .loc 1 4724 7 is_stmt 1 view .LVU886 +4724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2714 .loc 1 4724 17 is_stmt 0 view .LVU887 + 2715 011c E36A ldr r3, [r4, #44] +4724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2716 .loc 1 4724 56 view .LVU888 + 2717 011e 204A ldr r2, .L125+16 + 2718 0120 1A64 str r2, [r3, #64] +4727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2719 .loc 1 4727 7 is_stmt 1 view .LVU889 +4727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2720 .loc 1 4727 17 is_stmt 0 view .LVU890 + 2721 0122 E36A ldr r3, [r4, #44] +4727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2722 .loc 1 4727 53 view .LVU891 + 2723 0124 1C4A ldr r2, .L125+8 + 2724 0126 DA64 str r2, [r3, #76] +4730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2725 .loc 1 4730 7 is_stmt 1 view .LVU892 +4731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2726 .loc 1 4731 43 is_stmt 0 view .LVU893 + 2727 0128 2268 ldr r2, [r4] +4730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2728 .loc 1 4730 11 view .LVU894 + 2729 012a 059B ldr r3, [sp, #20] + 2730 012c 4C32 adds r2, r2, #76 + 2731 012e E06A ldr r0, [r4, #44] + 2732 0130 FFF7FEFF bl HAL_DMA_Start_IT + ARM GAS /tmp/ccGFzgX3.s page 193 + + + 2733 .LVL208: +4730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2734 .loc 1 4730 10 discriminator 1 view .LVU895 + 2735 0134 0028 cmp r0, #0 + 2736 0136 91D0 beq .L112 +4734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2737 .loc 1 4734 16 view .LVU896 + 2738 0138 0120 movs r0, #1 + 2739 013a 98E7 b .L102 + 2740 .LVL209: + 2741 .L109: +4759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + 2742 .loc 1 4759 7 is_stmt 1 view .LVU897 +4759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + 2743 .loc 1 4759 17 is_stmt 0 view .LVU898 + 2744 013c 636B ldr r3, [r4, #52] +4759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + 2745 .loc 1 4759 60 view .LVU899 + 2746 013e 194A ldr r2, .L125+20 + 2747 0140 DA63 str r2, [r3, #60] +4760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2748 .loc 1 4760 7 is_stmt 1 view .LVU900 +4760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2749 .loc 1 4760 17 is_stmt 0 view .LVU901 + 2750 0142 636B ldr r3, [r4, #52] +4760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2751 .loc 1 4760 64 view .LVU902 + 2752 0144 184A ldr r2, .L125+24 + 2753 0146 1A64 str r2, [r3, #64] +4763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2754 .loc 1 4763 7 is_stmt 1 view .LVU903 +4763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2755 .loc 1 4763 17 is_stmt 0 view .LVU904 + 2756 0148 636B ldr r3, [r4, #52] +4763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2757 .loc 1 4763 61 view .LVU905 + 2758 014a 134A ldr r2, .L125+8 + 2759 014c DA64 str r2, [r3, #76] +4766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2760 .loc 1 4766 7 is_stmt 1 view .LVU906 +4767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2761 .loc 1 4767 43 is_stmt 0 view .LVU907 + 2762 014e 2268 ldr r2, [r4] +4766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2763 .loc 1 4766 11 view .LVU908 + 2764 0150 059B ldr r3, [sp, #20] + 2765 0152 4C32 adds r2, r2, #76 + 2766 0154 606B ldr r0, [r4, #52] + 2767 0156 FFF7FEFF bl HAL_DMA_Start_IT + 2768 .LVL210: +4766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2769 .loc 1 4766 10 discriminator 1 view .LVU909 + 2770 015a 0028 cmp r0, #0 + 2771 015c 3FF47EAF beq .L112 +4770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2772 .loc 1 4770 16 view .LVU910 + 2773 0160 0120 movs r0, #1 + ARM GAS /tmp/ccGFzgX3.s page 194 + + + 2774 0162 84E7 b .L102 + 2775 .LVL211: + 2776 .L110: +4777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + 2777 .loc 1 4777 7 is_stmt 1 view .LVU911 +4777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + 2778 .loc 1 4777 17 is_stmt 0 view .LVU912 + 2779 0164 A36B ldr r3, [r4, #56] +4777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + 2780 .loc 1 4777 56 view .LVU913 + 2781 0166 114A ldr r2, .L125+28 + 2782 0168 DA63 str r2, [r3, #60] +4778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2783 .loc 1 4778 7 is_stmt 1 view .LVU914 +4778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2784 .loc 1 4778 17 is_stmt 0 view .LVU915 + 2785 016a A36B ldr r3, [r4, #56] +4778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2786 .loc 1 4778 60 view .LVU916 + 2787 016c 104A ldr r2, .L125+32 + 2788 016e 1A64 str r2, [r3, #64] +4781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2789 .loc 1 4781 7 is_stmt 1 view .LVU917 +4781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2790 .loc 1 4781 17 is_stmt 0 view .LVU918 + 2791 0170 A36B ldr r3, [r4, #56] +4781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2792 .loc 1 4781 57 view .LVU919 + 2793 0172 094A ldr r2, .L125+8 + 2794 0174 DA64 str r2, [r3, #76] +4784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2795 .loc 1 4784 7 is_stmt 1 view .LVU920 +4785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2796 .loc 1 4785 43 is_stmt 0 view .LVU921 + 2797 0176 2268 ldr r2, [r4] +4784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2798 .loc 1 4784 11 view .LVU922 + 2799 0178 059B ldr r3, [sp, #20] + 2800 017a 4C32 adds r2, r2, #76 + 2801 017c A06B ldr r0, [r4, #56] + 2802 017e FFF7FEFF bl HAL_DMA_Start_IT + 2803 .LVL212: +4784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 2804 .loc 1 4784 10 discriminator 1 view .LVU923 + 2805 0182 0028 cmp r0, #0 + 2806 0184 3FF46AAF beq .L112 +4788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2807 .loc 1 4788 16 view .LVU924 + 2808 0188 0120 movs r0, #1 + 2809 018a 70E7 b .L102 + 2810 .L123: +4680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2811 .loc 1 4680 16 view .LVU925 + 2812 018c 0120 movs r0, #1 + 2813 018e 6EE7 b .L102 + 2814 .L126: + 2815 .align 2 + ARM GAS /tmp/ccGFzgX3.s page 195 + + + 2816 .L125: + 2817 0190 00000000 .word TIM_DMAPeriodElapsedCplt + 2818 0194 00000000 .word TIM_DMAPeriodElapsedHalfCplt + 2819 0198 00000000 .word TIM_DMAError + 2820 019c 00000000 .word TIM_DMADelayPulseCplt + 2821 01a0 00000000 .word TIM_DMADelayPulseHalfCplt + 2822 01a4 00000000 .word TIMEx_DMACommutationCplt + 2823 01a8 00000000 .word TIMEx_DMACommutationHalfCplt + 2824 01ac 00000000 .word TIM_DMATriggerCplt + 2825 01b0 00000000 .word TIM_DMATriggerHalfCplt + 2826 .cfi_endproc + 2827 .LFE205: + 2829 .section .text.HAL_TIM_DMABurst_WriteStart,"ax",%progbits + 2830 .align 1 + 2831 .global HAL_TIM_DMABurst_WriteStart + 2832 .syntax unified + 2833 .thumb + 2834 .thumb_func + 2836 HAL_TIM_DMABurst_WriteStart: + 2837 .LVL213: + 2838 .LFB204: +4574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status; + 2839 .loc 1 4574 1 is_stmt 1 view -0 + 2840 .cfi_startproc + 2841 @ args = 4, pretend = 0, frame = 0 + 2842 @ frame_needed = 0, uses_anonymous_args = 0 +4574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status; + 2843 .loc 1 4574 1 is_stmt 0 view .LVU927 + 2844 0000 30B5 push {r4, r5, lr} + 2845 .LCFI29: + 2846 .cfi_def_cfa_offset 12 + 2847 .cfi_offset 4, -12 + 2848 .cfi_offset 5, -8 + 2849 .cfi_offset 14, -4 + 2850 0002 83B0 sub sp, sp, #12 + 2851 .LCFI30: + 2852 .cfi_def_cfa_offset 24 + 2853 0004 069D ldr r5, [sp, #24] +4575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2854 .loc 1 4575 3 is_stmt 1 view .LVU928 +4577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ((BurstLength) >> 8U) + 1U); + 2855 .loc 1 4577 3 view .LVU929 +4578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2856 .loc 1 4578 60 is_stmt 0 view .LVU930 + 2857 0006 2C0A lsrs r4, r5, #8 +4577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ((BurstLength) >> 8U) + 1U); + 2858 .loc 1 4577 12 view .LVU931 + 2859 0008 0134 adds r4, r4, #1 + 2860 000a 0194 str r4, [sp, #4] + 2861 000c 0095 str r5, [sp] + 2862 000e FFF7FEFF bl HAL_TIM_DMABurst_MultiWriteStart + 2863 .LVL214: +4582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2864 .loc 1 4582 3 is_stmt 1 view .LVU932 +4583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2865 .loc 1 4583 1 is_stmt 0 view .LVU933 + 2866 0012 03B0 add sp, sp, #12 + ARM GAS /tmp/ccGFzgX3.s page 196 + + + 2867 .LCFI31: + 2868 .cfi_def_cfa_offset 12 + 2869 @ sp needed + 2870 0014 30BD pop {r4, r5, pc} +4583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2871 .loc 1 4583 1 view .LVU934 + 2872 .cfi_endproc + 2873 .LFE204: + 2875 .section .text.HAL_TIM_DMABurst_WriteStop,"ax",%progbits + 2876 .align 1 + 2877 .global HAL_TIM_DMABurst_WriteStop + 2878 .syntax unified + 2879 .thumb + 2880 .thumb_func + 2882 HAL_TIM_DMABurst_WriteStop: + 2883 .LVL215: + 2884 .LFB206: +4816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 2885 .loc 1 4816 1 is_stmt 1 view -0 + 2886 .cfi_startproc + 2887 @ args = 0, pretend = 0, frame = 0 + 2888 @ frame_needed = 0, uses_anonymous_args = 0 +4816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 2889 .loc 1 4816 1 is_stmt 0 view .LVU936 + 2890 0000 38B5 push {r3, r4, r5, lr} + 2891 .LCFI32: + 2892 .cfi_def_cfa_offset 16 + 2893 .cfi_offset 3, -16 + 2894 .cfi_offset 4, -12 + 2895 .cfi_offset 5, -8 + 2896 .cfi_offset 14, -4 + 2897 0002 0546 mov r5, r0 + 2898 0004 0C46 mov r4, r1 +4817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2899 .loc 1 4817 3 is_stmt 1 view .LVU937 + 2900 .LVL216: +4820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2901 .loc 1 4820 3 view .LVU938 +4823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2902 .loc 1 4823 3 view .LVU939 + 2903 0006 B1F5006F cmp r1, #2048 + 2904 000a 2FD0 beq .L130 + 2905 000c 17D8 bhi .L131 + 2906 000e B1F5007F cmp r1, #512 + 2907 0012 23D0 beq .L132 + 2908 0014 B1F5806F cmp r1, #1024 + 2909 0018 24D0 beq .L133 + 2910 001a B1F5807F cmp r1, #256 + 2911 001e 0CD1 bne .L141 +4827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 2912 .loc 1 4827 7 view .LVU940 +4827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 2913 .loc 1 4827 13 is_stmt 0 view .LVU941 + 2914 0020 006A ldr r0, [r0, #32] + 2915 .LVL217: +4827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 2916 .loc 1 4827 13 view .LVU942 + ARM GAS /tmp/ccGFzgX3.s page 197 + + + 2917 0022 FFF7FEFF bl HAL_DMA_Abort_IT + 2918 .LVL218: +4828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2919 .loc 1 4828 7 is_stmt 1 view .LVU943 +4865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2920 .loc 1 4865 3 view .LVU944 + 2921 .L139: +4868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2922 .loc 1 4868 5 view .LVU945 + 2923 0026 2A68 ldr r2, [r5] + 2924 0028 D368 ldr r3, [r2, #12] + 2925 002a 23EA0403 bic r3, r3, r4 + 2926 002e D360 str r3, [r2, #12] +4871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2927 .loc 1 4871 5 view .LVU946 +4871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2928 .loc 1 4871 25 is_stmt 0 view .LVU947 + 2929 0030 0123 movs r3, #1 + 2930 0032 85F84830 strb r3, [r5, #72] + 2931 0036 0020 movs r0, #0 + 2932 .L135: + 2933 .LVL219: +4875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2934 .loc 1 4875 3 is_stmt 1 view .LVU948 +4876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 2935 .loc 1 4876 1 is_stmt 0 view .LVU949 + 2936 0038 38BD pop {r3, r4, r5, pc} + 2937 .LVL220: + 2938 .L141: +4823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2939 .loc 1 4823 3 view .LVU950 + 2940 003a 0120 movs r0, #1 + 2941 .LVL221: +4823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2942 .loc 1 4823 3 view .LVU951 + 2943 003c FCE7 b .L135 + 2944 .LVL222: + 2945 .L131: +4823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2946 .loc 1 4823 3 view .LVU952 + 2947 003e B1F5005F cmp r1, #8192 + 2948 0042 17D0 beq .L136 + 2949 0044 B1F5804F cmp r1, #16384 + 2950 0048 18D0 beq .L137 + 2951 004a B1F5805F cmp r1, #4096 + 2952 004e 03D1 bne .L142 +4847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 2953 .loc 1 4847 7 is_stmt 1 view .LVU953 +4847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 2954 .loc 1 4847 13 is_stmt 0 view .LVU954 + 2955 0050 006B ldr r0, [r0, #48] + 2956 .LVL223: +4847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 2957 .loc 1 4847 13 view .LVU955 + 2958 0052 FFF7FEFF bl HAL_DMA_Abort_IT + 2959 .LVL224: +4848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + ARM GAS /tmp/ccGFzgX3.s page 198 + + + 2960 .loc 1 4848 7 is_stmt 1 view .LVU956 +4865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2961 .loc 1 4865 3 view .LVU957 + 2962 0056 E6E7 b .L139 + 2963 .LVL225: + 2964 .L142: +4823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2965 .loc 1 4823 3 is_stmt 0 view .LVU958 + 2966 0058 0120 movs r0, #1 + 2967 .LVL226: +4823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2968 .loc 1 4823 3 view .LVU959 + 2969 005a EDE7 b .L135 + 2970 .LVL227: + 2971 .L132: +4832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 2972 .loc 1 4832 7 is_stmt 1 view .LVU960 +4832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 2973 .loc 1 4832 13 is_stmt 0 view .LVU961 + 2974 005c 406A ldr r0, [r0, #36] + 2975 .LVL228: +4832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 2976 .loc 1 4832 13 view .LVU962 + 2977 005e FFF7FEFF bl HAL_DMA_Abort_IT + 2978 .LVL229: +4833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2979 .loc 1 4833 7 is_stmt 1 view .LVU963 +4865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2980 .loc 1 4865 3 view .LVU964 + 2981 0062 E0E7 b .L139 + 2982 .LVL230: + 2983 .L133: +4837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 2984 .loc 1 4837 7 view .LVU965 +4837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 2985 .loc 1 4837 13 is_stmt 0 view .LVU966 + 2986 0064 806A ldr r0, [r0, #40] + 2987 .LVL231: +4837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 2988 .loc 1 4837 13 view .LVU967 + 2989 0066 FFF7FEFF bl HAL_DMA_Abort_IT + 2990 .LVL232: +4838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 2991 .loc 1 4838 7 is_stmt 1 view .LVU968 +4865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 2992 .loc 1 4865 3 view .LVU969 + 2993 006a DCE7 b .L139 + 2994 .LVL233: + 2995 .L130: +4842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 2996 .loc 1 4842 7 view .LVU970 +4842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 2997 .loc 1 4842 13 is_stmt 0 view .LVU971 + 2998 006c C06A ldr r0, [r0, #44] + 2999 .LVL234: +4842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3000 .loc 1 4842 13 view .LVU972 + ARM GAS /tmp/ccGFzgX3.s page 199 + + + 3001 006e FFF7FEFF bl HAL_DMA_Abort_IT + 3002 .LVL235: +4843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3003 .loc 1 4843 7 is_stmt 1 view .LVU973 +4865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3004 .loc 1 4865 3 view .LVU974 + 3005 0072 D8E7 b .L139 + 3006 .LVL236: + 3007 .L136: +4852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3008 .loc 1 4852 7 view .LVU975 +4852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3009 .loc 1 4852 13 is_stmt 0 view .LVU976 + 3010 0074 406B ldr r0, [r0, #52] + 3011 .LVL237: +4852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3012 .loc 1 4852 13 view .LVU977 + 3013 0076 FFF7FEFF bl HAL_DMA_Abort_IT + 3014 .LVL238: +4853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3015 .loc 1 4853 7 is_stmt 1 view .LVU978 +4865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3016 .loc 1 4865 3 view .LVU979 + 3017 007a D4E7 b .L139 + 3018 .LVL239: + 3019 .L137: +4857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3020 .loc 1 4857 7 view .LVU980 +4857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3021 .loc 1 4857 13 is_stmt 0 view .LVU981 + 3022 007c 806B ldr r0, [r0, #56] + 3023 .LVL240: +4857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3024 .loc 1 4857 13 view .LVU982 + 3025 007e FFF7FEFF bl HAL_DMA_Abort_IT + 3026 .LVL241: +4858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3027 .loc 1 4858 7 is_stmt 1 view .LVU983 +4865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3028 .loc 1 4865 3 view .LVU984 + 3029 0082 D0E7 b .L139 + 3030 .cfi_endproc + 3031 .LFE206: + 3033 .section .text.HAL_TIM_DMABurst_MultiReadStart,"ax",%progbits + 3034 .align 1 + 3035 .global HAL_TIM_DMABurst_MultiReadStart + 3036 .syntax unified + 3037 .thumb + 3038 .thumb_func + 3040 HAL_TIM_DMABurst_MultiReadStart: + 3041 .LVL242: + 3042 .LFB208: +4984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 3043 .loc 1 4984 1 view -0 + 3044 .cfi_startproc + 3045 @ args = 8, pretend = 0, frame = 0 + 3046 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccGFzgX3.s page 200 + + +4984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 3047 .loc 1 4984 1 is_stmt 0 view .LVU986 + 3048 0000 70B5 push {r4, r5, r6, lr} + 3049 .LCFI33: + 3050 .cfi_def_cfa_offset 16 + 3051 .cfi_offset 4, -16 + 3052 .cfi_offset 5, -12 + 3053 .cfi_offset 6, -8 + 3054 .cfi_offset 14, -4 + 3055 0002 0446 mov r4, r0 +4985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3056 .loc 1 4985 3 is_stmt 1 view .LVU987 + 3057 .LVL243: +4988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + 3058 .loc 1 4988 3 view .LVU988 +4989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + 3059 .loc 1 4989 3 view .LVU989 +4990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + 3060 .loc 1 4990 3 view .LVU990 +4991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + 3061 .loc 1 4991 3 view .LVU991 +4992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3062 .loc 1 4992 3 view .LVU992 +4994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3063 .loc 1 4994 3 view .LVU993 +4994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3064 .loc 1 4994 11 is_stmt 0 view .LVU994 + 3065 0004 90F84800 ldrb r0, [r0, #72] @ zero_extendqisi2 + 3066 .LVL244: +4994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3067 .loc 1 4994 11 view .LVU995 + 3068 0008 C0B2 uxtb r0, r0 +4994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3069 .loc 1 4994 6 view .LVU996 + 3070 000a 0228 cmp r0, #2 + 3071 000c 2FD0 beq .L144 + 3072 000e 0E46 mov r6, r1 + 3073 0010 1546 mov r5, r2 + 3074 0012 1A46 mov r2, r3 + 3075 .LVL245: +4998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3076 .loc 1 4998 8 is_stmt 1 view .LVU997 +4998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3077 .loc 1 4998 16 is_stmt 0 view .LVU998 + 3078 0014 94F84800 ldrb r0, [r4, #72] @ zero_extendqisi2 + 3079 0018 C0B2 uxtb r0, r0 +4998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3080 .loc 1 4998 11 view .LVU999 + 3081 001a 0128 cmp r0, #1 + 3082 001c 28D0 beq .L163 + 3083 .LVL246: + 3084 .L145: +5012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** switch (BurstRequestSrc) + 3085 .loc 1 5012 3 is_stmt 1 view .LVU1000 +5013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3086 .loc 1 5013 3 view .LVU1001 + 3087 001e B5F5006F cmp r5, #2048 + ARM GAS /tmp/ccGFzgX3.s page 201 + + + 3088 0022 78D0 beq .L146 + 3089 0024 33D8 bhi .L147 + 3090 0026 B5F5007F cmp r5, #512 + 3091 002a 4ED0 beq .L148 + 3092 002c B5F5806F cmp r5, #1024 + 3093 0030 5ED0 beq .L149 + 3094 0032 B5F5807F cmp r5, #256 + 3095 0036 28D1 bne .L164 +5018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + 3096 .loc 1 5018 7 view .LVU1002 +5018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + 3097 .loc 1 5018 17 is_stmt 0 view .LVU1003 + 3098 0038 236A ldr r3, [r4, #32] +5018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + 3099 .loc 1 5018 55 view .LVU1004 + 3100 003a 5549 ldr r1, .L167 + 3101 003c D963 str r1, [r3, #60] +5019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3102 .loc 1 5019 7 is_stmt 1 view .LVU1005 +5019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3103 .loc 1 5019 17 is_stmt 0 view .LVU1006 + 3104 003e 236A ldr r3, [r4, #32] +5019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3105 .loc 1 5019 59 view .LVU1007 + 3106 0040 5449 ldr r1, .L167+4 + 3107 0042 1964 str r1, [r3, #64] +5022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3108 .loc 1 5022 7 is_stmt 1 view .LVU1008 +5022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3109 .loc 1 5022 17 is_stmt 0 view .LVU1009 + 3110 0044 236A ldr r3, [r4, #32] +5022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3111 .loc 1 5022 56 view .LVU1010 + 3112 0046 5449 ldr r1, .L167+8 + 3113 0048 D964 str r1, [r3, #76] +5025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3114 .loc 1 5025 7 is_stmt 1 view .LVU1011 +5025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3115 .loc 1 5025 74 is_stmt 0 view .LVU1012 + 3116 004a 2168 ldr r1, [r4] +5025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3117 .loc 1 5025 11 view .LVU1013 + 3118 004c 059B ldr r3, [sp, #20] + 3119 004e 4C31 adds r1, r1, #76 + 3120 0050 206A ldr r0, [r4, #32] + 3121 0052 FFF7FEFF bl HAL_DMA_Start_IT + 3122 .LVL247: +5025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3123 .loc 1 5025 10 discriminator 1 view .LVU1014 + 3124 0056 0028 cmp r0, #0 + 3125 0058 40F09880 bne .L165 + 3126 .L154: + 3127 .LVL248: +5149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3128 .loc 1 5149 5 is_stmt 1 view .LVU1015 +5149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3129 .loc 1 5149 9 is_stmt 0 view .LVU1016 + ARM GAS /tmp/ccGFzgX3.s page 202 + + + 3130 005c 2368 ldr r3, [r4] +5149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3131 .loc 1 5149 45 view .LVU1017 + 3132 005e 049A ldr r2, [sp, #16] + 3133 0060 1643 orrs r6, r6, r2 + 3134 .LVL249: +5149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3135 .loc 1 5149 25 view .LVU1018 + 3136 0062 9E64 str r6, [r3, #72] +5152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3137 .loc 1 5152 5 is_stmt 1 view .LVU1019 + 3138 0064 2268 ldr r2, [r4] + 3139 0066 D368 ldr r3, [r2, #12] + 3140 0068 2B43 orrs r3, r3, r5 + 3141 006a D360 str r3, [r2, #12] + 3142 006c 0020 movs r0, #0 + 3143 .LVL250: + 3144 .L144: +5157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3145 .loc 1 5157 1 is_stmt 0 view .LVU1020 + 3146 006e 70BD pop {r4, r5, r6, pc} + 3147 .LVL251: + 3148 .L163: +5000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3149 .loc 1 5000 5 is_stmt 1 view .LVU1021 +5000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3150 .loc 1 5000 31 is_stmt 0 view .LVU1022 + 3151 0070 0499 ldr r1, [sp, #16] + 3152 .LVL252: +5000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3153 .loc 1 5000 31 view .LVU1023 + 3154 0072 B3FA83F3 clz r3, r3 + 3155 0076 5B09 lsrs r3, r3, #5 + 3156 0078 0029 cmp r1, #0 + 3157 007a 08BF it eq + 3158 007c 0023 moveq r3, #0 +5000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3159 .loc 1 5000 8 view .LVU1024 + 3160 007e 002B cmp r3, #0 + 3161 0080 F5D1 bne .L144 +5006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3162 .loc 1 5006 7 is_stmt 1 view .LVU1025 +5006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3163 .loc 1 5006 27 is_stmt 0 view .LVU1026 + 3164 0082 0223 movs r3, #2 + 3165 0084 84F84830 strb r3, [r4, #72] + 3166 0088 C9E7 b .L145 + 3167 .L164: +5013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3168 .loc 1 5013 3 view .LVU1027 + 3169 008a 0120 movs r0, #1 + 3170 008c EFE7 b .L144 + 3171 .L147: + 3172 008e B5F5005F cmp r5, #8192 + 3173 0092 53D0 beq .L151 + 3174 0094 B5F5804F cmp r5, #16384 + 3175 0098 64D0 beq .L152 + ARM GAS /tmp/ccGFzgX3.s page 203 + + + 3176 009a B5F5805F cmp r5, #4096 + 3177 009e 12D1 bne .L166 +5090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 3178 .loc 1 5090 7 is_stmt 1 view .LVU1028 +5090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 3179 .loc 1 5090 17 is_stmt 0 view .LVU1029 + 3180 00a0 236B ldr r3, [r4, #48] +5090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 3181 .loc 1 5090 52 view .LVU1030 + 3182 00a2 3E49 ldr r1, .L167+12 + 3183 00a4 D963 str r1, [r3, #60] +5091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3184 .loc 1 5091 7 is_stmt 1 view .LVU1031 +5091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3185 .loc 1 5091 17 is_stmt 0 view .LVU1032 + 3186 00a6 236B ldr r3, [r4, #48] +5091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3187 .loc 1 5091 56 view .LVU1033 + 3188 00a8 3D49 ldr r1, .L167+16 + 3189 00aa 1964 str r1, [r3, #64] +5094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3190 .loc 1 5094 7 is_stmt 1 view .LVU1034 +5094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3191 .loc 1 5094 17 is_stmt 0 view .LVU1035 + 3192 00ac 236B ldr r3, [r4, #48] +5094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3193 .loc 1 5094 53 view .LVU1036 + 3194 00ae 3A49 ldr r1, .L167+8 + 3195 00b0 D964 str r1, [r3, #76] +5097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3196 .loc 1 5097 7 is_stmt 1 view .LVU1037 +5097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3197 .loc 1 5097 71 is_stmt 0 view .LVU1038 + 3198 00b2 2168 ldr r1, [r4] +5097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3199 .loc 1 5097 11 view .LVU1039 + 3200 00b4 059B ldr r3, [sp, #20] + 3201 00b6 4C31 adds r1, r1, #76 + 3202 00b8 206B ldr r0, [r4, #48] + 3203 00ba FFF7FEFF bl HAL_DMA_Start_IT + 3204 .LVL253: +5097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3205 .loc 1 5097 10 discriminator 1 view .LVU1040 + 3206 00be 0028 cmp r0, #0 + 3207 00c0 CCD0 beq .L154 +5101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3208 .loc 1 5101 16 view .LVU1041 + 3209 00c2 0120 movs r0, #1 + 3210 00c4 D3E7 b .L144 + 3211 .LVL254: + 3212 .L166: +5013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3213 .loc 1 5013 3 view .LVU1042 + 3214 00c6 0120 movs r0, #1 + 3215 00c8 D1E7 b .L144 + 3216 .L148: +5036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + ARM GAS /tmp/ccGFzgX3.s page 204 + + + 3217 .loc 1 5036 7 is_stmt 1 view .LVU1043 +5036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 3218 .loc 1 5036 17 is_stmt 0 view .LVU1044 + 3219 00ca 636A ldr r3, [r4, #36] +5036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 3220 .loc 1 5036 52 view .LVU1045 + 3221 00cc 3349 ldr r1, .L167+12 + 3222 00ce D963 str r1, [r3, #60] +5037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3223 .loc 1 5037 7 is_stmt 1 view .LVU1046 +5037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3224 .loc 1 5037 17 is_stmt 0 view .LVU1047 + 3225 00d0 636A ldr r3, [r4, #36] +5037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3226 .loc 1 5037 56 view .LVU1048 + 3227 00d2 3349 ldr r1, .L167+16 + 3228 00d4 1964 str r1, [r3, #64] +5040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3229 .loc 1 5040 7 is_stmt 1 view .LVU1049 +5040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3230 .loc 1 5040 17 is_stmt 0 view .LVU1050 + 3231 00d6 636A ldr r3, [r4, #36] +5040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3232 .loc 1 5040 53 view .LVU1051 + 3233 00d8 2F49 ldr r1, .L167+8 + 3234 00da D964 str r1, [r3, #76] +5043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3235 .loc 1 5043 7 is_stmt 1 view .LVU1052 +5043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3236 .loc 1 5043 71 is_stmt 0 view .LVU1053 + 3237 00dc 2168 ldr r1, [r4] +5043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3238 .loc 1 5043 11 view .LVU1054 + 3239 00de 059B ldr r3, [sp, #20] + 3240 00e0 4C31 adds r1, r1, #76 + 3241 00e2 606A ldr r0, [r4, #36] + 3242 00e4 FFF7FEFF bl HAL_DMA_Start_IT + 3243 .LVL255: +5043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3244 .loc 1 5043 10 discriminator 1 view .LVU1055 + 3245 00e8 0028 cmp r0, #0 + 3246 00ea B7D0 beq .L154 +5047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3247 .loc 1 5047 16 view .LVU1056 + 3248 00ec 0120 movs r0, #1 + 3249 00ee BEE7 b .L144 + 3250 .LVL256: + 3251 .L149: +5054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 3252 .loc 1 5054 7 is_stmt 1 view .LVU1057 +5054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 3253 .loc 1 5054 17 is_stmt 0 view .LVU1058 + 3254 00f0 A36A ldr r3, [r4, #40] +5054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 3255 .loc 1 5054 52 view .LVU1059 + 3256 00f2 2A49 ldr r1, .L167+12 + 3257 00f4 D963 str r1, [r3, #60] + ARM GAS /tmp/ccGFzgX3.s page 205 + + +5055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3258 .loc 1 5055 7 is_stmt 1 view .LVU1060 +5055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3259 .loc 1 5055 17 is_stmt 0 view .LVU1061 + 3260 00f6 A36A ldr r3, [r4, #40] +5055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3261 .loc 1 5055 56 view .LVU1062 + 3262 00f8 2949 ldr r1, .L167+16 + 3263 00fa 1964 str r1, [r3, #64] +5058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3264 .loc 1 5058 7 is_stmt 1 view .LVU1063 +5058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3265 .loc 1 5058 17 is_stmt 0 view .LVU1064 + 3266 00fc A36A ldr r3, [r4, #40] +5058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3267 .loc 1 5058 53 view .LVU1065 + 3268 00fe 2649 ldr r1, .L167+8 + 3269 0100 D964 str r1, [r3, #76] +5061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3270 .loc 1 5061 7 is_stmt 1 view .LVU1066 +5061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3271 .loc 1 5061 71 is_stmt 0 view .LVU1067 + 3272 0102 2168 ldr r1, [r4] +5061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3273 .loc 1 5061 11 view .LVU1068 + 3274 0104 059B ldr r3, [sp, #20] + 3275 0106 4C31 adds r1, r1, #76 + 3276 0108 A06A ldr r0, [r4, #40] + 3277 010a FFF7FEFF bl HAL_DMA_Start_IT + 3278 .LVL257: +5061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3279 .loc 1 5061 10 discriminator 1 view .LVU1069 + 3280 010e 0028 cmp r0, #0 + 3281 0110 A4D0 beq .L154 +5065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3282 .loc 1 5065 16 view .LVU1070 + 3283 0112 0120 movs r0, #1 + 3284 0114 ABE7 b .L144 + 3285 .LVL258: + 3286 .L146: +5072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 3287 .loc 1 5072 7 is_stmt 1 view .LVU1071 +5072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 3288 .loc 1 5072 17 is_stmt 0 view .LVU1072 + 3289 0116 E36A ldr r3, [r4, #44] +5072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 3290 .loc 1 5072 52 view .LVU1073 + 3291 0118 2049 ldr r1, .L167+12 + 3292 011a D963 str r1, [r3, #60] +5073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3293 .loc 1 5073 7 is_stmt 1 view .LVU1074 +5073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3294 .loc 1 5073 17 is_stmt 0 view .LVU1075 + 3295 011c E36A ldr r3, [r4, #44] +5073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3296 .loc 1 5073 56 view .LVU1076 + 3297 011e 2049 ldr r1, .L167+16 + ARM GAS /tmp/ccGFzgX3.s page 206 + + + 3298 0120 1964 str r1, [r3, #64] +5076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3299 .loc 1 5076 7 is_stmt 1 view .LVU1077 +5076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3300 .loc 1 5076 17 is_stmt 0 view .LVU1078 + 3301 0122 E36A ldr r3, [r4, #44] +5076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3302 .loc 1 5076 53 view .LVU1079 + 3303 0124 1C49 ldr r1, .L167+8 + 3304 0126 D964 str r1, [r3, #76] +5079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3305 .loc 1 5079 7 is_stmt 1 view .LVU1080 +5079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3306 .loc 1 5079 71 is_stmt 0 view .LVU1081 + 3307 0128 2168 ldr r1, [r4] +5079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3308 .loc 1 5079 11 view .LVU1082 + 3309 012a 059B ldr r3, [sp, #20] + 3310 012c 4C31 adds r1, r1, #76 + 3311 012e E06A ldr r0, [r4, #44] + 3312 0130 FFF7FEFF bl HAL_DMA_Start_IT + 3313 .LVL259: +5079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3314 .loc 1 5079 10 discriminator 1 view .LVU1083 + 3315 0134 0028 cmp r0, #0 + 3316 0136 91D0 beq .L154 +5083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3317 .loc 1 5083 16 view .LVU1084 + 3318 0138 0120 movs r0, #1 + 3319 013a 98E7 b .L144 + 3320 .LVL260: + 3321 .L151: +5108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + 3322 .loc 1 5108 7 is_stmt 1 view .LVU1085 +5108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + 3323 .loc 1 5108 17 is_stmt 0 view .LVU1086 + 3324 013c 636B ldr r3, [r4, #52] +5108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + 3325 .loc 1 5108 60 view .LVU1087 + 3326 013e 1949 ldr r1, .L167+20 + 3327 0140 D963 str r1, [r3, #60] +5109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3328 .loc 1 5109 7 is_stmt 1 view .LVU1088 +5109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3329 .loc 1 5109 17 is_stmt 0 view .LVU1089 + 3330 0142 636B ldr r3, [r4, #52] +5109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3331 .loc 1 5109 64 view .LVU1090 + 3332 0144 1849 ldr r1, .L167+24 + 3333 0146 1964 str r1, [r3, #64] +5112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3334 .loc 1 5112 7 is_stmt 1 view .LVU1091 +5112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3335 .loc 1 5112 17 is_stmt 0 view .LVU1092 + 3336 0148 636B ldr r3, [r4, #52] +5112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3337 .loc 1 5112 61 view .LVU1093 + ARM GAS /tmp/ccGFzgX3.s page 207 + + + 3338 014a 1349 ldr r1, .L167+8 + 3339 014c D964 str r1, [r3, #76] +5115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3340 .loc 1 5115 7 is_stmt 1 view .LVU1094 +5115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3341 .loc 1 5115 79 is_stmt 0 view .LVU1095 + 3342 014e 2168 ldr r1, [r4] +5115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3343 .loc 1 5115 11 view .LVU1096 + 3344 0150 059B ldr r3, [sp, #20] + 3345 0152 4C31 adds r1, r1, #76 + 3346 0154 606B ldr r0, [r4, #52] + 3347 0156 FFF7FEFF bl HAL_DMA_Start_IT + 3348 .LVL261: +5115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3349 .loc 1 5115 10 discriminator 1 view .LVU1097 + 3350 015a 0028 cmp r0, #0 + 3351 015c 3FF47EAF beq .L154 +5119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3352 .loc 1 5119 16 view .LVU1098 + 3353 0160 0120 movs r0, #1 + 3354 0162 84E7 b .L144 + 3355 .LVL262: + 3356 .L152: +5126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + 3357 .loc 1 5126 7 is_stmt 1 view .LVU1099 +5126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + 3358 .loc 1 5126 17 is_stmt 0 view .LVU1100 + 3359 0164 A36B ldr r3, [r4, #56] +5126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + 3360 .loc 1 5126 56 view .LVU1101 + 3361 0166 1149 ldr r1, .L167+28 + 3362 0168 D963 str r1, [r3, #60] +5127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3363 .loc 1 5127 7 is_stmt 1 view .LVU1102 +5127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3364 .loc 1 5127 17 is_stmt 0 view .LVU1103 + 3365 016a A36B ldr r3, [r4, #56] +5127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3366 .loc 1 5127 60 view .LVU1104 + 3367 016c 1049 ldr r1, .L167+32 + 3368 016e 1964 str r1, [r3, #64] +5130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3369 .loc 1 5130 7 is_stmt 1 view .LVU1105 +5130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3370 .loc 1 5130 17 is_stmt 0 view .LVU1106 + 3371 0170 A36B ldr r3, [r4, #56] +5130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3372 .loc 1 5130 57 view .LVU1107 + 3373 0172 0949 ldr r1, .L167+8 + 3374 0174 D964 str r1, [r3, #76] +5133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3375 .loc 1 5133 7 is_stmt 1 view .LVU1108 +5133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3376 .loc 1 5133 75 is_stmt 0 view .LVU1109 + 3377 0176 2168 ldr r1, [r4] +5133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + ARM GAS /tmp/ccGFzgX3.s page 208 + + + 3378 .loc 1 5133 11 view .LVU1110 + 3379 0178 059B ldr r3, [sp, #20] + 3380 017a 4C31 adds r1, r1, #76 + 3381 017c A06B ldr r0, [r4, #56] + 3382 017e FFF7FEFF bl HAL_DMA_Start_IT + 3383 .LVL263: +5133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** DataLength) != HAL_OK) + 3384 .loc 1 5133 10 discriminator 1 view .LVU1111 + 3385 0182 0028 cmp r0, #0 + 3386 0184 3FF46AAF beq .L154 +5137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3387 .loc 1 5137 16 view .LVU1112 + 3388 0188 0120 movs r0, #1 + 3389 018a 70E7 b .L144 + 3390 .L165: +5029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3391 .loc 1 5029 16 view .LVU1113 + 3392 018c 0120 movs r0, #1 + 3393 018e 6EE7 b .L144 + 3394 .L168: + 3395 .align 2 + 3396 .L167: + 3397 0190 00000000 .word TIM_DMAPeriodElapsedCplt + 3398 0194 00000000 .word TIM_DMAPeriodElapsedHalfCplt + 3399 0198 00000000 .word TIM_DMAError + 3400 019c 00000000 .word TIM_DMACaptureCplt + 3401 01a0 00000000 .word TIM_DMACaptureHalfCplt + 3402 01a4 00000000 .word TIMEx_DMACommutationCplt + 3403 01a8 00000000 .word TIMEx_DMACommutationHalfCplt + 3404 01ac 00000000 .word TIM_DMATriggerCplt + 3405 01b0 00000000 .word TIM_DMATriggerHalfCplt + 3406 .cfi_endproc + 3407 .LFE208: + 3409 .section .text.HAL_TIM_DMABurst_ReadStart,"ax",%progbits + 3410 .align 1 + 3411 .global HAL_TIM_DMABurst_ReadStart + 3412 .syntax unified + 3413 .thumb + 3414 .thumb_func + 3416 HAL_TIM_DMABurst_ReadStart: + 3417 .LVL264: + 3418 .LFB207: +4925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status; + 3419 .loc 1 4925 1 is_stmt 1 view -0 + 3420 .cfi_startproc + 3421 @ args = 4, pretend = 0, frame = 0 + 3422 @ frame_needed = 0, uses_anonymous_args = 0 +4925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status; + 3423 .loc 1 4925 1 is_stmt 0 view .LVU1115 + 3424 0000 30B5 push {r4, r5, lr} + 3425 .LCFI34: + 3426 .cfi_def_cfa_offset 12 + 3427 .cfi_offset 4, -12 + 3428 .cfi_offset 5, -8 + 3429 .cfi_offset 14, -4 + 3430 0002 83B0 sub sp, sp, #12 + 3431 .LCFI35: + ARM GAS /tmp/ccGFzgX3.s page 209 + + + 3432 .cfi_def_cfa_offset 24 + 3433 0004 069D ldr r5, [sp, #24] +4926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3434 .loc 1 4926 3 is_stmt 1 view .LVU1116 +4928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ((BurstLength) >> 8U) + 1U); + 3435 .loc 1 4928 3 view .LVU1117 +4929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3436 .loc 1 4929 59 is_stmt 0 view .LVU1118 + 3437 0006 2C0A lsrs r4, r5, #8 +4928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ((BurstLength) >> 8U) + 1U); + 3438 .loc 1 4928 12 view .LVU1119 + 3439 0008 0134 adds r4, r4, #1 + 3440 000a 0194 str r4, [sp, #4] + 3441 000c 0095 str r5, [sp] + 3442 000e FFF7FEFF bl HAL_TIM_DMABurst_MultiReadStart + 3443 .LVL265: +4932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3444 .loc 1 4932 3 is_stmt 1 view .LVU1120 +4933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3445 .loc 1 4933 1 is_stmt 0 view .LVU1121 + 3446 0012 03B0 add sp, sp, #12 + 3447 .LCFI36: + 3448 .cfi_def_cfa_offset 12 + 3449 @ sp needed + 3450 0014 30BD pop {r4, r5, pc} +4933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3451 .loc 1 4933 1 view .LVU1122 + 3452 .cfi_endproc + 3453 .LFE207: + 3455 .section .text.HAL_TIM_DMABurst_ReadStop,"ax",%progbits + 3456 .align 1 + 3457 .global HAL_TIM_DMABurst_ReadStop + 3458 .syntax unified + 3459 .thumb + 3460 .thumb_func + 3462 HAL_TIM_DMABurst_ReadStop: + 3463 .LVL266: + 3464 .LFB209: +5166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 3465 .loc 1 5166 1 is_stmt 1 view -0 + 3466 .cfi_startproc + 3467 @ args = 0, pretend = 0, frame = 0 + 3468 @ frame_needed = 0, uses_anonymous_args = 0 +5166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 3469 .loc 1 5166 1 is_stmt 0 view .LVU1124 + 3470 0000 38B5 push {r3, r4, r5, lr} + 3471 .LCFI37: + 3472 .cfi_def_cfa_offset 16 + 3473 .cfi_offset 3, -16 + 3474 .cfi_offset 4, -12 + 3475 .cfi_offset 5, -8 + 3476 .cfi_offset 14, -4 + 3477 0002 0546 mov r5, r0 + 3478 0004 0C46 mov r4, r1 +5167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3479 .loc 1 5167 3 is_stmt 1 view .LVU1125 + 3480 .LVL267: + ARM GAS /tmp/ccGFzgX3.s page 210 + + +5170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3481 .loc 1 5170 3 view .LVU1126 +5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3482 .loc 1 5173 3 view .LVU1127 + 3483 0006 B1F5006F cmp r1, #2048 + 3484 000a 2FD0 beq .L172 + 3485 000c 17D8 bhi .L173 + 3486 000e B1F5007F cmp r1, #512 + 3487 0012 23D0 beq .L174 + 3488 0014 B1F5806F cmp r1, #1024 + 3489 0018 24D0 beq .L175 + 3490 001a B1F5807F cmp r1, #256 + 3491 001e 0CD1 bne .L183 +5177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3492 .loc 1 5177 7 view .LVU1128 +5177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3493 .loc 1 5177 13 is_stmt 0 view .LVU1129 + 3494 0020 006A ldr r0, [r0, #32] + 3495 .LVL268: +5177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3496 .loc 1 5177 13 view .LVU1130 + 3497 0022 FFF7FEFF bl HAL_DMA_Abort_IT + 3498 .LVL269: +5178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3499 .loc 1 5178 7 is_stmt 1 view .LVU1131 +5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3500 .loc 1 5215 3 view .LVU1132 + 3501 .L181: +5218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3502 .loc 1 5218 5 view .LVU1133 + 3503 0026 2A68 ldr r2, [r5] + 3504 0028 D368 ldr r3, [r2, #12] + 3505 002a 23EA0403 bic r3, r3, r4 + 3506 002e D360 str r3, [r2, #12] +5221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3507 .loc 1 5221 5 view .LVU1134 +5221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3508 .loc 1 5221 25 is_stmt 0 view .LVU1135 + 3509 0030 0123 movs r3, #1 + 3510 0032 85F84830 strb r3, [r5, #72] + 3511 0036 0020 movs r0, #0 + 3512 .L177: + 3513 .LVL270: +5225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3514 .loc 1 5225 3 is_stmt 1 view .LVU1136 +5226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3515 .loc 1 5226 1 is_stmt 0 view .LVU1137 + 3516 0038 38BD pop {r3, r4, r5, pc} + 3517 .LVL271: + 3518 .L183: +5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3519 .loc 1 5173 3 view .LVU1138 + 3520 003a 0120 movs r0, #1 + 3521 .LVL272: +5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3522 .loc 1 5173 3 view .LVU1139 + 3523 003c FCE7 b .L177 + ARM GAS /tmp/ccGFzgX3.s page 211 + + + 3524 .LVL273: + 3525 .L173: +5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3526 .loc 1 5173 3 view .LVU1140 + 3527 003e B1F5005F cmp r1, #8192 + 3528 0042 17D0 beq .L178 + 3529 0044 B1F5804F cmp r1, #16384 + 3530 0048 18D0 beq .L179 + 3531 004a B1F5805F cmp r1, #4096 + 3532 004e 03D1 bne .L184 +5197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3533 .loc 1 5197 7 is_stmt 1 view .LVU1141 +5197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3534 .loc 1 5197 13 is_stmt 0 view .LVU1142 + 3535 0050 006B ldr r0, [r0, #48] + 3536 .LVL274: +5197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3537 .loc 1 5197 13 view .LVU1143 + 3538 0052 FFF7FEFF bl HAL_DMA_Abort_IT + 3539 .LVL275: +5198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3540 .loc 1 5198 7 is_stmt 1 view .LVU1144 +5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3541 .loc 1 5215 3 view .LVU1145 + 3542 0056 E6E7 b .L181 + 3543 .LVL276: + 3544 .L184: +5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3545 .loc 1 5173 3 is_stmt 0 view .LVU1146 + 3546 0058 0120 movs r0, #1 + 3547 .LVL277: +5173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3548 .loc 1 5173 3 view .LVU1147 + 3549 005a EDE7 b .L177 + 3550 .LVL278: + 3551 .L174: +5182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3552 .loc 1 5182 7 is_stmt 1 view .LVU1148 +5182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3553 .loc 1 5182 13 is_stmt 0 view .LVU1149 + 3554 005c 406A ldr r0, [r0, #36] + 3555 .LVL279: +5182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3556 .loc 1 5182 13 view .LVU1150 + 3557 005e FFF7FEFF bl HAL_DMA_Abort_IT + 3558 .LVL280: +5183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3559 .loc 1 5183 7 is_stmt 1 view .LVU1151 +5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3560 .loc 1 5215 3 view .LVU1152 + 3561 0062 E0E7 b .L181 + 3562 .LVL281: + 3563 .L175: +5187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3564 .loc 1 5187 7 view .LVU1153 +5187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3565 .loc 1 5187 13 is_stmt 0 view .LVU1154 + ARM GAS /tmp/ccGFzgX3.s page 212 + + + 3566 0064 806A ldr r0, [r0, #40] + 3567 .LVL282: +5187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3568 .loc 1 5187 13 view .LVU1155 + 3569 0066 FFF7FEFF bl HAL_DMA_Abort_IT + 3570 .LVL283: +5188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3571 .loc 1 5188 7 is_stmt 1 view .LVU1156 +5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3572 .loc 1 5215 3 view .LVU1157 + 3573 006a DCE7 b .L181 + 3574 .LVL284: + 3575 .L172: +5192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3576 .loc 1 5192 7 view .LVU1158 +5192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3577 .loc 1 5192 13 is_stmt 0 view .LVU1159 + 3578 006c C06A ldr r0, [r0, #44] + 3579 .LVL285: +5192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3580 .loc 1 5192 13 view .LVU1160 + 3581 006e FFF7FEFF bl HAL_DMA_Abort_IT + 3582 .LVL286: +5193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3583 .loc 1 5193 7 is_stmt 1 view .LVU1161 +5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3584 .loc 1 5215 3 view .LVU1162 + 3585 0072 D8E7 b .L181 + 3586 .LVL287: + 3587 .L178: +5202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3588 .loc 1 5202 7 view .LVU1163 +5202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3589 .loc 1 5202 13 is_stmt 0 view .LVU1164 + 3590 0074 406B ldr r0, [r0, #52] + 3591 .LVL288: +5202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3592 .loc 1 5202 13 view .LVU1165 + 3593 0076 FFF7FEFF bl HAL_DMA_Abort_IT + 3594 .LVL289: +5203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3595 .loc 1 5203 7 is_stmt 1 view .LVU1166 +5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3596 .loc 1 5215 3 view .LVU1167 + 3597 007a D4E7 b .L181 + 3598 .LVL290: + 3599 .L179: +5207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3600 .loc 1 5207 7 view .LVU1168 +5207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3601 .loc 1 5207 13 is_stmt 0 view .LVU1169 + 3602 007c 806B ldr r0, [r0, #56] + 3603 .LVL291: +5207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 3604 .loc 1 5207 13 view .LVU1170 + 3605 007e FFF7FEFF bl HAL_DMA_Abort_IT + 3606 .LVL292: + ARM GAS /tmp/ccGFzgX3.s page 213 + + +5208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3607 .loc 1 5208 7 is_stmt 1 view .LVU1171 +5215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3608 .loc 1 5215 3 view .LVU1172 + 3609 0082 D0E7 b .L181 + 3610 .cfi_endproc + 3611 .LFE209: + 3613 .section .text.HAL_TIM_GenerateEvent,"ax",%progbits + 3614 .align 1 + 3615 .global HAL_TIM_GenerateEvent + 3616 .syntax unified + 3617 .thumb + 3618 .thumb_func + 3620 HAL_TIM_GenerateEvent: + 3621 .LVL293: + 3622 .LFB210: +5250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 3623 .loc 1 5250 1 view -0 + 3624 .cfi_startproc + 3625 @ args = 0, pretend = 0, frame = 0 + 3626 @ frame_needed = 0, uses_anonymous_args = 0 + 3627 @ link register save eliminated. +5252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + 3628 .loc 1 5252 3 view .LVU1174 +5253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3629 .loc 1 5253 3 view .LVU1175 +5256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3630 .loc 1 5256 3 view .LVU1176 +5256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3631 .loc 1 5256 3 view .LVU1177 + 3632 0000 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 3633 0004 012B cmp r3, #1 + 3634 0006 0ED0 beq .L187 +5256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3635 .loc 1 5256 3 discriminator 2 view .LVU1178 + 3636 0008 0123 movs r3, #1 + 3637 000a 80F83C30 strb r3, [r0, #60] +5256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3638 .loc 1 5256 3 discriminator 2 view .LVU1179 +5259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3639 .loc 1 5259 3 view .LVU1180 +5259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3640 .loc 1 5259 15 is_stmt 0 view .LVU1181 + 3641 000e 0222 movs r2, #2 + 3642 0010 80F83D20 strb r2, [r0, #61] +5262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3643 .loc 1 5262 3 is_stmt 1 view .LVU1182 +5262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3644 .loc 1 5262 7 is_stmt 0 view .LVU1183 + 3645 0014 0268 ldr r2, [r0] +5262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3646 .loc 1 5262 23 view .LVU1184 + 3647 0016 5161 str r1, [r2, #20] +5265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3648 .loc 1 5265 3 is_stmt 1 view .LVU1185 +5265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3649 .loc 1 5265 15 is_stmt 0 view .LVU1186 + ARM GAS /tmp/ccGFzgX3.s page 214 + + + 3650 0018 80F83D30 strb r3, [r0, #61] +5267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3651 .loc 1 5267 3 is_stmt 1 view .LVU1187 +5267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3652 .loc 1 5267 3 view .LVU1188 + 3653 001c 0023 movs r3, #0 + 3654 001e 80F83C30 strb r3, [r0, #60] +5267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3655 .loc 1 5267 3 view .LVU1189 +5270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3656 .loc 1 5270 3 view .LVU1190 +5270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3657 .loc 1 5270 10 is_stmt 0 view .LVU1191 + 3658 0022 1846 mov r0, r3 + 3659 .LVL294: +5270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3660 .loc 1 5270 10 view .LVU1192 + 3661 0024 7047 bx lr + 3662 .LVL295: + 3663 .L187: +5256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3664 .loc 1 5256 3 discriminator 1 view .LVU1193 + 3665 0026 0220 movs r0, #2 + 3666 .LVL296: +5271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3667 .loc 1 5271 1 view .LVU1194 + 3668 0028 7047 bx lr + 3669 .cfi_endproc + 3670 .LFE210: + 3672 .section .text.HAL_TIM_ConfigTI1Input,"ax",%progbits + 3673 .align 1 + 3674 .global HAL_TIM_ConfigTI1Input + 3675 .syntax unified + 3676 .thumb + 3677 .thumb_func + 3679 HAL_TIM_ConfigTI1Input: + 3680 .LVL297: + 3681 .LFB213: +5601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpcr2; + 3682 .loc 1 5601 1 is_stmt 1 view -0 + 3683 .cfi_startproc + 3684 @ args = 0, pretend = 0, frame = 0 + 3685 @ frame_needed = 0, uses_anonymous_args = 0 + 3686 @ link register save eliminated. +5602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3687 .loc 1 5602 3 view .LVU1196 +5605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + 3688 .loc 1 5605 3 view .LVU1197 +5606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3689 .loc 1 5606 3 view .LVU1198 +5609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3690 .loc 1 5609 3 view .LVU1199 +5609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3691 .loc 1 5609 16 is_stmt 0 view .LVU1200 + 3692 0000 0268 ldr r2, [r0] +5609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3693 .loc 1 5609 10 view .LVU1201 + ARM GAS /tmp/ccGFzgX3.s page 215 + + + 3694 0002 5368 ldr r3, [r2, #4] + 3695 .LVL298: +5612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3696 .loc 1 5612 3 is_stmt 1 view .LVU1202 +5612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3697 .loc 1 5612 10 is_stmt 0 view .LVU1203 + 3698 0004 23F08003 bic r3, r3, #128 + 3699 .LVL299: +5615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3700 .loc 1 5615 3 is_stmt 1 view .LVU1204 +5615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3701 .loc 1 5615 10 is_stmt 0 view .LVU1205 + 3702 0008 0B43 orrs r3, r3, r1 + 3703 .LVL300: +5618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3704 .loc 1 5618 3 is_stmt 1 view .LVU1206 +5618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3705 .loc 1 5618 23 is_stmt 0 view .LVU1207 + 3706 000a 5360 str r3, [r2, #4] +5620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3707 .loc 1 5620 3 is_stmt 1 view .LVU1208 +5621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3708 .loc 1 5621 1 is_stmt 0 view .LVU1209 + 3709 000c 0020 movs r0, #0 + 3710 .LVL301: +5621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3711 .loc 1 5621 1 view .LVU1210 + 3712 000e 7047 bx lr + 3713 .cfi_endproc + 3714 .LFE213: + 3716 .section .text.HAL_TIM_ReadCapturedValue,"ax",%progbits + 3717 .align 1 + 3718 .global HAL_TIM_ReadCapturedValue + 3719 .syntax unified + 3720 .thumb + 3721 .thumb_func + 3723 HAL_TIM_ReadCapturedValue: + 3724 .LVL302: + 3725 .LFB216: +5716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpreg = 0U; + 3726 .loc 1 5716 1 is_stmt 1 view -0 + 3727 .cfi_startproc + 3728 @ args = 0, pretend = 0, frame = 0 + 3729 @ frame_needed = 0, uses_anonymous_args = 0 + 3730 @ link register save eliminated. +5717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3731 .loc 1 5717 3 view .LVU1212 +5719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3732 .loc 1 5719 3 view .LVU1213 + 3733 0000 0C29 cmp r1, #12 + 3734 0002 14D8 bhi .L196 + 3735 0004 DFE801F0 tbb [pc, r1] + 3736 .L192: + 3737 0008 07 .byte (.L195-.L192)/2 + 3738 0009 13 .byte (.L196-.L192)/2 + 3739 000a 13 .byte (.L196-.L192)/2 + 3740 000b 13 .byte (.L196-.L192)/2 + ARM GAS /tmp/ccGFzgX3.s page 216 + + + 3741 000c 0A .byte (.L194-.L192)/2 + 3742 000d 13 .byte (.L196-.L192)/2 + 3743 000e 13 .byte (.L196-.L192)/2 + 3744 000f 13 .byte (.L196-.L192)/2 + 3745 0010 0D .byte (.L193-.L192)/2 + 3746 0011 13 .byte (.L196-.L192)/2 + 3747 0012 13 .byte (.L196-.L192)/2 + 3748 0013 13 .byte (.L196-.L192)/2 + 3749 0014 10 .byte (.L191-.L192)/2 + 3750 0015 00 .p2align 1 + 3751 .L195: +5724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3752 .loc 1 5724 7 view .LVU1214 +5727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3753 .loc 1 5727 7 view .LVU1215 +5727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3754 .loc 1 5727 21 is_stmt 0 view .LVU1216 + 3755 0016 0368 ldr r3, [r0] +5727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3756 .loc 1 5727 14 view .LVU1217 + 3757 0018 586B ldr r0, [r3, #52] + 3758 .LVL303: +5729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3759 .loc 1 5729 7 is_stmt 1 view .LVU1218 + 3760 001a 7047 bx lr + 3761 .LVL304: + 3762 .L194: +5734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3763 .loc 1 5734 7 view .LVU1219 +5737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3764 .loc 1 5737 7 view .LVU1220 +5737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3765 .loc 1 5737 22 is_stmt 0 view .LVU1221 + 3766 001c 0368 ldr r3, [r0] +5737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3767 .loc 1 5737 14 view .LVU1222 + 3768 001e 986B ldr r0, [r3, #56] + 3769 .LVL305: +5739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3770 .loc 1 5739 7 is_stmt 1 view .LVU1223 + 3771 0020 7047 bx lr + 3772 .LVL306: + 3773 .L193: +5745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3774 .loc 1 5745 7 view .LVU1224 +5748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3775 .loc 1 5748 7 view .LVU1225 +5748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3776 .loc 1 5748 22 is_stmt 0 view .LVU1226 + 3777 0022 0368 ldr r3, [r0] +5748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3778 .loc 1 5748 14 view .LVU1227 + 3779 0024 D86B ldr r0, [r3, #60] + 3780 .LVL307: +5750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3781 .loc 1 5750 7 is_stmt 1 view .LVU1228 + 3782 0026 7047 bx lr + ARM GAS /tmp/ccGFzgX3.s page 217 + + + 3783 .LVL308: + 3784 .L191: +5756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3785 .loc 1 5756 7 view .LVU1229 +5759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3786 .loc 1 5759 7 view .LVU1230 +5759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3787 .loc 1 5759 22 is_stmt 0 view .LVU1231 + 3788 0028 0368 ldr r3, [r0] +5759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3789 .loc 1 5759 14 view .LVU1232 + 3790 002a 186C ldr r0, [r3, #64] + 3791 .LVL309: +5761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3792 .loc 1 5761 7 is_stmt 1 view .LVU1233 + 3793 002c 7047 bx lr + 3794 .LVL310: + 3795 .L196: +5719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3796 .loc 1 5719 3 is_stmt 0 view .LVU1234 + 3797 002e 0020 movs r0, #0 + 3798 .LVL311: +5768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3799 .loc 1 5768 3 is_stmt 1 view .LVU1235 +5769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3800 .loc 1 5769 1 is_stmt 0 view .LVU1236 + 3801 0030 7047 bx lr + 3802 .cfi_endproc + 3803 .LFE216: + 3805 .section .text.HAL_TIM_PeriodElapsedCallback,"ax",%progbits + 3806 .align 1 + 3807 .weak HAL_TIM_PeriodElapsedCallback + 3808 .syntax unified + 3809 .thumb + 3810 .thumb_func + 3812 HAL_TIM_PeriodElapsedCallback: + 3813 .LVL312: + 3814 .LFB217: +5800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 3815 .loc 1 5800 1 is_stmt 1 view -0 + 3816 .cfi_startproc + 3817 @ args = 0, pretend = 0, frame = 0 + 3818 @ frame_needed = 0, uses_anonymous_args = 0 + 3819 @ link register save eliminated. +5802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3820 .loc 1 5802 3 view .LVU1238 +5807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3821 .loc 1 5807 1 is_stmt 0 view .LVU1239 + 3822 0000 7047 bx lr + 3823 .cfi_endproc + 3824 .LFE217: + 3826 .section .text.TIM_DMAPeriodElapsedCplt,"ax",%progbits + 3827 .align 1 + 3828 .syntax unified + 3829 .thumb + 3830 .thumb_func + 3832 TIM_DMAPeriodElapsedCplt: + ARM GAS /tmp/ccGFzgX3.s page 218 + + + 3833 .LVL313: + 3834 .LFB241: +6856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 3835 .loc 1 6856 1 is_stmt 1 view -0 + 3836 .cfi_startproc + 3837 @ args = 0, pretend = 0, frame = 0 + 3838 @ frame_needed = 0, uses_anonymous_args = 0 +6856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 3839 .loc 1 6856 1 is_stmt 0 view .LVU1241 + 3840 0000 08B5 push {r3, lr} + 3841 .LCFI38: + 3842 .cfi_def_cfa_offset 8 + 3843 .cfi_offset 3, -8 + 3844 .cfi_offset 14, -4 +6857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3845 .loc 1 6857 3 is_stmt 1 view .LVU1242 +6857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3846 .loc 1 6857 22 is_stmt 0 view .LVU1243 + 3847 0002 806B ldr r0, [r0, #56] + 3848 .LVL314: +6859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3849 .loc 1 6859 3 is_stmt 1 view .LVU1244 +6859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3850 .loc 1 6859 17 is_stmt 0 view .LVU1245 + 3851 0004 036A ldr r3, [r0, #32] +6859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3852 .loc 1 6859 42 view .LVU1246 + 3853 0006 DB69 ldr r3, [r3, #28] +6859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3854 .loc 1 6859 6 view .LVU1247 + 3855 0008 13B9 cbnz r3, .L199 +6861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3856 .loc 1 6861 5 is_stmt 1 view .LVU1248 +6861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 3857 .loc 1 6861 17 is_stmt 0 view .LVU1249 + 3858 000a 0123 movs r3, #1 + 3859 000c 80F83D30 strb r3, [r0, #61] + 3860 .L199: +6867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 3861 .loc 1 6867 3 is_stmt 1 view .LVU1250 + 3862 0010 FFF7FEFF bl HAL_TIM_PeriodElapsedCallback + 3863 .LVL315: +6869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3864 .loc 1 6869 1 is_stmt 0 view .LVU1251 + 3865 0014 08BD pop {r3, pc} + 3866 .cfi_endproc + 3867 .LFE241: + 3869 .section .text.HAL_TIM_PeriodElapsedHalfCpltCallback,"ax",%progbits + 3870 .align 1 + 3871 .weak HAL_TIM_PeriodElapsedHalfCpltCallback + 3872 .syntax unified + 3873 .thumb + 3874 .thumb_func + 3876 HAL_TIM_PeriodElapsedHalfCpltCallback: + 3877 .LVL316: + 3878 .LFB218: +5815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + ARM GAS /tmp/ccGFzgX3.s page 219 + + + 3879 .loc 1 5815 1 is_stmt 1 view -0 + 3880 .cfi_startproc + 3881 @ args = 0, pretend = 0, frame = 0 + 3882 @ frame_needed = 0, uses_anonymous_args = 0 + 3883 @ link register save eliminated. +5817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3884 .loc 1 5817 3 view .LVU1253 +5822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3885 .loc 1 5822 1 is_stmt 0 view .LVU1254 + 3886 0000 7047 bx lr + 3887 .cfi_endproc + 3888 .LFE218: + 3890 .section .text.TIM_DMAPeriodElapsedHalfCplt,"ax",%progbits + 3891 .align 1 + 3892 .syntax unified + 3893 .thumb + 3894 .thumb_func + 3896 TIM_DMAPeriodElapsedHalfCplt: + 3897 .LVL317: + 3898 .LFB242: +6877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 3899 .loc 1 6877 1 is_stmt 1 view -0 + 3900 .cfi_startproc + 3901 @ args = 0, pretend = 0, frame = 0 + 3902 @ frame_needed = 0, uses_anonymous_args = 0 +6877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 3903 .loc 1 6877 1 is_stmt 0 view .LVU1256 + 3904 0000 08B5 push {r3, lr} + 3905 .LCFI39: + 3906 .cfi_def_cfa_offset 8 + 3907 .cfi_offset 3, -8 + 3908 .cfi_offset 14, -4 +6878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3909 .loc 1 6878 3 is_stmt 1 view .LVU1257 + 3910 .LVL318: +6883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 3911 .loc 1 6883 3 view .LVU1258 + 3912 0002 806B ldr r0, [r0, #56] + 3913 .LVL319: +6883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 3914 .loc 1 6883 3 is_stmt 0 view .LVU1259 + 3915 0004 FFF7FEFF bl HAL_TIM_PeriodElapsedHalfCpltCallback + 3916 .LVL320: +6885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3917 .loc 1 6885 1 view .LVU1260 + 3918 0008 08BD pop {r3, pc} + 3919 .cfi_endproc + 3920 .LFE242: + 3922 .section .text.HAL_TIM_OC_DelayElapsedCallback,"ax",%progbits + 3923 .align 1 + 3924 .weak HAL_TIM_OC_DelayElapsedCallback + 3925 .syntax unified + 3926 .thumb + 3927 .thumb_func + 3929 HAL_TIM_OC_DelayElapsedCallback: + 3930 .LVL321: + 3931 .LFB219: + ARM GAS /tmp/ccGFzgX3.s page 220 + + +5830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 3932 .loc 1 5830 1 is_stmt 1 view -0 + 3933 .cfi_startproc + 3934 @ args = 0, pretend = 0, frame = 0 + 3935 @ frame_needed = 0, uses_anonymous_args = 0 + 3936 @ link register save eliminated. +5832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3937 .loc 1 5832 3 view .LVU1262 +5837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3938 .loc 1 5837 1 is_stmt 0 view .LVU1263 + 3939 0000 7047 bx lr + 3940 .cfi_endproc + 3941 .LFE219: + 3943 .section .text.HAL_TIM_IC_CaptureCallback,"ax",%progbits + 3944 .align 1 + 3945 .weak HAL_TIM_IC_CaptureCallback + 3946 .syntax unified + 3947 .thumb + 3948 .thumb_func + 3950 HAL_TIM_IC_CaptureCallback: + 3951 .LVL322: + 3952 .LFB220: +5845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 3953 .loc 1 5845 1 is_stmt 1 view -0 + 3954 .cfi_startproc + 3955 @ args = 0, pretend = 0, frame = 0 + 3956 @ frame_needed = 0, uses_anonymous_args = 0 + 3957 @ link register save eliminated. +5847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3958 .loc 1 5847 3 view .LVU1265 +5852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3959 .loc 1 5852 1 is_stmt 0 view .LVU1266 + 3960 0000 7047 bx lr + 3961 .cfi_endproc + 3962 .LFE220: + 3964 .section .text.TIM_DMACaptureCplt,"ax",%progbits + 3965 .align 1 + 3966 .global TIM_DMACaptureCplt + 3967 .syntax unified + 3968 .thumb + 3969 .thumb_func + 3971 TIM_DMACaptureCplt: + 3972 .LVL323: + 3973 .LFB239: +6754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 3974 .loc 1 6754 1 is_stmt 1 view -0 + 3975 .cfi_startproc + 3976 @ args = 0, pretend = 0, frame = 0 + 3977 @ frame_needed = 0, uses_anonymous_args = 0 +6754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 3978 .loc 1 6754 1 is_stmt 0 view .LVU1268 + 3979 0000 10B5 push {r4, lr} + 3980 .LCFI40: + 3981 .cfi_def_cfa_offset 8 + 3982 .cfi_offset 4, -8 + 3983 .cfi_offset 14, -4 +6755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 221 + + + 3984 .loc 1 6755 3 is_stmt 1 view .LVU1269 +6755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 3985 .loc 1 6755 22 is_stmt 0 view .LVU1270 + 3986 0002 846B ldr r4, [r0, #56] + 3987 .LVL324: +6757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3988 .loc 1 6757 3 is_stmt 1 view .LVU1271 +6757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3989 .loc 1 6757 25 is_stmt 0 view .LVU1272 + 3990 0004 636A ldr r3, [r4, #36] +6757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3991 .loc 1 6757 6 view .LVU1273 + 3992 0006 8342 cmp r3, r0 + 3993 0008 0ED0 beq .L212 +6767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3994 .loc 1 6767 8 is_stmt 1 view .LVU1274 +6767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3995 .loc 1 6767 30 is_stmt 0 view .LVU1275 + 3996 000a A36A ldr r3, [r4, #40] +6767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 3997 .loc 1 6767 11 view .LVU1276 + 3998 000c 8342 cmp r3, r0 + 3999 000e 16D0 beq .L213 +6777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4000 .loc 1 6777 8 is_stmt 1 view .LVU1277 +6777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4001 .loc 1 6777 30 is_stmt 0 view .LVU1278 + 4002 0010 E36A ldr r3, [r4, #44] +6777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4003 .loc 1 6777 11 view .LVU1279 + 4004 0012 8342 cmp r3, r0 + 4005 0014 1ED0 beq .L214 +6787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4006 .loc 1 6787 8 is_stmt 1 view .LVU1280 +6787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4007 .loc 1 6787 30 is_stmt 0 view .LVU1281 + 4008 0016 236B ldr r3, [r4, #48] +6787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4009 .loc 1 6787 11 view .LVU1282 + 4010 0018 8342 cmp r3, r0 + 4011 001a 26D0 beq .L215 + 4012 .L208: +6800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4013 .loc 1 6800 3 is_stmt 1 view .LVU1283 +6805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4014 .loc 1 6805 3 view .LVU1284 + 4015 001c 2046 mov r0, r4 + 4016 .LVL325: +6805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4017 .loc 1 6805 3 is_stmt 0 view .LVU1285 + 4018 001e FFF7FEFF bl HAL_TIM_IC_CaptureCallback + 4019 .LVL326: +6808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4020 .loc 1 6808 3 is_stmt 1 view .LVU1286 +6808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4021 .loc 1 6808 17 is_stmt 0 view .LVU1287 + 4022 0022 0023 movs r3, #0 + ARM GAS /tmp/ccGFzgX3.s page 222 + + + 4023 0024 2377 strb r3, [r4, #28] +6809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4024 .loc 1 6809 1 view .LVU1288 + 4025 0026 10BD pop {r4, pc} + 4026 .LVL327: + 4027 .L212: +6759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4028 .loc 1 6759 5 is_stmt 1 view .LVU1289 +6759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4029 .loc 1 6759 19 is_stmt 0 view .LVU1290 + 4030 0028 0123 movs r3, #1 + 4031 002a 2377 strb r3, [r4, #28] +6761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4032 .loc 1 6761 5 is_stmt 1 view .LVU1291 +6761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4033 .loc 1 6761 19 is_stmt 0 view .LVU1292 + 4034 002c C369 ldr r3, [r0, #28] +6761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4035 .loc 1 6761 8 view .LVU1293 + 4036 002e 002B cmp r3, #0 + 4037 0030 F4D1 bne .L208 +6763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 4038 .loc 1 6763 7 is_stmt 1 view .LVU1294 + 4039 0032 0123 movs r3, #1 + 4040 0034 84F83E30 strb r3, [r4, #62] +6764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4041 .loc 1 6764 7 view .LVU1295 + 4042 0038 84F84430 strb r3, [r4, #68] + 4043 003c EEE7 b .L208 + 4044 .L213: +6769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4045 .loc 1 6769 5 view .LVU1296 +6769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4046 .loc 1 6769 19 is_stmt 0 view .LVU1297 + 4047 003e 0223 movs r3, #2 + 4048 0040 2377 strb r3, [r4, #28] +6771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4049 .loc 1 6771 5 is_stmt 1 view .LVU1298 +6771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4050 .loc 1 6771 19 is_stmt 0 view .LVU1299 + 4051 0042 C369 ldr r3, [r0, #28] +6771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4052 .loc 1 6771 8 view .LVU1300 + 4053 0044 002B cmp r3, #0 + 4054 0046 E9D1 bne .L208 +6773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 4055 .loc 1 6773 7 is_stmt 1 view .LVU1301 + 4056 0048 0123 movs r3, #1 + 4057 004a 84F83F30 strb r3, [r4, #63] +6774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4058 .loc 1 6774 7 view .LVU1302 + 4059 004e 84F84530 strb r3, [r4, #69] + 4060 0052 E3E7 b .L208 + 4061 .L214: +6779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4062 .loc 1 6779 5 view .LVU1303 +6779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 223 + + + 4063 .loc 1 6779 19 is_stmt 0 view .LVU1304 + 4064 0054 0423 movs r3, #4 + 4065 0056 2377 strb r3, [r4, #28] +6781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4066 .loc 1 6781 5 is_stmt 1 view .LVU1305 +6781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4067 .loc 1 6781 19 is_stmt 0 view .LVU1306 + 4068 0058 C369 ldr r3, [r0, #28] +6781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4069 .loc 1 6781 8 view .LVU1307 + 4070 005a 002B cmp r3, #0 + 4071 005c DED1 bne .L208 +6783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + 4072 .loc 1 6783 7 is_stmt 1 view .LVU1308 + 4073 005e 0123 movs r3, #1 + 4074 0060 84F84030 strb r3, [r4, #64] +6784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4075 .loc 1 6784 7 view .LVU1309 + 4076 0064 84F84630 strb r3, [r4, #70] + 4077 0068 D8E7 b .L208 + 4078 .L215: +6789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4079 .loc 1 6789 5 view .LVU1310 +6789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4080 .loc 1 6789 19 is_stmt 0 view .LVU1311 + 4081 006a 0823 movs r3, #8 + 4082 006c 2377 strb r3, [r4, #28] +6791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4083 .loc 1 6791 5 is_stmt 1 view .LVU1312 +6791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4084 .loc 1 6791 19 is_stmt 0 view .LVU1313 + 4085 006e C369 ldr r3, [r0, #28] +6791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4086 .loc 1 6791 8 view .LVU1314 + 4087 0070 002B cmp r3, #0 + 4088 0072 D3D1 bne .L208 +6793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + 4089 .loc 1 6793 7 is_stmt 1 view .LVU1315 + 4090 0074 0123 movs r3, #1 + 4091 0076 84F84130 strb r3, [r4, #65] +6794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4092 .loc 1 6794 7 view .LVU1316 + 4093 007a 84F84730 strb r3, [r4, #71] + 4094 007e CDE7 b .L208 + 4095 .cfi_endproc + 4096 .LFE239: + 4098 .section .text.HAL_TIM_IC_CaptureHalfCpltCallback,"ax",%progbits + 4099 .align 1 + 4100 .weak HAL_TIM_IC_CaptureHalfCpltCallback + 4101 .syntax unified + 4102 .thumb + 4103 .thumb_func + 4105 HAL_TIM_IC_CaptureHalfCpltCallback: + 4106 .LVL328: + 4107 .LFB221: +5860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 4108 .loc 1 5860 1 view -0 + ARM GAS /tmp/ccGFzgX3.s page 224 + + + 4109 .cfi_startproc + 4110 @ args = 0, pretend = 0, frame = 0 + 4111 @ frame_needed = 0, uses_anonymous_args = 0 + 4112 @ link register save eliminated. +5862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4113 .loc 1 5862 3 view .LVU1318 +5867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4114 .loc 1 5867 1 is_stmt 0 view .LVU1319 + 4115 0000 7047 bx lr + 4116 .cfi_endproc + 4117 .LFE221: + 4119 .section .text.TIM_DMACaptureHalfCplt,"ax",%progbits + 4120 .align 1 + 4121 .global TIM_DMACaptureHalfCplt + 4122 .syntax unified + 4123 .thumb + 4124 .thumb_func + 4126 TIM_DMACaptureHalfCplt: + 4127 .LVL329: + 4128 .LFB240: +6817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 4129 .loc 1 6817 1 is_stmt 1 view -0 + 4130 .cfi_startproc + 4131 @ args = 0, pretend = 0, frame = 0 + 4132 @ frame_needed = 0, uses_anonymous_args = 0 +6817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 4133 .loc 1 6817 1 is_stmt 0 view .LVU1321 + 4134 0000 10B5 push {r4, lr} + 4135 .LCFI41: + 4136 .cfi_def_cfa_offset 8 + 4137 .cfi_offset 4, -8 + 4138 .cfi_offset 14, -4 +6818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4139 .loc 1 6818 3 is_stmt 1 view .LVU1322 +6818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4140 .loc 1 6818 22 is_stmt 0 view .LVU1323 + 4141 0002 846B ldr r4, [r0, #56] + 4142 .LVL330: +6820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4143 .loc 1 6820 3 is_stmt 1 view .LVU1324 +6820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4144 .loc 1 6820 25 is_stmt 0 view .LVU1325 + 4145 0004 636A ldr r3, [r4, #36] +6820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4146 .loc 1 6820 6 view .LVU1326 + 4147 0006 8342 cmp r3, r0 + 4148 0008 0BD0 beq .L223 +6824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4149 .loc 1 6824 8 is_stmt 1 view .LVU1327 +6824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4150 .loc 1 6824 30 is_stmt 0 view .LVU1328 + 4151 000a A36A ldr r3, [r4, #40] +6824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4152 .loc 1 6824 11 view .LVU1329 + 4153 000c 8342 cmp r3, r0 + 4154 000e 10D0 beq .L224 +6828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 225 + + + 4155 .loc 1 6828 8 is_stmt 1 view .LVU1330 +6828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4156 .loc 1 6828 30 is_stmt 0 view .LVU1331 + 4157 0010 E36A ldr r3, [r4, #44] +6828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4158 .loc 1 6828 11 view .LVU1332 + 4159 0012 8342 cmp r3, r0 + 4160 0014 10D0 beq .L225 +6832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4161 .loc 1 6832 8 is_stmt 1 view .LVU1333 +6832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4162 .loc 1 6832 30 is_stmt 0 view .LVU1334 + 4163 0016 236B ldr r3, [r4, #48] +6832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4164 .loc 1 6832 11 view .LVU1335 + 4165 0018 8342 cmp r3, r0 + 4166 001a 04D1 bne .L219 +6834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4167 .loc 1 6834 5 is_stmt 1 view .LVU1336 +6834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4168 .loc 1 6834 19 is_stmt 0 view .LVU1337 + 4169 001c 0823 movs r3, #8 + 4170 001e 2377 strb r3, [r4, #28] + 4171 0020 01E0 b .L219 + 4172 .L223: +6822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4173 .loc 1 6822 5 is_stmt 1 view .LVU1338 +6822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4174 .loc 1 6822 19 is_stmt 0 view .LVU1339 + 4175 0022 0123 movs r3, #1 + 4176 0024 2377 strb r3, [r4, #28] + 4177 .L219: +6839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4178 .loc 1 6839 3 is_stmt 1 view .LVU1340 +6844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4179 .loc 1 6844 3 view .LVU1341 + 4180 0026 2046 mov r0, r4 + 4181 .LVL331: +6844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4182 .loc 1 6844 3 is_stmt 0 view .LVU1342 + 4183 0028 FFF7FEFF bl HAL_TIM_IC_CaptureHalfCpltCallback + 4184 .LVL332: +6847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4185 .loc 1 6847 3 is_stmt 1 view .LVU1343 +6847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4186 .loc 1 6847 17 is_stmt 0 view .LVU1344 + 4187 002c 0023 movs r3, #0 + 4188 002e 2377 strb r3, [r4, #28] +6848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4189 .loc 1 6848 1 view .LVU1345 + 4190 0030 10BD pop {r4, pc} + 4191 .LVL333: + 4192 .L224: +6826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4193 .loc 1 6826 5 is_stmt 1 view .LVU1346 +6826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4194 .loc 1 6826 19 is_stmt 0 view .LVU1347 + ARM GAS /tmp/ccGFzgX3.s page 226 + + + 4195 0032 0223 movs r3, #2 + 4196 0034 2377 strb r3, [r4, #28] + 4197 0036 F6E7 b .L219 + 4198 .L225: +6830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4199 .loc 1 6830 5 is_stmt 1 view .LVU1348 +6830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4200 .loc 1 6830 19 is_stmt 0 view .LVU1349 + 4201 0038 0423 movs r3, #4 + 4202 003a 2377 strb r3, [r4, #28] + 4203 003c F3E7 b .L219 + 4204 .cfi_endproc + 4205 .LFE240: + 4207 .section .text.HAL_TIM_PWM_PulseFinishedCallback,"ax",%progbits + 4208 .align 1 + 4209 .weak HAL_TIM_PWM_PulseFinishedCallback + 4210 .syntax unified + 4211 .thumb + 4212 .thumb_func + 4214 HAL_TIM_PWM_PulseFinishedCallback: + 4215 .LVL334: + 4216 .LFB222: +5875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 4217 .loc 1 5875 1 is_stmt 1 view -0 + 4218 .cfi_startproc + 4219 @ args = 0, pretend = 0, frame = 0 + 4220 @ frame_needed = 0, uses_anonymous_args = 0 + 4221 @ link register save eliminated. +5877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4222 .loc 1 5877 3 view .LVU1351 +5882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4223 .loc 1 5882 1 is_stmt 0 view .LVU1352 + 4224 0000 7047 bx lr + 4225 .cfi_endproc + 4226 .LFE222: + 4228 .section .text.TIM_DMADelayPulseCplt,"ax",%progbits + 4229 .align 1 + 4230 .syntax unified + 4231 .thumb + 4232 .thumb_func + 4234 TIM_DMADelayPulseCplt: + 4235 .LVL335: + 4236 .LFB237: +6656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 4237 .loc 1 6656 1 is_stmt 1 view -0 + 4238 .cfi_startproc + 4239 @ args = 0, pretend = 0, frame = 0 + 4240 @ frame_needed = 0, uses_anonymous_args = 0 +6656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 4241 .loc 1 6656 1 is_stmt 0 view .LVU1354 + 4242 0000 10B5 push {r4, lr} + 4243 .LCFI42: + 4244 .cfi_def_cfa_offset 8 + 4245 .cfi_offset 4, -8 + 4246 .cfi_offset 14, -4 +6657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4247 .loc 1 6657 3 is_stmt 1 view .LVU1355 + ARM GAS /tmp/ccGFzgX3.s page 227 + + +6657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4248 .loc 1 6657 22 is_stmt 0 view .LVU1356 + 4249 0002 846B ldr r4, [r0, #56] + 4250 .LVL336: +6659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4251 .loc 1 6659 3 is_stmt 1 view .LVU1357 +6659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4252 .loc 1 6659 25 is_stmt 0 view .LVU1358 + 4253 0004 636A ldr r3, [r4, #36] +6659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4254 .loc 1 6659 6 view .LVU1359 + 4255 0006 8342 cmp r3, r0 + 4256 0008 0ED0 beq .L233 +6668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4257 .loc 1 6668 8 is_stmt 1 view .LVU1360 +6668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4258 .loc 1 6668 30 is_stmt 0 view .LVU1361 + 4259 000a A36A ldr r3, [r4, #40] +6668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4260 .loc 1 6668 11 view .LVU1362 + 4261 000c 8342 cmp r3, r0 + 4262 000e 14D0 beq .L234 +6677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4263 .loc 1 6677 8 is_stmt 1 view .LVU1363 +6677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4264 .loc 1 6677 30 is_stmt 0 view .LVU1364 + 4265 0010 E36A ldr r3, [r4, #44] +6677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4266 .loc 1 6677 11 view .LVU1365 + 4267 0012 8342 cmp r3, r0 + 4268 0014 1AD0 beq .L235 +6686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4269 .loc 1 6686 8 is_stmt 1 view .LVU1366 +6686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4270 .loc 1 6686 30 is_stmt 0 view .LVU1367 + 4271 0016 236B ldr r3, [r4, #48] +6686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4272 .loc 1 6686 11 view .LVU1368 + 4273 0018 8342 cmp r3, r0 + 4274 001a 20D0 beq .L236 + 4275 .L229: +6698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4276 .loc 1 6698 3 is_stmt 1 view .LVU1369 +6703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4277 .loc 1 6703 3 view .LVU1370 + 4278 001c 2046 mov r0, r4 + 4279 .LVL337: +6703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4280 .loc 1 6703 3 is_stmt 0 view .LVU1371 + 4281 001e FFF7FEFF bl HAL_TIM_PWM_PulseFinishedCallback + 4282 .LVL338: +6706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4283 .loc 1 6706 3 is_stmt 1 view .LVU1372 +6706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4284 .loc 1 6706 17 is_stmt 0 view .LVU1373 + 4285 0022 0023 movs r3, #0 + 4286 0024 2377 strb r3, [r4, #28] + ARM GAS /tmp/ccGFzgX3.s page 228 + + +6707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4287 .loc 1 6707 1 view .LVU1374 + 4288 0026 10BD pop {r4, pc} + 4289 .LVL339: + 4290 .L233: +6661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4291 .loc 1 6661 5 is_stmt 1 view .LVU1375 +6661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4292 .loc 1 6661 19 is_stmt 0 view .LVU1376 + 4293 0028 0123 movs r3, #1 + 4294 002a 2377 strb r3, [r4, #28] +6663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4295 .loc 1 6663 5 is_stmt 1 view .LVU1377 +6663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4296 .loc 1 6663 19 is_stmt 0 view .LVU1378 + 4297 002c C369 ldr r3, [r0, #28] +6663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4298 .loc 1 6663 8 view .LVU1379 + 4299 002e 002B cmp r3, #0 + 4300 0030 F4D1 bne .L229 +6665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4301 .loc 1 6665 7 is_stmt 1 view .LVU1380 + 4302 0032 0123 movs r3, #1 + 4303 0034 84F83E30 strb r3, [r4, #62] + 4304 0038 F0E7 b .L229 + 4305 .L234: +6670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4306 .loc 1 6670 5 view .LVU1381 +6670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4307 .loc 1 6670 19 is_stmt 0 view .LVU1382 + 4308 003a 0223 movs r3, #2 + 4309 003c 2377 strb r3, [r4, #28] +6672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4310 .loc 1 6672 5 is_stmt 1 view .LVU1383 +6672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4311 .loc 1 6672 19 is_stmt 0 view .LVU1384 + 4312 003e C369 ldr r3, [r0, #28] +6672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4313 .loc 1 6672 8 view .LVU1385 + 4314 0040 002B cmp r3, #0 + 4315 0042 EBD1 bne .L229 +6674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4316 .loc 1 6674 7 is_stmt 1 view .LVU1386 + 4317 0044 0123 movs r3, #1 + 4318 0046 84F83F30 strb r3, [r4, #63] + 4319 004a E7E7 b .L229 + 4320 .L235: +6679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4321 .loc 1 6679 5 view .LVU1387 +6679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4322 .loc 1 6679 19 is_stmt 0 view .LVU1388 + 4323 004c 0423 movs r3, #4 + 4324 004e 2377 strb r3, [r4, #28] +6681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4325 .loc 1 6681 5 is_stmt 1 view .LVU1389 +6681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4326 .loc 1 6681 19 is_stmt 0 view .LVU1390 + ARM GAS /tmp/ccGFzgX3.s page 229 + + + 4327 0050 C369 ldr r3, [r0, #28] +6681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4328 .loc 1 6681 8 view .LVU1391 + 4329 0052 002B cmp r3, #0 + 4330 0054 E2D1 bne .L229 +6683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4331 .loc 1 6683 7 is_stmt 1 view .LVU1392 + 4332 0056 0123 movs r3, #1 + 4333 0058 84F84030 strb r3, [r4, #64] + 4334 005c DEE7 b .L229 + 4335 .L236: +6688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4336 .loc 1 6688 5 view .LVU1393 +6688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4337 .loc 1 6688 19 is_stmt 0 view .LVU1394 + 4338 005e 0823 movs r3, #8 + 4339 0060 2377 strb r3, [r4, #28] +6690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4340 .loc 1 6690 5 is_stmt 1 view .LVU1395 +6690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4341 .loc 1 6690 19 is_stmt 0 view .LVU1396 + 4342 0062 C369 ldr r3, [r0, #28] +6690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4343 .loc 1 6690 8 view .LVU1397 + 4344 0064 002B cmp r3, #0 + 4345 0066 D9D1 bne .L229 +6692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4346 .loc 1 6692 7 is_stmt 1 view .LVU1398 + 4347 0068 0123 movs r3, #1 + 4348 006a 84F84130 strb r3, [r4, #65] + 4349 006e D5E7 b .L229 + 4350 .cfi_endproc + 4351 .LFE237: + 4353 .section .text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback,"ax",%progbits + 4354 .align 1 + 4355 .weak HAL_TIM_PWM_PulseFinishedHalfCpltCallback + 4356 .syntax unified + 4357 .thumb + 4358 .thumb_func + 4360 HAL_TIM_PWM_PulseFinishedHalfCpltCallback: + 4361 .LVL340: + 4362 .LFB223: +5890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 4363 .loc 1 5890 1 view -0 + 4364 .cfi_startproc + 4365 @ args = 0, pretend = 0, frame = 0 + 4366 @ frame_needed = 0, uses_anonymous_args = 0 + 4367 @ link register save eliminated. +5892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4368 .loc 1 5892 3 view .LVU1400 +5897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4369 .loc 1 5897 1 is_stmt 0 view .LVU1401 + 4370 0000 7047 bx lr + 4371 .cfi_endproc + 4372 .LFE223: + 4374 .section .text.TIM_DMADelayPulseHalfCplt,"ax",%progbits + 4375 .align 1 + ARM GAS /tmp/ccGFzgX3.s page 230 + + + 4376 .global TIM_DMADelayPulseHalfCplt + 4377 .syntax unified + 4378 .thumb + 4379 .thumb_func + 4381 TIM_DMADelayPulseHalfCplt: + 4382 .LVL341: + 4383 .LFB238: +6715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 4384 .loc 1 6715 1 is_stmt 1 view -0 + 4385 .cfi_startproc + 4386 @ args = 0, pretend = 0, frame = 0 + 4387 @ frame_needed = 0, uses_anonymous_args = 0 +6715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 4388 .loc 1 6715 1 is_stmt 0 view .LVU1403 + 4389 0000 10B5 push {r4, lr} + 4390 .LCFI43: + 4391 .cfi_def_cfa_offset 8 + 4392 .cfi_offset 4, -8 + 4393 .cfi_offset 14, -4 +6716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4394 .loc 1 6716 3 is_stmt 1 view .LVU1404 +6716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4395 .loc 1 6716 22 is_stmt 0 view .LVU1405 + 4396 0002 846B ldr r4, [r0, #56] + 4397 .LVL342: +6718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4398 .loc 1 6718 3 is_stmt 1 view .LVU1406 +6718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4399 .loc 1 6718 25 is_stmt 0 view .LVU1407 + 4400 0004 636A ldr r3, [r4, #36] +6718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4401 .loc 1 6718 6 view .LVU1408 + 4402 0006 8342 cmp r3, r0 + 4403 0008 0BD0 beq .L244 +6722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4404 .loc 1 6722 8 is_stmt 1 view .LVU1409 +6722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4405 .loc 1 6722 30 is_stmt 0 view .LVU1410 + 4406 000a A36A ldr r3, [r4, #40] +6722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4407 .loc 1 6722 11 view .LVU1411 + 4408 000c 8342 cmp r3, r0 + 4409 000e 10D0 beq .L245 +6726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4410 .loc 1 6726 8 is_stmt 1 view .LVU1412 +6726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4411 .loc 1 6726 30 is_stmt 0 view .LVU1413 + 4412 0010 E36A ldr r3, [r4, #44] +6726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4413 .loc 1 6726 11 view .LVU1414 + 4414 0012 8342 cmp r3, r0 + 4415 0014 10D0 beq .L246 +6730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4416 .loc 1 6730 8 is_stmt 1 view .LVU1415 +6730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4417 .loc 1 6730 30 is_stmt 0 view .LVU1416 + 4418 0016 236B ldr r3, [r4, #48] + ARM GAS /tmp/ccGFzgX3.s page 231 + + +6730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4419 .loc 1 6730 11 view .LVU1417 + 4420 0018 8342 cmp r3, r0 + 4421 001a 04D1 bne .L240 +6732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4422 .loc 1 6732 5 is_stmt 1 view .LVU1418 +6732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4423 .loc 1 6732 19 is_stmt 0 view .LVU1419 + 4424 001c 0823 movs r3, #8 + 4425 001e 2377 strb r3, [r4, #28] + 4426 0020 01E0 b .L240 + 4427 .L244: +6720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4428 .loc 1 6720 5 is_stmt 1 view .LVU1420 +6720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4429 .loc 1 6720 19 is_stmt 0 view .LVU1421 + 4430 0022 0123 movs r3, #1 + 4431 0024 2377 strb r3, [r4, #28] + 4432 .L240: +6737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4433 .loc 1 6737 3 is_stmt 1 view .LVU1422 +6742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4434 .loc 1 6742 3 view .LVU1423 + 4435 0026 2046 mov r0, r4 + 4436 .LVL343: +6742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4437 .loc 1 6742 3 is_stmt 0 view .LVU1424 + 4438 0028 FFF7FEFF bl HAL_TIM_PWM_PulseFinishedHalfCpltCallback + 4439 .LVL344: +6745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4440 .loc 1 6745 3 is_stmt 1 view .LVU1425 +6745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4441 .loc 1 6745 17 is_stmt 0 view .LVU1426 + 4442 002c 0023 movs r3, #0 + 4443 002e 2377 strb r3, [r4, #28] +6746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4444 .loc 1 6746 1 view .LVU1427 + 4445 0030 10BD pop {r4, pc} + 4446 .LVL345: + 4447 .L245: +6724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4448 .loc 1 6724 5 is_stmt 1 view .LVU1428 +6724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4449 .loc 1 6724 19 is_stmt 0 view .LVU1429 + 4450 0032 0223 movs r3, #2 + 4451 0034 2377 strb r3, [r4, #28] + 4452 0036 F6E7 b .L240 + 4453 .L246: +6728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4454 .loc 1 6728 5 is_stmt 1 view .LVU1430 +6728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4455 .loc 1 6728 19 is_stmt 0 view .LVU1431 + 4456 0038 0423 movs r3, #4 + 4457 003a 2377 strb r3, [r4, #28] + 4458 003c F3E7 b .L240 + 4459 .cfi_endproc + 4460 .LFE238: + ARM GAS /tmp/ccGFzgX3.s page 232 + + + 4462 .section .text.HAL_TIM_TriggerCallback,"ax",%progbits + 4463 .align 1 + 4464 .weak HAL_TIM_TriggerCallback + 4465 .syntax unified + 4466 .thumb + 4467 .thumb_func + 4469 HAL_TIM_TriggerCallback: + 4470 .LVL346: + 4471 .LFB224: +5905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 4472 .loc 1 5905 1 is_stmt 1 view -0 + 4473 .cfi_startproc + 4474 @ args = 0, pretend = 0, frame = 0 + 4475 @ frame_needed = 0, uses_anonymous_args = 0 + 4476 @ link register save eliminated. +5907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4477 .loc 1 5907 3 view .LVU1433 +5912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4478 .loc 1 5912 1 is_stmt 0 view .LVU1434 + 4479 0000 7047 bx lr + 4480 .cfi_endproc + 4481 .LFE224: + 4483 .section .text.HAL_TIM_IRQHandler,"ax",%progbits + 4484 .align 1 + 4485 .global HAL_TIM_IRQHandler + 4486 .syntax unified + 4487 .thumb + 4488 .thumb_func + 4490 HAL_TIM_IRQHandler: + 4491 .LVL347: + 4492 .LFB199: +3835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t itsource = htim->Instance->DIER; + 4493 .loc 1 3835 1 is_stmt 1 view -0 + 4494 .cfi_startproc + 4495 @ args = 0, pretend = 0, frame = 0 + 4496 @ frame_needed = 0, uses_anonymous_args = 0 +3835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t itsource = htim->Instance->DIER; + 4497 .loc 1 3835 1 is_stmt 0 view .LVU1436 + 4498 0000 70B5 push {r4, r5, r6, lr} + 4499 .LCFI44: + 4500 .cfi_def_cfa_offset 16 + 4501 .cfi_offset 4, -16 + 4502 .cfi_offset 5, -12 + 4503 .cfi_offset 6, -8 + 4504 .cfi_offset 14, -4 + 4505 0002 0446 mov r4, r0 +3836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t itflag = htim->Instance->SR; + 4506 .loc 1 3836 3 is_stmt 1 view .LVU1437 +3836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t itflag = htim->Instance->SR; + 4507 .loc 1 3836 27 is_stmt 0 view .LVU1438 + 4508 0004 0368 ldr r3, [r0] +3836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t itflag = htim->Instance->SR; + 4509 .loc 1 3836 12 view .LVU1439 + 4510 0006 DE68 ldr r6, [r3, #12] + 4511 .LVL348: +3837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4512 .loc 1 3837 3 is_stmt 1 view .LVU1440 + ARM GAS /tmp/ccGFzgX3.s page 233 + + +3837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4513 .loc 1 3837 12 is_stmt 0 view .LVU1441 + 4514 0008 1D69 ldr r5, [r3, #16] + 4515 .LVL349: +3840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4516 .loc 1 3840 3 is_stmt 1 view .LVU1442 +3840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4517 .loc 1 3840 6 is_stmt 0 view .LVU1443 + 4518 000a 15F0020F tst r5, #2 + 4519 000e 10D0 beq .L249 +3842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4520 .loc 1 3842 5 is_stmt 1 view .LVU1444 +3842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4521 .loc 1 3842 8 is_stmt 0 view .LVU1445 + 4522 0010 16F0020F tst r6, #2 + 4523 0014 0DD0 beq .L249 +3845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 4524 .loc 1 3845 9 is_stmt 1 view .LVU1446 + 4525 0016 6FF00202 mvn r2, #2 + 4526 001a 1A61 str r2, [r3, #16] +3846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4527 .loc 1 3846 9 view .LVU1447 +3846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4528 .loc 1 3846 23 is_stmt 0 view .LVU1448 + 4529 001c 0123 movs r3, #1 + 4530 001e 0377 strb r3, [r0, #28] +3849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4531 .loc 1 3849 9 is_stmt 1 view .LVU1449 +3849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4532 .loc 1 3849 18 is_stmt 0 view .LVU1450 + 4533 0020 0368 ldr r3, [r0] +3849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4534 .loc 1 3849 28 view .LVU1451 + 4535 0022 9B69 ldr r3, [r3, #24] +3849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4536 .loc 1 3849 12 view .LVU1452 + 4537 0024 13F0030F tst r3, #3 + 4538 0028 64D0 beq .L250 +3854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4539 .loc 1 3854 11 is_stmt 1 view .LVU1453 + 4540 002a FFF7FEFF bl HAL_TIM_IC_CaptureCallback + 4541 .LVL350: + 4542 .L251: +3868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4543 .loc 1 3868 9 view .LVU1454 +3868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4544 .loc 1 3868 23 is_stmt 0 view .LVU1455 + 4545 002e 0023 movs r3, #0 + 4546 0030 2377 strb r3, [r4, #28] + 4547 .L249: +3873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4548 .loc 1 3873 3 is_stmt 1 view .LVU1456 +3873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4549 .loc 1 3873 6 is_stmt 0 view .LVU1457 + 4550 0032 15F0040F tst r5, #4 + 4551 0036 12D0 beq .L252 +3875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 234 + + + 4552 .loc 1 3875 5 is_stmt 1 view .LVU1458 +3875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4553 .loc 1 3875 8 is_stmt 0 view .LVU1459 + 4554 0038 16F0040F tst r6, #4 + 4555 003c 0FD0 beq .L252 +3877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 4556 .loc 1 3877 7 is_stmt 1 view .LVU1460 + 4557 003e 2368 ldr r3, [r4] + 4558 0040 6FF00402 mvn r2, #4 + 4559 0044 1A61 str r2, [r3, #16] +3878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Input capture event */ + 4560 .loc 1 3878 7 view .LVU1461 +3878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Input capture event */ + 4561 .loc 1 3878 21 is_stmt 0 view .LVU1462 + 4562 0046 0223 movs r3, #2 + 4563 0048 2377 strb r3, [r4, #28] +3880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4564 .loc 1 3880 7 is_stmt 1 view .LVU1463 +3880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4565 .loc 1 3880 16 is_stmt 0 view .LVU1464 + 4566 004a 2368 ldr r3, [r4] +3880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4567 .loc 1 3880 26 view .LVU1465 + 4568 004c 9B69 ldr r3, [r3, #24] +3880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4569 .loc 1 3880 10 view .LVU1466 + 4570 004e 13F4407F tst r3, #768 + 4571 0052 55D0 beq .L253 +3885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4572 .loc 1 3885 9 is_stmt 1 view .LVU1467 + 4573 0054 2046 mov r0, r4 + 4574 0056 FFF7FEFF bl HAL_TIM_IC_CaptureCallback + 4575 .LVL351: + 4576 .L254: +3899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4577 .loc 1 3899 7 view .LVU1468 +3899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4578 .loc 1 3899 21 is_stmt 0 view .LVU1469 + 4579 005a 0023 movs r3, #0 + 4580 005c 2377 strb r3, [r4, #28] + 4581 .L252: +3903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4582 .loc 1 3903 3 is_stmt 1 view .LVU1470 +3903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4583 .loc 1 3903 6 is_stmt 0 view .LVU1471 + 4584 005e 15F0080F tst r5, #8 + 4585 0062 12D0 beq .L255 +3905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4586 .loc 1 3905 5 is_stmt 1 view .LVU1472 +3905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4587 .loc 1 3905 8 is_stmt 0 view .LVU1473 + 4588 0064 16F0080F tst r6, #8 + 4589 0068 0FD0 beq .L255 +3907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 4590 .loc 1 3907 7 is_stmt 1 view .LVU1474 + 4591 006a 2368 ldr r3, [r4] + 4592 006c 6FF00802 mvn r2, #8 + ARM GAS /tmp/ccGFzgX3.s page 235 + + + 4593 0070 1A61 str r2, [r3, #16] +3908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Input capture event */ + 4594 .loc 1 3908 7 view .LVU1475 +3908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Input capture event */ + 4595 .loc 1 3908 21 is_stmt 0 view .LVU1476 + 4596 0072 0423 movs r3, #4 + 4597 0074 2377 strb r3, [r4, #28] +3910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4598 .loc 1 3910 7 is_stmt 1 view .LVU1477 +3910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4599 .loc 1 3910 16 is_stmt 0 view .LVU1478 + 4600 0076 2368 ldr r3, [r4] +3910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4601 .loc 1 3910 26 view .LVU1479 + 4602 0078 DB69 ldr r3, [r3, #28] +3910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4603 .loc 1 3910 10 view .LVU1480 + 4604 007a 13F0030F tst r3, #3 + 4605 007e 46D0 beq .L256 +3915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4606 .loc 1 3915 9 is_stmt 1 view .LVU1481 + 4607 0080 2046 mov r0, r4 + 4608 0082 FFF7FEFF bl HAL_TIM_IC_CaptureCallback + 4609 .LVL352: + 4610 .L257: +3929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4611 .loc 1 3929 7 view .LVU1482 +3929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4612 .loc 1 3929 21 is_stmt 0 view .LVU1483 + 4613 0086 0023 movs r3, #0 + 4614 0088 2377 strb r3, [r4, #28] + 4615 .L255: +3933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4616 .loc 1 3933 3 is_stmt 1 view .LVU1484 +3933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4617 .loc 1 3933 6 is_stmt 0 view .LVU1485 + 4618 008a 15F0100F tst r5, #16 + 4619 008e 12D0 beq .L258 +3935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4620 .loc 1 3935 5 is_stmt 1 view .LVU1486 +3935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4621 .loc 1 3935 8 is_stmt 0 view .LVU1487 + 4622 0090 16F0100F tst r6, #16 + 4623 0094 0FD0 beq .L258 +3937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 4624 .loc 1 3937 7 is_stmt 1 view .LVU1488 + 4625 0096 2368 ldr r3, [r4] + 4626 0098 6FF01002 mvn r2, #16 + 4627 009c 1A61 str r2, [r3, #16] +3938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Input capture event */ + 4628 .loc 1 3938 7 view .LVU1489 +3938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Input capture event */ + 4629 .loc 1 3938 21 is_stmt 0 view .LVU1490 + 4630 009e 0823 movs r3, #8 + 4631 00a0 2377 strb r3, [r4, #28] +3940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4632 .loc 1 3940 7 is_stmt 1 view .LVU1491 + ARM GAS /tmp/ccGFzgX3.s page 236 + + +3940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4633 .loc 1 3940 16 is_stmt 0 view .LVU1492 + 4634 00a2 2368 ldr r3, [r4] +3940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4635 .loc 1 3940 26 view .LVU1493 + 4636 00a4 DB69 ldr r3, [r3, #28] +3940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4637 .loc 1 3940 10 view .LVU1494 + 4638 00a6 13F4407F tst r3, #768 + 4639 00aa 37D0 beq .L259 +3945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4640 .loc 1 3945 9 is_stmt 1 view .LVU1495 + 4641 00ac 2046 mov r0, r4 + 4642 00ae FFF7FEFF bl HAL_TIM_IC_CaptureCallback + 4643 .LVL353: + 4644 .L260: +3959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4645 .loc 1 3959 7 view .LVU1496 +3959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4646 .loc 1 3959 21 is_stmt 0 view .LVU1497 + 4647 00b2 0023 movs r3, #0 + 4648 00b4 2377 strb r3, [r4, #28] + 4649 .L258: +3963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4650 .loc 1 3963 3 is_stmt 1 view .LVU1498 +3963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4651 .loc 1 3963 6 is_stmt 0 view .LVU1499 + 4652 00b6 15F0010F tst r5, #1 + 4653 00ba 02D0 beq .L261 +3965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4654 .loc 1 3965 5 is_stmt 1 view .LVU1500 +3965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4655 .loc 1 3965 8 is_stmt 0 view .LVU1501 + 4656 00bc 16F0010F tst r6, #1 + 4657 00c0 33D1 bne .L267 + 4658 .L261: +3976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) + 4659 .loc 1 3976 3 is_stmt 1 view .LVU1502 +3976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) + 4660 .loc 1 3976 6 is_stmt 0 view .LVU1503 + 4661 00c2 15F4025F tst r5, #8320 + 4662 00c6 02D0 beq .L262 +3979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4663 .loc 1 3979 5 is_stmt 1 view .LVU1504 +3979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4664 .loc 1 3979 8 is_stmt 0 view .LVU1505 + 4665 00c8 16F0800F tst r6, #128 + 4666 00cc 35D1 bne .L268 + 4667 .L262: +3990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4668 .loc 1 3990 3 is_stmt 1 view .LVU1506 +3990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4669 .loc 1 3990 6 is_stmt 0 view .LVU1507 + 4670 00ce 15F4807F tst r5, #256 + 4671 00d2 02D0 beq .L263 +3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4672 .loc 1 3992 5 is_stmt 1 view .LVU1508 + ARM GAS /tmp/ccGFzgX3.s page 237 + + +3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4673 .loc 1 3992 8 is_stmt 0 view .LVU1509 + 4674 00d4 16F0800F tst r6, #128 + 4675 00d8 37D1 bne .L269 + 4676 .L263: +4003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4677 .loc 1 4003 3 is_stmt 1 view .LVU1510 +4003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4678 .loc 1 4003 6 is_stmt 0 view .LVU1511 + 4679 00da 15F0400F tst r5, #64 + 4680 00de 02D0 beq .L264 +4005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4681 .loc 1 4005 5 is_stmt 1 view .LVU1512 +4005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4682 .loc 1 4005 8 is_stmt 0 view .LVU1513 + 4683 00e0 16F0400F tst r6, #64 + 4684 00e4 39D1 bne .L270 + 4685 .L264: +4016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4686 .loc 1 4016 3 is_stmt 1 view .LVU1514 +4016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4687 .loc 1 4016 6 is_stmt 0 view .LVU1515 + 4688 00e6 15F0200F tst r5, #32 + 4689 00ea 02D0 beq .L248 +4018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4690 .loc 1 4018 5 is_stmt 1 view .LVU1516 +4018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4691 .loc 1 4018 8 is_stmt 0 view .LVU1517 + 4692 00ec 16F0200F tst r6, #32 + 4693 00f0 3BD1 bne .L271 + 4694 .L248: +4028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4695 .loc 1 4028 1 view .LVU1518 + 4696 00f2 70BD pop {r4, r5, r6, pc} + 4697 .LVL354: + 4698 .L250: +3864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); + 4699 .loc 1 3864 11 is_stmt 1 view .LVU1519 + 4700 00f4 FFF7FEFF bl HAL_TIM_OC_DelayElapsedCallback + 4701 .LVL355: +3865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4702 .loc 1 3865 11 view .LVU1520 + 4703 00f8 2046 mov r0, r4 + 4704 00fa FFF7FEFF bl HAL_TIM_PWM_PulseFinishedCallback + 4705 .LVL356: + 4706 00fe 96E7 b .L251 + 4707 .L253: +3895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); + 4708 .loc 1 3895 9 view .LVU1521 + 4709 0100 2046 mov r0, r4 + 4710 0102 FFF7FEFF bl HAL_TIM_OC_DelayElapsedCallback + 4711 .LVL357: +3896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4712 .loc 1 3896 9 view .LVU1522 + 4713 0106 2046 mov r0, r4 + 4714 0108 FFF7FEFF bl HAL_TIM_PWM_PulseFinishedCallback + 4715 .LVL358: + ARM GAS /tmp/ccGFzgX3.s page 238 + + + 4716 010c A5E7 b .L254 + 4717 .L256: +3925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); + 4718 .loc 1 3925 9 view .LVU1523 + 4719 010e 2046 mov r0, r4 + 4720 0110 FFF7FEFF bl HAL_TIM_OC_DelayElapsedCallback + 4721 .LVL359: +3926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4722 .loc 1 3926 9 view .LVU1524 + 4723 0114 2046 mov r0, r4 + 4724 0116 FFF7FEFF bl HAL_TIM_PWM_PulseFinishedCallback + 4725 .LVL360: + 4726 011a B4E7 b .L257 + 4727 .L259: +3955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); + 4728 .loc 1 3955 9 view .LVU1525 + 4729 011c 2046 mov r0, r4 + 4730 011e FFF7FEFF bl HAL_TIM_OC_DelayElapsedCallback + 4731 .LVL361: +3956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4732 .loc 1 3956 9 view .LVU1526 + 4733 0122 2046 mov r0, r4 + 4734 0124 FFF7FEFF bl HAL_TIM_PWM_PulseFinishedCallback + 4735 .LVL362: + 4736 0128 C3E7 b .L260 + 4737 .L267: +3967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + 4738 .loc 1 3967 7 view .LVU1527 + 4739 012a 2368 ldr r3, [r4] + 4740 012c 6FF00102 mvn r2, #1 + 4741 0130 1A61 str r2, [r3, #16] +3971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4742 .loc 1 3971 7 view .LVU1528 + 4743 0132 2046 mov r0, r4 + 4744 0134 FFF7FEFF bl HAL_TIM_PeriodElapsedCallback + 4745 .LVL363: + 4746 0138 C3E7 b .L261 + 4747 .L268: +3981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + 4748 .loc 1 3981 7 view .LVU1529 + 4749 013a 2368 ldr r3, [r4] + 4750 013c 6FF40252 mvn r2, #8320 + 4751 0140 1A61 str r2, [r3, #16] +3985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4752 .loc 1 3985 7 view .LVU1530 + 4753 0142 2046 mov r0, r4 + 4754 0144 FFF7FEFF bl HAL_TIMEx_BreakCallback + 4755 .LVL364: + 4756 0148 C1E7 b .L262 + 4757 .L269: +3994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + 4758 .loc 1 3994 7 view .LVU1531 + 4759 014a 2368 ldr r3, [r4] + 4760 014c 6FF48072 mvn r2, #256 + 4761 0150 1A61 str r2, [r3, #16] +3998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4762 .loc 1 3998 7 view .LVU1532 + ARM GAS /tmp/ccGFzgX3.s page 239 + + + 4763 0152 2046 mov r0, r4 + 4764 0154 FFF7FEFF bl HAL_TIMEx_Break2Callback + 4765 .LVL365: + 4766 0158 BFE7 b .L263 + 4767 .L270: +4007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + 4768 .loc 1 4007 7 view .LVU1533 + 4769 015a 2368 ldr r3, [r4] + 4770 015c 6FF04002 mvn r2, #64 + 4771 0160 1A61 str r2, [r3, #16] +4011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4772 .loc 1 4011 7 view .LVU1534 + 4773 0162 2046 mov r0, r4 + 4774 0164 FFF7FEFF bl HAL_TIM_TriggerCallback + 4775 .LVL366: + 4776 0168 BDE7 b .L264 + 4777 .L271: +4020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + 4778 .loc 1 4020 7 view .LVU1535 + 4779 016a 2368 ldr r3, [r4] + 4780 016c 6FF02002 mvn r2, #32 + 4781 0170 1A61 str r2, [r3, #16] +4024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4782 .loc 1 4024 7 view .LVU1536 + 4783 0172 2046 mov r0, r4 + 4784 0174 FFF7FEFF bl HAL_TIMEx_CommutCallback + 4785 .LVL367: +4028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4786 .loc 1 4028 1 is_stmt 0 view .LVU1537 + 4787 0178 BBE7 b .L248 + 4788 .cfi_endproc + 4789 .LFE199: + 4791 .section .text.TIM_DMATriggerCplt,"ax",%progbits + 4792 .align 1 + 4793 .syntax unified + 4794 .thumb + 4795 .thumb_func + 4797 TIM_DMATriggerCplt: + 4798 .LVL368: + 4799 .LFB243: +6893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 4800 .loc 1 6893 1 is_stmt 1 view -0 + 4801 .cfi_startproc + 4802 @ args = 0, pretend = 0, frame = 0 + 4803 @ frame_needed = 0, uses_anonymous_args = 0 +6893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 4804 .loc 1 6893 1 is_stmt 0 view .LVU1539 + 4805 0000 08B5 push {r3, lr} + 4806 .LCFI45: + 4807 .cfi_def_cfa_offset 8 + 4808 .cfi_offset 3, -8 + 4809 .cfi_offset 14, -4 +6894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4810 .loc 1 6894 3 is_stmt 1 view .LVU1540 +6894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4811 .loc 1 6894 22 is_stmt 0 view .LVU1541 + 4812 0002 806B ldr r0, [r0, #56] + ARM GAS /tmp/ccGFzgX3.s page 240 + + + 4813 .LVL369: +6896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4814 .loc 1 6896 3 is_stmt 1 view .LVU1542 +6896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4815 .loc 1 6896 17 is_stmt 0 view .LVU1543 + 4816 0004 836B ldr r3, [r0, #56] +6896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4817 .loc 1 6896 43 view .LVU1544 + 4818 0006 DB69 ldr r3, [r3, #28] +6896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4819 .loc 1 6896 6 view .LVU1545 + 4820 0008 13B9 cbnz r3, .L273 +6898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4821 .loc 1 6898 5 is_stmt 1 view .LVU1546 +6898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4822 .loc 1 6898 17 is_stmt 0 view .LVU1547 + 4823 000a 0123 movs r3, #1 + 4824 000c 80F83D30 strb r3, [r0, #61] + 4825 .L273: +6904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4826 .loc 1 6904 3 is_stmt 1 view .LVU1548 + 4827 0010 FFF7FEFF bl HAL_TIM_TriggerCallback + 4828 .LVL370: +6906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4829 .loc 1 6906 1 is_stmt 0 view .LVU1549 + 4830 0014 08BD pop {r3, pc} + 4831 .cfi_endproc + 4832 .LFE243: + 4834 .section .text.HAL_TIM_TriggerHalfCpltCallback,"ax",%progbits + 4835 .align 1 + 4836 .weak HAL_TIM_TriggerHalfCpltCallback + 4837 .syntax unified + 4838 .thumb + 4839 .thumb_func + 4841 HAL_TIM_TriggerHalfCpltCallback: + 4842 .LVL371: + 4843 .LFB225: +5920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 4844 .loc 1 5920 1 is_stmt 1 view -0 + 4845 .cfi_startproc + 4846 @ args = 0, pretend = 0, frame = 0 + 4847 @ frame_needed = 0, uses_anonymous_args = 0 + 4848 @ link register save eliminated. +5922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4849 .loc 1 5922 3 view .LVU1551 +5927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4850 .loc 1 5927 1 is_stmt 0 view .LVU1552 + 4851 0000 7047 bx lr + 4852 .cfi_endproc + 4853 .LFE225: + 4855 .section .text.TIM_DMATriggerHalfCplt,"ax",%progbits + 4856 .align 1 + 4857 .syntax unified + 4858 .thumb + 4859 .thumb_func + 4861 TIM_DMATriggerHalfCplt: + 4862 .LVL372: + ARM GAS /tmp/ccGFzgX3.s page 241 + + + 4863 .LFB244: +6914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 4864 .loc 1 6914 1 is_stmt 1 view -0 + 4865 .cfi_startproc + 4866 @ args = 0, pretend = 0, frame = 0 + 4867 @ frame_needed = 0, uses_anonymous_args = 0 +6914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 4868 .loc 1 6914 1 is_stmt 0 view .LVU1554 + 4869 0000 08B5 push {r3, lr} + 4870 .LCFI46: + 4871 .cfi_def_cfa_offset 8 + 4872 .cfi_offset 3, -8 + 4873 .cfi_offset 14, -4 +6915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4874 .loc 1 6915 3 is_stmt 1 view .LVU1555 + 4875 .LVL373: +6920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4876 .loc 1 6920 3 view .LVU1556 + 4877 0002 806B ldr r0, [r0, #56] + 4878 .LVL374: +6920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4879 .loc 1 6920 3 is_stmt 0 view .LVU1557 + 4880 0004 FFF7FEFF bl HAL_TIM_TriggerHalfCpltCallback + 4881 .LVL375: +6922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4882 .loc 1 6922 1 view .LVU1558 + 4883 0008 08BD pop {r3, pc} + 4884 .cfi_endproc + 4885 .LFE244: + 4887 .section .text.HAL_TIM_ErrorCallback,"ax",%progbits + 4888 .align 1 + 4889 .weak HAL_TIM_ErrorCallback + 4890 .syntax unified + 4891 .thumb + 4892 .thumb_func + 4894 HAL_TIM_ErrorCallback: + 4895 .LVL376: + 4896 .LFB226: +5935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 4897 .loc 1 5935 1 is_stmt 1 view -0 + 4898 .cfi_startproc + 4899 @ args = 0, pretend = 0, frame = 0 + 4900 @ frame_needed = 0, uses_anonymous_args = 0 + 4901 @ link register save eliminated. +5937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4902 .loc 1 5937 3 view .LVU1560 +5942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4903 .loc 1 5942 1 is_stmt 0 view .LVU1561 + 4904 0000 7047 bx lr + 4905 .cfi_endproc + 4906 .LFE226: + 4908 .section .text.TIM_DMAError,"ax",%progbits + 4909 .align 1 + 4910 .global TIM_DMAError + 4911 .syntax unified + 4912 .thumb + 4913 .thumb_func + ARM GAS /tmp/ccGFzgX3.s page 242 + + + 4915 TIM_DMAError: + 4916 .LVL377: + 4917 .LFB236: +6613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 4918 .loc 1 6613 1 is_stmt 1 view -0 + 4919 .cfi_startproc + 4920 @ args = 0, pretend = 0, frame = 0 + 4921 @ frame_needed = 0, uses_anonymous_args = 0 +6613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 4922 .loc 1 6613 1 is_stmt 0 view .LVU1563 + 4923 0000 10B5 push {r4, lr} + 4924 .LCFI47: + 4925 .cfi_def_cfa_offset 8 + 4926 .cfi_offset 4, -8 + 4927 .cfi_offset 14, -4 +6614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4928 .loc 1 6614 3 is_stmt 1 view .LVU1564 +6614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4929 .loc 1 6614 22 is_stmt 0 view .LVU1565 + 4930 0002 846B ldr r4, [r0, #56] + 4931 .LVL378: +6616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4932 .loc 1 6616 3 is_stmt 1 view .LVU1566 +6616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4933 .loc 1 6616 25 is_stmt 0 view .LVU1567 + 4934 0004 636A ldr r3, [r4, #36] +6616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4935 .loc 1 6616 6 view .LVU1568 + 4936 0006 8342 cmp r3, r0 + 4937 0008 0CD0 beq .L286 +6621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4938 .loc 1 6621 8 is_stmt 1 view .LVU1569 +6621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4939 .loc 1 6621 30 is_stmt 0 view .LVU1570 + 4940 000a A36A ldr r3, [r4, #40] +6621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4941 .loc 1 6621 11 view .LVU1571 + 4942 000c 8342 cmp r3, r0 + 4943 000e 13D0 beq .L287 +6626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4944 .loc 1 6626 8 is_stmt 1 view .LVU1572 +6626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4945 .loc 1 6626 30 is_stmt 0 view .LVU1573 + 4946 0010 E36A ldr r3, [r4, #44] +6626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4947 .loc 1 6626 11 view .LVU1574 + 4948 0012 8342 cmp r3, r0 + 4949 0014 16D0 beq .L288 +6631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4950 .loc 1 6631 8 is_stmt 1 view .LVU1575 +6631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4951 .loc 1 6631 30 is_stmt 0 view .LVU1576 + 4952 0016 236B ldr r3, [r4, #48] +6631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 4953 .loc 1 6631 11 view .LVU1577 + 4954 0018 8342 cmp r3, r0 + 4955 001a 19D0 beq .L289 + ARM GAS /tmp/ccGFzgX3.s page 243 + + +6638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4956 .loc 1 6638 5 is_stmt 1 view .LVU1578 +6638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4957 .loc 1 6638 17 is_stmt 0 view .LVU1579 + 4958 001c 0123 movs r3, #1 + 4959 001e 84F83D30 strb r3, [r4, #61] + 4960 0022 03E0 b .L281 + 4961 .L286: +6618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 4962 .loc 1 6618 5 is_stmt 1 view .LVU1580 +6618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 4963 .loc 1 6618 19 is_stmt 0 view .LVU1581 + 4964 0024 0123 movs r3, #1 + 4965 0026 2377 strb r3, [r4, #28] +6619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4966 .loc 1 6619 5 is_stmt 1 view .LVU1582 + 4967 0028 84F83E30 strb r3, [r4, #62] + 4968 .L281: +6644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4969 .loc 1 6644 3 view .LVU1583 + 4970 002c 2046 mov r0, r4 + 4971 .LVL379: +6644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 4972 .loc 1 6644 3 is_stmt 0 view .LVU1584 + 4973 002e FFF7FEFF bl HAL_TIM_ErrorCallback + 4974 .LVL380: +6647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4975 .loc 1 6647 3 is_stmt 1 view .LVU1585 +6647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4976 .loc 1 6647 17 is_stmt 0 view .LVU1586 + 4977 0032 0023 movs r3, #0 + 4978 0034 2377 strb r3, [r4, #28] +6648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 4979 .loc 1 6648 1 view .LVU1587 + 4980 0036 10BD pop {r4, pc} + 4981 .LVL381: + 4982 .L287: +6623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 4983 .loc 1 6623 5 is_stmt 1 view .LVU1588 +6623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 4984 .loc 1 6623 19 is_stmt 0 view .LVU1589 + 4985 0038 0223 movs r3, #2 + 4986 003a 2377 strb r3, [r4, #28] +6624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4987 .loc 1 6624 5 is_stmt 1 view .LVU1590 + 4988 003c 0123 movs r3, #1 + 4989 003e 84F83F30 strb r3, [r4, #63] + 4990 0042 F3E7 b .L281 + 4991 .L288: +6628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + 4992 .loc 1 6628 5 view .LVU1591 +6628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + 4993 .loc 1 6628 19 is_stmt 0 view .LVU1592 + 4994 0044 0423 movs r3, #4 + 4995 0046 2377 strb r3, [r4, #28] +6629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 4996 .loc 1 6629 5 is_stmt 1 view .LVU1593 + ARM GAS /tmp/ccGFzgX3.s page 244 + + + 4997 0048 0123 movs r3, #1 + 4998 004a 84F84030 strb r3, [r4, #64] + 4999 004e EDE7 b .L281 + 5000 .L289: +6633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + 5001 .loc 1 6633 5 view .LVU1594 +6633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + 5002 .loc 1 6633 19 is_stmt 0 view .LVU1595 + 5003 0050 0823 movs r3, #8 + 5004 0052 2377 strb r3, [r4, #28] +6634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5005 .loc 1 6634 5 is_stmt 1 view .LVU1596 + 5006 0054 0123 movs r3, #1 + 5007 0056 84F84130 strb r3, [r4, #65] + 5008 005a E7E7 b .L281 + 5009 .cfi_endproc + 5010 .LFE236: + 5012 .section .text.HAL_TIM_Base_GetState,"ax",%progbits + 5013 .align 1 + 5014 .global HAL_TIM_Base_GetState + 5015 .syntax unified + 5016 .thumb + 5017 .thumb_func + 5019 HAL_TIM_Base_GetState: + 5020 .LVL382: + 5021 .LFB227: +6493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return htim->State; + 5022 .loc 1 6493 1 view -0 + 5023 .cfi_startproc + 5024 @ args = 0, pretend = 0, frame = 0 + 5025 @ frame_needed = 0, uses_anonymous_args = 0 + 5026 @ link register save eliminated. +6494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5027 .loc 1 6494 3 view .LVU1598 +6494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5028 .loc 1 6494 14 is_stmt 0 view .LVU1599 + 5029 0000 90F83D00 ldrb r0, [r0, #61] @ zero_extendqisi2 + 5030 .LVL383: +6495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5031 .loc 1 6495 1 view .LVU1600 + 5032 0004 7047 bx lr + 5033 .cfi_endproc + 5034 .LFE227: + 5036 .section .text.HAL_TIM_OC_GetState,"ax",%progbits + 5037 .align 1 + 5038 .global HAL_TIM_OC_GetState + 5039 .syntax unified + 5040 .thumb + 5041 .thumb_func + 5043 HAL_TIM_OC_GetState: + 5044 .LVL384: + 5045 .LFB228: +6503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return htim->State; + 5046 .loc 1 6503 1 is_stmt 1 view -0 + 5047 .cfi_startproc + 5048 @ args = 0, pretend = 0, frame = 0 + 5049 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccGFzgX3.s page 245 + + + 5050 @ link register save eliminated. +6504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5051 .loc 1 6504 3 view .LVU1602 +6504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5052 .loc 1 6504 14 is_stmt 0 view .LVU1603 + 5053 0000 90F83D00 ldrb r0, [r0, #61] @ zero_extendqisi2 + 5054 .LVL385: +6505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5055 .loc 1 6505 1 view .LVU1604 + 5056 0004 7047 bx lr + 5057 .cfi_endproc + 5058 .LFE228: + 5060 .section .text.HAL_TIM_PWM_GetState,"ax",%progbits + 5061 .align 1 + 5062 .global HAL_TIM_PWM_GetState + 5063 .syntax unified + 5064 .thumb + 5065 .thumb_func + 5067 HAL_TIM_PWM_GetState: + 5068 .LVL386: + 5069 .LFB229: +6513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return htim->State; + 5070 .loc 1 6513 1 is_stmt 1 view -0 + 5071 .cfi_startproc + 5072 @ args = 0, pretend = 0, frame = 0 + 5073 @ frame_needed = 0, uses_anonymous_args = 0 + 5074 @ link register save eliminated. +6514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5075 .loc 1 6514 3 view .LVU1606 +6514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5076 .loc 1 6514 14 is_stmt 0 view .LVU1607 + 5077 0000 90F83D00 ldrb r0, [r0, #61] @ zero_extendqisi2 + 5078 .LVL387: +6515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5079 .loc 1 6515 1 view .LVU1608 + 5080 0004 7047 bx lr + 5081 .cfi_endproc + 5082 .LFE229: + 5084 .section .text.HAL_TIM_IC_GetState,"ax",%progbits + 5085 .align 1 + 5086 .global HAL_TIM_IC_GetState + 5087 .syntax unified + 5088 .thumb + 5089 .thumb_func + 5091 HAL_TIM_IC_GetState: + 5092 .LVL388: + 5093 .LFB230: +6523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return htim->State; + 5094 .loc 1 6523 1 is_stmt 1 view -0 + 5095 .cfi_startproc + 5096 @ args = 0, pretend = 0, frame = 0 + 5097 @ frame_needed = 0, uses_anonymous_args = 0 + 5098 @ link register save eliminated. +6524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5099 .loc 1 6524 3 view .LVU1610 +6524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5100 .loc 1 6524 14 is_stmt 0 view .LVU1611 + ARM GAS /tmp/ccGFzgX3.s page 246 + + + 5101 0000 90F83D00 ldrb r0, [r0, #61] @ zero_extendqisi2 + 5102 .LVL389: +6525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5103 .loc 1 6525 1 view .LVU1612 + 5104 0004 7047 bx lr + 5105 .cfi_endproc + 5106 .LFE230: + 5108 .section .text.HAL_TIM_OnePulse_GetState,"ax",%progbits + 5109 .align 1 + 5110 .global HAL_TIM_OnePulse_GetState + 5111 .syntax unified + 5112 .thumb + 5113 .thumb_func + 5115 HAL_TIM_OnePulse_GetState: + 5116 .LVL390: + 5117 .LFB231: +6533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return htim->State; + 5118 .loc 1 6533 1 is_stmt 1 view -0 + 5119 .cfi_startproc + 5120 @ args = 0, pretend = 0, frame = 0 + 5121 @ frame_needed = 0, uses_anonymous_args = 0 + 5122 @ link register save eliminated. +6534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5123 .loc 1 6534 3 view .LVU1614 +6534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5124 .loc 1 6534 14 is_stmt 0 view .LVU1615 + 5125 0000 90F83D00 ldrb r0, [r0, #61] @ zero_extendqisi2 + 5126 .LVL391: +6535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5127 .loc 1 6535 1 view .LVU1616 + 5128 0004 7047 bx lr + 5129 .cfi_endproc + 5130 .LFE231: + 5132 .section .text.HAL_TIM_Encoder_GetState,"ax",%progbits + 5133 .align 1 + 5134 .global HAL_TIM_Encoder_GetState + 5135 .syntax unified + 5136 .thumb + 5137 .thumb_func + 5139 HAL_TIM_Encoder_GetState: + 5140 .LVL392: + 5141 .LFB232: +6543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return htim->State; + 5142 .loc 1 6543 1 is_stmt 1 view -0 + 5143 .cfi_startproc + 5144 @ args = 0, pretend = 0, frame = 0 + 5145 @ frame_needed = 0, uses_anonymous_args = 0 + 5146 @ link register save eliminated. +6544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5147 .loc 1 6544 3 view .LVU1618 +6544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5148 .loc 1 6544 14 is_stmt 0 view .LVU1619 + 5149 0000 90F83D00 ldrb r0, [r0, #61] @ zero_extendqisi2 + 5150 .LVL393: +6545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5151 .loc 1 6545 1 view .LVU1620 + 5152 0004 7047 bx lr + ARM GAS /tmp/ccGFzgX3.s page 247 + + + 5153 .cfi_endproc + 5154 .LFE232: + 5156 .section .text.HAL_TIM_GetActiveChannel,"ax",%progbits + 5157 .align 1 + 5158 .global HAL_TIM_GetActiveChannel + 5159 .syntax unified + 5160 .thumb + 5161 .thumb_func + 5163 HAL_TIM_GetActiveChannel: + 5164 .LVL394: + 5165 .LFB233: +6553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return htim->Channel; + 5166 .loc 1 6553 1 is_stmt 1 view -0 + 5167 .cfi_startproc + 5168 @ args = 0, pretend = 0, frame = 0 + 5169 @ frame_needed = 0, uses_anonymous_args = 0 + 5170 @ link register save eliminated. +6554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5171 .loc 1 6554 3 view .LVU1622 +6555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5172 .loc 1 6555 1 is_stmt 0 view .LVU1623 + 5173 0000 007F ldrb r0, [r0, #28] @ zero_extendqisi2 + 5174 .LVL395: +6555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5175 .loc 1 6555 1 view .LVU1624 + 5176 0002 7047 bx lr + 5177 .cfi_endproc + 5178 .LFE233: + 5180 .section .text.HAL_TIM_GetChannelState,"ax",%progbits + 5181 .align 1 + 5182 .global HAL_TIM_GetChannelState + 5183 .syntax unified + 5184 .thumb + 5185 .thumb_func + 5187 HAL_TIM_GetChannelState: + 5188 .LVL396: + 5189 .LFB234: +6571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_state; + 5190 .loc 1 6571 1 is_stmt 1 view -0 + 5191 .cfi_startproc + 5192 @ args = 0, pretend = 0, frame = 0 + 5193 @ frame_needed = 0, uses_anonymous_args = 0 + 5194 @ link register save eliminated. +6572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5195 .loc 1 6572 3 view .LVU1626 +6575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5196 .loc 1 6575 3 view .LVU1627 +6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5197 .loc 1 6577 3 view .LVU1628 + 5198 0000 1029 cmp r1, #16 + 5199 0002 1ED8 bhi .L298 + 5200 0004 DFE801F0 tbb [pc, r1] + 5201 .L300: + 5202 0008 09 .byte (.L304-.L300)/2 + 5203 0009 1D .byte (.L298-.L300)/2 + 5204 000a 1D .byte (.L298-.L300)/2 + 5205 000b 1D .byte (.L298-.L300)/2 + ARM GAS /tmp/ccGFzgX3.s page 248 + + + 5206 000c 0D .byte (.L303-.L300)/2 + 5207 000d 1D .byte (.L298-.L300)/2 + 5208 000e 1D .byte (.L298-.L300)/2 + 5209 000f 1D .byte (.L298-.L300)/2 + 5210 0010 11 .byte (.L302-.L300)/2 + 5211 0011 1D .byte (.L298-.L300)/2 + 5212 0012 1D .byte (.L298-.L300)/2 + 5213 0013 1D .byte (.L298-.L300)/2 + 5214 0014 15 .byte (.L301-.L300)/2 + 5215 0015 1D .byte (.L298-.L300)/2 + 5216 0016 1D .byte (.L298-.L300)/2 + 5217 0017 1D .byte (.L298-.L300)/2 + 5218 0018 19 .byte (.L299-.L300)/2 + 5219 0019 00 .p2align 1 + 5220 .L304: +6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5221 .loc 1 6577 19 is_stmt 0 discriminator 1 view .LVU1629 + 5222 001a 90F83E00 ldrb r0, [r0, #62] @ zero_extendqisi2 + 5223 .LVL397: +6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5224 .loc 1 6577 19 discriminator 1 view .LVU1630 + 5225 001e C0B2 uxtb r0, r0 + 5226 0020 7047 bx lr + 5227 .LVL398: + 5228 .L303: +6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5229 .loc 1 6577 19 discriminator 4 view .LVU1631 + 5230 0022 90F83F00 ldrb r0, [r0, #63] @ zero_extendqisi2 + 5231 .LVL399: +6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5232 .loc 1 6577 19 discriminator 4 view .LVU1632 + 5233 0026 C0B2 uxtb r0, r0 + 5234 0028 7047 bx lr + 5235 .LVL400: + 5236 .L302: +6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5237 .loc 1 6577 19 discriminator 7 view .LVU1633 + 5238 002a 90F84000 ldrb r0, [r0, #64] @ zero_extendqisi2 + 5239 .LVL401: +6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5240 .loc 1 6577 19 discriminator 7 view .LVU1634 + 5241 002e C0B2 uxtb r0, r0 + 5242 0030 7047 bx lr + 5243 .LVL402: + 5244 .L301: +6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5245 .loc 1 6577 19 discriminator 10 view .LVU1635 + 5246 0032 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 5247 .LVL403: +6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5248 .loc 1 6577 19 discriminator 10 view .LVU1636 + 5249 0036 C0B2 uxtb r0, r0 + 5250 0038 7047 bx lr + 5251 .LVL404: + 5252 .L299: +6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5253 .loc 1 6577 19 discriminator 13 view .LVU1637 + ARM GAS /tmp/ccGFzgX3.s page 249 + + + 5254 003a 90F84200 ldrb r0, [r0, #66] @ zero_extendqisi2 + 5255 .LVL405: +6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5256 .loc 1 6577 19 discriminator 13 view .LVU1638 + 5257 003e C0B2 uxtb r0, r0 + 5258 0040 7047 bx lr + 5259 .LVL406: + 5260 .L298: +6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5261 .loc 1 6577 19 discriminator 14 view .LVU1639 + 5262 0042 90F84300 ldrb r0, [r0, #67] @ zero_extendqisi2 + 5263 .LVL407: +6577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5264 .loc 1 6577 19 discriminator 14 view .LVU1640 + 5265 0046 C0B2 uxtb r0, r0 + 5266 .LVL408: +6579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5267 .loc 1 6579 3 is_stmt 1 view .LVU1641 +6580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5268 .loc 1 6580 1 is_stmt 0 view .LVU1642 + 5269 0048 7047 bx lr + 5270 .cfi_endproc + 5271 .LFE234: + 5273 .section .text.HAL_TIM_DMABurstState,"ax",%progbits + 5274 .align 1 + 5275 .global HAL_TIM_DMABurstState + 5276 .syntax unified + 5277 .thumb + 5278 .thumb_func + 5280 HAL_TIM_DMABurstState: + 5281 .LVL409: + 5282 .LFB235: +6588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 5283 .loc 1 6588 1 is_stmt 1 view -0 + 5284 .cfi_startproc + 5285 @ args = 0, pretend = 0, frame = 0 + 5286 @ frame_needed = 0, uses_anonymous_args = 0 + 5287 @ link register save eliminated. +6590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5288 .loc 1 6590 3 view .LVU1644 +6592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5289 .loc 1 6592 3 view .LVU1645 +6592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5290 .loc 1 6592 14 is_stmt 0 view .LVU1646 + 5291 0000 90F84800 ldrb r0, [r0, #72] @ zero_extendqisi2 + 5292 .LVL410: +6593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5293 .loc 1 6593 1 view .LVU1647 + 5294 0004 7047 bx lr + 5295 .cfi_endproc + 5296 .LFE235: + 5298 .section .text.TIM_Base_SetConfig,"ax",%progbits + 5299 .align 1 + 5300 .global TIM_Base_SetConfig + 5301 .syntax unified + 5302 .thumb + 5303 .thumb_func + ARM GAS /tmp/ccGFzgX3.s page 250 + + + 5305 TIM_Base_SetConfig: + 5306 .LVL411: + 5307 .LFB245: +6931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpcr1; + 5308 .loc 1 6931 1 is_stmt 1 view -0 + 5309 .cfi_startproc + 5310 @ args = 0, pretend = 0, frame = 0 + 5311 @ frame_needed = 0, uses_anonymous_args = 0 +6931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpcr1; + 5312 .loc 1 6931 1 is_stmt 0 view .LVU1649 + 5313 0000 30B5 push {r4, r5, lr} + 5314 .LCFI48: + 5315 .cfi_def_cfa_offset 12 + 5316 .cfi_offset 4, -12 + 5317 .cfi_offset 5, -8 + 5318 .cfi_offset 14, -4 +6932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr1 = TIMx->CR1; + 5319 .loc 1 6932 3 is_stmt 1 view .LVU1650 +6933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5320 .loc 1 6933 3 view .LVU1651 +6933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5321 .loc 1 6933 10 is_stmt 0 view .LVU1652 + 5322 0002 0368 ldr r3, [r0] + 5323 .LVL412: +6936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5324 .loc 1 6936 3 is_stmt 1 view .LVU1653 +6936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5325 .loc 1 6936 7 is_stmt 0 view .LVU1654 + 5326 0004 3F4A ldr r2, .L317 + 5327 0006 9042 cmp r0, r2 + 5328 0008 14BF ite ne + 5329 000a 4FF0000E movne lr, #0 + 5330 000e 4FF0010E moveq lr, #1 + 5331 0012 B0F1804F cmp r0, #1073741824 + 5332 0016 14BF ite ne + 5333 0018 7246 movne r2, lr + 5334 001a 4EF00102 orreq r2, lr, #1 +6936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5335 .loc 1 6936 6 view .LVU1655 + 5336 001e AAB9 cbnz r2, .L308 +6936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5337 .loc 1 6936 7 discriminator 1 view .LVU1656 + 5338 0020 394C ldr r4, .L317+4 + 5339 0022 A042 cmp r0, r4 + 5340 0024 14BF ite ne + 5341 0026 0024 movne r4, #0 + 5342 0028 0124 moveq r4, #1 + 5343 002a 384D ldr r5, .L317+8 + 5344 002c A842 cmp r0, r5 + 5345 002e 0DD0 beq .L308 + 5346 0030 64B9 cbnz r4, .L308 +6936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5347 .loc 1 6936 7 discriminator 2 view .LVU1657 + 5348 0032 04F18044 add r4, r4, #1073741824 + 5349 0036 04F58234 add r4, r4, #66560 + 5350 003a A042 cmp r0, r4 + 5351 003c 14BF ite ne + ARM GAS /tmp/ccGFzgX3.s page 251 + + + 5352 003e 0024 movne r4, #0 + 5353 0040 0124 moveq r4, #1 + 5354 0042 05F50065 add r5, r5, #2048 + 5355 0046 A842 cmp r0, r5 + 5356 0048 00D0 beq .L308 + 5357 004a 1CB1 cbz r4, .L309 + 5358 .L308: +6939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr1 |= Structure->CounterMode; + 5359 .loc 1 6939 5 is_stmt 1 view .LVU1658 +6939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr1 |= Structure->CounterMode; + 5360 .loc 1 6939 12 is_stmt 0 view .LVU1659 + 5361 004c 23F07003 bic r3, r3, #112 + 5362 .LVL413: +6940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5363 .loc 1 6940 5 is_stmt 1 view .LVU1660 +6940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5364 .loc 1 6940 24 is_stmt 0 view .LVU1661 + 5365 0050 4C68 ldr r4, [r1, #4] +6940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5366 .loc 1 6940 12 view .LVU1662 + 5367 0052 2343 orrs r3, r3, r4 + 5368 .LVL414: + 5369 .L309: +6943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5370 .loc 1 6943 3 is_stmt 1 view .LVU1663 +6943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5371 .loc 1 6943 6 is_stmt 0 view .LVU1664 + 5372 0054 002A cmp r2, #0 + 5373 0056 33D1 bne .L311 +6943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5374 .loc 1 6943 7 discriminator 1 view .LVU1665 + 5375 0058 2B4A ldr r2, .L317+4 + 5376 005a 9042 cmp r0, r2 + 5377 005c 14BF ite ne + 5378 005e 0022 movne r2, #0 + 5379 0060 0122 moveq r2, #1 + 5380 0062 2A4C ldr r4, .L317+8 + 5381 0064 A042 cmp r0, r4 + 5382 0066 2BD0 beq .L311 + 5383 0068 52BB cbnz r2, .L311 +6943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5384 .loc 1 6943 7 discriminator 2 view .LVU1666 + 5385 006a 02F18042 add r2, r2, #1073741824 + 5386 006e 02F58232 add r2, r2, #66560 + 5387 0072 9042 cmp r0, r2 + 5388 0074 14BF ite ne + 5389 0076 0022 movne r2, #0 + 5390 0078 0122 moveq r2, #1 + 5391 007a 04F50064 add r4, r4, #2048 + 5392 007e A042 cmp r0, r4 + 5393 0080 1ED0 beq .L311 + 5394 0082 EAB9 cbnz r2, .L311 +6943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5395 .loc 1 6943 7 discriminator 3 view .LVU1667 + 5396 0084 224A ldr r2, .L317+12 + 5397 0086 9042 cmp r0, r2 + 5398 0088 14BF ite ne + ARM GAS /tmp/ccGFzgX3.s page 252 + + + 5399 008a 0022 movne r2, #0 + 5400 008c 0122 moveq r2, #1 + 5401 008e 04F59A34 add r4, r4, #78848 + 5402 0092 A042 cmp r0, r4 + 5403 0094 14D0 beq .L311 + 5404 0096 9AB9 cbnz r2, .L311 +6943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5405 .loc 1 6943 7 discriminator 4 view .LVU1668 + 5406 0098 1E4A ldr r2, .L317+16 + 5407 009a 9042 cmp r0, r2 + 5408 009c 14BF ite ne + 5409 009e 0022 movne r2, #0 + 5410 00a0 0122 moveq r2, #1 + 5411 00a2 04F50064 add r4, r4, #2048 + 5412 00a6 A042 cmp r0, r4 + 5413 00a8 0AD0 beq .L311 + 5414 00aa 4AB9 cbnz r2, .L311 +6943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5415 .loc 1 6943 7 discriminator 5 view .LVU1669 + 5416 00ac 1A4A ldr r2, .L317+20 + 5417 00ae 9042 cmp r0, r2 + 5418 00b0 14BF ite ne + 5419 00b2 0022 movne r2, #0 + 5420 00b4 0122 moveq r2, #1 + 5421 00b6 A4F59634 sub r4, r4, #76800 + 5422 00ba A042 cmp r0, r4 + 5423 00bc 00D0 beq .L311 + 5424 00be 22B1 cbz r2, .L312 + 5425 .L311: +6946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr1 |= (uint32_t)Structure->ClockDivision; + 5426 .loc 1 6946 5 is_stmt 1 view .LVU1670 +6946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr1 |= (uint32_t)Structure->ClockDivision; + 5427 .loc 1 6946 12 is_stmt 0 view .LVU1671 + 5428 00c0 23F4407C bic ip, r3, #768 + 5429 .LVL415: +6947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5430 .loc 1 6947 5 is_stmt 1 view .LVU1672 +6947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5431 .loc 1 6947 34 is_stmt 0 view .LVU1673 + 5432 00c4 CB68 ldr r3, [r1, #12] +6947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5433 .loc 1 6947 12 view .LVU1674 + 5434 00c6 43EA0C03 orr r3, r3, ip + 5435 .LVL416: + 5436 .L312: +6951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5437 .loc 1 6951 3 is_stmt 1 view .LVU1675 + 5438 00ca 23F08003 bic r3, r3, #128 + 5439 .LVL417: +6951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5440 .loc 1 6951 3 is_stmt 0 view .LVU1676 + 5441 00ce 4A69 ldr r2, [r1, #20] + 5442 00d0 1343 orrs r3, r3, r2 + 5443 .LVL418: +6953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5444 .loc 1 6953 3 is_stmt 1 view .LVU1677 +6953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 253 + + + 5445 .loc 1 6953 13 is_stmt 0 view .LVU1678 + 5446 00d2 0360 str r3, [r0] +6956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5447 .loc 1 6956 3 is_stmt 1 view .LVU1679 +6956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5448 .loc 1 6956 34 is_stmt 0 view .LVU1680 + 5449 00d4 8A68 ldr r2, [r1, #8] +6956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5450 .loc 1 6956 13 view .LVU1681 + 5451 00d6 C262 str r2, [r0, #44] +6959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5452 .loc 1 6959 3 is_stmt 1 view .LVU1682 +6959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5453 .loc 1 6959 24 is_stmt 0 view .LVU1683 + 5454 00d8 0A68 ldr r2, [r1] +6959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5455 .loc 1 6959 13 view .LVU1684 + 5456 00da 8262 str r2, [r0, #40] +6961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5457 .loc 1 6961 3 is_stmt 1 view .LVU1685 +6961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5458 .loc 1 6961 7 is_stmt 0 view .LVU1686 + 5459 00dc 0F4A ldr r2, .L317+24 + 5460 00de 9042 cmp r0, r2 + 5461 00e0 14BF ite ne + 5462 00e2 7346 movne r3, lr + 5463 00e4 4EF00103 orreq r3, lr, #1 + 5464 .LVL419: +6961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5465 .loc 1 6961 6 view .LVU1687 + 5466 00e8 0BB1 cbz r3, .L314 +6964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5467 .loc 1 6964 5 is_stmt 1 view .LVU1688 +6964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5468 .loc 1 6964 26 is_stmt 0 view .LVU1689 + 5469 00ea 0B69 ldr r3, [r1, #16] +6964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5470 .loc 1 6964 15 view .LVU1690 + 5471 00ec 0363 str r3, [r0, #48] + 5472 .L314: +6969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5473 .loc 1 6969 3 is_stmt 1 view .LVU1691 +6969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5474 .loc 1 6969 13 is_stmt 0 view .LVU1692 + 5475 00ee 0123 movs r3, #1 + 5476 00f0 4361 str r3, [r0, #20] +6972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5477 .loc 1 6972 3 is_stmt 1 view .LVU1693 +6972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5478 .loc 1 6972 7 is_stmt 0 view .LVU1694 + 5479 00f2 0369 ldr r3, [r0, #16] +6972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5480 .loc 1 6972 6 view .LVU1695 + 5481 00f4 13F0010F tst r3, #1 + 5482 00f8 03D0 beq .L307 +6975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5483 .loc 1 6975 5 is_stmt 1 view .LVU1696 + ARM GAS /tmp/ccGFzgX3.s page 254 + + + 5484 00fa 0369 ldr r3, [r0, #16] + 5485 00fc 23F00103 bic r3, r3, #1 + 5486 0100 0361 str r3, [r0, #16] + 5487 .L307: +6977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5488 .loc 1 6977 1 is_stmt 0 view .LVU1697 + 5489 0102 30BD pop {r4, r5, pc} + 5490 .L318: + 5491 .align 2 + 5492 .L317: + 5493 0104 00000140 .word 1073807360 + 5494 0108 00080040 .word 1073743872 + 5495 010c 00040040 .word 1073742848 + 5496 0110 00440140 .word 1073824768 + 5497 0114 00180040 .word 1073747968 + 5498 0118 00200040 .word 1073750016 + 5499 011c 00040140 .word 1073808384 + 5500 .cfi_endproc + 5501 .LFE245: + 5503 .section .text.HAL_TIM_Base_Init,"ax",%progbits + 5504 .align 1 + 5505 .global HAL_TIM_Base_Init + 5506 .syntax unified + 5507 .thumb + 5508 .thumb_func + 5510 HAL_TIM_Base_Init: + 5511 .LVL420: + 5512 .LFB141: + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM handle allocation */ + 5513 .loc 1 270 1 is_stmt 1 view -0 + 5514 .cfi_startproc + 5515 @ args = 0, pretend = 0, frame = 0 + 5516 @ frame_needed = 0, uses_anonymous_args = 0 + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5517 .loc 1 272 3 view .LVU1699 + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5518 .loc 1 272 6 is_stmt 0 view .LVU1700 + 5519 0000 60B3 cbz r0, .L322 + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM handle allocation */ + 5520 .loc 1 270 1 view .LVU1701 + 5521 0002 10B5 push {r4, lr} + 5522 .LCFI49: + 5523 .cfi_def_cfa_offset 8 + 5524 .cfi_offset 4, -8 + 5525 .cfi_offset 14, -4 + 5526 0004 0446 mov r4, r0 + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + 5527 .loc 1 278 3 is_stmt 1 view .LVU1702 + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + 5528 .loc 1 279 3 view .LVU1703 + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + 5529 .loc 1 280 3 view .LVU1704 + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + 5530 .loc 1 281 3 view .LVU1705 + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5531 .loc 1 282 3 view .LVU1706 + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 255 + + + 5532 .loc 1 284 3 view .LVU1707 + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5533 .loc 1 284 11 is_stmt 0 view .LVU1708 + 5534 0006 90F83D30 ldrb r3, [r0, #61] @ zero_extendqisi2 + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5535 .loc 1 284 6 view .LVU1709 + 5536 000a 13B3 cbz r3, .L327 + 5537 .LVL421: + 5538 .L321: + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5539 .loc 1 306 3 is_stmt 1 view .LVU1710 + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5540 .loc 1 306 15 is_stmt 0 view .LVU1711 + 5541 000c 0223 movs r3, #2 + 5542 000e 84F83D30 strb r3, [r4, #61] + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5543 .loc 1 309 3 is_stmt 1 view .LVU1712 + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5544 .loc 1 309 38 is_stmt 0 view .LVU1713 + 5545 0012 2146 mov r1, r4 + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5546 .loc 1 309 3 view .LVU1714 + 5547 0014 51F8040B ldr r0, [r1], #4 + 5548 0018 FFF7FEFF bl TIM_Base_SetConfig + 5549 .LVL422: + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5550 .loc 1 312 3 is_stmt 1 view .LVU1715 + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5551 .loc 1 312 23 is_stmt 0 view .LVU1716 + 5552 001c 0123 movs r3, #1 + 5553 001e 84F84830 strb r3, [r4, #72] + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5554 .loc 1 315 3 is_stmt 1 view .LVU1717 + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5555 .loc 1 315 3 view .LVU1718 + 5556 0022 84F83E30 strb r3, [r4, #62] + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5557 .loc 1 315 3 view .LVU1719 + 5558 0026 84F83F30 strb r3, [r4, #63] + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5559 .loc 1 315 3 view .LVU1720 + 5560 002a 84F84030 strb r3, [r4, #64] + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5561 .loc 1 315 3 view .LVU1721 + 5562 002e 84F84130 strb r3, [r4, #65] + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5563 .loc 1 315 3 view .LVU1722 + 5564 0032 84F84230 strb r3, [r4, #66] + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5565 .loc 1 315 3 view .LVU1723 + 5566 0036 84F84330 strb r3, [r4, #67] + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5567 .loc 1 315 3 view .LVU1724 + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5568 .loc 1 316 3 view .LVU1725 + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5569 .loc 1 316 3 view .LVU1726 + ARM GAS /tmp/ccGFzgX3.s page 256 + + + 5570 003a 84F84430 strb r3, [r4, #68] + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5571 .loc 1 316 3 view .LVU1727 + 5572 003e 84F84530 strb r3, [r4, #69] + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5573 .loc 1 316 3 view .LVU1728 + 5574 0042 84F84630 strb r3, [r4, #70] + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5575 .loc 1 316 3 view .LVU1729 + 5576 0046 84F84730 strb r3, [r4, #71] + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5577 .loc 1 316 3 view .LVU1730 + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5578 .loc 1 319 3 view .LVU1731 + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5579 .loc 1 319 15 is_stmt 0 view .LVU1732 + 5580 004a 84F83D30 strb r3, [r4, #61] + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5581 .loc 1 321 3 is_stmt 1 view .LVU1733 + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5582 .loc 1 321 10 is_stmt 0 view .LVU1734 + 5583 004e 0020 movs r0, #0 + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5584 .loc 1 322 1 view .LVU1735 + 5585 0050 10BD pop {r4, pc} + 5586 .LVL423: + 5587 .L327: + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5588 .loc 1 287 5 is_stmt 1 view .LVU1736 + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5589 .loc 1 287 16 is_stmt 0 view .LVU1737 + 5590 0052 80F83C30 strb r3, [r0, #60] + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 5591 .loc 1 301 5 is_stmt 1 view .LVU1738 + 5592 0056 FFF7FEFF bl HAL_TIM_Base_MspInit + 5593 .LVL424: + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 5594 .loc 1 301 5 is_stmt 0 view .LVU1739 + 5595 005a D7E7 b .L321 + 5596 .LVL425: + 5597 .L322: + 5598 .LCFI50: + 5599 .cfi_def_cfa_offset 0 + 5600 .cfi_restore 4 + 5601 .cfi_restore 14 + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5602 .loc 1 274 12 view .LVU1740 + 5603 005c 0120 movs r0, #1 + 5604 .LVL426: + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5605 .loc 1 322 1 view .LVU1741 + 5606 005e 7047 bx lr + 5607 .cfi_endproc + 5608 .LFE141: + 5610 .section .text.HAL_TIM_OC_Init,"ax",%progbits + 5611 .align 1 + 5612 .global HAL_TIM_OC_Init + ARM GAS /tmp/ccGFzgX3.s page 257 + + + 5613 .syntax unified + 5614 .thumb + 5615 .thumb_func + 5617 HAL_TIM_OC_Init: + 5618 .LVL427: + 5619 .LFB151: + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM handle allocation */ + 5620 .loc 1 654 1 is_stmt 1 view -0 + 5621 .cfi_startproc + 5622 @ args = 0, pretend = 0, frame = 0 + 5623 @ frame_needed = 0, uses_anonymous_args = 0 + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5624 .loc 1 656 3 view .LVU1743 + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5625 .loc 1 656 6 is_stmt 0 view .LVU1744 + 5626 0000 60B3 cbz r0, .L331 + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM handle allocation */ + 5627 .loc 1 654 1 view .LVU1745 + 5628 0002 10B5 push {r4, lr} + 5629 .LCFI51: + 5630 .cfi_def_cfa_offset 8 + 5631 .cfi_offset 4, -8 + 5632 .cfi_offset 14, -4 + 5633 0004 0446 mov r4, r0 + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + 5634 .loc 1 662 3 is_stmt 1 view .LVU1746 + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + 5635 .loc 1 663 3 view .LVU1747 + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + 5636 .loc 1 664 3 view .LVU1748 + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + 5637 .loc 1 665 3 view .LVU1749 + 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5638 .loc 1 666 3 view .LVU1750 + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5639 .loc 1 668 3 view .LVU1751 + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5640 .loc 1 668 11 is_stmt 0 view .LVU1752 + 5641 0006 90F83D30 ldrb r3, [r0, #61] @ zero_extendqisi2 + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5642 .loc 1 668 6 view .LVU1753 + 5643 000a 13B3 cbz r3, .L336 + 5644 .LVL428: + 5645 .L330: + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5646 .loc 1 690 3 is_stmt 1 view .LVU1754 + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5647 .loc 1 690 15 is_stmt 0 view .LVU1755 + 5648 000c 0223 movs r3, #2 + 5649 000e 84F83D30 strb r3, [r4, #61] + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5650 .loc 1 693 3 is_stmt 1 view .LVU1756 + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5651 .loc 1 693 39 is_stmt 0 view .LVU1757 + 5652 0012 2146 mov r1, r4 + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5653 .loc 1 693 3 view .LVU1758 + ARM GAS /tmp/ccGFzgX3.s page 258 + + + 5654 0014 51F8040B ldr r0, [r1], #4 + 5655 0018 FFF7FEFF bl TIM_Base_SetConfig + 5656 .LVL429: + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5657 .loc 1 696 3 is_stmt 1 view .LVU1759 + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5658 .loc 1 696 23 is_stmt 0 view .LVU1760 + 5659 001c 0123 movs r3, #1 + 5660 001e 84F84830 strb r3, [r4, #72] + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5661 .loc 1 699 3 is_stmt 1 view .LVU1761 + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5662 .loc 1 699 3 view .LVU1762 + 5663 0022 84F83E30 strb r3, [r4, #62] + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5664 .loc 1 699 3 view .LVU1763 + 5665 0026 84F83F30 strb r3, [r4, #63] + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5666 .loc 1 699 3 view .LVU1764 + 5667 002a 84F84030 strb r3, [r4, #64] + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5668 .loc 1 699 3 view .LVU1765 + 5669 002e 84F84130 strb r3, [r4, #65] + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5670 .loc 1 699 3 view .LVU1766 + 5671 0032 84F84230 strb r3, [r4, #66] + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5672 .loc 1 699 3 view .LVU1767 + 5673 0036 84F84330 strb r3, [r4, #67] + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5674 .loc 1 699 3 view .LVU1768 + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5675 .loc 1 700 3 view .LVU1769 + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5676 .loc 1 700 3 view .LVU1770 + 5677 003a 84F84430 strb r3, [r4, #68] + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5678 .loc 1 700 3 view .LVU1771 + 5679 003e 84F84530 strb r3, [r4, #69] + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5680 .loc 1 700 3 view .LVU1772 + 5681 0042 84F84630 strb r3, [r4, #70] + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5682 .loc 1 700 3 view .LVU1773 + 5683 0046 84F84730 strb r3, [r4, #71] + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5684 .loc 1 700 3 view .LVU1774 + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5685 .loc 1 703 3 view .LVU1775 + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5686 .loc 1 703 15 is_stmt 0 view .LVU1776 + 5687 004a 84F83D30 strb r3, [r4, #61] + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5688 .loc 1 705 3 is_stmt 1 view .LVU1777 + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5689 .loc 1 705 10 is_stmt 0 view .LVU1778 + 5690 004e 0020 movs r0, #0 + ARM GAS /tmp/ccGFzgX3.s page 259 + + + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5691 .loc 1 706 1 view .LVU1779 + 5692 0050 10BD pop {r4, pc} + 5693 .LVL430: + 5694 .L336: + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5695 .loc 1 671 5 is_stmt 1 view .LVU1780 + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5696 .loc 1 671 16 is_stmt 0 view .LVU1781 + 5697 0052 80F83C30 strb r3, [r0, #60] + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 5698 .loc 1 685 5 is_stmt 1 view .LVU1782 + 5699 0056 FFF7FEFF bl HAL_TIM_OC_MspInit + 5700 .LVL431: + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 5701 .loc 1 685 5 is_stmt 0 view .LVU1783 + 5702 005a D7E7 b .L330 + 5703 .LVL432: + 5704 .L331: + 5705 .LCFI52: + 5706 .cfi_def_cfa_offset 0 + 5707 .cfi_restore 4 + 5708 .cfi_restore 14 + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5709 .loc 1 658 12 view .LVU1784 + 5710 005c 0120 movs r0, #1 + 5711 .LVL433: + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5712 .loc 1 706 1 view .LVU1785 + 5713 005e 7047 bx lr + 5714 .cfi_endproc + 5715 .LFE151: + 5717 .section .text.HAL_TIM_PWM_Init,"ax",%progbits + 5718 .align 1 + 5719 .global HAL_TIM_PWM_Init + 5720 .syntax unified + 5721 .thumb + 5722 .thumb_func + 5724 HAL_TIM_PWM_Init: + 5725 .LVL434: + 5726 .LFB161: +1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM handle allocation */ + 5727 .loc 1 1323 1 is_stmt 1 view -0 + 5728 .cfi_startproc + 5729 @ args = 0, pretend = 0, frame = 0 + 5730 @ frame_needed = 0, uses_anonymous_args = 0 +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5731 .loc 1 1325 3 view .LVU1787 +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5732 .loc 1 1325 6 is_stmt 0 view .LVU1788 + 5733 0000 60B3 cbz r0, .L340 +1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM handle allocation */ + 5734 .loc 1 1323 1 view .LVU1789 + 5735 0002 10B5 push {r4, lr} + 5736 .LCFI53: + 5737 .cfi_def_cfa_offset 8 + 5738 .cfi_offset 4, -8 + ARM GAS /tmp/ccGFzgX3.s page 260 + + + 5739 .cfi_offset 14, -4 + 5740 0004 0446 mov r4, r0 +1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + 5741 .loc 1 1331 3 is_stmt 1 view .LVU1790 +1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + 5742 .loc 1 1332 3 view .LVU1791 +1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + 5743 .loc 1 1333 3 view .LVU1792 +1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + 5744 .loc 1 1334 3 view .LVU1793 +1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5745 .loc 1 1335 3 view .LVU1794 +1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5746 .loc 1 1337 3 view .LVU1795 +1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5747 .loc 1 1337 11 is_stmt 0 view .LVU1796 + 5748 0006 90F83D30 ldrb r3, [r0, #61] @ zero_extendqisi2 +1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5749 .loc 1 1337 6 view .LVU1797 + 5750 000a 13B3 cbz r3, .L345 + 5751 .LVL435: + 5752 .L339: +1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5753 .loc 1 1359 3 is_stmt 1 view .LVU1798 +1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5754 .loc 1 1359 15 is_stmt 0 view .LVU1799 + 5755 000c 0223 movs r3, #2 + 5756 000e 84F83D30 strb r3, [r4, #61] +1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5757 .loc 1 1362 3 is_stmt 1 view .LVU1800 +1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5758 .loc 1 1362 38 is_stmt 0 view .LVU1801 + 5759 0012 2146 mov r1, r4 +1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5760 .loc 1 1362 3 view .LVU1802 + 5761 0014 51F8040B ldr r0, [r1], #4 + 5762 0018 FFF7FEFF bl TIM_Base_SetConfig + 5763 .LVL436: +1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5764 .loc 1 1365 3 is_stmt 1 view .LVU1803 +1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5765 .loc 1 1365 23 is_stmt 0 view .LVU1804 + 5766 001c 0123 movs r3, #1 + 5767 001e 84F84830 strb r3, [r4, #72] +1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5768 .loc 1 1368 3 is_stmt 1 view .LVU1805 +1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5769 .loc 1 1368 3 view .LVU1806 + 5770 0022 84F83E30 strb r3, [r4, #62] +1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5771 .loc 1 1368 3 view .LVU1807 + 5772 0026 84F83F30 strb r3, [r4, #63] +1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5773 .loc 1 1368 3 view .LVU1808 + 5774 002a 84F84030 strb r3, [r4, #64] +1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5775 .loc 1 1368 3 view .LVU1809 + ARM GAS /tmp/ccGFzgX3.s page 261 + + + 5776 002e 84F84130 strb r3, [r4, #65] +1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5777 .loc 1 1368 3 view .LVU1810 + 5778 0032 84F84230 strb r3, [r4, #66] +1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5779 .loc 1 1368 3 view .LVU1811 + 5780 0036 84F84330 strb r3, [r4, #67] +1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5781 .loc 1 1368 3 view .LVU1812 +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5782 .loc 1 1369 3 view .LVU1813 +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5783 .loc 1 1369 3 view .LVU1814 + 5784 003a 84F84430 strb r3, [r4, #68] +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5785 .loc 1 1369 3 view .LVU1815 + 5786 003e 84F84530 strb r3, [r4, #69] +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5787 .loc 1 1369 3 view .LVU1816 + 5788 0042 84F84630 strb r3, [r4, #70] +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5789 .loc 1 1369 3 view .LVU1817 + 5790 0046 84F84730 strb r3, [r4, #71] +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5791 .loc 1 1369 3 view .LVU1818 +1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5792 .loc 1 1372 3 view .LVU1819 +1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5793 .loc 1 1372 15 is_stmt 0 view .LVU1820 + 5794 004a 84F83D30 strb r3, [r4, #61] +1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5795 .loc 1 1374 3 is_stmt 1 view .LVU1821 +1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5796 .loc 1 1374 10 is_stmt 0 view .LVU1822 + 5797 004e 0020 movs r0, #0 +1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5798 .loc 1 1375 1 view .LVU1823 + 5799 0050 10BD pop {r4, pc} + 5800 .LVL437: + 5801 .L345: +1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5802 .loc 1 1340 5 is_stmt 1 view .LVU1824 +1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5803 .loc 1 1340 16 is_stmt 0 view .LVU1825 + 5804 0052 80F83C30 strb r3, [r0, #60] +1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 5805 .loc 1 1354 5 is_stmt 1 view .LVU1826 + 5806 0056 FFF7FEFF bl HAL_TIM_PWM_MspInit + 5807 .LVL438: +1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 5808 .loc 1 1354 5 is_stmt 0 view .LVU1827 + 5809 005a D7E7 b .L339 + 5810 .LVL439: + 5811 .L340: + 5812 .LCFI54: + 5813 .cfi_def_cfa_offset 0 + 5814 .cfi_restore 4 + ARM GAS /tmp/ccGFzgX3.s page 262 + + + 5815 .cfi_restore 14 +1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5816 .loc 1 1327 12 view .LVU1828 + 5817 005c 0120 movs r0, #1 + 5818 .LVL440: +1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5819 .loc 1 1375 1 view .LVU1829 + 5820 005e 7047 bx lr + 5821 .cfi_endproc + 5822 .LFE161: + 5824 .section .text.HAL_TIM_IC_Init,"ax",%progbits + 5825 .align 1 + 5826 .global HAL_TIM_IC_Init + 5827 .syntax unified + 5828 .thumb + 5829 .thumb_func + 5831 HAL_TIM_IC_Init: + 5832 .LVL441: + 5833 .LFB171: +1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM handle allocation */ + 5834 .loc 1 1991 1 is_stmt 1 view -0 + 5835 .cfi_startproc + 5836 @ args = 0, pretend = 0, frame = 0 + 5837 @ frame_needed = 0, uses_anonymous_args = 0 +1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5838 .loc 1 1993 3 view .LVU1831 +1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5839 .loc 1 1993 6 is_stmt 0 view .LVU1832 + 5840 0000 60B3 cbz r0, .L349 +1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM handle allocation */ + 5841 .loc 1 1991 1 view .LVU1833 + 5842 0002 10B5 push {r4, lr} + 5843 .LCFI55: + 5844 .cfi_def_cfa_offset 8 + 5845 .cfi_offset 4, -8 + 5846 .cfi_offset 14, -4 + 5847 0004 0446 mov r4, r0 +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + 5848 .loc 1 1999 3 is_stmt 1 view .LVU1834 +2000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + 5849 .loc 1 2000 3 view .LVU1835 +2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + 5850 .loc 1 2001 3 view .LVU1836 +2002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + 5851 .loc 1 2002 3 view .LVU1837 +2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5852 .loc 1 2003 3 view .LVU1838 +2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5853 .loc 1 2005 3 view .LVU1839 +2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5854 .loc 1 2005 11 is_stmt 0 view .LVU1840 + 5855 0006 90F83D30 ldrb r3, [r0, #61] @ zero_extendqisi2 +2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5856 .loc 1 2005 6 view .LVU1841 + 5857 000a 13B3 cbz r3, .L354 + 5858 .LVL442: + 5859 .L348: + ARM GAS /tmp/ccGFzgX3.s page 263 + + +2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5860 .loc 1 2027 3 is_stmt 1 view .LVU1842 +2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5861 .loc 1 2027 15 is_stmt 0 view .LVU1843 + 5862 000c 0223 movs r3, #2 + 5863 000e 84F83D30 strb r3, [r4, #61] +2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5864 .loc 1 2030 3 is_stmt 1 view .LVU1844 +2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5865 .loc 1 2030 38 is_stmt 0 view .LVU1845 + 5866 0012 2146 mov r1, r4 +2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5867 .loc 1 2030 3 view .LVU1846 + 5868 0014 51F8040B ldr r0, [r1], #4 + 5869 0018 FFF7FEFF bl TIM_Base_SetConfig + 5870 .LVL443: +2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5871 .loc 1 2033 3 is_stmt 1 view .LVU1847 +2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5872 .loc 1 2033 23 is_stmt 0 view .LVU1848 + 5873 001c 0123 movs r3, #1 + 5874 001e 84F84830 strb r3, [r4, #72] +2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5875 .loc 1 2036 3 is_stmt 1 view .LVU1849 +2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5876 .loc 1 2036 3 view .LVU1850 + 5877 0022 84F83E30 strb r3, [r4, #62] +2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5878 .loc 1 2036 3 view .LVU1851 + 5879 0026 84F83F30 strb r3, [r4, #63] +2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5880 .loc 1 2036 3 view .LVU1852 + 5881 002a 84F84030 strb r3, [r4, #64] +2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5882 .loc 1 2036 3 view .LVU1853 + 5883 002e 84F84130 strb r3, [r4, #65] +2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5884 .loc 1 2036 3 view .LVU1854 + 5885 0032 84F84230 strb r3, [r4, #66] +2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5886 .loc 1 2036 3 view .LVU1855 + 5887 0036 84F84330 strb r3, [r4, #67] +2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 5888 .loc 1 2036 3 view .LVU1856 +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5889 .loc 1 2037 3 view .LVU1857 +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5890 .loc 1 2037 3 view .LVU1858 + 5891 003a 84F84430 strb r3, [r4, #68] +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5892 .loc 1 2037 3 view .LVU1859 + 5893 003e 84F84530 strb r3, [r4, #69] +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5894 .loc 1 2037 3 view .LVU1860 + 5895 0042 84F84630 strb r3, [r4, #70] +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5896 .loc 1 2037 3 view .LVU1861 + ARM GAS /tmp/ccGFzgX3.s page 264 + + + 5897 0046 84F84730 strb r3, [r4, #71] +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5898 .loc 1 2037 3 view .LVU1862 +2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5899 .loc 1 2040 3 view .LVU1863 +2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5900 .loc 1 2040 15 is_stmt 0 view .LVU1864 + 5901 004a 84F83D30 strb r3, [r4, #61] +2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5902 .loc 1 2042 3 is_stmt 1 view .LVU1865 +2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5903 .loc 1 2042 10 is_stmt 0 view .LVU1866 + 5904 004e 0020 movs r0, #0 +2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5905 .loc 1 2043 1 view .LVU1867 + 5906 0050 10BD pop {r4, pc} + 5907 .LVL444: + 5908 .L354: +2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5909 .loc 1 2008 5 is_stmt 1 view .LVU1868 +2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5910 .loc 1 2008 16 is_stmt 0 view .LVU1869 + 5911 0052 80F83C30 strb r3, [r0, #60] +2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 5912 .loc 1 2022 5 is_stmt 1 view .LVU1870 + 5913 0056 FFF7FEFF bl HAL_TIM_IC_MspInit + 5914 .LVL445: +2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 5915 .loc 1 2022 5 is_stmt 0 view .LVU1871 + 5916 005a D7E7 b .L348 + 5917 .LVL446: + 5918 .L349: + 5919 .LCFI56: + 5920 .cfi_def_cfa_offset 0 + 5921 .cfi_restore 4 + 5922 .cfi_restore 14 +1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 5923 .loc 1 1995 12 view .LVU1872 + 5924 005c 0120 movs r0, #1 + 5925 .LVL447: +2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5926 .loc 1 2043 1 view .LVU1873 + 5927 005e 7047 bx lr + 5928 .cfi_endproc + 5929 .LFE171: + 5931 .section .text.HAL_TIM_OnePulse_Init,"ax",%progbits + 5932 .align 1 + 5933 .global HAL_TIM_OnePulse_Init + 5934 .syntax unified + 5935 .thumb + 5936 .thumb_func + 5938 HAL_TIM_OnePulse_Init: + 5939 .LVL448: + 5940 .LFB181: +2640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM handle allocation */ + 5941 .loc 1 2640 1 is_stmt 1 view -0 + 5942 .cfi_startproc + ARM GAS /tmp/ccGFzgX3.s page 265 + + + 5943 @ args = 0, pretend = 0, frame = 0 + 5944 @ frame_needed = 0, uses_anonymous_args = 0 +2642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5945 .loc 1 2642 3 view .LVU1875 +2642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5946 .loc 1 2642 6 is_stmt 0 view .LVU1876 + 5947 0000 50B3 cbz r0, .L358 +2640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the TIM handle allocation */ + 5948 .loc 1 2640 1 view .LVU1877 + 5949 0002 38B5 push {r3, r4, r5, lr} + 5950 .LCFI57: + 5951 .cfi_def_cfa_offset 16 + 5952 .cfi_offset 3, -16 + 5953 .cfi_offset 4, -12 + 5954 .cfi_offset 5, -8 + 5955 .cfi_offset 14, -4 + 5956 0004 0D46 mov r5, r1 + 5957 0006 0446 mov r4, r0 +2648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + 5958 .loc 1 2648 3 is_stmt 1 view .LVU1878 +2649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + 5959 .loc 1 2649 3 view .LVU1879 +2650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + 5960 .loc 1 2650 3 view .LVU1880 +2651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + 5961 .loc 1 2651 3 view .LVU1881 +2652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + 5962 .loc 1 2652 3 view .LVU1882 +2653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5963 .loc 1 2653 3 view .LVU1883 +2655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5964 .loc 1 2655 3 view .LVU1884 +2655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5965 .loc 1 2655 11 is_stmt 0 view .LVU1885 + 5966 0008 90F83D30 ldrb r3, [r0, #61] @ zero_extendqisi2 +2655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 5967 .loc 1 2655 6 view .LVU1886 + 5968 000c FBB1 cbz r3, .L363 + 5969 .LVL449: + 5970 .L357: +2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5971 .loc 1 2677 3 is_stmt 1 view .LVU1887 +2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5972 .loc 1 2677 15 is_stmt 0 view .LVU1888 + 5973 000e 0223 movs r3, #2 + 5974 0010 84F83D30 strb r3, [r4, #61] +2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5975 .loc 1 2680 3 is_stmt 1 view .LVU1889 +2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5976 .loc 1 2680 38 is_stmt 0 view .LVU1890 + 5977 0014 2146 mov r1, r4 +2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5978 .loc 1 2680 3 view .LVU1891 + 5979 0016 51F8040B ldr r0, [r1], #4 + 5980 001a FFF7FEFF bl TIM_Base_SetConfig + 5981 .LVL450: +2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 266 + + + 5982 .loc 1 2683 3 is_stmt 1 view .LVU1892 +2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5983 .loc 1 2683 7 is_stmt 0 view .LVU1893 + 5984 001e 2268 ldr r2, [r4] +2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5985 .loc 1 2683 17 view .LVU1894 + 5986 0020 1368 ldr r3, [r2] +2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5987 .loc 1 2683 23 view .LVU1895 + 5988 0022 23F00803 bic r3, r3, #8 + 5989 0026 1360 str r3, [r2] +2686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5990 .loc 1 2686 3 is_stmt 1 view .LVU1896 +2686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5991 .loc 1 2686 7 is_stmt 0 view .LVU1897 + 5992 0028 2268 ldr r2, [r4] +2686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5993 .loc 1 2686 17 view .LVU1898 + 5994 002a 1368 ldr r3, [r2] +2686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5995 .loc 1 2686 23 view .LVU1899 + 5996 002c 2B43 orrs r3, r3, r5 + 5997 002e 1360 str r3, [r2] +2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5998 .loc 1 2689 3 is_stmt 1 view .LVU1900 +2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 5999 .loc 1 2689 23 is_stmt 0 view .LVU1901 + 6000 0030 0123 movs r3, #1 + 6001 0032 84F84830 strb r3, [r4, #72] +2692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 6002 .loc 1 2692 3 is_stmt 1 view .LVU1902 + 6003 0036 84F83E30 strb r3, [r4, #62] +2693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 6004 .loc 1 2693 3 view .LVU1903 + 6005 003a 84F83F30 strb r3, [r4, #63] +2694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 6006 .loc 1 2694 3 view .LVU1904 + 6007 003e 84F84430 strb r3, [r4, #68] +2695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6008 .loc 1 2695 3 view .LVU1905 + 6009 0042 84F84530 strb r3, [r4, #69] +2698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6010 .loc 1 2698 3 view .LVU1906 +2698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6011 .loc 1 2698 15 is_stmt 0 view .LVU1907 + 6012 0046 84F83D30 strb r3, [r4, #61] +2700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6013 .loc 1 2700 3 is_stmt 1 view .LVU1908 +2700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6014 .loc 1 2700 10 is_stmt 0 view .LVU1909 + 6015 004a 0020 movs r0, #0 +2701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6016 .loc 1 2701 1 view .LVU1910 + 6017 004c 38BD pop {r3, r4, r5, pc} + 6018 .LVL451: + 6019 .L363: +2658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 267 + + + 6020 .loc 1 2658 5 is_stmt 1 view .LVU1911 +2658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6021 .loc 1 2658 16 is_stmt 0 view .LVU1912 + 6022 004e 80F83C30 strb r3, [r0, #60] +2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 6023 .loc 1 2672 5 is_stmt 1 view .LVU1913 + 6024 0052 FFF7FEFF bl HAL_TIM_OnePulse_MspInit + 6025 .LVL452: +2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 6026 .loc 1 2672 5 is_stmt 0 view .LVU1914 + 6027 0056 DAE7 b .L357 + 6028 .LVL453: + 6029 .L358: + 6030 .LCFI58: + 6031 .cfi_def_cfa_offset 0 + 6032 .cfi_restore 3 + 6033 .cfi_restore 4 + 6034 .cfi_restore 5 + 6035 .cfi_restore 14 +2644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6036 .loc 1 2644 12 view .LVU1915 + 6037 0058 0120 movs r0, #1 + 6038 .LVL454: +2701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6039 .loc 1 2701 1 view .LVU1916 + 6040 005a 7047 bx lr + 6041 .cfi_endproc + 6042 .LFE181: + 6044 .section .text.HAL_TIM_Encoder_Init,"ax",%progbits + 6045 .align 1 + 6046 .global HAL_TIM_Encoder_Init + 6047 .syntax unified + 6048 .thumb + 6049 .thumb_func + 6051 HAL_TIM_Encoder_Init: + 6052 .LVL455: + 6053 .LFB189: +3031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 6054 .loc 1 3031 1 is_stmt 1 view -0 + 6055 .cfi_startproc + 6056 @ args = 0, pretend = 0, frame = 0 + 6057 @ frame_needed = 0, uses_anonymous_args = 0 +3032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmr1; + 6058 .loc 1 3032 3 view .LVU1918 +3033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccer; + 6059 .loc 1 3033 3 view .LVU1919 +3034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6060 .loc 1 3034 3 view .LVU1920 +3037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 6061 .loc 1 3037 3 view .LVU1921 +3037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 6062 .loc 1 3037 6 is_stmt 0 view .LVU1922 + 6063 0000 0028 cmp r0, #0 + 6064 0002 4DD0 beq .L367 +3031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 6065 .loc 1 3031 1 view .LVU1923 + 6066 0004 F8B5 push {r3, r4, r5, r6, r7, lr} + ARM GAS /tmp/ccGFzgX3.s page 268 + + + 6067 .LCFI59: + 6068 .cfi_def_cfa_offset 24 + 6069 .cfi_offset 3, -24 + 6070 .cfi_offset 4, -20 + 6071 .cfi_offset 5, -16 + 6072 .cfi_offset 6, -12 + 6073 .cfi_offset 7, -8 + 6074 .cfi_offset 14, -4 + 6075 0006 0D46 mov r5, r1 + 6076 0008 0446 mov r4, r0 +3043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + 6077 .loc 1 3043 3 is_stmt 1 view .LVU1924 +3044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + 6078 .loc 1 3044 3 view .LVU1925 +3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + 6079 .loc 1 3045 3 view .LVU1926 +3046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + 6080 .loc 1 3046 3 view .LVU1927 +3047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + 6081 .loc 1 3047 3 view .LVU1928 +3048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + 6082 .loc 1 3048 3 view .LVU1929 +3049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + 6083 .loc 1 3049 3 view .LVU1930 +3050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); + 6084 .loc 1 3050 3 view .LVU1931 +3051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + 6085 .loc 1 3051 3 view .LVU1932 +3052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + 6086 .loc 1 3052 3 view .LVU1933 +3053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + 6087 .loc 1 3053 3 view .LVU1934 +3054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + 6088 .loc 1 3054 3 view .LVU1935 +3055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + 6089 .loc 1 3055 3 view .LVU1936 +3056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6090 .loc 1 3056 3 view .LVU1937 +3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 6091 .loc 1 3058 3 view .LVU1938 +3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 6092 .loc 1 3058 11 is_stmt 0 view .LVU1939 + 6093 000a 90F83D30 ldrb r3, [r0, #61] @ zero_extendqisi2 +3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 6094 .loc 1 3058 6 view .LVU1940 + 6095 000e 002B cmp r3, #0 + 6096 0010 41D0 beq .L372 + 6097 .LVL456: + 6098 .L366: +3080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6099 .loc 1 3080 3 is_stmt 1 view .LVU1941 +3080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6100 .loc 1 3080 15 is_stmt 0 view .LVU1942 + 6101 0012 0223 movs r3, #2 + 6102 0014 84F83D30 strb r3, [r4, #61] +3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6103 .loc 1 3083 3 is_stmt 1 view .LVU1943 + ARM GAS /tmp/ccGFzgX3.s page 269 + + +3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6104 .loc 1 3083 7 is_stmt 0 view .LVU1944 + 6105 0018 2268 ldr r2, [r4] +3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6106 .loc 1 3083 17 view .LVU1945 + 6107 001a 9168 ldr r1, [r2, #8] +3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6108 .loc 1 3083 24 view .LVU1946 + 6109 001c 214B ldr r3, .L373 + 6110 001e 0B40 ands r3, r3, r1 + 6111 0020 9360 str r3, [r2, #8] +3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6112 .loc 1 3086 3 is_stmt 1 view .LVU1947 +3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6113 .loc 1 3086 38 is_stmt 0 view .LVU1948 + 6114 0022 2146 mov r1, r4 +3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6115 .loc 1 3086 3 view .LVU1949 + 6116 0024 51F8040B ldr r0, [r1], #4 + 6117 0028 FFF7FEFF bl TIM_Base_SetConfig + 6118 .LVL457: +3089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6119 .loc 1 3089 3 is_stmt 1 view .LVU1950 +3089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6120 .loc 1 3089 17 is_stmt 0 view .LVU1951 + 6121 002c 2168 ldr r1, [r4] +3089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6122 .loc 1 3089 11 view .LVU1952 + 6123 002e 8A68 ldr r2, [r1, #8] + 6124 .LVL458: +3092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6125 .loc 1 3092 3 is_stmt 1 view .LVU1953 +3092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6126 .loc 1 3092 12 is_stmt 0 view .LVU1954 + 6127 0030 8B69 ldr r3, [r1, #24] + 6128 .LVL459: +3095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6129 .loc 1 3095 3 is_stmt 1 view .LVU1955 +3095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6130 .loc 1 3095 11 is_stmt 0 view .LVU1956 + 6131 0032 0E6A ldr r6, [r1, #32] + 6132 .LVL460: +3098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6133 .loc 1 3098 3 is_stmt 1 view .LVU1957 +3098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6134 .loc 1 3098 21 is_stmt 0 view .LVU1958 + 6135 0034 2868 ldr r0, [r5] +3098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6136 .loc 1 3098 11 view .LVU1959 + 6137 0036 1043 orrs r0, r0, r2 + 6138 .LVL461: +3101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + 6139 .loc 1 3101 3 is_stmt 1 view .LVU1960 +3101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + 6140 .loc 1 3101 12 is_stmt 0 view .LVU1961 + 6141 0038 1B4A ldr r2, .L373+4 + 6142 003a 1A40 ands r2, r2, r3 + ARM GAS /tmp/ccGFzgX3.s page 270 + + + 6143 .LVL462: +3102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6144 .loc 1 3102 3 is_stmt 1 view .LVU1962 +3102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6145 .loc 1 3102 23 is_stmt 0 view .LVU1963 + 6146 003c AB68 ldr r3, [r5, #8] +3102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6147 .loc 1 3102 38 view .LVU1964 + 6148 003e AF69 ldr r7, [r5, #24] + 6149 0040 43EA0723 orr r3, r3, r7, lsl #8 +3102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6150 .loc 1 3102 12 view .LVU1965 + 6151 0044 1343 orrs r3, r3, r2 + 6152 .LVL463: +3105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + 6153 .loc 1 3105 3 is_stmt 1 view .LVU1966 +3106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + 6154 .loc 1 3106 3 view .LVU1967 +3106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + 6155 .loc 1 3106 12 is_stmt 0 view .LVU1968 + 6156 0046 194A ldr r2, .L373+8 + 6157 0048 1A40 ands r2, r2, r3 + 6158 .LVL464: +3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + 6159 .loc 1 3107 3 is_stmt 1 view .LVU1969 +3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + 6160 .loc 1 3107 22 is_stmt 0 view .LVU1970 + 6161 004a EB68 ldr r3, [r5, #12] +3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + 6162 .loc 1 3107 37 view .LVU1971 + 6163 004c EF69 ldr r7, [r5, #28] + 6164 004e 43EA0723 orr r3, r3, r7, lsl #8 +3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + 6165 .loc 1 3107 12 view .LVU1972 + 6166 0052 1A43 orrs r2, r2, r3 + 6167 .LVL465: +3108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6168 .loc 1 3108 3 is_stmt 1 view .LVU1973 +3108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6169 .loc 1 3108 52 is_stmt 0 view .LVU1974 + 6170 0054 2B6A ldr r3, [r5, #32] +3108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6171 .loc 1 3108 64 view .LVU1975 + 6172 0056 1B03 lsls r3, r3, #12 +3108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6173 .loc 1 3108 42 view .LVU1976 + 6174 0058 2F69 ldr r7, [r5, #16] + 6175 005a 43EA0713 orr r3, r3, r7, lsl #4 +3108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6176 .loc 1 3108 12 view .LVU1977 + 6177 005e 1343 orrs r3, r3, r2 + 6178 .LVL466: +3111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + 6179 .loc 1 3111 3 is_stmt 1 view .LVU1978 +3112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + 6180 .loc 1 3112 3 view .LVU1979 +3112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + ARM GAS /tmp/ccGFzgX3.s page 271 + + + 6181 .loc 1 3112 11 is_stmt 0 view .LVU1980 + 6182 0060 26F0AA06 bic r6, r6, #170 + 6183 .LVL467: +3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6184 .loc 1 3113 3 is_stmt 1 view .LVU1981 +3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6185 .loc 1 3113 21 is_stmt 0 view .LVU1982 + 6186 0064 6A68 ldr r2, [r5, #4] +3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6187 .loc 1 3113 45 view .LVU1983 + 6188 0066 6D69 ldr r5, [r5, #20] + 6189 .LVL468: +3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6190 .loc 1 3113 35 view .LVU1984 + 6191 0068 42EA0512 orr r2, r2, r5, lsl #4 +3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6192 .loc 1 3113 11 view .LVU1985 + 6193 006c 3243 orrs r2, r2, r6 + 6194 .LVL469: +3116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6195 .loc 1 3116 3 is_stmt 1 view .LVU1986 +3116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6196 .loc 1 3116 24 is_stmt 0 view .LVU1987 + 6197 006e 8860 str r0, [r1, #8] +3119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6198 .loc 1 3119 3 is_stmt 1 view .LVU1988 +3119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6199 .loc 1 3119 7 is_stmt 0 view .LVU1989 + 6200 0070 2168 ldr r1, [r4] +3119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6201 .loc 1 3119 25 view .LVU1990 + 6202 0072 8B61 str r3, [r1, #24] +3122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6203 .loc 1 3122 3 is_stmt 1 view .LVU1991 +3122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6204 .loc 1 3122 7 is_stmt 0 view .LVU1992 + 6205 0074 2368 ldr r3, [r4] + 6206 .LVL470: +3122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6207 .loc 1 3122 24 view .LVU1993 + 6208 0076 1A62 str r2, [r3, #32] + 6209 .LVL471: +3125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6210 .loc 1 3125 3 is_stmt 1 view .LVU1994 +3125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6211 .loc 1 3125 23 is_stmt 0 view .LVU1995 + 6212 0078 0123 movs r3, #1 + 6213 007a 84F84830 strb r3, [r4, #72] +3128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 6214 .loc 1 3128 3 is_stmt 1 view .LVU1996 + 6215 007e 84F83E30 strb r3, [r4, #62] +3129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 6216 .loc 1 3129 3 view .LVU1997 + 6217 0082 84F83F30 strb r3, [r4, #63] +3130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 6218 .loc 1 3130 3 view .LVU1998 + 6219 0086 84F84430 strb r3, [r4, #68] + ARM GAS /tmp/ccGFzgX3.s page 272 + + +3131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6220 .loc 1 3131 3 view .LVU1999 + 6221 008a 84F84530 strb r3, [r4, #69] +3134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6222 .loc 1 3134 3 view .LVU2000 +3134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6223 .loc 1 3134 15 is_stmt 0 view .LVU2001 + 6224 008e 84F83D30 strb r3, [r4, #61] +3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6225 .loc 1 3136 3 is_stmt 1 view .LVU2002 +3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6226 .loc 1 3136 10 is_stmt 0 view .LVU2003 + 6227 0092 0020 movs r0, #0 + 6228 .LVL472: +3137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6229 .loc 1 3137 1 view .LVU2004 + 6230 0094 F8BD pop {r3, r4, r5, r6, r7, pc} + 6231 .LVL473: + 6232 .L372: +3061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6233 .loc 1 3061 5 is_stmt 1 view .LVU2005 +3061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6234 .loc 1 3061 16 is_stmt 0 view .LVU2006 + 6235 0096 80F83C30 strb r3, [r0, #60] +3075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 6236 .loc 1 3075 5 is_stmt 1 view .LVU2007 + 6237 009a FFF7FEFF bl HAL_TIM_Encoder_MspInit + 6238 .LVL474: +3075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 6239 .loc 1 3075 5 is_stmt 0 view .LVU2008 + 6240 009e B8E7 b .L366 + 6241 .LVL475: + 6242 .L367: + 6243 .LCFI60: + 6244 .cfi_def_cfa_offset 0 + 6245 .cfi_restore 3 + 6246 .cfi_restore 4 + 6247 .cfi_restore 5 + 6248 .cfi_restore 6 + 6249 .cfi_restore 7 + 6250 .cfi_restore 14 +3039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6251 .loc 1 3039 12 view .LVU2009 + 6252 00a0 0120 movs r0, #1 + 6253 .LVL476: +3137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6254 .loc 1 3137 1 view .LVU2010 + 6255 00a2 7047 bx lr + 6256 .L374: + 6257 .align 2 + 6258 .L373: + 6259 00a4 F8BFFEFF .word -81928 + 6260 00a8 FCFCFFFF .word -772 + 6261 00ac 0303FFFF .word -64765 + 6262 .cfi_endproc + 6263 .LFE189: + 6265 .section .text.TIM_OC2_SetConfig,"ax",%progbits + ARM GAS /tmp/ccGFzgX3.s page 273 + + + 6266 .align 1 + 6267 .global TIM_OC2_SetConfig + 6268 .syntax unified + 6269 .thumb + 6270 .thumb_func + 6272 TIM_OC2_SetConfig: + 6273 .LVL477: + 6274 .LFB247: +7062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmrx; + 6275 .loc 1 7062 1 is_stmt 1 view -0 + 6276 .cfi_startproc + 6277 @ args = 0, pretend = 0, frame = 0 + 6278 @ frame_needed = 0, uses_anonymous_args = 0 + 6279 @ link register save eliminated. +7062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmrx; + 6280 .loc 1 7062 1 is_stmt 0 view .LVU2012 + 6281 0000 70B4 push {r4, r5, r6} + 6282 .LCFI61: + 6283 .cfi_def_cfa_offset 12 + 6284 .cfi_offset 4, -12 + 6285 .cfi_offset 5, -8 + 6286 .cfi_offset 6, -4 +7063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccer; + 6287 .loc 1 7063 3 is_stmt 1 view .LVU2013 +7064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpcr2; + 6288 .loc 1 7064 3 view .LVU2014 +7065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6289 .loc 1 7065 3 view .LVU2015 +7068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6290 .loc 1 7068 3 view .LVU2016 +7068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6291 .loc 1 7068 11 is_stmt 0 view .LVU2017 + 6292 0002 036A ldr r3, [r0, #32] + 6293 .LVL478: +7071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6294 .loc 1 7071 3 is_stmt 1 view .LVU2018 +7071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6295 .loc 1 7071 7 is_stmt 0 view .LVU2019 + 6296 0004 026A ldr r2, [r0, #32] +7071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6297 .loc 1 7071 14 view .LVU2020 + 6298 0006 22F01002 bic r2, r2, #16 + 6299 000a 0262 str r2, [r0, #32] +7074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6300 .loc 1 7074 3 is_stmt 1 view .LVU2021 +7074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6301 .loc 1 7074 10 is_stmt 0 view .LVU2022 + 6302 000c 4268 ldr r2, [r0, #4] + 6303 .LVL479: +7077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6304 .loc 1 7077 3 is_stmt 1 view .LVU2023 +7077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6305 .loc 1 7077 12 is_stmt 0 view .LVU2024 + 6306 000e 8569 ldr r5, [r0, #24] + 6307 .LVL480: +7080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR1_CC2S; + 6308 .loc 1 7080 3 is_stmt 1 view .LVU2025 + ARM GAS /tmp/ccGFzgX3.s page 274 + + +7081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6309 .loc 1 7081 3 view .LVU2026 +7081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6310 .loc 1 7081 12 is_stmt 0 view .LVU2027 + 6311 0010 144C ldr r4, .L379 + 6312 0012 2C40 ands r4, r4, r5 + 6313 .LVL481: +7084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6314 .loc 1 7084 3 is_stmt 1 view .LVU2028 +7084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6315 .loc 1 7084 25 is_stmt 0 view .LVU2029 + 6316 0014 0D68 ldr r5, [r1] +7084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6317 .loc 1 7084 12 view .LVU2030 + 6318 0016 44EA0525 orr r5, r4, r5, lsl #8 + 6319 .LVL482: +7087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output Compare Polarity */ + 6320 .loc 1 7087 3 is_stmt 1 view .LVU2031 +7087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output Compare Polarity */ + 6321 .loc 1 7087 11 is_stmt 0 view .LVU2032 + 6322 001a 23F02003 bic r3, r3, #32 + 6323 .LVL483: +7089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6324 .loc 1 7089 3 is_stmt 1 view .LVU2033 +7089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6325 .loc 1 7089 24 is_stmt 0 view .LVU2034 + 6326 001e 8C68 ldr r4, [r1, #8] +7089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6327 .loc 1 7089 11 view .LVU2035 + 6328 0020 43EA0413 orr r3, r3, r4, lsl #4 + 6329 .LVL484: +7091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 6330 .loc 1 7091 3 is_stmt 1 view .LVU2036 +7091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 6331 .loc 1 7091 7 is_stmt 0 view .LVU2037 + 6332 0024 104C ldr r4, .L379+4 + 6333 0026 114E ldr r6, .L379+8 +7091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 6334 .loc 1 7091 6 view .LVU2038 + 6335 0028 B042 cmp r0, r6 + 6336 002a 18BF it ne + 6337 002c A042 cmpne r0, r4 + 6338 002e 0CBF ite eq + 6339 0030 0124 moveq r4, #1 + 6340 0032 0024 movne r4, #0 + 6341 0034 06D1 bne .L376 +7093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6342 .loc 1 7093 5 is_stmt 1 view .LVU2039 +7096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output N Polarity */ + 6343 .loc 1 7096 5 view .LVU2040 +7096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output N Polarity */ + 6344 .loc 1 7096 13 is_stmt 0 view .LVU2041 + 6345 0036 23F08003 bic r3, r3, #128 + 6346 .LVL485: +7098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output N State */ + 6347 .loc 1 7098 5 is_stmt 1 view .LVU2042 +7098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output N State */ + ARM GAS /tmp/ccGFzgX3.s page 275 + + + 6348 .loc 1 7098 26 is_stmt 0 view .LVU2043 + 6349 003a CE68 ldr r6, [r1, #12] +7098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the Output N State */ + 6350 .loc 1 7098 13 view .LVU2044 + 6351 003c 43EA0613 orr r3, r3, r6, lsl #4 + 6352 .LVL486: +7100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6353 .loc 1 7100 5 is_stmt 1 view .LVU2045 +7100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6354 .loc 1 7100 13 is_stmt 0 view .LVU2046 + 6355 0040 23F04003 bic r3, r3, #64 + 6356 .LVL487: + 6357 .L376: +7103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 6358 .loc 1 7103 3 is_stmt 1 view .LVU2047 +7103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 6359 .loc 1 7103 6 is_stmt 0 view .LVU2048 + 6360 0044 3CB1 cbz r4, .L377 +7106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + 6361 .loc 1 7106 5 is_stmt 1 view .LVU2049 +7107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6362 .loc 1 7107 5 view .LVU2050 +7110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_OIS2N; + 6363 .loc 1 7110 5 view .LVU2051 + 6364 .LVL488: +7111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output Idle state */ + 6365 .loc 1 7111 5 view .LVU2052 +7111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output Idle state */ + 6366 .loc 1 7111 12 is_stmt 0 view .LVU2053 + 6367 0046 22F44062 bic r2, r2, #3072 + 6368 .LVL489: +7113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output N Idle state */ + 6369 .loc 1 7113 5 is_stmt 1 view .LVU2054 +7113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output N Idle state */ + 6370 .loc 1 7113 25 is_stmt 0 view .LVU2055 + 6371 004a 4C69 ldr r4, [r1, #20] +7113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Output N Idle state */ + 6372 .loc 1 7113 12 view .LVU2056 + 6373 004c 42EA8402 orr r2, r2, r4, lsl #2 + 6374 .LVL490: +7115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6375 .loc 1 7115 5 is_stmt 1 view .LVU2057 +7115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6376 .loc 1 7115 25 is_stmt 0 view .LVU2058 + 6377 0050 8C69 ldr r4, [r1, #24] +7115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6378 .loc 1 7115 12 view .LVU2059 + 6379 0052 42EA8402 orr r2, r2, r4, lsl #2 + 6380 .LVL491: + 6381 .L377: +7119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6382 .loc 1 7119 3 is_stmt 1 view .LVU2060 +7119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6383 .loc 1 7119 13 is_stmt 0 view .LVU2061 + 6384 0056 4260 str r2, [r0, #4] +7122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6385 .loc 1 7122 3 is_stmt 1 view .LVU2062 + ARM GAS /tmp/ccGFzgX3.s page 276 + + +7122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6386 .loc 1 7122 15 is_stmt 0 view .LVU2063 + 6387 0058 8561 str r5, [r0, #24] +7125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6388 .loc 1 7125 3 is_stmt 1 view .LVU2064 +7125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6389 .loc 1 7125 25 is_stmt 0 view .LVU2065 + 6390 005a 4A68 ldr r2, [r1, #4] + 6391 .LVL492: +7125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6392 .loc 1 7125 14 view .LVU2066 + 6393 005c 8263 str r2, [r0, #56] +7128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6394 .loc 1 7128 3 is_stmt 1 view .LVU2067 +7128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6395 .loc 1 7128 14 is_stmt 0 view .LVU2068 + 6396 005e 0362 str r3, [r0, #32] +7129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6397 .loc 1 7129 1 view .LVU2069 + 6398 0060 70BC pop {r4, r5, r6} + 6399 .LCFI62: + 6400 .cfi_restore 6 + 6401 .cfi_restore 5 + 6402 .cfi_restore 4 + 6403 .cfi_def_cfa_offset 0 + 6404 .LVL493: +7129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6405 .loc 1 7129 1 view .LVU2070 + 6406 0062 7047 bx lr + 6407 .L380: + 6408 .align 2 + 6409 .L379: + 6410 0064 FF8CFFFE .word -16806657 + 6411 0068 00000140 .word 1073807360 + 6412 006c 00040140 .word 1073808384 + 6413 .cfi_endproc + 6414 .LFE247: + 6416 .section .text.HAL_TIM_OC_ConfigChannel,"ax",%progbits + 6417 .align 1 + 6418 .global HAL_TIM_OC_ConfigChannel + 6419 .syntax unified + 6420 .thumb + 6421 .thumb_func + 6423 HAL_TIM_OC_ConfigChannel: + 6424 .LVL494: + 6425 .LFB200: +4071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 6426 .loc 1 4071 1 is_stmt 1 view -0 + 6427 .cfi_startproc + 6428 @ args = 0, pretend = 0, frame = 0 + 6429 @ frame_needed = 0, uses_anonymous_args = 0 +4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6430 .loc 1 4072 3 view .LVU2072 +4075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + 6431 .loc 1 4075 3 view .LVU2073 +4076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + 6432 .loc 1 4076 3 view .LVU2074 + ARM GAS /tmp/ccGFzgX3.s page 277 + + +4077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6433 .loc 1 4077 3 view .LVU2075 +4080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6434 .loc 1 4080 3 view .LVU2076 +4080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6435 .loc 1 4080 3 view .LVU2077 + 6436 0000 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 6437 0004 012B cmp r3, #1 + 6438 0006 36D0 beq .L391 +4071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 6439 .loc 1 4071 1 is_stmt 0 view .LVU2078 + 6440 0008 10B5 push {r4, lr} + 6441 .LCFI63: + 6442 .cfi_def_cfa_offset 8 + 6443 .cfi_offset 4, -8 + 6444 .cfi_offset 14, -4 + 6445 000a 0446 mov r4, r0 +4080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6446 .loc 1 4080 3 is_stmt 1 discriminator 2 view .LVU2079 + 6447 000c 0123 movs r3, #1 + 6448 000e 80F83C30 strb r3, [r0, #60] +4080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6449 .loc 1 4080 3 discriminator 2 view .LVU2080 +4082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 6450 .loc 1 4082 3 view .LVU2081 + 6451 0012 142A cmp r2, #20 + 6452 0014 2AD8 bhi .L392 + 6453 0016 DFE802F0 tbb [pc, r2] + 6454 .L385: + 6455 001a 0B .byte (.L390-.L385)/2 + 6456 001b 29 .byte (.L392-.L385)/2 + 6457 001c 29 .byte (.L392-.L385)/2 + 6458 001d 29 .byte (.L392-.L385)/2 + 6459 001e 10 .byte (.L389-.L385)/2 + 6460 001f 29 .byte (.L392-.L385)/2 + 6461 0020 29 .byte (.L392-.L385)/2 + 6462 0021 29 .byte (.L392-.L385)/2 + 6463 0022 15 .byte (.L388-.L385)/2 + 6464 0023 29 .byte (.L392-.L385)/2 + 6465 0024 29 .byte (.L392-.L385)/2 + 6466 0025 29 .byte (.L392-.L385)/2 + 6467 0026 1A .byte (.L387-.L385)/2 + 6468 0027 29 .byte (.L392-.L385)/2 + 6469 0028 29 .byte (.L392-.L385)/2 + 6470 0029 29 .byte (.L392-.L385)/2 + 6471 002a 1F .byte (.L386-.L385)/2 + 6472 002b 29 .byte (.L392-.L385)/2 + 6473 002c 29 .byte (.L392-.L385)/2 + 6474 002d 29 .byte (.L392-.L385)/2 + 6475 002e 24 .byte (.L384-.L385)/2 + 6476 002f 00 .p2align 1 + 6477 .L390: +4087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6478 .loc 1 4087 7 view .LVU2082 +4090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6479 .loc 1 4090 7 view .LVU2083 + 6480 0030 0068 ldr r0, [r0] + ARM GAS /tmp/ccGFzgX3.s page 278 + + + 6481 .LVL495: +4090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6482 .loc 1 4090 7 is_stmt 0 view .LVU2084 + 6483 0032 FFF7FEFF bl TIM_OC1_SetConfig + 6484 .LVL496: +4091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6485 .loc 1 4091 7 is_stmt 1 view .LVU2085 +4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6486 .loc 1 4072 21 is_stmt 0 view .LVU2086 + 6487 0036 0020 movs r0, #0 +4091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6488 .loc 1 4091 7 view .LVU2087 + 6489 0038 19E0 b .L383 + 6490 .LVL497: + 6491 .L389: +4097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6492 .loc 1 4097 7 is_stmt 1 view .LVU2088 +4100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6493 .loc 1 4100 7 view .LVU2089 + 6494 003a 0068 ldr r0, [r0] + 6495 .LVL498: +4100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6496 .loc 1 4100 7 is_stmt 0 view .LVU2090 + 6497 003c FFF7FEFF bl TIM_OC2_SetConfig + 6498 .LVL499: +4101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6499 .loc 1 4101 7 is_stmt 1 view .LVU2091 +4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6500 .loc 1 4072 21 is_stmt 0 view .LVU2092 + 6501 0040 0020 movs r0, #0 +4101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6502 .loc 1 4101 7 view .LVU2093 + 6503 0042 14E0 b .L383 + 6504 .LVL500: + 6505 .L388: +4107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6506 .loc 1 4107 7 is_stmt 1 view .LVU2094 +4110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6507 .loc 1 4110 7 view .LVU2095 + 6508 0044 0068 ldr r0, [r0] + 6509 .LVL501: +4110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6510 .loc 1 4110 7 is_stmt 0 view .LVU2096 + 6511 0046 FFF7FEFF bl TIM_OC3_SetConfig + 6512 .LVL502: +4111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6513 .loc 1 4111 7 is_stmt 1 view .LVU2097 +4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6514 .loc 1 4072 21 is_stmt 0 view .LVU2098 + 6515 004a 0020 movs r0, #0 +4111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6516 .loc 1 4111 7 view .LVU2099 + 6517 004c 0FE0 b .L383 + 6518 .LVL503: + 6519 .L387: +4117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6520 .loc 1 4117 7 is_stmt 1 view .LVU2100 + ARM GAS /tmp/ccGFzgX3.s page 279 + + +4120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6521 .loc 1 4120 7 view .LVU2101 + 6522 004e 0068 ldr r0, [r0] + 6523 .LVL504: +4120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6524 .loc 1 4120 7 is_stmt 0 view .LVU2102 + 6525 0050 FFF7FEFF bl TIM_OC4_SetConfig + 6526 .LVL505: +4121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6527 .loc 1 4121 7 is_stmt 1 view .LVU2103 +4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6528 .loc 1 4072 21 is_stmt 0 view .LVU2104 + 6529 0054 0020 movs r0, #0 +4121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6530 .loc 1 4121 7 view .LVU2105 + 6531 0056 0AE0 b .L383 + 6532 .LVL506: + 6533 .L386: +4127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6534 .loc 1 4127 7 is_stmt 1 view .LVU2106 +4130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6535 .loc 1 4130 7 view .LVU2107 + 6536 0058 0068 ldr r0, [r0] + 6537 .LVL507: +4130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6538 .loc 1 4130 7 is_stmt 0 view .LVU2108 + 6539 005a FFF7FEFF bl TIM_OC5_SetConfig + 6540 .LVL508: +4131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6541 .loc 1 4131 7 is_stmt 1 view .LVU2109 +4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6542 .loc 1 4072 21 is_stmt 0 view .LVU2110 + 6543 005e 0020 movs r0, #0 +4131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6544 .loc 1 4131 7 view .LVU2111 + 6545 0060 05E0 b .L383 + 6546 .LVL509: + 6547 .L384: +4137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6548 .loc 1 4137 7 is_stmt 1 view .LVU2112 +4140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6549 .loc 1 4140 7 view .LVU2113 + 6550 0062 0068 ldr r0, [r0] + 6551 .LVL510: +4140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6552 .loc 1 4140 7 is_stmt 0 view .LVU2114 + 6553 0064 FFF7FEFF bl TIM_OC6_SetConfig + 6554 .LVL511: +4141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6555 .loc 1 4141 7 is_stmt 1 view .LVU2115 +4072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6556 .loc 1 4072 21 is_stmt 0 view .LVU2116 + 6557 0068 0020 movs r0, #0 +4141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6558 .loc 1 4141 7 view .LVU2117 + 6559 006a 00E0 b .L383 + 6560 .LVL512: + ARM GAS /tmp/ccGFzgX3.s page 280 + + + 6561 .L392: +4082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 6562 .loc 1 4082 3 view .LVU2118 + 6563 006c 0120 movs r0, #1 + 6564 .LVL513: + 6565 .L383: +4149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6566 .loc 1 4149 3 is_stmt 1 view .LVU2119 +4149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6567 .loc 1 4149 3 view .LVU2120 + 6568 006e 0023 movs r3, #0 + 6569 0070 84F83C30 strb r3, [r4, #60] +4149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6570 .loc 1 4149 3 view .LVU2121 +4151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6571 .loc 1 4151 3 view .LVU2122 +4152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6572 .loc 1 4152 1 is_stmt 0 view .LVU2123 + 6573 0074 10BD pop {r4, pc} + 6574 .LVL514: + 6575 .L391: + 6576 .LCFI64: + 6577 .cfi_def_cfa_offset 0 + 6578 .cfi_restore 4 + 6579 .cfi_restore 14 +4080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6580 .loc 1 4080 3 discriminator 1 view .LVU2124 + 6581 0076 0220 movs r0, #2 + 6582 .LVL515: +4152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6583 .loc 1 4152 1 view .LVU2125 + 6584 0078 7047 bx lr + 6585 .cfi_endproc + 6586 .LFE200: + 6588 .section .text.HAL_TIM_PWM_ConfigChannel,"ax",%progbits + 6589 .align 1 + 6590 .global HAL_TIM_PWM_ConfigChannel + 6591 .syntax unified + 6592 .thumb + 6593 .thumb_func + 6595 HAL_TIM_PWM_ConfigChannel: + 6596 .LVL516: + 6597 .LFB202: +4271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 6598 .loc 1 4271 1 is_stmt 1 view -0 + 6599 .cfi_startproc + 6600 @ args = 0, pretend = 0, frame = 0 + 6601 @ frame_needed = 0, uses_anonymous_args = 0 +4271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 6602 .loc 1 4271 1 is_stmt 0 view .LVU2127 + 6603 0000 38B5 push {r3, r4, r5, lr} + 6604 .LCFI65: + 6605 .cfi_def_cfa_offset 16 + 6606 .cfi_offset 3, -16 + 6607 .cfi_offset 4, -12 + 6608 .cfi_offset 5, -8 + 6609 .cfi_offset 14, -4 + ARM GAS /tmp/ccGFzgX3.s page 281 + + +4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6610 .loc 1 4272 3 is_stmt 1 view .LVU2128 + 6611 .LVL517: +4275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + 6612 .loc 1 4275 3 view .LVU2129 +4276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + 6613 .loc 1 4276 3 view .LVU2130 +4277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + 6614 .loc 1 4277 3 view .LVU2131 +4278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6615 .loc 1 4278 3 view .LVU2132 +4281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6616 .loc 1 4281 3 view .LVU2133 +4281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6617 .loc 1 4281 3 view .LVU2134 + 6618 0002 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 6619 0006 012B cmp r3, #1 + 6620 0008 00F09580 beq .L407 + 6621 000c 0446 mov r4, r0 + 6622 000e 0D46 mov r5, r1 +4281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6623 .loc 1 4281 3 discriminator 2 view .LVU2135 + 6624 0010 0123 movs r3, #1 + 6625 0012 80F83C30 strb r3, [r0, #60] +4281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6626 .loc 1 4281 3 discriminator 2 view .LVU2136 +4283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 6627 .loc 1 4283 3 view .LVU2137 + 6628 0016 142A cmp r2, #20 + 6629 0018 00F28880 bhi .L408 + 6630 001c DFE802F0 tbb [pc, r2] + 6631 .L401: + 6632 0020 0B .byte (.L406-.L401)/2 + 6633 0021 86 .byte (.L408-.L401)/2 + 6634 0022 86 .byte (.L408-.L401)/2 + 6635 0023 86 .byte (.L408-.L401)/2 + 6636 0024 1F .byte (.L405-.L401)/2 + 6637 0025 86 .byte (.L408-.L401)/2 + 6638 0026 86 .byte (.L408-.L401)/2 + 6639 0027 86 .byte (.L408-.L401)/2 + 6640 0028 34 .byte (.L404-.L401)/2 + 6641 0029 86 .byte (.L408-.L401)/2 + 6642 002a 86 .byte (.L408-.L401)/2 + 6643 002b 86 .byte (.L408-.L401)/2 + 6644 002c 48 .byte (.L403-.L401)/2 + 6645 002d 86 .byte (.L408-.L401)/2 + 6646 002e 86 .byte (.L408-.L401)/2 + 6647 002f 86 .byte (.L408-.L401)/2 + 6648 0030 5D .byte (.L402-.L401)/2 + 6649 0031 86 .byte (.L408-.L401)/2 + 6650 0032 86 .byte (.L408-.L401)/2 + 6651 0033 86 .byte (.L408-.L401)/2 + 6652 0034 71 .byte (.L400-.L401)/2 + 6653 0035 00 .p2align 1 + 6654 .L406: +4288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6655 .loc 1 4288 7 view .LVU2138 + ARM GAS /tmp/ccGFzgX3.s page 282 + + +4291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6656 .loc 1 4291 7 view .LVU2139 + 6657 0036 0068 ldr r0, [r0] + 6658 .LVL518: +4291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6659 .loc 1 4291 7 is_stmt 0 view .LVU2140 + 6660 0038 FFF7FEFF bl TIM_OC1_SetConfig + 6661 .LVL519: +4294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6662 .loc 1 4294 7 is_stmt 1 view .LVU2141 +4294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6663 .loc 1 4294 11 is_stmt 0 view .LVU2142 + 6664 003c 2268 ldr r2, [r4] +4294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6665 .loc 1 4294 21 view .LVU2143 + 6666 003e 9369 ldr r3, [r2, #24] +4294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6667 .loc 1 4294 29 view .LVU2144 + 6668 0040 43F00803 orr r3, r3, #8 + 6669 0044 9361 str r3, [r2, #24] +4297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 |= sConfig->OCFastMode; + 6670 .loc 1 4297 7 is_stmt 1 view .LVU2145 +4297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 |= sConfig->OCFastMode; + 6671 .loc 1 4297 11 is_stmt 0 view .LVU2146 + 6672 0046 2268 ldr r2, [r4] +4297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 |= sConfig->OCFastMode; + 6673 .loc 1 4297 21 view .LVU2147 + 6674 0048 9369 ldr r3, [r2, #24] +4297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 |= sConfig->OCFastMode; + 6675 .loc 1 4297 29 view .LVU2148 + 6676 004a 23F00403 bic r3, r3, #4 + 6677 004e 9361 str r3, [r2, #24] +4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6678 .loc 1 4298 7 is_stmt 1 view .LVU2149 +4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6679 .loc 1 4298 11 is_stmt 0 view .LVU2150 + 6680 0050 2268 ldr r2, [r4] +4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6681 .loc 1 4298 21 view .LVU2151 + 6682 0052 9369 ldr r3, [r2, #24] +4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6683 .loc 1 4298 39 view .LVU2152 + 6684 0054 2969 ldr r1, [r5, #16] +4298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6685 .loc 1 4298 29 view .LVU2153 + 6686 0056 0B43 orrs r3, r3, r1 + 6687 0058 9361 str r3, [r2, #24] +4299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6688 .loc 1 4299 7 is_stmt 1 view .LVU2154 +4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6689 .loc 1 4272 21 is_stmt 0 view .LVU2155 + 6690 005a 0020 movs r0, #0 +4299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6691 .loc 1 4299 7 view .LVU2156 + 6692 005c 67E0 b .L399 + 6693 .LVL520: + 6694 .L405: + ARM GAS /tmp/ccGFzgX3.s page 283 + + +4305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6695 .loc 1 4305 7 is_stmt 1 view .LVU2157 +4308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6696 .loc 1 4308 7 view .LVU2158 + 6697 005e 0068 ldr r0, [r0] + 6698 .LVL521: +4308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6699 .loc 1 4308 7 is_stmt 0 view .LVU2159 + 6700 0060 FFF7FEFF bl TIM_OC2_SetConfig + 6701 .LVL522: +4311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6702 .loc 1 4311 7 is_stmt 1 view .LVU2160 +4311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6703 .loc 1 4311 11 is_stmt 0 view .LVU2161 + 6704 0064 2268 ldr r2, [r4] +4311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6705 .loc 1 4311 21 view .LVU2162 + 6706 0066 9369 ldr r3, [r2, #24] +4311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6707 .loc 1 4311 29 view .LVU2163 + 6708 0068 43F40063 orr r3, r3, #2048 + 6709 006c 9361 str r3, [r2, #24] +4314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + 6710 .loc 1 4314 7 is_stmt 1 view .LVU2164 +4314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + 6711 .loc 1 4314 11 is_stmt 0 view .LVU2165 + 6712 006e 2268 ldr r2, [r4] +4314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + 6713 .loc 1 4314 21 view .LVU2166 + 6714 0070 9369 ldr r3, [r2, #24] +4314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + 6715 .loc 1 4314 29 view .LVU2167 + 6716 0072 23F48063 bic r3, r3, #1024 + 6717 0076 9361 str r3, [r2, #24] +4315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6718 .loc 1 4315 7 is_stmt 1 view .LVU2168 +4315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6719 .loc 1 4315 11 is_stmt 0 view .LVU2169 + 6720 0078 2268 ldr r2, [r4] +4315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6721 .loc 1 4315 21 view .LVU2170 + 6722 007a 9369 ldr r3, [r2, #24] +4315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6723 .loc 1 4315 39 view .LVU2171 + 6724 007c 2969 ldr r1, [r5, #16] +4315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6725 .loc 1 4315 29 view .LVU2172 + 6726 007e 43EA0123 orr r3, r3, r1, lsl #8 + 6727 0082 9361 str r3, [r2, #24] +4316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6728 .loc 1 4316 7 is_stmt 1 view .LVU2173 +4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6729 .loc 1 4272 21 is_stmt 0 view .LVU2174 + 6730 0084 0020 movs r0, #0 +4316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6731 .loc 1 4316 7 view .LVU2175 + 6732 0086 52E0 b .L399 + ARM GAS /tmp/ccGFzgX3.s page 284 + + + 6733 .LVL523: + 6734 .L404: +4322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6735 .loc 1 4322 7 is_stmt 1 view .LVU2176 +4325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6736 .loc 1 4325 7 view .LVU2177 + 6737 0088 0068 ldr r0, [r0] + 6738 .LVL524: +4325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6739 .loc 1 4325 7 is_stmt 0 view .LVU2178 + 6740 008a FFF7FEFF bl TIM_OC3_SetConfig + 6741 .LVL525: +4328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6742 .loc 1 4328 7 is_stmt 1 view .LVU2179 +4328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6743 .loc 1 4328 11 is_stmt 0 view .LVU2180 + 6744 008e 2268 ldr r2, [r4] +4328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6745 .loc 1 4328 21 view .LVU2181 + 6746 0090 D369 ldr r3, [r2, #28] +4328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6747 .loc 1 4328 29 view .LVU2182 + 6748 0092 43F00803 orr r3, r3, #8 + 6749 0096 D361 str r3, [r2, #28] +4331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR2 |= sConfig->OCFastMode; + 6750 .loc 1 4331 7 is_stmt 1 view .LVU2183 +4331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR2 |= sConfig->OCFastMode; + 6751 .loc 1 4331 11 is_stmt 0 view .LVU2184 + 6752 0098 2268 ldr r2, [r4] +4331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR2 |= sConfig->OCFastMode; + 6753 .loc 1 4331 21 view .LVU2185 + 6754 009a D369 ldr r3, [r2, #28] +4331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR2 |= sConfig->OCFastMode; + 6755 .loc 1 4331 29 view .LVU2186 + 6756 009c 23F00403 bic r3, r3, #4 + 6757 00a0 D361 str r3, [r2, #28] +4332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6758 .loc 1 4332 7 is_stmt 1 view .LVU2187 +4332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6759 .loc 1 4332 11 is_stmt 0 view .LVU2188 + 6760 00a2 2268 ldr r2, [r4] +4332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6761 .loc 1 4332 21 view .LVU2189 + 6762 00a4 D369 ldr r3, [r2, #28] +4332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6763 .loc 1 4332 39 view .LVU2190 + 6764 00a6 2969 ldr r1, [r5, #16] +4332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6765 .loc 1 4332 29 view .LVU2191 + 6766 00a8 0B43 orrs r3, r3, r1 + 6767 00aa D361 str r3, [r2, #28] +4333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6768 .loc 1 4333 7 is_stmt 1 view .LVU2192 +4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6769 .loc 1 4272 21 is_stmt 0 view .LVU2193 + 6770 00ac 0020 movs r0, #0 +4333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + ARM GAS /tmp/ccGFzgX3.s page 285 + + + 6771 .loc 1 4333 7 view .LVU2194 + 6772 00ae 3EE0 b .L399 + 6773 .LVL526: + 6774 .L403: +4339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6775 .loc 1 4339 7 is_stmt 1 view .LVU2195 +4342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6776 .loc 1 4342 7 view .LVU2196 + 6777 00b0 0068 ldr r0, [r0] + 6778 .LVL527: +4342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6779 .loc 1 4342 7 is_stmt 0 view .LVU2197 + 6780 00b2 FFF7FEFF bl TIM_OC4_SetConfig + 6781 .LVL528: +4345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6782 .loc 1 4345 7 is_stmt 1 view .LVU2198 +4345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6783 .loc 1 4345 11 is_stmt 0 view .LVU2199 + 6784 00b6 2268 ldr r2, [r4] +4345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6785 .loc 1 4345 21 view .LVU2200 + 6786 00b8 D369 ldr r3, [r2, #28] +4345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6787 .loc 1 4345 29 view .LVU2201 + 6788 00ba 43F40063 orr r3, r3, #2048 + 6789 00be D361 str r3, [r2, #28] +4348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + 6790 .loc 1 4348 7 is_stmt 1 view .LVU2202 +4348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + 6791 .loc 1 4348 11 is_stmt 0 view .LVU2203 + 6792 00c0 2268 ldr r2, [r4] +4348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + 6793 .loc 1 4348 21 view .LVU2204 + 6794 00c2 D369 ldr r3, [r2, #28] +4348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + 6795 .loc 1 4348 29 view .LVU2205 + 6796 00c4 23F48063 bic r3, r3, #1024 + 6797 00c8 D361 str r3, [r2, #28] +4349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6798 .loc 1 4349 7 is_stmt 1 view .LVU2206 +4349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6799 .loc 1 4349 11 is_stmt 0 view .LVU2207 + 6800 00ca 2268 ldr r2, [r4] +4349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6801 .loc 1 4349 21 view .LVU2208 + 6802 00cc D369 ldr r3, [r2, #28] +4349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6803 .loc 1 4349 39 view .LVU2209 + 6804 00ce 2969 ldr r1, [r5, #16] +4349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6805 .loc 1 4349 29 view .LVU2210 + 6806 00d0 43EA0123 orr r3, r3, r1, lsl #8 + 6807 00d4 D361 str r3, [r2, #28] +4350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6808 .loc 1 4350 7 is_stmt 1 view .LVU2211 +4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6809 .loc 1 4272 21 is_stmt 0 view .LVU2212 + ARM GAS /tmp/ccGFzgX3.s page 286 + + + 6810 00d6 0020 movs r0, #0 +4350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6811 .loc 1 4350 7 view .LVU2213 + 6812 00d8 29E0 b .L399 + 6813 .LVL529: + 6814 .L402: +4356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6815 .loc 1 4356 7 is_stmt 1 view .LVU2214 +4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6816 .loc 1 4359 7 view .LVU2215 + 6817 00da 0068 ldr r0, [r0] + 6818 .LVL530: +4359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6819 .loc 1 4359 7 is_stmt 0 view .LVU2216 + 6820 00dc FFF7FEFF bl TIM_OC5_SetConfig + 6821 .LVL531: +4362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6822 .loc 1 4362 7 is_stmt 1 view .LVU2217 +4362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6823 .loc 1 4362 11 is_stmt 0 view .LVU2218 + 6824 00e0 2268 ldr r2, [r4] +4362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6825 .loc 1 4362 21 view .LVU2219 + 6826 00e2 536D ldr r3, [r2, #84] +4362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6827 .loc 1 4362 29 view .LVU2220 + 6828 00e4 43F00803 orr r3, r3, #8 + 6829 00e8 5365 str r3, [r2, #84] +4365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR3 |= sConfig->OCFastMode; + 6830 .loc 1 4365 7 is_stmt 1 view .LVU2221 +4365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR3 |= sConfig->OCFastMode; + 6831 .loc 1 4365 11 is_stmt 0 view .LVU2222 + 6832 00ea 2268 ldr r2, [r4] +4365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR3 |= sConfig->OCFastMode; + 6833 .loc 1 4365 21 view .LVU2223 + 6834 00ec 536D ldr r3, [r2, #84] +4365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR3 |= sConfig->OCFastMode; + 6835 .loc 1 4365 29 view .LVU2224 + 6836 00ee 23F00403 bic r3, r3, #4 + 6837 00f2 5365 str r3, [r2, #84] +4366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6838 .loc 1 4366 7 is_stmt 1 view .LVU2225 +4366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6839 .loc 1 4366 11 is_stmt 0 view .LVU2226 + 6840 00f4 2268 ldr r2, [r4] +4366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6841 .loc 1 4366 21 view .LVU2227 + 6842 00f6 536D ldr r3, [r2, #84] +4366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6843 .loc 1 4366 39 view .LVU2228 + 6844 00f8 2969 ldr r1, [r5, #16] +4366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6845 .loc 1 4366 29 view .LVU2229 + 6846 00fa 0B43 orrs r3, r3, r1 + 6847 00fc 5365 str r3, [r2, #84] +4367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6848 .loc 1 4367 7 is_stmt 1 view .LVU2230 + ARM GAS /tmp/ccGFzgX3.s page 287 + + +4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6849 .loc 1 4272 21 is_stmt 0 view .LVU2231 + 6850 00fe 0020 movs r0, #0 +4367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6851 .loc 1 4367 7 view .LVU2232 + 6852 0100 15E0 b .L399 + 6853 .LVL532: + 6854 .L400: +4373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6855 .loc 1 4373 7 is_stmt 1 view .LVU2233 +4376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6856 .loc 1 4376 7 view .LVU2234 + 6857 0102 0068 ldr r0, [r0] + 6858 .LVL533: +4376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6859 .loc 1 4376 7 is_stmt 0 view .LVU2235 + 6860 0104 FFF7FEFF bl TIM_OC6_SetConfig + 6861 .LVL534: +4379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6862 .loc 1 4379 7 is_stmt 1 view .LVU2236 +4379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6863 .loc 1 4379 11 is_stmt 0 view .LVU2237 + 6864 0108 2268 ldr r2, [r4] +4379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6865 .loc 1 4379 21 view .LVU2238 + 6866 010a 536D ldr r3, [r2, #84] +4379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6867 .loc 1 4379 29 view .LVU2239 + 6868 010c 43F40063 orr r3, r3, #2048 + 6869 0110 5365 str r3, [r2, #84] +4382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + 6870 .loc 1 4382 7 is_stmt 1 view .LVU2240 +4382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + 6871 .loc 1 4382 11 is_stmt 0 view .LVU2241 + 6872 0112 2268 ldr r2, [r4] +4382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + 6873 .loc 1 4382 21 view .LVU2242 + 6874 0114 536D ldr r3, [r2, #84] +4382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + 6875 .loc 1 4382 29 view .LVU2243 + 6876 0116 23F48063 bic r3, r3, #1024 + 6877 011a 5365 str r3, [r2, #84] +4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6878 .loc 1 4383 7 is_stmt 1 view .LVU2244 +4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6879 .loc 1 4383 11 is_stmt 0 view .LVU2245 + 6880 011c 2268 ldr r2, [r4] +4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6881 .loc 1 4383 21 view .LVU2246 + 6882 011e 536D ldr r3, [r2, #84] +4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6883 .loc 1 4383 39 view .LVU2247 + 6884 0120 2969 ldr r1, [r5, #16] +4383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 6885 .loc 1 4383 29 view .LVU2248 + 6886 0122 43EA0123 orr r3, r3, r1, lsl #8 + 6887 0126 5365 str r3, [r2, #84] + ARM GAS /tmp/ccGFzgX3.s page 288 + + +4384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6888 .loc 1 4384 7 is_stmt 1 view .LVU2249 +4272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6889 .loc 1 4272 21 is_stmt 0 view .LVU2250 + 6890 0128 0020 movs r0, #0 +4384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6891 .loc 1 4384 7 view .LVU2251 + 6892 012a 00E0 b .L399 + 6893 .LVL535: + 6894 .L408: +4283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 6895 .loc 1 4283 3 view .LVU2252 + 6896 012c 0120 movs r0, #1 + 6897 .LVL536: + 6898 .L399: +4392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6899 .loc 1 4392 3 is_stmt 1 view .LVU2253 +4392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6900 .loc 1 4392 3 view .LVU2254 + 6901 012e 0023 movs r3, #0 + 6902 0130 84F83C30 strb r3, [r4, #60] +4392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6903 .loc 1 4392 3 view .LVU2255 +4394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6904 .loc 1 4394 3 view .LVU2256 + 6905 .LVL537: + 6906 .L398: +4395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6907 .loc 1 4395 1 is_stmt 0 view .LVU2257 + 6908 0134 38BD pop {r3, r4, r5, pc} + 6909 .LVL538: + 6910 .L407: +4281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6911 .loc 1 4281 3 discriminator 1 view .LVU2258 + 6912 0136 0220 movs r0, #2 + 6913 .LVL539: +4281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6914 .loc 1 4281 3 discriminator 1 view .LVU2259 + 6915 0138 FCE7 b .L398 + 6916 .cfi_endproc + 6917 .LFE202: + 6919 .section .text.TIM_TI1_SetConfig,"ax",%progbits + 6920 .align 1 + 6921 .global TIM_TI1_SetConfig + 6922 .syntax unified + 6923 .thumb + 6924 .thumb_func + 6926 TIM_TI1_SetConfig: + 6927 .LVL540: + 6928 .LFB253: +7518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmr1; + 6929 .loc 1 7518 1 is_stmt 1 view -0 + 6930 .cfi_startproc + 6931 @ args = 0, pretend = 0, frame = 0 + 6932 @ frame_needed = 0, uses_anonymous_args = 0 + 6933 @ link register save eliminated. +7518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmr1; + ARM GAS /tmp/ccGFzgX3.s page 289 + + + 6934 .loc 1 7518 1 is_stmt 0 view .LVU2261 + 6935 0000 70B4 push {r4, r5, r6} + 6936 .LCFI66: + 6937 .cfi_def_cfa_offset 12 + 6938 .cfi_offset 4, -12 + 6939 .cfi_offset 5, -8 + 6940 .cfi_offset 6, -4 + 6941 0002 9446 mov ip, r2 +7519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccer; + 6942 .loc 1 7519 3 is_stmt 1 view .LVU2262 +7520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6943 .loc 1 7520 3 view .LVU2263 +7523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC1E; + 6944 .loc 1 7523 3 view .LVU2264 +7523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC1E; + 6945 .loc 1 7523 11 is_stmt 0 view .LVU2265 + 6946 0004 066A ldr r6, [r0, #32] + 6947 .LVL541: +7524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; + 6948 .loc 1 7524 3 is_stmt 1 view .LVU2266 +7524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; + 6949 .loc 1 7524 7 is_stmt 0 view .LVU2267 + 6950 0006 046A ldr r4, [r0, #32] +7524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; + 6951 .loc 1 7524 14 view .LVU2268 + 6952 0008 24F00104 bic r4, r4, #1 + 6953 000c 0462 str r4, [r0, #32] +7525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6954 .loc 1 7525 3 is_stmt 1 view .LVU2269 +7525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 6955 .loc 1 7525 12 is_stmt 0 view .LVU2270 + 6956 000e 8469 ldr r4, [r0, #24] + 6957 .LVL542: +7528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 6958 .loc 1 7528 3 is_stmt 1 view .LVU2271 +7528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 6959 .loc 1 7528 7 is_stmt 0 view .LVU2272 + 6960 0010 1D4D ldr r5, .L414 + 6961 0012 B0F1804F cmp r0, #1073741824 + 6962 0016 18BF it ne + 6963 0018 A842 cmpne r0, r5 + 6964 001a 23D0 beq .L411 +7528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 6965 .loc 1 7528 7 discriminator 2 view .LVU2273 + 6966 001c 1B4A ldr r2, .L414+4 + 6967 .LVL543: +7528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 6968 .loc 1 7528 7 discriminator 2 view .LVU2274 + 6969 001e 9042 cmp r0, r2 + 6970 0020 14BF ite ne + 6971 0022 0022 movne r2, #0 + 6972 0024 0122 moveq r2, #1 + 6973 0026 A5F57C45 sub r5, r5, #64512 + 6974 002a A842 cmp r0, r5 + 6975 002c 1AD0 beq .L411 + 6976 002e CAB9 cbnz r2, .L411 +7528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 290 + + + 6977 .loc 1 7528 7 discriminator 4 view .LVU2275 + 6978 0030 02F18042 add r2, r2, #1073741824 + 6979 0034 02F58232 add r2, r2, #66560 + 6980 0038 9042 cmp r0, r2 + 6981 003a 14BF ite ne + 6982 003c 0022 movne r2, #0 + 6983 003e 0122 moveq r2, #1 + 6984 0040 05F50065 add r5, r5, #2048 + 6985 0044 A842 cmp r0, r5 + 6986 0046 0DD0 beq .L411 + 6987 0048 62B9 cbnz r2, .L411 +7528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 6988 .loc 1 7528 7 discriminator 6 view .LVU2276 + 6989 004a 114A ldr r2, .L414+8 + 6990 004c 9042 cmp r0, r2 + 6991 004e 14BF ite ne + 6992 0050 0022 movne r2, #0 + 6993 0052 0122 moveq r2, #1 + 6994 0054 05F59A35 add r5, r5, #78848 + 6995 0058 A842 cmp r0, r5 + 6996 005a 03D0 beq .L411 + 6997 005c 12B9 cbnz r2, .L411 +7535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6998 .loc 1 7535 5 is_stmt 1 view .LVU2277 +7535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 6999 .loc 1 7535 14 is_stmt 0 view .LVU2278 + 7000 005e 44F00102 orr r2, r4, #1 + 7001 .LVL544: +7535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7002 .loc 1 7535 14 view .LVU2279 + 7003 0062 03E0 b .L412 + 7004 .LVL545: + 7005 .L411: +7530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= TIM_ICSelection; + 7006 .loc 1 7530 5 is_stmt 1 view .LVU2280 +7530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= TIM_ICSelection; + 7007 .loc 1 7530 14 is_stmt 0 view .LVU2281 + 7008 0064 24F00302 bic r2, r4, #3 + 7009 .LVL546: +7531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7010 .loc 1 7531 5 is_stmt 1 view .LVU2282 +7531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7011 .loc 1 7531 14 is_stmt 0 view .LVU2283 + 7012 0068 42EA0C02 orr r2, r2, ip + 7013 .LVL547: + 7014 .L412: +7539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + 7015 .loc 1 7539 3 is_stmt 1 view .LVU2284 +7539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + 7016 .loc 1 7539 12 is_stmt 0 view .LVU2285 + 7017 006c 22F0F002 bic r2, r2, #240 + 7018 .LVL548: +7540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7019 .loc 1 7540 3 is_stmt 1 view .LVU2286 +7540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7020 .loc 1 7540 30 is_stmt 0 view .LVU2287 + 7021 0070 1B01 lsls r3, r3, #4 + ARM GAS /tmp/ccGFzgX3.s page 291 + + + 7022 .LVL549: +7540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7023 .loc 1 7540 37 view .LVU2288 + 7024 0072 DBB2 uxtb r3, r3 +7540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7025 .loc 1 7540 12 view .LVU2289 + 7026 0074 1343 orrs r3, r3, r2 + 7027 .LVL550: +7543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + 7028 .loc 1 7543 3 is_stmt 1 view .LVU2290 +7543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + 7029 .loc 1 7543 11 is_stmt 0 view .LVU2291 + 7030 0076 26F00A02 bic r2, r6, #10 + 7031 .LVL551: +7544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7032 .loc 1 7544 3 is_stmt 1 view .LVU2292 +7544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7033 .loc 1 7544 30 is_stmt 0 view .LVU2293 + 7034 007a 01F00A01 and r1, r1, #10 + 7035 .LVL552: +7544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7036 .loc 1 7544 11 view .LVU2294 + 7037 007e 1143 orrs r1, r1, r2 + 7038 .LVL553: +7547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER = tmpccer; + 7039 .loc 1 7547 3 is_stmt 1 view .LVU2295 +7547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER = tmpccer; + 7040 .loc 1 7547 15 is_stmt 0 view .LVU2296 + 7041 0080 8361 str r3, [r0, #24] +7548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7042 .loc 1 7548 3 is_stmt 1 view .LVU2297 +7548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7043 .loc 1 7548 14 is_stmt 0 view .LVU2298 + 7044 0082 0162 str r1, [r0, #32] +7549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7045 .loc 1 7549 1 view .LVU2299 + 7046 0084 70BC pop {r4, r5, r6} + 7047 .LCFI67: + 7048 .cfi_restore 6 + 7049 .cfi_restore 5 + 7050 .cfi_restore 4 + 7051 .cfi_def_cfa_offset 0 + 7052 0086 7047 bx lr + 7053 .L415: + 7054 .align 2 + 7055 .L414: + 7056 0088 00000140 .word 1073807360 + 7057 008c 00080040 .word 1073743872 + 7058 0090 00180040 .word 1073747968 + 7059 .cfi_endproc + 7060 .LFE253: + 7062 .section .text.HAL_TIM_IC_ConfigChannel,"ax",%progbits + 7063 .align 1 + 7064 .global HAL_TIM_IC_ConfigChannel + 7065 .syntax unified + 7066 .thumb + 7067 .thumb_func + ARM GAS /tmp/ccGFzgX3.s page 292 + + + 7069 HAL_TIM_IC_ConfigChannel: + 7070 .LVL554: + 7071 .LFB201: +4168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 7072 .loc 1 4168 1 is_stmt 1 view -0 + 7073 .cfi_startproc + 7074 @ args = 0, pretend = 0, frame = 0 + 7075 @ frame_needed = 0, uses_anonymous_args = 0 +4168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 7076 .loc 1 4168 1 is_stmt 0 view .LVU2301 + 7077 0000 38B5 push {r3, r4, r5, lr} + 7078 .LCFI68: + 7079 .cfi_def_cfa_offset 16 + 7080 .cfi_offset 3, -16 + 7081 .cfi_offset 4, -12 + 7082 .cfi_offset 5, -8 + 7083 .cfi_offset 14, -4 +4169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7084 .loc 1 4169 3 is_stmt 1 view .LVU2302 + 7085 .LVL555: +4172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + 7086 .loc 1 4172 3 view .LVU2303 +4173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + 7087 .loc 1 4173 3 view .LVU2304 +4174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + 7088 .loc 1 4174 3 view .LVU2305 +4175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + 7089 .loc 1 4175 3 view .LVU2306 +4176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7090 .loc 1 4176 3 view .LVU2307 +4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7091 .loc 1 4179 3 view .LVU2308 +4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7092 .loc 1 4179 3 view .LVU2309 + 7093 0002 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 7094 0006 012B cmp r3, #1 + 7095 0008 5ED0 beq .L424 + 7096 000a 0446 mov r4, r0 + 7097 000c 0D46 mov r5, r1 +4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7098 .loc 1 4179 3 discriminator 2 view .LVU2310 + 7099 000e 0123 movs r3, #1 + 7100 0010 80F83C30 strb r3, [r0, #60] +4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7101 .loc 1 4179 3 discriminator 2 view .LVU2311 +4181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7102 .loc 1 4181 3 view .LVU2312 + 7103 0014 0C2A cmp r2, #12 + 7104 0016 52D8 bhi .L425 + 7105 0018 DFE802F0 tbb [pc, r2] + 7106 .L420: + 7107 001c 07 .byte (.L423-.L420)/2 + 7108 001d 51 .byte (.L425-.L420)/2 + 7109 001e 51 .byte (.L425-.L420)/2 + 7110 001f 51 .byte (.L425-.L420)/2 + 7111 0020 19 .byte (.L422-.L420)/2 + 7112 0021 51 .byte (.L425-.L420)/2 + ARM GAS /tmp/ccGFzgX3.s page 293 + + + 7113 0022 51 .byte (.L425-.L420)/2 + 7114 0023 51 .byte (.L425-.L420)/2 + 7115 0024 2C .byte (.L421-.L420)/2 + 7116 0025 51 .byte (.L425-.L420)/2 + 7117 0026 51 .byte (.L425-.L420)/2 + 7118 0027 51 .byte (.L425-.L420)/2 + 7119 0028 3E .byte (.L419-.L420)/2 + 7120 0029 00 .p2align 1 + 7121 .L423: +4184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, + 7122 .loc 1 4184 5 view .LVU2313 + 7123 002a CB68 ldr r3, [r1, #12] + 7124 002c 4A68 ldr r2, [r1, #4] + 7125 .LVL556: +4184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, + 7126 .loc 1 4184 5 is_stmt 0 view .LVU2314 + 7127 002e 0968 ldr r1, [r1] + 7128 .LVL557: +4184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, + 7129 .loc 1 4184 5 view .LVU2315 + 7130 0030 0068 ldr r0, [r0] + 7131 .LVL558: +4184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, + 7132 .loc 1 4184 5 view .LVU2316 + 7133 0032 FFF7FEFF bl TIM_TI1_SetConfig + 7134 .LVL559: +4190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7135 .loc 1 4190 5 is_stmt 1 view .LVU2317 +4190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7136 .loc 1 4190 9 is_stmt 0 view .LVU2318 + 7137 0036 2268 ldr r2, [r4] +4190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7138 .loc 1 4190 19 view .LVU2319 + 7139 0038 9369 ldr r3, [r2, #24] +4190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7140 .loc 1 4190 27 view .LVU2320 + 7141 003a 23F00C03 bic r3, r3, #12 + 7142 003e 9361 str r3, [r2, #24] +4193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7143 .loc 1 4193 5 is_stmt 1 view .LVU2321 +4193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7144 .loc 1 4193 9 is_stmt 0 view .LVU2322 + 7145 0040 2268 ldr r2, [r4] +4193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7146 .loc 1 4193 19 view .LVU2323 + 7147 0042 9369 ldr r3, [r2, #24] +4193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7148 .loc 1 4193 37 view .LVU2324 + 7149 0044 A968 ldr r1, [r5, #8] +4193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7150 .loc 1 4193 27 view .LVU2325 + 7151 0046 0B43 orrs r3, r3, r1 + 7152 0048 9361 str r3, [r2, #24] +4169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7153 .loc 1 4169 21 view .LVU2326 + 7154 004a 0020 movs r0, #0 + 7155 004c 38E0 b .L418 + ARM GAS /tmp/ccGFzgX3.s page 294 + + + 7156 .LVL560: + 7157 .L422: +4198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7158 .loc 1 4198 5 is_stmt 1 view .LVU2327 +4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, + 7159 .loc 1 4200 5 view .LVU2328 + 7160 004e CB68 ldr r3, [r1, #12] + 7161 0050 4A68 ldr r2, [r1, #4] + 7162 .LVL561: +4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, + 7163 .loc 1 4200 5 is_stmt 0 view .LVU2329 + 7164 0052 0968 ldr r1, [r1] + 7165 .LVL562: +4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, + 7166 .loc 1 4200 5 view .LVU2330 + 7167 0054 0068 ldr r0, [r0] + 7168 .LVL563: +4200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, + 7169 .loc 1 4200 5 view .LVU2331 + 7170 0056 FFF7FEFF bl TIM_TI2_SetConfig + 7171 .LVL564: +4206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7172 .loc 1 4206 5 is_stmt 1 view .LVU2332 +4206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7173 .loc 1 4206 9 is_stmt 0 view .LVU2333 + 7174 005a 2268 ldr r2, [r4] +4206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7175 .loc 1 4206 19 view .LVU2334 + 7176 005c 9369 ldr r3, [r2, #24] +4206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7177 .loc 1 4206 27 view .LVU2335 + 7178 005e 23F44063 bic r3, r3, #3072 + 7179 0062 9361 str r3, [r2, #24] +4209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7180 .loc 1 4209 5 is_stmt 1 view .LVU2336 +4209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7181 .loc 1 4209 9 is_stmt 0 view .LVU2337 + 7182 0064 2268 ldr r2, [r4] +4209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7183 .loc 1 4209 19 view .LVU2338 + 7184 0066 9369 ldr r3, [r2, #24] +4209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7185 .loc 1 4209 38 view .LVU2339 + 7186 0068 A968 ldr r1, [r5, #8] +4209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7187 .loc 1 4209 27 view .LVU2340 + 7188 006a 43EA0123 orr r3, r3, r1, lsl #8 + 7189 006e 9361 str r3, [r2, #24] +4169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7190 .loc 1 4169 21 view .LVU2341 + 7191 0070 0020 movs r0, #0 + 7192 0072 25E0 b .L418 + 7193 .LVL565: + 7194 .L421: +4214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7195 .loc 1 4214 5 is_stmt 1 view .LVU2342 +4216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, + ARM GAS /tmp/ccGFzgX3.s page 295 + + + 7196 .loc 1 4216 5 view .LVU2343 + 7197 0074 CB68 ldr r3, [r1, #12] + 7198 0076 4A68 ldr r2, [r1, #4] + 7199 .LVL566: +4216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, + 7200 .loc 1 4216 5 is_stmt 0 view .LVU2344 + 7201 0078 0968 ldr r1, [r1] + 7202 .LVL567: +4216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, + 7203 .loc 1 4216 5 view .LVU2345 + 7204 007a 0068 ldr r0, [r0] + 7205 .LVL568: +4216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, + 7206 .loc 1 4216 5 view .LVU2346 + 7207 007c FFF7FEFF bl TIM_TI3_SetConfig + 7208 .LVL569: +4222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7209 .loc 1 4222 5 is_stmt 1 view .LVU2347 +4222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7210 .loc 1 4222 9 is_stmt 0 view .LVU2348 + 7211 0080 2268 ldr r2, [r4] +4222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7212 .loc 1 4222 19 view .LVU2349 + 7213 0082 D369 ldr r3, [r2, #28] +4222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7214 .loc 1 4222 27 view .LVU2350 + 7215 0084 23F00C03 bic r3, r3, #12 + 7216 0088 D361 str r3, [r2, #28] +4225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7217 .loc 1 4225 5 is_stmt 1 view .LVU2351 +4225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7218 .loc 1 4225 9 is_stmt 0 view .LVU2352 + 7219 008a 2268 ldr r2, [r4] +4225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7220 .loc 1 4225 19 view .LVU2353 + 7221 008c D369 ldr r3, [r2, #28] +4225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7222 .loc 1 4225 37 view .LVU2354 + 7223 008e A968 ldr r1, [r5, #8] +4225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7224 .loc 1 4225 27 view .LVU2355 + 7225 0090 0B43 orrs r3, r3, r1 + 7226 0092 D361 str r3, [r2, #28] +4169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7227 .loc 1 4169 21 view .LVU2356 + 7228 0094 0020 movs r0, #0 + 7229 0096 13E0 b .L418 + 7230 .LVL570: + 7231 .L419: +4230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7232 .loc 1 4230 5 is_stmt 1 view .LVU2357 +4232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, + 7233 .loc 1 4232 5 view .LVU2358 + 7234 0098 CB68 ldr r3, [r1, #12] + 7235 009a 4A68 ldr r2, [r1, #4] + 7236 .LVL571: +4232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, + ARM GAS /tmp/ccGFzgX3.s page 296 + + + 7237 .loc 1 4232 5 is_stmt 0 view .LVU2359 + 7238 009c 0968 ldr r1, [r1] + 7239 .LVL572: +4232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, + 7240 .loc 1 4232 5 view .LVU2360 + 7241 009e 0068 ldr r0, [r0] + 7242 .LVL573: +4232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICPolarity, + 7243 .loc 1 4232 5 view .LVU2361 + 7244 00a0 FFF7FEFF bl TIM_TI4_SetConfig + 7245 .LVL574: +4238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7246 .loc 1 4238 5 is_stmt 1 view .LVU2362 +4238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7247 .loc 1 4238 9 is_stmt 0 view .LVU2363 + 7248 00a4 2268 ldr r2, [r4] +4238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7249 .loc 1 4238 19 view .LVU2364 + 7250 00a6 D369 ldr r3, [r2, #28] +4238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7251 .loc 1 4238 27 view .LVU2365 + 7252 00a8 23F44063 bic r3, r3, #3072 + 7253 00ac D361 str r3, [r2, #28] +4241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7254 .loc 1 4241 5 is_stmt 1 view .LVU2366 +4241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7255 .loc 1 4241 9 is_stmt 0 view .LVU2367 + 7256 00ae 2268 ldr r2, [r4] +4241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7257 .loc 1 4241 19 view .LVU2368 + 7258 00b0 D369 ldr r3, [r2, #28] +4241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7259 .loc 1 4241 38 view .LVU2369 + 7260 00b2 A968 ldr r1, [r5, #8] +4241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7261 .loc 1 4241 27 view .LVU2370 + 7262 00b4 43EA0123 orr r3, r3, r1, lsl #8 + 7263 00b8 D361 str r3, [r2, #28] +4169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7264 .loc 1 4169 21 view .LVU2371 + 7265 00ba 0020 movs r0, #0 + 7266 00bc 00E0 b .L418 + 7267 .LVL575: + 7268 .L425: +4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7269 .loc 1 4179 3 discriminator 2 view .LVU2372 + 7270 00be 0120 movs r0, #1 + 7271 .LVL576: + 7272 .L418: +4248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7273 .loc 1 4248 3 is_stmt 1 view .LVU2373 +4248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7274 .loc 1 4248 3 view .LVU2374 + 7275 00c0 0023 movs r3, #0 + 7276 00c2 84F83C30 strb r3, [r4, #60] +4248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7277 .loc 1 4248 3 view .LVU2375 + ARM GAS /tmp/ccGFzgX3.s page 297 + + +4250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7278 .loc 1 4250 3 view .LVU2376 + 7279 .LVL577: + 7280 .L417: +4251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7281 .loc 1 4251 1 is_stmt 0 view .LVU2377 + 7282 00c6 38BD pop {r3, r4, r5, pc} + 7283 .LVL578: + 7284 .L424: +4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7285 .loc 1 4179 3 discriminator 1 view .LVU2378 + 7286 00c8 0220 movs r0, #2 + 7287 .LVL579: +4179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7288 .loc 1 4179 3 discriminator 1 view .LVU2379 + 7289 00ca FCE7 b .L417 + 7290 .cfi_endproc + 7291 .LFE201: + 7293 .section .text.HAL_TIM_OnePulse_ConfigChannel,"ax",%progbits + 7294 .align 1 + 7295 .global HAL_TIM_OnePulse_ConfigChannel + 7296 .syntax unified + 7297 .thumb + 7298 .thumb_func + 7300 HAL_TIM_OnePulse_ConfigChannel: + 7301 .LVL580: + 7302 .LFB203: +4418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 7303 .loc 1 4418 1 is_stmt 1 view -0 + 7304 .cfi_startproc + 7305 @ args = 0, pretend = 0, frame = 32 + 7306 @ frame_needed = 0, uses_anonymous_args = 0 +4419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_OC_InitTypeDef temp1; + 7307 .loc 1 4419 3 view .LVU2381 +4420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7308 .loc 1 4420 3 view .LVU2382 +4423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + 7309 .loc 1 4423 3 view .LVU2383 +4424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7310 .loc 1 4424 3 view .LVU2384 +4426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7311 .loc 1 4426 3 view .LVU2385 +4426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7312 .loc 1 4426 6 is_stmt 0 view .LVU2386 + 7313 0000 9A42 cmp r2, r3 + 7314 0002 76D0 beq .L435 +4418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 7315 .loc 1 4418 1 view .LVU2387 + 7316 0004 70B5 push {r4, r5, r6, lr} + 7317 .LCFI69: + 7318 .cfi_def_cfa_offset 16 + 7319 .cfi_offset 4, -16 + 7320 .cfi_offset 5, -12 + 7321 .cfi_offset 6, -8 + 7322 .cfi_offset 14, -4 + 7323 0006 88B0 sub sp, sp, #32 + 7324 .LCFI70: + ARM GAS /tmp/ccGFzgX3.s page 298 + + + 7325 .cfi_def_cfa_offset 48 + 7326 0008 0446 mov r4, r0 + 7327 000a 0D46 mov r5, r1 + 7328 000c 1E46 mov r6, r3 +4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7329 .loc 1 4429 5 is_stmt 1 view .LVU2388 +4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7330 .loc 1 4429 5 view .LVU2389 + 7331 000e 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 7332 .LVL581: +4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7333 .loc 1 4429 5 is_stmt 0 view .LVU2390 + 7334 0012 012B cmp r3, #1 + 7335 0014 6FD0 beq .L436 +4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7336 .loc 1 4429 5 is_stmt 1 discriminator 2 view .LVU2391 + 7337 0016 0123 movs r3, #1 + 7338 0018 80F83C30 strb r3, [r0, #60] +4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7339 .loc 1 4429 5 discriminator 2 view .LVU2392 +4431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7340 .loc 1 4431 5 view .LVU2393 +4431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7341 .loc 1 4431 17 is_stmt 0 view .LVU2394 + 7342 001c 0223 movs r3, #2 + 7343 001e 80F83D30 strb r3, [r0, #61] +4434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.Pulse = sConfig->Pulse; + 7344 .loc 1 4434 5 is_stmt 1 view .LVU2395 +4434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.Pulse = sConfig->Pulse; + 7345 .loc 1 4434 27 is_stmt 0 view .LVU2396 + 7346 0022 0B68 ldr r3, [r1] +4434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.Pulse = sConfig->Pulse; + 7347 .loc 1 4434 18 view .LVU2397 + 7348 0024 0193 str r3, [sp, #4] +4435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.OCPolarity = sConfig->OCPolarity; + 7349 .loc 1 4435 5 is_stmt 1 view .LVU2398 +4435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.OCPolarity = sConfig->OCPolarity; + 7350 .loc 1 4435 26 is_stmt 0 view .LVU2399 + 7351 0026 4B68 ldr r3, [r1, #4] +4435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.OCPolarity = sConfig->OCPolarity; + 7352 .loc 1 4435 17 view .LVU2400 + 7353 0028 0293 str r3, [sp, #8] +4436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.OCNPolarity = sConfig->OCNPolarity; + 7354 .loc 1 4436 5 is_stmt 1 view .LVU2401 +4436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.OCNPolarity = sConfig->OCNPolarity; + 7355 .loc 1 4436 31 is_stmt 0 view .LVU2402 + 7356 002a 8B68 ldr r3, [r1, #8] +4436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.OCNPolarity = sConfig->OCNPolarity; + 7357 .loc 1 4436 22 view .LVU2403 + 7358 002c 0393 str r3, [sp, #12] +4437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.OCIdleState = sConfig->OCIdleState; + 7359 .loc 1 4437 5 is_stmt 1 view .LVU2404 +4437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.OCIdleState = sConfig->OCIdleState; + 7360 .loc 1 4437 32 is_stmt 0 view .LVU2405 + 7361 002e CB68 ldr r3, [r1, #12] +4437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.OCIdleState = sConfig->OCIdleState; + 7362 .loc 1 4437 23 view .LVU2406 + ARM GAS /tmp/ccGFzgX3.s page 299 + + + 7363 0030 0493 str r3, [sp, #16] +4438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.OCNIdleState = sConfig->OCNIdleState; + 7364 .loc 1 4438 5 is_stmt 1 view .LVU2407 +4438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.OCNIdleState = sConfig->OCNIdleState; + 7365 .loc 1 4438 32 is_stmt 0 view .LVU2408 + 7366 0032 0B69 ldr r3, [r1, #16] +4438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** temp1.OCNIdleState = sConfig->OCNIdleState; + 7367 .loc 1 4438 23 view .LVU2409 + 7368 0034 0693 str r3, [sp, #24] +4439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7369 .loc 1 4439 5 is_stmt 1 view .LVU2410 +4439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7370 .loc 1 4439 33 is_stmt 0 view .LVU2411 + 7371 0036 4B69 ldr r3, [r1, #20] +4439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7372 .loc 1 4439 24 view .LVU2412 + 7373 0038 0793 str r3, [sp, #28] +4441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7374 .loc 1 4441 5 is_stmt 1 view .LVU2413 + 7375 003a 52B1 cbz r2, .L429 + 7376 003c 042A cmp r2, #4 + 7377 003e 11D0 beq .L430 + 7378 0040 0120 movs r0, #1 + 7379 .LVL582: + 7380 .L431: +4514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7381 .loc 1 4514 5 view .LVU2414 +4514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7382 .loc 1 4514 17 is_stmt 0 view .LVU2415 + 7383 0042 0123 movs r3, #1 + 7384 0044 84F83D30 strb r3, [r4, #61] +4516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7385 .loc 1 4516 5 is_stmt 1 view .LVU2416 +4516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7386 .loc 1 4516 5 view .LVU2417 + 7387 0048 0023 movs r3, #0 + 7388 004a 84F83C30 strb r3, [r4, #60] +4516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7389 .loc 1 4516 5 view .LVU2418 +4518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7390 .loc 1 4518 5 view .LVU2419 + 7391 .LVL583: + 7392 .L428: +4524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7393 .loc 1 4524 1 is_stmt 0 view .LVU2420 + 7394 004e 08B0 add sp, sp, #32 + 7395 .LCFI71: + 7396 .cfi_remember_state + 7397 .cfi_def_cfa_offset 16 + 7398 @ sp needed + 7399 0050 70BD pop {r4, r5, r6, pc} + 7400 .LVL584: + 7401 .L429: + 7402 .LCFI72: + 7403 .cfi_restore_state +4445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7404 .loc 1 4445 9 is_stmt 1 view .LVU2421 + ARM GAS /tmp/ccGFzgX3.s page 300 + + +4447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 7405 .loc 1 4447 9 view .LVU2422 + 7406 0052 01A9 add r1, sp, #4 + 7407 .LVL585: +4447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 7408 .loc 1 4447 9 is_stmt 0 view .LVU2423 + 7409 0054 0068 ldr r0, [r0] + 7410 .LVL586: +4447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 7411 .loc 1 4447 9 view .LVU2424 + 7412 0056 FFF7FEFF bl TIM_OC1_SetConfig + 7413 .LVL587: +4448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7414 .loc 1 4448 9 is_stmt 1 view .LVU2425 +4464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7415 .loc 1 4464 5 view .LVU2426 + 7416 .L432: +4466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7417 .loc 1 4466 7 view .LVU2427 + 7418 005a 46B1 cbz r6, .L433 + 7419 005c 042E cmp r6, #4 + 7420 005e 27D0 beq .L434 + 7421 0060 0120 movs r0, #1 + 7422 0062 EEE7 b .L431 + 7423 .LVL588: + 7424 .L430: +4453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7425 .loc 1 4453 9 view .LVU2428 +4455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 7426 .loc 1 4455 9 view .LVU2429 + 7427 0064 01A9 add r1, sp, #4 + 7428 .LVL589: +4455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 7429 .loc 1 4455 9 is_stmt 0 view .LVU2430 + 7430 0066 0068 ldr r0, [r0] + 7431 .LVL590: +4455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 7432 .loc 1 4455 9 view .LVU2431 + 7433 0068 FFF7FEFF bl TIM_OC2_SetConfig + 7434 .LVL591: +4456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7435 .loc 1 4456 9 is_stmt 1 view .LVU2432 +4464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7436 .loc 1 4464 5 view .LVU2433 + 7437 006c F5E7 b .L432 + 7438 .L433: +4470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7439 .loc 1 4470 11 view .LVU2434 +4472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICSelection, sConfig->ICFilter); + 7440 .loc 1 4472 11 view .LVU2435 + 7441 006e 2B6A ldr r3, [r5, #32] + 7442 0070 EA69 ldr r2, [r5, #28] + 7443 0072 A969 ldr r1, [r5, #24] + 7444 0074 2068 ldr r0, [r4] + 7445 0076 FFF7FEFF bl TIM_TI1_SetConfig + 7446 .LVL592: +4476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 301 + + + 7447 .loc 1 4476 11 view .LVU2436 +4476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7448 .loc 1 4476 15 is_stmt 0 view .LVU2437 + 7449 007a 2268 ldr r2, [r4] +4476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7450 .loc 1 4476 25 view .LVU2438 + 7451 007c 9369 ldr r3, [r2, #24] +4476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7452 .loc 1 4476 33 view .LVU2439 + 7453 007e 23F00C03 bic r3, r3, #12 + 7454 0082 9361 str r3, [r2, #24] +4479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_TS_TI1FP1; + 7455 .loc 1 4479 11 is_stmt 1 view .LVU2440 +4479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_TS_TI1FP1; + 7456 .loc 1 4479 15 is_stmt 0 view .LVU2441 + 7457 0084 2268 ldr r2, [r4] +4479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_TS_TI1FP1; + 7458 .loc 1 4479 25 view .LVU2442 + 7459 0086 9368 ldr r3, [r2, #8] +4479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_TS_TI1FP1; + 7460 .loc 1 4479 32 view .LVU2443 + 7461 0088 23F07003 bic r3, r3, #112 + 7462 008c 9360 str r3, [r2, #8] +4480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7463 .loc 1 4480 11 is_stmt 1 view .LVU2444 +4480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7464 .loc 1 4480 15 is_stmt 0 view .LVU2445 + 7465 008e 2268 ldr r2, [r4] +4480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7466 .loc 1 4480 25 view .LVU2446 + 7467 0090 9368 ldr r3, [r2, #8] +4480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7468 .loc 1 4480 32 view .LVU2447 + 7469 0092 43F05003 orr r3, r3, #80 + 7470 0096 9360 str r3, [r2, #8] +4483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + 7471 .loc 1 4483 11 is_stmt 1 view .LVU2448 +4483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + 7472 .loc 1 4483 15 is_stmt 0 view .LVU2449 + 7473 0098 2268 ldr r2, [r4] +4483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + 7474 .loc 1 4483 25 view .LVU2450 + 7475 009a 9168 ldr r1, [r2, #8] +4483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + 7476 .loc 1 4483 32 view .LVU2451 + 7477 009c 174B ldr r3, .L441 + 7478 009e 0B40 ands r3, r3, r1 + 7479 00a0 9360 str r3, [r2, #8] +4484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 7480 .loc 1 4484 11 is_stmt 1 view .LVU2452 +4484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 7481 .loc 1 4484 15 is_stmt 0 view .LVU2453 + 7482 00a2 2268 ldr r2, [r4] +4484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 7483 .loc 1 4484 25 view .LVU2454 + 7484 00a4 9368 ldr r3, [r2, #8] +4484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + ARM GAS /tmp/ccGFzgX3.s page 302 + + + 7485 .loc 1 4484 32 view .LVU2455 + 7486 00a6 43F00603 orr r3, r3, #6 + 7487 00aa 9360 str r3, [r2, #8] +4485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7488 .loc 1 4485 11 is_stmt 1 view .LVU2456 + 7489 00ac 0020 movs r0, #0 + 7490 00ae C8E7 b .L431 + 7491 .L434: +4490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7492 .loc 1 4490 11 view .LVU2457 +4492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sConfig->ICSelection, sConfig->ICFilter); + 7493 .loc 1 4492 11 view .LVU2458 + 7494 00b0 2B6A ldr r3, [r5, #32] + 7495 00b2 EA69 ldr r2, [r5, #28] + 7496 00b4 A969 ldr r1, [r5, #24] + 7497 00b6 2068 ldr r0, [r4] + 7498 00b8 FFF7FEFF bl TIM_TI2_SetConfig + 7499 .LVL593: +4496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7500 .loc 1 4496 11 view .LVU2459 +4496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7501 .loc 1 4496 15 is_stmt 0 view .LVU2460 + 7502 00bc 2268 ldr r2, [r4] +4496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7503 .loc 1 4496 25 view .LVU2461 + 7504 00be 9369 ldr r3, [r2, #24] +4496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7505 .loc 1 4496 33 view .LVU2462 + 7506 00c0 23F44063 bic r3, r3, #3072 + 7507 00c4 9361 str r3, [r2, #24] +4499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_TS_TI2FP2; + 7508 .loc 1 4499 11 is_stmt 1 view .LVU2463 +4499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_TS_TI2FP2; + 7509 .loc 1 4499 15 is_stmt 0 view .LVU2464 + 7510 00c6 2268 ldr r2, [r4] +4499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_TS_TI2FP2; + 7511 .loc 1 4499 25 view .LVU2465 + 7512 00c8 9368 ldr r3, [r2, #8] +4499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_TS_TI2FP2; + 7513 .loc 1 4499 32 view .LVU2466 + 7514 00ca 23F07003 bic r3, r3, #112 + 7515 00ce 9360 str r3, [r2, #8] +4500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7516 .loc 1 4500 11 is_stmt 1 view .LVU2467 +4500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7517 .loc 1 4500 15 is_stmt 0 view .LVU2468 + 7518 00d0 2268 ldr r2, [r4] +4500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7519 .loc 1 4500 25 view .LVU2469 + 7520 00d2 9368 ldr r3, [r2, #8] +4500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7521 .loc 1 4500 32 view .LVU2470 + 7522 00d4 43F06003 orr r3, r3, #96 + 7523 00d8 9360 str r3, [r2, #8] +4503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + 7524 .loc 1 4503 11 is_stmt 1 view .LVU2471 +4503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + ARM GAS /tmp/ccGFzgX3.s page 303 + + + 7525 .loc 1 4503 15 is_stmt 0 view .LVU2472 + 7526 00da 2268 ldr r2, [r4] +4503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + 7527 .loc 1 4503 25 view .LVU2473 + 7528 00dc 9168 ldr r1, [r2, #8] +4503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + 7529 .loc 1 4503 32 view .LVU2474 + 7530 00de 074B ldr r3, .L441 + 7531 00e0 0B40 ands r3, r3, r1 + 7532 00e2 9360 str r3, [r2, #8] +4504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 7533 .loc 1 4504 11 is_stmt 1 view .LVU2475 +4504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 7534 .loc 1 4504 15 is_stmt 0 view .LVU2476 + 7535 00e4 2268 ldr r2, [r4] +4504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 7536 .loc 1 4504 25 view .LVU2477 + 7537 00e6 9368 ldr r3, [r2, #8] +4504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 7538 .loc 1 4504 32 view .LVU2478 + 7539 00e8 43F00603 orr r3, r3, #6 + 7540 00ec 9360 str r3, [r2, #8] +4505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7541 .loc 1 4505 11 is_stmt 1 view .LVU2479 + 7542 00ee 0020 movs r0, #0 + 7543 00f0 A7E7 b .L431 + 7544 .LVL594: + 7545 .L435: + 7546 .LCFI73: + 7547 .cfi_def_cfa_offset 0 + 7548 .cfi_restore 4 + 7549 .cfi_restore 5 + 7550 .cfi_restore 6 + 7551 .cfi_restore 14 +4522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7552 .loc 1 4522 12 is_stmt 0 view .LVU2480 + 7553 00f2 0120 movs r0, #1 + 7554 .LVL595: +4524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7555 .loc 1 4524 1 view .LVU2481 + 7556 00f4 7047 bx lr + 7557 .LVL596: + 7558 .L436: + 7559 .LCFI74: + 7560 .cfi_def_cfa_offset 48 + 7561 .cfi_offset 4, -16 + 7562 .cfi_offset 5, -12 + 7563 .cfi_offset 6, -8 + 7564 .cfi_offset 14, -4 +4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7565 .loc 1 4429 5 discriminator 1 view .LVU2482 + 7566 00f6 0220 movs r0, #2 + 7567 .LVL597: +4429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7568 .loc 1 4429 5 discriminator 1 view .LVU2483 + 7569 00f8 A9E7 b .L428 + 7570 .L442: + ARM GAS /tmp/ccGFzgX3.s page 304 + + + 7571 00fa 00BF .align 2 + 7572 .L441: + 7573 00fc F8FFFEFF .word -65544 + 7574 .cfi_endproc + 7575 .LFE203: + 7577 .section .text.TIM_ETR_SetConfig,"ax",%progbits + 7578 .align 1 + 7579 .global TIM_ETR_SetConfig + 7580 .syntax unified + 7581 .thumb + 7582 .thumb_func + 7584 TIM_ETR_SetConfig: + 7585 .LVL598: + 7586 .LFB260: +7793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +7794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Configures the TIMx External Trigger (ETR). +7795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. +7797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +7798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. +7799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. +7800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. +7801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. +7802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIM_ExtTRGPolarity The external Trigger Polarity. +7803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +7804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. +7805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. +7806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param ExtTRGFilter External Trigger Filter. +7807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F +7808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +7809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +7810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, +7811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +7812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7587 .loc 1 7812 1 is_stmt 1 view -0 + 7588 .cfi_startproc + 7589 @ args = 0, pretend = 0, frame = 0 + 7590 @ frame_needed = 0, uses_anonymous_args = 0 + 7591 @ link register save eliminated. + 7592 .loc 1 7812 1 is_stmt 0 view .LVU2485 + 7593 0000 10B4 push {r4} + 7594 .LCFI75: + 7595 .cfi_def_cfa_offset 4 + 7596 .cfi_offset 4, -4 +7813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 7597 .loc 1 7813 3 is_stmt 1 view .LVU2486 +7814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr = TIMx->SMCR; + 7598 .loc 1 7815 3 view .LVU2487 + 7599 .loc 1 7815 11 is_stmt 0 view .LVU2488 + 7600 0002 8468 ldr r4, [r0, #8] + 7601 .LVL599: +7816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the ETR Bits */ +7818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 7602 .loc 1 7818 3 is_stmt 1 view .LVU2489 + 7603 .loc 1 7818 11 is_stmt 0 view .LVU2490 + ARM GAS /tmp/ccGFzgX3.s page 305 + + + 7604 0004 24F47F4C bic ip, r4, #65280 + 7605 .LVL600: +7819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Prescaler, the Filter value and the Polarity */ +7821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + 7606 .loc 1 7821 3 is_stmt 1 view .LVU2491 + 7607 .loc 1 7821 67 is_stmt 0 view .LVU2492 + 7608 0008 42EA0322 orr r2, r2, r3, lsl #8 + 7609 .LVL601: + 7610 .loc 1 7821 45 view .LVU2493 + 7611 000c 0A43 orrs r2, r2, r1 + 7612 .loc 1 7821 11 view .LVU2494 + 7613 000e 42EA0C02 orr r2, r2, ip + 7614 .LVL602: +7822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx SMCR */ +7824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->SMCR = tmpsmcr; + 7615 .loc 1 7824 3 is_stmt 1 view .LVU2495 + 7616 .loc 1 7824 14 is_stmt 0 view .LVU2496 + 7617 0012 8260 str r2, [r0, #8] +7825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7618 .loc 1 7825 1 view .LVU2497 + 7619 0014 5DF8044B ldr r4, [sp], #4 + 7620 .LCFI76: + 7621 .cfi_restore 4 + 7622 .cfi_def_cfa_offset 0 + 7623 0018 7047 bx lr + 7624 .cfi_endproc + 7625 .LFE260: + 7627 .section .text.HAL_TIM_ConfigOCrefClear,"ax",%progbits + 7628 .align 1 + 7629 .global HAL_TIM_ConfigOCrefClear + 7630 .syntax unified + 7631 .thumb + 7632 .thumb_func + 7634 HAL_TIM_ConfigOCrefClear: + 7635 .LVL603: + 7636 .LFB211: +5291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 7637 .loc 1 5291 1 is_stmt 1 view -0 + 7638 .cfi_startproc + 7639 @ args = 0, pretend = 0, frame = 0 + 7640 @ frame_needed = 0, uses_anonymous_args = 0 +5292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7641 .loc 1 5292 3 view .LVU2499 +5295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + 7642 .loc 1 5295 3 view .LVU2500 +5296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7643 .loc 1 5296 3 view .LVU2501 +5299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7644 .loc 1 5299 3 view .LVU2502 +5299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7645 .loc 1 5299 3 view .LVU2503 + 7646 0000 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 7647 0004 012B cmp r3, #1 + 7648 0006 00F09B80 beq .L465 +5291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + ARM GAS /tmp/ccGFzgX3.s page 306 + + + 7649 .loc 1 5291 1 is_stmt 0 view .LVU2504 + 7650 000a 70B5 push {r4, r5, r6, lr} + 7651 .LCFI77: + 7652 .cfi_def_cfa_offset 16 + 7653 .cfi_offset 4, -16 + 7654 .cfi_offset 5, -12 + 7655 .cfi_offset 6, -8 + 7656 .cfi_offset 14, -4 + 7657 000c 0446 mov r4, r0 + 7658 000e 0D46 mov r5, r1 + 7659 0010 1646 mov r6, r2 +5299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7660 .loc 1 5299 3 is_stmt 1 discriminator 2 view .LVU2505 + 7661 0012 0123 movs r3, #1 + 7662 0014 80F83C30 strb r3, [r0, #60] +5299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7663 .loc 1 5299 3 discriminator 2 view .LVU2506 +5301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7664 .loc 1 5301 3 view .LVU2507 +5301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7665 .loc 1 5301 15 is_stmt 0 view .LVU2508 + 7666 0018 0223 movs r3, #2 + 7667 001a 80F83D30 strb r3, [r0, #61] +5303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7668 .loc 1 5303 3 is_stmt 1 view .LVU2509 +5303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7669 .loc 1 5303 28 is_stmt 0 view .LVU2510 + 7670 001e 4B68 ldr r3, [r1, #4] +5303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7671 .loc 1 5303 3 view .LVU2511 + 7672 0020 4BB1 cbz r3, .L447 + 7673 0022 012B cmp r3, #1 + 7674 0024 1BD0 beq .L448 + 7675 0026 0120 movs r0, #1 + 7676 .LVL604: + 7677 .L449: +5432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7678 .loc 1 5432 3 is_stmt 1 view .LVU2512 +5432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7679 .loc 1 5432 15 is_stmt 0 view .LVU2513 + 7680 0028 0123 movs r3, #1 + 7681 002a 84F83D30 strb r3, [r4, #61] +5434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7682 .loc 1 5434 3 is_stmt 1 view .LVU2514 +5434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7683 .loc 1 5434 3 view .LVU2515 + 7684 002e 0023 movs r3, #0 + 7685 0030 84F83C30 strb r3, [r4, #60] +5434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7686 .loc 1 5434 3 view .LVU2516 +5436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7687 .loc 1 5436 3 view .LVU2517 + 7688 .L446: +5437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7689 .loc 1 5437 1 is_stmt 0 view .LVU2518 + 7690 0034 70BD pop {r4, r5, r6, pc} + 7691 .LVL605: + ARM GAS /tmp/ccGFzgX3.s page 307 + + + 7692 .L447: +5308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 7693 .loc 1 5308 7 is_stmt 1 view .LVU2519 + 7694 0036 0268 ldr r2, [r0] + 7695 .LVL606: +5308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 7696 .loc 1 5308 7 is_stmt 0 view .LVU2520 + 7697 0038 9368 ldr r3, [r2, #8] + 7698 003a 23F47F43 bic r3, r3, #65280 + 7699 003e 9360 str r3, [r2, #8] +5309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7700 .loc 1 5309 7 is_stmt 1 view .LVU2521 +5339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7701 .loc 1 5339 3 view .LVU2522 + 7702 .LVL607: + 7703 .L450: +5341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7704 .loc 1 5341 5 view .LVU2523 + 7705 0040 142E cmp r6, #20 + 7706 0042 7BD8 bhi .L466 + 7707 0044 DFE806F0 tbb [pc, r6] + 7708 .L453: + 7709 0048 1A .byte (.L458-.L453)/2 + 7710 0049 7A .byte (.L466-.L453)/2 + 7711 004a 7A .byte (.L466-.L453)/2 + 7712 004b 7A .byte (.L466-.L453)/2 + 7713 004c 2A .byte (.L457-.L453)/2 + 7714 004d 7A .byte (.L466-.L453)/2 + 7715 004e 7A .byte (.L466-.L453)/2 + 7716 004f 7A .byte (.L466-.L453)/2 + 7717 0050 3A .byte (.L456-.L453)/2 + 7718 0051 7A .byte (.L466-.L453)/2 + 7719 0052 7A .byte (.L466-.L453)/2 + 7720 0053 7A .byte (.L466-.L453)/2 + 7721 0054 4A .byte (.L455-.L453)/2 + 7722 0055 7A .byte (.L466-.L453)/2 + 7723 0056 7A .byte (.L466-.L453)/2 + 7724 0057 7A .byte (.L466-.L453)/2 + 7725 0058 5A .byte (.L454-.L453)/2 + 7726 0059 7A .byte (.L466-.L453)/2 + 7727 005a 7A .byte (.L466-.L453)/2 + 7728 005b 7A .byte (.L466-.L453)/2 + 7729 005c 6A .byte (.L452-.L453)/2 + 7730 .LVL608: + 7731 005d 00 .p2align 1 + 7732 .L448: +5315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + 7733 .loc 1 5315 7 view .LVU2524 +5316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + 7734 .loc 1 5316 7 view .LVU2525 +5317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7735 .loc 1 5317 7 view .LVU2526 +5320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7736 .loc 1 5320 7 view .LVU2527 +5320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7737 .loc 1 5320 28 is_stmt 0 view .LVU2528 + 7738 005e C968 ldr r1, [r1, #12] + ARM GAS /tmp/ccGFzgX3.s page 308 + + + 7739 .LVL609: +5320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7740 .loc 1 5320 10 view .LVU2529 + 7741 0060 31B1 cbz r1, .L451 +5322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); + 7742 .loc 1 5322 9 is_stmt 1 view .LVU2530 +5322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); + 7743 .loc 1 5322 21 is_stmt 0 view .LVU2531 + 7744 0062 0120 movs r0, #1 + 7745 .LVL610: +5322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); + 7746 .loc 1 5322 21 view .LVU2532 + 7747 0064 84F83D00 strb r0, [r4, #61] +5323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + 7748 .loc 1 5323 9 is_stmt 1 view .LVU2533 +5323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + 7749 .loc 1 5323 9 view .LVU2534 + 7750 0068 0023 movs r3, #0 + 7751 006a 84F83C30 strb r3, [r4, #60] +5323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + 7752 .loc 1 5323 9 view .LVU2535 +5324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7753 .loc 1 5324 9 view .LVU2536 +5324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7754 .loc 1 5324 16 is_stmt 0 view .LVU2537 + 7755 006e E1E7 b .L446 + 7756 .LVL611: + 7757 .L451: +5327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClearInputConfig->ClearInputPrescaler, + 7758 .loc 1 5327 7 is_stmt 1 view .LVU2538 + 7759 0070 2B69 ldr r3, [r5, #16] + 7760 0072 AA68 ldr r2, [r5, #8] + 7761 .LVL612: +5327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClearInputConfig->ClearInputPrescaler, + 7762 .loc 1 5327 7 is_stmt 0 view .LVU2539 + 7763 0074 0068 ldr r0, [r0] + 7764 .LVL613: +5327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClearInputConfig->ClearInputPrescaler, + 7765 .loc 1 5327 7 view .LVU2540 + 7766 0076 FFF7FEFF bl TIM_ETR_SetConfig + 7767 .LVL614: +5331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7768 .loc 1 5331 7 is_stmt 1 view .LVU2541 +5339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7769 .loc 1 5339 3 view .LVU2542 + 7770 007a E1E7 b .L450 + 7771 .L458: +5345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7772 .loc 1 5345 9 view .LVU2543 +5345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7773 .loc 1 5345 30 is_stmt 0 view .LVU2544 + 7774 007c 2B68 ldr r3, [r5] +5345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7775 .loc 1 5345 12 view .LVU2545 + 7776 007e 33B1 cbz r3, .L459 +5348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7777 .loc 1 5348 11 is_stmt 1 view .LVU2546 + ARM GAS /tmp/ccGFzgX3.s page 309 + + + 7778 0080 2268 ldr r2, [r4] + 7779 0082 9369 ldr r3, [r2, #24] + 7780 0084 43F08003 orr r3, r3, #128 + 7781 0088 9361 str r3, [r2, #24] + 7782 008a 0020 movs r0, #0 + 7783 008c CCE7 b .L449 + 7784 .L459: +5353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7785 .loc 1 5353 11 view .LVU2547 + 7786 008e 2268 ldr r2, [r4] + 7787 0090 9369 ldr r3, [r2, #24] + 7788 0092 23F08003 bic r3, r3, #128 + 7789 0096 9361 str r3, [r2, #24] + 7790 0098 0020 movs r0, #0 + 7791 009a C5E7 b .L449 + 7792 .L457: +5359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7793 .loc 1 5359 9 view .LVU2548 +5359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7794 .loc 1 5359 30 is_stmt 0 view .LVU2549 + 7795 009c 2B68 ldr r3, [r5] +5359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7796 .loc 1 5359 12 view .LVU2550 + 7797 009e 33B1 cbz r3, .L460 +5362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7798 .loc 1 5362 11 is_stmt 1 view .LVU2551 + 7799 00a0 2268 ldr r2, [r4] + 7800 00a2 9369 ldr r3, [r2, #24] + 7801 00a4 43F40043 orr r3, r3, #32768 + 7802 00a8 9361 str r3, [r2, #24] + 7803 00aa 0020 movs r0, #0 + 7804 00ac BCE7 b .L449 + 7805 .L460: +5367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7806 .loc 1 5367 11 view .LVU2552 + 7807 00ae 2268 ldr r2, [r4] + 7808 00b0 9369 ldr r3, [r2, #24] + 7809 00b2 23F40043 bic r3, r3, #32768 + 7810 00b6 9361 str r3, [r2, #24] + 7811 00b8 0020 movs r0, #0 + 7812 00ba B5E7 b .L449 + 7813 .L456: +5373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7814 .loc 1 5373 9 view .LVU2553 +5373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7815 .loc 1 5373 30 is_stmt 0 view .LVU2554 + 7816 00bc 2B68 ldr r3, [r5] +5373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7817 .loc 1 5373 12 view .LVU2555 + 7818 00be 33B1 cbz r3, .L461 +5376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7819 .loc 1 5376 11 is_stmt 1 view .LVU2556 + 7820 00c0 2268 ldr r2, [r4] + 7821 00c2 D369 ldr r3, [r2, #28] + 7822 00c4 43F08003 orr r3, r3, #128 + 7823 00c8 D361 str r3, [r2, #28] + 7824 00ca 0020 movs r0, #0 + ARM GAS /tmp/ccGFzgX3.s page 310 + + + 7825 00cc ACE7 b .L449 + 7826 .L461: +5381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7827 .loc 1 5381 11 view .LVU2557 + 7828 00ce 2268 ldr r2, [r4] + 7829 00d0 D369 ldr r3, [r2, #28] + 7830 00d2 23F08003 bic r3, r3, #128 + 7831 00d6 D361 str r3, [r2, #28] + 7832 00d8 0020 movs r0, #0 + 7833 00da A5E7 b .L449 + 7834 .L455: +5387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7835 .loc 1 5387 9 view .LVU2558 +5387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7836 .loc 1 5387 30 is_stmt 0 view .LVU2559 + 7837 00dc 2B68 ldr r3, [r5] +5387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7838 .loc 1 5387 12 view .LVU2560 + 7839 00de 33B1 cbz r3, .L462 +5390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7840 .loc 1 5390 11 is_stmt 1 view .LVU2561 + 7841 00e0 2268 ldr r2, [r4] + 7842 00e2 D369 ldr r3, [r2, #28] + 7843 00e4 43F40043 orr r3, r3, #32768 + 7844 00e8 D361 str r3, [r2, #28] + 7845 00ea 0020 movs r0, #0 + 7846 00ec 9CE7 b .L449 + 7847 .L462: +5395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7848 .loc 1 5395 11 view .LVU2562 + 7849 00ee 2268 ldr r2, [r4] + 7850 00f0 D369 ldr r3, [r2, #28] + 7851 00f2 23F40043 bic r3, r3, #32768 + 7852 00f6 D361 str r3, [r2, #28] + 7853 00f8 0020 movs r0, #0 + 7854 00fa 95E7 b .L449 + 7855 .L454: +5401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7856 .loc 1 5401 9 view .LVU2563 +5401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7857 .loc 1 5401 30 is_stmt 0 view .LVU2564 + 7858 00fc 2B68 ldr r3, [r5] +5401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7859 .loc 1 5401 12 view .LVU2565 + 7860 00fe 33B1 cbz r3, .L463 +5404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7861 .loc 1 5404 11 is_stmt 1 view .LVU2566 + 7862 0100 2268 ldr r2, [r4] + 7863 0102 536D ldr r3, [r2, #84] + 7864 0104 43F08003 orr r3, r3, #128 + 7865 0108 5365 str r3, [r2, #84] + 7866 010a 0020 movs r0, #0 + 7867 010c 8CE7 b .L449 + 7868 .L463: +5409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7869 .loc 1 5409 11 view .LVU2567 + 7870 010e 2268 ldr r2, [r4] + ARM GAS /tmp/ccGFzgX3.s page 311 + + + 7871 0110 536D ldr r3, [r2, #84] + 7872 0112 23F08003 bic r3, r3, #128 + 7873 0116 5365 str r3, [r2, #84] + 7874 0118 0020 movs r0, #0 + 7875 011a 85E7 b .L449 + 7876 .L452: +5415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7877 .loc 1 5415 9 view .LVU2568 +5415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7878 .loc 1 5415 30 is_stmt 0 view .LVU2569 + 7879 011c 2B68 ldr r3, [r5] +5415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7880 .loc 1 5415 12 view .LVU2570 + 7881 011e 33B1 cbz r3, .L464 +5418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7882 .loc 1 5418 11 is_stmt 1 view .LVU2571 + 7883 0120 2268 ldr r2, [r4] + 7884 0122 536D ldr r3, [r2, #84] + 7885 0124 43F40043 orr r3, r3, #32768 + 7886 0128 5365 str r3, [r2, #84] + 7887 012a 0020 movs r0, #0 + 7888 012c 7CE7 b .L449 + 7889 .L464: +5423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7890 .loc 1 5423 11 view .LVU2572 + 7891 012e 2268 ldr r2, [r4] + 7892 0130 536D ldr r3, [r2, #84] + 7893 0132 23F40043 bic r3, r3, #32768 + 7894 0136 5365 str r3, [r2, #84] + 7895 0138 0020 movs r0, #0 + 7896 013a 75E7 b .L449 + 7897 .L466: +5341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7898 .loc 1 5341 5 is_stmt 0 view .LVU2573 + 7899 013c 0020 movs r0, #0 + 7900 013e 73E7 b .L449 + 7901 .LVL615: + 7902 .L465: + 7903 .LCFI78: + 7904 .cfi_def_cfa_offset 0 + 7905 .cfi_restore 4 + 7906 .cfi_restore 5 + 7907 .cfi_restore 6 + 7908 .cfi_restore 14 +5299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7909 .loc 1 5299 3 discriminator 1 view .LVU2574 + 7910 0140 0220 movs r0, #2 + 7911 .LVL616: +5437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7912 .loc 1 5437 1 view .LVU2575 + 7913 0142 7047 bx lr + 7914 .cfi_endproc + 7915 .LFE211: + 7917 .section .text.HAL_TIM_ConfigClockSource,"ax",%progbits + 7918 .align 1 + 7919 .global HAL_TIM_ConfigClockSource + 7920 .syntax unified + ARM GAS /tmp/ccGFzgX3.s page 312 + + + 7921 .thumb + 7922 .thumb_func + 7924 HAL_TIM_ConfigClockSource: + 7925 .LVL617: + 7926 .LFB212: +5447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 7927 .loc 1 5447 1 is_stmt 1 view -0 + 7928 .cfi_startproc + 7929 @ args = 0, pretend = 0, frame = 0 + 7930 @ frame_needed = 0, uses_anonymous_args = 0 +5448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 7931 .loc 1 5448 3 view .LVU2577 +5449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7932 .loc 1 5449 3 view .LVU2578 +5452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7933 .loc 1 5452 3 view .LVU2579 +5452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7934 .loc 1 5452 3 view .LVU2580 + 7935 0000 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 7936 0004 012B cmp r3, #1 + 7937 0006 76D0 beq .L482 +5447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 7938 .loc 1 5447 1 is_stmt 0 view .LVU2581 + 7939 0008 10B5 push {r4, lr} + 7940 .LCFI79: + 7941 .cfi_def_cfa_offset 8 + 7942 .cfi_offset 4, -8 + 7943 .cfi_offset 14, -4 + 7944 000a 0446 mov r4, r0 +5452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7945 .loc 1 5452 3 is_stmt 1 discriminator 2 view .LVU2582 + 7946 000c 0123 movs r3, #1 + 7947 000e 80F83C30 strb r3, [r0, #60] +5452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7948 .loc 1 5452 3 discriminator 2 view .LVU2583 +5454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7949 .loc 1 5454 3 view .LVU2584 +5454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7950 .loc 1 5454 15 is_stmt 0 view .LVU2585 + 7951 0012 0223 movs r3, #2 + 7952 0014 80F83D30 strb r3, [r0, #61] +5457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7953 .loc 1 5457 3 is_stmt 1 view .LVU2586 +5460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + 7954 .loc 1 5460 3 view .LVU2587 +5460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + 7955 .loc 1 5460 17 is_stmt 0 view .LVU2588 + 7956 0018 0268 ldr r2, [r0] +5460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + 7957 .loc 1 5460 11 view .LVU2589 + 7958 001a 9068 ldr r0, [r2, #8] + 7959 .LVL618: +5461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 7960 .loc 1 5461 3 is_stmt 1 view .LVU2590 +5462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR = tmpsmcr; + 7961 .loc 1 5462 3 view .LVU2591 +5462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->SMCR = tmpsmcr; + ARM GAS /tmp/ccGFzgX3.s page 313 + + + 7962 .loc 1 5462 11 is_stmt 0 view .LVU2592 + 7963 001c 374B ldr r3, .L491 + 7964 001e 0340 ands r3, r3, r0 + 7965 .LVL619: +5463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7966 .loc 1 5463 3 is_stmt 1 view .LVU2593 +5463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7967 .loc 1 5463 24 is_stmt 0 view .LVU2594 + 7968 0020 9360 str r3, [r2, #8] +5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7969 .loc 1 5465 3 is_stmt 1 view .LVU2595 +5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7970 .loc 1 5465 29 is_stmt 0 view .LVU2596 + 7971 0022 0B68 ldr r3, [r1] + 7972 .LVL620: +5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 7973 .loc 1 5465 3 view .LVU2597 + 7974 0024 602B cmp r3, #96 + 7975 0026 4CD0 beq .L473 + 7976 0028 23D8 bhi .L474 + 7977 002a 402B cmp r3, #64 + 7978 002c 54D0 beq .L475 + 7979 002e 11D8 bhi .L476 + 7980 0030 202B cmp r3, #32 + 7981 0032 03D0 beq .L477 + 7982 0034 0AD8 bhi .L478 + 7983 0036 0BB1 cbz r3, .L477 + 7984 0038 102B cmp r3, #16 + 7985 003a 05D1 bne .L489 + 7986 .L477: +5571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 7987 .loc 1 5571 7 is_stmt 1 view .LVU2598 +5573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 7988 .loc 1 5573 7 view .LVU2599 + 7989 003c 1946 mov r1, r3 + 7990 .LVL621: +5573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 7991 .loc 1 5573 7 is_stmt 0 view .LVU2600 + 7992 003e 2068 ldr r0, [r4] + 7993 0040 FFF7FEFF bl TIM_ITRx_SetConfig + 7994 .LVL622: +5574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7995 .loc 1 5574 7 is_stmt 1 view .LVU2601 +5448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 7996 .loc 1 5448 21 is_stmt 0 view .LVU2602 + 7997 0044 0020 movs r0, #0 +5574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 7998 .loc 1 5574 7 view .LVU2603 + 7999 0046 28E0 b .L479 + 8000 .LVL623: + 8001 .L489: +5578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8002 .loc 1 5578 14 view .LVU2604 + 8003 0048 0120 movs r0, #1 + 8004 004a 26E0 b .L479 + 8005 .L478: +5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 314 + + + 8006 .loc 1 5465 3 view .LVU2605 + 8007 004c 302B cmp r3, #48 + 8008 004e F5D0 beq .L477 +5578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8009 .loc 1 5578 14 view .LVU2606 + 8010 0050 0120 movs r0, #1 + 8011 0052 22E0 b .L479 + 8012 .L476: +5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8013 .loc 1 5465 3 view .LVU2607 + 8014 0054 502B cmp r3, #80 + 8015 0056 0AD1 bne .L490 +5520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8016 .loc 1 5520 7 is_stmt 1 view .LVU2608 +5523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + 8017 .loc 1 5523 7 view .LVU2609 +5524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8018 .loc 1 5524 7 view .LVU2610 +5526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 8019 .loc 1 5526 7 view .LVU2611 + 8020 0058 CA68 ldr r2, [r1, #12] + 8021 .LVL624: +5526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 8022 .loc 1 5526 7 is_stmt 0 view .LVU2612 + 8023 005a 4968 ldr r1, [r1, #4] + 8024 .LVL625: +5526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 8025 .loc 1 5526 7 view .LVU2613 + 8026 005c 2068 ldr r0, [r4] + 8027 .LVL626: +5526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 8028 .loc 1 5526 7 view .LVU2614 + 8029 005e FFF7FEFF bl TIM_TI1_ConfigInputStage + 8030 .LVL627: +5529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8031 .loc 1 5529 7 is_stmt 1 view .LVU2615 + 8032 0062 5021 movs r1, #80 + 8033 0064 2068 ldr r0, [r4] + 8034 0066 FFF7FEFF bl TIM_ITRx_SetConfig + 8035 .LVL628: +5530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8036 .loc 1 5530 7 view .LVU2616 +5448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 8037 .loc 1 5448 21 is_stmt 0 view .LVU2617 + 8038 006a 0020 movs r0, #0 +5530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8039 .loc 1 5530 7 view .LVU2618 + 8040 006c 15E0 b .L479 + 8041 .LVL629: + 8042 .L490: +5578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8043 .loc 1 5578 14 view .LVU2619 + 8044 006e 0120 movs r0, #1 + 8045 0070 13E0 b .L479 + 8046 .L474: +5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8047 .loc 1 5465 3 view .LVU2620 + ARM GAS /tmp/ccGFzgX3.s page 315 + + + 8048 0072 B3F5805F cmp r3, #4096 + 8049 0076 3AD0 beq .L483 + 8050 0078 B3F5005F cmp r3, #8192 + 8051 007c 14D0 beq .L481 + 8052 007e 702B cmp r3, #112 + 8053 0080 37D1 bne .L484 +5476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8054 .loc 1 5476 7 is_stmt 1 view .LVU2621 +5479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + 8055 .loc 1 5479 7 view .LVU2622 +5480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + 8056 .loc 1 5480 7 view .LVU2623 +5481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8057 .loc 1 5481 7 view .LVU2624 +5484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPrescaler, + 8058 .loc 1 5484 7 view .LVU2625 + 8059 0082 CB68 ldr r3, [r1, #12] + 8060 0084 4A68 ldr r2, [r1, #4] + 8061 .LVL630: +5484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPrescaler, + 8062 .loc 1 5484 7 is_stmt 0 view .LVU2626 + 8063 0086 8968 ldr r1, [r1, #8] + 8064 .LVL631: +5484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPrescaler, + 8065 .loc 1 5484 7 view .LVU2627 + 8066 0088 2068 ldr r0, [r4] + 8067 .LVL632: +5484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPrescaler, + 8068 .loc 1 5484 7 view .LVU2628 + 8069 008a FFF7FEFF bl TIM_ETR_SetConfig + 8070 .LVL633: +5490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + 8071 .loc 1 5490 7 is_stmt 1 view .LVU2629 +5490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + 8072 .loc 1 5490 21 is_stmt 0 view .LVU2630 + 8073 008e 2268 ldr r2, [r4] +5490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + 8074 .loc 1 5490 15 view .LVU2631 + 8075 0090 9368 ldr r3, [r2, #8] + 8076 .LVL634: +5491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx SMCR */ + 8077 .loc 1 5491 7 is_stmt 1 view .LVU2632 +5491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Write to TIMx SMCR */ + 8078 .loc 1 5491 15 is_stmt 0 view .LVU2633 + 8079 0092 43F07703 orr r3, r3, #119 + 8080 .LVL635: +5493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8081 .loc 1 5493 7 is_stmt 1 view .LVU2634 +5493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8082 .loc 1 5493 28 is_stmt 0 view .LVU2635 + 8083 0096 9360 str r3, [r2, #8] +5494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8084 .loc 1 5494 7 is_stmt 1 view .LVU2636 +5448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 8085 .loc 1 5448 21 is_stmt 0 view .LVU2637 + 8086 0098 0020 movs r0, #0 + 8087 .LVL636: + ARM GAS /tmp/ccGFzgX3.s page 316 + + + 8088 .L479: +5581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8089 .loc 1 5581 3 is_stmt 1 view .LVU2638 +5581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8090 .loc 1 5581 15 is_stmt 0 view .LVU2639 + 8091 009a 0123 movs r3, #1 + 8092 009c 84F83D30 strb r3, [r4, #61] +5583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8093 .loc 1 5583 3 is_stmt 1 view .LVU2640 +5583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8094 .loc 1 5583 3 view .LVU2641 + 8095 00a0 0023 movs r3, #0 + 8096 00a2 84F83C30 strb r3, [r4, #60] +5583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8097 .loc 1 5583 3 view .LVU2642 +5585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8098 .loc 1 5585 3 view .LVU2643 +5586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8099 .loc 1 5586 1 is_stmt 0 view .LVU2644 + 8100 00a6 10BD pop {r4, pc} + 8101 .LVL637: + 8102 .L481: +5500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8103 .loc 1 5500 7 is_stmt 1 view .LVU2645 +5503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + 8104 .loc 1 5503 7 view .LVU2646 +5504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + 8105 .loc 1 5504 7 view .LVU2647 +5505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8106 .loc 1 5505 7 view .LVU2648 +5508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPrescaler, + 8107 .loc 1 5508 7 view .LVU2649 + 8108 00a8 CB68 ldr r3, [r1, #12] + 8109 00aa 4A68 ldr r2, [r1, #4] + 8110 .LVL638: +5508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPrescaler, + 8111 .loc 1 5508 7 is_stmt 0 view .LVU2650 + 8112 00ac 8968 ldr r1, [r1, #8] + 8113 .LVL639: +5508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPrescaler, + 8114 .loc 1 5508 7 view .LVU2651 + 8115 00ae 2068 ldr r0, [r4] + 8116 .LVL640: +5508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPrescaler, + 8117 .loc 1 5508 7 view .LVU2652 + 8118 00b0 FFF7FEFF bl TIM_ETR_SetConfig + 8119 .LVL641: +5513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8120 .loc 1 5513 7 is_stmt 1 view .LVU2653 +5513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8121 .loc 1 5513 11 is_stmt 0 view .LVU2654 + 8122 00b4 2268 ldr r2, [r4] +5513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8123 .loc 1 5513 21 view .LVU2655 + 8124 00b6 9368 ldr r3, [r2, #8] +5513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8125 .loc 1 5513 28 view .LVU2656 + ARM GAS /tmp/ccGFzgX3.s page 317 + + + 8126 00b8 43F48043 orr r3, r3, #16384 + 8127 00bc 9360 str r3, [r2, #8] +5514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8128 .loc 1 5514 7 is_stmt 1 view .LVU2657 +5448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 8129 .loc 1 5448 21 is_stmt 0 view .LVU2658 + 8130 00be 0020 movs r0, #0 +5514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8131 .loc 1 5514 7 view .LVU2659 + 8132 00c0 EBE7 b .L479 + 8133 .LVL642: + 8134 .L473: +5536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8135 .loc 1 5536 7 is_stmt 1 view .LVU2660 +5539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + 8136 .loc 1 5539 7 view .LVU2661 +5540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8137 .loc 1 5540 7 view .LVU2662 +5542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 8138 .loc 1 5542 7 view .LVU2663 + 8139 00c2 CA68 ldr r2, [r1, #12] + 8140 .LVL643: +5542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 8141 .loc 1 5542 7 is_stmt 0 view .LVU2664 + 8142 00c4 4968 ldr r1, [r1, #4] + 8143 .LVL644: +5542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 8144 .loc 1 5542 7 view .LVU2665 + 8145 00c6 2068 ldr r0, [r4] + 8146 .LVL645: +5542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 8147 .loc 1 5542 7 view .LVU2666 + 8148 00c8 FFF7FEFF bl TIM_TI2_ConfigInputStage + 8149 .LVL646: +5545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8150 .loc 1 5545 7 is_stmt 1 view .LVU2667 + 8151 00cc 6021 movs r1, #96 + 8152 00ce 2068 ldr r0, [r4] + 8153 00d0 FFF7FEFF bl TIM_ITRx_SetConfig + 8154 .LVL647: +5546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8155 .loc 1 5546 7 view .LVU2668 +5448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 8156 .loc 1 5448 21 is_stmt 0 view .LVU2669 + 8157 00d4 0020 movs r0, #0 +5546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8158 .loc 1 5546 7 view .LVU2670 + 8159 00d6 E0E7 b .L479 + 8160 .LVL648: + 8161 .L475: +5552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8162 .loc 1 5552 7 is_stmt 1 view .LVU2671 +5555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + 8163 .loc 1 5555 7 view .LVU2672 +5556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8164 .loc 1 5556 7 view .LVU2673 +5558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + ARM GAS /tmp/ccGFzgX3.s page 318 + + + 8165 .loc 1 5558 7 view .LVU2674 + 8166 00d8 CA68 ldr r2, [r1, #12] + 8167 .LVL649: +5558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 8168 .loc 1 5558 7 is_stmt 0 view .LVU2675 + 8169 00da 4968 ldr r1, [r1, #4] + 8170 .LVL650: +5558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 8171 .loc 1 5558 7 view .LVU2676 + 8172 00dc 2068 ldr r0, [r4] + 8173 .LVL651: +5558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 8174 .loc 1 5558 7 view .LVU2677 + 8175 00de FFF7FEFF bl TIM_TI1_ConfigInputStage + 8176 .LVL652: +5561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8177 .loc 1 5561 7 is_stmt 1 view .LVU2678 + 8178 00e2 4021 movs r1, #64 + 8179 00e4 2068 ldr r0, [r4] + 8180 00e6 FFF7FEFF bl TIM_ITRx_SetConfig + 8181 .LVL653: +5562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8182 .loc 1 5562 7 view .LVU2679 +5448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 8183 .loc 1 5448 21 is_stmt 0 view .LVU2680 + 8184 00ea 0020 movs r0, #0 +5562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8185 .loc 1 5562 7 view .LVU2681 + 8186 00ec D5E7 b .L479 + 8187 .LVL654: + 8188 .L483: +5465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8189 .loc 1 5465 3 view .LVU2682 + 8190 00ee 0020 movs r0, #0 + 8191 00f0 D3E7 b .L479 + 8192 .L484: +5578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8193 .loc 1 5578 14 view .LVU2683 + 8194 00f2 0120 movs r0, #1 + 8195 00f4 D1E7 b .L479 + 8196 .LVL655: + 8197 .L482: + 8198 .LCFI80: + 8199 .cfi_def_cfa_offset 0 + 8200 .cfi_restore 4 + 8201 .cfi_restore 14 +5452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8202 .loc 1 5452 3 discriminator 1 view .LVU2684 + 8203 00f6 0220 movs r0, #2 + 8204 .LVL656: +5586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8205 .loc 1 5586 1 view .LVU2685 + 8206 00f8 7047 bx lr + 8207 .L492: + 8208 00fa 00BF .align 2 + 8209 .L491: + 8210 00fc 8800FEFF .word -130936 + ARM GAS /tmp/ccGFzgX3.s page 319 + + + 8211 .cfi_endproc + 8212 .LFE212: + 8214 .section .text.TIM_SlaveTimer_SetConfig,"ax",%progbits + 8215 .align 1 + 8216 .syntax unified + 8217 .thumb + 8218 .thumb_func + 8220 TIM_SlaveTimer_SetConfig: + 8221 .LVL657: + 8222 .LFB252: +7384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 8223 .loc 1 7384 1 is_stmt 1 view -0 + 8224 .cfi_startproc + 8225 @ args = 0, pretend = 0, frame = 0 + 8226 @ frame_needed = 0, uses_anonymous_args = 0 +7384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 8227 .loc 1 7384 1 is_stmt 0 view .LVU2687 + 8228 0000 10B5 push {r4, lr} + 8229 .LCFI81: + 8230 .cfi_def_cfa_offset 8 + 8231 .cfi_offset 4, -8 + 8232 .cfi_offset 14, -4 +7385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 8233 .loc 1 7385 3 is_stmt 1 view .LVU2688 + 8234 .LVL658: +7386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccmr1; + 8235 .loc 1 7386 3 view .LVU2689 +7387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpccer; + 8236 .loc 1 7387 3 view .LVU2690 +7388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8237 .loc 1 7388 3 view .LVU2691 +7391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8238 .loc 1 7391 3 view .LVU2692 +7391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8239 .loc 1 7391 17 is_stmt 0 view .LVU2693 + 8240 0002 0468 ldr r4, [r0] +7391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8241 .loc 1 7391 11 view .LVU2694 + 8242 0004 A268 ldr r2, [r4, #8] + 8243 .LVL659: +7394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Input Trigger source */ + 8244 .loc 1 7394 3 is_stmt 1 view .LVU2695 +7394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the Input Trigger source */ + 8245 .loc 1 7394 11 is_stmt 0 view .LVU2696 + 8246 0006 22F07002 bic r2, r2, #112 + 8247 .LVL660: +7396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8248 .loc 1 7396 3 is_stmt 1 view .LVU2697 +7396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8249 .loc 1 7396 26 is_stmt 0 view .LVU2698 + 8250 000a 4B68 ldr r3, [r1, #4] +7396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8251 .loc 1 7396 11 view .LVU2699 + 8252 000c 1343 orrs r3, r3, r2 + 8253 .LVL661: +7399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the slave mode */ + 8254 .loc 1 7399 3 is_stmt 1 view .LVU2700 + ARM GAS /tmp/ccGFzgX3.s page 320 + + +7399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set the slave mode */ + 8255 .loc 1 7399 11 is_stmt 0 view .LVU2701 + 8256 000e 2A4A ldr r2, .L509 + 8257 0010 1A40 ands r2, r2, r3 + 8258 .LVL662: +7401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8259 .loc 1 7401 3 is_stmt 1 view .LVU2702 +7401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8260 .loc 1 7401 26 is_stmt 0 view .LVU2703 + 8261 0012 0B68 ldr r3, [r1] +7401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8262 .loc 1 7401 11 view .LVU2704 + 8263 0014 1343 orrs r3, r3, r2 + 8264 .LVL663: +7404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8265 .loc 1 7404 3 is_stmt 1 view .LVU2705 +7404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8266 .loc 1 7404 24 is_stmt 0 view .LVU2706 + 8267 0016 A360 str r3, [r4, #8] +7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8268 .loc 1 7407 3 is_stmt 1 view .LVU2707 +7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8269 .loc 1 7407 23 is_stmt 0 view .LVU2708 + 8270 0018 4B68 ldr r3, [r1, #4] + 8271 .LVL664: +7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8272 .loc 1 7407 3 view .LVU2709 + 8273 001a 502B cmp r3, #80 + 8274 001c 30D0 beq .L494 + 8275 001e 0BD9 bls .L508 + 8276 0020 602B cmp r3, #96 + 8277 0022 34D0 beq .L499 + 8278 0024 702B cmp r3, #112 + 8279 0026 43D1 bne .L505 +7412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + 8280 .loc 1 7412 7 is_stmt 1 view .LVU2710 +7413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + 8281 .loc 1 7413 7 view .LVU2711 +7414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + 8282 .loc 1 7414 7 view .LVU2712 +7415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Configure the ETR Trigger source */ + 8283 .loc 1 7415 7 view .LVU2713 +7417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sSlaveConfig->TriggerPrescaler, + 8284 .loc 1 7417 7 view .LVU2714 + 8285 0028 0B69 ldr r3, [r1, #16] + 8286 002a 8A68 ldr r2, [r1, #8] + 8287 002c C968 ldr r1, [r1, #12] + 8288 .LVL665: +7417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sSlaveConfig->TriggerPrescaler, + 8289 .loc 1 7417 7 is_stmt 0 view .LVU2715 + 8290 002e 0068 ldr r0, [r0] + 8291 .LVL666: +7417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sSlaveConfig->TriggerPrescaler, + 8292 .loc 1 7417 7 view .LVU2716 + 8293 0030 FFF7FEFF bl TIM_ETR_SetConfig + 8294 .LVL667: +7421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + ARM GAS /tmp/ccGFzgX3.s page 321 + + + 8295 .loc 1 7421 7 is_stmt 1 view .LVU2717 +7385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 8296 .loc 1 7385 21 is_stmt 0 view .LVU2718 + 8297 0034 0020 movs r0, #0 + 8298 .L497: + 8299 .LVL668: +7494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8300 .loc 1 7494 1 view .LVU2719 + 8301 0036 10BD pop {r4, pc} + 8302 .LVL669: + 8303 .L508: +7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8304 .loc 1 7407 3 view .LVU2720 + 8305 0038 402B cmp r3, #64 + 8306 003a 0CD0 beq .L496 + 8307 003c 2ED8 bhi .L500 + 8308 003e 202B cmp r3, #32 + 8309 0040 2ED0 beq .L501 + 8310 0042 04D8 bhi .L498 + 8311 0044 73B3 cbz r3, .L502 + 8312 0046 102B cmp r3, #16 + 8313 0048 2ED1 bne .L503 + 8314 004a 0020 movs r0, #0 + 8315 .LVL670: +7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8316 .loc 1 7407 3 view .LVU2721 + 8317 004c F3E7 b .L497 + 8318 .LVL671: + 8319 .L498: +7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8320 .loc 1 7407 3 view .LVU2722 + 8321 004e 302B cmp r3, #48 + 8322 0050 2CD1 bne .L504 + 8323 0052 0020 movs r0, #0 + 8324 .LVL672: +7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8325 .loc 1 7407 3 view .LVU2723 + 8326 0054 EFE7 b .L497 + 8327 .LVL673: + 8328 .L496: +7427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + 8329 .loc 1 7427 7 is_stmt 1 view .LVU2724 +7428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8330 .loc 1 7428 7 view .LVU2725 +7430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8331 .loc 1 7430 7 view .LVU2726 +7430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8332 .loc 1 7430 23 is_stmt 0 view .LVU2727 + 8333 0056 0B68 ldr r3, [r1] +7430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8334 .loc 1 7430 10 view .LVU2728 + 8335 0058 052B cmp r3, #5 + 8336 005a 2BD0 beq .L506 +7436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCER &= ~TIM_CCER_CC1E; + 8337 .loc 1 7436 7 is_stmt 1 view .LVU2729 +7436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCER &= ~TIM_CCER_CC1E; + 8338 .loc 1 7436 21 is_stmt 0 view .LVU2730 + ARM GAS /tmp/ccGFzgX3.s page 322 + + + 8339 005c 0368 ldr r3, [r0] +7436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCER &= ~TIM_CCER_CC1E; + 8340 .loc 1 7436 15 view .LVU2731 + 8341 005e 1C6A ldr r4, [r3, #32] + 8342 .LVL674: +7437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 = htim->Instance->CCMR1; + 8343 .loc 1 7437 7 is_stmt 1 view .LVU2732 +7437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 = htim->Instance->CCMR1; + 8344 .loc 1 7437 21 is_stmt 0 view .LVU2733 + 8345 0060 1A6A ldr r2, [r3, #32] +7437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 = htim->Instance->CCMR1; + 8346 .loc 1 7437 28 view .LVU2734 + 8347 0062 22F00102 bic r2, r2, #1 + 8348 0066 1A62 str r2, [r3, #32] +7438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8349 .loc 1 7438 7 is_stmt 1 view .LVU2735 +7438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8350 .loc 1 7438 22 is_stmt 0 view .LVU2736 + 8351 0068 0268 ldr r2, [r0] +7438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8352 .loc 1 7438 16 view .LVU2737 + 8353 006a 9369 ldr r3, [r2, #24] + 8354 .LVL675: +7441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + 8355 .loc 1 7441 7 is_stmt 1 view .LVU2738 +7441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + 8356 .loc 1 7441 16 is_stmt 0 view .LVU2739 + 8357 006c 23F0F003 bic r3, r3, #240 + 8358 .LVL676: +7442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8359 .loc 1 7442 7 is_stmt 1 view .LVU2740 +7442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8360 .loc 1 7442 33 is_stmt 0 view .LVU2741 + 8361 0070 0969 ldr r1, [r1, #16] + 8362 .LVL677: +7442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8363 .loc 1 7442 16 view .LVU2742 + 8364 0072 43EA0113 orr r3, r3, r1, lsl #4 + 8365 .LVL678: +7445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCER = tmpccer; + 8366 .loc 1 7445 7 is_stmt 1 view .LVU2743 +7445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->Instance->CCER = tmpccer; + 8367 .loc 1 7445 29 is_stmt 0 view .LVU2744 + 8368 0076 9361 str r3, [r2, #24] +7446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8369 .loc 1 7446 7 is_stmt 1 view .LVU2745 +7446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8370 .loc 1 7446 11 is_stmt 0 view .LVU2746 + 8371 0078 0368 ldr r3, [r0] + 8372 .LVL679: +7446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8373 .loc 1 7446 28 view .LVU2747 + 8374 007a 1C62 str r4, [r3, #32] + 8375 .LVL680: +7447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8376 .loc 1 7447 7 is_stmt 1 view .LVU2748 +7385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + ARM GAS /tmp/ccGFzgX3.s page 323 + + + 8377 .loc 1 7385 21 is_stmt 0 view .LVU2749 + 8378 007c 0020 movs r0, #0 + 8379 .LVL681: +7447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8380 .loc 1 7447 7 view .LVU2750 + 8381 007e DAE7 b .L497 + 8382 .LVL682: + 8383 .L494: +7453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + 8384 .loc 1 7453 7 is_stmt 1 view .LVU2751 +7454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + 8385 .loc 1 7454 7 view .LVU2752 +7455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8386 .loc 1 7455 7 view .LVU2753 +7458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sSlaveConfig->TriggerPolarity, + 8387 .loc 1 7458 7 view .LVU2754 + 8388 0080 0A69 ldr r2, [r1, #16] + 8389 0082 8968 ldr r1, [r1, #8] + 8390 .LVL683: +7458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sSlaveConfig->TriggerPolarity, + 8391 .loc 1 7458 7 is_stmt 0 view .LVU2755 + 8392 0084 0068 ldr r0, [r0] + 8393 .LVL684: +7458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sSlaveConfig->TriggerPolarity, + 8394 .loc 1 7458 7 view .LVU2756 + 8395 0086 FFF7FEFF bl TIM_TI1_ConfigInputStage + 8396 .LVL685: +7461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8397 .loc 1 7461 7 is_stmt 1 view .LVU2757 +7385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 8398 .loc 1 7385 21 is_stmt 0 view .LVU2758 + 8399 008a 0020 movs r0, #0 +7461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8400 .loc 1 7461 7 view .LVU2759 + 8401 008c D3E7 b .L497 + 8402 .LVL686: + 8403 .L499: +7467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + 8404 .loc 1 7467 7 is_stmt 1 view .LVU2760 +7468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + 8405 .loc 1 7468 7 view .LVU2761 +7469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8406 .loc 1 7469 7 view .LVU2762 +7472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sSlaveConfig->TriggerPolarity, + 8407 .loc 1 7472 7 view .LVU2763 + 8408 008e 0A69 ldr r2, [r1, #16] + 8409 0090 8968 ldr r1, [r1, #8] + 8410 .LVL687: +7472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sSlaveConfig->TriggerPolarity, + 8411 .loc 1 7472 7 is_stmt 0 view .LVU2764 + 8412 0092 0068 ldr r0, [r0] + 8413 .LVL688: +7472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** sSlaveConfig->TriggerPolarity, + 8414 .loc 1 7472 7 view .LVU2765 + 8415 0094 FFF7FEFF bl TIM_TI2_ConfigInputStage + 8416 .LVL689: +7475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + ARM GAS /tmp/ccGFzgX3.s page 324 + + + 8417 .loc 1 7475 7 is_stmt 1 view .LVU2766 +7385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 8418 .loc 1 7385 21 is_stmt 0 view .LVU2767 + 8419 0098 0020 movs r0, #0 +7475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8420 .loc 1 7475 7 view .LVU2768 + 8421 009a CCE7 b .L497 + 8422 .LVL690: + 8423 .L500: +7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8424 .loc 1 7489 14 view .LVU2769 + 8425 009c 0120 movs r0, #1 + 8426 .LVL691: +7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8427 .loc 1 7489 14 view .LVU2770 + 8428 009e CAE7 b .L497 + 8429 .LVL692: + 8430 .L501: +7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8431 .loc 1 7407 3 view .LVU2771 + 8432 00a0 0020 movs r0, #0 + 8433 .LVL693: +7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8434 .loc 1 7407 3 view .LVU2772 + 8435 00a2 C8E7 b .L497 + 8436 .LVL694: + 8437 .L502: +7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8438 .loc 1 7407 3 view .LVU2773 + 8439 00a4 0020 movs r0, #0 + 8440 .LVL695: +7407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8441 .loc 1 7407 3 view .LVU2774 + 8442 00a6 C6E7 b .L497 + 8443 .LVL696: + 8444 .L503: +7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8445 .loc 1 7489 14 view .LVU2775 + 8446 00a8 0120 movs r0, #1 + 8447 .LVL697: +7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8448 .loc 1 7489 14 view .LVU2776 + 8449 00aa C4E7 b .L497 + 8450 .LVL698: + 8451 .L504: +7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8452 .loc 1 7489 14 view .LVU2777 + 8453 00ac 0120 movs r0, #1 + 8454 .LVL699: +7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8455 .loc 1 7489 14 view .LVU2778 + 8456 00ae C2E7 b .L497 + 8457 .LVL700: + 8458 .L505: +7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8459 .loc 1 7489 14 view .LVU2779 + 8460 00b0 0120 movs r0, #1 + ARM GAS /tmp/ccGFzgX3.s page 325 + + + 8461 .LVL701: +7489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 8462 .loc 1 7489 14 view .LVU2780 + 8463 00b2 C0E7 b .L497 + 8464 .LVL702: + 8465 .L506: +7432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8466 .loc 1 7432 16 view .LVU2781 + 8467 00b4 0120 movs r0, #1 + 8468 .LVL703: +7432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8469 .loc 1 7432 16 view .LVU2782 + 8470 00b6 BEE7 b .L497 + 8471 .L510: + 8472 .align 2 + 8473 .L509: + 8474 00b8 F8FFFEFF .word -65544 + 8475 .cfi_endproc + 8476 .LFE252: + 8478 .section .text.HAL_TIM_SlaveConfigSynchro,"ax",%progbits + 8479 .align 1 + 8480 .global HAL_TIM_SlaveConfigSynchro + 8481 .syntax unified + 8482 .thumb + 8483 .thumb_func + 8485 HAL_TIM_SlaveConfigSynchro: + 8486 .LVL704: + 8487 .LFB214: +5633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 8488 .loc 1 5633 1 is_stmt 1 view -0 + 8489 .cfi_startproc + 8490 @ args = 0, pretend = 0, frame = 0 + 8491 @ frame_needed = 0, uses_anonymous_args = 0 +5635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + 8492 .loc 1 5635 3 view .LVU2784 +5636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + 8493 .loc 1 5636 3 view .LVU2785 +5637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8494 .loc 1 5637 3 view .LVU2786 +5639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8495 .loc 1 5639 3 view .LVU2787 +5639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8496 .loc 1 5639 3 view .LVU2788 + 8497 0000 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 8498 0004 012B cmp r3, #1 + 8499 0006 22D0 beq .L514 +5633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 8500 .loc 1 5633 1 is_stmt 0 view .LVU2789 + 8501 0008 10B5 push {r4, lr} + 8502 .LCFI82: + 8503 .cfi_def_cfa_offset 8 + 8504 .cfi_offset 4, -8 + 8505 .cfi_offset 14, -4 + 8506 000a 0446 mov r4, r0 +5639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8507 .loc 1 5639 3 is_stmt 1 discriminator 2 view .LVU2790 + 8508 000c 0123 movs r3, #1 + ARM GAS /tmp/ccGFzgX3.s page 326 + + + 8509 000e 80F83C30 strb r3, [r0, #60] +5639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8510 .loc 1 5639 3 discriminator 2 view .LVU2791 +5641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8511 .loc 1 5641 3 view .LVU2792 +5641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8512 .loc 1 5641 15 is_stmt 0 view .LVU2793 + 8513 0012 0223 movs r3, #2 + 8514 0014 80F83D30 strb r3, [r0, #61] +5643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8515 .loc 1 5643 3 is_stmt 1 view .LVU2794 +5643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8516 .loc 1 5643 7 is_stmt 0 view .LVU2795 + 8517 0018 FFF7FEFF bl TIM_SlaveTimer_SetConfig + 8518 .LVL705: +5643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8519 .loc 1 5643 6 discriminator 1 view .LVU2796 + 8520 001c 80B9 cbnz r0, .L519 +5651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8521 .loc 1 5651 3 is_stmt 1 view .LVU2797 + 8522 001e 2268 ldr r2, [r4] + 8523 0020 D368 ldr r3, [r2, #12] + 8524 0022 23F04003 bic r3, r3, #64 + 8525 0026 D360 str r3, [r2, #12] +5654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8526 .loc 1 5654 3 view .LVU2798 + 8527 0028 2268 ldr r2, [r4] + 8528 002a D368 ldr r3, [r2, #12] + 8529 002c 23F48043 bic r3, r3, #16384 + 8530 0030 D360 str r3, [r2, #12] +5656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8531 .loc 1 5656 3 view .LVU2799 +5656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8532 .loc 1 5656 15 is_stmt 0 view .LVU2800 + 8533 0032 0123 movs r3, #1 + 8534 0034 84F83D30 strb r3, [r4, #61] +5658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8535 .loc 1 5658 3 is_stmt 1 view .LVU2801 +5658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8536 .loc 1 5658 3 view .LVU2802 + 8537 0038 0023 movs r3, #0 + 8538 003a 84F83C30 strb r3, [r4, #60] +5658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8539 .loc 1 5658 3 view .LVU2803 +5660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8540 .loc 1 5660 3 view .LVU2804 + 8541 .L512: +5661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8542 .loc 1 5661 1 is_stmt 0 view .LVU2805 + 8543 003e 10BD pop {r4, pc} + 8544 .LVL706: + 8545 .L519: +5645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); + 8546 .loc 1 5645 5 is_stmt 1 view .LVU2806 +5645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); + 8547 .loc 1 5645 17 is_stmt 0 view .LVU2807 + 8548 0040 0120 movs r0, #1 + ARM GAS /tmp/ccGFzgX3.s page 327 + + + 8549 0042 84F83D00 strb r0, [r4, #61] +5646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + 8550 .loc 1 5646 5 is_stmt 1 view .LVU2808 +5646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + 8551 .loc 1 5646 5 view .LVU2809 + 8552 0046 0023 movs r3, #0 + 8553 0048 84F83C30 strb r3, [r4, #60] +5646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + 8554 .loc 1 5646 5 view .LVU2810 +5647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8555 .loc 1 5647 5 view .LVU2811 +5647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8556 .loc 1 5647 12 is_stmt 0 view .LVU2812 + 8557 004c F7E7 b .L512 + 8558 .LVL707: + 8559 .L514: + 8560 .LCFI83: + 8561 .cfi_def_cfa_offset 0 + 8562 .cfi_restore 4 + 8563 .cfi_restore 14 +5639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8564 .loc 1 5639 3 discriminator 1 view .LVU2813 + 8565 004e 0220 movs r0, #2 + 8566 .LVL708: +5661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8567 .loc 1 5661 1 view .LVU2814 + 8568 0050 7047 bx lr + 8569 .cfi_endproc + 8570 .LFE214: + 8572 .section .text.HAL_TIM_SlaveConfigSynchro_IT,"ax",%progbits + 8573 .align 1 + 8574 .global HAL_TIM_SlaveConfigSynchro_IT + 8575 .syntax unified + 8576 .thumb + 8577 .thumb_func + 8579 HAL_TIM_SlaveConfigSynchro_IT: + 8580 .LVL709: + 8581 .LFB215: +5674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 8582 .loc 1 5674 1 is_stmt 1 view -0 + 8583 .cfi_startproc + 8584 @ args = 0, pretend = 0, frame = 0 + 8585 @ frame_needed = 0, uses_anonymous_args = 0 +5676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + 8586 .loc 1 5676 3 view .LVU2816 +5677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + 8587 .loc 1 5677 3 view .LVU2817 +5678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8588 .loc 1 5678 3 view .LVU2818 +5680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8589 .loc 1 5680 3 view .LVU2819 +5680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8590 .loc 1 5680 3 view .LVU2820 + 8591 0000 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 8592 0004 012B cmp r3, #1 + 8593 0006 22D0 beq .L523 +5674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + ARM GAS /tmp/ccGFzgX3.s page 328 + + + 8594 .loc 1 5674 1 is_stmt 0 view .LVU2821 + 8595 0008 10B5 push {r4, lr} + 8596 .LCFI84: + 8597 .cfi_def_cfa_offset 8 + 8598 .cfi_offset 4, -8 + 8599 .cfi_offset 14, -4 + 8600 000a 0446 mov r4, r0 +5680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8601 .loc 1 5680 3 is_stmt 1 discriminator 2 view .LVU2822 + 8602 000c 0123 movs r3, #1 + 8603 000e 80F83C30 strb r3, [r0, #60] +5680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8604 .loc 1 5680 3 discriminator 2 view .LVU2823 +5682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8605 .loc 1 5682 3 view .LVU2824 +5682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8606 .loc 1 5682 15 is_stmt 0 view .LVU2825 + 8607 0012 0223 movs r3, #2 + 8608 0014 80F83D30 strb r3, [r0, #61] +5684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8609 .loc 1 5684 3 is_stmt 1 view .LVU2826 +5684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8610 .loc 1 5684 7 is_stmt 0 view .LVU2827 + 8611 0018 FFF7FEFF bl TIM_SlaveTimer_SetConfig + 8612 .LVL710: +5684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8613 .loc 1 5684 6 discriminator 1 view .LVU2828 + 8614 001c 80B9 cbnz r0, .L528 +5692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8615 .loc 1 5692 3 is_stmt 1 view .LVU2829 + 8616 001e 2268 ldr r2, [r4] + 8617 0020 D368 ldr r3, [r2, #12] + 8618 0022 43F04003 orr r3, r3, #64 + 8619 0026 D360 str r3, [r2, #12] +5695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8620 .loc 1 5695 3 view .LVU2830 + 8621 0028 2268 ldr r2, [r4] + 8622 002a D368 ldr r3, [r2, #12] + 8623 002c 23F48043 bic r3, r3, #16384 + 8624 0030 D360 str r3, [r2, #12] +5697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8625 .loc 1 5697 3 view .LVU2831 +5697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8626 .loc 1 5697 15 is_stmt 0 view .LVU2832 + 8627 0032 0123 movs r3, #1 + 8628 0034 84F83D30 strb r3, [r4, #61] +5699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8629 .loc 1 5699 3 is_stmt 1 view .LVU2833 +5699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8630 .loc 1 5699 3 view .LVU2834 + 8631 0038 0023 movs r3, #0 + 8632 003a 84F83C30 strb r3, [r4, #60] +5699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8633 .loc 1 5699 3 view .LVU2835 +5701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8634 .loc 1 5701 3 view .LVU2836 + 8635 .L521: + ARM GAS /tmp/ccGFzgX3.s page 329 + + +5702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8636 .loc 1 5702 1 is_stmt 0 view .LVU2837 + 8637 003e 10BD pop {r4, pc} + 8638 .LVL711: + 8639 .L528: +5686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); + 8640 .loc 1 5686 5 is_stmt 1 view .LVU2838 +5686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_UNLOCK(htim); + 8641 .loc 1 5686 17 is_stmt 0 view .LVU2839 + 8642 0040 0120 movs r0, #1 + 8643 0042 84F83D00 strb r0, [r4, #61] +5687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + 8644 .loc 1 5687 5 is_stmt 1 view .LVU2840 +5687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + 8645 .loc 1 5687 5 view .LVU2841 + 8646 0046 0023 movs r3, #0 + 8647 0048 84F83C30 strb r3, [r4, #60] +5687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** return HAL_ERROR; + 8648 .loc 1 5687 5 view .LVU2842 +5688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8649 .loc 1 5688 5 view .LVU2843 +5688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8650 .loc 1 5688 12 is_stmt 0 view .LVU2844 + 8651 004c F7E7 b .L521 + 8652 .LVL712: + 8653 .L523: + 8654 .LCFI85: + 8655 .cfi_def_cfa_offset 0 + 8656 .cfi_restore 4 + 8657 .cfi_restore 14 +5680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8658 .loc 1 5680 3 discriminator 1 view .LVU2845 + 8659 004e 0220 movs r0, #2 + 8660 .LVL713: +5702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8661 .loc 1 5702 1 view .LVU2846 + 8662 0050 7047 bx lr + 8663 .cfi_endproc + 8664 .LFE215: + 8666 .section .text.TIM_CCxChannelCmd,"ax",%progbits + 8667 .align 1 + 8668 .global TIM_CCxChannelCmd + 8669 .syntax unified + 8670 .thumb + 8671 .thumb_func + 8673 TIM_CCxChannelCmd: + 8674 .LVL714: + 8675 .LFB261: +7826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** +7828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @brief Enables or disables the TIM Capture Compare Channel x. +7829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param Channel specifies the TIM Channel +7831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be one of the following values: +7832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 +7833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 +7834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 + ARM GAS /tmp/ccGFzgX3.s page 330 + + +7835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 +7836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_5: TIM Channel 5 selected +7837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @arg TIM_CHANNEL_6: TIM Channel 6 selected +7838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @param ChannelState specifies the TIM Channel CCxE bit new state. +7839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. +7840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** * @retval None +7841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** */ +7842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +7843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8676 .loc 1 7843 1 is_stmt 1 view -0 + 8677 .cfi_startproc + 8678 @ args = 0, pretend = 0, frame = 0 + 8679 @ frame_needed = 0, uses_anonymous_args = 0 + 8680 @ link register save eliminated. +7844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmp; + 8681 .loc 1 7844 3 view .LVU2848 +7845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ +7847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + 8682 .loc 1 7847 3 view .LVU2849 +7848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_CHANNELS(Channel)); + 8683 .loc 1 7848 3 view .LVU2850 +7849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + 8684 .loc 1 7850 3 view .LVU2851 + 8685 .loc 1 7850 35 is_stmt 0 view .LVU2852 + 8686 0000 01F01F01 and r1, r1, #31 + 8687 .LVL715: + 8688 .loc 1 7850 7 view .LVU2853 + 8689 0004 4FF0010C mov ip, #1 + 8690 0008 0CFA01FC lsl ip, ip, r1 + 8691 .LVL716: +7851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Reset the CCxE Bit */ +7853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER &= ~tmp; + 8692 .loc 1 7853 3 is_stmt 1 view .LVU2854 + 8693 .loc 1 7853 7 is_stmt 0 view .LVU2855 + 8694 000c 036A ldr r3, [r0, #32] + 8695 .loc 1 7853 14 view .LVU2856 + 8696 000e 23EA0C03 bic r3, r3, ip + 8697 0012 0362 str r3, [r0, #32] +7854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** +7855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Set or reset the CCxE Bit */ +7856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + 8698 .loc 1 7856 3 is_stmt 1 view .LVU2857 + 8699 .loc 1 7856 7 is_stmt 0 view .LVU2858 + 8700 0014 036A ldr r3, [r0, #32] + 8701 .loc 1 7856 41 view .LVU2859 + 8702 0016 8A40 lsls r2, r2, r1 + 8703 .LVL717: + 8704 .loc 1 7856 14 view .LVU2860 + 8705 0018 1343 orrs r3, r3, r2 + 8706 001a 0362 str r3, [r0, #32] +7857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8707 .loc 1 7857 1 view .LVU2861 + 8708 001c 7047 bx lr + 8709 .cfi_endproc + ARM GAS /tmp/ccGFzgX3.s page 331 + + + 8710 .LFE261: + 8712 .section .text.HAL_TIM_OC_Start,"ax",%progbits + 8713 .align 1 + 8714 .global HAL_TIM_OC_Start + 8715 .syntax unified + 8716 .thumb + 8717 .thumb_func + 8719 HAL_TIM_OC_Start: + 8720 .LVL718: + 8721 .LFB155: + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 8722 .loc 1 795 1 is_stmt 1 view -0 + 8723 .cfi_startproc + 8724 @ args = 0, pretend = 0, frame = 0 + 8725 @ frame_needed = 0, uses_anonymous_args = 0 + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 8726 .loc 1 795 1 is_stmt 0 view .LVU2863 + 8727 0000 10B5 push {r4, lr} + 8728 .LCFI86: + 8729 .cfi_def_cfa_offset 8 + 8730 .cfi_offset 4, -8 + 8731 .cfi_offset 14, -4 + 8732 0002 0446 mov r4, r0 + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8733 .loc 1 796 3 is_stmt 1 view .LVU2864 + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8734 .loc 1 799 3 view .LVU2865 + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8735 .loc 1 802 3 view .LVU2866 + 8736 0004 1029 cmp r1, #16 + 8737 0006 3CD8 bhi .L531 + 8738 0008 DFE801F0 tbb [pc, r1] + 8739 .L533: + 8740 000c 09 .byte (.L537-.L533)/2 + 8741 000d 3B .byte (.L531-.L533)/2 + 8742 000e 3B .byte (.L531-.L533)/2 + 8743 000f 3B .byte (.L531-.L533)/2 + 8744 0010 1F .byte (.L536-.L533)/2 + 8745 0011 3B .byte (.L531-.L533)/2 + 8746 0012 3B .byte (.L531-.L533)/2 + 8747 0013 3B .byte (.L531-.L533)/2 + 8748 0014 26 .byte (.L535-.L533)/2 + 8749 0015 3B .byte (.L531-.L533)/2 + 8750 0016 3B .byte (.L531-.L533)/2 + 8751 0017 3B .byte (.L531-.L533)/2 + 8752 0018 2D .byte (.L534-.L533)/2 + 8753 0019 3B .byte (.L531-.L533)/2 + 8754 001a 3B .byte (.L531-.L533)/2 + 8755 001b 3B .byte (.L531-.L533)/2 + 8756 001c 34 .byte (.L532-.L533)/2 + 8757 001d 00 .p2align 1 + 8758 .L537: + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8759 .loc 1 802 7 is_stmt 0 discriminator 1 view .LVU2867 + 8760 001e 90F83E30 ldrb r3, [r0, #62] @ zero_extendqisi2 + 8761 0022 DBB2 uxtb r3, r3 + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 332 + + + 8762 .loc 1 802 44 discriminator 1 view .LVU2868 + 8763 0024 013B subs r3, r3, #1 + 8764 0026 18BF it ne + 8765 0028 0123 movne r3, #1 + 8766 .L538: + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8767 .loc 1 802 6 discriminator 20 view .LVU2869 + 8768 002a 002B cmp r3, #0 + 8769 002c 40F08980 bne .L551 + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8770 .loc 1 808 3 is_stmt 1 view .LVU2870 + 8771 0030 1029 cmp r1, #16 + 8772 0032 74D8 bhi .L540 + 8773 0034 DFE801F0 tbb [pc, r1] + 8774 .L542: + 8775 0038 2C .byte (.L546-.L542)/2 + 8776 0039 73 .byte (.L540-.L542)/2 + 8777 003a 73 .byte (.L540-.L542)/2 + 8778 003b 73 .byte (.L540-.L542)/2 + 8779 003c 63 .byte (.L545-.L542)/2 + 8780 003d 73 .byte (.L540-.L542)/2 + 8781 003e 73 .byte (.L540-.L542)/2 + 8782 003f 73 .byte (.L540-.L542)/2 + 8783 0040 67 .byte (.L544-.L542)/2 + 8784 0041 73 .byte (.L540-.L542)/2 + 8785 0042 73 .byte (.L540-.L542)/2 + 8786 0043 73 .byte (.L540-.L542)/2 + 8787 0044 6B .byte (.L543-.L542)/2 + 8788 0045 73 .byte (.L540-.L542)/2 + 8789 0046 73 .byte (.L540-.L542)/2 + 8790 0047 73 .byte (.L540-.L542)/2 + 8791 0048 6F .byte (.L541-.L542)/2 + 8792 0049 00 .p2align 1 + 8793 .L536: + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8794 .loc 1 802 7 is_stmt 0 discriminator 4 view .LVU2871 + 8795 004a 90F83F30 ldrb r3, [r0, #63] @ zero_extendqisi2 + 8796 004e DBB2 uxtb r3, r3 + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8797 .loc 1 802 44 discriminator 4 view .LVU2872 + 8798 0050 013B subs r3, r3, #1 + 8799 0052 18BF it ne + 8800 0054 0123 movne r3, #1 + 8801 0056 E8E7 b .L538 + 8802 .L535: + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8803 .loc 1 802 7 discriminator 7 view .LVU2873 + 8804 0058 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 8805 005c DBB2 uxtb r3, r3 + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8806 .loc 1 802 44 discriminator 7 view .LVU2874 + 8807 005e 013B subs r3, r3, #1 + 8808 0060 18BF it ne + 8809 0062 0123 movne r3, #1 + 8810 0064 E1E7 b .L538 + 8811 .L534: + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 333 + + + 8812 .loc 1 802 7 discriminator 10 view .LVU2875 + 8813 0066 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 8814 006a DBB2 uxtb r3, r3 + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8815 .loc 1 802 44 discriminator 10 view .LVU2876 + 8816 006c 013B subs r3, r3, #1 + 8817 006e 18BF it ne + 8818 0070 0123 movne r3, #1 + 8819 0072 DAE7 b .L538 + 8820 .L532: + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8821 .loc 1 802 7 discriminator 13 view .LVU2877 + 8822 0074 90F84230 ldrb r3, [r0, #66] @ zero_extendqisi2 + 8823 0078 DBB2 uxtb r3, r3 + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8824 .loc 1 802 44 discriminator 13 view .LVU2878 + 8825 007a 013B subs r3, r3, #1 + 8826 007c 18BF it ne + 8827 007e 0123 movne r3, #1 + 8828 0080 D3E7 b .L538 + 8829 .L531: + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8830 .loc 1 802 7 discriminator 14 view .LVU2879 + 8831 0082 90F84330 ldrb r3, [r0, #67] @ zero_extendqisi2 + 8832 0086 DBB2 uxtb r3, r3 + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8833 .loc 1 802 44 discriminator 14 view .LVU2880 + 8834 0088 013B subs r3, r3, #1 + 8835 008a 18BF it ne + 8836 008c 0123 movne r3, #1 + 8837 008e CCE7 b .L538 + 8838 .L546: + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8839 .loc 1 808 3 discriminator 1 view .LVU2881 + 8840 0090 0223 movs r3, #2 + 8841 0092 84F83E30 strb r3, [r4, #62] + 8842 .L547: + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8843 .loc 1 811 3 is_stmt 1 view .LVU2882 + 8844 0096 0122 movs r2, #1 + 8845 0098 2068 ldr r0, [r4] + 8846 .LVL719: + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8847 .loc 1 811 3 is_stmt 0 view .LVU2883 + 8848 009a FFF7FEFF bl TIM_CCxChannelCmd + 8849 .LVL720: + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8850 .loc 1 813 3 is_stmt 1 view .LVU2884 + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8851 .loc 1 813 7 is_stmt 0 view .LVU2885 + 8852 009e 2368 ldr r3, [r4] + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8853 .loc 1 813 6 view .LVU2886 + 8854 00a0 2A49 ldr r1, .L554 + 8855 00a2 2B4A ldr r2, .L554+4 + 8856 00a4 9342 cmp r3, r2 + 8857 00a6 18BF it ne + ARM GAS /tmp/ccGFzgX3.s page 334 + + + 8858 00a8 8B42 cmpne r3, r1 + 8859 00aa 03D1 bne .L548 + 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8860 .loc 1 816 5 is_stmt 1 view .LVU2887 + 8861 00ac 5A6C ldr r2, [r3, #68] + 8862 00ae 42F40042 orr r2, r2, #32768 + 8863 00b2 5A64 str r2, [r3, #68] + 8864 .L548: + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8865 .loc 1 820 3 view .LVU2888 + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8866 .loc 1 820 7 is_stmt 0 view .LVU2889 + 8867 00b4 2368 ldr r3, [r4] + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8868 .loc 1 820 6 view .LVU2890 + 8869 00b6 254A ldr r2, .L554 + 8870 00b8 B3F1804F cmp r3, #1073741824 + 8871 00bc 18BF it ne + 8872 00be 9342 cmpne r3, r2 + 8873 00c0 31D0 beq .L549 + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8874 .loc 1 820 7 discriminator 1 view .LVU2891 + 8875 00c2 A2F57C42 sub r2, r2, #64512 + 8876 00c6 9342 cmp r3, r2 + 8877 00c8 2DD0 beq .L549 + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8878 .loc 1 820 7 discriminator 2 view .LVU2892 + 8879 00ca 02F58062 add r2, r2, #1024 + 8880 00ce 9342 cmp r3, r2 + 8881 00d0 29D0 beq .L549 + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8882 .loc 1 820 7 discriminator 3 view .LVU2893 + 8883 00d2 02F58062 add r2, r2, #1024 + 8884 00d6 9342 cmp r3, r2 + 8885 00d8 25D0 beq .L549 + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8886 .loc 1 820 7 discriminator 4 view .LVU2894 + 8887 00da 02F57842 add r2, r2, #63488 + 8888 00de 9342 cmp r3, r2 + 8889 00e0 21D0 beq .L549 + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8890 .loc 1 820 7 discriminator 5 view .LVU2895 + 8891 00e2 02F57052 add r2, r2, #15360 + 8892 00e6 9342 cmp r3, r2 + 8893 00e8 1DD0 beq .L549 + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8894 .loc 1 820 7 discriminator 6 view .LVU2896 + 8895 00ea A2F59432 sub r2, r2, #75776 + 8896 00ee 9342 cmp r3, r2 + 8897 00f0 19D0 beq .L549 + 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8898 .loc 1 830 5 is_stmt 1 view .LVU2897 + 8899 00f2 1A68 ldr r2, [r3] + 8900 00f4 42F00102 orr r2, r2, #1 + 8901 00f8 1A60 str r2, [r3] + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8902 .loc 1 834 10 is_stmt 0 view .LVU2898 + ARM GAS /tmp/ccGFzgX3.s page 335 + + + 8903 00fa 0020 movs r0, #0 + 8904 00fc 22E0 b .L539 + 8905 .LVL721: + 8906 .L545: + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8907 .loc 1 808 3 discriminator 3 view .LVU2899 + 8908 00fe 0223 movs r3, #2 + 8909 0100 84F83F30 strb r3, [r4, #63] + 8910 0104 C7E7 b .L547 + 8911 .L544: + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8912 .loc 1 808 3 discriminator 6 view .LVU2900 + 8913 0106 0223 movs r3, #2 + 8914 0108 84F84030 strb r3, [r4, #64] + 8915 010c C3E7 b .L547 + 8916 .L543: + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8917 .loc 1 808 3 discriminator 9 view .LVU2901 + 8918 010e 0223 movs r3, #2 + 8919 0110 84F84130 strb r3, [r4, #65] + 8920 0114 BFE7 b .L547 + 8921 .L541: + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8922 .loc 1 808 3 discriminator 12 view .LVU2902 + 8923 0116 0223 movs r3, #2 + 8924 0118 84F84230 strb r3, [r4, #66] + 8925 011c BBE7 b .L547 + 8926 .L540: + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8927 .loc 1 808 3 discriminator 13 view .LVU2903 + 8928 011e 0223 movs r3, #2 + 8929 0120 84F84330 strb r3, [r4, #67] + 8930 0124 B7E7 b .L547 + 8931 .LVL722: + 8932 .L549: + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8933 .loc 1 822 5 is_stmt 1 view .LVU2904 + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8934 .loc 1 822 29 is_stmt 0 view .LVU2905 + 8935 0126 9968 ldr r1, [r3, #8] + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 8936 .loc 1 822 13 view .LVU2906 + 8937 0128 0A4A ldr r2, .L554+8 + 8938 012a 0A40 ands r2, r2, r1 + 8939 .LVL723: + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8940 .loc 1 823 5 is_stmt 1 view .LVU2907 + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 8941 .loc 1 823 8 is_stmt 0 view .LVU2908 + 8942 012c 062A cmp r2, #6 + 8943 012e 18BF it ne + 8944 0130 B2F5803F cmpne r2, #65536 + 8945 0134 07D0 beq .L552 + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8946 .loc 1 825 7 is_stmt 1 view .LVU2909 + 8947 0136 1A68 ldr r2, [r3] + 8948 .LVL724: + ARM GAS /tmp/ccGFzgX3.s page 336 + + + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8949 .loc 1 825 7 is_stmt 0 view .LVU2910 + 8950 0138 42F00102 orr r2, r2, #1 + 8951 013c 1A60 str r2, [r3] + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8952 .loc 1 834 10 view .LVU2911 + 8953 013e 0020 movs r0, #0 + 8954 0140 00E0 b .L539 + 8955 .LVL725: + 8956 .L551: + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8957 .loc 1 804 12 view .LVU2912 + 8958 0142 0120 movs r0, #1 + 8959 .LVL726: + 8960 .L539: + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 8961 .loc 1 835 1 view .LVU2913 + 8962 0144 10BD pop {r4, pc} + 8963 .LVL727: + 8964 .L552: + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 8965 .loc 1 834 10 view .LVU2914 + 8966 0146 0020 movs r0, #0 + 8967 0148 FCE7 b .L539 + 8968 .L555: + 8969 014a 00BF .align 2 + 8970 .L554: + 8971 014c 00000140 .word 1073807360 + 8972 0150 00040140 .word 1073808384 + 8973 0154 07000100 .word 65543 + 8974 .cfi_endproc + 8975 .LFE155: + 8977 .section .text.HAL_TIM_OC_Stop,"ax",%progbits + 8978 .align 1 + 8979 .global HAL_TIM_OC_Stop + 8980 .syntax unified + 8981 .thumb + 8982 .thumb_func + 8984 HAL_TIM_OC_Stop: + 8985 .LVL728: + 8986 .LFB156: + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 8987 .loc 1 851 1 is_stmt 1 view -0 + 8988 .cfi_startproc + 8989 @ args = 0, pretend = 0, frame = 0 + 8990 @ frame_needed = 0, uses_anonymous_args = 0 + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 8991 .loc 1 851 1 is_stmt 0 view .LVU2916 + 8992 0000 38B5 push {r3, r4, r5, lr} + 8993 .LCFI87: + 8994 .cfi_def_cfa_offset 16 + 8995 .cfi_offset 3, -16 + 8996 .cfi_offset 4, -12 + 8997 .cfi_offset 5, -8 + 8998 .cfi_offset 14, -4 + 8999 0002 0446 mov r4, r0 + 9000 0004 0D46 mov r5, r1 + ARM GAS /tmp/ccGFzgX3.s page 337 + + + 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9001 .loc 1 853 3 is_stmt 1 view .LVU2917 + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9002 .loc 1 856 3 view .LVU2918 + 9003 0006 0022 movs r2, #0 + 9004 0008 0068 ldr r0, [r0] + 9005 .LVL729: + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9006 .loc 1 856 3 is_stmt 0 view .LVU2919 + 9007 000a FFF7FEFF bl TIM_CCxChannelCmd + 9008 .LVL730: + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9009 .loc 1 858 3 is_stmt 1 view .LVU2920 + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9010 .loc 1 858 7 is_stmt 0 view .LVU2921 + 9011 000e 2368 ldr r3, [r4] + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9012 .loc 1 858 6 view .LVU2922 + 9013 0010 2449 ldr r1, .L568 + 9014 0012 254A ldr r2, .L568+4 + 9015 0014 9342 cmp r3, r2 + 9016 0016 18BF it ne + 9017 0018 8B42 cmpne r3, r1 + 9018 001a 0DD1 bne .L557 + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9019 .loc 1 861 5 is_stmt 1 view .LVU2923 + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9020 .loc 1 861 5 view .LVU2924 + 9021 001c 196A ldr r1, [r3, #32] + 9022 001e 41F21112 movw r2, #4369 + 9023 0022 1142 tst r1, r2 + 9024 0024 08D1 bne .L557 + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9025 .loc 1 861 5 discriminator 1 view .LVU2925 + 9026 0026 196A ldr r1, [r3, #32] + 9027 0028 40F24442 movw r2, #1092 + 9028 002c 1142 tst r1, r2 + 9029 002e 03D1 bne .L557 + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9030 .loc 1 861 5 discriminator 3 view .LVU2926 + 9031 0030 5A6C ldr r2, [r3, #68] + 9032 0032 22F40042 bic r2, r2, #32768 + 9033 0036 5A64 str r2, [r3, #68] + 9034 .L557: + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9035 .loc 1 861 5 discriminator 5 view .LVU2927 + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9036 .loc 1 865 3 view .LVU2928 + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9037 .loc 1 865 3 view .LVU2929 + 9038 0038 2368 ldr r3, [r4] + 9039 003a 196A ldr r1, [r3, #32] + 9040 003c 41F21112 movw r2, #4369 + 9041 0040 1142 tst r1, r2 + 9042 0042 08D1 bne .L558 + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9043 .loc 1 865 3 discriminator 1 view .LVU2930 + ARM GAS /tmp/ccGFzgX3.s page 338 + + + 9044 0044 196A ldr r1, [r3, #32] + 9045 0046 40F24442 movw r2, #1092 + 9046 004a 1142 tst r1, r2 + 9047 004c 03D1 bne .L558 + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9048 .loc 1 865 3 discriminator 3 view .LVU2931 + 9049 004e 1A68 ldr r2, [r3] + 9050 0050 22F00102 bic r2, r2, #1 + 9051 0054 1A60 str r2, [r3] + 9052 .L558: + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9053 .loc 1 865 3 discriminator 5 view .LVU2932 + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9054 .loc 1 868 3 view .LVU2933 + 9055 0056 102D cmp r5, #16 + 9056 0058 1FD8 bhi .L559 + 9057 005a DFE805F0 tbb [pc, r5] + 9058 .L561: + 9059 005e 09 .byte (.L565-.L561)/2 + 9060 005f 1E .byte (.L559-.L561)/2 + 9061 0060 1E .byte (.L559-.L561)/2 + 9062 0061 1E .byte (.L559-.L561)/2 + 9063 0062 0E .byte (.L564-.L561)/2 + 9064 0063 1E .byte (.L559-.L561)/2 + 9065 0064 1E .byte (.L559-.L561)/2 + 9066 0065 1E .byte (.L559-.L561)/2 + 9067 0066 12 .byte (.L563-.L561)/2 + 9068 0067 1E .byte (.L559-.L561)/2 + 9069 0068 1E .byte (.L559-.L561)/2 + 9070 0069 1E .byte (.L559-.L561)/2 + 9071 006a 16 .byte (.L562-.L561)/2 + 9072 006b 1E .byte (.L559-.L561)/2 + 9073 006c 1E .byte (.L559-.L561)/2 + 9074 006d 1E .byte (.L559-.L561)/2 + 9075 006e 1A .byte (.L560-.L561)/2 + 9076 006f 00 .p2align 1 + 9077 .L565: + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9078 .loc 1 868 3 is_stmt 0 discriminator 1 view .LVU2934 + 9079 0070 0123 movs r3, #1 + 9080 0072 84F83E30 strb r3, [r4, #62] + 9081 .L566: + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9082 .loc 1 871 3 is_stmt 1 view .LVU2935 + 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9083 .loc 1 872 1 is_stmt 0 view .LVU2936 + 9084 0076 0020 movs r0, #0 + 9085 0078 38BD pop {r3, r4, r5, pc} + 9086 .LVL731: + 9087 .L564: + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9088 .loc 1 868 3 discriminator 3 view .LVU2937 + 9089 007a 0123 movs r3, #1 + 9090 007c 84F83F30 strb r3, [r4, #63] + 9091 0080 F9E7 b .L566 + 9092 .L563: + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 339 + + + 9093 .loc 1 868 3 discriminator 6 view .LVU2938 + 9094 0082 0123 movs r3, #1 + 9095 0084 84F84030 strb r3, [r4, #64] + 9096 0088 F5E7 b .L566 + 9097 .L562: + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9098 .loc 1 868 3 discriminator 9 view .LVU2939 + 9099 008a 0123 movs r3, #1 + 9100 008c 84F84130 strb r3, [r4, #65] + 9101 0090 F1E7 b .L566 + 9102 .L560: + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9103 .loc 1 868 3 discriminator 12 view .LVU2940 + 9104 0092 0123 movs r3, #1 + 9105 0094 84F84230 strb r3, [r4, #66] + 9106 0098 EDE7 b .L566 + 9107 .L559: + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9108 .loc 1 868 3 discriminator 13 view .LVU2941 + 9109 009a 0123 movs r3, #1 + 9110 009c 84F84330 strb r3, [r4, #67] + 9111 00a0 E9E7 b .L566 + 9112 .L569: + 9113 00a2 00BF .align 2 + 9114 .L568: + 9115 00a4 00000140 .word 1073807360 + 9116 00a8 00040140 .word 1073808384 + 9117 .cfi_endproc + 9118 .LFE156: + 9120 .section .text.HAL_TIM_OC_Start_IT,"ax",%progbits + 9121 .align 1 + 9122 .global HAL_TIM_OC_Start_IT + 9123 .syntax unified + 9124 .thumb + 9125 .thumb_func + 9127 HAL_TIM_OC_Start_IT: + 9128 .LVL732: + 9129 .LFB157: + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 9130 .loc 1 886 1 is_stmt 1 view -0 + 9131 .cfi_startproc + 9132 @ args = 0, pretend = 0, frame = 0 + 9133 @ frame_needed = 0, uses_anonymous_args = 0 + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 9134 .loc 1 886 1 is_stmt 0 view .LVU2943 + 9135 0000 10B5 push {r4, lr} + 9136 .LCFI88: + 9137 .cfi_def_cfa_offset 8 + 9138 .cfi_offset 4, -8 + 9139 .cfi_offset 14, -4 + 9140 0002 0446 mov r4, r0 + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 9141 .loc 1 887 3 is_stmt 1 view .LVU2944 + 9142 .LVL733: + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9143 .loc 1 888 3 view .LVU2945 + 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 340 + + + 9144 .loc 1 891 3 view .LVU2946 + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9145 .loc 1 894 3 view .LVU2947 + 9146 0004 1029 cmp r1, #16 + 9147 0006 3DD8 bhi .L571 + 9148 0008 DFE801F0 tbb [pc, r1] + 9149 .L573: + 9150 000c 09 .byte (.L577-.L573)/2 + 9151 000d 3C .byte (.L571-.L573)/2 + 9152 000e 3C .byte (.L571-.L573)/2 + 9153 000f 3C .byte (.L571-.L573)/2 + 9154 0010 20 .byte (.L576-.L573)/2 + 9155 0011 3C .byte (.L571-.L573)/2 + 9156 0012 3C .byte (.L571-.L573)/2 + 9157 0013 3C .byte (.L571-.L573)/2 + 9158 0014 27 .byte (.L575-.L573)/2 + 9159 0015 3C .byte (.L571-.L573)/2 + 9160 0016 3C .byte (.L571-.L573)/2 + 9161 0017 3C .byte (.L571-.L573)/2 + 9162 0018 2E .byte (.L574-.L573)/2 + 9163 0019 3C .byte (.L571-.L573)/2 + 9164 001a 3C .byte (.L571-.L573)/2 + 9165 001b 3C .byte (.L571-.L573)/2 + 9166 001c 35 .byte (.L572-.L573)/2 + 9167 001d 00 .p2align 1 + 9168 .L577: + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9169 .loc 1 894 7 is_stmt 0 discriminator 1 view .LVU2948 + 9170 001e 90F83E30 ldrb r3, [r0, #62] @ zero_extendqisi2 + 9171 0022 DBB2 uxtb r3, r3 + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9172 .loc 1 894 44 discriminator 1 view .LVU2949 + 9173 0024 013B subs r3, r3, #1 + 9174 0026 18BF it ne + 9175 0028 0123 movne r3, #1 + 9176 .L578: + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9177 .loc 1 894 6 discriminator 20 view .LVU2950 + 9178 002a 002B cmp r3, #0 + 9179 002c 40F0BE80 bne .L596 + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9180 .loc 1 900 3 is_stmt 1 view .LVU2951 + 9181 0030 1029 cmp r1, #16 + 9182 0032 00F28A80 bhi .L580 + 9183 0036 DFE801F0 tbb [pc, r1] + 9184 .L582: + 9185 003a 2C .byte (.L586-.L582)/2 + 9186 003b 88 .byte (.L580-.L582)/2 + 9187 003c 88 .byte (.L580-.L582)/2 + 9188 003d 88 .byte (.L580-.L582)/2 + 9189 003e 68 .byte (.L585-.L582)/2 + 9190 003f 88 .byte (.L580-.L582)/2 + 9191 0040 88 .byte (.L580-.L582)/2 + 9192 0041 88 .byte (.L580-.L582)/2 + 9193 0042 71 .byte (.L584-.L582)/2 + 9194 0043 88 .byte (.L580-.L582)/2 + 9195 0044 88 .byte (.L580-.L582)/2 + ARM GAS /tmp/ccGFzgX3.s page 341 + + + 9196 0045 88 .byte (.L580-.L582)/2 + 9197 0046 7A .byte (.L583-.L582)/2 + 9198 0047 88 .byte (.L580-.L582)/2 + 9199 0048 88 .byte (.L580-.L582)/2 + 9200 0049 88 .byte (.L580-.L582)/2 + 9201 004a 83 .byte (.L581-.L582)/2 + 9202 004b 00 .p2align 1 + 9203 .L576: + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9204 .loc 1 894 7 is_stmt 0 discriminator 4 view .LVU2952 + 9205 004c 90F83F30 ldrb r3, [r0, #63] @ zero_extendqisi2 + 9206 0050 DBB2 uxtb r3, r3 + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9207 .loc 1 894 44 discriminator 4 view .LVU2953 + 9208 0052 013B subs r3, r3, #1 + 9209 0054 18BF it ne + 9210 0056 0123 movne r3, #1 + 9211 0058 E7E7 b .L578 + 9212 .L575: + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9213 .loc 1 894 7 discriminator 7 view .LVU2954 + 9214 005a 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 9215 005e DBB2 uxtb r3, r3 + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9216 .loc 1 894 44 discriminator 7 view .LVU2955 + 9217 0060 013B subs r3, r3, #1 + 9218 0062 18BF it ne + 9219 0064 0123 movne r3, #1 + 9220 0066 E0E7 b .L578 + 9221 .L574: + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9222 .loc 1 894 7 discriminator 10 view .LVU2956 + 9223 0068 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 9224 006c DBB2 uxtb r3, r3 + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9225 .loc 1 894 44 discriminator 10 view .LVU2957 + 9226 006e 013B subs r3, r3, #1 + 9227 0070 18BF it ne + 9228 0072 0123 movne r3, #1 + 9229 0074 D9E7 b .L578 + 9230 .L572: + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9231 .loc 1 894 7 discriminator 13 view .LVU2958 + 9232 0076 90F84230 ldrb r3, [r0, #66] @ zero_extendqisi2 + 9233 007a DBB2 uxtb r3, r3 + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9234 .loc 1 894 44 discriminator 13 view .LVU2959 + 9235 007c 013B subs r3, r3, #1 + 9236 007e 18BF it ne + 9237 0080 0123 movne r3, #1 + 9238 0082 D2E7 b .L578 + 9239 .L571: + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9240 .loc 1 894 7 discriminator 14 view .LVU2960 + 9241 0084 90F84330 ldrb r3, [r0, #67] @ zero_extendqisi2 + 9242 0088 DBB2 uxtb r3, r3 + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 342 + + + 9243 .loc 1 894 44 discriminator 14 view .LVU2961 + 9244 008a 013B subs r3, r3, #1 + 9245 008c 18BF it ne + 9246 008e 0123 movne r3, #1 + 9247 0090 CBE7 b .L578 + 9248 .L586: + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9249 .loc 1 900 3 discriminator 1 view .LVU2962 + 9250 0092 0223 movs r3, #2 + 9251 0094 84F83E30 strb r3, [r4, #62] + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9252 .loc 1 902 3 is_stmt 1 view .LVU2963 + 9253 .L587: + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 9254 .loc 1 907 7 view .LVU2964 + 9255 0098 2268 ldr r2, [r4] + 9256 009a D368 ldr r3, [r2, #12] + 9257 009c 43F00203 orr r3, r3, #2 + 9258 00a0 D360 str r3, [r2, #12] + 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9259 .loc 1 908 7 view .LVU2965 + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9260 .loc 1 937 3 view .LVU2966 + 9261 .L592: + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9262 .loc 1 940 5 view .LVU2967 + 9263 00a2 0122 movs r2, #1 + 9264 00a4 2068 ldr r0, [r4] + 9265 .LVL734: + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9266 .loc 1 940 5 is_stmt 0 view .LVU2968 + 9267 00a6 FFF7FEFF bl TIM_CCxChannelCmd + 9268 .LVL735: + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9269 .loc 1 942 5 is_stmt 1 view .LVU2969 + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9270 .loc 1 942 9 is_stmt 0 view .LVU2970 + 9271 00aa 2368 ldr r3, [r4] + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9272 .loc 1 942 8 view .LVU2971 + 9273 00ac 4249 ldr r1, .L604 + 9274 00ae 434A ldr r2, .L604+4 + 9275 00b0 9342 cmp r3, r2 + 9276 00b2 18BF it ne + 9277 00b4 8B42 cmpne r3, r1 + 9278 00b6 03D1 bne .L593 + 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9279 .loc 1 945 7 is_stmt 1 view .LVU2972 + 9280 00b8 5A6C ldr r2, [r3, #68] + 9281 00ba 42F40042 orr r2, r2, #32768 + 9282 00be 5A64 str r2, [r3, #68] + 9283 .L593: + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9284 .loc 1 949 5 view .LVU2973 + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9285 .loc 1 949 9 is_stmt 0 view .LVU2974 + 9286 00c0 2368 ldr r3, [r4] + ARM GAS /tmp/ccGFzgX3.s page 343 + + + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9287 .loc 1 949 8 view .LVU2975 + 9288 00c2 3D4A ldr r2, .L604 + 9289 00c4 B3F1804F cmp r3, #1073741824 + 9290 00c8 18BF it ne + 9291 00ca 9342 cmpne r3, r2 + 9292 00cc 60D0 beq .L594 + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9293 .loc 1 949 9 discriminator 1 view .LVU2976 + 9294 00ce A2F57C42 sub r2, r2, #64512 + 9295 00d2 9342 cmp r3, r2 + 9296 00d4 5CD0 beq .L594 + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9297 .loc 1 949 9 discriminator 2 view .LVU2977 + 9298 00d6 02F58062 add r2, r2, #1024 + 9299 00da 9342 cmp r3, r2 + 9300 00dc 58D0 beq .L594 + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9301 .loc 1 949 9 discriminator 3 view .LVU2978 + 9302 00de 02F58062 add r2, r2, #1024 + 9303 00e2 9342 cmp r3, r2 + 9304 00e4 54D0 beq .L594 + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9305 .loc 1 949 9 discriminator 4 view .LVU2979 + 9306 00e6 02F57842 add r2, r2, #63488 + 9307 00ea 9342 cmp r3, r2 + 9308 00ec 50D0 beq .L594 + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9309 .loc 1 949 9 discriminator 5 view .LVU2980 + 9310 00ee 02F57052 add r2, r2, #15360 + 9311 00f2 9342 cmp r3, r2 + 9312 00f4 4CD0 beq .L594 + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9313 .loc 1 949 9 discriminator 6 view .LVU2981 + 9314 00f6 A2F59432 sub r2, r2, #75776 + 9315 00fa 9342 cmp r3, r2 + 9316 00fc 48D0 beq .L594 + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9317 .loc 1 959 7 is_stmt 1 view .LVU2982 + 9318 00fe 1A68 ldr r2, [r3] + 9319 0100 42F00102 orr r2, r2, #1 + 9320 0104 1A60 str r2, [r3] + 9321 0106 0020 movs r0, #0 + 9322 0108 51E0 b .L579 + 9323 .LVL736: + 9324 .L585: + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9325 .loc 1 900 3 is_stmt 0 discriminator 3 view .LVU2983 + 9326 010a 0223 movs r3, #2 + 9327 010c 84F83F30 strb r3, [r4, #63] + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9328 .loc 1 902 3 is_stmt 1 view .LVU2984 + 9329 .L588: + 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 9330 .loc 1 914 7 view .LVU2985 + 9331 0110 2268 ldr r2, [r4] + 9332 0112 D368 ldr r3, [r2, #12] + ARM GAS /tmp/ccGFzgX3.s page 344 + + + 9333 0114 43F00403 orr r3, r3, #4 + 9334 0118 D360 str r3, [r2, #12] + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9335 .loc 1 915 7 view .LVU2986 + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9336 .loc 1 937 3 view .LVU2987 + 9337 011a C2E7 b .L592 + 9338 .L584: + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9339 .loc 1 900 3 is_stmt 0 discriminator 6 view .LVU2988 + 9340 011c 0223 movs r3, #2 + 9341 011e 84F84030 strb r3, [r4, #64] + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9342 .loc 1 902 3 is_stmt 1 view .LVU2989 + 9343 .L589: + 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 9344 .loc 1 921 7 view .LVU2990 + 9345 0122 2268 ldr r2, [r4] + 9346 0124 D368 ldr r3, [r2, #12] + 9347 0126 43F00803 orr r3, r3, #8 + 9348 012a D360 str r3, [r2, #12] + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9349 .loc 1 922 7 view .LVU2991 + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9350 .loc 1 937 3 view .LVU2992 + 9351 012c B9E7 b .L592 + 9352 .L583: + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9353 .loc 1 900 3 is_stmt 0 discriminator 9 view .LVU2993 + 9354 012e 0223 movs r3, #2 + 9355 0130 84F84130 strb r3, [r4, #65] + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9356 .loc 1 902 3 is_stmt 1 view .LVU2994 + 9357 .L590: + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 9358 .loc 1 928 7 view .LVU2995 + 9359 0134 2268 ldr r2, [r4] + 9360 0136 D368 ldr r3, [r2, #12] + 9361 0138 43F01003 orr r3, r3, #16 + 9362 013c D360 str r3, [r2, #12] + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9363 .loc 1 929 7 view .LVU2996 + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9364 .loc 1 937 3 view .LVU2997 + 9365 013e B0E7 b .L592 + 9366 .L581: + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9367 .loc 1 900 3 is_stmt 0 discriminator 12 view .LVU2998 + 9368 0140 0223 movs r3, #2 + 9369 0142 84F84230 strb r3, [r4, #66] + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9370 .loc 1 902 3 is_stmt 1 view .LVU2999 + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9371 .loc 1 900 3 is_stmt 0 discriminator 12 view .LVU3000 + 9372 0146 0120 movs r0, #1 + 9373 .LVL737: + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 345 + + + 9374 .loc 1 900 3 discriminator 12 view .LVU3001 + 9375 0148 31E0 b .L579 + 9376 .LVL738: + 9377 .L580: + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9378 .loc 1 900 3 discriminator 13 view .LVU3002 + 9379 014a 0223 movs r3, #2 + 9380 014c 84F84330 strb r3, [r4, #67] + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9381 .loc 1 902 3 is_stmt 1 view .LVU3003 + 9382 0150 0C29 cmp r1, #12 + 9383 0152 2DD8 bhi .L597 + 9384 0154 01A3 adr r3, .L591 + 9385 0156 53F821F0 ldr pc, [r3, r1, lsl #2] + 9386 015a 00BF .p2align 2 + 9387 .L591: + 9388 015c 99000000 .word .L587+1 + 9389 0160 B1010000 .word .L597+1 + 9390 0164 B1010000 .word .L597+1 + 9391 0168 B1010000 .word .L597+1 + 9392 016c 11010000 .word .L588+1 + 9393 0170 B1010000 .word .L597+1 + 9394 0174 B1010000 .word .L597+1 + 9395 0178 B1010000 .word .L597+1 + 9396 017c 23010000 .word .L589+1 + 9397 0180 B1010000 .word .L597+1 + 9398 0184 B1010000 .word .L597+1 + 9399 0188 B1010000 .word .L597+1 + 9400 018c 35010000 .word .L590+1 + 9401 .LVL739: + 9402 .p2align 1 + 9403 .L594: + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 9404 .loc 1 951 7 view .LVU3004 + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 9405 .loc 1 951 31 is_stmt 0 view .LVU3005 + 9406 0190 9968 ldr r1, [r3, #8] + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 9407 .loc 1 951 15 view .LVU3006 + 9408 0192 0B4A ldr r2, .L604+8 + 9409 0194 0A40 ands r2, r2, r1 + 9410 .LVL740: + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9411 .loc 1 952 7 is_stmt 1 view .LVU3007 + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9412 .loc 1 952 10 is_stmt 0 view .LVU3008 + 9413 0196 062A cmp r2, #6 + 9414 0198 18BF it ne + 9415 019a B2F5803F cmpne r2, #65536 + 9416 019e 09D0 beq .L598 + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9417 .loc 1 954 9 is_stmt 1 view .LVU3009 + 9418 01a0 1A68 ldr r2, [r3] + 9419 .LVL741: + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9420 .loc 1 954 9 is_stmt 0 view .LVU3010 + 9421 01a2 42F00102 orr r2, r2, #1 + ARM GAS /tmp/ccGFzgX3.s page 346 + + + 9422 01a6 1A60 str r2, [r3] + 9423 01a8 0020 movs r0, #0 + 9424 01aa 00E0 b .L579 + 9425 .LVL742: + 9426 .L596: + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9427 .loc 1 896 12 view .LVU3011 + 9428 01ac 0120 movs r0, #1 + 9429 .LVL743: + 9430 .L579: + 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9431 .loc 1 965 1 view .LVU3012 + 9432 01ae 10BD pop {r4, pc} + 9433 .LVL744: + 9434 .L597: + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9435 .loc 1 902 3 view .LVU3013 + 9436 01b0 0120 movs r0, #1 + 9437 .LVL745: + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9438 .loc 1 902 3 view .LVU3014 + 9439 01b2 FCE7 b .L579 + 9440 .LVL746: + 9441 .L598: + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9442 .loc 1 902 3 view .LVU3015 + 9443 01b4 0020 movs r0, #0 + 9444 01b6 FAE7 b .L579 + 9445 .L605: + 9446 .align 2 + 9447 .L604: + 9448 01b8 00000140 .word 1073807360 + 9449 01bc 00040140 .word 1073808384 + 9450 01c0 07000100 .word 65543 + 9451 .cfi_endproc + 9452 .LFE157: + 9454 .section .text.HAL_TIM_OC_Stop_IT,"ax",%progbits + 9455 .align 1 + 9456 .global HAL_TIM_OC_Stop_IT + 9457 .syntax unified + 9458 .thumb + 9459 .thumb_func + 9461 HAL_TIM_OC_Stop_IT: + 9462 .LVL747: + 9463 .LFB158: + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 9464 .loc 1 979 1 is_stmt 1 view -0 + 9465 .cfi_startproc + 9466 @ args = 0, pretend = 0, frame = 0 + 9467 @ frame_needed = 0, uses_anonymous_args = 0 + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 9468 .loc 1 979 1 is_stmt 0 view .LVU3017 + 9469 0000 38B5 push {r3, r4, r5, lr} + 9470 .LCFI89: + 9471 .cfi_def_cfa_offset 16 + 9472 .cfi_offset 3, -16 + 9473 .cfi_offset 4, -12 + ARM GAS /tmp/ccGFzgX3.s page 347 + + + 9474 .cfi_offset 5, -8 + 9475 .cfi_offset 14, -4 + 9476 0002 0546 mov r5, r0 + 9477 0004 0C46 mov r4, r1 + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9478 .loc 1 980 3 is_stmt 1 view .LVU3018 + 9479 .LVL748: + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9480 .loc 1 983 3 view .LVU3019 + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9481 .loc 1 985 3 view .LVU3020 + 9482 0006 0C29 cmp r1, #12 + 9483 0008 73D8 bhi .L623 + 9484 000a DFE801F0 tbb [pc, r1] + 9485 .L609: + 9486 000e 07 .byte (.L612-.L609)/2 + 9487 000f 72 .byte (.L623-.L609)/2 + 9488 0010 72 .byte (.L623-.L609)/2 + 9489 0011 72 .byte (.L623-.L609)/2 + 9490 0012 42 .byte (.L611-.L609)/2 + 9491 0013 72 .byte (.L623-.L609)/2 + 9492 0014 72 .byte (.L623-.L609)/2 + 9493 0015 72 .byte (.L623-.L609)/2 + 9494 0016 48 .byte (.L610-.L609)/2 + 9495 0017 72 .byte (.L623-.L609)/2 + 9496 0018 72 .byte (.L623-.L609)/2 + 9497 0019 72 .byte (.L623-.L609)/2 + 9498 001a 4E .byte (.L608-.L609)/2 + 9499 001b 00 .p2align 1 + 9500 .L612: + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 9501 .loc 1 990 7 view .LVU3021 + 9502 001c 0268 ldr r2, [r0] + 9503 001e D368 ldr r3, [r2, #12] + 9504 0020 23F00203 bic r3, r3, #2 + 9505 0024 D360 str r3, [r2, #12] + 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9506 .loc 1 991 7 view .LVU3022 +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9507 .loc 1 1020 3 view .LVU3023 + 9508 .L613: +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9509 .loc 1 1023 5 view .LVU3024 + 9510 0026 0022 movs r2, #0 + 9511 0028 2146 mov r1, r4 + 9512 .LVL749: +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9513 .loc 1 1023 5 is_stmt 0 view .LVU3025 + 9514 002a 2868 ldr r0, [r5] + 9515 .LVL750: +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9516 .loc 1 1023 5 view .LVU3026 + 9517 002c FFF7FEFF bl TIM_CCxChannelCmd + 9518 .LVL751: +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9519 .loc 1 1025 5 is_stmt 1 view .LVU3027 +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 348 + + + 9520 .loc 1 1025 9 is_stmt 0 view .LVU3028 + 9521 0030 2B68 ldr r3, [r5] +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9522 .loc 1 1025 8 view .LVU3029 + 9523 0032 3149 ldr r1, .L625 + 9524 0034 314A ldr r2, .L625+4 + 9525 0036 9342 cmp r3, r2 + 9526 0038 18BF it ne + 9527 003a 8B42 cmpne r3, r1 + 9528 003c 0DD1 bne .L614 +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9529 .loc 1 1028 7 is_stmt 1 view .LVU3030 +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9530 .loc 1 1028 7 view .LVU3031 + 9531 003e 196A ldr r1, [r3, #32] + 9532 0040 41F21112 movw r2, #4369 + 9533 0044 1142 tst r1, r2 + 9534 0046 08D1 bne .L614 +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9535 .loc 1 1028 7 discriminator 1 view .LVU3032 + 9536 0048 196A ldr r1, [r3, #32] + 9537 004a 40F24442 movw r2, #1092 + 9538 004e 1142 tst r1, r2 + 9539 0050 03D1 bne .L614 +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9540 .loc 1 1028 7 discriminator 3 view .LVU3033 + 9541 0052 5A6C ldr r2, [r3, #68] + 9542 0054 22F40042 bic r2, r2, #32768 + 9543 0058 5A64 str r2, [r3, #68] + 9544 .L614: +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9545 .loc 1 1028 7 discriminator 5 view .LVU3034 +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9546 .loc 1 1032 5 view .LVU3035 +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9547 .loc 1 1032 5 view .LVU3036 + 9548 005a 2B68 ldr r3, [r5] + 9549 005c 196A ldr r1, [r3, #32] + 9550 005e 41F21112 movw r2, #4369 + 9551 0062 1142 tst r1, r2 + 9552 0064 08D1 bne .L615 +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9553 .loc 1 1032 5 discriminator 1 view .LVU3037 + 9554 0066 196A ldr r1, [r3, #32] + 9555 0068 40F24442 movw r2, #1092 + 9556 006c 1142 tst r1, r2 + 9557 006e 03D1 bne .L615 +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9558 .loc 1 1032 5 discriminator 3 view .LVU3038 + 9559 0070 1A68 ldr r2, [r3] + 9560 0072 22F00102 bic r2, r2, #1 + 9561 0076 1A60 str r2, [r3] + 9562 .L615: +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9563 .loc 1 1032 5 discriminator 5 view .LVU3039 +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9564 .loc 1 1035 5 view .LVU3040 + ARM GAS /tmp/ccGFzgX3.s page 349 + + + 9565 0078 102C cmp r4, #16 + 9566 007a 35D8 bhi .L616 + 9567 007c DFE804F0 tbb [pc, r4] + 9568 .L618: + 9569 0080 1B .byte (.L622-.L618)/2 + 9570 0081 34 .byte (.L616-.L618)/2 + 9571 0082 34 .byte (.L616-.L618)/2 + 9572 0083 34 .byte (.L616-.L618)/2 + 9573 0084 20 .byte (.L621-.L618)/2 + 9574 0085 34 .byte (.L616-.L618)/2 + 9575 0086 34 .byte (.L616-.L618)/2 + 9576 0087 34 .byte (.L616-.L618)/2 + 9577 0088 25 .byte (.L620-.L618)/2 + 9578 0089 34 .byte (.L616-.L618)/2 + 9579 008a 34 .byte (.L616-.L618)/2 + 9580 008b 34 .byte (.L616-.L618)/2 + 9581 008c 2A .byte (.L619-.L618)/2 + 9582 008d 34 .byte (.L616-.L618)/2 + 9583 008e 34 .byte (.L616-.L618)/2 + 9584 008f 34 .byte (.L616-.L618)/2 + 9585 0090 2F .byte (.L617-.L618)/2 + 9586 .LVL752: + 9587 0091 00 .p2align 1 + 9588 .L611: + 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 9589 .loc 1 997 7 view .LVU3041 + 9590 0092 0268 ldr r2, [r0] + 9591 0094 D368 ldr r3, [r2, #12] + 9592 0096 23F00403 bic r3, r3, #4 + 9593 009a D360 str r3, [r2, #12] + 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9594 .loc 1 998 7 view .LVU3042 +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9595 .loc 1 1020 3 view .LVU3043 + 9596 009c C3E7 b .L613 + 9597 .L610: +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 9598 .loc 1 1004 7 view .LVU3044 + 9599 009e 0268 ldr r2, [r0] + 9600 00a0 D368 ldr r3, [r2, #12] + 9601 00a2 23F00803 bic r3, r3, #8 + 9602 00a6 D360 str r3, [r2, #12] +1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9603 .loc 1 1005 7 view .LVU3045 +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9604 .loc 1 1020 3 view .LVU3046 + 9605 00a8 BDE7 b .L613 + 9606 .L608: +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 9607 .loc 1 1011 7 view .LVU3047 + 9608 00aa 0268 ldr r2, [r0] + 9609 00ac D368 ldr r3, [r2, #12] + 9610 00ae 23F01003 bic r3, r3, #16 + 9611 00b2 D360 str r3, [r2, #12] +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9612 .loc 1 1012 7 view .LVU3048 +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 350 + + + 9613 .loc 1 1020 3 view .LVU3049 + 9614 00b4 B7E7 b .L613 + 9615 .LVL753: + 9616 .L622: +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9617 .loc 1 1035 5 is_stmt 0 discriminator 1 view .LVU3050 + 9618 00b6 0123 movs r3, #1 + 9619 00b8 85F83E30 strb r3, [r5, #62] + 9620 00bc 0020 movs r0, #0 + 9621 00be 19E0 b .L607 + 9622 .L621: +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9623 .loc 1 1035 5 discriminator 3 view .LVU3051 + 9624 00c0 0123 movs r3, #1 + 9625 00c2 85F83F30 strb r3, [r5, #63] + 9626 00c6 0020 movs r0, #0 + 9627 00c8 14E0 b .L607 + 9628 .L620: +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9629 .loc 1 1035 5 discriminator 6 view .LVU3052 + 9630 00ca 0123 movs r3, #1 + 9631 00cc 85F84030 strb r3, [r5, #64] + 9632 00d0 0020 movs r0, #0 + 9633 00d2 0FE0 b .L607 + 9634 .L619: +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9635 .loc 1 1035 5 discriminator 9 view .LVU3053 + 9636 00d4 0123 movs r3, #1 + 9637 00d6 85F84130 strb r3, [r5, #65] + 9638 00da 0020 movs r0, #0 + 9639 00dc 0AE0 b .L607 + 9640 .L617: +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9641 .loc 1 1035 5 discriminator 12 view .LVU3054 + 9642 00de 0123 movs r3, #1 + 9643 00e0 85F84230 strb r3, [r5, #66] + 9644 00e4 0020 movs r0, #0 + 9645 00e6 05E0 b .L607 + 9646 .L616: +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9647 .loc 1 1035 5 discriminator 13 view .LVU3055 + 9648 00e8 0123 movs r3, #1 + 9649 00ea 85F84330 strb r3, [r5, #67] + 9650 00ee 0020 movs r0, #0 + 9651 00f0 00E0 b .L607 + 9652 .LVL754: + 9653 .L623: + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9654 .loc 1 985 3 view .LVU3056 + 9655 00f2 0120 movs r0, #1 + 9656 .LVL755: + 9657 .L607: +1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9658 .loc 1 1039 3 is_stmt 1 view .LVU3057 +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9659 .loc 1 1040 1 is_stmt 0 view .LVU3058 + 9660 00f4 38BD pop {r3, r4, r5, pc} + ARM GAS /tmp/ccGFzgX3.s page 351 + + + 9661 .LVL756: + 9662 .L626: +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9663 .loc 1 1040 1 view .LVU3059 + 9664 00f6 00BF .align 2 + 9665 .L625: + 9666 00f8 00000140 .word 1073807360 + 9667 00fc 00040140 .word 1073808384 + 9668 .cfi_endproc + 9669 .LFE158: + 9671 .section .text.HAL_TIM_OC_Start_DMA,"ax",%progbits + 9672 .align 1 + 9673 .global HAL_TIM_OC_Start_DMA + 9674 .syntax unified + 9675 .thumb + 9676 .thumb_func + 9678 HAL_TIM_OC_Start_DMA: + 9679 .LVL757: + 9680 .LFB159: +1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 9681 .loc 1 1057 1 is_stmt 1 view -0 + 9682 .cfi_startproc + 9683 @ args = 0, pretend = 0, frame = 0 + 9684 @ frame_needed = 0, uses_anonymous_args = 0 +1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 9685 .loc 1 1057 1 is_stmt 0 view .LVU3061 + 9686 0000 38B5 push {r3, r4, r5, lr} + 9687 .LCFI90: + 9688 .cfi_def_cfa_offset 16 + 9689 .cfi_offset 3, -16 + 9690 .cfi_offset 4, -12 + 9691 .cfi_offset 5, -8 + 9692 .cfi_offset 14, -4 + 9693 0002 0546 mov r5, r0 + 9694 0004 0C46 mov r4, r1 + 9695 0006 1146 mov r1, r2 + 9696 .LVL758: +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 9697 .loc 1 1058 3 is_stmt 1 view .LVU3062 +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9698 .loc 1 1059 3 view .LVU3063 +1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9699 .loc 1 1062 3 view .LVU3064 +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9700 .loc 1 1065 3 view .LVU3065 + 9701 0008 102C cmp r4, #16 + 9702 000a 41D8 bhi .L628 + 9703 000c DFE804F0 tbb [pc, r4] + 9704 .LVL759: + 9705 .L630: + 9706 0010 09 .byte (.L634-.L630)/2 + 9707 0011 40 .byte (.L628-.L630)/2 + 9708 0012 40 .byte (.L628-.L630)/2 + 9709 0013 40 .byte (.L628-.L630)/2 + 9710 0014 20 .byte (.L633-.L630)/2 + 9711 0015 40 .byte (.L628-.L630)/2 + 9712 0016 40 .byte (.L628-.L630)/2 + ARM GAS /tmp/ccGFzgX3.s page 352 + + + 9713 0017 40 .byte (.L628-.L630)/2 + 9714 0018 28 .byte (.L632-.L630)/2 + 9715 0019 40 .byte (.L628-.L630)/2 + 9716 001a 40 .byte (.L628-.L630)/2 + 9717 001b 40 .byte (.L628-.L630)/2 + 9718 001c 30 .byte (.L631-.L630)/2 + 9719 001d 40 .byte (.L628-.L630)/2 + 9720 001e 40 .byte (.L628-.L630)/2 + 9721 001f 40 .byte (.L628-.L630)/2 + 9722 0020 38 .byte (.L629-.L630)/2 + 9723 0021 00 .p2align 1 + 9724 .L634: +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9725 .loc 1 1065 7 is_stmt 0 discriminator 1 view .LVU3066 + 9726 0022 90F83E00 ldrb r0, [r0, #62] @ zero_extendqisi2 + 9727 .LVL760: +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9728 .loc 1 1065 7 discriminator 1 view .LVU3067 + 9729 0026 C0B2 uxtb r0, r0 +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9730 .loc 1 1065 44 discriminator 1 view .LVU3068 + 9731 0028 0228 cmp r0, #2 + 9732 002a 14BF ite ne + 9733 002c 0020 movne r0, #0 + 9734 002e 0120 moveq r0, #1 + 9735 .L635: +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9736 .loc 1 1065 6 discriminator 20 view .LVU3069 + 9737 0030 0028 cmp r0, #0 + 9738 0032 40F05581 bne .L661 +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9739 .loc 1 1069 8 is_stmt 1 view .LVU3070 + 9740 0036 102C cmp r4, #16 + 9741 0038 77D8 bhi .L637 + 9742 003a DFE804F0 tbb [pc, r4] + 9743 .L639: + 9744 003e 31 .byte (.L643-.L639)/2 + 9745 003f 76 .byte (.L637-.L639)/2 + 9746 0040 76 .byte (.L637-.L639)/2 + 9747 0041 76 .byte (.L637-.L639)/2 + 9748 0042 56 .byte (.L642-.L639)/2 + 9749 0043 76 .byte (.L637-.L639)/2 + 9750 0044 76 .byte (.L637-.L639)/2 + 9751 0045 76 .byte (.L637-.L639)/2 + 9752 0046 5E .byte (.L641-.L639)/2 + 9753 0047 76 .byte (.L637-.L639)/2 + 9754 0048 76 .byte (.L637-.L639)/2 + 9755 0049 76 .byte (.L637-.L639)/2 + 9756 004a 66 .byte (.L640-.L639)/2 + 9757 004b 76 .byte (.L637-.L639)/2 + 9758 004c 76 .byte (.L637-.L639)/2 + 9759 004d 76 .byte (.L637-.L639)/2 + 9760 004e 6E .byte (.L638-.L639)/2 + 9761 .LVL761: + 9762 004f 00 .p2align 1 + 9763 .L633: +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 353 + + + 9764 .loc 1 1065 7 is_stmt 0 discriminator 4 view .LVU3071 + 9765 0050 90F83F00 ldrb r0, [r0, #63] @ zero_extendqisi2 + 9766 .LVL762: +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9767 .loc 1 1065 7 discriminator 4 view .LVU3072 + 9768 0054 C0B2 uxtb r0, r0 +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9769 .loc 1 1065 44 discriminator 4 view .LVU3073 + 9770 0056 0228 cmp r0, #2 + 9771 0058 14BF ite ne + 9772 005a 0020 movne r0, #0 + 9773 005c 0120 moveq r0, #1 + 9774 005e E7E7 b .L635 + 9775 .LVL763: + 9776 .L632: +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9777 .loc 1 1065 7 discriminator 7 view .LVU3074 + 9778 0060 90F84000 ldrb r0, [r0, #64] @ zero_extendqisi2 + 9779 .LVL764: +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9780 .loc 1 1065 7 discriminator 7 view .LVU3075 + 9781 0064 C0B2 uxtb r0, r0 +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9782 .loc 1 1065 44 discriminator 7 view .LVU3076 + 9783 0066 0228 cmp r0, #2 + 9784 0068 14BF ite ne + 9785 006a 0020 movne r0, #0 + 9786 006c 0120 moveq r0, #1 + 9787 006e DFE7 b .L635 + 9788 .LVL765: + 9789 .L631: +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9790 .loc 1 1065 7 discriminator 10 view .LVU3077 + 9791 0070 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 9792 .LVL766: +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9793 .loc 1 1065 7 discriminator 10 view .LVU3078 + 9794 0074 C0B2 uxtb r0, r0 +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9795 .loc 1 1065 44 discriminator 10 view .LVU3079 + 9796 0076 0228 cmp r0, #2 + 9797 0078 14BF ite ne + 9798 007a 0020 movne r0, #0 + 9799 007c 0120 moveq r0, #1 + 9800 007e D7E7 b .L635 + 9801 .LVL767: + 9802 .L629: +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9803 .loc 1 1065 7 discriminator 13 view .LVU3080 + 9804 0080 90F84200 ldrb r0, [r0, #66] @ zero_extendqisi2 + 9805 .LVL768: +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9806 .loc 1 1065 7 discriminator 13 view .LVU3081 + 9807 0084 C0B2 uxtb r0, r0 +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9808 .loc 1 1065 44 discriminator 13 view .LVU3082 + 9809 0086 0228 cmp r0, #2 + ARM GAS /tmp/ccGFzgX3.s page 354 + + + 9810 0088 14BF ite ne + 9811 008a 0020 movne r0, #0 + 9812 008c 0120 moveq r0, #1 + 9813 008e CFE7 b .L635 + 9814 .LVL769: + 9815 .L628: +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9816 .loc 1 1065 7 discriminator 14 view .LVU3083 + 9817 0090 90F84300 ldrb r0, [r0, #67] @ zero_extendqisi2 + 9818 .LVL770: +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9819 .loc 1 1065 7 discriminator 14 view .LVU3084 + 9820 0094 C0B2 uxtb r0, r0 +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9821 .loc 1 1065 44 discriminator 14 view .LVU3085 + 9822 0096 0228 cmp r0, #2 + 9823 0098 14BF ite ne + 9824 009a 0020 movne r0, #0 + 9825 009c 0120 moveq r0, #1 + 9826 009e C7E7 b .L635 + 9827 .L643: +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9828 .loc 1 1069 12 discriminator 1 view .LVU3086 + 9829 00a0 95F83E20 ldrb r2, [r5, #62] @ zero_extendqisi2 + 9830 00a4 D2B2 uxtb r2, r2 +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9831 .loc 1 1069 49 discriminator 1 view .LVU3087 + 9832 00a6 012A cmp r2, #1 + 9833 00a8 14BF ite ne + 9834 00aa 0022 movne r2, #0 + 9835 00ac 0122 moveq r2, #1 + 9836 .L644: +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9837 .loc 1 1069 11 discriminator 20 view .LVU3088 + 9838 00ae 002A cmp r2, #0 + 9839 00b0 00F01881 beq .L662 +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9840 .loc 1 1071 5 is_stmt 1 view .LVU3089 +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9841 .loc 1 1071 8 is_stmt 0 view .LVU3090 + 9842 00b4 002B cmp r3, #0 + 9843 00b6 18BF it ne + 9844 00b8 0029 cmpne r1, #0 + 9845 00ba 00F01581 beq .L663 +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9846 .loc 1 1077 7 is_stmt 1 view .LVU3091 + 9847 00be 102C cmp r4, #16 + 9848 00c0 00F2DE80 bhi .L645 + 9849 00c4 DFE814F0 tbh [pc, r4, lsl #1] + 9850 .L647: + 9851 00c8 3900 .2byte (.L651-.L647)/2 + 9852 00ca DC00 .2byte (.L645-.L647)/2 + 9853 00cc DC00 .2byte (.L645-.L647)/2 + 9854 00ce DC00 .2byte (.L645-.L647)/2 + 9855 00d0 8C00 .2byte (.L650-.L647)/2 + 9856 00d2 DC00 .2byte (.L645-.L647)/2 + 9857 00d4 DC00 .2byte (.L645-.L647)/2 + ARM GAS /tmp/ccGFzgX3.s page 355 + + + 9858 00d6 DC00 .2byte (.L645-.L647)/2 + 9859 00d8 A500 .2byte (.L649-.L647)/2 + 9860 00da DC00 .2byte (.L645-.L647)/2 + 9861 00dc DC00 .2byte (.L645-.L647)/2 + 9862 00de DC00 .2byte (.L645-.L647)/2 + 9863 00e0 BE00 .2byte (.L648-.L647)/2 + 9864 00e2 DC00 .2byte (.L645-.L647)/2 + 9865 00e4 DC00 .2byte (.L645-.L647)/2 + 9866 00e6 DC00 .2byte (.L645-.L647)/2 + 9867 00e8 D700 .2byte (.L646-.L647)/2 + 9868 .p2align 1 + 9869 .L642: +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9870 .loc 1 1069 12 is_stmt 0 discriminator 4 view .LVU3092 + 9871 00ea 95F83F20 ldrb r2, [r5, #63] @ zero_extendqisi2 + 9872 00ee D2B2 uxtb r2, r2 +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9873 .loc 1 1069 49 discriminator 4 view .LVU3093 + 9874 00f0 012A cmp r2, #1 + 9875 00f2 14BF ite ne + 9876 00f4 0022 movne r2, #0 + 9877 00f6 0122 moveq r2, #1 + 9878 00f8 D9E7 b .L644 + 9879 .L641: +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9880 .loc 1 1069 12 discriminator 7 view .LVU3094 + 9881 00fa 95F84020 ldrb r2, [r5, #64] @ zero_extendqisi2 + 9882 00fe D2B2 uxtb r2, r2 +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9883 .loc 1 1069 49 discriminator 7 view .LVU3095 + 9884 0100 012A cmp r2, #1 + 9885 0102 14BF ite ne + 9886 0104 0022 movne r2, #0 + 9887 0106 0122 moveq r2, #1 + 9888 0108 D1E7 b .L644 + 9889 .L640: +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9890 .loc 1 1069 12 discriminator 10 view .LVU3096 + 9891 010a 95F84120 ldrb r2, [r5, #65] @ zero_extendqisi2 + 9892 010e D2B2 uxtb r2, r2 +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9893 .loc 1 1069 49 discriminator 10 view .LVU3097 + 9894 0110 012A cmp r2, #1 + 9895 0112 14BF ite ne + 9896 0114 0022 movne r2, #0 + 9897 0116 0122 moveq r2, #1 + 9898 0118 C9E7 b .L644 + 9899 .L638: +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9900 .loc 1 1069 12 discriminator 13 view .LVU3098 + 9901 011a 95F84220 ldrb r2, [r5, #66] @ zero_extendqisi2 + 9902 011e D2B2 uxtb r2, r2 +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9903 .loc 1 1069 49 discriminator 13 view .LVU3099 + 9904 0120 012A cmp r2, #1 + 9905 0122 14BF ite ne + 9906 0124 0022 movne r2, #0 + ARM GAS /tmp/ccGFzgX3.s page 356 + + + 9907 0126 0122 moveq r2, #1 + 9908 0128 C1E7 b .L644 + 9909 .L637: +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9910 .loc 1 1069 12 discriminator 14 view .LVU3100 + 9911 012a 95F84320 ldrb r2, [r5, #67] @ zero_extendqisi2 + 9912 012e D2B2 uxtb r2, r2 +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9913 .loc 1 1069 49 discriminator 14 view .LVU3101 + 9914 0130 012A cmp r2, #1 + 9915 0132 14BF ite ne + 9916 0134 0022 movne r2, #0 + 9917 0136 0122 moveq r2, #1 + 9918 0138 B9E7 b .L644 + 9919 .L651: +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9920 .loc 1 1077 7 discriminator 1 view .LVU3102 + 9921 013a 0222 movs r2, #2 + 9922 013c 85F83E20 strb r2, [r5, #62] +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9923 .loc 1 1085 3 is_stmt 1 view .LVU3103 + 9924 .L652: +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 9925 .loc 1 1090 7 view .LVU3104 +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 9926 .loc 1 1090 17 is_stmt 0 view .LVU3105 + 9927 0140 6A6A ldr r2, [r5, #36] +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 9928 .loc 1 1090 52 view .LVU3106 + 9929 0142 7048 ldr r0, .L675 + 9930 0144 D063 str r0, [r2, #60] +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9931 .loc 1 1091 7 is_stmt 1 view .LVU3107 +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9932 .loc 1 1091 17 is_stmt 0 view .LVU3108 + 9933 0146 6A6A ldr r2, [r5, #36] +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9934 .loc 1 1091 56 view .LVU3109 + 9935 0148 6F48 ldr r0, .L675+4 + 9936 014a 1064 str r0, [r2, #64] +1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9937 .loc 1 1094 7 is_stmt 1 view .LVU3110 +1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9938 .loc 1 1094 17 is_stmt 0 view .LVU3111 + 9939 014c 6A6A ldr r2, [r5, #36] +1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9940 .loc 1 1094 53 view .LVU3112 + 9941 014e 6F48 ldr r0, .L675+8 + 9942 0150 D064 str r0, [r2, #76] +1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 9943 .loc 1 1097 7 is_stmt 1 view .LVU3113 +1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 9944 .loc 1 1097 88 is_stmt 0 view .LVU3114 + 9945 0152 2A68 ldr r2, [r5] +1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 9946 .loc 1 1097 11 view .LVU3115 + 9947 0154 3432 adds r2, r2, #52 + ARM GAS /tmp/ccGFzgX3.s page 357 + + + 9948 0156 686A ldr r0, [r5, #36] + 9949 0158 FFF7FEFF bl HAL_DMA_Start_IT + 9950 .LVL771: +1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 9951 .loc 1 1097 10 discriminator 1 view .LVU3116 + 9952 015c 0028 cmp r0, #0 + 9953 015e 40F0C780 bne .L665 +1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 9954 .loc 1 1105 7 is_stmt 1 view .LVU3117 + 9955 0162 2A68 ldr r2, [r5] + 9956 0164 D368 ldr r3, [r2, #12] + 9957 0166 43F40073 orr r3, r3, #512 + 9958 016a D360 str r3, [r2, #12] +1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9959 .loc 1 1106 7 view .LVU3118 +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9960 .loc 1 1178 3 view .LVU3119 + 9961 .L657: +1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 9962 .loc 1 1181 5 view .LVU3120 + 9963 016c 0122 movs r2, #1 + 9964 016e 2146 mov r1, r4 + 9965 0170 2868 ldr r0, [r5] + 9966 0172 FFF7FEFF bl TIM_CCxChannelCmd + 9967 .LVL772: +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9968 .loc 1 1183 5 view .LVU3121 +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9969 .loc 1 1183 9 is_stmt 0 view .LVU3122 + 9970 0176 2B68 ldr r3, [r5] +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9971 .loc 1 1183 8 view .LVU3123 + 9972 0178 6549 ldr r1, .L675+12 + 9973 017a 664A ldr r2, .L675+16 + 9974 017c 9342 cmp r3, r2 + 9975 017e 18BF it ne + 9976 0180 8B42 cmpne r3, r1 + 9977 0182 03D1 bne .L658 +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 9978 .loc 1 1186 7 is_stmt 1 view .LVU3124 + 9979 0184 5A6C ldr r2, [r3, #68] + 9980 0186 42F40042 orr r2, r2, #32768 + 9981 018a 5A64 str r2, [r3, #68] + 9982 .L658: +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9983 .loc 1 1190 5 view .LVU3125 +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9984 .loc 1 1190 9 is_stmt 0 view .LVU3126 + 9985 018c 2B68 ldr r3, [r5] +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9986 .loc 1 1190 8 view .LVU3127 + 9987 018e 604A ldr r2, .L675+12 + 9988 0190 B3F1804F cmp r3, #1073741824 + 9989 0194 18BF it ne + 9990 0196 9342 cmpne r3, r2 + 9991 0198 00F09480 beq .L659 +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 358 + + + 9992 .loc 1 1190 9 discriminator 1 view .LVU3128 + 9993 019c A2F57C42 sub r2, r2, #64512 + 9994 01a0 9342 cmp r3, r2 + 9995 01a2 00F08F80 beq .L659 +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 9996 .loc 1 1190 9 discriminator 2 view .LVU3129 + 9997 01a6 02F58062 add r2, r2, #1024 + 9998 01aa 9342 cmp r3, r2 + 9999 01ac 00F08A80 beq .L659 +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10000 .loc 1 1190 9 discriminator 3 view .LVU3130 + 10001 01b0 02F58062 add r2, r2, #1024 + 10002 01b4 9342 cmp r3, r2 + 10003 01b6 00F08580 beq .L659 +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10004 .loc 1 1190 9 discriminator 4 view .LVU3131 + 10005 01ba 02F57842 add r2, r2, #63488 + 10006 01be 9342 cmp r3, r2 + 10007 01c0 00F08080 beq .L659 +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10008 .loc 1 1190 9 discriminator 5 view .LVU3132 + 10009 01c4 02F57052 add r2, r2, #15360 + 10010 01c8 9342 cmp r3, r2 + 10011 01ca 7BD0 beq .L659 +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10012 .loc 1 1190 9 discriminator 6 view .LVU3133 + 10013 01cc A2F59432 sub r2, r2, #75776 + 10014 01d0 9342 cmp r3, r2 + 10015 01d2 77D0 beq .L659 +1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10016 .loc 1 1200 7 is_stmt 1 view .LVU3134 + 10017 01d4 1A68 ldr r2, [r3] + 10018 01d6 42F00102 orr r2, r2, #1 + 10019 01da 1A60 str r2, [r3] + 10020 01dc 0020 movs r0, #0 + 10021 01de 82E0 b .L636 + 10022 .LVL773: + 10023 .L650: +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10024 .loc 1 1077 7 is_stmt 0 discriminator 3 view .LVU3135 + 10025 01e0 0222 movs r2, #2 + 10026 01e2 85F83F20 strb r2, [r5, #63] +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10027 .loc 1 1085 3 is_stmt 1 view .LVU3136 + 10028 .L653: +1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 10029 .loc 1 1112 7 view .LVU3137 +1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 10030 .loc 1 1112 17 is_stmt 0 view .LVU3138 + 10031 01e6 AA6A ldr r2, [r5, #40] +1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 10032 .loc 1 1112 52 view .LVU3139 + 10033 01e8 4648 ldr r0, .L675 + 10034 01ea D063 str r0, [r2, #60] +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10035 .loc 1 1113 7 is_stmt 1 view .LVU3140 +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 359 + + + 10036 .loc 1 1113 17 is_stmt 0 view .LVU3141 + 10037 01ec AA6A ldr r2, [r5, #40] +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10038 .loc 1 1113 56 view .LVU3142 + 10039 01ee 4648 ldr r0, .L675+4 + 10040 01f0 1064 str r0, [r2, #64] +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10041 .loc 1 1116 7 is_stmt 1 view .LVU3143 +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10042 .loc 1 1116 17 is_stmt 0 view .LVU3144 + 10043 01f2 AA6A ldr r2, [r5, #40] +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10044 .loc 1 1116 53 view .LVU3145 + 10045 01f4 4548 ldr r0, .L675+8 + 10046 01f6 D064 str r0, [r2, #76] +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 10047 .loc 1 1119 7 is_stmt 1 view .LVU3146 +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 10048 .loc 1 1119 88 is_stmt 0 view .LVU3147 + 10049 01f8 2A68 ldr r2, [r5] +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 10050 .loc 1 1119 11 view .LVU3148 + 10051 01fa 3832 adds r2, r2, #56 + 10052 01fc A86A ldr r0, [r5, #40] + 10053 01fe FFF7FEFF bl HAL_DMA_Start_IT + 10054 .LVL774: +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 10055 .loc 1 1119 10 discriminator 1 view .LVU3149 + 10056 0202 0028 cmp r0, #0 + 10057 0204 76D1 bne .L666 +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 10058 .loc 1 1127 7 is_stmt 1 view .LVU3150 + 10059 0206 2A68 ldr r2, [r5] + 10060 0208 D368 ldr r3, [r2, #12] + 10061 020a 43F48063 orr r3, r3, #1024 + 10062 020e D360 str r3, [r2, #12] +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10063 .loc 1 1128 7 view .LVU3151 +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10064 .loc 1 1178 3 view .LVU3152 + 10065 0210 ACE7 b .L657 + 10066 .LVL775: + 10067 .L649: +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10068 .loc 1 1077 7 is_stmt 0 discriminator 6 view .LVU3153 + 10069 0212 0222 movs r2, #2 + 10070 0214 85F84020 strb r2, [r5, #64] +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10071 .loc 1 1085 3 is_stmt 1 view .LVU3154 + 10072 .L654: +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 10073 .loc 1 1134 7 view .LVU3155 +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 10074 .loc 1 1134 17 is_stmt 0 view .LVU3156 + 10075 0218 EA6A ldr r2, [r5, #44] +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 10076 .loc 1 1134 52 view .LVU3157 + ARM GAS /tmp/ccGFzgX3.s page 360 + + + 10077 021a 3A48 ldr r0, .L675 + 10078 021c D063 str r0, [r2, #60] +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10079 .loc 1 1135 7 is_stmt 1 view .LVU3158 +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10080 .loc 1 1135 17 is_stmt 0 view .LVU3159 + 10081 021e EA6A ldr r2, [r5, #44] +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10082 .loc 1 1135 56 view .LVU3160 + 10083 0220 3948 ldr r0, .L675+4 + 10084 0222 1064 str r0, [r2, #64] +1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10085 .loc 1 1138 7 is_stmt 1 view .LVU3161 +1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10086 .loc 1 1138 17 is_stmt 0 view .LVU3162 + 10087 0224 EA6A ldr r2, [r5, #44] +1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10088 .loc 1 1138 53 view .LVU3163 + 10089 0226 3948 ldr r0, .L675+8 + 10090 0228 D064 str r0, [r2, #76] +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 10091 .loc 1 1141 7 is_stmt 1 view .LVU3164 +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 10092 .loc 1 1141 88 is_stmt 0 view .LVU3165 + 10093 022a 2A68 ldr r2, [r5] +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 10094 .loc 1 1141 11 view .LVU3166 + 10095 022c 3C32 adds r2, r2, #60 + 10096 022e E86A ldr r0, [r5, #44] + 10097 0230 FFF7FEFF bl HAL_DMA_Start_IT + 10098 .LVL776: +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 10099 .loc 1 1141 10 discriminator 1 view .LVU3167 + 10100 0234 0028 cmp r0, #0 + 10101 0236 5FD1 bne .L667 +1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 10102 .loc 1 1148 7 is_stmt 1 view .LVU3168 + 10103 0238 2A68 ldr r2, [r5] + 10104 023a D368 ldr r3, [r2, #12] + 10105 023c 43F40063 orr r3, r3, #2048 + 10106 0240 D360 str r3, [r2, #12] +1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10107 .loc 1 1149 7 view .LVU3169 +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10108 .loc 1 1178 3 view .LVU3170 + 10109 0242 93E7 b .L657 + 10110 .LVL777: + 10111 .L648: +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10112 .loc 1 1077 7 is_stmt 0 discriminator 9 view .LVU3171 + 10113 0244 0222 movs r2, #2 + 10114 0246 85F84120 strb r2, [r5, #65] +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10115 .loc 1 1085 3 is_stmt 1 view .LVU3172 + 10116 .L655: +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 10117 .loc 1 1155 7 view .LVU3173 + ARM GAS /tmp/ccGFzgX3.s page 361 + + +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 10118 .loc 1 1155 17 is_stmt 0 view .LVU3174 + 10119 024a 2A6B ldr r2, [r5, #48] +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 10120 .loc 1 1155 52 view .LVU3175 + 10121 024c 2D48 ldr r0, .L675 + 10122 024e D063 str r0, [r2, #60] +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10123 .loc 1 1156 7 is_stmt 1 view .LVU3176 +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10124 .loc 1 1156 17 is_stmt 0 view .LVU3177 + 10125 0250 2A6B ldr r2, [r5, #48] +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10126 .loc 1 1156 56 view .LVU3178 + 10127 0252 2D48 ldr r0, .L675+4 + 10128 0254 1064 str r0, [r2, #64] +1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10129 .loc 1 1159 7 is_stmt 1 view .LVU3179 +1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10130 .loc 1 1159 17 is_stmt 0 view .LVU3180 + 10131 0256 2A6B ldr r2, [r5, #48] +1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10132 .loc 1 1159 53 view .LVU3181 + 10133 0258 2C48 ldr r0, .L675+8 + 10134 025a D064 str r0, [r2, #76] +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 10135 .loc 1 1162 7 is_stmt 1 view .LVU3182 +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 10136 .loc 1 1162 88 is_stmt 0 view .LVU3183 + 10137 025c 2A68 ldr r2, [r5] +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 10138 .loc 1 1162 11 view .LVU3184 + 10139 025e 4032 adds r2, r2, #64 + 10140 0260 286B ldr r0, [r5, #48] + 10141 0262 FFF7FEFF bl HAL_DMA_Start_IT + 10142 .LVL778: +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 10143 .loc 1 1162 10 discriminator 1 view .LVU3185 + 10144 0266 0028 cmp r0, #0 + 10145 0268 48D1 bne .L668 +1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 10146 .loc 1 1169 7 is_stmt 1 view .LVU3186 + 10147 026a 2A68 ldr r2, [r5] + 10148 026c D368 ldr r3, [r2, #12] + 10149 026e 43F48053 orr r3, r3, #4096 + 10150 0272 D360 str r3, [r2, #12] +1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10151 .loc 1 1170 7 view .LVU3187 +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10152 .loc 1 1178 3 view .LVU3188 + 10153 0274 7AE7 b .L657 + 10154 .LVL779: + 10155 .L646: +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10156 .loc 1 1077 7 is_stmt 0 discriminator 12 view .LVU3189 + 10157 0276 0223 movs r3, #2 + 10158 .LVL780: + ARM GAS /tmp/ccGFzgX3.s page 362 + + +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10159 .loc 1 1077 7 discriminator 12 view .LVU3190 + 10160 0278 85F84230 strb r3, [r5, #66] +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10161 .loc 1 1085 3 is_stmt 1 view .LVU3191 +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10162 .loc 1 1077 7 is_stmt 0 discriminator 12 view .LVU3192 + 10163 027c 0120 movs r0, #1 + 10164 027e 32E0 b .L636 + 10165 .LVL781: + 10166 .L645: +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10167 .loc 1 1077 7 discriminator 13 view .LVU3193 + 10168 0280 0222 movs r2, #2 + 10169 0282 85F84320 strb r2, [r5, #67] +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10170 .loc 1 1085 3 is_stmt 1 view .LVU3194 + 10171 0286 0C2C cmp r4, #12 + 10172 0288 30D8 bhi .L664 + 10173 028a 01A2 adr r2, .L656 + 10174 028c 52F824F0 ldr pc, [r2, r4, lsl #2] + 10175 .p2align 2 + 10176 .L656: + 10177 0290 41010000 .word .L652+1 + 10178 0294 ED020000 .word .L664+1 + 10179 0298 ED020000 .word .L664+1 + 10180 029c ED020000 .word .L664+1 + 10181 02a0 E7010000 .word .L653+1 + 10182 02a4 ED020000 .word .L664+1 + 10183 02a8 ED020000 .word .L664+1 + 10184 02ac ED020000 .word .L664+1 + 10185 02b0 19020000 .word .L654+1 + 10186 02b4 ED020000 .word .L664+1 + 10187 02b8 ED020000 .word .L664+1 + 10188 02bc ED020000 .word .L664+1 + 10189 02c0 4B020000 .word .L655+1 + 10190 .LVL782: + 10191 .p2align 1 + 10192 .L659: +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 10193 .loc 1 1192 7 view .LVU3195 +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 10194 .loc 1 1192 31 is_stmt 0 view .LVU3196 + 10195 02c4 9968 ldr r1, [r3, #8] +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 10196 .loc 1 1192 15 view .LVU3197 + 10197 02c6 144A ldr r2, .L675+20 + 10198 02c8 0A40 ands r2, r2, r1 + 10199 .LVL783: +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10200 .loc 1 1193 7 is_stmt 1 view .LVU3198 +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10201 .loc 1 1193 10 is_stmt 0 view .LVU3199 + 10202 02ca 062A cmp r2, #6 + 10203 02cc 18BF it ne + 10204 02ce B2F5803F cmpne r2, #65536 + 10205 02d2 15D0 beq .L669 + ARM GAS /tmp/ccGFzgX3.s page 363 + + +1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10206 .loc 1 1195 9 is_stmt 1 view .LVU3200 + 10207 02d4 1A68 ldr r2, [r3] + 10208 .LVL784: +1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10209 .loc 1 1195 9 is_stmt 0 view .LVU3201 + 10210 02d6 42F00102 orr r2, r2, #1 + 10211 02da 1A60 str r2, [r3] + 10212 02dc 0020 movs r0, #0 + 10213 02de 02E0 b .L636 + 10214 .LVL785: + 10215 .L661: +1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10216 .loc 1 1067 12 view .LVU3202 + 10217 02e0 0220 movs r0, #2 + 10218 02e2 00E0 b .L636 + 10219 .L662: +1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10220 .loc 1 1082 12 view .LVU3203 + 10221 02e4 0120 movs r0, #1 + 10222 .LVL786: + 10223 .L636: +1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10224 .loc 1 1206 1 view .LVU3204 + 10225 02e6 38BD pop {r3, r4, r5, pc} + 10226 .LVL787: + 10227 .L663: +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10228 .loc 1 1073 14 view .LVU3205 + 10229 02e8 0120 movs r0, #1 + 10230 02ea FCE7 b .L636 + 10231 .L664: +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10232 .loc 1 1085 3 view .LVU3206 + 10233 02ec 0120 movs r0, #1 + 10234 02ee FAE7 b .L636 + 10235 .LVL788: + 10236 .L665: +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10237 .loc 1 1101 16 view .LVU3207 + 10238 02f0 0120 movs r0, #1 + 10239 02f2 F8E7 b .L636 + 10240 .L666: +1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10241 .loc 1 1123 16 view .LVU3208 + 10242 02f4 0120 movs r0, #1 + 10243 02f6 F6E7 b .L636 + 10244 .L667: +1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10245 .loc 1 1145 16 view .LVU3209 + 10246 02f8 0120 movs r0, #1 + 10247 02fa F4E7 b .L636 + 10248 .L668: +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10249 .loc 1 1166 16 view .LVU3210 + 10250 02fc 0120 movs r0, #1 + 10251 02fe F2E7 b .L636 + ARM GAS /tmp/ccGFzgX3.s page 364 + + + 10252 .LVL789: + 10253 .L669: +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10254 .loc 1 1166 16 view .LVU3211 + 10255 0300 0020 movs r0, #0 + 10256 0302 F0E7 b .L636 + 10257 .L676: + 10258 .align 2 + 10259 .L675: + 10260 0304 00000000 .word TIM_DMADelayPulseCplt + 10261 0308 00000000 .word TIM_DMADelayPulseHalfCplt + 10262 030c 00000000 .word TIM_DMAError + 10263 0310 00000140 .word 1073807360 + 10264 0314 00040140 .word 1073808384 + 10265 0318 07000100 .word 65543 + 10266 .cfi_endproc + 10267 .LFE159: + 10269 .section .text.HAL_TIM_OC_Stop_DMA,"ax",%progbits + 10270 .align 1 + 10271 .global HAL_TIM_OC_Stop_DMA + 10272 .syntax unified + 10273 .thumb + 10274 .thumb_func + 10276 HAL_TIM_OC_Stop_DMA: + 10277 .LVL790: + 10278 .LFB160: +1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 10279 .loc 1 1220 1 is_stmt 1 view -0 + 10280 .cfi_startproc + 10281 @ args = 0, pretend = 0, frame = 0 + 10282 @ frame_needed = 0, uses_anonymous_args = 0 +1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 10283 .loc 1 1220 1 is_stmt 0 view .LVU3213 + 10284 0000 38B5 push {r3, r4, r5, lr} + 10285 .LCFI91: + 10286 .cfi_def_cfa_offset 16 + 10287 .cfi_offset 3, -16 + 10288 .cfi_offset 4, -12 + 10289 .cfi_offset 5, -8 + 10290 .cfi_offset 14, -4 + 10291 0002 0446 mov r4, r0 + 10292 0004 0D46 mov r5, r1 +1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10293 .loc 1 1221 3 is_stmt 1 view .LVU3214 + 10294 .LVL791: +1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10295 .loc 1 1224 3 view .LVU3215 +1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10296 .loc 1 1226 3 view .LVU3216 + 10297 0006 0C29 cmp r1, #12 + 10298 0008 7FD8 bhi .L694 + 10299 000a DFE801F0 tbb [pc, r1] + 10300 .L680: + 10301 000e 07 .byte (.L683-.L680)/2 + 10302 000f 7E .byte (.L694-.L680)/2 + 10303 0010 7E .byte (.L694-.L680)/2 + 10304 0011 7E .byte (.L694-.L680)/2 + ARM GAS /tmp/ccGFzgX3.s page 365 + + + 10305 0012 45 .byte (.L682-.L680)/2 + 10306 0013 7E .byte (.L694-.L680)/2 + 10307 0014 7E .byte (.L694-.L680)/2 + 10308 0015 7E .byte (.L694-.L680)/2 + 10309 0016 4E .byte (.L681-.L680)/2 + 10310 0017 7E .byte (.L694-.L680)/2 + 10311 0018 7E .byte (.L694-.L680)/2 + 10312 0019 7E .byte (.L694-.L680)/2 + 10313 001a 57 .byte (.L679-.L680)/2 + 10314 001b 00 .p2align 1 + 10315 .L683: +1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + 10316 .loc 1 1231 7 view .LVU3217 + 10317 001c 0268 ldr r2, [r0] + 10318 001e D368 ldr r3, [r2, #12] + 10319 0020 23F40073 bic r3, r3, #512 + 10320 0024 D360 str r3, [r2, #12] +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 10321 .loc 1 1232 7 view .LVU3218 +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 10322 .loc 1 1232 13 is_stmt 0 view .LVU3219 + 10323 0026 406A ldr r0, [r0, #36] + 10324 .LVL792: +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 10325 .loc 1 1232 13 view .LVU3220 + 10326 0028 FFF7FEFF bl HAL_DMA_Abort_IT + 10327 .LVL793: +1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10328 .loc 1 1233 7 is_stmt 1 view .LVU3221 +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10329 .loc 1 1265 3 view .LVU3222 + 10330 .L684: +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10331 .loc 1 1268 5 view .LVU3223 + 10332 002c 0022 movs r2, #0 + 10333 002e 2946 mov r1, r5 + 10334 0030 2068 ldr r0, [r4] + 10335 0032 FFF7FEFF bl TIM_CCxChannelCmd + 10336 .LVL794: +1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10337 .loc 1 1270 5 view .LVU3224 +1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10338 .loc 1 1270 9 is_stmt 0 view .LVU3225 + 10339 0036 2368 ldr r3, [r4] +1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10340 .loc 1 1270 8 view .LVU3226 + 10341 0038 3549 ldr r1, .L696 + 10342 003a 364A ldr r2, .L696+4 + 10343 003c 9342 cmp r3, r2 + 10344 003e 18BF it ne + 10345 0040 8B42 cmpne r3, r1 + 10346 0042 0DD1 bne .L685 +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10347 .loc 1 1273 7 is_stmt 1 view .LVU3227 +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10348 .loc 1 1273 7 view .LVU3228 + 10349 0044 196A ldr r1, [r3, #32] + ARM GAS /tmp/ccGFzgX3.s page 366 + + + 10350 0046 41F21112 movw r2, #4369 + 10351 004a 1142 tst r1, r2 + 10352 004c 08D1 bne .L685 +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10353 .loc 1 1273 7 discriminator 1 view .LVU3229 + 10354 004e 196A ldr r1, [r3, #32] + 10355 0050 40F24442 movw r2, #1092 + 10356 0054 1142 tst r1, r2 + 10357 0056 03D1 bne .L685 +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10358 .loc 1 1273 7 discriminator 3 view .LVU3230 + 10359 0058 5A6C ldr r2, [r3, #68] + 10360 005a 22F40042 bic r2, r2, #32768 + 10361 005e 5A64 str r2, [r3, #68] + 10362 .L685: +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10363 .loc 1 1273 7 discriminator 5 view .LVU3231 +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10364 .loc 1 1277 5 view .LVU3232 +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10365 .loc 1 1277 5 view .LVU3233 + 10366 0060 2368 ldr r3, [r4] + 10367 0062 196A ldr r1, [r3, #32] + 10368 0064 41F21112 movw r2, #4369 + 10369 0068 1142 tst r1, r2 + 10370 006a 08D1 bne .L686 +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10371 .loc 1 1277 5 discriminator 1 view .LVU3234 + 10372 006c 196A ldr r1, [r3, #32] + 10373 006e 40F24442 movw r2, #1092 + 10374 0072 1142 tst r1, r2 + 10375 0074 03D1 bne .L686 +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10376 .loc 1 1277 5 discriminator 3 view .LVU3235 + 10377 0076 1A68 ldr r2, [r3] + 10378 0078 22F00102 bic r2, r2, #1 + 10379 007c 1A60 str r2, [r3] + 10380 .L686: +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10381 .loc 1 1277 5 discriminator 5 view .LVU3236 +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10382 .loc 1 1280 5 view .LVU3237 + 10383 007e 102D cmp r5, #16 + 10384 0080 3ED8 bhi .L687 + 10385 0082 DFE805F0 tbb [pc, r5] + 10386 .L689: + 10387 0086 24 .byte (.L693-.L689)/2 + 10388 0087 3D .byte (.L687-.L689)/2 + 10389 0088 3D .byte (.L687-.L689)/2 + 10390 0089 3D .byte (.L687-.L689)/2 + 10391 008a 29 .byte (.L692-.L689)/2 + 10392 008b 3D .byte (.L687-.L689)/2 + 10393 008c 3D .byte (.L687-.L689)/2 + 10394 008d 3D .byte (.L687-.L689)/2 + 10395 008e 2E .byte (.L691-.L689)/2 + 10396 008f 3D .byte (.L687-.L689)/2 + 10397 0090 3D .byte (.L687-.L689)/2 + ARM GAS /tmp/ccGFzgX3.s page 367 + + + 10398 0091 3D .byte (.L687-.L689)/2 + 10399 0092 33 .byte (.L690-.L689)/2 + 10400 0093 3D .byte (.L687-.L689)/2 + 10401 0094 3D .byte (.L687-.L689)/2 + 10402 0095 3D .byte (.L687-.L689)/2 + 10403 0096 38 .byte (.L688-.L689)/2 + 10404 .LVL795: + 10405 0097 00 .p2align 1 + 10406 .L682: +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + 10407 .loc 1 1239 7 view .LVU3238 + 10408 0098 0268 ldr r2, [r0] + 10409 009a D368 ldr r3, [r2, #12] + 10410 009c 23F48063 bic r3, r3, #1024 + 10411 00a0 D360 str r3, [r2, #12] +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 10412 .loc 1 1240 7 view .LVU3239 +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 10413 .loc 1 1240 13 is_stmt 0 view .LVU3240 + 10414 00a2 806A ldr r0, [r0, #40] + 10415 .LVL796: +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 10416 .loc 1 1240 13 view .LVU3241 + 10417 00a4 FFF7FEFF bl HAL_DMA_Abort_IT + 10418 .LVL797: +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10419 .loc 1 1241 7 is_stmt 1 view .LVU3242 +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10420 .loc 1 1265 3 view .LVU3243 + 10421 00a8 C0E7 b .L684 + 10422 .LVL798: + 10423 .L681: +1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + 10424 .loc 1 1247 7 view .LVU3244 + 10425 00aa 0268 ldr r2, [r0] + 10426 00ac D368 ldr r3, [r2, #12] + 10427 00ae 23F40063 bic r3, r3, #2048 + 10428 00b2 D360 str r3, [r2, #12] +1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 10429 .loc 1 1248 7 view .LVU3245 +1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 10430 .loc 1 1248 13 is_stmt 0 view .LVU3246 + 10431 00b4 C06A ldr r0, [r0, #44] + 10432 .LVL799: +1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 10433 .loc 1 1248 13 view .LVU3247 + 10434 00b6 FFF7FEFF bl HAL_DMA_Abort_IT + 10435 .LVL800: +1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10436 .loc 1 1249 7 is_stmt 1 view .LVU3248 +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10437 .loc 1 1265 3 view .LVU3249 + 10438 00ba B7E7 b .L684 + 10439 .LVL801: + 10440 .L679: +1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + 10441 .loc 1 1255 7 view .LVU3250 + ARM GAS /tmp/ccGFzgX3.s page 368 + + + 10442 00bc 0268 ldr r2, [r0] + 10443 00be D368 ldr r3, [r2, #12] + 10444 00c0 23F48053 bic r3, r3, #4096 + 10445 00c4 D360 str r3, [r2, #12] +1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 10446 .loc 1 1256 7 view .LVU3251 +1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 10447 .loc 1 1256 13 is_stmt 0 view .LVU3252 + 10448 00c6 006B ldr r0, [r0, #48] + 10449 .LVL802: +1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 10450 .loc 1 1256 13 view .LVU3253 + 10451 00c8 FFF7FEFF bl HAL_DMA_Abort_IT + 10452 .LVL803: +1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10453 .loc 1 1257 7 is_stmt 1 view .LVU3254 +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10454 .loc 1 1265 3 view .LVU3255 + 10455 00cc AEE7 b .L684 + 10456 .L693: +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10457 .loc 1 1280 5 is_stmt 0 discriminator 1 view .LVU3256 + 10458 00ce 0123 movs r3, #1 + 10459 00d0 84F83E30 strb r3, [r4, #62] + 10460 00d4 0020 movs r0, #0 + 10461 00d6 19E0 b .L678 + 10462 .L692: +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10463 .loc 1 1280 5 discriminator 3 view .LVU3257 + 10464 00d8 0123 movs r3, #1 + 10465 00da 84F83F30 strb r3, [r4, #63] + 10466 00de 0020 movs r0, #0 + 10467 00e0 14E0 b .L678 + 10468 .L691: +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10469 .loc 1 1280 5 discriminator 6 view .LVU3258 + 10470 00e2 0123 movs r3, #1 + 10471 00e4 84F84030 strb r3, [r4, #64] + 10472 00e8 0020 movs r0, #0 + 10473 00ea 0FE0 b .L678 + 10474 .L690: +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10475 .loc 1 1280 5 discriminator 9 view .LVU3259 + 10476 00ec 0123 movs r3, #1 + 10477 00ee 84F84130 strb r3, [r4, #65] + 10478 00f2 0020 movs r0, #0 + 10479 00f4 0AE0 b .L678 + 10480 .L688: +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10481 .loc 1 1280 5 discriminator 12 view .LVU3260 + 10482 00f6 0123 movs r3, #1 + 10483 00f8 84F84230 strb r3, [r4, #66] + 10484 00fc 0020 movs r0, #0 + 10485 00fe 05E0 b .L678 + 10486 .L687: +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10487 .loc 1 1280 5 discriminator 13 view .LVU3261 + ARM GAS /tmp/ccGFzgX3.s page 369 + + + 10488 0100 0123 movs r3, #1 + 10489 0102 84F84330 strb r3, [r4, #67] + 10490 0106 0020 movs r0, #0 + 10491 0108 00E0 b .L678 + 10492 .LVL804: + 10493 .L694: +1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10494 .loc 1 1226 3 view .LVU3262 + 10495 010a 0120 movs r0, #1 + 10496 .LVL805: + 10497 .L678: +1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10498 .loc 1 1284 3 is_stmt 1 view .LVU3263 +1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10499 .loc 1 1285 1 is_stmt 0 view .LVU3264 + 10500 010c 38BD pop {r3, r4, r5, pc} + 10501 .LVL806: + 10502 .L697: +1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10503 .loc 1 1285 1 view .LVU3265 + 10504 010e 00BF .align 2 + 10505 .L696: + 10506 0110 00000140 .word 1073807360 + 10507 0114 00040140 .word 1073808384 + 10508 .cfi_endproc + 10509 .LFE160: + 10511 .section .text.HAL_TIM_PWM_Start,"ax",%progbits + 10512 .align 1 + 10513 .global HAL_TIM_PWM_Start + 10514 .syntax unified + 10515 .thumb + 10516 .thumb_func + 10518 HAL_TIM_PWM_Start: + 10519 .LVL807: + 10520 .LFB165: +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 10521 .loc 1 1464 1 is_stmt 1 view -0 + 10522 .cfi_startproc + 10523 @ args = 0, pretend = 0, frame = 0 + 10524 @ frame_needed = 0, uses_anonymous_args = 0 +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 10525 .loc 1 1464 1 is_stmt 0 view .LVU3267 + 10526 0000 10B5 push {r4, lr} + 10527 .LCFI92: + 10528 .cfi_def_cfa_offset 8 + 10529 .cfi_offset 4, -8 + 10530 .cfi_offset 14, -4 + 10531 0002 0446 mov r4, r0 +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10532 .loc 1 1465 3 is_stmt 1 view .LVU3268 +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10533 .loc 1 1468 3 view .LVU3269 +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10534 .loc 1 1471 3 view .LVU3270 + 10535 0004 1029 cmp r1, #16 + 10536 0006 3CD8 bhi .L699 + 10537 0008 DFE801F0 tbb [pc, r1] + ARM GAS /tmp/ccGFzgX3.s page 370 + + + 10538 .L701: + 10539 000c 09 .byte (.L705-.L701)/2 + 10540 000d 3B .byte (.L699-.L701)/2 + 10541 000e 3B .byte (.L699-.L701)/2 + 10542 000f 3B .byte (.L699-.L701)/2 + 10543 0010 1F .byte (.L704-.L701)/2 + 10544 0011 3B .byte (.L699-.L701)/2 + 10545 0012 3B .byte (.L699-.L701)/2 + 10546 0013 3B .byte (.L699-.L701)/2 + 10547 0014 26 .byte (.L703-.L701)/2 + 10548 0015 3B .byte (.L699-.L701)/2 + 10549 0016 3B .byte (.L699-.L701)/2 + 10550 0017 3B .byte (.L699-.L701)/2 + 10551 0018 2D .byte (.L702-.L701)/2 + 10552 0019 3B .byte (.L699-.L701)/2 + 10553 001a 3B .byte (.L699-.L701)/2 + 10554 001b 3B .byte (.L699-.L701)/2 + 10555 001c 34 .byte (.L700-.L701)/2 + 10556 001d 00 .p2align 1 + 10557 .L705: +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10558 .loc 1 1471 7 is_stmt 0 discriminator 1 view .LVU3271 + 10559 001e 90F83E30 ldrb r3, [r0, #62] @ zero_extendqisi2 + 10560 0022 DBB2 uxtb r3, r3 +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10561 .loc 1 1471 44 discriminator 1 view .LVU3272 + 10562 0024 013B subs r3, r3, #1 + 10563 0026 18BF it ne + 10564 0028 0123 movne r3, #1 + 10565 .L706: +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10566 .loc 1 1471 6 discriminator 20 view .LVU3273 + 10567 002a 002B cmp r3, #0 + 10568 002c 40F08980 bne .L719 +1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10569 .loc 1 1477 3 is_stmt 1 view .LVU3274 + 10570 0030 1029 cmp r1, #16 + 10571 0032 74D8 bhi .L708 + 10572 0034 DFE801F0 tbb [pc, r1] + 10573 .L710: + 10574 0038 2C .byte (.L714-.L710)/2 + 10575 0039 73 .byte (.L708-.L710)/2 + 10576 003a 73 .byte (.L708-.L710)/2 + 10577 003b 73 .byte (.L708-.L710)/2 + 10578 003c 63 .byte (.L713-.L710)/2 + 10579 003d 73 .byte (.L708-.L710)/2 + 10580 003e 73 .byte (.L708-.L710)/2 + 10581 003f 73 .byte (.L708-.L710)/2 + 10582 0040 67 .byte (.L712-.L710)/2 + 10583 0041 73 .byte (.L708-.L710)/2 + 10584 0042 73 .byte (.L708-.L710)/2 + 10585 0043 73 .byte (.L708-.L710)/2 + 10586 0044 6B .byte (.L711-.L710)/2 + 10587 0045 73 .byte (.L708-.L710)/2 + 10588 0046 73 .byte (.L708-.L710)/2 + 10589 0047 73 .byte (.L708-.L710)/2 + 10590 0048 6F .byte (.L709-.L710)/2 + ARM GAS /tmp/ccGFzgX3.s page 371 + + + 10591 0049 00 .p2align 1 + 10592 .L704: +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10593 .loc 1 1471 7 is_stmt 0 discriminator 4 view .LVU3275 + 10594 004a 90F83F30 ldrb r3, [r0, #63] @ zero_extendqisi2 + 10595 004e DBB2 uxtb r3, r3 +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10596 .loc 1 1471 44 discriminator 4 view .LVU3276 + 10597 0050 013B subs r3, r3, #1 + 10598 0052 18BF it ne + 10599 0054 0123 movne r3, #1 + 10600 0056 E8E7 b .L706 + 10601 .L703: +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10602 .loc 1 1471 7 discriminator 7 view .LVU3277 + 10603 0058 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 10604 005c DBB2 uxtb r3, r3 +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10605 .loc 1 1471 44 discriminator 7 view .LVU3278 + 10606 005e 013B subs r3, r3, #1 + 10607 0060 18BF it ne + 10608 0062 0123 movne r3, #1 + 10609 0064 E1E7 b .L706 + 10610 .L702: +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10611 .loc 1 1471 7 discriminator 10 view .LVU3279 + 10612 0066 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 10613 006a DBB2 uxtb r3, r3 +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10614 .loc 1 1471 44 discriminator 10 view .LVU3280 + 10615 006c 013B subs r3, r3, #1 + 10616 006e 18BF it ne + 10617 0070 0123 movne r3, #1 + 10618 0072 DAE7 b .L706 + 10619 .L700: +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10620 .loc 1 1471 7 discriminator 13 view .LVU3281 + 10621 0074 90F84230 ldrb r3, [r0, #66] @ zero_extendqisi2 + 10622 0078 DBB2 uxtb r3, r3 +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10623 .loc 1 1471 44 discriminator 13 view .LVU3282 + 10624 007a 013B subs r3, r3, #1 + 10625 007c 18BF it ne + 10626 007e 0123 movne r3, #1 + 10627 0080 D3E7 b .L706 + 10628 .L699: +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10629 .loc 1 1471 7 discriminator 14 view .LVU3283 + 10630 0082 90F84330 ldrb r3, [r0, #67] @ zero_extendqisi2 + 10631 0086 DBB2 uxtb r3, r3 +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10632 .loc 1 1471 44 discriminator 14 view .LVU3284 + 10633 0088 013B subs r3, r3, #1 + 10634 008a 18BF it ne + 10635 008c 0123 movne r3, #1 + 10636 008e CCE7 b .L706 + 10637 .L714: + ARM GAS /tmp/ccGFzgX3.s page 372 + + +1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10638 .loc 1 1477 3 discriminator 1 view .LVU3285 + 10639 0090 0223 movs r3, #2 + 10640 0092 84F83E30 strb r3, [r4, #62] + 10641 .L715: +1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10642 .loc 1 1480 3 is_stmt 1 view .LVU3286 + 10643 0096 0122 movs r2, #1 + 10644 0098 2068 ldr r0, [r4] + 10645 .LVL808: +1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10646 .loc 1 1480 3 is_stmt 0 view .LVU3287 + 10647 009a FFF7FEFF bl TIM_CCxChannelCmd + 10648 .LVL809: +1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10649 .loc 1 1482 3 is_stmt 1 view .LVU3288 +1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10650 .loc 1 1482 7 is_stmt 0 view .LVU3289 + 10651 009e 2368 ldr r3, [r4] +1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10652 .loc 1 1482 6 view .LVU3290 + 10653 00a0 2A49 ldr r1, .L722 + 10654 00a2 2B4A ldr r2, .L722+4 + 10655 00a4 9342 cmp r3, r2 + 10656 00a6 18BF it ne + 10657 00a8 8B42 cmpne r3, r1 + 10658 00aa 03D1 bne .L716 +1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10659 .loc 1 1485 5 is_stmt 1 view .LVU3291 + 10660 00ac 5A6C ldr r2, [r3, #68] + 10661 00ae 42F40042 orr r2, r2, #32768 + 10662 00b2 5A64 str r2, [r3, #68] + 10663 .L716: +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10664 .loc 1 1489 3 view .LVU3292 +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10665 .loc 1 1489 7 is_stmt 0 view .LVU3293 + 10666 00b4 2368 ldr r3, [r4] +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10667 .loc 1 1489 6 view .LVU3294 + 10668 00b6 254A ldr r2, .L722 + 10669 00b8 B3F1804F cmp r3, #1073741824 + 10670 00bc 18BF it ne + 10671 00be 9342 cmpne r3, r2 + 10672 00c0 31D0 beq .L717 +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10673 .loc 1 1489 7 discriminator 1 view .LVU3295 + 10674 00c2 A2F57C42 sub r2, r2, #64512 + 10675 00c6 9342 cmp r3, r2 + 10676 00c8 2DD0 beq .L717 +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10677 .loc 1 1489 7 discriminator 2 view .LVU3296 + 10678 00ca 02F58062 add r2, r2, #1024 + 10679 00ce 9342 cmp r3, r2 + 10680 00d0 29D0 beq .L717 +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10681 .loc 1 1489 7 discriminator 3 view .LVU3297 + ARM GAS /tmp/ccGFzgX3.s page 373 + + + 10682 00d2 02F58062 add r2, r2, #1024 + 10683 00d6 9342 cmp r3, r2 + 10684 00d8 25D0 beq .L717 +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10685 .loc 1 1489 7 discriminator 4 view .LVU3298 + 10686 00da 02F57842 add r2, r2, #63488 + 10687 00de 9342 cmp r3, r2 + 10688 00e0 21D0 beq .L717 +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10689 .loc 1 1489 7 discriminator 5 view .LVU3299 + 10690 00e2 02F57052 add r2, r2, #15360 + 10691 00e6 9342 cmp r3, r2 + 10692 00e8 1DD0 beq .L717 +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10693 .loc 1 1489 7 discriminator 6 view .LVU3300 + 10694 00ea A2F59432 sub r2, r2, #75776 + 10695 00ee 9342 cmp r3, r2 + 10696 00f0 19D0 beq .L717 +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10697 .loc 1 1499 5 is_stmt 1 view .LVU3301 + 10698 00f2 1A68 ldr r2, [r3] + 10699 00f4 42F00102 orr r2, r2, #1 + 10700 00f8 1A60 str r2, [r3] +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10701 .loc 1 1503 10 is_stmt 0 view .LVU3302 + 10702 00fa 0020 movs r0, #0 + 10703 00fc 22E0 b .L707 + 10704 .LVL810: + 10705 .L713: +1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10706 .loc 1 1477 3 discriminator 3 view .LVU3303 + 10707 00fe 0223 movs r3, #2 + 10708 0100 84F83F30 strb r3, [r4, #63] + 10709 0104 C7E7 b .L715 + 10710 .L712: +1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10711 .loc 1 1477 3 discriminator 6 view .LVU3304 + 10712 0106 0223 movs r3, #2 + 10713 0108 84F84030 strb r3, [r4, #64] + 10714 010c C3E7 b .L715 + 10715 .L711: +1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10716 .loc 1 1477 3 discriminator 9 view .LVU3305 + 10717 010e 0223 movs r3, #2 + 10718 0110 84F84130 strb r3, [r4, #65] + 10719 0114 BFE7 b .L715 + 10720 .L709: +1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10721 .loc 1 1477 3 discriminator 12 view .LVU3306 + 10722 0116 0223 movs r3, #2 + 10723 0118 84F84230 strb r3, [r4, #66] + 10724 011c BBE7 b .L715 + 10725 .L708: +1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10726 .loc 1 1477 3 discriminator 13 view .LVU3307 + 10727 011e 0223 movs r3, #2 + 10728 0120 84F84330 strb r3, [r4, #67] + ARM GAS /tmp/ccGFzgX3.s page 374 + + + 10729 0124 B7E7 b .L715 + 10730 .LVL811: + 10731 .L717: +1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 10732 .loc 1 1491 5 is_stmt 1 view .LVU3308 +1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 10733 .loc 1 1491 29 is_stmt 0 view .LVU3309 + 10734 0126 9968 ldr r1, [r3, #8] +1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 10735 .loc 1 1491 13 view .LVU3310 + 10736 0128 0A4A ldr r2, .L722+8 + 10737 012a 0A40 ands r2, r2, r1 + 10738 .LVL812: +1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10739 .loc 1 1492 5 is_stmt 1 view .LVU3311 +1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10740 .loc 1 1492 8 is_stmt 0 view .LVU3312 + 10741 012c 062A cmp r2, #6 + 10742 012e 18BF it ne + 10743 0130 B2F5803F cmpne r2, #65536 + 10744 0134 07D0 beq .L720 +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10745 .loc 1 1494 7 is_stmt 1 view .LVU3313 + 10746 0136 1A68 ldr r2, [r3] + 10747 .LVL813: +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10748 .loc 1 1494 7 is_stmt 0 view .LVU3314 + 10749 0138 42F00102 orr r2, r2, #1 + 10750 013c 1A60 str r2, [r3] +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10751 .loc 1 1503 10 view .LVU3315 + 10752 013e 0020 movs r0, #0 + 10753 0140 00E0 b .L707 + 10754 .LVL814: + 10755 .L719: +1473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10756 .loc 1 1473 12 view .LVU3316 + 10757 0142 0120 movs r0, #1 + 10758 .LVL815: + 10759 .L707: +1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10760 .loc 1 1504 1 view .LVU3317 + 10761 0144 10BD pop {r4, pc} + 10762 .LVL816: + 10763 .L720: +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10764 .loc 1 1503 10 view .LVU3318 + 10765 0146 0020 movs r0, #0 + 10766 0148 FCE7 b .L707 + 10767 .L723: + 10768 014a 00BF .align 2 + 10769 .L722: + 10770 014c 00000140 .word 1073807360 + 10771 0150 00040140 .word 1073808384 + 10772 0154 07000100 .word 65543 + 10773 .cfi_endproc + 10774 .LFE165: + ARM GAS /tmp/ccGFzgX3.s page 375 + + + 10776 .section .text.HAL_TIM_PWM_Stop,"ax",%progbits + 10777 .align 1 + 10778 .global HAL_TIM_PWM_Stop + 10779 .syntax unified + 10780 .thumb + 10781 .thumb_func + 10783 HAL_TIM_PWM_Stop: + 10784 .LVL817: + 10785 .LFB166: +1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 10786 .loc 1 1520 1 is_stmt 1 view -0 + 10787 .cfi_startproc + 10788 @ args = 0, pretend = 0, frame = 0 + 10789 @ frame_needed = 0, uses_anonymous_args = 0 +1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 10790 .loc 1 1520 1 is_stmt 0 view .LVU3320 + 10791 0000 38B5 push {r3, r4, r5, lr} + 10792 .LCFI93: + 10793 .cfi_def_cfa_offset 16 + 10794 .cfi_offset 3, -16 + 10795 .cfi_offset 4, -12 + 10796 .cfi_offset 5, -8 + 10797 .cfi_offset 14, -4 + 10798 0002 0446 mov r4, r0 + 10799 0004 0D46 mov r5, r1 +1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10800 .loc 1 1522 3 is_stmt 1 view .LVU3321 +1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10801 .loc 1 1525 3 view .LVU3322 + 10802 0006 0022 movs r2, #0 + 10803 0008 0068 ldr r0, [r0] + 10804 .LVL818: +1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10805 .loc 1 1525 3 is_stmt 0 view .LVU3323 + 10806 000a FFF7FEFF bl TIM_CCxChannelCmd + 10807 .LVL819: +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10808 .loc 1 1527 3 is_stmt 1 view .LVU3324 +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10809 .loc 1 1527 7 is_stmt 0 view .LVU3325 + 10810 000e 2368 ldr r3, [r4] +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10811 .loc 1 1527 6 view .LVU3326 + 10812 0010 2449 ldr r1, .L736 + 10813 0012 254A ldr r2, .L736+4 + 10814 0014 9342 cmp r3, r2 + 10815 0016 18BF it ne + 10816 0018 8B42 cmpne r3, r1 + 10817 001a 0DD1 bne .L725 +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10818 .loc 1 1530 5 is_stmt 1 view .LVU3327 +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10819 .loc 1 1530 5 view .LVU3328 + 10820 001c 196A ldr r1, [r3, #32] + 10821 001e 41F21112 movw r2, #4369 + 10822 0022 1142 tst r1, r2 + 10823 0024 08D1 bne .L725 + ARM GAS /tmp/ccGFzgX3.s page 376 + + +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10824 .loc 1 1530 5 discriminator 1 view .LVU3329 + 10825 0026 196A ldr r1, [r3, #32] + 10826 0028 40F24442 movw r2, #1092 + 10827 002c 1142 tst r1, r2 + 10828 002e 03D1 bne .L725 +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10829 .loc 1 1530 5 discriminator 3 view .LVU3330 + 10830 0030 5A6C ldr r2, [r3, #68] + 10831 0032 22F40042 bic r2, r2, #32768 + 10832 0036 5A64 str r2, [r3, #68] + 10833 .L725: +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10834 .loc 1 1530 5 discriminator 5 view .LVU3331 +1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10835 .loc 1 1534 3 view .LVU3332 +1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10836 .loc 1 1534 3 view .LVU3333 + 10837 0038 2368 ldr r3, [r4] + 10838 003a 196A ldr r1, [r3, #32] + 10839 003c 41F21112 movw r2, #4369 + 10840 0040 1142 tst r1, r2 + 10841 0042 08D1 bne .L726 +1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10842 .loc 1 1534 3 discriminator 1 view .LVU3334 + 10843 0044 196A ldr r1, [r3, #32] + 10844 0046 40F24442 movw r2, #1092 + 10845 004a 1142 tst r1, r2 + 10846 004c 03D1 bne .L726 +1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10847 .loc 1 1534 3 discriminator 3 view .LVU3335 + 10848 004e 1A68 ldr r2, [r3] + 10849 0050 22F00102 bic r2, r2, #1 + 10850 0054 1A60 str r2, [r3] + 10851 .L726: +1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10852 .loc 1 1534 3 discriminator 5 view .LVU3336 +1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10853 .loc 1 1537 3 view .LVU3337 + 10854 0056 102D cmp r5, #16 + 10855 0058 1FD8 bhi .L727 + 10856 005a DFE805F0 tbb [pc, r5] + 10857 .L729: + 10858 005e 09 .byte (.L733-.L729)/2 + 10859 005f 1E .byte (.L727-.L729)/2 + 10860 0060 1E .byte (.L727-.L729)/2 + 10861 0061 1E .byte (.L727-.L729)/2 + 10862 0062 0E .byte (.L732-.L729)/2 + 10863 0063 1E .byte (.L727-.L729)/2 + 10864 0064 1E .byte (.L727-.L729)/2 + 10865 0065 1E .byte (.L727-.L729)/2 + 10866 0066 12 .byte (.L731-.L729)/2 + 10867 0067 1E .byte (.L727-.L729)/2 + 10868 0068 1E .byte (.L727-.L729)/2 + 10869 0069 1E .byte (.L727-.L729)/2 + 10870 006a 16 .byte (.L730-.L729)/2 + 10871 006b 1E .byte (.L727-.L729)/2 + ARM GAS /tmp/ccGFzgX3.s page 377 + + + 10872 006c 1E .byte (.L727-.L729)/2 + 10873 006d 1E .byte (.L727-.L729)/2 + 10874 006e 1A .byte (.L728-.L729)/2 + 10875 006f 00 .p2align 1 + 10876 .L733: +1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10877 .loc 1 1537 3 is_stmt 0 discriminator 1 view .LVU3338 + 10878 0070 0123 movs r3, #1 + 10879 0072 84F83E30 strb r3, [r4, #62] + 10880 .L734: +1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 10881 .loc 1 1540 3 is_stmt 1 view .LVU3339 +1541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10882 .loc 1 1541 1 is_stmt 0 view .LVU3340 + 10883 0076 0020 movs r0, #0 + 10884 0078 38BD pop {r3, r4, r5, pc} + 10885 .LVL820: + 10886 .L732: +1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10887 .loc 1 1537 3 discriminator 3 view .LVU3341 + 10888 007a 0123 movs r3, #1 + 10889 007c 84F83F30 strb r3, [r4, #63] + 10890 0080 F9E7 b .L734 + 10891 .L731: +1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10892 .loc 1 1537 3 discriminator 6 view .LVU3342 + 10893 0082 0123 movs r3, #1 + 10894 0084 84F84030 strb r3, [r4, #64] + 10895 0088 F5E7 b .L734 + 10896 .L730: +1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10897 .loc 1 1537 3 discriminator 9 view .LVU3343 + 10898 008a 0123 movs r3, #1 + 10899 008c 84F84130 strb r3, [r4, #65] + 10900 0090 F1E7 b .L734 + 10901 .L728: +1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10902 .loc 1 1537 3 discriminator 12 view .LVU3344 + 10903 0092 0123 movs r3, #1 + 10904 0094 84F84230 strb r3, [r4, #66] + 10905 0098 EDE7 b .L734 + 10906 .L727: +1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10907 .loc 1 1537 3 discriminator 13 view .LVU3345 + 10908 009a 0123 movs r3, #1 + 10909 009c 84F84330 strb r3, [r4, #67] + 10910 00a0 E9E7 b .L734 + 10911 .L737: + 10912 00a2 00BF .align 2 + 10913 .L736: + 10914 00a4 00000140 .word 1073807360 + 10915 00a8 00040140 .word 1073808384 + 10916 .cfi_endproc + 10917 .LFE166: + 10919 .section .text.HAL_TIM_PWM_Start_IT,"ax",%progbits + 10920 .align 1 + 10921 .global HAL_TIM_PWM_Start_IT + ARM GAS /tmp/ccGFzgX3.s page 378 + + + 10922 .syntax unified + 10923 .thumb + 10924 .thumb_func + 10926 HAL_TIM_PWM_Start_IT: + 10927 .LVL821: + 10928 .LFB167: +1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 10929 .loc 1 1555 1 is_stmt 1 view -0 + 10930 .cfi_startproc + 10931 @ args = 0, pretend = 0, frame = 0 + 10932 @ frame_needed = 0, uses_anonymous_args = 0 +1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 10933 .loc 1 1555 1 is_stmt 0 view .LVU3347 + 10934 0000 10B5 push {r4, lr} + 10935 .LCFI94: + 10936 .cfi_def_cfa_offset 8 + 10937 .cfi_offset 4, -8 + 10938 .cfi_offset 14, -4 + 10939 0002 0446 mov r4, r0 +1556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 10940 .loc 1 1556 3 is_stmt 1 view .LVU3348 + 10941 .LVL822: +1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10942 .loc 1 1557 3 view .LVU3349 +1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10943 .loc 1 1560 3 view .LVU3350 +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10944 .loc 1 1563 3 view .LVU3351 + 10945 0004 1029 cmp r1, #16 + 10946 0006 3DD8 bhi .L739 + 10947 0008 DFE801F0 tbb [pc, r1] + 10948 .L741: + 10949 000c 09 .byte (.L745-.L741)/2 + 10950 000d 3C .byte (.L739-.L741)/2 + 10951 000e 3C .byte (.L739-.L741)/2 + 10952 000f 3C .byte (.L739-.L741)/2 + 10953 0010 20 .byte (.L744-.L741)/2 + 10954 0011 3C .byte (.L739-.L741)/2 + 10955 0012 3C .byte (.L739-.L741)/2 + 10956 0013 3C .byte (.L739-.L741)/2 + 10957 0014 27 .byte (.L743-.L741)/2 + 10958 0015 3C .byte (.L739-.L741)/2 + 10959 0016 3C .byte (.L739-.L741)/2 + 10960 0017 3C .byte (.L739-.L741)/2 + 10961 0018 2E .byte (.L742-.L741)/2 + 10962 0019 3C .byte (.L739-.L741)/2 + 10963 001a 3C .byte (.L739-.L741)/2 + 10964 001b 3C .byte (.L739-.L741)/2 + 10965 001c 35 .byte (.L740-.L741)/2 + 10966 001d 00 .p2align 1 + 10967 .L745: +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10968 .loc 1 1563 7 is_stmt 0 discriminator 1 view .LVU3352 + 10969 001e 90F83E30 ldrb r3, [r0, #62] @ zero_extendqisi2 + 10970 0022 DBB2 uxtb r3, r3 +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10971 .loc 1 1563 44 discriminator 1 view .LVU3353 + ARM GAS /tmp/ccGFzgX3.s page 379 + + + 10972 0024 013B subs r3, r3, #1 + 10973 0026 18BF it ne + 10974 0028 0123 movne r3, #1 + 10975 .L746: +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 10976 .loc 1 1563 6 discriminator 20 view .LVU3354 + 10977 002a 002B cmp r3, #0 + 10978 002c 40F0BE80 bne .L764 +1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 10979 .loc 1 1569 3 is_stmt 1 view .LVU3355 + 10980 0030 1029 cmp r1, #16 + 10981 0032 00F28A80 bhi .L748 + 10982 0036 DFE801F0 tbb [pc, r1] + 10983 .L750: + 10984 003a 2C .byte (.L754-.L750)/2 + 10985 003b 88 .byte (.L748-.L750)/2 + 10986 003c 88 .byte (.L748-.L750)/2 + 10987 003d 88 .byte (.L748-.L750)/2 + 10988 003e 68 .byte (.L753-.L750)/2 + 10989 003f 88 .byte (.L748-.L750)/2 + 10990 0040 88 .byte (.L748-.L750)/2 + 10991 0041 88 .byte (.L748-.L750)/2 + 10992 0042 71 .byte (.L752-.L750)/2 + 10993 0043 88 .byte (.L748-.L750)/2 + 10994 0044 88 .byte (.L748-.L750)/2 + 10995 0045 88 .byte (.L748-.L750)/2 + 10996 0046 7A .byte (.L751-.L750)/2 + 10997 0047 88 .byte (.L748-.L750)/2 + 10998 0048 88 .byte (.L748-.L750)/2 + 10999 0049 88 .byte (.L748-.L750)/2 + 11000 004a 83 .byte (.L749-.L750)/2 + 11001 004b 00 .p2align 1 + 11002 .L744: +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11003 .loc 1 1563 7 is_stmt 0 discriminator 4 view .LVU3356 + 11004 004c 90F83F30 ldrb r3, [r0, #63] @ zero_extendqisi2 + 11005 0050 DBB2 uxtb r3, r3 +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11006 .loc 1 1563 44 discriminator 4 view .LVU3357 + 11007 0052 013B subs r3, r3, #1 + 11008 0054 18BF it ne + 11009 0056 0123 movne r3, #1 + 11010 0058 E7E7 b .L746 + 11011 .L743: +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11012 .loc 1 1563 7 discriminator 7 view .LVU3358 + 11013 005a 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 11014 005e DBB2 uxtb r3, r3 +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11015 .loc 1 1563 44 discriminator 7 view .LVU3359 + 11016 0060 013B subs r3, r3, #1 + 11017 0062 18BF it ne + 11018 0064 0123 movne r3, #1 + 11019 0066 E0E7 b .L746 + 11020 .L742: +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11021 .loc 1 1563 7 discriminator 10 view .LVU3360 + ARM GAS /tmp/ccGFzgX3.s page 380 + + + 11022 0068 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 11023 006c DBB2 uxtb r3, r3 +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11024 .loc 1 1563 44 discriminator 10 view .LVU3361 + 11025 006e 013B subs r3, r3, #1 + 11026 0070 18BF it ne + 11027 0072 0123 movne r3, #1 + 11028 0074 D9E7 b .L746 + 11029 .L740: +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11030 .loc 1 1563 7 discriminator 13 view .LVU3362 + 11031 0076 90F84230 ldrb r3, [r0, #66] @ zero_extendqisi2 + 11032 007a DBB2 uxtb r3, r3 +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11033 .loc 1 1563 44 discriminator 13 view .LVU3363 + 11034 007c 013B subs r3, r3, #1 + 11035 007e 18BF it ne + 11036 0080 0123 movne r3, #1 + 11037 0082 D2E7 b .L746 + 11038 .L739: +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11039 .loc 1 1563 7 discriminator 14 view .LVU3364 + 11040 0084 90F84330 ldrb r3, [r0, #67] @ zero_extendqisi2 + 11041 0088 DBB2 uxtb r3, r3 +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11042 .loc 1 1563 44 discriminator 14 view .LVU3365 + 11043 008a 013B subs r3, r3, #1 + 11044 008c 18BF it ne + 11045 008e 0123 movne r3, #1 + 11046 0090 CBE7 b .L746 + 11047 .L754: +1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11048 .loc 1 1569 3 discriminator 1 view .LVU3366 + 11049 0092 0223 movs r3, #2 + 11050 0094 84F83E30 strb r3, [r4, #62] +1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11051 .loc 1 1571 3 is_stmt 1 view .LVU3367 + 11052 .L755: +1576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 11053 .loc 1 1576 7 view .LVU3368 + 11054 0098 2268 ldr r2, [r4] + 11055 009a D368 ldr r3, [r2, #12] + 11056 009c 43F00203 orr r3, r3, #2 + 11057 00a0 D360 str r3, [r2, #12] +1577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11058 .loc 1 1577 7 view .LVU3369 +1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11059 .loc 1 1606 3 view .LVU3370 + 11060 .L760: +1609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11061 .loc 1 1609 5 view .LVU3371 + 11062 00a2 0122 movs r2, #1 + 11063 00a4 2068 ldr r0, [r4] + 11064 .LVL823: +1609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11065 .loc 1 1609 5 is_stmt 0 view .LVU3372 + 11066 00a6 FFF7FEFF bl TIM_CCxChannelCmd + ARM GAS /tmp/ccGFzgX3.s page 381 + + + 11067 .LVL824: +1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11068 .loc 1 1611 5 is_stmt 1 view .LVU3373 +1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11069 .loc 1 1611 9 is_stmt 0 view .LVU3374 + 11070 00aa 2368 ldr r3, [r4] +1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11071 .loc 1 1611 8 view .LVU3375 + 11072 00ac 4249 ldr r1, .L772 + 11073 00ae 434A ldr r2, .L772+4 + 11074 00b0 9342 cmp r3, r2 + 11075 00b2 18BF it ne + 11076 00b4 8B42 cmpne r3, r1 + 11077 00b6 03D1 bne .L761 +1614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11078 .loc 1 1614 7 is_stmt 1 view .LVU3376 + 11079 00b8 5A6C ldr r2, [r3, #68] + 11080 00ba 42F40042 orr r2, r2, #32768 + 11081 00be 5A64 str r2, [r3, #68] + 11082 .L761: +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11083 .loc 1 1618 5 view .LVU3377 +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11084 .loc 1 1618 9 is_stmt 0 view .LVU3378 + 11085 00c0 2368 ldr r3, [r4] +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11086 .loc 1 1618 8 view .LVU3379 + 11087 00c2 3D4A ldr r2, .L772 + 11088 00c4 B3F1804F cmp r3, #1073741824 + 11089 00c8 18BF it ne + 11090 00ca 9342 cmpne r3, r2 + 11091 00cc 60D0 beq .L762 +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11092 .loc 1 1618 9 discriminator 1 view .LVU3380 + 11093 00ce A2F57C42 sub r2, r2, #64512 + 11094 00d2 9342 cmp r3, r2 + 11095 00d4 5CD0 beq .L762 +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11096 .loc 1 1618 9 discriminator 2 view .LVU3381 + 11097 00d6 02F58062 add r2, r2, #1024 + 11098 00da 9342 cmp r3, r2 + 11099 00dc 58D0 beq .L762 +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11100 .loc 1 1618 9 discriminator 3 view .LVU3382 + 11101 00de 02F58062 add r2, r2, #1024 + 11102 00e2 9342 cmp r3, r2 + 11103 00e4 54D0 beq .L762 +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11104 .loc 1 1618 9 discriminator 4 view .LVU3383 + 11105 00e6 02F57842 add r2, r2, #63488 + 11106 00ea 9342 cmp r3, r2 + 11107 00ec 50D0 beq .L762 +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11108 .loc 1 1618 9 discriminator 5 view .LVU3384 + 11109 00ee 02F57052 add r2, r2, #15360 + 11110 00f2 9342 cmp r3, r2 + 11111 00f4 4CD0 beq .L762 + ARM GAS /tmp/ccGFzgX3.s page 382 + + +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11112 .loc 1 1618 9 discriminator 6 view .LVU3385 + 11113 00f6 A2F59432 sub r2, r2, #75776 + 11114 00fa 9342 cmp r3, r2 + 11115 00fc 48D0 beq .L762 +1628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11116 .loc 1 1628 7 is_stmt 1 view .LVU3386 + 11117 00fe 1A68 ldr r2, [r3] + 11118 0100 42F00102 orr r2, r2, #1 + 11119 0104 1A60 str r2, [r3] + 11120 0106 0020 movs r0, #0 + 11121 0108 51E0 b .L747 + 11122 .LVL825: + 11123 .L753: +1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11124 .loc 1 1569 3 is_stmt 0 discriminator 3 view .LVU3387 + 11125 010a 0223 movs r3, #2 + 11126 010c 84F83F30 strb r3, [r4, #63] +1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11127 .loc 1 1571 3 is_stmt 1 view .LVU3388 + 11128 .L756: +1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 11129 .loc 1 1583 7 view .LVU3389 + 11130 0110 2268 ldr r2, [r4] + 11131 0112 D368 ldr r3, [r2, #12] + 11132 0114 43F00403 orr r3, r3, #4 + 11133 0118 D360 str r3, [r2, #12] +1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11134 .loc 1 1584 7 view .LVU3390 +1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11135 .loc 1 1606 3 view .LVU3391 + 11136 011a C2E7 b .L760 + 11137 .L752: +1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11138 .loc 1 1569 3 is_stmt 0 discriminator 6 view .LVU3392 + 11139 011c 0223 movs r3, #2 + 11140 011e 84F84030 strb r3, [r4, #64] +1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11141 .loc 1 1571 3 is_stmt 1 view .LVU3393 + 11142 .L757: +1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 11143 .loc 1 1590 7 view .LVU3394 + 11144 0122 2268 ldr r2, [r4] + 11145 0124 D368 ldr r3, [r2, #12] + 11146 0126 43F00803 orr r3, r3, #8 + 11147 012a D360 str r3, [r2, #12] +1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11148 .loc 1 1591 7 view .LVU3395 +1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11149 .loc 1 1606 3 view .LVU3396 + 11150 012c B9E7 b .L760 + 11151 .L751: +1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11152 .loc 1 1569 3 is_stmt 0 discriminator 9 view .LVU3397 + 11153 012e 0223 movs r3, #2 + 11154 0130 84F84130 strb r3, [r4, #65] +1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 383 + + + 11155 .loc 1 1571 3 is_stmt 1 view .LVU3398 + 11156 .L758: +1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 11157 .loc 1 1597 7 view .LVU3399 + 11158 0134 2268 ldr r2, [r4] + 11159 0136 D368 ldr r3, [r2, #12] + 11160 0138 43F01003 orr r3, r3, #16 + 11161 013c D360 str r3, [r2, #12] +1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11162 .loc 1 1598 7 view .LVU3400 +1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11163 .loc 1 1606 3 view .LVU3401 + 11164 013e B0E7 b .L760 + 11165 .L749: +1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11166 .loc 1 1569 3 is_stmt 0 discriminator 12 view .LVU3402 + 11167 0140 0223 movs r3, #2 + 11168 0142 84F84230 strb r3, [r4, #66] +1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11169 .loc 1 1571 3 is_stmt 1 view .LVU3403 +1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11170 .loc 1 1569 3 is_stmt 0 discriminator 12 view .LVU3404 + 11171 0146 0120 movs r0, #1 + 11172 .LVL826: +1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11173 .loc 1 1569 3 discriminator 12 view .LVU3405 + 11174 0148 31E0 b .L747 + 11175 .LVL827: + 11176 .L748: +1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11177 .loc 1 1569 3 discriminator 13 view .LVU3406 + 11178 014a 0223 movs r3, #2 + 11179 014c 84F84330 strb r3, [r4, #67] +1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11180 .loc 1 1571 3 is_stmt 1 view .LVU3407 + 11181 0150 0C29 cmp r1, #12 + 11182 0152 2DD8 bhi .L765 + 11183 0154 01A3 adr r3, .L759 + 11184 0156 53F821F0 ldr pc, [r3, r1, lsl #2] + 11185 015a 00BF .p2align 2 + 11186 .L759: + 11187 015c 99000000 .word .L755+1 + 11188 0160 B1010000 .word .L765+1 + 11189 0164 B1010000 .word .L765+1 + 11190 0168 B1010000 .word .L765+1 + 11191 016c 11010000 .word .L756+1 + 11192 0170 B1010000 .word .L765+1 + 11193 0174 B1010000 .word .L765+1 + 11194 0178 B1010000 .word .L765+1 + 11195 017c 23010000 .word .L757+1 + 11196 0180 B1010000 .word .L765+1 + 11197 0184 B1010000 .word .L765+1 + 11198 0188 B1010000 .word .L765+1 + 11199 018c 35010000 .word .L758+1 + 11200 .LVL828: + 11201 .p2align 1 + 11202 .L762: + ARM GAS /tmp/ccGFzgX3.s page 384 + + +1620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 11203 .loc 1 1620 7 view .LVU3408 +1620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 11204 .loc 1 1620 31 is_stmt 0 view .LVU3409 + 11205 0190 9968 ldr r1, [r3, #8] +1620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 11206 .loc 1 1620 15 view .LVU3410 + 11207 0192 0B4A ldr r2, .L772+8 + 11208 0194 0A40 ands r2, r2, r1 + 11209 .LVL829: +1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11210 .loc 1 1621 7 is_stmt 1 view .LVU3411 +1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11211 .loc 1 1621 10 is_stmt 0 view .LVU3412 + 11212 0196 062A cmp r2, #6 + 11213 0198 18BF it ne + 11214 019a B2F5803F cmpne r2, #65536 + 11215 019e 09D0 beq .L766 +1623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11216 .loc 1 1623 9 is_stmt 1 view .LVU3413 + 11217 01a0 1A68 ldr r2, [r3] + 11218 .LVL830: +1623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11219 .loc 1 1623 9 is_stmt 0 view .LVU3414 + 11220 01a2 42F00102 orr r2, r2, #1 + 11221 01a6 1A60 str r2, [r3] + 11222 01a8 0020 movs r0, #0 + 11223 01aa 00E0 b .L747 + 11224 .LVL831: + 11225 .L764: +1565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11226 .loc 1 1565 12 view .LVU3415 + 11227 01ac 0120 movs r0, #1 + 11228 .LVL832: + 11229 .L747: +1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11230 .loc 1 1634 1 view .LVU3416 + 11231 01ae 10BD pop {r4, pc} + 11232 .LVL833: + 11233 .L765: +1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11234 .loc 1 1571 3 view .LVU3417 + 11235 01b0 0120 movs r0, #1 + 11236 .LVL834: +1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11237 .loc 1 1571 3 view .LVU3418 + 11238 01b2 FCE7 b .L747 + 11239 .LVL835: + 11240 .L766: +1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11241 .loc 1 1571 3 view .LVU3419 + 11242 01b4 0020 movs r0, #0 + 11243 01b6 FAE7 b .L747 + 11244 .L773: + 11245 .align 2 + 11246 .L772: + 11247 01b8 00000140 .word 1073807360 + ARM GAS /tmp/ccGFzgX3.s page 385 + + + 11248 01bc 00040140 .word 1073808384 + 11249 01c0 07000100 .word 65543 + 11250 .cfi_endproc + 11251 .LFE167: + 11253 .section .text.HAL_TIM_PWM_Stop_IT,"ax",%progbits + 11254 .align 1 + 11255 .global HAL_TIM_PWM_Stop_IT + 11256 .syntax unified + 11257 .thumb + 11258 .thumb_func + 11260 HAL_TIM_PWM_Stop_IT: + 11261 .LVL836: + 11262 .LFB168: +1648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 11263 .loc 1 1648 1 is_stmt 1 view -0 + 11264 .cfi_startproc + 11265 @ args = 0, pretend = 0, frame = 0 + 11266 @ frame_needed = 0, uses_anonymous_args = 0 +1648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 11267 .loc 1 1648 1 is_stmt 0 view .LVU3421 + 11268 0000 38B5 push {r3, r4, r5, lr} + 11269 .LCFI95: + 11270 .cfi_def_cfa_offset 16 + 11271 .cfi_offset 3, -16 + 11272 .cfi_offset 4, -12 + 11273 .cfi_offset 5, -8 + 11274 .cfi_offset 14, -4 + 11275 0002 0546 mov r5, r0 + 11276 0004 0C46 mov r4, r1 +1649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11277 .loc 1 1649 3 is_stmt 1 view .LVU3422 + 11278 .LVL837: +1652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11279 .loc 1 1652 3 view .LVU3423 +1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11280 .loc 1 1654 3 view .LVU3424 + 11281 0006 0C29 cmp r1, #12 + 11282 0008 73D8 bhi .L791 + 11283 000a DFE801F0 tbb [pc, r1] + 11284 .L777: + 11285 000e 07 .byte (.L780-.L777)/2 + 11286 000f 72 .byte (.L791-.L777)/2 + 11287 0010 72 .byte (.L791-.L777)/2 + 11288 0011 72 .byte (.L791-.L777)/2 + 11289 0012 42 .byte (.L779-.L777)/2 + 11290 0013 72 .byte (.L791-.L777)/2 + 11291 0014 72 .byte (.L791-.L777)/2 + 11292 0015 72 .byte (.L791-.L777)/2 + 11293 0016 48 .byte (.L778-.L777)/2 + 11294 0017 72 .byte (.L791-.L777)/2 + 11295 0018 72 .byte (.L791-.L777)/2 + 11296 0019 72 .byte (.L791-.L777)/2 + 11297 001a 4E .byte (.L776-.L777)/2 + 11298 001b 00 .p2align 1 + 11299 .L780: +1659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 11300 .loc 1 1659 7 view .LVU3425 + ARM GAS /tmp/ccGFzgX3.s page 386 + + + 11301 001c 0268 ldr r2, [r0] + 11302 001e D368 ldr r3, [r2, #12] + 11303 0020 23F00203 bic r3, r3, #2 + 11304 0024 D360 str r3, [r2, #12] +1660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11305 .loc 1 1660 7 view .LVU3426 +1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11306 .loc 1 1689 3 view .LVU3427 + 11307 .L781: +1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11308 .loc 1 1692 5 view .LVU3428 + 11309 0026 0022 movs r2, #0 + 11310 0028 2146 mov r1, r4 + 11311 .LVL838: +1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11312 .loc 1 1692 5 is_stmt 0 view .LVU3429 + 11313 002a 2868 ldr r0, [r5] + 11314 .LVL839: +1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11315 .loc 1 1692 5 view .LVU3430 + 11316 002c FFF7FEFF bl TIM_CCxChannelCmd + 11317 .LVL840: +1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11318 .loc 1 1694 5 is_stmt 1 view .LVU3431 +1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11319 .loc 1 1694 9 is_stmt 0 view .LVU3432 + 11320 0030 2B68 ldr r3, [r5] +1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11321 .loc 1 1694 8 view .LVU3433 + 11322 0032 3149 ldr r1, .L793 + 11323 0034 314A ldr r2, .L793+4 + 11324 0036 9342 cmp r3, r2 + 11325 0038 18BF it ne + 11326 003a 8B42 cmpne r3, r1 + 11327 003c 0DD1 bne .L782 +1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11328 .loc 1 1697 7 is_stmt 1 view .LVU3434 +1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11329 .loc 1 1697 7 view .LVU3435 + 11330 003e 196A ldr r1, [r3, #32] + 11331 0040 41F21112 movw r2, #4369 + 11332 0044 1142 tst r1, r2 + 11333 0046 08D1 bne .L782 +1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11334 .loc 1 1697 7 discriminator 1 view .LVU3436 + 11335 0048 196A ldr r1, [r3, #32] + 11336 004a 40F24442 movw r2, #1092 + 11337 004e 1142 tst r1, r2 + 11338 0050 03D1 bne .L782 +1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11339 .loc 1 1697 7 discriminator 3 view .LVU3437 + 11340 0052 5A6C ldr r2, [r3, #68] + 11341 0054 22F40042 bic r2, r2, #32768 + 11342 0058 5A64 str r2, [r3, #68] + 11343 .L782: +1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11344 .loc 1 1697 7 discriminator 5 view .LVU3438 + ARM GAS /tmp/ccGFzgX3.s page 387 + + +1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11345 .loc 1 1701 5 view .LVU3439 +1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11346 .loc 1 1701 5 view .LVU3440 + 11347 005a 2B68 ldr r3, [r5] + 11348 005c 196A ldr r1, [r3, #32] + 11349 005e 41F21112 movw r2, #4369 + 11350 0062 1142 tst r1, r2 + 11351 0064 08D1 bne .L783 +1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11352 .loc 1 1701 5 discriminator 1 view .LVU3441 + 11353 0066 196A ldr r1, [r3, #32] + 11354 0068 40F24442 movw r2, #1092 + 11355 006c 1142 tst r1, r2 + 11356 006e 03D1 bne .L783 +1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11357 .loc 1 1701 5 discriminator 3 view .LVU3442 + 11358 0070 1A68 ldr r2, [r3] + 11359 0072 22F00102 bic r2, r2, #1 + 11360 0076 1A60 str r2, [r3] + 11361 .L783: +1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11362 .loc 1 1701 5 discriminator 5 view .LVU3443 +1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11363 .loc 1 1704 5 view .LVU3444 + 11364 0078 102C cmp r4, #16 + 11365 007a 35D8 bhi .L784 + 11366 007c DFE804F0 tbb [pc, r4] + 11367 .L786: + 11368 0080 1B .byte (.L790-.L786)/2 + 11369 0081 34 .byte (.L784-.L786)/2 + 11370 0082 34 .byte (.L784-.L786)/2 + 11371 0083 34 .byte (.L784-.L786)/2 + 11372 0084 20 .byte (.L789-.L786)/2 + 11373 0085 34 .byte (.L784-.L786)/2 + 11374 0086 34 .byte (.L784-.L786)/2 + 11375 0087 34 .byte (.L784-.L786)/2 + 11376 0088 25 .byte (.L788-.L786)/2 + 11377 0089 34 .byte (.L784-.L786)/2 + 11378 008a 34 .byte (.L784-.L786)/2 + 11379 008b 34 .byte (.L784-.L786)/2 + 11380 008c 2A .byte (.L787-.L786)/2 + 11381 008d 34 .byte (.L784-.L786)/2 + 11382 008e 34 .byte (.L784-.L786)/2 + 11383 008f 34 .byte (.L784-.L786)/2 + 11384 0090 2F .byte (.L785-.L786)/2 + 11385 .LVL841: + 11386 0091 00 .p2align 1 + 11387 .L779: +1666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 11388 .loc 1 1666 7 view .LVU3445 + 11389 0092 0268 ldr r2, [r0] + 11390 0094 D368 ldr r3, [r2, #12] + 11391 0096 23F00403 bic r3, r3, #4 + 11392 009a D360 str r3, [r2, #12] +1667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11393 .loc 1 1667 7 view .LVU3446 + ARM GAS /tmp/ccGFzgX3.s page 388 + + +1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11394 .loc 1 1689 3 view .LVU3447 + 11395 009c C3E7 b .L781 + 11396 .L778: +1673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 11397 .loc 1 1673 7 view .LVU3448 + 11398 009e 0268 ldr r2, [r0] + 11399 00a0 D368 ldr r3, [r2, #12] + 11400 00a2 23F00803 bic r3, r3, #8 + 11401 00a6 D360 str r3, [r2, #12] +1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11402 .loc 1 1674 7 view .LVU3449 +1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11403 .loc 1 1689 3 view .LVU3450 + 11404 00a8 BDE7 b .L781 + 11405 .L776: +1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 11406 .loc 1 1680 7 view .LVU3451 + 11407 00aa 0268 ldr r2, [r0] + 11408 00ac D368 ldr r3, [r2, #12] + 11409 00ae 23F01003 bic r3, r3, #16 + 11410 00b2 D360 str r3, [r2, #12] +1681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11411 .loc 1 1681 7 view .LVU3452 +1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11412 .loc 1 1689 3 view .LVU3453 + 11413 00b4 B7E7 b .L781 + 11414 .LVL842: + 11415 .L790: +1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11416 .loc 1 1704 5 is_stmt 0 discriminator 1 view .LVU3454 + 11417 00b6 0123 movs r3, #1 + 11418 00b8 85F83E30 strb r3, [r5, #62] + 11419 00bc 0020 movs r0, #0 + 11420 00be 19E0 b .L775 + 11421 .L789: +1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11422 .loc 1 1704 5 discriminator 3 view .LVU3455 + 11423 00c0 0123 movs r3, #1 + 11424 00c2 85F83F30 strb r3, [r5, #63] + 11425 00c6 0020 movs r0, #0 + 11426 00c8 14E0 b .L775 + 11427 .L788: +1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11428 .loc 1 1704 5 discriminator 6 view .LVU3456 + 11429 00ca 0123 movs r3, #1 + 11430 00cc 85F84030 strb r3, [r5, #64] + 11431 00d0 0020 movs r0, #0 + 11432 00d2 0FE0 b .L775 + 11433 .L787: +1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11434 .loc 1 1704 5 discriminator 9 view .LVU3457 + 11435 00d4 0123 movs r3, #1 + 11436 00d6 85F84130 strb r3, [r5, #65] + 11437 00da 0020 movs r0, #0 + 11438 00dc 0AE0 b .L775 + 11439 .L785: + ARM GAS /tmp/ccGFzgX3.s page 389 + + +1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11440 .loc 1 1704 5 discriminator 12 view .LVU3458 + 11441 00de 0123 movs r3, #1 + 11442 00e0 85F84230 strb r3, [r5, #66] + 11443 00e4 0020 movs r0, #0 + 11444 00e6 05E0 b .L775 + 11445 .L784: +1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11446 .loc 1 1704 5 discriminator 13 view .LVU3459 + 11447 00e8 0123 movs r3, #1 + 11448 00ea 85F84330 strb r3, [r5, #67] + 11449 00ee 0020 movs r0, #0 + 11450 00f0 00E0 b .L775 + 11451 .LVL843: + 11452 .L791: +1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11453 .loc 1 1654 3 view .LVU3460 + 11454 00f2 0120 movs r0, #1 + 11455 .LVL844: + 11456 .L775: +1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11457 .loc 1 1708 3 is_stmt 1 view .LVU3461 +1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11458 .loc 1 1709 1 is_stmt 0 view .LVU3462 + 11459 00f4 38BD pop {r3, r4, r5, pc} + 11460 .LVL845: + 11461 .L794: +1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11462 .loc 1 1709 1 view .LVU3463 + 11463 00f6 00BF .align 2 + 11464 .L793: + 11465 00f8 00000140 .word 1073807360 + 11466 00fc 00040140 .word 1073808384 + 11467 .cfi_endproc + 11468 .LFE168: + 11470 .section .text.HAL_TIM_PWM_Start_DMA,"ax",%progbits + 11471 .align 1 + 11472 .global HAL_TIM_PWM_Start_DMA + 11473 .syntax unified + 11474 .thumb + 11475 .thumb_func + 11477 HAL_TIM_PWM_Start_DMA: + 11478 .LVL846: + 11479 .LFB169: +1726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 11480 .loc 1 1726 1 is_stmt 1 view -0 + 11481 .cfi_startproc + 11482 @ args = 0, pretend = 0, frame = 0 + 11483 @ frame_needed = 0, uses_anonymous_args = 0 +1726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 11484 .loc 1 1726 1 is_stmt 0 view .LVU3465 + 11485 0000 38B5 push {r3, r4, r5, lr} + 11486 .LCFI96: + 11487 .cfi_def_cfa_offset 16 + 11488 .cfi_offset 3, -16 + 11489 .cfi_offset 4, -12 + 11490 .cfi_offset 5, -8 + ARM GAS /tmp/ccGFzgX3.s page 390 + + + 11491 .cfi_offset 14, -4 + 11492 0002 0546 mov r5, r0 + 11493 0004 0C46 mov r4, r1 + 11494 0006 1146 mov r1, r2 + 11495 .LVL847: +1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 11496 .loc 1 1727 3 is_stmt 1 view .LVU3466 +1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11497 .loc 1 1728 3 view .LVU3467 +1731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11498 .loc 1 1731 3 view .LVU3468 +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11499 .loc 1 1734 3 view .LVU3469 + 11500 0008 102C cmp r4, #16 + 11501 000a 41D8 bhi .L796 + 11502 000c DFE804F0 tbb [pc, r4] + 11503 .LVL848: + 11504 .L798: + 11505 0010 09 .byte (.L802-.L798)/2 + 11506 0011 40 .byte (.L796-.L798)/2 + 11507 0012 40 .byte (.L796-.L798)/2 + 11508 0013 40 .byte (.L796-.L798)/2 + 11509 0014 20 .byte (.L801-.L798)/2 + 11510 0015 40 .byte (.L796-.L798)/2 + 11511 0016 40 .byte (.L796-.L798)/2 + 11512 0017 40 .byte (.L796-.L798)/2 + 11513 0018 28 .byte (.L800-.L798)/2 + 11514 0019 40 .byte (.L796-.L798)/2 + 11515 001a 40 .byte (.L796-.L798)/2 + 11516 001b 40 .byte (.L796-.L798)/2 + 11517 001c 30 .byte (.L799-.L798)/2 + 11518 001d 40 .byte (.L796-.L798)/2 + 11519 001e 40 .byte (.L796-.L798)/2 + 11520 001f 40 .byte (.L796-.L798)/2 + 11521 0020 38 .byte (.L797-.L798)/2 + 11522 0021 00 .p2align 1 + 11523 .L802: +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11524 .loc 1 1734 7 is_stmt 0 discriminator 1 view .LVU3470 + 11525 0022 90F83E00 ldrb r0, [r0, #62] @ zero_extendqisi2 + 11526 .LVL849: +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11527 .loc 1 1734 7 discriminator 1 view .LVU3471 + 11528 0026 C0B2 uxtb r0, r0 +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11529 .loc 1 1734 44 discriminator 1 view .LVU3472 + 11530 0028 0228 cmp r0, #2 + 11531 002a 14BF ite ne + 11532 002c 0020 movne r0, #0 + 11533 002e 0120 moveq r0, #1 + 11534 .L803: +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11535 .loc 1 1734 6 discriminator 20 view .LVU3473 + 11536 0030 0028 cmp r0, #0 + 11537 0032 40F05581 bne .L829 +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11538 .loc 1 1738 8 is_stmt 1 view .LVU3474 + ARM GAS /tmp/ccGFzgX3.s page 391 + + + 11539 0036 102C cmp r4, #16 + 11540 0038 77D8 bhi .L805 + 11541 003a DFE804F0 tbb [pc, r4] + 11542 .L807: + 11543 003e 31 .byte (.L811-.L807)/2 + 11544 003f 76 .byte (.L805-.L807)/2 + 11545 0040 76 .byte (.L805-.L807)/2 + 11546 0041 76 .byte (.L805-.L807)/2 + 11547 0042 56 .byte (.L810-.L807)/2 + 11548 0043 76 .byte (.L805-.L807)/2 + 11549 0044 76 .byte (.L805-.L807)/2 + 11550 0045 76 .byte (.L805-.L807)/2 + 11551 0046 5E .byte (.L809-.L807)/2 + 11552 0047 76 .byte (.L805-.L807)/2 + 11553 0048 76 .byte (.L805-.L807)/2 + 11554 0049 76 .byte (.L805-.L807)/2 + 11555 004a 66 .byte (.L808-.L807)/2 + 11556 004b 76 .byte (.L805-.L807)/2 + 11557 004c 76 .byte (.L805-.L807)/2 + 11558 004d 76 .byte (.L805-.L807)/2 + 11559 004e 6E .byte (.L806-.L807)/2 + 11560 .LVL850: + 11561 004f 00 .p2align 1 + 11562 .L801: +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11563 .loc 1 1734 7 is_stmt 0 discriminator 4 view .LVU3475 + 11564 0050 90F83F00 ldrb r0, [r0, #63] @ zero_extendqisi2 + 11565 .LVL851: +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11566 .loc 1 1734 7 discriminator 4 view .LVU3476 + 11567 0054 C0B2 uxtb r0, r0 +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11568 .loc 1 1734 44 discriminator 4 view .LVU3477 + 11569 0056 0228 cmp r0, #2 + 11570 0058 14BF ite ne + 11571 005a 0020 movne r0, #0 + 11572 005c 0120 moveq r0, #1 + 11573 005e E7E7 b .L803 + 11574 .LVL852: + 11575 .L800: +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11576 .loc 1 1734 7 discriminator 7 view .LVU3478 + 11577 0060 90F84000 ldrb r0, [r0, #64] @ zero_extendqisi2 + 11578 .LVL853: +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11579 .loc 1 1734 7 discriminator 7 view .LVU3479 + 11580 0064 C0B2 uxtb r0, r0 +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11581 .loc 1 1734 44 discriminator 7 view .LVU3480 + 11582 0066 0228 cmp r0, #2 + 11583 0068 14BF ite ne + 11584 006a 0020 movne r0, #0 + 11585 006c 0120 moveq r0, #1 + 11586 006e DFE7 b .L803 + 11587 .LVL854: + 11588 .L799: +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 392 + + + 11589 .loc 1 1734 7 discriminator 10 view .LVU3481 + 11590 0070 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 11591 .LVL855: +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11592 .loc 1 1734 7 discriminator 10 view .LVU3482 + 11593 0074 C0B2 uxtb r0, r0 +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11594 .loc 1 1734 44 discriminator 10 view .LVU3483 + 11595 0076 0228 cmp r0, #2 + 11596 0078 14BF ite ne + 11597 007a 0020 movne r0, #0 + 11598 007c 0120 moveq r0, #1 + 11599 007e D7E7 b .L803 + 11600 .LVL856: + 11601 .L797: +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11602 .loc 1 1734 7 discriminator 13 view .LVU3484 + 11603 0080 90F84200 ldrb r0, [r0, #66] @ zero_extendqisi2 + 11604 .LVL857: +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11605 .loc 1 1734 7 discriminator 13 view .LVU3485 + 11606 0084 C0B2 uxtb r0, r0 +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11607 .loc 1 1734 44 discriminator 13 view .LVU3486 + 11608 0086 0228 cmp r0, #2 + 11609 0088 14BF ite ne + 11610 008a 0020 movne r0, #0 + 11611 008c 0120 moveq r0, #1 + 11612 008e CFE7 b .L803 + 11613 .LVL858: + 11614 .L796: +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11615 .loc 1 1734 7 discriminator 14 view .LVU3487 + 11616 0090 90F84300 ldrb r0, [r0, #67] @ zero_extendqisi2 + 11617 .LVL859: +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11618 .loc 1 1734 7 discriminator 14 view .LVU3488 + 11619 0094 C0B2 uxtb r0, r0 +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11620 .loc 1 1734 44 discriminator 14 view .LVU3489 + 11621 0096 0228 cmp r0, #2 + 11622 0098 14BF ite ne + 11623 009a 0020 movne r0, #0 + 11624 009c 0120 moveq r0, #1 + 11625 009e C7E7 b .L803 + 11626 .L811: +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11627 .loc 1 1738 12 discriminator 1 view .LVU3490 + 11628 00a0 95F83E20 ldrb r2, [r5, #62] @ zero_extendqisi2 + 11629 00a4 D2B2 uxtb r2, r2 +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11630 .loc 1 1738 49 discriminator 1 view .LVU3491 + 11631 00a6 012A cmp r2, #1 + 11632 00a8 14BF ite ne + 11633 00aa 0022 movne r2, #0 + 11634 00ac 0122 moveq r2, #1 + 11635 .L812: + ARM GAS /tmp/ccGFzgX3.s page 393 + + +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11636 .loc 1 1738 11 discriminator 20 view .LVU3492 + 11637 00ae 002A cmp r2, #0 + 11638 00b0 00F01881 beq .L830 +1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11639 .loc 1 1740 5 is_stmt 1 view .LVU3493 +1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11640 .loc 1 1740 8 is_stmt 0 view .LVU3494 + 11641 00b4 002B cmp r3, #0 + 11642 00b6 18BF it ne + 11643 00b8 0029 cmpne r1, #0 + 11644 00ba 00F01581 beq .L831 +1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11645 .loc 1 1746 7 is_stmt 1 view .LVU3495 + 11646 00be 102C cmp r4, #16 + 11647 00c0 00F2DE80 bhi .L813 + 11648 00c4 DFE814F0 tbh [pc, r4, lsl #1] + 11649 .L815: + 11650 00c8 3900 .2byte (.L819-.L815)/2 + 11651 00ca DC00 .2byte (.L813-.L815)/2 + 11652 00cc DC00 .2byte (.L813-.L815)/2 + 11653 00ce DC00 .2byte (.L813-.L815)/2 + 11654 00d0 8C00 .2byte (.L818-.L815)/2 + 11655 00d2 DC00 .2byte (.L813-.L815)/2 + 11656 00d4 DC00 .2byte (.L813-.L815)/2 + 11657 00d6 DC00 .2byte (.L813-.L815)/2 + 11658 00d8 A500 .2byte (.L817-.L815)/2 + 11659 00da DC00 .2byte (.L813-.L815)/2 + 11660 00dc DC00 .2byte (.L813-.L815)/2 + 11661 00de DC00 .2byte (.L813-.L815)/2 + 11662 00e0 BE00 .2byte (.L816-.L815)/2 + 11663 00e2 DC00 .2byte (.L813-.L815)/2 + 11664 00e4 DC00 .2byte (.L813-.L815)/2 + 11665 00e6 DC00 .2byte (.L813-.L815)/2 + 11666 00e8 D700 .2byte (.L814-.L815)/2 + 11667 .p2align 1 + 11668 .L810: +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11669 .loc 1 1738 12 is_stmt 0 discriminator 4 view .LVU3496 + 11670 00ea 95F83F20 ldrb r2, [r5, #63] @ zero_extendqisi2 + 11671 00ee D2B2 uxtb r2, r2 +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11672 .loc 1 1738 49 discriminator 4 view .LVU3497 + 11673 00f0 012A cmp r2, #1 + 11674 00f2 14BF ite ne + 11675 00f4 0022 movne r2, #0 + 11676 00f6 0122 moveq r2, #1 + 11677 00f8 D9E7 b .L812 + 11678 .L809: +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11679 .loc 1 1738 12 discriminator 7 view .LVU3498 + 11680 00fa 95F84020 ldrb r2, [r5, #64] @ zero_extendqisi2 + 11681 00fe D2B2 uxtb r2, r2 +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11682 .loc 1 1738 49 discriminator 7 view .LVU3499 + 11683 0100 012A cmp r2, #1 + 11684 0102 14BF ite ne + ARM GAS /tmp/ccGFzgX3.s page 394 + + + 11685 0104 0022 movne r2, #0 + 11686 0106 0122 moveq r2, #1 + 11687 0108 D1E7 b .L812 + 11688 .L808: +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11689 .loc 1 1738 12 discriminator 10 view .LVU3500 + 11690 010a 95F84120 ldrb r2, [r5, #65] @ zero_extendqisi2 + 11691 010e D2B2 uxtb r2, r2 +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11692 .loc 1 1738 49 discriminator 10 view .LVU3501 + 11693 0110 012A cmp r2, #1 + 11694 0112 14BF ite ne + 11695 0114 0022 movne r2, #0 + 11696 0116 0122 moveq r2, #1 + 11697 0118 C9E7 b .L812 + 11698 .L806: +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11699 .loc 1 1738 12 discriminator 13 view .LVU3502 + 11700 011a 95F84220 ldrb r2, [r5, #66] @ zero_extendqisi2 + 11701 011e D2B2 uxtb r2, r2 +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11702 .loc 1 1738 49 discriminator 13 view .LVU3503 + 11703 0120 012A cmp r2, #1 + 11704 0122 14BF ite ne + 11705 0124 0022 movne r2, #0 + 11706 0126 0122 moveq r2, #1 + 11707 0128 C1E7 b .L812 + 11708 .L805: +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11709 .loc 1 1738 12 discriminator 14 view .LVU3504 + 11710 012a 95F84320 ldrb r2, [r5, #67] @ zero_extendqisi2 + 11711 012e D2B2 uxtb r2, r2 +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11712 .loc 1 1738 49 discriminator 14 view .LVU3505 + 11713 0130 012A cmp r2, #1 + 11714 0132 14BF ite ne + 11715 0134 0022 movne r2, #0 + 11716 0136 0122 moveq r2, #1 + 11717 0138 B9E7 b .L812 + 11718 .L819: +1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11719 .loc 1 1746 7 discriminator 1 view .LVU3506 + 11720 013a 0222 movs r2, #2 + 11721 013c 85F83E20 strb r2, [r5, #62] +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11722 .loc 1 1754 3 is_stmt 1 view .LVU3507 + 11723 .L820: +1759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 11724 .loc 1 1759 7 view .LVU3508 +1759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 11725 .loc 1 1759 17 is_stmt 0 view .LVU3509 + 11726 0140 6A6A ldr r2, [r5, #36] +1759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 11727 .loc 1 1759 52 view .LVU3510 + 11728 0142 7048 ldr r0, .L843 + 11729 0144 D063 str r0, [r2, #60] +1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 395 + + + 11730 .loc 1 1760 7 is_stmt 1 view .LVU3511 +1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11731 .loc 1 1760 17 is_stmt 0 view .LVU3512 + 11732 0146 6A6A ldr r2, [r5, #36] +1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11733 .loc 1 1760 56 view .LVU3513 + 11734 0148 6F48 ldr r0, .L843+4 + 11735 014a 1064 str r0, [r2, #64] +1763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11736 .loc 1 1763 7 is_stmt 1 view .LVU3514 +1763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11737 .loc 1 1763 17 is_stmt 0 view .LVU3515 + 11738 014c 6A6A ldr r2, [r5, #36] +1763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11739 .loc 1 1763 53 view .LVU3516 + 11740 014e 6F48 ldr r0, .L843+8 + 11741 0150 D064 str r0, [r2, #76] +1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 11742 .loc 1 1766 7 is_stmt 1 view .LVU3517 +1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 11743 .loc 1 1766 88 is_stmt 0 view .LVU3518 + 11744 0152 2A68 ldr r2, [r5] +1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 11745 .loc 1 1766 11 view .LVU3519 + 11746 0154 3432 adds r2, r2, #52 + 11747 0156 686A ldr r0, [r5, #36] + 11748 0158 FFF7FEFF bl HAL_DMA_Start_IT + 11749 .LVL860: +1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 11750 .loc 1 1766 10 discriminator 1 view .LVU3520 + 11751 015c 0028 cmp r0, #0 + 11752 015e 40F0C780 bne .L833 +1774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 11753 .loc 1 1774 7 is_stmt 1 view .LVU3521 + 11754 0162 2A68 ldr r2, [r5] + 11755 0164 D368 ldr r3, [r2, #12] + 11756 0166 43F40073 orr r3, r3, #512 + 11757 016a D360 str r3, [r2, #12] +1775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11758 .loc 1 1775 7 view .LVU3522 +1846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11759 .loc 1 1846 3 view .LVU3523 + 11760 .L825: +1849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11761 .loc 1 1849 5 view .LVU3524 + 11762 016c 0122 movs r2, #1 + 11763 016e 2146 mov r1, r4 + 11764 0170 2868 ldr r0, [r5] + 11765 0172 FFF7FEFF bl TIM_CCxChannelCmd + 11766 .LVL861: +1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11767 .loc 1 1851 5 view .LVU3525 +1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11768 .loc 1 1851 9 is_stmt 0 view .LVU3526 + 11769 0176 2B68 ldr r3, [r5] +1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11770 .loc 1 1851 8 view .LVU3527 + ARM GAS /tmp/ccGFzgX3.s page 396 + + + 11771 0178 6549 ldr r1, .L843+12 + 11772 017a 664A ldr r2, .L843+16 + 11773 017c 9342 cmp r3, r2 + 11774 017e 18BF it ne + 11775 0180 8B42 cmpne r3, r1 + 11776 0182 03D1 bne .L826 +1854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11777 .loc 1 1854 7 is_stmt 1 view .LVU3528 + 11778 0184 5A6C ldr r2, [r3, #68] + 11779 0186 42F40042 orr r2, r2, #32768 + 11780 018a 5A64 str r2, [r3, #68] + 11781 .L826: +1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11782 .loc 1 1858 5 view .LVU3529 +1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11783 .loc 1 1858 9 is_stmt 0 view .LVU3530 + 11784 018c 2B68 ldr r3, [r5] +1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11785 .loc 1 1858 8 view .LVU3531 + 11786 018e 604A ldr r2, .L843+12 + 11787 0190 B3F1804F cmp r3, #1073741824 + 11788 0194 18BF it ne + 11789 0196 9342 cmpne r3, r2 + 11790 0198 00F09480 beq .L827 +1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11791 .loc 1 1858 9 discriminator 1 view .LVU3532 + 11792 019c A2F57C42 sub r2, r2, #64512 + 11793 01a0 9342 cmp r3, r2 + 11794 01a2 00F08F80 beq .L827 +1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11795 .loc 1 1858 9 discriminator 2 view .LVU3533 + 11796 01a6 02F58062 add r2, r2, #1024 + 11797 01aa 9342 cmp r3, r2 + 11798 01ac 00F08A80 beq .L827 +1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11799 .loc 1 1858 9 discriminator 3 view .LVU3534 + 11800 01b0 02F58062 add r2, r2, #1024 + 11801 01b4 9342 cmp r3, r2 + 11802 01b6 00F08580 beq .L827 +1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11803 .loc 1 1858 9 discriminator 4 view .LVU3535 + 11804 01ba 02F57842 add r2, r2, #63488 + 11805 01be 9342 cmp r3, r2 + 11806 01c0 00F08080 beq .L827 +1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11807 .loc 1 1858 9 discriminator 5 view .LVU3536 + 11808 01c4 02F57052 add r2, r2, #15360 + 11809 01c8 9342 cmp r3, r2 + 11810 01ca 7BD0 beq .L827 +1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11811 .loc 1 1858 9 discriminator 6 view .LVU3537 + 11812 01cc A2F59432 sub r2, r2, #75776 + 11813 01d0 9342 cmp r3, r2 + 11814 01d2 77D0 beq .L827 +1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11815 .loc 1 1868 7 is_stmt 1 view .LVU3538 + 11816 01d4 1A68 ldr r2, [r3] + ARM GAS /tmp/ccGFzgX3.s page 397 + + + 11817 01d6 42F00102 orr r2, r2, #1 + 11818 01da 1A60 str r2, [r3] + 11819 01dc 0020 movs r0, #0 + 11820 01de 82E0 b .L804 + 11821 .LVL862: + 11822 .L818: +1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11823 .loc 1 1746 7 is_stmt 0 discriminator 3 view .LVU3539 + 11824 01e0 0222 movs r2, #2 + 11825 01e2 85F83F20 strb r2, [r5, #63] +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11826 .loc 1 1754 3 is_stmt 1 view .LVU3540 + 11827 .L821: +1781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 11828 .loc 1 1781 7 view .LVU3541 +1781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 11829 .loc 1 1781 17 is_stmt 0 view .LVU3542 + 11830 01e6 AA6A ldr r2, [r5, #40] +1781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 11831 .loc 1 1781 52 view .LVU3543 + 11832 01e8 4648 ldr r0, .L843 + 11833 01ea D063 str r0, [r2, #60] +1782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11834 .loc 1 1782 7 is_stmt 1 view .LVU3544 +1782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11835 .loc 1 1782 17 is_stmt 0 view .LVU3545 + 11836 01ec AA6A ldr r2, [r5, #40] +1782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11837 .loc 1 1782 56 view .LVU3546 + 11838 01ee 4648 ldr r0, .L843+4 + 11839 01f0 1064 str r0, [r2, #64] +1785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11840 .loc 1 1785 7 is_stmt 1 view .LVU3547 +1785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11841 .loc 1 1785 17 is_stmt 0 view .LVU3548 + 11842 01f2 AA6A ldr r2, [r5, #40] +1785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11843 .loc 1 1785 53 view .LVU3549 + 11844 01f4 4548 ldr r0, .L843+8 + 11845 01f6 D064 str r0, [r2, #76] +1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 11846 .loc 1 1788 7 is_stmt 1 view .LVU3550 +1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 11847 .loc 1 1788 88 is_stmt 0 view .LVU3551 + 11848 01f8 2A68 ldr r2, [r5] +1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 11849 .loc 1 1788 11 view .LVU3552 + 11850 01fa 3832 adds r2, r2, #56 + 11851 01fc A86A ldr r0, [r5, #40] + 11852 01fe FFF7FEFF bl HAL_DMA_Start_IT + 11853 .LVL863: +1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 11854 .loc 1 1788 10 discriminator 1 view .LVU3553 + 11855 0202 0028 cmp r0, #0 + 11856 0204 76D1 bne .L834 +1795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 11857 .loc 1 1795 7 is_stmt 1 view .LVU3554 + ARM GAS /tmp/ccGFzgX3.s page 398 + + + 11858 0206 2A68 ldr r2, [r5] + 11859 0208 D368 ldr r3, [r2, #12] + 11860 020a 43F48063 orr r3, r3, #1024 + 11861 020e D360 str r3, [r2, #12] +1796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11862 .loc 1 1796 7 view .LVU3555 +1846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11863 .loc 1 1846 3 view .LVU3556 + 11864 0210 ACE7 b .L825 + 11865 .LVL864: + 11866 .L817: +1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11867 .loc 1 1746 7 is_stmt 0 discriminator 6 view .LVU3557 + 11868 0212 0222 movs r2, #2 + 11869 0214 85F84020 strb r2, [r5, #64] +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11870 .loc 1 1754 3 is_stmt 1 view .LVU3558 + 11871 .L822: +1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 11872 .loc 1 1802 7 view .LVU3559 +1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 11873 .loc 1 1802 17 is_stmt 0 view .LVU3560 + 11874 0218 EA6A ldr r2, [r5, #44] +1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 11875 .loc 1 1802 52 view .LVU3561 + 11876 021a 3A48 ldr r0, .L843 + 11877 021c D063 str r0, [r2, #60] +1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11878 .loc 1 1803 7 is_stmt 1 view .LVU3562 +1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11879 .loc 1 1803 17 is_stmt 0 view .LVU3563 + 11880 021e EA6A ldr r2, [r5, #44] +1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11881 .loc 1 1803 56 view .LVU3564 + 11882 0220 3948 ldr r0, .L843+4 + 11883 0222 1064 str r0, [r2, #64] +1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11884 .loc 1 1806 7 is_stmt 1 view .LVU3565 +1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11885 .loc 1 1806 17 is_stmt 0 view .LVU3566 + 11886 0224 EA6A ldr r2, [r5, #44] +1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11887 .loc 1 1806 53 view .LVU3567 + 11888 0226 3948 ldr r0, .L843+8 + 11889 0228 D064 str r0, [r2, #76] +1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 11890 .loc 1 1809 7 is_stmt 1 view .LVU3568 +1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 11891 .loc 1 1809 88 is_stmt 0 view .LVU3569 + 11892 022a 2A68 ldr r2, [r5] +1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 11893 .loc 1 1809 11 view .LVU3570 + 11894 022c 3C32 adds r2, r2, #60 + 11895 022e E86A ldr r0, [r5, #44] + 11896 0230 FFF7FEFF bl HAL_DMA_Start_IT + 11897 .LVL865: +1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + ARM GAS /tmp/ccGFzgX3.s page 399 + + + 11898 .loc 1 1809 10 discriminator 1 view .LVU3571 + 11899 0234 0028 cmp r0, #0 + 11900 0236 5FD1 bne .L835 +1816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 11901 .loc 1 1816 7 is_stmt 1 view .LVU3572 + 11902 0238 2A68 ldr r2, [r5] + 11903 023a D368 ldr r3, [r2, #12] + 11904 023c 43F40063 orr r3, r3, #2048 + 11905 0240 D360 str r3, [r2, #12] +1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11906 .loc 1 1817 7 view .LVU3573 +1846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11907 .loc 1 1846 3 view .LVU3574 + 11908 0242 93E7 b .L825 + 11909 .LVL866: + 11910 .L816: +1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11911 .loc 1 1746 7 is_stmt 0 discriminator 9 view .LVU3575 + 11912 0244 0222 movs r2, #2 + 11913 0246 85F84120 strb r2, [r5, #65] +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11914 .loc 1 1754 3 is_stmt 1 view .LVU3576 + 11915 .L823: +1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 11916 .loc 1 1823 7 view .LVU3577 +1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 11917 .loc 1 1823 17 is_stmt 0 view .LVU3578 + 11918 024a 2A6B ldr r2, [r5, #48] +1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 11919 .loc 1 1823 52 view .LVU3579 + 11920 024c 2D48 ldr r0, .L843 + 11921 024e D063 str r0, [r2, #60] +1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11922 .loc 1 1824 7 is_stmt 1 view .LVU3580 +1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11923 .loc 1 1824 17 is_stmt 0 view .LVU3581 + 11924 0250 2A6B ldr r2, [r5, #48] +1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11925 .loc 1 1824 56 view .LVU3582 + 11926 0252 2D48 ldr r0, .L843+4 + 11927 0254 1064 str r0, [r2, #64] +1827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11928 .loc 1 1827 7 is_stmt 1 view .LVU3583 +1827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11929 .loc 1 1827 17 is_stmt 0 view .LVU3584 + 11930 0256 2A6B ldr r2, [r5, #48] +1827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 11931 .loc 1 1827 53 view .LVU3585 + 11932 0258 2C48 ldr r0, .L843+8 + 11933 025a D064 str r0, [r2, #76] +1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 11934 .loc 1 1830 7 is_stmt 1 view .LVU3586 +1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 11935 .loc 1 1830 88 is_stmt 0 view .LVU3587 + 11936 025c 2A68 ldr r2, [r5] +1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 11937 .loc 1 1830 11 view .LVU3588 + ARM GAS /tmp/ccGFzgX3.s page 400 + + + 11938 025e 4032 adds r2, r2, #64 + 11939 0260 286B ldr r0, [r5, #48] + 11940 0262 FFF7FEFF bl HAL_DMA_Start_IT + 11941 .LVL867: +1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 11942 .loc 1 1830 10 discriminator 1 view .LVU3589 + 11943 0266 0028 cmp r0, #0 + 11944 0268 48D1 bne .L836 +1837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 11945 .loc 1 1837 7 is_stmt 1 view .LVU3590 + 11946 026a 2A68 ldr r2, [r5] + 11947 026c D368 ldr r3, [r2, #12] + 11948 026e 43F48053 orr r3, r3, #4096 + 11949 0272 D360 str r3, [r2, #12] +1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11950 .loc 1 1838 7 view .LVU3591 +1846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11951 .loc 1 1846 3 view .LVU3592 + 11952 0274 7AE7 b .L825 + 11953 .LVL868: + 11954 .L814: +1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11955 .loc 1 1746 7 is_stmt 0 discriminator 12 view .LVU3593 + 11956 0276 0223 movs r3, #2 + 11957 .LVL869: +1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11958 .loc 1 1746 7 discriminator 12 view .LVU3594 + 11959 0278 85F84230 strb r3, [r5, #66] +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11960 .loc 1 1754 3 is_stmt 1 view .LVU3595 +1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11961 .loc 1 1746 7 is_stmt 0 discriminator 12 view .LVU3596 + 11962 027c 0120 movs r0, #1 + 11963 027e 32E0 b .L804 + 11964 .LVL870: + 11965 .L813: +1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 11966 .loc 1 1746 7 discriminator 13 view .LVU3597 + 11967 0280 0222 movs r2, #2 + 11968 0282 85F84320 strb r2, [r5, #67] +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11969 .loc 1 1754 3 is_stmt 1 view .LVU3598 + 11970 0286 0C2C cmp r4, #12 + 11971 0288 30D8 bhi .L832 + 11972 028a 01A2 adr r2, .L824 + 11973 028c 52F824F0 ldr pc, [r2, r4, lsl #2] + 11974 .p2align 2 + 11975 .L824: + 11976 0290 41010000 .word .L820+1 + 11977 0294 ED020000 .word .L832+1 + 11978 0298 ED020000 .word .L832+1 + 11979 029c ED020000 .word .L832+1 + 11980 02a0 E7010000 .word .L821+1 + 11981 02a4 ED020000 .word .L832+1 + 11982 02a8 ED020000 .word .L832+1 + 11983 02ac ED020000 .word .L832+1 + 11984 02b0 19020000 .word .L822+1 + ARM GAS /tmp/ccGFzgX3.s page 401 + + + 11985 02b4 ED020000 .word .L832+1 + 11986 02b8 ED020000 .word .L832+1 + 11987 02bc ED020000 .word .L832+1 + 11988 02c0 4B020000 .word .L823+1 + 11989 .LVL871: + 11990 .p2align 1 + 11991 .L827: +1860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 11992 .loc 1 1860 7 view .LVU3599 +1860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 11993 .loc 1 1860 31 is_stmt 0 view .LVU3600 + 11994 02c4 9968 ldr r1, [r3, #8] +1860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 11995 .loc 1 1860 15 view .LVU3601 + 11996 02c6 144A ldr r2, .L843+20 + 11997 02c8 0A40 ands r2, r2, r1 + 11998 .LVL872: +1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 11999 .loc 1 1861 7 is_stmt 1 view .LVU3602 +1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12000 .loc 1 1861 10 is_stmt 0 view .LVU3603 + 12001 02ca 062A cmp r2, #6 + 12002 02cc 18BF it ne + 12003 02ce B2F5803F cmpne r2, #65536 + 12004 02d2 15D0 beq .L837 +1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12005 .loc 1 1863 9 is_stmt 1 view .LVU3604 + 12006 02d4 1A68 ldr r2, [r3] + 12007 .LVL873: +1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12008 .loc 1 1863 9 is_stmt 0 view .LVU3605 + 12009 02d6 42F00102 orr r2, r2, #1 + 12010 02da 1A60 str r2, [r3] + 12011 02dc 0020 movs r0, #0 + 12012 02de 02E0 b .L804 + 12013 .LVL874: + 12014 .L829: +1736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12015 .loc 1 1736 12 view .LVU3606 + 12016 02e0 0220 movs r0, #2 + 12017 02e2 00E0 b .L804 + 12018 .L830: +1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12019 .loc 1 1751 12 view .LVU3607 + 12020 02e4 0120 movs r0, #1 + 12021 .LVL875: + 12022 .L804: +1874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12023 .loc 1 1874 1 view .LVU3608 + 12024 02e6 38BD pop {r3, r4, r5, pc} + 12025 .LVL876: + 12026 .L831: +1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12027 .loc 1 1742 14 view .LVU3609 + 12028 02e8 0120 movs r0, #1 + 12029 02ea FCE7 b .L804 + 12030 .L832: + ARM GAS /tmp/ccGFzgX3.s page 402 + + +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12031 .loc 1 1754 3 view .LVU3610 + 12032 02ec 0120 movs r0, #1 + 12033 02ee FAE7 b .L804 + 12034 .LVL877: + 12035 .L833: +1770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12036 .loc 1 1770 16 view .LVU3611 + 12037 02f0 0120 movs r0, #1 + 12038 02f2 F8E7 b .L804 + 12039 .L834: +1792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12040 .loc 1 1792 16 view .LVU3612 + 12041 02f4 0120 movs r0, #1 + 12042 02f6 F6E7 b .L804 + 12043 .L835: +1813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12044 .loc 1 1813 16 view .LVU3613 + 12045 02f8 0120 movs r0, #1 + 12046 02fa F4E7 b .L804 + 12047 .L836: +1834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12048 .loc 1 1834 16 view .LVU3614 + 12049 02fc 0120 movs r0, #1 + 12050 02fe F2E7 b .L804 + 12051 .LVL878: + 12052 .L837: +1834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12053 .loc 1 1834 16 view .LVU3615 + 12054 0300 0020 movs r0, #0 + 12055 0302 F0E7 b .L804 + 12056 .L844: + 12057 .align 2 + 12058 .L843: + 12059 0304 00000000 .word TIM_DMADelayPulseCplt + 12060 0308 00000000 .word TIM_DMADelayPulseHalfCplt + 12061 030c 00000000 .word TIM_DMAError + 12062 0310 00000140 .word 1073807360 + 12063 0314 00040140 .word 1073808384 + 12064 0318 07000100 .word 65543 + 12065 .cfi_endproc + 12066 .LFE169: + 12068 .section .text.HAL_TIM_PWM_Stop_DMA,"ax",%progbits + 12069 .align 1 + 12070 .global HAL_TIM_PWM_Stop_DMA + 12071 .syntax unified + 12072 .thumb + 12073 .thumb_func + 12075 HAL_TIM_PWM_Stop_DMA: + 12076 .LVL879: + 12077 .LFB170: +1888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 12078 .loc 1 1888 1 is_stmt 1 view -0 + 12079 .cfi_startproc + 12080 @ args = 0, pretend = 0, frame = 0 + 12081 @ frame_needed = 0, uses_anonymous_args = 0 +1888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + ARM GAS /tmp/ccGFzgX3.s page 403 + + + 12082 .loc 1 1888 1 is_stmt 0 view .LVU3617 + 12083 0000 38B5 push {r3, r4, r5, lr} + 12084 .LCFI97: + 12085 .cfi_def_cfa_offset 16 + 12086 .cfi_offset 3, -16 + 12087 .cfi_offset 4, -12 + 12088 .cfi_offset 5, -8 + 12089 .cfi_offset 14, -4 + 12090 0002 0446 mov r4, r0 + 12091 0004 0D46 mov r5, r1 +1889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12092 .loc 1 1889 3 is_stmt 1 view .LVU3618 + 12093 .LVL880: +1892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12094 .loc 1 1892 3 view .LVU3619 +1894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12095 .loc 1 1894 3 view .LVU3620 + 12096 0006 0C29 cmp r1, #12 + 12097 0008 7FD8 bhi .L862 + 12098 000a DFE801F0 tbb [pc, r1] + 12099 .L848: + 12100 000e 07 .byte (.L851-.L848)/2 + 12101 000f 7E .byte (.L862-.L848)/2 + 12102 0010 7E .byte (.L862-.L848)/2 + 12103 0011 7E .byte (.L862-.L848)/2 + 12104 0012 45 .byte (.L850-.L848)/2 + 12105 0013 7E .byte (.L862-.L848)/2 + 12106 0014 7E .byte (.L862-.L848)/2 + 12107 0015 7E .byte (.L862-.L848)/2 + 12108 0016 4E .byte (.L849-.L848)/2 + 12109 0017 7E .byte (.L862-.L848)/2 + 12110 0018 7E .byte (.L862-.L848)/2 + 12111 0019 7E .byte (.L862-.L848)/2 + 12112 001a 57 .byte (.L847-.L848)/2 + 12113 001b 00 .p2align 1 + 12114 .L851: +1899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + 12115 .loc 1 1899 7 view .LVU3621 + 12116 001c 0268 ldr r2, [r0] + 12117 001e D368 ldr r3, [r2, #12] + 12118 0020 23F40073 bic r3, r3, #512 + 12119 0024 D360 str r3, [r2, #12] +1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 12120 .loc 1 1900 7 view .LVU3622 +1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 12121 .loc 1 1900 13 is_stmt 0 view .LVU3623 + 12122 0026 406A ldr r0, [r0, #36] + 12123 .LVL881: +1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 12124 .loc 1 1900 13 view .LVU3624 + 12125 0028 FFF7FEFF bl HAL_DMA_Abort_IT + 12126 .LVL882: +1901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12127 .loc 1 1901 7 is_stmt 1 view .LVU3625 +1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12128 .loc 1 1933 3 view .LVU3626 + 12129 .L852: + ARM GAS /tmp/ccGFzgX3.s page 404 + + +1936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12130 .loc 1 1936 5 view .LVU3627 + 12131 002c 0022 movs r2, #0 + 12132 002e 2946 mov r1, r5 + 12133 0030 2068 ldr r0, [r4] + 12134 0032 FFF7FEFF bl TIM_CCxChannelCmd + 12135 .LVL883: +1938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12136 .loc 1 1938 5 view .LVU3628 +1938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12137 .loc 1 1938 9 is_stmt 0 view .LVU3629 + 12138 0036 2368 ldr r3, [r4] +1938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12139 .loc 1 1938 8 view .LVU3630 + 12140 0038 3549 ldr r1, .L864 + 12141 003a 364A ldr r2, .L864+4 + 12142 003c 9342 cmp r3, r2 + 12143 003e 18BF it ne + 12144 0040 8B42 cmpne r3, r1 + 12145 0042 0DD1 bne .L853 +1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12146 .loc 1 1941 7 is_stmt 1 view .LVU3631 +1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12147 .loc 1 1941 7 view .LVU3632 + 12148 0044 196A ldr r1, [r3, #32] + 12149 0046 41F21112 movw r2, #4369 + 12150 004a 1142 tst r1, r2 + 12151 004c 08D1 bne .L853 +1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12152 .loc 1 1941 7 discriminator 1 view .LVU3633 + 12153 004e 196A ldr r1, [r3, #32] + 12154 0050 40F24442 movw r2, #1092 + 12155 0054 1142 tst r1, r2 + 12156 0056 03D1 bne .L853 +1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12157 .loc 1 1941 7 discriminator 3 view .LVU3634 + 12158 0058 5A6C ldr r2, [r3, #68] + 12159 005a 22F40042 bic r2, r2, #32768 + 12160 005e 5A64 str r2, [r3, #68] + 12161 .L853: +1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12162 .loc 1 1941 7 discriminator 5 view .LVU3635 +1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12163 .loc 1 1945 5 view .LVU3636 +1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12164 .loc 1 1945 5 view .LVU3637 + 12165 0060 2368 ldr r3, [r4] + 12166 0062 196A ldr r1, [r3, #32] + 12167 0064 41F21112 movw r2, #4369 + 12168 0068 1142 tst r1, r2 + 12169 006a 08D1 bne .L854 +1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12170 .loc 1 1945 5 discriminator 1 view .LVU3638 + 12171 006c 196A ldr r1, [r3, #32] + 12172 006e 40F24442 movw r2, #1092 + 12173 0072 1142 tst r1, r2 + 12174 0074 03D1 bne .L854 + ARM GAS /tmp/ccGFzgX3.s page 405 + + +1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12175 .loc 1 1945 5 discriminator 3 view .LVU3639 + 12176 0076 1A68 ldr r2, [r3] + 12177 0078 22F00102 bic r2, r2, #1 + 12178 007c 1A60 str r2, [r3] + 12179 .L854: +1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12180 .loc 1 1945 5 discriminator 5 view .LVU3640 +1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12181 .loc 1 1948 5 view .LVU3641 + 12182 007e 102D cmp r5, #16 + 12183 0080 3ED8 bhi .L855 + 12184 0082 DFE805F0 tbb [pc, r5] + 12185 .L857: + 12186 0086 24 .byte (.L861-.L857)/2 + 12187 0087 3D .byte (.L855-.L857)/2 + 12188 0088 3D .byte (.L855-.L857)/2 + 12189 0089 3D .byte (.L855-.L857)/2 + 12190 008a 29 .byte (.L860-.L857)/2 + 12191 008b 3D .byte (.L855-.L857)/2 + 12192 008c 3D .byte (.L855-.L857)/2 + 12193 008d 3D .byte (.L855-.L857)/2 + 12194 008e 2E .byte (.L859-.L857)/2 + 12195 008f 3D .byte (.L855-.L857)/2 + 12196 0090 3D .byte (.L855-.L857)/2 + 12197 0091 3D .byte (.L855-.L857)/2 + 12198 0092 33 .byte (.L858-.L857)/2 + 12199 0093 3D .byte (.L855-.L857)/2 + 12200 0094 3D .byte (.L855-.L857)/2 + 12201 0095 3D .byte (.L855-.L857)/2 + 12202 0096 38 .byte (.L856-.L857)/2 + 12203 .LVL884: + 12204 0097 00 .p2align 1 + 12205 .L850: +1907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + 12206 .loc 1 1907 7 view .LVU3642 + 12207 0098 0268 ldr r2, [r0] + 12208 009a D368 ldr r3, [r2, #12] + 12209 009c 23F48063 bic r3, r3, #1024 + 12210 00a0 D360 str r3, [r2, #12] +1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 12211 .loc 1 1908 7 view .LVU3643 +1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 12212 .loc 1 1908 13 is_stmt 0 view .LVU3644 + 12213 00a2 806A ldr r0, [r0, #40] + 12214 .LVL885: +1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 12215 .loc 1 1908 13 view .LVU3645 + 12216 00a4 FFF7FEFF bl HAL_DMA_Abort_IT + 12217 .LVL886: +1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12218 .loc 1 1909 7 is_stmt 1 view .LVU3646 +1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12219 .loc 1 1933 3 view .LVU3647 + 12220 00a8 C0E7 b .L852 + 12221 .LVL887: + 12222 .L849: + ARM GAS /tmp/ccGFzgX3.s page 406 + + +1915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + 12223 .loc 1 1915 7 view .LVU3648 + 12224 00aa 0268 ldr r2, [r0] + 12225 00ac D368 ldr r3, [r2, #12] + 12226 00ae 23F40063 bic r3, r3, #2048 + 12227 00b2 D360 str r3, [r2, #12] +1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 12228 .loc 1 1916 7 view .LVU3649 +1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 12229 .loc 1 1916 13 is_stmt 0 view .LVU3650 + 12230 00b4 C06A ldr r0, [r0, #44] + 12231 .LVL888: +1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 12232 .loc 1 1916 13 view .LVU3651 + 12233 00b6 FFF7FEFF bl HAL_DMA_Abort_IT + 12234 .LVL889: +1917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12235 .loc 1 1917 7 is_stmt 1 view .LVU3652 +1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12236 .loc 1 1933 3 view .LVU3653 + 12237 00ba B7E7 b .L852 + 12238 .LVL890: + 12239 .L847: +1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + 12240 .loc 1 1923 7 view .LVU3654 + 12241 00bc 0268 ldr r2, [r0] + 12242 00be D368 ldr r3, [r2, #12] + 12243 00c0 23F48053 bic r3, r3, #4096 + 12244 00c4 D360 str r3, [r2, #12] +1924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 12245 .loc 1 1924 7 view .LVU3655 +1924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 12246 .loc 1 1924 13 is_stmt 0 view .LVU3656 + 12247 00c6 006B ldr r0, [r0, #48] + 12248 .LVL891: +1924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 12249 .loc 1 1924 13 view .LVU3657 + 12250 00c8 FFF7FEFF bl HAL_DMA_Abort_IT + 12251 .LVL892: +1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12252 .loc 1 1925 7 is_stmt 1 view .LVU3658 +1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12253 .loc 1 1933 3 view .LVU3659 + 12254 00cc AEE7 b .L852 + 12255 .L861: +1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12256 .loc 1 1948 5 is_stmt 0 discriminator 1 view .LVU3660 + 12257 00ce 0123 movs r3, #1 + 12258 00d0 84F83E30 strb r3, [r4, #62] + 12259 00d4 0020 movs r0, #0 + 12260 00d6 19E0 b .L846 + 12261 .L860: +1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12262 .loc 1 1948 5 discriminator 3 view .LVU3661 + 12263 00d8 0123 movs r3, #1 + 12264 00da 84F83F30 strb r3, [r4, #63] + 12265 00de 0020 movs r0, #0 + ARM GAS /tmp/ccGFzgX3.s page 407 + + + 12266 00e0 14E0 b .L846 + 12267 .L859: +1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12268 .loc 1 1948 5 discriminator 6 view .LVU3662 + 12269 00e2 0123 movs r3, #1 + 12270 00e4 84F84030 strb r3, [r4, #64] + 12271 00e8 0020 movs r0, #0 + 12272 00ea 0FE0 b .L846 + 12273 .L858: +1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12274 .loc 1 1948 5 discriminator 9 view .LVU3663 + 12275 00ec 0123 movs r3, #1 + 12276 00ee 84F84130 strb r3, [r4, #65] + 12277 00f2 0020 movs r0, #0 + 12278 00f4 0AE0 b .L846 + 12279 .L856: +1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12280 .loc 1 1948 5 discriminator 12 view .LVU3664 + 12281 00f6 0123 movs r3, #1 + 12282 00f8 84F84230 strb r3, [r4, #66] + 12283 00fc 0020 movs r0, #0 + 12284 00fe 05E0 b .L846 + 12285 .L855: +1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12286 .loc 1 1948 5 discriminator 13 view .LVU3665 + 12287 0100 0123 movs r3, #1 + 12288 0102 84F84330 strb r3, [r4, #67] + 12289 0106 0020 movs r0, #0 + 12290 0108 00E0 b .L846 + 12291 .LVL893: + 12292 .L862: +1894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12293 .loc 1 1894 3 view .LVU3666 + 12294 010a 0120 movs r0, #1 + 12295 .LVL894: + 12296 .L846: +1952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12297 .loc 1 1952 3 is_stmt 1 view .LVU3667 +1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12298 .loc 1 1953 1 is_stmt 0 view .LVU3668 + 12299 010c 38BD pop {r3, r4, r5, pc} + 12300 .LVL895: + 12301 .L865: +1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12302 .loc 1 1953 1 view .LVU3669 + 12303 010e 00BF .align 2 + 12304 .L864: + 12305 0110 00000140 .word 1073807360 + 12306 0114 00040140 .word 1073808384 + 12307 .cfi_endproc + 12308 .LFE170: + 12310 .section .text.HAL_TIM_IC_Start,"ax",%progbits + 12311 .align 1 + 12312 .global HAL_TIM_IC_Start + 12313 .syntax unified + 12314 .thumb + 12315 .thumb_func + ARM GAS /tmp/ccGFzgX3.s page 408 + + + 12317 HAL_TIM_IC_Start: + 12318 .LVL896: + 12319 .LFB175: +2130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 12320 .loc 1 2130 1 is_stmt 1 view -0 + 12321 .cfi_startproc + 12322 @ args = 0, pretend = 0, frame = 0 + 12323 @ frame_needed = 0, uses_anonymous_args = 0 +2130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 12324 .loc 1 2130 1 is_stmt 0 view .LVU3671 + 12325 0000 10B5 push {r4, lr} + 12326 .LCFI98: + 12327 .cfi_def_cfa_offset 8 + 12328 .cfi_offset 4, -8 + 12329 .cfi_offset 14, -4 + 12330 0002 0446 mov r4, r0 +2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + 12331 .loc 1 2131 3 is_stmt 1 view .LVU3672 +2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 12332 .loc 1 2132 3 view .LVU3673 + 12333 0004 1029 cmp r1, #16 + 12334 0006 33D8 bhi .L867 + 12335 0008 DFE801F0 tbb [pc, r1] + 12336 .L869: + 12337 000c 09 .byte (.L873-.L869)/2 + 12338 000d 32 .byte (.L867-.L869)/2 + 12339 000e 32 .byte (.L867-.L869)/2 + 12340 000f 32 .byte (.L867-.L869)/2 + 12341 0010 22 .byte (.L872-.L869)/2 + 12342 0011 32 .byte (.L867-.L869)/2 + 12343 0012 32 .byte (.L867-.L869)/2 + 12344 0013 32 .byte (.L867-.L869)/2 + 12345 0014 26 .byte (.L871-.L869)/2 + 12346 0015 32 .byte (.L867-.L869)/2 + 12347 0016 32 .byte (.L867-.L869)/2 + 12348 0017 32 .byte (.L867-.L869)/2 + 12349 0018 2A .byte (.L870-.L869)/2 + 12350 0019 32 .byte (.L867-.L869)/2 + 12351 001a 32 .byte (.L867-.L869)/2 + 12352 001b 32 .byte (.L867-.L869)/2 + 12353 001c 2E .byte (.L868-.L869)/2 + 12354 001d 00 .p2align 1 + 12355 .L873: +2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 12356 .loc 1 2132 47 is_stmt 0 discriminator 1 view .LVU3674 + 12357 001e 90F83E20 ldrb r2, [r0, #62] @ zero_extendqisi2 + 12358 0022 D2B2 uxtb r2, r2 + 12359 .L874: + 12360 .LVL897: +2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12361 .loc 1 2133 3 is_stmt 1 view .LVU3675 +2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12362 .loc 1 2133 61 is_stmt 0 view .LVU3676 + 12363 0024 41BB cbnz r1, .L875 +2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12364 .loc 1 2133 61 discriminator 1 view .LVU3677 + 12365 0026 94F84430 ldrb r3, [r4, #68] @ zero_extendqisi2 + ARM GAS /tmp/ccGFzgX3.s page 409 + + + 12366 002a DBB2 uxtb r3, r3 + 12367 .L876: + 12368 .LVL898: +2136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12369 .loc 1 2136 3 is_stmt 1 view .LVU3678 +2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + 12370 .loc 1 2139 3 view .LVU3679 +2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + 12371 .loc 1 2139 6 is_stmt 0 view .LVU3680 + 12372 002c 012B cmp r3, #1 + 12373 002e 08BF it eq + 12374 0030 012A cmpeq r2, #1 + 12375 0032 40F09080 bne .L893 +2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 12376 .loc 1 2146 3 is_stmt 1 view .LVU3681 + 12377 0036 1029 cmp r1, #16 + 12378 0038 73D8 bhi .L880 + 12379 003a DFE801F0 tbb [pc, r1] + 12380 .LVL899: + 12381 .L882: + 12382 003e 2D .byte (.L886-.L882)/2 + 12383 003f 72 .byte (.L880-.L882)/2 + 12384 0040 72 .byte (.L880-.L882)/2 + 12385 0041 72 .byte (.L880-.L882)/2 + 12386 0042 33 .byte (.L885-.L882)/2 + 12387 0043 72 .byte (.L880-.L882)/2 + 12388 0044 72 .byte (.L880-.L882)/2 + 12389 0045 72 .byte (.L880-.L882)/2 + 12390 0046 66 .byte (.L884-.L882)/2 + 12391 0047 72 .byte (.L880-.L882)/2 + 12392 0048 72 .byte (.L880-.L882)/2 + 12393 0049 72 .byte (.L880-.L882)/2 + 12394 004a 6A .byte (.L883-.L882)/2 + 12395 004b 72 .byte (.L880-.L882)/2 + 12396 004c 72 .byte (.L880-.L882)/2 + 12397 004d 72 .byte (.L880-.L882)/2 + 12398 004e 6E .byte (.L881-.L882)/2 + 12399 004f 00 .p2align 1 + 12400 .L872: +2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 12401 .loc 1 2132 47 is_stmt 0 discriminator 4 view .LVU3682 + 12402 0050 90F83F20 ldrb r2, [r0, #63] @ zero_extendqisi2 + 12403 0054 D2B2 uxtb r2, r2 + 12404 0056 E5E7 b .L874 + 12405 .L871: +2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 12406 .loc 1 2132 47 discriminator 7 view .LVU3683 + 12407 0058 90F84020 ldrb r2, [r0, #64] @ zero_extendqisi2 + 12408 005c D2B2 uxtb r2, r2 + 12409 005e E1E7 b .L874 + 12410 .L870: +2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 12411 .loc 1 2132 47 discriminator 10 view .LVU3684 + 12412 0060 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2 + 12413 0064 D2B2 uxtb r2, r2 + 12414 0066 DDE7 b .L874 + 12415 .L868: + ARM GAS /tmp/ccGFzgX3.s page 410 + + +2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 12416 .loc 1 2132 47 discriminator 13 view .LVU3685 + 12417 0068 90F84220 ldrb r2, [r0, #66] @ zero_extendqisi2 + 12418 006c D2B2 uxtb r2, r2 + 12419 006e D9E7 b .L874 + 12420 .L867: +2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 12421 .loc 1 2132 47 discriminator 14 view .LVU3686 + 12422 0070 90F84320 ldrb r2, [r0, #67] @ zero_extendqisi2 + 12423 0074 D2B2 uxtb r2, r2 + 12424 0076 D5E7 b .L874 + 12425 .LVL900: + 12426 .L875: +2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12427 .loc 1 2133 61 discriminator 2 view .LVU3687 + 12428 0078 0429 cmp r1, #4 + 12429 007a 05D0 beq .L896 +2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12430 .loc 1 2133 61 discriminator 5 view .LVU3688 + 12431 007c 0829 cmp r1, #8 + 12432 007e 07D0 beq .L897 +2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12433 .loc 1 2133 61 discriminator 8 view .LVU3689 + 12434 0080 94F84730 ldrb r3, [r4, #71] @ zero_extendqisi2 + 12435 0084 DBB2 uxtb r3, r3 + 12436 0086 D1E7 b .L876 + 12437 .L896: +2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12438 .loc 1 2133 61 discriminator 4 view .LVU3690 + 12439 0088 94F84530 ldrb r3, [r4, #69] @ zero_extendqisi2 + 12440 008c DBB2 uxtb r3, r3 + 12441 008e CDE7 b .L876 + 12442 .L897: +2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12443 .loc 1 2133 61 discriminator 7 view .LVU3691 + 12444 0090 94F84630 ldrb r3, [r4, #70] @ zero_extendqisi2 + 12445 0094 DBB2 uxtb r3, r3 + 12446 0096 C9E7 b .L876 + 12447 .LVL901: + 12448 .L886: +2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 12449 .loc 1 2146 3 discriminator 1 view .LVU3692 + 12450 0098 0223 movs r3, #2 + 12451 009a 84F83E30 strb r3, [r4, #62] +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12452 .loc 1 2147 3 is_stmt 1 view .LVU3693 +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12453 .loc 1 2147 3 is_stmt 0 discriminator 1 view .LVU3694 + 12454 009e 84F84430 strb r3, [r4, #68] + 12455 00a2 09E0 b .L887 + 12456 .L885: +2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 12457 .loc 1 2146 3 discriminator 3 view .LVU3695 + 12458 00a4 0223 movs r3, #2 + 12459 00a6 84F83F30 strb r3, [r4, #63] +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12460 .loc 1 2147 3 is_stmt 1 view .LVU3696 + ARM GAS /tmp/ccGFzgX3.s page 411 + + + 12461 .L888: +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12462 .loc 1 2147 3 is_stmt 0 discriminator 2 view .LVU3697 + 12463 00aa 0429 cmp r1, #4 + 12464 00ac 3DD0 beq .L898 +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12465 .loc 1 2147 3 discriminator 4 view .LVU3698 + 12466 00ae 0829 cmp r1, #8 + 12467 00b0 3FD0 beq .L899 +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12468 .loc 1 2147 3 discriminator 7 view .LVU3699 + 12469 00b2 0223 movs r3, #2 + 12470 00b4 84F84730 strb r3, [r4, #71] + 12471 .L887: +2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12472 .loc 1 2150 3 is_stmt 1 view .LVU3700 + 12473 00b8 0122 movs r2, #1 + 12474 .LVL902: +2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12475 .loc 1 2150 3 is_stmt 0 view .LVU3701 + 12476 00ba 2068 ldr r0, [r4] + 12477 .LVL903: +2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12478 .loc 1 2150 3 view .LVU3702 + 12479 00bc FFF7FEFF bl TIM_CCxChannelCmd + 12480 .LVL904: +2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12481 .loc 1 2153 3 is_stmt 1 view .LVU3703 +2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12482 .loc 1 2153 7 is_stmt 0 view .LVU3704 + 12483 00c0 2368 ldr r3, [r4] +2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12484 .loc 1 2153 6 view .LVU3705 + 12485 00c2 274A ldr r2, .L900 + 12486 00c4 B3F1804F cmp r3, #1073741824 + 12487 00c8 18BF it ne + 12488 00ca 9342 cmpne r3, r2 + 12489 00cc 35D0 beq .L891 +2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12490 .loc 1 2153 7 discriminator 1 view .LVU3706 + 12491 00ce A2F57C42 sub r2, r2, #64512 + 12492 00d2 9342 cmp r3, r2 + 12493 00d4 31D0 beq .L891 +2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12494 .loc 1 2153 7 discriminator 2 view .LVU3707 + 12495 00d6 02F58062 add r2, r2, #1024 + 12496 00da 9342 cmp r3, r2 + 12497 00dc 2DD0 beq .L891 +2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12498 .loc 1 2153 7 discriminator 3 view .LVU3708 + 12499 00de 02F58062 add r2, r2, #1024 + 12500 00e2 9342 cmp r3, r2 + 12501 00e4 29D0 beq .L891 +2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12502 .loc 1 2153 7 discriminator 4 view .LVU3709 + 12503 00e6 02F57842 add r2, r2, #63488 + 12504 00ea 9342 cmp r3, r2 + ARM GAS /tmp/ccGFzgX3.s page 412 + + + 12505 00ec 25D0 beq .L891 +2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12506 .loc 1 2153 7 discriminator 5 view .LVU3710 + 12507 00ee 02F57052 add r2, r2, #15360 + 12508 00f2 9342 cmp r3, r2 + 12509 00f4 21D0 beq .L891 +2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12510 .loc 1 2153 7 discriminator 6 view .LVU3711 + 12511 00f6 A2F59432 sub r2, r2, #75776 + 12512 00fa 9342 cmp r3, r2 + 12513 00fc 1DD0 beq .L891 +2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12514 .loc 1 2163 5 is_stmt 1 view .LVU3712 + 12515 00fe 1A68 ldr r2, [r3] + 12516 0100 42F00102 orr r2, r2, #1 + 12517 0104 1A60 str r2, [r3] +2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12518 .loc 1 2167 10 is_stmt 0 view .LVU3713 + 12519 0106 0020 movs r0, #0 + 12520 0108 26E0 b .L879 + 12521 .LVL905: + 12522 .L884: +2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 12523 .loc 1 2146 3 discriminator 6 view .LVU3714 + 12524 010a 0223 movs r3, #2 + 12525 010c 84F84030 strb r3, [r4, #64] +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12526 .loc 1 2147 3 is_stmt 1 view .LVU3715 + 12527 0110 CBE7 b .L888 + 12528 .L883: +2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 12529 .loc 1 2146 3 is_stmt 0 discriminator 9 view .LVU3716 + 12530 0112 0223 movs r3, #2 + 12531 0114 84F84130 strb r3, [r4, #65] +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12532 .loc 1 2147 3 is_stmt 1 view .LVU3717 + 12533 0118 C7E7 b .L888 + 12534 .L881: +2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 12535 .loc 1 2146 3 is_stmt 0 discriminator 12 view .LVU3718 + 12536 011a 0223 movs r3, #2 + 12537 011c 84F84230 strb r3, [r4, #66] +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12538 .loc 1 2147 3 is_stmt 1 view .LVU3719 + 12539 0120 C3E7 b .L888 + 12540 .L880: +2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 12541 .loc 1 2146 3 is_stmt 0 discriminator 13 view .LVU3720 + 12542 0122 0223 movs r3, #2 + 12543 0124 84F84330 strb r3, [r4, #67] +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12544 .loc 1 2147 3 is_stmt 1 view .LVU3721 + 12545 0128 BFE7 b .L888 + 12546 .L898: +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12547 .loc 1 2147 3 is_stmt 0 discriminator 3 view .LVU3722 + 12548 012a 0223 movs r3, #2 + ARM GAS /tmp/ccGFzgX3.s page 413 + + + 12549 012c 84F84530 strb r3, [r4, #69] + 12550 0130 C2E7 b .L887 + 12551 .L899: +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12552 .loc 1 2147 3 discriminator 6 view .LVU3723 + 12553 0132 0223 movs r3, #2 + 12554 0134 84F84630 strb r3, [r4, #70] + 12555 0138 BEE7 b .L887 + 12556 .LVL906: + 12557 .L891: +2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 12558 .loc 1 2155 5 is_stmt 1 view .LVU3724 +2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 12559 .loc 1 2155 29 is_stmt 0 view .LVU3725 + 12560 013a 9968 ldr r1, [r3, #8] +2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 12561 .loc 1 2155 13 view .LVU3726 + 12562 013c 094A ldr r2, .L900+4 + 12563 013e 0A40 ands r2, r2, r1 + 12564 .LVL907: +2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12565 .loc 1 2156 5 is_stmt 1 view .LVU3727 +2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12566 .loc 1 2156 8 is_stmt 0 view .LVU3728 + 12567 0140 062A cmp r2, #6 + 12568 0142 18BF it ne + 12569 0144 B2F5803F cmpne r2, #65536 + 12570 0148 07D0 beq .L894 +2158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12571 .loc 1 2158 7 is_stmt 1 view .LVU3729 + 12572 014a 1A68 ldr r2, [r3] + 12573 .LVL908: +2158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12574 .loc 1 2158 7 is_stmt 0 view .LVU3730 + 12575 014c 42F00102 orr r2, r2, #1 + 12576 0150 1A60 str r2, [r3] +2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12577 .loc 1 2167 10 view .LVU3731 + 12578 0152 0020 movs r0, #0 + 12579 0154 00E0 b .L879 + 12580 .LVL909: + 12581 .L893: +2142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12582 .loc 1 2142 12 view .LVU3732 + 12583 0156 0120 movs r0, #1 + 12584 .LVL910: + 12585 .L879: +2168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12586 .loc 1 2168 1 view .LVU3733 + 12587 0158 10BD pop {r4, pc} + 12588 .LVL911: + 12589 .L894: +2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12590 .loc 1 2167 10 view .LVU3734 + 12591 015a 0020 movs r0, #0 + 12592 015c FCE7 b .L879 + 12593 .L901: + ARM GAS /tmp/ccGFzgX3.s page 414 + + + 12594 015e 00BF .align 2 + 12595 .L900: + 12596 0160 00000140 .word 1073807360 + 12597 0164 07000100 .word 65543 + 12598 .cfi_endproc + 12599 .LFE175: + 12601 .section .text.HAL_TIM_IC_Stop,"ax",%progbits + 12602 .align 1 + 12603 .global HAL_TIM_IC_Stop + 12604 .syntax unified + 12605 .thumb + 12606 .thumb_func + 12608 HAL_TIM_IC_Stop: + 12609 .LVL912: + 12610 .LFB176: +2182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 12611 .loc 1 2182 1 is_stmt 1 view -0 + 12612 .cfi_startproc + 12613 @ args = 0, pretend = 0, frame = 0 + 12614 @ frame_needed = 0, uses_anonymous_args = 0 +2182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 12615 .loc 1 2182 1 is_stmt 0 view .LVU3736 + 12616 0000 38B5 push {r3, r4, r5, lr} + 12617 .LCFI99: + 12618 .cfi_def_cfa_offset 16 + 12619 .cfi_offset 3, -16 + 12620 .cfi_offset 4, -12 + 12621 .cfi_offset 5, -8 + 12622 .cfi_offset 14, -4 + 12623 0002 0446 mov r4, r0 + 12624 0004 0D46 mov r5, r1 +2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12625 .loc 1 2184 3 is_stmt 1 view .LVU3737 +2187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12626 .loc 1 2187 3 view .LVU3738 + 12627 0006 0022 movs r2, #0 + 12628 0008 0068 ldr r0, [r0] + 12629 .LVL913: +2187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12630 .loc 1 2187 3 is_stmt 0 view .LVU3739 + 12631 000a FFF7FEFF bl TIM_CCxChannelCmd + 12632 .LVL914: +2190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12633 .loc 1 2190 3 is_stmt 1 view .LVU3740 +2190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12634 .loc 1 2190 3 view .LVU3741 + 12635 000e 2368 ldr r3, [r4] + 12636 0010 196A ldr r1, [r3, #32] + 12637 0012 41F21112 movw r2, #4369 + 12638 0016 1142 tst r1, r2 + 12639 0018 08D1 bne .L903 +2190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12640 .loc 1 2190 3 discriminator 1 view .LVU3742 + 12641 001a 196A ldr r1, [r3, #32] + 12642 001c 40F24442 movw r2, #1092 + 12643 0020 1142 tst r1, r2 + 12644 0022 03D1 bne .L903 + ARM GAS /tmp/ccGFzgX3.s page 415 + + +2190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12645 .loc 1 2190 3 discriminator 3 view .LVU3743 + 12646 0024 1A68 ldr r2, [r3] + 12647 0026 22F00102 bic r2, r2, #1 + 12648 002a 1A60 str r2, [r3] + 12649 .L903: +2190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12650 .loc 1 2190 3 discriminator 5 view .LVU3744 +2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 12651 .loc 1 2193 3 view .LVU3745 + 12652 002c 102D cmp r5, #16 + 12653 002e 28D8 bhi .L904 + 12654 0030 DFE805F0 tbb [pc, r5] + 12655 .L906: + 12656 0034 09 .byte (.L910-.L906)/2 + 12657 0035 27 .byte (.L904-.L906)/2 + 12658 0036 27 .byte (.L904-.L906)/2 + 12659 0037 27 .byte (.L904-.L906)/2 + 12660 0038 0F .byte (.L909-.L906)/2 + 12661 0039 27 .byte (.L904-.L906)/2 + 12662 003a 27 .byte (.L904-.L906)/2 + 12663 003b 27 .byte (.L904-.L906)/2 + 12664 003c 1B .byte (.L908-.L906)/2 + 12665 003d 27 .byte (.L904-.L906)/2 + 12666 003e 27 .byte (.L904-.L906)/2 + 12667 003f 27 .byte (.L904-.L906)/2 + 12668 0040 1F .byte (.L907-.L906)/2 + 12669 0041 27 .byte (.L904-.L906)/2 + 12670 0042 27 .byte (.L904-.L906)/2 + 12671 0043 27 .byte (.L904-.L906)/2 + 12672 0044 23 .byte (.L905-.L906)/2 + 12673 0045 00 .p2align 1 + 12674 .L910: +2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 12675 .loc 1 2193 3 is_stmt 0 discriminator 1 view .LVU3746 + 12676 0046 0123 movs r3, #1 + 12677 0048 84F83E30 strb r3, [r4, #62] +2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12678 .loc 1 2194 3 is_stmt 1 view .LVU3747 +2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12679 .loc 1 2194 3 is_stmt 0 discriminator 1 view .LVU3748 + 12680 004c 84F84430 strb r3, [r4, #68] + 12681 0050 09E0 b .L911 + 12682 .L909: +2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 12683 .loc 1 2193 3 discriminator 3 view .LVU3749 + 12684 0052 0123 movs r3, #1 + 12685 0054 84F83F30 strb r3, [r4, #63] +2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12686 .loc 1 2194 3 is_stmt 1 view .LVU3750 + 12687 .L912: +2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12688 .loc 1 2194 3 is_stmt 0 discriminator 2 view .LVU3751 + 12689 0058 042D cmp r5, #4 + 12690 005a 16D0 beq .L916 +2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12691 .loc 1 2194 3 discriminator 4 view .LVU3752 + ARM GAS /tmp/ccGFzgX3.s page 416 + + + 12692 005c 082D cmp r5, #8 + 12693 005e 18D0 beq .L917 +2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12694 .loc 1 2194 3 discriminator 7 view .LVU3753 + 12695 0060 0123 movs r3, #1 + 12696 0062 84F84730 strb r3, [r4, #71] + 12697 .L911: +2197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12698 .loc 1 2197 3 is_stmt 1 view .LVU3754 +2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12699 .loc 1 2198 1 is_stmt 0 view .LVU3755 + 12700 0066 0020 movs r0, #0 + 12701 0068 38BD pop {r3, r4, r5, pc} + 12702 .LVL915: + 12703 .L908: +2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 12704 .loc 1 2193 3 discriminator 6 view .LVU3756 + 12705 006a 0123 movs r3, #1 + 12706 006c 84F84030 strb r3, [r4, #64] +2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12707 .loc 1 2194 3 is_stmt 1 view .LVU3757 + 12708 0070 F2E7 b .L912 + 12709 .L907: +2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 12710 .loc 1 2193 3 is_stmt 0 discriminator 9 view .LVU3758 + 12711 0072 0123 movs r3, #1 + 12712 0074 84F84130 strb r3, [r4, #65] +2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12713 .loc 1 2194 3 is_stmt 1 view .LVU3759 + 12714 0078 EEE7 b .L912 + 12715 .L905: +2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 12716 .loc 1 2193 3 is_stmt 0 discriminator 12 view .LVU3760 + 12717 007a 0123 movs r3, #1 + 12718 007c 84F84230 strb r3, [r4, #66] +2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12719 .loc 1 2194 3 is_stmt 1 view .LVU3761 + 12720 0080 EAE7 b .L912 + 12721 .L904: +2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 12722 .loc 1 2193 3 is_stmt 0 discriminator 13 view .LVU3762 + 12723 0082 0123 movs r3, #1 + 12724 0084 84F84330 strb r3, [r4, #67] +2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12725 .loc 1 2194 3 is_stmt 1 view .LVU3763 + 12726 0088 E6E7 b .L912 + 12727 .L916: +2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12728 .loc 1 2194 3 is_stmt 0 discriminator 3 view .LVU3764 + 12729 008a 0123 movs r3, #1 + 12730 008c 84F84530 strb r3, [r4, #69] + 12731 0090 E9E7 b .L911 + 12732 .L917: +2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12733 .loc 1 2194 3 discriminator 6 view .LVU3765 + 12734 0092 0123 movs r3, #1 + 12735 0094 84F84630 strb r3, [r4, #70] + ARM GAS /tmp/ccGFzgX3.s page 417 + + + 12736 0098 E5E7 b .L911 + 12737 .cfi_endproc + 12738 .LFE176: + 12740 .section .text.HAL_TIM_IC_Start_IT,"ax",%progbits + 12741 .align 1 + 12742 .global HAL_TIM_IC_Start_IT + 12743 .syntax unified + 12744 .thumb + 12745 .thumb_func + 12747 HAL_TIM_IC_Start_IT: + 12748 .LVL916: + 12749 .LFB177: +2212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 12750 .loc 1 2212 1 is_stmt 1 view -0 + 12751 .cfi_startproc + 12752 @ args = 0, pretend = 0, frame = 0 + 12753 @ frame_needed = 0, uses_anonymous_args = 0 +2212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 12754 .loc 1 2212 1 is_stmt 0 view .LVU3767 + 12755 0000 10B5 push {r4, lr} + 12756 .LCFI100: + 12757 .cfi_def_cfa_offset 8 + 12758 .cfi_offset 4, -8 + 12759 .cfi_offset 14, -4 + 12760 0002 0446 mov r4, r0 +2213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 12761 .loc 1 2213 3 is_stmt 1 view .LVU3768 + 12762 .LVL917: +2214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12763 .loc 1 2214 3 view .LVU3769 +2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 12764 .loc 1 2216 3 view .LVU3770 + 12765 0004 1029 cmp r1, #16 + 12766 0006 33D8 bhi .L919 + 12767 0008 DFE801F0 tbb [pc, r1] + 12768 .L921: + 12769 000c 09 .byte (.L925-.L921)/2 + 12770 000d 32 .byte (.L919-.L921)/2 + 12771 000e 32 .byte (.L919-.L921)/2 + 12772 000f 32 .byte (.L919-.L921)/2 + 12773 0010 22 .byte (.L924-.L921)/2 + 12774 0011 32 .byte (.L919-.L921)/2 + 12775 0012 32 .byte (.L919-.L921)/2 + 12776 0013 32 .byte (.L919-.L921)/2 + 12777 0014 26 .byte (.L923-.L921)/2 + 12778 0015 32 .byte (.L919-.L921)/2 + 12779 0016 32 .byte (.L919-.L921)/2 + 12780 0017 32 .byte (.L919-.L921)/2 + 12781 0018 2A .byte (.L922-.L921)/2 + 12782 0019 32 .byte (.L919-.L921)/2 + 12783 001a 32 .byte (.L919-.L921)/2 + 12784 001b 32 .byte (.L919-.L921)/2 + 12785 001c 2E .byte (.L920-.L921)/2 + 12786 001d 00 .p2align 1 + 12787 .L925: +2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 12788 .loc 1 2216 47 is_stmt 0 discriminator 1 view .LVU3771 + ARM GAS /tmp/ccGFzgX3.s page 418 + + + 12789 001e 90F83E20 ldrb r2, [r0, #62] @ zero_extendqisi2 + 12790 0022 D2B2 uxtb r2, r2 + 12791 .L926: + 12792 .LVL918: +2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12793 .loc 1 2217 3 is_stmt 1 view .LVU3772 +2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12794 .loc 1 2217 61 is_stmt 0 view .LVU3773 + 12795 0024 41BB cbnz r1, .L927 +2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12796 .loc 1 2217 61 discriminator 1 view .LVU3774 + 12797 0026 94F84430 ldrb r3, [r4, #68] @ zero_extendqisi2 + 12798 002a DBB2 uxtb r3, r3 + 12799 .L928: + 12800 .LVL919: +2220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12801 .loc 1 2220 3 is_stmt 1 view .LVU3775 +2223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + 12802 .loc 1 2223 3 view .LVU3776 +2223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + 12803 .loc 1 2223 6 is_stmt 0 view .LVU3777 + 12804 002c 012B cmp r3, #1 + 12805 002e 08BF it eq + 12806 0030 012A cmpeq r2, #1 + 12807 0032 40F0B080 bne .L951 +2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 12808 .loc 1 2230 3 is_stmt 1 view .LVU3778 + 12809 0036 1029 cmp r1, #16 + 12810 0038 55D8 bhi .L932 + 12811 003a DFE801F0 tbb [pc, r1] + 12812 .LVL920: + 12813 .L934: + 12814 003e 2D .byte (.L938-.L934)/2 + 12815 003f 54 .byte (.L932-.L934)/2 + 12816 0040 54 .byte (.L932-.L934)/2 + 12817 0041 54 .byte (.L932-.L934)/2 + 12818 0042 33 .byte (.L937-.L934)/2 + 12819 0043 54 .byte (.L932-.L934)/2 + 12820 0044 54 .byte (.L932-.L934)/2 + 12821 0045 54 .byte (.L932-.L934)/2 + 12822 0046 48 .byte (.L936-.L934)/2 + 12823 0047 54 .byte (.L932-.L934)/2 + 12824 0048 54 .byte (.L932-.L934)/2 + 12825 0049 54 .byte (.L932-.L934)/2 + 12826 004a 4C .byte (.L935-.L934)/2 + 12827 004b 54 .byte (.L932-.L934)/2 + 12828 004c 54 .byte (.L932-.L934)/2 + 12829 004d 54 .byte (.L932-.L934)/2 + 12830 004e 50 .byte (.L933-.L934)/2 + 12831 004f 00 .p2align 1 + 12832 .L924: +2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 12833 .loc 1 2216 47 is_stmt 0 discriminator 4 view .LVU3779 + 12834 0050 90F83F20 ldrb r2, [r0, #63] @ zero_extendqisi2 + 12835 0054 D2B2 uxtb r2, r2 + 12836 0056 E5E7 b .L926 + 12837 .L923: + ARM GAS /tmp/ccGFzgX3.s page 419 + + +2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 12838 .loc 1 2216 47 discriminator 7 view .LVU3780 + 12839 0058 90F84020 ldrb r2, [r0, #64] @ zero_extendqisi2 + 12840 005c D2B2 uxtb r2, r2 + 12841 005e E1E7 b .L926 + 12842 .L922: +2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 12843 .loc 1 2216 47 discriminator 10 view .LVU3781 + 12844 0060 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2 + 12845 0064 D2B2 uxtb r2, r2 + 12846 0066 DDE7 b .L926 + 12847 .L920: +2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 12848 .loc 1 2216 47 discriminator 13 view .LVU3782 + 12849 0068 90F84220 ldrb r2, [r0, #66] @ zero_extendqisi2 + 12850 006c D2B2 uxtb r2, r2 + 12851 006e D9E7 b .L926 + 12852 .L919: +2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 12853 .loc 1 2216 47 discriminator 14 view .LVU3783 + 12854 0070 90F84320 ldrb r2, [r0, #67] @ zero_extendqisi2 + 12855 0074 D2B2 uxtb r2, r2 + 12856 0076 D5E7 b .L926 + 12857 .LVL921: + 12858 .L927: +2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12859 .loc 1 2217 61 discriminator 2 view .LVU3784 + 12860 0078 0429 cmp r1, #4 + 12861 007a 05D0 beq .L957 +2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12862 .loc 1 2217 61 discriminator 5 view .LVU3785 + 12863 007c 0829 cmp r1, #8 + 12864 007e 07D0 beq .L958 +2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12865 .loc 1 2217 61 discriminator 8 view .LVU3786 + 12866 0080 94F84730 ldrb r3, [r4, #71] @ zero_extendqisi2 + 12867 0084 DBB2 uxtb r3, r3 + 12868 0086 D1E7 b .L928 + 12869 .L957: +2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12870 .loc 1 2217 61 discriminator 4 view .LVU3787 + 12871 0088 94F84530 ldrb r3, [r4, #69] @ zero_extendqisi2 + 12872 008c DBB2 uxtb r3, r3 + 12873 008e CDE7 b .L928 + 12874 .L958: +2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12875 .loc 1 2217 61 discriminator 7 view .LVU3788 + 12876 0090 94F84630 ldrb r3, [r4, #70] @ zero_extendqisi2 + 12877 0094 DBB2 uxtb r3, r3 + 12878 0096 C9E7 b .L928 + 12879 .LVL922: + 12880 .L938: +2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 12881 .loc 1 2230 3 discriminator 1 view .LVU3789 + 12882 0098 0223 movs r3, #2 + 12883 009a 84F83E30 strb r3, [r4, #62] +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 420 + + + 12884 .loc 1 2231 3 is_stmt 1 view .LVU3790 +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12885 .loc 1 2231 3 is_stmt 0 discriminator 1 view .LVU3791 + 12886 009e 84F84430 strb r3, [r4, #68] + 12887 00a2 09E0 b .L939 + 12888 .L937: +2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 12889 .loc 1 2230 3 discriminator 3 view .LVU3792 + 12890 00a4 0223 movs r3, #2 + 12891 00a6 84F83F30 strb r3, [r4, #63] +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12892 .loc 1 2231 3 is_stmt 1 view .LVU3793 + 12893 .L940: +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12894 .loc 1 2231 3 is_stmt 0 discriminator 2 view .LVU3794 + 12895 00aa 0429 cmp r1, #4 + 12896 00ac 1FD0 beq .L959 +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12897 .loc 1 2231 3 discriminator 4 view .LVU3795 + 12898 00ae 0829 cmp r1, #8 + 12899 00b0 4ED0 beq .L960 +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12900 .loc 1 2231 3 discriminator 7 view .LVU3796 + 12901 00b2 0223 movs r3, #2 + 12902 00b4 84F84730 strb r3, [r4, #71] + 12903 .L939: +2233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12904 .loc 1 2233 3 is_stmt 1 view .LVU3797 + 12905 00b8 0C29 cmp r1, #12 + 12906 00ba 6ED8 bhi .L952 + 12907 00bc DFE801F0 tbb [pc, r1] + 12908 .L946: + 12909 00c0 51 .byte (.L947-.L946)/2 + 12910 00c1 6D .byte (.L952-.L946)/2 + 12911 00c2 6D .byte (.L952-.L946)/2 + 12912 00c3 6D .byte (.L952-.L946)/2 + 12913 00c4 1A .byte (.L942-.L946)/2 + 12914 00c5 6D .byte (.L952-.L946)/2 + 12915 00c6 6D .byte (.L952-.L946)/2 + 12916 00c7 6D .byte (.L952-.L946)/2 + 12917 00c8 4B .byte (.L944-.L946)/2 + 12918 00c9 6D .byte (.L952-.L946)/2 + 12919 00ca 6D .byte (.L952-.L946)/2 + 12920 00cb 6D .byte (.L952-.L946)/2 + 12921 00cc 57 .byte (.L945-.L946)/2 + 12922 00cd 00 .p2align 1 + 12923 .L936: +2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 12924 .loc 1 2230 3 is_stmt 0 discriminator 6 view .LVU3798 + 12925 00ce 0223 movs r3, #2 + 12926 00d0 84F84030 strb r3, [r4, #64] +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12927 .loc 1 2231 3 is_stmt 1 view .LVU3799 + 12928 00d4 E9E7 b .L940 + 12929 .L935: +2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 12930 .loc 1 2230 3 is_stmt 0 discriminator 9 view .LVU3800 + ARM GAS /tmp/ccGFzgX3.s page 421 + + + 12931 00d6 0223 movs r3, #2 + 12932 00d8 84F84130 strb r3, [r4, #65] +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12933 .loc 1 2231 3 is_stmt 1 view .LVU3801 + 12934 00dc E5E7 b .L940 + 12935 .L933: +2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 12936 .loc 1 2230 3 is_stmt 0 discriminator 12 view .LVU3802 + 12937 00de 0223 movs r3, #2 + 12938 00e0 84F84230 strb r3, [r4, #66] +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12939 .loc 1 2231 3 is_stmt 1 view .LVU3803 + 12940 00e4 E1E7 b .L940 + 12941 .L932: +2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 12942 .loc 1 2230 3 is_stmt 0 discriminator 13 view .LVU3804 + 12943 00e6 0223 movs r3, #2 + 12944 00e8 84F84330 strb r3, [r4, #67] +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12945 .loc 1 2231 3 is_stmt 1 view .LVU3805 + 12946 00ec DDE7 b .L940 + 12947 .L959: +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12948 .loc 1 2231 3 is_stmt 0 discriminator 3 view .LVU3806 + 12949 00ee 0223 movs r3, #2 + 12950 00f0 84F84530 strb r3, [r4, #69] +2233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12951 .loc 1 2233 3 is_stmt 1 view .LVU3807 + 12952 .L942: +2245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 12953 .loc 1 2245 7 view .LVU3808 + 12954 00f4 2268 ldr r2, [r4] + 12955 .LVL923: +2245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 12956 .loc 1 2245 7 is_stmt 0 view .LVU3809 + 12957 00f6 D368 ldr r3, [r2, #12] + 12958 00f8 43F00403 orr r3, r3, #4 + 12959 00fc D360 str r3, [r2, #12] +2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 12960 .loc 1 2246 7 is_stmt 1 view .LVU3810 +2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12961 .loc 1 2268 3 view .LVU3811 + 12962 .L948: +2271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12963 .loc 1 2271 5 view .LVU3812 + 12964 00fe 0122 movs r2, #1 + 12965 0100 2068 ldr r0, [r4] + 12966 .LVL924: +2271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 12967 .loc 1 2271 5 is_stmt 0 view .LVU3813 + 12968 0102 FFF7FEFF bl TIM_CCxChannelCmd + 12969 .LVL925: +2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12970 .loc 1 2274 5 is_stmt 1 view .LVU3814 +2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12971 .loc 1 2274 9 is_stmt 0 view .LVU3815 + 12972 0106 2368 ldr r3, [r4] + ARM GAS /tmp/ccGFzgX3.s page 422 + + +2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12973 .loc 1 2274 8 view .LVU3816 + 12974 0108 264A ldr r2, .L961 + 12975 010a B3F1804F cmp r3, #1073741824 + 12976 010e 18BF it ne + 12977 0110 9342 cmpne r3, r2 + 12978 0112 32D0 beq .L949 +2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12979 .loc 1 2274 9 discriminator 1 view .LVU3817 + 12980 0114 A2F57C42 sub r2, r2, #64512 + 12981 0118 9342 cmp r3, r2 + 12982 011a 2ED0 beq .L949 +2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12983 .loc 1 2274 9 discriminator 2 view .LVU3818 + 12984 011c 02F58062 add r2, r2, #1024 + 12985 0120 9342 cmp r3, r2 + 12986 0122 2AD0 beq .L949 +2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12987 .loc 1 2274 9 discriminator 3 view .LVU3819 + 12988 0124 02F58062 add r2, r2, #1024 + 12989 0128 9342 cmp r3, r2 + 12990 012a 26D0 beq .L949 +2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12991 .loc 1 2274 9 discriminator 4 view .LVU3820 + 12992 012c 02F57842 add r2, r2, #63488 + 12993 0130 9342 cmp r3, r2 + 12994 0132 22D0 beq .L949 +2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12995 .loc 1 2274 9 discriminator 5 view .LVU3821 + 12996 0134 02F57052 add r2, r2, #15360 + 12997 0138 9342 cmp r3, r2 + 12998 013a 1ED0 beq .L949 +2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 12999 .loc 1 2274 9 discriminator 6 view .LVU3822 + 13000 013c A2F59432 sub r2, r2, #75776 + 13001 0140 9342 cmp r3, r2 + 13002 0142 1AD0 beq .L949 +2284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13003 .loc 1 2284 7 is_stmt 1 view .LVU3823 + 13004 0144 1A68 ldr r2, [r3] + 13005 0146 42F00102 orr r2, r2, #1 + 13006 014a 1A60 str r2, [r3] + 13007 014c 0020 movs r0, #0 + 13008 014e 23E0 b .L931 + 13009 .LVL926: + 13010 .L960: +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13011 .loc 1 2231 3 is_stmt 0 discriminator 6 view .LVU3824 + 13012 0150 0223 movs r3, #2 + 13013 0152 84F84630 strb r3, [r4, #70] +2233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13014 .loc 1 2233 3 is_stmt 1 view .LVU3825 + 13015 .L944: +2252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13016 .loc 1 2252 7 view .LVU3826 + 13017 0156 2268 ldr r2, [r4] + 13018 .LVL927: + ARM GAS /tmp/ccGFzgX3.s page 423 + + +2252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13019 .loc 1 2252 7 is_stmt 0 view .LVU3827 + 13020 0158 D368 ldr r3, [r2, #12] + 13021 015a 43F00803 orr r3, r3, #8 + 13022 015e D360 str r3, [r2, #12] +2253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13023 .loc 1 2253 7 is_stmt 1 view .LVU3828 +2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13024 .loc 1 2268 3 view .LVU3829 + 13025 0160 CDE7 b .L948 + 13026 .LVL928: + 13027 .L947: +2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13028 .loc 1 2238 7 view .LVU3830 + 13029 0162 2268 ldr r2, [r4] + 13030 .LVL929: +2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13031 .loc 1 2238 7 is_stmt 0 view .LVU3831 + 13032 0164 D368 ldr r3, [r2, #12] + 13033 0166 43F00203 orr r3, r3, #2 + 13034 016a D360 str r3, [r2, #12] +2239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13035 .loc 1 2239 7 is_stmt 1 view .LVU3832 +2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13036 .loc 1 2268 3 view .LVU3833 + 13037 016c C7E7 b .L948 + 13038 .LVL930: + 13039 .L945: +2259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13040 .loc 1 2259 7 view .LVU3834 + 13041 016e 2268 ldr r2, [r4] + 13042 .LVL931: +2259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13043 .loc 1 2259 7 is_stmt 0 view .LVU3835 + 13044 0170 D368 ldr r3, [r2, #12] + 13045 0172 43F01003 orr r3, r3, #16 + 13046 0176 D360 str r3, [r2, #12] +2260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13047 .loc 1 2260 7 is_stmt 1 view .LVU3836 +2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13048 .loc 1 2268 3 view .LVU3837 + 13049 0178 C1E7 b .L948 + 13050 .LVL932: + 13051 .L949: +2276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 13052 .loc 1 2276 7 view .LVU3838 +2276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 13053 .loc 1 2276 31 is_stmt 0 view .LVU3839 + 13054 017a 9968 ldr r1, [r3, #8] +2276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 13055 .loc 1 2276 15 view .LVU3840 + 13056 017c 0A4A ldr r2, .L961+4 + 13057 017e 0A40 ands r2, r2, r1 + 13058 .LVL933: +2277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13059 .loc 1 2277 7 is_stmt 1 view .LVU3841 +2277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 424 + + + 13060 .loc 1 2277 10 is_stmt 0 view .LVU3842 + 13061 0180 062A cmp r2, #6 + 13062 0182 18BF it ne + 13063 0184 B2F5803F cmpne r2, #65536 + 13064 0188 09D0 beq .L953 +2279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13065 .loc 1 2279 9 is_stmt 1 view .LVU3843 + 13066 018a 1A68 ldr r2, [r3] + 13067 .LVL934: +2279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13068 .loc 1 2279 9 is_stmt 0 view .LVU3844 + 13069 018c 42F00102 orr r2, r2, #1 + 13070 0190 1A60 str r2, [r3] + 13071 0192 0020 movs r0, #0 + 13072 0194 00E0 b .L931 + 13073 .LVL935: + 13074 .L951: +2226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13075 .loc 1 2226 12 view .LVU3845 + 13076 0196 0120 movs r0, #1 + 13077 .LVL936: + 13078 .L931: +2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13079 .loc 1 2290 1 view .LVU3846 + 13080 0198 10BD pop {r4, pc} + 13081 .LVL937: + 13082 .L952: +2233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13083 .loc 1 2233 3 view .LVU3847 + 13084 019a 0120 movs r0, #1 + 13085 .LVL938: +2233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13086 .loc 1 2233 3 view .LVU3848 + 13087 019c FCE7 b .L931 + 13088 .LVL939: + 13089 .L953: +2233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13090 .loc 1 2233 3 view .LVU3849 + 13091 019e 0020 movs r0, #0 + 13092 01a0 FAE7 b .L931 + 13093 .L962: + 13094 01a2 00BF .align 2 + 13095 .L961: + 13096 01a4 00000140 .word 1073807360 + 13097 01a8 07000100 .word 65543 + 13098 .cfi_endproc + 13099 .LFE177: + 13101 .section .text.HAL_TIM_IC_Stop_IT,"ax",%progbits + 13102 .align 1 + 13103 .global HAL_TIM_IC_Stop_IT + 13104 .syntax unified + 13105 .thumb + 13106 .thumb_func + 13108 HAL_TIM_IC_Stop_IT: + 13109 .LVL940: + 13110 .LFB178: +2304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + ARM GAS /tmp/ccGFzgX3.s page 425 + + + 13111 .loc 1 2304 1 is_stmt 1 view -0 + 13112 .cfi_startproc + 13113 @ args = 0, pretend = 0, frame = 0 + 13114 @ frame_needed = 0, uses_anonymous_args = 0 +2304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 13115 .loc 1 2304 1 is_stmt 0 view .LVU3851 + 13116 0000 38B5 push {r3, r4, r5, lr} + 13117 .LCFI101: + 13118 .cfi_def_cfa_offset 16 + 13119 .cfi_offset 3, -16 + 13120 .cfi_offset 4, -12 + 13121 .cfi_offset 5, -8 + 13122 .cfi_offset 14, -4 + 13123 0002 0546 mov r5, r0 + 13124 0004 0C46 mov r4, r1 +2305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13125 .loc 1 2305 3 is_stmt 1 view .LVU3852 + 13126 .LVL941: +2308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13127 .loc 1 2308 3 view .LVU3853 +2310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13128 .loc 1 2310 3 view .LVU3854 + 13129 0006 0C29 cmp r1, #12 + 13130 0008 6DD8 bhi .L982 + 13131 000a DFE801F0 tbb [pc, r1] + 13132 .L966: + 13133 000e 07 .byte (.L969-.L966)/2 + 13134 000f 6C .byte (.L982-.L966)/2 + 13135 0010 6C .byte (.L982-.L966)/2 + 13136 0011 6C .byte (.L982-.L966)/2 + 13137 0012 2D .byte (.L968-.L966)/2 + 13138 0013 6C .byte (.L982-.L966)/2 + 13139 0014 6C .byte (.L982-.L966)/2 + 13140 0015 6C .byte (.L982-.L966)/2 + 13141 0016 33 .byte (.L967-.L966)/2 + 13142 0017 6C .byte (.L982-.L966)/2 + 13143 0018 6C .byte (.L982-.L966)/2 + 13144 0019 6C .byte (.L982-.L966)/2 + 13145 001a 39 .byte (.L965-.L966)/2 + 13146 001b 00 .p2align 1 + 13147 .L969: +2315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13148 .loc 1 2315 7 view .LVU3855 + 13149 001c 0268 ldr r2, [r0] + 13150 001e D368 ldr r3, [r2, #12] + 13151 0020 23F00203 bic r3, r3, #2 + 13152 0024 D360 str r3, [r2, #12] +2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13153 .loc 1 2316 7 view .LVU3856 +2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13154 .loc 1 2345 3 view .LVU3857 + 13155 .L970: +2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13156 .loc 1 2348 5 view .LVU3858 + 13157 0026 0022 movs r2, #0 + 13158 0028 2146 mov r1, r4 + 13159 .LVL942: + ARM GAS /tmp/ccGFzgX3.s page 426 + + +2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13160 .loc 1 2348 5 is_stmt 0 view .LVU3859 + 13161 002a 2868 ldr r0, [r5] + 13162 .LVL943: +2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13163 .loc 1 2348 5 view .LVU3860 + 13164 002c FFF7FEFF bl TIM_CCxChannelCmd + 13165 .LVL944: +2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13166 .loc 1 2351 5 is_stmt 1 view .LVU3861 +2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13167 .loc 1 2351 5 view .LVU3862 + 13168 0030 2B68 ldr r3, [r5] + 13169 0032 196A ldr r1, [r3, #32] + 13170 0034 41F21112 movw r2, #4369 + 13171 0038 1142 tst r1, r2 + 13172 003a 08D1 bne .L971 +2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13173 .loc 1 2351 5 discriminator 1 view .LVU3863 + 13174 003c 196A ldr r1, [r3, #32] + 13175 003e 40F24442 movw r2, #1092 + 13176 0042 1142 tst r1, r2 + 13177 0044 03D1 bne .L971 +2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13178 .loc 1 2351 5 discriminator 3 view .LVU3864 + 13179 0046 1A68 ldr r2, [r3] + 13180 0048 22F00102 bic r2, r2, #1 + 13181 004c 1A60 str r2, [r3] + 13182 .L971: +2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13183 .loc 1 2351 5 discriminator 5 view .LVU3865 +2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 13184 .loc 1 2354 5 view .LVU3866 + 13185 004e 102C cmp r4, #16 + 13186 0050 3BD8 bhi .L972 + 13187 0052 DFE804F0 tbb [pc, r4] + 13188 .L974: + 13189 0056 1B .byte (.L978-.L974)/2 + 13190 0057 3A .byte (.L972-.L974)/2 + 13191 0058 3A .byte (.L972-.L974)/2 + 13192 0059 3A .byte (.L972-.L974)/2 + 13193 005a 22 .byte (.L977-.L974)/2 + 13194 005b 3A .byte (.L972-.L974)/2 + 13195 005c 3A .byte (.L972-.L974)/2 + 13196 005d 3A .byte (.L972-.L974)/2 + 13197 005e 2E .byte (.L976-.L974)/2 + 13198 005f 3A .byte (.L972-.L974)/2 + 13199 0060 3A .byte (.L972-.L974)/2 + 13200 0061 3A .byte (.L972-.L974)/2 + 13201 0062 32 .byte (.L975-.L974)/2 + 13202 0063 3A .byte (.L972-.L974)/2 + 13203 0064 3A .byte (.L972-.L974)/2 + 13204 0065 3A .byte (.L972-.L974)/2 + 13205 0066 36 .byte (.L973-.L974)/2 + 13206 .LVL945: + 13207 0067 00 .p2align 1 + 13208 .L968: + ARM GAS /tmp/ccGFzgX3.s page 427 + + +2322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13209 .loc 1 2322 7 view .LVU3867 + 13210 0068 0268 ldr r2, [r0] + 13211 006a D368 ldr r3, [r2, #12] + 13212 006c 23F00403 bic r3, r3, #4 + 13213 0070 D360 str r3, [r2, #12] +2323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13214 .loc 1 2323 7 view .LVU3868 +2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13215 .loc 1 2345 3 view .LVU3869 + 13216 0072 D8E7 b .L970 + 13217 .L967: +2329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13218 .loc 1 2329 7 view .LVU3870 + 13219 0074 0268 ldr r2, [r0] + 13220 0076 D368 ldr r3, [r2, #12] + 13221 0078 23F00803 bic r3, r3, #8 + 13222 007c D360 str r3, [r2, #12] +2330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13223 .loc 1 2330 7 view .LVU3871 +2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13224 .loc 1 2345 3 view .LVU3872 + 13225 007e D2E7 b .L970 + 13226 .L965: +2336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13227 .loc 1 2336 7 view .LVU3873 + 13228 0080 0268 ldr r2, [r0] + 13229 0082 D368 ldr r3, [r2, #12] + 13230 0084 23F01003 bic r3, r3, #16 + 13231 0088 D360 str r3, [r2, #12] +2337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13232 .loc 1 2337 7 view .LVU3874 +2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13233 .loc 1 2345 3 view .LVU3875 + 13234 008a CCE7 b .L970 + 13235 .LVL946: + 13236 .L978: +2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 13237 .loc 1 2354 5 is_stmt 0 discriminator 1 view .LVU3876 + 13238 008c 0123 movs r3, #1 + 13239 008e 85F83E30 strb r3, [r5, #62] +2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13240 .loc 1 2355 5 is_stmt 1 view .LVU3877 +2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13241 .loc 1 2355 5 is_stmt 0 discriminator 1 view .LVU3878 + 13242 0092 85F84430 strb r3, [r5, #68] + 13243 0096 0020 movs r0, #0 + 13244 0098 26E0 b .L964 + 13245 .L977: +2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 13246 .loc 1 2354 5 discriminator 3 view .LVU3879 + 13247 009a 0123 movs r3, #1 + 13248 009c 85F83F30 strb r3, [r5, #63] +2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13249 .loc 1 2355 5 is_stmt 1 view .LVU3880 + 13250 .L979: +2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + ARM GAS /tmp/ccGFzgX3.s page 428 + + + 13251 .loc 1 2355 5 is_stmt 0 discriminator 2 view .LVU3881 + 13252 00a0 042C cmp r4, #4 + 13253 00a2 16D0 beq .L984 +2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13254 .loc 1 2355 5 discriminator 4 view .LVU3882 + 13255 00a4 082C cmp r4, #8 + 13256 00a6 19D0 beq .L985 +2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13257 .loc 1 2355 5 discriminator 7 view .LVU3883 + 13258 00a8 0123 movs r3, #1 + 13259 00aa 85F84730 strb r3, [r5, #71] + 13260 00ae 0020 movs r0, #0 + 13261 00b0 1AE0 b .L964 + 13262 .L976: +2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 13263 .loc 1 2354 5 discriminator 6 view .LVU3884 + 13264 00b2 0123 movs r3, #1 + 13265 00b4 85F84030 strb r3, [r5, #64] +2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13266 .loc 1 2355 5 is_stmt 1 view .LVU3885 + 13267 00b8 F2E7 b .L979 + 13268 .L975: +2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 13269 .loc 1 2354 5 is_stmt 0 discriminator 9 view .LVU3886 + 13270 00ba 0123 movs r3, #1 + 13271 00bc 85F84130 strb r3, [r5, #65] +2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13272 .loc 1 2355 5 is_stmt 1 view .LVU3887 + 13273 00c0 EEE7 b .L979 + 13274 .L973: +2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 13275 .loc 1 2354 5 is_stmt 0 discriminator 12 view .LVU3888 + 13276 00c2 0123 movs r3, #1 + 13277 00c4 85F84230 strb r3, [r5, #66] +2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13278 .loc 1 2355 5 is_stmt 1 view .LVU3889 + 13279 00c8 EAE7 b .L979 + 13280 .L972: +2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 13281 .loc 1 2354 5 is_stmt 0 discriminator 13 view .LVU3890 + 13282 00ca 0123 movs r3, #1 + 13283 00cc 85F84330 strb r3, [r5, #67] +2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13284 .loc 1 2355 5 is_stmt 1 view .LVU3891 + 13285 00d0 E6E7 b .L979 + 13286 .L984: +2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13287 .loc 1 2355 5 is_stmt 0 discriminator 3 view .LVU3892 + 13288 00d2 0123 movs r3, #1 + 13289 00d4 85F84530 strb r3, [r5, #69] + 13290 00d8 0020 movs r0, #0 + 13291 00da 05E0 b .L964 + 13292 .L985: +2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13293 .loc 1 2355 5 discriminator 6 view .LVU3893 + 13294 00dc 0123 movs r3, #1 + 13295 00de 85F84630 strb r3, [r5, #70] + ARM GAS /tmp/ccGFzgX3.s page 429 + + + 13296 00e2 0020 movs r0, #0 + 13297 00e4 00E0 b .L964 + 13298 .LVL947: + 13299 .L982: +2310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13300 .loc 1 2310 3 view .LVU3894 + 13301 00e6 0120 movs r0, #1 + 13302 .LVL948: + 13303 .L964: +2359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13304 .loc 1 2359 3 is_stmt 1 view .LVU3895 +2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13305 .loc 1 2360 1 is_stmt 0 view .LVU3896 + 13306 00e8 38BD pop {r3, r4, r5, pc} +2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13307 .loc 1 2360 1 view .LVU3897 + 13308 .cfi_endproc + 13309 .LFE178: + 13311 .section .text.HAL_TIM_IC_Start_DMA,"ax",%progbits + 13312 .align 1 + 13313 .global HAL_TIM_IC_Start_DMA + 13314 .syntax unified + 13315 .thumb + 13316 .thumb_func + 13318 HAL_TIM_IC_Start_DMA: + 13319 .LVL949: + 13320 .LFB179: +2376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 13321 .loc 1 2376 1 is_stmt 1 view -0 + 13322 .cfi_startproc + 13323 @ args = 0, pretend = 0, frame = 0 + 13324 @ frame_needed = 0, uses_anonymous_args = 0 +2376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 13325 .loc 1 2376 1 is_stmt 0 view .LVU3899 + 13326 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 13327 .LCFI102: + 13328 .cfi_def_cfa_offset 24 + 13329 .cfi_offset 3, -24 + 13330 .cfi_offset 4, -20 + 13331 .cfi_offset 5, -16 + 13332 .cfi_offset 6, -12 + 13333 .cfi_offset 7, -8 + 13334 .cfi_offset 14, -4 + 13335 0002 0546 mov r5, r0 + 13336 0004 0C46 mov r4, r1 + 13337 0006 1646 mov r6, r2 + 13338 0008 1F46 mov r7, r3 +2377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** uint32_t tmpsmcr; + 13339 .loc 1 2377 3 is_stmt 1 view .LVU3900 + 13340 .LVL950: +2378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13341 .loc 1 2378 3 view .LVU3901 +2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 13342 .loc 1 2380 3 view .LVU3902 + 13343 000a 1029 cmp r1, #16 + 13344 000c 3DD8 bhi .L987 + 13345 000e DFE801F0 tbb [pc, r1] + ARM GAS /tmp/ccGFzgX3.s page 430 + + + 13346 .LVL951: + 13347 .L989: + 13348 0012 09 .byte (.L993-.L989)/2 + 13349 0013 3C .byte (.L987-.L989)/2 + 13350 0014 3C .byte (.L987-.L989)/2 + 13351 0015 3C .byte (.L987-.L989)/2 + 13352 0016 2C .byte (.L992-.L989)/2 + 13353 0017 3C .byte (.L987-.L989)/2 + 13354 0018 3C .byte (.L987-.L989)/2 + 13355 0019 3C .byte (.L987-.L989)/2 + 13356 001a 30 .byte (.L991-.L989)/2 + 13357 001b 3C .byte (.L987-.L989)/2 + 13358 001c 3C .byte (.L987-.L989)/2 + 13359 001d 3C .byte (.L987-.L989)/2 + 13360 001e 34 .byte (.L990-.L989)/2 + 13361 001f 3C .byte (.L987-.L989)/2 + 13362 0020 3C .byte (.L987-.L989)/2 + 13363 0021 3C .byte (.L987-.L989)/2 + 13364 0022 38 .byte (.L988-.L989)/2 + 13365 0023 00 .p2align 1 + 13366 .L993: +2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 13367 .loc 1 2380 47 is_stmt 0 discriminator 1 view .LVU3903 + 13368 0024 90F83E30 ldrb r3, [r0, #62] @ zero_extendqisi2 + 13369 0028 DBB2 uxtb r3, r3 + 13370 .L994: + 13371 .LVL952: +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13372 .loc 1 2381 3 is_stmt 1 view .LVU3904 +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13373 .loc 1 2381 61 is_stmt 0 view .LVU3905 + 13374 002a 94BB cbnz r4, .L995 +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13375 .loc 1 2381 61 discriminator 1 view .LVU3906 + 13376 002c 95F84410 ldrb r1, [r5, #68] @ zero_extendqisi2 + 13377 .LVL953: +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13378 .loc 1 2381 61 discriminator 1 view .LVU3907 + 13379 0030 C9B2 uxtb r1, r1 + 13380 .L996: + 13381 .LVL954: +2384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + 13382 .loc 1 2384 3 is_stmt 1 view .LVU3908 +2385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13383 .loc 1 2385 3 view .LVU3909 +2388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + 13384 .loc 1 2388 3 view .LVU3910 +2388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + 13385 .loc 1 2388 6 is_stmt 0 view .LVU3911 + 13386 0032 0229 cmp r1, #2 + 13387 0034 18BF it ne + 13388 0036 022B cmpne r3, #2 + 13389 0038 00F00781 beq .L1019 +2393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + 13390 .loc 1 2393 8 is_stmt 1 view .LVU3912 +2393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + 13391 .loc 1 2393 11 is_stmt 0 view .LVU3913 + ARM GAS /tmp/ccGFzgX3.s page 431 + + + 13392 003c 012B cmp r3, #1 + 13393 003e 08BF it eq + 13394 0040 0129 cmpeq r1, #1 + 13395 0042 40F00481 bne .L1020 +2396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13396 .loc 1 2396 5 is_stmt 1 view .LVU3914 +2396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13397 .loc 1 2396 8 is_stmt 0 view .LVU3915 + 13398 0046 002F cmp r7, #0 + 13399 0048 18BF it ne + 13400 004a 002E cmpne r6, #0 + 13401 004c 00F00181 beq .L1021 +2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 13402 .loc 1 2402 7 is_stmt 1 view .LVU3916 + 13403 0050 102C cmp r4, #16 + 13404 0052 5BD8 bhi .L1000 + 13405 0054 DFE804F0 tbb [pc, r4] + 13406 .LVL955: + 13407 .L1002: + 13408 0058 2D .byte (.L1006-.L1002)/2 + 13409 0059 5A .byte (.L1000-.L1002)/2 + 13410 005a 5A .byte (.L1000-.L1002)/2 + 13411 005b 5A .byte (.L1000-.L1002)/2 + 13412 005c 33 .byte (.L1005-.L1002)/2 + 13413 005d 5A .byte (.L1000-.L1002)/2 + 13414 005e 5A .byte (.L1000-.L1002)/2 + 13415 005f 5A .byte (.L1000-.L1002)/2 + 13416 0060 4E .byte (.L1004-.L1002)/2 + 13417 0061 5A .byte (.L1000-.L1002)/2 + 13418 0062 5A .byte (.L1000-.L1002)/2 + 13419 0063 5A .byte (.L1000-.L1002)/2 + 13420 0064 52 .byte (.L1003-.L1002)/2 + 13421 0065 5A .byte (.L1000-.L1002)/2 + 13422 0066 5A .byte (.L1000-.L1002)/2 + 13423 0067 5A .byte (.L1000-.L1002)/2 + 13424 0068 56 .byte (.L1001-.L1002)/2 + 13425 0069 00 .p2align 1 + 13426 .L992: +2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 13427 .loc 1 2380 47 is_stmt 0 discriminator 4 view .LVU3917 + 13428 006a 90F83F30 ldrb r3, [r0, #63] @ zero_extendqisi2 + 13429 006e DBB2 uxtb r3, r3 + 13430 0070 DBE7 b .L994 + 13431 .L991: +2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 13432 .loc 1 2380 47 discriminator 7 view .LVU3918 + 13433 0072 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 13434 0076 DBB2 uxtb r3, r3 + 13435 0078 D7E7 b .L994 + 13436 .L990: +2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 13437 .loc 1 2380 47 discriminator 10 view .LVU3919 + 13438 007a 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 13439 007e DBB2 uxtb r3, r3 + 13440 0080 D3E7 b .L994 + 13441 .L988: +2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + ARM GAS /tmp/ccGFzgX3.s page 432 + + + 13442 .loc 1 2380 47 discriminator 13 view .LVU3920 + 13443 0082 90F84230 ldrb r3, [r0, #66] @ zero_extendqisi2 + 13444 0086 DBB2 uxtb r3, r3 + 13445 0088 CFE7 b .L994 + 13446 .L987: +2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 13447 .loc 1 2380 47 discriminator 14 view .LVU3921 + 13448 008a 90F84330 ldrb r3, [r0, #67] @ zero_extendqisi2 + 13449 008e DBB2 uxtb r3, r3 + 13450 0090 CBE7 b .L994 + 13451 .LVL956: + 13452 .L995: +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13453 .loc 1 2381 61 discriminator 2 view .LVU3922 + 13454 0092 042C cmp r4, #4 + 13455 0094 05D0 beq .L1028 +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13456 .loc 1 2381 61 discriminator 5 view .LVU3923 + 13457 0096 082C cmp r4, #8 + 13458 0098 07D0 beq .L1029 +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13459 .loc 1 2381 61 discriminator 8 view .LVU3924 + 13460 009a 95F84710 ldrb r1, [r5, #71] @ zero_extendqisi2 + 13461 .LVL957: +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13462 .loc 1 2381 61 discriminator 8 view .LVU3925 + 13463 009e C9B2 uxtb r1, r1 + 13464 00a0 C7E7 b .L996 + 13465 .LVL958: + 13466 .L1028: +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13467 .loc 1 2381 61 discriminator 4 view .LVU3926 + 13468 00a2 95F84510 ldrb r1, [r5, #69] @ zero_extendqisi2 + 13469 .LVL959: +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13470 .loc 1 2381 61 discriminator 4 view .LVU3927 + 13471 00a6 C9B2 uxtb r1, r1 + 13472 00a8 C3E7 b .L996 + 13473 .LVL960: + 13474 .L1029: +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13475 .loc 1 2381 61 discriminator 7 view .LVU3928 + 13476 00aa 95F84610 ldrb r1, [r5, #70] @ zero_extendqisi2 + 13477 .LVL961: +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13478 .loc 1 2381 61 discriminator 7 view .LVU3929 + 13479 00ae C9B2 uxtb r1, r1 + 13480 00b0 BFE7 b .L996 + 13481 .LVL962: + 13482 .L1006: +2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 13483 .loc 1 2402 7 discriminator 1 view .LVU3930 + 13484 00b2 0223 movs r3, #2 + 13485 00b4 85F83E30 strb r3, [r5, #62] +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13486 .loc 1 2403 7 is_stmt 1 view .LVU3931 +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + ARM GAS /tmp/ccGFzgX3.s page 433 + + + 13487 .loc 1 2403 7 is_stmt 0 discriminator 1 view .LVU3932 + 13488 00b8 85F84430 strb r3, [r5, #68] + 13489 00bc 09E0 b .L1007 + 13490 .L1005: +2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 13491 .loc 1 2402 7 discriminator 3 view .LVU3933 + 13492 00be 0223 movs r3, #2 + 13493 00c0 85F83F30 strb r3, [r5, #63] +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13494 .loc 1 2403 7 is_stmt 1 view .LVU3934 + 13495 .L1008: +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13496 .loc 1 2403 7 is_stmt 0 discriminator 2 view .LVU3935 + 13497 00c4 042C cmp r4, #4 + 13498 00c6 25D0 beq .L1030 +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13499 .loc 1 2403 7 discriminator 4 view .LVU3936 + 13500 00c8 082C cmp r4, #8 + 13501 00ca 27D0 beq .L1031 +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13502 .loc 1 2403 7 discriminator 7 view .LVU3937 + 13503 00cc 0223 movs r3, #2 + 13504 00ce 85F84730 strb r3, [r5, #71] + 13505 .L1007: +2412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13506 .loc 1 2412 3 is_stmt 1 view .LVU3938 + 13507 00d2 0122 movs r2, #1 + 13508 .LVL963: +2412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13509 .loc 1 2412 3 is_stmt 0 view .LVU3939 + 13510 00d4 2146 mov r1, r4 + 13511 .LVL964: +2412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13512 .loc 1 2412 3 view .LVU3940 + 13513 00d6 2868 ldr r0, [r5] + 13514 .LVL965: +2412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13515 .loc 1 2412 3 view .LVU3941 + 13516 00d8 FFF7FEFF bl TIM_CCxChannelCmd + 13517 .LVL966: +2414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13518 .loc 1 2414 3 is_stmt 1 view .LVU3942 + 13519 00dc 0C2C cmp r4, #12 + 13520 00de 00F28280 bhi .L1022 + 13521 00e2 DFE804F0 tbb [pc, r4] + 13522 .L1013: + 13523 00e6 1F .byte (.L1016-.L1013)/2 + 13524 00e7 80 .byte (.L1022-.L1013)/2 + 13525 00e8 80 .byte (.L1022-.L1013)/2 + 13526 00e9 80 .byte (.L1022-.L1013)/2 + 13527 00ea 38 .byte (.L1015-.L1013)/2 + 13528 00eb 80 .byte (.L1022-.L1013)/2 + 13529 00ec 80 .byte (.L1022-.L1013)/2 + 13530 00ed 80 .byte (.L1022-.L1013)/2 + 13531 00ee 50 .byte (.L1014-.L1013)/2 + 13532 00ef 80 .byte (.L1022-.L1013)/2 + 13533 00f0 80 .byte (.L1022-.L1013)/2 + ARM GAS /tmp/ccGFzgX3.s page 434 + + + 13534 00f1 80 .byte (.L1022-.L1013)/2 + 13535 00f2 68 .byte (.L1012-.L1013)/2 + 13536 .LVL967: + 13537 00f3 00 .p2align 1 + 13538 .L1004: +2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 13539 .loc 1 2402 7 is_stmt 0 discriminator 6 view .LVU3943 + 13540 00f4 0223 movs r3, #2 + 13541 00f6 85F84030 strb r3, [r5, #64] +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13542 .loc 1 2403 7 is_stmt 1 view .LVU3944 + 13543 00fa E3E7 b .L1008 + 13544 .L1003: +2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 13545 .loc 1 2402 7 is_stmt 0 discriminator 9 view .LVU3945 + 13546 00fc 0223 movs r3, #2 + 13547 00fe 85F84130 strb r3, [r5, #65] +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13548 .loc 1 2403 7 is_stmt 1 view .LVU3946 + 13549 0102 DFE7 b .L1008 + 13550 .L1001: +2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 13551 .loc 1 2402 7 is_stmt 0 discriminator 12 view .LVU3947 + 13552 0104 0223 movs r3, #2 + 13553 0106 85F84230 strb r3, [r5, #66] +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13554 .loc 1 2403 7 is_stmt 1 view .LVU3948 + 13555 010a DBE7 b .L1008 + 13556 .L1000: +2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 13557 .loc 1 2402 7 is_stmt 0 discriminator 13 view .LVU3949 + 13558 010c 0223 movs r3, #2 + 13559 010e 85F84330 strb r3, [r5, #67] +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13560 .loc 1 2403 7 is_stmt 1 view .LVU3950 + 13561 0112 D7E7 b .L1008 + 13562 .L1030: +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13563 .loc 1 2403 7 is_stmt 0 discriminator 3 view .LVU3951 + 13564 0114 0223 movs r3, #2 + 13565 0116 85F84530 strb r3, [r5, #69] + 13566 011a DAE7 b .L1007 + 13567 .L1031: +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13568 .loc 1 2403 7 discriminator 6 view .LVU3952 + 13569 011c 0223 movs r3, #2 + 13570 011e 85F84630 strb r3, [r5, #70] + 13571 0122 D6E7 b .L1007 + 13572 .LVL968: + 13573 .L1016: +2419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 13574 .loc 1 2419 7 is_stmt 1 view .LVU3953 +2419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 13575 .loc 1 2419 17 is_stmt 0 view .LVU3954 + 13576 0124 6B6A ldr r3, [r5, #36] +2419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 13577 .loc 1 2419 52 view .LVU3955 + ARM GAS /tmp/ccGFzgX3.s page 435 + + + 13578 0126 504A ldr r2, .L1032 + 13579 0128 DA63 str r2, [r3, #60] +2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13580 .loc 1 2420 7 is_stmt 1 view .LVU3956 +2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13581 .loc 1 2420 17 is_stmt 0 view .LVU3957 + 13582 012a 6B6A ldr r3, [r5, #36] +2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13583 .loc 1 2420 56 view .LVU3958 + 13584 012c 4F4A ldr r2, .L1032+4 + 13585 012e 1A64 str r2, [r3, #64] +2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13586 .loc 1 2423 7 is_stmt 1 view .LVU3959 +2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13587 .loc 1 2423 17 is_stmt 0 view .LVU3960 + 13588 0130 6B6A ldr r3, [r5, #36] +2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13589 .loc 1 2423 53 view .LVU3961 + 13590 0132 4F4A ldr r2, .L1032+8 + 13591 0134 DA64 str r2, [r3, #76] +2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 13592 .loc 1 2426 7 is_stmt 1 view .LVU3962 +2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 13593 .loc 1 2426 71 is_stmt 0 view .LVU3963 + 13594 0136 2968 ldr r1, [r5] +2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 13595 .loc 1 2426 11 view .LVU3964 + 13596 0138 3B46 mov r3, r7 + 13597 013a 3246 mov r2, r6 + 13598 013c 3431 adds r1, r1, #52 + 13599 013e 686A ldr r0, [r5, #36] + 13600 0140 FFF7FEFF bl HAL_DMA_Start_IT + 13601 .LVL969: +2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 13602 .loc 1 2426 10 discriminator 1 view .LVU3965 + 13603 0144 0028 cmp r0, #0 + 13604 0146 40F08680 bne .L1023 +2433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13605 .loc 1 2433 7 is_stmt 1 view .LVU3966 + 13606 014a 2A68 ldr r2, [r5] + 13607 014c D368 ldr r3, [r2, #12] + 13608 014e 43F40073 orr r3, r3, #512 + 13609 0152 D360 str r3, [r2, #12] +2434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13610 .loc 1 2434 7 view .LVU3967 + 13611 0154 48E0 b .L1011 + 13612 .L1015: +2440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 13613 .loc 1 2440 7 view .LVU3968 +2440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 13614 .loc 1 2440 17 is_stmt 0 view .LVU3969 + 13615 0156 AB6A ldr r3, [r5, #40] +2440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 13616 .loc 1 2440 52 view .LVU3970 + 13617 0158 434A ldr r2, .L1032 + 13618 015a DA63 str r2, [r3, #60] +2441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 436 + + + 13619 .loc 1 2441 7 is_stmt 1 view .LVU3971 +2441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13620 .loc 1 2441 17 is_stmt 0 view .LVU3972 + 13621 015c AB6A ldr r3, [r5, #40] +2441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13622 .loc 1 2441 56 view .LVU3973 + 13623 015e 434A ldr r2, .L1032+4 + 13624 0160 1A64 str r2, [r3, #64] +2444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13625 .loc 1 2444 7 is_stmt 1 view .LVU3974 +2444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13626 .loc 1 2444 17 is_stmt 0 view .LVU3975 + 13627 0162 AB6A ldr r3, [r5, #40] +2444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13628 .loc 1 2444 53 view .LVU3976 + 13629 0164 424A ldr r2, .L1032+8 + 13630 0166 DA64 str r2, [r3, #76] +2447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 13631 .loc 1 2447 7 is_stmt 1 view .LVU3977 +2447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 13632 .loc 1 2447 71 is_stmt 0 view .LVU3978 + 13633 0168 2968 ldr r1, [r5] +2447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 13634 .loc 1 2447 11 view .LVU3979 + 13635 016a 3B46 mov r3, r7 + 13636 016c 3246 mov r2, r6 + 13637 016e 3831 adds r1, r1, #56 + 13638 0170 A86A ldr r0, [r5, #40] + 13639 0172 FFF7FEFF bl HAL_DMA_Start_IT + 13640 .LVL970: +2447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 13641 .loc 1 2447 10 discriminator 1 view .LVU3980 + 13642 0176 0028 cmp r0, #0 + 13643 0178 6FD1 bne .L1024 +2454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13644 .loc 1 2454 7 is_stmt 1 view .LVU3981 + 13645 017a 2A68 ldr r2, [r5] + 13646 017c D368 ldr r3, [r2, #12] + 13647 017e 43F48063 orr r3, r3, #1024 + 13648 0182 D360 str r3, [r2, #12] +2455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13649 .loc 1 2455 7 view .LVU3982 + 13650 0184 30E0 b .L1011 + 13651 .L1014: +2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 13652 .loc 1 2461 7 view .LVU3983 +2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 13653 .loc 1 2461 17 is_stmt 0 view .LVU3984 + 13654 0186 EB6A ldr r3, [r5, #44] +2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 13655 .loc 1 2461 52 view .LVU3985 + 13656 0188 374A ldr r2, .L1032 + 13657 018a DA63 str r2, [r3, #60] +2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13658 .loc 1 2462 7 is_stmt 1 view .LVU3986 +2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13659 .loc 1 2462 17 is_stmt 0 view .LVU3987 + ARM GAS /tmp/ccGFzgX3.s page 437 + + + 13660 018c EB6A ldr r3, [r5, #44] +2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13661 .loc 1 2462 56 view .LVU3988 + 13662 018e 374A ldr r2, .L1032+4 + 13663 0190 1A64 str r2, [r3, #64] +2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13664 .loc 1 2465 7 is_stmt 1 view .LVU3989 +2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13665 .loc 1 2465 17 is_stmt 0 view .LVU3990 + 13666 0192 EB6A ldr r3, [r5, #44] +2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13667 .loc 1 2465 53 view .LVU3991 + 13668 0194 364A ldr r2, .L1032+8 + 13669 0196 DA64 str r2, [r3, #76] +2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 13670 .loc 1 2468 7 is_stmt 1 view .LVU3992 +2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 13671 .loc 1 2468 71 is_stmt 0 view .LVU3993 + 13672 0198 2968 ldr r1, [r5] +2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 13673 .loc 1 2468 11 view .LVU3994 + 13674 019a 3B46 mov r3, r7 + 13675 019c 3246 mov r2, r6 + 13676 019e 3C31 adds r1, r1, #60 + 13677 01a0 E86A ldr r0, [r5, #44] + 13678 01a2 FFF7FEFF bl HAL_DMA_Start_IT + 13679 .LVL971: +2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 13680 .loc 1 2468 10 discriminator 1 view .LVU3995 + 13681 01a6 0028 cmp r0, #0 + 13682 01a8 59D1 bne .L1025 +2475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13683 .loc 1 2475 7 is_stmt 1 view .LVU3996 + 13684 01aa 2A68 ldr r2, [r5] + 13685 01ac D368 ldr r3, [r2, #12] + 13686 01ae 43F40063 orr r3, r3, #2048 + 13687 01b2 D360 str r3, [r2, #12] +2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13688 .loc 1 2476 7 view .LVU3997 + 13689 01b4 18E0 b .L1011 + 13690 .L1012: +2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 13691 .loc 1 2482 7 view .LVU3998 +2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 13692 .loc 1 2482 17 is_stmt 0 view .LVU3999 + 13693 01b6 2B6B ldr r3, [r5, #48] +2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 13694 .loc 1 2482 52 view .LVU4000 + 13695 01b8 2B4A ldr r2, .L1032 + 13696 01ba DA63 str r2, [r3, #60] +2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13697 .loc 1 2483 7 is_stmt 1 view .LVU4001 +2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13698 .loc 1 2483 17 is_stmt 0 view .LVU4002 + 13699 01bc 2B6B ldr r3, [r5, #48] +2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13700 .loc 1 2483 56 view .LVU4003 + ARM GAS /tmp/ccGFzgX3.s page 438 + + + 13701 01be 2B4A ldr r2, .L1032+4 + 13702 01c0 1A64 str r2, [r3, #64] +2486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13703 .loc 1 2486 7 is_stmt 1 view .LVU4004 +2486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13704 .loc 1 2486 17 is_stmt 0 view .LVU4005 + 13705 01c2 2B6B ldr r3, [r5, #48] +2486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13706 .loc 1 2486 53 view .LVU4006 + 13707 01c4 2A4A ldr r2, .L1032+8 + 13708 01c6 DA64 str r2, [r3, #76] +2489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 13709 .loc 1 2489 7 is_stmt 1 view .LVU4007 +2489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 13710 .loc 1 2489 71 is_stmt 0 view .LVU4008 + 13711 01c8 2968 ldr r1, [r5] +2489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 13712 .loc 1 2489 11 view .LVU4009 + 13713 01ca 3B46 mov r3, r7 + 13714 01cc 3246 mov r2, r6 + 13715 01ce 4031 adds r1, r1, #64 + 13716 01d0 286B ldr r0, [r5, #48] + 13717 01d2 FFF7FEFF bl HAL_DMA_Start_IT + 13718 .LVL972: +2489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 13719 .loc 1 2489 10 discriminator 1 view .LVU4010 + 13720 01d6 0028 cmp r0, #0 + 13721 01d8 43D1 bne .L1026 +2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13722 .loc 1 2496 7 is_stmt 1 view .LVU4011 + 13723 01da 2A68 ldr r2, [r5] + 13724 01dc D368 ldr r3, [r2, #12] + 13725 01de 43F48053 orr r3, r3, #4096 + 13726 01e2 D360 str r3, [r2, #12] +2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13727 .loc 1 2497 7 view .LVU4012 + 13728 01e4 00E0 b .L1011 + 13729 .L1022: +2414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13730 .loc 1 2414 3 is_stmt 0 view .LVU4013 + 13731 01e6 0120 movs r0, #1 + 13732 .L1011: + 13733 .LVL973: +2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13734 .loc 1 2506 3 is_stmt 1 view .LVU4014 +2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13735 .loc 1 2506 7 is_stmt 0 view .LVU4015 + 13736 01e8 2B68 ldr r3, [r5] +2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13737 .loc 1 2506 6 view .LVU4016 + 13738 01ea 224A ldr r2, .L1032+12 + 13739 01ec B3F1804F cmp r3, #1073741824 + 13740 01f0 18BF it ne + 13741 01f2 9342 cmpne r3, r2 + 13742 01f4 1CD0 beq .L1017 +2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13743 .loc 1 2506 7 discriminator 1 view .LVU4017 + ARM GAS /tmp/ccGFzgX3.s page 439 + + + 13744 01f6 A2F57C42 sub r2, r2, #64512 + 13745 01fa 9342 cmp r3, r2 + 13746 01fc 18D0 beq .L1017 +2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13747 .loc 1 2506 7 discriminator 2 view .LVU4018 + 13748 01fe 02F58062 add r2, r2, #1024 + 13749 0202 9342 cmp r3, r2 + 13750 0204 14D0 beq .L1017 +2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13751 .loc 1 2506 7 discriminator 3 view .LVU4019 + 13752 0206 02F58062 add r2, r2, #1024 + 13753 020a 9342 cmp r3, r2 + 13754 020c 10D0 beq .L1017 +2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13755 .loc 1 2506 7 discriminator 4 view .LVU4020 + 13756 020e 02F57842 add r2, r2, #63488 + 13757 0212 9342 cmp r3, r2 + 13758 0214 0CD0 beq .L1017 +2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13759 .loc 1 2506 7 discriminator 5 view .LVU4021 + 13760 0216 02F57052 add r2, r2, #15360 + 13761 021a 9342 cmp r3, r2 + 13762 021c 08D0 beq .L1017 +2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13763 .loc 1 2506 7 discriminator 6 view .LVU4022 + 13764 021e A2F59432 sub r2, r2, #75776 + 13765 0222 9342 cmp r3, r2 + 13766 0224 04D0 beq .L1017 +2516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13767 .loc 1 2516 5 is_stmt 1 view .LVU4023 + 13768 0226 1A68 ldr r2, [r3] + 13769 0228 42F00102 orr r2, r2, #1 + 13770 022c 1A60 str r2, [r3] + 13771 022e 0FE0 b .L999 + 13772 .L1017: +2508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 13773 .loc 1 2508 5 view .LVU4024 +2508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 13774 .loc 1 2508 29 is_stmt 0 view .LVU4025 + 13775 0230 9968 ldr r1, [r3, #8] +2508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 13776 .loc 1 2508 13 view .LVU4026 + 13777 0232 114A ldr r2, .L1032+16 + 13778 0234 0A40 ands r2, r2, r1 + 13779 .LVL974: +2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13780 .loc 1 2509 5 is_stmt 1 view .LVU4027 +2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13781 .loc 1 2509 8 is_stmt 0 view .LVU4028 + 13782 0236 062A cmp r2, #6 + 13783 0238 18BF it ne + 13784 023a B2F5803F cmpne r2, #65536 + 13785 023e 07D0 beq .L999 +2511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13786 .loc 1 2511 7 is_stmt 1 view .LVU4029 + 13787 0240 1A68 ldr r2, [r3] + 13788 .LVL975: + ARM GAS /tmp/ccGFzgX3.s page 440 + + +2511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13789 .loc 1 2511 7 is_stmt 0 view .LVU4030 + 13790 0242 42F00102 orr r2, r2, #1 + 13791 0246 1A60 str r2, [r3] + 13792 0248 02E0 b .L999 + 13793 .LVL976: + 13794 .L1019: +2391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13795 .loc 1 2391 12 view .LVU4031 + 13796 024a 0220 movs r0, #2 + 13797 .LVL977: +2391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13798 .loc 1 2391 12 view .LVU4032 + 13799 024c 00E0 b .L999 + 13800 .LVL978: + 13801 .L1020: +2408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13802 .loc 1 2408 12 view .LVU4033 + 13803 024e 0120 movs r0, #1 + 13804 .LVL979: + 13805 .L999: +2521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13806 .loc 1 2521 1 view .LVU4034 + 13807 0250 F8BD pop {r3, r4, r5, r6, r7, pc} + 13808 .LVL980: + 13809 .L1021: +2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13810 .loc 1 2398 14 view .LVU4035 + 13811 0252 0120 movs r0, #1 + 13812 .LVL981: +2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13813 .loc 1 2398 14 view .LVU4036 + 13814 0254 FCE7 b .L999 + 13815 .LVL982: + 13816 .L1023: +2430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13817 .loc 1 2430 16 view .LVU4037 + 13818 0256 0120 movs r0, #1 + 13819 0258 FAE7 b .L999 + 13820 .L1024: +2451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13821 .loc 1 2451 16 view .LVU4038 + 13822 025a 0120 movs r0, #1 + 13823 025c F8E7 b .L999 + 13824 .L1025: +2472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13825 .loc 1 2472 16 view .LVU4039 + 13826 025e 0120 movs r0, #1 + 13827 0260 F6E7 b .L999 + 13828 .L1026: +2493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13829 .loc 1 2493 16 view .LVU4040 + 13830 0262 0120 movs r0, #1 + 13831 0264 F4E7 b .L999 + 13832 .L1033: + 13833 0266 00BF .align 2 + 13834 .L1032: + ARM GAS /tmp/ccGFzgX3.s page 441 + + + 13835 0268 00000000 .word TIM_DMACaptureCplt + 13836 026c 00000000 .word TIM_DMACaptureHalfCplt + 13837 0270 00000000 .word TIM_DMAError + 13838 0274 00000140 .word 1073807360 + 13839 0278 07000100 .word 65543 + 13840 .cfi_endproc + 13841 .LFE179: + 13843 .section .text.HAL_TIM_IC_Stop_DMA,"ax",%progbits + 13844 .align 1 + 13845 .global HAL_TIM_IC_Stop_DMA + 13846 .syntax unified + 13847 .thumb + 13848 .thumb_func + 13850 HAL_TIM_IC_Stop_DMA: + 13851 .LVL983: + 13852 .LFB180: +2535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 13853 .loc 1 2535 1 is_stmt 1 view -0 + 13854 .cfi_startproc + 13855 @ args = 0, pretend = 0, frame = 0 + 13856 @ frame_needed = 0, uses_anonymous_args = 0 +2535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 13857 .loc 1 2535 1 is_stmt 0 view .LVU4042 + 13858 0000 38B5 push {r3, r4, r5, lr} + 13859 .LCFI103: + 13860 .cfi_def_cfa_offset 16 + 13861 .cfi_offset 3, -16 + 13862 .cfi_offset 4, -12 + 13863 .cfi_offset 5, -8 + 13864 .cfi_offset 14, -4 + 13865 0002 0446 mov r4, r0 + 13866 0004 0D46 mov r5, r1 +2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13867 .loc 1 2536 3 is_stmt 1 view .LVU4043 + 13868 .LVL984: +2539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + 13869 .loc 1 2539 3 view .LVU4044 +2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13870 .loc 1 2540 3 view .LVU4045 +2543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13871 .loc 1 2543 3 view .LVU4046 + 13872 0006 0022 movs r2, #0 + 13873 0008 0068 ldr r0, [r0] + 13874 .LVL985: +2543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13875 .loc 1 2543 3 is_stmt 0 view .LVU4047 + 13876 000a FFF7FEFF bl TIM_CCxChannelCmd + 13877 .LVL986: +2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13878 .loc 1 2545 3 is_stmt 1 view .LVU4048 + 13879 000e 0C2D cmp r5, #12 + 13880 0010 74D8 bhi .L1053 + 13881 0012 DFE805F0 tbb [pc, r5] + 13882 .L1037: + 13883 0016 07 .byte (.L1040-.L1037)/2 + 13884 0017 73 .byte (.L1053-.L1037)/2 + 13885 0018 73 .byte (.L1053-.L1037)/2 + ARM GAS /tmp/ccGFzgX3.s page 442 + + + 13886 0019 73 .byte (.L1053-.L1037)/2 + 13887 001a 2B .byte (.L1039-.L1037)/2 + 13888 001b 73 .byte (.L1053-.L1037)/2 + 13889 001c 73 .byte (.L1053-.L1037)/2 + 13890 001d 73 .byte (.L1053-.L1037)/2 + 13891 001e 34 .byte (.L1038-.L1037)/2 + 13892 001f 73 .byte (.L1053-.L1037)/2 + 13893 0020 73 .byte (.L1053-.L1037)/2 + 13894 0021 73 .byte (.L1053-.L1037)/2 + 13895 0022 3D .byte (.L1036-.L1037)/2 + 13896 0023 00 .p2align 1 + 13897 .L1040: +2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + 13898 .loc 1 2550 7 view .LVU4049 + 13899 0024 2268 ldr r2, [r4] + 13900 0026 D368 ldr r3, [r2, #12] + 13901 0028 23F40073 bic r3, r3, #512 + 13902 002c D360 str r3, [r2, #12] +2551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13903 .loc 1 2551 7 view .LVU4050 +2551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13904 .loc 1 2551 13 is_stmt 0 view .LVU4051 + 13905 002e 606A ldr r0, [r4, #36] + 13906 0030 FFF7FEFF bl HAL_DMA_Abort_IT + 13907 .LVL987: +2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13908 .loc 1 2552 7 is_stmt 1 view .LVU4052 +2584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13909 .loc 1 2584 3 view .LVU4053 + 13910 .L1041: +2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13911 .loc 1 2587 5 view .LVU4054 +2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13912 .loc 1 2587 5 view .LVU4055 + 13913 0034 2368 ldr r3, [r4] + 13914 0036 196A ldr r1, [r3, #32] + 13915 0038 41F21112 movw r2, #4369 + 13916 003c 1142 tst r1, r2 + 13917 003e 08D1 bne .L1042 +2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13918 .loc 1 2587 5 discriminator 1 view .LVU4056 + 13919 0040 196A ldr r1, [r3, #32] + 13920 0042 40F24442 movw r2, #1092 + 13921 0046 1142 tst r1, r2 + 13922 0048 03D1 bne .L1042 +2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13923 .loc 1 2587 5 discriminator 3 view .LVU4057 + 13924 004a 1A68 ldr r2, [r3] + 13925 004c 22F00102 bic r2, r2, #1 + 13926 0050 1A60 str r2, [r3] + 13927 .L1042: +2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 13928 .loc 1 2587 5 discriminator 5 view .LVU4058 +2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 13929 .loc 1 2590 5 view .LVU4059 + 13930 0052 102D cmp r5, #16 + 13931 0054 44D8 bhi .L1043 + ARM GAS /tmp/ccGFzgX3.s page 443 + + + 13932 0056 DFE805F0 tbb [pc, r5] + 13933 .L1045: + 13934 005a 24 .byte (.L1049-.L1045)/2 + 13935 005b 43 .byte (.L1043-.L1045)/2 + 13936 005c 43 .byte (.L1043-.L1045)/2 + 13937 005d 43 .byte (.L1043-.L1045)/2 + 13938 005e 2B .byte (.L1048-.L1045)/2 + 13939 005f 43 .byte (.L1043-.L1045)/2 + 13940 0060 43 .byte (.L1043-.L1045)/2 + 13941 0061 43 .byte (.L1043-.L1045)/2 + 13942 0062 37 .byte (.L1047-.L1045)/2 + 13943 0063 43 .byte (.L1043-.L1045)/2 + 13944 0064 43 .byte (.L1043-.L1045)/2 + 13945 0065 43 .byte (.L1043-.L1045)/2 + 13946 0066 3B .byte (.L1046-.L1045)/2 + 13947 0067 43 .byte (.L1043-.L1045)/2 + 13948 0068 43 .byte (.L1043-.L1045)/2 + 13949 0069 43 .byte (.L1043-.L1045)/2 + 13950 006a 3F .byte (.L1044-.L1045)/2 + 13951 006b 00 .p2align 1 + 13952 .L1039: +2558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + 13953 .loc 1 2558 7 view .LVU4060 + 13954 006c 2268 ldr r2, [r4] + 13955 006e D368 ldr r3, [r2, #12] + 13956 0070 23F48063 bic r3, r3, #1024 + 13957 0074 D360 str r3, [r2, #12] +2559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13958 .loc 1 2559 7 view .LVU4061 +2559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13959 .loc 1 2559 13 is_stmt 0 view .LVU4062 + 13960 0076 A06A ldr r0, [r4, #40] + 13961 0078 FFF7FEFF bl HAL_DMA_Abort_IT + 13962 .LVL988: +2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13963 .loc 1 2560 7 is_stmt 1 view .LVU4063 +2584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13964 .loc 1 2584 3 view .LVU4064 + 13965 007c DAE7 b .L1041 + 13966 .L1038: +2566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + 13967 .loc 1 2566 7 view .LVU4065 + 13968 007e 2268 ldr r2, [r4] + 13969 0080 D368 ldr r3, [r2, #12] + 13970 0082 23F40063 bic r3, r3, #2048 + 13971 0086 D360 str r3, [r2, #12] +2567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13972 .loc 1 2567 7 view .LVU4066 +2567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13973 .loc 1 2567 13 is_stmt 0 view .LVU4067 + 13974 0088 E06A ldr r0, [r4, #44] + 13975 008a FFF7FEFF bl HAL_DMA_Abort_IT + 13976 .LVL989: +2568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13977 .loc 1 2568 7 is_stmt 1 view .LVU4068 +2584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13978 .loc 1 2584 3 view .LVU4069 + ARM GAS /tmp/ccGFzgX3.s page 444 + + + 13979 008e D1E7 b .L1041 + 13980 .L1036: +2574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + 13981 .loc 1 2574 7 view .LVU4070 + 13982 0090 2268 ldr r2, [r4] + 13983 0092 D368 ldr r3, [r2, #12] + 13984 0094 23F48053 bic r3, r3, #4096 + 13985 0098 D360 str r3, [r2, #12] +2575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13986 .loc 1 2575 7 view .LVU4071 +2575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 13987 .loc 1 2575 13 is_stmt 0 view .LVU4072 + 13988 009a 206B ldr r0, [r4, #48] + 13989 009c FFF7FEFF bl HAL_DMA_Abort_IT + 13990 .LVL990: +2576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13991 .loc 1 2576 7 is_stmt 1 view .LVU4073 +2584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 13992 .loc 1 2584 3 view .LVU4074 + 13993 00a0 C8E7 b .L1041 + 13994 .L1049: +2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 13995 .loc 1 2590 5 is_stmt 0 discriminator 1 view .LVU4075 + 13996 00a2 0123 movs r3, #1 + 13997 00a4 84F83E30 strb r3, [r4, #62] +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13998 .loc 1 2591 5 is_stmt 1 view .LVU4076 +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 13999 .loc 1 2591 5 is_stmt 0 discriminator 1 view .LVU4077 + 14000 00a8 84F84430 strb r3, [r4, #68] + 14001 00ac 0020 movs r0, #0 + 14002 00ae 26E0 b .L1035 + 14003 .L1048: +2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 14004 .loc 1 2590 5 discriminator 3 view .LVU4078 + 14005 00b0 0123 movs r3, #1 + 14006 00b2 84F83F30 strb r3, [r4, #63] +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14007 .loc 1 2591 5 is_stmt 1 view .LVU4079 + 14008 .L1050: +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14009 .loc 1 2591 5 is_stmt 0 discriminator 2 view .LVU4080 + 14010 00b6 042D cmp r5, #4 + 14011 00b8 16D0 beq .L1055 +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14012 .loc 1 2591 5 discriminator 4 view .LVU4081 + 14013 00ba 082D cmp r5, #8 + 14014 00bc 19D0 beq .L1056 +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14015 .loc 1 2591 5 discriminator 7 view .LVU4082 + 14016 00be 0123 movs r3, #1 + 14017 00c0 84F84730 strb r3, [r4, #71] + 14018 00c4 0020 movs r0, #0 + 14019 00c6 1AE0 b .L1035 + 14020 .L1047: +2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 14021 .loc 1 2590 5 discriminator 6 view .LVU4083 + ARM GAS /tmp/ccGFzgX3.s page 445 + + + 14022 00c8 0123 movs r3, #1 + 14023 00ca 84F84030 strb r3, [r4, #64] +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14024 .loc 1 2591 5 is_stmt 1 view .LVU4084 + 14025 00ce F2E7 b .L1050 + 14026 .L1046: +2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 14027 .loc 1 2590 5 is_stmt 0 discriminator 9 view .LVU4085 + 14028 00d0 0123 movs r3, #1 + 14029 00d2 84F84130 strb r3, [r4, #65] +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14030 .loc 1 2591 5 is_stmt 1 view .LVU4086 + 14031 00d6 EEE7 b .L1050 + 14032 .L1044: +2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 14033 .loc 1 2590 5 is_stmt 0 discriminator 12 view .LVU4087 + 14034 00d8 0123 movs r3, #1 + 14035 00da 84F84230 strb r3, [r4, #66] +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14036 .loc 1 2591 5 is_stmt 1 view .LVU4088 + 14037 00de EAE7 b .L1050 + 14038 .L1043: +2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 14039 .loc 1 2590 5 is_stmt 0 discriminator 13 view .LVU4089 + 14040 00e0 0123 movs r3, #1 + 14041 00e2 84F84330 strb r3, [r4, #67] +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14042 .loc 1 2591 5 is_stmt 1 view .LVU4090 + 14043 00e6 E6E7 b .L1050 + 14044 .L1055: +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14045 .loc 1 2591 5 is_stmt 0 discriminator 3 view .LVU4091 + 14046 00e8 0123 movs r3, #1 + 14047 00ea 84F84530 strb r3, [r4, #69] + 14048 00ee 0020 movs r0, #0 + 14049 00f0 05E0 b .L1035 + 14050 .L1056: +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14051 .loc 1 2591 5 discriminator 6 view .LVU4092 + 14052 00f2 0123 movs r3, #1 + 14053 00f4 84F84630 strb r3, [r4, #70] + 14054 00f8 0020 movs r0, #0 + 14055 00fa 00E0 b .L1035 + 14056 .L1053: +2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14057 .loc 1 2545 3 view .LVU4093 + 14058 00fc 0120 movs r0, #1 + 14059 .L1035: + 14060 .LVL991: +2595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14061 .loc 1 2595 3 is_stmt 1 view .LVU4094 +2596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 14062 .loc 1 2596 1 is_stmt 0 view .LVU4095 + 14063 00fe 38BD pop {r3, r4, r5, pc} +2596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /** + 14064 .loc 1 2596 1 view .LVU4096 + 14065 .cfi_endproc + ARM GAS /tmp/ccGFzgX3.s page 446 + + + 14066 .LFE180: + 14068 .section .text.HAL_TIM_OnePulse_Start,"ax",%progbits + 14069 .align 1 + 14070 .global HAL_TIM_OnePulse_Start + 14071 .syntax unified + 14072 .thumb + 14073 .thumb_func + 14075 HAL_TIM_OnePulse_Start: + 14076 .LVL992: + 14077 .LFB185: +2789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 14078 .loc 1 2789 1 is_stmt 1 view -0 + 14079 .cfi_startproc + 14080 @ args = 0, pretend = 0, frame = 0 + 14081 @ frame_needed = 0, uses_anonymous_args = 0 +2789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 14082 .loc 1 2789 1 is_stmt 0 view .LVU4098 + 14083 0000 10B5 push {r4, lr} + 14084 .LCFI104: + 14085 .cfi_def_cfa_offset 8 + 14086 .cfi_offset 4, -8 + 14087 .cfi_offset 14, -4 + 14088 0002 0446 mov r4, r0 +2790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 14089 .loc 1 2790 3 is_stmt 1 view .LVU4099 +2790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 14090 .loc 1 2790 31 is_stmt 0 view .LVU4100 + 14091 0004 90F83E10 ldrb r1, [r0, #62] @ zero_extendqisi2 + 14092 .LVL993: +2790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 14093 .loc 1 2790 31 view .LVU4101 + 14094 0008 C9B2 uxtb r1, r1 + 14095 .LVL994: +2791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 14096 .loc 1 2791 3 is_stmt 1 view .LVU4102 +2791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 14097 .loc 1 2791 31 is_stmt 0 view .LVU4103 + 14098 000a 90F83F20 ldrb r2, [r0, #63] @ zero_extendqisi2 + 14099 000e D2B2 uxtb r2, r2 + 14100 .LVL995: +2792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 14101 .loc 1 2792 3 is_stmt 1 view .LVU4104 +2792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 14102 .loc 1 2792 31 is_stmt 0 view .LVU4105 + 14103 0010 90F84430 ldrb r3, [r0, #68] @ zero_extendqisi2 + 14104 0014 D8B2 uxtb r0, r3 + 14105 .LVL996: +2793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14106 .loc 1 2793 3 is_stmt 1 view .LVU4106 +2793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14107 .loc 1 2793 31 is_stmt 0 view .LVU4107 + 14108 0016 94F84530 ldrb r3, [r4, #69] @ zero_extendqisi2 + 14109 .LVL997: +2796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14110 .loc 1 2796 3 is_stmt 1 view .LVU4108 +2799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 14111 .loc 1 2799 3 view .LVU4109 + ARM GAS /tmp/ccGFzgX3.s page 447 + + +2799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 14112 .loc 1 2799 6 is_stmt 0 view .LVU4110 + 14113 001a 012A cmp r2, #1 + 14114 001c 08BF it eq + 14115 001e 0129 cmpeq r1, #1 + 14116 0020 26D1 bne .L1059 + 14117 0022 DBB2 uxtb r3, r3 +2802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14118 .loc 1 2802 41 view .LVU4111 + 14119 0024 013B subs r3, r3, #1 + 14120 .LVL998: +2802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14121 .loc 1 2802 41 view .LVU4112 + 14122 0026 18BF it ne + 14123 0028 0123 movne r3, #1 + 14124 .LVL999: +2802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14125 .loc 1 2802 7 view .LVU4113 + 14126 002a 0128 cmp r0, #1 + 14127 002c 22D1 bne .L1060 + 14128 002e 0BBB cbnz r3, .L1060 +2808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 14129 .loc 1 2808 3 is_stmt 1 view .LVU4114 + 14130 0030 0223 movs r3, #2 + 14131 0032 84F83E30 strb r3, [r4, #62] +2809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 14132 .loc 1 2809 3 view .LVU4115 + 14133 0036 84F83F30 strb r3, [r4, #63] +2810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 14134 .loc 1 2810 3 view .LVU4116 + 14135 003a 84F84430 strb r3, [r4, #68] +2811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14136 .loc 1 2811 3 view .LVU4117 + 14137 003e 84F84530 strb r3, [r4, #69] +2822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 14138 .loc 1 2822 3 view .LVU4118 + 14139 0042 0122 movs r2, #1 + 14140 .LVL1000: +2822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 14141 .loc 1 2822 3 is_stmt 0 view .LVU4119 + 14142 0044 0021 movs r1, #0 + 14143 .LVL1001: +2822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 14144 .loc 1 2822 3 view .LVU4120 + 14145 0046 2068 ldr r0, [r4] + 14146 .LVL1002: +2822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 14147 .loc 1 2822 3 view .LVU4121 + 14148 0048 FFF7FEFF bl TIM_CCxChannelCmd + 14149 .LVL1003: +2823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14150 .loc 1 2823 3 is_stmt 1 view .LVU4122 + 14151 004c 0122 movs r2, #1 + 14152 004e 0421 movs r1, #4 + 14153 0050 2068 ldr r0, [r4] + 14154 0052 FFF7FEFF bl TIM_CCxChannelCmd + 14155 .LVL1004: + ARM GAS /tmp/ccGFzgX3.s page 448 + + +2825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14156 .loc 1 2825 3 view .LVU4123 +2825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14157 .loc 1 2825 7 is_stmt 0 view .LVU4124 + 14158 0056 2368 ldr r3, [r4] +2825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14159 .loc 1 2825 6 view .LVU4125 + 14160 0058 0849 ldr r1, .L1063 + 14161 005a 094A ldr r2, .L1063+4 + 14162 005c 9342 cmp r3, r2 + 14163 005e 18BF it ne + 14164 0060 8B42 cmpne r3, r1 + 14165 0062 09D1 bne .L1061 +2828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14166 .loc 1 2828 5 is_stmt 1 view .LVU4126 + 14167 0064 5A6C ldr r2, [r3, #68] + 14168 0066 42F40042 orr r2, r2, #32768 + 14169 006a 5A64 str r2, [r3, #68] +2832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14170 .loc 1 2832 10 is_stmt 0 view .LVU4127 + 14171 006c 0020 movs r0, #0 + 14172 006e 00E0 b .L1058 + 14173 .LVL1005: + 14174 .L1059: +2804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14175 .loc 1 2804 12 view .LVU4128 + 14176 0070 0120 movs r0, #1 + 14177 .LVL1006: + 14178 .L1058: +2833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14179 .loc 1 2833 1 view .LVU4129 + 14180 0072 10BD pop {r4, pc} + 14181 .LVL1007: + 14182 .L1060: +2804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14183 .loc 1 2804 12 view .LVU4130 + 14184 0074 0120 movs r0, #1 + 14185 .LVL1008: +2804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14186 .loc 1 2804 12 view .LVU4131 + 14187 0076 FCE7 b .L1058 + 14188 .LVL1009: + 14189 .L1061: +2832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14190 .loc 1 2832 10 view .LVU4132 + 14191 0078 0020 movs r0, #0 + 14192 007a FAE7 b .L1058 + 14193 .L1064: + 14194 .align 2 + 14195 .L1063: + 14196 007c 00000140 .word 1073807360 + 14197 0080 00040140 .word 1073808384 + 14198 .cfi_endproc + 14199 .LFE185: + 14201 .section .text.HAL_TIM_OnePulse_Stop,"ax",%progbits + 14202 .align 1 + 14203 .global HAL_TIM_OnePulse_Stop + ARM GAS /tmp/ccGFzgX3.s page 449 + + + 14204 .syntax unified + 14205 .thumb + 14206 .thumb_func + 14208 HAL_TIM_OnePulse_Stop: + 14209 .LVL1010: + 14210 .LFB186: +2846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 14211 .loc 1 2846 1 is_stmt 1 view -0 + 14212 .cfi_startproc + 14213 @ args = 0, pretend = 0, frame = 0 + 14214 @ frame_needed = 0, uses_anonymous_args = 0 +2846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 14215 .loc 1 2846 1 is_stmt 0 view .LVU4134 + 14216 0000 10B5 push {r4, lr} + 14217 .LCFI105: + 14218 .cfi_def_cfa_offset 8 + 14219 .cfi_offset 4, -8 + 14220 .cfi_offset 14, -4 + 14221 0002 0446 mov r4, r0 +2848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14222 .loc 1 2848 3 is_stmt 1 view .LVU4135 +2856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 14223 .loc 1 2856 3 view .LVU4136 + 14224 0004 0022 movs r2, #0 + 14225 0006 1146 mov r1, r2 + 14226 .LVL1011: +2856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 14227 .loc 1 2856 3 is_stmt 0 view .LVU4137 + 14228 0008 0068 ldr r0, [r0] + 14229 .LVL1012: +2856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 14230 .loc 1 2856 3 view .LVU4138 + 14231 000a FFF7FEFF bl TIM_CCxChannelCmd + 14232 .LVL1013: +2857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14233 .loc 1 2857 3 is_stmt 1 view .LVU4139 + 14234 000e 0022 movs r2, #0 + 14235 0010 0421 movs r1, #4 + 14236 0012 2068 ldr r0, [r4] + 14237 0014 FFF7FEFF bl TIM_CCxChannelCmd + 14238 .LVL1014: +2859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14239 .loc 1 2859 3 view .LVU4140 +2859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14240 .loc 1 2859 7 is_stmt 0 view .LVU4141 + 14241 0018 2368 ldr r3, [r4] +2859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14242 .loc 1 2859 6 view .LVU4142 + 14243 001a 1749 ldr r1, .L1069 + 14244 001c 174A ldr r2, .L1069+4 + 14245 001e 9342 cmp r3, r2 + 14246 0020 18BF it ne + 14247 0022 8B42 cmpne r3, r1 + 14248 0024 0DD1 bne .L1066 +2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14249 .loc 1 2862 5 is_stmt 1 view .LVU4143 +2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + ARM GAS /tmp/ccGFzgX3.s page 450 + + + 14250 .loc 1 2862 5 view .LVU4144 + 14251 0026 196A ldr r1, [r3, #32] + 14252 0028 41F21112 movw r2, #4369 + 14253 002c 1142 tst r1, r2 + 14254 002e 08D1 bne .L1066 +2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14255 .loc 1 2862 5 discriminator 1 view .LVU4145 + 14256 0030 196A ldr r1, [r3, #32] + 14257 0032 40F24442 movw r2, #1092 + 14258 0036 1142 tst r1, r2 + 14259 0038 03D1 bne .L1066 +2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14260 .loc 1 2862 5 discriminator 3 view .LVU4146 + 14261 003a 5A6C ldr r2, [r3, #68] + 14262 003c 22F40042 bic r2, r2, #32768 + 14263 0040 5A64 str r2, [r3, #68] + 14264 .L1066: +2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14265 .loc 1 2862 5 discriminator 5 view .LVU4147 +2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14266 .loc 1 2866 3 view .LVU4148 +2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14267 .loc 1 2866 3 view .LVU4149 + 14268 0042 2368 ldr r3, [r4] + 14269 0044 196A ldr r1, [r3, #32] + 14270 0046 41F21112 movw r2, #4369 + 14271 004a 1142 tst r1, r2 + 14272 004c 08D1 bne .L1067 +2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14273 .loc 1 2866 3 discriminator 1 view .LVU4150 + 14274 004e 196A ldr r1, [r3, #32] + 14275 0050 40F24442 movw r2, #1092 + 14276 0054 1142 tst r1, r2 + 14277 0056 03D1 bne .L1067 +2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14278 .loc 1 2866 3 discriminator 3 view .LVU4151 + 14279 0058 1A68 ldr r2, [r3] + 14280 005a 22F00102 bic r2, r2, #1 + 14281 005e 1A60 str r2, [r3] + 14282 .L1067: +2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14283 .loc 1 2866 3 discriminator 5 view .LVU4152 +2869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 14284 .loc 1 2869 3 view .LVU4153 + 14285 0060 0123 movs r3, #1 + 14286 0062 84F83E30 strb r3, [r4, #62] +2870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 14287 .loc 1 2870 3 view .LVU4154 + 14288 0066 84F83F30 strb r3, [r4, #63] +2871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 14289 .loc 1 2871 3 view .LVU4155 + 14290 006a 84F84430 strb r3, [r4, #68] +2872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14291 .loc 1 2872 3 view .LVU4156 + 14292 006e 84F84530 strb r3, [r4, #69] +2875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14293 .loc 1 2875 3 view .LVU4157 + ARM GAS /tmp/ccGFzgX3.s page 451 + + +2876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14294 .loc 1 2876 1 is_stmt 0 view .LVU4158 + 14295 0072 0020 movs r0, #0 + 14296 0074 10BD pop {r4, pc} + 14297 .LVL1015: + 14298 .L1070: +2876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14299 .loc 1 2876 1 view .LVU4159 + 14300 0076 00BF .align 2 + 14301 .L1069: + 14302 0078 00000140 .word 1073807360 + 14303 007c 00040140 .word 1073808384 + 14304 .cfi_endproc + 14305 .LFE186: + 14307 .section .text.HAL_TIM_OnePulse_Start_IT,"ax",%progbits + 14308 .align 1 + 14309 .global HAL_TIM_OnePulse_Start_IT + 14310 .syntax unified + 14311 .thumb + 14312 .thumb_func + 14314 HAL_TIM_OnePulse_Start_IT: + 14315 .LVL1016: + 14316 .LFB187: +2889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 14317 .loc 1 2889 1 is_stmt 1 view -0 + 14318 .cfi_startproc + 14319 @ args = 0, pretend = 0, frame = 0 + 14320 @ frame_needed = 0, uses_anonymous_args = 0 +2889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 14321 .loc 1 2889 1 is_stmt 0 view .LVU4161 + 14322 0000 10B5 push {r4, lr} + 14323 .LCFI106: + 14324 .cfi_def_cfa_offset 8 + 14325 .cfi_offset 4, -8 + 14326 .cfi_offset 14, -4 + 14327 0002 0446 mov r4, r0 +2890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 14328 .loc 1 2890 3 is_stmt 1 view .LVU4162 +2890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 14329 .loc 1 2890 31 is_stmt 0 view .LVU4163 + 14330 0004 90F83E10 ldrb r1, [r0, #62] @ zero_extendqisi2 + 14331 .LVL1017: +2890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 14332 .loc 1 2890 31 view .LVU4164 + 14333 0008 C9B2 uxtb r1, r1 + 14334 .LVL1018: +2891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 14335 .loc 1 2891 3 is_stmt 1 view .LVU4165 +2891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 14336 .loc 1 2891 31 is_stmt 0 view .LVU4166 + 14337 000a 90F83F20 ldrb r2, [r0, #63] @ zero_extendqisi2 + 14338 000e D2B2 uxtb r2, r2 + 14339 .LVL1019: +2892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 14340 .loc 1 2892 3 is_stmt 1 view .LVU4167 +2892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 14341 .loc 1 2892 31 is_stmt 0 view .LVU4168 + ARM GAS /tmp/ccGFzgX3.s page 452 + + + 14342 0010 90F84430 ldrb r3, [r0, #68] @ zero_extendqisi2 + 14343 0014 D8B2 uxtb r0, r3 + 14344 .LVL1020: +2893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14345 .loc 1 2893 3 is_stmt 1 view .LVU4169 +2893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14346 .loc 1 2893 31 is_stmt 0 view .LVU4170 + 14347 0016 94F84530 ldrb r3, [r4, #69] @ zero_extendqisi2 + 14348 .LVL1021: +2896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14349 .loc 1 2896 3 is_stmt 1 view .LVU4171 +2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 14350 .loc 1 2899 3 view .LVU4172 +2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 14351 .loc 1 2899 6 is_stmt 0 view .LVU4173 + 14352 001a 012A cmp r2, #1 + 14353 001c 08BF it eq + 14354 001e 0129 cmpeq r1, #1 + 14355 0020 30D1 bne .L1073 + 14356 0022 DBB2 uxtb r3, r3 +2902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14357 .loc 1 2902 41 view .LVU4174 + 14358 0024 013B subs r3, r3, #1 + 14359 .LVL1022: +2902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14360 .loc 1 2902 41 view .LVU4175 + 14361 0026 18BF it ne + 14362 0028 0123 movne r3, #1 + 14363 .LVL1023: +2902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14364 .loc 1 2902 7 view .LVU4176 + 14365 002a 0128 cmp r0, #1 + 14366 002c 2CD1 bne .L1074 + 14367 002e 5BBB cbnz r3, .L1074 +2908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 14368 .loc 1 2908 3 is_stmt 1 view .LVU4177 + 14369 0030 0223 movs r3, #2 + 14370 0032 84F83E30 strb r3, [r4, #62] +2909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 14371 .loc 1 2909 3 view .LVU4178 + 14372 0036 84F83F30 strb r3, [r4, #63] +2910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 14373 .loc 1 2910 3 view .LVU4179 + 14374 003a 84F84430 strb r3, [r4, #68] +2911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14375 .loc 1 2911 3 view .LVU4180 + 14376 003e 84F84530 strb r3, [r4, #69] +2923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14377 .loc 1 2923 3 view .LVU4181 + 14378 0042 2268 ldr r2, [r4] + 14379 .LVL1024: +2923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14380 .loc 1 2923 3 is_stmt 0 view .LVU4182 + 14381 0044 D368 ldr r3, [r2, #12] + 14382 0046 43F00203 orr r3, r3, #2 + 14383 004a D360 str r3, [r2, #12] +2926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 453 + + + 14384 .loc 1 2926 3 is_stmt 1 view .LVU4183 + 14385 004c 2268 ldr r2, [r4] + 14386 004e D368 ldr r3, [r2, #12] + 14387 0050 43F00403 orr r3, r3, #4 + 14388 0054 D360 str r3, [r2, #12] +2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 14389 .loc 1 2928 3 view .LVU4184 + 14390 0056 0122 movs r2, #1 + 14391 0058 0021 movs r1, #0 + 14392 .LVL1025: +2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 14393 .loc 1 2928 3 is_stmt 0 view .LVU4185 + 14394 005a 2068 ldr r0, [r4] + 14395 .LVL1026: +2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 14396 .loc 1 2928 3 view .LVU4186 + 14397 005c FFF7FEFF bl TIM_CCxChannelCmd + 14398 .LVL1027: +2929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14399 .loc 1 2929 3 is_stmt 1 view .LVU4187 + 14400 0060 0122 movs r2, #1 + 14401 0062 0421 movs r1, #4 + 14402 0064 2068 ldr r0, [r4] + 14403 0066 FFF7FEFF bl TIM_CCxChannelCmd + 14404 .LVL1028: +2931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14405 .loc 1 2931 3 view .LVU4188 +2931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14406 .loc 1 2931 7 is_stmt 0 view .LVU4189 + 14407 006a 2368 ldr r3, [r4] +2931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14408 .loc 1 2931 6 view .LVU4190 + 14409 006c 0849 ldr r1, .L1077 + 14410 006e 094A ldr r2, .L1077+4 + 14411 0070 9342 cmp r3, r2 + 14412 0072 18BF it ne + 14413 0074 8B42 cmpne r3, r1 + 14414 0076 09D1 bne .L1075 +2934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14415 .loc 1 2934 5 is_stmt 1 view .LVU4191 + 14416 0078 5A6C ldr r2, [r3, #68] + 14417 007a 42F40042 orr r2, r2, #32768 + 14418 007e 5A64 str r2, [r3, #68] +2938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14419 .loc 1 2938 10 is_stmt 0 view .LVU4192 + 14420 0080 0020 movs r0, #0 + 14421 0082 00E0 b .L1072 + 14422 .LVL1029: + 14423 .L1073: +2904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14424 .loc 1 2904 12 view .LVU4193 + 14425 0084 0120 movs r0, #1 + 14426 .LVL1030: + 14427 .L1072: +2939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14428 .loc 1 2939 1 view .LVU4194 + 14429 0086 10BD pop {r4, pc} + ARM GAS /tmp/ccGFzgX3.s page 454 + + + 14430 .LVL1031: + 14431 .L1074: +2904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14432 .loc 1 2904 12 view .LVU4195 + 14433 0088 0120 movs r0, #1 + 14434 .LVL1032: +2904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14435 .loc 1 2904 12 view .LVU4196 + 14436 008a FCE7 b .L1072 + 14437 .LVL1033: + 14438 .L1075: +2938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14439 .loc 1 2938 10 view .LVU4197 + 14440 008c 0020 movs r0, #0 + 14441 008e FAE7 b .L1072 + 14442 .L1078: + 14443 .align 2 + 14444 .L1077: + 14445 0090 00000140 .word 1073807360 + 14446 0094 00040140 .word 1073808384 + 14447 .cfi_endproc + 14448 .LFE187: + 14450 .section .text.HAL_TIM_OnePulse_Stop_IT,"ax",%progbits + 14451 .align 1 + 14452 .global HAL_TIM_OnePulse_Stop_IT + 14453 .syntax unified + 14454 .thumb + 14455 .thumb_func + 14457 HAL_TIM_OnePulse_Stop_IT: + 14458 .LVL1034: + 14459 .LFB188: +2952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 14460 .loc 1 2952 1 is_stmt 1 view -0 + 14461 .cfi_startproc + 14462 @ args = 0, pretend = 0, frame = 0 + 14463 @ frame_needed = 0, uses_anonymous_args = 0 +2952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 14464 .loc 1 2952 1 is_stmt 0 view .LVU4199 + 14465 0000 10B5 push {r4, lr} + 14466 .LCFI107: + 14467 .cfi_def_cfa_offset 8 + 14468 .cfi_offset 4, -8 + 14469 .cfi_offset 14, -4 + 14470 0002 0446 mov r4, r0 +2954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14471 .loc 1 2954 3 is_stmt 1 view .LVU4200 +2957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14472 .loc 1 2957 3 view .LVU4201 + 14473 0004 0268 ldr r2, [r0] + 14474 0006 D368 ldr r3, [r2, #12] + 14475 0008 23F00203 bic r3, r3, #2 + 14476 000c D360 str r3, [r2, #12] +2960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14477 .loc 1 2960 3 view .LVU4202 + 14478 000e 0268 ldr r2, [r0] + 14479 0010 D368 ldr r3, [r2, #12] + 14480 0012 23F00403 bic r3, r3, #4 + ARM GAS /tmp/ccGFzgX3.s page 455 + + + 14481 0016 D360 str r3, [r2, #12] +2967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 14482 .loc 1 2967 3 view .LVU4203 + 14483 0018 0022 movs r2, #0 + 14484 001a 1146 mov r1, r2 + 14485 .LVL1035: +2967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 14486 .loc 1 2967 3 is_stmt 0 view .LVU4204 + 14487 001c 0068 ldr r0, [r0] + 14488 .LVL1036: +2967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 14489 .loc 1 2967 3 view .LVU4205 + 14490 001e FFF7FEFF bl TIM_CCxChannelCmd + 14491 .LVL1037: +2968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14492 .loc 1 2968 3 is_stmt 1 view .LVU4206 + 14493 0022 0022 movs r2, #0 + 14494 0024 0421 movs r1, #4 + 14495 0026 2068 ldr r0, [r4] + 14496 0028 FFF7FEFF bl TIM_CCxChannelCmd + 14497 .LVL1038: +2970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14498 .loc 1 2970 3 view .LVU4207 +2970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14499 .loc 1 2970 7 is_stmt 0 view .LVU4208 + 14500 002c 2368 ldr r3, [r4] +2970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14501 .loc 1 2970 6 view .LVU4209 + 14502 002e 1749 ldr r1, .L1083 + 14503 0030 174A ldr r2, .L1083+4 + 14504 0032 9342 cmp r3, r2 + 14505 0034 18BF it ne + 14506 0036 8B42 cmpne r3, r1 + 14507 0038 0DD1 bne .L1080 +2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14508 .loc 1 2973 5 is_stmt 1 view .LVU4210 +2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14509 .loc 1 2973 5 view .LVU4211 + 14510 003a 196A ldr r1, [r3, #32] + 14511 003c 41F21112 movw r2, #4369 + 14512 0040 1142 tst r1, r2 + 14513 0042 08D1 bne .L1080 +2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14514 .loc 1 2973 5 discriminator 1 view .LVU4212 + 14515 0044 196A ldr r1, [r3, #32] + 14516 0046 40F24442 movw r2, #1092 + 14517 004a 1142 tst r1, r2 + 14518 004c 03D1 bne .L1080 +2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14519 .loc 1 2973 5 discriminator 3 view .LVU4213 + 14520 004e 5A6C ldr r2, [r3, #68] + 14521 0050 22F40042 bic r2, r2, #32768 + 14522 0054 5A64 str r2, [r3, #68] + 14523 .L1080: +2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14524 .loc 1 2973 5 discriminator 5 view .LVU4214 +2977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 456 + + + 14525 .loc 1 2977 3 view .LVU4215 +2977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14526 .loc 1 2977 3 view .LVU4216 + 14527 0056 2368 ldr r3, [r4] + 14528 0058 196A ldr r1, [r3, #32] + 14529 005a 41F21112 movw r2, #4369 + 14530 005e 1142 tst r1, r2 + 14531 0060 08D1 bne .L1081 +2977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14532 .loc 1 2977 3 discriminator 1 view .LVU4217 + 14533 0062 196A ldr r1, [r3, #32] + 14534 0064 40F24442 movw r2, #1092 + 14535 0068 1142 tst r1, r2 + 14536 006a 03D1 bne .L1081 +2977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14537 .loc 1 2977 3 discriminator 3 view .LVU4218 + 14538 006c 1A68 ldr r2, [r3] + 14539 006e 22F00102 bic r2, r2, #1 + 14540 0072 1A60 str r2, [r3] + 14541 .L1081: +2977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14542 .loc 1 2977 3 discriminator 5 view .LVU4219 +2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 14543 .loc 1 2980 3 view .LVU4220 + 14544 0074 0123 movs r3, #1 + 14545 0076 84F83E30 strb r3, [r4, #62] +2981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 14546 .loc 1 2981 3 view .LVU4221 + 14547 007a 84F83F30 strb r3, [r4, #63] +2982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 14548 .loc 1 2982 3 view .LVU4222 + 14549 007e 84F84430 strb r3, [r4, #68] +2983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14550 .loc 1 2983 3 view .LVU4223 + 14551 0082 84F84530 strb r3, [r4, #69] +2986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14552 .loc 1 2986 3 view .LVU4224 +2987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14553 .loc 1 2987 1 is_stmt 0 view .LVU4225 + 14554 0086 0020 movs r0, #0 + 14555 0088 10BD pop {r4, pc} + 14556 .LVL1039: + 14557 .L1084: +2987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14558 .loc 1 2987 1 view .LVU4226 + 14559 008a 00BF .align 2 + 14560 .L1083: + 14561 008c 00000140 .word 1073807360 + 14562 0090 00040140 .word 1073808384 + 14563 .cfi_endproc + 14564 .LFE188: + 14566 .section .text.HAL_TIM_Encoder_Start,"ax",%progbits + 14567 .align 1 + 14568 .global HAL_TIM_Encoder_Start + 14569 .syntax unified + 14570 .thumb + 14571 .thumb_func + ARM GAS /tmp/ccGFzgX3.s page 457 + + + 14573 HAL_TIM_Encoder_Start: + 14574 .LVL1040: + 14575 .LFB193: +3226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 14576 .loc 1 3226 1 is_stmt 1 view -0 + 14577 .cfi_startproc + 14578 @ args = 0, pretend = 0, frame = 0 + 14579 @ frame_needed = 0, uses_anonymous_args = 0 +3226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 14580 .loc 1 3226 1 is_stmt 0 view .LVU4228 + 14581 0000 38B5 push {r3, r4, r5, lr} + 14582 .LCFI108: + 14583 .cfi_def_cfa_offset 16 + 14584 .cfi_offset 3, -16 + 14585 .cfi_offset 4, -12 + 14586 .cfi_offset 5, -8 + 14587 .cfi_offset 14, -4 + 14588 0002 0446 mov r4, r0 +3227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 14589 .loc 1 3227 3 is_stmt 1 view .LVU4229 +3227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 14590 .loc 1 3227 31 is_stmt 0 view .LVU4230 + 14591 0004 90F83E30 ldrb r3, [r0, #62] @ zero_extendqisi2 + 14592 0008 DBB2 uxtb r3, r3 + 14593 .LVL1041: +3228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 14594 .loc 1 3228 3 is_stmt 1 view .LVU4231 +3228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 14595 .loc 1 3228 31 is_stmt 0 view .LVU4232 + 14596 000a 90F83F20 ldrb r2, [r0, #63] @ zero_extendqisi2 + 14597 000e 5FFA82FC uxtb ip, r2 + 14598 .LVL1042: +3229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 14599 .loc 1 3229 3 is_stmt 1 view .LVU4233 +3229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 14600 .loc 1 3229 31 is_stmt 0 view .LVU4234 + 14601 0012 90F84420 ldrb r2, [r0, #68] @ zero_extendqisi2 + 14602 0016 D0B2 uxtb r0, r2 + 14603 .LVL1043: +3230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14604 .loc 1 3230 3 is_stmt 1 view .LVU4235 +3230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14605 .loc 1 3230 31 is_stmt 0 view .LVU4236 + 14606 0018 94F84520 ldrb r2, [r4, #69] @ zero_extendqisi2 + 14607 .LVL1044: +3233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14608 .loc 1 3233 3 is_stmt 1 view .LVU4237 +3236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14609 .loc 1 3236 3 view .LVU4238 +3236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14610 .loc 1 3236 6 is_stmt 0 view .LVU4239 + 14611 001c 0D46 mov r5, r1 + 14612 001e B1B9 cbnz r1, .L1086 +3238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + 14613 .loc 1 3238 5 is_stmt 1 view .LVU4240 +3238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + 14614 .loc 1 3238 8 is_stmt 0 view .LVU4241 + ARM GAS /tmp/ccGFzgX3.s page 458 + + + 14615 0020 0128 cmp r0, #1 + 14616 0022 08BF it eq + 14617 0024 012B cmpeq r3, #1 + 14618 0026 47D1 bne .L1094 +3245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 14619 .loc 1 3245 7 is_stmt 1 view .LVU4242 + 14620 0028 0223 movs r3, #2 + 14621 .LVL1045: +3245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 14622 .loc 1 3245 7 is_stmt 0 view .LVU4243 + 14623 002a 84F83E30 strb r3, [r4, #62] +3246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14624 .loc 1 3246 7 is_stmt 1 view .LVU4244 + 14625 002e 84F84430 strb r3, [r4, #68] + 14626 .LVL1046: + 14627 .L1088: +3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14628 .loc 1 3281 3 view .LVU4245 + 14629 0032 7DB3 cbz r5, .L1090 + 14630 0034 042D cmp r5, #4 + 14631 0036 39D0 beq .L1091 +3297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 14632 .loc 1 3297 7 view .LVU4246 + 14633 0038 0122 movs r2, #1 + 14634 003a 0021 movs r1, #0 + 14635 .LVL1047: +3297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 14636 .loc 1 3297 7 is_stmt 0 view .LVU4247 + 14637 003c 2068 ldr r0, [r4] + 14638 .LVL1048: +3297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 14639 .loc 1 3297 7 view .LVU4248 + 14640 003e FFF7FEFF bl TIM_CCxChannelCmd + 14641 .LVL1049: +3298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 14642 .loc 1 3298 7 is_stmt 1 view .LVU4249 + 14643 0042 0122 movs r2, #1 + 14644 0044 0421 movs r1, #4 + 14645 0046 2068 ldr r0, [r4] + 14646 0048 FFF7FEFF bl TIM_CCxChannelCmd + 14647 .LVL1050: +3299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14648 .loc 1 3299 7 view .LVU4250 + 14649 004c 27E0 b .L1093 + 14650 .LVL1051: + 14651 .L1086: +3299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14652 .loc 1 3299 7 is_stmt 0 view .LVU4251 + 14653 004e D2B2 uxtb r2, r2 +3249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14654 .loc 1 3249 8 is_stmt 1 view .LVU4252 +3249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14655 .loc 1 3249 11 is_stmt 0 view .LVU4253 + 14656 0050 0429 cmp r1, #4 + 14657 0052 14D0 beq .L1100 +3264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 14658 .loc 1 3264 5 is_stmt 1 view .LVU4254 + ARM GAS /tmp/ccGFzgX3.s page 459 + + +3264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 14659 .loc 1 3264 8 is_stmt 0 view .LVU4255 + 14660 0054 BCF1010F cmp ip, #1 + 14661 0058 08BF it eq + 14662 005a 012B cmpeq r3, #1 + 14663 005c 30D1 bne .L1096 +3267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14664 .loc 1 3267 43 view .LVU4256 + 14665 005e 013A subs r2, r2, #1 + 14666 .LVL1052: +3267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14667 .loc 1 3267 43 view .LVU4257 + 14668 0060 18BF it ne + 14669 0062 0122 movne r2, #1 + 14670 .LVL1053: +3267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14671 .loc 1 3267 9 view .LVU4258 + 14672 0064 0128 cmp r0, #1 + 14673 0066 2DD1 bne .L1097 + 14674 0068 62BB cbnz r2, .L1097 +3273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 14675 .loc 1 3273 7 is_stmt 1 view .LVU4259 + 14676 006a 0223 movs r3, #2 + 14677 .LVL1054: +3273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 14678 .loc 1 3273 7 is_stmt 0 view .LVU4260 + 14679 006c 84F83E30 strb r3, [r4, #62] +3274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 14680 .loc 1 3274 7 is_stmt 1 view .LVU4261 + 14681 0070 84F83F30 strb r3, [r4, #63] +3275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 14682 .loc 1 3275 7 view .LVU4262 + 14683 0074 84F84430 strb r3, [r4, #68] +3276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14684 .loc 1 3276 7 view .LVU4263 + 14685 0078 84F84530 strb r3, [r4, #69] + 14686 007c D9E7 b .L1088 + 14687 .LVL1055: + 14688 .L1100: +3251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + 14689 .loc 1 3251 5 view .LVU4264 +3251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + 14690 .loc 1 3251 8 is_stmt 0 view .LVU4265 + 14691 007e 012A cmp r2, #1 + 14692 0080 08BF it eq + 14693 0082 BCF1010F cmpeq ip, #1 + 14694 0086 19D1 bne .L1095 +3258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 14695 .loc 1 3258 7 is_stmt 1 view .LVU4266 + 14696 0088 0223 movs r3, #2 + 14697 .LVL1056: +3258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 14698 .loc 1 3258 7 is_stmt 0 view .LVU4267 + 14699 008a 84F83F30 strb r3, [r4, #63] +3259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14700 .loc 1 3259 7 is_stmt 1 view .LVU4268 + 14701 008e 84F84530 strb r3, [r4, #69] + ARM GAS /tmp/ccGFzgX3.s page 460 + + + 14702 0092 CEE7 b .L1088 + 14703 .LVL1057: + 14704 .L1090: +3285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 14705 .loc 1 3285 7 view .LVU4269 + 14706 0094 0122 movs r2, #1 + 14707 0096 0021 movs r1, #0 + 14708 .LVL1058: +3285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 14709 .loc 1 3285 7 is_stmt 0 view .LVU4270 + 14710 0098 2068 ldr r0, [r4] + 14711 .LVL1059: +3285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 14712 .loc 1 3285 7 view .LVU4271 + 14713 009a FFF7FEFF bl TIM_CCxChannelCmd + 14714 .LVL1060: +3286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14715 .loc 1 3286 7 is_stmt 1 view .LVU4272 + 14716 .L1093: +3303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14717 .loc 1 3303 3 view .LVU4273 + 14718 009e 2268 ldr r2, [r4] + 14719 00a0 1368 ldr r3, [r2] + 14720 00a2 43F00103 orr r3, r3, #1 + 14721 00a6 1360 str r3, [r2] +3306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14722 .loc 1 3306 3 view .LVU4274 +3306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14723 .loc 1 3306 10 is_stmt 0 view .LVU4275 + 14724 00a8 0020 movs r0, #0 + 14725 .L1087: +3307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14726 .loc 1 3307 1 view .LVU4276 + 14727 00aa 38BD pop {r3, r4, r5, pc} + 14728 .LVL1061: + 14729 .L1091: +3291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 14730 .loc 1 3291 7 is_stmt 1 view .LVU4277 + 14731 00ac 0122 movs r2, #1 + 14732 00ae 0421 movs r1, #4 + 14733 .LVL1062: +3291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 14734 .loc 1 3291 7 is_stmt 0 view .LVU4278 + 14735 00b0 2068 ldr r0, [r4] + 14736 .LVL1063: +3291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 14737 .loc 1 3291 7 view .LVU4279 + 14738 00b2 FFF7FEFF bl TIM_CCxChannelCmd + 14739 .LVL1064: +3292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14740 .loc 1 3292 7 is_stmt 1 view .LVU4280 + 14741 00b6 F2E7 b .L1093 + 14742 .LVL1065: + 14743 .L1094: +3241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14744 .loc 1 3241 14 is_stmt 0 view .LVU4281 + 14745 00b8 0120 movs r0, #1 + ARM GAS /tmp/ccGFzgX3.s page 461 + + + 14746 .LVL1066: +3241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14747 .loc 1 3241 14 view .LVU4282 + 14748 00ba F6E7 b .L1087 + 14749 .LVL1067: + 14750 .L1095: +3254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14751 .loc 1 3254 14 view .LVU4283 + 14752 00bc 0120 movs r0, #1 + 14753 .LVL1068: +3254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14754 .loc 1 3254 14 view .LVU4284 + 14755 00be F4E7 b .L1087 + 14756 .LVL1069: + 14757 .L1096: +3269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14758 .loc 1 3269 14 view .LVU4285 + 14759 00c0 0120 movs r0, #1 + 14760 .LVL1070: +3269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14761 .loc 1 3269 14 view .LVU4286 + 14762 00c2 F2E7 b .L1087 + 14763 .LVL1071: + 14764 .L1097: +3269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14765 .loc 1 3269 14 view .LVU4287 + 14766 00c4 0120 movs r0, #1 + 14767 .LVL1072: +3269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14768 .loc 1 3269 14 view .LVU4288 + 14769 00c6 F0E7 b .L1087 + 14770 .cfi_endproc + 14771 .LFE193: + 14773 .section .text.HAL_TIM_Encoder_Stop,"ax",%progbits + 14774 .align 1 + 14775 .global HAL_TIM_Encoder_Stop + 14776 .syntax unified + 14777 .thumb + 14778 .thumb_func + 14780 HAL_TIM_Encoder_Stop: + 14781 .LVL1073: + 14782 .LFB194: +3320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 14783 .loc 1 3320 1 is_stmt 1 view -0 + 14784 .cfi_startproc + 14785 @ args = 0, pretend = 0, frame = 0 + 14786 @ frame_needed = 0, uses_anonymous_args = 0 +3320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 14787 .loc 1 3320 1 is_stmt 0 view .LVU4290 + 14788 0000 38B5 push {r3, r4, r5, lr} + 14789 .LCFI109: + 14790 .cfi_def_cfa_offset 16 + 14791 .cfi_offset 3, -16 + 14792 .cfi_offset 4, -12 + 14793 .cfi_offset 5, -8 + 14794 .cfi_offset 14, -4 + 14795 0002 0446 mov r4, r0 + ARM GAS /tmp/ccGFzgX3.s page 462 + + +3322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14796 .loc 1 3322 3 is_stmt 1 view .LVU4291 +3326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14797 .loc 1 3326 3 view .LVU4292 + 14798 0004 0D46 mov r5, r1 + 14799 0006 61B1 cbz r1, .L1102 + 14800 0008 0429 cmp r1, #4 + 14801 000a 2FD0 beq .L1103 +3342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 14802 .loc 1 3342 7 view .LVU4293 + 14803 000c 0022 movs r2, #0 + 14804 000e 1146 mov r1, r2 + 14805 .LVL1074: +3342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 14806 .loc 1 3342 7 is_stmt 0 view .LVU4294 + 14807 0010 0068 ldr r0, [r0] + 14808 .LVL1075: +3342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 14809 .loc 1 3342 7 view .LVU4295 + 14810 0012 FFF7FEFF bl TIM_CCxChannelCmd + 14811 .LVL1076: +3343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 14812 .loc 1 3343 7 is_stmt 1 view .LVU4296 + 14813 0016 0022 movs r2, #0 + 14814 0018 0421 movs r1, #4 + 14815 001a 2068 ldr r0, [r4] + 14816 001c FFF7FEFF bl TIM_CCxChannelCmd + 14817 .LVL1077: +3344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14818 .loc 1 3344 7 view .LVU4297 + 14819 0020 04E0 b .L1105 + 14820 .LVL1078: + 14821 .L1102: +3330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 14822 .loc 1 3330 7 view .LVU4298 + 14823 0022 0022 movs r2, #0 + 14824 0024 1146 mov r1, r2 + 14825 .LVL1079: +3330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 14826 .loc 1 3330 7 is_stmt 0 view .LVU4299 + 14827 0026 0068 ldr r0, [r0] + 14828 .LVL1080: +3330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 14829 .loc 1 3330 7 view .LVU4300 + 14830 0028 FFF7FEFF bl TIM_CCxChannelCmd + 14831 .LVL1081: +3331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14832 .loc 1 3331 7 is_stmt 1 view .LVU4301 + 14833 .L1105: +3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14834 .loc 1 3349 3 view .LVU4302 +3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14835 .loc 1 3349 3 view .LVU4303 + 14836 002c 2368 ldr r3, [r4] + 14837 002e 196A ldr r1, [r3, #32] + 14838 0030 41F21112 movw r2, #4369 + 14839 0034 1142 tst r1, r2 + ARM GAS /tmp/ccGFzgX3.s page 463 + + + 14840 0036 08D1 bne .L1106 +3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14841 .loc 1 3349 3 discriminator 1 view .LVU4304 + 14842 0038 196A ldr r1, [r3, #32] + 14843 003a 40F24442 movw r2, #1092 + 14844 003e 1142 tst r1, r2 + 14845 0040 03D1 bne .L1106 +3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14846 .loc 1 3349 3 discriminator 3 view .LVU4305 + 14847 0042 1A68 ldr r2, [r3] + 14848 0044 22F00102 bic r2, r2, #1 + 14849 0048 1A60 str r2, [r3] + 14850 .L1106: +3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14851 .loc 1 3349 3 discriminator 5 view .LVU4306 +3352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14852 .loc 1 3352 3 view .LVU4307 +3352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 14853 .loc 1 3352 6 is_stmt 0 view .LVU4308 + 14854 004a 042D cmp r5, #4 + 14855 004c 18BF it ne + 14856 004e 002D cmpne r5, #0 + 14857 0050 3ED1 bne .L1107 +3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 14858 .loc 1 3354 5 is_stmt 1 view .LVU4309 + 14859 0052 102D cmp r5, #16 + 14860 0054 2ED8 bhi .L1108 + 14861 0056 DFE805F0 tbb [pc, r5] + 14862 .L1110: + 14863 005a 0F .byte (.L1114-.L1110)/2 + 14864 005b 2D .byte (.L1108-.L1110)/2 + 14865 005c 2D .byte (.L1108-.L1110)/2 + 14866 005d 2D .byte (.L1108-.L1110)/2 + 14867 005e 16 .byte (.L1113-.L1110)/2 + 14868 005f 2D .byte (.L1108-.L1110)/2 + 14869 0060 2D .byte (.L1108-.L1110)/2 + 14870 0061 2D .byte (.L1108-.L1110)/2 + 14871 0062 21 .byte (.L1112-.L1110)/2 + 14872 0063 2D .byte (.L1108-.L1110)/2 + 14873 0064 2D .byte (.L1108-.L1110)/2 + 14874 0065 2D .byte (.L1108-.L1110)/2 + 14875 0066 25 .byte (.L1111-.L1110)/2 + 14876 0067 2D .byte (.L1108-.L1110)/2 + 14877 0068 2D .byte (.L1108-.L1110)/2 + 14878 0069 2D .byte (.L1108-.L1110)/2 + 14879 006a 29 .byte (.L1109-.L1110)/2 + 14880 .LVL1082: + 14881 006b 00 .p2align 1 + 14882 .L1103: +3336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 14883 .loc 1 3336 7 view .LVU4310 + 14884 006c 0022 movs r2, #0 + 14885 006e 0421 movs r1, #4 + 14886 .LVL1083: +3336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 14887 .loc 1 3336 7 is_stmt 0 view .LVU4311 + 14888 0070 0068 ldr r0, [r0] + ARM GAS /tmp/ccGFzgX3.s page 464 + + + 14889 .LVL1084: +3336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 14890 .loc 1 3336 7 view .LVU4312 + 14891 0072 FFF7FEFF bl TIM_CCxChannelCmd + 14892 .LVL1085: +3337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14893 .loc 1 3337 7 is_stmt 1 view .LVU4313 + 14894 0076 D9E7 b .L1105 + 14895 .L1114: +3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 14896 .loc 1 3354 5 is_stmt 0 discriminator 1 view .LVU4314 + 14897 0078 0123 movs r3, #1 + 14898 007a 84F83E30 strb r3, [r4, #62] +3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14899 .loc 1 3355 5 is_stmt 1 view .LVU4315 + 14900 .L1115: +3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14901 .loc 1 3355 5 is_stmt 0 discriminator 1 view .LVU4316 + 14902 007e 0123 movs r3, #1 + 14903 0080 84F84430 strb r3, [r4, #68] + 14904 0084 2DE0 b .L1117 + 14905 .L1113: +3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 14906 .loc 1 3354 5 discriminator 3 view .LVU4317 + 14907 0086 0123 movs r3, #1 + 14908 0088 84F83F30 strb r3, [r4, #63] +3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14909 .loc 1 3355 5 is_stmt 1 view .LVU4318 + 14910 .L1116: +3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14911 .loc 1 3355 5 is_stmt 0 discriminator 2 view .LVU4319 + 14912 008c 042D cmp r5, #4 + 14913 008e 17D0 beq .L1122 +3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14914 .loc 1 3355 5 discriminator 4 view .LVU4320 + 14915 0090 082D cmp r5, #8 + 14916 0092 19D0 beq .L1123 +3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14917 .loc 1 3355 5 discriminator 7 view .LVU4321 + 14918 0094 0123 movs r3, #1 + 14919 0096 84F84730 strb r3, [r4, #71] + 14920 009a 22E0 b .L1117 + 14921 .L1112: +3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 14922 .loc 1 3354 5 discriminator 6 view .LVU4322 + 14923 009c 0123 movs r3, #1 + 14924 009e 84F84030 strb r3, [r4, #64] +3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14925 .loc 1 3355 5 is_stmt 1 view .LVU4323 + 14926 00a2 F3E7 b .L1116 + 14927 .L1111: +3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 14928 .loc 1 3354 5 is_stmt 0 discriminator 9 view .LVU4324 + 14929 00a4 0123 movs r3, #1 + 14930 00a6 84F84130 strb r3, [r4, #65] +3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14931 .loc 1 3355 5 is_stmt 1 view .LVU4325 + ARM GAS /tmp/ccGFzgX3.s page 465 + + + 14932 00aa EFE7 b .L1116 + 14933 .L1109: +3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 14934 .loc 1 3354 5 is_stmt 0 discriminator 12 view .LVU4326 + 14935 00ac 0123 movs r3, #1 + 14936 00ae 84F84230 strb r3, [r4, #66] +3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14937 .loc 1 3355 5 is_stmt 1 view .LVU4327 + 14938 00b2 EBE7 b .L1116 + 14939 .L1108: +3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 14940 .loc 1 3354 5 is_stmt 0 discriminator 13 view .LVU4328 + 14941 00b4 0123 movs r3, #1 + 14942 00b6 84F84330 strb r3, [r4, #67] +3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14943 .loc 1 3355 5 is_stmt 1 view .LVU4329 + 14944 00ba 002D cmp r5, #0 + 14945 00bc E6D1 bne .L1116 + 14946 00be DEE7 b .L1115 + 14947 .L1122: +3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14948 .loc 1 3355 5 is_stmt 0 discriminator 3 view .LVU4330 + 14949 00c0 0123 movs r3, #1 + 14950 00c2 84F84530 strb r3, [r4, #69] + 14951 00c6 0CE0 b .L1117 + 14952 .L1123: +3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14953 .loc 1 3355 5 discriminator 6 view .LVU4331 + 14954 00c8 0123 movs r3, #1 + 14955 00ca 84F84630 strb r3, [r4, #70] + 14956 00ce 08E0 b .L1117 + 14957 .L1107: +3359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 14958 .loc 1 3359 5 is_stmt 1 view .LVU4332 + 14959 00d0 0123 movs r3, #1 + 14960 00d2 84F83E30 strb r3, [r4, #62] +3360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 14961 .loc 1 3360 5 view .LVU4333 + 14962 00d6 84F83F30 strb r3, [r4, #63] +3361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 14963 .loc 1 3361 5 view .LVU4334 + 14964 00da 84F84430 strb r3, [r4, #68] +3362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14965 .loc 1 3362 5 view .LVU4335 + 14966 00de 84F84530 strb r3, [r4, #69] + 14967 .L1117: +3366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 14968 .loc 1 3366 3 view .LVU4336 +3367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14969 .loc 1 3367 1 is_stmt 0 view .LVU4337 + 14970 00e2 0020 movs r0, #0 + 14971 00e4 38BD pop {r3, r4, r5, pc} +3367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 14972 .loc 1 3367 1 view .LVU4338 + 14973 .cfi_endproc + 14974 .LFE194: + 14976 .section .text.HAL_TIM_Encoder_Start_IT,"ax",%progbits + ARM GAS /tmp/ccGFzgX3.s page 466 + + + 14977 .align 1 + 14978 .global HAL_TIM_Encoder_Start_IT + 14979 .syntax unified + 14980 .thumb + 14981 .thumb_func + 14983 HAL_TIM_Encoder_Start_IT: + 14984 .LVL1086: + 14985 .LFB195: +3380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 14986 .loc 1 3380 1 is_stmt 1 view -0 + 14987 .cfi_startproc + 14988 @ args = 0, pretend = 0, frame = 0 + 14989 @ frame_needed = 0, uses_anonymous_args = 0 +3380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 14990 .loc 1 3380 1 is_stmt 0 view .LVU4340 + 14991 0000 38B5 push {r3, r4, r5, lr} + 14992 .LCFI110: + 14993 .cfi_def_cfa_offset 16 + 14994 .cfi_offset 3, -16 + 14995 .cfi_offset 4, -12 + 14996 .cfi_offset 5, -8 + 14997 .cfi_offset 14, -4 + 14998 0002 0446 mov r4, r0 +3381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 14999 .loc 1 3381 3 is_stmt 1 view .LVU4341 +3381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 15000 .loc 1 3381 31 is_stmt 0 view .LVU4342 + 15001 0004 90F83E30 ldrb r3, [r0, #62] @ zero_extendqisi2 + 15002 0008 DBB2 uxtb r3, r3 + 15003 .LVL1087: +3382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 15004 .loc 1 3382 3 is_stmt 1 view .LVU4343 +3382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 15005 .loc 1 3382 31 is_stmt 0 view .LVU4344 + 15006 000a 90F83F20 ldrb r2, [r0, #63] @ zero_extendqisi2 + 15007 000e 5FFA82FC uxtb ip, r2 + 15008 .LVL1088: +3383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 15009 .loc 1 3383 3 is_stmt 1 view .LVU4345 +3383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 15010 .loc 1 3383 31 is_stmt 0 view .LVU4346 + 15011 0012 90F84420 ldrb r2, [r0, #68] @ zero_extendqisi2 + 15012 0016 D0B2 uxtb r0, r2 + 15013 .LVL1089: +3384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15014 .loc 1 3384 3 is_stmt 1 view .LVU4347 +3384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15015 .loc 1 3384 31 is_stmt 0 view .LVU4348 + 15016 0018 94F84520 ldrb r2, [r4, #69] @ zero_extendqisi2 + 15017 .LVL1090: +3387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15018 .loc 1 3387 3 is_stmt 1 view .LVU4349 +3390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15019 .loc 1 3390 3 view .LVU4350 +3390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15020 .loc 1 3390 6 is_stmt 0 view .LVU4351 + 15021 001c 0D46 mov r5, r1 + ARM GAS /tmp/ccGFzgX3.s page 467 + + + 15022 001e 09BB cbnz r1, .L1125 +3392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + 15023 .loc 1 3392 5 is_stmt 1 view .LVU4352 +3392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + 15024 .loc 1 3392 8 is_stmt 0 view .LVU4353 + 15025 0020 0128 cmp r0, #1 + 15026 0022 08BF it eq + 15027 0024 012B cmpeq r3, #1 + 15028 0026 5DD1 bne .L1133 +3399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 15029 .loc 1 3399 7 is_stmt 1 view .LVU4354 + 15030 0028 0223 movs r3, #2 + 15031 .LVL1091: +3399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 15032 .loc 1 3399 7 is_stmt 0 view .LVU4355 + 15033 002a 84F83E30 strb r3, [r4, #62] +3400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15034 .loc 1 3400 7 is_stmt 1 view .LVU4356 + 15035 002e 84F84430 strb r3, [r4, #68] + 15036 .LVL1092: + 15037 .L1127: +3436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15038 .loc 1 3436 3 view .LVU4357 + 15039 0032 002D cmp r5, #0 + 15040 0034 3AD0 beq .L1129 + 15041 0036 042D cmp r5, #4 + 15042 0038 49D0 beq .L1130 +3454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 15043 .loc 1 3454 7 view .LVU4358 + 15044 003a 0122 movs r2, #1 + 15045 003c 0021 movs r1, #0 + 15046 .LVL1093: +3454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 15047 .loc 1 3454 7 is_stmt 0 view .LVU4359 + 15048 003e 2068 ldr r0, [r4] + 15049 .LVL1094: +3454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 15050 .loc 1 3454 7 view .LVU4360 + 15051 0040 FFF7FEFF bl TIM_CCxChannelCmd + 15052 .LVL1095: +3455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + 15053 .loc 1 3455 7 is_stmt 1 view .LVU4361 + 15054 0044 0122 movs r2, #1 + 15055 0046 0421 movs r1, #4 + 15056 0048 2068 ldr r0, [r4] + 15057 004a FFF7FEFF bl TIM_CCxChannelCmd + 15058 .LVL1096: +3456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + 15059 .loc 1 3456 7 view .LVU4362 + 15060 004e 2268 ldr r2, [r4] + 15061 0050 D368 ldr r3, [r2, #12] + 15062 0052 43F00203 orr r3, r3, #2 + 15063 0056 D360 str r3, [r2, #12] +3457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 15064 .loc 1 3457 7 view .LVU4363 + 15065 0058 2268 ldr r2, [r4] + 15066 005a D368 ldr r3, [r2, #12] + ARM GAS /tmp/ccGFzgX3.s page 468 + + + 15067 005c 43F00403 orr r3, r3, #4 + 15068 0060 D360 str r3, [r2, #12] +3458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15069 .loc 1 3458 7 view .LVU4364 + 15070 0062 2DE0 b .L1132 + 15071 .LVL1097: + 15072 .L1125: +3458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15073 .loc 1 3458 7 is_stmt 0 view .LVU4365 + 15074 0064 D2B2 uxtb r2, r2 +3403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15075 .loc 1 3403 8 is_stmt 1 view .LVU4366 +3403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15076 .loc 1 3403 11 is_stmt 0 view .LVU4367 + 15077 0066 0429 cmp r1, #4 + 15078 0068 15D0 beq .L1139 +3418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 15079 .loc 1 3418 5 is_stmt 1 view .LVU4368 +3418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 15080 .loc 1 3418 8 is_stmt 0 view .LVU4369 + 15081 006a BCF1010F cmp ip, #1 + 15082 006e 08BF it eq + 15083 0070 012B cmpeq r3, #1 + 15084 0072 3BD1 bne .L1135 +3421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15085 .loc 1 3421 43 view .LVU4370 + 15086 0074 013A subs r2, r2, #1 + 15087 .LVL1098: +3421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15088 .loc 1 3421 43 view .LVU4371 + 15089 0076 18BF it ne + 15090 0078 0122 movne r2, #1 + 15091 .LVL1099: +3421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15092 .loc 1 3421 9 view .LVU4372 + 15093 007a 0128 cmp r0, #1 + 15094 007c 38D1 bne .L1136 + 15095 007e 002A cmp r2, #0 + 15096 0080 36D1 bne .L1136 +3427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 15097 .loc 1 3427 7 is_stmt 1 view .LVU4373 + 15098 0082 0223 movs r3, #2 + 15099 .LVL1100: +3427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 15100 .loc 1 3427 7 is_stmt 0 view .LVU4374 + 15101 0084 84F83E30 strb r3, [r4, #62] +3428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 15102 .loc 1 3428 7 is_stmt 1 view .LVU4375 + 15103 0088 84F83F30 strb r3, [r4, #63] +3429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 15104 .loc 1 3429 7 view .LVU4376 + 15105 008c 84F84430 strb r3, [r4, #68] +3430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15106 .loc 1 3430 7 view .LVU4377 + 15107 0090 84F84530 strb r3, [r4, #69] + 15108 0094 CDE7 b .L1127 + 15109 .LVL1101: + ARM GAS /tmp/ccGFzgX3.s page 469 + + + 15110 .L1139: +3405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + 15111 .loc 1 3405 5 view .LVU4378 +3405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + 15112 .loc 1 3405 8 is_stmt 0 view .LVU4379 + 15113 0096 012A cmp r2, #1 + 15114 0098 08BF it eq + 15115 009a BCF1010F cmpeq ip, #1 + 15116 009e 23D1 bne .L1134 +3412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 15117 .loc 1 3412 7 is_stmt 1 view .LVU4380 + 15118 00a0 0223 movs r3, #2 + 15119 .LVL1102: +3412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 15120 .loc 1 3412 7 is_stmt 0 view .LVU4381 + 15121 00a2 84F83F30 strb r3, [r4, #63] +3413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15122 .loc 1 3413 7 is_stmt 1 view .LVU4382 + 15123 00a6 84F84530 strb r3, [r4, #69] + 15124 00aa C2E7 b .L1127 + 15125 .LVL1103: + 15126 .L1129: +3440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + 15127 .loc 1 3440 7 view .LVU4383 + 15128 00ac 0122 movs r2, #1 + 15129 00ae 0021 movs r1, #0 + 15130 .LVL1104: +3440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + 15131 .loc 1 3440 7 is_stmt 0 view .LVU4384 + 15132 00b0 2068 ldr r0, [r4] + 15133 .LVL1105: +3440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + 15134 .loc 1 3440 7 view .LVU4385 + 15135 00b2 FFF7FEFF bl TIM_CCxChannelCmd + 15136 .LVL1106: +3441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 15137 .loc 1 3441 7 is_stmt 1 view .LVU4386 + 15138 00b6 2268 ldr r2, [r4] + 15139 00b8 D368 ldr r3, [r2, #12] + 15140 00ba 43F00203 orr r3, r3, #2 + 15141 00be D360 str r3, [r2, #12] +3442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15142 .loc 1 3442 7 view .LVU4387 + 15143 .L1132: +3463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15144 .loc 1 3463 3 view .LVU4388 + 15145 00c0 2268 ldr r2, [r4] + 15146 00c2 1368 ldr r3, [r2] + 15147 00c4 43F00103 orr r3, r3, #1 + 15148 00c8 1360 str r3, [r2] +3466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15149 .loc 1 3466 3 view .LVU4389 +3466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15150 .loc 1 3466 10 is_stmt 0 view .LVU4390 + 15151 00ca 0020 movs r0, #0 + 15152 .L1126: +3467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + ARM GAS /tmp/ccGFzgX3.s page 470 + + + 15153 .loc 1 3467 1 view .LVU4391 + 15154 00cc 38BD pop {r3, r4, r5, pc} + 15155 .LVL1107: + 15156 .L1130: +3447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + 15157 .loc 1 3447 7 is_stmt 1 view .LVU4392 + 15158 00ce 0122 movs r2, #1 + 15159 00d0 0421 movs r1, #4 + 15160 .LVL1108: +3447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + 15161 .loc 1 3447 7 is_stmt 0 view .LVU4393 + 15162 00d2 2068 ldr r0, [r4] + 15163 .LVL1109: +3447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + 15164 .loc 1 3447 7 view .LVU4394 + 15165 00d4 FFF7FEFF bl TIM_CCxChannelCmd + 15166 .LVL1110: +3448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** break; + 15167 .loc 1 3448 7 is_stmt 1 view .LVU4395 + 15168 00d8 2268 ldr r2, [r4] + 15169 00da D368 ldr r3, [r2, #12] + 15170 00dc 43F00403 orr r3, r3, #4 + 15171 00e0 D360 str r3, [r2, #12] +3449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15172 .loc 1 3449 7 view .LVU4396 + 15173 00e2 EDE7 b .L1132 + 15174 .LVL1111: + 15175 .L1133: +3395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15176 .loc 1 3395 14 is_stmt 0 view .LVU4397 + 15177 00e4 0120 movs r0, #1 + 15178 .LVL1112: +3395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15179 .loc 1 3395 14 view .LVU4398 + 15180 00e6 F1E7 b .L1126 + 15181 .LVL1113: + 15182 .L1134: +3408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15183 .loc 1 3408 14 view .LVU4399 + 15184 00e8 0120 movs r0, #1 + 15185 .LVL1114: +3408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15186 .loc 1 3408 14 view .LVU4400 + 15187 00ea EFE7 b .L1126 + 15188 .LVL1115: + 15189 .L1135: +3423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15190 .loc 1 3423 14 view .LVU4401 + 15191 00ec 0120 movs r0, #1 + 15192 .LVL1116: +3423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15193 .loc 1 3423 14 view .LVU4402 + 15194 00ee EDE7 b .L1126 + 15195 .LVL1117: + 15196 .L1136: +3423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15197 .loc 1 3423 14 view .LVU4403 + ARM GAS /tmp/ccGFzgX3.s page 471 + + + 15198 00f0 0120 movs r0, #1 + 15199 .LVL1118: +3423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15200 .loc 1 3423 14 view .LVU4404 + 15201 00f2 EBE7 b .L1126 + 15202 .cfi_endproc + 15203 .LFE195: + 15205 .section .text.HAL_TIM_Encoder_Stop_IT,"ax",%progbits + 15206 .align 1 + 15207 .global HAL_TIM_Encoder_Stop_IT + 15208 .syntax unified + 15209 .thumb + 15210 .thumb_func + 15212 HAL_TIM_Encoder_Stop_IT: + 15213 .LVL1119: + 15214 .LFB196: +3480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 15215 .loc 1 3480 1 is_stmt 1 view -0 + 15216 .cfi_startproc + 15217 @ args = 0, pretend = 0, frame = 0 + 15218 @ frame_needed = 0, uses_anonymous_args = 0 +3480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 15219 .loc 1 3480 1 is_stmt 0 view .LVU4406 + 15220 0000 38B5 push {r3, r4, r5, lr} + 15221 .LCFI111: + 15222 .cfi_def_cfa_offset 16 + 15223 .cfi_offset 3, -16 + 15224 .cfi_offset 4, -12 + 15225 .cfi_offset 5, -8 + 15226 .cfi_offset 14, -4 + 15227 0002 0446 mov r4, r0 +3482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15228 .loc 1 3482 3 is_stmt 1 view .LVU4407 +3486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15229 .loc 1 3486 3 view .LVU4408 +3486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15230 .loc 1 3486 6 is_stmt 0 view .LVU4409 + 15231 0004 0D46 mov r5, r1 + 15232 0006 0029 cmp r1, #0 + 15233 0008 35D0 beq .L1159 +3493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15234 .loc 1 3493 8 is_stmt 1 view .LVU4410 +3493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15235 .loc 1 3493 11 is_stmt 0 view .LVU4411 + 15236 000a 0429 cmp r1, #4 + 15237 000c 3ED0 beq .L1160 +3502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 15238 .loc 1 3502 5 is_stmt 1 view .LVU4412 + 15239 000e 0022 movs r2, #0 + 15240 0010 1146 mov r1, r2 + 15241 .LVL1120: +3502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 15242 .loc 1 3502 5 is_stmt 0 view .LVU4413 + 15243 0012 0068 ldr r0, [r0] + 15244 .LVL1121: +3502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 15245 .loc 1 3502 5 view .LVU4414 + ARM GAS /tmp/ccGFzgX3.s page 472 + + + 15246 0014 FFF7FEFF bl TIM_CCxChannelCmd + 15247 .LVL1122: +3503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15248 .loc 1 3503 5 is_stmt 1 view .LVU4415 + 15249 0018 0022 movs r2, #0 + 15250 001a 0421 movs r1, #4 + 15251 001c 2068 ldr r0, [r4] + 15252 001e FFF7FEFF bl TIM_CCxChannelCmd + 15253 .LVL1123: +3506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + 15254 .loc 1 3506 5 view .LVU4416 + 15255 0022 2268 ldr r2, [r4] + 15256 0024 D368 ldr r3, [r2, #12] + 15257 0026 23F00203 bic r3, r3, #2 + 15258 002a D360 str r3, [r2, #12] +3507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15259 .loc 1 3507 5 view .LVU4417 + 15260 002c 2268 ldr r2, [r4] + 15261 002e D368 ldr r3, [r2, #12] + 15262 0030 23F00403 bic r3, r3, #4 + 15263 0034 D360 str r3, [r2, #12] + 15264 .L1142: +3511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15265 .loc 1 3511 3 view .LVU4418 +3511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15266 .loc 1 3511 3 view .LVU4419 + 15267 0036 2368 ldr r3, [r4] + 15268 0038 196A ldr r1, [r3, #32] + 15269 003a 41F21112 movw r2, #4369 + 15270 003e 1142 tst r1, r2 + 15271 0040 08D1 bne .L1144 +3511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15272 .loc 1 3511 3 discriminator 1 view .LVU4420 + 15273 0042 196A ldr r1, [r3, #32] + 15274 0044 40F24442 movw r2, #1092 + 15275 0048 1142 tst r1, r2 + 15276 004a 03D1 bne .L1144 +3511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15277 .loc 1 3511 3 discriminator 3 view .LVU4421 + 15278 004c 1A68 ldr r2, [r3] + 15279 004e 22F00102 bic r2, r2, #1 + 15280 0052 1A60 str r2, [r3] + 15281 .L1144: +3511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15282 .loc 1 3511 3 discriminator 5 view .LVU4422 +3514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15283 .loc 1 3514 3 view .LVU4423 +3514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15284 .loc 1 3514 6 is_stmt 0 view .LVU4424 + 15285 0054 042D cmp r5, #4 + 15286 0056 18BF it ne + 15287 0058 002D cmpne r5, #0 + 15288 005a 4ED1 bne .L1145 +3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 15289 .loc 1 3516 5 is_stmt 1 view .LVU4425 + 15290 005c 102D cmp r5, #16 + 15291 005e 3ED8 bhi .L1146 + ARM GAS /tmp/ccGFzgX3.s page 473 + + + 15292 0060 DFE805F0 tbb [pc, r5] + 15293 .L1148: + 15294 0064 1F .byte (.L1152-.L1148)/2 + 15295 0065 3D .byte (.L1146-.L1148)/2 + 15296 0066 3D .byte (.L1146-.L1148)/2 + 15297 0067 3D .byte (.L1146-.L1148)/2 + 15298 0068 26 .byte (.L1151-.L1148)/2 + 15299 0069 3D .byte (.L1146-.L1148)/2 + 15300 006a 3D .byte (.L1146-.L1148)/2 + 15301 006b 3D .byte (.L1146-.L1148)/2 + 15302 006c 31 .byte (.L1150-.L1148)/2 + 15303 006d 3D .byte (.L1146-.L1148)/2 + 15304 006e 3D .byte (.L1146-.L1148)/2 + 15305 006f 3D .byte (.L1146-.L1148)/2 + 15306 0070 35 .byte (.L1149-.L1148)/2 + 15307 0071 3D .byte (.L1146-.L1148)/2 + 15308 0072 3D .byte (.L1146-.L1148)/2 + 15309 0073 3D .byte (.L1146-.L1148)/2 + 15310 0074 39 .byte (.L1147-.L1148)/2 + 15311 .LVL1124: + 15312 0075 00 .p2align 1 + 15313 .L1159: +3488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15314 .loc 1 3488 5 view .LVU4426 + 15315 0076 0022 movs r2, #0 + 15316 0078 1146 mov r1, r2 + 15317 .LVL1125: +3488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15318 .loc 1 3488 5 is_stmt 0 view .LVU4427 + 15319 007a 0068 ldr r0, [r0] + 15320 .LVL1126: +3488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15321 .loc 1 3488 5 view .LVU4428 + 15322 007c FFF7FEFF bl TIM_CCxChannelCmd + 15323 .LVL1127: +3491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15324 .loc 1 3491 5 is_stmt 1 view .LVU4429 + 15325 0080 2268 ldr r2, [r4] + 15326 0082 D368 ldr r3, [r2, #12] + 15327 0084 23F00203 bic r3, r3, #2 + 15328 0088 D360 str r3, [r2, #12] + 15329 008a D4E7 b .L1142 + 15330 .LVL1128: + 15331 .L1160: +3495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15332 .loc 1 3495 5 view .LVU4430 + 15333 008c 0022 movs r2, #0 + 15334 008e 0421 movs r1, #4 + 15335 .LVL1129: +3495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15336 .loc 1 3495 5 is_stmt 0 view .LVU4431 + 15337 0090 0068 ldr r0, [r0] + 15338 .LVL1130: +3495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15339 .loc 1 3495 5 view .LVU4432 + 15340 0092 FFF7FEFF bl TIM_CCxChannelCmd + 15341 .LVL1131: + ARM GAS /tmp/ccGFzgX3.s page 474 + + +3498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15342 .loc 1 3498 5 is_stmt 1 view .LVU4433 + 15343 0096 2268 ldr r2, [r4] + 15344 0098 D368 ldr r3, [r2, #12] + 15345 009a 23F00403 bic r3, r3, #4 + 15346 009e D360 str r3, [r2, #12] + 15347 00a0 C9E7 b .L1142 + 15348 .L1152: +3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 15349 .loc 1 3516 5 is_stmt 0 discriminator 1 view .LVU4434 + 15350 00a2 0123 movs r3, #1 + 15351 00a4 84F83E30 strb r3, [r4, #62] +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15352 .loc 1 3517 5 is_stmt 1 view .LVU4435 + 15353 .L1153: +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15354 .loc 1 3517 5 is_stmt 0 discriminator 1 view .LVU4436 + 15355 00a8 0123 movs r3, #1 + 15356 00aa 84F84430 strb r3, [r4, #68] + 15357 00ae 2DE0 b .L1155 + 15358 .L1151: +3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 15359 .loc 1 3516 5 discriminator 3 view .LVU4437 + 15360 00b0 0123 movs r3, #1 + 15361 00b2 84F83F30 strb r3, [r4, #63] +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15362 .loc 1 3517 5 is_stmt 1 view .LVU4438 + 15363 .L1154: +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15364 .loc 1 3517 5 is_stmt 0 discriminator 2 view .LVU4439 + 15365 00b6 042D cmp r5, #4 + 15366 00b8 17D0 beq .L1161 +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15367 .loc 1 3517 5 discriminator 4 view .LVU4440 + 15368 00ba 082D cmp r5, #8 + 15369 00bc 19D0 beq .L1162 +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15370 .loc 1 3517 5 discriminator 7 view .LVU4441 + 15371 00be 0123 movs r3, #1 + 15372 00c0 84F84730 strb r3, [r4, #71] + 15373 00c4 22E0 b .L1155 + 15374 .L1150: +3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 15375 .loc 1 3516 5 discriminator 6 view .LVU4442 + 15376 00c6 0123 movs r3, #1 + 15377 00c8 84F84030 strb r3, [r4, #64] +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15378 .loc 1 3517 5 is_stmt 1 view .LVU4443 + 15379 00cc F3E7 b .L1154 + 15380 .L1149: +3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 15381 .loc 1 3516 5 is_stmt 0 discriminator 9 view .LVU4444 + 15382 00ce 0123 movs r3, #1 + 15383 00d0 84F84130 strb r3, [r4, #65] +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15384 .loc 1 3517 5 is_stmt 1 view .LVU4445 + 15385 00d4 EFE7 b .L1154 + ARM GAS /tmp/ccGFzgX3.s page 475 + + + 15386 .L1147: +3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 15387 .loc 1 3516 5 is_stmt 0 discriminator 12 view .LVU4446 + 15388 00d6 0123 movs r3, #1 + 15389 00d8 84F84230 strb r3, [r4, #66] +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15390 .loc 1 3517 5 is_stmt 1 view .LVU4447 + 15391 00dc EBE7 b .L1154 + 15392 .L1146: +3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 15393 .loc 1 3516 5 is_stmt 0 discriminator 13 view .LVU4448 + 15394 00de 0123 movs r3, #1 + 15395 00e0 84F84330 strb r3, [r4, #67] +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15396 .loc 1 3517 5 is_stmt 1 view .LVU4449 + 15397 00e4 002D cmp r5, #0 + 15398 00e6 E6D1 bne .L1154 + 15399 00e8 DEE7 b .L1153 + 15400 .L1161: +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15401 .loc 1 3517 5 is_stmt 0 discriminator 3 view .LVU4450 + 15402 00ea 0123 movs r3, #1 + 15403 00ec 84F84530 strb r3, [r4, #69] + 15404 00f0 0CE0 b .L1155 + 15405 .L1162: +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15406 .loc 1 3517 5 discriminator 6 view .LVU4451 + 15407 00f2 0123 movs r3, #1 + 15408 00f4 84F84630 strb r3, [r4, #70] + 15409 00f8 08E0 b .L1155 + 15410 .L1145: +3521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 15411 .loc 1 3521 5 is_stmt 1 view .LVU4452 + 15412 00fa 0123 movs r3, #1 + 15413 00fc 84F83E30 strb r3, [r4, #62] +3522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 15414 .loc 1 3522 5 view .LVU4453 + 15415 0100 84F83F30 strb r3, [r4, #63] +3523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 15416 .loc 1 3523 5 view .LVU4454 + 15417 0104 84F84430 strb r3, [r4, #68] +3524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15418 .loc 1 3524 5 view .LVU4455 + 15419 0108 84F84530 strb r3, [r4, #69] + 15420 .L1155: +3528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15421 .loc 1 3528 3 view .LVU4456 +3529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15422 .loc 1 3529 1 is_stmt 0 view .LVU4457 + 15423 010c 0020 movs r0, #0 + 15424 010e 38BD pop {r3, r4, r5, pc} +3529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15425 .loc 1 3529 1 view .LVU4458 + 15426 .cfi_endproc + 15427 .LFE196: + 15429 .section .text.HAL_TIM_Encoder_Start_DMA,"ax",%progbits + 15430 .align 1 + ARM GAS /tmp/ccGFzgX3.s page 476 + + + 15431 .global HAL_TIM_Encoder_Start_DMA + 15432 .syntax unified + 15433 .thumb + 15434 .thumb_func + 15436 HAL_TIM_Encoder_Start_DMA: + 15437 .LVL1132: + 15438 .LFB197: +3546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 15439 .loc 1 3546 1 is_stmt 1 view -0 + 15440 .cfi_startproc + 15441 @ args = 4, pretend = 0, frame = 0 + 15442 @ frame_needed = 0, uses_anonymous_args = 0 +3546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 15443 .loc 1 3546 1 is_stmt 0 view .LVU4460 + 15444 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 15445 .LCFI112: + 15446 .cfi_def_cfa_offset 24 + 15447 .cfi_offset 3, -24 + 15448 .cfi_offset 4, -20 + 15449 .cfi_offset 5, -16 + 15450 .cfi_offset 6, -12 + 15451 .cfi_offset 7, -8 + 15452 .cfi_offset 14, -4 + 15453 0002 0446 mov r4, r0 + 15454 0004 1D46 mov r5, r3 + 15455 0006 BDF81860 ldrh r6, [sp, #24] +3547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 15456 .loc 1 3547 3 is_stmt 1 view .LVU4461 +3547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 15457 .loc 1 3547 31 is_stmt 0 view .LVU4462 + 15458 000a 90F83E00 ldrb r0, [r0, #62] @ zero_extendqisi2 + 15459 .LVL1133: +3547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 15460 .loc 1 3547 31 view .LVU4463 + 15461 000e C0B2 uxtb r0, r0 + 15462 .LVL1134: +3548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 15463 .loc 1 3548 3 is_stmt 1 view .LVU4464 +3548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 15464 .loc 1 3548 31 is_stmt 0 view .LVU4465 + 15465 0010 94F83F30 ldrb r3, [r4, #63] @ zero_extendqisi2 + 15466 .LVL1135: +3549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 15467 .loc 1 3549 3 is_stmt 1 view .LVU4466 +3549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 15468 .loc 1 3549 31 is_stmt 0 view .LVU4467 + 15469 0014 94F844C0 ldrb ip, [r4, #68] @ zero_extendqisi2 + 15470 0018 5FFA8CFC uxtb ip, ip + 15471 .LVL1136: +3550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15472 .loc 1 3550 3 is_stmt 1 view .LVU4468 +3550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15473 .loc 1 3550 31 is_stmt 0 view .LVU4469 + 15474 001c 94F845E0 ldrb lr, [r4, #69] @ zero_extendqisi2 + 15475 .LVL1137: +3553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15476 .loc 1 3553 3 is_stmt 1 view .LVU4470 + ARM GAS /tmp/ccGFzgX3.s page 477 + + +3556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15477 .loc 1 3556 3 view .LVU4471 +3556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15478 .loc 1 3556 6 is_stmt 0 view .LVU4472 + 15479 0020 0F46 mov r7, r1 + 15480 0022 71BB cbnz r1, .L1164 +3558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + 15481 .loc 1 3558 5 is_stmt 1 view .LVU4473 +3558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + 15482 .loc 1 3558 8 is_stmt 0 view .LVU4474 + 15483 0024 BCF1020F cmp ip, #2 + 15484 0028 18BF it ne + 15485 002a 0228 cmpne r0, #2 + 15486 002c 00F0EE80 beq .L1171 +3563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + 15487 .loc 1 3563 10 is_stmt 1 view .LVU4475 +3563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + 15488 .loc 1 3563 13 is_stmt 0 view .LVU4476 + 15489 0030 0128 cmp r0, #1 + 15490 0032 08BF it eq + 15491 0034 BCF1010F cmpeq ip, #1 + 15492 0038 40F0EA80 bne .L1172 +3566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15493 .loc 1 3566 7 is_stmt 1 view .LVU4477 +3566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15494 .loc 1 3566 10 is_stmt 0 view .LVU4478 + 15495 003c 002E cmp r6, #0 + 15496 003e 18BF it ne + 15497 0040 002A cmpne r2, #0 + 15498 0042 00F0E880 beq .L1173 +3572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 15499 .loc 1 3572 9 is_stmt 1 view .LVU4479 + 15500 0046 0223 movs r3, #2 + 15501 .LVL1138: +3572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 15502 .loc 1 3572 9 is_stmt 0 view .LVU4480 + 15503 0048 84F83E30 strb r3, [r4, #62] +3573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15504 .loc 1 3573 9 is_stmt 1 view .LVU4481 + 15505 004c 84F84430 strb r3, [r4, #68] + 15506 .LVL1139: + 15507 .L1166: +3638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15508 .loc 1 3638 3 view .LVU4482 + 15509 0050 002F cmp r7, #0 + 15510 0052 66D0 beq .L1168 + 15511 0054 042F cmp r7, #4 + 15512 0056 00F08780 beq .L1169 +3698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 15513 .loc 1 3698 7 view .LVU4483 +3698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 15514 .loc 1 3698 17 is_stmt 0 view .LVU4484 + 15515 005a 636A ldr r3, [r4, #36] +3698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 15516 .loc 1 3698 52 view .LVU4485 + 15517 005c 7849 ldr r1, .L1194 + 15518 005e D963 str r1, [r3, #60] + ARM GAS /tmp/ccGFzgX3.s page 478 + + +3699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15519 .loc 1 3699 7 is_stmt 1 view .LVU4486 +3699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15520 .loc 1 3699 17 is_stmt 0 view .LVU4487 + 15521 0060 636A ldr r3, [r4, #36] +3699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15522 .loc 1 3699 56 view .LVU4488 + 15523 0062 7849 ldr r1, .L1194+4 + 15524 0064 1964 str r1, [r3, #64] +3702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15525 .loc 1 3702 7 is_stmt 1 view .LVU4489 +3702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15526 .loc 1 3702 17 is_stmt 0 view .LVU4490 + 15527 0066 636A ldr r3, [r4, #36] +3702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15528 .loc 1 3702 53 view .LVU4491 + 15529 0068 7749 ldr r1, .L1194+8 + 15530 006a D964 str r1, [r3, #76] +3705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15531 .loc 1 3705 7 is_stmt 1 view .LVU4492 +3705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15532 .loc 1 3705 71 is_stmt 0 view .LVU4493 + 15533 006c 2168 ldr r1, [r4] +3705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15534 .loc 1 3705 11 view .LVU4494 + 15535 006e 3346 mov r3, r6 + 15536 0070 3431 adds r1, r1, #52 + 15537 0072 606A ldr r0, [r4, #36] + 15538 .LVL1140: +3705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15539 .loc 1 3705 11 view .LVU4495 + 15540 0074 FFF7FEFF bl HAL_DMA_Start_IT + 15541 .LVL1141: +3705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15542 .loc 1 3705 10 discriminator 1 view .LVU4496 + 15543 0078 0028 cmp r0, #0 + 15544 007a 00F09980 beq .L1189 +3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15545 .loc 1 3709 16 view .LVU4497 + 15546 007e 0125 movs r5, #1 + 15547 .LVL1142: +3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15548 .loc 1 3709 16 view .LVU4498 + 15549 0080 C7E0 b .L1165 + 15550 .LVL1143: + 15551 .L1164: +3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15552 .loc 1 3709 16 view .LVU4499 + 15553 0082 DBB2 uxtb r3, r3 +3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15554 .loc 1 3709 16 view .LVU4500 + 15555 0084 5FFA8EFE uxtb lr, lr +3581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15556 .loc 1 3581 8 is_stmt 1 view .LVU4501 +3581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15557 .loc 1 3581 11 is_stmt 0 view .LVU4502 + 15558 0088 0429 cmp r1, #4 + ARM GAS /tmp/ccGFzgX3.s page 479 + + + 15559 008a 33D0 beq .L1190 +3608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + 15560 .loc 1 3608 5 is_stmt 1 view .LVU4503 +3608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + 15561 .loc 1 3608 8 is_stmt 0 view .LVU4504 + 15562 008c 022B cmp r3, #2 + 15563 008e 18BF it ne + 15564 0090 0228 cmpne r0, #2 + 15565 0092 00F0C880 beq .L1177 +3611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15566 .loc 1 3611 43 view .LVU4505 + 15567 0096 BEF1020F cmp lr, #2 + 15568 009a 14BF ite ne + 15569 009c 0021 movne r1, #0 + 15570 .LVL1144: +3611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15571 .loc 1 3611 43 view .LVU4506 + 15572 009e 0121 moveq r1, #1 +3611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15573 .loc 1 3611 9 view .LVU4507 + 15574 00a0 BCF1020F cmp ip, #2 + 15575 00a4 00F0C180 beq .L1178 + 15576 00a8 0029 cmp r1, #0 + 15577 00aa 40F0BE80 bne .L1178 +3615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + 15578 .loc 1 3615 10 is_stmt 1 view .LVU4508 +3615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + 15579 .loc 1 3615 13 is_stmt 0 view .LVU4509 + 15580 00ae 0128 cmp r0, #1 + 15581 00b0 08BF it eq + 15582 00b2 012B cmpeq r3, #1 + 15583 00b4 40F0BB80 bne .L1179 +3618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15584 .loc 1 3618 48 view .LVU4510 + 15585 00b8 BEF1010F cmp lr, #1 + 15586 00bc 14BF ite ne + 15587 00be 0023 movne r3, #0 + 15588 .LVL1145: +3618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15589 .loc 1 3618 48 view .LVU4511 + 15590 00c0 0123 moveq r3, #1 +3618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15591 .loc 1 3618 14 view .LVU4512 + 15592 00c2 BCF1010F cmp ip, #1 + 15593 00c6 40F0B480 bne .L1180 + 15594 00ca 002B cmp r3, #0 + 15595 00cc 00F0B180 beq .L1180 +3620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15596 .loc 1 3620 7 is_stmt 1 view .LVU4513 +3620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15597 .loc 1 3620 10 is_stmt 0 view .LVU4514 + 15598 00d0 002D cmp r5, #0 + 15599 00d2 18BF it ne + 15600 00d4 002A cmpne r2, #0 + 15601 00d6 00F0AE80 beq .L1181 +3620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15602 .loc 1 3620 52 discriminator 1 view .LVU4515 + ARM GAS /tmp/ccGFzgX3.s page 480 + + + 15603 00da 002E cmp r6, #0 + 15604 00dc 00F0AD80 beq .L1182 +3626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 15605 .loc 1 3626 9 is_stmt 1 view .LVU4516 + 15606 00e0 0223 movs r3, #2 + 15607 00e2 84F83E30 strb r3, [r4, #62] +3627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 15608 .loc 1 3627 9 view .LVU4517 + 15609 00e6 84F83F30 strb r3, [r4, #63] +3628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 15610 .loc 1 3628 9 view .LVU4518 + 15611 00ea 84F84430 strb r3, [r4, #68] +3629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15612 .loc 1 3629 9 view .LVU4519 + 15613 00ee 84F84530 strb r3, [r4, #69] +3620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15614 .loc 1 3620 10 is_stmt 0 view .LVU4520 + 15615 00f2 ADE7 b .L1166 + 15616 .LVL1146: + 15617 .L1190: +3583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + 15618 .loc 1 3583 5 is_stmt 1 view .LVU4521 +3583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + 15619 .loc 1 3583 8 is_stmt 0 view .LVU4522 + 15620 00f4 BEF1020F cmp lr, #2 + 15621 00f8 18BF it ne + 15622 00fa 022B cmpne r3, #2 + 15623 00fc 00F08D80 beq .L1174 +3588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + 15624 .loc 1 3588 10 is_stmt 1 view .LVU4523 +3588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + 15625 .loc 1 3588 13 is_stmt 0 view .LVU4524 + 15626 0100 012B cmp r3, #1 + 15627 0102 08BF it eq + 15628 0104 BEF1010F cmpeq lr, #1 + 15629 0108 40F08980 bne .L1175 +3591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15630 .loc 1 3591 7 is_stmt 1 view .LVU4525 +3591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15631 .loc 1 3591 10 is_stmt 0 view .LVU4526 + 15632 010c 002E cmp r6, #0 + 15633 010e 18BF it ne + 15634 0110 002D cmpne r5, #0 + 15635 0112 00F08680 beq .L1176 +3597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 15636 .loc 1 3597 9 is_stmt 1 view .LVU4527 + 15637 0116 0223 movs r3, #2 + 15638 .LVL1147: +3597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 15639 .loc 1 3597 9 is_stmt 0 view .LVU4528 + 15640 0118 84F83F30 strb r3, [r4, #63] +3598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15641 .loc 1 3598 9 is_stmt 1 view .LVU4529 + 15642 011c 84F84530 strb r3, [r4, #69] + 15643 0120 96E7 b .L1166 + 15644 .LVL1148: + 15645 .L1168: + ARM GAS /tmp/ccGFzgX3.s page 481 + + +3643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 15646 .loc 1 3643 7 view .LVU4530 +3643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 15647 .loc 1 3643 17 is_stmt 0 view .LVU4531 + 15648 0122 636A ldr r3, [r4, #36] +3643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 15649 .loc 1 3643 52 view .LVU4532 + 15650 0124 4649 ldr r1, .L1194 + 15651 0126 D963 str r1, [r3, #60] +3644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15652 .loc 1 3644 7 is_stmt 1 view .LVU4533 +3644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15653 .loc 1 3644 17 is_stmt 0 view .LVU4534 + 15654 0128 636A ldr r3, [r4, #36] +3644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15655 .loc 1 3644 56 view .LVU4535 + 15656 012a 4649 ldr r1, .L1194+4 + 15657 012c 1964 str r1, [r3, #64] +3647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15658 .loc 1 3647 7 is_stmt 1 view .LVU4536 +3647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15659 .loc 1 3647 17 is_stmt 0 view .LVU4537 + 15660 012e 636A ldr r3, [r4, #36] +3647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15661 .loc 1 3647 53 view .LVU4538 + 15662 0130 4549 ldr r1, .L1194+8 + 15663 0132 D964 str r1, [r3, #76] +3650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15664 .loc 1 3650 7 is_stmt 1 view .LVU4539 +3650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15665 .loc 1 3650 71 is_stmt 0 view .LVU4540 + 15666 0134 2168 ldr r1, [r4] +3650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15667 .loc 1 3650 11 view .LVU4541 + 15668 0136 3346 mov r3, r6 + 15669 0138 3431 adds r1, r1, #52 + 15670 013a 606A ldr r0, [r4, #36] + 15671 .LVL1149: +3650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15672 .loc 1 3650 11 view .LVU4542 + 15673 013c FFF7FEFF bl HAL_DMA_Start_IT + 15674 .LVL1150: +3650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15675 .loc 1 3650 10 discriminator 1 view .LVU4543 + 15676 0140 0546 mov r5, r0 + 15677 .LVL1151: +3650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15678 .loc 1 3650 10 discriminator 1 view .LVU4544 + 15679 0142 08B1 cbz r0, .L1191 +3654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15680 .loc 1 3654 16 view .LVU4545 + 15681 0144 0125 movs r5, #1 + 15682 0146 64E0 b .L1165 + 15683 .L1191: +3657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15684 .loc 1 3657 7 is_stmt 1 view .LVU4546 + 15685 0148 2268 ldr r2, [r4] + ARM GAS /tmp/ccGFzgX3.s page 482 + + + 15686 014a D368 ldr r3, [r2, #12] + 15687 014c 43F40073 orr r3, r3, #512 + 15688 0150 D360 str r3, [r2, #12] +3660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15689 .loc 1 3660 7 view .LVU4547 + 15690 0152 0122 movs r2, #1 + 15691 0154 0021 movs r1, #0 + 15692 0156 2068 ldr r0, [r4] + 15693 0158 FFF7FEFF bl TIM_CCxChannelCmd + 15694 .LVL1152: +3663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15695 .loc 1 3663 7 view .LVU4548 + 15696 015c 2268 ldr r2, [r4] + 15697 015e 1368 ldr r3, [r2] + 15698 0160 43F00103 orr r3, r3, #1 + 15699 0164 1360 str r3, [r2] +3665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15700 .loc 1 3665 7 view .LVU4549 + 15701 0166 54E0 b .L1165 + 15702 .LVL1153: + 15703 .L1169: +3671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 15704 .loc 1 3671 7 view .LVU4550 +3671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 15705 .loc 1 3671 17 is_stmt 0 view .LVU4551 + 15706 0168 A36A ldr r3, [r4, #40] +3671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 15707 .loc 1 3671 52 view .LVU4552 + 15708 016a 354A ldr r2, .L1194 + 15709 .LVL1154: +3671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 15710 .loc 1 3671 52 view .LVU4553 + 15711 016c DA63 str r2, [r3, #60] +3672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15712 .loc 1 3672 7 is_stmt 1 view .LVU4554 +3672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15713 .loc 1 3672 17 is_stmt 0 view .LVU4555 + 15714 016e A36A ldr r3, [r4, #40] +3672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15715 .loc 1 3672 56 view .LVU4556 + 15716 0170 344A ldr r2, .L1194+4 + 15717 0172 1A64 str r2, [r3, #64] +3675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ + 15718 .loc 1 3675 7 is_stmt 1 view .LVU4557 +3675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ + 15719 .loc 1 3675 17 is_stmt 0 view .LVU4558 + 15720 0174 A36A ldr r3, [r4, #40] +3675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the DMA stream */ + 15721 .loc 1 3675 53 view .LVU4559 + 15722 0176 344A ldr r2, .L1194+8 + 15723 0178 DA64 str r2, [r3, #76] +3677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15724 .loc 1 3677 7 is_stmt 1 view .LVU4560 +3677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15725 .loc 1 3677 71 is_stmt 0 view .LVU4561 + 15726 017a 2168 ldr r1, [r4] +3677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + ARM GAS /tmp/ccGFzgX3.s page 483 + + + 15727 .loc 1 3677 11 view .LVU4562 + 15728 017c 3346 mov r3, r6 + 15729 017e 2A46 mov r2, r5 + 15730 0180 3831 adds r1, r1, #56 + 15731 0182 A06A ldr r0, [r4, #40] + 15732 .LVL1155: +3677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15733 .loc 1 3677 11 view .LVU4563 + 15734 0184 FFF7FEFF bl HAL_DMA_Start_IT + 15735 .LVL1156: +3677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15736 .loc 1 3677 10 discriminator 1 view .LVU4564 + 15737 0188 0546 mov r5, r0 + 15738 .LVL1157: +3677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15739 .loc 1 3677 10 discriminator 1 view .LVU4565 + 15740 018a 08B1 cbz r0, .L1192 +3681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15741 .loc 1 3681 16 view .LVU4566 + 15742 018c 0125 movs r5, #1 + 15743 018e 40E0 b .L1165 + 15744 .L1192: +3684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15745 .loc 1 3684 7 is_stmt 1 view .LVU4567 + 15746 0190 2268 ldr r2, [r4] + 15747 0192 D368 ldr r3, [r2, #12] + 15748 0194 43F48063 orr r3, r3, #1024 + 15749 0198 D360 str r3, [r2, #12] +3687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15750 .loc 1 3687 7 view .LVU4568 + 15751 019a 0122 movs r2, #1 + 15752 019c 0421 movs r1, #4 + 15753 019e 2068 ldr r0, [r4] + 15754 01a0 FFF7FEFF bl TIM_CCxChannelCmd + 15755 .LVL1158: +3690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15756 .loc 1 3690 7 view .LVU4569 + 15757 01a4 2268 ldr r2, [r4] + 15758 01a6 1368 ldr r3, [r2] + 15759 01a8 43F00103 orr r3, r3, #1 + 15760 01ac 1360 str r3, [r2] +3692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15761 .loc 1 3692 7 view .LVU4570 + 15762 01ae 30E0 b .L1165 + 15763 .LVL1159: + 15764 .L1189: +3713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 15765 .loc 1 3713 7 view .LVU4571 +3713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 15766 .loc 1 3713 17 is_stmt 0 view .LVU4572 + 15767 01b0 A36A ldr r3, [r4, #40] +3713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 15768 .loc 1 3713 52 view .LVU4573 + 15769 01b2 234A ldr r2, .L1194 + 15770 01b4 DA63 str r2, [r3, #60] +3714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15771 .loc 1 3714 7 is_stmt 1 view .LVU4574 + ARM GAS /tmp/ccGFzgX3.s page 484 + + +3714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15772 .loc 1 3714 17 is_stmt 0 view .LVU4575 + 15773 01b6 A36A ldr r3, [r4, #40] +3714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15774 .loc 1 3714 56 view .LVU4576 + 15775 01b8 224A ldr r2, .L1194+4 + 15776 01ba 1A64 str r2, [r3, #64] +3717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15777 .loc 1 3717 7 is_stmt 1 view .LVU4577 +3717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15778 .loc 1 3717 17 is_stmt 0 view .LVU4578 + 15779 01bc A36A ldr r3, [r4, #40] +3717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15780 .loc 1 3717 53 view .LVU4579 + 15781 01be 224A ldr r2, .L1194+8 + 15782 01c0 DA64 str r2, [r3, #76] +3720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15783 .loc 1 3720 7 is_stmt 1 view .LVU4580 +3720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15784 .loc 1 3720 71 is_stmt 0 view .LVU4581 + 15785 01c2 2168 ldr r1, [r4] +3720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15786 .loc 1 3720 11 view .LVU4582 + 15787 01c4 3346 mov r3, r6 + 15788 01c6 2A46 mov r2, r5 + 15789 01c8 3831 adds r1, r1, #56 + 15790 01ca A06A ldr r0, [r4, #40] + 15791 01cc FFF7FEFF bl HAL_DMA_Start_IT + 15792 .LVL1160: +3720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15793 .loc 1 3720 10 discriminator 1 view .LVU4583 + 15794 01d0 0546 mov r5, r0 + 15795 .LVL1161: +3720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** Length) != HAL_OK) + 15796 .loc 1 3720 10 discriminator 1 view .LVU4584 + 15797 01d2 08B1 cbz r0, .L1193 +3724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15798 .loc 1 3724 16 view .LVU4585 + 15799 01d4 0125 movs r5, #1 + 15800 01d6 1CE0 b .L1165 + 15801 .L1193: +3728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Enable the TIM Input Capture DMA request */ + 15802 .loc 1 3728 7 is_stmt 1 view .LVU4586 + 15803 01d8 2268 ldr r2, [r4] + 15804 01da D368 ldr r3, [r2, #12] + 15805 01dc 43F40073 orr r3, r3, #512 + 15806 01e0 D360 str r3, [r2, #12] +3730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15807 .loc 1 3730 7 view .LVU4587 + 15808 01e2 2268 ldr r2, [r4] + 15809 01e4 D368 ldr r3, [r2, #12] + 15810 01e6 43F48063 orr r3, r3, #1024 + 15811 01ea D360 str r3, [r2, #12] +3733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 15812 .loc 1 3733 7 view .LVU4588 + 15813 01ec 0122 movs r2, #1 + 15814 01ee 0021 movs r1, #0 + ARM GAS /tmp/ccGFzgX3.s page 485 + + + 15815 01f0 2068 ldr r0, [r4] + 15816 01f2 FFF7FEFF bl TIM_CCxChannelCmd + 15817 .LVL1162: +3734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15818 .loc 1 3734 7 view .LVU4589 + 15819 01f6 0122 movs r2, #1 + 15820 01f8 0421 movs r1, #4 + 15821 01fa 2068 ldr r0, [r4] + 15822 01fc FFF7FEFF bl TIM_CCxChannelCmd + 15823 .LVL1163: +3737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15824 .loc 1 3737 7 view .LVU4590 + 15825 0200 2268 ldr r2, [r4] + 15826 0202 1368 ldr r3, [r2] + 15827 0204 43F00103 orr r3, r3, #1 + 15828 0208 1360 str r3, [r2] +3739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15829 .loc 1 3739 7 view .LVU4591 + 15830 020a 02E0 b .L1165 + 15831 .LVL1164: + 15832 .L1171: +3561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15833 .loc 1 3561 14 is_stmt 0 view .LVU4592 + 15834 020c 0225 movs r5, #2 + 15835 .LVL1165: +3561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15836 .loc 1 3561 14 view .LVU4593 + 15837 020e 00E0 b .L1165 + 15838 .LVL1166: + 15839 .L1172: +3578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15840 .loc 1 3578 14 view .LVU4594 + 15841 0210 0125 movs r5, #1 + 15842 .LVL1167: + 15843 .L1165: +3745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15844 .loc 1 3745 1 view .LVU4595 + 15845 0212 2846 mov r0, r5 + 15846 0214 F8BD pop {r3, r4, r5, r6, r7, pc} + 15847 .LVL1168: + 15848 .L1173: +3568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15849 .loc 1 3568 16 view .LVU4596 + 15850 0216 0125 movs r5, #1 + 15851 .LVL1169: +3568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15852 .loc 1 3568 16 view .LVU4597 + 15853 0218 FBE7 b .L1165 + 15854 .LVL1170: + 15855 .L1174: +3586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15856 .loc 1 3586 14 view .LVU4598 + 15857 021a 0225 movs r5, #2 + 15858 .LVL1171: +3586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15859 .loc 1 3586 14 view .LVU4599 + 15860 021c F9E7 b .L1165 + ARM GAS /tmp/ccGFzgX3.s page 486 + + + 15861 .LVL1172: + 15862 .L1175: +3603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15863 .loc 1 3603 14 view .LVU4600 + 15864 021e 0125 movs r5, #1 + 15865 .LVL1173: +3603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15866 .loc 1 3603 14 view .LVU4601 + 15867 0220 F7E7 b .L1165 + 15868 .LVL1174: + 15869 .L1176: +3593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15870 .loc 1 3593 16 view .LVU4602 + 15871 0222 0125 movs r5, #1 + 15872 .LVL1175: +3593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15873 .loc 1 3593 16 view .LVU4603 + 15874 0224 F5E7 b .L1165 + 15875 .LVL1176: + 15876 .L1177: +3613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15877 .loc 1 3613 14 view .LVU4604 + 15878 0226 0225 movs r5, #2 + 15879 .LVL1177: +3613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15880 .loc 1 3613 14 view .LVU4605 + 15881 0228 F3E7 b .L1165 + 15882 .LVL1178: + 15883 .L1178: +3613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15884 .loc 1 3613 14 view .LVU4606 + 15885 022a 0225 movs r5, #2 + 15886 .LVL1179: +3613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15887 .loc 1 3613 14 view .LVU4607 + 15888 022c F1E7 b .L1165 + 15889 .LVL1180: + 15890 .L1179: +3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15891 .loc 1 3634 14 view .LVU4608 + 15892 022e 0125 movs r5, #1 + 15893 .LVL1181: +3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15894 .loc 1 3634 14 view .LVU4609 + 15895 0230 EFE7 b .L1165 + 15896 .LVL1182: + 15897 .L1180: +3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15898 .loc 1 3634 14 view .LVU4610 + 15899 0232 0125 movs r5, #1 + 15900 .LVL1183: +3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15901 .loc 1 3634 14 view .LVU4611 + 15902 0234 EDE7 b .L1165 + 15903 .LVL1184: + 15904 .L1181: +3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + ARM GAS /tmp/ccGFzgX3.s page 487 + + + 15905 .loc 1 3622 16 view .LVU4612 + 15906 0236 0125 movs r5, #1 + 15907 .LVL1185: +3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15908 .loc 1 3622 16 view .LVU4613 + 15909 0238 EBE7 b .L1165 + 15910 .LVL1186: + 15911 .L1182: +3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15912 .loc 1 3622 16 view .LVU4614 + 15913 023a 0125 movs r5, #1 + 15914 .LVL1187: +3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15915 .loc 1 3622 16 view .LVU4615 + 15916 023c E9E7 b .L1165 + 15917 .L1195: + 15918 023e 00BF .align 2 + 15919 .L1194: + 15920 0240 00000000 .word TIM_DMACaptureCplt + 15921 0244 00000000 .word TIM_DMACaptureHalfCplt + 15922 0248 00000000 .word TIM_DMAError + 15923 .cfi_endproc + 15924 .LFE197: + 15926 .section .text.HAL_TIM_Encoder_Stop_DMA,"ax",%progbits + 15927 .align 1 + 15928 .global HAL_TIM_Encoder_Stop_DMA + 15929 .syntax unified + 15930 .thumb + 15931 .thumb_func + 15933 HAL_TIM_Encoder_Stop_DMA: + 15934 .LVL1188: + 15935 .LFB198: +3758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 15936 .loc 1 3758 1 is_stmt 1 view -0 + 15937 .cfi_startproc + 15938 @ args = 0, pretend = 0, frame = 0 + 15939 @ frame_needed = 0, uses_anonymous_args = 0 +3758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** /* Check the parameters */ + 15940 .loc 1 3758 1 is_stmt 0 view .LVU4617 + 15941 0000 38B5 push {r3, r4, r5, lr} + 15942 .LCFI113: + 15943 .cfi_def_cfa_offset 16 + 15944 .cfi_offset 3, -16 + 15945 .cfi_offset 4, -12 + 15946 .cfi_offset 5, -8 + 15947 .cfi_offset 14, -4 + 15948 0002 0446 mov r4, r0 +3760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15949 .loc 1 3760 3 is_stmt 1 view .LVU4618 +3764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15950 .loc 1 3764 3 view .LVU4619 +3764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15951 .loc 1 3764 6 is_stmt 0 view .LVU4620 + 15952 0004 0D46 mov r5, r1 + 15953 0006 0029 cmp r1, #0 + 15954 0008 3BD0 beq .L1215 +3772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + ARM GAS /tmp/ccGFzgX3.s page 488 + + + 15955 .loc 1 3772 8 is_stmt 1 view .LVU4621 +3772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 15956 .loc 1 3772 11 is_stmt 0 view .LVU4622 + 15957 000a 0429 cmp r1, #4 + 15958 000c 47D0 beq .L1216 +3782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 15959 .loc 1 3782 5 is_stmt 1 view .LVU4623 + 15960 000e 0022 movs r2, #0 + 15961 0010 1146 mov r1, r2 + 15962 .LVL1189: +3782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 15963 .loc 1 3782 5 is_stmt 0 view .LVU4624 + 15964 0012 0068 ldr r0, [r0] + 15965 .LVL1190: +3782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 15966 .loc 1 3782 5 view .LVU4625 + 15967 0014 FFF7FEFF bl TIM_CCxChannelCmd + 15968 .LVL1191: +3783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15969 .loc 1 3783 5 is_stmt 1 view .LVU4626 + 15970 0018 0022 movs r2, #0 + 15971 001a 0421 movs r1, #4 + 15972 001c 2068 ldr r0, [r4] + 15973 001e FFF7FEFF bl TIM_CCxChannelCmd + 15974 .LVL1192: +3786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + 15975 .loc 1 3786 5 view .LVU4627 + 15976 0022 2268 ldr r2, [r4] + 15977 0024 D368 ldr r3, [r2, #12] + 15978 0026 23F40073 bic r3, r3, #512 + 15979 002a D360 str r3, [r2, #12] +3787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + 15980 .loc 1 3787 5 view .LVU4628 + 15981 002c 2268 ldr r2, [r4] + 15982 002e D368 ldr r3, [r2, #12] + 15983 0030 23F48063 bic r3, r3, #1024 + 15984 0034 D360 str r3, [r2, #12] +3788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + 15985 .loc 1 3788 5 view .LVU4629 +3788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + 15986 .loc 1 3788 11 is_stmt 0 view .LVU4630 + 15987 0036 606A ldr r0, [r4, #36] + 15988 0038 FFF7FEFF bl HAL_DMA_Abort_IT + 15989 .LVL1193: +3789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15990 .loc 1 3789 5 is_stmt 1 view .LVU4631 +3789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 15991 .loc 1 3789 11 is_stmt 0 view .LVU4632 + 15992 003c A06A ldr r0, [r4, #40] + 15993 003e FFF7FEFF bl HAL_DMA_Abort_IT + 15994 .LVL1194: + 15995 .L1198: +3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15996 .loc 1 3793 3 is_stmt 1 view .LVU4633 +3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 15997 .loc 1 3793 3 view .LVU4634 + 15998 0042 2368 ldr r3, [r4] + ARM GAS /tmp/ccGFzgX3.s page 489 + + + 15999 0044 196A ldr r1, [r3, #32] + 16000 0046 41F21112 movw r2, #4369 + 16001 004a 1142 tst r1, r2 + 16002 004c 08D1 bne .L1200 +3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 16003 .loc 1 3793 3 discriminator 1 view .LVU4635 + 16004 004e 196A ldr r1, [r3, #32] + 16005 0050 40F24442 movw r2, #1092 + 16006 0054 1142 tst r1, r2 + 16007 0056 03D1 bne .L1200 +3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 16008 .loc 1 3793 3 discriminator 3 view .LVU4636 + 16009 0058 1A68 ldr r2, [r3] + 16010 005a 22F00102 bic r2, r2, #1 + 16011 005e 1A60 str r2, [r3] + 16012 .L1200: +3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 16013 .loc 1 3793 3 discriminator 5 view .LVU4637 +3796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 16014 .loc 1 3796 3 view .LVU4638 +3796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** { + 16015 .loc 1 3796 6 is_stmt 0 view .LVU4639 + 16016 0060 042D cmp r5, #4 + 16017 0062 18BF it ne + 16018 0064 002D cmpne r5, #0 + 16019 0066 54D1 bne .L1201 +3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 16020 .loc 1 3798 5 is_stmt 1 view .LVU4640 + 16021 0068 102D cmp r5, #16 + 16022 006a 44D8 bhi .L1202 + 16023 006c DFE805F0 tbb [pc, r5] + 16024 .L1204: + 16025 0070 25 .byte (.L1208-.L1204)/2 + 16026 0071 43 .byte (.L1202-.L1204)/2 + 16027 0072 43 .byte (.L1202-.L1204)/2 + 16028 0073 43 .byte (.L1202-.L1204)/2 + 16029 0074 2C .byte (.L1207-.L1204)/2 + 16030 0075 43 .byte (.L1202-.L1204)/2 + 16031 0076 43 .byte (.L1202-.L1204)/2 + 16032 0077 43 .byte (.L1202-.L1204)/2 + 16033 0078 37 .byte (.L1206-.L1204)/2 + 16034 0079 43 .byte (.L1202-.L1204)/2 + 16035 007a 43 .byte (.L1202-.L1204)/2 + 16036 007b 43 .byte (.L1202-.L1204)/2 + 16037 007c 3B .byte (.L1205-.L1204)/2 + 16038 007d 43 .byte (.L1202-.L1204)/2 + 16039 007e 43 .byte (.L1202-.L1204)/2 + 16040 007f 43 .byte (.L1202-.L1204)/2 + 16041 0080 3F .byte (.L1203-.L1204)/2 + 16042 .LVL1195: + 16043 0081 00 .p2align 1 + 16044 .L1215: +3766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 16045 .loc 1 3766 5 view .LVU4641 + 16046 0082 0022 movs r2, #0 + 16047 0084 1146 mov r1, r2 + 16048 .LVL1196: + ARM GAS /tmp/ccGFzgX3.s page 490 + + +3766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 16049 .loc 1 3766 5 is_stmt 0 view .LVU4642 + 16050 0086 0068 ldr r0, [r0] + 16051 .LVL1197: +3766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 16052 .loc 1 3766 5 view .LVU4643 + 16053 0088 FFF7FEFF bl TIM_CCxChannelCmd + 16054 .LVL1198: +3769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + 16055 .loc 1 3769 5 is_stmt 1 view .LVU4644 + 16056 008c 2268 ldr r2, [r4] + 16057 008e D368 ldr r3, [r2, #12] + 16058 0090 23F40073 bic r3, r3, #512 + 16059 0094 D360 str r3, [r2, #12] +3770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 16060 .loc 1 3770 5 view .LVU4645 +3770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 16061 .loc 1 3770 11 is_stmt 0 view .LVU4646 + 16062 0096 606A ldr r0, [r4, #36] + 16063 0098 FFF7FEFF bl HAL_DMA_Abort_IT + 16064 .LVL1199: + 16065 009c D1E7 b .L1198 + 16066 .LVL1200: + 16067 .L1216: +3774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 16068 .loc 1 3774 5 is_stmt 1 view .LVU4647 + 16069 009e 0022 movs r2, #0 + 16070 00a0 0421 movs r1, #4 + 16071 .LVL1201: +3774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 16072 .loc 1 3774 5 is_stmt 0 view .LVU4648 + 16073 00a2 0068 ldr r0, [r0] + 16074 .LVL1202: +3774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 16075 .loc 1 3774 5 view .LVU4649 + 16076 00a4 FFF7FEFF bl TIM_CCxChannelCmd + 16077 .LVL1203: +3777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + 16078 .loc 1 3777 5 is_stmt 1 view .LVU4650 + 16079 00a8 2268 ldr r2, [r4] + 16080 00aa D368 ldr r3, [r2, #12] + 16081 00ac 23F48063 bic r3, r3, #1024 + 16082 00b0 D360 str r3, [r2, #12] +3778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 16083 .loc 1 3778 5 view .LVU4651 +3778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 16084 .loc 1 3778 11 is_stmt 0 view .LVU4652 + 16085 00b2 A06A ldr r0, [r4, #40] + 16086 00b4 FFF7FEFF bl HAL_DMA_Abort_IT + 16087 .LVL1204: + 16088 00b8 C3E7 b .L1198 + 16089 .L1208: +3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 16090 .loc 1 3798 5 discriminator 1 view .LVU4653 + 16091 00ba 0123 movs r3, #1 + 16092 00bc 84F83E30 strb r3, [r4, #62] +3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + ARM GAS /tmp/ccGFzgX3.s page 491 + + + 16093 .loc 1 3799 5 is_stmt 1 view .LVU4654 + 16094 .L1209: +3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 16095 .loc 1 3799 5 is_stmt 0 discriminator 1 view .LVU4655 + 16096 00c0 0123 movs r3, #1 + 16097 00c2 84F84430 strb r3, [r4, #68] + 16098 00c6 2DE0 b .L1211 + 16099 .L1207: +3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 16100 .loc 1 3798 5 discriminator 3 view .LVU4656 + 16101 00c8 0123 movs r3, #1 + 16102 00ca 84F83F30 strb r3, [r4, #63] +3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 16103 .loc 1 3799 5 is_stmt 1 view .LVU4657 + 16104 .L1210: +3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 16105 .loc 1 3799 5 is_stmt 0 discriminator 2 view .LVU4658 + 16106 00ce 042D cmp r5, #4 + 16107 00d0 17D0 beq .L1217 +3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 16108 .loc 1 3799 5 discriminator 4 view .LVU4659 + 16109 00d2 082D cmp r5, #8 + 16110 00d4 19D0 beq .L1218 +3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 16111 .loc 1 3799 5 discriminator 7 view .LVU4660 + 16112 00d6 0123 movs r3, #1 + 16113 00d8 84F84730 strb r3, [r4, #71] + 16114 00dc 22E0 b .L1211 + 16115 .L1206: +3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 16116 .loc 1 3798 5 discriminator 6 view .LVU4661 + 16117 00de 0123 movs r3, #1 + 16118 00e0 84F84030 strb r3, [r4, #64] +3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 16119 .loc 1 3799 5 is_stmt 1 view .LVU4662 + 16120 00e4 F3E7 b .L1210 + 16121 .L1205: +3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 16122 .loc 1 3798 5 is_stmt 0 discriminator 9 view .LVU4663 + 16123 00e6 0123 movs r3, #1 + 16124 00e8 84F84130 strb r3, [r4, #65] +3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 16125 .loc 1 3799 5 is_stmt 1 view .LVU4664 + 16126 00ec EFE7 b .L1210 + 16127 .L1203: +3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 16128 .loc 1 3798 5 is_stmt 0 discriminator 12 view .LVU4665 + 16129 00ee 0123 movs r3, #1 + 16130 00f0 84F84230 strb r3, [r4, #66] +3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 16131 .loc 1 3799 5 is_stmt 1 view .LVU4666 + 16132 00f4 EBE7 b .L1210 + 16133 .L1202: +3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 16134 .loc 1 3798 5 is_stmt 0 discriminator 13 view .LVU4667 + 16135 00f6 0123 movs r3, #1 + 16136 00f8 84F84330 strb r3, [r4, #67] + ARM GAS /tmp/ccGFzgX3.s page 492 + + +3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 16137 .loc 1 3799 5 is_stmt 1 view .LVU4668 + 16138 00fc 002D cmp r5, #0 + 16139 00fe E6D1 bne .L1210 + 16140 0100 DEE7 b .L1209 + 16141 .L1217: +3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 16142 .loc 1 3799 5 is_stmt 0 discriminator 3 view .LVU4669 + 16143 0102 0123 movs r3, #1 + 16144 0104 84F84530 strb r3, [r4, #69] + 16145 0108 0CE0 b .L1211 + 16146 .L1218: +3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 16147 .loc 1 3799 5 discriminator 6 view .LVU4670 + 16148 010a 0123 movs r3, #1 + 16149 010c 84F84630 strb r3, [r4, #70] + 16150 0110 08E0 b .L1211 + 16151 .L1201: +3803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 16152 .loc 1 3803 5 is_stmt 1 view .LVU4671 + 16153 0112 0123 movs r3, #1 + 16154 0114 84F83E30 strb r3, [r4, #62] +3804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 16155 .loc 1 3804 5 view .LVU4672 + 16156 0118 84F83F30 strb r3, [r4, #63] +3805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 16157 .loc 1 3805 5 view .LVU4673 + 16158 011c 84F84430 strb r3, [r4, #68] +3806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 16159 .loc 1 3806 5 view .LVU4674 + 16160 0120 84F84530 strb r3, [r4, #69] + 16161 .L1211: +3810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** } + 16162 .loc 1 3810 3 view .LVU4675 +3811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 16163 .loc 1 3811 1 is_stmt 0 view .LVU4676 + 16164 0124 0020 movs r0, #0 + 16165 0126 38BD pop {r3, r4, r5, pc} +3811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c **** + 16166 .loc 1 3811 1 view .LVU4677 + 16167 .cfi_endproc + 16168 .LFE198: + 16170 .text + 16171 .Letext0: + 16172 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 16173 .file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 16174 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + 16175 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 16176 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h" + 16177 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h" + 16178 .file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h" + ARM GAS /tmp/ccGFzgX3.s page 493 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_tim.c + /tmp/ccGFzgX3.s:20 .text.TIM_OC1_SetConfig:00000000 $t + /tmp/ccGFzgX3.s:25 .text.TIM_OC1_SetConfig:00000000 TIM_OC1_SetConfig + /tmp/ccGFzgX3.s:163 .text.TIM_OC1_SetConfig:0000005c $d + /tmp/ccGFzgX3.s:170 .text.TIM_OC3_SetConfig:00000000 $t + /tmp/ccGFzgX3.s:175 .text.TIM_OC3_SetConfig:00000000 TIM_OC3_SetConfig + /tmp/ccGFzgX3.s:313 .text.TIM_OC3_SetConfig:00000064 $d + /tmp/ccGFzgX3.s:320 .text.TIM_OC4_SetConfig:00000000 $t + /tmp/ccGFzgX3.s:325 .text.TIM_OC4_SetConfig:00000000 TIM_OC4_SetConfig + /tmp/ccGFzgX3.s:432 .text.TIM_OC4_SetConfig:00000048 $d + /tmp/ccGFzgX3.s:439 .text.TIM_OC5_SetConfig:00000000 $t + /tmp/ccGFzgX3.s:444 .text.TIM_OC5_SetConfig:00000000 TIM_OC5_SetConfig + /tmp/ccGFzgX3.s:549 .text.TIM_OC5_SetConfig:00000048 $d + /tmp/ccGFzgX3.s:556 .text.TIM_OC6_SetConfig:00000000 $t + /tmp/ccGFzgX3.s:561 .text.TIM_OC6_SetConfig:00000000 TIM_OC6_SetConfig + /tmp/ccGFzgX3.s:666 .text.TIM_OC6_SetConfig:00000048 $d + /tmp/ccGFzgX3.s:673 .text.TIM_TI1_ConfigInputStage:00000000 $t + /tmp/ccGFzgX3.s:678 .text.TIM_TI1_ConfigInputStage:00000000 TIM_TI1_ConfigInputStage + /tmp/ccGFzgX3.s:739 .text.TIM_TI2_SetConfig:00000000 $t + /tmp/ccGFzgX3.s:744 .text.TIM_TI2_SetConfig:00000000 TIM_TI2_SetConfig + /tmp/ccGFzgX3.s:825 .text.TIM_TI2_ConfigInputStage:00000000 $t + /tmp/ccGFzgX3.s:830 .text.TIM_TI2_ConfigInputStage:00000000 TIM_TI2_ConfigInputStage + /tmp/ccGFzgX3.s:891 .text.TIM_TI3_SetConfig:00000000 $t + /tmp/ccGFzgX3.s:896 .text.TIM_TI3_SetConfig:00000000 TIM_TI3_SetConfig + /tmp/ccGFzgX3.s:977 .text.TIM_TI4_SetConfig:00000000 $t + /tmp/ccGFzgX3.s:982 .text.TIM_TI4_SetConfig:00000000 TIM_TI4_SetConfig + /tmp/ccGFzgX3.s:1063 .text.TIM_ITRx_SetConfig:00000000 $t + /tmp/ccGFzgX3.s:1068 .text.TIM_ITRx_SetConfig:00000000 TIM_ITRx_SetConfig + /tmp/ccGFzgX3.s:1101 .text.HAL_TIM_Base_MspInit:00000000 $t + /tmp/ccGFzgX3.s:1107 .text.HAL_TIM_Base_MspInit:00000000 HAL_TIM_Base_MspInit + /tmp/ccGFzgX3.s:1122 .text.HAL_TIM_Base_MspDeInit:00000000 $t + /tmp/ccGFzgX3.s:1128 .text.HAL_TIM_Base_MspDeInit:00000000 HAL_TIM_Base_MspDeInit + /tmp/ccGFzgX3.s:1143 .text.HAL_TIM_Base_DeInit:00000000 $t + /tmp/ccGFzgX3.s:1149 .text.HAL_TIM_Base_DeInit:00000000 HAL_TIM_Base_DeInit + /tmp/ccGFzgX3.s:1235 .text.HAL_TIM_Base_Start:00000000 $t + /tmp/ccGFzgX3.s:1241 .text.HAL_TIM_Base_Start:00000000 HAL_TIM_Base_Start + /tmp/ccGFzgX3.s:1347 .text.HAL_TIM_Base_Start:00000080 $d + /tmp/ccGFzgX3.s:1353 .text.HAL_TIM_Base_Stop:00000000 $t + /tmp/ccGFzgX3.s:1359 .text.HAL_TIM_Base_Stop:00000000 HAL_TIM_Base_Stop + /tmp/ccGFzgX3.s:1400 .text.HAL_TIM_Base_Start_IT:00000000 $t + /tmp/ccGFzgX3.s:1406 .text.HAL_TIM_Base_Start_IT:00000000 HAL_TIM_Base_Start_IT + /tmp/ccGFzgX3.s:1517 .text.HAL_TIM_Base_Start_IT:00000088 $d + /tmp/ccGFzgX3.s:1523 .text.HAL_TIM_Base_Stop_IT:00000000 $t + /tmp/ccGFzgX3.s:1529 .text.HAL_TIM_Base_Stop_IT:00000000 HAL_TIM_Base_Stop_IT + /tmp/ccGFzgX3.s:1575 .text.HAL_TIM_Base_Start_DMA:00000000 $t + /tmp/ccGFzgX3.s:1581 .text.HAL_TIM_Base_Start_DMA:00000000 HAL_TIM_Base_Start_DMA + /tmp/ccGFzgX3.s:1743 .text.HAL_TIM_Base_Start_DMA:000000c8 $d + /tmp/ccGFzgX3.s:3832 .text.TIM_DMAPeriodElapsedCplt:00000000 TIM_DMAPeriodElapsedCplt + /tmp/ccGFzgX3.s:3896 .text.TIM_DMAPeriodElapsedHalfCplt:00000000 TIM_DMAPeriodElapsedHalfCplt + /tmp/ccGFzgX3.s:4915 .text.TIM_DMAError:00000000 TIM_DMAError + /tmp/ccGFzgX3.s:1752 .text.HAL_TIM_Base_Stop_DMA:00000000 $t + /tmp/ccGFzgX3.s:1758 .text.HAL_TIM_Base_Stop_DMA:00000000 HAL_TIM_Base_Stop_DMA + /tmp/ccGFzgX3.s:1816 .text.HAL_TIM_OC_MspInit:00000000 $t + /tmp/ccGFzgX3.s:1822 .text.HAL_TIM_OC_MspInit:00000000 HAL_TIM_OC_MspInit + /tmp/ccGFzgX3.s:1837 .text.HAL_TIM_OC_MspDeInit:00000000 $t + /tmp/ccGFzgX3.s:1843 .text.HAL_TIM_OC_MspDeInit:00000000 HAL_TIM_OC_MspDeInit + ARM GAS /tmp/ccGFzgX3.s page 494 + + + /tmp/ccGFzgX3.s:1858 .text.HAL_TIM_OC_DeInit:00000000 $t + /tmp/ccGFzgX3.s:1864 .text.HAL_TIM_OC_DeInit:00000000 HAL_TIM_OC_DeInit + /tmp/ccGFzgX3.s:1950 .text.HAL_TIM_PWM_MspInit:00000000 $t + /tmp/ccGFzgX3.s:1956 .text.HAL_TIM_PWM_MspInit:00000000 HAL_TIM_PWM_MspInit + /tmp/ccGFzgX3.s:1971 .text.HAL_TIM_PWM_MspDeInit:00000000 $t + /tmp/ccGFzgX3.s:1977 .text.HAL_TIM_PWM_MspDeInit:00000000 HAL_TIM_PWM_MspDeInit + /tmp/ccGFzgX3.s:1992 .text.HAL_TIM_PWM_DeInit:00000000 $t + /tmp/ccGFzgX3.s:1998 .text.HAL_TIM_PWM_DeInit:00000000 HAL_TIM_PWM_DeInit + /tmp/ccGFzgX3.s:2084 .text.HAL_TIM_IC_MspInit:00000000 $t + /tmp/ccGFzgX3.s:2090 .text.HAL_TIM_IC_MspInit:00000000 HAL_TIM_IC_MspInit + /tmp/ccGFzgX3.s:2105 .text.HAL_TIM_IC_MspDeInit:00000000 $t + /tmp/ccGFzgX3.s:2111 .text.HAL_TIM_IC_MspDeInit:00000000 HAL_TIM_IC_MspDeInit + /tmp/ccGFzgX3.s:2126 .text.HAL_TIM_IC_DeInit:00000000 $t + /tmp/ccGFzgX3.s:2132 .text.HAL_TIM_IC_DeInit:00000000 HAL_TIM_IC_DeInit + /tmp/ccGFzgX3.s:2218 .text.HAL_TIM_OnePulse_MspInit:00000000 $t + /tmp/ccGFzgX3.s:2224 .text.HAL_TIM_OnePulse_MspInit:00000000 HAL_TIM_OnePulse_MspInit + /tmp/ccGFzgX3.s:2239 .text.HAL_TIM_OnePulse_MspDeInit:00000000 $t + /tmp/ccGFzgX3.s:2245 .text.HAL_TIM_OnePulse_MspDeInit:00000000 HAL_TIM_OnePulse_MspDeInit + /tmp/ccGFzgX3.s:2260 .text.HAL_TIM_OnePulse_DeInit:00000000 $t + /tmp/ccGFzgX3.s:2266 .text.HAL_TIM_OnePulse_DeInit:00000000 HAL_TIM_OnePulse_DeInit + /tmp/ccGFzgX3.s:2336 .text.HAL_TIM_Encoder_MspInit:00000000 $t + /tmp/ccGFzgX3.s:2342 .text.HAL_TIM_Encoder_MspInit:00000000 HAL_TIM_Encoder_MspInit + /tmp/ccGFzgX3.s:2357 .text.HAL_TIM_Encoder_MspDeInit:00000000 $t + /tmp/ccGFzgX3.s:2363 .text.HAL_TIM_Encoder_MspDeInit:00000000 HAL_TIM_Encoder_MspDeInit + /tmp/ccGFzgX3.s:2378 .text.HAL_TIM_Encoder_DeInit:00000000 $t + /tmp/ccGFzgX3.s:2384 .text.HAL_TIM_Encoder_DeInit:00000000 HAL_TIM_Encoder_DeInit + /tmp/ccGFzgX3.s:2454 .text.HAL_TIM_DMABurst_MultiWriteStart:00000000 $t + /tmp/ccGFzgX3.s:2460 .text.HAL_TIM_DMABurst_MultiWriteStart:00000000 HAL_TIM_DMABurst_MultiWriteStart + /tmp/ccGFzgX3.s:2817 .text.HAL_TIM_DMABurst_MultiWriteStart:00000190 $d + /tmp/ccGFzgX3.s:4234 .text.TIM_DMADelayPulseCplt:00000000 TIM_DMADelayPulseCplt + /tmp/ccGFzgX3.s:4381 .text.TIM_DMADelayPulseHalfCplt:00000000 TIM_DMADelayPulseHalfCplt + /tmp/ccGFzgX3.s:4797 .text.TIM_DMATriggerCplt:00000000 TIM_DMATriggerCplt + /tmp/ccGFzgX3.s:4861 .text.TIM_DMATriggerHalfCplt:00000000 TIM_DMATriggerHalfCplt + /tmp/ccGFzgX3.s:2830 .text.HAL_TIM_DMABurst_WriteStart:00000000 $t + /tmp/ccGFzgX3.s:2836 .text.HAL_TIM_DMABurst_WriteStart:00000000 HAL_TIM_DMABurst_WriteStart + /tmp/ccGFzgX3.s:2876 .text.HAL_TIM_DMABurst_WriteStop:00000000 $t + /tmp/ccGFzgX3.s:2882 .text.HAL_TIM_DMABurst_WriteStop:00000000 HAL_TIM_DMABurst_WriteStop + /tmp/ccGFzgX3.s:3034 .text.HAL_TIM_DMABurst_MultiReadStart:00000000 $t + /tmp/ccGFzgX3.s:3040 .text.HAL_TIM_DMABurst_MultiReadStart:00000000 HAL_TIM_DMABurst_MultiReadStart + /tmp/ccGFzgX3.s:3397 .text.HAL_TIM_DMABurst_MultiReadStart:00000190 $d + /tmp/ccGFzgX3.s:3971 .text.TIM_DMACaptureCplt:00000000 TIM_DMACaptureCplt + /tmp/ccGFzgX3.s:4126 .text.TIM_DMACaptureHalfCplt:00000000 TIM_DMACaptureHalfCplt + /tmp/ccGFzgX3.s:3410 .text.HAL_TIM_DMABurst_ReadStart:00000000 $t + /tmp/ccGFzgX3.s:3416 .text.HAL_TIM_DMABurst_ReadStart:00000000 HAL_TIM_DMABurst_ReadStart + /tmp/ccGFzgX3.s:3456 .text.HAL_TIM_DMABurst_ReadStop:00000000 $t + /tmp/ccGFzgX3.s:3462 .text.HAL_TIM_DMABurst_ReadStop:00000000 HAL_TIM_DMABurst_ReadStop + /tmp/ccGFzgX3.s:3614 .text.HAL_TIM_GenerateEvent:00000000 $t + /tmp/ccGFzgX3.s:3620 .text.HAL_TIM_GenerateEvent:00000000 HAL_TIM_GenerateEvent + /tmp/ccGFzgX3.s:3673 .text.HAL_TIM_ConfigTI1Input:00000000 $t + /tmp/ccGFzgX3.s:3679 .text.HAL_TIM_ConfigTI1Input:00000000 HAL_TIM_ConfigTI1Input + /tmp/ccGFzgX3.s:3717 .text.HAL_TIM_ReadCapturedValue:00000000 $t + /tmp/ccGFzgX3.s:3723 .text.HAL_TIM_ReadCapturedValue:00000000 HAL_TIM_ReadCapturedValue + /tmp/ccGFzgX3.s:3737 .text.HAL_TIM_ReadCapturedValue:00000008 $d + /tmp/ccGFzgX3.s:3806 .text.HAL_TIM_PeriodElapsedCallback:00000000 $t + /tmp/ccGFzgX3.s:3812 .text.HAL_TIM_PeriodElapsedCallback:00000000 HAL_TIM_PeriodElapsedCallback + /tmp/ccGFzgX3.s:3827 .text.TIM_DMAPeriodElapsedCplt:00000000 $t + /tmp/ccGFzgX3.s:3870 .text.HAL_TIM_PeriodElapsedHalfCpltCallback:00000000 $t + ARM GAS /tmp/ccGFzgX3.s page 495 + + + /tmp/ccGFzgX3.s:3876 .text.HAL_TIM_PeriodElapsedHalfCpltCallback:00000000 HAL_TIM_PeriodElapsedHalfCpltCallback + /tmp/ccGFzgX3.s:3891 .text.TIM_DMAPeriodElapsedHalfCplt:00000000 $t + /tmp/ccGFzgX3.s:3923 .text.HAL_TIM_OC_DelayElapsedCallback:00000000 $t + /tmp/ccGFzgX3.s:3929 .text.HAL_TIM_OC_DelayElapsedCallback:00000000 HAL_TIM_OC_DelayElapsedCallback + /tmp/ccGFzgX3.s:3944 .text.HAL_TIM_IC_CaptureCallback:00000000 $t + /tmp/ccGFzgX3.s:3950 .text.HAL_TIM_IC_CaptureCallback:00000000 HAL_TIM_IC_CaptureCallback + /tmp/ccGFzgX3.s:3965 .text.TIM_DMACaptureCplt:00000000 $t + /tmp/ccGFzgX3.s:4099 .text.HAL_TIM_IC_CaptureHalfCpltCallback:00000000 $t + /tmp/ccGFzgX3.s:4105 .text.HAL_TIM_IC_CaptureHalfCpltCallback:00000000 HAL_TIM_IC_CaptureHalfCpltCallback + /tmp/ccGFzgX3.s:4120 .text.TIM_DMACaptureHalfCplt:00000000 $t + /tmp/ccGFzgX3.s:4208 .text.HAL_TIM_PWM_PulseFinishedCallback:00000000 $t + /tmp/ccGFzgX3.s:4214 .text.HAL_TIM_PWM_PulseFinishedCallback:00000000 HAL_TIM_PWM_PulseFinishedCallback + /tmp/ccGFzgX3.s:4229 .text.TIM_DMADelayPulseCplt:00000000 $t + /tmp/ccGFzgX3.s:4354 .text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback:00000000 $t + /tmp/ccGFzgX3.s:4360 .text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback:00000000 HAL_TIM_PWM_PulseFinishedHalfCpltCallback + /tmp/ccGFzgX3.s:4375 .text.TIM_DMADelayPulseHalfCplt:00000000 $t + /tmp/ccGFzgX3.s:4463 .text.HAL_TIM_TriggerCallback:00000000 $t + /tmp/ccGFzgX3.s:4469 .text.HAL_TIM_TriggerCallback:00000000 HAL_TIM_TriggerCallback + /tmp/ccGFzgX3.s:4484 .text.HAL_TIM_IRQHandler:00000000 $t + /tmp/ccGFzgX3.s:4490 .text.HAL_TIM_IRQHandler:00000000 HAL_TIM_IRQHandler + /tmp/ccGFzgX3.s:4792 .text.TIM_DMATriggerCplt:00000000 $t + /tmp/ccGFzgX3.s:4835 .text.HAL_TIM_TriggerHalfCpltCallback:00000000 $t + /tmp/ccGFzgX3.s:4841 .text.HAL_TIM_TriggerHalfCpltCallback:00000000 HAL_TIM_TriggerHalfCpltCallback + /tmp/ccGFzgX3.s:4856 .text.TIM_DMATriggerHalfCplt:00000000 $t + /tmp/ccGFzgX3.s:4888 .text.HAL_TIM_ErrorCallback:00000000 $t + /tmp/ccGFzgX3.s:4894 .text.HAL_TIM_ErrorCallback:00000000 HAL_TIM_ErrorCallback + /tmp/ccGFzgX3.s:4909 .text.TIM_DMAError:00000000 $t + /tmp/ccGFzgX3.s:5013 .text.HAL_TIM_Base_GetState:00000000 $t + /tmp/ccGFzgX3.s:5019 .text.HAL_TIM_Base_GetState:00000000 HAL_TIM_Base_GetState + /tmp/ccGFzgX3.s:5037 .text.HAL_TIM_OC_GetState:00000000 $t + /tmp/ccGFzgX3.s:5043 .text.HAL_TIM_OC_GetState:00000000 HAL_TIM_OC_GetState + /tmp/ccGFzgX3.s:5061 .text.HAL_TIM_PWM_GetState:00000000 $t + /tmp/ccGFzgX3.s:5067 .text.HAL_TIM_PWM_GetState:00000000 HAL_TIM_PWM_GetState + /tmp/ccGFzgX3.s:5085 .text.HAL_TIM_IC_GetState:00000000 $t + /tmp/ccGFzgX3.s:5091 .text.HAL_TIM_IC_GetState:00000000 HAL_TIM_IC_GetState + /tmp/ccGFzgX3.s:5109 .text.HAL_TIM_OnePulse_GetState:00000000 $t + /tmp/ccGFzgX3.s:5115 .text.HAL_TIM_OnePulse_GetState:00000000 HAL_TIM_OnePulse_GetState + /tmp/ccGFzgX3.s:5133 .text.HAL_TIM_Encoder_GetState:00000000 $t + /tmp/ccGFzgX3.s:5139 .text.HAL_TIM_Encoder_GetState:00000000 HAL_TIM_Encoder_GetState + /tmp/ccGFzgX3.s:5157 .text.HAL_TIM_GetActiveChannel:00000000 $t + /tmp/ccGFzgX3.s:5163 .text.HAL_TIM_GetActiveChannel:00000000 HAL_TIM_GetActiveChannel + /tmp/ccGFzgX3.s:5181 .text.HAL_TIM_GetChannelState:00000000 $t + /tmp/ccGFzgX3.s:5187 .text.HAL_TIM_GetChannelState:00000000 HAL_TIM_GetChannelState + /tmp/ccGFzgX3.s:5202 .text.HAL_TIM_GetChannelState:00000008 $d + /tmp/ccGFzgX3.s:5274 .text.HAL_TIM_DMABurstState:00000000 $t + /tmp/ccGFzgX3.s:5280 .text.HAL_TIM_DMABurstState:00000000 HAL_TIM_DMABurstState + /tmp/ccGFzgX3.s:5299 .text.TIM_Base_SetConfig:00000000 $t + /tmp/ccGFzgX3.s:5305 .text.TIM_Base_SetConfig:00000000 TIM_Base_SetConfig + /tmp/ccGFzgX3.s:5493 .text.TIM_Base_SetConfig:00000104 $d + /tmp/ccGFzgX3.s:5504 .text.HAL_TIM_Base_Init:00000000 $t + /tmp/ccGFzgX3.s:5510 .text.HAL_TIM_Base_Init:00000000 HAL_TIM_Base_Init + /tmp/ccGFzgX3.s:5611 .text.HAL_TIM_OC_Init:00000000 $t + /tmp/ccGFzgX3.s:5617 .text.HAL_TIM_OC_Init:00000000 HAL_TIM_OC_Init + /tmp/ccGFzgX3.s:5718 .text.HAL_TIM_PWM_Init:00000000 $t + /tmp/ccGFzgX3.s:5724 .text.HAL_TIM_PWM_Init:00000000 HAL_TIM_PWM_Init + /tmp/ccGFzgX3.s:5825 .text.HAL_TIM_IC_Init:00000000 $t + /tmp/ccGFzgX3.s:5831 .text.HAL_TIM_IC_Init:00000000 HAL_TIM_IC_Init + ARM GAS /tmp/ccGFzgX3.s page 496 + + + /tmp/ccGFzgX3.s:5932 .text.HAL_TIM_OnePulse_Init:00000000 $t + /tmp/ccGFzgX3.s:5938 .text.HAL_TIM_OnePulse_Init:00000000 HAL_TIM_OnePulse_Init + /tmp/ccGFzgX3.s:6045 .text.HAL_TIM_Encoder_Init:00000000 $t + /tmp/ccGFzgX3.s:6051 .text.HAL_TIM_Encoder_Init:00000000 HAL_TIM_Encoder_Init + /tmp/ccGFzgX3.s:6259 .text.HAL_TIM_Encoder_Init:000000a4 $d + /tmp/ccGFzgX3.s:6266 .text.TIM_OC2_SetConfig:00000000 $t + /tmp/ccGFzgX3.s:6272 .text.TIM_OC2_SetConfig:00000000 TIM_OC2_SetConfig + /tmp/ccGFzgX3.s:6410 .text.TIM_OC2_SetConfig:00000064 $d + /tmp/ccGFzgX3.s:6417 .text.HAL_TIM_OC_ConfigChannel:00000000 $t + /tmp/ccGFzgX3.s:6423 .text.HAL_TIM_OC_ConfigChannel:00000000 HAL_TIM_OC_ConfigChannel + /tmp/ccGFzgX3.s:6455 .text.HAL_TIM_OC_ConfigChannel:0000001a $d + /tmp/ccGFzgX3.s:6589 .text.HAL_TIM_PWM_ConfigChannel:00000000 $t + /tmp/ccGFzgX3.s:6595 .text.HAL_TIM_PWM_ConfigChannel:00000000 HAL_TIM_PWM_ConfigChannel + /tmp/ccGFzgX3.s:6632 .text.HAL_TIM_PWM_ConfigChannel:00000020 $d + /tmp/ccGFzgX3.s:6920 .text.TIM_TI1_SetConfig:00000000 $t + /tmp/ccGFzgX3.s:6926 .text.TIM_TI1_SetConfig:00000000 TIM_TI1_SetConfig + /tmp/ccGFzgX3.s:7056 .text.TIM_TI1_SetConfig:00000088 $d + /tmp/ccGFzgX3.s:7063 .text.HAL_TIM_IC_ConfigChannel:00000000 $t + /tmp/ccGFzgX3.s:7069 .text.HAL_TIM_IC_ConfigChannel:00000000 HAL_TIM_IC_ConfigChannel + /tmp/ccGFzgX3.s:7107 .text.HAL_TIM_IC_ConfigChannel:0000001c $d + /tmp/ccGFzgX3.s:7294 .text.HAL_TIM_OnePulse_ConfigChannel:00000000 $t + /tmp/ccGFzgX3.s:7300 .text.HAL_TIM_OnePulse_ConfigChannel:00000000 HAL_TIM_OnePulse_ConfigChannel + /tmp/ccGFzgX3.s:7573 .text.HAL_TIM_OnePulse_ConfigChannel:000000fc $d + /tmp/ccGFzgX3.s:7578 .text.TIM_ETR_SetConfig:00000000 $t + /tmp/ccGFzgX3.s:7584 .text.TIM_ETR_SetConfig:00000000 TIM_ETR_SetConfig + /tmp/ccGFzgX3.s:7628 .text.HAL_TIM_ConfigOCrefClear:00000000 $t + /tmp/ccGFzgX3.s:7634 .text.HAL_TIM_ConfigOCrefClear:00000000 HAL_TIM_ConfigOCrefClear + /tmp/ccGFzgX3.s:7709 .text.HAL_TIM_ConfigOCrefClear:00000048 $d + /tmp/ccGFzgX3.s:7918 .text.HAL_TIM_ConfigClockSource:00000000 $t + /tmp/ccGFzgX3.s:7924 .text.HAL_TIM_ConfigClockSource:00000000 HAL_TIM_ConfigClockSource + /tmp/ccGFzgX3.s:8210 .text.HAL_TIM_ConfigClockSource:000000fc $d + /tmp/ccGFzgX3.s:8215 .text.TIM_SlaveTimer_SetConfig:00000000 $t + /tmp/ccGFzgX3.s:8220 .text.TIM_SlaveTimer_SetConfig:00000000 TIM_SlaveTimer_SetConfig + /tmp/ccGFzgX3.s:8474 .text.TIM_SlaveTimer_SetConfig:000000b8 $d + /tmp/ccGFzgX3.s:8479 .text.HAL_TIM_SlaveConfigSynchro:00000000 $t + /tmp/ccGFzgX3.s:8485 .text.HAL_TIM_SlaveConfigSynchro:00000000 HAL_TIM_SlaveConfigSynchro + /tmp/ccGFzgX3.s:8573 .text.HAL_TIM_SlaveConfigSynchro_IT:00000000 $t + /tmp/ccGFzgX3.s:8579 .text.HAL_TIM_SlaveConfigSynchro_IT:00000000 HAL_TIM_SlaveConfigSynchro_IT + /tmp/ccGFzgX3.s:8667 .text.TIM_CCxChannelCmd:00000000 $t + /tmp/ccGFzgX3.s:8673 .text.TIM_CCxChannelCmd:00000000 TIM_CCxChannelCmd + /tmp/ccGFzgX3.s:8713 .text.HAL_TIM_OC_Start:00000000 $t + /tmp/ccGFzgX3.s:8719 .text.HAL_TIM_OC_Start:00000000 HAL_TIM_OC_Start + /tmp/ccGFzgX3.s:8740 .text.HAL_TIM_OC_Start:0000000c $d + /tmp/ccGFzgX3.s:8775 .text.HAL_TIM_OC_Start:00000038 $d + /tmp/ccGFzgX3.s:8971 .text.HAL_TIM_OC_Start:0000014c $d + /tmp/ccGFzgX3.s:8978 .text.HAL_TIM_OC_Stop:00000000 $t + /tmp/ccGFzgX3.s:8984 .text.HAL_TIM_OC_Stop:00000000 HAL_TIM_OC_Stop + /tmp/ccGFzgX3.s:9059 .text.HAL_TIM_OC_Stop:0000005e $d + /tmp/ccGFzgX3.s:9115 .text.HAL_TIM_OC_Stop:000000a4 $d + /tmp/ccGFzgX3.s:9121 .text.HAL_TIM_OC_Start_IT:00000000 $t + /tmp/ccGFzgX3.s:9127 .text.HAL_TIM_OC_Start_IT:00000000 HAL_TIM_OC_Start_IT + /tmp/ccGFzgX3.s:9150 .text.HAL_TIM_OC_Start_IT:0000000c $d + /tmp/ccGFzgX3.s:9185 .text.HAL_TIM_OC_Start_IT:0000003a $d + /tmp/ccGFzgX3.s:9388 .text.HAL_TIM_OC_Start_IT:0000015c $d + /tmp/ccGFzgX3.s:9402 .text.HAL_TIM_OC_Start_IT:00000190 $t + /tmp/ccGFzgX3.s:9448 .text.HAL_TIM_OC_Start_IT:000001b8 $d + /tmp/ccGFzgX3.s:9455 .text.HAL_TIM_OC_Stop_IT:00000000 $t + ARM GAS /tmp/ccGFzgX3.s page 497 + + + /tmp/ccGFzgX3.s:9461 .text.HAL_TIM_OC_Stop_IT:00000000 HAL_TIM_OC_Stop_IT + /tmp/ccGFzgX3.s:9486 .text.HAL_TIM_OC_Stop_IT:0000000e $d + /tmp/ccGFzgX3.s:9569 .text.HAL_TIM_OC_Stop_IT:00000080 $d + /tmp/ccGFzgX3.s:9666 .text.HAL_TIM_OC_Stop_IT:000000f8 $d + /tmp/ccGFzgX3.s:9672 .text.HAL_TIM_OC_Start_DMA:00000000 $t + /tmp/ccGFzgX3.s:9678 .text.HAL_TIM_OC_Start_DMA:00000000 HAL_TIM_OC_Start_DMA + /tmp/ccGFzgX3.s:9706 .text.HAL_TIM_OC_Start_DMA:00000010 $d + /tmp/ccGFzgX3.s:9744 .text.HAL_TIM_OC_Start_DMA:0000003e $d + /tmp/ccGFzgX3.s:9851 .text.HAL_TIM_OC_Start_DMA:000000c8 $d + /tmp/ccGFzgX3.s:9868 .text.HAL_TIM_OC_Start_DMA:000000ea $t + /tmp/ccGFzgX3.s:10177 .text.HAL_TIM_OC_Start_DMA:00000290 $d + /tmp/ccGFzgX3.s:10191 .text.HAL_TIM_OC_Start_DMA:000002c4 $t + /tmp/ccGFzgX3.s:10260 .text.HAL_TIM_OC_Start_DMA:00000304 $d + /tmp/ccGFzgX3.s:10270 .text.HAL_TIM_OC_Stop_DMA:00000000 $t + /tmp/ccGFzgX3.s:10276 .text.HAL_TIM_OC_Stop_DMA:00000000 HAL_TIM_OC_Stop_DMA + /tmp/ccGFzgX3.s:10301 .text.HAL_TIM_OC_Stop_DMA:0000000e $d + /tmp/ccGFzgX3.s:10387 .text.HAL_TIM_OC_Stop_DMA:00000086 $d + /tmp/ccGFzgX3.s:10506 .text.HAL_TIM_OC_Stop_DMA:00000110 $d + /tmp/ccGFzgX3.s:10512 .text.HAL_TIM_PWM_Start:00000000 $t + /tmp/ccGFzgX3.s:10518 .text.HAL_TIM_PWM_Start:00000000 HAL_TIM_PWM_Start + /tmp/ccGFzgX3.s:10539 .text.HAL_TIM_PWM_Start:0000000c $d + /tmp/ccGFzgX3.s:10574 .text.HAL_TIM_PWM_Start:00000038 $d + /tmp/ccGFzgX3.s:10770 .text.HAL_TIM_PWM_Start:0000014c $d + /tmp/ccGFzgX3.s:10777 .text.HAL_TIM_PWM_Stop:00000000 $t + /tmp/ccGFzgX3.s:10783 .text.HAL_TIM_PWM_Stop:00000000 HAL_TIM_PWM_Stop + /tmp/ccGFzgX3.s:10858 .text.HAL_TIM_PWM_Stop:0000005e $d + /tmp/ccGFzgX3.s:10914 .text.HAL_TIM_PWM_Stop:000000a4 $d + /tmp/ccGFzgX3.s:10920 .text.HAL_TIM_PWM_Start_IT:00000000 $t + /tmp/ccGFzgX3.s:10926 .text.HAL_TIM_PWM_Start_IT:00000000 HAL_TIM_PWM_Start_IT + /tmp/ccGFzgX3.s:10949 .text.HAL_TIM_PWM_Start_IT:0000000c $d + /tmp/ccGFzgX3.s:10984 .text.HAL_TIM_PWM_Start_IT:0000003a $d + /tmp/ccGFzgX3.s:11187 .text.HAL_TIM_PWM_Start_IT:0000015c $d + /tmp/ccGFzgX3.s:11201 .text.HAL_TIM_PWM_Start_IT:00000190 $t + /tmp/ccGFzgX3.s:11247 .text.HAL_TIM_PWM_Start_IT:000001b8 $d + /tmp/ccGFzgX3.s:11254 .text.HAL_TIM_PWM_Stop_IT:00000000 $t + /tmp/ccGFzgX3.s:11260 .text.HAL_TIM_PWM_Stop_IT:00000000 HAL_TIM_PWM_Stop_IT + /tmp/ccGFzgX3.s:11285 .text.HAL_TIM_PWM_Stop_IT:0000000e $d + /tmp/ccGFzgX3.s:11368 .text.HAL_TIM_PWM_Stop_IT:00000080 $d + /tmp/ccGFzgX3.s:11465 .text.HAL_TIM_PWM_Stop_IT:000000f8 $d + /tmp/ccGFzgX3.s:11471 .text.HAL_TIM_PWM_Start_DMA:00000000 $t + /tmp/ccGFzgX3.s:11477 .text.HAL_TIM_PWM_Start_DMA:00000000 HAL_TIM_PWM_Start_DMA + /tmp/ccGFzgX3.s:11505 .text.HAL_TIM_PWM_Start_DMA:00000010 $d + /tmp/ccGFzgX3.s:11543 .text.HAL_TIM_PWM_Start_DMA:0000003e $d + /tmp/ccGFzgX3.s:11650 .text.HAL_TIM_PWM_Start_DMA:000000c8 $d + /tmp/ccGFzgX3.s:11667 .text.HAL_TIM_PWM_Start_DMA:000000ea $t + /tmp/ccGFzgX3.s:11976 .text.HAL_TIM_PWM_Start_DMA:00000290 $d + /tmp/ccGFzgX3.s:11990 .text.HAL_TIM_PWM_Start_DMA:000002c4 $t + /tmp/ccGFzgX3.s:12059 .text.HAL_TIM_PWM_Start_DMA:00000304 $d + /tmp/ccGFzgX3.s:12069 .text.HAL_TIM_PWM_Stop_DMA:00000000 $t + /tmp/ccGFzgX3.s:12075 .text.HAL_TIM_PWM_Stop_DMA:00000000 HAL_TIM_PWM_Stop_DMA + /tmp/ccGFzgX3.s:12100 .text.HAL_TIM_PWM_Stop_DMA:0000000e $d + /tmp/ccGFzgX3.s:12186 .text.HAL_TIM_PWM_Stop_DMA:00000086 $d + /tmp/ccGFzgX3.s:12305 .text.HAL_TIM_PWM_Stop_DMA:00000110 $d + /tmp/ccGFzgX3.s:12311 .text.HAL_TIM_IC_Start:00000000 $t + /tmp/ccGFzgX3.s:12317 .text.HAL_TIM_IC_Start:00000000 HAL_TIM_IC_Start + /tmp/ccGFzgX3.s:12337 .text.HAL_TIM_IC_Start:0000000c $d + /tmp/ccGFzgX3.s:12382 .text.HAL_TIM_IC_Start:0000003e $d + ARM GAS /tmp/ccGFzgX3.s page 498 + + + /tmp/ccGFzgX3.s:12596 .text.HAL_TIM_IC_Start:00000160 $d + /tmp/ccGFzgX3.s:12602 .text.HAL_TIM_IC_Stop:00000000 $t + /tmp/ccGFzgX3.s:12608 .text.HAL_TIM_IC_Stop:00000000 HAL_TIM_IC_Stop + /tmp/ccGFzgX3.s:12656 .text.HAL_TIM_IC_Stop:00000034 $d + /tmp/ccGFzgX3.s:12741 .text.HAL_TIM_IC_Start_IT:00000000 $t + /tmp/ccGFzgX3.s:12747 .text.HAL_TIM_IC_Start_IT:00000000 HAL_TIM_IC_Start_IT + /tmp/ccGFzgX3.s:12769 .text.HAL_TIM_IC_Start_IT:0000000c $d + /tmp/ccGFzgX3.s:12814 .text.HAL_TIM_IC_Start_IT:0000003e $d + /tmp/ccGFzgX3.s:12909 .text.HAL_TIM_IC_Start_IT:000000c0 $d + /tmp/ccGFzgX3.s:13096 .text.HAL_TIM_IC_Start_IT:000001a4 $d + /tmp/ccGFzgX3.s:13102 .text.HAL_TIM_IC_Stop_IT:00000000 $t + /tmp/ccGFzgX3.s:13108 .text.HAL_TIM_IC_Stop_IT:00000000 HAL_TIM_IC_Stop_IT + /tmp/ccGFzgX3.s:13133 .text.HAL_TIM_IC_Stop_IT:0000000e $d + /tmp/ccGFzgX3.s:13189 .text.HAL_TIM_IC_Stop_IT:00000056 $d + /tmp/ccGFzgX3.s:13312 .text.HAL_TIM_IC_Start_DMA:00000000 $t + /tmp/ccGFzgX3.s:13318 .text.HAL_TIM_IC_Start_DMA:00000000 HAL_TIM_IC_Start_DMA + /tmp/ccGFzgX3.s:13348 .text.HAL_TIM_IC_Start_DMA:00000012 $d + /tmp/ccGFzgX3.s:13408 .text.HAL_TIM_IC_Start_DMA:00000058 $d + /tmp/ccGFzgX3.s:13523 .text.HAL_TIM_IC_Start_DMA:000000e6 $d + /tmp/ccGFzgX3.s:13835 .text.HAL_TIM_IC_Start_DMA:00000268 $d + /tmp/ccGFzgX3.s:13844 .text.HAL_TIM_IC_Stop_DMA:00000000 $t + /tmp/ccGFzgX3.s:13850 .text.HAL_TIM_IC_Stop_DMA:00000000 HAL_TIM_IC_Stop_DMA + /tmp/ccGFzgX3.s:13883 .text.HAL_TIM_IC_Stop_DMA:00000016 $d + /tmp/ccGFzgX3.s:13934 .text.HAL_TIM_IC_Stop_DMA:0000005a $d + /tmp/ccGFzgX3.s:14069 .text.HAL_TIM_OnePulse_Start:00000000 $t + /tmp/ccGFzgX3.s:14075 .text.HAL_TIM_OnePulse_Start:00000000 HAL_TIM_OnePulse_Start + /tmp/ccGFzgX3.s:14196 .text.HAL_TIM_OnePulse_Start:0000007c $d + /tmp/ccGFzgX3.s:14202 .text.HAL_TIM_OnePulse_Stop:00000000 $t + /tmp/ccGFzgX3.s:14208 .text.HAL_TIM_OnePulse_Stop:00000000 HAL_TIM_OnePulse_Stop + /tmp/ccGFzgX3.s:14302 .text.HAL_TIM_OnePulse_Stop:00000078 $d + /tmp/ccGFzgX3.s:14308 .text.HAL_TIM_OnePulse_Start_IT:00000000 $t + /tmp/ccGFzgX3.s:14314 .text.HAL_TIM_OnePulse_Start_IT:00000000 HAL_TIM_OnePulse_Start_IT + /tmp/ccGFzgX3.s:14445 .text.HAL_TIM_OnePulse_Start_IT:00000090 $d + /tmp/ccGFzgX3.s:14451 .text.HAL_TIM_OnePulse_Stop_IT:00000000 $t + /tmp/ccGFzgX3.s:14457 .text.HAL_TIM_OnePulse_Stop_IT:00000000 HAL_TIM_OnePulse_Stop_IT + /tmp/ccGFzgX3.s:14561 .text.HAL_TIM_OnePulse_Stop_IT:0000008c $d + /tmp/ccGFzgX3.s:14567 .text.HAL_TIM_Encoder_Start:00000000 $t + /tmp/ccGFzgX3.s:14573 .text.HAL_TIM_Encoder_Start:00000000 HAL_TIM_Encoder_Start + /tmp/ccGFzgX3.s:14774 .text.HAL_TIM_Encoder_Stop:00000000 $t + /tmp/ccGFzgX3.s:14780 .text.HAL_TIM_Encoder_Stop:00000000 HAL_TIM_Encoder_Stop + /tmp/ccGFzgX3.s:14863 .text.HAL_TIM_Encoder_Stop:0000005a $d + /tmp/ccGFzgX3.s:14977 .text.HAL_TIM_Encoder_Start_IT:00000000 $t + /tmp/ccGFzgX3.s:14983 .text.HAL_TIM_Encoder_Start_IT:00000000 HAL_TIM_Encoder_Start_IT + /tmp/ccGFzgX3.s:15206 .text.HAL_TIM_Encoder_Stop_IT:00000000 $t + /tmp/ccGFzgX3.s:15212 .text.HAL_TIM_Encoder_Stop_IT:00000000 HAL_TIM_Encoder_Stop_IT + /tmp/ccGFzgX3.s:15294 .text.HAL_TIM_Encoder_Stop_IT:00000064 $d + /tmp/ccGFzgX3.s:15430 .text.HAL_TIM_Encoder_Start_DMA:00000000 $t + /tmp/ccGFzgX3.s:15436 .text.HAL_TIM_Encoder_Start_DMA:00000000 HAL_TIM_Encoder_Start_DMA + /tmp/ccGFzgX3.s:15920 .text.HAL_TIM_Encoder_Start_DMA:00000240 $d + /tmp/ccGFzgX3.s:15927 .text.HAL_TIM_Encoder_Stop_DMA:00000000 $t + /tmp/ccGFzgX3.s:15933 .text.HAL_TIM_Encoder_Stop_DMA:00000000 HAL_TIM_Encoder_Stop_DMA + /tmp/ccGFzgX3.s:16025 .text.HAL_TIM_Encoder_Stop_DMA:00000070 $d + /tmp/ccGFzgX3.s:3750 .text.HAL_TIM_ReadCapturedValue:00000015 $d + /tmp/ccGFzgX3.s:3750 .text.HAL_TIM_ReadCapturedValue:00000016 $t + /tmp/ccGFzgX3.s:5219 .text.HAL_TIM_GetChannelState:00000019 $d + /tmp/ccGFzgX3.s:5219 .text.HAL_TIM_GetChannelState:0000001a $t + /tmp/ccGFzgX3.s:6476 .text.HAL_TIM_OC_ConfigChannel:0000002f $d + ARM GAS /tmp/ccGFzgX3.s page 499 + + + /tmp/ccGFzgX3.s:6476 .text.HAL_TIM_OC_ConfigChannel:00000030 $t + /tmp/ccGFzgX3.s:6653 .text.HAL_TIM_PWM_ConfigChannel:00000035 $d + /tmp/ccGFzgX3.s:6653 .text.HAL_TIM_PWM_ConfigChannel:00000036 $t + /tmp/ccGFzgX3.s:7120 .text.HAL_TIM_IC_ConfigChannel:00000029 $d + /tmp/ccGFzgX3.s:7120 .text.HAL_TIM_IC_ConfigChannel:0000002a $t + /tmp/ccGFzgX3.s:7731 .text.HAL_TIM_ConfigOCrefClear:0000005d $d + /tmp/ccGFzgX3.s:7731 .text.HAL_TIM_ConfigOCrefClear:0000005e $t + /tmp/ccGFzgX3.s:8757 .text.HAL_TIM_OC_Start:0000001d $d + /tmp/ccGFzgX3.s:8757 .text.HAL_TIM_OC_Start:0000001e $t + /tmp/ccGFzgX3.s:8792 .text.HAL_TIM_OC_Start:00000049 $d + /tmp/ccGFzgX3.s:8792 .text.HAL_TIM_OC_Start:0000004a $t + /tmp/ccGFzgX3.s:9076 .text.HAL_TIM_OC_Stop:0000006f $d + /tmp/ccGFzgX3.s:9076 .text.HAL_TIM_OC_Stop:00000070 $t + /tmp/ccGFzgX3.s:9167 .text.HAL_TIM_OC_Start_IT:0000001d $d + /tmp/ccGFzgX3.s:9167 .text.HAL_TIM_OC_Start_IT:0000001e $t + /tmp/ccGFzgX3.s:9202 .text.HAL_TIM_OC_Start_IT:0000004b $d + /tmp/ccGFzgX3.s:9202 .text.HAL_TIM_OC_Start_IT:0000004c $t + /tmp/ccGFzgX3.s:9499 .text.HAL_TIM_OC_Stop_IT:0000001b $d + /tmp/ccGFzgX3.s:9499 .text.HAL_TIM_OC_Stop_IT:0000001c $t + /tmp/ccGFzgX3.s:9587 .text.HAL_TIM_OC_Stop_IT:00000091 $d + /tmp/ccGFzgX3.s:9587 .text.HAL_TIM_OC_Stop_IT:00000092 $t + /tmp/ccGFzgX3.s:9723 .text.HAL_TIM_OC_Start_DMA:00000021 $d + /tmp/ccGFzgX3.s:9723 .text.HAL_TIM_OC_Start_DMA:00000022 $t + /tmp/ccGFzgX3.s:9762 .text.HAL_TIM_OC_Start_DMA:0000004f $d + /tmp/ccGFzgX3.s:9762 .text.HAL_TIM_OC_Start_DMA:00000050 $t + /tmp/ccGFzgX3.s:10314 .text.HAL_TIM_OC_Stop_DMA:0000001b $d + /tmp/ccGFzgX3.s:10314 .text.HAL_TIM_OC_Stop_DMA:0000001c $t + /tmp/ccGFzgX3.s:10405 .text.HAL_TIM_OC_Stop_DMA:00000097 $d + /tmp/ccGFzgX3.s:10405 .text.HAL_TIM_OC_Stop_DMA:00000098 $t + /tmp/ccGFzgX3.s:10556 .text.HAL_TIM_PWM_Start:0000001d $d + /tmp/ccGFzgX3.s:10556 .text.HAL_TIM_PWM_Start:0000001e $t + /tmp/ccGFzgX3.s:10591 .text.HAL_TIM_PWM_Start:00000049 $d + /tmp/ccGFzgX3.s:10591 .text.HAL_TIM_PWM_Start:0000004a $t + /tmp/ccGFzgX3.s:10875 .text.HAL_TIM_PWM_Stop:0000006f $d + /tmp/ccGFzgX3.s:10875 .text.HAL_TIM_PWM_Stop:00000070 $t + /tmp/ccGFzgX3.s:10966 .text.HAL_TIM_PWM_Start_IT:0000001d $d + /tmp/ccGFzgX3.s:10966 .text.HAL_TIM_PWM_Start_IT:0000001e $t + /tmp/ccGFzgX3.s:11001 .text.HAL_TIM_PWM_Start_IT:0000004b $d + /tmp/ccGFzgX3.s:11001 .text.HAL_TIM_PWM_Start_IT:0000004c $t + /tmp/ccGFzgX3.s:11298 .text.HAL_TIM_PWM_Stop_IT:0000001b $d + /tmp/ccGFzgX3.s:11298 .text.HAL_TIM_PWM_Stop_IT:0000001c $t + /tmp/ccGFzgX3.s:11386 .text.HAL_TIM_PWM_Stop_IT:00000091 $d + /tmp/ccGFzgX3.s:11386 .text.HAL_TIM_PWM_Stop_IT:00000092 $t + /tmp/ccGFzgX3.s:11522 .text.HAL_TIM_PWM_Start_DMA:00000021 $d + /tmp/ccGFzgX3.s:11522 .text.HAL_TIM_PWM_Start_DMA:00000022 $t + /tmp/ccGFzgX3.s:11561 .text.HAL_TIM_PWM_Start_DMA:0000004f $d + /tmp/ccGFzgX3.s:11561 .text.HAL_TIM_PWM_Start_DMA:00000050 $t + /tmp/ccGFzgX3.s:12113 .text.HAL_TIM_PWM_Stop_DMA:0000001b $d + /tmp/ccGFzgX3.s:12113 .text.HAL_TIM_PWM_Stop_DMA:0000001c $t + /tmp/ccGFzgX3.s:12204 .text.HAL_TIM_PWM_Stop_DMA:00000097 $d + /tmp/ccGFzgX3.s:12204 .text.HAL_TIM_PWM_Stop_DMA:00000098 $t + /tmp/ccGFzgX3.s:12354 .text.HAL_TIM_IC_Start:0000001d $d + /tmp/ccGFzgX3.s:12354 .text.HAL_TIM_IC_Start:0000001e $t + /tmp/ccGFzgX3.s:12399 .text.HAL_TIM_IC_Start:0000004f $d + /tmp/ccGFzgX3.s:12399 .text.HAL_TIM_IC_Start:00000050 $t + /tmp/ccGFzgX3.s:12673 .text.HAL_TIM_IC_Stop:00000045 $d + /tmp/ccGFzgX3.s:12673 .text.HAL_TIM_IC_Stop:00000046 $t + ARM GAS /tmp/ccGFzgX3.s page 500 + + + /tmp/ccGFzgX3.s:12786 .text.HAL_TIM_IC_Start_IT:0000001d $d + /tmp/ccGFzgX3.s:12786 .text.HAL_TIM_IC_Start_IT:0000001e $t + /tmp/ccGFzgX3.s:12831 .text.HAL_TIM_IC_Start_IT:0000004f $d + /tmp/ccGFzgX3.s:12831 .text.HAL_TIM_IC_Start_IT:00000050 $t + /tmp/ccGFzgX3.s:12922 .text.HAL_TIM_IC_Start_IT:000000cd $d + /tmp/ccGFzgX3.s:12922 .text.HAL_TIM_IC_Start_IT:000000ce $t + /tmp/ccGFzgX3.s:13146 .text.HAL_TIM_IC_Stop_IT:0000001b $d + /tmp/ccGFzgX3.s:13146 .text.HAL_TIM_IC_Stop_IT:0000001c $t + /tmp/ccGFzgX3.s:13207 .text.HAL_TIM_IC_Stop_IT:00000067 $d + /tmp/ccGFzgX3.s:13207 .text.HAL_TIM_IC_Stop_IT:00000068 $t + /tmp/ccGFzgX3.s:13365 .text.HAL_TIM_IC_Start_DMA:00000023 $d + /tmp/ccGFzgX3.s:13365 .text.HAL_TIM_IC_Start_DMA:00000024 $t + /tmp/ccGFzgX3.s:13425 .text.HAL_TIM_IC_Start_DMA:00000069 $d + /tmp/ccGFzgX3.s:13425 .text.HAL_TIM_IC_Start_DMA:0000006a $t + /tmp/ccGFzgX3.s:13537 .text.HAL_TIM_IC_Start_DMA:000000f3 $d + /tmp/ccGFzgX3.s:13537 .text.HAL_TIM_IC_Start_DMA:000000f4 $t + /tmp/ccGFzgX3.s:13896 .text.HAL_TIM_IC_Stop_DMA:00000023 $d + /tmp/ccGFzgX3.s:13896 .text.HAL_TIM_IC_Stop_DMA:00000024 $t + /tmp/ccGFzgX3.s:13951 .text.HAL_TIM_IC_Stop_DMA:0000006b $d + /tmp/ccGFzgX3.s:13951 .text.HAL_TIM_IC_Stop_DMA:0000006c $t + /tmp/ccGFzgX3.s:14881 .text.HAL_TIM_Encoder_Stop:0000006b $d + /tmp/ccGFzgX3.s:14881 .text.HAL_TIM_Encoder_Stop:0000006c $t + /tmp/ccGFzgX3.s:15312 .text.HAL_TIM_Encoder_Stop_IT:00000075 $d + /tmp/ccGFzgX3.s:15312 .text.HAL_TIM_Encoder_Stop_IT:00000076 $t + /tmp/ccGFzgX3.s:16043 .text.HAL_TIM_Encoder_Stop_DMA:00000081 $d + /tmp/ccGFzgX3.s:16043 .text.HAL_TIM_Encoder_Stop_DMA:00000082 $t + +UNDEFINED SYMBOLS +HAL_DMA_Start_IT +HAL_DMA_Abort_IT +TIMEx_DMACommutationCplt +TIMEx_DMACommutationHalfCplt +HAL_TIMEx_BreakCallback +HAL_TIMEx_Break2Callback +HAL_TIMEx_CommutCallback diff --git a/build/stm32f7xx_hal_tim.o b/build/stm32f7xx_hal_tim.o new file mode 100644 index 0000000000000000000000000000000000000000..b194a3cababd2a9e33c8e5c5b8f57d345327a68c GIT binary patch literal 160408 zcmeFa31C&#wKsmw9g=&K8#0F^1i0h|2qc8dC^I2}Fo>8DDWZfyyaZ7cL~5-@1Z&l{ zTCh%Sr4FrHwSZGq5T{ykY7nb9mR4(gwAIw2^3*5a@3+@J!@VRC+rIbxzxU_Zb=Tf& zuf5jVYp=b|KKq=|i>A%4F-_C3F4HJAoSI>5sq?VOKTXHtR?}}KYI(>G=oUK*)yS7w?c9|tciGNR|Bj9~8)~9+vhtFHS zt@vQ&IkT7NRA0WlxVox&lxXX635;ye*!V;)AW{ zc%bJu%X4OzSN4bvsE!;oR$m#bKH!UF&dxmHc9*84J!o6<0^0nM$idbn6R4|x_VTI& zzN{mq$rJBt9*M(4z^A`VfoYp z8*`>MKLM$pr80`c7{n1{7*3g0E7MNMtxSmx<`_mOiPb6b5=T;^zhr82)oHV0>rb=% z@`KL&l0})*R>s+xt)w<2*jb|N)KZ_&QV&C@WoHI_?Q1FNFnzwo8lb+!pK{1|{Hp2E`}~S4L%0rBUI4E0@`I~p_wwGjz4}1N+rMLrKWLgATg*Y# zmnhBq9VVQe@w2{0K@377(? z0#pO00;U0K0Mh{z0TYajorZB0G`z9hEE~1Q($;I%y?<{#F@M*ls@`oke|$mJrmBKA z&&REcH&x|ooC&-R^fcgA^_!}K;M+WWQIxMOJmtJ#^1|5 zr7fIuv&JYLvu7~Jf3S7+-sZAcpMS&neKkGyUl&W8<*{cjV9#8r#@KI`glop^4Ap$z z&bf16GLI^5=@Vs>p)8Gjg=Y|tQ6rqO^M5Yxk7?>GYgk#r$`1d!ml7o!#wz5stB|W6 z+wLhH+Sa2cx2B+Gv#Oh=rET|rY@D^OZNxs{i{_x#de*7@y{L3gq@`)r>q{anjk5}u z^7r+n#WDYlvxkROgc+rk9oMx+V!j*ls(*@>y|J?Dz0JrMJAF6Y``IP`I5}tx4(u`_ zM%l;68_1Q>-R)-h!*=Ld*gy>@F6HmStUZwxlc;CKMCw^F&e5|%d93vLHZ!~zefP94 zX&C`d{uVA>(lXTMY}OV%2+l{_Z)q6}u3K6Lf$Nr*0XEkb&2=lde%by`OBh`IEnNCe zOOegBUvpgzuIt*DtSF$y75UV-BHQL_*0xPPc;T*TNOQAs4gKKV8r?bOet%79<$R7f6)&9g+0l6Vm^NtdiNO0y7yq!-`Xox-~H{a z3cuO@n8N$oD;3Yn?X3#8!TKZPsqkpyY36H;raHEY{k@kE^~GN^M!(B|7>^Zjp$r>hQ4h?-?R+IY8~5cL#e{}uMc z>K1VyW++;I&8q1h>_a@U2Hf{sv1@B!o|zsRl(X*-@0%UT+1c4CfHXh`b~W=>teWnP zU8jEcso(rFWbd_CFa!FN>wp;L<*Y*y6 z`?N(?Tv9clP4E69k@GTkn)rQkxlwj-kBJO7DT-ZR^n-Sfrv8VbP6l;a^qqE}roOGH zm7vx{_q7K!b+4jM0d;!xg?7h+RAoVivLHiQ;M>DK=6>pS+d{3MC@ueR^_LOksQ!hj zf4JKbblBGaMO)u)TmC0)`P;VDuW74)@6!0sTFk8CjlCV~y*#(Wlb+F*hu^fevpPJU z!bN7pd!9FTb31(LS>W@fr?*97XLb0%NiRgmd9d=LCf7)FI|7O~ zpm_t}<%~pPhy_TkiQ~;sycwD|1HAOP;)UGf;&{z;4{R{gN9@Tx=vl~eYx*dZTQ8FG zaeHz*Diu#<`dF01svJ%qzh~7>jzs40N9}^;_qMp&eQ~uX+c{P|hb$6aRX^ydx9X3x z9nZ{GeV5{|wE1_cdf2W%($3hwWJULD!dej_6_42}p7K;Y6=3CZH|bRo$yFeB8Sq%f zPR-o4WRnSfkC0iLKP zVRu6rlQpi?c#6hV8dqyP1G=L3dt;MlT~(E{>%o-!rVC^m}+ zLqb_w{Ue^gw^n&RUO$|=NcVkgEZu^Pa^Rt2o7ea84V2qp2+S@$`dN`$=3inEqyS9_Z;k3F$CCANNXy5e8Wk$6+Lr7rg_F(cKByohx( z-P`6}u1;?jMe#I>vzCB?^A^BVl=FeZtech1_wvbtPk-6>atAjt+OMYWkS~={%ek9@ zY{i_%499%N>{SJ*222G^1JnSf1LSFg8J@jg#g1du^kee7_fPG;WA0C@ks0`WTjC59 z$FgxZ40yAfSt_f}#%?cuPOLeg@5k)4eE+)gy-|8X+aX)JQ8oonz?`Mx*wwLq$EQ|q zYIf$jU+nVO70Y|Hl*Tfud(A4W{AKJ{%c~D0N3yF6Q2R^lLscuRE^F!K9m;ZcHctBP zOlpa(#F?8vYk2i#&HZ9mEQ-Vm7k6jlA=}1ZD;p2(`ttA>UmQN{^&UQ~&jLF#JUk2B zsLle@VmK-5AL$5t)oEaM#_Y_vb4Q#8VqLt56_S)4>8SLo)4;_%4cy@2Y2XHroIbAC zr-ANsJK2?tZsQ7&ok`B%!N@+Ij?_Ve24w(p0fm6RfD*%qsk>6RV82z$u}kT8Da9`N z?Gm2v!v=gmA&P8?Rl$=A?ud+zYg&CZX|{Ibqsv;A{!1^tv@c*JUw5-mPTBBD1l$ezzo2RucekjxC_J4fC zsN1W&ZCMXZ#XZ5hAE%O@sskZUaYu)Tr;?2H6pz`FVrEwJyi=WGTR9cE)SAsx+nl)! z4X#&_lw4O=R{$snOfsH}&58wM&OAmsLf%bk9`A_B?2Xxf1kb@rJ#%*;%4O#ICvb7r zLSC5-O5$8(AISqr7LPS!iT=HzYHi!9`!Czdk@UfRfl+#vwQpCag{d)f)A2FSrYmCJ zP0z)An^Ko2Z90B=@}~N2zQLJzp62T3uAb2z*t%+`d54U*W}B~KAlg4@wGvyp(TN4gr7N5g5|9^3C&tU@(~h#p|X%C zdeC+sbW?8R< z@vqwH!3ZJ;FRI?uoKx{FL_|_Y;rZvEKNv6$Fbgmr&|>V44cmq@2JDi=bAN0vTYjgG z6qI8lw$VS;$aP$~&$qM2%*Wbqoc4o8H7Pr!UDxi{?Of%ph!P`w7up#!QoGG*M-R6D zSlV^%8r{w{-RkA4yb|qP*HYW)w4(>xFOYU!JGb2kuWo1FvaGQ!b6>d3+m^B~bz4T6e@{V;M2ZnEMLr#{KU(%N{9U}iwk&1O zv$2^mX|3&Napi(5d;h&S1sT_NFV01B+E$evw}}I@USmilBmR&s<_tsS4TbhrL)s{uu zQeSH>8wo3`_oObrJhofUKhJP0%R+4x@J2u)@WNJIrr~H;8++nZ0Qd+7=t(*V|K;f7h0}H?HHHe_!+>{C_e>w z0`M5%(RQv4nY-d6=8kv8)`xgH$UE>}tW}iYFP=>~xd2bnuK4~`#lu%itp1u3&5ph% zcKM;uXXY1pe~Epwcd@tS@=ENR7c>5Nug@4XL7p+jk00L`FaR(FFp|$0d}}j4f0v0f z&B~7Nwq^`kqj<|#uU@?ba5`WG;4JV?wt3&j^G&5)`y*;o?Aq(7RoS(@s8!pw=kX-Y z{k2&vF&l{uo>?|)6W(@Sfp<~!&!{?RRLx%+iS@VNKn&CGj)v%WMuRl&uiqW@)9;S> zj*0J%3hcKG2388SO^*InX|0StsqmEOE`_V2k0@LneX#xdSjw!<-!buif%jXu6U#d$ zK0_oMCf>a;CmO|u%H@$*$;|$G9BFvFcI11u`DYaCv31sJy@ksd(ih(McLe+N>C*#{ z1;_&w8jP$-QFZF6#`K@PF)(4mgfL(rpaL-J zh!}VjF<^XjIre2{NBL!!T^0kJ4LBcgNn8~0Dc6aD{c%z7T3i&o6c+{0DZfv`zMSve zJUr92 zhZJRsreuJ!RZ*&_N`h*`6y`gb@UoJa%33LA21j&RBNRdv96Q_^xsZhrsp0+EN)a$Td<#{$%x+^ zRjNcOU6rPwl%h&iDEU>X8YOyS%uZ*`$ylX2|gR*~$g|ADdWs=vx;cGZ8!cy`r)+kVZV zN#U2an}g*n#29RJ!*@ja~3kqbMFkKV?L%IO$uys7@XQsdh+epKUEjcX1~c1d~- zk}F;HJ*ZD{)pw&_<*Gl9dbO*LcrL~qgj-rx&1hTF(sI^}jHUc-TRJ#4a(K*sOYz%Q zc>`?V4Y28oqSIzBJ7PVS#hUH)Xmo6DmACsw#}8WN{l3w0xn0_b65sI~9jz$wE&sRl z$~?~%_v`o5%E{q7TWVk>e>0Ze*)mO8IcE6n+RC-oTk0iyo9|NNstg}!8HXMRTE?OW ze>tuR!{66E7U~{&hHKuWdQ1rqUNHnc_?xkG@QQNPqjGqueg`qb($TQD`FyPWjkuSY z;o-`@>Tsw$y3f41{!mHB6s+UFc^qg@s28}}$ag&8`dE%@-RHW-@7eFs5zn=6V(pvZ zLx4{J2LT@;A9S=M)wnL4YsKA*LW3@n+;HKA7fu7r0h}bO6yFx@ZLSob6c5t7%1CU~ z%+W`cA-aF>o-t$+^!htWCQh6<2v7kS0T`oo z+@tPaywfpf@a`=+gZDbg89bAdoWYYh$r-%k9hozZ?R}2zeU9yY_;r^NKDPI9fAwbV z#*giN%%o%jI1#pfbmKJD|VHbE zlz!$Prl0lQXF+_n;8_r#Ec)pui{7rC^#G-%GAd^dQ}kI-l|Boq)@MP}qH+>Y6MYnC zL0x@sEKldoS&%%J$Dadrf4WnucFMtl0|%x9dI9(=OeX0o`NrOSg(p6P`EmZ@7++JhI1d{n&_YLv>j-(15NrN>W0L(}#){)dlM^d3Hk|HXSYFuYUFYv8_ zKEe8}F7w>u@r3ilZccdY@7CpfBQ$8G8hP>=XPhwvFaj`EpR^>N?{ph!<>Mg-r#9op zjVlIJ0EPobYgzQqKG&(uORiHJoQtbdn~jJ@18*JVsUO#b;hkUz|)kr;_D3jf?_D0@P^^^2O#y zt~oR{WA}E?p!{7Pygg37Smmlgl^wo|jiESQsW3WBoUWX#MmuEw{P`mQa{%>#xr|sy zd4pLCn5Q^Ar{oQ`nI;VjsesHVu;?2u;CpgX-f1D3d074tD~F+GxqTe$R>Emd}p zF~h9$le4U|4LpBG_y48kIPmkgaOq!KM%(-ohFPa4-*BCtvy*B|KA-0Io8hupvAyz&^vcWED=tUl488I~dgTT5%JbPPFMa>@u}s&wiSrjA z)~U%M^(AoPsY&O5R}g=09~#299sZ7Fyx}MVj08+HxT+)S%%oYJQhe1OV5*W)Qe9nL z1~?8d9xz$U;rYiFCFgaOBOn=+{fe?jQ+WOnR_7njVBN?UNY?7(8Hn5snBP*Wo!Q#)eX@gOmStIXG440IiGkg9UPNXak@*6I(nQs)G zv*fSxLDc1g@;xVa;sYn|OG)lG{|>)+?6Z6+QS$#yUva(2TSCUm!q3)!frtsWF=E1L zHQOFCOA$3?)74)?$iD8|_xgs6ZR;#b2JU}pyKhiV+m64R>FgEVV~)d{$6~W|$ezWW zc=@$<#w585lzjQ>_{DZdHop?%Uu|XMgabPyJCd+2TxX{y&Q4|BFWTlCG_#dOXh`waL<0)PuSf zW_CJXokjT&HHW$O9FDi=a18$LY_u)eS$i+ovlwyBBHpyydBm-!^Z67Gt_8f`4C7rV zz5(FhcbND-L1*+qquP9fCUrWu>>W|>8Kp!yM>EHBFvoJX-52NC0|3JSqX1(u$5#Gw zq`%zm%)Fxse{ouikI9GC%G^LzlJrh8i8;X;he?iz84+vlYc;Uv+tzAu#lfa~V4cx%w{4jdV|TYxy6h3Z*UCL2W$}9k zHJ%|x$EB*5WRM@>Z?0<8IBL{5rX`HSUlZ77_FuZ6b6BnR0q$6}BD8V;EiI$4Bf6z! zBz8pneI0-MGoog2&6r_wzZW@`S`POCPKI(aR}^w0N=~toQ{07|B9}d4nMgeHuH(qY z4yiwOV*N{Nut)0udAp}Sz8mQODd1z2{{g^S>W{V5A8V;UGERT_ZoqlXWUa38SY6Y* zUR}ydD(3M`wpJ&Eg0=@zX|{tvIZo2m>0 zulR8J%w!ZobCV3?)I7(LR>>1c?vEyqFS*(T@+5D{1u~OX5_$aZq_fRGDFZ0rUzWnQ z!02ql@cya?%EJndgCOtE*>z;WB~-T(KYso|oYpSi|J&iDSz41NxJpt|1h z-eP8clROb4nCXRtTdle;P&)ut$L1;(jyHF zcbML*p&&Wteb^h^1`j~(FvGjUYw1OOxZ&Mt)qTOwII2gjdLVcM_3pCjp+E!FJZ4oh z0@J3W{*9<+&I1NR8&}4W`@cPTWpF@n*Ww<$$ zU2ek68=)Qe!5{EHmkG8}-U>AIh$cmY+320Voq;_(q{2L6q<_xpC|&iX&+dupSX~XI zUjeO26Ld9{zB?J!$-0`6{t#QMbTucv7-LPErmOksufn>dS-M)39)-}sYzE$(@!Mx$+}u@c(W+F+0z6rJ>aBeW<7=zY6Zy%^+kFxLyu!Do=|U2 zUuYEk>ILyj!GXy=1qNPs=i~=4}zR@O}|rAbwYXvGEvgCx>}i@ z6hifSU7eafgMDw*)fwsen7X8&=<4kB7@2R<)!OuIdgNz)B=a<;|B0=)^pRPdm;Me# z-KMJxj7%T1RhBQ?JPDTM@CURdFfP+~JSyJ1sOuLVp)3KVM}Bfe@HG_DPefQIN44vX z^eZ7bd4#U|(jSJ4lSk`nAl-*~Ngk)Gq4fI@u*nm3H6#6AL_qQkUClAPex#}7S>AJ@ z#!p>6ijq$Zo`UdB&qX99*J(~8{R`Ne+^DO*^y_j^JxNys>2F{PlIQDcD1955Pu10o z^hNM_@)BLmNnbz8iHjd|eHR z(hGGpLzJ%9)tvOWZ1`mbo`y}Fu_J`46HKcK5Q=^+mCAzjT+Pes5b@6gqv z^ktldUAl@fXL10Kdl%C}8is*C9h`+e=}A=jjOH}bi>UNjUG=3u!^n7ER|DyvaiA~i zDh7T7)wFqi5ag${9y!Us4{oK{@6hS5+G0~^{A;$@m6Y>_E%q$N?OT@E^b^>3zpiE& z-uGGmllNq5p>SyVJXnBblztm0{=e*5`!N|0>#8qUKo^;&t_Ok-(+ICs4+RUU)^F7_ zjFgEK7cjk#Qxg^B%FQNuh-rQU)zE%8%Lt9Zw3(r)DjAMN+CVadCZCb=92JZ(y=CC_ zv4hortZ9Ca{r?1RBeaIMq|ikudyJHmxZo$6-WBXaCaX`iX+F+AZ{x=ZeTt=Sh6-RH z`rLr~PV#iqdlUPR$?9_gMhoGgFCp6u_2dRE6veMEG!wsp&|>^%guaE}aOi!^v|*&2 zf$qso_}5&BXD6Rx2JeT2AaizdvpJ9z?!=h1lNXr-m{yRrgS^WnFE$5IohMQhY@n}~ zm;)bC^>FaFkez&*IY83-gdo#;@-lP4GN|!HCIwuzhN9 z9^03j171}8GmuxgQOi3E>YoEk&nViHjJzArOcAQ?H+*bUM9NV_ui@K|a?0n-Q{Oec zg{b&H#!tR^33LXU%p}w74eN6#8`LW>iGfB^N4TgLBP0T2NS#S4e_)fynMyh1*>;-U zmT$JfgMo3Re#@p7m^bsLeUT?yZ9vRx*rN0nn7eqF{I=EdsMV6gl;r#vh311W-n_X_ zlA6ChX!U&CFiQ~`y?y~FqoqG5&8#ir9HBar5*WC=is*O{Ye*alCC=x&ZUkHl=(Qg% z1aT6HW<%e>tZo#Y&w%s^s0eGo z9M`9m)icrF0_e-_jyXXT-w47rB<7HFq8=LvPXUa6uVPNkpv#)~KsJ-GR>hiNyfs0w zCJzyl1rTe3ed4T15o@NPeIh`t35nt}L5Pv4tVz=*f^aRs=yw~fdAqlGx)hX$KsK3` z#G1EzkI=4GzInTMm2yL!xZ&;IC$st==<{blUw;}p@9(W5C=X$n0T9K16yg*RCIgIq zbCJEw2ee{NN+ZZ-8j_MIexP^Uq&(1DP09u^aW5)vc%XNj8y@VfCgoRX|0O`Ic}Nt$ z3BoHRDmOeV#2{wP&o$96jn-VDtr-ByKu+kTwl!D8yWxs>H(ViZI0=0k0HXMNqGJOH z7m}zHe_x2d0^x1|R@VbuBnx`WI^GP@6QG;D5Od;(1--3>tR`SVZ?(EU0@DY8A{Cqq zdY`~);Fi1qAaip{Z?*6ygD@T-MlBTmt3X&rqB5#ki1&l=D}Yga8zcUeqC%CPKrr~E z^ER5ym(fzRk+b|tQ4Q1IaOBA^(Ngpu45U|!>d5g21pW(vzW>P-^jc9apR>-vDm)V) zi}dv(6(qNU@Iw++>|b4$@!wwZN(f6g1`&7$u@^jQZGBW@AmFG0A2 z#4DMgZWZEVAUq0y`sMIOzxU~$X*l>Z;4lbh6qi@7!FgDnxU0KoDAYb zfT%xHh>alB1B`yB;0|P#yA+=evUxo6zl^&)UU7NRZ1=b;MBI(&vk4%IhYIm^5cZL% z#vK*nhamh7VDuZntx4K2Ayx(u&DRUD282q0(XR$UYtGa|j)8J6$mWB#;+gS7o*6&n<3-#Z=<_pxD4s3E zzk={CiE79v2yrlCDh$Aomos5x=^=-4?>LL`mJF&4Ijh$Iow3L9&Y#t52HOzbuQ9RY zh`ejj=LeLR>H9NQZ@+J&XqtLBoYUthbOAaRaZiV)#{BxS;U-) zB`t&fZQ)poD+6^PK*a49ag89<1C(_eDXx#nY-(;Plpvf0(&=C@x7hNw6h8YT9d%rT3!*jA8U2A}zOp{rT_R#D zkcG#q|?m?qTJ04)=TBLik_p@2B8+Lo4NM-Ca^L)32Wb; zl{Rab>oy~Sm5W7KGkT7(S=Z12Gl7*WKv>P5vuxInFtg@IdGWR~VF>F-c~v%RIfLSz z1Xd;iVSOjB+Gf3r6ZCQd>rk8Z<-GAWYa564n*>%SRFV3dJjVmab21)CU}drt)(7&` z*3qP2E4jdbk-)muX8lFpByGR|^Ht<~vmr0VNX{th53 zuOV-?UU@vBGMn;3tn#$;Qh+hg+>Kj`S(+zLI$0P0A9Y7 z7C`hEd8biNDSTB7=w8nN^KXpR{khI~&{sKXI1H4vus?Sq)$o1ad_b=WjIRB;mZQ|x z<4?KDQQtxPMgRto#lWg@3C3`Y8_;Iv_O>L~XRpwCir^vB$!0_3@1 zMy`4;I0V8+B≀nWD5BOFcrE3dKBXh%82dyZzD@O?e)Jfr~wXS|jp((9|=*eOBRl z6!=U~`m$#K++uGwB7XvnvPurjt8e=pygO>=JobKZ_k-b z7oGts^FYz5yszGob0RtZ6NJBzD5*bZ6eDf{qIwQMMt@h18vXqsYy(8j2M31$8+O2k z0p<&w#fx1w3`Qfv{TgtyTD_kdo@c;Ikx&hZlN7zcV7<`9>R4Io4iY&fN{ zCTvKKny}MBt!5a$fM`LV6Dgz)P8$UflZT4QpMvlYKx6$R| z$EPUkbphsm#PxV?w&UjeU~x|j&-_ha%e-^5Rk9cl>Tw)+I@im&*-bQW2?*aHQQ5pU zTO9-43&Jl+JfB;Vwb}D1s|SYLLE<3TYo3=qk=?%p@iY42@0{-QvejWiF}V8xWXRvl zR?Tn; zazgfTBpw3cAc@M66S5oV$Oz>11@uymoRHl@PS4faU6aIJv%xS6P=d8@Fw&3^nF!YXl{ULa}$1K5_)D$=ZZZK zgw-UfXzrOcmtOn{2-lFPCLupd#pt^ryiTH;g#4^iDQi{)*$5!fT#%&>Q^%DU#%O>< zbAiY_6@>W!8FDWf@_G<11lZA>51Cd>+0i`2O|+u9%1yMQ`6M^dism!iL@Syvb`d*^ z<_qD5f#v`%$2T&ad1f@<41>*!IA|5kZ)B?d&fB2A4iHDaky%Ga2K(b!4>^kZ67@b1XUSX#PW{ijd2|a4A4VGb8Qa6U~=0Jyp6!$(!ko z&|@}mKx&kgnbR09smQdSqNV5_-heAJmyzQ-5HAN5Eym5$oRX=|M?VMQZzS$zYMqj) zQrhZ)II{;x5LC;k?grr(fI<5xb82QDU(gSJp(iz=Ttg0 zb;IHTX=Dc)d0>oe#5cSH&5gX}-<9Fa-#CnHA9R^M4nmFWt_*e8DJ(^vL5qy+?u_X? zo=G2slLj=%-SeJ|(VUeJKx_lZAhu?xso9Tv;_HCO1aQ#k$Wjz&soE0o=qvI7C_H?N z>__1nEbs%8*SRMeXvP?7(_N-M4{~Z5h(EDSot~j?^wU5s1Bj{9GZvB~sT`J(sBZMr zGtQ=|+d#Y#Ag0a~Q%@U$a05g}gG2d^j;7xttthNZL*Z5w_?82nJSCato$P}p@1{GR z`p488WhyMg==7*eHW#(r+ z${ETj!w_YFzL#Ub<`+HG7PAtBNhFS7>gs~Gt*2fqsNclvw$3?qT z^ZnUH+pcN<>ChsFK;t7$>6a+*VJi(U3(4KYCVxVyg`nE$WSqB>5T}KvubA~h9 zgCsv3#6~0p8P2{mm1O3D+6a*0>`PNy+si>%OX43Hi2KqOb9a+90tx^{pON@l+HoYl z1H#WpT$rqgGZumAz$n9b5776osF-i0sneVstnCy)-?O+F-W1{~AT*Ge#l`%V5PuHB zk4bzBdB}WQh<^j&&w$c(kjZW0uaNI>U-qm8trD|E+LJEY0?;@UZz!6ciD5?RWt#V6 zMX%>BN=vy__eg_}ICpA}(4$TF7^vv(9-rtQlXVX@+rx|!1Ma47mlVv(B+kmUu35=I z_kPEL__;kR*QTjw`V&B%0+3m`Hch?4x&?%50d|l*;8yDjvKKX72U%$=Tt;)=i{~%- zk*3>bA}b9v`3lk;;WG0e*!~8+<|k#aNUentX=*KGj={4cK+GJGrq%-ftr%k{KxTiG zOy3P4{E$R7`=f>U3J5QfsAm5-A?A-ooB(9@#|ZH}5LN<8r)rb8!4!LaVUFf#`fg3P z=I#Ma|6@FV$v#cDhmOTN(EK$+^V5*CZr%giuc6ocNx3!jPebb1=Uq_u0c7Z(hGsDh zj2nm7Gyon(D38xWH``3iP*~GfX}UE-s4D);;`vJu-0^{=X6U*gEV|xh<}+a10KMjQ zLo73|52?rB+d;h*AZA`4QjfncgYYy!X6VL{TA#zlW4{BC8TzphSAuXFiE4&^BE(;T z@G}zC`uwR7dtjI01C%n6G1wYliam79&}>a#q3PBP{Z!L0iRUk|X3jlBg(lx6nj1s$ zCw)(%tDK%~42|QBRGpsr{V1$WVEw>mT^q8F8V8y`=X3K+mqQs&Ct@__$O_A$GehcB zXf>#30ZPzd(A~~WWG|Mp`AVu2JzK$YHKqK?mhwufik{t|?gYq&q1PQgwJ;Xr3@y%Y}*5w@SX<;sU`F>-DFvd z?I;rVK=WSa-S4<;-VDYWkYX;xE=U&pcT&}2KNHj#K=#z%NmYyeRuHxT>>J!HbhD>D zDlbFgQlW}qKNg5N!=?5*sC^D{%)w|EwKG!H4eCQs{{j%TGg8$JDswUt4?rS#R;r5N zNg#|NQRSH9g}4%g(@9hjJX?rA2H{5}st7(oh|huW8$f9@Y@x}yFvT7UvU-cAyCZU- zS(^f@d%K3x3bs!m$NZT+l-{XoF&0%~KLwDX^iEZau^xmufYKg@sJ+sy79PykbXzUj z2bwJbXm~fp3APPj`zGX=XK-_(vh=$tDrA2G>h%Co`)e8mxJa&`K_?d3~*n%zFgd|7~^RbW9MHM`#e;cP%@9}u}H zm!TV6q826H!Erk3e#?9BdqHPb`P}<3`kOf;ETi8GsvP$=sILPgv%eRd$yqh34dV+C z_2WxWJ-&oN>;teP>_cq>w?5pRs?SE$F7yJ3P=)VXg)O>(kb9INH{E621s?1wA=sQh z(lTy(P)$}0)JA|9H$ABCjvs*VHi>U>YNiKI;RfkIGi0+VSG9W3rV~n2Z~M*;%y+@2q=9M3K&Np!=q{@ zloxP^;yE^Vk?9x>9D|)DcZTPo%Uazs=!lk|>z3-omXcR=OPnNl@kQqG!vSZC55S&x zVVL1KnZe#wPC=)piD26HijVo z7MIeyVBOQ`V166>bWwUsK*iN3puPtXrMCoBTrHc9FCGD+^tOPCs}DdpK%$zEp9j>0 zIYT?SPUb*dn)xdK0T*pt%GDbEC`J8!)P8!D_x` zTe~r!-amc->H&aQyD>10F3OmR4}1Y7R!ZeGTfq+b2kDJEmwY}XR-l8qcC_VyW?*I}^62fYsv~?lS1T69$-B*wxGA zdje`V^dhLw(zFV&&>2o@nw^0TPbWKZ+YFY!Qpy>&l&6!`q?8`mMPOmlI~g2S z(wh$&hvY~;pOP24BEkLGYVY13AC(Op{4}b*cqGT1E zuYvF?AW{x}>cJX1mACmQ;|_?(?V2O(J+elPNZ%5Kn9_i)7#*`c(pmG(ajqZ1~Wx62LSNrU1H1Fx&kQ^`J{W zPo|cjgL$_t|3SZ6aX$d{5`f5m&_8`8O!+eiuK{E@5Bb%s*EZti20-oQUBf9fuS9CwDCi5xYGuQh2#hnTuf%F@nT5nrHxCd}#+9-k0 zqfZ-GrNEB9F5{Rso`PVLPk7?IzCIP@Ux4~9K#c3_Q&E29Nw`MZG3`6 zYSz1KVA^;Etme744fS5N*ggaG6M)!I?^XMfqEis0fUeTU@(hS7bjfGh7>5q#ySDs7 zuS!eHK%EZ|`GsDUmUe)!6(GYYlHm+I6*mjOk!hnE)|*~$eA-CIldI$cuh-da%;j1; z=!s_?XR{vkIJ=F%lXbWLBOPckm^S9Y0J9bRGEuudD)(Ig>N=Xnw80@di~IdNboic2 zN;6n)pp@5bDc|!bSHA@6(*Qed>;{KBZE#4Aqh0LlFqf>=;#**DjtZs;>X zod!_fvvLoCd**)JKFv&5_cuX4o!z(F-7`Jvx%+BRzXOmpoat%c8vY{)uaT(MaHeO; zBJ>~D4AB6YxNMJ#!^=Qe4=BNAT;0PlCg+*&9@?Mu(_X3PIF0VhLm3UhMEGJaraf)Y>=Pn?-87|xPIvpn?mgzII>7&72_C@ep7aj$$ zcc>%k14uFKPeO09SS*~6f@#zf*{t$ml#4Z_TTKJEUgz?l=rQoc6fgy#>?1DJbfCD4 zVxWtNEXu4Sbg>5w#~K22BN0*{iVKL?4w_KUxU;+_Y6Y?1-#yN`I zKx7N+bU~Auxn?l{d5UPMD%KOlgi5qls6?VOZm{y#Gv_OwxkRn1SWhJEU9S5bV1aJ} zK>yMeMQ_unB^m=z{*$j}Z(@D6G!xB9XlA`pnu+EnG_x*~Q%lsE(9AmL6}pMO4{+;d zT|7`r^y7qP)_)2>Z=x*#cW>5j2B4YfR)D*i^`A>K(d`M%tlufkM0X`Lvwn{>6Kzds zW_`Of6Wy24%=!b;OvGt)n}%vPR|VP->_qlt$zOY@$&&D`BWeXGxw@J44FL2e`aZzj z%=!JL= z-#|11;4#(&IND}iZUz3XF4OL7b=fkK{2zta=&9x_l^5Ox&HH4x#*R%$SO1nnBF| zN17pNi59@cL>wnZ@DJ zB?{|_W&yvj8Nd4adMXx~Xq+lG5J`~F zC8GW#W(G7hJC&+Y1srEc#`tC7P1bZ_jGQRm_~1jLdR64FeQ~b128qK6b&lL_)CHRQ z6abbGJ*$cfh+Y)xOF-{S5x@53mYo7BWC!d=PWS)#TS48s%r#kxeQYZf>)LS$~YFZa~6 zg4(&VK4^i@iKx&$Ijpw=;--YkgxIAr+S0i)N`$n3=g4%L3qW$h^%Wyy$0J52#4bn1 zB-Z)JDnuI57=YW2tV{Mwm@^^9DFdrP55q8`B!F8Ks$Y4zhFuJ1cX!qY03e-ca6&Wd zu5ol0d!wZ{5tF7{xRXR{830uY&8+jr0Nq5h5}Hxf*9>5`#?6hid4xlOGMOJA{4WJgtD}|9--Lz{~1GRY!3i@ zL6iaL+!tJiY<2Iv6tgoUpPcM(iS-52Omt>KGwYX0Gtun{&8*)e%|uTmG_(G+G!yMhXlDIQX(sw0p_z4#*A+k> zlGJqrez^vSX$8DSMEg*~4k)WL(MlpZ~kj%^YFvMC3025184Zw4BUy$C-U@KU&~;DgR^n&kTIsphbu01P zajkTmMBF(66zwa75_1G`r9@!{@l+|>e5$}tz7nod)Zr+i(W=-;RH=%!MEGa`42?uf zRk4<6l~9S+3YCb8!An%7inT;ErOWt^Gf9lG-&)|2$uXv`5(>naCZc8lqKHV;HW5*m zE4I*>aEXd~XS{Q%VhjM!N<^Y!F3}pH5{ZhrjtZtxby+T@L`EsaiSy%=xo}&-S6hPm z0D#*utc!hWJ_aW=qiSE&%4sLwAZ4bjuXPoJ8&gj-P8FMoCJ2>?xdn4T#NmRMXr54s z<_nc*fl!IKcEC#{5z|DpOsGU>sA3ZlR~C4Q#M@0oj3rQsE>OiLq6>ve#36U`Kn-fA zSAS3u6+|-9Mj{?0fJ!7|Y9v}DR3fpyk!ZP4iNyLwqO*lcB-S?)eN(7JVtpgg#X=<# z>l;y0mxF6XJbGw1v_5-|Tq%y|HO@Ej3YuozM5Nr)p4vyoD0GcR}LsxKtwX7O+>al{fd-z5#l<;0j=9hOl=^N8LKCk ztnUQC2%@I}Y9zXu^>%3{>PTp2ogavxH&GtI-JA6h(o8fVp_%n>NHfvWgl5(+mS!S4 zz%3lA<1UWGV_dC9NM4o`FU{j4);vCo2VK+y$pT=8ki!$7kUXkgQV2UEoI=E$LzMH0 z^E4eO?#e_BVMat2H5~oEC5{gjVXcc})w{{gS?l9iJAJusN#)<_I|dx_jw?&I!cw;? z_rPVH9l4I&{GFAHL4;T$$tcHiCtR^ed8LkMsVe?2%$<_y>WCJrF?N|bCDV19F6B!V zWE*C+uSl4Zfa{4w;=htR)!mL6!JUCvm)u#`eeSI5K6lo2pF8Wi&z*JM=gzugxl_&A z|J~fleG2!T#N1?X4?@fYi*l5>Uek#`(sbfaq^vNKr{V{x+p7w#$g@Nghy4r@*A%Ek zt~?VHDiPIzm*}8SiD-cPR>k@uX(mDsc4DdXON^;=jA^1V?0~Hlkr?CJ?$#{>Rg7sO z5*2kUb$*G8dP{|}R^I}t3!msiL_HC8xtm#EA#BIRMN{JrMc3+raYQHe&FQ^(!vdBO%ktiVYsbVcrxloBJgi170s6?Xy?$}~|jB2hW z;&9!~Q1n%oJ?!z|M1T>=pqq%62$e_%-9+>~p%TfUn~3fgDv=DjiRcePC6Ylm5hW|5 z>xg8~P0pa}oIy9m4O%B94w@r{wGeugmkh7o8lF37opIJ%<8(JW1Fp9Q>~3~OUT=-u z-R!ua-g1Gv+3`iaSRGHO#XwhpORpMs;M#D!S!?lkw`87&kgr%W zcFf3uGQxj2I?1wB2fKNTvG44}yw zK;2`Y$^e?;2B1Tk1EAGM70MNgv7U%Fy5od(h5)iQ5p8xiv%XH6iDq zH#@_re+*6bB;VkY*wd+1;3H#?rNSCq#ZunH?K9jhY(&*D#9QS8K(Lwvrv z8+5)C8iIC+Av&mvjYOXcm580=_N)P$I2R>-aRCcwlSLwSTfu+TuDhE{4)|dS(Z#CR zNOYM{iGC_nqFaSZM6q%9f#$lhP)1Y{iPR>dONB}#Qk#fw7AlcQ?Q$&qC+#qnd~n8H zJy63Kh{)27T~;^AHFZSmRp*n4#HczVnU#}>iq%l-h(b#GNkmzySVzSFFDlbGiDYCWxQ@?{UvE8vWKplS?>XW zZlVl;yEp4Hc};Pi(Y@)Jd;oeA6$0G7Suc`iqCN@DtcRtUs5qgS^%7|&8j#S;dZ{!M zF^b%}SudAnqKbrO)}zu)G(4f1b^ePG7#Pv$gl5*qNHfv6gl5(!NHfvwgl5cV+(j?) ze4CiOot<^di}*F@hqb#Nh{x?Ha`rb!F@&x%SGATTFvMw66^7dk0G??n=rJiC1mZss z0IDOXfr97@P|==n6`?L`asdU&`ddJYzM}*!a0D%IELxBt#R!8SDdtp)kqmOG)Av-T z@2T#-Fbl4d+eZcz9%bS_7u}Hbh%Qh?wd221s6;;$DiOtYlOUO~b>bGOO+?%`fl4G& zn~1IwDv?NSLdm||W8qA6HWp@bOehgqy0Oc8X{o-8SgLr{am-d#tRs3+s6;ObmFQie z5{Zf16rH|DL=4?kt+*Dj@BLDw39m}g>3c+wfB_fBUI~C3 zC}F!4DdA-)Qo?&ud>`n56#okJffPG{K9VAS6D|hyZ~*Qi6wiGNiq`hUYn)@=#F5@5 zbn2owu;ACe+*3(YI-5$1ISU1hg{W8+8;MGVN+f4ljYQ`Nl}JX|h*GCl2B-)?B9Yoe zG(f0CBDINVl~9R9YL{X83|KlFiz_V2(rs8y5N$+rR8c+6UMEx{acvXPR-qF8S{0j! zL`8RDNx^5R4hM27MR6@)-=9d4Cg=!t`gRkRlT^1_O1MFal(1cjl<=?= zcK|&q#m9i2km6H7PfHQM30D#7!vP31if@)85u;RvB}cj$02b<^xNgFdQZSVPptwsG zb}bQE5~eZJt_ZCuYAese8HdY&{|M-Xe=|!`!5v^6l2BLKUk8yTBkX%~JNYt7EIC>`HtS6yg z@U6m|SUwYgCL#{An~CR0I-7XwO!`2a9)0J>C)mjPWVMf|$143wt=;5Uc8 z-eIqI@uElz7bx~xhrO2U;<)%YQGWq9K(RLv4F-6P)#go3-?)V2c2z5QJD)9%5Y8f6 ztBUIErWM8RW{aNF4zyXnVzy{yXC}C2i!9yG7CE|~Ev^w*whHJRDXsxpCq?|aF4t^1 z?DYgqJ3zA&xrn^icLf%%BWhR zSrCNhK%&{ISW7fVs6@3wC8`%HQKL|aXbL1iY?oIQEf_5ky{c#Kr$QyVS*S!m7b?-6 zLM6IKs6?W#5v4A#m(hZRMx{bI8TDL_TES$6hq0N z6xxck9+iy6+YLViZ94$BaZ3-1&Nv&aJ`Ns^qV%p~&sPALLC1}Cj-Wb6P?sy^0Qz^f zQb1N$IernRL~@ATL?m~#TB7$9Lle>as#r@zvE9VpVAWhlBvKn4sdbLjMn`I$Bh`*D zS&?i=oDfU^M+Ly63vt0g)fm!LWc0ETrypGc8ooF_sT11*)}nLw+g=!~-78Bv@H z2BZjXaG2wki#rBx0C#6mo}%ngI~uZdGHb5;fpEm-Q@0MDKtV?Uayq?sfQlF+N>QV1 zBpRoRwM27;N+iyyC8F3)?6OqsQc~-PD9%0Ej`%uDyt~=aQ)lUMH(Lq>S3>q|Wl22| z`?|tlKB{78+#IoMLI6Ar5@NwIt==&suCHr;9gZ&NcNxTX=6lIA>d}%c34V0%g7nTO zK-?_S@Z0$n0vR(&M4KU%NWKrMC87{eiB45T^+A3!ips;CJX*Q~DIebKELhP!;VMNP zh7et=ij73K3YF+ip%OhHRH7Y1C3;4vM4S^CO%zhaTB068C8Awj*^mC6TxFo)=0qg+ zH4*(ns6=946VXFLB@+9Zh@KNFk=WPd*jMM+*A!=8!qbJ^Cdk~~ZG!(2?9qAM+N-NS zoy9)_jUhG>@xFxFAZk{{CZeUP==#H*ChqFj2$iT+6`P1QsG@qnyGp1;n}te5BRjdR z1{8;SMiq`m5RUT703TK)(aCDA>xlMSbFJTWv2G$rF`GnL02K*Ak=IREHo$3G2m{?W~je;VTaqnj=NV1m_I z2Ssq5u$!!j#4W+IXn6&Is3D?y*S!Ge3_48X@;R6wR(53Q$udK(i;LMGONr=eRcs=1 zrLd2LN_0>aYl%J)DiL)YU9uXinAKiXbTvA<>Znq5xjtyEb9AY{C$)8Tns~_EUE+C4 zyumfx?e%lC!Y4$oR6PT|K_!}{ij72936_2gqvYN)hxbyNL%A!}LdJxfy^k zC8By)m|8l}YKbOxhv{9aeq@-YfDV@vk);!dxi*c$(dDL*J1;DSE+=31oV7$>iY}r7 zYFM>IRjSxXG*zfX6x)ei=&CL`1y@JX6zBG{BficO?{0SV)LDAm&04-j<*;ImvZS7f zeO)t9gR0osEXIE1f zx2w^+K4(``7q_d?&BwNNxSJf?*11+1_j6caM8~#u+ArMC!6!uAK;VcOi! z8E=Y&E*^*F@l+jQ?oe{nx!9wsSWEN-K<&Zxu_Egf*~vK(sKzwaR7XU4?%g}=G6J3?ijH>Hu zL3u3zqb6zvxSp0Miv1IwS3&9SUu0u*SC_m*tRqFtk=DE3bnwFe}uIe`4zHl3|M*ScAzBsAjJzI-TA z0`USV|KCU^Z{o0wgOD=~RZ#!vEK94TYX4ERWxs_7==RYXmnPILdWNQp9!sA%j!pD0 zFRMSJj2BlBuQvs$EXHD2a{g8N9IYo&jz#B*4X->wYO%4{6`cXV%NoBm9!tI@$Ev3Y z`w`=7O`uOos9W=7$w_QKKf!K`FHs-EkXMqRqs9zjUb6(*{lZ#rv!-{2ExlVcpEVw? zJzjiw$ZNA8^_Q8dsOg28&JBv2zC%~7EN$UFn$EKyUUvynr+BKU>3nkMm9Ohxm!B^r zdEFpL9RRX;K-c*_h`KZ%Gc2!G^($Zdv1pC^8BKprGgXhgYetOARkZb;0th zwSE)vvGpvDI<}t0569NC_`zEL|6f?oqh|0s+T*dpJ?7^<((paD`c@isbLu(E*PeFH z>Y)vdCyW?gbKJUh3ujE3y-=t_8_ro`3_W-CIYZA_zIf>AOO^~>bk52lXP$NDX+ut1 zw0QZ@VIwMrR}34v{LCe1oV)Zi!xB|}Lc`34p;J#=yL`!Mkn4yZIx~T@Q>9=sjMZya zju^g-=EN4Av2e}ul@&{{n*w?1@-x>|#CW&UETh2$05Uyq?#hxxgwWb zS}wV46(zbu#Gj51R7qLN!ic{Iie|sCCxFm!#`VYJ{(a-39co-rXIyKYaTTIjjVs#S zxM(r_WjR8*Zur+9*Ii@&sc{Wc9#cw(+4JQZmrTU+Ts6IZ%#1eIn{-q*;;T!S?++Z6 zjm0{YBHe}5ktS*jC7kqt7-5WxqmGU(V~@s*M_Oomr8_4cY2iQN!z;#H7Fx@)pR+6{ zCb({>u3J_OwO6uuq@P|S9&g+{J^0V*kPI-?-v?eF5SAq1XznZ2)C$*(*!n$j`rrQN z^h=hq#yCvRx~(IAjF(UNr~K$1WB-3;j1T|o`aAdWz_9;leEjYNEDbxg7u#zePGqKz zT9IMK&CEd$dgb`dq@JGmhD*F%H0<_>pQAZ?KJZ7v9-p}kKi+xx@z3(6nn_`#6W%3o zXE7_(m922D?ljD-pw{egoHd)MG&@%oLed2E9%(6&gdFxKTgp7MsF6QD{`mQmGz)3h zn=%VGvpLMb-Zf!=Z&;y{_E3KS#pI;yEgyi{~r5e%Km(1zdz3YLt;NZw~C*fZU=C+Pp=_o3Ia)${tWmnb%MI1 zi3@A}*=la#MRj8v0W+|(Q03!T9HxpRrFatE9-iP&qA8rzsbAk4YBDRjo=nW;f(pOs z#S%^#;^F4e*&)25M-|PT?+?mq7}l*@D&o2y^mnlmE};)PTRXcE91Q*cjwNz+Y8Ohk zbk*=)%733VcV~2A&5o`b)@S_pS@U>q7uK|O)v!7DYg#jO=uqoE)OiZ~B)`%^d3zuOC%@p&M5toTCMOM5#qlf-Q^he- zEKADvr}p)yaP`jPI{dYPW7WYQ@Ack(Q3bpAtoSE-Cnt^iAME9YD>xS1R;&?L%CJbC*y#u> z!74T?XUGI70Wtw&JMZP)d{KobCoV_56_FXAnB$*-=?e8l_Bn;OsQ6U&yZ)LD`91l0 z=4fgd3P<S4f}G>1JwJU)!P4)^C@k!~Zpjy^f6h@Kv&=<7!G5xuQw z>2?+U+j<>UM4uQx!lR7n;}d#y645*U4}13kUq!J#{(q7~LJttCfDn2wp^DTHLazao zCLutmp_oEZkzV8?qN1WAA~r-s1T0`zL=*)D%N4O>y>_vS{-0;&vuDrQ0N3li-}3+c zetALO=b71^ot>Sn=gbLPTzYhSuSbt6*rV^M|Nqk-y|96v4$9gKOnWIC+rhsy)5kIu z_2S99(`_Cjx$=ZY()2JK%8@I+P^qNAUh-}uDN`P?l($FuVy*!9TqimFe8*jt>oL1* zaQ-8Wb$&T3+*dxXyi`G+yA+PES*Ltlg>X>!w1L!C4h!+2WT{$w*+9+iY@%x`8Nu6( zXIs1NSHmttA1LYJvSE^*uJp{JQ7FEv%-K9pkU>1?^d8pfpwhXtz#FRCQz+!Pgku!TAseS zi$=EaX##2P5(TP~?o}nSx#QvnoT9b=mDJcmQD@oX4XS=3uX0O!jBeojh2TtxmVJCajTr|FOM|(S8R622@)U2v~Qc^rVC9bGk zM{=j%lBc|Gp2G2+`q-n0bZmP(sw`*RB)M=*k&}Hw2b-l29V3_X-!+f)5xJjrOYUsf zFfzr}|Iehvgo<^LtLxCQOOu*OOH}LKF?6>3FY8#mcYk>l(LYqw|1XEJE`h_?=LPmc zJ>)g|69+)~n&nd;Qx|$q`cHWP+;+OzUOD}a*V5~bMdDBOGLEZQIUZ#9W|z{7%CnjV zj(QWl-LP4IZ?f=g{)m!_t2_Ypv^uyL*CbC$ou6Cc}rTJetE0Ukhjj|o#Je| z#paYR7gttK+41}JcT@RQDEzCizOuiH=_~uIq`tDh67-eqTzXP0ct(9#OD|XM)D3i% z*8|FiPy2dF5x?I(K1-5#+u^(@+3PG3k9Q)w$k1RHk-OZOP`h9kd99*UODa;{ZK2Rb zwr`f`U~A|7vX5iDS~d-LTPjyc_lnMO;ZCe41Gx;)U5Phld9Yv0o(labf@~&RGBiyefs{>(uNzJorzvMgrVQ7VdXXsuG$lDQ zB~4S>N2WYHUz46OviU-3a)0);Ns5tW%Nd1x$%kY^#mFH(*qgW2;6hxVBD(w3JUt_5 z#edXlx@MO*PtMl6m(I3hdQnF&l6S9cwq46Ctx6SY_b<)fQ5$K9&ffU1%x;&SsPJa8tf@E*JXY z_Xlg(ecFDo!herh_HEt3`c_`7mQzSi{&LX}7k|56XXvxuD)xdSPCBiA8bi*+9G2Xh z#Cni%hY9bHVsB$k`3`aPr#PNXis)?gHd_zrZE^R;H%&^C=gIoexolEg6}>I$>_xIn zNhlwhq}2VfF$eG{-Kp_^_CGd$4f7r7iS)pewJB))TcIYS@b@Ig#m0eM??0 zh4f{Typ%^sftNKTRgT{BWF_>R=}l>!Too%xi-zu-FRLkyEe|O|@)l0va&lXfJIqU} z99O((k|)B&<2y!0XUgl?@;_CO^uSOVdGD`gT%0y-=oW7u zh`u>r+>svUPQZFvbDcCfE>+f`NmF;8O?Fq*H3E+-w&>$JeY9qe<#UE{EKk=hEt|!C z`l3@@RVhg>K0^y*dV6W!_LpbIe_Wa*hs{26Ag(4`Q4XV_3CHznLFcl!#x?b%uJ_2z zVmg$ySEYsHYe|2W+vHH?xT1CKZJ6v~#p7$ujVpT5e=L-JVcYyX&Ijk|`=~1mbkThc zT^H2`NMrR|My-D5^0q_S^KT7#&q&)sI+DAHsA=E34e6O8^qJWsJxV%@9Mc!sW7_X> zOiQRO4ReLO;gb;h#>gSVzLu%mHkI8%`lOt2^nrrZRFC6_bq={o_opkqNYAzG{dy@Q zcNm3bPta|n&mgpwHI^dMwPvBE($s9Yh>f&mep0xcmUboNoF>mZ3cLC~W|#hy9K_|O zBf4T6Y?fT$$XPt9#;a|{xAwSwvz%>NLEBpw$qL7WmPvC*ch}eb4=za$iMR}O&Dz}V z_FVp*BFVdQvrl`q@^j@RUM{|ab|q>;gp*Zian^5(oWbh#us{OAnQ7xnGC zh&I%hw1GYgF0B*PqJuVz)1!(_O12wW8(FJlXRz(vRkv6tX&1MFY~qjvKqBxwz|&6ka@ttQ*t{=}6I^+-wz?4b+v;dMD#NxO$$9Fm}|v&|Y@iO(pM8#mGhvJdC*Oe`vXzI_mzYXN+31N`-ZG z`q{O!Cv|s!(?D8HDjj@&azng36gJbh0d>{n9N$=VpV26%_X%BXPNDeFMJ}(9bP<`P zaBn+hVHe3KZFD|)2&Q=@T~yLV2`-W+efBMjf$^Q~GXmTGdIp*t7wYe}hIA%fxINwL zr+Cirp&naSC^SJ&it##aQT+LBaWCyC!Lr$XhejsZ#IiQAls1}NUyxW?6Dv!SoVzv2zACN1^}4g9n=`q{aeGB$kK@hk z6Pu#;(_1A%-G|9`boVqVa!3e#B=~S)*S|Z;!?(isMXYR+Y+8S93vAlBf}2*>YQ%oG zR`POYlD?D&AcaG-^<`yu$q_Ga#YweocZk=%QdEDH&|f9xN+HyLSbV6B?1%b}TlA;2 zHWqO;?Gw=lWG*>4+5J(T0!vh`w>+ZmV!KG8_`Q-)$YmFDJ5FI;j_m(BM`4##Oq1m8 zD7$mIq>{EaE=eB9X@5)5BzeH7Q^{eXgb*_-E?JSM+JY=NPPU=@%-3i;fgBL#6d7hG zlCG$;6n2pu5i~01A~_;xBx|q5$q_-L1Q*E>!S?nsa+K*NozWg_&-j-1FzKLjsw*aC z$aPiW_-?ut_8aZM_7h#F>Am)DRoBsOm_qt0PJhX#1a0rt9JvaZKfzTbBp+7L^X$J= zl{Q)xd918!Bz<1)$|x-PFBH~V3zPj)3zL1tFKnNz>%UwzEv>RGOLj6TOA56&XKlQ+ zIl2Rs)DwqnhR{Duk=IVQyDgYMEL2Jloxj=B@~`qapOC!ECg?FMqY?%in_M%koV_1<#l7B>bOpzI>U_csDB>*GyVbZ!bgg^rWMGysV#LiH^9TYh|KYExTe(fI1t5?B&L@!C)9 zxRdlV-g!>c%P0K^O!dIqUrXilwAvE(Oj>YUf?c=$|8yP0x1RA0{#1PfPn&L~63ygs z!vBIzruT#K@pt{RHQ}a{XR7kSVtYfI?A_x1`CC}Ia_{4AVaw{!C4E9`Z}P@^&ujIf zTyFVXo?KMdKi!pbAH6YsLiYNQKB5Y~)%gd_e2Noo!7VRK9P=k`J&VeNRNG1H4$#X6 zQ9FRP<@x`tDRm;fRUIrB!R`~B(Ic~-O?16<_-Q(b)hQY%{M;Ozsr7&3Oxhy%==+Apq=WK^>rWjIL-K~lDIcqq z2(6gkJ1Hb@KgGyHdwoW`R36sKePL3PY#{e9FdFM4*~RpD*HPX~anIW135|YoNFT6= zLiX0s-VR1SVPjwLCyTuGW6sDsKbPd)_|=WGy(D#A8o_z_5)oHPqQ;*!ND>*=Fu;MvrEiv4RVR6;-d z*Kb6D8nIHNb*1EkCMD$KSGrO)gDbVXA}dvXWJZBP{+-pj{;Y`Y6tP+QoO(0q2XNg3 zutBmy`l-fRG9)Qfx`VCMaQ89r{`!`j9_;ifiB8=}Hm-a=xo~_}ovE3=n>w)r1hdK=Vv!}fd?isE;IP4-_TK0#~0(twBU8jn->-3J3 zab?Bg=h%fdAKBZDLz!ilt#9YaD8!=ns3|F-+4h4Hvb*VSceyd0D1cYK!iZv-7fY%z)`x1M{dfpslbYHuy@kz8&7LuCYU+&X6DCg_GIwTHx2y?fKx+5Q+&nwG*0Aq@)IMq5OkbJK z&LNf1<$F`7PRg7A909PR|;jBwt( zWoApO(If&!z+|FeVjCMj;(7rF(q|K zuk+F}QhTQK@1NE;Beic@O1iXPkN!iGQj^;zxi5T5YSFw!%jD+G+a)!bHg0Bq$8j@q z^0MYMnbua~yh-`f#)=apeZtIHt(%NbZlhuLjLf_y@|{r~CuQc0mxRomag#dAw@J-v zo7H4mqX{#cj-Q#-WTN~VKRYvLLX#FrO$JCbVZ5wEliaLvd6Q>M&y{#W{&f2~oMvk- zy(uGQtkgocPD*~>jPxv7-gs#sg$>^#W3aTS?JQM)(A&cq+BS9{>^^z=U-5T{`RF^bNv)LCNs1BPBEwJU|qEr+MdF}QTBYwEYK!$yi8BlUoG@kOa0YKf3?yVD_KfKhlkBg+u`XG5xoo%d>M=gt-MlY~ zJLT8E$#>2*i~f!__w8@mzH_u?Q)f(@mM=$WIV40KKqK~H*~4fUe~Wt!V_VQ$H!so7 z8{Vke8U=b^xI5S$EJt0PD%|V?GjqJ7tfq%MA3Lb_seZ}c_6!%*H*5ODyh$c)mds1D zMpc4Ua;Kft8Tr%Y92q{hdA0PqTPVuGmfrLf&Dsn+PIwX9;NN)?I^ZIQnfdD2VhMZ z(yLWOidXk=%h?^;D^9k&+w9?{>((pH9f*ha=OnKc@0mG$e0I3zUYYi==N;SaZsQ$m z+?munXEsmqkL}?$?3bUNH`!hG=*5j!CdVv2N=EDux?cYAx4`x;*c<&$8!kCT&TzA` zyc&ATbH_Nj@JdZ(#dTTUA;~pXE=Q4Wy#}Xr?VA=Z(VNQeDS27bX1b%Fwp#RQF7h1X z%^5zyMJ`mks@F++rADut?M3#y>5dU;{iA9Wv6W?&`~!$yBYA7=U4(eYWDXa&We>>D zwfnfgiY@%ZnRj^cF8}QQ#_sHu<|^*iKYW%mlg3ZWG#Og)KyU4p>KE@7A?<$Z?jSXd z+9pGKwcs>r`?oaC#H{dYg`gC6W=j8DtXoSExi zHP~$_RrXKJ_Uz#ff4Uo{j2|z@x7_g3y!sg~S(5dxMY^3HE;E8FQ+1SzfALGj~$4 z=Ky#9ACTHQq6C}K!p@>I=jVEB><;^Se-n*P zwn6PtBBkqq^dV*(w_q)}1@o2=eJHT~%pNnw&&VH}o#kzyIrc^N5Q~dk$>43$Z*Z2TO*LsGF+iRMyu0hv_4%%n{YvI8YI5Z#=eTZ@XHCwP zD=xbaL>~B~wzk)@97OFl(nGpzXaCG9z0Y3c$PGv@Iax<{O|RdFD;wUiqzo>({KKT% zOyT3qkjc~JhBo>tBjR{u`(1k0h51>zdHT)9r@oc(`ks~=eL0~iLwY5j{y6LHZ5dp5 zMP4u1rtxprq@c(fQm^TyZK98DUWQ8@keZV>;yXa>Uk*+{5hIcyiu^?97RJS(!ghZ$iU0b%%neXAqpA zqv~GpM#5Vgt!Z@Y$PHBZ`pe}Q@4CrV+b&#If*a_lh1)F>bzqRz_b-vUP0r!gMH|9S z9NF*L`@B13ci`&pI&=6oNRDUWvzJ`Lc9m1d)E40#Rm&Za8hH`y-(>k$Q!-V7`yTJY zGTgS|GrZliyao%W`fKH7MVyzp4hkQ9bM3ieaKBW4m(`Y!D%s!aUdQnYwmYz#Tcpv$ zwezQTC!L6Cy~A+0js3m%)Vrsv-GJz;3?7I@UU=w^>X+r7)rD_gyb9=LJ@?w<&&$lt z_dBbs20N=hHt-5|7bT~-R-iY8H?6mTa370m57*B)2>QoBo)g+mqwOJ0=sn2M=brYF zMGKDC;Vu?=#q70n#9^k_kn}kb?cmkRuAV%gNORXn;d<+JnAf?&iQ$>N%P;BW?pd4W z_}$KN=ELC33>ALP@X4GmtHbm9#)0x7g=Gq zL)m??;3{%%@>W?^&TjJzdlwjSSeIVmpN4dm2c$+`PJ8o5-n+PqAAN?)cCx3=0r`3I zz|T8snI5UB=O)!pZhfwO)G7}!lbf_?5Pa?`Up}vY7VHoCk+%&lNhnd$RF&BK(ZAf0 zl2BqvXld-Sn5p}o*_$AL+SQ(*L#jf@Nykc|WD)MP#gB=pT&Bc@v8h zX@kMRs`nLx<;0>CJ^gi^@&`!V-lw%lwMp&x0;k4xy%kWPue7~%)eUK|84W> zUrIVvoBp$UM$Q-6mim`iq%D^eS{hoWZ5G-0^{*$@+@{lQm;b2=l@`Y@ ziCbD|S!lV`Ew-PXaNn~sY1BUK`VZ%~neO}(xeodlz|!3M%?hrc{#CHZ<80)yVXe#; zKJUeLwFO6(`-08)kI}6p4*y8Gss1r1C87EFVhN>FipLI=8a%V_VAq7^;p0(cnfh1A zQWE5x*2kUGlEMWVqkoyKyI*GP4X&uDwlFdc>l$lUR_2fFuaDUB-M$vNT>YzN%r`dJ zM!~$uepW3|zW#MH@7Nt#{#LtOzpWzcwD&ag=(uKisEHF=G-`2kxC#So}{VVFc7i{~;HgxAi*M}n07ue+$Oka1J z^tBP`k=u5^P51jsWZp+-$UAX{JpJo-k?j}R7WxZ%pd%TOe$o)`6Du4{@6-n zD1XXI&+z_FNdLH1#7{{6{8agfSpN#AwwabPN&d%5tk)Ey^AC~#v68Rz_muzcN6&`-PskJw%wO0H zl5Bte!h!h<`!ma{kSP+Fzla$ZHGh%7{6zxu7Y)o`)Z{aNT`^YvlxyTqNdAg!^!gSv ztC?Q!En+1<@+V}92c|D>Hp&FLe)Z*ltmH@jgyc*fU499(TPD!yUHOqmU|s)`f$2+{ z15wkLj4WQJPY6t(VBTW-(qgRSNB)FNslfE5BD1Bu(t&&}#s3MJGJ*Uuex|$%nX-ZW zvUYnd2v1cu{7PShGK9NTu%`YFwFK^3R5iTWq?vVT~*60+yO7wq1reYw!qAhQK zc#?|dYk95PN9T-{-d|J#jkPDlny&KO{|TA10_C0MXUeOPsS?Pq63DL_$d5dl>HKF0 z^3M*;UpOi$WIF7*9hd-2;|oa@4&>JfPJ!w5PSyVj$^IMNfAnnT z|Ab6RAV0;=lvg3y-=pUb?*H8a`P~BZrv>uU0{Pto`P~EgJp=hY1NprI`Mm=9eFFJ? z0{MLd`F#WV{R8>^1Nj32`2zy^g97<_HQ@h*OnM++?@;`okX&^{x4&M6_&*_YULgNG zKT}?X%=v-*;Qlo{kUu;y|A;{Th(P|RK)!!vrW1zD1%dnv0`rd!pZ3{@6hNxIq56!2YOLXZ}w}t}LUsmw%3`PqT|>4E&|f&7_){F!!rZVOMPM}7Y%WO4%2 z=h*4}R?6`wmRBK@8<;-VPOr}v+)u9e!WxpR-RSnpx6>zur^*k%(ib5!J23rhJN=6A zRI|gc-1Kt-)6cQf`&TV<0@GgduTb_SZoEMmW zeqj3ff#uH+OusNN{X#Q=^YbGzWvp3f=YJ?X*TV2CeGxK?1M@Eq1$PIxXC_YLn~{+88ALS|*4yp^^*|0v{Qzdx@Gm+a zH$0b%Wtl#3k?&2ZhUD%nx__^>%k%GYT)ZGWlZ$_fh{G@CMaZlPl()u~ z=il|X*uSc9@&0fjZvM|A;)e2iP53t7<-7Qaa49anEnFYJC%W?Q2$X+E zpuJq|Uq#*#F4@h$IWYfbJAYz$Di;q6#2*FXN#Wzc=5UU_2$?N`^0(OX^5GuOn-hKf-EOD%k7C;c)9(mO zzr#+yDm>MW@GE^0GP?rP?+WBU5XgVPmgl#}1A*xu3QYe{Ab(FFe~&HCzaHBYnEsK# z^pDu-yM(u=UM2WHA@f*Z`p4|_GsBZS7Jj8KLgtA;{8S)*IuJh-h@TC_&jsQGcKQA` zbobkS|8n=+{!=V>{a-m;io5=A7LMKZY4eC!&u^{6vAZ5^6A^2^|CGjEPimU`nPcnc z-zB;0z0qE_ao2lihhuj=R4pRbvi!SXm)|>(KO-Ew>mPr6xa%Fie0P1~m+!7m{JUtE z-#1*I%lDu1x$Bjx;e2;Ja%DuU+rmF_I3Gw z`?`F8{oMK8Uq5&L_S@Ix`|a!U{q}X|TfcqX`POe=m+!Z)%lDV>&cFWh-TBpTUzhK< zugmw>-<@y$^>^n}fB7!oU%t!tpCY;QYxnT>bLUsTe0M(e%XjBTzkHYPm+$gl443Ef z4@Sh=Km7G~=Tm?E-T8B3czTyVDI(VSYlUNXKCK-QYyRYjSoe=95wYff7ZGdziHJD5 ze0M(e%XjC`sp08ees)Bx^ZWVkeBF2q5$k8w66O7Y!^E9zc>~Pn5_><|o^ge| z$jG~IQYVSEetJ$$l;{7Qh?m&7r5R4_%5QDv5-+g%-OVaux4d5FR$^CPTk{z45<7i6 z^LJwHw~3~``I1=cl4v>@`L=FbAJ;!Rn(D-^{W_VBQE`eH7ZrCii=*N+vmq+(X`YOV z`XTuWZ`SCdtdp}y|fq{5(AYR1$uKwqlO;Pc1^ANGlmMHJE zAB>7GFz-jjqs@;|afT^g*wxp~KgQIFiZe|oVrgb6f2=v5xVMeRnHf>jk2gz+lkECt znRUct?DP}NmZ*4=*%K8{F$bdJZ1X0u+kdBh?xE)o-<#My$t) zM0q~6h`5rS{wi}Vu`7SA*-Y%pzt-#~cIB@#2Z>$zH<}O01t1N|gKMuEd|&{5#B0V*OlDqSuhIoOU zf1A0RSg%JaAch~zQK-f@y7536B&jQm3*o+JDemuR3toPCYTa2=0w*ZJY9hyw{Ccf zv{u3KAFO)x;1s{4$a%tFDC5;%#>@oQ)FlPh$sao8&8fqug0qqqm{(H+NfCpEyz-*P zsYN6P=8PQv6*YP*GUIgf1k$~sMZwjGNI%USf#lPUsA1FieKoQd7Z?F&2O`QW1v0{O zdF>KjV8rO1)8(D&d#wWB|3Eb(2WCYloxTDEzeFNjH$Ih7kB|D6p90G-FvV%h z@{VW)s^Je%r_$bF%;3VjbbpYhKSSUPNW9e#95aI@W<-BYiZ_=%=0uIn)m|irjsj`A z`UMiDVGE>%_v!*U-cDK|LlRE?^%9c7kTf}%MtpOC*I`|%R@ogq!(Z$YwSLhDoxspK zU9YGKWSyeo@cKlhdh22nU7MY1Ahon)^iW~1V!GJq94#bzw5T_&c3(Rd-W#6hWrV91 zovkIMo$`Aa+;pcHzD)uCFy`=C?-V0+y~P*I(sQ6L{nTH2B8?G!jP-+?KGPIP3NF!` zE^>k4eh|Ibh~$WcN2CTWWg>E-2S|IJJ-T>5HKKGsF;KXlafY&^h9^hOp{pxD4ds8a z{W12Ft;G(-7`?8Km4^p<{}wABmwQQlDaJmVC?*e+?DVhT>v$C3!gpij&Rois^7i0y zEGF0an%*4G!%K0EsLR*qT)O;qsw{uKI?kAl>IX6AHuZRn*{psTWAuI~cD#%?QnQTx zm!aPo`BO)pW*3rm*Rg({XdOy_5bWo*8h{gUVnWSQtay(88IM! z6Jx5W-^JL^sTVsz{5|mxY&Xe2kLebnz5}T9>HS=>Z)40as>~G#<<-4+N zT#dLkaVu5o(@p(3#tc#A;p2Gq#~72R{z^ZS*w*{E7}HdjcQVF~gD6%w*46LXKzt++ zzZQt!h%x%SLFc#I^%(0dvEEk~dnd-Uu=z%wcuAZPYr3m)Z#qydW#mbxC?8*!E@p~V zH0B&to}G+QW%`w>Ous{w>5r*0eIZ>hnckLPhWg9KxJ2`7OMh1D8Mj_i-Xx8sJlh{- z`iC@@>1|vt)^yQWcEZuBJczgbSYo?;$=|N&qVC7VYPkJZr+=I2^*&wW=1jMYbiKdV z=_{%4_}cb4%Z-F6Cf=d>qJAbL_G?*x)a|J8B+SN{sM}Zb=inu{0GHqjT!oEUo<48U z<3^4u%m1CYxjaYE^s%U)rHK7ajvu%V*W*UK4L9Rf+>X2OA$$a%K>bXH9*>Hsay%-b zzC^#0YnUwp~TruA*&M(YC8-+f}sf zD%y4xZM%wpsa>nbxONq7yNb45Mcb~TZCBB@t7zL*wCyU|b`@>Aind)v+pglj+pdq$ zUy7kUPRVxg*7xtEcZuvz(tkD)%cimYNk5|zE63|>RgTv)RoT8?xpx1NiRZ9gSK@l? z$#T-so39-4D75>p)K7MC+pp_mC-lnk`inij$n=TiR}IXUL)-;>qc`6x#9lqTH9<4em!Zw;BwE=P^ZSoJ6=wGA5dfc>_Y717*j``;`+I!wjX{L6#8H*6{Gpwp#d4lcs0@O}IiW3`=RzC^5vT`?0c#D%y6U&K%F zOZ*Y_{V*-RG*&=;9V{Kf>>^P$9Sca@Z7G;knoa zyJKG*jN|b_T!2^L2D}F!!2@^{KgFN0aGa}O1+0Uua6Hb()p!$b#fR~EJc=hUBpuvt zf2@Jcu`~9^(KrW}FusRhqYUA+%P)_$u_boJbj-$!aV1`loAE*1hp*ys zJb?*C-15)H#@HV9{U&XnEX>2jcop7)_u&E5_mgz~Pw{6gD(}N+dSz^nDcA%1;b7GF zk959^aUm|p)p#%7j}PNh_yK;3U*Y%oE5^u)M3+|>6R-}p#x&ITgLL{V%*Umu@Be82 z?f3)g`#73j9b4ldoQU)AI(!13Q$IB3MLbISr}(`(F~`(d#;?X#c^clptIG6NAYE5I7;Y#w? zl7B1SOZrZHi1cUi2GI$b$TQYF7OHXywr0*hr2p=W=IpP=b2st!TsnQNf#I>;j>8**|VQ12Ns&ehv7YC9*g8a!i2bYk)0xu{1dg7aK z6Y1NCci?W)pHg=kvk#wFWqn>zWj#K?Z}E5XW90@=r%O;}x{9jY+*ZNr=y@lCi%m2$R{f4_REF}v|mRmy#q z{3FD#<1x}dA^se{QKg(;$uA_whS-bbc@maTrQ8atv{Oyuy4Z;Hw#4nRiz?;xA%BRv z!kA$=N|kaake@?53oj;pIq~0cjVk4ABL8l6i81%$PF2c%l>Fz2U&O}6ZR*4geudI#w^lv)Z65_ zIW8vs3RR}R8gC%|PIZ$pcjH5(?^R{`{dkDr3i}VpVPQ6Obm-^AnUGPyp% z?@5oZEa_7JQtBdO%3>1f$#|~1z?e?hhxAdHrOHFb$vBJj<+w(jBhT&e7Sea%<7&P! zPvc9ZA5*2h-^C9}KY=<}LGue?aaGo*lKO#s{~#uj-;n$^#OGpX()$n(z#*!XlS}>r z^*v*j;0jfie--%~h&SP#r0*nt5Fb&coHxn;M9nqkbNrd~IJt+>@{3}ED(iPPHXywT zwjw=6Ju2T7h`q=kOnwIOIGjX!9`PKUNBU*Nm*Z8WZy?@;cdD}7?YJ9X#Mkg0`~-i) zI2qic^PjECdNx#FH>N4JP^CROkl&NIFAgI80^&@ZKza`GEWDWX<-~u(HL5K47V@{L z7s~s8_&DhYRH@G)e1-H6@mqCs6`Gt>oWJyb~WHeJ}BTe3A4wh~L8ZN&k}gTl|sq zkUSgE)n!JCC@2gUu&&mIZ z_&1D6a`Tl`Wx6t0f%KZhb+HlYZHe1s7t#mfDALDZmMZnyN&XY+BxCmCepQx#nEbbi z-^Y(h|Bm=a{EhS?HQf9qu#76@SH@b{7+Yf}?1Aa3v}1-k#+Y$9QI+~#s7n4k;)S@3 z^s9)k#T!Y#llX4jPWmInPvA48zfAlp9wq%F;?M9a(tjoX0}IJBvskJBS=ba)aTrd+ zMR=ns>$h2*AomftU6u9UL;gPE=kXBfZxX+Q$4UR1_yqn;dR#46Zc$87W%<>xA?Z!A zr7HDWNd9W|uv|yrwW`!}Bl%m2x8wb!KS}%yK2Q2<#7FTR(*HsH6`mm7)OO1&ghf@U z|5>Wks|luHZyc%0bd%KQjLF8Cs?`4?@|O{>#4AX@k@#l3jr8rryKpz@&k#R{2US__ z>-a8yir?a|7%$I+wZ3K5L&j9ZDyr1C4*AK%t?^vayA$`u0i=&4&cN}c&m_*nxvDI8 z5&jL=;_a%`Z-=_im}a{aqa^pU0~2j8|oSORJJ!l{g9Oke*E38qZaw zoOGOmxp)b##hdVcd_tAwy{Klyn3wTYRqFE&`TrpP3Qv%(Ukaep6~dyblvkekEUZR) zL*k~`lJw5Rso0bBA;iP*0@5cFPs1G2FC|`t%SpeQ_&Qv#%KC1{y?6|Nz=Vcwy874! z&r@YR$El-Y%tV~3N_*s!zmRw-t|a|h;v4X0Rmyn~58=mnQkCTuYb1`4=Wv*)%JQnJ zl3$;=F(#AVkvIjrlb%j|9*!h^BJot5N%|$k3vemvR}x=?H>gt29r!%Hk3XqW-?+x& z`EnnGB~@9UimK$-BCdyxNk50U1E#1_&TzaCFTA6(jOl@WRGEJ$`I*F7 zIED0C#24Xw(*H($1+FE1Bk^r`7wPvC@5aYesn22jOqKQcQB99Azv3UN)U#+amtS6$ z_$;hOdPCx-*iw~p`e3FiHRGybkhJu5VKHddwn?bN<8rX!}PQvW{WpHDmz$B>>)JQMR(Dd%#$ zRh9C$tG(oNg!qsu|^}lk~m#vO3I|SMd#1>iGfrUlD(YKdCZ( zu@<5%zoPn>yx)S=Rhhp5`K^iDVJFgi6Zgl#s+2Pk=c-cvGBqv6ti;u-l)sMr+lV*g zJ*4j@eiWY~{UGsSd|j3Dzs8?2wxvrijulj?Pc5~xJU7Qis??`7`6@lUh?n4Hq+dgPJ#HX<3-LDGN&4f&Pvd^lUm^ZGzNN}~{eY!gxws*A!%?cV z!(_F6jG2ZPs?rV@lfRt!Z@7l^^~4+TcGB-7z909fQvS>2zpb{8G4JC?sx0qo@_!@N zFN@OjI92LdhPXUdCcQ3kLu^KRd*aU6jr4)ULvT3hS;UiZx+?XYPyQ;kMT}X4YgMV= z2J*KMZ^NCWKTiBK?pLLpcgX)-Z6fQBCsZl-ck+w1ad85cRi!hr&nKRXmy*7ccr{*4`pv|*;$~Iqc^^KHNAMVatjcH zkN9~!q{?#NCI1VxRE+rszgMLme~@4NTo;$Za;mgf5^-&8ph`Ji$nU2Xi!p<6s4C@V zkUy1p2Ii5zfOrXBM*20x*W(6N%D40Ukjm%uvM6x(7~Rq8W9{mq!cc)lw2$y6nO8u5iV zi}Xdr%kXccUq^f+ZX|sx@pinQ^e2g*!RJYTjrb_Oqy8rE_hL*(7Z<~_SWT6BH&TBz zrWv+WWxYC*-;1~(rjtIJcq~pNJ(qYkUZP6*SChX{{o0t@aI-4Q+d=+g#82U~q#q%E z9gmUz3GwIn4e2L|V>-F=<5gL1MOD_jw)(mJeIIPBNNbi8X)b7Ug!$GRlcO>}}iKpUBRi?K7LC252{={{ep#4B$o9ltIG5hu`22H zi5p`}(z~c~?cEIrk$!955bNxzf$Zrnlo!>T+ZdK_OM z{Vn`Rm1lXM;g6&jkv^&GSzeWA4rk%nsw}@A`7MdtVh2^G?@#_n^#NltaGWahPbNQ~ zcrIS5%Jf%ZAtUjJ^7%Y0g=J9|W%K2B%qpi#tL$#pVK@q>s;?R|183vKxEPn?jd(NO zfm?7tzJN#Yb$lD&$M4np^0_-SF)l8Ia>--IEmTCgG_-LoY=q6wj&qaubb1i?M|s3$ z=bMf>I2Y&Pjd(NOfm`rCydU?Yjz84#6-V%O{79`S{RzKC8R~A+b^NgA+wpc{g;*C? z#u``$Q!owt;y|2^IXD;R;SyYdH{#8B2X4XLYIXU%7CwW|;mi0ceu`h<3H%A|I6o<` za>$ii1M6U8Y>p|IhC|e<@;Oo*gX1w9XW|lEfmh(wcrWh6J@^9$B{S|C*TrXfp&bMlz%nx4QR(3O8ULTJMk%1 zcGi7(5D()~d>g;TAMhl`#JO_L#u`{38)Iio#opK-XJQ^+jCMSu)N>i}O1u)U!S%Qi z@5kNv1n$KHcnIHC-!kTX{0zUu7V$2>4R*v79E3x06pq1}n1>hRe7pj$#v5=0Zo?h8 z8z03N@n!rw9>dSkj22#&+!EQg!-pQwO)m= z5>~}pSP$D_N9?PXm+vRRVK@rM<0QNk7vW`iIj+TZcsJT{tFoLYi1*?VwTyh;1>ZqC zj#bkCL2SpdN^Hlgip7h$`4X`Lo{crIJ~qbAn2JMi7*146%6E5TF3!gJxEOE5oAD0Z zg1hli+>871DC+m2>T~+}U@~^c-Z%({ z;#i!3`Kp{7=HfzJikIV+co*J-yYM00htK27_$q#mU*nJXD{3Fm`q**3VoBmMXvgzP zdQ;-oXvg(=!eD6*S zydCetNAXGAk1yaS_&J_HJ8oCXEi5;Du@}kl3(I0fY=q6Q4W5fba2QThSIF@Sb8$9a zj&^*mOt+4BJ#NMA_#{4quc%9m`8&Rg$MF~Z9pg&7>5Jl7cs4f07MP;0k?{lA4+r5y zoQgR(3zwlCZ@Wg0OT>1Zt;E|jUL~KW$36HMzJhlLqKR() zl2{HaVSQ|jEwL^3z&@Cc=ivmLf)`>wUV&HR9qLy3o&>xP@5h(bE%LbqJcjS$Z|Y`w z7*W<)80|P&Nw25z9diGMEwBxytGCJbsNn^eiSyJ=@;PU;<6k9SMZ8(vD4);9o%kTy z@vQmseu&26muSbgN^Hlqit*)Ken~8YHLwmg#^%@syI~(3fEhRr?YLH1o*maJt|NUt z-iDj;UfhWfUbNmH=$9Q>WrTwWGR>G>-Sbbf-M-uJ$ zRf+BRRk0iCJuw?+;%vMa7vVCz9IwQ6xE^oCJ8>KCKs(-5>S4#bihD`lkB9IG{){KF zP-VA%MbM6am2&L(SFtkb)vyjWz~BakEn1D&nj0I<(_xCEt#t74IVb9^8cw;p6x;K92|SReS^A#pC!7{0e`-Uob|V zHS7A@@wj3M;?h_Vt6)v6i-T||j>0iG5vO7f&O$p5SC+ewcm=M)tMNLt<8o#CO~iNM zJ-7=W!pHGxd>#+ttM~@Ki^uUt{1roIyY?!K71b&7J}uV5de|O2V|VP0<8UHQ#~hrC z^YC)K64&8++=&n3WB3$4hcDt=_#P%ybL*3ccHFM4-`T{qu|A%I9ng;3mFasBpN}JP zEKa~#co8ndr5H7SSIXT;`fa!i?f6~Ef1LPfJc6&|+i1t{%Jjbz>w8wZ9gATC*2KEl z6kA|-?2YMo9!^lF$@jTn4$i_$aS^V>)wl`ozpiB^Obx%&Q}a2 zx%w2wT38R8Vhikx12IFLB;#RmD$c-L@lM=^J8(BXihFTC9>ODd6yL@V@l*U7PvEck z2gcWM^(}^Fusl}9B&>&xum!fkj+lZyu`dqB^Kmqe#mn(ZT!-uNR=g9p;SSu5kK$h3 zkB9IG9>uruL;MuK#uNA}+VR7(o#SiLepm*}V^vJTme>|MqaAN7dk3(@d zj=}MmhjVZ~F2<|zI^2Mpa0fnskD?vNEbIR=@vC?Y-^H)dj$4-LeS(aOYxH8tjI@lPSV_R&GU9mg%!$CLS4z%i|a^V zkGJBTxD9vUZhRE?;(k1YNAM`Vjlbd_7+=q|kN)if-7b}}8rH!E*bX~lH|&YSa1`d^ zY`hc~;bnL^uElkD58j8n@lo81`|gmFv6wYG}t%%k&M1n`0|%kDakQ z_QpXt6i4A0oQP8~2WR0tT!<@h6<&?k;Rf7XR_$WS!U*fm;GoHkf4PE<`!Ae*a8)I{9i|w%w4nR9j{5knMB*as2I@)pK zl0TRDGQ1qu;yT=nTX84aapO|Xv&0ART|ADTdx<7*h-*sX6dEQ95- zDkfn)Y=kYa4R%C39$nU_CvjgKjOXKM9E+228s^~~T!E|bKD-|v!6)z~dfn~8GR>PXu0GnVdJO?|Y9Vaj4_a^R- zcAUJV4<{aj<8dm^Ks#<;rnlqf#f79V#fR~6+=tKOQG6Re#82^OJc)&xx%Mc6m9Q$- z!g|;i+hbSkj_2VBwBzSxJ+g@NaV{>vCAb#X;WPLgzJzvMyp(Il!;7Dg{uO?Qq2_M= z3S$B$Voj`zO)welIC&{QjkqrkL_1Di^2ZZT#Thss7voA?jT>+iK8O$F)A%gfarCl0 zJC0s_U(?shcoO^)zr|w7Edx<7;Tg?aO+7L;Mr| zhM~5uJqlw2CZZkBFW*CD$McI#G+j)_emDq+p&idJ(~TpZh|@6#=i)qEf-CS=yc4&f z9p5kI?fTQ$Nft=(}?qM4$jBLcmr<0+wm^kj=S(-d>miHqxc?vh@a!v_#^&`mD;)XsEW1F zejk9WM^oY!*bX~lH|&W6a4?R*(Ks9J_X9}zi-?!u<#;9DfE&<$Pk_vK7x6>t`SSM) zaWC%2&h#NrO|$0fGnp9adkWwJ7F63!htvhN22}y04Z+*@f5re z^U;2Pz)<=7dm4*ta4l}et+*2(#8>d|_zv3d5s>meBmNS<$Dh%(cgrn=#jzCH?-`JC z?Dq_a$)vZ&4%h{Ip#8o9nLeHPJe-CX;vBpL7vpkVjaT8lxD)O74#;vIBYp;-L;F1h zl5f9oY>X|j zEq21LXuqF8mUkZU1(=DGFdOINVqA%<@ou~qAHY5MBtC;L;7j-xzK8bv3Z#CY6Mu(4 zVyRAU{mWuytcDG-DYnLT*i%i9F@13e4#Vk~gL82n+V3xr`R(@?h_{ix8SllNct9N> z--C{?3$*p9qsoNNP79suAHivgq^S}+V3ln>FxIwh(kyphSTsuoP(F( zVqA{vaUsPcVxzhG<^7sq2&Ou~BD2wPwqOvm%^ z0?fp@s(e4)JY0&G;Z1l8ZpN+nI6jTf<3ao!zs4W&SBy<@%a6w@SRLzPLrlij*cL|8Mosu+>iEq3}m_^#INH=>SKJLf%q-)5BNLk zcW&r()vzWuz$VxV&%w@^ioMZ(-+`1jlz2E^jPr3BuEZsJIzVOgw<)vyjWz~LQG<7)dD^9g>9C$MyPmtPL6V0EmE4KW#8V+ZVl zJ+Kc>z$thk=Hn%}0GH$6@G86(Z^Bz}2R?xN)YkGG1`p$F_yhieF+JS$aaaONV@0fj zHL)%>!DKuKJ76mIzzH}7FT{LYikIOUT#L8iX1o`7;?wvn9>l}=C4P&);O|(jr)!T& zSRHF&3v7df@q8SOV{tN0!#tdW^Kmh*#MO8WUXNRGJ3fdHepx9>Jsd zHhziU;?H;ztMqp3R~_qOLu`i~aR?5>3>=43a60DWTwH}~@H)H^x2WkdZWABCJ$Mig z;~V%Eey%=Z%-8r6{)UD6xcnkm8|z~;Y>DS$Crra$I1q>6NX)?5YJK^BNnDJ}@gBSn zAHqlQX?zwB;$eIP-@@bg34Vp&;V<|*#`SgeD~hGD99F^V*bfKcFdT*Ba3W5}9Gr{u za0#x!EAVQ(0XN|7co%NRUHC9Qj&I;w_=Q?sp10!9coOUMbNLOhIkv*~*crQHZyba} zaTJchi8vK=a2C$Pg}4G&;njE@Zoo}=KkmjSa4&v?-{Ws+`n&ZmjK#4ER>!*75YNR< zn1;P@I9`C`aT3nKOK>qR$LsJ$+=O@F1GopD#Aom%#td-lR|HF7RZPNq*a+KWXY7u> zaRiRWES!vUaUL$g6}S%9$EAdLa2G`?8yc6%n9ryq~icjKxd;!13AMhl`4081>f+eslR>W#p z6B}R?Y=!4wI-Z9U)Uxt@vzUXk@CMxQ|5bKAa8;G}A3vHkH2XK8f~muF|$SMpKGqU zYU!G@-{*7g=eayQ++*8$b$k20&-Z+u=leX*dA{eKbGTQ0NPJjq6Ss*^iBF3=#TUij zim!-!#6IzT@z3H%;-})j#39JBYPuwqlPL3Ml9kn3JW5rS8nc{eHk~l@2CFY8GVn|#{j==Bh zh~;9Hc(-`3xLLekd`Ns)Y!kPMPl->9JH;2pcf~)6`^8VhVWDXI62wvBiQ<{!cyW?A zMa&aJ;v%s?EE6lm?~ury-xco^?-3so9~RrhZQ`@!c04C4{zm+r_`3L}_)qb3@t7;4 z`;QQh7f%wC#T0S8I6<5uP7|*nkH&o-@oMoJah+Hv-YwoMZWiws9}*uH+r(|+Q{vO& zPVq(Yx8f_}9JS2KoMg6`c9xI+8o-CdwjuBJEiQ;+U`Qk<5 zOfgrSD~7~;u|QlZt`N(_YH^iVFE)txi9Zy(#BT9-;%nj`#6OB3iJyx95{Ka0GW+p( z@gy->OcB$>bn)xr#o|11fq1oejaVjDimSw%#5=`%#7416+$HvkZ;Ee=ABzXX!{X3y zM&mm{JXt(V93!49P8DZ}nPQ$85*LXDV!2o)t`=_=?-DnNKM;Q;{*U;W*e-U6z2YA6 z9dWOCSmbYLaXg2M$BD^eia41(;CbhXUl%VHzaq}|@mO(`c((X8@j`Mxz86o-73YfAi`C*9 zu~xiITrX}AH;F$Ie=N3$t>P2n&&3_$GvW*4OX4oES3Ds8QyjWD8qYD}$>OQv81XD| zs(68zDQ1fyF<&eYmx{NDw~Fh&_sJ*my}RPa;sNn<@u;OyzpsjCisy)v#Hr#1Vy2iaUM|iP7m8Pl$9SkGjNc(9 zkH+_~lfykPg**=5hejTc?~fu+^1KZ4%bu4>Cgbnj$gkr2jmb0cz4PQ*o>xd>=Mr*) z=T(qj^Sl}o{Z~t3-0Mipj|LL+x{<{EZzi#Bw2+zjJu`Bq=e3i#=iEtRo$VrXJgz@HB7U+Q@srmhezFSjlhufytU>(bYQ#^jLHy*+h@Y%Q{N!51Pp(7! z(^I}krvkNC;E5I@;~_{j~3pWKM}$xVo#Y()IzW_AMpYeM|w{fM7zM*QT1 zo|i&yLHy)a#80*$e)18-Pqrd{@=?T3K8EV7w-G=2F5)L~zTzDP z?nC?}CPyNP^Y|q45aK6sog$UQ^{6xw*S#`GT-VDaah*1Y#QlyuG8MlgO5%QIA&L8@ zB_!^jSCDvapoY8{zY|N&!gF~fo_A^>@myIWiRaRq$@xRP7V=8`o+^pwgWE|w@7zh^ z`S>ofV2Ia4;_sTc@i-nPCXhIuM~aCgj_c845{ctGSxg~uoR1Y#NgVGJ#WWJmIAnch zkU0Klh?(RW`1>$1hs1g?N6aH3%0rOMC$T;(77IzN6UAZ)iS?pXtRS&&M8p~rjaehs zl2}L9iFG8_lX|g%#JaLkY$P*1uSsksXX5v)#1<04w2E!yZ2Ufu*iPnnUWeF8VjX%; z>>?3-x7b5sUD_q~l6m+(1F?_9I`xjYmki66+(Tvd==Y2IDW5kgGBNVgEU#uh7V*JGhavjEBY$U&j z@fVxPI*h;ALSnsb72C*qjKA1UV*Tw9JIMx&zt}}$J?<8J$c-3(v6sa9yhrRK8!`Uk zUUDKN%jzm7K7aK_A)s12!iTv6m zHj~J+Tf`O;`L0bgLV}nyanVO{5}$i z{MAJwZ@on#UtKs7M4nnmB0rUr$V>l6UXANd#HEClYz&!V^K{5C40@kvCqWjeN16TkNMcTt_~d4r2Yd5p$U9#vf*YST7nc1hG#1@nR6`!}d%N>q7b^ zAl8HRB-Vl9nCm?LmykH_Q?o!E@4HDHtXr}{9N&v)fjF-H=Sp!rW7>E_k<>Bl{_%|F z`gR71V=E*(pTyjb$gUxe*ZC&)Z={X6woT>jB<4zw>|G?r7G3D;qYM3YAYn+<9!Z{| z^E2q7Yy5Q~Q{~xYsy>gRJVYB~Q>gM{66-~U>_ifMo-8|soUQWfL%fR3Y`zYuBDx){13Z<_I%}c*nWNwDWAh`XZb?qZ`gkR#-RH7 z8FnAbuU0;W?dRjg%D=F^qfmYg&aX(=Nn|0`G1=+lGK`Px5Ltru%dQ|-U_4~|c?;{H zpNF95=OL_zetv=7MZfEDJ|X{JvI_k#doNjy^99)lNleON!$9nxK(0pr%T6KJ;CxSZ z8hJDNUv>^zi~g6LPp-xJn(PvC9r|B(E%`n4zw8FG4*f5?g}ej(FT0(r$N7@%9`Y{q zzwAD;0rAK_NMc(tB6}=}bvi@#3=#)nj_f()W*i@~i^(P&AF}=5*}EU( zA-kSz#_=KB|2@42F+Q?e$t^fOWOtBTaeT<`CR=cwLiQf=5nQK`y^n0gx-9z;`6#Ya z90MZ0k>q2zP9Zy)L|#ajok1c$}BCyM@G} z@Bhvl`r|p;$cw!y-$Nolej@uIi99)S1PK2`68SP!_CykSGe`Cu68W=Ob_vPzYuUBr z9GpMPZX}Uc{qslYx6wv^^?!#Ab{B2r**^KdLn7ZElI`*Q5qUR>gnu%L{F^R2gG3$< z$<8NvooiCns+EzVC19j7$`bRhNVq2AO)4&m6nT@DR8@JC_{OAA?%aZTS?3lk2uHHY z%a$#_cEJ1R1-zdg@cz_*_ou~uKa_iJLA27`vWn`+f=JP|VXOL3?v#MtrW|><_^l4* z#&30QXnxJ0dU7tAQ^2m7SyUA+m|InmTecjX=l7UflpT&1R)$OCIGEDGyCU4mxS9(h zi64aF}jukefFw<5Z0_S{RnNkIBaDy~aY{~}cQZTo=G_w4v%H@%;rrRK`nCpM!#Tgnb<<~ktTvYsp zmHr1#gAR&I!)4*hqDXkw4dF8PK#DFaSYZ5>#W`YFX;x81q`ER(ys)UW+AKQe$j%E_ zE-x>hRa#V06^3JJ>5`(Q*IDs$VL-PHbgL+J+c2O!r>JyU7JU9qIpglM+&`{Li&hP4 z+kgp%sjcvWYcmdmo87;+X~Y+*7)PhIJZAl4Y4-B6dWjfqVj#&NnfO6>I-gI zzn<}RG((lkue~;08Arj)g53Gv$SEo-E)7=>9(uF);I^v7)EY-$v&V6Cnm4PmvOHen zw6kCA?Bb`YOT$c~5qCyo-UO6zi~@=<5dunL>svs%S)T%m@%AN4Bg=0HXO$F{m4!>4 zKv1lLc%k6H^OrWeES9OQvzS4vlixo9sT%zgP{RHRC_?`Pl*IZcpxpFNwAep(8N$4* z0Vh0zB0wvn>sqYe2Dz}gj!#UUr&~wrARhSsDPXXCEHKA0R>!Q+{3F&8-EUr2Wq4Uu zX}HKfw9IiQ>C*D0*DWZou3U<_91D}Zw4k);hHz;4N@UO@MdQ0gwHB-@TUt_CZt0l1 z20QhiU$L&NtQvJj*2>~I`(s3cQk-8DH%*$I;-9Z+zatdlv@v?B7V8!hj@cK-NSwxU zZUnV9S{AptvEAY~$?SQg(%=@y_Kx3VOv#`Y`$cgZY<7y@BJFpC!r<1Led9Mac5nnW z*>Z^6aI2hc;Fg@p$1<$`|@ggpXTq3EndsE(iKsHvVt>;gX*J3|h1l*K72T#g5-d?1am~ zvCa5J9KXTT&KZwUPCcry`i3j7%FDR|M3@s4x!p2KzK z8F=4pDE7BA9KAxT|8UzXrZ>~kV?&Jwh0MPfIetR}{8l@D!{8Thd~blC9dC)%KHL(G zwQqx?w<4h4R>#l3Zq5L-q1fNL9lx@G_VNCa-M$K|ePf_x#^YT_Z&yJ34m*CY2Kb$Z zd1=p=-hlRf8Gd&AYOMC1WwmdrqjwRn%SXGy|G)V+?`PTdW(N4Ja{Ok(54Y`No6)Ow z+E;6}?`(LR{=3i7YY3?KXO7>70KeZmej5YY_lncLI;(xS%^GXpXO7-G&|_{en>l_z zb@UpbR|_W|zqm~s(>n`0*!|pyK|C4dW;6Xa27dPVCf4__f4I#X)4SZ!dlWmZGh(38 zyVTK3f?fv7**@ILkLgu7dg-{{A1~fgM=uY0wbH|*05QGIj^19}2Z$H%CP%NwiuZg= z?`cQxF!a`;+-xS^ryRXrD_-38jaBJ3UJauXNEy;i+f!`a09p`*7BdKmK9 zX7onjBz3^J1^Ds)zwOr$;CHd(w<*Byn~q;ofZr;|@4)~+K38D3uLXYW3$vMcfA09T z!tXNU1RB3r9KTNk>iwJJcL;td*1R`u_%BR)yM4(g;8~bB^^Sm_eSGv`d?D!{AIm^9 zzUMf4YXbDfIePmoy%I|=+tJ$-pqJ_Bd3W`)m* zFW&J{?dYXgdS#a04;;ON&}&1v+03|o-_c96^eW(N#$%hK*D`wGdT;c49KR$yqqy2s z3Yz)X?bMrzdeczegI5(^rrwVoy$#TtZp}ZV_g6=+!qTg@^iITLXV24aEV>&}ZZ;Fg zWXG=%A9}lu6KLw406$diWvZ+h^`_w8j02Cy#p0On=uJ#Qp%sUz_X^|zZO1zse%V&N#_w*Y-agceL*I|%CeYOTq@!2QN-aGT$K#IPUg+gW z?-omMx2uN>f*mL~o6&pK(M!7<&-%cL{rnxgO#A-j=;b6w^RCe|@&3cn%YmMW_f|{q z44lu~{m18}na9m$^iGGLJrD9Mz3;-=v~RYfw-0)!8!^!6Ephxt;vz(ToPNH>sW;!M zx6Z2fCP%Lrm9|>-ntop8=oMOecUXG&IeLkBJ{*r-#WtgNucKE2y$X17-0JZ%{qi$M zZ&wNmH-qCBf^fp;~ zvmL#W2qND2&UExTp=ZXo(b5Y$dOc^OFi!s!IeKaL^vAo|(!15wJ1745-s0$GK+lYC zlco0)M{nQP;*akGj$R-1%=q4K={@7<4Z}s3k~s11aP$&3^vBz5>Am6Tm8RiuDo}1V zvu^y}(Mz=S9)z=*F9#gG1YE>vjnh83da2OM#QQvcInE~DZ#a6%(@eF%7lqcL+-#tQqn8K0e7w*8>%hyz z`+%c22N&t^czA3x(m!_kxb9~$xIo5k>26x?S)hWF#^`5u%Mmu_+?)SV4 za;O~LO#2eyH(=gR8|wef5A|Na%fy=^y)^AV`2yr~eD*OL_4u0L_&ty}#J~6M`eiun z>w;e?&XLTyvJ+%<={r;m1v9EjNktQ51)|_ literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_hal_tim_ex.d b/build/stm32f7xx_hal_tim_ex.d new file mode 100644 index 0000000..f5f5aeb --- /dev/null +++ b/build/stm32f7xx_hal_tim_ex.d @@ -0,0 +1,68 @@ +build/stm32f7xx_hal_tim_ex.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/build/stm32f7xx_hal_tim_ex.lst b/build/stm32f7xx_hal_tim_ex.lst new file mode 100644 index 0000000..37c9b78 --- /dev/null +++ b/build/stm32f7xx_hal_tim_ex.lst @@ -0,0 +1,10691 @@ +ARM GAS /tmp/cc3heCqB.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_hal_tim_ex.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c" + 19 .section .text.TIM_CCxNChannelCmd,"ax",%progbits + 20 .align 1 + 21 .syntax unified + 22 .thumb + 23 .thumb_func + 25 TIM_CCxNChannelCmd: + 26 .LVL0: + 27 .LFB185: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @file stm32f7xx_hal_tim_ex.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief TIM HAL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * functionalities of the Timer Extended peripheral: + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * + Time Hall Sensor Interface Initialization + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * + Time Hall Sensor Interface Start + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * + Time Complementary signal break and dead time configuration + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * + Time Master and Slave synchronization configuration + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * + Timer remapping capabilities configuration + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ****************************************************************************** + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @attention + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * Copyright (c) 2017 STMicroelectronics. + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * All rights reserved. + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This software is licensed under terms that can be found in the LICENSE file + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * in the root directory of this software component. + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ****************************************************************************** + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @verbatim + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ============================================================================== + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ##### TIMER Extended features ##### + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ============================================================================== + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** [..] + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** The Timer Extended features include: + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (#) Complementary outputs with programmable dead-time for : + ARM GAS /tmp/cc3heCqB.s page 2 + + + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (++) Output Compare + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (++) PWM generation (Edge and Center-aligned Mode) + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (++) One-pulse mode output + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (#) Synchronization circuit to control the timer with external signals and to + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** interconnect several timers together. + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (#) Break input to put the timer output signals in reset state or in a known state. + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** positioning purposes + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ##### How to use this driver ##### + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ============================================================================== + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** [..] + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (#) Initialize the TIM low level resources by implementing the following functions + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** depending on the selected feature: + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (#) Initialize the TIM low level resources : + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (##) TIM pins configuration + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+++) Enable the clock for the TIM GPIOs using the following function: + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_RCC_GPIOx_CLK_ENABLE(); + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (#) The external Clock can be configured, if needed (the default clock is the + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** internal clock from the APBx), using the following function: + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ConfigClockSource, the clock configuration should be done before + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** any start function. + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (#) Configure the TIM in the desired functioning mode using one of the + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** initialization function of this driver: + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Timer Hall Sensor Interface and the commutation event with the corresponding + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Interrupt and DMA request if needed (Note that One Timer is used to interface + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** with the Hall sensor Interface and another Timer should be used to use + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** the commutation event). + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (#) Activate the TIM peripheral using one of the start functions: + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIMEx_OCN_Start_IT() + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIMEx_PWMN_Start_IT() + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePul + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA() + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIMEx_HallSensor_Start_IT(). + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @endverbatim + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ****************************************************************************** + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Includes ------------------------------------------------------------------*/ + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #include "stm32f7xx_hal.h" + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @addtogroup STM32F7xx_HAL_Driver + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @{ + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx TIMEx + ARM GAS /tmp/cc3heCqB.s page 3 + + + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief TIM Extended HAL module driver + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @{ + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #ifdef HAL_TIM_MODULE_ENABLED + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Private define ------------------------------------------------------------*/ + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Private macros ------------------------------------------------------------*/ + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Private variables ---------------------------------------------------------*/ + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Exported functions --------------------------------------------------------*/ + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @{ + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Timer Hall Sensor functions + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @verbatim + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ============================================================================== + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ##### Timer Hall Sensor functions ##### + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ============================================================================== + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** [..] + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** This section provides functions allowing to: + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Initialize and configure TIM HAL Sensor. + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) De-initialize TIM HAL Sensor. + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Start the Hall Sensor Interface. + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Stop the Hall Sensor Interface. + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Start the Hall Sensor Interface and enable interrupts. + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Stop the Hall Sensor Interface and disable interrupts. + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Start the Hall Sensor Interface and enable DMA transfers. + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Stop the Hall Sensor Interface and disable DMA transfers. + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @endverbatim + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @{ + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @note When the timer instance is initialized in Hall Sensor Interface mode, + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * timer channels 1 and channel 2 are reserved and cannot be used for + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * other purpose. + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param sConfig TIM Hall Sensor configuration structure + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeD + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_OC_InitTypeDef OC_Config; + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the TIM handle allocation */ + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (htim == NULL) + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + ARM GAS /tmp/cc3heCqB.s page 4 + + + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (htim->State == HAL_TIM_STATE_RESET) + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Allocate lock resource and initialize it */ + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Lock = HAL_UNLOCKED; + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Reset interrupt callbacks to legacy week callbacks */ + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_ResetCallback(htim); + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (htim->HallSensor_MspInitCallback == NULL) + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC */ + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->HallSensor_MspInitCallback(htim); + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #else + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIMEx_HallSensor_MspInit(htim); + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM state */ + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_BUSY; + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Configure the Time base in the Encoder Mode */ + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sens + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Reset the IC1PSC Bits */ + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the IC1PSC value */ + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Hall sensor interface (XOR function of the three inputs) */ + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= TIM_CR2_TI1S; + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR &= ~TIM_SMCR_TS; + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= TIM_TS_TI1F_ED; + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR &= ~TIM_SMCR_SMS; + ARM GAS /tmp/cc3heCqB.s page 5 + + + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** OC_Config.OCMode = TIM_OCMODE_PWM2; + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** OC_Config.Pulse = sConfig->Commutation_Delay; + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_OC2_SetConfig(htim->Instance, &OC_Config); + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** register to 101 */ + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 &= ~TIM_CR2_MMS; + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= TIM_TRGO_OC2REF; + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Initialize the DMA burst operation state */ + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Initialize the TIM channels state */ + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Initialize the TIM state*/ + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_READY; + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief DeInitializes the TIM Hall Sensor interface + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_BUSY; + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the TIM Peripheral Clock */ + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (htim->HallSensor_MspDeInitCallback == NULL) + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* DeInit the low level hardware */ + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->HallSensor_MspDeInitCallback(htim); + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #else + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + ARM GAS /tmp/cc3heCqB.s page 6 + + + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIMEx_HallSensor_MspDeInit(htim); + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Change the DMA burst operation state */ + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Change the TIM channels state */ + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Change TIM state */ + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_RESET; + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Release Lock */ + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_UNLOCK(htim); + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Initializes the TIM Hall Sensor MSP. + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval None + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Prevent unused argument(s) compilation warning */ + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** UNUSED(htim); + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief DeInitializes TIM Hall Sensor MSP. + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval None + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Prevent unused argument(s) compilation warning */ + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** UNUSED(htim); + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Starts the TIM Hall Sensor Interface. + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) + ARM GAS /tmp/cc3heCqB.s page 7 + + + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the TIM channels state */ + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM channels state */ + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Input Capture channel 1 + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Stops the TIM Hall sensor Interface. + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + ARM GAS /tmp/cc3heCqB.s page 8 + + + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Input Capture channels 1, 2 and 3 + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Peripheral */ + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM channels state */ + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the TIM channels state */ + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM channels state */ + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the capture compare Interrupts 1 event */ + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Input Capture channel 1 + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + ARM GAS /tmp/cc3heCqB.s page 9 + + + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Input Capture channel 1 + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the capture compare Interrupts event */ + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Peripheral */ + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM channels state */ + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Starts the TIM Hall Sensor Interface in DMA mode. + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param pData The destination Buffer address. + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param Length The length of data to be transferred from TIM peripheral to memory. + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + ARM GAS /tmp/cc3heCqB.s page 10 + + + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM channel state */ + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_BUSY; + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if ((pData == NULL) || (Length == 0U)) + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Input Capture channel 1 + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA Input Capture 1 Callbacks */ + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA error callback */ + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the DMA stream for Capture 1*/ + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return error status */ + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the capture compare 1 Interrupt */ + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + ARM GAS /tmp/cc3heCqB.s page 11 + + + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Stops the TIM Hall Sensor Interface in DMA mode. + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Input Capture channel 1 + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the capture compare Interrupts 1 event */ + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Peripheral */ + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM channel state */ + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @} + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Timer Complementary Output Compare functions + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @verbatim + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ============================================================================== + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ##### Timer Complementary Output Compare functions ##### + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ============================================================================== + ARM GAS /tmp/cc3heCqB.s page 12 + + + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** [..] + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** This section provides functions allowing to: + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Start the Complementary Output Compare/PWM. + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Stop the Complementary Output Compare/PWM. + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Start the Complementary Output Compare/PWM and enable interrupts. + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Stop the Complementary Output Compare/PWM and disable interrupts. + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @endverbatim + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @{ + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Starts the TIM Output Compare signal generation on the complementary + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * output. + 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM Output Compare handle + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param Channel TIM Channel to be enabled + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the TIM complementary channel state */ + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Capture compare channel N */ + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Main Output */ + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_MOE_ENABLE(htim); + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + ARM GAS /tmp/cc3heCqB.s page 13 + + + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Stops the TIM Output Compare signal generation on the complementary + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * output. + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM handle + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param Channel TIM Channel to be disabled + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: + 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Capture compare channel N */ + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Main Output */ + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_MOE_DISABLE(htim); + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Peripheral */ + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Starts the TIM Output Compare signal generation in interrupt mode + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * on the complementary output. + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM OC handle + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param Channel TIM Channel to be enabled + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + ARM GAS /tmp/cc3heCqB.s page 14 + + + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the TIM complementary channel state */ + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** switch (Channel) + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_1: + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the TIM Output Compare interrupt */ + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_2: + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the TIM Output Compare interrupt */ + 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_3: + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the TIM Output Compare interrupt */ + 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** default: + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** status = HAL_ERROR; + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (status == HAL_OK) + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the TIM Break interrupt */ + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Capture compare channel N */ + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Main Output */ + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_MOE_ENABLE(htim); + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + ARM GAS /tmp/cc3heCqB.s page 15 + + + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return status; + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Stops the TIM Output Compare signal generation in interrupt mode + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * on the complementary output. + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM Output Compare handle + 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param Channel TIM Channel to be disabled + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: + 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpccer; + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** switch (Channel) + 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_1: + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the TIM Output Compare interrupt */ + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_2: + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the TIM Output Compare interrupt */ + 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_3: + 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the TIM Output Compare interrupt */ + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** default: + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** status = HAL_ERROR; + 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + ARM GAS /tmp/cc3heCqB.s page 16 + + + 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (status == HAL_OK) + 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Capture compare channel N */ + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the TIM Break interrupt (only if no more channel is active) */ + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmpccer = htim->Instance->CCER; + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Main Output */ + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_MOE_DISABLE(htim); + 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Peripheral */ + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); + 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return status; + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Starts the TIM Output Compare signal generation in DMA mode + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * on the complementary output. + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM Output Compare handle + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param Channel TIM Channel to be enabled + 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param pData The source Buffer address. + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param Length The length of data to be transferred from memory to TIM peripheral + 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status + 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t + 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint16_t Length) + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_BUSY; + 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + ARM GAS /tmp/cc3heCqB.s page 17 + + + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if ((pData == NULL) || (Length == 0U)) + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else + 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** switch (Channel) + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_1: + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA compare callbacks */ + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA error callback */ + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the DMA stream */ + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance-> + 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return error status */ + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; + 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the TIM Output Compare DMA request */ + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_2: + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA compare callbacks */ + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA error callback */ + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the DMA stream */ + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance-> + 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return error status */ + 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; + 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the TIM Output Compare DMA request */ + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + ARM GAS /tmp/cc3heCqB.s page 18 + + + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_3: + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA compare callbacks */ + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA error callback */ + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the DMA stream */ + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance-> + 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return error status */ + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; + 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the TIM Output Compare DMA request */ + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** default: + 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** status = HAL_ERROR; + 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (status == HAL_OK) + 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Capture compare channel N */ + 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Main Output */ + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_MOE_ENABLE(htim); + 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else + 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return status; + 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Stops the TIM Output Compare signal generation in DMA mode +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * on the complementary output. + ARM GAS /tmp/cc3heCqB.s page 19 + + +1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM Output Compare handle +1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param Channel TIM Channel to be disabled +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); +1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** switch (Channel) +1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_1: +1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the TIM Output Compare DMA request */ +1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); +1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_2: +1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the TIM Output Compare DMA request */ +1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); +1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_3: +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the TIM Output Compare DMA request */ +1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); +1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); +1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** default: +1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** status = HAL_ERROR; +1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (status == HAL_OK) +1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Capture compare channel N */ +1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); +1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Main Output */ +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_MOE_DISABLE(htim); +1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Peripheral */ +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); +1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + ARM GAS /tmp/cc3heCqB.s page 20 + + +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ +1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return status; +1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @} +1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Timer Complementary PWM functions +1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @verbatim +1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ============================================================================== +1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ##### Timer Complementary PWM functions ##### +1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ============================================================================== +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** [..] +1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** This section provides functions allowing to: +1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Start the Complementary PWM. +1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Stop the Complementary PWM. +1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Start the Complementary PWM and enable interrupts. +1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Stop the Complementary PWM and disable interrupts. +1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Start the Complementary PWM and enable DMA transfers. +1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Stop the Complementary PWM and disable DMA transfers. +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @endverbatim +1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @{ +1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Starts the PWM signal generation on the complementary output. +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM handle +1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param Channel TIM Channel to be enabled +1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status +1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; +1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); +1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the TIM complementary channel state */ +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) +1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; +1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); +1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + ARM GAS /tmp/cc3heCqB.s page 21 + + +1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the complementary PWM output */ +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); +1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Main Output */ +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_MOE_ENABLE(htim); +1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) +1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ +1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; +1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Stops the PWM signal generation on the complementary output. +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM handle +1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param Channel TIM Channel to be disabled +1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status +1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); +1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the complementary PWM output */ +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Main Output */ +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_MOE_DISABLE(htim); +1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Peripheral */ +1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ +1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; +1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Starts the PWM signal generation in interrupt mode on the + ARM GAS /tmp/cc3heCqB.s page 22 + + +1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * complementary output. +1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM handle +1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param Channel TIM Channel to be disabled +1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status +1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; +1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; +1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); +1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the TIM complementary channel state */ +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** switch (Channel) +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_1: +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the TIM Capture/Compare 1 interrupt */ +1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); +1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_2: +1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the TIM Capture/Compare 2 interrupt */ +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); +1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_3: +1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the TIM Capture/Compare 3 interrupt */ +1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); +1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** default: +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** status = HAL_ERROR; +1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (status == HAL_OK) +1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the TIM Break interrupt */ + ARM GAS /tmp/cc3heCqB.s page 23 + + +1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); +1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the complementary PWM output */ +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); +1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Main Output */ +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_MOE_ENABLE(htim); +1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) +1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); +1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else +1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); +1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ +1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return status; +1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Stops the PWM signal generation in interrupt mode on the +1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * complementary output. +1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM handle +1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param Channel TIM Channel to be disabled +1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status +1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; +1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpccer; +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); +1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** switch (Channel) +1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_1: +1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the TIM Capture/Compare 1 interrupt */ +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); +1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_2: +1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + ARM GAS /tmp/cc3heCqB.s page 24 + + +1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the TIM Capture/Compare 2 interrupt */ +1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_3: +1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the TIM Capture/Compare 3 interrupt */ +1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); +1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** default: +1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** status = HAL_ERROR; +1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (status == HAL_OK) +1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the complementary PWM output */ +1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); +1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the TIM Break interrupt (only if no more channel is active) */ +1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmpccer = htim->Instance->CCER; +1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); +1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Main Output */ +1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_MOE_DISABLE(htim); +1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Peripheral */ +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); +1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ +1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return status; +1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Starts the TIM PWM signal generation in DMA mode on the +1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * complementary output +1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM handle +1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param Channel TIM Channel to be enabled +1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param pData The source Buffer address. +1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param Length The length of data to be transferred from memory to TIM peripheral +1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status +1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_ + ARM GAS /tmp/cc3heCqB.s page 25 + + +1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint16_t Length) +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; +1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; +1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); +1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) +1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_BUSY; +1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) +1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if ((pData == NULL) || (Length == 0U)) +1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; +1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else +1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); +1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else +1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; +1370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** switch (Channel) +1373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_1: +1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA compare callbacks */ +1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; +1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; +1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA error callback */ +1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; +1382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the DMA stream */ +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance-> +1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) +1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return error status */ +1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; +1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the TIM Capture/Compare 1 DMA request */ +1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); +1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_2: +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA compare callbacks */ +1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; +1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + ARM GAS /tmp/cc3heCqB.s page 26 + + +1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA error callback */ +1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; +1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the DMA stream */ +1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance-> +1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) +1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return error status */ +1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; +1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the TIM Capture/Compare 2 DMA request */ +1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); +1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_3: +1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA compare callbacks */ +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA error callback */ +1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; +1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the DMA stream */ +1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance-> +1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) +1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return error status */ +1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; +1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the TIM Capture/Compare 3 DMA request */ +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); +1434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** default: +1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** status = HAL_ERROR; +1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (status == HAL_OK) +1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the complementary PWM output */ +1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); +1446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Main Output */ +1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_MOE_ENABLE(htim); +1449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) +1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; +1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) +1455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + ARM GAS /tmp/cc3heCqB.s page 27 + + +1457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else +1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); +1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ +1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return status; +1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Stops the TIM PWM signal generation in DMA mode on the complementary +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * output +1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM handle +1473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param Channel TIM Channel to be disabled +1474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status +1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; +1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** switch (Channel) +1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_1: +1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the TIM Capture/Compare 1 DMA request */ +1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); +1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_2: +1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the TIM Capture/Compare 2 DMA request */ +1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); +1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); +1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_CHANNEL_3: +1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the TIM Capture/Compare 3 DMA request */ +1508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); +1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); +1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** default: + ARM GAS /tmp/cc3heCqB.s page 28 + + +1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** status = HAL_ERROR; +1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (status == HAL_OK) +1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the complementary PWM output */ +1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); +1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Main Output */ +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_MOE_DISABLE(htim); +1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Peripheral */ +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); +1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); +1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ +1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return status; +1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +1538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @} +1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions +1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Timer Complementary One Pulse functions +1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * +1544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @verbatim +1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ============================================================================== +1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ##### Timer Complementary One Pulse functions ##### +1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ============================================================================== +1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** [..] +1549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** This section provides functions allowing to: +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Start the Complementary One Pulse generation. +1551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Stop the Complementary One Pulse. +1552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Start the Complementary One Pulse and enable interrupts. +1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Stop the Complementary One Pulse and disable interrupts. +1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @endverbatim +1556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @{ +1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Starts the TIM One Pulse signal generation on the complementary +1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * output. +1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @note OutputChannel must match the pulse output channel chosen when calling +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @ref HAL_TIM_OnePulse_ConfigChannel(). +1564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM One Pulse handle +1565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param OutputChannel pulse output channel to enable +1566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status +1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ + ARM GAS /tmp/cc3heCqB.s page 29 + + +1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; +1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); +1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); +1576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA +1577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA +1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +1580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); +1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the TIM channels state */ +1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) +1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) +1585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) +1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) +1587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM channels state */ +1592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +1596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the complementary One Pulse output channel and the Input Capture channel */ +1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); +1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); +1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Main Output */ +1602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_MOE_ENABLE(htim); +1603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ +1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; +1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +1609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Stops the TIM One Pulse signal generation on the complementary +1610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * output. +1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @note OutputChannel must match the pulse output channel chosen when calling +1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @ref HAL_TIM_OnePulse_ConfigChannel(). +1613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM One Pulse handle +1614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param OutputChannel pulse output channel to disable +1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status +1619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; +1623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +1625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); +1626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the complementary One Pulse output channel and the Input Capture channel */ + ARM GAS /tmp/cc3heCqB.s page 30 + + +1628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); +1629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); +1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Main Output */ +1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_MOE_DISABLE(htim); +1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Peripheral */ +1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); +1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM channels state */ +1638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +1639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +1641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +1642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ +1644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; +1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +1648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the +1649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * complementary channel. +1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @note OutputChannel must match the pulse output channel chosen when calling +1651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @ref HAL_TIM_OnePulse_ConfigChannel(). +1652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM One Pulse handle +1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param OutputChannel pulse output channel to enable +1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status +1658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +1660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; +1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); +1663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); +1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA +1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA +1666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); +1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the TIM channels state */ +1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) +1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) +1673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) +1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) +1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_ERROR; +1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM channels state */ +1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +1681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +1682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); +1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); +1684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + ARM GAS /tmp/cc3heCqB.s page 31 + + +1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the TIM Capture/Compare 1 interrupt */ +1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); +1687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the TIM Capture/Compare 2 interrupt */ +1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); +1690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the complementary One Pulse output channel and the Input Capture channel */ +1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); +1693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); +1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Main Output */ +1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_MOE_ENABLE(htim); +1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ +1699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; +1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +1703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the +1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * complementary channel. +1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @note OutputChannel must match the pulse output channel chosen when calling +1706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @ref HAL_TIM_OnePulse_ConfigChannel(). +1707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM One Pulse handle +1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param OutputChannel pulse output channel to disable +1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status +1713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; +1717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); +1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the TIM Capture/Compare 1 interrupt */ +1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); +1723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the TIM Capture/Compare 2 interrupt */ +1725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); +1726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the complementary One Pulse output channel and the Input Capture channel */ +1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); +1729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); +1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Main Output */ +1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_MOE_DISABLE(htim); +1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable the Peripheral */ +1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); +1736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the TIM channels state */ +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +1741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + ARM GAS /tmp/cc3heCqB.s page 32 + + +1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Return function status */ +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; +1745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +1748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @} +1749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions +1752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Peripheral Control functions +1753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @verbatim +1755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ============================================================================== +1756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ##### Peripheral Control functions ##### +1757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ============================================================================== +1758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** [..] +1759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** This section provides functions allowing to: +1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Configure the commutation event in case of use of the Hall sensor interface. +1761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Configure Output channels for OC and PWM mode. +1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Configure Complementary channels, break features and dead time. +1764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Configure Master synchronization. +1765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Configure timer remapping capabilities. +1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Enable or disable channel grouping. +1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @endverbatim +1769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @{ +1770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +1773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Configure the TIM commutation event sequence. +1774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @note This function is mandatory to use the commutation event in order to +1775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * update the configuration at each commutation detection on the TRGI input of the Timer, +1776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * the typical use of this feature is with the use of another Timer(interface Timer) +1777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * configured in Hall sensor interface, this interface Timer will generate the +1778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * commutation at its TRGO output (connected to Timer used in this function) each time +1779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * the TI1 of the Interface Timer detect a commutation at its input TI1. +1780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM handle +1781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall +1782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TS_ITR0: Internal trigger 0 selected +1784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TS_ITR1: Internal trigger 1 selected +1785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TS_ITR2: Internal trigger 2 selected +1786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TS_ITR3: Internal trigger 3 selected +1787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TS_NONE: No trigger is needed +1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param CommutationSource the Commutation Event source +1789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer +1791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG +1792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status +1793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, +1795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t CommutationSource) +1796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + ARM GAS /tmp/cc3heCqB.s page 33 + + +1799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); +1800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_LOCK(htim); +1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || +1804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) +1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Input trigger */ +1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR &= ~TIM_SMCR_TS; +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= InputTrigger; +1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Capture Compare preload feature */ +1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= TIM_CR2_CCPC; +1813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Commutation event source */ +1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 &= ~TIM_CR2_CCUS; +1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= CommutationSource; +1816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable Commutation Interrupt */ +1818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); +1819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable Commutation DMA request */ +1821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); +1822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_UNLOCK(htim); +1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; +1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +1829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Configure the TIM commutation event sequence with interrupt. +1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @note This function is mandatory to use the commutation event in order to +1831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * update the configuration at each commutation detection on the TRGI input of the Timer, +1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * the typical use of this feature is with the use of another Timer(interface Timer) +1833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * configured in Hall sensor interface, this interface Timer will generate the +1834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * commutation at its TRGO output (connected to Timer used in this function) each time +1835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * the TI1 of the Interface Timer detect a commutation at its input TI1. +1836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM handle +1837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall +1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TS_ITR0: Internal trigger 0 selected +1840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TS_ITR1: Internal trigger 1 selected +1841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TS_ITR2: Internal trigger 2 selected +1842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TS_ITR3: Internal trigger 3 selected +1843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TS_NONE: No trigger is needed +1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param CommutationSource the Commutation Event source +1845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer +1847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG +1848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status +1849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, +1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t CommutationSource) +1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +1854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); +1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + ARM GAS /tmp/cc3heCqB.s page 34 + + +1856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_LOCK(htim); +1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || +1860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) +1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Input trigger */ +1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR &= ~TIM_SMCR_TS; +1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= InputTrigger; +1865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Capture Compare preload feature */ +1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= TIM_CR2_CCPC; +1869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Commutation event source */ +1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 &= ~TIM_CR2_CCUS; +1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= CommutationSource; +1872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable Commutation DMA request */ +1874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); +1875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Commutation Interrupt */ +1877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); +1878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_UNLOCK(htim); +1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; +1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Configure the TIM commutation event sequence with DMA. +1886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @note This function is mandatory to use the commutation event in order to +1887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * update the configuration at each commutation detection on the TRGI input of the Timer, +1888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * the typical use of this feature is with the use of another Timer(interface Timer) +1889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * configured in Hall sensor interface, this interface Timer will generate the +1890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * commutation at its TRGO output (connected to Timer used in this function) each time +1891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * the TI1 of the Interface Timer detect a commutation at its input TI1. +1892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @note The user should configure the DMA in his own software, in This function only the COMDE b +1893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM handle +1894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall +1895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TS_ITR0: Internal trigger 0 selected +1897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TS_ITR1: Internal trigger 1 selected +1898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TS_ITR2: Internal trigger 2 selected +1899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TS_ITR3: Internal trigger 3 selected +1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TS_NONE: No trigger is needed +1901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param CommutationSource the Commutation Event source +1902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer +1904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG +1905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status +1906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, +1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t CommutationSource) +1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +1911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); +1912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + ARM GAS /tmp/cc3heCqB.s page 35 + + +1913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_LOCK(htim); +1915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || +1917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) +1918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Input trigger */ +1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR &= ~TIM_SMCR_TS; +1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= InputTrigger; +1922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Capture Compare preload feature */ +1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= TIM_CR2_CCPC; +1926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Commutation event source */ +1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 &= ~TIM_CR2_CCUS; +1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= CommutationSource; +1929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Commutation DMA Request */ +1931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA Commutation Callback */ +1932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; +1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; +1934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA error callback */ +1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; +1936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Disable Commutation Interrupt */ +1938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); +1939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the Commutation DMA Request */ +1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); +1942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_UNLOCK(htim); +1944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; +1946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +1949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Configures the TIM in master mode. +1950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM handle. +1951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that +1952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * contains the selected trigger output (TRGO) and the Master/Slave +1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * mode. +1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status +1955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, +1957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** const TIM_MasterConfigTypeDef *sMasterConfi +1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpcr2; +1960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; +1961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +1963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); +1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); +1965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); +1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check input state */ +1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_LOCK(htim); +1969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + ARM GAS /tmp/cc3heCqB.s page 36 + + +1970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Change the handler state */ +1971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_BUSY; +1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Get the TIMx CR2 register value */ +1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmpcr2 = htim->Instance->CR2; +1975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Get the TIMx SMCR register value */ +1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR; +1978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ +1980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) +1981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +1982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +1983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); +1984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Clear the MMS2 bits */ +1986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmpcr2 &= ~TIM_CR2_MMS2; +1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the TRGO2 source*/ +1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmpcr2 |= sMasterConfig->MasterOutputTrigger2; +1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +1990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Reset the MMS Bits */ +1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmpcr2 &= ~TIM_CR2_MMS; +1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the TRGO source */ +1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmpcr2 |= sMasterConfig->MasterOutputTrigger; +1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Update TIMx CR2 */ +1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 = tmpcr2; +1998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) +2000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Reset the MSM Bit */ +2002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmpsmcr &= ~TIM_SMCR_MSM; +2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set master mode */ +2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmpsmcr |= sMasterConfig->MasterSlaveMode; +2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Update TIMx SMCR */ +2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR = tmpsmcr; +2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Change the htim state */ +2011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_READY; +2012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_UNLOCK(htim); +2014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; +2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State +2020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * and the AOE(automatic output enable). +2021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM handle +2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that +2023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * contains the BDTR Register configuration information for the TIM peripheral. +2024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @note Interrupts can be generated when an active level is detected on the +2025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * break input, the break 2 input or the system break input. Break +2026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + ARM GAS /tmp/cc3heCqB.s page 37 + + +2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status +2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, +2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTim +2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Keep this variable initialized to 0 as it is used to configure BDTR register */ +2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpbdtr = 0U; +2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); +2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); +2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); +2041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); +2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); +2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); +2045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check input state */ +2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_LOCK(htim); +2048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, +2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** the OSSI State, the dead time value and the Automatic Output Enable Bit */ +2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the BDTR bits */ +2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); +2054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); +2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); +2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); +2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); +2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); +2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); +2060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); +2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) +2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); +2066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); +2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); +2068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the BREAK2 input related BDTR bits */ +2070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); +2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); +2072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); +2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set TIMx_BDTR */ +2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->BDTR = tmpbdtr; +2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_UNLOCK(htim); +2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; +2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if defined(TIM_BREAK_INPUT_SUPPORT) +2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + ARM GAS /tmp/cc3heCqB.s page 38 + + +2084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Configures the break input source. +2086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM handle. +2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param BreakInput Break input to configure +2088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_BREAKINPUT_BRK: Timer break input +2090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input +2091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param sBreakInputConfig Break input source configuration +2092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status +2093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, +2095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t BreakInput, +2096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig +2097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; +2099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmporx; +2100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t bkin_enable_mask; +2101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t bkin_polarity_mask; +2102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t bkin_enable_bitpos; +2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t bkin_polarity_bitpos; +2104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +2106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); +2107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAKINPUT(BreakInput)); +2108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); +2109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); +2110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if defined(DFSDM1_Channel0) +2111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) +2112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); +2114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #else +2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); +2117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* DFSDM1_Channel0 */ +2118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check input state */ +2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_LOCK(htim); +2121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** switch (sBreakInputConfig->Source) +2123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_BREAKINPUTSOURCE_BKIN: +2125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** bkin_enable_mask = TIM1_AF1_BKINE; +2127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** bkin_enable_bitpos = TIM1_AF1_BKINE_Pos; +2128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** bkin_polarity_mask = TIM1_AF1_BKINP; +2129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos; +2130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if defined(DFSDM1_Channel0) +2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_BREAKINPUTSOURCE_DFSDM1: +2134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** bkin_enable_mask = TIM1_AF1_BKDF1BKE; +2136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** bkin_enable_bitpos = TIM1_AF1_BKDF1BKE_Pos; +2137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** bkin_polarity_mask = 0U; +2138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** bkin_polarity_bitpos = 0U; +2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +2140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + ARM GAS /tmp/cc3heCqB.s page 39 + + +2141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* DFSDM1_Channel0 */ +2142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** default: +2144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** bkin_enable_mask = 0U; +2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** bkin_polarity_mask = 0U; +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** bkin_enable_bitpos = 0U; +2148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** bkin_polarity_bitpos = 0U; +2149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** switch (BreakInput) +2154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_BREAKINPUT_BRK: +2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Get the TIMx_AF1 register value */ +2158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmporx = htim->Instance->AF1; +2159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the break input */ +2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmporx &= ~bkin_enable_mask; +2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; +2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the break input polarity */ +2165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if defined(DFSDM1_Channel0) +2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) +2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* DFSDM1_Channel0 */ +2168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmporx &= ~bkin_polarity_mask; +2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; +2171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set TIMx_AF1 */ +2174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->AF1 = tmporx; +2175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +2176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** case TIM_BREAKINPUT_BRK2: +2178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Get the TIMx_AF2 register value */ +2180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmporx = htim->Instance->AF2; +2181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Enable the break input */ +2183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmporx &= ~bkin_enable_mask; +2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; +2185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the break input polarity */ +2187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if defined(DFSDM1_Channel0) +2188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) +2189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* DFSDM1_Channel0 */ +2190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmporx &= ~bkin_polarity_mask; +2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; +2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set TIMx_AF2 */ +2196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->AF2 = tmporx; +2197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + ARM GAS /tmp/cc3heCqB.s page 40 + + +2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** default: +2200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** status = HAL_ERROR; +2201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; +2202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_UNLOCK(htim); +2205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return status; +2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /*TIM_BREAK_INPUT_SUPPORT */ +2209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +2211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Configures the TIMx Remapping input capabilities. +2212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM handle. +2213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param Remap specifies the TIM remapping source. +2214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +2215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default +2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output. +2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. +2218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. +2219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) +2220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock. +2221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock. +2222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. +2223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default +2224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TIM11_SPDIF: SPDIF Frame synchronous +2225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock +2226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * (HSE divided by a programmable prescaler) +2227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_TIM11_MCO1: TIM11 CH1 input is connected to MCO1 +2228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * +2229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status +2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +2232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check parameters */ +2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); +2235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_REMAP(Remap)); +2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_LOCK(htim); +2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the Timer remapping configuration */ +2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->OR = Remap; +2241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_READY; +2243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_UNLOCK(htim); +2245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; +2247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +2250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Group channel 5 and channel 1, 2 or 3 +2251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM handle. +2252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param Channels specifies the reference signal(s) the OC5REF is combined with. +2253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be any combination of the following values: +2254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC + ARM GAS /tmp/cc3heCqB.s page 41 + + +2255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF +2256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF +2257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF +2258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL status +2259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) +2261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check parameters */ +2263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); +2264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_GROUPCH5(Channels)); +2265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Process Locked */ +2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_LOCK(htim); +2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_BUSY; +2270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Clear GC5Cx bit fields */ +2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); +2273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set GC5Cx bit fields */ +2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CCR5 |= Channels; +2276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Change the htim state */ +2278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_READY; +2279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __HAL_UNLOCK(htim); +2281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return HAL_OK; +2283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +2286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @} +2287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions +2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Extended Callbacks functions +2291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * +2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @verbatim +2293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ============================================================================== +2294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ##### Extended Callbacks functions ##### +2295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ============================================================================== +2296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** [..] +2297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** This section provides Extended TIM callback functions: +2298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Timer Commutation callback +2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (+) Timer Break callback +2300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @endverbatim +2302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @{ +2303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +2306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Commutation callback in non-blocking mode +2307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM handle +2308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval None +2309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + ARM GAS /tmp/cc3heCqB.s page 42 + + +2312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Prevent unused argument(s) compilation warning */ +2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** UNUSED(htim); +2314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** the HAL_TIMEx_CommutCallback could be implemented in the user file +2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +2320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Commutation half complete callback in non-blocking mode +2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM handle +2322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval None +2323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +2325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Prevent unused argument(s) compilation warning */ +2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** UNUSED(htim); +2328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +2330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file +2331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +2335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Break detection callback in non-blocking mode +2336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM handle +2337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval None +2338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Prevent unused argument(s) compilation warning */ +2342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** UNUSED(htim); +2343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** the HAL_TIMEx_BreakCallback could be implemented in the user file +2346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +2350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Break2 detection callback in non blocking mode +2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim: TIM handle +2352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval None +2353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Prevent unused argument(s) compilation warning */ +2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** UNUSED(htim); +2358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** the HAL_TIMEx_Break2Callback could be implemented in the user file +2361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +2364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @} +2365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions +2368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Extended Peripheral State functions + ARM GAS /tmp/cc3heCqB.s page 43 + + +2369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * +2370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @verbatim +2371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ============================================================================== +2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ##### Extended Peripheral State functions ##### +2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** ============================================================================== +2374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** [..] +2375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** This subsection permits to get in run-time the status of the peripheral +2376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** and the data flow. +2377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** @endverbatim +2379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @{ +2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +2383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Return the TIM Hall Sensor interface handle state. +2384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor handle +2385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval HAL state +2386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) +2388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return htim->State; +2390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +2393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Return actual state of the TIM complementary channel. +2394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param htim TIM handle +2395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param ChannelN TIM Complementary channel +2396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +2397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 +2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 +2399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 +2400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval TIM Complementary channel state +2401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t Cha +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_state; +2405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ +2407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); +2408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); +2410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return channel_state; +2412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +2414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @} +2415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +2418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @} +2419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Private functions ---------------------------------------------------------*/ +2422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions +2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @{ +2424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + ARM GAS /tmp/cc3heCqB.s page 44 + + +2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +2427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief TIM DMA Commutation callback. +2428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param hdma pointer to DMA handle. +2429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval None +2430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +2432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; +2434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Change the htim state */ +2436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_READY; +2437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +2439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->CommutationCallback(htim); +2440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #else +2441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIMEx_CommutCallback(htim); +2442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +2443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +2446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief TIM DMA Commutation half complete callback. +2447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param hdma pointer to DMA handle. +2448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval None +2449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +2451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; +2453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Change the htim state */ +2455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_READY; +2456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +2458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->CommutationHalfCpltCallback(htim); +2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #else +2460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIMEx_CommutHalfCpltCallback(htim); +2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +2466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief TIM DMA Delay Pulse complete callback (complementary channel). +2467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param hdma pointer to DMA handle. +2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval None +2469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +2471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; +2473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (hdma == htim->hdma[TIM_DMA_ID_CC1]) +2475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; +2477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (hdma->Init.Mode == DMA_NORMAL) +2479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +2481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + ARM GAS /tmp/cc3heCqB.s page 45 + + +2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) +2484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; +2486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (hdma->Init.Mode == DMA_NORMAL) +2488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +2490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) +2493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; +2495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (hdma->Init.Mode == DMA_NORMAL) +2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); +2499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else +2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* nothing to do */ +2504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +2507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->PWM_PulseFinishedCallback(htim); +2508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #else +2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); +2510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +2511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +2513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +2516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief TIM DMA error callback (complementary channel) +2517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param hdma pointer to DMA handle. +2518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval None +2519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +2521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; +2523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (hdma == htim->hdma[TIM_DMA_ID_CC1]) +2525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; +2527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); +2528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) +2530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; +2532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); +2533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) +2535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; +2537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); +2538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** else + ARM GAS /tmp/cc3heCqB.s page 46 + + +2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { +2541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* nothing to do */ +2542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->ErrorCallback(htim); +2546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #else +2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ErrorCallback(htim); +2548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +2549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +2551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } +2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** +2554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @brief Enables or disables the TIM Capture Compare Channel xN. +2555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param TIMx to select the TIM peripheral +2556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param Channel specifies the TIM Channel +2557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be one of the following values: +2558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 +2559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 +2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 +2561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @param ChannelNState specifies the TIM Channel CCxNE bit new state. +2562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. +2563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** * @retval None +2564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** */ +2565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +2566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 28 .loc 1 2566 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. +2567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmp; + 33 .loc 1 2567 3 view .LVU1 +2568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ + 34 .loc 1 2569 3 view .LVU2 + 35 .loc 1 2569 36 is_stmt 0 view .LVU3 + 36 0000 01F00F01 and r1, r1, #15 + 37 .LVL1: + 38 .loc 1 2569 7 view .LVU4 + 39 0004 4FF0040C mov ip, #4 + 40 0008 0CFA01FC lsl ip, ip, r1 + 41 .LVL2: +2570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Reset the CCxNE Bit */ +2572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIMx->CCER &= ~tmp; + 42 .loc 1 2572 3 is_stmt 1 view .LVU5 + 43 .loc 1 2572 7 is_stmt 0 view .LVU6 + 44 000c 036A ldr r3, [r0, #32] + 45 .loc 1 2572 14 view .LVU7 + 46 000e 23EA0C03 bic r3, r3, ip + 47 0012 0362 str r3, [r0, #32] +2573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** +2574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set or reset the CCxNE Bit */ +2575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ + 48 .loc 1 2575 3 is_stmt 1 view .LVU8 + ARM GAS /tmp/cc3heCqB.s page 47 + + + 49 .loc 1 2575 7 is_stmt 0 view .LVU9 + 50 0014 036A ldr r3, [r0, #32] + 51 .loc 1 2575 42 view .LVU10 + 52 0016 8A40 lsls r2, r2, r1 + 53 .LVL3: + 54 .loc 1 2575 14 view .LVU11 + 55 0018 1343 orrs r3, r3, r2 + 56 001a 0362 str r3, [r0, #32] +2576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 57 .loc 1 2576 1 view .LVU12 + 58 001c 7047 bx lr + 59 .cfi_endproc + 60 .LFE185: + 62 .section .text.TIM_DMAErrorCCxN,"ax",%progbits + 63 .align 1 + 64 .syntax unified + 65 .thumb + 66 .thumb_func + 68 TIM_DMAErrorCCxN: + 69 .LVL4: + 70 .LFB184: +2521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 71 .loc 1 2521 1 is_stmt 1 view -0 + 72 .cfi_startproc + 73 @ args = 0, pretend = 0, frame = 0 + 74 @ frame_needed = 0, uses_anonymous_args = 0 +2521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 75 .loc 1 2521 1 is_stmt 0 view .LVU14 + 76 0000 10B5 push {r4, lr} + 77 .LCFI0: + 78 .cfi_def_cfa_offset 8 + 79 .cfi_offset 4, -8 + 80 .cfi_offset 14, -4 +2522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 81 .loc 1 2522 3 is_stmt 1 view .LVU15 +2522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 82 .loc 1 2522 22 is_stmt 0 view .LVU16 + 83 0002 846B ldr r4, [r0, #56] + 84 .LVL5: +2524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 85 .loc 1 2524 3 is_stmt 1 view .LVU17 +2524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 86 .loc 1 2524 25 is_stmt 0 view .LVU18 + 87 0004 636A ldr r3, [r4, #36] +2524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 88 .loc 1 2524 6 view .LVU19 + 89 0006 8342 cmp r3, r0 + 90 0008 0BD0 beq .L7 +2529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 91 .loc 1 2529 8 is_stmt 1 view .LVU20 +2529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 92 .loc 1 2529 30 is_stmt 0 view .LVU21 + 93 000a A36A ldr r3, [r4, #40] +2529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 94 .loc 1 2529 11 view .LVU22 + 95 000c 8342 cmp r3, r0 + 96 000e 0DD0 beq .L8 + ARM GAS /tmp/cc3heCqB.s page 48 + + +2534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 97 .loc 1 2534 8 is_stmt 1 view .LVU23 +2534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 98 .loc 1 2534 30 is_stmt 0 view .LVU24 + 99 0010 E36A ldr r3, [r4, #44] +2534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 100 .loc 1 2534 11 view .LVU25 + 101 0012 8342 cmp r3, r0 + 102 0014 10D0 beq .L9 + 103 .L4: +2542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 104 .loc 1 2542 3 is_stmt 1 view .LVU26 +2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 105 .loc 1 2547 3 view .LVU27 + 106 0016 2046 mov r0, r4 + 107 .LVL6: +2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 108 .loc 1 2547 3 is_stmt 0 view .LVU28 + 109 0018 FFF7FEFF bl HAL_TIM_ErrorCallback + 110 .LVL7: +2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 111 .loc 1 2550 3 is_stmt 1 view .LVU29 +2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 112 .loc 1 2550 17 is_stmt 0 view .LVU30 + 113 001c 0023 movs r3, #0 + 114 001e 2377 strb r3, [r4, #28] +2551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 115 .loc 1 2551 1 view .LVU31 + 116 0020 10BD pop {r4, pc} + 117 .LVL8: + 118 .L7: +2526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 119 .loc 1 2526 5 is_stmt 1 view .LVU32 +2526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 120 .loc 1 2526 19 is_stmt 0 view .LVU33 + 121 0022 0123 movs r3, #1 + 122 0024 2377 strb r3, [r4, #28] +2527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 123 .loc 1 2527 5 is_stmt 1 view .LVU34 + 124 0026 84F84430 strb r3, [r4, #68] + 125 002a F4E7 b .L4 + 126 .L8: +2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 127 .loc 1 2531 5 view .LVU35 +2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 128 .loc 1 2531 19 is_stmt 0 view .LVU36 + 129 002c 0223 movs r3, #2 + 130 002e 2377 strb r3, [r4, #28] +2532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 131 .loc 1 2532 5 is_stmt 1 view .LVU37 + 132 0030 0123 movs r3, #1 + 133 0032 84F84530 strb r3, [r4, #69] + 134 0036 EEE7 b .L4 + 135 .L9: +2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + 136 .loc 1 2536 5 view .LVU38 +2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + ARM GAS /tmp/cc3heCqB.s page 49 + + + 137 .loc 1 2536 19 is_stmt 0 view .LVU39 + 138 0038 0423 movs r3, #4 + 139 003a 2377 strb r3, [r4, #28] +2537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 140 .loc 1 2537 5 is_stmt 1 view .LVU40 + 141 003c 0123 movs r3, #1 + 142 003e 84F84630 strb r3, [r4, #70] + 143 0042 E8E7 b .L4 + 144 .cfi_endproc + 145 .LFE184: + 147 .section .text.TIM_DMADelayPulseNCplt,"ax",%progbits + 148 .align 1 + 149 .syntax unified + 150 .thumb + 151 .thumb_func + 153 TIM_DMADelayPulseNCplt: + 154 .LVL9: + 155 .LFB183: +2471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 156 .loc 1 2471 1 view -0 + 157 .cfi_startproc + 158 @ args = 0, pretend = 0, frame = 0 + 159 @ frame_needed = 0, uses_anonymous_args = 0 +2471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 160 .loc 1 2471 1 is_stmt 0 view .LVU42 + 161 0000 10B5 push {r4, lr} + 162 .LCFI1: + 163 .cfi_def_cfa_offset 8 + 164 .cfi_offset 4, -8 + 165 .cfi_offset 14, -4 +2472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 166 .loc 1 2472 3 is_stmt 1 view .LVU43 +2472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 167 .loc 1 2472 22 is_stmt 0 view .LVU44 + 168 0002 846B ldr r4, [r0, #56] + 169 .LVL10: +2474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 170 .loc 1 2474 3 is_stmt 1 view .LVU45 +2474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 171 .loc 1 2474 25 is_stmt 0 view .LVU46 + 172 0004 636A ldr r3, [r4, #36] +2474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 173 .loc 1 2474 6 view .LVU47 + 174 0006 8342 cmp r3, r0 + 175 0008 0BD0 beq .L15 +2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 176 .loc 1 2483 8 is_stmt 1 view .LVU48 +2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 177 .loc 1 2483 30 is_stmt 0 view .LVU49 + 178 000a A36A ldr r3, [r4, #40] +2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 179 .loc 1 2483 11 view .LVU50 + 180 000c 8342 cmp r3, r0 + 181 000e 11D0 beq .L16 +2492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 182 .loc 1 2492 8 is_stmt 1 view .LVU51 +2492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + ARM GAS /tmp/cc3heCqB.s page 50 + + + 183 .loc 1 2492 30 is_stmt 0 view .LVU52 + 184 0010 E36A ldr r3, [r4, #44] +2492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 185 .loc 1 2492 11 view .LVU53 + 186 0012 8342 cmp r3, r0 + 187 0014 17D0 beq .L17 + 188 .L12: +2504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 189 .loc 1 2504 3 is_stmt 1 view .LVU54 +2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 190 .loc 1 2509 3 view .LVU55 + 191 0016 2046 mov r0, r4 + 192 .LVL11: +2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 193 .loc 1 2509 3 is_stmt 0 view .LVU56 + 194 0018 FFF7FEFF bl HAL_TIM_PWM_PulseFinishedCallback + 195 .LVL12: +2512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 196 .loc 1 2512 3 is_stmt 1 view .LVU57 +2512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 197 .loc 1 2512 17 is_stmt 0 view .LVU58 + 198 001c 0023 movs r3, #0 + 199 001e 2377 strb r3, [r4, #28] +2513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 200 .loc 1 2513 1 view .LVU59 + 201 0020 10BD pop {r4, pc} + 202 .LVL13: + 203 .L15: +2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 204 .loc 1 2476 5 is_stmt 1 view .LVU60 +2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 205 .loc 1 2476 19 is_stmt 0 view .LVU61 + 206 0022 0123 movs r3, #1 + 207 0024 2377 strb r3, [r4, #28] +2478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 208 .loc 1 2478 5 is_stmt 1 view .LVU62 +2478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 209 .loc 1 2478 19 is_stmt 0 view .LVU63 + 210 0026 C369 ldr r3, [r0, #28] +2478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 211 .loc 1 2478 8 view .LVU64 + 212 0028 002B cmp r3, #0 + 213 002a F4D1 bne .L12 +2480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 214 .loc 1 2480 7 is_stmt 1 view .LVU65 + 215 002c 0123 movs r3, #1 + 216 002e 84F84430 strb r3, [r4, #68] + 217 0032 F0E7 b .L12 + 218 .L16: +2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 219 .loc 1 2485 5 view .LVU66 +2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 220 .loc 1 2485 19 is_stmt 0 view .LVU67 + 221 0034 0223 movs r3, #2 + 222 0036 2377 strb r3, [r4, #28] +2487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 223 .loc 1 2487 5 is_stmt 1 view .LVU68 + ARM GAS /tmp/cc3heCqB.s page 51 + + +2487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 224 .loc 1 2487 19 is_stmt 0 view .LVU69 + 225 0038 C369 ldr r3, [r0, #28] +2487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 226 .loc 1 2487 8 view .LVU70 + 227 003a 002B cmp r3, #0 + 228 003c EBD1 bne .L12 +2489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 229 .loc 1 2489 7 is_stmt 1 view .LVU71 + 230 003e 0123 movs r3, #1 + 231 0040 84F84530 strb r3, [r4, #69] + 232 0044 E7E7 b .L12 + 233 .L17: +2494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 234 .loc 1 2494 5 view .LVU72 +2494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 235 .loc 1 2494 19 is_stmt 0 view .LVU73 + 236 0046 0423 movs r3, #4 + 237 0048 2377 strb r3, [r4, #28] +2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 238 .loc 1 2496 5 is_stmt 1 view .LVU74 +2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 239 .loc 1 2496 19 is_stmt 0 view .LVU75 + 240 004a C369 ldr r3, [r0, #28] +2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 241 .loc 1 2496 8 view .LVU76 + 242 004c 002B cmp r3, #0 + 243 004e E2D1 bne .L12 +2498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 244 .loc 1 2498 7 is_stmt 1 view .LVU77 + 245 0050 0123 movs r3, #1 + 246 0052 84F84630 strb r3, [r4, #70] + 247 0056 DEE7 b .L12 + 248 .cfi_endproc + 249 .LFE183: + 251 .section .text.HAL_TIMEx_HallSensor_MspInit,"ax",%progbits + 252 .align 1 + 253 .weak HAL_TIMEx_HallSensor_MspInit + 254 .syntax unified + 255 .thumb + 256 .thumb_func + 258 HAL_TIMEx_HallSensor_MspInit: + 259 .LVL14: + 260 .LFB143: + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Prevent unused argument(s) compilation warning */ + 261 .loc 1 287 1 view -0 + 262 .cfi_startproc + 263 @ args = 0, pretend = 0, frame = 0 + 264 @ frame_needed = 0, uses_anonymous_args = 0 + 265 @ link register save eliminated. + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 266 .loc 1 289 3 view .LVU79 + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 267 .loc 1 294 1 is_stmt 0 view .LVU80 + 268 0000 7047 bx lr + 269 .cfi_endproc + 270 .LFE143: + ARM GAS /tmp/cc3heCqB.s page 52 + + + 272 .section .text.HAL_TIMEx_HallSensor_Init,"ax",%progbits + 273 .align 1 + 274 .global HAL_TIMEx_HallSensor_Init + 275 .syntax unified + 276 .thumb + 277 .thumb_func + 279 HAL_TIMEx_HallSensor_Init: + 280 .LVL15: + 281 .LFB141: + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_OC_InitTypeDef OC_Config; + 282 .loc 1 140 1 is_stmt 1 view -0 + 283 .cfi_startproc + 284 @ args = 0, pretend = 0, frame = 32 + 285 @ frame_needed = 0, uses_anonymous_args = 0 + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 286 .loc 1 141 3 view .LVU82 + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 287 .loc 1 144 3 view .LVU83 + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 288 .loc 1 144 6 is_stmt 0 view .LVU84 + 289 0000 0028 cmp r0, #0 + 290 0002 65D0 beq .L22 + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_OC_InitTypeDef OC_Config; + 291 .loc 1 140 1 view .LVU85 + 292 0004 70B5 push {r4, r5, r6, lr} + 293 .LCFI2: + 294 .cfi_def_cfa_offset 16 + 295 .cfi_offset 4, -16 + 296 .cfi_offset 5, -12 + 297 .cfi_offset 6, -8 + 298 .cfi_offset 14, -4 + 299 0006 88B0 sub sp, sp, #32 + 300 .LCFI3: + 301 .cfi_def_cfa_offset 48 + 302 0008 0E46 mov r6, r1 + 303 000a 0446 mov r4, r0 + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + 304 .loc 1 150 3 is_stmt 1 view .LVU86 + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + 305 .loc 1 151 3 view .LVU87 + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + 306 .loc 1 152 3 view .LVU88 + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + 307 .loc 1 153 3 view .LVU89 + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + 308 .loc 1 154 3 view .LVU90 + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + 309 .loc 1 155 3 view .LVU91 + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + 310 .loc 1 156 3 view .LVU92 + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 311 .loc 1 157 3 view .LVU93 + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 312 .loc 1 159 3 view .LVU94 + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 313 .loc 1 159 11 is_stmt 0 view .LVU95 + 314 000c 90F83D30 ldrb r3, [r0, #61] @ zero_extendqisi2 + ARM GAS /tmp/cc3heCqB.s page 53 + + + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 315 .loc 1 159 6 view .LVU96 + 316 0010 002B cmp r3, #0 + 317 0012 58D0 beq .L27 + 318 .LVL16: + 319 .L21: + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 320 .loc 1 181 3 is_stmt 1 view .LVU97 + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 321 .loc 1 181 15 is_stmt 0 view .LVU98 + 322 0014 0223 movs r3, #2 + 323 0016 84F83D30 strb r3, [r4, #61] + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 324 .loc 1 184 3 is_stmt 1 view .LVU99 + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 325 .loc 1 184 38 is_stmt 0 view .LVU100 + 326 001a 2146 mov r1, r4 + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 327 .loc 1 184 3 view .LVU101 + 328 001c 51F8040B ldr r0, [r1], #4 + 329 0020 FFF7FEFF bl TIM_Base_SetConfig + 330 .LVL17: + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 331 .loc 1 187 3 is_stmt 1 view .LVU102 + 332 0024 B368 ldr r3, [r6, #8] + 333 0026 0322 movs r2, #3 + 334 0028 3168 ldr r1, [r6] + 335 002a 2068 ldr r0, [r4] + 336 002c FFF7FEFF bl TIM_TI1_SetConfig + 337 .LVL18: + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the IC1PSC value */ + 338 .loc 1 190 3 view .LVU103 + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the IC1PSC value */ + 339 .loc 1 190 7 is_stmt 0 view .LVU104 + 340 0030 2268 ldr r2, [r4] + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the IC1PSC value */ + 341 .loc 1 190 17 view .LVU105 + 342 0032 9369 ldr r3, [r2, #24] + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the IC1PSC value */ + 343 .loc 1 190 25 view .LVU106 + 344 0034 23F00C03 bic r3, r3, #12 + 345 0038 9361 str r3, [r2, #24] + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 346 .loc 1 192 3 is_stmt 1 view .LVU107 + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 347 .loc 1 192 7 is_stmt 0 view .LVU108 + 348 003a 2268 ldr r2, [r4] + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 349 .loc 1 192 17 view .LVU109 + 350 003c 9369 ldr r3, [r2, #24] + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 351 .loc 1 192 35 view .LVU110 + 352 003e 7168 ldr r1, [r6, #4] + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 353 .loc 1 192 25 view .LVU111 + 354 0040 0B43 orrs r3, r3, r1 + 355 0042 9361 str r3, [r2, #24] + ARM GAS /tmp/cc3heCqB.s page 54 + + + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 356 .loc 1 195 3 is_stmt 1 view .LVU112 + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 357 .loc 1 195 7 is_stmt 0 view .LVU113 + 358 0044 2268 ldr r2, [r4] + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 359 .loc 1 195 17 view .LVU114 + 360 0046 5368 ldr r3, [r2, #4] + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 361 .loc 1 195 23 view .LVU115 + 362 0048 43F08003 orr r3, r3, #128 + 363 004c 5360 str r3, [r2, #4] + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= TIM_TS_TI1F_ED; + 364 .loc 1 198 3 is_stmt 1 view .LVU116 + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= TIM_TS_TI1F_ED; + 365 .loc 1 198 7 is_stmt 0 view .LVU117 + 366 004e 2268 ldr r2, [r4] + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= TIM_TS_TI1F_ED; + 367 .loc 1 198 17 view .LVU118 + 368 0050 9368 ldr r3, [r2, #8] + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= TIM_TS_TI1F_ED; + 369 .loc 1 198 24 view .LVU119 + 370 0052 23F07003 bic r3, r3, #112 + 371 0056 9360 str r3, [r2, #8] + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 372 .loc 1 199 3 is_stmt 1 view .LVU120 + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 373 .loc 1 199 7 is_stmt 0 view .LVU121 + 374 0058 2268 ldr r2, [r4] + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 375 .loc 1 199 17 view .LVU122 + 376 005a 9368 ldr r3, [r2, #8] + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 377 .loc 1 199 24 view .LVU123 + 378 005c 43F04003 orr r3, r3, #64 + 379 0060 9360 str r3, [r2, #8] + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + 380 .loc 1 202 3 is_stmt 1 view .LVU124 + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + 381 .loc 1 202 7 is_stmt 0 view .LVU125 + 382 0062 2268 ldr r2, [r4] + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + 383 .loc 1 202 17 view .LVU126 + 384 0064 9168 ldr r1, [r2, #8] + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + 385 .loc 1 202 24 view .LVU127 + 386 0066 1B4B ldr r3, .L28 + 387 0068 0B40 ands r3, r3, r1 + 388 006a 9360 str r3, [r2, #8] + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 389 .loc 1 203 3 is_stmt 1 view .LVU128 + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 390 .loc 1 203 7 is_stmt 0 view .LVU129 + 391 006c 2268 ldr r2, [r4] + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 392 .loc 1 203 17 view .LVU130 + 393 006e 9368 ldr r3, [r2, #8] + ARM GAS /tmp/cc3heCqB.s page 55 + + + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 394 .loc 1 203 24 view .LVU131 + 395 0070 43F00403 orr r3, r3, #4 + 396 0074 9360 str r3, [r2, #8] + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + 397 .loc 1 206 3 is_stmt 1 view .LVU132 + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + 398 .loc 1 206 24 is_stmt 0 view .LVU133 + 399 0076 0025 movs r5, #0 + 400 0078 0595 str r5, [sp, #20] + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** OC_Config.OCMode = TIM_OCMODE_PWM2; + 401 .loc 1 207 3 is_stmt 1 view .LVU134 + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** OC_Config.OCMode = TIM_OCMODE_PWM2; + 402 .loc 1 207 25 is_stmt 0 view .LVU135 + 403 007a 0695 str r5, [sp, #24] + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + 404 .loc 1 208 3 is_stmt 1 view .LVU136 + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + 405 .loc 1 208 20 is_stmt 0 view .LVU137 + 406 007c 7023 movs r3, #112 + 407 007e 0193 str r3, [sp, #4] + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + 408 .loc 1 209 3 is_stmt 1 view .LVU138 + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + 409 .loc 1 209 26 is_stmt 0 view .LVU139 + 410 0080 0795 str r5, [sp, #28] + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + 411 .loc 1 210 3 is_stmt 1 view .LVU140 + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + 412 .loc 1 210 25 is_stmt 0 view .LVU141 + 413 0082 0495 str r5, [sp, #16] + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** OC_Config.Pulse = sConfig->Commutation_Delay; + 414 .loc 1 211 3 is_stmt 1 view .LVU142 + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** OC_Config.Pulse = sConfig->Commutation_Delay; + 415 .loc 1 211 24 is_stmt 0 view .LVU143 + 416 0084 0395 str r5, [sp, #12] + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 417 .loc 1 212 3 is_stmt 1 view .LVU144 + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 418 .loc 1 212 28 is_stmt 0 view .LVU145 + 419 0086 F368 ldr r3, [r6, #12] + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 420 .loc 1 212 19 view .LVU146 + 421 0088 0293 str r3, [sp, #8] + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 422 .loc 1 214 3 is_stmt 1 view .LVU147 + 423 008a 01A9 add r1, sp, #4 + 424 008c 2068 ldr r0, [r4] + 425 008e FFF7FEFF bl TIM_OC2_SetConfig + 426 .LVL19: + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= TIM_TRGO_OC2REF; + 427 .loc 1 218 3 view .LVU148 + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= TIM_TRGO_OC2REF; + 428 .loc 1 218 7 is_stmt 0 view .LVU149 + 429 0092 2268 ldr r2, [r4] + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= TIM_TRGO_OC2REF; + 430 .loc 1 218 17 view .LVU150 + ARM GAS /tmp/cc3heCqB.s page 56 + + + 431 0094 5368 ldr r3, [r2, #4] + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= TIM_TRGO_OC2REF; + 432 .loc 1 218 23 view .LVU151 + 433 0096 23F07003 bic r3, r3, #112 + 434 009a 5360 str r3, [r2, #4] + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 435 .loc 1 219 3 is_stmt 1 view .LVU152 + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 436 .loc 1 219 7 is_stmt 0 view .LVU153 + 437 009c 2268 ldr r2, [r4] + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 438 .loc 1 219 17 view .LVU154 + 439 009e 5368 ldr r3, [r2, #4] + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 440 .loc 1 219 23 view .LVU155 + 441 00a0 43F05003 orr r3, r3, #80 + 442 00a4 5360 str r3, [r2, #4] + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 443 .loc 1 222 3 is_stmt 1 view .LVU156 + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 444 .loc 1 222 23 is_stmt 0 view .LVU157 + 445 00a6 0123 movs r3, #1 + 446 00a8 84F84830 strb r3, [r4, #72] + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 447 .loc 1 225 3 is_stmt 1 view .LVU158 + 448 00ac 84F83E30 strb r3, [r4, #62] + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 449 .loc 1 226 3 view .LVU159 + 450 00b0 84F83F30 strb r3, [r4, #63] + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 451 .loc 1 227 3 view .LVU160 + 452 00b4 84F84430 strb r3, [r4, #68] + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 453 .loc 1 228 3 view .LVU161 + 454 00b8 84F84530 strb r3, [r4, #69] + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 455 .loc 1 231 3 view .LVU162 + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 456 .loc 1 231 15 is_stmt 0 view .LVU163 + 457 00bc 84F83D30 strb r3, [r4, #61] + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 458 .loc 1 233 3 is_stmt 1 view .LVU164 + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 459 .loc 1 233 10 is_stmt 0 view .LVU165 + 460 00c0 2846 mov r0, r5 + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 461 .loc 1 234 1 view .LVU166 + 462 00c2 08B0 add sp, sp, #32 + 463 .LCFI4: + 464 .cfi_remember_state + 465 .cfi_def_cfa_offset 16 + 466 @ sp needed + 467 00c4 70BD pop {r4, r5, r6, pc} + 468 .LVL20: + 469 .L27: + 470 .LCFI5: + 471 .cfi_restore_state + ARM GAS /tmp/cc3heCqB.s page 57 + + + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 472 .loc 1 162 5 is_stmt 1 view .LVU167 + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 473 .loc 1 162 16 is_stmt 0 view .LVU168 + 474 00c6 80F83C30 strb r3, [r0, #60] + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 475 .loc 1 176 5 is_stmt 1 view .LVU169 + 476 00ca FFF7FEFF bl HAL_TIMEx_HallSensor_MspInit + 477 .LVL21: + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 478 .loc 1 176 5 is_stmt 0 view .LVU170 + 479 00ce A1E7 b .L21 + 480 .LVL22: + 481 .L22: + 482 .LCFI6: + 483 .cfi_def_cfa_offset 0 + 484 .cfi_restore 4 + 485 .cfi_restore 5 + 486 .cfi_restore 6 + 487 .cfi_restore 14 + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 488 .loc 1 146 12 view .LVU171 + 489 00d0 0120 movs r0, #1 + 490 .LVL23: + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 491 .loc 1 234 1 view .LVU172 + 492 00d2 7047 bx lr + 493 .L29: + 494 .align 2 + 495 .L28: + 496 00d4 F8FFFEFF .word -65544 + 497 .cfi_endproc + 498 .LFE141: + 500 .section .text.HAL_TIMEx_HallSensor_MspDeInit,"ax",%progbits + 501 .align 1 + 502 .weak HAL_TIMEx_HallSensor_MspDeInit + 503 .syntax unified + 504 .thumb + 505 .thumb_func + 507 HAL_TIMEx_HallSensor_MspDeInit: + 508 .LVL24: + 509 .LFB144: + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Prevent unused argument(s) compilation warning */ + 510 .loc 1 302 1 is_stmt 1 view -0 + 511 .cfi_startproc + 512 @ args = 0, pretend = 0, frame = 0 + 513 @ frame_needed = 0, uses_anonymous_args = 0 + 514 @ link register save eliminated. + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 515 .loc 1 304 3 view .LVU174 + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 516 .loc 1 309 1 is_stmt 0 view .LVU175 + 517 0000 7047 bx lr + 518 .cfi_endproc + 519 .LFE144: + 521 .section .text.HAL_TIMEx_HallSensor_DeInit,"ax",%progbits + 522 .align 1 + ARM GAS /tmp/cc3heCqB.s page 58 + + + 523 .global HAL_TIMEx_HallSensor_DeInit + 524 .syntax unified + 525 .thumb + 526 .thumb_func + 528 HAL_TIMEx_HallSensor_DeInit: + 529 .LVL25: + 530 .LFB142: + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 531 .loc 1 242 1 is_stmt 1 view -0 + 532 .cfi_startproc + 533 @ args = 0, pretend = 0, frame = 0 + 534 @ frame_needed = 0, uses_anonymous_args = 0 + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 535 .loc 1 242 1 is_stmt 0 view .LVU177 + 536 0000 10B5 push {r4, lr} + 537 .LCFI7: + 538 .cfi_def_cfa_offset 8 + 539 .cfi_offset 4, -8 + 540 .cfi_offset 14, -4 + 541 0002 0446 mov r4, r0 + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 542 .loc 1 244 3 is_stmt 1 view .LVU178 + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 543 .loc 1 246 3 view .LVU179 + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 544 .loc 1 246 15 is_stmt 0 view .LVU180 + 545 0004 0223 movs r3, #2 + 546 0006 80F83D30 strb r3, [r0, #61] + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 547 .loc 1 249 3 is_stmt 1 view .LVU181 + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 548 .loc 1 249 3 view .LVU182 + 549 000a 0368 ldr r3, [r0] + 550 000c 196A ldr r1, [r3, #32] + 551 000e 41F21112 movw r2, #4369 + 552 0012 1142 tst r1, r2 + 553 0014 08D1 bne .L32 + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 554 .loc 1 249 3 discriminator 1 view .LVU183 + 555 0016 196A ldr r1, [r3, #32] + 556 0018 40F24442 movw r2, #1092 + 557 001c 1142 tst r1, r2 + 558 001e 03D1 bne .L32 + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 559 .loc 1 249 3 discriminator 3 view .LVU184 + 560 0020 1A68 ldr r2, [r3] + 561 0022 22F00102 bic r2, r2, #1 + 562 0026 1A60 str r2, [r3] + 563 .L32: + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 564 .loc 1 249 3 discriminator 5 view .LVU185 + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 565 .loc 1 260 3 view .LVU186 + 566 0028 2046 mov r0, r4 + 567 .LVL26: + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 568 .loc 1 260 3 is_stmt 0 view .LVU187 + ARM GAS /tmp/cc3heCqB.s page 59 + + + 569 002a FFF7FEFF bl HAL_TIMEx_HallSensor_MspDeInit + 570 .LVL27: + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 571 .loc 1 264 3 is_stmt 1 view .LVU188 + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 572 .loc 1 264 23 is_stmt 0 view .LVU189 + 573 002e 0020 movs r0, #0 + 574 0030 84F84800 strb r0, [r4, #72] + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + 575 .loc 1 267 3 is_stmt 1 view .LVU190 + 576 0034 84F83E00 strb r0, [r4, #62] + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + 577 .loc 1 268 3 view .LVU191 + 578 0038 84F83F00 strb r0, [r4, #63] + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + 579 .loc 1 269 3 view .LVU192 + 580 003c 84F84400 strb r0, [r4, #68] + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 581 .loc 1 270 3 view .LVU193 + 582 0040 84F84500 strb r0, [r4, #69] + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 583 .loc 1 273 3 view .LVU194 + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 584 .loc 1 273 15 is_stmt 0 view .LVU195 + 585 0044 84F83D00 strb r0, [r4, #61] + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 586 .loc 1 276 3 is_stmt 1 view .LVU196 + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 587 .loc 1 276 3 view .LVU197 + 588 0048 84F83C00 strb r0, [r4, #60] + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 589 .loc 1 276 3 view .LVU198 + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 590 .loc 1 278 3 view .LVU199 + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 591 .loc 1 279 1 is_stmt 0 view .LVU200 + 592 004c 10BD pop {r4, pc} + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 593 .loc 1 279 1 view .LVU201 + 594 .cfi_endproc + 595 .LFE142: + 597 .section .text.HAL_TIMEx_HallSensor_Start,"ax",%progbits + 598 .align 1 + 599 .global HAL_TIMEx_HallSensor_Start + 600 .syntax unified + 601 .thumb + 602 .thumb_func + 604 HAL_TIMEx_HallSensor_Start: + 605 .LVL28: + 606 .LFB145: + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 607 .loc 1 317 1 is_stmt 1 view -0 + 608 .cfi_startproc + 609 @ args = 0, pretend = 0, frame = 0 + 610 @ frame_needed = 0, uses_anonymous_args = 0 + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 611 .loc 1 317 1 is_stmt 0 view .LVU203 + ARM GAS /tmp/cc3heCqB.s page 60 + + + 612 0000 10B5 push {r4, lr} + 613 .LCFI8: + 614 .cfi_def_cfa_offset 8 + 615 .cfi_offset 4, -8 + 616 .cfi_offset 14, -4 + 617 0002 0446 mov r4, r0 + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 618 .loc 1 318 3 is_stmt 1 view .LVU204 + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 619 .loc 1 319 3 view .LVU205 + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 620 .loc 1 319 31 is_stmt 0 view .LVU206 + 621 0004 90F83E10 ldrb r1, [r0, #62] @ zero_extendqisi2 + 622 0008 C9B2 uxtb r1, r1 + 623 .LVL29: + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 624 .loc 1 320 3 is_stmt 1 view .LVU207 + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 625 .loc 1 320 31 is_stmt 0 view .LVU208 + 626 000a 90F83F20 ldrb r2, [r0, #63] @ zero_extendqisi2 + 627 000e D2B2 uxtb r2, r2 + 628 .LVL30: + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 629 .loc 1 321 3 is_stmt 1 view .LVU209 + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 630 .loc 1 321 31 is_stmt 0 view .LVU210 + 631 0010 90F84430 ldrb r3, [r0, #68] @ zero_extendqisi2 + 632 0014 D8B2 uxtb r0, r3 + 633 .LVL31: + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 634 .loc 1 322 3 is_stmt 1 view .LVU211 + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 635 .loc 1 322 31 is_stmt 0 view .LVU212 + 636 0016 94F84530 ldrb r3, [r4, #69] @ zero_extendqisi2 + 637 .LVL32: + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 638 .loc 1 325 3 is_stmt 1 view .LVU213 + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 639 .loc 1 328 3 view .LVU214 + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 640 .loc 1 328 6 is_stmt 0 view .LVU215 + 641 001a 012A cmp r2, #1 + 642 001c 08BF it eq + 643 001e 0129 cmpeq r1, #1 + 644 0020 48D1 bne .L38 + 645 0022 DBB2 uxtb r3, r3 + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 646 .loc 1 331 41 view .LVU216 + 647 0024 013B subs r3, r3, #1 + 648 .LVL33: + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 649 .loc 1 331 41 view .LVU217 + 650 0026 18BF it ne + 651 0028 0123 movne r3, #1 + 652 .LVL34: + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 653 .loc 1 331 7 view .LVU218 + ARM GAS /tmp/cc3heCqB.s page 61 + + + 654 002a 0128 cmp r0, #1 + 655 002c 44D1 bne .L39 + 656 002e 002B cmp r3, #0 + 657 0030 42D1 bne .L39 + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 658 .loc 1 337 3 is_stmt 1 view .LVU219 + 659 0032 0223 movs r3, #2 + 660 0034 84F83E30 strb r3, [r4, #62] + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 661 .loc 1 338 3 view .LVU220 + 662 0038 84F83F30 strb r3, [r4, #63] + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 663 .loc 1 339 3 view .LVU221 + 664 003c 84F84430 strb r3, [r4, #68] + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 665 .loc 1 340 3 view .LVU222 + 666 0040 84F84530 strb r3, [r4, #69] + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 667 .loc 1 345 3 view .LVU223 + 668 0044 0122 movs r2, #1 + 669 .LVL35: + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 670 .loc 1 345 3 is_stmt 0 view .LVU224 + 671 0046 0021 movs r1, #0 + 672 .LVL36: + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 673 .loc 1 345 3 view .LVU225 + 674 0048 2068 ldr r0, [r4] + 675 .LVL37: + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 676 .loc 1 345 3 view .LVU226 + 677 004a FFF7FEFF bl TIM_CCxChannelCmd + 678 .LVL38: + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 679 .loc 1 348 3 is_stmt 1 view .LVU227 + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 680 .loc 1 348 7 is_stmt 0 view .LVU228 + 681 004e 2368 ldr r3, [r4] + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 682 .loc 1 348 6 view .LVU229 + 683 0050 1B4A ldr r2, .L42 + 684 0052 B3F1804F cmp r3, #1073741824 + 685 0056 18BF it ne + 686 0058 9342 cmpne r3, r2 + 687 005a 1DD0 beq .L36 + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 688 .loc 1 348 7 discriminator 1 view .LVU230 + 689 005c A2F57C42 sub r2, r2, #64512 + 690 0060 9342 cmp r3, r2 + 691 0062 19D0 beq .L36 + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 692 .loc 1 348 7 discriminator 2 view .LVU231 + 693 0064 02F58062 add r2, r2, #1024 + 694 0068 9342 cmp r3, r2 + 695 006a 15D0 beq .L36 + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 696 .loc 1 348 7 discriminator 3 view .LVU232 + ARM GAS /tmp/cc3heCqB.s page 62 + + + 697 006c 02F58062 add r2, r2, #1024 + 698 0070 9342 cmp r3, r2 + 699 0072 11D0 beq .L36 + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 700 .loc 1 348 7 discriminator 4 view .LVU233 + 701 0074 02F57842 add r2, r2, #63488 + 702 0078 9342 cmp r3, r2 + 703 007a 0DD0 beq .L36 + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 704 .loc 1 348 7 discriminator 5 view .LVU234 + 705 007c 02F57052 add r2, r2, #15360 + 706 0080 9342 cmp r3, r2 + 707 0082 09D0 beq .L36 + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 708 .loc 1 348 7 discriminator 6 view .LVU235 + 709 0084 A2F59432 sub r2, r2, #75776 + 710 0088 9342 cmp r3, r2 + 711 008a 05D0 beq .L36 + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 712 .loc 1 358 5 is_stmt 1 view .LVU236 + 713 008c 1A68 ldr r2, [r3] + 714 008e 42F00102 orr r2, r2, #1 + 715 0092 1A60 str r2, [r3] + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 716 .loc 1 362 10 is_stmt 0 view .LVU237 + 717 0094 0020 movs r0, #0 + 718 0096 0EE0 b .L35 + 719 .L36: + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 720 .loc 1 350 5 is_stmt 1 view .LVU238 + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 721 .loc 1 350 29 is_stmt 0 view .LVU239 + 722 0098 9968 ldr r1, [r3, #8] + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 723 .loc 1 350 13 view .LVU240 + 724 009a 0A4A ldr r2, .L42+4 + 725 009c 0A40 ands r2, r2, r1 + 726 .LVL39: + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 727 .loc 1 351 5 is_stmt 1 view .LVU241 + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 728 .loc 1 351 8 is_stmt 0 view .LVU242 + 729 009e 062A cmp r2, #6 + 730 00a0 18BF it ne + 731 00a2 B2F5803F cmpne r2, #65536 + 732 00a6 09D0 beq .L40 + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 733 .loc 1 353 7 is_stmt 1 view .LVU243 + 734 00a8 1A68 ldr r2, [r3] + 735 .LVL40: + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 736 .loc 1 353 7 is_stmt 0 view .LVU244 + 737 00aa 42F00102 orr r2, r2, #1 + 738 00ae 1A60 str r2, [r3] + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 739 .loc 1 362 10 view .LVU245 + 740 00b0 0020 movs r0, #0 + ARM GAS /tmp/cc3heCqB.s page 63 + + + 741 00b2 00E0 b .L35 + 742 .LVL41: + 743 .L38: + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 744 .loc 1 333 12 view .LVU246 + 745 00b4 0120 movs r0, #1 + 746 .LVL42: + 747 .L35: + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 748 .loc 1 363 1 view .LVU247 + 749 00b6 10BD pop {r4, pc} + 750 .LVL43: + 751 .L39: + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 752 .loc 1 333 12 view .LVU248 + 753 00b8 0120 movs r0, #1 + 754 .LVL44: + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 755 .loc 1 333 12 view .LVU249 + 756 00ba FCE7 b .L35 + 757 .LVL45: + 758 .L40: + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 759 .loc 1 362 10 view .LVU250 + 760 00bc 0020 movs r0, #0 + 761 00be FAE7 b .L35 + 762 .L43: + 763 .align 2 + 764 .L42: + 765 00c0 00000140 .word 1073807360 + 766 00c4 07000100 .word 65543 + 767 .cfi_endproc + 768 .LFE145: + 770 .section .text.HAL_TIMEx_HallSensor_Stop,"ax",%progbits + 771 .align 1 + 772 .global HAL_TIMEx_HallSensor_Stop + 773 .syntax unified + 774 .thumb + 775 .thumb_func + 777 HAL_TIMEx_HallSensor_Stop: + 778 .LVL46: + 779 .LFB146: + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 780 .loc 1 371 1 is_stmt 1 view -0 + 781 .cfi_startproc + 782 @ args = 0, pretend = 0, frame = 0 + 783 @ frame_needed = 0, uses_anonymous_args = 0 + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 784 .loc 1 371 1 is_stmt 0 view .LVU252 + 785 0000 10B5 push {r4, lr} + 786 .LCFI9: + 787 .cfi_def_cfa_offset 8 + 788 .cfi_offset 4, -8 + 789 .cfi_offset 14, -4 + 790 0002 0446 mov r4, r0 + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 791 .loc 1 373 3 is_stmt 1 view .LVU253 + ARM GAS /tmp/cc3heCqB.s page 64 + + + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 792 .loc 1 378 3 view .LVU254 + 793 0004 0022 movs r2, #0 + 794 0006 1146 mov r1, r2 + 795 0008 0068 ldr r0, [r0] + 796 .LVL47: + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 797 .loc 1 378 3 is_stmt 0 view .LVU255 + 798 000a FFF7FEFF bl TIM_CCxChannelCmd + 799 .LVL48: + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 800 .loc 1 381 3 is_stmt 1 view .LVU256 + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 801 .loc 1 381 3 view .LVU257 + 802 000e 2368 ldr r3, [r4] + 803 0010 196A ldr r1, [r3, #32] + 804 0012 41F21112 movw r2, #4369 + 805 0016 1142 tst r1, r2 + 806 0018 08D1 bne .L45 + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 807 .loc 1 381 3 discriminator 1 view .LVU258 + 808 001a 196A ldr r1, [r3, #32] + 809 001c 40F24442 movw r2, #1092 + 810 0020 1142 tst r1, r2 + 811 0022 03D1 bne .L45 + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 812 .loc 1 381 3 discriminator 3 view .LVU259 + 813 0024 1A68 ldr r2, [r3] + 814 0026 22F00102 bic r2, r2, #1 + 815 002a 1A60 str r2, [r3] + 816 .L45: + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 817 .loc 1 381 3 discriminator 5 view .LVU260 + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 818 .loc 1 384 3 view .LVU261 + 819 002c 0123 movs r3, #1 + 820 002e 84F83E30 strb r3, [r4, #62] + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 821 .loc 1 385 3 view .LVU262 + 822 0032 84F83F30 strb r3, [r4, #63] + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 823 .loc 1 386 3 view .LVU263 + 824 0036 84F84430 strb r3, [r4, #68] + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 825 .loc 1 387 3 view .LVU264 + 826 003a 84F84530 strb r3, [r4, #69] + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 827 .loc 1 390 3 view .LVU265 + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 828 .loc 1 391 1 is_stmt 0 view .LVU266 + 829 003e 0020 movs r0, #0 + 830 0040 10BD pop {r4, pc} + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 831 .loc 1 391 1 view .LVU267 + 832 .cfi_endproc + 833 .LFE146: + 835 .section .text.HAL_TIMEx_HallSensor_Start_IT,"ax",%progbits + ARM GAS /tmp/cc3heCqB.s page 65 + + + 836 .align 1 + 837 .global HAL_TIMEx_HallSensor_Start_IT + 838 .syntax unified + 839 .thumb + 840 .thumb_func + 842 HAL_TIMEx_HallSensor_Start_IT: + 843 .LVL49: + 844 .LFB147: + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 845 .loc 1 399 1 is_stmt 1 view -0 + 846 .cfi_startproc + 847 @ args = 0, pretend = 0, frame = 0 + 848 @ frame_needed = 0, uses_anonymous_args = 0 + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 849 .loc 1 399 1 is_stmt 0 view .LVU269 + 850 0000 10B5 push {r4, lr} + 851 .LCFI10: + 852 .cfi_def_cfa_offset 8 + 853 .cfi_offset 4, -8 + 854 .cfi_offset 14, -4 + 855 0002 0446 mov r4, r0 + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 856 .loc 1 400 3 is_stmt 1 view .LVU270 + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 857 .loc 1 401 3 view .LVU271 + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 858 .loc 1 401 31 is_stmt 0 view .LVU272 + 859 0004 90F83E10 ldrb r1, [r0, #62] @ zero_extendqisi2 + 860 0008 C9B2 uxtb r1, r1 + 861 .LVL50: + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 862 .loc 1 402 3 is_stmt 1 view .LVU273 + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 863 .loc 1 402 31 is_stmt 0 view .LVU274 + 864 000a 90F83F20 ldrb r2, [r0, #63] @ zero_extendqisi2 + 865 000e D2B2 uxtb r2, r2 + 866 .LVL51: + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 867 .loc 1 403 3 is_stmt 1 view .LVU275 + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 868 .loc 1 403 31 is_stmt 0 view .LVU276 + 869 0010 90F84430 ldrb r3, [r0, #68] @ zero_extendqisi2 + 870 0014 D8B2 uxtb r0, r3 + 871 .LVL52: + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 872 .loc 1 404 3 is_stmt 1 view .LVU277 + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 873 .loc 1 404 31 is_stmt 0 view .LVU278 + 874 0016 94F84530 ldrb r3, [r4, #69] @ zero_extendqisi2 + 875 .LVL53: + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 876 .loc 1 407 3 is_stmt 1 view .LVU279 + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 877 .loc 1 410 3 view .LVU280 + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 878 .loc 1 410 6 is_stmt 0 view .LVU281 + 879 001a 012A cmp r2, #1 + ARM GAS /tmp/cc3heCqB.s page 66 + + + 880 001c 08BF it eq + 881 001e 0129 cmpeq r1, #1 + 882 0020 4DD1 bne .L51 + 883 0022 DBB2 uxtb r3, r3 + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 884 .loc 1 413 41 view .LVU282 + 885 0024 013B subs r3, r3, #1 + 886 .LVL54: + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 887 .loc 1 413 41 view .LVU283 + 888 0026 18BF it ne + 889 0028 0123 movne r3, #1 + 890 .LVL55: + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 891 .loc 1 413 7 view .LVU284 + 892 002a 0128 cmp r0, #1 + 893 002c 49D1 bne .L52 + 894 002e 002B cmp r3, #0 + 895 0030 47D1 bne .L52 + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 896 .loc 1 419 3 is_stmt 1 view .LVU285 + 897 0032 0223 movs r3, #2 + 898 0034 84F83E30 strb r3, [r4, #62] + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 899 .loc 1 420 3 view .LVU286 + 900 0038 84F83F30 strb r3, [r4, #63] + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 901 .loc 1 421 3 view .LVU287 + 902 003c 84F84430 strb r3, [r4, #68] + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 903 .loc 1 422 3 view .LVU288 + 904 0040 84F84530 strb r3, [r4, #69] + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 905 .loc 1 425 3 view .LVU289 + 906 0044 2268 ldr r2, [r4] + 907 .LVL56: + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 908 .loc 1 425 3 is_stmt 0 view .LVU290 + 909 0046 D368 ldr r3, [r2, #12] + 910 0048 43F00203 orr r3, r3, #2 + 911 004c D360 str r3, [r2, #12] + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 912 .loc 1 430 3 is_stmt 1 view .LVU291 + 913 004e 0122 movs r2, #1 + 914 0050 0021 movs r1, #0 + 915 .LVL57: + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 916 .loc 1 430 3 is_stmt 0 view .LVU292 + 917 0052 2068 ldr r0, [r4] + 918 .LVL58: + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 919 .loc 1 430 3 view .LVU293 + 920 0054 FFF7FEFF bl TIM_CCxChannelCmd + 921 .LVL59: + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 922 .loc 1 433 3 is_stmt 1 view .LVU294 + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + ARM GAS /tmp/cc3heCqB.s page 67 + + + 923 .loc 1 433 7 is_stmt 0 view .LVU295 + 924 0058 2368 ldr r3, [r4] + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 925 .loc 1 433 6 view .LVU296 + 926 005a 1C4A ldr r2, .L55 + 927 005c B3F1804F cmp r3, #1073741824 + 928 0060 18BF it ne + 929 0062 9342 cmpne r3, r2 + 930 0064 1DD0 beq .L49 + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 931 .loc 1 433 7 discriminator 1 view .LVU297 + 932 0066 A2F57C42 sub r2, r2, #64512 + 933 006a 9342 cmp r3, r2 + 934 006c 19D0 beq .L49 + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 935 .loc 1 433 7 discriminator 2 view .LVU298 + 936 006e 02F58062 add r2, r2, #1024 + 937 0072 9342 cmp r3, r2 + 938 0074 15D0 beq .L49 + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 939 .loc 1 433 7 discriminator 3 view .LVU299 + 940 0076 02F58062 add r2, r2, #1024 + 941 007a 9342 cmp r3, r2 + 942 007c 11D0 beq .L49 + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 943 .loc 1 433 7 discriminator 4 view .LVU300 + 944 007e 02F57842 add r2, r2, #63488 + 945 0082 9342 cmp r3, r2 + 946 0084 0DD0 beq .L49 + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 947 .loc 1 433 7 discriminator 5 view .LVU301 + 948 0086 02F57052 add r2, r2, #15360 + 949 008a 9342 cmp r3, r2 + 950 008c 09D0 beq .L49 + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 951 .loc 1 433 7 discriminator 6 view .LVU302 + 952 008e A2F59432 sub r2, r2, #75776 + 953 0092 9342 cmp r3, r2 + 954 0094 05D0 beq .L49 + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 955 .loc 1 443 5 is_stmt 1 view .LVU303 + 956 0096 1A68 ldr r2, [r3] + 957 0098 42F00102 orr r2, r2, #1 + 958 009c 1A60 str r2, [r3] + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 959 .loc 1 447 10 is_stmt 0 view .LVU304 + 960 009e 0020 movs r0, #0 + 961 00a0 0EE0 b .L48 + 962 .L49: + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 963 .loc 1 435 5 is_stmt 1 view .LVU305 + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 964 .loc 1 435 29 is_stmt 0 view .LVU306 + 965 00a2 9968 ldr r1, [r3, #8] + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 966 .loc 1 435 13 view .LVU307 + 967 00a4 0A4A ldr r2, .L55+4 + ARM GAS /tmp/cc3heCqB.s page 68 + + + 968 00a6 0A40 ands r2, r2, r1 + 969 .LVL60: + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 970 .loc 1 436 5 is_stmt 1 view .LVU308 + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 971 .loc 1 436 8 is_stmt 0 view .LVU309 + 972 00a8 062A cmp r2, #6 + 973 00aa 18BF it ne + 974 00ac B2F5803F cmpne r2, #65536 + 975 00b0 09D0 beq .L53 + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 976 .loc 1 438 7 is_stmt 1 view .LVU310 + 977 00b2 1A68 ldr r2, [r3] + 978 .LVL61: + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 979 .loc 1 438 7 is_stmt 0 view .LVU311 + 980 00b4 42F00102 orr r2, r2, #1 + 981 00b8 1A60 str r2, [r3] + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 982 .loc 1 447 10 view .LVU312 + 983 00ba 0020 movs r0, #0 + 984 00bc 00E0 b .L48 + 985 .LVL62: + 986 .L51: + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 987 .loc 1 415 12 view .LVU313 + 988 00be 0120 movs r0, #1 + 989 .LVL63: + 990 .L48: + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 991 .loc 1 448 1 view .LVU314 + 992 00c0 10BD pop {r4, pc} + 993 .LVL64: + 994 .L52: + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 995 .loc 1 415 12 view .LVU315 + 996 00c2 0120 movs r0, #1 + 997 .LVL65: + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 998 .loc 1 415 12 view .LVU316 + 999 00c4 FCE7 b .L48 + 1000 .LVL66: + 1001 .L53: + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1002 .loc 1 447 10 view .LVU317 + 1003 00c6 0020 movs r0, #0 + 1004 00c8 FAE7 b .L48 + 1005 .L56: + 1006 00ca 00BF .align 2 + 1007 .L55: + 1008 00cc 00000140 .word 1073807360 + 1009 00d0 07000100 .word 65543 + 1010 .cfi_endproc + 1011 .LFE147: + 1013 .section .text.HAL_TIMEx_HallSensor_Stop_IT,"ax",%progbits + 1014 .align 1 + 1015 .global HAL_TIMEx_HallSensor_Stop_IT + ARM GAS /tmp/cc3heCqB.s page 69 + + + 1016 .syntax unified + 1017 .thumb + 1018 .thumb_func + 1020 HAL_TIMEx_HallSensor_Stop_IT: + 1021 .LVL67: + 1022 .LFB148: + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 1023 .loc 1 456 1 is_stmt 1 view -0 + 1024 .cfi_startproc + 1025 @ args = 0, pretend = 0, frame = 0 + 1026 @ frame_needed = 0, uses_anonymous_args = 0 + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 1027 .loc 1 456 1 is_stmt 0 view .LVU319 + 1028 0000 10B5 push {r4, lr} + 1029 .LCFI11: + 1030 .cfi_def_cfa_offset 8 + 1031 .cfi_offset 4, -8 + 1032 .cfi_offset 14, -4 + 1033 0002 0446 mov r4, r0 + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1034 .loc 1 458 3 is_stmt 1 view .LVU320 + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1035 .loc 1 463 3 view .LVU321 + 1036 0004 0022 movs r2, #0 + 1037 0006 1146 mov r1, r2 + 1038 0008 0068 ldr r0, [r0] + 1039 .LVL68: + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1040 .loc 1 463 3 is_stmt 0 view .LVU322 + 1041 000a FFF7FEFF bl TIM_CCxChannelCmd + 1042 .LVL69: + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1043 .loc 1 466 3 is_stmt 1 view .LVU323 + 1044 000e 2268 ldr r2, [r4] + 1045 0010 D368 ldr r3, [r2, #12] + 1046 0012 23F00203 bic r3, r3, #2 + 1047 0016 D360 str r3, [r2, #12] + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1048 .loc 1 469 3 view .LVU324 + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1049 .loc 1 469 3 view .LVU325 + 1050 0018 2368 ldr r3, [r4] + 1051 001a 196A ldr r1, [r3, #32] + 1052 001c 41F21112 movw r2, #4369 + 1053 0020 1142 tst r1, r2 + 1054 0022 08D1 bne .L58 + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1055 .loc 1 469 3 discriminator 1 view .LVU326 + 1056 0024 196A ldr r1, [r3, #32] + 1057 0026 40F24442 movw r2, #1092 + 1058 002a 1142 tst r1, r2 + 1059 002c 03D1 bne .L58 + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1060 .loc 1 469 3 discriminator 3 view .LVU327 + 1061 002e 1A68 ldr r2, [r3] + 1062 0030 22F00102 bic r2, r2, #1 + 1063 0034 1A60 str r2, [r3] + ARM GAS /tmp/cc3heCqB.s page 70 + + + 1064 .L58: + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1065 .loc 1 469 3 discriminator 5 view .LVU328 + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 1066 .loc 1 472 3 view .LVU329 + 1067 0036 0123 movs r3, #1 + 1068 0038 84F83E30 strb r3, [r4, #62] + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 1069 .loc 1 473 3 view .LVU330 + 1070 003c 84F83F30 strb r3, [r4, #63] + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 1071 .loc 1 474 3 view .LVU331 + 1072 0040 84F84430 strb r3, [r4, #68] + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1073 .loc 1 475 3 view .LVU332 + 1074 0044 84F84530 strb r3, [r4, #69] + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1075 .loc 1 478 3 view .LVU333 + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1076 .loc 1 479 1 is_stmt 0 view .LVU334 + 1077 0048 0020 movs r0, #0 + 1078 004a 10BD pop {r4, pc} + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1079 .loc 1 479 1 view .LVU335 + 1080 .cfi_endproc + 1081 .LFE148: + 1083 .section .text.HAL_TIMEx_HallSensor_Start_DMA,"ax",%progbits + 1084 .align 1 + 1085 .global HAL_TIMEx_HallSensor_Start_DMA + 1086 .syntax unified + 1087 .thumb + 1088 .thumb_func + 1090 HAL_TIMEx_HallSensor_Start_DMA: + 1091 .LVL70: + 1092 .LFB149: + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 1093 .loc 1 489 1 is_stmt 1 view -0 + 1094 .cfi_startproc + 1095 @ args = 0, pretend = 0, frame = 0 + 1096 @ frame_needed = 0, uses_anonymous_args = 0 + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 1097 .loc 1 489 1 is_stmt 0 view .LVU337 + 1098 0000 70B5 push {r4, r5, r6, lr} + 1099 .LCFI12: + 1100 .cfi_def_cfa_offset 16 + 1101 .cfi_offset 4, -16 + 1102 .cfi_offset 5, -12 + 1103 .cfi_offset 6, -8 + 1104 .cfi_offset 14, -4 + 1105 0002 0446 mov r4, r0 + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 1106 .loc 1 490 3 is_stmt 1 view .LVU338 + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 1107 .loc 1 491 3 view .LVU339 + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 1108 .loc 1 491 31 is_stmt 0 view .LVU340 + 1109 0004 90F83EC0 ldrb ip, [r0, #62] @ zero_extendqisi2 + ARM GAS /tmp/cc3heCqB.s page 71 + + + 1110 0008 5FFA8CFC uxtb ip, ip + 1111 .LVL71: + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1112 .loc 1 492 3 is_stmt 1 view .LVU341 + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1113 .loc 1 492 31 is_stmt 0 view .LVU342 + 1114 000c 90F84400 ldrb r0, [r0, #68] @ zero_extendqisi2 + 1115 .LVL72: + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1116 .loc 1 492 31 view .LVU343 + 1117 0010 C0B2 uxtb r0, r0 + 1118 .LVL73: + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1119 .loc 1 495 3 is_stmt 1 view .LVU344 + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + 1120 .loc 1 498 3 view .LVU345 + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + 1121 .loc 1 498 6 is_stmt 0 view .LVU346 + 1122 0012 0228 cmp r0, #2 + 1123 0014 18BF it ne + 1124 0016 BCF1020F cmpne ip, #2 + 1125 001a 5ED0 beq .L64 + 1126 001c 0E46 mov r6, r1 + 1127 001e 1546 mov r5, r2 + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + 1128 .loc 1 503 8 is_stmt 1 view .LVU347 + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + 1129 .loc 1 503 11 is_stmt 0 view .LVU348 + 1130 0020 BCF1010F cmp ip, #1 + 1131 0024 08BF it eq + 1132 0026 0128 cmpeq r0, #1 + 1133 0028 59D1 bne .L65 + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1134 .loc 1 506 5 is_stmt 1 view .LVU349 + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1135 .loc 1 506 8 is_stmt 0 view .LVU350 + 1136 002a 002A cmp r2, #0 + 1137 002c 18BF it ne + 1138 002e 0029 cmpne r1, #0 + 1139 0030 01D1 bne .L69 + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1140 .loc 1 508 14 view .LVU351 + 1141 0032 0120 movs r0, #1 + 1142 .LVL74: + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1143 .loc 1 508 14 view .LVU352 + 1144 0034 54E0 b .L61 + 1145 .LVL75: + 1146 .L69: + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 1147 .loc 1 512 7 is_stmt 1 view .LVU353 + 1148 0036 0223 movs r3, #2 + 1149 0038 84F83E30 strb r3, [r4, #62] + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1150 .loc 1 513 7 view .LVU354 + 1151 003c 84F84430 strb r3, [r4, #68] + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + ARM GAS /tmp/cc3heCqB.s page 72 + + + 1152 .loc 1 524 3 view .LVU355 + 1153 0040 0122 movs r2, #1 + 1154 .LVL76: + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1155 .loc 1 524 3 is_stmt 0 view .LVU356 + 1156 0042 0021 movs r1, #0 + 1157 .LVL77: + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1158 .loc 1 524 3 view .LVU357 + 1159 0044 2068 ldr r0, [r4] + 1160 .LVL78: + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1161 .loc 1 524 3 view .LVU358 + 1162 0046 FFF7FEFF bl TIM_CCxChannelCmd + 1163 .LVL79: + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 1164 .loc 1 527 3 is_stmt 1 view .LVU359 + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 1165 .loc 1 527 13 is_stmt 0 view .LVU360 + 1166 004a 636A ldr r3, [r4, #36] + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 1167 .loc 1 527 48 view .LVU361 + 1168 004c 264A ldr r2, .L70 + 1169 004e DA63 str r2, [r3, #60] + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA error callback */ + 1170 .loc 1 528 3 is_stmt 1 view .LVU362 + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA error callback */ + 1171 .loc 1 528 13 is_stmt 0 view .LVU363 + 1172 0050 636A ldr r3, [r4, #36] + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA error callback */ + 1173 .loc 1 528 52 view .LVU364 + 1174 0052 264A ldr r2, .L70+4 + 1175 0054 1A64 str r2, [r3, #64] + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1176 .loc 1 530 3 is_stmt 1 view .LVU365 + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1177 .loc 1 530 13 is_stmt 0 view .LVU366 + 1178 0056 636A ldr r3, [r4, #36] + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1179 .loc 1 530 49 view .LVU367 + 1180 0058 254A ldr r2, .L70+8 + 1181 005a DA64 str r2, [r3, #76] + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1182 .loc 1 533 3 is_stmt 1 view .LVU368 + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1183 .loc 1 533 67 is_stmt 0 view .LVU369 + 1184 005c 2168 ldr r1, [r4] + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1185 .loc 1 533 7 view .LVU370 + 1186 005e 2B46 mov r3, r5 + 1187 0060 3246 mov r2, r6 + 1188 0062 3431 adds r1, r1, #52 + 1189 0064 606A ldr r0, [r4, #36] + 1190 0066 FFF7FEFF bl HAL_DMA_Start_IT + 1191 .LVL80: + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1192 .loc 1 533 6 discriminator 1 view .LVU371 + ARM GAS /tmp/cc3heCqB.s page 73 + + + 1193 006a 0028 cmp r0, #0 + 1194 006c 39D1 bne .L67 + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1195 .loc 1 539 3 is_stmt 1 view .LVU372 + 1196 006e 2268 ldr r2, [r4] + 1197 0070 D368 ldr r3, [r2, #12] + 1198 0072 43F40073 orr r3, r3, #512 + 1199 0076 D360 str r3, [r2, #12] + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1200 .loc 1 542 3 view .LVU373 + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1201 .loc 1 542 7 is_stmt 0 view .LVU374 + 1202 0078 2368 ldr r3, [r4] + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1203 .loc 1 542 6 view .LVU375 + 1204 007a 1E4A ldr r2, .L70+12 + 1205 007c B3F1804F cmp r3, #1073741824 + 1206 0080 18BF it ne + 1207 0082 9342 cmpne r3, r2 + 1208 0084 1CD0 beq .L62 + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1209 .loc 1 542 7 discriminator 1 view .LVU376 + 1210 0086 A2F57C42 sub r2, r2, #64512 + 1211 008a 9342 cmp r3, r2 + 1212 008c 18D0 beq .L62 + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1213 .loc 1 542 7 discriminator 2 view .LVU377 + 1214 008e 02F58062 add r2, r2, #1024 + 1215 0092 9342 cmp r3, r2 + 1216 0094 14D0 beq .L62 + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1217 .loc 1 542 7 discriminator 3 view .LVU378 + 1218 0096 02F58062 add r2, r2, #1024 + 1219 009a 9342 cmp r3, r2 + 1220 009c 10D0 beq .L62 + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1221 .loc 1 542 7 discriminator 4 view .LVU379 + 1222 009e 02F57842 add r2, r2, #63488 + 1223 00a2 9342 cmp r3, r2 + 1224 00a4 0CD0 beq .L62 + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1225 .loc 1 542 7 discriminator 5 view .LVU380 + 1226 00a6 02F57052 add r2, r2, #15360 + 1227 00aa 9342 cmp r3, r2 + 1228 00ac 08D0 beq .L62 + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1229 .loc 1 542 7 discriminator 6 view .LVU381 + 1230 00ae A2F59432 sub r2, r2, #75776 + 1231 00b2 9342 cmp r3, r2 + 1232 00b4 04D0 beq .L62 + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1233 .loc 1 552 5 is_stmt 1 view .LVU382 + 1234 00b6 1A68 ldr r2, [r3] + 1235 00b8 42F00102 orr r2, r2, #1 + 1236 00bc 1A60 str r2, [r3] + 1237 00be 0FE0 b .L61 + 1238 .L62: + ARM GAS /tmp/cc3heCqB.s page 74 + + + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1239 .loc 1 544 5 view .LVU383 + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1240 .loc 1 544 29 is_stmt 0 view .LVU384 + 1241 00c0 9968 ldr r1, [r3, #8] + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1242 .loc 1 544 13 view .LVU385 + 1243 00c2 0D4A ldr r2, .L70+16 + 1244 00c4 0A40 ands r2, r2, r1 + 1245 .LVL81: + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1246 .loc 1 545 5 is_stmt 1 view .LVU386 + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1247 .loc 1 545 8 is_stmt 0 view .LVU387 + 1248 00c6 062A cmp r2, #6 + 1249 00c8 18BF it ne + 1250 00ca B2F5803F cmpne r2, #65536 + 1251 00ce 07D0 beq .L61 + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1252 .loc 1 547 7 is_stmt 1 view .LVU388 + 1253 00d0 1A68 ldr r2, [r3] + 1254 .LVL82: + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1255 .loc 1 547 7 is_stmt 0 view .LVU389 + 1256 00d2 42F00102 orr r2, r2, #1 + 1257 00d6 1A60 str r2, [r3] + 1258 00d8 02E0 b .L61 + 1259 .LVL83: + 1260 .L64: + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1261 .loc 1 501 12 view .LVU390 + 1262 00da 0220 movs r0, #2 + 1263 .LVL84: + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1264 .loc 1 501 12 view .LVU391 + 1265 00dc 00E0 b .L61 + 1266 .LVL85: + 1267 .L65: + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1268 .loc 1 518 12 view .LVU392 + 1269 00de 0120 movs r0, #1 + 1270 .LVL86: + 1271 .L61: + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1272 .loc 1 557 1 view .LVU393 + 1273 00e0 70BD pop {r4, r5, r6, pc} + 1274 .LVL87: + 1275 .L67: + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1276 .loc 1 536 12 view .LVU394 + 1277 00e2 0120 movs r0, #1 + 1278 00e4 FCE7 b .L61 + 1279 .L71: + 1280 00e6 00BF .align 2 + 1281 .L70: + 1282 00e8 00000000 .word TIM_DMACaptureCplt + 1283 00ec 00000000 .word TIM_DMACaptureHalfCplt + ARM GAS /tmp/cc3heCqB.s page 75 + + + 1284 00f0 00000000 .word TIM_DMAError + 1285 00f4 00000140 .word 1073807360 + 1286 00f8 07000100 .word 65543 + 1287 .cfi_endproc + 1288 .LFE149: + 1290 .section .text.HAL_TIMEx_HallSensor_Stop_DMA,"ax",%progbits + 1291 .align 1 + 1292 .global HAL_TIMEx_HallSensor_Stop_DMA + 1293 .syntax unified + 1294 .thumb + 1295 .thumb_func + 1297 HAL_TIMEx_HallSensor_Stop_DMA: + 1298 .LVL88: + 1299 .LFB150: + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 1300 .loc 1 565 1 is_stmt 1 view -0 + 1301 .cfi_startproc + 1302 @ args = 0, pretend = 0, frame = 0 + 1303 @ frame_needed = 0, uses_anonymous_args = 0 + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 1304 .loc 1 565 1 is_stmt 0 view .LVU396 + 1305 0000 10B5 push {r4, lr} + 1306 .LCFI13: + 1307 .cfi_def_cfa_offset 8 + 1308 .cfi_offset 4, -8 + 1309 .cfi_offset 14, -4 + 1310 0002 0446 mov r4, r0 + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1311 .loc 1 567 3 is_stmt 1 view .LVU397 + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1312 .loc 1 572 3 view .LVU398 + 1313 0004 0022 movs r2, #0 + 1314 0006 1146 mov r1, r2 + 1315 0008 0068 ldr r0, [r0] + 1316 .LVL89: + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1317 .loc 1 572 3 is_stmt 0 view .LVU399 + 1318 000a FFF7FEFF bl TIM_CCxChannelCmd + 1319 .LVL90: + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1320 .loc 1 576 3 is_stmt 1 view .LVU400 + 1321 000e 2268 ldr r2, [r4] + 1322 0010 D368 ldr r3, [r2, #12] + 1323 0012 23F40073 bic r3, r3, #512 + 1324 0016 D360 str r3, [r2, #12] + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1325 .loc 1 578 3 view .LVU401 + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1326 .loc 1 578 9 is_stmt 0 view .LVU402 + 1327 0018 606A ldr r0, [r4, #36] + 1328 001a FFF7FEFF bl HAL_DMA_Abort_IT + 1329 .LVL91: + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1330 .loc 1 581 3 is_stmt 1 view .LVU403 + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1331 .loc 1 581 3 view .LVU404 + 1332 001e 2368 ldr r3, [r4] + ARM GAS /tmp/cc3heCqB.s page 76 + + + 1333 0020 196A ldr r1, [r3, #32] + 1334 0022 41F21112 movw r2, #4369 + 1335 0026 1142 tst r1, r2 + 1336 0028 08D1 bne .L73 + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1337 .loc 1 581 3 discriminator 1 view .LVU405 + 1338 002a 196A ldr r1, [r3, #32] + 1339 002c 40F24442 movw r2, #1092 + 1340 0030 1142 tst r1, r2 + 1341 0032 03D1 bne .L73 + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1342 .loc 1 581 3 discriminator 3 view .LVU406 + 1343 0034 1A68 ldr r2, [r3] + 1344 0036 22F00102 bic r2, r2, #1 + 1345 003a 1A60 str r2, [r3] + 1346 .L73: + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1347 .loc 1 581 3 discriminator 5 view .LVU407 + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 1348 .loc 1 584 3 view .LVU408 + 1349 003c 0123 movs r3, #1 + 1350 003e 84F83E30 strb r3, [r4, #62] + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1351 .loc 1 585 3 view .LVU409 + 1352 0042 84F84430 strb r3, [r4, #68] + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1353 .loc 1 588 3 view .LVU410 + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1354 .loc 1 589 1 is_stmt 0 view .LVU411 + 1355 0046 0020 movs r0, #0 + 1356 0048 10BD pop {r4, pc} + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1357 .loc 1 589 1 view .LVU412 + 1358 .cfi_endproc + 1359 .LFE150: + 1361 .section .text.HAL_TIMEx_OCN_Start,"ax",%progbits + 1362 .align 1 + 1363 .global HAL_TIMEx_OCN_Start + 1364 .syntax unified + 1365 .thumb + 1366 .thumb_func + 1368 HAL_TIMEx_OCN_Start: + 1369 .LVL92: + 1370 .LFB151: + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 1371 .loc 1 627 1 is_stmt 1 view -0 + 1372 .cfi_startproc + 1373 @ args = 0, pretend = 0, frame = 0 + 1374 @ frame_needed = 0, uses_anonymous_args = 0 + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 1375 .loc 1 627 1 is_stmt 0 view .LVU414 + 1376 0000 10B5 push {r4, lr} + 1377 .LCFI14: + 1378 .cfi_def_cfa_offset 8 + 1379 .cfi_offset 4, -8 + 1380 .cfi_offset 14, -4 + 1381 0002 0446 mov r4, r0 + ARM GAS /tmp/cc3heCqB.s page 77 + + + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1382 .loc 1 628 3 is_stmt 1 view .LVU415 + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1383 .loc 1 631 3 view .LVU416 + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1384 .loc 1 634 3 view .LVU417 + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1385 .loc 1 634 46 is_stmt 0 view .LVU418 + 1386 0004 0846 mov r0, r1 + 1387 .LVL93: + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1388 .loc 1 634 46 view .LVU419 + 1389 0006 0029 cmp r1, #0 + 1390 0008 3BD1 bne .L76 + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1391 .loc 1 634 7 discriminator 1 view .LVU420 + 1392 000a 94F84430 ldrb r3, [r4, #68] @ zero_extendqisi2 + 1393 000e DBB2 uxtb r3, r3 + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1394 .loc 1 634 46 discriminator 1 view .LVU421 + 1395 0010 013B subs r3, r3, #1 + 1396 0012 18BF it ne + 1397 0014 0123 movne r3, #1 + 1398 .L77: + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1399 .loc 1 634 6 discriminator 12 view .LVU422 + 1400 0016 002B cmp r3, #0 + 1401 0018 6AD1 bne .L87 + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1402 .loc 1 640 3 is_stmt 1 view .LVU423 + 1403 001a 0028 cmp r0, #0 + 1404 001c 4AD1 bne .L81 + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1405 .loc 1 640 3 is_stmt 0 discriminator 1 view .LVU424 + 1406 001e 0223 movs r3, #2 + 1407 0020 84F84430 strb r3, [r4, #68] + 1408 .L82: + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1409 .loc 1 643 3 is_stmt 1 view .LVU425 + 1410 0024 0422 movs r2, #4 + 1411 0026 0146 mov r1, r0 + 1412 .LVL94: + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1413 .loc 1 643 3 is_stmt 0 view .LVU426 + 1414 0028 2068 ldr r0, [r4] + 1415 .LVL95: + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1416 .loc 1 643 3 view .LVU427 + 1417 002a FFF7FEFF bl TIM_CCxNChannelCmd + 1418 .LVL96: + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1419 .loc 1 646 3 is_stmt 1 view .LVU428 + 1420 002e 2268 ldr r2, [r4] + 1421 0030 536C ldr r3, [r2, #68] + 1422 0032 43F40043 orr r3, r3, #32768 + 1423 0036 5364 str r3, [r2, #68] + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + ARM GAS /tmp/cc3heCqB.s page 78 + + + 1424 .loc 1 649 3 view .LVU429 + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1425 .loc 1 649 7 is_stmt 0 view .LVU430 + 1426 0038 2368 ldr r3, [r4] + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1427 .loc 1 649 6 view .LVU431 + 1428 003a 2F4A ldr r2, .L94 + 1429 003c B3F1804F cmp r3, #1073741824 + 1430 0040 18BF it ne + 1431 0042 9342 cmpne r3, r2 + 1432 0044 46D0 beq .L85 + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1433 .loc 1 649 7 discriminator 1 view .LVU432 + 1434 0046 A2F57C42 sub r2, r2, #64512 + 1435 004a 9342 cmp r3, r2 + 1436 004c 42D0 beq .L85 + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1437 .loc 1 649 7 discriminator 2 view .LVU433 + 1438 004e 02F58062 add r2, r2, #1024 + 1439 0052 9342 cmp r3, r2 + 1440 0054 3ED0 beq .L85 + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1441 .loc 1 649 7 discriminator 3 view .LVU434 + 1442 0056 02F58062 add r2, r2, #1024 + 1443 005a 9342 cmp r3, r2 + 1444 005c 3AD0 beq .L85 + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1445 .loc 1 649 7 discriminator 4 view .LVU435 + 1446 005e 02F57842 add r2, r2, #63488 + 1447 0062 9342 cmp r3, r2 + 1448 0064 36D0 beq .L85 + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1449 .loc 1 649 7 discriminator 5 view .LVU436 + 1450 0066 02F57052 add r2, r2, #15360 + 1451 006a 9342 cmp r3, r2 + 1452 006c 32D0 beq .L85 + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1453 .loc 1 649 7 discriminator 6 view .LVU437 + 1454 006e A2F59432 sub r2, r2, #75776 + 1455 0072 9342 cmp r3, r2 + 1456 0074 2ED0 beq .L85 + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1457 .loc 1 659 5 is_stmt 1 view .LVU438 + 1458 0076 1A68 ldr r2, [r3] + 1459 0078 42F00102 orr r2, r2, #1 + 1460 007c 1A60 str r2, [r3] + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1461 .loc 1 663 10 is_stmt 0 view .LVU439 + 1462 007e 0020 movs r0, #0 + 1463 0080 37E0 b .L80 + 1464 .LVL97: + 1465 .L76: + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1466 .loc 1 634 46 discriminator 2 view .LVU440 + 1467 0082 0429 cmp r1, #4 + 1468 0084 08D0 beq .L90 + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + ARM GAS /tmp/cc3heCqB.s page 79 + + + 1469 .loc 1 634 46 discriminator 5 view .LVU441 + 1470 0086 0829 cmp r1, #8 + 1471 0088 0DD0 beq .L91 + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1472 .loc 1 634 7 discriminator 8 view .LVU442 + 1473 008a 94F84730 ldrb r3, [r4, #71] @ zero_extendqisi2 + 1474 008e DBB2 uxtb r3, r3 + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1475 .loc 1 634 46 discriminator 8 view .LVU443 + 1476 0090 013B subs r3, r3, #1 + 1477 0092 18BF it ne + 1478 0094 0123 movne r3, #1 + 1479 0096 BEE7 b .L77 + 1480 .L90: + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1481 .loc 1 634 7 discriminator 4 view .LVU444 + 1482 0098 94F84530 ldrb r3, [r4, #69] @ zero_extendqisi2 + 1483 009c DBB2 uxtb r3, r3 + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1484 .loc 1 634 46 discriminator 4 view .LVU445 + 1485 009e 013B subs r3, r3, #1 + 1486 00a0 18BF it ne + 1487 00a2 0123 movne r3, #1 + 1488 00a4 B7E7 b .L77 + 1489 .L91: + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1490 .loc 1 634 7 discriminator 7 view .LVU446 + 1491 00a6 94F84630 ldrb r3, [r4, #70] @ zero_extendqisi2 + 1492 00aa DBB2 uxtb r3, r3 + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1493 .loc 1 634 46 discriminator 7 view .LVU447 + 1494 00ac 013B subs r3, r3, #1 + 1495 00ae 18BF it ne + 1496 00b0 0123 movne r3, #1 + 1497 00b2 B0E7 b .L77 + 1498 .L81: + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1499 .loc 1 640 3 discriminator 2 view .LVU448 + 1500 00b4 0428 cmp r0, #4 + 1501 00b6 05D0 beq .L92 + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1502 .loc 1 640 3 discriminator 4 view .LVU449 + 1503 00b8 0828 cmp r0, #8 + 1504 00ba 07D0 beq .L93 + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1505 .loc 1 640 3 discriminator 7 view .LVU450 + 1506 00bc 0223 movs r3, #2 + 1507 00be 84F84730 strb r3, [r4, #71] + 1508 00c2 AFE7 b .L82 + 1509 .L92: + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1510 .loc 1 640 3 discriminator 3 view .LVU451 + 1511 00c4 0223 movs r3, #2 + 1512 00c6 84F84530 strb r3, [r4, #69] + 1513 00ca ABE7 b .L82 + 1514 .L93: + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + ARM GAS /tmp/cc3heCqB.s page 80 + + + 1515 .loc 1 640 3 discriminator 6 view .LVU452 + 1516 00cc 0223 movs r3, #2 + 1517 00ce 84F84630 strb r3, [r4, #70] + 1518 00d2 A7E7 b .L82 + 1519 .LVL98: + 1520 .L85: + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1521 .loc 1 651 5 is_stmt 1 view .LVU453 + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1522 .loc 1 651 29 is_stmt 0 view .LVU454 + 1523 00d4 9968 ldr r1, [r3, #8] + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1524 .loc 1 651 13 view .LVU455 + 1525 00d6 094A ldr r2, .L94+4 + 1526 00d8 0A40 ands r2, r2, r1 + 1527 .LVL99: + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1528 .loc 1 652 5 is_stmt 1 view .LVU456 + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1529 .loc 1 652 8 is_stmt 0 view .LVU457 + 1530 00da 062A cmp r2, #6 + 1531 00dc 18BF it ne + 1532 00de B2F5803F cmpne r2, #65536 + 1533 00e2 07D0 beq .L88 + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1534 .loc 1 654 7 is_stmt 1 view .LVU458 + 1535 00e4 1A68 ldr r2, [r3] + 1536 .LVL100: + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1537 .loc 1 654 7 is_stmt 0 view .LVU459 + 1538 00e6 42F00102 orr r2, r2, #1 + 1539 00ea 1A60 str r2, [r3] + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1540 .loc 1 663 10 view .LVU460 + 1541 00ec 0020 movs r0, #0 + 1542 00ee 00E0 b .L80 + 1543 .LVL101: + 1544 .L87: + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1545 .loc 1 636 12 view .LVU461 + 1546 00f0 0120 movs r0, #1 + 1547 .LVL102: + 1548 .L80: + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1549 .loc 1 664 1 view .LVU462 + 1550 00f2 10BD pop {r4, pc} + 1551 .LVL103: + 1552 .L88: + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1553 .loc 1 663 10 view .LVU463 + 1554 00f4 0020 movs r0, #0 + 1555 00f6 FCE7 b .L80 + 1556 .L95: + 1557 .align 2 + 1558 .L94: + 1559 00f8 00000140 .word 1073807360 + 1560 00fc 07000100 .word 65543 + ARM GAS /tmp/cc3heCqB.s page 81 + + + 1561 .cfi_endproc + 1562 .LFE151: + 1564 .section .text.HAL_TIMEx_OCN_Stop,"ax",%progbits + 1565 .align 1 + 1566 .global HAL_TIMEx_OCN_Stop + 1567 .syntax unified + 1568 .thumb + 1569 .thumb_func + 1571 HAL_TIMEx_OCN_Stop: + 1572 .LVL104: + 1573 .LFB152: + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 1574 .loc 1 678 1 is_stmt 1 view -0 + 1575 .cfi_startproc + 1576 @ args = 0, pretend = 0, frame = 0 + 1577 @ frame_needed = 0, uses_anonymous_args = 0 + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 1578 .loc 1 678 1 is_stmt 0 view .LVU465 + 1579 0000 38B5 push {r3, r4, r5, lr} + 1580 .LCFI15: + 1581 .cfi_def_cfa_offset 16 + 1582 .cfi_offset 3, -16 + 1583 .cfi_offset 4, -12 + 1584 .cfi_offset 5, -8 + 1585 .cfi_offset 14, -4 + 1586 0002 0446 mov r4, r0 + 1587 0004 0D46 mov r5, r1 + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1588 .loc 1 680 3 is_stmt 1 view .LVU466 + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1589 .loc 1 683 3 view .LVU467 + 1590 0006 0022 movs r2, #0 + 1591 0008 0068 ldr r0, [r0] + 1592 .LVL105: + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1593 .loc 1 683 3 is_stmt 0 view .LVU468 + 1594 000a FFF7FEFF bl TIM_CCxNChannelCmd + 1595 .LVL106: + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1596 .loc 1 686 3 is_stmt 1 view .LVU469 + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1597 .loc 1 686 3 view .LVU470 + 1598 000e 2368 ldr r3, [r4] + 1599 0010 196A ldr r1, [r3, #32] + 1600 0012 41F21112 movw r2, #4369 + 1601 0016 1142 tst r1, r2 + 1602 0018 08D1 bne .L97 + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1603 .loc 1 686 3 discriminator 1 view .LVU471 + 1604 001a 196A ldr r1, [r3, #32] + 1605 001c 40F24442 movw r2, #1092 + 1606 0020 1142 tst r1, r2 + 1607 0022 03D1 bne .L97 + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1608 .loc 1 686 3 discriminator 3 view .LVU472 + 1609 0024 5A6C ldr r2, [r3, #68] + 1610 0026 22F40042 bic r2, r2, #32768 + ARM GAS /tmp/cc3heCqB.s page 82 + + + 1611 002a 5A64 str r2, [r3, #68] + 1612 .L97: + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1613 .loc 1 686 3 discriminator 5 view .LVU473 + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1614 .loc 1 689 3 view .LVU474 + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1615 .loc 1 689 3 view .LVU475 + 1616 002c 2368 ldr r3, [r4] + 1617 002e 196A ldr r1, [r3, #32] + 1618 0030 41F21112 movw r2, #4369 + 1619 0034 1142 tst r1, r2 + 1620 0036 08D1 bne .L98 + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1621 .loc 1 689 3 discriminator 1 view .LVU476 + 1622 0038 196A ldr r1, [r3, #32] + 1623 003a 40F24442 movw r2, #1092 + 1624 003e 1142 tst r1, r2 + 1625 0040 03D1 bne .L98 + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1626 .loc 1 689 3 discriminator 3 view .LVU477 + 1627 0042 1A68 ldr r2, [r3] + 1628 0044 22F00102 bic r2, r2, #1 + 1629 0048 1A60 str r2, [r3] + 1630 .L98: + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1631 .loc 1 689 3 discriminator 5 view .LVU478 + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1632 .loc 1 692 3 view .LVU479 + 1633 004a 25B9 cbnz r5, .L99 + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1634 .loc 1 692 3 is_stmt 0 discriminator 1 view .LVU480 + 1635 004c 0123 movs r3, #1 + 1636 004e 84F84430 strb r3, [r4, #68] + 1637 .L100: + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1638 .loc 1 695 3 is_stmt 1 view .LVU481 + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1639 .loc 1 696 1 is_stmt 0 view .LVU482 + 1640 0052 0020 movs r0, #0 + 1641 0054 38BD pop {r3, r4, r5, pc} + 1642 .LVL107: + 1643 .L99: + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1644 .loc 1 692 3 discriminator 2 view .LVU483 + 1645 0056 042D cmp r5, #4 + 1646 0058 05D0 beq .L104 + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1647 .loc 1 692 3 discriminator 4 view .LVU484 + 1648 005a 082D cmp r5, #8 + 1649 005c 07D0 beq .L105 + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1650 .loc 1 692 3 discriminator 7 view .LVU485 + 1651 005e 0123 movs r3, #1 + 1652 0060 84F84730 strb r3, [r4, #71] + 1653 0064 F5E7 b .L100 + 1654 .L104: + ARM GAS /tmp/cc3heCqB.s page 83 + + + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1655 .loc 1 692 3 discriminator 3 view .LVU486 + 1656 0066 0123 movs r3, #1 + 1657 0068 84F84530 strb r3, [r4, #69] + 1658 006c F1E7 b .L100 + 1659 .L105: + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1660 .loc 1 692 3 discriminator 6 view .LVU487 + 1661 006e 0123 movs r3, #1 + 1662 0070 84F84630 strb r3, [r4, #70] + 1663 0074 EDE7 b .L100 + 1664 .cfi_endproc + 1665 .LFE152: + 1667 .section .text.HAL_TIMEx_OCN_Start_IT,"ax",%progbits + 1668 .align 1 + 1669 .global HAL_TIMEx_OCN_Start_IT + 1670 .syntax unified + 1671 .thumb + 1672 .thumb_func + 1674 HAL_TIMEx_OCN_Start_IT: + 1675 .LVL108: + 1676 .LFB153: + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1677 .loc 1 710 1 is_stmt 1 view -0 + 1678 .cfi_startproc + 1679 @ args = 0, pretend = 0, frame = 0 + 1680 @ frame_needed = 0, uses_anonymous_args = 0 + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1681 .loc 1 710 1 is_stmt 0 view .LVU489 + 1682 0000 10B5 push {r4, lr} + 1683 .LCFI16: + 1684 .cfi_def_cfa_offset 8 + 1685 .cfi_offset 4, -8 + 1686 .cfi_offset 14, -4 + 1687 0002 0446 mov r4, r0 + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 1688 .loc 1 711 3 is_stmt 1 view .LVU490 + 1689 .LVL109: + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1690 .loc 1 712 3 view .LVU491 + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1691 .loc 1 715 3 view .LVU492 + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1692 .loc 1 718 3 view .LVU493 + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1693 .loc 1 718 46 is_stmt 0 view .LVU494 + 1694 0004 0846 mov r0, r1 + 1695 .LVL110: + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1696 .loc 1 718 46 view .LVU495 + 1697 0006 0029 cmp r1, #0 + 1698 0008 46D1 bne .L107 + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1699 .loc 1 718 7 discriminator 1 view .LVU496 + 1700 000a 94F84430 ldrb r3, [r4, #68] @ zero_extendqisi2 + 1701 000e DBB2 uxtb r3, r3 + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + ARM GAS /tmp/cc3heCqB.s page 84 + + + 1702 .loc 1 718 46 discriminator 1 view .LVU497 + 1703 0010 013B subs r3, r3, #1 + 1704 0012 18BF it ne + 1705 0014 0123 movne r3, #1 + 1706 .L108: + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1707 .loc 1 718 6 discriminator 12 view .LVU498 + 1708 0016 002B cmp r3, #0 + 1709 0018 40F08680 bne .L121 + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1710 .loc 1 724 3 is_stmt 1 view .LVU499 + 1711 001c 0028 cmp r0, #0 + 1712 001e 54D1 bne .L112 + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1713 .loc 1 724 3 is_stmt 0 discriminator 1 view .LVU500 + 1714 0020 0223 movs r3, #2 + 1715 0022 84F84430 strb r3, [r4, #68] + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1716 .loc 1 726 3 is_stmt 1 view .LVU501 + 1717 .L113: + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 1718 .loc 1 731 7 view .LVU502 + 1719 0026 2268 ldr r2, [r4] + 1720 0028 D368 ldr r3, [r2, #12] + 1721 002a 43F00203 orr r3, r3, #2 + 1722 002e D360 str r3, [r2, #12] + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1723 .loc 1 732 7 view .LVU503 + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1724 .loc 1 755 3 view .LVU504 + 1725 .L118: + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1726 .loc 1 758 5 view .LVU505 + 1727 0030 2268 ldr r2, [r4] + 1728 0032 D368 ldr r3, [r2, #12] + 1729 0034 43F08003 orr r3, r3, #128 + 1730 0038 D360 str r3, [r2, #12] + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1731 .loc 1 761 5 view .LVU506 + 1732 003a 0422 movs r2, #4 + 1733 003c 0146 mov r1, r0 + 1734 .LVL111: + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1735 .loc 1 761 5 is_stmt 0 view .LVU507 + 1736 003e 2068 ldr r0, [r4] + 1737 .LVL112: + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1738 .loc 1 761 5 view .LVU508 + 1739 0040 FFF7FEFF bl TIM_CCxNChannelCmd + 1740 .LVL113: + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1741 .loc 1 764 5 is_stmt 1 view .LVU509 + 1742 0044 2268 ldr r2, [r4] + 1743 0046 536C ldr r3, [r2, #68] + 1744 0048 43F40043 orr r3, r3, #32768 + 1745 004c 5364 str r3, [r2, #68] + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + ARM GAS /tmp/cc3heCqB.s page 85 + + + 1746 .loc 1 767 5 view .LVU510 + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1747 .loc 1 767 9 is_stmt 0 view .LVU511 + 1748 004e 2368 ldr r3, [r4] + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1749 .loc 1 767 8 view .LVU512 + 1750 0050 374A ldr r2, .L129 + 1751 0052 B3F1804F cmp r3, #1073741824 + 1752 0056 18BF it ne + 1753 0058 9342 cmpne r3, r2 + 1754 005a 57D0 beq .L119 + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1755 .loc 1 767 9 discriminator 1 view .LVU513 + 1756 005c A2F57C42 sub r2, r2, #64512 + 1757 0060 9342 cmp r3, r2 + 1758 0062 53D0 beq .L119 + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1759 .loc 1 767 9 discriminator 2 view .LVU514 + 1760 0064 02F58062 add r2, r2, #1024 + 1761 0068 9342 cmp r3, r2 + 1762 006a 4FD0 beq .L119 + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1763 .loc 1 767 9 discriminator 3 view .LVU515 + 1764 006c 02F58062 add r2, r2, #1024 + 1765 0070 9342 cmp r3, r2 + 1766 0072 4BD0 beq .L119 + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1767 .loc 1 767 9 discriminator 4 view .LVU516 + 1768 0074 02F57842 add r2, r2, #63488 + 1769 0078 9342 cmp r3, r2 + 1770 007a 47D0 beq .L119 + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1771 .loc 1 767 9 discriminator 5 view .LVU517 + 1772 007c 02F57052 add r2, r2, #15360 + 1773 0080 9342 cmp r3, r2 + 1774 0082 43D0 beq .L119 + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1775 .loc 1 767 9 discriminator 6 view .LVU518 + 1776 0084 A2F59432 sub r2, r2, #75776 + 1777 0088 9342 cmp r3, r2 + 1778 008a 3FD0 beq .L119 + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1779 .loc 1 777 7 is_stmt 1 view .LVU519 + 1780 008c 1A68 ldr r2, [r3] + 1781 008e 42F00102 orr r2, r2, #1 + 1782 0092 1A60 str r2, [r3] + 1783 0094 0020 movs r0, #0 + 1784 0096 48E0 b .L111 + 1785 .LVL114: + 1786 .L107: + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1787 .loc 1 718 46 is_stmt 0 discriminator 2 view .LVU520 + 1788 0098 0429 cmp r1, #4 + 1789 009a 08D0 beq .L125 + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1790 .loc 1 718 46 discriminator 5 view .LVU521 + 1791 009c 0829 cmp r1, #8 + ARM GAS /tmp/cc3heCqB.s page 86 + + + 1792 009e 0DD0 beq .L126 + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1793 .loc 1 718 7 discriminator 8 view .LVU522 + 1794 00a0 94F84730 ldrb r3, [r4, #71] @ zero_extendqisi2 + 1795 00a4 DBB2 uxtb r3, r3 + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1796 .loc 1 718 46 discriminator 8 view .LVU523 + 1797 00a6 013B subs r3, r3, #1 + 1798 00a8 18BF it ne + 1799 00aa 0123 movne r3, #1 + 1800 00ac B3E7 b .L108 + 1801 .L125: + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1802 .loc 1 718 7 discriminator 4 view .LVU524 + 1803 00ae 94F84530 ldrb r3, [r4, #69] @ zero_extendqisi2 + 1804 00b2 DBB2 uxtb r3, r3 + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1805 .loc 1 718 46 discriminator 4 view .LVU525 + 1806 00b4 013B subs r3, r3, #1 + 1807 00b6 18BF it ne + 1808 00b8 0123 movne r3, #1 + 1809 00ba ACE7 b .L108 + 1810 .L126: + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1811 .loc 1 718 7 discriminator 7 view .LVU526 + 1812 00bc 94F84630 ldrb r3, [r4, #70] @ zero_extendqisi2 + 1813 00c0 DBB2 uxtb r3, r3 + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1814 .loc 1 718 46 discriminator 7 view .LVU527 + 1815 00c2 013B subs r3, r3, #1 + 1816 00c4 18BF it ne + 1817 00c6 0123 movne r3, #1 + 1818 00c8 A5E7 b .L108 + 1819 .L112: + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1820 .loc 1 724 3 discriminator 2 view .LVU528 + 1821 00ca 0428 cmp r0, #4 + 1822 00cc 0CD0 beq .L127 + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1823 .loc 1 724 3 discriminator 4 view .LVU529 + 1824 00ce 0828 cmp r0, #8 + 1825 00d0 13D0 beq .L128 + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1826 .loc 1 724 3 discriminator 7 view .LVU530 + 1827 00d2 0223 movs r3, #2 + 1828 00d4 84F84730 strb r3, [r4, #71] + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1829 .loc 1 726 3 is_stmt 1 view .LVU531 + 1830 00d8 0428 cmp r0, #4 + 1831 00da 08D0 beq .L115 + 1832 00dc 0828 cmp r0, #8 + 1833 00de 0FD0 beq .L117 + 1834 00e0 0028 cmp r0, #0 + 1835 00e2 A0D0 beq .L113 + 1836 00e4 0120 movs r0, #1 + 1837 .LVL115: + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + ARM GAS /tmp/cc3heCqB.s page 87 + + + 1838 .loc 1 726 3 is_stmt 0 view .LVU532 + 1839 00e6 20E0 b .L111 + 1840 .LVL116: + 1841 .L127: + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1842 .loc 1 724 3 discriminator 3 view .LVU533 + 1843 00e8 0223 movs r3, #2 + 1844 00ea 84F84530 strb r3, [r4, #69] + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1845 .loc 1 726 3 is_stmt 1 view .LVU534 + 1846 .L115: + 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 1847 .loc 1 738 7 view .LVU535 + 1848 00ee 2268 ldr r2, [r4] + 1849 00f0 D368 ldr r3, [r2, #12] + 1850 00f2 43F00403 orr r3, r3, #4 + 1851 00f6 D360 str r3, [r2, #12] + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1852 .loc 1 739 7 view .LVU536 + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1853 .loc 1 755 3 view .LVU537 + 1854 00f8 9AE7 b .L118 + 1855 .L128: + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1856 .loc 1 724 3 is_stmt 0 discriminator 6 view .LVU538 + 1857 00fa 0223 movs r3, #2 + 1858 00fc 84F84630 strb r3, [r4, #70] + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1859 .loc 1 726 3 is_stmt 1 view .LVU539 + 1860 .L117: + 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 1861 .loc 1 745 7 view .LVU540 + 1862 0100 2268 ldr r2, [r4] + 1863 0102 D368 ldr r3, [r2, #12] + 1864 0104 43F00803 orr r3, r3, #8 + 1865 0108 D360 str r3, [r2, #12] + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1866 .loc 1 746 7 view .LVU541 + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1867 .loc 1 755 3 view .LVU542 + 1868 010a 91E7 b .L118 + 1869 .LVL117: + 1870 .L119: + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1871 .loc 1 769 7 view .LVU543 + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1872 .loc 1 769 31 is_stmt 0 view .LVU544 + 1873 010c 9968 ldr r1, [r3, #8] + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1874 .loc 1 769 15 view .LVU545 + 1875 010e 094A ldr r2, .L129+4 + 1876 0110 0A40 ands r2, r2, r1 + 1877 .LVL118: + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1878 .loc 1 770 7 is_stmt 1 view .LVU546 + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1879 .loc 1 770 10 is_stmt 0 view .LVU547 + ARM GAS /tmp/cc3heCqB.s page 88 + + + 1880 0112 062A cmp r2, #6 + 1881 0114 18BF it ne + 1882 0116 B2F5803F cmpne r2, #65536 + 1883 011a 07D0 beq .L123 + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1884 .loc 1 772 9 is_stmt 1 view .LVU548 + 1885 011c 1A68 ldr r2, [r3] + 1886 .LVL119: + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1887 .loc 1 772 9 is_stmt 0 view .LVU549 + 1888 011e 42F00102 orr r2, r2, #1 + 1889 0122 1A60 str r2, [r3] + 1890 0124 0020 movs r0, #0 + 1891 0126 00E0 b .L111 + 1892 .LVL120: + 1893 .L121: + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1894 .loc 1 720 12 view .LVU550 + 1895 0128 0120 movs r0, #1 + 1896 .LVL121: + 1897 .L111: + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1898 .loc 1 783 1 view .LVU551 + 1899 012a 10BD pop {r4, pc} + 1900 .LVL122: + 1901 .L123: + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1902 .loc 1 783 1 view .LVU552 + 1903 012c 0020 movs r0, #0 + 1904 012e FCE7 b .L111 + 1905 .L130: + 1906 .align 2 + 1907 .L129: + 1908 0130 00000140 .word 1073807360 + 1909 0134 07000100 .word 65543 + 1910 .cfi_endproc + 1911 .LFE153: + 1913 .section .text.HAL_TIMEx_OCN_Stop_IT,"ax",%progbits + 1914 .align 1 + 1915 .global HAL_TIMEx_OCN_Stop_IT + 1916 .syntax unified + 1917 .thumb + 1918 .thumb_func + 1920 HAL_TIMEx_OCN_Stop_IT: + 1921 .LVL123: + 1922 .LFB154: + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1923 .loc 1 797 1 is_stmt 1 view -0 + 1924 .cfi_startproc + 1925 @ args = 0, pretend = 0, frame = 0 + 1926 @ frame_needed = 0, uses_anonymous_args = 0 + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1927 .loc 1 797 1 is_stmt 0 view .LVU554 + 1928 0000 38B5 push {r3, r4, r5, lr} + 1929 .LCFI17: + 1930 .cfi_def_cfa_offset 16 + 1931 .cfi_offset 3, -16 + ARM GAS /tmp/cc3heCqB.s page 89 + + + 1932 .cfi_offset 4, -12 + 1933 .cfi_offset 5, -8 + 1934 .cfi_offset 14, -4 + 1935 0002 0446 mov r4, r0 + 1936 0004 0D46 mov r5, r1 + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpccer; + 1937 .loc 1 798 3 is_stmt 1 view .LVU555 + 1938 .LVL124: + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1939 .loc 1 799 3 view .LVU556 + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1940 .loc 1 802 3 view .LVU557 + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1941 .loc 1 804 3 view .LVU558 + 1942 0006 0429 cmp r1, #4 + 1943 0008 3BD0 beq .L132 + 1944 000a 0829 cmp r1, #8 + 1945 000c 3FD0 beq .L133 + 1946 000e 0029 cmp r1, #0 + 1947 0010 56D1 bne .L142 + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 1948 .loc 1 809 7 view .LVU559 + 1949 0012 0268 ldr r2, [r0] + 1950 0014 D368 ldr r3, [r2, #12] + 1951 0016 23F00203 bic r3, r3, #2 + 1952 001a D360 str r3, [r2, #12] + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1953 .loc 1 810 7 view .LVU560 + 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1954 .loc 1 832 3 view .LVU561 + 1955 .L135: + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1956 .loc 1 835 5 view .LVU562 + 1957 001c 0022 movs r2, #0 + 1958 001e 2946 mov r1, r5 + 1959 .LVL125: + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1960 .loc 1 835 5 is_stmt 0 view .LVU563 + 1961 0020 2068 ldr r0, [r4] + 1962 .LVL126: + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1963 .loc 1 835 5 view .LVU564 + 1964 0022 FFF7FEFF bl TIM_CCxNChannelCmd + 1965 .LVL127: + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + 1966 .loc 1 838 5 is_stmt 1 view .LVU565 + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + 1967 .loc 1 838 19 is_stmt 0 view .LVU566 + 1968 0026 2368 ldr r3, [r4] + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + 1969 .loc 1 838 13 view .LVU567 + 1970 0028 196A ldr r1, [r3, #32] + 1971 .LVL128: + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1972 .loc 1 839 5 is_stmt 1 view .LVU568 + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 1973 .loc 1 839 8 is_stmt 0 view .LVU569 + ARM GAS /tmp/cc3heCqB.s page 90 + + + 1974 002a 40F24442 movw r2, #1092 + 1975 002e 1142 tst r1, r2 + 1976 0030 03D1 bne .L136 + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 1977 .loc 1 841 7 is_stmt 1 view .LVU570 + 1978 0032 DA68 ldr r2, [r3, #12] + 1979 0034 22F08002 bic r2, r2, #128 + 1980 0038 DA60 str r2, [r3, #12] + 1981 .L136: + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1982 .loc 1 845 5 view .LVU571 + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1983 .loc 1 845 5 view .LVU572 + 1984 003a 2368 ldr r3, [r4] + 1985 003c 196A ldr r1, [r3, #32] + 1986 .LVL129: + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1987 .loc 1 845 5 is_stmt 0 view .LVU573 + 1988 003e 41F21112 movw r2, #4369 + 1989 0042 1142 tst r1, r2 + 1990 0044 08D1 bne .L137 + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1991 .loc 1 845 5 is_stmt 1 discriminator 1 view .LVU574 + 1992 0046 196A ldr r1, [r3, #32] + 1993 0048 40F24442 movw r2, #1092 + 1994 004c 1142 tst r1, r2 + 1995 004e 03D1 bne .L137 + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 1996 .loc 1 845 5 discriminator 3 view .LVU575 + 1997 0050 5A6C ldr r2, [r3, #68] + 1998 0052 22F40042 bic r2, r2, #32768 + 1999 0056 5A64 str r2, [r3, #68] + 2000 .L137: + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2001 .loc 1 845 5 discriminator 5 view .LVU576 + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2002 .loc 1 848 5 view .LVU577 + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2003 .loc 1 848 5 view .LVU578 + 2004 0058 2368 ldr r3, [r4] + 2005 005a 196A ldr r1, [r3, #32] + 2006 005c 41F21112 movw r2, #4369 + 2007 0060 1142 tst r1, r2 + 2008 0062 08D1 bne .L138 + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2009 .loc 1 848 5 discriminator 1 view .LVU579 + 2010 0064 196A ldr r1, [r3, #32] + 2011 0066 40F24442 movw r2, #1092 + 2012 006a 1142 tst r1, r2 + 2013 006c 03D1 bne .L138 + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2014 .loc 1 848 5 discriminator 3 view .LVU580 + 2015 006e 1A68 ldr r2, [r3] + 2016 0070 22F00102 bic r2, r2, #1 + 2017 0074 1A60 str r2, [r3] + 2018 .L138: + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + ARM GAS /tmp/cc3heCqB.s page 91 + + + 2019 .loc 1 848 5 discriminator 5 view .LVU581 + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2020 .loc 1 851 5 view .LVU582 + 2021 0076 85B9 cbnz r5, .L139 + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2022 .loc 1 851 5 is_stmt 0 discriminator 1 view .LVU583 + 2023 0078 0123 movs r3, #1 + 2024 007a 84F84430 strb r3, [r4, #68] + 2025 007e 0020 movs r0, #0 + 2026 .LVL130: + 2027 .L134: + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2028 .loc 1 855 3 is_stmt 1 view .LVU584 + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2029 .loc 1 856 1 is_stmt 0 view .LVU585 + 2030 0080 38BD pop {r3, r4, r5, pc} + 2031 .LVL131: + 2032 .L132: + 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 2033 .loc 1 816 7 is_stmt 1 view .LVU586 + 2034 0082 0268 ldr r2, [r0] + 2035 0084 D368 ldr r3, [r2, #12] + 2036 0086 23F00403 bic r3, r3, #4 + 2037 008a D360 str r3, [r2, #12] + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2038 .loc 1 817 7 view .LVU587 + 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2039 .loc 1 832 3 view .LVU588 + 2040 008c C6E7 b .L135 + 2041 .L133: + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 2042 .loc 1 823 7 view .LVU589 + 2043 008e 0268 ldr r2, [r0] + 2044 0090 D368 ldr r3, [r2, #12] + 2045 0092 23F00803 bic r3, r3, #8 + 2046 0096 D360 str r3, [r2, #12] + 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2047 .loc 1 824 7 view .LVU590 + 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2048 .loc 1 832 3 view .LVU591 + 2049 0098 C0E7 b .L135 + 2050 .LVL132: + 2051 .L139: + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2052 .loc 1 851 5 is_stmt 0 discriminator 2 view .LVU592 + 2053 009a 042D cmp r5, #4 + 2054 009c 06D0 beq .L144 + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2055 .loc 1 851 5 discriminator 4 view .LVU593 + 2056 009e 082D cmp r5, #8 + 2057 00a0 09D0 beq .L145 + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2058 .loc 1 851 5 discriminator 7 view .LVU594 + 2059 00a2 0123 movs r3, #1 + 2060 00a4 84F84730 strb r3, [r4, #71] + 2061 00a8 0020 movs r0, #0 + 2062 00aa E9E7 b .L134 + ARM GAS /tmp/cc3heCqB.s page 92 + + + 2063 .L144: + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2064 .loc 1 851 5 discriminator 3 view .LVU595 + 2065 00ac 0123 movs r3, #1 + 2066 00ae 84F84530 strb r3, [r4, #69] + 2067 00b2 0020 movs r0, #0 + 2068 00b4 E4E7 b .L134 + 2069 .L145: + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2070 .loc 1 851 5 discriminator 6 view .LVU596 + 2071 00b6 0123 movs r3, #1 + 2072 00b8 84F84630 strb r3, [r4, #70] + 2073 00bc 0020 movs r0, #0 + 2074 00be DFE7 b .L134 + 2075 .LVL133: + 2076 .L142: + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2077 .loc 1 804 3 view .LVU597 + 2078 00c0 0120 movs r0, #1 + 2079 .LVL134: + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2080 .loc 1 804 3 view .LVU598 + 2081 00c2 DDE7 b .L134 + 2082 .cfi_endproc + 2083 .LFE154: + 2085 .section .text.HAL_TIMEx_OCN_Start_DMA,"ax",%progbits + 2086 .align 1 + 2087 .global HAL_TIMEx_OCN_Start_DMA + 2088 .syntax unified + 2089 .thumb + 2090 .thumb_func + 2092 HAL_TIMEx_OCN_Start_DMA: + 2093 .LVL135: + 2094 .LFB155: + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 2095 .loc 1 873 1 is_stmt 1 view -0 + 2096 .cfi_startproc + 2097 @ args = 0, pretend = 0, frame = 0 + 2098 @ frame_needed = 0, uses_anonymous_args = 0 + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 2099 .loc 1 873 1 is_stmt 0 view .LVU600 + 2100 0000 38B5 push {r3, r4, r5, lr} + 2101 .LCFI18: + 2102 .cfi_def_cfa_offset 16 + 2103 .cfi_offset 3, -16 + 2104 .cfi_offset 4, -12 + 2105 .cfi_offset 5, -8 + 2106 .cfi_offset 14, -4 + 2107 0002 0446 mov r4, r0 + 2108 0004 9446 mov ip, r2 + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 2109 .loc 1 874 3 is_stmt 1 view .LVU601 + 2110 .LVL136: + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2111 .loc 1 875 3 view .LVU602 + 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2112 .loc 1 878 3 view .LVU603 + ARM GAS /tmp/cc3heCqB.s page 93 + + + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2113 .loc 1 881 3 view .LVU604 + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2114 .loc 1 881 46 is_stmt 0 view .LVU605 + 2115 0006 0D46 mov r5, r1 + 2116 0008 0029 cmp r1, #0 + 2117 000a 6ED1 bne .L147 + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2118 .loc 1 881 7 discriminator 1 view .LVU606 + 2119 000c 90F84400 ldrb r0, [r0, #68] @ zero_extendqisi2 + 2120 .LVL137: + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2121 .loc 1 881 7 discriminator 1 view .LVU607 + 2122 0010 C0B2 uxtb r0, r0 + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2123 .loc 1 881 46 discriminator 1 view .LVU608 + 2124 0012 0228 cmp r0, #2 + 2125 0014 14BF ite ne + 2126 0016 0020 movne r0, #0 + 2127 0018 0120 moveq r0, #1 + 2128 .L148: + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2129 .loc 1 881 6 discriminator 12 view .LVU609 + 2130 001a 0028 cmp r0, #0 + 2131 001c 40F0EE80 bne .L165 + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2132 .loc 1 885 8 is_stmt 1 view .LVU610 + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2133 .loc 1 885 51 is_stmt 0 view .LVU611 + 2134 0020 002D cmp r5, #0 + 2135 0022 7ED1 bne .L152 + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2136 .loc 1 885 12 discriminator 1 view .LVU612 + 2137 0024 94F84420 ldrb r2, [r4, #68] @ zero_extendqisi2 + 2138 .LVL138: + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2139 .loc 1 885 12 discriminator 1 view .LVU613 + 2140 0028 D2B2 uxtb r2, r2 + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2141 .loc 1 885 51 discriminator 1 view .LVU614 + 2142 002a 012A cmp r2, #1 + 2143 002c 14BF ite ne + 2144 002e 0022 movne r2, #0 + 2145 0030 0122 moveq r2, #1 + 2146 .L153: + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2147 .loc 1 885 11 discriminator 12 view .LVU615 + 2148 0032 002A cmp r2, #0 + 2149 0034 00F0E480 beq .L166 + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2150 .loc 1 887 5 is_stmt 1 view .LVU616 + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2151 .loc 1 887 8 is_stmt 0 view .LVU617 + 2152 0038 002B cmp r3, #0 + 2153 003a 18BF it ne + 2154 003c BCF1000F cmpne ip, #0 + 2155 0040 00F0E080 beq .L167 + ARM GAS /tmp/cc3heCqB.s page 94 + + + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2156 .loc 1 893 7 is_stmt 1 view .LVU618 + 2157 0044 002D cmp r5, #0 + 2158 0046 40F08880 bne .L156 + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2159 .loc 1 893 7 is_stmt 0 discriminator 1 view .LVU619 + 2160 004a 0222 movs r2, #2 + 2161 004c 84F84420 strb r2, [r4, #68] + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2162 .loc 1 901 3 is_stmt 1 view .LVU620 + 2163 .L157: + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2164 .loc 1 906 7 view .LVU621 + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2165 .loc 1 906 17 is_stmt 0 view .LVU622 + 2166 0050 626A ldr r2, [r4, #36] + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2167 .loc 1 906 52 view .LVU623 + 2168 0052 7149 ldr r1, .L180 + 2169 .LVL139: + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2170 .loc 1 906 52 view .LVU624 + 2171 0054 D163 str r1, [r2, #60] + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2172 .loc 1 907 7 is_stmt 1 view .LVU625 + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2173 .loc 1 907 17 is_stmt 0 view .LVU626 + 2174 0056 626A ldr r2, [r4, #36] + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2175 .loc 1 907 56 view .LVU627 + 2176 0058 7049 ldr r1, .L180+4 + 2177 005a 1164 str r1, [r2, #64] + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2178 .loc 1 910 7 is_stmt 1 view .LVU628 + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2179 .loc 1 910 17 is_stmt 0 view .LVU629 + 2180 005c 626A ldr r2, [r4, #36] + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2181 .loc 1 910 53 view .LVU630 + 2182 005e 7049 ldr r1, .L180+8 + 2183 0060 D164 str r1, [r2, #76] + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 2184 .loc 1 913 7 is_stmt 1 view .LVU631 + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 2185 .loc 1 913 88 is_stmt 0 view .LVU632 + 2186 0062 2268 ldr r2, [r4] + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 2187 .loc 1 913 11 view .LVU633 + 2188 0064 3432 adds r2, r2, #52 + 2189 0066 6146 mov r1, ip + 2190 0068 606A ldr r0, [r4, #36] + 2191 006a FFF7FEFF bl HAL_DMA_Start_IT + 2192 .LVL140: + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 2193 .loc 1 913 10 discriminator 1 view .LVU634 + 2194 006e 0028 cmp r0, #0 + 2195 0070 40F0CA80 bne .L169 + ARM GAS /tmp/cc3heCqB.s page 95 + + + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 2196 .loc 1 920 7 is_stmt 1 view .LVU635 + 2197 0074 2268 ldr r2, [r4] + 2198 0076 D368 ldr r3, [r2, #12] + 2199 0078 43F40073 orr r3, r3, #512 + 2200 007c D360 str r3, [r2, #12] + 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2201 .loc 1 921 7 view .LVU636 + 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2202 .loc 1 971 3 view .LVU637 + 2203 .L162: + 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2204 .loc 1 974 5 view .LVU638 + 2205 007e 0422 movs r2, #4 + 2206 0080 2946 mov r1, r5 + 2207 0082 2068 ldr r0, [r4] + 2208 0084 FFF7FEFF bl TIM_CCxNChannelCmd + 2209 .LVL141: + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2210 .loc 1 977 5 view .LVU639 + 2211 0088 2268 ldr r2, [r4] + 2212 008a 536C ldr r3, [r2, #68] + 2213 008c 43F40043 orr r3, r3, #32768 + 2214 0090 5364 str r3, [r2, #68] + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2215 .loc 1 980 5 view .LVU640 + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2216 .loc 1 980 9 is_stmt 0 view .LVU641 + 2217 0092 2368 ldr r3, [r4] + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2218 .loc 1 980 8 view .LVU642 + 2219 0094 634A ldr r2, .L180+12 + 2220 0096 B3F1804F cmp r3, #1073741824 + 2221 009a 18BF it ne + 2222 009c 9342 cmpne r3, r2 + 2223 009e 00F09F80 beq .L163 + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2224 .loc 1 980 9 discriminator 1 view .LVU643 + 2225 00a2 A2F57C42 sub r2, r2, #64512 + 2226 00a6 9342 cmp r3, r2 + 2227 00a8 00F09A80 beq .L163 + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2228 .loc 1 980 9 discriminator 2 view .LVU644 + 2229 00ac 02F58062 add r2, r2, #1024 + 2230 00b0 9342 cmp r3, r2 + 2231 00b2 00F09580 beq .L163 + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2232 .loc 1 980 9 discriminator 3 view .LVU645 + 2233 00b6 02F58062 add r2, r2, #1024 + 2234 00ba 9342 cmp r3, r2 + 2235 00bc 00F09080 beq .L163 + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2236 .loc 1 980 9 discriminator 4 view .LVU646 + 2237 00c0 02F57842 add r2, r2, #63488 + 2238 00c4 9342 cmp r3, r2 + 2239 00c6 00F08B80 beq .L163 + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + ARM GAS /tmp/cc3heCqB.s page 96 + + + 2240 .loc 1 980 9 discriminator 5 view .LVU647 + 2241 00ca 02F57052 add r2, r2, #15360 + 2242 00ce 9342 cmp r3, r2 + 2243 00d0 00F08680 beq .L163 + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2244 .loc 1 980 9 discriminator 6 view .LVU648 + 2245 00d4 A2F59432 sub r2, r2, #75776 + 2246 00d8 9342 cmp r3, r2 + 2247 00da 00F08180 beq .L163 + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2248 .loc 1 990 7 is_stmt 1 view .LVU649 + 2249 00de 1A68 ldr r2, [r3] + 2250 00e0 42F00102 orr r2, r2, #1 + 2251 00e4 1A60 str r2, [r3] + 2252 00e6 0020 movs r0, #0 + 2253 00e8 8BE0 b .L151 + 2254 .LVL142: + 2255 .L147: + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2256 .loc 1 881 46 is_stmt 0 discriminator 2 view .LVU650 + 2257 00ea 0429 cmp r1, #4 + 2258 00ec 09D0 beq .L174 + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2259 .loc 1 881 46 discriminator 5 view .LVU651 + 2260 00ee 0829 cmp r1, #8 + 2261 00f0 0FD0 beq .L175 + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2262 .loc 1 881 7 discriminator 8 view .LVU652 + 2263 00f2 90F84700 ldrb r0, [r0, #71] @ zero_extendqisi2 + 2264 .LVL143: + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2265 .loc 1 881 7 discriminator 8 view .LVU653 + 2266 00f6 C0B2 uxtb r0, r0 + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2267 .loc 1 881 46 discriminator 8 view .LVU654 + 2268 00f8 0228 cmp r0, #2 + 2269 00fa 14BF ite ne + 2270 00fc 0020 movne r0, #0 + 2271 00fe 0120 moveq r0, #1 + 2272 0100 8BE7 b .L148 + 2273 .LVL144: + 2274 .L174: + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2275 .loc 1 881 7 discriminator 4 view .LVU655 + 2276 0102 90F84500 ldrb r0, [r0, #69] @ zero_extendqisi2 + 2277 .LVL145: + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2278 .loc 1 881 7 discriminator 4 view .LVU656 + 2279 0106 C0B2 uxtb r0, r0 + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2280 .loc 1 881 46 discriminator 4 view .LVU657 + 2281 0108 0228 cmp r0, #2 + 2282 010a 14BF ite ne + 2283 010c 0020 movne r0, #0 + 2284 010e 0120 moveq r0, #1 + 2285 0110 83E7 b .L148 + 2286 .LVL146: + ARM GAS /tmp/cc3heCqB.s page 97 + + + 2287 .L175: + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2288 .loc 1 881 7 discriminator 7 view .LVU658 + 2289 0112 90F84600 ldrb r0, [r0, #70] @ zero_extendqisi2 + 2290 .LVL147: + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2291 .loc 1 881 7 discriminator 7 view .LVU659 + 2292 0116 C0B2 uxtb r0, r0 + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2293 .loc 1 881 46 discriminator 7 view .LVU660 + 2294 0118 0228 cmp r0, #2 + 2295 011a 14BF ite ne + 2296 011c 0020 movne r0, #0 + 2297 011e 0120 moveq r0, #1 + 2298 0120 7BE7 b .L148 + 2299 .L152: + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2300 .loc 1 885 51 discriminator 2 view .LVU661 + 2301 0122 042D cmp r5, #4 + 2302 0124 09D0 beq .L176 + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2303 .loc 1 885 51 discriminator 5 view .LVU662 + 2304 0126 082D cmp r5, #8 + 2305 0128 0FD0 beq .L177 + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2306 .loc 1 885 12 discriminator 8 view .LVU663 + 2307 012a 94F84720 ldrb r2, [r4, #71] @ zero_extendqisi2 + 2308 .LVL148: + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2309 .loc 1 885 12 discriminator 8 view .LVU664 + 2310 012e D2B2 uxtb r2, r2 + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2311 .loc 1 885 51 discriminator 8 view .LVU665 + 2312 0130 012A cmp r2, #1 + 2313 0132 14BF ite ne + 2314 0134 0022 movne r2, #0 + 2315 0136 0122 moveq r2, #1 + 2316 0138 7BE7 b .L153 + 2317 .LVL149: + 2318 .L176: + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2319 .loc 1 885 12 discriminator 4 view .LVU666 + 2320 013a 94F84520 ldrb r2, [r4, #69] @ zero_extendqisi2 + 2321 .LVL150: + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2322 .loc 1 885 12 discriminator 4 view .LVU667 + 2323 013e D2B2 uxtb r2, r2 + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2324 .loc 1 885 51 discriminator 4 view .LVU668 + 2325 0140 012A cmp r2, #1 + 2326 0142 14BF ite ne + 2327 0144 0022 movne r2, #0 + 2328 0146 0122 moveq r2, #1 + 2329 0148 73E7 b .L153 + 2330 .LVL151: + 2331 .L177: + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + ARM GAS /tmp/cc3heCqB.s page 98 + + + 2332 .loc 1 885 12 discriminator 7 view .LVU669 + 2333 014a 94F84620 ldrb r2, [r4, #70] @ zero_extendqisi2 + 2334 .LVL152: + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2335 .loc 1 885 12 discriminator 7 view .LVU670 + 2336 014e D2B2 uxtb r2, r2 + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2337 .loc 1 885 51 discriminator 7 view .LVU671 + 2338 0150 012A cmp r2, #1 + 2339 0152 14BF ite ne + 2340 0154 0022 movne r2, #0 + 2341 0156 0122 moveq r2, #1 + 2342 0158 6BE7 b .L153 + 2343 .L156: + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2344 .loc 1 893 7 discriminator 2 view .LVU672 + 2345 015a 042D cmp r5, #4 + 2346 015c 0DD0 beq .L178 + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2347 .loc 1 893 7 discriminator 4 view .LVU673 + 2348 015e 082D cmp r5, #8 + 2349 0160 25D0 beq .L179 + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2350 .loc 1 893 7 discriminator 7 view .LVU674 + 2351 0162 0222 movs r2, #2 + 2352 0164 84F84720 strb r2, [r4, #71] + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2353 .loc 1 901 3 is_stmt 1 view .LVU675 + 2354 0168 042D cmp r5, #4 + 2355 016a 09D0 beq .L159 + 2356 016c 082D cmp r5, #8 + 2357 016e 21D0 beq .L161 + 2358 0170 002D cmp r5, #0 + 2359 0172 3FF46DAF beq .L157 + 2360 0176 0120 movs r0, #1 + 2361 0178 43E0 b .L151 + 2362 .L178: + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2363 .loc 1 893 7 is_stmt 0 discriminator 3 view .LVU676 + 2364 017a 0222 movs r2, #2 + 2365 017c 84F84520 strb r2, [r4, #69] + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2366 .loc 1 901 3 is_stmt 1 view .LVU677 + 2367 .L159: + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2368 .loc 1 927 7 view .LVU678 + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2369 .loc 1 927 17 is_stmt 0 view .LVU679 + 2370 0180 A26A ldr r2, [r4, #40] + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2371 .loc 1 927 52 view .LVU680 + 2372 0182 2549 ldr r1, .L180 + 2373 .LVL153: + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2374 .loc 1 927 52 view .LVU681 + 2375 0184 D163 str r1, [r2, #60] + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + ARM GAS /tmp/cc3heCqB.s page 99 + + + 2376 .loc 1 928 7 is_stmt 1 view .LVU682 + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2377 .loc 1 928 17 is_stmt 0 view .LVU683 + 2378 0186 A26A ldr r2, [r4, #40] + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2379 .loc 1 928 56 view .LVU684 + 2380 0188 2449 ldr r1, .L180+4 + 2381 018a 1164 str r1, [r2, #64] + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2382 .loc 1 931 7 is_stmt 1 view .LVU685 + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2383 .loc 1 931 17 is_stmt 0 view .LVU686 + 2384 018c A26A ldr r2, [r4, #40] + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2385 .loc 1 931 53 view .LVU687 + 2386 018e 2449 ldr r1, .L180+8 + 2387 0190 D164 str r1, [r2, #76] + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 2388 .loc 1 934 7 is_stmt 1 view .LVU688 + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 2389 .loc 1 934 88 is_stmt 0 view .LVU689 + 2390 0192 2268 ldr r2, [r4] + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 2391 .loc 1 934 11 view .LVU690 + 2392 0194 3832 adds r2, r2, #56 + 2393 0196 6146 mov r1, ip + 2394 0198 A06A ldr r0, [r4, #40] + 2395 019a FFF7FEFF bl HAL_DMA_Start_IT + 2396 .LVL154: + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 2397 .loc 1 934 10 discriminator 1 view .LVU691 + 2398 019e 0028 cmp r0, #0 + 2399 01a0 34D1 bne .L170 + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 2400 .loc 1 941 7 is_stmt 1 view .LVU692 + 2401 01a2 2268 ldr r2, [r4] + 2402 01a4 D368 ldr r3, [r2, #12] + 2403 01a6 43F48063 orr r3, r3, #1024 + 2404 01aa D360 str r3, [r2, #12] + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2405 .loc 1 942 7 view .LVU693 + 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2406 .loc 1 971 3 view .LVU694 + 2407 01ac 67E7 b .L162 + 2408 .LVL155: + 2409 .L179: + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2410 .loc 1 893 7 is_stmt 0 discriminator 6 view .LVU695 + 2411 01ae 0222 movs r2, #2 + 2412 01b0 84F84620 strb r2, [r4, #70] + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2413 .loc 1 901 3 is_stmt 1 view .LVU696 + 2414 .L161: + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2415 .loc 1 948 7 view .LVU697 + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2416 .loc 1 948 17 is_stmt 0 view .LVU698 + ARM GAS /tmp/cc3heCqB.s page 100 + + + 2417 01b4 E26A ldr r2, [r4, #44] + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2418 .loc 1 948 52 view .LVU699 + 2419 01b6 1849 ldr r1, .L180 + 2420 .LVL156: + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2421 .loc 1 948 52 view .LVU700 + 2422 01b8 D163 str r1, [r2, #60] + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2423 .loc 1 949 7 is_stmt 1 view .LVU701 + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2424 .loc 1 949 17 is_stmt 0 view .LVU702 + 2425 01ba E26A ldr r2, [r4, #44] + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2426 .loc 1 949 56 view .LVU703 + 2427 01bc 1749 ldr r1, .L180+4 + 2428 01be 1164 str r1, [r2, #64] + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2429 .loc 1 952 7 is_stmt 1 view .LVU704 + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2430 .loc 1 952 17 is_stmt 0 view .LVU705 + 2431 01c0 E26A ldr r2, [r4, #44] + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2432 .loc 1 952 53 view .LVU706 + 2433 01c2 1749 ldr r1, .L180+8 + 2434 01c4 D164 str r1, [r2, #76] + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 2435 .loc 1 955 7 is_stmt 1 view .LVU707 + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 2436 .loc 1 955 88 is_stmt 0 view .LVU708 + 2437 01c6 2268 ldr r2, [r4] + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 2438 .loc 1 955 11 view .LVU709 + 2439 01c8 3C32 adds r2, r2, #60 + 2440 01ca 6146 mov r1, ip + 2441 01cc E06A ldr r0, [r4, #44] + 2442 01ce FFF7FEFF bl HAL_DMA_Start_IT + 2443 .LVL157: + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 2444 .loc 1 955 10 discriminator 1 view .LVU710 + 2445 01d2 E8B9 cbnz r0, .L171 + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 2446 .loc 1 962 7 is_stmt 1 view .LVU711 + 2447 01d4 2268 ldr r2, [r4] + 2448 01d6 D368 ldr r3, [r2, #12] + 2449 01d8 43F40063 orr r3, r3, #2048 + 2450 01dc D360 str r3, [r2, #12] + 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2451 .loc 1 963 7 view .LVU712 + 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2452 .loc 1 971 3 view .LVU713 + 2453 01de 4EE7 b .L162 + 2454 .L163: + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 2455 .loc 1 982 7 view .LVU714 + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 2456 .loc 1 982 31 is_stmt 0 view .LVU715 + ARM GAS /tmp/cc3heCqB.s page 101 + + + 2457 01e0 9968 ldr r1, [r3, #8] + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 2458 .loc 1 982 15 view .LVU716 + 2459 01e2 114A ldr r2, .L180+16 + 2460 01e4 0A40 ands r2, r2, r1 + 2461 .LVL158: + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2462 .loc 1 983 7 is_stmt 1 view .LVU717 + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2463 .loc 1 983 10 is_stmt 0 view .LVU718 + 2464 01e6 062A cmp r2, #6 + 2465 01e8 18BF it ne + 2466 01ea B2F5803F cmpne r2, #65536 + 2467 01ee 11D0 beq .L172 + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2468 .loc 1 985 9 is_stmt 1 view .LVU719 + 2469 01f0 1A68 ldr r2, [r3] + 2470 .LVL159: + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2471 .loc 1 985 9 is_stmt 0 view .LVU720 + 2472 01f2 42F00102 orr r2, r2, #1 + 2473 01f6 1A60 str r2, [r3] + 2474 01f8 0020 movs r0, #0 + 2475 01fa 02E0 b .L151 + 2476 .LVL160: + 2477 .L165: + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2478 .loc 1 883 12 view .LVU721 + 2479 01fc 0220 movs r0, #2 + 2480 01fe 00E0 b .L151 + 2481 .LVL161: + 2482 .L166: + 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2483 .loc 1 898 12 view .LVU722 + 2484 0200 0120 movs r0, #1 + 2485 .LVL162: + 2486 .L151: + 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2487 .loc 1 996 1 view .LVU723 + 2488 0202 38BD pop {r3, r4, r5, pc} + 2489 .LVL163: + 2490 .L167: + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2491 .loc 1 889 14 view .LVU724 + 2492 0204 0120 movs r0, #1 + 2493 0206 FCE7 b .L151 + 2494 .LVL164: + 2495 .L169: + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2496 .loc 1 917 16 view .LVU725 + 2497 0208 0120 movs r0, #1 + 2498 020a FAE7 b .L151 + 2499 .L170: + 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2500 .loc 1 938 16 view .LVU726 + 2501 020c 0120 movs r0, #1 + 2502 020e F8E7 b .L151 + ARM GAS /tmp/cc3heCqB.s page 102 + + + 2503 .L171: + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2504 .loc 1 959 16 view .LVU727 + 2505 0210 0120 movs r0, #1 + 2506 0212 F6E7 b .L151 + 2507 .LVL165: + 2508 .L172: + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2509 .loc 1 959 16 view .LVU728 + 2510 0214 0020 movs r0, #0 + 2511 0216 F4E7 b .L151 + 2512 .L181: + 2513 .align 2 + 2514 .L180: + 2515 0218 00000000 .word TIM_DMADelayPulseNCplt + 2516 021c 00000000 .word TIM_DMADelayPulseHalfCplt + 2517 0220 00000000 .word TIM_DMAErrorCCxN + 2518 0224 00000140 .word 1073807360 + 2519 0228 07000100 .word 65543 + 2520 .cfi_endproc + 2521 .LFE155: + 2523 .section .text.HAL_TIMEx_OCN_Stop_DMA,"ax",%progbits + 2524 .align 1 + 2525 .global HAL_TIMEx_OCN_Stop_DMA + 2526 .syntax unified + 2527 .thumb + 2528 .thumb_func + 2530 HAL_TIMEx_OCN_Stop_DMA: + 2531 .LVL166: + 2532 .LFB156: +1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 2533 .loc 1 1010 1 is_stmt 1 view -0 + 2534 .cfi_startproc + 2535 @ args = 0, pretend = 0, frame = 0 + 2536 @ frame_needed = 0, uses_anonymous_args = 0 +1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 2537 .loc 1 1010 1 is_stmt 0 view .LVU730 + 2538 0000 38B5 push {r3, r4, r5, lr} + 2539 .LCFI19: + 2540 .cfi_def_cfa_offset 16 + 2541 .cfi_offset 3, -16 + 2542 .cfi_offset 4, -12 + 2543 .cfi_offset 5, -8 + 2544 .cfi_offset 14, -4 + 2545 0002 0446 mov r4, r0 + 2546 0004 0D46 mov r5, r1 +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2547 .loc 1 1011 3 is_stmt 1 view .LVU731 + 2548 .LVL167: +1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2549 .loc 1 1014 3 view .LVU732 +1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2550 .loc 1 1016 3 view .LVU733 + 2551 0006 0429 cmp r1, #4 + 2552 0008 34D0 beq .L183 + 2553 000a 0829 cmp r1, #8 + 2554 000c 3BD0 beq .L184 + ARM GAS /tmp/cc3heCqB.s page 103 + + + 2555 000e 0029 cmp r1, #0 + 2556 0010 55D1 bne .L192 +1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + 2557 .loc 1 1021 7 view .LVU734 + 2558 0012 0268 ldr r2, [r0] + 2559 0014 D368 ldr r3, [r2, #12] + 2560 0016 23F40073 bic r3, r3, #512 + 2561 001a D360 str r3, [r2, #12] +1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 2562 .loc 1 1022 7 view .LVU735 +1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 2563 .loc 1 1022 13 is_stmt 0 view .LVU736 + 2564 001c 406A ldr r0, [r0, #36] + 2565 .LVL168: +1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 2566 .loc 1 1022 13 view .LVU737 + 2567 001e FFF7FEFF bl HAL_DMA_Abort_IT + 2568 .LVL169: +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2569 .loc 1 1023 7 is_stmt 1 view .LVU738 +1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2570 .loc 1 1047 3 view .LVU739 + 2571 .L186: +1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2572 .loc 1 1050 5 view .LVU740 + 2573 0022 0022 movs r2, #0 + 2574 0024 2946 mov r1, r5 + 2575 0026 2068 ldr r0, [r4] + 2576 0028 FFF7FEFF bl TIM_CCxNChannelCmd + 2577 .LVL170: +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2578 .loc 1 1053 5 view .LVU741 +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2579 .loc 1 1053 5 view .LVU742 + 2580 002c 2368 ldr r3, [r4] + 2581 002e 196A ldr r1, [r3, #32] + 2582 0030 41F21112 movw r2, #4369 + 2583 0034 1142 tst r1, r2 + 2584 0036 08D1 bne .L187 +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2585 .loc 1 1053 5 discriminator 1 view .LVU743 + 2586 0038 196A ldr r1, [r3, #32] + 2587 003a 40F24442 movw r2, #1092 + 2588 003e 1142 tst r1, r2 + 2589 0040 03D1 bne .L187 +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2590 .loc 1 1053 5 discriminator 3 view .LVU744 + 2591 0042 5A6C ldr r2, [r3, #68] + 2592 0044 22F40042 bic r2, r2, #32768 + 2593 0048 5A64 str r2, [r3, #68] + 2594 .L187: +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2595 .loc 1 1053 5 discriminator 5 view .LVU745 +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2596 .loc 1 1056 5 view .LVU746 +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2597 .loc 1 1056 5 view .LVU747 + ARM GAS /tmp/cc3heCqB.s page 104 + + + 2598 004a 2368 ldr r3, [r4] + 2599 004c 196A ldr r1, [r3, #32] + 2600 004e 41F21112 movw r2, #4369 + 2601 0052 1142 tst r1, r2 + 2602 0054 08D1 bne .L188 +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2603 .loc 1 1056 5 discriminator 1 view .LVU748 + 2604 0056 196A ldr r1, [r3, #32] + 2605 0058 40F24442 movw r2, #1092 + 2606 005c 1142 tst r1, r2 + 2607 005e 03D1 bne .L188 +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2608 .loc 1 1056 5 discriminator 3 view .LVU749 + 2609 0060 1A68 ldr r2, [r3] + 2610 0062 22F00102 bic r2, r2, #1 + 2611 0066 1A60 str r2, [r3] + 2612 .L188: +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2613 .loc 1 1056 5 discriminator 5 view .LVU750 +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2614 .loc 1 1059 5 view .LVU751 + 2615 0068 B5B9 cbnz r5, .L189 +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2616 .loc 1 1059 5 is_stmt 0 discriminator 1 view .LVU752 + 2617 006a 0123 movs r3, #1 + 2618 006c 84F84430 strb r3, [r4, #68] + 2619 0070 0020 movs r0, #0 + 2620 .L185: + 2621 .LVL171: +1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2622 .loc 1 1063 3 is_stmt 1 view .LVU753 +1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2623 .loc 1 1064 1 is_stmt 0 view .LVU754 + 2624 0072 38BD pop {r3, r4, r5, pc} + 2625 .LVL172: + 2626 .L183: +1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + 2627 .loc 1 1029 7 is_stmt 1 view .LVU755 + 2628 0074 0268 ldr r2, [r0] + 2629 0076 D368 ldr r3, [r2, #12] + 2630 0078 23F48063 bic r3, r3, #1024 + 2631 007c D360 str r3, [r2, #12] +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 2632 .loc 1 1030 7 view .LVU756 +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 2633 .loc 1 1030 13 is_stmt 0 view .LVU757 + 2634 007e 806A ldr r0, [r0, #40] + 2635 .LVL173: +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 2636 .loc 1 1030 13 view .LVU758 + 2637 0080 FFF7FEFF bl HAL_DMA_Abort_IT + 2638 .LVL174: +1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2639 .loc 1 1031 7 is_stmt 1 view .LVU759 +1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2640 .loc 1 1047 3 view .LVU760 + 2641 0084 CDE7 b .L186 + ARM GAS /tmp/cc3heCqB.s page 105 + + + 2642 .LVL175: + 2643 .L184: +1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + 2644 .loc 1 1037 7 view .LVU761 + 2645 0086 0268 ldr r2, [r0] + 2646 0088 D368 ldr r3, [r2, #12] + 2647 008a 23F40063 bic r3, r3, #2048 + 2648 008e D360 str r3, [r2, #12] +1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 2649 .loc 1 1038 7 view .LVU762 +1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 2650 .loc 1 1038 13 is_stmt 0 view .LVU763 + 2651 0090 C06A ldr r0, [r0, #44] + 2652 .LVL176: +1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 2653 .loc 1 1038 13 view .LVU764 + 2654 0092 FFF7FEFF bl HAL_DMA_Abort_IT + 2655 .LVL177: +1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2656 .loc 1 1039 7 is_stmt 1 view .LVU765 +1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2657 .loc 1 1047 3 view .LVU766 + 2658 0096 C4E7 b .L186 + 2659 .L189: +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2660 .loc 1 1059 5 is_stmt 0 discriminator 2 view .LVU767 + 2661 0098 042D cmp r5, #4 + 2662 009a 06D0 beq .L194 +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2663 .loc 1 1059 5 discriminator 4 view .LVU768 + 2664 009c 082D cmp r5, #8 + 2665 009e 09D0 beq .L195 +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2666 .loc 1 1059 5 discriminator 7 view .LVU769 + 2667 00a0 0123 movs r3, #1 + 2668 00a2 84F84730 strb r3, [r4, #71] + 2669 00a6 0020 movs r0, #0 + 2670 00a8 E3E7 b .L185 + 2671 .L194: +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2672 .loc 1 1059 5 discriminator 3 view .LVU770 + 2673 00aa 0123 movs r3, #1 + 2674 00ac 84F84530 strb r3, [r4, #69] + 2675 00b0 0020 movs r0, #0 + 2676 00b2 DEE7 b .L185 + 2677 .L195: +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2678 .loc 1 1059 5 discriminator 6 view .LVU771 + 2679 00b4 0123 movs r3, #1 + 2680 00b6 84F84630 strb r3, [r4, #70] + 2681 00ba 0020 movs r0, #0 + 2682 00bc D9E7 b .L185 + 2683 .LVL178: + 2684 .L192: +1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2685 .loc 1 1016 3 view .LVU772 + 2686 00be 0120 movs r0, #1 + ARM GAS /tmp/cc3heCqB.s page 106 + + + 2687 .LVL179: +1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2688 .loc 1 1016 3 view .LVU773 + 2689 00c0 D7E7 b .L185 + 2690 .cfi_endproc + 2691 .LFE156: + 2693 .section .text.HAL_TIMEx_PWMN_Start,"ax",%progbits + 2694 .align 1 + 2695 .global HAL_TIMEx_PWMN_Start + 2696 .syntax unified + 2697 .thumb + 2698 .thumb_func + 2700 HAL_TIMEx_PWMN_Start: + 2701 .LVL180: + 2702 .LFB157: +1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 2703 .loc 1 1100 1 is_stmt 1 view -0 + 2704 .cfi_startproc + 2705 @ args = 0, pretend = 0, frame = 0 + 2706 @ frame_needed = 0, uses_anonymous_args = 0 +1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 2707 .loc 1 1100 1 is_stmt 0 view .LVU775 + 2708 0000 10B5 push {r4, lr} + 2709 .LCFI20: + 2710 .cfi_def_cfa_offset 8 + 2711 .cfi_offset 4, -8 + 2712 .cfi_offset 14, -4 + 2713 0002 0446 mov r4, r0 +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2714 .loc 1 1101 3 is_stmt 1 view .LVU776 +1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2715 .loc 1 1104 3 view .LVU777 +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2716 .loc 1 1107 3 view .LVU778 +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2717 .loc 1 1107 46 is_stmt 0 view .LVU779 + 2718 0004 0846 mov r0, r1 + 2719 .LVL181: +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2720 .loc 1 1107 46 view .LVU780 + 2721 0006 0029 cmp r1, #0 + 2722 0008 3BD1 bne .L197 +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2723 .loc 1 1107 7 discriminator 1 view .LVU781 + 2724 000a 94F84430 ldrb r3, [r4, #68] @ zero_extendqisi2 + 2725 000e DBB2 uxtb r3, r3 +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2726 .loc 1 1107 46 discriminator 1 view .LVU782 + 2727 0010 013B subs r3, r3, #1 + 2728 0012 18BF it ne + 2729 0014 0123 movne r3, #1 + 2730 .L198: +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2731 .loc 1 1107 6 discriminator 12 view .LVU783 + 2732 0016 002B cmp r3, #0 + 2733 0018 6AD1 bne .L208 +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + ARM GAS /tmp/cc3heCqB.s page 107 + + + 2734 .loc 1 1113 3 is_stmt 1 view .LVU784 + 2735 001a 0028 cmp r0, #0 + 2736 001c 4AD1 bne .L202 +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2737 .loc 1 1113 3 is_stmt 0 discriminator 1 view .LVU785 + 2738 001e 0223 movs r3, #2 + 2739 0020 84F84430 strb r3, [r4, #68] + 2740 .L203: +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2741 .loc 1 1116 3 is_stmt 1 view .LVU786 + 2742 0024 0422 movs r2, #4 + 2743 0026 0146 mov r1, r0 + 2744 .LVL182: +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2745 .loc 1 1116 3 is_stmt 0 view .LVU787 + 2746 0028 2068 ldr r0, [r4] + 2747 .LVL183: +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2748 .loc 1 1116 3 view .LVU788 + 2749 002a FFF7FEFF bl TIM_CCxNChannelCmd + 2750 .LVL184: +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2751 .loc 1 1119 3 is_stmt 1 view .LVU789 + 2752 002e 2268 ldr r2, [r4] + 2753 0030 536C ldr r3, [r2, #68] + 2754 0032 43F40043 orr r3, r3, #32768 + 2755 0036 5364 str r3, [r2, #68] +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2756 .loc 1 1122 3 view .LVU790 +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2757 .loc 1 1122 7 is_stmt 0 view .LVU791 + 2758 0038 2368 ldr r3, [r4] +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2759 .loc 1 1122 6 view .LVU792 + 2760 003a 2F4A ldr r2, .L215 + 2761 003c B3F1804F cmp r3, #1073741824 + 2762 0040 18BF it ne + 2763 0042 9342 cmpne r3, r2 + 2764 0044 46D0 beq .L206 +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2765 .loc 1 1122 7 discriminator 1 view .LVU793 + 2766 0046 A2F57C42 sub r2, r2, #64512 + 2767 004a 9342 cmp r3, r2 + 2768 004c 42D0 beq .L206 +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2769 .loc 1 1122 7 discriminator 2 view .LVU794 + 2770 004e 02F58062 add r2, r2, #1024 + 2771 0052 9342 cmp r3, r2 + 2772 0054 3ED0 beq .L206 +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2773 .loc 1 1122 7 discriminator 3 view .LVU795 + 2774 0056 02F58062 add r2, r2, #1024 + 2775 005a 9342 cmp r3, r2 + 2776 005c 3AD0 beq .L206 +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2777 .loc 1 1122 7 discriminator 4 view .LVU796 + 2778 005e 02F57842 add r2, r2, #63488 + ARM GAS /tmp/cc3heCqB.s page 108 + + + 2779 0062 9342 cmp r3, r2 + 2780 0064 36D0 beq .L206 +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2781 .loc 1 1122 7 discriminator 5 view .LVU797 + 2782 0066 02F57052 add r2, r2, #15360 + 2783 006a 9342 cmp r3, r2 + 2784 006c 32D0 beq .L206 +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2785 .loc 1 1122 7 discriminator 6 view .LVU798 + 2786 006e A2F59432 sub r2, r2, #75776 + 2787 0072 9342 cmp r3, r2 + 2788 0074 2ED0 beq .L206 +1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2789 .loc 1 1132 5 is_stmt 1 view .LVU799 + 2790 0076 1A68 ldr r2, [r3] + 2791 0078 42F00102 orr r2, r2, #1 + 2792 007c 1A60 str r2, [r3] +1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2793 .loc 1 1136 10 is_stmt 0 view .LVU800 + 2794 007e 0020 movs r0, #0 + 2795 0080 37E0 b .L201 + 2796 .LVL185: + 2797 .L197: +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2798 .loc 1 1107 46 discriminator 2 view .LVU801 + 2799 0082 0429 cmp r1, #4 + 2800 0084 08D0 beq .L211 +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2801 .loc 1 1107 46 discriminator 5 view .LVU802 + 2802 0086 0829 cmp r1, #8 + 2803 0088 0DD0 beq .L212 +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2804 .loc 1 1107 7 discriminator 8 view .LVU803 + 2805 008a 94F84730 ldrb r3, [r4, #71] @ zero_extendqisi2 + 2806 008e DBB2 uxtb r3, r3 +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2807 .loc 1 1107 46 discriminator 8 view .LVU804 + 2808 0090 013B subs r3, r3, #1 + 2809 0092 18BF it ne + 2810 0094 0123 movne r3, #1 + 2811 0096 BEE7 b .L198 + 2812 .L211: +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2813 .loc 1 1107 7 discriminator 4 view .LVU805 + 2814 0098 94F84530 ldrb r3, [r4, #69] @ zero_extendqisi2 + 2815 009c DBB2 uxtb r3, r3 +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2816 .loc 1 1107 46 discriminator 4 view .LVU806 + 2817 009e 013B subs r3, r3, #1 + 2818 00a0 18BF it ne + 2819 00a2 0123 movne r3, #1 + 2820 00a4 B7E7 b .L198 + 2821 .L212: +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2822 .loc 1 1107 7 discriminator 7 view .LVU807 + 2823 00a6 94F84630 ldrb r3, [r4, #70] @ zero_extendqisi2 + 2824 00aa DBB2 uxtb r3, r3 + ARM GAS /tmp/cc3heCqB.s page 109 + + +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2825 .loc 1 1107 46 discriminator 7 view .LVU808 + 2826 00ac 013B subs r3, r3, #1 + 2827 00ae 18BF it ne + 2828 00b0 0123 movne r3, #1 + 2829 00b2 B0E7 b .L198 + 2830 .L202: +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2831 .loc 1 1113 3 discriminator 2 view .LVU809 + 2832 00b4 0428 cmp r0, #4 + 2833 00b6 05D0 beq .L213 +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2834 .loc 1 1113 3 discriminator 4 view .LVU810 + 2835 00b8 0828 cmp r0, #8 + 2836 00ba 07D0 beq .L214 +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2837 .loc 1 1113 3 discriminator 7 view .LVU811 + 2838 00bc 0223 movs r3, #2 + 2839 00be 84F84730 strb r3, [r4, #71] + 2840 00c2 AFE7 b .L203 + 2841 .L213: +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2842 .loc 1 1113 3 discriminator 3 view .LVU812 + 2843 00c4 0223 movs r3, #2 + 2844 00c6 84F84530 strb r3, [r4, #69] + 2845 00ca ABE7 b .L203 + 2846 .L214: +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2847 .loc 1 1113 3 discriminator 6 view .LVU813 + 2848 00cc 0223 movs r3, #2 + 2849 00ce 84F84630 strb r3, [r4, #70] + 2850 00d2 A7E7 b .L203 + 2851 .LVL186: + 2852 .L206: +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 2853 .loc 1 1124 5 is_stmt 1 view .LVU814 +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 2854 .loc 1 1124 29 is_stmt 0 view .LVU815 + 2855 00d4 9968 ldr r1, [r3, #8] +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 2856 .loc 1 1124 13 view .LVU816 + 2857 00d6 094A ldr r2, .L215+4 + 2858 00d8 0A40 ands r2, r2, r1 + 2859 .LVL187: +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2860 .loc 1 1125 5 is_stmt 1 view .LVU817 +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 2861 .loc 1 1125 8 is_stmt 0 view .LVU818 + 2862 00da 062A cmp r2, #6 + 2863 00dc 18BF it ne + 2864 00de B2F5803F cmpne r2, #65536 + 2865 00e2 07D0 beq .L209 +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2866 .loc 1 1127 7 is_stmt 1 view .LVU819 + 2867 00e4 1A68 ldr r2, [r3] + 2868 .LVL188: +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + ARM GAS /tmp/cc3heCqB.s page 110 + + + 2869 .loc 1 1127 7 is_stmt 0 view .LVU820 + 2870 00e6 42F00102 orr r2, r2, #1 + 2871 00ea 1A60 str r2, [r3] +1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2872 .loc 1 1136 10 view .LVU821 + 2873 00ec 0020 movs r0, #0 + 2874 00ee 00E0 b .L201 + 2875 .LVL189: + 2876 .L208: +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2877 .loc 1 1109 12 view .LVU822 + 2878 00f0 0120 movs r0, #1 + 2879 .LVL190: + 2880 .L201: +1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2881 .loc 1 1137 1 view .LVU823 + 2882 00f2 10BD pop {r4, pc} + 2883 .LVL191: + 2884 .L209: +1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2885 .loc 1 1136 10 view .LVU824 + 2886 00f4 0020 movs r0, #0 + 2887 00f6 FCE7 b .L201 + 2888 .L216: + 2889 .align 2 + 2890 .L215: + 2891 00f8 00000140 .word 1073807360 + 2892 00fc 07000100 .word 65543 + 2893 .cfi_endproc + 2894 .LFE157: + 2896 .section .text.HAL_TIMEx_PWMN_Stop,"ax",%progbits + 2897 .align 1 + 2898 .global HAL_TIMEx_PWMN_Stop + 2899 .syntax unified + 2900 .thumb + 2901 .thumb_func + 2903 HAL_TIMEx_PWMN_Stop: + 2904 .LVL192: + 2905 .LFB158: +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 2906 .loc 1 1150 1 is_stmt 1 view -0 + 2907 .cfi_startproc + 2908 @ args = 0, pretend = 0, frame = 0 + 2909 @ frame_needed = 0, uses_anonymous_args = 0 +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 2910 .loc 1 1150 1 is_stmt 0 view .LVU826 + 2911 0000 38B5 push {r3, r4, r5, lr} + 2912 .LCFI21: + 2913 .cfi_def_cfa_offset 16 + 2914 .cfi_offset 3, -16 + 2915 .cfi_offset 4, -12 + 2916 .cfi_offset 5, -8 + 2917 .cfi_offset 14, -4 + 2918 0002 0446 mov r4, r0 + 2919 0004 0D46 mov r5, r1 +1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2920 .loc 1 1152 3 is_stmt 1 view .LVU827 + ARM GAS /tmp/cc3heCqB.s page 111 + + +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2921 .loc 1 1155 3 view .LVU828 + 2922 0006 0022 movs r2, #0 + 2923 0008 0068 ldr r0, [r0] + 2924 .LVL193: +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2925 .loc 1 1155 3 is_stmt 0 view .LVU829 + 2926 000a FFF7FEFF bl TIM_CCxNChannelCmd + 2927 .LVL194: +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2928 .loc 1 1158 3 is_stmt 1 view .LVU830 +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2929 .loc 1 1158 3 view .LVU831 + 2930 000e 2368 ldr r3, [r4] + 2931 0010 196A ldr r1, [r3, #32] + 2932 0012 41F21112 movw r2, #4369 + 2933 0016 1142 tst r1, r2 + 2934 0018 08D1 bne .L218 +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2935 .loc 1 1158 3 discriminator 1 view .LVU832 + 2936 001a 196A ldr r1, [r3, #32] + 2937 001c 40F24442 movw r2, #1092 + 2938 0020 1142 tst r1, r2 + 2939 0022 03D1 bne .L218 +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2940 .loc 1 1158 3 discriminator 3 view .LVU833 + 2941 0024 5A6C ldr r2, [r3, #68] + 2942 0026 22F40042 bic r2, r2, #32768 + 2943 002a 5A64 str r2, [r3, #68] + 2944 .L218: +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2945 .loc 1 1158 3 discriminator 5 view .LVU834 +1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2946 .loc 1 1161 3 view .LVU835 +1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2947 .loc 1 1161 3 view .LVU836 + 2948 002c 2368 ldr r3, [r4] + 2949 002e 196A ldr r1, [r3, #32] + 2950 0030 41F21112 movw r2, #4369 + 2951 0034 1142 tst r1, r2 + 2952 0036 08D1 bne .L219 +1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2953 .loc 1 1161 3 discriminator 1 view .LVU837 + 2954 0038 196A ldr r1, [r3, #32] + 2955 003a 40F24442 movw r2, #1092 + 2956 003e 1142 tst r1, r2 + 2957 0040 03D1 bne .L219 +1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2958 .loc 1 1161 3 discriminator 3 view .LVU838 + 2959 0042 1A68 ldr r2, [r3] + 2960 0044 22F00102 bic r2, r2, #1 + 2961 0048 1A60 str r2, [r3] + 2962 .L219: +1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2963 .loc 1 1161 3 discriminator 5 view .LVU839 +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2964 .loc 1 1164 3 view .LVU840 + ARM GAS /tmp/cc3heCqB.s page 112 + + + 2965 004a 25B9 cbnz r5, .L220 +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2966 .loc 1 1164 3 is_stmt 0 discriminator 1 view .LVU841 + 2967 004c 0123 movs r3, #1 + 2968 004e 84F84430 strb r3, [r4, #68] + 2969 .L221: +1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 2970 .loc 1 1167 3 is_stmt 1 view .LVU842 +1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2971 .loc 1 1168 1 is_stmt 0 view .LVU843 + 2972 0052 0020 movs r0, #0 + 2973 0054 38BD pop {r3, r4, r5, pc} + 2974 .LVL195: + 2975 .L220: +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2976 .loc 1 1164 3 discriminator 2 view .LVU844 + 2977 0056 042D cmp r5, #4 + 2978 0058 05D0 beq .L225 +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2979 .loc 1 1164 3 discriminator 4 view .LVU845 + 2980 005a 082D cmp r5, #8 + 2981 005c 07D0 beq .L226 +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2982 .loc 1 1164 3 discriminator 7 view .LVU846 + 2983 005e 0123 movs r3, #1 + 2984 0060 84F84730 strb r3, [r4, #71] + 2985 0064 F5E7 b .L221 + 2986 .L225: +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2987 .loc 1 1164 3 discriminator 3 view .LVU847 + 2988 0066 0123 movs r3, #1 + 2989 0068 84F84530 strb r3, [r4, #69] + 2990 006c F1E7 b .L221 + 2991 .L226: +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 2992 .loc 1 1164 3 discriminator 6 view .LVU848 + 2993 006e 0123 movs r3, #1 + 2994 0070 84F84630 strb r3, [r4, #70] + 2995 0074 EDE7 b .L221 + 2996 .cfi_endproc + 2997 .LFE158: + 2999 .section .text.HAL_TIMEx_PWMN_Start_IT,"ax",%progbits + 3000 .align 1 + 3001 .global HAL_TIMEx_PWMN_Start_IT + 3002 .syntax unified + 3003 .thumb + 3004 .thumb_func + 3006 HAL_TIMEx_PWMN_Start_IT: + 3007 .LVL196: + 3008 .LFB159: +1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 3009 .loc 1 1182 1 is_stmt 1 view -0 + 3010 .cfi_startproc + 3011 @ args = 0, pretend = 0, frame = 0 + 3012 @ frame_needed = 0, uses_anonymous_args = 0 +1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 3013 .loc 1 1182 1 is_stmt 0 view .LVU850 + ARM GAS /tmp/cc3heCqB.s page 113 + + + 3014 0000 10B5 push {r4, lr} + 3015 .LCFI22: + 3016 .cfi_def_cfa_offset 8 + 3017 .cfi_offset 4, -8 + 3018 .cfi_offset 14, -4 + 3019 0002 0446 mov r4, r0 +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 3020 .loc 1 1183 3 is_stmt 1 view .LVU851 + 3021 .LVL197: +1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3022 .loc 1 1184 3 view .LVU852 +1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3023 .loc 1 1187 3 view .LVU853 +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3024 .loc 1 1190 3 view .LVU854 +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3025 .loc 1 1190 46 is_stmt 0 view .LVU855 + 3026 0004 0846 mov r0, r1 + 3027 .LVL198: +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3028 .loc 1 1190 46 view .LVU856 + 3029 0006 0029 cmp r1, #0 + 3030 0008 46D1 bne .L228 +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3031 .loc 1 1190 7 discriminator 1 view .LVU857 + 3032 000a 94F84430 ldrb r3, [r4, #68] @ zero_extendqisi2 + 3033 000e DBB2 uxtb r3, r3 +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3034 .loc 1 1190 46 discriminator 1 view .LVU858 + 3035 0010 013B subs r3, r3, #1 + 3036 0012 18BF it ne + 3037 0014 0123 movne r3, #1 + 3038 .L229: +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3039 .loc 1 1190 6 discriminator 12 view .LVU859 + 3040 0016 002B cmp r3, #0 + 3041 0018 40F08680 bne .L242 +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3042 .loc 1 1196 3 is_stmt 1 view .LVU860 + 3043 001c 0028 cmp r0, #0 + 3044 001e 54D1 bne .L233 +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3045 .loc 1 1196 3 is_stmt 0 discriminator 1 view .LVU861 + 3046 0020 0223 movs r3, #2 + 3047 0022 84F84430 strb r3, [r4, #68] +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3048 .loc 1 1198 3 is_stmt 1 view .LVU862 + 3049 .L234: +1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 3050 .loc 1 1203 7 view .LVU863 + 3051 0026 2268 ldr r2, [r4] + 3052 0028 D368 ldr r3, [r2, #12] + 3053 002a 43F00203 orr r3, r3, #2 + 3054 002e D360 str r3, [r2, #12] +1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3055 .loc 1 1204 7 view .LVU864 +1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + ARM GAS /tmp/cc3heCqB.s page 114 + + + 3056 .loc 1 1226 3 view .LVU865 + 3057 .L239: +1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3058 .loc 1 1229 5 view .LVU866 + 3059 0030 2268 ldr r2, [r4] + 3060 0032 D368 ldr r3, [r2, #12] + 3061 0034 43F08003 orr r3, r3, #128 + 3062 0038 D360 str r3, [r2, #12] +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3063 .loc 1 1232 5 view .LVU867 + 3064 003a 0422 movs r2, #4 + 3065 003c 0146 mov r1, r0 + 3066 .LVL199: +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3067 .loc 1 1232 5 is_stmt 0 view .LVU868 + 3068 003e 2068 ldr r0, [r4] + 3069 .LVL200: +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3070 .loc 1 1232 5 view .LVU869 + 3071 0040 FFF7FEFF bl TIM_CCxNChannelCmd + 3072 .LVL201: +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3073 .loc 1 1235 5 is_stmt 1 view .LVU870 + 3074 0044 2268 ldr r2, [r4] + 3075 0046 536C ldr r3, [r2, #68] + 3076 0048 43F40043 orr r3, r3, #32768 + 3077 004c 5364 str r3, [r2, #68] +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3078 .loc 1 1238 5 view .LVU871 +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3079 .loc 1 1238 9 is_stmt 0 view .LVU872 + 3080 004e 2368 ldr r3, [r4] +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3081 .loc 1 1238 8 view .LVU873 + 3082 0050 374A ldr r2, .L250 + 3083 0052 B3F1804F cmp r3, #1073741824 + 3084 0056 18BF it ne + 3085 0058 9342 cmpne r3, r2 + 3086 005a 57D0 beq .L240 +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3087 .loc 1 1238 9 discriminator 1 view .LVU874 + 3088 005c A2F57C42 sub r2, r2, #64512 + 3089 0060 9342 cmp r3, r2 + 3090 0062 53D0 beq .L240 +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3091 .loc 1 1238 9 discriminator 2 view .LVU875 + 3092 0064 02F58062 add r2, r2, #1024 + 3093 0068 9342 cmp r3, r2 + 3094 006a 4FD0 beq .L240 +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3095 .loc 1 1238 9 discriminator 3 view .LVU876 + 3096 006c 02F58062 add r2, r2, #1024 + 3097 0070 9342 cmp r3, r2 + 3098 0072 4BD0 beq .L240 +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3099 .loc 1 1238 9 discriminator 4 view .LVU877 + 3100 0074 02F57842 add r2, r2, #63488 + ARM GAS /tmp/cc3heCqB.s page 115 + + + 3101 0078 9342 cmp r3, r2 + 3102 007a 47D0 beq .L240 +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3103 .loc 1 1238 9 discriminator 5 view .LVU878 + 3104 007c 02F57052 add r2, r2, #15360 + 3105 0080 9342 cmp r3, r2 + 3106 0082 43D0 beq .L240 +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3107 .loc 1 1238 9 discriminator 6 view .LVU879 + 3108 0084 A2F59432 sub r2, r2, #75776 + 3109 0088 9342 cmp r3, r2 + 3110 008a 3FD0 beq .L240 +1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3111 .loc 1 1248 7 is_stmt 1 view .LVU880 + 3112 008c 1A68 ldr r2, [r3] + 3113 008e 42F00102 orr r2, r2, #1 + 3114 0092 1A60 str r2, [r3] + 3115 0094 0020 movs r0, #0 + 3116 0096 48E0 b .L232 + 3117 .LVL202: + 3118 .L228: +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3119 .loc 1 1190 46 is_stmt 0 discriminator 2 view .LVU881 + 3120 0098 0429 cmp r1, #4 + 3121 009a 08D0 beq .L246 +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3122 .loc 1 1190 46 discriminator 5 view .LVU882 + 3123 009c 0829 cmp r1, #8 + 3124 009e 0DD0 beq .L247 +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3125 .loc 1 1190 7 discriminator 8 view .LVU883 + 3126 00a0 94F84730 ldrb r3, [r4, #71] @ zero_extendqisi2 + 3127 00a4 DBB2 uxtb r3, r3 +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3128 .loc 1 1190 46 discriminator 8 view .LVU884 + 3129 00a6 013B subs r3, r3, #1 + 3130 00a8 18BF it ne + 3131 00aa 0123 movne r3, #1 + 3132 00ac B3E7 b .L229 + 3133 .L246: +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3134 .loc 1 1190 7 discriminator 4 view .LVU885 + 3135 00ae 94F84530 ldrb r3, [r4, #69] @ zero_extendqisi2 + 3136 00b2 DBB2 uxtb r3, r3 +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3137 .loc 1 1190 46 discriminator 4 view .LVU886 + 3138 00b4 013B subs r3, r3, #1 + 3139 00b6 18BF it ne + 3140 00b8 0123 movne r3, #1 + 3141 00ba ACE7 b .L229 + 3142 .L247: +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3143 .loc 1 1190 7 discriminator 7 view .LVU887 + 3144 00bc 94F84630 ldrb r3, [r4, #70] @ zero_extendqisi2 + 3145 00c0 DBB2 uxtb r3, r3 +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3146 .loc 1 1190 46 discriminator 7 view .LVU888 + ARM GAS /tmp/cc3heCqB.s page 116 + + + 3147 00c2 013B subs r3, r3, #1 + 3148 00c4 18BF it ne + 3149 00c6 0123 movne r3, #1 + 3150 00c8 A5E7 b .L229 + 3151 .L233: +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3152 .loc 1 1196 3 discriminator 2 view .LVU889 + 3153 00ca 0428 cmp r0, #4 + 3154 00cc 0CD0 beq .L248 +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3155 .loc 1 1196 3 discriminator 4 view .LVU890 + 3156 00ce 0828 cmp r0, #8 + 3157 00d0 13D0 beq .L249 +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3158 .loc 1 1196 3 discriminator 7 view .LVU891 + 3159 00d2 0223 movs r3, #2 + 3160 00d4 84F84730 strb r3, [r4, #71] +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3161 .loc 1 1198 3 is_stmt 1 view .LVU892 + 3162 00d8 0428 cmp r0, #4 + 3163 00da 08D0 beq .L236 + 3164 00dc 0828 cmp r0, #8 + 3165 00de 0FD0 beq .L238 + 3166 00e0 0028 cmp r0, #0 + 3167 00e2 A0D0 beq .L234 + 3168 00e4 0120 movs r0, #1 + 3169 .LVL203: +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3170 .loc 1 1198 3 is_stmt 0 view .LVU893 + 3171 00e6 20E0 b .L232 + 3172 .LVL204: + 3173 .L248: +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3174 .loc 1 1196 3 discriminator 3 view .LVU894 + 3175 00e8 0223 movs r3, #2 + 3176 00ea 84F84530 strb r3, [r4, #69] +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3177 .loc 1 1198 3 is_stmt 1 view .LVU895 + 3178 .L236: +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 3179 .loc 1 1210 7 view .LVU896 + 3180 00ee 2268 ldr r2, [r4] + 3181 00f0 D368 ldr r3, [r2, #12] + 3182 00f2 43F00403 orr r3, r3, #4 + 3183 00f6 D360 str r3, [r2, #12] +1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3184 .loc 1 1211 7 view .LVU897 +1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3185 .loc 1 1226 3 view .LVU898 + 3186 00f8 9AE7 b .L239 + 3187 .L249: +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3188 .loc 1 1196 3 is_stmt 0 discriminator 6 view .LVU899 + 3189 00fa 0223 movs r3, #2 + 3190 00fc 84F84630 strb r3, [r4, #70] +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3191 .loc 1 1198 3 is_stmt 1 view .LVU900 + ARM GAS /tmp/cc3heCqB.s page 117 + + + 3192 .L238: +1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 3193 .loc 1 1217 7 view .LVU901 + 3194 0100 2268 ldr r2, [r4] + 3195 0102 D368 ldr r3, [r2, #12] + 3196 0104 43F00803 orr r3, r3, #8 + 3197 0108 D360 str r3, [r2, #12] +1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3198 .loc 1 1218 7 view .LVU902 +1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3199 .loc 1 1226 3 view .LVU903 + 3200 010a 91E7 b .L239 + 3201 .LVL205: + 3202 .L240: +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 3203 .loc 1 1240 7 view .LVU904 +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 3204 .loc 1 1240 31 is_stmt 0 view .LVU905 + 3205 010c 9968 ldr r1, [r3, #8] +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 3206 .loc 1 1240 15 view .LVU906 + 3207 010e 094A ldr r2, .L250+4 + 3208 0110 0A40 ands r2, r2, r1 + 3209 .LVL206: +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3210 .loc 1 1241 7 is_stmt 1 view .LVU907 +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3211 .loc 1 1241 10 is_stmt 0 view .LVU908 + 3212 0112 062A cmp r2, #6 + 3213 0114 18BF it ne + 3214 0116 B2F5803F cmpne r2, #65536 + 3215 011a 07D0 beq .L244 +1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3216 .loc 1 1243 9 is_stmt 1 view .LVU909 + 3217 011c 1A68 ldr r2, [r3] + 3218 .LVL207: +1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3219 .loc 1 1243 9 is_stmt 0 view .LVU910 + 3220 011e 42F00102 orr r2, r2, #1 + 3221 0122 1A60 str r2, [r3] + 3222 0124 0020 movs r0, #0 + 3223 0126 00E0 b .L232 + 3224 .LVL208: + 3225 .L242: +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3226 .loc 1 1192 12 view .LVU911 + 3227 0128 0120 movs r0, #1 + 3228 .LVL209: + 3229 .L232: +1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3230 .loc 1 1254 1 view .LVU912 + 3231 012a 10BD pop {r4, pc} + 3232 .LVL210: + 3233 .L244: +1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3234 .loc 1 1254 1 view .LVU913 + 3235 012c 0020 movs r0, #0 + ARM GAS /tmp/cc3heCqB.s page 118 + + + 3236 012e FCE7 b .L232 + 3237 .L251: + 3238 .align 2 + 3239 .L250: + 3240 0130 00000140 .word 1073807360 + 3241 0134 07000100 .word 65543 + 3242 .cfi_endproc + 3243 .LFE159: + 3245 .section .text.HAL_TIMEx_PWMN_Stop_IT,"ax",%progbits + 3246 .align 1 + 3247 .global HAL_TIMEx_PWMN_Stop_IT + 3248 .syntax unified + 3249 .thumb + 3250 .thumb_func + 3252 HAL_TIMEx_PWMN_Stop_IT: + 3253 .LVL211: + 3254 .LFB160: +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 3255 .loc 1 1268 1 is_stmt 1 view -0 + 3256 .cfi_startproc + 3257 @ args = 0, pretend = 0, frame = 0 + 3258 @ frame_needed = 0, uses_anonymous_args = 0 +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 3259 .loc 1 1268 1 is_stmt 0 view .LVU915 + 3260 0000 38B5 push {r3, r4, r5, lr} + 3261 .LCFI23: + 3262 .cfi_def_cfa_offset 16 + 3263 .cfi_offset 3, -16 + 3264 .cfi_offset 4, -12 + 3265 .cfi_offset 5, -8 + 3266 .cfi_offset 14, -4 + 3267 0002 0446 mov r4, r0 + 3268 0004 0D46 mov r5, r1 +1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpccer; + 3269 .loc 1 1269 3 is_stmt 1 view .LVU916 + 3270 .LVL212: +1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3271 .loc 1 1270 3 view .LVU917 +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3272 .loc 1 1273 3 view .LVU918 +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3273 .loc 1 1275 3 view .LVU919 + 3274 0006 0429 cmp r1, #4 + 3275 0008 3BD0 beq .L253 + 3276 000a 0829 cmp r1, #8 + 3277 000c 3FD0 beq .L254 + 3278 000e 0029 cmp r1, #0 + 3279 0010 56D1 bne .L263 +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 3280 .loc 1 1280 7 view .LVU920 + 3281 0012 0268 ldr r2, [r0] + 3282 0014 D368 ldr r3, [r2, #12] + 3283 0016 23F00203 bic r3, r3, #2 + 3284 001a D360 str r3, [r2, #12] +1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3285 .loc 1 1281 7 view .LVU921 +1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + ARM GAS /tmp/cc3heCqB.s page 119 + + + 3286 .loc 1 1303 3 view .LVU922 + 3287 .L256: +1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3288 .loc 1 1306 5 view .LVU923 + 3289 001c 0022 movs r2, #0 + 3290 001e 2946 mov r1, r5 + 3291 .LVL213: +1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3292 .loc 1 1306 5 is_stmt 0 view .LVU924 + 3293 0020 2068 ldr r0, [r4] + 3294 .LVL214: +1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3295 .loc 1 1306 5 view .LVU925 + 3296 0022 FFF7FEFF bl TIM_CCxNChannelCmd + 3297 .LVL215: +1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + 3298 .loc 1 1309 5 is_stmt 1 view .LVU926 +1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + 3299 .loc 1 1309 19 is_stmt 0 view .LVU927 + 3300 0026 2368 ldr r3, [r4] +1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + 3301 .loc 1 1309 13 view .LVU928 + 3302 0028 196A ldr r1, [r3, #32] + 3303 .LVL216: +1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3304 .loc 1 1310 5 is_stmt 1 view .LVU929 +1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3305 .loc 1 1310 8 is_stmt 0 view .LVU930 + 3306 002a 40F24442 movw r2, #1092 + 3307 002e 1142 tst r1, r2 + 3308 0030 03D1 bne .L257 +1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3309 .loc 1 1312 7 is_stmt 1 view .LVU931 + 3310 0032 DA68 ldr r2, [r3, #12] + 3311 0034 22F08002 bic r2, r2, #128 + 3312 0038 DA60 str r2, [r3, #12] + 3313 .L257: +1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3314 .loc 1 1316 5 view .LVU932 +1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3315 .loc 1 1316 5 view .LVU933 + 3316 003a 2368 ldr r3, [r4] + 3317 003c 196A ldr r1, [r3, #32] + 3318 .LVL217: +1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3319 .loc 1 1316 5 is_stmt 0 view .LVU934 + 3320 003e 41F21112 movw r2, #4369 + 3321 0042 1142 tst r1, r2 + 3322 0044 08D1 bne .L258 +1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3323 .loc 1 1316 5 is_stmt 1 discriminator 1 view .LVU935 + 3324 0046 196A ldr r1, [r3, #32] + 3325 0048 40F24442 movw r2, #1092 + 3326 004c 1142 tst r1, r2 + 3327 004e 03D1 bne .L258 +1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3328 .loc 1 1316 5 discriminator 3 view .LVU936 + ARM GAS /tmp/cc3heCqB.s page 120 + + + 3329 0050 5A6C ldr r2, [r3, #68] + 3330 0052 22F40042 bic r2, r2, #32768 + 3331 0056 5A64 str r2, [r3, #68] + 3332 .L258: +1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3333 .loc 1 1316 5 discriminator 5 view .LVU937 +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3334 .loc 1 1319 5 view .LVU938 +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3335 .loc 1 1319 5 view .LVU939 + 3336 0058 2368 ldr r3, [r4] + 3337 005a 196A ldr r1, [r3, #32] + 3338 005c 41F21112 movw r2, #4369 + 3339 0060 1142 tst r1, r2 + 3340 0062 08D1 bne .L259 +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3341 .loc 1 1319 5 discriminator 1 view .LVU940 + 3342 0064 196A ldr r1, [r3, #32] + 3343 0066 40F24442 movw r2, #1092 + 3344 006a 1142 tst r1, r2 + 3345 006c 03D1 bne .L259 +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3346 .loc 1 1319 5 discriminator 3 view .LVU941 + 3347 006e 1A68 ldr r2, [r3] + 3348 0070 22F00102 bic r2, r2, #1 + 3349 0074 1A60 str r2, [r3] + 3350 .L259: +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3351 .loc 1 1319 5 discriminator 5 view .LVU942 +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3352 .loc 1 1322 5 view .LVU943 + 3353 0076 85B9 cbnz r5, .L260 +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3354 .loc 1 1322 5 is_stmt 0 discriminator 1 view .LVU944 + 3355 0078 0123 movs r3, #1 + 3356 007a 84F84430 strb r3, [r4, #68] + 3357 007e 0020 movs r0, #0 + 3358 .LVL218: + 3359 .L255: +1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3360 .loc 1 1326 3 is_stmt 1 view .LVU945 +1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3361 .loc 1 1327 1 is_stmt 0 view .LVU946 + 3362 0080 38BD pop {r3, r4, r5, pc} + 3363 .LVL219: + 3364 .L253: +1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 3365 .loc 1 1287 7 is_stmt 1 view .LVU947 + 3366 0082 0268 ldr r2, [r0] + 3367 0084 D368 ldr r3, [r2, #12] + 3368 0086 23F00403 bic r3, r3, #4 + 3369 008a D360 str r3, [r2, #12] +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3370 .loc 1 1288 7 view .LVU948 +1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3371 .loc 1 1303 3 view .LVU949 + 3372 008c C6E7 b .L256 + ARM GAS /tmp/cc3heCqB.s page 121 + + + 3373 .L254: +1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 3374 .loc 1 1294 7 view .LVU950 + 3375 008e 0268 ldr r2, [r0] + 3376 0090 D368 ldr r3, [r2, #12] + 3377 0092 23F00803 bic r3, r3, #8 + 3378 0096 D360 str r3, [r2, #12] +1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3379 .loc 1 1295 7 view .LVU951 +1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3380 .loc 1 1303 3 view .LVU952 + 3381 0098 C0E7 b .L256 + 3382 .LVL220: + 3383 .L260: +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3384 .loc 1 1322 5 is_stmt 0 discriminator 2 view .LVU953 + 3385 009a 042D cmp r5, #4 + 3386 009c 06D0 beq .L265 +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3387 .loc 1 1322 5 discriminator 4 view .LVU954 + 3388 009e 082D cmp r5, #8 + 3389 00a0 09D0 beq .L266 +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3390 .loc 1 1322 5 discriminator 7 view .LVU955 + 3391 00a2 0123 movs r3, #1 + 3392 00a4 84F84730 strb r3, [r4, #71] + 3393 00a8 0020 movs r0, #0 + 3394 00aa E9E7 b .L255 + 3395 .L265: +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3396 .loc 1 1322 5 discriminator 3 view .LVU956 + 3397 00ac 0123 movs r3, #1 + 3398 00ae 84F84530 strb r3, [r4, #69] + 3399 00b2 0020 movs r0, #0 + 3400 00b4 E4E7 b .L255 + 3401 .L266: +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3402 .loc 1 1322 5 discriminator 6 view .LVU957 + 3403 00b6 0123 movs r3, #1 + 3404 00b8 84F84630 strb r3, [r4, #70] + 3405 00bc 0020 movs r0, #0 + 3406 00be DFE7 b .L255 + 3407 .LVL221: + 3408 .L263: +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3409 .loc 1 1275 3 view .LVU958 + 3410 00c0 0120 movs r0, #1 + 3411 .LVL222: +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3412 .loc 1 1275 3 view .LVU959 + 3413 00c2 DDE7 b .L255 + 3414 .cfi_endproc + 3415 .LFE160: + 3417 .section .text.HAL_TIMEx_PWMN_Start_DMA,"ax",%progbits + 3418 .align 1 + 3419 .global HAL_TIMEx_PWMN_Start_DMA + 3420 .syntax unified + ARM GAS /tmp/cc3heCqB.s page 122 + + + 3421 .thumb + 3422 .thumb_func + 3424 HAL_TIMEx_PWMN_Start_DMA: + 3425 .LVL223: + 3426 .LFB161: +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 3427 .loc 1 1344 1 is_stmt 1 view -0 + 3428 .cfi_startproc + 3429 @ args = 0, pretend = 0, frame = 0 + 3430 @ frame_needed = 0, uses_anonymous_args = 0 +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 3431 .loc 1 1344 1 is_stmt 0 view .LVU961 + 3432 0000 38B5 push {r3, r4, r5, lr} + 3433 .LCFI24: + 3434 .cfi_def_cfa_offset 16 + 3435 .cfi_offset 3, -16 + 3436 .cfi_offset 4, -12 + 3437 .cfi_offset 5, -8 + 3438 .cfi_offset 14, -4 + 3439 0002 0446 mov r4, r0 + 3440 0004 9446 mov ip, r2 +1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 3441 .loc 1 1345 3 is_stmt 1 view .LVU962 + 3442 .LVL224: +1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3443 .loc 1 1346 3 view .LVU963 +1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3444 .loc 1 1349 3 view .LVU964 +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3445 .loc 1 1352 3 view .LVU965 +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3446 .loc 1 1352 46 is_stmt 0 view .LVU966 + 3447 0006 0D46 mov r5, r1 + 3448 0008 0029 cmp r1, #0 + 3449 000a 6ED1 bne .L268 +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3450 .loc 1 1352 7 discriminator 1 view .LVU967 + 3451 000c 90F84400 ldrb r0, [r0, #68] @ zero_extendqisi2 + 3452 .LVL225: +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3453 .loc 1 1352 7 discriminator 1 view .LVU968 + 3454 0010 C0B2 uxtb r0, r0 +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3455 .loc 1 1352 46 discriminator 1 view .LVU969 + 3456 0012 0228 cmp r0, #2 + 3457 0014 14BF ite ne + 3458 0016 0020 movne r0, #0 + 3459 0018 0120 moveq r0, #1 + 3460 .L269: +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3461 .loc 1 1352 6 discriminator 12 view .LVU970 + 3462 001a 0028 cmp r0, #0 + 3463 001c 40F0EE80 bne .L286 +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3464 .loc 1 1356 8 is_stmt 1 view .LVU971 +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3465 .loc 1 1356 51 is_stmt 0 view .LVU972 + ARM GAS /tmp/cc3heCqB.s page 123 + + + 3466 0020 002D cmp r5, #0 + 3467 0022 7ED1 bne .L273 +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3468 .loc 1 1356 12 discriminator 1 view .LVU973 + 3469 0024 94F84420 ldrb r2, [r4, #68] @ zero_extendqisi2 + 3470 .LVL226: +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3471 .loc 1 1356 12 discriminator 1 view .LVU974 + 3472 0028 D2B2 uxtb r2, r2 +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3473 .loc 1 1356 51 discriminator 1 view .LVU975 + 3474 002a 012A cmp r2, #1 + 3475 002c 14BF ite ne + 3476 002e 0022 movne r2, #0 + 3477 0030 0122 moveq r2, #1 + 3478 .L274: +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3479 .loc 1 1356 11 discriminator 12 view .LVU976 + 3480 0032 002A cmp r2, #0 + 3481 0034 00F0E480 beq .L287 +1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3482 .loc 1 1358 5 is_stmt 1 view .LVU977 +1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3483 .loc 1 1358 8 is_stmt 0 view .LVU978 + 3484 0038 002B cmp r3, #0 + 3485 003a 18BF it ne + 3486 003c BCF1000F cmpne ip, #0 + 3487 0040 00F0E080 beq .L288 +1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3488 .loc 1 1364 7 is_stmt 1 view .LVU979 + 3489 0044 002D cmp r5, #0 + 3490 0046 40F08880 bne .L277 +1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3491 .loc 1 1364 7 is_stmt 0 discriminator 1 view .LVU980 + 3492 004a 0222 movs r2, #2 + 3493 004c 84F84420 strb r2, [r4, #68] +1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3494 .loc 1 1372 3 is_stmt 1 view .LVU981 + 3495 .L278: +1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 3496 .loc 1 1377 7 view .LVU982 +1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 3497 .loc 1 1377 17 is_stmt 0 view .LVU983 + 3498 0050 626A ldr r2, [r4, #36] +1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 3499 .loc 1 1377 52 view .LVU984 + 3500 0052 7149 ldr r1, .L301 + 3501 .LVL227: +1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 3502 .loc 1 1377 52 view .LVU985 + 3503 0054 D163 str r1, [r2, #60] +1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3504 .loc 1 1378 7 is_stmt 1 view .LVU986 +1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3505 .loc 1 1378 17 is_stmt 0 view .LVU987 + 3506 0056 626A ldr r2, [r4, #36] +1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + ARM GAS /tmp/cc3heCqB.s page 124 + + + 3507 .loc 1 1378 56 view .LVU988 + 3508 0058 7049 ldr r1, .L301+4 + 3509 005a 1164 str r1, [r2, #64] +1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3510 .loc 1 1381 7 is_stmt 1 view .LVU989 +1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3511 .loc 1 1381 17 is_stmt 0 view .LVU990 + 3512 005c 626A ldr r2, [r4, #36] +1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3513 .loc 1 1381 53 view .LVU991 + 3514 005e 7049 ldr r1, .L301+8 + 3515 0060 D164 str r1, [r2, #76] +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 3516 .loc 1 1384 7 is_stmt 1 view .LVU992 +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 3517 .loc 1 1384 88 is_stmt 0 view .LVU993 + 3518 0062 2268 ldr r2, [r4] +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 3519 .loc 1 1384 11 view .LVU994 + 3520 0064 3432 adds r2, r2, #52 + 3521 0066 6146 mov r1, ip + 3522 0068 606A ldr r0, [r4, #36] + 3523 006a FFF7FEFF bl HAL_DMA_Start_IT + 3524 .LVL228: +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 3525 .loc 1 1384 10 discriminator 1 view .LVU995 + 3526 006e 0028 cmp r0, #0 + 3527 0070 40F0CA80 bne .L290 +1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 3528 .loc 1 1391 7 is_stmt 1 view .LVU996 + 3529 0074 2268 ldr r2, [r4] + 3530 0076 D368 ldr r3, [r2, #12] + 3531 0078 43F40073 orr r3, r3, #512 + 3532 007c D360 str r3, [r2, #12] +1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3533 .loc 1 1392 7 view .LVU997 +1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3534 .loc 1 1442 3 view .LVU998 + 3535 .L283: +1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3536 .loc 1 1445 5 view .LVU999 + 3537 007e 0422 movs r2, #4 + 3538 0080 2946 mov r1, r5 + 3539 0082 2068 ldr r0, [r4] + 3540 0084 FFF7FEFF bl TIM_CCxNChannelCmd + 3541 .LVL229: +1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3542 .loc 1 1448 5 view .LVU1000 + 3543 0088 2268 ldr r2, [r4] + 3544 008a 536C ldr r3, [r2, #68] + 3545 008c 43F40043 orr r3, r3, #32768 + 3546 0090 5364 str r3, [r2, #68] +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3547 .loc 1 1451 5 view .LVU1001 +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3548 .loc 1 1451 9 is_stmt 0 view .LVU1002 + 3549 0092 2368 ldr r3, [r4] + ARM GAS /tmp/cc3heCqB.s page 125 + + +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3550 .loc 1 1451 8 view .LVU1003 + 3551 0094 634A ldr r2, .L301+12 + 3552 0096 B3F1804F cmp r3, #1073741824 + 3553 009a 18BF it ne + 3554 009c 9342 cmpne r3, r2 + 3555 009e 00F09F80 beq .L284 +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3556 .loc 1 1451 9 discriminator 1 view .LVU1004 + 3557 00a2 A2F57C42 sub r2, r2, #64512 + 3558 00a6 9342 cmp r3, r2 + 3559 00a8 00F09A80 beq .L284 +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3560 .loc 1 1451 9 discriminator 2 view .LVU1005 + 3561 00ac 02F58062 add r2, r2, #1024 + 3562 00b0 9342 cmp r3, r2 + 3563 00b2 00F09580 beq .L284 +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3564 .loc 1 1451 9 discriminator 3 view .LVU1006 + 3565 00b6 02F58062 add r2, r2, #1024 + 3566 00ba 9342 cmp r3, r2 + 3567 00bc 00F09080 beq .L284 +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3568 .loc 1 1451 9 discriminator 4 view .LVU1007 + 3569 00c0 02F57842 add r2, r2, #63488 + 3570 00c4 9342 cmp r3, r2 + 3571 00c6 00F08B80 beq .L284 +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3572 .loc 1 1451 9 discriminator 5 view .LVU1008 + 3573 00ca 02F57052 add r2, r2, #15360 + 3574 00ce 9342 cmp r3, r2 + 3575 00d0 00F08680 beq .L284 +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3576 .loc 1 1451 9 discriminator 6 view .LVU1009 + 3577 00d4 A2F59432 sub r2, r2, #75776 + 3578 00d8 9342 cmp r3, r2 + 3579 00da 00F08180 beq .L284 +1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3580 .loc 1 1461 7 is_stmt 1 view .LVU1010 + 3581 00de 1A68 ldr r2, [r3] + 3582 00e0 42F00102 orr r2, r2, #1 + 3583 00e4 1A60 str r2, [r3] + 3584 00e6 0020 movs r0, #0 + 3585 00e8 8BE0 b .L272 + 3586 .LVL230: + 3587 .L268: +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3588 .loc 1 1352 46 is_stmt 0 discriminator 2 view .LVU1011 + 3589 00ea 0429 cmp r1, #4 + 3590 00ec 09D0 beq .L295 +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3591 .loc 1 1352 46 discriminator 5 view .LVU1012 + 3592 00ee 0829 cmp r1, #8 + 3593 00f0 0FD0 beq .L296 +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3594 .loc 1 1352 7 discriminator 8 view .LVU1013 + 3595 00f2 90F84700 ldrb r0, [r0, #71] @ zero_extendqisi2 + ARM GAS /tmp/cc3heCqB.s page 126 + + + 3596 .LVL231: +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3597 .loc 1 1352 7 discriminator 8 view .LVU1014 + 3598 00f6 C0B2 uxtb r0, r0 +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3599 .loc 1 1352 46 discriminator 8 view .LVU1015 + 3600 00f8 0228 cmp r0, #2 + 3601 00fa 14BF ite ne + 3602 00fc 0020 movne r0, #0 + 3603 00fe 0120 moveq r0, #1 + 3604 0100 8BE7 b .L269 + 3605 .LVL232: + 3606 .L295: +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3607 .loc 1 1352 7 discriminator 4 view .LVU1016 + 3608 0102 90F84500 ldrb r0, [r0, #69] @ zero_extendqisi2 + 3609 .LVL233: +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3610 .loc 1 1352 7 discriminator 4 view .LVU1017 + 3611 0106 C0B2 uxtb r0, r0 +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3612 .loc 1 1352 46 discriminator 4 view .LVU1018 + 3613 0108 0228 cmp r0, #2 + 3614 010a 14BF ite ne + 3615 010c 0020 movne r0, #0 + 3616 010e 0120 moveq r0, #1 + 3617 0110 83E7 b .L269 + 3618 .LVL234: + 3619 .L296: +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3620 .loc 1 1352 7 discriminator 7 view .LVU1019 + 3621 0112 90F84600 ldrb r0, [r0, #70] @ zero_extendqisi2 + 3622 .LVL235: +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3623 .loc 1 1352 7 discriminator 7 view .LVU1020 + 3624 0116 C0B2 uxtb r0, r0 +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3625 .loc 1 1352 46 discriminator 7 view .LVU1021 + 3626 0118 0228 cmp r0, #2 + 3627 011a 14BF ite ne + 3628 011c 0020 movne r0, #0 + 3629 011e 0120 moveq r0, #1 + 3630 0120 7BE7 b .L269 + 3631 .L273: +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3632 .loc 1 1356 51 discriminator 2 view .LVU1022 + 3633 0122 042D cmp r5, #4 + 3634 0124 09D0 beq .L297 +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3635 .loc 1 1356 51 discriminator 5 view .LVU1023 + 3636 0126 082D cmp r5, #8 + 3637 0128 0FD0 beq .L298 +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3638 .loc 1 1356 12 discriminator 8 view .LVU1024 + 3639 012a 94F84720 ldrb r2, [r4, #71] @ zero_extendqisi2 + 3640 .LVL236: +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + ARM GAS /tmp/cc3heCqB.s page 127 + + + 3641 .loc 1 1356 12 discriminator 8 view .LVU1025 + 3642 012e D2B2 uxtb r2, r2 +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3643 .loc 1 1356 51 discriminator 8 view .LVU1026 + 3644 0130 012A cmp r2, #1 + 3645 0132 14BF ite ne + 3646 0134 0022 movne r2, #0 + 3647 0136 0122 moveq r2, #1 + 3648 0138 7BE7 b .L274 + 3649 .LVL237: + 3650 .L297: +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3651 .loc 1 1356 12 discriminator 4 view .LVU1027 + 3652 013a 94F84520 ldrb r2, [r4, #69] @ zero_extendqisi2 + 3653 .LVL238: +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3654 .loc 1 1356 12 discriminator 4 view .LVU1028 + 3655 013e D2B2 uxtb r2, r2 +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3656 .loc 1 1356 51 discriminator 4 view .LVU1029 + 3657 0140 012A cmp r2, #1 + 3658 0142 14BF ite ne + 3659 0144 0022 movne r2, #0 + 3660 0146 0122 moveq r2, #1 + 3661 0148 73E7 b .L274 + 3662 .LVL239: + 3663 .L298: +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3664 .loc 1 1356 12 discriminator 7 view .LVU1030 + 3665 014a 94F84620 ldrb r2, [r4, #70] @ zero_extendqisi2 + 3666 .LVL240: +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3667 .loc 1 1356 12 discriminator 7 view .LVU1031 + 3668 014e D2B2 uxtb r2, r2 +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3669 .loc 1 1356 51 discriminator 7 view .LVU1032 + 3670 0150 012A cmp r2, #1 + 3671 0152 14BF ite ne + 3672 0154 0022 movne r2, #0 + 3673 0156 0122 moveq r2, #1 + 3674 0158 6BE7 b .L274 + 3675 .L277: +1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3676 .loc 1 1364 7 discriminator 2 view .LVU1033 + 3677 015a 042D cmp r5, #4 + 3678 015c 0DD0 beq .L299 +1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3679 .loc 1 1364 7 discriminator 4 view .LVU1034 + 3680 015e 082D cmp r5, #8 + 3681 0160 25D0 beq .L300 +1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3682 .loc 1 1364 7 discriminator 7 view .LVU1035 + 3683 0162 0222 movs r2, #2 + 3684 0164 84F84720 strb r2, [r4, #71] +1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3685 .loc 1 1372 3 is_stmt 1 view .LVU1036 + 3686 0168 042D cmp r5, #4 + ARM GAS /tmp/cc3heCqB.s page 128 + + + 3687 016a 09D0 beq .L280 + 3688 016c 082D cmp r5, #8 + 3689 016e 21D0 beq .L282 + 3690 0170 002D cmp r5, #0 + 3691 0172 3FF46DAF beq .L278 + 3692 0176 0120 movs r0, #1 + 3693 0178 43E0 b .L272 + 3694 .L299: +1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3695 .loc 1 1364 7 is_stmt 0 discriminator 3 view .LVU1037 + 3696 017a 0222 movs r2, #2 + 3697 017c 84F84520 strb r2, [r4, #69] +1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3698 .loc 1 1372 3 is_stmt 1 view .LVU1038 + 3699 .L280: +1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 3700 .loc 1 1398 7 view .LVU1039 +1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 3701 .loc 1 1398 17 is_stmt 0 view .LVU1040 + 3702 0180 A26A ldr r2, [r4, #40] +1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 3703 .loc 1 1398 52 view .LVU1041 + 3704 0182 2549 ldr r1, .L301 + 3705 .LVL241: +1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 3706 .loc 1 1398 52 view .LVU1042 + 3707 0184 D163 str r1, [r2, #60] +1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3708 .loc 1 1399 7 is_stmt 1 view .LVU1043 +1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3709 .loc 1 1399 17 is_stmt 0 view .LVU1044 + 3710 0186 A26A ldr r2, [r4, #40] +1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3711 .loc 1 1399 56 view .LVU1045 + 3712 0188 2449 ldr r1, .L301+4 + 3713 018a 1164 str r1, [r2, #64] +1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3714 .loc 1 1402 7 is_stmt 1 view .LVU1046 +1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3715 .loc 1 1402 17 is_stmt 0 view .LVU1047 + 3716 018c A26A ldr r2, [r4, #40] +1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3717 .loc 1 1402 53 view .LVU1048 + 3718 018e 2449 ldr r1, .L301+8 + 3719 0190 D164 str r1, [r2, #76] +1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 3720 .loc 1 1405 7 is_stmt 1 view .LVU1049 +1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 3721 .loc 1 1405 88 is_stmt 0 view .LVU1050 + 3722 0192 2268 ldr r2, [r4] +1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 3723 .loc 1 1405 11 view .LVU1051 + 3724 0194 3832 adds r2, r2, #56 + 3725 0196 6146 mov r1, ip + 3726 0198 A06A ldr r0, [r4, #40] + 3727 019a FFF7FEFF bl HAL_DMA_Start_IT + 3728 .LVL242: + ARM GAS /tmp/cc3heCqB.s page 129 + + +1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 3729 .loc 1 1405 10 discriminator 1 view .LVU1052 + 3730 019e 0028 cmp r0, #0 + 3731 01a0 34D1 bne .L291 +1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 3732 .loc 1 1412 7 is_stmt 1 view .LVU1053 + 3733 01a2 2268 ldr r2, [r4] + 3734 01a4 D368 ldr r3, [r2, #12] + 3735 01a6 43F48063 orr r3, r3, #1024 + 3736 01aa D360 str r3, [r2, #12] +1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3737 .loc 1 1413 7 view .LVU1054 +1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3738 .loc 1 1442 3 view .LVU1055 + 3739 01ac 67E7 b .L283 + 3740 .LVL243: + 3741 .L300: +1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3742 .loc 1 1364 7 is_stmt 0 discriminator 6 view .LVU1056 + 3743 01ae 0222 movs r2, #2 + 3744 01b0 84F84620 strb r2, [r4, #70] +1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3745 .loc 1 1372 3 is_stmt 1 view .LVU1057 + 3746 .L282: +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 3747 .loc 1 1419 7 view .LVU1058 +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 3748 .loc 1 1419 17 is_stmt 0 view .LVU1059 + 3749 01b4 E26A ldr r2, [r4, #44] +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 3750 .loc 1 1419 52 view .LVU1060 + 3751 01b6 1849 ldr r1, .L301 + 3752 .LVL244: +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 3753 .loc 1 1419 52 view .LVU1061 + 3754 01b8 D163 str r1, [r2, #60] +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3755 .loc 1 1420 7 is_stmt 1 view .LVU1062 +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3756 .loc 1 1420 17 is_stmt 0 view .LVU1063 + 3757 01ba E26A ldr r2, [r4, #44] +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3758 .loc 1 1420 56 view .LVU1064 + 3759 01bc 1749 ldr r1, .L301+4 + 3760 01be 1164 str r1, [r2, #64] +1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3761 .loc 1 1423 7 is_stmt 1 view .LVU1065 +1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3762 .loc 1 1423 17 is_stmt 0 view .LVU1066 + 3763 01c0 E26A ldr r2, [r4, #44] +1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3764 .loc 1 1423 53 view .LVU1067 + 3765 01c2 1749 ldr r1, .L301+8 + 3766 01c4 D164 str r1, [r2, #76] +1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 3767 .loc 1 1426 7 is_stmt 1 view .LVU1068 +1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + ARM GAS /tmp/cc3heCqB.s page 130 + + + 3768 .loc 1 1426 88 is_stmt 0 view .LVU1069 + 3769 01c6 2268 ldr r2, [r4] +1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 3770 .loc 1 1426 11 view .LVU1070 + 3771 01c8 3C32 adds r2, r2, #60 + 3772 01ca 6146 mov r1, ip + 3773 01cc E06A ldr r0, [r4, #44] + 3774 01ce FFF7FEFF bl HAL_DMA_Start_IT + 3775 .LVL245: +1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** Length) != HAL_OK) + 3776 .loc 1 1426 10 discriminator 1 view .LVU1071 + 3777 01d2 E8B9 cbnz r0, .L292 +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 3778 .loc 1 1433 7 is_stmt 1 view .LVU1072 + 3779 01d4 2268 ldr r2, [r4] + 3780 01d6 D368 ldr r3, [r2, #12] + 3781 01d8 43F40063 orr r3, r3, #2048 + 3782 01dc D360 str r3, [r2, #12] +1434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3783 .loc 1 1434 7 view .LVU1073 +1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3784 .loc 1 1442 3 view .LVU1074 + 3785 01de 4EE7 b .L283 + 3786 .L284: +1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 3787 .loc 1 1453 7 view .LVU1075 +1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 3788 .loc 1 1453 31 is_stmt 0 view .LVU1076 + 3789 01e0 9968 ldr r1, [r3, #8] +1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 3790 .loc 1 1453 15 view .LVU1077 + 3791 01e2 114A ldr r2, .L301+16 + 3792 01e4 0A40 ands r2, r2, r1 + 3793 .LVL246: +1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3794 .loc 1 1454 7 is_stmt 1 view .LVU1078 +1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3795 .loc 1 1454 10 is_stmt 0 view .LVU1079 + 3796 01e6 062A cmp r2, #6 + 3797 01e8 18BF it ne + 3798 01ea B2F5803F cmpne r2, #65536 + 3799 01ee 11D0 beq .L293 +1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3800 .loc 1 1456 9 is_stmt 1 view .LVU1080 + 3801 01f0 1A68 ldr r2, [r3] + 3802 .LVL247: +1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3803 .loc 1 1456 9 is_stmt 0 view .LVU1081 + 3804 01f2 42F00102 orr r2, r2, #1 + 3805 01f6 1A60 str r2, [r3] + 3806 01f8 0020 movs r0, #0 + 3807 01fa 02E0 b .L272 + 3808 .LVL248: + 3809 .L286: +1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3810 .loc 1 1354 12 view .LVU1082 + 3811 01fc 0220 movs r0, #2 + ARM GAS /tmp/cc3heCqB.s page 131 + + + 3812 01fe 00E0 b .L272 + 3813 .LVL249: + 3814 .L287: +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3815 .loc 1 1369 12 view .LVU1083 + 3816 0200 0120 movs r0, #1 + 3817 .LVL250: + 3818 .L272: +1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3819 .loc 1 1467 1 view .LVU1084 + 3820 0202 38BD pop {r3, r4, r5, pc} + 3821 .LVL251: + 3822 .L288: +1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3823 .loc 1 1360 14 view .LVU1085 + 3824 0204 0120 movs r0, #1 + 3825 0206 FCE7 b .L272 + 3826 .LVL252: + 3827 .L290: +1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3828 .loc 1 1388 16 view .LVU1086 + 3829 0208 0120 movs r0, #1 + 3830 020a FAE7 b .L272 + 3831 .L291: +1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3832 .loc 1 1409 16 view .LVU1087 + 3833 020c 0120 movs r0, #1 + 3834 020e F8E7 b .L272 + 3835 .L292: +1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3836 .loc 1 1430 16 view .LVU1088 + 3837 0210 0120 movs r0, #1 + 3838 0212 F6E7 b .L272 + 3839 .LVL253: + 3840 .L293: +1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3841 .loc 1 1430 16 view .LVU1089 + 3842 0214 0020 movs r0, #0 + 3843 0216 F4E7 b .L272 + 3844 .L302: + 3845 .align 2 + 3846 .L301: + 3847 0218 00000000 .word TIM_DMADelayPulseNCplt + 3848 021c 00000000 .word TIM_DMADelayPulseHalfCplt + 3849 0220 00000000 .word TIM_DMAErrorCCxN + 3850 0224 00000140 .word 1073807360 + 3851 0228 07000100 .word 65543 + 3852 .cfi_endproc + 3853 .LFE161: + 3855 .section .text.HAL_TIMEx_PWMN_Stop_DMA,"ax",%progbits + 3856 .align 1 + 3857 .global HAL_TIMEx_PWMN_Stop_DMA + 3858 .syntax unified + 3859 .thumb + 3860 .thumb_func + 3862 HAL_TIMEx_PWMN_Stop_DMA: + 3863 .LVL254: + ARM GAS /tmp/cc3heCqB.s page 132 + + + 3864 .LFB162: +1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 3865 .loc 1 1481 1 is_stmt 1 view -0 + 3866 .cfi_startproc + 3867 @ args = 0, pretend = 0, frame = 0 + 3868 @ frame_needed = 0, uses_anonymous_args = 0 +1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 3869 .loc 1 1481 1 is_stmt 0 view .LVU1091 + 3870 0000 38B5 push {r3, r4, r5, lr} + 3871 .LCFI25: + 3872 .cfi_def_cfa_offset 16 + 3873 .cfi_offset 3, -16 + 3874 .cfi_offset 4, -12 + 3875 .cfi_offset 5, -8 + 3876 .cfi_offset 14, -4 + 3877 0002 0446 mov r4, r0 + 3878 0004 0D46 mov r5, r1 +1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3879 .loc 1 1482 3 is_stmt 1 view .LVU1092 + 3880 .LVL255: +1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3881 .loc 1 1485 3 view .LVU1093 +1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3882 .loc 1 1487 3 view .LVU1094 + 3883 0006 0429 cmp r1, #4 + 3884 0008 34D0 beq .L304 + 3885 000a 0829 cmp r1, #8 + 3886 000c 3BD0 beq .L305 + 3887 000e 0029 cmp r1, #0 + 3888 0010 55D1 bne .L313 +1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + 3889 .loc 1 1492 7 view .LVU1095 + 3890 0012 0268 ldr r2, [r0] + 3891 0014 D368 ldr r3, [r2, #12] + 3892 0016 23F40073 bic r3, r3, #512 + 3893 001a D360 str r3, [r2, #12] +1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 3894 .loc 1 1493 7 view .LVU1096 +1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 3895 .loc 1 1493 13 is_stmt 0 view .LVU1097 + 3896 001c 406A ldr r0, [r0, #36] + 3897 .LVL256: +1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 3898 .loc 1 1493 13 view .LVU1098 + 3899 001e FFF7FEFF bl HAL_DMA_Abort_IT + 3900 .LVL257: +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3901 .loc 1 1494 7 is_stmt 1 view .LVU1099 +1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3902 .loc 1 1518 3 view .LVU1100 + 3903 .L307: +1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3904 .loc 1 1521 5 view .LVU1101 + 3905 0022 0022 movs r2, #0 + 3906 0024 2946 mov r1, r5 + 3907 0026 2068 ldr r0, [r4] + 3908 0028 FFF7FEFF bl TIM_CCxNChannelCmd + ARM GAS /tmp/cc3heCqB.s page 133 + + + 3909 .LVL258: +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3910 .loc 1 1524 5 view .LVU1102 +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3911 .loc 1 1524 5 view .LVU1103 + 3912 002c 2368 ldr r3, [r4] + 3913 002e 196A ldr r1, [r3, #32] + 3914 0030 41F21112 movw r2, #4369 + 3915 0034 1142 tst r1, r2 + 3916 0036 08D1 bne .L308 +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3917 .loc 1 1524 5 discriminator 1 view .LVU1104 + 3918 0038 196A ldr r1, [r3, #32] + 3919 003a 40F24442 movw r2, #1092 + 3920 003e 1142 tst r1, r2 + 3921 0040 03D1 bne .L308 +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3922 .loc 1 1524 5 discriminator 3 view .LVU1105 + 3923 0042 5A6C ldr r2, [r3, #68] + 3924 0044 22F40042 bic r2, r2, #32768 + 3925 0048 5A64 str r2, [r3, #68] + 3926 .L308: +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3927 .loc 1 1524 5 discriminator 5 view .LVU1106 +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3928 .loc 1 1527 5 view .LVU1107 +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3929 .loc 1 1527 5 view .LVU1108 + 3930 004a 2368 ldr r3, [r4] + 3931 004c 196A ldr r1, [r3, #32] + 3932 004e 41F21112 movw r2, #4369 + 3933 0052 1142 tst r1, r2 + 3934 0054 08D1 bne .L309 +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3935 .loc 1 1527 5 discriminator 1 view .LVU1109 + 3936 0056 196A ldr r1, [r3, #32] + 3937 0058 40F24442 movw r2, #1092 + 3938 005c 1142 tst r1, r2 + 3939 005e 03D1 bne .L309 +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3940 .loc 1 1527 5 discriminator 3 view .LVU1110 + 3941 0060 1A68 ldr r2, [r3] + 3942 0062 22F00102 bic r2, r2, #1 + 3943 0066 1A60 str r2, [r3] + 3944 .L309: +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3945 .loc 1 1527 5 discriminator 5 view .LVU1111 +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3946 .loc 1 1530 5 view .LVU1112 + 3947 0068 B5B9 cbnz r5, .L310 +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3948 .loc 1 1530 5 is_stmt 0 discriminator 1 view .LVU1113 + 3949 006a 0123 movs r3, #1 + 3950 006c 84F84430 strb r3, [r4, #68] + 3951 0070 0020 movs r0, #0 + 3952 .L306: + 3953 .LVL259: + ARM GAS /tmp/cc3heCqB.s page 134 + + +1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3954 .loc 1 1534 3 is_stmt 1 view .LVU1114 +1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 3955 .loc 1 1535 1 is_stmt 0 view .LVU1115 + 3956 0072 38BD pop {r3, r4, r5, pc} + 3957 .LVL260: + 3958 .L304: +1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + 3959 .loc 1 1500 7 is_stmt 1 view .LVU1116 + 3960 0074 0268 ldr r2, [r0] + 3961 0076 D368 ldr r3, [r2, #12] + 3962 0078 23F48063 bic r3, r3, #1024 + 3963 007c D360 str r3, [r2, #12] +1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 3964 .loc 1 1501 7 view .LVU1117 +1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 3965 .loc 1 1501 13 is_stmt 0 view .LVU1118 + 3966 007e 806A ldr r0, [r0, #40] + 3967 .LVL261: +1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 3968 .loc 1 1501 13 view .LVU1119 + 3969 0080 FFF7FEFF bl HAL_DMA_Abort_IT + 3970 .LVL262: +1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3971 .loc 1 1502 7 is_stmt 1 view .LVU1120 +1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3972 .loc 1 1518 3 view .LVU1121 + 3973 0084 CDE7 b .L307 + 3974 .LVL263: + 3975 .L305: +1508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + 3976 .loc 1 1508 7 view .LVU1122 + 3977 0086 0268 ldr r2, [r0] + 3978 0088 D368 ldr r3, [r2, #12] + 3979 008a 23F40063 bic r3, r3, #2048 + 3980 008e D360 str r3, [r2, #12] +1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 3981 .loc 1 1509 7 view .LVU1123 +1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 3982 .loc 1 1509 13 is_stmt 0 view .LVU1124 + 3983 0090 C06A ldr r0, [r0, #44] + 3984 .LVL264: +1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 3985 .loc 1 1509 13 view .LVU1125 + 3986 0092 FFF7FEFF bl HAL_DMA_Abort_IT + 3987 .LVL265: +1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3988 .loc 1 1510 7 is_stmt 1 view .LVU1126 +1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 3989 .loc 1 1518 3 view .LVU1127 + 3990 0096 C4E7 b .L307 + 3991 .L310: +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3992 .loc 1 1530 5 is_stmt 0 discriminator 2 view .LVU1128 + 3993 0098 042D cmp r5, #4 + 3994 009a 06D0 beq .L315 +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + ARM GAS /tmp/cc3heCqB.s page 135 + + + 3995 .loc 1 1530 5 discriminator 4 view .LVU1129 + 3996 009c 082D cmp r5, #8 + 3997 009e 09D0 beq .L316 +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 3998 .loc 1 1530 5 discriminator 7 view .LVU1130 + 3999 00a0 0123 movs r3, #1 + 4000 00a2 84F84730 strb r3, [r4, #71] + 4001 00a6 0020 movs r0, #0 + 4002 00a8 E3E7 b .L306 + 4003 .L315: +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4004 .loc 1 1530 5 discriminator 3 view .LVU1131 + 4005 00aa 0123 movs r3, #1 + 4006 00ac 84F84530 strb r3, [r4, #69] + 4007 00b0 0020 movs r0, #0 + 4008 00b2 DEE7 b .L306 + 4009 .L316: +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4010 .loc 1 1530 5 discriminator 6 view .LVU1132 + 4011 00b4 0123 movs r3, #1 + 4012 00b6 84F84630 strb r3, [r4, #70] + 4013 00ba 0020 movs r0, #0 + 4014 00bc D9E7 b .L306 + 4015 .LVL266: + 4016 .L313: +1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 4017 .loc 1 1487 3 view .LVU1133 + 4018 00be 0120 movs r0, #1 + 4019 .LVL267: +1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 4020 .loc 1 1487 3 view .LVU1134 + 4021 00c0 D7E7 b .L306 + 4022 .cfi_endproc + 4023 .LFE162: + 4025 .section .text.HAL_TIMEx_OnePulseN_Start,"ax",%progbits + 4026 .align 1 + 4027 .global HAL_TIMEx_OnePulseN_Start + 4028 .syntax unified + 4029 .thumb + 4030 .thumb_func + 4032 HAL_TIMEx_OnePulseN_Start: + 4033 .LVL268: + 4034 .LFB163: +1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + 4035 .loc 1 1572 1 is_stmt 1 view -0 + 4036 .cfi_startproc + 4037 @ args = 0, pretend = 0, frame = 0 + 4038 @ frame_needed = 0, uses_anonymous_args = 0 +1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + 4039 .loc 1 1572 1 is_stmt 0 view .LVU1136 + 4040 0000 38B5 push {r3, r4, r5, lr} + 4041 .LCFI26: + 4042 .cfi_def_cfa_offset 16 + 4043 .cfi_offset 3, -16 + 4044 .cfi_offset 4, -12 + 4045 .cfi_offset 5, -8 + 4046 .cfi_offset 14, -4 + ARM GAS /tmp/cc3heCqB.s page 136 + + + 4047 0002 0446 mov r4, r0 +1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 4048 .loc 1 1573 3 is_stmt 1 view .LVU1137 +1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 4049 .loc 1 1573 77 is_stmt 0 view .LVU1138 + 4050 0004 8E46 mov lr, r1 + 4051 0006 91BB cbnz r1, .L320 +1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 4052 .loc 1 1573 77 discriminator 1 view .LVU1139 + 4053 0008 0425 movs r5, #4 + 4054 .L318: + 4055 .LVL269: +1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 4056 .loc 1 1574 3 is_stmt 1 view .LVU1140 +1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 4057 .loc 1 1574 31 is_stmt 0 view .LVU1141 + 4058 000a 94F83E00 ldrb r0, [r4, #62] @ zero_extendqisi2 + 4059 .LVL270: +1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 4060 .loc 1 1574 31 view .LVU1142 + 4061 000e C0B2 uxtb r0, r0 + 4062 .LVL271: +1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 4063 .loc 1 1575 3 is_stmt 1 view .LVU1143 +1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 4064 .loc 1 1575 31 is_stmt 0 view .LVU1144 + 4065 0010 94F83F20 ldrb r2, [r4, #63] @ zero_extendqisi2 + 4066 0014 D2B2 uxtb r2, r2 + 4067 .LVL272: +1576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 4068 .loc 1 1576 3 is_stmt 1 view .LVU1145 +1576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 4069 .loc 1 1576 31 is_stmt 0 view .LVU1146 + 4070 0016 94F84430 ldrb r3, [r4, #68] @ zero_extendqisi2 + 4071 001a 5FFA83FC uxtb ip, r3 + 4072 .LVL273: +1577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4073 .loc 1 1577 3 is_stmt 1 view .LVU1147 +1577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4074 .loc 1 1577 31 is_stmt 0 view .LVU1148 + 4075 001e 94F84530 ldrb r3, [r4, #69] @ zero_extendqisi2 + 4076 0022 DBB2 uxtb r3, r3 + 4077 .LVL274: +1580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4078 .loc 1 1580 3 is_stmt 1 view .LVU1149 +1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 4079 .loc 1 1583 3 view .LVU1150 +1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 4080 .loc 1 1583 6 is_stmt 0 view .LVU1151 + 4081 0024 012A cmp r2, #1 + 4082 0026 08BF it eq + 4083 0028 0128 cmpeq r0, #1 + 4084 002a 22D1 bne .L321 +1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 4085 .loc 1 1586 41 view .LVU1152 + 4086 002c 013B subs r3, r3, #1 + 4087 .LVL275: + ARM GAS /tmp/cc3heCqB.s page 137 + + +1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 4088 .loc 1 1586 41 view .LVU1153 + 4089 002e 18BF it ne + 4090 0030 0123 movne r3, #1 + 4091 .LVL276: +1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 4092 .loc 1 1586 7 view .LVU1154 + 4093 0032 BCF1010F cmp ip, #1 + 4094 0036 1ED1 bne .L322 + 4095 0038 EBB9 cbnz r3, .L322 +1592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 4096 .loc 1 1592 3 is_stmt 1 view .LVU1155 + 4097 003a 0223 movs r3, #2 + 4098 003c 84F83E30 strb r3, [r4, #62] +1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 4099 .loc 1 1593 3 view .LVU1156 + 4100 0040 84F83F30 strb r3, [r4, #63] +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 4101 .loc 1 1594 3 view .LVU1157 + 4102 0044 84F84430 strb r3, [r4, #68] +1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4103 .loc 1 1595 3 view .LVU1158 + 4104 0048 84F84530 strb r3, [r4, #69] +1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + 4105 .loc 1 1598 3 view .LVU1159 + 4106 004c 0422 movs r2, #4 + 4107 .LVL277: +1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + 4108 .loc 1 1598 3 is_stmt 0 view .LVU1160 + 4109 004e 7146 mov r1, lr + 4110 .LVL278: +1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + 4111 .loc 1 1598 3 view .LVU1161 + 4112 0050 2068 ldr r0, [r4] + 4113 .LVL279: +1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + 4114 .loc 1 1598 3 view .LVU1162 + 4115 0052 FFF7FEFF bl TIM_CCxNChannelCmd + 4116 .LVL280: +1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4117 .loc 1 1599 3 is_stmt 1 view .LVU1163 + 4118 0056 0122 movs r2, #1 + 4119 0058 2946 mov r1, r5 + 4120 005a 2068 ldr r0, [r4] + 4121 005c FFF7FEFF bl TIM_CCxChannelCmd + 4122 .LVL281: +1602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4123 .loc 1 1602 3 view .LVU1164 + 4124 0060 2268 ldr r2, [r4] + 4125 0062 536C ldr r3, [r2, #68] + 4126 0064 43F40043 orr r3, r3, #32768 + 4127 0068 5364 str r3, [r2, #68] +1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4128 .loc 1 1605 3 view .LVU1165 +1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4129 .loc 1 1605 10 is_stmt 0 view .LVU1166 + 4130 006a 0020 movs r0, #0 + ARM GAS /tmp/cc3heCqB.s page 138 + + + 4131 006c 02E0 b .L319 + 4132 .LVL282: + 4133 .L320: +1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 4134 .loc 1 1573 77 discriminator 2 view .LVU1167 + 4135 006e 0025 movs r5, #0 + 4136 0070 CBE7 b .L318 + 4137 .LVL283: + 4138 .L321: +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4139 .loc 1 1588 12 view .LVU1168 + 4140 0072 0120 movs r0, #1 + 4141 .LVL284: + 4142 .L319: +1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4143 .loc 1 1606 1 view .LVU1169 + 4144 0074 38BD pop {r3, r4, r5, pc} + 4145 .LVL285: + 4146 .L322: +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4147 .loc 1 1588 12 view .LVU1170 + 4148 0076 0120 movs r0, #1 + 4149 .LVL286: +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4150 .loc 1 1588 12 view .LVU1171 + 4151 0078 FCE7 b .L319 + 4152 .cfi_endproc + 4153 .LFE163: + 4155 .section .text.HAL_TIMEx_OnePulseN_Stop,"ax",%progbits + 4156 .align 1 + 4157 .global HAL_TIMEx_OnePulseN_Stop + 4158 .syntax unified + 4159 .thumb + 4160 .thumb_func + 4162 HAL_TIMEx_OnePulseN_Stop: + 4163 .LVL287: + 4164 .LFB164: +1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + 4165 .loc 1 1621 1 is_stmt 1 view -0 + 4166 .cfi_startproc + 4167 @ args = 0, pretend = 0, frame = 0 + 4168 @ frame_needed = 0, uses_anonymous_args = 0 +1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + 4169 .loc 1 1621 1 is_stmt 0 view .LVU1173 + 4170 0000 38B5 push {r3, r4, r5, lr} + 4171 .LCFI27: + 4172 .cfi_def_cfa_offset 16 + 4173 .cfi_offset 3, -16 + 4174 .cfi_offset 4, -12 + 4175 .cfi_offset 5, -8 + 4176 .cfi_offset 14, -4 + 4177 0002 0446 mov r4, r0 +1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4178 .loc 1 1622 3 is_stmt 1 view .LVU1174 +1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4179 .loc 1 1622 77 is_stmt 0 view .LVU1175 + 4180 0004 0029 cmp r1, #0 + ARM GAS /tmp/cc3heCqB.s page 139 + + + 4181 0006 32D1 bne .L328 +1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4182 .loc 1 1622 77 discriminator 1 view .LVU1176 + 4183 0008 0425 movs r5, #4 + 4184 .L325: + 4185 .LVL288: +1625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4186 .loc 1 1625 3 is_stmt 1 view .LVU1177 +1628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + 4187 .loc 1 1628 3 view .LVU1178 + 4188 000a 0022 movs r2, #0 + 4189 000c 2068 ldr r0, [r4] + 4190 .LVL289: +1628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + 4191 .loc 1 1628 3 is_stmt 0 view .LVU1179 + 4192 000e FFF7FEFF bl TIM_CCxNChannelCmd + 4193 .LVL290: +1629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4194 .loc 1 1629 3 is_stmt 1 view .LVU1180 + 4195 0012 0022 movs r2, #0 + 4196 0014 2946 mov r1, r5 + 4197 0016 2068 ldr r0, [r4] + 4198 0018 FFF7FEFF bl TIM_CCxChannelCmd + 4199 .LVL291: +1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4200 .loc 1 1632 3 view .LVU1181 +1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4201 .loc 1 1632 3 view .LVU1182 + 4202 001c 2368 ldr r3, [r4] + 4203 001e 196A ldr r1, [r3, #32] + 4204 0020 41F21112 movw r2, #4369 + 4205 0024 1142 tst r1, r2 + 4206 0026 08D1 bne .L326 +1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4207 .loc 1 1632 3 discriminator 1 view .LVU1183 + 4208 0028 196A ldr r1, [r3, #32] + 4209 002a 40F24442 movw r2, #1092 + 4210 002e 1142 tst r1, r2 + 4211 0030 03D1 bne .L326 +1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4212 .loc 1 1632 3 discriminator 3 view .LVU1184 + 4213 0032 5A6C ldr r2, [r3, #68] + 4214 0034 22F40042 bic r2, r2, #32768 + 4215 0038 5A64 str r2, [r3, #68] + 4216 .L326: +1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4217 .loc 1 1632 3 discriminator 5 view .LVU1185 +1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4218 .loc 1 1635 3 view .LVU1186 +1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4219 .loc 1 1635 3 view .LVU1187 + 4220 003a 2368 ldr r3, [r4] + 4221 003c 196A ldr r1, [r3, #32] + 4222 003e 41F21112 movw r2, #4369 + 4223 0042 1142 tst r1, r2 + 4224 0044 08D1 bne .L327 +1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + ARM GAS /tmp/cc3heCqB.s page 140 + + + 4225 .loc 1 1635 3 discriminator 1 view .LVU1188 + 4226 0046 196A ldr r1, [r3, #32] + 4227 0048 40F24442 movw r2, #1092 + 4228 004c 1142 tst r1, r2 + 4229 004e 03D1 bne .L327 +1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4230 .loc 1 1635 3 discriminator 3 view .LVU1189 + 4231 0050 1A68 ldr r2, [r3] + 4232 0052 22F00102 bic r2, r2, #1 + 4233 0056 1A60 str r2, [r3] + 4234 .L327: +1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4235 .loc 1 1635 3 discriminator 5 view .LVU1190 +1638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 4236 .loc 1 1638 3 view .LVU1191 + 4237 0058 0123 movs r3, #1 + 4238 005a 84F83E30 strb r3, [r4, #62] +1639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 4239 .loc 1 1639 3 view .LVU1192 + 4240 005e 84F83F30 strb r3, [r4, #63] +1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 4241 .loc 1 1640 3 view .LVU1193 + 4242 0062 84F84430 strb r3, [r4, #68] +1641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4243 .loc 1 1641 3 view .LVU1194 + 4244 0066 84F84530 strb r3, [r4, #69] +1644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4245 .loc 1 1644 3 view .LVU1195 +1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4246 .loc 1 1645 1 is_stmt 0 view .LVU1196 + 4247 006a 0020 movs r0, #0 + 4248 006c 38BD pop {r3, r4, r5, pc} + 4249 .LVL292: + 4250 .L328: +1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4251 .loc 1 1622 77 discriminator 2 view .LVU1197 + 4252 006e 0025 movs r5, #0 + 4253 0070 CBE7 b .L325 + 4254 .cfi_endproc + 4255 .LFE164: + 4257 .section .text.HAL_TIMEx_OnePulseN_Start_IT,"ax",%progbits + 4258 .align 1 + 4259 .global HAL_TIMEx_OnePulseN_Start_IT + 4260 .syntax unified + 4261 .thumb + 4262 .thumb_func + 4264 HAL_TIMEx_OnePulseN_Start_IT: + 4265 .LVL293: + 4266 .LFB165: +1660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + 4267 .loc 1 1660 1 is_stmt 1 view -0 + 4268 .cfi_startproc + 4269 @ args = 0, pretend = 0, frame = 0 + 4270 @ frame_needed = 0, uses_anonymous_args = 0 +1660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + 4271 .loc 1 1660 1 is_stmt 0 view .LVU1199 + 4272 0000 38B5 push {r3, r4, r5, lr} + ARM GAS /tmp/cc3heCqB.s page 141 + + + 4273 .LCFI28: + 4274 .cfi_def_cfa_offset 16 + 4275 .cfi_offset 3, -16 + 4276 .cfi_offset 4, -12 + 4277 .cfi_offset 5, -8 + 4278 .cfi_offset 14, -4 + 4279 0002 0446 mov r4, r0 +1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 4280 .loc 1 1661 3 is_stmt 1 view .LVU1200 +1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 4281 .loc 1 1661 77 is_stmt 0 view .LVU1201 + 4282 0004 8E46 mov lr, r1 + 4283 0006 0029 cmp r1, #0 + 4284 0008 3CD1 bne .L333 +1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 4285 .loc 1 1661 77 discriminator 1 view .LVU1202 + 4286 000a 0425 movs r5, #4 + 4287 .L331: + 4288 .LVL294: +1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 4289 .loc 1 1662 3 is_stmt 1 view .LVU1203 +1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 4290 .loc 1 1662 31 is_stmt 0 view .LVU1204 + 4291 000c 94F83E00 ldrb r0, [r4, #62] @ zero_extendqisi2 + 4292 .LVL295: +1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 4293 .loc 1 1662 31 view .LVU1205 + 4294 0010 C0B2 uxtb r0, r0 + 4295 .LVL296: +1663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 4296 .loc 1 1663 3 is_stmt 1 view .LVU1206 +1663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 4297 .loc 1 1663 31 is_stmt 0 view .LVU1207 + 4298 0012 94F83F20 ldrb r2, [r4, #63] @ zero_extendqisi2 + 4299 0016 D2B2 uxtb r2, r2 + 4300 .LVL297: +1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 4301 .loc 1 1664 3 is_stmt 1 view .LVU1208 +1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 4302 .loc 1 1664 31 is_stmt 0 view .LVU1209 + 4303 0018 94F84430 ldrb r3, [r4, #68] @ zero_extendqisi2 + 4304 001c 5FFA83FC uxtb ip, r3 + 4305 .LVL298: +1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4306 .loc 1 1665 3 is_stmt 1 view .LVU1210 +1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4307 .loc 1 1665 31 is_stmt 0 view .LVU1211 + 4308 0020 94F84530 ldrb r3, [r4, #69] @ zero_extendqisi2 + 4309 0024 DBB2 uxtb r3, r3 + 4310 .LVL299: +1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4311 .loc 1 1668 3 is_stmt 1 view .LVU1212 +1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 4312 .loc 1 1671 3 view .LVU1213 +1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 4313 .loc 1 1671 6 is_stmt 0 view .LVU1214 + 4314 0026 012A cmp r2, #1 + ARM GAS /tmp/cc3heCqB.s page 142 + + + 4315 0028 08BF it eq + 4316 002a 0128 cmpeq r0, #1 + 4317 002c 2CD1 bne .L334 +1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 4318 .loc 1 1674 41 view .LVU1215 + 4319 002e 013B subs r3, r3, #1 + 4320 .LVL300: +1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 4321 .loc 1 1674 41 view .LVU1216 + 4322 0030 18BF it ne + 4323 0032 0123 movne r3, #1 + 4324 .LVL301: +1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 4325 .loc 1 1674 7 view .LVU1217 + 4326 0034 BCF1010F cmp ip, #1 + 4327 0038 28D1 bne .L335 + 4328 003a 3BBB cbnz r3, .L335 +1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 4329 .loc 1 1680 3 is_stmt 1 view .LVU1218 + 4330 003c 0223 movs r3, #2 + 4331 003e 84F83E30 strb r3, [r4, #62] +1681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 4332 .loc 1 1681 3 view .LVU1219 + 4333 0042 84F83F30 strb r3, [r4, #63] +1682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 4334 .loc 1 1682 3 view .LVU1220 + 4335 0046 84F84430 strb r3, [r4, #68] +1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4336 .loc 1 1683 3 view .LVU1221 + 4337 004a 84F84530 strb r3, [r4, #69] +1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4338 .loc 1 1686 3 view .LVU1222 + 4339 004e 2268 ldr r2, [r4] + 4340 .LVL302: +1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4341 .loc 1 1686 3 is_stmt 0 view .LVU1223 + 4342 0050 D368 ldr r3, [r2, #12] + 4343 0052 43F00203 orr r3, r3, #2 + 4344 0056 D360 str r3, [r2, #12] +1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4345 .loc 1 1689 3 is_stmt 1 view .LVU1224 + 4346 0058 2268 ldr r2, [r4] + 4347 005a D368 ldr r3, [r2, #12] + 4348 005c 43F00403 orr r3, r3, #4 + 4349 0060 D360 str r3, [r2, #12] +1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + 4350 .loc 1 1692 3 view .LVU1225 + 4351 0062 0422 movs r2, #4 + 4352 0064 7146 mov r1, lr + 4353 .LVL303: +1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + 4354 .loc 1 1692 3 is_stmt 0 view .LVU1226 + 4355 0066 2068 ldr r0, [r4] + 4356 .LVL304: +1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + 4357 .loc 1 1692 3 view .LVU1227 + 4358 0068 FFF7FEFF bl TIM_CCxNChannelCmd + ARM GAS /tmp/cc3heCqB.s page 143 + + + 4359 .LVL305: +1693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4360 .loc 1 1693 3 is_stmt 1 view .LVU1228 + 4361 006c 0122 movs r2, #1 + 4362 006e 2946 mov r1, r5 + 4363 0070 2068 ldr r0, [r4] + 4364 0072 FFF7FEFF bl TIM_CCxChannelCmd + 4365 .LVL306: +1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4366 .loc 1 1696 3 view .LVU1229 + 4367 0076 2268 ldr r2, [r4] + 4368 0078 536C ldr r3, [r2, #68] + 4369 007a 43F40043 orr r3, r3, #32768 + 4370 007e 5364 str r3, [r2, #68] +1699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4371 .loc 1 1699 3 view .LVU1230 +1699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4372 .loc 1 1699 10 is_stmt 0 view .LVU1231 + 4373 0080 0020 movs r0, #0 + 4374 0082 02E0 b .L332 + 4375 .LVL307: + 4376 .L333: +1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 4377 .loc 1 1661 77 discriminator 2 view .LVU1232 + 4378 0084 0025 movs r5, #0 + 4379 0086 C1E7 b .L331 + 4380 .LVL308: + 4381 .L334: +1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4382 .loc 1 1676 12 view .LVU1233 + 4383 0088 0120 movs r0, #1 + 4384 .LVL309: + 4385 .L332: +1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4386 .loc 1 1700 1 view .LVU1234 + 4387 008a 38BD pop {r3, r4, r5, pc} + 4388 .LVL310: + 4389 .L335: +1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4390 .loc 1 1676 12 view .LVU1235 + 4391 008c 0120 movs r0, #1 + 4392 .LVL311: +1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4393 .loc 1 1676 12 view .LVU1236 + 4394 008e FCE7 b .L332 + 4395 .cfi_endproc + 4396 .LFE165: + 4398 .section .text.HAL_TIMEx_OnePulseN_Stop_IT,"ax",%progbits + 4399 .align 1 + 4400 .global HAL_TIMEx_OnePulseN_Stop_IT + 4401 .syntax unified + 4402 .thumb + 4403 .thumb_func + 4405 HAL_TIMEx_OnePulseN_Stop_IT: + 4406 .LVL312: + 4407 .LFB166: +1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + ARM GAS /tmp/cc3heCqB.s page 144 + + + 4408 .loc 1 1715 1 is_stmt 1 view -0 + 4409 .cfi_startproc + 4410 @ args = 0, pretend = 0, frame = 0 + 4411 @ frame_needed = 0, uses_anonymous_args = 0 +1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + 4412 .loc 1 1715 1 is_stmt 0 view .LVU1238 + 4413 0000 38B5 push {r3, r4, r5, lr} + 4414 .LCFI29: + 4415 .cfi_def_cfa_offset 16 + 4416 .cfi_offset 3, -16 + 4417 .cfi_offset 4, -12 + 4418 .cfi_offset 5, -8 + 4419 .cfi_offset 14, -4 + 4420 0002 0446 mov r4, r0 +1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4421 .loc 1 1716 3 is_stmt 1 view .LVU1239 +1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4422 .loc 1 1716 77 is_stmt 0 view .LVU1240 + 4423 0004 0029 cmp r1, #0 + 4424 0006 3CD1 bne .L341 +1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4425 .loc 1 1716 77 discriminator 1 view .LVU1241 + 4426 0008 0425 movs r5, #4 + 4427 .L338: + 4428 .LVL313: +1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4429 .loc 1 1719 3 is_stmt 1 view .LVU1242 +1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4430 .loc 1 1722 3 view .LVU1243 + 4431 000a 2268 ldr r2, [r4] + 4432 000c D368 ldr r3, [r2, #12] + 4433 000e 23F00203 bic r3, r3, #2 + 4434 0012 D360 str r3, [r2, #12] +1725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4435 .loc 1 1725 3 view .LVU1244 + 4436 0014 2268 ldr r2, [r4] + 4437 0016 D368 ldr r3, [r2, #12] + 4438 0018 23F00403 bic r3, r3, #4 + 4439 001c D360 str r3, [r2, #12] +1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + 4440 .loc 1 1728 3 view .LVU1245 + 4441 001e 0022 movs r2, #0 + 4442 0020 2068 ldr r0, [r4] + 4443 .LVL314: +1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + 4444 .loc 1 1728 3 is_stmt 0 view .LVU1246 + 4445 0022 FFF7FEFF bl TIM_CCxNChannelCmd + 4446 .LVL315: +1729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4447 .loc 1 1729 3 is_stmt 1 view .LVU1247 + 4448 0026 0022 movs r2, #0 + 4449 0028 2946 mov r1, r5 + 4450 002a 2068 ldr r0, [r4] + 4451 002c FFF7FEFF bl TIM_CCxChannelCmd + 4452 .LVL316: +1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4453 .loc 1 1732 3 view .LVU1248 + ARM GAS /tmp/cc3heCqB.s page 145 + + +1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4454 .loc 1 1732 3 view .LVU1249 + 4455 0030 2368 ldr r3, [r4] + 4456 0032 196A ldr r1, [r3, #32] + 4457 0034 41F21112 movw r2, #4369 + 4458 0038 1142 tst r1, r2 + 4459 003a 08D1 bne .L339 +1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4460 .loc 1 1732 3 discriminator 1 view .LVU1250 + 4461 003c 196A ldr r1, [r3, #32] + 4462 003e 40F24442 movw r2, #1092 + 4463 0042 1142 tst r1, r2 + 4464 0044 03D1 bne .L339 +1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4465 .loc 1 1732 3 discriminator 3 view .LVU1251 + 4466 0046 5A6C ldr r2, [r3, #68] + 4467 0048 22F40042 bic r2, r2, #32768 + 4468 004c 5A64 str r2, [r3, #68] + 4469 .L339: +1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4470 .loc 1 1732 3 discriminator 5 view .LVU1252 +1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4471 .loc 1 1735 3 view .LVU1253 +1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4472 .loc 1 1735 3 view .LVU1254 + 4473 004e 2368 ldr r3, [r4] + 4474 0050 196A ldr r1, [r3, #32] + 4475 0052 41F21112 movw r2, #4369 + 4476 0056 1142 tst r1, r2 + 4477 0058 08D1 bne .L340 +1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4478 .loc 1 1735 3 discriminator 1 view .LVU1255 + 4479 005a 196A ldr r1, [r3, #32] + 4480 005c 40F24442 movw r2, #1092 + 4481 0060 1142 tst r1, r2 + 4482 0062 03D1 bne .L340 +1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4483 .loc 1 1735 3 discriminator 3 view .LVU1256 + 4484 0064 1A68 ldr r2, [r3] + 4485 0066 22F00102 bic r2, r2, #1 + 4486 006a 1A60 str r2, [r3] + 4487 .L340: +1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4488 .loc 1 1735 3 discriminator 5 view .LVU1257 +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 4489 .loc 1 1738 3 view .LVU1258 + 4490 006c 0123 movs r3, #1 + 4491 006e 84F83E30 strb r3, [r4, #62] +1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 4492 .loc 1 1739 3 view .LVU1259 + 4493 0072 84F83F30 strb r3, [r4, #63] +1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 4494 .loc 1 1740 3 view .LVU1260 + 4495 0076 84F84430 strb r3, [r4, #68] +1741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4496 .loc 1 1741 3 view .LVU1261 + 4497 007a 84F84530 strb r3, [r4, #69] + ARM GAS /tmp/cc3heCqB.s page 146 + + +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4498 .loc 1 1744 3 view .LVU1262 +1745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4499 .loc 1 1745 1 is_stmt 0 view .LVU1263 + 4500 007e 0020 movs r0, #0 + 4501 0080 38BD pop {r3, r4, r5, pc} + 4502 .LVL317: + 4503 .L341: +1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4504 .loc 1 1716 77 discriminator 2 view .LVU1264 + 4505 0082 0025 movs r5, #0 + 4506 0084 C1E7 b .L338 + 4507 .cfi_endproc + 4508 .LFE166: + 4510 .section .text.HAL_TIMEx_ConfigCommutEvent,"ax",%progbits + 4511 .align 1 + 4512 .global HAL_TIMEx_ConfigCommutEvent + 4513 .syntax unified + 4514 .thumb + 4515 .thumb_func + 4517 HAL_TIMEx_ConfigCommutEvent: + 4518 .LVL318: + 4519 .LFB167: +1796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 4520 .loc 1 1796 1 is_stmt 1 view -0 + 4521 .cfi_startproc + 4522 @ args = 0, pretend = 0, frame = 0 + 4523 @ frame_needed = 0, uses_anonymous_args = 0 + 4524 @ link register save eliminated. +1796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 4525 .loc 1 1796 1 is_stmt 0 view .LVU1266 + 4526 0000 0346 mov r3, r0 +1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + 4527 .loc 1 1798 3 is_stmt 1 view .LVU1267 +1799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4528 .loc 1 1799 3 view .LVU1268 +1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4529 .loc 1 1801 3 view .LVU1269 +1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4530 .loc 1 1801 3 view .LVU1270 + 4531 0002 90F83C00 ldrb r0, [r0, #60] @ zero_extendqisi2 + 4532 .LVL319: +1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4533 .loc 1 1801 3 is_stmt 0 view .LVU1271 + 4534 0006 0128 cmp r0, #1 + 4535 0008 33D0 beq .L348 +1796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 4536 .loc 1 1796 1 view .LVU1272 + 4537 000a 10B4 push {r4} + 4538 .LCFI30: + 4539 .cfi_def_cfa_offset 4 + 4540 .cfi_offset 4, -4 +1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4541 .loc 1 1801 3 is_stmt 1 discriminator 2 view .LVU1273 + 4542 000c 0120 movs r0, #1 + 4543 000e 83F83C00 strb r0, [r3, #60] +1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + ARM GAS /tmp/cc3heCqB.s page 147 + + + 4544 .loc 1 1801 3 discriminator 2 view .LVU1274 +1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + 4545 .loc 1 1803 3 view .LVU1275 + 4546 0012 2029 cmp r1, #32 + 4547 0014 03D0 beq .L345 + 4548 0016 29D8 bhi .L346 + 4549 0018 09B1 cbz r1, .L345 + 4550 001a 1029 cmp r1, #16 + 4551 001c 08D1 bne .L347 + 4552 .L345: +1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= InputTrigger; + 4553 .loc 1 1807 5 view .LVU1276 +1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= InputTrigger; + 4554 .loc 1 1807 9 is_stmt 0 view .LVU1277 + 4555 001e 1C68 ldr r4, [r3] +1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= InputTrigger; + 4556 .loc 1 1807 19 view .LVU1278 + 4557 0020 A068 ldr r0, [r4, #8] +1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= InputTrigger; + 4558 .loc 1 1807 26 view .LVU1279 + 4559 0022 20F07000 bic r0, r0, #112 + 4560 0026 A060 str r0, [r4, #8] +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4561 .loc 1 1808 5 is_stmt 1 view .LVU1280 +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4562 .loc 1 1808 9 is_stmt 0 view .LVU1281 + 4563 0028 1C68 ldr r4, [r3] +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4564 .loc 1 1808 19 view .LVU1282 + 4565 002a A068 ldr r0, [r4, #8] +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4566 .loc 1 1808 26 view .LVU1283 + 4567 002c 0143 orrs r1, r1, r0 + 4568 .LVL320: +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4569 .loc 1 1808 26 view .LVU1284 + 4570 002e A160 str r1, [r4, #8] + 4571 .L347: +1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Commutation event source */ + 4572 .loc 1 1812 3 is_stmt 1 view .LVU1285 +1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Commutation event source */ + 4573 .loc 1 1812 7 is_stmt 0 view .LVU1286 + 4574 0030 1868 ldr r0, [r3] +1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Commutation event source */ + 4575 .loc 1 1812 17 view .LVU1287 + 4576 0032 4168 ldr r1, [r0, #4] +1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Commutation event source */ + 4577 .loc 1 1812 23 view .LVU1288 + 4578 0034 41F00101 orr r1, r1, #1 + 4579 0038 4160 str r1, [r0, #4] +1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= CommutationSource; + 4580 .loc 1 1814 3 is_stmt 1 view .LVU1289 +1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= CommutationSource; + 4581 .loc 1 1814 7 is_stmt 0 view .LVU1290 + 4582 003a 1868 ldr r0, [r3] +1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= CommutationSource; + 4583 .loc 1 1814 17 view .LVU1291 + ARM GAS /tmp/cc3heCqB.s page 148 + + + 4584 003c 4168 ldr r1, [r0, #4] +1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= CommutationSource; + 4585 .loc 1 1814 23 view .LVU1292 + 4586 003e 21F00401 bic r1, r1, #4 + 4587 0042 4160 str r1, [r0, #4] +1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4588 .loc 1 1815 3 is_stmt 1 view .LVU1293 +1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4589 .loc 1 1815 7 is_stmt 0 view .LVU1294 + 4590 0044 1868 ldr r0, [r3] +1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4591 .loc 1 1815 17 view .LVU1295 + 4592 0046 4168 ldr r1, [r0, #4] +1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4593 .loc 1 1815 23 view .LVU1296 + 4594 0048 0A43 orrs r2, r2, r1 + 4595 .LVL321: +1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4596 .loc 1 1815 23 view .LVU1297 + 4597 004a 4260 str r2, [r0, #4] +1818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4598 .loc 1 1818 3 is_stmt 1 view .LVU1298 + 4599 004c 1968 ldr r1, [r3] + 4600 004e CA68 ldr r2, [r1, #12] + 4601 0050 22F02002 bic r2, r2, #32 + 4602 0054 CA60 str r2, [r1, #12] +1821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4603 .loc 1 1821 3 view .LVU1299 + 4604 0056 1968 ldr r1, [r3] + 4605 0058 CA68 ldr r2, [r1, #12] + 4606 005a 22F40052 bic r2, r2, #8192 + 4607 005e CA60 str r2, [r1, #12] +1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4608 .loc 1 1823 3 view .LVU1300 +1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4609 .loc 1 1823 3 view .LVU1301 + 4610 0060 0020 movs r0, #0 + 4611 0062 83F83C00 strb r0, [r3, #60] +1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4612 .loc 1 1823 3 view .LVU1302 +1825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4613 .loc 1 1825 3 view .LVU1303 +1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4614 .loc 1 1826 1 is_stmt 0 view .LVU1304 + 4615 0066 5DF8044B ldr r4, [sp], #4 + 4616 .LCFI31: + 4617 .cfi_remember_state + 4618 .cfi_restore 4 + 4619 .cfi_def_cfa_offset 0 + 4620 006a 7047 bx lr + 4621 .LVL322: + 4622 .L346: + 4623 .LCFI32: + 4624 .cfi_restore_state +1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4625 .loc 1 1826 1 view .LVU1305 + 4626 006c 3029 cmp r1, #48 + ARM GAS /tmp/cc3heCqB.s page 149 + + + 4627 006e DFD1 bne .L347 + 4628 0070 D5E7 b .L345 + 4629 .L348: + 4630 .LCFI33: + 4631 .cfi_def_cfa_offset 0 + 4632 .cfi_restore 4 +1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4633 .loc 1 1801 3 discriminator 1 view .LVU1306 + 4634 0072 0220 movs r0, #2 +1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4635 .loc 1 1826 1 view .LVU1307 + 4636 0074 7047 bx lr + 4637 .cfi_endproc + 4638 .LFE167: + 4640 .section .text.HAL_TIMEx_ConfigCommutEvent_IT,"ax",%progbits + 4641 .align 1 + 4642 .global HAL_TIMEx_ConfigCommutEvent_IT + 4643 .syntax unified + 4644 .thumb + 4645 .thumb_func + 4647 HAL_TIMEx_ConfigCommutEvent_IT: + 4648 .LVL323: + 4649 .LFB168: +1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 4650 .loc 1 1852 1 is_stmt 1 view -0 + 4651 .cfi_startproc + 4652 @ args = 0, pretend = 0, frame = 0 + 4653 @ frame_needed = 0, uses_anonymous_args = 0 + 4654 @ link register save eliminated. +1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 4655 .loc 1 1852 1 is_stmt 0 view .LVU1309 + 4656 0000 0346 mov r3, r0 +1854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + 4657 .loc 1 1854 3 is_stmt 1 view .LVU1310 +1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4658 .loc 1 1855 3 view .LVU1311 +1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4659 .loc 1 1857 3 view .LVU1312 +1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4660 .loc 1 1857 3 view .LVU1313 + 4661 0002 90F83C00 ldrb r0, [r0, #60] @ zero_extendqisi2 + 4662 .LVL324: +1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4663 .loc 1 1857 3 is_stmt 0 view .LVU1314 + 4664 0006 0128 cmp r0, #1 + 4665 0008 33D0 beq .L358 +1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 4666 .loc 1 1852 1 view .LVU1315 + 4667 000a 10B4 push {r4} + 4668 .LCFI34: + 4669 .cfi_def_cfa_offset 4 + 4670 .cfi_offset 4, -4 +1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4671 .loc 1 1857 3 is_stmt 1 discriminator 2 view .LVU1316 + 4672 000c 0120 movs r0, #1 + 4673 000e 83F83C00 strb r0, [r3, #60] +1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + ARM GAS /tmp/cc3heCqB.s page 150 + + + 4674 .loc 1 1857 3 discriminator 2 view .LVU1317 +1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + 4675 .loc 1 1859 3 view .LVU1318 + 4676 0012 2029 cmp r1, #32 + 4677 0014 03D0 beq .L355 + 4678 0016 29D8 bhi .L356 + 4679 0018 09B1 cbz r1, .L355 + 4680 001a 1029 cmp r1, #16 + 4681 001c 08D1 bne .L357 + 4682 .L355: +1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= InputTrigger; + 4683 .loc 1 1863 5 view .LVU1319 +1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= InputTrigger; + 4684 .loc 1 1863 9 is_stmt 0 view .LVU1320 + 4685 001e 1C68 ldr r4, [r3] +1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= InputTrigger; + 4686 .loc 1 1863 19 view .LVU1321 + 4687 0020 A068 ldr r0, [r4, #8] +1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= InputTrigger; + 4688 .loc 1 1863 26 view .LVU1322 + 4689 0022 20F07000 bic r0, r0, #112 + 4690 0026 A060 str r0, [r4, #8] +1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4691 .loc 1 1864 5 is_stmt 1 view .LVU1323 +1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4692 .loc 1 1864 9 is_stmt 0 view .LVU1324 + 4693 0028 1C68 ldr r4, [r3] +1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4694 .loc 1 1864 19 view .LVU1325 + 4695 002a A068 ldr r0, [r4, #8] +1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4696 .loc 1 1864 26 view .LVU1326 + 4697 002c 0143 orrs r1, r1, r0 + 4698 .LVL325: +1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4699 .loc 1 1864 26 view .LVU1327 + 4700 002e A160 str r1, [r4, #8] + 4701 .L357: +1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Commutation event source */ + 4702 .loc 1 1868 3 is_stmt 1 view .LVU1328 +1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Commutation event source */ + 4703 .loc 1 1868 7 is_stmt 0 view .LVU1329 + 4704 0030 1868 ldr r0, [r3] +1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Commutation event source */ + 4705 .loc 1 1868 17 view .LVU1330 + 4706 0032 4168 ldr r1, [r0, #4] +1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Commutation event source */ + 4707 .loc 1 1868 23 view .LVU1331 + 4708 0034 41F00101 orr r1, r1, #1 + 4709 0038 4160 str r1, [r0, #4] +1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= CommutationSource; + 4710 .loc 1 1870 3 is_stmt 1 view .LVU1332 +1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= CommutationSource; + 4711 .loc 1 1870 7 is_stmt 0 view .LVU1333 + 4712 003a 1868 ldr r0, [r3] +1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= CommutationSource; + 4713 .loc 1 1870 17 view .LVU1334 + ARM GAS /tmp/cc3heCqB.s page 151 + + + 4714 003c 4168 ldr r1, [r0, #4] +1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= CommutationSource; + 4715 .loc 1 1870 23 view .LVU1335 + 4716 003e 21F00401 bic r1, r1, #4 + 4717 0042 4160 str r1, [r0, #4] +1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4718 .loc 1 1871 3 is_stmt 1 view .LVU1336 +1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4719 .loc 1 1871 7 is_stmt 0 view .LVU1337 + 4720 0044 1868 ldr r0, [r3] +1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4721 .loc 1 1871 17 view .LVU1338 + 4722 0046 4168 ldr r1, [r0, #4] +1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4723 .loc 1 1871 23 view .LVU1339 + 4724 0048 0A43 orrs r2, r2, r1 + 4725 .LVL326: +1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4726 .loc 1 1871 23 view .LVU1340 + 4727 004a 4260 str r2, [r0, #4] +1874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4728 .loc 1 1874 3 is_stmt 1 view .LVU1341 + 4729 004c 1968 ldr r1, [r3] + 4730 004e CA68 ldr r2, [r1, #12] + 4731 0050 22F40052 bic r2, r2, #8192 + 4732 0054 CA60 str r2, [r1, #12] +1877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4733 .loc 1 1877 3 view .LVU1342 + 4734 0056 1968 ldr r1, [r3] + 4735 0058 CA68 ldr r2, [r1, #12] + 4736 005a 42F02002 orr r2, r2, #32 + 4737 005e CA60 str r2, [r1, #12] +1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4738 .loc 1 1879 3 view .LVU1343 +1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4739 .loc 1 1879 3 view .LVU1344 + 4740 0060 0020 movs r0, #0 + 4741 0062 83F83C00 strb r0, [r3, #60] +1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4742 .loc 1 1879 3 view .LVU1345 +1881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4743 .loc 1 1881 3 view .LVU1346 +1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4744 .loc 1 1882 1 is_stmt 0 view .LVU1347 + 4745 0066 5DF8044B ldr r4, [sp], #4 + 4746 .LCFI35: + 4747 .cfi_remember_state + 4748 .cfi_restore 4 + 4749 .cfi_def_cfa_offset 0 + 4750 006a 7047 bx lr + 4751 .LVL327: + 4752 .L356: + 4753 .LCFI36: + 4754 .cfi_restore_state +1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4755 .loc 1 1882 1 view .LVU1348 + 4756 006c 3029 cmp r1, #48 + ARM GAS /tmp/cc3heCqB.s page 152 + + + 4757 006e DFD1 bne .L357 + 4758 0070 D5E7 b .L355 + 4759 .L358: + 4760 .LCFI37: + 4761 .cfi_def_cfa_offset 0 + 4762 .cfi_restore 4 +1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4763 .loc 1 1857 3 discriminator 1 view .LVU1349 + 4764 0072 0220 movs r0, #2 +1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4765 .loc 1 1882 1 view .LVU1350 + 4766 0074 7047 bx lr + 4767 .cfi_endproc + 4768 .LFE168: + 4770 .section .text.HAL_TIMEx_ConfigCommutEvent_DMA,"ax",%progbits + 4771 .align 1 + 4772 .global HAL_TIMEx_ConfigCommutEvent_DMA + 4773 .syntax unified + 4774 .thumb + 4775 .thumb_func + 4777 HAL_TIMEx_ConfigCommutEvent_DMA: + 4778 .LVL328: + 4779 .LFB169: +1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 4780 .loc 1 1909 1 is_stmt 1 view -0 + 4781 .cfi_startproc + 4782 @ args = 0, pretend = 0, frame = 0 + 4783 @ frame_needed = 0, uses_anonymous_args = 0 + 4784 @ link register save eliminated. +1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 4785 .loc 1 1909 1 is_stmt 0 view .LVU1352 + 4786 0000 0346 mov r3, r0 +1911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + 4787 .loc 1 1911 3 is_stmt 1 view .LVU1353 +1912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4788 .loc 1 1912 3 view .LVU1354 +1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4789 .loc 1 1914 3 view .LVU1355 +1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4790 .loc 1 1914 3 view .LVU1356 + 4791 0002 90F83C00 ldrb r0, [r0, #60] @ zero_extendqisi2 + 4792 .LVL329: +1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4793 .loc 1 1914 3 is_stmt 0 view .LVU1357 + 4794 0006 0128 cmp r0, #1 + 4795 0008 3CD0 beq .L368 +1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check the parameters */ + 4796 .loc 1 1909 1 view .LVU1358 + 4797 000a 10B4 push {r4} + 4798 .LCFI38: + 4799 .cfi_def_cfa_offset 4 + 4800 .cfi_offset 4, -4 +1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4801 .loc 1 1914 3 is_stmt 1 discriminator 2 view .LVU1359 + 4802 000c 0120 movs r0, #1 + 4803 000e 83F83C00 strb r0, [r3, #60] +1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + ARM GAS /tmp/cc3heCqB.s page 153 + + + 4804 .loc 1 1914 3 discriminator 2 view .LVU1360 +1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + 4805 .loc 1 1916 3 view .LVU1361 + 4806 0012 2029 cmp r1, #32 + 4807 0014 03D0 beq .L365 + 4808 0016 32D8 bhi .L366 + 4809 0018 09B1 cbz r1, .L365 + 4810 001a 1029 cmp r1, #16 + 4811 001c 08D1 bne .L367 + 4812 .L365: +1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= InputTrigger; + 4813 .loc 1 1920 5 view .LVU1362 +1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= InputTrigger; + 4814 .loc 1 1920 9 is_stmt 0 view .LVU1363 + 4815 001e 1C68 ldr r4, [r3] +1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= InputTrigger; + 4816 .loc 1 1920 19 view .LVU1364 + 4817 0020 A068 ldr r0, [r4, #8] +1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->SMCR |= InputTrigger; + 4818 .loc 1 1920 26 view .LVU1365 + 4819 0022 20F07000 bic r0, r0, #112 + 4820 0026 A060 str r0, [r4, #8] +1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4821 .loc 1 1921 5 is_stmt 1 view .LVU1366 +1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4822 .loc 1 1921 9 is_stmt 0 view .LVU1367 + 4823 0028 1C68 ldr r4, [r3] +1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4824 .loc 1 1921 19 view .LVU1368 + 4825 002a A068 ldr r0, [r4, #8] +1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4826 .loc 1 1921 26 view .LVU1369 + 4827 002c 0143 orrs r1, r1, r0 + 4828 .LVL330: +1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4829 .loc 1 1921 26 view .LVU1370 + 4830 002e A160 str r1, [r4, #8] + 4831 .L367: +1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Commutation event source */ + 4832 .loc 1 1925 3 is_stmt 1 view .LVU1371 +1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Commutation event source */ + 4833 .loc 1 1925 7 is_stmt 0 view .LVU1372 + 4834 0030 1868 ldr r0, [r3] +1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Commutation event source */ + 4835 .loc 1 1925 17 view .LVU1373 + 4836 0032 4168 ldr r1, [r0, #4] +1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the Commutation event source */ + 4837 .loc 1 1925 23 view .LVU1374 + 4838 0034 41F00101 orr r1, r1, #1 + 4839 0038 4160 str r1, [r0, #4] +1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= CommutationSource; + 4840 .loc 1 1927 3 is_stmt 1 view .LVU1375 +1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= CommutationSource; + 4841 .loc 1 1927 7 is_stmt 0 view .LVU1376 + 4842 003a 1868 ldr r0, [r3] +1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= CommutationSource; + 4843 .loc 1 1927 17 view .LVU1377 + ARM GAS /tmp/cc3heCqB.s page 154 + + + 4844 003c 4168 ldr r1, [r0, #4] +1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->Instance->CR2 |= CommutationSource; + 4845 .loc 1 1927 23 view .LVU1378 + 4846 003e 21F00401 bic r1, r1, #4 + 4847 0042 4160 str r1, [r0, #4] +1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4848 .loc 1 1928 3 is_stmt 1 view .LVU1379 +1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4849 .loc 1 1928 7 is_stmt 0 view .LVU1380 + 4850 0044 1868 ldr r0, [r3] +1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4851 .loc 1 1928 17 view .LVU1381 + 4852 0046 4168 ldr r1, [r0, #4] +1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4853 .loc 1 1928 23 view .LVU1382 + 4854 0048 0A43 orrs r2, r2, r1 + 4855 .LVL331: +1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4856 .loc 1 1928 23 view .LVU1383 + 4857 004a 4260 str r2, [r0, #4] +1932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + 4858 .loc 1 1932 3 is_stmt 1 view .LVU1384 +1932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + 4859 .loc 1 1932 13 is_stmt 0 view .LVU1385 + 4860 004c 5A6B ldr r2, [r3, #52] +1932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + 4861 .loc 1 1932 56 view .LVU1386 + 4862 004e 0E49 ldr r1, .L373 + 4863 0050 D163 str r1, [r2, #60] +1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA error callback */ + 4864 .loc 1 1933 3 is_stmt 1 view .LVU1387 +1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA error callback */ + 4865 .loc 1 1933 13 is_stmt 0 view .LVU1388 + 4866 0052 5A6B ldr r2, [r3, #52] +1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set the DMA error callback */ + 4867 .loc 1 1933 60 view .LVU1389 + 4868 0054 0D49 ldr r1, .L373+4 + 4869 0056 1164 str r1, [r2, #64] +1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4870 .loc 1 1935 3 is_stmt 1 view .LVU1390 +1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4871 .loc 1 1935 13 is_stmt 0 view .LVU1391 + 4872 0058 5A6B ldr r2, [r3, #52] +1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4873 .loc 1 1935 57 view .LVU1392 + 4874 005a 0D49 ldr r1, .L373+8 + 4875 005c D164 str r1, [r2, #76] +1938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4876 .loc 1 1938 3 is_stmt 1 view .LVU1393 + 4877 005e 1968 ldr r1, [r3] + 4878 0060 CA68 ldr r2, [r1, #12] + 4879 0062 22F02002 bic r2, r2, #32 + 4880 0066 CA60 str r2, [r1, #12] +1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4881 .loc 1 1941 3 view .LVU1394 + 4882 0068 1968 ldr r1, [r3] + 4883 006a CA68 ldr r2, [r1, #12] + ARM GAS /tmp/cc3heCqB.s page 155 + + + 4884 006c 42F40052 orr r2, r2, #8192 + 4885 0070 CA60 str r2, [r1, #12] +1943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4886 .loc 1 1943 3 view .LVU1395 +1943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4887 .loc 1 1943 3 view .LVU1396 + 4888 0072 0020 movs r0, #0 + 4889 0074 83F83C00 strb r0, [r3, #60] +1943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4890 .loc 1 1943 3 view .LVU1397 +1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4891 .loc 1 1945 3 view .LVU1398 +1946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4892 .loc 1 1946 1 is_stmt 0 view .LVU1399 + 4893 0078 5DF8044B ldr r4, [sp], #4 + 4894 .LCFI39: + 4895 .cfi_remember_state + 4896 .cfi_restore 4 + 4897 .cfi_def_cfa_offset 0 + 4898 007c 7047 bx lr + 4899 .LVL332: + 4900 .L366: + 4901 .LCFI40: + 4902 .cfi_restore_state +1946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4903 .loc 1 1946 1 view .LVU1400 + 4904 007e 3029 cmp r1, #48 + 4905 0080 D6D1 bne .L367 + 4906 0082 CCE7 b .L365 + 4907 .L368: + 4908 .LCFI41: + 4909 .cfi_def_cfa_offset 0 + 4910 .cfi_restore 4 +1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4911 .loc 1 1914 3 discriminator 1 view .LVU1401 + 4912 0084 0220 movs r0, #2 +1946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4913 .loc 1 1946 1 view .LVU1402 + 4914 0086 7047 bx lr + 4915 .L374: + 4916 .align 2 + 4917 .L373: + 4918 0088 00000000 .word TIMEx_DMACommutationCplt + 4919 008c 00000000 .word TIMEx_DMACommutationHalfCplt + 4920 0090 00000000 .word TIM_DMAError + 4921 .cfi_endproc + 4922 .LFE169: + 4924 .section .text.HAL_TIMEx_MasterConfigSynchronization,"ax",%progbits + 4925 .align 1 + 4926 .global HAL_TIMEx_MasterConfigSynchronization + 4927 .syntax unified + 4928 .thumb + 4929 .thumb_func + 4931 HAL_TIMEx_MasterConfigSynchronization: + 4932 .LVL333: + 4933 .LFB170: +1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpcr2; + ARM GAS /tmp/cc3heCqB.s page 156 + + + 4934 .loc 1 1958 1 is_stmt 1 view -0 + 4935 .cfi_startproc + 4936 @ args = 0, pretend = 0, frame = 0 + 4937 @ frame_needed = 0, uses_anonymous_args = 0 + 4938 @ link register save eliminated. +1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 4939 .loc 1 1959 3 view .LVU1404 +1960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4940 .loc 1 1960 3 view .LVU1405 +1963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + 4941 .loc 1 1963 3 view .LVU1406 +1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + 4942 .loc 1 1964 3 view .LVU1407 +1965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4943 .loc 1 1965 3 view .LVU1408 +1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4944 .loc 1 1968 3 view .LVU1409 +1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4945 .loc 1 1968 3 view .LVU1410 + 4946 0000 90F83C20 ldrb r2, [r0, #60] @ zero_extendqisi2 + 4947 0004 012A cmp r2, #1 + 4948 0006 45D0 beq .L380 +1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmpcr2; + 4949 .loc 1 1958 1 is_stmt 0 view .LVU1411 + 4950 0008 70B4 push {r4, r5, r6} + 4951 .LCFI42: + 4952 .cfi_def_cfa_offset 12 + 4953 .cfi_offset 4, -12 + 4954 .cfi_offset 5, -8 + 4955 .cfi_offset 6, -4 + 4956 000a 0346 mov r3, r0 +1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4957 .loc 1 1968 3 is_stmt 1 discriminator 2 view .LVU1412 + 4958 000c 0122 movs r2, #1 + 4959 000e 80F83C20 strb r2, [r0, #60] +1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4960 .loc 1 1968 3 discriminator 2 view .LVU1413 +1971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4961 .loc 1 1971 3 view .LVU1414 +1971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4962 .loc 1 1971 15 is_stmt 0 view .LVU1415 + 4963 0012 0222 movs r2, #2 + 4964 0014 80F83D20 strb r2, [r0, #61] +1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4965 .loc 1 1974 3 is_stmt 1 view .LVU1416 +1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4966 .loc 1 1974 16 is_stmt 0 view .LVU1417 + 4967 0018 0268 ldr r2, [r0] +1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4968 .loc 1 1974 10 view .LVU1418 + 4969 001a 5068 ldr r0, [r2, #4] + 4970 .LVL334: +1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4971 .loc 1 1977 3 is_stmt 1 view .LVU1419 +1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4972 .loc 1 1977 11 is_stmt 0 view .LVU1420 + 4973 001c 9468 ldr r4, [r2, #8] + ARM GAS /tmp/cc3heCqB.s page 157 + + + 4974 .LVL335: +1980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 4975 .loc 1 1980 3 is_stmt 1 view .LVU1421 +1980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 4976 .loc 1 1980 6 is_stmt 0 view .LVU1422 + 4977 001e 1E4E ldr r6, .L385 + 4978 0020 1E4D ldr r5, .L385+4 + 4979 0022 AA42 cmp r2, r5 + 4980 0024 18BF it ne + 4981 0026 B242 cmpne r2, r6 + 4982 0028 03D1 bne .L377 +1983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4983 .loc 1 1983 5 is_stmt 1 view .LVU1423 +1986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the TRGO2 source*/ + 4984 .loc 1 1986 5 view .LVU1424 +1986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the TRGO2 source*/ + 4985 .loc 1 1986 12 is_stmt 0 view .LVU1425 + 4986 002a 20F47000 bic r0, r0, #15728640 + 4987 .LVL336: +1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4988 .loc 1 1988 5 is_stmt 1 view .LVU1426 +1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4989 .loc 1 1988 28 is_stmt 0 view .LVU1427 + 4990 002e 4D68 ldr r5, [r1, #4] +1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 4991 .loc 1 1988 12 view .LVU1428 + 4992 0030 2843 orrs r0, r0, r5 + 4993 .LVL337: + 4994 .L377: +1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the TRGO source */ + 4995 .loc 1 1992 3 is_stmt 1 view .LVU1429 +1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Select the TRGO source */ + 4996 .loc 1 1992 10 is_stmt 0 view .LVU1430 + 4997 0032 20F07000 bic r0, r0, #112 + 4998 .LVL338: +1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 4999 .loc 1 1994 3 is_stmt 1 view .LVU1431 +1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5000 .loc 1 1994 10 is_stmt 0 view .LVU1432 + 5001 0036 0D68 ldr r5, [r1] + 5002 0038 2843 orrs r0, r0, r5 + 5003 .LVL339: +1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5004 .loc 1 1997 3 is_stmt 1 view .LVU1433 +1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5005 .loc 1 1997 23 is_stmt 0 view .LVU1434 + 5006 003a 5060 str r0, [r2, #4] +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 5007 .loc 1 1999 3 is_stmt 1 view .LVU1435 +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 5008 .loc 1 1999 7 is_stmt 0 view .LVU1436 + 5009 003c 1A68 ldr r2, [r3] +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 5010 .loc 1 1999 6 view .LVU1437 + 5011 003e 1648 ldr r0, .L385 + 5012 .LVL340: +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + ARM GAS /tmp/cc3heCqB.s page 158 + + + 5013 .loc 1 1999 6 view .LVU1438 + 5014 0040 B2F1804F cmp r2, #1073741824 + 5015 0044 18BF it ne + 5016 0046 8242 cmpne r2, r0 + 5017 0048 17D0 beq .L378 +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 5018 .loc 1 1999 7 discriminator 1 view .LVU1439 + 5019 004a A0F57C40 sub r0, r0, #64512 + 5020 004e 8242 cmp r2, r0 + 5021 0050 13D0 beq .L378 +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 5022 .loc 1 1999 7 discriminator 2 view .LVU1440 + 5023 0052 00F58060 add r0, r0, #1024 + 5024 0056 8242 cmp r2, r0 + 5025 0058 0FD0 beq .L378 +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 5026 .loc 1 1999 7 discriminator 3 view .LVU1441 + 5027 005a 00F58060 add r0, r0, #1024 + 5028 005e 8242 cmp r2, r0 + 5029 0060 0BD0 beq .L378 +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 5030 .loc 1 1999 7 discriminator 4 view .LVU1442 + 5031 0062 00F57840 add r0, r0, #63488 + 5032 0066 8242 cmp r2, r0 + 5033 0068 07D0 beq .L378 +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 5034 .loc 1 1999 7 discriminator 5 view .LVU1443 + 5035 006a 00F57050 add r0, r0, #15360 + 5036 006e 8242 cmp r2, r0 + 5037 0070 03D0 beq .L378 +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 5038 .loc 1 1999 7 discriminator 6 view .LVU1444 + 5039 0072 A0F59430 sub r0, r0, #75776 + 5040 0076 8242 cmp r2, r0 + 5041 0078 04D1 bne .L379 + 5042 .L378: +2002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set master mode */ + 5043 .loc 1 2002 5 is_stmt 1 view .LVU1445 +2002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Set master mode */ + 5044 .loc 1 2002 13 is_stmt 0 view .LVU1446 + 5045 007a 24F08004 bic r4, r4, #128 + 5046 .LVL341: +2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5047 .loc 1 2004 5 is_stmt 1 view .LVU1447 +2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5048 .loc 1 2004 29 is_stmt 0 view .LVU1448 + 5049 007e 8968 ldr r1, [r1, #8] + 5050 .LVL342: +2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5051 .loc 1 2004 13 view .LVU1449 + 5052 0080 2143 orrs r1, r1, r4 + 5053 .LVL343: +2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5054 .loc 1 2007 5 is_stmt 1 view .LVU1450 +2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5055 .loc 1 2007 26 is_stmt 0 view .LVU1451 + 5056 0082 9160 str r1, [r2, #8] + ARM GAS /tmp/cc3heCqB.s page 159 + + + 5057 .LVL344: + 5058 .L379: +2011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5059 .loc 1 2011 3 is_stmt 1 view .LVU1452 +2011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5060 .loc 1 2011 15 is_stmt 0 view .LVU1453 + 5061 0084 0122 movs r2, #1 + 5062 0086 83F83D20 strb r2, [r3, #61] +2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5063 .loc 1 2013 3 is_stmt 1 view .LVU1454 +2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5064 .loc 1 2013 3 view .LVU1455 + 5065 008a 0020 movs r0, #0 + 5066 008c 83F83C00 strb r0, [r3, #60] +2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5067 .loc 1 2013 3 view .LVU1456 +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5068 .loc 1 2015 3 view .LVU1457 +2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5069 .loc 1 2016 1 is_stmt 0 view .LVU1458 + 5070 0090 70BC pop {r4, r5, r6} + 5071 .LCFI43: + 5072 .cfi_restore 6 + 5073 .cfi_restore 5 + 5074 .cfi_restore 4 + 5075 .cfi_def_cfa_offset 0 + 5076 0092 7047 bx lr + 5077 .LVL345: + 5078 .L380: +1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5079 .loc 1 1968 3 discriminator 1 view .LVU1459 + 5080 0094 0220 movs r0, #2 + 5081 .LVL346: +2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5082 .loc 1 2016 1 view .LVU1460 + 5083 0096 7047 bx lr + 5084 .L386: + 5085 .align 2 + 5086 .L385: + 5087 0098 00000140 .word 1073807360 + 5088 009c 00040140 .word 1073808384 + 5089 .cfi_endproc + 5090 .LFE170: + 5092 .section .text.HAL_TIMEx_ConfigBreakDeadTime,"ax",%progbits + 5093 .align 1 + 5094 .global HAL_TIMEx_ConfigBreakDeadTime + 5095 .syntax unified + 5096 .thumb + 5097 .thumb_func + 5099 HAL_TIMEx_ConfigBreakDeadTime: + 5100 .LVL347: + 5101 .LFB171: +2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + 5102 .loc 1 2031 1 is_stmt 1 view -0 + 5103 .cfi_startproc + 5104 @ args = 0, pretend = 0, frame = 0 + 5105 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/cc3heCqB.s page 160 + + + 5106 @ link register save eliminated. +2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5107 .loc 1 2033 3 view .LVU1462 +2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + 5108 .loc 1 2036 3 view .LVU1463 +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + 5109 .loc 1 2037 3 view .LVU1464 +2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + 5110 .loc 1 2038 3 view .LVU1465 +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + 5111 .loc 1 2039 3 view .LVU1466 +2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + 5112 .loc 1 2040 3 view .LVU1467 +2041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + 5113 .loc 1 2041 3 view .LVU1468 +2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); + 5114 .loc 1 2042 3 view .LVU1469 +2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + 5115 .loc 1 2043 3 view .LVU1470 +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5116 .loc 1 2044 3 view .LVU1471 +2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5117 .loc 1 2047 3 view .LVU1472 +2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5118 .loc 1 2047 3 view .LVU1473 + 5119 0000 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 5120 0004 012B cmp r3, #1 + 5121 0006 3CD0 beq .L390 +2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + 5122 .loc 1 2031 1 is_stmt 0 view .LVU1474 + 5123 0008 30B4 push {r4, r5} + 5124 .LCFI44: + 5125 .cfi_def_cfa_offset 8 + 5126 .cfi_offset 4, -8 + 5127 .cfi_offset 5, -4 + 5128 000a 0246 mov r2, r0 +2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5129 .loc 1 2047 3 is_stmt 1 discriminator 2 view .LVU1475 + 5130 000c 0123 movs r3, #1 + 5131 000e 80F83C30 strb r3, [r0, #60] +2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5132 .loc 1 2047 3 discriminator 2 view .LVU1476 +2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + 5133 .loc 1 2053 3 view .LVU1477 + 5134 0012 CB68 ldr r3, [r1, #12] + 5135 .LVL348: +2054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + 5136 .loc 1 2054 3 view .LVU1478 + 5137 0014 23F44073 bic r3, r3, #768 + 5138 .LVL349: +2054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + 5139 .loc 1 2054 3 is_stmt 0 view .LVU1479 + 5140 0018 8868 ldr r0, [r1, #8] + 5141 .LVL350: +2054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + 5142 .loc 1 2054 3 view .LVU1480 + 5143 001a 0343 orrs r3, r3, r0 + ARM GAS /tmp/cc3heCqB.s page 161 + + + 5144 .LVL351: +2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + 5145 .loc 1 2055 3 is_stmt 1 view .LVU1481 + 5146 001c 23F48063 bic r3, r3, #1024 + 5147 .LVL352: +2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + 5148 .loc 1 2055 3 is_stmt 0 view .LVU1482 + 5149 0020 4868 ldr r0, [r1, #4] + 5150 .LVL353: +2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + 5151 .loc 1 2055 3 view .LVU1483 + 5152 0022 0343 orrs r3, r3, r0 + 5153 .LVL354: +2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + 5154 .loc 1 2056 3 is_stmt 1 view .LVU1484 + 5155 0024 23F40063 bic r3, r3, #2048 + 5156 .LVL355: +2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + 5157 .loc 1 2056 3 is_stmt 0 view .LVU1485 + 5158 0028 0868 ldr r0, [r1] + 5159 .LVL356: +2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + 5160 .loc 1 2056 3 view .LVU1486 + 5161 002a 0343 orrs r3, r3, r0 + 5162 .LVL357: +2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + 5163 .loc 1 2057 3 is_stmt 1 view .LVU1487 + 5164 002c 23F48053 bic r3, r3, #4096 + 5165 .LVL358: +2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + 5166 .loc 1 2057 3 is_stmt 0 view .LVU1488 + 5167 0030 0869 ldr r0, [r1, #16] + 5168 .LVL359: +2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + 5169 .loc 1 2057 3 view .LVU1489 + 5170 0032 0343 orrs r3, r3, r0 + 5171 .LVL360: +2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + 5172 .loc 1 2058 3 is_stmt 1 view .LVU1490 + 5173 0034 23F40053 bic r3, r3, #8192 + 5174 .LVL361: +2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + 5175 .loc 1 2058 3 is_stmt 0 view .LVU1491 + 5176 0038 4869 ldr r0, [r1, #20] + 5177 .LVL362: +2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + 5178 .loc 1 2058 3 view .LVU1492 + 5179 003a 0343 orrs r3, r3, r0 + 5180 .LVL363: +2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); + 5181 .loc 1 2059 3 is_stmt 1 view .LVU1493 + 5182 003c 23F48043 bic r3, r3, #16384 + 5183 .LVL364: +2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); + 5184 .loc 1 2059 3 is_stmt 0 view .LVU1494 + 5185 0040 886A ldr r0, [r1, #40] + 5186 .LVL365: + ARM GAS /tmp/cc3heCqB.s page 162 + + +2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); + 5187 .loc 1 2059 3 view .LVU1495 + 5188 0042 0343 orrs r3, r3, r0 + 5189 .LVL366: +2060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5190 .loc 1 2060 3 is_stmt 1 view .LVU1496 + 5191 0044 23F47023 bic r3, r3, #983040 + 5192 .LVL367: +2060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5193 .loc 1 2060 3 is_stmt 0 view .LVU1497 + 5194 0048 8869 ldr r0, [r1, #24] + 5195 .LVL368: +2060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5196 .loc 1 2060 3 view .LVU1498 + 5197 004a 43EA0043 orr r3, r3, r0, lsl #16 + 5198 .LVL369: +2062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 5199 .loc 1 2062 3 is_stmt 1 view .LVU1499 +2062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 5200 .loc 1 2062 7 is_stmt 0 view .LVU1500 + 5201 004e 1068 ldr r0, [r2] +2062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 5202 .loc 1 2062 6 view .LVU1501 + 5203 0050 0D4D ldr r5, .L395 + 5204 0052 0E4C ldr r4, .L395+4 + 5205 0054 A042 cmp r0, r4 + 5206 0056 18BF it ne + 5207 0058 A842 cmpne r0, r5 + 5208 005a 0CD1 bne .L389 +2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); + 5209 .loc 1 2065 5 is_stmt 1 view .LVU1502 +2066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + 5210 .loc 1 2066 5 view .LVU1503 +2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5211 .loc 1 2067 5 view .LVU1504 +2070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); + 5212 .loc 1 2070 5 view .LVU1505 + 5213 005c 23F47003 bic r3, r3, #15728640 + 5214 .LVL370: +2070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); + 5215 .loc 1 2070 5 is_stmt 0 view .LVU1506 + 5216 0060 4C6A ldr r4, [r1, #36] + 5217 0062 43EA0453 orr r3, r3, r4, lsl #20 + 5218 .LVL371: +2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); + 5219 .loc 1 2071 5 is_stmt 1 view .LVU1507 + 5220 0066 23F08073 bic r3, r3, #16777216 + 5221 .LVL372: +2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); + 5222 .loc 1 2071 5 is_stmt 0 view .LVU1508 + 5223 006a CC69 ldr r4, [r1, #28] + 5224 .LVL373: +2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); + 5225 .loc 1 2071 5 view .LVU1509 + 5226 006c 2343 orrs r3, r3, r4 + 5227 .LVL374: +2072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + ARM GAS /tmp/cc3heCqB.s page 163 + + + 5228 .loc 1 2072 5 is_stmt 1 view .LVU1510 + 5229 006e 23F00073 bic r3, r3, #33554432 + 5230 .LVL375: +2072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5231 .loc 1 2072 5 is_stmt 0 view .LVU1511 + 5232 0072 096A ldr r1, [r1, #32] + 5233 .LVL376: +2072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5234 .loc 1 2072 5 view .LVU1512 + 5235 0074 0B43 orrs r3, r3, r1 + 5236 .LVL377: + 5237 .L389: +2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5238 .loc 1 2076 3 is_stmt 1 view .LVU1513 +2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5239 .loc 1 2076 24 is_stmt 0 view .LVU1514 + 5240 0076 4364 str r3, [r0, #68] +2078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5241 .loc 1 2078 3 is_stmt 1 view .LVU1515 +2078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5242 .loc 1 2078 3 view .LVU1516 + 5243 0078 0020 movs r0, #0 + 5244 007a 82F83C00 strb r0, [r2, #60] +2078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5245 .loc 1 2078 3 view .LVU1517 +2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5246 .loc 1 2080 3 view .LVU1518 +2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if defined(TIM_BREAK_INPUT_SUPPORT) + 5247 .loc 1 2081 1 is_stmt 0 view .LVU1519 + 5248 007e 30BC pop {r4, r5} + 5249 .LCFI45: + 5250 .cfi_restore 5 + 5251 .cfi_restore 4 + 5252 .cfi_def_cfa_offset 0 + 5253 0080 7047 bx lr + 5254 .LVL378: + 5255 .L390: +2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5256 .loc 1 2047 3 discriminator 1 view .LVU1520 + 5257 0082 0220 movs r0, #2 + 5258 .LVL379: +2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if defined(TIM_BREAK_INPUT_SUPPORT) + 5259 .loc 1 2081 1 view .LVU1521 + 5260 0084 7047 bx lr + 5261 .L396: + 5262 0086 00BF .align 2 + 5263 .L395: + 5264 0088 00000140 .word 1073807360 + 5265 008c 00040140 .word 1073808384 + 5266 .cfi_endproc + 5267 .LFE171: + 5269 .section .text.HAL_TIMEx_ConfigBreakInput,"ax",%progbits + 5270 .align 1 + 5271 .global HAL_TIMEx_ConfigBreakInput + 5272 .syntax unified + 5273 .thumb + 5274 .thumb_func + ARM GAS /tmp/cc3heCqB.s page 164 + + + 5276 HAL_TIMEx_ConfigBreakInput: + 5277 .LVL380: + 5278 .LFB172: +2097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 5279 .loc 1 2097 1 is_stmt 1 view -0 + 5280 .cfi_startproc + 5281 @ args = 0, pretend = 0, frame = 0 + 5282 @ frame_needed = 0, uses_anonymous_args = 0 +2097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 5283 .loc 1 2097 1 is_stmt 0 view .LVU1523 + 5284 0000 0346 mov r3, r0 +2098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmporx; + 5285 .loc 1 2098 3 is_stmt 1 view .LVU1524 + 5286 .LVL381: +2099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t bkin_enable_mask; + 5287 .loc 1 2099 3 view .LVU1525 +2100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t bkin_polarity_mask; + 5288 .loc 1 2100 3 view .LVU1526 +2101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t bkin_enable_bitpos; + 5289 .loc 1 2101 3 view .LVU1527 +2102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t bkin_polarity_bitpos; + 5290 .loc 1 2102 3 view .LVU1528 +2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5291 .loc 1 2103 3 view .LVU1529 +2106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAKINPUT(BreakInput)); + 5292 .loc 1 2106 3 view .LVU1530 +2107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); + 5293 .loc 1 2107 3 view .LVU1531 +2108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); + 5294 .loc 1 2108 3 view .LVU1532 +2109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #if defined(DFSDM1_Channel0) + 5295 .loc 1 2109 3 view .LVU1533 +2111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 5296 .loc 1 2111 3 view .LVU1534 +2113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5297 .loc 1 2113 5 view .LVU1535 +2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5298 .loc 1 2120 3 view .LVU1536 +2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5299 .loc 1 2120 3 view .LVU1537 + 5300 0002 90F83C00 ldrb r0, [r0, #60] @ zero_extendqisi2 + 5301 .LVL382: +2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5302 .loc 1 2120 3 is_stmt 0 view .LVU1538 + 5303 0006 0128 cmp r0, #1 + 5304 0008 4AD0 beq .L405 +2097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 5305 .loc 1 2097 1 view .LVU1539 + 5306 000a F0B5 push {r4, r5, r6, r7, lr} + 5307 .LCFI46: + 5308 .cfi_def_cfa_offset 20 + 5309 .cfi_offset 4, -20 + 5310 .cfi_offset 5, -16 + 5311 .cfi_offset 6, -12 + 5312 .cfi_offset 7, -8 + 5313 .cfi_offset 14, -4 +2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + ARM GAS /tmp/cc3heCqB.s page 165 + + + 5314 .loc 1 2120 3 is_stmt 1 discriminator 2 view .LVU1540 + 5315 000c 0120 movs r0, #1 + 5316 000e 83F83C00 strb r0, [r3, #60] +2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5317 .loc 1 2120 3 discriminator 2 view .LVU1541 +2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 5318 .loc 1 2122 3 view .LVU1542 +2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 5319 .loc 1 2122 28 is_stmt 0 view .LVU1543 + 5320 0012 1068 ldr r0, [r2] +2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 5321 .loc 1 2122 3 view .LVU1544 + 5322 0014 0128 cmp r0, #1 + 5323 0016 08D0 beq .L406 + 5324 0018 0828 cmp r0, #8 + 5325 001a 12D1 bne .L407 +2136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** bkin_polarity_mask = 0U; + 5326 .loc 1 2136 26 view .LVU1545 + 5327 001c 0646 mov r6, r0 +2138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 5328 .loc 1 2138 28 view .LVU1546 + 5329 001e 4FF0000C mov ip, #0 +2137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** bkin_polarity_bitpos = 0U; + 5330 .loc 1 2137 26 view .LVU1547 + 5331 0022 E646 mov lr, ip +2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** bkin_enable_bitpos = TIM1_AF1_BKDF1BKE_Pos; + 5332 .loc 1 2135 24 view .LVU1548 + 5333 0024 4FF48075 mov r5, #256 + 5334 0028 05E0 b .L399 + 5335 .L406: +2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 5336 .loc 1 2122 3 view .LVU1549 + 5337 002a 0546 mov r5, r0 + 5338 002c 4FF0090C mov ip, #9 + 5339 0030 0026 movs r6, #0 + 5340 0032 4FF4007E mov lr, #512 + 5341 .L399: + 5342 .LVL383: +2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** { + 5343 .loc 1 2153 3 is_stmt 1 view .LVU1550 + 5344 0036 0129 cmp r1, #1 + 5345 0038 09D0 beq .L400 + 5346 003a 0229 cmp r1, #2 + 5347 003c 1DD0 beq .L401 + 5348 003e 0120 movs r0, #1 + 5349 0040 17E0 b .L402 + 5350 .LVL384: + 5351 .L407: +2148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 5352 .loc 1 2148 28 is_stmt 0 view .LVU1551 + 5353 0042 4FF0000C mov ip, #0 +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** bkin_polarity_bitpos = 0U; + 5354 .loc 1 2147 26 view .LVU1552 + 5355 0046 6646 mov r6, ip +2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** bkin_enable_bitpos = 0U; + 5356 .loc 1 2146 26 view .LVU1553 + 5357 0048 E646 mov lr, ip + ARM GAS /tmp/cc3heCqB.s page 166 + + +2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** bkin_polarity_mask = 0U; + 5358 .loc 1 2145 24 view .LVU1554 + 5359 004a 6546 mov r5, ip + 5360 004c F3E7 b .L399 + 5361 .LVL385: + 5362 .L400: +2158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5363 .loc 1 2158 7 is_stmt 1 view .LVU1555 +2158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5364 .loc 1 2158 20 is_stmt 0 view .LVU1556 + 5365 004e 1C68 ldr r4, [r3] +2158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5366 .loc 1 2158 14 view .LVU1557 + 5367 0050 276E ldr r7, [r4, #96] + 5368 .LVL386: +2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + 5369 .loc 1 2161 7 is_stmt 1 view .LVU1558 +2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5370 .loc 1 2162 7 view .LVU1559 +2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5371 .loc 1 2162 35 is_stmt 0 view .LVU1560 + 5372 0052 5168 ldr r1, [r2, #4] + 5373 .LVL387: +2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5374 .loc 1 2162 44 view .LVU1561 + 5375 0054 B140 lsls r1, r1, r6 + 5376 0056 7940 eors r1, r1, r7 + 5377 0058 2940 ands r1, r1, r5 +2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5378 .loc 1 2162 14 view .LVU1562 + 5379 005a 7940 eors r1, r1, r7 + 5380 .LVL388: +2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* DFSDM1_Channel0 */ + 5381 .loc 1 2166 7 is_stmt 1 view .LVU1563 +2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* DFSDM1_Channel0 */ + 5382 .loc 1 2166 10 is_stmt 0 view .LVU1564 + 5383 005c 0828 cmp r0, #8 + 5384 005e 06D0 beq .L403 +2169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + 5385 .loc 1 2169 9 is_stmt 1 view .LVU1565 + 5386 .LVL389: +2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5387 .loc 1 2170 9 view .LVU1566 +2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5388 .loc 1 2170 37 is_stmt 0 view .LVU1567 + 5389 0060 9268 ldr r2, [r2, #8] + 5390 .LVL390: +2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5391 .loc 1 2170 48 view .LVU1568 + 5392 0062 02FA0CF2 lsl r2, r2, ip + 5393 0066 4A40 eors r2, r2, r1 + 5394 0068 02EA0E02 and r2, r2, lr +2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5395 .loc 1 2170 16 view .LVU1569 + 5396 006c 5140 eors r1, r1, r2 + 5397 .LVL391: + 5398 .L403: + ARM GAS /tmp/cc3heCqB.s page 167 + + +2174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 5399 .loc 1 2174 7 is_stmt 1 view .LVU1570 +2174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 5400 .loc 1 2174 27 is_stmt 0 view .LVU1571 + 5401 006e 2166 str r1, [r4, #96] +2175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5402 .loc 1 2175 7 is_stmt 1 view .LVU1572 +2098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmporx; + 5403 .loc 1 2098 21 is_stmt 0 view .LVU1573 + 5404 0070 0020 movs r0, #0 + 5405 .LVL392: + 5406 .L402: +2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5407 .loc 1 2204 3 is_stmt 1 view .LVU1574 +2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5408 .loc 1 2204 3 view .LVU1575 + 5409 0072 0022 movs r2, #0 + 5410 0074 83F83C20 strb r2, [r3, #60] +2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5411 .loc 1 2204 3 view .LVU1576 +2206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5412 .loc 1 2206 3 view .LVU1577 +2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /*TIM_BREAK_INPUT_SUPPORT */ + 5413 .loc 1 2207 1 is_stmt 0 view .LVU1578 + 5414 0078 F0BD pop {r4, r5, r6, r7, pc} + 5415 .LVL393: + 5416 .L401: +2180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5417 .loc 1 2180 7 is_stmt 1 view .LVU1579 +2180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5418 .loc 1 2180 20 is_stmt 0 view .LVU1580 + 5419 007a 1C68 ldr r4, [r3] +2180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5420 .loc 1 2180 14 view .LVU1581 + 5421 007c 676E ldr r7, [r4, #100] + 5422 .LVL394: +2183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + 5423 .loc 1 2183 7 is_stmt 1 view .LVU1582 +2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5424 .loc 1 2184 7 view .LVU1583 +2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5425 .loc 1 2184 35 is_stmt 0 view .LVU1584 + 5426 007e 5168 ldr r1, [r2, #4] + 5427 .LVL395: +2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5428 .loc 1 2184 44 view .LVU1585 + 5429 0080 B140 lsls r1, r1, r6 + 5430 0082 7940 eors r1, r1, r7 + 5431 0084 2940 ands r1, r1, r5 +2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5432 .loc 1 2184 14 view .LVU1586 + 5433 0086 7940 eors r1, r1, r7 + 5434 .LVL396: +2188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* DFSDM1_Channel0 */ + 5435 .loc 1 2188 7 is_stmt 1 view .LVU1587 +2188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* DFSDM1_Channel0 */ + 5436 .loc 1 2188 10 is_stmt 0 view .LVU1588 + ARM GAS /tmp/cc3heCqB.s page 168 + + + 5437 0088 0828 cmp r0, #8 + 5438 008a 06D0 beq .L404 +2191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + 5439 .loc 1 2191 9 is_stmt 1 view .LVU1589 + 5440 .LVL397: +2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5441 .loc 1 2192 9 view .LVU1590 +2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5442 .loc 1 2192 37 is_stmt 0 view .LVU1591 + 5443 008c 9268 ldr r2, [r2, #8] + 5444 .LVL398: +2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5445 .loc 1 2192 48 view .LVU1592 + 5446 008e 02FA0CF2 lsl r2, r2, ip + 5447 0092 4A40 eors r2, r2, r1 + 5448 0094 02EA0E02 and r2, r2, lr +2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5449 .loc 1 2192 16 view .LVU1593 + 5450 0098 5140 eors r1, r1, r2 + 5451 .LVL399: + 5452 .L404: +2196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 5453 .loc 1 2196 7 is_stmt 1 view .LVU1594 +2196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** break; + 5454 .loc 1 2196 27 is_stmt 0 view .LVU1595 + 5455 009a 6166 str r1, [r4, #100] +2197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5456 .loc 1 2197 7 is_stmt 1 view .LVU1596 +2098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** uint32_t tmporx; + 5457 .loc 1 2098 21 is_stmt 0 view .LVU1597 + 5458 009c 0020 movs r0, #0 +2197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5459 .loc 1 2197 7 view .LVU1598 + 5460 009e E8E7 b .L402 + 5461 .LVL400: + 5462 .L405: + 5463 .LCFI47: + 5464 .cfi_def_cfa_offset 0 + 5465 .cfi_restore 4 + 5466 .cfi_restore 5 + 5467 .cfi_restore 6 + 5468 .cfi_restore 7 + 5469 .cfi_restore 14 +2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5470 .loc 1 2120 3 discriminator 1 view .LVU1599 + 5471 00a0 0220 movs r0, #2 +2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /*TIM_BREAK_INPUT_SUPPORT */ + 5472 .loc 1 2207 1 view .LVU1600 + 5473 00a2 7047 bx lr + 5474 .cfi_endproc + 5475 .LFE172: + 5477 .section .text.HAL_TIMEx_RemapConfig,"ax",%progbits + 5478 .align 1 + 5479 .global HAL_TIMEx_RemapConfig + 5480 .syntax unified + 5481 .thumb + 5482 .thumb_func + ARM GAS /tmp/cc3heCqB.s page 169 + + + 5484 HAL_TIMEx_RemapConfig: + 5485 .LVL401: + 5486 .LFB173: +2232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check parameters */ + 5487 .loc 1 2232 1 is_stmt 1 view -0 + 5488 .cfi_startproc + 5489 @ args = 0, pretend = 0, frame = 0 + 5490 @ frame_needed = 0, uses_anonymous_args = 0 + 5491 @ link register save eliminated. +2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_REMAP(Remap)); + 5492 .loc 1 2234 3 view .LVU1602 +2235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5493 .loc 1 2235 3 view .LVU1603 +2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5494 .loc 1 2237 3 view .LVU1604 +2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5495 .loc 1 2237 3 view .LVU1605 + 5496 0000 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 5497 0004 012B cmp r3, #1 + 5498 0006 0BD0 beq .L414 +2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5499 .loc 1 2237 3 discriminator 2 view .LVU1606 + 5500 0008 0123 movs r3, #1 + 5501 000a 80F83C30 strb r3, [r0, #60] +2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5502 .loc 1 2237 3 discriminator 2 view .LVU1607 +2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5503 .loc 1 2240 3 view .LVU1608 +2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5504 .loc 1 2240 7 is_stmt 0 view .LVU1609 + 5505 000e 0268 ldr r2, [r0] +2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5506 .loc 1 2240 22 view .LVU1610 + 5507 0010 1165 str r1, [r2, #80] +2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5508 .loc 1 2242 3 is_stmt 1 view .LVU1611 +2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5509 .loc 1 2242 15 is_stmt 0 view .LVU1612 + 5510 0012 80F83D30 strb r3, [r0, #61] +2244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5511 .loc 1 2244 3 is_stmt 1 view .LVU1613 +2244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5512 .loc 1 2244 3 view .LVU1614 + 5513 0016 0023 movs r3, #0 + 5514 0018 80F83C30 strb r3, [r0, #60] +2244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5515 .loc 1 2244 3 view .LVU1615 +2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5516 .loc 1 2246 3 view .LVU1616 +2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5517 .loc 1 2246 10 is_stmt 0 view .LVU1617 + 5518 001c 1846 mov r0, r3 + 5519 .LVL402: +2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5520 .loc 1 2246 10 view .LVU1618 + 5521 001e 7047 bx lr + 5522 .LVL403: + ARM GAS /tmp/cc3heCqB.s page 170 + + + 5523 .L414: +2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5524 .loc 1 2237 3 discriminator 1 view .LVU1619 + 5525 0020 0220 movs r0, #2 + 5526 .LVL404: +2247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5527 .loc 1 2247 1 view .LVU1620 + 5528 0022 7047 bx lr + 5529 .cfi_endproc + 5530 .LFE173: + 5532 .section .text.HAL_TIMEx_GroupChannel5,"ax",%progbits + 5533 .align 1 + 5534 .global HAL_TIMEx_GroupChannel5 + 5535 .syntax unified + 5536 .thumb + 5537 .thumb_func + 5539 HAL_TIMEx_GroupChannel5: + 5540 .LVL405: + 5541 .LFB174: +2261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check parameters */ + 5542 .loc 1 2261 1 is_stmt 1 view -0 + 5543 .cfi_startproc + 5544 @ args = 0, pretend = 0, frame = 0 + 5545 @ frame_needed = 0, uses_anonymous_args = 0 + 5546 @ link register save eliminated. +2263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** assert_param(IS_TIM_GROUPCH5(Channels)); + 5547 .loc 1 2263 3 view .LVU1622 +2264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5548 .loc 1 2264 3 view .LVU1623 +2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5549 .loc 1 2267 3 view .LVU1624 +2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5550 .loc 1 2267 3 view .LVU1625 + 5551 0000 90F83C30 ldrb r3, [r0, #60] @ zero_extendqisi2 + 5552 0004 012B cmp r3, #1 + 5553 0006 18D0 beq .L417 +2261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Check parameters */ + 5554 .loc 1 2261 1 is_stmt 0 view .LVU1626 + 5555 0008 10B4 push {r4} + 5556 .LCFI48: + 5557 .cfi_def_cfa_offset 4 + 5558 .cfi_offset 4, -4 +2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5559 .loc 1 2267 3 is_stmt 1 discriminator 2 view .LVU1627 + 5560 000a 0122 movs r2, #1 + 5561 000c 80F83C20 strb r2, [r0, #60] +2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5562 .loc 1 2267 3 discriminator 2 view .LVU1628 +2269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5563 .loc 1 2269 3 view .LVU1629 +2269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5564 .loc 1 2269 15 is_stmt 0 view .LVU1630 + 5565 0010 0223 movs r3, #2 + 5566 0012 80F83D30 strb r3, [r0, #61] +2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5567 .loc 1 2272 3 is_stmt 1 view .LVU1631 +2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + ARM GAS /tmp/cc3heCqB.s page 171 + + + 5568 .loc 1 2272 7 is_stmt 0 view .LVU1632 + 5569 0016 0468 ldr r4, [r0] +2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5570 .loc 1 2272 17 view .LVU1633 + 5571 0018 A36D ldr r3, [r4, #88] +2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5572 .loc 1 2272 24 view .LVU1634 + 5573 001a 23F06043 bic r3, r3, #-536870912 + 5574 001e A365 str r3, [r4, #88] +2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5575 .loc 1 2275 3 is_stmt 1 view .LVU1635 +2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5576 .loc 1 2275 7 is_stmt 0 view .LVU1636 + 5577 0020 0468 ldr r4, [r0] +2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5578 .loc 1 2275 17 view .LVU1637 + 5579 0022 A36D ldr r3, [r4, #88] +2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5580 .loc 1 2275 24 view .LVU1638 + 5581 0024 0B43 orrs r3, r3, r1 + 5582 0026 A365 str r3, [r4, #88] +2278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5583 .loc 1 2278 3 is_stmt 1 view .LVU1639 +2278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5584 .loc 1 2278 15 is_stmt 0 view .LVU1640 + 5585 0028 80F83D20 strb r2, [r0, #61] +2280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5586 .loc 1 2280 3 is_stmt 1 view .LVU1641 +2280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5587 .loc 1 2280 3 view .LVU1642 + 5588 002c 0023 movs r3, #0 + 5589 002e 80F83C30 strb r3, [r0, #60] +2280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5590 .loc 1 2280 3 view .LVU1643 +2282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5591 .loc 1 2282 3 view .LVU1644 +2282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5592 .loc 1 2282 10 is_stmt 0 view .LVU1645 + 5593 0032 1846 mov r0, r3 + 5594 .LVL406: +2283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5595 .loc 1 2283 1 view .LVU1646 + 5596 0034 5DF8044B ldr r4, [sp], #4 + 5597 .LCFI49: + 5598 .cfi_restore 4 + 5599 .cfi_def_cfa_offset 0 + 5600 0038 7047 bx lr + 5601 .LVL407: + 5602 .L417: +2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5603 .loc 1 2267 3 discriminator 1 view .LVU1647 + 5604 003a 0220 movs r0, #2 + 5605 .LVL408: +2283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5606 .loc 1 2283 1 view .LVU1648 + 5607 003c 7047 bx lr + 5608 .cfi_endproc + ARM GAS /tmp/cc3heCqB.s page 172 + + + 5609 .LFE174: + 5611 .section .text.HAL_TIMEx_CommutCallback,"ax",%progbits + 5612 .align 1 + 5613 .weak HAL_TIMEx_CommutCallback + 5614 .syntax unified + 5615 .thumb + 5616 .thumb_func + 5618 HAL_TIMEx_CommutCallback: + 5619 .LVL409: + 5620 .LFB175: +2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Prevent unused argument(s) compilation warning */ + 5621 .loc 1 2311 1 is_stmt 1 view -0 + 5622 .cfi_startproc + 5623 @ args = 0, pretend = 0, frame = 0 + 5624 @ frame_needed = 0, uses_anonymous_args = 0 + 5625 @ link register save eliminated. +2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5626 .loc 1 2313 3 view .LVU1650 +2318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 5627 .loc 1 2318 1 is_stmt 0 view .LVU1651 + 5628 0000 7047 bx lr + 5629 .cfi_endproc + 5630 .LFE175: + 5632 .section .text.TIMEx_DMACommutationCplt,"ax",%progbits + 5633 .align 1 + 5634 .global TIMEx_DMACommutationCplt + 5635 .syntax unified + 5636 .thumb + 5637 .thumb_func + 5639 TIMEx_DMACommutationCplt: + 5640 .LVL410: + 5641 .LFB181: +2432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 5642 .loc 1 2432 1 is_stmt 1 view -0 + 5643 .cfi_startproc + 5644 @ args = 0, pretend = 0, frame = 0 + 5645 @ frame_needed = 0, uses_anonymous_args = 0 +2432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 5646 .loc 1 2432 1 is_stmt 0 view .LVU1653 + 5647 0000 08B5 push {r3, lr} + 5648 .LCFI50: + 5649 .cfi_def_cfa_offset 8 + 5650 .cfi_offset 3, -8 + 5651 .cfi_offset 14, -4 +2433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5652 .loc 1 2433 3 is_stmt 1 view .LVU1654 +2433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5653 .loc 1 2433 22 is_stmt 0 view .LVU1655 + 5654 0002 806B ldr r0, [r0, #56] + 5655 .LVL411: +2436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5656 .loc 1 2436 3 is_stmt 1 view .LVU1656 +2436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5657 .loc 1 2436 15 is_stmt 0 view .LVU1657 + 5658 0004 0123 movs r3, #1 + 5659 0006 80F83D30 strb r3, [r0, #61] +2441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + ARM GAS /tmp/cc3heCqB.s page 173 + + + 5660 .loc 1 2441 3 is_stmt 1 view .LVU1658 + 5661 000a FFF7FEFF bl HAL_TIMEx_CommutCallback + 5662 .LVL412: +2443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5663 .loc 1 2443 1 is_stmt 0 view .LVU1659 + 5664 000e 08BD pop {r3, pc} + 5665 .cfi_endproc + 5666 .LFE181: + 5668 .section .text.HAL_TIMEx_CommutHalfCpltCallback,"ax",%progbits + 5669 .align 1 + 5670 .weak HAL_TIMEx_CommutHalfCpltCallback + 5671 .syntax unified + 5672 .thumb + 5673 .thumb_func + 5675 HAL_TIMEx_CommutHalfCpltCallback: + 5676 .LVL413: + 5677 .LFB176: +2325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Prevent unused argument(s) compilation warning */ + 5678 .loc 1 2325 1 is_stmt 1 view -0 + 5679 .cfi_startproc + 5680 @ args = 0, pretend = 0, frame = 0 + 5681 @ frame_needed = 0, uses_anonymous_args = 0 + 5682 @ link register save eliminated. +2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5683 .loc 1 2327 3 view .LVU1661 +2332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5684 .loc 1 2332 1 is_stmt 0 view .LVU1662 + 5685 0000 7047 bx lr + 5686 .cfi_endproc + 5687 .LFE176: + 5689 .section .text.TIMEx_DMACommutationHalfCplt,"ax",%progbits + 5690 .align 1 + 5691 .global TIMEx_DMACommutationHalfCplt + 5692 .syntax unified + 5693 .thumb + 5694 .thumb_func + 5696 TIMEx_DMACommutationHalfCplt: + 5697 .LVL414: + 5698 .LFB182: +2451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 5699 .loc 1 2451 1 is_stmt 1 view -0 + 5700 .cfi_startproc + 5701 @ args = 0, pretend = 0, frame = 0 + 5702 @ frame_needed = 0, uses_anonymous_args = 0 +2451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 5703 .loc 1 2451 1 is_stmt 0 view .LVU1664 + 5704 0000 08B5 push {r3, lr} + 5705 .LCFI51: + 5706 .cfi_def_cfa_offset 8 + 5707 .cfi_offset 3, -8 + 5708 .cfi_offset 14, -4 +2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5709 .loc 1 2452 3 is_stmt 1 view .LVU1665 +2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5710 .loc 1 2452 22 is_stmt 0 view .LVU1666 + 5711 0002 806B ldr r0, [r0, #56] + 5712 .LVL415: + ARM GAS /tmp/cc3heCqB.s page 174 + + +2455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5713 .loc 1 2455 3 is_stmt 1 view .LVU1667 +2455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5714 .loc 1 2455 15 is_stmt 0 view .LVU1668 + 5715 0004 0123 movs r3, #1 + 5716 0006 80F83D30 strb r3, [r0, #61] +2460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 5717 .loc 1 2460 3 is_stmt 1 view .LVU1669 + 5718 000a FFF7FEFF bl HAL_TIMEx_CommutHalfCpltCallback + 5719 .LVL416: +2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5720 .loc 1 2462 1 is_stmt 0 view .LVU1670 + 5721 000e 08BD pop {r3, pc} + 5722 .cfi_endproc + 5723 .LFE182: + 5725 .section .text.HAL_TIMEx_BreakCallback,"ax",%progbits + 5726 .align 1 + 5727 .weak HAL_TIMEx_BreakCallback + 5728 .syntax unified + 5729 .thumb + 5730 .thumb_func + 5732 HAL_TIMEx_BreakCallback: + 5733 .LVL417: + 5734 .LFB177: +2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Prevent unused argument(s) compilation warning */ + 5735 .loc 1 2340 1 is_stmt 1 view -0 + 5736 .cfi_startproc + 5737 @ args = 0, pretend = 0, frame = 0 + 5738 @ frame_needed = 0, uses_anonymous_args = 0 + 5739 @ link register save eliminated. +2342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5740 .loc 1 2342 3 view .LVU1672 +2347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5741 .loc 1 2347 1 is_stmt 0 view .LVU1673 + 5742 0000 7047 bx lr + 5743 .cfi_endproc + 5744 .LFE177: + 5746 .section .text.HAL_TIMEx_Break2Callback,"ax",%progbits + 5747 .align 1 + 5748 .weak HAL_TIMEx_Break2Callback + 5749 .syntax unified + 5750 .thumb + 5751 .thumb_func + 5753 HAL_TIMEx_Break2Callback: + 5754 .LVL418: + 5755 .LFB178: +2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /* Prevent unused argument(s) compilation warning */ + 5756 .loc 1 2355 1 is_stmt 1 view -0 + 5757 .cfi_startproc + 5758 @ args = 0, pretend = 0, frame = 0 + 5759 @ frame_needed = 0, uses_anonymous_args = 0 + 5760 @ link register save eliminated. +2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5761 .loc 1 2357 3 view .LVU1675 +2362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 5762 .loc 1 2362 1 is_stmt 0 view .LVU1676 + 5763 0000 7047 bx lr + ARM GAS /tmp/cc3heCqB.s page 175 + + + 5764 .cfi_endproc + 5765 .LFE178: + 5767 .section .text.HAL_TIMEx_HallSensor_GetState,"ax",%progbits + 5768 .align 1 + 5769 .global HAL_TIMEx_HallSensor_GetState + 5770 .syntax unified + 5771 .thumb + 5772 .thumb_func + 5774 HAL_TIMEx_HallSensor_GetState: + 5775 .LVL419: + 5776 .LFB179: +2388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** return htim->State; + 5777 .loc 1 2388 1 is_stmt 1 view -0 + 5778 .cfi_startproc + 5779 @ args = 0, pretend = 0, frame = 0 + 5780 @ frame_needed = 0, uses_anonymous_args = 0 + 5781 @ link register save eliminated. +2389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5782 .loc 1 2389 3 view .LVU1678 +2389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5783 .loc 1 2389 14 is_stmt 0 view .LVU1679 + 5784 0000 90F83D00 ldrb r0, [r0, #61] @ zero_extendqisi2 + 5785 .LVL420: +2390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5786 .loc 1 2390 1 view .LVU1680 + 5787 0004 7047 bx lr + 5788 .cfi_endproc + 5789 .LFE179: + 5791 .section .text.HAL_TIMEx_GetChannelNState,"ax",%progbits + 5792 .align 1 + 5793 .global HAL_TIMEx_GetChannelNState + 5794 .syntax unified + 5795 .thumb + 5796 .thumb_func + 5798 HAL_TIMEx_GetChannelNState: + 5799 .LVL421: + 5800 .LFB180: +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_state; + 5801 .loc 1 2403 1 is_stmt 1 view -0 + 5802 .cfi_startproc + 5803 @ args = 0, pretend = 0, frame = 0 + 5804 @ frame_needed = 0, uses_anonymous_args = 0 + 5805 @ link register save eliminated. +2404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5806 .loc 1 2404 3 view .LVU1682 +2407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5807 .loc 1 2407 3 view .LVU1683 +2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5808 .loc 1 2409 3 view .LVU1684 +2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5809 .loc 1 2409 19 is_stmt 0 view .LVU1685 + 5810 0000 19B9 cbnz r1, .L432 +2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5811 .loc 1 2409 19 discriminator 1 view .LVU1686 + 5812 0002 90F84400 ldrb r0, [r0, #68] @ zero_extendqisi2 + 5813 .LVL422: +2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + ARM GAS /tmp/cc3heCqB.s page 176 + + + 5814 .loc 1 2409 19 discriminator 1 view .LVU1687 + 5815 0006 C0B2 uxtb r0, r0 + 5816 0008 7047 bx lr + 5817 .LVL423: + 5818 .L432: +2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5819 .loc 1 2409 19 discriminator 2 view .LVU1688 + 5820 000a 0429 cmp r1, #4 + 5821 000c 05D0 beq .L436 +2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5822 .loc 1 2409 19 discriminator 5 view .LVU1689 + 5823 000e 0829 cmp r1, #8 + 5824 0010 07D0 beq .L437 +2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5825 .loc 1 2409 19 discriminator 8 view .LVU1690 + 5826 0012 90F84700 ldrb r0, [r0, #71] @ zero_extendqisi2 + 5827 .LVL424: +2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5828 .loc 1 2409 19 discriminator 8 view .LVU1691 + 5829 0016 C0B2 uxtb r0, r0 + 5830 .LVL425: +2411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** } + 5831 .loc 1 2411 3 is_stmt 1 view .LVU1692 +2412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** /** + 5832 .loc 1 2412 1 is_stmt 0 view .LVU1693 + 5833 0018 7047 bx lr + 5834 .LVL426: + 5835 .L436: +2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5836 .loc 1 2409 19 discriminator 4 view .LVU1694 + 5837 001a 90F84500 ldrb r0, [r0, #69] @ zero_extendqisi2 + 5838 .LVL427: +2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5839 .loc 1 2409 19 discriminator 4 view .LVU1695 + 5840 001e C0B2 uxtb r0, r0 + 5841 0020 7047 bx lr + 5842 .LVL428: + 5843 .L437: +2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5844 .loc 1 2409 19 discriminator 7 view .LVU1696 + 5845 0022 90F84600 ldrb r0, [r0, #70] @ zero_extendqisi2 + 5846 .LVL429: +2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c **** + 5847 .loc 1 2409 19 discriminator 7 view .LVU1697 + 5848 0026 C0B2 uxtb r0, r0 + 5849 0028 7047 bx lr + 5850 .cfi_endproc + 5851 .LFE180: + 5853 .text + 5854 .Letext0: + 5855 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 5856 .file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 5857 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + 5858 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 5859 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h" + 5860 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h" + 5861 .file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h" + ARM GAS /tmp/cc3heCqB.s page 177 + + + ARM GAS /tmp/cc3heCqB.s page 178 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_tim_ex.c + /tmp/cc3heCqB.s:20 .text.TIM_CCxNChannelCmd:00000000 $t + /tmp/cc3heCqB.s:25 .text.TIM_CCxNChannelCmd:00000000 TIM_CCxNChannelCmd + /tmp/cc3heCqB.s:63 .text.TIM_DMAErrorCCxN:00000000 $t + /tmp/cc3heCqB.s:68 .text.TIM_DMAErrorCCxN:00000000 TIM_DMAErrorCCxN + /tmp/cc3heCqB.s:148 .text.TIM_DMADelayPulseNCplt:00000000 $t + /tmp/cc3heCqB.s:153 .text.TIM_DMADelayPulseNCplt:00000000 TIM_DMADelayPulseNCplt + /tmp/cc3heCqB.s:252 .text.HAL_TIMEx_HallSensor_MspInit:00000000 $t + /tmp/cc3heCqB.s:258 .text.HAL_TIMEx_HallSensor_MspInit:00000000 HAL_TIMEx_HallSensor_MspInit + /tmp/cc3heCqB.s:273 .text.HAL_TIMEx_HallSensor_Init:00000000 $t + /tmp/cc3heCqB.s:279 .text.HAL_TIMEx_HallSensor_Init:00000000 HAL_TIMEx_HallSensor_Init + /tmp/cc3heCqB.s:496 .text.HAL_TIMEx_HallSensor_Init:000000d4 $d + /tmp/cc3heCqB.s:501 .text.HAL_TIMEx_HallSensor_MspDeInit:00000000 $t + /tmp/cc3heCqB.s:507 .text.HAL_TIMEx_HallSensor_MspDeInit:00000000 HAL_TIMEx_HallSensor_MspDeInit + /tmp/cc3heCqB.s:522 .text.HAL_TIMEx_HallSensor_DeInit:00000000 $t + /tmp/cc3heCqB.s:528 .text.HAL_TIMEx_HallSensor_DeInit:00000000 HAL_TIMEx_HallSensor_DeInit + /tmp/cc3heCqB.s:598 .text.HAL_TIMEx_HallSensor_Start:00000000 $t + /tmp/cc3heCqB.s:604 .text.HAL_TIMEx_HallSensor_Start:00000000 HAL_TIMEx_HallSensor_Start + /tmp/cc3heCqB.s:765 .text.HAL_TIMEx_HallSensor_Start:000000c0 $d + /tmp/cc3heCqB.s:771 .text.HAL_TIMEx_HallSensor_Stop:00000000 $t + /tmp/cc3heCqB.s:777 .text.HAL_TIMEx_HallSensor_Stop:00000000 HAL_TIMEx_HallSensor_Stop + /tmp/cc3heCqB.s:836 .text.HAL_TIMEx_HallSensor_Start_IT:00000000 $t + /tmp/cc3heCqB.s:842 .text.HAL_TIMEx_HallSensor_Start_IT:00000000 HAL_TIMEx_HallSensor_Start_IT + /tmp/cc3heCqB.s:1008 .text.HAL_TIMEx_HallSensor_Start_IT:000000cc $d + /tmp/cc3heCqB.s:1014 .text.HAL_TIMEx_HallSensor_Stop_IT:00000000 $t + /tmp/cc3heCqB.s:1020 .text.HAL_TIMEx_HallSensor_Stop_IT:00000000 HAL_TIMEx_HallSensor_Stop_IT + /tmp/cc3heCqB.s:1084 .text.HAL_TIMEx_HallSensor_Start_DMA:00000000 $t + /tmp/cc3heCqB.s:1090 .text.HAL_TIMEx_HallSensor_Start_DMA:00000000 HAL_TIMEx_HallSensor_Start_DMA + /tmp/cc3heCqB.s:1282 .text.HAL_TIMEx_HallSensor_Start_DMA:000000e8 $d + /tmp/cc3heCqB.s:1291 .text.HAL_TIMEx_HallSensor_Stop_DMA:00000000 $t + /tmp/cc3heCqB.s:1297 .text.HAL_TIMEx_HallSensor_Stop_DMA:00000000 HAL_TIMEx_HallSensor_Stop_DMA + /tmp/cc3heCqB.s:1362 .text.HAL_TIMEx_OCN_Start:00000000 $t + /tmp/cc3heCqB.s:1368 .text.HAL_TIMEx_OCN_Start:00000000 HAL_TIMEx_OCN_Start + /tmp/cc3heCqB.s:1559 .text.HAL_TIMEx_OCN_Start:000000f8 $d + /tmp/cc3heCqB.s:1565 .text.HAL_TIMEx_OCN_Stop:00000000 $t + /tmp/cc3heCqB.s:1571 .text.HAL_TIMEx_OCN_Stop:00000000 HAL_TIMEx_OCN_Stop + /tmp/cc3heCqB.s:1668 .text.HAL_TIMEx_OCN_Start_IT:00000000 $t + /tmp/cc3heCqB.s:1674 .text.HAL_TIMEx_OCN_Start_IT:00000000 HAL_TIMEx_OCN_Start_IT + /tmp/cc3heCqB.s:1908 .text.HAL_TIMEx_OCN_Start_IT:00000130 $d + /tmp/cc3heCqB.s:1914 .text.HAL_TIMEx_OCN_Stop_IT:00000000 $t + /tmp/cc3heCqB.s:1920 .text.HAL_TIMEx_OCN_Stop_IT:00000000 HAL_TIMEx_OCN_Stop_IT + /tmp/cc3heCqB.s:2086 .text.HAL_TIMEx_OCN_Start_DMA:00000000 $t + /tmp/cc3heCqB.s:2092 .text.HAL_TIMEx_OCN_Start_DMA:00000000 HAL_TIMEx_OCN_Start_DMA + /tmp/cc3heCqB.s:2515 .text.HAL_TIMEx_OCN_Start_DMA:00000218 $d + /tmp/cc3heCqB.s:2524 .text.HAL_TIMEx_OCN_Stop_DMA:00000000 $t + /tmp/cc3heCqB.s:2530 .text.HAL_TIMEx_OCN_Stop_DMA:00000000 HAL_TIMEx_OCN_Stop_DMA + /tmp/cc3heCqB.s:2694 .text.HAL_TIMEx_PWMN_Start:00000000 $t + /tmp/cc3heCqB.s:2700 .text.HAL_TIMEx_PWMN_Start:00000000 HAL_TIMEx_PWMN_Start + /tmp/cc3heCqB.s:2891 .text.HAL_TIMEx_PWMN_Start:000000f8 $d + /tmp/cc3heCqB.s:2897 .text.HAL_TIMEx_PWMN_Stop:00000000 $t + /tmp/cc3heCqB.s:2903 .text.HAL_TIMEx_PWMN_Stop:00000000 HAL_TIMEx_PWMN_Stop + /tmp/cc3heCqB.s:3000 .text.HAL_TIMEx_PWMN_Start_IT:00000000 $t + /tmp/cc3heCqB.s:3006 .text.HAL_TIMEx_PWMN_Start_IT:00000000 HAL_TIMEx_PWMN_Start_IT + /tmp/cc3heCqB.s:3240 .text.HAL_TIMEx_PWMN_Start_IT:00000130 $d + /tmp/cc3heCqB.s:3246 .text.HAL_TIMEx_PWMN_Stop_IT:00000000 $t + /tmp/cc3heCqB.s:3252 .text.HAL_TIMEx_PWMN_Stop_IT:00000000 HAL_TIMEx_PWMN_Stop_IT + ARM GAS /tmp/cc3heCqB.s page 179 + + + /tmp/cc3heCqB.s:3418 .text.HAL_TIMEx_PWMN_Start_DMA:00000000 $t + /tmp/cc3heCqB.s:3424 .text.HAL_TIMEx_PWMN_Start_DMA:00000000 HAL_TIMEx_PWMN_Start_DMA + /tmp/cc3heCqB.s:3847 .text.HAL_TIMEx_PWMN_Start_DMA:00000218 $d + /tmp/cc3heCqB.s:3856 .text.HAL_TIMEx_PWMN_Stop_DMA:00000000 $t + /tmp/cc3heCqB.s:3862 .text.HAL_TIMEx_PWMN_Stop_DMA:00000000 HAL_TIMEx_PWMN_Stop_DMA + /tmp/cc3heCqB.s:4026 .text.HAL_TIMEx_OnePulseN_Start:00000000 $t + /tmp/cc3heCqB.s:4032 .text.HAL_TIMEx_OnePulseN_Start:00000000 HAL_TIMEx_OnePulseN_Start + /tmp/cc3heCqB.s:4156 .text.HAL_TIMEx_OnePulseN_Stop:00000000 $t + /tmp/cc3heCqB.s:4162 .text.HAL_TIMEx_OnePulseN_Stop:00000000 HAL_TIMEx_OnePulseN_Stop + /tmp/cc3heCqB.s:4258 .text.HAL_TIMEx_OnePulseN_Start_IT:00000000 $t + /tmp/cc3heCqB.s:4264 .text.HAL_TIMEx_OnePulseN_Start_IT:00000000 HAL_TIMEx_OnePulseN_Start_IT + /tmp/cc3heCqB.s:4399 .text.HAL_TIMEx_OnePulseN_Stop_IT:00000000 $t + /tmp/cc3heCqB.s:4405 .text.HAL_TIMEx_OnePulseN_Stop_IT:00000000 HAL_TIMEx_OnePulseN_Stop_IT + /tmp/cc3heCqB.s:4511 .text.HAL_TIMEx_ConfigCommutEvent:00000000 $t + /tmp/cc3heCqB.s:4517 .text.HAL_TIMEx_ConfigCommutEvent:00000000 HAL_TIMEx_ConfigCommutEvent + /tmp/cc3heCqB.s:4641 .text.HAL_TIMEx_ConfigCommutEvent_IT:00000000 $t + /tmp/cc3heCqB.s:4647 .text.HAL_TIMEx_ConfigCommutEvent_IT:00000000 HAL_TIMEx_ConfigCommutEvent_IT + /tmp/cc3heCqB.s:4771 .text.HAL_TIMEx_ConfigCommutEvent_DMA:00000000 $t + /tmp/cc3heCqB.s:4777 .text.HAL_TIMEx_ConfigCommutEvent_DMA:00000000 HAL_TIMEx_ConfigCommutEvent_DMA + /tmp/cc3heCqB.s:4918 .text.HAL_TIMEx_ConfigCommutEvent_DMA:00000088 $d + /tmp/cc3heCqB.s:5639 .text.TIMEx_DMACommutationCplt:00000000 TIMEx_DMACommutationCplt + /tmp/cc3heCqB.s:5696 .text.TIMEx_DMACommutationHalfCplt:00000000 TIMEx_DMACommutationHalfCplt + /tmp/cc3heCqB.s:4925 .text.HAL_TIMEx_MasterConfigSynchronization:00000000 $t + /tmp/cc3heCqB.s:4931 .text.HAL_TIMEx_MasterConfigSynchronization:00000000 HAL_TIMEx_MasterConfigSynchronization + /tmp/cc3heCqB.s:5087 .text.HAL_TIMEx_MasterConfigSynchronization:00000098 $d + /tmp/cc3heCqB.s:5093 .text.HAL_TIMEx_ConfigBreakDeadTime:00000000 $t + /tmp/cc3heCqB.s:5099 .text.HAL_TIMEx_ConfigBreakDeadTime:00000000 HAL_TIMEx_ConfigBreakDeadTime + /tmp/cc3heCqB.s:5264 .text.HAL_TIMEx_ConfigBreakDeadTime:00000088 $d + /tmp/cc3heCqB.s:5270 .text.HAL_TIMEx_ConfigBreakInput:00000000 $t + /tmp/cc3heCqB.s:5276 .text.HAL_TIMEx_ConfigBreakInput:00000000 HAL_TIMEx_ConfigBreakInput + /tmp/cc3heCqB.s:5478 .text.HAL_TIMEx_RemapConfig:00000000 $t + /tmp/cc3heCqB.s:5484 .text.HAL_TIMEx_RemapConfig:00000000 HAL_TIMEx_RemapConfig + /tmp/cc3heCqB.s:5533 .text.HAL_TIMEx_GroupChannel5:00000000 $t + /tmp/cc3heCqB.s:5539 .text.HAL_TIMEx_GroupChannel5:00000000 HAL_TIMEx_GroupChannel5 + /tmp/cc3heCqB.s:5612 .text.HAL_TIMEx_CommutCallback:00000000 $t + /tmp/cc3heCqB.s:5618 .text.HAL_TIMEx_CommutCallback:00000000 HAL_TIMEx_CommutCallback + /tmp/cc3heCqB.s:5633 .text.TIMEx_DMACommutationCplt:00000000 $t + /tmp/cc3heCqB.s:5669 .text.HAL_TIMEx_CommutHalfCpltCallback:00000000 $t + /tmp/cc3heCqB.s:5675 .text.HAL_TIMEx_CommutHalfCpltCallback:00000000 HAL_TIMEx_CommutHalfCpltCallback + /tmp/cc3heCqB.s:5690 .text.TIMEx_DMACommutationHalfCplt:00000000 $t + /tmp/cc3heCqB.s:5726 .text.HAL_TIMEx_BreakCallback:00000000 $t + /tmp/cc3heCqB.s:5732 .text.HAL_TIMEx_BreakCallback:00000000 HAL_TIMEx_BreakCallback + /tmp/cc3heCqB.s:5747 .text.HAL_TIMEx_Break2Callback:00000000 $t + /tmp/cc3heCqB.s:5753 .text.HAL_TIMEx_Break2Callback:00000000 HAL_TIMEx_Break2Callback + /tmp/cc3heCqB.s:5768 .text.HAL_TIMEx_HallSensor_GetState:00000000 $t + /tmp/cc3heCqB.s:5774 .text.HAL_TIMEx_HallSensor_GetState:00000000 HAL_TIMEx_HallSensor_GetState + /tmp/cc3heCqB.s:5792 .text.HAL_TIMEx_GetChannelNState:00000000 $t + /tmp/cc3heCqB.s:5798 .text.HAL_TIMEx_GetChannelNState:00000000 HAL_TIMEx_GetChannelNState + +UNDEFINED SYMBOLS +HAL_TIM_ErrorCallback +HAL_TIM_PWM_PulseFinishedCallback +TIM_Base_SetConfig +TIM_TI1_SetConfig +TIM_OC2_SetConfig +TIM_CCxChannelCmd +HAL_DMA_Start_IT + ARM GAS /tmp/cc3heCqB.s page 180 + + +TIM_DMACaptureCplt +TIM_DMACaptureHalfCplt +TIM_DMAError +HAL_DMA_Abort_IT +TIM_DMADelayPulseHalfCplt diff --git a/build/stm32f7xx_hal_tim_ex.o b/build/stm32f7xx_hal_tim_ex.o new file mode 100644 index 0000000000000000000000000000000000000000..cffa83ddedf5533b864bc92417fcb36429340370 GIT binary patch literal 67256 zcmeFa33yf2+4jHpnKBSaAWUL_L&6XgG68}bAQNGRkOW0RAwVEu3`sz&6OOgoT2!>w zp<)&5P^(gH)jHLAXe~IjS|_x&SgS24Dy>@o_r2D=&)MfBV2Ag6ukU|-?kns3_VcW@ zo;449?~{Gbm^7o>bzR3hTqoa&OOCVoQ{xjJZIJIYIEx&2Po_J2PbeefAMWSD6?yMv z1cQr%D=sL@t_&`2nVfa^IV+c}IJ=_Dj_dK+b;lp@nYANY{pF|s{L;zGJ1Oe{7oX?s zuPWNNJAgAc@0|UUivGGgr1R>ccXub+=x%KE>0sm0X6NvII~l*KXpgZ)&0maWQqgW> zk(#%Srn=~j-7S-y{Kg$Ecb|Vpx9U*!=KbS~oWtks2*ASlqCwSj_J_JKmp^R^<`y?a zn|PkvbZK+mo{Zq74Ln=d)TNSVbxoCfHU;YzLD!VGrzLo)Ijh`LX3j2dI&^xMGEWzR z&KVNEEOJ>(o_lG^WueQ0mwnU}xYWJbOQFu#pf%d9fnAnqO3^v{C%{dFtAd*ZH@+yp zI`xj02R7|5En@Dj+wDeMCh!09pI@@xL)C%2O$ZZgI%GxphuwR0uSnf_$cnNLt17xz z1b6mp%H87z`YlpRM3I7n6yPSpRl!Yy8xL3NWIaG@oA*!1dV2fj{S%|lacRXNI|3hXT6}3mFR?qg5&EuROYNlc2@89cYqR-?Xx6?tpIm6wZZnS=v*I%lN;x)2l#n5TL zU&7CROP8z|GVS+E2Q?jDT~a-|c+mdy)5)J^`czd>DA%oy%^RyK_c@hyOY@ovWA#w2dZ9*$5w zl&BsGVx@JWV|Rsyr|w7{-gU>8{gY$qKe(Ht-pkF;AyvnuJ9dZi!#h&*Q_LJXx#)Jx z!knpYHLNcB(eCdzrFB}jj;UFUE{<1?)p6)YT`^h@Hdc>cmAlWWI38s_*c>1vJ1YK=;@#zbFhOzE^Wewxr4KTc?kZD@@Qv_`gCBb1NU%+K86 zKMx$oLO)9dv4u>s2g?i%l7URT5$ zvV-+9Iclv8+To0xxNr6CZnSb2^^>AMTrmXo^}`i|QD6LIeT_qXZPk1~TJ!y;B`+*m zzMFBXqi?V1i#Ttu=z}=?WSmmO*=6Fqd#~yjF=nAZclXUd-F@TBo88Bm+1R z`vm)keV7&ehn?%~{1h5K8ufTI`ukkl-%U%F+5E=Z^S|lgcPIDoeJuSZlftiUKi}s- z^RUr8)}gomA=ca9i1qeYP_o~lRNh?o^%}$d#DCLDU#~G-PrqJc?7rgbHO7g4y~gmG z^#AoWhO6X7)ffLFG-M0zEIQw&5OYj~-e(p|t2Z7gz19tx9Uhj%9 ze#aw}yH2}EH@33IcS=q)u*(_pELJwVhBIYnc*)Mt5GU7OBPH%aJKhud*LIv7;mP*} z#y!B4ZCRb+rAYIuN;|?=+WehI|Dt1Q&A!E4h1)akYyXuR_+?TJFgLVdujuU=ZT;`m z$}e{Zap$Piaq~y*$hymoo{jV9@ZgT&FQ?s^H9U1^PSe(==$;m5>mr`HmDerm+f?3E zzQ=XT&Do$mA)TdHRxCQC=^0!zL<7&*vwcqOGm9K!^Mw7O=`E9shQGPTS9Zm|mY+M9CYHXUlhXfo=dVoZ{kv7ve$+i| z(vFt9g4J#=?iEG@_#7V%G}Sb1X&NwVz|31JaQ_VV1f%;}oS9Aem28i$V9la_O}(dV zH+SmJs_3(0>&K^-omG*&!})mAqO&S+C280N+z5RN*iv&=MG)b(6rEKO+Bta7rqH*V z231~+yIf}@MO$Yr_qR-D3-LPN3Ats+Uy*xw>5ihi0@W_=Se6z&+myGjtnK`!U}YZm zx>F3DC8<`fOKqm!sheWBsq*|4lw0!7Z?1gLsmyBXIx$GzI>V@!_SbIJxS!@UpGPHA+{136904;r=sVc#|FYwN5Fu4q|b zfu`<_ywmF#sc*HdUmK<`d!lW1b2m8Dbp7hQJ&P)@Z{%4QkbS|6X-5%Tr)6^L-J4d@ z{&;h5IrV|gG%b^H*W78De8|1_YPn@{XgKb#3{TN@CH;9lN%A_fWpX&`I04f=L++ay zj+0Ri>78!=4r|W?sVVouD-cSV76t+-OCx|AIfKeTczg=|!Y2fQ)bL5hFZJ#;#|fr{ zpejCOEX)Ld)CK3G4>=p>q1E^Z^8+UT43m*ixOq*xlhQYMotyR<^r@A#PVjoS`^gNG z=cH{$62TihIh0yc4*zYQoSHTp;et1Maz@&{U74aMXQfut-c6p|(@Eck@&<2qgBK%W zN>lK@VA`E143aH&g7*i#bRm~G!3R7!ls1^r9`xkYv}sKDAy3XotwS;odtz4Vq{)zf z>B&9Qjz${6M?AT2+7Fn`M?E32%31YJ@NrKboLW;?=>(tfY)@Xzbv#o?M#Nh4QaFxh$N)_cxwABXu^scX(n=+UKmDot|8umPPZ=d-A-r%b1-PJb6KCc{OVPMNeJ? zxx@*+8ztVwpm6gavsXK3pors!H<~H)qxNq zgcvL9Qe*8y;fpP=2I-fbp!15QlEK0EBE>VwiV}P4x;Zii3^LfLL9a?+C@ z&`m*JyN8M(1h+6_KMGjQ6ll8jO({rw5GR@Upnxews(L50A8I3Il*CZxb`&Ay2#Kkg zbugK7l*Ek8w@`$X@e;E#hcoaLi9InLqWh#w3m%VT!c41MPRi`G3S>QV8S;}dMqqJVU~`Un2|XM&6jeb#H`F$DK3%NGjlHkFPGTY32s8mr>qG6 zhIwGp-7-@CoOS{8u$+nhrK>kEevCRx`9NYQ^Fo&8ZxU0T;CNQkC&4 z?HHt%mW6JZ(%n^>PTG-3D<#{LLutF2rCy$#npQ|teLOiM?Pi)g#FMkq-e9#I>d8IR zUZnm0p4>O>9*p*sfu5X`b_a_%$djXK*Rf!Eo;*11541nTlk=VQ(dbMm!`$FiEDVd# z%g$6OBVG4$h#4>7!^zl&)^#%;#(5y4615!6s6m8~lYTebXOtUkf>($Uy!c1D?lTZG zh9iKJQGgFO;{sR-IO#K4i1BXlCdOePFHWWF{*!SoMy)v+-7uisj8vq9IFGQRCcDAc z7>9wpI5S;$8q8+A2cvFA5akbKbDU02qOfHa@llD{kFL8(MH*z$M zvqegyJJe1WrD>clQkJp(S(u1PKbU+NjpXvbVB`co}R_F`IZ|z76!v5 z&~(d6Elj%rCz;QqU!@j%-8A!7rZHM#D03I;DRr#G)Xb%5h}76fcY@9IE)7<}P?*-b zWu#W5Jx{Y4_(-jancag7q*lkwK82B<>dgrlM^~crrcMuDMLUe%*FBq6HaIQfx_^h< zlOL!CX1%ZbEUP!4e!Y;s_3P`7!g{TO2nf-L&gG zD2{=122|3_%V{>DDri>1xt}1V9F7!t6|;4?hrJMPU;%RE{ywcY8~Jf49)*jt&c1|V zkXsXI$N7L(%unu(vdY9>hI412W~|j4)5g;3KcU?ZXRY33t(G8#A~<994?e58?ssYB z64V;#pnE%$n47C(W-m!Qf@YhcZG^LCw^*~6K(QGv4_R}5i-Cm4c}=XRGko^8A%OdS z%-$JkCA9Z6w2#ACduLjEA40JQ&e(Hlbg=s-WOs2|e=~ zG4pk4GijcS{!bWnh+BnT?v|)2sA5mL6=4oF`6)>|l1=H>AZR`9=OqPYRoS3I$W{&2dmYzdU_vbz%gWn2-2%v~e<%_<8Dd z*%<2fMytC8J{vc{#&rnlUW(G#j1;7rGVX--*Kj$n(7P~oERFmf=YON}I*y^D)H+71 zN83(=8`z&YEJ^LfO9t-dw^4Z+Lyk%{!}C2TeoN(>_;5#C<*CTiM!13dnANbL-E+m56&)skCpL*lqy!# zXlO^k<>b)dUsH}{2wsG*gB!>iaQCK|obQH$yCI~q1O*!Eu4F1V_)^&l&r>kHxa}Cg zwkB^#nZZ4c@gWrN!wt-3Rs6`NG87|}m&pU~VWr(2;v;WMtl;AUs4(1ux?KoPvw_T z{2dPVKV^=N^4Z@2b#YfJyL&}DDrFMwpA7AKIBWl?l({r@4HVy_(%3&b#mwO^LGc?n z*dNB>7)Y|8!oG85%zhxHg7#-aJDuIzg22 zBk>M!9@MYH&&}rkrm<@e-WP$7wbn zQ79gu@@E`ZXIkZlP`nQ}Y?aFPu_@b}w2y)xyTd;%`qY$Zv=e1VNGxbEEBt(9(yjLu zv=!m{qb=P_V+E~`Ok_bTp&bur3tAsBOL;34tKe)wkFf>45sDk&h9NJe!cT)ORXEq> z#C#MnALH1FdA@vn1L5w44foWZUWMmH%9xM0pnV0-<|8jMn+-n*N%exW`50pJaV8X} zQE4iCsI9SWP+Uu;sqkS|`63k0QMnGb+yd{VxV&5#7z}Y-a2%ApO7da0x_ggvrOb9P$v^$`!+wC?#5iAc zh!cHYUWukKL7xs|LtSog+>db2!&`wKgL*si;ckmn#Yds>?1yha`#hYjijP7w%mmce zaq{780Y46z=2;KLIx35~@_Z691^gZqm%&B7St)4>`h+9%8edL0L~cO@_Xs9xrowAN zrlULu?K5yTC)b2bM{y3p%mAg$$+b2omqB?koUQ7uHYdM;;%>NTmFlyT?u@G8)v0@$ zFGCv;{C&i8FOOyDw9rwknyh}9WZ`UvP76&nRRcu;cFc`lqC zl}*9X4JhcXxSIPOoX!0ToBP^9iZ6XoZW7%7w^^x=Zq?+-SWzj>=0r z#5vHY9O@p6KH%o~DuLtiX5_#f!}d3wA}46J&M!gxG@Px3oS@k{509b*bY_D)z!q&4 z6irl`@i@>H?II|?4R@gNxC%Qg_i4S)@xBt;<#5)1Yru^6 z??dq|I9s-MTeg0Axc>n6731*-oC`+#(w>G4Pe(lW@3FK;2h4@QT4-0o4db-J1@~_V zfiCG5*&Rn7I<{F8G0Z1nr{uot#)tXm@cRzUKEZ)vs_b3YY>)4R_BJ>>dfs*CGQ=xT z{Dw-iroHPnHX#1+!AK9zmh(M(OLPSk%cwM4kH5HPueSw?%~YCQ#`{)z9~9f+hOvmu z|LsU9mj7ZWx&nGGW++Zz13v38qIgBYHXQ1HqbqX%q_0Rbp#CfDxxG2eO_82-%}%w) z5ZqydGYzh-iC0Uo)D%Lbi+q+|gry>ccb|?~y2v$kUJq>zoGtQZTjY&Uv{Gq`e6cOv z?NHoIrP*y=VwG<|@iLXB9xk=Yu2=_C;OuT|i&d6FaRgj+9`cfqWwV)jpM`JrWw`>u zmLt5IjaIjXZ*|SC@j__7NlRWgiB+-Le?G>+RO++z6fE6LOHafsmAdBY`q$7t4QC5K z!4`fm6n~-86n>)3ef}`q(SfstFSE*Hp_oIZDSWwAo(IJyD$Q22!Yc2E;&!;`tWF9) z#N`76ccg1?lLZijHx%|FxAuO=NY`xG%w3d?EZu;lpgEW;ZO{R(nYIu#9{~|`Z+wI> z?On)(y9mLDo9?vNTz`e~;R9zzGAqfu)0Xd^$DVXy+{ViYnTw!qAnMt;&@{^FP`1Ji z?}b)zFKnX!tB`lX9rhBfe5W^`uLLfxABHaN@b2X^$Oqak&>nJzq3N8x7#gn|U9CIH z8FmR&JD}RDU>Dar(dQVSxjoM)1}JT-0KBfCt+jyp8QA;LoqA_|v^UYqT9>4I?KBfGc=klGc`R;@TSdmOTo1_kZF z-zw5&*eLKYGUQI^(gl7tE!xP)M-)DM=!%n6o^(?p$P5Ey%BIO16UoYUgWXIv6ry`3 z3c?Kc;ECg8_i~42Flx`RDL^k@s>*q9*PWWpAbkcQNFgHiEpR7hc$puTQEChvlBk@T zZPon>kON!HVHw@s9&TCs_bN<;L-F)9RsjKIHYY(5`8nIT|7c&e1*~pB2a^$*9Ei|y zlQwkpTW7gw(_$20&;@7Vd3gH86-X>MF}o&bo|!yEacq>qiNU63Clp~wqHluV&_qAQ z^pY6n<%$)X9}9|B8kUh1bhxU;G^(oLFcsA5P@LF-;o-Q>90GmYNq1tG{MW|9=mgtM z1g#}vLG54z&otBLGge`(W{N;kEgT7da5)(}<%>N1d zUh*C>h?oU}{luSF%GmwWo4|%O!J9HW2E2*RT5zcKCJux18;7Wa%}-mfy81%$9;7s!NKHs&JH^IT1 z*b3+Orff~m!C5EAV(2hQ5HZu5Bq(2Gy@{=G#|Mvg>V`sER=Q_s{oR(6Y^-lC8r{A>{7Qvyk#2UC1=X58!4t^9`;ox^V zKnD}V`EW546uxcz<`7pJKbfGg6%How89R=^Sp}Ty%$)^nwWs)u9q|w+#zUMK^TtU$ z#4+&@$8;WIK|BNt96S8OWD~TUl*!HZ9G@MJeo&$EiL=aUEpd+35{!JH{tPc1?Qp0O zf^q%bi!u%PDl7o;zdL#&Iy(u;xdp?5$T8}58Dta=Y9be|i?c2x(&fv~`?WZO%*rzu z$_!7rE;TafT59s)5R2e!mhBJF<;%}ZYzVAiE(9y|DT0F)q6F^H&H~~E4#pY- zjE2iOP@r`VtTF_rJ6I)-g3CKtgf3tH%~)r^QnUz#aatMC|hA zn;JO z@jo%t{mU;a`>pF6DH}ZKS{hja2b;tyxM}~TO_+aZW50H%3g&5V4czqq5u57gLo~Ku&BL(dsEaEw!Z>hZ3W|S=i+Sk9 z?2Ix0JajPjkGKMDZJH>qF>Ph*HLf(35zj0$dKMg7lHi1vut-5pH#)mRxx}7lkXxk( zIvkv+F!d5!%xN8Qxz!R|;SN6aZbAsmtpwxxr(Vii;e1oCog>SPvId{AV*t)<0qco# z;1Z&7vNX$y;i>jKL~{A$j)r73oQFuJPJQy>+tDxxYBV_n9tRkYIRwr63q{$+OIU!R z#la~6TNNS}PkWJgyjq6z4u7dQMwxq(V~e>bIS!~N*%7{?R1ES}rJ`AXsVLic2QO7D zo=O#u_y0ht0;+rRJbRu6BptbsF{X&K%&Fm+aXViEbEpB-cM#QAX05{&F(%00lb%y`csR+`fj3EJ@Iobm<6 zdk*pKByY+#9bduh2)CJ<8_!8XDRI*XQJdhDTboD?4PIom`1BpzmDRvuP|~CgUK>w8 zq1QTQ(`JjcARc@{Joo~iX`Bv)D}uvlBSymooi_K{c-(}!#otC8%V@7GAnE7^8KooE znA3WK;i1K6($O6<`VYZy{#J;`^Hp=Y0v@FQd;>u`&l_&{!S8^%VwIG+WF z{u2*g8&996e8&Ks+hQ$<2VW2mp45K^BX|KE`VUb8XZlY(?g9JHBM5t-HiDNqm>ZOn zu;r{LHd!rUCzpES600R1G^h2%!{)SxV1fr}SKQh(0p<`kwYkLER!i8_<`S1#En!oe zOV}i0P3l4wfn#lOvqN*X*uJZC<7cV@VX*VZ$5&Mgy8x<%c+Z^H6Q5WuVZH(bb91Mi_t)wWlqi3=1Qw29=2NI z5p!BY(Ch)nNYr@FA*{{0gta**ZgcL#&{{(sCWuY&V$Cq3ErP#h4uf_A9EKl0V@CjI zUb*>=37n_KJaxiq=jaC*|oVqzm`A^2XhIrSU&LJ{P ziZukEe)=O(KFoR(%$wgEk<9_M6M|zH*3Srq<+%;veR5J80EfOo(7vzdc<~O>bGXEH zHt(iGk4hjIq>~!#YSeQG8zNx_^S2UWe^o0nNGEB)cI@C(hps@dXCQOLNUJ5-i~O}o z`9Y1O`>dKQQx{(^`>YE)2)Ua;%3|cL{l)ql~Q3>|Q1u&ryoD4C+5_XBM zi7(Oh4@3Ki3Gnr@Uxs@4df7)Me7)>D&VRk^PeVm^wn0sYUfU}MN!t1ZY%IjY#ehBM zBA9UaRz(I$vJekiWjyB)ERE|NL+moAbBMR${2L$2*5WZZ>u^*+gZ(67?ahtbtK9`H z;~IOo2IZv~#Mto!&Yp*Z0fI4o+bBq}BLins;c#Iax4$6ft&<+$XcMaD2%y@YGQw;2 z^bKH_J;i722;dCOVk&rsJx`5!>crPX43bpAehb`PcGk$fO*HfU7zRnQ;5auyd6)61 zB_4$H)duUzMyth{?_kEL!e*FJ9=4~C0F07!wPd$Xwqk1I!E58eldLn-^~O$3Jh*RJ zsDYpF=!f&6a9EIu!{E%Fuz1`9-U+Kf*v_iWSMdyzRBZtp%QW3n2e9C)cm_$b;5a{k z@)qM!OR(~N6@NcO8!f47n6W8vsA5L>nLWJ+V3dPZd^~t zEk1q6fhs;8_kb18`=Xsy{9(}RvdZ2%t@ov8Z)IT2M4(Ky7WkG5@7_ZZFW{e$p4?&2 zi^!MlIX*i-dP0qq2}VVO5x=%tf<~Yvp0`?pX3bR7$@jkCrNbJZ6E}WL-1wZh@ngJ< z`Wo_7bLC1qyd1a30Fg5)k9iiRL-LfF;=zu}gH_3cU5W?$G>;c898NAgKDRJ^z?>p& z9vdvo%>tgXo_X+A5|2kLSU=|YSHpip@mj^r;(4NH$Kw|1w~Ai)8zc`FCx~A8v%W(1 z!bKF0z0iMrUEj7g{x|CT4*aJ}(A)(MxSw_Fim%U^FVOMUMpbL`hQ`*m!n*pIqe`mB zZrr$VO8Jb1R$Exty2L45-_}~Vs(EqY@+C_O8(LS7T(fpf<`xzIs&2GG?c#Vb#L+=G6-u zHx?}6SZHfsig)1^G;ts*)DZ{=MKGr5AQ~%68ACASbyF$Ps-a(MWN)JG|V&a5xfN9t~$h2uBLbypvhpNg$Mv*o_BH zESOdhPtGR~A%1<8?e_~-_ zVX=x<6i$cE9mFQT=Zu1I79^Z@D?k-w1Q(-g1z*N{g@XwVe%pa6cCTx@T~SZ3=J0P2 zA$J)*g7feZo)+xlqNA0BJLaU=Enr(^M-!5|A1}OQ6BK5L2bz=d2Vk*n&f(}pW~9`N zFDx7tiALG0IcCuJQ@p$crZGeO2=OD#kH|EZJAE4JV;0Za3&Q;ot!orQA%+bGVB~lh zNe`x#qGpy9pk@X{O&w9$KN^T6Wc)*Ayr@s4G*X;g4ZV=NVwScbA<{*`|Dv?TsMy(& zg8xGWUc>?qVu2S%S>R|ifCo;#Dd$P$-4=NMzgXgTlS@3E?aSepXB#v%alCs37lwH{nx{qPw3w&G;Yv1NG#o)YyUU;%J^$b86Tyx1 zI`0e_!P;rjAV#qp9LB0y84Yk5jL*Y&g)|`83rda;7+A!sJMl_dW8!j zuKI65xPYZ7HHFD2Wnm~s3L+Ct+y8qdGrgS#1L)B}xWJ5(RGUg_sgXj{OqwAp;cc`G znS!JluLd6>qu_@bRCXwJnbvuoX#h2{Kjok&4NMw1+b}FxNfUaZOdSVKhpI!WoKhxo zG}$a2)>)R4)`rKGN@4a_)NX~bU%|Q;?DJyBcHw$g27H$g6q&P^E;*4;37P=pjcO#rgHPQDv zKtrKrXPKr#rOb=ccqVgs5>NYu!!Uq4!Xl8+tGISV<{|8ydC{b`{M~qN%`maEd?_Me z7BRW9<33{=@>>=jh3sb-Pa9$s5e;_%5F(7qvs3*l>LVOpRcLs#FB*+`F9nM+_ekS- zYPU;c?CCscv8hUDym|1fWYJ1YXPIw?z1L6JbO9E~R8+_;iz*-c$vl&3)WM}^ByFcPv|A0Y1>%SmspfVT5|*hAPhpRWL%8XM`#kVN!ub z^fp#GGowZzV}rDDvz3DV-2b44#;}I^qw!%3J$L&VoU36wSooh<8)o`XN)T;ufbM?f z8S{dfoORxIuxSonhV-(6IR(L9{3{4#Buw0UQ#1%P2C%NMoePoWzNS$-bngxd6blm* z$`tGGC!mx23}vz7Z%EL^MnJ}aM!?(-BjDLoo7Mlv)`>4v?Ekat#5HNE+<$kSFjMA# zvrbee41Y7G|IPKdvvneq-4vs3v2UH|chFU0CRd3G(d1R)BUQ}*KURr{(qn7d*Q>6(dEcrZc@e4a%Dw_Op`t$aZ z-qmv0rq*15Z%O(uvp!3<&W+oDTDZteGi@gp@c38(ar-7C*wmqb+q-sBzj?jp!`6RN z#3ji^JiD8Et74y^a*BX_rf3U8AO5`rm0bb>D+7wN_%;?(ae3hbkjWMZU~ym z+`SA(ntO#a(6nKs&%1yb3^Uk_OlFBU_jm)u-fqh^y#T}4?73a80|&Tb4dYHTZ>7*| z>^4|l*xr8}tXxe{KQWnhgEib+7exc%grWIYma!*_Xb)S^mRLcvY(e`D;??EBKZ=xl zWU3i8hH*9Ci)6}dZ-(Y3X6i&{DmQuaaz~aOOoL3Om^lofp5fpjW@rVQG1akdBEde~ zhI4qaZi5(G!EV#SIl19}Bg1_M;98)qG!h)R489Fe4Gi}kh&%?n7ML5hxbRMiflQ7bjxrM9_m;b_WAPVc-P%sa+W^6maFd#JVbFeFdK zC`Z_$q;+b`fs9;|^pN9VMy@}Qk?jZac!3_-;clqu4$pGlHh$P);MNNpk6qF=!-gOB z!hmPEvS$qP=9{VBgKB0HIt9w>Zi_}ga>jBt5(%Du4!A_y0EHo>YCu4!4{ zUf22 z>{(-;ok|pRal?|8PG#lH+EI=#rMk82TbGzjEcCK#Q&SZ@)WJH2hLY*}Vk(qnClm$ezQE2mGY^2PVn`^>f$Q}HlygsP&VwXtEPsnE)` zYnC-H_wr@*B}fsK7SD^%md#AuYjR_|N---rmX}4RqN={uXU)^IJ)H9O?Q3frSFLSW zTGMJ^s;@ZqIJVP=ta!3pcz|cDwT-JATAa4#=aLG3zZ&eDWNRlGJ^eW#)fM!+A$SDCDiC79P{FI#4k zpIS9zlF44@-B1%GYboC5{`ROldCiih*0pPzzhNdj6N(+6Vs33+eQbhd{Hc}27 z8df3sxG`T2y{_ub+_N;|Idyj&D)Ka?=rma~i`KPc23kFJ&C%S=;rznkYw~-O#AYjwkM0IWf=1y6!Aa!RTXaTQ_1I#UgAcA>Rt% zG%a1-z#wg_m&E#k>f68WCG?#c7?Lv@H#DxoR5WWUW|nwO+HvQfhU{XcGMkExwLI6- zr19d-h_(ePH_q|}HjNgW4&!~+H_EXtCFCV(g6XtG+-`6hvq^f(xmV$d+SYinY;ke4{Hv+7OwO*X#$jR&sk_cT5Off+N?QTEAx_0H<2aUM4Db#-Mk8;my@Q>4vos;5@ZjTcGXfdoa?6+`)0DbnU%GUjTT#BV6D~!^{-|A zww_&C;xkcMiHn2Ia;6PCdk1>&LernBo7XhAH8n1cO&q2Jnsq3)FYmAtvW)Tac{!Op zYi_i%cx=>uhcH@FR5Gf#sOZS($kj_)){kF;b*XXV$kk&Zw>Pa{y%<~u{j!z~V@575 zK7t~4yzL|LHN^24YD=MLXkF4Y9$!%0Ft%~z>cf|{6fA9tj$Dqvr6)DCE*n`A9XT7) zvZYvpMz-1gN*m;5>(`jQOHAjh4d1Zvt`uf8u36sRWVYBPrkc&-;_oFhi_rjfLz%eT zahu?622F2?N%8tmN|DzrxDcwW9nFt1PMel6%wSj$V{5!OzSvmCvez4IaIempjA=2m z#38Vm4{NY%=YHFi2Hx@MV^-2U7~k0*q>f+#U6NZ9)=c@*rRctGzVPPqLd7U-TD!Wj za9QKhhQgUsYw8PY8~x}w>7pdYgp2_u(e@nLu=vW#x;$t4ehuN zuBog@3JlG{wzbRJ(bo0?C0Z*=J)iyH2ivgZ@)8r#R2p$9zf6U`FnQy;@ms`Sa(U|NC&D za`FEm4&=x0;2+5Eyd=LI$lk$rsqPj!$6cHLSU0DyWsapnH z{X92N^~B>y#a~|LdlJXhx$Y_S8w}YyZoo-(x1Q&O&kday{3d!$V44{$Pd;bIt{0AR z{5JW29+Oz6V_^`-!NwN<2LyfZZ1&0jG+c5#zZ^+QpZ`NrUW|_h{{MmF;^zjO@YqQs zXF8FtDKpao>8U+JJ>6bzAAI%a5VxP3gWod9#rQ}*{Hl<%_e;M&zCi64@m~d;jp7G> z5Irv73_pFFP=EZNBK*6BvBG&U!2dY#9YH6Y6h5qXPC4dXsR8)=k09Pd>~9~wmv|xq zFqiY-0+9Vj5dZU*7@j|25I=%WdXj&-`8ie2Z}v#{P7H%+*+hH(7Gn9kCi!nHjjYV7Tgg<*oQh5A`ith+I1C#s*8hb^tZaUBx zn&lmo6n;>We_oP*p0U?A*3I*h!VgIb&sQVHkDxOw$$wZ4o@oY;Yr~~CWRlFNpE&D&bJ+OY+7wFmlvQ4khStQxoFLpLc=6=2h=G#jo za}VDG^XsjWHye4Z^OR)n)q6NcI_5{1ac=X2`4L;Nc>YSAfs(oZ?%|AgCQ4>mdpMJv zc?t3qXT9XD#($!7m1LWKnRBn?8;pOs^P=RzMy_!9o7haBd+Q!}4Gq3|V`Nk#`gfIs z-#zlllbzB8d78r?a%X%Se!8<-GWW+lFh5)d+~sYIf;esRPAqsgam!nrdmq+?ujqwKA(gv z`EM_F=qP^A_*YhJS{)u7`O4nGFR@%5z109{Xq@@(51L!SHoZiTP8!GmBXc z+^+7BapP+qvHHCHcaY=tn)pC2uD50AlNNsLu}H z^Rf3`(oYt#*hMjar{fnAMv$l5SE#3-fuAy@e2RSyPx>ai4@f_oFG+y|>qSqlmb{F_ z#{OL}@Ga~+$P4UyE&~_F(+>-D04uU>CP9LBpvuM2Lm_tN;Ith}Q^_7V>v+wd#9WV>yD`t!)4cY#R{=O zTqm9>ZWn(oz9w>iNjo2lpNVeJ>QlvBF<&ectHe5SvA9m$Bz{-?fq0vEzxb^9d-2cW z-^Fa~>zL0&MD8mo4-pR+i^Xx`RPh+GQN&M`n)qjnmx$MicZd&(&xx;#?~9*_>DU*V z{E1V=rDB_SmUywaRlHq%NPIx3=f$_hQMd)ndYUDkAg&Tm5ibSv7AI7nl;p8uDG58X{(*#@zsmnJay6b4i+D_I;`JqAKSvxSeUVryeVI5@`s2x! zj&q{8Qu>of*gHi$OZp4RX2mN*}~Vf#uI2 z7vi3i*kAer@n{l@@^ReF&FP8oq66L*4yixj}i+pky zz)iNN#9xsJ|6BRLE%{I4U!?z3@@FD$h1qhFh@U0)l75inA>v`uA0hcDaia9oCC?V? zrC%g@sn{(2ddVk?r%Qi<5q|oytq*Mm6F$rr%L}Vvc_?~BVJ4* z{i{gi??;kv74MM#e#sAuk4wK(@=M}t(*K#9h5M=EUip6}|CH`F-7aDliS%^2g#oNZ9Y%!*Vc*{1=l`9A}JpB)JazZ28ZYTqn+xeyQXp zakca(OFm6JOZtl>Um|`_`s*eCNc^$%_ej29{H652mb_E^Es6YpB6iKTq%@oDK_ zlKhJJhV<`A{;T+r^j}I2_O$j>Nu=LXa$m8(^ur~O6icL^Ah|-EOd|iw#nVaHy^yTH zdL>>;qFmR=|7OXziQA=rQ1T<rO5P-%EB(ciFB7kn{zl2Sh_{o-=QH9T#D9wY zd)xdTM&hw%fmlMKJf-rVB6)^5NBR>aH;BumZ7e}IGjX!qvStPa-}#$`g+Op#1o`%mb_YQC1L**af^73coT_y+)Wl? zzbrmLA|Fr6{{_jv6JL}5UCHl@d!_$EvWpu-v=bqbP7lew#Y3eZCi!r&NcvLAW#S|f z`CKHPEN&5RBazO1WC31XEzYqicZTP+<;twI=H(VS^BK}zUS4y5N&X9hd_W3!h5dtALZaNI@}Deux>!RZ{9^g9A#u&r zDsCVVf0O(#l>A+Bi}cq@zFxdZ`k#}q_pJDa_@Nl${e0Xv!!0R8T)rBj3JeQHENw;UF@%Wknc!-SNx|KaBa9W zv8&i$93+;AM~IV1-0zwy&Jp=NAL^UM)ndE2Q8dpz5bkox+sFp&bHqEvyTzx)UyCn_ zFN@~6NdvB@B=_R;jn#OLAe!f9kOxa1Eshf>ij`uWc&vD$xL9lzH;AW+<~a<~xk~c2 zqIoWZM*kUQ@B#6c;w$6{j`OEgNKx5Vqn;~Zz3XrA*xzEkqO;sfGN@g?y!ahGVG{~-Psl0z79 zw4W;W6?4QqahNz(JX)+5`Mo3BStu?M+r*Q^)5Wty^PC9rE|+|(c)R#>@fYGF;u9jj zpTua7aNQ;M5_83&;z+Sr94GR7O-#o;hXQ9x=J%VZpC>ko&El!z zCh?mhzxTv=KM;Q?-YniGJ}f>aJ}dr4d|UjJ_<^`r)iei&u)f#lMIjiJyx96!BIoQw~1kW_h}ay~IPr z!^8ryOso>8i?hWhag}(UXr8Mfor@)3CjLykPkc?>CGHmgBKE{W#{BjbE5vGXrZ`7D zOFU1!N4#HrRD4pzS4?gDiW9^NajG~|yhOZQyhglE+$(-8R`dB5@;^KX zV86TAOB^a5CXN@&#VO(p(LB$p!MsNqTrRE@+r*Q^GsLsS3&rn>*Nf)47VP~*@^w={0er0eEtKbi})!OBM%UB#bOfo&Buu2#d2|~Xr5~!++4}Wi49_- zc(Qn!c#e3!c#U|Sc$4^J@qY1P@g?yUahLdxxKG?KreJT(`}1AIY_X3xP|On#7YoI) zqIn($JF_L%iN}j4istzj!kr}fbnz_l67h2JR`GW6XX1V0GvagN>*O@Yc}x7W_<&08dpNNl&Pm0fp&x@~!uZtgwpNLqUR)ur5ziFQ z6~8TR7PpBvi+6~3iN6pZ5?>Tw7T*;AAigL5RSag^@}`L0#2(@yVt=tjJVG2Vn&(+4 z?=;D?#1qI0{F|!SEUp&6BVH_CAzm$BFaAjUiMU<7SA0M;&$*D^Q<8rpz99ZyG|#&b z?lZ~e`4;4eo&%+e-NjyFju;h(iHD2kIT!34A$h!5F4l|l#6{v#v7MagI2*-H;yL0C z;!Wc1;!nl1SnP{?Im};s|19ni z_lcj0Uy705wm#Cu?qV-7M~sR^;%M<`aiTa|tP_tHPZS%)X7Ob4H1Qnqe9=5-Lw%X& zY~VxEKPtW;{!V;Dd|Uib{6zdhbou-V_RRA&&^%uQbEJ=oMdE1jXmO%AUtB1f=WMXE zQnGoj2Kijc-xfEE*NWGR+sW~`Un4#!J|ey$zAgS)G|$%%Z=dA-;+JBO&!OO-E_M@p ziHC?K;t}F_v0OCI-C$>i-%s)&afmoZJW?zZtHkNzZ1EWJcyWceMqDqN=W|H+GRfZ; zuM@Y4zYrf1pAerBUlCsy-zUf6xsJGB{9MfHXZ?GM=J_1L50qRY9wCkw%f%XU44&tR z3&cfYySPz2Lp)pjp?ITsn|P;qk9fcMsQ9G#JMmTVZShayC*nUum(R73->{e`4igK+ z60uyIB-WFoaQ{kNBrX-t5ziODD_$yIDgHp*Cf+Ra_d99-F7X%QL*f(SGvZG1CGkV? z6Y&et#j_#WHP7=v^E?mCmcEZTK+F|~izCI+;y7`-I9ohcoG-2o;*;XD;`8Ef#n;8R#COH_#mxRTf7xO`ae!!^{~`b8`5#y${b=!M zaiUl)P7~*db4Bw!5Ox+xUM{W_TSfC+5aE6#`Brhe_%rbV@t5LG@g>nb|AU=fl6Q-L z5kC~o^FW0ALbA)}WRO$E3^7~mBMuV}7fZw=#A{Q9M<=NW4V6jyxRCbHv-kJH^Mvr^OxOi{hu^ zXCl8NKzk9ftJq!aE9QtJ#3FI5c(hm{R*N&mIbws@D6SG)#BYn6#Vf?C#qHwH#0SJ* ziaW#?#Xpe4@qHEXZ{kN{O0Mx9@pv{9NppXY)Tm93l=E$BCulbaF86V~WR$ z^ToAdoA?d!bn!bR>i%N!`{Fg?o#Nf%{o=#oE8^?oJL0?I-^7o^e~AASyCLsPzlS(n z94U?#$B7fgN^zPvOI#tY5!Z_+i(AAi#B0Ut#rwnu#mB{`#U0{{;;Z7D;$KP3T_1}7 z5dSIm7-Ic zwD^Yjw)ki9196|YU+jvp$nta-`-(YYo;XY_70blQ;&icIoF^_Pv3Fi6wuvW+7mD8% zFBh*AZzge#d7F5*c(3?tai{pQ_?oy^{8;>4#H*-`-AplC%oj(9qr|b|1hGOqR-7*` z7MF>u#dYF&;sxTx;$`C1;#To)@m}#^@iFn&;!bfF*$dx`5#Ja0h@pJzpDJdG*N1!9SKlsG}G7N?1|;xXch;$rc1@htIM;&;R?;uYex;`QP!;!ni8#e2n9#W%%2 ziSLPf#gE0$MZ9XvlsiT2B1RnO*E$ZW#C-n=w*k!eo3I@)-$O!l^F1(Z%}jh;`kL>L zm62$NDJ1%D4T*6ukHmOeL}DIlA~C;L_y=>PojJZeAnc%J6C;4JLl z$r_ZOtiyA4@)-R85_ufHpGwZhbq#rfeQyx|&#jDd1IkY>LHWr>l%HIV@{`RdKe-a+ zCs!j~9Dy*tKOv@)_{b2m$S(Gsv1DJ$cov5$HH?x7gsL>mC$sf`@?a5Vw99A_Rc6|! zR4gOWPN*V7RE=pbRteh;Rbkq#UYth`a-0R?A`*!&6`M%3=PI#7H!q4WlT-A4Ja89f^rLsgcgY!gp9HvvGWyj%aX(q3_X>ax`vLk{NHqNq z{VjtsX!;@g9e&Nq^gq)d(f@KNgHaOwaIk3lC;H0^Su`Iub(3= z_N(X9K=h|g>0puL{4N7T|1tmfihgr4^1%M`CW(HspU-vCKW;>x*e|}|b1?LWn~*p5 z1M@rw?SF1h$Y}3W{}(@K%$KINH*gJW!xe8MG|>_SMvKL+Rb4kd> zM*Eq53)%Erw4>>dkWGI?=1qTtZ2BA8)$}LGX1+xGZj!xoNVM}6lCLHU(61!lLlz-_ zl3ygz{_jiPLyked*biYpl|+AtN;cmsJqr1fTuP#U)JvX6qMx)#ZYL`+UrFZskjuy#j6cbXNc6W;C2t~+ zLH$U+nneG5Sn^}!eAJKR7fJNT_a*Nk(Jw!j?1UgUpudqw-+X^_3HqDld=mY&RB{=K zemg^Q4T=7{K=L9I{dkq+7Lw~=LEFiz+Zz^x?X8wg-Wh)Hpxr6puM;>0i}A+%0xAmd zswBR2%>TN!0=$$x?unN%#b4ak!7Kg_E&DEi8!!HHB;Om0ytlE%ZFCyUyqE3ZX7nnx zuQ2qlg|e?+`wCO$m1|!aM(@=6%5e7eT3;E=dl%SO2GqO3Itv$j@0oL8U%Vsiz@7&w zQ|t|Cc>mhL4e*s;2M%$N?8jfC)@l6MyVMTmdyo>u;`5zlon0NH|2Jh^}bmon9om=Se(zkYWU)a26*;*_Z=DcC?;?~9uw(nXEe(KLJHncXZ zS>A|Mg^Py`(NVLic}=5d5zCTOumnGe#UE<(#ahbPDF7=C&k4U!5o9|$#7Vr&5<0AemsW3VJrBR;YJ`#a=LiD6Fa_u#lfX2%GRcqKWb<(%WNcNrr7-zg3i{K%95VN(-r?C>1cl$;uYC4!84$B~CeHo# z{tDT%fz#MIq9=sg1NmhJ(82uixBRg^uOGpO`&f6Z-A#g1rjQ z80h7Xdv?FQ(9QAo?e4R;D9PSnbXZ<5c!!riUQ7DzW%%sjQY4nY^ONlDhdpeSV~3YN zUL*MJ_4L`prA*A;?Me2kkfG0G)@(S6w@4z_!zWLpA?wPss?wxVa(BLP1ZsuP*7QBDM zj<*wP<5h&$f{T&ohMD=-E4-THp=+4)hJ{y!(;p0mId-SUKA89Ky5n_1Vg8K^j|Y_u z5_ANP39k+wx`b&yb_X5n@2T)g=vOadyP2UM32z>}B1Ft@HzxD%t?<^ti{ zY~zi$qP(_ve!mHC+3|WDk9|_6)9y!C(fGvjyCJ;qj)$&#?q3J4SI?W>8qaS#bgejU z026K1@%Ccf;yoffej_WE--__oz_a}BcRYRz)B87t#%z%e1VfmqT@+r|^CZvj0VvGB z3E>T5Z0UAjaArLA*?qjnz_a!MLl-%3PIyb;jYfD4;hk|j41MH0e#6tp+mFU}D#H6H zyqe?nI^G}QeF1MW!uu_}y5k*oJdQbd|M;$Sti3uUy3b8?9Aosn0o)9xoqx<5?E)5j zJ|^Jb4s7T3i=m*r{_Y8H8N6BSH#6Q#(bczau4mJI6W}Rw>+d)wxSy_%3a3dXB@vVHt(x=T`S z;eC=6yR&jnLucjQ6kfHKq~o|oG~Ny2RevH5>|`86jyEa1h0B>vdHkQ?P4)5%^)NDO$%>)EgP36@4VwR0y=k8~HwQyLfp>9F^ zy93=AD>s-ez83#h(SfjdG1Qyq;}djfdPnT|jR#3`&{i;KnKaJb>5-IX@EmIkp3z|Y kElezzVX=G|K0Init.HwFlowCtl != UART_HWCONTROL_NONE) + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the parameters */ + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the parameters */ + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_INSTANCE(huart->Instance)); + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_RESET) + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Allocate lock resource and initialize it */ + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Lock = HAL_UNLOCKED; + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_InitCallbacksToDefault(huart); + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->MspInitCallback == NULL) + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + ARM GAS /tmp/ccQxTlMj.s page 7 + + + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->MspInitCallback = HAL_UART_MspInit; + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Init the low level hardware */ + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->MspInitCallback(huart); + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Init the low level hardware : GPIO, CLOCK */ + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_MspInit(huart); + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_DISABLE(huart); + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Perform advanced settings configuration */ + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* For some items, configuration requires to be done prior TE and RE bits are set */ + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_AdvFeatureConfig(huart); + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the UART Communication parameters */ + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (UART_SetConfig(huart) == HAL_ERROR) + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* In asynchronous mode, the following bits must be kept cleared: + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** - LINEN and CLKEN bits in the USART_CR2 register, + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_ENABLE(huart); + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return (UART_CheckIdleState(huart)); + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Initialize the half-duplex mode according to the specified + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * parameters in the UART_InitTypeDef and creates the associated handle. + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the UART handle allocation */ + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart == NULL) + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check UART instance */ + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 8 + + + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_RESET) + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Allocate lock resource and initialize it */ + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Lock = HAL_UNLOCKED; + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_InitCallbacksToDefault(huart); + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->MspInitCallback == NULL) + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->MspInitCallback = HAL_UART_MspInit; + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Init the low level hardware */ + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->MspInitCallback(huart); + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Init the low level hardware : GPIO, CLOCK */ + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_MspInit(huart); + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_DISABLE(huart); + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Perform advanced settings configuration */ + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* For some items, configuration requires to be done prior TE and RE bits are set */ + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_AdvFeatureConfig(huart); + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the UART Communication parameters */ + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (UART_SetConfig(huart) == HAL_ERROR) + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* In half-duplex mode, the following bits must be kept cleared: + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** - LINEN and CLKEN bits in the USART_CR2 register, + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** - SCEN and IREN bits in the USART_CR3 register.*/ + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_ENABLE(huart); + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return (UART_CheckIdleState(huart)); + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Initialize the LIN mode according to the specified + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * parameters in the UART_InitTypeDef and creates the associated handle. + ARM GAS /tmp/ccQxTlMj.s page 9 + + + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param BreakDetectLength Specifies the LIN break detection length. + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * This parameter can be one of the following values: + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the UART handle allocation */ + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart == NULL) + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the LIN UART instance */ + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the Break detection length parameter */ + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* LIN mode limited to 16-bit oversampling only */ + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* LIN mode limited to 8-bit data length */ + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->Init.WordLength != UART_WORDLENGTH_8B) + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_RESET) + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Allocate lock resource and initialize it */ + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Lock = HAL_UNLOCKED; + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_InitCallbacksToDefault(huart); + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->MspInitCallback == NULL) + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->MspInitCallback = HAL_UART_MspInit; + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Init the low level hardware */ + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->MspInitCallback(huart); + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Init the low level hardware : GPIO, CLOCK */ + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_MspInit(huart); + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_DISABLE(huart); + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Perform advanced settings configuration */ + ARM GAS /tmp/ccQxTlMj.s page 10 + + + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* For some items, configuration requires to be done prior TE and RE bits are set */ + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_AdvFeatureConfig(huart); + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the UART Communication parameters */ + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (UART_SetConfig(huart) == HAL_ERROR) + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* In LIN mode, the following bits must be kept cleared: + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** - LINEN and CLKEN bits in the USART_CR2 register, + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** - SCEN and IREN bits in the USART_CR3 register.*/ + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the USART LIN Break detection length. */ + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_ENABLE(huart); + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return (UART_CheckIdleState(huart)); + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Initialize the multiprocessor mode according to the specified + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * parameters in the UART_InitTypeDef and initialize the associated handle. + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param Address UART node address (4-, 6-, 7- or 8-bit long). + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param WakeUpMethod Specifies the UART wakeup method. + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * This parameter can be one of the following values: + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note If the user resorts to idle line detection wake up, the Address parameter + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * is useless and ignored by the initialization function. + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note If the user resorts to address mark wake up, the address length detection + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * is configured by default to 4 bits only. For the UART to be able to + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * manage 6-, 7- or 8-bit long addresses detection, the API + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * HAL_MultiProcessorEx_AddressLength_Set() must be called after + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * HAL_MultiProcessor_Init(). + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t Wake + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the UART handle allocation */ + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart == NULL) + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 11 + + + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the wake up method parameter */ + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_RESET) + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Allocate lock resource and initialize it */ + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Lock = HAL_UNLOCKED; + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_InitCallbacksToDefault(huart); + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->MspInitCallback == NULL) + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->MspInitCallback = HAL_UART_MspInit; + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Init the low level hardware */ + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->MspInitCallback(huart); + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Init the low level hardware : GPIO, CLOCK */ + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_MspInit(huart); + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_DISABLE(huart); + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Perform advanced settings configuration */ + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* For some items, configuration requires to be done prior TE and RE bits are set */ + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_AdvFeatureConfig(huart); + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the UART Communication parameters */ + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (UART_SetConfig(huart) == HAL_ERROR) + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* In multiprocessor mode, the following bits must be kept cleared: + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** - LINEN and CLKEN bits in the USART_CR2 register, + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* If address mark wake up method is chosen, set the USART address node */ + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS) + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the wake up method by setting the WAKE bit in the CR1 register */ + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_ENABLE(huart); + ARM GAS /tmp/ccQxTlMj.s page 12 + + + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return (UART_CheckIdleState(huart)); + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief DeInitialize the UART peripheral. + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the UART handle allocation */ + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart == NULL) + 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the parameters */ + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_INSTANCE(huart->Instance)); + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_DISABLE(huart); + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->CR1 = 0x0U; + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->CR2 = 0x0U; + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->CR3 = 0x0U; + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->MspDeInitCallback == NULL) + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->MspDeInitCallback = HAL_UART_MspDeInit; + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* DeInit the low level hardware */ + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->MspDeInitCallback(huart); + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* DeInit the low level hardware */ + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_MspDeInit(huart); + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_RESET; + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_RESET; + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UNLOCK(huart); + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Initialize the UART MSP. + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None + ARM GAS /tmp/ccQxTlMj.s page 13 + + + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UNUSED(huart); + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** the HAL_UART_MspInit can be implemented in the user file + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** + 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief DeInitialize the UART MSP. + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UNUSED(huart); + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** the HAL_UART_MspDeInit can be implemented in the user file + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Register a User UART Callback + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * To be used to override the weak predefined callback + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_In + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart uart handle + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param CallbackID ID of the callback to be registered + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * This parameter can be one of the following values: + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param pCallback pointer to the Callback function + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef C + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pUART_CallbackTypeDef pCallback) + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef status = HAL_OK; + 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (pCallback == NULL) + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + ARM GAS /tmp/ccQxTlMj.s page 14 + + + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_READY) + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** switch (CallbackID) + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_TX_HALFCOMPLETE_CB_ID : + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxHalfCpltCallback = pCallback; + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_TX_COMPLETE_CB_ID : + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxCpltCallback = pCallback; + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_RX_HALFCOMPLETE_CB_ID : + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxHalfCpltCallback = pCallback; + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_RX_COMPLETE_CB_ID : + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxCpltCallback = pCallback; + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_ERROR_CB_ID : + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCallback = pCallback; + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_ABORT_COMPLETE_CB_ID : + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->AbortCpltCallback = pCallback; + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->AbortTransmitCpltCallback = pCallback; + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->AbortReceiveCpltCallback = pCallback; + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if defined(USART_CR1_UESM) + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if defined(USART_CR3_WUFIE) + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_WAKEUP_CB_ID : + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->WakeupCallback = pCallback; + 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USART_CR3_WUFIE */ + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USART_CR1_UESM */ + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_MSPINIT_CB_ID : + 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->MspInitCallback = pCallback; + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_MSPDEINIT_CB_ID : + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->MspDeInitCallback = pCallback; + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + ARM GAS /tmp/ccQxTlMj.s page 15 + + + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** default : + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** status = HAL_ERROR; + 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else if (huart->gState == HAL_UART_STATE_RESET) + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** switch (CallbackID) + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_MSPINIT_CB_ID : + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->MspInitCallback = pCallback; + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_MSPDEINIT_CB_ID : + 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->MspDeInitCallback = pCallback; + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** default : + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** status = HAL_ERROR; + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** status = HAL_ERROR; + 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return status; + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Unregister an UART Callback + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * UART callaback is redirected to the weak predefined callback + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_ + 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET + 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart uart handle + 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param CallbackID ID of the callback to be unregistered + 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * This parameter can be one of the following values: + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + ARM GAS /tmp/ccQxTlMj.s page 16 + + + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status + 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ + 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef status = HAL_OK; + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_UART_STATE_READY == huart->gState) + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** switch (CallbackID) + 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_TX_HALFCOMPLETE_CB_ID : + 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHa + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_TX_COMPLETE_CB_ID : + 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpl + 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_RX_HALFCOMPLETE_CB_ID : + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHal + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_RX_COMPLETE_CB_ID : + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpl + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_ERROR_CB_ID : + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak Error + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_ABORT_COMPLETE_CB_ID : + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak Abort + 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak + 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** AbortTransmitCplt + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak + 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** AbortReceiveCpltC + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if defined(USART_CR1_UESM) + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if defined(USART_CR3_WUFIE) + 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_WAKEUP_CB_ID : + 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak Wakeu + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USART_CR3_WUFIE */ + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USART_CR1_UESM */ + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_MSPINIT_CB_ID : + 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspIn + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_MSPDEINIT_CB_ID : + ARM GAS /tmp/ccQxTlMj.s page 17 + + + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDe + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** default : + 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** status = HAL_ERROR; + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else if (HAL_UART_STATE_RESET == huart->gState) + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** switch (CallbackID) + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_MSPINIT_CB_ID : + 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->MspInitCallback = HAL_UART_MspInit; + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case HAL_UART_MSPDEINIT_CB_ID : + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->MspDeInitCallback = HAL_UART_MspDeInit; + 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** default : + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** status = HAL_ERROR; + 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else + 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** status = HAL_ERROR; + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return status; + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Register a User UART Rx Event Callback + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * To be used instead of the weak predefined callback + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart Uart handle + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param pCallback Pointer to the Rx Event Callback function + 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallback + 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef status = HAL_OK; + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (pCallback == NULL) + 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 18 + + + 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->RxState == HAL_UART_STATE_READY) + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventCallback = pCallback; + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else + 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** status = HAL_ERROR; + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return status; + 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** + 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief UnRegister the UART Rx Event Callback + 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefine + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart Uart handle + 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status + 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ + 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) + 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef status = HAL_OK; + 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->RxState == HAL_UART_STATE_READY) + 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ + 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else + 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** status = HAL_ERROR; + 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return status; + 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** + 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @} + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** @defgroup UART_Exported_Functions_Group2 IO operation functions + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief UART Transmit/Receive functions + 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** @verbatim + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** =============================================================================== + 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ##### IO operation functions ##### + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** =============================================================================== + 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** This subsection provides a set of functions allowing to manage the UART asynchronous + 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** and Half duplex data transfers. + 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (#) There are two mode of transfer: +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) Blocking mode: The communication is performed in polling mode. +1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** The HAL status of all data processing is returned by the same function + ARM GAS /tmp/ccQxTlMj.s page 19 + + +1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** after finishing transfer. +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) Non-Blocking mode: The communication is performed using Interrupts +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** or DMA, These API's return the HAL status. +1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** The end of the data processing will be indicated through the +1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** dedicated UART IRQ when using Interrupt mode or the DMA IRQ when +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** using DMA mode. +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** will be executed respectively at the end of the transmit or Receive process +1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** The HAL_UART_ErrorCallback()user callback will be executed when a communication error is +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (#) Blocking mode API's are : +1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_Transmit() +1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_Receive() +1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (#) Non-Blocking mode API's with Interrupt are : +1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_Transmit_IT() +1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_Receive_IT() +1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_IRQHandler() +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (#) Non-Blocking mode API's with DMA are : +1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_Transmit_DMA() +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_Receive_DMA() +1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_DMAPause() +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_DMAResume() +1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_DMAStop() +1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: +1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_TxHalfCpltCallback() +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_TxCpltCallback() +1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_RxHalfCpltCallback() +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_RxCpltCallback() +1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_ErrorCallback() +1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (#) Non-Blocking mode transfers could be aborted using Abort API's : +1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_Abort() +1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_AbortTransmit() +1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_AbortReceive() +1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_Abort_IT() +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_AbortTransmit_IT() +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_AbortReceive_IT() +1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Call +1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_AbortCpltCallback() +1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_AbortTransmitCpltCallback() +1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_AbortReceiveCpltCallback() +1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes o +1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** reception services: +1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UARTEx_RxEventCallback() +1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if defined(USART_CR1_UESM) +1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (#) Wakeup from Stop mode Callback: +1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UARTEx_WakeupCallback() +1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** Errors are handled as follows : + ARM GAS /tmp/ccQxTlMj.s page 20 + + +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but er +1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error +1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** in Interrupt mode reception . +1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** Received character is then retrieved and stored in Rx buffer, Error code is set to allow +1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** to identify error type, and HAL_UART_ErrorCallback() user callback is executed. +1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** Transfer is kept ongoing on UART side. +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** If user wants to abort it, Abort services should be called by user. +1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) Error is considered as Blocking : Transfer could not be completed properly and is aborte +1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. +1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** user callback is executed. +1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** -@- In the Half duplex communication, it is forbidden to run the transmit +1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** @endverbatim +1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @{ +1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Send an amount of data in blocking mode. +1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1- +1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * the sent data is handled as a set of u16. In this case, Size must indicate the number +1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * of u16 provided through pData. +1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param pData Pointer to data buffer (u8 or u16 data elements). +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param Size Amount of data elements (u8 or u16) to be sent. +1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param Timeout Timeout duration. +1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const uint8_t *pdata8bits; +1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const uint16_t *pdata16bits; +1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t tickstart; +1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that a Tx process is not already ongoing */ +1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_READY) +1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((pData == NULL) || (Size == 0U)) +1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; +1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Init tickstart for timeout management */ +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** tickstart = HAL_GetTick(); +1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferSize = Size; +1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = Size; +1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) +1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata8bits = NULL; + ARM GAS /tmp/ccQxTlMj.s page 21 + + +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits = (const uint16_t *) pData; +1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata8bits = pData; +1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits = NULL; +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** while (huart->TxXferCount > 0U) +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_TIMEOUT; +1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (pdata8bits == NULL) +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); +1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits++; +1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata8bits++; +1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount--; +1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) +1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_TIMEOUT; +1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* At end of Tx process, restore huart->gState to Ready */ +1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_BUSY; +1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Receive an amount of data in blocking mode. +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1- +1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * the received data is handled as a set of u16. In this case, Size must indicate the numb +1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * of u16 available through pData. +1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param pData Pointer to data buffer (u8 or u16 data elements). +1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param Size Amount of data elements (u8 or u16) to be received. +1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param Timeout Timeout duration. + ARM GAS /tmp/ccQxTlMj.s page 22 + + +1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32 +1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint8_t *pdata8bits; +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint16_t *pdata16bits; +1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint16_t uhMask; +1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t tickstart; +1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that a Rx process is not already ongoing */ +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->RxState == HAL_UART_STATE_READY) +1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((pData == NULL) || (Size == 0U)) +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; +1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Init tickstart for timeout management */ +1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** tickstart = HAL_GetTick(); +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferSize = Size; +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = Size; +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Computation of UART mask to apply to RDR register */ +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_MASK_COMPUTATION(huart); +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uhMask = huart->Mask; +1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ +1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) +1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata8bits = NULL; +1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits = (uint16_t *) pData; +1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata8bits = pData; +1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits = NULL; +1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* as long as data have to be received */ +1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** while (huart->RxXferCount > 0U) +1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) +1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_TIMEOUT; +1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (pdata8bits == NULL) +1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); +1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits++; +1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + ARM GAS /tmp/ccQxTlMj.s page 23 + + +1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); +1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata8bits++; +1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount--; +1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* At end of Rx process, restore huart->RxState to Ready */ +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_BUSY; +1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Send an amount of data in interrupt mode. +1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1- +1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * the sent data is handled as a set of u16. In this case, Size must indicate the number +1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * of u16 provided through pData. +1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param pData Pointer to data buffer (u8 or u16 data elements). +1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param Size Amount of data elements (u8 or u16) to be sent. +1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Si +1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that a Tx process is not already ongoing */ +1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_READY) +1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((pData == NULL) || (Size == 0U)) +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; +1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pTxBuffPtr = pData; +1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferSize = Size; +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = Size; +1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxISR = NULL; +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; +1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the Tx ISR function pointer according to the data word length */ +1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxISR = UART_TxISR_16BIT; +1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxISR = UART_TxISR_8BIT; +1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 24 + + +1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the Transmit Data Register Empty interrupt */ +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); +1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_BUSY; +1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Receive an amount of data in interrupt mode. +1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1- +1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * the received data is handled as a set of u16. In this case, Size must indicate the numb +1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * of u16 available through pData. +1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param pData Pointer to data buffer (u8 or u16 data elements). +1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param Size Amount of data elements (u8 or u16) to be received. +1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that a Rx process is not already ongoing */ +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->RxState == HAL_UART_STATE_READY) +1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((pData == NULL) || (Size == 0U)) +1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; +1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set Reception type to Standard reception */ +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that USART RTOEN bit is set */ +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) +1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the UART Receiver Timeout Interrupt */ +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); +1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return (UART_Start_Receive_IT(huart, pData, Size)); +1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_BUSY; +1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Send an amount of data in DMA mode. +1338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1- +1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * the sent data is handled as a set of u16. In this case, Size must indicate the number +1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * of u16 provided through pData. +1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +1342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param pData Pointer to data buffer (u8 or u16 data elements). +1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param Size Amount of data elements (u8 or u16) to be sent. + ARM GAS /tmp/ccQxTlMj.s page 25 + + +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t S +1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that a Tx process is not already ongoing */ +1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_READY) +1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((pData == NULL) || (Size == 0U)) +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; +1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pTxBuffPtr = pData; +1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferSize = Size; +1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = Size; +1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; +1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmatx != NULL) +1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the UART DMA transfer complete callback */ +1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; +1367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the UART DMA Half transfer complete callback */ +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; +1370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the DMA error callback */ +1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmatx->XferErrorCallback = UART_DMAError; +1373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the DMA abort callback */ +1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = NULL; +1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the UART transmit DMA channel */ +1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance-> +1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set error code to DMA */ +1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_DMA; +1382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Restore huart->gState to ready */ +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; +1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear the TC flag in the ICR register */ +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); +1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the DMA transfer for transmit request by setting the DMAT bit +1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** in the UART CR3 register */ +1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_BUSY; + ARM GAS /tmp/ccQxTlMj.s page 26 + + +1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Receive an amount of data in DMA mode. +1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note When the UART parity is enabled (PCE = 1), the received data contain +1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * the parity bit (MSB position). +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1- +1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * the received data is handled as a set of u16. In this case, Size must indicate the numb +1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * of u16 available through pData. +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param pData Pointer to data buffer (u8 or u16 data elements). +1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param Size Amount of data elements (u8 or u16) to be received. +1414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that a Rx process is not already ongoing */ +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->RxState == HAL_UART_STATE_READY) +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((pData == NULL) || (Size == 0U)) +1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; +1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set Reception type to Standard reception */ +1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that USART RTOEN bit is set */ +1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) +1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the UART Receiver Timeout Interrupt */ +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); +1434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return (UART_Start_Receive_DMA(huart, pData, Size)); +1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_BUSY; +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Pause the DMA Transfer. +1446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +1449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const HAL_UART_StateTypeDef gstate = huart->gState; +1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const HAL_UART_StateTypeDef rxstate = huart->RxState; +1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && +1455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) +1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the UART DMA Tx request */ + ARM GAS /tmp/ccQxTlMj.s page 27 + + +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && +1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) +1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the UART DMA Rx request */ +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Resume the DMA Transfer. +1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_BUSY_TX) +1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the UART DMA Tx request */ +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->RxState == HAL_UART_STATE_BUSY_RX) +1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear the Overrun flag before resuming the Rx transfer */ +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); +1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ +1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->Init.Parity != UART_PARITY_NONE) +1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); +1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); +1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the UART DMA Rx request */ +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Stop the DMA Transfer. +1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +1508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +1511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* The Lock is not implemented on this API to allow the user application +1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() +1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + ARM GAS /tmp/ccQxTlMj.s page 28 + + +1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete +1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of +1517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** the stream and the corresponding call back is executed. */ +1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const HAL_UART_StateTypeDef gstate = huart->gState; +1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const HAL_UART_StateTypeDef rxstate = huart->RxState; +1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Stop UART DMA Tx request if ongoing */ +1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) +1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Tx channel */ +1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmatx != NULL) +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) +1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) +1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set error code to DMA */ +1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_DMA; +1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_TIMEOUT; +1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_EndTxTransfer(huart); +1544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Stop UART DMA Rx request if ongoing */ +1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && +1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) +1549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Rx channel */ +1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmarx != NULL) +1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) +1556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) +1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set error code to DMA */ +1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_DMA; +1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_TIMEOUT; +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_EndRxTransfer(huart); +1568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + ARM GAS /tmp/ccQxTlMj.s page 29 + + +1572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +1574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Abort ongoing transfers (blocking mode). +1575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +1576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or +1577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * This procedure performs following operations : +1578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Disable UART Interrupts (Tx and Rx) +1579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +1580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) +1581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Set handle State to READY +1582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note This procedure is executed in blocking mode : when exiting function, Abort is considere +1583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +1584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +1585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USA +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +1590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ +1592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) +1593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); +1595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Tx channel if enabled */ +1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) +1599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the UART DMA Tx request if enabled */ +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ +1604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmatx != NULL) +1605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the UART DMA Abort callback to Null. +1607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** No call back execution at end of DMA abort procedure */ +1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = NULL; +1609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) +1611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) +1613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set error code to DMA */ +1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_DMA; +1616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_TIMEOUT; +1618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Rx channel if enabled */ +1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) +1625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the UART DMA Rx request if enabled */ +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 30 + + +1629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ +1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmarx != NULL) +1631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the UART DMA Abort callback to Null. +1633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** No call back execution at end of DMA abort procedure */ +1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = NULL; +1635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) +1637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) +1639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set error code to DMA */ +1641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_DMA; +1642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_TIMEOUT; +1644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Reset Tx and Rx transfer counters */ +1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = 0U; +1651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; +1652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); +1655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Discard the received data */ +1658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); +1659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Restore huart->gState and huart->RxState to Ready */ +1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +1663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +1664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +1666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +1671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Abort ongoing Transmit transfer (blocking mode). +1672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +1673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt +1674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * This procedure performs following operations : +1675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Disable UART Interrupts (Tx) +1676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +1677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) +1678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Set handle State to READY +1679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note This procedure is executed in blocking mode : when exiting function, Abort is considere +1680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +1681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +1682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable TXEIE and TCIE interrupts */ +1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + ARM GAS /tmp/ccQxTlMj.s page 31 + + +1686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Tx channel if enabled */ +1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) +1689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the UART DMA Tx request if enabled */ +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ +1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmatx != NULL) +1695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the UART DMA Abort callback to Null. +1697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** No call back execution at end of DMA abort procedure */ +1698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = NULL; +1699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) +1701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) +1703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set error code to DMA */ +1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_DMA; +1706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_TIMEOUT; +1708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Reset Tx transfer counter */ +1714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = 0U; +1715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Restore huart->gState to Ready */ +1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +1724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Abort ongoing Receive transfer (blocking mode). +1725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +1726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt +1727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * This procedure performs following operations : +1728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Disable UART Interrupts (Rx) +1729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +1730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) +1731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Set handle State to READY +1732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note This procedure is executed in blocking mode : when exiting function, Abort is considere +1733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +1734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +1735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +1736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +1740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ +1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + ARM GAS /tmp/ccQxTlMj.s page 32 + + +1743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); +1745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Rx channel if enabled */ +1748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) +1749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the UART DMA Rx request if enabled */ +1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmarx != NULL) +1755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the UART DMA Abort callback to Null. +1757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** No call back execution at end of DMA abort procedure */ +1758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = NULL; +1759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) +1761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) +1763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set error code to DMA */ +1765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_DMA; +1766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_TIMEOUT; +1768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Reset Rx transfer counter */ +1774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; +1775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +1777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); +1778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Discard the received data */ +1780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); +1781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Restore huart->RxState to Ready */ +1783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +1784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +1785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +1787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +1790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Abort ongoing transfers (Interrupt mode). +1791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +1792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or +1793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * This procedure performs following operations : +1794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Disable UART Interrupts (Tx and Rx) +1795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +1796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) +1797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Set handle State to READY +1798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - At abort completion, call user abort complete callback +1799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + ARM GAS /tmp/ccQxTlMj.s page 33 + + +1800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * considered as completed only when user abort complete callback is executed (not when ex +1801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +1802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +1803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +1804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t abortcplt = 1U; +1806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable interrupts */ +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USA +1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +1810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ +1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) +1813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); +1815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks sh +1818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** before any call to DMA Abort functions */ +1819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* DMA Tx Handle is valid */ +1820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmatx != NULL) +1821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. +1823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** Otherwise, set it to NULL */ +1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) +1825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; +1827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +1829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = NULL; +1831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* DMA Rx Handle is valid */ +1834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmarx != NULL) +1835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. +1837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** Otherwise, set it to NULL */ +1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) +1839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; +1841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +1843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = NULL; +1845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Tx channel if enabled */ +1849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) +1850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable DMA Tx at UART level */ +1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ +1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmatx != NULL) +1856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + ARM GAS /tmp/ccQxTlMj.s page 34 + + +1857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* UART Tx DMA Abort callback has already been initialised : +1858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ +1859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort DMA TX */ +1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) +1862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = NULL; +1864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +1866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** abortcplt = 0U; +1868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Rx channel if enabled */ +1873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) +1874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the UART DMA Rx request if enabled */ +1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +1877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ +1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmarx != NULL) +1880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* UART Rx DMA Abort callback has already been initialised : +1882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ +1883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort DMA RX */ +1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) +1886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = NULL; +1888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** abortcplt = 1U; +1889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +1891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** abortcplt = 0U; +1893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* if no DMA abort complete callback execution is required => call user Abort Complete callback * +1898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (abortcplt == 1U) +1899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Reset Tx and Rx transfer counters */ +1901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = 0U; +1902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; +1903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear ISR function pointers */ +1905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxISR = NULL; +1906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxISR = NULL; +1907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Reset errorCode */ +1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +1910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +1912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF +1913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 35 + + +1914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Discard the received data */ +1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); +1917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Restore huart->gState and huart->RxState to Ready */ +1919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +1922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* As no DMA to be aborted, call directly user Abort complete callback */ +1924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +1925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call registered Abort complete callback */ +1926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->AbortCpltCallback(huart); +1927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +1928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call legacy weak Abort complete callback */ +1929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_AbortCpltCallback(huart); +1930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +1931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +1934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +1937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Abort ongoing Transmit transfer (Interrupt mode). +1938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +1939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt +1940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * This procedure performs following operations : +1941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Disable UART Interrupts (Tx) +1942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +1943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) +1944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Set handle State to READY +1945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - At abort completion, call user abort complete callback +1946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be +1947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * considered as completed only when user abort complete callback is executed (not when ex +1948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +1949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +1950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +1951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable interrupts */ +1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +1954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Tx channel if enabled */ +1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) +1957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the UART DMA Tx request if enabled */ +1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +1960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ +1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmatx != NULL) +1963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the UART DMA Abort callback : +1965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ +1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; +1967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort DMA TX */ +1969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) +1970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + ARM GAS /tmp/ccQxTlMj.s page 36 + + +1971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ +1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmatx->XferAbortCallback(huart->hdmatx); +1973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +1976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Reset Tx transfer counter */ +1978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = 0U; +1979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear TxISR function pointers */ +1981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxISR = NULL; +1982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Restore huart->gState to Ready */ +1984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +1985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +1986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* As no DMA to be aborted, call directly user Abort complete callback */ +1987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +1988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call registered Abort Transmit Complete Callback */ +1989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->AbortTransmitCpltCallback(huart); +1990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +1991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call legacy weak Abort Transmit Complete Callback */ +1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_AbortTransmitCpltCallback(huart); +1993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +1994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +1996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +1997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +1998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Reset Tx transfer counter */ +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = 0U; +2000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear TxISR function pointers */ +2002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxISR = NULL; +2003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Restore huart->gState to Ready */ +2006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* As no DMA to be aborted, call directly user Abort complete callback */ +2009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call registered Abort Transmit Complete Callback */ +2011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->AbortTransmitCpltCallback(huart); +2012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +2013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call legacy weak Abort Transmit Complete Callback */ +2014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_AbortTransmitCpltCallback(huart); +2015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +2016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Abort ongoing Receive transfer (Interrupt mode). +2023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +2024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt +2025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * This procedure performs following operations : +2026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Disable UART Interrupts (Rx) +2027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Disable the DMA transfer in the peripheral register (if enabled) + ARM GAS /tmp/ccQxTlMj.s page 37 + + +2028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) +2029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - Set handle State to READY +2030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - At abort completion, call user abort complete callback +2031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be +2032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * considered as completed only when user abort complete callback is executed (not when ex +2033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +2034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +2040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ +2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) +2043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); +2045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Rx channel if enabled */ +2048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) +2049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the UART DMA Rx request if enabled */ +2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +2052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ +2054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmarx != NULL) +2055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the UART DMA Abort callback : +2057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ +2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; +2059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort DMA RX */ +2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) +2062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ +2064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback(huart->hdmarx); +2065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +2068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Reset Rx transfer counter */ +2070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; +2071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear RxISR function pointer */ +2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pRxBuffPtr = NULL; +2074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_F +2077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Discard the received data */ +2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); +2080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Restore huart->RxState to Ready */ +2082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +2084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 38 + + +2085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* As no DMA to be aborted, call directly user Abort complete callback */ +2086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call registered Abort Receive Complete Callback */ +2088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->AbortReceiveCpltCallback(huart); +2089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +2090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call legacy weak Abort Receive Complete Callback */ +2091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_AbortReceiveCpltCallback(huart); +2092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +2093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +2096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Reset Rx transfer counter */ +2098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; +2099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear RxISR function pointer */ +2101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pRxBuffPtr = NULL; +2102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +2104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF +2105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Restore huart->RxState to Ready */ +2107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +2108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +2109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* As no DMA to be aborted, call directly user Abort complete callback */ +2111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call registered Abort Receive Complete Callback */ +2113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->AbortReceiveCpltCallback(huart); +2114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +2115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call legacy weak Abort Receive Complete Callback */ +2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_AbortReceiveCpltCallback(huart); +2117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +2118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +2121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Handle UART interrupt request. +2125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +2126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +2127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +2129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t isrflags = READ_REG(huart->Instance->ISR); +2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t cr1its = READ_REG(huart->Instance->CR1); +2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t cr3its = READ_REG(huart->Instance->CR3); +2133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t errorflags; +2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t errorcode; +2136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* If no error occurs */ +2138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | +2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (errorflags == 0U) +2140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* UART in mode Receiver ---------------------------------------------------*/ + ARM GAS /tmp/ccQxTlMj.s page 39 + + +2142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (((isrflags & USART_ISR_RXNE) != 0U) +2143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && ((cr1its & USART_CR1_RXNEIE) != 0U)) +2144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->RxISR != NULL) +2146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxISR(huart); +2148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return; +2150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* If some errors occur */ +2154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((errorflags != 0U) +2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && (((cr3its & USART_CR3_EIE) != 0U) +2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))) +2157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* UART parity error interrupt occurred -------------------------------------*/ +2159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) +2160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); +2162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_PE; +2164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* UART frame error interrupt occurred --------------------------------------*/ +2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) +2168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); +2170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_FE; +2172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* UART noise error interrupt occurred --------------------------------------*/ +2175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) +2176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); +2178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_NE; +2180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* UART Over-Run interrupt occurred -----------------------------------------*/ +2183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (((isrflags & USART_ISR_ORE) != 0U) +2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && (((cr1its & USART_CR1_RXNEIE) != 0U) || +2185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ((cr3its & USART_CR3_EIE) != 0U))) +2186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); +2188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_ORE; +2190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* UART Receiver Timeout interrupt occurred ---------------------------------*/ +2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) +2194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); +2196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_RTO; +2198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + ARM GAS /tmp/ccQxTlMj.s page 40 + + +2199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call UART Error Call back function if need be ----------------------------*/ +2201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->ErrorCode != HAL_UART_ERROR_NONE) +2202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* UART in mode Receiver --------------------------------------------------*/ +2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (((isrflags & USART_ISR_RXNE) != 0U) +2205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && ((cr1its & USART_CR1_RXNEIE) != 0U)) +2206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->RxISR != NULL) +2208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxISR(huart); +2210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* If Error is to be considered as blocking : +2214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** - Receiver Timeout error in Reception +2215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** - Overrun error in Reception +2216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** - any error occurs in DMA mode reception +2217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** errorcode = huart->ErrorCode; +2219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || +2220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) +2221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Blocking error : transfer is aborted +2223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** Set the UART state ready to be able to start again the process, +2224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ +2225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_EndRxTransfer(huart); +2226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Rx channel if enabled */ +2228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) +2229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the UART DMA Rx request if enabled */ +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +2232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort the UART DMA Rx channel */ +2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmarx != NULL) +2235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the UART DMA Abort callback : +2237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ +2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; +2239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Abort DMA RX */ +2241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) +2242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ +2244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback(huart->hdmarx); +2245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +2248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call user error callback */ +2250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call registered error callback*/ +2252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCallback(huart); +2253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +2254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call legacy weak error callback*/ +2255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_ErrorCallback(huart); + ARM GAS /tmp/ccQxTlMj.s page 41 + + +2256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +2257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +2261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call user error callback */ +2263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call registered error callback*/ +2265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCallback(huart); +2266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +2267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call legacy weak error callback*/ +2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_ErrorCallback(huart); +2269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +2270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +2273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Non Blocking error : transfer could go on. +2275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** Error is notified to user through user error callback */ +2276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call registered error callback*/ +2278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCallback(huart); +2279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +2280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call legacy weak error callback*/ +2281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_ErrorCallback(huart); +2282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +2283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +2284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return; +2287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } /* End if some error occurs */ +2289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check current reception Mode : +2291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** If Reception till IDLE event has been selected : */ +2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) +2293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && ((isrflags & USART_ISR_IDLE) != 0U) +2294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && ((cr1its & USART_ISR_IDLE) != 0U)) +2295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); +2297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check if DMA mode is enabled in UART */ +2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) +2300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* DMA mode enabled */ +2302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check received length : If all expected data are received, do nothing, +2303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (DMA cplt callback will be called). +2304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** Otherwise, if at least one data has already been received, IDLE event is to be notified to +2305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); +2306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((nb_remaining_rx_data > 0U) +2307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && (nb_remaining_rx_data < huart->RxXferSize)) +2308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Reception is not complete */ +2310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = nb_remaining_rx_data; +2311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + ARM GAS /tmp/ccQxTlMj.s page 42 + + +2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) +2314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ +2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); +2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +2318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the DMA transfer for the receiver request by resetting the DMAR bit +2320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** in the UART CR3 register */ +2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +2322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* At end of Rx process, restore huart->RxState to Ready */ +2324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +2325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +2326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); +2328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Last bytes received, so no need as the abort is immediate */ +2330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (void)HAL_DMA_Abort(huart->hdmarx); +2331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Initialize type of RxEvent that correspond to RxEvent callback execution; +2334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** In this case, Rx Event type is Idle Event */ +2335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventType = HAL_UART_RXEVENT_IDLE; +2336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call registered Rx Event callback*/ +2339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +2340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +2341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call legacy weak Rx Event callback*/ +2342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +2343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ +2344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return; +2346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +2348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* DMA mode not enabled */ +2350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check received length : If all expected data are received, do nothing. +2351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** Otherwise, if at least one data has already been received, IDLE event is to be notified to +2352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; +2353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((huart->RxXferCount > 0U) +2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && (nb_rx_data > 0U)) +2355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the UART Parity Error Interrupt and RXNE interrupts */ +2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +2358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ +2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +2361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Rx process is completed, restore huart->RxState to Ready */ +2363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +2364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +2365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear RxISR function pointer */ +2367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxISR = NULL; +2368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ARM GAS /tmp/ccQxTlMj.s page 43 + + +2370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Initialize type of RxEvent that correspond to RxEvent callback execution; +2372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** In this case, Rx Event type is Idle Event */ +2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventType = HAL_UART_RXEVENT_IDLE; +2374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call registered Rx complete callback*/ +2377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventCallback(huart, nb_rx_data); +2378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +2379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call legacy weak Rx Event callback*/ +2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UARTEx_RxEventCallback(huart, nb_rx_data); +2381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ +2382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return; +2384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if defined(USART_CR1_UESM) +2387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if defined(USART_CR3_WUFIE) +2388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ +2390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) +2391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); +2393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* UART Rx state is not reset as a reception process might be ongoing. +2395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** If UART handle state fields need to be reset to READY, this could be done in Wakeup callback +2396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call registered Wakeup Callback */ +2399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->WakeupCallback(huart); +2400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +2401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call legacy weak Wakeup Callback */ +2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UARTEx_WakeupCallback(huart); +2403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +2404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return; +2405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USART_CR3_WUFIE */ +2407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USART_CR1_UESM */ +2408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* UART in mode Transmitter ------------------------------------------------*/ +2410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (((isrflags & USART_ISR_TXE) != 0U) +2411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && ((cr1its & USART_CR1_TXEIE) != 0U)) +2412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->TxISR != NULL) +2414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxISR(huart); +2416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return; +2418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* UART in mode Transmitter (transmission end) -----------------------------*/ +2421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) +2422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_EndTransmit_IT(huart); +2424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return; +2425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 44 + + +2427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Tx Transfer completed callback. +2431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +2432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +2433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +2435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +2437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UNUSED(huart); +2438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +2440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** the HAL_UART_TxCpltCallback can be implemented in the user file. +2441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Tx Half Transfer completed callback. +2446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +2447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +2448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +2450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UNUSED(huart); +2453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* NOTE: This function should not be modified, when the callback is needed, +2455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** the HAL_UART_TxHalfCpltCallback can be implemented in the user file. +2456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Rx Transfer completed callback. +2461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +2462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +2463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +2467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UNUSED(huart); +2468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +2470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** the HAL_UART_RxCpltCallback can be implemented in the user file. +2471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Rx Half Transfer completed callback. +2476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +2477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +2478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +2480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UNUSED(huart); +2483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 45 + + +2484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* NOTE: This function should not be modified, when the callback is needed, +2485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** the HAL_UART_RxHalfCpltCallback can be implemented in the user file. +2486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief UART error callback. +2491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +2492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +2493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +2495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UNUSED(huart); +2498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +2500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** the HAL_UART_ErrorCallback can be implemented in the user file. +2501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief UART Abort Complete callback. +2506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +2507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +2508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +2510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +2512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UNUSED(huart); +2513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +2515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** the HAL_UART_AbortCpltCallback can be implemented in the user file. +2516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief UART Abort Complete callback. +2521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +2522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +2523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) +2525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +2527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UNUSED(huart); +2528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +2530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. +2531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief UART Abort Receive Complete callback. +2536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +2537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +2538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) +2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + ARM GAS /tmp/ccQxTlMj.s page 46 + + +2541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +2542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UNUSED(huart); +2543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +2545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. +2546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Reception Event Callback (Rx event notification called after use of advanced reception +2551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle +2552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param Size Number of data available in application reception buffer (indicates a position in +2553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * reception buffer until which, data are available) +2554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +2555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +2557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +2559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UNUSED(huart); +2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UNUSED(Size); +2561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +2563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** the HAL_UARTEx_RxEventCallback can be implemented in the user file. +2564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if defined(USART_CR1_UESM) +2568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief UART wakeup from Stop mode callback. +2570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +2571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +2572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +2574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ +2576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UNUSED(huart); +2577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* NOTE : This function should not be modified, when the callback is needed, +2579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** the HAL_UARTEx_WakeupCallback can be implemented in the user file. +2580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USART_CR1_UESM */ +2584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @} +2586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions +2589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief UART control functions +2590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * +2591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** @verbatim +2592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** =============================================================================== +2593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ##### Peripheral Control functions ##### +2594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** =============================================================================== +2595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** [..] +2596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** This subsection provides a set of functions allowing to control the UART. +2597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on th + ARM GAS /tmp/ccQxTlMj.s page 47 + + +2598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature +2599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature +2600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode +2601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode +2602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode +2603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) UART_SetConfig() API configures the UART peripheral +2604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features +2605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization +2606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter +2607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver +2608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) HAL_LIN_SendBreak() API transmits the break characters +2609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** @endverbatim +2610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @{ +2611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Update on the fly the receiver timeout value in RTOR register. +2615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart Pointer to a UART_HandleTypeDef structure that contains +2616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * the configuration information for the specified UART module. +2617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout +2618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * value must be less or equal to 0x0FFFFFFFF. +2619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +2620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) +2622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); +2624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); +2625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Enable the UART receiver timeout feature. +2629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart Pointer to a UART_HandleTypeDef structure that contains +2630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * the configuration information for the specified UART module. +2631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +2632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) +2634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_READY) +2636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Process Locked */ +2638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_LOCK(huart); +2639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; +2641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the USART RTOEN bit */ +2643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); +2644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Process Unlocked */ +2648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UNLOCK(huart); +2649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +2651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +2653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_BUSY; + ARM GAS /tmp/ccQxTlMj.s page 48 + + +2655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Disable the UART receiver timeout feature. +2660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart Pointer to a UART_HandleTypeDef structure that contains +2661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * the configuration information for the specified UART module. +2662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +2663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) +2665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_READY) +2667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Process Locked */ +2669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_LOCK(huart); +2670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; +2672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear the USART RTOEN bit */ +2674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); +2675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Process Unlocked */ +2679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UNLOCK(huart); +2680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +2682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +2684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_BUSY; +2686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Enable UART in mute mode (does not mean UART enters mute mode; +2691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). +2692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +2693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +2694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) +2696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_LOCK(huart); +2698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; +2700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable USART mute mode by setting the MME bit in the CR1 register */ +2702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME); +2703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return (UART_CheckIdleState(huart)); +2707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Disable UART mute mode (does not mean the UART actually exits mute mode +2711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * as it may not have been in mute mode at this very moment). + ARM GAS /tmp/ccQxTlMj.s page 49 + + +2712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +2713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +2714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) +2716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_LOCK(huart); +2718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; +2720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable USART mute mode by clearing the MME bit in the CR1 register */ +2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); +2723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return (UART_CheckIdleState(huart)); +2727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Enter UART mute mode (means UART actually enters mute mode). +2731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. +2732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +2733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +2734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +2736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); +2738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Enable the UART transmitter and disable the UART receiver. +2742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +2743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +2744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +2746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_LOCK(huart); +2748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; +2749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear TE and RE bits */ +2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); +2752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ +2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE); +2755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UNLOCK(huart); +2759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Enable the UART receiver and disable the UART transmitter. +2765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +2766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status. +2767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) + ARM GAS /tmp/ccQxTlMj.s page 50 + + +2769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_LOCK(huart); +2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; +2772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear TE and RE bits */ +2774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); +2775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ +2777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE); +2778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UNLOCK(huart); +2782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +2784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Transmit break characters. +2789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +2790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +2791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +2793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the parameters */ +2795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); +2796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_LOCK(huart); +2798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; +2800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Send break characters */ +2802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST); +2803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +2805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UNLOCK(huart); +2807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +2809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @} +2813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions +2816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief UART Peripheral State functions +2817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * +2818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** @verbatim +2819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ============================================================================== +2820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ##### Peripheral State and Error functions ##### +2821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ============================================================================== +2822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** [..] +2823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** This subsection provides functions allowing to : +2824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) Return the UART handle state. +2825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (+) Return the UART handle error code + ARM GAS /tmp/ccQxTlMj.s page 51 + + +2826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** @endverbatim +2828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @{ +2829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Return the UART handle state. +2833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart Pointer to a UART_HandleTypeDef structure that contains +2834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * the configuration information for the specified UART. +2835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL state +2836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) +2838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t temp1; +2840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t temp2; +2841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** temp1 = huart->gState; +2842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** temp2 = huart->RxState; +2843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return (HAL_UART_StateTypeDef)(temp1 | temp2); +2845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Return the UART handle error code. +2849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart Pointer to a UART_HandleTypeDef structure that contains +2850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * the configuration information for the specified UART. +2851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval UART Error Code +2852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) +2854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return huart->ErrorCode; +2856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @} +2859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @} +2863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** @defgroup UART_Private_Functions UART Private Functions +2866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @{ +2867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Initialize the callbacks to their default values. +2871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +2872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval none +2873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +2875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +2876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Init the UART Callback settings */ +2878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltC +2879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallb +2880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltC +2881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallb +2882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallba + ARM GAS /tmp/ccQxTlMj.s page 52 + + +2883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCa +2884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransm +2885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiv +2886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if defined(USART_CR1_UESM) +2887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if defined(USART_CR3_WUFIE) +2888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallb +2889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USART_CR3_WUFIE */ +2890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USART_CR1_UESM */ +2891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCall +2892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +2895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +2897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Configure the UART peripheral. +2898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +2899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +2900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +2901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +2902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t tmpreg; +2904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint16_t brrtemp; +2905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_ClockSourceTypeDef clocksource; +2906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t usartdiv; +2907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef ret = HAL_OK; +2908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t pclk; +2909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the parameters */ +2911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); +2912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); +2913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); +2914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); +2915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_PARITY(huart->Init.Parity)); +2917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_MODE(huart->Init.Mode)); +2918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); +2919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); +2920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*-------------------------- USART CR1 Configuration -----------------------*/ +2922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure +2923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * the UART Word Length, Parity, Mode and oversampling: +2924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * set the M bits according to huart->Init.WordLength value +2925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * set PCE and PS bits according to huart->Init.Parity value +2926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * set TE and RE bits according to huart->Init.Mode value +2927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * set OVER8 bit according to huart->Init.OverSampling value */ +2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.O +2929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); +2930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*-------------------------- USART CR2 Configuration -----------------------*/ +2932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Configure the UART Stop Bits: Set STOP[13:12] bits according +2933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * to huart->Init.StopBits value */ +2934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); +2935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*-------------------------- USART CR3 Configuration -----------------------*/ +2937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Configure +2938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - UART HardWare Flow Control: set CTSE and RTSE bits according +2939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * to huart->Init.HwFlowCtl value + ARM GAS /tmp/ccQxTlMj.s page 53 + + +2940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * - one-bit sampling method versus three samples' majority rule according +2941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * to huart->Init.OneBitSampling (not applicable to LPUART) */ +2942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** tmpreg = (uint32_t)huart->Init.HwFlowCtl; +2943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** tmpreg |= huart->Init.OneBitSampling; +2945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); +2946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*-------------------------- USART BRR Configuration -----------------------*/ +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_GETCLOCKSOURCE(huart, clocksource); +2950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->Init.OverSampling == UART_OVERSAMPLING_8) +2952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** switch (clocksource) +2954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case UART_CLOCKSOURCE_PCLK1: +2956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pclk = HAL_RCC_GetPCLK1Freq(); +2957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; +2958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case UART_CLOCKSOURCE_PCLK2: +2959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pclk = HAL_RCC_GetPCLK2Freq(); +2960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; +2961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case UART_CLOCKSOURCE_HSI: +2962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pclk = (uint32_t) HSI_VALUE; +2963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; +2964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case UART_CLOCKSOURCE_SYSCLK: +2965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pclk = HAL_RCC_GetSysClockFreq(); +2966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; +2967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case UART_CLOCKSOURCE_LSE: +2968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pclk = (uint32_t) LSE_VALUE; +2969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; +2970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** default: +2971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pclk = 0U; +2972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ret = HAL_ERROR; +2973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; +2974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +2976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* USARTDIV must be greater than or equal to 0d16 */ +2977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (pclk != 0U) +2978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); +2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) +2981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** brrtemp = (uint16_t)(usartdiv & 0xFFF0U); +2983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); +2984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->BRR = brrtemp; +2985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +2987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ret = HAL_ERROR; +2989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +2992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +2993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** switch (clocksource) +2995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +2996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case UART_CLOCKSOURCE_PCLK1: + ARM GAS /tmp/ccQxTlMj.s page 54 + + +2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pclk = HAL_RCC_GetPCLK1Freq(); +2998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; +2999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case UART_CLOCKSOURCE_PCLK2: +3000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pclk = HAL_RCC_GetPCLK2Freq(); +3001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; +3002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case UART_CLOCKSOURCE_HSI: +3003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pclk = (uint32_t) HSI_VALUE; +3004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; +3005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case UART_CLOCKSOURCE_SYSCLK: +3006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pclk = HAL_RCC_GetSysClockFreq(); +3007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; +3008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case UART_CLOCKSOURCE_LSE: +3009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pclk = (uint32_t) LSE_VALUE; +3010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; +3011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** default: +3012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pclk = 0U; +3013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ret = HAL_ERROR; +3014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; +3015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (pclk != 0U) +3018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* USARTDIV must be greater than or equal to 0d16 */ +3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); +3021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) +3022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->BRR = (uint16_t)usartdiv; +3024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +3026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ret = HAL_ERROR; +3028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear ISR function pointers */ +3034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxISR = NULL; +3035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxISR = NULL; +3036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return ret; +3038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Configure the UART peripheral advanced features. +3042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +3043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +3044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +3046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check whether the set of advanced features to configure is properly set */ +3048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); +3049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* if required, configure RX/TX pins swap */ +3051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) +3052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + ARM GAS /tmp/ccQxTlMj.s page 55 + + +3054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); +3055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* if required, configure TX pin active level inversion */ +3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) +3059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); +3061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); +3062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* if required, configure RX pin active level inversion */ +3065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) +3066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); +3068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); +3069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* if required, configure data inversion */ +3072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) +3073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); +3075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); +3076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* if required, configure RX overrun detection disabling */ +3079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) +3080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); +3082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); +3083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* if required, configure DMA disabling on reception error */ +3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) +3087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); +3089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); +3090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* if required, configure auto Baud rate detection scheme */ +3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) +3094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); +3096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); +3097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); +3098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* set auto Baudrate detection parameters if detection is enabled */ +3099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) +3100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); +3102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); +3103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* if required, configure MSB first on communication line */ +3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) +3108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); +3110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + ARM GAS /tmp/ccQxTlMj.s page 56 + + +3111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Check the UART Idle State. +3116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +3117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +3118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +3120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t tickstart; +3122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Initialize the UART ErrorCode */ +3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +3125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Init tickstart for timeout management */ +3127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** tickstart = HAL_GetTick(); +3128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check if the Transmitter is enabled */ +3130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) +3131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Wait until TEACK flag is set */ +3133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALU +3134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable TXE interrupt for the interrupt process */ +3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE)); +3137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +3139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UNLOCK(huart); +3141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Timeout occurred */ +3143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_TIMEOUT; +3144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if defined(USART_ISR_REACK) +3147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check if the Receiver is enabled */ +3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) +3150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Wait until REACK flag is set */ +3152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALU +3153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) +3155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** interrupts for the interrupt process */ +3156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +3157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +3158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +3160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UNLOCK(huart); +3162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Timeout occurred */ +3164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_TIMEOUT; +3165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USART_ISR_REACK */ + ARM GAS /tmp/ccQxTlMj.s page 57 + + +3168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Initialize the UART State */ +3170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +3171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +3172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +3173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; +3174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UNLOCK(huart); +3176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +3178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief This function handles UART Communication Timeout. It waits +3182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * until a flag is no longer in the specified status. +3183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +3184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param Flag Specifies the UART flag to check +3185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param Status The actual Flag status (SET or RESET) +3186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param Tickstart Tick start value +3187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param Timeout Timeout duration +3188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +3189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus +3191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t Tickstart, uint32_t Timeout) +3192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Wait until flag is set */ +3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) +3195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check for the Timeout */ +3197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (Timeout != HAL_MAX_DELAY) +3198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +3200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_TIMEOUT; +3203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag +3206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) +3208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear Overrun Error flag*/ +3210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); +3211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Blocking error : transfer is aborted +3213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** Set the UART state ready to be able to start again the process, +3214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** Disable Rx Interrupts if ongoing */ +3215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_EndRxTransfer(huart); +3216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_ORE; +3218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Process Unlocked */ +3220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UNLOCK(huart); +3221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; +3223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + ARM GAS /tmp/ccQxTlMj.s page 58 + + +3225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear Receiver Timeout flag*/ +3227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); +3228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Blocking error : transfer is aborted +3230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** Set the UART state ready to be able to start again the process, +3231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** Disable Rx Interrupts if ongoing */ +3232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_EndRxTransfer(huart); +3233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_RTO; +3235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Process Unlocked */ +3237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UNLOCK(huart); +3238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_TIMEOUT; +3240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +3245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Start Receive operation in interrupt mode. +3249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note This function could be called by all HAL UART API providing reception in Interrupt mode +3250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note When calling this function, parameters validity is considered as already checked, +3251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * i.e. Rx State, buffer address, ... +3252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * UART Handle is assumed as Locked. +3253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +3254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param pData Pointer to data buffer (u8 or u16 data elements). +3255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param Size Amount of data elements (u8 or u16) to be received. +3256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +3257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +3259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pRxBuffPtr = pData; +3261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferSize = Size; +3262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = Size; +3263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxISR = NULL; +3264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Computation of UART mask to apply to RDR register */ +3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_MASK_COMPUTATION(huart); +3267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +3269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; +3270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ +3272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); +3273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the Rx ISR function pointer according to the data word length */ +3275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) +3276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxISR = UART_RxISR_16BIT; +3278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +3280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxISR = UART_RxISR_8BIT; + ARM GAS /tmp/ccQxTlMj.s page 59 + + +3282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ +3285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->Init.Parity != UART_PARITY_NONE) +3286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); +3288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +3290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE); +3292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +3294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Start Receive operation in DMA mode. +3298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note This function could be called by all HAL UART API providing reception in DMA mode. +3299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note When calling this function, parameters validity is considered as already checked, +3300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * i.e. Rx State, buffer address, ... +3301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * UART Handle is assumed as Locked. +3302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +3303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param pData Pointer to data buffer (u8 or u16 data elements). +3304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param Size Amount of data elements (u8 or u16) to be received. +3305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval HAL status +3306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +3308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pRxBuffPtr = pData; +3310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferSize = Size; +3311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +3313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; +3314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmarx != NULL) +3316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the UART DMA transfer complete callback */ +3318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; +3319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the UART DMA Half transfer complete callback */ +3321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; +3322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the DMA error callback */ +3324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmarx->XferErrorCallback = UART_DMAError; +3325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set the DMA abort callback */ +3327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = NULL; +3328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the DMA channel */ +3330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPt +3331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set error code to DMA */ +3333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_DMA; +3334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Restore huart->RxState to ready */ +3336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +3337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_ERROR; + ARM GAS /tmp/ccQxTlMj.s page 60 + + +3339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the UART Parity Error Interrupt */ +3343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->Init.Parity != UART_PARITY_NONE) +3344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); +3346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ +3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); +3350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the DMA transfer for the receiver request by setting the DMAR bit +3352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** in the UART CR3 register */ +3353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); +3354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return HAL_OK; +3356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit compl +3361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +3362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +3363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +3365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 27 .loc 1 3365 1 view -0 + 28 .cfi_startproc + 29 @ args = 0, pretend = 0, frame = 0 + 30 @ frame_needed = 0, uses_anonymous_args = 0 + 31 @ link register save eliminated. + 32 .LVL0: + 33 .L2: +3366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable TXEIE and TCIE interrupts */ +3367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + 34 .loc 1 3367 3 discriminator 1 view .LVU1 + 35 .LBB414: + 36 .loc 1 3367 3 discriminator 1 view .LVU2 + 37 .loc 1 3367 3 discriminator 1 view .LVU3 + 38 .loc 1 3367 3 discriminator 1 view .LVU4 + 39 0000 0268 ldr r2, [r0] + 40 .LVL1: + 41 .LBB415: + 42 .LBI415: + 43 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + ARM GAS /tmp/ccQxTlMj.s page 61 + + + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + ARM GAS /tmp/ccQxTlMj.s page 62 + + + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + ARM GAS /tmp/ccQxTlMj.s page 63 + + + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccQxTlMj.s page 64 + + + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccQxTlMj.s page 65 + + + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccQxTlMj.s page 66 + + + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + ARM GAS /tmp/ccQxTlMj.s page 67 + + + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + ARM GAS /tmp/ccQxTlMj.s page 68 + + + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccQxTlMj.s page 69 + + + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + ARM GAS /tmp/ccQxTlMj.s page 70 + + + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + ARM GAS /tmp/ccQxTlMj.s page 71 + + + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccQxTlMj.s page 72 + + + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + ARM GAS /tmp/ccQxTlMj.s page 73 + + + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + ARM GAS /tmp/ccQxTlMj.s page 74 + + + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccQxTlMj.s page 75 + + + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + ARM GAS /tmp/ccQxTlMj.s page 76 + + + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 881:Drivers/CMSIS/Include/cmsis_gcc.h **** + 882:Drivers/CMSIS/Include/cmsis_gcc.h **** + 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier + 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. + 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) + 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); + 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 892:Drivers/CMSIS/Include/cmsis_gcc.h **** + 893:Drivers/CMSIS/Include/cmsis_gcc.h **** + 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) + 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 + 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) + 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); + 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 906:Drivers/CMSIS/Include/cmsis_gcc.h **** + 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 911:Drivers/CMSIS/Include/cmsis_gcc.h **** + 912:Drivers/CMSIS/Include/cmsis_gcc.h **** + 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes + 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) + 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 922:Drivers/CMSIS/Include/cmsis_gcc.h **** + 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + ARM GAS /tmp/ccQxTlMj.s page 77 + + + 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 926:Drivers/CMSIS/Include/cmsis_gcc.h **** + 927:Drivers/CMSIS/Include/cmsis_gcc.h **** + 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam + 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); + 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; + 940:Drivers/CMSIS/Include/cmsis_gcc.h **** + 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 945:Drivers/CMSIS/Include/cmsis_gcc.h **** + 946:Drivers/CMSIS/Include/cmsis_gcc.h **** + 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) + 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v + 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate + 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate + 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value + 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) + 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; + 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) + 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; + 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); + 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 963:Drivers/CMSIS/Include/cmsis_gcc.h **** + 964:Drivers/CMSIS/Include/cmsis_gcc.h **** + 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint + 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. + 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula + 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. + 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break + 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) + 973:Drivers/CMSIS/Include/cmsis_gcc.h **** + 974:Drivers/CMSIS/Include/cmsis_gcc.h **** + 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value + 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. + 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccQxTlMj.s page 78 + + + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) + 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 984:Drivers/CMSIS/Include/cmsis_gcc.h **** + 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + 991:Drivers/CMSIS/Include/cmsis_gcc.h **** + 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ + 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) + 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; + 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; + 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; + 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ +1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; +1002:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1003:Drivers/CMSIS/Include/cmsis_gcc.h **** +1004:Drivers/CMSIS/Include/cmsis_gcc.h **** +1005:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1006:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Count leading zeros +1007:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Counts the number of leading zeros of a data value. +1008:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to count the leading zeros +1009:Drivers/CMSIS/Include/cmsis_gcc.h **** \return number of leading zeros in value +1010:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1011:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CLZ (uint8_t)__builtin_clz +1012:Drivers/CMSIS/Include/cmsis_gcc.h **** +1013:Drivers/CMSIS/Include/cmsis_gcc.h **** +1014:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +1015:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ +1016:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ +1017:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +1018:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1019:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (8 bit) +1020:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 8 bit value. +1021:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data +1022:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) +1023:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1024:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +1025:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1026:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; +1027:Drivers/CMSIS/Include/cmsis_gcc.h **** +1028:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) +1029:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +1030:Drivers/CMSIS/Include/cmsis_gcc.h **** #else +1031:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not +1032:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. +1033:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1034:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +1035:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1036:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */ +1037:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccQxTlMj.s page 79 + + +1038:Drivers/CMSIS/Include/cmsis_gcc.h **** +1039:Drivers/CMSIS/Include/cmsis_gcc.h **** +1040:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1041:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (16 bit) +1042:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 16 bit values. +1043:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data +1044:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) +1045:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1046:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +1047:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1048:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; +1049:Drivers/CMSIS/Include/cmsis_gcc.h **** +1050:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) +1051:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +1052:Drivers/CMSIS/Include/cmsis_gcc.h **** #else +1053:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not +1054:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. +1055:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1056:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +1057:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1058:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */ +1059:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1060:Drivers/CMSIS/Include/cmsis_gcc.h **** +1061:Drivers/CMSIS/Include/cmsis_gcc.h **** +1062:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1063:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (32 bit) +1064:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 32 bit values. +1065:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data +1066:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) +1067:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) + 44 .loc 2 1068 31 view .LVU5 + 45 .LBB416: +1069:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 46 .loc 2 1070 5 view .LVU6 +1071:Drivers/CMSIS/Include/cmsis_gcc.h **** +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 47 .loc 2 1072 4 view .LVU7 + 48 .syntax unified + 49 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 50 0002 52E8003F ldrex r3, [r2] + 51 @ 0 "" 2 + 52 .LVL2: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 53 .loc 2 1073 4 view .LVU8 + 54 .loc 2 1073 4 is_stmt 0 view .LVU9 + 55 .thumb + 56 .syntax unified + 57 .LBE416: + 58 .LBE415: + 59 .loc 1 3367 3 discriminator 1 view .LVU10 + 60 0006 23F0C003 bic r3, r3, #192 + 61 .LVL3: + 62 .loc 1 3367 3 is_stmt 1 discriminator 1 view .LVU11 + 63 .LBB417: + 64 .LBI417: + ARM GAS /tmp/ccQxTlMj.s page 80 + + +1074:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1075:Drivers/CMSIS/Include/cmsis_gcc.h **** +1076:Drivers/CMSIS/Include/cmsis_gcc.h **** +1077:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1078:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (8 bit) +1079:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 8 bit values. +1080:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store +1081:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location +1082:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded +1083:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed +1084:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1085:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +1086:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1087:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; +1088:Drivers/CMSIS/Include/cmsis_gcc.h **** +1089:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); +1090:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); +1091:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1092:Drivers/CMSIS/Include/cmsis_gcc.h **** +1093:Drivers/CMSIS/Include/cmsis_gcc.h **** +1094:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1095:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (16 bit) +1096:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 16 bit values. +1097:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store +1098:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location +1099:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded +1100:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed +1101:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1102:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +1103:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1104:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; +1105:Drivers/CMSIS/Include/cmsis_gcc.h **** +1106:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); +1107:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); +1108:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1109:Drivers/CMSIS/Include/cmsis_gcc.h **** +1110:Drivers/CMSIS/Include/cmsis_gcc.h **** +1111:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1112:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (32 bit) +1113:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 32 bit values. +1114:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store +1115:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location +1116:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded +1117:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed +1118:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) + 65 .loc 2 1119 31 view .LVU12 + 66 .LBB418: +1120:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 67 .loc 2 1121 4 view .LVU13 +1122:Drivers/CMSIS/Include/cmsis_gcc.h **** +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 68 .loc 2 1123 4 view .LVU14 + 69 .syntax unified + 70 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 71 000a 42E80031 strex r1, r3, [r2] + ARM GAS /tmp/ccQxTlMj.s page 81 + + + 72 @ 0 "" 2 + 73 .LVL4: +1124:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 74 .loc 2 1124 4 view .LVU15 + 75 .loc 2 1124 4 is_stmt 0 view .LVU16 + 76 .thumb + 77 .syntax unified + 78 .LBE418: + 79 .LBE417: + 80 .loc 1 3367 3 discriminator 1 view .LVU17 + 81 000e 0029 cmp r1, #0 + 82 0010 F6D1 bne .L2 + 83 .LBE414: + 84 .loc 1 3367 3 is_stmt 1 discriminator 2 view .LVU18 +3368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* At end of Tx process, restore huart->gState to Ready */ +3370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; + 85 .loc 1 3370 3 view .LVU19 + 86 .loc 1 3370 17 is_stmt 0 view .LVU20 + 87 0012 2023 movs r3, #32 + 88 .LVL5: + 89 .loc 1 3370 17 view .LVU21 + 90 0014 C367 str r3, [r0, #124] +3371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 91 .loc 1 3371 1 view .LVU22 + 92 0016 7047 bx lr + 93 .cfi_endproc + 94 .LFE191: + 96 .section .text.UART_EndRxTransfer,"ax",%progbits + 97 .align 1 + 98 .syntax unified + 99 .thumb + 100 .thumb_func + 102 UART_EndRxTransfer: + 103 .LFB192: +3372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception comp +3376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +3377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +3378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +3380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 104 .loc 1 3380 1 is_stmt 1 view -0 + 105 .cfi_startproc + 106 @ args = 0, pretend = 0, frame = 0 + 107 @ frame_needed = 0, uses_anonymous_args = 0 + 108 @ link register save eliminated. + 109 .LVL6: + 110 .L4: +3381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ +3382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + 111 .loc 1 3382 3 discriminator 1 view .LVU24 + 112 .LBB419: + 113 .loc 1 3382 3 discriminator 1 view .LVU25 + 114 .loc 1 3382 3 discriminator 1 view .LVU26 + ARM GAS /tmp/ccQxTlMj.s page 82 + + + 115 .loc 1 3382 3 discriminator 1 view .LVU27 + 116 0000 0268 ldr r2, [r0] + 117 .LVL7: + 118 .LBB420: + 119 .LBI420: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 120 .loc 2 1068 31 view .LVU28 + 121 .LBB421: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 122 .loc 2 1070 5 view .LVU29 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 123 .loc 2 1072 4 view .LVU30 + 124 .syntax unified + 125 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 126 0002 52E8003F ldrex r3, [r2] + 127 @ 0 "" 2 + 128 .LVL8: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 129 .loc 2 1073 4 view .LVU31 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 130 .loc 2 1073 4 is_stmt 0 view .LVU32 + 131 .thumb + 132 .syntax unified + 133 .LBE421: + 134 .LBE420: + 135 .loc 1 3382 3 discriminator 1 view .LVU33 + 136 0006 23F49073 bic r3, r3, #288 + 137 .LVL9: + 138 .loc 1 3382 3 is_stmt 1 discriminator 1 view .LVU34 + 139 .LBB422: + 140 .LBI422: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 141 .loc 2 1119 31 view .LVU35 + 142 .LBB423: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 143 .loc 2 1121 4 view .LVU36 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 144 .loc 2 1123 4 view .LVU37 + 145 .syntax unified + 146 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 147 000a 42E80031 strex r1, r3, [r2] + 148 @ 0 "" 2 + 149 .LVL10: + 150 .loc 2 1124 4 view .LVU38 + 151 .loc 2 1124 4 is_stmt 0 view .LVU39 + 152 .thumb + 153 .syntax unified + 154 .LBE423: + 155 .LBE422: + 156 .loc 1 3382 3 discriminator 1 view .LVU40 + 157 000e 0029 cmp r1, #0 + 158 0010 F6D1 bne .L4 + 159 .LVL11: + 160 .L5: + 161 .loc 1 3382 3 discriminator 1 view .LVU41 + 162 .LBE419: + 163 .loc 1 3382 3 is_stmt 1 discriminator 2 view .LVU42 + ARM GAS /tmp/ccQxTlMj.s page 83 + + +3383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 164 .loc 1 3383 3 discriminator 1 view .LVU43 + 165 .LBB424: + 166 .loc 1 3383 3 discriminator 1 view .LVU44 + 167 .loc 1 3383 3 discriminator 1 view .LVU45 + 168 .loc 1 3383 3 discriminator 1 view .LVU46 + 169 0012 0268 ldr r2, [r0] + 170 .LVL12: + 171 .LBB425: + 172 .LBI425: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 173 .loc 2 1068 31 view .LVU47 + 174 .LBB426: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175 .loc 2 1070 5 view .LVU48 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 176 .loc 2 1072 4 view .LVU49 + 177 0014 02F10803 add r3, r2, #8 + 178 .LVL13: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 179 .loc 2 1072 4 is_stmt 0 view .LVU50 + 180 .syntax unified + 181 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 182 0018 53E8003F ldrex r3, [r3] + 183 @ 0 "" 2 + 184 .LVL14: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185 .loc 2 1073 4 is_stmt 1 view .LVU51 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 186 .loc 2 1073 4 is_stmt 0 view .LVU52 + 187 .thumb + 188 .syntax unified + 189 .LBE426: + 190 .LBE425: + 191 .loc 1 3383 3 discriminator 1 view .LVU53 + 192 001c 23F00103 bic r3, r3, #1 + 193 .LVL15: + 194 .loc 1 3383 3 is_stmt 1 discriminator 1 view .LVU54 + 195 .LBB427: + 196 .LBI427: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 197 .loc 2 1119 31 view .LVU55 + 198 .LBB428: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199 .loc 2 1121 4 view .LVU56 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 200 .loc 2 1123 4 view .LVU57 + 201 0020 0832 adds r2, r2, #8 + 202 .LVL16: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 203 .loc 2 1123 4 is_stmt 0 view .LVU58 + 204 .syntax unified + 205 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 206 0022 42E80031 strex r1, r3, [r2] + 207 @ 0 "" 2 + 208 .LVL17: + 209 .loc 2 1124 4 is_stmt 1 view .LVU59 + ARM GAS /tmp/ccQxTlMj.s page 84 + + + 210 .loc 2 1124 4 is_stmt 0 view .LVU60 + 211 .thumb + 212 .syntax unified + 213 .LBE428: + 214 .LBE427: + 215 .loc 1 3383 3 discriminator 1 view .LVU61 + 216 0026 0029 cmp r1, #0 + 217 0028 F3D1 bne .L5 + 218 .LBE424: + 219 .loc 1 3383 3 is_stmt 1 discriminator 2 view .LVU62 +3384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ +3386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 220 .loc 1 3386 3 view .LVU63 + 221 .loc 1 3386 12 is_stmt 0 view .LVU64 + 222 002a 036E ldr r3, [r0, #96] + 223 .LVL18: + 224 .loc 1 3386 6 view .LVU65 + 225 002c 012B cmp r3, #1 + 226 002e 06D0 beq .L7 + 227 .L6: +3387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 228 .loc 1 3388 5 is_stmt 1 discriminator 2 view .LVU66 +3389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* At end of Rx process, restore huart->RxState to Ready */ +3392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 229 .loc 1 3392 3 view .LVU67 + 230 .loc 1 3392 18 is_stmt 0 view .LVU68 + 231 0030 2023 movs r3, #32 + 232 0032 C0F88030 str r3, [r0, #128] +3393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 233 .loc 1 3393 3 is_stmt 1 view .LVU69 + 234 .loc 1 3393 24 is_stmt 0 view .LVU70 + 235 0036 0023 movs r3, #0 + 236 0038 0366 str r3, [r0, #96] +3394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Reset RxIsr function pointer */ +3396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxISR = NULL; + 237 .loc 1 3396 3 is_stmt 1 view .LVU71 + 238 .loc 1 3396 16 is_stmt 0 view .LVU72 + 239 003a 8366 str r3, [r0, #104] +3397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 240 .loc 1 3397 1 view .LVU73 + 241 003c 7047 bx lr + 242 .L7: +3388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 243 .loc 1 3388 5 is_stmt 1 discriminator 1 view .LVU74 + 244 .LBB429: +3388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 245 .loc 1 3388 5 discriminator 1 view .LVU75 +3388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 246 .loc 1 3388 5 discriminator 1 view .LVU76 +3388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 247 .loc 1 3388 5 discriminator 1 view .LVU77 + 248 003e 0268 ldr r2, [r0] + ARM GAS /tmp/ccQxTlMj.s page 85 + + + 249 .LVL19: + 250 .LBB430: + 251 .LBI430: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 252 .loc 2 1068 31 view .LVU78 + 253 .LBB431: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 254 .loc 2 1070 5 view .LVU79 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 255 .loc 2 1072 4 view .LVU80 + 256 .syntax unified + 257 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 258 0040 52E8003F ldrex r3, [r2] + 259 @ 0 "" 2 + 260 .LVL20: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 261 .loc 2 1073 4 view .LVU81 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 262 .loc 2 1073 4 is_stmt 0 view .LVU82 + 263 .thumb + 264 .syntax unified + 265 .LBE431: + 266 .LBE430: +3388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 267 .loc 1 3388 5 discriminator 1 view .LVU83 + 268 0044 23F01003 bic r3, r3, #16 + 269 .LVL21: +3388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 270 .loc 1 3388 5 is_stmt 1 discriminator 1 view .LVU84 + 271 .LBB432: + 272 .LBI432: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 273 .loc 2 1119 31 view .LVU85 + 274 .LBB433: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 275 .loc 2 1121 4 view .LVU86 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 276 .loc 2 1123 4 view .LVU87 + 277 .syntax unified + 278 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 279 0048 42E80031 strex r1, r3, [r2] + 280 @ 0 "" 2 + 281 .LVL22: + 282 .loc 2 1124 4 view .LVU88 + 283 .loc 2 1124 4 is_stmt 0 view .LVU89 + 284 .thumb + 285 .syntax unified + 286 .LBE433: + 287 .LBE432: +3388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 288 .loc 1 3388 5 discriminator 1 view .LVU90 + 289 004c 0029 cmp r1, #0 + 290 004e F6D1 bne .L7 + 291 0050 EEE7 b .L6 + 292 .LBE429: + 293 .cfi_endproc + 294 .LFE192: + ARM GAS /tmp/ccQxTlMj.s page 86 + + + 296 .section .text.UART_TxISR_8BIT,"ax",%progbits + 297 .align 1 + 298 .syntax unified + 299 .thumb + 300 .thumb_func + 302 UART_TxISR_8BIT: + 303 .LVL23: + 304 .LFB203: +3398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief DMA UART transmit process complete callback. +3402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param hdma DMA handle. +3403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +3404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +3406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); +3408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* DMA Normal mode */ +3410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (hdma->Init.Mode != DMA_CIRCULAR) +3411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = 0U; +3413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the DMA transfer for transmit request by resetting the DMAT bit +3415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** in the UART CR3 register */ +3416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); +3417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the UART Transmit Complete Interrupt */ +3419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); +3420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* DMA Circular mode */ +3422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +3423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call registered Tx complete callback*/ +3426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxCpltCallback(huart); +3427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +3428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call legacy weak Tx complete callback*/ +3429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_TxCpltCallback(huart); +3430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief DMA UART transmit process half complete callback. +3436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param hdma DMA handle. +3437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +3438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +3440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); +3442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call registered Tx Half complete callback*/ +3445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxHalfCpltCallback(huart); +3446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else + ARM GAS /tmp/ccQxTlMj.s page 87 + + +3447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call legacy weak Tx Half complete callback*/ +3448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_TxHalfCpltCallback(huart); +3449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief DMA UART receive process complete callback. +3454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param hdma DMA handle. +3455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +3456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +3458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); +3460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* DMA Normal mode */ +3462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (hdma->Init.Mode != DMA_CIRCULAR) +3463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; +3465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ +3467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); +3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +3469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the DMA transfer for the receiver request by resetting the DMAR bit +3471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** in the UART CR3 register */ +3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); +3473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* At end of Rx process, restore huart->RxState to Ready */ +3475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +3476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ +3478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) +3479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); +3481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Initialize type of RxEvent that correspond to RxEvent callback execution; +3485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** In this case, Rx Event type is Transfer Complete */ +3486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; +3487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check current reception Mode : +3489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** If Reception till IDLE event has been selected : use Rx Event callback */ +3490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) +3491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call registered Rx Event callback*/ +3494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventCallback(huart, huart->RxXferSize); +3495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +3496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call legacy weak Rx Event callback*/ +3497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +3498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +3501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* In other cases : use Rx Complete callback */ +3503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + ARM GAS /tmp/ccQxTlMj.s page 88 + + +3504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call registered Rx complete callback*/ +3505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxCpltCallback(huart); +3506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +3507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call legacy weak Rx complete callback*/ +3508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_RxCpltCallback(huart); +3509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief DMA UART receive process half complete callback. +3515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param hdma DMA handle. +3516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +3517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +3519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); +3521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Initialize type of RxEvent that correspond to RxEvent callback execution; +3523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** In this case, Rx Event type is Half Transfer */ +3524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventType = HAL_UART_RXEVENT_HT; +3525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check current reception Mode : +3527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** If Reception till IDLE event has been selected : use Rx Event callback */ +3528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) +3529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call registered Rx Event callback*/ +3532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventCallback(huart, huart->RxXferSize / 2U); +3533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +3534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call legacy weak Rx Event callback*/ +3535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); +3536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +3539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* In other cases : use Rx Half Complete callback */ +3541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call registered Rx Half complete callback*/ +3543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxHalfCpltCallback(huart); +3544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +3545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call legacy weak Rx Half complete callback*/ +3546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_RxHalfCpltCallback(huart); +3547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief DMA UART communication error callback. +3553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param hdma DMA handle. +3554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +3555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** static void UART_DMAError(DMA_HandleTypeDef *hdma) +3557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); +3559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const HAL_UART_StateTypeDef gstate = huart->gState; + ARM GAS /tmp/ccQxTlMj.s page 89 + + +3561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const HAL_UART_StateTypeDef rxstate = huart->RxState; +3562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Stop UART DMA Tx request if ongoing */ +3564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && +3565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) +3566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = 0U; +3568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_EndTxTransfer(huart); +3569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Stop UART DMA Rx request if ongoing */ +3572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && +3573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) +3574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; +3576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_EndRxTransfer(huart); +3577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode |= HAL_UART_ERROR_DMA; +3580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call registered error callback*/ +3583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCallback(huart); +3584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +3585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call legacy weak error callback*/ +3586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_ErrorCallback(huart); +3587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief DMA UART communication abort callback, when initiated by HAL services on Error +3592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * (To be called at end of DMA Abort procedure following error occurrence). +3593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param hdma DMA handle. +3594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +3595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +3597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); +3599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; +3600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = 0U; +3601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call registered error callback*/ +3604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCallback(huart); +3605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +3606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call legacy weak error callback*/ +3607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_ErrorCallback(huart); +3608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief DMA UART Tx communication abort callback, when initiated by user +3613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * (To be called at end of DMA Tx Abort procedure following user abort request). +3614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note When this callback is executed, User Abort complete call back is called only if no +3615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * Abort still ongoing for Rx DMA Handle. +3616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param hdma DMA handle. +3617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None + ARM GAS /tmp/ccQxTlMj.s page 90 + + +3618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +3620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); +3622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmatx->XferAbortCallback = NULL; +3624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check if an Abort process is still ongoing */ +3626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmarx != NULL) +3627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmarx->XferAbortCallback != NULL) +3629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return; +3631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callba +3635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = 0U; +3636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; +3637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Reset errorCode */ +3639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +3640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +3642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); +3643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Restore huart->gState and huart->RxState to Ready */ +3646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +3647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +3648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +3649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call user Abort complete callback */ +3651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call registered Abort complete callback */ +3653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->AbortCpltCallback(huart); +3654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +3655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call legacy weak Abort complete callback */ +3656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_AbortCpltCallback(huart); +3657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief DMA UART Rx communication abort callback, when initiated by user +3663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * (To be called at end of DMA Rx Abort procedure following user abort request). +3664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note When this callback is executed, User Abort complete call back is called only if no +3665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * Abort still ongoing for Tx DMA Handle. +3666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param hdma DMA handle. +3667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +3668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +3670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); +3672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->hdmarx->XferAbortCallback = NULL; +3674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 91 + + +3675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check if an Abort process is still ongoing */ +3676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmatx != NULL) +3677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->hdmatx->XferAbortCallback != NULL) +3679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return; +3681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callba +3685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = 0U; +3686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; +3687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Reset errorCode */ +3689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; +3690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +3692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); +3693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Discard the received data */ +3695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); +3696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Restore huart->gState and huart->RxState to Ready */ +3698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +3699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +3700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +3701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call user Abort complete callback */ +3703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call registered Abort complete callback */ +3705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->AbortCpltCallback(huart); +3706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +3707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call legacy weak Abort complete callback */ +3708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_AbortCpltCallback(huart); +3709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief DMA UART Tx communication abort callback, when initiated by user by a call to +3715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) +3716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * (This callback is executed at end of DMA Tx Abort procedure following user abort reques +3717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * and leads to user Tx Abort Complete callback execution). +3718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param hdma DMA handle. +3719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +3720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +3722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); +3724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = 0U; +3726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Restore huart->gState to Ready */ +3729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; +3730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call user Abort complete callback */ + ARM GAS /tmp/ccQxTlMj.s page 92 + + +3732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call registered Abort Transmit Complete Callback */ +3734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->AbortTransmitCpltCallback(huart); +3735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +3736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call legacy weak Abort Transmit Complete Callback */ +3737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_AbortTransmitCpltCallback(huart); +3738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief DMA UART Rx communication abort callback, when initiated by user by a call to +3743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) +3744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * (This callback is executed at end of DMA Rx Abort procedure following user abort reques +3745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * and leads to user Rx Abort Complete callback execution). +3746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param hdma DMA handle. +3747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +3748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +3750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; +3752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; +3754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear the Error flags in the ICR register */ +3756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); +3757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Discard the received data */ +3759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); +3760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Restore huart->RxState to Ready */ +3762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +3763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +3764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call user Abort complete callback */ +3766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call registered Abort Receive Complete Callback */ +3768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->AbortReceiveCpltCallback(huart); +3769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +3770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Call legacy weak Abort Receive Complete Callback */ +3771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_AbortReceiveCpltCallback(huart); +3772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief TX interrupt handler for 7 or 8 bits data word length . +3777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note Function is called under interruption only, once +3778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * interruptions have been enabled by HAL_UART_Transmit_IT(). +3779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +3780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +3781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) +3783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 305 .loc 1 3783 1 is_stmt 1 view -0 + 306 .cfi_startproc + 307 @ args = 0, pretend = 0, frame = 0 + 308 @ frame_needed = 0, uses_anonymous_args = 0 + 309 @ link register save eliminated. + ARM GAS /tmp/ccQxTlMj.s page 93 + + +3784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that a Tx process is ongoing */ +3785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_BUSY_TX) + 310 .loc 1 3785 3 view .LVU92 + 311 .loc 1 3785 12 is_stmt 0 view .LVU93 + 312 0000 C36F ldr r3, [r0, #124] + 313 .loc 1 3785 6 view .LVU94 + 314 0002 212B cmp r3, #33 + 315 0004 00D0 beq .L13 + 316 .L8: +3786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->TxXferCount == 0U) +3788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the UART Transmit Data Register Empty Interrupt */ +3790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); +3791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the UART Transmit Complete Interrupt */ +3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); +3794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +3796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); +3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pTxBuffPtr++; +3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount--; +3800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 317 .loc 1 3802 1 view .LVU95 + 318 0006 7047 bx lr + 319 .L13: +3787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 320 .loc 1 3787 5 is_stmt 1 view .LVU96 +3787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 321 .loc 1 3787 14 is_stmt 0 view .LVU97 + 322 0008 B0F85230 ldrh r3, [r0, #82] + 323 000c 9BB2 uxth r3, r3 +3787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 324 .loc 1 3787 8 view .LVU98 + 325 000e 93B9 cbnz r3, .L10 + 326 .L11: +3790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 327 .loc 1 3790 7 is_stmt 1 discriminator 1 view .LVU99 + 328 .LBB434: +3790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 329 .loc 1 3790 7 discriminator 1 view .LVU100 +3790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 330 .loc 1 3790 7 discriminator 1 view .LVU101 +3790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 331 .loc 1 3790 7 discriminator 1 view .LVU102 + 332 0010 0268 ldr r2, [r0] + 333 .LVL24: + 334 .LBB435: + 335 .LBI435: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 336 .loc 2 1068 31 view .LVU103 + 337 .LBB436: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 338 .loc 2 1070 5 view .LVU104 + ARM GAS /tmp/ccQxTlMj.s page 94 + + +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 339 .loc 2 1072 4 view .LVU105 + 340 .syntax unified + 341 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 342 0012 52E8003F ldrex r3, [r2] + 343 @ 0 "" 2 + 344 .LVL25: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 345 .loc 2 1073 4 view .LVU106 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 346 .loc 2 1073 4 is_stmt 0 view .LVU107 + 347 .thumb + 348 .syntax unified + 349 .LBE436: + 350 .LBE435: +3790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 351 .loc 1 3790 7 discriminator 1 view .LVU108 + 352 0016 23F08003 bic r3, r3, #128 + 353 .LVL26: +3790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 354 .loc 1 3790 7 is_stmt 1 discriminator 1 view .LVU109 + 355 .LBB437: + 356 .LBI437: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 357 .loc 2 1119 31 view .LVU110 + 358 .LBB438: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 359 .loc 2 1121 4 view .LVU111 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 360 .loc 2 1123 4 view .LVU112 + 361 .syntax unified + 362 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 363 001a 42E80031 strex r1, r3, [r2] + 364 @ 0 "" 2 + 365 .LVL27: + 366 .loc 2 1124 4 view .LVU113 + 367 .loc 2 1124 4 is_stmt 0 view .LVU114 + 368 .thumb + 369 .syntax unified + 370 .LBE438: + 371 .LBE437: +3790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 372 .loc 1 3790 7 discriminator 1 view .LVU115 + 373 001e 0029 cmp r1, #0 + 374 0020 F6D1 bne .L11 + 375 .LVL28: + 376 .L12: +3790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 377 .loc 1 3790 7 discriminator 1 view .LVU116 + 378 .LBE434: +3790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 379 .loc 1 3790 7 is_stmt 1 discriminator 2 view .LVU117 +3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 380 .loc 1 3793 7 discriminator 1 view .LVU118 + 381 .LBB439: +3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 382 .loc 1 3793 7 discriminator 1 view .LVU119 + ARM GAS /tmp/ccQxTlMj.s page 95 + + +3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 383 .loc 1 3793 7 discriminator 1 view .LVU120 +3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 384 .loc 1 3793 7 discriminator 1 view .LVU121 + 385 0022 0268 ldr r2, [r0] + 386 .LVL29: + 387 .LBB440: + 388 .LBI440: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 389 .loc 2 1068 31 view .LVU122 + 390 .LBB441: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391 .loc 2 1070 5 view .LVU123 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 392 .loc 2 1072 4 view .LVU124 + 393 .syntax unified + 394 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 395 0024 52E8003F ldrex r3, [r2] + 396 @ 0 "" 2 + 397 .LVL30: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 398 .loc 2 1073 4 view .LVU125 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 399 .loc 2 1073 4 is_stmt 0 view .LVU126 + 400 .thumb + 401 .syntax unified + 402 .LBE441: + 403 .LBE440: +3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 404 .loc 1 3793 7 discriminator 1 view .LVU127 + 405 0028 43F04003 orr r3, r3, #64 + 406 .LVL31: +3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 407 .loc 1 3793 7 is_stmt 1 discriminator 1 view .LVU128 + 408 .LBB442: + 409 .LBI442: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 410 .loc 2 1119 31 view .LVU129 + 411 .LBB443: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 412 .loc 2 1121 4 view .LVU130 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 413 .loc 2 1123 4 view .LVU131 + 414 .syntax unified + 415 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 416 002c 42E80031 strex r1, r3, [r2] + 417 @ 0 "" 2 + 418 .LVL32: + 419 .loc 2 1124 4 view .LVU132 + 420 .loc 2 1124 4 is_stmt 0 view .LVU133 + 421 .thumb + 422 .syntax unified + 423 .LBE443: + 424 .LBE442: +3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 425 .loc 1 3793 7 discriminator 1 view .LVU134 + 426 0030 0029 cmp r1, #0 + ARM GAS /tmp/ccQxTlMj.s page 96 + + + 427 0032 F6D1 bne .L12 + 428 0034 7047 bx lr + 429 .LVL33: + 430 .L10: +3793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 431 .loc 1 3793 7 discriminator 1 view .LVU135 + 432 .LBE439: +3797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pTxBuffPtr++; + 433 .loc 1 3797 7 is_stmt 1 view .LVU136 +3797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pTxBuffPtr++; + 434 .loc 1 3797 46 is_stmt 0 view .LVU137 + 435 0036 C36C ldr r3, [r0, #76] +3797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pTxBuffPtr++; + 436 .loc 1 3797 40 view .LVU138 + 437 0038 1A78 ldrb r2, [r3] @ zero_extendqisi2 +3797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pTxBuffPtr++; + 438 .loc 1 3797 12 view .LVU139 + 439 003a 0368 ldr r3, [r0] +3797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pTxBuffPtr++; + 440 .loc 1 3797 28 view .LVU140 + 441 003c 9A62 str r2, [r3, #40] +3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount--; + 442 .loc 1 3798 7 is_stmt 1 view .LVU141 +3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount--; + 443 .loc 1 3798 12 is_stmt 0 view .LVU142 + 444 003e C36C ldr r3, [r0, #76] +3798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount--; + 445 .loc 1 3798 24 view .LVU143 + 446 0040 0133 adds r3, r3, #1 + 447 0042 C364 str r3, [r0, #76] +3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 448 .loc 1 3799 7 is_stmt 1 view .LVU144 +3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 449 .loc 1 3799 12 is_stmt 0 view .LVU145 + 450 0044 B0F85230 ldrh r3, [r0, #82] + 451 0048 9BB2 uxth r3, r3 +3799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 452 .loc 1 3799 25 view .LVU146 + 453 004a 013B subs r3, r3, #1 + 454 004c 9BB2 uxth r3, r3 + 455 004e A0F85230 strh r3, [r0, #82] @ movhi + 456 .loc 1 3802 1 view .LVU147 + 457 0052 D8E7 b .L8 + 458 .cfi_endproc + 459 .LFE203: + 461 .section .text.UART_TxISR_16BIT,"ax",%progbits + 462 .align 1 + 463 .syntax unified + 464 .thumb + 465 .thumb_func + 467 UART_TxISR_16BIT: + 468 .LVL34: + 469 .LFB204: +3803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief TX interrupt handler for 9 bits data word length. +3806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note Function is called under interruption only, once + ARM GAS /tmp/ccQxTlMj.s page 97 + + +3807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * interruptions have been enabled by HAL_UART_Transmit_IT(). +3808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +3809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +3810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) +3812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 470 .loc 1 3812 1 is_stmt 1 view -0 + 471 .cfi_startproc + 472 @ args = 0, pretend = 0, frame = 0 + 473 @ frame_needed = 0, uses_anonymous_args = 0 + 474 @ link register save eliminated. +3813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const uint16_t *tmp; + 475 .loc 1 3813 3 view .LVU149 +3814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that a Tx process is ongoing */ +3816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_BUSY_TX) + 476 .loc 1 3816 3 view .LVU150 + 477 .loc 1 3816 12 is_stmt 0 view .LVU151 + 478 0000 C36F ldr r3, [r0, #124] + 479 .loc 1 3816 6 view .LVU152 + 480 0002 212B cmp r3, #33 + 481 0004 00D0 beq .L19 + 482 .L14: +3817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->TxXferCount == 0U) +3819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the UART Transmit Data Register Empty Interrupt */ +3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); +3822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the UART Transmit Complete Interrupt */ +3824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); +3825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +3827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** tmp = (const uint16_t *) huart->pTxBuffPtr; +3829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); +3830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pTxBuffPtr += 2U; +3831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount--; +3832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 483 .loc 1 3834 1 view .LVU153 + 484 0006 7047 bx lr + 485 .L19: +3818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 486 .loc 1 3818 5 is_stmt 1 view .LVU154 +3818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 487 .loc 1 3818 14 is_stmt 0 view .LVU155 + 488 0008 B0F85230 ldrh r3, [r0, #82] + 489 000c 9BB2 uxth r3, r3 +3818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 490 .loc 1 3818 8 view .LVU156 + 491 000e 93B9 cbnz r3, .L16 + 492 .L17: +3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 493 .loc 1 3821 7 is_stmt 1 discriminator 1 view .LVU157 + 494 .LBB444: + ARM GAS /tmp/ccQxTlMj.s page 98 + + +3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 495 .loc 1 3821 7 discriminator 1 view .LVU158 +3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 496 .loc 1 3821 7 discriminator 1 view .LVU159 +3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 497 .loc 1 3821 7 discriminator 1 view .LVU160 + 498 0010 0268 ldr r2, [r0] + 499 .LVL35: + 500 .LBB445: + 501 .LBI445: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 502 .loc 2 1068 31 view .LVU161 + 503 .LBB446: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 504 .loc 2 1070 5 view .LVU162 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 505 .loc 2 1072 4 view .LVU163 + 506 .syntax unified + 507 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 508 0012 52E8003F ldrex r3, [r2] + 509 @ 0 "" 2 + 510 .LVL36: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 511 .loc 2 1073 4 view .LVU164 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 512 .loc 2 1073 4 is_stmt 0 view .LVU165 + 513 .thumb + 514 .syntax unified + 515 .LBE446: + 516 .LBE445: +3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 517 .loc 1 3821 7 discriminator 1 view .LVU166 + 518 0016 23F08003 bic r3, r3, #128 + 519 .LVL37: +3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 520 .loc 1 3821 7 is_stmt 1 discriminator 1 view .LVU167 + 521 .LBB447: + 522 .LBI447: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 523 .loc 2 1119 31 view .LVU168 + 524 .LBB448: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 525 .loc 2 1121 4 view .LVU169 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 526 .loc 2 1123 4 view .LVU170 + 527 .syntax unified + 528 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 529 001a 42E80031 strex r1, r3, [r2] + 530 @ 0 "" 2 + 531 .LVL38: + 532 .loc 2 1124 4 view .LVU171 + 533 .loc 2 1124 4 is_stmt 0 view .LVU172 + 534 .thumb + 535 .syntax unified + 536 .LBE448: + 537 .LBE447: +3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 99 + + + 538 .loc 1 3821 7 discriminator 1 view .LVU173 + 539 001e 0029 cmp r1, #0 + 540 0020 F6D1 bne .L17 + 541 .LVL39: + 542 .L18: +3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 543 .loc 1 3821 7 discriminator 1 view .LVU174 + 544 .LBE444: +3821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 545 .loc 1 3821 7 is_stmt 1 discriminator 2 view .LVU175 +3824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 546 .loc 1 3824 7 discriminator 1 view .LVU176 + 547 .LBB449: +3824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 548 .loc 1 3824 7 discriminator 1 view .LVU177 +3824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 549 .loc 1 3824 7 discriminator 1 view .LVU178 +3824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 550 .loc 1 3824 7 discriminator 1 view .LVU179 + 551 0022 0268 ldr r2, [r0] + 552 .LVL40: + 553 .LBB450: + 554 .LBI450: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 555 .loc 2 1068 31 view .LVU180 + 556 .LBB451: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 557 .loc 2 1070 5 view .LVU181 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 558 .loc 2 1072 4 view .LVU182 + 559 .syntax unified + 560 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 561 0024 52E8003F ldrex r3, [r2] + 562 @ 0 "" 2 + 563 .LVL41: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 564 .loc 2 1073 4 view .LVU183 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 565 .loc 2 1073 4 is_stmt 0 view .LVU184 + 566 .thumb + 567 .syntax unified + 568 .LBE451: + 569 .LBE450: +3824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 570 .loc 1 3824 7 discriminator 1 view .LVU185 + 571 0028 43F04003 orr r3, r3, #64 + 572 .LVL42: +3824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 573 .loc 1 3824 7 is_stmt 1 discriminator 1 view .LVU186 + 574 .LBB452: + 575 .LBI452: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 576 .loc 2 1119 31 view .LVU187 + 577 .LBB453: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 578 .loc 2 1121 4 view .LVU188 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/ccQxTlMj.s page 100 + + + 579 .loc 2 1123 4 view .LVU189 + 580 .syntax unified + 581 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 582 002c 42E80031 strex r1, r3, [r2] + 583 @ 0 "" 2 + 584 .LVL43: + 585 .loc 2 1124 4 view .LVU190 + 586 .loc 2 1124 4 is_stmt 0 view .LVU191 + 587 .thumb + 588 .syntax unified + 589 .LBE453: + 590 .LBE452: +3824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 591 .loc 1 3824 7 discriminator 1 view .LVU192 + 592 0030 0029 cmp r1, #0 + 593 0032 F6D1 bne .L18 + 594 0034 7047 bx lr + 595 .LVL44: + 596 .L16: +3824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 597 .loc 1 3824 7 discriminator 1 view .LVU193 + 598 .LBE449: +3828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + 599 .loc 1 3828 7 is_stmt 1 view .LVU194 +3828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + 600 .loc 1 3828 11 is_stmt 0 view .LVU195 + 601 0036 C36C ldr r3, [r0, #76] + 602 .LVL45: +3829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pTxBuffPtr += 2U; + 603 .loc 1 3829 7 is_stmt 1 view .LVU196 +3829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pTxBuffPtr += 2U; + 604 .loc 1 3829 43 is_stmt 0 view .LVU197 + 605 0038 1B88 ldrh r3, [r3] + 606 .LVL46: +3829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pTxBuffPtr += 2U; + 607 .loc 1 3829 12 view .LVU198 + 608 003a 0268 ldr r2, [r0] +3829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pTxBuffPtr += 2U; + 609 .loc 1 3829 50 view .LVU199 + 610 003c C3F30803 ubfx r3, r3, #0, #9 +3829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pTxBuffPtr += 2U; + 611 .loc 1 3829 28 view .LVU200 + 612 0040 9362 str r3, [r2, #40] + 613 .LVL47: +3830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount--; + 614 .loc 1 3830 7 is_stmt 1 view .LVU201 +3830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount--; + 615 .loc 1 3830 12 is_stmt 0 view .LVU202 + 616 0042 C36C ldr r3, [r0, #76] +3830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount--; + 617 .loc 1 3830 25 view .LVU203 + 618 0044 0233 adds r3, r3, #2 + 619 0046 C364 str r3, [r0, #76] +3831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 620 .loc 1 3831 7 is_stmt 1 view .LVU204 +3831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 621 .loc 1 3831 12 is_stmt 0 view .LVU205 + ARM GAS /tmp/ccQxTlMj.s page 101 + + + 622 0048 B0F85230 ldrh r3, [r0, #82] + 623 004c 9BB2 uxth r3, r3 +3831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 624 .loc 1 3831 25 view .LVU206 + 625 004e 013B subs r3, r3, #1 + 626 0050 9BB2 uxth r3, r3 + 627 0052 A0F85230 strh r3, [r0, #82] @ movhi + 628 .loc 1 3834 1 view .LVU207 + 629 0056 D6E7 b .L14 + 630 .cfi_endproc + 631 .LFE204: + 633 .section .text.HAL_UART_MspInit,"ax",%progbits + 634 .align 1 + 635 .weak HAL_UART_MspInit + 636 .syntax unified + 637 .thumb + 638 .thumb_func + 640 HAL_UART_MspInit: + 641 .LVL48: + 642 .LFB146: + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 643 .loc 1 662 1 is_stmt 1 view -0 + 644 .cfi_startproc + 645 @ args = 0, pretend = 0, frame = 0 + 646 @ frame_needed = 0, uses_anonymous_args = 0 + 647 @ link register save eliminated. + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 648 .loc 1 664 3 view .LVU209 + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 649 .loc 1 669 1 is_stmt 0 view .LVU210 + 650 0000 7047 bx lr + 651 .cfi_endproc + 652 .LFE146: + 654 .section .text.HAL_UART_MspDeInit,"ax",%progbits + 655 .align 1 + 656 .weak HAL_UART_MspDeInit + 657 .syntax unified + 658 .thumb + 659 .thumb_func + 661 HAL_UART_MspDeInit: + 662 .LVL49: + 663 .LFB147: + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 664 .loc 1 677 1 is_stmt 1 view -0 + 665 .cfi_startproc + 666 @ args = 0, pretend = 0, frame = 0 + 667 @ frame_needed = 0, uses_anonymous_args = 0 + 668 @ link register save eliminated. + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 669 .loc 1 679 3 view .LVU212 + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 670 .loc 1 684 1 is_stmt 0 view .LVU213 + 671 0000 7047 bx lr + 672 .cfi_endproc + 673 .LFE147: + 675 .section .text.HAL_UART_DeInit,"ax",%progbits + 676 .align 1 + ARM GAS /tmp/ccQxTlMj.s page 102 + + + 677 .global HAL_UART_DeInit + 678 .syntax unified + 679 .thumb + 680 .thumb_func + 682 HAL_UART_DeInit: + 683 .LVL50: + 684 .LFB145: + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the UART handle allocation */ + 685 .loc 1 615 1 is_stmt 1 view -0 + 686 .cfi_startproc + 687 @ args = 0, pretend = 0, frame = 0 + 688 @ frame_needed = 0, uses_anonymous_args = 0 + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 689 .loc 1 617 3 view .LVU215 + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 690 .loc 1 617 6 is_stmt 0 view .LVU216 + 691 0000 E0B1 cbz r0, .L24 + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the UART handle allocation */ + 692 .loc 1 615 1 view .LVU217 + 693 0002 38B5 push {r3, r4, r5, lr} + 694 .LCFI0: + 695 .cfi_def_cfa_offset 16 + 696 .cfi_offset 3, -16 + 697 .cfi_offset 4, -12 + 698 .cfi_offset 5, -8 + 699 .cfi_offset 14, -4 + 700 0004 0546 mov r5, r0 + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 701 .loc 1 623 3 is_stmt 1 view .LVU218 + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 702 .loc 1 625 3 view .LVU219 + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 703 .loc 1 625 17 is_stmt 0 view .LVU220 + 704 0006 2423 movs r3, #36 + 705 0008 C367 str r3, [r0, #124] + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 706 .loc 1 627 3 is_stmt 1 view .LVU221 + 707 000a 0268 ldr r2, [r0] + 708 000c 1368 ldr r3, [r2] + 709 000e 23F00103 bic r3, r3, #1 + 710 0012 1360 str r3, [r2] + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->CR2 = 0x0U; + 711 .loc 1 629 3 view .LVU222 + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->CR2 = 0x0U; + 712 .loc 1 629 8 is_stmt 0 view .LVU223 + 713 0014 0368 ldr r3, [r0] + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->CR2 = 0x0U; + 714 .loc 1 629 24 view .LVU224 + 715 0016 0024 movs r4, #0 + 716 0018 1C60 str r4, [r3] + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->CR3 = 0x0U; + 717 .loc 1 630 3 is_stmt 1 view .LVU225 + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->CR3 = 0x0U; + 718 .loc 1 630 8 is_stmt 0 view .LVU226 + 719 001a 0368 ldr r3, [r0] + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->CR3 = 0x0U; + 720 .loc 1 630 24 view .LVU227 + ARM GAS /tmp/ccQxTlMj.s page 103 + + + 721 001c 5C60 str r4, [r3, #4] + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 722 .loc 1 631 3 is_stmt 1 view .LVU228 + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 723 .loc 1 631 8 is_stmt 0 view .LVU229 + 724 001e 0368 ldr r3, [r0] + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 725 .loc 1 631 24 view .LVU230 + 726 0020 9C60 str r4, [r3, #8] + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 727 .loc 1 642 3 is_stmt 1 view .LVU231 + 728 0022 FFF7FEFF bl HAL_UART_MspDeInit + 729 .LVL51: + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_RESET; + 730 .loc 1 645 3 view .LVU232 + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_RESET; + 731 .loc 1 645 20 is_stmt 0 view .LVU233 + 732 0026 C5F88440 str r4, [r5, #132] + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_RESET; + 733 .loc 1 646 3 is_stmt 1 view .LVU234 + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_RESET; + 734 .loc 1 646 17 is_stmt 0 view .LVU235 + 735 002a EC67 str r4, [r5, #124] + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 736 .loc 1 647 3 is_stmt 1 view .LVU236 + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 737 .loc 1 647 18 is_stmt 0 view .LVU237 + 738 002c C5F88040 str r4, [r5, #128] + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; + 739 .loc 1 648 3 is_stmt 1 view .LVU238 + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; + 740 .loc 1 648 24 is_stmt 0 view .LVU239 + 741 0030 2C66 str r4, [r5, #96] + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 742 .loc 1 649 3 is_stmt 1 view .LVU240 + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 743 .loc 1 649 22 is_stmt 0 view .LVU241 + 744 0032 6C66 str r4, [r5, #100] + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 745 .loc 1 651 3 is_stmt 1 view .LVU242 + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 746 .loc 1 651 3 view .LVU243 + 747 0034 85F87840 strb r4, [r5, #120] + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 748 .loc 1 651 3 view .LVU244 + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 749 .loc 1 653 3 view .LVU245 + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 750 .loc 1 653 10 is_stmt 0 view .LVU246 + 751 0038 2046 mov r0, r4 + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 752 .loc 1 654 1 view .LVU247 + 753 003a 38BD pop {r3, r4, r5, pc} + 754 .LVL52: + 755 .L24: + 756 .LCFI1: + 757 .cfi_def_cfa_offset 0 + ARM GAS /tmp/ccQxTlMj.s page 104 + + + 758 .cfi_restore 3 + 759 .cfi_restore 4 + 760 .cfi_restore 5 + 761 .cfi_restore 14 + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 762 .loc 1 619 12 view .LVU248 + 763 003c 0120 movs r0, #1 + 764 .LVL53: + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 765 .loc 1 654 1 view .LVU249 + 766 003e 7047 bx lr + 767 .cfi_endproc + 768 .LFE145: + 770 .section .text.HAL_UART_Transmit_IT,"ax",%progbits + 771 .align 1 + 772 .global HAL_UART_Transmit_IT + 773 .syntax unified + 774 .thumb + 775 .thumb_func + 777 HAL_UART_Transmit_IT: + 778 .LVL54: + 779 .LFB150: +1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that a Tx process is not already ongoing */ + 780 .loc 1 1260 1 is_stmt 1 view -0 + 781 .cfi_startproc + 782 @ args = 0, pretend = 0, frame = 0 + 783 @ frame_needed = 0, uses_anonymous_args = 0 + 784 @ link register save eliminated. +1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 785 .loc 1 1262 3 view .LVU251 +1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 786 .loc 1 1262 12 is_stmt 0 view .LVU252 + 787 0000 C36F ldr r3, [r0, #124] +1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 788 .loc 1 1262 6 view .LVU253 + 789 0002 202B cmp r3, #32 + 790 0004 25D1 bne .L34 +1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 791 .loc 1 1264 5 is_stmt 1 view .LVU254 +1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 792 .loc 1 1264 8 is_stmt 0 view .LVU255 + 793 0006 002A cmp r2, #0 + 794 0008 18BF it ne + 795 000a 0029 cmpne r1, #0 + 796 000c 23D0 beq .L35 +1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferSize = Size; + 797 .loc 1 1269 5 is_stmt 1 view .LVU256 +1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferSize = Size; + 798 .loc 1 1269 24 is_stmt 0 view .LVU257 + 799 000e C164 str r1, [r0, #76] +1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = Size; + 800 .loc 1 1270 5 is_stmt 1 view .LVU258 +1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = Size; + 801 .loc 1 1270 24 is_stmt 0 view .LVU259 + 802 0010 A0F85020 strh r2, [r0, #80] @ movhi +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxISR = NULL; + 803 .loc 1 1271 5 is_stmt 1 view .LVU260 + ARM GAS /tmp/ccQxTlMj.s page 105 + + +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxISR = NULL; + 804 .loc 1 1271 24 is_stmt 0 view .LVU261 + 805 0014 A0F85220 strh r2, [r0, #82] @ movhi +1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 806 .loc 1 1272 5 is_stmt 1 view .LVU262 +1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 807 .loc 1 1272 24 is_stmt 0 view .LVU263 + 808 0018 0023 movs r3, #0 + 809 001a C366 str r3, [r0, #108] +1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; + 810 .loc 1 1274 5 is_stmt 1 view .LVU264 +1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; + 811 .loc 1 1274 22 is_stmt 0 view .LVU265 + 812 001c C0F88430 str r3, [r0, #132] +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 813 .loc 1 1275 5 is_stmt 1 view .LVU266 +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 814 .loc 1 1275 19 is_stmt 0 view .LVU267 + 815 0020 2123 movs r3, #33 + 816 0022 C367 str r3, [r0, #124] +1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 817 .loc 1 1278 5 is_stmt 1 view .LVU268 +1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 818 .loc 1 1278 21 is_stmt 0 view .LVU269 + 819 0024 8368 ldr r3, [r0, #8] +1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 820 .loc 1 1278 8 view .LVU270 + 821 0026 B3F5805F cmp r3, #4096 + 822 002a 0CD0 beq .L36 + 823 .L31: +1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 824 .loc 1 1284 7 is_stmt 1 view .LVU271 +1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 825 .loc 1 1284 20 is_stmt 0 view .LVU272 + 826 002c 0B4B ldr r3, .L37 + 827 002e C366 str r3, [r0, #108] + 828 .LVL55: + 829 .L33: +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 830 .loc 1 1288 5 is_stmt 1 discriminator 1 view .LVU273 + 831 .LBB454: +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 832 .loc 1 1288 5 discriminator 1 view .LVU274 +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 833 .loc 1 1288 5 discriminator 1 view .LVU275 +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 834 .loc 1 1288 5 discriminator 1 view .LVU276 + 835 0030 0268 ldr r2, [r0] + 836 .LVL56: + 837 .LBB455: + 838 .LBI455: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 839 .loc 2 1068 31 view .LVU277 + 840 .LBB456: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 841 .loc 2 1070 5 view .LVU278 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/ccQxTlMj.s page 106 + + + 842 .loc 2 1072 4 view .LVU279 + 843 .syntax unified + 844 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 845 0032 52E8003F ldrex r3, [r2] + 846 @ 0 "" 2 + 847 .LVL57: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 848 .loc 2 1073 4 view .LVU280 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 849 .loc 2 1073 4 is_stmt 0 view .LVU281 + 850 .thumb + 851 .syntax unified + 852 .LBE456: + 853 .LBE455: +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 854 .loc 1 1288 5 discriminator 1 view .LVU282 + 855 0036 43F08003 orr r3, r3, #128 + 856 .LVL58: +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 857 .loc 1 1288 5 is_stmt 1 discriminator 1 view .LVU283 + 858 .LBB457: + 859 .LBI457: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 860 .loc 2 1119 31 view .LVU284 + 861 .LBB458: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 862 .loc 2 1121 4 view .LVU285 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 863 .loc 2 1123 4 view .LVU286 + 864 .syntax unified + 865 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 866 003a 42E80031 strex r1, r3, [r2] + 867 @ 0 "" 2 + 868 .LVL59: + 869 .loc 2 1124 4 view .LVU287 + 870 .loc 2 1124 4 is_stmt 0 view .LVU288 + 871 .thumb + 872 .syntax unified + 873 .LBE458: + 874 .LBE457: +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 875 .loc 1 1288 5 discriminator 1 view .LVU289 + 876 003e 0029 cmp r1, #0 + 877 0040 F6D1 bne .L33 + 878 .LBE454: +1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 879 .loc 1 1290 12 view .LVU290 + 880 0042 0020 movs r0, #0 + 881 .LVL60: + 882 .LBB459: +1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 883 .loc 1 1290 12 view .LVU291 + 884 0044 7047 bx lr + 885 .LVL61: + 886 .L36: +1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 887 .loc 1 1290 12 view .LVU292 + ARM GAS /tmp/ccQxTlMj.s page 107 + + + 888 .LBE459: +1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 889 .loc 1 1278 71 discriminator 1 view .LVU293 + 890 0046 0369 ldr r3, [r0, #16] +1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 891 .loc 1 1278 56 discriminator 1 view .LVU294 + 892 0048 002B cmp r3, #0 + 893 004a EFD1 bne .L31 +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 894 .loc 1 1280 7 is_stmt 1 view .LVU295 +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 895 .loc 1 1280 20 is_stmt 0 view .LVU296 + 896 004c 044B ldr r3, .L37+4 + 897 004e C366 str r3, [r0, #108] + 898 0050 EEE7 b .L33 + 899 .L34: +1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 900 .loc 1 1294 12 view .LVU297 + 901 0052 0220 movs r0, #2 + 902 .LVL62: +1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 903 .loc 1 1294 12 view .LVU298 + 904 0054 7047 bx lr + 905 .LVL63: + 906 .L35: +1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 907 .loc 1 1266 14 view .LVU299 + 908 0056 0120 movs r0, #1 + 909 .LVL64: +1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 910 .loc 1 1296 1 view .LVU300 + 911 0058 7047 bx lr + 912 .L38: + 913 005a 00BF .align 2 + 914 .L37: + 915 005c 00000000 .word UART_TxISR_8BIT + 916 0060 00000000 .word UART_TxISR_16BIT + 917 .cfi_endproc + 918 .LFE150: + 920 .section .text.HAL_UART_Transmit_DMA,"ax",%progbits + 921 .align 1 + 922 .global HAL_UART_Transmit_DMA + 923 .syntax unified + 924 .thumb + 925 .thumb_func + 927 HAL_UART_Transmit_DMA: + 928 .LVL65: + 929 .LFB152: +1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that a Tx process is not already ongoing */ + 930 .loc 1 1347 1 is_stmt 1 view -0 + 931 .cfi_startproc + 932 @ args = 0, pretend = 0, frame = 0 + 933 @ frame_needed = 0, uses_anonymous_args = 0 +1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that a Tx process is not already ongoing */ + 934 .loc 1 1347 1 is_stmt 0 view .LVU302 + 935 0000 1346 mov r3, r2 +1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + ARM GAS /tmp/ccQxTlMj.s page 108 + + + 936 .loc 1 1349 3 is_stmt 1 view .LVU303 +1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 937 .loc 1 1349 12 is_stmt 0 view .LVU304 + 938 0002 C26F ldr r2, [r0, #124] + 939 .LVL66: +1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 940 .loc 1 1349 6 view .LVU305 + 941 0004 202A cmp r2, #32 + 942 0006 3BD1 bne .L43 +1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that a Tx process is not already ongoing */ + 943 .loc 1 1347 1 view .LVU306 + 944 0008 10B5 push {r4, lr} + 945 .LCFI2: + 946 .cfi_def_cfa_offset 8 + 947 .cfi_offset 4, -8 + 948 .cfi_offset 14, -4 + 949 000a 0446 mov r4, r0 +1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 950 .loc 1 1351 5 is_stmt 1 view .LVU307 +1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 951 .loc 1 1351 8 is_stmt 0 view .LVU308 + 952 000c 002B cmp r3, #0 + 953 000e 18BF it ne + 954 0010 0029 cmpne r1, #0 + 955 0012 37D0 beq .L44 +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferSize = Size; + 956 .loc 1 1356 5 is_stmt 1 view .LVU309 +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferSize = Size; + 957 .loc 1 1356 24 is_stmt 0 view .LVU310 + 958 0014 C164 str r1, [r0, #76] +1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = Size; + 959 .loc 1 1357 5 is_stmt 1 view .LVU311 +1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = Size; + 960 .loc 1 1357 24 is_stmt 0 view .LVU312 + 961 0016 A0F85030 strh r3, [r0, #80] @ movhi +1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 962 .loc 1 1358 5 is_stmt 1 view .LVU313 +1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 963 .loc 1 1358 24 is_stmt 0 view .LVU314 + 964 001a A0F85230 strh r3, [r0, #82] @ movhi +1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; + 965 .loc 1 1360 5 is_stmt 1 view .LVU315 +1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; + 966 .loc 1 1360 22 is_stmt 0 view .LVU316 + 967 001e 0022 movs r2, #0 + 968 0020 C0F88420 str r2, [r0, #132] +1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 969 .loc 1 1361 5 is_stmt 1 view .LVU317 +1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 970 .loc 1 1361 19 is_stmt 0 view .LVU318 + 971 0024 2122 movs r2, #33 + 972 0026 C267 str r2, [r0, #124] +1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 973 .loc 1 1363 5 is_stmt 1 view .LVU319 +1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 974 .loc 1 1363 14 is_stmt 0 view .LVU320 + 975 0028 026F ldr r2, [r0, #112] + ARM GAS /tmp/ccQxTlMj.s page 109 + + +1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 976 .loc 1 1363 8 view .LVU321 + 977 002a C2B1 cbz r2, .L41 +1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 978 .loc 1 1366 7 is_stmt 1 view .LVU322 +1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 979 .loc 1 1366 39 is_stmt 0 view .LVU323 + 980 002c 1649 ldr r1, .L49 + 981 .LVL67: +1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 982 .loc 1 1366 39 view .LVU324 + 983 002e D163 str r1, [r2, #60] + 984 .LVL68: +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 985 .loc 1 1369 7 is_stmt 1 view .LVU325 +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 986 .loc 1 1369 12 is_stmt 0 view .LVU326 + 987 0030 026F ldr r2, [r0, #112] +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 988 .loc 1 1369 43 view .LVU327 + 989 0032 1649 ldr r1, .L49+4 + 990 0034 1164 str r1, [r2, #64] +1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 991 .loc 1 1372 7 is_stmt 1 view .LVU328 +1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 992 .loc 1 1372 12 is_stmt 0 view .LVU329 + 993 0036 026F ldr r2, [r0, #112] +1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 994 .loc 1 1372 40 view .LVU330 + 995 0038 1549 ldr r1, .L49+8 + 996 003a D164 str r1, [r2, #76] +1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 997 .loc 1 1375 7 is_stmt 1 view .LVU331 +1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 998 .loc 1 1375 12 is_stmt 0 view .LVU332 + 999 003c 026F ldr r2, [r0, #112] +1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1000 .loc 1 1375 40 view .LVU333 + 1001 003e 0021 movs r1, #0 + 1002 0040 1165 str r1, [r2, #80] +1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1003 .loc 1 1378 7 is_stmt 1 view .LVU334 +1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1004 .loc 1 1378 88 is_stmt 0 view .LVU335 + 1005 0042 0268 ldr r2, [r0] +1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1006 .loc 1 1378 11 view .LVU336 + 1007 0044 2832 adds r2, r2, #40 + 1008 0046 C16C ldr r1, [r0, #76] + 1009 0048 006F ldr r0, [r0, #112] + 1010 .LVL69: +1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1011 .loc 1 1378 11 view .LVU337 + 1012 004a FFF7FEFF bl HAL_DMA_Start_IT + 1013 .LVL70: +1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1014 .loc 1 1378 10 discriminator 1 view .LVU338 + ARM GAS /tmp/ccQxTlMj.s page 110 + + + 1015 004e 30B1 cbz r0, .L41 +1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1016 .loc 1 1381 9 is_stmt 1 view .LVU339 +1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1017 .loc 1 1381 26 is_stmt 0 view .LVU340 + 1018 0050 1023 movs r3, #16 + 1019 0052 C4F88430 str r3, [r4, #132] +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1020 .loc 1 1384 9 is_stmt 1 view .LVU341 +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1021 .loc 1 1384 23 is_stmt 0 view .LVU342 + 1022 0056 2023 movs r3, #32 + 1023 0058 E367 str r3, [r4, #124] +1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1024 .loc 1 1386 9 is_stmt 1 view .LVU343 +1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1025 .loc 1 1386 16 is_stmt 0 view .LVU344 + 1026 005a 0120 movs r0, #1 + 1027 005c 0FE0 b .L40 + 1028 .L41: +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1029 .loc 1 1390 5 is_stmt 1 view .LVU345 + 1030 005e 2368 ldr r3, [r4] + 1031 0060 4022 movs r2, #64 + 1032 0062 1A62 str r2, [r3, #32] + 1033 .L42: +1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1034 .loc 1 1394 5 discriminator 1 view .LVU346 + 1035 .LBB460: +1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1036 .loc 1 1394 5 discriminator 1 view .LVU347 +1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1037 .loc 1 1394 5 discriminator 1 view .LVU348 +1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1038 .loc 1 1394 5 discriminator 1 view .LVU349 + 1039 0064 2268 ldr r2, [r4] + 1040 .LVL71: + 1041 .LBB461: + 1042 .LBI461: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1043 .loc 2 1068 31 view .LVU350 + 1044 .LBB462: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1045 .loc 2 1070 5 view .LVU351 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1046 .loc 2 1072 4 view .LVU352 + 1047 0066 02F10803 add r3, r2, #8 + 1048 .LVL72: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1049 .loc 2 1072 4 is_stmt 0 view .LVU353 + 1050 .syntax unified + 1051 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1052 006a 53E8003F ldrex r3, [r3] + 1053 @ 0 "" 2 + 1054 .LVL73: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1055 .loc 2 1073 4 is_stmt 1 view .LVU354 + ARM GAS /tmp/ccQxTlMj.s page 111 + + +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1056 .loc 2 1073 4 is_stmt 0 view .LVU355 + 1057 .thumb + 1058 .syntax unified + 1059 .LBE462: + 1060 .LBE461: +1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1061 .loc 1 1394 5 discriminator 1 view .LVU356 + 1062 006e 43F08003 orr r3, r3, #128 + 1063 .LVL74: +1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1064 .loc 1 1394 5 is_stmt 1 discriminator 1 view .LVU357 + 1065 .LBB463: + 1066 .LBI463: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1067 .loc 2 1119 31 view .LVU358 + 1068 .LBB464: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1069 .loc 2 1121 4 view .LVU359 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1070 .loc 2 1123 4 view .LVU360 + 1071 0072 0832 adds r2, r2, #8 + 1072 .LVL75: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1073 .loc 2 1123 4 is_stmt 0 view .LVU361 + 1074 .syntax unified + 1075 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1076 0074 42E80031 strex r1, r3, [r2] + 1077 @ 0 "" 2 + 1078 .LVL76: + 1079 .loc 2 1124 4 is_stmt 1 view .LVU362 + 1080 .loc 2 1124 4 is_stmt 0 view .LVU363 + 1081 .thumb + 1082 .syntax unified + 1083 .LBE464: + 1084 .LBE463: +1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1085 .loc 1 1394 5 discriminator 1 view .LVU364 + 1086 0078 0029 cmp r1, #0 + 1087 007a F3D1 bne .L42 + 1088 .LBE460: +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1089 .loc 1 1396 12 view .LVU365 + 1090 007c 0020 movs r0, #0 + 1091 .LVL77: + 1092 .L40: +1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1093 .loc 1 1402 1 view .LVU366 + 1094 007e 10BD pop {r4, pc} + 1095 .LVL78: + 1096 .L43: + 1097 .LCFI3: + 1098 .cfi_def_cfa_offset 0 + 1099 .cfi_restore 4 + 1100 .cfi_restore 14 +1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1101 .loc 1 1400 12 view .LVU367 + ARM GAS /tmp/ccQxTlMj.s page 112 + + + 1102 0080 0220 movs r0, #2 + 1103 .LVL79: +1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1104 .loc 1 1402 1 view .LVU368 + 1105 0082 7047 bx lr + 1106 .LVL80: + 1107 .L44: + 1108 .LCFI4: + 1109 .cfi_def_cfa_offset 8 + 1110 .cfi_offset 4, -8 + 1111 .cfi_offset 14, -4 +1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1112 .loc 1 1353 14 view .LVU369 + 1113 0084 0120 movs r0, #1 + 1114 .LVL81: +1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1115 .loc 1 1353 14 view .LVU370 + 1116 0086 FAE7 b .L40 + 1117 .L50: + 1118 .align 2 + 1119 .L49: + 1120 0088 00000000 .word UART_DMATransmitCplt + 1121 008c 00000000 .word UART_DMATxHalfCplt + 1122 0090 00000000 .word UART_DMAError + 1123 .cfi_endproc + 1124 .LFE152: + 1126 .section .text.HAL_UART_DMAPause,"ax",%progbits + 1127 .align 1 + 1128 .global HAL_UART_DMAPause + 1129 .syntax unified + 1130 .thumb + 1131 .thumb_func + 1133 HAL_UART_DMAPause: + 1134 .LVL82: + 1135 .LFB154: +1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const HAL_UART_StateTypeDef gstate = huart->gState; + 1136 .loc 1 1450 1 is_stmt 1 view -0 + 1137 .cfi_startproc + 1138 @ args = 0, pretend = 0, frame = 0 + 1139 @ frame_needed = 0, uses_anonymous_args = 0 + 1140 @ link register save eliminated. +1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const HAL_UART_StateTypeDef gstate = huart->gState; + 1141 .loc 1 1450 1 is_stmt 0 view .LVU372 + 1142 0000 10B4 push {r4} + 1143 .LCFI5: + 1144 .cfi_def_cfa_offset 4 + 1145 .cfi_offset 4, -4 +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const HAL_UART_StateTypeDef rxstate = huart->RxState; + 1146 .loc 1 1451 3 is_stmt 1 view .LVU373 +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const HAL_UART_StateTypeDef rxstate = huart->RxState; + 1147 .loc 1 1451 31 is_stmt 0 view .LVU374 + 1148 0002 C26F ldr r2, [r0, #124] + 1149 .LVL83: +1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1150 .loc 1 1452 3 is_stmt 1 view .LVU375 +1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1151 .loc 1 1452 31 is_stmt 0 view .LVU376 + ARM GAS /tmp/ccQxTlMj.s page 113 + + + 1152 0004 D0F88040 ldr r4, [r0, #128] + 1153 .LVL84: +1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 1154 .loc 1 1454 3 is_stmt 1 view .LVU377 +1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 1155 .loc 1 1454 8 is_stmt 0 view .LVU378 + 1156 0008 0368 ldr r3, [r0] + 1157 000a 9B68 ldr r3, [r3, #8] +1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 1158 .loc 1 1454 6 view .LVU379 + 1159 000c 13F0800F tst r3, #128 + 1160 0010 01D0 beq .L52 +1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 1161 .loc 1 1454 62 discriminator 1 view .LVU380 + 1162 0012 212A cmp r2, #33 + 1163 0014 0AD0 beq .L53 + 1164 .LVL85: + 1165 .L52: +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1166 .loc 1 1458 5 is_stmt 1 discriminator 2 view .LVU381 +1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 1167 .loc 1 1460 3 view .LVU382 +1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 1168 .loc 1 1460 8 is_stmt 0 view .LVU383 + 1169 0016 0368 ldr r3, [r0] + 1170 0018 9B68 ldr r3, [r3, #8] +1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 1171 .loc 1 1460 6 view .LVU384 + 1172 001a 13F0400F tst r3, #64 + 1173 001e 01D0 beq .L54 +1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 1174 .loc 1 1460 62 discriminator 1 view .LVU385 + 1175 0020 222C cmp r4, #34 + 1176 0022 10D0 beq .L55 + 1177 .L54: +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1178 .loc 1 1468 5 is_stmt 1 discriminator 2 view .LVU386 +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1179 .loc 1 1471 3 view .LVU387 +1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1180 .loc 1 1472 1 is_stmt 0 view .LVU388 + 1181 0024 0020 movs r0, #0 + 1182 .LVL86: +1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1183 .loc 1 1472 1 view .LVU389 + 1184 0026 5DF8044B ldr r4, [sp], #4 + 1185 .LCFI6: + 1186 .cfi_remember_state + 1187 .cfi_restore 4 + 1188 .cfi_def_cfa_offset 0 + 1189 .LVL87: +1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1190 .loc 1 1472 1 view .LVU390 + 1191 002a 7047 bx lr + 1192 .LVL88: + 1193 .L53: + 1194 .LCFI7: + ARM GAS /tmp/ccQxTlMj.s page 114 + + + 1195 .cfi_restore_state +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1196 .loc 1 1458 5 is_stmt 1 discriminator 1 view .LVU391 + 1197 .LBB465: +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1198 .loc 1 1458 5 discriminator 1 view .LVU392 +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1199 .loc 1 1458 5 discriminator 1 view .LVU393 +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1200 .loc 1 1458 5 discriminator 1 view .LVU394 + 1201 002c 0268 ldr r2, [r0] + 1202 .LVL89: + 1203 .LBB466: + 1204 .LBI466: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1205 .loc 2 1068 31 view .LVU395 + 1206 .LBB467: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1207 .loc 2 1070 5 view .LVU396 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1208 .loc 2 1072 4 view .LVU397 + 1209 002e 02F10803 add r3, r2, #8 + 1210 .LVL90: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1211 .loc 2 1072 4 is_stmt 0 view .LVU398 + 1212 .syntax unified + 1213 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1214 0032 53E8003F ldrex r3, [r3] + 1215 @ 0 "" 2 + 1216 .LVL91: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1217 .loc 2 1073 4 is_stmt 1 view .LVU399 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1218 .loc 2 1073 4 is_stmt 0 view .LVU400 + 1219 .thumb + 1220 .syntax unified + 1221 .LBE467: + 1222 .LBE466: +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1223 .loc 1 1458 5 discriminator 1 view .LVU401 + 1224 0036 23F08003 bic r3, r3, #128 + 1225 .LVL92: +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1226 .loc 1 1458 5 is_stmt 1 discriminator 1 view .LVU402 + 1227 .LBB468: + 1228 .LBI468: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1229 .loc 2 1119 31 view .LVU403 + 1230 .LBB469: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1231 .loc 2 1121 4 view .LVU404 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1232 .loc 2 1123 4 view .LVU405 + 1233 003a 0832 adds r2, r2, #8 + 1234 .LVL93: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1235 .loc 2 1123 4 is_stmt 0 view .LVU406 + ARM GAS /tmp/ccQxTlMj.s page 115 + + + 1236 .syntax unified + 1237 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1238 003c 42E80031 strex r1, r3, [r2] + 1239 @ 0 "" 2 + 1240 .LVL94: + 1241 .loc 2 1124 4 is_stmt 1 view .LVU407 + 1242 .loc 2 1124 4 is_stmt 0 view .LVU408 + 1243 .thumb + 1244 .syntax unified + 1245 .LBE469: + 1246 .LBE468: +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1247 .loc 1 1458 5 discriminator 1 view .LVU409 + 1248 0040 0029 cmp r1, #0 + 1249 0042 F3D1 bne .L53 + 1250 0044 E7E7 b .L52 + 1251 .LVL95: + 1252 .L55: +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1253 .loc 1 1458 5 discriminator 1 view .LVU410 + 1254 .LBE465: +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1255 .loc 1 1464 5 is_stmt 1 discriminator 1 view .LVU411 + 1256 .LBB470: +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1257 .loc 1 1464 5 discriminator 1 view .LVU412 +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1258 .loc 1 1464 5 discriminator 1 view .LVU413 +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1259 .loc 1 1464 5 discriminator 1 view .LVU414 + 1260 0046 0268 ldr r2, [r0] + 1261 .LVL96: + 1262 .LBB471: + 1263 .LBI471: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1264 .loc 2 1068 31 view .LVU415 + 1265 .LBB472: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1266 .loc 2 1070 5 view .LVU416 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1267 .loc 2 1072 4 view .LVU417 + 1268 .syntax unified + 1269 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1270 0048 52E8003F ldrex r3, [r2] + 1271 @ 0 "" 2 + 1272 .LVL97: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1273 .loc 2 1073 4 view .LVU418 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1274 .loc 2 1073 4 is_stmt 0 view .LVU419 + 1275 .thumb + 1276 .syntax unified + 1277 .LBE472: + 1278 .LBE471: +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1279 .loc 1 1464 5 discriminator 1 view .LVU420 + 1280 004c 23F48073 bic r3, r3, #256 + ARM GAS /tmp/ccQxTlMj.s page 116 + + + 1281 .LVL98: +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1282 .loc 1 1464 5 is_stmt 1 discriminator 1 view .LVU421 + 1283 .LBB473: + 1284 .LBI473: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1285 .loc 2 1119 31 view .LVU422 + 1286 .LBB474: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1287 .loc 2 1121 4 view .LVU423 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1288 .loc 2 1123 4 view .LVU424 + 1289 .syntax unified + 1290 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1291 0050 42E80031 strex r1, r3, [r2] + 1292 @ 0 "" 2 + 1293 .LVL99: + 1294 .loc 2 1124 4 view .LVU425 + 1295 .loc 2 1124 4 is_stmt 0 view .LVU426 + 1296 .thumb + 1297 .syntax unified + 1298 .LBE474: + 1299 .LBE473: +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1300 .loc 1 1464 5 discriminator 1 view .LVU427 + 1301 0054 0029 cmp r1, #0 + 1302 0056 F6D1 bne .L55 + 1303 .LVL100: + 1304 .L56: +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1305 .loc 1 1464 5 discriminator 1 view .LVU428 + 1306 .LBE470: +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1307 .loc 1 1464 5 is_stmt 1 discriminator 2 view .LVU429 +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1308 .loc 1 1465 5 discriminator 1 view .LVU430 + 1309 .LBB475: +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1310 .loc 1 1465 5 discriminator 1 view .LVU431 +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1311 .loc 1 1465 5 discriminator 1 view .LVU432 +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1312 .loc 1 1465 5 discriminator 1 view .LVU433 + 1313 0058 0268 ldr r2, [r0] + 1314 .LVL101: + 1315 .LBB476: + 1316 .LBI476: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1317 .loc 2 1068 31 view .LVU434 + 1318 .LBB477: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1319 .loc 2 1070 5 view .LVU435 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1320 .loc 2 1072 4 view .LVU436 + 1321 005a 02F10803 add r3, r2, #8 + 1322 .LVL102: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/ccQxTlMj.s page 117 + + + 1323 .loc 2 1072 4 is_stmt 0 view .LVU437 + 1324 .syntax unified + 1325 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1326 005e 53E8003F ldrex r3, [r3] + 1327 @ 0 "" 2 + 1328 .LVL103: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1329 .loc 2 1073 4 is_stmt 1 view .LVU438 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1330 .loc 2 1073 4 is_stmt 0 view .LVU439 + 1331 .thumb + 1332 .syntax unified + 1333 .LBE477: + 1334 .LBE476: +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1335 .loc 1 1465 5 discriminator 1 view .LVU440 + 1336 0062 23F00103 bic r3, r3, #1 + 1337 .LVL104: +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1338 .loc 1 1465 5 is_stmt 1 discriminator 1 view .LVU441 + 1339 .LBB478: + 1340 .LBI478: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1341 .loc 2 1119 31 view .LVU442 + 1342 .LBB479: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1343 .loc 2 1121 4 view .LVU443 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1344 .loc 2 1123 4 view .LVU444 + 1345 0066 0832 adds r2, r2, #8 + 1346 .LVL105: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1347 .loc 2 1123 4 is_stmt 0 view .LVU445 + 1348 .syntax unified + 1349 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1350 0068 42E80031 strex r1, r3, [r2] + 1351 @ 0 "" 2 + 1352 .LVL106: + 1353 .loc 2 1124 4 is_stmt 1 view .LVU446 + 1354 .loc 2 1124 4 is_stmt 0 view .LVU447 + 1355 .thumb + 1356 .syntax unified + 1357 .LBE479: + 1358 .LBE478: +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1359 .loc 1 1465 5 discriminator 1 view .LVU448 + 1360 006c 0029 cmp r1, #0 + 1361 006e F3D1 bne .L56 + 1362 .LVL107: + 1363 .L57: +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1364 .loc 1 1465 5 discriminator 1 view .LVU449 + 1365 .LBE475: +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1366 .loc 1 1465 5 is_stmt 1 discriminator 2 view .LVU450 +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1367 .loc 1 1468 5 discriminator 1 view .LVU451 + ARM GAS /tmp/ccQxTlMj.s page 118 + + + 1368 .LBB480: +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1369 .loc 1 1468 5 discriminator 1 view .LVU452 +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1370 .loc 1 1468 5 discriminator 1 view .LVU453 +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1371 .loc 1 1468 5 discriminator 1 view .LVU454 + 1372 0070 0268 ldr r2, [r0] + 1373 .LVL108: + 1374 .LBB481: + 1375 .LBI481: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1376 .loc 2 1068 31 view .LVU455 + 1377 .LBB482: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1378 .loc 2 1070 5 view .LVU456 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1379 .loc 2 1072 4 view .LVU457 + 1380 0072 02F10803 add r3, r2, #8 + 1381 .LVL109: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1382 .loc 2 1072 4 is_stmt 0 view .LVU458 + 1383 .syntax unified + 1384 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1385 0076 53E8003F ldrex r3, [r3] + 1386 @ 0 "" 2 + 1387 .LVL110: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1388 .loc 2 1073 4 is_stmt 1 view .LVU459 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1389 .loc 2 1073 4 is_stmt 0 view .LVU460 + 1390 .thumb + 1391 .syntax unified + 1392 .LBE482: + 1393 .LBE481: +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1394 .loc 1 1468 5 discriminator 1 view .LVU461 + 1395 007a 23F04003 bic r3, r3, #64 + 1396 .LVL111: +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1397 .loc 1 1468 5 is_stmt 1 discriminator 1 view .LVU462 + 1398 .LBB483: + 1399 .LBI483: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1400 .loc 2 1119 31 view .LVU463 + 1401 .LBB484: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1402 .loc 2 1121 4 view .LVU464 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1403 .loc 2 1123 4 view .LVU465 + 1404 007e 0832 adds r2, r2, #8 + 1405 .LVL112: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1406 .loc 2 1123 4 is_stmt 0 view .LVU466 + 1407 .syntax unified + 1408 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1409 0080 42E80031 strex r1, r3, [r2] + ARM GAS /tmp/ccQxTlMj.s page 119 + + + 1410 @ 0 "" 2 + 1411 .LVL113: + 1412 .loc 2 1124 4 is_stmt 1 view .LVU467 + 1413 .loc 2 1124 4 is_stmt 0 view .LVU468 + 1414 .thumb + 1415 .syntax unified + 1416 .LBE484: + 1417 .LBE483: +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1418 .loc 1 1468 5 discriminator 1 view .LVU469 + 1419 0084 0029 cmp r1, #0 + 1420 0086 F3D1 bne .L57 + 1421 0088 CCE7 b .L54 + 1422 .LBE480: + 1423 .cfi_endproc + 1424 .LFE154: + 1426 .section .text.HAL_UART_DMAResume,"ax",%progbits + 1427 .align 1 + 1428 .global HAL_UART_DMAResume + 1429 .syntax unified + 1430 .thumb + 1431 .thumb_func + 1433 HAL_UART_DMAResume: + 1434 .LVL114: + 1435 .LFB155: +1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_BUSY_TX) + 1436 .loc 1 1480 1 is_stmt 1 view -0 + 1437 .cfi_startproc + 1438 @ args = 0, pretend = 0, frame = 0 + 1439 @ frame_needed = 0, uses_anonymous_args = 0 + 1440 @ link register save eliminated. +1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1441 .loc 1 1481 3 view .LVU471 +1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1442 .loc 1 1481 12 is_stmt 0 view .LVU472 + 1443 0000 C36F ldr r3, [r0, #124] +1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1444 .loc 1 1481 6 view .LVU473 + 1445 0002 212B cmp r3, #33 + 1446 0004 05D0 beq .L61 + 1447 .L60: +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1448 .loc 1 1484 5 is_stmt 1 discriminator 2 view .LVU474 +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1449 .loc 1 1486 3 view .LVU475 +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1450 .loc 1 1486 12 is_stmt 0 view .LVU476 + 1451 0006 D0F88030 ldr r3, [r0, #128] +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1452 .loc 1 1486 6 view .LVU477 + 1453 000a 222B cmp r3, #34 + 1454 000c 0ED0 beq .L67 + 1455 .L62: +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1456 .loc 1 1499 5 is_stmt 1 discriminator 2 view .LVU478 +1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1457 .loc 1 1502 3 view .LVU479 + ARM GAS /tmp/ccQxTlMj.s page 120 + + +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1458 .loc 1 1503 1 is_stmt 0 view .LVU480 + 1459 000e 0020 movs r0, #0 + 1460 .LVL115: +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1461 .loc 1 1503 1 view .LVU481 + 1462 0010 7047 bx lr + 1463 .LVL116: + 1464 .L61: +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1465 .loc 1 1484 5 is_stmt 1 discriminator 1 view .LVU482 + 1466 .LBB485: +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1467 .loc 1 1484 5 discriminator 1 view .LVU483 +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1468 .loc 1 1484 5 discriminator 1 view .LVU484 +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1469 .loc 1 1484 5 discriminator 1 view .LVU485 + 1470 0012 0268 ldr r2, [r0] + 1471 .LVL117: + 1472 .LBB486: + 1473 .LBI486: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1474 .loc 2 1068 31 view .LVU486 + 1475 .LBB487: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1476 .loc 2 1070 5 view .LVU487 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1477 .loc 2 1072 4 view .LVU488 + 1478 0014 02F10803 add r3, r2, #8 + 1479 .LVL118: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1480 .loc 2 1072 4 is_stmt 0 view .LVU489 + 1481 .syntax unified + 1482 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1483 0018 53E8003F ldrex r3, [r3] + 1484 @ 0 "" 2 + 1485 .LVL119: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1486 .loc 2 1073 4 is_stmt 1 view .LVU490 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1487 .loc 2 1073 4 is_stmt 0 view .LVU491 + 1488 .thumb + 1489 .syntax unified + 1490 .LBE487: + 1491 .LBE486: +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1492 .loc 1 1484 5 discriminator 1 view .LVU492 + 1493 001c 43F08003 orr r3, r3, #128 + 1494 .LVL120: +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1495 .loc 1 1484 5 is_stmt 1 discriminator 1 view .LVU493 + 1496 .LBB488: + 1497 .LBI488: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1498 .loc 2 1119 31 view .LVU494 + 1499 .LBB489: + ARM GAS /tmp/ccQxTlMj.s page 121 + + +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1500 .loc 2 1121 4 view .LVU495 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1501 .loc 2 1123 4 view .LVU496 + 1502 0020 0832 adds r2, r2, #8 + 1503 .LVL121: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1504 .loc 2 1123 4 is_stmt 0 view .LVU497 + 1505 .syntax unified + 1506 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1507 0022 42E80031 strex r1, r3, [r2] + 1508 @ 0 "" 2 + 1509 .LVL122: + 1510 .loc 2 1124 4 is_stmt 1 view .LVU498 + 1511 .loc 2 1124 4 is_stmt 0 view .LVU499 + 1512 .thumb + 1513 .syntax unified + 1514 .LBE489: + 1515 .LBE488: +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1516 .loc 1 1484 5 discriminator 1 view .LVU500 + 1517 0026 0029 cmp r1, #0 + 1518 0028 F3D1 bne .L61 + 1519 002a ECE7 b .L60 + 1520 .LVL123: + 1521 .L67: +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1522 .loc 1 1484 5 discriminator 1 view .LVU501 + 1523 .LBE485: +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1524 .loc 1 1489 5 is_stmt 1 view .LVU502 + 1525 002c 0368 ldr r3, [r0] + 1526 002e 0822 movs r2, #8 + 1527 0030 1A62 str r2, [r3, #32] +1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1528 .loc 1 1492 5 view .LVU503 +1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1529 .loc 1 1492 20 is_stmt 0 view .LVU504 + 1530 0032 0369 ldr r3, [r0, #16] +1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1531 .loc 1 1492 8 view .LVU505 + 1532 0034 43B1 cbz r3, .L65 + 1533 .L64: +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1534 .loc 1 1494 7 is_stmt 1 discriminator 1 view .LVU506 + 1535 .LBB490: +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1536 .loc 1 1494 7 discriminator 1 view .LVU507 +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1537 .loc 1 1494 7 discriminator 1 view .LVU508 +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1538 .loc 1 1494 7 discriminator 1 view .LVU509 + 1539 0036 0268 ldr r2, [r0] + 1540 .LVL124: + 1541 .LBB491: + 1542 .LBI491: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccQxTlMj.s page 122 + + + 1543 .loc 2 1068 31 view .LVU510 + 1544 .LBB492: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1545 .loc 2 1070 5 view .LVU511 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1546 .loc 2 1072 4 view .LVU512 + 1547 .syntax unified + 1548 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1549 0038 52E8003F ldrex r3, [r2] + 1550 @ 0 "" 2 + 1551 .LVL125: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1552 .loc 2 1073 4 view .LVU513 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1553 .loc 2 1073 4 is_stmt 0 view .LVU514 + 1554 .thumb + 1555 .syntax unified + 1556 .LBE492: + 1557 .LBE491: +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1558 .loc 1 1494 7 discriminator 1 view .LVU515 + 1559 003c 43F48073 orr r3, r3, #256 + 1560 .LVL126: +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1561 .loc 1 1494 7 is_stmt 1 discriminator 1 view .LVU516 + 1562 .LBB493: + 1563 .LBI493: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1564 .loc 2 1119 31 view .LVU517 + 1565 .LBB494: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1566 .loc 2 1121 4 view .LVU518 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1567 .loc 2 1123 4 view .LVU519 + 1568 .syntax unified + 1569 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1570 0040 42E80031 strex r1, r3, [r2] + 1571 @ 0 "" 2 + 1572 .LVL127: + 1573 .loc 2 1124 4 view .LVU520 + 1574 .loc 2 1124 4 is_stmt 0 view .LVU521 + 1575 .thumb + 1576 .syntax unified + 1577 .LBE494: + 1578 .LBE493: +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1579 .loc 1 1494 7 discriminator 1 view .LVU522 + 1580 0044 0029 cmp r1, #0 + 1581 0046 F6D1 bne .L64 + 1582 .LVL128: + 1583 .L65: +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1584 .loc 1 1494 7 discriminator 1 view .LVU523 + 1585 .LBE490: +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1586 .loc 1 1494 7 is_stmt 1 discriminator 2 view .LVU524 +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 123 + + + 1587 .loc 1 1496 5 discriminator 1 view .LVU525 + 1588 .LBB495: +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1589 .loc 1 1496 5 discriminator 1 view .LVU526 +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1590 .loc 1 1496 5 discriminator 1 view .LVU527 +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1591 .loc 1 1496 5 discriminator 1 view .LVU528 + 1592 0048 0268 ldr r2, [r0] + 1593 .LVL129: + 1594 .LBB496: + 1595 .LBI496: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1596 .loc 2 1068 31 view .LVU529 + 1597 .LBB497: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1598 .loc 2 1070 5 view .LVU530 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1599 .loc 2 1072 4 view .LVU531 + 1600 004a 02F10803 add r3, r2, #8 + 1601 .LVL130: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1602 .loc 2 1072 4 is_stmt 0 view .LVU532 + 1603 .syntax unified + 1604 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1605 004e 53E8003F ldrex r3, [r3] + 1606 @ 0 "" 2 + 1607 .LVL131: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1608 .loc 2 1073 4 is_stmt 1 view .LVU533 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1609 .loc 2 1073 4 is_stmt 0 view .LVU534 + 1610 .thumb + 1611 .syntax unified + 1612 .LBE497: + 1613 .LBE496: +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1614 .loc 1 1496 5 discriminator 1 view .LVU535 + 1615 0052 43F00103 orr r3, r3, #1 + 1616 .LVL132: +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1617 .loc 1 1496 5 is_stmt 1 discriminator 1 view .LVU536 + 1618 .LBB498: + 1619 .LBI498: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1620 .loc 2 1119 31 view .LVU537 + 1621 .LBB499: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1622 .loc 2 1121 4 view .LVU538 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1623 .loc 2 1123 4 view .LVU539 + 1624 0056 0832 adds r2, r2, #8 + 1625 .LVL133: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1626 .loc 2 1123 4 is_stmt 0 view .LVU540 + 1627 .syntax unified + 1628 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + ARM GAS /tmp/ccQxTlMj.s page 124 + + + 1629 0058 42E80031 strex r1, r3, [r2] + 1630 @ 0 "" 2 + 1631 .LVL134: + 1632 .loc 2 1124 4 is_stmt 1 view .LVU541 + 1633 .loc 2 1124 4 is_stmt 0 view .LVU542 + 1634 .thumb + 1635 .syntax unified + 1636 .LBE499: + 1637 .LBE498: +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1638 .loc 1 1496 5 discriminator 1 view .LVU543 + 1639 005c 0029 cmp r1, #0 + 1640 005e F3D1 bne .L65 + 1641 .LVL135: + 1642 .L66: +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1643 .loc 1 1496 5 discriminator 1 view .LVU544 + 1644 .LBE495: +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1645 .loc 1 1496 5 is_stmt 1 discriminator 2 view .LVU545 +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1646 .loc 1 1499 5 discriminator 1 view .LVU546 + 1647 .LBB500: +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1648 .loc 1 1499 5 discriminator 1 view .LVU547 +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1649 .loc 1 1499 5 discriminator 1 view .LVU548 +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1650 .loc 1 1499 5 discriminator 1 view .LVU549 + 1651 0060 0268 ldr r2, [r0] + 1652 .LVL136: + 1653 .LBB501: + 1654 .LBI501: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1655 .loc 2 1068 31 view .LVU550 + 1656 .LBB502: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1657 .loc 2 1070 5 view .LVU551 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1658 .loc 2 1072 4 view .LVU552 + 1659 0062 02F10803 add r3, r2, #8 + 1660 .LVL137: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1661 .loc 2 1072 4 is_stmt 0 view .LVU553 + 1662 .syntax unified + 1663 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1664 0066 53E8003F ldrex r3, [r3] + 1665 @ 0 "" 2 + 1666 .LVL138: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1667 .loc 2 1073 4 is_stmt 1 view .LVU554 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1668 .loc 2 1073 4 is_stmt 0 view .LVU555 + 1669 .thumb + 1670 .syntax unified + 1671 .LBE502: + 1672 .LBE501: + ARM GAS /tmp/ccQxTlMj.s page 125 + + +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1673 .loc 1 1499 5 discriminator 1 view .LVU556 + 1674 006a 43F04003 orr r3, r3, #64 + 1675 .LVL139: +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1676 .loc 1 1499 5 is_stmt 1 discriminator 1 view .LVU557 + 1677 .LBB503: + 1678 .LBI503: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1679 .loc 2 1119 31 view .LVU558 + 1680 .LBB504: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1681 .loc 2 1121 4 view .LVU559 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1682 .loc 2 1123 4 view .LVU560 + 1683 006e 0832 adds r2, r2, #8 + 1684 .LVL140: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1685 .loc 2 1123 4 is_stmt 0 view .LVU561 + 1686 .syntax unified + 1687 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1688 0070 42E80031 strex r1, r3, [r2] + 1689 @ 0 "" 2 + 1690 .LVL141: + 1691 .loc 2 1124 4 is_stmt 1 view .LVU562 + 1692 .loc 2 1124 4 is_stmt 0 view .LVU563 + 1693 .thumb + 1694 .syntax unified + 1695 .LBE504: + 1696 .LBE503: +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1697 .loc 1 1499 5 discriminator 1 view .LVU564 + 1698 0074 0029 cmp r1, #0 + 1699 0076 F3D1 bne .L66 + 1700 0078 C9E7 b .L62 + 1701 .LBE500: + 1702 .cfi_endproc + 1703 .LFE155: + 1705 .section .text.HAL_UART_DMAStop,"ax",%progbits + 1706 .align 1 + 1707 .global HAL_UART_DMAStop + 1708 .syntax unified + 1709 .thumb + 1710 .thumb_func + 1712 HAL_UART_DMAStop: + 1713 .LVL142: + 1714 .LFB156: +1511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* The Lock is not implemented on this API to allow the user application + 1715 .loc 1 1511 1 is_stmt 1 view -0 + 1716 .cfi_startproc + 1717 @ args = 0, pretend = 0, frame = 0 + 1718 @ frame_needed = 0, uses_anonymous_args = 0 +1511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* The Lock is not implemented on this API to allow the user application + 1719 .loc 1 1511 1 is_stmt 0 view .LVU566 + 1720 0000 38B5 push {r3, r4, r5, lr} + 1721 .LCFI8: + 1722 .cfi_def_cfa_offset 16 + ARM GAS /tmp/ccQxTlMj.s page 126 + + + 1723 .cfi_offset 3, -16 + 1724 .cfi_offset 4, -12 + 1725 .cfi_offset 5, -8 + 1726 .cfi_offset 14, -4 + 1727 0002 0446 mov r4, r0 +1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const HAL_UART_StateTypeDef rxstate = huart->RxState; + 1728 .loc 1 1519 3 is_stmt 1 view .LVU567 +1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const HAL_UART_StateTypeDef rxstate = huart->RxState; + 1729 .loc 1 1519 31 is_stmt 0 view .LVU568 + 1730 0004 C26F ldr r2, [r0, #124] + 1731 .LVL143: +1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1732 .loc 1 1520 3 is_stmt 1 view .LVU569 +1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1733 .loc 1 1520 31 is_stmt 0 view .LVU570 + 1734 0006 D0F88050 ldr r5, [r0, #128] + 1735 .LVL144: +1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 1736 .loc 1 1523 3 is_stmt 1 view .LVU571 +1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 1737 .loc 1 1523 8 is_stmt 0 view .LVU572 + 1738 000a 0368 ldr r3, [r0] + 1739 000c 9B68 ldr r3, [r3, #8] +1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 1740 .loc 1 1523 6 view .LVU573 + 1741 000e 13F0800F tst r3, #128 + 1742 0012 01D0 beq .L69 +1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 1743 .loc 1 1523 62 discriminator 1 view .LVU574 + 1744 0014 212A cmp r2, #33 + 1745 0016 08D0 beq .L70 + 1746 .LVL145: + 1747 .L69: +1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 1748 .loc 1 1547 3 is_stmt 1 view .LVU575 +1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 1749 .loc 1 1547 8 is_stmt 0 view .LVU576 + 1750 0018 2368 ldr r3, [r4] + 1751 001a 9B68 ldr r3, [r3, #8] +1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 1752 .loc 1 1547 6 view .LVU577 + 1753 001c 13F0400F tst r3, #64 + 1754 0020 42D0 beq .L75 +1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 1755 .loc 1 1547 62 discriminator 1 view .LVU578 + 1756 0022 222D cmp r5, #34 + 1757 0024 20D0 beq .L73 +1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1758 .loc 1 1570 10 view .LVU579 + 1759 0026 0020 movs r0, #0 + 1760 0028 3FE0 b .L72 + 1761 .LVL146: + 1762 .L70: +1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1763 .loc 1 1526 5 is_stmt 1 discriminator 1 view .LVU580 + 1764 .LBB505: +1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 127 + + + 1765 .loc 1 1526 5 discriminator 1 view .LVU581 +1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1766 .loc 1 1526 5 discriminator 1 view .LVU582 +1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1767 .loc 1 1526 5 discriminator 1 view .LVU583 + 1768 002a 2268 ldr r2, [r4] + 1769 .LVL147: + 1770 .LBB506: + 1771 .LBI506: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1772 .loc 2 1068 31 view .LVU584 + 1773 .LBB507: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1774 .loc 2 1070 5 view .LVU585 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1775 .loc 2 1072 4 view .LVU586 + 1776 002c 02F10803 add r3, r2, #8 + 1777 .LVL148: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1778 .loc 2 1072 4 is_stmt 0 view .LVU587 + 1779 .syntax unified + 1780 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1781 0030 53E8003F ldrex r3, [r3] + 1782 @ 0 "" 2 + 1783 .LVL149: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1784 .loc 2 1073 4 is_stmt 1 view .LVU588 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1785 .loc 2 1073 4 is_stmt 0 view .LVU589 + 1786 .thumb + 1787 .syntax unified + 1788 .LBE507: + 1789 .LBE506: +1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1790 .loc 1 1526 5 discriminator 1 view .LVU590 + 1791 0034 23F08003 bic r3, r3, #128 + 1792 .LVL150: +1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1793 .loc 1 1526 5 is_stmt 1 discriminator 1 view .LVU591 + 1794 .LBB508: + 1795 .LBI508: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1796 .loc 2 1119 31 view .LVU592 + 1797 .LBB509: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1798 .loc 2 1121 4 view .LVU593 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1799 .loc 2 1123 4 view .LVU594 + 1800 0038 0832 adds r2, r2, #8 + 1801 .LVL151: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1802 .loc 2 1123 4 is_stmt 0 view .LVU595 + 1803 .syntax unified + 1804 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1805 003a 42E80031 strex r1, r3, [r2] + 1806 @ 0 "" 2 + 1807 .LVL152: + ARM GAS /tmp/ccQxTlMj.s page 128 + + + 1808 .loc 2 1124 4 is_stmt 1 view .LVU596 + 1809 .loc 2 1124 4 is_stmt 0 view .LVU597 + 1810 .thumb + 1811 .syntax unified + 1812 .LBE509: + 1813 .LBE508: +1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1814 .loc 1 1526 5 discriminator 1 view .LVU598 + 1815 003e 0029 cmp r1, #0 + 1816 0040 F3D1 bne .L70 + 1817 .LBE505: +1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1818 .loc 1 1526 5 is_stmt 1 discriminator 2 view .LVU599 +1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1819 .loc 1 1529 5 view .LVU600 +1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1820 .loc 1 1529 14 is_stmt 0 view .LVU601 + 1821 0042 206F ldr r0, [r4, #112] + 1822 .LVL153: +1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1823 .loc 1 1529 8 view .LVU602 + 1824 0044 10B1 cbz r0, .L71 +1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1825 .loc 1 1531 7 is_stmt 1 view .LVU603 +1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1826 .loc 1 1531 11 is_stmt 0 view .LVU604 + 1827 0046 FFF7FEFF bl HAL_DMA_Abort + 1828 .LVL154: +1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1829 .loc 1 1531 10 discriminator 1 view .LVU605 + 1830 004a 18B9 cbnz r0, .L78 + 1831 .L71: +1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1832 .loc 1 1543 5 is_stmt 1 view .LVU606 + 1833 004c 2046 mov r0, r4 + 1834 004e FFF7FEFF bl UART_EndTxTransfer + 1835 .LVL155: + 1836 0052 E1E7 b .L69 + 1837 .L78: +1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1838 .loc 1 1533 9 view .LVU607 +1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1839 .loc 1 1533 13 is_stmt 0 view .LVU608 + 1840 0054 206F ldr r0, [r4, #112] + 1841 0056 FFF7FEFF bl HAL_DMA_GetError + 1842 .LVL156: +1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1843 .loc 1 1533 12 discriminator 1 view .LVU609 + 1844 005a 2028 cmp r0, #32 + 1845 005c F6D1 bne .L71 +1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1846 .loc 1 1536 11 is_stmt 1 view .LVU610 +1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1847 .loc 1 1536 28 is_stmt 0 view .LVU611 + 1848 005e 1023 movs r3, #16 + 1849 0060 C4F88430 str r3, [r4, #132] +1538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + ARM GAS /tmp/ccQxTlMj.s page 129 + + + 1850 .loc 1 1538 11 is_stmt 1 view .LVU612 +1538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1851 .loc 1 1538 18 is_stmt 0 view .LVU613 + 1852 0064 0320 movs r0, #3 + 1853 0066 20E0 b .L72 + 1854 .LVL157: + 1855 .L73: +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1856 .loc 1 1550 5 is_stmt 1 discriminator 1 view .LVU614 + 1857 .LBB510: +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1858 .loc 1 1550 5 discriminator 1 view .LVU615 +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1859 .loc 1 1550 5 discriminator 1 view .LVU616 +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1860 .loc 1 1550 5 discriminator 1 view .LVU617 + 1861 0068 2268 ldr r2, [r4] + 1862 .LVL158: + 1863 .LBB511: + 1864 .LBI511: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1865 .loc 2 1068 31 view .LVU618 + 1866 .LBB512: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1867 .loc 2 1070 5 view .LVU619 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1868 .loc 2 1072 4 view .LVU620 + 1869 006a 02F10803 add r3, r2, #8 + 1870 .LVL159: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1871 .loc 2 1072 4 is_stmt 0 view .LVU621 + 1872 .syntax unified + 1873 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1874 006e 53E8003F ldrex r3, [r3] + 1875 @ 0 "" 2 + 1876 .LVL160: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1877 .loc 2 1073 4 is_stmt 1 view .LVU622 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1878 .loc 2 1073 4 is_stmt 0 view .LVU623 + 1879 .thumb + 1880 .syntax unified + 1881 .LBE512: + 1882 .LBE511: +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1883 .loc 1 1550 5 discriminator 1 view .LVU624 + 1884 0072 23F04003 bic r3, r3, #64 + 1885 .LVL161: +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1886 .loc 1 1550 5 is_stmt 1 discriminator 1 view .LVU625 + 1887 .LBB513: + 1888 .LBI513: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1889 .loc 2 1119 31 view .LVU626 + 1890 .LBB514: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1891 .loc 2 1121 4 view .LVU627 + ARM GAS /tmp/ccQxTlMj.s page 130 + + +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1892 .loc 2 1123 4 view .LVU628 + 1893 0076 0832 adds r2, r2, #8 + 1894 .LVL162: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1895 .loc 2 1123 4 is_stmt 0 view .LVU629 + 1896 .syntax unified + 1897 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1898 0078 42E80031 strex r1, r3, [r2] + 1899 @ 0 "" 2 + 1900 .LVL163: + 1901 .loc 2 1124 4 is_stmt 1 view .LVU630 + 1902 .loc 2 1124 4 is_stmt 0 view .LVU631 + 1903 .thumb + 1904 .syntax unified + 1905 .LBE514: + 1906 .LBE513: +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1907 .loc 1 1550 5 discriminator 1 view .LVU632 + 1908 007c 0029 cmp r1, #0 + 1909 007e F3D1 bne .L73 + 1910 .LBE510: +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1911 .loc 1 1550 5 is_stmt 1 discriminator 2 view .LVU633 +1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1912 .loc 1 1553 5 view .LVU634 +1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1913 .loc 1 1553 14 is_stmt 0 view .LVU635 + 1914 0080 606F ldr r0, [r4, #116] +1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1915 .loc 1 1553 8 view .LVU636 + 1916 0082 10B1 cbz r0, .L74 +1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1917 .loc 1 1555 7 is_stmt 1 view .LVU637 +1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1918 .loc 1 1555 11 is_stmt 0 view .LVU638 + 1919 0084 FFF7FEFF bl HAL_DMA_Abort + 1920 .LVL164: +1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1921 .loc 1 1555 10 discriminator 1 view .LVU639 + 1922 0088 20B9 cbnz r0, .L79 + 1923 .L74: +1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1924 .loc 1 1567 5 is_stmt 1 view .LVU640 + 1925 008a 2046 mov r0, r4 + 1926 008c FFF7FEFF bl UART_EndRxTransfer + 1927 .LVL165: +1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1928 .loc 1 1570 10 is_stmt 0 view .LVU641 + 1929 0090 0020 movs r0, #0 + 1930 0092 0AE0 b .L72 + 1931 .L79: +1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1932 .loc 1 1557 9 is_stmt 1 view .LVU642 +1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1933 .loc 1 1557 13 is_stmt 0 view .LVU643 + 1934 0094 606F ldr r0, [r4, #116] + ARM GAS /tmp/ccQxTlMj.s page 131 + + + 1935 0096 FFF7FEFF bl HAL_DMA_GetError + 1936 .LVL166: +1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 1937 .loc 1 1557 12 discriminator 1 view .LVU644 + 1938 009a 2028 cmp r0, #32 + 1939 009c F5D1 bne .L74 +1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1940 .loc 1 1560 11 is_stmt 1 view .LVU645 +1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1941 .loc 1 1560 28 is_stmt 0 view .LVU646 + 1942 009e 1023 movs r3, #16 + 1943 00a0 C4F88430 str r3, [r4, #132] +1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1944 .loc 1 1562 11 is_stmt 1 view .LVU647 +1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1945 .loc 1 1562 18 is_stmt 0 view .LVU648 + 1946 00a4 0320 movs r0, #3 + 1947 00a6 00E0 b .L72 + 1948 .LVL167: + 1949 .L75: +1570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 1950 .loc 1 1570 10 view .LVU649 + 1951 00a8 0020 movs r0, #0 + 1952 .L72: +1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1953 .loc 1 1571 1 view .LVU650 + 1954 00aa 38BD pop {r3, r4, r5, pc} +1571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 1955 .loc 1 1571 1 view .LVU651 + 1956 .cfi_endproc + 1957 .LFE156: + 1959 .section .text.HAL_UART_Abort,"ax",%progbits + 1960 .align 1 + 1961 .global HAL_UART_Abort + 1962 .syntax unified + 1963 .thumb + 1964 .thumb_func + 1966 HAL_UART_Abort: + 1967 .LVL168: + 1968 .LFB157: +1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + 1969 .loc 1 1586 1 is_stmt 1 view -0 + 1970 .cfi_startproc + 1971 @ args = 0, pretend = 0, frame = 0 + 1972 @ frame_needed = 0, uses_anonymous_args = 0 +1586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + 1973 .loc 1 1586 1 is_stmt 0 view .LVU653 + 1974 0000 10B5 push {r4, lr} + 1975 .LCFI9: + 1976 .cfi_def_cfa_offset 8 + 1977 .cfi_offset 4, -8 + 1978 .cfi_offset 14, -4 + 1979 0002 0446 mov r4, r0 + 1980 .L81: +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1981 .loc 1 1588 3 is_stmt 1 discriminator 1 view .LVU654 + 1982 .LBB515: + ARM GAS /tmp/ccQxTlMj.s page 132 + + +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1983 .loc 1 1588 3 discriminator 1 view .LVU655 +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1984 .loc 1 1588 3 discriminator 1 view .LVU656 +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 1985 .loc 1 1588 3 discriminator 1 view .LVU657 + 1986 0004 2268 ldr r2, [r4] + 1987 .LVL169: + 1988 .LBB516: + 1989 .LBI516: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1990 .loc 2 1068 31 view .LVU658 + 1991 .LBB517: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1992 .loc 2 1070 5 view .LVU659 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1993 .loc 2 1072 4 view .LVU660 + 1994 .syntax unified + 1995 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1996 0006 52E8003F ldrex r3, [r2] + 1997 @ 0 "" 2 + 1998 .LVL170: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1999 .loc 2 1073 4 view .LVU661 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2000 .loc 2 1073 4 is_stmt 0 view .LVU662 + 2001 .thumb + 2002 .syntax unified + 2003 .LBE517: + 2004 .LBE516: +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 2005 .loc 1 1588 3 discriminator 1 view .LVU663 + 2006 000a 23F4F073 bic r3, r3, #480 + 2007 .LVL171: +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 2008 .loc 1 1588 3 is_stmt 1 discriminator 1 view .LVU664 + 2009 .LBB518: + 2010 .LBI518: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2011 .loc 2 1119 31 view .LVU665 + 2012 .LBB519: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2013 .loc 2 1121 4 view .LVU666 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2014 .loc 2 1123 4 view .LVU667 + 2015 .syntax unified + 2016 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2017 000e 42E80031 strex r1, r3, [r2] + 2018 @ 0 "" 2 + 2019 .LVL172: + 2020 .loc 2 1124 4 view .LVU668 + 2021 .loc 2 1124 4 is_stmt 0 view .LVU669 + 2022 .thumb + 2023 .syntax unified + 2024 .LBE519: + 2025 .LBE518: +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ARM GAS /tmp/ccQxTlMj.s page 133 + + + 2026 .loc 1 1588 3 discriminator 1 view .LVU670 + 2027 0012 0029 cmp r1, #0 + 2028 0014 F6D1 bne .L81 + 2029 .LVL173: + 2030 .L82: +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 2031 .loc 1 1588 3 discriminator 1 view .LVU671 + 2032 .LBE515: +1588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 2033 .loc 1 1588 3 is_stmt 1 discriminator 2 view .LVU672 +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2034 .loc 1 1589 3 discriminator 1 view .LVU673 + 2035 .LBB520: +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2036 .loc 1 1589 3 discriminator 1 view .LVU674 +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2037 .loc 1 1589 3 discriminator 1 view .LVU675 +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2038 .loc 1 1589 3 discriminator 1 view .LVU676 + 2039 0016 2268 ldr r2, [r4] + 2040 .LVL174: + 2041 .LBB521: + 2042 .LBI521: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2043 .loc 2 1068 31 view .LVU677 + 2044 .LBB522: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2045 .loc 2 1070 5 view .LVU678 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2046 .loc 2 1072 4 view .LVU679 + 2047 0018 02F10803 add r3, r2, #8 + 2048 .LVL175: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2049 .loc 2 1072 4 is_stmt 0 view .LVU680 + 2050 .syntax unified + 2051 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2052 001c 53E8003F ldrex r3, [r3] + 2053 @ 0 "" 2 + 2054 .LVL176: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2055 .loc 2 1073 4 is_stmt 1 view .LVU681 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2056 .loc 2 1073 4 is_stmt 0 view .LVU682 + 2057 .thumb + 2058 .syntax unified + 2059 .LBE522: + 2060 .LBE521: +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2061 .loc 1 1589 3 discriminator 1 view .LVU683 + 2062 0020 23F00103 bic r3, r3, #1 + 2063 .LVL177: +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2064 .loc 1 1589 3 is_stmt 1 discriminator 1 view .LVU684 + 2065 .LBB523: + 2066 .LBI523: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2067 .loc 2 1119 31 view .LVU685 + ARM GAS /tmp/ccQxTlMj.s page 134 + + + 2068 .LBB524: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2069 .loc 2 1121 4 view .LVU686 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2070 .loc 2 1123 4 view .LVU687 + 2071 0024 0832 adds r2, r2, #8 + 2072 .LVL178: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2073 .loc 2 1123 4 is_stmt 0 view .LVU688 + 2074 .syntax unified + 2075 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2076 0026 42E80031 strex r1, r3, [r2] + 2077 @ 0 "" 2 + 2078 .LVL179: + 2079 .loc 2 1124 4 is_stmt 1 view .LVU689 + 2080 .loc 2 1124 4 is_stmt 0 view .LVU690 + 2081 .thumb + 2082 .syntax unified + 2083 .LBE524: + 2084 .LBE523: +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2085 .loc 1 1589 3 discriminator 1 view .LVU691 + 2086 002a 0029 cmp r1, #0 + 2087 002c F3D1 bne .L82 + 2088 .LBE520: +1589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2089 .loc 1 1589 3 is_stmt 1 discriminator 2 view .LVU692 +1592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2090 .loc 1 1592 3 view .LVU693 +1592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2091 .loc 1 1592 12 is_stmt 0 view .LVU694 + 2092 002e 236E ldr r3, [r4, #96] + 2093 .LVL180: +1592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2094 .loc 1 1592 6 view .LVU695 + 2095 0030 012B cmp r3, #1 + 2096 0032 47D0 beq .L84 + 2097 .L83: +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2098 .loc 1 1594 5 is_stmt 1 discriminator 2 view .LVU696 +1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2099 .loc 1 1598 3 view .LVU697 +1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2100 .loc 1 1598 7 is_stmt 0 view .LVU698 + 2101 0034 2368 ldr r3, [r4] + 2102 0036 9B68 ldr r3, [r3, #8] +1598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2103 .loc 1 1598 6 view .LVU699 + 2104 0038 13F0800F tst r3, #128 + 2105 003c 14D0 beq .L85 + 2106 .L86: +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2107 .loc 1 1601 5 is_stmt 1 discriminator 1 view .LVU700 + 2108 .LBB525: +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2109 .loc 1 1601 5 discriminator 1 view .LVU701 +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 135 + + + 2110 .loc 1 1601 5 discriminator 1 view .LVU702 +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2111 .loc 1 1601 5 discriminator 1 view .LVU703 + 2112 003e 2268 ldr r2, [r4] + 2113 .LVL181: + 2114 .LBB526: + 2115 .LBI526: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2116 .loc 2 1068 31 view .LVU704 + 2117 .LBB527: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2118 .loc 2 1070 5 view .LVU705 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2119 .loc 2 1072 4 view .LVU706 + 2120 0040 02F10803 add r3, r2, #8 + 2121 .LVL182: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2122 .loc 2 1072 4 is_stmt 0 view .LVU707 + 2123 .syntax unified + 2124 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2125 0044 53E8003F ldrex r3, [r3] + 2126 @ 0 "" 2 + 2127 .LVL183: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2128 .loc 2 1073 4 is_stmt 1 view .LVU708 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2129 .loc 2 1073 4 is_stmt 0 view .LVU709 + 2130 .thumb + 2131 .syntax unified + 2132 .LBE527: + 2133 .LBE526: +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2134 .loc 1 1601 5 discriminator 1 view .LVU710 + 2135 0048 23F08003 bic r3, r3, #128 + 2136 .LVL184: +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2137 .loc 1 1601 5 is_stmt 1 discriminator 1 view .LVU711 + 2138 .LBB528: + 2139 .LBI528: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2140 .loc 2 1119 31 view .LVU712 + 2141 .LBB529: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2142 .loc 2 1121 4 view .LVU713 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2143 .loc 2 1123 4 view .LVU714 + 2144 004c 0832 adds r2, r2, #8 + 2145 .LVL185: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2146 .loc 2 1123 4 is_stmt 0 view .LVU715 + 2147 .syntax unified + 2148 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2149 004e 42E80031 strex r1, r3, [r2] + 2150 @ 0 "" 2 + 2151 .LVL186: + 2152 .loc 2 1124 4 is_stmt 1 view .LVU716 + 2153 .loc 2 1124 4 is_stmt 0 view .LVU717 + ARM GAS /tmp/ccQxTlMj.s page 136 + + + 2154 .thumb + 2155 .syntax unified + 2156 .LBE529: + 2157 .LBE528: +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2158 .loc 1 1601 5 discriminator 1 view .LVU718 + 2159 0052 0029 cmp r1, #0 + 2160 0054 F3D1 bne .L86 + 2161 .LBE525: +1601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2162 .loc 1 1601 5 is_stmt 1 discriminator 2 view .LVU719 +1604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2163 .loc 1 1604 5 view .LVU720 +1604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2164 .loc 1 1604 14 is_stmt 0 view .LVU721 + 2165 0056 236F ldr r3, [r4, #112] + 2166 .LVL187: +1604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2167 .loc 1 1604 8 view .LVU722 + 2168 0058 33B1 cbz r3, .L85 +1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2169 .loc 1 1608 7 is_stmt 1 view .LVU723 +1608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2170 .loc 1 1608 40 is_stmt 0 view .LVU724 + 2171 005a 0022 movs r2, #0 + 2172 005c 1A65 str r2, [r3, #80] +1610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2173 .loc 1 1610 7 is_stmt 1 view .LVU725 +1610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2174 .loc 1 1610 11 is_stmt 0 view .LVU726 + 2175 005e 206F ldr r0, [r4, #112] + 2176 .LVL188: +1610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2177 .loc 1 1610 11 view .LVU727 + 2178 0060 FFF7FEFF bl HAL_DMA_Abort + 2179 .LVL189: +1610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2180 .loc 1 1610 10 discriminator 1 view .LVU728 + 2181 0064 0028 cmp r0, #0 + 2182 0066 37D1 bne .L91 + 2183 .LVL190: + 2184 .L85: +1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2185 .loc 1 1624 3 is_stmt 1 view .LVU729 +1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2186 .loc 1 1624 7 is_stmt 0 view .LVU730 + 2187 0068 2368 ldr r3, [r4] + 2188 006a 9B68 ldr r3, [r3, #8] +1624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2189 .loc 1 1624 6 view .LVU731 + 2190 006c 13F0400F tst r3, #64 + 2191 0070 13D0 beq .L88 + 2192 .L89: +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2193 .loc 1 1627 5 is_stmt 1 discriminator 1 view .LVU732 + 2194 .LBB530: +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 137 + + + 2195 .loc 1 1627 5 discriminator 1 view .LVU733 +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2196 .loc 1 1627 5 discriminator 1 view .LVU734 +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2197 .loc 1 1627 5 discriminator 1 view .LVU735 + 2198 0072 2268 ldr r2, [r4] + 2199 .LVL191: + 2200 .LBB531: + 2201 .LBI531: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2202 .loc 2 1068 31 view .LVU736 + 2203 .LBB532: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2204 .loc 2 1070 5 view .LVU737 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2205 .loc 2 1072 4 view .LVU738 + 2206 0074 02F10803 add r3, r2, #8 + 2207 .LVL192: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2208 .loc 2 1072 4 is_stmt 0 view .LVU739 + 2209 .syntax unified + 2210 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2211 0078 53E8003F ldrex r3, [r3] + 2212 @ 0 "" 2 + 2213 .LVL193: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2214 .loc 2 1073 4 is_stmt 1 view .LVU740 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2215 .loc 2 1073 4 is_stmt 0 view .LVU741 + 2216 .thumb + 2217 .syntax unified + 2218 .LBE532: + 2219 .LBE531: +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2220 .loc 1 1627 5 discriminator 1 view .LVU742 + 2221 007c 23F04003 bic r3, r3, #64 + 2222 .LVL194: +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2223 .loc 1 1627 5 is_stmt 1 discriminator 1 view .LVU743 + 2224 .LBB533: + 2225 .LBI533: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2226 .loc 2 1119 31 view .LVU744 + 2227 .LBB534: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2228 .loc 2 1121 4 view .LVU745 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2229 .loc 2 1123 4 view .LVU746 + 2230 0080 0832 adds r2, r2, #8 + 2231 .LVL195: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2232 .loc 2 1123 4 is_stmt 0 view .LVU747 + 2233 .syntax unified + 2234 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2235 0082 42E80031 strex r1, r3, [r2] + 2236 @ 0 "" 2 + 2237 .LVL196: + ARM GAS /tmp/ccQxTlMj.s page 138 + + + 2238 .loc 2 1124 4 is_stmt 1 view .LVU748 + 2239 .loc 2 1124 4 is_stmt 0 view .LVU749 + 2240 .thumb + 2241 .syntax unified + 2242 .LBE534: + 2243 .LBE533: +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2244 .loc 1 1627 5 discriminator 1 view .LVU750 + 2245 0086 0029 cmp r1, #0 + 2246 0088 F3D1 bne .L89 + 2247 .LBE530: +1627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2248 .loc 1 1627 5 is_stmt 1 discriminator 2 view .LVU751 +1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2249 .loc 1 1630 5 view .LVU752 +1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2250 .loc 1 1630 14 is_stmt 0 view .LVU753 + 2251 008a 636F ldr r3, [r4, #116] + 2252 .LVL197: +1630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2253 .loc 1 1630 8 view .LVU754 + 2254 008c 2BB1 cbz r3, .L88 +1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2255 .loc 1 1634 7 is_stmt 1 view .LVU755 +1634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2256 .loc 1 1634 40 is_stmt 0 view .LVU756 + 2257 008e 0022 movs r2, #0 + 2258 0090 1A65 str r2, [r3, #80] +1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2259 .loc 1 1636 7 is_stmt 1 view .LVU757 +1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2260 .loc 1 1636 11 is_stmt 0 view .LVU758 + 2261 0092 606F ldr r0, [r4, #116] + 2262 0094 FFF7FEFF bl HAL_DMA_Abort + 2263 .LVL198: +1636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2264 .loc 1 1636 10 discriminator 1 view .LVU759 + 2265 0098 40BB cbnz r0, .L92 + 2266 .LVL199: + 2267 .L88: +1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; + 2268 .loc 1 1650 3 is_stmt 1 view .LVU760 +1650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; + 2269 .loc 1 1650 22 is_stmt 0 view .LVU761 + 2270 009a 0020 movs r0, #0 + 2271 009c A4F85200 strh r0, [r4, #82] @ movhi +1651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2272 .loc 1 1651 3 is_stmt 1 view .LVU762 +1651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2273 .loc 1 1651 22 is_stmt 0 view .LVU763 + 2274 00a0 A4F85A00 strh r0, [r4, #90] @ movhi +1654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2275 .loc 1 1654 3 is_stmt 1 view .LVU764 + 2276 00a4 2368 ldr r3, [r4] + 2277 00a6 0F22 movs r2, #15 + 2278 00a8 1A62 str r2, [r3, #32] +1658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 139 + + + 2279 .loc 1 1658 3 view .LVU765 + 2280 00aa 2268 ldr r2, [r4] + 2281 00ac 9369 ldr r3, [r2, #24] + 2282 00ae 43F00803 orr r3, r3, #8 + 2283 00b2 9361 str r3, [r2, #24] +1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 2284 .loc 1 1661 3 view .LVU766 +1661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 2285 .loc 1 1661 18 is_stmt 0 view .LVU767 + 2286 00b4 2023 movs r3, #32 + 2287 00b6 E367 str r3, [r4, #124] +1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 2288 .loc 1 1662 3 is_stmt 1 view .LVU768 +1662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 2289 .loc 1 1662 18 is_stmt 0 view .LVU769 + 2290 00b8 C4F88030 str r3, [r4, #128] +1663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2291 .loc 1 1663 3 is_stmt 1 view .LVU770 +1663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2292 .loc 1 1663 24 is_stmt 0 view .LVU771 + 2293 00bc 2066 str r0, [r4, #96] +1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2294 .loc 1 1665 3 is_stmt 1 view .LVU772 +1665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2295 .loc 1 1665 20 is_stmt 0 view .LVU773 + 2296 00be C4F88400 str r0, [r4, #132] +1667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2297 .loc 1 1667 3 is_stmt 1 view .LVU774 + 2298 .L87: +1668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2299 .loc 1 1668 1 is_stmt 0 view .LVU775 + 2300 00c2 10BD pop {r4, pc} + 2301 .LVL200: + 2302 .L84: +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2303 .loc 1 1594 5 is_stmt 1 discriminator 1 view .LVU776 + 2304 .LBB535: +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2305 .loc 1 1594 5 discriminator 1 view .LVU777 +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2306 .loc 1 1594 5 discriminator 1 view .LVU778 +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2307 .loc 1 1594 5 discriminator 1 view .LVU779 + 2308 00c4 2268 ldr r2, [r4] + 2309 .LVL201: + 2310 .LBB536: + 2311 .LBI536: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2312 .loc 2 1068 31 view .LVU780 + 2313 .LBB537: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2314 .loc 2 1070 5 view .LVU781 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2315 .loc 2 1072 4 view .LVU782 + 2316 .syntax unified + 2317 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2318 00c6 52E8003F ldrex r3, [r2] + ARM GAS /tmp/ccQxTlMj.s page 140 + + + 2319 @ 0 "" 2 + 2320 .LVL202: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2321 .loc 2 1073 4 view .LVU783 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2322 .loc 2 1073 4 is_stmt 0 view .LVU784 + 2323 .thumb + 2324 .syntax unified + 2325 .LBE537: + 2326 .LBE536: +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2327 .loc 1 1594 5 discriminator 1 view .LVU785 + 2328 00ca 23F01003 bic r3, r3, #16 + 2329 .LVL203: +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2330 .loc 1 1594 5 is_stmt 1 discriminator 1 view .LVU786 + 2331 .LBB538: + 2332 .LBI538: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2333 .loc 2 1119 31 view .LVU787 + 2334 .LBB539: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2335 .loc 2 1121 4 view .LVU788 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2336 .loc 2 1123 4 view .LVU789 + 2337 .syntax unified + 2338 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2339 00ce 42E80031 strex r1, r3, [r2] + 2340 @ 0 "" 2 + 2341 .LVL204: + 2342 .loc 2 1124 4 view .LVU790 + 2343 .loc 2 1124 4 is_stmt 0 view .LVU791 + 2344 .thumb + 2345 .syntax unified + 2346 .LBE539: + 2347 .LBE538: +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2348 .loc 1 1594 5 discriminator 1 view .LVU792 + 2349 00d2 0029 cmp r1, #0 + 2350 00d4 F6D1 bne .L84 + 2351 00d6 ADE7 b .L83 + 2352 .LVL205: + 2353 .L91: +1594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2354 .loc 1 1594 5 discriminator 1 view .LVU793 + 2355 .LBE535: +1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2356 .loc 1 1612 9 is_stmt 1 view .LVU794 +1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2357 .loc 1 1612 13 is_stmt 0 view .LVU795 + 2358 00d8 206F ldr r0, [r4, #112] + 2359 00da FFF7FEFF bl HAL_DMA_GetError + 2360 .LVL206: +1612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2361 .loc 1 1612 12 discriminator 1 view .LVU796 + 2362 00de 2028 cmp r0, #32 + 2363 00e0 C2D1 bne .L85 + ARM GAS /tmp/ccQxTlMj.s page 141 + + +1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2364 .loc 1 1615 11 is_stmt 1 view .LVU797 +1615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2365 .loc 1 1615 28 is_stmt 0 view .LVU798 + 2366 00e2 1023 movs r3, #16 + 2367 00e4 C4F88430 str r3, [r4, #132] +1617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2368 .loc 1 1617 11 is_stmt 1 view .LVU799 +1617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2369 .loc 1 1617 18 is_stmt 0 view .LVU800 + 2370 00e8 0320 movs r0, #3 + 2371 00ea EAE7 b .L87 + 2372 .LVL207: + 2373 .L92: +1638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2374 .loc 1 1638 9 is_stmt 1 view .LVU801 +1638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2375 .loc 1 1638 13 is_stmt 0 view .LVU802 + 2376 00ec 606F ldr r0, [r4, #116] + 2377 00ee FFF7FEFF bl HAL_DMA_GetError + 2378 .LVL208: +1638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2379 .loc 1 1638 12 discriminator 1 view .LVU803 + 2380 00f2 2028 cmp r0, #32 + 2381 00f4 D1D1 bne .L88 +1641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2382 .loc 1 1641 11 is_stmt 1 view .LVU804 +1641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2383 .loc 1 1641 28 is_stmt 0 view .LVU805 + 2384 00f6 1023 movs r3, #16 + 2385 00f8 C4F88430 str r3, [r4, #132] +1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2386 .loc 1 1643 11 is_stmt 1 view .LVU806 +1643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2387 .loc 1 1643 18 is_stmt 0 view .LVU807 + 2388 00fc 0320 movs r0, #3 + 2389 00fe E0E7 b .L87 + 2390 .cfi_endproc + 2391 .LFE157: + 2393 .section .text.HAL_UART_AbortTransmit,"ax",%progbits + 2394 .align 1 + 2395 .global HAL_UART_AbortTransmit + 2396 .syntax unified + 2397 .thumb + 2398 .thumb_func + 2400 HAL_UART_AbortTransmit: + 2401 .LVL209: + 2402 .LFB158: +1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable TXEIE and TCIE interrupts */ + 2403 .loc 1 1683 1 is_stmt 1 view -0 + 2404 .cfi_startproc + 2405 @ args = 0, pretend = 0, frame = 0 + 2406 @ frame_needed = 0, uses_anonymous_args = 0 +1683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable TXEIE and TCIE interrupts */ + 2407 .loc 1 1683 1 is_stmt 0 view .LVU809 + 2408 0000 10B5 push {r4, lr} + 2409 .LCFI10: + ARM GAS /tmp/ccQxTlMj.s page 142 + + + 2410 .cfi_def_cfa_offset 8 + 2411 .cfi_offset 4, -8 + 2412 .cfi_offset 14, -4 + 2413 0002 0446 mov r4, r0 + 2414 .L94: +1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2415 .loc 1 1685 3 is_stmt 1 discriminator 1 view .LVU810 + 2416 .LBB540: +1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2417 .loc 1 1685 3 discriminator 1 view .LVU811 +1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2418 .loc 1 1685 3 discriminator 1 view .LVU812 +1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2419 .loc 1 1685 3 discriminator 1 view .LVU813 + 2420 0004 2268 ldr r2, [r4] + 2421 .LVL210: + 2422 .LBB541: + 2423 .LBI541: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2424 .loc 2 1068 31 view .LVU814 + 2425 .LBB542: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2426 .loc 2 1070 5 view .LVU815 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2427 .loc 2 1072 4 view .LVU816 + 2428 .syntax unified + 2429 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2430 0006 52E8003F ldrex r3, [r2] + 2431 @ 0 "" 2 + 2432 .LVL211: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2433 .loc 2 1073 4 view .LVU817 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2434 .loc 2 1073 4 is_stmt 0 view .LVU818 + 2435 .thumb + 2436 .syntax unified + 2437 .LBE542: + 2438 .LBE541: +1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2439 .loc 1 1685 3 discriminator 1 view .LVU819 + 2440 000a 23F0C003 bic r3, r3, #192 + 2441 .LVL212: +1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2442 .loc 1 1685 3 is_stmt 1 discriminator 1 view .LVU820 + 2443 .LBB543: + 2444 .LBI543: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2445 .loc 2 1119 31 view .LVU821 + 2446 .LBB544: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2447 .loc 2 1121 4 view .LVU822 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2448 .loc 2 1123 4 view .LVU823 + 2449 .syntax unified + 2450 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2451 000e 42E80031 strex r1, r3, [r2] + 2452 @ 0 "" 2 + ARM GAS /tmp/ccQxTlMj.s page 143 + + + 2453 .LVL213: + 2454 .loc 2 1124 4 view .LVU824 + 2455 .loc 2 1124 4 is_stmt 0 view .LVU825 + 2456 .thumb + 2457 .syntax unified + 2458 .LBE544: + 2459 .LBE543: +1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2460 .loc 1 1685 3 discriminator 1 view .LVU826 + 2461 0012 0029 cmp r1, #0 + 2462 0014 F6D1 bne .L94 + 2463 .LBE540: +1685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2464 .loc 1 1685 3 is_stmt 1 discriminator 2 view .LVU827 +1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2465 .loc 1 1688 3 view .LVU828 +1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2466 .loc 1 1688 7 is_stmt 0 view .LVU829 + 2467 0016 2368 ldr r3, [r4] + 2468 .LVL214: +1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2469 .loc 1 1688 7 view .LVU830 + 2470 0018 9B68 ldr r3, [r3, #8] +1688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2471 .loc 1 1688 6 view .LVU831 + 2472 001a 13F0800F tst r3, #128 + 2473 001e 13D0 beq .L95 + 2474 .L96: +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2475 .loc 1 1691 5 is_stmt 1 discriminator 1 view .LVU832 + 2476 .LBB545: +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2477 .loc 1 1691 5 discriminator 1 view .LVU833 +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2478 .loc 1 1691 5 discriminator 1 view .LVU834 +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2479 .loc 1 1691 5 discriminator 1 view .LVU835 + 2480 0020 2268 ldr r2, [r4] + 2481 .LVL215: + 2482 .LBB546: + 2483 .LBI546: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2484 .loc 2 1068 31 view .LVU836 + 2485 .LBB547: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2486 .loc 2 1070 5 view .LVU837 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2487 .loc 2 1072 4 view .LVU838 + 2488 0022 02F10803 add r3, r2, #8 + 2489 .LVL216: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2490 .loc 2 1072 4 is_stmt 0 view .LVU839 + 2491 .syntax unified + 2492 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2493 0026 53E8003F ldrex r3, [r3] + 2494 @ 0 "" 2 + 2495 .LVL217: + ARM GAS /tmp/ccQxTlMj.s page 144 + + +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2496 .loc 2 1073 4 is_stmt 1 view .LVU840 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2497 .loc 2 1073 4 is_stmt 0 view .LVU841 + 2498 .thumb + 2499 .syntax unified + 2500 .LBE547: + 2501 .LBE546: +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2502 .loc 1 1691 5 discriminator 1 view .LVU842 + 2503 002a 23F08003 bic r3, r3, #128 + 2504 .LVL218: +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2505 .loc 1 1691 5 is_stmt 1 discriminator 1 view .LVU843 + 2506 .LBB548: + 2507 .LBI548: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2508 .loc 2 1119 31 view .LVU844 + 2509 .LBB549: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2510 .loc 2 1121 4 view .LVU845 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2511 .loc 2 1123 4 view .LVU846 + 2512 002e 0832 adds r2, r2, #8 + 2513 .LVL219: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2514 .loc 2 1123 4 is_stmt 0 view .LVU847 + 2515 .syntax unified + 2516 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2517 0030 42E80031 strex r1, r3, [r2] + 2518 @ 0 "" 2 + 2519 .LVL220: + 2520 .loc 2 1124 4 is_stmt 1 view .LVU848 + 2521 .loc 2 1124 4 is_stmt 0 view .LVU849 + 2522 .thumb + 2523 .syntax unified + 2524 .LBE549: + 2525 .LBE548: +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2526 .loc 1 1691 5 discriminator 1 view .LVU850 + 2527 0034 0029 cmp r1, #0 + 2528 0036 F3D1 bne .L96 + 2529 .LBE545: +1691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2530 .loc 1 1691 5 is_stmt 1 discriminator 2 view .LVU851 +1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2531 .loc 1 1694 5 view .LVU852 +1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2532 .loc 1 1694 14 is_stmt 0 view .LVU853 + 2533 0038 236F ldr r3, [r4, #112] + 2534 .LVL221: +1694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2535 .loc 1 1694 8 view .LVU854 + 2536 003a 2BB1 cbz r3, .L95 +1698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2537 .loc 1 1698 7 is_stmt 1 view .LVU855 +1698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 145 + + + 2538 .loc 1 1698 40 is_stmt 0 view .LVU856 + 2539 003c 0022 movs r2, #0 + 2540 003e 1A65 str r2, [r3, #80] +1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2541 .loc 1 1700 7 is_stmt 1 view .LVU857 +1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2542 .loc 1 1700 11 is_stmt 0 view .LVU858 + 2543 0040 206F ldr r0, [r4, #112] + 2544 .LVL222: +1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2545 .loc 1 1700 11 view .LVU859 + 2546 0042 FFF7FEFF bl HAL_DMA_Abort + 2547 .LVL223: +1700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2548 .loc 1 1700 10 discriminator 1 view .LVU860 + 2549 0046 28B9 cbnz r0, .L99 + 2550 .LVL224: + 2551 .L95: +1714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2552 .loc 1 1714 3 is_stmt 1 view .LVU861 +1714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2553 .loc 1 1714 22 is_stmt 0 view .LVU862 + 2554 0048 0020 movs r0, #0 + 2555 004a A4F85200 strh r0, [r4, #82] @ movhi +1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2556 .loc 1 1718 3 is_stmt 1 view .LVU863 +1718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2557 .loc 1 1718 17 is_stmt 0 view .LVU864 + 2558 004e 2023 movs r3, #32 + 2559 0050 E367 str r3, [r4, #124] +1720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2560 .loc 1 1720 3 is_stmt 1 view .LVU865 + 2561 .L97: +1721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2562 .loc 1 1721 1 is_stmt 0 view .LVU866 + 2563 0052 10BD pop {r4, pc} + 2564 .LVL225: + 2565 .L99: +1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2566 .loc 1 1702 9 is_stmt 1 view .LVU867 +1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2567 .loc 1 1702 13 is_stmt 0 view .LVU868 + 2568 0054 206F ldr r0, [r4, #112] + 2569 0056 FFF7FEFF bl HAL_DMA_GetError + 2570 .LVL226: +1702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2571 .loc 1 1702 12 discriminator 1 view .LVU869 + 2572 005a 2028 cmp r0, #32 + 2573 005c F4D1 bne .L95 +1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2574 .loc 1 1705 11 is_stmt 1 view .LVU870 +1705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2575 .loc 1 1705 28 is_stmt 0 view .LVU871 + 2576 005e 1023 movs r3, #16 + 2577 0060 C4F88430 str r3, [r4, #132] +1707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2578 .loc 1 1707 11 is_stmt 1 view .LVU872 + ARM GAS /tmp/ccQxTlMj.s page 146 + + +1707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2579 .loc 1 1707 18 is_stmt 0 view .LVU873 + 2580 0064 0320 movs r0, #3 + 2581 0066 F4E7 b .L97 + 2582 .cfi_endproc + 2583 .LFE158: + 2585 .section .text.HAL_UART_AbortReceive,"ax",%progbits + 2586 .align 1 + 2587 .global HAL_UART_AbortReceive + 2588 .syntax unified + 2589 .thumb + 2590 .thumb_func + 2592 HAL_UART_AbortReceive: + 2593 .LVL227: + 2594 .LFB159: +1736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + 2595 .loc 1 1736 1 is_stmt 1 view -0 + 2596 .cfi_startproc + 2597 @ args = 0, pretend = 0, frame = 0 + 2598 @ frame_needed = 0, uses_anonymous_args = 0 +1736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + 2599 .loc 1 1736 1 is_stmt 0 view .LVU875 + 2600 0000 10B5 push {r4, lr} + 2601 .LCFI11: + 2602 .cfi_def_cfa_offset 8 + 2603 .cfi_offset 4, -8 + 2604 .cfi_offset 14, -4 + 2605 0002 0446 mov r4, r0 + 2606 .L101: +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 2607 .loc 1 1738 3 is_stmt 1 discriminator 1 view .LVU876 + 2608 .LBB550: +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 2609 .loc 1 1738 3 discriminator 1 view .LVU877 +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 2610 .loc 1 1738 3 discriminator 1 view .LVU878 +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 2611 .loc 1 1738 3 discriminator 1 view .LVU879 + 2612 0004 2268 ldr r2, [r4] + 2613 .LVL228: + 2614 .LBB551: + 2615 .LBI551: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2616 .loc 2 1068 31 view .LVU880 + 2617 .LBB552: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2618 .loc 2 1070 5 view .LVU881 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2619 .loc 2 1072 4 view .LVU882 + 2620 .syntax unified + 2621 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2622 0006 52E8003F ldrex r3, [r2] + 2623 @ 0 "" 2 + 2624 .LVL229: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2625 .loc 2 1073 4 view .LVU883 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccQxTlMj.s page 147 + + + 2626 .loc 2 1073 4 is_stmt 0 view .LVU884 + 2627 .thumb + 2628 .syntax unified + 2629 .LBE552: + 2630 .LBE551: +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 2631 .loc 1 1738 3 discriminator 1 view .LVU885 + 2632 000a 23F49073 bic r3, r3, #288 + 2633 .LVL230: +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 2634 .loc 1 1738 3 is_stmt 1 discriminator 1 view .LVU886 + 2635 .LBB553: + 2636 .LBI553: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2637 .loc 2 1119 31 view .LVU887 + 2638 .LBB554: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2639 .loc 2 1121 4 view .LVU888 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2640 .loc 2 1123 4 view .LVU889 + 2641 .syntax unified + 2642 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2643 000e 42E80031 strex r1, r3, [r2] + 2644 @ 0 "" 2 + 2645 .LVL231: + 2646 .loc 2 1124 4 view .LVU890 + 2647 .loc 2 1124 4 is_stmt 0 view .LVU891 + 2648 .thumb + 2649 .syntax unified + 2650 .LBE554: + 2651 .LBE553: +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 2652 .loc 1 1738 3 discriminator 1 view .LVU892 + 2653 0012 0029 cmp r1, #0 + 2654 0014 F6D1 bne .L101 + 2655 .LVL232: + 2656 .L102: +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 2657 .loc 1 1738 3 discriminator 1 view .LVU893 + 2658 .LBE550: +1738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 2659 .loc 1 1738 3 is_stmt 1 discriminator 2 view .LVU894 +1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2660 .loc 1 1739 3 discriminator 1 view .LVU895 + 2661 .LBB555: +1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2662 .loc 1 1739 3 discriminator 1 view .LVU896 +1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2663 .loc 1 1739 3 discriminator 1 view .LVU897 +1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2664 .loc 1 1739 3 discriminator 1 view .LVU898 + 2665 0016 2268 ldr r2, [r4] + 2666 .LVL233: + 2667 .LBB556: + 2668 .LBI556: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2669 .loc 2 1068 31 view .LVU899 + ARM GAS /tmp/ccQxTlMj.s page 148 + + + 2670 .LBB557: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2671 .loc 2 1070 5 view .LVU900 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2672 .loc 2 1072 4 view .LVU901 + 2673 0018 02F10803 add r3, r2, #8 + 2674 .LVL234: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2675 .loc 2 1072 4 is_stmt 0 view .LVU902 + 2676 .syntax unified + 2677 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2678 001c 53E8003F ldrex r3, [r3] + 2679 @ 0 "" 2 + 2680 .LVL235: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2681 .loc 2 1073 4 is_stmt 1 view .LVU903 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2682 .loc 2 1073 4 is_stmt 0 view .LVU904 + 2683 .thumb + 2684 .syntax unified + 2685 .LBE557: + 2686 .LBE556: +1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2687 .loc 1 1739 3 discriminator 1 view .LVU905 + 2688 0020 23F00103 bic r3, r3, #1 + 2689 .LVL236: +1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2690 .loc 1 1739 3 is_stmt 1 discriminator 1 view .LVU906 + 2691 .LBB558: + 2692 .LBI558: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2693 .loc 2 1119 31 view .LVU907 + 2694 .LBB559: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2695 .loc 2 1121 4 view .LVU908 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2696 .loc 2 1123 4 view .LVU909 + 2697 0024 0832 adds r2, r2, #8 + 2698 .LVL237: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2699 .loc 2 1123 4 is_stmt 0 view .LVU910 + 2700 .syntax unified + 2701 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2702 0026 42E80031 strex r1, r3, [r2] + 2703 @ 0 "" 2 + 2704 .LVL238: + 2705 .loc 2 1124 4 is_stmt 1 view .LVU911 + 2706 .loc 2 1124 4 is_stmt 0 view .LVU912 + 2707 .thumb + 2708 .syntax unified + 2709 .LBE559: + 2710 .LBE558: +1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2711 .loc 1 1739 3 discriminator 1 view .LVU913 + 2712 002a 0029 cmp r1, #0 + 2713 002c F3D1 bne .L102 + 2714 .LBE555: + ARM GAS /tmp/ccQxTlMj.s page 149 + + +1739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2715 .loc 1 1739 3 is_stmt 1 discriminator 2 view .LVU914 +1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2716 .loc 1 1742 3 view .LVU915 +1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2717 .loc 1 1742 12 is_stmt 0 view .LVU916 + 2718 002e 236E ldr r3, [r4, #96] + 2719 .LVL239: +1742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2720 .loc 1 1742 6 view .LVU917 + 2721 0030 012B cmp r3, #1 + 2722 0032 28D0 beq .L104 + 2723 .L103: +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2724 .loc 1 1744 5 is_stmt 1 discriminator 2 view .LVU918 +1748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2725 .loc 1 1748 3 view .LVU919 +1748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2726 .loc 1 1748 7 is_stmt 0 view .LVU920 + 2727 0034 2368 ldr r3, [r4] + 2728 0036 9B68 ldr r3, [r3, #8] +1748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2729 .loc 1 1748 6 view .LVU921 + 2730 0038 13F0400F tst r3, #64 + 2731 003c 13D0 beq .L105 + 2732 .L106: +1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2733 .loc 1 1751 5 is_stmt 1 discriminator 1 view .LVU922 + 2734 .LBB560: +1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2735 .loc 1 1751 5 discriminator 1 view .LVU923 +1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2736 .loc 1 1751 5 discriminator 1 view .LVU924 +1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2737 .loc 1 1751 5 discriminator 1 view .LVU925 + 2738 003e 2268 ldr r2, [r4] + 2739 .LVL240: + 2740 .LBB561: + 2741 .LBI561: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2742 .loc 2 1068 31 view .LVU926 + 2743 .LBB562: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2744 .loc 2 1070 5 view .LVU927 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2745 .loc 2 1072 4 view .LVU928 + 2746 0040 02F10803 add r3, r2, #8 + 2747 .LVL241: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2748 .loc 2 1072 4 is_stmt 0 view .LVU929 + 2749 .syntax unified + 2750 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2751 0044 53E8003F ldrex r3, [r3] + 2752 @ 0 "" 2 + 2753 .LVL242: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2754 .loc 2 1073 4 is_stmt 1 view .LVU930 + ARM GAS /tmp/ccQxTlMj.s page 150 + + +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2755 .loc 2 1073 4 is_stmt 0 view .LVU931 + 2756 .thumb + 2757 .syntax unified + 2758 .LBE562: + 2759 .LBE561: +1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2760 .loc 1 1751 5 discriminator 1 view .LVU932 + 2761 0048 23F04003 bic r3, r3, #64 + 2762 .LVL243: +1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2763 .loc 1 1751 5 is_stmt 1 discriminator 1 view .LVU933 + 2764 .LBB563: + 2765 .LBI563: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2766 .loc 2 1119 31 view .LVU934 + 2767 .LBB564: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2768 .loc 2 1121 4 view .LVU935 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2769 .loc 2 1123 4 view .LVU936 + 2770 004c 0832 adds r2, r2, #8 + 2771 .LVL244: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2772 .loc 2 1123 4 is_stmt 0 view .LVU937 + 2773 .syntax unified + 2774 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2775 004e 42E80031 strex r1, r3, [r2] + 2776 @ 0 "" 2 + 2777 .LVL245: + 2778 .loc 2 1124 4 is_stmt 1 view .LVU938 + 2779 .loc 2 1124 4 is_stmt 0 view .LVU939 + 2780 .thumb + 2781 .syntax unified + 2782 .LBE564: + 2783 .LBE563: +1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2784 .loc 1 1751 5 discriminator 1 view .LVU940 + 2785 0052 0029 cmp r1, #0 + 2786 0054 F3D1 bne .L106 + 2787 .LBE560: +1751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2788 .loc 1 1751 5 is_stmt 1 discriminator 2 view .LVU941 +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2789 .loc 1 1754 5 view .LVU942 +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2790 .loc 1 1754 14 is_stmt 0 view .LVU943 + 2791 0056 636F ldr r3, [r4, #116] + 2792 .LVL246: +1754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2793 .loc 1 1754 8 view .LVU944 + 2794 0058 2BB1 cbz r3, .L105 +1758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2795 .loc 1 1758 7 is_stmt 1 view .LVU945 +1758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2796 .loc 1 1758 40 is_stmt 0 view .LVU946 + 2797 005a 0022 movs r2, #0 + ARM GAS /tmp/ccQxTlMj.s page 151 + + + 2798 005c 1A65 str r2, [r3, #80] +1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2799 .loc 1 1760 7 is_stmt 1 view .LVU947 +1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2800 .loc 1 1760 11 is_stmt 0 view .LVU948 + 2801 005e 606F ldr r0, [r4, #116] + 2802 .LVL247: +1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2803 .loc 1 1760 11 view .LVU949 + 2804 0060 FFF7FEFF bl HAL_DMA_Abort + 2805 .LVL248: +1760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2806 .loc 1 1760 10 discriminator 1 view .LVU950 + 2807 0064 C8B9 cbnz r0, .L109 + 2808 .LVL249: + 2809 .L105: +1774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2810 .loc 1 1774 3 is_stmt 1 view .LVU951 +1774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2811 .loc 1 1774 22 is_stmt 0 view .LVU952 + 2812 0066 0020 movs r0, #0 + 2813 0068 A4F85A00 strh r0, [r4, #90] @ movhi +1777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2814 .loc 1 1777 3 is_stmt 1 view .LVU953 + 2815 006c 2368 ldr r3, [r4] + 2816 006e 0F22 movs r2, #15 + 2817 0070 1A62 str r2, [r3, #32] +1780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2818 .loc 1 1780 3 view .LVU954 + 2819 0072 2268 ldr r2, [r4] + 2820 0074 9369 ldr r3, [r2, #24] + 2821 0076 43F00803 orr r3, r3, #8 + 2822 007a 9361 str r3, [r2, #24] +1783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 2823 .loc 1 1783 3 view .LVU955 +1783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 2824 .loc 1 1783 18 is_stmt 0 view .LVU956 + 2825 007c 2023 movs r3, #32 + 2826 007e C4F88030 str r3, [r4, #128] +1784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2827 .loc 1 1784 3 is_stmt 1 view .LVU957 +1784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2828 .loc 1 1784 24 is_stmt 0 view .LVU958 + 2829 0082 2066 str r0, [r4, #96] +1786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2830 .loc 1 1786 3 is_stmt 1 view .LVU959 + 2831 .L107: +1787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2832 .loc 1 1787 1 is_stmt 0 view .LVU960 + 2833 0084 10BD pop {r4, pc} + 2834 .LVL250: + 2835 .L104: +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2836 .loc 1 1744 5 is_stmt 1 discriminator 1 view .LVU961 + 2837 .LBB565: +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2838 .loc 1 1744 5 discriminator 1 view .LVU962 + ARM GAS /tmp/ccQxTlMj.s page 152 + + +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2839 .loc 1 1744 5 discriminator 1 view .LVU963 +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2840 .loc 1 1744 5 discriminator 1 view .LVU964 + 2841 0086 2268 ldr r2, [r4] + 2842 .LVL251: + 2843 .LBB566: + 2844 .LBI566: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2845 .loc 2 1068 31 view .LVU965 + 2846 .LBB567: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2847 .loc 2 1070 5 view .LVU966 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2848 .loc 2 1072 4 view .LVU967 + 2849 .syntax unified + 2850 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2851 0088 52E8003F ldrex r3, [r2] + 2852 @ 0 "" 2 + 2853 .LVL252: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2854 .loc 2 1073 4 view .LVU968 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2855 .loc 2 1073 4 is_stmt 0 view .LVU969 + 2856 .thumb + 2857 .syntax unified + 2858 .LBE567: + 2859 .LBE566: +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2860 .loc 1 1744 5 discriminator 1 view .LVU970 + 2861 008c 23F01003 bic r3, r3, #16 + 2862 .LVL253: +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2863 .loc 1 1744 5 is_stmt 1 discriminator 1 view .LVU971 + 2864 .LBB568: + 2865 .LBI568: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2866 .loc 2 1119 31 view .LVU972 + 2867 .LBB569: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2868 .loc 2 1121 4 view .LVU973 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2869 .loc 2 1123 4 view .LVU974 + 2870 .syntax unified + 2871 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2872 0090 42E80031 strex r1, r3, [r2] + 2873 @ 0 "" 2 + 2874 .LVL254: + 2875 .loc 2 1124 4 view .LVU975 + 2876 .loc 2 1124 4 is_stmt 0 view .LVU976 + 2877 .thumb + 2878 .syntax unified + 2879 .LBE569: + 2880 .LBE568: +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2881 .loc 1 1744 5 discriminator 1 view .LVU977 + 2882 0094 0029 cmp r1, #0 + ARM GAS /tmp/ccQxTlMj.s page 153 + + + 2883 0096 F6D1 bne .L104 + 2884 0098 CCE7 b .L103 + 2885 .LVL255: + 2886 .L109: +1744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2887 .loc 1 1744 5 discriminator 1 view .LVU978 + 2888 .LBE565: +1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2889 .loc 1 1762 9 is_stmt 1 view .LVU979 +1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2890 .loc 1 1762 13 is_stmt 0 view .LVU980 + 2891 009a 606F ldr r0, [r4, #116] + 2892 009c FFF7FEFF bl HAL_DMA_GetError + 2893 .LVL256: +1762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2894 .loc 1 1762 12 discriminator 1 view .LVU981 + 2895 00a0 2028 cmp r0, #32 + 2896 00a2 E0D1 bne .L105 +1765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2897 .loc 1 1765 11 is_stmt 1 view .LVU982 +1765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2898 .loc 1 1765 28 is_stmt 0 view .LVU983 + 2899 00a4 1023 movs r3, #16 + 2900 00a6 C4F88430 str r3, [r4, #132] +1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2901 .loc 1 1767 11 is_stmt 1 view .LVU984 +1767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 2902 .loc 1 1767 18 is_stmt 0 view .LVU985 + 2903 00aa 0320 movs r0, #3 + 2904 00ac EAE7 b .L107 + 2905 .cfi_endproc + 2906 .LFE159: + 2908 .section .text.HAL_UART_TxCpltCallback,"ax",%progbits + 2909 .align 1 + 2910 .weak HAL_UART_TxCpltCallback + 2911 .syntax unified + 2912 .thumb + 2913 .thumb_func + 2915 HAL_UART_TxCpltCallback: + 2916 .LVL257: + 2917 .LFB164: +2435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 2918 .loc 1 2435 1 is_stmt 1 view -0 + 2919 .cfi_startproc + 2920 @ args = 0, pretend = 0, frame = 0 + 2921 @ frame_needed = 0, uses_anonymous_args = 0 + 2922 @ link register save eliminated. +2437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2923 .loc 1 2437 3 view .LVU987 +2442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2924 .loc 1 2442 1 is_stmt 0 view .LVU988 + 2925 0000 7047 bx lr + 2926 .cfi_endproc + 2927 .LFE164: + 2929 .section .text.UART_DMATransmitCplt,"ax",%progbits + 2930 .align 1 + 2931 .syntax unified + ARM GAS /tmp/ccQxTlMj.s page 154 + + + 2932 .thumb + 2933 .thumb_func + 2935 UART_DMATransmitCplt: + 2936 .LVL258: + 2937 .LFB193: +3406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 2938 .loc 1 3406 1 is_stmt 1 view -0 + 2939 .cfi_startproc + 2940 @ args = 0, pretend = 0, frame = 0 + 2941 @ frame_needed = 0, uses_anonymous_args = 0 +3406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 2942 .loc 1 3406 1 is_stmt 0 view .LVU990 + 2943 0000 08B5 push {r3, lr} + 2944 .LCFI12: + 2945 .cfi_def_cfa_offset 8 + 2946 .cfi_offset 3, -8 + 2947 .cfi_offset 14, -4 +3407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2948 .loc 1 3407 3 is_stmt 1 view .LVU991 +3407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2949 .loc 1 3407 23 is_stmt 0 view .LVU992 + 2950 0002 816B ldr r1, [r0, #56] + 2951 .LVL259: +3410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2952 .loc 1 3410 3 is_stmt 1 view .LVU993 +3410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2953 .loc 1 3410 17 is_stmt 0 view .LVU994 + 2954 0004 C369 ldr r3, [r0, #28] +3410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 2955 .loc 1 3410 6 view .LVU995 + 2956 0006 B3F5807F cmp r3, #256 + 2957 000a 18D0 beq .L112 +3412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2958 .loc 1 3412 5 is_stmt 1 view .LVU996 +3412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2959 .loc 1 3412 24 is_stmt 0 view .LVU997 + 2960 000c 0023 movs r3, #0 + 2961 000e A1F85230 strh r3, [r1, #82] @ movhi + 2962 .LVL260: + 2963 .L113: +3416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2964 .loc 1 3416 5 is_stmt 1 discriminator 1 view .LVU998 + 2965 .LBB570: +3416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2966 .loc 1 3416 5 discriminator 1 view .LVU999 +3416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2967 .loc 1 3416 5 discriminator 1 view .LVU1000 +3416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2968 .loc 1 3416 5 discriminator 1 view .LVU1001 + 2969 0012 0A68 ldr r2, [r1] + 2970 .LVL261: + 2971 .LBB571: + 2972 .LBI571: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2973 .loc 2 1068 31 view .LVU1002 + 2974 .LBB572: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccQxTlMj.s page 155 + + + 2975 .loc 2 1070 5 view .LVU1003 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2976 .loc 2 1072 4 view .LVU1004 + 2977 0014 02F10803 add r3, r2, #8 + 2978 .LVL262: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 2979 .loc 2 1072 4 is_stmt 0 view .LVU1005 + 2980 .syntax unified + 2981 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2982 0018 53E8003F ldrex r3, [r3] + 2983 @ 0 "" 2 + 2984 .LVL263: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2985 .loc 2 1073 4 is_stmt 1 view .LVU1006 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 2986 .loc 2 1073 4 is_stmt 0 view .LVU1007 + 2987 .thumb + 2988 .syntax unified + 2989 .LBE572: + 2990 .LBE571: +3416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2991 .loc 1 3416 5 discriminator 1 view .LVU1008 + 2992 001c 23F08003 bic r3, r3, #128 + 2993 .LVL264: +3416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 2994 .loc 1 3416 5 is_stmt 1 discriminator 1 view .LVU1009 + 2995 .LBB573: + 2996 .LBI573: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2997 .loc 2 1119 31 view .LVU1010 + 2998 .LBB574: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2999 .loc 2 1121 4 view .LVU1011 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3000 .loc 2 1123 4 view .LVU1012 + 3001 0020 0832 adds r2, r2, #8 + 3002 .LVL265: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3003 .loc 2 1123 4 is_stmt 0 view .LVU1013 + 3004 .syntax unified + 3005 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3006 0022 42E80030 strex r0, r3, [r2] + 3007 @ 0 "" 2 + 3008 .LVL266: + 3009 .loc 2 1124 4 is_stmt 1 view .LVU1014 + 3010 .loc 2 1124 4 is_stmt 0 view .LVU1015 + 3011 .thumb + 3012 .syntax unified + 3013 .LBE574: + 3014 .LBE573: +3416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3015 .loc 1 3416 5 discriminator 1 view .LVU1016 + 3016 0026 0028 cmp r0, #0 + 3017 0028 F3D1 bne .L113 + 3018 .LVL267: + 3019 .L114: +3416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 156 + + + 3020 .loc 1 3416 5 discriminator 1 view .LVU1017 + 3021 .LBE570: +3416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3022 .loc 1 3416 5 is_stmt 1 discriminator 2 view .LVU1018 +3419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3023 .loc 1 3419 5 discriminator 1 view .LVU1019 + 3024 .LBB575: +3419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3025 .loc 1 3419 5 discriminator 1 view .LVU1020 +3419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3026 .loc 1 3419 5 discriminator 1 view .LVU1021 +3419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3027 .loc 1 3419 5 discriminator 1 view .LVU1022 + 3028 002a 0A68 ldr r2, [r1] + 3029 .LVL268: + 3030 .LBB576: + 3031 .LBI576: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 3032 .loc 2 1068 31 view .LVU1023 + 3033 .LBB577: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 3034 .loc 2 1070 5 view .LVU1024 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3035 .loc 2 1072 4 view .LVU1025 + 3036 .syntax unified + 3037 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3038 002c 52E8003F ldrex r3, [r2] + 3039 @ 0 "" 2 + 3040 .LVL269: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 3041 .loc 2 1073 4 view .LVU1026 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 3042 .loc 2 1073 4 is_stmt 0 view .LVU1027 + 3043 .thumb + 3044 .syntax unified + 3045 .LBE577: + 3046 .LBE576: +3419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3047 .loc 1 3419 5 discriminator 1 view .LVU1028 + 3048 0030 43F04003 orr r3, r3, #64 + 3049 .LVL270: +3419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3050 .loc 1 3419 5 is_stmt 1 discriminator 1 view .LVU1029 + 3051 .LBB578: + 3052 .LBI578: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 3053 .loc 2 1119 31 view .LVU1030 + 3054 .LBB579: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 3055 .loc 2 1121 4 view .LVU1031 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3056 .loc 2 1123 4 view .LVU1032 + 3057 .syntax unified + 3058 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3059 0034 42E80030 strex r0, r3, [r2] + 3060 @ 0 "" 2 + 3061 .LVL271: + ARM GAS /tmp/ccQxTlMj.s page 157 + + + 3062 .loc 2 1124 4 view .LVU1033 + 3063 .loc 2 1124 4 is_stmt 0 view .LVU1034 + 3064 .thumb + 3065 .syntax unified + 3066 .LBE579: + 3067 .LBE578: +3419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3068 .loc 1 3419 5 discriminator 1 view .LVU1035 + 3069 0038 0028 cmp r0, #0 + 3070 003a F6D1 bne .L114 + 3071 .LVL272: + 3072 .L111: +3419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3073 .loc 1 3419 5 discriminator 1 view .LVU1036 + 3074 .LBE575: +3432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3075 .loc 1 3432 1 view .LVU1037 + 3076 003c 08BD pop {r3, pc} + 3077 .LVL273: + 3078 .L112: +3429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3079 .loc 1 3429 5 is_stmt 1 view .LVU1038 + 3080 003e 0846 mov r0, r1 + 3081 .LVL274: +3429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3082 .loc 1 3429 5 is_stmt 0 view .LVU1039 + 3083 0040 FFF7FEFF bl HAL_UART_TxCpltCallback + 3084 .LVL275: +3432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3085 .loc 1 3432 1 view .LVU1040 + 3086 0044 FAE7 b .L111 + 3087 .cfi_endproc + 3088 .LFE193: + 3090 .section .text.UART_EndTransmit_IT,"ax",%progbits + 3091 .align 1 + 3092 .syntax unified + 3093 .thumb + 3094 .thumb_func + 3096 UART_EndTransmit_IT: + 3097 .LFB205: +3835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief Wrap up transmission in non-blocking mode. +3839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart pointer to a UART_HandleTypeDef structure that contains +3840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * the configuration information for the specified UART module. +3841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +3842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +3844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3098 .loc 1 3844 1 is_stmt 1 view -0 + 3099 .cfi_startproc + 3100 @ args = 0, pretend = 0, frame = 0 + 3101 @ frame_needed = 0, uses_anonymous_args = 0 + 3102 .LVL276: + 3103 .loc 1 3844 1 is_stmt 0 view .LVU1042 + 3104 0000 08B5 push {r3, lr} + ARM GAS /tmp/ccQxTlMj.s page 158 + + + 3105 .LCFI13: + 3106 .cfi_def_cfa_offset 8 + 3107 .cfi_offset 3, -8 + 3108 .cfi_offset 14, -4 + 3109 .L118: +3845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the UART Transmit Complete Interrupt */ +3846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + 3110 .loc 1 3846 3 is_stmt 1 discriminator 1 view .LVU1043 + 3111 .LBB580: + 3112 .loc 1 3846 3 discriminator 1 view .LVU1044 + 3113 .loc 1 3846 3 discriminator 1 view .LVU1045 + 3114 .loc 1 3846 3 discriminator 1 view .LVU1046 + 3115 0002 0268 ldr r2, [r0] + 3116 .LVL277: + 3117 .LBB581: + 3118 .LBI581: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 3119 .loc 2 1068 31 view .LVU1047 + 3120 .LBB582: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 3121 .loc 2 1070 5 view .LVU1048 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3122 .loc 2 1072 4 view .LVU1049 + 3123 .syntax unified + 3124 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3125 0004 52E8003F ldrex r3, [r2] + 3126 @ 0 "" 2 + 3127 .LVL278: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 3128 .loc 2 1073 4 view .LVU1050 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 3129 .loc 2 1073 4 is_stmt 0 view .LVU1051 + 3130 .thumb + 3131 .syntax unified + 3132 .LBE582: + 3133 .LBE581: + 3134 .loc 1 3846 3 discriminator 1 view .LVU1052 + 3135 0008 23F04003 bic r3, r3, #64 + 3136 .LVL279: + 3137 .loc 1 3846 3 is_stmt 1 discriminator 1 view .LVU1053 + 3138 .LBB583: + 3139 .LBI583: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 3140 .loc 2 1119 31 view .LVU1054 + 3141 .LBB584: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 3142 .loc 2 1121 4 view .LVU1055 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3143 .loc 2 1123 4 view .LVU1056 + 3144 .syntax unified + 3145 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3146 000c 42E80031 strex r1, r3, [r2] + 3147 @ 0 "" 2 + 3148 .LVL280: + 3149 .loc 2 1124 4 view .LVU1057 + 3150 .loc 2 1124 4 is_stmt 0 view .LVU1058 + 3151 .thumb + ARM GAS /tmp/ccQxTlMj.s page 159 + + + 3152 .syntax unified + 3153 .LBE584: + 3154 .LBE583: + 3155 .loc 1 3846 3 discriminator 1 view .LVU1059 + 3156 0010 0029 cmp r1, #0 + 3157 0012 F6D1 bne .L118 + 3158 .LBE580: + 3159 .loc 1 3846 3 is_stmt 1 discriminator 2 view .LVU1060 +3847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Tx process is ended, restore huart->gState to Ready */ +3849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_READY; + 3160 .loc 1 3849 3 view .LVU1061 + 3161 .loc 1 3849 17 is_stmt 0 view .LVU1062 + 3162 0014 2023 movs r3, #32 + 3163 .LVL281: + 3164 .loc 1 3849 17 view .LVU1063 + 3165 0016 C367 str r3, [r0, #124] +3850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Cleat TxISR function pointer */ +3852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxISR = NULL; + 3166 .loc 1 3852 3 is_stmt 1 view .LVU1064 + 3167 .loc 1 3852 16 is_stmt 0 view .LVU1065 + 3168 0018 0023 movs r3, #0 + 3169 001a C366 str r3, [r0, #108] +3853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call registered Tx complete callback*/ +3856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxCpltCallback(huart); +3857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +3858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call legacy weak Tx complete callback*/ +3859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_TxCpltCallback(huart); + 3170 .loc 1 3859 3 is_stmt 1 view .LVU1066 + 3171 001c FFF7FEFF bl HAL_UART_TxCpltCallback + 3172 .LVL282: +3860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3173 .loc 1 3861 1 is_stmt 0 view .LVU1067 + 3174 0020 08BD pop {r3, pc} + 3175 .cfi_endproc + 3176 .LFE205: + 3178 .section .text.HAL_UART_TxHalfCpltCallback,"ax",%progbits + 3179 .align 1 + 3180 .weak HAL_UART_TxHalfCpltCallback + 3181 .syntax unified + 3182 .thumb + 3183 .thumb_func + 3185 HAL_UART_TxHalfCpltCallback: + 3186 .LVL283: + 3187 .LFB165: +2450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 3188 .loc 1 2450 1 is_stmt 1 view -0 + 3189 .cfi_startproc + 3190 @ args = 0, pretend = 0, frame = 0 + 3191 @ frame_needed = 0, uses_anonymous_args = 0 + 3192 @ link register save eliminated. +2452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3193 .loc 1 2452 3 view .LVU1069 + ARM GAS /tmp/ccQxTlMj.s page 160 + + +2457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3194 .loc 1 2457 1 is_stmt 0 view .LVU1070 + 3195 0000 7047 bx lr + 3196 .cfi_endproc + 3197 .LFE165: + 3199 .section .text.UART_DMATxHalfCplt,"ax",%progbits + 3200 .align 1 + 3201 .syntax unified + 3202 .thumb + 3203 .thumb_func + 3205 UART_DMATxHalfCplt: + 3206 .LVL284: + 3207 .LFB194: +3440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 3208 .loc 1 3440 1 is_stmt 1 view -0 + 3209 .cfi_startproc + 3210 @ args = 0, pretend = 0, frame = 0 + 3211 @ frame_needed = 0, uses_anonymous_args = 0 +3440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 3212 .loc 1 3440 1 is_stmt 0 view .LVU1072 + 3213 0000 08B5 push {r3, lr} + 3214 .LCFI14: + 3215 .cfi_def_cfa_offset 8 + 3216 .cfi_offset 3, -8 + 3217 .cfi_offset 14, -4 +3441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3218 .loc 1 3441 3 is_stmt 1 view .LVU1073 + 3219 .LVL285: +3448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3220 .loc 1 3448 3 view .LVU1074 + 3221 0002 806B ldr r0, [r0, #56] + 3222 .LVL286: +3448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3223 .loc 1 3448 3 is_stmt 0 view .LVU1075 + 3224 0004 FFF7FEFF bl HAL_UART_TxHalfCpltCallback + 3225 .LVL287: +3450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3226 .loc 1 3450 1 view .LVU1076 + 3227 0008 08BD pop {r3, pc} + 3228 .cfi_endproc + 3229 .LFE194: + 3231 .section .text.HAL_UART_RxCpltCallback,"ax",%progbits + 3232 .align 1 + 3233 .weak HAL_UART_RxCpltCallback + 3234 .syntax unified + 3235 .thumb + 3236 .thumb_func + 3238 HAL_UART_RxCpltCallback: + 3239 .LVL288: + 3240 .LFB166: +2465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 3241 .loc 1 2465 1 is_stmt 1 view -0 + 3242 .cfi_startproc + 3243 @ args = 0, pretend = 0, frame = 0 + 3244 @ frame_needed = 0, uses_anonymous_args = 0 + 3245 @ link register save eliminated. +2467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 161 + + + 3246 .loc 1 2467 3 view .LVU1078 +2472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3247 .loc 1 2472 1 is_stmt 0 view .LVU1079 + 3248 0000 7047 bx lr + 3249 .cfi_endproc + 3250 .LFE166: + 3252 .section .text.HAL_UART_RxHalfCpltCallback,"ax",%progbits + 3253 .align 1 + 3254 .weak HAL_UART_RxHalfCpltCallback + 3255 .syntax unified + 3256 .thumb + 3257 .thumb_func + 3259 HAL_UART_RxHalfCpltCallback: + 3260 .LVL289: + 3261 .LFB167: +2480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 3262 .loc 1 2480 1 is_stmt 1 view -0 + 3263 .cfi_startproc + 3264 @ args = 0, pretend = 0, frame = 0 + 3265 @ frame_needed = 0, uses_anonymous_args = 0 + 3266 @ link register save eliminated. +2482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3267 .loc 1 2482 3 view .LVU1081 +2487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3268 .loc 1 2487 1 is_stmt 0 view .LVU1082 + 3269 0000 7047 bx lr + 3270 .cfi_endproc + 3271 .LFE167: + 3273 .section .text.HAL_UART_ErrorCallback,"ax",%progbits + 3274 .align 1 + 3275 .weak HAL_UART_ErrorCallback + 3276 .syntax unified + 3277 .thumb + 3278 .thumb_func + 3280 HAL_UART_ErrorCallback: + 3281 .LVL290: + 3282 .LFB168: +2495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 3283 .loc 1 2495 1 is_stmt 1 view -0 + 3284 .cfi_startproc + 3285 @ args = 0, pretend = 0, frame = 0 + 3286 @ frame_needed = 0, uses_anonymous_args = 0 + 3287 @ link register save eliminated. +2497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3288 .loc 1 2497 3 view .LVU1084 +2502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3289 .loc 1 2502 1 is_stmt 0 view .LVU1085 + 3290 0000 7047 bx lr + 3291 .cfi_endproc + 3292 .LFE168: + 3294 .section .text.UART_DMAError,"ax",%progbits + 3295 .align 1 + 3296 .syntax unified + 3297 .thumb + 3298 .thumb_func + 3300 UART_DMAError: + 3301 .LVL291: + ARM GAS /tmp/ccQxTlMj.s page 162 + + + 3302 .LFB197: +3557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 3303 .loc 1 3557 1 is_stmt 1 view -0 + 3304 .cfi_startproc + 3305 @ args = 0, pretend = 0, frame = 0 + 3306 @ frame_needed = 0, uses_anonymous_args = 0 +3557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 3307 .loc 1 3557 1 is_stmt 0 view .LVU1087 + 3308 0000 38B5 push {r3, r4, r5, lr} + 3309 .LCFI15: + 3310 .cfi_def_cfa_offset 16 + 3311 .cfi_offset 3, -16 + 3312 .cfi_offset 4, -12 + 3313 .cfi_offset 5, -8 + 3314 .cfi_offset 14, -4 +3558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3315 .loc 1 3558 3 is_stmt 1 view .LVU1088 +3558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3316 .loc 1 3558 23 is_stmt 0 view .LVU1089 + 3317 0002 846B ldr r4, [r0, #56] + 3318 .LVL292: +3560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const HAL_UART_StateTypeDef rxstate = huart->RxState; + 3319 .loc 1 3560 3 is_stmt 1 view .LVU1090 +3560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const HAL_UART_StateTypeDef rxstate = huart->RxState; + 3320 .loc 1 3560 31 is_stmt 0 view .LVU1091 + 3321 0004 E26F ldr r2, [r4, #124] + 3322 .LVL293: +3561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3323 .loc 1 3561 3 is_stmt 1 view .LVU1092 +3561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3324 .loc 1 3561 31 is_stmt 0 view .LVU1093 + 3325 0006 D4F88050 ldr r5, [r4, #128] + 3326 .LVL294: +3564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 3327 .loc 1 3564 3 is_stmt 1 view .LVU1094 +3564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 3328 .loc 1 3564 8 is_stmt 0 view .LVU1095 + 3329 000a 2368 ldr r3, [r4] + 3330 000c 9B68 ldr r3, [r3, #8] +3564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 3331 .loc 1 3564 6 view .LVU1096 + 3332 000e 13F0800F tst r3, #128 + 3333 0012 01D0 beq .L127 +3564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (gstate == HAL_UART_STATE_BUSY_TX)) + 3334 .loc 1 3564 62 discriminator 1 view .LVU1097 + 3335 0014 212A cmp r2, #33 + 3336 0016 10D0 beq .L130 + 3337 .LVL295: + 3338 .L127: +3572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 3339 .loc 1 3572 3 is_stmt 1 view .LVU1098 +3572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 3340 .loc 1 3572 8 is_stmt 0 view .LVU1099 + 3341 0018 2368 ldr r3, [r4] + 3342 001a 9B68 ldr r3, [r3, #8] +3572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 3343 .loc 1 3572 6 view .LVU1100 + ARM GAS /tmp/ccQxTlMj.s page 163 + + + 3344 001c 13F0400F tst r3, #64 + 3345 0020 01D0 beq .L128 +3572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** (rxstate == HAL_UART_STATE_BUSY_RX)) + 3346 .loc 1 3572 62 discriminator 1 view .LVU1101 + 3347 0022 222D cmp r5, #34 + 3348 0024 10D0 beq .L131 + 3349 .L128: +3579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3350 .loc 1 3579 3 is_stmt 1 view .LVU1102 +3579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3351 .loc 1 3579 8 is_stmt 0 view .LVU1103 + 3352 0026 D4F88430 ldr r3, [r4, #132] +3579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3353 .loc 1 3579 20 view .LVU1104 + 3354 002a 43F01003 orr r3, r3, #16 + 3355 002e C4F88430 str r3, [r4, #132] +3586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3356 .loc 1 3586 3 is_stmt 1 view .LVU1105 + 3357 0032 2046 mov r0, r4 + 3358 0034 FFF7FEFF bl HAL_UART_ErrorCallback + 3359 .LVL296: +3588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3360 .loc 1 3588 1 is_stmt 0 view .LVU1106 + 3361 0038 38BD pop {r3, r4, r5, pc} + 3362 .LVL297: + 3363 .L130: +3567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_EndTxTransfer(huart); + 3364 .loc 1 3567 5 is_stmt 1 view .LVU1107 +3567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_EndTxTransfer(huart); + 3365 .loc 1 3567 24 is_stmt 0 view .LVU1108 + 3366 003a 0023 movs r3, #0 + 3367 003c A4F85230 strh r3, [r4, #82] @ movhi +3568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3368 .loc 1 3568 5 is_stmt 1 view .LVU1109 + 3369 0040 2046 mov r0, r4 + 3370 .LVL298: +3568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3371 .loc 1 3568 5 is_stmt 0 view .LVU1110 + 3372 0042 FFF7FEFF bl UART_EndTxTransfer + 3373 .LVL299: +3568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3374 .loc 1 3568 5 view .LVU1111 + 3375 0046 E7E7 b .L127 + 3376 .L131: +3575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_EndRxTransfer(huart); + 3377 .loc 1 3575 5 is_stmt 1 view .LVU1112 +3575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_EndRxTransfer(huart); + 3378 .loc 1 3575 24 is_stmt 0 view .LVU1113 + 3379 0048 0023 movs r3, #0 + 3380 004a A4F85A30 strh r3, [r4, #90] @ movhi +3576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3381 .loc 1 3576 5 is_stmt 1 view .LVU1114 + 3382 004e 2046 mov r0, r4 + 3383 0050 FFF7FEFF bl UART_EndRxTransfer + 3384 .LVL300: + 3385 0054 E7E7 b .L128 + 3386 .cfi_endproc + ARM GAS /tmp/ccQxTlMj.s page 164 + + + 3387 .LFE197: + 3389 .section .text.UART_DMAAbortOnError,"ax",%progbits + 3390 .align 1 + 3391 .syntax unified + 3392 .thumb + 3393 .thumb_func + 3395 UART_DMAAbortOnError: + 3396 .LVL301: + 3397 .LFB198: +3597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 3398 .loc 1 3597 1 view -0 + 3399 .cfi_startproc + 3400 @ args = 0, pretend = 0, frame = 0 + 3401 @ frame_needed = 0, uses_anonymous_args = 0 +3597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 3402 .loc 1 3597 1 is_stmt 0 view .LVU1116 + 3403 0000 08B5 push {r3, lr} + 3404 .LCFI16: + 3405 .cfi_def_cfa_offset 8 + 3406 .cfi_offset 3, -8 + 3407 .cfi_offset 14, -4 +3598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; + 3408 .loc 1 3598 3 is_stmt 1 view .LVU1117 +3598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; + 3409 .loc 1 3598 23 is_stmt 0 view .LVU1118 + 3410 0002 806B ldr r0, [r0, #56] + 3411 .LVL302: +3599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = 0U; + 3412 .loc 1 3599 3 is_stmt 1 view .LVU1119 +3599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = 0U; + 3413 .loc 1 3599 22 is_stmt 0 view .LVU1120 + 3414 0004 0023 movs r3, #0 + 3415 0006 A0F85A30 strh r3, [r0, #90] @ movhi +3600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3416 .loc 1 3600 3 is_stmt 1 view .LVU1121 +3600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3417 .loc 1 3600 22 is_stmt 0 view .LVU1122 + 3418 000a A0F85230 strh r3, [r0, #82] @ movhi +3607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3419 .loc 1 3607 3 is_stmt 1 view .LVU1123 + 3420 000e FFF7FEFF bl HAL_UART_ErrorCallback + 3421 .LVL303: +3609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3422 .loc 1 3609 1 is_stmt 0 view .LVU1124 + 3423 0012 08BD pop {r3, pc} + 3424 .cfi_endproc + 3425 .LFE198: + 3427 .section .text.HAL_UART_AbortCpltCallback,"ax",%progbits + 3428 .align 1 + 3429 .weak HAL_UART_AbortCpltCallback + 3430 .syntax unified + 3431 .thumb + 3432 .thumb_func + 3434 HAL_UART_AbortCpltCallback: + 3435 .LVL304: + 3436 .LFB169: +2510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + ARM GAS /tmp/ccQxTlMj.s page 165 + + + 3437 .loc 1 2510 1 is_stmt 1 view -0 + 3438 .cfi_startproc + 3439 @ args = 0, pretend = 0, frame = 0 + 3440 @ frame_needed = 0, uses_anonymous_args = 0 + 3441 @ link register save eliminated. +2512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3442 .loc 1 2512 3 view .LVU1126 +2517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3443 .loc 1 2517 1 is_stmt 0 view .LVU1127 + 3444 0000 7047 bx lr + 3445 .cfi_endproc + 3446 .LFE169: + 3448 .section .text.HAL_UART_Abort_IT,"ax",%progbits + 3449 .align 1 + 3450 .global HAL_UART_Abort_IT + 3451 .syntax unified + 3452 .thumb + 3453 .thumb_func + 3455 HAL_UART_Abort_IT: + 3456 .LVL305: + 3457 .LFB160: +1804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t abortcplt = 1U; + 3458 .loc 1 1804 1 is_stmt 1 view -0 + 3459 .cfi_startproc + 3460 @ args = 0, pretend = 0, frame = 0 + 3461 @ frame_needed = 0, uses_anonymous_args = 0 +1804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t abortcplt = 1U; + 3462 .loc 1 1804 1 is_stmt 0 view .LVU1129 + 3463 0000 38B5 push {r3, r4, r5, lr} + 3464 .LCFI17: + 3465 .cfi_def_cfa_offset 16 + 3466 .cfi_offset 3, -16 + 3467 .cfi_offset 4, -12 + 3468 .cfi_offset 5, -8 + 3469 .cfi_offset 14, -4 + 3470 0002 0446 mov r4, r0 +1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3471 .loc 1 1805 3 is_stmt 1 view .LVU1130 + 3472 .LVL306: + 3473 .L136: +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 3474 .loc 1 1808 3 discriminator 1 view .LVU1131 + 3475 .LBB585: +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 3476 .loc 1 1808 3 discriminator 1 view .LVU1132 +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 3477 .loc 1 1808 3 discriminator 1 view .LVU1133 +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 3478 .loc 1 1808 3 discriminator 1 view .LVU1134 + 3479 0004 2268 ldr r2, [r4] + 3480 .LVL307: + 3481 .LBB586: + 3482 .LBI586: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 3483 .loc 2 1068 31 view .LVU1135 + 3484 .LBB587: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccQxTlMj.s page 166 + + + 3485 .loc 2 1070 5 view .LVU1136 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3486 .loc 2 1072 4 view .LVU1137 + 3487 .syntax unified + 3488 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3489 0006 52E8003F ldrex r3, [r2] + 3490 @ 0 "" 2 + 3491 .LVL308: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 3492 .loc 2 1073 4 view .LVU1138 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 3493 .loc 2 1073 4 is_stmt 0 view .LVU1139 + 3494 .thumb + 3495 .syntax unified + 3496 .LBE587: + 3497 .LBE586: +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 3498 .loc 1 1808 3 discriminator 1 view .LVU1140 + 3499 000a 23F4F073 bic r3, r3, #480 + 3500 .LVL309: +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 3501 .loc 1 1808 3 is_stmt 1 discriminator 1 view .LVU1141 + 3502 .LBB588: + 3503 .LBI588: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 3504 .loc 2 1119 31 view .LVU1142 + 3505 .LBB589: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 3506 .loc 2 1121 4 view .LVU1143 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3507 .loc 2 1123 4 view .LVU1144 + 3508 .syntax unified + 3509 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3510 000e 42E80031 strex r1, r3, [r2] + 3511 @ 0 "" 2 + 3512 .LVL310: + 3513 .loc 2 1124 4 view .LVU1145 + 3514 .loc 2 1124 4 is_stmt 0 view .LVU1146 + 3515 .thumb + 3516 .syntax unified + 3517 .LBE589: + 3518 .LBE588: +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 3519 .loc 1 1808 3 discriminator 1 view .LVU1147 + 3520 0012 0029 cmp r1, #0 + 3521 0014 F6D1 bne .L136 + 3522 .LVL311: + 3523 .L137: +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 3524 .loc 1 1808 3 discriminator 1 view .LVU1148 + 3525 .LBE585: +1808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 3526 .loc 1 1808 3 is_stmt 1 discriminator 2 view .LVU1149 +1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3527 .loc 1 1809 3 discriminator 1 view .LVU1150 + 3528 .LBB590: +1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 167 + + + 3529 .loc 1 1809 3 discriminator 1 view .LVU1151 +1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3530 .loc 1 1809 3 discriminator 1 view .LVU1152 +1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3531 .loc 1 1809 3 discriminator 1 view .LVU1153 + 3532 0016 2268 ldr r2, [r4] + 3533 .LVL312: + 3534 .LBB591: + 3535 .LBI591: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 3536 .loc 2 1068 31 view .LVU1154 + 3537 .LBB592: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 3538 .loc 2 1070 5 view .LVU1155 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3539 .loc 2 1072 4 view .LVU1156 + 3540 0018 02F10803 add r3, r2, #8 + 3541 .LVL313: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3542 .loc 2 1072 4 is_stmt 0 view .LVU1157 + 3543 .syntax unified + 3544 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3545 001c 53E8003F ldrex r3, [r3] + 3546 @ 0 "" 2 + 3547 .LVL314: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 3548 .loc 2 1073 4 is_stmt 1 view .LVU1158 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 3549 .loc 2 1073 4 is_stmt 0 view .LVU1159 + 3550 .thumb + 3551 .syntax unified + 3552 .LBE592: + 3553 .LBE591: +1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3554 .loc 1 1809 3 discriminator 1 view .LVU1160 + 3555 0020 23F00103 bic r3, r3, #1 + 3556 .LVL315: +1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3557 .loc 1 1809 3 is_stmt 1 discriminator 1 view .LVU1161 + 3558 .LBB593: + 3559 .LBI593: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 3560 .loc 2 1119 31 view .LVU1162 + 3561 .LBB594: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 3562 .loc 2 1121 4 view .LVU1163 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3563 .loc 2 1123 4 view .LVU1164 + 3564 0024 0832 adds r2, r2, #8 + 3565 .LVL316: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3566 .loc 2 1123 4 is_stmt 0 view .LVU1165 + 3567 .syntax unified + 3568 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3569 0026 42E80031 strex r1, r3, [r2] + 3570 @ 0 "" 2 + 3571 .LVL317: + ARM GAS /tmp/ccQxTlMj.s page 168 + + + 3572 .loc 2 1124 4 is_stmt 1 view .LVU1166 + 3573 .loc 2 1124 4 is_stmt 0 view .LVU1167 + 3574 .thumb + 3575 .syntax unified + 3576 .LBE594: + 3577 .LBE593: +1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3578 .loc 1 1809 3 discriminator 1 view .LVU1168 + 3579 002a 0029 cmp r1, #0 + 3580 002c F3D1 bne .L137 + 3581 .LBE590: +1809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3582 .loc 1 1809 3 is_stmt 1 discriminator 2 view .LVU1169 +1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3583 .loc 1 1812 3 view .LVU1170 +1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3584 .loc 1 1812 12 is_stmt 0 view .LVU1171 + 3585 002e 236E ldr r3, [r4, #96] + 3586 .LVL318: +1812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3587 .loc 1 1812 6 view .LVU1172 + 3588 0030 012B cmp r3, #1 + 3589 0032 2ED0 beq .L139 + 3590 .L138: +1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3591 .loc 1 1814 5 is_stmt 1 discriminator 2 view .LVU1173 +1820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3592 .loc 1 1820 3 view .LVU1174 +1820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3593 .loc 1 1820 12 is_stmt 0 view .LVU1175 + 3594 0034 236F ldr r3, [r4, #112] +1820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3595 .loc 1 1820 6 view .LVU1176 + 3596 0036 33B1 cbz r3, .L140 +1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3597 .loc 1 1824 5 is_stmt 1 view .LVU1177 +1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3598 .loc 1 1824 9 is_stmt 0 view .LVU1178 + 3599 0038 2268 ldr r2, [r4] + 3600 003a 9268 ldr r2, [r2, #8] +1824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3601 .loc 1 1824 8 view .LVU1179 + 3602 003c 12F0800F tst r2, #128 + 3603 0040 31D0 beq .L141 +1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3604 .loc 1 1826 7 is_stmt 1 view .LVU1180 +1826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3605 .loc 1 1826 40 is_stmt 0 view .LVU1181 + 3606 0042 394A ldr r2, .L153 + 3607 0044 1A65 str r2, [r3, #80] + 3608 .L140: +1834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3609 .loc 1 1834 3 is_stmt 1 view .LVU1182 +1834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3610 .loc 1 1834 12 is_stmt 0 view .LVU1183 + 3611 0046 636F ldr r3, [r4, #116] +1834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + ARM GAS /tmp/ccQxTlMj.s page 169 + + + 3612 .loc 1 1834 6 view .LVU1184 + 3613 0048 33B1 cbz r3, .L142 +1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3614 .loc 1 1838 5 is_stmt 1 view .LVU1185 +1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3615 .loc 1 1838 9 is_stmt 0 view .LVU1186 + 3616 004a 2268 ldr r2, [r4] + 3617 004c 9268 ldr r2, [r2, #8] +1838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3618 .loc 1 1838 8 view .LVU1187 + 3619 004e 12F0400F tst r2, #64 + 3620 0052 2BD0 beq .L143 +1840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3621 .loc 1 1840 7 is_stmt 1 view .LVU1188 +1840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3622 .loc 1 1840 40 is_stmt 0 view .LVU1189 + 3623 0054 354A ldr r2, .L153+4 + 3624 0056 1A65 str r2, [r3, #80] + 3625 .L142: +1849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3626 .loc 1 1849 3 is_stmt 1 view .LVU1190 +1849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3627 .loc 1 1849 7 is_stmt 0 view .LVU1191 + 3628 0058 2368 ldr r3, [r4] + 3629 005a 9B68 ldr r3, [r3, #8] +1849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3630 .loc 1 1849 6 view .LVU1192 + 3631 005c 13F0800F tst r3, #128 + 3632 0060 27D0 beq .L150 + 3633 .L145: +1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3634 .loc 1 1852 5 is_stmt 1 discriminator 1 view .LVU1193 + 3635 .LBB595: +1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3636 .loc 1 1852 5 discriminator 1 view .LVU1194 +1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3637 .loc 1 1852 5 discriminator 1 view .LVU1195 +1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3638 .loc 1 1852 5 discriminator 1 view .LVU1196 + 3639 0062 2168 ldr r1, [r4] + 3640 .LVL319: + 3641 .LBB596: + 3642 .LBI596: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 3643 .loc 2 1068 31 view .LVU1197 + 3644 .LBB597: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 3645 .loc 2 1070 5 view .LVU1198 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3646 .loc 2 1072 4 view .LVU1199 + 3647 0064 01F10803 add r3, r1, #8 + 3648 .LVL320: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3649 .loc 2 1072 4 is_stmt 0 view .LVU1200 + 3650 .syntax unified + 3651 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3652 0068 53E8003F ldrex r3, [r3] + ARM GAS /tmp/ccQxTlMj.s page 170 + + + 3653 @ 0 "" 2 + 3654 .LVL321: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 3655 .loc 2 1073 4 is_stmt 1 view .LVU1201 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 3656 .loc 2 1073 4 is_stmt 0 view .LVU1202 + 3657 .thumb + 3658 .syntax unified + 3659 .LBE597: + 3660 .LBE596: +1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3661 .loc 1 1852 5 discriminator 1 view .LVU1203 + 3662 006c 23F08003 bic r3, r3, #128 + 3663 .LVL322: +1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3664 .loc 1 1852 5 is_stmt 1 discriminator 1 view .LVU1204 + 3665 .LBB598: + 3666 .LBI598: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 3667 .loc 2 1119 31 view .LVU1205 + 3668 .LBB599: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 3669 .loc 2 1121 4 view .LVU1206 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3670 .loc 2 1123 4 view .LVU1207 + 3671 0070 0831 adds r1, r1, #8 + 3672 .LVL323: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3673 .loc 2 1123 4 is_stmt 0 view .LVU1208 + 3674 .syntax unified + 3675 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3676 0072 41E80032 strex r2, r3, [r1] + 3677 @ 0 "" 2 + 3678 .thumb + 3679 .syntax unified + 3680 0076 1546 mov r5, r2 + 3681 .LVL324: + 3682 .loc 2 1124 4 is_stmt 1 view .LVU1209 + 3683 .loc 2 1124 4 is_stmt 0 view .LVU1210 + 3684 .LBE599: + 3685 .LBE598: +1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3686 .loc 1 1852 5 discriminator 1 view .LVU1211 + 3687 0078 002A cmp r2, #0 + 3688 007a F2D1 bne .L145 + 3689 .LBE595: +1852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3690 .loc 1 1852 5 is_stmt 1 discriminator 2 view .LVU1212 +1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3691 .loc 1 1855 5 view .LVU1213 +1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3692 .loc 1 1855 14 is_stmt 0 view .LVU1214 + 3693 007c 206F ldr r0, [r4, #112] + 3694 .LVL325: +1855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3695 .loc 1 1855 8 view .LVU1215 + 3696 007e 0028 cmp r0, #0 + ARM GAS /tmp/ccQxTlMj.s page 171 + + + 3697 0080 4BD0 beq .L151 +1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3698 .loc 1 1861 7 is_stmt 1 view .LVU1216 +1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3699 .loc 1 1861 11 is_stmt 0 view .LVU1217 + 3700 0082 FFF7FEFF bl HAL_DMA_Abort_IT + 3701 .LVL326: +1861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3702 .loc 1 1861 10 discriminator 1 view .LVU1218 + 3703 0086 A8B1 cbz r0, .L144 +1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3704 .loc 1 1863 9 is_stmt 1 view .LVU1219 +1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3705 .loc 1 1863 14 is_stmt 0 view .LVU1220 + 3706 0088 236F ldr r3, [r4, #112] +1863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3707 .loc 1 1863 42 view .LVU1221 + 3708 008a 0022 movs r2, #0 + 3709 008c 1A65 str r2, [r3, #80] +1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3710 .loc 1 1805 12 view .LVU1222 + 3711 008e 0125 movs r5, #1 + 3712 0090 10E0 b .L144 + 3713 .LVL327: + 3714 .L139: +1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3715 .loc 1 1814 5 is_stmt 1 discriminator 1 view .LVU1223 + 3716 .LBB600: +1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3717 .loc 1 1814 5 discriminator 1 view .LVU1224 +1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3718 .loc 1 1814 5 discriminator 1 view .LVU1225 +1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3719 .loc 1 1814 5 discriminator 1 view .LVU1226 + 3720 0092 2268 ldr r2, [r4] + 3721 .LVL328: + 3722 .LBB601: + 3723 .LBI601: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 3724 .loc 2 1068 31 view .LVU1227 + 3725 .LBB602: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 3726 .loc 2 1070 5 view .LVU1228 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3727 .loc 2 1072 4 view .LVU1229 + 3728 .syntax unified + 3729 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3730 0094 52E8003F ldrex r3, [r2] + 3731 @ 0 "" 2 + 3732 .LVL329: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 3733 .loc 2 1073 4 view .LVU1230 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 3734 .loc 2 1073 4 is_stmt 0 view .LVU1231 + 3735 .thumb + 3736 .syntax unified + 3737 .LBE602: + ARM GAS /tmp/ccQxTlMj.s page 172 + + + 3738 .LBE601: +1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3739 .loc 1 1814 5 discriminator 1 view .LVU1232 + 3740 0098 23F01003 bic r3, r3, #16 + 3741 .LVL330: +1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3742 .loc 1 1814 5 is_stmt 1 discriminator 1 view .LVU1233 + 3743 .LBB603: + 3744 .LBI603: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 3745 .loc 2 1119 31 view .LVU1234 + 3746 .LBB604: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 3747 .loc 2 1121 4 view .LVU1235 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3748 .loc 2 1123 4 view .LVU1236 + 3749 .syntax unified + 3750 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3751 009c 42E80031 strex r1, r3, [r2] + 3752 @ 0 "" 2 + 3753 .LVL331: + 3754 .loc 2 1124 4 view .LVU1237 + 3755 .loc 2 1124 4 is_stmt 0 view .LVU1238 + 3756 .thumb + 3757 .syntax unified + 3758 .LBE604: + 3759 .LBE603: +1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3760 .loc 1 1814 5 discriminator 1 view .LVU1239 + 3761 00a0 0029 cmp r1, #0 + 3762 00a2 F6D1 bne .L139 + 3763 00a4 C6E7 b .L138 + 3764 .LVL332: + 3765 .L141: +1814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3766 .loc 1 1814 5 discriminator 1 view .LVU1240 + 3767 .LBE600: +1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3768 .loc 1 1830 7 is_stmt 1 view .LVU1241 +1830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3769 .loc 1 1830 40 is_stmt 0 view .LVU1242 + 3770 00a6 0022 movs r2, #0 + 3771 00a8 1A65 str r2, [r3, #80] + 3772 00aa CCE7 b .L140 + 3773 .L143: +1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3774 .loc 1 1844 7 is_stmt 1 view .LVU1243 +1844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3775 .loc 1 1844 40 is_stmt 0 view .LVU1244 + 3776 00ac 0022 movs r2, #0 + 3777 00ae 1A65 str r2, [r3, #80] + 3778 00b0 D2E7 b .L142 + 3779 .L150: +1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3780 .loc 1 1805 12 view .LVU1245 + 3781 00b2 0125 movs r5, #1 + 3782 .LVL333: + ARM GAS /tmp/ccQxTlMj.s page 173 + + + 3783 .L144: +1873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3784 .loc 1 1873 3 is_stmt 1 view .LVU1246 +1873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3785 .loc 1 1873 7 is_stmt 0 view .LVU1247 + 3786 00b4 2368 ldr r3, [r4] + 3787 00b6 9B68 ldr r3, [r3, #8] +1873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3788 .loc 1 1873 6 view .LVU1248 + 3789 00b8 13F0400F tst r3, #64 + 3790 00bc 2FD0 beq .L146 + 3791 .L147: +1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3792 .loc 1 1876 5 is_stmt 1 discriminator 1 view .LVU1249 + 3793 .LBB605: +1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3794 .loc 1 1876 5 discriminator 1 view .LVU1250 +1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3795 .loc 1 1876 5 discriminator 1 view .LVU1251 +1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3796 .loc 1 1876 5 discriminator 1 view .LVU1252 + 3797 00be 2268 ldr r2, [r4] + 3798 .LVL334: + 3799 .LBB606: + 3800 .LBI606: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 3801 .loc 2 1068 31 view .LVU1253 + 3802 .LBB607: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 3803 .loc 2 1070 5 view .LVU1254 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3804 .loc 2 1072 4 view .LVU1255 + 3805 00c0 02F10803 add r3, r2, #8 + 3806 .LVL335: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3807 .loc 2 1072 4 is_stmt 0 view .LVU1256 + 3808 .syntax unified + 3809 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3810 00c4 53E8003F ldrex r3, [r3] + 3811 @ 0 "" 2 + 3812 .LVL336: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 3813 .loc 2 1073 4 is_stmt 1 view .LVU1257 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 3814 .loc 2 1073 4 is_stmt 0 view .LVU1258 + 3815 .thumb + 3816 .syntax unified + 3817 .LBE607: + 3818 .LBE606: +1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3819 .loc 1 1876 5 discriminator 1 view .LVU1259 + 3820 00c8 23F04003 bic r3, r3, #64 + 3821 .LVL337: +1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3822 .loc 1 1876 5 is_stmt 1 discriminator 1 view .LVU1260 + 3823 .LBB608: + 3824 .LBI608: + ARM GAS /tmp/ccQxTlMj.s page 174 + + +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 3825 .loc 2 1119 31 view .LVU1261 + 3826 .LBB609: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 3827 .loc 2 1121 4 view .LVU1262 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3828 .loc 2 1123 4 view .LVU1263 + 3829 00cc 0832 adds r2, r2, #8 + 3830 .LVL338: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 3831 .loc 2 1123 4 is_stmt 0 view .LVU1264 + 3832 .syntax unified + 3833 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3834 00ce 42E80031 strex r1, r3, [r2] + 3835 @ 0 "" 2 + 3836 .LVL339: + 3837 .loc 2 1124 4 is_stmt 1 view .LVU1265 + 3838 .loc 2 1124 4 is_stmt 0 view .LVU1266 + 3839 .thumb + 3840 .syntax unified + 3841 .LBE609: + 3842 .LBE608: +1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3843 .loc 1 1876 5 discriminator 1 view .LVU1267 + 3844 00d2 0029 cmp r1, #0 + 3845 00d4 F3D1 bne .L147 + 3846 .LBE605: +1876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3847 .loc 1 1876 5 is_stmt 1 discriminator 2 view .LVU1268 +1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3848 .loc 1 1879 5 view .LVU1269 +1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3849 .loc 1 1879 14 is_stmt 0 view .LVU1270 + 3850 00d6 606F ldr r0, [r4, #116] +1879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3851 .loc 1 1879 8 view .LVU1271 + 3852 00d8 08B3 cbz r0, .L146 +1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3853 .loc 1 1885 7 is_stmt 1 view .LVU1272 +1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3854 .loc 1 1885 11 is_stmt 0 view .LVU1273 + 3855 00da FFF7FEFF bl HAL_DMA_Abort_IT + 3856 .LVL340: +1885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3857 .loc 1 1885 10 discriminator 1 view .LVU1274 + 3858 00de 00B3 cbz r0, .L148 +1887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** abortcplt = 1U; + 3859 .loc 1 1887 9 is_stmt 1 view .LVU1275 +1887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** abortcplt = 1U; + 3860 .loc 1 1887 14 is_stmt 0 view .LVU1276 + 3861 00e0 636F ldr r3, [r4, #116] +1887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** abortcplt = 1U; + 3862 .loc 1 1887 42 view .LVU1277 + 3863 00e2 0022 movs r2, #0 + 3864 00e4 1A65 str r2, [r3, #80] +1888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3865 .loc 1 1888 9 is_stmt 1 view .LVU1278 + ARM GAS /tmp/ccQxTlMj.s page 175 + + + 3866 .LVL341: +1898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3867 .loc 1 1898 3 view .LVU1279 + 3868 .L149: +1901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; + 3869 .loc 1 1901 5 view .LVU1280 +1901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; + 3870 .loc 1 1901 24 is_stmt 0 view .LVU1281 + 3871 00e6 0023 movs r3, #0 + 3872 00e8 A4F85230 strh r3, [r4, #82] @ movhi +1902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3873 .loc 1 1902 5 is_stmt 1 view .LVU1282 +1902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3874 .loc 1 1902 24 is_stmt 0 view .LVU1283 + 3875 00ec A4F85A30 strh r3, [r4, #90] @ movhi +1905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxISR = NULL; + 3876 .loc 1 1905 5 is_stmt 1 view .LVU1284 +1905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxISR = NULL; + 3877 .loc 1 1905 18 is_stmt 0 view .LVU1285 + 3878 00f0 A366 str r3, [r4, #104] +1906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3879 .loc 1 1906 5 is_stmt 1 view .LVU1286 +1906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3880 .loc 1 1906 18 is_stmt 0 view .LVU1287 + 3881 00f2 E366 str r3, [r4, #108] +1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3882 .loc 1 1909 5 is_stmt 1 view .LVU1288 +1909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3883 .loc 1 1909 22 is_stmt 0 view .LVU1289 + 3884 00f4 C4F88430 str r3, [r4, #132] +1912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3885 .loc 1 1912 5 is_stmt 1 view .LVU1290 + 3886 00f8 2268 ldr r2, [r4] + 3887 00fa 0F21 movs r1, #15 + 3888 00fc 1162 str r1, [r2, #32] +1916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3889 .loc 1 1916 5 view .LVU1291 + 3890 00fe 2168 ldr r1, [r4] + 3891 0100 8A69 ldr r2, [r1, #24] + 3892 0102 42F00802 orr r2, r2, #8 + 3893 0106 8A61 str r2, [r1, #24] +1919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 3894 .loc 1 1919 5 view .LVU1292 +1919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 3895 .loc 1 1919 20 is_stmt 0 view .LVU1293 + 3896 0108 2022 movs r2, #32 + 3897 010a E267 str r2, [r4, #124] +1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 3898 .loc 1 1920 5 is_stmt 1 view .LVU1294 +1920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 3899 .loc 1 1920 20 is_stmt 0 view .LVU1295 + 3900 010c C4F88020 str r2, [r4, #128] +1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3901 .loc 1 1921 5 is_stmt 1 view .LVU1296 +1921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3902 .loc 1 1921 26 is_stmt 0 view .LVU1297 + 3903 0110 2366 str r3, [r4, #96] + ARM GAS /tmp/ccQxTlMj.s page 176 + + +1929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 3904 .loc 1 1929 5 is_stmt 1 view .LVU1298 + 3905 0112 2046 mov r0, r4 + 3906 0114 FFF7FEFF bl HAL_UART_AbortCpltCallback + 3907 .LVL342: + 3908 0118 03E0 b .L148 + 3909 .LVL343: + 3910 .L151: +1805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3911 .loc 1 1805 12 is_stmt 0 view .LVU1299 + 3912 011a 0125 movs r5, #1 + 3913 011c CAE7 b .L144 + 3914 .LVL344: + 3915 .L146: +1898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3916 .loc 1 1898 3 is_stmt 1 view .LVU1300 +1898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3917 .loc 1 1898 6 is_stmt 0 view .LVU1301 + 3918 011e 012D cmp r5, #1 + 3919 0120 E1D0 beq .L149 + 3920 .LVL345: + 3921 .L148: +1933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 3922 .loc 1 1933 3 is_stmt 1 view .LVU1302 +1934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3923 .loc 1 1934 1 is_stmt 0 view .LVU1303 + 3924 0122 0020 movs r0, #0 + 3925 0124 38BD pop {r3, r4, r5, pc} + 3926 .LVL346: + 3927 .L154: +1934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3928 .loc 1 1934 1 view .LVU1304 + 3929 0126 00BF .align 2 + 3930 .L153: + 3931 0128 00000000 .word UART_DMATxAbortCallback + 3932 012c 00000000 .word UART_DMARxAbortCallback + 3933 .cfi_endproc + 3934 .LFE160: + 3936 .section .text.UART_DMARxAbortCallback,"ax",%progbits + 3937 .align 1 + 3938 .syntax unified + 3939 .thumb + 3940 .thumb_func + 3942 UART_DMARxAbortCallback: + 3943 .LVL347: + 3944 .LFB200: +3670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 3945 .loc 1 3670 1 is_stmt 1 view -0 + 3946 .cfi_startproc + 3947 @ args = 0, pretend = 0, frame = 0 + 3948 @ frame_needed = 0, uses_anonymous_args = 0 +3670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 3949 .loc 1 3670 1 is_stmt 0 view .LVU1306 + 3950 0000 08B5 push {r3, lr} + 3951 .LCFI18: + 3952 .cfi_def_cfa_offset 8 + 3953 .cfi_offset 3, -8 + ARM GAS /tmp/ccQxTlMj.s page 177 + + + 3954 .cfi_offset 14, -4 +3671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3955 .loc 1 3671 3 is_stmt 1 view .LVU1307 +3671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3956 .loc 1 3671 23 is_stmt 0 view .LVU1308 + 3957 0002 806B ldr r0, [r0, #56] + 3958 .LVL348: +3673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3959 .loc 1 3673 3 is_stmt 1 view .LVU1309 +3673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3960 .loc 1 3673 8 is_stmt 0 view .LVU1310 + 3961 0004 436F ldr r3, [r0, #116] +3673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3962 .loc 1 3673 36 view .LVU1311 + 3963 0006 0022 movs r2, #0 + 3964 0008 1A65 str r2, [r3, #80] +3676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3965 .loc 1 3676 3 is_stmt 1 view .LVU1312 +3676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3966 .loc 1 3676 12 is_stmt 0 view .LVU1313 + 3967 000a 036F ldr r3, [r0, #112] +3676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3968 .loc 1 3676 6 view .LVU1314 + 3969 000c 0BB1 cbz r3, .L156 +3678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3970 .loc 1 3678 5 is_stmt 1 view .LVU1315 +3678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3971 .loc 1 3678 22 is_stmt 0 view .LVU1316 + 3972 000e 1B6D ldr r3, [r3, #80] +3678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 3973 .loc 1 3678 8 view .LVU1317 + 3974 0010 ABB9 cbnz r3, .L155 + 3975 .L156: +3685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; + 3976 .loc 1 3685 3 is_stmt 1 view .LVU1318 +3685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; + 3977 .loc 1 3685 22 is_stmt 0 view .LVU1319 + 3978 0012 0023 movs r3, #0 + 3979 0014 A0F85230 strh r3, [r0, #82] @ movhi +3686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3980 .loc 1 3686 3 is_stmt 1 view .LVU1320 +3686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3981 .loc 1 3686 22 is_stmt 0 view .LVU1321 + 3982 0018 A0F85A30 strh r3, [r0, #90] @ movhi +3689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3983 .loc 1 3689 3 is_stmt 1 view .LVU1322 +3689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3984 .loc 1 3689 20 is_stmt 0 view .LVU1323 + 3985 001c C0F88430 str r3, [r0, #132] +3692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3986 .loc 1 3692 3 is_stmt 1 view .LVU1324 + 3987 0020 0268 ldr r2, [r0] + 3988 0022 0F21 movs r1, #15 + 3989 0024 1162 str r1, [r2, #32] +3695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 3990 .loc 1 3695 3 view .LVU1325 + 3991 0026 0168 ldr r1, [r0] + ARM GAS /tmp/ccQxTlMj.s page 178 + + + 3992 0028 8A69 ldr r2, [r1, #24] + 3993 002a 42F00802 orr r2, r2, #8 + 3994 002e 8A61 str r2, [r1, #24] +3698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 3995 .loc 1 3698 3 view .LVU1326 +3698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 3996 .loc 1 3698 18 is_stmt 0 view .LVU1327 + 3997 0030 2022 movs r2, #32 + 3998 0032 C267 str r2, [r0, #124] +3699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 3999 .loc 1 3699 3 is_stmt 1 view .LVU1328 +3699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 4000 .loc 1 3699 18 is_stmt 0 view .LVU1329 + 4001 0034 C0F88020 str r2, [r0, #128] +3700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4002 .loc 1 3700 3 is_stmt 1 view .LVU1330 +3700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4003 .loc 1 3700 24 is_stmt 0 view .LVU1331 + 4004 0038 0366 str r3, [r0, #96] +3708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4005 .loc 1 3708 3 is_stmt 1 view .LVU1332 + 4006 003a FFF7FEFF bl HAL_UART_AbortCpltCallback + 4007 .LVL349: + 4008 .L155: +3710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4009 .loc 1 3710 1 is_stmt 0 view .LVU1333 + 4010 003e 08BD pop {r3, pc} + 4011 .cfi_endproc + 4012 .LFE200: + 4014 .section .text.UART_DMATxAbortCallback,"ax",%progbits + 4015 .align 1 + 4016 .syntax unified + 4017 .thumb + 4018 .thumb_func + 4020 UART_DMATxAbortCallback: + 4021 .LVL350: + 4022 .LFB199: +3620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 4023 .loc 1 3620 1 is_stmt 1 view -0 + 4024 .cfi_startproc + 4025 @ args = 0, pretend = 0, frame = 0 + 4026 @ frame_needed = 0, uses_anonymous_args = 0 +3620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 4027 .loc 1 3620 1 is_stmt 0 view .LVU1335 + 4028 0000 08B5 push {r3, lr} + 4029 .LCFI19: + 4030 .cfi_def_cfa_offset 8 + 4031 .cfi_offset 3, -8 + 4032 .cfi_offset 14, -4 +3621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4033 .loc 1 3621 3 is_stmt 1 view .LVU1336 +3621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4034 .loc 1 3621 23 is_stmt 0 view .LVU1337 + 4035 0002 806B ldr r0, [r0, #56] + 4036 .LVL351: +3623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4037 .loc 1 3623 3 is_stmt 1 view .LVU1338 + ARM GAS /tmp/ccQxTlMj.s page 179 + + +3623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4038 .loc 1 3623 8 is_stmt 0 view .LVU1339 + 4039 0004 036F ldr r3, [r0, #112] +3623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4040 .loc 1 3623 36 view .LVU1340 + 4041 0006 0022 movs r2, #0 + 4042 0008 1A65 str r2, [r3, #80] +3626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4043 .loc 1 3626 3 is_stmt 1 view .LVU1341 +3626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4044 .loc 1 3626 12 is_stmt 0 view .LVU1342 + 4045 000a 436F ldr r3, [r0, #116] +3626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4046 .loc 1 3626 6 view .LVU1343 + 4047 000c 0BB1 cbz r3, .L160 +3628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4048 .loc 1 3628 5 is_stmt 1 view .LVU1344 +3628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4049 .loc 1 3628 22 is_stmt 0 view .LVU1345 + 4050 000e 1B6D ldr r3, [r3, #80] +3628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4051 .loc 1 3628 8 view .LVU1346 + 4052 0010 83B9 cbnz r3, .L159 + 4053 .L160: +3635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; + 4054 .loc 1 3635 3 is_stmt 1 view .LVU1347 +3635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = 0U; + 4055 .loc 1 3635 22 is_stmt 0 view .LVU1348 + 4056 0012 0023 movs r3, #0 + 4057 0014 A0F85230 strh r3, [r0, #82] @ movhi +3636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4058 .loc 1 3636 3 is_stmt 1 view .LVU1349 +3636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4059 .loc 1 3636 22 is_stmt 0 view .LVU1350 + 4060 0018 A0F85A30 strh r3, [r0, #90] @ movhi +3639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4061 .loc 1 3639 3 is_stmt 1 view .LVU1351 +3639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4062 .loc 1 3639 20 is_stmt 0 view .LVU1352 + 4063 001c C0F88430 str r3, [r0, #132] +3642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4064 .loc 1 3642 3 is_stmt 1 view .LVU1353 + 4065 0020 0268 ldr r2, [r0] + 4066 0022 0F21 movs r1, #15 + 4067 0024 1162 str r1, [r2, #32] +3646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 4068 .loc 1 3646 3 view .LVU1354 +3646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 4069 .loc 1 3646 18 is_stmt 0 view .LVU1355 + 4070 0026 2022 movs r2, #32 + 4071 0028 C267 str r2, [r0, #124] +3647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 4072 .loc 1 3647 3 is_stmt 1 view .LVU1356 +3647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 4073 .loc 1 3647 18 is_stmt 0 view .LVU1357 + 4074 002a C0F88020 str r2, [r0, #128] +3648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 180 + + + 4075 .loc 1 3648 3 is_stmt 1 view .LVU1358 +3648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4076 .loc 1 3648 24 is_stmt 0 view .LVU1359 + 4077 002e 0366 str r3, [r0, #96] +3656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4078 .loc 1 3656 3 is_stmt 1 view .LVU1360 + 4079 0030 FFF7FEFF bl HAL_UART_AbortCpltCallback + 4080 .LVL352: + 4081 .L159: +3658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4082 .loc 1 3658 1 is_stmt 0 view .LVU1361 + 4083 0034 08BD pop {r3, pc} + 4084 .cfi_endproc + 4085 .LFE199: + 4087 .section .text.HAL_UART_AbortTransmitCpltCallback,"ax",%progbits + 4088 .align 1 + 4089 .weak HAL_UART_AbortTransmitCpltCallback + 4090 .syntax unified + 4091 .thumb + 4092 .thumb_func + 4094 HAL_UART_AbortTransmitCpltCallback: + 4095 .LVL353: + 4096 .LFB170: +2525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 4097 .loc 1 2525 1 is_stmt 1 view -0 + 4098 .cfi_startproc + 4099 @ args = 0, pretend = 0, frame = 0 + 4100 @ frame_needed = 0, uses_anonymous_args = 0 + 4101 @ link register save eliminated. +2527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4102 .loc 1 2527 3 view .LVU1363 +2532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4103 .loc 1 2532 1 is_stmt 0 view .LVU1364 + 4104 0000 7047 bx lr + 4105 .cfi_endproc + 4106 .LFE170: + 4108 .section .text.HAL_UART_AbortTransmit_IT,"ax",%progbits + 4109 .align 1 + 4110 .global HAL_UART_AbortTransmit_IT + 4111 .syntax unified + 4112 .thumb + 4113 .thumb_func + 4115 HAL_UART_AbortTransmit_IT: + 4116 .LVL354: + 4117 .LFB161: +1951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable interrupts */ + 4118 .loc 1 1951 1 is_stmt 1 view -0 + 4119 .cfi_startproc + 4120 @ args = 0, pretend = 0, frame = 0 + 4121 @ frame_needed = 0, uses_anonymous_args = 0 +1951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable interrupts */ + 4122 .loc 1 1951 1 is_stmt 0 view .LVU1366 + 4123 0000 10B5 push {r4, lr} + 4124 .LCFI20: + 4125 .cfi_def_cfa_offset 8 + 4126 .cfi_offset 4, -8 + 4127 .cfi_offset 14, -4 + ARM GAS /tmp/ccQxTlMj.s page 181 + + + 4128 0002 0446 mov r4, r0 + 4129 .L165: +1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4130 .loc 1 1953 3 is_stmt 1 discriminator 1 view .LVU1367 + 4131 .LBB610: +1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4132 .loc 1 1953 3 discriminator 1 view .LVU1368 +1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4133 .loc 1 1953 3 discriminator 1 view .LVU1369 +1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4134 .loc 1 1953 3 discriminator 1 view .LVU1370 + 4135 0004 2268 ldr r2, [r4] + 4136 .LVL355: + 4137 .LBB611: + 4138 .LBI611: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 4139 .loc 2 1068 31 view .LVU1371 + 4140 .LBB612: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 4141 .loc 2 1070 5 view .LVU1372 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4142 .loc 2 1072 4 view .LVU1373 + 4143 .syntax unified + 4144 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 4145 0006 52E8003F ldrex r3, [r2] + 4146 @ 0 "" 2 + 4147 .LVL356: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 4148 .loc 2 1073 4 view .LVU1374 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 4149 .loc 2 1073 4 is_stmt 0 view .LVU1375 + 4150 .thumb + 4151 .syntax unified + 4152 .LBE612: + 4153 .LBE611: +1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4154 .loc 1 1953 3 discriminator 1 view .LVU1376 + 4155 000a 23F0C003 bic r3, r3, #192 + 4156 .LVL357: +1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4157 .loc 1 1953 3 is_stmt 1 discriminator 1 view .LVU1377 + 4158 .LBB613: + 4159 .LBI613: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 4160 .loc 2 1119 31 view .LVU1378 + 4161 .LBB614: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 4162 .loc 2 1121 4 view .LVU1379 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4163 .loc 2 1123 4 view .LVU1380 + 4164 .syntax unified + 4165 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 4166 000e 42E80031 strex r1, r3, [r2] + 4167 @ 0 "" 2 + 4168 .LVL358: + 4169 .loc 2 1124 4 view .LVU1381 + 4170 .loc 2 1124 4 is_stmt 0 view .LVU1382 + ARM GAS /tmp/ccQxTlMj.s page 182 + + + 4171 .thumb + 4172 .syntax unified + 4173 .LBE614: + 4174 .LBE613: +1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4175 .loc 1 1953 3 discriminator 1 view .LVU1383 + 4176 0012 0029 cmp r1, #0 + 4177 0014 F6D1 bne .L165 + 4178 .LBE610: +1953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4179 .loc 1 1953 3 is_stmt 1 discriminator 2 view .LVU1384 +1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4180 .loc 1 1956 3 view .LVU1385 +1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4181 .loc 1 1956 7 is_stmt 0 view .LVU1386 + 4182 0016 2368 ldr r3, [r4] + 4183 .LVL359: +1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4184 .loc 1 1956 7 view .LVU1387 + 4185 0018 9B68 ldr r3, [r3, #8] +1956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4186 .loc 1 1956 6 view .LVU1388 + 4187 001a 13F0800F tst r3, #128 + 4188 001e 21D0 beq .L166 + 4189 .L167: +1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4190 .loc 1 1959 5 is_stmt 1 discriminator 1 view .LVU1389 + 4191 .LBB615: +1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4192 .loc 1 1959 5 discriminator 1 view .LVU1390 +1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4193 .loc 1 1959 5 discriminator 1 view .LVU1391 +1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4194 .loc 1 1959 5 discriminator 1 view .LVU1392 + 4195 0020 2268 ldr r2, [r4] + 4196 .LVL360: + 4197 .LBB616: + 4198 .LBI616: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 4199 .loc 2 1068 31 view .LVU1393 + 4200 .LBB617: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 4201 .loc 2 1070 5 view .LVU1394 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4202 .loc 2 1072 4 view .LVU1395 + 4203 0022 02F10803 add r3, r2, #8 + 4204 .LVL361: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4205 .loc 2 1072 4 is_stmt 0 view .LVU1396 + 4206 .syntax unified + 4207 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 4208 0026 53E8003F ldrex r3, [r3] + 4209 @ 0 "" 2 + 4210 .LVL362: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 4211 .loc 2 1073 4 is_stmt 1 view .LVU1397 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccQxTlMj.s page 183 + + + 4212 .loc 2 1073 4 is_stmt 0 view .LVU1398 + 4213 .thumb + 4214 .syntax unified + 4215 .LBE617: + 4216 .LBE616: +1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4217 .loc 1 1959 5 discriminator 1 view .LVU1399 + 4218 002a 23F08003 bic r3, r3, #128 + 4219 .LVL363: +1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4220 .loc 1 1959 5 is_stmt 1 discriminator 1 view .LVU1400 + 4221 .LBB618: + 4222 .LBI618: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 4223 .loc 2 1119 31 view .LVU1401 + 4224 .LBB619: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 4225 .loc 2 1121 4 view .LVU1402 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4226 .loc 2 1123 4 view .LVU1403 + 4227 002e 0832 adds r2, r2, #8 + 4228 .LVL364: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4229 .loc 2 1123 4 is_stmt 0 view .LVU1404 + 4230 .syntax unified + 4231 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 4232 0030 42E80031 strex r1, r3, [r2] + 4233 @ 0 "" 2 + 4234 .LVL365: + 4235 .loc 2 1124 4 is_stmt 1 view .LVU1405 + 4236 .loc 2 1124 4 is_stmt 0 view .LVU1406 + 4237 .thumb + 4238 .syntax unified + 4239 .LBE619: + 4240 .LBE618: +1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4241 .loc 1 1959 5 discriminator 1 view .LVU1407 + 4242 0034 0029 cmp r1, #0 + 4243 0036 F3D1 bne .L167 + 4244 .LBE615: +1959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4245 .loc 1 1959 5 is_stmt 1 discriminator 2 view .LVU1408 +1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4246 .loc 1 1962 5 view .LVU1409 +1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4247 .loc 1 1962 14 is_stmt 0 view .LVU1410 + 4248 0038 236F ldr r3, [r4, #112] + 4249 .LVL366: +1962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4250 .loc 1 1962 8 view .LVU1411 + 4251 003a 4BB1 cbz r3, .L168 +1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4252 .loc 1 1966 7 is_stmt 1 view .LVU1412 +1966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4253 .loc 1 1966 40 is_stmt 0 view .LVU1413 + 4254 003c 0F4A ldr r2, .L171 + 4255 003e 1A65 str r2, [r3, #80] + ARM GAS /tmp/ccQxTlMj.s page 184 + + +1969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4256 .loc 1 1969 7 is_stmt 1 view .LVU1414 +1969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4257 .loc 1 1969 11 is_stmt 0 view .LVU1415 + 4258 0040 206F ldr r0, [r4, #112] + 4259 .LVL367: +1969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4260 .loc 1 1969 11 view .LVU1416 + 4261 0042 FFF7FEFF bl HAL_DMA_Abort_IT + 4262 .LVL368: +1969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4263 .loc 1 1969 10 discriminator 1 view .LVU1417 + 4264 0046 B0B1 cbz r0, .L169 +1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4265 .loc 1 1972 9 is_stmt 1 view .LVU1418 +1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4266 .loc 1 1972 14 is_stmt 0 view .LVU1419 + 4267 0048 206F ldr r0, [r4, #112] +1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4268 .loc 1 1972 22 view .LVU1420 + 4269 004a 036D ldr r3, [r0, #80] +1972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4270 .loc 1 1972 9 view .LVU1421 + 4271 004c 9847 blx r3 + 4272 .LVL369: + 4273 004e 12E0 b .L169 + 4274 .LVL370: + 4275 .L168: +1978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4276 .loc 1 1978 7 is_stmt 1 view .LVU1422 +1978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4277 .loc 1 1978 26 is_stmt 0 view .LVU1423 + 4278 0050 0023 movs r3, #0 + 4279 0052 A4F85230 strh r3, [r4, #82] @ movhi +1981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4280 .loc 1 1981 7 is_stmt 1 view .LVU1424 +1981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4281 .loc 1 1981 20 is_stmt 0 view .LVU1425 + 4282 0056 E366 str r3, [r4, #108] +1984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4283 .loc 1 1984 7 is_stmt 1 view .LVU1426 +1984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4284 .loc 1 1984 21 is_stmt 0 view .LVU1427 + 4285 0058 2023 movs r3, #32 + 4286 005a E367 str r3, [r4, #124] +1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4287 .loc 1 1992 7 is_stmt 1 view .LVU1428 + 4288 005c 2046 mov r0, r4 + 4289 .LVL371: +1992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4290 .loc 1 1992 7 is_stmt 0 view .LVU1429 + 4291 005e FFF7FEFF bl HAL_UART_AbortTransmitCpltCallback + 4292 .LVL372: + 4293 0062 08E0 b .L169 + 4294 .LVL373: + 4295 .L166: +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 185 + + + 4296 .loc 1 1999 5 is_stmt 1 view .LVU1430 +1999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4297 .loc 1 1999 24 is_stmt 0 view .LVU1431 + 4298 0064 0023 movs r3, #0 + 4299 0066 A4F85230 strh r3, [r4, #82] @ movhi +2002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4300 .loc 1 2002 5 is_stmt 1 view .LVU1432 +2002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4301 .loc 1 2002 18 is_stmt 0 view .LVU1433 + 4302 006a E366 str r3, [r4, #108] +2006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4303 .loc 1 2006 5 is_stmt 1 view .LVU1434 +2006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4304 .loc 1 2006 19 is_stmt 0 view .LVU1435 + 4305 006c 2023 movs r3, #32 + 4306 006e E367 str r3, [r4, #124] +2014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4307 .loc 1 2014 5 is_stmt 1 view .LVU1436 + 4308 0070 2046 mov r0, r4 + 4309 .LVL374: +2014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4310 .loc 1 2014 5 is_stmt 0 view .LVU1437 + 4311 0072 FFF7FEFF bl HAL_UART_AbortTransmitCpltCallback + 4312 .LVL375: + 4313 .L169: +2018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4314 .loc 1 2018 3 is_stmt 1 view .LVU1438 +2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4315 .loc 1 2019 1 is_stmt 0 view .LVU1439 + 4316 0076 0020 movs r0, #0 + 4317 0078 10BD pop {r4, pc} + 4318 .LVL376: + 4319 .L172: +2019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4320 .loc 1 2019 1 view .LVU1440 + 4321 007a 00BF .align 2 + 4322 .L171: + 4323 007c 00000000 .word UART_DMATxOnlyAbortCallback + 4324 .cfi_endproc + 4325 .LFE161: + 4327 .section .text.UART_DMATxOnlyAbortCallback,"ax",%progbits + 4328 .align 1 + 4329 .syntax unified + 4330 .thumb + 4331 .thumb_func + 4333 UART_DMATxOnlyAbortCallback: + 4334 .LVL377: + 4335 .LFB201: +3722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 4336 .loc 1 3722 1 is_stmt 1 view -0 + 4337 .cfi_startproc + 4338 @ args = 0, pretend = 0, frame = 0 + 4339 @ frame_needed = 0, uses_anonymous_args = 0 +3722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 4340 .loc 1 3722 1 is_stmt 0 view .LVU1442 + 4341 0000 08B5 push {r3, lr} + 4342 .LCFI21: + ARM GAS /tmp/ccQxTlMj.s page 186 + + + 4343 .cfi_def_cfa_offset 8 + 4344 .cfi_offset 3, -8 + 4345 .cfi_offset 14, -4 +3723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4346 .loc 1 3723 3 is_stmt 1 view .LVU1443 +3723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4347 .loc 1 3723 23 is_stmt 0 view .LVU1444 + 4348 0002 806B ldr r0, [r0, #56] + 4349 .LVL378: +3725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4350 .loc 1 3725 3 is_stmt 1 view .LVU1445 +3725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4351 .loc 1 3725 22 is_stmt 0 view .LVU1446 + 4352 0004 0023 movs r3, #0 + 4353 0006 A0F85230 strh r3, [r0, #82] @ movhi +3729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4354 .loc 1 3729 3 is_stmt 1 view .LVU1447 +3729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4355 .loc 1 3729 17 is_stmt 0 view .LVU1448 + 4356 000a 2023 movs r3, #32 + 4357 000c C367 str r3, [r0, #124] +3737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4358 .loc 1 3737 3 is_stmt 1 view .LVU1449 + 4359 000e FFF7FEFF bl HAL_UART_AbortTransmitCpltCallback + 4360 .LVL379: +3739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4361 .loc 1 3739 1 is_stmt 0 view .LVU1450 + 4362 0012 08BD pop {r3, pc} + 4363 .cfi_endproc + 4364 .LFE201: + 4366 .section .text.HAL_UART_AbortReceiveCpltCallback,"ax",%progbits + 4367 .align 1 + 4368 .weak HAL_UART_AbortReceiveCpltCallback + 4369 .syntax unified + 4370 .thumb + 4371 .thumb_func + 4373 HAL_UART_AbortReceiveCpltCallback: + 4374 .LVL380: + 4375 .LFB171: +2540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 4376 .loc 1 2540 1 is_stmt 1 view -0 + 4377 .cfi_startproc + 4378 @ args = 0, pretend = 0, frame = 0 + 4379 @ frame_needed = 0, uses_anonymous_args = 0 + 4380 @ link register save eliminated. +2542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4381 .loc 1 2542 3 view .LVU1452 +2547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4382 .loc 1 2547 1 is_stmt 0 view .LVU1453 + 4383 0000 7047 bx lr + 4384 .cfi_endproc + 4385 .LFE171: + 4387 .section .text.HAL_UART_AbortReceive_IT,"ax",%progbits + 4388 .align 1 + 4389 .global HAL_UART_AbortReceive_IT + 4390 .syntax unified + 4391 .thumb + ARM GAS /tmp/ccQxTlMj.s page 187 + + + 4392 .thumb_func + 4394 HAL_UART_AbortReceive_IT: + 4395 .LVL381: + 4396 .LFB162: +2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + 4397 .loc 1 2036 1 is_stmt 1 view -0 + 4398 .cfi_startproc + 4399 @ args = 0, pretend = 0, frame = 0 + 4400 @ frame_needed = 0, uses_anonymous_args = 0 +2036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + 4401 .loc 1 2036 1 is_stmt 0 view .LVU1455 + 4402 0000 10B5 push {r4, lr} + 4403 .LCFI22: + 4404 .cfi_def_cfa_offset 8 + 4405 .cfi_offset 4, -8 + 4406 .cfi_offset 14, -4 + 4407 0002 0446 mov r4, r0 + 4408 .L177: +2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 4409 .loc 1 2038 3 is_stmt 1 discriminator 1 view .LVU1456 + 4410 .LBB620: +2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 4411 .loc 1 2038 3 discriminator 1 view .LVU1457 +2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 4412 .loc 1 2038 3 discriminator 1 view .LVU1458 +2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 4413 .loc 1 2038 3 discriminator 1 view .LVU1459 + 4414 0004 2268 ldr r2, [r4] + 4415 .LVL382: + 4416 .LBB621: + 4417 .LBI621: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 4418 .loc 2 1068 31 view .LVU1460 + 4419 .LBB622: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 4420 .loc 2 1070 5 view .LVU1461 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4421 .loc 2 1072 4 view .LVU1462 + 4422 .syntax unified + 4423 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 4424 0006 52E8003F ldrex r3, [r2] + 4425 @ 0 "" 2 + 4426 .LVL383: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 4427 .loc 2 1073 4 view .LVU1463 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 4428 .loc 2 1073 4 is_stmt 0 view .LVU1464 + 4429 .thumb + 4430 .syntax unified + 4431 .LBE622: + 4432 .LBE621: +2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 4433 .loc 1 2038 3 discriminator 1 view .LVU1465 + 4434 000a 23F49073 bic r3, r3, #288 + 4435 .LVL384: +2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 4436 .loc 1 2038 3 is_stmt 1 discriminator 1 view .LVU1466 + ARM GAS /tmp/ccQxTlMj.s page 188 + + + 4437 .LBB623: + 4438 .LBI623: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 4439 .loc 2 1119 31 view .LVU1467 + 4440 .LBB624: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 4441 .loc 2 1121 4 view .LVU1468 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4442 .loc 2 1123 4 view .LVU1469 + 4443 .syntax unified + 4444 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 4445 000e 42E80031 strex r1, r3, [r2] + 4446 @ 0 "" 2 + 4447 .LVL385: + 4448 .loc 2 1124 4 view .LVU1470 + 4449 .loc 2 1124 4 is_stmt 0 view .LVU1471 + 4450 .thumb + 4451 .syntax unified + 4452 .LBE624: + 4453 .LBE623: +2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 4454 .loc 1 2038 3 discriminator 1 view .LVU1472 + 4455 0012 0029 cmp r1, #0 + 4456 0014 F6D1 bne .L177 + 4457 .LVL386: + 4458 .L178: +2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 4459 .loc 1 2038 3 discriminator 1 view .LVU1473 + 4460 .LBE620: +2038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 4461 .loc 1 2038 3 is_stmt 1 discriminator 2 view .LVU1474 +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4462 .loc 1 2039 3 discriminator 1 view .LVU1475 + 4463 .LBB625: +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4464 .loc 1 2039 3 discriminator 1 view .LVU1476 +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4465 .loc 1 2039 3 discriminator 1 view .LVU1477 +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4466 .loc 1 2039 3 discriminator 1 view .LVU1478 + 4467 0016 2268 ldr r2, [r4] + 4468 .LVL387: + 4469 .LBB626: + 4470 .LBI626: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 4471 .loc 2 1068 31 view .LVU1479 + 4472 .LBB627: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 4473 .loc 2 1070 5 view .LVU1480 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4474 .loc 2 1072 4 view .LVU1481 + 4475 0018 02F10803 add r3, r2, #8 + 4476 .LVL388: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4477 .loc 2 1072 4 is_stmt 0 view .LVU1482 + 4478 .syntax unified + 4479 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + ARM GAS /tmp/ccQxTlMj.s page 189 + + + 4480 001c 53E8003F ldrex r3, [r3] + 4481 @ 0 "" 2 + 4482 .LVL389: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 4483 .loc 2 1073 4 is_stmt 1 view .LVU1483 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 4484 .loc 2 1073 4 is_stmt 0 view .LVU1484 + 4485 .thumb + 4486 .syntax unified + 4487 .LBE627: + 4488 .LBE626: +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4489 .loc 1 2039 3 discriminator 1 view .LVU1485 + 4490 0020 23F00103 bic r3, r3, #1 + 4491 .LVL390: +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4492 .loc 1 2039 3 is_stmt 1 discriminator 1 view .LVU1486 + 4493 .LBB628: + 4494 .LBI628: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 4495 .loc 2 1119 31 view .LVU1487 + 4496 .LBB629: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 4497 .loc 2 1121 4 view .LVU1488 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4498 .loc 2 1123 4 view .LVU1489 + 4499 0024 0832 adds r2, r2, #8 + 4500 .LVL391: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4501 .loc 2 1123 4 is_stmt 0 view .LVU1490 + 4502 .syntax unified + 4503 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 4504 0026 42E80031 strex r1, r3, [r2] + 4505 @ 0 "" 2 + 4506 .LVL392: + 4507 .loc 2 1124 4 is_stmt 1 view .LVU1491 + 4508 .loc 2 1124 4 is_stmt 0 view .LVU1492 + 4509 .thumb + 4510 .syntax unified + 4511 .LBE629: + 4512 .LBE628: +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4513 .loc 1 2039 3 discriminator 1 view .LVU1493 + 4514 002a 0029 cmp r1, #0 + 4515 002c F3D1 bne .L178 + 4516 .LBE625: +2039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4517 .loc 1 2039 3 is_stmt 1 discriminator 2 view .LVU1494 +2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4518 .loc 1 2042 3 view .LVU1495 +2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4519 .loc 1 2042 12 is_stmt 0 view .LVU1496 + 4520 002e 236E ldr r3, [r4, #96] + 4521 .LVL393: +2042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4522 .loc 1 2042 6 view .LVU1497 + 4523 0030 012B cmp r3, #1 + ARM GAS /tmp/ccQxTlMj.s page 190 + + + 4524 0032 1CD0 beq .L180 + 4525 .L179: +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4526 .loc 1 2044 5 is_stmt 1 discriminator 2 view .LVU1498 +2048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4527 .loc 1 2048 3 view .LVU1499 +2048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4528 .loc 1 2048 7 is_stmt 0 view .LVU1500 + 4529 0034 2368 ldr r3, [r4] + 4530 0036 9A68 ldr r2, [r3, #8] +2048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4531 .loc 1 2048 6 view .LVU1501 + 4532 0038 12F0400F tst r2, #64 + 4533 003c 35D0 beq .L181 + 4534 .L182: +2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4535 .loc 1 2051 5 is_stmt 1 discriminator 1 view .LVU1502 + 4536 .LBB630: +2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4537 .loc 1 2051 5 discriminator 1 view .LVU1503 +2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4538 .loc 1 2051 5 discriminator 1 view .LVU1504 +2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4539 .loc 1 2051 5 discriminator 1 view .LVU1505 + 4540 003e 2268 ldr r2, [r4] + 4541 .LVL394: + 4542 .LBB631: + 4543 .LBI631: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 4544 .loc 2 1068 31 view .LVU1506 + 4545 .LBB632: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 4546 .loc 2 1070 5 view .LVU1507 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4547 .loc 2 1072 4 view .LVU1508 + 4548 0040 02F10803 add r3, r2, #8 + 4549 .LVL395: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4550 .loc 2 1072 4 is_stmt 0 view .LVU1509 + 4551 .syntax unified + 4552 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 4553 0044 53E8003F ldrex r3, [r3] + 4554 @ 0 "" 2 + 4555 .LVL396: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 4556 .loc 2 1073 4 is_stmt 1 view .LVU1510 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 4557 .loc 2 1073 4 is_stmt 0 view .LVU1511 + 4558 .thumb + 4559 .syntax unified + 4560 .LBE632: + 4561 .LBE631: +2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4562 .loc 1 2051 5 discriminator 1 view .LVU1512 + 4563 0048 23F04003 bic r3, r3, #64 + 4564 .LVL397: +2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 191 + + + 4565 .loc 1 2051 5 is_stmt 1 discriminator 1 view .LVU1513 + 4566 .LBB633: + 4567 .LBI633: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 4568 .loc 2 1119 31 view .LVU1514 + 4569 .LBB634: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 4570 .loc 2 1121 4 view .LVU1515 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4571 .loc 2 1123 4 view .LVU1516 + 4572 004c 0832 adds r2, r2, #8 + 4573 .LVL398: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4574 .loc 2 1123 4 is_stmt 0 view .LVU1517 + 4575 .syntax unified + 4576 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 4577 004e 42E80031 strex r1, r3, [r2] + 4578 @ 0 "" 2 + 4579 .LVL399: + 4580 .loc 2 1124 4 is_stmt 1 view .LVU1518 + 4581 .loc 2 1124 4 is_stmt 0 view .LVU1519 + 4582 .thumb + 4583 .syntax unified + 4584 .LBE634: + 4585 .LBE633: +2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4586 .loc 1 2051 5 discriminator 1 view .LVU1520 + 4587 0052 0029 cmp r1, #0 + 4588 0054 F3D1 bne .L182 + 4589 .LBE630: +2051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4590 .loc 1 2051 5 is_stmt 1 discriminator 2 view .LVU1521 +2054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4591 .loc 1 2054 5 view .LVU1522 +2054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4592 .loc 1 2054 14 is_stmt 0 view .LVU1523 + 4593 0056 636F ldr r3, [r4, #116] + 4594 .LVL400: +2054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4595 .loc 1 2054 8 view .LVU1524 + 4596 0058 9BB1 cbz r3, .L183 +2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4597 .loc 1 2058 7 is_stmt 1 view .LVU1525 +2058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4598 .loc 1 2058 40 is_stmt 0 view .LVU1526 + 4599 005a 1B4A ldr r2, .L186 + 4600 005c 1A65 str r2, [r3, #80] +2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4601 .loc 1 2061 7 is_stmt 1 view .LVU1527 +2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4602 .loc 1 2061 11 is_stmt 0 view .LVU1528 + 4603 005e 606F ldr r0, [r4, #116] + 4604 .LVL401: +2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4605 .loc 1 2061 11 view .LVU1529 + 4606 0060 FFF7FEFF bl HAL_DMA_Abort_IT + 4607 .LVL402: + ARM GAS /tmp/ccQxTlMj.s page 192 + + +2061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4608 .loc 1 2061 10 discriminator 1 view .LVU1530 + 4609 0064 70B3 cbz r0, .L184 +2064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4610 .loc 1 2064 9 is_stmt 1 view .LVU1531 +2064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4611 .loc 1 2064 14 is_stmt 0 view .LVU1532 + 4612 0066 606F ldr r0, [r4, #116] +2064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4613 .loc 1 2064 22 view .LVU1533 + 4614 0068 036D ldr r3, [r0, #80] +2064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4615 .loc 1 2064 9 view .LVU1534 + 4616 006a 9847 blx r3 + 4617 .LVL403: + 4618 006c 2AE0 b .L184 + 4619 .LVL404: + 4620 .L180: +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4621 .loc 1 2044 5 is_stmt 1 discriminator 1 view .LVU1535 + 4622 .LBB635: +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4623 .loc 1 2044 5 discriminator 1 view .LVU1536 +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4624 .loc 1 2044 5 discriminator 1 view .LVU1537 +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4625 .loc 1 2044 5 discriminator 1 view .LVU1538 + 4626 006e 2268 ldr r2, [r4] + 4627 .LVL405: + 4628 .LBB636: + 4629 .LBI636: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 4630 .loc 2 1068 31 view .LVU1539 + 4631 .LBB637: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 4632 .loc 2 1070 5 view .LVU1540 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4633 .loc 2 1072 4 view .LVU1541 + 4634 .syntax unified + 4635 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 4636 0070 52E8003F ldrex r3, [r2] + 4637 @ 0 "" 2 + 4638 .LVL406: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 4639 .loc 2 1073 4 view .LVU1542 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 4640 .loc 2 1073 4 is_stmt 0 view .LVU1543 + 4641 .thumb + 4642 .syntax unified + 4643 .LBE637: + 4644 .LBE636: +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4645 .loc 1 2044 5 discriminator 1 view .LVU1544 + 4646 0074 23F01003 bic r3, r3, #16 + 4647 .LVL407: +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4648 .loc 1 2044 5 is_stmt 1 discriminator 1 view .LVU1545 + ARM GAS /tmp/ccQxTlMj.s page 193 + + + 4649 .LBB638: + 4650 .LBI638: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 4651 .loc 2 1119 31 view .LVU1546 + 4652 .LBB639: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 4653 .loc 2 1121 4 view .LVU1547 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4654 .loc 2 1123 4 view .LVU1548 + 4655 .syntax unified + 4656 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 4657 0078 42E80031 strex r1, r3, [r2] + 4658 @ 0 "" 2 + 4659 .LVL408: + 4660 .loc 2 1124 4 view .LVU1549 + 4661 .loc 2 1124 4 is_stmt 0 view .LVU1550 + 4662 .thumb + 4663 .syntax unified + 4664 .LBE639: + 4665 .LBE638: +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4666 .loc 1 2044 5 discriminator 1 view .LVU1551 + 4667 007c 0029 cmp r1, #0 + 4668 007e F6D1 bne .L180 + 4669 0080 D8E7 b .L179 + 4670 .LVL409: + 4671 .L183: +2044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4672 .loc 1 2044 5 discriminator 1 view .LVU1552 + 4673 .LBE635: +2070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4674 .loc 1 2070 7 is_stmt 1 view .LVU1553 +2070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4675 .loc 1 2070 26 is_stmt 0 view .LVU1554 + 4676 0082 0023 movs r3, #0 + 4677 0084 A4F85A30 strh r3, [r4, #90] @ movhi +2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4678 .loc 1 2073 7 is_stmt 1 view .LVU1555 +2073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4679 .loc 1 2073 25 is_stmt 0 view .LVU1556 + 4680 0088 6365 str r3, [r4, #84] +2076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4681 .loc 1 2076 7 is_stmt 1 view .LVU1557 + 4682 008a 2268 ldr r2, [r4] + 4683 008c 0F21 movs r1, #15 + 4684 008e 1162 str r1, [r2, #32] +2079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4685 .loc 1 2079 7 view .LVU1558 + 4686 0090 2168 ldr r1, [r4] + 4687 0092 8A69 ldr r2, [r1, #24] + 4688 0094 42F00802 orr r2, r2, #8 + 4689 0098 8A61 str r2, [r1, #24] +2082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 4690 .loc 1 2082 7 view .LVU1559 +2082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 4691 .loc 1 2082 22 is_stmt 0 view .LVU1560 + 4692 009a 2022 movs r2, #32 + ARM GAS /tmp/ccQxTlMj.s page 194 + + + 4693 009c C4F88020 str r2, [r4, #128] +2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4694 .loc 1 2083 7 is_stmt 1 view .LVU1561 +2083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4695 .loc 1 2083 28 is_stmt 0 view .LVU1562 + 4696 00a0 2366 str r3, [r4, #96] +2091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4697 .loc 1 2091 7 is_stmt 1 view .LVU1563 + 4698 00a2 2046 mov r0, r4 + 4699 .LVL410: +2091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4700 .loc 1 2091 7 is_stmt 0 view .LVU1564 + 4701 00a4 FFF7FEFF bl HAL_UART_AbortReceiveCpltCallback + 4702 .LVL411: + 4703 00a8 0CE0 b .L184 + 4704 .LVL412: + 4705 .L181: +2098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4706 .loc 1 2098 5 is_stmt 1 view .LVU1565 +2098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4707 .loc 1 2098 24 is_stmt 0 view .LVU1566 + 4708 00aa 0022 movs r2, #0 + 4709 00ac A4F85A20 strh r2, [r4, #90] @ movhi +2101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4710 .loc 1 2101 5 is_stmt 1 view .LVU1567 +2101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4711 .loc 1 2101 23 is_stmt 0 view .LVU1568 + 4712 00b0 6265 str r2, [r4, #84] +2104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4713 .loc 1 2104 5 is_stmt 1 view .LVU1569 + 4714 00b2 0F21 movs r1, #15 + 4715 00b4 1962 str r1, [r3, #32] +2107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 4716 .loc 1 2107 5 view .LVU1570 +2107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 4717 .loc 1 2107 20 is_stmt 0 view .LVU1571 + 4718 00b6 2023 movs r3, #32 + 4719 00b8 C4F88030 str r3, [r4, #128] +2108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4720 .loc 1 2108 5 is_stmt 1 view .LVU1572 +2108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4721 .loc 1 2108 26 is_stmt 0 view .LVU1573 + 4722 00bc 2266 str r2, [r4, #96] +2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4723 .loc 1 2116 5 is_stmt 1 view .LVU1574 + 4724 00be 2046 mov r0, r4 + 4725 .LVL413: +2116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4726 .loc 1 2116 5 is_stmt 0 view .LVU1575 + 4727 00c0 FFF7FEFF bl HAL_UART_AbortReceiveCpltCallback + 4728 .LVL414: + 4729 .L184: +2120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4730 .loc 1 2120 3 is_stmt 1 view .LVU1576 +2121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4731 .loc 1 2121 1 is_stmt 0 view .LVU1577 + 4732 00c4 0020 movs r0, #0 + ARM GAS /tmp/ccQxTlMj.s page 195 + + + 4733 00c6 10BD pop {r4, pc} + 4734 .LVL415: + 4735 .L187: +2121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4736 .loc 1 2121 1 view .LVU1578 + 4737 .align 2 + 4738 .L186: + 4739 00c8 00000000 .word UART_DMARxOnlyAbortCallback + 4740 .cfi_endproc + 4741 .LFE162: + 4743 .section .text.UART_DMARxOnlyAbortCallback,"ax",%progbits + 4744 .align 1 + 4745 .syntax unified + 4746 .thumb + 4747 .thumb_func + 4749 UART_DMARxOnlyAbortCallback: + 4750 .LVL416: + 4751 .LFB202: +3750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 4752 .loc 1 3750 1 is_stmt 1 view -0 + 4753 .cfi_startproc + 4754 @ args = 0, pretend = 0, frame = 0 + 4755 @ frame_needed = 0, uses_anonymous_args = 0 +3750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 4756 .loc 1 3750 1 is_stmt 0 view .LVU1580 + 4757 0000 08B5 push {r3, lr} + 4758 .LCFI23: + 4759 .cfi_def_cfa_offset 8 + 4760 .cfi_offset 3, -8 + 4761 .cfi_offset 14, -4 +3751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4762 .loc 1 3751 3 is_stmt 1 view .LVU1581 +3751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4763 .loc 1 3751 23 is_stmt 0 view .LVU1582 + 4764 0002 806B ldr r0, [r0, #56] + 4765 .LVL417: +3753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4766 .loc 1 3753 3 is_stmt 1 view .LVU1583 +3753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4767 .loc 1 3753 22 is_stmt 0 view .LVU1584 + 4768 0004 0022 movs r2, #0 + 4769 0006 A0F85A20 strh r2, [r0, #90] @ movhi +3756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4770 .loc 1 3756 3 is_stmt 1 view .LVU1585 + 4771 000a 0368 ldr r3, [r0] + 4772 000c 0F21 movs r1, #15 + 4773 000e 1962 str r1, [r3, #32] +3759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4774 .loc 1 3759 3 view .LVU1586 + 4775 0010 0168 ldr r1, [r0] + 4776 0012 8B69 ldr r3, [r1, #24] + 4777 0014 43F00803 orr r3, r3, #8 + 4778 0018 8B61 str r3, [r1, #24] +3762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 4779 .loc 1 3762 3 view .LVU1587 +3762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 4780 .loc 1 3762 18 is_stmt 0 view .LVU1588 + ARM GAS /tmp/ccQxTlMj.s page 196 + + + 4781 001a 2023 movs r3, #32 + 4782 001c C0F88030 str r3, [r0, #128] +3763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4783 .loc 1 3763 3 is_stmt 1 view .LVU1589 +3763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4784 .loc 1 3763 24 is_stmt 0 view .LVU1590 + 4785 0020 0266 str r2, [r0, #96] +3771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 4786 .loc 1 3771 3 is_stmt 1 view .LVU1591 + 4787 0022 FFF7FEFF bl HAL_UART_AbortReceiveCpltCallback + 4788 .LVL418: +3773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4789 .loc 1 3773 1 is_stmt 0 view .LVU1592 + 4790 0026 08BD pop {r3, pc} + 4791 .cfi_endproc + 4792 .LFE202: + 4794 .section .text.HAL_UARTEx_RxEventCallback,"ax",%progbits + 4795 .align 1 + 4796 .weak HAL_UARTEx_RxEventCallback + 4797 .syntax unified + 4798 .thumb + 4799 .thumb_func + 4801 HAL_UARTEx_RxEventCallback: + 4802 .LVL419: + 4803 .LFB172: +2557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 4804 .loc 1 2557 1 is_stmt 1 view -0 + 4805 .cfi_startproc + 4806 @ args = 0, pretend = 0, frame = 0 + 4807 @ frame_needed = 0, uses_anonymous_args = 0 + 4808 @ link register save eliminated. +2559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UNUSED(Size); + 4809 .loc 1 2559 3 view .LVU1594 +2560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4810 .loc 1 2560 3 view .LVU1595 +2565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4811 .loc 1 2565 1 is_stmt 0 view .LVU1596 + 4812 0000 7047 bx lr + 4813 .cfi_endproc + 4814 .LFE172: + 4816 .section .text.UART_RxISR_8BIT,"ax",%progbits + 4817 .align 1 + 4818 .syntax unified + 4819 .thumb + 4820 .thumb_func + 4822 UART_RxISR_8BIT: + 4823 .LVL420: + 4824 .LFB206: +3862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief RX interrupt handler for 7 or 8 bits data word length . +3865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +3866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +3867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +3869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4825 .loc 1 3869 1 is_stmt 1 view -0 + ARM GAS /tmp/ccQxTlMj.s page 197 + + + 4826 .cfi_startproc + 4827 @ args = 0, pretend = 0, frame = 0 + 4828 @ frame_needed = 0, uses_anonymous_args = 0 + 4829 .loc 1 3869 1 is_stmt 0 view .LVU1598 + 4830 0000 08B5 push {r3, lr} + 4831 .LCFI24: + 4832 .cfi_def_cfa_offset 8 + 4833 .cfi_offset 3, -8 + 4834 .cfi_offset 14, -4 +3870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint16_t uhMask = huart->Mask; + 4835 .loc 1 3870 3 is_stmt 1 view .LVU1599 + 4836 .loc 1 3870 12 is_stmt 0 view .LVU1600 + 4837 0002 B0F85C30 ldrh r3, [r0, #92] + 4838 .LVL421: +3871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint16_t uhdata; + 4839 .loc 1 3871 3 is_stmt 1 view .LVU1601 +3872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that a Rx process is ongoing */ +3874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 4840 .loc 1 3874 3 view .LVU1602 + 4841 .loc 1 3874 12 is_stmt 0 view .LVU1603 + 4842 0006 D0F88020 ldr r2, [r0, #128] + 4843 .loc 1 3874 6 view .LVU1604 + 4844 000a 222A cmp r2, #34 + 4845 000c 05D0 beq .L202 +3875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uhdata = (uint16_t) READ_REG(huart->Instance->RDR); +3877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); +3878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pRxBuffPtr++; +3879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount--; +3880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->RxXferCount == 0U) +3882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the UART Parity Error Interrupt and RXNE interrupts */ +3884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +3885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ +3887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +3888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Rx process is completed, restore huart->RxState to Ready */ +3890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +3891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear RxISR function pointer */ +3893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxISR = NULL; +3894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Initialize type of RxEvent to Transfer Complete */ +3896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; +3897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that USART RTOEN bit is set */ +3899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) +3900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the UART Receiver Timeout Interrupt */ +3902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); +3903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check current reception Mode : +3906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** If Reception till IDLE event has been selected : */ + ARM GAS /tmp/ccQxTlMj.s page 198 + + +3907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) +3908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set reception type to Standard */ +3910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +3911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable IDLE interrupt */ +3913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); +3914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) +3916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear IDLE Flag */ +3918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); +3919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call registered Rx Event callback*/ +3923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventCallback(huart, huart->RxXferSize); +3924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +3925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call legacy weak Rx Event callback*/ +3926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +3927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ +3928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +3930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Standard reception API called */ +3932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +3933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call registered Rx complete callback*/ +3934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxCpltCallback(huart); +3935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +3936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call legacy weak Rx complete callback*/ +3937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_RxCpltCallback(huart); +3938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +3939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +3943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear RXNE interrupt flag */ +3945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 4846 .loc 1 3945 5 is_stmt 1 view .LVU1605 + 4847 000e 0268 ldr r2, [r0] + 4848 0010 9369 ldr r3, [r2, #24] + 4849 .LVL422: + 4850 .loc 1 3945 5 is_stmt 0 view .LVU1606 + 4851 0012 43F00803 orr r3, r3, #8 + 4852 0016 9361 str r3, [r2, #24] + 4853 .LVL423: + 4854 .L191: +3946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 4855 .loc 1 3947 1 view .LVU1607 + 4856 0018 08BD pop {r3, pc} + 4857 .LVL424: + 4858 .L202: +3876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + 4859 .loc 1 3876 5 is_stmt 1 view .LVU1608 +3876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + ARM GAS /tmp/ccQxTlMj.s page 199 + + + 4860 .loc 1 3876 25 is_stmt 0 view .LVU1609 + 4861 001a 0268 ldr r2, [r0] + 4862 001c 516A ldr r1, [r2, #36] + 4863 .LVL425: +3877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pRxBuffPtr++; + 4864 .loc 1 3877 5 is_stmt 1 view .LVU1610 +3877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pRxBuffPtr++; + 4865 .loc 1 3877 45 is_stmt 0 view .LVU1611 + 4866 001e DBB2 uxtb r3, r3 + 4867 .LVL426: +3877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pRxBuffPtr++; + 4868 .loc 1 3877 11 view .LVU1612 + 4869 0020 426D ldr r2, [r0, #84] +3877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pRxBuffPtr++; + 4870 .loc 1 3877 26 view .LVU1613 + 4871 0022 0B40 ands r3, r3, r1 +3877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pRxBuffPtr++; + 4872 .loc 1 3877 24 view .LVU1614 + 4873 0024 1370 strb r3, [r2] + 4874 .LVL427: +3878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount--; + 4875 .loc 1 3878 5 is_stmt 1 view .LVU1615 +3878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount--; + 4876 .loc 1 3878 10 is_stmt 0 view .LVU1616 + 4877 0026 436D ldr r3, [r0, #84] +3878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount--; + 4878 .loc 1 3878 22 view .LVU1617 + 4879 0028 0133 adds r3, r3, #1 + 4880 002a 4365 str r3, [r0, #84] +3879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4881 .loc 1 3879 5 is_stmt 1 view .LVU1618 +3879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4882 .loc 1 3879 10 is_stmt 0 view .LVU1619 + 4883 002c B0F85A30 ldrh r3, [r0, #90] + 4884 0030 9BB2 uxth r3, r3 +3879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4885 .loc 1 3879 23 view .LVU1620 + 4886 0032 013B subs r3, r3, #1 + 4887 0034 9BB2 uxth r3, r3 + 4888 0036 A0F85A30 strh r3, [r0, #90] @ movhi +3881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4889 .loc 1 3881 5 is_stmt 1 view .LVU1621 +3881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4890 .loc 1 3881 14 is_stmt 0 view .LVU1622 + 4891 003a B0F85A30 ldrh r3, [r0, #90] + 4892 003e 9BB2 uxth r3, r3 +3881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 4893 .loc 1 3881 8 view .LVU1623 + 4894 0040 002B cmp r3, #0 + 4895 0042 E9D1 bne .L191 + 4896 .LVL428: + 4897 .L194: +3884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4898 .loc 1 3884 7 is_stmt 1 discriminator 1 view .LVU1624 + 4899 .LBB640: +3884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4900 .loc 1 3884 7 discriminator 1 view .LVU1625 + ARM GAS /tmp/ccQxTlMj.s page 200 + + +3884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4901 .loc 1 3884 7 discriminator 1 view .LVU1626 +3884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4902 .loc 1 3884 7 discriminator 1 view .LVU1627 + 4903 0044 0268 ldr r2, [r0] + 4904 .LVL429: + 4905 .LBB641: + 4906 .LBI641: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 4907 .loc 2 1068 31 view .LVU1628 + 4908 .LBB642: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 4909 .loc 2 1070 5 view .LVU1629 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4910 .loc 2 1072 4 view .LVU1630 + 4911 .syntax unified + 4912 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 4913 0046 52E8003F ldrex r3, [r2] + 4914 @ 0 "" 2 + 4915 .LVL430: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 4916 .loc 2 1073 4 view .LVU1631 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 4917 .loc 2 1073 4 is_stmt 0 view .LVU1632 + 4918 .thumb + 4919 .syntax unified + 4920 .LBE642: + 4921 .LBE641: +3884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4922 .loc 1 3884 7 discriminator 1 view .LVU1633 + 4923 004a 23F49073 bic r3, r3, #288 + 4924 .LVL431: +3884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4925 .loc 1 3884 7 is_stmt 1 discriminator 1 view .LVU1634 + 4926 .LBB643: + 4927 .LBI643: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 4928 .loc 2 1119 31 view .LVU1635 + 4929 .LBB644: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 4930 .loc 2 1121 4 view .LVU1636 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4931 .loc 2 1123 4 view .LVU1637 + 4932 .syntax unified + 4933 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 4934 004e 42E80031 strex r1, r3, [r2] + 4935 @ 0 "" 2 + 4936 .LVL432: + 4937 .loc 2 1124 4 view .LVU1638 + 4938 .loc 2 1124 4 is_stmt 0 view .LVU1639 + 4939 .thumb + 4940 .syntax unified + 4941 .LBE644: + 4942 .LBE643: +3884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4943 .loc 1 3884 7 discriminator 1 view .LVU1640 + 4944 0052 0029 cmp r1, #0 + ARM GAS /tmp/ccQxTlMj.s page 201 + + + 4945 0054 F6D1 bne .L194 + 4946 .LVL433: + 4947 .L195: +3884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4948 .loc 1 3884 7 discriminator 1 view .LVU1641 + 4949 .LBE640: +3884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4950 .loc 1 3884 7 is_stmt 1 discriminator 2 view .LVU1642 +3887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4951 .loc 1 3887 7 discriminator 1 view .LVU1643 + 4952 .LBB645: +3887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4953 .loc 1 3887 7 discriminator 1 view .LVU1644 +3887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4954 .loc 1 3887 7 discriminator 1 view .LVU1645 +3887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4955 .loc 1 3887 7 discriminator 1 view .LVU1646 + 4956 0056 0268 ldr r2, [r0] + 4957 .LVL434: + 4958 .LBB646: + 4959 .LBI646: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 4960 .loc 2 1068 31 view .LVU1647 + 4961 .LBB647: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 4962 .loc 2 1070 5 view .LVU1648 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4963 .loc 2 1072 4 view .LVU1649 + 4964 0058 02F10803 add r3, r2, #8 + 4965 .LVL435: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4966 .loc 2 1072 4 is_stmt 0 view .LVU1650 + 4967 .syntax unified + 4968 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 4969 005c 53E8003F ldrex r3, [r3] + 4970 @ 0 "" 2 + 4971 .LVL436: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 4972 .loc 2 1073 4 is_stmt 1 view .LVU1651 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 4973 .loc 2 1073 4 is_stmt 0 view .LVU1652 + 4974 .thumb + 4975 .syntax unified + 4976 .LBE647: + 4977 .LBE646: +3887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4978 .loc 1 3887 7 discriminator 1 view .LVU1653 + 4979 0060 23F00103 bic r3, r3, #1 + 4980 .LVL437: +3887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 4981 .loc 1 3887 7 is_stmt 1 discriminator 1 view .LVU1654 + 4982 .LBB648: + 4983 .LBI648: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 4984 .loc 2 1119 31 view .LVU1655 + 4985 .LBB649: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccQxTlMj.s page 202 + + + 4986 .loc 2 1121 4 view .LVU1656 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4987 .loc 2 1123 4 view .LVU1657 + 4988 0064 0832 adds r2, r2, #8 + 4989 .LVL438: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 4990 .loc 2 1123 4 is_stmt 0 view .LVU1658 + 4991 .syntax unified + 4992 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 4993 0066 42E80031 strex r1, r3, [r2] + 4994 @ 0 "" 2 + 4995 .LVL439: + 4996 .loc 2 1124 4 is_stmt 1 view .LVU1659 + 4997 .loc 2 1124 4 is_stmt 0 view .LVU1660 + 4998 .thumb + 4999 .syntax unified + 5000 .LBE649: + 5001 .LBE648: +3887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5002 .loc 1 3887 7 discriminator 1 view .LVU1661 + 5003 006a 0029 cmp r1, #0 + 5004 006c F3D1 bne .L195 + 5005 .LBE645: +3887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5006 .loc 1 3887 7 is_stmt 1 discriminator 2 view .LVU1662 +3890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5007 .loc 1 3890 7 view .LVU1663 +3890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5008 .loc 1 3890 22 is_stmt 0 view .LVU1664 + 5009 006e 2023 movs r3, #32 + 5010 .LVL440: +3890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5011 .loc 1 3890 22 view .LVU1665 + 5012 0070 C0F88030 str r3, [r0, #128] +3893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5013 .loc 1 3893 7 is_stmt 1 view .LVU1666 +3893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5014 .loc 1 3893 20 is_stmt 0 view .LVU1667 + 5015 0074 0023 movs r3, #0 + 5016 0076 8366 str r3, [r0, #104] +3896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5017 .loc 1 3896 7 is_stmt 1 view .LVU1668 +3896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5018 .loc 1 3896 26 is_stmt 0 view .LVU1669 + 5019 0078 4366 str r3, [r0, #100] +3899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5020 .loc 1 3899 7 is_stmt 1 view .LVU1670 +3899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5021 .loc 1 3899 11 is_stmt 0 view .LVU1671 + 5022 007a 0368 ldr r3, [r0] + 5023 007c 5B68 ldr r3, [r3, #4] +3899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5024 .loc 1 3899 10 view .LVU1672 + 5025 007e 13F4000F tst r3, #8388608 + 5026 0082 08D0 beq .L196 + 5027 .L197: +3902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + ARM GAS /tmp/ccQxTlMj.s page 203 + + + 5028 .loc 1 3902 9 is_stmt 1 discriminator 1 view .LVU1673 + 5029 .LBB650: +3902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5030 .loc 1 3902 9 discriminator 1 view .LVU1674 +3902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5031 .loc 1 3902 9 discriminator 1 view .LVU1675 +3902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5032 .loc 1 3902 9 discriminator 1 view .LVU1676 + 5033 0084 0268 ldr r2, [r0] + 5034 .LVL441: + 5035 .LBB651: + 5036 .LBI651: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5037 .loc 2 1068 31 view .LVU1677 + 5038 .LBB652: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5039 .loc 2 1070 5 view .LVU1678 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5040 .loc 2 1072 4 view .LVU1679 + 5041 .syntax unified + 5042 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 5043 0086 52E8003F ldrex r3, [r2] + 5044 @ 0 "" 2 + 5045 .LVL442: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5046 .loc 2 1073 4 view .LVU1680 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5047 .loc 2 1073 4 is_stmt 0 view .LVU1681 + 5048 .thumb + 5049 .syntax unified + 5050 .LBE652: + 5051 .LBE651: +3902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5052 .loc 1 3902 9 discriminator 1 view .LVU1682 + 5053 008a 23F08063 bic r3, r3, #67108864 + 5054 .LVL443: +3902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5055 .loc 1 3902 9 is_stmt 1 discriminator 1 view .LVU1683 + 5056 .LBB653: + 5057 .LBI653: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5058 .loc 2 1119 31 view .LVU1684 + 5059 .LBB654: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5060 .loc 2 1121 4 view .LVU1685 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5061 .loc 2 1123 4 view .LVU1686 + 5062 .syntax unified + 5063 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 5064 008e 42E80031 strex r1, r3, [r2] + 5065 @ 0 "" 2 + 5066 .LVL444: + 5067 .loc 2 1124 4 view .LVU1687 + 5068 .loc 2 1124 4 is_stmt 0 view .LVU1688 + 5069 .thumb + 5070 .syntax unified + 5071 .LBE654: + ARM GAS /tmp/ccQxTlMj.s page 204 + + + 5072 .LBE653: +3902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5073 .loc 1 3902 9 discriminator 1 view .LVU1689 + 5074 0092 0029 cmp r1, #0 + 5075 0094 F6D1 bne .L197 + 5076 .LVL445: + 5077 .L196: +3902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5078 .loc 1 3902 9 discriminator 1 view .LVU1690 + 5079 .LBE650: +3902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5080 .loc 1 3902 9 is_stmt 1 discriminator 2 view .LVU1691 +3907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5081 .loc 1 3907 7 view .LVU1692 +3907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5082 .loc 1 3907 16 is_stmt 0 view .LVU1693 + 5083 0096 036E ldr r3, [r0, #96] +3907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5084 .loc 1 3907 10 view .LVU1694 + 5085 0098 012B cmp r3, #1 + 5086 009a 16D1 bne .L198 +3910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5087 .loc 1 3910 9 is_stmt 1 view .LVU1695 +3910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5088 .loc 1 3910 30 is_stmt 0 view .LVU1696 + 5089 009c 0023 movs r3, #0 + 5090 009e 0366 str r3, [r0, #96] + 5091 .L199: +3913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5092 .loc 1 3913 9 is_stmt 1 discriminator 1 view .LVU1697 + 5093 .LBB655: +3913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5094 .loc 1 3913 9 discriminator 1 view .LVU1698 +3913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5095 .loc 1 3913 9 discriminator 1 view .LVU1699 +3913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5096 .loc 1 3913 9 discriminator 1 view .LVU1700 + 5097 00a0 0268 ldr r2, [r0] + 5098 .LVL446: + 5099 .LBB656: + 5100 .LBI656: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5101 .loc 2 1068 31 view .LVU1701 + 5102 .LBB657: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5103 .loc 2 1070 5 view .LVU1702 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5104 .loc 2 1072 4 view .LVU1703 + 5105 .syntax unified + 5106 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 5107 00a2 52E8003F ldrex r3, [r2] + 5108 @ 0 "" 2 + 5109 .LVL447: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5110 .loc 2 1073 4 view .LVU1704 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5111 .loc 2 1073 4 is_stmt 0 view .LVU1705 + ARM GAS /tmp/ccQxTlMj.s page 205 + + + 5112 .thumb + 5113 .syntax unified + 5114 .LBE657: + 5115 .LBE656: +3913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5116 .loc 1 3913 9 discriminator 1 view .LVU1706 + 5117 00a6 23F01003 bic r3, r3, #16 + 5118 .LVL448: +3913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5119 .loc 1 3913 9 is_stmt 1 discriminator 1 view .LVU1707 + 5120 .LBB658: + 5121 .LBI658: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5122 .loc 2 1119 31 view .LVU1708 + 5123 .LBB659: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5124 .loc 2 1121 4 view .LVU1709 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5125 .loc 2 1123 4 view .LVU1710 + 5126 .syntax unified + 5127 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 5128 00aa 42E80031 strex r1, r3, [r2] + 5129 @ 0 "" 2 + 5130 .LVL449: + 5131 .loc 2 1124 4 view .LVU1711 + 5132 .loc 2 1124 4 is_stmt 0 view .LVU1712 + 5133 .thumb + 5134 .syntax unified + 5135 .LBE659: + 5136 .LBE658: +3913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5137 .loc 1 3913 9 discriminator 1 view .LVU1713 + 5138 00ae 0029 cmp r1, #0 + 5139 00b0 F6D1 bne .L199 + 5140 .LBE655: +3913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5141 .loc 1 3913 9 is_stmt 1 discriminator 2 view .LVU1714 +3915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5142 .loc 1 3915 9 view .LVU1715 +3915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5143 .loc 1 3915 13 is_stmt 0 view .LVU1716 + 5144 00b2 0368 ldr r3, [r0] + 5145 .LVL450: +3915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5146 .loc 1 3915 13 view .LVU1717 + 5147 00b4 DA69 ldr r2, [r3, #28] +3915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5148 .loc 1 3915 12 view .LVU1718 + 5149 00b6 12F0100F tst r2, #16 + 5150 00ba 01D0 beq .L200 +3918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5151 .loc 1 3918 11 is_stmt 1 view .LVU1719 + 5152 00bc 1022 movs r2, #16 + 5153 00be 1A62 str r2, [r3, #32] + 5154 .L200: +3926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 5155 .loc 1 3926 9 view .LVU1720 + ARM GAS /tmp/ccQxTlMj.s page 206 + + + 5156 00c0 B0F85810 ldrh r1, [r0, #88] + 5157 00c4 FFF7FEFF bl HAL_UARTEx_RxEventCallback + 5158 .LVL451: +3926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 5159 .loc 1 3926 9 is_stmt 0 view .LVU1721 + 5160 00c8 A6E7 b .L191 + 5161 .LVL452: + 5162 .L198: +3937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 5163 .loc 1 3937 9 is_stmt 1 view .LVU1722 + 5164 00ca FFF7FEFF bl HAL_UART_RxCpltCallback + 5165 .LVL453: +3937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 5166 .loc 1 3937 9 is_stmt 0 view .LVU1723 + 5167 00ce A3E7 b .L191 + 5168 .cfi_endproc + 5169 .LFE206: + 5171 .section .text.UART_RxISR_16BIT,"ax",%progbits + 5172 .align 1 + 5173 .syntax unified + 5174 .thumb + 5175 .thumb_func + 5177 UART_RxISR_16BIT: + 5178 .LVL454: + 5179 .LFB207: +3948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** +3950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @brief RX interrupt handler for 9 bits data word length . +3951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @note Function is called under interruption only, once +3952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * interruptions have been enabled by HAL_UART_Receive_IT() +3953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @param huart UART handle. +3954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** * @retval None +3955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** */ +3956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +3957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5180 .loc 1 3957 1 is_stmt 1 view -0 + 5181 .cfi_startproc + 5182 @ args = 0, pretend = 0, frame = 0 + 5183 @ frame_needed = 0, uses_anonymous_args = 0 + 5184 .loc 1 3957 1 is_stmt 0 view .LVU1725 + 5185 0000 08B5 push {r3, lr} + 5186 .LCFI25: + 5187 .cfi_def_cfa_offset 8 + 5188 .cfi_offset 3, -8 + 5189 .cfi_offset 14, -4 +3958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint16_t *tmp; + 5190 .loc 1 3958 3 is_stmt 1 view .LVU1726 +3959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint16_t uhMask = huart->Mask; + 5191 .loc 1 3959 3 view .LVU1727 + 5192 .loc 1 3959 12 is_stmt 0 view .LVU1728 + 5193 0002 B0F85C20 ldrh r2, [r0, #92] + 5194 .LVL455: +3960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint16_t uhdata; + 5195 .loc 1 3960 3 is_stmt 1 view .LVU1729 +3961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that a Rx process is ongoing */ +3963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->RxState == HAL_UART_STATE_BUSY_RX) + ARM GAS /tmp/ccQxTlMj.s page 207 + + + 5196 .loc 1 3963 3 view .LVU1730 + 5197 .loc 1 3963 12 is_stmt 0 view .LVU1731 + 5198 0006 D0F88030 ldr r3, [r0, #128] + 5199 .loc 1 3963 6 view .LVU1732 + 5200 000a 222B cmp r3, #34 + 5201 000c 05D0 beq .L214 +3964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uhdata = (uint16_t) READ_REG(huart->Instance->RDR); +3966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** tmp = (uint16_t *) huart->pRxBuffPtr ; +3967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** *tmp = (uint16_t)(uhdata & uhMask); +3968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pRxBuffPtr += 2U; +3969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount--; +3970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->RxXferCount == 0U) +3972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ +3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); +3975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ +3977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); +3978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Rx process is completed, restore huart->RxState to Ready */ +3980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; +3981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear RxISR function pointer */ +3983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxISR = NULL; +3984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Initialize type of RxEvent to Transfer Complete */ +3986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; +3987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that USART RTOEN bit is set */ +3989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) +3990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Enable the UART Receiver Timeout Interrupt */ +3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); +3993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +3994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +3995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check current reception Mode : +3996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** If Reception till IDLE event has been selected : */ +3997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) +3998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +3999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Set reception type to Standard */ +4000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +4001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +4002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Disable IDLE interrupt */ +4003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); +4004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +4005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) +4006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +4007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear IDLE Flag */ +4008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); +4009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +4010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** +4011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +4012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call registered Rx Event callback*/ +4013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventCallback(huart, huart->RxXferSize); +4014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else + ARM GAS /tmp/ccQxTlMj.s page 208 + + +4015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call legacy weak Rx Event callback*/ +4016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +4017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ +4018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +4019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +4020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +4021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Standard reception API called */ +4022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +4023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call registered Rx complete callback*/ +4024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxCpltCallback(huart); +4025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #else +4026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /*Call legacy weak Rx complete callback*/ +4027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_UART_RxCpltCallback(huart); +4028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +4029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +4030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +4031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +4032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** else +4033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { +4034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Clear RXNE interrupt flag */ +4035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 5202 .loc 1 4035 5 is_stmt 1 view .LVU1733 + 5203 000e 0268 ldr r2, [r0] + 5204 .LVL456: + 5205 .loc 1 4035 5 is_stmt 0 view .LVU1734 + 5206 0010 9369 ldr r3, [r2, #24] + 5207 0012 43F00803 orr r3, r3, #8 + 5208 0016 9361 str r3, [r2, #24] + 5209 .LVL457: + 5210 .L203: +4036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } +4037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5211 .loc 1 4037 1 view .LVU1735 + 5212 0018 08BD pop {r3, pc} + 5213 .LVL458: + 5214 .L214: +3965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** tmp = (uint16_t *) huart->pRxBuffPtr ; + 5215 .loc 1 3965 5 is_stmt 1 view .LVU1736 +3965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** tmp = (uint16_t *) huart->pRxBuffPtr ; + 5216 .loc 1 3965 25 is_stmt 0 view .LVU1737 + 5217 001a 0368 ldr r3, [r0] + 5218 001c 5B6A ldr r3, [r3, #36] + 5219 .LVL459: +3966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** *tmp = (uint16_t)(uhdata & uhMask); + 5220 .loc 1 3966 5 is_stmt 1 view .LVU1738 +3966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** *tmp = (uint16_t)(uhdata & uhMask); + 5221 .loc 1 3966 9 is_stmt 0 view .LVU1739 + 5222 001e 416D ldr r1, [r0, #84] + 5223 .LVL460: +3967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pRxBuffPtr += 2U; + 5224 .loc 1 3967 5 is_stmt 1 view .LVU1740 +3967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pRxBuffPtr += 2U; + 5225 .loc 1 3967 12 is_stmt 0 view .LVU1741 + 5226 0020 1340 ands r3, r3, r2 + 5227 .LVL461: +3967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pRxBuffPtr += 2U; + 5228 .loc 1 3967 10 view .LVU1742 + ARM GAS /tmp/ccQxTlMj.s page 209 + + + 5229 0022 0B80 strh r3, [r1] @ movhi +3968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount--; + 5230 .loc 1 3968 5 is_stmt 1 view .LVU1743 +3968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount--; + 5231 .loc 1 3968 10 is_stmt 0 view .LVU1744 + 5232 0024 436D ldr r3, [r0, #84] +3968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount--; + 5233 .loc 1 3968 23 view .LVU1745 + 5234 0026 0233 adds r3, r3, #2 + 5235 0028 4365 str r3, [r0, #84] +3969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5236 .loc 1 3969 5 is_stmt 1 view .LVU1746 +3969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5237 .loc 1 3969 10 is_stmt 0 view .LVU1747 + 5238 002a B0F85A30 ldrh r3, [r0, #90] + 5239 002e 9BB2 uxth r3, r3 +3969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5240 .loc 1 3969 23 view .LVU1748 + 5241 0030 013B subs r3, r3, #1 + 5242 0032 9BB2 uxth r3, r3 + 5243 0034 A0F85A30 strh r3, [r0, #90] @ movhi +3971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5244 .loc 1 3971 5 is_stmt 1 view .LVU1749 +3971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5245 .loc 1 3971 14 is_stmt 0 view .LVU1750 + 5246 0038 B0F85A30 ldrh r3, [r0, #90] + 5247 003c 9BB2 uxth r3, r3 +3971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5248 .loc 1 3971 8 view .LVU1751 + 5249 003e 002B cmp r3, #0 + 5250 0040 EAD1 bne .L203 + 5251 .LVL462: + 5252 .L206: +3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5253 .loc 1 3974 7 is_stmt 1 discriminator 1 view .LVU1752 + 5254 .LBB660: +3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5255 .loc 1 3974 7 discriminator 1 view .LVU1753 +3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5256 .loc 1 3974 7 discriminator 1 view .LVU1754 +3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5257 .loc 1 3974 7 discriminator 1 view .LVU1755 + 5258 0042 0268 ldr r2, [r0] + 5259 .LVL463: + 5260 .LBB661: + 5261 .LBI661: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5262 .loc 2 1068 31 view .LVU1756 + 5263 .LBB662: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5264 .loc 2 1070 5 view .LVU1757 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5265 .loc 2 1072 4 view .LVU1758 + 5266 .syntax unified + 5267 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 5268 0044 52E8003F ldrex r3, [r2] + 5269 @ 0 "" 2 + ARM GAS /tmp/ccQxTlMj.s page 210 + + + 5270 .LVL464: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5271 .loc 2 1073 4 view .LVU1759 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5272 .loc 2 1073 4 is_stmt 0 view .LVU1760 + 5273 .thumb + 5274 .syntax unified + 5275 .LBE662: + 5276 .LBE661: +3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5277 .loc 1 3974 7 discriminator 1 view .LVU1761 + 5278 0048 23F49073 bic r3, r3, #288 + 5279 .LVL465: +3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5280 .loc 1 3974 7 is_stmt 1 discriminator 1 view .LVU1762 + 5281 .LBB663: + 5282 .LBI663: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5283 .loc 2 1119 31 view .LVU1763 + 5284 .LBB664: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5285 .loc 2 1121 4 view .LVU1764 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5286 .loc 2 1123 4 view .LVU1765 + 5287 .syntax unified + 5288 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 5289 004c 42E80031 strex r1, r3, [r2] + 5290 @ 0 "" 2 + 5291 .LVL466: + 5292 .loc 2 1124 4 view .LVU1766 + 5293 .loc 2 1124 4 is_stmt 0 view .LVU1767 + 5294 .thumb + 5295 .syntax unified + 5296 .LBE664: + 5297 .LBE663: +3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5298 .loc 1 3974 7 discriminator 1 view .LVU1768 + 5299 0050 0029 cmp r1, #0 + 5300 0052 F6D1 bne .L206 + 5301 .LVL467: + 5302 .L207: +3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5303 .loc 1 3974 7 discriminator 1 view .LVU1769 + 5304 .LBE660: +3974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5305 .loc 1 3974 7 is_stmt 1 discriminator 2 view .LVU1770 +3977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5306 .loc 1 3977 7 discriminator 1 view .LVU1771 + 5307 .LBB665: +3977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5308 .loc 1 3977 7 discriminator 1 view .LVU1772 +3977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5309 .loc 1 3977 7 discriminator 1 view .LVU1773 +3977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5310 .loc 1 3977 7 discriminator 1 view .LVU1774 + 5311 0054 0268 ldr r2, [r0] + 5312 .LVL468: + ARM GAS /tmp/ccQxTlMj.s page 211 + + + 5313 .LBB666: + 5314 .LBI666: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5315 .loc 2 1068 31 view .LVU1775 + 5316 .LBB667: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5317 .loc 2 1070 5 view .LVU1776 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5318 .loc 2 1072 4 view .LVU1777 + 5319 0056 02F10803 add r3, r2, #8 + 5320 .LVL469: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5321 .loc 2 1072 4 is_stmt 0 view .LVU1778 + 5322 .syntax unified + 5323 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 5324 005a 53E8003F ldrex r3, [r3] + 5325 @ 0 "" 2 + 5326 .LVL470: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5327 .loc 2 1073 4 is_stmt 1 view .LVU1779 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5328 .loc 2 1073 4 is_stmt 0 view .LVU1780 + 5329 .thumb + 5330 .syntax unified + 5331 .LBE667: + 5332 .LBE666: +3977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5333 .loc 1 3977 7 discriminator 1 view .LVU1781 + 5334 005e 23F00103 bic r3, r3, #1 + 5335 .LVL471: +3977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5336 .loc 1 3977 7 is_stmt 1 discriminator 1 view .LVU1782 + 5337 .LBB668: + 5338 .LBI668: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5339 .loc 2 1119 31 view .LVU1783 + 5340 .LBB669: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5341 .loc 2 1121 4 view .LVU1784 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5342 .loc 2 1123 4 view .LVU1785 + 5343 0062 0832 adds r2, r2, #8 + 5344 .LVL472: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5345 .loc 2 1123 4 is_stmt 0 view .LVU1786 + 5346 .syntax unified + 5347 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 5348 0064 42E80031 strex r1, r3, [r2] + 5349 @ 0 "" 2 + 5350 .LVL473: + 5351 .loc 2 1124 4 is_stmt 1 view .LVU1787 + 5352 .loc 2 1124 4 is_stmt 0 view .LVU1788 + 5353 .thumb + 5354 .syntax unified + 5355 .LBE669: + 5356 .LBE668: +3977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 212 + + + 5357 .loc 1 3977 7 discriminator 1 view .LVU1789 + 5358 0068 0029 cmp r1, #0 + 5359 006a F3D1 bne .L207 + 5360 .LBE665: +3977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5361 .loc 1 3977 7 is_stmt 1 discriminator 2 view .LVU1790 +3980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5362 .loc 1 3980 7 view .LVU1791 +3980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5363 .loc 1 3980 22 is_stmt 0 view .LVU1792 + 5364 006c 2023 movs r3, #32 + 5365 .LVL474: +3980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5366 .loc 1 3980 22 view .LVU1793 + 5367 006e C0F88030 str r3, [r0, #128] +3983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5368 .loc 1 3983 7 is_stmt 1 view .LVU1794 +3983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5369 .loc 1 3983 20 is_stmt 0 view .LVU1795 + 5370 0072 0023 movs r3, #0 + 5371 0074 8366 str r3, [r0, #104] +3986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5372 .loc 1 3986 7 is_stmt 1 view .LVU1796 +3986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5373 .loc 1 3986 26 is_stmt 0 view .LVU1797 + 5374 0076 4366 str r3, [r0, #100] +3989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5375 .loc 1 3989 7 is_stmt 1 view .LVU1798 +3989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5376 .loc 1 3989 11 is_stmt 0 view .LVU1799 + 5377 0078 0368 ldr r3, [r0] + 5378 007a 5B68 ldr r3, [r3, #4] +3989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5379 .loc 1 3989 10 view .LVU1800 + 5380 007c 13F4000F tst r3, #8388608 + 5381 0080 08D0 beq .L208 + 5382 .L209: +3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5383 .loc 1 3992 9 is_stmt 1 discriminator 1 view .LVU1801 + 5384 .LBB670: +3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5385 .loc 1 3992 9 discriminator 1 view .LVU1802 +3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5386 .loc 1 3992 9 discriminator 1 view .LVU1803 +3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5387 .loc 1 3992 9 discriminator 1 view .LVU1804 + 5388 0082 0268 ldr r2, [r0] + 5389 .LVL475: + 5390 .LBB671: + 5391 .LBI671: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5392 .loc 2 1068 31 view .LVU1805 + 5393 .LBB672: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5394 .loc 2 1070 5 view .LVU1806 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5395 .loc 2 1072 4 view .LVU1807 + ARM GAS /tmp/ccQxTlMj.s page 213 + + + 5396 .syntax unified + 5397 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 5398 0084 52E8003F ldrex r3, [r2] + 5399 @ 0 "" 2 + 5400 .LVL476: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5401 .loc 2 1073 4 view .LVU1808 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5402 .loc 2 1073 4 is_stmt 0 view .LVU1809 + 5403 .thumb + 5404 .syntax unified + 5405 .LBE672: + 5406 .LBE671: +3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5407 .loc 1 3992 9 discriminator 1 view .LVU1810 + 5408 0088 23F08063 bic r3, r3, #67108864 + 5409 .LVL477: +3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5410 .loc 1 3992 9 is_stmt 1 discriminator 1 view .LVU1811 + 5411 .LBB673: + 5412 .LBI673: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5413 .loc 2 1119 31 view .LVU1812 + 5414 .LBB674: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5415 .loc 2 1121 4 view .LVU1813 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5416 .loc 2 1123 4 view .LVU1814 + 5417 .syntax unified + 5418 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 5419 008c 42E80031 strex r1, r3, [r2] + 5420 @ 0 "" 2 + 5421 .LVL478: + 5422 .loc 2 1124 4 view .LVU1815 + 5423 .loc 2 1124 4 is_stmt 0 view .LVU1816 + 5424 .thumb + 5425 .syntax unified + 5426 .LBE674: + 5427 .LBE673: +3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5428 .loc 1 3992 9 discriminator 1 view .LVU1817 + 5429 0090 0029 cmp r1, #0 + 5430 0092 F6D1 bne .L209 + 5431 .LVL479: + 5432 .L208: +3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5433 .loc 1 3992 9 discriminator 1 view .LVU1818 + 5434 .LBE670: +3992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5435 .loc 1 3992 9 is_stmt 1 discriminator 2 view .LVU1819 +3997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5436 .loc 1 3997 7 view .LVU1820 +3997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5437 .loc 1 3997 16 is_stmt 0 view .LVU1821 + 5438 0094 036E ldr r3, [r0, #96] +3997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5439 .loc 1 3997 10 view .LVU1822 + ARM GAS /tmp/ccQxTlMj.s page 214 + + + 5440 0096 012B cmp r3, #1 + 5441 0098 16D1 bne .L210 +4000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5442 .loc 1 4000 9 is_stmt 1 view .LVU1823 +4000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5443 .loc 1 4000 30 is_stmt 0 view .LVU1824 + 5444 009a 0023 movs r3, #0 + 5445 009c 0366 str r3, [r0, #96] + 5446 .L211: +4003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5447 .loc 1 4003 9 is_stmt 1 discriminator 1 view .LVU1825 + 5448 .LBB675: +4003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5449 .loc 1 4003 9 discriminator 1 view .LVU1826 +4003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5450 .loc 1 4003 9 discriminator 1 view .LVU1827 +4003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5451 .loc 1 4003 9 discriminator 1 view .LVU1828 + 5452 009e 0268 ldr r2, [r0] + 5453 .LVL480: + 5454 .LBB676: + 5455 .LBI676: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5456 .loc 2 1068 31 view .LVU1829 + 5457 .LBB677: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5458 .loc 2 1070 5 view .LVU1830 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5459 .loc 2 1072 4 view .LVU1831 + 5460 .syntax unified + 5461 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 5462 00a0 52E8003F ldrex r3, [r2] + 5463 @ 0 "" 2 + 5464 .LVL481: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5465 .loc 2 1073 4 view .LVU1832 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5466 .loc 2 1073 4 is_stmt 0 view .LVU1833 + 5467 .thumb + 5468 .syntax unified + 5469 .LBE677: + 5470 .LBE676: +4003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5471 .loc 1 4003 9 discriminator 1 view .LVU1834 + 5472 00a4 23F01003 bic r3, r3, #16 + 5473 .LVL482: +4003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5474 .loc 1 4003 9 is_stmt 1 discriminator 1 view .LVU1835 + 5475 .LBB678: + 5476 .LBI678: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5477 .loc 2 1119 31 view .LVU1836 + 5478 .LBB679: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5479 .loc 2 1121 4 view .LVU1837 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5480 .loc 2 1123 4 view .LVU1838 + ARM GAS /tmp/ccQxTlMj.s page 215 + + + 5481 .syntax unified + 5482 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 5483 00a8 42E80031 strex r1, r3, [r2] + 5484 @ 0 "" 2 + 5485 .LVL483: + 5486 .loc 2 1124 4 view .LVU1839 + 5487 .loc 2 1124 4 is_stmt 0 view .LVU1840 + 5488 .thumb + 5489 .syntax unified + 5490 .LBE679: + 5491 .LBE678: +4003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5492 .loc 1 4003 9 discriminator 1 view .LVU1841 + 5493 00ac 0029 cmp r1, #0 + 5494 00ae F6D1 bne .L211 + 5495 .LBE675: +4003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5496 .loc 1 4003 9 is_stmt 1 discriminator 2 view .LVU1842 +4005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5497 .loc 1 4005 9 view .LVU1843 +4005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5498 .loc 1 4005 13 is_stmt 0 view .LVU1844 + 5499 00b0 0368 ldr r3, [r0] + 5500 .LVL484: +4005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5501 .loc 1 4005 13 view .LVU1845 + 5502 00b2 DA69 ldr r2, [r3, #28] +4005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5503 .loc 1 4005 12 view .LVU1846 + 5504 00b4 12F0100F tst r2, #16 + 5505 00b8 01D0 beq .L212 +4008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5506 .loc 1 4008 11 is_stmt 1 view .LVU1847 + 5507 00ba 1022 movs r2, #16 + 5508 00bc 1A62 str r2, [r3, #32] + 5509 .L212: +4016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 5510 .loc 1 4016 9 view .LVU1848 + 5511 00be B0F85810 ldrh r1, [r0, #88] + 5512 00c2 FFF7FEFF bl HAL_UARTEx_RxEventCallback + 5513 .LVL485: +4016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 5514 .loc 1 4016 9 is_stmt 0 view .LVU1849 + 5515 00c6 A7E7 b .L203 + 5516 .LVL486: + 5517 .L210: +4027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 5518 .loc 1 4027 9 is_stmt 1 view .LVU1850 + 5519 00c8 FFF7FEFF bl HAL_UART_RxCpltCallback + 5520 .LVL487: +4027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 5521 .loc 1 4027 9 is_stmt 0 view .LVU1851 + 5522 00cc A4E7 b .L203 + 5523 .cfi_endproc + 5524 .LFE207: + 5526 .section .text.UART_DMARxHalfCplt,"ax",%progbits + 5527 .align 1 + ARM GAS /tmp/ccQxTlMj.s page 216 + + + 5528 .syntax unified + 5529 .thumb + 5530 .thumb_func + 5532 UART_DMARxHalfCplt: + 5533 .LVL488: + 5534 .LFB196: +3519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 5535 .loc 1 3519 1 is_stmt 1 view -0 + 5536 .cfi_startproc + 5537 @ args = 0, pretend = 0, frame = 0 + 5538 @ frame_needed = 0, uses_anonymous_args = 0 +3519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 5539 .loc 1 3519 1 is_stmt 0 view .LVU1853 + 5540 0000 08B5 push {r3, lr} + 5541 .LCFI26: + 5542 .cfi_def_cfa_offset 8 + 5543 .cfi_offset 3, -8 + 5544 .cfi_offset 14, -4 +3520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5545 .loc 1 3520 3 is_stmt 1 view .LVU1854 +3520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5546 .loc 1 3520 23 is_stmt 0 view .LVU1855 + 5547 0002 806B ldr r0, [r0, #56] + 5548 .LVL489: +3524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5549 .loc 1 3524 3 is_stmt 1 view .LVU1856 +3524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5550 .loc 1 3524 22 is_stmt 0 view .LVU1857 + 5551 0004 0123 movs r3, #1 + 5552 0006 4366 str r3, [r0, #100] +3528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5553 .loc 1 3528 3 is_stmt 1 view .LVU1858 +3528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5554 .loc 1 3528 12 is_stmt 0 view .LVU1859 + 5555 0008 036E ldr r3, [r0, #96] +3528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5556 .loc 1 3528 6 view .LVU1860 + 5557 000a 012B cmp r3, #1 + 5558 000c 02D0 beq .L219 +3546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 5559 .loc 1 3546 5 is_stmt 1 view .LVU1861 + 5560 000e FFF7FEFF bl HAL_UART_RxHalfCpltCallback + 5561 .LVL490: + 5562 .L215: +3549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5563 .loc 1 3549 1 is_stmt 0 view .LVU1862 + 5564 0012 08BD pop {r3, pc} + 5565 .LVL491: + 5566 .L219: +3535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 5567 .loc 1 3535 5 is_stmt 1 view .LVU1863 +3535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 5568 .loc 1 3535 44 is_stmt 0 view .LVU1864 + 5569 0014 B0F85810 ldrh r1, [r0, #88] +3535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 5570 .loc 1 3535 5 view .LVU1865 + 5571 0018 4908 lsrs r1, r1, #1 + ARM GAS /tmp/ccQxTlMj.s page 217 + + + 5572 001a FFF7FEFF bl HAL_UARTEx_RxEventCallback + 5573 .LVL492: +3535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 5574 .loc 1 3535 5 view .LVU1866 + 5575 001e F8E7 b .L215 + 5576 .cfi_endproc + 5577 .LFE196: + 5579 .section .text.UART_DMAReceiveCplt,"ax",%progbits + 5580 .align 1 + 5581 .syntax unified + 5582 .thumb + 5583 .thumb_func + 5585 UART_DMAReceiveCplt: + 5586 .LVL493: + 5587 .LFB195: +3458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 5588 .loc 1 3458 1 is_stmt 1 view -0 + 5589 .cfi_startproc + 5590 @ args = 0, pretend = 0, frame = 0 + 5591 @ frame_needed = 0, uses_anonymous_args = 0 +3458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 5592 .loc 1 3458 1 is_stmt 0 view .LVU1868 + 5593 0000 08B5 push {r3, lr} + 5594 .LCFI27: + 5595 .cfi_def_cfa_offset 8 + 5596 .cfi_offset 3, -8 + 5597 .cfi_offset 14, -4 + 5598 0002 0346 mov r3, r0 +3459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5599 .loc 1 3459 3 is_stmt 1 view .LVU1869 +3459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5600 .loc 1 3459 23 is_stmt 0 view .LVU1870 + 5601 0004 806B ldr r0, [r0, #56] + 5602 .LVL494: +3462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5603 .loc 1 3462 3 is_stmt 1 view .LVU1871 +3462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5604 .loc 1 3462 17 is_stmt 0 view .LVU1872 + 5605 0006 DB69 ldr r3, [r3, #28] + 5606 .LVL495: +3462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5607 .loc 1 3462 6 view .LVU1873 + 5608 0008 B3F5807F cmp r3, #256 + 5609 000c 29D0 beq .L221 +3464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5610 .loc 1 3464 5 is_stmt 1 view .LVU1874 +3464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5611 .loc 1 3464 24 is_stmt 0 view .LVU1875 + 5612 000e 0023 movs r3, #0 + 5613 0010 A0F85A30 strh r3, [r0, #90] @ movhi + 5614 .L222: +3467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 5615 .loc 1 3467 5 is_stmt 1 discriminator 1 view .LVU1876 + 5616 .LBB680: +3467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 5617 .loc 1 3467 5 discriminator 1 view .LVU1877 +3467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ARM GAS /tmp/ccQxTlMj.s page 218 + + + 5618 .loc 1 3467 5 discriminator 1 view .LVU1878 +3467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 5619 .loc 1 3467 5 discriminator 1 view .LVU1879 + 5620 0014 0268 ldr r2, [r0] + 5621 .LVL496: + 5622 .LBB681: + 5623 .LBI681: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5624 .loc 2 1068 31 view .LVU1880 + 5625 .LBB682: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5626 .loc 2 1070 5 view .LVU1881 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5627 .loc 2 1072 4 view .LVU1882 + 5628 .syntax unified + 5629 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 5630 0016 52E8003F ldrex r3, [r2] + 5631 @ 0 "" 2 + 5632 .LVL497: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5633 .loc 2 1073 4 view .LVU1883 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5634 .loc 2 1073 4 is_stmt 0 view .LVU1884 + 5635 .thumb + 5636 .syntax unified + 5637 .LBE682: + 5638 .LBE681: +3467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 5639 .loc 1 3467 5 discriminator 1 view .LVU1885 + 5640 001a 23F48073 bic r3, r3, #256 + 5641 .LVL498: +3467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 5642 .loc 1 3467 5 is_stmt 1 discriminator 1 view .LVU1886 + 5643 .LBB683: + 5644 .LBI683: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5645 .loc 2 1119 31 view .LVU1887 + 5646 .LBB684: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5647 .loc 2 1121 4 view .LVU1888 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5648 .loc 2 1123 4 view .LVU1889 + 5649 .syntax unified + 5650 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 5651 001e 42E80031 strex r1, r3, [r2] + 5652 @ 0 "" 2 + 5653 .LVL499: + 5654 .loc 2 1124 4 view .LVU1890 + 5655 .loc 2 1124 4 is_stmt 0 view .LVU1891 + 5656 .thumb + 5657 .syntax unified + 5658 .LBE684: + 5659 .LBE683: +3467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 5660 .loc 1 3467 5 discriminator 1 view .LVU1892 + 5661 0022 0029 cmp r1, #0 + 5662 0024 F6D1 bne .L222 + ARM GAS /tmp/ccQxTlMj.s page 219 + + + 5663 .LVL500: + 5664 .L223: +3467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 5665 .loc 1 3467 5 discriminator 1 view .LVU1893 + 5666 .LBE680: +3467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 5667 .loc 1 3467 5 is_stmt 1 discriminator 2 view .LVU1894 +3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5668 .loc 1 3468 5 discriminator 1 view .LVU1895 + 5669 .LBB685: +3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5670 .loc 1 3468 5 discriminator 1 view .LVU1896 +3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5671 .loc 1 3468 5 discriminator 1 view .LVU1897 +3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5672 .loc 1 3468 5 discriminator 1 view .LVU1898 + 5673 0026 0268 ldr r2, [r0] + 5674 .LVL501: + 5675 .LBB686: + 5676 .LBI686: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5677 .loc 2 1068 31 view .LVU1899 + 5678 .LBB687: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5679 .loc 2 1070 5 view .LVU1900 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5680 .loc 2 1072 4 view .LVU1901 + 5681 0028 02F10803 add r3, r2, #8 + 5682 .LVL502: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5683 .loc 2 1072 4 is_stmt 0 view .LVU1902 + 5684 .syntax unified + 5685 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 5686 002c 53E8003F ldrex r3, [r3] + 5687 @ 0 "" 2 + 5688 .LVL503: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5689 .loc 2 1073 4 is_stmt 1 view .LVU1903 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5690 .loc 2 1073 4 is_stmt 0 view .LVU1904 + 5691 .thumb + 5692 .syntax unified + 5693 .LBE687: + 5694 .LBE686: +3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5695 .loc 1 3468 5 discriminator 1 view .LVU1905 + 5696 0030 23F00103 bic r3, r3, #1 + 5697 .LVL504: +3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5698 .loc 1 3468 5 is_stmt 1 discriminator 1 view .LVU1906 + 5699 .LBB688: + 5700 .LBI688: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5701 .loc 2 1119 31 view .LVU1907 + 5702 .LBB689: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5703 .loc 2 1121 4 view .LVU1908 + ARM GAS /tmp/ccQxTlMj.s page 220 + + +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5704 .loc 2 1123 4 view .LVU1909 + 5705 0034 0832 adds r2, r2, #8 + 5706 .LVL505: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5707 .loc 2 1123 4 is_stmt 0 view .LVU1910 + 5708 .syntax unified + 5709 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 5710 0036 42E80031 strex r1, r3, [r2] + 5711 @ 0 "" 2 + 5712 .LVL506: + 5713 .loc 2 1124 4 is_stmt 1 view .LVU1911 + 5714 .loc 2 1124 4 is_stmt 0 view .LVU1912 + 5715 .thumb + 5716 .syntax unified + 5717 .LBE689: + 5718 .LBE688: +3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5719 .loc 1 3468 5 discriminator 1 view .LVU1913 + 5720 003a 0029 cmp r1, #0 + 5721 003c F3D1 bne .L223 + 5722 .LVL507: + 5723 .L224: +3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5724 .loc 1 3468 5 discriminator 1 view .LVU1914 + 5725 .LBE685: +3468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5726 .loc 1 3468 5 is_stmt 1 discriminator 2 view .LVU1915 +3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5727 .loc 1 3472 5 discriminator 1 view .LVU1916 + 5728 .LBB690: +3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5729 .loc 1 3472 5 discriminator 1 view .LVU1917 +3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5730 .loc 1 3472 5 discriminator 1 view .LVU1918 +3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5731 .loc 1 3472 5 discriminator 1 view .LVU1919 + 5732 003e 0268 ldr r2, [r0] + 5733 .LVL508: + 5734 .LBB691: + 5735 .LBI691: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5736 .loc 2 1068 31 view .LVU1920 + 5737 .LBB692: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5738 .loc 2 1070 5 view .LVU1921 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5739 .loc 2 1072 4 view .LVU1922 + 5740 0040 02F10803 add r3, r2, #8 + 5741 .LVL509: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5742 .loc 2 1072 4 is_stmt 0 view .LVU1923 + 5743 .syntax unified + 5744 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 5745 0044 53E8003F ldrex r3, [r3] + 5746 @ 0 "" 2 + 5747 .LVL510: + ARM GAS /tmp/ccQxTlMj.s page 221 + + +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5748 .loc 2 1073 4 is_stmt 1 view .LVU1924 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5749 .loc 2 1073 4 is_stmt 0 view .LVU1925 + 5750 .thumb + 5751 .syntax unified + 5752 .LBE692: + 5753 .LBE691: +3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5754 .loc 1 3472 5 discriminator 1 view .LVU1926 + 5755 0048 23F04003 bic r3, r3, #64 + 5756 .LVL511: +3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5757 .loc 1 3472 5 is_stmt 1 discriminator 1 view .LVU1927 + 5758 .LBB693: + 5759 .LBI693: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5760 .loc 2 1119 31 view .LVU1928 + 5761 .LBB694: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5762 .loc 2 1121 4 view .LVU1929 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5763 .loc 2 1123 4 view .LVU1930 + 5764 004c 0832 adds r2, r2, #8 + 5765 .LVL512: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5766 .loc 2 1123 4 is_stmt 0 view .LVU1931 + 5767 .syntax unified + 5768 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 5769 004e 42E80031 strex r1, r3, [r2] + 5770 @ 0 "" 2 + 5771 .LVL513: + 5772 .loc 2 1124 4 is_stmt 1 view .LVU1932 + 5773 .loc 2 1124 4 is_stmt 0 view .LVU1933 + 5774 .thumb + 5775 .syntax unified + 5776 .LBE694: + 5777 .LBE693: +3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5778 .loc 1 3472 5 discriminator 1 view .LVU1934 + 5779 0052 0029 cmp r1, #0 + 5780 0054 F3D1 bne .L224 + 5781 .LBE690: +3472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5782 .loc 1 3472 5 is_stmt 1 discriminator 2 view .LVU1935 +3475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5783 .loc 1 3475 5 view .LVU1936 +3475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5784 .loc 1 3475 20 is_stmt 0 view .LVU1937 + 5785 0056 2023 movs r3, #32 + 5786 .LVL514: +3475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5787 .loc 1 3475 20 view .LVU1938 + 5788 0058 C0F88030 str r3, [r0, #128] +3478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5789 .loc 1 3478 5 is_stmt 1 view .LVU1939 +3478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + ARM GAS /tmp/ccQxTlMj.s page 222 + + + 5790 .loc 1 3478 14 is_stmt 0 view .LVU1940 + 5791 005c 036E ldr r3, [r0, #96] +3478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5792 .loc 1 3478 8 view .LVU1941 + 5793 005e 012B cmp r3, #1 + 5794 0060 07D0 beq .L225 + 5795 .LVL515: + 5796 .L221: +3480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5797 .loc 1 3480 7 is_stmt 1 discriminator 2 view .LVU1942 +3486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5798 .loc 1 3486 3 view .LVU1943 +3486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5799 .loc 1 3486 22 is_stmt 0 view .LVU1944 + 5800 0062 0023 movs r3, #0 + 5801 0064 4366 str r3, [r0, #100] +3490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5802 .loc 1 3490 3 is_stmt 1 view .LVU1945 +3490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5803 .loc 1 3490 12 is_stmt 0 view .LVU1946 + 5804 0066 036E ldr r3, [r0, #96] +3490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5805 .loc 1 3490 6 view .LVU1947 + 5806 0068 012B cmp r3, #1 + 5807 006a 0CD0 beq .L229 +3508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 5808 .loc 1 3508 5 is_stmt 1 view .LVU1948 + 5809 006c FFF7FEFF bl HAL_UART_RxCpltCallback + 5810 .LVL516: + 5811 .L220: +3511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5812 .loc 1 3511 1 is_stmt 0 view .LVU1949 + 5813 0070 08BD pop {r3, pc} + 5814 .LVL517: + 5815 .L225: +3480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5816 .loc 1 3480 7 is_stmt 1 discriminator 1 view .LVU1950 + 5817 .LBB695: +3480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5818 .loc 1 3480 7 discriminator 1 view .LVU1951 +3480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5819 .loc 1 3480 7 discriminator 1 view .LVU1952 +3480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5820 .loc 1 3480 7 discriminator 1 view .LVU1953 + 5821 0072 0268 ldr r2, [r0] + 5822 .LVL518: + 5823 .LBB696: + 5824 .LBI696: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5825 .loc 2 1068 31 view .LVU1954 + 5826 .LBB697: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5827 .loc 2 1070 5 view .LVU1955 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5828 .loc 2 1072 4 view .LVU1956 + 5829 .syntax unified + 5830 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + ARM GAS /tmp/ccQxTlMj.s page 223 + + + 5831 0074 52E8003F ldrex r3, [r2] + 5832 @ 0 "" 2 + 5833 .LVL519: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5834 .loc 2 1073 4 view .LVU1957 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 5835 .loc 2 1073 4 is_stmt 0 view .LVU1958 + 5836 .thumb + 5837 .syntax unified + 5838 .LBE697: + 5839 .LBE696: +3480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5840 .loc 1 3480 7 discriminator 1 view .LVU1959 + 5841 0078 23F01003 bic r3, r3, #16 + 5842 .LVL520: +3480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5843 .loc 1 3480 7 is_stmt 1 discriminator 1 view .LVU1960 + 5844 .LBB698: + 5845 .LBI698: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 5846 .loc 2 1119 31 view .LVU1961 + 5847 .LBB699: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 5848 .loc 2 1121 4 view .LVU1962 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 5849 .loc 2 1123 4 view .LVU1963 + 5850 .syntax unified + 5851 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 5852 007c 42E80031 strex r1, r3, [r2] + 5853 @ 0 "" 2 + 5854 .LVL521: + 5855 .loc 2 1124 4 view .LVU1964 + 5856 .loc 2 1124 4 is_stmt 0 view .LVU1965 + 5857 .thumb + 5858 .syntax unified + 5859 .LBE699: + 5860 .LBE698: +3480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5861 .loc 1 3480 7 discriminator 1 view .LVU1966 + 5862 0080 0029 cmp r1, #0 + 5863 0082 F6D1 bne .L225 + 5864 0084 EDE7 b .L221 + 5865 .LVL522: + 5866 .L229: +3480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5867 .loc 1 3480 7 discriminator 1 view .LVU1967 + 5868 .LBE695: +3497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 5869 .loc 1 3497 5 is_stmt 1 view .LVU1968 + 5870 0086 B0F85810 ldrh r1, [r0, #88] + 5871 008a FFF7FEFF bl HAL_UARTEx_RxEventCallback + 5872 .LVL523: +3497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 5873 .loc 1 3497 5 is_stmt 0 view .LVU1969 + 5874 008e EFE7 b .L220 + 5875 .cfi_endproc + 5876 .LFE195: + ARM GAS /tmp/ccQxTlMj.s page 224 + + + 5878 .section .text.HAL_UARTEx_WakeupCallback,"ax",%progbits + 5879 .align 1 + 5880 .weak HAL_UARTEx_WakeupCallback + 5881 .syntax unified + 5882 .thumb + 5883 .thumb_func + 5885 HAL_UARTEx_WakeupCallback: + 5886 .LVL524: + 5887 .LFB173: +2574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Prevent unused argument(s) compilation warning */ + 5888 .loc 1 2574 1 is_stmt 1 view -0 + 5889 .cfi_startproc + 5890 @ args = 0, pretend = 0, frame = 0 + 5891 @ frame_needed = 0, uses_anonymous_args = 0 + 5892 @ link register save eliminated. +2576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5893 .loc 1 2576 3 view .LVU1971 +2581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5894 .loc 1 2581 1 is_stmt 0 view .LVU1972 + 5895 0000 7047 bx lr + 5896 .cfi_endproc + 5897 .LFE173: + 5899 .section .text.HAL_UART_IRQHandler,"ax",%progbits + 5900 .align 1 + 5901 .global HAL_UART_IRQHandler + 5902 .syntax unified + 5903 .thumb + 5904 .thumb_func + 5906 HAL_UART_IRQHandler: + 5907 .LVL525: + 5908 .LFB163: +2129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t isrflags = READ_REG(huart->Instance->ISR); + 5909 .loc 1 2129 1 is_stmt 1 view -0 + 5910 .cfi_startproc + 5911 @ args = 0, pretend = 0, frame = 0 + 5912 @ frame_needed = 0, uses_anonymous_args = 0 +2129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t isrflags = READ_REG(huart->Instance->ISR); + 5913 .loc 1 2129 1 is_stmt 0 view .LVU1974 + 5914 0000 70B5 push {r4, r5, r6, lr} + 5915 .LCFI28: + 5916 .cfi_def_cfa_offset 16 + 5917 .cfi_offset 4, -16 + 5918 .cfi_offset 5, -12 + 5919 .cfi_offset 6, -8 + 5920 .cfi_offset 14, -4 + 5921 0002 0446 mov r4, r0 +2130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t cr1its = READ_REG(huart->Instance->CR1); + 5922 .loc 1 2130 3 is_stmt 1 view .LVU1975 +2130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t cr1its = READ_REG(huart->Instance->CR1); + 5923 .loc 1 2130 25 is_stmt 0 view .LVU1976 + 5924 0004 0268 ldr r2, [r0] +2130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t cr1its = READ_REG(huart->Instance->CR1); + 5925 .loc 1 2130 12 view .LVU1977 + 5926 0006 D369 ldr r3, [r2, #28] + 5927 .LVL526: +2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t cr3its = READ_REG(huart->Instance->CR3); + 5928 .loc 1 2131 3 is_stmt 1 view .LVU1978 + ARM GAS /tmp/ccQxTlMj.s page 225 + + +2131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t cr3its = READ_REG(huart->Instance->CR3); + 5929 .loc 1 2131 12 is_stmt 0 view .LVU1979 + 5930 0008 1168 ldr r1, [r2] + 5931 .LVL527: +2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5932 .loc 1 2132 3 is_stmt 1 view .LVU1980 +2132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5933 .loc 1 2132 12 is_stmt 0 view .LVU1981 + 5934 000a 9068 ldr r0, [r2, #8] + 5935 .LVL528: +2134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t errorcode; + 5936 .loc 1 2134 3 is_stmt 1 view .LVU1982 +2135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 5937 .loc 1 2135 3 view .LVU1983 +2138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (errorflags == 0U) + 5938 .loc 1 2138 3 view .LVU1984 +2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5939 .loc 1 2139 3 view .LVU1985 +2139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5940 .loc 1 2139 6 is_stmt 0 view .LVU1986 + 5941 000c 40F60F0C movw ip, #2063 + 5942 0010 13EA0C0F tst r3, ip + 5943 0014 0AD1 bne .L232 +2142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && ((cr1its & USART_CR1_RXNEIE) != 0U)) + 5944 .loc 1 2142 5 is_stmt 1 view .LVU1987 +2142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && ((cr1its & USART_CR1_RXNEIE) != 0U)) + 5945 .loc 1 2142 8 is_stmt 0 view .LVU1988 + 5946 0016 13F0200F tst r3, #32 + 5947 001a 0DD0 beq .L233 +2143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5948 .loc 1 2143 9 view .LVU1989 + 5949 001c 11F0200F tst r1, #32 + 5950 0020 0AD0 beq .L233 +2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5951 .loc 1 2145 7 is_stmt 1 view .LVU1990 +2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5952 .loc 1 2145 16 is_stmt 0 view .LVU1991 + 5953 0022 A36E ldr r3, [r4, #104] + 5954 .LVL529: +2145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5955 .loc 1 2145 10 view .LVU1992 + 5956 0024 0BB3 cbz r3, .L231 +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5957 .loc 1 2147 9 is_stmt 1 view .LVU1993 + 5958 0026 2046 mov r0, r4 + 5959 .LVL530: +2147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5960 .loc 1 2147 9 is_stmt 0 view .LVU1994 + 5961 0028 9847 blx r3 + 5962 .LVL531: +2149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 5963 .loc 1 2149 7 is_stmt 1 view .LVU1995 + 5964 002a 1EE0 b .L231 + 5965 .LVL532: + 5966 .L232: +2155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))) + 5967 .loc 1 2155 7 is_stmt 0 view .LVU1996 + ARM GAS /tmp/ccQxTlMj.s page 226 + + + 5968 002c 10F00105 ands r5, r0, #1 + 5969 0030 1CD1 bne .L236 +2156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5970 .loc 1 2156 11 view .LVU1997 + 5971 0032 AB4E ldr r6, .L270 + 5972 0034 3142 tst r1, r6 + 5973 0036 19D1 bne .L236 + 5974 .L233: +2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && ((isrflags & USART_ISR_IDLE) != 0U) + 5975 .loc 1 2292 3 is_stmt 1 view .LVU1998 +2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && ((isrflags & USART_ISR_IDLE) != 0U) + 5976 .loc 1 2292 13 is_stmt 0 view .LVU1999 + 5977 0038 256E ldr r5, [r4, #96] +2292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && ((isrflags & USART_ISR_IDLE) != 0U) + 5978 .loc 1 2292 6 view .LVU2000 + 5979 003a 012D cmp r5, #1 + 5980 003c 00F0A480 beq .L266 + 5981 .L250: +2390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5982 .loc 1 2390 3 is_stmt 1 view .LVU2001 +2390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5983 .loc 1 2390 6 is_stmt 0 view .LVU2002 + 5984 0040 13F4801F tst r3, #1048576 + 5985 0044 03D0 beq .L262 +2390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5986 .loc 1 2390 42 discriminator 1 view .LVU2003 + 5987 0046 10F4800F tst r0, #4194304 + 5988 004a 40F03781 bne .L267 + 5989 .L262: +2410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && ((cr1its & USART_CR1_TXEIE) != 0U)) + 5990 .loc 1 2410 3 is_stmt 1 view .LVU2004 +2410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && ((cr1its & USART_CR1_TXEIE) != 0U)) + 5991 .loc 1 2410 6 is_stmt 0 view .LVU2005 + 5992 004e 13F0800F tst r3, #128 + 5993 0052 03D0 beq .L263 +2411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5994 .loc 1 2411 7 view .LVU2006 + 5995 0054 11F0800F tst r1, #128 + 5996 0058 40F03781 bne .L268 + 5997 .L263: +2421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5998 .loc 1 2421 3 is_stmt 1 view .LVU2007 +2421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 5999 .loc 1 2421 6 is_stmt 0 view .LVU2008 + 6000 005c 13F0400F tst r3, #64 + 6001 0060 03D0 beq .L231 +2421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6002 .loc 1 2421 41 discriminator 1 view .LVU2009 + 6003 0062 11F0400F tst r1, #64 + 6004 0066 40F03781 bne .L269 + 6005 .LVL533: + 6006 .L231: +2427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6007 .loc 1 2427 1 view .LVU2010 + 6008 006a 70BD pop {r4, r5, r6, pc} + 6009 .LVL534: + 6010 .L236: + ARM GAS /tmp/ccQxTlMj.s page 227 + + +2159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6011 .loc 1 2159 5 is_stmt 1 view .LVU2011 +2159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6012 .loc 1 2159 8 is_stmt 0 view .LVU2012 + 6013 006c 13F0010F tst r3, #1 + 6014 0070 09D0 beq .L237 +2159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6015 .loc 1 2159 43 discriminator 1 view .LVU2013 + 6016 0072 11F4807F tst r1, #256 + 6017 0076 06D0 beq .L237 +2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6018 .loc 1 2161 7 is_stmt 1 view .LVU2014 + 6019 0078 0120 movs r0, #1 + 6020 .LVL535: +2161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6021 .loc 1 2161 7 is_stmt 0 view .LVU2015 + 6022 007a 1062 str r0, [r2, #32] +2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6023 .loc 1 2163 7 is_stmt 1 view .LVU2016 +2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6024 .loc 1 2163 12 is_stmt 0 view .LVU2017 + 6025 007c D4F88420 ldr r2, [r4, #132] +2163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6026 .loc 1 2163 24 view .LVU2018 + 6027 0080 0243 orrs r2, r2, r0 + 6028 0082 C4F88420 str r2, [r4, #132] + 6029 .L237: +2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6030 .loc 1 2167 5 is_stmt 1 view .LVU2019 +2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6031 .loc 1 2167 8 is_stmt 0 view .LVU2020 + 6032 0086 13F0020F tst r3, #2 + 6033 008a 09D0 beq .L238 +2167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6034 .loc 1 2167 43 discriminator 1 view .LVU2021 + 6035 008c 45B1 cbz r5, .L238 +2169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6036 .loc 1 2169 7 is_stmt 1 view .LVU2022 + 6037 008e 2268 ldr r2, [r4] + 6038 0090 0220 movs r0, #2 + 6039 0092 1062 str r0, [r2, #32] +2171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6040 .loc 1 2171 7 view .LVU2023 +2171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6041 .loc 1 2171 12 is_stmt 0 view .LVU2024 + 6042 0094 D4F88420 ldr r2, [r4, #132] +2171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6043 .loc 1 2171 24 view .LVU2025 + 6044 0098 42F00402 orr r2, r2, #4 + 6045 009c C4F88420 str r2, [r4, #132] + 6046 .L238: +2175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6047 .loc 1 2175 5 is_stmt 1 view .LVU2026 +2175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6048 .loc 1 2175 8 is_stmt 0 view .LVU2027 + 6049 00a0 13F0040F tst r3, #4 + 6050 00a4 09D0 beq .L239 + ARM GAS /tmp/ccQxTlMj.s page 228 + + +2175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6051 .loc 1 2175 43 discriminator 1 view .LVU2028 + 6052 00a6 45B1 cbz r5, .L239 +2177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6053 .loc 1 2177 7 is_stmt 1 view .LVU2029 + 6054 00a8 2268 ldr r2, [r4] + 6055 00aa 0420 movs r0, #4 + 6056 00ac 1062 str r0, [r2, #32] +2179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6057 .loc 1 2179 7 view .LVU2030 +2179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6058 .loc 1 2179 12 is_stmt 0 view .LVU2031 + 6059 00ae D4F88420 ldr r2, [r4, #132] +2179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6060 .loc 1 2179 24 view .LVU2032 + 6061 00b2 42F00202 orr r2, r2, #2 + 6062 00b6 C4F88420 str r2, [r4, #132] + 6063 .L239: +2183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && (((cr1its & USART_CR1_RXNEIE) != 0U) || + 6064 .loc 1 2183 5 is_stmt 1 view .LVU2033 +2183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && (((cr1its & USART_CR1_RXNEIE) != 0U) || + 6065 .loc 1 2183 8 is_stmt 0 view .LVU2034 + 6066 00ba 13F0080F tst r3, #8 + 6067 00be 0BD0 beq .L240 +2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ((cr3its & USART_CR3_EIE) != 0U))) + 6068 .loc 1 2184 9 view .LVU2035 + 6069 00c0 11F0200F tst r1, #32 + 6070 00c4 00D1 bne .L241 +2184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ((cr3its & USART_CR3_EIE) != 0U))) + 6071 .loc 1 2184 49 discriminator 1 view .LVU2036 + 6072 00c6 3DB1 cbz r5, .L240 + 6073 .L241: +2187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6074 .loc 1 2187 7 is_stmt 1 view .LVU2037 + 6075 00c8 2268 ldr r2, [r4] + 6076 00ca 0820 movs r0, #8 + 6077 00cc 1062 str r0, [r2, #32] +2189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6078 .loc 1 2189 7 view .LVU2038 +2189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6079 .loc 1 2189 12 is_stmt 0 view .LVU2039 + 6080 00ce D4F88420 ldr r2, [r4, #132] +2189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6081 .loc 1 2189 24 view .LVU2040 + 6082 00d2 0243 orrs r2, r2, r0 + 6083 00d4 C4F88420 str r2, [r4, #132] + 6084 .L240: +2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6085 .loc 1 2193 5 is_stmt 1 view .LVU2041 +2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6086 .loc 1 2193 8 is_stmt 0 view .LVU2042 + 6087 00d8 13F4006F tst r3, #2048 + 6088 00dc 0CD0 beq .L242 +2193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6089 .loc 1 2193 45 discriminator 1 view .LVU2043 + 6090 00de 11F0806F tst r1, #67108864 + 6091 00e2 09D0 beq .L242 + ARM GAS /tmp/ccQxTlMj.s page 229 + + +2195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6092 .loc 1 2195 7 is_stmt 1 view .LVU2044 + 6093 00e4 2268 ldr r2, [r4] + 6094 00e6 4FF40060 mov r0, #2048 + 6095 00ea 1062 str r0, [r2, #32] +2197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6096 .loc 1 2197 7 view .LVU2045 +2197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6097 .loc 1 2197 12 is_stmt 0 view .LVU2046 + 6098 00ec D4F88420 ldr r2, [r4, #132] +2197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6099 .loc 1 2197 24 view .LVU2047 + 6100 00f0 42F02002 orr r2, r2, #32 + 6101 00f4 C4F88420 str r2, [r4, #132] + 6102 .L242: +2201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6103 .loc 1 2201 5 is_stmt 1 view .LVU2048 +2201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6104 .loc 1 2201 14 is_stmt 0 view .LVU2049 + 6105 00f8 D4F88420 ldr r2, [r4, #132] +2201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6106 .loc 1 2201 8 view .LVU2050 + 6107 00fc 002A cmp r2, #0 + 6108 00fe B4D0 beq .L231 +2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && ((cr1its & USART_CR1_RXNEIE) != 0U)) + 6109 .loc 1 2204 7 is_stmt 1 view .LVU2051 +2204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && ((cr1its & USART_CR1_RXNEIE) != 0U)) + 6110 .loc 1 2204 10 is_stmt 0 view .LVU2052 + 6111 0100 13F0200F tst r3, #32 + 6112 0104 06D0 beq .L244 +2205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6113 .loc 1 2205 11 view .LVU2053 + 6114 0106 11F0200F tst r1, #32 + 6115 010a 03D0 beq .L244 +2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6116 .loc 1 2207 9 is_stmt 1 view .LVU2054 +2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6117 .loc 1 2207 18 is_stmt 0 view .LVU2055 + 6118 010c A36E ldr r3, [r4, #104] + 6119 .LVL536: +2207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6120 .loc 1 2207 12 view .LVU2056 + 6121 010e 0BB1 cbz r3, .L244 +2209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6122 .loc 1 2209 11 is_stmt 1 view .LVU2057 + 6123 0110 2046 mov r0, r4 + 6124 0112 9847 blx r3 + 6125 .LVL537: + 6126 .L244: +2218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + 6127 .loc 1 2218 7 view .LVU2058 +2218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + 6128 .loc 1 2218 17 is_stmt 0 view .LVU2059 + 6129 0114 D4F88420 ldr r2, [r4, #132] + 6130 .LVL538: +2219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + 6131 .loc 1 2219 7 is_stmt 1 view .LVU2060 + ARM GAS /tmp/ccQxTlMj.s page 230 + + +2219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + 6132 .loc 1 2219 12 is_stmt 0 view .LVU2061 + 6133 0118 2368 ldr r3, [r4] + 6134 011a 9B68 ldr r3, [r3, #8] +2219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + 6135 .loc 1 2219 10 view .LVU2062 + 6136 011c 13F0400F tst r3, #64 + 6137 0120 02D1 bne .L245 +2219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + 6138 .loc 1 2219 66 discriminator 1 view .LVU2063 + 6139 0122 12F0280F tst r2, #40 + 6140 0126 28D0 beq .L246 + 6141 .L245: +2225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6142 .loc 1 2225 9 is_stmt 1 view .LVU2064 + 6143 0128 2046 mov r0, r4 + 6144 012a FFF7FEFF bl UART_EndRxTransfer + 6145 .LVL539: +2228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6146 .loc 1 2228 9 view .LVU2065 +2228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6147 .loc 1 2228 13 is_stmt 0 view .LVU2066 + 6148 012e 2368 ldr r3, [r4] + 6149 0130 9B68 ldr r3, [r3, #8] +2228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6150 .loc 1 2228 12 view .LVU2067 + 6151 0132 13F0400F tst r3, #64 + 6152 0136 1CD0 beq .L247 + 6153 .L248: +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6154 .loc 1 2231 11 is_stmt 1 discriminator 1 view .LVU2068 + 6155 .LBB700: +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6156 .loc 1 2231 11 discriminator 1 view .LVU2069 +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6157 .loc 1 2231 11 discriminator 1 view .LVU2070 +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6158 .loc 1 2231 11 discriminator 1 view .LVU2071 + 6159 0138 2268 ldr r2, [r4] + 6160 .LVL540: + 6161 .LBB701: + 6162 .LBI701: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 6163 .loc 2 1068 31 view .LVU2072 + 6164 .LBB702: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 6165 .loc 2 1070 5 view .LVU2073 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6166 .loc 2 1072 4 view .LVU2074 + 6167 013a 02F10803 add r3, r2, #8 + 6168 .LVL541: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6169 .loc 2 1072 4 is_stmt 0 view .LVU2075 + 6170 .syntax unified + 6171 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 6172 013e 53E8003F ldrex r3, [r3] + 6173 @ 0 "" 2 + ARM GAS /tmp/ccQxTlMj.s page 231 + + + 6174 .LVL542: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 6175 .loc 2 1073 4 is_stmt 1 view .LVU2076 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 6176 .loc 2 1073 4 is_stmt 0 view .LVU2077 + 6177 .thumb + 6178 .syntax unified + 6179 .LBE702: + 6180 .LBE701: +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6181 .loc 1 2231 11 discriminator 1 view .LVU2078 + 6182 0142 23F04003 bic r3, r3, #64 + 6183 .LVL543: +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6184 .loc 1 2231 11 is_stmt 1 discriminator 1 view .LVU2079 + 6185 .LBB703: + 6186 .LBI703: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 6187 .loc 2 1119 31 view .LVU2080 + 6188 .LBB704: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 6189 .loc 2 1121 4 view .LVU2081 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6190 .loc 2 1123 4 view .LVU2082 + 6191 0146 0832 adds r2, r2, #8 + 6192 .LVL544: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6193 .loc 2 1123 4 is_stmt 0 view .LVU2083 + 6194 .syntax unified + 6195 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 6196 0148 42E80031 strex r1, r3, [r2] + 6197 @ 0 "" 2 + 6198 .LVL545: + 6199 .loc 2 1124 4 is_stmt 1 view .LVU2084 + 6200 .loc 2 1124 4 is_stmt 0 view .LVU2085 + 6201 .thumb + 6202 .syntax unified + 6203 .LBE704: + 6204 .LBE703: +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6205 .loc 1 2231 11 discriminator 1 view .LVU2086 + 6206 014c 0029 cmp r1, #0 + 6207 014e F3D1 bne .L248 + 6208 .LBE700: +2231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6209 .loc 1 2231 11 is_stmt 1 discriminator 2 view .LVU2087 +2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6210 .loc 1 2234 11 view .LVU2088 +2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6211 .loc 1 2234 20 is_stmt 0 view .LVU2089 + 6212 0150 636F ldr r3, [r4, #116] + 6213 .LVL546: +2234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6214 .loc 1 2234 14 view .LVU2090 + 6215 0152 53B1 cbz r3, .L249 +2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6216 .loc 1 2238 13 is_stmt 1 view .LVU2091 + ARM GAS /tmp/ccQxTlMj.s page 232 + + +2238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6217 .loc 1 2238 46 is_stmt 0 view .LVU2092 + 6218 0154 634A ldr r2, .L270+4 + 6219 0156 1A65 str r2, [r3, #80] +2241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6220 .loc 1 2241 13 is_stmt 1 view .LVU2093 +2241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6221 .loc 1 2241 17 is_stmt 0 view .LVU2094 + 6222 0158 606F ldr r0, [r4, #116] + 6223 015a FFF7FEFF bl HAL_DMA_Abort_IT + 6224 .LVL547: +2241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6225 .loc 1 2241 16 discriminator 1 view .LVU2095 + 6226 015e 0028 cmp r0, #0 + 6227 0160 83D0 beq .L231 +2244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6228 .loc 1 2244 15 is_stmt 1 view .LVU2096 +2244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6229 .loc 1 2244 20 is_stmt 0 view .LVU2097 + 6230 0162 606F ldr r0, [r4, #116] +2244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6231 .loc 1 2244 28 view .LVU2098 + 6232 0164 036D ldr r3, [r0, #80] +2244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6233 .loc 1 2244 15 view .LVU2099 + 6234 0166 9847 blx r3 + 6235 .LVL548: + 6236 0168 7FE7 b .L231 + 6237 .L249: +2255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 6238 .loc 1 2255 13 is_stmt 1 view .LVU2100 + 6239 016a 2046 mov r0, r4 + 6240 016c FFF7FEFF bl HAL_UART_ErrorCallback + 6241 .LVL549: + 6242 0170 7BE7 b .L231 + 6243 .LVL550: + 6244 .L247: +2268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 6245 .loc 1 2268 11 view .LVU2101 + 6246 0172 2046 mov r0, r4 + 6247 0174 FFF7FEFF bl HAL_UART_ErrorCallback + 6248 .LVL551: + 6249 0178 77E7 b .L231 + 6250 .LVL552: + 6251 .L246: +2281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 6252 .loc 1 2281 9 view .LVU2102 + 6253 017a 2046 mov r0, r4 + 6254 017c FFF7FEFF bl HAL_UART_ErrorCallback + 6255 .LVL553: +2283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6256 .loc 1 2283 9 view .LVU2103 +2283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6257 .loc 1 2283 26 is_stmt 0 view .LVU2104 + 6258 0180 0023 movs r3, #0 + 6259 0182 C4F88430 str r3, [r4, #132] +2286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 233 + + + 6260 .loc 1 2286 5 is_stmt 1 view .LVU2105 + 6261 0186 70E7 b .L231 + 6262 .LVL554: + 6263 .L266: +2293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && ((cr1its & USART_ISR_IDLE) != 0U)) + 6264 .loc 1 2293 7 is_stmt 0 view .LVU2106 + 6265 0188 13F0100F tst r3, #16 + 6266 018c 3FF458AF beq .L250 +2294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6267 .loc 1 2294 7 view .LVU2107 + 6268 0190 11F0100F tst r1, #16 + 6269 0194 3FF454AF beq .L250 +2296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6270 .loc 1 2296 5 is_stmt 1 view .LVU2108 + 6271 0198 1023 movs r3, #16 + 6272 .LVL555: +2296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6273 .loc 1 2296 5 is_stmt 0 view .LVU2109 + 6274 019a 1362 str r3, [r2, #32] +2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6275 .loc 1 2299 5 is_stmt 1 view .LVU2110 +2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6276 .loc 1 2299 9 is_stmt 0 view .LVU2111 + 6277 019c 2368 ldr r3, [r4] + 6278 019e 9B68 ldr r3, [r3, #8] +2299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6279 .loc 1 2299 8 view .LVU2112 + 6280 01a0 13F0400F tst r3, #64 + 6281 01a4 50D0 beq .L251 + 6282 .LBB705: +2305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((nb_remaining_rx_data > 0U) + 6283 .loc 1 2305 7 is_stmt 1 view .LVU2113 +2305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((nb_remaining_rx_data > 0U) + 6284 .loc 1 2305 50 is_stmt 0 view .LVU2114 + 6285 01a6 626F ldr r2, [r4, #116] + 6286 01a8 1368 ldr r3, [r2] + 6287 01aa 5B68 ldr r3, [r3, #4] +2305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((nb_remaining_rx_data > 0U) + 6288 .loc 1 2305 16 view .LVU2115 + 6289 01ac 9BB2 uxth r3, r3 + 6290 .LVL556: +2306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && (nb_remaining_rx_data < huart->RxXferSize)) + 6291 .loc 1 2306 7 is_stmt 1 view .LVU2116 +2306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && (nb_remaining_rx_data < huart->RxXferSize)) + 6292 .loc 1 2306 10 is_stmt 0 view .LVU2117 + 6293 01ae 002B cmp r3, #0 + 6294 01b0 3FF45BAF beq .L231 +2307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6295 .loc 1 2307 43 view .LVU2118 + 6296 01b4 B4F85810 ldrh r1, [r4, #88] + 6297 .LVL557: +2307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6298 .loc 1 2307 11 view .LVU2119 + 6299 01b8 9942 cmp r1, r3 + 6300 01ba 7FF656AF bls .L231 +2310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6301 .loc 1 2310 9 is_stmt 1 view .LVU2120 + ARM GAS /tmp/ccQxTlMj.s page 234 + + +2310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6302 .loc 1 2310 28 is_stmt 0 view .LVU2121 + 6303 01be A4F85A30 strh r3, [r4, #90] @ movhi +2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6304 .loc 1 2313 9 is_stmt 1 view .LVU2122 +2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6305 .loc 1 2313 32 is_stmt 0 view .LVU2123 + 6306 01c2 D369 ldr r3, [r2, #28] + 6307 .LVL558: +2313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6308 .loc 1 2313 12 view .LVU2124 + 6309 01c4 B3F5807F cmp r3, #256 + 6310 01c8 31D0 beq .L253 + 6311 .L254: +2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 6312 .loc 1 2316 11 is_stmt 1 discriminator 1 view .LVU2125 + 6313 .LBB706: +2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 6314 .loc 1 2316 11 discriminator 1 view .LVU2126 +2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 6315 .loc 1 2316 11 discriminator 1 view .LVU2127 +2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 6316 .loc 1 2316 11 discriminator 1 view .LVU2128 + 6317 01ca 2268 ldr r2, [r4] + 6318 .LVL559: + 6319 .LBB707: + 6320 .LBI707: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 6321 .loc 2 1068 31 view .LVU2129 + 6322 .LBB708: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 6323 .loc 2 1070 5 view .LVU2130 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6324 .loc 2 1072 4 view .LVU2131 + 6325 .syntax unified + 6326 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 6327 01cc 52E8003F ldrex r3, [r2] + 6328 @ 0 "" 2 + 6329 .LVL560: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 6330 .loc 2 1073 4 view .LVU2132 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 6331 .loc 2 1073 4 is_stmt 0 view .LVU2133 + 6332 .thumb + 6333 .syntax unified + 6334 .LBE708: + 6335 .LBE707: +2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 6336 .loc 1 2316 11 discriminator 1 view .LVU2134 + 6337 01d0 23F48073 bic r3, r3, #256 + 6338 .LVL561: +2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 6339 .loc 1 2316 11 is_stmt 1 discriminator 1 view .LVU2135 + 6340 .LBB709: + 6341 .LBI709: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 6342 .loc 2 1119 31 view .LVU2136 + ARM GAS /tmp/ccQxTlMj.s page 235 + + + 6343 .LBB710: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 6344 .loc 2 1121 4 view .LVU2137 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6345 .loc 2 1123 4 view .LVU2138 + 6346 .syntax unified + 6347 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 6348 01d4 42E80031 strex r1, r3, [r2] + 6349 @ 0 "" 2 + 6350 .LVL562: + 6351 .loc 2 1124 4 view .LVU2139 + 6352 .loc 2 1124 4 is_stmt 0 view .LVU2140 + 6353 .thumb + 6354 .syntax unified + 6355 .LBE710: + 6356 .LBE709: +2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 6357 .loc 1 2316 11 discriminator 1 view .LVU2141 + 6358 01d8 0029 cmp r1, #0 + 6359 01da F6D1 bne .L254 + 6360 .LVL563: + 6361 .L255: +2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 6362 .loc 1 2316 11 discriminator 1 view .LVU2142 + 6363 .LBE706: +2316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 6364 .loc 1 2316 11 is_stmt 1 discriminator 2 view .LVU2143 +2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6365 .loc 1 2317 11 discriminator 1 view .LVU2144 + 6366 .LBB711: +2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6367 .loc 1 2317 11 discriminator 1 view .LVU2145 +2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6368 .loc 1 2317 11 discriminator 1 view .LVU2146 +2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6369 .loc 1 2317 11 discriminator 1 view .LVU2147 + 6370 01dc 2268 ldr r2, [r4] + 6371 .LVL564: + 6372 .LBB712: + 6373 .LBI712: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 6374 .loc 2 1068 31 view .LVU2148 + 6375 .LBB713: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 6376 .loc 2 1070 5 view .LVU2149 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6377 .loc 2 1072 4 view .LVU2150 + 6378 01de 02F10803 add r3, r2, #8 + 6379 .LVL565: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6380 .loc 2 1072 4 is_stmt 0 view .LVU2151 + 6381 .syntax unified + 6382 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 6383 01e2 53E8003F ldrex r3, [r3] + 6384 @ 0 "" 2 + 6385 .LVL566: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccQxTlMj.s page 236 + + + 6386 .loc 2 1073 4 is_stmt 1 view .LVU2152 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 6387 .loc 2 1073 4 is_stmt 0 view .LVU2153 + 6388 .thumb + 6389 .syntax unified + 6390 .LBE713: + 6391 .LBE712: +2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6392 .loc 1 2317 11 discriminator 1 view .LVU2154 + 6393 01e6 23F00103 bic r3, r3, #1 + 6394 .LVL567: +2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6395 .loc 1 2317 11 is_stmt 1 discriminator 1 view .LVU2155 + 6396 .LBB714: + 6397 .LBI714: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 6398 .loc 2 1119 31 view .LVU2156 + 6399 .LBB715: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 6400 .loc 2 1121 4 view .LVU2157 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6401 .loc 2 1123 4 view .LVU2158 + 6402 01ea 0832 adds r2, r2, #8 + 6403 .LVL568: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6404 .loc 2 1123 4 is_stmt 0 view .LVU2159 + 6405 .syntax unified + 6406 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 6407 01ec 42E80031 strex r1, r3, [r2] + 6408 @ 0 "" 2 + 6409 .LVL569: + 6410 .loc 2 1124 4 is_stmt 1 view .LVU2160 + 6411 .loc 2 1124 4 is_stmt 0 view .LVU2161 + 6412 .thumb + 6413 .syntax unified + 6414 .LBE715: + 6415 .LBE714: +2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6416 .loc 1 2317 11 discriminator 1 view .LVU2162 + 6417 01f0 0029 cmp r1, #0 + 6418 01f2 F3D1 bne .L255 + 6419 .LVL570: + 6420 .L256: +2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6421 .loc 1 2317 11 discriminator 1 view .LVU2163 + 6422 .LBE711: +2317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6423 .loc 1 2317 11 is_stmt 1 discriminator 2 view .LVU2164 +2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6424 .loc 1 2321 11 discriminator 1 view .LVU2165 + 6425 .LBB716: +2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6426 .loc 1 2321 11 discriminator 1 view .LVU2166 +2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6427 .loc 1 2321 11 discriminator 1 view .LVU2167 +2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6428 .loc 1 2321 11 discriminator 1 view .LVU2168 + ARM GAS /tmp/ccQxTlMj.s page 237 + + + 6429 01f4 2268 ldr r2, [r4] + 6430 .LVL571: + 6431 .LBB717: + 6432 .LBI717: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 6433 .loc 2 1068 31 view .LVU2169 + 6434 .LBB718: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 6435 .loc 2 1070 5 view .LVU2170 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6436 .loc 2 1072 4 view .LVU2171 + 6437 01f6 02F10803 add r3, r2, #8 + 6438 .LVL572: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6439 .loc 2 1072 4 is_stmt 0 view .LVU2172 + 6440 .syntax unified + 6441 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 6442 01fa 53E8003F ldrex r3, [r3] + 6443 @ 0 "" 2 + 6444 .LVL573: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 6445 .loc 2 1073 4 is_stmt 1 view .LVU2173 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 6446 .loc 2 1073 4 is_stmt 0 view .LVU2174 + 6447 .thumb + 6448 .syntax unified + 6449 .LBE718: + 6450 .LBE717: +2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6451 .loc 1 2321 11 discriminator 1 view .LVU2175 + 6452 01fe 23F04003 bic r3, r3, #64 + 6453 .LVL574: +2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6454 .loc 1 2321 11 is_stmt 1 discriminator 1 view .LVU2176 + 6455 .LBB719: + 6456 .LBI719: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 6457 .loc 2 1119 31 view .LVU2177 + 6458 .LBB720: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 6459 .loc 2 1121 4 view .LVU2178 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6460 .loc 2 1123 4 view .LVU2179 + 6461 0202 0832 adds r2, r2, #8 + 6462 .LVL575: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6463 .loc 2 1123 4 is_stmt 0 view .LVU2180 + 6464 .syntax unified + 6465 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 6466 0204 42E80031 strex r1, r3, [r2] + 6467 @ 0 "" 2 + 6468 .LVL576: + 6469 .loc 2 1124 4 is_stmt 1 view .LVU2181 + 6470 .loc 2 1124 4 is_stmt 0 view .LVU2182 + 6471 .thumb + 6472 .syntax unified + 6473 .LBE720: + ARM GAS /tmp/ccQxTlMj.s page 238 + + + 6474 .LBE719: +2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6475 .loc 1 2321 11 discriminator 1 view .LVU2183 + 6476 0208 0029 cmp r1, #0 + 6477 020a F3D1 bne .L256 + 6478 .LBE716: +2321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6479 .loc 1 2321 11 is_stmt 1 discriminator 2 view .LVU2184 +2324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 6480 .loc 1 2324 11 view .LVU2185 +2324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 6481 .loc 1 2324 26 is_stmt 0 view .LVU2186 + 6482 020c 2023 movs r3, #32 + 6483 .LVL577: +2324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 6484 .loc 1 2324 26 view .LVU2187 + 6485 020e C4F88030 str r3, [r4, #128] + 6486 .LVL578: +2325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6487 .loc 1 2325 11 is_stmt 1 view .LVU2188 +2325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6488 .loc 1 2325 32 is_stmt 0 view .LVU2189 + 6489 0212 0023 movs r3, #0 + 6490 0214 2366 str r3, [r4, #96] + 6491 .L257: +2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6492 .loc 1 2327 11 is_stmt 1 discriminator 1 view .LVU2190 + 6493 .LBB721: +2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6494 .loc 1 2327 11 discriminator 1 view .LVU2191 +2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6495 .loc 1 2327 11 discriminator 1 view .LVU2192 +2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6496 .loc 1 2327 11 discriminator 1 view .LVU2193 + 6497 0216 2268 ldr r2, [r4] + 6498 .LVL579: + 6499 .LBB722: + 6500 .LBI722: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 6501 .loc 2 1068 31 view .LVU2194 + 6502 .LBB723: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 6503 .loc 2 1070 5 view .LVU2195 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6504 .loc 2 1072 4 view .LVU2196 + 6505 .syntax unified + 6506 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 6507 0218 52E8003F ldrex r3, [r2] + 6508 @ 0 "" 2 + 6509 .LVL580: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 6510 .loc 2 1073 4 view .LVU2197 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 6511 .loc 2 1073 4 is_stmt 0 view .LVU2198 + 6512 .thumb + 6513 .syntax unified + 6514 .LBE723: + ARM GAS /tmp/ccQxTlMj.s page 239 + + + 6515 .LBE722: +2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6516 .loc 1 2327 11 discriminator 1 view .LVU2199 + 6517 021c 23F01003 bic r3, r3, #16 + 6518 .LVL581: +2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6519 .loc 1 2327 11 is_stmt 1 discriminator 1 view .LVU2200 + 6520 .LBB724: + 6521 .LBI724: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 6522 .loc 2 1119 31 view .LVU2201 + 6523 .LBB725: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 6524 .loc 2 1121 4 view .LVU2202 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6525 .loc 2 1123 4 view .LVU2203 + 6526 .syntax unified + 6527 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 6528 0220 42E80031 strex r1, r3, [r2] + 6529 @ 0 "" 2 + 6530 .LVL582: + 6531 .loc 2 1124 4 view .LVU2204 + 6532 .loc 2 1124 4 is_stmt 0 view .LVU2205 + 6533 .thumb + 6534 .syntax unified + 6535 .LBE725: + 6536 .LBE724: +2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6537 .loc 1 2327 11 discriminator 1 view .LVU2206 + 6538 0224 0029 cmp r1, #0 + 6539 0226 F6D1 bne .L257 + 6540 .LBE721: +2327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6541 .loc 1 2327 11 is_stmt 1 discriminator 2 view .LVU2207 +2330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6542 .loc 1 2330 11 view .LVU2208 +2330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6543 .loc 1 2330 17 is_stmt 0 view .LVU2209 + 6544 0228 606F ldr r0, [r4, #116] + 6545 .LVL583: +2330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6546 .loc 1 2330 17 view .LVU2210 + 6547 022a FFF7FEFF bl HAL_DMA_Abort + 6548 .LVL584: + 6549 .L253: +2335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6550 .loc 1 2335 9 is_stmt 1 view .LVU2211 +2335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6551 .loc 1 2335 28 is_stmt 0 view .LVU2212 + 6552 022e 0223 movs r3, #2 + 6553 0230 6366 str r3, [r4, #100] +2342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 6554 .loc 1 2342 9 is_stmt 1 view .LVU2213 +2342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 6555 .loc 1 2342 49 is_stmt 0 view .LVU2214 + 6556 0232 B4F85810 ldrh r1, [r4, #88] +2342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + ARM GAS /tmp/ccQxTlMj.s page 240 + + + 6557 .loc 1 2342 69 view .LVU2215 + 6558 0236 B4F85A30 ldrh r3, [r4, #90] + 6559 023a 9BB2 uxth r3, r3 +2342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 6560 .loc 1 2342 9 view .LVU2216 + 6561 023c C91A subs r1, r1, r3 + 6562 023e 89B2 uxth r1, r1 + 6563 0240 2046 mov r0, r4 + 6564 0242 FFF7FEFF bl HAL_UARTEx_RxEventCallback + 6565 .LVL585: +2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6566 .loc 1 2345 7 is_stmt 1 view .LVU2217 + 6567 0246 10E7 b .L231 + 6568 .LVL586: + 6569 .L251: +2345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6570 .loc 1 2345 7 is_stmt 0 view .LVU2218 + 6571 .LBE705: + 6572 .LBB726: +2352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((huart->RxXferCount > 0U) + 6573 .loc 1 2352 7 is_stmt 1 view .LVU2219 +2352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((huart->RxXferCount > 0U) + 6574 .loc 1 2352 34 is_stmt 0 view .LVU2220 + 6575 0248 B4F85810 ldrh r1, [r4, #88] + 6576 .LVL587: +2352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((huart->RxXferCount > 0U) + 6577 .loc 1 2352 54 view .LVU2221 + 6578 024c B4F85A30 ldrh r3, [r4, #90] + 6579 0250 9BB2 uxth r3, r3 +2352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((huart->RxXferCount > 0U) + 6580 .loc 1 2352 16 view .LVU2222 + 6581 0252 C91A subs r1, r1, r3 + 6582 0254 89B2 uxth r1, r1 + 6583 .LVL588: +2353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && (nb_rx_data > 0U)) + 6584 .loc 1 2353 7 is_stmt 1 view .LVU2223 +2353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && (nb_rx_data > 0U)) + 6585 .loc 1 2353 17 is_stmt 0 view .LVU2224 + 6586 0256 B4F85A30 ldrh r3, [r4, #90] + 6587 025a 9BB2 uxth r3, r3 +2353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** && (nb_rx_data > 0U)) + 6588 .loc 1 2353 10 view .LVU2225 + 6589 025c 002B cmp r3, #0 + 6590 025e 3FF404AF beq .L231 +2354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6591 .loc 1 2354 11 view .LVU2226 + 6592 0262 0029 cmp r1, #0 + 6593 0264 3FF401AF beq .L231 + 6594 .LVL589: + 6595 .L259: +2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6596 .loc 1 2357 9 is_stmt 1 discriminator 1 view .LVU2227 + 6597 .LBB727: +2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6598 .loc 1 2357 9 discriminator 1 view .LVU2228 +2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6599 .loc 1 2357 9 discriminator 1 view .LVU2229 + ARM GAS /tmp/ccQxTlMj.s page 241 + + +2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6600 .loc 1 2357 9 discriminator 1 view .LVU2230 + 6601 0268 2268 ldr r2, [r4] + 6602 .LVL590: + 6603 .LBB728: + 6604 .LBI728: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 6605 .loc 2 1068 31 view .LVU2231 + 6606 .LBB729: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 6607 .loc 2 1070 5 view .LVU2232 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6608 .loc 2 1072 4 view .LVU2233 + 6609 .syntax unified + 6610 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 6611 026a 52E8003F ldrex r3, [r2] + 6612 @ 0 "" 2 + 6613 .LVL591: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 6614 .loc 2 1073 4 view .LVU2234 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 6615 .loc 2 1073 4 is_stmt 0 view .LVU2235 + 6616 .thumb + 6617 .syntax unified + 6618 .LBE729: + 6619 .LBE728: +2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6620 .loc 1 2357 9 discriminator 1 view .LVU2236 + 6621 026e 23F49073 bic r3, r3, #288 + 6622 .LVL592: +2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6623 .loc 1 2357 9 is_stmt 1 discriminator 1 view .LVU2237 + 6624 .LBB730: + 6625 .LBI730: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 6626 .loc 2 1119 31 view .LVU2238 + 6627 .LBB731: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 6628 .loc 2 1121 4 view .LVU2239 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6629 .loc 2 1123 4 view .LVU2240 + 6630 .syntax unified + 6631 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 6632 0272 42E80030 strex r0, r3, [r2] + 6633 @ 0 "" 2 + 6634 .LVL593: + 6635 .loc 2 1124 4 view .LVU2241 + 6636 .loc 2 1124 4 is_stmt 0 view .LVU2242 + 6637 .thumb + 6638 .syntax unified + 6639 .LBE731: + 6640 .LBE730: +2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6641 .loc 1 2357 9 discriminator 1 view .LVU2243 + 6642 0276 0028 cmp r0, #0 + 6643 0278 F6D1 bne .L259 + 6644 .LVL594: + ARM GAS /tmp/ccQxTlMj.s page 242 + + + 6645 .L260: +2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6646 .loc 1 2357 9 discriminator 1 view .LVU2244 + 6647 .LBE727: +2357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6648 .loc 1 2357 9 is_stmt 1 discriminator 2 view .LVU2245 +2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6649 .loc 1 2360 9 discriminator 1 view .LVU2246 + 6650 .LBB732: +2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6651 .loc 1 2360 9 discriminator 1 view .LVU2247 +2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6652 .loc 1 2360 9 discriminator 1 view .LVU2248 +2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6653 .loc 1 2360 9 discriminator 1 view .LVU2249 + 6654 027a 2268 ldr r2, [r4] + 6655 .LVL595: + 6656 .LBB733: + 6657 .LBI733: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 6658 .loc 2 1068 31 view .LVU2250 + 6659 .LBB734: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 6660 .loc 2 1070 5 view .LVU2251 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6661 .loc 2 1072 4 view .LVU2252 + 6662 027c 02F10803 add r3, r2, #8 + 6663 .LVL596: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6664 .loc 2 1072 4 is_stmt 0 view .LVU2253 + 6665 .syntax unified + 6666 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 6667 0280 53E8003F ldrex r3, [r3] + 6668 @ 0 "" 2 + 6669 .LVL597: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 6670 .loc 2 1073 4 is_stmt 1 view .LVU2254 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 6671 .loc 2 1073 4 is_stmt 0 view .LVU2255 + 6672 .thumb + 6673 .syntax unified + 6674 .LBE734: + 6675 .LBE733: +2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6676 .loc 1 2360 9 discriminator 1 view .LVU2256 + 6677 0284 23F00103 bic r3, r3, #1 + 6678 .LVL598: +2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6679 .loc 1 2360 9 is_stmt 1 discriminator 1 view .LVU2257 + 6680 .LBB735: + 6681 .LBI735: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 6682 .loc 2 1119 31 view .LVU2258 + 6683 .LBB736: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 6684 .loc 2 1121 4 view .LVU2259 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/ccQxTlMj.s page 243 + + + 6685 .loc 2 1123 4 view .LVU2260 + 6686 0288 0832 adds r2, r2, #8 + 6687 .LVL599: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6688 .loc 2 1123 4 is_stmt 0 view .LVU2261 + 6689 .syntax unified + 6690 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 6691 028a 42E80030 strex r0, r3, [r2] + 6692 @ 0 "" 2 + 6693 .LVL600: + 6694 .loc 2 1124 4 is_stmt 1 view .LVU2262 + 6695 .loc 2 1124 4 is_stmt 0 view .LVU2263 + 6696 .thumb + 6697 .syntax unified + 6698 .LBE736: + 6699 .LBE735: +2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6700 .loc 1 2360 9 discriminator 1 view .LVU2264 + 6701 028e 0028 cmp r0, #0 + 6702 0290 F3D1 bne .L260 + 6703 .LBE732: +2360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6704 .loc 1 2360 9 is_stmt 1 discriminator 2 view .LVU2265 +2363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 6705 .loc 1 2363 9 view .LVU2266 +2363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 6706 .loc 1 2363 24 is_stmt 0 view .LVU2267 + 6707 0292 2023 movs r3, #32 + 6708 .LVL601: +2363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 6709 .loc 1 2363 24 view .LVU2268 + 6710 0294 C4F88030 str r3, [r4, #128] +2364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6711 .loc 1 2364 9 is_stmt 1 view .LVU2269 +2364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6712 .loc 1 2364 30 is_stmt 0 view .LVU2270 + 6713 0298 0023 movs r3, #0 + 6714 029a 2366 str r3, [r4, #96] +2367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6715 .loc 1 2367 9 is_stmt 1 view .LVU2271 +2367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6716 .loc 1 2367 22 is_stmt 0 view .LVU2272 + 6717 029c A366 str r3, [r4, #104] + 6718 .L261: +2369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6719 .loc 1 2369 9 is_stmt 1 discriminator 1 view .LVU2273 + 6720 .LBB737: +2369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6721 .loc 1 2369 9 discriminator 1 view .LVU2274 +2369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6722 .loc 1 2369 9 discriminator 1 view .LVU2275 +2369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6723 .loc 1 2369 9 discriminator 1 view .LVU2276 + 6724 029e 2268 ldr r2, [r4] + 6725 .LVL602: + 6726 .LBB738: + 6727 .LBI738: + ARM GAS /tmp/ccQxTlMj.s page 244 + + +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 6728 .loc 2 1068 31 view .LVU2277 + 6729 .LBB739: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 6730 .loc 2 1070 5 view .LVU2278 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6731 .loc 2 1072 4 view .LVU2279 + 6732 .syntax unified + 6733 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 6734 02a0 52E8003F ldrex r3, [r2] + 6735 @ 0 "" 2 + 6736 .LVL603: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 6737 .loc 2 1073 4 view .LVU2280 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 6738 .loc 2 1073 4 is_stmt 0 view .LVU2281 + 6739 .thumb + 6740 .syntax unified + 6741 .LBE739: + 6742 .LBE738: +2369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6743 .loc 1 2369 9 discriminator 1 view .LVU2282 + 6744 02a4 23F01003 bic r3, r3, #16 + 6745 .LVL604: +2369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6746 .loc 1 2369 9 is_stmt 1 discriminator 1 view .LVU2283 + 6747 .LBB740: + 6748 .LBI740: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 6749 .loc 2 1119 31 view .LVU2284 + 6750 .LBB741: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 6751 .loc 2 1121 4 view .LVU2285 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 6752 .loc 2 1123 4 view .LVU2286 + 6753 .syntax unified + 6754 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 6755 02a8 42E80030 strex r0, r3, [r2] + 6756 @ 0 "" 2 + 6757 .LVL605: + 6758 .loc 2 1124 4 view .LVU2287 + 6759 .loc 2 1124 4 is_stmt 0 view .LVU2288 + 6760 .thumb + 6761 .syntax unified + 6762 .LBE741: + 6763 .LBE740: +2369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6764 .loc 1 2369 9 discriminator 1 view .LVU2289 + 6765 02ac 0028 cmp r0, #0 + 6766 02ae F6D1 bne .L261 + 6767 .LBE737: +2369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6768 .loc 1 2369 9 is_stmt 1 discriminator 2 view .LVU2290 +2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6769 .loc 1 2373 9 view .LVU2291 +2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6770 .loc 1 2373 28 is_stmt 0 view .LVU2292 + ARM GAS /tmp/ccQxTlMj.s page 245 + + + 6771 02b0 0223 movs r3, #2 + 6772 .LVL606: +2373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6773 .loc 1 2373 28 view .LVU2293 + 6774 02b2 6366 str r3, [r4, #100] +2380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 6775 .loc 1 2380 9 is_stmt 1 view .LVU2294 + 6776 02b4 2046 mov r0, r4 + 6777 02b6 FFF7FEFF bl HAL_UARTEx_RxEventCallback + 6778 .LVL607: +2383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6779 .loc 1 2383 7 view .LVU2295 + 6780 02ba D6E6 b .L231 + 6781 .LVL608: + 6782 .L267: +2383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6783 .loc 1 2383 7 is_stmt 0 view .LVU2296 + 6784 .LBE726: +2392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6785 .loc 1 2392 5 is_stmt 1 view .LVU2297 + 6786 02bc 4FF48013 mov r3, #1048576 + 6787 .LVL609: +2392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6788 .loc 1 2392 5 is_stmt 0 view .LVU2298 + 6789 02c0 1362 str r3, [r2, #32] +2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 6790 .loc 1 2402 5 is_stmt 1 view .LVU2299 + 6791 02c2 2046 mov r0, r4 + 6792 .LVL610: +2402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + 6793 .loc 1 2402 5 is_stmt 0 view .LVU2300 + 6794 02c4 FFF7FEFF bl HAL_UARTEx_WakeupCallback + 6795 .LVL611: +2404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6796 .loc 1 2404 5 is_stmt 1 view .LVU2301 + 6797 02c8 CFE6 b .L231 + 6798 .LVL612: + 6799 .L268: +2413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6800 .loc 1 2413 5 view .LVU2302 +2413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6801 .loc 1 2413 14 is_stmt 0 view .LVU2303 + 6802 02ca E36E ldr r3, [r4, #108] + 6803 .LVL613: +2413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6804 .loc 1 2413 8 view .LVU2304 + 6805 02cc 002B cmp r3, #0 + 6806 02ce 3FF4CCAE beq .L231 +2415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6807 .loc 1 2415 7 is_stmt 1 view .LVU2305 + 6808 02d2 2046 mov r0, r4 + 6809 .LVL614: +2415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6810 .loc 1 2415 7 is_stmt 0 view .LVU2306 + 6811 02d4 9847 blx r3 + 6812 .LVL615: +2417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + ARM GAS /tmp/ccQxTlMj.s page 246 + + + 6813 .loc 1 2417 5 is_stmt 1 view .LVU2307 + 6814 02d6 C8E6 b .L231 + 6815 .LVL616: + 6816 .L269: +2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return; + 6817 .loc 1 2423 5 view .LVU2308 + 6818 02d8 2046 mov r0, r4 + 6819 .LVL617: +2423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return; + 6820 .loc 1 2423 5 is_stmt 0 view .LVU2309 + 6821 02da FFF7FEFF bl UART_EndTransmit_IT + 6822 .LVL618: +2424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6823 .loc 1 2424 5 is_stmt 1 view .LVU2310 + 6824 02de C4E6 b .L231 + 6825 .L271: + 6826 .align 2 + 6827 .L270: + 6828 02e0 20010004 .word 67109152 + 6829 02e4 00000000 .word UART_DMAAbortOnError + 6830 .cfi_endproc + 6831 .LFE163: + 6833 .section .text.HAL_UART_ReceiverTimeout_Config,"ax",%progbits + 6834 .align 1 + 6835 .global HAL_UART_ReceiverTimeout_Config + 6836 .syntax unified + 6837 .thumb + 6838 .thumb_func + 6840 HAL_UART_ReceiverTimeout_Config: + 6841 .LVL619: + 6842 .LFB174: +2622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); + 6843 .loc 1 2622 1 view -0 + 6844 .cfi_startproc + 6845 @ args = 0, pretend = 0, frame = 0 + 6846 @ frame_needed = 0, uses_anonymous_args = 0 + 6847 @ link register save eliminated. +2623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); + 6848 .loc 1 2623 3 view .LVU2312 +2624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6849 .loc 1 2624 3 view .LVU2313 + 6850 0000 0268 ldr r2, [r0] + 6851 0002 5369 ldr r3, [r2, #20] + 6852 0004 03F07F43 and r3, r3, #-16777216 + 6853 0008 0B43 orrs r3, r3, r1 + 6854 000a 5361 str r3, [r2, #20] +2625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6855 .loc 1 2625 1 is_stmt 0 view .LVU2314 + 6856 000c 7047 bx lr + 6857 .cfi_endproc + 6858 .LFE174: + 6860 .section .text.HAL_UART_EnableReceiverTimeout,"ax",%progbits + 6861 .align 1 + 6862 .global HAL_UART_EnableReceiverTimeout + 6863 .syntax unified + 6864 .thumb + 6865 .thumb_func + ARM GAS /tmp/ccQxTlMj.s page 247 + + + 6867 HAL_UART_EnableReceiverTimeout: + 6868 .LVL620: + 6869 .LFB175: +2634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_READY) + 6870 .loc 1 2634 1 is_stmt 1 view -0 + 6871 .cfi_startproc + 6872 @ args = 0, pretend = 0, frame = 0 + 6873 @ frame_needed = 0, uses_anonymous_args = 0 + 6874 @ link register save eliminated. +2635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6875 .loc 1 2635 3 view .LVU2316 +2635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6876 .loc 1 2635 12 is_stmt 0 view .LVU2317 + 6877 0000 C36F ldr r3, [r0, #124] +2635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6878 .loc 1 2635 6 view .LVU2318 + 6879 0002 202B cmp r3, #32 + 6880 0004 14D1 bne .L275 +2638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6881 .loc 1 2638 5 is_stmt 1 view .LVU2319 +2638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6882 .loc 1 2638 5 view .LVU2320 + 6883 0006 90F87830 ldrb r3, [r0, #120] @ zero_extendqisi2 + 6884 000a 012B cmp r3, #1 + 6885 000c 12D0 beq .L276 +2638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6886 .loc 1 2638 5 discriminator 2 view .LVU2321 + 6887 000e 0123 movs r3, #1 + 6888 0010 80F87830 strb r3, [r0, #120] +2638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6889 .loc 1 2638 5 discriminator 2 view .LVU2322 +2640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6890 .loc 1 2640 5 view .LVU2323 +2640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6891 .loc 1 2640 19 is_stmt 0 view .LVU2324 + 6892 0014 2423 movs r3, #36 + 6893 0016 C367 str r3, [r0, #124] +2643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6894 .loc 1 2643 5 is_stmt 1 view .LVU2325 + 6895 0018 0268 ldr r2, [r0] + 6896 001a 5368 ldr r3, [r2, #4] + 6897 001c 43F40003 orr r3, r3, #8388608 + 6898 0020 5360 str r3, [r2, #4] +2645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6899 .loc 1 2645 5 view .LVU2326 +2645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6900 .loc 1 2645 19 is_stmt 0 view .LVU2327 + 6901 0022 2023 movs r3, #32 + 6902 0024 C367 str r3, [r0, #124] +2648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6903 .loc 1 2648 5 is_stmt 1 view .LVU2328 +2648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6904 .loc 1 2648 5 view .LVU2329 + 6905 0026 0023 movs r3, #0 + 6906 0028 80F87830 strb r3, [r0, #120] +2648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6907 .loc 1 2648 5 view .LVU2330 + ARM GAS /tmp/ccQxTlMj.s page 248 + + +2650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6908 .loc 1 2650 5 view .LVU2331 +2650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6909 .loc 1 2650 12 is_stmt 0 view .LVU2332 + 6910 002c 1846 mov r0, r3 + 6911 .LVL621: +2650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6912 .loc 1 2650 12 view .LVU2333 + 6913 002e 7047 bx lr + 6914 .LVL622: + 6915 .L275: +2654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6916 .loc 1 2654 12 view .LVU2334 + 6917 0030 0220 movs r0, #2 + 6918 .LVL623: +2654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6919 .loc 1 2654 12 view .LVU2335 + 6920 0032 7047 bx lr + 6921 .LVL624: + 6922 .L276: +2638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6923 .loc 1 2638 5 discriminator 1 view .LVU2336 + 6924 0034 0220 movs r0, #2 + 6925 .LVL625: +2656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6926 .loc 1 2656 1 view .LVU2337 + 6927 0036 7047 bx lr + 6928 .cfi_endproc + 6929 .LFE175: + 6931 .section .text.HAL_UART_DisableReceiverTimeout,"ax",%progbits + 6932 .align 1 + 6933 .global HAL_UART_DisableReceiverTimeout + 6934 .syntax unified + 6935 .thumb + 6936 .thumb_func + 6938 HAL_UART_DisableReceiverTimeout: + 6939 .LVL626: + 6940 .LFB176: +2665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if (huart->gState == HAL_UART_STATE_READY) + 6941 .loc 1 2665 1 is_stmt 1 view -0 + 6942 .cfi_startproc + 6943 @ args = 0, pretend = 0, frame = 0 + 6944 @ frame_needed = 0, uses_anonymous_args = 0 + 6945 @ link register save eliminated. +2666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6946 .loc 1 2666 3 view .LVU2339 +2666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6947 .loc 1 2666 12 is_stmt 0 view .LVU2340 + 6948 0000 C36F ldr r3, [r0, #124] +2666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 6949 .loc 1 2666 6 view .LVU2341 + 6950 0002 202B cmp r3, #32 + 6951 0004 14D1 bne .L279 +2669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6952 .loc 1 2669 5 is_stmt 1 view .LVU2342 +2669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6953 .loc 1 2669 5 view .LVU2343 + ARM GAS /tmp/ccQxTlMj.s page 249 + + + 6954 0006 90F87830 ldrb r3, [r0, #120] @ zero_extendqisi2 + 6955 000a 012B cmp r3, #1 + 6956 000c 12D0 beq .L280 +2669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6957 .loc 1 2669 5 discriminator 2 view .LVU2344 + 6958 000e 0123 movs r3, #1 + 6959 0010 80F87830 strb r3, [r0, #120] +2669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6960 .loc 1 2669 5 discriminator 2 view .LVU2345 +2671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6961 .loc 1 2671 5 view .LVU2346 +2671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6962 .loc 1 2671 19 is_stmt 0 view .LVU2347 + 6963 0014 2423 movs r3, #36 + 6964 0016 C367 str r3, [r0, #124] +2674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6965 .loc 1 2674 5 is_stmt 1 view .LVU2348 + 6966 0018 0268 ldr r2, [r0] + 6967 001a 5368 ldr r3, [r2, #4] + 6968 001c 23F40003 bic r3, r3, #8388608 + 6969 0020 5360 str r3, [r2, #4] +2676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6970 .loc 1 2676 5 view .LVU2349 +2676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6971 .loc 1 2676 19 is_stmt 0 view .LVU2350 + 6972 0022 2023 movs r3, #32 + 6973 0024 C367 str r3, [r0, #124] +2679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6974 .loc 1 2679 5 is_stmt 1 view .LVU2351 +2679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6975 .loc 1 2679 5 view .LVU2352 + 6976 0026 0023 movs r3, #0 + 6977 0028 80F87830 strb r3, [r0, #120] +2679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6978 .loc 1 2679 5 view .LVU2353 +2681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6979 .loc 1 2681 5 view .LVU2354 +2681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6980 .loc 1 2681 12 is_stmt 0 view .LVU2355 + 6981 002c 1846 mov r0, r3 + 6982 .LVL627: +2681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6983 .loc 1 2681 12 view .LVU2356 + 6984 002e 7047 bx lr + 6985 .LVL628: + 6986 .L279: +2685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6987 .loc 1 2685 12 view .LVU2357 + 6988 0030 0220 movs r0, #2 + 6989 .LVL629: +2685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 6990 .loc 1 2685 12 view .LVU2358 + 6991 0032 7047 bx lr + 6992 .LVL630: + 6993 .L280: +2669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6994 .loc 1 2669 5 discriminator 1 view .LVU2359 + ARM GAS /tmp/ccQxTlMj.s page 250 + + + 6995 0034 0220 movs r0, #2 + 6996 .LVL631: +2687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 6997 .loc 1 2687 1 view .LVU2360 + 6998 0036 7047 bx lr + 6999 .cfi_endproc + 7000 .LFE176: + 7002 .section .text.HAL_MultiProcessor_EnterMuteMode,"ax",%progbits + 7003 .align 1 + 7004 .global HAL_MultiProcessor_EnterMuteMode + 7005 .syntax unified + 7006 .thumb + 7007 .thumb_func + 7009 HAL_MultiProcessor_EnterMuteMode: + 7010 .LVL632: + 7011 .LFB179: +2736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); + 7012 .loc 1 2736 1 is_stmt 1 view -0 + 7013 .cfi_startproc + 7014 @ args = 0, pretend = 0, frame = 0 + 7015 @ frame_needed = 0, uses_anonymous_args = 0 + 7016 @ link register save eliminated. +2737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 7017 .loc 1 2737 3 view .LVU2362 + 7018 0000 0268 ldr r2, [r0] + 7019 0002 9369 ldr r3, [r2, #24] + 7020 0004 43F00403 orr r3, r3, #4 + 7021 0008 9361 str r3, [r2, #24] +2738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7022 .loc 1 2738 1 is_stmt 0 view .LVU2363 + 7023 000a 7047 bx lr + 7024 .cfi_endproc + 7025 .LFE179: + 7027 .section .text.HAL_HalfDuplex_EnableTransmitter,"ax",%progbits + 7028 .align 1 + 7029 .global HAL_HalfDuplex_EnableTransmitter + 7030 .syntax unified + 7031 .thumb + 7032 .thumb_func + 7034 HAL_HalfDuplex_EnableTransmitter: + 7035 .LVL633: + 7036 .LFB180: +2746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_LOCK(huart); + 7037 .loc 1 2746 1 is_stmt 1 view -0 + 7038 .cfi_startproc + 7039 @ args = 0, pretend = 0, frame = 0 + 7040 @ frame_needed = 0, uses_anonymous_args = 0 + 7041 @ link register save eliminated. +2747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 7042 .loc 1 2747 3 view .LVU2365 +2747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 7043 .loc 1 2747 3 view .LVU2366 + 7044 0000 90F87830 ldrb r3, [r0, #120] @ zero_extendqisi2 + 7045 0004 012B cmp r3, #1 + 7046 0006 1DD0 beq .L286 +2747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 7047 .loc 1 2747 3 discriminator 2 view .LVU2367 + ARM GAS /tmp/ccQxTlMj.s page 251 + + + 7048 0008 0123 movs r3, #1 + 7049 000a 80F87830 strb r3, [r0, #120] +2747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 7050 .loc 1 2747 3 discriminator 2 view .LVU2368 +2748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7051 .loc 1 2748 3 view .LVU2369 +2748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7052 .loc 1 2748 17 is_stmt 0 view .LVU2370 + 7053 000e 2423 movs r3, #36 + 7054 0010 C367 str r3, [r0, #124] + 7055 .L284: +2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7056 .loc 1 2751 3 is_stmt 1 discriminator 1 view .LVU2371 + 7057 .LBB742: +2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7058 .loc 1 2751 3 discriminator 1 view .LVU2372 +2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7059 .loc 1 2751 3 discriminator 1 view .LVU2373 +2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7060 .loc 1 2751 3 discriminator 1 view .LVU2374 + 7061 0012 0268 ldr r2, [r0] + 7062 .LVL634: + 7063 .LBB743: + 7064 .LBI743: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 7065 .loc 2 1068 31 view .LVU2375 + 7066 .LBB744: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 7067 .loc 2 1070 5 view .LVU2376 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 7068 .loc 2 1072 4 view .LVU2377 + 7069 .syntax unified + 7070 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 7071 0014 52E8003F ldrex r3, [r2] + 7072 @ 0 "" 2 + 7073 .LVL635: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 7074 .loc 2 1073 4 view .LVU2378 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 7075 .loc 2 1073 4 is_stmt 0 view .LVU2379 + 7076 .thumb + 7077 .syntax unified + 7078 .LBE744: + 7079 .LBE743: +2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7080 .loc 1 2751 3 discriminator 1 view .LVU2380 + 7081 0018 23F00C03 bic r3, r3, #12 + 7082 .LVL636: +2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7083 .loc 1 2751 3 is_stmt 1 discriminator 1 view .LVU2381 + 7084 .LBB745: + 7085 .LBI745: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 7086 .loc 2 1119 31 view .LVU2382 + 7087 .LBB746: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 7088 .loc 2 1121 4 view .LVU2383 + ARM GAS /tmp/ccQxTlMj.s page 252 + + +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 7089 .loc 2 1123 4 view .LVU2384 + 7090 .syntax unified + 7091 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 7092 001c 42E80031 strex r1, r3, [r2] + 7093 @ 0 "" 2 + 7094 .LVL637: + 7095 .loc 2 1124 4 view .LVU2385 + 7096 .loc 2 1124 4 is_stmt 0 view .LVU2386 + 7097 .thumb + 7098 .syntax unified + 7099 .LBE746: + 7100 .LBE745: +2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7101 .loc 1 2751 3 discriminator 1 view .LVU2387 + 7102 0020 0029 cmp r1, #0 + 7103 0022 F6D1 bne .L284 + 7104 .LVL638: + 7105 .L285: +2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7106 .loc 1 2751 3 discriminator 1 view .LVU2388 + 7107 .LBE742: +2751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7108 .loc 1 2751 3 is_stmt 1 discriminator 2 view .LVU2389 +2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7109 .loc 1 2754 3 discriminator 1 view .LVU2390 + 7110 .LBB747: +2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7111 .loc 1 2754 3 discriminator 1 view .LVU2391 +2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7112 .loc 1 2754 3 discriminator 1 view .LVU2392 +2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7113 .loc 1 2754 3 discriminator 1 view .LVU2393 + 7114 0024 0268 ldr r2, [r0] + 7115 .LVL639: + 7116 .LBB748: + 7117 .LBI748: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 7118 .loc 2 1068 31 view .LVU2394 + 7119 .LBB749: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 7120 .loc 2 1070 5 view .LVU2395 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 7121 .loc 2 1072 4 view .LVU2396 + 7122 .syntax unified + 7123 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 7124 0026 52E8003F ldrex r3, [r2] + 7125 @ 0 "" 2 + 7126 .LVL640: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 7127 .loc 2 1073 4 view .LVU2397 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 7128 .loc 2 1073 4 is_stmt 0 view .LVU2398 + 7129 .thumb + 7130 .syntax unified + 7131 .LBE749: + 7132 .LBE748: + ARM GAS /tmp/ccQxTlMj.s page 253 + + +2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7133 .loc 1 2754 3 discriminator 1 view .LVU2399 + 7134 002a 43F00803 orr r3, r3, #8 + 7135 .LVL641: +2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7136 .loc 1 2754 3 is_stmt 1 discriminator 1 view .LVU2400 + 7137 .LBB750: + 7138 .LBI750: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 7139 .loc 2 1119 31 view .LVU2401 + 7140 .LBB751: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 7141 .loc 2 1121 4 view .LVU2402 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 7142 .loc 2 1123 4 view .LVU2403 + 7143 .syntax unified + 7144 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 7145 002e 42E80031 strex r1, r3, [r2] + 7146 @ 0 "" 2 + 7147 .LVL642: + 7148 .loc 2 1124 4 view .LVU2404 + 7149 .loc 2 1124 4 is_stmt 0 view .LVU2405 + 7150 .thumb + 7151 .syntax unified + 7152 .LBE751: + 7153 .LBE750: +2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7154 .loc 1 2754 3 discriminator 1 view .LVU2406 + 7155 0032 0029 cmp r1, #0 + 7156 0034 F6D1 bne .L285 + 7157 .LBE747: +2754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7158 .loc 1 2754 3 is_stmt 1 discriminator 2 view .LVU2407 +2756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7159 .loc 1 2756 3 view .LVU2408 +2756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7160 .loc 1 2756 17 is_stmt 0 view .LVU2409 + 7161 0036 2023 movs r3, #32 + 7162 .LVL643: +2756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7163 .loc 1 2756 17 view .LVU2410 + 7164 0038 C367 str r3, [r0, #124] +2758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7165 .loc 1 2758 3 is_stmt 1 view .LVU2411 +2758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7166 .loc 1 2758 3 view .LVU2412 + 7167 003a 0023 movs r3, #0 + 7168 003c 80F87830 strb r3, [r0, #120] +2758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7169 .loc 1 2758 3 view .LVU2413 +2760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 7170 .loc 1 2760 3 view .LVU2414 +2760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 7171 .loc 1 2760 10 is_stmt 0 view .LVU2415 + 7172 0040 1846 mov r0, r3 + 7173 .LVL644: +2760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + ARM GAS /tmp/ccQxTlMj.s page 254 + + + 7174 .loc 1 2760 10 view .LVU2416 + 7175 0042 7047 bx lr + 7176 .LVL645: + 7177 .L286: +2747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 7178 .loc 1 2747 3 discriminator 1 view .LVU2417 + 7179 0044 0220 movs r0, #2 + 7180 .LVL646: +2761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7181 .loc 1 2761 1 view .LVU2418 + 7182 0046 7047 bx lr + 7183 .cfi_endproc + 7184 .LFE180: + 7186 .section .text.HAL_HalfDuplex_EnableReceiver,"ax",%progbits + 7187 .align 1 + 7188 .global HAL_HalfDuplex_EnableReceiver + 7189 .syntax unified + 7190 .thumb + 7191 .thumb_func + 7193 HAL_HalfDuplex_EnableReceiver: + 7194 .LVL647: + 7195 .LFB181: +2769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_LOCK(huart); + 7196 .loc 1 2769 1 is_stmt 1 view -0 + 7197 .cfi_startproc + 7198 @ args = 0, pretend = 0, frame = 0 + 7199 @ frame_needed = 0, uses_anonymous_args = 0 + 7200 @ link register save eliminated. +2770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 7201 .loc 1 2770 3 view .LVU2420 +2770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 7202 .loc 1 2770 3 view .LVU2421 + 7203 0000 90F87830 ldrb r3, [r0, #120] @ zero_extendqisi2 + 7204 0004 012B cmp r3, #1 + 7205 0006 1DD0 beq .L291 +2770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 7206 .loc 1 2770 3 discriminator 2 view .LVU2422 + 7207 0008 0123 movs r3, #1 + 7208 000a 80F87830 strb r3, [r0, #120] +2770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 7209 .loc 1 2770 3 discriminator 2 view .LVU2423 +2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7210 .loc 1 2771 3 view .LVU2424 +2771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7211 .loc 1 2771 17 is_stmt 0 view .LVU2425 + 7212 000e 2423 movs r3, #36 + 7213 0010 C367 str r3, [r0, #124] + 7214 .L289: +2774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7215 .loc 1 2774 3 is_stmt 1 discriminator 1 view .LVU2426 + 7216 .LBB752: +2774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7217 .loc 1 2774 3 discriminator 1 view .LVU2427 +2774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7218 .loc 1 2774 3 discriminator 1 view .LVU2428 +2774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7219 .loc 1 2774 3 discriminator 1 view .LVU2429 + ARM GAS /tmp/ccQxTlMj.s page 255 + + + 7220 0012 0268 ldr r2, [r0] + 7221 .LVL648: + 7222 .LBB753: + 7223 .LBI753: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 7224 .loc 2 1068 31 view .LVU2430 + 7225 .LBB754: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 7226 .loc 2 1070 5 view .LVU2431 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 7227 .loc 2 1072 4 view .LVU2432 + 7228 .syntax unified + 7229 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 7230 0014 52E8003F ldrex r3, [r2] + 7231 @ 0 "" 2 + 7232 .LVL649: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 7233 .loc 2 1073 4 view .LVU2433 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 7234 .loc 2 1073 4 is_stmt 0 view .LVU2434 + 7235 .thumb + 7236 .syntax unified + 7237 .LBE754: + 7238 .LBE753: +2774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7239 .loc 1 2774 3 discriminator 1 view .LVU2435 + 7240 0018 23F00C03 bic r3, r3, #12 + 7241 .LVL650: +2774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7242 .loc 1 2774 3 is_stmt 1 discriminator 1 view .LVU2436 + 7243 .LBB755: + 7244 .LBI755: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 7245 .loc 2 1119 31 view .LVU2437 + 7246 .LBB756: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 7247 .loc 2 1121 4 view .LVU2438 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 7248 .loc 2 1123 4 view .LVU2439 + 7249 .syntax unified + 7250 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 7251 001c 42E80031 strex r1, r3, [r2] + 7252 @ 0 "" 2 + 7253 .LVL651: + 7254 .loc 2 1124 4 view .LVU2440 + 7255 .loc 2 1124 4 is_stmt 0 view .LVU2441 + 7256 .thumb + 7257 .syntax unified + 7258 .LBE756: + 7259 .LBE755: +2774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7260 .loc 1 2774 3 discriminator 1 view .LVU2442 + 7261 0020 0029 cmp r1, #0 + 7262 0022 F6D1 bne .L289 + 7263 .LVL652: + 7264 .L290: +2774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 256 + + + 7265 .loc 1 2774 3 discriminator 1 view .LVU2443 + 7266 .LBE752: +2774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7267 .loc 1 2774 3 is_stmt 1 discriminator 2 view .LVU2444 +2777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7268 .loc 1 2777 3 discriminator 1 view .LVU2445 + 7269 .LBB757: +2777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7270 .loc 1 2777 3 discriminator 1 view .LVU2446 +2777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7271 .loc 1 2777 3 discriminator 1 view .LVU2447 +2777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7272 .loc 1 2777 3 discriminator 1 view .LVU2448 + 7273 0024 0268 ldr r2, [r0] + 7274 .LVL653: + 7275 .LBB758: + 7276 .LBI758: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 7277 .loc 2 1068 31 view .LVU2449 + 7278 .LBB759: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 7279 .loc 2 1070 5 view .LVU2450 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 7280 .loc 2 1072 4 view .LVU2451 + 7281 .syntax unified + 7282 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 7283 0026 52E8003F ldrex r3, [r2] + 7284 @ 0 "" 2 + 7285 .LVL654: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 7286 .loc 2 1073 4 view .LVU2452 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 7287 .loc 2 1073 4 is_stmt 0 view .LVU2453 + 7288 .thumb + 7289 .syntax unified + 7290 .LBE759: + 7291 .LBE758: +2777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7292 .loc 1 2777 3 discriminator 1 view .LVU2454 + 7293 002a 43F00403 orr r3, r3, #4 + 7294 .LVL655: +2777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7295 .loc 1 2777 3 is_stmt 1 discriminator 1 view .LVU2455 + 7296 .LBB760: + 7297 .LBI760: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 7298 .loc 2 1119 31 view .LVU2456 + 7299 .LBB761: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 7300 .loc 2 1121 4 view .LVU2457 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 7301 .loc 2 1123 4 view .LVU2458 + 7302 .syntax unified + 7303 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 7304 002e 42E80031 strex r1, r3, [r2] + 7305 @ 0 "" 2 + 7306 .LVL656: + ARM GAS /tmp/ccQxTlMj.s page 257 + + + 7307 .loc 2 1124 4 view .LVU2459 + 7308 .loc 2 1124 4 is_stmt 0 view .LVU2460 + 7309 .thumb + 7310 .syntax unified + 7311 .LBE761: + 7312 .LBE760: +2777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7313 .loc 1 2777 3 discriminator 1 view .LVU2461 + 7314 0032 0029 cmp r1, #0 + 7315 0034 F6D1 bne .L290 + 7316 .LBE757: +2777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7317 .loc 1 2777 3 is_stmt 1 discriminator 2 view .LVU2462 +2779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7318 .loc 1 2779 3 view .LVU2463 +2779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7319 .loc 1 2779 17 is_stmt 0 view .LVU2464 + 7320 0036 2023 movs r3, #32 + 7321 .LVL657: +2779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7322 .loc 1 2779 17 view .LVU2465 + 7323 0038 C367 str r3, [r0, #124] +2781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7324 .loc 1 2781 3 is_stmt 1 view .LVU2466 +2781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7325 .loc 1 2781 3 view .LVU2467 + 7326 003a 0023 movs r3, #0 + 7327 003c 80F87830 strb r3, [r0, #120] +2781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7328 .loc 1 2781 3 view .LVU2468 +2783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 7329 .loc 1 2783 3 view .LVU2469 +2783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 7330 .loc 1 2783 10 is_stmt 0 view .LVU2470 + 7331 0040 1846 mov r0, r3 + 7332 .LVL658: +2783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 7333 .loc 1 2783 10 view .LVU2471 + 7334 0042 7047 bx lr + 7335 .LVL659: + 7336 .L291: +2770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY; + 7337 .loc 1 2770 3 discriminator 1 view .LVU2472 + 7338 0044 0220 movs r0, #2 + 7339 .LVL660: +2784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7340 .loc 1 2784 1 view .LVU2473 + 7341 0046 7047 bx lr + 7342 .cfi_endproc + 7343 .LFE181: + 7345 .section .text.HAL_LIN_SendBreak,"ax",%progbits + 7346 .align 1 + 7347 .global HAL_LIN_SendBreak + 7348 .syntax unified + 7349 .thumb + 7350 .thumb_func + 7352 HAL_LIN_SendBreak: + ARM GAS /tmp/ccQxTlMj.s page 258 + + + 7353 .LVL661: + 7354 .LFB182: +2793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the parameters */ + 7355 .loc 1 2793 1 is_stmt 1 view -0 + 7356 .cfi_startproc + 7357 @ args = 0, pretend = 0, frame = 0 + 7358 @ frame_needed = 0, uses_anonymous_args = 0 + 7359 @ link register save eliminated. +2795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7360 .loc 1 2795 3 view .LVU2475 +2797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7361 .loc 1 2797 3 view .LVU2476 +2797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7362 .loc 1 2797 3 view .LVU2477 + 7363 0000 90F87830 ldrb r3, [r0, #120] @ zero_extendqisi2 + 7364 0004 012B cmp r3, #1 + 7365 0006 10D0 beq .L294 +2797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7366 .loc 1 2797 3 discriminator 2 view .LVU2478 + 7367 0008 0123 movs r3, #1 + 7368 000a 80F87830 strb r3, [r0, #120] +2797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7369 .loc 1 2797 3 discriminator 2 view .LVU2479 +2799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7370 .loc 1 2799 3 view .LVU2480 +2799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7371 .loc 1 2799 17 is_stmt 0 view .LVU2481 + 7372 000e 2423 movs r3, #36 + 7373 0010 C367 str r3, [r0, #124] +2802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7374 .loc 1 2802 3 is_stmt 1 view .LVU2482 + 7375 0012 0268 ldr r2, [r0] + 7376 0014 9369 ldr r3, [r2, #24] + 7377 0016 43F00203 orr r3, r3, #2 + 7378 001a 9361 str r3, [r2, #24] +2804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7379 .loc 1 2804 3 view .LVU2483 +2804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7380 .loc 1 2804 17 is_stmt 0 view .LVU2484 + 7381 001c 2023 movs r3, #32 + 7382 001e C367 str r3, [r0, #124] +2806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7383 .loc 1 2806 3 is_stmt 1 view .LVU2485 +2806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7384 .loc 1 2806 3 view .LVU2486 + 7385 0020 0023 movs r3, #0 + 7386 0022 80F87830 strb r3, [r0, #120] +2806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7387 .loc 1 2806 3 view .LVU2487 +2808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 7388 .loc 1 2808 3 view .LVU2488 +2808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 7389 .loc 1 2808 10 is_stmt 0 view .LVU2489 + 7390 0026 1846 mov r0, r3 + 7391 .LVL662: +2808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 7392 .loc 1 2808 10 view .LVU2490 + ARM GAS /tmp/ccQxTlMj.s page 259 + + + 7393 0028 7047 bx lr + 7394 .LVL663: + 7395 .L294: +2797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7396 .loc 1 2797 3 discriminator 1 view .LVU2491 + 7397 002a 0220 movs r0, #2 + 7398 .LVL664: +2809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7399 .loc 1 2809 1 view .LVU2492 + 7400 002c 7047 bx lr + 7401 .cfi_endproc + 7402 .LFE182: + 7404 .section .text.HAL_UART_GetState,"ax",%progbits + 7405 .align 1 + 7406 .global HAL_UART_GetState + 7407 .syntax unified + 7408 .thumb + 7409 .thumb_func + 7411 HAL_UART_GetState: + 7412 .LVL665: + 7413 .LFB183: +2838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t temp1; + 7414 .loc 1 2838 1 is_stmt 1 view -0 + 7415 .cfi_startproc + 7416 @ args = 0, pretend = 0, frame = 0 + 7417 @ frame_needed = 0, uses_anonymous_args = 0 + 7418 @ link register save eliminated. +2839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t temp2; + 7419 .loc 1 2839 3 view .LVU2494 +2840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** temp1 = huart->gState; + 7420 .loc 1 2840 3 view .LVU2495 +2841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** temp2 = huart->RxState; + 7421 .loc 1 2841 3 view .LVU2496 +2841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** temp2 = huart->RxState; + 7422 .loc 1 2841 9 is_stmt 0 view .LVU2497 + 7423 0000 C26F ldr r2, [r0, #124] + 7424 .LVL666: +2842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7425 .loc 1 2842 3 is_stmt 1 view .LVU2498 +2842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7426 .loc 1 2842 9 is_stmt 0 view .LVU2499 + 7427 0002 D0F88000 ldr r0, [r0, #128] + 7428 .LVL667: +2844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 7429 .loc 1 2844 3 is_stmt 1 view .LVU2500 +2845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7430 .loc 1 2845 1 is_stmt 0 view .LVU2501 + 7431 0006 1043 orrs r0, r0, r2 + 7432 .LVL668: +2845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7433 .loc 1 2845 1 view .LVU2502 + 7434 0008 7047 bx lr + 7435 .cfi_endproc + 7436 .LFE183: + 7438 .section .text.HAL_UART_GetError,"ax",%progbits + 7439 .align 1 + 7440 .global HAL_UART_GetError + ARM GAS /tmp/ccQxTlMj.s page 260 + + + 7441 .syntax unified + 7442 .thumb + 7443 .thumb_func + 7445 HAL_UART_GetError: + 7446 .LVL669: + 7447 .LFB184: +2854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** return huart->ErrorCode; + 7448 .loc 1 2854 1 is_stmt 1 view -0 + 7449 .cfi_startproc + 7450 @ args = 0, pretend = 0, frame = 0 + 7451 @ frame_needed = 0, uses_anonymous_args = 0 + 7452 @ link register save eliminated. +2855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 7453 .loc 1 2855 3 view .LVU2504 +2855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 7454 .loc 1 2855 15 is_stmt 0 view .LVU2505 + 7455 0000 D0F88400 ldr r0, [r0, #132] + 7456 .LVL670: +2856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /** + 7457 .loc 1 2856 1 view .LVU2506 + 7458 0004 7047 bx lr + 7459 .cfi_endproc + 7460 .LFE184: + 7462 .section .text.UART_SetConfig,"ax",%progbits + 7463 .align 1 + 7464 .global UART_SetConfig + 7465 .syntax unified + 7466 .thumb + 7467 .thumb_func + 7469 UART_SetConfig: + 7470 .LVL671: + 7471 .LFB185: +2902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t tmpreg; + 7472 .loc 1 2902 1 is_stmt 1 view -0 + 7473 .cfi_startproc + 7474 @ args = 0, pretend = 0, frame = 0 + 7475 @ frame_needed = 0, uses_anonymous_args = 0 +2902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t tmpreg; + 7476 .loc 1 2902 1 is_stmt 0 view .LVU2508 + 7477 0000 10B5 push {r4, lr} + 7478 .LCFI29: + 7479 .cfi_def_cfa_offset 8 + 7480 .cfi_offset 4, -8 + 7481 .cfi_offset 14, -4 + 7482 0002 0446 mov r4, r0 +2903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint16_t brrtemp; + 7483 .loc 1 2903 3 is_stmt 1 view .LVU2509 +2904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** UART_ClockSourceTypeDef clocksource; + 7484 .loc 1 2904 3 view .LVU2510 +2905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t usartdiv; + 7485 .loc 1 2905 3 view .LVU2511 +2906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** HAL_StatusTypeDef ret = HAL_OK; + 7486 .loc 1 2906 3 view .LVU2512 +2907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t pclk; + 7487 .loc 1 2907 3 view .LVU2513 + 7488 .LVL672: +2908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 261 + + + 7489 .loc 1 2908 3 view .LVU2514 +2911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + 7490 .loc 1 2911 3 view .LVU2515 +2912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + 7491 .loc 1 2912 3 view .LVU2516 +2913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); + 7492 .loc 1 2913 3 view .LVU2517 +2914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7493 .loc 1 2914 3 view .LVU2518 +2916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_MODE(huart->Init.Mode)); + 7494 .loc 1 2916 3 view .LVU2519 +2917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + 7495 .loc 1 2917 3 view .LVU2520 +2918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + 7496 .loc 1 2918 3 view .LVU2521 +2919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7497 .loc 1 2919 3 view .LVU2522 +2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 7498 .loc 1 2928 3 view .LVU2523 +2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 7499 .loc 1 2928 33 is_stmt 0 view .LVU2524 + 7500 0004 8368 ldr r3, [r0, #8] +2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 7501 .loc 1 2928 58 view .LVU2525 + 7502 0006 0269 ldr r2, [r0, #16] +2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 7503 .loc 1 2928 45 view .LVU2526 + 7504 0008 1343 orrs r3, r3, r2 +2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 7505 .loc 1 2928 79 view .LVU2527 + 7506 000a 4269 ldr r2, [r0, #20] +2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 7507 .loc 1 2928 66 view .LVU2528 + 7508 000c 1343 orrs r3, r3, r2 +2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 7509 .loc 1 2928 98 view .LVU2529 + 7510 000e C269 ldr r2, [r0, #28] +2928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 7511 .loc 1 2928 10 view .LVU2530 + 7512 0010 1343 orrs r3, r3, r2 + 7513 .LVL673: +2929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7514 .loc 1 2929 3 is_stmt 1 view .LVU2531 + 7515 0012 0168 ldr r1, [r0] + 7516 0014 0868 ldr r0, [r1] + 7517 .LVL674: +2929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7518 .loc 1 2929 3 is_stmt 0 view .LVU2532 + 7519 0016 914A ldr r2, .L384 + 7520 0018 0240 ands r2, r2, r0 + 7521 001a 1A43 orrs r2, r2, r3 + 7522 001c 0A60 str r2, [r1] +2934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7523 .loc 1 2934 3 is_stmt 1 view .LVU2533 + 7524 001e 2268 ldr r2, [r4] + 7525 0020 5368 ldr r3, [r2, #4] + 7526 .LVL675: + ARM GAS /tmp/ccQxTlMj.s page 262 + + +2934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7527 .loc 1 2934 3 is_stmt 0 view .LVU2534 + 7528 0022 23F44053 bic r3, r3, #12288 + 7529 0026 E168 ldr r1, [r4, #12] + 7530 0028 0B43 orrs r3, r3, r1 + 7531 002a 5360 str r3, [r2, #4] +2942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7532 .loc 1 2942 3 is_stmt 1 view .LVU2535 +2942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7533 .loc 1 2942 10 is_stmt 0 view .LVU2536 + 7534 002c A269 ldr r2, [r4, #24] + 7535 .LVL676: +2944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + 7536 .loc 1 2944 3 is_stmt 1 view .LVU2537 +2944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + 7537 .loc 1 2944 24 is_stmt 0 view .LVU2538 + 7538 002e 236A ldr r3, [r4, #32] +2944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + 7539 .loc 1 2944 10 view .LVU2539 + 7540 0030 1A43 orrs r2, r2, r3 + 7541 .LVL677: +2945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7542 .loc 1 2945 3 is_stmt 1 view .LVU2540 + 7543 0032 2168 ldr r1, [r4] + 7544 0034 8B68 ldr r3, [r1, #8] + 7545 0036 23F43063 bic r3, r3, #2816 + 7546 003a 1343 orrs r3, r3, r2 + 7547 003c 8B60 str r3, [r1, #8] +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7548 .loc 1 2949 3 view .LVU2541 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7549 .loc 1 2949 3 view .LVU2542 + 7550 003e 2368 ldr r3, [r4] + 7551 0040 874A ldr r2, .L384+4 + 7552 .LVL678: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7553 .loc 1 2949 3 is_stmt 0 view .LVU2543 + 7554 0042 9342 cmp r3, r2 + 7555 0044 18D0 beq .L375 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7556 .loc 1 2949 3 is_stmt 1 discriminator 2 view .LVU2544 + 7557 0046 874A ldr r2, .L384+8 + 7558 0048 9342 cmp r3, r2 + 7559 004a 3AD0 beq .L376 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7560 .loc 1 2949 3 discriminator 9 view .LVU2545 + 7561 004c 864A ldr r2, .L384+12 + 7562 004e 9342 cmp r3, r2 + 7563 0050 4FD0 beq .L377 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7564 .loc 1 2949 3 discriminator 16 view .LVU2546 + 7565 0052 864A ldr r2, .L384+16 + 7566 0054 9342 cmp r3, r2 + 7567 0056 5ED0 beq .L378 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7568 .loc 1 2949 3 discriminator 23 view .LVU2547 + 7569 0058 854A ldr r2, .L384+20 + ARM GAS /tmp/ccQxTlMj.s page 263 + + + 7570 005a 9342 cmp r3, r2 + 7571 005c 6DD0 beq .L379 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7572 .loc 1 2949 3 discriminator 30 view .LVU2548 + 7573 005e 854A ldr r2, .L384+24 + 7574 0060 9342 cmp r3, r2 + 7575 0062 7FD0 beq .L380 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7576 .loc 1 2949 3 discriminator 37 view .LVU2549 + 7577 0064 844A ldr r2, .L384+28 + 7578 0066 9342 cmp r3, r2 + 7579 0068 00F09180 beq .L381 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7580 .loc 1 2949 3 discriminator 44 view .LVU2550 + 7581 006c 834A ldr r2, .L384+32 + 7582 006e 9342 cmp r3, r2 + 7583 0070 00F0A280 beq .L382 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7584 .loc 1 2949 3 is_stmt 0 discriminator 51 view .LVU2551 + 7585 0074 1023 movs r3, #16 + 7586 0076 0BE0 b .L302 + 7587 .L375: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7588 .loc 1 2949 3 is_stmt 1 discriminator 1 view .LVU2552 + 7589 0078 814B ldr r3, .L384+36 + 7590 007a D3F89030 ldr r3, [r3, #144] + 7591 007e 03F00303 and r3, r3, #3 + 7592 0082 032B cmp r3, #3 + 7593 0084 1BD8 bhi .L299 + 7594 0086 DFE803F0 tbb [pc, r3] + 7595 .L301: + 7596 008a 02 .byte (.L304-.L301)/2 + 7597 008b 16 .byte (.L303-.L301)/2 + 7598 008c AB .byte (.L338-.L301)/2 + 7599 008d 18 .byte (.L300-.L301)/2 + 7600 .p2align 1 + 7601 .L304: + 7602 008e 0123 movs r3, #1 + 7603 .L302: + 7604 .LVL679: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7605 .loc 1 2949 3 discriminator 57 view .LVU2553 +2951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 7606 .loc 1 2951 3 view .LVU2554 +2951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 7607 .loc 1 2951 18 is_stmt 0 view .LVU2555 + 7608 0090 E069 ldr r0, [r4, #28] +2951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 7609 .loc 1 2951 6 view .LVU2556 + 7610 0092 B0F5004F cmp r0, #32768 + 7611 0096 00F0D780 beq .L383 +2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 7612 .loc 1 2994 5 is_stmt 1 view .LVU2557 + 7613 009a 082B cmp r3, #8 + 7614 009c 00F23881 bhi .L369 + 7615 00a0 DFE813F0 tbh [pc, r3, lsl #1] + 7616 .L332: + ARM GAS /tmp/ccQxTlMj.s page 264 + + + 7617 00a4 1401 .2byte (.L336-.L332)/2 + 7618 00a6 2701 .2byte (.L335-.L332)/2 + 7619 00a8 1201 .2byte (.L334-.L332)/2 + 7620 00aa 3601 .2byte (.L369-.L332)/2 + 7621 00ac 2A01 .2byte (.L333-.L332)/2 + 7622 00ae 3601 .2byte (.L369-.L332)/2 + 7623 00b0 3601 .2byte (.L369-.L332)/2 + 7624 00b2 3601 .2byte (.L369-.L332)/2 + 7625 00b4 2D01 .2byte (.L370-.L332)/2 + 7626 .LVL680: + 7627 .p2align 1 + 7628 .L303: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7629 .loc 1 2949 3 discriminator 5 view .LVU2558 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7630 .loc 1 2949 3 discriminator 5 view .LVU2559 + 7631 00b6 0423 movs r3, #4 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7632 .loc 1 2949 3 is_stmt 0 view .LVU2560 + 7633 00b8 EAE7 b .L302 + 7634 .LVL681: + 7635 .L300: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7636 .loc 1 2949 3 is_stmt 1 discriminator 7 view .LVU2561 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7637 .loc 1 2949 3 discriminator 7 view .LVU2562 + 7638 00ba 0823 movs r3, #8 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7639 .loc 1 2949 3 is_stmt 0 view .LVU2563 + 7640 00bc E8E7 b .L302 + 7641 .LVL682: + 7642 .L299: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7643 .loc 1 2949 3 is_stmt 1 discriminator 3 view .LVU2564 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7644 .loc 1 2949 3 discriminator 3 view .LVU2565 + 7645 00be 1023 movs r3, #16 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7646 .loc 1 2949 3 is_stmt 0 view .LVU2566 + 7647 00c0 E6E7 b .L302 + 7648 .LVL683: + 7649 .L376: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7650 .loc 1 2949 3 is_stmt 1 discriminator 8 view .LVU2567 + 7651 00c2 6F4B ldr r3, .L384+36 + 7652 00c4 D3F89030 ldr r3, [r3, #144] + 7653 00c8 03F00C03 and r3, r3, #12 + 7654 00cc 0C2B cmp r3, #12 + 7655 00ce 0ED8 bhi .L306 + 7656 00d0 DFE803F0 tbb [pc, r3] + 7657 .L308: + 7658 00d4 07 .byte (.L310-.L308)/2 + 7659 00d5 0D .byte (.L306-.L308)/2 + 7660 00d6 0D .byte (.L306-.L308)/2 + 7661 00d7 0D .byte (.L306-.L308)/2 + 7662 00d8 09 .byte (.L309-.L308)/2 + 7663 00d9 0D .byte (.L306-.L308)/2 + ARM GAS /tmp/ccQxTlMj.s page 265 + + + 7664 00da 0D .byte (.L306-.L308)/2 + 7665 00db 0D .byte (.L306-.L308)/2 + 7666 00dc 88 .byte (.L339-.L308)/2 + 7667 00dd 0D .byte (.L306-.L308)/2 + 7668 00de 0D .byte (.L306-.L308)/2 + 7669 00df 0D .byte (.L306-.L308)/2 + 7670 00e0 0B .byte (.L307-.L308)/2 + 7671 00e1 00 .p2align 1 + 7672 .L310: + 7673 00e2 0023 movs r3, #0 + 7674 00e4 D4E7 b .L302 + 7675 .L309: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7676 .loc 1 2949 3 discriminator 12 view .LVU2568 + 7677 .LVL684: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7678 .loc 1 2949 3 discriminator 12 view .LVU2569 + 7679 00e6 0423 movs r3, #4 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7680 .loc 1 2949 3 is_stmt 0 view .LVU2570 + 7681 00e8 D2E7 b .L302 + 7682 .LVL685: + 7683 .L307: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7684 .loc 1 2949 3 is_stmt 1 discriminator 14 view .LVU2571 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7685 .loc 1 2949 3 discriminator 14 view .LVU2572 + 7686 00ea 0823 movs r3, #8 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7687 .loc 1 2949 3 is_stmt 0 view .LVU2573 + 7688 00ec D0E7 b .L302 + 7689 .LVL686: + 7690 .L306: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7691 .loc 1 2949 3 is_stmt 1 discriminator 10 view .LVU2574 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7692 .loc 1 2949 3 discriminator 10 view .LVU2575 + 7693 00ee 1023 movs r3, #16 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7694 .loc 1 2949 3 is_stmt 0 view .LVU2576 + 7695 00f0 CEE7 b .L302 + 7696 .LVL687: + 7697 .L377: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7698 .loc 1 2949 3 is_stmt 1 discriminator 15 view .LVU2577 + 7699 00f2 634B ldr r3, .L384+36 + 7700 00f4 D3F89030 ldr r3, [r3, #144] + 7701 00f8 03F03003 and r3, r3, #48 + 7702 00fc 202B cmp r3, #32 + 7703 00fe 73D0 beq .L340 + 7704 0100 05D8 bhi .L312 + 7705 0102 002B cmp r3, #0 + 7706 0104 72D0 beq .L341 + 7707 0106 102B cmp r3, #16 + 7708 0108 72D1 bne .L342 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7709 .loc 1 2949 3 is_stmt 0 discriminator 19 view .LVU2578 + ARM GAS /tmp/ccQxTlMj.s page 266 + + + 7710 010a 0423 movs r3, #4 + 7711 010c C0E7 b .L302 + 7712 .L312: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7713 .loc 1 2949 3 discriminator 15 view .LVU2579 + 7714 010e 302B cmp r3, #48 + 7715 0110 70D1 bne .L343 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7716 .loc 1 2949 3 discriminator 21 view .LVU2580 + 7717 0112 0823 movs r3, #8 + 7718 0114 BCE7 b .L302 + 7719 .L378: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7720 .loc 1 2949 3 is_stmt 1 discriminator 22 view .LVU2581 + 7721 0116 5A4B ldr r3, .L384+36 + 7722 0118 D3F89030 ldr r3, [r3, #144] + 7723 011c 03F0C003 and r3, r3, #192 + 7724 0120 802B cmp r3, #128 + 7725 0122 69D0 beq .L344 + 7726 0124 05D8 bhi .L314 + 7727 0126 002B cmp r3, #0 + 7728 0128 68D0 beq .L345 + 7729 012a 402B cmp r3, #64 + 7730 012c 68D1 bne .L346 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7731 .loc 1 2949 3 is_stmt 0 discriminator 26 view .LVU2582 + 7732 012e 0423 movs r3, #4 + 7733 0130 AEE7 b .L302 + 7734 .L314: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7735 .loc 1 2949 3 discriminator 22 view .LVU2583 + 7736 0132 C02B cmp r3, #192 + 7737 0134 66D1 bne .L347 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7738 .loc 1 2949 3 discriminator 28 view .LVU2584 + 7739 0136 0823 movs r3, #8 + 7740 0138 AAE7 b .L302 + 7741 .L379: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7742 .loc 1 2949 3 is_stmt 1 discriminator 29 view .LVU2585 + 7743 013a 514B ldr r3, .L384+36 + 7744 013c D3F89030 ldr r3, [r3, #144] + 7745 0140 03F44073 and r3, r3, #768 + 7746 0144 B3F5007F cmp r3, #512 + 7747 0148 5ED0 beq .L348 + 7748 014a 06D8 bhi .L316 + 7749 014c 002B cmp r3, #0 + 7750 014e 5DD0 beq .L349 + 7751 0150 B3F5807F cmp r3, #256 + 7752 0154 5CD1 bne .L350 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7753 .loc 1 2949 3 is_stmt 0 discriminator 33 view .LVU2586 + 7754 0156 0423 movs r3, #4 + 7755 0158 9AE7 b .L302 + 7756 .L316: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7757 .loc 1 2949 3 discriminator 29 view .LVU2587 + ARM GAS /tmp/ccQxTlMj.s page 267 + + + 7758 015a B3F5407F cmp r3, #768 + 7759 015e 59D1 bne .L351 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7760 .loc 1 2949 3 discriminator 35 view .LVU2588 + 7761 0160 0823 movs r3, #8 + 7762 0162 95E7 b .L302 + 7763 .L380: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7764 .loc 1 2949 3 is_stmt 1 discriminator 36 view .LVU2589 + 7765 0164 464B ldr r3, .L384+36 + 7766 0166 D3F89030 ldr r3, [r3, #144] + 7767 016a 03F44063 and r3, r3, #3072 + 7768 016e B3F5006F cmp r3, #2048 + 7769 0172 51D0 beq .L352 + 7770 0174 06D8 bhi .L318 + 7771 0176 002B cmp r3, #0 + 7772 0178 50D0 beq .L353 + 7773 017a B3F5806F cmp r3, #1024 + 7774 017e 4FD1 bne .L354 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7775 .loc 1 2949 3 is_stmt 0 discriminator 40 view .LVU2590 + 7776 0180 0423 movs r3, #4 + 7777 0182 85E7 b .L302 + 7778 .L318: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7779 .loc 1 2949 3 discriminator 36 view .LVU2591 + 7780 0184 B3F5406F cmp r3, #3072 + 7781 0188 4CD1 bne .L355 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7782 .loc 1 2949 3 discriminator 42 view .LVU2592 + 7783 018a 0823 movs r3, #8 + 7784 018c 80E7 b .L302 + 7785 .L381: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7786 .loc 1 2949 3 is_stmt 1 discriminator 43 view .LVU2593 + 7787 018e 3C4B ldr r3, .L384+36 + 7788 0190 D3F89030 ldr r3, [r3, #144] + 7789 0194 03F44053 and r3, r3, #12288 + 7790 0198 B3F5005F cmp r3, #8192 + 7791 019c 44D0 beq .L356 + 7792 019e 06D8 bhi .L320 + 7793 01a0 002B cmp r3, #0 + 7794 01a2 43D0 beq .L357 + 7795 01a4 B3F5805F cmp r3, #4096 + 7796 01a8 42D1 bne .L358 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7797 .loc 1 2949 3 is_stmt 0 discriminator 47 view .LVU2594 + 7798 01aa 0423 movs r3, #4 + 7799 01ac 70E7 b .L302 + 7800 .L320: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7801 .loc 1 2949 3 discriminator 43 view .LVU2595 + 7802 01ae B3F5405F cmp r3, #12288 + 7803 01b2 3FD1 bne .L359 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7804 .loc 1 2949 3 discriminator 49 view .LVU2596 + 7805 01b4 0823 movs r3, #8 + ARM GAS /tmp/ccQxTlMj.s page 268 + + + 7806 01b6 6BE7 b .L302 + 7807 .L382: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7808 .loc 1 2949 3 is_stmt 1 discriminator 50 view .LVU2597 + 7809 01b8 314B ldr r3, .L384+36 + 7810 01ba D3F89030 ldr r3, [r3, #144] + 7811 01be 03F44043 and r3, r3, #49152 + 7812 01c2 B3F5004F cmp r3, #32768 + 7813 01c6 37D0 beq .L361 + 7814 01c8 05D8 bhi .L321 + 7815 01ca BBB3 cbz r3, .L362 + 7816 01cc B3F5804F cmp r3, #16384 + 7817 01d0 36D1 bne .L363 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7818 .loc 1 2949 3 is_stmt 0 discriminator 54 view .LVU2598 + 7819 01d2 0423 movs r3, #4 + 7820 01d4 5CE7 b .L302 + 7821 .L321: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7822 .loc 1 2949 3 discriminator 50 view .LVU2599 + 7823 01d6 B3F5404F cmp r3, #49152 + 7824 01da 33D1 bne .L364 +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7825 .loc 1 2949 3 discriminator 56 view .LVU2600 + 7826 01dc 0823 movs r3, #8 + 7827 01de 57E7 b .L302 + 7828 .L338: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7829 .loc 1 2949 3 discriminator 6 view .LVU2601 + 7830 01e0 0223 movs r3, #2 + 7831 01e2 55E7 b .L302 + 7832 .L339: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7833 .loc 1 2949 3 discriminator 13 view .LVU2602 + 7834 01e4 0223 movs r3, #2 + 7835 01e6 53E7 b .L302 + 7836 .L340: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7837 .loc 1 2949 3 discriminator 20 view .LVU2603 + 7838 01e8 0223 movs r3, #2 + 7839 01ea 51E7 b .L302 + 7840 .L341: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7841 .loc 1 2949 3 discriminator 15 view .LVU2604 + 7842 01ec 0023 movs r3, #0 + 7843 01ee 4FE7 b .L302 + 7844 .L342: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7845 .loc 1 2949 3 discriminator 17 view .LVU2605 + 7846 01f0 1023 movs r3, #16 + 7847 01f2 4DE7 b .L302 + 7848 .L343: + 7849 01f4 1023 movs r3, #16 + 7850 01f6 4BE7 b .L302 + 7851 .L344: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7852 .loc 1 2949 3 discriminator 27 view .LVU2606 + ARM GAS /tmp/ccQxTlMj.s page 269 + + + 7853 01f8 0223 movs r3, #2 + 7854 01fa 49E7 b .L302 + 7855 .L345: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7856 .loc 1 2949 3 discriminator 22 view .LVU2607 + 7857 01fc 0023 movs r3, #0 + 7858 01fe 47E7 b .L302 + 7859 .L346: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7860 .loc 1 2949 3 discriminator 24 view .LVU2608 + 7861 0200 1023 movs r3, #16 + 7862 0202 45E7 b .L302 + 7863 .L347: + 7864 0204 1023 movs r3, #16 + 7865 0206 43E7 b .L302 + 7866 .L348: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7867 .loc 1 2949 3 discriminator 34 view .LVU2609 + 7868 0208 0223 movs r3, #2 + 7869 020a 41E7 b .L302 + 7870 .L349: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7871 .loc 1 2949 3 discriminator 29 view .LVU2610 + 7872 020c 0023 movs r3, #0 + 7873 020e 3FE7 b .L302 + 7874 .L350: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7875 .loc 1 2949 3 discriminator 31 view .LVU2611 + 7876 0210 1023 movs r3, #16 + 7877 0212 3DE7 b .L302 + 7878 .L351: + 7879 0214 1023 movs r3, #16 + 7880 0216 3BE7 b .L302 + 7881 .L352: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7882 .loc 1 2949 3 discriminator 41 view .LVU2612 + 7883 0218 0223 movs r3, #2 + 7884 021a 39E7 b .L302 + 7885 .L353: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7886 .loc 1 2949 3 discriminator 36 view .LVU2613 + 7887 021c 0123 movs r3, #1 + 7888 021e 37E7 b .L302 + 7889 .L354: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7890 .loc 1 2949 3 discriminator 38 view .LVU2614 + 7891 0220 1023 movs r3, #16 + 7892 0222 35E7 b .L302 + 7893 .L355: + 7894 0224 1023 movs r3, #16 + 7895 0226 33E7 b .L302 + 7896 .L356: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7897 .loc 1 2949 3 discriminator 48 view .LVU2615 + 7898 0228 0223 movs r3, #2 + 7899 022a 31E7 b .L302 + 7900 .L357: + ARM GAS /tmp/ccQxTlMj.s page 270 + + +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7901 .loc 1 2949 3 discriminator 43 view .LVU2616 + 7902 022c 0023 movs r3, #0 + 7903 022e 2FE7 b .L302 + 7904 .L358: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7905 .loc 1 2949 3 discriminator 45 view .LVU2617 + 7906 0230 1023 movs r3, #16 + 7907 0232 2DE7 b .L302 + 7908 .L359: + 7909 0234 1023 movs r3, #16 + 7910 0236 2BE7 b .L302 + 7911 .L361: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7912 .loc 1 2949 3 discriminator 55 view .LVU2618 + 7913 0238 0223 movs r3, #2 + 7914 023a 29E7 b .L302 + 7915 .L362: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7916 .loc 1 2949 3 discriminator 50 view .LVU2619 + 7917 023c 0023 movs r3, #0 + 7918 023e 27E7 b .L302 + 7919 .L363: +2949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 7920 .loc 1 2949 3 discriminator 52 view .LVU2620 + 7921 0240 1023 movs r3, #16 + 7922 0242 25E7 b .L302 + 7923 .L364: + 7924 0244 1023 movs r3, #16 + 7925 0246 23E7 b .L302 + 7926 .LVL688: + 7927 .L383: +2953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 7928 .loc 1 2953 5 is_stmt 1 view .LVU2621 + 7929 0248 082B cmp r3, #8 + 7930 024a 5BD8 bhi .L365 + 7931 024c DFE803F0 tbb [pc, r3] + 7932 .L325: + 7933 0250 1A .byte (.L329-.L325)/2 + 7934 0251 34 .byte (.L328-.L325)/2 + 7935 0252 3A .byte (.L366-.L325)/2 + 7936 0253 5A .byte (.L365-.L325)/2 + 7937 0254 37 .byte (.L326-.L325)/2 + 7938 0255 5A .byte (.L365-.L325)/2 + 7939 0256 5A .byte (.L365-.L325)/2 + 7940 0257 5A .byte (.L365-.L325)/2 + 7941 0258 1E .byte (.L327-.L325)/2 + 7942 0259 00 .p2align 1 + 7943 .L385: + 7944 025a 00BF .align 2 + 7945 .L384: + 7946 025c F369FFEF .word -268473869 + 7947 0260 00100140 .word 1073811456 + 7948 0264 00440040 .word 1073759232 + 7949 0268 00480040 .word 1073760256 + 7950 026c 004C0040 .word 1073761280 + 7951 0270 00500040 .word 1073762304 + ARM GAS /tmp/ccQxTlMj.s page 271 + + + 7952 0274 00140140 .word 1073812480 + 7953 0278 00780040 .word 1073772544 + 7954 027c 007C0040 .word 1073773568 + 7955 0280 00380240 .word 1073887232 + 7956 .L329: +2956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 7957 .loc 1 2956 9 view .LVU2622 +2956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 7958 .loc 1 2956 16 is_stmt 0 view .LVU2623 + 7959 0284 FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 7960 .LVL689: +2957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case UART_CLOCKSOURCE_PCLK2: + 7961 .loc 1 2957 9 is_stmt 1 view .LVU2624 + 7962 .L330: +2977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 7963 .loc 1 2977 5 view .LVU2625 +2977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 7964 .loc 1 2977 8 is_stmt 0 view .LVU2626 + 7965 0288 0028 cmp r0, #0 + 7966 028a 3DD0 beq .L367 + 7967 .LVL690: + 7968 .L327: +2979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 7969 .loc 1 2979 7 is_stmt 1 view .LVU2627 +2979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 7970 .loc 1 2979 29 is_stmt 0 view .LVU2628 + 7971 028c 6268 ldr r2, [r4, #4] + 7972 028e 5308 lsrs r3, r2, #1 + 7973 0290 03EB4003 add r3, r3, r0, lsl #1 +2979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 7974 .loc 1 2979 16 view .LVU2629 + 7975 0294 B3FBF2F3 udiv r3, r3, r2 + 7976 .LVL691: +2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 7977 .loc 1 2980 7 is_stmt 1 view .LVU2630 +2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 7978 .loc 1 2980 38 is_stmt 0 view .LVU2631 + 7979 0298 A3F11001 sub r1, r3, #16 +2980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 7980 .loc 1 2980 10 view .LVU2632 + 7981 029c 4FF6EF72 movw r2, #65519 + 7982 02a0 9142 cmp r1, r2 + 7983 02a2 33D8 bhi .L368 +2982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + 7984 .loc 1 2982 9 is_stmt 1 view .LVU2633 +2982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + 7985 .loc 1 2982 19 is_stmt 0 view .LVU2634 + 7986 02a4 9AB2 uxth r2, r3 +2982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + 7987 .loc 1 2982 17 view .LVU2635 + 7988 02a6 22F00F02 bic r2, r2, #15 + 7989 .LVL692: +2983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->BRR = brrtemp; + 7990 .loc 1 2983 9 is_stmt 1 view .LVU2636 +2983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->BRR = brrtemp; + 7991 .loc 1 2983 20 is_stmt 0 view .LVU2637 + 7992 02aa C3F34203 ubfx r3, r3, #1, #3 + ARM GAS /tmp/ccQxTlMj.s page 272 + + + 7993 .LVL693: +2983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->Instance->BRR = brrtemp; + 7994 .loc 1 2983 17 view .LVU2638 + 7995 02ae 1343 orrs r3, r3, r2 + 7996 .LVL694: +2984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 7997 .loc 1 2984 9 is_stmt 1 view .LVU2639 +2984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 7998 .loc 1 2984 14 is_stmt 0 view .LVU2640 + 7999 02b0 2268 ldr r2, [r4] +2984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8000 .loc 1 2984 30 view .LVU2641 + 8001 02b2 D360 str r3, [r2, #12] + 8002 02b4 0020 movs r0, #0 + 8003 02b6 30E0 b .L323 + 8004 .LVL695: + 8005 .L328: +2959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 8006 .loc 1 2959 9 is_stmt 1 view .LVU2642 +2959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 8007 .loc 1 2959 16 is_stmt 0 view .LVU2643 + 8008 02b8 FFF7FEFF bl HAL_RCC_GetPCLK2Freq + 8009 .LVL696: +2960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case UART_CLOCKSOURCE_HSI: + 8010 .loc 1 2960 9 is_stmt 1 view .LVU2644 + 8011 02bc E4E7 b .L330 + 8012 .LVL697: + 8013 .L326: +2965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 8014 .loc 1 2965 9 view .LVU2645 +2965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 8015 .loc 1 2965 16 is_stmt 0 view .LVU2646 + 8016 02be FFF7FEFF bl HAL_RCC_GetSysClockFreq + 8017 .LVL698: +2966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case UART_CLOCKSOURCE_LSE: + 8018 .loc 1 2966 9 is_stmt 1 view .LVU2647 + 8019 02c2 E1E7 b .L330 + 8020 .LVL699: + 8021 .L366: +2962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 8022 .loc 1 2962 14 is_stmt 0 view .LVU2648 + 8023 02c4 1748 ldr r0, .L386 + 8024 02c6 E1E7 b .L327 + 8025 .L334: +2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8026 .loc 1 2994 5 view .LVU2649 + 8027 02c8 1648 ldr r0, .L386 + 8028 02ca 02E0 b .L331 + 8029 .L336: +2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 8030 .loc 1 2997 9 is_stmt 1 view .LVU2650 +2997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 8031 .loc 1 2997 16 is_stmt 0 view .LVU2651 + 8032 02cc FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 8033 .LVL700: +2998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case UART_CLOCKSOURCE_PCLK2: + 8034 .loc 1 2998 9 is_stmt 1 view .LVU2652 + ARM GAS /tmp/ccQxTlMj.s page 273 + + + 8035 .L337: +3017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8036 .loc 1 3017 5 view .LVU2653 +3017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8037 .loc 1 3017 8 is_stmt 0 view .LVU2654 + 8038 02d0 00B3 cbz r0, .L371 + 8039 .LVL701: + 8040 .L331: +3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 8041 .loc 1 3020 7 is_stmt 1 view .LVU2655 +3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 8042 .loc 1 3020 29 is_stmt 0 view .LVU2656 + 8043 02d2 6368 ldr r3, [r4, #4] + 8044 02d4 00EB5300 add r0, r0, r3, lsr #1 +3020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 8045 .loc 1 3020 16 view .LVU2657 + 8046 02d8 B0FBF3F0 udiv r0, r0, r3 + 8047 .LVL702: +3021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8048 .loc 1 3021 7 is_stmt 1 view .LVU2658 +3021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8049 .loc 1 3021 38 is_stmt 0 view .LVU2659 + 8050 02dc A0F11002 sub r2, r0, #16 +3021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8051 .loc 1 3021 10 view .LVU2660 + 8052 02e0 4FF6EF73 movw r3, #65519 + 8053 02e4 9A42 cmp r2, r3 + 8054 02e6 17D8 bhi .L372 +3023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8055 .loc 1 3023 9 is_stmt 1 view .LVU2661 +3023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8056 .loc 1 3023 14 is_stmt 0 view .LVU2662 + 8057 02e8 2368 ldr r3, [r4] + 8058 02ea 80B2 uxth r0, r0 + 8059 .LVL703: +3023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8060 .loc 1 3023 30 view .LVU2663 + 8061 02ec D860 str r0, [r3, #12] + 8062 02ee 0020 movs r0, #0 + 8063 02f0 13E0 b .L323 + 8064 .LVL704: + 8065 .L335: +3000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 8066 .loc 1 3000 9 is_stmt 1 view .LVU2664 +3000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 8067 .loc 1 3000 16 is_stmt 0 view .LVU2665 + 8068 02f2 FFF7FEFF bl HAL_RCC_GetPCLK2Freq + 8069 .LVL705: +3001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case UART_CLOCKSOURCE_HSI: + 8070 .loc 1 3001 9 is_stmt 1 view .LVU2666 + 8071 02f6 EBE7 b .L337 + 8072 .LVL706: + 8073 .L333: +3006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 8074 .loc 1 3006 9 view .LVU2667 +3006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 8075 .loc 1 3006 16 is_stmt 0 view .LVU2668 + ARM GAS /tmp/ccQxTlMj.s page 274 + + + 8076 02f8 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 8077 .LVL707: +3007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** case UART_CLOCKSOURCE_LSE: + 8078 .loc 1 3007 9 is_stmt 1 view .LVU2669 + 8079 02fc E8E7 b .L337 + 8080 .LVL708: + 8081 .L370: +3009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** break; + 8082 .loc 1 3009 14 is_stmt 0 view .LVU2670 + 8083 02fe 4FF40040 mov r0, #32768 + 8084 0302 E6E7 b .L331 + 8085 .L365: +2953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8086 .loc 1 2953 5 view .LVU2671 + 8087 0304 0120 movs r0, #1 + 8088 0306 08E0 b .L323 + 8089 .LVL709: + 8090 .L367: +2953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8091 .loc 1 2953 5 view .LVU2672 + 8092 0308 0020 movs r0, #0 + 8093 .LVL710: +2953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8094 .loc 1 2953 5 view .LVU2673 + 8095 030a 06E0 b .L323 + 8096 .LVL711: + 8097 .L368: +2988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8098 .loc 1 2988 13 view .LVU2674 + 8099 030c 0120 movs r0, #1 + 8100 030e 04E0 b .L323 + 8101 .LVL712: + 8102 .L369: +2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8103 .loc 1 2994 5 view .LVU2675 + 8104 0310 0120 movs r0, #1 + 8105 0312 02E0 b .L323 + 8106 .LVL713: + 8107 .L371: +2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8108 .loc 1 2994 5 view .LVU2676 + 8109 0314 0020 movs r0, #0 + 8110 .LVL714: +2994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8111 .loc 1 2994 5 view .LVU2677 + 8112 0316 00E0 b .L323 + 8113 .LVL715: + 8114 .L372: +3027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8115 .loc 1 3027 13 view .LVU2678 + 8116 0318 0120 movs r0, #1 + 8117 .LVL716: + 8118 .L323: +3034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxISR = NULL; + 8119 .loc 1 3034 3 is_stmt 1 view .LVU2679 +3034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxISR = NULL; + 8120 .loc 1 3034 16 is_stmt 0 view .LVU2680 + ARM GAS /tmp/ccQxTlMj.s page 275 + + + 8121 031a 0023 movs r3, #0 + 8122 031c A366 str r3, [r4, #104] +3035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8123 .loc 1 3035 3 is_stmt 1 view .LVU2681 +3035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8124 .loc 1 3035 16 is_stmt 0 view .LVU2682 + 8125 031e E366 str r3, [r4, #108] +3037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8126 .loc 1 3037 3 is_stmt 1 view .LVU2683 +3038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8127 .loc 1 3038 1 is_stmt 0 view .LVU2684 + 8128 0320 10BD pop {r4, pc} + 8129 .LVL717: + 8130 .L387: +3038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8131 .loc 1 3038 1 view .LVU2685 + 8132 0322 00BF .align 2 + 8133 .L386: + 8134 0324 0024F400 .word 16000000 + 8135 .cfi_endproc + 8136 .LFE185: + 8138 .section .text.UART_AdvFeatureConfig,"ax",%progbits + 8139 .align 1 + 8140 .global UART_AdvFeatureConfig + 8141 .syntax unified + 8142 .thumb + 8143 .thumb_func + 8145 UART_AdvFeatureConfig: + 8146 .LVL718: + 8147 .LFB186: +3046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check whether the set of advanced features to configure is properly set */ + 8148 .loc 1 3046 1 is_stmt 1 view -0 + 8149 .cfi_startproc + 8150 @ args = 0, pretend = 0, frame = 0 + 8151 @ frame_needed = 0, uses_anonymous_args = 0 + 8152 @ link register save eliminated. +3048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8153 .loc 1 3048 3 view .LVU2687 +3051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8154 .loc 1 3051 3 view .LVU2688 +3051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8155 .loc 1 3051 7 is_stmt 0 view .LVU2689 + 8156 0000 436A ldr r3, [r0, #36] +3051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8157 .loc 1 3051 6 view .LVU2690 + 8158 0002 13F0080F tst r3, #8 + 8159 0006 06D0 beq .L389 +3053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + 8160 .loc 1 3053 5 is_stmt 1 view .LVU2691 +3054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8161 .loc 1 3054 5 view .LVU2692 + 8162 0008 0268 ldr r2, [r0] + 8163 000a 5368 ldr r3, [r2, #4] + 8164 000c 23F40043 bic r3, r3, #32768 + 8165 0010 416B ldr r1, [r0, #52] + 8166 0012 0B43 orrs r3, r3, r1 + 8167 0014 5360 str r3, [r2, #4] + ARM GAS /tmp/ccQxTlMj.s page 276 + + + 8168 .L389: +3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8169 .loc 1 3058 3 view .LVU2693 +3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8170 .loc 1 3058 7 is_stmt 0 view .LVU2694 + 8171 0016 436A ldr r3, [r0, #36] +3058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8172 .loc 1 3058 6 view .LVU2695 + 8173 0018 13F0010F tst r3, #1 + 8174 001c 06D0 beq .L390 +3060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + 8175 .loc 1 3060 5 is_stmt 1 view .LVU2696 +3061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8176 .loc 1 3061 5 view .LVU2697 + 8177 001e 0268 ldr r2, [r0] + 8178 0020 5368 ldr r3, [r2, #4] + 8179 0022 23F40033 bic r3, r3, #131072 + 8180 0026 816A ldr r1, [r0, #40] + 8181 0028 0B43 orrs r3, r3, r1 + 8182 002a 5360 str r3, [r2, #4] + 8183 .L390: +3065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8184 .loc 1 3065 3 view .LVU2698 +3065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8185 .loc 1 3065 7 is_stmt 0 view .LVU2699 + 8186 002c 436A ldr r3, [r0, #36] +3065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8187 .loc 1 3065 6 view .LVU2700 + 8188 002e 13F0020F tst r3, #2 + 8189 0032 06D0 beq .L391 +3067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + 8190 .loc 1 3067 5 is_stmt 1 view .LVU2701 +3068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8191 .loc 1 3068 5 view .LVU2702 + 8192 0034 0268 ldr r2, [r0] + 8193 0036 5368 ldr r3, [r2, #4] + 8194 0038 23F48033 bic r3, r3, #65536 + 8195 003c C16A ldr r1, [r0, #44] + 8196 003e 0B43 orrs r3, r3, r1 + 8197 0040 5360 str r3, [r2, #4] + 8198 .L391: +3072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8199 .loc 1 3072 3 view .LVU2703 +3072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8200 .loc 1 3072 7 is_stmt 0 view .LVU2704 + 8201 0042 436A ldr r3, [r0, #36] +3072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8202 .loc 1 3072 6 view .LVU2705 + 8203 0044 13F0040F tst r3, #4 + 8204 0048 06D0 beq .L392 +3074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + 8205 .loc 1 3074 5 is_stmt 1 view .LVU2706 +3075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8206 .loc 1 3075 5 view .LVU2707 + 8207 004a 0268 ldr r2, [r0] + 8208 004c 5368 ldr r3, [r2, #4] + 8209 004e 23F48023 bic r3, r3, #262144 + ARM GAS /tmp/ccQxTlMj.s page 277 + + + 8210 0052 016B ldr r1, [r0, #48] + 8211 0054 0B43 orrs r3, r3, r1 + 8212 0056 5360 str r3, [r2, #4] + 8213 .L392: +3079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8214 .loc 1 3079 3 view .LVU2708 +3079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8215 .loc 1 3079 7 is_stmt 0 view .LVU2709 + 8216 0058 436A ldr r3, [r0, #36] +3079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8217 .loc 1 3079 6 view .LVU2710 + 8218 005a 13F0100F tst r3, #16 + 8219 005e 06D0 beq .L393 +3081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + 8220 .loc 1 3081 5 is_stmt 1 view .LVU2711 +3082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8221 .loc 1 3082 5 view .LVU2712 + 8222 0060 0268 ldr r2, [r0] + 8223 0062 9368 ldr r3, [r2, #8] + 8224 0064 23F48053 bic r3, r3, #4096 + 8225 0068 816B ldr r1, [r0, #56] + 8226 006a 0B43 orrs r3, r3, r1 + 8227 006c 9360 str r3, [r2, #8] + 8228 .L393: +3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8229 .loc 1 3086 3 view .LVU2713 +3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8230 .loc 1 3086 7 is_stmt 0 view .LVU2714 + 8231 006e 436A ldr r3, [r0, #36] +3086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8232 .loc 1 3086 6 view .LVU2715 + 8233 0070 13F0200F tst r3, #32 + 8234 0074 06D0 beq .L394 +3088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + 8235 .loc 1 3088 5 is_stmt 1 view .LVU2716 +3089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8236 .loc 1 3089 5 view .LVU2717 + 8237 0076 0268 ldr r2, [r0] + 8238 0078 9368 ldr r3, [r2, #8] + 8239 007a 23F40053 bic r3, r3, #8192 + 8240 007e C16B ldr r1, [r0, #60] + 8241 0080 0B43 orrs r3, r3, r1 + 8242 0082 9360 str r3, [r2, #8] + 8243 .L394: +3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8244 .loc 1 3093 3 view .LVU2718 +3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8245 .loc 1 3093 7 is_stmt 0 view .LVU2719 + 8246 0084 436A ldr r3, [r0, #36] +3093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8247 .loc 1 3093 6 view .LVU2720 + 8248 0086 13F0400F tst r3, #64 + 8249 008a 0AD0 beq .L395 +3095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + 8250 .loc 1 3095 5 is_stmt 1 view .LVU2721 +3096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + 8251 .loc 1 3096 5 view .LVU2722 + ARM GAS /tmp/ccQxTlMj.s page 278 + + +3097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* set auto Baudrate detection parameters if detection is enabled */ + 8252 .loc 1 3097 5 view .LVU2723 + 8253 008c 0268 ldr r2, [r0] + 8254 008e 5368 ldr r3, [r2, #4] + 8255 0090 23F48013 bic r3, r3, #1048576 + 8256 0094 016C ldr r1, [r0, #64] + 8257 0096 0B43 orrs r3, r3, r1 + 8258 0098 5360 str r3, [r2, #4] +3099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8259 .loc 1 3099 5 view .LVU2724 +3099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8260 .loc 1 3099 28 is_stmt 0 view .LVU2725 + 8261 009a 036C ldr r3, [r0, #64] +3099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8262 .loc 1 3099 8 view .LVU2726 + 8263 009c B3F5801F cmp r3, #1048576 + 8264 00a0 0BD0 beq .L397 + 8265 .L395: +3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8266 .loc 1 3107 3 is_stmt 1 view .LVU2727 +3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8267 .loc 1 3107 7 is_stmt 0 view .LVU2728 + 8268 00a2 436A ldr r3, [r0, #36] +3107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8269 .loc 1 3107 6 view .LVU2729 + 8270 00a4 13F0800F tst r3, #128 + 8271 00a8 06D0 beq .L388 +3109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + 8272 .loc 1 3109 5 is_stmt 1 view .LVU2730 +3110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8273 .loc 1 3110 5 view .LVU2731 + 8274 00aa 0268 ldr r2, [r0] + 8275 00ac 5368 ldr r3, [r2, #4] + 8276 00ae 23F40023 bic r3, r3, #524288 + 8277 00b2 816C ldr r1, [r0, #72] + 8278 00b4 0B43 orrs r3, r3, r1 + 8279 00b6 5360 str r3, [r2, #4] + 8280 .L388: +3112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8281 .loc 1 3112 1 is_stmt 0 view .LVU2732 + 8282 00b8 7047 bx lr + 8283 .L397: +3101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + 8284 .loc 1 3101 7 is_stmt 1 view .LVU2733 +3102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8285 .loc 1 3102 7 view .LVU2734 + 8286 00ba 0268 ldr r2, [r0] + 8287 00bc 5368 ldr r3, [r2, #4] + 8288 00be 23F4C003 bic r3, r3, #6291456 + 8289 00c2 416C ldr r1, [r0, #68] + 8290 00c4 0B43 orrs r3, r3, r1 + 8291 00c6 5360 str r3, [r2, #4] + 8292 00c8 EBE7 b .L395 + 8293 .cfi_endproc + 8294 .LFE186: + 8296 .section .text.UART_WaitOnFlagUntilTimeout,"ax",%progbits + 8297 .align 1 + ARM GAS /tmp/ccQxTlMj.s page 279 + + + 8298 .global UART_WaitOnFlagUntilTimeout + 8299 .syntax unified + 8300 .thumb + 8301 .thumb_func + 8303 UART_WaitOnFlagUntilTimeout: + 8304 .LVL719: + 8305 .LFB188: +3192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Wait until flag is set */ + 8306 .loc 1 3192 1 view -0 + 8307 .cfi_startproc + 8308 @ args = 4, pretend = 0, frame = 0 + 8309 @ frame_needed = 0, uses_anonymous_args = 0 +3192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Wait until flag is set */ + 8310 .loc 1 3192 1 is_stmt 0 view .LVU2736 + 8311 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr} + 8312 .LCFI30: + 8313 .cfi_def_cfa_offset 32 + 8314 .cfi_offset 3, -32 + 8315 .cfi_offset 4, -28 + 8316 .cfi_offset 5, -24 + 8317 .cfi_offset 6, -20 + 8318 .cfi_offset 7, -16 + 8319 .cfi_offset 8, -12 + 8320 .cfi_offset 9, -8 + 8321 .cfi_offset 14, -4 + 8322 0004 0546 mov r5, r0 + 8323 0006 0E46 mov r6, r1 + 8324 0008 1746 mov r7, r2 + 8325 000a 9946 mov r9, r3 + 8326 000c DDF82080 ldr r8, [sp, #32] +3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8327 .loc 1 3194 3 is_stmt 1 view .LVU2737 + 8328 .LVL720: + 8329 .L400: +3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8330 .loc 1 3194 59 view .LVU2738 +3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8331 .loc 1 3194 11 is_stmt 0 view .LVU2739 + 8332 0010 2B68 ldr r3, [r5] + 8333 0012 DC69 ldr r4, [r3, #28] +3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8334 .loc 1 3194 50 view .LVU2740 + 8335 0014 36EA0404 bics r4, r6, r4 + 8336 0018 0CBF ite eq + 8337 001a 0124 moveq r4, #1 + 8338 001c 0024 movne r4, #0 +3194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8339 .loc 1 3194 59 view .LVU2741 + 8340 001e BC42 cmp r4, r7 + 8341 0020 3AD1 bne .L407 +3197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8342 .loc 1 3197 5 is_stmt 1 view .LVU2742 +3197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8343 .loc 1 3197 8 is_stmt 0 view .LVU2743 + 8344 0022 B8F1FF3F cmp r8, #-1 + 8345 0026 F3D0 beq .L400 +3199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + ARM GAS /tmp/ccQxTlMj.s page 280 + + + 8346 .loc 1 3199 7 is_stmt 1 view .LVU2744 +3199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8347 .loc 1 3199 13 is_stmt 0 view .LVU2745 + 8348 0028 FFF7FEFF bl HAL_GetTick + 8349 .LVL721: +3199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8350 .loc 1 3199 27 discriminator 1 view .LVU2746 + 8351 002c A0EB0900 sub r0, r0, r9 +3199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8352 .loc 1 3199 10 discriminator 1 view .LVU2747 + 8353 0030 4045 cmp r0, r8 + 8354 0032 34D8 bhi .L404 +3199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8355 .loc 1 3199 51 discriminator 1 view .LVU2748 + 8356 0034 B8F1000F cmp r8, #0 + 8357 0038 33D0 beq .L405 +3205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8358 .loc 1 3205 7 is_stmt 1 view .LVU2749 +3205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8359 .loc 1 3205 12 is_stmt 0 view .LVU2750 + 8360 003a 2B68 ldr r3, [r5] + 8361 003c 1A68 ldr r2, [r3] +3205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8362 .loc 1 3205 10 view .LVU2751 + 8363 003e 12F0040F tst r2, #4 + 8364 0042 E5D0 beq .L400 +3205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8365 .loc 1 3205 100 discriminator 1 view .LVU2752 + 8366 0044 B6F14002 subs r2, r6, #64 + 8367 0048 18BF it ne + 8368 004a 0122 movne r2, #1 +3205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8369 .loc 1 3205 91 discriminator 1 view .LVU2753 + 8370 004c 802E cmp r6, #128 + 8371 004e DFD0 beq .L400 + 8372 0050 002A cmp r2, #0 + 8373 0052 DDD0 beq .L400 +3207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8374 .loc 1 3207 9 is_stmt 1 view .LVU2754 +3207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8375 .loc 1 3207 13 is_stmt 0 view .LVU2755 + 8376 0054 DA69 ldr r2, [r3, #28] +3207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8377 .loc 1 3207 12 view .LVU2756 + 8378 0056 12F0080F tst r2, #8 + 8379 005a 11D1 bne .L408 +3224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8380 .loc 1 3224 9 is_stmt 1 view .LVU2757 +3224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8381 .loc 1 3224 13 is_stmt 0 view .LVU2758 + 8382 005c DA69 ldr r2, [r3, #28] +3224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8383 .loc 1 3224 12 view .LVU2759 + 8384 005e 12F4006F tst r2, #2048 + 8385 0062 D5D0 beq .L400 +3227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8386 .loc 1 3227 11 is_stmt 1 view .LVU2760 + ARM GAS /tmp/ccQxTlMj.s page 281 + + + 8387 0064 4FF40062 mov r2, #2048 + 8388 0068 1A62 str r2, [r3, #32] +3232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8389 .loc 1 3232 11 view .LVU2761 + 8390 006a 2846 mov r0, r5 + 8391 006c FFF7FEFF bl UART_EndRxTransfer + 8392 .LVL722: +3234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8393 .loc 1 3234 11 view .LVU2762 +3234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8394 .loc 1 3234 28 is_stmt 0 view .LVU2763 + 8395 0070 2023 movs r3, #32 + 8396 0072 C5F88430 str r3, [r5, #132] +3237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8397 .loc 1 3237 11 is_stmt 1 view .LVU2764 +3237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8398 .loc 1 3237 11 view .LVU2765 + 8399 0076 0023 movs r3, #0 + 8400 0078 85F87830 strb r3, [r5, #120] +3237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8401 .loc 1 3237 11 view .LVU2766 +3239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8402 .loc 1 3239 11 view .LVU2767 +3239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8403 .loc 1 3239 18 is_stmt 0 view .LVU2768 + 8404 007c 0320 movs r0, #3 + 8405 007e 0CE0 b .L401 + 8406 .L408: +3210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8407 .loc 1 3210 11 is_stmt 1 view .LVU2769 + 8408 0080 0824 movs r4, #8 + 8409 0082 1C62 str r4, [r3, #32] +3215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8410 .loc 1 3215 11 view .LVU2770 + 8411 0084 2846 mov r0, r5 + 8412 0086 FFF7FEFF bl UART_EndRxTransfer + 8413 .LVL723: +3217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8414 .loc 1 3217 11 view .LVU2771 +3217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8415 .loc 1 3217 28 is_stmt 0 view .LVU2772 + 8416 008a C5F88440 str r4, [r5, #132] +3220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8417 .loc 1 3220 11 is_stmt 1 view .LVU2773 +3220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8418 .loc 1 3220 11 view .LVU2774 + 8419 008e 0023 movs r3, #0 + 8420 0090 85F87830 strb r3, [r5, #120] +3220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8421 .loc 1 3220 11 view .LVU2775 +3222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8422 .loc 1 3222 11 view .LVU2776 +3222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8423 .loc 1 3222 18 is_stmt 0 view .LVU2777 + 8424 0094 0120 movs r0, #1 + 8425 0096 00E0 b .L401 + 8426 .L407: + ARM GAS /tmp/ccQxTlMj.s page 282 + + +3244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8427 .loc 1 3244 10 view .LVU2778 + 8428 0098 0020 movs r0, #0 + 8429 .L401: +3245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8430 .loc 1 3245 1 view .LVU2779 + 8431 009a BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} + 8432 .LVL724: + 8433 .L404: +3202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8434 .loc 1 3202 16 view .LVU2780 + 8435 009e 0320 movs r0, #3 + 8436 00a0 FBE7 b .L401 + 8437 .L405: + 8438 00a2 0320 movs r0, #3 + 8439 00a4 F9E7 b .L401 + 8440 .cfi_endproc + 8441 .LFE188: + 8443 .section .text.HAL_UART_Transmit,"ax",%progbits + 8444 .align 1 + 8445 .global HAL_UART_Transmit + 8446 .syntax unified + 8447 .thumb + 8448 .thumb_func + 8450 HAL_UART_Transmit: + 8451 .LVL725: + 8452 .LFB148: +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const uint8_t *pdata8bits; + 8453 .loc 1 1090 1 is_stmt 1 view -0 + 8454 .cfi_startproc + 8455 @ args = 0, pretend = 0, frame = 0 + 8456 @ frame_needed = 0, uses_anonymous_args = 0 +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const uint8_t *pdata8bits; + 8457 .loc 1 1090 1 is_stmt 0 view .LVU2782 + 8458 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 8459 .LCFI31: + 8460 .cfi_def_cfa_offset 24 + 8461 .cfi_offset 4, -24 + 8462 .cfi_offset 5, -20 + 8463 .cfi_offset 6, -16 + 8464 .cfi_offset 7, -12 + 8465 .cfi_offset 8, -8 + 8466 .cfi_offset 14, -4 + 8467 0004 82B0 sub sp, sp, #8 + 8468 .LCFI32: + 8469 .cfi_def_cfa_offset 32 + 8470 0006 1E46 mov r6, r3 +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** const uint16_t *pdata16bits; + 8471 .loc 1 1091 3 is_stmt 1 view .LVU2783 +1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t tickstart; + 8472 .loc 1 1092 3 view .LVU2784 +1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8473 .loc 1 1093 3 view .LVU2785 +1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8474 .loc 1 1096 3 view .LVU2786 +1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8475 .loc 1 1096 12 is_stmt 0 view .LVU2787 + ARM GAS /tmp/ccQxTlMj.s page 283 + + + 8476 0008 C36F ldr r3, [r0, #124] + 8477 .LVL726: +1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8478 .loc 1 1096 6 view .LVU2788 + 8479 000a 202B cmp r3, #32 + 8480 000c 57D1 bne .L418 + 8481 000e 0446 mov r4, r0 + 8482 0010 0D46 mov r5, r1 + 8483 0012 9046 mov r8, r2 +1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8484 .loc 1 1098 5 is_stmt 1 view .LVU2789 +1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8485 .loc 1 1098 8 is_stmt 0 view .LVU2790 + 8486 0014 002A cmp r2, #0 + 8487 0016 18BF it ne + 8488 0018 0029 cmpne r1, #0 + 8489 001a 01D1 bne .L423 +1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8490 .loc 1 1100 15 view .LVU2791 + 8491 001c 0120 movs r0, #1 + 8492 .LVL727: +1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8493 .loc 1 1100 15 view .LVU2792 + 8494 001e 4FE0 b .L410 + 8495 .LVL728: + 8496 .L423: +1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; + 8497 .loc 1 1103 5 is_stmt 1 view .LVU2793 +1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->gState = HAL_UART_STATE_BUSY_TX; + 8498 .loc 1 1103 22 is_stmt 0 view .LVU2794 + 8499 0020 0023 movs r3, #0 + 8500 0022 C0F88430 str r3, [r0, #132] +1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8501 .loc 1 1104 5 is_stmt 1 view .LVU2795 +1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8502 .loc 1 1104 19 is_stmt 0 view .LVU2796 + 8503 0026 2123 movs r3, #33 + 8504 0028 C367 str r3, [r0, #124] +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8505 .loc 1 1107 5 is_stmt 1 view .LVU2797 +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8506 .loc 1 1107 17 is_stmt 0 view .LVU2798 + 8507 002a FFF7FEFF bl HAL_GetTick + 8508 .LVL729: +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8509 .loc 1 1107 17 view .LVU2799 + 8510 002e 0746 mov r7, r0 + 8511 .LVL730: +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = Size; + 8512 .loc 1 1109 5 is_stmt 1 view .LVU2800 +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->TxXferCount = Size; + 8513 .loc 1 1109 24 is_stmt 0 view .LVU2801 + 8514 0030 A4F85080 strh r8, [r4, #80] @ movhi +1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8515 .loc 1 1110 5 is_stmt 1 view .LVU2802 +1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8516 .loc 1 1110 24 is_stmt 0 view .LVU2803 + ARM GAS /tmp/ccQxTlMj.s page 284 + + + 8517 0034 A4F85280 strh r8, [r4, #82] @ movhi +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8518 .loc 1 1113 5 is_stmt 1 view .LVU2804 +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8519 .loc 1 1113 21 is_stmt 0 view .LVU2805 + 8520 0038 A368 ldr r3, [r4, #8] +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8521 .loc 1 1113 8 view .LVU2806 + 8522 003a B3F5805F cmp r3, #4096 + 8523 003e 02D0 beq .L424 +1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8524 .loc 1 1121 19 view .LVU2807 + 8525 0040 4FF00008 mov r8, #0 + 8526 .LVL731: +1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8527 .loc 1 1121 19 view .LVU2808 + 8528 0044 15E0 b .L415 + 8529 .L424: +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8530 .loc 1 1113 71 discriminator 1 view .LVU2809 + 8531 0046 2369 ldr r3, [r4, #16] +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8532 .loc 1 1113 56 discriminator 1 view .LVU2810 + 8533 0048 3BB3 cbz r3, .L421 +1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8534 .loc 1 1121 19 view .LVU2811 + 8535 004a 4FF00008 mov r8, #0 + 8536 004e 10E0 b .L415 + 8537 .LVL732: + 8538 .L426: +1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8539 .loc 1 1129 9 is_stmt 1 view .LVU2812 +1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8540 .loc 1 1129 23 is_stmt 0 view .LVU2813 + 8541 0050 2023 movs r3, #32 + 8542 0052 E367 str r3, [r4, #124] +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8543 .loc 1 1131 9 is_stmt 1 view .LVU2814 +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8544 .loc 1 1131 16 is_stmt 0 view .LVU2815 + 8545 0054 0320 movs r0, #3 + 8546 0056 33E0 b .L410 + 8547 .L427: +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits++; + 8548 .loc 1 1135 9 is_stmt 1 view .LVU2816 +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits++; + 8549 .loc 1 1135 43 is_stmt 0 view .LVU2817 + 8550 0058 38F8023B ldrh r3, [r8], #2 + 8551 .LVL733: +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits++; + 8552 .loc 1 1135 14 view .LVU2818 + 8553 005c 2268 ldr r2, [r4] +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits++; + 8554 .loc 1 1135 32 view .LVU2819 + 8555 005e C3F30803 ubfx r3, r3, #0, #9 +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits++; + 8556 .loc 1 1135 30 view .LVU2820 + ARM GAS /tmp/ccQxTlMj.s page 285 + + + 8557 0062 9362 str r3, [r2, #40] +1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8558 .loc 1 1136 9 is_stmt 1 view .LVU2821 + 8559 .LVL734: + 8560 .L414: +1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8561 .loc 1 1143 7 view .LVU2822 +1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8562 .loc 1 1143 12 is_stmt 0 view .LVU2823 + 8563 0064 B4F85220 ldrh r2, [r4, #82] + 8564 0068 92B2 uxth r2, r2 +1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8565 .loc 1 1143 25 view .LVU2824 + 8566 006a 013A subs r2, r2, #1 + 8567 006c 92B2 uxth r2, r2 + 8568 006e A4F85220 strh r2, [r4, #82] @ movhi + 8569 .LVL735: + 8570 .L415: +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8571 .loc 1 1124 31 is_stmt 1 view .LVU2825 +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8572 .loc 1 1124 17 is_stmt 0 view .LVU2826 + 8573 0072 B4F85230 ldrh r3, [r4, #82] + 8574 0076 9BB2 uxth r3, r3 +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8575 .loc 1 1124 31 view .LVU2827 + 8576 0078 93B1 cbz r3, .L425 +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8577 .loc 1 1126 7 is_stmt 1 view .LVU2828 +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8578 .loc 1 1126 11 is_stmt 0 view .LVU2829 + 8579 007a 0096 str r6, [sp] + 8580 007c 3B46 mov r3, r7 + 8581 007e 0022 movs r2, #0 + 8582 0080 8021 movs r1, #128 + 8583 0082 2046 mov r0, r4 + 8584 0084 FFF7FEFF bl UART_WaitOnFlagUntilTimeout + 8585 .LVL736: +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8586 .loc 1 1126 10 discriminator 1 view .LVU2830 + 8587 0088 0028 cmp r0, #0 + 8588 008a E1D1 bne .L426 +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8589 .loc 1 1133 7 is_stmt 1 view .LVU2831 +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8590 .loc 1 1133 10 is_stmt 0 view .LVU2832 + 8591 008c 002D cmp r5, #0 + 8592 008e E3D0 beq .L427 +1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata8bits++; + 8593 .loc 1 1140 9 is_stmt 1 view .LVU2833 +1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata8bits++; + 8594 .loc 1 1140 42 is_stmt 0 view .LVU2834 + 8595 0090 15F8012B ldrb r2, [r5], #1 @ zero_extendqisi2 + 8596 .LVL737: +1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata8bits++; + 8597 .loc 1 1140 14 view .LVU2835 + 8598 0094 2368 ldr r3, [r4] + ARM GAS /tmp/ccQxTlMj.s page 286 + + +1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata8bits++; + 8599 .loc 1 1140 30 view .LVU2836 + 8600 0096 9A62 str r2, [r3, #40] +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8601 .loc 1 1141 9 is_stmt 1 view .LVU2837 + 8602 .LVL738: +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8603 .loc 1 1141 9 is_stmt 0 view .LVU2838 + 8604 0098 E4E7 b .L414 + 8605 .LVL739: + 8606 .L421: +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8607 .loc 1 1116 19 view .LVU2839 + 8608 009a A846 mov r8, r5 +1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits = (const uint16_t *) pData; + 8609 .loc 1 1115 19 view .LVU2840 + 8610 009c 0025 movs r5, #0 + 8611 .LVL740: +1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits = (const uint16_t *) pData; + 8612 .loc 1 1115 19 view .LVU2841 + 8613 009e E8E7 b .L415 + 8614 .LVL741: + 8615 .L425: +1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8616 .loc 1 1146 5 is_stmt 1 view .LVU2842 +1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8617 .loc 1 1146 9 is_stmt 0 view .LVU2843 + 8618 00a0 0096 str r6, [sp] + 8619 00a2 3B46 mov r3, r7 + 8620 00a4 0022 movs r2, #0 + 8621 00a6 4021 movs r1, #64 + 8622 00a8 2046 mov r0, r4 + 8623 00aa FFF7FEFF bl UART_WaitOnFlagUntilTimeout + 8624 .LVL742: +1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8625 .loc 1 1146 8 discriminator 1 view .LVU2844 + 8626 00ae 10B9 cbnz r0, .L428 +1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8627 .loc 1 1154 5 is_stmt 1 view .LVU2845 +1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8628 .loc 1 1154 19 is_stmt 0 view .LVU2846 + 8629 00b0 2023 movs r3, #32 + 8630 00b2 E367 str r3, [r4, #124] +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8631 .loc 1 1156 5 is_stmt 1 view .LVU2847 +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8632 .loc 1 1156 12 is_stmt 0 view .LVU2848 + 8633 00b4 04E0 b .L410 + 8634 .L428: +1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8635 .loc 1 1148 7 is_stmt 1 view .LVU2849 +1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8636 .loc 1 1148 21 is_stmt 0 view .LVU2850 + 8637 00b6 2023 movs r3, #32 + 8638 00b8 E367 str r3, [r4, #124] +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8639 .loc 1 1150 7 is_stmt 1 view .LVU2851 + ARM GAS /tmp/ccQxTlMj.s page 287 + + +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8640 .loc 1 1150 14 is_stmt 0 view .LVU2852 + 8641 00ba 0320 movs r0, #3 + 8642 00bc 00E0 b .L410 + 8643 .LVL743: + 8644 .L418: +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8645 .loc 1 1160 12 view .LVU2853 + 8646 00be 0220 movs r0, #2 + 8647 .LVL744: + 8648 .L410: +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8649 .loc 1 1162 1 view .LVU2854 + 8650 00c0 02B0 add sp, sp, #8 + 8651 .LCFI33: + 8652 .cfi_def_cfa_offset 24 + 8653 @ sp needed + 8654 00c2 BDE8F081 pop {r4, r5, r6, r7, r8, pc} +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8655 .loc 1 1162 1 view .LVU2855 + 8656 .cfi_endproc + 8657 .LFE148: + 8659 .section .text.HAL_UART_Receive,"ax",%progbits + 8660 .align 1 + 8661 .global HAL_UART_Receive + 8662 .syntax unified + 8663 .thumb + 8664 .thumb_func + 8666 HAL_UART_Receive: + 8667 .LVL745: + 8668 .LFB149: +1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint8_t *pdata8bits; + 8669 .loc 1 1176 1 is_stmt 1 view -0 + 8670 .cfi_startproc + 8671 @ args = 0, pretend = 0, frame = 0 + 8672 @ frame_needed = 0, uses_anonymous_args = 0 +1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint8_t *pdata8bits; + 8673 .loc 1 1176 1 is_stmt 0 view .LVU2857 + 8674 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 8675 .LCFI34: + 8676 .cfi_def_cfa_offset 28 + 8677 .cfi_offset 4, -28 + 8678 .cfi_offset 5, -24 + 8679 .cfi_offset 6, -20 + 8680 .cfi_offset 7, -16 + 8681 .cfi_offset 8, -12 + 8682 .cfi_offset 9, -8 + 8683 .cfi_offset 14, -4 + 8684 0004 83B0 sub sp, sp, #12 + 8685 .LCFI35: + 8686 .cfi_def_cfa_offset 40 + 8687 0006 1E46 mov r6, r3 +1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint16_t *pdata16bits; + 8688 .loc 1 1177 3 is_stmt 1 view .LVU2858 +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint16_t uhMask; + 8689 .loc 1 1178 3 view .LVU2859 +1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t tickstart; + ARM GAS /tmp/ccQxTlMj.s page 288 + + + 8690 .loc 1 1179 3 view .LVU2860 +1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8691 .loc 1 1180 3 view .LVU2861 +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8692 .loc 1 1183 3 view .LVU2862 +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8693 .loc 1 1183 12 is_stmt 0 view .LVU2863 + 8694 0008 D0F88030 ldr r3, [r0, #128] + 8695 .LVL746: +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8696 .loc 1 1183 6 view .LVU2864 + 8697 000c 202B cmp r3, #32 + 8698 000e 7ED1 bne .L444 + 8699 0010 0446 mov r4, r0 + 8700 0012 0D46 mov r5, r1 + 8701 0014 9046 mov r8, r2 +1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8702 .loc 1 1185 5 is_stmt 1 view .LVU2865 +1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8703 .loc 1 1185 8 is_stmt 0 view .LVU2866 + 8704 0016 002A cmp r2, #0 + 8705 0018 18BF it ne + 8706 001a 0029 cmpne r1, #0 + 8707 001c 01D1 bne .L449 +1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8708 .loc 1 1187 15 view .LVU2867 + 8709 001e 0120 movs r0, #1 + 8710 .LVL747: +1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8711 .loc 1 1187 15 view .LVU2868 + 8712 0020 76E0 b .L430 + 8713 .LVL748: + 8714 .L449: +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 8715 .loc 1 1190 5 is_stmt 1 view .LVU2869 +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 8716 .loc 1 1190 22 is_stmt 0 view .LVU2870 + 8717 0022 0023 movs r3, #0 + 8718 0024 C0F88430 str r3, [r0, #132] +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8719 .loc 1 1191 5 is_stmt 1 view .LVU2871 +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8720 .loc 1 1191 20 is_stmt 0 view .LVU2872 + 8721 0028 2222 movs r2, #34 + 8722 .LVL749: +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8723 .loc 1 1191 20 view .LVU2873 + 8724 002a C0F88020 str r2, [r0, #128] +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8725 .loc 1 1192 5 is_stmt 1 view .LVU2874 +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8726 .loc 1 1192 26 is_stmt 0 view .LVU2875 + 8727 002e 0366 str r3, [r0, #96] +1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8728 .loc 1 1195 5 is_stmt 1 view .LVU2876 +1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8729 .loc 1 1195 17 is_stmt 0 view .LVU2877 + ARM GAS /tmp/ccQxTlMj.s page 289 + + + 8730 0030 FFF7FEFF bl HAL_GetTick + 8731 .LVL750: +1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8732 .loc 1 1195 17 view .LVU2878 + 8733 0034 0746 mov r7, r0 + 8734 .LVL751: +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = Size; + 8735 .loc 1 1197 5 is_stmt 1 view .LVU2879 +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = Size; + 8736 .loc 1 1197 24 is_stmt 0 view .LVU2880 + 8737 0036 A4F85880 strh r8, [r4, #88] @ movhi +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8738 .loc 1 1198 5 is_stmt 1 view .LVU2881 +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8739 .loc 1 1198 24 is_stmt 0 view .LVU2882 + 8740 003a A4F85A80 strh r8, [r4, #90] @ movhi +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uhMask = huart->Mask; + 8741 .loc 1 1201 5 is_stmt 1 view .LVU2883 +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uhMask = huart->Mask; + 8742 .loc 1 1201 5 view .LVU2884 + 8743 003e A368 ldr r3, [r4, #8] + 8744 0040 B3F5805F cmp r3, #4096 + 8745 0044 06D0 beq .L450 +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uhMask = huart->Mask; + 8746 .loc 1 1201 5 discriminator 2 view .LVU2885 + 8747 0046 A3B9 cbnz r3, .L434 +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uhMask = huart->Mask; + 8748 .loc 1 1201 5 discriminator 5 view .LVU2886 + 8749 0048 2269 ldr r2, [r4, #16] + 8750 004a 72B9 cbnz r2, .L435 +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uhMask = huart->Mask; + 8751 .loc 1 1201 5 discriminator 7 view .LVU2887 + 8752 004c FF22 movs r2, #255 + 8753 004e A4F85C20 strh r2, [r4, #92] @ movhi + 8754 0052 14E0 b .L433 + 8755 .L450: +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uhMask = huart->Mask; + 8756 .loc 1 1201 5 discriminator 1 view .LVU2888 + 8757 0054 2269 ldr r2, [r4, #16] + 8758 0056 22B9 cbnz r2, .L432 +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uhMask = huart->Mask; + 8759 .loc 1 1201 5 discriminator 3 view .LVU2889 + 8760 0058 40F2FF12 movw r2, #511 + 8761 005c A4F85C20 strh r2, [r4, #92] @ movhi + 8762 0060 0DE0 b .L433 + 8763 .L432: +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uhMask = huart->Mask; + 8764 .loc 1 1201 5 discriminator 4 view .LVU2890 + 8765 0062 FF22 movs r2, #255 + 8766 0064 A4F85C20 strh r2, [r4, #92] @ movhi + 8767 0068 09E0 b .L433 + 8768 .L435: +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uhMask = huart->Mask; + 8769 .loc 1 1201 5 discriminator 8 view .LVU2891 + 8770 006a 7F22 movs r2, #127 + 8771 006c A4F85C20 strh r2, [r4, #92] @ movhi + 8772 0070 05E0 b .L433 + ARM GAS /tmp/ccQxTlMj.s page 290 + + + 8773 .L434: +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uhMask = huart->Mask; + 8774 .loc 1 1201 5 discriminator 6 view .LVU2892 + 8775 0072 B3F1805F cmp r3, #268435456 + 8776 0076 0AD0 beq .L451 +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uhMask = huart->Mask; + 8777 .loc 1 1201 5 discriminator 10 view .LVU2893 + 8778 0078 0022 movs r2, #0 + 8779 007a A4F85C20 strh r2, [r4, #92] @ movhi + 8780 .L433: +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uhMask = huart->Mask; + 8781 .loc 1 1201 5 discriminator 13 view .LVU2894 +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8782 .loc 1 1202 5 view .LVU2895 +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8783 .loc 1 1202 12 is_stmt 0 view .LVU2896 + 8784 007e B4F85C80 ldrh r8, [r4, #92] + 8785 .LVL752: +1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8786 .loc 1 1205 5 is_stmt 1 view .LVU2897 +1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8787 .loc 1 1205 8 is_stmt 0 view .LVU2898 + 8788 0082 B3F5805F cmp r3, #4096 + 8789 0086 0CD0 beq .L452 +1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8790 .loc 1 1213 19 view .LVU2899 + 8791 0088 4FF00009 mov r9, #0 + 8792 008c 24E0 b .L439 + 8793 .LVL753: + 8794 .L451: +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uhMask = huart->Mask; + 8795 .loc 1 1201 5 is_stmt 1 discriminator 9 view .LVU2900 + 8796 008e 2269 ldr r2, [r4, #16] + 8797 0090 1AB9 cbnz r2, .L437 +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uhMask = huart->Mask; + 8798 .loc 1 1201 5 discriminator 11 view .LVU2901 + 8799 0092 7F22 movs r2, #127 + 8800 0094 A4F85C20 strh r2, [r4, #92] @ movhi + 8801 0098 F1E7 b .L433 + 8802 .L437: +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uhMask = huart->Mask; + 8803 .loc 1 1201 5 discriminator 12 view .LVU2902 + 8804 009a 3F22 movs r2, #63 + 8805 009c A4F85C20 strh r2, [r4, #92] @ movhi + 8806 00a0 EDE7 b .L433 + 8807 .LVL754: + 8808 .L452: +1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8809 .loc 1 1205 71 is_stmt 0 discriminator 1 view .LVU2903 + 8810 00a2 2369 ldr r3, [r4, #16] +1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8811 .loc 1 1205 56 discriminator 1 view .LVU2904 + 8812 00a4 13B1 cbz r3, .L447 +1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8813 .loc 1 1213 19 view .LVU2905 + 8814 00a6 4FF00009 mov r9, #0 + 8815 00aa 15E0 b .L439 + ARM GAS /tmp/ccQxTlMj.s page 291 + + + 8816 .L447: +1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8817 .loc 1 1208 19 view .LVU2906 + 8818 00ac A946 mov r9, r5 +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits = (uint16_t *) pData; + 8819 .loc 1 1207 19 view .LVU2907 + 8820 00ae 0025 movs r5, #0 + 8821 .LVL755: +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits = (uint16_t *) pData; + 8822 .loc 1 1207 19 view .LVU2908 + 8823 00b0 12E0 b .L439 + 8824 .LVL756: + 8825 .L454: +1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8826 .loc 1 1221 9 is_stmt 1 view .LVU2909 +1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8827 .loc 1 1221 24 is_stmt 0 view .LVU2910 + 8828 00b2 2023 movs r3, #32 + 8829 00b4 C4F88030 str r3, [r4, #128] +1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8830 .loc 1 1223 9 is_stmt 1 view .LVU2911 +1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8831 .loc 1 1223 16 is_stmt 0 view .LVU2912 + 8832 00b8 0320 movs r0, #3 + 8833 00ba 29E0 b .L430 + 8834 .L441: +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata8bits++; + 8835 .loc 1 1232 9 is_stmt 1 view .LVU2913 +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata8bits++; + 8836 .loc 1 1232 38 is_stmt 0 view .LVU2914 + 8837 00bc 2368 ldr r3, [r4] +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata8bits++; + 8838 .loc 1 1232 48 view .LVU2915 + 8839 00be 5A6A ldr r2, [r3, #36] +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata8bits++; + 8840 .loc 1 1232 56 view .LVU2916 + 8841 00c0 5FFA88F3 uxtb r3, r8 +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata8bits++; + 8842 .loc 1 1232 23 view .LVU2917 + 8843 00c4 1340 ands r3, r3, r2 +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata8bits++; + 8844 .loc 1 1232 21 view .LVU2918 + 8845 00c6 05F8013B strb r3, [r5], #1 + 8846 .LVL757: +1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8847 .loc 1 1233 9 is_stmt 1 view .LVU2919 + 8848 .L442: +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8849 .loc 1 1235 7 view .LVU2920 +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8850 .loc 1 1235 12 is_stmt 0 view .LVU2921 + 8851 00ca B4F85A20 ldrh r2, [r4, #90] + 8852 00ce 92B2 uxth r2, r2 +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8853 .loc 1 1235 25 view .LVU2922 + 8854 00d0 013A subs r2, r2, #1 + 8855 00d2 92B2 uxth r2, r2 + ARM GAS /tmp/ccQxTlMj.s page 292 + + + 8856 00d4 A4F85A20 strh r2, [r4, #90] @ movhi + 8857 .LVL758: + 8858 .L439: +1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8859 .loc 1 1217 31 is_stmt 1 view .LVU2923 +1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8860 .loc 1 1217 17 is_stmt 0 view .LVU2924 + 8861 00d8 B4F85A30 ldrh r3, [r4, #90] + 8862 00dc 9BB2 uxth r3, r3 +1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8863 .loc 1 1217 31 view .LVU2925 + 8864 00de 8BB1 cbz r3, .L453 +1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8865 .loc 1 1219 7 is_stmt 1 view .LVU2926 +1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8866 .loc 1 1219 11 is_stmt 0 view .LVU2927 + 8867 00e0 0096 str r6, [sp] + 8868 00e2 3B46 mov r3, r7 + 8869 00e4 0022 movs r2, #0 + 8870 00e6 2021 movs r1, #32 + 8871 00e8 2046 mov r0, r4 + 8872 00ea FFF7FEFF bl UART_WaitOnFlagUntilTimeout + 8873 .LVL759: +1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8874 .loc 1 1219 10 discriminator 1 view .LVU2928 + 8875 00ee 0028 cmp r0, #0 + 8876 00f0 DFD1 bne .L454 +1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8877 .loc 1 1225 7 is_stmt 1 view .LVU2929 +1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8878 .loc 1 1225 10 is_stmt 0 view .LVU2930 + 8879 00f2 002D cmp r5, #0 + 8880 00f4 E2D1 bne .L441 +1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits++; + 8881 .loc 1 1227 9 is_stmt 1 view .LVU2931 +1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits++; + 8882 .loc 1 1227 40 is_stmt 0 view .LVU2932 + 8883 00f6 2368 ldr r3, [r4] +1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits++; + 8884 .loc 1 1227 50 view .LVU2933 + 8885 00f8 5B6A ldr r3, [r3, #36] +1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits++; + 8886 .loc 1 1227 24 view .LVU2934 + 8887 00fa 08EA0303 and r3, r8, r3 +1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** pdata16bits++; + 8888 .loc 1 1227 22 view .LVU2935 + 8889 00fe 29F8023B strh r3, [r9], #2 @ movhi + 8890 .LVL760: +1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8891 .loc 1 1228 9 is_stmt 1 view .LVU2936 +1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8892 .loc 1 1228 9 is_stmt 0 view .LVU2937 + 8893 0102 E2E7 b .L442 + 8894 .L453: +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8895 .loc 1 1239 5 is_stmt 1 view .LVU2938 +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 293 + + + 8896 .loc 1 1239 20 is_stmt 0 view .LVU2939 + 8897 0104 2023 movs r3, #32 + 8898 0106 C4F88030 str r3, [r4, #128] +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8899 .loc 1 1241 5 is_stmt 1 view .LVU2940 +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8900 .loc 1 1241 12 is_stmt 0 view .LVU2941 + 8901 010a 0020 movs r0, #0 + 8902 010c 00E0 b .L430 + 8903 .LVL761: + 8904 .L444: +1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8905 .loc 1 1245 12 view .LVU2942 + 8906 010e 0220 movs r0, #2 + 8907 .LVL762: + 8908 .L430: +1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8909 .loc 1 1247 1 view .LVU2943 + 8910 0110 03B0 add sp, sp, #12 + 8911 .LCFI36: + 8912 .cfi_def_cfa_offset 28 + 8913 @ sp needed + 8914 0112 BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} +1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8915 .loc 1 1247 1 view .LVU2944 + 8916 .cfi_endproc + 8917 .LFE149: + 8919 .section .text.UART_CheckIdleState,"ax",%progbits + 8920 .align 1 + 8921 .global UART_CheckIdleState + 8922 .syntax unified + 8923 .thumb + 8924 .thumb_func + 8926 UART_CheckIdleState: + 8927 .LVL763: + 8928 .LFB187: +3120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t tickstart; + 8929 .loc 1 3120 1 is_stmt 1 view -0 + 8930 .cfi_startproc + 8931 @ args = 0, pretend = 0, frame = 0 + 8932 @ frame_needed = 0, uses_anonymous_args = 0 +3120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** uint32_t tickstart; + 8933 .loc 1 3120 1 is_stmt 0 view .LVU2946 + 8934 0000 30B5 push {r4, r5, lr} + 8935 .LCFI37: + 8936 .cfi_def_cfa_offset 12 + 8937 .cfi_offset 4, -12 + 8938 .cfi_offset 5, -8 + 8939 .cfi_offset 14, -4 + 8940 0002 83B0 sub sp, sp, #12 + 8941 .LCFI38: + 8942 .cfi_def_cfa_offset 24 + 8943 0004 0446 mov r4, r0 +3121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8944 .loc 1 3121 3 is_stmt 1 view .LVU2947 +3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8945 .loc 1 3124 3 view .LVU2948 + ARM GAS /tmp/ccQxTlMj.s page 294 + + +3124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8946 .loc 1 3124 20 is_stmt 0 view .LVU2949 + 8947 0006 0023 movs r3, #0 + 8948 0008 C0F88430 str r3, [r0, #132] +3127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8949 .loc 1 3127 3 is_stmt 1 view .LVU2950 +3127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8950 .loc 1 3127 15 is_stmt 0 view .LVU2951 + 8951 000c FFF7FEFF bl HAL_GetTick + 8952 .LVL764: +3127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8953 .loc 1 3127 15 view .LVU2952 + 8954 0010 0546 mov r5, r0 + 8955 .LVL765: +3130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8956 .loc 1 3130 3 is_stmt 1 view .LVU2953 +3130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8957 .loc 1 3130 13 is_stmt 0 view .LVU2954 + 8958 0012 2268 ldr r2, [r4] +3130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8959 .loc 1 3130 23 view .LVU2955 + 8960 0014 1268 ldr r2, [r2] +3130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8961 .loc 1 3130 6 view .LVU2956 + 8962 0016 12F0080F tst r2, #8 + 8963 001a 0FD1 bne .L463 + 8964 .LVL766: + 8965 .L456: +3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8966 .loc 1 3149 3 is_stmt 1 view .LVU2957 +3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8967 .loc 1 3149 13 is_stmt 0 view .LVU2958 + 8968 001c 2368 ldr r3, [r4] +3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8969 .loc 1 3149 23 view .LVU2959 + 8970 001e 1B68 ldr r3, [r3] +3149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 8971 .loc 1 3149 6 view .LVU2960 + 8972 0020 13F0040F tst r3, #4 + 8973 0024 26D1 bne .L464 + 8974 .L459: +3170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 8975 .loc 1 3170 3 is_stmt 1 view .LVU2961 +3170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_READY; + 8976 .loc 1 3170 17 is_stmt 0 view .LVU2962 + 8977 0026 2023 movs r3, #32 + 8978 0028 E367 str r3, [r4, #124] +3171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8979 .loc 1 3171 3 is_stmt 1 view .LVU2963 +3171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8980 .loc 1 3171 18 is_stmt 0 view .LVU2964 + 8981 002a C4F88030 str r3, [r4, #128] +3172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; + 8982 .loc 1 3172 3 is_stmt 1 view .LVU2965 +3172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; + 8983 .loc 1 3172 24 is_stmt 0 view .LVU2966 + 8984 002e 0020 movs r0, #0 + ARM GAS /tmp/ccQxTlMj.s page 295 + + + 8985 0030 2066 str r0, [r4, #96] +3173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8986 .loc 1 3173 3 is_stmt 1 view .LVU2967 +3173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8987 .loc 1 3173 22 is_stmt 0 view .LVU2968 + 8988 0032 6066 str r0, [r4, #100] +3175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8989 .loc 1 3175 3 is_stmt 1 view .LVU2969 +3175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8990 .loc 1 3175 3 view .LVU2970 + 8991 0034 84F87800 strb r0, [r4, #120] +3175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8992 .loc 1 3175 3 view .LVU2971 +3177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 8993 .loc 1 3177 3 view .LVU2972 + 8994 .L458: +3178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 8995 .loc 1 3178 1 is_stmt 0 view .LVU2973 + 8996 0038 03B0 add sp, sp, #12 + 8997 .LCFI39: + 8998 .cfi_remember_state + 8999 .cfi_def_cfa_offset 12 + 9000 @ sp needed + 9001 003a 30BD pop {r4, r5, pc} + 9002 .LVL767: + 9003 .L463: + 9004 .LCFI40: + 9005 .cfi_restore_state +3133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9006 .loc 1 3133 5 is_stmt 1 view .LVU2974 +3133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9007 .loc 1 3133 9 is_stmt 0 view .LVU2975 + 9008 003c 6FF07E43 mvn r3, #-33554432 + 9009 0040 0093 str r3, [sp] + 9010 0042 0346 mov r3, r0 + 9011 0044 0022 movs r2, #0 + 9012 0046 4FF40011 mov r1, #2097152 + 9013 004a 2046 mov r0, r4 + 9014 .LVL768: +3133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9015 .loc 1 3133 9 view .LVU2976 + 9016 004c FFF7FEFF bl UART_WaitOnFlagUntilTimeout + 9017 .LVL769: +3133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9018 .loc 1 3133 8 discriminator 1 view .LVU2977 + 9019 0050 0028 cmp r0, #0 + 9020 0052 E3D0 beq .L456 + 9021 .L457: +3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9022 .loc 1 3136 7 is_stmt 1 discriminator 1 view .LVU2978 + 9023 .LBB762: +3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9024 .loc 1 3136 7 discriminator 1 view .LVU2979 +3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9025 .loc 1 3136 7 discriminator 1 view .LVU2980 +3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9026 .loc 1 3136 7 discriminator 1 view .LVU2981 + ARM GAS /tmp/ccQxTlMj.s page 296 + + + 9027 0054 2268 ldr r2, [r4] + 9028 .LVL770: + 9029 .LBB763: + 9030 .LBI763: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 9031 .loc 2 1068 31 view .LVU2982 + 9032 .LBB764: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9033 .loc 2 1070 5 view .LVU2983 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 9034 .loc 2 1072 4 view .LVU2984 + 9035 .syntax unified + 9036 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 9037 0056 52E8003F ldrex r3, [r2] + 9038 @ 0 "" 2 + 9039 .LVL771: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 9040 .loc 2 1073 4 view .LVU2985 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 9041 .loc 2 1073 4 is_stmt 0 view .LVU2986 + 9042 .thumb + 9043 .syntax unified + 9044 .LBE764: + 9045 .LBE763: +3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9046 .loc 1 3136 7 discriminator 1 view .LVU2987 + 9047 005a 23F08003 bic r3, r3, #128 + 9048 .LVL772: +3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9049 .loc 1 3136 7 is_stmt 1 discriminator 1 view .LVU2988 + 9050 .LBB765: + 9051 .LBI765: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 9052 .loc 2 1119 31 view .LVU2989 + 9053 .LBB766: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9054 .loc 2 1121 4 view .LVU2990 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 9055 .loc 2 1123 4 view .LVU2991 + 9056 .syntax unified + 9057 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 9058 005e 42E80031 strex r1, r3, [r2] + 9059 @ 0 "" 2 + 9060 .LVL773: + 9061 .loc 2 1124 4 view .LVU2992 + 9062 .loc 2 1124 4 is_stmt 0 view .LVU2993 + 9063 .thumb + 9064 .syntax unified + 9065 .LBE766: + 9066 .LBE765: +3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9067 .loc 1 3136 7 discriminator 1 view .LVU2994 + 9068 0062 0029 cmp r1, #0 + 9069 0064 F6D1 bne .L457 + 9070 .LBE762: +3136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9071 .loc 1 3136 7 is_stmt 1 discriminator 2 view .LVU2995 + ARM GAS /tmp/ccQxTlMj.s page 297 + + +3138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9072 .loc 1 3138 7 view .LVU2996 +3138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9073 .loc 1 3138 21 is_stmt 0 view .LVU2997 + 9074 0066 2023 movs r3, #32 + 9075 .LVL774: +3138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9076 .loc 1 3138 21 view .LVU2998 + 9077 0068 E367 str r3, [r4, #124] +3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9078 .loc 1 3140 7 is_stmt 1 view .LVU2999 +3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9079 .loc 1 3140 7 view .LVU3000 + 9080 006a 0023 movs r3, #0 + 9081 006c 84F87830 strb r3, [r4, #120] +3140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9082 .loc 1 3140 7 view .LVU3001 +3143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9083 .loc 1 3143 7 view .LVU3002 +3143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9084 .loc 1 3143 14 is_stmt 0 view .LVU3003 + 9085 0070 0320 movs r0, #3 + 9086 0072 E1E7 b .L458 + 9087 .LVL775: + 9088 .L464: +3152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9089 .loc 1 3152 5 is_stmt 1 view .LVU3004 +3152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9090 .loc 1 3152 9 is_stmt 0 view .LVU3005 + 9091 0074 6FF07E43 mvn r3, #-33554432 + 9092 0078 0093 str r3, [sp] + 9093 007a 2B46 mov r3, r5 + 9094 007c 0022 movs r2, #0 + 9095 007e 4FF48001 mov r1, #4194304 + 9096 0082 2046 mov r0, r4 + 9097 0084 FFF7FEFF bl UART_WaitOnFlagUntilTimeout + 9098 .LVL776: +3152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9099 .loc 1 3152 8 discriminator 1 view .LVU3006 + 9100 0088 0028 cmp r0, #0 + 9101 008a CCD0 beq .L459 + 9102 .L460: +3156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 9103 .loc 1 3156 7 is_stmt 1 discriminator 1 view .LVU3007 + 9104 .LBB767: +3156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 9105 .loc 1 3156 7 discriminator 1 view .LVU3008 +3156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 9106 .loc 1 3156 7 discriminator 1 view .LVU3009 +3156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 9107 .loc 1 3156 7 discriminator 1 view .LVU3010 + 9108 008c 2268 ldr r2, [r4] + 9109 .LVL777: + 9110 .LBB768: + 9111 .LBI768: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 9112 .loc 2 1068 31 view .LVU3011 + ARM GAS /tmp/ccQxTlMj.s page 298 + + + 9113 .LBB769: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9114 .loc 2 1070 5 view .LVU3012 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 9115 .loc 2 1072 4 view .LVU3013 + 9116 .syntax unified + 9117 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 9118 008e 52E8003F ldrex r3, [r2] + 9119 @ 0 "" 2 + 9120 .LVL778: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 9121 .loc 2 1073 4 view .LVU3014 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 9122 .loc 2 1073 4 is_stmt 0 view .LVU3015 + 9123 .thumb + 9124 .syntax unified + 9125 .LBE769: + 9126 .LBE768: +3156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 9127 .loc 1 3156 7 discriminator 1 view .LVU3016 + 9128 0092 23F49073 bic r3, r3, #288 + 9129 .LVL779: +3156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 9130 .loc 1 3156 7 is_stmt 1 discriminator 1 view .LVU3017 + 9131 .LBB770: + 9132 .LBI770: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 9133 .loc 2 1119 31 view .LVU3018 + 9134 .LBB771: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9135 .loc 2 1121 4 view .LVU3019 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 9136 .loc 2 1123 4 view .LVU3020 + 9137 .syntax unified + 9138 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 9139 0096 42E80031 strex r1, r3, [r2] + 9140 @ 0 "" 2 + 9141 .LVL780: + 9142 .loc 2 1124 4 view .LVU3021 + 9143 .loc 2 1124 4 is_stmt 0 view .LVU3022 + 9144 .thumb + 9145 .syntax unified + 9146 .LBE771: + 9147 .LBE770: +3156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 9148 .loc 1 3156 7 discriminator 1 view .LVU3023 + 9149 009a 0029 cmp r1, #0 + 9150 009c F6D1 bne .L460 + 9151 .LVL781: + 9152 .L461: +3156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 9153 .loc 1 3156 7 discriminator 1 view .LVU3024 + 9154 .LBE767: +3156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 9155 .loc 1 3156 7 is_stmt 1 discriminator 2 view .LVU3025 +3157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9156 .loc 1 3157 7 discriminator 1 view .LVU3026 + ARM GAS /tmp/ccQxTlMj.s page 299 + + + 9157 .LBB772: +3157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9158 .loc 1 3157 7 discriminator 1 view .LVU3027 +3157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9159 .loc 1 3157 7 discriminator 1 view .LVU3028 +3157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9160 .loc 1 3157 7 discriminator 1 view .LVU3029 + 9161 009e 2268 ldr r2, [r4] + 9162 .LVL782: + 9163 .LBB773: + 9164 .LBI773: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 9165 .loc 2 1068 31 view .LVU3030 + 9166 .LBB774: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9167 .loc 2 1070 5 view .LVU3031 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 9168 .loc 2 1072 4 view .LVU3032 + 9169 00a0 02F10803 add r3, r2, #8 + 9170 .LVL783: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 9171 .loc 2 1072 4 is_stmt 0 view .LVU3033 + 9172 .syntax unified + 9173 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 9174 00a4 53E8003F ldrex r3, [r3] + 9175 @ 0 "" 2 + 9176 .LVL784: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 9177 .loc 2 1073 4 is_stmt 1 view .LVU3034 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 9178 .loc 2 1073 4 is_stmt 0 view .LVU3035 + 9179 .thumb + 9180 .syntax unified + 9181 .LBE774: + 9182 .LBE773: +3157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9183 .loc 1 3157 7 discriminator 1 view .LVU3036 + 9184 00a8 23F00103 bic r3, r3, #1 + 9185 .LVL785: +3157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9186 .loc 1 3157 7 is_stmt 1 discriminator 1 view .LVU3037 + 9187 .LBB775: + 9188 .LBI775: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 9189 .loc 2 1119 31 view .LVU3038 + 9190 .LBB776: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9191 .loc 2 1121 4 view .LVU3039 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 9192 .loc 2 1123 4 view .LVU3040 + 9193 00ac 0832 adds r2, r2, #8 + 9194 .LVL786: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 9195 .loc 2 1123 4 is_stmt 0 view .LVU3041 + 9196 .syntax unified + 9197 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 9198 00ae 42E80031 strex r1, r3, [r2] + ARM GAS /tmp/ccQxTlMj.s page 300 + + + 9199 @ 0 "" 2 + 9200 .LVL787: + 9201 .loc 2 1124 4 is_stmt 1 view .LVU3042 + 9202 .loc 2 1124 4 is_stmt 0 view .LVU3043 + 9203 .thumb + 9204 .syntax unified + 9205 .LBE776: + 9206 .LBE775: +3157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9207 .loc 1 3157 7 discriminator 1 view .LVU3044 + 9208 00b2 0029 cmp r1, #0 + 9209 00b4 F3D1 bne .L461 + 9210 .LBE772: +3157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9211 .loc 1 3157 7 is_stmt 1 discriminator 2 view .LVU3045 +3159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9212 .loc 1 3159 7 view .LVU3046 +3159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9213 .loc 1 3159 22 is_stmt 0 view .LVU3047 + 9214 00b6 2023 movs r3, #32 + 9215 .LVL788: +3159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9216 .loc 1 3159 22 view .LVU3048 + 9217 00b8 C4F88030 str r3, [r4, #128] +3161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9218 .loc 1 3161 7 is_stmt 1 view .LVU3049 +3161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9219 .loc 1 3161 7 view .LVU3050 + 9220 00bc 0023 movs r3, #0 + 9221 00be 84F87830 strb r3, [r4, #120] +3161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9222 .loc 1 3161 7 view .LVU3051 +3164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9223 .loc 1 3164 7 view .LVU3052 +3164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9224 .loc 1 3164 14 is_stmt 0 view .LVU3053 + 9225 00c2 0320 movs r0, #3 + 9226 00c4 B8E7 b .L458 + 9227 .cfi_endproc + 9228 .LFE187: + 9230 .section .text.HAL_UART_Init,"ax",%progbits + 9231 .align 1 + 9232 .global HAL_UART_Init + 9233 .syntax unified + 9234 .thumb + 9235 .thumb_func + 9237 HAL_UART_Init: + 9238 .LVL789: + 9239 .LFB141: + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the UART handle allocation */ + 9240 .loc 1 290 1 is_stmt 1 view -0 + 9241 .cfi_startproc + 9242 @ args = 0, pretend = 0, frame = 0 + 9243 @ frame_needed = 0, uses_anonymous_args = 0 + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9244 .loc 1 292 3 view .LVU3055 + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + ARM GAS /tmp/ccQxTlMj.s page 301 + + + 9245 .loc 1 292 6 is_stmt 0 view .LVU3056 + 9246 0000 68B3 cbz r0, .L469 + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the UART handle allocation */ + 9247 .loc 1 290 1 view .LVU3057 + 9248 0002 10B5 push {r4, lr} + 9249 .LCFI41: + 9250 .cfi_def_cfa_offset 8 + 9251 .cfi_offset 4, -8 + 9252 .cfi_offset 14, -4 + 9253 0004 0446 mov r4, r0 + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9254 .loc 1 297 3 is_stmt 1 view .LVU3058 + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9255 .loc 1 300 5 view .LVU3059 + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9256 .loc 1 305 5 view .LVU3060 + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9257 .loc 1 308 3 view .LVU3061 + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9258 .loc 1 308 12 is_stmt 0 view .LVU3062 + 9259 0006 C36F ldr r3, [r0, #124] + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9260 .loc 1 308 6 view .LVU3063 + 9261 0008 03B3 cbz r3, .L474 + 9262 .LVL790: + 9263 .L467: + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9264 .loc 1 329 3 is_stmt 1 view .LVU3064 + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9265 .loc 1 329 17 is_stmt 0 view .LVU3065 + 9266 000a 2423 movs r3, #36 + 9267 000c E367 str r3, [r4, #124] + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9268 .loc 1 331 3 is_stmt 1 view .LVU3066 + 9269 000e 2268 ldr r2, [r4] + 9270 0010 1368 ldr r3, [r2] + 9271 0012 23F00103 bic r3, r3, #1 + 9272 0016 1360 str r3, [r2] + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9273 .loc 1 335 3 view .LVU3067 + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9274 .loc 1 335 26 is_stmt 0 view .LVU3068 + 9275 0018 636A ldr r3, [r4, #36] + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9276 .loc 1 335 6 view .LVU3069 + 9277 001a E3B9 cbnz r3, .L475 + 9278 .L468: + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9279 .loc 1 341 3 is_stmt 1 view .LVU3070 + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9280 .loc 1 341 7 is_stmt 0 view .LVU3071 + 9281 001c 2046 mov r0, r4 + 9282 001e FFF7FEFF bl UART_SetConfig + 9283 .LVL791: + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9284 .loc 1 341 6 discriminator 1 view .LVU3072 + 9285 0022 0128 cmp r0, #1 + ARM GAS /tmp/ccQxTlMj.s page 302 + + + 9286 0024 11D0 beq .L466 + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 9287 .loc 1 349 3 is_stmt 1 view .LVU3073 + 9288 0026 2268 ldr r2, [r4] + 9289 0028 5368 ldr r3, [r2, #4] + 9290 002a 23F49043 bic r3, r3, #18432 + 9291 002e 5360 str r3, [r2, #4] + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9292 .loc 1 350 3 view .LVU3074 + 9293 0030 2268 ldr r2, [r4] + 9294 0032 9368 ldr r3, [r2, #8] + 9295 0034 23F02A03 bic r3, r3, #42 + 9296 0038 9360 str r3, [r2, #8] + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9297 .loc 1 352 3 view .LVU3075 + 9298 003a 2268 ldr r2, [r4] + 9299 003c 1368 ldr r3, [r2] + 9300 003e 43F00103 orr r3, r3, #1 + 9301 0042 1360 str r3, [r2] + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9302 .loc 1 355 3 view .LVU3076 + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9303 .loc 1 355 11 is_stmt 0 view .LVU3077 + 9304 0044 2046 mov r0, r4 + 9305 0046 FFF7FEFF bl UART_CheckIdleState + 9306 .LVL792: + 9307 .L466: + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9308 .loc 1 356 1 view .LVU3078 + 9309 004a 10BD pop {r4, pc} + 9310 .LVL793: + 9311 .L474: + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9312 .loc 1 311 5 is_stmt 1 view .LVU3079 + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9313 .loc 1 311 17 is_stmt 0 view .LVU3080 + 9314 004c 80F87830 strb r3, [r0, #120] + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 9315 .loc 1 325 5 is_stmt 1 view .LVU3081 + 9316 0050 FFF7FEFF bl HAL_UART_MspInit + 9317 .LVL794: + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 9318 .loc 1 325 5 is_stmt 0 view .LVU3082 + 9319 0054 D9E7 b .L467 + 9320 .L475: + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9321 .loc 1 337 5 is_stmt 1 view .LVU3083 + 9322 0056 2046 mov r0, r4 + 9323 0058 FFF7FEFF bl UART_AdvFeatureConfig + 9324 .LVL795: + 9325 005c DEE7 b .L468 + 9326 .LVL796: + 9327 .L469: + 9328 .LCFI42: + 9329 .cfi_def_cfa_offset 0 + 9330 .cfi_restore 4 + 9331 .cfi_restore 14 + ARM GAS /tmp/ccQxTlMj.s page 303 + + + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9332 .loc 1 294 12 is_stmt 0 view .LVU3084 + 9333 005e 0120 movs r0, #1 + 9334 .LVL797: + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9335 .loc 1 356 1 view .LVU3085 + 9336 0060 7047 bx lr + 9337 .cfi_endproc + 9338 .LFE141: + 9340 .section .text.HAL_HalfDuplex_Init,"ax",%progbits + 9341 .align 1 + 9342 .global HAL_HalfDuplex_Init + 9343 .syntax unified + 9344 .thumb + 9345 .thumb_func + 9347 HAL_HalfDuplex_Init: + 9348 .LVL798: + 9349 .LFB142: + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the UART handle allocation */ + 9350 .loc 1 365 1 is_stmt 1 view -0 + 9351 .cfi_startproc + 9352 @ args = 0, pretend = 0, frame = 0 + 9353 @ frame_needed = 0, uses_anonymous_args = 0 + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9354 .loc 1 367 3 view .LVU3087 + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9355 .loc 1 367 6 is_stmt 0 view .LVU3088 + 9356 0000 0028 cmp r0, #0 + 9357 0002 32D0 beq .L480 + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the UART handle allocation */ + 9358 .loc 1 365 1 view .LVU3089 + 9359 0004 10B5 push {r4, lr} + 9360 .LCFI43: + 9361 .cfi_def_cfa_offset 8 + 9362 .cfi_offset 4, -8 + 9363 .cfi_offset 14, -4 + 9364 0006 0446 mov r4, r0 + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9365 .loc 1 373 3 is_stmt 1 view .LVU3090 + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9366 .loc 1 375 3 view .LVU3091 + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9367 .loc 1 375 12 is_stmt 0 view .LVU3092 + 9368 0008 C36F ldr r3, [r0, #124] + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9369 .loc 1 375 6 view .LVU3093 + 9370 000a 2BB3 cbz r3, .L485 + 9371 .LVL799: + 9372 .L478: + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9373 .loc 1 396 3 is_stmt 1 view .LVU3094 + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9374 .loc 1 396 17 is_stmt 0 view .LVU3095 + 9375 000c 2423 movs r3, #36 + 9376 000e E367 str r3, [r4, #124] + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9377 .loc 1 398 3 is_stmt 1 view .LVU3096 + ARM GAS /tmp/ccQxTlMj.s page 304 + + + 9378 0010 2268 ldr r2, [r4] + 9379 0012 1368 ldr r3, [r2] + 9380 0014 23F00103 bic r3, r3, #1 + 9381 0018 1360 str r3, [r2] + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9382 .loc 1 402 3 view .LVU3097 + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9383 .loc 1 402 26 is_stmt 0 view .LVU3098 + 9384 001a 636A ldr r3, [r4, #36] + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9385 .loc 1 402 6 view .LVU3099 + 9386 001c 0BBB cbnz r3, .L486 + 9387 .L479: + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9388 .loc 1 408 3 is_stmt 1 view .LVU3100 + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9389 .loc 1 408 7 is_stmt 0 view .LVU3101 + 9390 001e 2046 mov r0, r4 + 9391 0020 FFF7FEFF bl UART_SetConfig + 9392 .LVL800: + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9393 .loc 1 408 6 discriminator 1 view .LVU3102 + 9394 0024 0128 cmp r0, #1 + 9395 0026 16D0 beq .L477 + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + 9396 .loc 1 416 3 is_stmt 1 view .LVU3103 + 9397 0028 2268 ldr r2, [r4] + 9398 002a 5368 ldr r3, [r2, #4] + 9399 002c 23F49043 bic r3, r3, #18432 + 9400 0030 5360 str r3, [r2, #4] + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9401 .loc 1 417 3 view .LVU3104 + 9402 0032 2268 ldr r2, [r4] + 9403 0034 9368 ldr r3, [r2, #8] + 9404 0036 23F02203 bic r3, r3, #34 + 9405 003a 9360 str r3, [r2, #8] + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9406 .loc 1 420 3 view .LVU3105 + 9407 003c 2268 ldr r2, [r4] + 9408 003e 9368 ldr r3, [r2, #8] + 9409 0040 43F00803 orr r3, r3, #8 + 9410 0044 9360 str r3, [r2, #8] + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9411 .loc 1 422 3 view .LVU3106 + 9412 0046 2268 ldr r2, [r4] + 9413 0048 1368 ldr r3, [r2] + 9414 004a 43F00103 orr r3, r3, #1 + 9415 004e 1360 str r3, [r2] + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9416 .loc 1 425 3 view .LVU3107 + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9417 .loc 1 425 11 is_stmt 0 view .LVU3108 + 9418 0050 2046 mov r0, r4 + 9419 0052 FFF7FEFF bl UART_CheckIdleState + 9420 .LVL801: + 9421 .L477: + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 305 + + + 9422 .loc 1 426 1 view .LVU3109 + 9423 0056 10BD pop {r4, pc} + 9424 .LVL802: + 9425 .L485: + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9426 .loc 1 378 5 is_stmt 1 view .LVU3110 + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9427 .loc 1 378 17 is_stmt 0 view .LVU3111 + 9428 0058 80F87830 strb r3, [r0, #120] + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 9429 .loc 1 392 5 is_stmt 1 view .LVU3112 + 9430 005c FFF7FEFF bl HAL_UART_MspInit + 9431 .LVL803: + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 9432 .loc 1 392 5 is_stmt 0 view .LVU3113 + 9433 0060 D4E7 b .L478 + 9434 .L486: + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9435 .loc 1 404 5 is_stmt 1 view .LVU3114 + 9436 0062 2046 mov r0, r4 + 9437 0064 FFF7FEFF bl UART_AdvFeatureConfig + 9438 .LVL804: + 9439 0068 D9E7 b .L479 + 9440 .LVL805: + 9441 .L480: + 9442 .LCFI44: + 9443 .cfi_def_cfa_offset 0 + 9444 .cfi_restore 4 + 9445 .cfi_restore 14 + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9446 .loc 1 369 12 is_stmt 0 view .LVU3115 + 9447 006a 0120 movs r0, #1 + 9448 .LVL806: + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9449 .loc 1 426 1 view .LVU3116 + 9450 006c 7047 bx lr + 9451 .cfi_endproc + 9452 .LFE142: + 9454 .section .text.HAL_LIN_Init,"ax",%progbits + 9455 .align 1 + 9456 .global HAL_LIN_Init + 9457 .syntax unified + 9458 .thumb + 9459 .thumb_func + 9461 HAL_LIN_Init: + 9462 .LVL807: + 9463 .LFB143: + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the UART handle allocation */ + 9464 .loc 1 440 1 is_stmt 1 view -0 + 9465 .cfi_startproc + 9466 @ args = 0, pretend = 0, frame = 0 + 9467 @ frame_needed = 0, uses_anonymous_args = 0 + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9468 .loc 1 442 3 view .LVU3118 + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9469 .loc 1 442 6 is_stmt 0 view .LVU3119 + 9470 0000 0028 cmp r0, #0 + ARM GAS /tmp/ccQxTlMj.s page 306 + + + 9471 0002 40D0 beq .L491 + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the UART handle allocation */ + 9472 .loc 1 440 1 view .LVU3120 + 9473 0004 38B5 push {r3, r4, r5, lr} + 9474 .LCFI45: + 9475 .cfi_def_cfa_offset 16 + 9476 .cfi_offset 3, -16 + 9477 .cfi_offset 4, -12 + 9478 .cfi_offset 5, -8 + 9479 .cfi_offset 14, -4 + 9480 0006 0D46 mov r5, r1 + 9481 0008 0446 mov r4, r0 + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the Break detection length parameter */ + 9482 .loc 1 448 3 is_stmt 1 view .LVU3121 + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9483 .loc 1 450 3 view .LVU3122 + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9484 .loc 1 453 3 view .LVU3123 + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9485 .loc 1 453 18 is_stmt 0 view .LVU3124 + 9486 000a C369 ldr r3, [r0, #28] + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9487 .loc 1 453 6 view .LVU3125 + 9488 000c B3F5004F cmp r3, #32768 + 9489 0010 3BD0 beq .L492 + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9490 .loc 1 458 3 is_stmt 1 view .LVU3126 + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9491 .loc 1 458 18 is_stmt 0 view .LVU3127 + 9492 0012 8368 ldr r3, [r0, #8] + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9493 .loc 1 458 6 view .LVU3128 + 9494 0014 002B cmp r3, #0 + 9495 0016 3AD1 bne .L493 + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9496 .loc 1 463 3 is_stmt 1 view .LVU3129 + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9497 .loc 1 463 12 is_stmt 0 view .LVU3130 + 9498 0018 C36F ldr r3, [r0, #124] + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9499 .loc 1 463 6 view .LVU3131 + 9500 001a 5BB3 cbz r3, .L498 + 9501 .LVL808: + 9502 .L489: + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9503 .loc 1 484 3 is_stmt 1 view .LVU3132 + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9504 .loc 1 484 17 is_stmt 0 view .LVU3133 + 9505 001c 2423 movs r3, #36 + 9506 001e E367 str r3, [r4, #124] + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9507 .loc 1 486 3 is_stmt 1 view .LVU3134 + 9508 0020 2268 ldr r2, [r4] + 9509 0022 1368 ldr r3, [r2] + 9510 0024 23F00103 bic r3, r3, #1 + 9511 0028 1360 str r3, [r2] + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + ARM GAS /tmp/ccQxTlMj.s page 307 + + + 9512 .loc 1 490 3 view .LVU3135 + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9513 .loc 1 490 26 is_stmt 0 view .LVU3136 + 9514 002a 636A ldr r3, [r4, #36] + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9515 .loc 1 490 6 view .LVU3137 + 9516 002c 3BBB cbnz r3, .L499 + 9517 .L490: + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9518 .loc 1 496 3 is_stmt 1 view .LVU3138 + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9519 .loc 1 496 7 is_stmt 0 view .LVU3139 + 9520 002e 2046 mov r0, r4 + 9521 0030 FFF7FEFF bl UART_SetConfig + 9522 .LVL809: + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9523 .loc 1 496 6 discriminator 1 view .LVU3140 + 9524 0034 0128 cmp r0, #1 + 9525 0036 1CD0 beq .L488 + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + 9526 .loc 1 504 3 is_stmt 1 view .LVU3141 + 9527 0038 2268 ldr r2, [r4] + 9528 003a 5368 ldr r3, [r2, #4] + 9529 003c 23F40063 bic r3, r3, #2048 + 9530 0040 5360 str r3, [r2, #4] + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9531 .loc 1 505 3 view .LVU3142 + 9532 0042 2268 ldr r2, [r4] + 9533 0044 9368 ldr r3, [r2, #8] + 9534 0046 23F02A03 bic r3, r3, #42 + 9535 004a 9360 str r3, [r2, #8] + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9536 .loc 1 508 3 view .LVU3143 + 9537 004c 2268 ldr r2, [r4] + 9538 004e 5368 ldr r3, [r2, #4] + 9539 0050 43F48043 orr r3, r3, #16384 + 9540 0054 5360 str r3, [r2, #4] + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9541 .loc 1 511 3 view .LVU3144 + 9542 0056 2268 ldr r2, [r4] + 9543 0058 5368 ldr r3, [r2, #4] + 9544 005a 23F02003 bic r3, r3, #32 + 9545 005e 2B43 orrs r3, r3, r5 + 9546 0060 5360 str r3, [r2, #4] + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9547 .loc 1 513 3 view .LVU3145 + 9548 0062 2268 ldr r2, [r4] + 9549 0064 1368 ldr r3, [r2] + 9550 0066 43F00103 orr r3, r3, #1 + 9551 006a 1360 str r3, [r2] + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9552 .loc 1 516 3 view .LVU3146 + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9553 .loc 1 516 11 is_stmt 0 view .LVU3147 + 9554 006c 2046 mov r0, r4 + 9555 006e FFF7FEFF bl UART_CheckIdleState + 9556 .LVL810: + ARM GAS /tmp/ccQxTlMj.s page 308 + + + 9557 .L488: + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9558 .loc 1 517 1 view .LVU3148 + 9559 0072 38BD pop {r3, r4, r5, pc} + 9560 .LVL811: + 9561 .L498: + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9562 .loc 1 466 5 is_stmt 1 view .LVU3149 + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9563 .loc 1 466 17 is_stmt 0 view .LVU3150 + 9564 0074 80F87830 strb r3, [r0, #120] + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 9565 .loc 1 480 5 is_stmt 1 view .LVU3151 + 9566 0078 FFF7FEFF bl HAL_UART_MspInit + 9567 .LVL812: + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 9568 .loc 1 480 5 is_stmt 0 view .LVU3152 + 9569 007c CEE7 b .L489 + 9570 .L499: + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9571 .loc 1 492 5 is_stmt 1 view .LVU3153 + 9572 007e 2046 mov r0, r4 + 9573 0080 FFF7FEFF bl UART_AdvFeatureConfig + 9574 .LVL813: + 9575 0084 D3E7 b .L490 + 9576 .LVL814: + 9577 .L491: + 9578 .LCFI46: + 9579 .cfi_def_cfa_offset 0 + 9580 .cfi_restore 3 + 9581 .cfi_restore 4 + 9582 .cfi_restore 5 + 9583 .cfi_restore 14 + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9584 .loc 1 444 12 is_stmt 0 view .LVU3154 + 9585 0086 0120 movs r0, #1 + 9586 .LVL815: + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9587 .loc 1 517 1 view .LVU3155 + 9588 0088 7047 bx lr + 9589 .LVL816: + 9590 .L492: + 9591 .LCFI47: + 9592 .cfi_def_cfa_offset 16 + 9593 .cfi_offset 3, -16 + 9594 .cfi_offset 4, -12 + 9595 .cfi_offset 5, -8 + 9596 .cfi_offset 14, -4 + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9597 .loc 1 455 12 view .LVU3156 + 9598 008a 0120 movs r0, #1 + 9599 .LVL817: + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9600 .loc 1 455 12 view .LVU3157 + 9601 008c F1E7 b .L488 + 9602 .LVL818: + 9603 .L493: + ARM GAS /tmp/ccQxTlMj.s page 309 + + + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9604 .loc 1 460 12 view .LVU3158 + 9605 008e 0120 movs r0, #1 + 9606 .LVL819: + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9607 .loc 1 460 12 view .LVU3159 + 9608 0090 EFE7 b .L488 + 9609 .cfi_endproc + 9610 .LFE143: + 9612 .section .text.HAL_MultiProcessor_Init,"ax",%progbits + 9613 .align 1 + 9614 .global HAL_MultiProcessor_Init + 9615 .syntax unified + 9616 .thumb + 9617 .thumb_func + 9619 HAL_MultiProcessor_Init: + 9620 .LVL820: + 9621 .LFB144: + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the UART handle allocation */ + 9622 .loc 1 539 1 is_stmt 1 view -0 + 9623 .cfi_startproc + 9624 @ args = 0, pretend = 0, frame = 0 + 9625 @ frame_needed = 0, uses_anonymous_args = 0 + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9626 .loc 1 541 3 view .LVU3161 + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9627 .loc 1 541 6 is_stmt 0 view .LVU3162 + 9628 0000 0028 cmp r0, #0 + 9629 0002 40D0 beq .L505 + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check the UART handle allocation */ + 9630 .loc 1 539 1 view .LVU3163 + 9631 0004 70B5 push {r4, r5, r6, lr} + 9632 .LCFI48: + 9633 .cfi_def_cfa_offset 16 + 9634 .cfi_offset 4, -16 + 9635 .cfi_offset 5, -12 + 9636 .cfi_offset 6, -8 + 9637 .cfi_offset 14, -4 + 9638 0006 0E46 mov r6, r1 + 9639 0008 1546 mov r5, r2 + 9640 000a 0446 mov r4, r0 + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9641 .loc 1 547 3 is_stmt 1 view .LVU3164 + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9642 .loc 1 549 3 view .LVU3165 + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9643 .loc 1 549 12 is_stmt 0 view .LVU3166 + 9644 000c C36F ldr r3, [r0, #124] + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9645 .loc 1 549 6 view .LVU3167 + 9646 000e 4BB3 cbz r3, .L510 + 9647 .LVL821: + 9648 .L502: + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9649 .loc 1 570 3 is_stmt 1 view .LVU3168 + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9650 .loc 1 570 17 is_stmt 0 view .LVU3169 + ARM GAS /tmp/ccQxTlMj.s page 310 + + + 9651 0010 2423 movs r3, #36 + 9652 0012 E367 str r3, [r4, #124] + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9653 .loc 1 572 3 is_stmt 1 view .LVU3170 + 9654 0014 2268 ldr r2, [r4] + 9655 0016 1368 ldr r3, [r2] + 9656 0018 23F00103 bic r3, r3, #1 + 9657 001c 1360 str r3, [r2] + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9658 .loc 1 576 3 view .LVU3171 + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9659 .loc 1 576 26 is_stmt 0 view .LVU3172 + 9660 001e 636A ldr r3, [r4, #36] + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9661 .loc 1 576 6 view .LVU3173 + 9662 0020 2BBB cbnz r3, .L511 + 9663 .L503: + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9664 .loc 1 582 3 is_stmt 1 view .LVU3174 + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9665 .loc 1 582 7 is_stmt 0 view .LVU3175 + 9666 0022 2046 mov r0, r4 + 9667 0024 FFF7FEFF bl UART_SetConfig + 9668 .LVL822: + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9669 .loc 1 582 6 discriminator 1 view .LVU3176 + 9670 0028 0128 cmp r0, #1 + 9671 002a 1AD0 beq .L501 + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 9672 .loc 1 590 3 is_stmt 1 view .LVU3177 + 9673 002c 2268 ldr r2, [r4] + 9674 002e 5368 ldr r3, [r2, #4] + 9675 0030 23F49043 bic r3, r3, #18432 + 9676 0034 5360 str r3, [r2, #4] + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9677 .loc 1 591 3 view .LVU3178 + 9678 0036 2268 ldr r2, [r4] + 9679 0038 9368 ldr r3, [r2, #8] + 9680 003a 23F02A03 bic r3, r3, #42 + 9681 003e 9360 str r3, [r2, #8] + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9682 .loc 1 593 3 view .LVU3179 + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 9683 .loc 1 593 6 is_stmt 0 view .LVU3180 + 9684 0040 B5F5006F cmp r5, #2048 + 9685 0044 17D0 beq .L512 + 9686 .L504: + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9687 .loc 1 600 3 is_stmt 1 view .LVU3181 + 9688 0046 2268 ldr r2, [r4] + 9689 0048 1368 ldr r3, [r2] + 9690 004a 23F40063 bic r3, r3, #2048 + 9691 004e 2B43 orrs r3, r3, r5 + 9692 0050 1360 str r3, [r2] + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9693 .loc 1 602 3 view .LVU3182 + 9694 0052 2268 ldr r2, [r4] + ARM GAS /tmp/ccQxTlMj.s page 311 + + + 9695 0054 1368 ldr r3, [r2] + 9696 0056 43F00103 orr r3, r3, #1 + 9697 005a 1360 str r3, [r2] + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9698 .loc 1 605 3 view .LVU3183 + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9699 .loc 1 605 11 is_stmt 0 view .LVU3184 + 9700 005c 2046 mov r0, r4 + 9701 005e FFF7FEFF bl UART_CheckIdleState + 9702 .LVL823: + 9703 .L501: + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9704 .loc 1 606 1 view .LVU3185 + 9705 0062 70BD pop {r4, r5, r6, pc} + 9706 .LVL824: + 9707 .L510: + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9708 .loc 1 552 5 is_stmt 1 view .LVU3186 + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9709 .loc 1 552 17 is_stmt 0 view .LVU3187 + 9710 0064 80F87830 strb r3, [r0, #120] + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 9711 .loc 1 566 5 is_stmt 1 view .LVU3188 + 9712 0068 FFF7FEFF bl HAL_UART_MspInit + 9713 .LVL825: + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 9714 .loc 1 566 5 is_stmt 0 view .LVU3189 + 9715 006c D0E7 b .L502 + 9716 .L511: + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9717 .loc 1 578 5 is_stmt 1 view .LVU3190 + 9718 006e 2046 mov r0, r4 + 9719 0070 FFF7FEFF bl UART_AdvFeatureConfig + 9720 .LVL826: + 9721 0074 D5E7 b .L503 + 9722 .L512: + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9723 .loc 1 596 5 view .LVU3191 + 9724 0076 2268 ldr r2, [r4] + 9725 0078 5368 ldr r3, [r2, #4] + 9726 007a 23F07F43 bic r3, r3, #-16777216 + 9727 007e 43EA0663 orr r3, r3, r6, lsl #24 + 9728 0082 5360 str r3, [r2, #4] + 9729 0084 DFE7 b .L504 + 9730 .LVL827: + 9731 .L505: + 9732 .LCFI49: + 9733 .cfi_def_cfa_offset 0 + 9734 .cfi_restore 4 + 9735 .cfi_restore 5 + 9736 .cfi_restore 6 + 9737 .cfi_restore 14 + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9738 .loc 1 543 12 is_stmt 0 view .LVU3192 + 9739 0086 0120 movs r0, #1 + 9740 .LVL828: + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 312 + + + 9741 .loc 1 606 1 view .LVU3193 + 9742 0088 7047 bx lr + 9743 .cfi_endproc + 9744 .LFE144: + 9746 .section .text.HAL_MultiProcessor_EnableMuteMode,"ax",%progbits + 9747 .align 1 + 9748 .global HAL_MultiProcessor_EnableMuteMode + 9749 .syntax unified + 9750 .thumb + 9751 .thumb_func + 9753 HAL_MultiProcessor_EnableMuteMode: + 9754 .LVL829: + 9755 .LFB177: +2696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_LOCK(huart); + 9756 .loc 1 2696 1 is_stmt 1 view -0 + 9757 .cfi_startproc + 9758 @ args = 0, pretend = 0, frame = 0 + 9759 @ frame_needed = 0, uses_anonymous_args = 0 +2696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_LOCK(huart); + 9760 .loc 1 2696 1 is_stmt 0 view .LVU3195 + 9761 0000 08B5 push {r3, lr} + 9762 .LCFI50: + 9763 .cfi_def_cfa_offset 8 + 9764 .cfi_offset 3, -8 + 9765 .cfi_offset 14, -4 +2697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9766 .loc 1 2697 3 is_stmt 1 view .LVU3196 +2697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9767 .loc 1 2697 3 view .LVU3197 + 9768 0002 90F87830 ldrb r3, [r0, #120] @ zero_extendqisi2 + 9769 0006 012B cmp r3, #1 + 9770 0008 12D0 beq .L516 +2697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9771 .loc 1 2697 3 discriminator 2 view .LVU3198 + 9772 000a 0123 movs r3, #1 + 9773 000c 80F87830 strb r3, [r0, #120] +2697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9774 .loc 1 2697 3 discriminator 2 view .LVU3199 +2699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9775 .loc 1 2699 3 view .LVU3200 +2699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9776 .loc 1 2699 17 is_stmt 0 view .LVU3201 + 9777 0010 2423 movs r3, #36 + 9778 0012 C367 str r3, [r0, #124] + 9779 .L515: +2702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9780 .loc 1 2702 3 is_stmt 1 discriminator 1 view .LVU3202 + 9781 .LBB777: +2702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9782 .loc 1 2702 3 discriminator 1 view .LVU3203 +2702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9783 .loc 1 2702 3 discriminator 1 view .LVU3204 +2702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9784 .loc 1 2702 3 discriminator 1 view .LVU3205 + 9785 0014 0268 ldr r2, [r0] + 9786 .LVL830: + 9787 .LBB778: + ARM GAS /tmp/ccQxTlMj.s page 313 + + + 9788 .LBI778: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 9789 .loc 2 1068 31 view .LVU3206 + 9790 .LBB779: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9791 .loc 2 1070 5 view .LVU3207 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 9792 .loc 2 1072 4 view .LVU3208 + 9793 .syntax unified + 9794 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 9795 0016 52E8003F ldrex r3, [r2] + 9796 @ 0 "" 2 + 9797 .LVL831: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 9798 .loc 2 1073 4 view .LVU3209 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 9799 .loc 2 1073 4 is_stmt 0 view .LVU3210 + 9800 .thumb + 9801 .syntax unified + 9802 .LBE779: + 9803 .LBE778: +2702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9804 .loc 1 2702 3 discriminator 1 view .LVU3211 + 9805 001a 43F40053 orr r3, r3, #8192 + 9806 .LVL832: +2702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9807 .loc 1 2702 3 is_stmt 1 discriminator 1 view .LVU3212 + 9808 .LBB780: + 9809 .LBI780: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 9810 .loc 2 1119 31 view .LVU3213 + 9811 .LBB781: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9812 .loc 2 1121 4 view .LVU3214 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 9813 .loc 2 1123 4 view .LVU3215 + 9814 .syntax unified + 9815 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 9816 001e 42E80031 strex r1, r3, [r2] + 9817 @ 0 "" 2 + 9818 .LVL833: + 9819 .loc 2 1124 4 view .LVU3216 + 9820 .loc 2 1124 4 is_stmt 0 view .LVU3217 + 9821 .thumb + 9822 .syntax unified + 9823 .LBE781: + 9824 .LBE780: +2702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9825 .loc 1 2702 3 discriminator 1 view .LVU3218 + 9826 0022 0029 cmp r1, #0 + 9827 0024 F6D1 bne .L515 + 9828 .LBE777: +2702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9829 .loc 1 2702 3 is_stmt 1 discriminator 2 view .LVU3219 +2704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9830 .loc 1 2704 3 view .LVU3220 +2704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 314 + + + 9831 .loc 1 2704 17 is_stmt 0 view .LVU3221 + 9832 0026 2023 movs r3, #32 + 9833 .LVL834: +2704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9834 .loc 1 2704 17 view .LVU3222 + 9835 0028 C367 str r3, [r0, #124] +2706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9836 .loc 1 2706 3 is_stmt 1 view .LVU3223 +2706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9837 .loc 1 2706 11 is_stmt 0 view .LVU3224 + 9838 002a FFF7FEFF bl UART_CheckIdleState + 9839 .LVL835: + 9840 .L514: +2707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9841 .loc 1 2707 1 view .LVU3225 + 9842 002e 08BD pop {r3, pc} + 9843 .LVL836: + 9844 .L516: +2697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9845 .loc 1 2697 3 discriminator 1 view .LVU3226 + 9846 0030 0220 movs r0, #2 + 9847 .LVL837: +2697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9848 .loc 1 2697 3 discriminator 1 view .LVU3227 + 9849 0032 FCE7 b .L514 + 9850 .cfi_endproc + 9851 .LFE177: + 9853 .section .text.HAL_MultiProcessor_DisableMuteMode,"ax",%progbits + 9854 .align 1 + 9855 .global HAL_MultiProcessor_DisableMuteMode + 9856 .syntax unified + 9857 .thumb + 9858 .thumb_func + 9860 HAL_MultiProcessor_DisableMuteMode: + 9861 .LVL838: + 9862 .LFB178: +2716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_LOCK(huart); + 9863 .loc 1 2716 1 is_stmt 1 view -0 + 9864 .cfi_startproc + 9865 @ args = 0, pretend = 0, frame = 0 + 9866 @ frame_needed = 0, uses_anonymous_args = 0 +2716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** __HAL_LOCK(huart); + 9867 .loc 1 2716 1 is_stmt 0 view .LVU3229 + 9868 0000 08B5 push {r3, lr} + 9869 .LCFI51: + 9870 .cfi_def_cfa_offset 8 + 9871 .cfi_offset 3, -8 + 9872 .cfi_offset 14, -4 +2717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9873 .loc 1 2717 3 is_stmt 1 view .LVU3230 +2717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9874 .loc 1 2717 3 view .LVU3231 + 9875 0002 90F87830 ldrb r3, [r0, #120] @ zero_extendqisi2 + 9876 0006 012B cmp r3, #1 + 9877 0008 12D0 beq .L521 +2717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9878 .loc 1 2717 3 discriminator 2 view .LVU3232 + ARM GAS /tmp/ccQxTlMj.s page 315 + + + 9879 000a 0123 movs r3, #1 + 9880 000c 80F87830 strb r3, [r0, #120] +2717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9881 .loc 1 2717 3 discriminator 2 view .LVU3233 +2719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9882 .loc 1 2719 3 view .LVU3234 +2719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9883 .loc 1 2719 17 is_stmt 0 view .LVU3235 + 9884 0010 2423 movs r3, #36 + 9885 0012 C367 str r3, [r0, #124] + 9886 .L520: +2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9887 .loc 1 2722 3 is_stmt 1 discriminator 1 view .LVU3236 + 9888 .LBB782: +2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9889 .loc 1 2722 3 discriminator 1 view .LVU3237 +2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9890 .loc 1 2722 3 discriminator 1 view .LVU3238 +2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9891 .loc 1 2722 3 discriminator 1 view .LVU3239 + 9892 0014 0268 ldr r2, [r0] + 9893 .LVL839: + 9894 .LBB783: + 9895 .LBI783: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 9896 .loc 2 1068 31 view .LVU3240 + 9897 .LBB784: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9898 .loc 2 1070 5 view .LVU3241 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 9899 .loc 2 1072 4 view .LVU3242 + 9900 .syntax unified + 9901 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 9902 0016 52E8003F ldrex r3, [r2] + 9903 @ 0 "" 2 + 9904 .LVL840: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 9905 .loc 2 1073 4 view .LVU3243 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 9906 .loc 2 1073 4 is_stmt 0 view .LVU3244 + 9907 .thumb + 9908 .syntax unified + 9909 .LBE784: + 9910 .LBE783: +2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9911 .loc 1 2722 3 discriminator 1 view .LVU3245 + 9912 001a 23F40053 bic r3, r3, #8192 + 9913 .LVL841: +2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9914 .loc 1 2722 3 is_stmt 1 discriminator 1 view .LVU3246 + 9915 .LBB785: + 9916 .LBI785: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 9917 .loc 2 1119 31 view .LVU3247 + 9918 .LBB786: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 9919 .loc 2 1121 4 view .LVU3248 + ARM GAS /tmp/ccQxTlMj.s page 316 + + +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 9920 .loc 2 1123 4 view .LVU3249 + 9921 .syntax unified + 9922 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 9923 001e 42E80031 strex r1, r3, [r2] + 9924 @ 0 "" 2 + 9925 .LVL842: + 9926 .loc 2 1124 4 view .LVU3250 + 9927 .loc 2 1124 4 is_stmt 0 view .LVU3251 + 9928 .thumb + 9929 .syntax unified + 9930 .LBE786: + 9931 .LBE785: +2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9932 .loc 1 2722 3 discriminator 1 view .LVU3252 + 9933 0022 0029 cmp r1, #0 + 9934 0024 F6D1 bne .L520 + 9935 .LBE782: +2722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9936 .loc 1 2722 3 is_stmt 1 discriminator 2 view .LVU3253 +2724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9937 .loc 1 2724 3 view .LVU3254 +2724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9938 .loc 1 2724 17 is_stmt 0 view .LVU3255 + 9939 0026 2023 movs r3, #32 + 9940 .LVL843: +2724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9941 .loc 1 2724 17 view .LVU3256 + 9942 0028 C367 str r3, [r0, #124] +2726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9943 .loc 1 2726 3 is_stmt 1 view .LVU3257 +2726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 9944 .loc 1 2726 11 is_stmt 0 view .LVU3258 + 9945 002a FFF7FEFF bl UART_CheckIdleState + 9946 .LVL844: + 9947 .L519: +2727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9948 .loc 1 2727 1 view .LVU3259 + 9949 002e 08BD pop {r3, pc} + 9950 .LVL845: + 9951 .L521: +2717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9952 .loc 1 2717 3 discriminator 1 view .LVU3260 + 9953 0030 0220 movs r0, #2 + 9954 .LVL846: +2717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9955 .loc 1 2717 3 discriminator 1 view .LVU3261 + 9956 0032 FCE7 b .L519 + 9957 .cfi_endproc + 9958 .LFE178: + 9960 .section .text.UART_Start_Receive_IT,"ax",%progbits + 9961 .align 1 + 9962 .global UART_Start_Receive_IT + 9963 .syntax unified + 9964 .thumb + 9965 .thumb_func + 9967 UART_Start_Receive_IT: + ARM GAS /tmp/ccQxTlMj.s page 317 + + + 9968 .LVL847: + 9969 .LFB189: +3259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pRxBuffPtr = pData; + 9970 .loc 1 3259 1 is_stmt 1 view -0 + 9971 .cfi_startproc + 9972 @ args = 0, pretend = 0, frame = 0 + 9973 @ frame_needed = 0, uses_anonymous_args = 0 + 9974 @ link register save eliminated. +3260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferSize = Size; + 9975 .loc 1 3260 3 view .LVU3263 +3260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferSize = Size; + 9976 .loc 1 3260 22 is_stmt 0 view .LVU3264 + 9977 0000 4165 str r1, [r0, #84] +3261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = Size; + 9978 .loc 1 3261 3 is_stmt 1 view .LVU3265 +3261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferCount = Size; + 9979 .loc 1 3261 22 is_stmt 0 view .LVU3266 + 9980 0002 A0F85820 strh r2, [r0, #88] @ movhi +3262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxISR = NULL; + 9981 .loc 1 3262 3 is_stmt 1 view .LVU3267 +3262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxISR = NULL; + 9982 .loc 1 3262 22 is_stmt 0 view .LVU3268 + 9983 0006 A0F85A20 strh r2, [r0, #90] @ movhi +3263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9984 .loc 1 3263 3 is_stmt 1 view .LVU3269 +3263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9985 .loc 1 3263 22 is_stmt 0 view .LVU3270 + 9986 000a 0023 movs r3, #0 + 9987 000c 8366 str r3, [r0, #104] +3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9988 .loc 1 3266 3 is_stmt 1 view .LVU3271 +3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9989 .loc 1 3266 3 view .LVU3272 + 9990 000e 8368 ldr r3, [r0, #8] + 9991 0010 B3F5805F cmp r3, #4096 + 9992 0014 06D0 beq .L537 +3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9993 .loc 1 3266 3 discriminator 2 view .LVU3273 + 9994 0016 A3B9 cbnz r3, .L527 +3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9995 .loc 1 3266 3 discriminator 5 view .LVU3274 + 9996 0018 0369 ldr r3, [r0, #16] + 9997 001a 73B9 cbnz r3, .L528 +3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 9998 .loc 1 3266 3 discriminator 7 view .LVU3275 + 9999 001c FF23 movs r3, #255 + 10000 001e A0F85C30 strh r3, [r0, #92] @ movhi + 10001 0022 14E0 b .L526 + 10002 .L537: +3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10003 .loc 1 3266 3 discriminator 1 view .LVU3276 + 10004 0024 0369 ldr r3, [r0, #16] + 10005 0026 23B9 cbnz r3, .L525 +3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10006 .loc 1 3266 3 discriminator 3 view .LVU3277 + 10007 0028 40F2FF13 movw r3, #511 + 10008 002c A0F85C30 strh r3, [r0, #92] @ movhi + ARM GAS /tmp/ccQxTlMj.s page 318 + + + 10009 0030 0DE0 b .L526 + 10010 .L525: +3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10011 .loc 1 3266 3 discriminator 4 view .LVU3278 + 10012 0032 FF23 movs r3, #255 + 10013 0034 A0F85C30 strh r3, [r0, #92] @ movhi + 10014 0038 09E0 b .L526 + 10015 .L528: +3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10016 .loc 1 3266 3 discriminator 8 view .LVU3279 + 10017 003a 7F23 movs r3, #127 + 10018 003c A0F85C30 strh r3, [r0, #92] @ movhi + 10019 0040 05E0 b .L526 + 10020 .L527: +3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10021 .loc 1 3266 3 discriminator 6 view .LVU3280 + 10022 0042 B3F1805F cmp r3, #268435456 + 10023 0046 27D0 beq .L538 +3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10024 .loc 1 3266 3 discriminator 10 view .LVU3281 + 10025 0048 0023 movs r3, #0 + 10026 004a A0F85C30 strh r3, [r0, #92] @ movhi + 10027 .L526: +3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10028 .loc 1 3266 3 discriminator 13 view .LVU3282 +3268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 10029 .loc 1 3268 3 view .LVU3283 +3268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 10030 .loc 1 3268 20 is_stmt 0 view .LVU3284 + 10031 004e 0023 movs r3, #0 + 10032 0050 C0F88430 str r3, [r0, #132] +3269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10033 .loc 1 3269 3 is_stmt 1 view .LVU3285 +3269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10034 .loc 1 3269 18 is_stmt 0 view .LVU3286 + 10035 0054 2223 movs r3, #34 + 10036 0056 C0F88030 str r3, [r0, #128] + 10037 .LVL848: + 10038 .L531: +3272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10039 .loc 1 3272 3 is_stmt 1 discriminator 1 view .LVU3287 + 10040 .LBB787: +3272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10041 .loc 1 3272 3 discriminator 1 view .LVU3288 +3272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10042 .loc 1 3272 3 discriminator 1 view .LVU3289 +3272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10043 .loc 1 3272 3 discriminator 1 view .LVU3290 + 10044 005a 0268 ldr r2, [r0] + 10045 .LVL849: + 10046 .LBB788: + 10047 .LBI788: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 10048 .loc 2 1068 31 view .LVU3291 + 10049 .LBB789: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 10050 .loc 2 1070 5 view .LVU3292 + ARM GAS /tmp/ccQxTlMj.s page 319 + + +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10051 .loc 2 1072 4 view .LVU3293 + 10052 005c 02F10803 add r3, r2, #8 + 10053 .LVL850: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10054 .loc 2 1072 4 is_stmt 0 view .LVU3294 + 10055 .syntax unified + 10056 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 10057 0060 53E8003F ldrex r3, [r3] + 10058 @ 0 "" 2 + 10059 .LVL851: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 10060 .loc 2 1073 4 is_stmt 1 view .LVU3295 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 10061 .loc 2 1073 4 is_stmt 0 view .LVU3296 + 10062 .thumb + 10063 .syntax unified + 10064 .LBE789: + 10065 .LBE788: +3272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10066 .loc 1 3272 3 discriminator 1 view .LVU3297 + 10067 0064 43F00103 orr r3, r3, #1 + 10068 .LVL852: +3272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10069 .loc 1 3272 3 is_stmt 1 discriminator 1 view .LVU3298 + 10070 .LBB790: + 10071 .LBI790: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 10072 .loc 2 1119 31 view .LVU3299 + 10073 .LBB791: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 10074 .loc 2 1121 4 view .LVU3300 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10075 .loc 2 1123 4 view .LVU3301 + 10076 0068 0832 adds r2, r2, #8 + 10077 .LVL853: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10078 .loc 2 1123 4 is_stmt 0 view .LVU3302 + 10079 .syntax unified + 10080 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 10081 006a 42E80031 strex r1, r3, [r2] + 10082 @ 0 "" 2 + 10083 .LVL854: + 10084 .loc 2 1124 4 is_stmt 1 view .LVU3303 + 10085 .loc 2 1124 4 is_stmt 0 view .LVU3304 + 10086 .thumb + 10087 .syntax unified + 10088 .LBE791: + 10089 .LBE790: +3272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10090 .loc 1 3272 3 discriminator 1 view .LVU3305 + 10091 006e 0029 cmp r1, #0 + 10092 0070 F3D1 bne .L531 + 10093 .LBE787: +3272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10094 .loc 1 3272 3 is_stmt 1 discriminator 2 view .LVU3306 +3275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + ARM GAS /tmp/ccQxTlMj.s page 320 + + + 10095 .loc 1 3275 3 view .LVU3307 +3275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10096 .loc 1 3275 19 is_stmt 0 view .LVU3308 + 10097 0072 8368 ldr r3, [r0, #8] + 10098 .LVL855: +3275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10099 .loc 1 3275 6 view .LVU3309 + 10100 0074 B3F5805F cmp r3, #4096 + 10101 0078 18D0 beq .L539 + 10102 .L532: +3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10103 .loc 1 3281 5 is_stmt 1 view .LVU3310 +3281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10104 .loc 1 3281 18 is_stmt 0 view .LVU3311 + 10105 007a 144B ldr r3, .L540 + 10106 007c 8366 str r3, [r0, #104] + 10107 .L533: +3285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10108 .loc 1 3285 3 is_stmt 1 view .LVU3312 +3285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10109 .loc 1 3285 18 is_stmt 0 view .LVU3313 + 10110 007e 0369 ldr r3, [r0, #16] +3285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10111 .loc 1 3285 6 view .LVU3314 + 10112 0080 D3B1 cbz r3, .L534 + 10113 .L535: +3287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10114 .loc 1 3287 5 is_stmt 1 discriminator 1 view .LVU3315 + 10115 .LBB792: +3287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10116 .loc 1 3287 5 discriminator 1 view .LVU3316 +3287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10117 .loc 1 3287 5 discriminator 1 view .LVU3317 +3287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10118 .loc 1 3287 5 discriminator 1 view .LVU3318 + 10119 0082 0268 ldr r2, [r0] + 10120 .LVL856: + 10121 .LBB793: + 10122 .LBI793: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 10123 .loc 2 1068 31 view .LVU3319 + 10124 .LBB794: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 10125 .loc 2 1070 5 view .LVU3320 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10126 .loc 2 1072 4 view .LVU3321 + 10127 .syntax unified + 10128 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 10129 0084 52E8003F ldrex r3, [r2] + 10130 @ 0 "" 2 + 10131 .LVL857: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 10132 .loc 2 1073 4 view .LVU3322 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 10133 .loc 2 1073 4 is_stmt 0 view .LVU3323 + 10134 .thumb + 10135 .syntax unified + ARM GAS /tmp/ccQxTlMj.s page 321 + + + 10136 .LBE794: + 10137 .LBE793: +3287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10138 .loc 1 3287 5 discriminator 1 view .LVU3324 + 10139 0088 43F49073 orr r3, r3, #288 + 10140 .LVL858: +3287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10141 .loc 1 3287 5 is_stmt 1 discriminator 1 view .LVU3325 + 10142 .LBB795: + 10143 .LBI795: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 10144 .loc 2 1119 31 view .LVU3326 + 10145 .LBB796: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 10146 .loc 2 1121 4 view .LVU3327 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10147 .loc 2 1123 4 view .LVU3328 + 10148 .syntax unified + 10149 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 10150 008c 42E80031 strex r1, r3, [r2] + 10151 @ 0 "" 2 + 10152 .LVL859: + 10153 .loc 2 1124 4 view .LVU3329 + 10154 .loc 2 1124 4 is_stmt 0 view .LVU3330 + 10155 .thumb + 10156 .syntax unified + 10157 .LBE796: + 10158 .LBE795: +3287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10159 .loc 1 3287 5 discriminator 1 view .LVU3331 + 10160 0090 0029 cmp r1, #0 + 10161 0092 F6D1 bne .L535 + 10162 .LVL860: + 10163 .L536: +3287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10164 .loc 1 3287 5 discriminator 1 view .LVU3332 + 10165 .LBE792: +3291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10166 .loc 1 3291 5 is_stmt 1 discriminator 2 view .LVU3333 +3293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10167 .loc 1 3293 3 view .LVU3334 +3294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10168 .loc 1 3294 1 is_stmt 0 view .LVU3335 + 10169 0094 0020 movs r0, #0 + 10170 .LVL861: +3294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10171 .loc 1 3294 1 view .LVU3336 + 10172 0096 7047 bx lr + 10173 .LVL862: + 10174 .L538: +3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10175 .loc 1 3266 3 is_stmt 1 discriminator 9 view .LVU3337 + 10176 0098 0369 ldr r3, [r0, #16] + 10177 009a 1BB9 cbnz r3, .L530 +3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10178 .loc 1 3266 3 discriminator 11 view .LVU3338 + 10179 009c 7F23 movs r3, #127 + ARM GAS /tmp/ccQxTlMj.s page 322 + + + 10180 009e A0F85C30 strh r3, [r0, #92] @ movhi + 10181 00a2 D4E7 b .L526 + 10182 .L530: +3266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10183 .loc 1 3266 3 discriminator 12 view .LVU3339 + 10184 00a4 3F23 movs r3, #63 + 10185 00a6 A0F85C30 strh r3, [r0, #92] @ movhi + 10186 00aa D0E7 b .L526 + 10187 .LVL863: + 10188 .L539: +3275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10189 .loc 1 3275 69 is_stmt 0 discriminator 1 view .LVU3340 + 10190 00ac 0369 ldr r3, [r0, #16] +3275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10191 .loc 1 3275 54 discriminator 1 view .LVU3341 + 10192 00ae 002B cmp r3, #0 + 10193 00b0 E3D1 bne .L532 +3277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10194 .loc 1 3277 5 is_stmt 1 view .LVU3342 +3277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10195 .loc 1 3277 18 is_stmt 0 view .LVU3343 + 10196 00b2 074B ldr r3, .L540+4 + 10197 00b4 8366 str r3, [r0, #104] + 10198 00b6 E2E7 b .L533 + 10199 .L534: +3291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10200 .loc 1 3291 5 is_stmt 1 discriminator 1 view .LVU3344 + 10201 .LBB797: +3291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10202 .loc 1 3291 5 discriminator 1 view .LVU3345 +3291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10203 .loc 1 3291 5 discriminator 1 view .LVU3346 +3291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10204 .loc 1 3291 5 discriminator 1 view .LVU3347 + 10205 00b8 0268 ldr r2, [r0] + 10206 .LVL864: + 10207 .LBB798: + 10208 .LBI798: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 10209 .loc 2 1068 31 view .LVU3348 + 10210 .LBB799: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 10211 .loc 2 1070 5 view .LVU3349 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10212 .loc 2 1072 4 view .LVU3350 + 10213 .syntax unified + 10214 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 10215 00ba 52E8003F ldrex r3, [r2] + 10216 @ 0 "" 2 + 10217 .LVL865: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 10218 .loc 2 1073 4 view .LVU3351 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 10219 .loc 2 1073 4 is_stmt 0 view .LVU3352 + 10220 .thumb + 10221 .syntax unified + 10222 .LBE799: + ARM GAS /tmp/ccQxTlMj.s page 323 + + + 10223 .LBE798: +3291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10224 .loc 1 3291 5 discriminator 1 view .LVU3353 + 10225 00be 43F02003 orr r3, r3, #32 + 10226 .LVL866: +3291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10227 .loc 1 3291 5 is_stmt 1 discriminator 1 view .LVU3354 + 10228 .LBB800: + 10229 .LBI800: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 10230 .loc 2 1119 31 view .LVU3355 + 10231 .LBB801: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 10232 .loc 2 1121 4 view .LVU3356 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10233 .loc 2 1123 4 view .LVU3357 + 10234 .syntax unified + 10235 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 10236 00c2 42E80031 strex r1, r3, [r2] + 10237 @ 0 "" 2 + 10238 .LVL867: + 10239 .loc 2 1124 4 view .LVU3358 + 10240 .loc 2 1124 4 is_stmt 0 view .LVU3359 + 10241 .thumb + 10242 .syntax unified + 10243 .LBE801: + 10244 .LBE800: +3291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10245 .loc 1 3291 5 discriminator 1 view .LVU3360 + 10246 00c6 0029 cmp r1, #0 + 10247 00c8 F6D1 bne .L534 + 10248 00ca E3E7 b .L536 + 10249 .L541: + 10250 .align 2 + 10251 .L540: + 10252 00cc 00000000 .word UART_RxISR_8BIT + 10253 00d0 00000000 .word UART_RxISR_16BIT + 10254 .LBE797: + 10255 .cfi_endproc + 10256 .LFE189: + 10258 .section .text.HAL_UART_Receive_IT,"ax",%progbits + 10259 .align 1 + 10260 .global HAL_UART_Receive_IT + 10261 .syntax unified + 10262 .thumb + 10263 .thumb_func + 10265 HAL_UART_Receive_IT: + 10266 .LVL868: + 10267 .LFB151: +1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that a Rx process is not already ongoing */ + 10268 .loc 1 1309 1 is_stmt 1 view -0 + 10269 .cfi_startproc + 10270 @ args = 0, pretend = 0, frame = 0 + 10271 @ frame_needed = 0, uses_anonymous_args = 0 +1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that a Rx process is not already ongoing */ + 10272 .loc 1 1309 1 is_stmt 0 view .LVU3362 + 10273 0000 38B5 push {r3, r4, r5, lr} + ARM GAS /tmp/ccQxTlMj.s page 324 + + + 10274 .LCFI52: + 10275 .cfi_def_cfa_offset 16 + 10276 .cfi_offset 3, -16 + 10277 .cfi_offset 4, -12 + 10278 .cfi_offset 5, -8 + 10279 .cfi_offset 14, -4 +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10280 .loc 1 1311 3 is_stmt 1 view .LVU3363 +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10281 .loc 1 1311 12 is_stmt 0 view .LVU3364 + 10282 0002 D0F88030 ldr r3, [r0, #128] +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10283 .loc 1 1311 6 view .LVU3365 + 10284 0006 202B cmp r3, #32 + 10285 0008 16D1 bne .L546 +1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10286 .loc 1 1313 5 is_stmt 1 view .LVU3366 +1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10287 .loc 1 1313 8 is_stmt 0 view .LVU3367 + 10288 000a 002A cmp r2, #0 + 10289 000c 18BF it ne + 10290 000e 0029 cmpne r1, #0 + 10291 0010 14D0 beq .L547 +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10292 .loc 1 1319 5 is_stmt 1 view .LVU3368 +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10293 .loc 1 1319 26 is_stmt 0 view .LVU3369 + 10294 0012 0023 movs r3, #0 + 10295 0014 0366 str r3, [r0, #96] +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10296 .loc 1 1322 5 is_stmt 1 view .LVU3370 +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10297 .loc 1 1322 9 is_stmt 0 view .LVU3371 + 10298 0016 0368 ldr r3, [r0] + 10299 0018 5B68 ldr r3, [r3, #4] +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10300 .loc 1 1322 8 view .LVU3372 + 10301 001a 13F4000F tst r3, #8388608 + 10302 001e 08D0 beq .L544 + 10303 .L545: +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10304 .loc 1 1325 7 is_stmt 1 discriminator 1 view .LVU3373 + 10305 .LBB802: +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10306 .loc 1 1325 7 discriminator 1 view .LVU3374 +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10307 .loc 1 1325 7 discriminator 1 view .LVU3375 +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10308 .loc 1 1325 7 discriminator 1 view .LVU3376 + 10309 0020 0468 ldr r4, [r0] + 10310 .LVL869: + 10311 .LBB803: + 10312 .LBI803: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 10313 .loc 2 1068 31 view .LVU3377 + 10314 .LBB804: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccQxTlMj.s page 325 + + + 10315 .loc 2 1070 5 view .LVU3378 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10316 .loc 2 1072 4 view .LVU3379 + 10317 .syntax unified + 10318 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 10319 0022 54E8003F ldrex r3, [r4] + 10320 @ 0 "" 2 + 10321 .LVL870: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 10322 .loc 2 1073 4 view .LVU3380 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 10323 .loc 2 1073 4 is_stmt 0 view .LVU3381 + 10324 .thumb + 10325 .syntax unified + 10326 .LBE804: + 10327 .LBE803: +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10328 .loc 1 1325 7 discriminator 1 view .LVU3382 + 10329 0026 43F08063 orr r3, r3, #67108864 + 10330 .LVL871: +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10331 .loc 1 1325 7 is_stmt 1 discriminator 1 view .LVU3383 + 10332 .LBB805: + 10333 .LBI805: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 10334 .loc 2 1119 31 view .LVU3384 + 10335 .LBB806: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 10336 .loc 2 1121 4 view .LVU3385 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10337 .loc 2 1123 4 view .LVU3386 + 10338 .syntax unified + 10339 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 10340 002a 44E80035 strex r5, r3, [r4] + 10341 @ 0 "" 2 + 10342 .LVL872: + 10343 .loc 2 1124 4 view .LVU3387 + 10344 .loc 2 1124 4 is_stmt 0 view .LVU3388 + 10345 .thumb + 10346 .syntax unified + 10347 .LBE806: + 10348 .LBE805: +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10349 .loc 1 1325 7 discriminator 1 view .LVU3389 + 10350 002e 002D cmp r5, #0 + 10351 0030 F6D1 bne .L545 + 10352 .LVL873: + 10353 .L544: +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10354 .loc 1 1325 7 discriminator 1 view .LVU3390 + 10355 .LBE802: +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10356 .loc 1 1325 7 is_stmt 1 discriminator 2 view .LVU3391 +1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10357 .loc 1 1328 5 view .LVU3392 +1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10358 .loc 1 1328 13 is_stmt 0 view .LVU3393 + ARM GAS /tmp/ccQxTlMj.s page 326 + + + 10359 0032 FFF7FEFF bl UART_Start_Receive_IT + 10360 .LVL874: +1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10361 .loc 1 1328 13 view .LVU3394 + 10362 0036 00E0 b .L543 + 10363 .LVL875: + 10364 .L546: +1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10365 .loc 1 1332 12 view .LVU3395 + 10366 0038 0220 movs r0, #2 + 10367 .LVL876: + 10368 .L543: +1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10369 .loc 1 1334 1 view .LVU3396 + 10370 003a 38BD pop {r3, r4, r5, pc} + 10371 .LVL877: + 10372 .L547: +1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10373 .loc 1 1315 14 view .LVU3397 + 10374 003c 0120 movs r0, #1 + 10375 .LVL878: +1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10376 .loc 1 1315 14 view .LVU3398 + 10377 003e FCE7 b .L543 + 10378 .cfi_endproc + 10379 .LFE151: + 10381 .section .text.UART_Start_Receive_DMA,"ax",%progbits + 10382 .align 1 + 10383 .global UART_Start_Receive_DMA + 10384 .syntax unified + 10385 .thumb + 10386 .thumb_func + 10388 UART_Start_Receive_DMA: + 10389 .LVL879: + 10390 .LFB190: +3308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pRxBuffPtr = pData; + 10391 .loc 1 3308 1 is_stmt 1 view -0 + 10392 .cfi_startproc + 10393 @ args = 0, pretend = 0, frame = 0 + 10394 @ frame_needed = 0, uses_anonymous_args = 0 +3308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->pRxBuffPtr = pData; + 10395 .loc 1 3308 1 is_stmt 0 view .LVU3400 + 10396 0000 10B5 push {r4, lr} + 10397 .LCFI53: + 10398 .cfi_def_cfa_offset 8 + 10399 .cfi_offset 4, -8 + 10400 .cfi_offset 14, -4 + 10401 0002 0446 mov r4, r0 + 10402 0004 1346 mov r3, r2 +3309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferSize = Size; + 10403 .loc 1 3309 3 is_stmt 1 view .LVU3401 +3309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxXferSize = Size; + 10404 .loc 1 3309 21 is_stmt 0 view .LVU3402 + 10405 0006 4165 str r1, [r0, #84] +3310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10406 .loc 1 3310 3 is_stmt 1 view .LVU3403 +3310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 327 + + + 10407 .loc 1 3310 21 is_stmt 0 view .LVU3404 + 10408 0008 A0F85820 strh r2, [r0, #88] @ movhi +3312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 10409 .loc 1 3312 3 is_stmt 1 view .LVU3405 +3312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 10410 .loc 1 3312 20 is_stmt 0 view .LVU3406 + 10411 000c 0022 movs r2, #0 + 10412 .LVL880: +3312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 10413 .loc 1 3312 20 view .LVU3407 + 10414 000e C0F88420 str r2, [r0, #132] +3313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10415 .loc 1 3313 3 is_stmt 1 view .LVU3408 +3313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10416 .loc 1 3313 18 is_stmt 0 view .LVU3409 + 10417 0012 2222 movs r2, #34 + 10418 0014 C0F88020 str r2, [r0, #128] +3315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10419 .loc 1 3315 3 is_stmt 1 view .LVU3410 +3315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10420 .loc 1 3315 12 is_stmt 0 view .LVU3411 + 10421 0018 426F ldr r2, [r0, #116] +3315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10422 .loc 1 3315 6 view .LVU3412 + 10423 001a 8AB1 cbz r2, .L550 +3318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10424 .loc 1 3318 5 is_stmt 1 view .LVU3413 +3318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10425 .loc 1 3318 37 is_stmt 0 view .LVU3414 + 10426 001c 1F49 ldr r1, .L558 + 10427 .LVL881: +3318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10428 .loc 1 3318 37 view .LVU3415 + 10429 001e D163 str r1, [r2, #60] + 10430 .LVL882: +3321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10431 .loc 1 3321 5 is_stmt 1 view .LVU3416 +3321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10432 .loc 1 3321 10 is_stmt 0 view .LVU3417 + 10433 0020 426F ldr r2, [r0, #116] +3321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10434 .loc 1 3321 41 view .LVU3418 + 10435 0022 1F49 ldr r1, .L558+4 + 10436 0024 1164 str r1, [r2, #64] +3324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10437 .loc 1 3324 5 is_stmt 1 view .LVU3419 +3324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10438 .loc 1 3324 10 is_stmt 0 view .LVU3420 + 10439 0026 426F ldr r2, [r0, #116] +3324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10440 .loc 1 3324 38 view .LVU3421 + 10441 0028 1E49 ldr r1, .L558+8 + 10442 002a D164 str r1, [r2, #76] +3327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10443 .loc 1 3327 5 is_stmt 1 view .LVU3422 +3327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10444 .loc 1 3327 10 is_stmt 0 view .LVU3423 + ARM GAS /tmp/ccQxTlMj.s page 328 + + + 10445 002c 426F ldr r2, [r0, #116] +3327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10446 .loc 1 3327 38 view .LVU3424 + 10447 002e 0021 movs r1, #0 + 10448 0030 1165 str r1, [r2, #80] +3330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10449 .loc 1 3330 5 is_stmt 1 view .LVU3425 +3330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10450 .loc 1 3330 57 is_stmt 0 view .LVU3426 + 10451 0032 0168 ldr r1, [r0] +3330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10452 .loc 1 3330 9 view .LVU3427 + 10453 0034 426D ldr r2, [r0, #84] + 10454 0036 2431 adds r1, r1, #36 + 10455 0038 406F ldr r0, [r0, #116] + 10456 .LVL883: +3330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10457 .loc 1 3330 9 view .LVU3428 + 10458 003a FFF7FEFF bl HAL_DMA_Start_IT + 10459 .LVL884: +3330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10460 .loc 1 3330 8 discriminator 1 view .LVU3429 + 10461 003e 20BB cbnz r0, .L557 + 10462 .L550: +3343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10463 .loc 1 3343 3 is_stmt 1 view .LVU3430 +3343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10464 .loc 1 3343 18 is_stmt 0 view .LVU3431 + 10465 0040 2369 ldr r3, [r4, #16] +3343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10466 .loc 1 3343 6 view .LVU3432 + 10467 0042 43B1 cbz r3, .L554 + 10468 .L553: +3345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10469 .loc 1 3345 5 is_stmt 1 discriminator 1 view .LVU3433 + 10470 .LBB807: +3345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10471 .loc 1 3345 5 discriminator 1 view .LVU3434 +3345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10472 .loc 1 3345 5 discriminator 1 view .LVU3435 +3345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10473 .loc 1 3345 5 discriminator 1 view .LVU3436 + 10474 0044 2268 ldr r2, [r4] + 10475 .LVL885: + 10476 .LBB808: + 10477 .LBI808: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 10478 .loc 2 1068 31 view .LVU3437 + 10479 .LBB809: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 10480 .loc 2 1070 5 view .LVU3438 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10481 .loc 2 1072 4 view .LVU3439 + 10482 .syntax unified + 10483 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 10484 0046 52E8003F ldrex r3, [r2] + 10485 @ 0 "" 2 + ARM GAS /tmp/ccQxTlMj.s page 329 + + + 10486 .LVL886: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 10487 .loc 2 1073 4 view .LVU3440 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 10488 .loc 2 1073 4 is_stmt 0 view .LVU3441 + 10489 .thumb + 10490 .syntax unified + 10491 .LBE809: + 10492 .LBE808: +3345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10493 .loc 1 3345 5 discriminator 1 view .LVU3442 + 10494 004a 43F48073 orr r3, r3, #256 + 10495 .LVL887: +3345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10496 .loc 1 3345 5 is_stmt 1 discriminator 1 view .LVU3443 + 10497 .LBB810: + 10498 .LBI810: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 10499 .loc 2 1119 31 view .LVU3444 + 10500 .LBB811: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 10501 .loc 2 1121 4 view .LVU3445 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10502 .loc 2 1123 4 view .LVU3446 + 10503 .syntax unified + 10504 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 10505 004e 42E80031 strex r1, r3, [r2] + 10506 @ 0 "" 2 + 10507 .LVL888: + 10508 .loc 2 1124 4 view .LVU3447 + 10509 .loc 2 1124 4 is_stmt 0 view .LVU3448 + 10510 .thumb + 10511 .syntax unified + 10512 .LBE811: + 10513 .LBE810: +3345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10514 .loc 1 3345 5 discriminator 1 view .LVU3449 + 10515 0052 0029 cmp r1, #0 + 10516 0054 F6D1 bne .L553 + 10517 .LVL889: + 10518 .L554: +3345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10519 .loc 1 3345 5 discriminator 1 view .LVU3450 + 10520 .LBE807: +3345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10521 .loc 1 3345 5 is_stmt 1 discriminator 2 view .LVU3451 +3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10522 .loc 1 3349 3 discriminator 1 view .LVU3452 + 10523 .LBB812: +3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10524 .loc 1 3349 3 discriminator 1 view .LVU3453 +3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10525 .loc 1 3349 3 discriminator 1 view .LVU3454 +3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10526 .loc 1 3349 3 discriminator 1 view .LVU3455 + 10527 0056 2268 ldr r2, [r4] + 10528 .LVL890: + ARM GAS /tmp/ccQxTlMj.s page 330 + + + 10529 .LBB813: + 10530 .LBI813: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 10531 .loc 2 1068 31 view .LVU3456 + 10532 .LBB814: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 10533 .loc 2 1070 5 view .LVU3457 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10534 .loc 2 1072 4 view .LVU3458 + 10535 0058 02F10803 add r3, r2, #8 + 10536 .LVL891: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10537 .loc 2 1072 4 is_stmt 0 view .LVU3459 + 10538 .syntax unified + 10539 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 10540 005c 53E8003F ldrex r3, [r3] + 10541 @ 0 "" 2 + 10542 .LVL892: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 10543 .loc 2 1073 4 is_stmt 1 view .LVU3460 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 10544 .loc 2 1073 4 is_stmt 0 view .LVU3461 + 10545 .thumb + 10546 .syntax unified + 10547 .LBE814: + 10548 .LBE813: +3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10549 .loc 1 3349 3 discriminator 1 view .LVU3462 + 10550 0060 43F00103 orr r3, r3, #1 + 10551 .LVL893: +3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10552 .loc 1 3349 3 is_stmt 1 discriminator 1 view .LVU3463 + 10553 .LBB815: + 10554 .LBI815: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 10555 .loc 2 1119 31 view .LVU3464 + 10556 .LBB816: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 10557 .loc 2 1121 4 view .LVU3465 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10558 .loc 2 1123 4 view .LVU3466 + 10559 0064 0832 adds r2, r2, #8 + 10560 .LVL894: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10561 .loc 2 1123 4 is_stmt 0 view .LVU3467 + 10562 .syntax unified + 10563 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 10564 0066 42E80031 strex r1, r3, [r2] + 10565 @ 0 "" 2 + 10566 .LVL895: + 10567 .loc 2 1124 4 is_stmt 1 view .LVU3468 + 10568 .loc 2 1124 4 is_stmt 0 view .LVU3469 + 10569 .thumb + 10570 .syntax unified + 10571 .LBE816: + 10572 .LBE815: +3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + ARM GAS /tmp/ccQxTlMj.s page 331 + + + 10573 .loc 1 3349 3 discriminator 1 view .LVU3470 + 10574 006a 0029 cmp r1, #0 + 10575 006c F3D1 bne .L554 + 10576 .LVL896: + 10577 .L555: +3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10578 .loc 1 3349 3 discriminator 1 view .LVU3471 + 10579 .LBE812: +3349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10580 .loc 1 3349 3 is_stmt 1 discriminator 2 view .LVU3472 +3353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10581 .loc 1 3353 3 discriminator 1 view .LVU3473 + 10582 .LBB817: +3353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10583 .loc 1 3353 3 discriminator 1 view .LVU3474 +3353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10584 .loc 1 3353 3 discriminator 1 view .LVU3475 +3353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10585 .loc 1 3353 3 discriminator 1 view .LVU3476 + 10586 006e 2268 ldr r2, [r4] + 10587 .LVL897: + 10588 .LBB818: + 10589 .LBI818: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 10590 .loc 2 1068 31 view .LVU3477 + 10591 .LBB819: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 10592 .loc 2 1070 5 view .LVU3478 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10593 .loc 2 1072 4 view .LVU3479 + 10594 0070 02F10803 add r3, r2, #8 + 10595 .LVL898: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10596 .loc 2 1072 4 is_stmt 0 view .LVU3480 + 10597 .syntax unified + 10598 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 10599 0074 53E8003F ldrex r3, [r3] + 10600 @ 0 "" 2 + 10601 .LVL899: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 10602 .loc 2 1073 4 is_stmt 1 view .LVU3481 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 10603 .loc 2 1073 4 is_stmt 0 view .LVU3482 + 10604 .thumb + 10605 .syntax unified + 10606 .LBE819: + 10607 .LBE818: +3353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10608 .loc 1 3353 3 discriminator 1 view .LVU3483 + 10609 0078 43F04003 orr r3, r3, #64 + 10610 .LVL900: +3353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10611 .loc 1 3353 3 is_stmt 1 discriminator 1 view .LVU3484 + 10612 .LBB820: + 10613 .LBI820: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 10614 .loc 2 1119 31 view .LVU3485 + ARM GAS /tmp/ccQxTlMj.s page 332 + + + 10615 .LBB821: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 10616 .loc 2 1121 4 view .LVU3486 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10617 .loc 2 1123 4 view .LVU3487 + 10618 007c 0832 adds r2, r2, #8 + 10619 .LVL901: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10620 .loc 2 1123 4 is_stmt 0 view .LVU3488 + 10621 .syntax unified + 10622 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 10623 007e 42E80031 strex r1, r3, [r2] + 10624 @ 0 "" 2 + 10625 .LVL902: + 10626 .loc 2 1124 4 is_stmt 1 view .LVU3489 + 10627 .loc 2 1124 4 is_stmt 0 view .LVU3490 + 10628 .thumb + 10629 .syntax unified + 10630 .LBE821: + 10631 .LBE820: +3353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10632 .loc 1 3353 3 discriminator 1 view .LVU3491 + 10633 0082 0029 cmp r1, #0 + 10634 0084 F3D1 bne .L555 + 10635 .LBE817: +3355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10636 .loc 1 3355 10 view .LVU3492 + 10637 0086 0020 movs r0, #0 + 10638 .LVL903: + 10639 .L551: +3356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10640 .loc 1 3356 1 view .LVU3493 + 10641 0088 10BD pop {r4, pc} + 10642 .LVL904: + 10643 .L557: +3333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10644 .loc 1 3333 7 is_stmt 1 view .LVU3494 +3333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10645 .loc 1 3333 24 is_stmt 0 view .LVU3495 + 10646 008a 1023 movs r3, #16 + 10647 008c C4F88430 str r3, [r4, #132] +3336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10648 .loc 1 3336 7 is_stmt 1 view .LVU3496 +3336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10649 .loc 1 3336 22 is_stmt 0 view .LVU3497 + 10650 0090 2023 movs r3, #32 + 10651 0092 C4F88030 str r3, [r4, #128] +3338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10652 .loc 1 3338 7 is_stmt 1 view .LVU3498 +3338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10653 .loc 1 3338 14 is_stmt 0 view .LVU3499 + 10654 0096 0120 movs r0, #1 + 10655 0098 F6E7 b .L551 + 10656 .L559: + 10657 009a 00BF .align 2 + 10658 .L558: + 10659 009c 00000000 .word UART_DMAReceiveCplt + ARM GAS /tmp/ccQxTlMj.s page 333 + + + 10660 00a0 00000000 .word UART_DMARxHalfCplt + 10661 00a4 00000000 .word UART_DMAError + 10662 .cfi_endproc + 10663 .LFE190: + 10665 .section .text.HAL_UART_Receive_DMA,"ax",%progbits + 10666 .align 1 + 10667 .global HAL_UART_Receive_DMA + 10668 .syntax unified + 10669 .thumb + 10670 .thumb_func + 10672 HAL_UART_Receive_DMA: + 10673 .LVL905: + 10674 .LFB153: +1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that a Rx process is not already ongoing */ + 10675 .loc 1 1417 1 is_stmt 1 view -0 + 10676 .cfi_startproc + 10677 @ args = 0, pretend = 0, frame = 0 + 10678 @ frame_needed = 0, uses_anonymous_args = 0 +1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** /* Check that a Rx process is not already ongoing */ + 10679 .loc 1 1417 1 is_stmt 0 view .LVU3501 + 10680 0000 38B5 push {r3, r4, r5, lr} + 10681 .LCFI54: + 10682 .cfi_def_cfa_offset 16 + 10683 .cfi_offset 3, -16 + 10684 .cfi_offset 4, -12 + 10685 .cfi_offset 5, -8 + 10686 .cfi_offset 14, -4 +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10687 .loc 1 1419 3 is_stmt 1 view .LVU3502 +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10688 .loc 1 1419 12 is_stmt 0 view .LVU3503 + 10689 0002 D0F88030 ldr r3, [r0, #128] +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10690 .loc 1 1419 6 view .LVU3504 + 10691 0006 202B cmp r3, #32 + 10692 0008 16D1 bne .L564 +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10693 .loc 1 1421 5 is_stmt 1 view .LVU3505 +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10694 .loc 1 1421 8 is_stmt 0 view .LVU3506 + 10695 000a 002A cmp r2, #0 + 10696 000c 18BF it ne + 10697 000e 0029 cmpne r1, #0 + 10698 0010 14D0 beq .L565 +1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10699 .loc 1 1427 5 is_stmt 1 view .LVU3507 +1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10700 .loc 1 1427 26 is_stmt 0 view .LVU3508 + 10701 0012 0023 movs r3, #0 + 10702 0014 0366 str r3, [r0, #96] +1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10703 .loc 1 1430 5 is_stmt 1 view .LVU3509 +1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + 10704 .loc 1 1430 9 is_stmt 0 view .LVU3510 + 10705 0016 0368 ldr r3, [r0] + 10706 0018 5B68 ldr r3, [r3, #4] +1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** { + ARM GAS /tmp/ccQxTlMj.s page 334 + + + 10707 .loc 1 1430 8 view .LVU3511 + 10708 001a 13F4000F tst r3, #8388608 + 10709 001e 08D0 beq .L562 + 10710 .L563: +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10711 .loc 1 1433 7 is_stmt 1 discriminator 1 view .LVU3512 + 10712 .LBB822: +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10713 .loc 1 1433 7 discriminator 1 view .LVU3513 +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10714 .loc 1 1433 7 discriminator 1 view .LVU3514 +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10715 .loc 1 1433 7 discriminator 1 view .LVU3515 + 10716 0020 0468 ldr r4, [r0] + 10717 .LVL906: + 10718 .LBB823: + 10719 .LBI823: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 10720 .loc 2 1068 31 view .LVU3516 + 10721 .LBB824: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 10722 .loc 2 1070 5 view .LVU3517 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10723 .loc 2 1072 4 view .LVU3518 + 10724 .syntax unified + 10725 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 10726 0022 54E8003F ldrex r3, [r4] + 10727 @ 0 "" 2 + 10728 .LVL907: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 10729 .loc 2 1073 4 view .LVU3519 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 10730 .loc 2 1073 4 is_stmt 0 view .LVU3520 + 10731 .thumb + 10732 .syntax unified + 10733 .LBE824: + 10734 .LBE823: +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10735 .loc 1 1433 7 discriminator 1 view .LVU3521 + 10736 0026 43F08063 orr r3, r3, #67108864 + 10737 .LVL908: +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10738 .loc 1 1433 7 is_stmt 1 discriminator 1 view .LVU3522 + 10739 .LBB825: + 10740 .LBI825: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 10741 .loc 2 1119 31 view .LVU3523 + 10742 .LBB826: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 10743 .loc 2 1121 4 view .LVU3524 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 10744 .loc 2 1123 4 view .LVU3525 + 10745 .syntax unified + 10746 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 10747 002a 44E80035 strex r5, r3, [r4] + 10748 @ 0 "" 2 + 10749 .LVL909: + ARM GAS /tmp/ccQxTlMj.s page 335 + + + 10750 .loc 2 1124 4 view .LVU3526 + 10751 .loc 2 1124 4 is_stmt 0 view .LVU3527 + 10752 .thumb + 10753 .syntax unified + 10754 .LBE826: + 10755 .LBE825: +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10756 .loc 1 1433 7 discriminator 1 view .LVU3528 + 10757 002e 002D cmp r5, #0 + 10758 0030 F6D1 bne .L563 + 10759 .LVL910: + 10760 .L562: +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10761 .loc 1 1433 7 discriminator 1 view .LVU3529 + 10762 .LBE822: +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10763 .loc 1 1433 7 is_stmt 1 discriminator 2 view .LVU3530 +1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10764 .loc 1 1436 5 view .LVU3531 +1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10765 .loc 1 1436 13 is_stmt 0 view .LVU3532 + 10766 0032 FFF7FEFF bl UART_Start_Receive_DMA + 10767 .LVL911: +1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10768 .loc 1 1436 13 view .LVU3533 + 10769 0036 00E0 b .L561 + 10770 .LVL912: + 10771 .L564: +1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10772 .loc 1 1440 12 view .LVU3534 + 10773 0038 0220 movs r0, #2 + 10774 .LVL913: + 10775 .L561: +1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** + 10776 .loc 1 1442 1 view .LVU3535 + 10777 003a 38BD pop {r3, r4, r5, pc} + 10778 .LVL914: + 10779 .L565: +1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10780 .loc 1 1423 14 view .LVU3536 + 10781 003c 0120 movs r0, #1 + 10782 .LVL915: +1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c **** } + 10783 .loc 1 1423 14 view .LVU3537 + 10784 003e FCE7 b .L561 + 10785 .cfi_endproc + 10786 .LFE153: + 10788 .text + 10789 .Letext0: + 10790 .file 3 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 10791 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 10792 .file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + 10793 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 10794 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h" + 10795 .file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h" + 10796 .file 9 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h" + 10797 .file 10 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h" + ARM GAS /tmp/ccQxTlMj.s page 336 + + + ARM GAS /tmp/ccQxTlMj.s page 337 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_uart.c + /tmp/ccQxTlMj.s:20 .text.UART_EndTxTransfer:00000000 $t + /tmp/ccQxTlMj.s:25 .text.UART_EndTxTransfer:00000000 UART_EndTxTransfer + /tmp/ccQxTlMj.s:97 .text.UART_EndRxTransfer:00000000 $t + /tmp/ccQxTlMj.s:102 .text.UART_EndRxTransfer:00000000 UART_EndRxTransfer + /tmp/ccQxTlMj.s:297 .text.UART_TxISR_8BIT:00000000 $t + /tmp/ccQxTlMj.s:302 .text.UART_TxISR_8BIT:00000000 UART_TxISR_8BIT + /tmp/ccQxTlMj.s:462 .text.UART_TxISR_16BIT:00000000 $t + /tmp/ccQxTlMj.s:467 .text.UART_TxISR_16BIT:00000000 UART_TxISR_16BIT + /tmp/ccQxTlMj.s:634 .text.HAL_UART_MspInit:00000000 $t + /tmp/ccQxTlMj.s:640 .text.HAL_UART_MspInit:00000000 HAL_UART_MspInit + /tmp/ccQxTlMj.s:655 .text.HAL_UART_MspDeInit:00000000 $t + /tmp/ccQxTlMj.s:661 .text.HAL_UART_MspDeInit:00000000 HAL_UART_MspDeInit + /tmp/ccQxTlMj.s:676 .text.HAL_UART_DeInit:00000000 $t + /tmp/ccQxTlMj.s:682 .text.HAL_UART_DeInit:00000000 HAL_UART_DeInit + /tmp/ccQxTlMj.s:771 .text.HAL_UART_Transmit_IT:00000000 $t + /tmp/ccQxTlMj.s:777 .text.HAL_UART_Transmit_IT:00000000 HAL_UART_Transmit_IT + /tmp/ccQxTlMj.s:915 .text.HAL_UART_Transmit_IT:0000005c $d + /tmp/ccQxTlMj.s:921 .text.HAL_UART_Transmit_DMA:00000000 $t + /tmp/ccQxTlMj.s:927 .text.HAL_UART_Transmit_DMA:00000000 HAL_UART_Transmit_DMA + /tmp/ccQxTlMj.s:1120 .text.HAL_UART_Transmit_DMA:00000088 $d + /tmp/ccQxTlMj.s:2935 .text.UART_DMATransmitCplt:00000000 UART_DMATransmitCplt + /tmp/ccQxTlMj.s:3205 .text.UART_DMATxHalfCplt:00000000 UART_DMATxHalfCplt + /tmp/ccQxTlMj.s:3300 .text.UART_DMAError:00000000 UART_DMAError + /tmp/ccQxTlMj.s:1127 .text.HAL_UART_DMAPause:00000000 $t + /tmp/ccQxTlMj.s:1133 .text.HAL_UART_DMAPause:00000000 HAL_UART_DMAPause + /tmp/ccQxTlMj.s:1427 .text.HAL_UART_DMAResume:00000000 $t + /tmp/ccQxTlMj.s:1433 .text.HAL_UART_DMAResume:00000000 HAL_UART_DMAResume + /tmp/ccQxTlMj.s:1706 .text.HAL_UART_DMAStop:00000000 $t + /tmp/ccQxTlMj.s:1712 .text.HAL_UART_DMAStop:00000000 HAL_UART_DMAStop + /tmp/ccQxTlMj.s:1960 .text.HAL_UART_Abort:00000000 $t + /tmp/ccQxTlMj.s:1966 .text.HAL_UART_Abort:00000000 HAL_UART_Abort + /tmp/ccQxTlMj.s:2394 .text.HAL_UART_AbortTransmit:00000000 $t + /tmp/ccQxTlMj.s:2400 .text.HAL_UART_AbortTransmit:00000000 HAL_UART_AbortTransmit + /tmp/ccQxTlMj.s:2586 .text.HAL_UART_AbortReceive:00000000 $t + /tmp/ccQxTlMj.s:2592 .text.HAL_UART_AbortReceive:00000000 HAL_UART_AbortReceive + /tmp/ccQxTlMj.s:2909 .text.HAL_UART_TxCpltCallback:00000000 $t + /tmp/ccQxTlMj.s:2915 .text.HAL_UART_TxCpltCallback:00000000 HAL_UART_TxCpltCallback + /tmp/ccQxTlMj.s:2930 .text.UART_DMATransmitCplt:00000000 $t + /tmp/ccQxTlMj.s:3091 .text.UART_EndTransmit_IT:00000000 $t + /tmp/ccQxTlMj.s:3096 .text.UART_EndTransmit_IT:00000000 UART_EndTransmit_IT + /tmp/ccQxTlMj.s:3179 .text.HAL_UART_TxHalfCpltCallback:00000000 $t + /tmp/ccQxTlMj.s:3185 .text.HAL_UART_TxHalfCpltCallback:00000000 HAL_UART_TxHalfCpltCallback + /tmp/ccQxTlMj.s:3200 .text.UART_DMATxHalfCplt:00000000 $t + /tmp/ccQxTlMj.s:3232 .text.HAL_UART_RxCpltCallback:00000000 $t + /tmp/ccQxTlMj.s:3238 .text.HAL_UART_RxCpltCallback:00000000 HAL_UART_RxCpltCallback + /tmp/ccQxTlMj.s:3253 .text.HAL_UART_RxHalfCpltCallback:00000000 $t + /tmp/ccQxTlMj.s:3259 .text.HAL_UART_RxHalfCpltCallback:00000000 HAL_UART_RxHalfCpltCallback + /tmp/ccQxTlMj.s:3274 .text.HAL_UART_ErrorCallback:00000000 $t + /tmp/ccQxTlMj.s:3280 .text.HAL_UART_ErrorCallback:00000000 HAL_UART_ErrorCallback + /tmp/ccQxTlMj.s:3295 .text.UART_DMAError:00000000 $t + /tmp/ccQxTlMj.s:3390 .text.UART_DMAAbortOnError:00000000 $t + /tmp/ccQxTlMj.s:3395 .text.UART_DMAAbortOnError:00000000 UART_DMAAbortOnError + /tmp/ccQxTlMj.s:3428 .text.HAL_UART_AbortCpltCallback:00000000 $t + /tmp/ccQxTlMj.s:3434 .text.HAL_UART_AbortCpltCallback:00000000 HAL_UART_AbortCpltCallback + /tmp/ccQxTlMj.s:3449 .text.HAL_UART_Abort_IT:00000000 $t + ARM GAS /tmp/ccQxTlMj.s page 338 + + + /tmp/ccQxTlMj.s:3455 .text.HAL_UART_Abort_IT:00000000 HAL_UART_Abort_IT + /tmp/ccQxTlMj.s:3931 .text.HAL_UART_Abort_IT:00000128 $d + /tmp/ccQxTlMj.s:4020 .text.UART_DMATxAbortCallback:00000000 UART_DMATxAbortCallback + /tmp/ccQxTlMj.s:3942 .text.UART_DMARxAbortCallback:00000000 UART_DMARxAbortCallback + /tmp/ccQxTlMj.s:3937 .text.UART_DMARxAbortCallback:00000000 $t + /tmp/ccQxTlMj.s:4015 .text.UART_DMATxAbortCallback:00000000 $t + /tmp/ccQxTlMj.s:4088 .text.HAL_UART_AbortTransmitCpltCallback:00000000 $t + /tmp/ccQxTlMj.s:4094 .text.HAL_UART_AbortTransmitCpltCallback:00000000 HAL_UART_AbortTransmitCpltCallback + /tmp/ccQxTlMj.s:4109 .text.HAL_UART_AbortTransmit_IT:00000000 $t + /tmp/ccQxTlMj.s:4115 .text.HAL_UART_AbortTransmit_IT:00000000 HAL_UART_AbortTransmit_IT + /tmp/ccQxTlMj.s:4323 .text.HAL_UART_AbortTransmit_IT:0000007c $d + /tmp/ccQxTlMj.s:4333 .text.UART_DMATxOnlyAbortCallback:00000000 UART_DMATxOnlyAbortCallback + /tmp/ccQxTlMj.s:4328 .text.UART_DMATxOnlyAbortCallback:00000000 $t + /tmp/ccQxTlMj.s:4367 .text.HAL_UART_AbortReceiveCpltCallback:00000000 $t + /tmp/ccQxTlMj.s:4373 .text.HAL_UART_AbortReceiveCpltCallback:00000000 HAL_UART_AbortReceiveCpltCallback + /tmp/ccQxTlMj.s:4388 .text.HAL_UART_AbortReceive_IT:00000000 $t + /tmp/ccQxTlMj.s:4394 .text.HAL_UART_AbortReceive_IT:00000000 HAL_UART_AbortReceive_IT + /tmp/ccQxTlMj.s:4739 .text.HAL_UART_AbortReceive_IT:000000c8 $d + /tmp/ccQxTlMj.s:4749 .text.UART_DMARxOnlyAbortCallback:00000000 UART_DMARxOnlyAbortCallback + /tmp/ccQxTlMj.s:4744 .text.UART_DMARxOnlyAbortCallback:00000000 $t + /tmp/ccQxTlMj.s:4795 .text.HAL_UARTEx_RxEventCallback:00000000 $t + /tmp/ccQxTlMj.s:4801 .text.HAL_UARTEx_RxEventCallback:00000000 HAL_UARTEx_RxEventCallback + /tmp/ccQxTlMj.s:4817 .text.UART_RxISR_8BIT:00000000 $t + /tmp/ccQxTlMj.s:4822 .text.UART_RxISR_8BIT:00000000 UART_RxISR_8BIT + /tmp/ccQxTlMj.s:5172 .text.UART_RxISR_16BIT:00000000 $t + /tmp/ccQxTlMj.s:5177 .text.UART_RxISR_16BIT:00000000 UART_RxISR_16BIT + /tmp/ccQxTlMj.s:5527 .text.UART_DMARxHalfCplt:00000000 $t + /tmp/ccQxTlMj.s:5532 .text.UART_DMARxHalfCplt:00000000 UART_DMARxHalfCplt + /tmp/ccQxTlMj.s:5580 .text.UART_DMAReceiveCplt:00000000 $t + /tmp/ccQxTlMj.s:5585 .text.UART_DMAReceiveCplt:00000000 UART_DMAReceiveCplt + /tmp/ccQxTlMj.s:5879 .text.HAL_UARTEx_WakeupCallback:00000000 $t + /tmp/ccQxTlMj.s:5885 .text.HAL_UARTEx_WakeupCallback:00000000 HAL_UARTEx_WakeupCallback + /tmp/ccQxTlMj.s:5900 .text.HAL_UART_IRQHandler:00000000 $t + /tmp/ccQxTlMj.s:5906 .text.HAL_UART_IRQHandler:00000000 HAL_UART_IRQHandler + /tmp/ccQxTlMj.s:6828 .text.HAL_UART_IRQHandler:000002e0 $d + /tmp/ccQxTlMj.s:6834 .text.HAL_UART_ReceiverTimeout_Config:00000000 $t + /tmp/ccQxTlMj.s:6840 .text.HAL_UART_ReceiverTimeout_Config:00000000 HAL_UART_ReceiverTimeout_Config + /tmp/ccQxTlMj.s:6861 .text.HAL_UART_EnableReceiverTimeout:00000000 $t + /tmp/ccQxTlMj.s:6867 .text.HAL_UART_EnableReceiverTimeout:00000000 HAL_UART_EnableReceiverTimeout + /tmp/ccQxTlMj.s:6932 .text.HAL_UART_DisableReceiverTimeout:00000000 $t + /tmp/ccQxTlMj.s:6938 .text.HAL_UART_DisableReceiverTimeout:00000000 HAL_UART_DisableReceiverTimeout + /tmp/ccQxTlMj.s:7003 .text.HAL_MultiProcessor_EnterMuteMode:00000000 $t + /tmp/ccQxTlMj.s:7009 .text.HAL_MultiProcessor_EnterMuteMode:00000000 HAL_MultiProcessor_EnterMuteMode + /tmp/ccQxTlMj.s:7028 .text.HAL_HalfDuplex_EnableTransmitter:00000000 $t + /tmp/ccQxTlMj.s:7034 .text.HAL_HalfDuplex_EnableTransmitter:00000000 HAL_HalfDuplex_EnableTransmitter + /tmp/ccQxTlMj.s:7187 .text.HAL_HalfDuplex_EnableReceiver:00000000 $t + /tmp/ccQxTlMj.s:7193 .text.HAL_HalfDuplex_EnableReceiver:00000000 HAL_HalfDuplex_EnableReceiver + /tmp/ccQxTlMj.s:7346 .text.HAL_LIN_SendBreak:00000000 $t + /tmp/ccQxTlMj.s:7352 .text.HAL_LIN_SendBreak:00000000 HAL_LIN_SendBreak + /tmp/ccQxTlMj.s:7405 .text.HAL_UART_GetState:00000000 $t + /tmp/ccQxTlMj.s:7411 .text.HAL_UART_GetState:00000000 HAL_UART_GetState + /tmp/ccQxTlMj.s:7439 .text.HAL_UART_GetError:00000000 $t + /tmp/ccQxTlMj.s:7445 .text.HAL_UART_GetError:00000000 HAL_UART_GetError + /tmp/ccQxTlMj.s:7463 .text.UART_SetConfig:00000000 $t + /tmp/ccQxTlMj.s:7469 .text.UART_SetConfig:00000000 UART_SetConfig + /tmp/ccQxTlMj.s:7596 .text.UART_SetConfig:0000008a $d + /tmp/ccQxTlMj.s:7600 .text.UART_SetConfig:0000008e $t + ARM GAS /tmp/ccQxTlMj.s page 339 + + + /tmp/ccQxTlMj.s:7617 .text.UART_SetConfig:000000a4 $d + /tmp/ccQxTlMj.s:7627 .text.UART_SetConfig:000000b6 $t + /tmp/ccQxTlMj.s:7658 .text.UART_SetConfig:000000d4 $d + /tmp/ccQxTlMj.s:7933 .text.UART_SetConfig:00000250 $d + /tmp/ccQxTlMj.s:7946 .text.UART_SetConfig:0000025c $d + /tmp/ccQxTlMj.s:7959 .text.UART_SetConfig:00000284 $t + /tmp/ccQxTlMj.s:8134 .text.UART_SetConfig:00000324 $d + /tmp/ccQxTlMj.s:8139 .text.UART_AdvFeatureConfig:00000000 $t + /tmp/ccQxTlMj.s:8145 .text.UART_AdvFeatureConfig:00000000 UART_AdvFeatureConfig + /tmp/ccQxTlMj.s:8297 .text.UART_WaitOnFlagUntilTimeout:00000000 $t + /tmp/ccQxTlMj.s:8303 .text.UART_WaitOnFlagUntilTimeout:00000000 UART_WaitOnFlagUntilTimeout + /tmp/ccQxTlMj.s:8444 .text.HAL_UART_Transmit:00000000 $t + /tmp/ccQxTlMj.s:8450 .text.HAL_UART_Transmit:00000000 HAL_UART_Transmit + /tmp/ccQxTlMj.s:8660 .text.HAL_UART_Receive:00000000 $t + /tmp/ccQxTlMj.s:8666 .text.HAL_UART_Receive:00000000 HAL_UART_Receive + /tmp/ccQxTlMj.s:8920 .text.UART_CheckIdleState:00000000 $t + /tmp/ccQxTlMj.s:8926 .text.UART_CheckIdleState:00000000 UART_CheckIdleState + /tmp/ccQxTlMj.s:9231 .text.HAL_UART_Init:00000000 $t + /tmp/ccQxTlMj.s:9237 .text.HAL_UART_Init:00000000 HAL_UART_Init + /tmp/ccQxTlMj.s:9341 .text.HAL_HalfDuplex_Init:00000000 $t + /tmp/ccQxTlMj.s:9347 .text.HAL_HalfDuplex_Init:00000000 HAL_HalfDuplex_Init + /tmp/ccQxTlMj.s:9455 .text.HAL_LIN_Init:00000000 $t + /tmp/ccQxTlMj.s:9461 .text.HAL_LIN_Init:00000000 HAL_LIN_Init + /tmp/ccQxTlMj.s:9613 .text.HAL_MultiProcessor_Init:00000000 $t + /tmp/ccQxTlMj.s:9619 .text.HAL_MultiProcessor_Init:00000000 HAL_MultiProcessor_Init + /tmp/ccQxTlMj.s:9747 .text.HAL_MultiProcessor_EnableMuteMode:00000000 $t + /tmp/ccQxTlMj.s:9753 .text.HAL_MultiProcessor_EnableMuteMode:00000000 HAL_MultiProcessor_EnableMuteMode + /tmp/ccQxTlMj.s:9854 .text.HAL_MultiProcessor_DisableMuteMode:00000000 $t + /tmp/ccQxTlMj.s:9860 .text.HAL_MultiProcessor_DisableMuteMode:00000000 HAL_MultiProcessor_DisableMuteMode + /tmp/ccQxTlMj.s:9961 .text.UART_Start_Receive_IT:00000000 $t + /tmp/ccQxTlMj.s:9967 .text.UART_Start_Receive_IT:00000000 UART_Start_Receive_IT + /tmp/ccQxTlMj.s:10252 .text.UART_Start_Receive_IT:000000cc $d + /tmp/ccQxTlMj.s:10259 .text.HAL_UART_Receive_IT:00000000 $t + /tmp/ccQxTlMj.s:10265 .text.HAL_UART_Receive_IT:00000000 HAL_UART_Receive_IT + /tmp/ccQxTlMj.s:10382 .text.UART_Start_Receive_DMA:00000000 $t + /tmp/ccQxTlMj.s:10388 .text.UART_Start_Receive_DMA:00000000 UART_Start_Receive_DMA + /tmp/ccQxTlMj.s:10659 .text.UART_Start_Receive_DMA:0000009c $d + /tmp/ccQxTlMj.s:10666 .text.HAL_UART_Receive_DMA:00000000 $t + /tmp/ccQxTlMj.s:10672 .text.HAL_UART_Receive_DMA:00000000 HAL_UART_Receive_DMA + /tmp/ccQxTlMj.s:7671 .text.UART_SetConfig:000000e1 $d + /tmp/ccQxTlMj.s:7671 .text.UART_SetConfig:000000e2 $t + /tmp/ccQxTlMj.s:7942 .text.UART_SetConfig:00000259 $d + /tmp/ccQxTlMj.s:7942 .text.UART_SetConfig:0000025a $t + +UNDEFINED SYMBOLS +HAL_DMA_Start_IT +HAL_DMA_Abort +HAL_DMA_GetError +HAL_DMA_Abort_IT +HAL_RCC_GetPCLK1Freq +HAL_RCC_GetPCLK2Freq +HAL_RCC_GetSysClockFreq +HAL_GetTick diff --git a/build/stm32f7xx_hal_uart.o b/build/stm32f7xx_hal_uart.o new file mode 100644 index 0000000000000000000000000000000000000000..a8eaff49694aaa3ae3b88f0a8537ebab995a548c GIT binary patch literal 129304 zcmeFa33ydSw)eg349Uqr2Eq^_;2{A-0wD+@D#IaQ1Vsr15phC549L`oHtiSz6^FJF zaY9>Y=eBJX&~|8XZl^|WP*iM(Mr{o(4pC6))~nxdt=fB^eNGN~?|a|xKKDLvAD^{r z)vAA0{cF{#+O_vN!3z!>TWgGQypM5uImw*kwERtT(SZu+lt^{x}{g^FWoo>aah8lVu@YEbIfx$Ks0e+h_KB7%D`JH@5bjB zt&=$^eI#Bh>3hv_ouhcKueaD)3diFqwSx?%y0znOZ6}_)eX3jkE5E+8-H8w0D6vy+ z_krClzPE$Cf@7{=y&vw5qp`4EQxF%N!HW3<);Z;!PPMF^UI%UQ#$J+AC&+sG{7S83 znI`_|#BbX(!MSbE6sMx0P$Ti`StDCmx2H&iKFhquXA-YY(MFelV8{8r@2{u*@qXOw z`CyB0+uj@)e_$W9Y#R$x*`|)rvb7`Z^@wFF%!)QzTfEn9zn|T~eggYy(0}QE?&Zfz zDvQ1Q>;+|!$zRr6nLM@0_sVvk?Z@nau?H_a{h3+pPZyLnITgQQKgn&qTC1I2ySC(N z^td}Wman(OHpVn+|JfXS&|S%aeO>M`vI|OF$2Lk&ji-CM?7f2@Tz2~V^SAD4tn+3; z_K+gq8|)!{i<-8wQ;lTCb;r`)25)pKh?r`-Vw#&JH^t9MFHXf;EV4Ix{W*@T)&E@l zS2am=mp80zXv_ZAzvhgxdZpG8OHC#5UrX?1-?38%<`?99u6*H~>!rM)cmzquA_t>ZKtbflD zKaSKk!}Igjb)NgXN5rcW@amLmxvzz^T@z^c>C-qJ#KZ1I?-0Kf-yWM)^gPF2o?TBL;Y;u>gWB1~R_#%Fj z@e|8G}y(cpaMZ+FU> z|M;|13%l(zEzX^u`=UG7I!f-{I>vHlG9G3Y_nBrIF4rCRa&}xf;e`Tg_WnI5RC8~Q zm-mh~g&Mq_Ikqv>Fn;!1>ucubB}x{IoNES*JoSDekUY>{)QSC(8u;fBA=YTHu838aX7 z$^CmK7s(vn(Ja?n*{2v!+@2Lu$3uU!N6alrsunmctgw=tT=(@h1w z!XF{sUt$|&#A9MI+C7wqYa360OLzDE+1+LBdb5$~+#~1T-M4+6D`~FyQBNp?6alEJk!@{xvjBecjLa{rlQ@Ag^8AfE|imJn0j6=p}B;X zE!bGnVhVGbig!0&kkw@3Mbo&K#6u(572_o>AxaKg$9>tg*R(`Jwj|<~MEsJFTM{eG zQ;yD-q123}wz%7wpD#@2=djwx?RKWx{%Ts{T3h;ddOy%4BhAuQ!ZOlzGEyn?_WID4 zwk^F1do|g;%CnaJ$PQA!Zo0pNIK7rO**)ZfX4}F!Zu)aKb=VP>RWE2RVT}ymJ^8+3 zO())0R8ca`>#eS7+WZpM-;L{?%Hg|@zwZHJ>V}#NzMgcS+*w}Lc$?oJ-RLpeS3Y_fhju@(#K2v&sK=+mxJ6*coj;g3R)oROyZR9>@|KYpMeI7e~ zwyl=aN|1#c=h$~`v3sPjxHXlB))EG`&(}X1x4W^VWSY(W+eaVFlm0f{D>L}QN7nl6 zM{(ms2;Fk@ctWgv(Q6yDcmBEUq?{ZJSI*Bbt5ctZx{(+X>fCwWlSq zm)7zGBTq5NkJYRAk$QHgj&O!vaJcQYOG>YHN6q)2!R@-0Q@6Lrw&wGnX(#fN?G&Z( zk^4$WPyEktW(;~kpRb&vkqZuQ;u*l650*BBW|fSrL7qlTL#*MdBSMKzBXg&gH`F&& z>`v6b*MQ%r-ZHCVcBhfu8ZO6HJ-uY)b!|s>s`Z;gPTISy3Hs35Ua#owxmUN4O=_;diB`V*9N7zjDSoEpIf& zDxEI}U-;J@B`xjDex|J%WO^g=Utbfc__#S%v7@=D;-lvIZcF*${K^7tDZ5RZHaW<0 zB+qdwwl+s9UIE_(eslA57hfHYSDw)n-R4v-Y$~c;xFu5YWOH@pf-SL%$C{_Om?y)H zm9rGn(3Gfb0CR8ila({U+}%9hVsL74+nXAbAJyx66Cmp z;P}T4;KmICcY@%?4FGp+bEx7Nq#ha1iDw)hI0`wE{220wqaTKhBtL@uaP*F^P173cW8s~N@P=={+;!_0MP}UBpD(&sgTL(lB0373p4Z+La86R+Mbb^fOJ?f05Hj()GX!|0IOIJq}CJL{eMzuncc_KTtr zZJe>XrsKAXhQ{^Vs9B<@omz88GxwFmN6jYA88)7^-NYkE2;CudDsG+m!Aw2JcHixc zoL$lq<4(gqMD#l&N1QGzLaZif9dO}n&l>WrjRT(Yt&ya)!uTx|sr72wZLGf#>($z> z+}GH5q__H~d~1R`y5-PVV&+J1;W^CvzIjc;rO|KSskl%}<+MPL0;;@0+9{$29 z9MDwR(24VRr0~P0KYWo0l|Et08>{}>?iN)%oY)}b3jE7~s4E8+Nn z?SuD(4lQ@zV?Mxp#g*&LAuHEYGfqz4v95EjJ+#&-Z|r98Ku)jswm5x1XllR5RPy{W z?QhL@)jBCm6S}tT1BbPD?IU&a@&u=x3v)pl%^Ul$G z)|0VJW-L?Ov1B#f`bhb#g^&EebI1wtcH7Hml|PdB@`tvPYqQ;2bGBcgrP1vhzGyr- zw@IE^PGCeQG|JwQFW$)MPR&k_Slk!Q!xiyqbH%KZbyC`X`)?UnTSg#fh;V#=-eXRg zeeyq-?Z6miN|M7ow;n!Vkdlm^~U)v z=Z|!*4l_f zu`NE_+^|8OVV{{F-q0PU<^KEb>9ap@-yfP@#k4Q0Zw2eLT-I_+@9@=VB@OaUv}CH~ zQM6I+(Bg?V-Babe>`9#NdmYeZ`>1TyN8TT8UDK;Wt3JxLkE`i}w|+m;+g7)?H{IS6 zO@kk7Q_Gk*kviiJZCcvkR35VBnfb@J>itl^cR5MR2%YJvBb0MkqmG)=mUy^Q_0(|> z_Q$>1W%8;rG4U@*KW}z=C7KpISWw$uIL$w@6^lxrMWZ&^Or zl1;t$o4pfn++TkmG&}BR@Pl^$;~j(U;O$@+4!n_wG)xpvwlq#3wZl2k>HGB-SqrjX z$hSh@={w+(TI(76?TpVa z-%pg=x2+kUu2TJxT>q)xPsrOI@0%XkBTfA4=H&Z58R~y^oOey+IY)gKF*U|<^1J3c zPEMiYl)8@el29zWFHc3GNOlRZP$>K40umEDx{V}RBPAD#W^winMWW@B#G+SaJ5Km; zxm1-7qoK$tT*6=FaOuC#LFmziVwFpHVVKLneQprzaxQfA8>nPOqO;~LaPKA?q9ixfd=H(-~bt5Rh-OI=FPR*kH4lkddH=j-- zcY67v+*)bxE-&BC$$u*b;I}3$z2~fod>YC*3aZ-e=OMq_cc2n!@$!+pt#}~vg_n=z zjvPa?UwZlcyq9rtWS5sO${UnRez%uzm-idVf92&%^ZtT=BVUJ#)io7md3VS#zVXWA zdGEk3vd7DJ&wEMg|07gX1-Zt_l(Ar*LrD@@)X@mZl~SYe#}#weEJ zaJULKIej9ZhI87pW{8#kPULe7Bu2>}K(KiE2>Ag7i^Lj_qh8Fs?Mz-ILc*HP|OIl$a3RXWnQQ}8kuI+!S1z=7eV6cklwSLZa~ z;Ntf&W*?Ammx5E=lbOpt(9K4QM@jZzHybP7k6yEfxY_*TBWNIdxSK61K8(?1*SOhs z#YK`m%*~b-4`F!ON4VLt;stQdKFZC;i(%+wPjIu{i*FI|F>bb3@g)L2-p%%L!sCdi z?5Ux^rmNkkCl-G%*;~8XS)5$FRi^EBH+zCp5|PclU8KFa2PPflg6&~C zD2c2k6YkC>`_7QHJWQrU?=D60SXIshd{aD{8nJ430-WL*P>p$U5Gi)pe`8)8#ENgh zH!&{`@-+@(W8At$#h)>d*jP8)u6PQ}V|8w}w0I#dicNI0WllH?lCk5$O>ipe6+0>C zdttLlnwaW>oZ^p!+^KFhQrtsYY;d!&;#;NkbT^w{yb`C!=DXRV;uG*xY@wTNSKN{2 zV`sYA(&9BTu*Gh+thl}Odybop7yn7TaDkic?u4%;aAFsRPoj-*PwD1&ZI{z|G?!`- zxwwlnw$9X(D>$9Loq}7qnu2>#Lj}VbW~5-N44~jNS*C=#IP>9foC@JOY4jP}=*eO@ zQ|NBCh6Nbf)^J%Kd$njIO=uv;Uh5*d7s#++Io|b1}3xuR)-LT(De73nh^k$>hH%Y}=Wzm?H0C>1g&a+MM$uxn?;qHd^b4fT;SzPO@t=0F9??=bZY)i)mN^X~p<9x5q&jKaq z;QH+Iypq*kNe3a5yg2)q0np5S)n(b~J*L+zDr|#`9A~p!_?TZ41D$VzKSc*frVrLQ zQnqOB0>_+H*ydJ@S7W#e>C%pj`FUZ!1j#+f9b&v3s%CLv8!^6#yn%GB;lkP2xu3Z& zJL{A=j=8u{PobY-`~=zeLW)PB*z0Igfh+(YUqMkAq6X>qYci!M9T2BHL2j&I^;+lF ziciJd7eFNvuO}mi@dVOsE}3IdjzQo>&Y6RZ&i8m-YI)6}d^V!ICJEM&>q&?K5(BTi zE&_7_qP!kJS&ul%Ynoskxi+}9l-HjDJdY@^Pf>Ov$}2=**vE&iOVCy!+kIZw7v{*6 zb_63UMtLp6;5c%XA_HWt$Ey#R-iY!VfifI%l-Cu4b>zCjt);vs0hov=uhUUxAu=kZp{>l(_hMwHiD5RN0)+Ykd}FnIOX-C*uQl-Cm|8xhOvF2Oo- zy~nMkytV>(1yNpqM`=cs*Y_yjA&yh=9G6{vpg=#}OBR15#+EBk6!!2UeP~X>v`rk0T zk93tFmQcBo9;}P{*pT`MrQaaxqFNA+BiADk1LSz{>Y{=O`wXHkst^USE;?GUj$9|W zwbVs}0SrRaMMt3=iKvUFp-e^KC7k9V1K2PuuYQ)794*g8l-FdzI&z(g7$CbmUMs*{ zhS;e?*@#$PGX(3%b+%hedA$zc6-0UMLHQa{UTwIm=OOS~#^qY%&pxkVHl)fak0Z+K zV!=9cy$mrxE(fpvIta{xi1HeXBBxTz>q@~oa$V`xQeLM3I2lo1XQ9YJP&*M>()|U ze+BRkqP%vae2FNpoGf;EgiwEhi-h|5^ph6qn<>&z@AMlgny?$*<(SK;Y#KOa+wDDE zc%X!L0_zZ@tE{4SNF4|}*sQ{^Y$~%TJq^*pGJAaF8bb__BJeuc^TC{p=wPo#xeBp^ z%@?dAR~Tz89qe5Ims<%0k3(_7_fr5X-5> za=MhVOAzJMU2u+Edm#qMN(kx<+zjR>L^*9hS%+9oL<^kcTJ6?SPA>p>4pC0;puB}B zr!P@j5I!Z5rCj%u;4{y;4wt*8IJ_SrV;%lnfo_+k&iC!=5^o%v?KrZDnJALUw?L+V z*Kw4A>4fMw`lIwiGWwQUI*wWZqYxd(@hHb3Iu1D!&qG@Ic8le75oJq}Ouhy3na620 znClVcbRWv^k&M2jmU4O)z|)9wdK2XhL^;Xh&nF0|Vn@9cT z@(T_WcDG~w4Pu)su+448unEz@-mC0>A!GYn8@r=SqV4x6H`7@9b}IhXrb?R2;XrB- z+uTQObSlPU7$?Rd1(fb+vu|hSw*kWpF%IQo{%(!S(Jw|S2GfIdJd_UD#Y2m*)nXgi z#c{?bZ9OMqOLX=zPNyqm=X>1c8K?9{Y5q~4=i_Y#2+t?5{t>Y}pR_zb#_$oM!+w+A zd&nLoHxsAR5-6Js-F8=Ckt42IxQ{pf3)>8ocB`=VLTtNBZM*U|U@Fp;NOO83*LCz3 z|K)A;{qr(Pmms>(;L1m?x>*7_7Q8P08^BzL=t8>}H90^meMc`Ze`5K&&&qg;!?OE^tJp7(jJu)Kax`R@?rl>k8$Afpij zoW6=b+mh#FcL}Q5ZszT|5C@=ZaVFUuNg0M{VO z>mHQ55#{w1$`c6Tx`2xuaC%&cV&k?_HmUh;+_Geytw7CFe%#Kt>tPSp-H46bpV_#r zU@h&7^dR<~epOsLT~3Ufqul0dvDCHP7px;!32LdO?i&E0 zAENF%2BjWR_svFWK;R{uh9H9&j^%Z{<#hq&=ON0gk6@Fh1t4F0yjFo(i72n%qTGpC zUa|n}G8ilxwUpQ603Jh>*Q+R75aqQ4_wQ8u7LhGM4`|tV&<u?Ynu#(4(E*)<@(Uyo0Bd|+2U%V#D8CZP6aYX@2Cuw+ z3+7ftd2K^^9myB~)KXrb1K5cuuVNyw5K&$|QMw}>f@Hs$fLLD*v6Fu&Wd|e5DM6{- zYh+RkkX;_9Ixt5g%IQ>;>4@c|`;zWXy6aF&Ih_q)F`}G)h4M>8Io*bG3&Ll=M+tP( z-JNqbHl6c5{+xHWbN&eEhmifHj?}bc*w6ZPGnP$Aruhc)5Ur_SKLGO{qGQ;D@->oi zzNw{SXu}yWPtJkz8mU|qM8|Lt%7F-<-sV^d+@1OMrJk7XLXM!+92EDWcW3@EiQaiw zXCs|Yk^|As{G;V9>Pie(i19`_67I}DX(9DDV|Whn-zj`f#M^Nf+qo-b6KR9!xMjNv zyi)*jA9x*icQECMj{9JggAhCJqfr9y6sV=+J{rJSM8`cHot^D5zA`^O5mLWwUpN<0CphCtANv9 zKBBxTL_y#soGwQ8jeETIvAhOTJ_u1>3qbJudqnSFK>q6S8V}}3M0qu$oR3&u=c3sA z*AmgFrM#{Ka5bX59zl5sQC^!-HX-cTvi{`dZFf^Iuc$)y6&0^3pO#sFG!Q;pLCW4Y zrQD02NArhD^fc4bdx(vmNAr)8=&9f^wGU#W=h6HVC3?=rumI^gg^U>bcJsXPLcZ>j zFH-tEqTVbukV9-8&Pi*b0#W8tT!4^jK1I$pBrkaH+li+E{7*s zHAkR~M${W8qnwDqOZ>MA`IFDVE~0!PqP&&~Hu;hh$VK3l*QH=CL6q0cC^sRN z*A*y%mz>m6UK;?cLzLGGD9<6v>m8K05O$b{xrqPmN_)$4`jWC1L^(YwI7hCJBL>Jm z%#(7;W(SKR%Bc*c6Jj|%Em%jc&$+dfQ-1(*FjY>qD5DVNbUey&2%p~OO%CqntU!p| zfq5RKrnth3k+bqgN{p<;dL`0%Nkr?^F9-SnhWo`BH)@#$HE5 z=F%Q?p-;5^@(&f-*JE9Ubm=D>WB+{pV(oDZe?atA{Y>iaqB}b?iF`ei?xyrhL}z9a z2z#cMs5d}1fY+JH>BKuUL}#WeN*Q8j<|M)D%l&C?EuEPG0Qw_3Gow*z5uKS6QI1F8 zC6RVBa(Q=;*F?)}A>|7Y<#nZClW!t{90^`|T>|DJM0wqWvKq0xu0=8Wc67C9)KXsS z0NjTtujf#nMU>ZDC~qS05>9_WDsZ#)*D;n?3+107%4;nM`>OsfQUl}zk5>+J8%C7Z zU=%qvT3+`ER$tSvcWWuHaR81)l-JKt<|E4MVw7bF@x!^z#!nrJY;Pw(&^`ipH{-*J z5#76+38tDYl8EZg9vIF4;fEiL(^H~Q@BwViUa(Fd^SCUR5A(7JcE@=Mk=^tGy0R~< zKFq6@kTZ3JXm-AgJTH0g?iF^N8(?d0?&*c-F?oXo{{+@YkS@QF5Ir_eL-Z>QUx;zN zoMa~F>GxqBIX0CbT?W#(IWDiWeB)b>;XpB-FYKn+>TNlkWFch>PhG^pIj_CEke`iV zD$->vOU;~MksC4m9_g{1)mlP9kH=8LqCAbVi>211$t(KWE0V8Bq=?(h!Ymr=k!QaI z#G(gcam=g!Kzrm3l1#U*^o{WT?=$LFnvd{_X`k28$oJUtp;z_k;Qc%wwa*(VRmW0o zv{XM>eALlWKNG_lVjM2UQfs^n!*Yb?H^?09$W6{cmD~JWzxf@x2g?-PPK96FO5p-3 zH3ce-b}Mb}<#B4tJxnU?qQXu@AI%7G=U@kp z5#>~l5=Zz{n$0p3uwp;uk2Jzp=?FYg})-876pHuoNq66|qf9~wVsVvLZuf}>g;tw((gdOCSc93sT`X-WTkU%!! z6dhy>n9mR$WE5IqB;z2drGxAQpcK(T_Cx85=paX-)F68wWTiPL%y=3CgB%Q8cH!gv zF*f8LE@PZdOUFuUmFB)IDvild=}N!SnA}>aw3P}kNTojJ?p!Jjb;GN`?d1h3*zg*f zdx%spb-mil{b*?J5zE1t@zj(z*QQObeH|WhYswopTeFQHn0?G6(!_T;sZjYs!a~2x z8RB-LkG9|CjFo2*?PR68(LQd?RJvPJ_z#3Ksfy&M4anP>zCp z>5&GNckLGXvd0JLsp6l<)1dNV+(IAE8SJqQG)o1^zJg`Oc?uS$c;t1t__D$wfZvKKE&gI?rAm-wyrHNTQp>tc3S*}?1`%66reFaP~(Y>gO%hhhljWbMq;ki|A541O#v5xXRCV z43M9L*QL4~%o0SG>O&|GB987ywSslzI@YbFOLa4Vmk?d5EhwKMx>Tdw(!&V6?x4nK z{8Z0Pvdbkh9FtQdVOmCcDbn>N5N{(ttM-`Z=P2`Glnz0Z`6dwDin%r+21tMK%Df)T zctn{upv*)ZWxiFgj$F67wUqgJ0M0>_`AU=(h%&zu<#q&K!f7{>)8FIO#`1cM@<$Qn z^)3izkn2Z?0rH~9>oqX{hA6KHCyEf_D6fwN>&Ugmt);v=1L%k-uc0W1BFbw5N*w|( z;gpX@f8+Biw!BWG{8U7FeGQ6(2-okW2Oy__SAR8vIU7-4_o4hAag>+*PRclPjfqAr z<@FqZrxE3~1LY$`dHp-ew+OsCP@@-eFf(m$79B0Gw%qHB5am@0f{Eu^h8Q6K@ObS9 zrU#2;M0gOYG*G!Zdi1IoItRvU6+*&%OzX5n3(J}o49c30`c`X;LBiAe4TFPq)fb$XMbsNep zi1K;_@{;)q`K_$H zfmxEY^*9MzMXtP_L6N)Onq*9y z3)Ft*?rg@si@#`+2Uz)RLXKc;=81#6ThFfSgxq=-W1Wq36{MU$Up&y8i?6fwd2Ab{ zuOm7aSs?7gDkF0YkW0a9jC=}aC!%u^g0p^erTYYH#WDKrO0n!b;@|q837NWdvM!5-blvj7b z>W_G2f~A)7dJw=mM0ve|@*1MNK0)~yf!91POOSu~yuQoUcczA^{sD~gS|C_Qu8R-@ zZJ;5CfPB;+b)+ODZ^ zOnF^E`FV))N`N3_kv@zvA(q!z!6v`Srk3)07ry4(u=0dgoC{hzBzk@ zgzzM+qY*!ZuizMOhyEKIDu1B#0VGoh0~rfmhyG_UFCseh?I`aecIX8tfe@ya4*e?t zyAU0EE{CHSqC?*or3(VDI2XEby2IS^y3>ZrK*|q5lvgNeaW$TeTn?udNQ_|%+wh7ZFThFe?VH}6}^EB`f&mTp0 zo_0h80Mfnqwah|B9{&*X}Ul8@j7bu@2>W?hW6A=Vn9k_@; zH~GAZEw9d$?}I3>Qo$y-8X#AIS6&0bR3XZ1I*J^kEU&b!hFZ$&Yyf8=%IhYS)rj(1 zhjJeRua#WxKxQ23`KyDCpXVrl7ExZS1gl@;Tu*9%bO*1z-U9O`qP$vAK0_?8n*{5~ zb**UBQeII`Bw;y~$ZfI{N-3he`l0ki;3Z)r8`O6`uOXIKE#)K1AU4IG5LvRfMHoZxb!A z?Jd|?~ z<+T!J1;To}n2W5p9`CwJPx<=^d3H`NvW^kje?BXD>%JGPoZHOF!@WiJe3m}qzKr!x zh`*ke4fV$RQkLGj!|VwL(eY-{P~g@LWE6NEZz-4#h>o`}N+n{)TYwVS_o$`gtpSig zbiBu+9E0e1=b+3+;N`8SGVV!s9{y~3T}b%_i1JEXPe9)Gc&!Gr3Q=A!qR7$6@=9Az z)KXsC0lbYUuMkHQ2T@)fQQC{a=_>QE8hOCy)s&^T$UcMwIgr<#i3p)d;+3UT@uFnQ7~lrW`5#{wIN(*9nrQN!zrMz+m@g*suyed)lN0e6rWfNJp=LMv=0b7zH4keTu13O zNTxUi@`*RTd%)a{==h#Oc>=NHON&!#>G)m;uocnq?L_%IqT_Qoetb^`UU4pik!KSg zuN$r3+k+`Vlvg-Q=!y%6PfBFgcI0Cse%~!O;r;=?)4KCGc(eZ~&+q-S^eeKDu)d4p)5t<)q#un zXGo35>p;tEHRabM%Bxhc$@?vk?>t@`!2BLjUhku9M=YmLBVLX=l$&J+6} z%Bvcs3W3+NT(%)weO`yycsPvmk%;noPO$m|f|p1QkX7K-UsJ$LMwHill(~rIwOO$G zcYb>RpqBDl24D%Iylz0b4pCnBqTGYP%iAC3jP(39!t#2C@~05xl@P2WSKS|g^Z~ED z-UjnJqP+4rwd5d{SK9tSE#*}Xpev%hMxoRo%Ii3kV-d<1a=8qN5P^1GA8&chqkImc zycP*oAA{t~V1PX9@wx=eg^2R{1Ih!4<<%%yN3Iu(MlI#_GJqEm<@Gtrr-<^3aJUE| z!F}s`a=MV-MUjQn<4adzC%ZOAyB|f9ciej@>qrYG$^x|SX+MhU`{&_U4?^tE%Ri6m z&&$umaE2K5=jAQdco~M}i2l-(uyEpsdA|8Ns`r{Tl>Qn~-}C`tpOYP0c zW<8?5X-4@FvA!XW@r_(1G7PoUH{S#JC!)TIbEfHvsBaEL8GvAt?Ya?p*ymMX=j;f| zMHVAI#h|IA8vKYMbnhxefM0u@5S%FwyX9?Dk>$z?%<@H+tw%2Vwi7QC=fZ zh9mG2PE!$sV*Rzv`fC#96A|Sl)5l2iZ5zaAFxyWo=PH$OGhLgk(lq;ucl=9Rz-ISUM zM|u(Y+o(Q6@4)&#VmF)L*?pxf!5tg1o6SAeH~>RGq^ra&Vd(sFj5qG}cHH%pjz@Id za?7H=^8t*l{0%V)QR7#3Z$J-0R8Ri|DwwqP&9Wxc`pQ zjKE7cO-5vO+xd9d^7=l((<7q1B$8~5k0mugKJ<8%jNof(M0xc>>4`WRyLE!)pTZ>A z+*- z@EFoHPUZk)3~kwQ-(dH*eb|#aB0BDJ5DW(Ci5MU`;C0+pVEQ0B?vW@X5IgSPg4JWY z#J<$haZd&?3DI%SML8YOaW6q>MDVz*5%~=~4*0&1$~6H8tipT^Ff;8a&jB@2eKvm+ z>&u9BKuxq>{xy$*+@$&-)&Vuq>EeK2U^oNmI)lu)$Pu(<9k9?&{O>9K9ik49fMSgz zx)A}%1+NZx4$PB?I^ZjmU5Isnbi|iOTo;Q*Ep8 zEz}@>JRC<`)*XFqJglMg*GQ�J0Bwb;ko>)+6eU7g3%^GR6b7)E(~vcpFi7>_Yhh zQFp}Ho3eC&(s(#1PD_>ML&I2iMv^B-nL;^TOc>{le`iG3!+zB5EMouCATmM1VHJie z#Hi!n8JQ;Ie;dPAq#E5Fcg%)CS2n{kM8|!A6zh7?Jse0eed@Refa#CuxJRSZB6i%# zJ$x7@LoFTmi2#mAbleM379cwAOHeLC`1Cd(GiTSb(j z9gr^a_gH3iME?bpqc9vUM*SC1Zj9(JKF`IlSd9Af<(ne<_W5QEtC1c9=|Fxq-Sab) zl%KJNVsZZ$uRqscyoSyK)7w<$(c_4~$e+Xf7>$_|$9p3m5z)K0d^@t65%n!M1lB_)xr3|(@*DawL+U-Q4;gjlr&!-aI&ToJ51COy>ns-D9Hc^mT4;r-=FwV+ zO=xut*yIKyv?`Ofp3AVM(i+e5FmnR5<^g$-e$3-OtvN<__D`|CCk(m+5e63}TdtUd zO&Ht|uua7#41S-q^=!bF%3xeJoplQ^5FaO~W)c%U$8 zBFdn1z=o;}`Xy~W<@qAWp#Lxkgiem^YsAgrbATSOgTTVnUo0B5WR8@Q0Yy@BN~DdH z@H_2QTn8>8zCwMx1}wf$^8ZM%wkfF&C+KIv=W_z<=zEtfH)gg7Pa)#%7y!OiPxV zK9HF94W81RZ~<8K98;kxEAQEiR% zx^EZLzhr`WxF#x=$$7^`kJYiqqfY-4w~1~8lX`guJOO*@5<`>ybY>T*v>Hs@6#UPqtW+7t)F)|7Tk)iF6dKP1gOyNox?}ussDojN1MaJkEq7 zRN)YI7QC%QYz6Kb-lr>yY;DG=_e>mhBhUN-zGNZ45zTO-OzVs+{z5m7s-{TR<2Xh)9J()qU~6 zkYL11{$*P%iF6b!CY$n+=x>WKC6c5>f85$7>51s7Aay@oNk<_m3+iYL5_c&xT#Mld zH3obv25a;^XN*)AOiFwujXsj6Iv*ME@eGU$w0aUr)-jX0$f-huSd^&<93>G+TMC{z zFbY`;()>&hEy`>pg{mN|F-gFP!5RZpuf%w*Ru3RA#&DS$1CA1dHTp669cm2pE(UA#k;X{%dsC4?qmOiqpe!=bd+Jgs2NGNgcv?UE zawWzk5lH4B&Zne<0t1~!Fv!XZObyT1zR^b-Bh`yikwK%6bc~=ZGG!oxF(0B0)Jsx> zuuL|Qc%M!v!aop8j%ka*(hj&<3~6IAMykt73ydXb3@{XwMFtr5!8k~(2aw${^ipG> zcQII_k2FTASEnL_Mjz=IL0M#=_y3p2o*Lxh*95&}|c^q}ck^$(S8^An`0!xWKR)HLQ* zJI1er5{#U<=3Adc0+A_@%(Qp_rp%2UaiF}L|B*0SL2;&Ous?;PVitgywjqBQu4lNt z^(@f&3awj6@=L37bw9Ef_C!)P-VPXKR|;&WyjJp!{)T3ZR4-3O28}+_F@mzlz}7bq z<1nqBM3QxkEOXgb^~jOjU+ZP_6iGXZc;>(;-T6sm%-#sF0@SYv>yyfM32 zs|S#aFf3N1;O)nV!5V#}F;cw|N$EXl^pTDcltl)5PhB{&wlc+X1Ur!|i9j-iuN-k? z4GJdYEEp^)uehWdSN|grdQfPs)nk5PKxvCkRY@e|f;~z;flw@ov=S^P>wkpA5QOu* z)Ea43uI?vJ+8YT>ua+2D_oax2gD7PPC`m-p!o)KN+L17cgOpXIXi@Ci^{3RBxNi(h zl%Om!;5u0yLy$lhPNuU=@Yv$FX_wAmtsdxI+O$R==@>Csqu;yCtrxkz(T0LdPzoiP z;4C%z9XUn}*64R+j6_mFDl%yFk^C&kM+PD{j#2iSVDDs||0#19pennFcq2&F--!YX z*U>jDqf(JZ->}Gj5TXlTp6lu*@tffv@H*%l zC(z8%l-kov!2h)vk3a%5XD;cI3B7j*cgDIRVivN0g}ulPrly+Q#LX z17Tpm&j2~oLyIyS2@J|8!WxqVGQSl#m#WLPdJ;+2F$=gXLX?syi^b~HOCpj+)ibA2 zmFCa)(4s6sQm6{T8j}Q!7_8A>DOlXkwWQo#B)J|5-d!ZW)fRKj@R@>*fRse)Ye0Gp z!*Nyl_#+ zPsJu-07?>(v5rZ`bCgci?tB^n!|BWwKpQdL! z*MY!!6yxJc$sZBlTKYyGX^d2VE)^Lx`bftJ$|3_}_l{EM>5=LVAncKG68kaunokiz zs7fLb<0K!7QV`>lh)Lk=$3=Lp=ywG-Q)HZDC6NX-_SyV~1vkHxmgS$Hb^AUJE#)Jv zg!n(mc&&*Z{DidJo(3aUm;WDzp63~D=^^MtT)U*=B(amEd18hxbwM#35c z5g^-!crK;)D>1B8V<7&-V2ys8#z^(msmP$wNAg=29~tOfc8`a(dJ;+2F>ATphUfwp z7`nc+Y*GT%b>WMWUk$$ZDz%`P7ruyJDl76XrV$Ep!zr=D7Du1-<<0Ma6 z^;wdCv+9>5Us-hz$+uSho+PH;sV^dFXH}YS^|>D8y|$7h(qGv5SYc}dBy5C(vrI1s-MjCy^)ukb6L+sLyG$Oh*B$LPv;J1;c z$Uh$;O#*q0MErsJG>P~FwTVRfLH(LU{DJx%iTDFmT#{=$5tnqx+@EY-fF;R7_7+yc zPRfB=*xsP@O(Oyf1f5ig+1gxNeR^S`VM%%;K@O7dV~Zt`kPa4;ZS|?aLTi$YLV|F~ z*Vc1HqRK=LsyI5Z z5lDtZtgRs-@9w6uiO)vZF6WRG$id2~Urw^xs&cb?QX8v(iDZ*iw~@SKRcdAY_nK9c{bk%3g+M-Hms?%3zdGsfYy`JR zf4#N2I_a;$s?wi(2bccj{~!of`umGjsjMGv*MX1pCN9i&&Tw)IW1ZG`efkFJS={Lx zJg52w&$Yh6bFgplhV2^y4D|nO*;oBH;cOE5KT8I875(S!Ca5vFS4e#$|61NKM332` z=s%t3)Jr0gcKr6t!8H;tbc`6R(MK91)w`!6gGL|e7(rQNp!Z1_AJOUo<3bGbkI@B2?U>mZ=BY72NetHL zcVvuIKPwd(H2O%#2+AVsl2N`K<0`G5L~59wi?I>WITB@=MM)x(Hg}#mFbXEvNb{F@ zXi=_2Qo>9S)|ez<#9)m9s&`>ruhj#{wHR(wW57{jutp!rZv-*klZp%)eI(EMJ~GgI z>hWe1KFa*S?zwg<3j4Yw^HiNE$!)6ENpiQfO7f(tb&|ZG>O@JTkIbim0!rju7jU-y z!b)y|0q;8cg_Sk><1_l*RNGW!(C8x_BPfdu1gzYJsRh`}2DK^gt_ z`dkVEE)5!eq@!PHTV$a3u~eO`)sslFj!AGCh3F7P8I3R+Nkq~d<(UKH6-P<)M|)^d zWH>2Q1!0Xz0-1lZnHt@V)cf)1uFq%O!G~6^bU1!0J#do^=h2J)qac^ ztkFjrBh}X;DM6Mr`bftJ$|3{3+n;h@qz%-2lNuyViT(Dq0fm>Tu{EO15vzT~6IJb` z_G854B77V81!QEKP_!tEk-$p^qX=sZ@D_tLCVioI&v&$X5=quEPjYz{(G@7l3kXyt z5lLIeo;fgNiR4WnH+yJNUO`e^EC_2%5-?)0#uOLJqGIhL_8W%1ZN5_}cMla8t2$AV z)z&J>z1GUr{S=V?Yn93TdLG%!QDFt;){z0^a*S6Xfr)kW?_aFZM;iT87g>`5WYFj% z9U~}<41~Z~jFYu`5=qwiAAeM6fMlj8@v;IOkWUZT~LNV2@B;xZ4>PDEKKR;OMPku<8FIgP3`zt}^IVk2Y% zntqHCgf%7!WPa*)s|0^$)D~OtfkyIYBTTG^cAPkBA2lX>kW$l*ODUp55v5G5|Ls4l z4$MXZ0;4SnuJ&UFlMX=wGwc{KSff8Eomq{V_~PKyO;ezJ!aGn<9*i@v^zw(!Xr}Qpu zT4SJhF<4`ucL^#9iD2(!9W#Z?Nr*Z`lxbph>Ln3LbChQev?F&zX}J4 z-|{EB8=umhTbzval(8oJuuV@$Y1;jLf3j))<3oQWZgH~dz&e)|E^9O}Q;sRe&{K^P z%=Tl%V2%FN7$eoIkifYoX!MbGSFp%qY=iciOCnpEq>WaONhS20Lb|t%Xqvb)d;_F-=s<-8Ew&>Hp$y&GE7^9 zLZV!fqg1VzMBv&)tG~{W#U=|OI45N7QlE{Yt4)-7Vs+{z5lLHxo;lEttU_sik%ty# zF_N+h1!0YW2^51hrVKHJStd%-gw_AG3hjRKzh@OPZ~kW#8mmc?S|qq`BtOv>OEM{~ zSn`u?u_QCnipjS6$fDx4t|Zc-t}n0W;9rJ}m9C}1z&l`a{>Qd6A<#~fHYnAC?bIdP znc!E>c$Co}L=FNISQ(BHgEjgq!{{IJ+FOL*X3*#(9U~}FW;(0EDiNBI6m zlJ%+{CyBHh+!2%gj8Ez3NB*SEJ8w?tO?ykU>B*A#O}jf~vgrvaO}E-esmmuHVGEQ* zMr;4cY$=cre+?q+UlP?hMiP;*bLItWM3JsizN_*ogtXu|NkqcVFV0^himj0HwRJBeLY4$%7A;8?m#!H)Z2%eKsfgq_9buMx%8_8r84Fs6K}$ytZjc@8Ilq~2PDNteX-yw|Xj z;~}9`Bx%CxTw8y7V4_7y1j<+>8D_1LB#^xYOcrHyqPyJ1RxgtDGS^O$@l%9Vb}SO{ z2&XkkPPbM`q!Fx=EVoukq}jbup~(H%#`TZPY~z!XjgL<@KFK4xmwQmkU!vKDj!8B& zA=%I|$%ZC)93;&`e#|*Cnw1tKlz;S7Mkx-HWRa>9B{|1hB@qrk?J()`3R_7MyNykh zWQDa#BAoVee)e9GjZYFeCP`#`l8E}mHk5K}4Ekg?{otRNq;j?uU+wKO`>!ko?VDVC zFE{n@O>Ta(o5tN#qE|j1ZilNBShKz>5OuJd&v(<&X=#<4_r@zxD>;jFVxU3f;n`iVykIH2~R#fwiKJ!0(1 z*4nRr;dI9Xj6AA-OntvG^QO-^bH=GozcbHR*l*6PY5h){KE2;53+MKoH-Fx#eNR1Q z+N^&42UHzU)xX~?7nxdr)Tw99ntm$1B|G%n^pF{;&@un}h(&V;957QzHk>l&}S*Go-yl;lc7@8AnX5(MKfm2TZGP%b*l`b5(c(ezm2r4HaX+enV6#ilr_&i zC6ieRWPmSJBI&Kz7M!SYqPjJOZ|h{DVJ8&fyC^RFqsZPR5{m8{zGz-N8f_PiwCk5; zA}%oeb+N*-suc3@JVSX3;28ykvZ~rgi?d8TYP#_xV@$Hs4L{oH*K;#;dJ)g8aC1BT zZR<{7v8<{;Gix}Y5y+UepWmM^J;Qj`B^5K1x@X(IvVZ} zZHpzGH8fhPY5!;usp+N&lNJ7XJQJA~kBns^t(oxUDNJq+j?@CS6`N2v#h=f0q3?E4 zmy`(?S4E>);h)8$1(1jhiDpZ~SrwTmygNI^*@_JRx_!{uSDhZ1VGH=UodN>RZl9^~ zw=y-pHl^_^TQ~lxZG1>phiDc2d&Q&q@n~5*nw`~6hgd3VKUMb`5;aGq1=k1SjFR?A zZ?si!EclOj25-AoF9k; z3%HG4F26b+j~*^m?HUhdrL5zpa}5N;S>=B4_F-5D z{KRm*VGebNS#6iSbXpPJPc~pt#Cw&Z_E(ivm8MPxkQW~k%@xK~(H!b@!jzLWJlavy zYTeV|BY=clbQ7=_-CQ3%&vlx=xmve8#e@QP{r2g3>NkILwU{eI;<~8m8O`q+HRbqd zTs$7iPVvug^Q?cmMfZhKn2EQk4T!9&=rHMKh`TKxAmJ@^v0 zbGy98(`I6MO8a+Yr2bl~E;4TJEqm$W@{}%a&Dh1ZQ2H(G`8+1H#EW~GmJpHZ-PG(v zg|fnJs=T@LrfzP=soTC6ayO=syE-Ge9q!a+bsVm1RyGWs#_~+l_`27Voh5sJygj9x zOM}yB0bi#0*p4OR32dv^eA-0bnbN~083(dEr4u2aaU!?urHi{$x>%O6i*H&@3%a8|gqD$SM~?&vSci4x+i7R?{_!u3xnT>pMP)`fb56=FPoE0HOC!O(?st~B4Rs4>vLpMc z4e1-NaX*f2^<^pT-<{?di`kN#IPVMq{}8uS&fVE|gSWFXJkz*#w(45J;T0)e-<;O9 z#n^dEos;g-Ui2w& za6#NXVGVWD{)yxLGnjo?@y=r9?pckyZ&r!7um0hJj2r8h9{u1=>CzPLw+Dm7y76@z zBts-{+nOH>TmbEVEVB87?BJ8+$~Hd{)Yql*wE^|F6uvK=6FA3Nz&Zu!v@@e|?@`ZW zWel*ZygvNcwxj+yrJHAMH)+S7hmt*Ip3;;6^X4?+9mRFV@EH%1d*8CseD?fL`Rx6( zGi(Gm@c1rUhkfe5rnS#_UJ$@fZ3ORmjr-2BE?=F}{;D)*Sxj@%S^p;+!E3F$w)1pH zO4rNNy0(~I$*%ts^E7<8x8}ST1LeUrc1*@4_O?eexWv|^aQs!!{g&V-*8M-d#L}W+ zNr^sOwSF*sxs!L;mg9ez#{qf#lb0Uc2=zfr;~|l0%iZd|*zhOWlDsqJ-Nq$pZ&@s6 zcdHjUnNKZV7eO!GozniY*6&WfaU199tBpJ|c40iGKj)<2rn0naa#P88=DQ>HN!|wM zYbj6iZw8;_E#MXf=%%8t#l)rZmMENcAVE=`M&hcy&CBQByzC>~)2prBTebW4R`B@V z3jWqPH2}(g@m6|c(L&&z}&DU)zTS!(az z3j^>*N2U?LOe6sM`Mj4=hRO(mNV@hlDOYgx*a;5l{#aAOayK0Rd4FkYYhp zR8UY+K}10W8+HK^5mB+BqN1XLiUOiy!~gd>^V!Yr5}*5ip8xBYm-620oHJ+6%$zAZ zGdT$zFZ}NOYs74x@n;h{Uif8p=Fcg#+XcTPBu0E=u{(TLq>{e#+8)r_-S3Oj*Gua~ zcF)jmm&V1mbsIjJUf7l1SC_kumK)GLO4p+zA4@E)8F>iz`%WM>c=f99sOOyazW=uk z^Yee&Fi*`Y;Hvf2xbUmiW3$fLFt_>z{?ifs$zbK7E#hzZ-4XR4_3IC95x>lBu1tYP z@c-uP>%-^F+TYLzB4&LkYSw<4d-G@gzv>Kb>e#^40uRMof(;5k#Jv&GnyFgR*hdlon6Qg1r;lg`g8_OA|g7`F4V9)a+vNhh$_z-wM}-EA)9u5-3u6CY!XXUFAc zvP67LHC_7H1#~U<$U{4x<=NAZ%DQPCJ0S9TU1C93*7G7SJ^j0he@0w-ZVSKk^b73q z3xxIZ0xyF8&Wt|Y`;(uIsDF!Jf2f!HW!}iYy49AndZ*IM$wdaey$Jioxl5sMcSSJ_=x7uRu3Ge2K5_2*dN3jL~}Ij)SD z;~nSD@$2ByR@@x@?xm&SD)+OB3ujmH!X@W_{#h`rGXNh{gOUGwkT-7r5Uq@Spn41HsBeM@N71gAw(A z;MX73Z`Qdo?&$dcqu;CuwjjLUd>b+Q*TNUi?>A3GEZ+aF-z+U?j;A8#`24wZd?~oJ z|7E{oUzdMRmVxsiuW{l=rXSpA}6o^SeLJ*U9uRQCld5A_^>@=qe_f7h=+)N}kY8~ie1v#3^{ASrKfP-(~$h=G%xy zy%xS+{Q^(;1?+SYC|fADU(|-ase(>P6$&_OyMDtiHN**7SiTdOBiv9o;!N@TJ$uP2Jcwg8O1sp`S~L zbA^lhK_fr6&=6aI(|TTP_XnEziJF-^3vKF(LR)Bq-&>AbDrp4L!X1fm-d;>+Nv+jOf#bUd6 z^>4y9k11hE1>Y?GWoGm_))fvcDi(f{+i->3qe4C2FY|6uD--OFF}lTHO5gmOt2w3A zVry0zzb)q}w2Sx}@iFIFp+E_>DNw4P9&VND*M)1Ru3Cr&{k570Xf}27Zy3p{Gv z8>~EZ)bJ-i6jA>Hzy7Fo`0zQiDDbFp_rJ{IaKtS37dVSeu8iAEy7IA()55JWe{~i3 zt@8HZ?7~;qHxcvNbMETemOmqRN3mFJD>hM^m_%)&p4w`*8AoXyRE?>vl(xU8YZiGpuB5*k;%uCa$ZF zd^(I3(^HYyK=F93<%B>n-ZQg9r4DDxuU+4|VAS1~7wkY?-o9T^s$Pz3|a*HwYBgY=-XXJ zSi8&n&#PQVEAT4(xGr7JdC_!Psql_=UvAjp!vALdNl91WKXtV43ab2;h|1TTTlr_M za_zMo14GY{7PW8Ecyy^Lo!Fa4~`w5QvS=>9EcFL&wJ+X@${Z2z2Z|J1X8n%a`LinV|J z@)tf^!Cgf7hl?hR99Jy3~d)wXUT$w$vsr zwS`Mb6GQ{Hs`4+d?A6vxKw+&}kE(6@* zvaEleunQx-Aze(J%C7g$x75I-PQlvh1wSaahN{+Ef_BMcPwM=6l@HFVjz2Fu!$!=@ z)oN1(G7GG=wrcIusktu9^sZ}6Ol$Y4mi4^`ZZ`H>t^Z)qJuQxpdfWT!%IfYFDr&C5 z$Fb#O0<-=fh2>|uD++hRzemJ83dPP;9GDSbzHrfqqyKMJ{9SHgOhd zXruYBfZ10H`_@oh8&vO^7WZl8V{hiVyB*DACRj?Rm{Eo_keZ7l=pzkH&pX`M7&U2OgGP) zsL^_RNG}eb?|00&s;(7!zx@Ke+|kb+Ixnz}7WTqgp29ZnAXQ8@_N#Ec*$!>x1C!z} zu!aZpuX{LXD>6?B4Y_tmaI?@RRP+2h{r;Q7B?H=L3f1luu~F~TMUEYawSt0c$QHif zHN>J9;78(F69W$O!#Y)IxVCEpEq_Ql0!8Xu-}@zK6T) zQJ2WG>=HIz$$tK7*Fhq**4w$2U@t}4MzSw;{{C!V=j%TSYKfygwZ0T zJua`~y1Q=m`QNU~`#nAsSM0>;H2N7^3vNfa7wg^oT(N;vYf+*3F-5g@RJng!qQL90 zAErlKhxzv$Zq}#>nvkcx_hyG(hxr8#o#!^BT`H*~xtj!qI#qN>SGzoRbN6R{4>K?D zo%@3Y&HRCgncr~k%ul$P|Ht=^J`7eK`nKV>{lSR(ulMT@eP{H`oXlT7?osL@#w}me z%QS2C5_|aXOtjHc+{*UGvK`a>4XF<1Ul1jXcDsj5t?wUMZ7tiKleQO+9OaIjg*sa& zO7$nvr_y@5;9gSIbKRl+blub?`da9Ruog76szSdOq#HK>-MmLd%zQ|JGrz=Ueqr>? zpAO_NzRkRc&Qf+fcFUNQ|FPBodVP!uG+;K==6gdeN=BE9@6q ztaT~>`&BcNN9f5Bt?748YXar^X%Pec=c_?oqua5#qJJo@6*~Ia7dzJ}+-_Fjj(Ly1 zY@G82=~MqJ06XS8=U&EdJohr*?^k-qz~&X0X~*3{(Jj3D|I)(i3u@uXh!(zZZVO-h zzqRn$s_JRwIn)JT4GJFmg64m7{_jsO6*vxecD>cDq=N6`9m!&YgpMcv8okqh!;Ecm z=k&#(kZSE$|k``@wnpw=n!K{_7)Vyu_bz zc!8h&Bb}Wh3+uPZ+->6W{&!iOKPOmE2%bNCTCdQNyI)LO*FV(01lKOVQF?>MlHFOs z|Hu7C%R2=%Yhy&S7M|Oz-^vt<`Zb@`k-r9IR}R5n`5M9{MWTO66Fip{_~7E7;BO=O zE5SdM|K+!u&9gQ9SGfEFuloi3wWKq5MLQ2Sk11I<#{E*#wD{7s?%dg3MA=tW zyO`3i$yrabi~8Uh+P?|yHg=tudX{HbmG<XV)|VQNN>*CRbIy>FI&n?KKU4N4v` zIJtl7;GrqWJ;(G(?Q2bFIbeu2!fLk6o;|z)YNE?YNli=f(q;|G%o>m}Gh=FaMLh;4 zxrG~?)iWn&dX6_KHP4n{Mpka-q^yhy@%m+Z&yr^3dIK}2*>CEn%<8KFf^9b4ho)Za zb?=d!;`JUhG(I`8UA#X&Kzz%DmaP&K5-yByHf?t6F zpO`(fO|uD!Z7rNSJw30Ph8XBPIX!2B64Gn=w8wb9z>;;)ye|+~-i5ZO+JTnU<5Dl{+mnZ%p4bw-h~7 zQU?3WqjlkLY0FBP)pKS>R$kid>Dk_(9@=XD=FqC|J|ibL&r9kPzMZYXscA`RJ;$W2_&-2lgC1l!{b)%B;azQ)m0VKiKnorw#E}SMQ8GTO_S1t1Wr@40RRvDSSV% z`R6w?SpN)lt5z+?_-n#-=pLE5>Eotmu&?B#WlqbOK0{qEbB@0|owK^EbZC9KDzvI{ z^2ShuZ9=Uqw_m2FCWr6LYPY{ut!*jE$zv>Gc5brm(Y9z3@^aWgt+rHmdum*0?b_8Pn1; zvofnKdEUeQo28&q>V8%XJ;j z9l1hBW~;%DsXb<7PtBO69m{%3a7yiD`P((EfEAEtN4GKUyK`_DI*4PbwLNmr>XF>v z4lFJG)`cICQ!h@{X7Prm+NmSBU;`79QmjX|3Ld20`c~KTkGtB!wz6EJt#b}iwuN-$ zwj-{cW!!;0w2J&ii{52IRTQxAh9(X6=KO?n&qHbkd*$>j9Sz;-A;0qAY0DdSdr$~wFMPYLe9cY8=Dt{ld(@&Z^zJ!hhuEOwL(jBeSbPS(7VOqMH zbMB^cleqKNn8dcBO&dC~hp+5VH%gk3H$8YlcgN)MIjyY2W!rAqew=-@E#jYa$M}~C zksZX%HS(aOrg_8Dr(_Jx9+;6gdHMv`` z>w16W&Y3h}X0HsLu5&Wn+P8I)nwOK2J}uM{`&`j$>hvp;^QL;igKTI{19P+Uw^{P! zjPXgvNkSf)f@KG-EkurFJY8M(pD=kJep9viGHmellV*;92$^Vne$J-gm=t2Ed* z*ah6dBXpi))mr1+Qn>S6Quo0r{%Jev07p-aJR^kflmk+G`p51G(`V>_;CgFfTXk1| z^>k0q%}AOsL5F_-_-V5Y?VQ$zumf(QJK)->*zJ#6<>^`DGbXrImpy)}f2k052yz*r zmF%yb;MvsrY~HN=!=qbD|B@u#E;`5C0l*F$k-L7>PCq7jde+2D9Z7W=kTR@ikHpZY zmZ49rLZ4cPKD7ybYU}ChHz&_s@40P5=NRVB8E%KPeKE8Y!F|TdnU(9V7R6R;2d19{#>+TRHz4-rqO;oO3TXf@>f( zBWpr;?cP(ofvMelW!fd8f4KB7$E=UqKAJo^Ju53?Dwlo1Lw9HsSZ(?Hn7gc>G1*=8 zW~YTNYkFkn_}AH9W-b>Ry0-4yGS#hW|IBaS4?>qk<8>+TjsQ6`ve-TSbsWB1+67Fa z4%!2HxN}HowYa029of^hQx-f~%g{$R9XeOg9~i5U~pTMX$Bzx$7#xbyl5E(|@Hj0h zwqZcS^KB@(=r~?!!JlsW(7kk-1w|GHt}DE((CE_M&Rwr+?9A|KCa6rj{ty1F(1)I- zi!N08D@%L3_ILL`yT6wdEMvo1CY3I-uuxj@U8TLG65;jPkfXujD6RaXu573cp&>#o z&xY?yqW%gl!T-mGCoL#_b69%#JZ(LMPv6Tgw?NAfkzPA2{ePO?hX2(3-SpAr{!<*j z>^3ZFQvUjnXp6P?-{uisM}k{N1+TwuVReKrzYVkcZ*_;4o9CCaZT(-jEqwZY|1!M| z+xp+k--dGymJ6>}U9`aT_a;a`LGL~oz)b!o%GYI`g!a$R7NEpvF;(yAjoZvP)* zD;r+khLZiC;^tBL*2luj$0`nA2R7uamdS0K@N#=qE?)l!f7a_m_tNnTiY|=1E_PAO z;v!1|OKsWe1`EjDu1uAMvDd{cDzZ4RMEOa2f9}%KS~=n6^h*+|t43r^Nu?VWUR1h9 zd{li&rAzupm88;DMinnzGO0x5em~C5)3tw^9Y?~qLzeQA{bkFsyryAw+fcd5`TI=a zZvH_l>@XI&{B|r-`QSFS^1EK$y+2}IwpN*7{|H~l;pyS)_&t>mZ*Mm@eZl*n4b>am zPXE(1Nr@_$ZiA$Hg&OE%OuL@V270lj;szEgT)b$xA{7c%EL1sArBKyE)e6-pbbg`Q z+7{72;YmfjlmCS0>sLU-Lk)jwN5%Y~fDMQm_7l)}sFlKE8-}{7VynfLqj1=;)K)Cu z#YB~l;g9S2=dHrZ5B~{h81%^cV?B*T>*`OFh21de`BMbExTx}R-eAg)aOLCj3+q$B zD;ib4XjFc&sQhA4`NgC1ZI8_V325((Y=22_tg=UkiiGzVYftH@@}*t*C86@Az47{N z>(|atg}v(h86F!R+~Roe2J(lwxSsya{|V^NA4ayPOn#<51-!CR`DLT>%SGjvi^{JM zl^?#RSpAiv@*`UlP_Kzh3EvxR`f5@6)uQHKJu1I?RDR8<{F>e>m9X_`=k>x~&8YGh zM3uiFDnC9dKRznIc2vI2CI2Vj)rrcllb@+i0UcQ**GKq~*7EB`sPeY)@m?KO0(w?x(T)D!VdD$36t~ zH*+HEkIrusm2ZEFE&nH=wGcUdTQ~nbp(1VhBQY8tUTK9xgUkB`0*WK2Zy%b{J_PjF ziX!tnMCEsk%J1kk*23EI+I3T5uVYmC&Qaw%dmSjh-<9tiRlaLf`L14n%E!C%cC^m_ z33y3S<&(TiDR0+bg_R%v6Y!Fw$|r|sYx#Rb<@a#w_i*U6)g!8Wuc-2N6wUt$c)g?Y zd*^5BQ$T-THFACTiOTOAm2ZE@H~%N#^^3~ym!GLm0k3~le*dWa0a5t_qVfku{Br^4c~`fS%i{*PaNNND@`@#wJF zre7Eqk5ybZ;7{$jvw85dt*?us+8gorLX@8pm2cmU^M3;R3uckq)2=G=e**fmW|8^B z@-y`*pufHonQvDa`9A?~WK{mh{7iic=t>}R`ur;cD;Ut91BuMHzYCK86VTd^%paSd zsZRm@;gHDuaZ&jbqVgw1HKt(xU`$Tmshrk-#$B&m(%$sAtLVM4IwV+^80$16Wf`loX#J&M#TNSEyT@T{s3i=>&{thHw@8T3M zGphUy@^`!ZG;cAn-6trg0b!wx^fV@p3=0eaA1S22<&X0!YQe3&emuczPyC+CpXd!D?&jjj-Zhe_G-XF-n zP3-OtM?OpqyJ76^@`uI#4dl8LLbs=b_ln(@RBm#KC6@p$791CGr_{@X2xL zu}c19txyt=xk7RH+Bi4SZo*q?#M6OLF{Szs?ZQ*So|FXJ?;e~7tMMP51fz(jyRLkG zetsBiWd0)=SBjO8pBnWpNvK)*eIoQ|DwG%X0!~{ z@_F95kAMq)`OGGddd(p6H9aeE&QrtSN(#PebWVX_V_oO5$JqG~aYGHZSJK>L_3)Ii zgGv5lYAbNgy9rT={u^Rpi4m{6`CBpc-UyGsUF!ev>|8B$Z~uiF7+miBeS!t`j~r32 zlY}Mc-_{;uZz$~oWS~pty`TpN(EUepDy)1v1=M6G- zTXdNDDt{kc=~lkDE+XzAeXOZ;yRJ0tzK)gu5xbKftY<8-UE5o^ZszO$-+(lWSgeZ( zJ1-Z1)Bm${){Y?-YrdsPpKrd+{G@(A-7CId_e*49eLZh#>f*@md{}w{y7s8NePb&A zj_2jzTv=FO16}<}A8Y9<_n`T%=e>-3WMO?>t4*v$_KLsnU-uM$!~bi$7F#)sU48pJ zUD5jGrjmX=vE6sE)}^ERSepDONnO-`yOaE#P-++N8n_fg-dWHZop@7 z4<5xcSS;YruNpSNPB;kH;geXYh(BE-cEJHS1~YI9+V?D5zFBDBvn*bT_u><{6A$1Q zcmn^y(lLHLHL)pn#C~`&+V>}$?*d$kH{{a`(8jmemT>6nez;4)l;oA68g z1vPks+x``?9(KixF&9_kM%-qO^Sr0=IrA~kdzJimh~LL=@H_m;R6qQa_#Z4%!cQ+_ zs=f+X)ztiIVoTE7Vpr08VqY9d{-rnxr{D}z^ACUhJ@%#8O>E954hd+`2C-Fa6 zL>HD;e^IPys{UHonDhi}jXlZlizzq^$C|2lB3_19kgpf_+ zLH=x`Hzz4!|LJFQ=0=Jt9p7#PCApHaU zob<2p82&;2S&Y+#xXq^oRx}eluR30UP03Hd3$Ziy!hU#>sd_R^wLiyH-88qRx>sK^RWRo!PeLwyP8^#WK1J{ z1g4Wd38&y(^5@}Fyb13#Rqq;Hi<`;ciqGLoxCi&)$EMczSEkN=-{NV~1LghnIILl6 z`Qxz>=`FAo_8`9xUW7w&jH&r$U?$Eae-19d#kd?-;N7O`xfi#P{sg{2`c8Ze50ZZf zzs6(uv#EN2$G@?71%LTVV`Z$4b+I8PnA<$>LUWYob;cy}`;$MMcodE$eJXJ_&M;Na zHRLZbQ+2-xmz&x?caguIcq2YW`g6oD;Vx74>?i+2v#;lUf}fkJ_Za!V5dV&6NiVK1 z=vJ;YmN!*TO;hWkzS&>*39z}T^6km*LEHxil72DqB{Uoa*U8Y{U*@OE`)%yYYUlMjr&Yn zZt}k*{szA%{Ws!2(W~s&Qv|D;s;4H_C%q{qU=sN~aS*29XjAPQhZ8ZE{3~!CF2tMg z7F=nnp4Ip`=}+Q|r0>E#_!0S^;y3smo;FqQA9xl^RPmSpJgkB>upTzT1XK02#=fKv z#9^e5#<6%g`7`ipoR2q}s`pmB10Nv&A>4vb;0yQ)?lD!*KKz38uklCHPvaRZrW<(H z4@zMrtcG<>)!P`GV@LA4VjmoUL-Ar9YpR}1%r(`&=bCLiZyqi*)t+VK-$i^6K0x|o z#M|&0Q}yg1{|&Rb=e>pRnyU9x@{bW8$5W)AB`&NR*j7HyR6Qjyp7grdjPzF64*QTl z0EgnmINnsfnK%vSkbgBU#v5=2uEcvy)$;&8L;CahD(P?FTX>lKBX}H7;-9AKEmYlC zV_mwqoT>Fv2`|7p*c216ovC_~Ol|LeW>GzF!BM17GF9&s%qBk%my&)H-a-0mybm8I z|4Doici=u#^FM$e;8)~-izo0j{*8rd`0Xres-BWqi}ZTfob=Y%9{Z9%5QpJNoM5Wn z%Px&*f;ZyrxC-wxRnLR?BlQ$P5M>1i1ZtAIj$vt9d5?0_`Iq4@4(&o zF8LqgVLXDz@g)9XYI)-H0I2W=9WU@aQ_E4+RDM0;M%bM64#ZtBne@TLsW`$^{iE@6 z(r4h+q%XuJxQhHWxE?p+6Q=5Y7GK0S$bSnD;vxJRkKqYZ^_<3H7bw>9m%>V>@@rr` zCX(L-HLQaTu(_#vT4Ha~`(qmE zBk@w4PJS-V#d&zWsd|^=3S3M6I^2v~@i}}6cblqbFMdM$=XjL#AMq3hYWwRU4$EK# zJl|Bkb+I9~A^$?`j=gX&rs8N*{U_7B+4H91<>X&U{$k=Aa5?F#iSNU8q(4slBtA>} zZsNW87U`c5e~w2?wdXh%s^iDyO|>`Pyj{zW4Ndj)mgILK?vA}lPbD6XqfON_7H5z? z8|Rb01aHJOF%UKqynaYpHy4Z&N z3$Z))!Xc)n8-^os68Tdw4`<=Ecpctos-ESzj`W9dE9uYR^Y|wD@8HMy86GuN?~iy2 z{~4wKU!hlr03SSj`XK+r#avAUc)y`&G&uszaah^ zza#xu;y>^o(o59$r#}xXnAV?(>tZ9)+Yn!f{csSbnwowL@pznUs@<3499)1m;_Y~! zsd_e<^K^d!UnG66spZ~}pOAjkyxQ}Az~4!aY2cSHhNVr_Uyb;DtV4PW;#Sy!^xo!N z&+CsPNS|P;J(F=d>2u9F`ksh4k-o}Q`89Yy`RnmH(qFTA_!arz;t4#BXHCt& zNJHPESkct{t72`ek1enjb}&^>7aUA_Dvl<798Sb5$iEU7;u5^oRJ|*4H9k!KCVUE? z#hv&XzHMrIernG0yf5%a(*H2Eyk{}c$S)U%HB9BlV7y~zT&wdqUT$hVUrGLA;u~YkWBz-&X#dpmqT0T5N`Y(9ayhQ&u^F7a0 z`_IP~*xnrKd7ZE?=_7HxIZ)qEFpu=>aGBX%_dW4m(zoDtv!kAq;$G4}!6W8{o_7>~ zAzgpD$F)~~vd1gjPWK})p7ccQV7Ai!hW$w&jTxraMJCQ9eK9UKr)mGfm8Q1K{p4>Z z-il9?zLWSh+(-IB;zRfa>Bosr;;*C^ZsE@_7E74gPL+wPW4x($*2N1+?~J`jAAmzJ zo%{^U!W^7ys^0my2yY|*PP`8v#7+1(K4Yq$=kZlj%kd8R@8iehe}+Gk{u|nhvsObHpHgb*3@*Jup15}{~{cTm*OOxf;pz@nTa=$elxBl{T{p@w~_xezKpwY zzo~lP!-M!W`N!}S{)+!#Akkm`;-=~;jde(GfC;3x#SW+ezqhIiuKc)zK7*5h-ezl3{8-;W3IEAqd^6L=cWnyR-*OW&ec(Nw>vinXym zw!l`{!BjoTn1&-T-BiDwW~$!HaVGh5@Mh9)!_}nUkL&Si@}I+9xCalIYR^GDgvZD~ zj=$m`7|=1#+82kVP1REl8<5@vTa(@ayWn8*Q*kto#mh|9n~iyRE&12sGQ1V<#(QzS zsd_fzOQi3_eWV}25Aa*^zsJ*f1`D_L>n(~Uv8t){QxofBV{C=(u#2ho4aPAz9T(t@ zcppB2d+-qcfM?BZx{usO4%hv4EN@!-OyxHsZiX#Qm2ZpvNgs?ONWT=vVJ`Vs;5=N2 z%S_d~0$1WX@*l>n_!Pc`J8`e6diLX2q<@PiNdFc8z!GgWotFDNtb#SLzNvbfVghz1 zKMDKcARLaPaGa@nCgPQ(UxQ0XUxv5h1LQx1Tkr{d(Nw*=a1Xvu{zv#FeuF>Z&-jO_ zdd_0`c8axLDr3B<{QB4!JDMuj75m@-9A*yJa|IlW(@afwInKeWaWUS2x0=H}?{0hy zUoq8R_nU+D{0%=aRsUh~e;_`AznCijJC<(mmoJCaP370Zdf1ly4w#I+@gh^x4aZS9 znf$3Z183uWT!c57s^=D5Px?mOM*4Pq0r!)C06)Rc@tCQ4f5M;9(>1THuOe6q%VIS= zAM2T_r#W`VG*jCn-Rz<7*_dgn{#^2}Azpw>NMAv`64#ijXDvQO`m?x`^w;rC{EYlB z@q7FUe>YX{KN#rX$7M{lvjWz{TG$wyV;fWTT!@26Pr*^7r(*`rB!3Prz{Plrse13k zyKw{gkK&WK9e3bveA84t@8CD2e}_Ml{yYASrS%=j)W|*oc6R#$HKHfn3EqFVwCx0Vu!>92TQ}w=vZ{R`l58>B%3{T;&__wKg3U%_W zWNN)s!#bol!e-co{O;Hv2jj)2>K%jQF`In-%|DO1@>^m@?23I&O*a@*aV+^0a2j5Y zbMR`s&Qv{1@gCCe$45wi9G}G9irG>#G>8&_LRhmSQTqyeQai`oe+hd-Ly4rjs^00Ci}T1|h&SOaco*J->rB=2Fuq9o z4t#_3ckq4uhWzjFXZ#Hd=^muj8;2#ZimCNg1M6WUY>92Lv#ENLa2V+$aXjgnI1R5R ze?H!TH{&W(_1=pQ;1=?qz!&fp+>871eN**(gg=sg3jZX%P_kbx1}m9b57n>^Ho!zv z^|r%~*oXW9I213&aX1mDnX2bU|5}#lz$u!Q*%m z|G={tqjR^_QyME{JT@`4-?caE>V6`2GqwKunaUqVJQBx{K81KX=8-;+cp)w|>w4Zz zct7du@iEe$#O=73{QdYLeu7_{bv^HU{0aXu)qbz1Z!s)|m9QGtGF4AK>_B=K>`nSW zya>mUKM|*6E?#A--UYZASCGFF*Wx4~P+PaEt&eiuw7eK?LKeIj0lSCW4XF2Nh|4pZ}AjrZXu@*l@%@kM+M-@pT=>iGb_ zC;cZpL;6{?u|=$Wc~i?-8RM}oHaAtSHMYl|X zs@}0U0WT+i240Qx@dmsZSDNat>&$qaFL4w3Pm{ls_%+-|`a$AD_yy_5iBICMrt1F# z&+DsL>!Cc>FqK~$>tj3eJ7N#)gDIw_8-b%Sll*Bo6X)OpT#U<1)pIL8MEWE61nJM> zi})7#@8TgmjNh56_XM8CLj9Dk<&VMASPrY>1z6uyJ&my|>B%^N^b{P1lgOWfc{mH_ zo2qvS-iWKnUxVv$BW}Z|@kLYh?7(+P{}2z8{tbSIf0F+X7VYn^my%e?RJ}DY9-EP$ zh#jyC_Qw90W~!g3n~&)J6=s^+4!NfCuOVK5OGsZqyb{-t{xI<-+-g3e@rUpY(%-^^ zq<@BA;?Ly&hTZ_bT}808`H0RdSOx2m-w0b`TkML-*w0iwLrpF3IJ27PO~lJgt&cqN z=MgW&rKI0ZybA9jeIxN^+-9o&r*R+YZ{tU#e~w?_Y4Xotp@Dw8V(>gu^;X2HSfBjH z*b3WWH|&A^P1Q5O)cUyGT<>`^aJH%Sv4H%WiEqP|q(4Z!0XLDpo%jXZVXFS!_zCHs z<5ALo#8Vg;Kw5;z(2VWSCkXIc8-&r^W@O-)w5V z+=eSje~@?sZX$g<@e8=aeBATiCH@c(o0{J@_#OU9{y$iBus{EjSjp6MH838Vk)Mbi zunYFa{+MQJxzo+tv>q^%{9N*{Azpw>NMAv`64#LaF!3hbO8Se$JMcBq-zEMK50QS9 z_y;^m`rpKbhWP6x*3@#8Bd&ziO)Xbl9Av88DDxKGx5V-0V|qSK{%qo_a6akFh;PL^ zNq>O&A$*kdXNaH2S4e-8_#OO!^e>6O!S6}`jrdRWF7n%74BOxsQ_DBmEU)(ta5m}J z<85YH-IvD)Nq-V|m=(3(;$Bnh=RNWd6Cc52rpo_Ge$f=gYxJHnmN7MbHB;@YPuv(= zklvBFEA}9L2(kVQwX5f1Q}s{7Yw>n`$kcqEFz?p5clf-icI+nq0PzR-3F+Swe~%|j z)l($Zw+c4JF6K79uWPQ-{b5WsHNQ*DZF)XHJPmV9m0yH+;bwf<+~#?2ns@5?2flBr z-p|c#p7%ZRPk7o?`J!pQH825_Oih=D>6nG{@fN%XJ^k4DHbt-`mcgc&fbFm&>U8g> zAB@9rBwmJDI0I+nZKy?a^*oAO@M(Mwci|rV2tUOi@e~FM`Sr$O6|8~HFcG_BFC31e z(8h1H^_7j+;ZnR6ZM=3Xw+7eZ6Zj0ifp6hKJcP&bBo;30*BgtKu{t)z1Wdx7I1ESP z6r7Ip(Eb*Kwf}Zpg&T1*+Bof2ZYREn2k{sl$Fo>C;7?c99HZ+XtckU-GbUjl9Dt*7 zEKb5HcqLwgi|~5fh?~)kC#d#pC*Fa(@lAXOkKj@K9skDC+Ocf;%3&RBfbFpp4#bOa z98Sb5@Jd{cD{u|2#SQoJC0>Y2a22k>&A1hJ;%j&i58-h< zi8i*mEl(^~#|y9_Hbpo7qsq45QgLoK^pc}7I`F{}y&hyL1VI6FMEwB}KH=FCYj)O1-FT*T!<1?zf8=p}wCH*E` zfh*CC!>Dr45Wj>w@jX0<$MGcofoCzMjNjg3SOep+6}H1}*aL^+#dsNJ;WfAbSKvx~ z7&qaIxC7tC5Ai7efPb4s_1;)n-*Q+98(f9k>S9 z;zrzz`|$vNgrDL!_#K|aU+}yNetXNK8@EvHcjFdHH(sH1;}zO+Q7#3?<0PDgbMYp; z1>HD=s>h8(D7TURG`@&C@O}IUf4~#y#vN2We-pd$1{Igny)xSlb+7@t@dcIMiTENM zikIRz%*1Ip4;SK{csD+XZahKFXFKr=xE~MTx8?)7zl5joSB$OX=NHF1*Z`YjOYDeU zaR{d2C>(=x(2WebmIale+=<>%)?o@6y5lLDt{00{kRREMmNr%%Iza|7R;(K@yKgX}|G@ij?dbVfnFNNo0ZFJ-CDc_C5 zC*3%F(v8C>FQHsI=HN_pds(jgzN(FC=#3~!IKaGG*R41lN1+=RPx-Tnug7J$&YY|Fq;Lzm@$i(si+B&ZaqyJ>F7eOi9KC0b zXVLzKlBJi!N>~$XVMpwWLof|9FcatC)p#@Bh7aNf+>S5cemsC*;kS4O|H4x7{&JMX z+E^buo3r%ZGxos&I2y;|B%FfR;ZnQ{@4?4#8}7nA_z`}JKjJA2)biUGhgGl!Hp4{h zj=gX=j>4&!jn|lKb)N)pz?<Ph(6S zfBwa=8lI0Wuod>eJ~-aY(>NoTg*oWPc~kx(;+yamT#M`QQQU&>nK`=OgP-G9_%r^7 zXVKme>ya`v}O1u{zz>T;WpTzC>GVa1R z@GW%XwyB+N+&1|;>3?I9dj4`0#q+Q{R>SkL9yY=RY>geUD_)A@FcYU?9?rsRZ~io=Y=T{|JEr1rbmP9Mo~guF;k9@x-hmI{BltYNjPK(|_$7XW$MGb(@!d3kH@=&! z-q2s33$P(J#m<<7DL4!#;S`*QZu~aYe-rU7=*DkTx*NYuK1TXB+>LwjUHlM_;t%*Y z7HZ@#M>(v74X_Dz!ftpG4#kOh8D5Fk;Bs{1uc`g(h#$sh@kM+K-^C+%6y5l0s>hA5 zCf&GdvRq?-dFo&T?1bI0FAl^s9D!4CI?l&Mcr)IH58?*gjxXSTJb+)}w|EBs!ctBA z4@kw;!qNzPQ zh-39DffbmOF{{%*uQa424kmthuOg9~sauEurvFuL*5G@mDk zU&A->GyD?2$Dh#CvmonFMX(}P#fIi!eec57*dB-BNK8jJewwD6N}P>X;FUNZ7vW8K z3$Db~_!K^iZ{S;a7?0pD_&XMF;V(~Vya4N9Yiy4L@gf|Fm!caVZLr>ZBzEJXDV|5{ z#zRx=#zT{CJT&RXLz7Ro@Y}N;_u_v1)a;@A3wR8VV_brtUjoZvC9H|H(2akl`rP6wTk$D;4d1{+co!FU z69?cB9FLQ54qlCm@djLt_u=FCB<{w&_z8ZFZhSJWcQ-znjA`jFPcf{9=c5~k%(fG8 zFYJdG;ZVE`v+xSM66fP0T!m|J3qFA_;4A3H9aDQgApRD=$G^~Po&|H}M@jh==ei{1$)2Qy6IN*B^&f zum(26MC^{ea5#>_shEw|;&pfz-h&U}Be)fx!q@RlJd8*1IG#j%x53s|ELO(q*c1~m z347u&9EnqKI=XSiRKFWnOx{lVD%^;haVNfpZ{vIT34V^J(2XCa`ir&om!}j~!fMzA zTVOZrfvKjhq1`xPat!f!yaL@gValIRya?~ayYW$Uu@RFh4UWI zUHAsRgk%VmUAJo8>dV0Dq=T2m*UOD zThWcnrS#W`58+`vhR5+Vp1~3w{N*_hYh!(EfvvCy_Q8ws63oIJbmMHPeK!!Vz?FC} zK7dc*v*^av()4azE%`C&pW#pF#@AAQk&gcI6vfJBUEK%3I@kcaVlwu_K{ymI#<4g7 zXW(qS9+%<0_y9hG&*Q83I=+qX;kWobp2fnQ{N*Zv=V3h7#Wr{$_QOHw#>3M3nMCZy z#Zv6X#gbQ&ehuD=ci_Xg37^7e@eOdRkmrFbs=iy?!0q?>4(Tz)`>D{RFK+cS=4*{4DOk-MAkQ;8FYme?~X%le2!77Hi&%T*pL zV?%6;Zk(uiJs%`?<3uSQMm!0p;9PX$L#f>D#H;XrT#uXZaomM_@DuzTkKzybHx}yd zFHbqFgblC>cEcVx5HG?JI2xy8E-u3B@ix2@H{he_#&yzqc!l_F^AY`?Djvea_!oM~ zez`a-fz|N>tdEVc19ril*cYeZbexHE@OoT^x1$@kN$q}^coXi%z4#8kk6+_4Jb|aN zNDqHGi(*x*iOsPkCSz|LfunI6UXJr|5#DZA({&ZD#dWv|A4fO-lFGk8{1JYNNAM`R zahFv7XW~EbESB!+&%Yd2#hTa}+hbQu#sN44$KnK>jaT79T!J^_ZMX>^$KALW-^CB{ zGyD>N!QZiDFMs*UU{$P%&9NmWV{aU0uGjr=9EWbaC8f_NUW7N{Ew~of;iI?(U&dYd z2EK(S@fZ9Hz21Ji%3uYoju&7HY=r}G2oA?lI0dKUOq_$)<1)M#AHXNjjhD1u@8=P} ziJ#$@_%ph3kyO5DAAh+@Vgs|X=QY8W*cN+XKfDNsVg_bnHs;|9bmJUpKKBwofREx9 zd<9=cH?EPUJ52m7evhZ|3>NF_FHb2vAKkb{s;3pP8`ns&8^=fvApH_d#~hrAi}41$ z%e+nR#o~J0h+FX~bmJDO{0`#J@Jl>~$I*>fr1EEo|G_{%f4;@hjbEg46^W~2XH3FA zH~>>|I9`h5Fb8MiRd_8vfDhqj+=|=r1$-0V!Gm}R&){De=YGbE4;SMNcn{u>Zu}ul=f)qB&s+K}p7%2D!F~81x^ak9 z?lAEYbmI;w-HkgWOAPSqI}a;iHLQhh93qu(N}Pc0up^GgNtlH>I2*6RoA4G~iL3De zdpK^b2d~6ya1maQ zYjGVuid)c)FQj(9K)eh0pc_|6`Ck!#hi-f!rT;?wJ9>ls5RqQ~Uyt;t%*U{)SZt`|YWT zb+I9~z*g7+-S|RUj-JGQaU4#>X?Qu#!nx?i7g9ZoiI?H6xYoQ|?@iz)d>psq3-~I& zj>plBBcyuH5dVdNA%6XFSQ_29LMmUCxF))Bg_PcqxIK2lWbBP@{2`T3A-)(d!I?M* zuf^-|MqG|={2|qMH}U3#&d@rM+@O6!B z)OXy&roIy$HFXVh!qhqMjHzRvS4gVQ7d2D0{N_+Czd2mXZ;sOPo0n+$%`sYjbDWmn z%+T_ill6YNIYr}An$xuWX112!%whbSJT1S)GqwEYEG@q|N6T-{)$*HHYx&K2T7GlB zmfyTd%WvMSP%WtZG9X8dkkDA&)PMA8boH6gUm7xFDYWd9vwEX6J zEx)Oi9&bLPa#pmmt`D#%mc%Ni`b`atH&sZR+}Y4nKhh?4CYb6^dYtHNZ>nE)!fvMe zmo}ZVkEwp9)3kGlsrIDd2vgsON8?yCUgP`WWV5#3GeK<<*B`YhoZ1AgUuxAm=b38s zLR@01pWcYeO)bm{TxqJ`uEzUJE#!l^!Bjtf6t|e_&rjepW;?m%+~hDY*YJV9?mlJbRCZKOzocwafvxg+aH&k+Fw`TN^`EZKi+3*|9ucQ znDey#af>-$+aI4XwO>DvFPqxGci|pW`}sb6+tmL49v(Dr*Y?N5=AGL9c+}K!;0HWm z>UeM(&zL$c{DtngpyNZ4!b+F!_^?*n-(u;G6FOd0uvog|g^n9FESB!Lp-x}dV%gBt zam0?RSkUN$qc!n%zC`3RC;n-BqRbt8!|a?N3Wg?MG`(?LWt> z%T&G3T|*A_ybh-JlPTv*?H}&D`Q{YuMj{q}G(ss7qX>%jWyP*eT$a&x}+yF_`D`j4r8 zxU!|ZMb}SSN7nDkw2`;#eebqX{VZMU%KF!5rux;~_EP=H{rxHRpY>XY)^FVN+z0e~ zTAdWDpS){s@VvXa$Vb$lJoyaQAKK>HlrGjLbp50?v8s3dMXTK9_c2RzKG5_dEY>!k zK)zO)>qlB8uKX-h+j1rGYO^xe8Jhl4i?z-6k^i3vD^REuibvF*zMQq-)_HE?Dkvr^Y(=`AH|(at^73N z5vKb6RN`#2zuHf{#MFMUf_SB={ozsKEvEL1UBr9Lp=v+zL36l{U&JR&?Jq?FQtc^f zYQL#KT*cJ>)08;D9H;e9+{e`Z2$pCn&-}* zmX|(G=H>WK4t~nZn3d->pOBuH?lm8mo9i{Vgyut&Qqsos%$krkD=jBID|cc>PE0AMV!va&}4)are#6+jaEq%=Y%pww9KGe}ru%CK4eQCMK~2f?24f zl!#e@!AeMFLH^Mn5h4pl_Un7z+;iv5nK!P7ef!?r`+c8t&b{~jx&!k>V~H!eKDUbTxG+btX4ZX_F^MnjNoiGQ1V( zc1ozoO5q8+UorMlMWgTM{9>hTH%=_9*BK$X*J4z*BJI$+pmVx&O0 zN^@&PL;&38*AxhgqXSBgbY#5^DyRsTX7pT>N285)n3&XI<4AX6q;c5IRveWHaZV`h z)!Gjw%TTiy#Yoqn#@9U98{fCjGLmJi&vTv{IabX+#%2R(Ph z_~k(Yx$s#g zTqnr;F4vWI>i%t}Qg; znj+dQqLx}LqF8m^(B-!-(KgQs0zZ?&Au@!UnrpMWA;WEd?0O@oXCrC2MGoyg{3ji5F+y{>dm zBMA0Ia^BvfbgdP1$CR!ex>}U6G4BWpreLWx6|Ij|h3$#k_86uo=+-{`d=6{bF5B=S zjWRaUk)6dNc}ehYK^gI;VqxB&*p@tcrrUusHs(#BK=RVy#Zg8)JUUw*J;O>KJ-cm1 zJsams&$d!G4FiWBVc1yLqI9Fsjj;%8)-^&Wm+Hw|mfH?4RzR6&6lV_uKq z9TfRahn9JpG!M@hcoek8ybX#sF8Tx0KbE&!@!kjTV@oUM`>x_$5Ij1bIKIP**Ny|8 zVaA9OO);~baec%vERkmka=9UxR^&AV$Or+D5T#L75w^2cd~+x<}f7hR0Z89 zN_QH%=Qs(hQ61U=Y{)#OA`j|+>W|r2IFD}?FOE4-8pmwR`%3Zd7wtmlc;@}4c#CLG zm0?)(_DwimWxh4g(R>yg@yMn?C-ayKzjIJdd0?u``h7_8)?)D0qMnWY&Q`pn$b+sy zoX0bYw;w!AOIl;zGR0dhc$jLlyo}@KJF^}HuAmj7EV}|7UN|%N13<-?!K3V1WApG)m zbqTcWcU1A7x)Hx8&M>T*_nP9J5Ijt&THc3>N53^5kKlcvc;kYHDOt-qp?Gt_+ZMq) zu6P#&uTJpJE8bD?I7hkhYG<7(h>AKGG{iJyG+qNeehBfofDc(^L9~~#myP|kcpixp0 zyvvF=4qhBOI^I@cVcxB{e#>#N3%o4q**HFWH;Nnw6N0xIV&*-ncsJaM?^zj!HS-=( zyy=e@<69$m&5B3A8M`%t*PwWd1g}T%)+yct_+D>O1g}r=lHk$#iQ13aoAceNc&jS# zwkzIh!AlF?mx{Lyym8dCkzcZ7ikAkD$6p`nIlf;NFO8e}S^^m3{`gt(0ukR@Xqi`q zMv&uWFL?VIW_0xNAH~}UUL57re(SI>Z86Co>aWO;9YDl#7Ek%lC1`QzsGVu{i1T<=@iv?)e18i`Xw2KBcw4@! zigf})ygU}>y{&i$aI&wb8xmv8drR@g&*D68;(GyF=DlZl3(Wo#Q>tRqX+Rqz9xWd! zUG-g6;arv0eX8PH09`fCiEQMTjNVx!`{VcTaeXuSzJz*?kKSp7ZXXPH!oQk$Rcs-D zz?$==wdkgp2VE!bIbK2e5iG=`w8*CzMzN#wt7318_?U;wa*1vx9_+^v3mfbH2PJug AE&u=k literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_hal_uart_ex.d b/build/stm32f7xx_hal_uart_ex.d new file mode 100644 index 0000000..d52f0d7 --- /dev/null +++ b/build/stm32f7xx_hal_uart_ex.d @@ -0,0 +1,68 @@ +build/stm32f7xx_hal_uart_ex.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/build/stm32f7xx_hal_uart_ex.lst b/build/stm32f7xx_hal_uart_ex.lst new file mode 100644 index 0000000..ebeb78d --- /dev/null +++ b/build/stm32f7xx_hal_uart_ex.lst @@ -0,0 +1,3980 @@ +ARM GAS /tmp/cc5ct5Ve.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_hal_uart_ex.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c" + 19 .section .text.UARTEx_Wakeup_AddressConfig,"ax",%progbits + 20 .align 1 + 21 .syntax unified + 22 .thumb + 23 .thumb_func + 25 UARTEx_Wakeup_AddressConfig: + 26 .LVL0: + 27 .LFB152: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @file stm32f7xx_hal_uart_ex.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @brief Extended UART HAL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * This file provides firmware functions to manage the following extended + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * + Peripheral Control functions + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** ****************************************************************************** + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @attention + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * Copyright (c) 2017 STMicroelectronics. + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * All rights reserved. + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * This software is licensed under terms that can be found in the LICENSE file + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * in the root directory of this software component. + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** ****************************************************************************** + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** @verbatim + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** ============================================================================== + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** ##### UART peripheral extended features ##### + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** ============================================================================== + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (#) Declare a UART_HandleTypeDef handle structure. + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (#) For the UART RS485 Driver Enable mode, initialize the UART registers + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** by calling the HAL_RS485Ex_Init() API. + ARM GAS /tmp/cc5ct5Ve.s page 2 + + + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** @endverbatim + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** ****************************************************************************** + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Includes ------------------------------------------------------------------*/ + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** #include "stm32f7xx_hal.h" + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** @addtogroup STM32F7xx_HAL_Driver + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @{ + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** @defgroup UARTEx UARTEx + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @brief UART Extended HAL module driver + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @{ + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** #ifdef HAL_UART_MODULE_ENABLED + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Private define ------------------------------------------------------------*/ + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Private macros ------------------------------------------------------------*/ + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Private variables ---------------------------------------------------------*/ + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** @defgroup UARTEx_Private_Functions UARTEx Private Functions + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @{ + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** #if defined(USART_CR1_UESM) + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelecti + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** #endif /* USART_CR1_UESM */ + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @} + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Exported functions --------------------------------------------------------*/ + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @{ + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @brief Extended Initialization and Configuration Functions + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** @verbatim + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** =============================================================================== + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** ##### Initialization and Configuration functions ##### + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** =============================================================================== + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** [..] + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** in asynchronous mode. + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (+) For the asynchronous mode the parameters below can be configured: + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (++) Baud Rate + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (++) Word Length + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (++) Stop Bit + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (++) Parity: If the parity is enabled, then the MSB bit of the data written + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** in the data register is transmitted but is changed by the parity bit. + ARM GAS /tmp/cc5ct5Ve.s page 3 + + + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (++) Hardware flow control + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (++) Receiver/transmitter modes + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (++) Over Sampling Method + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (++) One-Bit Sampling Method + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (+) For the asynchronous mode, the following advanced features can be configured as well: + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (++) TX and/or RX pin level inversion + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (++) data logical level inversion + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (++) RX and TX pins swap + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (++) RX overrun detection disabling + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (++) DMA disabling on RX error + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (++) MSB first on communication line + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (++) auto Baud rate detection + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** [..] + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** procedures (details for the procedures are available in reference manual). + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** @endverbatim + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** Depending on the frame length defined by the M1 and M0 bits (7-bit, + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** 8-bit or 9-bit), the possible UART formats are listed in the + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** following table. + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** Table 1. UART frame format. + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** +-----------------------------------------------------------------------+ + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** | M1 bit | M0 bit | PCE bit | UART frame | + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** | 0 | 0 | 0 | | SB | 8 bit data | STB | | + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** | 0 | 1 | 0 | | SB | 9 bit data | STB | | + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** | 1 | 0 | 0 | | SB | 7 bit data | STB | | + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** |---------|---------|-----------|---------------------------------------| + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** +-----------------------------------------------------------------------+ + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @{ + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @brief Initialize the RS485 Driver enable feature according to the specified + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * parameters in the UART_InitTypeDef and creates the associated handle. + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param huart UART handle. + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param Polarity Select the driver enable polarity. + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * This parameter can be one of the following values: + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @arg @ref UART_DE_POLARITY_LOW DE signal is active low + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param AssertionTime Driver Enable assertion time: + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * 5-bit value defining the time between the activation of the DE (Driver Enable) + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * signal and the beginning of the start bit. It is expressed in sample time + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * units (1/8 or 1/16 bit time, depending on the oversampling rate) + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param DeassertionTime Driver Enable deassertion time: + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * 5-bit value defining the time between the end of the last stop bit, in a + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * transmitted message, and the de-activation of the DE (Driver Enable) signal. + ARM GAS /tmp/cc5ct5Ve.s page 4 + + + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * oversampling rate). + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @retval HAL status + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t Assertion + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uint32_t DeassertionTime) + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uint32_t temp; + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Check the UART handle allocation */ + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (huart == NULL) + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return HAL_ERROR; + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Check the Driver Enable UART instance */ + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Check the Driver Enable polarity */ + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** assert_param(IS_UART_DE_POLARITY(Polarity)); + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Check the Driver Enable assertion time */ + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Check the Driver Enable deassertion time */ + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (huart->gState == HAL_UART_STATE_RESET) + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Allocate lock resource and initialize it */ + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->Lock = HAL_UNLOCKED; + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** UART_InitCallbacksToDefault(huart); + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (huart->MspInitCallback == NULL) + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->MspInitCallback = HAL_UART_MspInit; + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Init the low level hardware */ + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->MspInitCallback(huart); + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** #else + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_UART_MspInit(huart); + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Disable the Peripheral */ + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Perform advanced settings configuration */ + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* For some items, configuration requires to be done prior TE and RE bits are set */ + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** UART_AdvFeatureConfig(huart); + ARM GAS /tmp/cc5ct5Ve.s page 5 + + + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Set the UART Communication parameters */ + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (UART_SetConfig(huart) == HAL_ERROR) + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return HAL_ERROR; + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** SET_BIT(huart->Instance->CR3, USART_CR3_DEM); + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Set the Driver Enable polarity */ + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Set the Driver Enable assertion and deassertion times */ + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Enable the Peripheral */ + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** __HAL_UART_ENABLE(huart); + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return (UART_CheckIdleState(huart)); + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @} + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @brief Extended Peripheral Control functions + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** @verbatim + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** =============================================================================== + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** ##### Peripheral Control functions ##### + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** =============================================================================== + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** [..] This section provides the following functions: + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** detection length to more than 4 bits for multiprocessor address mark wake up. + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** #if defined(USART_CR1_UESM) + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** trigger: address match, Start Bit detection or RXNE bit status. + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (+) HAL_UARTEx_DisableStopMode() API disables the above functionality + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** #endif + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** [..] This subsection also provides a set of additional functions providing enhanced reception + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** services to user. (For example, these functions allow application to handle use cases + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** where number of data to be received is unknown). + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (#) Compared to standard reception services which only consider number of received + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** data elements as reception completion criteria, these functions also consider additional ev + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** as triggers for updating reception status to caller : + ARM GAS /tmp/cc5ct5Ve.s page 6 + + + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (+) Detection of inactivity period (RX line has not been active for a given period). + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** for 1 frame time, after last received byte. + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (++) RX inactivity detected by RTO, i.e. line has been in idle state + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** for a programmable time, after last received byte. + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (+) Detection that a specific character has been received. + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (#) There are two mode of transfer: + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (+) Blocking mode: The reception is performed in polling mode, until either expected number + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** or till IDLE event occurs. Reception is handled only during function execution. + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** When function exits, no data reception could occur. HAL status and number of actually re + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** are returned by function after finishing transfer. + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** These API's return the HAL status. + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** The end of the data processing will be indicated through the + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** The HAL_UART_ErrorCallback()user callback will be executed when a reception error is det + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (#) Blocking mode API: + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (+) HAL_UARTEx_ReceiveToIdle() + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (#) Non-Blocking mode API with Interrupt: + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (+) HAL_UARTEx_ReceiveToIdle_IT() + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (#) Non-Blocking mode API with DMA: + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (+) HAL_UARTEx_ReceiveToIdle_DMA() + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** @endverbatim + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @{ + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** #if defined(USART_CR3_UCESM) + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @brief Keep UART Clock enabled when in Stop Mode. + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @note When the USART clock source is configured to be LSE or HSI, it is possible to keep enab + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * this clock during STOP mode by setting the UCESM bit in USART_CR3 control register. + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @note When LPUART is used to wakeup from stop with LSE is selected as LPUART clock source, + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * and desired baud rate is 9600 baud, the bit UCESM bit in LPUART_CR3 control register mu + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param huart UART handle. + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @retval HAL status + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart) + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Process Locked */ + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** __HAL_LOCK(huart); + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Set UCESM bit */ + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_UCESM); + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Process Unlocked */ + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return HAL_OK; + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** + ARM GAS /tmp/cc5ct5Ve.s page 7 + + + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @brief Disable UART Clock when in Stop Mode. + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param huart UART handle. + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @retval HAL status + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart) + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Process Locked */ + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** __HAL_LOCK(huart); + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Clear UCESM bit */ + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_UCESM); + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Process Unlocked */ + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return HAL_OK; + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** #endif /* USART_CR3_UCESM */ + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @brief By default in multiprocessor mode, when the wake up method is set + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * to address mark, the UART handles only 4-bit long addresses detection; + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * this API allows to enable longer addresses detection (6-, 7- or 8-bit + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * long). + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param huart UART handle. + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param AddressLength This parameter can be one of the following values: + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @retval HAL status + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t Addres + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Check the UART handle allocation */ + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (huart == NULL) + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return HAL_ERROR; + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Check the address length parameter */ + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Disable the Peripheral */ + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Set the address length */ + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Enable the Peripheral */ + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** __HAL_UART_ENABLE(huart); + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* TEACK and/or REACK to check before moving huart->gState to Ready */ + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return (UART_CheckIdleState(huart)); + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + ARM GAS /tmp/cc5ct5Ve.s page 8 + + + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** #if defined(USART_CR1_UESM) + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @brief Set Wakeup from Stop mode interrupt flag selection. + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @note It is the application responsibility to enable the interrupt used as + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * usart_wkup interrupt source before entering low-power mode. + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param huart UART handle. + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * This parameter can be one of the following values: + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @arg @ref UART_WAKEUP_ON_ADDRESS + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @arg @ref UART_WAKEUP_ON_STARTBIT + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @retval HAL status + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeD + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uint32_t tickstart; + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* check the wake-up from stop mode UART instance */ + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* check the wake-up selection parameter */ + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Process Locked */ + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** __HAL_LOCK(huart); + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_BUSY; + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Disable the Peripheral */ + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** __HAL_UART_DISABLE(huart); + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** #if defined(USART_CR3_WUS) + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Set the wake-up selection scheme */ + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** #endif /* USART_CR3_WUS */ + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Enable the Peripheral */ + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** __HAL_UART_ENABLE(huart); + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Init tickstart for timeout management */ + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** tickstart = HAL_GetTick(); + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Wait until REACK flag is set */ + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** status = HAL_TIMEOUT; + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** else + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Initialize the UART State */ + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->gState = HAL_UART_STATE_READY; + ARM GAS /tmp/cc5ct5Ve.s page 9 + + + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Process Unlocked */ + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return status; + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @brief Enable UART Stop Mode. + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param huart UART handle. + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @retval HAL status + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Process Locked */ + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** __HAL_LOCK(huart); + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Set UESM bit */ + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Process Unlocked */ + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return HAL_OK; + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @brief Disable UART Stop Mode. + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param huart UART handle. + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @retval HAL status + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Process Locked */ + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** __HAL_LOCK(huart); + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Clear UESM bit */ + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Process Unlocked */ + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** __HAL_UNLOCK(huart); + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return HAL_OK; + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** #endif /* USART_CR1_UESM */ + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @brief Receive an amount of data in blocking mode till either the expected number of data + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * is received or an IDLE event occurs. + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @note HAL_OK is returned if reception is completed (expected number of data has been received) + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * or if reception is stopped after IDLE event (less than the expected number of data has b + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * In this case, RxLen output parameter indicates number of data available in reception buf + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * the received data is handled as a set of uint16_t. In this case, Size must indicate the + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * of uint16_t available through pData. + ARM GAS /tmp/cc5ct5Ve.s page 10 + + + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param huart UART handle. + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param RxLen Number of data elements finally received + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * (could be lower than Size, in case reception ends on IDLE event) + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @retval HAL status + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uint32_t Timeout) + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uint8_t *pdata8bits; + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uint16_t *pdata16bits; + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uint16_t uhMask; + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uint32_t tickstart; + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Check that a Rx process is not already ongoing */ + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (huart->RxState == HAL_UART_STATE_READY) + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if ((pData == NULL) || (Size == 0U)) + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return HAL_ERROR; + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->ErrorCode = HAL_UART_ERROR_NONE; + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Init tickstart for timeout management */ + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** tickstart = HAL_GetTick(); + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxXferSize = Size; + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxXferCount = Size; + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Computation of UART mask to apply to RDR register */ + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** UART_MASK_COMPUTATION(huart); + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uhMask = huart->Mask; + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** pdata8bits = NULL; + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** pdata16bits = (uint16_t *) pData; + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** else + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** pdata8bits = pData; + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** pdata16bits = NULL; + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Initialize output number of received elements */ + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** *RxLen = 0U; + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* as long as data have to be received */ + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** while (huart->RxXferCount > 0U) + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + ARM GAS /tmp/cc5ct5Ve.s page 11 + + + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Check if IDLE flag is set */ + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Clear IDLE flag in ISR */ + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* If Set, but no data ever received, clear flag without exiting loop */ + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* If Set, and data has already been received, this means Idle Event is valid : End recepti + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (*RxLen > 0U) + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_IDLE; + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_READY; + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return HAL_OK; + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Check if RXNE flag is set */ + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (pdata8bits == NULL) + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** pdata16bits++; + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** else + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** pdata8bits++; + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Increment number of received elements */ + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** *RxLen += 1U; + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxXferCount--; + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Check for the Timeout */ + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (Timeout != HAL_MAX_DELAY) + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_READY; + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return HAL_TIMEOUT; + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Set number of received elements in output parameter : RxLen */ + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** *RxLen = huart->RxXferSize - huart->RxXferCount; + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* At end of Rx process, restore huart->RxState to Ready */ + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_READY; + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return HAL_OK; + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** else + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return HAL_BUSY; + ARM GAS /tmp/cc5ct5Ve.s page 12 + + + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @brief Receive an amount of data in interrupt mode till either the expected number of data + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * is received or an IDLE event occurs. + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @note Reception is initiated by this function call. Further progress of reception is achieved + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of receptio + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * number of received data elements. + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * the received data is handled as a set of uint16_t. In this case, Size must indicate the + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * of uint16_t available through pData. + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param huart UART handle. + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @retval HAL status + 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t S + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Check that a Rx process is not already ongoing */ + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (huart->RxState == HAL_UART_STATE_READY) + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if ((pData == NULL) || (Size == 0U)) + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return HAL_ERROR; + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Set Reception type to reception till IDLE Event*/ + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (void)UART_Start_Receive_IT(huart, pData, Size); + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** else + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* In case of errors already pending when reception is started, + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** Interrupts may have already been raised and lead to reception abortion. + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (Overrun error for instance). + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** status = HAL_ERROR; + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return status; + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** else + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return HAL_BUSY; + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + ARM GAS /tmp/cc5ct5Ve.s page 13 + + + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @brief Receive an amount of data in DMA mode till either the expected number + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * of data is received or an IDLE event occurs. + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @note Reception is initiated by this function call. Further progress of reception is achieved + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * to DMA services, transferring automatically received data elements in user reception buf + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * calling registered callbacks at half/end of reception. UART IDLE events are also used to + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * reception phase as ended. In all cases, callback execution will indicate number of recei + 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @note When the UART parity is enabled (PCE = 1), the received data contain + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * the parity bit (MSB position). + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * the received data is handled as a set of uint16_t. In this case, Size must indicate the + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * of uint16_t available through pData. + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param huart UART handle. + 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @retval HAL status + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_StatusTypeDef status; + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Check that a Rx process is not already ongoing */ + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (huart->RxState == HAL_UART_STATE_READY) + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if ((pData == NULL) || (Size == 0U)) + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return HAL_ERROR; + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Set Reception type to reception till IDLE Event*/ + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** status = UART_Start_Receive_DMA(huart, pData, Size); + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Check Rx process has been successfully started */ + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (status == HAL_OK) + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** else + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* In case of errors already pending when reception is started, + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** Interrupts may have already been raised and lead to reception abortion. + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** (Overrun error for instance). + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** status = HAL_ERROR; + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return status; + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** else + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + ARM GAS /tmp/cc5ct5Ve.s page 14 + + + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return HAL_BUSY; + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @brief Provide Rx Event type that has lead to RxEvent callback execution. + 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, pro + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * of reception process is provided to application through calls of Rx Event callback (eith + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could o + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * to Rx Event callback execution. + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @note This function is expected to be called within the user implementation of Rx Event Callba + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * in order to provide the accurate value : + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * In Interrupt Mode : + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has be + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * received data is lower than expected one) + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * In DMA Mode : + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has be + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * received data is lower than expected one). + 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * In DMA mode, RxEvent callback could be called several times; + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * When DMA is configured in Normal Mode, HT event does not stop Reception process; + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception proc + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param huart UART handle. + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart) + 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Return Rx Event type value, as stored in UART handle */ + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** return (huart->RxEventType); + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @} + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @} + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** @addtogroup UARTEx_Private_Functions + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @{ + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** #if defined(USART_CR1_UESM) + 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /** + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detectio + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param huart UART handle. + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @param WakeUpSelection UART wake up from stop mode parameters. + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** * @retval None + 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** */ + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelecti + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 28 .loc 1 770 1 view -0 + 29 .cfi_startproc + ARM GAS /tmp/cc5ct5Ve.s page 15 + + + 30 @ args = 0, pretend = 0, frame = 8 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .loc 1 770 1 is_stmt 0 view .LVU1 + 34 0000 82B0 sub sp, sp, #8 + 35 .LCFI0: + 36 .cfi_def_cfa_offset 8 + 37 0002 02AB add r3, sp, #8 + 38 0004 03E90600 stmdb r3, {r1, r2} + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); + 39 .loc 1 771 3 is_stmt 1 view .LVU2 + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Set the USART address length */ + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); + 40 .loc 1 774 3 view .LVU3 + 41 0008 0268 ldr r2, [r0] + 42 000a 5368 ldr r3, [r2, #4] + 43 000c 23F01003 bic r3, r3, #16 + 44 0010 BDF80410 ldrh r1, [sp, #4] + 45 0014 0B43 orrs r3, r3, r1 + 46 0016 5360 str r3, [r2, #4] + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Set the USART address node */ + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_AD + 47 .loc 1 777 3 view .LVU4 + 48 0018 0268 ldr r2, [r0] + 49 001a 5368 ldr r3, [r2, #4] + 50 001c 23F07F43 bic r3, r3, #-16777216 + 51 0020 9DF80610 ldrb r1, [sp, #6] @ zero_extendqisi2 + 52 0024 43EA0163 orr r3, r3, r1, lsl #24 + 53 0028 5360 str r3, [r2, #4] + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 54 .loc 1 778 1 is_stmt 0 view .LVU5 + 55 002a 02B0 add sp, sp, #8 + 56 .LCFI1: + 57 .cfi_def_cfa_offset 0 + 58 @ sp needed + 59 002c 7047 bx lr + 60 .cfi_endproc + 61 .LFE152: + 63 .section .text.HAL_RS485Ex_Init,"ax",%progbits + 64 .align 1 + 65 .global HAL_RS485Ex_Init + 66 .syntax unified + 67 .thumb + 68 .thumb_func + 70 HAL_RS485Ex_Init: + 71 .LVL1: + 72 .LFB141: + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uint32_t temp; + 73 .loc 1 152 1 is_stmt 1 view -0 + 74 .cfi_startproc + 75 @ args = 0, pretend = 0, frame = 0 + 76 @ frame_needed = 0, uses_anonymous_args = 0 + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 77 .loc 1 153 3 view .LVU7 + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + ARM GAS /tmp/cc5ct5Ve.s page 16 + + + 78 .loc 1 156 3 view .LVU8 + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 79 .loc 1 156 6 is_stmt 0 view .LVU9 + 80 0000 0028 cmp r0, #0 + 81 0002 3AD0 beq .L7 + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uint32_t temp; + 82 .loc 1 152 1 view .LVU10 + 83 0004 F8B5 push {r3, r4, r5, r6, r7, lr} + 84 .LCFI2: + 85 .cfi_def_cfa_offset 24 + 86 .cfi_offset 3, -24 + 87 .cfi_offset 4, -20 + 88 .cfi_offset 5, -16 + 89 .cfi_offset 6, -12 + 90 .cfi_offset 7, -8 + 91 .cfi_offset 14, -4 + 92 0006 0F46 mov r7, r1 + 93 0008 1646 mov r6, r2 + 94 000a 1D46 mov r5, r3 + 95 000c 0446 mov r4, r0 + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 96 .loc 1 161 3 is_stmt 1 view .LVU11 + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 97 .loc 1 164 3 view .LVU12 + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 98 .loc 1 167 3 view .LVU13 + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 99 .loc 1 170 3 view .LVU14 + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 100 .loc 1 172 3 view .LVU15 + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 101 .loc 1 172 12 is_stmt 0 view .LVU16 + 102 000e C36F ldr r3, [r0, #124] + 103 .LVL2: + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 104 .loc 1 172 6 view .LVU17 + 105 0010 53B3 cbz r3, .L12 + 106 .LVL3: + 107 .L5: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 108 .loc 1 193 3 is_stmt 1 view .LVU18 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 109 .loc 1 193 17 is_stmt 0 view .LVU19 + 110 0012 2423 movs r3, #36 + 111 0014 E367 str r3, [r4, #124] + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 112 .loc 1 196 3 is_stmt 1 view .LVU20 + 113 0016 2268 ldr r2, [r4] + 114 0018 1368 ldr r3, [r2] + 115 001a 23F00103 bic r3, r3, #1 + 116 001e 1360 str r3, [r2] + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 117 .loc 1 200 3 view .LVU21 + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 118 .loc 1 200 26 is_stmt 0 view .LVU22 + 119 0020 636A ldr r3, [r4, #36] + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + ARM GAS /tmp/cc5ct5Ve.s page 17 + + + 120 .loc 1 200 6 view .LVU23 + 121 0022 33BB cbnz r3, .L13 + 122 .L6: + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 123 .loc 1 206 3 is_stmt 1 view .LVU24 + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 124 .loc 1 206 7 is_stmt 0 view .LVU25 + 125 0024 2046 mov r0, r4 + 126 0026 FFF7FEFF bl UART_SetConfig + 127 .LVL4: + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 128 .loc 1 206 6 discriminator 1 view .LVU26 + 129 002a 0128 cmp r0, #1 + 130 002c 1BD0 beq .L4 + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 131 .loc 1 212 3 is_stmt 1 view .LVU27 + 132 002e 2268 ldr r2, [r4] + 133 0030 9368 ldr r3, [r2, #8] + 134 0032 43F48043 orr r3, r3, #16384 + 135 0036 9360 str r3, [r2, #8] + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 136 .loc 1 215 3 view .LVU28 + 137 0038 2268 ldr r2, [r4] + 138 003a 9368 ldr r3, [r2, #8] + 139 003c 23F40043 bic r3, r3, #32768 + 140 0040 3B43 orrs r3, r3, r7 + 141 0042 9360 str r3, [r2, #8] + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + 142 .loc 1 218 3 view .LVU29 + 143 .LVL5: + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + 144 .loc 1 219 3 view .LVU30 + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + 145 .loc 1 219 28 is_stmt 0 view .LVU31 + 146 0044 2D04 lsls r5, r5, #16 + 147 .LVL6: + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + 148 .loc 1 219 8 view .LVU32 + 149 0046 45EA4652 orr r2, r5, r6, lsl #21 + 150 .LVL7: + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 151 .loc 1 220 3 is_stmt 1 view .LVU33 + 152 004a 2168 ldr r1, [r4] + 153 004c 0B68 ldr r3, [r1] + 154 004e 6FF31943 bfc r3, #16, #10 + 155 0052 1343 orrs r3, r3, r2 + 156 0054 0B60 str r3, [r1] + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 157 .loc 1 223 3 view .LVU34 + 158 0056 2268 ldr r2, [r4] + 159 .LVL8: + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 160 .loc 1 223 3 is_stmt 0 view .LVU35 + 161 0058 1368 ldr r3, [r2] + 162 005a 43F00103 orr r3, r3, #1 + 163 005e 1360 str r3, [r2] + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + ARM GAS /tmp/cc5ct5Ve.s page 18 + + + 164 .loc 1 226 3 is_stmt 1 view .LVU36 + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 165 .loc 1 226 11 is_stmt 0 view .LVU37 + 166 0060 2046 mov r0, r4 + 167 0062 FFF7FEFF bl UART_CheckIdleState + 168 .LVL9: + 169 .L4: + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 170 .loc 1 227 1 view .LVU38 + 171 0066 F8BD pop {r3, r4, r5, r6, r7, pc} + 172 .LVL10: + 173 .L12: + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 174 .loc 1 175 5 is_stmt 1 view .LVU39 + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 175 .loc 1 175 17 is_stmt 0 view .LVU40 + 176 0068 80F87830 strb r3, [r0, #120] + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 177 .loc 1 189 5 is_stmt 1 view .LVU41 + 178 006c FFF7FEFF bl HAL_UART_MspInit + 179 .LVL11: + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + 180 .loc 1 189 5 is_stmt 0 view .LVU42 + 181 0070 CFE7 b .L5 + 182 .L13: + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 183 .loc 1 202 5 is_stmt 1 view .LVU43 + 184 0072 2046 mov r0, r4 + 185 0074 FFF7FEFF bl UART_AdvFeatureConfig + 186 .LVL12: + 187 0078 D4E7 b .L6 + 188 .LVL13: + 189 .L7: + 190 .LCFI3: + 191 .cfi_def_cfa_offset 0 + 192 .cfi_restore 3 + 193 .cfi_restore 4 + 194 .cfi_restore 5 + 195 .cfi_restore 6 + 196 .cfi_restore 7 + 197 .cfi_restore 14 + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 198 .loc 1 158 12 is_stmt 0 view .LVU44 + 199 007a 0120 movs r0, #1 + 200 .LVL14: + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 201 .loc 1 227 1 view .LVU45 + 202 007c 7047 bx lr + 203 .cfi_endproc + 204 .LFE141: + 206 .section .text.HAL_UARTEx_EnableClockStopMode,"ax",%progbits + 207 .align 1 + 208 .global HAL_UARTEx_EnableClockStopMode + 209 .syntax unified + 210 .thumb + 211 .thumb_func + 213 HAL_UARTEx_EnableClockStopMode: + ARM GAS /tmp/cc5ct5Ve.s page 19 + + + 214 .LVL15: + 215 .LFB142: + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Process Locked */ + 216 .loc 1 303 1 is_stmt 1 view -0 + 217 .cfi_startproc + 218 @ args = 0, pretend = 0, frame = 0 + 219 @ frame_needed = 0, uses_anonymous_args = 0 + 220 @ link register save eliminated. + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 221 .loc 1 305 3 view .LVU47 + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 222 .loc 1 305 3 view .LVU48 + 223 0000 90F87830 ldrb r3, [r0, #120] @ zero_extendqisi2 + 224 0004 012B cmp r3, #1 + 225 0006 13D0 beq .L17 + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 226 .loc 1 305 3 discriminator 2 view .LVU49 + 227 0008 0123 movs r3, #1 + 228 000a 80F87830 strb r3, [r0, #120] + 229 .L16: + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 230 .loc 1 305 3 discriminator 3 view .LVU50 + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 231 .loc 1 308 3 discriminator 1 view .LVU51 + 232 .LBB32: + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 233 .loc 1 308 3 discriminator 1 view .LVU52 + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 234 .loc 1 308 3 discriminator 1 view .LVU53 + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 235 .loc 1 308 3 discriminator 1 view .LVU54 + 236 000e 0268 ldr r2, [r0] + 237 .LVL16: + 238 .LBB33: + 239 .LBI33: + 240 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + ARM GAS /tmp/cc5ct5Ve.s page 20 + + + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + ARM GAS /tmp/cc5ct5Ve.s page 21 + + + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/cc5ct5Ve.s page 22 + + + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/cc5ct5Ve.s page 23 + + + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + ARM GAS /tmp/cc5ct5Ve.s page 24 + + + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/cc5ct5Ve.s page 25 + + + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cc5ct5Ve.s page 26 + + + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + ARM GAS /tmp/cc5ct5Ve.s page 27 + + + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/cc5ct5Ve.s page 28 + + + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cc5ct5Ve.s page 29 + + + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/cc5ct5Ve.s page 30 + + + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cc5ct5Ve.s page 31 + + + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + ARM GAS /tmp/cc5ct5Ve.s page 32 + + + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + ARM GAS /tmp/cc5ct5Ve.s page 33 + + + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + ARM GAS /tmp/cc5ct5Ve.s page 34 + + + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/cc5ct5Ve.s page 35 + + + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 881:Drivers/CMSIS/Include/cmsis_gcc.h **** + 882:Drivers/CMSIS/Include/cmsis_gcc.h **** + 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier + 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. + 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) + 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); + 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 892:Drivers/CMSIS/Include/cmsis_gcc.h **** + 893:Drivers/CMSIS/Include/cmsis_gcc.h **** + 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) + 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 + 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) + 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); + 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 906:Drivers/CMSIS/Include/cmsis_gcc.h **** + 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 911:Drivers/CMSIS/Include/cmsis_gcc.h **** + 912:Drivers/CMSIS/Include/cmsis_gcc.h **** + 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes + 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) + 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 922:Drivers/CMSIS/Include/cmsis_gcc.h **** + 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 926:Drivers/CMSIS/Include/cmsis_gcc.h **** + 927:Drivers/CMSIS/Include/cmsis_gcc.h **** + 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam + 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/cc5ct5Ve.s page 36 + + + 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); + 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; + 940:Drivers/CMSIS/Include/cmsis_gcc.h **** + 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 945:Drivers/CMSIS/Include/cmsis_gcc.h **** + 946:Drivers/CMSIS/Include/cmsis_gcc.h **** + 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) + 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v + 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate + 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate + 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value + 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) + 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; + 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) + 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; + 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); + 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 963:Drivers/CMSIS/Include/cmsis_gcc.h **** + 964:Drivers/CMSIS/Include/cmsis_gcc.h **** + 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint + 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. + 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula + 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. + 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break + 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) + 973:Drivers/CMSIS/Include/cmsis_gcc.h **** + 974:Drivers/CMSIS/Include/cmsis_gcc.h **** + 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value + 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. + 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) + 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 984:Drivers/CMSIS/Include/cmsis_gcc.h **** + 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + ARM GAS /tmp/cc5ct5Ve.s page 37 + + + 991:Drivers/CMSIS/Include/cmsis_gcc.h **** + 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ + 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) + 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; + 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; + 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; + 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ +1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; +1002:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1003:Drivers/CMSIS/Include/cmsis_gcc.h **** +1004:Drivers/CMSIS/Include/cmsis_gcc.h **** +1005:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1006:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Count leading zeros +1007:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Counts the number of leading zeros of a data value. +1008:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to count the leading zeros +1009:Drivers/CMSIS/Include/cmsis_gcc.h **** \return number of leading zeros in value +1010:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1011:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CLZ (uint8_t)__builtin_clz +1012:Drivers/CMSIS/Include/cmsis_gcc.h **** +1013:Drivers/CMSIS/Include/cmsis_gcc.h **** +1014:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +1015:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ +1016:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ +1017:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +1018:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1019:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (8 bit) +1020:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 8 bit value. +1021:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data +1022:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) +1023:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1024:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +1025:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1026:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; +1027:Drivers/CMSIS/Include/cmsis_gcc.h **** +1028:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) +1029:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +1030:Drivers/CMSIS/Include/cmsis_gcc.h **** #else +1031:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not +1032:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. +1033:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1034:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +1035:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1036:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */ +1037:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1038:Drivers/CMSIS/Include/cmsis_gcc.h **** +1039:Drivers/CMSIS/Include/cmsis_gcc.h **** +1040:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1041:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (16 bit) +1042:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 16 bit values. +1043:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data +1044:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) +1045:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1046:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +1047:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/cc5ct5Ve.s page 38 + + +1048:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; +1049:Drivers/CMSIS/Include/cmsis_gcc.h **** +1050:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) +1051:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +1052:Drivers/CMSIS/Include/cmsis_gcc.h **** #else +1053:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not +1054:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. +1055:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1056:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +1057:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1058:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */ +1059:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1060:Drivers/CMSIS/Include/cmsis_gcc.h **** +1061:Drivers/CMSIS/Include/cmsis_gcc.h **** +1062:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1063:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (32 bit) +1064:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 32 bit values. +1065:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data +1066:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) +1067:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) + 241 .loc 2 1068 31 view .LVU55 + 242 .LBB34: +1069:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 243 .loc 2 1070 5 view .LVU56 +1071:Drivers/CMSIS/Include/cmsis_gcc.h **** +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 244 .loc 2 1072 4 view .LVU57 + 245 0010 02F10803 add r3, r2, #8 + 246 .LVL17: + 247 .loc 2 1072 4 is_stmt 0 view .LVU58 + 248 .syntax unified + 249 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 250 0014 53E8003F ldrex r3, [r3] + 251 @ 0 "" 2 + 252 .LVL18: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253 .loc 2 1073 4 is_stmt 1 view .LVU59 + 254 .loc 2 1073 4 is_stmt 0 view .LVU60 + 255 .thumb + 256 .syntax unified + 257 .LBE34: + 258 .LBE33: + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 259 .loc 1 308 3 discriminator 1 view .LVU61 + 260 0018 43F40003 orr r3, r3, #8388608 + 261 .LVL19: + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 262 .loc 1 308 3 is_stmt 1 discriminator 1 view .LVU62 + 263 .LBB35: + 264 .LBI35: +1074:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1075:Drivers/CMSIS/Include/cmsis_gcc.h **** +1076:Drivers/CMSIS/Include/cmsis_gcc.h **** +1077:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1078:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (8 bit) + ARM GAS /tmp/cc5ct5Ve.s page 39 + + +1079:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 8 bit values. +1080:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store +1081:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location +1082:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded +1083:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed +1084:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1085:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +1086:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1087:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; +1088:Drivers/CMSIS/Include/cmsis_gcc.h **** +1089:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); +1090:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); +1091:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1092:Drivers/CMSIS/Include/cmsis_gcc.h **** +1093:Drivers/CMSIS/Include/cmsis_gcc.h **** +1094:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1095:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (16 bit) +1096:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 16 bit values. +1097:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store +1098:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location +1099:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded +1100:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed +1101:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1102:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +1103:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1104:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; +1105:Drivers/CMSIS/Include/cmsis_gcc.h **** +1106:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); +1107:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); +1108:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1109:Drivers/CMSIS/Include/cmsis_gcc.h **** +1110:Drivers/CMSIS/Include/cmsis_gcc.h **** +1111:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1112:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (32 bit) +1113:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 32 bit values. +1114:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store +1115:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location +1116:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded +1117:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed +1118:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) + 265 .loc 2 1119 31 view .LVU63 + 266 .LBB36: +1120:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 267 .loc 2 1121 4 view .LVU64 +1122:Drivers/CMSIS/Include/cmsis_gcc.h **** +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 268 .loc 2 1123 4 view .LVU65 + 269 001c 0832 adds r2, r2, #8 + 270 .LVL20: + 271 .loc 2 1123 4 is_stmt 0 view .LVU66 + 272 .syntax unified + 273 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 274 001e 42E80031 strex r1, r3, [r2] + 275 @ 0 "" 2 + 276 .LVL21: + ARM GAS /tmp/cc5ct5Ve.s page 40 + + +1124:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 277 .loc 2 1124 4 is_stmt 1 view .LVU67 + 278 .loc 2 1124 4 is_stmt 0 view .LVU68 + 279 .thumb + 280 .syntax unified + 281 .LBE36: + 282 .LBE35: + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 283 .loc 1 308 3 discriminator 1 view .LVU69 + 284 0022 0029 cmp r1, #0 + 285 0024 F3D1 bne .L16 + 286 .LBE32: + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 287 .loc 1 308 3 is_stmt 1 discriminator 2 view .LVU70 + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 288 .loc 1 311 3 view .LVU71 + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 289 .loc 1 311 3 view .LVU72 + 290 0026 0023 movs r3, #0 + 291 .LVL22: + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 292 .loc 1 311 3 is_stmt 0 view .LVU73 + 293 0028 80F87830 strb r3, [r0, #120] + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 294 .loc 1 311 3 is_stmt 1 view .LVU74 + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 295 .loc 1 313 3 view .LVU75 + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 296 .loc 1 313 10 is_stmt 0 view .LVU76 + 297 002c 1846 mov r0, r3 + 298 .LVL23: + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 299 .loc 1 313 10 view .LVU77 + 300 002e 7047 bx lr + 301 .LVL24: + 302 .L17: + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 303 .loc 1 305 3 discriminator 1 view .LVU78 + 304 0030 0220 movs r0, #2 + 305 .LVL25: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 306 .loc 1 314 1 view .LVU79 + 307 0032 7047 bx lr + 308 .cfi_endproc + 309 .LFE142: + 311 .section .text.HAL_UARTEx_DisableClockStopMode,"ax",%progbits + 312 .align 1 + 313 .global HAL_UARTEx_DisableClockStopMode + 314 .syntax unified + 315 .thumb + 316 .thumb_func + 318 HAL_UARTEx_DisableClockStopMode: + 319 .LVL26: + 320 .LFB143: + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Process Locked */ + 321 .loc 1 322 1 is_stmt 1 view -0 + 322 .cfi_startproc + ARM GAS /tmp/cc5ct5Ve.s page 41 + + + 323 @ args = 0, pretend = 0, frame = 0 + 324 @ frame_needed = 0, uses_anonymous_args = 0 + 325 @ link register save eliminated. + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 326 .loc 1 324 3 view .LVU81 + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 327 .loc 1 324 3 view .LVU82 + 328 0000 90F87830 ldrb r3, [r0, #120] @ zero_extendqisi2 + 329 0004 012B cmp r3, #1 + 330 0006 13D0 beq .L21 + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 331 .loc 1 324 3 discriminator 2 view .LVU83 + 332 0008 0123 movs r3, #1 + 333 000a 80F87830 strb r3, [r0, #120] + 334 .L20: + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 335 .loc 1 324 3 discriminator 3 view .LVU84 + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 336 .loc 1 327 3 discriminator 1 view .LVU85 + 337 .LBB37: + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 338 .loc 1 327 3 discriminator 1 view .LVU86 + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 339 .loc 1 327 3 discriminator 1 view .LVU87 + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 340 .loc 1 327 3 discriminator 1 view .LVU88 + 341 000e 0268 ldr r2, [r0] + 342 .LVL27: + 343 .LBB38: + 344 .LBI38: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345 .loc 2 1068 31 view .LVU89 + 346 .LBB39: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 347 .loc 2 1070 5 view .LVU90 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 348 .loc 2 1072 4 view .LVU91 + 349 0010 02F10803 add r3, r2, #8 + 350 .LVL28: +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 351 .loc 2 1072 4 is_stmt 0 view .LVU92 + 352 .syntax unified + 353 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 354 0014 53E8003F ldrex r3, [r3] + 355 @ 0 "" 2 + 356 .LVL29: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 357 .loc 2 1073 4 is_stmt 1 view .LVU93 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 358 .loc 2 1073 4 is_stmt 0 view .LVU94 + 359 .thumb + 360 .syntax unified + 361 .LBE39: + 362 .LBE38: + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 363 .loc 1 327 3 discriminator 1 view .LVU95 + 364 0018 23F40003 bic r3, r3, #8388608 + ARM GAS /tmp/cc5ct5Ve.s page 42 + + + 365 .LVL30: + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 366 .loc 1 327 3 is_stmt 1 discriminator 1 view .LVU96 + 367 .LBB40: + 368 .LBI40: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 369 .loc 2 1119 31 view .LVU97 + 370 .LBB41: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 371 .loc 2 1121 4 view .LVU98 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 372 .loc 2 1123 4 view .LVU99 + 373 001c 0832 adds r2, r2, #8 + 374 .LVL31: +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 375 .loc 2 1123 4 is_stmt 0 view .LVU100 + 376 .syntax unified + 377 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 378 001e 42E80031 strex r1, r3, [r2] + 379 @ 0 "" 2 + 380 .LVL32: + 381 .loc 2 1124 4 is_stmt 1 view .LVU101 + 382 .loc 2 1124 4 is_stmt 0 view .LVU102 + 383 .thumb + 384 .syntax unified + 385 .LBE41: + 386 .LBE40: + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 387 .loc 1 327 3 discriminator 1 view .LVU103 + 388 0022 0029 cmp r1, #0 + 389 0024 F3D1 bne .L20 + 390 .LBE37: + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 391 .loc 1 327 3 is_stmt 1 discriminator 2 view .LVU104 + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 392 .loc 1 330 3 view .LVU105 + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 393 .loc 1 330 3 view .LVU106 + 394 0026 0023 movs r3, #0 + 395 .LVL33: + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 396 .loc 1 330 3 is_stmt 0 view .LVU107 + 397 0028 80F87830 strb r3, [r0, #120] + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 398 .loc 1 330 3 is_stmt 1 view .LVU108 + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 399 .loc 1 332 3 view .LVU109 + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 400 .loc 1 332 10 is_stmt 0 view .LVU110 + 401 002c 1846 mov r0, r3 + 402 .LVL34: + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 403 .loc 1 332 10 view .LVU111 + 404 002e 7047 bx lr + 405 .LVL35: + 406 .L21: + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + ARM GAS /tmp/cc5ct5Ve.s page 43 + + + 407 .loc 1 324 3 discriminator 1 view .LVU112 + 408 0030 0220 movs r0, #2 + 409 .LVL36: + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 410 .loc 1 333 1 view .LVU113 + 411 0032 7047 bx lr + 412 .cfi_endproc + 413 .LFE143: + 415 .section .text.HAL_MultiProcessorEx_AddressLength_Set,"ax",%progbits + 416 .align 1 + 417 .global HAL_MultiProcessorEx_AddressLength_Set + 418 .syntax unified + 419 .thumb + 420 .thumb_func + 422 HAL_MultiProcessorEx_AddressLength_Set: + 423 .LVL37: + 424 .LFB144: + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Check the UART handle allocation */ + 425 .loc 1 350 1 is_stmt 1 view -0 + 426 .cfi_startproc + 427 @ args = 0, pretend = 0, frame = 0 + 428 @ frame_needed = 0, uses_anonymous_args = 0 + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 429 .loc 1 352 3 view .LVU115 + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 430 .loc 1 352 6 is_stmt 0 view .LVU116 + 431 0000 B8B1 cbz r0, .L24 + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Check the UART handle allocation */ + 432 .loc 1 350 1 view .LVU117 + 433 0002 08B5 push {r3, lr} + 434 .LCFI4: + 435 .cfi_def_cfa_offset 8 + 436 .cfi_offset 3, -8 + 437 .cfi_offset 14, -4 + 438 0004 0346 mov r3, r0 + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 439 .loc 1 358 3 is_stmt 1 view .LVU118 + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 440 .loc 1 360 3 view .LVU119 + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 441 .loc 1 360 17 is_stmt 0 view .LVU120 + 442 0006 2422 movs r2, #36 + 443 0008 C267 str r2, [r0, #124] + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 444 .loc 1 363 3 is_stmt 1 view .LVU121 + 445 000a 0068 ldr r0, [r0] + 446 .LVL38: + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 447 .loc 1 363 3 is_stmt 0 view .LVU122 + 448 000c 0268 ldr r2, [r0] + 449 000e 22F00102 bic r2, r2, #1 + 450 0012 0260 str r2, [r0] + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 451 .loc 1 366 3 is_stmt 1 view .LVU123 + 452 0014 1868 ldr r0, [r3] + 453 0016 4268 ldr r2, [r0, #4] + 454 0018 22F01002 bic r2, r2, #16 + ARM GAS /tmp/cc5ct5Ve.s page 44 + + + 455 001c 1143 orrs r1, r1, r2 + 456 .LVL39: + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 457 .loc 1 366 3 is_stmt 0 view .LVU124 + 458 001e 4160 str r1, [r0, #4] + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 459 .loc 1 369 3 is_stmt 1 view .LVU125 + 460 0020 1968 ldr r1, [r3] + 461 0022 0A68 ldr r2, [r1] + 462 0024 42F00102 orr r2, r2, #1 + 463 0028 0A60 str r2, [r1] + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 464 .loc 1 372 3 view .LVU126 + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 465 .loc 1 372 11 is_stmt 0 view .LVU127 + 466 002a 1846 mov r0, r3 + 467 002c FFF7FEFF bl UART_CheckIdleState + 468 .LVL40: + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 469 .loc 1 373 1 view .LVU128 + 470 0030 08BD pop {r3, pc} + 471 .LVL41: + 472 .L24: + 473 .LCFI5: + 474 .cfi_def_cfa_offset 0 + 475 .cfi_restore 3 + 476 .cfi_restore 14 + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 477 .loc 1 354 12 view .LVU129 + 478 0032 0120 movs r0, #1 + 479 .LVL42: + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 480 .loc 1 373 1 view .LVU130 + 481 0034 7047 bx lr + 482 .cfi_endproc + 483 .LFE144: + 485 .section .text.HAL_UARTEx_StopModeWakeUpSourceConfig,"ax",%progbits + 486 .align 1 + 487 .global HAL_UARTEx_StopModeWakeUpSourceConfig + 488 .syntax unified + 489 .thumb + 490 .thumb_func + 492 HAL_UARTEx_StopModeWakeUpSourceConfig: + 493 .LVL43: + 494 .LFB145: + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 495 .loc 1 389 1 is_stmt 1 view -0 + 496 .cfi_startproc + 497 @ args = 0, pretend = 0, frame = 8 + 498 @ frame_needed = 0, uses_anonymous_args = 0 + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 499 .loc 1 389 1 is_stmt 0 view .LVU132 + 500 0000 10B5 push {r4, lr} + 501 .LCFI6: + 502 .cfi_def_cfa_offset 8 + 503 .cfi_offset 4, -8 + 504 .cfi_offset 14, -4 + ARM GAS /tmp/cc5ct5Ve.s page 45 + + + 505 0002 84B0 sub sp, sp, #16 + 506 .LCFI7: + 507 .cfi_def_cfa_offset 24 + 508 0004 04AB add r3, sp, #16 + 509 0006 03E90600 stmdb r3, {r1, r2} + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uint32_t tickstart; + 510 .loc 1 390 3 is_stmt 1 view .LVU133 + 511 .LVL44: + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 512 .loc 1 391 3 view .LVU134 + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* check the wake-up selection parameter */ + 513 .loc 1 394 3 view .LVU135 + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 514 .loc 1 396 3 view .LVU136 + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 515 .loc 1 399 3 view .LVU137 + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 516 .loc 1 399 3 view .LVU138 + 517 000a 90F87830 ldrb r3, [r0, #120] @ zero_extendqisi2 + 518 000e 012B cmp r3, #1 + 519 0010 33D0 beq .L33 + 520 0012 0446 mov r4, r0 + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 521 .loc 1 399 3 discriminator 2 view .LVU139 + 522 0014 0123 movs r3, #1 + 523 0016 80F87830 strb r3, [r0, #120] + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 524 .loc 1 399 3 discriminator 2 view .LVU140 + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 525 .loc 1 401 3 view .LVU141 + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 526 .loc 1 401 17 is_stmt 0 view .LVU142 + 527 001a 2423 movs r3, #36 + 528 001c C367 str r3, [r0, #124] + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 529 .loc 1 404 3 is_stmt 1 view .LVU143 + 530 001e 0268 ldr r2, [r0] + 531 0020 1368 ldr r3, [r2] + 532 0022 23F00103 bic r3, r3, #1 + 533 0026 1360 str r3, [r2] + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** #endif /* USART_CR3_WUS */ + 534 .loc 1 408 3 view .LVU144 + 535 0028 0168 ldr r1, [r0] + 536 002a 8B68 ldr r3, [r1, #8] + 537 002c 23F44013 bic r3, r3, #3145728 + 538 0030 029A ldr r2, [sp, #8] + 539 0032 1343 orrs r3, r3, r2 + 540 0034 8B60 str r3, [r1, #8] + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 541 .loc 1 411 3 view .LVU145 + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 542 .loc 1 411 6 is_stmt 0 view .LVU146 + 543 0036 A2B1 cbz r2, .L36 + 544 .LVL45: + 545 .L31: + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 546 .loc 1 417 3 is_stmt 1 view .LVU147 + ARM GAS /tmp/cc5ct5Ve.s page 46 + + + 547 0038 2268 ldr r2, [r4] + 548 003a 1368 ldr r3, [r2] + 549 003c 43F00103 orr r3, r3, #1 + 550 0040 1360 str r3, [r2] + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 551 .loc 1 420 3 view .LVU148 + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 552 .loc 1 420 15 is_stmt 0 view .LVU149 + 553 0042 FFF7FEFF bl HAL_GetTick + 554 .LVL46: + 555 0046 0346 mov r3, r0 + 556 .LVL47: + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 557 .loc 1 423 3 is_stmt 1 view .LVU150 + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 558 .loc 1 423 7 is_stmt 0 view .LVU151 + 559 0048 6FF07E42 mvn r2, #-33554432 + 560 004c 0092 str r2, [sp] + 561 004e 0022 movs r2, #0 + 562 0050 4FF48001 mov r1, #4194304 + 563 0054 2046 mov r0, r4 + 564 .LVL48: + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 565 .loc 1 423 7 view .LVU152 + 566 0056 FFF7FEFF bl UART_WaitOnFlagUntilTimeout + 567 .LVL49: + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 568 .loc 1 423 6 discriminator 1 view .LVU153 + 569 005a 40B9 cbnz r0, .L34 + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 570 .loc 1 430 5 is_stmt 1 view .LVU154 + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 571 .loc 1 430 19 is_stmt 0 view .LVU155 + 572 005c 2023 movs r3, #32 + 573 005e E367 str r3, [r4, #124] + 574 0060 06E0 b .L32 + 575 .LVL50: + 576 .L36: + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 577 .loc 1 413 5 is_stmt 1 view .LVU156 + 578 0062 04AB add r3, sp, #16 + 579 0064 13E90600 ldmdb r3, {r1, r2} + 580 0068 FFF7FEFF bl UARTEx_Wakeup_AddressConfig + 581 .LVL51: + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 582 .loc 1 413 5 is_stmt 0 view .LVU157 + 583 006c E4E7 b .L31 + 584 .LVL52: + 585 .L34: + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 586 .loc 1 425 12 view .LVU158 + 587 006e 0320 movs r0, #3 + 588 .L32: + 589 .LVL53: + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 590 .loc 1 434 3 is_stmt 1 view .LVU159 + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + ARM GAS /tmp/cc5ct5Ve.s page 47 + + + 591 .loc 1 434 3 view .LVU160 + 592 0070 0023 movs r3, #0 + 593 0072 84F87830 strb r3, [r4, #120] + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 594 .loc 1 434 3 view .LVU161 + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 595 .loc 1 436 3 view .LVU162 + 596 .LVL54: + 597 .L30: + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 598 .loc 1 437 1 is_stmt 0 view .LVU163 + 599 0076 04B0 add sp, sp, #16 + 600 .LCFI8: + 601 .cfi_remember_state + 602 .cfi_def_cfa_offset 8 + 603 @ sp needed + 604 0078 10BD pop {r4, pc} + 605 .LVL55: + 606 .L33: + 607 .LCFI9: + 608 .cfi_restore_state + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 609 .loc 1 399 3 discriminator 1 view .LVU164 + 610 007a 0220 movs r0, #2 + 611 .LVL56: + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 612 .loc 1 399 3 discriminator 1 view .LVU165 + 613 007c FBE7 b .L30 + 614 .cfi_endproc + 615 .LFE145: + 617 .section .text.HAL_UARTEx_EnableStopMode,"ax",%progbits + 618 .align 1 + 619 .global HAL_UARTEx_EnableStopMode + 620 .syntax unified + 621 .thumb + 622 .thumb_func + 624 HAL_UARTEx_EnableStopMode: + 625 .LVL57: + 626 .LFB146: + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Process Locked */ + 627 .loc 1 446 1 is_stmt 1 view -0 + 628 .cfi_startproc + 629 @ args = 0, pretend = 0, frame = 0 + 630 @ frame_needed = 0, uses_anonymous_args = 0 + 631 @ link register save eliminated. + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 632 .loc 1 448 3 view .LVU167 + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 633 .loc 1 448 3 view .LVU168 + 634 0000 90F87830 ldrb r3, [r0, #120] @ zero_extendqisi2 + 635 0004 012B cmp r3, #1 + 636 0006 10D0 beq .L40 + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 637 .loc 1 448 3 discriminator 2 view .LVU169 + 638 0008 0123 movs r3, #1 + 639 000a 80F87830 strb r3, [r0, #120] + 640 .L39: + ARM GAS /tmp/cc5ct5Ve.s page 48 + + + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 641 .loc 1 448 3 discriminator 3 view .LVU170 + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 642 .loc 1 451 3 discriminator 1 view .LVU171 + 643 .LBB42: + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 644 .loc 1 451 3 discriminator 1 view .LVU172 + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 645 .loc 1 451 3 discriminator 1 view .LVU173 + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 646 .loc 1 451 3 discriminator 1 view .LVU174 + 647 000e 0268 ldr r2, [r0] + 648 .LVL58: + 649 .LBB43: + 650 .LBI43: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 651 .loc 2 1068 31 view .LVU175 + 652 .LBB44: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 653 .loc 2 1070 5 view .LVU176 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 654 .loc 2 1072 4 view .LVU177 + 655 .syntax unified + 656 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 657 0010 52E8003F ldrex r3, [r2] + 658 @ 0 "" 2 + 659 .LVL59: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 660 .loc 2 1073 4 view .LVU178 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 661 .loc 2 1073 4 is_stmt 0 view .LVU179 + 662 .thumb + 663 .syntax unified + 664 .LBE44: + 665 .LBE43: + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 666 .loc 1 451 3 discriminator 1 view .LVU180 + 667 0014 43F00203 orr r3, r3, #2 + 668 .LVL60: + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 669 .loc 1 451 3 is_stmt 1 discriminator 1 view .LVU181 + 670 .LBB45: + 671 .LBI45: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 672 .loc 2 1119 31 view .LVU182 + 673 .LBB46: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 674 .loc 2 1121 4 view .LVU183 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 675 .loc 2 1123 4 view .LVU184 + 676 .syntax unified + 677 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 678 0018 42E80031 strex r1, r3, [r2] + 679 @ 0 "" 2 + 680 .LVL61: + 681 .loc 2 1124 4 view .LVU185 + 682 .loc 2 1124 4 is_stmt 0 view .LVU186 + ARM GAS /tmp/cc5ct5Ve.s page 49 + + + 683 .thumb + 684 .syntax unified + 685 .LBE46: + 686 .LBE45: + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 687 .loc 1 451 3 discriminator 1 view .LVU187 + 688 001c 0029 cmp r1, #0 + 689 001e F6D1 bne .L39 + 690 .LBE42: + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 691 .loc 1 451 3 is_stmt 1 discriminator 2 view .LVU188 + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 692 .loc 1 454 3 view .LVU189 + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 693 .loc 1 454 3 view .LVU190 + 694 0020 0023 movs r3, #0 + 695 .LVL62: + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 696 .loc 1 454 3 is_stmt 0 view .LVU191 + 697 0022 80F87830 strb r3, [r0, #120] + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 698 .loc 1 454 3 is_stmt 1 view .LVU192 + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 699 .loc 1 456 3 view .LVU193 + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 700 .loc 1 456 10 is_stmt 0 view .LVU194 + 701 0026 1846 mov r0, r3 + 702 .LVL63: + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 703 .loc 1 456 10 view .LVU195 + 704 0028 7047 bx lr + 705 .LVL64: + 706 .L40: + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 707 .loc 1 448 3 discriminator 1 view .LVU196 + 708 002a 0220 movs r0, #2 + 709 .LVL65: + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 710 .loc 1 457 1 view .LVU197 + 711 002c 7047 bx lr + 712 .cfi_endproc + 713 .LFE146: + 715 .section .text.HAL_UARTEx_DisableStopMode,"ax",%progbits + 716 .align 1 + 717 .global HAL_UARTEx_DisableStopMode + 718 .syntax unified + 719 .thumb + 720 .thumb_func + 722 HAL_UARTEx_DisableStopMode: + 723 .LVL66: + 724 .LFB147: + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Process Locked */ + 725 .loc 1 465 1 is_stmt 1 view -0 + 726 .cfi_startproc + 727 @ args = 0, pretend = 0, frame = 0 + 728 @ frame_needed = 0, uses_anonymous_args = 0 + 729 @ link register save eliminated. + ARM GAS /tmp/cc5ct5Ve.s page 50 + + + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 730 .loc 1 467 3 view .LVU199 + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 731 .loc 1 467 3 view .LVU200 + 732 0000 90F87830 ldrb r3, [r0, #120] @ zero_extendqisi2 + 733 0004 012B cmp r3, #1 + 734 0006 10D0 beq .L44 + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 735 .loc 1 467 3 discriminator 2 view .LVU201 + 736 0008 0123 movs r3, #1 + 737 000a 80F87830 strb r3, [r0, #120] + 738 .L43: + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 739 .loc 1 467 3 discriminator 3 view .LVU202 + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 740 .loc 1 470 3 discriminator 1 view .LVU203 + 741 .LBB47: + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 742 .loc 1 470 3 discriminator 1 view .LVU204 + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 743 .loc 1 470 3 discriminator 1 view .LVU205 + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 744 .loc 1 470 3 discriminator 1 view .LVU206 + 745 000e 0268 ldr r2, [r0] + 746 .LVL67: + 747 .LBB48: + 748 .LBI48: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 749 .loc 2 1068 31 view .LVU207 + 750 .LBB49: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 751 .loc 2 1070 5 view .LVU208 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 752 .loc 2 1072 4 view .LVU209 + 753 .syntax unified + 754 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 755 0010 52E8003F ldrex r3, [r2] + 756 @ 0 "" 2 + 757 .LVL68: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 758 .loc 2 1073 4 view .LVU210 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 759 .loc 2 1073 4 is_stmt 0 view .LVU211 + 760 .thumb + 761 .syntax unified + 762 .LBE49: + 763 .LBE48: + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 764 .loc 1 470 3 discriminator 1 view .LVU212 + 765 0014 23F00203 bic r3, r3, #2 + 766 .LVL69: + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 767 .loc 1 470 3 is_stmt 1 discriminator 1 view .LVU213 + 768 .LBB50: + 769 .LBI50: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 770 .loc 2 1119 31 view .LVU214 + ARM GAS /tmp/cc5ct5Ve.s page 51 + + + 771 .LBB51: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 772 .loc 2 1121 4 view .LVU215 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 773 .loc 2 1123 4 view .LVU216 + 774 .syntax unified + 775 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 776 0018 42E80031 strex r1, r3, [r2] + 777 @ 0 "" 2 + 778 .LVL70: + 779 .loc 2 1124 4 view .LVU217 + 780 .loc 2 1124 4 is_stmt 0 view .LVU218 + 781 .thumb + 782 .syntax unified + 783 .LBE51: + 784 .LBE50: + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 785 .loc 1 470 3 discriminator 1 view .LVU219 + 786 001c 0029 cmp r1, #0 + 787 001e F6D1 bne .L43 + 788 .LBE47: + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 789 .loc 1 470 3 is_stmt 1 discriminator 2 view .LVU220 + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 790 .loc 1 473 3 view .LVU221 + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 791 .loc 1 473 3 view .LVU222 + 792 0020 0023 movs r3, #0 + 793 .LVL71: + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 794 .loc 1 473 3 is_stmt 0 view .LVU223 + 795 0022 80F87830 strb r3, [r0, #120] + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 796 .loc 1 473 3 is_stmt 1 view .LVU224 + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 797 .loc 1 475 3 view .LVU225 + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 798 .loc 1 475 10 is_stmt 0 view .LVU226 + 799 0026 1846 mov r0, r3 + 800 .LVL72: + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 801 .loc 1 475 10 view .LVU227 + 802 0028 7047 bx lr + 803 .LVL73: + 804 .L44: + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 805 .loc 1 467 3 discriminator 1 view .LVU228 + 806 002a 0220 movs r0, #2 + 807 .LVL74: + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 808 .loc 1 476 1 view .LVU229 + 809 002c 7047 bx lr + 810 .cfi_endproc + 811 .LFE147: + 813 .section .text.HAL_UARTEx_ReceiveToIdle,"ax",%progbits + 814 .align 1 + 815 .global HAL_UARTEx_ReceiveToIdle + ARM GAS /tmp/cc5ct5Ve.s page 52 + + + 816 .syntax unified + 817 .thumb + 818 .thumb_func + 820 HAL_UARTEx_ReceiveToIdle: + 821 .LVL75: + 822 .LFB148: + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uint8_t *pdata8bits; + 823 .loc 1 498 1 is_stmt 1 view -0 + 824 .cfi_startproc + 825 @ args = 4, pretend = 0, frame = 0 + 826 @ frame_needed = 0, uses_anonymous_args = 0 + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uint8_t *pdata8bits; + 827 .loc 1 498 1 is_stmt 0 view .LVU231 + 828 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, r10, lr} + 829 .LCFI10: + 830 .cfi_def_cfa_offset 32 + 831 .cfi_offset 4, -32 + 832 .cfi_offset 5, -28 + 833 .cfi_offset 6, -24 + 834 .cfi_offset 7, -20 + 835 .cfi_offset 8, -16 + 836 .cfi_offset 9, -12 + 837 .cfi_offset 10, -8 + 838 .cfi_offset 14, -4 + 839 0004 1D46 mov r5, r3 + 840 0006 089E ldr r6, [sp, #32] + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uint16_t *pdata16bits; + 841 .loc 1 499 3 is_stmt 1 view .LVU232 + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uint16_t uhMask; + 842 .loc 1 500 3 view .LVU233 + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uint32_t tickstart; + 843 .loc 1 501 3 view .LVU234 + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 844 .loc 1 502 3 view .LVU235 + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 845 .loc 1 505 3 view .LVU236 + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 846 .loc 1 505 12 is_stmt 0 view .LVU237 + 847 0008 D0F88030 ldr r3, [r0, #128] + 848 .LVL76: + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 849 .loc 1 505 6 view .LVU238 + 850 000c 202B cmp r3, #32 + 851 000e 40F0A380 bne .L63 + 852 0012 0446 mov r4, r0 + 853 0014 0F46 mov r7, r1 + 854 0016 9146 mov r9, r2 + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 855 .loc 1 507 5 is_stmt 1 view .LVU239 + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 856 .loc 1 507 8 is_stmt 0 view .LVU240 + 857 0018 002A cmp r2, #0 + 858 001a 18BF it ne + 859 001c 0029 cmpne r1, #0 + 860 001e 01D1 bne .L68 + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 861 .loc 1 509 15 view .LVU241 + ARM GAS /tmp/cc5ct5Ve.s page 53 + + + 862 0020 0120 movs r0, #1 + 863 .LVL77: + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 864 .loc 1 509 15 view .LVU242 + 865 0022 9AE0 b .L46 + 866 .LVL78: + 867 .L68: + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 868 .loc 1 512 5 is_stmt 1 view .LVU243 + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_BUSY_RX; + 869 .loc 1 512 22 is_stmt 0 view .LVU244 + 870 0024 0023 movs r3, #0 + 871 0026 C0F88430 str r3, [r0, #132] + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + 872 .loc 1 513 5 is_stmt 1 view .LVU245 + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + 873 .loc 1 513 20 is_stmt 0 view .LVU246 + 874 002a 2222 movs r2, #34 + 875 .LVL79: + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + 876 .loc 1 513 20 view .LVU247 + 877 002c C0F88020 str r2, [r0, #128] + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; + 878 .loc 1 514 5 is_stmt 1 view .LVU248 + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; + 879 .loc 1 514 26 is_stmt 0 view .LVU249 + 880 0030 0122 movs r2, #1 + 881 0032 0266 str r2, [r0, #96] + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 882 .loc 1 515 5 is_stmt 1 view .LVU250 + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 883 .loc 1 515 24 is_stmt 0 view .LVU251 + 884 0034 4366 str r3, [r0, #100] + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 885 .loc 1 518 5 is_stmt 1 view .LVU252 + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 886 .loc 1 518 17 is_stmt 0 view .LVU253 + 887 0036 FFF7FEFF bl HAL_GetTick + 888 .LVL80: + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 889 .loc 1 518 17 view .LVU254 + 890 003a 8046 mov r8, r0 + 891 .LVL81: + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxXferCount = Size; + 892 .loc 1 520 5 is_stmt 1 view .LVU255 + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxXferCount = Size; + 893 .loc 1 520 24 is_stmt 0 view .LVU256 + 894 003c A4F85890 strh r9, [r4, #88] @ movhi + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 895 .loc 1 521 5 is_stmt 1 view .LVU257 + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 896 .loc 1 521 24 is_stmt 0 view .LVU258 + 897 0040 A4F85A90 strh r9, [r4, #90] @ movhi + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uhMask = huart->Mask; + 898 .loc 1 524 5 is_stmt 1 view .LVU259 + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uhMask = huart->Mask; + 899 .loc 1 524 5 view .LVU260 + ARM GAS /tmp/cc5ct5Ve.s page 54 + + + 900 0044 A368 ldr r3, [r4, #8] + 901 0046 B3F5805F cmp r3, #4096 + 902 004a 06D0 beq .L69 + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uhMask = huart->Mask; + 903 .loc 1 524 5 discriminator 2 view .LVU261 + 904 004c A3B9 cbnz r3, .L50 + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uhMask = huart->Mask; + 905 .loc 1 524 5 discriminator 5 view .LVU262 + 906 004e 2269 ldr r2, [r4, #16] + 907 0050 72B9 cbnz r2, .L51 + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uhMask = huart->Mask; + 908 .loc 1 524 5 discriminator 7 view .LVU263 + 909 0052 FF22 movs r2, #255 + 910 0054 A4F85C20 strh r2, [r4, #92] @ movhi + 911 0058 14E0 b .L49 + 912 .L69: + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uhMask = huart->Mask; + 913 .loc 1 524 5 discriminator 1 view .LVU264 + 914 005a 2269 ldr r2, [r4, #16] + 915 005c 22B9 cbnz r2, .L48 + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uhMask = huart->Mask; + 916 .loc 1 524 5 discriminator 3 view .LVU265 + 917 005e 40F2FF12 movw r2, #511 + 918 0062 A4F85C20 strh r2, [r4, #92] @ movhi + 919 0066 0DE0 b .L49 + 920 .L48: + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uhMask = huart->Mask; + 921 .loc 1 524 5 discriminator 4 view .LVU266 + 922 0068 FF22 movs r2, #255 + 923 006a A4F85C20 strh r2, [r4, #92] @ movhi + 924 006e 09E0 b .L49 + 925 .L51: + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uhMask = huart->Mask; + 926 .loc 1 524 5 discriminator 8 view .LVU267 + 927 0070 7F22 movs r2, #127 + 928 0072 A4F85C20 strh r2, [r4, #92] @ movhi + 929 0076 05E0 b .L49 + 930 .L50: + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uhMask = huart->Mask; + 931 .loc 1 524 5 discriminator 6 view .LVU268 + 932 0078 B3F1805F cmp r3, #268435456 + 933 007c 0CD0 beq .L70 + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uhMask = huart->Mask; + 934 .loc 1 524 5 discriminator 10 view .LVU269 + 935 007e 0022 movs r2, #0 + 936 0080 A4F85C20 strh r2, [r4, #92] @ movhi + 937 .L49: + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uhMask = huart->Mask; + 938 .loc 1 524 5 discriminator 13 view .LVU270 + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 939 .loc 1 525 5 view .LVU271 + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 940 .loc 1 525 12 is_stmt 0 view .LVU272 + 941 0084 B4F85C90 ldrh r9, [r4, #92] + 942 .LVL82: + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 943 .loc 1 528 5 is_stmt 1 view .LVU273 + ARM GAS /tmp/cc5ct5Ve.s page 55 + + + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 944 .loc 1 528 8 is_stmt 0 view .LVU274 + 945 0088 B3F5805F cmp r3, #4096 + 946 008c 0ED0 beq .L71 + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 947 .loc 1 536 19 view .LVU275 + 948 008e 4FF0000A mov r10, #0 + 949 .LVL83: + 950 .L54: + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 951 .loc 1 540 5 is_stmt 1 view .LVU276 + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 952 .loc 1 540 12 is_stmt 0 view .LVU277 + 953 0092 0023 movs r3, #0 + 954 0094 2B80 strh r3, [r5] @ movhi + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 955 .loc 1 543 5 is_stmt 1 view .LVU278 + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 956 .loc 1 543 11 is_stmt 0 view .LVU279 + 957 0096 2AE0 b .L55 + 958 .LVL84: + 959 .L70: + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uhMask = huart->Mask; + 960 .loc 1 524 5 is_stmt 1 discriminator 9 view .LVU280 + 961 0098 2269 ldr r2, [r4, #16] + 962 009a 1AB9 cbnz r2, .L53 + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uhMask = huart->Mask; + 963 .loc 1 524 5 discriminator 11 view .LVU281 + 964 009c 7F22 movs r2, #127 + 965 009e A4F85C20 strh r2, [r4, #92] @ movhi + 966 00a2 EFE7 b .L49 + 967 .L53: + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** uhMask = huart->Mask; + 968 .loc 1 524 5 discriminator 12 view .LVU282 + 969 00a4 3F22 movs r2, #63 + 970 00a6 A4F85C20 strh r2, [r4, #92] @ movhi + 971 00aa EBE7 b .L49 + 972 .LVL85: + 973 .L71: + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 974 .loc 1 528 71 is_stmt 0 discriminator 1 view .LVU283 + 975 00ac 2369 ldr r3, [r4, #16] + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 976 .loc 1 528 56 discriminator 1 view .LVU284 + 977 00ae 13B1 cbz r3, .L66 + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 978 .loc 1 536 19 view .LVU285 + 979 00b0 4FF0000A mov r10, #0 + 980 00b4 EDE7 b .L54 + 981 .L66: + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 982 .loc 1 531 19 view .LVU286 + 983 00b6 BA46 mov r10, r7 + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** pdata16bits = (uint16_t *) pData; + 984 .loc 1 530 19 view .LVU287 + 985 00b8 0027 movs r7, #0 + 986 .LVL86: + ARM GAS /tmp/cc5ct5Ve.s page 56 + + + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** pdata16bits = (uint16_t *) pData; + 987 .loc 1 530 19 view .LVU288 + 988 00ba EAE7 b .L54 + 989 .LVL87: + 990 .L74: + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_READY; + 991 .loc 1 555 11 is_stmt 1 view .LVU289 + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxState = HAL_UART_STATE_READY; + 992 .loc 1 555 30 is_stmt 0 view .LVU290 + 993 00bc 0223 movs r3, #2 + 994 00be 6366 str r3, [r4, #100] + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 995 .loc 1 556 11 is_stmt 1 view .LVU291 + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 996 .loc 1 556 26 is_stmt 0 view .LVU292 + 997 00c0 2023 movs r3, #32 + 998 00c2 C4F88030 str r3, [r4, #128] + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 999 .loc 1 558 11 is_stmt 1 view .LVU293 + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1000 .loc 1 558 18 is_stmt 0 view .LVU294 + 1001 00c6 0020 movs r0, #0 + 1002 00c8 47E0 b .L46 + 1003 .L75: + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** pdata16bits++; + 1004 .loc 1 567 11 is_stmt 1 view .LVU295 + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** pdata16bits++; + 1005 .loc 1 567 52 is_stmt 0 view .LVU296 + 1006 00ca 5B6A ldr r3, [r3, #36] + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** pdata16bits++; + 1007 .loc 1 567 26 view .LVU297 + 1008 00cc 09EA0303 and r3, r9, r3 + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** pdata16bits++; + 1009 .loc 1 567 24 view .LVU298 + 1010 00d0 2AF8023B strh r3, [r10], #2 @ movhi + 1011 .LVL88: + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1012 .loc 1 568 11 is_stmt 1 view .LVU299 + 1013 .L59: + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxXferCount--; + 1014 .loc 1 576 9 view .LVU300 + 1015 00d4 2B88 ldrh r3, [r5] + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxXferCount--; + 1016 .loc 1 576 16 is_stmt 0 view .LVU301 + 1017 00d6 0133 adds r3, r3, #1 + 1018 00d8 2B80 strh r3, [r5] @ movhi + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1019 .loc 1 577 9 is_stmt 1 view .LVU302 + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1020 .loc 1 577 14 is_stmt 0 view .LVU303 + 1021 00da B4F85A30 ldrh r3, [r4, #90] + 1022 00de 9BB2 uxth r3, r3 + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1023 .loc 1 577 27 view .LVU304 + 1024 00e0 013B subs r3, r3, #1 + 1025 00e2 9BB2 uxth r3, r3 + 1026 00e4 A4F85A30 strh r3, [r4, #90] @ movhi + ARM GAS /tmp/cc5ct5Ve.s page 57 + + + 1027 .L57: + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1028 .loc 1 581 7 is_stmt 1 view .LVU305 + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1029 .loc 1 581 10 is_stmt 0 view .LVU306 + 1030 00e8 B6F1FF3F cmp r6, #-1 + 1031 00ec 1BD1 bne .L72 + 1032 .L55: + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1033 .loc 1 543 31 is_stmt 1 view .LVU307 + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1034 .loc 1 543 17 is_stmt 0 view .LVU308 + 1035 00ee B4F85A20 ldrh r2, [r4, #90] + 1036 00f2 92B2 uxth r2, r2 + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1037 .loc 1 543 31 view .LVU309 + 1038 00f4 22B3 cbz r2, .L73 + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1039 .loc 1 546 7 is_stmt 1 view .LVU310 + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1040 .loc 1 546 11 is_stmt 0 view .LVU311 + 1041 00f6 2368 ldr r3, [r4] + 1042 00f8 DA69 ldr r2, [r3, #28] + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1043 .loc 1 546 10 view .LVU312 + 1044 00fa 12F0100F tst r2, #16 + 1045 00fe 04D0 beq .L56 + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1046 .loc 1 549 9 is_stmt 1 view .LVU313 + 1047 0100 1022 movs r2, #16 + 1048 0102 1A62 str r2, [r3, #32] + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1049 .loc 1 553 9 view .LVU314 + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1050 .loc 1 553 13 is_stmt 0 view .LVU315 + 1051 0104 2B88 ldrh r3, [r5] + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1052 .loc 1 553 12 view .LVU316 + 1053 0106 002B cmp r3, #0 + 1054 0108 D8D1 bne .L74 + 1055 .L56: + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1056 .loc 1 563 7 is_stmt 1 view .LVU317 + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1057 .loc 1 563 11 is_stmt 0 view .LVU318 + 1058 010a 2368 ldr r3, [r4] + 1059 010c DA69 ldr r2, [r3, #28] + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1060 .loc 1 563 10 view .LVU319 + 1061 010e 12F0200F tst r2, #32 + 1062 0112 E9D0 beq .L57 + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1063 .loc 1 565 9 is_stmt 1 view .LVU320 + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1064 .loc 1 565 12 is_stmt 0 view .LVU321 + 1065 0114 002F cmp r7, #0 + 1066 0116 D8D0 beq .L75 + ARM GAS /tmp/cc5ct5Ve.s page 58 + + + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** pdata8bits++; + 1067 .loc 1 572 11 is_stmt 1 view .LVU322 + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** pdata8bits++; + 1068 .loc 1 572 50 is_stmt 0 view .LVU323 + 1069 0118 5A6A ldr r2, [r3, #36] + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** pdata8bits++; + 1070 .loc 1 572 58 view .LVU324 + 1071 011a 5FFA89F3 uxtb r3, r9 + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** pdata8bits++; + 1072 .loc 1 572 25 view .LVU325 + 1073 011e 1340 ands r3, r3, r2 + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** pdata8bits++; + 1074 .loc 1 572 23 view .LVU326 + 1075 0120 07F8013B strb r3, [r7], #1 + 1076 .LVL89: + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1077 .loc 1 573 11 is_stmt 1 view .LVU327 + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1078 .loc 1 573 11 is_stmt 0 view .LVU328 + 1079 0124 D6E7 b .L59 + 1080 .L72: + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1081 .loc 1 583 9 is_stmt 1 view .LVU329 + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1082 .loc 1 583 15 is_stmt 0 view .LVU330 + 1083 0126 FFF7FEFF bl HAL_GetTick + 1084 .LVL90: + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1085 .loc 1 583 29 discriminator 1 view .LVU331 + 1086 012a A0EB0800 sub r0, r0, r8 + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1087 .loc 1 583 12 discriminator 1 view .LVU332 + 1088 012e B042 cmp r0, r6 + 1089 0130 01D8 bhi .L61 + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1090 .loc 1 583 53 discriminator 1 view .LVU333 + 1091 0132 002E cmp r6, #0 + 1092 0134 DBD1 bne .L55 + 1093 .L61: + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1094 .loc 1 585 11 is_stmt 1 view .LVU334 + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1095 .loc 1 585 26 is_stmt 0 view .LVU335 + 1096 0136 2023 movs r3, #32 + 1097 0138 C4F88030 str r3, [r4, #128] + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1098 .loc 1 587 11 is_stmt 1 view .LVU336 + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1099 .loc 1 587 18 is_stmt 0 view .LVU337 + 1100 013c 0320 movs r0, #3 + 1101 013e 0CE0 b .L46 + 1102 .L73: + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* At end of Rx process, restore huart->RxState to Ready */ + 1103 .loc 1 593 5 is_stmt 1 view .LVU338 + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* At end of Rx process, restore huart->RxState to Ready */ + 1104 .loc 1 593 19 is_stmt 0 view .LVU339 + 1105 0140 B4F85830 ldrh r3, [r4, #88] + ARM GAS /tmp/cc5ct5Ve.s page 59 + + + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* At end of Rx process, restore huart->RxState to Ready */ + 1106 .loc 1 593 39 view .LVU340 + 1107 0144 B4F85A20 ldrh r2, [r4, #90] + 1108 0148 92B2 uxth r2, r2 + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* At end of Rx process, restore huart->RxState to Ready */ + 1109 .loc 1 593 32 view .LVU341 + 1110 014a 9B1A subs r3, r3, r2 + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* At end of Rx process, restore huart->RxState to Ready */ + 1111 .loc 1 593 12 view .LVU342 + 1112 014c 2B80 strh r3, [r5] @ movhi + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1113 .loc 1 595 5 is_stmt 1 view .LVU343 + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1114 .loc 1 595 20 is_stmt 0 view .LVU344 + 1115 014e 2023 movs r3, #32 + 1116 0150 C4F88030 str r3, [r4, #128] + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1117 .loc 1 597 5 is_stmt 1 view .LVU345 + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1118 .loc 1 597 12 is_stmt 0 view .LVU346 + 1119 0154 0020 movs r0, #0 + 1120 0156 00E0 b .L46 + 1121 .LVL91: + 1122 .L63: + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1123 .loc 1 601 12 view .LVU347 + 1124 0158 0220 movs r0, #2 + 1125 .LVL92: + 1126 .L46: + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1127 .loc 1 603 1 view .LVU348 + 1128 015a BDE8F087 pop {r4, r5, r6, r7, r8, r9, r10, pc} + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1129 .loc 1 603 1 view .LVU349 + 1130 .cfi_endproc + 1131 .LFE148: + 1133 .section .text.HAL_UARTEx_ReceiveToIdle_IT,"ax",%progbits + 1134 .align 1 + 1135 .global HAL_UARTEx_ReceiveToIdle_IT + 1136 .syntax unified + 1137 .thumb + 1138 .thumb_func + 1140 HAL_UARTEx_ReceiveToIdle_IT: + 1141 .LVL93: + 1142 .LFB149: + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1143 .loc 1 620 1 is_stmt 1 view -0 + 1144 .cfi_startproc + 1145 @ args = 0, pretend = 0, frame = 0 + 1146 @ frame_needed = 0, uses_anonymous_args = 0 + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1147 .loc 1 621 3 view .LVU351 + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1148 .loc 1 624 3 view .LVU352 + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1149 .loc 1 624 12 is_stmt 0 view .LVU353 + 1150 0000 D0F88030 ldr r3, [r0, #128] + ARM GAS /tmp/cc5ct5Ve.s page 60 + + + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1151 .loc 1 624 6 view .LVU354 + 1152 0004 202B cmp r3, #32 + 1153 0006 20D1 bne .L80 + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1154 .loc 1 620 1 view .LVU355 + 1155 0008 10B5 push {r4, lr} + 1156 .LCFI11: + 1157 .cfi_def_cfa_offset 8 + 1158 .cfi_offset 4, -8 + 1159 .cfi_offset 14, -4 + 1160 000a 0446 mov r4, r0 + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1161 .loc 1 626 5 is_stmt 1 view .LVU356 + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1162 .loc 1 626 8 is_stmt 0 view .LVU357 + 1163 000c 002A cmp r2, #0 + 1164 000e 18BF it ne + 1165 0010 0029 cmpne r1, #0 + 1166 0012 01D1 bne .L87 + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1167 .loc 1 628 14 view .LVU358 + 1168 0014 0120 movs r0, #1 + 1169 .LVL94: + 1170 .L77: + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1171 .loc 1 657 1 view .LVU359 + 1172 0016 10BD pop {r4, pc} + 1173 .LVL95: + 1174 .L87: + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; + 1175 .loc 1 632 5 is_stmt 1 view .LVU360 + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; + 1176 .loc 1 632 26 is_stmt 0 view .LVU361 + 1177 0018 0123 movs r3, #1 + 1178 001a 0366 str r3, [r0, #96] + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1179 .loc 1 633 5 is_stmt 1 view .LVU362 + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1180 .loc 1 633 24 is_stmt 0 view .LVU363 + 1181 001c 0023 movs r3, #0 + 1182 001e 4366 str r3, [r0, #100] + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1183 .loc 1 635 5 is_stmt 1 view .LVU364 + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1184 .loc 1 635 11 is_stmt 0 view .LVU365 + 1185 0020 FFF7FEFF bl UART_Start_Receive_IT + 1186 .LVL96: + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1187 .loc 1 637 5 is_stmt 1 view .LVU366 + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1188 .loc 1 637 14 is_stmt 0 view .LVU367 + 1189 0024 236E ldr r3, [r4, #96] + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1190 .loc 1 637 8 view .LVU368 + 1191 0026 012B cmp r3, #1 + 1192 0028 01D0 beq .L88 + ARM GAS /tmp/cc5ct5Ve.s page 61 + + + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1193 .loc 1 648 14 view .LVU369 + 1194 002a 0120 movs r0, #1 + 1195 .LVL97: + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1196 .loc 1 651 5 is_stmt 1 view .LVU370 + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1197 .loc 1 651 12 is_stmt 0 view .LVU371 + 1198 002c F3E7 b .L77 + 1199 .LVL98: + 1200 .L88: + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 1201 .loc 1 639 7 is_stmt 1 view .LVU372 + 1202 002e 2368 ldr r3, [r4] + 1203 0030 1022 movs r2, #16 + 1204 0032 1A62 str r2, [r3, #32] + 1205 .L79: + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1206 .loc 1 640 7 discriminator 1 view .LVU373 + 1207 .LBB52: + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1208 .loc 1 640 7 discriminator 1 view .LVU374 + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1209 .loc 1 640 7 discriminator 1 view .LVU375 + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1210 .loc 1 640 7 discriminator 1 view .LVU376 + 1211 0034 2268 ldr r2, [r4] + 1212 .LVL99: + 1213 .LBB53: + 1214 .LBI53: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1215 .loc 2 1068 31 view .LVU377 + 1216 .LBB54: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1217 .loc 2 1070 5 view .LVU378 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1218 .loc 2 1072 4 view .LVU379 + 1219 .syntax unified + 1220 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1221 0036 52E8003F ldrex r3, [r2] + 1222 @ 0 "" 2 + 1223 .LVL100: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1224 .loc 2 1073 4 view .LVU380 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1225 .loc 2 1073 4 is_stmt 0 view .LVU381 + 1226 .thumb + 1227 .syntax unified + 1228 .LBE54: + 1229 .LBE53: + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1230 .loc 1 640 7 discriminator 1 view .LVU382 + 1231 003a 43F01003 orr r3, r3, #16 + 1232 .LVL101: + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1233 .loc 1 640 7 is_stmt 1 discriminator 1 view .LVU383 + 1234 .LBB55: + ARM GAS /tmp/cc5ct5Ve.s page 62 + + + 1235 .LBI55: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1236 .loc 2 1119 31 view .LVU384 + 1237 .LBB56: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1238 .loc 2 1121 4 view .LVU385 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1239 .loc 2 1123 4 view .LVU386 + 1240 .syntax unified + 1241 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1242 003e 42E80031 strex r1, r3, [r2] + 1243 @ 0 "" 2 + 1244 .LVL102: + 1245 .loc 2 1124 4 view .LVU387 + 1246 .loc 2 1124 4 is_stmt 0 view .LVU388 + 1247 .thumb + 1248 .syntax unified + 1249 .LBE56: + 1250 .LBE55: + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1251 .loc 1 640 7 discriminator 1 view .LVU389 + 1252 0042 0029 cmp r1, #0 + 1253 0044 F6D1 bne .L79 + 1254 .LBE52: + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1255 .loc 1 621 21 view .LVU390 + 1256 0046 0020 movs r0, #0 + 1257 .LBB57: + 1258 0048 E5E7 b .L77 + 1259 .LVL103: + 1260 .L80: + 1261 .LCFI12: + 1262 .cfi_def_cfa_offset 0 + 1263 .cfi_restore 4 + 1264 .cfi_restore 14 + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1265 .loc 1 621 21 view .LVU391 + 1266 .LBE57: + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1267 .loc 1 655 12 view .LVU392 + 1268 004a 0220 movs r0, #2 + 1269 .LVL104: + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1270 .loc 1 657 1 view .LVU393 + 1271 004c 7047 bx lr + 1272 .cfi_endproc + 1273 .LFE149: + 1275 .section .text.HAL_UARTEx_ReceiveToIdle_DMA,"ax",%progbits + 1276 .align 1 + 1277 .global HAL_UARTEx_ReceiveToIdle_DMA + 1278 .syntax unified + 1279 .thumb + 1280 .thumb_func + 1282 HAL_UARTEx_ReceiveToIdle_DMA: + 1283 .LVL105: + 1284 .LFB150: + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_StatusTypeDef status; + ARM GAS /tmp/cc5ct5Ve.s page 63 + + + 1285 .loc 1 677 1 is_stmt 1 view -0 + 1286 .cfi_startproc + 1287 @ args = 0, pretend = 0, frame = 0 + 1288 @ frame_needed = 0, uses_anonymous_args = 0 + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1289 .loc 1 678 3 view .LVU395 + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1290 .loc 1 681 3 view .LVU396 + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1291 .loc 1 681 12 is_stmt 0 view .LVU397 + 1292 0000 D0F88030 ldr r3, [r0, #128] + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1293 .loc 1 681 6 view .LVU398 + 1294 0004 202B cmp r3, #32 + 1295 0006 21D1 bne .L93 + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** HAL_StatusTypeDef status; + 1296 .loc 1 677 1 view .LVU399 + 1297 0008 10B5 push {r4, lr} + 1298 .LCFI13: + 1299 .cfi_def_cfa_offset 8 + 1300 .cfi_offset 4, -8 + 1301 .cfi_offset 14, -4 + 1302 000a 0446 mov r4, r0 + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1303 .loc 1 683 5 is_stmt 1 view .LVU400 + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1304 .loc 1 683 8 is_stmt 0 view .LVU401 + 1305 000c 002A cmp r2, #0 + 1306 000e 18BF it ne + 1307 0010 0029 cmpne r1, #0 + 1308 0012 01D1 bne .L100 + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1309 .loc 1 685 14 view .LVU402 + 1310 0014 0120 movs r0, #1 + 1311 .LVL106: + 1312 .L90: + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1313 .loc 1 718 1 view .LVU403 + 1314 0016 10BD pop {r4, pc} + 1315 .LVL107: + 1316 .L100: + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; + 1317 .loc 1 689 5 is_stmt 1 view .LVU404 + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** huart->RxEventType = HAL_UART_RXEVENT_TC; + 1318 .loc 1 689 26 is_stmt 0 view .LVU405 + 1319 0018 0123 movs r3, #1 + 1320 001a 0366 str r3, [r0, #96] + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1321 .loc 1 690 5 is_stmt 1 view .LVU406 + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1322 .loc 1 690 24 is_stmt 0 view .LVU407 + 1323 001c 0023 movs r3, #0 + 1324 001e 4366 str r3, [r0, #100] + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1325 .loc 1 692 5 is_stmt 1 view .LVU408 + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1326 .loc 1 692 15 is_stmt 0 view .LVU409 + ARM GAS /tmp/cc5ct5Ve.s page 64 + + + 1327 0020 FFF7FEFF bl UART_Start_Receive_DMA + 1328 .LVL108: + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1329 .loc 1 695 5 is_stmt 1 view .LVU410 + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1330 .loc 1 695 8 is_stmt 0 view .LVU411 + 1331 0024 0028 cmp r0, #0 + 1332 0026 F6D1 bne .L90 + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1333 .loc 1 697 7 is_stmt 1 view .LVU412 + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1334 .loc 1 697 16 is_stmt 0 view .LVU413 + 1335 0028 236E ldr r3, [r4, #96] + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** { + 1336 .loc 1 697 10 view .LVU414 + 1337 002a 012B cmp r3, #1 + 1338 002c 01D0 beq .L101 + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1339 .loc 1 708 16 view .LVU415 + 1340 002e 0120 movs r0, #1 + 1341 .LVL109: + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1342 .loc 1 712 5 is_stmt 1 view .LVU416 + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1343 .loc 1 712 12 is_stmt 0 view .LVU417 + 1344 0030 F1E7 b .L90 + 1345 .LVL110: + 1346 .L101: + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 1347 .loc 1 699 9 is_stmt 1 view .LVU418 + 1348 0032 2368 ldr r3, [r4] + 1349 0034 1022 movs r2, #16 + 1350 0036 1A62 str r2, [r3, #32] + 1351 .L92: + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1352 .loc 1 700 9 discriminator 1 view .LVU419 + 1353 .LBB58: + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1354 .loc 1 700 9 discriminator 1 view .LVU420 + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1355 .loc 1 700 9 discriminator 1 view .LVU421 + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1356 .loc 1 700 9 discriminator 1 view .LVU422 + 1357 0038 2268 ldr r2, [r4] + 1358 .LVL111: + 1359 .LBB59: + 1360 .LBI59: +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1361 .loc 2 1068 31 view .LVU423 + 1362 .LBB60: +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1363 .loc 2 1070 5 view .LVU424 +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1364 .loc 2 1072 4 view .LVU425 + 1365 .syntax unified + 1366 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1367 003a 52E8003F ldrex r3, [r2] + ARM GAS /tmp/cc5ct5Ve.s page 65 + + + 1368 @ 0 "" 2 + 1369 .LVL112: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1370 .loc 2 1073 4 view .LVU426 +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1371 .loc 2 1073 4 is_stmt 0 view .LVU427 + 1372 .thumb + 1373 .syntax unified + 1374 .LBE60: + 1375 .LBE59: + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1376 .loc 1 700 9 discriminator 1 view .LVU428 + 1377 003e 43F01003 orr r3, r3, #16 + 1378 .LVL113: + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1379 .loc 1 700 9 is_stmt 1 discriminator 1 view .LVU429 + 1380 .LBB61: + 1381 .LBI61: +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1382 .loc 2 1119 31 view .LVU430 + 1383 .LBB62: +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1384 .loc 2 1121 4 view .LVU431 +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1385 .loc 2 1123 4 view .LVU432 + 1386 .syntax unified + 1387 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1388 0042 42E80031 strex r1, r3, [r2] + 1389 @ 0 "" 2 + 1390 .LVL114: + 1391 .loc 2 1124 4 view .LVU433 + 1392 .loc 2 1124 4 is_stmt 0 view .LVU434 + 1393 .thumb + 1394 .syntax unified + 1395 .LBE62: + 1396 .LBE61: + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1397 .loc 1 700 9 discriminator 1 view .LVU435 + 1398 0046 0029 cmp r1, #0 + 1399 0048 F6D1 bne .L92 + 1400 004a E4E7 b .L90 + 1401 .LVL115: + 1402 .L93: + 1403 .LCFI14: + 1404 .cfi_def_cfa_offset 0 + 1405 .cfi_restore 4 + 1406 .cfi_restore 14 + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1407 .loc 1 700 9 discriminator 1 view .LVU436 + 1408 .LBE58: + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1409 .loc 1 716 12 view .LVU437 + 1410 004c 0220 movs r0, #2 + 1411 .LVL116: + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1412 .loc 1 718 1 view .LVU438 + 1413 004e 7047 bx lr + ARM GAS /tmp/cc5ct5Ve.s page 66 + + + 1414 .cfi_endproc + 1415 .LFE150: + 1417 .section .text.HAL_UARTEx_GetRxEventType,"ax",%progbits + 1418 .align 1 + 1419 .global HAL_UARTEx_GetRxEventType + 1420 .syntax unified + 1421 .thumb + 1422 .thumb_func + 1424 HAL_UARTEx_GetRxEventType: + 1425 .LVL117: + 1426 .LFB151: + 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** /* Return Rx Event type value, as stored in UART handle */ + 1427 .loc 1 745 1 is_stmt 1 view -0 + 1428 .cfi_startproc + 1429 @ args = 0, pretend = 0, frame = 0 + 1430 @ frame_needed = 0, uses_anonymous_args = 0 + 1431 @ link register save eliminated. + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1432 .loc 1 747 3 view .LVU440 + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** } + 1433 .loc 1 747 16 is_stmt 0 view .LVU441 + 1434 0000 406E ldr r0, [r0, #100] + 1435 .LVL118: + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c **** + 1436 .loc 1 748 1 view .LVU442 + 1437 0002 7047 bx lr + 1438 .cfi_endproc + 1439 .LFE151: + 1441 .text + 1442 .Letext0: + 1443 .file 3 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 1444 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 1445 .file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + 1446 .file 6 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 1447 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h" + 1448 .file 8 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h" + 1449 .file 9 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h" + 1450 .file 10 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h" + ARM GAS /tmp/cc5ct5Ve.s page 67 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_hal_uart_ex.c + /tmp/cc5ct5Ve.s:20 .text.UARTEx_Wakeup_AddressConfig:00000000 $t + /tmp/cc5ct5Ve.s:25 .text.UARTEx_Wakeup_AddressConfig:00000000 UARTEx_Wakeup_AddressConfig + /tmp/cc5ct5Ve.s:64 .text.HAL_RS485Ex_Init:00000000 $t + /tmp/cc5ct5Ve.s:70 .text.HAL_RS485Ex_Init:00000000 HAL_RS485Ex_Init + /tmp/cc5ct5Ve.s:207 .text.HAL_UARTEx_EnableClockStopMode:00000000 $t + /tmp/cc5ct5Ve.s:213 .text.HAL_UARTEx_EnableClockStopMode:00000000 HAL_UARTEx_EnableClockStopMode + /tmp/cc5ct5Ve.s:312 .text.HAL_UARTEx_DisableClockStopMode:00000000 $t + /tmp/cc5ct5Ve.s:318 .text.HAL_UARTEx_DisableClockStopMode:00000000 HAL_UARTEx_DisableClockStopMode + /tmp/cc5ct5Ve.s:416 .text.HAL_MultiProcessorEx_AddressLength_Set:00000000 $t + /tmp/cc5ct5Ve.s:422 .text.HAL_MultiProcessorEx_AddressLength_Set:00000000 HAL_MultiProcessorEx_AddressLength_Set + /tmp/cc5ct5Ve.s:486 .text.HAL_UARTEx_StopModeWakeUpSourceConfig:00000000 $t + /tmp/cc5ct5Ve.s:492 .text.HAL_UARTEx_StopModeWakeUpSourceConfig:00000000 HAL_UARTEx_StopModeWakeUpSourceConfig + /tmp/cc5ct5Ve.s:618 .text.HAL_UARTEx_EnableStopMode:00000000 $t + /tmp/cc5ct5Ve.s:624 .text.HAL_UARTEx_EnableStopMode:00000000 HAL_UARTEx_EnableStopMode + /tmp/cc5ct5Ve.s:716 .text.HAL_UARTEx_DisableStopMode:00000000 $t + /tmp/cc5ct5Ve.s:722 .text.HAL_UARTEx_DisableStopMode:00000000 HAL_UARTEx_DisableStopMode + /tmp/cc5ct5Ve.s:814 .text.HAL_UARTEx_ReceiveToIdle:00000000 $t + /tmp/cc5ct5Ve.s:820 .text.HAL_UARTEx_ReceiveToIdle:00000000 HAL_UARTEx_ReceiveToIdle + /tmp/cc5ct5Ve.s:1134 .text.HAL_UARTEx_ReceiveToIdle_IT:00000000 $t + /tmp/cc5ct5Ve.s:1140 .text.HAL_UARTEx_ReceiveToIdle_IT:00000000 HAL_UARTEx_ReceiveToIdle_IT + /tmp/cc5ct5Ve.s:1276 .text.HAL_UARTEx_ReceiveToIdle_DMA:00000000 $t + /tmp/cc5ct5Ve.s:1282 .text.HAL_UARTEx_ReceiveToIdle_DMA:00000000 HAL_UARTEx_ReceiveToIdle_DMA + /tmp/cc5ct5Ve.s:1418 .text.HAL_UARTEx_GetRxEventType:00000000 $t + /tmp/cc5ct5Ve.s:1424 .text.HAL_UARTEx_GetRxEventType:00000000 HAL_UARTEx_GetRxEventType + +UNDEFINED SYMBOLS +UART_SetConfig +UART_CheckIdleState +HAL_UART_MspInit +UART_AdvFeatureConfig +HAL_GetTick +UART_WaitOnFlagUntilTimeout +UART_Start_Receive_IT +UART_Start_Receive_DMA diff --git a/build/stm32f7xx_hal_uart_ex.o b/build/stm32f7xx_hal_uart_ex.o new file mode 100644 index 0000000000000000000000000000000000000000..32e4fa312e8134191b8d2be8acf2f6c50c971407 GIT binary patch literal 26092 zcmd^{d3;pW`Tx(IJ2ROqWCBSrEP)}35|&I7b`h1V5M>ETkcen9Boh+J=467=uObTW zRdK0WwbHs&Tl;O@msVQ+YPI^S7F%tt)=FK9OIx9!;L7jwIrq6UcZOi?>-GKX_q(s0 zdEe(b&w0*%?lO~eUd@tP!!VS67^+ysC8f5s=orr|jbb$g@fY0dy2pIqt6ZIporSxz z%viBvWWAkeJ7rDMB4N7y^G>_ird&sOUD)^sus?*h3u-kCCTJt(9ahBy8 zSyjXN}F;zTF!u)itVM`MyntRr`gH1<=ago$h#x1K zR!zAWCU*7sS2Msu%)b^;E4m90!D$WqpE}D+*EtVf#$7u99X^e_Ra@B-qhmV zarpym#As4zGUeF{`YsN(pPt^KE36$OZR3kOgUg2^M_rm@Ap3Rse3DpS5@%! zm#kdPK*r7o4>XrqUT+>dZIfLZwbK>Y{@(73tyT@Zl=YC?(V|(~jY6|S6nVEzLe)6x!fs_djVHUn+X`+xmblaArVFm0zw&gruT_faAYg;}UZ_oF{(}88-Sk7UlguzqWfFfXlPq;3i89y2vv;;xiHOXy zl(N*xNajBiMM#;Ev6=n~m7kF*vqg0K??952qeb-j_tAKPh#CHeP?VJ8Ma=SVgTItY z5p(>{p#~{6BIfx|!2nD-LB#R?BavasQV|3Gn`qo1Vv+wR%y*@T#r}3wBjpqkrz`VY zOx)_~idQ(L!{|Wv8QY*z8K2_R$oL~l>&mF%z|VLB4&52&L+?@MqpU`cYbGV8%9@Yd zTT?F0T7`!4=P>s2i9BbEq*1(L0vpR!==RTM16?(Nt?MeB<^Pfey?R1K$IkXIVeGXN zPt|GX`5Rg8Z%;Zyiwpe!MdKSpT}&!?+xBG&uA zjSN%1Kf#)OP5un#d;5gVx)+=M3mAK+h-=hHHz({Uceb$}PILGH-I*{N>285wp2ocH za#@-)A&k^(L}tJjOdW}0`IjTTuS_~X`6FmApFIxTeiOO->~Y}p|DB>e4l?vO@YPA$ zEdMd+58o0IbNpHKTrXmtpEp&$CK1Og^EnJL-^u1xC{t#!@3hqIEX@c=zE&|({`V+` zMRfc3GW$*ueg3Hw*Nd3pf0ae=6EVxb1C8K|h?wJljoA%~nCJf-x%q}f9PbaK-F*Kg zV!%J1;&~z#DRUKFpKsnjGO(t8T+mnulB#lD(#ZkHU8-sgueGD{!QoG z>Yu=-{jg}i7Tf(-fWCjEourG==|7XMJ`%Cp|9#eXPyS||Z@<5hY4?g4)zixNalSRJ zhWw||c>knVwC8jDMa=heEt-X!3_bdNUrplZHw(8I7_PiDjC6NEk!{qY06F}C<_mZj z>8^&5b{~D_7$#NjHPB@GQcF|s#ECzMYNnP;Pb&XiC}ZlJ466a%{_)5?_2_hc)hzTX z^9xigb-vk)l)1)3u=TZhv-J{fyaHX0{$Ts&&;zn(X1T`Mtnpgg^58I*xyA+b)?(X~ zAS25g$59S189DllA8NEw4(qhvrx_HDT;pzb)@gR)lkCLEdMmR&)sE?p#T;RL%rqgy z7#BIT=TiH*$7>k3#I*Vr#4yYeD1}l%e&8_v2!k=J(WHnvmNhr($8ZKfT*bC^T|K16 z8ZNFeB;_Rv{QA zX?EH>T-D5)h6#C;hkQQ&C_>;~<%$qQI1EJts5cc8Z zUkIwO6jCK^`B5v0CM}0H6}hJ%Osa&ySv4M^U=4(sI4MU^s;CGb_o0?Y8uhLy&c_?S zLG_IFj;2`#buFxo>U6tl*1M|MG#jCfAXrVa-qpyac^!(EsMJlf-qpsYnPZ{@5Ui%@ zv6|*8C@w}g3I=K>oLkMZ$(6DhisumXEP`&9IW*x1+sA;#KD454mcPK{&j`9%_Tpp@ zg4Ha#3HebeiFC90P)09;ZkBwUj6=}PG6N@N2+}OCCp1d|N6c;`K4MNo^Vh)ID9x~& zWw)`A&B7~l7{O|m-9|l|zJ3D5j}XSpM=Kh8 zjMAG6wZvc(G#t7{W2EReb=Ne_~Ge$7wD9o@lg#1sa{MgWo%@QaUQ~3eRjZX}{ zAoW6VI>KbOCs%~YQ;~!xm?A9MSmRt)c!#6HoNk<5U&QLW!>D9^uY;p+ArxoAB7k7^ z;~xx@CI2&GUPI9Rm<5I6M-GAki^t(i_v0Rze1xF;(F?C`1gjspNErO!wULQ*KaNBE z7zEvqWjF~U=zgrhNfiQ)vBsMi4#xIjs`1nayW6%K6|6=pLNh{AHJ-AnaW`Ukmpn{0 zXaQ%s8rxy=a|B(D-{E8j!f@3LPYgA6ng7?6w$7S&t3Sb|P3S<`!d}wPN;LbMGQUFH3L3;0*+8R9tM0icwf=G7%=% z!Z`=S6keWqQ3)dxYl%40SYa-#EIQI?Fv^a^aPVXtJb2Jhle=Nbbsc4$$$@sNqpX~` zW$!5t10`-_Cqz+$izS~ zDjYfRofyaFjeff^DvU+UU_bnPgrGb1C|FrzbCK1l$72;a79p`y^>~9tGo0y8ZH7q$ zg6`CdadIJo)v0<&@}mI3KqB3#w<7)~1l_4m;N%wwx>H}l$?p+xj5V%hLj{MaMhm8h z)u%zDmetseB<~?4Rb!S_jd@r*=O7GI4OmQsGhK}pFgX!HS7Q@SHX;mH4J6XlxB>Ck zBIs&7hLcASbTwYY$!`#FOf^1b-(4SH896lnib#XkrfK>*eEmGuVhkqx2!v^maDBRd zF*|z$Bm8d`_R$K%$%QoO#0F3b=g=Fk5YtZwuV>iQ1+B;BRw5}ug@S$%ZzrDu%Zd)<8|B#z#-o+#v}#U2*|SPFBdSgbDoTNWyKd;<-z>0)6igQtX|T*2@N+* zT0-}#6l%KE)u}6SHho=oK-VPbY(`8DXB%N&Bq!mN!GXDjaIWTb>)b~MMGqt#v^P{e zfr*B<$+1hrHm4mLMY|=JSm!>nUi84Q$7pEbp3oNp)kG9pT7pgt)kG|_v;^HAt|*9- z!*agDcCHf``m(kyp34e57iY9xbVIGMoh8z8-H_ngHD&+Y{mS9GA;Gmo$6Yrhx-5cN zhJfZEW+1p!`8LvO1Xfy(O3+d^+A3x6?o!`{tGH)_3QHNYG~!P$aZ9H%W~q!?Bxgu! z2xoVnfM|>;AIZMq=sMhCHQU#8H=Urn38^$exBr{nP4~|3wu_!rOIXSA&AU71TDm*# zI@T$iOZGv>E>)%n&2%{@gZjLD8)-FanPa}OL+RL1j;@*mg??a*cd9ieEM?5n&|`ul z$cS4yl`%`}G1sz8m99uuv>4I^M>sl{INH(@e1{4xv09(j6LkCU zyBx`JSk6`u*B}^b6>%eivy&|$7iC34QDp5vieV1+8XAzoqwIbJ7^St^4H zOPMewpw-9!3w3d!CY;`+Om)7;QA3tKk38Et_mLY#4>%7O(_6R8N?LyF(4{jPV$v}IGOkfX%$F=mc9{-y z3FE{;frv5$XEv0X8qs!voY9DpgQMOW-tpb zMN9{Kx@XO_HBSl<95dI@7M3zz0D}rkIqZD=|E}VAnBpK+B!@lD^Www*@V928V2dF@ zbn4S4qR-M2bb{+N@eQUUtQ?2sd_~;(s<`tNap$Y-f*xiRZ++%F;VadT!jli2R4;Gu6qHR2FMnEZv z4g{Z$8B~*Ew{THtT?p3tqEBMq$85Ajy)y8WO9Kxs4?OI6j%*$_d4s@XnFalf#8a+d z_Ca5)=VAmF)Opx`Z2xw?Hvc#B=SxsiUCOoE_&jrj!Y}YxY6PP?(zPKR87OURS~_z^ z?cAZEmcl#bzdfU1O+rz4Ka3E6J-LYz& z!b8C}R-~ckQ_67)McCN<@8)GWW%+%)G z+}s>b1{B@^6}bV=NbR9~jc2T_J<5~9Q~U_YSOBA0r*vg|#zW&{lF}}3z`N9w4%s-? zquu+-#oJ^78x_3mNHb$vp)ZXC8;Z~w>TdPA4X>cI(U{W&>yf3X+5&ECRO?5@Z# zdswyXglj>})0#82f75%^DIPz{ZF-OA0Ek*6Ac#Jm?8$~6 zJ>0jz+w93OGxXR=4H$4@c(bKtR|na^$=Po=ziE%Z@0K2ScI7qr`3}5Fci-aC-R(4Z zQ@6Y8Kj`Zn-?&777_LNjCY0#XLre6p|F}eZq>E0>&c<}rvy;u<>G7f2{g_}LZ=q+j z?t)`IIULI#Z>gTIWS)*Fnu){}*WDHW!fh#0p3192H=uVQSE-gz51!JR@L$F`42up<(fK#BsXB>E79%8Bom+c*X=hN3cW~K1gS#1@v&wXK{m` z3=6X@qT9vzg&B3W5nM-G^MU;=PIWmp<5`nM*KD z^XbA|7f9;GGF^NRa%cUq;AWcX?9@VC7gR9H7B`ONhn^VLhh7VRY{Dm3Olx|i(8m1j zInMd>CWbziOQ*pt=NO(`vnPlaFblAz7bLCNcVK{jO+6;*dbAx{55I04YXGI7K3R~_ z;#pRGigbO@2?K|(&u&*jeNuIOEnL{)8F?ee94xOw3nj-*%=jy4R{ zYzX&8o6hQw$Fwv?L(wo*)!`1cPD`p{Fxpoc8fUz7hL#AF@hTrpcw)cdhLptZmm5nDWX5X?n)Z5-2%Ox7_=~vx-z3T${W3YFi zYh7=+J-{Cihft$fv0EG^wu`vDH(c2jZ4CAFcX#!!Q_FEr7ZaL>nmfXgs=h%uiu?~Yc5y1Ung+Scn*Ea_`oZ|6*t#i8zw1S6dd zbLejxsvPX-sETL_Rvt8979GA~&!Aa-R(7<|S^-g27uOCe?05K8{^;Cui!ZHq&qrFr$ zx~#4j%@b9ug=*^R3HJ>~RdrV++!pQX>s9rk2!@01vB;3B7#M&p^fXlXNzeOmjzWkD~TQS=zzUZz zH^`yOi%wG~E=Qex-R+jcs?KoRdiE&Cd^p~Ctg*hX=v8f5byI_CJTug<8k(>g>SoX@ zTWs1Sl}@JfqGc-sRpoO7)?;{JM%j#+9Yyfh{V6R?KV>;b0*4n9)X&=SjJ4U1m|t?|Z1rC(ps zc*nz)tYR%jMeG8Pv5I9uM|>CZm+hAdg;3vT=1o3qMH-)5v=h4e4-O}Bk859GZCaTS?)XQyTQD$;>>ZFcyBhwA@ltv+ml|{R<4BiolNgZvd0@W$6>0Jq8Q>7-w<2P!K!&K=>@%U|)<1p2Tq zBa`AsCdFqb#b+nQ=O)GHCdH3VlAWWA`6srXsm3MQ=O@V%ljKQBGJjMPKTQ4Qk5fKU z&4bACz_~RF{a+W4)<1`CPLjKmWapP8{DRlufEC>BfOOpAo3{-Laj>32dCCHfy51~4qbA1&0``aROUXMcm-Urz}=>J)X=iDBp zvei3D@t;dP=l3Xu{yf|revx(OflJk}5460_CEWArD*$fRSo4|`+9_-}Ae>2PCTDTjG3p_P4$F4wqW@2(x*hIu$(O4KI#!t6+taFc!5 z`-J#YUGlTu;au^?(z@Zpb=UEDm~=Oi^acWB<0yo*Db`o^X;bmbVan5#ijvct_n*3oC^DR*UJD3t1k@rwDt61HvuB8-$Mw|1A8wkpC}5KkdS(@D<^1;g`a6 zT*7G2e*+?mg#157%4Nd2!WF_*!qbEU!V82~3%@7)sqh!V7leNneklA*n2Jj&^Uo6& z3oC_-h0BCZ!qvi7;X2`v@Iv8r!rO)S3!fD35c0o7SdM=RzZ7P;Ej|B7i1AZ}M++AV zhlJk|-YtAY_>Axs;XA^;LKkiU=zo-OvT%;DM%W~56GnvR3%3fl3HiT7^!p3p^TOAK ze;0l!8d@TbCG2wxELpM#j+hr-Wn?!CFo+|n-k$Z#@(Qg#_ z0^!9Z^1WR6J<;DG{BP0UFML?|ti=Bx;mg8Tg>RAYyG!_?@PNdBA@rod4(*XD93>nr z%qQWelteo%AaNVFP*_bO{W6JPE%Ir?HqrNqJRlqr{T7ig5ndts?}+?e;ca9A{_#cR zp9`NRQJ&|7F9`o4@oxz~6n-T9ltj9(gf85AQ}&anPqvW%Z$UXAoFXg{&LWYnmPGqB zlB4l2tin@Bqz_B{86pn~&ldefB3~xFO7u62yiItA= zABg-<;a<@n6xqZDm*w@5@RuWUo-m(8{f-jOC1F=h=HS;O!j+;Ak*vS)bcyd3o+tXv z!f%QGYT>tqKaltz2_FzXB7BlW{?7=X7yeP=Ul+b3d{4MX__2`x*~I#!<59~sO8;|> z=6K4`7n7*ZbYZ#J%@)>*{sdv8=$nOWggp{}hVX3RM&TtS^1niOweVJnzfE|L@TbB@ zg^vq=MWWolBk=(62jOcH|Bl4(7I~lWQ_-j5k&@|iNz{9caDwQkiX0TqB$3YoVTbSx z5`H$42p0%1BH?!{iTGPY{+{qo(cdTXL&Bet2)`$hZYPPpdq=oO^k0(jZ{X3F^pdbk z6OI%8L}9V$ON8aZN{O!(E*CZmPbJ}Zt*}ElAn|7kHwm{0uMl1>yop48?jo@^-6MQd z^iPwh$FGGiNc>B}w?zLp;YXt1Cp;ibMIX`62;peqSYZ)~{HF*@g!3i-IN>7UiNYpf zvoJ)WK0PF^!Dk2uCH_2#zf9ySh1ZJyR*`QL-X;3`MSfWLbJ0H|^7F#qivBf`{~~;w zM0xfL)A4{od7`k4M7gVk^}th z{Gsr_g%1fI6LQZ7=KrFQn>$c`Tgd$#C?61VF9*sag!(xSa)HR)(Sh;$`3>ZL4ZJ@% zLD(QXNvNOa5WiOBjY9og2mPfYUm?6sc%zUzBGLct!XF8LB78{rn2?)7(Ed%~--I6s z_46R&zY-ZgxzhIf`4IXsBIgUap9KBQ7gh*sge!$73tNTl!l+O`FTxMEqM*NPg*OYi z`xNze3GWd;AbdplobUx9ccoyuw}jl7g7SVL|9OG3e!c{`4+Z5(LT*Jtd5(}9P4NDw zPPjt2Qm8kBLj0h}=Lk0mFBV=dyheDv@VmnA3-$9W{QX#D?q0$CUlqP7d|UW|@Sno3 zg!;J_=~A)gF#QN2x5J{GCoC3D7jg>$#?KXUqYTQY3fqO9!am`EaI^4Y;g!N`g!;J{ z{#uRZwlWQaxV?0`=?OvRs@-QJ5kS_ILOh$eBmUaey&FRbdhHZ zj}~&%4yLacau+DdrwF-!2W9S=MV=+(9y^q|B?s?IZxn75-Y$GV_=r$Hm&5*lMApyc zkavpA-8txwJNuB_po2^kax)If6NTK5gYqmPx8$H)Cu}8gpV=;4FYFVZC)_N&On9Y` zyKyl6kA>WJgYuI??z}zPI$9$n~+ z5^@I+%4>vSVVAI97!`7p5ZYfZyj6Ic@E+k$g-;0edj+K9HX%&^Cn5L$U>&&a5&60B zpisX*z`1^Z0FLEzH8?@Y9YQEC5OOOJ$}5GZ3D*j{ggwGd!YxAX48rvKJpriS4}f=z zUcVQByj^7O7ef2r3AsH8?|a`B{zJG&_^I$qA$Ja;y?ze>7KvOeZ&B5K05CZZCaV*-?6R3t1WQJ(2ST^=N!MH!q&qI?U43rUo-TDX`*d6x)vc~R~r z%3w2z@~;uLk|J=5<$oqM;-@_!zUB~-fl=rVB%6As;4^h6yNtEjt zGz81@0*U-v$5yewjzoFx75PCD<$6Nor^y`bb|v!5B-&}8$OlN2mm71keE1g`UGC{3mysyH z3J#pr6Ai5eqY;ap_8ESh6;(n0lu8BH4h*Ou6+!tDbJ%Z#gZS}{WyLQd6TTOYtHr@^ z-{~G=H0(FKiMf1(?|2gvNd8~*ZSNt)Nct}Kkoe?pbcf9_@w?rBZ^CbRzkwCM!abxw zNnhk@H|^oIgX>zldOP~isro#$c5NiQ!OFza;AfFeF%${)t_!2**{_zxp&I%!6%9*+p=dPHwRSKHxBtO04z?Jw`uk!go5c^uf$6M|N%*84 zrn5eh?HI>nG6JUOzqR9hPR=(7oqgE(HbCLDTML=L{jd+)ZW$D~MN$hTqNqZt0M3s> z!1AHjVV0{4!Rc=&WM^G$e^(~iah?xn_h^#cV%W`r&OU5^4?^KAUv-7mPAnhwSQd4= zy$?Few-Lf{^?g^;Ed+Tifj=xuy1uy8i22J!dZ$0`k~&;F&rY)A_vypgtxmFQh8=%9 zV;^>X`TogS-}VaYn#=m)6>6+}_%D%!@;!_J#=f)<+aLZRFTr0F{@9=NhgXL&f43+3 zbE9GFZD*kEZ(EYTa~%G%9sZt4^4A1^>?`}Q{e2*Iwx0W7-pqo@foOgF4JXca*;0Y; zU~#=-J#d+c)#H;Se|z!64a1&%u(SR7PyqX!8SKL#xD59?_F>1lVdu_Wkq`SMtkRK9B5h&=&4%U6hCm#+tQ==Of7^ih0_wWEYB v+pbBN#*Q_xyB7&r#$p8e%R*q)ppG3Gcu}6~NND@x&~@6mPgUyNVeI}dKUmkk literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_it.d b/build/stm32f7xx_it.d new file mode 100644 index 0000000..f98b74b --- /dev/null +++ b/build/stm32f7xx_it.d @@ -0,0 +1,93 @@ +build/stm32f7xx_it.o: Src/stm32f7xx_it.c Inc/main.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h Inc/stm32f7xx_it.h +Inc/main.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h: +Inc/stm32f7xx_it.h: diff --git a/build/stm32f7xx_it.lst b/build/stm32f7xx_it.lst new file mode 100644 index 0000000..400b9aa --- /dev/null +++ b/build/stm32f7xx_it.lst @@ -0,0 +1,13989 @@ +ARM GAS /tmp/ccvzubVv.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_it.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Src/stm32f7xx_it.c" + 19 .section .text.NMI_Handler,"ax",%progbits + 20 .align 1 + 21 .global NMI_Handler + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 NMI_Handler: + 27 .LFB1183: + 1:Src/stm32f7xx_it.c **** /* USER CODE BEGIN Header */ + 2:Src/stm32f7xx_it.c **** /** + 3:Src/stm32f7xx_it.c **** ****************************************************************************** + 4:Src/stm32f7xx_it.c **** * @file stm32f7xx_it.c + 5:Src/stm32f7xx_it.c **** * @brief Interrupt Service Routines. + 6:Src/stm32f7xx_it.c **** ****************************************************************************** + 7:Src/stm32f7xx_it.c **** * @attention + 8:Src/stm32f7xx_it.c **** * + 9:Src/stm32f7xx_it.c **** * Copyright (c) 2023 STMicroelectronics. + 10:Src/stm32f7xx_it.c **** * All rights reserved. + 11:Src/stm32f7xx_it.c **** * + 12:Src/stm32f7xx_it.c **** * This software is licensed under terms that can be found in the LICENSE file + 13:Src/stm32f7xx_it.c **** * in the root directory of this software component. + 14:Src/stm32f7xx_it.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Src/stm32f7xx_it.c **** * + 16:Src/stm32f7xx_it.c **** ****************************************************************************** + 17:Src/stm32f7xx_it.c **** */ + 18:Src/stm32f7xx_it.c **** /* USER CODE END Header */ + 19:Src/stm32f7xx_it.c **** + 20:Src/stm32f7xx_it.c **** /* Includes ------------------------------------------------------------------*/ + 21:Src/stm32f7xx_it.c **** #include "main.h" + 22:Src/stm32f7xx_it.c **** #include "stm32f7xx_it.h" + 23:Src/stm32f7xx_it.c **** /* Private includes ----------------------------------------------------------*/ + 24:Src/stm32f7xx_it.c **** /* USER CODE BEGIN Includes */ + 25:Src/stm32f7xx_it.c **** /* USER CODE END Includes */ + 26:Src/stm32f7xx_it.c **** + 27:Src/stm32f7xx_it.c **** /* Private typedef -----------------------------------------------------------*/ + 28:Src/stm32f7xx_it.c **** /* USER CODE BEGIN TD */ + 29:Src/stm32f7xx_it.c **** + 30:Src/stm32f7xx_it.c **** /* USER CODE END TD */ + 31:Src/stm32f7xx_it.c **** + ARM GAS /tmp/ccvzubVv.s page 2 + + + 32:Src/stm32f7xx_it.c **** /* Private define ------------------------------------------------------------*/ + 33:Src/stm32f7xx_it.c **** /* USER CODE BEGIN PD */ + 34:Src/stm32f7xx_it.c **** + 35:Src/stm32f7xx_it.c **** /* USER CODE END PD */ + 36:Src/stm32f7xx_it.c **** + 37:Src/stm32f7xx_it.c **** /* Private macro -------------------------------------------------------------*/ + 38:Src/stm32f7xx_it.c **** /* USER CODE BEGIN PM */ + 39:Src/stm32f7xx_it.c **** + 40:Src/stm32f7xx_it.c **** /* USER CODE END PM */ + 41:Src/stm32f7xx_it.c **** + 42:Src/stm32f7xx_it.c **** /* Private variables ---------------------------------------------------------*/ + 43:Src/stm32f7xx_it.c **** /* USER CODE BEGIN PV */ + 44:Src/stm32f7xx_it.c **** extern uint32_t TO6, TO7, TO6_uart, TO10, TO10_counter; + 45:Src/stm32f7xx_it.c **** extern uint16_t UART_rec_incr, UART_header, COMMAND[CL_16]; + 46:Src/stm32f7xx_it.c **** extern uint8_t uart_buf, flg_tmt, CPU_state, State_Data[2], UART_transmission_request, u_tx_flg, T + 47:Src/stm32f7xx_it.c **** extern task_t task; + 48:Src/stm32f7xx_it.c **** extern task_state; + 49:Src/stm32f7xx_it.c **** extern LD_Blinker_StateTypeDef LD_blinker; + 50:Src/stm32f7xx_it.c **** /* USER CODE END PV */ + 51:Src/stm32f7xx_it.c **** + 52:Src/stm32f7xx_it.c **** /* Private function prototypes -----------------------------------------------*/ + 53:Src/stm32f7xx_it.c **** /* USER CODE BEGIN PFP */ + 54:Src/stm32f7xx_it.c **** void UART_RxCpltCallback(void); + 55:Src/stm32f7xx_it.c **** void DMA2_Stream7_TransferComplete(void); + 56:Src/stm32f7xx_it.c **** /* USER CODE END PFP */ + 57:Src/stm32f7xx_it.c **** + 58:Src/stm32f7xx_it.c **** /* Private user code ---------------------------------------------------------*/ + 59:Src/stm32f7xx_it.c **** /* USER CODE BEGIN 0 */ + 60:Src/stm32f7xx_it.c **** + 61:Src/stm32f7xx_it.c **** /* USER CODE END 0 */ + 62:Src/stm32f7xx_it.c **** + 63:Src/stm32f7xx_it.c **** /* External variables --------------------------------------------------------*/ + 64:Src/stm32f7xx_it.c **** extern ADC_HandleTypeDef hadc1; + 65:Src/stm32f7xx_it.c **** extern ADC_HandleTypeDef hadc3; + 66:Src/stm32f7xx_it.c **** extern TIM_HandleTypeDef htim8; + 67:Src/stm32f7xx_it.c **** extern TIM_HandleTypeDef htim10; + 68:Src/stm32f7xx_it.c **** extern TIM_HandleTypeDef htim11; + 69:Src/stm32f7xx_it.c **** /* USER CODE BEGIN EV */ + 70:Src/stm32f7xx_it.c **** + 71:Src/stm32f7xx_it.c **** /* USER CODE END EV */ + 72:Src/stm32f7xx_it.c **** + 73:Src/stm32f7xx_it.c **** /******************************************************************************/ + 74:Src/stm32f7xx_it.c **** /* Cortex-M7 Processor Interruption and Exception Handlers */ + 75:Src/stm32f7xx_it.c **** /******************************************************************************/ + 76:Src/stm32f7xx_it.c **** /** + 77:Src/stm32f7xx_it.c **** * @brief This function handles Non maskable interrupt. + 78:Src/stm32f7xx_it.c **** */ + 79:Src/stm32f7xx_it.c **** void NMI_Handler(void) + 80:Src/stm32f7xx_it.c **** { + 28 .loc 1 80 1 view -0 + 29 .cfi_startproc + 30 @ Volatile: function does not return. + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 34 .L2: + 81:Src/stm32f7xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + ARM GAS /tmp/ccvzubVv.s page 3 + + + 82:Src/stm32f7xx_it.c **** + 83:Src/stm32f7xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 0 */ + 84:Src/stm32f7xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + 85:Src/stm32f7xx_it.c **** while (1) + 35 .loc 1 85 3 view .LVU1 + 86:Src/stm32f7xx_it.c **** { + 87:Src/stm32f7xx_it.c **** } + 36 .loc 1 87 3 view .LVU2 + 85:Src/stm32f7xx_it.c **** { + 37 .loc 1 85 9 view .LVU3 + 38 0000 FEE7 b .L2 + 39 .cfi_endproc + 40 .LFE1183: + 42 .section .text.HardFault_Handler,"ax",%progbits + 43 .align 1 + 44 .global HardFault_Handler + 45 .syntax unified + 46 .thumb + 47 .thumb_func + 49 HardFault_Handler: + 50 .LFB1184: + 88:Src/stm32f7xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 1 */ + 89:Src/stm32f7xx_it.c **** } + 90:Src/stm32f7xx_it.c **** + 91:Src/stm32f7xx_it.c **** /** + 92:Src/stm32f7xx_it.c **** * @brief This function handles Hard fault interrupt. + 93:Src/stm32f7xx_it.c **** */ + 94:Src/stm32f7xx_it.c **** void HardFault_Handler(void) + 95:Src/stm32f7xx_it.c **** { + 51 .loc 1 95 1 view -0 + 52 .cfi_startproc + 53 @ Volatile: function does not return. + 54 @ args = 0, pretend = 0, frame = 0 + 55 @ frame_needed = 0, uses_anonymous_args = 0 + 56 @ link register save eliminated. + 57 .L4: + 96:Src/stm32f7xx_it.c **** /* USER CODE BEGIN HardFault_IRQn 0 */ + 97:Src/stm32f7xx_it.c **** + 98:Src/stm32f7xx_it.c **** /* USER CODE END HardFault_IRQn 0 */ + 99:Src/stm32f7xx_it.c **** while (1) + 58 .loc 1 99 3 view .LVU5 + 100:Src/stm32f7xx_it.c **** { + 101:Src/stm32f7xx_it.c **** /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + 102:Src/stm32f7xx_it.c **** /* USER CODE END W1_HardFault_IRQn 0 */ + 103:Src/stm32f7xx_it.c **** } + 59 .loc 1 103 3 view .LVU6 + 99:Src/stm32f7xx_it.c **** { + 60 .loc 1 99 9 view .LVU7 + 61 0000 FEE7 b .L4 + 62 .cfi_endproc + 63 .LFE1184: + 65 .section .text.MemManage_Handler,"ax",%progbits + 66 .align 1 + 67 .global MemManage_Handler + 68 .syntax unified + 69 .thumb + 70 .thumb_func + ARM GAS /tmp/ccvzubVv.s page 4 + + + 72 MemManage_Handler: + 73 .LFB1185: + 104:Src/stm32f7xx_it.c **** } + 105:Src/stm32f7xx_it.c **** + 106:Src/stm32f7xx_it.c **** /** + 107:Src/stm32f7xx_it.c **** * @brief This function handles Memory management fault. + 108:Src/stm32f7xx_it.c **** */ + 109:Src/stm32f7xx_it.c **** void MemManage_Handler(void) + 110:Src/stm32f7xx_it.c **** { + 74 .loc 1 110 1 view -0 + 75 .cfi_startproc + 76 @ Volatile: function does not return. + 77 @ args = 0, pretend = 0, frame = 0 + 78 @ frame_needed = 0, uses_anonymous_args = 0 + 79 @ link register save eliminated. + 80 .L6: + 111:Src/stm32f7xx_it.c **** /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + 112:Src/stm32f7xx_it.c **** + 113:Src/stm32f7xx_it.c **** /* USER CODE END MemoryManagement_IRQn 0 */ + 114:Src/stm32f7xx_it.c **** while (1) + 81 .loc 1 114 3 view .LVU9 + 115:Src/stm32f7xx_it.c **** { + 116:Src/stm32f7xx_it.c **** /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + 117:Src/stm32f7xx_it.c **** /* USER CODE END W1_MemoryManagement_IRQn 0 */ + 118:Src/stm32f7xx_it.c **** } + 82 .loc 1 118 3 view .LVU10 + 114:Src/stm32f7xx_it.c **** { + 83 .loc 1 114 9 view .LVU11 + 84 0000 FEE7 b .L6 + 85 .cfi_endproc + 86 .LFE1185: + 88 .section .text.BusFault_Handler,"ax",%progbits + 89 .align 1 + 90 .global BusFault_Handler + 91 .syntax unified + 92 .thumb + 93 .thumb_func + 95 BusFault_Handler: + 96 .LFB1186: + 119:Src/stm32f7xx_it.c **** } + 120:Src/stm32f7xx_it.c **** + 121:Src/stm32f7xx_it.c **** /** + 122:Src/stm32f7xx_it.c **** * @brief This function handles Pre-fetch fault, memory access fault. + 123:Src/stm32f7xx_it.c **** */ + 124:Src/stm32f7xx_it.c **** void BusFault_Handler(void) + 125:Src/stm32f7xx_it.c **** { + 97 .loc 1 125 1 view -0 + 98 .cfi_startproc + 99 @ Volatile: function does not return. + 100 @ args = 0, pretend = 0, frame = 0 + 101 @ frame_needed = 0, uses_anonymous_args = 0 + 102 @ link register save eliminated. + 103 .L8: + 126:Src/stm32f7xx_it.c **** /* USER CODE BEGIN BusFault_IRQn 0 */ + 127:Src/stm32f7xx_it.c **** + 128:Src/stm32f7xx_it.c **** /* USER CODE END BusFault_IRQn 0 */ + 129:Src/stm32f7xx_it.c **** while (1) + ARM GAS /tmp/ccvzubVv.s page 5 + + + 104 .loc 1 129 3 view .LVU13 + 130:Src/stm32f7xx_it.c **** { + 131:Src/stm32f7xx_it.c **** /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + 132:Src/stm32f7xx_it.c **** /* USER CODE END W1_BusFault_IRQn 0 */ + 133:Src/stm32f7xx_it.c **** } + 105 .loc 1 133 3 view .LVU14 + 129:Src/stm32f7xx_it.c **** { + 106 .loc 1 129 9 view .LVU15 + 107 0000 FEE7 b .L8 + 108 .cfi_endproc + 109 .LFE1186: + 111 .section .text.UsageFault_Handler,"ax",%progbits + 112 .align 1 + 113 .global UsageFault_Handler + 114 .syntax unified + 115 .thumb + 116 .thumb_func + 118 UsageFault_Handler: + 119 .LFB1187: + 134:Src/stm32f7xx_it.c **** } + 135:Src/stm32f7xx_it.c **** + 136:Src/stm32f7xx_it.c **** /** + 137:Src/stm32f7xx_it.c **** * @brief This function handles Undefined instruction or illegal state. + 138:Src/stm32f7xx_it.c **** */ + 139:Src/stm32f7xx_it.c **** void UsageFault_Handler(void) + 140:Src/stm32f7xx_it.c **** { + 120 .loc 1 140 1 view -0 + 121 .cfi_startproc + 122 @ Volatile: function does not return. + 123 @ args = 0, pretend = 0, frame = 0 + 124 @ frame_needed = 0, uses_anonymous_args = 0 + 125 @ link register save eliminated. + 126 .L10: + 141:Src/stm32f7xx_it.c **** /* USER CODE BEGIN UsageFault_IRQn 0 */ + 142:Src/stm32f7xx_it.c **** + 143:Src/stm32f7xx_it.c **** /* USER CODE END UsageFault_IRQn 0 */ + 144:Src/stm32f7xx_it.c **** while (1) + 127 .loc 1 144 3 view .LVU17 + 145:Src/stm32f7xx_it.c **** { + 146:Src/stm32f7xx_it.c **** /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + 147:Src/stm32f7xx_it.c **** /* USER CODE END W1_UsageFault_IRQn 0 */ + 148:Src/stm32f7xx_it.c **** } + 128 .loc 1 148 3 view .LVU18 + 144:Src/stm32f7xx_it.c **** { + 129 .loc 1 144 9 view .LVU19 + 130 0000 FEE7 b .L10 + 131 .cfi_endproc + 132 .LFE1187: + 134 .section .text.SVC_Handler,"ax",%progbits + 135 .align 1 + 136 .global SVC_Handler + 137 .syntax unified + 138 .thumb + 139 .thumb_func + 141 SVC_Handler: + 142 .LFB1188: + 149:Src/stm32f7xx_it.c **** } + ARM GAS /tmp/ccvzubVv.s page 6 + + + 150:Src/stm32f7xx_it.c **** + 151:Src/stm32f7xx_it.c **** /** + 152:Src/stm32f7xx_it.c **** * @brief This function handles System service call via SWI instruction. + 153:Src/stm32f7xx_it.c **** */ + 154:Src/stm32f7xx_it.c **** void SVC_Handler(void) + 155:Src/stm32f7xx_it.c **** { + 143 .loc 1 155 1 view -0 + 144 .cfi_startproc + 145 @ args = 0, pretend = 0, frame = 0 + 146 @ frame_needed = 0, uses_anonymous_args = 0 + 147 @ link register save eliminated. + 156:Src/stm32f7xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 0 */ + 157:Src/stm32f7xx_it.c **** + 158:Src/stm32f7xx_it.c **** /* USER CODE END SVCall_IRQn 0 */ + 159:Src/stm32f7xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 1 */ + 160:Src/stm32f7xx_it.c **** + 161:Src/stm32f7xx_it.c **** /* USER CODE END SVCall_IRQn 1 */ + 162:Src/stm32f7xx_it.c **** } + 148 .loc 1 162 1 view .LVU21 + 149 0000 7047 bx lr + 150 .cfi_endproc + 151 .LFE1188: + 153 .section .text.DebugMon_Handler,"ax",%progbits + 154 .align 1 + 155 .global DebugMon_Handler + 156 .syntax unified + 157 .thumb + 158 .thumb_func + 160 DebugMon_Handler: + 161 .LFB1189: + 163:Src/stm32f7xx_it.c **** + 164:Src/stm32f7xx_it.c **** /** + 165:Src/stm32f7xx_it.c **** * @brief This function handles Debug monitor. + 166:Src/stm32f7xx_it.c **** */ + 167:Src/stm32f7xx_it.c **** void DebugMon_Handler(void) + 168:Src/stm32f7xx_it.c **** { + 162 .loc 1 168 1 view -0 + 163 .cfi_startproc + 164 @ args = 0, pretend = 0, frame = 0 + 165 @ frame_needed = 0, uses_anonymous_args = 0 + 166 @ link register save eliminated. + 169:Src/stm32f7xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + 170:Src/stm32f7xx_it.c **** + 171:Src/stm32f7xx_it.c **** /* USER CODE END DebugMonitor_IRQn 0 */ + 172:Src/stm32f7xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + 173:Src/stm32f7xx_it.c **** + 174:Src/stm32f7xx_it.c **** /* USER CODE END DebugMonitor_IRQn 1 */ + 175:Src/stm32f7xx_it.c **** } + 167 .loc 1 175 1 view .LVU23 + 168 0000 7047 bx lr + 169 .cfi_endproc + 170 .LFE1189: + 172 .section .text.PendSV_Handler,"ax",%progbits + 173 .align 1 + 174 .global PendSV_Handler + 175 .syntax unified + 176 .thumb + ARM GAS /tmp/ccvzubVv.s page 7 + + + 177 .thumb_func + 179 PendSV_Handler: + 180 .LFB1190: + 176:Src/stm32f7xx_it.c **** + 177:Src/stm32f7xx_it.c **** /** + 178:Src/stm32f7xx_it.c **** * @brief This function handles Pendable request for system service. + 179:Src/stm32f7xx_it.c **** */ + 180:Src/stm32f7xx_it.c **** void PendSV_Handler(void) + 181:Src/stm32f7xx_it.c **** { + 181 .loc 1 181 1 view -0 + 182 .cfi_startproc + 183 @ args = 0, pretend = 0, frame = 0 + 184 @ frame_needed = 0, uses_anonymous_args = 0 + 185 @ link register save eliminated. + 182:Src/stm32f7xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 0 */ + 183:Src/stm32f7xx_it.c **** + 184:Src/stm32f7xx_it.c **** /* USER CODE END PendSV_IRQn 0 */ + 185:Src/stm32f7xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 1 */ + 186:Src/stm32f7xx_it.c **** + 187:Src/stm32f7xx_it.c **** /* USER CODE END PendSV_IRQn 1 */ + 188:Src/stm32f7xx_it.c **** } + 186 .loc 1 188 1 view .LVU25 + 187 0000 7047 bx lr + 188 .cfi_endproc + 189 .LFE1190: + 191 .section .text.SysTick_Handler,"ax",%progbits + 192 .align 1 + 193 .global SysTick_Handler + 194 .syntax unified + 195 .thumb + 196 .thumb_func + 198 SysTick_Handler: + 199 .LFB1191: + 189:Src/stm32f7xx_it.c **** + 190:Src/stm32f7xx_it.c **** /** + 191:Src/stm32f7xx_it.c **** * @brief This function handles System tick timer. + 192:Src/stm32f7xx_it.c **** */ + 193:Src/stm32f7xx_it.c **** void SysTick_Handler(void) + 194:Src/stm32f7xx_it.c **** { + 200 .loc 1 194 1 view -0 + 201 .cfi_startproc + 202 @ args = 0, pretend = 0, frame = 0 + 203 @ frame_needed = 0, uses_anonymous_args = 0 + 204 0000 08B5 push {r3, lr} + 205 .LCFI0: + 206 .cfi_def_cfa_offset 8 + 207 .cfi_offset 3, -8 + 208 .cfi_offset 14, -4 + 195:Src/stm32f7xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 0 */ + 196:Src/stm32f7xx_it.c **** + 197:Src/stm32f7xx_it.c **** /* USER CODE END SysTick_IRQn 0 */ + 198:Src/stm32f7xx_it.c **** HAL_IncTick(); + 209 .loc 1 198 3 view .LVU27 + 210 0002 FFF7FEFF bl HAL_IncTick + 211 .LVL0: + 199:Src/stm32f7xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 1 */ + 200:Src/stm32f7xx_it.c **** + ARM GAS /tmp/ccvzubVv.s page 8 + + + 201:Src/stm32f7xx_it.c **** /* USER CODE END SysTick_IRQn 1 */ + 202:Src/stm32f7xx_it.c **** } + 212 .loc 1 202 1 is_stmt 0 view .LVU28 + 213 0006 08BD pop {r3, pc} + 214 .cfi_endproc + 215 .LFE1191: + 217 .section .text.ADC_IRQHandler,"ax",%progbits + 218 .align 1 + 219 .global ADC_IRQHandler + 220 .syntax unified + 221 .thumb + 222 .thumb_func + 224 ADC_IRQHandler: + 225 .LFB1192: + 203:Src/stm32f7xx_it.c **** + 204:Src/stm32f7xx_it.c **** /******************************************************************************/ + 205:Src/stm32f7xx_it.c **** /* STM32F7xx Peripheral Interrupt Handlers */ + 206:Src/stm32f7xx_it.c **** /* Add here the Interrupt Handlers for the used peripherals. */ + 207:Src/stm32f7xx_it.c **** /* For the available peripheral interrupt handler names, */ + 208:Src/stm32f7xx_it.c **** /* please refer to the startup file (startup_stm32f7xx.s). */ + 209:Src/stm32f7xx_it.c **** /******************************************************************************/ + 210:Src/stm32f7xx_it.c **** + 211:Src/stm32f7xx_it.c **** /** + 212:Src/stm32f7xx_it.c **** * @brief This function handles ADC1, ADC2 and ADC3 global interrupts. + 213:Src/stm32f7xx_it.c **** */ + 214:Src/stm32f7xx_it.c **** void ADC_IRQHandler(void) + 215:Src/stm32f7xx_it.c **** { + 226 .loc 1 215 1 is_stmt 1 view -0 + 227 .cfi_startproc + 228 @ args = 0, pretend = 0, frame = 0 + 229 @ frame_needed = 0, uses_anonymous_args = 0 + 230 0000 08B5 push {r3, lr} + 231 .LCFI1: + 232 .cfi_def_cfa_offset 8 + 233 .cfi_offset 3, -8 + 234 .cfi_offset 14, -4 + 216:Src/stm32f7xx_it.c **** /* USER CODE BEGIN ADC_IRQn 0 */ + 217:Src/stm32f7xx_it.c **** + 218:Src/stm32f7xx_it.c **** /* USER CODE END ADC_IRQn 0 */ + 219:Src/stm32f7xx_it.c **** HAL_ADC_IRQHandler(&hadc1); + 235 .loc 1 219 3 view .LVU30 + 236 0002 0348 ldr r0, .L18 + 237 0004 FFF7FEFF bl HAL_ADC_IRQHandler + 238 .LVL1: + 220:Src/stm32f7xx_it.c **** HAL_ADC_IRQHandler(&hadc3); + 239 .loc 1 220 3 view .LVU31 + 240 0008 0248 ldr r0, .L18+4 + 241 000a FFF7FEFF bl HAL_ADC_IRQHandler + 242 .LVL2: + 221:Src/stm32f7xx_it.c **** /* USER CODE BEGIN ADC_IRQn 1 */ + 222:Src/stm32f7xx_it.c **** + 223:Src/stm32f7xx_it.c **** /* USER CODE END ADC_IRQn 1 */ + 224:Src/stm32f7xx_it.c **** } + 243 .loc 1 224 1 is_stmt 0 view .LVU32 + 244 000e 08BD pop {r3, pc} + 245 .L19: + 246 .align 2 + ARM GAS /tmp/ccvzubVv.s page 9 + + + 247 .L18: + 248 0010 00000000 .word hadc1 + 249 0014 00000000 .word hadc3 + 250 .cfi_endproc + 251 .LFE1192: + 253 .section .text.TIM1_UP_TIM10_IRQHandler,"ax",%progbits + 254 .align 1 + 255 .global TIM1_UP_TIM10_IRQHandler + 256 .syntax unified + 257 .thumb + 258 .thumb_func + 260 TIM1_UP_TIM10_IRQHandler: + 261 .LFB1193: + 225:Src/stm32f7xx_it.c **** + 226:Src/stm32f7xx_it.c **** /** + 227:Src/stm32f7xx_it.c **** * @brief This function handles TIM1 update interrupt and TIM10 global interrupt. + 228:Src/stm32f7xx_it.c **** */ + 229:Src/stm32f7xx_it.c **** void TIM1_UP_TIM10_IRQHandler(void) + 230:Src/stm32f7xx_it.c **** { + 262 .loc 1 230 1 is_stmt 1 view -0 + 263 .cfi_startproc + 264 @ args = 0, pretend = 0, frame = 0 + 265 @ frame_needed = 0, uses_anonymous_args = 0 + 266 0000 08B5 push {r3, lr} + 267 .LCFI2: + 268 .cfi_def_cfa_offset 8 + 269 .cfi_offset 3, -8 + 270 .cfi_offset 14, -4 + 231:Src/stm32f7xx_it.c **** /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 0 */ + 232:Src/stm32f7xx_it.c **** //HAL_GPIO_WritePin(GPIOG, GPIO_PIN_9, GPIO_PIN_SET); // set the current step laser current trigge + 233:Src/stm32f7xx_it.c **** //HAL_GPIO_WritePin(GPIOG, GPIO_PIN_9, GPIO_PIN_RESET); + 234:Src/stm32f7xx_it.c **** TO10++; + 271 .loc 1 234 2 view .LVU34 + 272 .loc 1 234 6 is_stmt 0 view .LVU35 + 273 0002 084A ldr r2, .L24 + 274 0004 1368 ldr r3, [r2] + 275 0006 0133 adds r3, r3, #1 + 276 0008 1360 str r3, [r2] + 235:Src/stm32f7xx_it.c **** if (TO10 == TO10_counter) + 277 .loc 1 235 2 is_stmt 1 view .LVU36 + 278 .loc 1 235 11 is_stmt 0 view .LVU37 + 279 000a 074A ldr r2, .L24+4 + 280 000c 1268 ldr r2, [r2] + 281 .loc 1 235 5 view .LVU38 + 282 000e 9342 cmp r3, r2 + 283 0010 03D0 beq .L23 + 284 .L21: + 236:Src/stm32f7xx_it.c **** TIM10_coflag = 1; + 237:Src/stm32f7xx_it.c **** /* USER CODE END TIM1_UP_TIM10_IRQn 0 */ + 238:Src/stm32f7xx_it.c **** HAL_TIM_IRQHandler(&htim10); + 285 .loc 1 238 3 is_stmt 1 view .LVU39 + 286 0012 0648 ldr r0, .L24+8 + 287 0014 FFF7FEFF bl HAL_TIM_IRQHandler + 288 .LVL3: + 239:Src/stm32f7xx_it.c **** /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 1 */ + 240:Src/stm32f7xx_it.c **** + 241:Src/stm32f7xx_it.c **** /* USER CODE END TIM1_UP_TIM10_IRQn 1 */ + ARM GAS /tmp/ccvzubVv.s page 10 + + + 242:Src/stm32f7xx_it.c **** } + 289 .loc 1 242 1 is_stmt 0 view .LVU40 + 290 0018 08BD pop {r3, pc} + 291 .L23: + 236:Src/stm32f7xx_it.c **** TIM10_coflag = 1; + 292 .loc 1 236 3 is_stmt 1 view .LVU41 + 236:Src/stm32f7xx_it.c **** TIM10_coflag = 1; + 293 .loc 1 236 16 is_stmt 0 view .LVU42 + 294 001a 054B ldr r3, .L24+12 + 295 001c 0122 movs r2, #1 + 296 001e 1A70 strb r2, [r3] + 297 0020 F7E7 b .L21 + 298 .L25: + 299 0022 00BF .align 2 + 300 .L24: + 301 0024 00000000 .word TO10 + 302 0028 00000000 .word TO10_counter + 303 002c 00000000 .word htim10 + 304 0030 00000000 .word TIM10_coflag + 305 .cfi_endproc + 306 .LFE1193: + 308 .section .text.TIM1_TRG_COM_TIM11_IRQHandler,"ax",%progbits + 309 .align 1 + 310 .global TIM1_TRG_COM_TIM11_IRQHandler + 311 .syntax unified + 312 .thumb + 313 .thumb_func + 315 TIM1_TRG_COM_TIM11_IRQHandler: + 316 .LFB1194: + 243:Src/stm32f7xx_it.c **** + 244:Src/stm32f7xx_it.c **** /** + 245:Src/stm32f7xx_it.c **** * @brief This function handles TIM1 trigger and commutation interrupts and TIM11 global interrupt + 246:Src/stm32f7xx_it.c **** */ + 247:Src/stm32f7xx_it.c **** void TIM1_TRG_COM_TIM11_IRQHandler(void) + 248:Src/stm32f7xx_it.c **** { + 317 .loc 1 248 1 is_stmt 1 view -0 + 318 .cfi_startproc + 319 @ args = 0, pretend = 0, frame = 0 + 320 @ frame_needed = 0, uses_anonymous_args = 0 + 321 0000 08B5 push {r3, lr} + 322 .LCFI3: + 323 .cfi_def_cfa_offset 8 + 324 .cfi_offset 3, -8 + 325 .cfi_offset 14, -4 + 249:Src/stm32f7xx_it.c **** /* USER CODE BEGIN TIM1_TRG_COM_TIM11_IRQn 0 */ + 250:Src/stm32f7xx_it.c **** TIM11 -> CR1 |= 1 << 3; //sets timer to one-pulse mode. So it will turn off at the next UpdateEven + 326 .loc 1 250 2 view .LVU44 + 327 .loc 1 250 8 is_stmt 0 view .LVU45 + 328 0002 094B ldr r3, .L28 + 329 0004 1A68 ldr r2, [r3] + 330 .loc 1 250 15 view .LVU46 + 331 0006 42F00802 orr r2, r2, #8 + 332 000a 1A60 str r2, [r3] + 251:Src/stm32f7xx_it.c **** TIM4 -> CR1 |= 1 << 3; //sets timer to one-pulse mode. So it will turn off at the next UpdateEvent + 333 .loc 1 251 2 is_stmt 1 view .LVU47 + 334 .loc 1 251 7 is_stmt 0 view .LVU48 + 335 000c 0749 ldr r1, .L28+4 + ARM GAS /tmp/ccvzubVv.s page 11 + + + 336 000e 0A68 ldr r2, [r1] + 337 .loc 1 251 14 view .LVU49 + 338 0010 42F00802 orr r2, r2, #8 + 339 0014 0A60 str r2, [r1] + 252:Src/stm32f7xx_it.c **** TIM11 -> DIER &= ~(1); //disable interrupt + 340 .loc 1 252 2 is_stmt 1 view .LVU50 + 341 .loc 1 252 8 is_stmt 0 view .LVU51 + 342 0016 DA68 ldr r2, [r3, #12] + 343 .loc 1 252 16 view .LVU52 + 344 0018 22F00102 bic r2, r2, #1 + 345 001c DA60 str r2, [r3, #12] + 253:Src/stm32f7xx_it.c **** /* USER CODE END TIM1_TRG_COM_TIM11_IRQn 0 */ + 254:Src/stm32f7xx_it.c **** HAL_TIM_IRQHandler(&htim11); + 346 .loc 1 254 3 is_stmt 1 view .LVU53 + 347 001e 0448 ldr r0, .L28+8 + 348 0020 FFF7FEFF bl HAL_TIM_IRQHandler + 349 .LVL4: + 255:Src/stm32f7xx_it.c **** /* USER CODE BEGIN TIM1_TRG_COM_TIM11_IRQn 1 */ + 256:Src/stm32f7xx_it.c **** + 257:Src/stm32f7xx_it.c **** /* USER CODE END TIM1_TRG_COM_TIM11_IRQn 1 */ + 258:Src/stm32f7xx_it.c **** } + 350 .loc 1 258 1 is_stmt 0 view .LVU54 + 351 0024 08BD pop {r3, pc} + 352 .L29: + 353 0026 00BF .align 2 + 354 .L28: + 355 0028 00480140 .word 1073825792 + 356 002c 00080040 .word 1073743872 + 357 0030 00000000 .word htim11 + 358 .cfi_endproc + 359 .LFE1194: + 361 .section .text.TIM2_IRQHandler,"ax",%progbits + 362 .align 1 + 363 .global TIM2_IRQHandler + 364 .syntax unified + 365 .thumb + 366 .thumb_func + 368 TIM2_IRQHandler: + 369 .LFB1195: + 259:Src/stm32f7xx_it.c **** + 260:Src/stm32f7xx_it.c **** /** + 261:Src/stm32f7xx_it.c **** * @brief This function handles TIM2 global interrupt. + 262:Src/stm32f7xx_it.c **** */ + 263:Src/stm32f7xx_it.c **** void TIM2_IRQHandler(void) + 264:Src/stm32f7xx_it.c **** { + 370 .loc 1 264 1 is_stmt 1 view -0 + 371 .cfi_startproc + 372 @ args = 0, pretend = 0, frame = 0 + 373 @ frame_needed = 0, uses_anonymous_args = 0 + 374 @ link register save eliminated. + 265:Src/stm32f7xx_it.c **** /* USER CODE BEGIN TIM2_IRQn 0 */ + 266:Src/stm32f7xx_it.c **** + 267:Src/stm32f7xx_it.c **** /* USER CODE END TIM2_IRQn 0 */ + 268:Src/stm32f7xx_it.c **** /* USER CODE BEGIN TIM2_IRQn 1 */ + 269:Src/stm32f7xx_it.c **** + 270:Src/stm32f7xx_it.c **** /* USER CODE END TIM2_IRQn 1 */ + 271:Src/stm32f7xx_it.c **** } + ARM GAS /tmp/ccvzubVv.s page 12 + + + 375 .loc 1 271 1 view .LVU56 + 376 0000 7047 bx lr + 377 .cfi_endproc + 378 .LFE1195: + 380 .section .text.TIM8_UP_TIM13_IRQHandler,"ax",%progbits + 381 .align 1 + 382 .global TIM8_UP_TIM13_IRQHandler + 383 .syntax unified + 384 .thumb + 385 .thumb_func + 387 TIM8_UP_TIM13_IRQHandler: + 388 .LFB1197: + 272:Src/stm32f7xx_it.c **** + 273:Src/stm32f7xx_it.c **** /** + 274:Src/stm32f7xx_it.c **** * @brief This function handles USART1 global interrupt. + 275:Src/stm32f7xx_it.c **** */ + 276:Src/stm32f7xx_it.c **** void USART1_IRQHandler(void) + 277:Src/stm32f7xx_it.c **** { + 278:Src/stm32f7xx_it.c **** /* USER CODE BEGIN USART1_IRQn 0 */ + 279:Src/stm32f7xx_it.c **** volatile uint8_t temp; + 280:Src/stm32f7xx_it.c **** if(LL_USART_IsActiveFlag_RXNE(USART1) && LL_USART_IsEnabledIT_RXNE(USART1)) + 281:Src/stm32f7xx_it.c **** { + 282:Src/stm32f7xx_it.c **** UART_RxCpltCallback(); + 283:Src/stm32f7xx_it.c **** } + 284:Src/stm32f7xx_it.c **** else + 285:Src/stm32f7xx_it.c **** { + 286:Src/stm32f7xx_it.c **** if(LL_USART_IsActiveFlag_ORE(USART1)) + 287:Src/stm32f7xx_it.c **** { + 288:Src/stm32f7xx_it.c **** //temp = USART1->RDR; + 289:Src/stm32f7xx_it.c **** temp+= LL_USART_ReceiveData8(USART1); + 290:Src/stm32f7xx_it.c **** } + 291:Src/stm32f7xx_it.c **** else if(LL_USART_IsActiveFlag_FE(USART1)) + 292:Src/stm32f7xx_it.c **** { + 293:Src/stm32f7xx_it.c **** //(void) USART1->RDR; + 294:Src/stm32f7xx_it.c **** temp+= LL_USART_ReceiveData8(USART1); + 295:Src/stm32f7xx_it.c **** } + 296:Src/stm32f7xx_it.c **** else if(LL_USART_IsActiveFlag_NE(USART1)) + 297:Src/stm32f7xx_it.c **** { + 298:Src/stm32f7xx_it.c **** //(void) USART1->RDR; + 299:Src/stm32f7xx_it.c **** temp+= LL_USART_ReceiveData8(USART1); + 300:Src/stm32f7xx_it.c **** } + 301:Src/stm32f7xx_it.c **** else if(LL_USART_IsActiveFlag_PE(USART1)) + 302:Src/stm32f7xx_it.c **** { + 303:Src/stm32f7xx_it.c **** //(void) USART1->RDR; + 304:Src/stm32f7xx_it.c **** temp+= LL_USART_ReceiveData8(USART1); + 305:Src/stm32f7xx_it.c **** } + 306:Src/stm32f7xx_it.c **** else + 307:Src/stm32f7xx_it.c **** { + 308:Src/stm32f7xx_it.c **** if(LL_USART_IsActiveFlag_TC(USART6) && LL_USART_IsEnabledIT_TC(USART6)) + 309:Src/stm32f7xx_it.c **** { + 310:Src/stm32f7xx_it.c **** LL_USART_ClearFlag_TC(USART1); + 311:Src/stm32f7xx_it.c **** //test_counter += 1; + 312:Src/stm32f7xx_it.c **** //if(UART_transmission_busy == 1){ + 313:Src/stm32f7xx_it.c **** LL_USART_DisableIT_TC(USART1); + 314:Src/stm32f7xx_it.c **** //UART_transmission_busy = 0; + 315:Src/stm32f7xx_it.c **** } + 316:Src/stm32f7xx_it.c **** } + ARM GAS /tmp/ccvzubVv.s page 13 + + + 317:Src/stm32f7xx_it.c **** } + 318:Src/stm32f7xx_it.c **** + 319:Src/stm32f7xx_it.c **** /* USER CODE END USART1_IRQn 0 */ + 320:Src/stm32f7xx_it.c **** /* USER CODE BEGIN USART1_IRQn 1 */ + 321:Src/stm32f7xx_it.c **** + 322:Src/stm32f7xx_it.c **** /* USER CODE END USART1_IRQn 1 */ + 323:Src/stm32f7xx_it.c **** } + 324:Src/stm32f7xx_it.c **** + 325:Src/stm32f7xx_it.c **** /** + 326:Src/stm32f7xx_it.c **** * @brief This function handles TIM8 update interrupt and TIM13 global interrupt. + 327:Src/stm32f7xx_it.c **** */ + 328:Src/stm32f7xx_it.c **** void TIM8_UP_TIM13_IRQHandler(void) + 329:Src/stm32f7xx_it.c **** { + 389 .loc 1 329 1 view -0 + 390 .cfi_startproc + 391 @ args = 0, pretend = 0, frame = 0 + 392 @ frame_needed = 0, uses_anonymous_args = 0 + 393 0000 10B5 push {r4, lr} + 394 .LCFI4: + 395 .cfi_def_cfa_offset 8 + 396 .cfi_offset 4, -8 + 397 .cfi_offset 14, -4 + 330:Src/stm32f7xx_it.c **** /* USER CODE BEGIN TIM8_UP_TIM13_IRQn 0 */ + 331:Src/stm32f7xx_it.c **** // HAL_GPIO_TogglePin(LD_blinker.signal_port, LD_blinker.signal_pin); + 332:Src/stm32f7xx_it.c **** //HAL_GPIO_TogglePin(OUT_11_GPIO_Port, OUT_11_Pin); + 333:Src/stm32f7xx_it.c **** //* + 334:Src/stm32f7xx_it.c **** switch (LD_blinker.state) { + 398 .loc 1 334 2 view .LVU58 + 399 .loc 1 334 20 is_stmt 0 view .LVU59 + 400 0002 114B ldr r3, .L36 + 401 0004 9B7A ldrb r3, [r3, #10] @ zero_extendqisi2 + 402 .loc 1 334 2 view .LVU60 + 403 0006 022B cmp r3, #2 + 404 0008 0ED0 beq .L32 + 405 000a 032B cmp r3, #3 + 406 000c 18D1 bne .L34 + 335:Src/stm32f7xx_it.c **** case 0: //no LD update required + 336:Src/stm32f7xx_it.c **** break; + 337:Src/stm32f7xx_it.c **** case 1: //LD ON, need update + 338:Src/stm32f7xx_it.c **** //Set_LTEC(LD_blinker.task_type , LD_blinker.param); + 339:Src/stm32f7xx_it.c **** //LD_blinker.state = 0; + 340:Src/stm32f7xx_it.c **** break; + 341:Src/stm32f7xx_it.c **** case 2: //set LD ON, blinking + 342:Src/stm32f7xx_it.c **** //Set_LTEC(TT_CHANGE_CURR_2, task.current_param); + 343:Src/stm32f7xx_it.c **** Set_LTEC(2 , LD_blinker.param); + 344:Src/stm32f7xx_it.c **** HAL_GPIO_WritePin(LD_blinker.signal_port, LD_blinker.signal_pin, GPIO_PIN_SET); + 345:Src/stm32f7xx_it.c **** LD_blinker.state = 3; + 346:Src/stm32f7xx_it.c **** break; + 347:Src/stm32f7xx_it.c **** case 3: //set LD OFF, blinking + 348:Src/stm32f7xx_it.c **** Set_LTEC(2 , 0); + 407 .loc 1 348 4 is_stmt 1 view .LVU61 + 408 000e 0021 movs r1, #0 + 409 0010 0220 movs r0, #2 + 410 0012 FFF7FEFF bl Set_LTEC + 411 .LVL5: + 349:Src/stm32f7xx_it.c **** HAL_GPIO_WritePin(LD_blinker.signal_port, LD_blinker.signal_pin, GPIO_PIN_RESET); + 412 .loc 1 349 4 view .LVU62 + ARM GAS /tmp/ccvzubVv.s page 14 + + + 413 0016 0C4C ldr r4, .L36 + 414 0018 0022 movs r2, #0 + 415 001a 6188 ldrh r1, [r4, #2] + 416 001c 6068 ldr r0, [r4, #4] + 417 001e FFF7FEFF bl HAL_GPIO_WritePin + 418 .LVL6: + 350:Src/stm32f7xx_it.c **** LD_blinker.state = 2; + 419 .loc 1 350 4 view .LVU63 + 420 .loc 1 350 21 is_stmt 0 view .LVU64 + 421 0022 0223 movs r3, #2 + 422 0024 A372 strb r3, [r4, #10] + 351:Src/stm32f7xx_it.c **** break; + 423 .loc 1 351 3 is_stmt 1 view .LVU65 + 424 0026 0BE0 b .L34 + 425 .L32: + 343:Src/stm32f7xx_it.c **** HAL_GPIO_WritePin(LD_blinker.signal_port, LD_blinker.signal_pin, GPIO_PIN_SET); + 426 .loc 1 343 4 view .LVU66 + 427 0028 074C ldr r4, .L36 + 428 002a 2189 ldrh r1, [r4, #8] + 429 002c 0220 movs r0, #2 + 430 002e FFF7FEFF bl Set_LTEC + 431 .LVL7: + 344:Src/stm32f7xx_it.c **** LD_blinker.state = 3; + 432 .loc 1 344 4 view .LVU67 + 433 0032 0122 movs r2, #1 + 434 0034 6188 ldrh r1, [r4, #2] + 435 0036 6068 ldr r0, [r4, #4] + 436 0038 FFF7FEFF bl HAL_GPIO_WritePin + 437 .LVL8: + 345:Src/stm32f7xx_it.c **** break; + 438 .loc 1 345 4 view .LVU68 + 345:Src/stm32f7xx_it.c **** break; + 439 .loc 1 345 21 is_stmt 0 view .LVU69 + 440 003c 0323 movs r3, #3 + 441 003e A372 strb r3, [r4, #10] + 346:Src/stm32f7xx_it.c **** case 3: //set LD OFF, blinking + 442 .loc 1 346 3 is_stmt 1 view .LVU70 + 443 .L34: + 352:Src/stm32f7xx_it.c **** } + 353:Src/stm32f7xx_it.c **** //*/ + 354:Src/stm32f7xx_it.c **** /* USER CODE END TIM8_UP_TIM13_IRQn 0 */ + 355:Src/stm32f7xx_it.c **** HAL_TIM_IRQHandler(&htim8); + 444 .loc 1 355 3 view .LVU71 + 445 0040 0248 ldr r0, .L36+4 + 446 0042 FFF7FEFF bl HAL_TIM_IRQHandler + 447 .LVL9: + 356:Src/stm32f7xx_it.c **** /* USER CODE BEGIN TIM8_UP_TIM13_IRQn 1 */ + 357:Src/stm32f7xx_it.c **** + 358:Src/stm32f7xx_it.c **** /* USER CODE END TIM8_UP_TIM13_IRQn 1 */ + 359:Src/stm32f7xx_it.c **** } + 448 .loc 1 359 1 is_stmt 0 view .LVU72 + 449 0046 10BD pop {r4, pc} + 450 .L37: + 451 .align 2 + 452 .L36: + 453 0048 00000000 .word LD_blinker + 454 004c 00000000 .word htim8 + ARM GAS /tmp/ccvzubVv.s page 15 + + + 455 .cfi_endproc + 456 .LFE1197: + 458 .section .text.TIM5_IRQHandler,"ax",%progbits + 459 .align 1 + 460 .global TIM5_IRQHandler + 461 .syntax unified + 462 .thumb + 463 .thumb_func + 465 TIM5_IRQHandler: + 466 .LFB1198: + 360:Src/stm32f7xx_it.c **** + 361:Src/stm32f7xx_it.c **** /** + 362:Src/stm32f7xx_it.c **** * @brief This function handles TIM5 global interrupt. + 363:Src/stm32f7xx_it.c **** */ + 364:Src/stm32f7xx_it.c **** void TIM5_IRQHandler(void) + 365:Src/stm32f7xx_it.c **** { + 467 .loc 1 365 1 is_stmt 1 view -0 + 468 .cfi_startproc + 469 @ args = 0, pretend = 0, frame = 0 + 470 @ frame_needed = 0, uses_anonymous_args = 0 + 471 @ link register save eliminated. + 366:Src/stm32f7xx_it.c **** /* USER CODE BEGIN TIM5_IRQn 0 */ + 367:Src/stm32f7xx_it.c **** + 368:Src/stm32f7xx_it.c **** /* USER CODE END TIM5_IRQn 0 */ + 369:Src/stm32f7xx_it.c **** /* USER CODE BEGIN TIM5_IRQn 1 */ + 370:Src/stm32f7xx_it.c **** + 371:Src/stm32f7xx_it.c **** /* USER CODE END TIM5_IRQn 1 */ + 372:Src/stm32f7xx_it.c **** } + 472 .loc 1 372 1 view .LVU74 + 473 0000 7047 bx lr + 474 .cfi_endproc + 475 .LFE1198: + 477 .section .text.TIM6_DAC_IRQHandler,"ax",%progbits + 478 .align 1 + 479 .global TIM6_DAC_IRQHandler + 480 .syntax unified + 481 .thumb + 482 .thumb_func + 484 TIM6_DAC_IRQHandler: + 485 .LFB1199: + 373:Src/stm32f7xx_it.c **** + 374:Src/stm32f7xx_it.c **** /** + 375:Src/stm32f7xx_it.c **** * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts. + 376:Src/stm32f7xx_it.c **** */ + 377:Src/stm32f7xx_it.c **** void TIM6_DAC_IRQHandler(void) + 378:Src/stm32f7xx_it.c **** { + 486 .loc 1 378 1 view -0 + 487 .cfi_startproc + 488 @ args = 0, pretend = 0, frame = 0 + 489 @ frame_needed = 0, uses_anonymous_args = 0 + 490 0000 08B5 push {r3, lr} + 491 .LCFI5: + 492 .cfi_def_cfa_offset 8 + 493 .cfi_offset 3, -8 + 494 .cfi_offset 14, -4 + 379:Src/stm32f7xx_it.c **** /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ + 380:Src/stm32f7xx_it.c **** + ARM GAS /tmp/ccvzubVv.s page 16 + + + 381:Src/stm32f7xx_it.c **** /* USER CODE END TIM6_DAC_IRQn 0 */ + 382:Src/stm32f7xx_it.c **** /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ + 383:Src/stm32f7xx_it.c **** if(LL_TIM_IsActiveFlag_UPDATE(TIM6)) + 495 .loc 1 383 3 view .LVU76 + 496 .LVL10: + 497 .LBB58: + 498 .LBI58: + 499 .file 2 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @file stm32f7xx_ll_tim.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Header file of TIM LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * This software is licensed under terms that can be found in the LICENSE file + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifndef __STM32F7xx_LL_TIM_H + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __STM32F7xx_LL_TIM_H + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifdef __cplusplus + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** extern "C" { + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Includes ------------------------------------------------------------------*/ + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #include "stm32f7xx.h" + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @addtogroup STM32F7xx_LL_Driver + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defi + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL TIM + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private types -------------------------------------------------------------*/ + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private variables ---------------------------------------------------------*/ + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Variables TIM Private Variables + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t OFFSET_TAB_CCMRx[] = + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 0: TIMx_CH1 */ + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 1: TIMx_CH1N */ + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 2: TIMx_CH2 */ + ARM GAS /tmp/ccvzubVv.s page 17 + + + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 3: TIMx_CH2N */ + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 4: TIMx_CH3 */ + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 5: TIMx_CH3N */ + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 6: TIMx_CH4 */ + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x3CU, /* 7: TIMx_CH5 */ + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x3CU /* 8: TIMx_CH6 */ + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OCxx[] = + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: OC1M, OC1FE, OC1PE */ + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 1: - NA */ + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 2: OC2M, OC2FE, OC2PE */ + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 3: - NA */ + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 4: OC3M, OC3FE, OC3PE */ + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 5: - NA */ + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 6: OC4M, OC4FE, OC4PE */ + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 7: OC5M, OC5FE, OC5PE */ + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U /* 8: OC6M, OC6FE, OC6PE */ + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_ICxx[] = + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: CC1S, IC1PSC, IC1F */ + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 1: - NA */ + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 2: CC2S, IC2PSC, IC2F */ + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 3: - NA */ + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 4: CC3S, IC3PSC, IC3F */ + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 5: - NA */ + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 6: CC4S, IC4PSC, IC4F */ + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 7: - NA */ + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U /* 8: - NA */ + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_CCxP[] = + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: CC1P */ + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2U, /* 1: CC1NP */ + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4U, /* 2: CC2P */ + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 6U, /* 3: CC2NP */ + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 4: CC3P */ + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 10U, /* 5: CC3NP */ + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 12U, /* 6: CC4P */ + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 16U, /* 7: CC5P */ + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 20U /* 8: CC6P */ + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OISx[] = + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: OIS1 */ + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1U, /* 1: OIS1N */ + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2U, /* 2: OIS2 */ + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3U, /* 3: OIS2N */ + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4U, /* 4: OIS3 */ + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 5U, /* 5: OIS3N */ + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 6U, /* 6: OIS4 */ + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 7: OIS5 */ + ARM GAS /tmp/ccvzubVv.s page 18 + + + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 10U /* 8: OIS6 */ + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private constants ---------------------------------------------------------*/ + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Constants TIM Private Constants + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(TIM_BREAK_INPUT_SUPPORT) + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Defines used for the bit position in the register and perform offsets */ + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Generic bit definitions for TIMx_AF1 register */ + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */ + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Remap mask definitions */ + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_SHIFT 16U + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_MASK 0x0000FFFFU + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT) + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM5_OR_RMP_MASK (TIM5_OR_TI4_RMP << TIMx_OR_RMP_SHIFT) + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM11_OR_RMP_MASK (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_1 ((uint8_t)0x7F) + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_2 ((uint8_t)0x3F) + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_3 ((uint8_t)0x1F) + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_4 ((uint8_t)0x1F) + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_1 ((uint8_t)0x00) + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_2 ((uint8_t)0x80) + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_3 ((uint8_t)0xC0) + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_4 ((uint8_t)0xE0) + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private macros ------------------------------------------------------------*/ + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Macros TIM Private Macros + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief Convert channel id into channel index. + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CHANNEL__ This parameter can be one of the following values: + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 + ARM GAS /tmp/ccvzubVv.s page 19 + + + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval none + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief Calculate the deadtime sampling period(in ps). + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz). + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CKD__ This parameter can be one of the following values: + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval none + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported types ------------------------------------------------------------*/ + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Time Base configuration structure definition. + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data=0x0000 and Max_D + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetPrescaler().*/ + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CounterMode; /*!< Specifies the counter mode. + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetCounterMode().*/ + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Auto-Reload Register at the next update event. + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter must be a number between Min_Data=0x0000 and Max_ + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Some timer instances may support 32 bits counters. In that case + ARM GAS /tmp/ccvzubVv.s page 20 + + + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** be a number between 0x0000 and 0xFFFFFFFF. + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetAutoReload().*/ + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ClockDivision; /*!< Specifies the clock division. + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetClockDivision().*/ + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downc + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** reaches zero, an update event is generated and counting restarts + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** from the RCR value (N). + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This means in PWM mode that (N+1) corresponds to: + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** - the number of PWM periods in edge-aligned mode + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** - the number of half PWM period in center-aligned mode + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** GP timers: this parameter must be a number between Min_Data = 0x + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Max_Data = 0xFF. + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Advanced timers: this parameter must be a number between Min_Dat + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Max_Data = 0xFFFF. + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetRepetitionCounter().*/ + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_InitTypeDef; + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Output Compare configuration structure definition. + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCMode; /*!< Specifies the output mode. + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCMODE. + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetMode().*/ + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCState; /*!< Specifies the TIM Output Compare state. + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functions + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functions + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Re + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data=0x0000 and Max_Data= + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** LL_TIM_OC_SetCompareCHx (x=1..6).*/ + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCPolarity; /*!< Specifies the output polarity. + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + ARM GAS /tmp/ccvzubVv.s page 21 + + + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetPolarity().*/ + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetPolarity().*/ + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetIdleState().*/ + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetIdleState().*/ + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_OC_InitTypeDef; + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Input Capture configuration structure definition. + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICActiveInput; /*!< Specifies the input. + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICFilter; /*!< Specifies the input capture filter. + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_IC_InitTypeDef; + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + ARM GAS /tmp/ccvzubVv.s page 22 + + + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Encoder interface configuration structure definition. + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetEncoderMode().*/ + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Filter; /*!< Specifies the TI2 input filter. + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + ARM GAS /tmp/ccvzubVv.s page 23 + + + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_ENCODER_InitTypeDef; + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Hall sensor interface configuration structure definition. + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Prescaler must be set to get a maximum counter period longer th + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** time interval between 2 consecutive changes on the Hall inputs. + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref TIM_LL_EC_IC_FILTER. + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compa + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** A positive pulse (TRGO event) is generated with a programmable + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** a change occurs on the Hall inputs. + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data = 0x0000 and Ma + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetCompareCH2().*/ + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_HALLSENSOR_InitTypeDef; + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief BDTR (Break and Dead Time) structure definition + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OSSR + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetOffStates() + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field cannot be modified as long as LOCK level + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OSSI + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + ARM GAS /tmp/ccvzubVv.s page 24 + + + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetOffStates() + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field cannot be modified as long as LOCK level + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t LockLevel; /*!< Specifies the LOCK level parameters. + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note The LOCK bits can be written only once after the reset. + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** register has been written, their content is frozen until the + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** switching-on of the outputs. + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data = 0x00 and Ma + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetDeadTime() + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARIT + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK() + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK() + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + ARM GAS /tmp/ccvzubVv.s page 25 + + + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARI + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK2() + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK2() + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTP + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAut + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_BDTR_InitTypeDef; + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported constants --------------------------------------------------------*/ + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Flags defines which can be used with LL_TIM_ReadReg function. + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrup + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrup + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrup + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrup + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrup + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrup + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt fla + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapt + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapt + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapt + ARM GAS /tmp/ccvzubVv.s page 26 + + + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapt + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt fla + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by softw + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_IT IT Defines + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrup + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrup + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrup + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrup + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable * + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/unde + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + ARM GAS /tmp/ccvzubVv.s page 27 + + + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounte + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and + 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and + 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and + 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division + 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ + 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ + 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction + 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ + 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down + 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bi + 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bi + 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request + 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when + 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when + ARM GAS /tmp/ccvzubVv.s page 28 + + + 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level + 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write + 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ + 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ + 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ + 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CHANNEL Channel + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 + 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output ch + 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 + 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output ch + 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 + 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output ch + 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 + 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ + 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ + 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) + 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State + 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ + 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on + 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ + 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** Legacy definitions for compatibility purpose + 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @cond 0 + 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1 + 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2 + 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @endcond + 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode + 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FROZEN 0x00000000U + 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 + 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 + ARM GAS /tmp/ccvzubVv.s page 29 + + + 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) + 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 + 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) + 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) + 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1 + 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) + 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) + 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1 + 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1 + 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) + 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity + 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ + 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ + 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State + 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!__REG__, (__VAL +1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Read a value in TIM register. +1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __INSTANCE__ TIM Instance +1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __REG__ Register to be read + ARM GAS /tmp/ccvzubVv.s page 37 + + +1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Register value +1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro retrieving the UIFCPY flag from the counter value. +1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); +1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied +1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * to TIMx_CNT register bit 31) +1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CNT__ Counter value +1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval UIF status bit +1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ +1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) +1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested de +1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); +1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) +1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CKD__ This parameter can be one of the following values: +1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 +1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 +1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 +1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DT__ deadtime duration (in ns) +1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval DTG[0:7] +1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ +1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? +1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : +1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__C +1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMC +1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) +1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__C +1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC +1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) +1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__ +1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC +1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) +1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U) +1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the prescaler value to achieve the required counter clock freq +1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); +1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) +1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CNTCLK__ counter clock frequency (in Hz) +1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) +1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ +1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U +1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal fr +1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); +1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) + ARM GAS /tmp/ccvzubVv.s page 38 + + +1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler +1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __FREQ__ output signal frequency (in Hz) +1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) +1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ +1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) +1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the compare value required to achieve the required timer outpu +1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * active/inactive delay. +1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); +1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) +1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler +1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DELAY__ timer output compare active/inactive delay (in us) +1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Compare value (between Min_Data=0 and Max_Data=65535) +1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ +1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ +1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) +1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration +1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (when the timer operates in one pulse mode). +1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); +1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) +1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler +1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DELAY__ timer output compare active/inactive delay (in us) +1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PULSE__ pulse duration (in us) +1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) +1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ +1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ +1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) +1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro retrieving the ratio of the input capture prescaler +1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); +1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __ICPSC__ This parameter can be one of the following values: +1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 +1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 +1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 +1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 +1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Input capture prescaler ratio (1, 2, 4 or 8) +1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ +1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) +1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported functions --------------------------------------------------------*/ +1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions +1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + ARM GAS /tmp/ccvzubVv.s page 39 + + +1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Time_Base Time Base configuration +1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable timer counter. +1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_EnableCounter +1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) +1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_CEN); +1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable timer counter. +1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_DisableCounter +1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) +1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); +1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the timer counter is enabled. +1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter +1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) +1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); +1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable update event generation. +1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent +1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) +1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); +1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable update event generation. +1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent +1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) +1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_UDIS); +1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + ARM GAS /tmp/ccvzubVv.s page 40 + + +1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether update event generation is enabled. +1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent +1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Inverted state of bit (0 or 1). +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); +1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set update event source +1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * generate an update interrupt or DMA request if enabled: +1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Counter overflow/underflow +1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Setting the UG bit +1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Update generation through the slave mode controller +1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter +1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * overflow/underflow generates an update interrupt or DMA request if enabled. +1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 URS LL_TIM_SetUpdateSource +1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param UpdateSource This parameter can be one of the following values: +1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_REGULAR +1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_COUNTER +1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) +1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); +1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual event update source +1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 URS LL_TIM_GetUpdateSource +1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_REGULAR +1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_COUNTER +1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) +1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); +1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set one pulse mode (one shot v.s. repetitive). +1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode +1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OnePulseMode This parameter can be one of the following values: +1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE +1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE +1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) +1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + ARM GAS /tmp/ccvzubVv.s page 41 + + +1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); +1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual one pulse mode. +1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode +1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE +1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE +1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) +1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); +1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the timer counter counting mode. +1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to +1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * check whether or not the counter mode selection feature is supported +1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * by a timer instance. +1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) +1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * requires a timer reset to avoid unexpected direction +1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * due to DIR bit readonly in center aligned mode. +1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n +1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR1 CMS LL_TIM_SetCounterMode +1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CounterMode This parameter can be one of the following values: +1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_UP +1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_DOWN +1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP +1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN +1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN +1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) +1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); +1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual counter mode. +1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to +1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * check whether or not the counter mode selection feature is supported +1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * by a timer instance. +1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n +1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR1 CMS LL_TIM_GetCounterMode +1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_UP +1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_DOWN +1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP +1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN +1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN +1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) +1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + ARM GAS /tmp/ccvzubVv.s page 42 + + +1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t counter_mode; +1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); +1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** if (counter_mode == 0U) +1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return counter_mode; +1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable auto-reload (ARR) preload. +1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload +1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) +1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_ARPE); +1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable auto-reload (ARR) preload. +1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload +1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) +1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); +1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether auto-reload (ARR) preload is enabled. +1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload +1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) +1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); +1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the division ratio between the timer clock and the sampling clock used by the dead +1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (when supported) and the digital filters. +1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check +1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not the clock division feature is supported by the timer +1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * instance. +1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CKD LL_TIM_SetClockDivision +1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ClockDivision This parameter can be one of the following values: +1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 +1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 +1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + ARM GAS /tmp/ccvzubVv.s page 43 + + +1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) +1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); +1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the actual division ratio between the timer clock and the sampling clock used by t +1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * generators (when supported) and the digital filters. +1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check +1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not the clock division feature is supported by the timer +1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * instance. +1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CKD LL_TIM_GetClockDivision +1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 +1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 +1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 +1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) +1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); +1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the counter value. +1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CNT CNT LL_TIM_SetCounter +1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) +1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CNT, Counter); +1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the counter value. +1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CNT CNT LL_TIM_GetCounter +1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) +1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) +1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CNT)); +1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current direction of the counter +1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_GetDirection +1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: + ARM GAS /tmp/ccvzubVv.s page 44 + + +1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERDIRECTION_UP +1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN +1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) +1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the prescaler value. +1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). +1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The prescaler can be changed on the fly as this control register is buffered. The new +1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * prescaler ratio is taken into account at the next update event. +1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter +1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll PSC PSC LL_TIM_SetPrescaler +1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Prescaler between Min_Data=0 and Max_Data=65535 +1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) +1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->PSC, Prescaler); +1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the prescaler value. +1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll PSC PSC LL_TIM_GetPrescaler +1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Prescaler value between Min_Data=0 and Max_Data=65535 +1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) +1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->PSC)); +1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the auto-reload value. +1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The counter is blocked while the auto-reload value is null. +1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter +1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll ARR ARR LL_TIM_SetAutoReload +1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param AutoReload between Min_Data=0 and Max_Data=65535 +1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) +1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->ARR, AutoReload); +1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the auto-reload value. +1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll ARR ARR LL_TIM_GetAutoReload +1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance + ARM GAS /tmp/ccvzubVv.s page 45 + + +1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value +1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) +1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->ARR)); +1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the repetition counter value. +1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note For advanced timer instances RepetitionCounter can be up to 65535. +1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check +1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a repetition counter. +1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll RCR REP LL_TIM_SetRepetitionCounter +1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. +1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) +1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->RCR, RepetitionCounter); +1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the repetition counter value. +1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check +1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a repetition counter. +1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll RCR REP LL_TIM_GetRepetitionCounter +1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Repetition counter value +1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) +1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->RCR)); +1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter regis +1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This allows both the counter value and a potential roll-over condition signalled by the U +1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in an atomic way. +1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap +1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) +1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable update interrupt flag (UIF) remapping. +1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap +1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) +1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); + ARM GAS /tmp/ccvzubVv.s page 46 + + +1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether update interrupt flag (UIF) copy is set. +1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Counter Counter value +1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) +1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); +1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration +1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. +1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, +1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * they are updated only when a commutation event (COM) occurs. +1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Only on channels that have a complementary output. +1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check +1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. +1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload +1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) +1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR2, TIM_CR2_CCPC); +1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. +1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check +1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. +1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload +1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) +1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); +1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is en +1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload +1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); + ARM GAS /tmp/ccvzubVv.s page 47 + + +1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). +1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check +1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. +1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate +1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CCUpdateSource This parameter can be one of the following values: +1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI +1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) +1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); +1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger of the capture/compare DMA request. +1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger +1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMAReqTrigger This parameter can be one of the following values: +1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_CC +1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE +1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) +1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); +1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual trigger of the capture/compare DMA request. +1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger +1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_CC +1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE +1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) +1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); +1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the lock level to freeze the +1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * configuration of several capture/compare parameters. +1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the lock mechanism is supported by a timer instance. +1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel +1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param LockLevel This parameter can be one of the following values: +1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_OFF +1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_1 +1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_2 +1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_3 + ARM GAS /tmp/ccvzubVv.s page 48 + + +1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) +1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); +1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable capture/compare channels. +1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_EnableChannel\n +1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_EnableChannel\n +1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_EnableChannel\n +1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_EnableChannel\n +1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_EnableChannel\n +1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_EnableChannel\n +1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_EnableChannel\n +1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_EnableChannel +1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: +1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CCER, Channels); +1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable capture/compare channels. +1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n +1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_DisableChannel\n +1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_DisableChannel\n +1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_DisableChannel\n +1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_DisableChannel\n +1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_DisableChannel\n +1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_DisableChannel\n +1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_DisableChannel\n +1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_DisableChannel +1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: +1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 + ARM GAS /tmp/ccvzubVv.s page 49 + + +1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CCER, Channels); +1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether channel(s) is(are) enabled. +1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n +1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n +1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_IsEnabledChannel\n +1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n +1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_IsEnabledChannel\n +1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n +1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_IsEnabledChannel\n +1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_IsEnabledChannel\n +1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_IsEnabledChannel +1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: +1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) +1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); +1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration +1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure an output channel. +1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n +1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n +1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n +1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n +1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n +1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n +1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1P LL_TIM_OC_ConfigOutput\n +1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_ConfigOutput\n +1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_ConfigOutput\n +1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_ConfigOutput\n +1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_ConfigOutput\n + ARM GAS /tmp/ccvzubVv.s page 50 + + +1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_ConfigOutput\n +1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS1 LL_TIM_OC_ConfigOutput\n +1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_ConfigOutput\n +1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_ConfigOutput\n +1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_ConfigOutput\n +1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_ConfigOutput\n +1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_ConfigOutput +1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Configuration This parameter must be a combination of all the following values: +1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW +1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH +1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configura +1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); +1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), +1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); +1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), +1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); +1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Define the behavior of the output reference signal OCxREF from which +1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * OCx and OCxN (when relevant) are derived. +1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n +1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2M LL_TIM_OC_SetMode\n +1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3M LL_TIM_OC_SetMode\n +1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4M LL_TIM_OC_SetMode\n +1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5M LL_TIM_OC_SetMode\n +1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6M LL_TIM_OC_SetMode +1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Mode This parameter can be one of the following values: +1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FROZEN +1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ACTIVE +1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_INACTIVE +1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_TOGGLE +1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE +1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE +1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM1 +1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM2 + ARM GAS /tmp/ccvzubVv.s page 51 + + +1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 +1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 +1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 +1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 +1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 +1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 +1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) +1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT +2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the output compare mode of an output channel. +2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n +2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2M LL_TIM_OC_GetMode\n +2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3M LL_TIM_OC_GetMode\n +2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4M LL_TIM_OC_GetMode\n +2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5M LL_TIM_OC_GetMode\n +2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6M LL_TIM_OC_GetMode +2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FROZEN +2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ACTIVE +2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_INACTIVE +2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_TOGGLE +2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE +2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE +2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM1 +2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM2 +2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 +2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 +2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 +2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 +2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) +2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT +2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the polarity of an output channel. +2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n + ARM GAS /tmp/ccvzubVv.s page 52 + + +2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_OC_SetPolarity\n +2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_SetPolarity\n +2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_OC_SetPolarity\n +2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_SetPolarity\n +2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_OC_SetPolarity\n +2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_SetPolarity\n +2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_SetPolarity\n +2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_SetPolarity +2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Polarity This parameter can be one of the following values: +2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH +2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_LOW +2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) +2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[i +2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the polarity of an output channel. +2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n +2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_OC_GetPolarity\n +2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_GetPolarity\n +2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_OC_GetPolarity\n +2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_GetPolarity\n +2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_OC_GetPolarity\n +2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_GetPolarity\n +2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_GetPolarity\n +2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_GetPolarity +2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH +2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_LOW +2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) + ARM GAS /tmp/ccvzubVv.s page 53 + + +2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChan +2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the IDLE state of an output channel +2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function is significant only for the timer instances +2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) +2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * can be used to check whether or not a timer instance provides +2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a break input. +2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n +2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_SetIdleState\n +2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_SetIdleState\n +2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_SetIdleState\n +2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_SetIdleState\n +2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3N LL_TIM_OC_SetIdleState\n +2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_SetIdleState\n +2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_SetIdleState\n +2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_SetIdleState +2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param IdleState This parameter can be one of the following values: +2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW +2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_HIGH +2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState +2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iC +2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the IDLE state of an output channel +2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n +2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_GetIdleState\n +2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_GetIdleState\n +2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_GetIdleState\n +2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_GetIdleState\n +2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3N LL_TIM_OC_GetIdleState\n +2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_GetIdleState\n +2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_GetIdleState\n +2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_GetIdleState +2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N + ARM GAS /tmp/ccvzubVv.s page 54 + + +2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW +2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_HIGH +2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) +2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChanne +2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable fast mode for the output channel. +2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Acts only if the channel is configured in PWM1 or PWM2 mode. +2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n +2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_EnableFast\n +2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_EnableFast\n +2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_EnableFast\n +2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_EnableFast\n +2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_EnableFast +2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) +2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); +2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable fast mode for the output channel. +2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n +2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_DisableFast\n +2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_DisableFast\n +2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_DisableFast\n +2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_DisableFast\n +2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_DisableFast +2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 + ARM GAS /tmp/ccvzubVv.s page 55 + + +2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) +2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); +2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether fast mode is enabled for the output channel. +2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n +2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n +2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n +2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n +2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n +2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast +2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) +2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; +2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable compare register (TIMx_CCRx) preload for the output channel. +2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n +2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n +2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n +2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n +2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n +2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_EnablePreload +2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + ARM GAS /tmp/ccvzubVv.s page 56 + + +2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable compare register (TIMx_CCRx) preload for the output channel. +2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n +2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n +2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n +2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n +2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n +2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_DisablePreload +2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channe +2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n +2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n +2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n +2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n +2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n +2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload +2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) +2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; +2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + ARM GAS /tmp/ccvzubVv.s page 57 + + +2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable clearing the output channel on an external event. +2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function can only be used in Output compare and PWM modes. It does not work in Force +2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether +2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. +2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n +2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_EnableClear\n +2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_EnableClear\n +2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_EnableClear\n +2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_EnableClear\n +2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_EnableClear +2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) +2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable clearing the output channel on an external event. +2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether +2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. +2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n +2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_DisableClear\n +2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_DisableClear\n +2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_DisableClear\n +2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_DisableClear\n +2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_DisableClear +2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) +2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + ARM GAS /tmp/ccvzubVv.s page 58 + + +2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates clearing the output channel on an external event is enabled for the output ch +2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function enables clearing the output channel on an external event. +2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function can only be used in Output compare and PWM modes. It does not work in Force +2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether +2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. +2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n +2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n +2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n +2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n +2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n +2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear +2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) +2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; +2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal an +2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the Ocx and OCxN signals). +2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * dead-time insertion feature is supported by a timer instance. +2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter +2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime +2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DeadTime between Min_Data=0 and Max_Data=255 +2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) +2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); +2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 1 (TIMx_CCR1). +2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. +2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not +2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 1 is supported by a timer instance. +2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 +2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + ARM GAS /tmp/ccvzubVv.s page 59 + + +2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) +2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR1, CompareValue); +2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 2 (TIMx_CCR2). +2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. +2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not +2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 2 is supported by a timer instance. +2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 +2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) +2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR2, CompareValue); +2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 3 (TIMx_CCR3). +2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. +2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not +2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel is supported by a timer instance. +2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 +2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) +2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR3, CompareValue); +2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 4 (TIMx_CCR4). +2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. +2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not +2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 4 is supported by a timer instance. +2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 +2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) +2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR4, CompareValue); +2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + ARM GAS /tmp/ccvzubVv.s page 60 + + +2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 5 (TIMx_CCR5). +2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not +2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 5 is supported by a timer instance. +2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 +2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) +2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); +2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 6 (TIMx_CCR6). +2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not +2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 6 is supported by a timer instance. +2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 +2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) +2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR6, CompareValue); +2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR1) set for output channel 1. +2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF +2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not +2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 1 is supported by a timer instance. +2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 +2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) +2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR1)); +2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR2) set for output channel 2. +2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF +2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not +2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 2 is supported by a timer instance. +2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 +2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) +2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR2)); + ARM GAS /tmp/ccvzubVv.s page 61 + + +2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR3) set for output channel 3. +2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF +2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not +2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 3 is supported by a timer instance. +2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 +2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) +2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR3)); +2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR4) set for output channel 4. +2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF +2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not +2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 4 is supported by a timer instance. +2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 +2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) +2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR4)); +2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR5) set for output channel 5. +2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not +2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 5 is supported by a timer instance. +2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 +2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) +2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); +2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR6) set for output channel 6. +2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not +2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 6 is supported by a timer instance. +2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 +2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) +2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + ARM GAS /tmp/ccvzubVv.s page 62 + + +2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR6)); +2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Select on which reference signal the OC5REF is combined to. +2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check +2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports the combined 3-phase PWM mode. +2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n +2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n +2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels +2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param GroupCH5 This parameter can be a combination of the following values: +2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_NONE +2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC1REFC +2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC2REFC +2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC3REFC +2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) +2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); +2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration +2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure input channel. +2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n +2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC1PSC LL_TIM_IC_Config\n +2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC1F LL_TIM_IC_Config\n +2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_Config\n +2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_Config\n +2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_Config\n +2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_Config\n +2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_Config\n +2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_Config\n +2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_Config\n +2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_Config\n +2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_Config\n +2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1P LL_TIM_IC_Config\n +2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_Config\n +2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_Config\n +2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_Config\n +2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_Config\n +2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_Config\n +2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_Config\n +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_Config +2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 + ARM GAS /tmp/ccvzubVv.s page 63 + + +2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Configuration This parameter must be a combination of all the following values: +2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_ +2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 +2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 +2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_I +2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChanne +2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) +2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** << SHIFT_TAB_ICxx[iChannel]); +2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), +2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); +2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the active input. +2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n +2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n +2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n +2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_SetActiveInput +2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICActiveInput This parameter can be one of the following values: +2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI +2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI +2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_TRC +2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiv +2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT +2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current active input. +2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n +2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n +2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n +2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_GetActiveInput +2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: + ARM GAS /tmp/ccvzubVv.s page 64 + + +2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI +2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI +2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_TRC +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) +2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann +2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the prescaler of input channel. +2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n +2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n +2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n +2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler +2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICPrescaler This parameter can be one of the following values: +2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 +2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 +2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 +2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 +2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescal +2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT +2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current prescaler value acting on an input channel. +2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n +2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n +2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n +2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler +2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 +2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 +2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 +2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 +2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) +2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + ARM GAS /tmp/ccvzubVv.s page 65 + + +2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iCha +2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the input filter duration. +2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n +2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_SetFilter\n +2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_SetFilter\n +2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_SetFilter +2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICFilter This parameter can be one of the following values: +2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 +2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 +2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 +2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 +2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 +2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 +2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 +2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 +2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 +2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 +2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 +2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 +2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 +2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 +2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 +2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 +2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) +2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ +2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the input filter duration. +2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n +2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_GetFilter\n +2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_GetFilter\n +2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_GetFilter +2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 + ARM GAS /tmp/ccvzubVv.s page 66 + + +2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 +2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 +2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 +2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 +2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 +2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 +2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 +2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 +2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 +2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 +2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 +2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 +2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 +2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 +2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 +2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) +2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann +2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the input channel polarity. +2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n +2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_SetPolarity\n +2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_SetPolarity\n +2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_SetPolarity\n +2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_SetPolarity\n +2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_SetPolarity\n +2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_SetPolarity\n +2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_SetPolarity +2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICPolarity This parameter can be one of the following values: +2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING +2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_FALLING +2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE +2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity +2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), +2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ICPolarity << SHIFT_TAB_CCxP[iChannel]); +2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current input channel polarity. +2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n +2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_GetPolarity\n +2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_GetPolarity\n + ARM GAS /tmp/ccvzubVv.s page 67 + + +2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_GetPolarity\n +2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_GetPolarity\n +2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_GetPolarity\n +2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_GetPolarity\n +2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_GetPolarity +2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING +2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_FALLING +2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE +2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> +2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SHIFT_TAB_CCxP[iChannel]); +2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). +2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not +2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. +2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination +2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) +2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR2, TIM_CR2_TI1S); +2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. +2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not +2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. +2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination +2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) +2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); +2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. +2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not +2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. +2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination +2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + ARM GAS /tmp/ccvzubVv.s page 68 + + +2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) +2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); +2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 1. +2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF +2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not +2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 1 is supported by a timer instance. +2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 +2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) +2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) +2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR1)); +2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 2. +2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF +2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not +2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 2 is supported by a timer instance. +2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 +2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) +2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) +2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR2)); +2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 3. +2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF +2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not +3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 3 is supported by a timer instance. +3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 +3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) +3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) +3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR3)); +3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 4. +3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF +3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + ARM GAS /tmp/ccvzubVv.s page 69 + + +3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not +3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 4 is supported by a timer instance. +3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 +3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) +3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) +3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR4)); +3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection +3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable external clock mode 2. +3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ET +3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check +3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. +3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_EnableExternalClock +3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) +3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); +3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable external clock mode 2. +3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check +3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. +3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_DisableExternalClock +3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) +3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); +3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether external clock mode 2 is enabled. +3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check +3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. +3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock +3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) +3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); + ARM GAS /tmp/ccvzubVv.s page 70 + + +3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the clock source of the counter clock. +3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note when selected clock source is external clock mode 1, the timer input +3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() +3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * function. This timer input must be configured by calling +3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the @ref LL_TIM_IC_Config() function. +3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check +3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode1. +3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check +3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. +3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetClockSource\n +3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ECE LL_TIM_SetClockSource +3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ClockSource This parameter can be one of the following values: +3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL +3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 +3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 +3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) +3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); +3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the encoder interface mode. +3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check +3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports the encoder mode. +3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetEncoderMode +3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param EncoderMode This parameter can be one of the following values: +3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 +3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 +3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 +3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) +3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); +3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration +3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger output (TRGO) used for timer synchronization . +3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check +3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance can operate as a master timer. +3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput +3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TimerSynchronization This parameter can be one of the following values: + ARM GAS /tmp/ccvzubVv.s page 71 + + +3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_RESET +3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_ENABLE +3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_UPDATE +3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_CC1IF +3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC1REF +3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC2REF +3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC3REF +3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC4REF +3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) +3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); +3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . +3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check +3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance can be used for ADC synchronization. +3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 +3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer Instance +3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ADCSynchronization This parameter can be one of the following values: +3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_RESET +3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_ENABLE +3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_UPDATE +3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_CC1F +3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC1 +3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC2 +3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC3 +3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4 +3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5 +3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC6 +3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING +3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING +3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING +3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING +3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING +3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING +3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) +3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); +3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the synchronization mode of a slave timer. +3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. +3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetSlaveMode +3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param SlaveMode This parameter can be one of the following values: +3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_DISABLED +3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_RESET +3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_GATED +3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_TRIGGER +3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER + ARM GAS /tmp/ccvzubVv.s page 72 + + +3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) +3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); +3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the selects the trigger input to be used to synchronize the counter. +3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. +3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR TS LL_TIM_SetTriggerInput +3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TriggerInput This parameter can be one of the following values: +3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR0 +3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR1 +3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR2 +3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR3 +3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI1F_ED +3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI1FP1 +3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI2FP2 +3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ETRF +3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) +3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); +3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the Master/Slave mode. +3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. +3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode +3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) +3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); +3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the Master/Slave mode. +3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. +3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode +3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) +3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); +3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the Master/Slave mode is enabled. + ARM GAS /tmp/ccvzubVv.s page 73 + + +3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. +3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode +3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) +3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); +3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the external trigger (ETR) input. +3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not +3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an external trigger input. +3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ETP LL_TIM_ConfigETR\n +3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ETPS LL_TIM_ConfigETR\n +3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ETF LL_TIM_ConfigETR +3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRPolarity This parameter can be one of the following values: +3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED +3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_POLARITY_INVERTED +3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRPrescaler This parameter can be one of the following values: +3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 +3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 +3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 +3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 +3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRFilter This parameter can be one of the following values: +3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1 +3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 +3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 +3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 +3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 +3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 +3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 +3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 +3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 +3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 +3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 +3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 +3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 +3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 +3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 +3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 +3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescale +3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ETRFilter) +3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | +3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Break_Function Break function configuration + ARM GAS /tmp/ccvzubVv.s page 74 + + +3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the break function. +3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKE LL_TIM_EnableBRK +3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) +3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); +3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the break function. +3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKE LL_TIM_DisableBRK +3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) +3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); +3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the break input. +3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n +3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR BKF LL_TIM_ConfigBRK +3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakPolarity This parameter can be one of the following values: +3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_POLARITY_LOW +3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_POLARITY_HIGH +3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakFilter This parameter can be one of the following values: +3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 +3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 +3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 +3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 +3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 +3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 +3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 +3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 +3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 +3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 +3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 +3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 +3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 +3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 +3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 +3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 +3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + ARM GAS /tmp/ccvzubVv.s page 75 + + +3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, +3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakFilter) +3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); +3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the break 2 function. +3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not +3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. +3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 +3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) +3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the break 2 function. +3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not +3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. +3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 +3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) +3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the break 2 input. +3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not +3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. +3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n +3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR BK2F LL_TIM_ConfigBRK2 +3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Break2Polarity This parameter can be one of the following values: +3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_POLARITY_LOW +3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH +3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Break2Filter This parameter can be one of the following values: +3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 +3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 +3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 +3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 +3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 +3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 +3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 +3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 +3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 +3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 +3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 +3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 +3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 +3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 + ARM GAS /tmp/ccvzubVv.s page 76 + + +3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 +3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 +3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2F +3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); +3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. +3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n +3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR OSSR LL_TIM_SetOffStates +3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OffStateIdle This parameter can be one of the following values: +3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSI_DISABLE +3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSI_ENABLE +3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OffStateRun This parameter can be one of the following values: +3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSR_DISABLE +3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSR_ENABLE +3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStat +3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); +3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable automatic output (MOE can be set by software or automatically when a break input +3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput +3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) +3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); +3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable automatic output (MOE can be set only by software). +3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput +3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) +3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); +3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether automatic output is enabled. + ARM GAS /tmp/ccvzubVv.s page 77 + + +3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput +3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) +3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); +3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). +3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by +3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * software and is reset in case of break or break2 event +3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs +3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) +3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); +3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). +3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by +3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * software and is reset in case of break or break2 event. +3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs +3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) +3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); +3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether outputs are enabled. +3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs +3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) +3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); +3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(TIM_BREAK_INPUT_SUPPORT) +3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the signals connected to the designated timer break input. + ARM GAS /tmp/ccvzubVv.s page 78 + + +3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether +3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. +3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n +3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKE LL_TIM_EnableBreakInputSource\n +3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INE LL_TIM_EnableBreakInputSource\n +3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKE LL_TIM_EnableBreakInputSource +3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: +3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN +3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 +3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: +3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN +3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK +3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t +3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); +3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, Source); +3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the signals connected to the designated timer break input. +3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether +3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. +3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n +3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKE LL_TIM_DisableBreakInputSource\n +3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INE LL_TIM_DisableBreakInputSource\n +3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKE LL_TIM_DisableBreakInputSource +3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: +3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN +3559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 +3560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: +3561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN +3562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK +3563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_ +3566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); +3568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, Source); +3569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the polarity of the break signal for the timer break input. +3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether +3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. +3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n +3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKP LL_TIM_SetBreakInputSourcePolarity\n +3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n +3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKP LL_TIM_SetBreakInputSourcePolarity +3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: +3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN +3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 +3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: + ARM GAS /tmp/ccvzubVv.s page 79 + + +3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN +3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK +3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Polarity This parameter can be one of the following values: +3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_POLARITY_LOW +3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_POLARITY_HIGH +3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uin +3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Polarity) +3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); +3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOUR +3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */ +3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configures the timer DMA burst feature. +3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or +3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * not a timer instance supports the DMA burst mode. +3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n +3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * DCR DBA LL_TIM_ConfigDMABurst +3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMABurstBaseAddress This parameter can be one of the following values: +3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 +3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 +3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR +3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER +3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_SR +3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR +3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 +3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 +3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER +3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT +3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC +3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR +3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR +3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 +3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 +3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 +3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 +3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR +3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_OR +3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 +3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 +3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 +3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 (*) +3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 (*) +3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (*) value not defined in all devices +3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMABurstLength This parameter can be one of the following values: +3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER +3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS + ARM GAS /tmp/ccvzubVv.s page 80 + + +3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS +3642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS +3643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS +3644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS +3645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS +3646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS +3647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS +3648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS +3649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS +3650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS +3651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS +3652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS +3653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS +3654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS +3655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS +3656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS +3657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_ +3660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); +3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping +3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Remap TIM inputs (input channel, internal/external triggers). +3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not +3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a some timer inputs can be remapped. +3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n +3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM5_OR TI4_RMP LL_TIM_SetRemap\n +3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM11_OR TI1_RMP LL_TIM_SetRemap +3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Remap Remap param depends on the TIMx. Description available only +3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in CHM version of the User Manual (not in .pdf). +3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Otherwise see Reference Manual description of OR registers. +3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Below description summarizes "Timer Instance" and "Remap" param combinations: +3684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM2: one of the following values +3686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * ITR1_RMP can be one of the following values +3688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO +3689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP +3690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF +3691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF +3692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM5: one of the following values +3694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO +3696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI +3697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE + ARM GAS /tmp/ccvzubVv.s page 81 + + +3698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC +3699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM11: one of the following values +3701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO +3703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX +3704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE +3705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_MCO1 +3706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) +3710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); +3712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +3716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management +3719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +3720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the update interrupt flag (UIF). +3723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE +3724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) +3728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); +3730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). +3734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE +3735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) + 500 .loc 2 3738 26 view .LVU77 + 501 .LBB59: +3739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); + 502 .loc 2 3740 3 view .LVU78 + 503 .loc 2 3740 12 is_stmt 0 view .LVU79 + 504 0002 094B ldr r3, .L42 + 505 0004 1B69 ldr r3, [r3, #16] + 506 .loc 2 3740 66 view .LVU80 + 507 0006 13F0010F tst r3, #1 + 508 000a 0BD0 beq .L39 + 509 .LVL11: + 510 .loc 2 3740 66 view .LVU81 + 511 .LBE59: + 512 .LBE58: + 384:Src/stm32f7xx_it.c **** { + ARM GAS /tmp/ccvzubVv.s page 82 + + + 385:Src/stm32f7xx_it.c **** LL_TIM_ClearFlag_UPDATE(TIM6); + 513 .loc 1 385 5 is_stmt 1 view .LVU82 + 514 .LBB60: + 515 .LBI60: +3727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 516 .loc 2 3727 22 view .LVU83 + 517 .LBB61: +3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 518 .loc 2 3729 3 view .LVU84 + 519 000c 064B ldr r3, .L42 + 520 000e 6FF00102 mvn r2, #1 + 521 0012 1A61 str r2, [r3, #16] + 522 .LVL12: +3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 523 .loc 2 3729 3 is_stmt 0 view .LVU85 + 524 .LBE61: + 525 .LBE60: + 386:Src/stm32f7xx_it.c **** TO6++;//increment tick + 526 .loc 1 386 5 is_stmt 1 view .LVU86 + 527 .loc 1 386 8 is_stmt 0 view .LVU87 + 528 0014 054A ldr r2, .L42+4 + 529 0016 1368 ldr r3, [r2] + 530 0018 0133 adds r3, r3, #1 + 531 001a 1360 str r3, [r2] + 387:Src/stm32f7xx_it.c **** //10 ms or 100 Hz + 388:Src/stm32f7xx_it.c **** HAL_GPIO_TogglePin(TEST_01_GPIO_Port, TEST_01_Pin); + 532 .loc 1 388 5 is_stmt 1 view .LVU88 + 533 001c 0221 movs r1, #2 + 534 001e 0448 ldr r0, .L42+8 + 535 0020 FFF7FEFF bl HAL_GPIO_TogglePin + 536 .LVL13: + 537 .L39: + 389:Src/stm32f7xx_it.c **** //HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_12); + 390:Src/stm32f7xx_it.c **** } + 391:Src/stm32f7xx_it.c **** /* USER CODE END TIM6_DAC_IRQn 1 */ + 392:Src/stm32f7xx_it.c **** } + 538 .loc 1 392 1 is_stmt 0 view .LVU89 + 539 0024 08BD pop {r3, pc} + 540 .L43: + 541 0026 00BF .align 2 + 542 .L42: + 543 0028 00100040 .word 1073745920 + 544 002c 00000000 .word TO6 + 545 0030 000C0240 .word 1073875968 + 546 .cfi_endproc + 547 .LFE1199: + 549 .section .text.TIM7_IRQHandler,"ax",%progbits + 550 .align 1 + 551 .global TIM7_IRQHandler + 552 .syntax unified + 553 .thumb + 554 .thumb_func + 556 TIM7_IRQHandler: + 557 .LFB1200: + 393:Src/stm32f7xx_it.c **** + 394:Src/stm32f7xx_it.c **** /** + 395:Src/stm32f7xx_it.c **** * @brief This function handles TIM7 global interrupt. + ARM GAS /tmp/ccvzubVv.s page 83 + + + 396:Src/stm32f7xx_it.c **** */ + 397:Src/stm32f7xx_it.c **** void TIM7_IRQHandler(void) + 398:Src/stm32f7xx_it.c **** { + 558 .loc 1 398 1 is_stmt 1 view -0 + 559 .cfi_startproc + 560 @ args = 0, pretend = 0, frame = 0 + 561 @ frame_needed = 0, uses_anonymous_args = 0 + 562 @ link register save eliminated. + 399:Src/stm32f7xx_it.c **** /* USER CODE BEGIN TIM7_IRQn 0 */ + 400:Src/stm32f7xx_it.c **** + 401:Src/stm32f7xx_it.c **** /* USER CODE END TIM7_IRQn 0 */ + 402:Src/stm32f7xx_it.c **** /* USER CODE BEGIN TIM7_IRQn 1 */ + 403:Src/stm32f7xx_it.c **** if(LL_TIM_IsActiveFlag_UPDATE(TIM7)) + 563 .loc 1 403 3 view .LVU91 + 564 .LVL14: + 565 .LBB62: + 566 .LBI62: +3738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 567 .loc 2 3738 26 view .LVU92 + 568 .LBB63: + 569 .loc 2 3740 3 view .LVU93 + 570 .loc 2 3740 12 is_stmt 0 view .LVU94 + 571 0000 064B ldr r3, .L46 + 572 0002 1B69 ldr r3, [r3, #16] + 573 .loc 2 3740 66 view .LVU95 + 574 0004 13F0010F tst r3, #1 + 575 0008 07D0 beq .L44 + 576 .LVL15: + 577 .loc 2 3740 66 view .LVU96 + 578 .LBE63: + 579 .LBE62: + 404:Src/stm32f7xx_it.c **** { + 405:Src/stm32f7xx_it.c **** LL_TIM_ClearFlag_UPDATE(TIM7); + 580 .loc 1 405 5 is_stmt 1 view .LVU97 + 581 .LBB64: + 582 .LBI64: +3727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 583 .loc 2 3727 22 view .LVU98 + 584 .LBB65: +3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 585 .loc 2 3729 3 view .LVU99 + 586 000a 044B ldr r3, .L46 + 587 000c 6FF00102 mvn r2, #1 + 588 0010 1A61 str r2, [r3, #16] + 589 .LVL16: +3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 590 .loc 2 3729 3 is_stmt 0 view .LVU100 + 591 .LBE65: + 592 .LBE64: + 406:Src/stm32f7xx_it.c **** TO7++; + 593 .loc 1 406 5 is_stmt 1 view .LVU101 + 594 .loc 1 406 8 is_stmt 0 view .LVU102 + 595 0012 034A ldr r2, .L46+4 + 596 0014 1368 ldr r3, [r2] + 597 0016 0133 adds r3, r3, #1 + 598 0018 1360 str r3, [r2] + 599 .L44: + ARM GAS /tmp/ccvzubVv.s page 84 + + + 407:Src/stm32f7xx_it.c **** //1 ms or 1000 Hz + 408:Src/stm32f7xx_it.c **** //HAL_GPIO_TogglePin(TEST_01_GPIO_Port, TEST_01_Pin); + 409:Src/stm32f7xx_it.c **** } + 410:Src/stm32f7xx_it.c **** /* USER CODE END TIM7_IRQn 1 */ + 411:Src/stm32f7xx_it.c **** } + 600 .loc 1 411 1 view .LVU103 + 601 001a 7047 bx lr + 602 .L47: + 603 .align 2 + 604 .L46: + 605 001c 00140040 .word 1073746944 + 606 0020 00000000 .word TO7 + 607 .cfi_endproc + 608 .LFE1200: + 610 .section .text.UART_RxCpltCallback,"ax",%progbits + 611 .align 1 + 612 .global UART_RxCpltCallback + 613 .syntax unified + 614 .thumb + 615 .thumb_func + 617 UART_RxCpltCallback: + 618 .LFB1202: + 412:Src/stm32f7xx_it.c **** + 413:Src/stm32f7xx_it.c **** /** + 414:Src/stm32f7xx_it.c **** * @brief This function handles DMA2 stream7 global interrupt. + 415:Src/stm32f7xx_it.c **** */ + 416:Src/stm32f7xx_it.c **** void DMA2_Stream7_IRQHandler(void) + 417:Src/stm32f7xx_it.c **** { + 418:Src/stm32f7xx_it.c **** /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */ + 419:Src/stm32f7xx_it.c **** if(LL_DMA_IsActiveFlag_TC7(DMA2) == 1) + 420:Src/stm32f7xx_it.c **** { + 421:Src/stm32f7xx_it.c **** DMA2_Stream7_TransferComplete(); + 422:Src/stm32f7xx_it.c **** u_tx_flg = 0;//indicate that transfer compete + 423:Src/stm32f7xx_it.c **** } + 424:Src/stm32f7xx_it.c **** else if(LL_DMA_IsActiveFlag_TE7(DMA2) == 1) + 425:Src/stm32f7xx_it.c **** { + 426:Src/stm32f7xx_it.c **** LL_DMA_ClearFlag_TE7(DMA2); + 427:Src/stm32f7xx_it.c **** } + 428:Src/stm32f7xx_it.c **** /* USER CODE END DMA2_Stream7_IRQn 0 */ + 429:Src/stm32f7xx_it.c **** /* USER CODE BEGIN DMA2_Stream7_IRQn 1 */ + 430:Src/stm32f7xx_it.c **** + 431:Src/stm32f7xx_it.c **** /* USER CODE END DMA2_Stream7_IRQn 1 */ + 432:Src/stm32f7xx_it.c **** } + 433:Src/stm32f7xx_it.c **** + 434:Src/stm32f7xx_it.c **** /* USER CODE BEGIN 1 */ + 435:Src/stm32f7xx_it.c **** void UART_RxCpltCallback(void) + 436:Src/stm32f7xx_it.c **** { + 619 .loc 1 436 1 is_stmt 1 view -0 + 620 .cfi_startproc + 621 @ args = 0, pretend = 0, frame = 0 + 622 @ frame_needed = 0, uses_anonymous_args = 0 + 623 @ link register save eliminated. + 624 0000 10B4 push {r4} + 625 .LCFI6: + 626 .cfi_def_cfa_offset 4 + 627 .cfi_offset 4, -4 + 437:Src/stm32f7xx_it.c **** uart_buf = LL_USART_ReceiveData8(USART1); + ARM GAS /tmp/ccvzubVv.s page 85 + + + 628 .loc 1 437 5 view .LVU105 + 629 .LVL17: + 630 .LBB66: + 631 .LBI66: + 632 .file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @file stm32f7xx_ll_usart.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Header file of USART LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This software is licensed under terms that can be found in the LICENSE file + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * in the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifndef STM32F7xx_LL_USART_H + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define STM32F7xx_LL_USART_H + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifdef __cplusplus + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** extern "C" { + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Includes ------------------------------------------------------------------*/ + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #include "stm32f7xx.h" + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @addtogroup STM32F7xx_LL_Driver + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \ + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL USART + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private types -------------------------------------------------------------*/ + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private variables ---------------------------------------------------------*/ + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private constants ---------------------------------------------------------*/ + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Constants USART Private Constants + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private macros ------------------------------------------------------------*/ + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) + ARM GAS /tmp/ccvzubVv.s page 86 + + + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Macros USART Private Macros + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/ + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported types ------------------------------------------------------------*/ + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_ES_INIT USART Exported Init structures + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief LL USART Init Structure definition + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t BaudRate; /*!< This field defines expected Usart communication baud rat + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetBaudRate().*/ + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or receive + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_DATAWI + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetDataWidth().*/ + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_STOPBI + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetStopBitsLength().*/ + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t Parity; /*!< Specifies the parity mode. + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_PARITY + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetParity().*/ + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is en + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_DIRECT + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetTransferDirection().*/ + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enab + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_HWCONT + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetHWFlowCtrl().*/ + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_OVERSA + ARM GAS /tmp/ccvzubVv.s page 87 + + + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetOverSampling().*/ + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_InitTypeDef; + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief LL USART Clock Init Structure definition + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_CLOCK. + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_Disabl + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_POLARI + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetClockPolarity(). + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_PHASE. + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetClockPhase(). + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the l + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** data bit (MSB) has to be output on the SCLK pin in synch + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_LASTCL + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetLastClkPulseOutput(). + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_ClockInitTypeDef; + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USE_FULL_LL_DRIVER */ + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported constants --------------------------------------------------------*/ + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Constants USART Exported Constants + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Flags defines which can be used with LL_USART_WriteReg function + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error cle + ARM GAS /tmp/ccvzubVv.s page 88 + + + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error cl + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error dete + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error cl + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detect + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission com + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission com + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detect + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag * + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block cle + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Flags defines which can be used with LL_USART_ReadReg function + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error fla + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error fl + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected f + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error fl + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detect + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data regist + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission com + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data re + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detect + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt fl + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block fla + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate e + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate f + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_ISR_REACK) + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable a + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_ISR_REACK */ + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission com + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ + ARM GAS /tmp/ccvzubVv.s page 89 + + + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IT IT Defines + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt e + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data regist + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission com + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data re + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block int + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detect + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt en + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission com + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DIRECTION Communication Direction + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PARITY Parity Control + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_NONE 0x00000000U /*!< Parity co + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity co + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity co + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP Wakeup + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute + ARM GAS /tmp/ccvzubVv.s page 90 + + + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DATAWIDTH Datawidth + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : S + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : S + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : S + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLOCK Clock Signal + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provid + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided * + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/ + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the l + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the l + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PHASE Clock Phase + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transiti + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transit + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_POLARITY Clock Polarity + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK + ARM GAS /tmp/ccvzubVv.s page 91 + + + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCL + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_STOPBITS Stop Bits + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1 0x00000000U /*!< 1 s + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 s + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as d + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works usin + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works usin + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the da + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the da + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BITORDER Bit Order + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/rece + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/rece + ARM GAS /tmp/ccvzubVv.s page 92 + + + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Me + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Fa + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_HWCONTROL Hardware Control + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and R + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS outpu + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and R + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS) + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake u + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake u + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake u + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */ + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode * + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + ARM GAS /tmp/ccvzubVv.s page 93 + + + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection m + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection m + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data regis + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data regis + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported macro ------------------------------------------------------------*/ + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Macros USART Exported Macros + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Write a value in USART register + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __INSTANCE__ USART Instance + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __REG__ Register to be written + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __VALUE__ Value to be written in the register + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VAL + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Read a value in USART register + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __INSTANCE__ USART Instance + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __REG__ Register to be read + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Register value + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + ARM GAS /tmp/ccvzubVv.s page 94 + + + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Compute USARTDIV value according to Peripheral Clock and + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __BAUDRATE__ Baud rate value to achieve + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\ + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ((__BAUDRATE__)/2U))/(__BAUDRATE_ + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Compute USARTDIV value according to Peripheral Clock and + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __BAUDRATE__ Baud rate value to achieve + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/ + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported functions --------------------------------------------------------*/ + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Functions USART Exported Functions + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration Configuration functions + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Enable + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_Enable + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR1, USART_CR1_UE); + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + ARM GAS /tmp/ccvzubVv.s page 95 + + + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Disable (all USART prescalers and outputs are disabled) + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When USART is disabled, USART prescalers and outputs are stopped immediately, + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * and current operations are discarded. The configuration of the USART is kept, but all t + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * flags, in the USARTx_ISR are set to their default values. + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_Disable + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR1, USART_CR1_UE); + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART is enabled + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_IsEnabled + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART enabled in STOP Mode. + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provide + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * USART clock selection is HSI or LSE in RCC. + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_EnableInStopMode + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART disabled in STOP Mode. + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_DisableInStopMode + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + ARM GAS /tmp/ccvzubVv.s page 96 + + + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_UCESM) + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Clock enabled in STOP Mode + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is called, USART Clock is enabled while in STOP mode + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_EnableClockInStopMode + 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx) + 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_UCESM); + 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART clock disabled in STOP Mode + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is called, USART Clock is disabled while in STOP mode + 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_DisableClockInStopMode + 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx) + 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM); + 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART clock is enabled in STOP Mode + 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_IsClockEnabledInStopMode + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(const USART_TypeDef *USARTx) + 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)); + 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_UCESM */ + 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM*/ + 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_EnableDirectionRx + 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) + 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); + ARM GAS /tmp/ccvzubVv.s page 97 + + + 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Receiver Disable + 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_DisableDirectionRx + 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) + 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); + 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Transmitter Enable + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TE LL_USART_EnableDirectionTx + 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) + 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); + 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Transmitter Disable + 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TE LL_USART_DisableDirectionTx + 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) + 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); + 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure simultaneously enabled/disabled states + 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * of Transmitter and Receiver + 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_SetTransferDirection\n + 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 TE LL_USART_SetTransferDirection + 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param TransferDirection This parameter can be one of the following values: + 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_NONE + 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_RX + 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX + 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX_RX + 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirectio + 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); + 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return enabled/disabled states of Transmitter and Receiver + 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_GetTransferDirection\n + 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 TE LL_USART_GetTransferDirection + ARM GAS /tmp/ccvzubVv.s page 98 + + + 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_NONE + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_RX + 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX + 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX_RX + 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) + 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); + 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Parity (enabled/disabled and parity mode if enabled). + 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This function selects if hardware parity control (generation and detection) is enabled + 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * When the parity control is enabled (Odd or Even), computed parity bit is inserted at th + 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (9th or 8th bit depending on data width) and parity is checked on the received data. + 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_SetParity\n + 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_SetParity + 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Parity This parameter can be one of the following values: + 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE + 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN + 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD + 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) + 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); + 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_GetParity\n + 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_GetParity + 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE + 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN + 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD + 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) + 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); + 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Receiver Wake Up method from Mute mode. + 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod + 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Method This parameter can be one of the following values: + 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_IDLELINE + 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) + 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + ARM GAS /tmp/ccvzubVv.s page 99 + + + 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); + 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Receiver Wake Up method from Mute mode + 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod + 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_IDLELINE + 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) + 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); + 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) + 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 M0 LL_USART_SetDataWidth\n + 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_SetDataWidth + 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataWidth This parameter can be one of the following values: + 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B + 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B + 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B + 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) + 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); + 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 M0 LL_USART_GetDataWidth\n + 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_GetDataWidth + 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B + 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B + 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B + 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) + 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); + 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Allow switch between Mute Mode and Active mode + 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_EnableMuteMode + 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) + 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); + 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + ARM GAS /tmp/ccvzubVv.s page 100 + + + 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_DisableMuteMode + 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) + 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); + 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if switch between Mute Mode and Active mode is allowed + 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode + 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). + 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) + 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); + 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Oversampling to 8-bit or 16-bit mode + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 OVER8 LL_USART_SetOverSampling + 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: + 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 + 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 + 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) + 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); + 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Oversampling mode + 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 OVER8 LL_USART_GetOverSampling + 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 + 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 + 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) + 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); + 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not + 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput + 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LastBitClockPulse This parameter can be one of the following values: + ARM GAS /tmp/ccvzubVv.s page 101 + + + 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPul + 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); + 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve Clock pulse of the last data bit output configuration + 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (Last bit Clock pulse output to the SCLK pin or not) + 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput + 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) + 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); + 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select the phase of the clock output on the SCLK pin in synchronous mode + 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_SetClockPhase + 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param ClockPhase This parameter can be one of the following values: + 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE + 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE + 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) + 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); + 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return phase of the clock output on the SCLK pin in synchronous mode + 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_GetClockPhase + 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE + 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE + 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) + 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); + 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + ARM GAS /tmp/ccvzubVv.s page 102 + + + 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode + 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPOL LL_USART_SetClockPolarity + 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param ClockPolarity This parameter can be one of the following values: + 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW + 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) + 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); + 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return polarity of the clock output on the SCLK pin in synchronous mode + 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPOL LL_USART_GetClockPolarity + 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW + 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH + 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) + 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); + 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock + 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : +1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function +1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function +1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutpu +1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_ConfigClock\n +1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CPOL LL_USART_ConfigClock\n +1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 LBCL LL_USART_ConfigClock +1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Phase This parameter can be one of the following values: +1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE +1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE +1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Polarity This parameter can be one of the following values: +1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW +1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH +1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LBCPOutput This parameter can be one of the following values: +1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT +1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT +1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, +1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCP +1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + ARM GAS /tmp/ccvzubVv.s page 103 + + +1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Clock output on SCLK pin +1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not +1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. +1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput +1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) +1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Clock output on SCLK pin +1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not +1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. +1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput +1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) +1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); +1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Clock output on SCLK pin is enabled +1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not +1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. +1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput +1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) +1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); +1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set the length of the stop bits +1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 STOP LL_USART_SetStopBitsLength +1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param StopBits This parameter can be one of the following values: +1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 +1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 +1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 +1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 +1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) +1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + ARM GAS /tmp/ccvzubVv.s page 104 + + +1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve the length of the stop bits +1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 STOP LL_USART_GetStopBitsLength +1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 +1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 +1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 +1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 +1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) +1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); +1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) +1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : +1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Data Width configuration using @ref LL_USART_SetDataWidth() function +1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Parity Control and mode configuration using @ref LL_USART_SetParity() function +1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function +1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_ConfigCharacter\n +1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_ConfigCharacter\n +1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M0 LL_USART_ConfigCharacter\n +1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_ConfigCharacter\n +1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigCharacter +1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataWidth This parameter can be one of the following values: +1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B +1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B +1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B +1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Parity This parameter can be one of the following values: +1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE +1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN +1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD +1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param StopBits This parameter can be one of the following values: +1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 +1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 +1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 +1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 +1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t P +1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t StopBits) +1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); +1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure TX/RX pins swapping setting. +1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap +1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param SwapConfig This parameter can be one of the following values: +1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_STANDARD +1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_SWAPPED +1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + ARM GAS /tmp/ccvzubVv.s page 105 + + +1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) +1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); +1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve TX/RX pins swapping configuration. +1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap +1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_STANDARD +1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_SWAPPED +1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) +1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); +1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure RX pin active level logic +1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel +1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PinInvMethod This parameter can be one of the following values: +1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD +1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED +1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); +1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve RX pin active level logic configuration +1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel +1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD +1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED +1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) +1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); +1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure TX pin active level logic +1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel +1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PinInvMethod This parameter can be one of the following values: +1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD +1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED +1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); + ARM GAS /tmp/ccvzubVv.s page 106 + + +1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve TX pin active level logic configuration +1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel +1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD +1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED +1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) +1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); +1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Binary data logic. +1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Allow to define how Logical data from the data register are send/received : +1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) +1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic +1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataLogic This parameter can be one of the following values: +1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE +1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE +1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) +1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); +1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve Binary data configuration +1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic +1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE +1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE +1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) +1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); +1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure transfer bit order (either Less or Most Significant Bit First) +1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note MSB First means data is transmitted/received with the MSB first, following the start bi +1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LSB First means data is transmitted/received with data bit 0 first, following the start +1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder +1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BitOrder This parameter can be one of the following values: +1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_LSBFIRST +1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_MSBFIRST +1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) +1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + ARM GAS /tmp/ccvzubVv.s page 107 + + +1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return transfer bit order (either Less or Most Significant Bit First) +1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note MSB First means data is transmitted/received with the MSB first, following the start bi +1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LSB First means data is transmitted/received with data bit 0 first, following the start +1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder +1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_LSBFIRST +1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_MSBFIRST +1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) +1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); +1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Auto Baud-Rate Detection +1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or +1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate +1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) +1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_ABREN); +1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Auto Baud-Rate Detection +1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or +1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate +1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) +1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); +1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled +1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud +1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) +1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); +1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ARM GAS /tmp/ccvzubVv.s page 108 + + +1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Auto Baud-Rate mode bits +1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or +1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode +1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AutoBaudRateMode This parameter can be one of the following values: +1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE +1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME +1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME +1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) +1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); +1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Auto Baud-Rate mode +1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or +1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode +1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT +1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE +1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME +1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME +1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) +1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); +1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Receiver Timeout +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout +1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) +1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_RTOEN); +1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Receiver Timeout +1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout +1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) +1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); +1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ARM GAS /tmp/ccvzubVv.s page 109 + + +1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Receiver Timeout feature is enabled +1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) +1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Address of the USART node. +1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This is used in multiprocessor communication during Mute mode or Stop mode, +1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * for wake up with address mark detection. +1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. +1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (b7-b4 should be set to 0) +1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. +1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (This is used in multiprocessor communication during Mute mode or Stop mode, +1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * for wake up with 7-bit address mark detection. +1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * The MSB of the character sent by the transmitter should be equal to 1. +1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * It may also be used for character detection during normal reception, +1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Mute mode inactive (for example, end of block detection in ModBus protocol). +1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * In this case, the whole received character (8-bit) is compared to the ADD[7:0] +1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * value and CMF flag is set on match) +1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n +1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 ADDM7 LL_USART_ConfigNodeAddress +1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AddressLen This parameter can be one of the following values: +1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_4B +1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_7B +1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param NodeAddress 4 or 7 bit Address of the USART node. +1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_ +1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, +1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); +1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. +1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note If 4-bit Address Detection is selected in ADDM7, +1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) +1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * If 7-bit Address Detection is selected in ADDM7, +1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) +1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADD LL_USART_GetNodeAddress +1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) +1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) +1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) + ARM GAS /tmp/ccvzubVv.s page 110 + + +1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen +1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_4B +1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_7B +1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) +1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); +1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable RTS HW Flow Control +1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl +1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) +1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_RTSE); +1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable RTS HW Flow Control +1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl +1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) +1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); +1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable CTS HW Flow Control +1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl +1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) +1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_CTSE); +1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable CTS HW Flow Control +1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl +1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + ARM GAS /tmp/ccvzubVv.s page 111 + + +1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) +1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); +1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure HW Flow Control mode (both CTS and RTS) +1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n +1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 CTSE LL_USART_SetHWFlowCtrl +1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param HardwareFlowControl This parameter can be one of the following values: +1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_NONE +1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS +1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_CTS +1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS_CTS +1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) +1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return HW Flow Control configuration (both CTS and RTS) +1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n +1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 CTSE LL_USART_GetHWFlowCtrl +1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_NONE +1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS +1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_CTS +1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS_CTS +1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) +1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable One bit sampling method +1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp +1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) +1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); +1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable One bit sampling method +1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp + ARM GAS /tmp/ccvzubVv.s page 112 + + +1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) +1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); +1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if One bit sampling method is enabled +1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp +1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) +1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); +1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Overrun detection +1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect +1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) +1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); +1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Overrun detection +1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect +1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) +1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); +1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Overrun detection is enabled +1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect +1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) +1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) +1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS) +1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) +1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + ARM GAS /tmp/ccvzubVv.s page 113 + + +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. +1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUS LL_USART_SetWKUPType +1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Type This parameter can be one of the following values: +1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_ADDRESS +1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_STARTBIT +1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_RXNE +1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) +1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type); +1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) +1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not +1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. +1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUS LL_USART_GetWKUPType +1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_ADDRESS +1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_STARTBIT +1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_RXNE +1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx) +1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); +1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */ +1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ +1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure USART BRR register for achieving expected Baud Rate value. +1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Compute and set USARTDIV value in BRR Register (full BRR content) +1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values +1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Peripheral clock and Baud rate values provided as function parameters should be valid +1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (Baud rate value != 0) +1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. +1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll BRR BRR LL_USART_SetBaudRate +1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PeriphClk Peripheral Clock +1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: +1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 +1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 +1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BaudRate Baud Rate +1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverS +1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t BaudRate) +1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t usartdiv; +1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t brrtemp; +1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (OverSampling == LL_USART_OVERSAMPLING_8) +1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); + ARM GAS /tmp/ccvzubVv.s page 114 + + +1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrtemp = usartdiv & 0xFFF0U; +1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); +1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->BRR = brrtemp; +1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else +1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); +1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return current Baud Rate value, according to USARTDIV present in BRR register +1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (full BRR content), and to used Peripheral Clock and Oversampling mode values +1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be ret +1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. +1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll BRR BRR LL_USART_GetBaudRate +1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PeriphClk Peripheral Clock +1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: +1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 +1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 +1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Baud Rate +1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint +1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t usartdiv; +1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t brrresult = 0x0U; +1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** usartdiv = USARTx->BRR; +1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (usartdiv == 0U) +1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Do not perform a division by 0 */ +1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else if (OverSampling == LL_USART_OVERSAMPLING_8) +1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; +1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (usartdiv != 0U) +1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrresult = (PeriphClk * 2U) / usartdiv; +1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else +1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if ((usartdiv & 0xFFFFU) != 0U) +1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrresult = PeriphClk / usartdiv; +1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (brrresult); +1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Receiver Time Out Value (expressed in nb of bits duration) +1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR RTO LL_USART_SetRxTimeout +1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + ARM GAS /tmp/ccvzubVv.s page 115 + + +1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout) +1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); +1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Get Receiver Time Out Value (expressed in nb of bits duration) +1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR RTO LL_USART_GetRxTimeout +1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF +1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) +1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); +1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Block Length value in reception +1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR BLEN LL_USART_SetBlockLength +1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF +1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) +1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); +1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Get Block Length value in reception +1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RTOR BLEN LL_USART_GetBlockLength +1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0xFF +1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) +1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); +1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature +1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable IrDA mode +1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not +1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. +1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IREN LL_USART_EnableIrda +1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + ARM GAS /tmp/ccvzubVv.s page 116 + + +1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) +1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_IREN); +1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable IrDA mode +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not +1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. +1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IREN LL_USART_DisableIrda +1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) +1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); +1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if IrDA mode is enabled +1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not +1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. +1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IREN LL_USART_IsEnabledIrda +1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) +1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); +1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure IrDA Power Mode (Normal or Low Power) +1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not +1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. +1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode +1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PowerMode This parameter can be one of the following values: +1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_IRDA_POWER_NORMAL +1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_IRDA_POWER_LOW +1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) +1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); +1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) +1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not +1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. +1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode +1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_IRDA_POWER_NORMAL +1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE +1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + ARM GAS /tmp/ccvzubVv.s page 117 + + +1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) +1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); +1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Irda prescaler value, used for dividing the USART clock source +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * to achieve the Irda Low Power frequency (8 bits value) +1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not +1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. +1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler +1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF +1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Irda prescaler value, used for dividing the USART clock source +1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * to achieve the Irda Low Power frequency (8 bits value) +1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not +1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. +1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler +1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) +1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) +1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feat +1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Smartcard NACK transmission +1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK +1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) +1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_NACK); +1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Smartcard NACK transmission + ARM GAS /tmp/ccvzubVv.s page 118 + + +1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK +1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) +1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); +1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Smartcard NACK transmission is enabled +1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK +1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) +1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); +1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Smartcard mode +1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCEN LL_USART_EnableSmartcard +1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) +1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_SCEN); +1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Smartcard mode +1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCEN LL_USART_DisableSmartcard +1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) +1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); +1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Smartcard mode is enabled +1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard +1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). + ARM GAS /tmp/ccvzubVv.s page 119 + + +1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) +1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); +1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) +1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mo +1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * In transmission mode, it specifies the number of automatic retransmission retries, befo +1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * generating a transmission error (FE bit set). +1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * In reception mode, it specifies the number or erroneous reception trials, before genera +1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * reception error (RXNE and PE bits set) +1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount +1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7 +1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryC +1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); +1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) +1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount +1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) +1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) +1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); +1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Smartcard prescaler value, used for dividing the USART clock +1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * source to provide the SMARTCARD Clock (5 bits value) +1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler +1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 +1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Smartcard prescaler value, used for dividing the USART clock +1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * source to provide the SMARTCARD Clock (5 bits value) +1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + ARM GAS /tmp/ccvzubVv.s page 120 + + +1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler +1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) +1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) +1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods +2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (GT[7:0] bits : Guard time value) +2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime +2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF +2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) +2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); +2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods +2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (GT[7:0] bits : Guard time value) +2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime +2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) +2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) +2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); +2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex f +2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Single Wire Half-Duplex mode +2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not +2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. +2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex +2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) +2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + ARM GAS /tmp/ccvzubVv.s page 121 + + +2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Single Wire Half-Duplex mode +2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not +2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. +2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex +2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) +2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); +2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Single Wire Half-Duplex mode is enabled +2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not +2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. +2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex +2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) +2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); +2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature +2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set LIN Break Detection Length +2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen +2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LINBDLength This parameter can be one of the following values: +2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_10B +2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_11B +2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) +2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); +2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return LIN Break Detection Length +2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. + ARM GAS /tmp/ccvzubVv.s page 122 + + +2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen +2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_10B +2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LINBREAK_DETECT_11B +2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) +2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); +2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable LIN mode +2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_EnableLIN +2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) +2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_LINEN); +2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable LIN mode +2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_DisableLIN +2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) +2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); +2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if LIN mode is enabled +2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN +2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) +2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); +2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature +2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + ARM GAS /tmp/ccvzubVv.s page 123 + + +2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits) +2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not +2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. +2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime +2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Time Value between Min_Data=0 and Max_Data=31 +2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) +2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); +2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return DEDT (Driver Enable De-Assertion Time) +2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not +2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. +2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime +2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 +2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) +2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). +2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not +2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. +2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime +2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Time Value between Min_Data=0 and Max_Data=31 +2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) +2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); +2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return DEAT (Driver Enable Assertion Time) +2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not +2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. +2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime +2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 +2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) +2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Driver Enable (DE) Mode + ARM GAS /tmp/ccvzubVv.s page 124 + + +2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not +2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. +2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEM LL_USART_EnableDEMode +2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) +2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_DEM); +2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Driver Enable (DE) Mode +2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not +2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. +2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEM LL_USART_DisableDEMode +2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) +2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_DEM); +2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Driver Enable (DE) Mode is enabled +2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not +2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. +2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode +2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) +2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); +2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select Driver Enable Polarity +2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not +2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. +2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity +2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Polarity This parameter can be one of the following values: +2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_HIGH +2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_LOW +2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity) +2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity); +2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Driver Enable Polarity +2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not +2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Driver Enable feature is supported by the USARTx instance. + ARM GAS /tmp/ccvzubVv.s page 125 + + +2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity +2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_HIGH +2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DE_POLARITY_LOW +2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) +2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); +2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services +2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) +2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In UART mode, the following bits must be kept cleared: +2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, +2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - CLKEN bit in the USART_CR2 register, +2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, +2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, +2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. +2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : +2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function +2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function +2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function +2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function +2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function +2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Asynchronous Mode +2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, ...) should be set using +2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions +2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n +2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigAsyncMode\n +2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigAsyncMode\n +2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigAsyncMode\n +2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigAsyncMode +2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) +2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Asynchronous mode, the following bits must be kept cleared: +2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN, CLKEN bits in the USART_CR2 register, +2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN, IREN and HDSEL bits in the USART_CR3 register. +2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); +2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); +2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Synchronous Mode +2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In Synchronous mode, the following bits must be kept cleared: + ARM GAS /tmp/ccvzubVv.s page 126 + + +2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, +2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, +2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, +2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. +2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also sets the USART in Synchronous mode. +2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not +2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. +2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : +2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function +2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function +2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function +2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function +2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function +2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Synchronous Mode +2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using +2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions +2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n +2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigSyncMode\n +2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigSyncMode\n +2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigSyncMode\n +2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigSyncMode +2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) +2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Synchronous mode, the following bits must be kept cleared: +2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN bit in the USART_CR2 register, +2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN, IREN and HDSEL bits in the USART_CR3 register. +2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); +2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); +2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in Synchronous mode */ +2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in LIN Mode +2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In LIN mode, the following bits must be kept cleared: +2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - STOP and CLKEN bits in the USART_CR2 register, +2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, +2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, +2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. +2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also set the UART/USART in LIN mode. +2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : +2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function +2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function +2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function +2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function +2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function +2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function +2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to LIN Mode +2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using +2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions +2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n + ARM GAS /tmp/ccvzubVv.s page 127 + + +2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigLINMode\n +2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 LINEN LL_USART_ConfigLINMode\n +2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigLINMode\n +2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigLINMode\n +2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigLINMode +2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) +2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In LIN mode, the following bits must be kept cleared: +2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - STOP and CLKEN bits in the USART_CR2 register, +2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - IREN, SCEN and HDSEL bits in the USART_CR3 register. +2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); +2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); +2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Set the UART/USART in LIN mode */ +2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_LINEN); +2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode +2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In Half Duplex mode, the following bits must be kept cleared: +2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, +2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - CLKEN bit in the USART_CR2 register, +2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, +2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, +2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also sets the UART/USART in Half Duplex mode. +2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not +2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Half-Duplex mode is supported by the USARTx instance. +2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : +2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function +2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function +2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function +2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function +2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function +2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Half Duplex Mode +2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, ...) should be set using +2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions +2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n +2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n +2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n +2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n +2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigHalfDuplexMode +2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) +2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Half Duplex mode, the following bits must be kept cleared: +2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN and CLKEN bits in the USART_CR2 register, +2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN and IREN bits in the USART_CR3 register. +2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); +2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); +2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in Half Duplex mode */ +2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_HDSEL); + ARM GAS /tmp/ccvzubVv.s page 128 + + +2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Smartcard Mode +2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In Smartcard mode, the following bits must be kept cleared: +2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, +2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, +2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. +2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also configures Stop bits to 1.5 bits and +2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * sets the USART in Smartcard mode (SCEN bit). +2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Clock Output is also enabled (CLKEN). +2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : +2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function +2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function +2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function +2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function +2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function +2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function +2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Smartcard Mode +2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Parity, ...) should be set using +2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions +2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n +2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigSmartcardMode\n +2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigSmartcardMode\n +2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigSmartcardMode\n +2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigSmartcardMode +2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) +2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Smartcard mode, the following bits must be kept cleared: +2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN bit in the USART_CR2 register, +2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - IREN and HDSEL bits in the USART_CR3 register. +2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); +2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); +2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Configure Stop bits to 1.5 bits */ +2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Synchronous mode is activated by default */ +2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); +2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in Smartcard mode */ +2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_SCEN); +2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Irda Mode +2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In IRDA mode, the following bits must be kept cleared: +2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, +2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - STOP and CLKEN bits in the USART_CR2 register, +2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, +2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. +2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This function also sets the UART/USART in IRDA mode (IREN bit). +2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not +2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * IrDA feature is supported by the USARTx instance. +2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : + ARM GAS /tmp/ccvzubVv.s page 129 + + +2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function +2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function +2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function +2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function +2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function +2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function +2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Irda Mode +2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Word length, Power mode, ...) should be set using +2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions +2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n +2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigIrdaMode\n +2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigIrdaMode\n +2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigIrdaMode\n +2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigIrdaMode\n +2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigIrdaMode +2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) +2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In IRDA mode, the following bits must be kept cleared: +2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN, STOP and CLKEN bits in the USART_CR2 register, +2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - SCEN and HDSEL bits in the USART_CR3 register. +2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); +2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); +2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* set the UART/USART in IRDA mode */ +2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_IREN); +2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Perform basic configuration of USART for enabling use in Multi processor Mode +2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (several USARTs connected in a network, one of the USARTs can be the master, +2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * its TX output connected to the RX inputs of the other slaves USARTs). +2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In MultiProcessor mode, the following bits must be kept cleared: +2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - LINEN bit in the USART_CR2 register, +2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - CLKEN bit in the USART_CR2 register, +2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - SCEN bit in the USART_CR3 register, +2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - IREN bit in the USART_CR3 register, +2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - HDSEL bit in the USART_CR3 register. +2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : +2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function +2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function +2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function +2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function +2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function +2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Other remaining configurations items related to Multi processor Mode +2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (as Baud Rate, Wake Up Method, Node address, ...) should be set using +2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * dedicated functions +2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n +2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n +2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 SCEN LL_USART_ConfigMultiProcessMode\n +2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n +2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 IREN LL_USART_ConfigMultiProcessMode +2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + ARM GAS /tmp/ccvzubVv.s page 130 + + +2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) +2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* In Multi Processor mode, the following bits must be kept cleared: +2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - LINEN and CLKEN bits in the USART_CR2 register, +2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** - IREN, SCEN and HDSEL bits in the USART_CR3 register. +2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); +2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); +2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_FLAG_Management FLAG_Management +2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Parity Error Flag is set or not +2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR PE LL_USART_IsActiveFlag_PE +2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) +2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); +2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Framing Error Flag is set or not +2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR FE LL_USART_IsActiveFlag_FE +2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) +2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); +2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Noise error detected Flag is set or not +2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR NE LL_USART_IsActiveFlag_NE +2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) +2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); +2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART OverRun Error Flag is set or not +2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE +2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + ARM GAS /tmp/ccvzubVv.s page 131 + + +2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) +2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); +2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART IDLE line detected Flag is set or not +2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE +2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) +2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); +2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Read Data Register Not Empty Flag is set or not +2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR RXNE LL_USART_IsActiveFlag_RXNE +2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(const USART_TypeDef *USARTx) +2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL); +2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmission Complete Flag is set or not +2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TC LL_USART_IsActiveFlag_TC +2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) +2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); +2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmit Data Register Empty Flag is set or not +2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TXE LL_USART_IsActiveFlag_TXE +2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx) +2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL); +2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART LIN Break Detection Flag is set or not +2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD +2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + ARM GAS /tmp/ccvzubVv.s page 132 + + +2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) +2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); +2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART CTS interrupt Flag is set or not +2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS +2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) +2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); +2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART CTS Flag is set or not +2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS +2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) +2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); +2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receiver Time Out Flag is set or not +2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO +2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) +2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); +2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART End Of Block Flag is set or not +2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB +2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) +2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); +2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Auto-Baud Rate Error Flag is set or not + ARM GAS /tmp/ccvzubVv.s page 133 + + +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or +2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE +2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) +2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); +2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Auto-Baud Rate Flag is set or not +2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or +2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR +2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) +2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); +2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Busy Flag is set or not +2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY +2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) +2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); +2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Character Match Flag is set or not +2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM +2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) +2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); +2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Send Break Flag is set or not +2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK +2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) +2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); +2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ARM GAS /tmp/ccvzubVv.s page 134 + + +2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not +2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU +2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) +2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); +2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) +2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) +2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Wake Up from stop mode Flag is set or not +2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not +2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. +2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP +2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx) +2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); +2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ +2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ +2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not +2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK +2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) +2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); +2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_ISR_REACK) +2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receive Enable Acknowledge Flag is set or not +2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK +2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) +2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_ISR_REACK */ +2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) +2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ +2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not +2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT + ARM GAS /tmp/ccvzubVv.s page 135 + + +2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) +2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); +2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ +2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Parity Error Flag +2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR PECF LL_USART_ClearFlag_PE +2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) +2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_PECF); +2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Framing Error Flag +2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR FECF LL_USART_ClearFlag_FE +2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) +2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_FECF); +2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Noise Error detected Flag +2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR NCF LL_USART_ClearFlag_NE +2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) +2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_NCF); +2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear OverRun Error Flag +2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE +2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) +2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_ORECF); +2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear IDLE line detected Flag +2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE +2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + ARM GAS /tmp/ccvzubVv.s page 136 + + +2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) +2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); +2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Transmission Complete Flag +2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR TCCF LL_USART_ClearFlag_TC +2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) +2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_TCCF); +2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) +2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ +2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Smartcard Transmission Complete Before Guard Time Flag +2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT +2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) +2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF); +2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ +2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear LIN Break Detection Flag +2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD +2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) +2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_LBDCF); +2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear CTS Interrupt Flag +2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS +2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) +2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_CTSCF); +2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + ARM GAS /tmp/ccvzubVv.s page 137 + + +2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Receiver Time Out Flag +2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO +2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) +2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_RTOCF); +2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear End Of Block Flag +2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB +2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) +2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); +2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Character Match Flag +2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR CMCF LL_USART_ClearFlag_CM +2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) +2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_CMCF); +2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) +2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) +2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Clear Wake Up from stop mode Flag +3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not +3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. +3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP +3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) +3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** WRITE_REG(USARTx->ICR, USART_ICR_WUCF); +3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ +3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ +3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ARM GAS /tmp/ccvzubVv.s page 138 + + +3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_IT_Management IT_Management +3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable IDLE Interrupt +3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE +3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) +3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); +3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable RX Not Empty Interrupt +3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE +3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) +3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); +3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Transmission Complete Interrupt +3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TCIE LL_USART_EnableIT_TC +3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) +3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); +3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable TX Empty Interrupt +3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE +3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) +3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE); +3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Parity Error Interrupt +3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PEIE LL_USART_EnableIT_PE +3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) +3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); + ARM GAS /tmp/ccvzubVv.s page 139 + + +3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Character Match Interrupt +3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 CMIE LL_USART_EnableIT_CM +3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) +3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE); +3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Receiver Timeout Interrupt +3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO +3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) +3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE); +3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable End Of Block Interrupt +3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB +3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) +3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE); +3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable LIN Break Detection Interrupt +3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD +3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) +3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_LBDIE); +3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Error Interrupt +3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a fram +3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). +3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 0: Interrupt is inhibited +3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. +3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR + ARM GAS /tmp/ccvzubVv.s page 140 + + +3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) +3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); +3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable CTS Interrupt +3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS +3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) +3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); +3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) +3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) +3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Wake Up from Stop Mode Interrupt +3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not +3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. +3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP +3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) +3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE); +3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ +3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ +3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) +3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ +3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt +3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT +3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) +3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ +3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable IDLE Interrupt +3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE + ARM GAS /tmp/ccvzubVv.s page 141 + + +3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) +3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); +3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable RX Not Empty Interrupt +3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE +3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) +3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); +3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Transmission Complete Interrupt +3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TCIE LL_USART_DisableIT_TC +3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) +3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); +3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable TX Empty Interrupt +3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE +3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) +3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); +3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Parity Error Interrupt +3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PEIE LL_USART_DisableIT_PE +3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) +3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); +3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Character Match Interrupt +3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 CMIE LL_USART_DisableIT_CM +3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + ARM GAS /tmp/ccvzubVv.s page 142 + + +3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) +3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); +3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Receiver Timeout Interrupt +3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO +3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) +3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); +3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable End Of Block Interrupt +3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB +3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) +3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); +3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable LIN Break Detection Interrupt +3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD +3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) +3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); +3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Error Interrupt +3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a fram +3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). +3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 0: Interrupt is inhibited +3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. +3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR +3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) +3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); +3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + ARM GAS /tmp/ccvzubVv.s page 143 + + +3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable CTS Interrupt +3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS +3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) +3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); +3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) +3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) +3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Wake Up from Stop Mode Interrupt +3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not +3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. +3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP +3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) +3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); +3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ +3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ +3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) +3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ +3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt +3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT +3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) +3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ +3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART IDLE Interrupt source is enabled or disabled. +3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE +3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) +3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); +3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + ARM GAS /tmp/ccvzubVv.s page 144 + + +3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. +3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE +3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(const USART_TypeDef *USARTx) +3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1U : 0U); +3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. +3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC +3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) +3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); +3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART TX Empty Interrupt is enabled or disabled. +3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE +3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(const USART_TypeDef *USARTx) +3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1U : 0U); +3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Parity Error Interrupt is enabled or disabled. +3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE +3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) +3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); +3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Character Match Interrupt is enabled or disabled. +3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM +3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) +3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); +3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + ARM GAS /tmp/ccvzubVv.s page 145 + + +3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled. +3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO +3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) +3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); +3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART End Of Block Interrupt is enabled or disabled. +3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB +3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) +3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); +3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. +3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not +3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LIN feature is supported by the USARTx instance. +3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD +3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) +3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); +3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Error Interrupt is enabled or disabled. +3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR +3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) +3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); +3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART CTS Interrupt is enabled or disabled. +3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS +3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) +3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + ARM GAS /tmp/ccvzubVv.s page 146 + + +3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); +3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) +3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) +3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. +3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not +3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. +3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP +3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx) +3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); +3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ +3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ +3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) +3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Function available only on devices supporting Transmit Complete before Guard Time feature */ +3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or +3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not +3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Smartcard feature is supported by the USARTx instance. +3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT +3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) +3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); +3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ +3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_DMA_Management DMA_Management +3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable DMA Mode for reception +3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX +3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) +3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); +3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable DMA Mode for reception + ARM GAS /tmp/ccvzubVv.s page 147 + + +3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX +3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) +3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); +3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if DMA Mode is enabled for reception +3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX +3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) +3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); +3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable DMA Mode for transmission +3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX +3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) +3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); +3559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable DMA Mode for transmission +3563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX +3564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) +3568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); +3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Check if DMA Mode is enabled for transmission +3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX +3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) +3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); +3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable DMA Disabling on Reception Error +3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr +3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + ARM GAS /tmp/ccvzubVv.s page 148 + + +3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) +3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_DDRE); +3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable DMA Disabling on Reception Error +3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr +3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) +3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE); +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if DMA Disabling on Reception Error is disabled +3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr +3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) +3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); +3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Get the data register address used for DMA transfer +3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n +3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr +3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Direction This parameter can be one of the following values: +3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT +3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE +3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Address of data register +3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) +3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t data_reg_addr; +3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) +3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* return address of TDR register */ +3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** data_reg_addr = (uint32_t) &(USARTx->TDR); +3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else +3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* return address of RDR register */ +3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** data_reg_addr = (uint32_t) &(USARTx->RDR); +3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return data_reg_addr; +3642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +3643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ARM GAS /tmp/ccvzubVv.s page 149 + + +3644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} +3646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Data_Management Data_Management +3649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ +3650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +3652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +3653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Read Receiver Data register (Receive Data value, 8 bits) +3654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll RDR RDR LL_USART_ReceiveData8 +3655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +3656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Value between Min_Data=0x00 and Max_Data=0xFF +3657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) + 633 .loc 3 3658 25 view .LVU106 + 634 .LBB67: +3659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +3660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); + 635 .loc 3 3660 3 view .LVU107 + 636 .loc 3 3660 20 is_stmt 0 view .LVU108 + 637 0002 974B ldr r3, .L80 + 638 0004 5A6A ldr r2, [r3, #36] + 639 .loc 3 3660 10 view .LVU109 + 640 0006 D2B2 uxtb r2, r2 + 641 .LVL18: + 642 .loc 3 3660 10 view .LVU110 + 643 .LBE67: + 644 .LBE66: + 645 .loc 1 437 14 discriminator 1 view .LVU111 + 646 0008 964B ldr r3, .L80+4 + 647 000a 1A70 strb r2, [r3] + 438:Src/stm32f7xx_it.c **** switch (UART_rec_incr) + 648 .loc 1 438 5 is_stmt 1 view .LVU112 + 649 000c 964B ldr r3, .L80+8 + 650 000e 1B88 ldrh r3, [r3] + 651 0010 1F2B cmp r3, #31 + 652 0012 00F20B81 bhi .L49 + 653 0016 DFE813F0 tbh [pc, r3, lsl #1] + 654 .L51: + 655 001a 2000 .2byte (.L54-.L51)/2 + 656 001c 2F00 .2byte (.L53-.L51)/2 + 657 001e 0901 .2byte (.L49-.L51)/2 + 658 0020 0901 .2byte (.L49-.L51)/2 + 659 0022 0901 .2byte (.L49-.L51)/2 + 660 0024 0901 .2byte (.L49-.L51)/2 + 661 0026 0901 .2byte (.L49-.L51)/2 + 662 0028 0901 .2byte (.L49-.L51)/2 + 663 002a 0901 .2byte (.L49-.L51)/2 + 664 002c 0901 .2byte (.L49-.L51)/2 + 665 002e 0901 .2byte (.L49-.L51)/2 + 666 0030 0901 .2byte (.L49-.L51)/2 + 667 0032 0901 .2byte (.L49-.L51)/2 + 668 0034 0901 .2byte (.L49-.L51)/2 + 669 0036 0901 .2byte (.L49-.L51)/2 + 670 0038 0901 .2byte (.L49-.L51)/2 + 671 003a 0901 .2byte (.L49-.L51)/2 + ARM GAS /tmp/ccvzubVv.s page 150 + + + 672 003c 0901 .2byte (.L49-.L51)/2 + 673 003e 0901 .2byte (.L49-.L51)/2 + 674 0040 0901 .2byte (.L49-.L51)/2 + 675 0042 0901 .2byte (.L49-.L51)/2 + 676 0044 0901 .2byte (.L49-.L51)/2 + 677 0046 0901 .2byte (.L49-.L51)/2 + 678 0048 0901 .2byte (.L49-.L51)/2 + 679 004a 0901 .2byte (.L49-.L51)/2 + 680 004c 0901 .2byte (.L49-.L51)/2 + 681 004e 0901 .2byte (.L49-.L51)/2 + 682 0050 0901 .2byte (.L49-.L51)/2 + 683 0052 0901 .2byte (.L49-.L51)/2 + 684 0054 9500 .2byte (.L52-.L51)/2 + 685 0056 0901 .2byte (.L49-.L51)/2 + 686 0058 CF00 .2byte (.L50-.L51)/2 + 687 .p2align 1 + 688 .L54: + 439:Src/stm32f7xx_it.c **** { + 440:Src/stm32f7xx_it.c **** case 0: + 441:Src/stm32f7xx_it.c **** TO6_uart = TO6;//Save the time of start rec. command + 689 .loc 1 441 9 view .LVU113 + 690 .loc 1 441 18 is_stmt 0 view .LVU114 + 691 005a 8449 ldr r1, .L80+12 + 692 005c 0868 ldr r0, [r1] + 693 005e 8449 ldr r1, .L80+16 + 694 0060 0860 str r0, [r1] + 442:Src/stm32f7xx_it.c **** flg_tmt = 1;//Set the timeout flag + 695 .loc 1 442 9 is_stmt 1 view .LVU115 + 696 .loc 1 442 17 is_stmt 0 view .LVU116 + 697 0062 8449 ldr r1, .L80+20 + 698 0064 0120 movs r0, #1 + 699 0066 0870 strb r0, [r1] + 443:Src/stm32f7xx_it.c **** UART_header = uart_buf; + 700 .loc 1 443 9 is_stmt 1 view .LVU117 + 701 .loc 1 443 21 is_stmt 0 view .LVU118 + 702 0068 8349 ldr r1, .L80+24 + 703 006a 0A80 strh r2, [r1] @ movhi + 444:Src/stm32f7xx_it.c **** UART_rec_incr++; + 704 .loc 1 444 9 is_stmt 1 view .LVU119 + 705 .loc 1 444 22 is_stmt 0 view .LVU120 + 706 006c 0344 add r3, r3, r0 + 707 006e 7E4A ldr r2, .L80+8 + 708 0070 1380 strh r3, [r2] @ movhi + 445:Src/stm32f7xx_it.c **** break; + 709 .loc 1 445 5 is_stmt 1 view .LVU121 + 710 .L48: + 446:Src/stm32f7xx_it.c **** case 1: + 447:Src/stm32f7xx_it.c **** UART_header += ((uint16_t)uart_buf<<8); + 448:Src/stm32f7xx_it.c **** switch (UART_header) + 449:Src/stm32f7xx_it.c **** { + 450:Src/stm32f7xx_it.c **** case 0x1111: //received long packet + 451:Src/stm32f7xx_it.c **** UART_rec_incr = 2;//timeout flag is still setting! + 452:Src/stm32f7xx_it.c **** break; + 453:Src/stm32f7xx_it.c **** case 0x2222: //Back to default + 454:Src/stm32f7xx_it.c **** UART_rec_incr = 0; + 455:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 456:Src/stm32f7xx_it.c **** CPU_state = DEFAULT_ENABLE; + ARM GAS /tmp/ccvzubVv.s page 151 + + + 457:Src/stm32f7xx_it.c **** break; + 458:Src/stm32f7xx_it.c **** case 0x3333: //Transmith saved DATA + 459:Src/stm32f7xx_it.c **** UART_rec_incr = 0; + 460:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 461:Src/stm32f7xx_it.c **** CPU_state = TRANS_S_ENABLE; + 462:Src/stm32f7xx_it.c **** break; + 463:Src/stm32f7xx_it.c **** case 0x4444: //Received packet + 464:Src/stm32f7xx_it.c **** UART_rec_incr = 0; + 465:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 466:Src/stm32f7xx_it.c **** CPU_state = TRANS_ENABLE; + 467:Src/stm32f7xx_it.c **** break; + 468:Src/stm32f7xx_it.c **** case 0x5555: //Erase saved DATA + 469:Src/stm32f7xx_it.c **** UART_rec_incr = 0; + 470:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 471:Src/stm32f7xx_it.c **** CPU_state = REMOVE_FILE; + 472:Src/stm32f7xx_it.c **** break; + 473:Src/stm32f7xx_it.c **** case 0x6666: //Request state + 474:Src/stm32f7xx_it.c **** UART_rec_incr = 0; + 475:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 476:Src/stm32f7xx_it.c **** CPU_state = STATE; + 477:Src/stm32f7xx_it.c **** break; + 478:Src/stm32f7xx_it.c **** case 0x7777: + 479:Src/stm32f7xx_it.c **** UART_rec_incr = 2;//timeout flag is still setting! + 480:Src/stm32f7xx_it.c **** break; + 481:Src/stm32f7xx_it.c **** default: //error decoding header + 482:Src/stm32f7xx_it.c **** UART_rec_incr = 0; + 483:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 484:Src/stm32f7xx_it.c **** //UART_transmission_request = MESS_01; + 485:Src/stm32f7xx_it.c **** //CPU_state = HALT; + 486:Src/stm32f7xx_it.c **** State_Data[0] |= UART_ERR; + 487:Src/stm32f7xx_it.c **** CPU_state = DEFAULT_ENABLE;//Parking system and send error state! + 488:Src/stm32f7xx_it.c **** break; + 489:Src/stm32f7xx_it.c **** } + 490:Src/stm32f7xx_it.c **** break; + 491:Src/stm32f7xx_it.c **** + 492:Src/stm32f7xx_it.c **** case (CL_8 - 1): + 493:Src/stm32f7xx_it.c **** if (UART_header == 0x1111) + 494:Src/stm32f7xx_it.c **** { + 495:Src/stm32f7xx_it.c **** if ((UART_rec_incr & 0x0001) > 0) + 496:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr >> 1) - 1] += ((uint16_t)(uart_buf)) << 8; + 497:Src/stm32f7xx_it.c **** else + 498:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr >> 1) - 1] = (uint16_t)(uart_buf); + 499:Src/stm32f7xx_it.c **** CPU_state = DECODE_ENABLE; + 500:Src/stm32f7xx_it.c **** UART_rec_incr = 0; + 501:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 502:Src/stm32f7xx_it.c **** } + 503:Src/stm32f7xx_it.c **** else + 504:Src/stm32f7xx_it.c **** { + 505:Src/stm32f7xx_it.c **** if ((UART_rec_incr&0x0001)>0) + 506:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8; + 507:Src/stm32f7xx_it.c **** else + 508:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr>>1)-1] = (uint16_t)(uart_buf); + 509:Src/stm32f7xx_it.c **** UART_rec_incr++; + 510:Src/stm32f7xx_it.c **** UART_transmission_request = NO_MESS; + 511:Src/stm32f7xx_it.c **** } + 512:Src/stm32f7xx_it.c **** break; + 513:Src/stm32f7xx_it.c **** case (TSK_8 - 1): + ARM GAS /tmp/ccvzubVv.s page 152 + + + 514:Src/stm32f7xx_it.c **** if (UART_header == 0x7777) + 515:Src/stm32f7xx_it.c **** { + 516:Src/stm32f7xx_it.c **** if ((UART_rec_incr&0x0001)>0) + 517:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8; + 518:Src/stm32f7xx_it.c **** else + 519:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr>>1)-1] = (uint16_t)(uart_buf); + 520:Src/stm32f7xx_it.c **** CPU_state = DECODE_TASK; + 521:Src/stm32f7xx_it.c **** UART_rec_incr = 0; + 522:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 523:Src/stm32f7xx_it.c **** } + 524:Src/stm32f7xx_it.c **** else + 525:Src/stm32f7xx_it.c **** { + 526:Src/stm32f7xx_it.c **** if ((UART_rec_incr&0x0001)>0) + 527:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8; + 528:Src/stm32f7xx_it.c **** else + 529:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr>>1)-1] = (uint16_t)(uart_buf); + 530:Src/stm32f7xx_it.c **** UART_rec_incr++; + 531:Src/stm32f7xx_it.c **** UART_transmission_request = NO_MESS; + 532:Src/stm32f7xx_it.c **** } + 533:Src/stm32f7xx_it.c **** break; + 534:Src/stm32f7xx_it.c **** default: + 535:Src/stm32f7xx_it.c **** if ((UART_rec_incr&0x0001)>0) + 536:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8; + 537:Src/stm32f7xx_it.c **** else + 538:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr>>1)-1] = (uint16_t)(uart_buf); + 539:Src/stm32f7xx_it.c **** UART_rec_incr++; + 540:Src/stm32f7xx_it.c **** UART_transmission_request = NO_MESS; + 541:Src/stm32f7xx_it.c **** break; + 542:Src/stm32f7xx_it.c **** } + 543:Src/stm32f7xx_it.c **** // HAL_UART_Receive_IT(&huart1, &uart_buf, 1); + 544:Src/stm32f7xx_it.c **** } + 711 .loc 1 544 1 is_stmt 0 view .LVU122 + 712 0072 5DF8044B ldr r4, [sp], #4 + 713 .LCFI7: + 714 .cfi_remember_state + 715 .cfi_restore 4 + 716 .cfi_def_cfa_offset 0 + 717 0076 7047 bx lr + 718 .L53: + 719 .LCFI8: + 720 .cfi_restore_state + 447:Src/stm32f7xx_it.c **** switch (UART_header) + 721 .loc 1 447 9 is_stmt 1 view .LVU123 + 447:Src/stm32f7xx_it.c **** switch (UART_header) + 722 .loc 1 447 21 is_stmt 0 view .LVU124 + 723 0078 7F49 ldr r1, .L80+24 + 724 007a 0B88 ldrh r3, [r1] + 725 007c 03EB0223 add r3, r3, r2, lsl #8 + 726 0080 9BB2 uxth r3, r3 + 727 0082 0B80 strh r3, [r1] @ movhi + 448:Src/stm32f7xx_it.c **** { + 728 .loc 1 448 9 is_stmt 1 view .LVU125 + 729 0084 44F24442 movw r2, #17476 + 730 0088 9342 cmp r3, r2 + 731 008a 37D0 beq .L56 + 732 008c 0FD8 bhi .L57 + 733 008e 42F22222 movw r2, #8738 + ARM GAS /tmp/ccvzubVv.s page 153 + + + 734 0092 9342 cmp r3, r2 + 735 0094 20D0 beq .L58 + 736 0096 43F23332 movw r2, #13107 + 737 009a 9342 cmp r3, r2 + 738 009c 25D0 beq .L59 + 739 009e 41F21112 movw r2, #4369 + 740 00a2 9342 cmp r3, r2 + 741 00a4 40D1 bne .L61 + 451:Src/stm32f7xx_it.c **** break; + 742 .loc 1 451 13 view .LVU126 + 451:Src/stm32f7xx_it.c **** break; + 743 .loc 1 451 27 is_stmt 0 view .LVU127 + 744 00a6 704B ldr r3, .L80+8 + 745 00a8 0222 movs r2, #2 + 746 00aa 1A80 strh r2, [r3] @ movhi + 452:Src/stm32f7xx_it.c **** case 0x2222: //Back to default + 747 .loc 1 452 9 is_stmt 1 view .LVU128 + 748 00ac E1E7 b .L48 + 749 .L57: + 750 00ae 46F26662 movw r2, #26214 + 751 00b2 9342 cmp r3, r2 + 752 00b4 2BD0 beq .L62 + 753 00b6 47F27772 movw r2, #30583 + 754 00ba 9342 cmp r3, r2 + 755 00bc 30D0 beq .L63 + 756 00be 45F25552 movw r2, #21845 + 757 00c2 9342 cmp r3, r2 + 758 00c4 30D1 bne .L61 + 469:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 759 .loc 1 469 13 view .LVU129 + 469:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 760 .loc 1 469 27 is_stmt 0 view .LVU130 + 761 00c6 0023 movs r3, #0 + 762 00c8 674A ldr r2, .L80+8 + 763 00ca 1380 strh r3, [r2] @ movhi + 470:Src/stm32f7xx_it.c **** CPU_state = REMOVE_FILE; + 764 .loc 1 470 13 is_stmt 1 view .LVU131 + 470:Src/stm32f7xx_it.c **** CPU_state = REMOVE_FILE; + 765 .loc 1 470 21 is_stmt 0 view .LVU132 + 766 00cc 694A ldr r2, .L80+20 + 767 00ce 1370 strb r3, [r2] + 471:Src/stm32f7xx_it.c **** break; + 768 .loc 1 471 13 is_stmt 1 view .LVU133 + 471:Src/stm32f7xx_it.c **** break; + 769 .loc 1 471 23 is_stmt 0 view .LVU134 + 770 00d0 6A4B ldr r3, .L80+28 + 771 00d2 0522 movs r2, #5 + 772 00d4 1A70 strb r2, [r3] + 472:Src/stm32f7xx_it.c **** case 0x6666: //Request state + 773 .loc 1 472 9 is_stmt 1 view .LVU135 + 774 00d6 CCE7 b .L48 + 775 .L58: + 454:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 776 .loc 1 454 13 view .LVU136 + 454:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 777 .loc 1 454 27 is_stmt 0 view .LVU137 + 778 00d8 0023 movs r3, #0 + ARM GAS /tmp/ccvzubVv.s page 154 + + + 779 00da 634A ldr r2, .L80+8 + 780 00dc 1380 strh r3, [r2] @ movhi + 455:Src/stm32f7xx_it.c **** CPU_state = DEFAULT_ENABLE; + 781 .loc 1 455 13 is_stmt 1 view .LVU138 + 455:Src/stm32f7xx_it.c **** CPU_state = DEFAULT_ENABLE; + 782 .loc 1 455 21 is_stmt 0 view .LVU139 + 783 00de 654A ldr r2, .L80+20 + 784 00e0 1370 strb r3, [r2] + 456:Src/stm32f7xx_it.c **** break; + 785 .loc 1 456 13 is_stmt 1 view .LVU140 + 456:Src/stm32f7xx_it.c **** break; + 786 .loc 1 456 23 is_stmt 0 view .LVU141 + 787 00e2 664B ldr r3, .L80+28 + 788 00e4 0222 movs r2, #2 + 789 00e6 1A70 strb r2, [r3] + 457:Src/stm32f7xx_it.c **** case 0x3333: //Transmith saved DATA + 790 .loc 1 457 9 is_stmt 1 view .LVU142 + 791 00e8 C3E7 b .L48 + 792 .L59: + 459:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 793 .loc 1 459 13 view .LVU143 + 459:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 794 .loc 1 459 27 is_stmt 0 view .LVU144 + 795 00ea 0023 movs r3, #0 + 796 00ec 5E4A ldr r2, .L80+8 + 797 00ee 1380 strh r3, [r2] @ movhi + 460:Src/stm32f7xx_it.c **** CPU_state = TRANS_S_ENABLE; + 798 .loc 1 460 13 is_stmt 1 view .LVU145 + 460:Src/stm32f7xx_it.c **** CPU_state = TRANS_S_ENABLE; + 799 .loc 1 460 21 is_stmt 0 view .LVU146 + 800 00f0 604A ldr r2, .L80+20 + 801 00f2 1370 strb r3, [r2] + 461:Src/stm32f7xx_it.c **** break; + 802 .loc 1 461 13 is_stmt 1 view .LVU147 + 461:Src/stm32f7xx_it.c **** break; + 803 .loc 1 461 23 is_stmt 0 view .LVU148 + 804 00f4 614B ldr r3, .L80+28 + 805 00f6 0322 movs r2, #3 + 806 00f8 1A70 strb r2, [r3] + 462:Src/stm32f7xx_it.c **** case 0x4444: //Received packet + 807 .loc 1 462 9 is_stmt 1 view .LVU149 + 808 00fa BAE7 b .L48 + 809 .L56: + 464:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 810 .loc 1 464 13 view .LVU150 + 464:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 811 .loc 1 464 27 is_stmt 0 view .LVU151 + 812 00fc 0023 movs r3, #0 + 813 00fe 5A4A ldr r2, .L80+8 + 814 0100 1380 strh r3, [r2] @ movhi + 465:Src/stm32f7xx_it.c **** CPU_state = TRANS_ENABLE; + 815 .loc 1 465 13 is_stmt 1 view .LVU152 + 465:Src/stm32f7xx_it.c **** CPU_state = TRANS_ENABLE; + 816 .loc 1 465 21 is_stmt 0 view .LVU153 + 817 0102 5C4A ldr r2, .L80+20 + 818 0104 1370 strb r3, [r2] + 466:Src/stm32f7xx_it.c **** break; + ARM GAS /tmp/ccvzubVv.s page 155 + + + 819 .loc 1 466 13 is_stmt 1 view .LVU154 + 466:Src/stm32f7xx_it.c **** break; + 820 .loc 1 466 23 is_stmt 0 view .LVU155 + 821 0106 5D4B ldr r3, .L80+28 + 822 0108 0422 movs r2, #4 + 823 010a 1A70 strb r2, [r3] + 467:Src/stm32f7xx_it.c **** case 0x5555: //Erase saved DATA + 824 .loc 1 467 9 is_stmt 1 view .LVU156 + 825 010c B1E7 b .L48 + 826 .L62: + 474:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 827 .loc 1 474 13 view .LVU157 + 474:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 828 .loc 1 474 27 is_stmt 0 view .LVU158 + 829 010e 0023 movs r3, #0 + 830 0110 554A ldr r2, .L80+8 + 831 0112 1380 strh r3, [r2] @ movhi + 475:Src/stm32f7xx_it.c **** CPU_state = STATE; + 832 .loc 1 475 13 is_stmt 1 view .LVU159 + 475:Src/stm32f7xx_it.c **** CPU_state = STATE; + 833 .loc 1 475 21 is_stmt 0 view .LVU160 + 834 0114 574A ldr r2, .L80+20 + 835 0116 1370 strb r3, [r2] + 476:Src/stm32f7xx_it.c **** break; + 836 .loc 1 476 13 is_stmt 1 view .LVU161 + 476:Src/stm32f7xx_it.c **** break; + 837 .loc 1 476 23 is_stmt 0 view .LVU162 + 838 0118 584B ldr r3, .L80+28 + 839 011a 0622 movs r2, #6 + 840 011c 1A70 strb r2, [r3] + 477:Src/stm32f7xx_it.c **** case 0x7777: + 841 .loc 1 477 9 is_stmt 1 view .LVU163 + 842 011e A8E7 b .L48 + 843 .L63: + 479:Src/stm32f7xx_it.c **** break; + 844 .loc 1 479 13 view .LVU164 + 479:Src/stm32f7xx_it.c **** break; + 845 .loc 1 479 27 is_stmt 0 view .LVU165 + 846 0120 514B ldr r3, .L80+8 + 847 0122 0222 movs r2, #2 + 848 0124 1A80 strh r2, [r3] @ movhi + 480:Src/stm32f7xx_it.c **** default: //error decoding header + 849 .loc 1 480 13 is_stmt 1 view .LVU166 + 850 0126 A4E7 b .L48 + 851 .L61: + 482:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 852 .loc 1 482 13 view .LVU167 + 482:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 853 .loc 1 482 27 is_stmt 0 view .LVU168 + 854 0128 0023 movs r3, #0 + 855 012a 4F4A ldr r2, .L80+8 + 856 012c 1380 strh r3, [r2] @ movhi + 483:Src/stm32f7xx_it.c **** //UART_transmission_request = MESS_01; + 857 .loc 1 483 13 is_stmt 1 view .LVU169 + 483:Src/stm32f7xx_it.c **** //UART_transmission_request = MESS_01; + 858 .loc 1 483 21 is_stmt 0 view .LVU170 + 859 012e 514A ldr r2, .L80+20 + ARM GAS /tmp/ccvzubVv.s page 156 + + + 860 0130 1370 strb r3, [r2] + 486:Src/stm32f7xx_it.c **** CPU_state = DEFAULT_ENABLE;//Parking system and send error state! + 861 .loc 1 486 13 is_stmt 1 view .LVU171 + 486:Src/stm32f7xx_it.c **** CPU_state = DEFAULT_ENABLE;//Parking system and send error state! + 862 .loc 1 486 23 is_stmt 0 view .LVU172 + 863 0132 534A ldr r2, .L80+32 + 864 0134 1378 ldrb r3, [r2] @ zero_extendqisi2 + 486:Src/stm32f7xx_it.c **** CPU_state = DEFAULT_ENABLE;//Parking system and send error state! + 865 .loc 1 486 27 view .LVU173 + 866 0136 43F00203 orr r3, r3, #2 + 867 013a 1370 strb r3, [r2] + 487:Src/stm32f7xx_it.c **** break; + 868 .loc 1 487 13 is_stmt 1 view .LVU174 + 487:Src/stm32f7xx_it.c **** break; + 869 .loc 1 487 23 is_stmt 0 view .LVU175 + 870 013c 4F4B ldr r3, .L80+28 + 871 013e 0222 movs r2, #2 + 872 0140 1A70 strb r2, [r3] + 488:Src/stm32f7xx_it.c **** } + 873 .loc 1 488 9 is_stmt 1 view .LVU176 + 874 0142 96E7 b .L48 + 875 .L52: + 493:Src/stm32f7xx_it.c **** { + 876 .loc 1 493 9 view .LVU177 + 493:Src/stm32f7xx_it.c **** { + 877 .loc 1 493 25 is_stmt 0 view .LVU178 + 878 0144 4C49 ldr r1, .L80+24 + 879 0146 0888 ldrh r0, [r1] + 493:Src/stm32f7xx_it.c **** { + 880 .loc 1 493 12 view .LVU179 + 881 0148 41F21111 movw r1, #4369 + 882 014c 8842 cmp r0, r1 + 883 014e 12D0 beq .L78 + 505:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8; + 884 .loc 1 505 13 is_stmt 1 view .LVU180 + 505:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8; + 885 .loc 1 505 16 is_stmt 0 view .LVU181 + 886 0150 13F0010F tst r3, #1 + 887 0154 2AD0 beq .L68 + 506:Src/stm32f7xx_it.c **** else + 888 .loc 1 506 17 is_stmt 1 view .LVU182 + 506:Src/stm32f7xx_it.c **** else + 889 .loc 1 506 24 is_stmt 0 view .LVU183 + 890 0156 5908 lsrs r1, r3, #1 + 891 0158 0139 subs r1, r1, #1 + 892 015a 4A4C ldr r4, .L80+36 + 893 015c 34F81100 ldrh r0, [r4, r1, lsl #1] + 506:Src/stm32f7xx_it.c **** else + 894 .loc 1 506 47 view .LVU184 + 895 0160 00EB0222 add r2, r0, r2, lsl #8 + 896 0164 24F81120 strh r2, [r4, r1, lsl #1] @ movhi + 897 .L69: + 509:Src/stm32f7xx_it.c **** UART_transmission_request = NO_MESS; + 898 .loc 1 509 12 is_stmt 1 view .LVU185 + 509:Src/stm32f7xx_it.c **** UART_transmission_request = NO_MESS; + 899 .loc 1 509 25 is_stmt 0 view .LVU186 + 900 0168 0133 adds r3, r3, #1 + ARM GAS /tmp/ccvzubVv.s page 157 + + + 901 016a 3F4A ldr r2, .L80+8 + 902 016c 1380 strh r3, [r2] @ movhi + 510:Src/stm32f7xx_it.c **** } + 903 .loc 1 510 12 is_stmt 1 view .LVU187 + 510:Src/stm32f7xx_it.c **** } + 904 .loc 1 510 38 is_stmt 0 view .LVU188 + 905 016e 464B ldr r3, .L80+40 + 906 0170 0022 movs r2, #0 + 907 0172 1A70 strb r2, [r3] + 908 0174 7DE7 b .L48 + 909 .L78: + 495:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr >> 1) - 1] += ((uint16_t)(uart_buf)) << 8; + 910 .loc 1 495 13 is_stmt 1 view .LVU189 + 495:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr >> 1) - 1] += ((uint16_t)(uart_buf)) << 8; + 911 .loc 1 495 16 is_stmt 0 view .LVU190 + 912 0176 13F0010F tst r3, #1 + 913 017a 11D0 beq .L66 + 496:Src/stm32f7xx_it.c **** else + 914 .loc 1 496 17 is_stmt 1 view .LVU191 + 496:Src/stm32f7xx_it.c **** else + 915 .loc 1 496 24 is_stmt 0 view .LVU192 + 916 017c 5B08 lsrs r3, r3, #1 + 917 017e 013B subs r3, r3, #1 + 918 0180 4048 ldr r0, .L80+36 + 919 0182 30F81310 ldrh r1, [r0, r3, lsl #1] + 496:Src/stm32f7xx_it.c **** else + 920 .loc 1 496 51 view .LVU193 + 921 0186 01EB0222 add r2, r1, r2, lsl #8 + 922 018a 20F81320 strh r2, [r0, r3, lsl #1] @ movhi + 923 .L67: + 499:Src/stm32f7xx_it.c **** UART_rec_incr = 0; + 924 .loc 1 499 13 is_stmt 1 view .LVU194 + 499:Src/stm32f7xx_it.c **** UART_rec_incr = 0; + 925 .loc 1 499 23 is_stmt 0 view .LVU195 + 926 018e 3B4B ldr r3, .L80+28 + 927 0190 0122 movs r2, #1 + 928 0192 1A70 strb r2, [r3] + 500:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 929 .loc 1 500 13 is_stmt 1 view .LVU196 + 500:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 930 .loc 1 500 27 is_stmt 0 view .LVU197 + 931 0194 0023 movs r3, #0 + 932 0196 344A ldr r2, .L80+8 + 933 0198 1380 strh r3, [r2] @ movhi + 501:Src/stm32f7xx_it.c **** } + 934 .loc 1 501 13 is_stmt 1 view .LVU198 + 501:Src/stm32f7xx_it.c **** } + 935 .loc 1 501 21 is_stmt 0 view .LVU199 + 936 019a 364A ldr r2, .L80+20 + 937 019c 1370 strb r3, [r2] + 938 019e 68E7 b .L48 + 939 .L66: + 498:Src/stm32f7xx_it.c **** CPU_state = DECODE_ENABLE; + 940 .loc 1 498 17 is_stmt 1 view .LVU200 + 498:Src/stm32f7xx_it.c **** CPU_state = DECODE_ENABLE; + 941 .loc 1 498 40 is_stmt 0 view .LVU201 + 942 01a0 5B08 lsrs r3, r3, #1 + ARM GAS /tmp/ccvzubVv.s page 158 + + + 498:Src/stm32f7xx_it.c **** CPU_state = DECODE_ENABLE; + 943 .loc 1 498 46 view .LVU202 + 944 01a2 013B subs r3, r3, #1 + 498:Src/stm32f7xx_it.c **** CPU_state = DECODE_ENABLE; + 945 .loc 1 498 51 view .LVU203 + 946 01a4 3749 ldr r1, .L80+36 + 947 01a6 21F81320 strh r2, [r1, r3, lsl #1] @ movhi + 948 01aa F0E7 b .L67 + 949 .L68: + 508:Src/stm32f7xx_it.c **** UART_rec_incr++; + 950 .loc 1 508 17 is_stmt 1 view .LVU204 + 508:Src/stm32f7xx_it.c **** UART_rec_incr++; + 951 .loc 1 508 39 is_stmt 0 view .LVU205 + 952 01ac 5908 lsrs r1, r3, #1 + 508:Src/stm32f7xx_it.c **** UART_rec_incr++; + 953 .loc 1 508 43 view .LVU206 + 954 01ae 0139 subs r1, r1, #1 + 508:Src/stm32f7xx_it.c **** UART_rec_incr++; + 955 .loc 1 508 47 view .LVU207 + 956 01b0 3448 ldr r0, .L80+36 + 957 01b2 20F81120 strh r2, [r0, r1, lsl #1] @ movhi + 958 01b6 D7E7 b .L69 + 959 .L50: + 514:Src/stm32f7xx_it.c **** { + 960 .loc 1 514 9 is_stmt 1 view .LVU208 + 514:Src/stm32f7xx_it.c **** { + 961 .loc 1 514 25 is_stmt 0 view .LVU209 + 962 01b8 2F49 ldr r1, .L80+24 + 963 01ba 0888 ldrh r0, [r1] + 514:Src/stm32f7xx_it.c **** { + 964 .loc 1 514 12 view .LVU210 + 965 01bc 47F27771 movw r1, #30583 + 966 01c0 8842 cmp r0, r1 + 967 01c2 12D0 beq .L79 + 526:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8; + 968 .loc 1 526 13 is_stmt 1 view .LVU211 + 526:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8; + 969 .loc 1 526 16 is_stmt 0 view .LVU212 + 970 01c4 13F0010F tst r3, #1 + 971 01c8 2AD0 beq .L73 + 527:Src/stm32f7xx_it.c **** else + 972 .loc 1 527 17 is_stmt 1 view .LVU213 + 527:Src/stm32f7xx_it.c **** else + 973 .loc 1 527 24 is_stmt 0 view .LVU214 + 974 01ca 5908 lsrs r1, r3, #1 + 975 01cc 0139 subs r1, r1, #1 + 976 01ce 2D4C ldr r4, .L80+36 + 977 01d0 34F81100 ldrh r0, [r4, r1, lsl #1] + 527:Src/stm32f7xx_it.c **** else + 978 .loc 1 527 47 view .LVU215 + 979 01d4 00EB0222 add r2, r0, r2, lsl #8 + 980 01d8 24F81120 strh r2, [r4, r1, lsl #1] @ movhi + 981 .L74: + 530:Src/stm32f7xx_it.c **** UART_transmission_request = NO_MESS; + 982 .loc 1 530 13 is_stmt 1 view .LVU216 + 530:Src/stm32f7xx_it.c **** UART_transmission_request = NO_MESS; + 983 .loc 1 530 26 is_stmt 0 view .LVU217 + ARM GAS /tmp/ccvzubVv.s page 159 + + + 984 01dc 0133 adds r3, r3, #1 + 985 01de 224A ldr r2, .L80+8 + 986 01e0 1380 strh r3, [r2] @ movhi + 531:Src/stm32f7xx_it.c **** } + 987 .loc 1 531 13 is_stmt 1 view .LVU218 + 531:Src/stm32f7xx_it.c **** } + 988 .loc 1 531 39 is_stmt 0 view .LVU219 + 989 01e2 294B ldr r3, .L80+40 + 990 01e4 0022 movs r2, #0 + 991 01e6 1A70 strb r2, [r3] + 992 01e8 43E7 b .L48 + 993 .L79: + 516:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8; + 994 .loc 1 516 13 is_stmt 1 view .LVU220 + 516:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8; + 995 .loc 1 516 16 is_stmt 0 view .LVU221 + 996 01ea 13F0010F tst r3, #1 + 997 01ee 11D0 beq .L71 + 517:Src/stm32f7xx_it.c **** else + 998 .loc 1 517 16 is_stmt 1 view .LVU222 + 517:Src/stm32f7xx_it.c **** else + 999 .loc 1 517 23 is_stmt 0 view .LVU223 + 1000 01f0 5B08 lsrs r3, r3, #1 + 1001 01f2 013B subs r3, r3, #1 + 1002 01f4 2348 ldr r0, .L80+36 + 1003 01f6 30F81310 ldrh r1, [r0, r3, lsl #1] + 517:Src/stm32f7xx_it.c **** else + 1004 .loc 1 517 46 view .LVU224 + 1005 01fa 01EB0222 add r2, r1, r2, lsl #8 + 1006 01fe 20F81320 strh r2, [r0, r3, lsl #1] @ movhi + 1007 .L72: + 520:Src/stm32f7xx_it.c **** UART_rec_incr = 0; + 1008 .loc 1 520 13 is_stmt 1 view .LVU225 + 520:Src/stm32f7xx_it.c **** UART_rec_incr = 0; + 1009 .loc 1 520 23 is_stmt 0 view .LVU226 + 1010 0202 1E4B ldr r3, .L80+28 + 1011 0204 0822 movs r2, #8 + 1012 0206 1A70 strb r2, [r3] + 521:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 1013 .loc 1 521 13 is_stmt 1 view .LVU227 + 521:Src/stm32f7xx_it.c **** flg_tmt = 0;//Reset the timeout flag + 1014 .loc 1 521 27 is_stmt 0 view .LVU228 + 1015 0208 0023 movs r3, #0 + 1016 020a 174A ldr r2, .L80+8 + 1017 020c 1380 strh r3, [r2] @ movhi + 522:Src/stm32f7xx_it.c **** } + 1018 .loc 1 522 13 is_stmt 1 view .LVU229 + 522:Src/stm32f7xx_it.c **** } + 1019 .loc 1 522 21 is_stmt 0 view .LVU230 + 1020 020e 194A ldr r2, .L80+20 + 1021 0210 1370 strb r3, [r2] + 1022 0212 2EE7 b .L48 + 1023 .L71: + 519:Src/stm32f7xx_it.c **** CPU_state = DECODE_TASK; + 1024 .loc 1 519 17 is_stmt 1 view .LVU231 + 519:Src/stm32f7xx_it.c **** CPU_state = DECODE_TASK; + 1025 .loc 1 519 39 is_stmt 0 view .LVU232 + ARM GAS /tmp/ccvzubVv.s page 160 + + + 1026 0214 5B08 lsrs r3, r3, #1 + 519:Src/stm32f7xx_it.c **** CPU_state = DECODE_TASK; + 1027 .loc 1 519 43 view .LVU233 + 1028 0216 013B subs r3, r3, #1 + 519:Src/stm32f7xx_it.c **** CPU_state = DECODE_TASK; + 1029 .loc 1 519 47 view .LVU234 + 1030 0218 1A49 ldr r1, .L80+36 + 1031 021a 21F81320 strh r2, [r1, r3, lsl #1] @ movhi + 1032 021e F0E7 b .L72 + 1033 .L73: + 529:Src/stm32f7xx_it.c **** UART_rec_incr++; + 1034 .loc 1 529 17 is_stmt 1 view .LVU235 + 529:Src/stm32f7xx_it.c **** UART_rec_incr++; + 1035 .loc 1 529 39 is_stmt 0 view .LVU236 + 1036 0220 5908 lsrs r1, r3, #1 + 529:Src/stm32f7xx_it.c **** UART_rec_incr++; + 1037 .loc 1 529 43 view .LVU237 + 1038 0222 0139 subs r1, r1, #1 + 529:Src/stm32f7xx_it.c **** UART_rec_incr++; + 1039 .loc 1 529 47 view .LVU238 + 1040 0224 1748 ldr r0, .L80+36 + 1041 0226 20F81120 strh r2, [r0, r1, lsl #1] @ movhi + 1042 022a D7E7 b .L74 + 1043 .L49: + 535:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8; + 1044 .loc 1 535 9 is_stmt 1 view .LVU239 + 535:Src/stm32f7xx_it.c **** COMMAND[(UART_rec_incr>>1)-1] += ((uint16_t)(uart_buf))<<8; + 1045 .loc 1 535 12 is_stmt 0 view .LVU240 + 1046 022c 13F0010F tst r3, #1 + 1047 0230 0FD0 beq .L75 + 536:Src/stm32f7xx_it.c **** else + 1048 .loc 1 536 13 is_stmt 1 view .LVU241 + 536:Src/stm32f7xx_it.c **** else + 1049 .loc 1 536 20 is_stmt 0 view .LVU242 + 1050 0232 5908 lsrs r1, r3, #1 + 1051 0234 0139 subs r1, r1, #1 + 1052 0236 134C ldr r4, .L80+36 + 1053 0238 34F81100 ldrh r0, [r4, r1, lsl #1] + 536:Src/stm32f7xx_it.c **** else + 1054 .loc 1 536 43 view .LVU243 + 1055 023c 00EB0222 add r2, r0, r2, lsl #8 + 1056 0240 24F81120 strh r2, [r4, r1, lsl #1] @ movhi + 1057 .L76: + 539:Src/stm32f7xx_it.c **** UART_transmission_request = NO_MESS; + 1058 .loc 1 539 9 is_stmt 1 view .LVU244 + 539:Src/stm32f7xx_it.c **** UART_transmission_request = NO_MESS; + 1059 .loc 1 539 22 is_stmt 0 view .LVU245 + 1060 0244 0133 adds r3, r3, #1 + 1061 0246 084A ldr r2, .L80+8 + 1062 0248 1380 strh r3, [r2] @ movhi + 540:Src/stm32f7xx_it.c **** break; + 1063 .loc 1 540 9 is_stmt 1 view .LVU246 + 540:Src/stm32f7xx_it.c **** break; + 1064 .loc 1 540 35 is_stmt 0 view .LVU247 + 1065 024a 0F4B ldr r3, .L80+40 + 1066 024c 0022 movs r2, #0 + 1067 024e 1A70 strb r2, [r3] + ARM GAS /tmp/ccvzubVv.s page 161 + + + 541:Src/stm32f7xx_it.c **** } + 1068 .loc 1 541 5 is_stmt 1 view .LVU248 + 1069 .loc 1 544 1 is_stmt 0 view .LVU249 + 1070 0250 0FE7 b .L48 + 1071 .L75: + 538:Src/stm32f7xx_it.c **** UART_rec_incr++; + 1072 .loc 1 538 13 is_stmt 1 view .LVU250 + 538:Src/stm32f7xx_it.c **** UART_rec_incr++; + 1073 .loc 1 538 35 is_stmt 0 view .LVU251 + 1074 0252 5908 lsrs r1, r3, #1 + 538:Src/stm32f7xx_it.c **** UART_rec_incr++; + 1075 .loc 1 538 39 view .LVU252 + 1076 0254 0139 subs r1, r1, #1 + 538:Src/stm32f7xx_it.c **** UART_rec_incr++; + 1077 .loc 1 538 43 view .LVU253 + 1078 0256 0B48 ldr r0, .L80+36 + 1079 0258 20F81120 strh r2, [r0, r1, lsl #1] @ movhi + 1080 025c F2E7 b .L76 + 1081 .L81: + 1082 025e 00BF .align 2 + 1083 .L80: + 1084 0260 00100140 .word 1073811456 + 1085 0264 00000000 .word uart_buf + 1086 0268 00000000 .word UART_rec_incr + 1087 026c 00000000 .word TO6 + 1088 0270 00000000 .word TO6_uart + 1089 0274 00000000 .word flg_tmt + 1090 0278 00000000 .word UART_header + 1091 027c 00000000 .word CPU_state + 1092 0280 00000000 .word State_Data + 1093 0284 00000000 .word COMMAND + 1094 0288 00000000 .word UART_transmission_request + 1095 .cfi_endproc + 1096 .LFE1202: + 1098 .section .text.USART1_IRQHandler,"ax",%progbits + 1099 .align 1 + 1100 .global USART1_IRQHandler + 1101 .syntax unified + 1102 .thumb + 1103 .thumb_func + 1105 USART1_IRQHandler: + 1106 .LFB1196: + 277:Src/stm32f7xx_it.c **** /* USER CODE BEGIN USART1_IRQn 0 */ + 1107 .loc 1 277 1 is_stmt 1 view -0 + 1108 .cfi_startproc + 1109 @ args = 0, pretend = 0, frame = 8 + 1110 @ frame_needed = 0, uses_anonymous_args = 0 + 1111 0000 00B5 push {lr} + 1112 .LCFI9: + 1113 .cfi_def_cfa_offset 4 + 1114 .cfi_offset 14, -4 + 1115 0002 83B0 sub sp, sp, #12 + 1116 .LCFI10: + 1117 .cfi_def_cfa_offset 16 + 279:Src/stm32f7xx_it.c **** if(LL_USART_IsActiveFlag_RXNE(USART1) && LL_USART_IsEnabledIT_RXNE(USART1)) + 1118 .loc 1 279 3 view .LVU255 + 280:Src/stm32f7xx_it.c **** { + ARM GAS /tmp/ccvzubVv.s page 162 + + + 1119 .loc 1 280 3 view .LVU256 + 1120 .LVL19: + 1121 .LBB68: + 1122 .LBI68: +2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 1123 .loc 3 2640 26 view .LVU257 + 1124 .LBB69: +2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1125 .loc 3 2642 3 view .LVU258 +2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1126 .loc 3 2642 12 is_stmt 0 view .LVU259 + 1127 0004 304B ldr r3, .L98 + 1128 0006 DB69 ldr r3, [r3, #28] +2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1129 .loc 3 2642 77 view .LVU260 + 1130 0008 13F0200F tst r3, #32 + 1131 000c 07D0 beq .L83 + 1132 .LVL20: +2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1133 .loc 3 2642 77 view .LVU261 + 1134 .LBE69: + 1135 .LBE68: + 1136 .LBB70: + 1137 .LBI70: +3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 1138 .loc 3 3366 26 is_stmt 1 view .LVU262 + 1139 .LBB71: +3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1140 .loc 3 3368 3 view .LVU263 +3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1141 .loc 3 3368 12 is_stmt 0 view .LVU264 + 1142 000e 2E4B ldr r3, .L98 + 1143 0010 1B68 ldr r3, [r3] +3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1144 .loc 3 3368 80 view .LVU265 + 1145 0012 13F0200F tst r3, #32 + 1146 0016 02D0 beq .L83 + 1147 .LVL21: +3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1148 .loc 3 3368 80 view .LVU266 + 1149 .LBE71: + 1150 .LBE70: + 282:Src/stm32f7xx_it.c **** } + 1151 .loc 1 282 5 is_stmt 1 view .LVU267 + 1152 0018 FFF7FEFF bl UART_RxCpltCallback + 1153 .LVL22: + 1154 001c 33E0 b .L82 + 1155 .L83: + 286:Src/stm32f7xx_it.c **** { + 1156 .loc 1 286 5 view .LVU268 + 1157 .LVL23: + 1158 .LBB72: + 1159 .LBI72: +2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 1160 .loc 3 2618 26 view .LVU269 + 1161 .LBB73: +2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + ARM GAS /tmp/ccvzubVv.s page 163 + + + 1162 .loc 3 2620 3 view .LVU270 +2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1163 .loc 3 2620 12 is_stmt 0 view .LVU271 + 1164 001e 2A4B ldr r3, .L98 + 1165 0020 DB69 ldr r3, [r3, #28] +2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1166 .loc 3 2620 75 view .LVU272 + 1167 0022 13F0080F tst r3, #8 + 1168 0026 25D1 bne .L85 + 1169 .LVL24: +2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1170 .loc 3 2620 75 view .LVU273 + 1171 .LBE73: + 1172 .LBE72: + 291:Src/stm32f7xx_it.c **** { + 1173 .loc 1 291 10 is_stmt 1 view .LVU274 + 1174 .LBB74: + 1175 .LBI74: +2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 1176 .loc 3 2596 26 view .LVU275 + 1177 .LBB75: +2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1178 .loc 3 2598 3 view .LVU276 +2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1179 .loc 3 2598 12 is_stmt 0 view .LVU277 + 1180 0028 274B ldr r3, .L98 + 1181 002a DB69 ldr r3, [r3, #28] +2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1182 .loc 3 2598 73 view .LVU278 + 1183 002c 13F0020F tst r3, #2 + 1184 0030 2CD1 bne .L86 + 1185 .LVL25: +2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1186 .loc 3 2598 73 view .LVU279 + 1187 .LBE75: + 1188 .LBE74: + 296:Src/stm32f7xx_it.c **** { + 1189 .loc 1 296 10 is_stmt 1 view .LVU280 + 1190 .LBB76: + 1191 .LBI76: +2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 1192 .loc 3 2607 26 view .LVU281 + 1193 .LBB77: +2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1194 .loc 3 2609 3 view .LVU282 +2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1195 .loc 3 2609 12 is_stmt 0 view .LVU283 + 1196 0032 254B ldr r3, .L98 + 1197 0034 DB69 ldr r3, [r3, #28] +2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1198 .loc 3 2609 73 view .LVU284 + 1199 0036 13F0040F tst r3, #4 + 1200 003a 31D1 bne .L88 + 1201 .LVL26: +2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1202 .loc 3 2609 73 view .LVU285 + 1203 .LBE77: + ARM GAS /tmp/ccvzubVv.s page 164 + + + 1204 .LBE76: + 301:Src/stm32f7xx_it.c **** { + 1205 .loc 1 301 10 is_stmt 1 view .LVU286 + 1206 .LBB78: + 1207 .LBI78: +2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 1208 .loc 3 2585 26 view .LVU287 + 1209 .LBB79: +2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1210 .loc 3 2587 3 view .LVU288 +2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1211 .loc 3 2587 12 is_stmt 0 view .LVU289 + 1212 003c 224B ldr r3, .L98 + 1213 003e DB69 ldr r3, [r3, #28] +2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1214 .loc 3 2587 73 view .LVU290 + 1215 0040 13F0010F tst r3, #1 + 1216 0044 36D1 bne .L90 + 1217 .LVL27: +2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1218 .loc 3 2587 73 view .LVU291 + 1219 .LBE79: + 1220 .LBE78: + 308:Src/stm32f7xx_it.c **** { + 1221 .loc 1 308 7 is_stmt 1 view .LVU292 + 1222 .LBB80: + 1223 .LBI80: +2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 1224 .loc 3 2651 26 view .LVU293 + 1225 .LBB81: +2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1226 .loc 3 2653 3 view .LVU294 +2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1227 .loc 3 2653 12 is_stmt 0 view .LVU295 + 1228 0046 214B ldr r3, .L98+4 + 1229 0048 DB69 ldr r3, [r3, #28] +2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1230 .loc 3 2653 73 view .LVU296 + 1231 004a 13F0400F tst r3, #64 + 1232 004e 1AD0 beq .L82 + 1233 .LVL28: +2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1234 .loc 3 2653 73 view .LVU297 + 1235 .LBE81: + 1236 .LBE80: + 1237 .LBB82: + 1238 .LBI82: +3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 1239 .loc 3 3377 26 is_stmt 1 view .LVU298 + 1240 .LBB83: +3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1241 .loc 3 3379 3 view .LVU299 +3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1242 .loc 3 3379 12 is_stmt 0 view .LVU300 + 1243 0050 1E4B ldr r3, .L98+4 + 1244 0052 1B68 ldr r3, [r3] +3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + ARM GAS /tmp/ccvzubVv.s page 165 + + + 1245 .loc 3 3379 77 view .LVU301 + 1246 0054 13F0400F tst r3, #64 + 1247 0058 15D0 beq .L82 + 1248 .LVL29: +3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1249 .loc 3 3379 77 view .LVU302 + 1250 .LBE83: + 1251 .LBE82: + 310:Src/stm32f7xx_it.c **** //test_counter += 1; + 1252 .loc 1 310 9 is_stmt 1 view .LVU303 + 1253 .LBB84: + 1254 .LBI84: +2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 1255 .loc 3 2916 22 view .LVU304 + 1256 .LBB85: +2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1257 .loc 3 2918 3 view .LVU305 + 1258 005a 1B4B ldr r3, .L98 + 1259 005c 4022 movs r2, #64 + 1260 005e 1A62 str r2, [r3, #32] + 1261 .LVL30: +2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1262 .loc 3 2918 3 is_stmt 0 view .LVU306 + 1263 .LBE85: + 1264 .LBE84: + 313:Src/stm32f7xx_it.c **** //UART_transmission_busy = 0; + 1265 .loc 1 313 9 is_stmt 1 view .LVU307 + 1266 .LBB86: + 1267 .LBI86: +3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 1268 .loc 3 3213 22 view .LVU308 + 1269 .L93: +3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1270 .loc 3 3215 3 discriminator 1 view .LVU309 + 1271 .LBB87: +3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1272 .loc 3 3215 3 discriminator 1 view .LVU310 +3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1273 .loc 3 3215 3 discriminator 1 view .LVU311 +3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1274 .loc 3 3215 3 discriminator 1 view .LVU312 + 1275 .LBB88: + 1276 .LBI88: + 1277 .file 4 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + ARM GAS /tmp/ccvzubVv.s page 166 + + + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + ARM GAS /tmp/ccvzubVv.s page 167 + + + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + ARM GAS /tmp/ccvzubVv.s page 168 + + + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccvzubVv.s page 169 + + + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccvzubVv.s page 170 + + + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + ARM GAS /tmp/ccvzubVv.s page 171 + + + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccvzubVv.s page 172 + + + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + ARM GAS /tmp/ccvzubVv.s page 173 + + + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccvzubVv.s page 174 + + + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccvzubVv.s page 175 + + + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccvzubVv.s page 176 + + + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + ARM GAS /tmp/ccvzubVv.s page 177 + + + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + ARM GAS /tmp/ccvzubVv.s page 178 + + + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccvzubVv.s page 179 + + + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccvzubVv.s page 180 + + + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + ARM GAS /tmp/ccvzubVv.s page 181 + + + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 881:Drivers/CMSIS/Include/cmsis_gcc.h **** + 882:Drivers/CMSIS/Include/cmsis_gcc.h **** + 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier + 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. + 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) + 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); + 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 892:Drivers/CMSIS/Include/cmsis_gcc.h **** + 893:Drivers/CMSIS/Include/cmsis_gcc.h **** + 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) + 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 + 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) + 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); + 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 906:Drivers/CMSIS/Include/cmsis_gcc.h **** + 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 911:Drivers/CMSIS/Include/cmsis_gcc.h **** + 912:Drivers/CMSIS/Include/cmsis_gcc.h **** + 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes + 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) + 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 922:Drivers/CMSIS/Include/cmsis_gcc.h **** + 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccvzubVv.s page 182 + + + 926:Drivers/CMSIS/Include/cmsis_gcc.h **** + 927:Drivers/CMSIS/Include/cmsis_gcc.h **** + 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam + 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); + 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; + 940:Drivers/CMSIS/Include/cmsis_gcc.h **** + 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 945:Drivers/CMSIS/Include/cmsis_gcc.h **** + 946:Drivers/CMSIS/Include/cmsis_gcc.h **** + 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) + 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v + 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate + 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate + 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value + 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) + 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; + 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) + 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; + 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); + 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 963:Drivers/CMSIS/Include/cmsis_gcc.h **** + 964:Drivers/CMSIS/Include/cmsis_gcc.h **** + 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint + 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. + 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula + 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. + 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break + 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) + 973:Drivers/CMSIS/Include/cmsis_gcc.h **** + 974:Drivers/CMSIS/Include/cmsis_gcc.h **** + 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value + 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. + 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) + 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccvzubVv.s page 183 + + + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 984:Drivers/CMSIS/Include/cmsis_gcc.h **** + 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + 991:Drivers/CMSIS/Include/cmsis_gcc.h **** + 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ + 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) + 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; + 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; + 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; + 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ +1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; +1002:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1003:Drivers/CMSIS/Include/cmsis_gcc.h **** +1004:Drivers/CMSIS/Include/cmsis_gcc.h **** +1005:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1006:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Count leading zeros +1007:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Counts the number of leading zeros of a data value. +1008:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to count the leading zeros +1009:Drivers/CMSIS/Include/cmsis_gcc.h **** \return number of leading zeros in value +1010:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1011:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CLZ (uint8_t)__builtin_clz +1012:Drivers/CMSIS/Include/cmsis_gcc.h **** +1013:Drivers/CMSIS/Include/cmsis_gcc.h **** +1014:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ +1015:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ +1016:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ +1017:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +1018:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1019:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (8 bit) +1020:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 8 bit value. +1021:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data +1022:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) +1023:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1024:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +1025:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1026:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; +1027:Drivers/CMSIS/Include/cmsis_gcc.h **** +1028:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) +1029:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +1030:Drivers/CMSIS/Include/cmsis_gcc.h **** #else +1031:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not +1032:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. +1033:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1034:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +1035:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1036:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */ +1037:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1038:Drivers/CMSIS/Include/cmsis_gcc.h **** +1039:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccvzubVv.s page 184 + + +1040:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1041:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (16 bit) +1042:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 16 bit values. +1043:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data +1044:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) +1045:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1046:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +1047:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1048:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; +1049:Drivers/CMSIS/Include/cmsis_gcc.h **** +1050:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) +1051:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +1052:Drivers/CMSIS/Include/cmsis_gcc.h **** #else +1053:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not +1054:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. +1055:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1056:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +1057:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1058:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */ +1059:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1060:Drivers/CMSIS/Include/cmsis_gcc.h **** +1061:Drivers/CMSIS/Include/cmsis_gcc.h **** +1062:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1063:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (32 bit) +1064:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 32 bit values. +1065:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data +1066:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) +1067:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1068:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) + 1278 .loc 4 1068 31 view .LVU313 + 1279 .LBB89: +1069:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1070:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 1280 .loc 4 1070 5 view .LVU314 +1071:Drivers/CMSIS/Include/cmsis_gcc.h **** +1072:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 1281 .loc 4 1072 4 view .LVU315 + 1282 0060 194A ldr r2, .L98 + 1283 .syntax unified + 1284 @ 1072 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1285 0062 52E8003F ldrex r3, [r2] + 1286 @ 0 "" 2 + 1287 .LVL31: +1073:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1288 .loc 4 1073 4 view .LVU316 + 1289 .loc 4 1073 4 is_stmt 0 view .LVU317 + 1290 .thumb + 1291 .syntax unified + 1292 .LBE89: + 1293 .LBE88: +3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1294 .loc 3 3215 3 discriminator 1 view .LVU318 + 1295 0066 23F04003 bic r3, r3, #64 + 1296 .LVL32: +3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1297 .loc 3 3215 3 is_stmt 1 discriminator 1 view .LVU319 + 1298 .LBB90: + ARM GAS /tmp/ccvzubVv.s page 185 + + + 1299 .LBI90: +1074:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1075:Drivers/CMSIS/Include/cmsis_gcc.h **** +1076:Drivers/CMSIS/Include/cmsis_gcc.h **** +1077:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1078:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (8 bit) +1079:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 8 bit values. +1080:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store +1081:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location +1082:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded +1083:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed +1084:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1085:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +1086:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1087:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; +1088:Drivers/CMSIS/Include/cmsis_gcc.h **** +1089:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); +1090:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); +1091:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1092:Drivers/CMSIS/Include/cmsis_gcc.h **** +1093:Drivers/CMSIS/Include/cmsis_gcc.h **** +1094:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1095:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (16 bit) +1096:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 16 bit values. +1097:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store +1098:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location +1099:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded +1100:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed +1101:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1102:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +1103:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1104:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; +1105:Drivers/CMSIS/Include/cmsis_gcc.h **** +1106:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); +1107:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); +1108:Drivers/CMSIS/Include/cmsis_gcc.h **** } +1109:Drivers/CMSIS/Include/cmsis_gcc.h **** +1110:Drivers/CMSIS/Include/cmsis_gcc.h **** +1111:Drivers/CMSIS/Include/cmsis_gcc.h **** /** +1112:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (32 bit) +1113:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 32 bit values. +1114:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store +1115:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location +1116:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded +1117:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed +1118:Drivers/CMSIS/Include/cmsis_gcc.h **** */ +1119:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) + 1300 .loc 4 1119 31 view .LVU320 + 1301 .LBB91: +1120:Drivers/CMSIS/Include/cmsis_gcc.h **** { +1121:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 1302 .loc 4 1121 4 view .LVU321 +1122:Drivers/CMSIS/Include/cmsis_gcc.h **** +1123:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 1303 .loc 4 1123 4 view .LVU322 + 1304 .syntax unified + 1305 @ 1123 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + ARM GAS /tmp/ccvzubVv.s page 186 + + + 1306 006a 42E80031 strex r1, r3, [r2] + 1307 @ 0 "" 2 + 1308 .LVL33: +1124:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 1309 .loc 4 1124 4 view .LVU323 + 1310 .loc 4 1124 4 is_stmt 0 view .LVU324 + 1311 .thumb + 1312 .syntax unified + 1313 .LBE91: + 1314 .LBE90: +3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1315 .loc 3 3215 3 discriminator 1 view .LVU325 + 1316 006e 0029 cmp r1, #0 + 1317 0070 F6D1 bne .L93 + 1318 0072 08E0 b .L82 + 1319 .LVL34: + 1320 .L85: +3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 1321 .loc 3 3215 3 discriminator 1 view .LVU326 + 1322 .LBE87: + 1323 .LBE86: + 289:Src/stm32f7xx_it.c **** } + 1324 .loc 1 289 7 is_stmt 1 view .LVU327 + 1325 .LBB92: + 1326 .LBI92: +3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 1327 .loc 3 3658 25 view .LVU328 + 1328 .LBB93: + 1329 .loc 3 3660 3 view .LVU329 + 1330 .loc 3 3660 20 is_stmt 0 view .LVU330 + 1331 0074 144B ldr r3, .L98 + 1332 0076 5B6A ldr r3, [r3, #36] + 1333 .LVL35: + 1334 .loc 3 3660 20 view .LVU331 + 1335 .LBE93: + 1336 .LBE92: + 289:Src/stm32f7xx_it.c **** } + 1337 .loc 1 289 11 discriminator 1 view .LVU332 + 1338 0078 9DF80720 ldrb r2, [sp, #7] @ zero_extendqisi2 + 1339 007c 52FA83F3 uxtab r3, r2, r3 + 1340 0080 DBB2 uxtb r3, r3 + 1341 0082 8DF80730 strb r3, [sp, #7] + 1342 .L82: + 323:Src/stm32f7xx_it.c **** + 1343 .loc 1 323 1 view .LVU333 + 1344 0086 03B0 add sp, sp, #12 + 1345 .LCFI11: + 1346 .cfi_remember_state + 1347 .cfi_def_cfa_offset 4 + 1348 @ sp needed + 1349 0088 5DF804FB ldr pc, [sp], #4 + 1350 .LVL36: + 1351 .L86: + 1352 .LCFI12: + 1353 .cfi_restore_state + 294:Src/stm32f7xx_it.c **** } + 1354 .loc 1 294 7 is_stmt 1 view .LVU334 + ARM GAS /tmp/ccvzubVv.s page 187 + + + 1355 .LBB94: + 1356 .LBI94: +3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 1357 .loc 3 3658 25 view .LVU335 + 1358 .LBB95: + 1359 .loc 3 3660 3 view .LVU336 + 1360 .loc 3 3660 20 is_stmt 0 view .LVU337 + 1361 008c 0E4B ldr r3, .L98 + 1362 008e 5B6A ldr r3, [r3, #36] + 1363 .LVL37: + 1364 .loc 3 3660 20 view .LVU338 + 1365 .LBE95: + 1366 .LBE94: + 294:Src/stm32f7xx_it.c **** } + 1367 .loc 1 294 11 discriminator 1 view .LVU339 + 1368 0090 9DF80720 ldrb r2, [sp, #7] @ zero_extendqisi2 + 1369 0094 52FA83F3 uxtab r3, r2, r3 + 1370 0098 DBB2 uxtb r3, r3 + 1371 009a 8DF80730 strb r3, [sp, #7] + 1372 009e F2E7 b .L82 + 1373 .LVL38: + 1374 .L88: + 299:Src/stm32f7xx_it.c **** } + 1375 .loc 1 299 7 is_stmt 1 view .LVU340 + 1376 .LBB96: + 1377 .LBI96: +3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 1378 .loc 3 3658 25 view .LVU341 + 1379 .LBB97: + 1380 .loc 3 3660 3 view .LVU342 + 1381 .loc 3 3660 20 is_stmt 0 view .LVU343 + 1382 00a0 094B ldr r3, .L98 + 1383 00a2 5B6A ldr r3, [r3, #36] + 1384 .LVL39: + 1385 .loc 3 3660 20 view .LVU344 + 1386 .LBE97: + 1387 .LBE96: + 299:Src/stm32f7xx_it.c **** } + 1388 .loc 1 299 11 discriminator 1 view .LVU345 + 1389 00a4 9DF80720 ldrb r2, [sp, #7] @ zero_extendqisi2 + 1390 00a8 52FA83F3 uxtab r3, r2, r3 + 1391 00ac DBB2 uxtb r3, r3 + 1392 00ae 8DF80730 strb r3, [sp, #7] + 1393 00b2 E8E7 b .L82 + 1394 .LVL40: + 1395 .L90: + 304:Src/stm32f7xx_it.c **** } + 1396 .loc 1 304 7 is_stmt 1 view .LVU346 + 1397 .LBB98: + 1398 .LBI98: +3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 1399 .loc 3 3658 25 view .LVU347 + 1400 .LBB99: + 1401 .loc 3 3660 3 view .LVU348 + 1402 .loc 3 3660 20 is_stmt 0 view .LVU349 + 1403 00b4 044B ldr r3, .L98 + 1404 00b6 5B6A ldr r3, [r3, #36] + ARM GAS /tmp/ccvzubVv.s page 188 + + + 1405 .LVL41: + 1406 .loc 3 3660 20 view .LVU350 + 1407 .LBE99: + 1408 .LBE98: + 304:Src/stm32f7xx_it.c **** } + 1409 .loc 1 304 11 discriminator 1 view .LVU351 + 1410 00b8 9DF80720 ldrb r2, [sp, #7] @ zero_extendqisi2 + 1411 00bc 52FA83F3 uxtab r3, r2, r3 + 1412 00c0 DBB2 uxtb r3, r3 + 1413 00c2 8DF80730 strb r3, [sp, #7] + 1414 00c6 DEE7 b .L82 + 1415 .L99: + 1416 .align 2 + 1417 .L98: + 1418 00c8 00100140 .word 1073811456 + 1419 00cc 00140140 .word 1073812480 + 1420 .cfi_endproc + 1421 .LFE1196: + 1423 .section .text.DMA2_Stream7_TransferComplete,"ax",%progbits + 1424 .align 1 + 1425 .global DMA2_Stream7_TransferComplete + 1426 .syntax unified + 1427 .thumb + 1428 .thumb_func + 1430 DMA2_Stream7_TransferComplete: + 1431 .LFB1203: + 545:Src/stm32f7xx_it.c **** + 546:Src/stm32f7xx_it.c **** //----------------------------------------------- + 547:Src/stm32f7xx_it.c **** void DMA2_Stream7_TransferComplete(void) + 548:Src/stm32f7xx_it.c **** { + 1432 .loc 1 548 1 is_stmt 1 view -0 + 1433 .cfi_startproc + 1434 @ args = 0, pretend = 0, frame = 0 + 1435 @ frame_needed = 0, uses_anonymous_args = 0 + 1436 @ link register save eliminated. + 549:Src/stm32f7xx_it.c **** LL_DMA_ClearFlag_TC7(DMA2); + 1437 .loc 1 549 3 view .LVU353 + 1438 .LVL42: + 1439 .LBB100: + 1440 .LBI100: + 1441 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @file stm32f7xx_ll_dma.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Header file of DMA LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * This software is licensed under terms that can be found in the LICENSE file in + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** + ARM GAS /tmp/ccvzubVv.s page 189 + + + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifndef __STM32F7xx_LL_DMA_H + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __STM32F7xx_LL_DMA_H + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifdef __cplusplus + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** extern "C" { + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Includes ------------------------------------------------------------------*/ + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #include "stm32f7xx.h" + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @addtogroup STM32F7xx_LL_Driver + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined (DMA1) || defined (DMA2) + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL DMA + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private types -------------------------------------------------------------*/ + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private variables ---------------------------------------------------------*/ + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Variables DMA Private Variables + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** static const uint8_t STREAM_OFFSET_TAB[] = + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }; + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private constants ---------------------------------------------------------*/ + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Constants DMA Private Constants + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_SxCR_CHSEL_3) + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define DMA_CHANNEL_SELECTION_8_15 + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_SxCR_CHSEL_3 */ + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + ARM GAS /tmp/ccvzubVv.s page 190 + + + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private macros ------------------------------------------------------------*/ + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported types ------------------------------------------------------------*/ + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(USE_FULL_LL_DRIVER) + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** typedef struct + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or as Source base address in case of memory to memory trans + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or as Destination base address in case of memory to memory + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Direction; /*!< Specifies if the data will be transferred from memory to pe + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** from memory to memory or from peripheral to memory. + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_DIRECTION + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Mode; /*!< Specifies the normal or circular operation mode. + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MODE + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The circular buffer mode cannot be used if the memory + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** data transfer direction is configured on the selected + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** is incremented or not. + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PERIPH + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** is incremented or not. + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MEMORY + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** in case of memory to memory transfer direction. + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination dat + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** in case of memory to memory transfer direction. + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** The data unit is equal to the source buffer configuration s + ARM GAS /tmp/ccvzubVv.s page 191 + + + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or MemorySize parameters depending in the transfer directio + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Channel; /*!< Specifies the peripheral channel. + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_CHANNEL + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Priority; /*!< Specifies the channel priority level. + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PRIORITY + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_FIFOMODE + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The Direct mode (FIFO mode disabled) cannot be used i + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** memory-to-memory data transfer is configured on the selecte + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHO + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory t + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** It specifies the amount of data to be transferred in a sing + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** transaction. + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MBURST + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The burst mode is possible only if the address Increm + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripher + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** It specifies the amount of data to be transferred in a sing + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** transaction. + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PBURST + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The burst mode is possible only if the address Increm + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } LL_DMA_InitTypeDef; + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /*USE_FULL_LL_DRIVER*/ + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported constants --------------------------------------------------------*/ + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_STREAM STREAM + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_0 0x00000000U + ARM GAS /tmp/ccvzubVv.s page 192 + + + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_1 0x00000001U + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_2 0x00000002U + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_3 0x00000003U + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_4 0x00000004U + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_5 0x00000005U + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_6 0x00000006U + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_7 0x00000007U + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_ALL 0xFFFF0000U + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DIRECTION DIRECTION + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direc + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direc + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MODE MODE + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mo + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering m + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mo + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PERIPH PERIPH + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MEMORY MEMORY + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disa + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enab + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + ARM GAS /tmp/ccvzubVv.s page 193 + + + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : By + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : Ha + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Wo + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offse + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offse + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PRIORITY PRIORITY + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CHANNEL CHANNEL + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_0 0x00000000U + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_CHANNEL_SELECTION_8_15) + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) + ARM GAS /tmp/ccvzubVv.s page 194 + + + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_15 DMA_SxCR_CHSEL + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_CHANNEL_SELECTION_8_15 */ + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MBURST MBURST + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PBURST PBURST + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral b + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral b + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral b + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral b + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode di + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode en + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_lev + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_l + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_l + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_l + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empt + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + ARM GAS /tmp/ccvzubVv.s page 195 + + + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO thresho + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO thresho + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO thresho + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO thresho + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentT + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentT + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported macro ------------------------------------------------------------*/ + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Write a value in DMA register + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __INSTANCE__ DMA Instance + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __REG__ Register to be written + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __VALUE__ Value to be written in the register + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Read a value in DMA register + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __INSTANCE__ DMA Instance + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __REG__ Register to be read + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Register value + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMAx_Streamy into DMAx + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM_INSTANCE__ DMAx_Streamy + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval DMAx + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + ARM GAS /tmp/ccvzubVv.s page 196 + + + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM_INSTANCE__ DMAx_Streamy + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval LL_DMA_CHANNEL_y + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** LL_DMA_STREAM_7) + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __DMA_INSTANCE__ DMAx + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM__ LL_DMA_STREAM_y + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval DMAx_Streamy + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** DMA2_Stream7) + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + ARM GAS /tmp/ccvzubVv.s page 197 + + + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported functions --------------------------------------------------------*/ + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_Configuration Configuration + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable DMA stream. + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_EnableStream + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable DMA stream. + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_DisableStream + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Check if DMA stream is enabled or disabled. + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_IsEnabledStream + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + ARM GAS /tmp/ccvzubVv.s page 198 + + + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure all parameters linked to DMA transfer. + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_ConfigTransfer\n + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR CIRC LL_DMA_ConfigTransfer\n + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PINC LL_DMA_ConfigTransfer\n + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR MINC LL_DMA_ConfigTransfer\n + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PSIZE LL_DMA_ConfigTransfer\n + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR MSIZE LL_DMA_ConfigTransfer\n + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PL LL_DMA_ConfigTransfer\n + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_ConfigTransfer + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Configuration This parameter must be a combination of all the following values: + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH o + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDAT + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDAT + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HI + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** *@retval None + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configurati + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_Sx + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** Configuration); + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Data transfer direction (read from peripheral or from memory). + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_SetDataTransferDirection + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + ARM GAS /tmp/ccvzubVv.s page 199 + + + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Direction This parameter can be one of the following values: + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Data transfer direction (read from peripheral or from memory). + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_GetDataTransferDirection + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set DMA mode normal, circular or peripheral flow control. + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CIRC LL_DMA_SetMode\n + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_SetMode + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Mode This parameter can be one of the following values: + 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL + 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_CIRCULAR + 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_PFCTRL + ARM GAS /tmp/ccvzubVv.s page 200 + + + 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) + 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get DMA mode normal, circular or peripheral flow control. + 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CIRC LL_DMA_GetMode\n + 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_GetMode + 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL + 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_CIRCULAR + 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_PFCTRL + 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) + 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral increment mode. + 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINC LL_DMA_SetPeriphIncMode + 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param IncrementMode This parameter can be one of the following values: + 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_NOINCREMENT + 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT + 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment + 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral increment mode. + 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINC LL_DMA_GetPeriphIncMode + ARM GAS /tmp/ccvzubVv.s page 201 + + + 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_NOINCREMENT + 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT + 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) + 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory increment mode. + 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MINC LL_DMA_SetMemoryIncMode + 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param IncrementMode This parameter can be one of the following values: + 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_NOINCREMENT + 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT + 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment + 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory increment mode. + 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MINC LL_DMA_GetMemoryIncMode + 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_NOINCREMENT + ARM GAS /tmp/ccvzubVv.s page 202 + + + 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT + 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) + 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral size. + 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PSIZE LL_DMA_SetPeriphSize + 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Size This parameter can be one of the following values: + 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE + 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_WORD + 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) + 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral size. + 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PSIZE LL_DMA_GetPeriphSize + 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE + 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_WORD + 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) + 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory size. + 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MSIZE LL_DMA_SetMemorySize + ARM GAS /tmp/ccvzubVv.s page 203 + + + 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Size This parameter can be one of the following values: + 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE + 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_WORD + 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) + 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory size. + 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MSIZE LL_DMA_GetMemorySize + 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE + 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_WORD + 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) + 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral increment offset size. + 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize + 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + ARM GAS /tmp/ccvzubVv.s page 204 + + + 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param OffsetSize This parameter can be one of the following values: + 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSiz + 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral increment offset size. + 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize + 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) + 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Stream priority level. + 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Priority This parameter can be one of the following values: + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW + 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_MEDIUM + 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_HIGH + 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_VERYHIGH + 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pr + 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + ARM GAS /tmp/ccvzubVv.s page 205 + + + 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream priority level. + 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel + 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW + 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_MEDIUM + 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_HIGH + 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_VERYHIGH + 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) + 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Number of data to transfer. + 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll NDTR NDT LL_DMA_SetDataLength + 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This action has no effect if + 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * stream is enabled. + 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param NbData Between 0 to 0xFFFFFFFF + 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) + 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, + 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Number of data to transfer. + 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll NDTR NDT LL_DMA_GetDataLength + 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Once the stream is enabled, the return value indicate the + 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * remaining bytes to be transmitted. + 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + ARM GAS /tmp/ccvzubVv.s page 206 + + + 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF + 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) + 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Select Channel number associated to the Stream. +1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CHSEL LL_DMA_SetChannelSelection +1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: +1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_0 +1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 +1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 +1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 +1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 +1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 +1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 +1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 +1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_8 (*) +1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_9 (*) +1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_10 (*) +1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_11 (*) +1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_12 (*) +1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_13 (*) +1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_14 (*) +1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_15 (*) +1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * +1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * (*) value not defined in all devices. +1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channe +1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D +1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Channel number associated to the Stream. +1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CHSEL LL_DMA_GetChannelSelection +1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + ARM GAS /tmp/ccvzubVv.s page 207 + + +1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: +1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_0 +1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 +1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 +1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 +1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 +1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 +1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 +1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 +1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_8 (*) +1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_9 (*) +1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_10 (*) +1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_11 (*) +1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_12 (*) +1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_13 (*) +1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_14 (*) +1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_15 (*) +1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * +1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * (*) value not defined in all devices. +1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream) +1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory burst transfer configuration. +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer +1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Mburst This parameter can be one of the following values: +1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_SINGLE +1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC4 +1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC8 +1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC16 +1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) +1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D +1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + ARM GAS /tmp/ccvzubVv.s page 208 + + +1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory burst transfer configuration. +1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer +1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: +1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_SINGLE +1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC4 +1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC8 +1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC16 +1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral burst transfer configuration. +1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer +1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Pburst This parameter can be one of the following values: +1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_SINGLE +1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC4 +1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC8 +1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC16 +1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) +1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D +1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral burst transfer configuration. +1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer +1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + ARM GAS /tmp/ccvzubVv.s page 209 + + +1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: +1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_SINGLE +1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC4 +1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC8 +1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC16 +1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. +1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CT LL_DMA_SetCurrentTargetMem +1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param CurrentMemory This parameter can be one of the following values: +1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM0 +1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM1 +1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Curren +1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, +1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. +1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CT LL_DMA_GetCurrentTargetMem +1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: +1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM0 +1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM1 +1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) + ARM GAS /tmp/ccvzubVv.s page 210 + + +1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable the double buffer mode. +1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode +1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA +1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable the double buffer mode. +1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode +1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D +1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get FIFO status. +1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FS LL_DMA_GetFIFOStatus +1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + ARM GAS /tmp/ccvzubVv.s page 211 + + +1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: +1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_0_25 +1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_25_50 +1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_50_75 +1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_75_100 +1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_EMPTY +1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_FULL +1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) +1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable Fifo mode. +1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode +1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, +1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Fifo mode. +1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode +1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DM +1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Select FIFO threshold. +1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold +1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + ARM GAS /tmp/ccvzubVv.s page 212 + + +1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Threshold This parameter can be one of the following values: +1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 +1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 +1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 +1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL +1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold +1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, +1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get FIFO threshold. +1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold +1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: +1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 +1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 +1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 +1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure the FIFO . +1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_ConfigFifo\n +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * FCR DMDIS LL_DMA_ConfigFifo +1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + ARM GAS /tmp/ccvzubVv.s page 213 + + +1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param FifoMode This parameter can be one of the following values: +1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOMODE_ENABLE +1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOMODE_DISABLE +1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param FifoThreshold This parameter can be one of the following values: +1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 +1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 +1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 +1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL +1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint3 +1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, +1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure the Source and Destination addresses. +1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA stream is enabled. +1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n +1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * PAR PA LL_DMA_ConfigAddresses +1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param SrcAddress Between 0 to 0xFFFFFFFF +1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DstAddress Between 0 to 0xFFFFFFFF +1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Direction This parameter can be one of the following values: +1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY +1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH +1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY +1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress +1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Direction Memory to Periph */ +1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) +1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR +1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, +1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Direction Periph to Memory and Memory to Memory */ +1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** else +1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, +1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR +1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + ARM GAS /tmp/ccvzubVv.s page 214 + + +1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Memory address. +1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress +1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO +1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. +1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param MemoryAddress Between 0 to 0xFFFFFFFF +1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd +1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, +1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Peripheral address. +1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_SetPeriphAddress +1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO +1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. +1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param PeriphAddress Between 0 to 0xFFFFFFFF +1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAdd +1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, P +1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Memory address. +1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress +1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO +1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + ARM GAS /tmp/ccvzubVv.s page 215 + + +1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF +1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream) +1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Peripheral address. +1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_GetPeriphAddress +1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO +1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF +1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream) +1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream]))) +1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Memory to Memory Source address. +1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress +1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. +1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. +1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param MemoryAddress Between 0 to 0xFFFFFFFF +1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd +1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, M +1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Memory to Memory Destination address. +1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress +1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + ARM GAS /tmp/ccvzubVv.s page 216 + + +1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. +1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param MemoryAddress Between 0 to 0xFFFFFFFF +1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd +1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR +1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Memory to Memory Source address. +1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress +1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. +1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF +1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream) +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])) +1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Memory to Memory Destination address. +1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress +1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. +1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF +1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream) + ARM GAS /tmp/ccvzubVv.s page 217 + + +1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))-> +1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory 1 address (used in case of Double buffer mode). +1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M1AR M1A LL_DMA_SetMemory1Address +1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Address Between 0 to 0xFFFFFFFF +1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) +1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, +1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory 1 address (used in case of Double buffer mode). +1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M1AR M1A LL_DMA_GetMemory1Address +1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF +1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) +1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR); +1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} +1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management +1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ +1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 half transfer flag. +1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 +1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + ARM GAS /tmp/ccvzubVv.s page 218 + + +1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) +1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0)); +1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 half transfer flag. +1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 +1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1)); +1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 half transfer flag. +1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 +1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2)); +1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 half transfer flag. +1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 +1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3)); +1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 half transfer flag. +1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 +1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); +1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 half transfer flag. +1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 +1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + ARM GAS /tmp/ccvzubVv.s page 219 + + +1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); +1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 half transfer flag. +1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 +1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); +1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 half transfer flag. +1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 +1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); +1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 transfer complete flag. +1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 +1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) +1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0)); +1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 transfer complete flag. +1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1)); +1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 transfer complete flag. +1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 +1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + ARM GAS /tmp/ccvzubVv.s page 220 + + +1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2)); +1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 transfer complete flag. +1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 +1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3)); +1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 transfer complete flag. +1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 +1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); +1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 transfer complete flag. +1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 +1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); +1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 transfer complete flag. +1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 +1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); +1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 transfer complete flag. +1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 +1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); +1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + ARM GAS /tmp/ccvzubVv.s page 221 + + +1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 transfer error flag. +1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 +1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) +1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0)); +1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 transfer error flag. +1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 +1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1)); +1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 transfer error flag. +1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 +1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2)); +1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 transfer error flag. +1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 +1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3)); +1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 transfer error flag. +1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 +1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); +1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + ARM GAS /tmp/ccvzubVv.s page 222 + + +1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 transfer error flag. +1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 +1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); +1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 transfer error flag. +1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 +1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6)); +1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 transfer error flag. +1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 +1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7)); +1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 direct mode error flag. +1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 +1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) +1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0)); +1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 direct mode error flag. +1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 +1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) +1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1)); +1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 direct mode error flag. +1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 + ARM GAS /tmp/ccvzubVv.s page 223 + + +1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) +1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2)); +1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 direct mode error flag. +1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 +1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) +1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3)); +1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 direct mode error flag. +1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 +1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) +1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4)); +1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 direct mode error flag. +1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 +1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) +1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5)); +1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 direct mode error flag. +1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 +1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) +2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6)); +2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 direct mode error flag. +2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 +2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). + ARM GAS /tmp/ccvzubVv.s page 224 + + +2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) +2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7)); +2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 0 FIFO error flag. +2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 +2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) +2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0)); +2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 1 FIFO error flag. +2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) +2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1)); +2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 2 FIFO error flag. +2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 +2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) +2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2)); +2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 3 FIFO error flag. +2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 +2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) +2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3)); +2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 4 FIFO error flag. +2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 +2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) + ARM GAS /tmp/ccvzubVv.s page 225 + + +2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4)); +2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 5 FIFO error flag. +2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 +2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) +2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5)); +2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 6 FIFO error flag. +2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 +2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) +2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6)); +2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream 7 FIFO error flag. +2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 +2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). +2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) +2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7)); +2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 half transfer flag. +2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 +2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) +2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); +2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 half transfer flag. +2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 +2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1); + ARM GAS /tmp/ccvzubVv.s page 226 + + +2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 half transfer flag. +2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 +2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2); +2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 half transfer flag. +2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 +2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3); +2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 half transfer flag. +2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 +2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4); +2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 half transfer flag. +2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 +2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5); +2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 half transfer flag. +2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 +2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6); +2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + ARM GAS /tmp/ccvzubVv.s page 227 + + +2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 half transfer flag. +2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 +2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7); +2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 transfer complete flag. +2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 +2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) +2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0); +2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 transfer complete flag. +2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 +2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1); +2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 transfer complete flag. +2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 +2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2); +2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 transfer complete flag. +2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 +2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3); +2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 transfer complete flag. + ARM GAS /tmp/ccvzubVv.s page 228 + + +2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 +2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4); +2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 transfer complete flag. +2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 +2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5); +2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 transfer complete flag. +2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 +2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6); +2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 transfer complete flag. +2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 +2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) + 1442 .loc 5 2277 22 view .LVU354 + 1443 .LBB101: +2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7); + 1444 .loc 5 2279 3 view .LVU355 + 1445 0000 024B ldr r3, .L101 + 1446 0002 4FF00062 mov r2, #134217728 + 1447 0006 DA60 str r2, [r3, #12] + 1448 .LVL43: + 1449 .loc 5 2279 3 is_stmt 0 view .LVU356 + 1450 .LBE101: + 1451 .LBE100: + 550:Src/stm32f7xx_it.c **** } + 1452 .loc 1 550 1 view .LVU357 + 1453 0008 7047 bx lr + 1454 .L102: + 1455 000a 00BF .align 2 + 1456 .L101: + 1457 000c 00640240 .word 1073898496 + ARM GAS /tmp/ccvzubVv.s page 229 + + + 1458 .cfi_endproc + 1459 .LFE1203: + 1461 .section .text.DMA2_Stream7_IRQHandler,"ax",%progbits + 1462 .align 1 + 1463 .global DMA2_Stream7_IRQHandler + 1464 .syntax unified + 1465 .thumb + 1466 .thumb_func + 1468 DMA2_Stream7_IRQHandler: + 1469 .LFB1201: + 417:Src/stm32f7xx_it.c **** /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */ + 1470 .loc 1 417 1 is_stmt 1 view -0 + 1471 .cfi_startproc + 1472 @ args = 0, pretend = 0, frame = 0 + 1473 @ frame_needed = 0, uses_anonymous_args = 0 + 1474 0000 08B5 push {r3, lr} + 1475 .LCFI13: + 1476 .cfi_def_cfa_offset 8 + 1477 .cfi_offset 3, -8 + 1478 .cfi_offset 14, -4 + 419:Src/stm32f7xx_it.c **** { + 1479 .loc 1 419 3 view .LVU359 + 1480 .LVL44: + 1481 .LBB102: + 1482 .LBI102: +1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 1483 .loc 5 1837 26 view .LVU360 + 1484 .LBB103: +1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 1485 .loc 5 1839 3 view .LVU361 +1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 1486 .loc 5 1839 11 is_stmt 0 view .LVU362 + 1487 0002 0A4B ldr r3, .L108 + 1488 0004 5B68 ldr r3, [r3, #4] + 1489 .LVL45: +1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 1490 .loc 5 1839 11 view .LVU363 + 1491 .LBE103: + 1492 .LBE102: + 419:Src/stm32f7xx_it.c **** { + 1493 .loc 1 419 5 discriminator 1 view .LVU364 + 1494 0006 13F0006F tst r3, #134217728 + 1495 000a 09D1 bne .L107 + 424:Src/stm32f7xx_it.c **** { + 1496 .loc 1 424 8 is_stmt 1 view .LVU365 + 1497 .LVL46: + 1498 .LBB104: + 1499 .LBI104: +1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 1500 .loc 5 1925 26 view .LVU366 + 1501 .LBB105: +1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 1502 .loc 5 1927 3 view .LVU367 +1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 1503 .loc 5 1927 11 is_stmt 0 view .LVU368 + 1504 000c 074B ldr r3, .L108 + 1505 000e 5B68 ldr r3, [r3, #4] + ARM GAS /tmp/ccvzubVv.s page 230 + + + 1506 .LVL47: +1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 1507 .loc 5 1927 11 view .LVU369 + 1508 .LBE105: + 1509 .LBE104: + 424:Src/stm32f7xx_it.c **** { + 1510 .loc 1 424 10 discriminator 1 view .LVU370 + 1511 0010 13F0007F tst r3, #33554432 + 1512 0014 03D0 beq .L103 + 426:Src/stm32f7xx_it.c **** } + 1513 .loc 1 426 5 is_stmt 1 view .LVU371 + 1514 .LVL48: + 1515 .LBB106: + 1516 .LBI106: +2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 0 transfer error flag. +2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 +2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) +2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0); +2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 1 transfer error flag. +2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 +2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1); +2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 2 transfer error flag. +2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 +2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2); +2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 3 transfer error flag. +2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 +2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + ARM GAS /tmp/ccvzubVv.s page 231 + + +2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3); +2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 4 transfer error flag. +2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 +2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4); +2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 5 transfer error flag. +2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 +2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5); +2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 6 transfer error flag. +2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 +2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6); +2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Clear Stream 7 transfer error flag. +2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 +2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) + 1517 .loc 5 2365 22 view .LVU372 + 1518 .LBB107: +2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7); + 1519 .loc 5 2367 3 view .LVU373 + 1520 0016 054B ldr r3, .L108 + 1521 0018 4FF00072 mov r2, #33554432 + 1522 001c DA60 str r2, [r3, #12] + 1523 .LVL49: + 1524 .L103: + 1525 .loc 5 2367 3 is_stmt 0 view .LVU374 + 1526 .LBE107: + 1527 .LBE106: + 432:Src/stm32f7xx_it.c **** + ARM GAS /tmp/ccvzubVv.s page 232 + + + 1528 .loc 1 432 1 view .LVU375 + 1529 001e 08BD pop {r3, pc} + 1530 .L107: + 421:Src/stm32f7xx_it.c **** u_tx_flg = 0;//indicate that transfer compete + 1531 .loc 1 421 5 is_stmt 1 view .LVU376 + 1532 0020 FFF7FEFF bl DMA2_Stream7_TransferComplete + 1533 .LVL50: + 422:Src/stm32f7xx_it.c **** } + 1534 .loc 1 422 5 view .LVU377 + 422:Src/stm32f7xx_it.c **** } + 1535 .loc 1 422 14 is_stmt 0 view .LVU378 + 1536 0024 024B ldr r3, .L108+4 + 1537 0026 0022 movs r2, #0 + 1538 0028 1A70 strb r2, [r3] + 1539 002a F8E7 b .L103 + 1540 .L109: + 1541 .align 2 + 1542 .L108: + 1543 002c 00640240 .word 1073898496 + 1544 0030 00000000 .word u_tx_flg + 1545 .cfi_endproc + 1546 .LFE1201: + 1548 .text + 1549 .Letext0: + 1550 .file 6 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 1551 .file 7 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 1552 .file 8 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + 1553 .file 9 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 1554 .file 10 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h" + 1555 .file 11 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h" + 1556 .file 12 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h" + 1557 .file 13 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h" + 1558 .file 14 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h" + 1559 .file 15 "Inc/main.h" + 1560 .file 16 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h" + ARM GAS /tmp/ccvzubVv.s page 233 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_it.c + /tmp/ccvzubVv.s:20 .text.NMI_Handler:00000000 $t + /tmp/ccvzubVv.s:26 .text.NMI_Handler:00000000 NMI_Handler + /tmp/ccvzubVv.s:43 .text.HardFault_Handler:00000000 $t + /tmp/ccvzubVv.s:49 .text.HardFault_Handler:00000000 HardFault_Handler + /tmp/ccvzubVv.s:66 .text.MemManage_Handler:00000000 $t + /tmp/ccvzubVv.s:72 .text.MemManage_Handler:00000000 MemManage_Handler + /tmp/ccvzubVv.s:89 .text.BusFault_Handler:00000000 $t + /tmp/ccvzubVv.s:95 .text.BusFault_Handler:00000000 BusFault_Handler + /tmp/ccvzubVv.s:112 .text.UsageFault_Handler:00000000 $t + /tmp/ccvzubVv.s:118 .text.UsageFault_Handler:00000000 UsageFault_Handler + /tmp/ccvzubVv.s:135 .text.SVC_Handler:00000000 $t + /tmp/ccvzubVv.s:141 .text.SVC_Handler:00000000 SVC_Handler + /tmp/ccvzubVv.s:154 .text.DebugMon_Handler:00000000 $t + /tmp/ccvzubVv.s:160 .text.DebugMon_Handler:00000000 DebugMon_Handler + /tmp/ccvzubVv.s:173 .text.PendSV_Handler:00000000 $t + /tmp/ccvzubVv.s:179 .text.PendSV_Handler:00000000 PendSV_Handler + /tmp/ccvzubVv.s:192 .text.SysTick_Handler:00000000 $t + /tmp/ccvzubVv.s:198 .text.SysTick_Handler:00000000 SysTick_Handler + /tmp/ccvzubVv.s:218 .text.ADC_IRQHandler:00000000 $t + /tmp/ccvzubVv.s:224 .text.ADC_IRQHandler:00000000 ADC_IRQHandler + /tmp/ccvzubVv.s:248 .text.ADC_IRQHandler:00000010 $d + /tmp/ccvzubVv.s:254 .text.TIM1_UP_TIM10_IRQHandler:00000000 $t + /tmp/ccvzubVv.s:260 .text.TIM1_UP_TIM10_IRQHandler:00000000 TIM1_UP_TIM10_IRQHandler + /tmp/ccvzubVv.s:301 .text.TIM1_UP_TIM10_IRQHandler:00000024 $d + /tmp/ccvzubVv.s:309 .text.TIM1_TRG_COM_TIM11_IRQHandler:00000000 $t + /tmp/ccvzubVv.s:315 .text.TIM1_TRG_COM_TIM11_IRQHandler:00000000 TIM1_TRG_COM_TIM11_IRQHandler + /tmp/ccvzubVv.s:355 .text.TIM1_TRG_COM_TIM11_IRQHandler:00000028 $d + /tmp/ccvzubVv.s:362 .text.TIM2_IRQHandler:00000000 $t + /tmp/ccvzubVv.s:368 .text.TIM2_IRQHandler:00000000 TIM2_IRQHandler + /tmp/ccvzubVv.s:381 .text.TIM8_UP_TIM13_IRQHandler:00000000 $t + /tmp/ccvzubVv.s:387 .text.TIM8_UP_TIM13_IRQHandler:00000000 TIM8_UP_TIM13_IRQHandler + /tmp/ccvzubVv.s:453 .text.TIM8_UP_TIM13_IRQHandler:00000048 $d + /tmp/ccvzubVv.s:459 .text.TIM5_IRQHandler:00000000 $t + /tmp/ccvzubVv.s:465 .text.TIM5_IRQHandler:00000000 TIM5_IRQHandler + /tmp/ccvzubVv.s:478 .text.TIM6_DAC_IRQHandler:00000000 $t + /tmp/ccvzubVv.s:484 .text.TIM6_DAC_IRQHandler:00000000 TIM6_DAC_IRQHandler + /tmp/ccvzubVv.s:543 .text.TIM6_DAC_IRQHandler:00000028 $d + /tmp/ccvzubVv.s:550 .text.TIM7_IRQHandler:00000000 $t + /tmp/ccvzubVv.s:556 .text.TIM7_IRQHandler:00000000 TIM7_IRQHandler + /tmp/ccvzubVv.s:605 .text.TIM7_IRQHandler:0000001c $d + /tmp/ccvzubVv.s:611 .text.UART_RxCpltCallback:00000000 $t + /tmp/ccvzubVv.s:617 .text.UART_RxCpltCallback:00000000 UART_RxCpltCallback + /tmp/ccvzubVv.s:655 .text.UART_RxCpltCallback:0000001a $d + /tmp/ccvzubVv.s:687 .text.UART_RxCpltCallback:0000005a $t + /tmp/ccvzubVv.s:1084 .text.UART_RxCpltCallback:00000260 $d + /tmp/ccvzubVv.s:1099 .text.USART1_IRQHandler:00000000 $t + /tmp/ccvzubVv.s:1105 .text.USART1_IRQHandler:00000000 USART1_IRQHandler + /tmp/ccvzubVv.s:1418 .text.USART1_IRQHandler:000000c8 $d + /tmp/ccvzubVv.s:1424 .text.DMA2_Stream7_TransferComplete:00000000 $t + /tmp/ccvzubVv.s:1430 .text.DMA2_Stream7_TransferComplete:00000000 DMA2_Stream7_TransferComplete + /tmp/ccvzubVv.s:1457 .text.DMA2_Stream7_TransferComplete:0000000c $d + /tmp/ccvzubVv.s:1462 .text.DMA2_Stream7_IRQHandler:00000000 $t + /tmp/ccvzubVv.s:1468 .text.DMA2_Stream7_IRQHandler:00000000 DMA2_Stream7_IRQHandler + /tmp/ccvzubVv.s:1543 .text.DMA2_Stream7_IRQHandler:0000002c $d + + ARM GAS /tmp/ccvzubVv.s page 234 + + +UNDEFINED SYMBOLS +HAL_IncTick +HAL_ADC_IRQHandler +hadc1 +hadc3 +HAL_TIM_IRQHandler +TO10 +TO10_counter +htim10 +TIM10_coflag +htim11 +Set_LTEC +HAL_GPIO_WritePin +LD_blinker +htim8 +HAL_GPIO_TogglePin +TO6 +TO7 +uart_buf +UART_rec_incr +TO6_uart +flg_tmt +UART_header +CPU_state +State_Data +COMMAND +UART_transmission_request +u_tx_flg diff --git a/build/stm32f7xx_it.o b/build/stm32f7xx_it.o new file mode 100644 index 0000000000000000000000000000000000000000..ebac6fada671b34b001ab5be9a2c8fddc3858139 GIT binary patch literal 28160 zcmchA2YejWx$l{oUF}L+RNZ99tSlFSrB$)9jj=)1mMqB`3Dj6g#(t2LCUHR@pXAN!oYvCaJRKKS=f{^Rf7 zN4*bPjXX2;(fg=l)BB)zOa6edD!<#aC2!!0T5BppG~CU`lESf1_Nm7lT?f4nW;PcN z)b971h25T}EPa;M{p!Gy{f7B!x68@lG1X{PE3c|%y0Ohla{gXb zWQORGzeO#HUeGDl2QyI;p@Srg2 zmJ*poNxtOReki|LogpbaQ!YtiNeWmju=R2txTg8&<9~VI)y;)tS2r)b;DD9t1K(M{ zdpm!BNR_KhCsWZ1WjSz6-2( z&EgyG^PO4$L4EBNwQHxcU#b0I$&xE-LsNAhtg5=AcG*2uYc`h@p85NI zn?C68xuSOE)aDOPieFJ%G1c(FwhrK4RlF0H2e;&p9pCImZ9czG759P@1E-&9$9@9N zao}`=6K%G@c?6uJ!TBmU$2Pmb`93(?z&Q$>?adkB+_~=vo%3ywv_WzNB%NFGch~JV zt^BbzZTaebElu7F;A!p!wRuylp@XJ&c#T80w5HrNBT|83RX|w zN3GncW4y+p)r}RO=I0pD3VoU%I#jnsRlFLyYmnE#KI*J(DuQhPK3ZMf7=pE5?<+^1 zh{B1fd6uQ+xde6&)Opq=h|C{_f|B&hE^WR_DqGF7Y^{uoMMkz^~OP3;>}*RcZEJP zvrG3b(`T;i%DqeUnUTF_Z;?K$&MurUnP;*iarjhY3M5gKf7;2`={ryaU*L`<}Qr7!!r82_vkD-|c9NavZ zhW9xigwqU7k{?nqE(h1&PZ&I5I)zEs%MR#Nj^d z-Wy0MH<_93o~JV3g(F#=9m?}`?pffO#VV_=qf&XE5z+;+N_n0Y(u)xh2A&hr?|X~n z^FrqM?to{W7lbVE-A(f6LeBTyPx2Q+F7o{=$tfX2S&dzAW3P})vsy_0QpgftDINcn zkfpv#k}nEb;afxUB_UV)y6M%+Lay_zN0>do7IK4cDhuQ*LRR~Zp!7FF*87em`KpkO zS@rPZHKAIRbu+5U^Sbo|_>A7E#A+#z!U4Vyv#*r5x8B@Dw84n02@CjAqKUKFfhv7dD4P@ryW zm-777p_c~QJL{C^DTgiz)O5i9&m6im(80QY+Mz3gS+xI*L$3~IlYZ8r*98kmKj+XJ zf(uAL@6gr3_Yob>3l3c$sHgp(J9K045jOWY!9xcxxEhE6 zSWNm?4*gZs5~Ba2LwAF&LdSIIK9#K){$E?xIY{Vch51W8f3h+^OH|#T9c5M}67P3t z7wA>W^S(oS1GS9Z2M+BIp2xC&=+HSqKlA#?p$h^XM?n8C4n056#Jc|2p%(?37@JQV zIuz(&6aCbomj=2>f9B97D*MlDJD*$DVesC~BII}s4&dHfjOEBXcN17D_hU3vLs`F| z;5(KN0@Ld%M|TnJ%qpXc+E2oo%B{u$+K(eq=E2q>5QthTklEUosEZ8RS_WNo&( zA;_%oRb)0`2=E<-e($UD>sg^#`36ZIETqf#AUc-s5Fx$3e?fk}4MO^TJ7C>+xR5!% z-=lf>YK1KD-9oZK$oalMVLb9}5pt35L1x}6WC*!}>=1IPZy9RGw@t_r--}c}M#xfS zeS*Qv*KK}%y1>4E<6J1^9*%@6_jxoJBexY+&Dx8WLSRmk02!f{A?B z=^(7V%Lb`lmB=I|S@AWN1QomF8e&3U5H-4wG zbA0P4JwnnJ__iZT{w^Ws`+f=M{72=p7nsG1e7A7oawtnJ2(d=KMf7^JuoK zBDBLmg}ASL>!1@@C8W!@31tne5z_0s5=jG24fuVBlXPkz$M-C<3N(sxfwIP#c#HKh zwC34EOQ6g!u0*c6*Pu))_hwXzk^46=%-kQLMy%W|2&PMAUyC3HRvA`5L@p+9(jQ_N zPc!{7Y%#en!FMCK0OzL4&S7pF4eNHMp^}rP&M>}Unr}f{<#MrWOi-#f&}V1$le=>8p|1cRCbWVU7*KU&g{_Gg2RYFpx0ROv8F@8X4nqI zjO9|_LH6%Jzp?ygoql6*gz}xn^0{a@sSiVxz^+AMK1qO}fnc7|>+5+b- z4_i|PRP=f&1G5~=(S)Ym%0-!G(vD_Y%C!*Z+4U^Yg@&~a2J>B{agVIGCN>H7eU3%4)6Tq$laXE zRr7Zuo!KQ^)0N@P^5+!HzZVA0sBjI_a=9VUF7TQ~{CB@b7ybgjgW6*P0 z>e-ow`*2`kSKAt8l;&|*H4IQ|LCv$Ng}b3`lr9qLQ21z+E*EMsD$OV@73xAJFUzB2 zhOzJ>%F2pt%0oB+jYh{Ts1};ES{BY`S2Y&?j!D9~bP-e@nc;;(T}sXHQk(J+b~<(p zweT99vivC9&UTZ!he^sK=|OmhP#0-guTZ8NvdW@8C_Qq#3^6jQ3*SL#L4~PV<51_b zx@rq6sA4QUmHE{<)Y+u!g<53nLi((CGYlh;jb_gZncD*mwaAFTm8^FlDNT{g<>Ce6 zZZw|kMu<02Oc(8hUomb$Z3h027ox9H!~<%O&V0pq3>o+*&3wbyO&Jf6u@H-mV{pvb zi)05F?O+?lW(I~)@UWYwE8`g`hmM|478pFRe;CV5t7s5h%^_DUF)m?j?>Fr97ei7= z%`8|7ojTW6HK?x*JZR(;T?%d&7#-MYAcis+d&B^5h7Msj?u3EjYb7sjfUz)cH8QqB zQuJL&E(POa?5g-AP$;u9cwiZfI}P71>RklMonYLKT@|kdh1`|F!(yKNv*G?H>TQDL z2{0bVu9hyv;X=mi0Aqmd>k{#fe1<0ncfg82oCk^w9#DbGxB@pTXe!){za3W}>5@i+P5T(FKXlr~-OnR$ehP zqS)l2fClv-h|W_uqJCzvG*yTrJk zF=!NaJJ>z2V-%w-B@84R?HkAj_KYgps!%0Mz-Kf6Q1d&;LJnFr1L?G?D%l`f3pA_4 zs8mZgfyHKykd&~$6-c&IV4clu=gm>-Ko??Z%rgp(0N4EHNyS@H7ntI3^9BbLO&Rlz zjFVusC<@8bNcR+rUi=gItHnGZDAX&xiFz+X@(1X=q4h?QO1BRlN~pKk@cxW?XG8J@ zbUxR5-v>pp$wL+OijBaZsrMu#a}mMLQQ4@cX2;mfG^ zAS7Rd&S_dN2dOAFdFZCz8YA-u)H?u@YoT+s*86v)qS)kN0=sdDkvWXER`ekx_d(}g z><1|%ax_*NAf5;JS?tB1Bj}WPc<9G&UFNsSXdn}}1b+{e-(g=l7sOw2@)>p&`d1`6 z9w!D5Ba*1-H{j-2s88%g&x1G!C%o6N@+}aD<76XtY{eXh=&Z@ZZtO;p5xk0->ahq~ z9n{o%7gNl`%whk8pF;lL3WJ@5?nK##O}7M?w@)VKgMfboev#;ykU5u`IZVMz~Fy1$efC$dw# zIj!_6m3C7J@vu8psqsr@@UpE$_UBZ(ol0I%J@8^F`vy-`sqt?akp9@#ro0gS%Xp63 z5U8(Fsm$2Nd>^ot9GA?YJJPv-q=DJFUtW0oiZNQf#6Q=t*u8AwCH_MObELuT!5Abavcez=N;aP z$6>_%rWYz)71%0odTo{P?@>(mc^>hB%L`lKJkR0UM))!+lsO6yCSXw z>}K&1751SEfmO+>EI$$MgJ`B?)p|;zu7IxOeAih}Sp6Of;wp6v*!rceL#Oq_uAtp0 zj9g<`FyChd7Y4Uw>>H{NTnGC-qa3A7hf`B9d*_2OtP!c2< z+2WgKV4QXthxvR^p3XG41bHliGkN*Ed`)sEKO044Q3`mX)SNlS3O}=*>()h^mt;&F zn!h^9;YDz0feS{{vn+&GqMV2OH=wE(CMUF6i^9g?ey8{=pvA1el3*f7hq*YcQZ=z) zOx4RZ@{H=NYihNP&{vGg{0`&cS|8cleLLJop>((vQkidN{Gb+4jJp<-#&nb~r_&;py^=z%{eJS&LY#NVutePxyq{(n&x=2TCY(m2t6pkPoJ)jVX2Y zw3DR?C(-a$__aC5$+ARN(=rwx<7pTbg4)+EH06hMJ1WOrNMW+RE0T3=jY=PKuabJx zo}pVMJBl8aoQjsw%Qy|$mmC>b68D+aH))0(^dzND*IK*4Gu7!X;%@s~Bd=u0mm~_& z#3|=MTEyeuFSW?|87Zl%H#;S2SEo$&#n8+3oLME9PV@>i-G94es2yz$uRA3CF!fai z)}AvYU}^8+mB!gUL?zi}OR-6A!7LK6QfzX8nOy30IRnXf5-+gNbBGrUpExCafZj~K zrsr~GX3WXO5IaL+=%|&l9`Q&)Kd}y$zd}nWOc{Dy;HZnRAD~m;Y2Foi~g{#7q<%6Q> zWMHSSkL?=ljUl(`3==k)n;M@OURBjkKL#hly>xS$Gc**L7#t1{F#ajr$?<4>!sho5 zj}MMV;1x(L4pY?nhNDj6KD>#7b2LHGSc5FVz~VEJB#n#=M28}Mv3|#d<0siW#|B4d z<0s{qtRC&7dnu)$mDvjy*JXk7aCC44$ug2$q))ab)}>mOvBl=TA2W2B+!-y% zWviL$`Xv_Z%+n^nK8wlE#N_7-n4M$tynfrH(UunY`(e#peOeO%s580&B%hZMj)cBkxa5B%TJc{L= z>nk{2CSGvh=v2r_nY1MU|305&!cAd{*p6H?E ztO&tvb74wvyOO=2A|I`+(0Vv8(G6O|8{oM0qC3H9cRI!gJB@0s{_Sb?W-ZLhu=Wib zT6Wg7tjUp`Jz~qgK8x%NN%vlEB11c!C&Ri<(%q4gF3mkSjBbI(ea--LnQPrsKua0I z{nZIJ_rqF6djLS?gdyacqyUT{xf}R+d9PR=3gWo^4>)^7!$~7d1MxzsD zSQKs?h{pTCh{k&dHe$KBYi+D-cxC@sxNj^}wiEyQPKw6+%c??UZJ_%5P{gwFn09&` zbiWiJ!Bbm%;%)u)gX6t*qa$3uqI3!+Sre(RLG^ST(HI@+8;ZqM&E&*rM+|QCwZ}E6 z`dH88&eqY9h@;XT9~_MjPMoYz+wln*(x?bavHrHAFfZYU+2Wt@U^X z*sdu=T{jCgfaTmO*0Gq>VI}D#>}=?wbGz;8oM8PA502Ak)a{9rvGEDD9Sx$jvTkf> zqAof#)DuOc+1%CM!DN*ck>1gMRAr*NlI=2KN;1cHTM6kK+O~BmhH7+VVsK<~baI?A zYaPWZeiE%`RaIm{)v{Q+wp3#iU-hkPYi+IBTCeK(>M9OZJgnkjH4g{#um*=#EpFBF zRw$s)Ob$(`q0y0@A$>?`sJhltYiwT{8$2SIjIrY2l7yziu8(oGxxJ|^ z(%!Tc_0H!&d~)SnV;4g`uFvStX~QPqu3j!d8;8C#~9q2C^h4~`8a5)9LegoDY2 z;wWP`P^Xx)_wKGbol!$PJ{nK7ocbmNgl4yGl~HKAaXRKYk90DKD|^&%B&`*AHN2%h z(lazTass+g`?hwxV`|4^aKvu==uG3iQFbt=O6(CwhB7n^cu?QeSyS86pd#o99Sz%$ z`jP=^Q^T|X%{1CG6l>~=pkN%~a8)#hUYQ6|YL8^iB*LeAX+uW`-WEozSmL^&STwE& z!LGWs2~V9-&gn($*6axD(A0D!cC*(-oN#n>!C+UH9vnAgjNI1I5vfdPVDN86uVFcB zS|e?nHo>zK#8ISx+uHO>W{Cy#dx_MVU!-KH~ZV`glXH9d&vbYnrF98*bctYL%|(TAGo*uJ$v zk8bt^mQe2OjgBNnlCfw!I*j)3^rM7eW>qw-Ra-DsrcR1ULv|xyflhdmT!+eT=ImWg zvr9_HNn7_kN0vGQ+Fj2cu{&GaIceiqmDYZ0YTG)xRPyN4*4f_BfDYhTO>I84+d6mH zqg~(VBm$wIaRJfd$L1T8y%0;^!1_7jDLw4dysLmNSlr;6N%CUw)1SPX@XT> zmSXjn2@d`;!J6r+NLg0sR-wB~W%6jdr5=Iph>gW22D##p0a1ayiU&J?ELPY?)pXme ztJ~eKJ>6P6M=wh5tz8YR?J2!g zGpe{^N*#p3XpN3Ucg7MOXCgK{rrNr8v|}V|8o~TC(yQkRj1H(`Ov!qv*G{wRCJ#)y zQLtK4NAStW#O_G{kUfve!w+%R7?*d)#PW zB0@>_I%5-&mac|6EK9JsWkb)9#VQCAmfZ)xeQX{v8JvO`aCT^t0}*4CzkdSYN| z8lN5_F7y7O6mG|sCvHC4 zw?EPBaDl)DCWb40{m?Yh7u#)jhUrOox+AqUb?#QRljEsnY)KhXJ7T>tTph3jtkXRV zmk~NTY{$u$Hui!z5kdB^q~a%CW3+WNumTTGZn@KwV1&!W-Kr6n0BLU3M{4awM(Te5aBhz=`Z6u)I)GPg)8wocF)__vJj{RSwvmb9 z2~|EYIvgwSkM%{%TbtUu$~&TcgQM*OqZ6YegT0Z?$)538yg%9-i^QXS(Rlgh*hnlM zofwTr+Usi5l);INkM>XC$|vSDpOhh1T96(BI(Db5JDm<`_bFM_>b0f55UgwNPz`N$ zov|V5U21b(-TF{T<-zOqwHz*mD$A-4Ouw+hV*x&m{5v+>SU4@{4`@31sR!lG#=Fh` zujv9OGa#Ru)C9ffn3o#*iK!#vQ=i%Re7f_W@zecJ&W}%vkp5ie_mA|F^GVj@Qzhq# z6i)TirJA7YT;r6iCxfcS$G6g)jZd5)yVR%&=9slvL07FWB~LzyO7<-|&zedIqkQ(F zj1@R_uWcx6RT%+KYo?jy&2tqPbBuY`d}D!8Xe`2emP`2jCv8h+xzziAPZnEz3X`A889uS)3uj_l`Q;7Aytk?WJ#Na=lrR1z6~(FS<06t=Nl2zn}wQ7O`qHreNe!X)d|UzDc5Nb65)*>b)? zU~jg(JJGDCEmLmcjfYf!7i)V@OKST)k^}+$P?~;7>rc0W(6lnnELD`IU!?U*6Iw-y zGoDzgIE`MGMlVmJr)!=93-1pnZa2dip^#3J5jv6-Y z)=$u<=?weT>xA5+j!Mz@+HWH#df9eoG($A&QdqFcj$6fZWchcm4OQZ1&GqKTLb{ai5jV=aFmTf;z)uhS! z!veDGcowMbLbrpLhyHnDn*J$i^u=lPHEHyXpvkiB&r^2`ZTmA{{Wwkk#WeaA(dU?y zhyMC@n*2SH^9_qU^iQ1;bh$A;nao%=((}^jP#Rs5M)TK{&c^hIrO{1k^bu+F383ln z6!tvy_tS-@tvnS{HwbOVqe$JKmVWxJ0ej)TbV4odOSy2Ex%{1Z%{gP?KFjq=@{PNh z_p(#3=+bWnaoOlxeDgeQk!)XQ*tfIwrI*}KO}Qd4|?|7x`|6j`jdJwopkTgzJ&%ODVHXoXFMoKn3=x$z+dG-HSG@dTKg`3 z+JZdsNG0`&P2z^ObN!HfJwJV4TVJZ$4|bdz?^kEtjtII|^tqleBTBUpyTuM(3DWlaY})L%e|=*PC^Z1b%|ZNTgb4W< z@p!!DM?3*db%J*Z zJ|g&*Ab*$3bQ!p8AkG!sBzUCYNrLwX{z&jof`1bXxNJMe3i7iHw99vkiI)i8DEO%0 z>w@nIej!+f%Mqr#Q1Cjz&jkz7FencRt`Iy}uu*WU;5NZg!AZf>1ivY`NAO<+ev*0m;y97@YJX`Pr!Ak|N z5`0MThk{QCJ|p;!;C{i61@#vh;Ll=QuF|iif(Hp!2(A&_Ac$KLTE9uKTX0P9Ou@?q z_XyrA__*Md;2VOKe%o%n;E3S4g4YY`uK>W`r-XiA(1o88u^gF#3k8b=R|u8~^2fK- z-y(Rl;PHZ|2wo(3v*5FWuL!;+_>rI)wC#oj!-5+Gw+Idh?h-s#@LPg=1n&|2q2RNE zuL!;+_!q%!{7R7J3JW$0_6eRT_zl4;i3j6Xr-FA0-XnOQ;A6y%O8rFeIU@3TkyxhG zD}t|!{2ihHEcl@y7ZSAN67&;cXATjIfCYkI5&24?D+E^yHi*1Quv7Tk1-~jdEbO z%p)S7g~S#3X_H{F$SZ|jBe-6$S>$bkJA{9nV2|Lq$WIbHUHI1!k?$VjGW>o(@E+m+ zfVf1de-nI+2)~~Z`uBn#33{-=qkf^_G9v7UiBDC4>{JsW?-KqF!D9tSh|r4* zo+kXW1kV$^TIAOY-X{FJ1n(C7k;tDAd|vo_1z!?;OXTkeekAo!@P8)woZ#yse?#yc;s06iLqQiV z1XymbV2}v^77)?Cmk>kvsi0tm@YfN)g6|LrRuf@oi_qJMNPjF5H!Y)rF(ULvg+7G{ zy|an9#d^NrMMUUbDfEqkcM_q0FA@6#f)5j+|Af#l5TW-H5q16>!9NQBT_XDap9Mb? zK0o?lV$637;wP%w&O9RK%7uct^6$q4}W~@>dJ;gD#}E3ic2&&-DwA2*w4^ zCL##u3tlRyueZU!Ug&=kyj}301@9B&muhH-UsWMKFZc(+w*>i>6v}xomB_E55c#QB zBENb<9Ym-RT9$Q7Ub7QNIxX_yx^1|KQ2P~n}Ynl z2?RL`FT(xKPN&A3-XI1r0WE`1o;_1^7(xbVqB2l0U>>{AiwuP`gTEn!-M0j zzHb10O6X?=`S}ixufG+1OYj{*ez}9=>VF7k@csbkEJ1#&gX8F8!R3Mn3F>}>Psn2V zr^hFBGd+HVh#22Wh#3DWh!`Ky74-O7O~m-xNW}QtPDDQ2iO9d32)_r2D3|U(A^COn z65Qt^AM3gch-kl;6VWfOC1Tyahln`cNjwNY`siInloVEae>_>DitZygbF<1+}x>v$sK#AgnS&*enK>2 z%B}C0g_PPsdWlju5K%sTzYOIvT%b{&HX_RL02(CyzupUk-%k?ZZvp+SweN${-=#vA z5aIV~p`oh%uNS(Jh;noZy`6~i^a(vcM7bt}-c3aL&K3FsBFcHC(AN@C-tP&0FA?Q_ zQs}3NDF5q1zd=MCJ`(yoUIz`65l()= z%;wB|T4eKQJ~OiUGoBpT>{*^4*@EP!NH%B2vm~3H_Ksi}uMUZYv=@!1C23EUrUiJI zGW%POX)0g(kjTy%W>Q`cOG!QZ)1pMel;=Px31>VJN|B~K1e%u2_HI^^l)uJFd1cY| zBjt%qSNhL^rqieBB|W*(8h!j73w{^WKZ^FG&!as(@z^evB*iPU$t2#<9@!Z~qhlr7 zX=ZZpLSD?Vh*qn@y`#hWcM3_V`thML_CdSkqg&9%bAx)aiG_{xiK&=%wfD5~Va?G^eVC-`H&Htpe@G?!wM=pJPwXw*~Zk?9N6#Zd}JF+iQot5O}nQ zTc8Ph`7oAjuMe{1HsjdiyBNv##$c~R?ByicTa#w*+ApzJm1gf+*rOf#mzQMk=rnuJ zL*~Q`r-^gUGx(S2A5%DQr-E!wIXEvRm*Y<4%Qnb-F^wkTaz&cG5a`+Rb>8{lx|Q2f z=*ANH7@<-l~Gu=i$~z0*KDU+kbw z$KLPL?0pJ*j34bS5y@5D5FH7Mkv&fp3?$KE+iy44`HqL zxY!~%_AX7cx92$f8iw{tusim?lV)!hGP{?CWOMA@oMx{b?;x~8NPAcgChYwn&E9fM zJgZqjvN`tnZcuW)?di6!wP>#tyW`(a#9oD@KN=@{IiSf#d)$AXrneIB9B|HaHb?KZ zH2=Dw_kiORl%1;ib((*T(dqKi7stQ1p@(W3bMo=l*xy)nXvZ`Ws)=m_^x8dkn{EJ? k_HwW@CP~dmUEFA2+kmY%#~v;bQuMCvQR>sA3>>}x3t~32fdBvi literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_ll_dma.d b/build/stm32f7xx_ll_dma.d new file mode 100644 index 0000000..a6e131b --- /dev/null +++ b/build/stm32f7xx_ll_dma.d @@ -0,0 +1,72 @@ +build/stm32f7xx_ll_dma.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h: diff --git a/build/stm32f7xx_ll_dma.lst b/build/stm32f7xx_ll_dma.lst new file mode 100644 index 0000000..301eb07 --- /dev/null +++ b/build/stm32f7xx_ll_dma.lst @@ -0,0 +1,3506 @@ +ARM GAS /tmp/ccMRPLCc.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_ll_dma.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c" + 19 .section .text.LL_DMA_DeInit,"ax",%progbits + 20 .align 1 + 21 .global LL_DMA_DeInit + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 LL_DMA_DeInit: + 27 .LVL0: + 28 .LFB320: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @file stm32f7xx_ll_dma.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @brief DMA LL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * This software is licensed under terms that can be found in the LICENSE file in + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** */ + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #if defined(USE_FULL_LL_DRIVER) + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Includes ------------------------------------------------------------------*/ + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #include "stm32f7xx_ll_dma.h" + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #include "stm32f7xx_ll_bus.h" + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #ifdef USE_FULL_ASSERT + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #include "stm32_assert.h" + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #else + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define assert_param(expr) ((void)0U) + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #endif + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /** @addtogroup STM32F7xx_LL_Driver + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @{ + ARM GAS /tmp/ccMRPLCc.s page 2 + + + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** */ + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #if defined (DMA1) || defined (DMA2) + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /** @defgroup DMA_LL DMA + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @{ + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** */ + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Private types -------------------------------------------------------------*/ + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Private variables ---------------------------------------------------------*/ + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Private constants ---------------------------------------------------------*/ + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Private macros ------------------------------------------------------------*/ + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /** @addtogroup DMA_LL_Private_Macros + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @{ + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** */ + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY) + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \ + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_MODE_PFCTRL)) + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #if defined(DMA_CHANNEL_SELECTION_8_15) + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \ + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_1) || \ + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_2) || \ + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_3) || \ + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_4) || \ + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_5) || \ + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_6) || \ + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_7) || \ + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_8) || \ + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_9) || \ + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_10) || \ + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_11) || \ + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_12) || \ + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_13) || \ + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_14) || \ + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_15)) + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + ARM GAS /tmp/ccMRPLCc.s page 3 + + + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #else + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \ + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_1) || \ + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_2) || \ + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_3) || \ + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_4) || \ + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_5) || \ + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_6) || \ + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_CHANNEL_7)) + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #endif /* DMA_CHANNEL_SELECTION_8_15 */ + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \ + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** (((STREAM) == LL_DMA_STREAM_0) || \ + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((STREAM) == LL_DMA_STREAM_1) || \ + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((STREAM) == LL_DMA_STREAM_2) || \ + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((STREAM) == LL_DMA_STREAM_3) || \ + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((STREAM) == LL_DMA_STREAM_4) || \ + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((STREAM) == LL_DMA_STREAM_5) || \ + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((STREAM) == LL_DMA_STREAM_6) || \ + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((STREAM) == LL_DMA_STREAM_7) || \ + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((STREAM) == LL_DMA_STREAM_ALL))) ||\ + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** (((INSTANCE) == DMA2) && \ + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** (((STREAM) == LL_DMA_STREAM_0) || \ + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((STREAM) == LL_DMA_STREAM_1) || \ + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((STREAM) == LL_DMA_STREAM_2) || \ + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((STREAM) == LL_DMA_STREAM_3) || \ + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((STREAM) == LL_DMA_STREAM_4) || \ + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((STREAM) == LL_DMA_STREAM_5) || \ + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((STREAM) == LL_DMA_STREAM_6) || \ + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((STREAM) == LL_DMA_STREAM_7) || \ + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((STREAM) == LL_DMA_STREAM_ALL)))) + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \ + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((STATE) == LL_DMA_FIFOMODE_ENABLE)) + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \ + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \ + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \ + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL)) + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \ + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((BURST) == LL_DMA_MBURST_INC4) || \ + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((BURST) == LL_DMA_MBURST_INC8) || \ + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((BURST) == LL_DMA_MBURST_INC16)) + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** #define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \ + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((BURST) == LL_DMA_PBURST_INC4) || \ + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((BURST) == LL_DMA_PBURST_INC8) || \ + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ((BURST) == LL_DMA_PBURST_INC16)) + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /** + ARM GAS /tmp/ccMRPLCc.s page 4 + + + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @} + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** */ + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Private function prototypes -----------------------------------------------*/ + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Exported functions --------------------------------------------------------*/ + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /** @addtogroup DMA_LL_Exported_Functions + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @{ + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** */ + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /** @addtogroup DMA_LL_EF_Init + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @{ + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** */ + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /** + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @brief De-initialize the DMA registers to their default reset values. + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @param DMAx DMAx Instance + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @param Stream This parameter can be one of the following values: + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @arg @ref LL_DMA_STREAM_0 + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @arg @ref LL_DMA_STREAM_1 + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @arg @ref LL_DMA_STREAM_2 + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @arg @ref LL_DMA_STREAM_3 + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @arg @ref LL_DMA_STREAM_4 + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @arg @ref LL_DMA_STREAM_5 + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @arg @ref LL_DMA_STREAM_6 + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @arg @ref LL_DMA_STREAM_7 + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @arg @ref LL_DMA_STREAM_ALL + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @retval An ErrorStatus enumeration value: + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * - SUCCESS: DMA registers are de-initialized + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * - ERROR: DMA registers are not de-initialized + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** */ + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream) + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 29 .loc 1 177 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0; + 33 .loc 1 178 3 view .LVU1 + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ErrorStatus status = SUCCESS; + 34 .loc 1 179 3 view .LVU2 + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Check the DMA Instance DMAx and Stream parameters*/ + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)); + 35 .loc 1 182 3 view .LVU3 + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** if (Stream == LL_DMA_STREAM_ALL) + 36 .loc 1 184 3 view .LVU4 + 37 .loc 1 184 6 is_stmt 0 view .LVU5 + 38 0000 11F5803F cmn r1, #65536 + 39 0004 58D0 beq .L35 + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0; + 40 .loc 1 177 1 view .LVU6 + 41 0006 10B5 push {r4, lr} + 42 .LCFI0: + 43 .cfi_def_cfa_offset 8 + 44 .cfi_offset 4, -8 + ARM GAS /tmp/ccMRPLCc.s page 5 + + + 45 .cfi_offset 14, -4 + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** if (DMAx == DMA1) + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Force reset of DMA clock */ + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Release reset of DMA clock */ + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** else if (DMAx == DMA2) + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Force reset of DMA clock */ + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2); + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Release reset of DMA clock */ + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** else + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** status = ERROR; + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** else + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Disable the selected Stream */ + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_DMA_DisableStream(DMAx,Stream); + 46 .loc 1 210 5 is_stmt 1 view .LVU7 + 47 .LVL1: + 48 .LBB30: + 49 .LBI30: + 50 .file 2 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @file stm32f7xx_ll_dma.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Header file of DMA LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * This software is licensed under terms that can be found in the LICENSE file in + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifndef __STM32F7xx_LL_DMA_H + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __STM32F7xx_LL_DMA_H + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #ifdef __cplusplus + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** extern "C" { + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif + ARM GAS /tmp/ccMRPLCc.s page 6 + + + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Includes ------------------------------------------------------------------*/ + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #include "stm32f7xx.h" + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @addtogroup STM32F7xx_LL_Driver + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined (DMA1) || defined (DMA2) + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL DMA + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private types -------------------------------------------------------------*/ + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private variables ---------------------------------------------------------*/ + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Variables DMA Private Variables + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** static const uint8_t STREAM_OFFSET_TAB[] = + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** }; + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private constants ---------------------------------------------------------*/ + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Private_Constants DMA Private Constants + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_SxCR_CHSEL_3) + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define DMA_CHANNEL_SELECTION_8_15 + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_SxCR_CHSEL_3 */ + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Private macros ------------------------------------------------------------*/ + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported types ------------------------------------------------------------*/ + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(USE_FULL_LL_DRIVER) + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** typedef struct + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + ARM GAS /tmp/ccMRPLCc.s page 7 + + + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or as Source base address in case of memory to memory trans + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or as Destination base address in case of memory to memory + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Direction; /*!< Specifies if the data will be transferred from memory to pe + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** from memory to memory or from peripheral to memory. + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_DIRECTION + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Mode; /*!< Specifies the normal or circular operation mode. + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MODE + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The circular buffer mode cannot be used if the memory + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** data transfer direction is configured on the selected + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** is incremented or not. + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PERIPH + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** is incremented or not. + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MEMORY + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** in case of memory to memory transfer direction. + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination dat + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** in case of memory to memory transfer direction. + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** The data unit is equal to the source buffer configuration s + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** or MemorySize parameters depending in the transfer directio + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter must be a value between Min_Data = 0 and Max + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Channel; /*!< Specifies the peripheral channel. + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_CHANNEL + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + ARM GAS /tmp/ccMRPLCc.s page 8 + + + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t Priority; /*!< Specifies the channel priority level. + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PRIORITY + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_FIFOMODE + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The Direct mode (FIFO mode disabled) cannot be used i + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** memory-to-memory data transfer is configured on the selecte + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHO + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory t + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** It specifies the amount of data to be transferred in a sing + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** transaction. + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_MBURST + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The burst mode is possible only if the address Increm + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripher + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** It specifies the amount of data to be transferred in a sing + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** transaction. + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This parameter can be a value of @ref DMA_LL_EC_PBURST + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** @note The burst mode is possible only if the address Increm + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** This feature can be modified afterwards using unitary funct + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } LL_DMA_InitTypeDef; + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /*USE_FULL_LL_DRIVER*/ + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported constants --------------------------------------------------------*/ + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_STREAM STREAM + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_0 0x00000000U + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_1 0x00000001U + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_2 0x00000002U + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_3 0x00000003U + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_4 0x00000004U + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_5 0x00000005U + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_6 0x00000006U + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_7 0x00000007U + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_STREAM_ALL 0xFFFF0000U + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + ARM GAS /tmp/ccMRPLCc.s page 9 + + + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DIRECTION DIRECTION + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direc + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direc + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MODE MODE + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mo + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering m + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mo + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PERIPH PERIPH + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MEMORY MEMORY + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disa + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enab + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + ARM GAS /tmp/ccMRPLCc.s page 10 + + + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : By + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : Ha + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Wo + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offse + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offse + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PRIORITY PRIORITY + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CHANNEL CHANNEL + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_0 0x00000000U + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #if defined(DMA_CHANNEL_SELECTION_8_15) + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CHANNEL_15 DMA_SxCR_CHSEL + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #endif /* DMA_CHANNEL_SELECTION_8_15 */ + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + ARM GAS /tmp/ccMRPLCc.s page 11 + + + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_MBURST MBURST + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_PBURST PBURST + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral b + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral b + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral b + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral b + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode di + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode en + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_lev + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_l + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_l + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_l + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empt + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO thresho + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO thresho + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO thresho + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO thresho + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM + ARM GAS /tmp/ccMRPLCc.s page 12 + + + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentT + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentT + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported macro ------------------------------------------------------------*/ + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Write a value in DMA register + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __INSTANCE__ DMA Instance + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __REG__ Register to be written + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __VALUE__ Value to be written in the register + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Read a value in DMA register + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __INSTANCE__ DMA Instance + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __REG__ Register to be read + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Register value + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMAx_Streamy into DMAx + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM_INSTANCE__ DMAx_Streamy + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval DMAx + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM_INSTANCE__ DMAx_Streamy + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval LL_DMA_CHANNEL_y + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ + ARM GAS /tmp/ccMRPLCc.s page 13 + + + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** LL_DMA_STREAM_7) + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __DMA_INSTANCE__ DMAx + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param __STREAM__ LL_DMA_STREAM_y + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval DMAx_Streamy + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DM + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** DMA2_Stream7) + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @} + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Exported functions --------------------------------------------------------*/ + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** @defgroup DMA_LL_EF_Configuration Configuration + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @{ + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + ARM GAS /tmp/ccMRPLCc.s page 14 + + + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable DMA stream. + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_EnableStream + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable DMA stream. + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_DisableStream + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) + 51 .loc 2 517 22 view .LVU8 + 52 .LBB31: + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 53 .loc 2 519 3 view .LVU9 + 54 0008 694B ldr r3, .L38 + 55 000a 13F801C0 ldrb ip, [r3, r1] @ zero_extendqisi2 + 56 000e 50F80C30 ldr r3, [r0, ip] + 57 0012 23F00103 bic r3, r3, #1 + 58 0016 40F80C30 str r3, [r0, ip] + 59 .LVL2: + 60 .loc 2 519 3 is_stmt 0 view .LVU10 + 61 .LBE31: + 62 .LBE30: + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Get the DMA Stream Instance */ + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream)); + 63 .loc 1 213 5 is_stmt 1 view .LVU11 + 64 .loc 1 213 34 is_stmt 0 view .LVU12 + 65 001a 664B ldr r3, .L38+4 + 66 001c C31A subs r3, r0, r3 + ARM GAS /tmp/ccMRPLCc.s page 15 + + + 67 001e 18BF it ne + 68 0020 0123 movne r3, #1 + 69 0022 0A1E subs r2, r1, #0 + 70 0024 18BF it ne + 71 0026 0122 movne r2, #1 + 72 .loc 1 213 11 view .LVU13 + 73 0028 53EA0204 orrs r4, r3, r2 + 74 002c 64D0 beq .L16 + 75 .loc 1 213 34 discriminator 1 view .LVU14 + 76 002e 624C ldr r4, .L38+8 + 77 0030 B0EB040E subs lr, r0, r4 + 78 0034 18BF it ne + 79 0036 4FF0010E movne lr, #1 + 80 003a 52EA0E02 orrs r2, r2, lr + 81 003e 72D0 beq .L17 + 82 .loc 1 213 34 discriminator 3 view .LVU15 + 83 0040 4A1E subs r2, r1, #1 + 84 0042 18BF it ne + 85 0044 0122 movne r2, #1 + 86 0046 53EA0204 orrs r4, r3, r2 + 87 004a 6ED0 beq .L18 + 88 .loc 1 213 34 discriminator 5 view .LVU16 + 89 004c 5EEA0202 orrs r2, lr, r2 + 90 0050 6DD0 beq .L19 + 91 .loc 1 213 34 discriminator 7 view .LVU17 + 92 0052 8A1E subs r2, r1, #2 + 93 0054 18BF it ne + 94 0056 0122 movne r2, #1 + 95 0058 53EA0204 orrs r4, r3, r2 + 96 005c 69D0 beq .L20 + 97 .loc 1 213 34 discriminator 9 view .LVU18 + 98 005e 5EEA0202 orrs r2, lr, r2 + 99 0062 68D0 beq .L21 + 100 .loc 1 213 34 discriminator 11 view .LVU19 + 101 0064 CA1E subs r2, r1, #3 + 102 0066 18BF it ne + 103 0068 0122 movne r2, #1 + 104 006a 53EA0204 orrs r4, r3, r2 + 105 006e 64D0 beq .L22 + 106 .loc 1 213 34 discriminator 13 view .LVU20 + 107 0070 5EEA0202 orrs r2, lr, r2 + 108 0074 63D0 beq .L23 + 109 .loc 1 213 34 discriminator 15 view .LVU21 + 110 0076 0A1F subs r2, r1, #4 + 111 0078 18BF it ne + 112 007a 0122 movne r2, #1 + 113 007c 53EA0204 orrs r4, r3, r2 + 114 0080 5FD0 beq .L24 + 115 .loc 1 213 34 discriminator 17 view .LVU22 + 116 0082 5EEA0202 orrs r2, lr, r2 + 117 0086 5ED0 beq .L25 + 118 .loc 1 213 34 discriminator 19 view .LVU23 + 119 0088 4A1F subs r2, r1, #5 + 120 008a 18BF it ne + 121 008c 0122 movne r2, #1 + 122 008e 53EA0204 orrs r4, r3, r2 + 123 0092 5AD0 beq .L26 + ARM GAS /tmp/ccMRPLCc.s page 16 + + + 124 .loc 1 213 34 discriminator 21 view .LVU24 + 125 0094 5EEA0202 orrs r2, lr, r2 + 126 0098 59D0 beq .L27 + 127 .loc 1 213 34 discriminator 23 view .LVU25 + 128 009a 8A1F subs r2, r1, #6 + 129 009c 18BF it ne + 130 009e 0122 movne r2, #1 + 131 00a0 1343 orrs r3, r3, r2 + 132 00a2 56D0 beq .L28 + 133 .loc 1 213 34 discriminator 25 view .LVU26 + 134 00a4 5EEA0202 orrs r2, lr, r2 + 135 00a8 55D0 beq .L29 + 136 .loc 1 213 34 discriminator 27 view .LVU27 + 137 00aa 424B ldr r3, .L38+4 + 138 00ac 9842 cmp r0, r3 + 139 00ae 08BF it eq + 140 00b0 0729 cmpeq r1, #7 + 141 00b2 52D1 bne .L30 + 142 .loc 1 213 34 discriminator 29 view .LVU28 + 143 00b4 B833 adds r3, r3, #184 + 144 00b6 20E0 b .L5 + 145 .L35: + 146 .LCFI1: + 147 .cfi_def_cfa_offset 0 + 148 .cfi_restore 4 + 149 .cfi_restore 14 + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 150 .loc 1 186 5 is_stmt 1 view .LVU29 + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 151 .loc 1 186 8 is_stmt 0 view .LVU30 + 152 00b8 3E4B ldr r3, .L38+4 + 153 00ba 9842 cmp r0, r3 + 154 00bc 04D0 beq .L36 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 155 .loc 1 194 10 is_stmt 1 view .LVU31 + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 156 .loc 1 194 13 is_stmt 0 view .LVU32 + 157 00be 3E4B ldr r3, .L38+8 + 158 00c0 9842 cmp r0, r3 + 159 00c2 0DD0 beq .L37 + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 160 .loc 1 204 14 view .LVU33 + 161 00c4 0120 movs r0, #1 + 162 .LVL3: + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Reset DMAx_Streamy configuration register */ + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_DMA_WriteReg(tmp, CR, 0U); + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Reset DMAx_Streamy remaining bytes register */ + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_DMA_WriteReg(tmp, NDTR, 0U); + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Reset DMAx_Streamy peripheral address register */ + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_DMA_WriteReg(tmp, PAR, 0U); + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Reset DMAx_Streamy memory address register */ + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_DMA_WriteReg(tmp, M0AR, 0U); + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + ARM GAS /tmp/ccMRPLCc.s page 17 + + + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Reset DMAx_Streamy memory address register */ + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_DMA_WriteReg(tmp, M1AR, 0U); + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Reset DMAx_Streamy FIFO control register */ + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_DMA_WriteReg(tmp, FCR, 0x00000021U); + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Reset Channel register field for DMAx Stream*/ + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0); + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** if(Stream == LL_DMA_STREAM_0) + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Reset the Stream0 pending flags */ + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMAx->LIFCR = 0x0000003FU; + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** else if(Stream == LL_DMA_STREAM_1) + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Reset the Stream1 pending flags */ + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMAx->LIFCR = 0x00000F40U; + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** else if(Stream == LL_DMA_STREAM_2) + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Reset the Stream2 pending flags */ + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMAx->LIFCR = 0x003F0000U; + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** else if(Stream == LL_DMA_STREAM_3) + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Reset the Stream3 pending flags */ + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMAx->LIFCR = 0x0F400000U; + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** else if(Stream == LL_DMA_STREAM_4) + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Reset the Stream4 pending flags */ + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMAx->HIFCR = 0x0000003FU; + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** else if(Stream == LL_DMA_STREAM_5) + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Reset the Stream5 pending flags */ + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMAx->HIFCR = 0x00000F40U; + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** else if(Stream == LL_DMA_STREAM_6) + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Reset the Stream6 pending flags */ + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMAx->HIFCR = 0x003F0000U; + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** else if(Stream == LL_DMA_STREAM_7) + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Reset the Stream7 pending flags */ + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMAx->HIFCR = 0x0F400000U; + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** else + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** status = ERROR; + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** return status; + 163 .loc 1 282 3 is_stmt 1 view .LVU34 + ARM GAS /tmp/ccMRPLCc.s page 18 + + + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 164 .loc 1 283 1 is_stmt 0 view .LVU35 + 165 00c6 7047 bx lr + 166 .LVL4: + 167 .L36: + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 168 .loc 1 189 7 is_stmt 1 view .LVU36 + 169 .LBB32: + 170 .LBI32: + 171 .file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @file stm32f7xx_ll_bus.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @verbatim + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @attention + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * Copyright (c) 2017 STMicroelectronics. + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * All rights reserved. + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * This software is licensed under terms that can be found in the LICENSE file in + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * the root directory of this software component. + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifndef __STM32F7xx_LL_BUS_H + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define __STM32F7xx_LL_BUS_H + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifdef __cplusplus + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** extern "C" { + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #include "stm32f7xx.h" + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @addtogroup STM32F7xx_LL_Driver + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + ARM GAS /tmp/ccMRPLCc.s page 19 + + + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC) + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOJ) + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOJ */ + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOK) + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOK */ + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DTCMRAM RCC_AHB1ENR_DTCMRAMEN + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DMA2D) + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DMA2D */ + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(ETH) + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* ETH */ + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_AXI RCC_AHB1LPENR_AXILPEN + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN + ARM GAS /tmp/ccMRPLCc.s page 20 + + + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DCMI) + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DCMI */ + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(JPEG) + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_JPEG RCC_AHB2ENR_JPEGEN + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* JPEG */ + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CRYP) + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CRYP */ + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(AES) + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* AES */ + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(HASH) + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* HASH */ + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPDIFRX) + ARM GAS /tmp/ccMRPLCc.s page 21 + + + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPDIFRX */ + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(I2C4) + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C4 RCC_APB1ENR_I2C4EN + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* I2C4 */ + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN2) + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN2 */ + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN3) + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN3 */ + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CEC) + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CEC */ + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC_APB1ENR_RTCEN) + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCEN + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* RCC_APB1ENR_RTCEN */ + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SDMMC2) + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC2 RCC_APB2ENR_SDMMC2EN + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SDMMC2 */ + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPI6) + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN + ARM GAS /tmp/ccMRPLCc.s page 22 + + + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPI6 */ + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(LTDC) + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* LTDC */ + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DSI) + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DSI */ + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DFSDM1_Channel0) + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DFSDM1_Channel0 */ + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(MDIOS) + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_MDIO RCC_APB2ENR_MDIOEN + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* MDIOS */ + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(USB_HS_PHYC) + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_OTGPHYC RCC_APB2ENR_OTGPHYCEN + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* USB_HS_PHYC */ + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_EnableClock\n + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n + ARM GAS /tmp/ccMRPLCc.s page 23 + + + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n + ARM GAS /tmp/ccMRPLCc.s page 24 + + + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_IsEnabledClock\n + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_IsEnabledClock + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n + ARM GAS /tmp/ccMRPLCc.s page 25 + + + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_DisableClock\n + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_DisableClock + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1ENR, Periphs); + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n + ARM GAS /tmp/ccMRPLCc.s page 26 + + + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 172 .loc 3 476 22 view .LVU37 + 173 .LBB33: + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1RSTR, Periphs); + 174 .loc 3 478 3 view .LVU38 + 175 00c8 A3F52053 sub r3, r3, #10240 + 176 00cc 1A69 ldr r2, [r3, #16] + 177 00ce 42F40012 orr r2, r2, #2097152 + 178 00d2 1A61 str r2, [r3, #16] + 179 .LVL5: + 180 .loc 3 478 3 is_stmt 0 view .LVU39 + 181 .LBE33: + 182 .LBE32: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 183 .loc 1 192 7 is_stmt 1 view .LVU40 + 184 .LBB34: + 185 .LBI34: + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n + ARM GAS /tmp/ccMRPLCc.s page 27 + + + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 186 .loc 3 523 22 view .LVU41 + 187 .LBB35: + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1RSTR, Periphs); + 188 .loc 3 525 3 view .LVU42 + 189 00d4 1A69 ldr r2, [r3, #16] + 190 00d6 22F40012 bic r2, r2, #2097152 + 191 00da 1A61 str r2, [r3, #16] + 192 .LVL6: + 193 .loc 3 525 3 is_stmt 0 view .LVU43 + 194 .LBE35: + 195 .LBE34: + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 196 .loc 1 179 15 view .LVU44 + 197 00dc 0020 movs r0, #0 + 198 .LVL7: + 199 .LBB37: + 200 .LBB36: + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 201 .loc 3 526 1 view .LVU45 + 202 00de 7047 bx lr + 203 .LVL8: + ARM GAS /tmp/ccMRPLCc.s page 28 + + + 204 .L37: + 205 .loc 3 526 1 view .LVU46 + 206 .LBE36: + 207 .LBE37: + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 208 .loc 1 197 7 is_stmt 1 view .LVU47 + 209 .LBB38: + 210 .LBI38: + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 211 .loc 3 476 22 view .LVU48 + 212 .LBB39: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 213 .loc 3 478 3 view .LVU49 + 214 00e0 A3F53053 sub r3, r3, #11264 + 215 00e4 1A69 ldr r2, [r3, #16] + 216 00e6 42F48002 orr r2, r2, #4194304 + 217 00ea 1A61 str r2, [r3, #16] + 218 .LVL9: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 219 .loc 3 478 3 is_stmt 0 view .LVU50 + 220 .LBE39: + 221 .LBE38: + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 222 .loc 1 200 7 is_stmt 1 view .LVU51 + 223 .LBB40: + 224 .LBI40: + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 225 .loc 3 523 22 view .LVU52 + 226 .LBB41: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 227 .loc 3 525 3 view .LVU53 + 228 00ec 1A69 ldr r2, [r3, #16] + 229 00ee 22F48002 bic r2, r2, #4194304 + 230 00f2 1A61 str r2, [r3, #16] + 231 .LVL10: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 232 .loc 3 525 3 is_stmt 0 view .LVU54 + 233 .LBE41: + 234 .LBE40: + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 235 .loc 1 179 15 view .LVU55 + 236 00f4 0020 movs r0, #0 + 237 .LVL11: + 238 .LBB43: + 239 .LBB42: + 240 .loc 3 526 1 view .LVU56 + 241 00f6 7047 bx lr + 242 .LVL12: + 243 .L16: + 244 .LCFI2: + 245 .cfi_def_cfa_offset 8 + 246 .cfi_offset 4, -8 + 247 .cfi_offset 14, -4 + 248 .loc 3 526 1 view .LVU57 + 249 .LBE42: + 250 .LBE43: + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + ARM GAS /tmp/ccMRPLCc.s page 29 + + + 251 .loc 1 213 11 discriminator 2 view .LVU58 + 252 00f8 304B ldr r3, .L38+12 + 253 .L5: + 254 .LVL13: + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 255 .loc 1 216 5 is_stmt 1 view .LVU59 + 256 00fa 0022 movs r2, #0 + 257 00fc 1A60 str r2, [r3] + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 258 .loc 1 219 5 view .LVU60 + 259 00fe 5A60 str r2, [r3, #4] + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 260 .loc 1 222 5 view .LVU61 + 261 0100 9A60 str r2, [r3, #8] + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 262 .loc 1 225 5 view .LVU62 + 263 0102 DA60 str r2, [r3, #12] + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 264 .loc 1 228 5 view .LVU63 + 265 0104 1A61 str r2, [r3, #16] + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 266 .loc 1 231 5 view .LVU64 + 267 0106 2122 movs r2, #33 + 268 0108 5A61 str r2, [r3, #20] + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 269 .loc 1 234 5 view .LVU65 + 270 .LVL14: + 271 .LBB44: + 272 .LBI44: + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Check if DMA stream is enabled or disabled. + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR EN LL_DMA_IsEnabledStream + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval State of bit (1 or 0). + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure all parameters linked to DMA transfer. + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_ConfigTransfer\n + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR CIRC LL_DMA_ConfigTransfer\n + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PINC LL_DMA_ConfigTransfer\n + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR MINC LL_DMA_ConfigTransfer\n + ARM GAS /tmp/ccMRPLCc.s page 30 + + + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PSIZE LL_DMA_ConfigTransfer\n + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR MSIZE LL_DMA_ConfigTransfer\n + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PL LL_DMA_ConfigTransfer\n + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_ConfigTransfer + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Configuration This parameter must be a combination of all the following values: + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH o + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDAT + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDAT + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HI + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** *@retval None + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configurati + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_Sx + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** Configuration); + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Data transfer direction (read from peripheral or from memory). + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_SetDataTransferDirection + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Direction This parameter can be one of the following values: + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Data transfer direction (read from peripheral or from memory). + ARM GAS /tmp/ccMRPLCc.s page 31 + + + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DIR LL_DMA_GetDataTransferDirection + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set DMA mode normal, circular or peripheral flow control. + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CIRC LL_DMA_SetMode\n + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_SetMode + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Mode This parameter can be one of the following values: + 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL + 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_CIRCULAR + 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_PFCTRL + 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) + 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get DMA mode normal, circular or peripheral flow control. + 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CIRC LL_DMA_GetMode\n + 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * CR PFCTRL LL_DMA_GetMode + 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + ARM GAS /tmp/ccMRPLCc.s page 32 + + + 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_NORMAL + 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_CIRCULAR + 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MODE_PFCTRL + 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) + 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral increment mode. + 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINC LL_DMA_SetPeriphIncMode + 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param IncrementMode This parameter can be one of the following values: + 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_NOINCREMENT + 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT + 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment + 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral increment mode. + 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINC LL_DMA_GetPeriphIncMode + 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_NOINCREMENT + 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PERIPH_INCREMENT + 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) + 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + ARM GAS /tmp/ccMRPLCc.s page 33 + + + 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory increment mode. + 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MINC LL_DMA_SetMemoryIncMode + 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param IncrementMode This parameter can be one of the following values: + 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_NOINCREMENT + 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT + 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Increment + 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory increment mode. + 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MINC LL_DMA_GetMemoryIncMode + 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_NOINCREMENT + 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MEMORY_INCREMENT + 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) + 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral size. + 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PSIZE LL_DMA_SetPeriphSize + 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + ARM GAS /tmp/ccMRPLCc.s page 34 + + + 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Size This parameter can be one of the following values: + 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE + 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_WORD + 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) + 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral size. + 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PSIZE LL_DMA_GetPeriphSize + 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_BYTE + 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PDATAALIGN_WORD + 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) + 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory size. + 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MSIZE LL_DMA_SetMemorySize + 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Size This parameter can be one of the following values: + 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE + 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_WORD + 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) + 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + ARM GAS /tmp/ccMRPLCc.s page 35 + + + 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory size. + 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MSIZE LL_DMA_GetMemorySize + 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_BYTE + 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MDATAALIGN_WORD + 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) + 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral increment offset size. + 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize + 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param OffsetSize This parameter can be one of the following values: + 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSiz + 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral increment offset size. + 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize + 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + ARM GAS /tmp/ccMRPLCc.s page 36 + + + 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) + 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Stream priority level. + 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Priority This parameter can be one of the following values: + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW + 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_MEDIUM + 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_HIGH + 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_VERYHIGH + 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pr + 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Stream priority level. + 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel + 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: + 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_LOW + 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_MEDIUM + 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_HIGH + 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PRIORITY_VERYHIGH + ARM GAS /tmp/ccMRPLCc.s page 37 + + + 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) + 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Number of data to transfer. + 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll NDTR NDT LL_DMA_SetDataLength + 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This action has no effect if + 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * stream is enabled. + 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param NbData Between 0 to 0xFFFFFFFF + 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None + 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) + 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, + 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Number of data to transfer. + 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll NDTR NDT LL_DMA_GetDataLength + 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Once the stream is enabled, the return value indicate the + 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * remaining bytes to be transmitted. + 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance + 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: + 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 + 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 + 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 + 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 + 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Between 0 to 0xFFFFFFFF + 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) + 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- + 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** + 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Select Channel number associated to the Stream. +1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CHSEL LL_DMA_SetChannelSelection +1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 + ARM GAS /tmp/ccMRPLCc.s page 38 + + +1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Channel This parameter can be one of the following values: +1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_0 +1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 +1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 +1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 +1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 +1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 +1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 +1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 +1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_8 (*) +1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_9 (*) +1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_10 (*) +1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_11 (*) +1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_12 (*) +1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_13 (*) +1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_14 (*) +1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_15 (*) +1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * +1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * (*) value not defined in all devices. +1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channe + 273 .loc 2 1032 22 view .LVU66 + 274 .LBB45: +1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D + 275 .loc 2 1034 3 view .LVU67 + 276 010a 50F80C30 ldr r3, [r0, ip] + 277 .LVL15: + 278 .loc 2 1034 3 is_stmt 0 view .LVU68 + 279 010e 23F0F053 bic r3, r3, #503316480 + 280 0112 40F80C30 str r3, [r0, ip] + 281 .LVL16: + 282 .loc 2 1034 3 view .LVU69 + 283 .LBE45: + 284 .LBE44: + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 285 .loc 1 236 5 is_stmt 1 view .LVU70 + 286 0116 0729 cmp r1, #7 + 287 0118 47D8 bhi .L31 + 288 011a DFE801F0 tbb [pc, r1] + 289 .L7: + 290 011e 20 .byte (.L14-.L7)/2 + 291 011f 24 .byte (.L13-.L7)/2 + 292 0120 29 .byte (.L12-.L7)/2 + 293 0121 2E .byte (.L11-.L7)/2 + 294 0122 33 .byte (.L10-.L7)/2 + 295 0123 37 .byte (.L9-.L7)/2 + 296 0124 3C .byte (.L8-.L7)/2 + 297 0125 41 .byte (.L6-.L7)/2 + ARM GAS /tmp/ccMRPLCc.s page 39 + + + 298 .LVL17: + 299 .p2align 1 + 300 .L17: + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 301 .loc 1 213 34 is_stmt 0 discriminator 4 view .LVU71 + 302 0126 264B ldr r3, .L38+16 + 303 0128 E7E7 b .L5 + 304 .L18: + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 305 .loc 1 213 34 discriminator 6 view .LVU72 + 306 012a 264B ldr r3, .L38+20 + 307 012c E5E7 b .L5 + 308 .L19: + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 309 .loc 1 213 34 discriminator 8 view .LVU73 + 310 012e 264B ldr r3, .L38+24 + 311 0130 E3E7 b .L5 + 312 .L20: + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 313 .loc 1 213 34 discriminator 10 view .LVU74 + 314 0132 264B ldr r3, .L38+28 + 315 0134 E1E7 b .L5 + 316 .L21: + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 317 .loc 1 213 34 discriminator 12 view .LVU75 + 318 0136 264B ldr r3, .L38+32 + 319 0138 DFE7 b .L5 + 320 .L22: + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 321 .loc 1 213 34 discriminator 14 view .LVU76 + 322 013a 264B ldr r3, .L38+36 + 323 013c DDE7 b .L5 + 324 .L23: + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 325 .loc 1 213 34 discriminator 16 view .LVU77 + 326 013e 264B ldr r3, .L38+40 + 327 0140 DBE7 b .L5 + 328 .L24: + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 329 .loc 1 213 34 discriminator 18 view .LVU78 + 330 0142 264B ldr r3, .L38+44 + 331 0144 D9E7 b .L5 + 332 .L25: + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 333 .loc 1 213 34 discriminator 20 view .LVU79 + 334 0146 264B ldr r3, .L38+48 + 335 0148 D7E7 b .L5 + 336 .L26: + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 337 .loc 1 213 34 discriminator 22 view .LVU80 + 338 014a 264B ldr r3, .L38+52 + 339 014c D5E7 b .L5 + 340 .L27: + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 341 .loc 1 213 34 discriminator 24 view .LVU81 + 342 014e 264B ldr r3, .L38+56 + 343 0150 D3E7 b .L5 + ARM GAS /tmp/ccMRPLCc.s page 40 + + + 344 .L28: + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 345 .loc 1 213 34 discriminator 26 view .LVU82 + 346 0152 264B ldr r3, .L38+60 + 347 0154 D1E7 b .L5 + 348 .L29: + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 349 .loc 1 213 34 discriminator 28 view .LVU83 + 350 0156 264B ldr r3, .L38+64 + 351 0158 CFE7 b .L5 + 352 .L30: + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 353 .loc 1 213 34 discriminator 30 view .LVU84 + 354 015a 264B ldr r3, .L38+68 + 355 015c CDE7 b .L5 + 356 .LVL18: + 357 .L14: + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 358 .loc 1 239 8 is_stmt 1 view .LVU85 + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 359 .loc 1 239 20 is_stmt 0 view .LVU86 + 360 015e 3F23 movs r3, #63 + 361 0160 8360 str r3, [r0, #8] + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 362 .loc 1 179 15 view .LVU87 + 363 0162 0020 movs r0, #0 + 364 .LVL19: + 365 .L4: + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 366 .loc 1 282 3 is_stmt 1 view .LVU88 + 367 .loc 1 283 1 is_stmt 0 view .LVU89 + 368 0164 10BD pop {r4, pc} + 369 .LVL20: + 370 .L13: + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 371 .loc 1 244 8 is_stmt 1 view .LVU90 + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 372 .loc 1 244 20 is_stmt 0 view .LVU91 + 373 0166 4FF47463 mov r3, #3904 + 374 016a 8360 str r3, [r0, #8] + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 375 .loc 1 179 15 view .LVU92 + 376 016c 0020 movs r0, #0 + 377 .LVL21: + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 378 .loc 1 179 15 view .LVU93 + 379 016e F9E7 b .L4 + 380 .LVL22: + 381 .L12: + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 382 .loc 1 249 8 is_stmt 1 view .LVU94 + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 383 .loc 1 249 20 is_stmt 0 view .LVU95 + 384 0170 4FF47C13 mov r3, #4128768 + 385 0174 8360 str r3, [r0, #8] + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 386 .loc 1 179 15 view .LVU96 + ARM GAS /tmp/ccMRPLCc.s page 41 + + + 387 0176 0020 movs r0, #0 + 388 .LVL23: + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 389 .loc 1 179 15 view .LVU97 + 390 0178 F4E7 b .L4 + 391 .LVL24: + 392 .L11: + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 393 .loc 1 254 8 is_stmt 1 view .LVU98 + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 394 .loc 1 254 20 is_stmt 0 view .LVU99 + 395 017a 4FF07463 mov r3, #255852544 + 396 017e 8360 str r3, [r0, #8] + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 397 .loc 1 179 15 view .LVU100 + 398 0180 0020 movs r0, #0 + 399 .LVL25: + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 400 .loc 1 179 15 view .LVU101 + 401 0182 EFE7 b .L4 + 402 .LVL26: + 403 .L10: + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 404 .loc 1 259 8 is_stmt 1 view .LVU102 + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 405 .loc 1 259 20 is_stmt 0 view .LVU103 + 406 0184 3F23 movs r3, #63 + 407 0186 C360 str r3, [r0, #12] + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 408 .loc 1 179 15 view .LVU104 + 409 0188 0020 movs r0, #0 + 410 .LVL27: + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 411 .loc 1 179 15 view .LVU105 + 412 018a EBE7 b .L4 + 413 .LVL28: + 414 .L9: + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 415 .loc 1 264 8 is_stmt 1 view .LVU106 + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 416 .loc 1 264 20 is_stmt 0 view .LVU107 + 417 018c 4FF47463 mov r3, #3904 + 418 0190 C360 str r3, [r0, #12] + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 419 .loc 1 179 15 view .LVU108 + 420 0192 0020 movs r0, #0 + 421 .LVL29: + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 422 .loc 1 179 15 view .LVU109 + 423 0194 E6E7 b .L4 + 424 .LVL30: + 425 .L8: + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 426 .loc 1 269 8 is_stmt 1 view .LVU110 + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 427 .loc 1 269 20 is_stmt 0 view .LVU111 + 428 0196 4FF47C13 mov r3, #4128768 + ARM GAS /tmp/ccMRPLCc.s page 42 + + + 429 019a C360 str r3, [r0, #12] + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 430 .loc 1 179 15 view .LVU112 + 431 019c 0020 movs r0, #0 + 432 .LVL31: + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 433 .loc 1 179 15 view .LVU113 + 434 019e E1E7 b .L4 + 435 .LVL32: + 436 .L6: + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 437 .loc 1 274 8 is_stmt 1 view .LVU114 + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 438 .loc 1 274 20 is_stmt 0 view .LVU115 + 439 01a0 4FF07463 mov r3, #255852544 + 440 01a4 C360 str r3, [r0, #12] + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 441 .loc 1 179 15 view .LVU116 + 442 01a6 0020 movs r0, #0 + 443 .LVL33: + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 444 .loc 1 179 15 view .LVU117 + 445 01a8 DCE7 b .L4 + 446 .LVL34: + 447 .L31: + 448 .LBB47: + 449 .LBB46: + 450 .loc 2 1034 3 view .LVU118 + 451 01aa 0120 movs r0, #1 + 452 .LVL35: + 453 .loc 2 1034 3 view .LVU119 + 454 01ac DAE7 b .L4 + 455 .L39: + 456 01ae 00BF .align 2 + 457 .L38: + 458 01b0 00000000 .word STREAM_OFFSET_TAB + 459 01b4 00600240 .word 1073897472 + 460 01b8 00640240 .word 1073898496 + 461 01bc 10600240 .word 1073897488 + 462 01c0 10640240 .word 1073898512 + 463 01c4 28600240 .word 1073897512 + 464 01c8 28640240 .word 1073898536 + 465 01cc 40600240 .word 1073897536 + 466 01d0 40640240 .word 1073898560 + 467 01d4 58600240 .word 1073897560 + 468 01d8 58640240 .word 1073898584 + 469 01dc 70600240 .word 1073897584 + 470 01e0 70640240 .word 1073898608 + 471 01e4 88600240 .word 1073897608 + 472 01e8 88640240 .word 1073898632 + 473 01ec A0600240 .word 1073897632 + 474 01f0 A0640240 .word 1073898656 + 475 01f4 B8640240 .word 1073898680 + 476 .LBE46: + 477 .LBE47: + 478 .cfi_endproc + 479 .LFE320: + ARM GAS /tmp/ccMRPLCc.s page 43 + + + 481 .section .text.LL_DMA_Init,"ax",%progbits + 482 .align 1 + 483 .global LL_DMA_Init + 484 .syntax unified + 485 .thumb + 486 .thumb_func + 488 LL_DMA_Init: + 489 .LVL36: + 490 .LFB321: + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /** + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros : + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @arg @ref __LL_DMA_GET_INSTANCE + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @arg @ref __LL_DMA_GET_STREAM + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @param DMAx DMAx Instance + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @param Stream This parameter can be one of the following values: + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @arg @ref LL_DMA_STREAM_0 + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @arg @ref LL_DMA_STREAM_1 + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @arg @ref LL_DMA_STREAM_2 + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @arg @ref LL_DMA_STREAM_3 + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @arg @ref LL_DMA_STREAM_4 + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @arg @ref LL_DMA_STREAM_5 + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @arg @ref LL_DMA_STREAM_6 + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @arg @ref LL_DMA_STREAM_7 + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @retval An ErrorStatus enumeration value: + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * - SUCCESS: DMA registers are initialized + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * - ERROR: Not applicable + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** */ + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct) + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 491 .loc 1 306 1 is_stmt 1 view -0 + 492 .cfi_startproc + 493 @ args = 0, pretend = 0, frame = 0 + 494 @ frame_needed = 0, uses_anonymous_args = 0 + 495 .loc 1 306 1 is_stmt 0 view .LVU121 + 496 0000 30B5 push {r4, r5, lr} + 497 .LCFI3: + 498 .cfi_def_cfa_offset 12 + 499 .cfi_offset 4, -12 + 500 .cfi_offset 5, -8 + 501 .cfi_offset 14, -4 + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Check the DMA Instance DMAx and Stream parameters*/ + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)); + 502 .loc 1 308 3 is_stmt 1 view .LVU122 + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Check the DMA parameters from DMA_InitStruct */ + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); + 503 .loc 1 311 3 view .LVU123 + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); + 504 .loc 1 312 3 view .LVU124 + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); + 505 .loc 1 313 3 view .LVU125 + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); + 506 .loc 1 314 3 view .LVU126 + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); + ARM GAS /tmp/ccMRPLCc.s page 44 + + + 507 .loc 1 315 3 view .LVU127 + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); + 508 .loc 1 316 3 view .LVU128 + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); + 509 .loc 1 317 3 view .LVU129 + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel)); + 510 .loc 1 318 3 view .LVU130 + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); + 511 .loc 1 319 3 view .LVU131 + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode)); + 512 .loc 1 320 3 view .LVU132 + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Check the memory burst, peripheral burst and FIFO threshold parameters only + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** when FIFO mode is enabled */ + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) + 513 .loc 1 323 3 view .LVU133 + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold)); + 514 .loc 1 325 5 view .LVU134 + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst)); + 515 .loc 1 326 5 view .LVU135 + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst)); + 516 .loc 1 327 5 view .LVU136 + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /*---------------------------- DMAx SxCR Configuration ------------------------ + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * Configure DMAx_Streamy: data transfer direction, data transfer mode, + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * peripheral and memory increment mode, + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * data size alignment and priority level with parameters : + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * - Direction: DMA_SxCR_DIR[1:0] bits + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * - Mode: DMA_SxCR_CIRC bit + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * - Priority: DMA_SxCR_PL[1:0] bits + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** */ + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \ + 517 .loc 1 342 3 view .LVU137 + 518 .loc 1 342 53 is_stmt 0 view .LVU138 + 519 0002 9368 ldr r3, [r2, #8] + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->Mode | \ + 520 .loc 1 343 39 view .LVU139 + 521 0004 D468 ldr r4, [r2, #12] + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->Mode | \ + 522 .loc 1 342 65 view .LVU140 + 523 0006 2343 orrs r3, r3, r4 + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->PeriphOrM2MSrcIncMode | \ + 524 .loc 1 344 39 view .LVU141 + 525 0008 1469 ldr r4, [r2, #16] + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->Mode | \ + 526 .loc 1 343 65 view .LVU142 + 527 000a 2343 orrs r3, r3, r4 + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->MemoryOrM2MDstIncMode | \ + 528 .loc 1 345 39 view .LVU143 + 529 000c 5469 ldr r4, [r2, #20] + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->PeriphOrM2MSrcIncMode | \ + 530 .loc 1 344 65 view .LVU144 + ARM GAS /tmp/ccMRPLCc.s page 45 + + + 531 000e 2343 orrs r3, r3, r4 + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->PeriphOrM2MSrcDataSize | \ + 532 .loc 1 346 39 view .LVU145 + 533 0010 9469 ldr r4, [r2, #24] + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->MemoryOrM2MDstIncMode | \ + 534 .loc 1 345 65 view .LVU146 + 535 0012 2343 orrs r3, r3, r4 + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->MemoryOrM2MDstDataSize | \ + 536 .loc 1 347 39 view .LVU147 + 537 0014 D469 ldr r4, [r2, #28] + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->PeriphOrM2MSrcDataSize | \ + 538 .loc 1 346 65 view .LVU148 + 539 0016 2343 orrs r3, r3, r4 + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->Priority + 540 .loc 1 348 39 view .LVU149 + 541 0018 946A ldr r4, [r2, #40] + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->Mode | \ + 542 .loc 1 342 3 view .LVU150 + 543 001a 2343 orrs r3, r3, r4 + 544 .LVL37: + 545 .LBB48: + 546 .LBI48: + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 547 .loc 2 572 22 is_stmt 1 view .LVU151 + 548 .LBB49: + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_Sx + 549 .loc 2 574 3 view .LVU152 + 550 001c 1C4C ldr r4, .L43 + 551 001e 615C ldrb r1, [r4, r1] @ zero_extendqisi2 + 552 .LVL38: + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_Sx + 553 .loc 2 574 3 is_stmt 0 view .LVU153 + 554 0020 01EB000C add ip, r1, r0 + 555 0024 4558 ldr r5, [r0, r1] + 556 0026 1B4C ldr r4, .L43+4 + 557 0028 2C40 ands r4, r4, r5 + 558 002a 2343 orrs r3, r3, r4 + 559 .LVL39: + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_Sx + 560 .loc 2 574 3 view .LVU154 + 561 002c 4350 str r3, [r0, r1] + 562 .LVL40: + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_Sx + 563 .loc 2 574 3 view .LVU155 + 564 .LBE49: + 565 .LBE48: + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** ); + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) + 566 .loc 1 351 3 is_stmt 1 view .LVU156 + 567 .loc 1 351 20 is_stmt 0 view .LVU157 + 568 002e D36A ldr r3, [r2, #44] + 569 .loc 1 351 5 view .LVU158 + 570 0030 A3B1 cbz r3, .L41 + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /*---------------------------- DMAx SxFCR Configuration ------------------------ + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters : + ARM GAS /tmp/ccMRPLCc.s page 46 + + + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * - FIFOMode: DMA_SxFCR_DMDIS bit + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** */ + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold); + 571 .loc 1 358 5 is_stmt 1 view .LVU159 + 572 0032 156B ldr r5, [r2, #48] + 573 .LVL41: + 574 .LBB50: + 575 .LBI50: +1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get the Channel number associated to the Stream. +1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CHSEL LL_DMA_GetChannelSelection +1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: +1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_0 +1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_1 +1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_2 +1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_3 +1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_4 +1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_5 +1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_6 +1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_7 +1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_8 (*) +1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_9 (*) +1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_10 (*) +1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_11 (*) +1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_12 (*) +1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_13 (*) +1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_14 (*) +1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CHANNEL_15 (*) +1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * +1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * (*) value not defined in all devices. +1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream) +1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Memory burst transfer configuration. +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer +1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 + ARM GAS /tmp/ccMRPLCc.s page 47 + + +1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Mburst This parameter can be one of the following values: +1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_SINGLE +1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC4 +1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC8 +1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC16 +1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) +1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D +1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Memory burst transfer configuration. +1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer +1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: +1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_SINGLE +1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC4 +1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC8 +1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_MBURST_INC16 +1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Peripheral burst transfer configuration. +1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer +1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Pburst This parameter can be one of the following values: +1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_SINGLE +1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC4 + ARM GAS /tmp/ccMRPLCc.s page 48 + + +1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC8 +1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC16 +1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) +1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D +1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get Peripheral burst transfer configuration. +1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer +1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: +1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_SINGLE +1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC4 +1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC8 +1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_PBURST_INC16 +1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. +1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CT LL_DMA_SetCurrentTargetMem +1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param CurrentMemory This parameter can be one of the following values: +1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM0 +1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM1 +1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Curren +1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, +1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** + ARM GAS /tmp/ccMRPLCc.s page 49 + + +1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. +1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR CT LL_DMA_GetCurrentTargetMem +1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: +1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM0 +1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_CURRENTTARGETMEM1 +1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) +1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable the double buffer mode. +1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode +1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA +1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable the double buffer mode. +1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode +1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) + ARM GAS /tmp/ccMRPLCc.s page 50 + + +1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, D +1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get FIFO status. +1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FS LL_DMA_GetFIFOStatus +1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: +1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_0_25 +1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_25_50 +1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_50_75 +1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_75_100 +1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_EMPTY +1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOSTATUS_FULL +1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) +1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Disable Fifo mode. +1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode +1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, +1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Enable Fifo mode. +1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode +1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 + ARM GAS /tmp/ccMRPLCc.s page 51 + + +1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DM +1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Select FIFO threshold. +1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold +1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Threshold This parameter can be one of the following values: +1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 +1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 +1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 +1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL +1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold +1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, +1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Get FIFO threshold. +1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold +1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval Returned value can be one of the following values: +1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 +1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 +1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 +1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ + ARM GAS /tmp/ccMRPLCc.s page 52 + + +1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))- +1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure the FIFO . +1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll FCR FTH LL_DMA_ConfigFifo\n +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * FCR DMDIS LL_DMA_ConfigFifo +1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param FifoMode This parameter can be one of the following values: +1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOMODE_ENABLE +1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOMODE_DISABLE +1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param FifoThreshold This parameter can be one of the following values: +1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 +1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 +1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 +1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL +1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint3 + 576 .loc 2 1397 22 view .LVU160 + 577 .LBB51: +1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, + 578 .loc 2 1399 3 view .LVU161 + 579 0034 DCF81440 ldr r4, [ip, #20] + 580 0038 24F00704 bic r4, r4, #7 + 581 003c 2B43 orrs r3, r3, r5 + 582 .LVL42: + 583 .loc 2 1399 3 is_stmt 0 view .LVU162 + 584 003e 2343 orrs r3, r3, r4 + 585 0040 CCF81430 str r3, [ip, #20] + 586 .LVL43: + 587 .loc 2 1399 3 view .LVU163 + 588 .LBE51: + 589 .LBE50: + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /*---------------------------- DMAx SxCR Configuration -------------------------- + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * Configure DMAx_Streamy: memory burst transfer with parameters : + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * - MemBurst: DMA_SxCR_MBURST[1:0] bits + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** */ + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst); + 590 .loc 1 364 5 is_stmt 1 view .LVU164 + 591 0044 536B ldr r3, [r2, #52] + 592 .LVL44: + 593 .LBB52: + 594 .LBI52: + ARM GAS /tmp/ccMRPLCc.s page 53 + + +1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 595 .loc 2 1095 22 view .LVU165 + 596 .LBB53: +1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 597 .loc 2 1097 3 view .LVU166 + 598 0046 4458 ldr r4, [r0, r1] + 599 0048 24F0C074 bic r4, r4, #25165824 + 600 004c 2343 orrs r3, r3, r4 + 601 .LVL45: +1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 602 .loc 2 1097 3 is_stmt 0 view .LVU167 + 603 004e 4350 str r3, [r0, r1] + 604 .LVL46: +1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 605 .loc 2 1097 3 view .LVU168 + 606 .LBE53: + 607 .LBE52: + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /*---------------------------- DMAx SxCR Configuration -------------------------- + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * Configure DMAx_Streamy: peripheral burst transfer with parameters : + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** */ + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst); + 608 .loc 1 370 5 is_stmt 1 view .LVU169 + 609 0050 936B ldr r3, [r2, #56] + 610 .LVL47: + 611 .LBB54: + 612 .LBI54: +1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 613 .loc 2 1144 22 view .LVU170 + 614 .LBB55: +1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 615 .loc 2 1146 3 view .LVU171 + 616 0052 4458 ldr r4, [r0, r1] + 617 0054 24F4C004 bic r4, r4, #6291456 + 618 0058 2343 orrs r3, r3, r4 + 619 .LVL48: +1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 620 .loc 2 1146 3 is_stmt 0 view .LVU172 + 621 005a 4350 str r3, [r0, r1] + 622 .LVL49: + 623 .L41: +1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 624 .loc 2 1146 3 view .LVU173 + 625 .LBE55: + 626 .LBE54: + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /*-------------------------- DMAx SxM0AR Configuration -------------------------- + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * Configure the memory or destination base address with parameter : + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** */ + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress); + 627 .loc 1 377 3 is_stmt 1 view .LVU174 + 628 005c 5368 ldr r3, [r2, #4] + 629 .LVL50: + 630 .LBB56: + ARM GAS /tmp/ccMRPLCc.s page 54 + + + 631 .LBI56: +1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Configure the Source and Destination addresses. +1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA stream is enabled. +1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n +1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * PAR PA LL_DMA_ConfigAddresses +1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param SrcAddress Between 0 to 0xFFFFFFFF +1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DstAddress Between 0 to 0xFFFFFFFF +1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Direction This parameter can be one of the following values: +1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY +1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH +1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY +1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress +1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Direction Memory to Periph */ +1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) +1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR +1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, +1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /* Direction Periph to Memory and Memory to Memory */ +1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** else +1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, +1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR +1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Memory address. +1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress +1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO +1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. +1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 + ARM GAS /tmp/ccMRPLCc.s page 55 + + +1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param MemoryAddress Between 0 to 0xFFFFFFFF +1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAdd + 632 .loc 2 1459 22 view .LVU175 + 633 .LBB57: +1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, + 634 .loc 2 1461 3 view .LVU176 + 635 005e CCF80C30 str r3, [ip, #12] + 636 .LVL51: + 637 .loc 2 1461 3 is_stmt 0 view .LVU177 + 638 .LBE57: + 639 .LBE56: + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /*-------------------------- DMAx SxPAR Configuration --------------------------- + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * Configure the peripheral or source base address with parameter : + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** */ + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress); + 640 .loc 1 383 3 is_stmt 1 view .LVU178 + 641 0062 1368 ldr r3, [r2] + 642 .LVL52: + 643 .LBB58: + 644 .LBI58: +1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } +1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** +1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** /** +1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @brief Set the Peripheral address. +1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @rmtoll PAR PA LL_DMA_SetPeriphAddress +1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMO +1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @note This API must not be called when the DMA channel is enabled. +1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param DMAx DMAx Instance +1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param Stream This parameter can be one of the following values: +1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_0 +1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_1 +1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_2 +1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_3 +1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_4 +1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_5 +1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_6 +1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @arg @ref LL_DMA_STREAM_7 +1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @param PeriphAddress Between 0 to 0xFFFFFFFF +1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** * @retval None +1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** */ +1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAdd + 645 .loc 2 1482 22 view .LVU179 + 646 .LBB59: +1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { +1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, P + 647 .loc 2 1484 3 view .LVU180 + 648 0064 CCF80830 str r3, [ip, #8] + 649 .LVL53: + 650 .loc 2 1484 3 is_stmt 0 view .LVU181 + 651 .LBE59: + 652 .LBE58: + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + ARM GAS /tmp/ccMRPLCc.s page 56 + + + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /*--------------------------- DMAx SxNDTR Configuration ------------------------- + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * Configure the peripheral base address with parameter : + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * - NbData: DMA_SxNDT[15:0] bits + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** */ + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData); + 653 .loc 1 389 3 is_stmt 1 view .LVU182 + 654 0068 136A ldr r3, [r2, #32] + 655 .LVL54: + 656 .LBB60: + 657 .LBI60: + 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 658 .loc 2 971 22 view .LVU183 + 659 .LBB61: + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 660 .loc 2 973 3 view .LVU184 + 661 006a DCF80440 ldr r4, [ip, #4] + 662 006e DFF828E0 ldr lr, .L43+8 + 663 0072 04EA0E0E and lr, r4, lr + 664 0076 43EA0E03 orr r3, r3, lr + 665 .LVL55: + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 666 .loc 2 973 3 is_stmt 0 view .LVU185 + 667 007a CCF80430 str r3, [ip, #4] + 668 .LVL56: + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 669 .loc 2 973 3 view .LVU186 + 670 .LBE61: + 671 .LBE60: + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /*--------------------------- DMA SxCR_CHSEL Configuration ---------------------- + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * Configure the peripheral base address with parameter : + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * - PeriphRequest: DMA_SxCR_CHSEL[3:0] bits + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** */ + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel); + 672 .loc 1 395 3 is_stmt 1 view .LVU187 + 673 007e 536A ldr r3, [r2, #36] + 674 .LVL57: + 675 .LBB62: + 676 .LBI62: +1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** { + 677 .loc 2 1032 22 view .LVU188 + 678 .LBB63: +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 679 .loc 2 1034 3 view .LVU189 + 680 0080 4258 ldr r2, [r0, r1] + 681 .LVL58: +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 682 .loc 2 1034 3 is_stmt 0 view .LVU190 + 683 0082 22F0F052 bic r2, r2, #503316480 + 684 0086 1343 orrs r3, r3, r2 + 685 .LVL59: +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 686 .loc 2 1034 3 view .LVU191 + 687 0088 4350 str r3, [r0, r1] + 688 .LVL60: +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h **** } + 689 .loc 2 1034 3 view .LVU192 + ARM GAS /tmp/ccMRPLCc.s page 57 + + + 690 .LBE63: + 691 .LBE62: + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** return SUCCESS; + 692 .loc 1 397 3 is_stmt 1 view .LVU193 + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 693 .loc 1 398 1 is_stmt 0 view .LVU194 + 694 008a 0020 movs r0, #0 + 695 .LVL61: + 696 .loc 1 398 1 view .LVU195 + 697 008c 30BD pop {r4, r5, pc} + 698 .L44: + 699 008e 00BF .align 2 + 700 .L43: + 701 0090 00000000 .word STREAM_OFFSET_TAB + 702 0094 1F80FCFF .word -229345 + 703 0098 0000FFFF .word -65536 + 704 .cfi_endproc + 705 .LFE321: + 707 .section .text.LL_DMA_StructInit,"ax",%progbits + 708 .align 1 + 709 .global LL_DMA_StructInit + 710 .syntax unified + 711 .thumb + 712 .thumb_func + 714 LL_DMA_StructInit: + 715 .LVL62: + 716 .LFB322: + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /** + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @brief Set each @ref LL_DMA_InitTypeDef field to default value. + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** * @retval None + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** */ + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** { + 717 .loc 1 406 1 is_stmt 1 view -0 + 718 .cfi_startproc + 719 @ args = 0, pretend = 0, frame = 0 + 720 @ frame_needed = 0, uses_anonymous_args = 0 + 721 @ link register save eliminated. + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** /* Set DMA_InitStruct fields to default values */ + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; + 722 .loc 1 408 3 view .LVU197 + 723 .loc 1 408 42 is_stmt 0 view .LVU198 + 724 0000 0023 movs r3, #0 + 725 0002 0360 str r3, [r0] + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; + 726 .loc 1 409 3 is_stmt 1 view .LVU199 + 727 .loc 1 409 42 is_stmt 0 view .LVU200 + 728 0004 4360 str r3, [r0, #4] + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; + 729 .loc 1 410 3 is_stmt 1 view .LVU201 + 730 .loc 1 410 42 is_stmt 0 view .LVU202 + 731 0006 8360 str r3, [r0, #8] + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; + 732 .loc 1 411 3 is_stmt 1 view .LVU203 + ARM GAS /tmp/ccMRPLCc.s page 58 + + + 733 .loc 1 411 42 is_stmt 0 view .LVU204 + 734 0008 C360 str r3, [r0, #12] + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; + 735 .loc 1 412 3 is_stmt 1 view .LVU205 + 736 .loc 1 412 42 is_stmt 0 view .LVU206 + 737 000a 0361 str r3, [r0, #16] + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; + 738 .loc 1 413 3 is_stmt 1 view .LVU207 + 739 .loc 1 413 42 is_stmt 0 view .LVU208 + 740 000c 4361 str r3, [r0, #20] + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; + 741 .loc 1 414 3 is_stmt 1 view .LVU209 + 742 .loc 1 414 42 is_stmt 0 view .LVU210 + 743 000e 8361 str r3, [r0, #24] + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; + 744 .loc 1 415 3 is_stmt 1 view .LVU211 + 745 .loc 1 415 42 is_stmt 0 view .LVU212 + 746 0010 C361 str r3, [r0, #28] + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->NbData = 0x00000000U; + 747 .loc 1 416 3 is_stmt 1 view .LVU213 + 748 .loc 1 416 42 is_stmt 0 view .LVU214 + 749 0012 0362 str r3, [r0, #32] + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->Channel = LL_DMA_CHANNEL_0; + 750 .loc 1 417 3 is_stmt 1 view .LVU215 + 751 .loc 1 417 42 is_stmt 0 view .LVU216 + 752 0014 4362 str r3, [r0, #36] + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; + 753 .loc 1 418 3 is_stmt 1 view .LVU217 + 754 .loc 1 418 42 is_stmt 0 view .LVU218 + 755 0016 8362 str r3, [r0, #40] + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE; + 756 .loc 1 419 3 is_stmt 1 view .LVU219 + 757 .loc 1 419 42 is_stmt 0 view .LVU220 + 758 0018 C362 str r3, [r0, #44] + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4; + 759 .loc 1 420 3 is_stmt 1 view .LVU221 + 760 .loc 1 420 42 is_stmt 0 view .LVU222 + 761 001a 0363 str r3, [r0, #48] + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE; + 762 .loc 1 421 3 is_stmt 1 view .LVU223 + 763 .loc 1 421 42 is_stmt 0 view .LVU224 + 764 001c 4363 str r3, [r0, #52] + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE; + 765 .loc 1 422 3 is_stmt 1 view .LVU225 + 766 .loc 1 422 42 is_stmt 0 view .LVU226 + 767 001e 8363 str r3, [r0, #56] + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c **** } + 768 .loc 1 423 1 view .LVU227 + 769 0020 7047 bx lr + 770 .cfi_endproc + 771 .LFE322: + 773 .section .rodata.STREAM_OFFSET_TAB,"a" + 774 .align 2 + 777 STREAM_OFFSET_TAB: + 778 0000 10284058 .ascii "\020(@Xp\210\240\270" + 778 7088A0B8 + 779 .text + ARM GAS /tmp/ccMRPLCc.s page 59 + + + 780 .Letext0: + 781 .file 4 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 782 .file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 783 .file 6 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + ARM GAS /tmp/ccMRPLCc.s page 60 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_ll_dma.c + /tmp/ccMRPLCc.s:20 .text.LL_DMA_DeInit:00000000 $t + /tmp/ccMRPLCc.s:26 .text.LL_DMA_DeInit:00000000 LL_DMA_DeInit + /tmp/ccMRPLCc.s:290 .text.LL_DMA_DeInit:0000011e $d + /tmp/ccMRPLCc.s:299 .text.LL_DMA_DeInit:00000126 $t + /tmp/ccMRPLCc.s:458 .text.LL_DMA_DeInit:000001b0 $d + /tmp/ccMRPLCc.s:777 .rodata.STREAM_OFFSET_TAB:00000000 STREAM_OFFSET_TAB + /tmp/ccMRPLCc.s:482 .text.LL_DMA_Init:00000000 $t + /tmp/ccMRPLCc.s:488 .text.LL_DMA_Init:00000000 LL_DMA_Init + /tmp/ccMRPLCc.s:701 .text.LL_DMA_Init:00000090 $d + /tmp/ccMRPLCc.s:708 .text.LL_DMA_StructInit:00000000 $t + /tmp/ccMRPLCc.s:714 .text.LL_DMA_StructInit:00000000 LL_DMA_StructInit + /tmp/ccMRPLCc.s:774 .rodata.STREAM_OFFSET_TAB:00000000 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32f7xx_ll_dma.o b/build/stm32f7xx_ll_dma.o new file mode 100644 index 0000000000000000000000000000000000000000..42d12258b88c193b56ac1c1104d4ac3f18b46163 GIT binary patch literal 14784 zcmchddw7)9oyX5R@62S#gpeB$Fv{ej;3bm_AgHKGCR_puq#4j?En$+Gkipz`GNFJX zDAEU6Z&h1u*Q(S@t5pl$ZEJBKtZNlDRou4f7K^L2cteYd+Lrx(&-*)*NnpGC>>qoc zocD8nm-9R4J@0wnoO$1~VQ%9*%d(V7mYSx9C8cK1)E3VSjcMw5Ritu1-FR;6P|l>99h(XPpbJFU{p6L2gEA8@&&L+y>*-*aad?p$)v%5FK3?Me(S zOj&z}mLG7rdWN>9G;yuz8hSpZiE2&9Q05d9vrTK34=qe-F4UR}hPG-=e&{?cFB_^` zbW5FYXU54bzjphhx{AyIBr*?Zz19v@|n>zaEE0r^?rnP^|9Z#Ipfunl>ZYbJr5e$?Jr|HKQ*$?{}S!njhv;j3aQv( z+2!Dvn>-)5#@vOF`gA^WrB3H=HgnL(ZvO_#9~;@18EQaxKQVHa|IcjpFGkMsN9lja z$OZmSX#dp6h5l10f9A^7*P*n?zmRA9xv>ZQxwIcPa+!ZId;Ntg_uG27r}?+h{-v>3 z`Y&evuZ%py|1ACgYUJ7e#q|H1X>X4IO4|Q!>^1%j_V;0|tSGKgb0FxE6Wy|<9 z`zO=xGV)UYDU4?uxz*oJyW5uYyU3r5DemzY`wD*zWv`K={%-nbnD)B-kFY(TvG-?& z!Wi!{Mo#)y(?8Srukn|$eZOP3OE+5n&ln)fD6X{pQ`zEJqu65k3vp|BvW?TD`tE|P0zYdDk$P<5q0WLy8AA+EDo@GA`kHRluxf_aY$b}z3*oVR&D7*#1k7map ztBE_tD5V!9Jk%pwot9^u7k>L;;nhC@x$t!evrw2$;YA3oD4a*(X$Y%PNFu9=ry=+} z6!f8);kqr)*BEXYEZ4y2Dppzm;XxGcr*Ia8-6%YdtR{YncrA>;!$rte!t&h62q(br zZTReErCbPZ&H>~?H-r)t0?2COIz(8Gf+I8@-#-O{$>DjmaL{7eaP(FlQq$l6@ z8Jv68*N#v2^egM3iF;v*BGhu^6CPpxhsW{xu?_Og$WwfHwE9?uhsi9w;yDZD!T=2K zz~gP?!h8r{qHq{lO*si&c#f_->|x=ljCR(U2?M9#SY#DoPie&v!R6_U&2%Y*aw^Ox z(nUvl3k4Ss?;~5k%DCS|Iu|Zyry|knDx}ME884ei=fk{=F2x-6OpKAGR}Tj~dcgZ& z>Os~6z8Qs06gc4DN8uJ^Ourd!tWEr`36{^ChKIkg<)o7ODH z_&NsC^}Gj0&fHR76o_Z>s+96-Kv+o6(m6Ol__|Z=YWh9QYP^S?Y7eJZdswP*ioj8- zox&i4tj0UdsW#}DIo#Tyr(U=Af#bML3%uP?tIKJ6DXxWUjT3;$~ z_j0GTUIux=Mm0VqooX-Gvxlp_V9(dp^uLl9>{h4RSGbO@IlPXX(@wQHt}}+K&2cTz z)p!fS@d90~Yz7C&!)i_yk1MSuk4v|NX_af8n4RypvyaPO=FPQQtQ<@pSDEtr&w&zi zWP-A@&-9<=Kf~XUj|bdIitx*jcK9i2&gGW@VE%bG2)~L4dPkZ<>NSvY(I&}AV z3`~d_$VzNA3@8E)YPniKEu-V(ZJGSqz7&o zCfoqX>ovLTKsk&0^mH`@OEnX8$y9%_KUF7xUirDYJ>8Av0J5dNMx@;m?D+%c@tUQ;zSN|0dgU75%M%|@rW+5asXMn#LBw&M|FvgdTpe* zAd!?>?xHbzA!K3SdgCE!(Ad>42-%h|ee_#|LC zvN1W%_y=zan!IiJ2!f=e%~-#mu?E$H5N^mXa})EzoXZ|ODj1nD-+It^<_^e+=`bj4X2 zPd;CrA$1#-K3fX6il!uGaefZ4*JffHlj)tA(ME5YwPHXn45o3dGZ% zY9QG&y}Fa#>F#ce_C$gm?Cnw7E)MqyZTsLrP_$9JM@1P^RXk2dJSZ?2sVa_$cWHQi z#?iF5Tb9Sp&mUjl@p>)1Vp}`MgBN4P0k_LD!G72UV}bX2w?*Yk>n%?Socu{o3Eur$ zb8xV)$HCKyLk7h$Ecsa)%hEWOa#_k}X*^34S(?;}!*MJf-^$RjpvQ;EncjNOSTNhp zoa3?4q6&B{Z@wqPYyWUVz-^;Tw>w?xM3%st-Hs#2sXJu9e!%4$F(TiwIXgV3=wYc47XQD{Dt1}u zOYMTXs>bHIi(6EEJQ3?i#`}6zQ>>>iv35zKsk*6tAXyuYCSn5vsu54WrrNepUvFo8 z<-B-jpK6XJ;{9F5UfWz()e>IXLPthzo8Qu0)i$p$(GhEj4aAZP%4#;$oQU@&;>op& z;ljy8EYj1qbZvjEKGvxQy805y0KfA{bKzJr)D`LNjdh1(-O|6hdVGZWhmT)8pDR+2 zvf(Esd)?HB2X1p?V?%W~G;cn7qfbJgENaz9l96zH9UjT(o9R?I9D*adKiwHA=~{h! zAky9)bIyPj)~J@b;khm6&8@FeY-(v22Cl2GJE{h8Mzh{{`m6AgBsDUzlU);_iQ*&EdmS8N~2NMJ7m(J;V9kpvZV~MmgWUay3A`g$LUQVu{X3N31OoiAE9?^JBfS zL?qdlXloADjdF&jZJ@6+`OQcoHfqdM7kIFDAilCU77cWCMG^{^K+nx|oio!1(Fkvf z;XzH+>BK82Rotf>|Z^zJX&=+#qPdHvK-69voRy1P(%_PU1wwAxO!Hsyyw);{$R8}P`(m> zQB3U4^6EhO5=fm<+)CvG&a-gY0~TI6|Ru0J*}h&Ca^g-V8648P6oH z?rW=Xh;RX{tf?q^X3Z^cQr@u{O=Db{zC3qpvGqf)xctv)`I zZnn7;PD}cG=LmV^uQMAf-hwnce?3iv%nxEta_s!AXJp#9r^);w#>5|Gmck47v}EJg z;mG)29sl~2k2h6f!A6vk{){@DY{X~#!)bJTnZqWO>=9Rh^4L-KaiiqiQ8M1*rX^dA zPm>sLWN&OWVU&H6y!~^2mE~c4&x8kuk8>pt<1TZ`O zncRsY>ATWAf2S-4mDk?@F6?+#-7{Kx{HD_kO6A^a!d z6~Y^Z-1x$JPYa(Fz9@V{_^$9TB(A%KAGxfTBb*`(3eOfc3coH~C0r}qBD`66kML39 zGs0JeZwn6!zaX=f`kOElUrgDrVquWPrx||VB~K^uaNvd%`ZbE&ELWNw`<+{4C5k?+XtKzYzXS=*105 zzf55PiMW%5#|wjEuNIyqxGvKw+gQn@*^kBi6Ydo567Cib3124>XRq*W;UTdf7Fzf?%=7UGvxRxWA`)?mg(nJ67yFsQkZ``R zS-4cVoJ5=s;Ywjr>}!OV3pWd|72Y7cgT%bNpTsrYE__7nzZCngMSfBEis;`H`6J;W z(H{}n#=i!RM;3|rxx(?n6UBbAuv&P!u!cmvxxxnF1!Dh(aHZ(GNj(2A75zrxR>;X}fI6}}{VL-;4*XF?B_9_$ZygppH(<-$3_2H|;fF%*gQZ???E-yV z4}jd=MV=(&E-uPv3AvGraU9qE9ixlpf{Q15DyZx!Al{E_e{!k-Iw3ZE4|FMM722jM$HZg6J*^!f_a>nqTW zOubKt9VA-Dt`AM@x6tJFTl&oso+Ydk&J%L89R0e4N#Ppd2BBVOp{&{wzb7k>Qd{==@@fvnpx@gSRc zDmbvVCmCr6lL?1iri2$hNfqSl85L~D8}uMvyacHXj{N0%lwSXa9pUM`2z2y`K86e) z{d-u)iN@LoSGL7_@qRw&lq2o!iP&nVbw|_P*O4wp@a}76O#0_|9Ife&_r^>_oS+JJ z^!4<_@CG!k)y_nu2TrvuO~FVqnTWR!CK2|3osNSiE{pzc&Pu%2=?RZwor-a!A1<9v zqy1=Onu^SM_CNV?ZjEmDun7Vi=PVQ70bseKYLJG4iO$8Uws zBonV5iu8ETq{ZX?Wa4pcksj|k#49nuK!`deaHOA+-$#M{G0C)hJrrrDrw+l7TMSJy zwyU8?@853pj{$kUSYD<2$8$4vP*kP3kNE%DBx8FJ3R9--njEDb;E75yw)-HDXtx~y z_i-<>UB1CGtaEY zvF(PO9&ZlfaZDMH?~zQreJGncD5_TwkIx*FjE%b-(&Oz$JU)LIFCW>&`w(T;G3U6a z$k}=gl}@xVe<3t}PnJ0Mf_4%c{k%AkCcOo}6-EHrE)zZ!j_BWiqJNCd{^68T{mX|R z?zMiXbgC)E`wJt0rY$mUdZ;A)4noQMAE%__<$xR$#7m_p<{zKCCYg8~^K`!gJP=Ba I5jIo&FQ$X}mH+?% literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_ll_exti.d b/build/stm32f7xx_ll_exti.d new file mode 100644 index 0000000..8ab207e --- /dev/null +++ b/build/stm32f7xx_ll_exti.d @@ -0,0 +1,70 @@ +build/stm32f7xx_ll_exti.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/build/stm32f7xx_ll_exti.lst b/build/stm32f7xx_ll_exti.lst new file mode 100644 index 0000000..5c65d3b --- /dev/null +++ b/build/stm32f7xx_ll_exti.lst @@ -0,0 +1,1533 @@ +ARM GAS /tmp/ccsXZQ1q.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_ll_exti.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c" + 19 .section .text.LL_EXTI_DeInit,"ax",%progbits + 20 .align 1 + 21 .global LL_EXTI_DeInit + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 LL_EXTI_DeInit: + 27 .LFB157: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * @file stm32f7xx_ll_exti.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * @brief EXTI LL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * This software is licensed under terms that can be found in the LICENSE file + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * in the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** */ + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #if defined(USE_FULL_LL_DRIVER) + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Includes ------------------------------------------------------------------*/ + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #include "stm32f7xx_ll_exti.h" + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #ifdef USE_FULL_ASSERT + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #include "stm32_assert.h" + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #else + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #define assert_param(expr) ((void)0U) + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #endif + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /** @addtogroup STM32F7xx_LL_Driver + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * @{ + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** */ + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** + ARM GAS /tmp/ccsXZQ1q.s page 2 + + + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #if defined (EXTI) + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /** @defgroup EXTI_LL EXTI + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * @{ + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** */ + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Private types -------------------------------------------------------------*/ + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Private variables ---------------------------------------------------------*/ + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Private constants ---------------------------------------------------------*/ + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Private macros ------------------------------------------------------------*/ + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /** @addtogroup EXTI_LL_Private_Macros + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * @{ + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** */ + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x0 + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** #define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLIN + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /** + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * @} + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** */ + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Private function prototypes -----------------------------------------------*/ + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Exported functions --------------------------------------------------------*/ + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /** @addtogroup EXTI_LL_Exported_Functions + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * @{ + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** */ + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /** @addtogroup EXTI_LL_EF_Init + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * @{ + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** */ + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /** + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * @brief De-initialize the EXTI registers to their default reset values. + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * @retval An ErrorStatus enumeration value: + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * - SUCCESS: EXTI registers are de-initialized + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * - ERROR: not applicable + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** */ + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** uint32_t LL_EXTI_DeInit(void) + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** { + 28 .loc 1 80 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Interrupt mask register set to default reset values */ + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_WriteReg(IMR, 0x00000000U); + 33 .loc 1 82 3 view .LVU1 + ARM GAS /tmp/ccsXZQ1q.s page 3 + + + 34 0000 054B ldr r3, .L2 + 35 0002 0020 movs r0, #0 + 36 0004 1860 str r0, [r3] + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Event mask register set to default reset values */ + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_WriteReg(EMR, 0x00000000U); + 37 .loc 1 84 3 view .LVU2 + 38 0006 5860 str r0, [r3, #4] + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Rising Trigger selection register set to default reset values */ + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_WriteReg(RTSR, 0x00000000U); + 39 .loc 1 86 3 view .LVU3 + 40 0008 9860 str r0, [r3, #8] + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Falling Trigger selection register set to default reset values */ + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_WriteReg(FTSR, 0x00000000U); + 41 .loc 1 88 3 view .LVU4 + 42 000a D860 str r0, [r3, #12] + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Software interrupt event register set to default reset values */ + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_WriteReg(SWIER, 0x00000000U); + 43 .loc 1 90 3 view .LVU5 + 44 000c 1861 str r0, [r3, #16] + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Pending register set to default reset values */ + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_WriteReg(PR, 0x01FFFFFFU); + 45 .loc 1 92 3 view .LVU6 + 46 000e 6FF07E42 mvn r2, #-33554432 + 47 0012 5A61 str r2, [r3, #20] + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** return SUCCESS; + 48 .loc 1 94 3 view .LVU7 + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** } + 49 .loc 1 95 1 is_stmt 0 view .LVU8 + 50 0014 7047 bx lr + 51 .L3: + 52 0016 00BF .align 2 + 53 .L2: + 54 0018 003C0140 .word 1073822720 + 55 .cfi_endproc + 56 .LFE157: + 58 .section .text.LL_EXTI_Init,"ax",%progbits + 59 .align 1 + 60 .global LL_EXTI_Init + 61 .syntax unified + 62 .thumb + 63 .thumb_func + 65 LL_EXTI_Init: + 66 .LVL0: + 67 .LFB158: + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /** + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * @retval An ErrorStatus enumeration value: + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * - SUCCESS: EXTI registers are initialized + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * - ERROR: not applicable + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** */ + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** { + 68 .loc 1 105 1 is_stmt 1 view -0 + 69 .cfi_startproc + ARM GAS /tmp/ccsXZQ1q.s page 4 + + + 70 @ args = 0, pretend = 0, frame = 0 + 71 @ frame_needed = 0, uses_anonymous_args = 0 + 72 @ link register save eliminated. + 73 .loc 1 105 1 is_stmt 0 view .LVU10 + 74 0000 10B4 push {r4} + 75 .LCFI0: + 76 .cfi_def_cfa_offset 4 + 77 .cfi_offset 4, -4 + 78 0002 0346 mov r3, r0 + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** ErrorStatus status = SUCCESS; + 79 .loc 1 106 3 is_stmt 1 view .LVU11 + 80 .LVL1: + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Check the parameters */ + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); + 81 .loc 1 108 3 view .LVU12 + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); + 82 .loc 1 109 3 view .LVU13 + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); + 83 .loc 1 110 3 view .LVU14 + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* ENABLE LineCommand */ + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** if (EXTI_InitStruct->LineCommand != DISABLE) + 84 .loc 1 113 3 view .LVU15 + 85 .loc 1 113 22 is_stmt 0 view .LVU16 + 86 0004 0079 ldrb r0, [r0, #4] @ zero_extendqisi2 + 87 .LVL2: + 88 .loc 1 113 6 view .LVU17 + 89 0006 0028 cmp r0, #0 + 90 0008 52D0 beq .L5 + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** { + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); + 91 .loc 1 115 5 is_stmt 1 view .LVU18 + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Configure EXTI Lines in range from 0 to 31 */ + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) + 92 .loc 1 118 5 view .LVU19 + 93 .loc 1 118 24 is_stmt 0 view .LVU20 + 94 000a 1A68 ldr r2, [r3] + 95 .loc 1 118 8 view .LVU21 + 96 000c 002A cmp r2, #0 + 97 000e 5DD0 beq .L12 + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** { + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** switch (EXTI_InitStruct->Mode) + 98 .loc 1 120 7 is_stmt 1 view .LVU22 + 99 .loc 1 120 30 is_stmt 0 view .LVU23 + 100 0010 5879 ldrb r0, [r3, #5] @ zero_extendqisi2 + 101 .loc 1 120 7 view .LVU24 + 102 0012 0128 cmp r0, #1 + 103 0014 20D0 beq .L7 + 104 0016 0228 cmp r0, #2 + 105 0018 29D0 beq .L8 + 106 001a 0028 cmp r0, #0 + 107 001c 31D1 bne .L13 + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** { + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** case LL_EXTI_MODE_IT: + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* First Disable Event on provided Lines */ + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + ARM GAS /tmp/ccsXZQ1q.s page 5 + + + 108 .loc 1 124 11 is_stmt 1 view .LVU25 + 109 .LVL3: + 110 .LBB30: + 111 .LBI30: + 112 .file 2 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @file stm32f7xx_ll_exti.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @brief Header file of EXTI LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * This software is licensed under terms that can be found in the LICENSE file + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * in the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #ifndef __STM32F7xx_LL_EXTI_H + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define __STM32F7xx_LL_EXTI_H + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #ifdef __cplusplus + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** extern "C" { + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Includes ------------------------------------------------------------------*/ + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #include "stm32f7xx.h" + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @addtogroup STM32F7xx_LL_Driver + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @{ + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined (EXTI) + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL EXTI + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @{ + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Private types -------------------------------------------------------------*/ + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Private variables ---------------------------------------------------------*/ + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Private constants ---------------------------------------------------------*/ + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Private Macros ------------------------------------------------------------*/ + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(USE_FULL_LL_DRIVER) + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @{ + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @} + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif /*USE_FULL_LL_DRIVER*/ + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Exported types ------------------------------------------------------------*/ + ARM GAS /tmp/ccsXZQ1q.s page 6 + + + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(USE_FULL_LL_DRIVER) + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @{ + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** typedef struct + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines i + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** This parameter can be any combination of @ref EXTI_LL_EC_LINE + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** This parameter can be set either to ENABLE or DISABLE */ + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } LL_EXTI_InitTypeDef; + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @} + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif /*USE_FULL_LL_DRIVER*/ + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Exported constants --------------------------------------------------------*/ + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @{ + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_EC_LINE LINE + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @{ + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM16) + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM18) + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ + ARM GAS /tmp/ccsXZQ1q.s page 7 + + + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM20) + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM21) + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM22) + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM24) + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM25) + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM26) + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM27) + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM28) + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM29) + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM30) + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(EXTI_IMR_IM31) + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(USE_FULL_LL_DRIVER) + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif /*USE_FULL_LL_DRIVER*/ + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @} + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #if defined(USE_FULL_LL_DRIVER) + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_EC_MODE Mode + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @{ + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @} + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + ARM GAS /tmp/ccsXZQ1q.s page 8 + + + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @{ + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @} + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #endif /*USE_FULL_LL_DRIVER*/ + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @} + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Exported macro ------------------------------------------------------------*/ + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @{ + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @{ + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @brief Write a value in EXTI register + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @param __REG__ Register to be written + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @param __VALUE__ Value to be written in the register + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @retval None + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @brief Read a value in EXTI register + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @param __REG__ Register to be read + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @retval Register value + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** #define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @} + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @} + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /* Exported functions --------------------------------------------------------*/ + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + ARM GAS /tmp/ccsXZQ1q.s page 9 + + + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @{ + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_EF_IT_Management IT_Management + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @{ + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note The reset value for the direct or internal lines (see RM) + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * is set to 1 in order to enable the interrupt by default. + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * Bits are set automatically at Power on. + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @param ExtiLine This parameter can be one of the following values: + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_17 + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_23 + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_24(*) + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_ALL_0_31 + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note (*): Available in some devices + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @retval None + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** SET_BIT(EXTI->IMR, ExtiLine); + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note The reset value for the direct or internal lines (see RM) + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * is set to 1 in order to enable the interrupt by default. + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * Bits are set automatically at Power on. + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @param ExtiLine This parameter can be one of the following values: + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + ARM GAS /tmp/ccsXZQ1q.s page 10 + + + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_17 + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_23 + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_24(*) + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_ALL_0_31 + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note (*): Available in some devices + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @retval None + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** CLEAR_BIT(EXTI->IMR, ExtiLine); + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note The reset value for the direct or internal lines (see RM) + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * is set to 1 in order to enable the interrupt by default. + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * Bits are set automatically at Power on. + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @param ExtiLine This parameter can be one of the following values: + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + ARM GAS /tmp/ccsXZQ1q.s page 11 + + + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_17 + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_23 + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_24(*) + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_ALL_0_31 + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note (*): Available in some devices + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @retval State of bit (1 or 0). + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @} + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_EF_Event_Management Event_Management + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @{ + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @param ExtiLine This parameter can be one of the following values: + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_17 + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_23 + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_24(*) + ARM GAS /tmp/ccsXZQ1q.s page 12 + + + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_ALL_0_31 + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note (*): Available in some devices + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @retval None + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** SET_BIT(EXTI->EMR, ExtiLine); + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @param ExtiLine This parameter can be one of the following values: + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_17 + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_23 + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_24(*) + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_ALL_0_31 + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note (*): Available in some devices + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @retval None + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) + 113 .loc 2 441 22 view .LVU26 + 114 .LBB31: + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** CLEAR_BIT(EXTI->EMR, ExtiLine); + 115 .loc 2 443 3 view .LVU27 + 116 001e 2D49 ldr r1, .L16 + 117 0020 4C68 ldr r4, [r1, #4] + 118 0022 24EA0202 bic r2, r4, r2 + 119 .LVL4: + 120 .loc 2 443 3 is_stmt 0 view .LVU28 + ARM GAS /tmp/ccsXZQ1q.s page 13 + + + 121 0026 4A60 str r2, [r1, #4] + 122 .LVL5: + 123 .loc 2 443 3 view .LVU29 + 124 .LBE31: + 125 .LBE30: + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Then Enable IT on provided Lines */ + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + 126 .loc 1 126 11 is_stmt 1 view .LVU30 + 127 0028 1A68 ldr r2, [r3] + 128 .LVL6: + 129 .LBB32: + 130 .LBI32: + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 131 .loc 2 267 22 view .LVU31 + 132 .LBB33: + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 133 .loc 2 269 3 view .LVU32 + 134 002a 0C68 ldr r4, [r1] + 135 002c 2243 orrs r2, r2, r4 + 136 .LVL7: + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 137 .loc 2 269 3 is_stmt 0 view .LVU33 + 138 002e 0A60 str r2, [r1] + 139 .LVL8: + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 140 .loc 2 269 3 view .LVU34 + 141 .LBE33: + 142 .LBE32: + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** break; + 143 .loc 1 127 11 is_stmt 1 view .LVU35 + 144 .L9: + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** case LL_EXTI_MODE_EVENT: + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* First Disable IT on provided Lines */ + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Then Enable Event on provided Lines */ + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** break; + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** case LL_EXTI_MODE_IT_EVENT: + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Directly Enable IT & Event on provided Lines */ + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** break; + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** default: + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** status = ERROR; + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** break; + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** } + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) + 145 .loc 1 143 7 view .LVU36 + 146 .loc 1 143 26 is_stmt 0 view .LVU37 + 147 0030 9A79 ldrb r2, [r3, #6] @ zero_extendqisi2 + 148 .loc 1 143 10 view .LVU38 + 149 0032 002A cmp r2, #0 + 150 0034 47D0 beq .L6 + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** { + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** switch (EXTI_InitStruct->Trigger) + 151 .loc 1 145 9 is_stmt 1 view .LVU39 + 152 0036 022A cmp r2, #2 + ARM GAS /tmp/ccsXZQ1q.s page 14 + + + 153 0038 25D0 beq .L10 + 154 003a 032A cmp r2, #3 + 155 003c 2ED0 beq .L11 + 156 003e 012A cmp r2, #1 + 157 0040 46D1 bne .L14 + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** { + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** case LL_EXTI_TRIGGER_RISING: + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* First Disable Falling Trigger on provided Lines */ + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + 158 .loc 1 149 13 view .LVU40 + 159 0042 1C68 ldr r4, [r3] + 160 .LVL9: + 161 .LBB34: + 162 .LBI34: + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @param ExtiLine This parameter can be one of the following values: + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_17 + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_23 + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_24(*) + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_ALL_0_31 + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note (*): Available in some devices + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @retval State of bit (1 or 0). + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + ARM GAS /tmp/ccsXZQ1q.s page 15 + + + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @} + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @{ + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note The configurable wakeup lines are edge-triggered. No glitch must be + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * generated on these lines. If a rising edge on a configurable interrupt + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * line occurs during a write operation in the EXTI_RTSR register, the + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * pending bit is not set. + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * Rising and falling edge triggers can be set for + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * the same interrupt line. In this case, both generate a trigger + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * condition. + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @param ExtiLine This parameter can be a combination of the following values: + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @retval None + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** SET_BIT(EXTI->RTSR, ExtiLine); + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note The configurable wakeup lines are edge-triggered. No glitch must be + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * generated on these lines. If a rising edge on a configurable interrupt + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * line occurs during a write operation in the EXTI_RTSR register, the + ARM GAS /tmp/ccsXZQ1q.s page 16 + + + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * pending bit is not set. + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * Rising and falling edge triggers can be set for + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * the same interrupt line. In this case, both generate a trigger + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * condition. + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @param ExtiLine This parameter can be a combination of the following values: + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @retval None + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** CLEAR_BIT(EXTI->RTSR, ExtiLine); + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @param ExtiLine This parameter can be a combination of the following values: + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + ARM GAS /tmp/ccsXZQ1q.s page 17 + + + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @retval State of bit (1 or 0). + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @} + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @{ + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note The configurable wakeup lines are edge-triggered. No glitch must be + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * generated on these lines. If a falling edge on a configurable interrupt + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * line occurs during a write operation in the EXTI_FTSR register, the + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * pending bit is not set. + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * Rising and falling edge triggers can be set for + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * the same interrupt line. In this case, both generate a trigger + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * condition. + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @param ExtiLine This parameter can be a combination of the following values: + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + ARM GAS /tmp/ccsXZQ1q.s page 18 + + + 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @retval None + 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) + 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** SET_BIT(EXTI->FTSR, ExtiLine); + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** /** + 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note The configurable wakeup lines are edge-triggered. No glitch must be + 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * generated on these lines. If a Falling edge on a configurable interrupt + 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * line occurs during a write operation in the EXTI_FTSR register, the + 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * pending bit is not set. + 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * Rising and falling edge triggers can be set for the same interrupt line. + 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * In this case, both generate a trigger condition. + 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 + 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @param ExtiLine This parameter can be a combination of the following values: + 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_0 + 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_1 + 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_2 + 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_3 + 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_4 + 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_5 + 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_6 + 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_7 + 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_8 + 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_9 + 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_10 + 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_11 + 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_12 + 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_13 + 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_14 + 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_15 + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_16 + 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_18 + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_19 + 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_20 + 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_21 + 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @arg @ref LL_EXTI_LINE_22 + 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @note Please check each device line mapping for EXTI Line availability + 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** * @retval None + 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** */ + 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) + 163 .loc 2 702 22 view .LVU41 + 164 .LBB35: + 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** CLEAR_BIT(EXTI->FTSR, ExtiLine); + 165 .loc 2 704 3 view .LVU42 + 166 0044 234A ldr r2, .L16 + 167 0046 D168 ldr r1, [r2, #12] + 168 0048 21EA0401 bic r1, r1, r4 + 169 004c D160 str r1, [r2, #12] + 170 .LVL10: + 171 .loc 2 704 3 is_stmt 0 view .LVU43 + 172 .LBE35: + ARM GAS /tmp/ccsXZQ1q.s page 19 + + + 173 .LBE34: + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Then Enable Rising Trigger on provided Lines */ + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + 174 .loc 1 151 13 is_stmt 1 view .LVU44 + 175 004e 1B68 ldr r3, [r3] + 176 .LVL11: + 177 .LBB36: + 178 .LBI36: + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 179 .loc 2 532 22 view .LVU45 + 180 .LBB37: + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 181 .loc 2 534 3 view .LVU46 + 182 0050 9168 ldr r1, [r2, #8] + 183 0052 0B43 orrs r3, r3, r1 + 184 .LVL12: + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 185 .loc 2 534 3 is_stmt 0 view .LVU47 + 186 0054 9360 str r3, [r2, #8] + 187 .LVL13: + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 188 .loc 2 534 3 view .LVU48 + 189 .LBE37: + 190 .LBE36: + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** break; + 191 .loc 1 152 13 is_stmt 1 view .LVU49 + 192 .LBB39: + 193 .LBB38: + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 194 .loc 2 536 1 is_stmt 0 view .LVU50 + 195 0056 36E0 b .L6 + 196 .LVL14: + 197 .L7: + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 198 .loc 2 536 1 view .LVU51 + 199 .LBE38: + 200 .LBE39: + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Then Enable Event on provided Lines */ + 201 .loc 1 130 11 is_stmt 1 view .LVU52 + 202 .LBB40: + 203 .LBI40: + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 204 .loc 2 309 22 view .LVU53 + 205 .LBB41: + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 206 .loc 2 311 3 view .LVU54 + 207 0058 1E49 ldr r1, .L16 + 208 005a 0868 ldr r0, [r1] + 209 005c 20EA0202 bic r2, r0, r2 + 210 .LVL15: + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 211 .loc 2 311 3 is_stmt 0 view .LVU55 + 212 0060 0A60 str r2, [r1] + 213 .LVL16: + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 214 .loc 2 311 3 view .LVU56 + 215 .LBE41: + ARM GAS /tmp/ccsXZQ1q.s page 20 + + + 216 .LBE40: + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** break; + 217 .loc 1 132 11 is_stmt 1 view .LVU57 + 218 0062 1A68 ldr r2, [r3] + 219 .LVL17: + 220 .LBB42: + 221 .LBI42: + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 222 .loc 2 400 22 view .LVU58 + 223 .LBB43: + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 224 .loc 2 402 3 view .LVU59 + 225 0064 4868 ldr r0, [r1, #4] + 226 0066 0243 orrs r2, r2, r0 + 227 .LVL18: + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 228 .loc 2 402 3 is_stmt 0 view .LVU60 + 229 0068 4A60 str r2, [r1, #4] + 230 .LVL19: + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 231 .loc 2 402 3 view .LVU61 + 232 .LBE43: + 233 .LBE42: + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** case LL_EXTI_MODE_IT_EVENT: + 234 .loc 1 133 11 is_stmt 1 view .LVU62 + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Check the parameters */ + 235 .loc 1 106 15 is_stmt 0 view .LVU63 + 236 006a 0020 movs r0, #0 + 237 .LBB45: + 238 .LBB44: + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 239 .loc 2 404 1 view .LVU64 + 240 006c E0E7 b .L9 + 241 .L8: + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 242 .loc 2 404 1 view .LVU65 + 243 .LBE44: + 244 .LBE45: + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + 245 .loc 1 136 11 is_stmt 1 view .LVU66 + 246 .LVL20: + 247 .LBB46: + 248 .LBI46: + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 249 .loc 2 267 22 view .LVU67 + 250 .LBB47: + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 251 .loc 2 269 3 view .LVU68 + 252 006e 1949 ldr r1, .L16 + 253 0070 0868 ldr r0, [r1] + 254 0072 0243 orrs r2, r2, r0 + 255 .LVL21: + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 256 .loc 2 269 3 is_stmt 0 view .LVU69 + 257 0074 0A60 str r2, [r1] + 258 .LVL22: + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + ARM GAS /tmp/ccsXZQ1q.s page 21 + + + 259 .loc 2 269 3 view .LVU70 + 260 .LBE47: + 261 .LBE46: + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** break; + 262 .loc 1 137 11 is_stmt 1 view .LVU71 + 263 0076 1A68 ldr r2, [r3] + 264 .LVL23: + 265 .LBB48: + 266 .LBI48: + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 267 .loc 2 400 22 view .LVU72 + 268 .LBB49: + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 269 .loc 2 402 3 view .LVU73 + 270 0078 4868 ldr r0, [r1, #4] + 271 007a 0243 orrs r2, r2, r0 + 272 .LVL24: + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 273 .loc 2 402 3 is_stmt 0 view .LVU74 + 274 007c 4A60 str r2, [r1, #4] + 275 .LVL25: + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 276 .loc 2 402 3 view .LVU75 + 277 .LBE49: + 278 .LBE48: + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** default: + 279 .loc 1 138 11 is_stmt 1 view .LVU76 + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Check the parameters */ + 280 .loc 1 106 15 is_stmt 0 view .LVU77 + 281 007e 0020 movs r0, #0 + 282 .LBB51: + 283 .LBB50: + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 284 .loc 2 404 1 view .LVU78 + 285 0080 D6E7 b .L9 + 286 .L13: + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 287 .loc 2 404 1 view .LVU79 + 288 .LBE50: + 289 .LBE51: + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** { + 290 .loc 1 120 7 view .LVU80 + 291 0082 0120 movs r0, #1 + 292 0084 D4E7 b .L9 + 293 .LVL26: + 294 .L10: + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** case LL_EXTI_TRIGGER_FALLING: + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* First Disable Rising Trigger on provided Lines */ + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + 295 .loc 1 155 13 is_stmt 1 view .LVU81 + 296 0086 1C68 ldr r4, [r3] + 297 .LVL27: + 298 .LBB52: + 299 .LBI52: + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 300 .loc 2 575 22 view .LVU82 + 301 .LBB53: + ARM GAS /tmp/ccsXZQ1q.s page 22 + + + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 302 .loc 2 577 3 view .LVU83 + 303 0088 124A ldr r2, .L16 + 304 008a 9168 ldr r1, [r2, #8] + 305 008c 21EA0401 bic r1, r1, r4 + 306 0090 9160 str r1, [r2, #8] + 307 .LVL28: + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 308 .loc 2 577 3 is_stmt 0 view .LVU84 + 309 .LBE53: + 310 .LBE52: + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Then Enable Falling Trigger on provided Lines */ + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + 311 .loc 1 157 13 is_stmt 1 view .LVU85 + 312 0092 1B68 ldr r3, [r3] + 313 .LVL29: + 314 .LBB54: + 315 .LBI54: + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 316 .loc 2 661 22 view .LVU86 + 317 .LBB55: + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 318 .loc 2 663 3 view .LVU87 + 319 0094 D168 ldr r1, [r2, #12] + 320 0096 0B43 orrs r3, r3, r1 + 321 .LVL30: + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 322 .loc 2 663 3 is_stmt 0 view .LVU88 + 323 0098 D360 str r3, [r2, #12] + 324 .LVL31: + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 325 .loc 2 663 3 view .LVU89 + 326 .LBE55: + 327 .LBE54: + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** break; + 328 .loc 1 158 13 is_stmt 1 view .LVU90 + 329 .LBB57: + 330 .LBB56: + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 331 .loc 2 664 1 is_stmt 0 view .LVU91 + 332 009a 14E0 b .L6 + 333 .LVL32: + 334 .L11: + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 335 .loc 2 664 1 view .LVU92 + 336 .LBE56: + 337 .LBE57: + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** case LL_EXTI_TRIGGER_RISING_FALLING: + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + 338 .loc 1 160 13 is_stmt 1 view .LVU93 + 339 009c 1968 ldr r1, [r3] + 340 .LVL33: + 341 .LBB58: + 342 .LBI58: + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 343 .loc 2 532 22 view .LVU94 + 344 .LBB59: + ARM GAS /tmp/ccsXZQ1q.s page 23 + + + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 345 .loc 2 534 3 view .LVU95 + 346 009e 0D4A ldr r2, .L16 + 347 00a0 9468 ldr r4, [r2, #8] + 348 00a2 2143 orrs r1, r1, r4 + 349 .LVL34: + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 350 .loc 2 534 3 is_stmt 0 view .LVU96 + 351 00a4 9160 str r1, [r2, #8] + 352 .LVL35: + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 353 .loc 2 534 3 view .LVU97 + 354 .LBE59: + 355 .LBE58: + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + 356 .loc 1 161 13 is_stmt 1 view .LVU98 + 357 00a6 1B68 ldr r3, [r3] + 358 .LVL36: + 359 .LBB60: + 360 .LBI60: + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 361 .loc 2 661 22 view .LVU99 + 362 .LBB61: + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 363 .loc 2 663 3 view .LVU100 + 364 00a8 D168 ldr r1, [r2, #12] + 365 00aa 0B43 orrs r3, r3, r1 + 366 .LVL37: + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 367 .loc 2 663 3 is_stmt 0 view .LVU101 + 368 00ac D360 str r3, [r2, #12] + 369 .LVL38: + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 370 .loc 2 663 3 view .LVU102 + 371 .LBE61: + 372 .LBE60: + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** break; + 373 .loc 1 162 13 is_stmt 1 view .LVU103 + 374 .LBB63: + 375 .LBB62: + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 376 .loc 2 664 1 is_stmt 0 view .LVU104 + 377 00ae 0AE0 b .L6 + 378 .LVL39: + 379 .L5: + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** + 380 .loc 2 664 1 view .LVU105 + 381 .LBE62: + 382 .LBE63: + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** default: + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** status = ERROR; + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** break; + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** } + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** } + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** } + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** } + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* DISABLE LineCommand */ + ARM GAS /tmp/ccsXZQ1q.s page 24 + + + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** else + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** { + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* De-configure EXTI Lines in range from 0 to 31 */ + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + 383 .loc 1 174 5 is_stmt 1 view .LVU106 + 384 .LBB64: + 385 .LBI64: + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 386 .loc 2 309 22 view .LVU107 + 387 .LBB65: + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 388 .loc 2 311 3 view .LVU108 + 389 00b0 084A ldr r2, .L16 + 390 00b2 1168 ldr r1, [r2] + 391 00b4 1C68 ldr r4, [r3] + 392 00b6 21EA0401 bic r1, r1, r4 + 393 00ba 1160 str r1, [r2] + 394 .LVL40: + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 395 .loc 2 311 3 is_stmt 0 view .LVU109 + 396 .LBE65: + 397 .LBE64: + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + 398 .loc 1 175 5 is_stmt 1 view .LVU110 + 399 00bc 1968 ldr r1, [r3] + 400 .LVL41: + 401 .LBB66: + 402 .LBI66: + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** { + 403 .loc 2 441 22 view .LVU111 + 404 .LBB67: + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 405 .loc 2 443 3 view .LVU112 + 406 00be 5368 ldr r3, [r2, #4] + 407 .LVL42: + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 408 .loc 2 443 3 is_stmt 0 view .LVU113 + 409 00c0 23EA0103 bic r3, r3, r1 + 410 00c4 5360 str r3, [r2, #4] + 411 .LVL43: + 412 .L6: + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h **** } + 413 .loc 2 443 3 view .LVU114 + 414 .LBE67: + 415 .LBE66: + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** } + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** return status; + 416 .loc 1 177 3 is_stmt 1 view .LVU115 + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** } + 417 .loc 1 178 1 is_stmt 0 view .LVU116 + 418 00c6 5DF8044B ldr r4, [sp], #4 + 419 .LCFI1: + 420 .cfi_remember_state + 421 .cfi_restore 4 + 422 .cfi_def_cfa_offset 0 + 423 00ca 7047 bx lr + 424 .LVL44: + ARM GAS /tmp/ccsXZQ1q.s page 25 + + + 425 .L12: + 426 .LCFI2: + 427 .cfi_restore_state + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /* Check the parameters */ + 428 .loc 1 106 15 view .LVU117 + 429 00cc 0020 movs r0, #0 + 430 00ce FAE7 b .L6 + 431 .LVL45: + 432 .L14: + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** { + 433 .loc 1 145 9 view .LVU118 + 434 00d0 0120 movs r0, #1 + 435 .LVL46: + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** { + 436 .loc 1 145 9 view .LVU119 + 437 00d2 F8E7 b .L6 + 438 .L17: + 439 .align 2 + 440 .L16: + 441 00d4 003C0140 .word 1073822720 + 442 .cfi_endproc + 443 .LFE158: + 445 .section .text.LL_EXTI_StructInit,"ax",%progbits + 446 .align 1 + 447 .global LL_EXTI_StructInit + 448 .syntax unified + 449 .thumb + 450 .thumb_func + 452 LL_EXTI_StructInit: + 453 .LVL47: + 454 .LFB159: + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** /** + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** * @retval None + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** */ + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** { + 455 .loc 1 186 1 is_stmt 1 view -0 + 456 .cfi_startproc + 457 @ args = 0, pretend = 0, frame = 0 + 458 @ frame_needed = 0, uses_anonymous_args = 0 + 459 @ link register save eliminated. + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; + 460 .loc 1 187 3 view .LVU121 + 461 .loc 1 187 35 is_stmt 0 view .LVU122 + 462 0000 0023 movs r3, #0 + 463 0002 0360 str r3, [r0] + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** EXTI_InitStruct->LineCommand = DISABLE; + 464 .loc 1 188 3 is_stmt 1 view .LVU123 + 465 .loc 1 188 35 is_stmt 0 view .LVU124 + 466 0004 0371 strb r3, [r0, #4] + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; + 467 .loc 1 189 3 is_stmt 1 view .LVU125 + 468 .loc 1 189 35 is_stmt 0 view .LVU126 + 469 0006 4371 strb r3, [r0, #5] + ARM GAS /tmp/ccsXZQ1q.s page 26 + + + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; + 470 .loc 1 190 3 is_stmt 1 view .LVU127 + 471 .loc 1 190 35 is_stmt 0 view .LVU128 + 472 0008 0223 movs r3, #2 + 473 000a 8371 strb r3, [r0, #6] + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c **** } + 474 .loc 1 191 1 view .LVU129 + 475 000c 7047 bx lr + 476 .cfi_endproc + 477 .LFE159: + 479 .text + 480 .Letext0: + 481 .file 3 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 482 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 483 .file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + ARM GAS /tmp/ccsXZQ1q.s page 27 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_ll_exti.c + /tmp/ccsXZQ1q.s:20 .text.LL_EXTI_DeInit:00000000 $t + /tmp/ccsXZQ1q.s:26 .text.LL_EXTI_DeInit:00000000 LL_EXTI_DeInit + /tmp/ccsXZQ1q.s:54 .text.LL_EXTI_DeInit:00000018 $d + /tmp/ccsXZQ1q.s:59 .text.LL_EXTI_Init:00000000 $t + /tmp/ccsXZQ1q.s:65 .text.LL_EXTI_Init:00000000 LL_EXTI_Init + /tmp/ccsXZQ1q.s:441 .text.LL_EXTI_Init:000000d4 $d + /tmp/ccsXZQ1q.s:446 .text.LL_EXTI_StructInit:00000000 $t + /tmp/ccsXZQ1q.s:452 .text.LL_EXTI_StructInit:00000000 LL_EXTI_StructInit + +NO UNDEFINED SYMBOLS diff --git a/build/stm32f7xx_ll_exti.o b/build/stm32f7xx_ll_exti.o new file mode 100644 index 0000000000000000000000000000000000000000..35fedecf04df63cc4e15bbc0cf893121449c8f72 GIT binary patch literal 8940 zcma)>3vg7|dB@MWckgP^YK2~439!3ZV1#U~B;GhY3_=KDfn`a=)J~#Ztyb((X$8A0 zDpJ7MAvLW@!HJ0-$FZsFdPwRxN#jnSV<(!gO<*uZA@+ABu)SS zbH6LyT^OflbnfqbkMo_!J@?$RSNC`JY}Q&UFKN}JrX{7`y2)6aWd==Zj%rZOohn)% z-x+^Aej#3;82_(B8}Ci*=~CZNYxEseFWQ^ce$~`>ZcbV?fB4+a{kkc7&T3kGPBpck zZ|UwyFSu-3TjO)m73rHh%HvP$SIu4LtmcL1?B>`x-MsnyymaH%^Xd7Q1NwY?Zu*gQ zxZ_jt6&G*n4yB{0S&o`p(pJaTxQbr9)Bvr8DAT$(F6rp^FU?EWY<G^E;+>hyu$*5Rr8ARK$aw;i zo#G`{KZwef4n2UIU|D5<1K4fwvX?a+f+a9UbD-=mpmzdJCR=kO^i9x)ui&D>AH`KGdnw@jrELSA+vjyBr0{WERQOR06>g8w?RmQyutI@) zG+q(1R?m0}awNtHT2o<$+o&R|VYJrQvMH-E5OFAO4EH0L)#yY3Wp#=eRQ6$3?y`5n zyHby_v9m#xA<^-m(yv3Bxf>UKHpa5 zkanVA@iK(09}NG9ZWbE+F9QBfBQW!ht2$1=Q*`0wIb?k*@-p2x2`|9q3saF!(=ASyKaX7WBAti% zyCxFn>C3QMyu3uW7o0Na%sl-PF7MLq2HxhcqhKzt(d|o)xy5|2BgmLRodWe;(<^Eo zv|NM@TQS$x*R9#w=Gf+RA|%B1X5}@QXZR$IoFCVC(pu*lzr&jAY2=Vy<9g5duZ&Yi zBfIAs>#VhI%}#X2I;&yiopFt4^=j7`XU|U1$nm?z6MB_v)C{|vMy^`dxLmI=#<}%0 zhG}#SVZGcKl&;nbD{I4c<=o00!D`*7tAg-cpu*vGP-0)3t?bI%!ygE*4tLjLcUi6o zM;t;}akV-ehJ&*@tYImOC_Che-LU*quOgN*Jt*W&yL`<#|=~3 z>6%!FG36hN^opZVsv)MmIb2i`HO^uqU6U8=UOSL^svOnlG@yDVj*$~vkYoaFE0Mx`eQIr4Vs&O@mJ1}1x zw;*fPM>HW@Dv#@QYDO`J3>Tsex!7eBG~12C0IpN17bPk%O5%gaGp1)4l1aR^990|{ zEf7P<#VxomiL~oN>@IO(lq_-q8BqwnDoUeFLU+J*Ar4*Raugc#W-vX6;HF1`$B{7< z;tAyI3TcpWrJ`LzEm#X+CQ*u>5|PWCnpEDZ0H$uwXOZR zqe$xb z-QT(?wJ(!Qq2cMaTM^HAs(fK=>5>t4XLNKhHCf2SlI-ra>NIaqzA%h)bS#ZQdM+za z7mC1?!V{IFm1AzI{XL}}yKddhNb4LOthEA|nQ8OCDIJ7Eu(htXc9t_67H=qS}OQUBr)D%n-qnSU1Z~l>6|2NijeW)KaVRg_xY-$y9O;@0PSbBJ+IKabRfOp&gPSF0e1bE0D%Lrx^ z+N&~@KXt=K*96e&JLoa)KYq-exqpo_!(J4N;=Jr%3uhUm)@j83!h#UaFQRU>H0liG zGP`!Aa;h~wK9*`7New4jw{`apwDu*2GvmGK@xpjElN{`y7|N$|BZ*{cFqarkYzLnO=(re&5Pe%h;_Wdt$?TqAk1dH;j&sv@D6X z+y!Z5I8jKn9ZGR`w=~aV;skYo1;9N|pD0uzr?CZO$&lihBe&2l^8-MGydu?(mxV!jD=fs^w z2H!T0?S3<7!}OghQy3nfz@1e78^ob3UBaHzE$3TPj{zpj#Jl+ zS*fm$j@zS6?aOaBOFfqwZEsn!xOCm)rvu)AzeUo@I#5{=F|zkU<;&E2p;C7Nc|&F3 zh_;5yzg4L=;Fm{{KMw&L+Hpzny{Ggd6rGiwE!$KuQnqb|RUWDd)ahCJ2D@H2=s9{G zKDpe?S8z%4s{-o3f9p46L-LDw*SSX%Pl*@2S2VQo@|#tp37C%o^;0^$9DT`FPKm!` z{J%ftgCC8)WUF9_f6!;;fupQMo>3x~m&m*$)5$j9di-+Lw1ASWYD(m~5*febe92a` z)m+G&Mc&&Q%nwiClzD$^F#eSy^M2M~eBNoI=p3@3pceR+=yjH$w|Dp+OZ*H*ObdZI zN{c@-g}g_U8%QV@k{H@;qF*Y!UARHGMR=ERKsY4K2(!WmgkKYWTll8%U11F-g#D=( z{+@8PaJ_J|a6mXD+$%gRds_Is@I?|2(i!33iT;N|eyX%WO8tlMKgpR&{Zi}! zEPu)&VT5GAMV=?*S1iV97Mkypkk^TQqmZAo=y$hphcG4fj4&_yN#OzEF|nTz@{=&* zJx$`ieo6FS6}~L?Zwg-%z9IG>2!A5_ex|B-w4a_*t4AqVU;jS!q0rK24kXM zN+M2&*t>*xi~WPbdxg8jo)u1t{ve4spAh{c!q1BRl<-;Mi()?`{HEx?O(M>lqW_`r zr((Y>{JHRd#g5au8D9m7@mC9H3FnJ_p|FL-`dCe3D_bkvEczY7q%bEuEIcm!obY+! z-wOX;_@?k@!Ye`>ZLRW`%gsX(!KGiGoJ;M8h z{NB#`dxb}YM}^0QpAzz`I{p7zcvk4`PyD1#`#%fc5?&OV{RnomAA#%kU zi{R@j??2YOx1OVvd5|Je&s+Z}8ri%jA$b1Y`j3j;dk)$}UM5^6TqE2fEPYPQ`x5cv zVjmW!g`>hr68%0PJS_Sn!lNX{aZG65pYU&&`@NR)0DB$nxR~+4Zu$?oN#bl0`xc3# zV)^}Jg~Sk8$hk~=CHz(^s2G1)sn}3HuVPfhyko~E_efH#GzaBkmG5{G!!bEFoEn+u_TW9_}%KSHIhq= z!D&O^wpgN2$Yq8m3JClEP2RbVYmI4{i>WJ?s!8*4#cjda(M_d(v@!Ag9zy5DR z-)r|NUmXf z;+=zz@i^aJyjM~7>Y%6^(b(v9#>;o0Ki-KO-RGR~s*t^S-$R-4yfGffx$J?Gc(nhZ z#IFkH2Chjj(TDkx(9^GiU#};CY?tZB$o~GFM*r9c_77XoRR6A^jPC3KOgf5qOFRK& xn@ps)7Ae03zf(|hZ(~fhTZPOveZx~9!us0^otM0LIQ|v+T|oZ=o)I>$___REG__, (__VALU + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @brief Read a value in GPIO register + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param __INSTANCE__ GPIO Instance + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param __REG__ Register to be read + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @retval Register value + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** */ + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @} + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** */ + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @} + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** */ + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /* Exported functions --------------------------------------------------------*/ + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @{ + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** */ + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @{ + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** */ + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @brief Configure gpio mode for a dedicated pin on dedicated port. + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @rmtoll MODER MODEy LL_GPIO_SetPinMode + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param GPIOx GPIO Port + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + ARM GAS /tmp/ccZKwQMo.s page 6 + + + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param Mode This parameter can be one of the following values: + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_INPUT + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_OUTPUT + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ALTERNATE + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ANALOG + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @retval None + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** */ + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** { + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL( + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** } + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @brief Return gpio mode for a dedicated pin on dedicated port. + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @rmtoll MODER MODEy LL_GPIO_GetPinMode + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param GPIOx GPIO Port + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_INPUT + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_OUTPUT + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ALTERNATE + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_MODE_ANALOG + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** */ + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** { + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->MODER, + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** } + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @brief Configure gpio output type for several pins on dedicated port. + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @note Output type as to be set when gpio pin is in output or + ARM GAS /tmp/ccZKwQMo.s page 7 + + + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * alternate modes. Possible type are Push-pull or Open-drain. + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param GPIOx GPIO Port + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param PinMask This parameter can be a combination of the following values: + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param OutputType This parameter can be one of the following values: + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @retval None + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** */ + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t Outpu + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** { + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** } + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @brief Return gpio output type for several pins on dedicated port. + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @note Output type as to be set when gpio pin is in output or + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * alternate modes. Possible type are Push-pull or Open-drain. + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param GPIOx GPIO Port + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_ALL + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + ARM GAS /tmp/ccZKwQMo.s page 8 + + + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** */ + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** { + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** } + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @brief Configure gpio speed for a dedicated pin on dedicated port. + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @note I/O speed can be Low, Medium, Fast or High speed. + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @note Refer to datasheet for frequency specifications and the power + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * supply and load conditions for each speed. + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param GPIOx GPIO Port + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param Speed This parameter can be one of the following values: + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_LOW + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @retval None + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** */ + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** { + 29 .loc 2 414 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 .loc 2 414 1 is_stmt 0 view .LVU1 + 34 0000 00B5 push {lr} + 35 .LCFI0: + 36 .cfi_def_cfa_offset 4 + 37 .cfi_offset 14, -4 + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)), + 38 .loc 2 415 3 is_stmt 1 view .LVU2 + 39 0002 8368 ldr r3, [r0, #8] + 40 .LVL1: + 41 .LBB76: + 42 .LBI76: + ARM GAS /tmp/ccZKwQMo.s page 9 + + + 43 .file 3 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + ARM GAS /tmp/ccZKwQMo.s page 10 + + + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + ARM GAS /tmp/ccZKwQMo.s page 11 + + + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + ARM GAS /tmp/ccZKwQMo.s page 12 + + + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccZKwQMo.s page 13 + + + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccZKwQMo.s page 14 + + + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + ARM GAS /tmp/ccZKwQMo.s page 15 + + + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccZKwQMo.s page 16 + + + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccZKwQMo.s page 17 + + + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + ARM GAS /tmp/ccZKwQMo.s page 18 + + + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + ARM GAS /tmp/ccZKwQMo.s page 19 + + + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccZKwQMo.s page 20 + + + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + ARM GAS /tmp/ccZKwQMo.s page 21 + + + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + ARM GAS /tmp/ccZKwQMo.s page 22 + + + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + ARM GAS /tmp/ccZKwQMo.s page 23 + + + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + ARM GAS /tmp/ccZKwQMo.s page 24 + + + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 881:Drivers/CMSIS/Include/cmsis_gcc.h **** + 882:Drivers/CMSIS/Include/cmsis_gcc.h **** + 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier + 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. + 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) + 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); + 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 892:Drivers/CMSIS/Include/cmsis_gcc.h **** + 893:Drivers/CMSIS/Include/cmsis_gcc.h **** + 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) + 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 + 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) + 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); + 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 906:Drivers/CMSIS/Include/cmsis_gcc.h **** + 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 911:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccZKwQMo.s page 25 + + + 912:Drivers/CMSIS/Include/cmsis_gcc.h **** + 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes + 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) + 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 922:Drivers/CMSIS/Include/cmsis_gcc.h **** + 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 926:Drivers/CMSIS/Include/cmsis_gcc.h **** + 927:Drivers/CMSIS/Include/cmsis_gcc.h **** + 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam + 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); + 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; + 940:Drivers/CMSIS/Include/cmsis_gcc.h **** + 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 945:Drivers/CMSIS/Include/cmsis_gcc.h **** + 946:Drivers/CMSIS/Include/cmsis_gcc.h **** + 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) + 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v + 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate + 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate + 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value + 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) + 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; + 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) + 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; + 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); + 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 963:Drivers/CMSIS/Include/cmsis_gcc.h **** + 964:Drivers/CMSIS/Include/cmsis_gcc.h **** + 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint + 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. + 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula + ARM GAS /tmp/ccZKwQMo.s page 26 + + + 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. + 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break + 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) + 973:Drivers/CMSIS/Include/cmsis_gcc.h **** + 974:Drivers/CMSIS/Include/cmsis_gcc.h **** + 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value + 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. + 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) + 44 .loc 3 981 31 view .LVU3 + 45 .LBB77: + 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 46 .loc 3 983 3 view .LVU4 + 984:Drivers/CMSIS/Include/cmsis_gcc.h **** + 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 47 .loc 3 988 4 view .LVU5 + 48 .syntax unified + 49 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 50 0004 91FAA1FC rbit ip, r1 + 51 @ 0 "" 2 + 52 .LVL2: + 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + 991:Drivers/CMSIS/Include/cmsis_gcc.h **** + 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ + 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) + 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; + 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; + 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; + 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ +1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 53 .loc 3 1001 3 view .LVU6 + 54 .loc 3 1001 3 is_stmt 0 view .LVU7 + 55 .thumb + 56 .syntax unified + 57 .LBE77: + 58 .LBE76: + 59 .loc 2 415 3 discriminator 2 view .LVU8 + 60 0008 BCFA8CFC clz ip, ip + 61 000c 4FEA4C0C lsl ip, ip, #1 + 62 0010 4FF0030E mov lr, #3 + 63 0014 0EFA0CFC lsl ip, lr, ip + 64 0018 23EA0C03 bic r3, r3, ip + 65 .LVL3: + 66 .LBB78: + 67 .LBI78: + ARM GAS /tmp/ccZKwQMo.s page 27 + + + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 68 .loc 3 981 31 is_stmt 1 view .LVU9 + 69 .LBB79: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 70 .loc 3 983 3 view .LVU10 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 71 .loc 3 988 4 view .LVU11 + 72 .syntax unified + 73 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 74 001c 91FAA1F1 rbit r1, r1 + 75 @ 0 "" 2 + 76 .LVL4: + 77 .loc 3 1001 3 view .LVU12 + 78 .loc 3 1001 3 is_stmt 0 view .LVU13 + 79 .thumb + 80 .syntax unified + 81 .LBE79: + 82 .LBE78: + 83 .loc 2 415 3 discriminator 4 view .LVU14 + 84 0020 B1FA81F1 clz r1, r1 + 85 0024 4900 lsls r1, r1, #1 + 86 0026 8A40 lsls r2, r2, r1 + 87 .LVL5: + 88 .loc 2 415 3 discriminator 4 view .LVU15 + 89 0028 1343 orrs r3, r3, r2 + 90 002a 8360 str r3, [r0, #8] + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** (Speed << (POSITION_VAL(Pin) * 2U))); + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** } + 91 .loc 2 417 1 view .LVU16 + 92 002c 5DF804FB ldr pc, [sp], #4 + 93 .cfi_endproc + 94 .LFE145: + 96 .section .text.LL_GPIO_SetPinPull,"ax",%progbits + 97 .align 1 + 98 .syntax unified + 99 .thumb + 100 .thumb_func + 102 LL_GPIO_SetPinPull: + 103 .LVL6: + 104 .LFB147: + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @brief Return gpio speed for a dedicated pin on dedicated port. + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @note I/O speed can be Low, Medium, Fast or High speed. + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @note Refer to datasheet for frequency specifications and the power + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * supply and load conditions for each speed. + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param GPIOx GPIO Port + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + ARM GAS /tmp/ccZKwQMo.s page 28 + + + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_LOW + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** */ + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** { + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** } + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param GPIOx GPIO Port + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param Pull This parameter can be one of the following values: + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_NO + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_UP + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_DOWN + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @retval None + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** */ + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** { + 105 .loc 2 485 1 is_stmt 1 view -0 + 106 .cfi_startproc + 107 @ args = 0, pretend = 0, frame = 0 + 108 @ frame_needed = 0, uses_anonymous_args = 0 + 109 .loc 2 485 1 is_stmt 0 view .LVU18 + 110 0000 00B5 push {lr} + ARM GAS /tmp/ccZKwQMo.s page 29 + + + 111 .LCFI1: + 112 .cfi_def_cfa_offset 4 + 113 .cfi_offset 14, -4 + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL( + 114 .loc 2 486 3 is_stmt 1 view .LVU19 + 115 0002 C368 ldr r3, [r0, #12] + 116 .LVL7: + 117 .LBB80: + 118 .LBI80: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 119 .loc 3 981 31 view .LVU20 + 120 .LBB81: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 121 .loc 3 983 3 view .LVU21 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 122 .loc 3 988 4 view .LVU22 + 123 .syntax unified + 124 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 125 0004 91FAA1FC rbit ip, r1 + 126 @ 0 "" 2 + 127 .LVL8: + 128 .loc 3 1001 3 view .LVU23 + 129 .loc 3 1001 3 is_stmt 0 view .LVU24 + 130 .thumb + 131 .syntax unified + 132 .LBE81: + 133 .LBE80: + 134 .loc 2 486 3 discriminator 2 view .LVU25 + 135 0008 BCFA8CFC clz ip, ip + 136 000c 4FEA4C0C lsl ip, ip, #1 + 137 0010 4FF0030E mov lr, #3 + 138 0014 0EFA0CFC lsl ip, lr, ip + 139 0018 23EA0C03 bic r3, r3, ip + 140 .LVL9: + 141 .LBB82: + 142 .LBI82: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 143 .loc 3 981 31 is_stmt 1 view .LVU26 + 144 .LBB83: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145 .loc 3 983 3 view .LVU27 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 146 .loc 3 988 4 view .LVU28 + 147 .syntax unified + 148 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 149 001c 91FAA1F1 rbit r1, r1 + 150 @ 0 "" 2 + 151 .LVL10: + 152 .loc 3 1001 3 view .LVU29 + 153 .loc 3 1001 3 is_stmt 0 view .LVU30 + 154 .thumb + 155 .syntax unified + 156 .LBE83: + 157 .LBE82: + 158 .loc 2 486 3 discriminator 4 view .LVU31 + 159 0020 B1FA81F1 clz r1, r1 + 160 0024 4900 lsls r1, r1, #1 + ARM GAS /tmp/ccZKwQMo.s page 30 + + + 161 0026 8A40 lsls r2, r2, r1 + 162 .LVL11: + 163 .loc 2 486 3 discriminator 4 view .LVU32 + 164 0028 1343 orrs r3, r3, r2 + 165 002a C360 str r3, [r0, #12] + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** } + 166 .loc 2 487 1 view .LVU33 + 167 002c 5DF804FB ldr pc, [sp], #4 + 168 .cfi_endproc + 169 .LFE147: + 171 .section .text.LL_GPIO_SetAFPin_0_7,"ax",%progbits + 172 .align 1 + 173 .syntax unified + 174 .thumb + 175 .thumb_func + 177 LL_GPIO_SetAFPin_0_7: + 178 .LVL12: + 179 .LFB149: + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param GPIOx GPIO Port + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_NO + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_UP + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PULL_DOWN + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** */ + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** { + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->PUPDR, + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** } + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @note Possible values are from AF0 to AF15 depending on target. + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + ARM GAS /tmp/ccZKwQMo.s page 31 + + + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param GPIOx GPIO Port + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param Alternate This parameter can be one of the following values: + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_0 + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_1 + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_2 + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_3 + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_4 + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_5 + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_6 + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_7 + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_8 + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_9 + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_10 + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_11 + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_12 + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_13 + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_14 + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_15 + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @retval None + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** */ + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** { + 180 .loc 2 557 1 is_stmt 1 view -0 + 181 .cfi_startproc + 182 @ args = 0, pretend = 0, frame = 0 + 183 @ frame_needed = 0, uses_anonymous_args = 0 + 184 .loc 2 557 1 is_stmt 0 view .LVU35 + 185 0000 00B5 push {lr} + 186 .LCFI2: + 187 .cfi_def_cfa_offset 4 + 188 .cfi_offset 14, -4 + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U)), + 189 .loc 2 558 3 is_stmt 1 view .LVU36 + 190 0002 036A ldr r3, [r0, #32] + 191 .LVL13: + 192 .LBB84: + 193 .LBI84: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 194 .loc 3 981 31 view .LVU37 + 195 .LBB85: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 196 .loc 3 983 3 view .LVU38 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 197 .loc 3 988 4 view .LVU39 + 198 .syntax unified + 199 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 200 0004 91FAA1FC rbit ip, r1 + 201 @ 0 "" 2 + ARM GAS /tmp/ccZKwQMo.s page 32 + + + 202 .LVL14: + 203 .loc 3 1001 3 view .LVU40 + 204 .loc 3 1001 3 is_stmt 0 view .LVU41 + 205 .thumb + 206 .syntax unified + 207 .LBE85: + 208 .LBE84: + 209 .loc 2 558 3 discriminator 2 view .LVU42 + 210 0008 BCFA8CFC clz ip, ip + 211 000c 4FEA8C0C lsl ip, ip, #2 + 212 0010 4FF00F0E mov lr, #15 + 213 0014 0EFA0CFC lsl ip, lr, ip + 214 0018 23EA0C03 bic r3, r3, ip + 215 .LVL15: + 216 .LBB86: + 217 .LBI86: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 218 .loc 3 981 31 is_stmt 1 view .LVU43 + 219 .LBB87: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 220 .loc 3 983 3 view .LVU44 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 221 .loc 3 988 4 view .LVU45 + 222 .syntax unified + 223 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 224 001c 91FAA1F1 rbit r1, r1 + 225 @ 0 "" 2 + 226 .LVL16: + 227 .loc 3 1001 3 view .LVU46 + 228 .loc 3 1001 3 is_stmt 0 view .LVU47 + 229 .thumb + 230 .syntax unified + 231 .LBE87: + 232 .LBE86: + 233 .loc 2 558 3 discriminator 4 view .LVU48 + 234 0020 B1FA81F1 clz r1, r1 + 235 0024 8900 lsls r1, r1, #2 + 236 0026 8A40 lsls r2, r2, r1 + 237 .LVL17: + 238 .loc 2 558 3 discriminator 4 view .LVU49 + 239 0028 1343 orrs r3, r3, r2 + 240 002a 0362 str r3, [r0, #32] + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** (Alternate << (POSITION_VAL(Pin) * 4U))); + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** } + 241 .loc 2 560 1 view .LVU50 + 242 002c 5DF804FB ldr pc, [sp], #4 + 243 .cfi_endproc + 244 .LFE149: + 246 .section .text.LL_GPIO_SetAFPin_8_15,"ax",%progbits + 247 .align 1 + 248 .syntax unified + 249 .thumb + 250 .thumb_func + 252 LL_GPIO_SetAFPin_8_15: + 253 .LVL18: + 254 .LFB151: + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** + ARM GAS /tmp/ccZKwQMo.s page 33 + + + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param GPIOx GPIO Port + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_0 + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_1 + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_2 + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_3 + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_4 + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_5 + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_6 + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_7 + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @retval Returned value can be one of the following values: + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_0 + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_1 + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_2 + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_3 + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_4 + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_5 + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_6 + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_7 + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_8 + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_9 + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_10 + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_11 + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_12 + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_13 + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_14 + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_15 + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** */ + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** { + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** return (uint32_t)(READ_BIT(GPIOx->AFR[0], + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** } + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** /** + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @note Possible values are from AF0 to AF15 depending on target. + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @note Warning: only one pin can be passed as parameter. + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param GPIOx GPIO Port + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param Pin This parameter can be one of the following values: + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_8 + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_9 + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_10 + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_11 + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_12 + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_13 + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_14 + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_PIN_15 + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @param Alternate This parameter can be one of the following values: + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_0 + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_1 + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_2 + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_3 + ARM GAS /tmp/ccZKwQMo.s page 34 + + + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_4 + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_5 + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_6 + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_7 + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_8 + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_9 + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_10 + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_11 + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_12 + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_13 + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_14 + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @arg @ref LL_GPIO_AF_15 + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** * @retval None + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** */ + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** { + 255 .loc 2 634 1 is_stmt 1 view -0 + 256 .cfi_startproc + 257 @ args = 0, pretend = 0, frame = 0 + 258 @ frame_needed = 0, uses_anonymous_args = 0 + 259 .loc 2 634 1 is_stmt 0 view .LVU52 + 260 0000 00B5 push {lr} + 261 .LCFI3: + 262 .cfi_def_cfa_offset 4 + 263 .cfi_offset 14, -4 + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U)), + 264 .loc 2 635 3 is_stmt 1 view .LVU53 + 265 0002 436A ldr r3, [r0, #36] + 266 0004 090A lsrs r1, r1, #8 + 267 .LVL19: + 268 .LBB88: + 269 .LBI88: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 270 .loc 3 981 31 view .LVU54 + 271 .LBB89: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272 .loc 3 983 3 view .LVU55 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 273 .loc 3 988 4 view .LVU56 + 274 .syntax unified + 275 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 276 0006 91FAA1FC rbit ip, r1 + 277 @ 0 "" 2 + 278 .LVL20: + 279 .loc 3 1001 3 view .LVU57 + 280 .loc 3 1001 3 is_stmt 0 view .LVU58 + 281 .thumb + 282 .syntax unified + 283 .LBE89: + 284 .LBE88: + 285 .loc 2 635 3 discriminator 2 view .LVU59 + 286 000a BCFA8CFC clz ip, ip + 287 000e 4FEA8C0C lsl ip, ip, #2 + 288 0012 4FF00F0E mov lr, #15 + 289 0016 0EFA0CFC lsl ip, lr, ip + 290 001a 23EA0C03 bic r3, r3, ip + 291 .LVL21: + ARM GAS /tmp/ccZKwQMo.s page 35 + + + 292 .LBB90: + 293 .LBI90: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 294 .loc 3 981 31 is_stmt 1 view .LVU60 + 295 .LBB91: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296 .loc 3 983 3 view .LVU61 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 297 .loc 3 988 4 view .LVU62 + 298 .syntax unified + 299 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 300 001e 91FAA1F1 rbit r1, r1 + 301 @ 0 "" 2 + 302 .LVL22: + 303 .loc 3 1001 3 view .LVU63 + 304 .loc 3 1001 3 is_stmt 0 view .LVU64 + 305 .thumb + 306 .syntax unified + 307 .LBE91: + 308 .LBE90: + 309 .loc 2 635 3 discriminator 4 view .LVU65 + 310 0022 B1FA81F1 clz r1, r1 + 311 0026 8900 lsls r1, r1, #2 + 312 0028 8A40 lsls r2, r2, r1 + 313 .LVL23: + 314 .loc 2 635 3 discriminator 4 view .LVU66 + 315 002a 1343 orrs r3, r3, r2 + 316 002c 4362 str r3, [r0, #36] + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** } + 317 .loc 2 637 1 view .LVU67 + 318 002e 5DF804FB ldr pc, [sp], #4 + 319 .cfi_endproc + 320 .LFE151: + 322 .section .text.LL_GPIO_SetPinMode,"ax",%progbits + 323 .align 1 + 324 .syntax unified + 325 .thumb + 326 .thumb_func + 328 LL_GPIO_SetPinMode: + 329 .LVL24: + 330 .LFB141: + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL( + 331 .loc 2 274 1 is_stmt 1 view -0 + 332 .cfi_startproc + 333 @ args = 0, pretend = 0, frame = 0 + 334 @ frame_needed = 0, uses_anonymous_args = 0 + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL( + 335 .loc 2 274 1 is_stmt 0 view .LVU69 + 336 0000 00B5 push {lr} + 337 .LCFI4: + 338 .cfi_def_cfa_offset 4 + 339 .cfi_offset 14, -4 + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** } + 340 .loc 2 275 3 is_stmt 1 view .LVU70 + 341 0002 0368 ldr r3, [r0] + 342 .LVL25: + ARM GAS /tmp/ccZKwQMo.s page 36 + + + 343 .LBB92: + 344 .LBI92: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345 .loc 3 981 31 view .LVU71 + 346 .LBB93: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 347 .loc 3 983 3 view .LVU72 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 348 .loc 3 988 4 view .LVU73 + 349 .syntax unified + 350 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 351 0004 91FAA1FC rbit ip, r1 + 352 @ 0 "" 2 + 353 .LVL26: + 354 .loc 3 1001 3 view .LVU74 + 355 .loc 3 1001 3 is_stmt 0 view .LVU75 + 356 .thumb + 357 .syntax unified + 358 .LBE93: + 359 .LBE92: + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** } + 360 .loc 2 275 3 discriminator 2 view .LVU76 + 361 0008 BCFA8CFC clz ip, ip + 362 000c 4FEA4C0C lsl ip, ip, #1 + 363 0010 4FF0030E mov lr, #3 + 364 0014 0EFA0CFC lsl ip, lr, ip + 365 0018 23EA0C03 bic r3, r3, ip + 366 .LVL27: + 367 .LBB94: + 368 .LBI94: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 369 .loc 3 981 31 is_stmt 1 view .LVU77 + 370 .LBB95: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 371 .loc 3 983 3 view .LVU78 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 372 .loc 3 988 4 view .LVU79 + 373 .syntax unified + 374 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 375 001c 91FAA1F1 rbit r1, r1 + 376 @ 0 "" 2 + 377 .LVL28: + 378 .loc 3 1001 3 view .LVU80 + 379 .loc 3 1001 3 is_stmt 0 view .LVU81 + 380 .thumb + 381 .syntax unified + 382 .LBE95: + 383 .LBE94: + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** } + 384 .loc 2 275 3 discriminator 4 view .LVU82 + 385 0020 B1FA81F1 clz r1, r1 + 386 0024 4900 lsls r1, r1, #1 + 387 0026 8A40 lsls r2, r2, r1 + 388 .LVL29: + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** } + 389 .loc 2 275 3 discriminator 4 view .LVU83 + 390 0028 1343 orrs r3, r3, r2 + ARM GAS /tmp/ccZKwQMo.s page 37 + + + 391 002a 0360 str r3, [r0] + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** + 392 .loc 2 276 1 view .LVU84 + 393 002c 5DF804FB ldr pc, [sp], #4 + 394 .cfi_endproc + 395 .LFE141: + 397 .section .text.LL_GPIO_DeInit,"ax",%progbits + 398 .align 1 + 399 .global LL_GPIO_DeInit + 400 .syntax unified + 401 .thumb + 402 .thumb_func + 404 LL_GPIO_DeInit: + 405 .LVL30: + 406 .LFB199: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @file stm32f7xx_ll_gpio.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @brief GPIO LL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * This software is licensed under terms that can be found in the LICENSE file + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * in the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** */ + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined(USE_FULL_LL_DRIVER) + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Includes ------------------------------------------------------------------*/ + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #include "stm32f7xx_ll_gpio.h" + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #include "stm32f7xx_ll_bus.h" + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #ifdef USE_FULL_ASSERT + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #include "stm32_assert.h" + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #else + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #define assert_param(expr) ((void)0U) + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #endif + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /** @addtogroup STM32F7xx_LL_Driver + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @{ + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** */ + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /** @addtogroup GPIO_LL + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @{ + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** */ + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Private types -------------------------------------------------------------*/ + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Private variables ---------------------------------------------------------*/ + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Private constants ---------------------------------------------------------*/ + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Private macros ------------------------------------------------------------*/ + ARM GAS /tmp/ccZKwQMo.s page 38 + + + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /** @addtogroup GPIO_LL_Private_Macros + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @{ + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** */ + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GP + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\ + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_MODE_ANALOG)) + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\ + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH)) + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_PULL_UP) ||\ + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_PULL_DOWN)) + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\ + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_1 ) ||\ + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_2 ) ||\ + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_3 ) ||\ + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_4 ) ||\ + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_5 ) ||\ + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_6 ) ||\ + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_7 ) ||\ + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_8 ) ||\ + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_9 ) ||\ + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_10 ) ||\ + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_11 ) ||\ + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_12 ) ||\ + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_13 ) ||\ + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_14 ) ||\ + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ((__VALUE__) == LL_GPIO_AF_15 )) + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /** + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @} + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** */ + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Private function prototypes -----------------------------------------------*/ + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Exported functions --------------------------------------------------------*/ + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /** @addtogroup GPIO_LL_Exported_Functions + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @{ + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** */ + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /** @addtogroup GPIO_LL_EF_Init + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @{ + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** */ + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /** + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @brief De-initialize GPIO registers (Registers restored to their default values). + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @param GPIOx GPIO Port + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @retval An ErrorStatus enumeration value: + ARM GAS /tmp/ccZKwQMo.s page 39 + + + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * - SUCCESS: GPIO registers are de-initialized + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * - ERROR: Wrong GPIO Port + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** */ + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 407 .loc 1 104 1 is_stmt 1 view -0 + 408 .cfi_startproc + 409 @ args = 0, pretend = 0, frame = 0 + 410 @ frame_needed = 0, uses_anonymous_args = 0 + 411 @ link register save eliminated. + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ErrorStatus status = SUCCESS; + 412 .loc 1 105 3 view .LVU86 + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Check the parameters */ + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + 413 .loc 1 108 3 view .LVU87 + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Force and Release reset on clock of GPIOx Port */ + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** if (GPIOx == GPIOA) + 414 .loc 1 111 3 view .LVU88 + 415 .loc 1 111 6 is_stmt 0 view .LVU89 + 416 0000 534B ldr r3, .L35 + 417 0002 9842 cmp r0, r3 + 418 0004 1FD0 beq .L24 + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA); + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA); + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** else if (GPIOx == GPIOB) + 419 .loc 1 116 8 is_stmt 1 view .LVU90 + 420 .loc 1 116 11 is_stmt 0 view .LVU91 + 421 0006 534B ldr r3, .L35+4 + 422 0008 9842 cmp r0, r3 + 423 000a 28D0 beq .L25 + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB); + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB); + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** else if (GPIOx == GPIOC) + 424 .loc 1 121 8 is_stmt 1 view .LVU92 + 425 .loc 1 121 11 is_stmt 0 view .LVU93 + 426 000c 524B ldr r3, .L35+8 + 427 000e 9842 cmp r0, r3 + 428 0010 31D0 beq .L26 + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC); + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC); + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined(GPIOD) + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** else if (GPIOx == GPIOD) + 429 .loc 1 127 8 is_stmt 1 view .LVU94 + 430 .loc 1 127 11 is_stmt 0 view .LVU95 + 431 0012 524B ldr r3, .L35+12 + 432 0014 9842 cmp r0, r3 + 433 0016 3AD0 beq .L27 + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD); + ARM GAS /tmp/ccZKwQMo.s page 40 + + + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD); + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #endif /* GPIOD */ + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined(GPIOE) + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** else if (GPIOx == GPIOE) + 434 .loc 1 134 8 is_stmt 1 view .LVU96 + 435 .loc 1 134 11 is_stmt 0 view .LVU97 + 436 0018 514B ldr r3, .L35+16 + 437 001a 9842 cmp r0, r3 + 438 001c 43D0 beq .L28 + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE); + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE); + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #endif /* GPIOE */ + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined(GPIOF) + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** else if (GPIOx == GPIOF) + 439 .loc 1 141 8 is_stmt 1 view .LVU98 + 440 .loc 1 141 11 is_stmt 0 view .LVU99 + 441 001e 514B ldr r3, .L35+20 + 442 0020 9842 cmp r0, r3 + 443 0022 4CD0 beq .L29 + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF); + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF); + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #endif /* GPIOF */ + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined(GPIOG) + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** else if (GPIOx == GPIOG) + 444 .loc 1 148 8 is_stmt 1 view .LVU100 + 445 .loc 1 148 11 is_stmt 0 view .LVU101 + 446 0024 504B ldr r3, .L35+24 + 447 0026 9842 cmp r0, r3 + 448 0028 55D0 beq .L30 + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOG); + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOG); + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #endif /* GPIOG */ + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined(GPIOH) + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** else if (GPIOx == GPIOH) + 449 .loc 1 155 8 is_stmt 1 view .LVU102 + 450 .loc 1 155 11 is_stmt 0 view .LVU103 + 451 002a 504B ldr r3, .L35+28 + 452 002c 9842 cmp r0, r3 + 453 002e 5ED0 beq .L31 + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOH); + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOH); + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #endif /* GPIOH */ + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined(GPIOI) + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** else if (GPIOx == GPIOI) + 454 .loc 1 162 8 is_stmt 1 view .LVU104 + 455 .loc 1 162 11 is_stmt 0 view .LVU105 + 456 0030 4F4B ldr r3, .L35+32 + 457 0032 9842 cmp r0, r3 + ARM GAS /tmp/ccZKwQMo.s page 41 + + + 458 0034 67D0 beq .L32 + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOI); + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOI); + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #endif /* GPIOI */ + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined(GPIOJ) + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** else if (GPIOx == GPIOJ) + 459 .loc 1 169 8 is_stmt 1 view .LVU106 + 460 .loc 1 169 11 is_stmt 0 view .LVU107 + 461 0036 4F4B ldr r3, .L35+36 + 462 0038 9842 cmp r0, r3 + 463 003a 70D0 beq .L33 + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOJ); + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOJ); + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #endif /* GPIOJ */ + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #if defined(GPIOK) + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** else if (GPIOx == GPIOK) + 464 .loc 1 176 8 is_stmt 1 view .LVU108 + 465 .loc 1 176 11 is_stmt 0 view .LVU109 + 466 003c 4E4B ldr r3, .L35+40 + 467 003e 9842 cmp r0, r3 + 468 0040 79D0 beq .L34 + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOK); + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOK); + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** #endif /* GPIOK */ + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** else + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** status = ERROR; + 469 .loc 1 184 12 view .LVU110 + 470 0042 0120 movs r0, #1 + 471 .LVL31: + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** return (status); + 472 .loc 1 187 3 is_stmt 1 view .LVU111 + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 473 .loc 1 188 1 is_stmt 0 view .LVU112 + 474 0044 7047 bx lr + 475 .LVL32: + 476 .L24: + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA); + 477 .loc 1 113 5 is_stmt 1 view .LVU113 + 478 .LBB96: + 479 .LBI96: + 480 .file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @file stm32f7xx_ll_bus.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @verbatim + ARM GAS /tmp/ccZKwQMo.s page 42 + + + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @attention + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * Copyright (c) 2017 STMicroelectronics. + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * All rights reserved. + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * This software is licensed under terms that can be found in the LICENSE file in + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * the root directory of this software component. + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifndef __STM32F7xx_LL_BUS_H + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define __STM32F7xx_LL_BUS_H + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifdef __cplusplus + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** extern "C" { + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #include "stm32f7xx.h" + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @addtogroup STM32F7xx_LL_Driver + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC) + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + ARM GAS /tmp/ccZKwQMo.s page 43 + + + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOJ) + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOJ */ + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOK) + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOK */ + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DTCMRAM RCC_AHB1ENR_DTCMRAMEN + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DMA2D) + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DMA2D */ + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(ETH) + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* ETH */ + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_AXI RCC_AHB1LPENR_AXILPEN + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DCMI) + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DCMI */ + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(JPEG) + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_JPEG RCC_AHB2ENR_JPEGEN + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* JPEG */ + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CRYP) + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CRYP */ + ARM GAS /tmp/ccZKwQMo.s page 44 + + + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(AES) + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* AES */ + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(HASH) + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* HASH */ + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPDIFRX) + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPDIFRX */ + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(I2C4) + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C4 RCC_APB1ENR_I2C4EN + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* I2C4 */ + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN2) + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN2 */ + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN3) + ARM GAS /tmp/ccZKwQMo.s page 45 + + + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN3 */ + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CEC) + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CEC */ + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC_APB1ENR_RTCEN) + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCEN + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* RCC_APB1ENR_RTCEN */ + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SDMMC2) + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC2 RCC_APB2ENR_SDMMC2EN + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SDMMC2 */ + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPI6) + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPI6 */ + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(LTDC) + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* LTDC */ + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DSI) + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DSI */ + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DFSDM1_Channel0) + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DFSDM1_Channel0 */ + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(MDIOS) + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_MDIO RCC_APB2ENR_MDIOEN + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* MDIOS */ + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(USB_HS_PHYC) + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_OTGPHYC RCC_APB2ENR_OTGPHYCEN + ARM GAS /tmp/ccZKwQMo.s page 46 + + + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* USB_HS_PHYC */ + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_EnableClock\n + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + ARM GAS /tmp/ccZKwQMo.s page 47 + + + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_IsEnabledClock\n + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_IsEnabledClock + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + ARM GAS /tmp/ccZKwQMo.s page 48 + + + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_DisableClock\n + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_DisableClock + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + ARM GAS /tmp/ccZKwQMo.s page 49 + + + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1ENR, Periphs); + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + ARM GAS /tmp/ccZKwQMo.s page 50 + + + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 481 .loc 4 476 22 view .LVU114 + 482 .LBB97: + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1RSTR, Periphs); + 483 .loc 4 478 3 view .LVU115 + 484 0046 03F56053 add r3, r3, #14336 + 485 004a 1A69 ldr r2, [r3, #16] + 486 004c 42F00102 orr r2, r2, #1 + 487 0050 1A61 str r2, [r3, #16] + 488 .LVL33: + 489 .loc 4 478 3 is_stmt 0 view .LVU116 + 490 .LBE97: + 491 .LBE96: + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 492 .loc 1 114 5 is_stmt 1 view .LVU117 + 493 .LBB98: + 494 .LBI98: + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + ARM GAS /tmp/ccZKwQMo.s page 51 + + + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 495 .loc 4 523 22 view .LVU118 + 496 .LBB99: + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1RSTR, Periphs); + 497 .loc 4 525 3 view .LVU119 + 498 0052 1A69 ldr r2, [r3, #16] + 499 0054 22F00102 bic r2, r2, #1 + 500 0058 1A61 str r2, [r3, #16] + 501 .LVL34: + 502 .loc 4 525 3 is_stmt 0 view .LVU120 + 503 .LBE99: + 504 .LBE98: + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 505 .loc 1 105 15 view .LVU121 + 506 005a 0020 movs r0, #0 + 507 .LVL35: + 508 .LBB101: + 509 .LBB100: + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 510 .loc 4 526 1 view .LVU122 + 511 005c 7047 bx lr + 512 .LVL36: + 513 .L25: + 514 .loc 4 526 1 view .LVU123 + 515 .LBE100: + 516 .LBE101: + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB); + 517 .loc 1 118 5 is_stmt 1 view .LVU124 + 518 .LBB102: + 519 .LBI102: + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 520 .loc 4 476 22 view .LVU125 + 521 .LBB103: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 522 .loc 4 478 3 view .LVU126 + 523 005e 03F55053 add r3, r3, #13312 + 524 0062 1A69 ldr r2, [r3, #16] + 525 0064 42F00202 orr r2, r2, #2 + 526 0068 1A61 str r2, [r3, #16] + ARM GAS /tmp/ccZKwQMo.s page 52 + + + 527 .LVL37: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 528 .loc 4 478 3 is_stmt 0 view .LVU127 + 529 .LBE103: + 530 .LBE102: + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 531 .loc 1 119 5 is_stmt 1 view .LVU128 + 532 .LBB104: + 533 .LBI104: + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 534 .loc 4 523 22 view .LVU129 + 535 .LBB105: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 536 .loc 4 525 3 view .LVU130 + 537 006a 1A69 ldr r2, [r3, #16] + 538 006c 22F00202 bic r2, r2, #2 + 539 0070 1A61 str r2, [r3, #16] + 540 .LVL38: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 541 .loc 4 525 3 is_stmt 0 view .LVU131 + 542 .LBE105: + 543 .LBE104: + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 544 .loc 1 105 15 view .LVU132 + 545 0072 0020 movs r0, #0 + 546 .LVL39: + 547 .LBB107: + 548 .LBB106: + 549 .loc 4 526 1 view .LVU133 + 550 0074 7047 bx lr + 551 .LVL40: + 552 .L26: + 553 .loc 4 526 1 view .LVU134 + 554 .LBE106: + 555 .LBE107: + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC); + 556 .loc 1 123 5 is_stmt 1 view .LVU135 + 557 .LBB108: + 558 .LBI108: + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 559 .loc 4 476 22 view .LVU136 + 560 .LBB109: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 561 .loc 4 478 3 view .LVU137 + 562 0076 03F54053 add r3, r3, #12288 + 563 007a 1A69 ldr r2, [r3, #16] + 564 007c 42F00402 orr r2, r2, #4 + 565 0080 1A61 str r2, [r3, #16] + 566 .LVL41: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 567 .loc 4 478 3 is_stmt 0 view .LVU138 + 568 .LBE109: + 569 .LBE108: + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 570 .loc 1 124 5 is_stmt 1 view .LVU139 + 571 .LBB110: + 572 .LBI110: + ARM GAS /tmp/ccZKwQMo.s page 53 + + + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 573 .loc 4 523 22 view .LVU140 + 574 .LBB111: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 575 .loc 4 525 3 view .LVU141 + 576 0082 1A69 ldr r2, [r3, #16] + 577 0084 22F00402 bic r2, r2, #4 + 578 0088 1A61 str r2, [r3, #16] + 579 .LVL42: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 580 .loc 4 525 3 is_stmt 0 view .LVU142 + 581 .LBE111: + 582 .LBE110: + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 583 .loc 1 105 15 view .LVU143 + 584 008a 0020 movs r0, #0 + 585 .LVL43: + 586 .LBB113: + 587 .LBB112: + 588 .loc 4 526 1 view .LVU144 + 589 008c 7047 bx lr + 590 .LVL44: + 591 .L27: + 592 .loc 4 526 1 view .LVU145 + 593 .LBE112: + 594 .LBE113: + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD); + 595 .loc 1 129 5 is_stmt 1 view .LVU146 + 596 .LBB114: + 597 .LBI114: + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 598 .loc 4 476 22 view .LVU147 + 599 .LBB115: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 600 .loc 4 478 3 view .LVU148 + 601 008e 03F53053 add r3, r3, #11264 + 602 0092 1A69 ldr r2, [r3, #16] + 603 0094 42F00802 orr r2, r2, #8 + 604 0098 1A61 str r2, [r3, #16] + 605 .LVL45: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 606 .loc 4 478 3 is_stmt 0 view .LVU149 + 607 .LBE115: + 608 .LBE114: + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 609 .loc 1 130 5 is_stmt 1 view .LVU150 + 610 .LBB116: + 611 .LBI116: + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 612 .loc 4 523 22 view .LVU151 + 613 .LBB117: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 614 .loc 4 525 3 view .LVU152 + 615 009a 1A69 ldr r2, [r3, #16] + 616 009c 22F00802 bic r2, r2, #8 + 617 00a0 1A61 str r2, [r3, #16] + 618 .LVL46: + ARM GAS /tmp/ccZKwQMo.s page 54 + + + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 619 .loc 4 525 3 is_stmt 0 view .LVU153 + 620 .LBE117: + 621 .LBE116: + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 622 .loc 1 105 15 view .LVU154 + 623 00a2 0020 movs r0, #0 + 624 .LVL47: + 625 .LBB119: + 626 .LBB118: + 627 .loc 4 526 1 view .LVU155 + 628 00a4 7047 bx lr + 629 .LVL48: + 630 .L28: + 631 .loc 4 526 1 view .LVU156 + 632 .LBE118: + 633 .LBE119: + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE); + 634 .loc 1 136 5 is_stmt 1 view .LVU157 + 635 .LBB120: + 636 .LBI120: + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 637 .loc 4 476 22 view .LVU158 + 638 .LBB121: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 639 .loc 4 478 3 view .LVU159 + 640 00a6 03F52053 add r3, r3, #10240 + 641 00aa 1A69 ldr r2, [r3, #16] + 642 00ac 42F01002 orr r2, r2, #16 + 643 00b0 1A61 str r2, [r3, #16] + 644 .LVL49: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 645 .loc 4 478 3 is_stmt 0 view .LVU160 + 646 .LBE121: + 647 .LBE120: + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 648 .loc 1 137 5 is_stmt 1 view .LVU161 + 649 .LBB122: + 650 .LBI122: + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 651 .loc 4 523 22 view .LVU162 + 652 .LBB123: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 653 .loc 4 525 3 view .LVU163 + 654 00b2 1A69 ldr r2, [r3, #16] + 655 00b4 22F01002 bic r2, r2, #16 + 656 00b8 1A61 str r2, [r3, #16] + 657 .LVL50: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 658 .loc 4 525 3 is_stmt 0 view .LVU164 + 659 .LBE123: + 660 .LBE122: + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 661 .loc 1 105 15 view .LVU165 + 662 00ba 0020 movs r0, #0 + 663 .LVL51: + 664 .LBB125: + ARM GAS /tmp/ccZKwQMo.s page 55 + + + 665 .LBB124: + 666 .loc 4 526 1 view .LVU166 + 667 00bc 7047 bx lr + 668 .LVL52: + 669 .L29: + 670 .loc 4 526 1 view .LVU167 + 671 .LBE124: + 672 .LBE125: + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF); + 673 .loc 1 143 5 is_stmt 1 view .LVU168 + 674 .LBB126: + 675 .LBI126: + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 676 .loc 4 476 22 view .LVU169 + 677 .LBB127: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 678 .loc 4 478 3 view .LVU170 + 679 00be 03F51053 add r3, r3, #9216 + 680 00c2 1A69 ldr r2, [r3, #16] + 681 00c4 42F02002 orr r2, r2, #32 + 682 00c8 1A61 str r2, [r3, #16] + 683 .LVL53: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 684 .loc 4 478 3 is_stmt 0 view .LVU171 + 685 .LBE127: + 686 .LBE126: + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 687 .loc 1 144 5 is_stmt 1 view .LVU172 + 688 .LBB128: + 689 .LBI128: + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 690 .loc 4 523 22 view .LVU173 + 691 .LBB129: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 692 .loc 4 525 3 view .LVU174 + 693 00ca 1A69 ldr r2, [r3, #16] + 694 00cc 22F02002 bic r2, r2, #32 + 695 00d0 1A61 str r2, [r3, #16] + 696 .LVL54: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 697 .loc 4 525 3 is_stmt 0 view .LVU175 + 698 .LBE129: + 699 .LBE128: + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 700 .loc 1 105 15 view .LVU176 + 701 00d2 0020 movs r0, #0 + 702 .LVL55: + 703 .LBB131: + 704 .LBB130: + 705 .loc 4 526 1 view .LVU177 + 706 00d4 7047 bx lr + 707 .LVL56: + 708 .L30: + 709 .loc 4 526 1 view .LVU178 + 710 .LBE130: + 711 .LBE131: + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOG); + ARM GAS /tmp/ccZKwQMo.s page 56 + + + 712 .loc 1 150 5 is_stmt 1 view .LVU179 + 713 .LBB132: + 714 .LBI132: + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 715 .loc 4 476 22 view .LVU180 + 716 .LBB133: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 717 .loc 4 478 3 view .LVU181 + 718 00d6 03F50053 add r3, r3, #8192 + 719 00da 1A69 ldr r2, [r3, #16] + 720 00dc 42F04002 orr r2, r2, #64 + 721 00e0 1A61 str r2, [r3, #16] + 722 .LVL57: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 723 .loc 4 478 3 is_stmt 0 view .LVU182 + 724 .LBE133: + 725 .LBE132: + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 726 .loc 1 151 5 is_stmt 1 view .LVU183 + 727 .LBB134: + 728 .LBI134: + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 729 .loc 4 523 22 view .LVU184 + 730 .LBB135: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 731 .loc 4 525 3 view .LVU185 + 732 00e2 1A69 ldr r2, [r3, #16] + 733 00e4 22F04002 bic r2, r2, #64 + 734 00e8 1A61 str r2, [r3, #16] + 735 .LVL58: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 736 .loc 4 525 3 is_stmt 0 view .LVU186 + 737 .LBE135: + 738 .LBE134: + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 739 .loc 1 105 15 view .LVU187 + 740 00ea 0020 movs r0, #0 + 741 .LVL59: + 742 .LBB137: + 743 .LBB136: + 744 .loc 4 526 1 view .LVU188 + 745 00ec 7047 bx lr + 746 .LVL60: + 747 .L31: + 748 .loc 4 526 1 view .LVU189 + 749 .LBE136: + 750 .LBE137: + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOH); + 751 .loc 1 157 5 is_stmt 1 view .LVU190 + 752 .LBB138: + 753 .LBI138: + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 754 .loc 4 476 22 view .LVU191 + 755 .LBB139: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 756 .loc 4 478 3 view .LVU192 + 757 00ee 03F5E053 add r3, r3, #7168 + ARM GAS /tmp/ccZKwQMo.s page 57 + + + 758 00f2 1A69 ldr r2, [r3, #16] + 759 00f4 42F08002 orr r2, r2, #128 + 760 00f8 1A61 str r2, [r3, #16] + 761 .LVL61: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 762 .loc 4 478 3 is_stmt 0 view .LVU193 + 763 .LBE139: + 764 .LBE138: + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 765 .loc 1 158 5 is_stmt 1 view .LVU194 + 766 .LBB140: + 767 .LBI140: + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 768 .loc 4 523 22 view .LVU195 + 769 .LBB141: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 770 .loc 4 525 3 view .LVU196 + 771 00fa 1A69 ldr r2, [r3, #16] + 772 00fc 22F08002 bic r2, r2, #128 + 773 0100 1A61 str r2, [r3, #16] + 774 .LVL62: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 775 .loc 4 525 3 is_stmt 0 view .LVU197 + 776 .LBE141: + 777 .LBE140: + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 778 .loc 1 105 15 view .LVU198 + 779 0102 0020 movs r0, #0 + 780 .LVL63: + 781 .LBB143: + 782 .LBB142: + 783 .loc 4 526 1 view .LVU199 + 784 0104 7047 bx lr + 785 .LVL64: + 786 .L32: + 787 .loc 4 526 1 view .LVU200 + 788 .LBE142: + 789 .LBE143: + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOI); + 790 .loc 1 164 5 is_stmt 1 view .LVU201 + 791 .LBB144: + 792 .LBI144: + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 793 .loc 4 476 22 view .LVU202 + 794 .LBB145: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 795 .loc 4 478 3 view .LVU203 + 796 0106 03F5C053 add r3, r3, #6144 + 797 010a 1A69 ldr r2, [r3, #16] + 798 010c 42F48072 orr r2, r2, #256 + 799 0110 1A61 str r2, [r3, #16] + 800 .LVL65: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 801 .loc 4 478 3 is_stmt 0 view .LVU204 + 802 .LBE145: + 803 .LBE144: + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + ARM GAS /tmp/ccZKwQMo.s page 58 + + + 804 .loc 1 165 5 is_stmt 1 view .LVU205 + 805 .LBB146: + 806 .LBI146: + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 807 .loc 4 523 22 view .LVU206 + 808 .LBB147: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 809 .loc 4 525 3 view .LVU207 + 810 0112 1A69 ldr r2, [r3, #16] + 811 0114 22F48072 bic r2, r2, #256 + 812 0118 1A61 str r2, [r3, #16] + 813 .LVL66: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 814 .loc 4 525 3 is_stmt 0 view .LVU208 + 815 .LBE147: + 816 .LBE146: + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 817 .loc 1 105 15 view .LVU209 + 818 011a 0020 movs r0, #0 + 819 .LVL67: + 820 .LBB149: + 821 .LBB148: + 822 .loc 4 526 1 view .LVU210 + 823 011c 7047 bx lr + 824 .LVL68: + 825 .L33: + 826 .loc 4 526 1 view .LVU211 + 827 .LBE148: + 828 .LBE149: + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOJ); + 829 .loc 1 171 5 is_stmt 1 view .LVU212 + 830 .LBB150: + 831 .LBI150: + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 832 .loc 4 476 22 view .LVU213 + 833 .LBB151: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 834 .loc 4 478 3 view .LVU214 + 835 011e 03F5A053 add r3, r3, #5120 + 836 0122 1A69 ldr r2, [r3, #16] + 837 0124 42F40072 orr r2, r2, #512 + 838 0128 1A61 str r2, [r3, #16] + 839 .LVL69: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 840 .loc 4 478 3 is_stmt 0 view .LVU215 + 841 .LBE151: + 842 .LBE150: + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 843 .loc 1 172 5 is_stmt 1 view .LVU216 + 844 .LBB152: + 845 .LBI152: + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 846 .loc 4 523 22 view .LVU217 + 847 .LBB153: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 848 .loc 4 525 3 view .LVU218 + 849 012a 1A69 ldr r2, [r3, #16] + ARM GAS /tmp/ccZKwQMo.s page 59 + + + 850 012c 22F40072 bic r2, r2, #512 + 851 0130 1A61 str r2, [r3, #16] + 852 .LVL70: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 853 .loc 4 525 3 is_stmt 0 view .LVU219 + 854 .LBE153: + 855 .LBE152: + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 856 .loc 1 105 15 view .LVU220 + 857 0132 0020 movs r0, #0 + 858 .LVL71: + 859 .LBB155: + 860 .LBB154: + 861 .loc 4 526 1 view .LVU221 + 862 0134 7047 bx lr + 863 .LVL72: + 864 .L34: + 865 .loc 4 526 1 view .LVU222 + 866 .LBE154: + 867 .LBE155: + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOK); + 868 .loc 1 178 5 is_stmt 1 view .LVU223 + 869 .LBB156: + 870 .LBI156: + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 871 .loc 4 476 22 view .LVU224 + 872 .LBB157: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 873 .loc 4 478 3 view .LVU225 + 874 0136 03F58053 add r3, r3, #4096 + 875 013a 1A69 ldr r2, [r3, #16] + 876 013c 42F48062 orr r2, r2, #1024 + 877 0140 1A61 str r2, [r3, #16] + 878 .LVL73: + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 879 .loc 4 478 3 is_stmt 0 view .LVU226 + 880 .LBE157: + 881 .LBE156: + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 882 .loc 1 179 5 is_stmt 1 view .LVU227 + 883 .LBB158: + 884 .LBI158: + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 885 .loc 4 523 22 view .LVU228 + 886 .LBB159: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 887 .loc 4 525 3 view .LVU229 + 888 0142 1A69 ldr r2, [r3, #16] + 889 0144 22F48062 bic r2, r2, #1024 + 890 0148 1A61 str r2, [r3, #16] + 891 .LVL74: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 892 .loc 4 525 3 is_stmt 0 view .LVU230 + 893 .LBE159: + 894 .LBE158: + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 895 .loc 1 105 15 view .LVU231 + ARM GAS /tmp/ccZKwQMo.s page 60 + + + 896 014a 0020 movs r0, #0 + 897 .LVL75: + 898 .LBB161: + 899 .LBB160: + 900 .loc 4 526 1 view .LVU232 + 901 014c 7047 bx lr + 902 .L36: + 903 014e 00BF .align 2 + 904 .L35: + 905 0150 00000240 .word 1073872896 + 906 0154 00040240 .word 1073873920 + 907 0158 00080240 .word 1073874944 + 908 015c 000C0240 .word 1073875968 + 909 0160 00100240 .word 1073876992 + 910 0164 00140240 .word 1073878016 + 911 0168 00180240 .word 1073879040 + 912 016c 001C0240 .word 1073880064 + 913 0170 00200240 .word 1073881088 + 914 0174 00240240 .word 1073882112 + 915 0178 00280240 .word 1073883136 + 916 .LBE160: + 917 .LBE161: + 918 .cfi_endproc + 919 .LFE199: + 921 .section .text.LL_GPIO_Init,"ax",%progbits + 922 .align 1 + 923 .global LL_GPIO_Init + 924 .syntax unified + 925 .thumb + 926 .thumb_func + 928 LL_GPIO_Init: + 929 .LVL76: + 930 .LFB200: + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /** + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @param GPIOx GPIO Port + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * that contains the configuration information for the specified GPIO peripheral. + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @retval An ErrorStatus enumeration value: + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * - ERROR: Not applicable + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** */ + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 931 .loc 1 200 1 is_stmt 1 view -0 + 932 .cfi_startproc + 933 @ args = 0, pretend = 0, frame = 0 + 934 @ frame_needed = 0, uses_anonymous_args = 0 + 935 .loc 1 200 1 is_stmt 0 view .LVU234 + 936 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 937 .LCFI5: + 938 .cfi_def_cfa_offset 24 + 939 .cfi_offset 3, -24 + 940 .cfi_offset 4, -20 + 941 .cfi_offset 5, -16 + 942 .cfi_offset 6, -12 + ARM GAS /tmp/ccZKwQMo.s page 61 + + + 943 .cfi_offset 7, -8 + 944 .cfi_offset 14, -4 + 945 0002 0746 mov r7, r0 + 946 0004 0E46 mov r6, r1 + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** uint32_t pinpos = 0x00000000U; + 947 .loc 1 201 3 is_stmt 1 view .LVU235 + 948 .LVL77: + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** uint32_t currentpin = 0x00000000U; + 949 .loc 1 202 3 view .LVU236 + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Check the parameters */ + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + 950 .loc 1 205 3 view .LVU237 + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); + 951 .loc 1 206 3 view .LVU238 + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); + 952 .loc 1 207 3 view .LVU239 + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); + 953 .loc 1 208 3 view .LVU240 + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* ------------------------- Configure the port pins ---------------- */ + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Initialize pinpos on first pin set */ + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** pinpos = POSITION_VAL(GPIO_InitStruct->Pin); + 954 .loc 1 212 3 view .LVU241 + 955 .loc 1 212 12 is_stmt 0 view .LVU242 + 956 0006 0D68 ldr r5, [r1] + 957 .LVL78: + 958 .LBB162: + 959 .LBI162: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 960 .loc 3 981 31 is_stmt 1 view .LVU243 + 961 .LBB163: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 962 .loc 3 983 3 view .LVU244 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 963 .loc 3 988 4 view .LVU245 + 964 .syntax unified + 965 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 966 0008 95FAA5F5 rbit r5, r5 + 967 @ 0 "" 2 + 968 .LVL79: + 969 .loc 3 1001 3 view .LVU246 + 970 .loc 3 1001 3 is_stmt 0 view .LVU247 + 971 .thumb + 972 .syntax unified + 973 .LBE163: + 974 .LBE162: + 975 .loc 1 212 10 discriminator 2 view .LVU248 + 976 000c B5FA85F5 clz r5, r5 + 977 .LVL80: + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Configure the port pins */ + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) + 978 .loc 1 215 3 is_stmt 1 view .LVU249 + 979 .loc 1 215 9 is_stmt 0 view .LVU250 + 980 0010 19E0 b .L38 + 981 .LVL81: + ARM GAS /tmp/ccZKwQMo.s page 62 + + + 982 .L46: + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Get current io position */ + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos); + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** if (currentpin) + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Check Speed mode parameters */ + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); + 983 .loc 1 225 9 is_stmt 1 view .LVU251 + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Speed mode configuration */ + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + 984 .loc 1 228 9 view .LVU252 + 985 0012 B268 ldr r2, [r6, #8] + 986 0014 2146 mov r1, r4 + 987 0016 3846 mov r0, r7 + 988 0018 FFF7FEFF bl LL_GPIO_SetPinSpeed + 989 .LVL82: + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Check Output mode parameters */ + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + 990 .loc 1 231 9 view .LVU253 + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Output mode configuration*/ + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); + 991 .loc 1 234 9 view .LVU254 + 992 001c 3268 ldr r2, [r6] + 993 001e F168 ldr r1, [r6, #12] + 994 .LVL83: + 995 .LBB164: + 996 .LBI164: + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** { + 997 .loc 2 342 22 view .LVU255 + 998 .LBB165: + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** } + 999 .loc 2 344 3 view .LVU256 + 1000 0020 7B68 ldr r3, [r7, #4] + 1001 0022 23EA0203 bic r3, r3, r2 + 1002 0026 01FB02F2 mul r2, r1, r2 + 1003 .LVL84: + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** } + 1004 .loc 2 344 3 is_stmt 0 view .LVU257 + 1005 002a 1343 orrs r3, r3, r2 + 1006 002c 7B60 str r3, [r7, #4] + 1007 .LVL85: + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** + 1008 .loc 2 345 1 view .LVU258 + 1009 002e 16E0 b .L40 + 1010 .L42: + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h **** + 1011 .loc 2 345 1 view .LVU259 + 1012 .LBE165: + 1013 .LBE164: + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + ARM GAS /tmp/ccZKwQMo.s page 63 + + + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Pull-up Pull down resistor configuration*/ + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Check Alternate parameter */ + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Speed mode configuration */ + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** if (POSITION_VAL(currentpin) < 0x00000008U) + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** else + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); + 1014 .loc 1 252 11 is_stmt 1 view .LVU260 + 1015 0030 7269 ldr r2, [r6, #20] + 1016 0032 2146 mov r1, r4 + 1017 0034 3846 mov r0, r7 + 1018 0036 FFF7FEFF bl LL_GPIO_SetAFPin_8_15 + 1019 .LVL86: + 1020 .L41: + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Pin Mode configuration */ + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); + 1021 .loc 1 256 7 view .LVU261 + 1022 003a 7268 ldr r2, [r6, #4] + 1023 003c 2146 mov r1, r4 + 1024 003e 3846 mov r0, r7 + 1025 0040 FFF7FEFF bl LL_GPIO_SetPinMode + 1026 .LVL87: + 1027 .L39: + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** pinpos++; + 1028 .loc 1 258 5 view .LVU262 + 1029 .loc 1 258 11 is_stmt 0 view .LVU263 + 1030 0044 0135 adds r5, r5, #1 + 1031 .LVL88: + 1032 .L38: + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 1033 .loc 1 215 45 is_stmt 1 view .LVU264 + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 1034 .loc 1 215 27 is_stmt 0 view .LVU265 + 1035 0046 3468 ldr r4, [r6] + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 1036 .loc 1 215 45 view .LVU266 + 1037 0048 34FA05F2 lsrs r2, r4, r5 + 1038 004c 1BD0 beq .L45 + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 1039 .loc 1 218 5 is_stmt 1 view .LVU267 + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 1040 .loc 1 218 56 is_stmt 0 view .LVU268 + 1041 004e 0122 movs r2, #1 + 1042 0050 AA40 lsls r2, r2, r5 + ARM GAS /tmp/ccZKwQMo.s page 64 + + + 1043 .LVL89: + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 1044 .loc 1 220 5 is_stmt 1 view .LVU269 + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 1045 .loc 1 220 8 is_stmt 0 view .LVU270 + 1046 0052 1440 ands r4, r2, r4 + 1047 .LVL90: + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 1048 .loc 1 220 8 view .LVU271 + 1049 0054 F6D0 beq .L39 + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 1050 .loc 1 222 7 is_stmt 1 view .LVU272 + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 1051 .loc 1 222 27 is_stmt 0 view .LVU273 + 1052 0056 7368 ldr r3, [r6, #4] + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 1053 .loc 1 222 58 view .LVU274 + 1054 0058 013B subs r3, r3, #1 + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 1055 .loc 1 222 10 view .LVU275 + 1056 005a 012B cmp r3, #1 + 1057 005c D9D9 bls .L46 + 1058 .L40: + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 1059 .loc 1 238 7 is_stmt 1 view .LVU276 + 1060 005e 3269 ldr r2, [r6, #16] + 1061 0060 2146 mov r1, r4 + 1062 0062 3846 mov r0, r7 + 1063 0064 FFF7FEFF bl LL_GPIO_SetPinPull + 1064 .LVL91: + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 1065 .loc 1 240 7 view .LVU277 + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 1066 .loc 1 240 26 is_stmt 0 view .LVU278 + 1067 0068 7368 ldr r3, [r6, #4] + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 1068 .loc 1 240 10 view .LVU279 + 1069 006a 022B cmp r3, #2 + 1070 006c E5D1 bne .L41 + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 1071 .loc 1 243 9 is_stmt 1 view .LVU280 + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 1072 .loc 1 246 9 view .LVU281 + 1073 .LVL92: + 1074 .LBB166: + 1075 .LBI166: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1076 .loc 3 981 31 view .LVU282 + 1077 .LBB167: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1078 .loc 3 983 3 view .LVU283 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1079 .loc 3 988 4 view .LVU284 + 1080 .syntax unified + 1081 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1082 006e 94FAA4F3 rbit r3, r4 + 1083 @ 0 "" 2 + ARM GAS /tmp/ccZKwQMo.s page 65 + + + 1084 .LVL93: + 1085 .loc 3 1001 3 view .LVU285 + 1086 .loc 3 1001 3 is_stmt 0 view .LVU286 + 1087 .thumb + 1088 .syntax unified + 1089 .LBE167: + 1090 .LBE166: + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 1091 .loc 1 246 13 discriminator 2 view .LVU287 + 1092 0072 B3FA83F3 clz r3, r3 + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 1093 .loc 1 246 12 discriminator 2 view .LVU288 + 1094 0076 072B cmp r3, #7 + 1095 0078 DAD8 bhi .L42 + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 1096 .loc 1 248 11 is_stmt 1 view .LVU289 + 1097 007a 7269 ldr r2, [r6, #20] + 1098 007c 2146 mov r1, r4 + 1099 007e 3846 mov r0, r7 + 1100 0080 FFF7FEFF bl LL_GPIO_SetAFPin_0_7 + 1101 .LVL94: + 1102 0084 D9E7 b .L41 + 1103 .LVL95: + 1104 .L45: + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** return (SUCCESS); + 1105 .loc 1 260 3 view .LVU290 + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 1106 .loc 1 261 1 is_stmt 0 view .LVU291 + 1107 0086 0020 movs r0, #0 + 1108 0088 F8BD pop {r3, r4, r5, r6, r7, pc} + 1109 .loc 1 261 1 view .LVU292 + 1110 .cfi_endproc + 1111 .LFE200: + 1113 .section .text.LL_GPIO_StructInit,"ax",%progbits + 1114 .align 1 + 1115 .global LL_GPIO_StructInit + 1116 .syntax unified + 1117 .thumb + 1118 .thumb_func + 1120 LL_GPIO_StructInit: + 1121 .LVL96: + 1122 .LFB201: + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /** + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * whose fields will be set to default values. + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** * @retval None + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** */ + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** { + 1123 .loc 1 271 1 is_stmt 1 view -0 + 1124 .cfi_startproc + 1125 @ args = 0, pretend = 0, frame = 0 + 1126 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccZKwQMo.s page 66 + + + 1127 @ link register save eliminated. + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** /* Reset GPIO init structure parameters values */ + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; + 1128 .loc 1 273 3 view .LVU294 + 1129 .loc 1 273 31 is_stmt 0 view .LVU295 + 1130 0000 4FF6FF73 movw r3, #65535 + 1131 0004 0360 str r3, [r0] + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG; + 1132 .loc 1 274 3 is_stmt 1 view .LVU296 + 1133 .loc 1 274 31 is_stmt 0 view .LVU297 + 1134 0006 0323 movs r3, #3 + 1135 0008 4360 str r3, [r0, #4] + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW; + 1136 .loc 1 275 3 is_stmt 1 view .LVU298 + 1137 .loc 1 275 31 is_stmt 0 view .LVU299 + 1138 000a 0023 movs r3, #0 + 1139 000c 8360 str r3, [r0, #8] + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 1140 .loc 1 276 3 is_stmt 1 view .LVU300 + 1141 .loc 1 276 31 is_stmt 0 view .LVU301 + 1142 000e C360 str r3, [r0, #12] + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** GPIO_InitStruct->Pull = LL_GPIO_PULL_NO; + 1143 .loc 1 277 3 is_stmt 1 view .LVU302 + 1144 .loc 1 277 31 is_stmt 0 view .LVU303 + 1145 0010 0361 str r3, [r0, #16] + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** GPIO_InitStruct->Alternate = LL_GPIO_AF_0; + 1146 .loc 1 278 3 is_stmt 1 view .LVU304 + 1147 .loc 1 278 31 is_stmt 0 view .LVU305 + 1148 0012 4361 str r3, [r0, #20] + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c **** } + 1149 .loc 1 279 1 view .LVU306 + 1150 0014 7047 bx lr + 1151 .cfi_endproc + 1152 .LFE201: + 1154 .text + 1155 .Letext0: + 1156 .file 5 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 1157 .file 6 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 1158 .file 7 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + ARM GAS /tmp/ccZKwQMo.s page 67 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_ll_gpio.c + /tmp/ccZKwQMo.s:20 .text.LL_GPIO_SetPinSpeed:00000000 $t + /tmp/ccZKwQMo.s:25 .text.LL_GPIO_SetPinSpeed:00000000 LL_GPIO_SetPinSpeed + /tmp/ccZKwQMo.s:97 .text.LL_GPIO_SetPinPull:00000000 $t + /tmp/ccZKwQMo.s:102 .text.LL_GPIO_SetPinPull:00000000 LL_GPIO_SetPinPull + /tmp/ccZKwQMo.s:172 .text.LL_GPIO_SetAFPin_0_7:00000000 $t + /tmp/ccZKwQMo.s:177 .text.LL_GPIO_SetAFPin_0_7:00000000 LL_GPIO_SetAFPin_0_7 + /tmp/ccZKwQMo.s:247 .text.LL_GPIO_SetAFPin_8_15:00000000 $t + /tmp/ccZKwQMo.s:252 .text.LL_GPIO_SetAFPin_8_15:00000000 LL_GPIO_SetAFPin_8_15 + /tmp/ccZKwQMo.s:323 .text.LL_GPIO_SetPinMode:00000000 $t + /tmp/ccZKwQMo.s:328 .text.LL_GPIO_SetPinMode:00000000 LL_GPIO_SetPinMode + /tmp/ccZKwQMo.s:398 .text.LL_GPIO_DeInit:00000000 $t + /tmp/ccZKwQMo.s:404 .text.LL_GPIO_DeInit:00000000 LL_GPIO_DeInit + /tmp/ccZKwQMo.s:905 .text.LL_GPIO_DeInit:00000150 $d + /tmp/ccZKwQMo.s:922 .text.LL_GPIO_Init:00000000 $t + /tmp/ccZKwQMo.s:928 .text.LL_GPIO_Init:00000000 LL_GPIO_Init + /tmp/ccZKwQMo.s:1114 .text.LL_GPIO_StructInit:00000000 $t + /tmp/ccZKwQMo.s:1120 .text.LL_GPIO_StructInit:00000000 LL_GPIO_StructInit + +NO UNDEFINED SYMBOLS diff --git a/build/stm32f7xx_ll_gpio.o b/build/stm32f7xx_ll_gpio.o new file mode 100644 index 0000000000000000000000000000000000000000..6482396b4e9fe08608ff348efae1875ebdaddaef GIT binary patch literal 19376 zcmeI4d3aRS-N(TV?S?BNYU9HD{hs?flRJ}0`}TdF_pjb3 z=YGy_IlptxJ?E}-Z_Zh;xX!XHWfn`7s6k1oJL|N?ovBfx!fLWo_ipaEeBh=}9~`*& z)1|u?=PZ5C88KoY=hLaXa~$aR+%>RqPrcewRZz2e^?!UE_(a|N=s)TIsQ5dl4aUD1 z@kb7cf02&ww0QArP77uIb0un|g!50f$njdFnvT1=dh#x=OLjG4U7^==cP&G{Mz0s| zYCwL4UZ1*aDe`Odx^LI<$gkgJh5Hsd`&Kti=&XLvvL{3)bWYJ!THm1cw&+PuU#0Z{ z(UYEjy4Gikp7iu#tFM*dJ}i3D(<`m75FICO zdL??&({J$nTf`rvUOlXoU8Mp@nMgTEc}Sy?3Xvuug^`MpO6;nS@6D(iQJ35Coq_H9 z?j1O9-}u+>?kK98UAOAoyHnV`dLTL?3g*= zzCUr7HRblI(N!Prig#FFwhn*krOKptyu&{HPtRO2ux;->1Dp3|9RBi)gOOhPiwb}I zv!x&Ik2|ZKsWq$B)Xl3OUF}3_B7F;Q%0+J!mw@%Tqf|~IvM*vU%JlC^(Ak+8aX8w6 zjGGB7xQ4LZZ_yTT&xX65>2?6lNUYql!e&~m%w^gy<5|Gjf|WaS{MTU#bnAi{KcOn% zcJ?GxkgDsDGNxl?so;9xjzKvzt6^z;WbhD=_tqjJE90*0A4zv;94W+Wi6%rRU?lM{f6b&8M!d@F1Al_y^$wn&98(1nRY&#Xip8R z?45Kt%XaR9BJ+yi+jeLjG+8xpd)E|Gp(oMf;Cn_6gm}yf?lE#^R!u$p-#2nj=vqeI zYvjDpoh<)>kw=HN(Z0{fg`q6UAKLkP15ce4>SQ-QGWKxjUe@=qk&8nv<-gnc7wc}6 zgwAC70b`#Y+QRam7iTUFp+_mZ#=biA0p*~P+d_*eXPEjrLYzgx zOk?lMs%gUZ4jDNST1o#bhW&UvtB+~J%D$<7Q+$F>|% zXde?A7f@t@5sNh zM=NIu&8Il`K%H+LhN9L8D+nkxmX@z6>v*(a)VI+dSjs3^4XPl(c8#`9W`P~Kx;rex zDa6Hk(^YCr0zs`ECCnE?8AckT1MR3~9G4H>=40j=NWe1t%S7s0R-^5aP3uY~XpGH)TNaTmfb%p6zxaI-r!8x1PF3kHYH zM=IO~VFEH^DO?5N%gD?@@+$2?#^x%9WPO<1#Q?0d0WQZQ=}M!>w6e^ENm%X7R_c8C zO|%;9uVTH-PQWr3mg}%5+&IKi3(Lc(`GFx8Zj(`n_SR`sC6%pVPb2rlE3@E!{KAkQ)(y4Ue>NL8ob-!mKZHCLnWF%T`o}jF+ zx=)%&--Y?AWTdrp;c64z&T`*3k$wc1A0#8uYU^P?+Z~f3ZTc0=JeYWGx`ZxVU4vw8 zbdRPRd-n=lUP?xy)m}uGO>VP^v2{%ezKN89N$Mhb+lf|tHC--p zZ!?h&f_Wlc^mclPE?hl9w@ck!CejSJR3szOYOkZqW$s=R=~$Q-B_lmg7q0$5w=3NV z*nxEKB5-L=Mxxcej4oHX^XS5{TL<&nWTbcK!qouXwz_R5(xq_uW-=13_V?&=y?cR) zbPLSel970PvAG(BWNmYQXd?X#E0YTxuaSQQ}vl(y?rdp^+I(zQn5a!ueVoGc?}d-B2DAL68nU=LL_D5 zf@K;q`oQ%lTz-zE4_q%I^E{F|goO@fA+Dw%v5+qCF6?ZBE--;Rn+`tZXd6yPNYlBa zl|pavaOE}q2z!pd=||Z0Y~?aIEkW{{euRAjm1je-4oNqiW2d;nh$_3xc3wA4-wv0X zk#tKQK<0iVujxGQDz3svETo(M4D35ifdOPbW&t(jR~*YXFeH@N^jz#h7LVIr)8DXW z`J4WRwUDi>fKw?_@l6m=dzI{RGX*t;m)dr|ug5zP&f8cN!S4kk%sAUf#obhNZo-2aH&DkJw6GURY=427=?5JeY!IRu0iH%7Ep&igbC(6 z=S;TP6Q_s=NQmW>O7bbZ;OOfd^e5k%HliTg88LChieSFgXysw1+Qlk6`zuhwbF6Yk z%+3CC_MGhc0_+|~D#8^9^fPE#^#vAm8AULaW8P&JSlQVq;?BvYK9uW4fLLEJ8@p5% z6q%mgQ)EjW+5?xY0qZN-*>Lu%WsKYs#F&KGBP2GOL;XkzrCZ0?c~V(YkzZyVlcRfp z=!fRyTcfP1tgEVXSbCJ}YnhGG1tZaK_HT5u6apQZQ(vIV1*O~=DW@y3gFmjuCL24` zx1B^c?jWn8pwYU&I-A8;WuKURf^K!8t11e_XZ*~;{Dg}(Ss0HBy*Vdt*<>j@>+))} zYmzbG+%Rm*Opgvu*0>@#Sl{F!TI>{M*5FnN>t+@CHwWgw-y@~}Q{k8#K#wiAAdJy2k&P-70}~f>Q>U+KZt?QGY)e^2L9$c>K^IG%kYa}5 zc`O_BSZO?XXy(B>56M>3Zy>!OE0EI*o4|!`j6gTC4#`r>8-e9WL0r2h)Px(DKi@N9 zZ59jrj>6#xB~}njwmJiASuCT4gV8A!Mz##eQp*OFp87DYZY1boD_*ObC5(($F1ami zs|U&$5*m%Qw^&qo$|j@xS6GWe7z2XaB}?sf_Ngy@H2ouW1LadZGjVE~nKEu%Sejrj z{G};h?3sy6(#({%d1m64G&AJ~Ju~r8nwj!%Ju~rqnwj!jo|$+j%}hCf351ptyx#P; zobn{kOzBucGZVZr^qVR3E(^g4-dg$1s9G;(aw^45sK00p__^*tHXo;%}F z%Smgiilo-onv;fTIXI_jZKcnb8qOJ8`L!IWOS!_cD`L6-ydutd8y5=qw~J!Azuw)>l+5B8oi zrH7N?7xsJ!reW*1XkqdPh4}COB{vJVPI6GbV21vC{4j(5zvkz1nV&o&nS}$yC7nE8 za4~wGqquDGpdSoNHhEs+j>NN(Sx!SHhGec8jD8a`jAJeqjNY7Ewn4!&idpVPhUbw7 zk$Cnn%M-}_2FY9(82ulR*^Oi_2#nsG2F#U!(VOGFxdbqJb6hv)exoTipx^8R?NysNXNd`)X>c_h|d+SA(;EsaK6I?F3&lvS2h zly{1!slY2=8(rJk8bxykTa=8c;)(7VmF;X~S6B0zzRupVR(4{jx`T(!*6w&`yczYE zb)fgDUM>A`XyFu3wBg4? zb6+6rI-}jdIM;D<%Ys(G#?P9zbKhAO%|Y0&A8HTK4!^*$t~K4ZF)aQH-bkt7U1!(| zJ~I`(>kL}~>{3DbkP7Yy_(Z0W(R!&dEPAU9|Xx~0?;VZ@M{*=Ny zL@NXMMa|wSZg-^=epC+WSZH0Z1dyA!d$m4>k=9OKSL)(uX_ZfJ$wjNlY)n;UksC^>m$C%F^g0Vx!$ z7^4r#uesc5e1~Mq&DBl%=9!k8!(17vnvMf@PCIwQvXq`)qBjT*-E96mVR;&hMD}PE z*%o5VUsPSOxM9KZjjFG+r>{4zV$pbiSK`1YQk-ealV=;>*=_OS=7kOQOPlL^Iupy+ z_eE=??P_UL!-55P*<^l0bwy(no<+fll{PPIY^Z3i>y5QW8>8`PLP1%{cEme+V~H@| zk*Ti5+awMBU0rySQy4TYF zL|?yd5o?*@^>=Ngt3RrA%*F*x3mR80sI5@_sCRZV8iUrdF}{+fb4`g@e`|tWWLI=s zYNJ|Qy8Oh31?VZNU|D0;wyxfuHDSGC&l*-VV3Q=p1+iFftSJ#m^v6|WO--}ecC|If zv3(UvGL>q{(puKgP+h6FWpi_5b^Y>WP2M)qTdcgJw>w(i9&L-1FR5=>UfvjK>+Egl z=uPzYbhb7(^|!>MvGz!7v^f@Oi^R$oMth>MNTN5^+)z`U<_t}9yth5^)krMrwYjag zzojecuXcVN2BUd;^DNch6YpHp6KxB(c0^*jrFu|(y1`A6^yN0;rk_!XZJ(S%-j*JW zNH5M3-E|!$B>*Og9!+lorI_O0w&jG0#7|eP{jpfICxIES<9YMJOoHj`7pjpN+8FJM zM&dF@jZdXAxf#ja%w+D!WbP>cHbU)9ebH!}?%+Dstf!c#Yg$oLv!JO-Eof|9+Nkuj zri1P(GBeDsW9GiM!DlyD9I5B3*9C1flV^TcA{y(7B(Q%hUfeXl-rIX>j`OCE6gYlG zxTa!O*t^ILS5B{-Q89h`oN#G(YhVAoR_ut;b*0_2ASXKdyIa6^=-d0&9$DH}aTLX_ z-bkVp*U9rR+HFuoVyzwXa0R_~R z@Frybh`=Shd-%WTdGqp*;^au31aB7kAjK@a*_%J2aC7in_q@RQ&ILAFbJy&7i{JO^0uBaEmd$V?V+@LVjl{aHyHGY&>L)$Sj0+VLB!Z*kN}pG13Jnmj5^_Rnbga~2IQjvg() zJYi5k&Qasj1!(9Uu51tmi(~)<4Gbcme zDaxlBJbesN>O-7Q%VRiC`o(R@W2>BgjZ@00*>|?qTOg zFz!>rSA}m0`M`$uBZNzYap7j+&BA+xj|!g^{!zGB=-`=wU4&nsg;Rwygf+q@VXH7M z+${XI@MhsX!bgSA3jZkFD=grf9jJe*aHep9kT0#$zDBrSc!ls9;Y~um4oCl|gnX%u z@^0bZg_(G&LVcldny`$-pjQfy5&cSG3pq}ycHwE{L3r>d_H#tuEWA+k-xm2Q;dP?F zRpjpr?-V^>3uD}eg^!V_cc<_f;qS%%C*eE7_l2L5C}-i2O!6%-60Z^H_~V6Bgog;r zg?!hG?U+ZRT(z)HxKivV30sA0gxw^{T_C(k_*3C?!o4KMV?T+*or4{d)Nh19Kan!p zF`63qM^QA2Ee6fE+c&YFPvGa{A`u#xk zcaw|1M7T`2ibVe+B;MYM3OmIf7yBh5 ze@l3k=x-MJR^go_;@m6ziSP-rKP`Mg_=@mPB+Bg;z9alZ?E8h8@ZomI5f+eWKi@O6 zF(>#25?L(vGO^c-yhPY2`cp-25uQ$>e4j8OJWuQw3BM)0Qg|bYa@&Qs3GWm81Hwmz zJA_Y@X#Wc&j^VEeUlaS^#2&zf7W8>A@+XZ*M*ye7m;Yk)xzzPkA185BGJDs!mEV1ywvAsTqbCuxthEq z;d#4QSRyPJ>g!+F>qI_QxJ=g3j5+1Mb z5bEo2$Uhc&hww?^Z-mba|18`s+#}p41fDPk6ELGU1KFZNl#heQ|-V|Cz`Zuj3(S z3Uh?~kcWDHyhk1-oGY9!)b|&#^OGL>oh72QZXp3Hh}PWqwdbMubrzzhR;NY#~2Z zp{(yeKz^A*`F0^cL81I}A-^}F{F0C#mQda!)b|gNLvo$Y&qZj*`@5R_K7{fd;c+C+ z=Szhr2u~LF3gf~vg+Z#yWzDtuR{?=PSq5czWb>wegOCo(_W;Q4uv@b5x>{SUpq?g#aCKR5|x=^qyI^9{;X zLVdjtSzqsi{BDDGeVq^T(+$e{Iv>>6^`O442d@+RjY598LH~z@J4u{xpAo(!{BPkN z;XdJ~LOfE_<@oUh%j@fS@KBKt7xJqM+Ute<@PhKGLVjdHxnFp;P+z}8&+jg1zg~!G zq3ntB208k{=eQi7Fo}6nLSnw_=b|V#n=w$f-$PL2f!qvhyVTVv(N1)s~kcgA5$2JZ{KnX0A&K$Q z&;7tKWsF;~u!O|;>F0sqbjsK+e1VIcO=3Kc7FLlM*IMCH67}CnqTYO-S5Z%lL_PX> z9pYBXd8(Gj8^kN){)#xLLfKPf9w5#UB2Om~uU6zmB;uYT@@f+C6C&$zL_HUaY{pHG z6XM@UJ?ec>?2nL~pJnm&-HAvGn234oFgg5?l~85;*-4eP#N(=riZb)a*#D$@IE(&C zb%2szE=_PF49HYHRUUX6CBP}hl z=vw8ocJ;RU#YimDvnGn|!1}y0Lp5EUJy8=88&Z|E_I7vUhf{y4_E@AFPV*a=ltmJW zSZ7Or0%8B@1&1Yt>878#v(QYgd<&+YUW%}$AEusO(*0=Tawrm}+CTK;+)S^R^VBS+ z-a07!er=G4^J`A?yW$J{&P?;;v4p>0nZ?w5B^3U8KZHD7y+2Cx<1v80-w?kSTA2*HDw^Gzvbb1tEmjKv5ighyRra&tUwmy$CqDI z>cx*Y{L-BDB6PA|-UFI43{eAzRm{j@Y(;7Dj;{93pNz*}@Jv5=EH-5r;#xTHKGG~E z%VW2{edi+H>(DXYXe1MlA5@q!jPWMERp4`6vlv?)GX8jNwcc1W9>>qbTPg9(oLhB> zQs1Rf7RFF#Pjb*Fzbc%O%F91JN^bJ_$kLUB-YDuW}W8Pf~>ltOeyYLW-;+_T1xRNUZB)B Jj1e}I{U5M`QRe^v literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_ll_rcc.d b/build/stm32f7xx_ll_rcc.d new file mode 100644 index 0000000..2860358 --- /dev/null +++ b/build/stm32f7xx_ll_rcc.d @@ -0,0 +1,70 @@ +build/stm32f7xx_ll_rcc.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/build/stm32f7xx_ll_rcc.lst b/build/stm32f7xx_ll_rcc.lst new file mode 100644 index 0000000..b0ef13f --- /dev/null +++ b/build/stm32f7xx_ll_rcc.lst @@ -0,0 +1,11469 @@ +ARM GAS /tmp/cc42qbQx.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_ll_rcc.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c" + 19 .section .text.LL_RCC_DeInit,"ax",%progbits + 20 .align 1 + 21 .global LL_RCC_DeInit + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 LL_RCC_DeInit: + 27 .LFB295: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @file stm32f7xx_ll_rcc.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief RCC LL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * This software is licensed under terms that can be found in the LICENSE file in + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** ****************************************************************************** + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(USE_FULL_LL_DRIVER) + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Includes ------------------------------------------------------------------*/ + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #include "stm32f7xx_ll_rcc.h" + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #ifdef USE_FULL_ASSERT + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #include "stm32_assert.h" + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #else + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define assert_param(expr) ((void)0U) + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** @addtogroup STM32F7xx_LL_Driver + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @{ + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(RCC) + ARM GAS /tmp/cc42qbQx.s page 2 + + + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** @addtogroup RCC_LL + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @{ + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Private types -------------------------------------------------------------*/ + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Private variables ---------------------------------------------------------*/ + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Private constants ---------------------------------------------------------*/ + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Private macros ------------------------------------------------------------*/ + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** @addtogroup RCC_LL_Private_Macros + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @{ + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE) \ + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** || ((__VALUE__) == LL_RCC_USART6_CLKSOURCE)) + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \ + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE) \ + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** || ((__VALUE__) == LL_RCC_UART7_CLKSOURCE) \ + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** || ((__VALUE__) == LL_RCC_UART8_CLKSOURCE)) + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(I2C4) + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \ + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE)) + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #else + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* I2C4 */ + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE)) + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \ + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE)) + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(SDMMC2) + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE) \ + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** || ((__VALUE__) == LL_RCC_SDMMC2_CLKSOURCE)) + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #else + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE)) + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* SDMMC2 */ + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE)) + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(DFSDM1_Channel0) + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE)) + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURC + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* DFSDM1_Channel0 */ + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE)) + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + ARM GAS /tmp/cc42qbQx.s page 3 + + + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(CEC) + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE)) + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* CEC */ + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(DSI) + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE)) + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* DSI */ + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(LTDC) + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE)) + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* LTDC */ + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(SPDIFRX) + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE)) + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* SPDIFRX */ + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @} + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Private function prototypes -----------------------------------------------*/ + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** @defgroup RCC_LL_Private_Functions RCC Private functions + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @{ + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_GetSystemClockFreq(void); + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLL_GetFreqDomain_SYS(void); + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLL_GetFreqDomain_SAI(void); + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLL_GetFreqDomain_48M(void); + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(DSI) + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLL_GetFreqDomain_DSI(void); + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* DSI */ + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void); + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLSAI_GetFreqDomain_48M(void); + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(LTDC) + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void); + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* LTDC */ + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void); + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void); + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(SPDIFRX) + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void); + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* SPDIFRX */ + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @} + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Exported functions --------------------------------------------------------*/ + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** @addtogroup RCC_LL_Exported_Functions + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @{ + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** @addtogroup RCC_LL_EF_Init + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @{ + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + ARM GAS /tmp/cc42qbQx.s page 4 + + + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Reset the RCC clock configuration to the default reset state. + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @note The default reset state of the clock configuration is given below: + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - HSI ON and used as system clock source + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - HSE, PLL, PLLI2S, PLLSAI OFF + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - AHB, APB1 and APB2 prescaler set to 1. + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - CSS, MCO OFF + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - All interrupts disabled + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @note This function doesn't modify the configuration of the + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - Peripheral clocks + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - LSI, LSE and RTC clocks + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval An ErrorStatus enumeration value: + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - SUCCESS: RCC registers are de-initialized + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - ERROR: not applicable + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** ErrorStatus LL_RCC_DeInit(void) + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 28 .loc 1 163 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 8 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 0000 82B0 sub sp, sp, #8 + 34 .LCFI0: + 35 .cfi_def_cfa_offset 8 + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** __IO uint32_t vl_mask; + 36 .loc 1 164 3 view .LVU1 + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Set HSION bit */ + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** LL_RCC_HSI_Enable(); + 37 .loc 1 167 3 view .LVU2 + 38 .LBB234: + 39 .LBI234: + 40 .file 2 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @file stm32f7xx_ll_rcc.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Header file of RCC LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * This software is licensed under terms that can be found in the LICENSE file in + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** ****************************************************************************** + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #ifndef __STM32F7xx_LL_RCC_H + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __STM32F7xx_LL_RCC_H + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #ifdef __cplusplus + ARM GAS /tmp/cc42qbQx.s page 5 + + + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** extern "C" { + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Includes ------------------------------------------------------------------*/ + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #include "stm32f7xx.h" + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @addtogroup STM32F7xx_LL_Driver + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC) + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL RCC + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Private types -------------------------------------------------------------*/ + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Private variables ---------------------------------------------------------*/ + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Variables RCC Private Variables + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_DCKCFGR1_PLLSAIDIVR) + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16}; + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_DCKCFGR1_PLLSAIDIVR */ + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Private constants ---------------------------------------------------------*/ + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Private macros ------------------------------------------------------------*/ + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Macros RCC Private Macros + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /*USE_FULL_LL_DRIVER*/ + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Exported types ------------------------------------------------------------*/ + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Types RCC Exported Types + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief RCC Clocks Frequency Structure + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** typedef struct + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + ARM GAS /tmp/cc42qbQx.s page 6 + + + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } LL_RCC_ClocksTypeDef; + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */ + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Exported constants --------------------------------------------------------*/ + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Defines used to adapt values of different oscillators + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note These values could be modified in the user environment according to + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * HW set-up. + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined (HSE_VALUE) + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */ + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* HSE_VALUE */ + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined (HSI_VALUE) + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* HSI_VALUE */ + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined (LSE_VALUE) + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* LSE_VALUE */ + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined (LSI_VALUE) + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* LSI_VALUE */ + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined (EXTERNAL_CLOCK_VALUE) + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* EXTERNAL_CLOCK_VALUE */ + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined (EXTERNAL_SAI1_CLOCK_VALUE) + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined (EXTERNAL_SAI2_CLOCK_VALUE) + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* EXTERNAL_SAI2_CLOCK_VALUE */ + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Flags defines which can be used with LL_RCC_WriteReg function + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + ARM GAS /tmp/cc42qbQx.s page 7 + + + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */ + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */ + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Flags defines which can be used with LL_RCC_ReadReg function + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */ + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */ + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_IT IT Defines + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving cap + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high drivi + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low drivin + ARM GAS /tmp/cc42qbQx.s page 8 + + + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving ca + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ + ARM GAS /tmp/cc42qbQx.s page 9 + + + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1 + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2 + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFG + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFG + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFG + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFG + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */ + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */ + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE cl + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */ + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE cl + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE cl + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */ + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE cl + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE cl + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE cl + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1| + ARM GAS /tmp/cc42qbQx.s page 10 + + + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */ + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE cl + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE cl + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE cl + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1| + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE cl + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1| + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2| + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2| + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2| + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for th + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be pro + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */ + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | 0x00000000U + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | 0x00000000U + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | 0x00000000U + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | 0x00000000U + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_UARTx_CLKSOURCE Peripheral UART clock source selection + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + ARM GAS /tmp/cc42qbQx.s page 11 + + + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | 0x00000000U) + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_ + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_ + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_ + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | 0x00000000U) + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_ + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_ + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_ + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | 0x00000000U) + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_ + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_ + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_ + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | 0x00000000U) + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_ + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_ + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_ + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C1SEL|0x00000000U) /*!< PCLK1 + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_0 + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_1 + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C2SEL|0x00000000U) /*!< PCLK1 + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_0 + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_1 + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C3SEL|0x00000000U) /*!< PCLK1 + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_0 + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_1 + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(I2C4) + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C4_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C4SEL|0x00000000U) /*!< PCLK1 + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C4_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_0 + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C4_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_1 + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* I2C4 */ + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LP + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock u + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock u + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTI + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI1SEL | 0x00000000U) + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_ + ARM GAS /tmp/cc42qbQx.s page 12 + + + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_ + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_SAI1SEL_PLLSRC_SUPPORT) + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */ + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI2SEL | 0x00000000U) + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_ + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_ + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_SAI2SEL_PLLSRC_SUPPORT) + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */ + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SDMMCx_CLKSOURCE Peripheral SDMMC clock source selection + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | 0x00000000U) + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | (RCC_DCKCFGR2_SD + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SDMMC2) + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | 0x00000000U) + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | (RCC_DCKCFGR2_SD + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SDMMC2 */ + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as RNG clock s + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI clock used as RNG cloc + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as USB clock s + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI1 clock used as USB clo + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI) + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR2_DSISEL /*!< PLL clock used as DSI byte lan + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */ + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(CEC) + ARM GAS /tmp/cc42qbQx.s page 13 + + + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE_LSE 0x00000000U /*!< LSE oscillator clock + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 RCC_DCKCFGR2_CECSEL /*!< HSI oscillator clock + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* CEC */ + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock u + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator cl + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DFSDM1_Channel0) + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /*!< SAI1 clock used as D + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL /*!< SAI2 clock used as D + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL /*!< System clock used as + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DFSDM1_Channel0 */ + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE RCC_DCKCFGR2_USART1SEL /*!< USART1 Clock source selectio + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE RCC_DCKCFGR2_USART2SEL /*!< USART2 Clock source selectio + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE RCC_DCKCFGR2_USART3SEL /*!< USART3 Clock source selectio + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE RCC_DCKCFGR2_USART6SEL /*!< USART6 Clock source selectio + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + ARM GAS /tmp/cc42qbQx.s page 14 + + + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_UARTx Peripheral UART get clock source + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE RCC_DCKCFGR2_UART4SEL /*!< UART4 Clock source selection + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE RCC_DCKCFGR2_UART5SEL /*!< UART5 Clock source selection + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE RCC_DCKCFGR2_UART7SEL /*!< UART7 Clock source selection + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE RCC_DCKCFGR2_UART8SEL /*!< UART8 Clock source selection + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2Cx Peripheral I2C get clock source + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE RCC_DCKCFGR2_I2C1SEL /*!< I2C1 Clock source selection * + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE RCC_DCKCFGR2_I2C2SEL /*!< I2C2 Clock source selection * + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE RCC_DCKCFGR2_I2C3SEL /*!< I2C3 Clock source selection * + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(I2C4) + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C4_CLKSOURCE RCC_DCKCFGR2_I2C4SEL /*!< I2C4 Clock source selection * + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* I2C4 */ + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selectio + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR1_SAI1SEL /*!< SAI1 Clock source selection */ + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR1_SAI2SEL /*!< SAI2 Clock source selection */ + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SDMMCx Peripheral SDMMC get clock source + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC1_CLKSOURCE RCC_DCKCFGR2_SDMMC1SEL /*!< SDMMC1 Clock source selectio + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SDMMC2) + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC2_CLKSOURCE RCC_DCKCFGR2_SDMMC2SEL /*!< SDMMC2 Clock source selectio + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SDMMC2 */ + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + ARM GAS /tmp/cc42qbQx.s page 15 + + + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source sel + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< RNG Clock source selection */ + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< USB Clock source selection */ + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(CEC) + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */ + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* CEC */ + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S Clock source selection */ + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DFSDM1_Channel0) + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR1_ADFSDM1SEL /*!< DFSDM Audio Clock source se + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source + 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR1_DFSDM1SEL /*!< DFSDM Clock source selection + 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DFSDM1_Channel0 */ + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI) + ARM GAS /tmp/cc42qbQx.s page 16 + + + 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source + 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR2_DSISEL /*!< DSI Clock source selection */ + 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */ + 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(LTDC) + 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR1_PLLSAIDIVR /*!< LTDC Clock source selection + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* LTDC */ + 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SPDIFRX) + 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source + 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SPDIFRX1_CLKSOURCE RCC_PLLI2SCFGR_PLLI2SP /*!< SPDIFRX Clock source select + 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SPDIFRX */ + 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock + 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used a + 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used a + 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divide + 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection + 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice + 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR1_TIMPRE /*!< Timers clock to four + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source + 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL + 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL e + 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + ARM GAS /tmp/cc42qbQx.s page 17 + + + 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor + 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI divisio + 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI + 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI divisio + 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI + 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI + 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_P + 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI divisio + 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI + 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI + 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_P + 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI + 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P + 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P + 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P + 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI divisio + 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI + 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI + 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_P + 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI + 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P + 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P + 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P + 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI + 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI divisio + 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI + 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI + 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_P + 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI + 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P + 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P + 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P + 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI + 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI + 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + ARM GAS /tmp/cc42qbQx.s page 18 + + + 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLCFGR_PLLR) + 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR) + 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL d + 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL d + 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL d + 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL d + 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL d + 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL d + 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLCFGR_PLLR */ + 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) + 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for + 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for + 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for + 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PL + 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) + 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL di + 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL di + 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL di + 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL di + 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL di + 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_ + 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL di + 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL di + 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL di + 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_ + 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL di + 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_ + 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_ + 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_ + 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + ARM GAS /tmp/cc42qbQx.s page 19 + + + 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection + 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spe + 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spect + 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ) + 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division fact + 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) + 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division fact + 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) + 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) + 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RC + 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division fact + 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) + 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) + 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RC + 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) + 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RC + 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RC + 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RC + 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ) + 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division f + 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR1_PLLI2SDIVQ_0 /*!< PLLI2S division f + 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR1_PLLI2SDIVQ_1 /*!< PLLI2S division f + 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) + 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR1_PLLI2SDIVQ_2 /*!< PLLI2S division f + 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) + 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) + 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | + 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR1_PLLI2SDIVQ_3 /*!< PLLI2S division f + 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_0) + 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1) + 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | + 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2) + 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | + 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | + 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | + 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR1_PLLI2SDIVQ_4 /*!< PLLI2S division f + 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_0) + 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1) + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | + 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2) + ARM GAS /tmp/cc42qbQx.s page 20 + + + 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | + 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | + 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | + 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3) + 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | + 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | + 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | + 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | + 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | + 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | + 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | + 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR) + 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 + 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) + 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 + 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) + 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) + 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RC + 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLI2SCFGR_PLLI2SP) + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP) + 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PL + 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division fact + 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division fact + 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) + 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLI2SCFGR_PLLI2SP */ + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ) + 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division fact + 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) + 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division fact + 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) + 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) + 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RC + 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division fact + 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) + 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) + 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RC + 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) + 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RC + 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RC + ARM GAS /tmp/cc42qbQx.s page 21 + + + 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RC + 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ) + 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for + 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR1_PLLSAIDIVQ_0 /*!< PLLSAI division f + 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR1_PLLSAIDIVQ_1 /*!< PLLSAI division f + 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) + 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR1_PLLSAIDIVQ_2 /*!< PLLSAI division f + 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) + 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) + 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | + 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR1_PLLSAIDIVQ_3 /*!< PLLSAI division f + 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_0) + 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1) + 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | + 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2) + 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | + 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | + 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | + 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR1_PLLSAIDIVQ_4 /*!< PLLSAI division fa + 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_0) + 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1) + 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | + 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2) + 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | + 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | + 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | + 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3) + 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | + 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | + 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | + 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | + 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | + 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | + 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLSAICFGR_PLLSAIR) + 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR) + 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 + 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) + 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 + 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) + 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) + 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RC + 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + ARM GAS /tmp/cc42qbQx.s page 22 + + + 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLSAICFGR_PLLSAIR */ + 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_DCKCFGR1_PLLSAIDIVR) + 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR) + 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for P + 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR1_PLLSAIDIVR_0 /*!< PLLSAI division fac +1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR1_PLLSAIDIVR_1 /*!< PLLSAI division fac +1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVR_1 | RCC_DCKCFGR1_PLLSAIDIVR_0) +1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_DCKCFGR1_PLLSAIDIVR */ +1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP) +1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for +1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division fact +1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division fact +1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) +1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Exported macro ------------------------------------------------------------*/ +1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros +1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros +1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Write a value in RCC register +1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __REG__ Register to be written +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __VALUE__ Value to be written in the register +1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) +1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Read a value in RCC register +1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __REG__ Register to be read +1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Register value +1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + ARM GAS /tmp/cc42qbQx.s page 23 + + +1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies +1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLCLK frequency on system domain +1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); +1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 + ARM GAS /tmp/cc42qbQx.s page 24 + + +1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLN__ Between 50 and 432 +1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLP__ This parameter can be one of the following values: +1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_2 +1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_4 +1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_6 +1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_8 +1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) +1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ( +1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U)) +1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain +1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); +1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 + ARM GAS /tmp/cc42qbQx.s page 25 + + +1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLN__ Between 50 and 432 +1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLQ__ This parameter can be one of the following values: +1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_2 +1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_3 +1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_4 +1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_5 +1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_6 +1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_7 +1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_8 +1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_9 +1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_10 +1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_11 +1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_12 +1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_13 +1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_14 +1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_15 +1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) +1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) +1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos )) + ARM GAS /tmp/cc42qbQx.s page 26 + + +1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI) +1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLCLK frequency used on DSI +1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), +1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); +1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 + ARM GAS /tmp/cc42qbQx.s page 27 + + +1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLN__ Between 50 and 432 +1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLR__ This parameter can be one of the following values: +1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_2 +1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_3 +1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_4 +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_5 +1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_6 +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_7 +1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) +1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) +1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) +1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */ +1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLSAI frequency used for SAI1 and SAI2 domains +1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ +1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 + ARM GAS /tmp/cc42qbQx.s page 28 + + +1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLSAIN__ Between 50 and 432 +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLSAIQ__ This parameter can be one of the following values: +1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_2 +1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_3 +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_4 +1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_5 +1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_6 +1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_7 +1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_8 +1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_9 +1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_10 +1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_11 +1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_12 +1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_13 +1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_14 +1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_15 +1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLSAIDIVQ__ This parameter can be one of the following values: +1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 +1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 + ARM GAS /tmp/cc42qbQx.s page 29 + + +1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 +1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 +1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 +1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 +1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 +1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 +1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 +1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 +1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 +1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 +1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 +1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 +1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 +1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 +1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 +1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 +1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 +1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 +1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 +1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 +1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 +1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 +1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 +1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 +1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 +1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 +1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 +1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 +1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 +1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 +1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PLLSAI clock frequency (in Hz) +1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDI +1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCF +1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain +1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ()); +1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 + ARM GAS /tmp/cc42qbQx.s page 30 + + +1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLSAIN__ Between 50 and 432 +1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLSAIP__ This parameter can be one of the following values: +1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIP_DIV_2 +1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIP_DIV_4 +1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIP_DIV_6 +1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIP_DIV_8 +1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PLLSAI clock frequency (in Hz) +1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUT +1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U ) * 2U)) +1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + ARM GAS /tmp/cc42qbQx.s page 31 + + +1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(LTDC) +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain +1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR +1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 + ARM GAS /tmp/cc42qbQx.s page 32 + + +1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLSAIN__ Between 50 and 432 +1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLSAIR__ This parameter can be one of the following values: +1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_2 +1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_3 +1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_4 +1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_5 +1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_6 +1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_7 +1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLSAIDIVR__ This parameter can be one of the following values: +1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 +1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 +1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 +1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 +1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PLLSAI clock frequency (in Hz) +1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAID +1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__P +1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* LTDC */ +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLI2S frequency used for SAI1 and SAI2 domains +1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ +1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 + ARM GAS /tmp/cc42qbQx.s page 33 + + +1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLI2SN__ Between 50 and 432 +1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLI2SQ__ This parameter can be one of the following values: +1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_2 +1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_3 +1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_4 +1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_5 +1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_6 +1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_7 +1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_8 +1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_9 +1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_10 +1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_11 +1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_12 +1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_13 +1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_14 + ARM GAS /tmp/cc42qbQx.s page 34 + + +1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_15 +1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLI2SDIVQ__ This parameter can be one of the following values: +1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 +1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 +1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 +1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 +1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 +1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 +1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 +1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 +1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 +1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 +1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 +1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 +1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 +1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 +1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 +1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 +1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 +1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 +1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 +1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 +1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 +1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 +1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 +1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 +1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 +1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 +1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 +1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 +1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 +1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 +1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 +1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 +1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PLLI2S clock frequency (in Hz) +1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SDI +1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** (((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ__) >> RCC_DCKCF +1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SPDIFRX) +1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain +1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ()); +1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 + ARM GAS /tmp/cc42qbQx.s page 35 + + +1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLI2SN__ Between 50 and 432 +1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLI2SP__ This parameter can be one of the following values: +1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_2 +1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_4 +1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_6 +1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_8 + ARM GAS /tmp/cc42qbQx.s page 36 + + +1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PLLI2S clock frequency (in Hz) +1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__I +1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U)) +1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SPDIFRX */ +1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain +1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ()); +1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 + ARM GAS /tmp/cc42qbQx.s page 37 + + +1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLI2SN__ Between 50 and 432 +1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLI2SR__ This parameter can be one of the following values: +1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_2 +1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_3 +1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_4 +1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_5 +1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_6 +1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_7 +1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PLLI2S clock frequency (in Hz) +1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUT +1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos)) +1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the HCLK frequency +1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) +1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __AHBPRESCALER__ This parameter can be one of the following values: +1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 +1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 +1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 +1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 +1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 +1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 +1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 +1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 +1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 +1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval HCLK clock frequency (in Hz) +1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTabl +1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PCLK1 frequency (ABP1) +1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __HCLKFREQ__ HCLK frequency +1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __APB1PRESCALER__ This parameter can be one of the following values: +1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 +1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 +1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 +1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 +1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 +1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PCLK1 clock frequency (in Hz) + ARM GAS /tmp/cc42qbQx.s page 38 + + +1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[ +1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PCLK2 frequency (ABP2) +1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __HCLKFREQ__ HCLK frequency +1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __APB2PRESCALER__ This parameter can be one of the following values: +1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_1 +1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_2 +1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_4 +1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_8 +1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_16 +1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PCLK2 clock frequency (in Hz) +1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[ +1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Exported functions --------------------------------------------------------*/ +1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions +1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSE HSE +1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable the Clock Security System. +1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS +1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_CSSON); +1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable HSE external oscillator (HSE Bypass) +1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass +1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSEBYP); +1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable HSE external oscillator (HSE Bypass) +1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass +1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None + ARM GAS /tmp/cc42qbQx.s page 39 + + +1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable HSE crystal oscillator (HSE ON) +1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSEON LL_RCC_HSE_Enable +1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Enable(void) +1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSEON); +1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable HSE crystal oscillator (HSE ON) +1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSEON LL_RCC_HSE_Disable +1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Disable(void) +1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Check if HSE oscillator Ready +1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSERDY LL_RCC_HSE_IsReady +1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); +1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI HSI +2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable HSI oscillator +2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSION LL_RCC_HSI_Enable +2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Enable(void) + 41 .loc 2 2010 22 view .LVU3 + 42 .LBB235: +2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSION); + 43 .loc 2 2012 3 view .LVU4 + 44 0002 224A ldr r2, .L7 + 45 0004 1368 ldr r3, [r2] + ARM GAS /tmp/cc42qbQx.s page 40 + + + 46 0006 43F00103 orr r3, r3, #1 + 47 000a 1360 str r3, [r2] + 48 .LBE235: + 49 .LBE234: + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Wait for HSI READY bit */ + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** while(LL_RCC_HSI_IsReady() != 1U) + 50 .loc 1 170 3 view .LVU5 + 51 .L2: + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {} + 52 .loc 1 171 4 view .LVU6 + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {} + 53 .loc 1 170 30 discriminator 1 view .LVU7 + 54 .LBB236: + 55 .LBI236: +2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable HSI oscillator +2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSION LL_RCC_HSI_Disable +2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Disable(void) +2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSION); +2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Check if HSI clock is ready +2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady +2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval State of bit (1 or 0). +2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) + 56 .loc 2 2030 26 view .LVU8 + 57 .LBB237: +2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); + 58 .loc 2 2032 3 view .LVU9 + 59 .loc 2 2032 11 is_stmt 0 view .LVU10 + 60 000c 1F4B ldr r3, .L7 + 61 000e 1B68 ldr r3, [r3] + 62 .LBE237: + 63 .LBE236: + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {} + 64 .loc 1 170 30 discriminator 1 view .LVU11 + 65 0010 13F0020F tst r3, #2 + 66 0014 FAD0 beq .L2 + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Reset CFGR register */ + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** LL_RCC_WriteReg(CFGR, 0x00000000U); + 67 .loc 1 174 3 is_stmt 1 view .LVU12 + 68 0016 1D4B ldr r3, .L7 + 69 0018 0022 movs r2, #0 + 70 001a 9A60 str r2, [r3, #8] + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Read CR register */ + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** vl_mask = LL_RCC_ReadReg(CR); + ARM GAS /tmp/cc42qbQx.s page 41 + + + 71 .loc 1 177 3 view .LVU13 + 72 .loc 1 177 13 is_stmt 0 view .LVU14 + 73 001c 1A68 ldr r2, [r3] + 74 .loc 1 177 11 view .LVU15 + 75 001e 0192 str r2, [sp, #4] + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Reset HSEON, HSEBYP, PLLON, CSSON, PLLI2SON and PLLSAION bits */ + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_PLLSAION + 76 .loc 1 180 3 is_stmt 1 view .LVU16 + 77 0020 0199 ldr r1, [sp, #4] + 78 0022 1B4A ldr r2, .L7+4 + 79 0024 0A40 ands r2, r2, r1 + 80 0026 0192 str r2, [sp, #4] + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Write new value in CR register */ + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** LL_RCC_WriteReg(CR, vl_mask); + 81 .loc 1 183 3 view .LVU17 + 82 0028 019A ldr r2, [sp, #4] + 83 002a 1A60 str r2, [r3] + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Set HSITRIM bits to the reset value*/ + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** LL_RCC_HSI_SetCalibTrimming(0x10U); + 84 .loc 1 186 3 view .LVU18 + 85 .LVL0: + 86 .LBB238: + 87 .LBI238: +2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get HSI Calibration value +2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note When HSITRIM is written, HSICAL is updated with the sum of +2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * HSITRIM and the factory trim value +2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration +2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0xFF +2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); +2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Set HSI Calibration trimming +2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note user-programmable trimming value that is added to the HSICAL +2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note Default value is 16, which, when added to the HSICAL value, +2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * should trim the HSI to 16 MHz +/- 1 % +2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming +2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Value Between Min_Data = 0 and Max_Data = 31 +2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) + 88 .loc 2 2056 22 view .LVU19 + 89 .LBB239: +2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); + 90 .loc 2 2058 3 view .LVU20 + 91 002c 1A68 ldr r2, [r3] + 92 002e 22F0F802 bic r2, r2, #248 + ARM GAS /tmp/cc42qbQx.s page 42 + + + 93 0032 42F08002 orr r2, r2, #128 + 94 0036 1A60 str r2, [r3] + 95 .LVL1: + 96 .loc 2 2058 3 is_stmt 0 view .LVU21 + 97 .LBE239: + 98 .LBE238: + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Wait for PLL READY bit to be reset */ + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** while(LL_RCC_PLL_IsReady() != 0U) + 99 .loc 1 189 3 is_stmt 1 view .LVU22 + 100 .L3: + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {} + 101 .loc 1 190 4 view .LVU23 + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {} + 102 .loc 1 189 30 discriminator 1 view .LVU24 + 103 .LBB240: + 104 .LBI240: +2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get HSI Calibration trimming +2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming +2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Between Min_Data = 0 and Max_Data = 31 +2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); +2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSE LSE +2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable Low Speed External (LSE) crystal. +2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR LSEON LL_RCC_LSE_Enable +2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Enable(void) +2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable Low Speed External (LSE) crystal. +2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR LSEON LL_RCC_LSE_Disable +2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Disable(void) +2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + ARM GAS /tmp/cc42qbQx.s page 43 + + +2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable external clock source (LSE bypass). +2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass +2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable external clock source (LSE bypass). +2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass +2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Set LSE oscillator drive capability +2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note The oscillator is in Xtal mode when it is not in bypass mode. +2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability +2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param LSEDrive This parameter can be one of the following values: +2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_LOW +2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH +2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW +2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_HIGH +2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get LSE oscillator drive capability +2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability +2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_LOW +2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH +2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW +2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_HIGH +2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Check if LSE oscillator Ready +2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady +2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval State of bit (1 or 0). +2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + ARM GAS /tmp/cc42qbQx.s page 44 + + +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); +2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSI LSI +2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable LSI Oscillator +2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CSR LSION LL_RCC_LSI_Enable +2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Enable(void) +2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_LSION); +2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable LSI Oscillator +2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CSR LSION LL_RCC_LSI_Disable +2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Disable(void) +2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Check if LSI is Ready +2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady +2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval State of bit (1 or 0). +2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); +2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_System System +2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure the system clock source +2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR SW LL_RCC_SetSysClkSource +2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI +2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE +2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL +2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None + ARM GAS /tmp/cc42qbQx.s page 45 + + +2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get the system clock source +2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR SWS LL_RCC_GetSysClkSource +2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI +2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE +2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL +2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Set AHB prescaler +2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler +2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 +2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 +2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 +2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 +2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 +2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 +2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 +2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 +2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 +2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Set APB1 prescaler +2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler +2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 +2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 +2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 +2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 +2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 +2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); +2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Set APB2 prescaler + ARM GAS /tmp/cc42qbQx.s page 46 + + +2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler +2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_1 +2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_2 +2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_4 +2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_8 +2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_16 +2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); +2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get AHB prescaler +2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler +2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 +2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 +2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 +2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 +2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 +2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 +2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 +2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 +2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 +2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get APB1 prescaler +2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler +2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 +2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 +2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 +2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 +2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 +2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); +2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get APB2 prescaler +2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler +2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_1 +2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_2 +2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_4 +2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_8 +2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_16 + ARM GAS /tmp/cc42qbQx.s page 47 + + +2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); +2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_MCO MCO +2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure MCOx +2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n +2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * CFGR MCO1PRE LL_RCC_ConfigMCO\n +2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * CFGR MCO2 LL_RCC_ConfigMCO\n +2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * CFGR MCO2PRE LL_RCC_ConfigMCO +2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param MCOxSource This parameter can be one of the following values: +2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSI +2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_LSE +2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSE +2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK +2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK +2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S +2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO2SOURCE_HSE +2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK +2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param MCOxPrescaler This parameter can be one of the following values: +2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_1 +2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_2 +2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_3 +2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_4 +2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_5 +2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO2_DIV_1 +2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO2_DIV_2 +2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO2_DIV_3 +2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO2_DIV_4 +2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO2_DIV_5 +2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << +2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source +2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure USARTx clock source + ARM GAS /tmp/cc42qbQx.s page 48 + + +2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 USART1SEL LL_RCC_SetUSARTClockSource\n +2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 USART2SEL LL_RCC_SetUSARTClockSource\n +2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 USART3SEL LL_RCC_SetUSARTClockSource\n +2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 USART6SEL LL_RCC_SetUSARTClockSource +2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param USARTxSource This parameter can be one of the following values: +2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 +2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK +2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI +2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE +2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 +2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK +2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI +2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE +2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 +2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK +2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI +2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE +2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2 +2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK +2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI +2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE +2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU)); +2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure UARTx clock source +2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 UART4SEL LL_RCC_SetUARTClockSource\n +2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 UART5SEL LL_RCC_SetUARTClockSource\n +2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 UART7SEL LL_RCC_SetUARTClockSource\n +2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 UART8SEL LL_RCC_SetUARTClockSource +2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param UARTxSource This parameter can be one of the following values: +2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 +2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK +2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI +2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE +2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 +2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK +2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI +2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE +2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 +2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK +2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI +2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE +2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 +2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK +2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI +2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE +2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) +2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU)); +2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + ARM GAS /tmp/cc42qbQx.s page 49 + + +2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure I2Cx clock source +2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 I2C1SEL LL_RCC_SetI2CClockSource\n +2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 I2C2SEL LL_RCC_SetI2CClockSource\n +2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 I2C3SEL LL_RCC_SetI2CClockSource\n +2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 I2C4SEL LL_RCC_SetI2CClockSource +2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param I2CxSource This parameter can be one of the following values: +2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 +2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK +2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI +2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 +2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK +2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI +2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 +2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK +2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI +2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*) +2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*) +2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) +2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * +2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * (*) value not defined in all devices. +2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, (I2CxSource & 0xFFFF0000U), (I2CxSource << 16U)); +2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure LPTIMx clock source +2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource +2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param LPTIMxSource This parameter can be one of the following values: +2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 +2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI +2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI +2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE +2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) +2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource); +2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure SAIx clock source +2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 SAI1SEL LL_RCC_SetSAIClockSource\n +2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR1 SAI2SEL LL_RCC_SetSAIClockSource +2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param SAIxSource This parameter can be one of the following values: +2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI +2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S +2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN +2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*) +2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI +2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S +2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN +2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) + ARM GAS /tmp/cc42qbQx.s page 50 + + +2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * +2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * (*) value not defined in all devices. +2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) +2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR1, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U)); +2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure SDMMC clock source +2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_SetSDMMCClockSource\n +2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 SDMMC2SEL LL_RCC_SetSDMMCClockSource +2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param SDMMCxSource This parameter can be one of the following values: +2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK +2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK +2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*) +2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*) +2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * +2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * (*) value not defined in all devices. +2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource) +2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, (SDMMCxSource & 0xFFFF0000U), (SDMMCxSource << 16U)); +2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure 48Mhz domain clock source +2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource +2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param CK48MxSource This parameter can be one of the following values: +2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL +2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI +2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource) +2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource); +2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure RNG clock source +2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource +2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param RNGxSource This parameter can be one of the following values: +2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL +2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI +2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) +2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource); +2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure USB clock source +2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource +2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param USBxSource This parameter can be one of the following values: + ARM GAS /tmp/cc42qbQx.s page 51 + + +2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLL +2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI +2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource); +2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(CEC) +2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure CEC clock source +2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource +2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE +2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 +2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source) +2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source); +2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* CEC */ +2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure I2S clock source +2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource +2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S +2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN +2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source) +2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source); +2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI) +2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure DSI clock source +2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 DSISEL LL_RCC_SetDSIClockSource +2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY +2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL +2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) +2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, Source); +2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */ +2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DFSDM1_Channel0) +2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure DFSDM Audio clock source +2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource +2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: + ARM GAS /tmp/cc42qbQx.s page 52 + + +2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 +2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 +2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source) +2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, Source); +2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure DFSDM Kernel clock source +2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_SetDFSDMClockSource +2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 +2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK +2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source) +2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, Source); +2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DFSDM1_Channel0 */ +2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get USARTx clock source +2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 USART1SEL LL_RCC_GetUSARTClockSource\n +2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 USART2SEL LL_RCC_GetUSARTClockSource\n +2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 USART3SEL LL_RCC_GetUSARTClockSource\n +2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 USART6SEL LL_RCC_GetUSARTClockSource +2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param USARTx This parameter can be one of the following values: +2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE +2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE +2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE +2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART6_CLKSOURCE +2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 +2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK +2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI +2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE +2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 +2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK +2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI +2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE +2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 +2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK +2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI +2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE +2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2 +2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK +2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI +2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE +2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USARTx) | (USARTx << 16U)); +2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + ARM GAS /tmp/cc42qbQx.s page 53 + + +2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get UARTx clock source +2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 UART4SEL LL_RCC_GetUARTClockSource\n +2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 UART5SEL LL_RCC_GetUARTClockSource\n +2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 UART7SEL LL_RCC_GetUARTClockSource\n +2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 UART8SEL LL_RCC_GetUARTClockSource +2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param UARTx This parameter can be one of the following values: +2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART4_CLKSOURCE +2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART5_CLKSOURCE +2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART7_CLKSOURCE +2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART8_CLKSOURCE +2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 +2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK +2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI +2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE +2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 +2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK +2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI +2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE +2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 +2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK +2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI +2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE +2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 +2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK +2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI +2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE +2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) +2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR2, UARTx) | (UARTx << 16U)); +2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get I2Cx clock source +2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 I2C1SEL LL_RCC_GetI2CClockSource\n +2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 I2C2SEL LL_RCC_GetI2CClockSource\n +2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 I2C3SEL LL_RCC_GetI2CClockSource\n +2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 I2C4SEL LL_RCC_GetI2CClockSource +2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param I2Cx This parameter can be one of the following values: +2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE +2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C2_CLKSOURCE +2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE +2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C4_CLKSOURCE (*) +2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 +2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK +2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI +2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 +2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK +2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI +2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 +2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK +2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI +2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*) +2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*) + ARM GAS /tmp/cc42qbQx.s page 54 + + +2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) +2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * +2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * (*) value not defined in all devices. +2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)((READ_BIT(RCC->DCKCFGR2, I2Cx) >> 16U) | I2Cx); +2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get LPTIMx clock source +2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource +2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param LPTIMx This parameter can be one of the following values: +2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE +2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 +2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI +2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI +2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE +2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) +2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)); +2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get SAIx clock source +2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 SAI1SEL LL_RCC_GetSAIClockSource\n +2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR1 SAI2SEL LL_RCC_GetSAIClockSource +2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param SAIx This parameter can be one of the following values: +2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI1_CLKSOURCE +2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI2_CLKSOURCE +2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI +2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S +2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN +2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*) +2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI +2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S +2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN +2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) +2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * +2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * (*) value not defined in all devices. +2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) +2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR1, SAIx) >> 16U | SAIx); +2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get SDMMCx clock source +2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_GetSDMMCClockSource\n +2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 SDMMC2SEL LL_RCC_GetSDMMCClockSource +2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param SDMMCx This parameter can be one of the following values: +2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC1_CLKSOURCE +2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC1_CLKSOURCE (*) +2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: + ARM GAS /tmp/cc42qbQx.s page 55 + + +2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK +2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK +2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*) +2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*) +2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * +2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * (*) value not defined in all devices. +2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx) +2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDMMCx) >> 16U | SDMMCx); +2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get 48Mhz domain clock source +2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource +2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param CK48Mx This parameter can be one of the following values: +2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CK48M_CLKSOURCE +2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL +2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI +2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx) +2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx)); +2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get RNGx clock source +2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource +2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param RNGx This parameter can be one of the following values: +2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE +2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL +2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI +2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) +2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx)); +2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get USBx clock source +2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource +2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param USBx This parameter can be one of the following values: +2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE +2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLL +2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI +2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx)); +2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(CEC) +2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get CEC Clock Source + ARM GAS /tmp/cc42qbQx.s page 56 + + +2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource +2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param CECx This parameter can be one of the following values: +2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE +2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE +2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 +2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) +2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx)); +2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* CEC */ +2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get I2S Clock Source +2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource +2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param I2Sx This parameter can be one of the following values: +2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S1_CLKSOURCE +2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S +2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN +2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) +2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx)); +2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DFSDM1_Channel0) +2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get DFSDM Audio Clock Source +2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource +2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param DFSDMx This parameter can be one of the following values: +2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE +2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 +2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 +2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx) +2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx)); +2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get DFSDM Audio Clock Source +2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_GetDFSDMClockSource +2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param DFSDMx This parameter can be one of the following values: +2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_CLKSOURCE +2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 +2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK +2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx) +2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx)); +2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DFSDM1_Channel0 */ +2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + ARM GAS /tmp/cc42qbQx.s page 57 + + +2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI) +2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get DSI Clock Source +2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 DSISEL LL_RCC_GetDSIClockSource +2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param DSIx This parameter can be one of the following values: +2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DSI_CLKSOURCE +2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY +2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL +2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) +2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR2, DSIx)); +2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */ +2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_RTC RTC +2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Set RTC Clock Source +2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note Once the RTC clock source has been selected, it cannot be changed anymore unless +2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is +2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * set). The BDRST bit can be used to reset them. +2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource +2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE +2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE +2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI +2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE +2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get RTC Clock Source +2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource +2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE +2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE +2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI +2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE +2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + ARM GAS /tmp/cc42qbQx.s page 58 + + +2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable RTC +2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR RTCEN LL_RCC_EnableRTC +2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_EnableRTC(void) +2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable RTC +2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR RTCEN LL_RCC_DisableRTC +2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_DisableRTC(void) +2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Check if RTC has been enabled or not +2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC +2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval State of bit (1 or 0). +2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); +2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Force the Backup domain reset +2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset +2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Release the Backup domain reset +2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset +2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Set HSE Prescalers for RTC Clock +3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler +3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_NOCLOCK +3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_2 +3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_3 +3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_4 + ARM GAS /tmp/cc42qbQx.s page 59 + + +3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_5 +3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_6 +3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_7 +3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_8 +3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_9 +3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_10 +3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_11 +3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_12 +3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_13 +3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_14 +3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_15 +3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_16 +3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_17 +3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_18 +3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_19 +3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_20 +3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_21 +3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_22 +3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_23 +3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_24 +3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_25 +3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_26 +3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_27 +3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_28 +3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_29 +3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_30 +3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_31 +3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler) +3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler); +3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get HSE Prescalers for RTC Clock +3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler +3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_NOCLOCK +3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_2 +3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_3 +3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_4 +3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_5 +3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_6 +3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_7 +3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_8 +3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_9 +3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_10 +3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_11 +3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_12 +3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_13 +3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_14 +3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_15 +3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_16 +3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_17 +3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_18 +3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_19 + ARM GAS /tmp/cc42qbQx.s page 60 + + +3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_20 +3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_21 +3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_22 +3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_23 +3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_24 +3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_25 +3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_26 +3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_27 +3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_28 +3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_29 +3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_30 +3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_31 +3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) +3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)); +3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM +3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Set Timers Clock Prescalers +3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 TIMPRE LL_RCC_SetTIMPrescaler +3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_TIM_PRESCALER_TWICE +3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES +3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler) +3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE, Prescaler); +3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get Timers Clock Prescalers +3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 TIMPRE LL_RCC_GetTIMPrescaler +3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_TIM_PRESCALER_TWICE +3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES +3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void) +3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE)); +3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_PLL PLL +3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + ARM GAS /tmp/cc42qbQx.s page 61 + + +3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable PLL +3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR PLLON LL_RCC_PLL_Enable +3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_Enable(void) +3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_PLLON); +3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable PLL +3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note Cannot be disabled if the PLL clock is used as the system clock +3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR PLLON LL_RCC_PLL_Disable +3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_Disable(void) +3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Check if PLL Ready +3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady +3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval State of bit (1 or 0). +3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) + 105 .loc 2 3153 26 view .LVU25 + 106 .LBB241: +3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); + 107 .loc 2 3155 3 view .LVU26 + 108 .loc 2 3155 11 is_stmt 0 view .LVU27 + 109 0038 144B ldr r3, .L7 + 110 003a 1B68 ldr r3, [r3] + 111 .LBE241: + 112 .LBE240: + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {} + 113 .loc 1 189 30 discriminator 1 view .LVU28 + 114 003c 13F0007F tst r3, #33554432 + 115 0040 FAD1 bne .L3 + 116 .L4: + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Wait for PLLI2S READY bit to be reset */ + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** while(LL_RCC_PLLI2S_IsReady() != 0U) + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {} + 117 .loc 1 194 4 is_stmt 1 view .LVU29 + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {} + 118 .loc 1 193 33 discriminator 1 view .LVU30 + 119 .LBB242: + 120 .LBI242: +3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure PLL used for SYSCLK Domain + ARM GAS /tmp/cc42qbQx.s page 62 + + +3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLL Source and PLLM Divider can be written only when PLL, +3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2S and PLLSAI are disabled +3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLLN/PLLP can be written only when PLL is disabled +3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n +3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n +3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n +3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS +3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLM This parameter can be one of the following values: +3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 + ARM GAS /tmp/cc42qbQx.s page 63 + + +3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLN Between 50 and 432 +3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLP This parameter can be one of the following values: +3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_2 +3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_4 +3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_6 +3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_8 +3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uin +3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_P +3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); +3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure PLL used for 48Mhz domain clock +3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLL Source and PLLM Divider can be written only when PLL, +3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2S and PLLSAI are disabled +3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLLN/PLLQ can be written only when PLL is disabled +3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note This can be selected for USB, RNG, SDMMC1 +3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n +3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n +3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n +3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M +3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLM This parameter can be one of the following values: +3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 + ARM GAS /tmp/cc42qbQx.s page 64 + + +3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLN Between 50 and 432 +3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLQ This parameter can be one of the following values: +3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_2 +3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_3 +3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_4 +3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_5 +3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_6 +3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_7 + ARM GAS /tmp/cc42qbQx.s page 65 + + +3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_8 +3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_9 +3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_10 +3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_11 +3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_12 +3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_13 +3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_14 +3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_15 +3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uin +3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_P +3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ); +3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI) +3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure PLL used for DSI clock +3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLL Source and PLLM Divider can be written only when PLL, +3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2S and PLLSAI are disabled +3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLLN/PLLR can be written only when PLL is disabled +3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note This can be selected for DSI +3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n +3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n +3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n +3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI +3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLM This parameter can be one of the following values: +3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 + ARM GAS /tmp/cc42qbQx.s page 66 + + +3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLN Between 50 and 432 +3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLR This parameter can be one of the following values: +3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_2 +3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_3 +3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_4 +3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_5 +3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_6 +3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_7 +3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uin +3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_P +3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); +3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */ +3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure PLL clock source +3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource +3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLSource This parameter can be one of the following values: + ARM GAS /tmp/cc42qbQx.s page 67 + + +3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); +3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get the oscillator used as PLL clock source. +3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource +3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get Main PLL multiplication factor for VCO +3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN +3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Between 50 and 432 +3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) +3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); +3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get Main PLL division factor for PLLP +3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP +3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_2 +3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_4 +3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_6 +3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_8 +3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) +3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); +3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get Main PLL division factor for PLLQ +3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note used for PLL48MCLK selected for USB, RNG, SDMMC (48 MHz clock) +3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ +3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_2 +3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_3 +3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_4 +3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_5 +3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_6 +3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_7 +3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_8 + ARM GAS /tmp/cc42qbQx.s page 68 + + +3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_9 +3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_10 +3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_11 +3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_12 +3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_13 +3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_14 +3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_15 +3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) +3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)); +3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLCFGR_PLLR) +3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get Main PLL division factor for PLLR +3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note used for PLLCLK (system clock) +3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR +3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_2 +3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_3 +3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_4 +3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_5 +3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_6 +3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_7 +3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) +3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); +3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLCFGR_PLLR */ +3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get Division factor for the main PLL and other PLL +3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider +3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 + ARM GAS /tmp/cc42qbQx.s page 69 + + +3559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +3560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +3561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +3562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +3563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +3564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +3565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +3566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +3567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +3568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +3569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) +3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); +3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure Spread Spectrum used for PLL +3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note These bits must be written before enabling PLL +3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n +3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n +3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum +3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Mod Between Min_Data=0 and Max_Data=8191 +3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Inc Between Min_Data=0 and Max_Data=32767 +3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Sel This parameter can be one of the following values: +3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SPREAD_SELECT_CENTER + ARM GAS /tmp/cc42qbQx.s page 70 + + +3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SPREAD_SELECT_DOWN +3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel) +3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << +3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get Spread Spectrum Modulation Period for PLL +3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation +3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Between Min_Data=0 and Max_Data=8191 +3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void) +3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER)); +3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get Spread Spectrum Incrementation Step for PLL +3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note Must be written before enabling PLL +3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation +3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Between Min_Data=0 and Max_Data=32767 +3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void) +3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos); +3643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get Spread Spectrum Selection for PLL +3647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note Must be written before enabling PLL +3648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection +3649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +3650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SPREAD_SELECT_CENTER +3651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SPREAD_SELECT_DOWN +3652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void) +3654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL)); +3656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable Spread Spectrum for PLL. +3660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable +3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void) +3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); +3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable Spread Spectrum for PLL. +3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable +3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + ARM GAS /tmp/cc42qbQx.s page 71 + + +3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void) +3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); +3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_PLLI2S PLLI2S +3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +3684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable PLLI2S +3688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable +3689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void) +3692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_PLLI2SON); +3694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable PLLI2S +3698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable +3699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void) +3702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); +3704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Check if PLLI2S Ready +3708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady +3709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval State of bit (1 or 0). +3710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void) + 121 .loc 2 3711 26 view .LVU31 + 122 .LBB243: +3712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY)); + 123 .loc 2 3713 3 view .LVU32 + 124 .loc 2 3713 11 is_stmt 0 view .LVU33 + 125 0042 124B ldr r3, .L7 + 126 0044 1B68 ldr r3, [r3] + 127 .LBE243: + 128 .LBE242: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {} + 129 .loc 1 193 33 discriminator 1 view .LVU34 + 130 0046 13F0006F tst r3, #134217728 + 131 004a FAD1 bne .L4 + 132 .L5: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Wait for PLLSAI READY bit to be reset */ + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** while(LL_RCC_PLLSAI_IsReady() != 0U) + ARM GAS /tmp/cc42qbQx.s page 72 + + + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {} + 133 .loc 1 198 4 is_stmt 1 view .LVU35 + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {} + 134 .loc 1 197 33 discriminator 1 view .LVU36 + 135 .LBB244: + 136 .LBI244: +3714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure PLLI2S used for SAI1 and SAI2 domain clock +3718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLL Source and PLLM Divider can be written only when PLL, +3719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2S and PLLSAI are disabled +3720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLLN/PLLQ can be written only when PLLI2S is disabled +3721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note This can be selected for SAI1 and SAI2 +3722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n +3723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n +3724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n +3725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n +3726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI +3727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +3728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +3730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLM This parameter can be one of the following values: +3731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +3732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +3733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +3734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +3735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +3736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +3737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +3738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +3739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +3740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +3741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +3742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +3743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +3744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +3745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +3746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +3747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +3748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +3749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +3750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +3751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +3752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +3753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +3754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +3755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +3756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +3757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +3758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +3759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +3760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +3761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +3762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +3763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +3764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 + ARM GAS /tmp/cc42qbQx.s page 73 + + +3765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +3766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +3767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +3768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +3769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +3770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +3771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +3772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +3773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +3774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +3775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +3776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +3777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +3778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +3779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +3780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +3781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +3782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +3783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +3784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +3785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +3786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +3787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +3788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +3789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +3790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +3791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +3792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +3793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLN Between 50 and 432 +3794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLQ This parameter can be one of the following values: +3795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_2 +3796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_3 +3797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_4 +3798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_5 +3799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_6 +3800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_7 +3801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_8 +3802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_9 +3803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_10 +3804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_11 +3805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_12 +3806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_13 +3807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_14 +3808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_15 +3809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLDIVQ This parameter can be one of the following values: +3810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 +3811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 +3812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 +3813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 +3814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 +3815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 +3816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 +3817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 +3818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 +3819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 +3820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 +3821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 + ARM GAS /tmp/cc42qbQx.s page 74 + + +3822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 +3823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 +3824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 +3825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 +3826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 +3827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 +3828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 +3829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 +3830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 +3831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 +3832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 +3833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 +3834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 +3835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 +3836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 +3837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 +3838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 +3839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 +3840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 +3841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 +3842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, +3845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); +3847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCF +3848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, PLLDIVQ); +3849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SPDIFRX) +3852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure PLLI2S used for SPDIFRX domain clock +3854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLL Source and PLLM Divider can be written only when PLL, +3855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2S and PLLSAI are disabled +3856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLLN/PLLP can be written only when PLLI2S is disabled +3857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note This can be selected for SPDIFRX +3858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n +3859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n +3860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n +3861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX +3862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +3863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +3864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +3865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLM This parameter can be one of the following values: +3866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +3867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +3868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +3869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +3870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +3871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +3872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +3873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +3874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +3875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +3876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +3877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +3878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 + ARM GAS /tmp/cc42qbQx.s page 75 + + +3879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +3880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +3881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +3882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +3883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +3884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +3885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +3886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +3887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +3888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +3889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +3890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +3891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +3892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +3893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +3894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +3895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +3896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +3897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +3898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +3899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +3900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +3901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +3902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +3903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +3904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +3905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +3906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +3907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +3908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +3909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +3910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +3911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +3912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +3913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +3914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +3915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +3916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +3917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +3918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +3919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +3920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +3921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +3922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +3923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +3924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +3925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +3926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +3927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +3928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLN Between 50 and 432 +3929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLP This parameter can be one of the following values: +3930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_2 +3931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_4 +3932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_6 +3933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_8 +3934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + ARM GAS /tmp/cc42qbQx.s page 76 + + +3936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PL +3937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); +3939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCF +3940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SPDIFRX */ +3942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure PLLI2S used for I2S1 domain clock +3945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLL Source and PLLM Divider can be written only when PLL, +3946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2S and PLLSAI are disabled +3947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLLN/PLLR can be written only when PLLI2S is disabled +3948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note This can be selected for I2S +3949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n +3950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n +3951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n +3952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S +3953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +3954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +3955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +3956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLM This parameter can be one of the following values: +3957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +3958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +3959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +3960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +3961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +3962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +3963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +3964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +3965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +3966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +3967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +3968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +3969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +3970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +3971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +3972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +3973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +3974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +3975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +3976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +3977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +3978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +3979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +3980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +3981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +3982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +3983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +3984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +3985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +3986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +3987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +3988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +3989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +3990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +3991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +3992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 + ARM GAS /tmp/cc42qbQx.s page 77 + + +3993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +3994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +3995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +3996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +3997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +3998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +3999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +4000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +4001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +4002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +4003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +4004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +4005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +4006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +4007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +4008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +4009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +4010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +4011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +4012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +4013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +4014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +4015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +4016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +4017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +4018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +4019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLN Between 50 and 432 +4020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLR This parameter can be one of the following values: +4021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_2 +4022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_3 +4023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_4 +4024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_5 +4025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_6 +4026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_7 +4027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +4028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, +4030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); +4032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCF +4033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get I2SPLL multiplication factor for VCO +4037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN +4038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Between 50 and 432 +4039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void) +4041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos +4043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get I2SPLL division factor for PLLI2SQ +4047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ +4048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +4049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_2 + ARM GAS /tmp/cc42qbQx.s page 78 + + +4050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_3 +4051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_4 +4052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_5 +4053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_6 +4054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_7 +4055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_8 +4056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_9 +4057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_10 +4058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_11 +4059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_12 +4060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_13 +4061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_14 +4062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_15 +4063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void) +4065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ)); +4067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get I2SPLL division factor for PLLI2SR +4071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note used for PLLI2SCLK (I2S clock) +4072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR +4073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +4074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_2 +4075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_3 +4076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_4 +4077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_5 +4078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_6 +4079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_7 +4080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void) +4082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR)); +4084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLI2SCFGR_PLLI2SP) +4087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get I2SPLL division factor for PLLI2SP +4089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note used for PLLSPDIFRXCLK (SPDIFRX clock) +4090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP +4091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +4092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_2 +4093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_4 +4094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_6 +4095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_8 +4096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void) +4098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP)); +4100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLI2SCFGR_PLLI2SP */ +4102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get I2SPLL division factor for PLLI2SDIVQ +4105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock) +4106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ + ARM GAS /tmp/cc42qbQx.s page 79 + + +4107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +4108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 +4109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 +4110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 +4111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 +4112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 +4113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 +4114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 +4115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 +4116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 +4117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 +4118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 +4119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 +4120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 +4121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 +4122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 +4123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 +4124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 +4125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 +4126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 +4127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 +4128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 +4129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 +4130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 +4131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 +4132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 +4133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 +4134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 +4135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 +4136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 +4137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 +4138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 +4139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 +4140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void) +4142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ)); +4144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +4148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_PLLSAI PLLSAI +4151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +4152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable PLLSAI +4156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable +4157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +4158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLSAI_Enable(void) +4160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_PLLSAION); +4162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + ARM GAS /tmp/cc42qbQx.s page 80 + + +4164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable PLLSAI +4166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable +4167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +4168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLSAI_Disable(void) +4170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); +4172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Check if PLLSAI Ready +4176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady +4177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval State of bit (1 or 0). +4178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void) + 137 .loc 2 4179 26 view .LVU37 + 138 .LBB245: +4180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY)); + 139 .loc 2 4181 3 view .LVU38 + 140 .loc 2 4181 11 is_stmt 0 view .LVU39 + 141 004c 0F4B ldr r3, .L7 + 142 004e 1B68 ldr r3, [r3] + 143 .LBE245: + 144 .LBE244: + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** {} + 145 .loc 1 197 33 discriminator 1 view .LVU40 + 146 0050 13F0005F tst r3, #536870912 + 147 0054 FAD1 bne .L5 + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Reset PLLCFGR register */ + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** LL_RCC_WriteReg(PLLCFGR, 0x24003010U); + 148 .loc 1 201 3 is_stmt 1 view .LVU41 + 149 0056 0D4B ldr r3, .L7 + 150 0058 0E4A ldr r2, .L7+8 + 151 005a 5A60 str r2, [r3, #4] + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Reset PLLI2SCFGR register */ + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** LL_RCC_WriteReg(PLLI2SCFGR, 0x24003000U); + 152 .loc 1 204 3 view .LVU42 + 153 005c 103A subs r2, r2, #16 + 154 005e C3F88420 str r2, [r3, #132] + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Reset PLLSAICFGR register */ + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** LL_RCC_WriteReg(PLLSAICFGR, 0x24003000U); + 155 .loc 1 207 3 view .LVU43 + 156 0062 C3F88820 str r2, [r3, #136] + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Disable all interrupts */ + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | R + 157 .loc 1 210 3 view .LVU44 + 158 0066 DA68 ldr r2, [r3, #12] + 159 0068 22F4FE42 bic r2, r2, #32512 + 160 006c DA60 str r2, [r3, #12] + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Clear all interrupt flags */ + ARM GAS /tmp/cc42qbQx.s page 81 + + + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR + 161 .loc 1 213 3 view .LVU45 + 162 006e DA68 ldr r2, [r3, #12] + 163 0070 42F47F02 orr r2, r2, #16711680 + 164 0074 DA60 str r2, [r3, #12] + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Clear LSION bit */ + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); + 165 .loc 1 216 3 view .LVU46 + 166 0076 5A6F ldr r2, [r3, #116] + 167 0078 22F00102 bic r2, r2, #1 + 168 007c 5A67 str r2, [r3, #116] + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Reset all CSR flags */ + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** SET_BIT(RCC->CSR, RCC_CSR_RMVF); + 169 .loc 1 219 3 view .LVU47 + 170 007e 5A6F ldr r2, [r3, #116] + 171 0080 42F08072 orr r2, r2, #16777216 + 172 0084 5A67 str r2, [r3, #116] + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return SUCCESS; + 173 .loc 1 221 3 view .LVU48 + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 174 .loc 1 222 1 is_stmt 0 view .LVU49 + 175 0086 0020 movs r0, #0 + 176 0088 02B0 add sp, sp, #8 + 177 .LCFI1: + 178 .cfi_def_cfa_offset 0 + 179 @ sp needed + 180 008a 7047 bx lr + 181 .L8: + 182 .align 2 + 183 .L7: + 184 008c 00380240 .word 1073887232 + 185 0090 FFFFF2EA .word -353173505 + 186 0094 10300024 .word 603992080 + 187 .cfi_endproc + 188 .LFE295: + 190 .section .text.LL_RCC_GetCECClockFreq,"ax",%progbits + 191 .align 1 + 192 .global LL_RCC_GetCECClockFreq + 193 .syntax unified + 194 .thumb + 195 .thumb_func + 197 LL_RCC_GetCECClockFreq: + 198 .LVL2: + 199 .LFB305: + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @} + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** @addtogroup RCC_LL_EF_Get_Freq + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses c + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * and different peripheral clocks available on the device. + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + ARM GAS /tmp/cc42qbQx.s page 82 + + + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***) + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * or HSI_VALUE(**) multiplied/divided by the PLL factors. + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @note (**) HSI_VALUE is a constant defined in this file (default value + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * 16 MHz) but the real value may vary depending on the variations + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * in voltage and temperature. + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @note (***) HSE_VALUE is a constant defined in this file (default value + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * 25 MHz), user has to ensure that HSE_VALUE is same as the real + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * frequency of the crystal used. Otherwise, this function may + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * have wrong result. + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @note The result of this function could be incorrect when using fractional + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * value for HSE crystal. + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @note This function can be used by the user application to compute the + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * baud-rate for the communication peripherals or configure other parameters. + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @{ + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses c + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * must be called to update structure fields. Otherwise, any + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * configuration based on this function will be incorrect. + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval None + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Get SYSCLK frequency */ + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* HCLK clock frequency */ + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* PCLK1 clock frequency */ + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* PCLK2 clock frequency */ + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency); + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return USARTx clock frequency + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @param USARTxSource This parameter can be one of the following values: + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_USART1_CLKSOURCE + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_USART2_CLKSOURCE + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_USART3_CLKSOURCE + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_USART6_CLKSOURCE + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval USART clock frequency (in Hz) + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Check parameter */ + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (USARTxSource == LL_RCC_USART1_CLKSOURCE) + ARM GAS /tmp/cc42qbQx.s page 83 + + + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* USART1CLK clock frequency */ + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** usart_frequency = RCC_GetSystemClockFreq(); + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** usart_frequency = HSI_VALUE; + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_LSE_IsReady()) + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** usart_frequency = LSE_VALUE; + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */ + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** else if (USARTxSource == LL_RCC_USART2_CLKSOURCE) + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* USART2CLK clock frequency */ + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** usart_frequency = RCC_GetSystemClockFreq(); + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** usart_frequency = HSI_VALUE; + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_LSE_IsReady()) + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** usart_frequency = LSE_VALUE; + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + ARM GAS /tmp/cc42qbQx.s page 84 + + + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** else if (USARTxSource == LL_RCC_USART6_CLKSOURCE) + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* USART6CLK clock frequency */ + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_USART6_CLKSOURCE_SYSCLK: /* USART6 Clock is System Clock */ + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** usart_frequency = RCC_GetSystemClockFreq(); + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_USART6_CLKSOURCE_HSI: /* USART6 Clock is HSI Osc. */ + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** usart_frequency = HSI_VALUE; + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_USART6_CLKSOURCE_LSE: /* USART6 Clock is LSE Osc. */ + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_LSE_IsReady()) + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** usart_frequency = LSE_VALUE; + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_USART6_CLKSOURCE_PCLK2: /* USART6 Clock is PCLK2 */ + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** else + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (USARTxSource == LL_RCC_USART3_CLKSOURCE) + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* USART3CLK clock frequency */ + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */ + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** usart_frequency = RCC_GetSystemClockFreq(); + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */ + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** usart_frequency = HSI_VALUE; + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */ + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_LSE_IsReady()) + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** usart_frequency = LSE_VALUE; + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */ + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + ARM GAS /tmp/cc42qbQx.s page 85 + + + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return usart_frequency; + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return UARTx clock frequency + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @param UARTxSource This parameter can be one of the following values: + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_UART4_CLKSOURCE + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_UART5_CLKSOURCE + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_UART7_CLKSOURCE + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_UART8_CLKSOURCE + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval UART clock frequency (in Hz) + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Check parameter */ + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource)); + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (UARTxSource == LL_RCC_UART4_CLKSOURCE) + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* UART4CLK clock frequency */ + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetUARTClockSource(UARTxSource)) + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */ + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uart_frequency = RCC_GetSystemClockFreq(); + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */ + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uart_frequency = HSI_VALUE; + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */ + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_LSE_IsReady()) + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uart_frequency = LSE_VALUE; + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */ + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** else if (UARTxSource == LL_RCC_UART5_CLKSOURCE) + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* UART5CLK clock frequency */ + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetUARTClockSource(UARTxSource)) + ARM GAS /tmp/cc42qbQx.s page 86 + + + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */ + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uart_frequency = RCC_GetSystemClockFreq(); + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */ + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uart_frequency = HSI_VALUE; + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */ + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_LSE_IsReady()) + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uart_frequency = LSE_VALUE; + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */ + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** else if (UARTxSource == LL_RCC_UART7_CLKSOURCE) + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* UART7CLK clock frequency */ + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetUARTClockSource(UARTxSource)) + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_UART7_CLKSOURCE_SYSCLK: /* UART7 Clock is System Clock */ + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uart_frequency = RCC_GetSystemClockFreq(); + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_UART7_CLKSOURCE_HSI: /* UART7 Clock is HSI Osc. */ + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uart_frequency = HSI_VALUE; + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_UART7_CLKSOURCE_LSE: /* UART7 Clock is LSE Osc. */ + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_LSE_IsReady()) + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uart_frequency = LSE_VALUE; + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_UART7_CLKSOURCE_PCLK1: /* UART7 Clock is PCLK1 */ + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** else + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (UARTxSource == LL_RCC_UART8_CLKSOURCE) + ARM GAS /tmp/cc42qbQx.s page 87 + + + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* UART8CLK clock frequency */ + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetUARTClockSource(UARTxSource)) + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_UART8_CLKSOURCE_SYSCLK: /* UART8 Clock is System Clock */ + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uart_frequency = RCC_GetSystemClockFreq(); + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_UART8_CLKSOURCE_HSI: /* UART8 Clock is HSI Osc. */ + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uart_frequency = HSI_VALUE; + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_UART8_CLKSOURCE_LSE: /* UART8 Clock is LSE Osc. */ + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_LSE_IsReady()) + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uart_frequency = LSE_VALUE; + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_UART8_CLKSOURCE_PCLK1: /* UART8 Clock is PCLK1 */ + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return uart_frequency; + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return I2Cx clock frequency + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @param I2CxSource This parameter can be one of the following values: + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_I2C1_CLKSOURCE + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_I2C2_CLKSOURCE + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_I2C3_CLKSOURCE + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_I2C4_CLKSOURCE (*) + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * (*) value not defined in all devices. + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval I2C clock frequency (in Hz) + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Check parameter */ + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* I2C1 CLK clock frequency */ + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetI2CClockSource(I2CxSource)) + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ + ARM GAS /tmp/cc42qbQx.s page 88 + + + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** i2c_frequency = RCC_GetSystemClockFreq(); + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** i2c_frequency = HSI_VALUE; + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */ + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE) + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* I2C2 CLK clock frequency */ + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetI2CClockSource(I2CxSource)) + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */ + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** i2c_frequency = RCC_GetSystemClockFreq(); + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */ + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** i2c_frequency = HSI_VALUE; + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */ + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** else if (I2CxSource == LL_RCC_I2C3_CLKSOURCE) + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* I2C3 CLK clock frequency */ + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetI2CClockSource(I2CxSource)) + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */ + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** i2c_frequency = RCC_GetSystemClockFreq(); + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */ + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** i2c_frequency = HSI_VALUE; + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */ + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + ARM GAS /tmp/cc42qbQx.s page 89 + + + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(I2C4) + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** else + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (I2CxSource == LL_RCC_I2C4_CLKSOURCE) + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* I2C4 CLK clock frequency */ + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetI2CClockSource(I2CxSource)) + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */ + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** i2c_frequency = RCC_GetSystemClockFreq(); + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */ + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** i2c_frequency = HSI_VALUE; + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */ + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #else + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** else + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Nothing to do */ + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* I2C4 */ + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return i2c_frequency; + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** + 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return I2Sx clock frequency + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @param I2SxSource This parameter can be one of the following values: + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_I2S1_CLKSOURCE + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval I2S clock frequency (in Hz) + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLLI2S oscillator is not ready + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource) + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Check parameter */ + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource)); + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (I2SxSource == LL_RCC_I2S1_CLKSOURCE) + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* I2S1 CLK clock frequency */ + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetI2SClockSource(I2SxSource)) + ARM GAS /tmp/cc42qbQx.s page 90 + + + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_I2S1_CLKSOURCE_PLLI2S: /* I2S1 Clock is PLLI2S */ + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_PLLI2S_IsReady()) + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S(); + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */ + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** i2s_frequency = EXTERNAL_CLOCK_VALUE; + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return i2s_frequency; + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return LPTIMx clock frequency + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @param LPTIMxSource This parameter can be one of the following values: + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval LPTIM clock frequency (in Hz) + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not r + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Check parameter */ + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource)); + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE) + 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* LPTIM1CLK clock frequency */ + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_LSI_IsReady()) + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** lptim_frequency = LSI_VALUE; + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */ + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** lptim_frequency = HSI_VALUE; + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */ + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_LSE_IsReady()) + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** lptim_frequency = LSE_VALUE; + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + ARM GAS /tmp/cc42qbQx.s page 91 + + + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */ + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return lptim_frequency; + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return SAIx clock frequency + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @param SAIxSource This parameter can be one of the following values: + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_SAI1_CLKSOURCE + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_SAI2_CLKSOURCE + 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval SAI clock frequency (in Hz) + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Check parameter */ + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource)); + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (SAIxSource == LL_RCC_SAI1_CLKSOURCE) + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* SAI1CLK clock frequency */ + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetSAIClockSource(SAIxSource)) + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */ + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_PLLSAI_IsReady()) + 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI(); + 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */ + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_PLLI2S_IsReady()) + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI(); + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(RCC_SAI1SEL_PLLSRC_SUPPORT) + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_SAI1_CLKSOURCE_PLLSRC: + 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_PLL_GetMainSource()) + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 clock source */ + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_HSE_IsReady()) + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** sai_frequency = HSE_VALUE; + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 clock source */ + ARM GAS /tmp/cc42qbQx.s page 92 + + + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** sai_frequency = HSI_VALUE; + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */ + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */ + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** sai_frequency = EXTERNAL_SAI1_CLOCK_VALUE; + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** else + 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (SAIxSource == LL_RCC_SAI2_CLKSOURCE) + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* SAI2CLK clock frequency */ + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetSAIClockSource(SAIxSource)) + 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */ + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_PLLSAI_IsReady()) + 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI(); + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */ + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_PLLI2S_IsReady()) + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI(); + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(RCC_SAI2SEL_PLLSRC_SUPPORT) + 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_SAI2_CLKSOURCE_PLLSRC: + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_PLL_GetMainSource()) + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */ + 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_HSE_IsReady()) + 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** sai_frequency = HSE_VALUE; + 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */ + 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** sai_frequency = HSI_VALUE; + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + ARM GAS /tmp/cc42qbQx.s page 93 + + + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */ + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */ + 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** sai_frequency = EXTERNAL_SAI2_CLOCK_VALUE; + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return sai_frequency; + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return SDMMCx clock frequency + 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @param SDMMCxSource This parameter can be one of the following values: + 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_SDMMC1_CLKSOURCE + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*) + 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * (*) value not defined in all devices. + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval SDMMC clock frequency (in Hz) + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLL is not ready + 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Check parameter */ + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource)); + 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (SDMMCxSource == LL_RCC_SDMMC1_CLKSOURCE) + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* SDMMC1CLK clock frequency */ + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource)) + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK: /* PLL48 clock used as SDMMC1 clock source */ + 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE)) + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */ + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_PLL_IsReady()) + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** sdmmc_frequency = RCC_PLL_GetFreqDomain_48M(); + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */ + 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_PLLSAI_IsReady()) + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M(); + 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + ARM GAS /tmp/cc42qbQx.s page 94 + + + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_SDMMC1_CLKSOURCE_SYSCLK: /* PLL clock used as SDMMC1 clock source */ + 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** sdmmc_frequency = RCC_GetSystemClockFreq(); + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(SDMMC2) + 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** else + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* SDMMC2CLK clock frequency */ + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource)) + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK: /* PLL48 clock used as SDMMC2 clock source */ + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE)) + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */ + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_PLL_IsReady()) + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** sdmmc_frequency = RCC_PLL_GetFreqDomain_48M(); + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */ + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_PLLSAI_IsReady()) + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M(); + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_SDMMC2_CLKSOURCE_SYSCLK: /* PLL clock used as SDMMC2 clock source */ + 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** sdmmc_frequency = RCC_GetSystemClockFreq(); + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* SDMMC2 */ + 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return sdmmc_frequency; + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** + 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return RNGx clock frequency + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @param RNGxSource This parameter can be one of the following values: + 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_RNG_CLKSOURCE + 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval RNG clock frequency (in Hz) + 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource) + 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Check parameter */ + 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource)); + 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + ARM GAS /tmp/cc42qbQx.s page 95 + + + 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* RNGCLK clock frequency */ + 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetRNGClockSource(RNGxSource)) + 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */ + 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_PLL_IsReady()) + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** rng_frequency = RCC_PLL_GetFreqDomain_48M(); + 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_RNG_CLKSOURCE_PLLSAI: /* PLLSAI clock used as RNG clock source */ + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: + 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_PLLSAI_IsReady()) + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** rng_frequency = RCC_PLLSAI_GetFreqDomain_48M(); + 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return rng_frequency; + 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(CEC) + 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** + 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return CEC clock frequency + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @param CECxSource This parameter can be one of the following values: +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_CEC_CLKSOURCE +1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval CEC clock frequency (in Hz) +1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource) +1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 200 .loc 1 1005 1 is_stmt 1 view -0 + 201 .cfi_startproc + 202 @ args = 0, pretend = 0, frame = 0 + 203 @ frame_needed = 0, uses_anonymous_args = 0 + 204 @ link register save eliminated. +1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 205 .loc 1 1006 3 view .LVU51 +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Check parameter */ +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource)); + 206 .loc 1 1009 3 view .LVU52 +1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* CECCLK clock frequency */ +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetCECClockSource(CECxSource)) + 207 .loc 1 1012 3 view .LVU53 + 208 .LBB246: + 209 .LBI246: +2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 210 .loc 2 2847 26 view .LVU54 + 211 .LBB247: +2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 212 .loc 2 2849 3 view .LVU55 +2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 213 .loc 2 2849 21 is_stmt 0 view .LVU56 + 214 0000 0A4B ldr r3, .L15 + ARM GAS /tmp/cc42qbQx.s page 96 + + + 215 0002 D3F89030 ldr r3, [r3, #144] + 216 .LVL3: +2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 217 .loc 2 2849 21 view .LVU57 + 218 .LBE247: + 219 .LBE246: + 220 .loc 1 1012 3 discriminator 1 view .LVU58 + 221 0006 1842 tst r0, r3 + 222 0008 05D1 bne .L10 +1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */ +1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_LSE_IsReady()) + 223 .loc 1 1015 7 is_stmt 1 view .LVU59 + 224 .LBB248: + 225 .LBI248: +2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 226 .loc 2 2154 26 view .LVU60 + 227 .LBB249: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 228 .loc 2 2156 3 view .LVU61 +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 229 .loc 2 2156 11 is_stmt 0 view .LVU62 + 230 000a 084B ldr r3, .L15 + 231 000c 186F ldr r0, [r3, #112] + 232 .LVL4: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 233 .loc 2 2156 11 view .LVU63 + 234 .LBE249: + 235 .LBE248: + 236 .loc 1 1015 10 discriminator 1 view .LVU64 + 237 000e 10F00200 ands r0, r0, #2 + 238 0012 08D1 bne .L14 + 239 .LVL5: + 240 .L9: +1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** cec_frequency = LSE_VALUE; +1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */ +1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_HSI_IsReady()) +1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** cec_frequency = HSI_VALUE/488U; +1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return cec_frequency; +1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 241 .loc 1 1031 1 view .LVU65 + 242 0014 7047 bx lr + 243 .LVL6: + 244 .L10: +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 245 .loc 1 1023 7 is_stmt 1 view .LVU66 + 246 .LBB250: + ARM GAS /tmp/cc42qbQx.s page 97 + + + 247 .LBI250: +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 248 .loc 2 2030 26 view .LVU67 + 249 .LBB251: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 250 .loc 2 2032 3 view .LVU68 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 251 .loc 2 2032 11 is_stmt 0 view .LVU69 + 252 0016 054B ldr r3, .L15 + 253 0018 1868 ldr r0, [r3] + 254 .LVL7: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 255 .loc 2 2032 11 view .LVU70 + 256 .LBE251: + 257 .LBE250: +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 258 .loc 1 1023 10 discriminator 1 view .LVU71 + 259 001a 10F00200 ands r0, r0, #2 + 260 001e F9D0 beq .L9 +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 261 .loc 1 1025 23 view .LVU72 + 262 0020 48F21200 movw r0, #32786 + 263 .LVL8: +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 264 .loc 1 1030 3 is_stmt 1 view .LVU73 +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 265 .loc 1 1030 10 is_stmt 0 view .LVU74 + 266 0024 F6E7 b .L9 + 267 .LVL9: + 268 .L14: +1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 269 .loc 1 1017 23 view .LVU75 + 270 0026 4FF40040 mov r0, #32768 + 271 002a 7047 bx lr + 272 .L16: + 273 .align 2 + 274 .L15: + 275 002c 00380240 .word 1073887232 + 276 .cfi_endproc + 277 .LFE305: + 279 .section .text.RCC_GetHCLKClockFreq,"ax",%progbits + 280 .align 1 + 281 .global RCC_GetHCLKClockFreq + 282 .syntax unified + 283 .thumb + 284 .thumb_func + 286 RCC_GetHCLKClockFreq: + 287 .LVL10: + 288 .LFB312: +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* CEC */ +1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return USBx clock frequency +1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @param USBxSource This parameter can be one of the following values: +1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_USB_CLKSOURCE +1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval USB clock frequency (in Hz) +1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + ARM GAS /tmp/cc42qbQx.s page 98 + + +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; +1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Check parameter */ +1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); +1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* USBCLK clock frequency */ +1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetUSBClockSource(USBxSource)) +1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ +1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_PLL_IsReady()) +1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** usb_frequency = RCC_PLL_GetFreqDomain_48M(); +1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_USB_CLKSOURCE_PLLSAI: /* PLLSAI clock used as USB clock source */ +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_PLLSAI_IsReady()) +1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** usb_frequency = RCC_PLLSAI_GetFreqDomain_48M(); +1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return usb_frequency; +1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(DFSDM1_Channel0) +1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return DFSDMx clock frequency +1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @param DFSDMxSource This parameter can be one of the following values: +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_DFSDM1_CLKSOURCE +1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval DFSDM clock frequency (in Hz) +1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource) +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO; +1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Check parameter */ +1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource)); +1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* DFSDM1CLK clock frequency */ +1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource)) +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */ +1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** dfsdm_frequency = RCC_GetSystemClockFreq(); +1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */ +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: +1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); +1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return dfsdm_frequency; + ARM GAS /tmp/cc42qbQx.s page 99 + + +1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return DFSDMx Audio clock frequency +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @param DFSDMxSource This parameter can be one of the following values: +1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE +1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval DFSDM clock frequency (in Hz) +1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready +1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource) +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO; +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Check parameter */ +1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource)); +1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* DFSDM1CLK clock frequency */ +1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource)) +1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1: /* SAI1 clock used as DFSDM1 audio clock */ +1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE); +1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2: /* SAI2 clock used as DFSDM1 audio clock */ +1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI2_CLKSOURCE); +1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return dfsdm_frequency; +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* DFSDM1_Channel0 */ +1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(DSI) +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return DSI clock frequency +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @param DSIxSource This parameter can be one of the following values: +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_DSI_CLKSOURCE +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval DSI clock frequency (in Hz) +1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready +1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used +1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource) +1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; +1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Check parameter */ +1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource)); +1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* DSICLK clock frequency */ +1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetDSIClockSource(DSIxSource)) +1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLL Osc. */ +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_PLL_IsReady()) +1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** dsi_frequency = RCC_PLL_GetFreqDomain_DSI(); +1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + ARM GAS /tmp/cc42qbQx.s page 100 + + +1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */ +1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA; +1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return dsi_frequency; +1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* DSI */ +1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(LTDC) +1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return LTDC clock frequency +1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @param LTDCxSource This parameter can be one of the following values: +1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_LTDC_CLKSOURCE +1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval LTDC clock frequency (in Hz) +1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready +1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource) +1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; +1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Check parameter */ +1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource)); +1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_PLLSAI_IsReady()) +1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC(); +1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return ltdc_frequency; +1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* LTDC */ +1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(SPDIFRX) +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return SPDIFRX clock frequency +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @param SPDIFRXxSource This parameter can be one of the following values: +1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE +1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval SPDIFRX clock frequency (in Hz) +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource) +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO; +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Check parameter */ +1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource)); +1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** if (LL_RCC_PLLI2S_IsReady()) +1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX(); +1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return spdifrx_frequency; + ARM GAS /tmp/cc42qbQx.s page 101 + + +1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* SPDIFRX */ +1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @} +1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @} +1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** @addtogroup RCC_LL_Private_Functions +1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @{ +1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return SYSTEM clock frequency +1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval SYSTEM clock frequency (in Hz) +1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_GetSystemClockFreq(void) +1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t frequency = 0U; +1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Get SYSCLK source -------------------------------------------------------*/ +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (LL_RCC_GetSysClkSource()) +1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** frequency = HSI_VALUE; +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ +1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** frequency = HSE_VALUE; +1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ +1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** frequency = RCC_PLL_GetFreqDomain_SYS(); +1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: +1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** frequency = HSI_VALUE; +1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return frequency; +1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return HCLK clock frequency +1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @param SYSCLK_Frequency SYSCLK clock frequency +1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval HCLK clock frequency (in Hz) +1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) +1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 289 .loc 1 1263 1 is_stmt 1 view -0 + 290 .cfi_startproc + 291 @ args = 0, pretend = 0, frame = 0 + 292 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/cc42qbQx.s page 102 + + + 293 @ link register save eliminated. +1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* HCLK clock frequency */ +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); + 294 .loc 1 1265 3 view .LVU77 + 295 .LBB252: + 296 .LBI252: +2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 297 .loc 2 2298 26 view .LVU78 + 298 .LBB253: +2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 299 .loc 2 2300 3 view .LVU79 +2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 300 .loc 2 2300 21 is_stmt 0 view .LVU80 + 301 0000 034B ldr r3, .L18 + 302 0002 9B68 ldr r3, [r3, #8] + 303 .LBE253: + 304 .LBE252: + 305 .loc 1 1265 10 discriminator 1 view .LVU81 + 306 0004 C3F30313 ubfx r3, r3, #4, #4 + 307 0008 024A ldr r2, .L18+4 + 308 000a D35C ldrb r3, [r2, r3] @ zero_extendqisi2 +1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 309 .loc 1 1266 1 view .LVU82 + 310 000c D840 lsrs r0, r0, r3 + 311 .LVL11: + 312 .loc 1 1266 1 view .LVU83 + 313 000e 7047 bx lr + 314 .L19: + 315 .align 2 + 316 .L18: + 317 0010 00380240 .word 1073887232 + 318 0014 00000000 .word AHBPrescTable + 319 .cfi_endproc + 320 .LFE312: + 322 .section .text.RCC_GetPCLK1ClockFreq,"ax",%progbits + 323 .align 1 + 324 .global RCC_GetPCLK1ClockFreq + 325 .syntax unified + 326 .thumb + 327 .thumb_func + 329 RCC_GetPCLK1ClockFreq: + 330 .LVL12: + 331 .LFB313: +1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return PCLK1 clock frequency +1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @param HCLK_Frequency HCLK clock frequency +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval PCLK1 clock frequency (in Hz) +1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) +1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 332 .loc 1 1274 1 is_stmt 1 view -0 + 333 .cfi_startproc + 334 @ args = 0, pretend = 0, frame = 0 + 335 @ frame_needed = 0, uses_anonymous_args = 0 + 336 @ link register save eliminated. +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* PCLK1 clock frequency */ + ARM GAS /tmp/cc42qbQx.s page 103 + + +1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); + 337 .loc 1 1276 3 view .LVU85 + 338 .LBB254: + 339 .LBI254: +2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 340 .loc 2 2313 26 view .LVU86 + 341 .LBB255: +2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 342 .loc 2 2315 3 view .LVU87 +2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 343 .loc 2 2315 21 is_stmt 0 view .LVU88 + 344 0000 034B ldr r3, .L21 + 345 0002 9B68 ldr r3, [r3, #8] + 346 .LBE255: + 347 .LBE254: + 348 .loc 1 1276 10 discriminator 1 view .LVU89 + 349 0004 C3F38223 ubfx r3, r3, #10, #3 + 350 0008 024A ldr r2, .L21+4 + 351 000a D35C ldrb r3, [r2, r3] @ zero_extendqisi2 +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 352 .loc 1 1277 1 view .LVU90 + 353 000c D840 lsrs r0, r0, r3 + 354 .LVL13: + 355 .loc 1 1277 1 view .LVU91 + 356 000e 7047 bx lr + 357 .L22: + 358 .align 2 + 359 .L21: + 360 0010 00380240 .word 1073887232 + 361 0014 00000000 .word APBPrescTable + 362 .cfi_endproc + 363 .LFE313: + 365 .section .text.RCC_GetPCLK2ClockFreq,"ax",%progbits + 366 .align 1 + 367 .global RCC_GetPCLK2ClockFreq + 368 .syntax unified + 369 .thumb + 370 .thumb_func + 372 RCC_GetPCLK2ClockFreq: + 373 .LVL14: + 374 .LFB314: +1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return PCLK2 clock frequency +1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @param HCLK_Frequency HCLK clock frequency +1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval PCLK2 clock frequency (in Hz) +1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) +1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 375 .loc 1 1285 1 is_stmt 1 view -0 + 376 .cfi_startproc + 377 @ args = 0, pretend = 0, frame = 0 + 378 @ frame_needed = 0, uses_anonymous_args = 0 + 379 @ link register save eliminated. +1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* PCLK2 clock frequency */ +1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); + 380 .loc 1 1287 3 view .LVU93 + ARM GAS /tmp/cc42qbQx.s page 104 + + + 381 .LBB256: + 382 .LBI256: +2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 383 .loc 2 2328 26 view .LVU94 + 384 .LBB257: +2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 385 .loc 2 2330 3 view .LVU95 +2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 386 .loc 2 2330 21 is_stmt 0 view .LVU96 + 387 0000 034B ldr r3, .L24 + 388 0002 9B68 ldr r3, [r3, #8] + 389 .LBE257: + 390 .LBE256: + 391 .loc 1 1287 10 discriminator 1 view .LVU97 + 392 0004 C3F34233 ubfx r3, r3, #13, #3 + 393 0008 024A ldr r2, .L24+4 + 394 000a D35C ldrb r3, [r2, r3] @ zero_extendqisi2 +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 395 .loc 1 1288 1 view .LVU98 + 396 000c D840 lsrs r0, r0, r3 + 397 .LVL15: + 398 .loc 1 1288 1 view .LVU99 + 399 000e 7047 bx lr + 400 .L25: + 401 .align 2 + 402 .L24: + 403 0010 00380240 .word 1073887232 + 404 0014 00000000 .word APBPrescTable + 405 .cfi_endproc + 406 .LFE314: + 408 .section .text.RCC_PLL_GetFreqDomain_SYS,"ax",%progbits + 409 .align 1 + 410 .global RCC_PLL_GetFreqDomain_SYS + 411 .syntax unified + 412 .thumb + 413 .thumb_func + 415 RCC_PLL_GetFreqDomain_SYS: + 416 .LFB315: +1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return PLL clock frequency used for system domain +1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval PLL clock frequency (in Hz) +1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLL_GetFreqDomain_SYS(void) +1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 417 .loc 1 1295 1 is_stmt 1 view -0 + 418 .cfi_startproc + 419 @ args = 0, pretend = 0, frame = 0 + 420 @ frame_needed = 0, uses_anonymous_args = 0 + 421 @ link register save eliminated. +1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t pllinputfreq = 0U, pllsource = 0U; + 422 .loc 1 1296 3 view .LVU101 + 423 .LVL16: +1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN +1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** SYSCLK = PLL_VCO / PLLP +1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ + ARM GAS /tmp/cc42qbQx.s page 105 + + +1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllsource = LL_RCC_PLL_GetMainSource(); + 424 .loc 1 1301 3 view .LVU102 + 425 .LBB258: + 426 .LBI258: +3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 427 .loc 2 3461 26 view .LVU103 + 428 .LBB259: +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 429 .loc 2 3463 3 view .LVU104 +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 430 .loc 2 3463 21 is_stmt 0 view .LVU105 + 431 0000 0D4B ldr r3, .L29 + 432 0002 5B68 ldr r3, [r3, #4] +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 433 .loc 2 3463 10 view .LVU106 + 434 0004 03F48003 and r3, r3, #4194304 + 435 .LVL17: +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 436 .loc 2 3463 10 view .LVU107 + 437 .LBE259: + 438 .LBE258: +1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (pllsource) + 439 .loc 1 1303 3 is_stmt 1 view .LVU108 + 440 0008 9BB9 cbnz r3, .L28 +1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ +1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; + 441 .loc 1 1306 20 is_stmt 0 view .LVU109 + 442 000a 0C48 ldr r0, .L29+4 + 443 .L27: + 444 .LVL18: +1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ +1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSE_VALUE; +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: +1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; +1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + 445 .loc 1 1317 3 is_stmt 1 view .LVU110 + 446 .LBB260: + 447 .LBI260: +3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 448 .loc 2 3601 26 view .LVU111 + 449 .LBB261: +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 450 .loc 2 3603 3 view .LVU112 +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 451 .loc 2 3603 21 is_stmt 0 view .LVU113 + 452 000c 0A4B ldr r3, .L29 + 453 .LVL19: +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 454 .loc 2 3603 21 view .LVU114 + ARM GAS /tmp/cc42qbQx.s page 106 + + + 455 000e 5A68 ldr r2, [r3, #4] +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 456 .loc 2 3603 10 view .LVU115 + 457 0010 02F03F02 and r2, r2, #63 + 458 .LBE261: + 459 .LBE260: + 460 .loc 1 1317 10 discriminator 1 view .LVU116 + 461 0014 B0FBF2F0 udiv r0, r0, r2 + 462 .LVL20: + 463 .LBB262: + 464 .LBI262: +3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 465 .loc 2 3471 26 is_stmt 1 view .LVU117 + 466 .LBB263: +3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 467 .loc 2 3473 3 view .LVU118 +3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 468 .loc 2 3473 21 is_stmt 0 view .LVU119 + 469 0018 5A68 ldr r2, [r3, #4] +3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 470 .loc 2 3473 10 view .LVU120 + 471 001a C2F38812 ubfx r2, r2, #6, #9 + 472 .LBE263: + 473 .LBE262: + 474 .loc 1 1317 10 discriminator 2 view .LVU121 + 475 001e 02FB00F0 mul r0, r2, r0 + 476 .LBB264: + 477 .LBI264: +3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 478 .loc 2 3485 26 is_stmt 1 view .LVU122 + 479 .LBB265: +3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 480 .loc 2 3487 3 view .LVU123 +3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 481 .loc 2 3487 21 is_stmt 0 view .LVU124 + 482 0022 5B68 ldr r3, [r3, #4] + 483 .LBE265: + 484 .LBE264: + 485 .loc 1 1317 10 discriminator 3 view .LVU125 + 486 0024 C3F30143 ubfx r3, r3, #16, #2 + 487 0028 0133 adds r3, r3, #1 + 488 002a 5B00 lsls r3, r3, #1 +1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 489 .loc 1 1319 1 view .LVU126 + 490 002c B0FBF3F0 udiv r0, r0, r3 + 491 0030 7047 bx lr + 492 .LVL21: + 493 .L28: +1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 494 .loc 1 1310 20 view .LVU127 + 495 0032 0348 ldr r0, .L29+8 + 496 0034 EAE7 b .L27 + 497 .L30: + 498 0036 00BF .align 2 + 499 .L29: + 500 0038 00380240 .word 1073887232 + ARM GAS /tmp/cc42qbQx.s page 107 + + + 501 003c 0024F400 .word 16000000 + 502 0040 40787D01 .word 25000000 + 503 .cfi_endproc + 504 .LFE315: + 506 .section .text.RCC_GetSystemClockFreq,"ax",%progbits + 507 .align 1 + 508 .global RCC_GetSystemClockFreq + 509 .syntax unified + 510 .thumb + 511 .thumb_func + 513 RCC_GetSystemClockFreq: + 514 .LFB311: +1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t frequency = 0U; + 515 .loc 1 1231 1 is_stmt 1 view -0 + 516 .cfi_startproc + 517 @ args = 0, pretend = 0, frame = 0 + 518 @ frame_needed = 0, uses_anonymous_args = 0 + 519 0000 08B5 push {r3, lr} + 520 .LCFI2: + 521 .cfi_def_cfa_offset 8 + 522 .cfi_offset 3, -8 + 523 .cfi_offset 14, -4 +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 524 .loc 1 1232 3 view .LVU129 + 525 .LVL22: +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 526 .loc 1 1235 3 view .LVU130 + 527 .LBB266: + 528 .LBI266: +2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 529 .loc 2 2227 26 view .LVU131 + 530 .LBB267: +2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 531 .loc 2 2229 3 view .LVU132 +2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 532 .loc 2 2229 21 is_stmt 0 view .LVU133 + 533 0002 074B ldr r3, .L36 + 534 0004 9B68 ldr r3, [r3, #8] +2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 535 .loc 2 2229 10 view .LVU134 + 536 0006 03F00C03 and r3, r3, #12 + 537 .LBE267: + 538 .LBE266: +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 539 .loc 1 1235 3 discriminator 1 view .LVU135 + 540 000a 042B cmp r3, #4 + 541 000c 04D0 beq .L33 + 542 000e 082B cmp r3, #8 + 543 0010 04D1 bne .L34 +1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 544 .loc 1 1246 7 is_stmt 1 view .LVU136 +1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 545 .loc 1 1246 19 is_stmt 0 view .LVU137 + 546 0012 FFF7FEFF bl RCC_PLL_GetFreqDomain_SYS + 547 .LVL23: +1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 548 .loc 1 1247 7 is_stmt 1 view .LVU138 + ARM GAS /tmp/cc42qbQx.s page 108 + + + 549 .L31: +1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 550 .loc 1 1255 1 is_stmt 0 view .LVU139 + 551 0016 08BD pop {r3, pc} + 552 .LVL24: + 553 .L33: +1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 554 .loc 1 1242 17 view .LVU140 + 555 0018 0248 ldr r0, .L36+4 + 556 001a FCE7 b .L31 + 557 .L34: +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 558 .loc 1 1235 3 discriminator 1 view .LVU141 + 559 001c 0248 ldr r0, .L36+8 + 560 .LVL25: +1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 561 .loc 1 1254 3 is_stmt 1 view .LVU142 +1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 562 .loc 1 1254 10 is_stmt 0 view .LVU143 + 563 001e FAE7 b .L31 + 564 .L37: + 565 .align 2 + 566 .L36: + 567 0020 00380240 .word 1073887232 + 568 0024 40787D01 .word 25000000 + 569 0028 0024F400 .word 16000000 + 570 .cfi_endproc + 571 .LFE311: + 573 .section .text.LL_RCC_GetSystemClocksFreq,"ax",%progbits + 574 .align 1 + 575 .global LL_RCC_GetSystemClocksFreq + 576 .syntax unified + 577 .thumb + 578 .thumb_func + 580 LL_RCC_GetSystemClocksFreq: + 581 .LVL26: + 582 .LFB296: + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Get SYSCLK frequency */ + 583 .loc 1 258 1 is_stmt 1 view -0 + 584 .cfi_startproc + 585 @ args = 0, pretend = 0, frame = 0 + 586 @ frame_needed = 0, uses_anonymous_args = 0 + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* Get SYSCLK frequency */ + 587 .loc 1 258 1 is_stmt 0 view .LVU145 + 588 0000 10B5 push {r4, lr} + 589 .LCFI3: + 590 .cfi_def_cfa_offset 8 + 591 .cfi_offset 4, -8 + 592 .cfi_offset 14, -4 + 593 0002 0446 mov r4, r0 + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 594 .loc 1 260 3 is_stmt 1 view .LVU146 + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 595 .loc 1 260 34 is_stmt 0 view .LVU147 + 596 0004 FFF7FEFF bl RCC_GetSystemClockFreq + 597 .LVL27: + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + ARM GAS /tmp/cc42qbQx.s page 109 + + + 598 .loc 1 260 32 discriminator 1 view .LVU148 + 599 0008 2060 str r0, [r4] + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 600 .loc 1 263 3 is_stmt 1 view .LVU149 + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 601 .loc 1 263 34 is_stmt 0 view .LVU150 + 602 000a FFF7FEFF bl RCC_GetHCLKClockFreq + 603 .LVL28: + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 604 .loc 1 263 32 discriminator 1 view .LVU151 + 605 000e 6060 str r0, [r4, #4] + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 606 .loc 1 266 3 is_stmt 1 view .LVU152 + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 607 .loc 1 266 34 is_stmt 0 view .LVU153 + 608 0010 FFF7FEFF bl RCC_GetPCLK1ClockFreq + 609 .LVL29: + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 610 .loc 1 266 32 discriminator 1 view .LVU154 + 611 0014 A060 str r0, [r4, #8] + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 612 .loc 1 269 3 is_stmt 1 view .LVU155 + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 613 .loc 1 269 34 is_stmt 0 view .LVU156 + 614 0016 6068 ldr r0, [r4, #4] + 615 0018 FFF7FEFF bl RCC_GetPCLK2ClockFreq + 616 .LVL30: + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 617 .loc 1 269 32 discriminator 1 view .LVU157 + 618 001c E060 str r0, [r4, #12] + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 619 .loc 1 270 1 view .LVU158 + 620 001e 10BD pop {r4, pc} + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 621 .loc 1 270 1 view .LVU159 + 622 .cfi_endproc + 623 .LFE296: + 625 .section .text.LL_RCC_GetUSARTClockFreq,"ax",%progbits + 626 .align 1 + 627 .global LL_RCC_GetUSARTClockFreq + 628 .syntax unified + 629 .thumb + 630 .thumb_func + 632 LL_RCC_GetUSARTClockFreq: + 633 .LVL31: + 634 .LFB297: + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 635 .loc 1 283 1 is_stmt 1 view -0 + 636 .cfi_startproc + 637 @ args = 0, pretend = 0, frame = 0 + 638 @ frame_needed = 0, uses_anonymous_args = 0 + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 639 .loc 1 283 1 is_stmt 0 view .LVU161 + 640 0000 08B5 push {r3, lr} + 641 .LCFI4: + 642 .cfi_def_cfa_offset 8 + 643 .cfi_offset 3, -8 + ARM GAS /tmp/cc42qbQx.s page 110 + + + 644 .cfi_offset 14, -4 + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 645 .loc 1 284 3 is_stmt 1 view .LVU162 + 646 .LVL32: + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 647 .loc 1 287 3 view .LVU163 + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 648 .loc 1 289 3 view .LVU164 + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 649 .loc 1 289 6 is_stmt 0 view .LVU165 + 650 0002 0328 cmp r0, #3 + 651 0004 08D0 beq .L67 + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 652 .loc 1 318 8 is_stmt 1 view .LVU166 + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 653 .loc 1 318 11 is_stmt 0 view .LVU167 + 654 0006 0C28 cmp r0, #12 + 655 0008 2ED0 beq .L68 + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 656 .loc 1 347 8 is_stmt 1 view .LVU168 + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 657 .loc 1 347 11 is_stmt 0 view .LVU169 + 658 000a B0F5406F cmp r0, #3072 + 659 000e 53D0 beq .L69 + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 660 .loc 1 378 5 is_stmt 1 view .LVU170 + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 661 .loc 1 378 8 is_stmt 0 view .LVU171 + 662 0010 3028 cmp r0, #48 + 663 0012 7AD0 beq .L70 + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 664 .loc 1 284 12 view .LVU172 + 665 0014 0020 movs r0, #0 + 666 .LVL33: + 667 .L40: + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 668 .loc 1 409 1 view .LVU173 + 669 0016 08BD pop {r3, pc} + 670 .LVL34: + 671 .L67: + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 672 .loc 1 292 5 is_stmt 1 view .LVU174 + 673 .LBB268: + 674 .LBI268: +2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 675 .loc 2 2664 26 view .LVU175 + 676 .LBB269: +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 677 .loc 2 2666 3 view .LVU176 +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 678 .loc 2 2666 21 is_stmt 0 view .LVU177 + 679 0018 514B ldr r3, .L71 + 680 001a D3F89030 ldr r3, [r3, #144] + 681 001e 0340 ands r3, r3, r0 +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 682 .loc 2 2666 10 view .LVU178 + 683 0020 43EA0043 orr r3, r3, r0, lsl #16 + ARM GAS /tmp/cc42qbQx.s page 111 + + + 684 .LVL35: +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 685 .loc 2 2666 10 view .LVU179 + 686 .LBE269: + 687 .LBE268: + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 688 .loc 1 292 5 discriminator 1 view .LVU180 + 689 0024 4F4A ldr r2, .L71+4 + 690 0026 9342 cmp r3, r2 + 691 0028 08D0 beq .L42 + 692 002a B3F1031F cmp r3, #196611 + 693 002e 0CD0 beq .L43 + 694 0030 013A subs r2, r2, #1 + 695 0032 9342 cmp r3, r2 + 696 0034 11D1 bne .L44 + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 697 .loc 1 295 9 is_stmt 1 view .LVU181 + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 698 .loc 1 295 27 is_stmt 0 view .LVU182 + 699 0036 FFF7FEFF bl RCC_GetSystemClockFreq + 700 .LVL36: + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 701 .loc 1 296 9 is_stmt 1 view .LVU183 + 702 003a ECE7 b .L40 + 703 .LVL37: + 704 .L42: + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 705 .loc 1 299 9 view .LVU184 + 706 .LBB270: + 707 .LBI270: +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 708 .loc 2 2030 26 view .LVU185 + 709 .LBB271: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 710 .loc 2 2032 3 view .LVU186 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 711 .loc 2 2032 11 is_stmt 0 view .LVU187 + 712 003c 484B ldr r3, .L71 + 713 003e 1868 ldr r0, [r3] + 714 .LVL38: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 715 .loc 2 2032 11 view .LVU188 + 716 .LBE271: + 717 .LBE270: + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 718 .loc 1 299 12 discriminator 1 view .LVU189 + 719 0040 10F00200 ands r0, r0, #2 + 720 0044 E7D0 beq .L40 + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 721 .loc 1 301 27 view .LVU190 + 722 0046 4848 ldr r0, .L71+8 + 723 0048 E5E7 b .L40 + 724 .LVL39: + 725 .L43: + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 726 .loc 1 306 9 is_stmt 1 view .LVU191 + 727 .LBB272: + ARM GAS /tmp/cc42qbQx.s page 112 + + + 728 .LBI272: +2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 729 .loc 2 2154 26 view .LVU192 + 730 .LBB273: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 731 .loc 2 2156 3 view .LVU193 +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 732 .loc 2 2156 11 is_stmt 0 view .LVU194 + 733 004a 454B ldr r3, .L71 + 734 004c 186F ldr r0, [r3, #112] + 735 .LVL40: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 736 .loc 2 2156 11 view .LVU195 + 737 .LBE273: + 738 .LBE272: + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 739 .loc 1 306 12 discriminator 1 view .LVU196 + 740 004e 10F00200 ands r0, r0, #2 + 741 0052 E0D0 beq .L40 + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 742 .loc 1 308 27 view .LVU197 + 743 0054 4FF40040 mov r0, #32768 + 744 0058 DDE7 b .L40 + 745 .LVL41: + 746 .L44: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 747 .loc 1 314 9 is_stmt 1 view .LVU198 + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 748 .loc 1 314 27 is_stmt 0 view .LVU199 + 749 005a FFF7FEFF bl RCC_GetSystemClockFreq + 750 .LVL42: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 751 .loc 1 314 27 discriminator 1 view .LVU200 + 752 005e FFF7FEFF bl RCC_GetHCLKClockFreq + 753 .LVL43: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 754 .loc 1 314 27 discriminator 2 view .LVU201 + 755 0062 FFF7FEFF bl RCC_GetPCLK2ClockFreq + 756 .LVL44: + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 757 .loc 1 315 9 is_stmt 1 view .LVU202 + 758 0066 D6E7 b .L40 + 759 .LVL45: + 760 .L68: + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 761 .loc 1 321 5 view .LVU203 + 762 .LBB274: + 763 .LBI274: +2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 764 .loc 2 2664 26 view .LVU204 + 765 .LBB275: +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 766 .loc 2 2666 3 view .LVU205 +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 767 .loc 2 2666 21 is_stmt 0 view .LVU206 + 768 0068 3D4B ldr r3, .L71 + 769 006a D3F89030 ldr r3, [r3, #144] + ARM GAS /tmp/cc42qbQx.s page 113 + + + 770 006e 0340 ands r3, r3, r0 +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 771 .loc 2 2666 10 view .LVU207 + 772 0070 43EA0043 orr r3, r3, r0, lsl #16 + 773 .LVL46: +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 774 .loc 2 2666 10 view .LVU208 + 775 .LBE275: + 776 .LBE274: + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 777 .loc 1 321 5 discriminator 1 view .LVU209 + 778 0074 3D4A ldr r2, .L71+12 + 779 0076 9342 cmp r3, r2 + 780 0078 08D0 beq .L47 + 781 007a B3F10C1F cmp r3, #786444 + 782 007e 0CD0 beq .L48 + 783 0080 043A subs r2, r2, #4 + 784 0082 9342 cmp r3, r2 + 785 0084 11D1 bne .L49 + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 786 .loc 1 324 9 is_stmt 1 view .LVU210 + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 787 .loc 1 324 27 is_stmt 0 view .LVU211 + 788 0086 FFF7FEFF bl RCC_GetSystemClockFreq + 789 .LVL47: + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 790 .loc 1 325 9 is_stmt 1 view .LVU212 + 791 008a C4E7 b .L40 + 792 .LVL48: + 793 .L47: + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 794 .loc 1 328 9 view .LVU213 + 795 .LBB276: + 796 .LBI276: +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 797 .loc 2 2030 26 view .LVU214 + 798 .LBB277: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 799 .loc 2 2032 3 view .LVU215 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 800 .loc 2 2032 11 is_stmt 0 view .LVU216 + 801 008c 344B ldr r3, .L71 + 802 008e 1868 ldr r0, [r3] + 803 .LVL49: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 804 .loc 2 2032 11 view .LVU217 + 805 .LBE277: + 806 .LBE276: + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 807 .loc 1 328 12 discriminator 1 view .LVU218 + 808 0090 10F00200 ands r0, r0, #2 + 809 0094 BFD0 beq .L40 + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 810 .loc 1 330 27 view .LVU219 + 811 0096 3448 ldr r0, .L71+8 + 812 0098 BDE7 b .L40 + 813 .LVL50: + ARM GAS /tmp/cc42qbQx.s page 114 + + + 814 .L48: + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 815 .loc 1 335 9 is_stmt 1 view .LVU220 + 816 .LBB278: + 817 .LBI278: +2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 818 .loc 2 2154 26 view .LVU221 + 819 .LBB279: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 820 .loc 2 2156 3 view .LVU222 +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 821 .loc 2 2156 11 is_stmt 0 view .LVU223 + 822 009a 314B ldr r3, .L71 + 823 009c 186F ldr r0, [r3, #112] + 824 .LVL51: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 825 .loc 2 2156 11 view .LVU224 + 826 .LBE279: + 827 .LBE278: + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 828 .loc 1 335 12 discriminator 1 view .LVU225 + 829 009e 10F00200 ands r0, r0, #2 + 830 00a2 B8D0 beq .L40 + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 831 .loc 1 337 27 view .LVU226 + 832 00a4 4FF40040 mov r0, #32768 + 833 00a8 B5E7 b .L40 + 834 .LVL52: + 835 .L49: + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 836 .loc 1 343 9 is_stmt 1 view .LVU227 + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 837 .loc 1 343 27 is_stmt 0 view .LVU228 + 838 00aa FFF7FEFF bl RCC_GetSystemClockFreq + 839 .LVL53: + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 840 .loc 1 343 27 discriminator 1 view .LVU229 + 841 00ae FFF7FEFF bl RCC_GetHCLKClockFreq + 842 .LVL54: + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 843 .loc 1 343 27 discriminator 2 view .LVU230 + 844 00b2 FFF7FEFF bl RCC_GetPCLK1ClockFreq + 845 .LVL55: + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 846 .loc 1 344 9 is_stmt 1 view .LVU231 + 847 00b6 AEE7 b .L40 + 848 .LVL56: + 849 .L69: + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 850 .loc 1 350 5 view .LVU232 + 851 .LBB280: + 852 .LBI280: +2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 853 .loc 2 2664 26 view .LVU233 + 854 .LBB281: +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 855 .loc 2 2666 3 view .LVU234 + ARM GAS /tmp/cc42qbQx.s page 115 + + +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 856 .loc 2 2666 21 is_stmt 0 view .LVU235 + 857 00b8 294B ldr r3, .L71 + 858 00ba D3F89030 ldr r3, [r3, #144] + 859 00be 0340 ands r3, r3, r0 +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 860 .loc 2 2666 10 view .LVU236 + 861 00c0 43EA0043 orr r3, r3, r0, lsl #16 + 862 .LVL57: +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 863 .loc 2 2666 10 view .LVU237 + 864 .LBE281: + 865 .LBE280: + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 866 .loc 1 350 5 discriminator 1 view .LVU238 + 867 00c4 2A4A ldr r2, .L71+16 + 868 00c6 9342 cmp r3, r2 + 869 00c8 09D0 beq .L51 + 870 00ca B3F10C2F cmp r3, #201329664 + 871 00ce 0DD0 beq .L52 + 872 00d0 A2F58062 sub r2, r2, #1024 + 873 00d4 9342 cmp r3, r2 + 874 00d6 11D1 bne .L53 + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 875 .loc 1 353 9 is_stmt 1 view .LVU239 + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 876 .loc 1 353 27 is_stmt 0 view .LVU240 + 877 00d8 FFF7FEFF bl RCC_GetSystemClockFreq + 878 .LVL58: + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 879 .loc 1 354 9 is_stmt 1 view .LVU241 + 880 00dc 9BE7 b .L40 + 881 .LVL59: + 882 .L51: + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 883 .loc 1 357 9 view .LVU242 + 884 .LBB282: + 885 .LBI282: +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 886 .loc 2 2030 26 view .LVU243 + 887 .LBB283: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 888 .loc 2 2032 3 view .LVU244 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 889 .loc 2 2032 11 is_stmt 0 view .LVU245 + 890 00de 204B ldr r3, .L71 + 891 00e0 1868 ldr r0, [r3] + 892 .LVL60: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 893 .loc 2 2032 11 view .LVU246 + 894 .LBE283: + 895 .LBE282: + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 896 .loc 1 357 12 discriminator 1 view .LVU247 + 897 00e2 10F00200 ands r0, r0, #2 + 898 00e6 96D0 beq .L40 + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + ARM GAS /tmp/cc42qbQx.s page 116 + + + 899 .loc 1 359 27 view .LVU248 + 900 00e8 1F48 ldr r0, .L71+8 + 901 00ea 94E7 b .L40 + 902 .LVL61: + 903 .L52: + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 904 .loc 1 364 9 is_stmt 1 view .LVU249 + 905 .LBB284: + 906 .LBI284: +2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 907 .loc 2 2154 26 view .LVU250 + 908 .LBB285: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 909 .loc 2 2156 3 view .LVU251 +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 910 .loc 2 2156 11 is_stmt 0 view .LVU252 + 911 00ec 1C4B ldr r3, .L71 + 912 00ee 186F ldr r0, [r3, #112] + 913 .LVL62: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 914 .loc 2 2156 11 view .LVU253 + 915 .LBE285: + 916 .LBE284: + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 917 .loc 1 364 12 discriminator 1 view .LVU254 + 918 00f0 10F00200 ands r0, r0, #2 + 919 00f4 8FD0 beq .L40 + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 920 .loc 1 366 27 view .LVU255 + 921 00f6 4FF40040 mov r0, #32768 + 922 00fa 8CE7 b .L40 + 923 .LVL63: + 924 .L53: + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 925 .loc 1 372 9 is_stmt 1 view .LVU256 + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 926 .loc 1 372 27 is_stmt 0 view .LVU257 + 927 00fc FFF7FEFF bl RCC_GetSystemClockFreq + 928 .LVL64: + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 929 .loc 1 372 27 discriminator 1 view .LVU258 + 930 0100 FFF7FEFF bl RCC_GetHCLKClockFreq + 931 .LVL65: + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 932 .loc 1 372 27 discriminator 2 view .LVU259 + 933 0104 FFF7FEFF bl RCC_GetPCLK2ClockFreq + 934 .LVL66: + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 935 .loc 1 373 9 is_stmt 1 view .LVU260 + 936 0108 85E7 b .L40 + 937 .LVL67: + 938 .L70: + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 939 .loc 1 381 7 view .LVU261 + 940 .LBB286: + 941 .LBI286: +2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + ARM GAS /tmp/cc42qbQx.s page 117 + + + 942 .loc 2 2664 26 view .LVU262 + 943 .LBB287: +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 944 .loc 2 2666 3 view .LVU263 +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 945 .loc 2 2666 21 is_stmt 0 view .LVU264 + 946 010a 154B ldr r3, .L71 + 947 010c D3F89030 ldr r3, [r3, #144] + 948 0110 0340 ands r3, r3, r0 +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 949 .loc 2 2666 10 view .LVU265 + 950 0112 43EA0043 orr r3, r3, r0, lsl #16 + 951 .LVL68: +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 952 .loc 2 2666 10 view .LVU266 + 953 .LBE287: + 954 .LBE286: + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 955 .loc 1 381 7 discriminator 1 view .LVU267 + 956 0116 174A ldr r2, .L71+20 + 957 0118 9342 cmp r3, r2 + 958 011a 08D0 beq .L54 + 959 011c B3F1301F cmp r3, #3145776 + 960 0120 0DD0 beq .L55 + 961 0122 103A subs r2, r2, #16 + 962 0124 9342 cmp r3, r2 + 963 0126 13D1 bne .L56 + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 964 .loc 1 384 11 is_stmt 1 view .LVU268 + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 965 .loc 1 384 29 is_stmt 0 view .LVU269 + 966 0128 FFF7FEFF bl RCC_GetSystemClockFreq + 967 .LVL69: + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 968 .loc 1 385 11 is_stmt 1 view .LVU270 + 969 012c 73E7 b .L40 + 970 .LVL70: + 971 .L54: + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 972 .loc 1 388 11 view .LVU271 + 973 .LBB288: + 974 .LBI288: +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 975 .loc 2 2030 26 view .LVU272 + 976 .LBB289: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 977 .loc 2 2032 3 view .LVU273 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 978 .loc 2 2032 11 is_stmt 0 view .LVU274 + 979 012e 0C4B ldr r3, .L71 + 980 0130 1868 ldr r0, [r3] + 981 .LVL71: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 982 .loc 2 2032 11 view .LVU275 + 983 .LBE289: + 984 .LBE288: + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + ARM GAS /tmp/cc42qbQx.s page 118 + + + 985 .loc 1 388 14 discriminator 1 view .LVU276 + 986 0132 10F00200 ands r0, r0, #2 + 987 0136 3FF46EAF beq .L40 + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 988 .loc 1 390 29 view .LVU277 + 989 013a 0B48 ldr r0, .L71+8 + 990 013c 6BE7 b .L40 + 991 .LVL72: + 992 .L55: + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 993 .loc 1 395 11 is_stmt 1 view .LVU278 + 994 .LBB290: + 995 .LBI290: +2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 996 .loc 2 2154 26 view .LVU279 + 997 .LBB291: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 998 .loc 2 2156 3 view .LVU280 +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 999 .loc 2 2156 11 is_stmt 0 view .LVU281 + 1000 013e 084B ldr r3, .L71 + 1001 0140 186F ldr r0, [r3, #112] + 1002 .LVL73: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1003 .loc 2 2156 11 view .LVU282 + 1004 .LBE291: + 1005 .LBE290: + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1006 .loc 1 395 14 discriminator 1 view .LVU283 + 1007 0142 10F00200 ands r0, r0, #2 + 1008 0146 3FF466AF beq .L40 + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1009 .loc 1 397 29 view .LVU284 + 1010 014a 4FF40040 mov r0, #32768 + 1011 .LVL74: + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1012 .loc 1 408 3 is_stmt 1 view .LVU285 + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1013 .loc 1 408 10 is_stmt 0 view .LVU286 + 1014 014e 62E7 b .L40 + 1015 .LVL75: + 1016 .L56: + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1017 .loc 1 403 11 is_stmt 1 view .LVU287 + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1018 .loc 1 403 29 is_stmt 0 view .LVU288 + 1019 0150 FFF7FEFF bl RCC_GetSystemClockFreq + 1020 .LVL76: + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1021 .loc 1 403 29 discriminator 1 view .LVU289 + 1022 0154 FFF7FEFF bl RCC_GetHCLKClockFreq + 1023 .LVL77: + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1024 .loc 1 403 29 discriminator 2 view .LVU290 + 1025 0158 FFF7FEFF bl RCC_GetPCLK1ClockFreq + 1026 .LVL78: + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + ARM GAS /tmp/cc42qbQx.s page 119 + + + 1027 .loc 1 404 11 is_stmt 1 view .LVU291 + 1028 015c 5BE7 b .L40 + 1029 .L72: + 1030 015e 00BF .align 2 + 1031 .L71: + 1032 0160 00380240 .word 1073887232 + 1033 0164 02000300 .word 196610 + 1034 0168 0024F400 .word 16000000 + 1035 016c 08000C00 .word 786440 + 1036 0170 0008000C .word 201328640 + 1037 0174 20003000 .word 3145760 + 1038 .cfi_endproc + 1039 .LFE297: + 1041 .section .text.LL_RCC_GetUARTClockFreq,"ax",%progbits + 1042 .align 1 + 1043 .global LL_RCC_GetUARTClockFreq + 1044 .syntax unified + 1045 .thumb + 1046 .thumb_func + 1048 LL_RCC_GetUARTClockFreq: + 1049 .LVL79: + 1050 .LFB298: + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 1051 .loc 1 422 1 view -0 + 1052 .cfi_startproc + 1053 @ args = 0, pretend = 0, frame = 0 + 1054 @ frame_needed = 0, uses_anonymous_args = 0 + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 1055 .loc 1 422 1 is_stmt 0 view .LVU293 + 1056 0000 08B5 push {r3, lr} + 1057 .LCFI5: + 1058 .cfi_def_cfa_offset 8 + 1059 .cfi_offset 3, -8 + 1060 .cfi_offset 14, -4 + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1061 .loc 1 423 3 is_stmt 1 view .LVU294 + 1062 .LVL80: + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1063 .loc 1 426 3 view .LVU295 + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1064 .loc 1 428 3 view .LVU296 + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1065 .loc 1 428 6 is_stmt 0 view .LVU297 + 1066 0002 C028 cmp r0, #192 + 1067 0004 0AD0 beq .L100 + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1068 .loc 1 457 8 is_stmt 1 view .LVU298 + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1069 .loc 1 457 11 is_stmt 0 view .LVU299 + 1070 0006 B0F5407F cmp r0, #768 + 1071 000a 2FD0 beq .L101 + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1072 .loc 1 486 8 is_stmt 1 view .LVU300 + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1073 .loc 1 486 11 is_stmt 0 view .LVU301 + 1074 000c B0F5405F cmp r0, #12288 + 1075 0010 55D0 beq .L102 + ARM GAS /tmp/cc42qbQx.s page 120 + + + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1076 .loc 1 517 5 is_stmt 1 view .LVU302 + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1077 .loc 1 517 8 is_stmt 0 view .LVU303 + 1078 0012 B0F5404F cmp r0, #49152 + 1079 0016 7BD0 beq .L103 + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1080 .loc 1 423 12 view .LVU304 + 1081 0018 0020 movs r0, #0 + 1082 .LVL81: + 1083 .L73: + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1084 .loc 1 548 1 view .LVU305 + 1085 001a 08BD pop {r3, pc} + 1086 .LVL82: + 1087 .L100: + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1088 .loc 1 431 5 is_stmt 1 view .LVU306 + 1089 .LBB292: + 1090 .LBI292: +2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1091 .loc 2 2698 26 view .LVU307 + 1092 .LBB293: +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1093 .loc 2 2700 3 view .LVU308 +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1094 .loc 2 2700 21 is_stmt 0 view .LVU309 + 1095 001c 524B ldr r3, .L104 + 1096 001e D3F89030 ldr r3, [r3, #144] + 1097 0022 0340 ands r3, r3, r0 +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1098 .loc 2 2700 10 view .LVU310 + 1099 0024 43EA0043 orr r3, r3, r0, lsl #16 + 1100 .LVL83: +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1101 .loc 2 2700 10 view .LVU311 + 1102 .LBE293: + 1103 .LBE292: + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1104 .loc 1 431 5 discriminator 1 view .LVU312 + 1105 0028 504A ldr r2, .L104+4 + 1106 002a 9342 cmp r3, r2 + 1107 002c 08D0 beq .L75 + 1108 002e B3F1C01F cmp r3, #12583104 + 1109 0032 0CD0 beq .L76 + 1110 0034 403A subs r2, r2, #64 + 1111 0036 9342 cmp r3, r2 + 1112 0038 11D1 bne .L77 + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1113 .loc 1 434 9 is_stmt 1 view .LVU313 + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1114 .loc 1 434 26 is_stmt 0 view .LVU314 + 1115 003a FFF7FEFF bl RCC_GetSystemClockFreq + 1116 .LVL84: + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1117 .loc 1 435 9 is_stmt 1 view .LVU315 + 1118 003e ECE7 b .L73 + ARM GAS /tmp/cc42qbQx.s page 121 + + + 1119 .LVL85: + 1120 .L75: + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1121 .loc 1 438 9 view .LVU316 + 1122 .LBB294: + 1123 .LBI294: +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1124 .loc 2 2030 26 view .LVU317 + 1125 .LBB295: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1126 .loc 2 2032 3 view .LVU318 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1127 .loc 2 2032 11 is_stmt 0 view .LVU319 + 1128 0040 494B ldr r3, .L104 + 1129 0042 1868 ldr r0, [r3] + 1130 .LVL86: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1131 .loc 2 2032 11 view .LVU320 + 1132 .LBE295: + 1133 .LBE294: + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1134 .loc 1 438 12 discriminator 1 view .LVU321 + 1135 0044 10F00200 ands r0, r0, #2 + 1136 0048 E7D0 beq .L73 + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1137 .loc 1 440 26 view .LVU322 + 1138 004a 4948 ldr r0, .L104+8 + 1139 004c E5E7 b .L73 + 1140 .LVL87: + 1141 .L76: + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1142 .loc 1 445 9 is_stmt 1 view .LVU323 + 1143 .LBB296: + 1144 .LBI296: +2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1145 .loc 2 2154 26 view .LVU324 + 1146 .LBB297: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1147 .loc 2 2156 3 view .LVU325 +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1148 .loc 2 2156 11 is_stmt 0 view .LVU326 + 1149 004e 464B ldr r3, .L104 + 1150 0050 186F ldr r0, [r3, #112] + 1151 .LVL88: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1152 .loc 2 2156 11 view .LVU327 + 1153 .LBE297: + 1154 .LBE296: + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1155 .loc 1 445 12 discriminator 1 view .LVU328 + 1156 0052 10F00200 ands r0, r0, #2 + 1157 0056 E0D0 beq .L73 + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1158 .loc 1 447 26 view .LVU329 + 1159 0058 4FF40040 mov r0, #32768 + 1160 005c DDE7 b .L73 + 1161 .LVL89: + ARM GAS /tmp/cc42qbQx.s page 122 + + + 1162 .L77: + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1163 .loc 1 453 9 is_stmt 1 view .LVU330 + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1164 .loc 1 453 26 is_stmt 0 view .LVU331 + 1165 005e FFF7FEFF bl RCC_GetSystemClockFreq + 1166 .LVL90: + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1167 .loc 1 453 26 discriminator 1 view .LVU332 + 1168 0062 FFF7FEFF bl RCC_GetHCLKClockFreq + 1169 .LVL91: + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1170 .loc 1 453 26 discriminator 2 view .LVU333 + 1171 0066 FFF7FEFF bl RCC_GetPCLK1ClockFreq + 1172 .LVL92: + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1173 .loc 1 454 9 is_stmt 1 view .LVU334 + 1174 006a D6E7 b .L73 + 1175 .LVL93: + 1176 .L101: + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1177 .loc 1 460 5 view .LVU335 + 1178 .LBB298: + 1179 .LBI298: +2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1180 .loc 2 2698 26 view .LVU336 + 1181 .LBB299: +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1182 .loc 2 2700 3 view .LVU337 +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1183 .loc 2 2700 21 is_stmt 0 view .LVU338 + 1184 006c 3E4B ldr r3, .L104 + 1185 006e D3F89030 ldr r3, [r3, #144] + 1186 0072 0340 ands r3, r3, r0 +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1187 .loc 2 2700 10 view .LVU339 + 1188 0074 43EA0043 orr r3, r3, r0, lsl #16 + 1189 .LVL94: +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1190 .loc 2 2700 10 view .LVU340 + 1191 .LBE299: + 1192 .LBE298: + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1193 .loc 1 460 5 discriminator 1 view .LVU341 + 1194 0078 3E4A ldr r2, .L104+12 + 1195 007a 9342 cmp r3, r2 + 1196 007c 09D0 beq .L80 + 1197 007e B3F1032F cmp r3, #50332416 + 1198 0082 0DD0 beq .L81 + 1199 0084 A2F58072 sub r2, r2, #256 + 1200 0088 9342 cmp r3, r2 + 1201 008a 11D1 bne .L82 + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1202 .loc 1 463 9 is_stmt 1 view .LVU342 + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1203 .loc 1 463 26 is_stmt 0 view .LVU343 + 1204 008c FFF7FEFF bl RCC_GetSystemClockFreq + ARM GAS /tmp/cc42qbQx.s page 123 + + + 1205 .LVL95: + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1206 .loc 1 464 9 is_stmt 1 view .LVU344 + 1207 0090 C3E7 b .L73 + 1208 .LVL96: + 1209 .L80: + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1210 .loc 1 467 9 view .LVU345 + 1211 .LBB300: + 1212 .LBI300: +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1213 .loc 2 2030 26 view .LVU346 + 1214 .LBB301: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1215 .loc 2 2032 3 view .LVU347 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1216 .loc 2 2032 11 is_stmt 0 view .LVU348 + 1217 0092 354B ldr r3, .L104 + 1218 0094 1868 ldr r0, [r3] + 1219 .LVL97: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1220 .loc 2 2032 11 view .LVU349 + 1221 .LBE301: + 1222 .LBE300: + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1223 .loc 1 467 12 discriminator 1 view .LVU350 + 1224 0096 10F00200 ands r0, r0, #2 + 1225 009a BED0 beq .L73 + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1226 .loc 1 469 26 view .LVU351 + 1227 009c 3448 ldr r0, .L104+8 + 1228 009e BCE7 b .L73 + 1229 .LVL98: + 1230 .L81: + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1231 .loc 1 474 9 is_stmt 1 view .LVU352 + 1232 .LBB302: + 1233 .LBI302: +2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1234 .loc 2 2154 26 view .LVU353 + 1235 .LBB303: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1236 .loc 2 2156 3 view .LVU354 +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1237 .loc 2 2156 11 is_stmt 0 view .LVU355 + 1238 00a0 314B ldr r3, .L104 + 1239 00a2 186F ldr r0, [r3, #112] + 1240 .LVL99: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1241 .loc 2 2156 11 view .LVU356 + 1242 .LBE303: + 1243 .LBE302: + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1244 .loc 1 474 12 discriminator 1 view .LVU357 + 1245 00a4 10F00200 ands r0, r0, #2 + 1246 00a8 B7D0 beq .L73 + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + ARM GAS /tmp/cc42qbQx.s page 124 + + + 1247 .loc 1 476 26 view .LVU358 + 1248 00aa 4FF40040 mov r0, #32768 + 1249 00ae B4E7 b .L73 + 1250 .LVL100: + 1251 .L82: + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1252 .loc 1 482 9 is_stmt 1 view .LVU359 + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1253 .loc 1 482 26 is_stmt 0 view .LVU360 + 1254 00b0 FFF7FEFF bl RCC_GetSystemClockFreq + 1255 .LVL101: + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1256 .loc 1 482 26 discriminator 1 view .LVU361 + 1257 00b4 FFF7FEFF bl RCC_GetHCLKClockFreq + 1258 .LVL102: + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1259 .loc 1 482 26 discriminator 2 view .LVU362 + 1260 00b8 FFF7FEFF bl RCC_GetPCLK1ClockFreq + 1261 .LVL103: + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1262 .loc 1 483 9 is_stmt 1 view .LVU363 + 1263 00bc ADE7 b .L73 + 1264 .LVL104: + 1265 .L102: + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1266 .loc 1 489 5 view .LVU364 + 1267 .LBB304: + 1268 .LBI304: +2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1269 .loc 2 2698 26 view .LVU365 + 1270 .LBB305: +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1271 .loc 2 2700 3 view .LVU366 +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1272 .loc 2 2700 21 is_stmt 0 view .LVU367 + 1273 00be 2A4B ldr r3, .L104 + 1274 00c0 D3F89030 ldr r3, [r3, #144] + 1275 00c4 0340 ands r3, r3, r0 +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1276 .loc 2 2700 10 view .LVU368 + 1277 00c6 43EA0043 orr r3, r3, r0, lsl #16 + 1278 .LVL105: +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1279 .loc 2 2700 10 view .LVU369 + 1280 .LBE305: + 1281 .LBE304: + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1282 .loc 1 489 5 discriminator 1 view .LVU370 + 1283 00ca 2B4A ldr r2, .L104+16 + 1284 00cc 9342 cmp r3, r2 + 1285 00ce 09D0 beq .L84 + 1286 00d0 B3F1302F cmp r3, #805318656 + 1287 00d4 0DD0 beq .L85 + 1288 00d6 A2F58052 sub r2, r2, #4096 + 1289 00da 9342 cmp r3, r2 + 1290 00dc 11D1 bne .L86 + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + ARM GAS /tmp/cc42qbQx.s page 125 + + + 1291 .loc 1 492 9 is_stmt 1 view .LVU371 + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1292 .loc 1 492 26 is_stmt 0 view .LVU372 + 1293 00de FFF7FEFF bl RCC_GetSystemClockFreq + 1294 .LVL106: + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1295 .loc 1 493 9 is_stmt 1 view .LVU373 + 1296 00e2 9AE7 b .L73 + 1297 .LVL107: + 1298 .L84: + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1299 .loc 1 496 9 view .LVU374 + 1300 .LBB306: + 1301 .LBI306: +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1302 .loc 2 2030 26 view .LVU375 + 1303 .LBB307: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1304 .loc 2 2032 3 view .LVU376 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1305 .loc 2 2032 11 is_stmt 0 view .LVU377 + 1306 00e4 204B ldr r3, .L104 + 1307 00e6 1868 ldr r0, [r3] + 1308 .LVL108: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1309 .loc 2 2032 11 view .LVU378 + 1310 .LBE307: + 1311 .LBE306: + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1312 .loc 1 496 12 discriminator 1 view .LVU379 + 1313 00e8 10F00200 ands r0, r0, #2 + 1314 00ec 95D0 beq .L73 + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1315 .loc 1 498 26 view .LVU380 + 1316 00ee 2048 ldr r0, .L104+8 + 1317 00f0 93E7 b .L73 + 1318 .LVL109: + 1319 .L85: + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1320 .loc 1 503 9 is_stmt 1 view .LVU381 + 1321 .LBB308: + 1322 .LBI308: +2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1323 .loc 2 2154 26 view .LVU382 + 1324 .LBB309: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1325 .loc 2 2156 3 view .LVU383 +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1326 .loc 2 2156 11 is_stmt 0 view .LVU384 + 1327 00f2 1D4B ldr r3, .L104 + 1328 00f4 186F ldr r0, [r3, #112] + 1329 .LVL110: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1330 .loc 2 2156 11 view .LVU385 + 1331 .LBE309: + 1332 .LBE308: + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + ARM GAS /tmp/cc42qbQx.s page 126 + + + 1333 .loc 1 503 12 discriminator 1 view .LVU386 + 1334 00f6 10F00200 ands r0, r0, #2 + 1335 00fa 8ED0 beq .L73 + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1336 .loc 1 505 26 view .LVU387 + 1337 00fc 4FF40040 mov r0, #32768 + 1338 0100 8BE7 b .L73 + 1339 .LVL111: + 1340 .L86: + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1341 .loc 1 511 9 is_stmt 1 view .LVU388 + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1342 .loc 1 511 26 is_stmt 0 view .LVU389 + 1343 0102 FFF7FEFF bl RCC_GetSystemClockFreq + 1344 .LVL112: + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1345 .loc 1 511 26 discriminator 1 view .LVU390 + 1346 0106 FFF7FEFF bl RCC_GetHCLKClockFreq + 1347 .LVL113: + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1348 .loc 1 511 26 discriminator 2 view .LVU391 + 1349 010a FFF7FEFF bl RCC_GetPCLK1ClockFreq + 1350 .LVL114: + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1351 .loc 1 512 9 is_stmt 1 view .LVU392 + 1352 010e 84E7 b .L73 + 1353 .LVL115: + 1354 .L103: + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1355 .loc 1 520 7 view .LVU393 + 1356 .LBB310: + 1357 .LBI310: +2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1358 .loc 2 2698 26 view .LVU394 + 1359 .LBB311: +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1360 .loc 2 2700 3 view .LVU395 +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1361 .loc 2 2700 21 is_stmt 0 view .LVU396 + 1362 0110 154B ldr r3, .L104 + 1363 0112 D3F89030 ldr r3, [r3, #144] + 1364 0116 0340 ands r3, r3, r0 +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1365 .loc 2 2700 10 view .LVU397 + 1366 0118 43EA0043 orr r3, r3, r0, lsl #16 + 1367 .LVL116: +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1368 .loc 2 2700 10 view .LVU398 + 1369 .LBE311: + 1370 .LBE310: + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1371 .loc 1 520 7 discriminator 1 view .LVU399 + 1372 011c 174A ldr r2, .L104+20 + 1373 011e 9342 cmp r3, r2 + 1374 0120 09D0 beq .L87 + 1375 0122 B3F1C02F cmp r3, #-1073692672 + 1376 0126 0ED0 beq .L88 + ARM GAS /tmp/cc42qbQx.s page 127 + + + 1377 0128 A2F58042 sub r2, r2, #16384 + 1378 012c 9342 cmp r3, r2 + 1379 012e 13D1 bne .L89 + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1380 .loc 1 523 11 is_stmt 1 view .LVU400 + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1381 .loc 1 523 28 is_stmt 0 view .LVU401 + 1382 0130 FFF7FEFF bl RCC_GetSystemClockFreq + 1383 .LVL117: + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1384 .loc 1 524 11 is_stmt 1 view .LVU402 + 1385 0134 71E7 b .L73 + 1386 .LVL118: + 1387 .L87: + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1388 .loc 1 527 11 view .LVU403 + 1389 .LBB312: + 1390 .LBI312: +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1391 .loc 2 2030 26 view .LVU404 + 1392 .LBB313: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1393 .loc 2 2032 3 view .LVU405 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1394 .loc 2 2032 11 is_stmt 0 view .LVU406 + 1395 0136 0C4B ldr r3, .L104 + 1396 0138 1868 ldr r0, [r3] + 1397 .LVL119: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1398 .loc 2 2032 11 view .LVU407 + 1399 .LBE313: + 1400 .LBE312: + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1401 .loc 1 527 14 discriminator 1 view .LVU408 + 1402 013a 10F00200 ands r0, r0, #2 + 1403 013e 3FF46CAF beq .L73 + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1404 .loc 1 529 28 view .LVU409 + 1405 0142 0B48 ldr r0, .L104+8 + 1406 0144 69E7 b .L73 + 1407 .LVL120: + 1408 .L88: + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1409 .loc 1 534 11 is_stmt 1 view .LVU410 + 1410 .LBB314: + 1411 .LBI314: +2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1412 .loc 2 2154 26 view .LVU411 + 1413 .LBB315: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1414 .loc 2 2156 3 view .LVU412 +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1415 .loc 2 2156 11 is_stmt 0 view .LVU413 + 1416 0146 084B ldr r3, .L104 + 1417 0148 186F ldr r0, [r3, #112] + 1418 .LVL121: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + ARM GAS /tmp/cc42qbQx.s page 128 + + + 1419 .loc 2 2156 11 view .LVU414 + 1420 .LBE315: + 1421 .LBE314: + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1422 .loc 1 534 14 discriminator 1 view .LVU415 + 1423 014a 10F00200 ands r0, r0, #2 + 1424 014e 3FF464AF beq .L73 + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1425 .loc 1 536 28 view .LVU416 + 1426 0152 4FF40040 mov r0, #32768 + 1427 .LVL122: + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1428 .loc 1 547 3 is_stmt 1 view .LVU417 + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1429 .loc 1 547 10 is_stmt 0 view .LVU418 + 1430 0156 60E7 b .L73 + 1431 .LVL123: + 1432 .L89: + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1433 .loc 1 542 11 is_stmt 1 view .LVU419 + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1434 .loc 1 542 28 is_stmt 0 view .LVU420 + 1435 0158 FFF7FEFF bl RCC_GetSystemClockFreq + 1436 .LVL124: + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1437 .loc 1 542 28 discriminator 1 view .LVU421 + 1438 015c FFF7FEFF bl RCC_GetHCLKClockFreq + 1439 .LVL125: + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1440 .loc 1 542 28 discriminator 2 view .LVU422 + 1441 0160 FFF7FEFF bl RCC_GetPCLK1ClockFreq + 1442 .LVL126: + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1443 .loc 1 543 11 is_stmt 1 view .LVU423 + 1444 0164 59E7 b .L73 + 1445 .L105: + 1446 0166 00BF .align 2 + 1447 .L104: + 1448 0168 00380240 .word 1073887232 + 1449 016c 8000C000 .word 12583040 + 1450 0170 0024F400 .word 16000000 + 1451 0174 00020003 .word 50332160 + 1452 0178 00200030 .word 805314560 + 1453 017c 008000C0 .word -1073709056 + 1454 .cfi_endproc + 1455 .LFE298: + 1457 .section .text.LL_RCC_GetI2CClockFreq,"ax",%progbits + 1458 .align 1 + 1459 .global LL_RCC_GetI2CClockFreq + 1460 .syntax unified + 1461 .thumb + 1462 .thumb_func + 1464 LL_RCC_GetI2CClockFreq: + 1465 .LVL127: + 1466 .LFB299: + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 1467 .loc 1 563 1 view -0 + ARM GAS /tmp/cc42qbQx.s page 129 + + + 1468 .cfi_startproc + 1469 @ args = 0, pretend = 0, frame = 0 + 1470 @ frame_needed = 0, uses_anonymous_args = 0 + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 1471 .loc 1 563 1 is_stmt 0 view .LVU425 + 1472 0000 08B5 push {r3, lr} + 1473 .LCFI6: + 1474 .cfi_def_cfa_offset 8 + 1475 .cfi_offset 3, -8 + 1476 .cfi_offset 14, -4 + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1477 .loc 1 564 3 is_stmt 1 view .LVU426 + 1478 .LVL128: + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1479 .loc 1 567 3 view .LVU427 + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1480 .loc 1 569 3 view .LVU428 + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1481 .loc 1 569 6 is_stmt 0 view .LVU429 + 1482 0002 B0F5403F cmp r0, #196608 + 1483 0006 0AD0 beq .L133 + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1484 .loc 1 591 8 is_stmt 1 view .LVU430 + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1485 .loc 1 591 11 is_stmt 0 view .LVU431 + 1486 0008 B0F5402F cmp r0, #786432 + 1487 000c 24D0 beq .L134 + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1488 .loc 1 613 8 is_stmt 1 view .LVU432 + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1489 .loc 1 613 11 is_stmt 0 view .LVU433 + 1490 000e B0F5401F cmp r0, #3145728 + 1491 0012 3ED0 beq .L135 + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1492 .loc 1 638 5 is_stmt 1 view .LVU434 + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1493 .loc 1 638 8 is_stmt 0 view .LVU435 + 1494 0014 B0F5400F cmp r0, #12582912 + 1495 0018 58D0 beq .L136 + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1496 .loc 1 564 12 view .LVU436 + 1497 001a 0020 movs r0, #0 + 1498 .LVL129: + 1499 .L106: + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1500 .loc 1 669 1 view .LVU437 + 1501 001c 08BD pop {r3, pc} + 1502 .LVL130: + 1503 .L133: + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1504 .loc 1 572 5 is_stmt 1 view .LVU438 + 1505 .LBB316: + 1506 .LBI316: +2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1507 .loc 2 2730 26 view .LVU439 + 1508 .LBB317: +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + ARM GAS /tmp/cc42qbQx.s page 130 + + + 1509 .loc 2 2732 3 view .LVU440 +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1510 .loc 2 2732 22 is_stmt 0 view .LVU441 + 1511 001e 3A4B ldr r3, .L137 + 1512 0020 D3F89030 ldr r3, [r3, #144] + 1513 0024 0340 ands r3, r3, r0 +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1514 .loc 2 2732 10 view .LVU442 + 1515 0026 40EA1340 orr r0, r0, r3, lsr #16 + 1516 .LVL131: +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1517 .loc 2 2732 10 view .LVU443 + 1518 .LBE317: + 1519 .LBE316: + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1520 .loc 1 572 5 discriminator 1 view .LVU444 + 1521 002a 384B ldr r3, .L137+4 + 1522 002c 9842 cmp r0, r3 + 1523 002e 09D0 beq .L108 + 1524 0030 0133 adds r3, r3, #1 + 1525 0032 9842 cmp r0, r3 + 1526 0034 09D0 beq .L109 + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1527 .loc 1 587 9 is_stmt 1 view .LVU445 + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1528 .loc 1 587 25 is_stmt 0 view .LVU446 + 1529 0036 FFF7FEFF bl RCC_GetSystemClockFreq + 1530 .LVL132: + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1531 .loc 1 587 25 discriminator 1 view .LVU447 + 1532 003a FFF7FEFF bl RCC_GetHCLKClockFreq + 1533 .LVL133: + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1534 .loc 1 587 25 discriminator 2 view .LVU448 + 1535 003e FFF7FEFF bl RCC_GetPCLK1ClockFreq + 1536 .LVL134: + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1537 .loc 1 588 9 is_stmt 1 view .LVU449 + 1538 0042 EBE7 b .L106 + 1539 .LVL135: + 1540 .L108: + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1541 .loc 1 575 9 view .LVU450 + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1542 .loc 1 575 25 is_stmt 0 view .LVU451 + 1543 0044 FFF7FEFF bl RCC_GetSystemClockFreq + 1544 .LVL136: + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1545 .loc 1 576 9 is_stmt 1 view .LVU452 + 1546 0048 E8E7 b .L106 + 1547 .LVL137: + 1548 .L109: + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1549 .loc 1 579 9 view .LVU453 + 1550 .LBB318: + 1551 .LBI318: +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + ARM GAS /tmp/cc42qbQx.s page 131 + + + 1552 .loc 2 2030 26 view .LVU454 + 1553 .LBB319: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1554 .loc 2 2032 3 view .LVU455 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1555 .loc 2 2032 11 is_stmt 0 view .LVU456 + 1556 004a 2F4B ldr r3, .L137 + 1557 004c 1868 ldr r0, [r3] + 1558 .LBE319: + 1559 .LBE318: + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1560 .loc 1 579 12 discriminator 1 view .LVU457 + 1561 004e 10F00200 ands r0, r0, #2 + 1562 0052 E3D0 beq .L106 + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1563 .loc 1 581 25 view .LVU458 + 1564 0054 2E48 ldr r0, .L137+8 + 1565 0056 E1E7 b .L106 + 1566 .LVL138: + 1567 .L134: + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1568 .loc 1 594 5 is_stmt 1 view .LVU459 + 1569 .LBB320: + 1570 .LBI320: +2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1571 .loc 2 2730 26 view .LVU460 + 1572 .LBB321: +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1573 .loc 2 2732 3 view .LVU461 +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1574 .loc 2 2732 22 is_stmt 0 view .LVU462 + 1575 0058 2B4B ldr r3, .L137 + 1576 005a D3F89030 ldr r3, [r3, #144] + 1577 005e 0340 ands r3, r3, r0 +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1578 .loc 2 2732 10 view .LVU463 + 1579 0060 40EA1340 orr r0, r0, r3, lsr #16 + 1580 .LVL139: +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1581 .loc 2 2732 10 view .LVU464 + 1582 .LBE321: + 1583 .LBE320: + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1584 .loc 1 594 5 discriminator 1 view .LVU465 + 1585 0064 2B4B ldr r3, .L137+12 + 1586 0066 9842 cmp r0, r3 + 1587 0068 09D0 beq .L113 + 1588 006a 0433 adds r3, r3, #4 + 1589 006c 9842 cmp r0, r3 + 1590 006e 09D0 beq .L114 + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1591 .loc 1 609 9 is_stmt 1 view .LVU466 + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1592 .loc 1 609 25 is_stmt 0 view .LVU467 + 1593 0070 FFF7FEFF bl RCC_GetSystemClockFreq + 1594 .LVL140: + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + ARM GAS /tmp/cc42qbQx.s page 132 + + + 1595 .loc 1 609 25 discriminator 1 view .LVU468 + 1596 0074 FFF7FEFF bl RCC_GetHCLKClockFreq + 1597 .LVL141: + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1598 .loc 1 609 25 discriminator 2 view .LVU469 + 1599 0078 FFF7FEFF bl RCC_GetPCLK1ClockFreq + 1600 .LVL142: + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1601 .loc 1 610 9 is_stmt 1 view .LVU470 + 1602 007c CEE7 b .L106 + 1603 .LVL143: + 1604 .L113: + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1605 .loc 1 597 9 view .LVU471 + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1606 .loc 1 597 25 is_stmt 0 view .LVU472 + 1607 007e FFF7FEFF bl RCC_GetSystemClockFreq + 1608 .LVL144: + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1609 .loc 1 598 9 is_stmt 1 view .LVU473 + 1610 0082 CBE7 b .L106 + 1611 .LVL145: + 1612 .L114: + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1613 .loc 1 601 9 view .LVU474 + 1614 .LBB322: + 1615 .LBI322: +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1616 .loc 2 2030 26 view .LVU475 + 1617 .LBB323: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1618 .loc 2 2032 3 view .LVU476 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1619 .loc 2 2032 11 is_stmt 0 view .LVU477 + 1620 0084 204B ldr r3, .L137 + 1621 0086 1868 ldr r0, [r3] + 1622 .LBE323: + 1623 .LBE322: + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1624 .loc 1 601 12 discriminator 1 view .LVU478 + 1625 0088 10F00200 ands r0, r0, #2 + 1626 008c C6D0 beq .L106 + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1627 .loc 1 603 25 view .LVU479 + 1628 008e 2048 ldr r0, .L137+8 + 1629 0090 C4E7 b .L106 + 1630 .LVL146: + 1631 .L135: + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1632 .loc 1 616 5 is_stmt 1 view .LVU480 + 1633 .LBB324: + 1634 .LBI324: +2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1635 .loc 2 2730 26 view .LVU481 + 1636 .LBB325: +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1637 .loc 2 2732 3 view .LVU482 + ARM GAS /tmp/cc42qbQx.s page 133 + + +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1638 .loc 2 2732 22 is_stmt 0 view .LVU483 + 1639 0092 1D4B ldr r3, .L137 + 1640 0094 D3F89030 ldr r3, [r3, #144] + 1641 0098 0340 ands r3, r3, r0 +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1642 .loc 2 2732 10 view .LVU484 + 1643 009a 40EA1340 orr r0, r0, r3, lsr #16 + 1644 .LVL147: +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1645 .loc 2 2732 10 view .LVU485 + 1646 .LBE325: + 1647 .LBE324: + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1648 .loc 1 616 5 discriminator 1 view .LVU486 + 1649 009e 1E4B ldr r3, .L137+16 + 1650 00a0 9842 cmp r0, r3 + 1651 00a2 09D0 beq .L117 + 1652 00a4 1033 adds r3, r3, #16 + 1653 00a6 9842 cmp r0, r3 + 1654 00a8 09D0 beq .L118 + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1655 .loc 1 631 9 is_stmt 1 view .LVU487 + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1656 .loc 1 631 25 is_stmt 0 view .LVU488 + 1657 00aa FFF7FEFF bl RCC_GetSystemClockFreq + 1658 .LVL148: + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1659 .loc 1 631 25 discriminator 1 view .LVU489 + 1660 00ae FFF7FEFF bl RCC_GetHCLKClockFreq + 1661 .LVL149: + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1662 .loc 1 631 25 discriminator 2 view .LVU490 + 1663 00b2 FFF7FEFF bl RCC_GetPCLK1ClockFreq + 1664 .LVL150: + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1665 .loc 1 632 9 is_stmt 1 view .LVU491 + 1666 00b6 B1E7 b .L106 + 1667 .LVL151: + 1668 .L117: + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1669 .loc 1 619 9 view .LVU492 + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1670 .loc 1 619 25 is_stmt 0 view .LVU493 + 1671 00b8 FFF7FEFF bl RCC_GetSystemClockFreq + 1672 .LVL152: + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1673 .loc 1 620 9 is_stmt 1 view .LVU494 + 1674 00bc AEE7 b .L106 + 1675 .LVL153: + 1676 .L118: + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1677 .loc 1 623 9 view .LVU495 + 1678 .LBB326: + 1679 .LBI326: +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1680 .loc 2 2030 26 view .LVU496 + ARM GAS /tmp/cc42qbQx.s page 134 + + + 1681 .LBB327: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1682 .loc 2 2032 3 view .LVU497 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1683 .loc 2 2032 11 is_stmt 0 view .LVU498 + 1684 00be 124B ldr r3, .L137 + 1685 00c0 1868 ldr r0, [r3] + 1686 .LBE327: + 1687 .LBE326: + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1688 .loc 1 623 12 discriminator 1 view .LVU499 + 1689 00c2 10F00200 ands r0, r0, #2 + 1690 00c6 A9D0 beq .L106 + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1691 .loc 1 625 25 view .LVU500 + 1692 00c8 1148 ldr r0, .L137+8 + 1693 00ca A7E7 b .L106 + 1694 .LVL154: + 1695 .L136: + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1696 .loc 1 641 7 is_stmt 1 view .LVU501 + 1697 .LBB328: + 1698 .LBI328: +2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1699 .loc 2 2730 26 view .LVU502 + 1700 .LBB329: +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1701 .loc 2 2732 3 view .LVU503 +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1702 .loc 2 2732 22 is_stmt 0 view .LVU504 + 1703 00cc 0E4B ldr r3, .L137 + 1704 00ce D3F89030 ldr r3, [r3, #144] + 1705 00d2 0340 ands r3, r3, r0 +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1706 .loc 2 2732 10 view .LVU505 + 1707 00d4 40EA1340 orr r0, r0, r3, lsr #16 + 1708 .LVL155: +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1709 .loc 2 2732 10 view .LVU506 + 1710 .LBE329: + 1711 .LBE328: + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1712 .loc 1 641 7 discriminator 1 view .LVU507 + 1713 00d8 104B ldr r3, .L137+20 + 1714 00da 9842 cmp r0, r3 + 1715 00dc 09D0 beq .L120 + 1716 00de 4033 adds r3, r3, #64 + 1717 00e0 9842 cmp r0, r3 + 1718 00e2 09D0 beq .L121 + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1719 .loc 1 656 11 is_stmt 1 view .LVU508 + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1720 .loc 1 656 27 is_stmt 0 view .LVU509 + 1721 00e4 FFF7FEFF bl RCC_GetSystemClockFreq + 1722 .LVL156: + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1723 .loc 1 656 27 discriminator 1 view .LVU510 + ARM GAS /tmp/cc42qbQx.s page 135 + + + 1724 00e8 FFF7FEFF bl RCC_GetHCLKClockFreq + 1725 .LVL157: + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1726 .loc 1 656 27 discriminator 2 view .LVU511 + 1727 00ec FFF7FEFF bl RCC_GetPCLK1ClockFreq + 1728 .LVL158: + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1729 .loc 1 657 11 is_stmt 1 view .LVU512 + 1730 00f0 94E7 b .L106 + 1731 .LVL159: + 1732 .L120: + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1733 .loc 1 644 11 view .LVU513 + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1734 .loc 1 644 27 is_stmt 0 view .LVU514 + 1735 00f2 FFF7FEFF bl RCC_GetSystemClockFreq + 1736 .LVL160: + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1737 .loc 1 645 11 is_stmt 1 view .LVU515 + 1738 00f6 91E7 b .L106 + 1739 .LVL161: + 1740 .L121: + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1741 .loc 1 648 11 view .LVU516 + 1742 .LBB330: + 1743 .LBI330: +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1744 .loc 2 2030 26 view .LVU517 + 1745 .LBB331: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1746 .loc 2 2032 3 view .LVU518 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1747 .loc 2 2032 11 is_stmt 0 view .LVU519 + 1748 00f8 034B ldr r3, .L137 + 1749 00fa 1868 ldr r0, [r3] + 1750 .LBE331: + 1751 .LBE330: + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1752 .loc 1 648 14 discriminator 1 view .LVU520 + 1753 00fc 10F00200 ands r0, r0, #2 + 1754 0100 8CD0 beq .L106 + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1755 .loc 1 650 27 view .LVU521 + 1756 0102 0348 ldr r0, .L137+8 + 1757 .LVL162: + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1758 .loc 1 668 3 is_stmt 1 view .LVU522 + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1759 .loc 1 668 10 is_stmt 0 view .LVU523 + 1760 0104 8AE7 b .L106 + 1761 .L138: + 1762 0106 00BF .align 2 + 1763 .L137: + 1764 0108 00380240 .word 1073887232 + 1765 010c 01000300 .word 196609 + 1766 0110 0024F400 .word 16000000 + 1767 0114 04000C00 .word 786436 + ARM GAS /tmp/cc42qbQx.s page 136 + + + 1768 0118 10003000 .word 3145744 + 1769 011c 4000C000 .word 12582976 + 1770 .cfi_endproc + 1771 .LFE299: + 1773 .section .text.LL_RCC_GetLPTIMClockFreq,"ax",%progbits + 1774 .align 1 + 1775 .global LL_RCC_GetLPTIMClockFreq + 1776 .syntax unified + 1777 .thumb + 1778 .thumb_func + 1780 LL_RCC_GetLPTIMClockFreq: + 1781 .LVL163: + 1782 .LFB301: + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 1783 .loc 1 715 1 is_stmt 1 view -0 + 1784 .cfi_startproc + 1785 @ args = 0, pretend = 0, frame = 0 + 1786 @ frame_needed = 0, uses_anonymous_args = 0 + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1787 .loc 1 716 3 view .LVU525 + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1788 .loc 1 719 3 view .LVU526 + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1789 .loc 1 721 3 view .LVU527 + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1790 .loc 1 721 6 is_stmt 0 view .LVU528 + 1791 0000 B0F1407F cmp r0, #50331648 + 1792 0004 01D0 beq .L152 + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1793 .loc 1 716 12 view .LVU529 + 1794 0006 0020 movs r0, #0 + 1795 .LVL164: + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1796 .loc 1 755 1 view .LVU530 + 1797 0008 7047 bx lr + 1798 .LVL165: + 1799 .L152: + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 1800 .loc 1 715 1 view .LVU531 + 1801 000a 08B5 push {r3, lr} + 1802 .LCFI7: + 1803 .cfi_def_cfa_offset 8 + 1804 .cfi_offset 3, -8 + 1805 .cfi_offset 14, -4 + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1806 .loc 1 724 5 is_stmt 1 view .LVU532 + 1807 .LVL166: + 1808 .LBB332: + 1809 .LBI332: +2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1810 .loc 2 2746 26 view .LVU533 + 1811 .LBB333: +2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1812 .loc 2 2748 3 view .LVU534 +2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1813 .loc 2 2748 21 is_stmt 0 view .LVU535 + 1814 000c 154B ldr r3, .L153 + ARM GAS /tmp/cc42qbQx.s page 137 + + + 1815 000e D3F89030 ldr r3, [r3, #144] +2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1816 .loc 2 2748 10 view .LVU536 + 1817 0012 03F04073 and r3, r3, #50331648 + 1818 .LVL167: +2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1819 .loc 2 2748 10 view .LVU537 + 1820 .LBE333: + 1821 .LBE332: + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1822 .loc 1 724 5 discriminator 1 view .LVU538 + 1823 0016 B3F1007F cmp r3, #33554432 + 1824 001a 0DD0 beq .L141 + 1825 001c B3F1407F cmp r3, #50331648 + 1826 0020 11D0 beq .L142 + 1827 0022 B3F1807F cmp r3, #16777216 + 1828 0026 16D1 bne .L143 + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1829 .loc 1 727 9 is_stmt 1 view .LVU539 + 1830 .LBB334: + 1831 .LBI334: +2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1832 .loc 2 2192 26 view .LVU540 + 1833 .LBB335: +2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1834 .loc 2 2194 3 view .LVU541 +2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1835 .loc 2 2194 11 is_stmt 0 view .LVU542 + 1836 0028 0E4B ldr r3, .L153 + 1837 002a 586F ldr r0, [r3, #116] + 1838 .LVL168: +2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1839 .loc 2 2194 11 view .LVU543 + 1840 .LBE335: + 1841 .LBE334: + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1842 .loc 1 727 12 discriminator 1 view .LVU544 + 1843 002c 10F00200 ands r0, r0, #2 + 1844 0030 17D0 beq .L139 + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1845 .loc 1 729 27 view .LVU545 + 1846 0032 4FF4FA40 mov r0, #32000 + 1847 0036 14E0 b .L139 + 1848 .LVL169: + 1849 .L141: + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1850 .loc 1 734 9 is_stmt 1 view .LVU546 + 1851 .LBB336: + 1852 .LBI336: +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1853 .loc 2 2030 26 view .LVU547 + 1854 .LBB337: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1855 .loc 2 2032 3 view .LVU548 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1856 .loc 2 2032 11 is_stmt 0 view .LVU549 + 1857 0038 0A4B ldr r3, .L153 + ARM GAS /tmp/cc42qbQx.s page 138 + + + 1858 003a 1868 ldr r0, [r3] + 1859 .LVL170: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1860 .loc 2 2032 11 view .LVU550 + 1861 .LBE337: + 1862 .LBE336: + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1863 .loc 1 734 12 discriminator 1 view .LVU551 + 1864 003c 10F00200 ands r0, r0, #2 + 1865 0040 0FD0 beq .L139 + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1866 .loc 1 736 27 view .LVU552 + 1867 0042 0948 ldr r0, .L153+4 + 1868 0044 0DE0 b .L139 + 1869 .LVL171: + 1870 .L142: + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1871 .loc 1 741 9 is_stmt 1 view .LVU553 + 1872 .LBB338: + 1873 .LBI338: +2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1874 .loc 2 2154 26 view .LVU554 + 1875 .LBB339: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1876 .loc 2 2156 3 view .LVU555 +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1877 .loc 2 2156 11 is_stmt 0 view .LVU556 + 1878 0046 074B ldr r3, .L153 + 1879 0048 186F ldr r0, [r3, #112] + 1880 .LVL172: +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1881 .loc 2 2156 11 view .LVU557 + 1882 .LBE339: + 1883 .LBE338: + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1884 .loc 1 741 12 discriminator 1 view .LVU558 + 1885 004a 10F00200 ands r0, r0, #2 + 1886 004e 08D0 beq .L139 + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1887 .loc 1 743 27 view .LVU559 + 1888 0050 4FF40040 mov r0, #32768 + 1889 .LVL173: + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1890 .loc 1 754 3 is_stmt 1 view .LVU560 + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1891 .loc 1 754 10 is_stmt 0 view .LVU561 + 1892 0054 05E0 b .L139 + 1893 .LVL174: + 1894 .L143: + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1895 .loc 1 749 9 is_stmt 1 view .LVU562 + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1896 .loc 1 749 27 is_stmt 0 view .LVU563 + 1897 0056 FFF7FEFF bl RCC_GetSystemClockFreq + 1898 .LVL175: + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1899 .loc 1 749 27 discriminator 1 view .LVU564 + ARM GAS /tmp/cc42qbQx.s page 139 + + + 1900 005a FFF7FEFF bl RCC_GetHCLKClockFreq + 1901 .LVL176: + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1902 .loc 1 749 27 discriminator 2 view .LVU565 + 1903 005e FFF7FEFF bl RCC_GetPCLK1ClockFreq + 1904 .LVL177: + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1905 .loc 1 750 9 is_stmt 1 view .LVU566 + 1906 .L139: + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1907 .loc 1 755 1 is_stmt 0 view .LVU567 + 1908 0062 08BD pop {r3, pc} + 1909 .L154: + 1910 .align 2 + 1911 .L153: + 1912 0064 00380240 .word 1073887232 + 1913 0068 0024F400 .word 16000000 + 1914 .cfi_endproc + 1915 .LFE301: + 1917 .section .text.LL_RCC_GetDFSDMClockFreq,"ax",%progbits + 1918 .align 1 + 1919 .global LL_RCC_GetDFSDMClockFreq + 1920 .syntax unified + 1921 .thumb + 1922 .thumb_func + 1924 LL_RCC_GetDFSDMClockFreq: + 1925 .LVL178: + 1926 .LFB307: +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 1927 .loc 1 1077 1 is_stmt 1 view -0 + 1928 .cfi_startproc + 1929 @ args = 0, pretend = 0, frame = 0 + 1930 @ frame_needed = 0, uses_anonymous_args = 0 +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 1931 .loc 1 1077 1 is_stmt 0 view .LVU569 + 1932 0000 08B5 push {r3, lr} + 1933 .LCFI8: + 1934 .cfi_def_cfa_offset 8 + 1935 .cfi_offset 3, -8 + 1936 .cfi_offset 14, -4 +1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1937 .loc 1 1078 3 is_stmt 1 view .LVU570 + 1938 .LVL179: +1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1939 .loc 1 1081 3 view .LVU571 +1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1940 .loc 1 1084 3 view .LVU572 + 1941 .LBB340: + 1942 .LBI340: +2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1943 .loc 2 2891 26 view .LVU573 + 1944 .LBB341: +2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1945 .loc 2 2893 3 view .LVU574 +2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1946 .loc 2 2893 21 is_stmt 0 view .LVU575 + 1947 0002 084B ldr r3, .L160 + ARM GAS /tmp/cc42qbQx.s page 140 + + + 1948 0004 D3F88C30 ldr r3, [r3, #140] +2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1949 .loc 2 2893 10 view .LVU576 + 1950 0008 1840 ands r0, r0, r3 + 1951 .LVL180: +2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1952 .loc 2 2893 10 view .LVU577 + 1953 .LBE341: + 1954 .LBE340: +1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1955 .loc 1 1084 3 discriminator 1 view .LVU578 + 1956 000a B0F1007F cmp r0, #33554432 + 1957 000e 06D0 beq .L159 +1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1958 .loc 1 1092 7 is_stmt 1 view .LVU579 +1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1959 .loc 1 1092 25 is_stmt 0 view .LVU580 + 1960 0010 FFF7FEFF bl RCC_GetSystemClockFreq + 1961 .LVL181: +1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1962 .loc 1 1092 25 discriminator 1 view .LVU581 + 1963 0014 FFF7FEFF bl RCC_GetHCLKClockFreq + 1964 .LVL182: +1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1965 .loc 1 1092 25 discriminator 2 view .LVU582 + 1966 0018 FFF7FEFF bl RCC_GetPCLK2ClockFreq + 1967 .LVL183: +1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1968 .loc 1 1093 7 is_stmt 1 view .LVU583 +1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 1969 .loc 1 1096 3 view .LVU584 + 1970 .L155: +1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1971 .loc 1 1097 1 is_stmt 0 view .LVU585 + 1972 001c 08BD pop {r3, pc} + 1973 .LVL184: + 1974 .L159: +1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1975 .loc 1 1087 7 is_stmt 1 view .LVU586 +1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 1976 .loc 1 1087 25 is_stmt 0 view .LVU587 + 1977 001e FFF7FEFF bl RCC_GetSystemClockFreq + 1978 .LVL185: +1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 1979 .loc 1 1088 7 is_stmt 1 view .LVU588 + 1980 0022 FBE7 b .L155 + 1981 .L161: + 1982 .align 2 + 1983 .L160: + 1984 0024 00380240 .word 1073887232 + 1985 .cfi_endproc + 1986 .LFE307: + 1988 .section .text.RCC_PLL_GetFreqDomain_48M,"ax",%progbits + 1989 .align 1 + 1990 .global RCC_PLL_GetFreqDomain_48M + 1991 .syntax unified + 1992 .thumb + ARM GAS /tmp/cc42qbQx.s page 141 + + + 1993 .thumb_func + 1995 RCC_PLL_GetFreqDomain_48M: + 1996 .LFB316: +1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return PLL clock frequency used for 48 MHz domain +1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval PLL clock frequency (in Hz) +1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLL_GetFreqDomain_48M(void) +1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 1997 .loc 1 1326 1 view -0 + 1998 .cfi_startproc + 1999 @ args = 0, pretend = 0, frame = 0 + 2000 @ frame_needed = 0, uses_anonymous_args = 0 + 2001 @ link register save eliminated. +1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t pllinputfreq = 0U, pllsource = 0U; + 2002 .loc 1 1327 3 view .LVU590 + 2003 .LVL186: +1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN +1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 48M Domain clock = PLL_VCO / PLLQ +1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllsource = LL_RCC_PLL_GetMainSource(); + 2004 .loc 1 1332 3 view .LVU591 + 2005 .LBB342: + 2006 .LBI342: +3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2007 .loc 2 3461 26 view .LVU592 + 2008 .LBB343: +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2009 .loc 2 3463 3 view .LVU593 +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2010 .loc 2 3463 21 is_stmt 0 view .LVU594 + 2011 0000 0C4B ldr r3, .L165 + 2012 0002 5B68 ldr r3, [r3, #4] +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2013 .loc 2 3463 10 view .LVU595 + 2014 0004 03F48003 and r3, r3, #4194304 + 2015 .LVL187: +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2016 .loc 2 3463 10 view .LVU596 + 2017 .LBE343: + 2018 .LBE342: +1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (pllsource) + 2019 .loc 1 1334 3 is_stmt 1 view .LVU597 + 2020 0008 8BB9 cbnz r3, .L164 +1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ +1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; + 2021 .loc 1 1337 20 is_stmt 0 view .LVU598 + 2022 000a 0B4B ldr r3, .L165+4 + 2023 .LVL188: + 2024 .L163: +1338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + ARM GAS /tmp/cc42qbQx.s page 142 + + +1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSE_VALUE; +1342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: +1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; +1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + 2025 .loc 1 1348 3 is_stmt 1 view .LVU599 + 2026 .LBB344: + 2027 .LBI344: +3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2028 .loc 2 3601 26 view .LVU600 + 2029 .LBB345: +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2030 .loc 2 3603 3 view .LVU601 +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2031 .loc 2 3603 21 is_stmt 0 view .LVU602 + 2032 000c 094A ldr r2, .L165 + 2033 000e 5168 ldr r1, [r2, #4] +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2034 .loc 2 3603 10 view .LVU603 + 2035 0010 01F03F01 and r1, r1, #63 + 2036 .LBE345: + 2037 .LBE344: + 2038 .loc 1 1348 10 discriminator 1 view .LVU604 + 2039 0014 B3FBF1F3 udiv r3, r3, r1 + 2040 .LVL189: + 2041 .LBB346: + 2042 .LBI346: +3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2043 .loc 2 3471 26 is_stmt 1 view .LVU605 + 2044 .LBB347: +3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2045 .loc 2 3473 3 view .LVU606 +3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2046 .loc 2 3473 21 is_stmt 0 view .LVU607 + 2047 0018 5168 ldr r1, [r2, #4] +3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2048 .loc 2 3473 10 view .LVU608 + 2049 001a C1F38811 ubfx r1, r1, #6, #9 + 2050 .LBE347: + 2051 .LBE346: + 2052 .loc 1 1348 10 discriminator 2 view .LVU609 + 2053 001e 01FB03F3 mul r3, r1, r3 + 2054 .LBB348: + 2055 .LBI348: +3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2056 .loc 2 3510 26 is_stmt 1 view .LVU610 + 2057 .LBB349: +3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2058 .loc 2 3512 3 view .LVU611 +3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2059 .loc 2 3512 21 is_stmt 0 view .LVU612 + 2060 0022 5068 ldr r0, [r2, #4] + 2061 .LBE349: + 2062 .LBE348: + ARM GAS /tmp/cc42qbQx.s page 143 + + + 2063 .loc 1 1348 10 discriminator 3 view .LVU613 + 2064 0024 C0F30360 ubfx r0, r0, #24, #4 +1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); +1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2065 .loc 1 1350 1 view .LVU614 + 2066 0028 B3FBF0F0 udiv r0, r3, r0 + 2067 002c 7047 bx lr + 2068 .LVL190: + 2069 .L164: +1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 2070 .loc 1 1341 20 view .LVU615 + 2071 002e 034B ldr r3, .L165+8 + 2072 .LVL191: +1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 2073 .loc 1 1341 20 view .LVU616 + 2074 0030 ECE7 b .L163 + 2075 .L166: + 2076 0032 00BF .align 2 + 2077 .L165: + 2078 0034 00380240 .word 1073887232 + 2079 0038 0024F400 .word 16000000 + 2080 003c 40787D01 .word 25000000 + 2081 .cfi_endproc + 2082 .LFE316: + 2084 .section .text.RCC_PLLSAI_GetFreqDomain_SAI,"ax",%progbits + 2085 .align 1 + 2086 .global RCC_PLLSAI_GetFreqDomain_SAI + 2087 .syntax unified + 2088 .thumb + 2089 .thumb_func + 2091 RCC_PLLSAI_GetFreqDomain_SAI: + 2092 .LFB317: +1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(DSI) +1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return PLL clock frequency used for DSI clock +1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval PLL clock frequency (in Hz) +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLL_GetFreqDomain_DSI(void) +1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t pllinputfreq = 0U, pllsource = 0U; +1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN +1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** DSICLK = PLL_VCO / PLLR +1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllsource = LL_RCC_PLL_GetMainSource(); +1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (pllsource) +1367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSE_VALUE; +1370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ +1373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: +1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; +1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + ARM GAS /tmp/cc42qbQx.s page 144 + + +1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), +1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); +1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* DSI */ +1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return PLLSAI clock frequency used for SAI1 and SAI2 domains +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval PLLSAI clock frequency (in Hz) +1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void) +1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2093 .loc 1 1387 1 is_stmt 1 view -0 + 2094 .cfi_startproc + 2095 @ args = 0, pretend = 0, frame = 0 + 2096 @ frame_needed = 0, uses_anonymous_args = 0 + 2097 @ link register save eliminated. +1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t pllinputfreq = 0U, pllsource = 0U; + 2098 .loc 1 1388 3 view .LVU618 + 2099 .LVL192: +1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN +1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** SAI1 and SAI2 domains clock = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ +1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllsource = LL_RCC_PLL_GetMainSource(); + 2100 .loc 1 1393 3 view .LVU619 + 2101 .LBB350: + 2102 .LBI350: +3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2103 .loc 2 3461 26 view .LVU620 + 2104 .LBB351: +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2105 .loc 2 3463 3 view .LVU621 +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2106 .loc 2 3463 21 is_stmt 0 view .LVU622 + 2107 0000 104B ldr r3, .L170 + 2108 0002 5B68 ldr r3, [r3, #4] +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2109 .loc 2 3463 10 view .LVU623 + 2110 0004 03F48003 and r3, r3, #4194304 + 2111 .LVL193: +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2112 .loc 2 3463 10 view .LVU624 + 2113 .LBE351: + 2114 .LBE350: +1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (pllsource) + 2115 .loc 1 1395 3 is_stmt 1 view .LVU625 + 2116 0008 CBB9 cbnz r3, .L169 +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */ +1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; + 2117 .loc 1 1398 20 is_stmt 0 view .LVU626 + 2118 000a 0F48 ldr r0, .L170+4 + 2119 .L168: + 2120 .LVL194: +1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + ARM GAS /tmp/cc42qbQx.s page 145 + + +1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */ +1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSE_VALUE; +1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: +1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; +1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + 2121 .loc 1 1409 3 is_stmt 1 view .LVU627 + 2122 .LBB352: + 2123 .LBI352: +3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2124 .loc 2 3601 26 view .LVU628 + 2125 .LBB353: +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2126 .loc 2 3603 3 view .LVU629 +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2127 .loc 2 3603 21 is_stmt 0 view .LVU630 + 2128 000c 0D4A ldr r2, .L170 + 2129 000e 5368 ldr r3, [r2, #4] + 2130 .LVL195: +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2131 .loc 2 3603 10 view .LVU631 + 2132 0010 03F03F03 and r3, r3, #63 + 2133 .LBE353: + 2134 .LBE352: + 2135 .loc 1 1409 10 discriminator 1 view .LVU632 + 2136 0014 B0FBF3F0 udiv r0, r0, r3 + 2137 .LVL196: + 2138 .LBB354: + 2139 .LBI354: +4182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure PLLSAI used for SAI1 and SAI2 domain clock +4186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLL Source and PLLM Divider can be written only when PLL, +4187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2S and PLLSAI are disabled +4188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLLN/PLLQ can be written only when PLLSAI is disabled +4189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note This can be selected for SAI1 and SAI2 +4190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n +4191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n +4192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n +4193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n +4194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR1 PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI +4195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +4196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +4197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +4198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLM This parameter can be one of the following values: +4199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +4200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +4201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +4202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +4203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +4204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +4205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 + ARM GAS /tmp/cc42qbQx.s page 146 + + +4206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +4207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +4208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +4209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +4210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +4211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +4212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +4213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +4214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +4215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +4216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +4217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +4218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +4219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +4220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +4221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +4222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +4223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +4224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +4225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +4226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +4227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +4228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +4229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +4230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +4231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +4232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +4233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +4234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +4235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +4236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +4237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +4238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +4239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +4240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +4241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +4242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +4243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +4244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +4245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +4246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +4247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +4248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +4249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +4250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +4251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +4252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +4253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +4254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +4255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +4256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +4257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +4258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +4259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +4260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +4261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLN Between 50 and 432 +4262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLQ This parameter can be one of the following values: + ARM GAS /tmp/cc42qbQx.s page 147 + + +4263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_2 +4264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_3 +4265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_4 +4266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_5 +4267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_6 +4268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_7 +4269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_8 +4270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_9 +4271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_10 +4272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_11 +4273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_12 +4274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_13 +4275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_14 +4276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_15 +4277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLDIVQ This parameter can be one of the following values: +4278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 +4279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 +4280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 +4281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 +4282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 +4283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 +4284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 +4285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 +4286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 +4287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 +4288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 +4289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 +4290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 +4291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 +4292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 +4293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 +4294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 +4295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 +4296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 +4297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 +4298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 +4299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 +4300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 +4301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 +4302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 +4303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 +4304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 +4305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 +4306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 +4307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 +4308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 +4309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 +4310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +4311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, +4313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); +4315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICF +4316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, PLLDIVQ); +4317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + ARM GAS /tmp/cc42qbQx.s page 148 + + +4320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure PLLSAI used for 48Mhz domain clock +4321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLL Source and PLLM Divider can be written only when PLL, +4322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2S and PLLSAI are disabled +4323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLLN/PLLP can be written only when PLLSAI is disabled +4324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note This can be selected for USB, RNG, SDMMC1 +4325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n +4326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n +4327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n +4328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M +4329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +4330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +4331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +4332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLM This parameter can be one of the following values: +4333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +4334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +4335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +4336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +4337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +4338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +4339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +4340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +4341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +4342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +4343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +4344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +4345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +4346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +4347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +4348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +4349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +4350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +4351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +4352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +4353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +4354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +4355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +4356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +4357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +4358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +4359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +4360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +4361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +4362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +4363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +4364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +4365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +4366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +4367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +4368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +4369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +4370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +4371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +4372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +4373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +4374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +4375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +4376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 + ARM GAS /tmp/cc42qbQx.s page 149 + + +4377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +4378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +4379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +4380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +4381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +4382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +4383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +4384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +4385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +4386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +4387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +4388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +4389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +4390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +4391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +4392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +4393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +4394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +4395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLN Between 50 and 432 +4396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLP This parameter can be one of the following values: +4397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIP_DIV_2 +4398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIP_DIV_4 +4399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIP_DIV_6 +4400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIP_DIV_8 +4401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +4402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, +4404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); +4406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICF +4407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(LTDC) +4410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure PLLSAI used for LTDC domain clock +4412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLL Source and PLLM Divider can be written only when PLL, +4413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2S and PLLSAI are disabled +4414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLLN/PLLR can be written only when PLLSAI is disabled +4415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note This can be selected for LTDC +4416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n +4417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n +4418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n +4419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n +4420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR1 PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC +4421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +4422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +4423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +4424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLM This parameter can be one of the following values: +4425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +4426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +4427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +4428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +4429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +4430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +4431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +4432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +4433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 + ARM GAS /tmp/cc42qbQx.s page 150 + + +4434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +4435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +4436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +4437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +4438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +4439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +4440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +4441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +4442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +4443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +4444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +4445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +4446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +4447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +4448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +4449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +4450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +4451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +4452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +4453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +4454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +4455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +4456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +4457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +4458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +4459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +4460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +4461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +4462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +4463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +4464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +4465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +4466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +4467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +4468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +4469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +4470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +4471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +4472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +4473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +4474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +4475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +4476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +4477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +4478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +4479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +4480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +4481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +4482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +4483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +4484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +4485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +4486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +4487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLN Between 50 and 432 +4488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLR This parameter can be one of the following values: +4489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_2 +4490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_3 + ARM GAS /tmp/cc42qbQx.s page 151 + + +4491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_4 +4492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_5 +4493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_6 +4494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_7 +4495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLDIVR This parameter can be one of the following values: +4496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 +4497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 +4498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 +4499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 +4500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +4501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, +4503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); +4505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICF +4506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, PLLDIVR); +4507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* LTDC */ +4509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get SAIPLL multiplication factor for VCO +4512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN +4513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Between 50 and 432 +4514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void) + 2140 .loc 2 4515 26 is_stmt 1 view .LVU633 + 2141 .LBB355: +4516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos + 2142 .loc 2 4517 3 view .LVU634 + 2143 .loc 2 4517 21 is_stmt 0 view .LVU635 + 2144 0018 D2F88830 ldr r3, [r2, #136] + 2145 .loc 2 4517 10 view .LVU636 + 2146 001c C3F38813 ubfx r3, r3, #6, #9 + 2147 .LBE355: + 2148 .LBE354: + 2149 .loc 1 1409 10 discriminator 2 view .LVU637 + 2150 0020 03FB00F0 mul r0, r3, r0 + 2151 .LBB356: + 2152 .LBI356: +4518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get SAIPLL division factor for PLLSAIQ +4522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ +4523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +4524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_2 +4525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_3 +4526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_4 +4527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_5 +4528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_6 +4529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_7 +4530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_8 +4531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_9 +4532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_10 +4533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_11 +4534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_12 + ARM GAS /tmp/cc42qbQx.s page 152 + + +4535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_13 +4536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_14 +4537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_15 +4538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void) + 2153 .loc 2 4539 26 is_stmt 1 view .LVU638 + 2154 .LBB357: +4540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ)); + 2155 .loc 2 4541 3 view .LVU639 + 2156 .loc 2 4541 21 is_stmt 0 view .LVU640 + 2157 0024 D2F88830 ldr r3, [r2, #136] + 2158 .LBE357: + 2159 .LBE356: + 2160 .loc 1 1409 10 discriminator 3 view .LVU641 + 2161 0028 C3F30363 ubfx r3, r3, #24, #4 + 2162 .LBB358: + 2163 .LBI358: +4542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLSAICFGR_PLLSAIR) +4545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get SAIPLL division factor for PLLSAIR +4547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note used for PLLSAICLK (SAI clock) +4548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR +4549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +4550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_2 +4551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_3 +4552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_4 +4553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_5 +4554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_6 +4555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_7 +4556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void) +4558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR)); +4560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLSAICFGR_PLLSAIR */ +4562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get SAIPLL division factor for PLLSAIP +4565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note used for PLL48MCLK (48M domain clock) +4566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP +4567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +4568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIP_DIV_2 +4569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIP_DIV_4 +4570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIP_DIV_6 +4571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIP_DIV_8 +4572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void) +4574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP)); +4576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get SAIPLL division factor for PLLSAIDIVQ +4580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock) + ARM GAS /tmp/cc42qbQx.s page 153 + + +4581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ +4582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +4583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 +4584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 +4585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 +4586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 +4587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 +4588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 +4589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 +4590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 +4591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 +4592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 +4593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 +4594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 +4595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 +4596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 +4597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 +4598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 +4599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 +4600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 +4601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 +4602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 +4603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 +4604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 +4605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 +4606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 +4607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 +4608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 +4609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 +4610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 +4611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 +4612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 +4613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 +4614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 +4615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void) + 2164 .loc 2 4616 26 is_stmt 1 view .LVU642 + 2165 .LBB359: +4617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ)); + 2166 .loc 2 4618 3 view .LVU643 + 2167 .loc 2 4618 21 is_stmt 0 view .LVU644 + 2168 002c D2F88C20 ldr r2, [r2, #140] + 2169 .LBE359: + 2170 .LBE358: + 2171 .loc 1 1409 10 discriminator 4 view .LVU645 + 2172 0030 C2F30422 ubfx r2, r2, #8, #5 + 2173 0034 02FB0333 mla r3, r2, r3, r3 +1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_G +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2174 .loc 1 1411 1 view .LVU646 + 2175 0038 B0FBF3F0 udiv r0, r0, r3 + 2176 003c 7047 bx lr + 2177 .LVL197: + 2178 .L169: +1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 2179 .loc 1 1402 20 view .LVU647 + ARM GAS /tmp/cc42qbQx.s page 154 + + + 2180 003e 0348 ldr r0, .L170+8 + 2181 0040 E4E7 b .L168 + 2182 .L171: + 2183 0042 00BF .align 2 + 2184 .L170: + 2185 0044 00380240 .word 1073887232 + 2186 0048 0024F400 .word 16000000 + 2187 004c 40787D01 .word 25000000 + 2188 .cfi_endproc + 2189 .LFE317: + 2191 .section .text.RCC_PLLSAI_GetFreqDomain_48M,"ax",%progbits + 2192 .align 1 + 2193 .global RCC_PLLSAI_GetFreqDomain_48M + 2194 .syntax unified + 2195 .thumb + 2196 .thumb_func + 2198 RCC_PLLSAI_GetFreqDomain_48M: + 2199 .LFB318: +1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return PLLSAI clock frequency used for 48Mhz domain +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval PLLSAI clock frequency (in Hz) +1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLSAI_GetFreqDomain_48M(void) +1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2200 .loc 1 1418 1 is_stmt 1 view -0 + 2201 .cfi_startproc + 2202 @ args = 0, pretend = 0, frame = 0 + 2203 @ frame_needed = 0, uses_anonymous_args = 0 + 2204 @ link register save eliminated. +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t pllinputfreq = 0U, pllsource = 0U; + 2205 .loc 1 1419 3 view .LVU649 + 2206 .LVL198: +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN +1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** 48M Domain clock = PLLSAI_VCO / PLLSAIP +1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllsource = LL_RCC_PLL_GetMainSource(); + 2207 .loc 1 1424 3 view .LVU650 + 2208 .LBB360: + 2209 .LBI360: +3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2210 .loc 2 3461 26 view .LVU651 + 2211 .LBB361: +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2212 .loc 2 3463 3 view .LVU652 +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2213 .loc 2 3463 21 is_stmt 0 view .LVU653 + 2214 0000 0E4B ldr r3, .L175 + 2215 0002 5B68 ldr r3, [r3, #4] +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2216 .loc 2 3463 10 view .LVU654 + 2217 0004 03F48003 and r3, r3, #4194304 + 2218 .LVL199: +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2219 .loc 2 3463 10 view .LVU655 + 2220 .LBE361: + ARM GAS /tmp/cc42qbQx.s page 155 + + + 2221 .LBE360: +1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (pllsource) + 2222 .loc 1 1426 3 is_stmt 1 view .LVU656 + 2223 0008 ABB9 cbnz r3, .L174 +1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */ +1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; + 2224 .loc 1 1429 20 is_stmt 0 view .LVU657 + 2225 000a 0D48 ldr r0, .L175+4 + 2226 .L173: + 2227 .LVL200: +1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */ +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSE_VALUE; +1434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: +1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; +1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + 2228 .loc 1 1440 3 is_stmt 1 view .LVU658 + 2229 .LBB362: + 2230 .LBI362: +3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2231 .loc 2 3601 26 view .LVU659 + 2232 .LBB363: +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2233 .loc 2 3603 3 view .LVU660 +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2234 .loc 2 3603 21 is_stmt 0 view .LVU661 + 2235 000c 0B4B ldr r3, .L175 + 2236 .LVL201: +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2237 .loc 2 3603 21 view .LVU662 + 2238 000e 5A68 ldr r2, [r3, #4] +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2239 .loc 2 3603 10 view .LVU663 + 2240 0010 02F03F02 and r2, r2, #63 + 2241 .LBE363: + 2242 .LBE362: + 2243 .loc 1 1440 10 discriminator 1 view .LVU664 + 2244 0014 B0FBF2F0 udiv r0, r0, r2 + 2245 .LVL202: + 2246 .LBB364: + 2247 .LBI364: +4515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2248 .loc 2 4515 26 is_stmt 1 view .LVU665 + 2249 .LBB365: +4517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2250 .loc 2 4517 3 view .LVU666 +4517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2251 .loc 2 4517 21 is_stmt 0 view .LVU667 + 2252 0018 D3F88820 ldr r2, [r3, #136] +4517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + ARM GAS /tmp/cc42qbQx.s page 156 + + + 2253 .loc 2 4517 10 view .LVU668 + 2254 001c C2F38812 ubfx r2, r2, #6, #9 + 2255 .LBE365: + 2256 .LBE364: + 2257 .loc 1 1440 10 discriminator 2 view .LVU669 + 2258 0020 02FB00F0 mul r0, r2, r0 + 2259 .LBB366: + 2260 .LBI366: +4573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2261 .loc 2 4573 26 is_stmt 1 view .LVU670 + 2262 .LBB367: +4575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2263 .loc 2 4575 3 view .LVU671 +4575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2264 .loc 2 4575 21 is_stmt 0 view .LVU672 + 2265 0024 D3F88830 ldr r3, [r3, #136] + 2266 .LBE367: + 2267 .LBE366: + 2268 .loc 1 1440 10 discriminator 3 view .LVU673 + 2269 0028 C3F30143 ubfx r3, r3, #16, #2 + 2270 002c 0133 adds r3, r3, #1 + 2271 002e 5B00 lsls r3, r3, #1 +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP()); +1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2272 .loc 1 1442 1 view .LVU674 + 2273 0030 B0FBF3F0 udiv r0, r0, r3 + 2274 0034 7047 bx lr + 2275 .LVL203: + 2276 .L174: +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 2277 .loc 1 1433 20 view .LVU675 + 2278 0036 0348 ldr r0, .L175+8 + 2279 0038 E8E7 b .L173 + 2280 .L176: + 2281 003a 00BF .align 2 + 2282 .L175: + 2283 003c 00380240 .word 1073887232 + 2284 0040 0024F400 .word 16000000 + 2285 0044 40787D01 .word 25000000 + 2286 .cfi_endproc + 2287 .LFE318: + 2289 .section .text.LL_RCC_GetSDMMCClockFreq,"ax",%progbits + 2290 .align 1 + 2291 .global LL_RCC_GetSDMMCClockFreq + 2292 .syntax unified + 2293 .thumb + 2294 .thumb_func + 2296 LL_RCC_GetSDMMCClockFreq: + 2297 .LVL204: + 2298 .LFB303: + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 2299 .loc 1 886 1 is_stmt 1 view -0 + 2300 .cfi_startproc + 2301 @ args = 0, pretend = 0, frame = 0 + 2302 @ frame_needed = 0, uses_anonymous_args = 0 + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 2303 .loc 1 886 1 is_stmt 0 view .LVU677 + ARM GAS /tmp/cc42qbQx.s page 157 + + + 2304 0000 08B5 push {r3, lr} + 2305 .LCFI9: + 2306 .cfi_def_cfa_offset 8 + 2307 .cfi_offset 3, -8 + 2308 .cfi_offset 14, -4 + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 2309 .loc 1 887 3 is_stmt 1 view .LVU678 + 2310 .LVL205: + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 2311 .loc 1 890 3 view .LVU679 + 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2312 .loc 1 892 3 view .LVU680 + 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2313 .loc 1 892 6 is_stmt 0 view .LVU681 + 2314 0002 B0F1805F cmp r0, #268435456 + 2315 0006 16D0 beq .L185 + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2316 .loc 1 927 6 is_stmt 1 view .LVU682 + 2317 .LVL206: + 2318 .LBB368: + 2319 .LBI368: +2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2320 .loc 2 2790 26 view .LVU683 + 2321 .LBB369: +2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2322 .loc 2 2792 3 view .LVU684 +2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2323 .loc 2 2792 21 is_stmt 0 view .LVU685 + 2324 0008 214B ldr r3, .L186 + 2325 000a D3F89030 ldr r3, [r3, #144] + 2326 000e 0340 ands r3, r3, r0 +2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2327 .loc 2 2792 10 view .LVU686 + 2328 0010 40EA1340 orr r0, r0, r3, lsr #16 + 2329 .LVL207: +2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2330 .loc 2 2792 10 view .LVU687 + 2331 .LBE369: + 2332 .LBE368: + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2333 .loc 1 927 6 discriminator 1 view .LVU688 + 2334 0014 B0F1005F cmp r0, #536870912 + 2335 0018 37D1 bne .L182 + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2336 .loc 1 930 10 is_stmt 1 view .LVU689 + 2337 .LVL208: + 2338 .LBB370: + 2339 .LBI370: +2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2340 .loc 2 2804 26 view .LVU690 + 2341 .LBB371: +2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2342 .loc 2 2806 3 view .LVU691 +2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2343 .loc 2 2806 21 is_stmt 0 view .LVU692 + 2344 001a 1D4B ldr r3, .L186 + 2345 001c D3F89030 ldr r3, [r3, #144] + ARM GAS /tmp/cc42qbQx.s page 158 + + + 2346 .LVL209: +2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2347 .loc 2 2806 21 view .LVU693 + 2348 .LBE371: + 2349 .LBE370: + 2350 0020 13F0006F tst r3, #134217728 + 2351 0024 29D1 bne .L183 + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2352 .loc 1 933 14 is_stmt 1 view .LVU694 + 2353 .LBB372: + 2354 .LBI372: +3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2355 .loc 2 3153 26 view .LVU695 + 2356 .LBB373: +3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2357 .loc 2 3155 3 view .LVU696 +3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2358 .loc 2 3155 11 is_stmt 0 view .LVU697 + 2359 0026 1A4B ldr r3, .L186 + 2360 0028 1868 ldr r0, [r3] + 2361 .LBE373: + 2362 .LBE372: + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2363 .loc 1 933 17 discriminator 1 view .LVU698 + 2364 002a 10F00070 ands r0, r0, #33554432 + 2365 002e 2ED0 beq .L177 + 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2366 .loc 1 935 16 is_stmt 1 view .LVU699 + 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2367 .loc 1 935 34 is_stmt 0 view .LVU700 + 2368 0030 FFF7FEFF bl RCC_PLL_GetFreqDomain_48M + 2369 .LVL210: + 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2370 .loc 1 935 34 view .LVU701 + 2371 0034 2BE0 b .L177 + 2372 .LVL211: + 2373 .L185: + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2374 .loc 1 895 5 is_stmt 1 view .LVU702 + 2375 .LBB374: + 2376 .LBI374: +2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2377 .loc 2 2790 26 view .LVU703 + 2378 .LBB375: +2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2379 .loc 2 2792 3 view .LVU704 +2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2380 .loc 2 2792 21 is_stmt 0 view .LVU705 + 2381 0036 164B ldr r3, .L186 + 2382 0038 D3F89030 ldr r3, [r3, #144] + 2383 003c 0340 ands r3, r3, r0 +2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2384 .loc 2 2792 10 view .LVU706 + 2385 003e 40EA1340 orr r0, r0, r3, lsr #16 + 2386 .LVL212: +2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2387 .loc 2 2792 10 view .LVU707 + ARM GAS /tmp/cc42qbQx.s page 159 + + + 2388 .LBE375: + 2389 .LBE374: + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2390 .loc 1 895 5 discriminator 1 view .LVU708 + 2391 0042 B0F1805F cmp r0, #268435456 + 2392 0046 15D1 bne .L179 + 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2393 .loc 1 898 9 is_stmt 1 view .LVU709 + 2394 .LVL213: + 2395 .LBB376: + 2396 .LBI376: +2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2397 .loc 2 2804 26 view .LVU710 + 2398 .LBB377: +2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2399 .loc 2 2806 3 view .LVU711 +2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2400 .loc 2 2806 21 is_stmt 0 view .LVU712 + 2401 0048 114B ldr r3, .L186 + 2402 004a D3F89030 ldr r3, [r3, #144] + 2403 .LVL214: +2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2404 .loc 2 2806 21 view .LVU713 + 2405 .LBE377: + 2406 .LBE376: + 2407 004e 13F0006F tst r3, #134217728 + 2408 0052 07D1 bne .L180 + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2409 .loc 1 901 13 is_stmt 1 view .LVU714 + 2410 .LBB378: + 2411 .LBI378: +3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2412 .loc 2 3153 26 view .LVU715 + 2413 .LBB379: +3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2414 .loc 2 3155 3 view .LVU716 +3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2415 .loc 2 3155 11 is_stmt 0 view .LVU717 + 2416 0054 0E4B ldr r3, .L186 + 2417 0056 1868 ldr r0, [r3] + 2418 .LBE379: + 2419 .LBE378: + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2420 .loc 1 901 16 discriminator 1 view .LVU718 + 2421 0058 10F00070 ands r0, r0, #33554432 + 2422 005c 17D0 beq .L177 + 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2423 .loc 1 903 15 is_stmt 1 view .LVU719 + 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2424 .loc 1 903 33 is_stmt 0 view .LVU720 + 2425 005e FFF7FEFF bl RCC_PLL_GetFreqDomain_48M + 2426 .LVL215: + 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2427 .loc 1 903 33 view .LVU721 + 2428 0062 14E0 b .L177 + 2429 .LVL216: + 2430 .L180: + ARM GAS /tmp/cc42qbQx.s page 160 + + + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2431 .loc 1 909 13 is_stmt 1 view .LVU722 + 2432 .LBB380: + 2433 .LBI380: +4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2434 .loc 2 4179 26 view .LVU723 + 2435 .LBB381: +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2436 .loc 2 4181 3 view .LVU724 +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2437 .loc 2 4181 11 is_stmt 0 view .LVU725 + 2438 0064 0A4B ldr r3, .L186 + 2439 0066 1868 ldr r0, [r3] + 2440 .LBE381: + 2441 .LBE380: + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2442 .loc 1 909 16 discriminator 1 view .LVU726 + 2443 0068 10F00050 ands r0, r0, #536870912 + 2444 006c 0FD0 beq .L177 + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2445 .loc 1 911 15 is_stmt 1 view .LVU727 + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2446 .loc 1 911 33 is_stmt 0 view .LVU728 + 2447 006e FFF7FEFF bl RCC_PLLSAI_GetFreqDomain_48M + 2448 .LVL217: + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2449 .loc 1 911 33 view .LVU729 + 2450 0072 0CE0 b .L177 + 2451 .LVL218: + 2452 .L179: + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 2453 .loc 1 919 7 is_stmt 1 view .LVU730 + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 2454 .loc 1 919 25 is_stmt 0 view .LVU731 + 2455 0074 FFF7FEFF bl RCC_GetSystemClockFreq + 2456 .LVL219: + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2457 .loc 1 920 7 is_stmt 1 view .LVU732 + 2458 0078 09E0 b .L177 + 2459 .LVL220: + 2460 .L183: + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2461 .loc 1 941 14 view .LVU733 + 2462 .LBB382: + 2463 .LBI382: +4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2464 .loc 2 4179 26 view .LVU734 + 2465 .LBB383: +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2466 .loc 2 4181 3 view .LVU735 +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2467 .loc 2 4181 11 is_stmt 0 view .LVU736 + 2468 007a 054B ldr r3, .L186 + 2469 007c 1868 ldr r0, [r3] + 2470 .LBE383: + 2471 .LBE382: + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + ARM GAS /tmp/cc42qbQx.s page 161 + + + 2472 .loc 1 941 17 discriminator 1 view .LVU737 + 2473 007e 10F00050 ands r0, r0, #536870912 + 2474 0082 04D0 beq .L177 + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2475 .loc 1 943 16 is_stmt 1 view .LVU738 + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2476 .loc 1 943 34 is_stmt 0 view .LVU739 + 2477 0084 FFF7FEFF bl RCC_PLLSAI_GetFreqDomain_48M + 2478 .LVL221: + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2479 .loc 1 943 34 view .LVU740 + 2480 0088 01E0 b .L177 + 2481 .LVL222: + 2482 .L182: + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 2483 .loc 1 951 8 is_stmt 1 view .LVU741 + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 2484 .loc 1 951 26 is_stmt 0 view .LVU742 + 2485 008a FFF7FEFF bl RCC_GetSystemClockFreq + 2486 .LVL223: + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2487 .loc 1 952 8 is_stmt 1 view .LVU743 + 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2488 .loc 1 957 3 view .LVU744 + 2489 .L177: + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 2490 .loc 1 958 1 is_stmt 0 view .LVU745 + 2491 008e 08BD pop {r3, pc} + 2492 .L187: + 2493 .align 2 + 2494 .L186: + 2495 0090 00380240 .word 1073887232 + 2496 .cfi_endproc + 2497 .LFE303: + 2499 .section .text.LL_RCC_GetRNGClockFreq,"ax",%progbits + 2500 .align 1 + 2501 .global LL_RCC_GetRNGClockFreq + 2502 .syntax unified + 2503 .thumb + 2504 .thumb_func + 2506 LL_RCC_GetRNGClockFreq: + 2507 .LVL224: + 2508 .LFB304: + 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 2509 .loc 1 968 1 is_stmt 1 view -0 + 2510 .cfi_startproc + 2511 @ args = 0, pretend = 0, frame = 0 + 2512 @ frame_needed = 0, uses_anonymous_args = 0 + 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 2513 .loc 1 968 1 is_stmt 0 view .LVU747 + 2514 0000 08B5 push {r3, lr} + 2515 .LCFI10: + 2516 .cfi_def_cfa_offset 8 + 2517 .cfi_offset 3, -8 + 2518 .cfi_offset 14, -4 + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 2519 .loc 1 969 3 is_stmt 1 view .LVU748 + ARM GAS /tmp/cc42qbQx.s page 162 + + + 2520 .LVL225: + 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 2521 .loc 1 972 3 view .LVU749 + 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2522 .loc 1 975 3 view .LVU750 + 2523 .LBB384: + 2524 .LBI384: +2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2525 .loc 2 2818 26 view .LVU751 + 2526 .LBB385: +2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2527 .loc 2 2820 3 view .LVU752 +2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2528 .loc 2 2820 21 is_stmt 0 view .LVU753 + 2529 0002 0B4B ldr r3, .L193 + 2530 0004 D3F89030 ldr r3, [r3, #144] + 2531 .LVL226: +2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2532 .loc 2 2820 21 view .LVU754 + 2533 .LBE385: + 2534 .LBE384: + 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2535 .loc 1 975 3 discriminator 1 view .LVU755 + 2536 0008 1842 tst r0, r3 + 2537 000a 08D1 bne .L189 + 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2538 .loc 1 978 7 is_stmt 1 view .LVU756 + 2539 .LBB386: + 2540 .LBI386: +3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2541 .loc 2 3153 26 view .LVU757 + 2542 .LBB387: +3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2543 .loc 2 3155 3 view .LVU758 +3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2544 .loc 2 3155 11 is_stmt 0 view .LVU759 + 2545 000c 084B ldr r3, .L193 + 2546 000e 1868 ldr r0, [r3] + 2547 .LVL227: +3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2548 .loc 2 3155 11 view .LVU760 + 2549 .LBE387: + 2550 .LBE386: + 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2551 .loc 1 978 10 discriminator 1 view .LVU761 + 2552 0010 10F00070 ands r0, r0, #33554432 + 2553 0014 00D1 bne .L192 + 2554 .LVL228: + 2555 .L188: + 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 2556 .loc 1 994 1 view .LVU762 + 2557 0016 08BD pop {r3, pc} + 2558 .LVL229: + 2559 .L192: + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2560 .loc 1 980 9 is_stmt 1 view .LVU763 + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + ARM GAS /tmp/cc42qbQx.s page 163 + + + 2561 .loc 1 980 25 is_stmt 0 view .LVU764 + 2562 0018 FFF7FEFF bl RCC_PLL_GetFreqDomain_48M + 2563 .LVL230: + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2564 .loc 1 980 25 view .LVU765 + 2565 001c FBE7 b .L188 + 2566 .LVL231: + 2567 .L189: + 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2568 .loc 1 986 7 is_stmt 1 view .LVU766 + 2569 .LBB388: + 2570 .LBI388: +4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2571 .loc 2 4179 26 view .LVU767 + 2572 .LBB389: +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2573 .loc 2 4181 3 view .LVU768 +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2574 .loc 2 4181 11 is_stmt 0 view .LVU769 + 2575 001e 044B ldr r3, .L193 + 2576 0020 1868 ldr r0, [r3] + 2577 .LVL232: +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2578 .loc 2 4181 11 view .LVU770 + 2579 .LBE389: + 2580 .LBE388: + 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2581 .loc 1 986 10 discriminator 1 view .LVU771 + 2582 0022 10F00050 ands r0, r0, #536870912 + 2583 0026 F6D0 beq .L188 + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2584 .loc 1 988 9 is_stmt 1 view .LVU772 + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2585 .loc 1 988 25 is_stmt 0 view .LVU773 + 2586 0028 FFF7FEFF bl RCC_PLLSAI_GetFreqDomain_48M + 2587 .LVL233: + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2588 .loc 1 993 3 is_stmt 1 view .LVU774 + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2589 .loc 1 993 10 is_stmt 0 view .LVU775 + 2590 002c F3E7 b .L188 + 2591 .L194: + 2592 002e 00BF .align 2 + 2593 .L193: + 2594 0030 00380240 .word 1073887232 + 2595 .cfi_endproc + 2596 .LFE304: + 2598 .section .text.LL_RCC_GetUSBClockFreq,"ax",%progbits + 2599 .align 1 + 2600 .global LL_RCC_GetUSBClockFreq + 2601 .syntax unified + 2602 .thumb + 2603 .thumb_func + 2605 LL_RCC_GetUSBClockFreq: + 2606 .LVL234: + 2607 .LFB306: +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + ARM GAS /tmp/cc42qbQx.s page 164 + + + 2608 .loc 1 1041 1 is_stmt 1 view -0 + 2609 .cfi_startproc + 2610 @ args = 0, pretend = 0, frame = 0 + 2611 @ frame_needed = 0, uses_anonymous_args = 0 +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 2612 .loc 1 1041 1 is_stmt 0 view .LVU777 + 2613 0000 08B5 push {r3, lr} + 2614 .LCFI11: + 2615 .cfi_def_cfa_offset 8 + 2616 .cfi_offset 3, -8 + 2617 .cfi_offset 14, -4 +1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 2618 .loc 1 1042 3 is_stmt 1 view .LVU778 + 2619 .LVL235: +1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 2620 .loc 1 1045 3 view .LVU779 +1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2621 .loc 1 1048 3 view .LVU780 + 2622 .LBB390: + 2623 .LBI390: +2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2624 .loc 2 2832 26 view .LVU781 + 2625 .LBB391: +2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2626 .loc 2 2834 3 view .LVU782 +2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2627 .loc 2 2834 21 is_stmt 0 view .LVU783 + 2628 0002 0B4B ldr r3, .L200 + 2629 0004 D3F89030 ldr r3, [r3, #144] + 2630 .LVL236: +2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2631 .loc 2 2834 21 view .LVU784 + 2632 .LBE391: + 2633 .LBE390: +1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2634 .loc 1 1048 3 discriminator 1 view .LVU785 + 2635 0008 1842 tst r0, r3 + 2636 000a 08D1 bne .L196 +1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2637 .loc 1 1051 7 is_stmt 1 view .LVU786 + 2638 .LBB392: + 2639 .LBI392: +3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2640 .loc 2 3153 26 view .LVU787 + 2641 .LBB393: +3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2642 .loc 2 3155 3 view .LVU788 +3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2643 .loc 2 3155 11 is_stmt 0 view .LVU789 + 2644 000c 084B ldr r3, .L200 + 2645 000e 1868 ldr r0, [r3] + 2646 .LVL237: +3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2647 .loc 2 3155 11 view .LVU790 + 2648 .LBE393: + 2649 .LBE392: +1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + ARM GAS /tmp/cc42qbQx.s page 165 + + + 2650 .loc 1 1051 10 discriminator 1 view .LVU791 + 2651 0010 10F00070 ands r0, r0, #33554432 + 2652 0014 00D1 bne .L199 + 2653 .LVL238: + 2654 .L195: +1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 2655 .loc 1 1067 1 view .LVU792 + 2656 0016 08BD pop {r3, pc} + 2657 .LVL239: + 2658 .L199: +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2659 .loc 1 1053 9 is_stmt 1 view .LVU793 +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2660 .loc 1 1053 25 is_stmt 0 view .LVU794 + 2661 0018 FFF7FEFF bl RCC_PLL_GetFreqDomain_48M + 2662 .LVL240: +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2663 .loc 1 1053 25 view .LVU795 + 2664 001c FBE7 b .L195 + 2665 .LVL241: + 2666 .L196: +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2667 .loc 1 1059 7 is_stmt 1 view .LVU796 + 2668 .LBB394: + 2669 .LBI394: +4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2670 .loc 2 4179 26 view .LVU797 + 2671 .LBB395: +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2672 .loc 2 4181 3 view .LVU798 +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2673 .loc 2 4181 11 is_stmt 0 view .LVU799 + 2674 001e 044B ldr r3, .L200 + 2675 0020 1868 ldr r0, [r3] + 2676 .LVL242: +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2677 .loc 2 4181 11 view .LVU800 + 2678 .LBE395: + 2679 .LBE394: +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2680 .loc 1 1059 10 discriminator 1 view .LVU801 + 2681 0022 10F00050 ands r0, r0, #536870912 + 2682 0026 F6D0 beq .L195 +1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2683 .loc 1 1061 9 is_stmt 1 view .LVU802 +1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2684 .loc 1 1061 25 is_stmt 0 view .LVU803 + 2685 0028 FFF7FEFF bl RCC_PLLSAI_GetFreqDomain_48M + 2686 .LVL243: +1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2687 .loc 1 1066 3 is_stmt 1 view .LVU804 +1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2688 .loc 1 1066 10 is_stmt 0 view .LVU805 + 2689 002c F3E7 b .L195 + 2690 .L201: + 2691 002e 00BF .align 2 + 2692 .L200: + ARM GAS /tmp/cc42qbQx.s page 166 + + + 2693 0030 00380240 .word 1073887232 + 2694 .cfi_endproc + 2695 .LFE306: + 2697 .section .text.RCC_PLLSAI_GetFreqDomain_LTDC,"ax",%progbits + 2698 .align 1 + 2699 .global RCC_PLLSAI_GetFreqDomain_LTDC + 2700 .syntax unified + 2701 .thumb + 2702 .thumb_func + 2704 RCC_PLLSAI_GetFreqDomain_LTDC: + 2705 .LFB319: +1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(LTDC) +1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return PLLSAI clock frequency used for LTDC domain +1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval PLLSAI clock frequency (in Hz) +1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void) +1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2706 .loc 1 1450 1 is_stmt 1 view -0 + 2707 .cfi_startproc + 2708 @ args = 0, pretend = 0, frame = 0 + 2709 @ frame_needed = 0, uses_anonymous_args = 0 + 2710 @ link register save eliminated. +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t pllinputfreq = 0U, pllsource = 0U; + 2711 .loc 1 1451 3 view .LVU807 + 2712 .LVL244: +1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN +1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR +1455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllsource = LL_RCC_PLL_GetMainSource(); + 2713 .loc 1 1456 3 view .LVU808 + 2714 .LBB396: + 2715 .LBI396: +3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2716 .loc 2 3461 26 view .LVU809 + 2717 .LBB397: +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2718 .loc 2 3463 3 view .LVU810 +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2719 .loc 2 3463 21 is_stmt 0 view .LVU811 + 2720 0000 114B ldr r3, .L205 + 2721 0002 5B68 ldr r3, [r3, #4] +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2722 .loc 2 3463 10 view .LVU812 + 2723 0004 03F48003 and r3, r3, #4194304 + 2724 .LVL245: +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2725 .loc 2 3463 10 view .LVU813 + 2726 .LBE397: + 2727 .LBE396: +1457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (pllsource) + 2728 .loc 1 1458 3 is_stmt 1 view .LVU814 + 2729 0008 DBB9 cbnz r3, .L204 +1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + ARM GAS /tmp/cc42qbQx.s page 167 + + +1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */ +1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; + 2730 .loc 1 1461 20 is_stmt 0 view .LVU815 + 2731 000a 1048 ldr r0, .L205+4 + 2732 .L203: + 2733 .LVL246: +1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */ +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSE_VALUE; +1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: +1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; +1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + 2734 .loc 1 1472 3 is_stmt 1 view .LVU816 + 2735 .LBB398: + 2736 .LBI398: +3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2737 .loc 2 3601 26 view .LVU817 + 2738 .LBB399: +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2739 .loc 2 3603 3 view .LVU818 +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2740 .loc 2 3603 21 is_stmt 0 view .LVU819 + 2741 000c 0E4A ldr r2, .L205 + 2742 000e 5368 ldr r3, [r2, #4] + 2743 .LVL247: +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2744 .loc 2 3603 10 view .LVU820 + 2745 0010 03F03F03 and r3, r3, #63 + 2746 .LBE399: + 2747 .LBE398: + 2748 .loc 1 1472 10 discriminator 1 view .LVU821 + 2749 0014 B0FBF3F0 udiv r0, r0, r3 + 2750 .LVL248: + 2751 .LBB400: + 2752 .LBI400: +4515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2753 .loc 2 4515 26 is_stmt 1 view .LVU822 + 2754 .LBB401: +4517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2755 .loc 2 4517 3 view .LVU823 +4517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2756 .loc 2 4517 21 is_stmt 0 view .LVU824 + 2757 0018 D2F88830 ldr r3, [r2, #136] +4517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2758 .loc 2 4517 10 view .LVU825 + 2759 001c C3F38813 ubfx r3, r3, #6, #9 + 2760 .LBE401: + 2761 .LBE400: + 2762 .loc 1 1472 10 discriminator 2 view .LVU826 + 2763 0020 03FB00F0 mul r0, r3, r0 + 2764 .LBB402: + 2765 .LBI402: + ARM GAS /tmp/cc42qbQx.s page 168 + + +4557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2766 .loc 2 4557 26 is_stmt 1 view .LVU827 + 2767 .LBB403: +4559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2768 .loc 2 4559 3 view .LVU828 +4559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2769 .loc 2 4559 21 is_stmt 0 view .LVU829 + 2770 0024 D2F88830 ldr r3, [r2, #136] + 2771 .LBE403: + 2772 .LBE402: + 2773 .loc 1 1472 10 discriminator 3 view .LVU830 + 2774 0028 C3F30273 ubfx r3, r3, #28, #3 + 2775 .LBB404: + 2776 .LBI404: +4619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_DCKCFGR1_PLLSAIDIVR) +4622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get SAIPLL division factor for PLLSAIDIVR +4624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note used for LTDC domain clock +4625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR +4626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +4627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 +4628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 +4629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 +4630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 +4631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void) + 2777 .loc 2 4632 26 is_stmt 1 view .LVU831 + 2778 .LBB405: +4633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR)); + 2779 .loc 2 4634 3 view .LVU832 + 2780 .loc 2 4634 21 is_stmt 0 view .LVU833 + 2781 002c D2F88C20 ldr r2, [r2, #140] + 2782 .LBE405: + 2783 .LBE404: + 2784 .loc 1 1472 10 discriminator 4 view .LVU834 + 2785 0030 C2F30142 ubfx r2, r2, #16, #2 + 2786 0034 0649 ldr r1, .L205+8 + 2787 0036 8A5C ldrb r2, [r1, r2] @ zero_extendqisi2 + 2788 0038 02FB03F3 mul r3, r2, r3 +1473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_G +1474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2789 .loc 1 1474 1 view .LVU835 + 2790 003c B0FBF3F0 udiv r0, r0, r3 + 2791 0040 7047 bx lr + 2792 .LVL249: + 2793 .L204: +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 2794 .loc 1 1465 20 view .LVU836 + 2795 0042 0448 ldr r0, .L205+12 + 2796 0044 E2E7 b .L203 + 2797 .L206: + 2798 0046 00BF .align 2 + 2799 .L205: + 2800 0048 00380240 .word 1073887232 + ARM GAS /tmp/cc42qbQx.s page 169 + + + 2801 004c 0024F400 .word 16000000 + 2802 0050 00000000 .word aRCC_PLLSAIDIVRPrescTable + 2803 0054 40787D01 .word 25000000 + 2804 .cfi_endproc + 2805 .LFE319: + 2807 .section .text.LL_RCC_GetLTDCClockFreq,"ax",%progbits + 2808 .align 1 + 2809 .global LL_RCC_GetLTDCClockFreq + 2810 .syntax unified + 2811 .thumb + 2812 .thumb_func + 2814 LL_RCC_GetLTDCClockFreq: + 2815 .LVL250: + 2816 .LFB309: +1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 2817 .loc 1 1175 1 is_stmt 1 view -0 + 2818 .cfi_startproc + 2819 @ args = 0, pretend = 0, frame = 0 + 2820 @ frame_needed = 0, uses_anonymous_args = 0 +1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 2821 .loc 1 1175 1 is_stmt 0 view .LVU838 + 2822 0000 08B5 push {r3, lr} + 2823 .LCFI12: + 2824 .cfi_def_cfa_offset 8 + 2825 .cfi_offset 3, -8 + 2826 .cfi_offset 14, -4 +1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 2827 .loc 1 1176 3 is_stmt 1 view .LVU839 + 2828 .LVL251: +1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 2829 .loc 1 1179 3 view .LVU840 +1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2830 .loc 1 1181 3 view .LVU841 + 2831 .LBB406: + 2832 .LBI406: +4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2833 .loc 2 4179 26 view .LVU842 + 2834 .LBB407: +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2835 .loc 2 4181 3 view .LVU843 +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2836 .loc 2 4181 11 is_stmt 0 view .LVU844 + 2837 0002 044B ldr r3, .L211 + 2838 0004 1868 ldr r0, [r3] + 2839 .LVL252: +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2840 .loc 2 4181 11 view .LVU845 + 2841 .LBE407: + 2842 .LBE406: +1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2843 .loc 1 1181 6 discriminator 1 view .LVU846 + 2844 0006 10F00050 ands r0, r0, #536870912 + 2845 000a 00D1 bne .L210 + 2846 .LVL253: + 2847 .L207: +1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* LTDC */ + 2848 .loc 1 1187 1 view .LVU847 + ARM GAS /tmp/cc42qbQx.s page 170 + + + 2849 000c 08BD pop {r3, pc} + 2850 .LVL254: + 2851 .L210: +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2852 .loc 1 1183 6 is_stmt 1 view .LVU848 +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2853 .loc 1 1183 23 is_stmt 0 view .LVU849 + 2854 000e FFF7FEFF bl RCC_PLLSAI_GetFreqDomain_LTDC + 2855 .LVL255: +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2856 .loc 1 1186 3 is_stmt 1 view .LVU850 +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2857 .loc 1 1186 10 is_stmt 0 view .LVU851 + 2858 0012 FBE7 b .L207 + 2859 .L212: + 2860 .align 2 + 2861 .L211: + 2862 0014 00380240 .word 1073887232 + 2863 .cfi_endproc + 2864 .LFE309: + 2866 .section .text.RCC_PLLI2S_GetFreqDomain_SAI,"ax",%progbits + 2867 .align 1 + 2868 .global RCC_PLLI2S_GetFreqDomain_SAI + 2869 .syntax unified + 2870 .thumb + 2871 .thumb_func + 2873 RCC_PLLI2S_GetFreqDomain_SAI: + 2874 .LFB320: +1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* LTDC */ +1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return PLLI2S clock frequency used for SAI1 and SAI2 domains +1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval PLLI2S clock frequency (in Hz) +1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void) +1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2875 .loc 1 1482 1 is_stmt 1 view -0 + 2876 .cfi_startproc + 2877 @ args = 0, pretend = 0, frame = 0 + 2878 @ frame_needed = 0, uses_anonymous_args = 0 + 2879 @ link register save eliminated. +1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t pllinputfreq = 0U, pllsource = 0U; + 2880 .loc 1 1483 3 view .LVU853 + 2881 .LVL256: +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** SAI1 and SAI2 domains clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ +1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllsource = LL_RCC_PLL_GetMainSource(); + 2882 .loc 1 1488 3 view .LVU854 + 2883 .LBB408: + 2884 .LBI408: +3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2885 .loc 2 3461 26 view .LVU855 + 2886 .LBB409: +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2887 .loc 2 3463 3 view .LVU856 + ARM GAS /tmp/cc42qbQx.s page 171 + + +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2888 .loc 2 3463 21 is_stmt 0 view .LVU857 + 2889 0000 104B ldr r3, .L216 + 2890 0002 5B68 ldr r3, [r3, #4] +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2891 .loc 2 3463 10 view .LVU858 + 2892 0004 03F48003 and r3, r3, #4194304 + 2893 .LVL257: +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2894 .loc 2 3463 10 view .LVU859 + 2895 .LBE409: + 2896 .LBE408: +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (pllsource) + 2897 .loc 1 1490 3 is_stmt 1 view .LVU860 + 2898 0008 CBB9 cbnz r3, .L215 +1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */ +1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; + 2899 .loc 1 1493 20 is_stmt 0 view .LVU861 + 2900 000a 0F48 ldr r0, .L216+4 + 2901 .L214: + 2902 .LVL258: +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */ +1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSE_VALUE; +1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: +1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; +1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return __LL_RCC_CALC_PLLI2S_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + 2903 .loc 1 1504 3 is_stmt 1 view .LVU862 + 2904 .LBB410: + 2905 .LBI410: +3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2906 .loc 2 3601 26 view .LVU863 + 2907 .LBB411: +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2908 .loc 2 3603 3 view .LVU864 +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2909 .loc 2 3603 21 is_stmt 0 view .LVU865 + 2910 000c 0D4A ldr r2, .L216 + 2911 000e 5368 ldr r3, [r2, #4] + 2912 .LVL259: +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2913 .loc 2 3603 10 view .LVU866 + 2914 0010 03F03F03 and r3, r3, #63 + 2915 .LBE411: + 2916 .LBE410: + 2917 .loc 1 1504 10 discriminator 1 view .LVU867 + 2918 0014 B0FBF3F0 udiv r0, r0, r3 + 2919 .LVL260: + 2920 .LBB412: + 2921 .LBI412: + ARM GAS /tmp/cc42qbQx.s page 172 + + +4040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2922 .loc 2 4040 26 is_stmt 1 view .LVU868 + 2923 .LBB413: +4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2924 .loc 2 4042 3 view .LVU869 +4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2925 .loc 2 4042 21 is_stmt 0 view .LVU870 + 2926 0018 D2F88430 ldr r3, [r2, #132] +4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2927 .loc 2 4042 10 view .LVU871 + 2928 001c C3F38813 ubfx r3, r3, #6, #9 + 2929 .LBE413: + 2930 .LBE412: + 2931 .loc 1 1504 10 discriminator 2 view .LVU872 + 2932 0020 03FB00F0 mul r0, r3, r0 + 2933 .LBB414: + 2934 .LBI414: +4064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2935 .loc 2 4064 26 is_stmt 1 view .LVU873 + 2936 .LBB415: +4066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2937 .loc 2 4066 3 view .LVU874 +4066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2938 .loc 2 4066 21 is_stmt 0 view .LVU875 + 2939 0024 D2F88430 ldr r3, [r2, #132] + 2940 .LBE415: + 2941 .LBE414: + 2942 .loc 1 1504 10 discriminator 3 view .LVU876 + 2943 0028 C3F30363 ubfx r3, r3, #24, #4 + 2944 .LBB416: + 2945 .LBI416: +4141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 2946 .loc 2 4141 26 is_stmt 1 view .LVU877 + 2947 .LBB417: +4143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2948 .loc 2 4143 3 view .LVU878 +4143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2949 .loc 2 4143 21 is_stmt 0 view .LVU879 + 2950 002c D2F88C20 ldr r2, [r2, #140] +4143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 2951 .loc 2 4143 10 view .LVU880 + 2952 0030 02F01F02 and r2, r2, #31 + 2953 .LBE417: + 2954 .LBE416: + 2955 .loc 1 1504 10 discriminator 4 view .LVU881 + 2956 0034 02FB0333 mla r3, r2, r3, r3 +1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_G +1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 2957 .loc 1 1506 1 view .LVU882 + 2958 0038 B0FBF3F0 udiv r0, r0, r3 + 2959 003c 7047 bx lr + 2960 .LVL261: + 2961 .L215: +1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 2962 .loc 1 1497 20 view .LVU883 + 2963 003e 0348 ldr r0, .L216+8 + 2964 0040 E4E7 b .L214 + ARM GAS /tmp/cc42qbQx.s page 173 + + + 2965 .L217: + 2966 0042 00BF .align 2 + 2967 .L216: + 2968 0044 00380240 .word 1073887232 + 2969 0048 0024F400 .word 16000000 + 2970 004c 40787D01 .word 25000000 + 2971 .cfi_endproc + 2972 .LFE320: + 2974 .section .text.LL_RCC_GetSAIClockFreq,"ax",%progbits + 2975 .align 1 + 2976 .global LL_RCC_GetSAIClockFreq + 2977 .syntax unified + 2978 .thumb + 2979 .thumb_func + 2981 LL_RCC_GetSAIClockFreq: + 2982 .LVL262: + 2983 .LFB302: + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 2984 .loc 1 766 1 is_stmt 1 view -0 + 2985 .cfi_startproc + 2986 @ args = 0, pretend = 0, frame = 0 + 2987 @ frame_needed = 0, uses_anonymous_args = 0 + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 2988 .loc 1 766 1 is_stmt 0 view .LVU885 + 2989 0000 08B5 push {r3, lr} + 2990 .LCFI13: + 2991 .cfi_def_cfa_offset 8 + 2992 .cfi_offset 3, -8 + 2993 .cfi_offset 14, -4 + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 2994 .loc 1 767 3 is_stmt 1 view .LVU886 + 2995 .LVL263: + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 2996 .loc 1 770 3 view .LVU887 + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2997 .loc 1 772 3 view .LVU888 + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 2998 .loc 1 772 6 is_stmt 0 view .LVU889 + 2999 0002 B0F5401F cmp r0, #3145728 + 3000 0006 04D0 beq .L239 + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3001 .loc 1 822 5 is_stmt 1 view .LVU890 + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3002 .loc 1 822 8 is_stmt 0 view .LVU891 + 3003 0008 B0F5400F cmp r0, #12582912 + 3004 000c 3BD0 beq .L240 + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 3005 .loc 1 767 12 view .LVU892 + 3006 000e 0020 movs r0, #0 + 3007 .LVL264: + 3008 .L218: + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 3009 .loc 1 873 1 view .LVU893 + 3010 0010 08BD pop {r3, pc} + 3011 .LVL265: + 3012 .L239: + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + ARM GAS /tmp/cc42qbQx.s page 174 + + + 3013 .loc 1 775 5 is_stmt 1 view .LVU894 + 3014 .LBB418: + 3015 .LBI418: +2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3016 .loc 2 2770 26 view .LVU895 + 3017 .LBB419: +2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3018 .loc 2 2772 3 view .LVU896 +2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3019 .loc 2 2772 21 is_stmt 0 view .LVU897 + 3020 0012 3D4B ldr r3, .L245 + 3021 0014 D3F88C30 ldr r3, [r3, #140] + 3022 0018 0340 ands r3, r3, r0 +2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3023 .loc 2 2772 10 view .LVU898 + 3024 001a 40EA1340 orr r0, r0, r3, lsr #16 + 3025 .LVL266: +2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3026 .loc 2 2772 10 view .LVU899 + 3027 .LBE419: + 3028 .LBE418: + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3029 .loc 1 775 5 discriminator 1 view .LVU900 + 3030 001e 3B4B ldr r3, .L245+4 + 3031 0020 9842 cmp r0, r3 + 3032 0022 6AD0 beq .L231 + 3033 0024 0FD8 bhi .L221 + 3034 0026 B0F5401F cmp r0, #3145728 + 3035 002a 1DD0 beq .L222 + 3036 002c 103B subs r3, r3, #16 + 3037 002e 9842 cmp r0, r3 + 3038 0030 07D1 bne .L241 + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3039 .loc 1 785 9 is_stmt 1 view .LVU901 + 3040 .LBB420: + 3041 .LBI420: +3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3042 .loc 2 3711 26 view .LVU902 + 3043 .LBB421: +3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3044 .loc 2 3713 3 view .LVU903 +3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3045 .loc 2 3713 11 is_stmt 0 view .LVU904 + 3046 0032 354B ldr r3, .L245 + 3047 0034 1868 ldr r0, [r3] + 3048 .LBE421: + 3049 .LBE420: + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3050 .loc 1 785 12 discriminator 1 view .LVU905 + 3051 0036 10F00060 ands r0, r0, #134217728 + 3052 003a E9D0 beq .L218 + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3053 .loc 1 787 11 is_stmt 1 view .LVU906 + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3054 .loc 1 787 27 is_stmt 0 view .LVU907 + 3055 003c FFF7FEFF bl RCC_PLLI2S_GetFreqDomain_SAI + 3056 .LVL267: + ARM GAS /tmp/cc42qbQx.s page 175 + + + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3057 .loc 1 787 27 view .LVU908 + 3058 0040 E6E7 b .L218 + 3059 .LVL268: + 3060 .L241: + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3061 .loc 1 775 5 discriminator 1 view .LVU909 + 3062 0042 0020 movs r0, #0 + 3063 0044 E4E7 b .L218 + 3064 .L221: + 3065 0046 B0F1301F cmp r0, #3145776 + 3066 004a 0BD1 bne .L242 + 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3067 .loc 1 793 9 is_stmt 1 view .LVU910 + 3068 .LBB422: + 3069 .LBI422: +3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3070 .loc 2 3461 26 view .LVU911 + 3071 .LBB423: +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3072 .loc 2 3463 3 view .LVU912 +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3073 .loc 2 3463 21 is_stmt 0 view .LVU913 + 3074 004c 2E4B ldr r3, .L245 + 3075 004e 5B68 ldr r3, [r3, #4] + 3076 .LBE423: + 3077 .LBE422: + 3078 0050 13F4800F tst r3, #4194304 + 3079 0054 10D0 beq .L225 + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3080 .loc 1 796 14 is_stmt 1 view .LVU914 + 3081 .LBB424: + 3082 .LBI424: +1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3083 .loc 2 1992 26 view .LVU915 + 3084 .LBB425: +1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3085 .loc 2 1994 3 view .LVU916 +1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3086 .loc 2 1994 11 is_stmt 0 view .LVU917 + 3087 0056 2C4B ldr r3, .L245 + 3088 0058 1868 ldr r0, [r3] + 3089 .LBE425: + 3090 .LBE424: + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3091 .loc 1 796 17 discriminator 1 view .LVU918 + 3092 005a 10F40030 ands r0, r0, #131072 + 3093 005e D7D0 beq .L218 + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3094 .loc 1 798 30 view .LVU919 + 3095 0060 2B48 ldr r0, .L245+8 + 3096 0062 D5E7 b .L218 + 3097 .L242: + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3098 .loc 1 775 5 discriminator 1 view .LVU920 + 3099 0064 0020 movs r0, #0 + 3100 0066 D3E7 b .L218 + ARM GAS /tmp/cc42qbQx.s page 176 + + + 3101 .L222: + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3102 .loc 1 778 9 is_stmt 1 view .LVU921 + 3103 .LBB426: + 3104 .LBI426: +4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3105 .loc 2 4179 26 view .LVU922 + 3106 .LBB427: +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3107 .loc 2 4181 3 view .LVU923 +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3108 .loc 2 4181 11 is_stmt 0 view .LVU924 + 3109 0068 274B ldr r3, .L245 + 3110 006a 1868 ldr r0, [r3] + 3111 .LBE427: + 3112 .LBE426: + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3113 .loc 1 778 12 discriminator 1 view .LVU925 + 3114 006c 10F00050 ands r0, r0, #536870912 + 3115 0070 CED0 beq .L218 + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3116 .loc 1 780 11 is_stmt 1 view .LVU926 + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3117 .loc 1 780 27 is_stmt 0 view .LVU927 + 3118 0072 FFF7FEFF bl RCC_PLLSAI_GetFreqDomain_SAI + 3119 .LVL269: + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3120 .loc 1 780 27 view .LVU928 + 3121 0076 CBE7 b .L218 + 3122 .LVL270: + 3123 .L225: + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3124 .loc 1 804 14 is_stmt 1 view .LVU929 + 3125 .LBB428: + 3126 .LBI428: +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3127 .loc 2 2030 26 view .LVU930 + 3128 .LBB429: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3129 .loc 2 2032 3 view .LVU931 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3130 .loc 2 2032 11 is_stmt 0 view .LVU932 + 3131 0078 234B ldr r3, .L245 + 3132 007a 1868 ldr r0, [r3] + 3133 .LBE429: + 3134 .LBE428: + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3135 .loc 1 804 17 discriminator 1 view .LVU933 + 3136 007c 10F00200 ands r0, r0, #2 + 3137 0080 C6D0 beq .L218 + 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3138 .loc 1 806 30 view .LVU934 + 3139 0082 2448 ldr r0, .L245+12 + 3140 0084 C4E7 b .L218 + 3141 .LVL271: + 3142 .L240: + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + ARM GAS /tmp/cc42qbQx.s page 177 + + + 3143 .loc 1 825 7 is_stmt 1 view .LVU935 + 3144 .LBB430: + 3145 .LBI430: +2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3146 .loc 2 2770 26 view .LVU936 + 3147 .LBB431: +2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3148 .loc 2 2772 3 view .LVU937 +2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3149 .loc 2 2772 21 is_stmt 0 view .LVU938 + 3150 0086 204B ldr r3, .L245 + 3151 0088 D3F88C30 ldr r3, [r3, #140] + 3152 008c 0340 ands r3, r3, r0 +2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3153 .loc 2 2772 10 view .LVU939 + 3154 008e 40EA1340 orr r0, r0, r3, lsr #16 + 3155 .LVL272: +2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3156 .loc 2 2772 10 view .LVU940 + 3157 .LBE431: + 3158 .LBE430: + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3159 .loc 1 825 7 discriminator 1 view .LVU941 + 3160 0092 214B ldr r3, .L245+16 + 3161 0094 9842 cmp r0, r3 + 3162 0096 33D0 beq .L235 + 3163 0098 0FD8 bhi .L226 + 3164 009a B0F5400F cmp r0, #12582912 + 3165 009e 1DD0 beq .L227 + 3166 00a0 403B subs r3, r3, #64 + 3167 00a2 9842 cmp r0, r3 + 3168 00a4 07D1 bne .L243 + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3169 .loc 1 835 9 is_stmt 1 view .LVU942 + 3170 .LBB432: + 3171 .LBI432: +3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3172 .loc 2 3711 26 view .LVU943 + 3173 .LBB433: +3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3174 .loc 2 3713 3 view .LVU944 +3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3175 .loc 2 3713 11 is_stmt 0 view .LVU945 + 3176 00a6 184B ldr r3, .L245 + 3177 00a8 1868 ldr r0, [r3] + 3178 .LBE433: + 3179 .LBE432: + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3180 .loc 1 835 12 discriminator 1 view .LVU946 + 3181 00aa 10F00060 ands r0, r0, #134217728 + 3182 00ae AFD0 beq .L218 + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3183 .loc 1 837 11 is_stmt 1 view .LVU947 + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3184 .loc 1 837 27 is_stmt 0 view .LVU948 + 3185 00b0 FFF7FEFF bl RCC_PLLI2S_GetFreqDomain_SAI + 3186 .LVL273: + ARM GAS /tmp/cc42qbQx.s page 178 + + + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3187 .loc 1 837 27 view .LVU949 + 3188 00b4 ACE7 b .L218 + 3189 .LVL274: + 3190 .L243: + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3191 .loc 1 825 7 discriminator 1 view .LVU950 + 3192 00b6 0020 movs r0, #0 + 3193 00b8 AAE7 b .L218 + 3194 .L226: + 3195 00ba B0F1C01F cmp r0, #12583104 + 3196 00be 0BD1 bne .L244 + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3197 .loc 1 843 9 is_stmt 1 view .LVU951 + 3198 .LBB434: + 3199 .LBI434: +3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3200 .loc 2 3461 26 view .LVU952 + 3201 .LBB435: +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3202 .loc 2 3463 3 view .LVU953 +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3203 .loc 2 3463 21 is_stmt 0 view .LVU954 + 3204 00c0 114B ldr r3, .L245 + 3205 00c2 5B68 ldr r3, [r3, #4] + 3206 .LBE435: + 3207 .LBE434: + 3208 00c4 13F4800F tst r3, #4194304 + 3209 00c8 10D0 beq .L230 + 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3210 .loc 1 846 14 is_stmt 1 view .LVU955 + 3211 .LBB436: + 3212 .LBI436: +1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3213 .loc 2 1992 26 view .LVU956 + 3214 .LBB437: +1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3215 .loc 2 1994 3 view .LVU957 +1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3216 .loc 2 1994 11 is_stmt 0 view .LVU958 + 3217 00ca 0F4B ldr r3, .L245 + 3218 00cc 1868 ldr r0, [r3] + 3219 .LBE437: + 3220 .LBE436: + 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3221 .loc 1 846 17 discriminator 1 view .LVU959 + 3222 00ce 10F40030 ands r0, r0, #131072 + 3223 00d2 9DD0 beq .L218 + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3224 .loc 1 848 30 view .LVU960 + 3225 00d4 0E48 ldr r0, .L245+8 + 3226 00d6 9BE7 b .L218 + 3227 .L244: + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3228 .loc 1 825 7 discriminator 1 view .LVU961 + 3229 00d8 0020 movs r0, #0 + 3230 00da 99E7 b .L218 + ARM GAS /tmp/cc42qbQx.s page 179 + + + 3231 .L227: + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3232 .loc 1 828 9 is_stmt 1 view .LVU962 + 3233 .LBB438: + 3234 .LBI438: +4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3235 .loc 2 4179 26 view .LVU963 + 3236 .LBB439: +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3237 .loc 2 4181 3 view .LVU964 +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3238 .loc 2 4181 11 is_stmt 0 view .LVU965 + 3239 00dc 0A4B ldr r3, .L245 + 3240 00de 1868 ldr r0, [r3] + 3241 .LBE439: + 3242 .LBE438: + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3243 .loc 1 828 12 discriminator 1 view .LVU966 + 3244 00e0 10F00050 ands r0, r0, #536870912 + 3245 00e4 94D0 beq .L218 + 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3246 .loc 1 830 11 is_stmt 1 view .LVU967 + 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3247 .loc 1 830 27 is_stmt 0 view .LVU968 + 3248 00e6 FFF7FEFF bl RCC_PLLSAI_GetFreqDomain_SAI + 3249 .LVL275: + 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3250 .loc 1 830 27 view .LVU969 + 3251 00ea 91E7 b .L218 + 3252 .LVL276: + 3253 .L230: + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3254 .loc 1 854 14 is_stmt 1 view .LVU970 + 3255 .LBB440: + 3256 .LBI440: +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3257 .loc 2 2030 26 view .LVU971 + 3258 .LBB441: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3259 .loc 2 2032 3 view .LVU972 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3260 .loc 2 2032 11 is_stmt 0 view .LVU973 + 3261 00ec 064B ldr r3, .L245 + 3262 00ee 1868 ldr r0, [r3] + 3263 .LBE441: + 3264 .LBE440: + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3265 .loc 1 854 17 discriminator 1 view .LVU974 + 3266 00f0 10F00200 ands r0, r0, #2 + 3267 00f4 8CD0 beq .L218 + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3268 .loc 1 856 30 view .LVU975 + 3269 00f6 0748 ldr r0, .L245+12 + 3270 .LVL277: + 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3271 .loc 1 872 3 is_stmt 1 view .LVU976 + 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + ARM GAS /tmp/cc42qbQx.s page 180 + + + 3272 .loc 1 872 10 is_stmt 0 view .LVU977 + 3273 00f8 8AE7 b .L218 + 3274 .LVL278: + 3275 .L231: + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 3276 .loc 1 813 23 view .LVU978 + 3277 00fa 4BF68030 movw r0, #48000 + 3278 00fe 87E7 b .L218 + 3279 .L235: + 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 3280 .loc 1 863 25 view .LVU979 + 3281 0100 4BF68030 movw r0, #48000 + 3282 0104 84E7 b .L218 + 3283 .L246: + 3284 0106 00BF .align 2 + 3285 .L245: + 3286 0108 00380240 .word 1073887232 + 3287 010c 20003000 .word 3145760 + 3288 0110 40787D01 .word 25000000 + 3289 0114 0024F400 .word 16000000 + 3290 0118 8000C000 .word 12583040 + 3291 .cfi_endproc + 3292 .LFE302: + 3294 .section .text.LL_RCC_GetDFSDMAudioClockFreq,"ax",%progbits + 3295 .align 1 + 3296 .global LL_RCC_GetDFSDMAudioClockFreq + 3297 .syntax unified + 3298 .thumb + 3299 .thumb_func + 3301 LL_RCC_GetDFSDMAudioClockFreq: + 3302 .LVL279: + 3303 .LFB308: +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 3304 .loc 1 1107 1 is_stmt 1 view -0 + 3305 .cfi_startproc + 3306 @ args = 0, pretend = 0, frame = 0 + 3307 @ frame_needed = 0, uses_anonymous_args = 0 +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 3308 .loc 1 1107 1 is_stmt 0 view .LVU981 + 3309 0000 08B5 push {r3, lr} + 3310 .LCFI14: + 3311 .cfi_def_cfa_offset 8 + 3312 .cfi_offset 3, -8 + 3313 .cfi_offset 14, -4 +1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 3314 .loc 1 1108 3 is_stmt 1 view .LVU982 + 3315 .LVL280: +1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 3316 .loc 1 1111 3 view .LVU983 +1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3317 .loc 1 1114 3 view .LVU984 + 3318 .LBB442: + 3319 .LBI442: +2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3320 .loc 2 2877 26 view .LVU985 + 3321 .LBB443: +2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + ARM GAS /tmp/cc42qbQx.s page 181 + + + 3322 .loc 2 2879 3 view .LVU986 +2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3323 .loc 2 2879 21 is_stmt 0 view .LVU987 + 3324 0002 074B ldr r3, .L251 + 3325 0004 D3F88C30 ldr r3, [r3, #140] + 3326 .LVL281: +2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3327 .loc 2 2879 21 view .LVU988 + 3328 .LBE443: + 3329 .LBE442: +1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3330 .loc 1 1114 3 discriminator 1 view .LVU989 + 3331 0008 1842 tst r0, r3 + 3332 000a 04D1 bne .L248 +1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 3333 .loc 1 1117 7 is_stmt 1 view .LVU990 +1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 3334 .loc 1 1117 25 is_stmt 0 view .LVU991 + 3335 000c 4FF44010 mov r0, #3145728 + 3336 .LVL282: +1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 3337 .loc 1 1117 25 view .LVU992 + 3338 0010 FFF7FEFF bl LL_RCC_GetSAIClockFreq + 3339 .LVL283: +1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 3340 .loc 1 1118 7 is_stmt 1 view .LVU993 + 3341 .L247: +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* DFSDM1_Channel0 */ + 3342 .loc 1 1127 1 is_stmt 0 view .LVU994 + 3343 0014 08BD pop {r3, pc} + 3344 .LVL284: + 3345 .L248: +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 3346 .loc 1 1122 7 is_stmt 1 view .LVU995 +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 3347 .loc 1 1122 25 is_stmt 0 view .LVU996 + 3348 0016 4FF44000 mov r0, #12582912 + 3349 .LVL285: +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 3350 .loc 1 1122 25 view .LVU997 + 3351 001a FFF7FEFF bl LL_RCC_GetSAIClockFreq + 3352 .LVL286: +1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3353 .loc 1 1123 7 is_stmt 1 view .LVU998 +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3354 .loc 1 1126 3 view .LVU999 +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3355 .loc 1 1126 10 is_stmt 0 view .LVU1000 + 3356 001e F9E7 b .L247 + 3357 .L252: + 3358 .align 2 + 3359 .L251: + 3360 0020 00380240 .word 1073887232 + 3361 .cfi_endproc + 3362 .LFE308: + 3364 .section .text.RCC_PLLI2S_GetFreqDomain_SPDIFRX,"ax",%progbits + 3365 .align 1 + ARM GAS /tmp/cc42qbQx.s page 182 + + + 3366 .global RCC_PLLI2S_GetFreqDomain_SPDIFRX + 3367 .syntax unified + 3368 .thumb + 3369 .thumb_func + 3371 RCC_PLLI2S_GetFreqDomain_SPDIFRX: + 3372 .LFB321: +1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #if defined(SPDIFRX) +1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** +1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return PLLI2S clock frequency used for SPDIFRX domain +1511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval PLLI2S clock frequency (in Hz) +1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void) +1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3373 .loc 1 1514 1 is_stmt 1 view -0 + 3374 .cfi_startproc + 3375 @ args = 0, pretend = 0, frame = 0 + 3376 @ frame_needed = 0, uses_anonymous_args = 0 + 3377 @ link register save eliminated. +1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t pllinputfreq = 0U, pllsource = 0U; + 3378 .loc 1 1515 3 view .LVU1002 + 3379 .LVL287: +1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN +1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP +1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllsource = LL_RCC_PLL_GetMainSource(); + 3380 .loc 1 1520 3 view .LVU1003 + 3381 .LBB444: + 3382 .LBI444: +3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3383 .loc 2 3461 26 view .LVU1004 + 3384 .LBB445: +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3385 .loc 2 3463 3 view .LVU1005 +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3386 .loc 2 3463 21 is_stmt 0 view .LVU1006 + 3387 0000 0E4B ldr r3, .L256 + 3388 0002 5B68 ldr r3, [r3, #4] +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3389 .loc 2 3463 10 view .LVU1007 + 3390 0004 03F48003 and r3, r3, #4194304 + 3391 .LVL288: +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3392 .loc 2 3463 10 view .LVU1008 + 3393 .LBE445: + 3394 .LBE444: +1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (pllsource) + 3395 .loc 1 1522 3 is_stmt 1 view .LVU1009 + 3396 0008 ABB9 cbnz r3, .L255 +1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */ +1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; + 3397 .loc 1 1525 20 is_stmt 0 view .LVU1010 + 3398 000a 0D48 ldr r0, .L256+4 + 3399 .L254: + ARM GAS /tmp/cc42qbQx.s page 183 + + + 3400 .LVL289: +1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */ +1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSE_VALUE; +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: +1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; +1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + 3401 .loc 1 1537 3 is_stmt 1 view .LVU1011 + 3402 .LBB446: + 3403 .LBI446: +3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3404 .loc 2 3601 26 view .LVU1012 + 3405 .LBB447: +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3406 .loc 2 3603 3 view .LVU1013 +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3407 .loc 2 3603 21 is_stmt 0 view .LVU1014 + 3408 000c 0B4B ldr r3, .L256 + 3409 .LVL290: +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3410 .loc 2 3603 21 view .LVU1015 + 3411 000e 5A68 ldr r2, [r3, #4] +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3412 .loc 2 3603 10 view .LVU1016 + 3413 0010 02F03F02 and r2, r2, #63 + 3414 .LBE447: + 3415 .LBE446: + 3416 .loc 1 1537 10 discriminator 1 view .LVU1017 + 3417 0014 B0FBF2F0 udiv r0, r0, r2 + 3418 .LVL291: + 3419 .LBB448: + 3420 .LBI448: +4040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3421 .loc 2 4040 26 is_stmt 1 view .LVU1018 + 3422 .LBB449: +4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3423 .loc 2 4042 3 view .LVU1019 +4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3424 .loc 2 4042 21 is_stmt 0 view .LVU1020 + 3425 0018 D3F88420 ldr r2, [r3, #132] +4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3426 .loc 2 4042 10 view .LVU1021 + 3427 001c C2F38812 ubfx r2, r2, #6, #9 + 3428 .LBE449: + 3429 .LBE448: + 3430 .loc 1 1537 10 discriminator 2 view .LVU1022 + 3431 0020 02FB00F0 mul r0, r2, r0 + 3432 .LBB450: + 3433 .LBI450: +4097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3434 .loc 2 4097 26 is_stmt 1 view .LVU1023 + ARM GAS /tmp/cc42qbQx.s page 184 + + + 3435 .LBB451: +4099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3436 .loc 2 4099 3 view .LVU1024 +4099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3437 .loc 2 4099 21 is_stmt 0 view .LVU1025 + 3438 0024 D3F88430 ldr r3, [r3, #132] + 3439 .LBE451: + 3440 .LBE450: + 3441 .loc 1 1537 10 discriminator 3 view .LVU1026 + 3442 0028 C3F30143 ubfx r3, r3, #16, #2 + 3443 002c 0133 adds r3, r3, #1 + 3444 002e 5B00 lsls r3, r3, #1 +1538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP()); +1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3445 .loc 1 1539 1 view .LVU1027 + 3446 0030 B0FBF3F0 udiv r0, r0, r3 + 3447 0034 7047 bx lr + 3448 .LVL292: + 3449 .L255: +1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 3450 .loc 1 1529 20 view .LVU1028 + 3451 0036 0348 ldr r0, .L256+8 + 3452 0038 E8E7 b .L254 + 3453 .L257: + 3454 003a 00BF .align 2 + 3455 .L256: + 3456 003c 00380240 .word 1073887232 + 3457 0040 0024F400 .word 16000000 + 3458 0044 40787D01 .word 25000000 + 3459 .cfi_endproc + 3460 .LFE321: + 3462 .section .text.LL_RCC_GetSPDIFRXClockFreq,"ax",%progbits + 3463 .align 1 + 3464 .global LL_RCC_GetSPDIFRXClockFreq + 3465 .syntax unified + 3466 .thumb + 3467 .thumb_func + 3469 LL_RCC_GetSPDIFRXClockFreq: + 3470 .LVL293: + 3471 .LFB310: +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 3472 .loc 1 1199 1 is_stmt 1 view -0 + 3473 .cfi_startproc + 3474 @ args = 0, pretend = 0, frame = 0 + 3475 @ frame_needed = 0, uses_anonymous_args = 0 +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 3476 .loc 1 1199 1 is_stmt 0 view .LVU1030 + 3477 0000 08B5 push {r3, lr} + 3478 .LCFI15: + 3479 .cfi_def_cfa_offset 8 + 3480 .cfi_offset 3, -8 + 3481 .cfi_offset 14, -4 +1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 3482 .loc 1 1200 3 is_stmt 1 view .LVU1031 + 3483 .LVL294: +1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 3484 .loc 1 1203 3 view .LVU1032 + ARM GAS /tmp/cc42qbQx.s page 185 + + +1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3485 .loc 1 1205 3 view .LVU1033 + 3486 .LBB452: + 3487 .LBI452: +3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3488 .loc 2 3711 26 view .LVU1034 + 3489 .LBB453: +3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3490 .loc 2 3713 3 view .LVU1035 +3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3491 .loc 2 3713 11 is_stmt 0 view .LVU1036 + 3492 0002 044B ldr r3, .L262 + 3493 0004 1868 ldr r0, [r3] + 3494 .LVL295: +3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3495 .loc 2 3713 11 view .LVU1037 + 3496 .LBE453: + 3497 .LBE452: +1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3498 .loc 1 1205 6 discriminator 1 view .LVU1038 + 3499 0006 10F00060 ands r0, r0, #134217728 + 3500 000a 00D1 bne .L261 + 3501 .LVL296: + 3502 .L258: +1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* SPDIFRX */ + 3503 .loc 1 1211 1 view .LVU1039 + 3504 000c 08BD pop {r3, pc} + 3505 .LVL297: + 3506 .L261: +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3507 .loc 1 1207 6 is_stmt 1 view .LVU1040 +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3508 .loc 1 1207 26 is_stmt 0 view .LVU1041 + 3509 000e FFF7FEFF bl RCC_PLLI2S_GetFreqDomain_SPDIFRX + 3510 .LVL298: +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3511 .loc 1 1210 3 is_stmt 1 view .LVU1042 +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3512 .loc 1 1210 10 is_stmt 0 view .LVU1043 + 3513 0012 FBE7 b .L258 + 3514 .L263: + 3515 .align 2 + 3516 .L262: + 3517 0014 00380240 .word 1073887232 + 3518 .cfi_endproc + 3519 .LFE310: + 3521 .section .text.RCC_PLLI2S_GetFreqDomain_I2S,"ax",%progbits + 3522 .align 1 + 3523 .global RCC_PLLI2S_GetFreqDomain_I2S + 3524 .syntax unified + 3525 .thumb + 3526 .thumb_func + 3528 RCC_PLLI2S_GetFreqDomain_I2S: + 3529 .LFB322: +1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** #endif /* SPDIFRX */ +1541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /** + ARM GAS /tmp/cc42qbQx.s page 186 + + +1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @brief Return PLLI2S clock frequency used for I2S domain +1544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** * @retval PLLI2S clock frequency (in Hz) +1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void) +1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3530 .loc 1 1547 1 is_stmt 1 view -0 + 3531 .cfi_startproc + 3532 @ args = 0, pretend = 0, frame = 0 + 3533 @ frame_needed = 0, uses_anonymous_args = 0 + 3534 @ link register save eliminated. +1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t pllinputfreq = 0U, pllsource = 0U; + 3535 .loc 1 1548 3 view .LVU1045 + 3536 .LVL299: +1549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN +1551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** I2S Domain clock = PLLI2S_VCO / PLLI2SR +1552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** */ +1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllsource = LL_RCC_PLL_GetMainSource(); + 3537 .loc 1 1553 3 view .LVU1046 + 3538 .LBB454: + 3539 .LBI454: +3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3540 .loc 2 3461 26 view .LVU1047 + 3541 .LBB455: +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3542 .loc 2 3463 3 view .LVU1048 +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3543 .loc 2 3463 21 is_stmt 0 view .LVU1049 + 3544 0000 0D4B ldr r3, .L267 + 3545 0002 5B68 ldr r3, [r3, #4] + 3546 .LVL300: +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3547 .loc 2 3463 21 view .LVU1050 + 3548 .LBE455: + 3549 .LBE454: +1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** switch (pllsource) + 3550 .loc 1 1555 3 is_stmt 1 view .LVU1051 + 3551 0004 13F4800F tst r3, #4194304 + 3552 0008 13D0 beq .L266 +1556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { +1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */ +1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSE_VALUE; + 3553 .loc 1 1558 20 is_stmt 0 view .LVU1052 + 3554 000a 0C4B ldr r3, .L267+4 + 3555 .LVL301: + 3556 .L265: +1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** +1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */ +1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** default: +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** pllinputfreq = HSI_VALUE; +1564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; +1565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } +1566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** return __LL_RCC_CALC_PLLI2S_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + 3557 .loc 1 1566 3 is_stmt 1 view .LVU1053 + 3558 .LBB456: + ARM GAS /tmp/cc42qbQx.s page 187 + + + 3559 .LBI456: +3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3560 .loc 2 3601 26 view .LVU1054 + 3561 .LBB457: +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3562 .loc 2 3603 3 view .LVU1055 +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3563 .loc 2 3603 21 is_stmt 0 view .LVU1056 + 3564 000c 0A4A ldr r2, .L267 + 3565 000e 5168 ldr r1, [r2, #4] +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3566 .loc 2 3603 10 view .LVU1057 + 3567 0010 01F03F01 and r1, r1, #63 + 3568 .LBE457: + 3569 .LBE456: + 3570 .loc 1 1566 10 discriminator 1 view .LVU1058 + 3571 0014 B3FBF1F3 udiv r3, r3, r1 + 3572 .LVL302: + 3573 .LBB458: + 3574 .LBI458: +4040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3575 .loc 2 4040 26 is_stmt 1 view .LVU1059 + 3576 .LBB459: +4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3577 .loc 2 4042 3 view .LVU1060 +4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3578 .loc 2 4042 21 is_stmt 0 view .LVU1061 + 3579 0018 D2F88410 ldr r1, [r2, #132] +4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3580 .loc 2 4042 10 view .LVU1062 + 3581 001c C1F38811 ubfx r1, r1, #6, #9 + 3582 .LBE459: + 3583 .LBE458: + 3584 .loc 1 1566 10 discriminator 2 view .LVU1063 + 3585 0020 01FB03F3 mul r3, r1, r3 + 3586 .LBB460: + 3587 .LBI460: +4081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3588 .loc 2 4081 26 is_stmt 1 view .LVU1064 + 3589 .LBB461: +4083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3590 .loc 2 4083 3 view .LVU1065 +4083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3591 .loc 2 4083 21 is_stmt 0 view .LVU1066 + 3592 0024 D2F88400 ldr r0, [r2, #132] + 3593 .LBE461: + 3594 .LBE460: + 3595 .loc 1 1566 10 discriminator 3 view .LVU1067 + 3596 0028 C0F30270 ubfx r0, r0, #28, #3 +1567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR()); +1568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3597 .loc 1 1568 1 view .LVU1068 + 3598 002c B3FBF0F0 udiv r0, r3, r0 + 3599 0030 7047 bx lr + 3600 .LVL303: + 3601 .L266: +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + ARM GAS /tmp/cc42qbQx.s page 188 + + + 3602 .loc 1 1563 20 view .LVU1069 + 3603 0032 034B ldr r3, .L267+8 + 3604 .LVL304: +1563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 3605 .loc 1 1563 20 view .LVU1070 + 3606 0034 EAE7 b .L265 + 3607 .L268: + 3608 0036 00BF .align 2 + 3609 .L267: + 3610 0038 00380240 .word 1073887232 + 3611 003c 40787D01 .word 25000000 + 3612 0040 0024F400 .word 16000000 + 3613 .cfi_endproc + 3614 .LFE322: + 3616 .section .text.LL_RCC_GetI2SClockFreq,"ax",%progbits + 3617 .align 1 + 3618 .global LL_RCC_GetI2SClockFreq + 3619 .syntax unified + 3620 .thumb + 3621 .thumb_func + 3623 LL_RCC_GetI2SClockFreq: + 3624 .LVL305: + 3625 .LFB300: + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 3626 .loc 1 679 1 is_stmt 1 view -0 + 3627 .cfi_startproc + 3628 @ args = 0, pretend = 0, frame = 0 + 3629 @ frame_needed = 0, uses_anonymous_args = 0 + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 3630 .loc 1 680 3 view .LVU1072 + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 3631 .loc 1 683 3 view .LVU1073 + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3632 .loc 1 685 3 view .LVU1074 + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3633 .loc 1 685 6 is_stmt 0 view .LVU1075 + 3634 0000 B0F5000F cmp r0, #8388608 + 3635 0004 01D0 beq .L277 + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 3636 .loc 1 680 12 view .LVU1076 + 3637 0006 0020 movs r0, #0 + 3638 .LVL306: + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 3639 .loc 1 705 1 view .LVU1077 + 3640 0008 7047 bx lr + 3641 .LVL307: + 3642 .L277: + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 3643 .loc 1 679 1 view .LVU1078 + 3644 000a 08B5 push {r3, lr} + 3645 .LCFI16: + 3646 .cfi_def_cfa_offset 8 + 3647 .cfi_offset 3, -8 + 3648 .cfi_offset 14, -4 + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3649 .loc 1 688 5 is_stmt 1 view .LVU1079 + 3650 .LVL308: + ARM GAS /tmp/cc42qbQx.s page 189 + + + 3651 .LBB462: + 3652 .LBI462: +2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3653 .loc 2 2862 26 view .LVU1080 + 3654 .LBB463: +2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3655 .loc 2 2864 3 view .LVU1081 +2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3656 .loc 2 2864 21 is_stmt 0 view .LVU1082 + 3657 000c 074B ldr r3, .L279 + 3658 000e 9B68 ldr r3, [r3, #8] + 3659 .LVL309: +2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3660 .loc 2 2864 21 view .LVU1083 + 3661 .LBE463: + 3662 .LBE462: + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3663 .loc 1 688 5 discriminator 1 view .LVU1084 + 3664 0010 1842 tst r0, r3 + 3665 0012 08D1 bne .L272 + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3666 .loc 1 691 9 is_stmt 1 view .LVU1085 + 3667 .LBB464: + 3668 .LBI464: +3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 3669 .loc 2 3711 26 view .LVU1086 + 3670 .LBB465: +3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3671 .loc 2 3713 3 view .LVU1087 +3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3672 .loc 2 3713 11 is_stmt 0 view .LVU1088 + 3673 0014 054B ldr r3, .L279 + 3674 0016 1868 ldr r0, [r3] + 3675 .LVL310: +3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 3676 .loc 2 3713 11 view .LVU1089 + 3677 .LBE465: + 3678 .LBE464: + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** { + 3679 .loc 1 691 12 discriminator 1 view .LVU1090 + 3680 0018 10F00060 ands r0, r0, #134217728 + 3681 001c 00D1 bne .L278 + 3682 .LVL311: + 3683 .L269: + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** + 3684 .loc 1 705 1 view .LVU1091 + 3685 001e 08BD pop {r3, pc} + 3686 .LVL312: + 3687 .L278: + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3688 .loc 1 693 11 is_stmt 1 view .LVU1092 + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3689 .loc 1 693 27 is_stmt 0 view .LVU1093 + 3690 0020 FFF7FEFF bl RCC_PLLI2S_GetFreqDomain_I2S + 3691 .LVL313: + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3692 .loc 1 693 27 view .LVU1094 + ARM GAS /tmp/cc42qbQx.s page 190 + + + 3693 0024 FBE7 b .L269 + 3694 .LVL314: + 3695 .L272: + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** break; + 3696 .loc 1 699 23 view .LVU1095 + 3697 0026 0248 ldr r0, .L279+4 + 3698 .LVL315: + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3699 .loc 1 704 3 is_stmt 1 view .LVU1096 + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c **** } + 3700 .loc 1 704 10 is_stmt 0 view .LVU1097 + 3701 0028 F9E7 b .L269 + 3702 .L280: + 3703 002a 00BF .align 2 + 3704 .L279: + 3705 002c 00380240 .word 1073887232 + 3706 0030 0080BB00 .word 12288000 + 3707 .cfi_endproc + 3708 .LFE300: + 3710 .section .rodata.aRCC_PLLSAIDIVRPrescTable,"a" + 3711 .align 2 + 3714 aRCC_PLLSAIDIVRPrescTable: + 3715 0000 02040810 .ascii "\002\004\010\020" + 3716 .text + 3717 .Letext0: + 3718 .file 3 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 3719 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h" + 3720 .file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 3721 .file 6 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + ARM GAS /tmp/cc42qbQx.s page 191 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_ll_rcc.c + /tmp/cc42qbQx.s:20 .text.LL_RCC_DeInit:00000000 $t + /tmp/cc42qbQx.s:26 .text.LL_RCC_DeInit:00000000 LL_RCC_DeInit + /tmp/cc42qbQx.s:184 .text.LL_RCC_DeInit:0000008c $d + /tmp/cc42qbQx.s:191 .text.LL_RCC_GetCECClockFreq:00000000 $t + /tmp/cc42qbQx.s:197 .text.LL_RCC_GetCECClockFreq:00000000 LL_RCC_GetCECClockFreq + /tmp/cc42qbQx.s:275 .text.LL_RCC_GetCECClockFreq:0000002c $d + /tmp/cc42qbQx.s:280 .text.RCC_GetHCLKClockFreq:00000000 $t + /tmp/cc42qbQx.s:286 .text.RCC_GetHCLKClockFreq:00000000 RCC_GetHCLKClockFreq + /tmp/cc42qbQx.s:317 .text.RCC_GetHCLKClockFreq:00000010 $d + /tmp/cc42qbQx.s:323 .text.RCC_GetPCLK1ClockFreq:00000000 $t + /tmp/cc42qbQx.s:329 .text.RCC_GetPCLK1ClockFreq:00000000 RCC_GetPCLK1ClockFreq + /tmp/cc42qbQx.s:360 .text.RCC_GetPCLK1ClockFreq:00000010 $d + /tmp/cc42qbQx.s:366 .text.RCC_GetPCLK2ClockFreq:00000000 $t + /tmp/cc42qbQx.s:372 .text.RCC_GetPCLK2ClockFreq:00000000 RCC_GetPCLK2ClockFreq + /tmp/cc42qbQx.s:403 .text.RCC_GetPCLK2ClockFreq:00000010 $d + /tmp/cc42qbQx.s:409 .text.RCC_PLL_GetFreqDomain_SYS:00000000 $t + /tmp/cc42qbQx.s:415 .text.RCC_PLL_GetFreqDomain_SYS:00000000 RCC_PLL_GetFreqDomain_SYS + /tmp/cc42qbQx.s:500 .text.RCC_PLL_GetFreqDomain_SYS:00000038 $d + /tmp/cc42qbQx.s:507 .text.RCC_GetSystemClockFreq:00000000 $t + /tmp/cc42qbQx.s:513 .text.RCC_GetSystemClockFreq:00000000 RCC_GetSystemClockFreq + /tmp/cc42qbQx.s:567 .text.RCC_GetSystemClockFreq:00000020 $d + /tmp/cc42qbQx.s:574 .text.LL_RCC_GetSystemClocksFreq:00000000 $t + /tmp/cc42qbQx.s:580 .text.LL_RCC_GetSystemClocksFreq:00000000 LL_RCC_GetSystemClocksFreq + /tmp/cc42qbQx.s:626 .text.LL_RCC_GetUSARTClockFreq:00000000 $t + /tmp/cc42qbQx.s:632 .text.LL_RCC_GetUSARTClockFreq:00000000 LL_RCC_GetUSARTClockFreq + /tmp/cc42qbQx.s:1032 .text.LL_RCC_GetUSARTClockFreq:00000160 $d + /tmp/cc42qbQx.s:1042 .text.LL_RCC_GetUARTClockFreq:00000000 $t + /tmp/cc42qbQx.s:1048 .text.LL_RCC_GetUARTClockFreq:00000000 LL_RCC_GetUARTClockFreq + /tmp/cc42qbQx.s:1448 .text.LL_RCC_GetUARTClockFreq:00000168 $d + /tmp/cc42qbQx.s:1458 .text.LL_RCC_GetI2CClockFreq:00000000 $t + /tmp/cc42qbQx.s:1464 .text.LL_RCC_GetI2CClockFreq:00000000 LL_RCC_GetI2CClockFreq + /tmp/cc42qbQx.s:1764 .text.LL_RCC_GetI2CClockFreq:00000108 $d + /tmp/cc42qbQx.s:1774 .text.LL_RCC_GetLPTIMClockFreq:00000000 $t + /tmp/cc42qbQx.s:1780 .text.LL_RCC_GetLPTIMClockFreq:00000000 LL_RCC_GetLPTIMClockFreq + /tmp/cc42qbQx.s:1912 .text.LL_RCC_GetLPTIMClockFreq:00000064 $d + /tmp/cc42qbQx.s:1918 .text.LL_RCC_GetDFSDMClockFreq:00000000 $t + /tmp/cc42qbQx.s:1924 .text.LL_RCC_GetDFSDMClockFreq:00000000 LL_RCC_GetDFSDMClockFreq + /tmp/cc42qbQx.s:1984 .text.LL_RCC_GetDFSDMClockFreq:00000024 $d + /tmp/cc42qbQx.s:1989 .text.RCC_PLL_GetFreqDomain_48M:00000000 $t + /tmp/cc42qbQx.s:1995 .text.RCC_PLL_GetFreqDomain_48M:00000000 RCC_PLL_GetFreqDomain_48M + /tmp/cc42qbQx.s:2078 .text.RCC_PLL_GetFreqDomain_48M:00000034 $d + /tmp/cc42qbQx.s:2085 .text.RCC_PLLSAI_GetFreqDomain_SAI:00000000 $t + /tmp/cc42qbQx.s:2091 .text.RCC_PLLSAI_GetFreqDomain_SAI:00000000 RCC_PLLSAI_GetFreqDomain_SAI + /tmp/cc42qbQx.s:2185 .text.RCC_PLLSAI_GetFreqDomain_SAI:00000044 $d + /tmp/cc42qbQx.s:2192 .text.RCC_PLLSAI_GetFreqDomain_48M:00000000 $t + /tmp/cc42qbQx.s:2198 .text.RCC_PLLSAI_GetFreqDomain_48M:00000000 RCC_PLLSAI_GetFreqDomain_48M + /tmp/cc42qbQx.s:2283 .text.RCC_PLLSAI_GetFreqDomain_48M:0000003c $d + /tmp/cc42qbQx.s:2290 .text.LL_RCC_GetSDMMCClockFreq:00000000 $t + /tmp/cc42qbQx.s:2296 .text.LL_RCC_GetSDMMCClockFreq:00000000 LL_RCC_GetSDMMCClockFreq + /tmp/cc42qbQx.s:2495 .text.LL_RCC_GetSDMMCClockFreq:00000090 $d + /tmp/cc42qbQx.s:2500 .text.LL_RCC_GetRNGClockFreq:00000000 $t + /tmp/cc42qbQx.s:2506 .text.LL_RCC_GetRNGClockFreq:00000000 LL_RCC_GetRNGClockFreq + /tmp/cc42qbQx.s:2594 .text.LL_RCC_GetRNGClockFreq:00000030 $d + /tmp/cc42qbQx.s:2599 .text.LL_RCC_GetUSBClockFreq:00000000 $t + /tmp/cc42qbQx.s:2605 .text.LL_RCC_GetUSBClockFreq:00000000 LL_RCC_GetUSBClockFreq + ARM GAS /tmp/cc42qbQx.s page 192 + + + /tmp/cc42qbQx.s:2693 .text.LL_RCC_GetUSBClockFreq:00000030 $d + /tmp/cc42qbQx.s:2698 .text.RCC_PLLSAI_GetFreqDomain_LTDC:00000000 $t + /tmp/cc42qbQx.s:2704 .text.RCC_PLLSAI_GetFreqDomain_LTDC:00000000 RCC_PLLSAI_GetFreqDomain_LTDC + /tmp/cc42qbQx.s:2800 .text.RCC_PLLSAI_GetFreqDomain_LTDC:00000048 $d + /tmp/cc42qbQx.s:3714 .rodata.aRCC_PLLSAIDIVRPrescTable:00000000 aRCC_PLLSAIDIVRPrescTable + /tmp/cc42qbQx.s:2808 .text.LL_RCC_GetLTDCClockFreq:00000000 $t + /tmp/cc42qbQx.s:2814 .text.LL_RCC_GetLTDCClockFreq:00000000 LL_RCC_GetLTDCClockFreq + /tmp/cc42qbQx.s:2862 .text.LL_RCC_GetLTDCClockFreq:00000014 $d + /tmp/cc42qbQx.s:2867 .text.RCC_PLLI2S_GetFreqDomain_SAI:00000000 $t + /tmp/cc42qbQx.s:2873 .text.RCC_PLLI2S_GetFreqDomain_SAI:00000000 RCC_PLLI2S_GetFreqDomain_SAI + /tmp/cc42qbQx.s:2968 .text.RCC_PLLI2S_GetFreqDomain_SAI:00000044 $d + /tmp/cc42qbQx.s:2975 .text.LL_RCC_GetSAIClockFreq:00000000 $t + /tmp/cc42qbQx.s:2981 .text.LL_RCC_GetSAIClockFreq:00000000 LL_RCC_GetSAIClockFreq + /tmp/cc42qbQx.s:3286 .text.LL_RCC_GetSAIClockFreq:00000108 $d + /tmp/cc42qbQx.s:3295 .text.LL_RCC_GetDFSDMAudioClockFreq:00000000 $t + /tmp/cc42qbQx.s:3301 .text.LL_RCC_GetDFSDMAudioClockFreq:00000000 LL_RCC_GetDFSDMAudioClockFreq + /tmp/cc42qbQx.s:3360 .text.LL_RCC_GetDFSDMAudioClockFreq:00000020 $d + /tmp/cc42qbQx.s:3365 .text.RCC_PLLI2S_GetFreqDomain_SPDIFRX:00000000 $t + /tmp/cc42qbQx.s:3371 .text.RCC_PLLI2S_GetFreqDomain_SPDIFRX:00000000 RCC_PLLI2S_GetFreqDomain_SPDIFRX + /tmp/cc42qbQx.s:3456 .text.RCC_PLLI2S_GetFreqDomain_SPDIFRX:0000003c $d + /tmp/cc42qbQx.s:3463 .text.LL_RCC_GetSPDIFRXClockFreq:00000000 $t + /tmp/cc42qbQx.s:3469 .text.LL_RCC_GetSPDIFRXClockFreq:00000000 LL_RCC_GetSPDIFRXClockFreq + /tmp/cc42qbQx.s:3517 .text.LL_RCC_GetSPDIFRXClockFreq:00000014 $d + /tmp/cc42qbQx.s:3522 .text.RCC_PLLI2S_GetFreqDomain_I2S:00000000 $t + /tmp/cc42qbQx.s:3528 .text.RCC_PLLI2S_GetFreqDomain_I2S:00000000 RCC_PLLI2S_GetFreqDomain_I2S + /tmp/cc42qbQx.s:3610 .text.RCC_PLLI2S_GetFreqDomain_I2S:00000038 $d + /tmp/cc42qbQx.s:3617 .text.LL_RCC_GetI2SClockFreq:00000000 $t + /tmp/cc42qbQx.s:3623 .text.LL_RCC_GetI2SClockFreq:00000000 LL_RCC_GetI2SClockFreq + /tmp/cc42qbQx.s:3705 .text.LL_RCC_GetI2SClockFreq:0000002c $d + /tmp/cc42qbQx.s:3711 .rodata.aRCC_PLLSAIDIVRPrescTable:00000000 $d + +UNDEFINED SYMBOLS +AHBPrescTable +APBPrescTable diff --git a/build/stm32f7xx_ll_rcc.o b/build/stm32f7xx_ll_rcc.o new file mode 100644 index 0000000000000000000000000000000000000000..5ab837b5349ff3eaa0b4658dd49e7f7089728164 GIT binary patch literal 48784 zcmds=33L=y`u3~3x|5KdBtX~$1dIY9ED9=1AS_`u5>!M-2qX|N5KIEb86BdcgNllZ zj-w9l`-TI!jX1ck!vt{~bsR<=SQ|DW@n^PR6ws($x<@4fGR z?|X0Es_yFUtQa?CylvZ-x7k*K6_G5faf8VT4KXONCRpRG^VavAlwDo2+jg?&bf4V0 zI(v5@62#7$vozn{VVgH*}p39o$8+Zej4-6oOi0n>{}6dXU?qJp1bY9tOc`b zVXbb~0xK`De(3~jSfKde!LL5cEVA;GCvV@srYLtzXj{_c+}h0D0V`?S(g~r-xz$X6 z*IfElmi0}`ar>-dx1KZk`s!!)I@y6q+fRL4I(F05pVuqCe$3!lecI$xs-1mJ&h?L_ zmL^Z0RUOzpDzN^*SG#9bKfQNVR^WiO`xLZem)L_(vDP2hyL;&br}VQH>u>bk%7;6R z=h#V`65)-rJJkvH4K^qB4Q@O5?N0}jHU~<7XbF^l-@>vi$MTt*g5#N+H;2bL=6KVb zIn|VQ%*ouGw8<$*YECUEY+nC$acy~XQNeGUt-Peo$D8;##U-CvCC5#=YD`k|hCNRA z)MopbtH!i7?d@zSRkT`~OH2RTGEQ;a(afm*tA#Ci`&teC8SkyhOITIdcn;zG(ZS&3}-+o*QNJ6pdTJ zax9KTl9g)lkY^QHNt?D5Bs1nK2Jkrh1Rjt3or(Q)pC@JVWD8`s|HVtQ} zhs}kh|7q##tJ&Ao47RGd)zo|?9G~YApJx#tu1HQX+w5j)X11#Nkg54VOP1QaySZ)Y zoh|9Unwh3%ajTkZP0cG>9MxRi?37-t_}H4CLCnuggr^wsTEC}wg^gG&oshIiXU6X0 z`VD)m6=@im;uURiY+BKNTl(agX7%iVQT@I+XGgN^XEe7dP1}*EF;6mM9@^oLU(#l8 zO-tI8gdVIe$}L_G`w3A|PTI^m2h5t5sa zfU~!(ddpsC&V~cKxo%G08MAI?s{SjFWt65(D#r>s%HbOO+Wu8V&+J{5?O^qF)6Trt z_OH%+dT+32;D9sOTZcc2v6n7;_db?Zn&Ml_x8sWBt>#F>cJzAwNsJxL#XU{4+c)>{ zjUys4d+0WIPGs-4Y7gJm$wby#T4>_acSrlE(oM75ZEI^ZES-pP;g!r<+QF3e#>Fbj zFmkFHi8edj>z!2=G+Nte-Em3Ulwz#qj!EJb(%7=Ld7}|@HD%wJdVAHM|4p5?is8GD zWtOJ@?3e`V-7&GpBuu>cRE*1BcU*#{ANbKd&;&##3FlNQ$}WUKgM^TRrFSK-_kcwVtdPBiuhJj>y?&XMh;ldH|JyR$n&+? z18oj=+sx?NTx{CRb!*Rg(A2&U7VkluThJ!s@3xttHvin5UV1%B{Het~m#wn3rq&fL z32Jk7b0XG`$=@^;{lOepD*jwrz55QXxx7y?=k=K2w&V5{XYx!=+KiON)OY5bKJ+=X z(svGVJbvjM(s<8_9&g@nv47dksgsj^YsPE)S7v&v2GZ7+y@93Py5Ze#d3{;`wUyzm zg}n3PIiWMh*IJ+yJ#z2Un*M49f=QVRx>~s8a0}Y0Z7eHw3X*G*jV9_4NJ^ZG8|gqW zu`meO2|ZCQ5D1-}NM&dvrKC^};EX|ar!cpYM$2&s*hxpTR3PzWRCSI>!eL0q^N|y( zV|Fm{Sm+aip@mBttVF7A#-3D!gKZ_w1|IU{3@gaIHZ8CbJhlV%wrz^M?iES2g3q!@ zXLuVN-hq1CPF@@OBG4uQ_c$pf)2+~#fwsSgKG4fboeo`Swb>wJw9k`sQrDm>p|3qTH}#1G$lnConx6LRk~)?0w_bi;>Klky zXul`tr#{d8?*eVFF#Z*!wx_-Cz5JroAlpCS$wN}#3_d&5(IpnpGk z`NgU4VEJ1lQGYOgf)4(8jA;!~FTA?*h|c}D6NY~S(ZnW=fSA9U2eQ*rkQ zIppQfN&SKTCwOvY>W^$M(QB_dH4&2~l;q_vO(`iyyxVwkLuw-ZN%qP&rna#C6gS`L z)nuoh$p%tA#Y#K%A-0g_DOTC3BN*azPqErgJ&t3X;VIVGR@zh=Y3n#G@IF1!t^^Y9 zwhJ*gG8XY<$k>E1;2z{p&?MaFWCMYu;6>=WnS94XHuKf7f}@en9L-auus!u5?3UFw zGcdW$14w4AM~4DaQ{DMsWhJ8Jz%+@$tidoDI8I_x)@q(sWfD^@=L9$tINqs-p=`SZ zW$omIWSh3Qjl~`~$Ffg_&78B~f}NUR>LMa$%efIfhq60s48=YWd%J_3OeXKJaLQn} z+a_eRdj?vLrp-eR6WtP$+uaUrE(CMP^R$0}HlJD^3Z#XH2hmsi(@@02QsmLYpTZt~ z9x@)*BV#dk*Tc_4#>3m7Scg5@L-g9RcZcG6Xvg)C+QwEMLJJRjBcS$6J`c-aogO}n z0e55git8a4lC9WX4_|RT3?aw|p^W2Ub6gL1gyO}J+G|>QNbN#s`=J4I7y{bR!tXzF zKHlx~dnWSe_Y#b?>-W8`-$%m50oYx??{)p255*kpar|B%*Y7RxWiot;9(!v0xAL1> z%kQ^Y$)SbcXJeAt7y115W<(~YitG0!uHVc}Q(W ztH?qNzneHY`uqGY){Iz$6UL3~0N3xCaBn(xcSa0w{k{l_^W*zHB(C3M;mdCL5}py= z=m52^LE968IdDaw79MVdBX+va!?DQYoaK#&>tUwr;bU-Q19sQLOxMHDp!f)ToXEC| z>tXM>9#Z?CRvtnN4}0*e3i>=`=jh={@UT6XYUCcy#WNT4I0t*Xm%Bj12FJ8`CK^)- zH1%CDvh;bTZV8+EE@(`Zz|1I``e!RsKLqL3iJXzU;+W#KxIM2Y$St5(OJHUZO?}eJ z)E=1XV6Wo(ztv}oYs=NBVe_UfhqKvk4w@BtGqjs%>s#1j?*csVVrXvTM>`lSM z+$^X%nW?$>J^c)m_!`^OItCs$( zmbmVtrM7f`y04{tsCT2P{UBTF0SVay*-|cQWMa=5z&bPBmgYlo8upGOJNx>?c-gap zDIA7Q$0KJQirj$R>dY(b-!d%g&&cXxmpP@Q^R2EtrKmKD61dR8{+NLq;&ZG3WgdbF zdps`Gu46-j{pi>m&~C%-I(C%nSP*gj0m_bD{f?Po9Ue^S0UMo)kTV>`j^PmG(lJi7 zT#hOyZ!YH+Pubj_%7R;WLbfw~Zt+@m91Pgs(yd8o0NF>-tuvvm#hx>iUT3*(y#U2# z>>Y3RyJg~)8%%kWZf!(P3VPoLyVWio6148^NhTAWgDGZQ%{s&b-LrdPuF_$y-nspd z-~|#V)!m4*z0--DpS(!%RKGe6{%(SRT;p#a)a-^mXB~%smt)S31}JKoa^ zyU$6fhK){FA%`dD1K6#0?eId&M45+l?Dn@#O1sg}@=UUMz?`(~gH8&<`8_A?3qJ1{ z&SzlA9*?^1Q|bH*u6v(D`yuw6EmXebx_2xhHxPTrr{M%_xu=u~=Rcg3MA+!`269$F za}Kp}!ucB9<7pBd&Uc)6;p|`+()VRPhu1=JB~06#zwN(d=$1KVT0Rc#U$EzNqw-AG z;atog3wy^P28$lqJaF#WH#+H$(%}xsxerC|VbP8s!hI7k9`ac37AI>5%YB2Kr%>i^ zEN42_huJ(F!Nl!OmTBcE3OtNqVuh2|4W61-{)w7zgz>1x{NNzDf!_R5Nj@w7;dm!|$26-^t1yf`pl)bG-!56;9UNMkLG`xXRO9 zCJkl^&u9C`Kx7_w!5WFR9_vh71ipqb{xM)CauKxo*mFj6rW_2IiF`j4S7Yzk8{y4@ zU7H6p=!s6+K%7~fh9PGHs*J<#F4BWojt3LNwoaP4CQqT32i`H+9nsZOFuhNtz{4yi zx;R-TEG8N})KHrY3p^FrQ=5mgnaIaL(W?t7@Ngv)M>`oWcwU_fk7k9vx`Wv~+`~kP zyxKy6hi93XEU#Xsz{6H1rpc@KDDbd@iQ)2UCj}mMGjSpYs~8Esgvniw1n*pPH+q`S zq`}bqp6lDozM)}XYvHba1Y+F&3^&`H6SqQpIrf|_C}O|r4$ZVw%i^NmaXf+mx@%o~ zCSDJuy^7)ObTV=-Le?Lc-7WzkEMPVd{g`+w;0AUW1s;Yo@jkR%kH%BrVGkAFGrR3pTJ{e8;@Rqb_4dD^LR!KaXngt^W%asJuOzoKzc&KDzdLXUFt9?0YUK*~wlG!}0V&Y`gzLEkD>zJqx zq}}7yz6~{R3Dk}`r(<{UC$+Y#2vM{8F zV+8Hn?Z|r81jVc9g8evVe*3dHpKiC!EnX3pft|?7>A-X9PTQ zIXLiyuphM3>~!CRT5h};-4rwv7c^J#Y!?t^RnDOOdI<=eaG-I=d0uKy_{i>aI zf@gCP>{W+tUde18u3=)kY~DnHhufHVM>fO5`ZBej+G%%tHdnyjIboY0F`Ea*(%vnb zUs2$JVYI)M%}fT82VM~Dq(H`xp3SwecV*b-QOxGy7$!0T8Sc_RVLT3#m}rlw!Wm+w z3ReV^n2&^+GmDTgwu~91agXyD8%kgmEp|hp_qxj8iMFGVGxFZHmg~L2cAOqXgjURvpEil zlCaIy%;tgdvrA?3Ito0jW8yg3WI$~mo@L@RJMDGP<}4&;hHbvjY#tbIyGk~9Qs9B7 zo?RoG8~}t7F=OH!JEH)BFnzCuy~Sahh0Nw*5ECnHcdCq}z{40OF0p;9%4ujNJZH@C zan6|64i|e_KeKea=asQw+1LppVeBL!VeIttvSxURnO+%A9!@8#n+YR67Q`uMS$Wvc zL#OOxJEF^N0!Z2RPzrZIdkgm5Bor|XrXyh*!~}BZCdSpYY;_Ov{oFkJ0F2tVq?vb% zk!M|t{aKpl{b^=fUKMY1-%h{c>>g#f?4m*U#dInX_MJ`--uf`@@PI|lvhQirGat%+ zO!F{|iN~ES@UhciWPAntyRln6_&SKWK^{0S?agg^@P+gkqys#Rr}C*bJ$N%eg-RaE zsC=%C)$8dXG`U%w%$vwgulpz_g~hGtVc=hFz1)2i{~i|qL-DU+@pg*0hQ+>El>_CO zUfrt^(?I{Q_zI#Hu)|_%GQ>R@Ug7tdyCW<r$c9#=dxh(1xoucXVd00)g)jjV$mE59S95nch_*SG~n zq?EV?I@5lkSAZ`Td%urm3##F60p1S=x_brq>bLjJG}_%O@DVL!dIk7;uJ;7?A=4|c zmE8|`1^BwC_a%&Gz$jxqBZ^CqMQI)Y0B+ zUIE^Y_Wlzm%4^B$#a~(cajyXHrh0!(w;uN_?4^Z!yaK#7_wK?v_jnf8anvsM3UKx8 zeIebtIC+E{s0zAV?G@nLZoN-oooY4FYcq@Iw(-XO28wOM;@kB1`y?-SCd0lVEIx^4 zBCsYb^6j|5B2Vn|K20ShwYMFfslB_iFG)$q8ozqYVLx{z%J5+gEc;F(%Jv%1xgB($}s+nF5Md@ChoB$PP&+gnchF)7EU9Gx-|m#SbNiwGTQkf3sC zEYY?nX4}Y0>Vd2Q=t!F(zM7*_ho|DLhHN_}1;#>0r?6;Bn&l+9;>7G>@IMs_Himpx zk*3y-0`E`+?U5-d$a5W{jf?_R>4N4m{mlhntgRY@=PZ~d+omIIEW6MimFhKjSn9;= zwsw|XoczZzsVtr&bEf4$!Xsl47Q8wcm_6NobW941&P+KubP^hFj|Y`ur&Y2;T-yn< zoqN%Fw$;`ih-Nx=1!7FH`A#7;C1agY9K$rwgtyDZs2fPWg71uW^)hfViEhwz#cQs6 z21b*kmKQFBAcTAD73&e(yA<}WXRL$J(!pMZ;a<~H9*X7{+Fl@B70dPZN5``I_{-!O zONaR_(T=$kaUpZBKLM-gM$8@eUdSpRgydN4R0C$il-7px$>fl%lxWpk#bfe2-NnEk~mZhj4Q?$@2qCTvaoZWlB@|M zIEJ_XSK7{pNAdbiN8M$hj9_H_<4+lP)9e*NEBBS+>2^SR-g#cBkL{E~OLn=;;!bO}|7o>G%E<8#FIPR$@Iy!nTg zmw{gqUN+_T&}$mav1MBEXG1ib7hX3aj3xuj*>;HT@JwJ4l15u~Cr+?Y%xu2ZfGzp` zq3oLtT(A7uraBG`jJI(X&=Xd5=U~x|WFPE7D>W?NEB_z1;Bq!b3%zWqs=+S9gC{Df^a>3uCe=Ux^*vBG{0>HdJOi#Gn`_**FJ< zEfp(Gs;|UysY!+%tq~igCLeay#Ai~IJ6$!gUuyDu?A`^GX*WQT)6zCqJM|m+X0y#> zEA`e>lBw9adXqJ7n#<15Zd#X!WV1(ZMJV^fj$RVOVzMa@ce9D{G1-(Sx!J^tG1-() zcC!h(8*jikd$5^tn}Gxeh-7uFW>(XUOwCme$vtXvr$W&_S_vsCSVJKH+`RmSAmzH& zi9Xo<{h(anW)p14pAFG$>ZT-)H#?dKa_MH8q%m~Ovq`mQl#>XbyY`)??6%G)q{16p z;v6CKe&KZVD)E|!b_u%X?*Qc^+-zcIOg3fTO2#?suT6O!b{HpKjmf6`wwq1RU4Lz; z%yy`g+RJyz4zmZ08oeH)G&vSKd>~4tCVkWQY^llLV@GM?JgLc*u9|pQYVuK6O*|nr z`J}5Rc1ulu<*JEqq$c;fYJ%@mvkxRA;w>M@GMjD2NMjOF&P1{jI~KJ-!KOUI%_fSm`?D!?_%w>V6#26$Pj|D4(_*qI zSGd_kO-wfB%iU~(QS%$8e2tq;+=ShqP5CzLaE(}x-JeZ)gPTooLin>O|HsWHK8nev z{E3@Qd=-;Tnezv269GHgIAwm$7}*3L>G|8HJlM@9_$1Gt9e%QBmGJ=|AL;qC!;ko^ zGCt|!vlD+dWxmUbwuz>gY(D(Mh!F?`ig1kG`GPwhrz|JQvk5+e^+%0z zUw0-DeDdng4nK*t%J@K*k6``T;YYGo*%)M%#bi@1#}3a4PAPwFxMMb`f5pbh$yvj5 zf-~h9rAbZ=G(yamn&hBDOiFj!fc*o;Gib>e3)vI z0fU;DCN;@OxTiK#rz(eJP*4HZ&1RdkA|L4}CA-iNtE8vT#wzJh`)Hde0{^({cF#>G zQSaaI43Di6c_zsl?C|Ed;70SDB=TD9wCruRd95(aXp6)5q5F)?GC>~9#+uxUT$r9S znHwXImE2Fv6B#;gO=6x{WLDd6A(GnfnZf%G(f+=0=;ZjY^7xV);aen9z*se=cNAKKVByL9xF z*{*g#dEGqgXA4YRGS3>YtiEnQ&BD0@7R;MBprUSZ|0T6cs`^(|%w0HO;NZeRg#!mH zTr#g_S!Gq&RLRuxiRA;vRxMvRuL=!E+8zLVrleKhuz2vG`E;kIW_I1Yd4==nZ7Xdx zPo4UPN_=s&u$tdrt3Rv0p=$B$a6xD>r6nE(dr=BcU zj&x4YcD9}|GZf4Yb+ZCNyDhRhInSD`P)dRwv|YXP_!)&EC!u&$C@sMbrQ{*qYwAE_ zXR9fkFh6J~I2+EeV@$2>z*eG6eO6r<3MPyW^@ue1WM^L~qj$Dcwkma5_g1BL&vD%v zHE`4kHnk!J%YCsDo3V7YIdpva1bi83Px& z?ZA(4Ghd%s7_ukF*7+_{=hD`7_Qb8TGCADN6|L)h5x34|tdrfrIJY~~^bXF2k_*{E zC&5`$Ylm_YdNG;e#$ab#uT)+rIS(%c8Otk|6w*Y3^I0Z_B`0KTxS0WGZLKo*hcnfC z$GNaJFJw;%!j~TzMjDVT3otzzR++EM;m}zufVTWl|^`E+-}oz%1y5Z@boG zl9~c%6(%^@@G`*;Bu0(Mx%i$pyH^zI3FfgdXH&0VD-I9YJ@TR~UMGt^+U0~2U^6Mf z=~~Fi?@Qt9!rg~Mw(+&zTUKDyogb~d5VV)9a6|iSmKWMk@+1yG$aLfJ#dfGo!d0Qp zsM#iAKrb^`&!m~MXn_S&O~Jp`*`dxOQD(3y@@V*Ejud$wlim~=LvyC%I0Oo5I27t* z>fIUNjkn^taYr0C-i~(T`Z#WU_$%DFIKCVEj2kycN8_S6ZhRf>#!qpIGuce~@x;rKIdxS4y=GY+#hcE-IM+c|f}-HOg}#&z<~xJRQp z=gzq2(Ya2M8FznF=iDOO&^c3N49)qvvXga}- zE|D4cdXyV(k$d0lybKTY%#)A5^m;(yT0L37pS=^F0MLAM!P+cMqW+#TDDJ0speGbtu$ z(Q7$|jzQz~BD^$x>~F@M1lKMrf;P^4w%dG@W}P*+NEaoFstWd;UGq?LC;}+nrqN#Q)Erpvq+I$%c8Di7sRphoogjB zh1+1!jE)0W7(1au%UJ?-eoxLc)Q74kLB*n zgfienEzbA*ZmYJrgBNvM^&mzr`nKxtzLOqtFqe*pyt}Gb!Z%LdEmy$V;N4Yy70!h3 zymfV))x4`JGIv#ZfutzUKJ$6DHjZaITY0u7j%T|(&u+<$-0!(=2b}j7=zj0t_qhRgSA@2v-fK$=LzxL9d4F2SRc@wx0=9%rL@lO&L@RC7%2(kcY$Ywh zxm>Nh>Te~}wDK3Ul7Uuwu$8m~_ipg{j^^}my>ZJuih&B3OH3#*%QMf6bf=x`*d6{# zZWrE0rEnLLP>DAeNj#l8m{)JnC(sLtUR>Ri)P2p$*AgvaE)a}5dDg@%9sAuIjVP}!#EpjM z)x&YTdJ!j>d0839tMzfb+WL!L-R(O&-iUK{+}rBxh+2}g*xc`(93OV@&dkWkaecK; z=}TLm9DBSI=k3_MpmPULoND*wT}o6auW92Au=~pR;qco991!M^hDUW-{{K8&-*T<@+iT&cLE@h-8N{(HP!OmcHf_THEMNqPwl^Ob#&7C z3e3S&H)nWI1@WPDkF`W|L)T8qKn~v9*gU z7A~1RWY|=HTjs58(^$RnsbpM<=TXhlhJ}k~&qvi|RZHfb<<*kOX`T%8OuMFiDM_8INev{gmM&Yv}$UX zEXXs5WlQQ8E?81kna5vyTv}7JaLLkT4RqaW8eUGBG1eE>$e4s1jUEX&i_v2A!d;E1 z{9RJ1Vq8e27S$-)MU-Ec$f^O%mx=Xuo?byiJ793nF(&h#HwS65qC-cZr7tlqN$%a~>H20JF` zk%Imypt{GmHaFcWMd*EzA6+_TAlC$RcCmlJqh@gHIn55uIBRLu*sA$feRXYJLtaz` zIN+VO?j$vFS~$qx0$LtyhK_};c~$pKs4(t1YS7JThThMhCpno>4nVx0BVs3Z0d zIW^dnHE#O!l-Zy>Sknaqid1IB5K4np4z)0M4!JHLk4Xs7HqFs zoTg^*6i?2oh`oh_>U}XYr~EIS2=K?!y6wf+o!e&SOdnT1Zu*Ji#uiy#YG61uD4ZG` zH5OxxKVG{saAdgfQP%RB*^4XcPxn=dSqD@%JhRQh=w2ngN{md*DTzRtGXCb>QzUvJ zGpmNb5U+I{LS3cHPcDx>RqK~lE}UQ2=!+}|Ju)DJqOa`{C(LZrJk!;IDqVpU^>AQ@ zSj*t(;6bw+%rZUDw^$s~2CRA!;R+lR5lx@53zsjf^cMBX+GW0LElS8SbE0z|hi8{+ z`#nB6+!})It?6DMv0Zq7ko;LR#W!;I2|X(!~B3>=#0KD^HxR5WPtz@nm~^ZGBI zw{+Qvd05Y?8v8FE3b~yu1XLB;*Zt7rbTl6?F~1IWuM~ejHlXB4M9y zomf$`tjer`5v@PwI6pZrhGAOp7ErCpknywLyC9UGP*O6k+&@O%YNJ{hvPNq_b?xG+ z0rRUWD+WxRSTT&(DDwk^j1Ni14=H74v$%GBH`iX$D7Ud6$^cF)E&_v zFP3Pe{H*$tn$x2r12xWT|7orj6NT|9j>rJxF0nrL*4wLTPT;yF3w+I66G}>s$txIm z_6!6*a_`^x!@o+yor2vI=&E}!%u){yA~Xso)j3H?w0fP{FqRxCxHBT z(f>r|$B_K(@MBYG=lsBBc9cHP)vt`z^J7)<%JXAZ@$~%IRXjaEhBZD;y9GXf{QWA1 z-Y@fGSALlvxAOOEE#!FZ4*3;&zulQJb{TKauD=}p@wd;9gL&or`us!GkM;jh?Zl2B z`{TuNG=ELIf}eb{?8A@@4IS5is+EwIIJHe6IVmfcW4E(AIJtI5{3=lwyPMq;KE`f- zRnXeQPlbjzyhRaCGvR&(Goo_%2`Jx&A0v;72|wP)-;7xuE)xu=m~ikz@cvk#2c~?# za4Gy^hi`N6wT9^O38s8zxJ*Jg#e{>eutk?oiYcEIQ$9JSJbuC!B_j5dW6Gz-lutF~ zhlNY|XAJ#`KIbjSw4WC)kKc>)ZH|=@V;?_0=Gz>rZA^Y!V{cA)*zl8mzRj_+W6Ecn z^3~z;_*Dnr=2-1w%C|G+`H5F|!!LaKHhknSrhErezA{{fy^U;+)iI`gM^m2XjJtL8 z5{8b|Ii`GPQ=aF9yWzKJe4B$$#z&8T7gL_+l)H8D5{8b|HKu%5Q=XqBcDJrx!qCB& zYNG9TGv(KWOLYsUnBYHJiY}jL$`^%8<%LsBIQTwvborh!<$K1I&yOjeZ_0D6akqT) zeF&y`Cfe3uSFNLi?~+Bg*T>Y4==deG$mZZfwUIpP3rzV)d(9WL@&irz$oj?wJhC|$kLWWbc6^3J3M1v1Z{0>zj`s`q_XR|PB`z5>nV1CAV_c*`7%CEEz{T8fl+4UA@m6?m!Sdn;E( zV%{IZ>&N(Id~X!##c|9Ve0UY_y|EN~#~*Rhm*c+e9m$G)PbvJ?efVu+^Wq> zqmI0B6q6DEZGxCy@LhWKkFSXEqJ~zyHxTgB@Q|4?@9&4-Add0Edl4U_j(Q1v$TrM7 zWswL(zp<`bao+cU+mTA%E7TYVOmt%289uZ{_ql`LYV4DUL)P`ZgJNE;`ku>}^*m7R z-unj@MVN*2CmD+dudB(6`PC-u3*39h2?m zVdrh>e-OENupK-jGxZBd*ylHkNd8JC^JkK%&o4+(Z`uV-yU6D^q?o^2`Rm1vB=R3s zKEL_I`dn8@d??W5^P5JjUnIS05BaAme~$8xQhnnG?2eROu0OQ5RBRxT->CfGOMj@i z82?cJBbEC^^>?cNSJIy-n)t)Mi39x3ls<=qK9|IJbd$b_gj1$G$m>}0a`$^!^n0b` zi&fs#N4Wy&W92gF1GqS*Gyk{xej_f1b(ELs3&D^-mTdgP_o_Nk22H&cxNcECmtXjX zy;I%S$bky{L>^_3cjzSVqyw|@qiy6I{l*jYyu)BV$AcU#@_Iq}IB|xE&=@`Y&-{9k z^Oo`>;ya>kyZW}`KykEqyjUTgA)YHJ%LBt9i>6aORb5p7(@0u_jZ*h3sBjuwv> zE5tLzbH$s*hs3AF?IQm{4BPoyOyn;)LhdORi2Pq2)Q=EP5-Ul}gF4CQifhCh#RtVF z#Fxl&%lfC#T|P=*6?8Uq!;t)#4S>|5@_Q;yonlKPYYxw}|`?E6jgMd{cZ^{I|GM+#`N1 z;uh8TnMRJqd=a}ze*_6X3&p|GkCI#>P9ag>{EjJjg5A{C9w~n?=IU?qng(53xx4;UxSl7RO0{yyO$a(@4~xCoT~A|6Qm* zOFT!sSiD@kO1w$DUA$X-Sp2K_H}Pc>{=Y@yW%Ik@C(`dD;s1W|N9o%nx%xD*J&F3A z#qMH1k^cmS`A3Rl#0lbLai;hiu|ljN;pbUo4(5e;vGmuF@bfzHM(O!)F{yu0e3V4} z&Eiv{`SD`tw@ZFY{7C#%{6hR*JSaMCT)XKc{OnBPV%uHpC;c!I{tOq#DSwhUO+1-| zo%v)sevCpqQ~L8s*!hFFM)_BZe-dvaVdo(-1^-D)d|LXgB<#E%~Ut zS4v(bUO}S%HR5&Rt>ObD+WRXx8vmR}e1=4Oe^>rLCI3tOK>A&hzY-6Suwx;%WKc{K zb4j$hl~A5v^P}wC6f97ZK$6jz4?7;$ovm8)K`(Pvq)Sbu2BB@;ziQ06CWbs z$CG3M{%?o)JPEta%70Jt4)MRz?~(kq_!9{`PO8g9F_(nBE@DsV`-(%v5n?F`zfK@= zvw5=k8xnRFD8F9vnc~^fuadl4yqbia>%?{9gUa6^ZkGOO@p*B(__p|-_+N3C_#Fwq z6VgDe0m)(q68c^w{69?WC;c$V!^LqV>Q54MxiXV}%^QriS_>=OvM$v96iE?elc4ANQFtM*VL>wWO zlAI6Z5X=YhHzenS^6Mp^DV{C;D#@$Gt4Y|oPFyEGsQeA$X6c_6pBLX!{=4FTrT1%Dcs{rMK~dl=_gEPQp&M*g-5%en0Uj>5mmh ziBrVm#S_H2;sWt>u~9rnJXgF-yh{9|c$;{)c)$20iGDmSzAF7T@eT06+$ruBe-s0FLyYzl#0-)DU6cAAVm}i7I-10rGb6;& zB>FX3`6o#}MVupjjpU``StRWIUOZ2{O8I{jZei9 z@;{aQh4_{9KS>T`yX8|z*vS-g#NNt3TpTR@FmbrZANgnfY2tKo9tnRIh-XN@T>P#0 z2XVEyM!cCs{oBO{rQaw%Dn2K^EN&J5O``sX;uq3?C4M6w6q9i8&3?2MJBhu-e&Uhh zNO6M5AKzvDlf}8>>0*O;j(DMX1&Q%oM|Q{m*b(m_;s1K&KOuRG_?-0HB)=iPPr}ZJ zVvD$6`9FvWcms~*Qp60gi`YZ#Ee;ZgipPpmNcdSM&XRt%I8R(EE)&lZFBC5kFBfkj zVfQxi0qHl0kBHBTFNuE_-x2>UekkrEVRye6Xz#`$QA`o}e|;IBu3``I2yw7DTpTA( z6HgN7hzrF!@ps}%@lx>`k-vz|_U{rO5}zP3UtS`+;PryIjYPlRRep=)&&A!+{~(zU zbXmR)2|MXxme@=AhlvBFKT14CoFGmS%f#P^bH(}MnIzi%op^!t7mJsP*NZoaw}}sl z4~vhBuaL0&5AmPUzb}3uektw~_lqIC5zaUyi|Jx_5_Wru{iPoy9wnBDrQ#Iv1o1R+ zfw)vWOFU1!L|iNWS-eAhP<&K;N_<(|F1{zWkeDyK$xfEFPux$UUje)U&-`=}a+cVE zMEN}NaB+}WLZaSrWC*{YC!R#YPKELtq(4hMN4!Y9OuSNDC*CUFDLz8N?q9{{q<>l5 zD!wEBTl`S`Qrsu*7j5*B{m2x%i-qC{af*0~xJW!pTqXWdyhGe1J}Yh)KM?nb_z02l zBSY*a4ira;)5SSry?Cy;R=h>rBt9d)DSjk=D~2%l83+E4XtIxZv^YVWC02{S6E6~P z5bqH;i?4|9h@Xo4#l)^|yY0o^;t+9+c)WP3h_^+}a{;^!Vu;%tLo9QKC}!A094a0w zmWa4DHsxlBGsSvxD*jowxI#Q%yjZ+UyiL4ITrX}E|0@1Xe4WJm=x>WV#E-i1!#n6dko+xKXjunDC*aD7V!D_m7Kr`CA>uG`lvpCp zB>Uq1EwNIp7Hh?N@gnh3@oMo;;!Wah;$tN4xy(Oh1D})plGrT1E`BEN62B4okI-qy z=5sO-KRRNVOSZ-PU1BfsFtLQhdjk{1Y2tKo35oa8%yT~QEXn7HSChC#{z<%9yj|QZ zJ|&vxe<*LB|ADVd|F*b8{7BqSmf?L}F&K1Z^BfTRE|T*^^V|>mzLF=3Q^ga+lf??L zN^BrUku474H%`@vd5#CW<~bgCk@S~}>%?2che*7yx=GwDJ|(^( z{!`o`ek7Xbb*P`j=T)Hj-+o|@Wb=O@A)DuR;9=7D6^Dz(qIpht4DK%|gQtkI#WTg< ziRXzIir0wdc^&HCEctfv1@RSeyJ()vq5Quke<*$??h?NdzZX*yT|YC#K4cR9?SME? zJW@2zMU%ZkWg6AvZI`J0q zaq&sG|$r};QUQSc`#GV5zX^6 z=!Zx?RvaZBCzgw|#M8tjqWMp%uydB=bHw|_hs4Lk&Ej+7OJcM5y7->BLu?U07tQ}) zMZ4ch{z>FDko`>-)5UgTN3n-!o~NPwK*>jn=J^@)lO>zyW{~GdHvi_fH$I<48T_4S zo}WR!Rq~zU1L9vq^V|&O%yTpF@6vA*|09~`X2{FGW#Tv0eY!ojNFBNYfPqeI?#Jj}%#23X^Me}?N<=>LrB7QD@C4M8C=VK^u zo{xcT`Md~hCk_>l6-&ek;&EcRI7>WDoG&gCo5YpkRb)@gGS9=n8ztW=z95?CUdVq< z@|)tv;%DL>@oO=}=RT;{M$8m*#C)+p93T!BOT-D{G;zAPMqDf2Al@Y2CEh2R=UMRQ z5y^iOpAlacw~B9y?}+~q&2ui;`9ks@aliP3Xr6PSToRxEfEi-8*jdDXq&4|{#3RH( z;!&b`4hB2sIT$!m`l+IM4hH>9$#cX?@wejd#mmL3MDyGW_3x7Wn7CPdmBjmg&EnhQ zdtyC7vcO5$nXWMDx4~^)Hotg?O!agLt2~UVKFStN4oe z5AjX$9q}`9m-w~#o!ADiW!V2TF-Oc53&einU~#B8L7Xg37f%%Di;G0_oC@tNlYD`A zk!YS%A%Csp+r+!X2gMDdc}|7$<~bF(Rr=S&55$kfFT_2f&F3?y7ZOv&OfgT)7yF6> z#KqznqIvEFd*?{LK)gs?Bd!&15N{Ii6z>(yb12w*M6!7v1^H>oFN<5nH^hI6{}KNy z?i6>6`^6tbhtFqVKT*sOv&BwgH?fa+gg8Vr&#hpmSn^o$1o32Xk+?)$A)YU;6|WWV zB=H{Bz2XM(5iupl&Cd|qi{|+f>K!4uP&Ch%pg&sjL~*J(L!2pAi#1}sc&7LV@e=V$ z@fy)QXF_}TNPbA%B%0?;$bU(4v-rCBk@$)DrMOpg_?!jx6UB5fOYAB35&Me+#nIw8 z(L8U0J@dQ?oFjduc)D0Ct`N@`FBUHo*NL}?cZ>Ino5iQZ7sXe__rx7yi}<;CKs+cW zw0Gl?ES8E>#2MmD(L6swKPx4lF4l@?ispF|%AF_qLh&;3O7TzPpT*n7yT$e5M$tTP zg552WUl3mrw~KFy?~5OZpNYG~uf^{~yMr5#keDH6i=D;pVv#sR94Af`XNjkYwPL+^ z9@z=sXA#ZwCdgMxzC*l6G|!umze)15WXQ5!6r07@#rMP=;#cA~BHkvj0;k}06$v|d z3}asJ=aINaFCcMmQ$*sLFpR{xR7}D~DG7hdNQ{elpBn4h9Ll(_s3viLzm$ZrMzXJE zHIaq-hpPkiU&My!AL9(g{WtTE!F>sd_kq`wcz^3raxBK5#Os(B$w|0BA*bqnYdEum za=H8O-FSb^js3&hU4}^{4!A8h%p}oYbj>iAM8DA`!#ooG&ld|w6z(S$k%$MnU^t9K zT!xFqB#gmz!%`A)nj*qw6R#QKOcHTBRh&bj(MqwJL>z0xr6l6nAU2YS>)B!x3FlUd zt4PFowYY{vyw{4?l8E~a;!Pytf17w0iO$?7t|u`b8^uRSjLQ?^782w0toR~{PQNNP zlNhhp#kWa}+k0Xk8#2Z(HvlH#a|tBI>rE2ll+5>QF+L;79Lxif;}HZg4i}PL@SL6R ziy`jj^TU{*C&LEgJTMh3uq^X=NyK#kU(X<(=5v0C&g6Q7{@zNWpK#d<%+>jae)f}GM54dLB^Q(M zd5UD1GW|bQ@*EPr)JR@R!uZ*en@GfEtz|undomNNA)QFca!58iTajuyaMsQul!4G>08V3 z%(eO@)nBm1Z!yQS1AXL|t_tgFdHxn2`pf*rL}k_7Wea96Tr$5F=etQ)%$-|TwcKsM z)!?^l{bEI3#gYY8SQI!J+!C!d_%YTh&mvY8t8iZJ;>A_?jZt5%`E?bGQE2q^sf85{ z4Rs6WE^C0WR9m3uXG4`zG5&x2X_MV8b$LlKl;B9P|+Yaphe(*ZV z*n68-?mZ~{{Ydh)i(8^_KWxqaWHdH(f;&Tp>>_L@+J_Hf%1wl@*wSe>tLxJ|)?ZHi-$pF8o}Tko@%je2aC<9B+D zy;qTu7suX$7<)x$M*PFAU)bL27<)T$&sT$dZ)3aMI8IUi!5-%y`-|JSu)POk?9D{S z3y|+^p1pfx?7awkc_>7C_y}6q-qsji#~;7@P$<_krg9XYim_Mhv)4!EX#c|)d(T1{Z+!Xs%inGeoaJY~yv^%J z0?PUOQHpl+P>B6F9J|+#zA^UroHrl&-saik=ZgIHs$tI?H@xf!+dD4C-VE3)^^B<; z#oxx1y8-3m#cz2`yN$m1;pI)Z-RooQZG=7c)!V#&JRMVRKgz|MS5L;Y+vIB(FQdZk z{#*7id}iy1*Nk3URCwtS624)wics$Ku5KM3y*wM`{Bd4|cIV)A<5-lTpR~vM!rw>m z>Oi!vFTnZhIRV+rwjdM5&98_d+r;H0 zB)mE_({7w)_22@o&CBEOLip_!-{)StX%8=R!~V^aJ+67&jye_3b})9{Mtj_s#FPtG zyZ2_X<$kAfp1vQ-mHEaE*=9Qv3BP}N_ec6W8YNgR2|Itc0#k6Qsf5GXi!5u9CxBjm xNnbP8dXy`I0ffh@!cKcUpV=ntg|{7bxPR~|JbSzc@TsjG58ypT8qwyJ`#(wNPHO-F literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_ll_sdmmc.d b/build/stm32f7xx_ll_sdmmc.d new file mode 100644 index 0000000..0ea7a7b --- /dev/null +++ b/build/stm32f7xx_ll_sdmmc.d @@ -0,0 +1,68 @@ +build/stm32f7xx_ll_sdmmc.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/build/stm32f7xx_ll_sdmmc.lst b/build/stm32f7xx_ll_sdmmc.lst new file mode 100644 index 0000000..e815942 --- /dev/null +++ b/build/stm32f7xx_ll_sdmmc.lst @@ -0,0 +1,6063 @@ +ARM GAS /tmp/ccPSMkLq.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_ll_sdmmc.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c" + 19 .section .text.SDMMC_GetCmdError,"ax",%progbits + 20 .align 1 + 21 .syntax unified + 22 .thumb + 23 .thumb_func + 25 SDMMC_GetCmdError: + 26 .LVL0: + 27 .LFB186: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @file stm32f7xx_ll_sdmmc.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief SDMMC Low Layer HAL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * This file provides firmware functions to manage the following + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * functionalities of the SDMMC peripheral: + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * + Initialization/de-initialization functions + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * + I/O operation functions + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * + Peripheral Control functions + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * + Peripheral State functions + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ****************************************************************************** + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @attention + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * Copyright (c) 2017 STMicroelectronics. + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * All rights reserved. + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * This software is licensed under terms that can be found in the LICENSE file + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * in the root directory of this software component. + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ****************************************************************************** + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @verbatim + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ============================================================================== + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ##### SDMMC peripheral features ##### + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ============================================================================== + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** devices. + ARM GAS /tmp/ccPSMkLq.s page 2 + + + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** [..] The SDMMC features include the following: + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** for three different databus modes: 1-bit (default), 4-bit and 8-bit + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility) + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (+) Full compliance with SD Memory Card Specifications Version 2.0 + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** different data bus modes: 1-bit (default) and 4-bit + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Rev1.1) + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (+) Data transfer up to 48 MHz for the 8 bit mode + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (+) Data and command output enable signals to control external bidirectional drivers + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ##### How to use this driver ##### + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ============================================================================== + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** [..] + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** This driver is a considered as a driver of service for external devices drivers + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** that interfaces with the SDMMC peripheral. + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** is used in the device's driver to perform SDMMC operations and functionalities. + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** This driver is almost transparent for the final user, it is only used to implement other + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** functionalities of the external device. + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** [..] + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK, + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** PLL is well configured. + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** The SDMMC peripheral uses two clock signals: + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) SDMMC adapter clock (SDMMCCLK = 48 MHz) + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) APB2 bus clock (PCLK2) + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition: + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK)) + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** peripheral. + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (+) Enable the Power ON State using the SDMMC_PowerState_ON() + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** function and disable it using the function SDMMC_PowerState_OFF(). + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros. + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT() + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** and __SDMMC_DISABLE_IT() if you need to use interrupt mode. + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (+) When using the DMA mode + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) Configure the DMA in the MSP layer of the external device + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) Active the needed channel Request + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) Enable the DMA using __SDMMC_DMA_ENABLE() macro or Disable it using the macro + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** __SDMMC_DMA_DISABLE(). + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (+) To control the CPSM (Command Path State Machine) and send + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** commands to the card use the SDMMC_SendCommand(), + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** to the selected command to be sent. + ARM GAS /tmp/ccPSMkLq.s page 3 + + + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** The parameters that should be filled are: + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) Command Argument + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) Command Index + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) Command Response type + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) Command Wait + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) CPSM Status (Enable or Disable). + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** -@@- To check if the command is well received, read the SDMMC_CMDRESP + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** register using the SDMMC_GetCommandResponse(). + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_GetResponse() function. + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (+) To control the DPSM (Data Path State Machine) and send/receive + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(), + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_ReadFIFO(), SDMMC_WriteFIFO() and SDMMC_GetFIFOCount() functions. + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** *** Read Operations *** + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ======================= + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** [..] + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (#) First, user has to fill the data structure (pointer to + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_DataInitTypeDef) according to the selected data type to be received. + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** The parameters that should be filled are: + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) Data TimeOut + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) Data Length + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) Data Block size + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) Data Transfer direction: should be from card (To SDMMC) + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) Data Transfer mode + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) DPSM Status (Enable or Disable) + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (#) Configure the SDMMC resources to receive the data from the card + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** according to selected transfer mode (Refer to Step 8, 9 and 10). + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (#) Send the selected Read command (refer to step 11). + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (#) Use the SDMMC flags/interrupts to check the transfer status. + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** *** Write Operations *** + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ======================== + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** [..] + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (#) First, user has to fill the data structure (pointer to + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_DataInitTypeDef) according to the selected data type to be received. + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** The parameters that should be filled are: + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) Data TimeOut + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) Data Length + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) Data Block size + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) Data Transfer direction: should be to card (To CARD) + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) Data Transfer mode + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (++) DPSM Status (Enable or Disable) + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (#) Configure the SDMMC resources to send the data to the card according to + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** selected transfer mode. + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (#) Send the selected Write command. + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (#) Use the SDMMC flags/interrupts to check the transfer status. + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** *** Command management operations *** + ARM GAS /tmp/ccPSMkLq.s page 4 + + + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ===================================== + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** [..] + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (#) The commands used for Read/Write/Erase operations are managed in + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** separate functions. + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Each function allows to send the needed command with the related argument, + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** then check the response. + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** By the same approach, you could implement a command and check the response. + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @endverbatim + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ****************************************************************************** + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Includes ------------------------------------------------------------------*/ + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** #include "stm32f7xx_hal.h" + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** #if defined(SDMMC1) + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** @addtogroup STM32F7xx_HAL_Driver + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @{ + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** @defgroup SDMMC_LL SDMMC Low Layer + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Low layer module for SD + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @{ + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** #if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED) + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Private typedef -----------------------------------------------------------*/ + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Private define ------------------------------------------------------------*/ + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Private macro -------------------------------------------------------------*/ + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Private variables ---------------------------------------------------------*/ + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Private function prototypes -----------------------------------------------*/ + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx); + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Exported functions --------------------------------------------------------*/ + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @{ + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Initialization and Configuration functions + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @verbatim + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** =============================================================================== + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ##### Initialization/de-initialization functions ##### + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** =============================================================================== + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** [..] This section provides functions allowing to: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @endverbatim + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @{ + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Initializes the SDMMC according to the specified + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * parameters in the SDMMC_InitTypeDef and create the associated handle. + ARM GAS /tmp/ccPSMkLq.s page 5 + + + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param Init: SDMMC initialization structure + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t tmpreg = 0; + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check the parameters */ + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx)); + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass)); + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave)); + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide)); + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv)); + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set SDMMC configuration parameters */ + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** tmpreg |= (Init.ClockEdge |\ + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Init.ClockBypass |\ + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Init.ClockPowerSave |\ + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Init.BusWide |\ + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Init.HardwareFlowControl |\ + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Init.ClockDiv + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ); + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Write to SDMMC CLKCR */ + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return HAL_OK; + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @} + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** @defgroup HAL_SDMMC_LL_Group2 IO operation functions + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Data transfers functions + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @verbatim + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** =============================================================================== + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ##### I/O operation functions ##### + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** =============================================================================== + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** [..] + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** This subsection provides a set of functions allowing to manage the SDMMC data + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** transfers. + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @endverbatim + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @{ + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Read data (word) from Rx FIFO in blocking mode (polling) + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + ARM GAS /tmp/ccPSMkLq.s page 6 + + + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx) + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Read data from Rx FIFO */ + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return (SDMMCx->FIFO); + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Write data (word) to Tx FIFO in blocking mode (polling) + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param pWriteData: pointer to data to write + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData) + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Write data to FIFO */ + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMCx->FIFO = *pWriteData; + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return HAL_OK; + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @} + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief management functions + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @verbatim + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** =============================================================================== + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ##### Peripheral Control functions ##### + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** =============================================================================== + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** [..] + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** This subsection provides a set of functions allowing to control the SDMMC data + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** transfers. + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @endverbatim + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @{ + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Set SDMMC Power state to ON. + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx) + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set power state to ON */ + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMCx->POWER = SDMMC_POWER_PWRCTRL; + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return HAL_OK; + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Set SDMMC Power state to OFF. + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + ARM GAS /tmp/ccPSMkLq.s page 7 + + + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx) + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set power state to OFF */ + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMCx->POWER = (uint32_t)0x00000000; + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return HAL_OK; + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Get SDMMC Power state. + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval Power status of the controller. The returned value can be one of the + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * following values: + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * - 0x00: Power OFF + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * - 0x02: Power UP + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * - 0x03: Power ON + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx) + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL); + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Configure the SDMMC command path according to the specified parameters in + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * SDMMC_CmdInitTypeDef structure and send the command + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * the configuration information for the SDMMC command + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command) + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t tmpreg = 0; + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check the parameters */ + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex)); + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_RESPONSE(Command->Response)); + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt)); + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_CPSM(Command->CPSM)); + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set the SDMMC Argument value */ + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMCx->ARG = Command->Argument; + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set SDMMC command parameters */ + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** tmpreg |= (uint32_t)(Command->CmdIndex |\ + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Command->Response |\ + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Command->WaitForInterrupt |\ + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Command->CPSM); + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Write to SDMMC CMD register */ + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg); + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return HAL_OK; + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Return the command index of last command for which response received + ARM GAS /tmp/ccPSMkLq.s page 8 + + + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval Command index of the last command response received + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx) + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return (uint8_t)(SDMMCx->RESPCMD); + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Return the response received from the card for the last command + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param Response: Specifies the SDMMC response register. + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * This parameter can be one of the following values: + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @arg SDMMC_RESP1: Response Register 1 + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @arg SDMMC_RESP2: Response Register 2 + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @arg SDMMC_RESP3: Response Register 3 + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @arg SDMMC_RESP4: Response Register 4 + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval The Corresponding response register value + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t tmp; + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check the parameters */ + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_RESP(Response)); + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Get the response */ + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** tmp = (uint32_t)(&(SDMMCx->RESP1)) + Response; + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return (*(__IO uint32_t *) tmp); + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Configure the SDMMC data path according to the specified + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * parameters in the SDMMC_DataInitTypeDef. + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param Data : pointer to a SDMMC_DataInitTypeDef structure + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * that contains the configuration information for the SDMMC data. + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data) + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t tmpreg = 0; + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check the parameters */ + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength)); + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize)); + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir)); + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode)); + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_DPSM(Data->DPSM)); + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set the SDMMC Data TimeOut value */ + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMCx->DTIMER = Data->DataTimeOut; + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set the SDMMC DataLength value */ + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMCx->DLEN = Data->DataLength; + ARM GAS /tmp/ccPSMkLq.s page 9 + + + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set the SDMMC data configuration parameters */ + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** tmpreg |= (uint32_t)(Data->DataBlockSize |\ + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Data->TransferDir |\ + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Data->TransferMode |\ + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Data->DPSM); + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Write to SDMMC DCTRL */ + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return HAL_OK; + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Returns number of remaining data bytes to be transferred. + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval Number of remaining data bytes to be transferred + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx) + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return (SDMMCx->DCOUNT); + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Get the FIFO data + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval Data received + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx) + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return (SDMMCx->FIFO); + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Sets one of the two options of inserting read wait interval. + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMC_ReadWaitMode: SDMMC Read Wait operation mode. + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * This parameter can be: + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2 + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval None + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode) + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check the parameters */ + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode)); + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set SDMMC read wait mode */ + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode); + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return HAL_OK; + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @} + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + ARM GAS /tmp/ccPSMkLq.s page 10 + + + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** @defgroup HAL_SDMMC_LL_Group4 Command management functions + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Data transfers functions + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @verbatim + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** =============================================================================== + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ##### Commands management functions ##### + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** =============================================================================== + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** [..] + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** This subsection provides a set of functions allowing to manage the needed commands. + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @endverbatim + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @{ + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Data Block Length command and check the response + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set Block Size for Card */ + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = (uint32_t)BlockSize; + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN; + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT); + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Read Single Block command and check the response + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set Block Size for Card */ + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK; + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + ARM GAS /tmp/ccPSMkLq.s page 11 + + + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Read Multi Block command and check the response + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set Block Size for Card */ + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK; + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT); + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Write Single Block command and check the response + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set Block Size for Card */ + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK; + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Write Multi Block command and check the response + ARM GAS /tmp/ccPSMkLq.s page 12 + + + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set Block Size for Card */ + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK; + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT); + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Start Address Erase command for SD and check the response + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set Block Size for Card */ + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = (uint32_t)StartAdd; + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START; + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_START, SDMMC_CMDTIMEOUT); + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the End Address Erase command for SD and check the response + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set Block Size for Card */ + ARM GAS /tmp/ccPSMkLq.s page 13 + + + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = (uint32_t)EndAdd; + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END; + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_END, SDMMC_CMDTIMEOUT); + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Start Address Erase command and check the response + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set Block Size for Card */ + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = (uint32_t)StartAdd; + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START; + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_START, SDMMC_CMDTIMEOUT); + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the End Address Erase command and check the response + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set Block Size for Card */ + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = (uint32_t)EndAdd; + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END; + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_END, SDMMC_CMDTIMEOUT); + ARM GAS /tmp/ccPSMkLq.s page 14 + + + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Erase command and check the response + 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx) + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set Block Size for Card */ + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = 0U; + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE; + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE, SDMMC_MAXERASETIMEOUT); + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Stop Transfer command and check the response. + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx) + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Send CMD12 STOP_TRANSMISSION */ + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = 0U; + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION; + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT); + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Select Deselect command and check the response. + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param addr: Address of the card to be selected + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + ARM GAS /tmp/ccPSMkLq.s page 15 + + + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr) + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Send CMD7 SDMMC_SEL_DESEL_CARD */ + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = (uint32_t)Addr; + 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD; + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT); + 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Go Idle State command and check the response. + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx) + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = 0U; + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; + 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_NO; + 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdError(SDMMCx); + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Operating Condition command and check the response. + 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx) + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Send CMD8 to verify SD card interface operating condition */ + 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Argument: - [31:12]: Reserved (shall be set to '0') + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) + 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** - [7:0]: Check Pattern (recommended 0xAA) */ + ARM GAS /tmp/ccPSMkLq.s page 16 + + + 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* CMD Response: R7 */ + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN; + 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; + 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp7(SDMMCx); + 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Application command to verify that that the next command + 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * is an application specific com-mand rather than a standard command + 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * and check the response. + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param Argument: Command Argument + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) + 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = (uint32_t)Argument; + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD; + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* If there is a HAL_ERROR, it is a MMC card, else + 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** it is a SD card: SD card 2.0 (voltage range mismatch) + 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** or SD card 1.x */ + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_CMD, SDMMC_CMDTIMEOUT); + 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the command asking the accessed card to send its operating + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * condition register (OCR) + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param Argument: Command Argument + 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | Argument; + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; + ARM GAS /tmp/ccPSMkLq.s page 17 + + + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp3(SDMMCx); + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Bus Width command and check the response. + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param BusWidth: BusWidth + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth) + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = (uint32_t)BusWidth; + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH; + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT); + 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Send SCR command and check the response. + 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx) + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Send CMD51 SD_APP_SEND_SCR */ + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = 0U; + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR; + 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT); + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + ARM GAS /tmp/ccPSMkLq.s page 18 + + + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Send CID command and check the response. + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx) + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Send CMD2 ALL_SEND_CID */ + 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = 0U; + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID; + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; + 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp2(SDMMCx); + 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Send CSD command and check the response. + 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param Argument: Command Argument + 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status + 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Send CMD9 SEND_CSD */ + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = Argument; + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD; + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp2(SDMMCx); + 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** + 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Send CSD command and check the response. + 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base + 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param pRCA: Card RCA + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ + ARM GAS /tmp/ccPSMkLq.s page 19 + + +1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA) +1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; +1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Send CMD3 SD_CMD_SET_REL_ADDR */ +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = 0U; +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; +1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); +1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ +1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA); +1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; +1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** +1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Set Relative Address command to MMC card (not SD card). +1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx Pointer to SDMMC register base +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param RCA Card RCA +1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ +1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA) +1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; +1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Send CMD3 SD_CMD_SET_REL_ADDR */ +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = ((uint32_t)RCA << 16U); +1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; +1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; +1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; +1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); +1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_REL_ADDR, SDMMC_CMDTIMEOUT); +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; +1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** +1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Status command and check the response. +1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base +1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param Argument: Command Argument +1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status +1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ +1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; +1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; +1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = Argument; +1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS; + ARM GAS /tmp/ccPSMkLq.s page 20 + + +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; +1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; +1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); +1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ +1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT); +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; +1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** +1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Status register command and check the response. +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base +1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ +1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx) +1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; +1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = 0U; +1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS; +1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; +1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; +1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; +1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ +1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT); +1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** +1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Sends host capacity support information and activates the card's +1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * initialization process. Send SDMMC_CMD_SEND_OP_COND command +1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base +1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @parame Argument: Argument used for the command +1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status +1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ +1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; +1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; +1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = Argument; +1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND; +1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; +1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); +1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ +1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp3(SDMMCx); +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; + ARM GAS /tmp/ccPSMkLq.s page 21 + + +1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** +1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH command +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx: Pointer to SDMMC register base +1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @parame Argument: Argument used for the command +1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ +1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */ +1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* CMD Response: R1 */ +1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN */ +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH; +1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); +1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ +1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SWITCH, SDMMC_CMDTIMEOUT); +1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** +1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Send the Send EXT_CSD command and check the response. +1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx Pointer to SDMMC register base +1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param Argument Command Argument +1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval HAL status +1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ +1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; +1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; +1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Send CMD9 SEND_CSD */ +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Argument = Argument; +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; +1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; +1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); +1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check for error conditions */ +1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD,SDMMC_CMDTIMEOUT); +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return errorstate; +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** +1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @} +1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ +1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + ARM GAS /tmp/ccPSMkLq.s page 22 + + +1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** @defgroup HAL_SDMMC_LL_Group5 Responses management functions +1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Responses functions +1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * +1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @verbatim +1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** =============================================================================== +1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ##### Responses management functions ##### +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** =============================================================================== +1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** [..] +1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** This subsection provides a set of functions allowing to manage the needed responses. +1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** @endverbatim +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @{ +1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ +1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Checks for error conditions for R1 response. +1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx Pointer to SDMMC register base +1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SD_CMD: The sent command index +1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval SD Card error state +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout) +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t response_r1; +1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t sta_reg; +1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* 8 is the number of required instructions cycles for the below loop statement. +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** The Timeout is expressed in ms */ +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t count = Timeout * (SystemCoreClock / 8U /1000U); +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** do +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** if (count-- == 0U) +1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_TIMEOUT; +1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sta_reg = SDMMCx->STA; +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || +1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); +1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) +1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); +1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_CMD_RSP_TIMEOUT; +1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) +1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); +1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_CMD_CRC_FAIL; +1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else +1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Nothing to do */ +1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Clear all the static flags */ +1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + ARM GAS /tmp/ccPSMkLq.s page 23 + + +1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check response received is of desired command */ +1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_CMD_CRC_FAIL; +1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* We have received response, retrieve it for analysis */ +1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO) +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_NONE; +1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE) +1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_ADDR_OUT_OF_RANGE; +1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED) +1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_ADDR_MISALIGNED; +1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR) +1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_BLOCK_LEN_ERR; +1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR) +1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_ERASE_SEQ_ERR; +1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM) +1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_BAD_ERASE_PARAM; +1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION) +1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_WRITE_PROT_VIOLATION; +1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED) +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_LOCK_UNLOCK_FAILED; +1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED) +1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_COM_CRC_FAILED; +1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD) +1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_ILLEGAL_CMD; +1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED) +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_CARD_ECC_FAILED; +1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR) +1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_CC_ERR; + ARM GAS /tmp/ccPSMkLq.s page 24 + + +1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN) +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_STREAM_READ_UNDERRUN; +1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN) +1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_STREAM_WRITE_OVERRUN; +1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE) +1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_CID_CSD_OVERWRITE; +1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP) +1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_WP_ERASE_SKIP; +1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED) +1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_CARD_ECC_DISABLED; +1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET) +1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_ERASE_RESET; +1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR) +1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_AKE_SEQ_ERR; +1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else +1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; +1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Checks for error conditions for R2 (CID or CSD) response. +1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx Pointer to SDMMC register base +1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval SD Card error state +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ +1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) +1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t sta_reg; +1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* 8 is the number of required instructions cycles for the below loop statement. +1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** The SDMMC_CMDTIMEOUT is expressed in ms */ +1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); +1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** do +1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** if (count-- == 0U) +1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_TIMEOUT; +1338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sta_reg = SDMMCx->STA; +1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || +1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); +1342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + ARM GAS /tmp/ccPSMkLq.s page 25 + + +1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); +1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_CMD_RSP_TIMEOUT; +1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) +1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_CMD_CRC_FAIL; +1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* No error flag set */ +1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Clear all the static flags */ +1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); +1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_NONE; +1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** +1366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Checks for error conditions for R3 (OCR) response. +1367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx Pointer to SDMMC register base +1368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval SD Card error state +1369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ +1370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) +1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t sta_reg; +1373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* 8 is the number of required instructions cycles for the below loop statement. +1374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** The SDMMC_CMDTIMEOUT is expressed in ms */ +1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); +1376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** do +1378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** if (count-- == 0U) +1380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_TIMEOUT; +1382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sta_reg = SDMMCx->STA; +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || +1385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); +1386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) +1388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); +1390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_CMD_RSP_TIMEOUT; +1392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else +1394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Clear all the static flags */ +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); +1397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_NONE; + ARM GAS /tmp/ccPSMkLq.s page 26 + + +1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** +1403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Checks for error conditions for R6 (RCA) response. +1404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx Pointer to SDMMC register base +1405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SD_CMD: The sent command index +1406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param pRCA: Pointer to the variable that will contain the SD card relative +1407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * address RCA +1408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval SD Card error state +1409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ +1410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA) +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t response_r1; +1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t sta_reg; +1414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* 8 is the number of required instructions cycles for the below loop statement. +1416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** The SDMMC_CMDTIMEOUT is expressed in ms */ +1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); +1418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** do +1420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** if (count-- == 0U) +1422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_TIMEOUT; +1424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sta_reg = SDMMCx->STA; +1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || +1427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); +1428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) +1430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); +1432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_CMD_RSP_TIMEOUT; +1434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) +1436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); +1438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_CMD_CRC_FAIL; +1440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else +1442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Nothing to do */ +1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check response received is of desired command */ +1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) +1448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_CMD_CRC_FAIL; +1450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Clear all the static flags */ +1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); +1454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* We have received response, retrieve it. */ +1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); + ARM GAS /tmp/ccPSMkLq.s page 27 + + +1457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILE +1459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** *pRCA = (uint16_t) (response_r1 >> 16); +1461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_NONE; +1463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) +1465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_ILLEGAL_CMD; +1467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) +1469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_COM_CRC_FAILED; +1471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else +1473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; +1475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** +1479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Checks for error conditions for R7 response. +1480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx Pointer to SDMMC register base +1481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval SD Card error state +1482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ +1483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t sta_reg; +1486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* 8 is the number of required instructions cycles for the below loop statement. +1487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** The SDMMC_CMDTIMEOUT is expressed in ms */ +1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); +1489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** do +1491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** if (count-- == 0U) +1493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_TIMEOUT; +1495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sta_reg = SDMMCx->STA; +1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || +1498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); +1499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) +1501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Card is SD V2.0 compliant */ +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); +1504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_CMD_RSP_TIMEOUT; +1506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) +1508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Card is SD V2.0 compliant */ +1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); +1511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_CMD_CRC_FAIL; +1513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + ARM GAS /tmp/ccPSMkLq.s page 28 + + +1514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** else +1515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Nothing to do */ +1517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND)) +1520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Card is SD V2.0 compliant */ +1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND); +1523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_NONE; +1526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** +1530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @} +1531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ +1532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Private function ----------------------------------------------------------*/ +1534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** @addtogroup SD_Private_Functions +1535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @{ +1536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ +1537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /** +1539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @brief Checks for error conditions for CMD0. +1540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @param SDMMCx Pointer to SDMMC register base +1541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** * @retval SD Card error state +1542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** */ +1543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) +1544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 28 .loc 1 1544 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. +1545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* 8 is the number of required instructions cycles for the below loop statement. +1546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** The SDMMC_CMDTIMEOUT is expressed in ms */ +1547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + 33 .loc 1 1547 3 view .LVU1 + 34 .loc 1 1547 61 is_stmt 0 view .LVU2 + 35 0000 0B4B ldr r3, .L5 + 36 0002 1B68 ldr r3, [r3] + 37 0004 0B4A ldr r2, .L5+4 + 38 0006 A2FB0323 umull r2, r3, r2, r3 + 39 000a 5B0A lsrs r3, r3, #9 + 40 .loc 1 1547 12 view .LVU3 + 41 000c 41F28832 movw r2, #5000 + 42 0010 02FB03F3 mul r3, r2, r3 + 43 .LVL1: + 44 .L3: +1548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** do + 45 .loc 1 1549 3 is_stmt 1 view .LVU4 +1550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** if (count-- == 0U) + 46 .loc 1 1551 5 view .LVU5 + ARM GAS /tmp/ccPSMkLq.s page 29 + + + 47 0014 1A46 mov r2, r3 + 48 .loc 1 1551 14 is_stmt 0 view .LVU6 + 49 0016 013B subs r3, r3, #1 + 50 .LVL2: + 51 .loc 1 1551 8 view .LVU7 + 52 0018 3AB1 cbz r2, .L4 +1552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { +1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_TIMEOUT; +1554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } +1555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT)); + 53 .loc 1 1556 10 is_stmt 1 view .LVU8 + 54 .loc 1 1556 11 is_stmt 0 view .LVU9 + 55 001a 426B ldr r2, [r0, #52] + 56 .loc 1 1556 10 view .LVU10 + 57 001c 12F0800F tst r2, #128 + 58 0020 F8D0 beq .L3 +1557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Clear all the static flags */ +1559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + 59 .loc 1 1559 3 is_stmt 1 view .LVU11 + 60 0022 C523 movs r3, #197 + 61 .LVL3: + 62 .loc 1 1559 3 is_stmt 0 view .LVU12 + 63 0024 8363 str r3, [r0, #56] +1560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** +1561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return SDMMC_ERROR_NONE; + 64 .loc 1 1561 3 is_stmt 1 view .LVU13 + 65 .loc 1 1561 10 is_stmt 0 view .LVU14 + 66 0026 0020 movs r0, #0 + 67 .LVL4: + 68 .loc 1 1561 10 view .LVU15 + 69 0028 7047 bx lr + 70 .LVL5: + 71 .L4: +1553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 72 .loc 1 1553 14 view .LVU16 + 73 002a 4FF00040 mov r0, #-2147483648 + 74 .LVL6: +1562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 75 .loc 1 1562 1 view .LVU17 + 76 002e 7047 bx lr + 77 .L6: + 78 .align 2 + 79 .L5: + 80 0030 00000000 .word SystemCoreClock + 81 0034 D34D6210 .word 274877907 + 82 .cfi_endproc + 83 .LFE186: + 85 .section .text.SDMMC_Init,"ax",%progbits + 86 .align 1 + 87 .global SDMMC_Init + 88 .syntax unified + 89 .thumb + 90 .thumb_func + 92 SDMMC_Init: + 93 .LVL7: + ARM GAS /tmp/ccPSMkLq.s page 30 + + + 94 .LFB141: + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t tmpreg = 0; + 95 .loc 1 208 1 is_stmt 1 view -0 + 96 .cfi_startproc + 97 @ args = 28, pretend = 16, frame = 0 + 98 @ frame_needed = 0, uses_anonymous_args = 0 + 99 @ link register save eliminated. + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t tmpreg = 0; + 100 .loc 1 208 1 is_stmt 0 view .LVU19 + 101 0000 84B0 sub sp, sp, #16 + 102 .LCFI0: + 103 .cfi_def_cfa_offset 16 + 104 0002 0DF1040C add ip, sp, #4 + 105 0006 8CE80E00 stm ip, {r1, r2, r3} + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 106 .loc 1 209 3 is_stmt 1 view .LVU20 + 107 .LVL8: + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); + 108 .loc 1 212 3 view .LVU21 + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass)); + 109 .loc 1 213 3 view .LVU22 + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave)); + 110 .loc 1 214 3 view .LVU23 + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide)); + 111 .loc 1 215 3 view .LVU24 + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); + 112 .loc 1 216 3 view .LVU25 + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv)); + 113 .loc 1 217 3 view .LVU26 + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 114 .loc 1 218 3 view .LVU27 + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Init.ClockBypass |\ + 115 .loc 1 221 3 view .LVU28 + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Init.ClockBypass |\ + 116 .loc 1 221 39 is_stmt 0 view .LVU29 + 117 000a 0B46 mov r3, r1 + 118 000c 1343 orrs r3, r3, r2 + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Init.BusWide |\ + 119 .loc 1 223 18 view .LVU30 + 120 000e 039A ldr r2, [sp, #12] + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Init.ClockPowerSave |\ + 121 .loc 1 222 39 view .LVU31 + 122 0010 1343 orrs r3, r3, r2 + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Init.HardwareFlowControl |\ + 123 .loc 1 224 18 view .LVU32 + 124 0012 049A ldr r2, [sp, #16] + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Init.BusWide |\ + 125 .loc 1 223 39 view .LVU33 + 126 0014 1343 orrs r3, r3, r2 + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Init.ClockDiv + 127 .loc 1 225 18 view .LVU34 + 128 0016 059A ldr r2, [sp, #20] + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Init.HardwareFlowControl |\ + 129 .loc 1 224 39 view .LVU35 + 130 0018 1343 orrs r3, r3, r2 + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ); + 131 .loc 1 226 18 view .LVU36 + ARM GAS /tmp/ccPSMkLq.s page 31 + + + 132 001a 069A ldr r2, [sp, #24] + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Init.ClockDiv + 133 .loc 1 225 39 view .LVU37 + 134 001c 1343 orrs r3, r3, r2 + 135 .LVL9: + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 136 .loc 1 230 3 is_stmt 1 view .LVU38 + 137 001e 4168 ldr r1, [r0, #4] + 138 0020 034A ldr r2, .L9 + 139 0022 0A40 ands r2, r2, r1 + 140 0024 1343 orrs r3, r3, r2 + 141 .LVL10: + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 142 .loc 1 230 3 is_stmt 0 view .LVU39 + 143 0026 4360 str r3, [r0, #4] + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 144 .loc 1 232 3 is_stmt 1 view .LVU40 + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 145 .loc 1 233 1 is_stmt 0 view .LVU41 + 146 0028 0020 movs r0, #0 + 147 .LVL11: + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 148 .loc 1 233 1 view .LVU42 + 149 002a 04B0 add sp, sp, #16 + 150 .LCFI1: + 151 .cfi_def_cfa_offset 0 + 152 002c 7047 bx lr + 153 .L10: + 154 002e 00BF .align 2 + 155 .L9: + 156 0030 0081FFFF .word -32512 + 157 .cfi_endproc + 158 .LFE141: + 160 .section .text.SDMMC_ReadFIFO,"ax",%progbits + 161 .align 1 + 162 .global SDMMC_ReadFIFO + 163 .syntax unified + 164 .thumb + 165 .thumb_func + 167 SDMMC_ReadFIFO: + 168 .LVL12: + 169 .LFB142: + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Read data from Rx FIFO */ + 170 .loc 1 261 1 is_stmt 1 view -0 + 171 .cfi_startproc + 172 @ args = 0, pretend = 0, frame = 0 + 173 @ frame_needed = 0, uses_anonymous_args = 0 + 174 @ link register save eliminated. + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 175 .loc 1 263 3 view .LVU44 + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 176 .loc 1 263 17 is_stmt 0 view .LVU45 + 177 0000 D0F88000 ldr r0, [r0, #128] + 178 .LVL13: + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 179 .loc 1 264 1 view .LVU46 + 180 0004 7047 bx lr + ARM GAS /tmp/ccPSMkLq.s page 32 + + + 181 .cfi_endproc + 182 .LFE142: + 184 .section .text.SDMMC_WriteFIFO,"ax",%progbits + 185 .align 1 + 186 .global SDMMC_WriteFIFO + 187 .syntax unified + 188 .thumb + 189 .thumb_func + 191 SDMMC_WriteFIFO: + 192 .LVL14: + 193 .LFB143: + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Write data to FIFO */ + 194 .loc 1 273 1 is_stmt 1 view -0 + 195 .cfi_startproc + 196 @ args = 0, pretend = 0, frame = 0 + 197 @ frame_needed = 0, uses_anonymous_args = 0 + 198 @ link register save eliminated. + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 199 .loc 1 275 3 view .LVU48 + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 200 .loc 1 275 18 is_stmt 0 view .LVU49 + 201 0000 0B68 ldr r3, [r1] + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 202 .loc 1 275 16 view .LVU50 + 203 0002 C0F88030 str r3, [r0, #128] + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 204 .loc 1 277 3 is_stmt 1 view .LVU51 + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 205 .loc 1 278 1 is_stmt 0 view .LVU52 + 206 0006 0020 movs r0, #0 + 207 .LVL15: + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 208 .loc 1 278 1 view .LVU53 + 209 0008 7047 bx lr + 210 .cfi_endproc + 211 .LFE143: + 213 .section .text.SDMMC_PowerState_ON,"ax",%progbits + 214 .align 1 + 215 .global SDMMC_PowerState_ON + 216 .syntax unified + 217 .thumb + 218 .thumb_func + 220 SDMMC_PowerState_ON: + 221 .LVL16: + 222 .LFB144: + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set power state to ON */ + 223 .loc 1 305 1 is_stmt 1 view -0 + 224 .cfi_startproc + 225 @ args = 0, pretend = 0, frame = 0 + 226 @ frame_needed = 0, uses_anonymous_args = 0 + 227 @ link register save eliminated. + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 228 .loc 1 307 3 view .LVU55 + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 229 .loc 1 307 17 is_stmt 0 view .LVU56 + 230 0000 0323 movs r3, #3 + 231 0002 0360 str r3, [r0] + ARM GAS /tmp/ccPSMkLq.s page 33 + + + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 232 .loc 1 309 3 is_stmt 1 view .LVU57 + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 233 .loc 1 310 1 is_stmt 0 view .LVU58 + 234 0004 0020 movs r0, #0 + 235 .LVL17: + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 236 .loc 1 310 1 view .LVU59 + 237 0006 7047 bx lr + 238 .cfi_endproc + 239 .LFE144: + 241 .section .text.SDMMC_PowerState_OFF,"ax",%progbits + 242 .align 1 + 243 .global SDMMC_PowerState_OFF + 244 .syntax unified + 245 .thumb + 246 .thumb_func + 248 SDMMC_PowerState_OFF: + 249 .LVL18: + 250 .LFB145: + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set power state to OFF */ + 251 .loc 1 318 1 is_stmt 1 view -0 + 252 .cfi_startproc + 253 @ args = 0, pretend = 0, frame = 0 + 254 @ frame_needed = 0, uses_anonymous_args = 0 + 255 @ link register save eliminated. + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Set power state to OFF */ + 256 .loc 1 318 1 is_stmt 0 view .LVU61 + 257 0000 0346 mov r3, r0 + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 258 .loc 1 320 3 is_stmt 1 view .LVU62 + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 259 .loc 1 320 17 is_stmt 0 view .LVU63 + 260 0002 0020 movs r0, #0 + 261 .LVL19: + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 262 .loc 1 320 17 view .LVU64 + 263 0004 1860 str r0, [r3] + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 264 .loc 1 322 3 is_stmt 1 view .LVU65 + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 265 .loc 1 323 1 is_stmt 0 view .LVU66 + 266 0006 7047 bx lr + 267 .cfi_endproc + 268 .LFE145: + 270 .section .text.SDMMC_GetPowerState,"ax",%progbits + 271 .align 1 + 272 .global SDMMC_GetPowerState + 273 .syntax unified + 274 .thumb + 275 .thumb_func + 277 SDMMC_GetPowerState: + 278 .LVL20: + 279 .LFB146: + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL); + 280 .loc 1 335 1 is_stmt 1 view -0 + 281 .cfi_startproc + ARM GAS /tmp/ccPSMkLq.s page 34 + + + 282 @ args = 0, pretend = 0, frame = 0 + 283 @ frame_needed = 0, uses_anonymous_args = 0 + 284 @ link register save eliminated. + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 285 .loc 1 336 3 view .LVU68 + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 286 .loc 1 336 17 is_stmt 0 view .LVU69 + 287 0000 0068 ldr r0, [r0] + 288 .LVL21: + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 289 .loc 1 337 1 view .LVU70 + 290 0002 00F00300 and r0, r0, #3 + 291 0006 7047 bx lr + 292 .cfi_endproc + 293 .LFE146: + 295 .section .text.SDMMC_SendCommand,"ax",%progbits + 296 .align 1 + 297 .global SDMMC_SendCommand + 298 .syntax unified + 299 .thumb + 300 .thumb_func + 302 SDMMC_SendCommand: + 303 .LVL22: + 304 .LFB147: + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t tmpreg = 0; + 305 .loc 1 348 1 is_stmt 1 view -0 + 306 .cfi_startproc + 307 @ args = 0, pretend = 0, frame = 0 + 308 @ frame_needed = 0, uses_anonymous_args = 0 + 309 @ link register save eliminated. + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 310 .loc 1 349 3 view .LVU72 + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_RESPONSE(Command->Response)); + 311 .loc 1 352 3 view .LVU73 + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt)); + 312 .loc 1 353 3 view .LVU74 + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_CPSM(Command->CPSM)); + 313 .loc 1 354 3 view .LVU75 + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 314 .loc 1 355 3 view .LVU76 + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 315 .loc 1 358 3 view .LVU77 + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 316 .loc 1 358 24 is_stmt 0 view .LVU78 + 317 0000 0B68 ldr r3, [r1] + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 318 .loc 1 358 15 view .LVU79 + 319 0002 8360 str r3, [r0, #8] + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Command->Response |\ + 320 .loc 1 361 3 is_stmt 1 view .LVU80 + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Command->Response |\ + 321 .loc 1 361 31 is_stmt 0 view .LVU81 + 322 0004 4B68 ldr r3, [r1, #4] + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Command->WaitForInterrupt |\ + 323 .loc 1 362 31 view .LVU82 + 324 0006 8A68 ldr r2, [r1, #8] + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Command->Response |\ + ARM GAS /tmp/ccPSMkLq.s page 35 + + + 325 .loc 1 361 50 view .LVU83 + 326 0008 1343 orrs r3, r3, r2 + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Command->CPSM); + 327 .loc 1 363 31 view .LVU84 + 328 000a CA68 ldr r2, [r1, #12] + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Command->WaitForInterrupt |\ + 329 .loc 1 362 50 view .LVU85 + 330 000c 1343 orrs r3, r3, r2 + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 331 .loc 1 364 31 view .LVU86 + 332 000e 0A69 ldr r2, [r1, #16] + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Command->CPSM); + 333 .loc 1 363 50 view .LVU87 + 334 0010 1343 orrs r3, r3, r2 + 335 .LVL23: + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 336 .loc 1 367 3 is_stmt 1 view .LVU88 + 337 0012 C268 ldr r2, [r0, #12] + 338 0014 6FF30B02 bfc r2, #0, #12 + 339 0018 1343 orrs r3, r3, r2 + 340 .LVL24: + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 341 .loc 1 367 3 is_stmt 0 view .LVU89 + 342 001a C360 str r3, [r0, #12] + 343 .LVL25: + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 344 .loc 1 369 3 is_stmt 1 view .LVU90 + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 345 .loc 1 370 1 is_stmt 0 view .LVU91 + 346 001c 0020 movs r0, #0 + 347 .LVL26: + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 348 .loc 1 370 1 view .LVU92 + 349 001e 7047 bx lr + 350 .cfi_endproc + 351 .LFE147: + 353 .section .text.SDMMC_GetCommandResponse,"ax",%progbits + 354 .align 1 + 355 .global SDMMC_GetCommandResponse + 356 .syntax unified + 357 .thumb + 358 .thumb_func + 360 SDMMC_GetCommandResponse: + 361 .LVL27: + 362 .LFB148: + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return (uint8_t)(SDMMCx->RESPCMD); + 363 .loc 1 378 1 is_stmt 1 view -0 + 364 .cfi_startproc + 365 @ args = 0, pretend = 0, frame = 0 + 366 @ frame_needed = 0, uses_anonymous_args = 0 + 367 @ link register save eliminated. + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 368 .loc 1 379 3 view .LVU94 + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 369 .loc 1 379 26 is_stmt 0 view .LVU95 + 370 0000 0069 ldr r0, [r0, #16] + 371 .LVL28: + ARM GAS /tmp/ccPSMkLq.s page 36 + + + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 372 .loc 1 380 1 view .LVU96 + 373 0002 C0B2 uxtb r0, r0 + 374 0004 7047 bx lr + 375 .cfi_endproc + 376 .LFE148: + 378 .section .text.SDMMC_GetResponse,"ax",%progbits + 379 .align 1 + 380 .global SDMMC_GetResponse + 381 .syntax unified + 382 .thumb + 383 .thumb_func + 385 SDMMC_GetResponse: + 386 .LVL29: + 387 .LFB149: + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t tmp; + 388 .loc 1 395 1 is_stmt 1 view -0 + 389 .cfi_startproc + 390 @ args = 0, pretend = 0, frame = 0 + 391 @ frame_needed = 0, uses_anonymous_args = 0 + 392 @ link register save eliminated. + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 393 .loc 1 396 3 view .LVU98 + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 394 .loc 1 399 3 view .LVU99 + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 395 .loc 1 402 3 view .LVU100 + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 396 .loc 1 402 20 is_stmt 0 view .LVU101 + 397 0000 1430 adds r0, r0, #20 + 398 .LVL30: + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 399 .loc 1 404 3 is_stmt 1 view .LVU102 + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 400 .loc 1 404 11 is_stmt 0 view .LVU103 + 401 0002 4058 ldr r0, [r0, r1] + 402 .LVL31: + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 403 .loc 1 405 1 view .LVU104 + 404 0004 7047 bx lr + 405 .cfi_endproc + 406 .LFE149: + 408 .section .text.SDMMC_ConfigData,"ax",%progbits + 409 .align 1 + 410 .global SDMMC_ConfigData + 411 .syntax unified + 412 .thumb + 413 .thumb_func + 415 SDMMC_ConfigData: + 416 .LVL32: + 417 .LFB150: + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t tmpreg = 0; + 418 .loc 1 416 1 is_stmt 1 view -0 + 419 .cfi_startproc + 420 @ args = 0, pretend = 0, frame = 0 + 421 @ frame_needed = 0, uses_anonymous_args = 0 + 422 @ link register save eliminated. + ARM GAS /tmp/ccPSMkLq.s page 37 + + + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 423 .loc 1 417 3 view .LVU106 + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize)); + 424 .loc 1 420 3 view .LVU107 + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir)); + 425 .loc 1 421 3 view .LVU108 + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode)); + 426 .loc 1 422 3 view .LVU109 + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** assert_param(IS_SDMMC_DPSM(Data->DPSM)); + 427 .loc 1 423 3 view .LVU110 + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 428 .loc 1 424 3 view .LVU111 + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 429 .loc 1 427 3 view .LVU112 + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 430 .loc 1 427 24 is_stmt 0 view .LVU113 + 431 0000 0B68 ldr r3, [r1] + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 432 .loc 1 427 18 view .LVU114 + 433 0002 4362 str r3, [r0, #36] + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 434 .loc 1 430 3 is_stmt 1 view .LVU115 + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 435 .loc 1 430 22 is_stmt 0 view .LVU116 + 436 0004 4B68 ldr r3, [r1, #4] + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 437 .loc 1 430 16 view .LVU117 + 438 0006 8362 str r3, [r0, #40] + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Data->TransferDir |\ + 439 .loc 1 433 3 is_stmt 1 view .LVU118 + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Data->TransferDir |\ + 440 .loc 1 433 28 is_stmt 0 view .LVU119 + 441 0008 8B68 ldr r3, [r1, #8] + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Data->TransferMode |\ + 442 .loc 1 434 28 view .LVU120 + 443 000a CA68 ldr r2, [r1, #12] + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Data->TransferDir |\ + 444 .loc 1 433 44 view .LVU121 + 445 000c 1343 orrs r3, r3, r2 + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Data->DPSM); + 446 .loc 1 435 28 view .LVU122 + 447 000e 0A69 ldr r2, [r1, #16] + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Data->TransferMode |\ + 448 .loc 1 434 44 view .LVU123 + 449 0010 1343 orrs r3, r3, r2 + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 450 .loc 1 436 28 view .LVU124 + 451 0012 4A69 ldr r2, [r1, #20] + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** Data->DPSM); + 452 .loc 1 435 44 view .LVU125 + 453 0014 1343 orrs r3, r3, r2 + 454 .LVL33: + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 455 .loc 1 439 3 is_stmt 1 view .LVU126 + 456 0016 C26A ldr r2, [r0, #44] + 457 0018 22F0F702 bic r2, r2, #247 + 458 001c 1343 orrs r3, r3, r2 + ARM GAS /tmp/ccPSMkLq.s page 38 + + + 459 .LVL34: + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 460 .loc 1 439 3 is_stmt 0 view .LVU127 + 461 001e C362 str r3, [r0, #44] + 462 .LVL35: + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 463 .loc 1 441 3 is_stmt 1 view .LVU128 + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 464 .loc 1 443 1 is_stmt 0 view .LVU129 + 465 0020 0020 movs r0, #0 + 466 .LVL36: + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 467 .loc 1 443 1 view .LVU130 + 468 0022 7047 bx lr + 469 .cfi_endproc + 470 .LFE150: + 472 .section .text.SDMMC_GetDataCounter,"ax",%progbits + 473 .align 1 + 474 .global SDMMC_GetDataCounter + 475 .syntax unified + 476 .thumb + 477 .thumb_func + 479 SDMMC_GetDataCounter: + 480 .LVL37: + 481 .LFB151: + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return (SDMMCx->DCOUNT); + 482 .loc 1 451 1 is_stmt 1 view -0 + 483 .cfi_startproc + 484 @ args = 0, pretend = 0, frame = 0 + 485 @ frame_needed = 0, uses_anonymous_args = 0 + 486 @ link register save eliminated. + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 487 .loc 1 452 3 view .LVU132 + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 488 .loc 1 452 17 is_stmt 0 view .LVU133 + 489 0000 006B ldr r0, [r0, #48] + 490 .LVL38: + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 491 .loc 1 453 1 view .LVU134 + 492 0002 7047 bx lr + 493 .cfi_endproc + 494 .LFE151: + 496 .section .text.SDMMC_GetFIFOCount,"ax",%progbits + 497 .align 1 + 498 .global SDMMC_GetFIFOCount + 499 .syntax unified + 500 .thumb + 501 .thumb_func + 503 SDMMC_GetFIFOCount: + 504 .LVL39: + 505 .LFB152: + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** return (SDMMCx->FIFO); + 506 .loc 1 461 1 is_stmt 1 view -0 + 507 .cfi_startproc + 508 @ args = 0, pretend = 0, frame = 0 + 509 @ frame_needed = 0, uses_anonymous_args = 0 + 510 @ link register save eliminated. + ARM GAS /tmp/ccPSMkLq.s page 39 + + + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 511 .loc 1 462 3 view .LVU136 + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 512 .loc 1 462 17 is_stmt 0 view .LVU137 + 513 0000 D0F88000 ldr r0, [r0, #128] + 514 .LVL40: + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 515 .loc 1 463 1 view .LVU138 + 516 0004 7047 bx lr + 517 .cfi_endproc + 518 .LFE152: + 520 .section .text.SDMMC_SetSDMMCReadWaitMode,"ax",%progbits + 521 .align 1 + 522 .global SDMMC_SetSDMMCReadWaitMode + 523 .syntax unified + 524 .thumb + 525 .thumb_func + 527 SDMMC_SetSDMMCReadWaitMode: + 528 .LVL41: + 529 .LFB153: + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* Check the parameters */ + 530 .loc 1 475 1 is_stmt 1 view -0 + 531 .cfi_startproc + 532 @ args = 0, pretend = 0, frame = 0 + 533 @ frame_needed = 0, uses_anonymous_args = 0 + 534 @ link register save eliminated. + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 535 .loc 1 477 3 view .LVU140 + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 536 .loc 1 480 3 view .LVU141 + 537 0000 C36A ldr r3, [r0, #44] + 538 0002 23F48063 bic r3, r3, #1024 + 539 0006 0B43 orrs r3, r3, r1 + 540 0008 C362 str r3, [r0, #44] + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 541 .loc 1 482 3 view .LVU142 + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 542 .loc 1 483 1 is_stmt 0 view .LVU143 + 543 000a 0020 movs r0, #0 + 544 .LVL42: + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 545 .loc 1 483 1 view .LVU144 + 546 000c 7047 bx lr + 547 .cfi_endproc + 548 .LFE153: + 550 .section .text.SDMMC_CmdGoIdleState,"ax",%progbits + 551 .align 1 + 552 .global SDMMC_CmdGoIdleState + 553 .syntax unified + 554 .thumb + 555 .thumb_func + 557 SDMMC_CmdGoIdleState: + 558 .LVL43: + 559 .LFB166: + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 560 .loc 1 799 1 is_stmt 1 view -0 + 561 .cfi_startproc + ARM GAS /tmp/ccPSMkLq.s page 40 + + + 562 @ args = 0, pretend = 0, frame = 24 + 563 @ frame_needed = 0, uses_anonymous_args = 0 + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 564 .loc 1 799 1 is_stmt 0 view .LVU146 + 565 0000 10B5 push {r4, lr} + 566 .LCFI2: + 567 .cfi_def_cfa_offset 8 + 568 .cfi_offset 4, -8 + 569 .cfi_offset 14, -4 + 570 0002 86B0 sub sp, sp, #24 + 571 .LCFI3: + 572 .cfi_def_cfa_offset 32 + 573 0004 0446 mov r4, r0 + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 574 .loc 1 800 3 is_stmt 1 view .LVU147 + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 575 .loc 1 801 3 view .LVU148 + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; + 576 .loc 1 803 3 view .LVU149 + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; + 577 .loc 1 803 34 is_stmt 0 view .LVU150 + 578 0006 0023 movs r3, #0 + 579 0008 0193 str r3, [sp, #4] + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_NO; + 580 .loc 1 804 3 is_stmt 1 view .LVU151 + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_NO; + 581 .loc 1 804 34 is_stmt 0 view .LVU152 + 582 000a 0293 str r3, [sp, #8] + 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 583 .loc 1 805 3 is_stmt 1 view .LVU153 + 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 584 .loc 1 805 34 is_stmt 0 view .LVU154 + 585 000c 0393 str r3, [sp, #12] + 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 586 .loc 1 806 3 is_stmt 1 view .LVU155 + 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 587 .loc 1 806 34 is_stmt 0 view .LVU156 + 588 000e 0493 str r3, [sp, #16] + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 589 .loc 1 807 3 is_stmt 1 view .LVU157 + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 590 .loc 1 807 34 is_stmt 0 view .LVU158 + 591 0010 4FF48063 mov r3, #1024 + 592 0014 0593 str r3, [sp, #20] + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 593 .loc 1 808 3 is_stmt 1 view .LVU159 + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 594 .loc 1 808 9 is_stmt 0 view .LVU160 + 595 0016 01A9 add r1, sp, #4 + 596 0018 FFF7FEFF bl SDMMC_SendCommand + 597 .LVL44: + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 598 .loc 1 811 3 is_stmt 1 view .LVU161 + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 599 .loc 1 811 16 is_stmt 0 view .LVU162 + 600 001c 2046 mov r0, r4 + 601 001e FFF7FEFF bl SDMMC_GetCmdError + ARM GAS /tmp/ccPSMkLq.s page 41 + + + 602 .LVL45: + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 603 .loc 1 813 3 is_stmt 1 view .LVU163 + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 604 .loc 1 814 1 is_stmt 0 view .LVU164 + 605 0022 06B0 add sp, sp, #24 + 606 .LCFI4: + 607 .cfi_def_cfa_offset 8 + 608 @ sp needed + 609 0024 10BD pop {r4, pc} + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 610 .loc 1 814 1 view .LVU165 + 611 .cfi_endproc + 612 .LFE166: + 614 .section .text.SDMMC_GetCmdResp1,"ax",%progbits + 615 .align 1 + 616 .global SDMMC_GetCmdResp1 + 617 .syntax unified + 618 .thumb + 619 .thumb_func + 621 SDMMC_GetCmdResp1: + 622 .LVL46: + 623 .LFB181: +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t response_r1; + 624 .loc 1 1192 1 is_stmt 1 view -0 + 625 .cfi_startproc + 626 @ args = 0, pretend = 0, frame = 0 + 627 @ frame_needed = 0, uses_anonymous_args = 0 +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t response_r1; + 628 .loc 1 1192 1 is_stmt 0 view .LVU167 + 629 0000 38B5 push {r3, r4, r5, lr} + 630 .LCFI5: + 631 .cfi_def_cfa_offset 16 + 632 .cfi_offset 3, -16 + 633 .cfi_offset 4, -12 + 634 .cfi_offset 5, -8 + 635 .cfi_offset 14, -4 + 636 0002 0446 mov r4, r0 + 637 0004 0D46 mov r5, r1 +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t sta_reg; + 638 .loc 1 1193 3 is_stmt 1 view .LVU168 +1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 639 .loc 1 1194 3 view .LVU169 +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 640 .loc 1 1198 3 view .LVU170 +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 641 .loc 1 1198 52 is_stmt 0 view .LVU171 + 642 0006 504B ldr r3, .L53 + 643 0008 1B68 ldr r3, [r3] + 644 000a 5049 ldr r1, .L53+4 + 645 .LVL47: +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 646 .loc 1 1198 52 view .LVU172 + 647 000c A1FB0313 umull r1, r3, r1, r3 + 648 0010 5B0A lsrs r3, r3, #9 +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 649 .loc 1 1198 12 view .LVU173 + ARM GAS /tmp/ccPSMkLq.s page 42 + + + 650 0012 03FB02F2 mul r2, r3, r2 + 651 .LVL48: + 652 .L27: +1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 653 .loc 1 1200 3 is_stmt 1 view .LVU174 +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 654 .loc 1 1202 5 view .LVU175 + 655 0016 1346 mov r3, r2 +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 656 .loc 1 1202 14 is_stmt 0 view .LVU176 + 657 0018 013A subs r2, r2, #1 + 658 .LVL49: +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 659 .loc 1 1202 8 view .LVU177 + 660 001a 002B cmp r3, #0 + 661 001c 5DD0 beq .L30 +1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + 662 .loc 1 1206 5 is_stmt 1 view .LVU178 +1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + 663 .loc 1 1206 13 is_stmt 0 view .LVU179 + 664 001e 636B ldr r3, [r4, #52] + 665 .LVL50: +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + 666 .loc 1 1207 95 is_stmt 1 view .LVU180 + 667 0020 13F0450F tst r3, #69 + 668 0024 F7D0 beq .L27 +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + 669 .loc 1 1207 95 is_stmt 0 discriminator 1 view .LVU181 + 670 0026 13F4006F tst r3, #2048 + 671 002a F4D1 bne .L27 +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 672 .loc 1 1210 3 is_stmt 1 view .LVU182 +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 673 .loc 1 1210 6 is_stmt 0 view .LVU183 + 674 002c 636B ldr r3, [r4, #52] + 675 .LVL51: +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 676 .loc 1 1210 5 view .LVU184 + 677 002e 13F0040F tst r3, #4 + 678 0032 06D1 bne .L51 +1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 679 .loc 1 1216 8 is_stmt 1 view .LVU185 +1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 680 .loc 1 1216 11 is_stmt 0 view .LVU186 + 681 0034 636B ldr r3, [r4, #52] +1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 682 .loc 1 1216 10 view .LVU187 + 683 0036 13F0010F tst r3, #1 + 684 003a 05D0 beq .L29 +1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 685 .loc 1 1218 5 is_stmt 1 view .LVU188 + 686 003c 0120 movs r0, #1 + 687 .LVL52: +1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 688 .loc 1 1218 5 is_stmt 0 view .LVU189 + 689 003e A063 str r0, [r4, #56] +1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + ARM GAS /tmp/ccPSMkLq.s page 43 + + + 690 .loc 1 1220 5 is_stmt 1 view .LVU190 +1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 691 .loc 1 1220 12 is_stmt 0 view .LVU191 + 692 0040 4DE0 b .L25 + 693 .LVL53: + 694 .L51: +1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 695 .loc 1 1212 5 is_stmt 1 view .LVU192 + 696 0042 0420 movs r0, #4 + 697 .LVL54: +1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 698 .loc 1 1212 5 is_stmt 0 view .LVU193 + 699 0044 A063 str r0, [r4, #56] +1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 700 .loc 1 1214 5 is_stmt 1 view .LVU194 +1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 701 .loc 1 1214 12 is_stmt 0 view .LVU195 + 702 0046 4AE0 b .L25 + 703 .LVL55: + 704 .L29: +1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 705 .loc 1 1225 3 is_stmt 1 view .LVU196 +1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 706 .loc 1 1228 3 view .LVU197 + 707 0048 C523 movs r3, #197 + 708 004a A363 str r3, [r4, #56] +1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 709 .loc 1 1231 3 view .LVU198 +1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 710 .loc 1 1231 6 is_stmt 0 view .LVU199 + 711 004c 2046 mov r0, r4 + 712 .LVL56: +1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 713 .loc 1 1231 6 view .LVU200 + 714 004e FFF7FEFF bl SDMMC_GetCommandResponse + 715 .LVL57: +1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 716 .loc 1 1231 5 discriminator 1 view .LVU201 + 717 0052 A842 cmp r0, r5 + 718 0054 01D0 beq .L52 +1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 719 .loc 1 1233 12 view .LVU202 + 720 0056 0120 movs r0, #1 + 721 0058 41E0 b .L25 + 722 .L52: +1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 723 .loc 1 1237 3 is_stmt 1 view .LVU203 +1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 724 .loc 1 1237 17 is_stmt 0 view .LVU204 + 725 005a 0021 movs r1, #0 + 726 005c 2046 mov r0, r4 + 727 005e FFF7FEFF bl SDMMC_GetResponse + 728 .LVL58: + 729 0062 0346 mov r3, r0 + 730 .LVL59: +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 731 .loc 1 1239 3 is_stmt 1 view .LVU205 + ARM GAS /tmp/ccPSMkLq.s page 44 + + +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 732 .loc 1 1239 19 is_stmt 0 view .LVU206 + 733 0064 3A48 ldr r0, .L53+8 + 734 .LVL60: +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 735 .loc 1 1239 19 view .LVU207 + 736 0066 1840 ands r0, r0, r3 +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 737 .loc 1 1239 5 view .LVU208 + 738 0068 C8B3 cbz r0, .L25 +1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 739 .loc 1 1243 8 is_stmt 1 view .LVU209 +1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 740 .loc 1 1243 10 is_stmt 0 view .LVU210 + 741 006a 002B cmp r3, #0 + 742 006c 38DB blt .L32 +1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 743 .loc 1 1247 8 is_stmt 1 view .LVU211 +1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 744 .loc 1 1247 10 is_stmt 0 view .LVU212 + 745 006e 13F0804F tst r3, #1073741824 + 746 0072 38D1 bne .L33 +1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 747 .loc 1 1251 8 is_stmt 1 view .LVU213 +1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 748 .loc 1 1251 10 is_stmt 0 view .LVU214 + 749 0074 13F0005F tst r3, #536870912 + 750 0078 37D1 bne .L34 +1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 751 .loc 1 1255 8 is_stmt 1 view .LVU215 +1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 752 .loc 1 1255 10 is_stmt 0 view .LVU216 + 753 007a 13F0805F tst r3, #268435456 + 754 007e 36D1 bne .L35 +1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 755 .loc 1 1259 8 is_stmt 1 view .LVU217 +1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 756 .loc 1 1259 10 is_stmt 0 view .LVU218 + 757 0080 13F0006F tst r3, #134217728 + 758 0084 36D1 bne .L36 +1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 759 .loc 1 1263 8 is_stmt 1 view .LVU219 +1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 760 .loc 1 1263 10 is_stmt 0 view .LVU220 + 761 0086 13F0806F tst r3, #67108864 + 762 008a 36D1 bne .L37 +1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 763 .loc 1 1267 8 is_stmt 1 view .LVU221 +1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 764 .loc 1 1267 10 is_stmt 0 view .LVU222 + 765 008c 13F0807F tst r3, #16777216 + 766 0090 36D1 bne .L38 +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 767 .loc 1 1271 8 is_stmt 1 view .LVU223 +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 768 .loc 1 1271 10 is_stmt 0 view .LVU224 + 769 0092 13F4000F tst r3, #8388608 + ARM GAS /tmp/ccPSMkLq.s page 45 + + + 770 0096 36D1 bne .L39 +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 771 .loc 1 1275 8 is_stmt 1 view .LVU225 +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 772 .loc 1 1275 10 is_stmt 0 view .LVU226 + 773 0098 13F4800F tst r3, #4194304 + 774 009c 36D1 bne .L40 +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 775 .loc 1 1279 8 is_stmt 1 view .LVU227 +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 776 .loc 1 1279 10 is_stmt 0 view .LVU228 + 777 009e 13F4001F tst r3, #2097152 + 778 00a2 36D1 bne .L41 +1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 779 .loc 1 1283 8 is_stmt 1 view .LVU229 +1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 780 .loc 1 1283 10 is_stmt 0 view .LVU230 + 781 00a4 13F4801F tst r3, #1048576 + 782 00a8 36D1 bne .L42 +1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 783 .loc 1 1287 8 is_stmt 1 view .LVU231 +1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 784 .loc 1 1287 10 is_stmt 0 view .LVU232 + 785 00aa 13F4802F tst r3, #262144 + 786 00ae 36D1 bne .L43 +1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 787 .loc 1 1291 8 is_stmt 1 view .LVU233 +1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 788 .loc 1 1291 10 is_stmt 0 view .LVU234 + 789 00b0 13F4003F tst r3, #131072 + 790 00b4 36D1 bne .L44 +1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 791 .loc 1 1295 8 is_stmt 1 view .LVU235 +1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 792 .loc 1 1295 10 is_stmt 0 view .LVU236 + 793 00b6 13F4803F tst r3, #65536 + 794 00ba 36D1 bne .L45 +1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 795 .loc 1 1299 8 is_stmt 1 view .LVU237 +1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 796 .loc 1 1299 10 is_stmt 0 view .LVU238 + 797 00bc 13F4004F tst r3, #32768 + 798 00c0 36D1 bne .L46 +1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 799 .loc 1 1303 8 is_stmt 1 view .LVU239 +1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 800 .loc 1 1303 10 is_stmt 0 view .LVU240 + 801 00c2 13F4804F tst r3, #16384 + 802 00c6 36D1 bne .L47 +1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 803 .loc 1 1307 8 is_stmt 1 view .LVU241 +1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 804 .loc 1 1307 10 is_stmt 0 view .LVU242 + 805 00c8 13F4005F tst r3, #8192 + 806 00cc 36D1 bne .L48 +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 807 .loc 1 1311 8 is_stmt 1 view .LVU243 + ARM GAS /tmp/ccPSMkLq.s page 46 + + +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 808 .loc 1 1311 10 is_stmt 0 view .LVU244 + 809 00ce 13F0080F tst r3, #8 + 810 00d2 36D0 beq .L49 +1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 811 .loc 1 1313 12 view .LVU245 + 812 00d4 4FF40000 mov r0, #8388608 + 813 00d8 01E0 b .L25 + 814 .LVL61: + 815 .L30: +1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 816 .loc 1 1204 14 view .LVU246 + 817 00da 4FF00040 mov r0, #-2147483648 + 818 .LVL62: + 819 .L25: +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 820 .loc 1 1319 1 view .LVU247 + 821 00de 38BD pop {r3, r4, r5, pc} + 822 .LVL63: + 823 .L32: +1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 824 .loc 1 1245 12 view .LVU248 + 825 00e0 4FF00070 mov r0, #33554432 + 826 00e4 FBE7 b .L25 + 827 .L33: +1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 828 .loc 1 1249 12 view .LVU249 + 829 00e6 4020 movs r0, #64 + 830 00e8 F9E7 b .L25 + 831 .L34: +1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 832 .loc 1 1253 12 view .LVU250 + 833 00ea 8020 movs r0, #128 + 834 00ec F7E7 b .L25 + 835 .L35: +1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 836 .loc 1 1257 12 view .LVU251 + 837 00ee 4FF48070 mov r0, #256 + 838 00f2 F4E7 b .L25 + 839 .L36: +1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 840 .loc 1 1261 12 view .LVU252 + 841 00f4 4FF40070 mov r0, #512 + 842 00f8 F1E7 b .L25 + 843 .L37: +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 844 .loc 1 1265 12 view .LVU253 + 845 00fa 4FF48060 mov r0, #1024 + 846 00fe EEE7 b .L25 + 847 .L38: +1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 848 .loc 1 1269 12 view .LVU254 + 849 0100 4FF40060 mov r0, #2048 + 850 0104 EBE7 b .L25 + 851 .L39: +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 852 .loc 1 1273 12 view .LVU255 + ARM GAS /tmp/ccPSMkLq.s page 47 + + + 853 0106 4FF48050 mov r0, #4096 + 854 010a E8E7 b .L25 + 855 .L40: +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 856 .loc 1 1277 12 view .LVU256 + 857 010c 4FF40050 mov r0, #8192 + 858 0110 E5E7 b .L25 + 859 .L41: +1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 860 .loc 1 1281 12 view .LVU257 + 861 0112 4FF48040 mov r0, #16384 + 862 0116 E2E7 b .L25 + 863 .L42: +1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 864 .loc 1 1285 12 view .LVU258 + 865 0118 4FF40040 mov r0, #32768 + 866 011c DFE7 b .L25 + 867 .L43: +1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 868 .loc 1 1289 12 view .LVU259 + 869 011e 4FF40030 mov r0, #131072 + 870 0122 DCE7 b .L25 + 871 .L44: +1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 872 .loc 1 1293 12 view .LVU260 + 873 0124 4FF48020 mov r0, #262144 + 874 0128 D9E7 b .L25 + 875 .L45: +1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 876 .loc 1 1297 12 view .LVU261 + 877 012a 4FF40020 mov r0, #524288 + 878 012e D6E7 b .L25 + 879 .L46: +1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 880 .loc 1 1301 12 view .LVU262 + 881 0130 4FF48010 mov r0, #1048576 + 882 0134 D3E7 b .L25 + 883 .L47: +1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 884 .loc 1 1305 12 view .LVU263 + 885 0136 4FF40010 mov r0, #2097152 + 886 013a D0E7 b .L25 + 887 .L48: +1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 888 .loc 1 1309 12 view .LVU264 + 889 013c 4FF48000 mov r0, #4194304 + 890 0140 CDE7 b .L25 + 891 .L49: +1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 892 .loc 1 1317 12 view .LVU265 + 893 0142 4FF48030 mov r0, #65536 + 894 0146 CAE7 b .L25 + 895 .L54: + 896 .align 2 + 897 .L53: + 898 0148 00000000 .word SystemCoreClock + 899 014c D34D6210 .word 274877907 + ARM GAS /tmp/ccPSMkLq.s page 48 + + + 900 0150 08E0FFFD .word -33562616 + 901 .cfi_endproc + 902 .LFE181: + 904 .section .text.SDMMC_CmdBlockLength,"ax",%progbits + 905 .align 1 + 906 .global SDMMC_CmdBlockLength + 907 .syntax unified + 908 .thumb + 909 .thumb_func + 911 SDMMC_CmdBlockLength: + 912 .LVL64: + 913 .LFB154: + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 914 .loc 1 510 1 is_stmt 1 view -0 + 915 .cfi_startproc + 916 @ args = 0, pretend = 0, frame = 24 + 917 @ frame_needed = 0, uses_anonymous_args = 0 + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 918 .loc 1 510 1 is_stmt 0 view .LVU267 + 919 0000 30B5 push {r4, r5, lr} + 920 .LCFI6: + 921 .cfi_def_cfa_offset 12 + 922 .cfi_offset 4, -12 + 923 .cfi_offset 5, -8 + 924 .cfi_offset 14, -4 + 925 0002 87B0 sub sp, sp, #28 + 926 .LCFI7: + 927 .cfi_def_cfa_offset 40 + 928 0004 0446 mov r4, r0 + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 929 .loc 1 511 3 is_stmt 1 view .LVU268 + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 930 .loc 1 512 3 view .LVU269 + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN; + 931 .loc 1 515 3 view .LVU270 + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN; + 932 .loc 1 515 34 is_stmt 0 view .LVU271 + 933 0006 0191 str r1, [sp, #4] + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 934 .loc 1 516 3 is_stmt 1 view .LVU272 + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 935 .loc 1 516 34 is_stmt 0 view .LVU273 + 936 0008 1025 movs r5, #16 + 937 000a 0295 str r5, [sp, #8] + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 938 .loc 1 517 3 is_stmt 1 view .LVU274 + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 939 .loc 1 517 34 is_stmt 0 view .LVU275 + 940 000c 4023 movs r3, #64 + 941 000e 0393 str r3, [sp, #12] + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 942 .loc 1 518 3 is_stmt 1 view .LVU276 + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 943 .loc 1 518 34 is_stmt 0 view .LVU277 + 944 0010 0023 movs r3, #0 + 945 0012 0493 str r3, [sp, #16] + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + ARM GAS /tmp/ccPSMkLq.s page 49 + + + 946 .loc 1 519 3 is_stmt 1 view .LVU278 + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 947 .loc 1 519 34 is_stmt 0 view .LVU279 + 948 0014 4FF48063 mov r3, #1024 + 949 0018 0593 str r3, [sp, #20] + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 950 .loc 1 520 3 is_stmt 1 view .LVU280 + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 951 .loc 1 520 9 is_stmt 0 view .LVU281 + 952 001a 01A9 add r1, sp, #4 + 953 .LVL65: + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 954 .loc 1 520 9 view .LVU282 + 955 001c FFF7FEFF bl SDMMC_SendCommand + 956 .LVL66: + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 957 .loc 1 523 3 is_stmt 1 view .LVU283 + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 958 .loc 1 523 16 is_stmt 0 view .LVU284 + 959 0020 41F28832 movw r2, #5000 + 960 0024 2946 mov r1, r5 + 961 0026 2046 mov r0, r4 + 962 0028 FFF7FEFF bl SDMMC_GetCmdResp1 + 963 .LVL67: + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 964 .loc 1 525 3 is_stmt 1 view .LVU285 + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 965 .loc 1 526 1 is_stmt 0 view .LVU286 + 966 002c 07B0 add sp, sp, #28 + 967 .LCFI8: + 968 .cfi_def_cfa_offset 12 + 969 @ sp needed + 970 002e 30BD pop {r4, r5, pc} + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 971 .loc 1 526 1 view .LVU287 + 972 .cfi_endproc + 973 .LFE154: + 975 .section .text.SDMMC_CmdReadSingleBlock,"ax",%progbits + 976 .align 1 + 977 .global SDMMC_CmdReadSingleBlock + 978 .syntax unified + 979 .thumb + 980 .thumb_func + 982 SDMMC_CmdReadSingleBlock: + 983 .LVL68: + 984 .LFB155: + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 985 .loc 1 534 1 is_stmt 1 view -0 + 986 .cfi_startproc + 987 @ args = 0, pretend = 0, frame = 24 + 988 @ frame_needed = 0, uses_anonymous_args = 0 + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 989 .loc 1 534 1 is_stmt 0 view .LVU289 + 990 0000 30B5 push {r4, r5, lr} + 991 .LCFI9: + 992 .cfi_def_cfa_offset 12 + 993 .cfi_offset 4, -12 + ARM GAS /tmp/ccPSMkLq.s page 50 + + + 994 .cfi_offset 5, -8 + 995 .cfi_offset 14, -4 + 996 0002 87B0 sub sp, sp, #28 + 997 .LCFI10: + 998 .cfi_def_cfa_offset 40 + 999 0004 0446 mov r4, r0 + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 1000 .loc 1 535 3 is_stmt 1 view .LVU290 + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1001 .loc 1 536 3 view .LVU291 + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK; + 1002 .loc 1 539 3 view .LVU292 + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK; + 1003 .loc 1 539 34 is_stmt 0 view .LVU293 + 1004 0006 0191 str r1, [sp, #4] + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1005 .loc 1 540 3 is_stmt 1 view .LVU294 + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1006 .loc 1 540 34 is_stmt 0 view .LVU295 + 1007 0008 1125 movs r5, #17 + 1008 000a 0295 str r5, [sp, #8] + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1009 .loc 1 541 3 is_stmt 1 view .LVU296 + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1010 .loc 1 541 34 is_stmt 0 view .LVU297 + 1011 000c 4023 movs r3, #64 + 1012 000e 0393 str r3, [sp, #12] + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1013 .loc 1 542 3 is_stmt 1 view .LVU298 + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1014 .loc 1 542 34 is_stmt 0 view .LVU299 + 1015 0010 0023 movs r3, #0 + 1016 0012 0493 str r3, [sp, #16] + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1017 .loc 1 543 3 is_stmt 1 view .LVU300 + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1018 .loc 1 543 34 is_stmt 0 view .LVU301 + 1019 0014 4FF48063 mov r3, #1024 + 1020 0018 0593 str r3, [sp, #20] + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1021 .loc 1 544 3 is_stmt 1 view .LVU302 + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1022 .loc 1 544 9 is_stmt 0 view .LVU303 + 1023 001a 01A9 add r1, sp, #4 + 1024 .LVL69: + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1025 .loc 1 544 9 view .LVU304 + 1026 001c FFF7FEFF bl SDMMC_SendCommand + 1027 .LVL70: + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1028 .loc 1 547 3 is_stmt 1 view .LVU305 + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1029 .loc 1 547 16 is_stmt 0 view .LVU306 + 1030 0020 41F28832 movw r2, #5000 + 1031 0024 2946 mov r1, r5 + 1032 0026 2046 mov r0, r4 + 1033 0028 FFF7FEFF bl SDMMC_GetCmdResp1 + ARM GAS /tmp/ccPSMkLq.s page 51 + + + 1034 .LVL71: + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 1035 .loc 1 549 3 is_stmt 1 view .LVU307 + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1036 .loc 1 550 1 is_stmt 0 view .LVU308 + 1037 002c 07B0 add sp, sp, #28 + 1038 .LCFI11: + 1039 .cfi_def_cfa_offset 12 + 1040 @ sp needed + 1041 002e 30BD pop {r4, r5, pc} + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1042 .loc 1 550 1 view .LVU309 + 1043 .cfi_endproc + 1044 .LFE155: + 1046 .section .text.SDMMC_CmdReadMultiBlock,"ax",%progbits + 1047 .align 1 + 1048 .global SDMMC_CmdReadMultiBlock + 1049 .syntax unified + 1050 .thumb + 1051 .thumb_func + 1053 SDMMC_CmdReadMultiBlock: + 1054 .LVL72: + 1055 .LFB156: + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1056 .loc 1 558 1 is_stmt 1 view -0 + 1057 .cfi_startproc + 1058 @ args = 0, pretend = 0, frame = 24 + 1059 @ frame_needed = 0, uses_anonymous_args = 0 + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1060 .loc 1 558 1 is_stmt 0 view .LVU311 + 1061 0000 30B5 push {r4, r5, lr} + 1062 .LCFI12: + 1063 .cfi_def_cfa_offset 12 + 1064 .cfi_offset 4, -12 + 1065 .cfi_offset 5, -8 + 1066 .cfi_offset 14, -4 + 1067 0002 87B0 sub sp, sp, #28 + 1068 .LCFI13: + 1069 .cfi_def_cfa_offset 40 + 1070 0004 0446 mov r4, r0 + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 1071 .loc 1 559 3 is_stmt 1 view .LVU312 + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1072 .loc 1 560 3 view .LVU313 + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK; + 1073 .loc 1 563 3 view .LVU314 + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK; + 1074 .loc 1 563 34 is_stmt 0 view .LVU315 + 1075 0006 0191 str r1, [sp, #4] + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1076 .loc 1 564 3 is_stmt 1 view .LVU316 + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1077 .loc 1 564 34 is_stmt 0 view .LVU317 + 1078 0008 1225 movs r5, #18 + 1079 000a 0295 str r5, [sp, #8] + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1080 .loc 1 565 3 is_stmt 1 view .LVU318 + ARM GAS /tmp/ccPSMkLq.s page 52 + + + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1081 .loc 1 565 34 is_stmt 0 view .LVU319 + 1082 000c 4023 movs r3, #64 + 1083 000e 0393 str r3, [sp, #12] + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1084 .loc 1 566 3 is_stmt 1 view .LVU320 + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1085 .loc 1 566 34 is_stmt 0 view .LVU321 + 1086 0010 0023 movs r3, #0 + 1087 0012 0493 str r3, [sp, #16] + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1088 .loc 1 567 3 is_stmt 1 view .LVU322 + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1089 .loc 1 567 34 is_stmt 0 view .LVU323 + 1090 0014 4FF48063 mov r3, #1024 + 1091 0018 0593 str r3, [sp, #20] + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1092 .loc 1 568 3 is_stmt 1 view .LVU324 + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1093 .loc 1 568 9 is_stmt 0 view .LVU325 + 1094 001a 01A9 add r1, sp, #4 + 1095 .LVL73: + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1096 .loc 1 568 9 view .LVU326 + 1097 001c FFF7FEFF bl SDMMC_SendCommand + 1098 .LVL74: + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1099 .loc 1 571 3 is_stmt 1 view .LVU327 + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1100 .loc 1 571 16 is_stmt 0 view .LVU328 + 1101 0020 41F28832 movw r2, #5000 + 1102 0024 2946 mov r1, r5 + 1103 0026 2046 mov r0, r4 + 1104 0028 FFF7FEFF bl SDMMC_GetCmdResp1 + 1105 .LVL75: + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 1106 .loc 1 573 3 is_stmt 1 view .LVU329 + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1107 .loc 1 574 1 is_stmt 0 view .LVU330 + 1108 002c 07B0 add sp, sp, #28 + 1109 .LCFI14: + 1110 .cfi_def_cfa_offset 12 + 1111 @ sp needed + 1112 002e 30BD pop {r4, r5, pc} + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1113 .loc 1 574 1 view .LVU331 + 1114 .cfi_endproc + 1115 .LFE156: + 1117 .section .text.SDMMC_CmdWriteSingleBlock,"ax",%progbits + 1118 .align 1 + 1119 .global SDMMC_CmdWriteSingleBlock + 1120 .syntax unified + 1121 .thumb + 1122 .thumb_func + 1124 SDMMC_CmdWriteSingleBlock: + 1125 .LVL76: + 1126 .LFB157: + ARM GAS /tmp/ccPSMkLq.s page 53 + + + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1127 .loc 1 582 1 is_stmt 1 view -0 + 1128 .cfi_startproc + 1129 @ args = 0, pretend = 0, frame = 24 + 1130 @ frame_needed = 0, uses_anonymous_args = 0 + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1131 .loc 1 582 1 is_stmt 0 view .LVU333 + 1132 0000 30B5 push {r4, r5, lr} + 1133 .LCFI15: + 1134 .cfi_def_cfa_offset 12 + 1135 .cfi_offset 4, -12 + 1136 .cfi_offset 5, -8 + 1137 .cfi_offset 14, -4 + 1138 0002 87B0 sub sp, sp, #28 + 1139 .LCFI16: + 1140 .cfi_def_cfa_offset 40 + 1141 0004 0446 mov r4, r0 + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 1142 .loc 1 583 3 is_stmt 1 view .LVU334 + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1143 .loc 1 584 3 view .LVU335 + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK; + 1144 .loc 1 587 3 view .LVU336 + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK; + 1145 .loc 1 587 34 is_stmt 0 view .LVU337 + 1146 0006 0191 str r1, [sp, #4] + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1147 .loc 1 588 3 is_stmt 1 view .LVU338 + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1148 .loc 1 588 34 is_stmt 0 view .LVU339 + 1149 0008 1825 movs r5, #24 + 1150 000a 0295 str r5, [sp, #8] + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1151 .loc 1 589 3 is_stmt 1 view .LVU340 + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1152 .loc 1 589 34 is_stmt 0 view .LVU341 + 1153 000c 4023 movs r3, #64 + 1154 000e 0393 str r3, [sp, #12] + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1155 .loc 1 590 3 is_stmt 1 view .LVU342 + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1156 .loc 1 590 34 is_stmt 0 view .LVU343 + 1157 0010 0023 movs r3, #0 + 1158 0012 0493 str r3, [sp, #16] + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1159 .loc 1 591 3 is_stmt 1 view .LVU344 + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1160 .loc 1 591 34 is_stmt 0 view .LVU345 + 1161 0014 4FF48063 mov r3, #1024 + 1162 0018 0593 str r3, [sp, #20] + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1163 .loc 1 592 3 is_stmt 1 view .LVU346 + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1164 .loc 1 592 9 is_stmt 0 view .LVU347 + 1165 001a 01A9 add r1, sp, #4 + 1166 .LVL77: + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + ARM GAS /tmp/ccPSMkLq.s page 54 + + + 1167 .loc 1 592 9 view .LVU348 + 1168 001c FFF7FEFF bl SDMMC_SendCommand + 1169 .LVL78: + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1170 .loc 1 595 3 is_stmt 1 view .LVU349 + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1171 .loc 1 595 16 is_stmt 0 view .LVU350 + 1172 0020 41F28832 movw r2, #5000 + 1173 0024 2946 mov r1, r5 + 1174 0026 2046 mov r0, r4 + 1175 0028 FFF7FEFF bl SDMMC_GetCmdResp1 + 1176 .LVL79: + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 1177 .loc 1 597 3 is_stmt 1 view .LVU351 + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1178 .loc 1 598 1 is_stmt 0 view .LVU352 + 1179 002c 07B0 add sp, sp, #28 + 1180 .LCFI17: + 1181 .cfi_def_cfa_offset 12 + 1182 @ sp needed + 1183 002e 30BD pop {r4, r5, pc} + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1184 .loc 1 598 1 view .LVU353 + 1185 .cfi_endproc + 1186 .LFE157: + 1188 .section .text.SDMMC_CmdWriteMultiBlock,"ax",%progbits + 1189 .align 1 + 1190 .global SDMMC_CmdWriteMultiBlock + 1191 .syntax unified + 1192 .thumb + 1193 .thumb_func + 1195 SDMMC_CmdWriteMultiBlock: + 1196 .LVL80: + 1197 .LFB158: + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1198 .loc 1 606 1 is_stmt 1 view -0 + 1199 .cfi_startproc + 1200 @ args = 0, pretend = 0, frame = 24 + 1201 @ frame_needed = 0, uses_anonymous_args = 0 + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1202 .loc 1 606 1 is_stmt 0 view .LVU355 + 1203 0000 30B5 push {r4, r5, lr} + 1204 .LCFI18: + 1205 .cfi_def_cfa_offset 12 + 1206 .cfi_offset 4, -12 + 1207 .cfi_offset 5, -8 + 1208 .cfi_offset 14, -4 + 1209 0002 87B0 sub sp, sp, #28 + 1210 .LCFI19: + 1211 .cfi_def_cfa_offset 40 + 1212 0004 0446 mov r4, r0 + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 1213 .loc 1 607 3 is_stmt 1 view .LVU356 + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1214 .loc 1 608 3 view .LVU357 + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK; + 1215 .loc 1 611 3 view .LVU358 + ARM GAS /tmp/ccPSMkLq.s page 55 + + + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK; + 1216 .loc 1 611 34 is_stmt 0 view .LVU359 + 1217 0006 0191 str r1, [sp, #4] + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1218 .loc 1 612 3 is_stmt 1 view .LVU360 + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1219 .loc 1 612 34 is_stmt 0 view .LVU361 + 1220 0008 1925 movs r5, #25 + 1221 000a 0295 str r5, [sp, #8] + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1222 .loc 1 613 3 is_stmt 1 view .LVU362 + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1223 .loc 1 613 34 is_stmt 0 view .LVU363 + 1224 000c 4023 movs r3, #64 + 1225 000e 0393 str r3, [sp, #12] + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1226 .loc 1 614 3 is_stmt 1 view .LVU364 + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1227 .loc 1 614 34 is_stmt 0 view .LVU365 + 1228 0010 0023 movs r3, #0 + 1229 0012 0493 str r3, [sp, #16] + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1230 .loc 1 615 3 is_stmt 1 view .LVU366 + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1231 .loc 1 615 34 is_stmt 0 view .LVU367 + 1232 0014 4FF48063 mov r3, #1024 + 1233 0018 0593 str r3, [sp, #20] + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1234 .loc 1 616 3 is_stmt 1 view .LVU368 + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1235 .loc 1 616 9 is_stmt 0 view .LVU369 + 1236 001a 01A9 add r1, sp, #4 + 1237 .LVL81: + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1238 .loc 1 616 9 view .LVU370 + 1239 001c FFF7FEFF bl SDMMC_SendCommand + 1240 .LVL82: + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1241 .loc 1 619 3 is_stmt 1 view .LVU371 + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1242 .loc 1 619 16 is_stmt 0 view .LVU372 + 1243 0020 41F28832 movw r2, #5000 + 1244 0024 2946 mov r1, r5 + 1245 0026 2046 mov r0, r4 + 1246 0028 FFF7FEFF bl SDMMC_GetCmdResp1 + 1247 .LVL83: + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 1248 .loc 1 621 3 is_stmt 1 view .LVU373 + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1249 .loc 1 622 1 is_stmt 0 view .LVU374 + 1250 002c 07B0 add sp, sp, #28 + 1251 .LCFI20: + 1252 .cfi_def_cfa_offset 12 + 1253 @ sp needed + 1254 002e 30BD pop {r4, r5, pc} + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1255 .loc 1 622 1 view .LVU375 + ARM GAS /tmp/ccPSMkLq.s page 56 + + + 1256 .cfi_endproc + 1257 .LFE158: + 1259 .section .text.SDMMC_CmdSDEraseStartAdd,"ax",%progbits + 1260 .align 1 + 1261 .global SDMMC_CmdSDEraseStartAdd + 1262 .syntax unified + 1263 .thumb + 1264 .thumb_func + 1266 SDMMC_CmdSDEraseStartAdd: + 1267 .LVL84: + 1268 .LFB159: + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1269 .loc 1 630 1 is_stmt 1 view -0 + 1270 .cfi_startproc + 1271 @ args = 0, pretend = 0, frame = 24 + 1272 @ frame_needed = 0, uses_anonymous_args = 0 + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1273 .loc 1 630 1 is_stmt 0 view .LVU377 + 1274 0000 30B5 push {r4, r5, lr} + 1275 .LCFI21: + 1276 .cfi_def_cfa_offset 12 + 1277 .cfi_offset 4, -12 + 1278 .cfi_offset 5, -8 + 1279 .cfi_offset 14, -4 + 1280 0002 87B0 sub sp, sp, #28 + 1281 .LCFI22: + 1282 .cfi_def_cfa_offset 40 + 1283 0004 0446 mov r4, r0 + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 1284 .loc 1 631 3 is_stmt 1 view .LVU378 + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1285 .loc 1 632 3 view .LVU379 + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START; + 1286 .loc 1 635 3 view .LVU380 + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START; + 1287 .loc 1 635 34 is_stmt 0 view .LVU381 + 1288 0006 0191 str r1, [sp, #4] + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1289 .loc 1 636 3 is_stmt 1 view .LVU382 + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1290 .loc 1 636 34 is_stmt 0 view .LVU383 + 1291 0008 2025 movs r5, #32 + 1292 000a 0295 str r5, [sp, #8] + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1293 .loc 1 637 3 is_stmt 1 view .LVU384 + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1294 .loc 1 637 34 is_stmt 0 view .LVU385 + 1295 000c 4023 movs r3, #64 + 1296 000e 0393 str r3, [sp, #12] + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1297 .loc 1 638 3 is_stmt 1 view .LVU386 + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1298 .loc 1 638 34 is_stmt 0 view .LVU387 + 1299 0010 0023 movs r3, #0 + 1300 0012 0493 str r3, [sp, #16] + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1301 .loc 1 639 3 is_stmt 1 view .LVU388 + ARM GAS /tmp/ccPSMkLq.s page 57 + + + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1302 .loc 1 639 34 is_stmt 0 view .LVU389 + 1303 0014 4FF48063 mov r3, #1024 + 1304 0018 0593 str r3, [sp, #20] + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1305 .loc 1 640 3 is_stmt 1 view .LVU390 + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1306 .loc 1 640 9 is_stmt 0 view .LVU391 + 1307 001a 01A9 add r1, sp, #4 + 1308 .LVL85: + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1309 .loc 1 640 9 view .LVU392 + 1310 001c FFF7FEFF bl SDMMC_SendCommand + 1311 .LVL86: + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1312 .loc 1 643 3 is_stmt 1 view .LVU393 + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1313 .loc 1 643 16 is_stmt 0 view .LVU394 + 1314 0020 41F28832 movw r2, #5000 + 1315 0024 2946 mov r1, r5 + 1316 0026 2046 mov r0, r4 + 1317 0028 FFF7FEFF bl SDMMC_GetCmdResp1 + 1318 .LVL87: + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 1319 .loc 1 645 3 is_stmt 1 view .LVU395 + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1320 .loc 1 646 1 is_stmt 0 view .LVU396 + 1321 002c 07B0 add sp, sp, #28 + 1322 .LCFI23: + 1323 .cfi_def_cfa_offset 12 + 1324 @ sp needed + 1325 002e 30BD pop {r4, r5, pc} + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1326 .loc 1 646 1 view .LVU397 + 1327 .cfi_endproc + 1328 .LFE159: + 1330 .section .text.SDMMC_CmdSDEraseEndAdd,"ax",%progbits + 1331 .align 1 + 1332 .global SDMMC_CmdSDEraseEndAdd + 1333 .syntax unified + 1334 .thumb + 1335 .thumb_func + 1337 SDMMC_CmdSDEraseEndAdd: + 1338 .LVL88: + 1339 .LFB160: + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1340 .loc 1 654 1 is_stmt 1 view -0 + 1341 .cfi_startproc + 1342 @ args = 0, pretend = 0, frame = 24 + 1343 @ frame_needed = 0, uses_anonymous_args = 0 + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1344 .loc 1 654 1 is_stmt 0 view .LVU399 + 1345 0000 30B5 push {r4, r5, lr} + 1346 .LCFI24: + 1347 .cfi_def_cfa_offset 12 + 1348 .cfi_offset 4, -12 + 1349 .cfi_offset 5, -8 + ARM GAS /tmp/ccPSMkLq.s page 58 + + + 1350 .cfi_offset 14, -4 + 1351 0002 87B0 sub sp, sp, #28 + 1352 .LCFI25: + 1353 .cfi_def_cfa_offset 40 + 1354 0004 0446 mov r4, r0 + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 1355 .loc 1 655 3 is_stmt 1 view .LVU400 + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1356 .loc 1 656 3 view .LVU401 + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END; + 1357 .loc 1 659 3 view .LVU402 + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END; + 1358 .loc 1 659 34 is_stmt 0 view .LVU403 + 1359 0006 0191 str r1, [sp, #4] + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1360 .loc 1 660 3 is_stmt 1 view .LVU404 + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1361 .loc 1 660 34 is_stmt 0 view .LVU405 + 1362 0008 2125 movs r5, #33 + 1363 000a 0295 str r5, [sp, #8] + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1364 .loc 1 661 3 is_stmt 1 view .LVU406 + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1365 .loc 1 661 34 is_stmt 0 view .LVU407 + 1366 000c 4023 movs r3, #64 + 1367 000e 0393 str r3, [sp, #12] + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1368 .loc 1 662 3 is_stmt 1 view .LVU408 + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1369 .loc 1 662 34 is_stmt 0 view .LVU409 + 1370 0010 0023 movs r3, #0 + 1371 0012 0493 str r3, [sp, #16] + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1372 .loc 1 663 3 is_stmt 1 view .LVU410 + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1373 .loc 1 663 34 is_stmt 0 view .LVU411 + 1374 0014 4FF48063 mov r3, #1024 + 1375 0018 0593 str r3, [sp, #20] + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1376 .loc 1 664 3 is_stmt 1 view .LVU412 + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1377 .loc 1 664 9 is_stmt 0 view .LVU413 + 1378 001a 01A9 add r1, sp, #4 + 1379 .LVL89: + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1380 .loc 1 664 9 view .LVU414 + 1381 001c FFF7FEFF bl SDMMC_SendCommand + 1382 .LVL90: + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1383 .loc 1 667 3 is_stmt 1 view .LVU415 + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1384 .loc 1 667 16 is_stmt 0 view .LVU416 + 1385 0020 41F28832 movw r2, #5000 + 1386 0024 2946 mov r1, r5 + 1387 0026 2046 mov r0, r4 + 1388 0028 FFF7FEFF bl SDMMC_GetCmdResp1 + 1389 .LVL91: + ARM GAS /tmp/ccPSMkLq.s page 59 + + + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 1390 .loc 1 669 3 is_stmt 1 view .LVU417 + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1391 .loc 1 670 1 is_stmt 0 view .LVU418 + 1392 002c 07B0 add sp, sp, #28 + 1393 .LCFI26: + 1394 .cfi_def_cfa_offset 12 + 1395 @ sp needed + 1396 002e 30BD pop {r4, r5, pc} + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1397 .loc 1 670 1 view .LVU419 + 1398 .cfi_endproc + 1399 .LFE160: + 1401 .section .text.SDMMC_CmdEraseStartAdd,"ax",%progbits + 1402 .align 1 + 1403 .global SDMMC_CmdEraseStartAdd + 1404 .syntax unified + 1405 .thumb + 1406 .thumb_func + 1408 SDMMC_CmdEraseStartAdd: + 1409 .LVL92: + 1410 .LFB161: + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1411 .loc 1 678 1 is_stmt 1 view -0 + 1412 .cfi_startproc + 1413 @ args = 0, pretend = 0, frame = 24 + 1414 @ frame_needed = 0, uses_anonymous_args = 0 + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1415 .loc 1 678 1 is_stmt 0 view .LVU421 + 1416 0000 30B5 push {r4, r5, lr} + 1417 .LCFI27: + 1418 .cfi_def_cfa_offset 12 + 1419 .cfi_offset 4, -12 + 1420 .cfi_offset 5, -8 + 1421 .cfi_offset 14, -4 + 1422 0002 87B0 sub sp, sp, #28 + 1423 .LCFI28: + 1424 .cfi_def_cfa_offset 40 + 1425 0004 0446 mov r4, r0 + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 1426 .loc 1 679 3 is_stmt 1 view .LVU422 + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1427 .loc 1 680 3 view .LVU423 + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START; + 1428 .loc 1 683 3 view .LVU424 + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START; + 1429 .loc 1 683 34 is_stmt 0 view .LVU425 + 1430 0006 0191 str r1, [sp, #4] + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1431 .loc 1 684 3 is_stmt 1 view .LVU426 + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1432 .loc 1 684 34 is_stmt 0 view .LVU427 + 1433 0008 2325 movs r5, #35 + 1434 000a 0295 str r5, [sp, #8] + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1435 .loc 1 685 3 is_stmt 1 view .LVU428 + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + ARM GAS /tmp/ccPSMkLq.s page 60 + + + 1436 .loc 1 685 34 is_stmt 0 view .LVU429 + 1437 000c 4023 movs r3, #64 + 1438 000e 0393 str r3, [sp, #12] + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1439 .loc 1 686 3 is_stmt 1 view .LVU430 + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1440 .loc 1 686 34 is_stmt 0 view .LVU431 + 1441 0010 0023 movs r3, #0 + 1442 0012 0493 str r3, [sp, #16] + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1443 .loc 1 687 3 is_stmt 1 view .LVU432 + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1444 .loc 1 687 34 is_stmt 0 view .LVU433 + 1445 0014 4FF48063 mov r3, #1024 + 1446 0018 0593 str r3, [sp, #20] + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1447 .loc 1 688 3 is_stmt 1 view .LVU434 + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1448 .loc 1 688 9 is_stmt 0 view .LVU435 + 1449 001a 01A9 add r1, sp, #4 + 1450 .LVL93: + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1451 .loc 1 688 9 view .LVU436 + 1452 001c FFF7FEFF bl SDMMC_SendCommand + 1453 .LVL94: + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1454 .loc 1 691 3 is_stmt 1 view .LVU437 + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1455 .loc 1 691 16 is_stmt 0 view .LVU438 + 1456 0020 41F28832 movw r2, #5000 + 1457 0024 2946 mov r1, r5 + 1458 0026 2046 mov r0, r4 + 1459 0028 FFF7FEFF bl SDMMC_GetCmdResp1 + 1460 .LVL95: + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 1461 .loc 1 693 3 is_stmt 1 view .LVU439 + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1462 .loc 1 694 1 is_stmt 0 view .LVU440 + 1463 002c 07B0 add sp, sp, #28 + 1464 .LCFI29: + 1465 .cfi_def_cfa_offset 12 + 1466 @ sp needed + 1467 002e 30BD pop {r4, r5, pc} + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1468 .loc 1 694 1 view .LVU441 + 1469 .cfi_endproc + 1470 .LFE161: + 1472 .section .text.SDMMC_CmdEraseEndAdd,"ax",%progbits + 1473 .align 1 + 1474 .global SDMMC_CmdEraseEndAdd + 1475 .syntax unified + 1476 .thumb + 1477 .thumb_func + 1479 SDMMC_CmdEraseEndAdd: + 1480 .LVL96: + 1481 .LFB162: + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + ARM GAS /tmp/ccPSMkLq.s page 61 + + + 1482 .loc 1 702 1 is_stmt 1 view -0 + 1483 .cfi_startproc + 1484 @ args = 0, pretend = 0, frame = 24 + 1485 @ frame_needed = 0, uses_anonymous_args = 0 + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1486 .loc 1 702 1 is_stmt 0 view .LVU443 + 1487 0000 30B5 push {r4, r5, lr} + 1488 .LCFI30: + 1489 .cfi_def_cfa_offset 12 + 1490 .cfi_offset 4, -12 + 1491 .cfi_offset 5, -8 + 1492 .cfi_offset 14, -4 + 1493 0002 87B0 sub sp, sp, #28 + 1494 .LCFI31: + 1495 .cfi_def_cfa_offset 40 + 1496 0004 0446 mov r4, r0 + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 1497 .loc 1 703 3 is_stmt 1 view .LVU444 + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1498 .loc 1 704 3 view .LVU445 + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END; + 1499 .loc 1 707 3 view .LVU446 + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END; + 1500 .loc 1 707 34 is_stmt 0 view .LVU447 + 1501 0006 0191 str r1, [sp, #4] + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1502 .loc 1 708 3 is_stmt 1 view .LVU448 + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1503 .loc 1 708 34 is_stmt 0 view .LVU449 + 1504 0008 2425 movs r5, #36 + 1505 000a 0295 str r5, [sp, #8] + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1506 .loc 1 709 3 is_stmt 1 view .LVU450 + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1507 .loc 1 709 34 is_stmt 0 view .LVU451 + 1508 000c 4023 movs r3, #64 + 1509 000e 0393 str r3, [sp, #12] + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1510 .loc 1 710 3 is_stmt 1 view .LVU452 + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1511 .loc 1 710 34 is_stmt 0 view .LVU453 + 1512 0010 0023 movs r3, #0 + 1513 0012 0493 str r3, [sp, #16] + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1514 .loc 1 711 3 is_stmt 1 view .LVU454 + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1515 .loc 1 711 34 is_stmt 0 view .LVU455 + 1516 0014 4FF48063 mov r3, #1024 + 1517 0018 0593 str r3, [sp, #20] + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1518 .loc 1 712 3 is_stmt 1 view .LVU456 + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1519 .loc 1 712 9 is_stmt 0 view .LVU457 + 1520 001a 01A9 add r1, sp, #4 + 1521 .LVL97: + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1522 .loc 1 712 9 view .LVU458 + ARM GAS /tmp/ccPSMkLq.s page 62 + + + 1523 001c FFF7FEFF bl SDMMC_SendCommand + 1524 .LVL98: + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1525 .loc 1 715 3 is_stmt 1 view .LVU459 + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1526 .loc 1 715 16 is_stmt 0 view .LVU460 + 1527 0020 41F28832 movw r2, #5000 + 1528 0024 2946 mov r1, r5 + 1529 0026 2046 mov r0, r4 + 1530 0028 FFF7FEFF bl SDMMC_GetCmdResp1 + 1531 .LVL99: + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 1532 .loc 1 717 3 is_stmt 1 view .LVU461 + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1533 .loc 1 718 1 is_stmt 0 view .LVU462 + 1534 002c 07B0 add sp, sp, #28 + 1535 .LCFI32: + 1536 .cfi_def_cfa_offset 12 + 1537 @ sp needed + 1538 002e 30BD pop {r4, r5, pc} + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1539 .loc 1 718 1 view .LVU463 + 1540 .cfi_endproc + 1541 .LFE162: + 1543 .section .text.SDMMC_CmdErase,"ax",%progbits + 1544 .align 1 + 1545 .global SDMMC_CmdErase + 1546 .syntax unified + 1547 .thumb + 1548 .thumb_func + 1550 SDMMC_CmdErase: + 1551 .LVL100: + 1552 .LFB163: + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1553 .loc 1 726 1 is_stmt 1 view -0 + 1554 .cfi_startproc + 1555 @ args = 0, pretend = 0, frame = 24 + 1556 @ frame_needed = 0, uses_anonymous_args = 0 + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1557 .loc 1 726 1 is_stmt 0 view .LVU465 + 1558 0000 30B5 push {r4, r5, lr} + 1559 .LCFI33: + 1560 .cfi_def_cfa_offset 12 + 1561 .cfi_offset 4, -12 + 1562 .cfi_offset 5, -8 + 1563 .cfi_offset 14, -4 + 1564 0002 87B0 sub sp, sp, #28 + 1565 .LCFI34: + 1566 .cfi_def_cfa_offset 40 + 1567 0004 0446 mov r4, r0 + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 1568 .loc 1 727 3 is_stmt 1 view .LVU466 + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1569 .loc 1 728 3 view .LVU467 + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE; + 1570 .loc 1 731 3 view .LVU468 + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE; + ARM GAS /tmp/ccPSMkLq.s page 63 + + + 1571 .loc 1 731 34 is_stmt 0 view .LVU469 + 1572 0006 0023 movs r3, #0 + 1573 0008 0193 str r3, [sp, #4] + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1574 .loc 1 732 3 is_stmt 1 view .LVU470 + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1575 .loc 1 732 34 is_stmt 0 view .LVU471 + 1576 000a 2625 movs r5, #38 + 1577 000c 0295 str r5, [sp, #8] + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1578 .loc 1 733 3 is_stmt 1 view .LVU472 + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1579 .loc 1 733 34 is_stmt 0 view .LVU473 + 1580 000e 4022 movs r2, #64 + 1581 0010 0392 str r2, [sp, #12] + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1582 .loc 1 734 3 is_stmt 1 view .LVU474 + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1583 .loc 1 734 34 is_stmt 0 view .LVU475 + 1584 0012 0493 str r3, [sp, #16] + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1585 .loc 1 735 3 is_stmt 1 view .LVU476 + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1586 .loc 1 735 34 is_stmt 0 view .LVU477 + 1587 0014 4FF48063 mov r3, #1024 + 1588 0018 0593 str r3, [sp, #20] + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1589 .loc 1 736 3 is_stmt 1 view .LVU478 + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1590 .loc 1 736 9 is_stmt 0 view .LVU479 + 1591 001a 01A9 add r1, sp, #4 + 1592 001c FFF7FEFF bl SDMMC_SendCommand + 1593 .LVL101: + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1594 .loc 1 739 3 is_stmt 1 view .LVU480 + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1595 .loc 1 739 16 is_stmt 0 view .LVU481 + 1596 0020 4FF21862 movw r2, #63000 + 1597 0024 2946 mov r1, r5 + 1598 0026 2046 mov r0, r4 + 1599 0028 FFF7FEFF bl SDMMC_GetCmdResp1 + 1600 .LVL102: + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 1601 .loc 1 741 3 is_stmt 1 view .LVU482 + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1602 .loc 1 742 1 is_stmt 0 view .LVU483 + 1603 002c 07B0 add sp, sp, #28 + 1604 .LCFI35: + 1605 .cfi_def_cfa_offset 12 + 1606 @ sp needed + 1607 002e 30BD pop {r4, r5, pc} + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1608 .loc 1 742 1 view .LVU484 + 1609 .cfi_endproc + 1610 .LFE163: + 1612 .section .text.SDMMC_CmdStopTransfer,"ax",%progbits + 1613 .align 1 + ARM GAS /tmp/ccPSMkLq.s page 64 + + + 1614 .global SDMMC_CmdStopTransfer + 1615 .syntax unified + 1616 .thumb + 1617 .thumb_func + 1619 SDMMC_CmdStopTransfer: + 1620 .LVL103: + 1621 .LFB164: + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1622 .loc 1 750 1 is_stmt 1 view -0 + 1623 .cfi_startproc + 1624 @ args = 0, pretend = 0, frame = 24 + 1625 @ frame_needed = 0, uses_anonymous_args = 0 + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1626 .loc 1 750 1 is_stmt 0 view .LVU486 + 1627 0000 30B5 push {r4, r5, lr} + 1628 .LCFI36: + 1629 .cfi_def_cfa_offset 12 + 1630 .cfi_offset 4, -12 + 1631 .cfi_offset 5, -8 + 1632 .cfi_offset 14, -4 + 1633 0002 87B0 sub sp, sp, #28 + 1634 .LCFI37: + 1635 .cfi_def_cfa_offset 40 + 1636 0004 0446 mov r4, r0 + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 1637 .loc 1 751 3 is_stmt 1 view .LVU487 + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1638 .loc 1 752 3 view .LVU488 + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION; + 1639 .loc 1 755 3 view .LVU489 + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION; + 1640 .loc 1 755 34 is_stmt 0 view .LVU490 + 1641 0006 0023 movs r3, #0 + 1642 0008 0193 str r3, [sp, #4] + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1643 .loc 1 756 3 is_stmt 1 view .LVU491 + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1644 .loc 1 756 34 is_stmt 0 view .LVU492 + 1645 000a 0C25 movs r5, #12 + 1646 000c 0295 str r5, [sp, #8] + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1647 .loc 1 757 3 is_stmt 1 view .LVU493 + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1648 .loc 1 757 34 is_stmt 0 view .LVU494 + 1649 000e 4022 movs r2, #64 + 1650 0010 0392 str r2, [sp, #12] + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1651 .loc 1 758 3 is_stmt 1 view .LVU495 + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1652 .loc 1 758 34 is_stmt 0 view .LVU496 + 1653 0012 0493 str r3, [sp, #16] + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1654 .loc 1 759 3 is_stmt 1 view .LVU497 + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1655 .loc 1 759 34 is_stmt 0 view .LVU498 + 1656 0014 4FF48063 mov r3, #1024 + 1657 0018 0593 str r3, [sp, #20] + ARM GAS /tmp/ccPSMkLq.s page 65 + + + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1658 .loc 1 760 3 is_stmt 1 view .LVU499 + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1659 .loc 1 760 9 is_stmt 0 view .LVU500 + 1660 001a 01A9 add r1, sp, #4 + 1661 001c FFF7FEFF bl SDMMC_SendCommand + 1662 .LVL104: + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1663 .loc 1 763 3 is_stmt 1 view .LVU501 + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1664 .loc 1 763 16 is_stmt 0 view .LVU502 + 1665 0020 034A ldr r2, .L77 + 1666 0022 2946 mov r1, r5 + 1667 0024 2046 mov r0, r4 + 1668 0026 FFF7FEFF bl SDMMC_GetCmdResp1 + 1669 .LVL105: + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 1670 .loc 1 765 3 is_stmt 1 view .LVU503 + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1671 .loc 1 766 1 is_stmt 0 view .LVU504 + 1672 002a 07B0 add sp, sp, #28 + 1673 .LCFI38: + 1674 .cfi_def_cfa_offset 12 + 1675 @ sp needed + 1676 002c 30BD pop {r4, r5, pc} + 1677 .LVL106: + 1678 .L78: + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1679 .loc 1 766 1 view .LVU505 + 1680 002e 00BF .align 2 + 1681 .L77: + 1682 0030 00E1F505 .word 100000000 + 1683 .cfi_endproc + 1684 .LFE164: + 1686 .section .text.SDMMC_CmdSelDesel,"ax",%progbits + 1687 .align 1 + 1688 .global SDMMC_CmdSelDesel + 1689 .syntax unified + 1690 .thumb + 1691 .thumb_func + 1693 SDMMC_CmdSelDesel: + 1694 .LVL107: + 1695 .LFB165: + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1696 .loc 1 775 1 is_stmt 1 view -0 + 1697 .cfi_startproc + 1698 @ args = 0, pretend = 0, frame = 24 + 1699 @ frame_needed = 0, uses_anonymous_args = 0 + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1700 .loc 1 775 1 is_stmt 0 view .LVU507 + 1701 0000 30B5 push {r4, r5, lr} + 1702 .LCFI39: + 1703 .cfi_def_cfa_offset 12 + 1704 .cfi_offset 4, -12 + 1705 .cfi_offset 5, -8 + 1706 .cfi_offset 14, -4 + 1707 0002 87B0 sub sp, sp, #28 + ARM GAS /tmp/ccPSMkLq.s page 66 + + + 1708 .LCFI40: + 1709 .cfi_def_cfa_offset 40 + 1710 0004 0446 mov r4, r0 + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 1711 .loc 1 776 3 is_stmt 1 view .LVU508 + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1712 .loc 1 777 3 view .LVU509 + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD; + 1713 .loc 1 780 3 view .LVU510 + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD; + 1714 .loc 1 780 34 is_stmt 0 view .LVU511 + 1715 0006 0192 str r2, [sp, #4] + 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1716 .loc 1 781 3 is_stmt 1 view .LVU512 + 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1717 .loc 1 781 34 is_stmt 0 view .LVU513 + 1718 0008 0725 movs r5, #7 + 1719 000a 0295 str r5, [sp, #8] + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1720 .loc 1 782 3 is_stmt 1 view .LVU514 + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1721 .loc 1 782 34 is_stmt 0 view .LVU515 + 1722 000c 4023 movs r3, #64 + 1723 000e 0393 str r3, [sp, #12] + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1724 .loc 1 783 3 is_stmt 1 view .LVU516 + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1725 .loc 1 783 34 is_stmt 0 view .LVU517 + 1726 0010 0023 movs r3, #0 + 1727 0012 0493 str r3, [sp, #16] + 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1728 .loc 1 784 3 is_stmt 1 view .LVU518 + 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1729 .loc 1 784 34 is_stmt 0 view .LVU519 + 1730 0014 4FF48063 mov r3, #1024 + 1731 0018 0593 str r3, [sp, #20] + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1732 .loc 1 785 3 is_stmt 1 view .LVU520 + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1733 .loc 1 785 9 is_stmt 0 view .LVU521 + 1734 001a 01A9 add r1, sp, #4 + 1735 001c FFF7FEFF bl SDMMC_SendCommand + 1736 .LVL108: + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1737 .loc 1 788 3 is_stmt 1 view .LVU522 + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1738 .loc 1 788 16 is_stmt 0 view .LVU523 + 1739 0020 41F28832 movw r2, #5000 + 1740 0024 2946 mov r1, r5 + 1741 0026 2046 mov r0, r4 + 1742 0028 FFF7FEFF bl SDMMC_GetCmdResp1 + 1743 .LVL109: + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 1744 .loc 1 790 3 is_stmt 1 view .LVU524 + 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1745 .loc 1 791 1 is_stmt 0 view .LVU525 + 1746 002c 07B0 add sp, sp, #28 + ARM GAS /tmp/ccPSMkLq.s page 67 + + + 1747 .LCFI41: + 1748 .cfi_def_cfa_offset 12 + 1749 @ sp needed + 1750 002e 30BD pop {r4, r5, pc} + 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1751 .loc 1 791 1 view .LVU526 + 1752 .cfi_endproc + 1753 .LFE165: + 1755 .section .text.SDMMC_CmdAppCommand,"ax",%progbits + 1756 .align 1 + 1757 .global SDMMC_CmdAppCommand + 1758 .syntax unified + 1759 .thumb + 1760 .thumb_func + 1762 SDMMC_CmdAppCommand: + 1763 .LVL110: + 1764 .LFB168: + 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1765 .loc 1 853 1 is_stmt 1 view -0 + 1766 .cfi_startproc + 1767 @ args = 0, pretend = 0, frame = 24 + 1768 @ frame_needed = 0, uses_anonymous_args = 0 + 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1769 .loc 1 853 1 is_stmt 0 view .LVU528 + 1770 0000 30B5 push {r4, r5, lr} + 1771 .LCFI42: + 1772 .cfi_def_cfa_offset 12 + 1773 .cfi_offset 4, -12 + 1774 .cfi_offset 5, -8 + 1775 .cfi_offset 14, -4 + 1776 0002 87B0 sub sp, sp, #28 + 1777 .LCFI43: + 1778 .cfi_def_cfa_offset 40 + 1779 0004 0446 mov r4, r0 + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 1780 .loc 1 854 3 is_stmt 1 view .LVU529 + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1781 .loc 1 855 3 view .LVU530 + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD; + 1782 .loc 1 857 3 view .LVU531 + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD; + 1783 .loc 1 857 34 is_stmt 0 view .LVU532 + 1784 0006 0191 str r1, [sp, #4] + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1785 .loc 1 858 3 is_stmt 1 view .LVU533 + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1786 .loc 1 858 34 is_stmt 0 view .LVU534 + 1787 0008 3725 movs r5, #55 + 1788 000a 0295 str r5, [sp, #8] + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1789 .loc 1 859 3 is_stmt 1 view .LVU535 + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1790 .loc 1 859 34 is_stmt 0 view .LVU536 + 1791 000c 4023 movs r3, #64 + 1792 000e 0393 str r3, [sp, #12] + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1793 .loc 1 860 3 is_stmt 1 view .LVU537 + ARM GAS /tmp/ccPSMkLq.s page 68 + + + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1794 .loc 1 860 34 is_stmt 0 view .LVU538 + 1795 0010 0023 movs r3, #0 + 1796 0012 0493 str r3, [sp, #16] + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1797 .loc 1 861 3 is_stmt 1 view .LVU539 + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1798 .loc 1 861 34 is_stmt 0 view .LVU540 + 1799 0014 4FF48063 mov r3, #1024 + 1800 0018 0593 str r3, [sp, #20] + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1801 .loc 1 862 3 is_stmt 1 view .LVU541 + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1802 .loc 1 862 9 is_stmt 0 view .LVU542 + 1803 001a 01A9 add r1, sp, #4 + 1804 .LVL111: + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1805 .loc 1 862 9 view .LVU543 + 1806 001c FFF7FEFF bl SDMMC_SendCommand + 1807 .LVL112: + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1808 .loc 1 868 3 is_stmt 1 view .LVU544 + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1809 .loc 1 868 16 is_stmt 0 view .LVU545 + 1810 0020 41F28832 movw r2, #5000 + 1811 0024 2946 mov r1, r5 + 1812 0026 2046 mov r0, r4 + 1813 0028 FFF7FEFF bl SDMMC_GetCmdResp1 + 1814 .LVL113: + 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 1815 .loc 1 870 3 is_stmt 1 view .LVU546 + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1816 .loc 1 871 1 is_stmt 0 view .LVU547 + 1817 002c 07B0 add sp, sp, #28 + 1818 .LCFI44: + 1819 .cfi_def_cfa_offset 12 + 1820 @ sp needed + 1821 002e 30BD pop {r4, r5, pc} + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1822 .loc 1 871 1 view .LVU548 + 1823 .cfi_endproc + 1824 .LFE168: + 1826 .section .text.SDMMC_CmdBusWidth,"ax",%progbits + 1827 .align 1 + 1828 .global SDMMC_CmdBusWidth + 1829 .syntax unified + 1830 .thumb + 1831 .thumb_func + 1833 SDMMC_CmdBusWidth: + 1834 .LVL114: + 1835 .LFB170: + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1836 .loc 1 905 1 is_stmt 1 view -0 + 1837 .cfi_startproc + 1838 @ args = 0, pretend = 0, frame = 24 + 1839 @ frame_needed = 0, uses_anonymous_args = 0 + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + ARM GAS /tmp/ccPSMkLq.s page 69 + + + 1840 .loc 1 905 1 is_stmt 0 view .LVU550 + 1841 0000 30B5 push {r4, r5, lr} + 1842 .LCFI45: + 1843 .cfi_def_cfa_offset 12 + 1844 .cfi_offset 4, -12 + 1845 .cfi_offset 5, -8 + 1846 .cfi_offset 14, -4 + 1847 0002 87B0 sub sp, sp, #28 + 1848 .LCFI46: + 1849 .cfi_def_cfa_offset 40 + 1850 0004 0446 mov r4, r0 + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 1851 .loc 1 906 3 is_stmt 1 view .LVU551 + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1852 .loc 1 907 3 view .LVU552 + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH; + 1853 .loc 1 909 3 view .LVU553 + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH; + 1854 .loc 1 909 34 is_stmt 0 view .LVU554 + 1855 0006 0191 str r1, [sp, #4] + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1856 .loc 1 910 3 is_stmt 1 view .LVU555 + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1857 .loc 1 910 34 is_stmt 0 view .LVU556 + 1858 0008 0625 movs r5, #6 + 1859 000a 0295 str r5, [sp, #8] + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1860 .loc 1 911 3 is_stmt 1 view .LVU557 + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1861 .loc 1 911 34 is_stmt 0 view .LVU558 + 1862 000c 4023 movs r3, #64 + 1863 000e 0393 str r3, [sp, #12] + 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1864 .loc 1 912 3 is_stmt 1 view .LVU559 + 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1865 .loc 1 912 34 is_stmt 0 view .LVU560 + 1866 0010 0023 movs r3, #0 + 1867 0012 0493 str r3, [sp, #16] + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1868 .loc 1 913 3 is_stmt 1 view .LVU561 + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1869 .loc 1 913 34 is_stmt 0 view .LVU562 + 1870 0014 4FF48063 mov r3, #1024 + 1871 0018 0593 str r3, [sp, #20] + 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1872 .loc 1 914 3 is_stmt 1 view .LVU563 + 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1873 .loc 1 914 9 is_stmt 0 view .LVU564 + 1874 001a 01A9 add r1, sp, #4 + 1875 .LVL115: + 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1876 .loc 1 914 9 view .LVU565 + 1877 001c FFF7FEFF bl SDMMC_SendCommand + 1878 .LVL116: + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1879 .loc 1 917 3 is_stmt 1 view .LVU566 + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + ARM GAS /tmp/ccPSMkLq.s page 70 + + + 1880 .loc 1 917 16 is_stmt 0 view .LVU567 + 1881 0020 41F28832 movw r2, #5000 + 1882 0024 2946 mov r1, r5 + 1883 0026 2046 mov r0, r4 + 1884 0028 FFF7FEFF bl SDMMC_GetCmdResp1 + 1885 .LVL117: + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 1886 .loc 1 919 3 is_stmt 1 view .LVU568 + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1887 .loc 1 920 1 is_stmt 0 view .LVU569 + 1888 002c 07B0 add sp, sp, #28 + 1889 .LCFI47: + 1890 .cfi_def_cfa_offset 12 + 1891 @ sp needed + 1892 002e 30BD pop {r4, r5, pc} + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1893 .loc 1 920 1 view .LVU570 + 1894 .cfi_endproc + 1895 .LFE170: + 1897 .section .text.SDMMC_CmdSendSCR,"ax",%progbits + 1898 .align 1 + 1899 .global SDMMC_CmdSendSCR + 1900 .syntax unified + 1901 .thumb + 1902 .thumb_func + 1904 SDMMC_CmdSendSCR: + 1905 .LVL118: + 1906 .LFB171: + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1907 .loc 1 928 1 is_stmt 1 view -0 + 1908 .cfi_startproc + 1909 @ args = 0, pretend = 0, frame = 24 + 1910 @ frame_needed = 0, uses_anonymous_args = 0 + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1911 .loc 1 928 1 is_stmt 0 view .LVU572 + 1912 0000 30B5 push {r4, r5, lr} + 1913 .LCFI48: + 1914 .cfi_def_cfa_offset 12 + 1915 .cfi_offset 4, -12 + 1916 .cfi_offset 5, -8 + 1917 .cfi_offset 14, -4 + 1918 0002 87B0 sub sp, sp, #28 + 1919 .LCFI49: + 1920 .cfi_def_cfa_offset 40 + 1921 0004 0446 mov r4, r0 + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 1922 .loc 1 929 3 is_stmt 1 view .LVU573 + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1923 .loc 1 930 3 view .LVU574 + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR; + 1924 .loc 1 933 3 view .LVU575 + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR; + 1925 .loc 1 933 34 is_stmt 0 view .LVU576 + 1926 0006 0023 movs r3, #0 + 1927 0008 0193 str r3, [sp, #4] + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1928 .loc 1 934 3 is_stmt 1 view .LVU577 + ARM GAS /tmp/ccPSMkLq.s page 71 + + + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1929 .loc 1 934 34 is_stmt 0 view .LVU578 + 1930 000a 3325 movs r5, #51 + 1931 000c 0295 str r5, [sp, #8] + 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1932 .loc 1 935 3 is_stmt 1 view .LVU579 + 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 1933 .loc 1 935 34 is_stmt 0 view .LVU580 + 1934 000e 4022 movs r2, #64 + 1935 0010 0392 str r2, [sp, #12] + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1936 .loc 1 936 3 is_stmt 1 view .LVU581 + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 1937 .loc 1 936 34 is_stmt 0 view .LVU582 + 1938 0012 0493 str r3, [sp, #16] + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1939 .loc 1 937 3 is_stmt 1 view .LVU583 + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 1940 .loc 1 937 34 is_stmt 0 view .LVU584 + 1941 0014 4FF48063 mov r3, #1024 + 1942 0018 0593 str r3, [sp, #20] + 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1943 .loc 1 938 3 is_stmt 1 view .LVU585 + 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1944 .loc 1 938 9 is_stmt 0 view .LVU586 + 1945 001a 01A9 add r1, sp, #4 + 1946 001c FFF7FEFF bl SDMMC_SendCommand + 1947 .LVL119: + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1948 .loc 1 941 3 is_stmt 1 view .LVU587 + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1949 .loc 1 941 16 is_stmt 0 view .LVU588 + 1950 0020 41F28832 movw r2, #5000 + 1951 0024 2946 mov r1, r5 + 1952 0026 2046 mov r0, r4 + 1953 0028 FFF7FEFF bl SDMMC_GetCmdResp1 + 1954 .LVL120: + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 1955 .loc 1 943 3 is_stmt 1 view .LVU589 + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1956 .loc 1 944 1 is_stmt 0 view .LVU590 + 1957 002c 07B0 add sp, sp, #28 + 1958 .LCFI50: + 1959 .cfi_def_cfa_offset 12 + 1960 @ sp needed + 1961 002e 30BD pop {r4, r5, pc} + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1962 .loc 1 944 1 view .LVU591 + 1963 .cfi_endproc + 1964 .LFE171: + 1966 .section .text.SDMMC_CmdSetRelAddMmc,"ax",%progbits + 1967 .align 1 + 1968 .global SDMMC_CmdSetRelAddMmc + 1969 .syntax unified + 1970 .thumb + 1971 .thumb_func + 1973 SDMMC_CmdSetRelAddMmc: + ARM GAS /tmp/ccPSMkLq.s page 72 + + + 1974 .LVL121: + 1975 .LFB175: +1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1976 .loc 1 1027 1 is_stmt 1 view -0 + 1977 .cfi_startproc + 1978 @ args = 0, pretend = 0, frame = 24 + 1979 @ frame_needed = 0, uses_anonymous_args = 0 +1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 1980 .loc 1 1027 1 is_stmt 0 view .LVU593 + 1981 0000 30B5 push {r4, r5, lr} + 1982 .LCFI51: + 1983 .cfi_def_cfa_offset 12 + 1984 .cfi_offset 4, -12 + 1985 .cfi_offset 5, -8 + 1986 .cfi_offset 14, -4 + 1987 0002 87B0 sub sp, sp, #28 + 1988 .LCFI52: + 1989 .cfi_def_cfa_offset 40 + 1990 0004 0446 mov r4, r0 +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 1991 .loc 1 1028 3 is_stmt 1 view .LVU594 +1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 1992 .loc 1 1029 3 view .LVU595 +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; + 1993 .loc 1 1032 3 view .LVU596 +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; + 1994 .loc 1 1032 51 is_stmt 0 view .LVU597 + 1995 0006 0904 lsls r1, r1, #16 + 1996 .LVL122: +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; + 1997 .loc 1 1032 34 view .LVU598 + 1998 0008 0191 str r1, [sp, #4] +1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 1999 .loc 1 1033 3 is_stmt 1 view .LVU599 +1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 2000 .loc 1 1033 34 is_stmt 0 view .LVU600 + 2001 000a 0325 movs r5, #3 + 2002 000c 0295 str r5, [sp, #8] +1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 2003 .loc 1 1034 3 is_stmt 1 view .LVU601 +1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 2004 .loc 1 1034 34 is_stmt 0 view .LVU602 + 2005 000e 4023 movs r3, #64 + 2006 0010 0393 str r3, [sp, #12] +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 2007 .loc 1 1035 3 is_stmt 1 view .LVU603 +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 2008 .loc 1 1035 34 is_stmt 0 view .LVU604 + 2009 0012 0023 movs r3, #0 + 2010 0014 0493 str r3, [sp, #16] +1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 2011 .loc 1 1036 3 is_stmt 1 view .LVU605 +1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 2012 .loc 1 1036 34 is_stmt 0 view .LVU606 + 2013 0016 4FF48063 mov r3, #1024 + 2014 001a 0593 str r3, [sp, #20] +1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + ARM GAS /tmp/ccPSMkLq.s page 73 + + + 2015 .loc 1 1037 3 is_stmt 1 view .LVU607 +1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2016 .loc 1 1037 9 is_stmt 0 view .LVU608 + 2017 001c 01A9 add r1, sp, #4 + 2018 001e FFF7FEFF bl SDMMC_SendCommand + 2019 .LVL123: +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2020 .loc 1 1040 3 is_stmt 1 view .LVU609 +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2021 .loc 1 1040 16 is_stmt 0 view .LVU610 + 2022 0022 41F28832 movw r2, #5000 + 2023 0026 2946 mov r1, r5 + 2024 0028 2046 mov r0, r4 + 2025 002a FFF7FEFF bl SDMMC_GetCmdResp1 + 2026 .LVL124: +1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2027 .loc 1 1042 3 is_stmt 1 view .LVU611 +1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2028 .loc 1 1043 1 is_stmt 0 view .LVU612 + 2029 002e 07B0 add sp, sp, #28 + 2030 .LCFI53: + 2031 .cfi_def_cfa_offset 12 + 2032 @ sp needed + 2033 0030 30BD pop {r4, r5, pc} +1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2034 .loc 1 1043 1 view .LVU613 + 2035 .cfi_endproc + 2036 .LFE175: + 2038 .section .text.SDMMC_CmdSendStatus,"ax",%progbits + 2039 .align 1 + 2040 .global SDMMC_CmdSendStatus + 2041 .syntax unified + 2042 .thumb + 2043 .thumb_func + 2045 SDMMC_CmdSendStatus: + 2046 .LVL125: + 2047 .LFB176: +1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 2048 .loc 1 1052 1 is_stmt 1 view -0 + 2049 .cfi_startproc + 2050 @ args = 0, pretend = 0, frame = 24 + 2051 @ frame_needed = 0, uses_anonymous_args = 0 +1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 2052 .loc 1 1052 1 is_stmt 0 view .LVU615 + 2053 0000 30B5 push {r4, r5, lr} + 2054 .LCFI54: + 2055 .cfi_def_cfa_offset 12 + 2056 .cfi_offset 4, -12 + 2057 .cfi_offset 5, -8 + 2058 .cfi_offset 14, -4 + 2059 0002 87B0 sub sp, sp, #28 + 2060 .LCFI55: + 2061 .cfi_def_cfa_offset 40 + 2062 0004 0446 mov r4, r0 +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 2063 .loc 1 1053 3 is_stmt 1 view .LVU616 +1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + ARM GAS /tmp/ccPSMkLq.s page 74 + + + 2064 .loc 1 1054 3 view .LVU617 +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS; + 2065 .loc 1 1056 3 view .LVU618 +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS; + 2066 .loc 1 1056 34 is_stmt 0 view .LVU619 + 2067 0006 0191 str r1, [sp, #4] +1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 2068 .loc 1 1057 3 is_stmt 1 view .LVU620 +1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 2069 .loc 1 1057 34 is_stmt 0 view .LVU621 + 2070 0008 0D25 movs r5, #13 + 2071 000a 0295 str r5, [sp, #8] +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 2072 .loc 1 1058 3 is_stmt 1 view .LVU622 +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 2073 .loc 1 1058 34 is_stmt 0 view .LVU623 + 2074 000c 4023 movs r3, #64 + 2075 000e 0393 str r3, [sp, #12] +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 2076 .loc 1 1059 3 is_stmt 1 view .LVU624 +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 2077 .loc 1 1059 34 is_stmt 0 view .LVU625 + 2078 0010 0023 movs r3, #0 + 2079 0012 0493 str r3, [sp, #16] +1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 2080 .loc 1 1060 3 is_stmt 1 view .LVU626 +1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 2081 .loc 1 1060 34 is_stmt 0 view .LVU627 + 2082 0014 4FF48063 mov r3, #1024 + 2083 0018 0593 str r3, [sp, #20] +1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2084 .loc 1 1061 3 is_stmt 1 view .LVU628 +1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2085 .loc 1 1061 9 is_stmt 0 view .LVU629 + 2086 001a 01A9 add r1, sp, #4 + 2087 .LVL126: +1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2088 .loc 1 1061 9 view .LVU630 + 2089 001c FFF7FEFF bl SDMMC_SendCommand + 2090 .LVL127: +1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2091 .loc 1 1064 3 is_stmt 1 view .LVU631 +1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2092 .loc 1 1064 16 is_stmt 0 view .LVU632 + 2093 0020 41F28832 movw r2, #5000 + 2094 0024 2946 mov r1, r5 + 2095 0026 2046 mov r0, r4 + 2096 0028 FFF7FEFF bl SDMMC_GetCmdResp1 + 2097 .LVL128: +1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2098 .loc 1 1066 3 is_stmt 1 view .LVU633 +1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2099 .loc 1 1067 1 is_stmt 0 view .LVU634 + 2100 002c 07B0 add sp, sp, #28 + 2101 .LCFI56: + 2102 .cfi_def_cfa_offset 12 + 2103 @ sp needed + ARM GAS /tmp/ccPSMkLq.s page 75 + + + 2104 002e 30BD pop {r4, r5, pc} +1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2105 .loc 1 1067 1 view .LVU635 + 2106 .cfi_endproc + 2107 .LFE176: + 2109 .section .text.SDMMC_CmdStatusRegister,"ax",%progbits + 2110 .align 1 + 2111 .global SDMMC_CmdStatusRegister + 2112 .syntax unified + 2113 .thumb + 2114 .thumb_func + 2116 SDMMC_CmdStatusRegister: + 2117 .LVL129: + 2118 .LFB177: +1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 2119 .loc 1 1075 1 is_stmt 1 view -0 + 2120 .cfi_startproc + 2121 @ args = 0, pretend = 0, frame = 24 + 2122 @ frame_needed = 0, uses_anonymous_args = 0 +1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 2123 .loc 1 1075 1 is_stmt 0 view .LVU637 + 2124 0000 30B5 push {r4, r5, lr} + 2125 .LCFI57: + 2126 .cfi_def_cfa_offset 12 + 2127 .cfi_offset 4, -12 + 2128 .cfi_offset 5, -8 + 2129 .cfi_offset 14, -4 + 2130 0002 87B0 sub sp, sp, #28 + 2131 .LCFI58: + 2132 .cfi_def_cfa_offset 40 + 2133 0004 0446 mov r4, r0 +1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 2134 .loc 1 1076 3 is_stmt 1 view .LVU638 +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2135 .loc 1 1077 3 view .LVU639 +1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS; + 2136 .loc 1 1079 3 view .LVU640 +1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS; + 2137 .loc 1 1079 34 is_stmt 0 view .LVU641 + 2138 0006 0023 movs r3, #0 + 2139 0008 0193 str r3, [sp, #4] +1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 2140 .loc 1 1080 3 is_stmt 1 view .LVU642 +1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 2141 .loc 1 1080 34 is_stmt 0 view .LVU643 + 2142 000a 0D25 movs r5, #13 + 2143 000c 0295 str r5, [sp, #8] +1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 2144 .loc 1 1081 3 is_stmt 1 view .LVU644 +1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 2145 .loc 1 1081 34 is_stmt 0 view .LVU645 + 2146 000e 4022 movs r2, #64 + 2147 0010 0392 str r2, [sp, #12] +1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 2148 .loc 1 1082 3 is_stmt 1 view .LVU646 +1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 2149 .loc 1 1082 34 is_stmt 0 view .LVU647 + ARM GAS /tmp/ccPSMkLq.s page 76 + + + 2150 0012 0493 str r3, [sp, #16] +1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 2151 .loc 1 1083 3 is_stmt 1 view .LVU648 +1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 2152 .loc 1 1083 34 is_stmt 0 view .LVU649 + 2153 0014 4FF48063 mov r3, #1024 + 2154 0018 0593 str r3, [sp, #20] +1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2155 .loc 1 1084 3 is_stmt 1 view .LVU650 +1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2156 .loc 1 1084 9 is_stmt 0 view .LVU651 + 2157 001a 01A9 add r1, sp, #4 + 2158 001c FFF7FEFF bl SDMMC_SendCommand + 2159 .LVL130: +1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2160 .loc 1 1087 3 is_stmt 1 view .LVU652 +1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2161 .loc 1 1087 16 is_stmt 0 view .LVU653 + 2162 0020 41F28832 movw r2, #5000 + 2163 0024 2946 mov r1, r5 + 2164 0026 2046 mov r0, r4 + 2165 0028 FFF7FEFF bl SDMMC_GetCmdResp1 + 2166 .LVL131: +1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2167 .loc 1 1089 3 is_stmt 1 view .LVU654 +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2168 .loc 1 1090 1 is_stmt 0 view .LVU655 + 2169 002c 07B0 add sp, sp, #28 + 2170 .LCFI59: + 2171 .cfi_def_cfa_offset 12 + 2172 @ sp needed + 2173 002e 30BD pop {r4, r5, pc} +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2174 .loc 1 1090 1 view .LVU656 + 2175 .cfi_endproc + 2176 .LFE177: + 2178 .section .text.SDMMC_CmdSwitch,"ax",%progbits + 2179 .align 1 + 2180 .global SDMMC_CmdSwitch + 2181 .syntax unified + 2182 .thumb + 2183 .thumb_func + 2185 SDMMC_CmdSwitch: + 2186 .LVL132: + 2187 .LFB179: +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 2188 .loc 1 1124 1 is_stmt 1 view -0 + 2189 .cfi_startproc + 2190 @ args = 0, pretend = 0, frame = 24 + 2191 @ frame_needed = 0, uses_anonymous_args = 0 +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 2192 .loc 1 1124 1 is_stmt 0 view .LVU658 + 2193 0000 30B5 push {r4, r5, lr} + 2194 .LCFI60: + 2195 .cfi_def_cfa_offset 12 + 2196 .cfi_offset 4, -12 + 2197 .cfi_offset 5, -8 + ARM GAS /tmp/ccPSMkLq.s page 77 + + + 2198 .cfi_offset 14, -4 + 2199 0002 87B0 sub sp, sp, #28 + 2200 .LCFI61: + 2201 .cfi_def_cfa_offset 40 + 2202 0004 0446 mov r4, r0 +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 2203 .loc 1 1125 3 is_stmt 1 view .LVU659 +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2204 .loc 1 1126 3 view .LVU660 +1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH; + 2205 .loc 1 1130 3 view .LVU661 +1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH; + 2206 .loc 1 1130 34 is_stmt 0 view .LVU662 + 2207 0006 0191 str r1, [sp, #4] +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 2208 .loc 1 1131 3 is_stmt 1 view .LVU663 +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 2209 .loc 1 1131 34 is_stmt 0 view .LVU664 + 2210 0008 0625 movs r5, #6 + 2211 000a 0295 str r5, [sp, #8] +1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 2212 .loc 1 1132 3 is_stmt 1 view .LVU665 +1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 2213 .loc 1 1132 34 is_stmt 0 view .LVU666 + 2214 000c 4023 movs r3, #64 + 2215 000e 0393 str r3, [sp, #12] +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 2216 .loc 1 1133 3 is_stmt 1 view .LVU667 +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 2217 .loc 1 1133 34 is_stmt 0 view .LVU668 + 2218 0010 0023 movs r3, #0 + 2219 0012 0493 str r3, [sp, #16] +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 2220 .loc 1 1134 3 is_stmt 1 view .LVU669 +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 2221 .loc 1 1134 34 is_stmt 0 view .LVU670 + 2222 0014 4FF48063 mov r3, #1024 + 2223 0018 0593 str r3, [sp, #20] +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2224 .loc 1 1135 3 is_stmt 1 view .LVU671 +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2225 .loc 1 1135 9 is_stmt 0 view .LVU672 + 2226 001a 01A9 add r1, sp, #4 + 2227 .LVL133: +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2228 .loc 1 1135 9 view .LVU673 + 2229 001c FFF7FEFF bl SDMMC_SendCommand + 2230 .LVL134: +1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2231 .loc 1 1138 3 is_stmt 1 view .LVU674 +1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2232 .loc 1 1138 16 is_stmt 0 view .LVU675 + 2233 0020 41F28832 movw r2, #5000 + 2234 0024 2946 mov r1, r5 + 2235 0026 2046 mov r0, r4 + 2236 0028 FFF7FEFF bl SDMMC_GetCmdResp1 + 2237 .LVL135: + ARM GAS /tmp/ccPSMkLq.s page 78 + + +1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2238 .loc 1 1140 3 is_stmt 1 view .LVU676 +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2239 .loc 1 1141 1 is_stmt 0 view .LVU677 + 2240 002c 07B0 add sp, sp, #28 + 2241 .LCFI62: + 2242 .cfi_def_cfa_offset 12 + 2243 @ sp needed + 2244 002e 30BD pop {r4, r5, pc} +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2245 .loc 1 1141 1 view .LVU678 + 2246 .cfi_endproc + 2247 .LFE179: + 2249 .section .text.SDMMC_CmdSendEXTCSD,"ax",%progbits + 2250 .align 1 + 2251 .global SDMMC_CmdSendEXTCSD + 2252 .syntax unified + 2253 .thumb + 2254 .thumb_func + 2256 SDMMC_CmdSendEXTCSD: + 2257 .LVL136: + 2258 .LFB180: +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 2259 .loc 1 1150 1 is_stmt 1 view -0 + 2260 .cfi_startproc + 2261 @ args = 0, pretend = 0, frame = 24 + 2262 @ frame_needed = 0, uses_anonymous_args = 0 +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 2263 .loc 1 1150 1 is_stmt 0 view .LVU680 + 2264 0000 30B5 push {r4, r5, lr} + 2265 .LCFI63: + 2266 .cfi_def_cfa_offset 12 + 2267 .cfi_offset 4, -12 + 2268 .cfi_offset 5, -8 + 2269 .cfi_offset 14, -4 + 2270 0002 87B0 sub sp, sp, #28 + 2271 .LCFI64: + 2272 .cfi_def_cfa_offset 40 + 2273 0004 0446 mov r4, r0 +1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 2274 .loc 1 1151 3 is_stmt 1 view .LVU681 +1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2275 .loc 1 1152 3 view .LVU682 +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; + 2276 .loc 1 1155 3 view .LVU683 +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; + 2277 .loc 1 1155 34 is_stmt 0 view .LVU684 + 2278 0006 0191 str r1, [sp, #4] +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 2279 .loc 1 1156 3 is_stmt 1 view .LVU685 +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 2280 .loc 1 1156 34 is_stmt 0 view .LVU686 + 2281 0008 0825 movs r5, #8 + 2282 000a 0295 str r5, [sp, #8] +1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 2283 .loc 1 1157 3 is_stmt 1 view .LVU687 +1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + ARM GAS /tmp/ccPSMkLq.s page 79 + + + 2284 .loc 1 1157 34 is_stmt 0 view .LVU688 + 2285 000c 4023 movs r3, #64 + 2286 000e 0393 str r3, [sp, #12] +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 2287 .loc 1 1158 3 is_stmt 1 view .LVU689 +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 2288 .loc 1 1158 34 is_stmt 0 view .LVU690 + 2289 0010 0023 movs r3, #0 + 2290 0012 0493 str r3, [sp, #16] +1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 2291 .loc 1 1159 3 is_stmt 1 view .LVU691 +1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 2292 .loc 1 1159 34 is_stmt 0 view .LVU692 + 2293 0014 4FF48063 mov r3, #1024 + 2294 0018 0593 str r3, [sp, #20] +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2295 .loc 1 1160 3 is_stmt 1 view .LVU693 +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2296 .loc 1 1160 9 is_stmt 0 view .LVU694 + 2297 001a 01A9 add r1, sp, #4 + 2298 .LVL137: +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2299 .loc 1 1160 9 view .LVU695 + 2300 001c FFF7FEFF bl SDMMC_SendCommand + 2301 .LVL138: +1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2302 .loc 1 1163 3 is_stmt 1 view .LVU696 +1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2303 .loc 1 1163 16 is_stmt 0 view .LVU697 + 2304 0020 41F28832 movw r2, #5000 + 2305 0024 2946 mov r1, r5 + 2306 0026 2046 mov r0, r4 + 2307 0028 FFF7FEFF bl SDMMC_GetCmdResp1 + 2308 .LVL139: +1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2309 .loc 1 1165 3 is_stmt 1 view .LVU698 +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2310 .loc 1 1166 1 is_stmt 0 view .LVU699 + 2311 002c 07B0 add sp, sp, #28 + 2312 .LCFI65: + 2313 .cfi_def_cfa_offset 12 + 2314 @ sp needed + 2315 002e 30BD pop {r4, r5, pc} +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2316 .loc 1 1166 1 view .LVU700 + 2317 .cfi_endproc + 2318 .LFE180: + 2320 .section .text.SDMMC_GetCmdResp2,"ax",%progbits + 2321 .align 1 + 2322 .global SDMMC_GetCmdResp2 + 2323 .syntax unified + 2324 .thumb + 2325 .thumb_func + 2327 SDMMC_GetCmdResp2: + 2328 .LVL140: + 2329 .LFB182: +1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t sta_reg; + ARM GAS /tmp/ccPSMkLq.s page 80 + + + 2330 .loc 1 1327 1 is_stmt 1 view -0 + 2331 .cfi_startproc + 2332 @ args = 0, pretend = 0, frame = 0 + 2333 @ frame_needed = 0, uses_anonymous_args = 0 + 2334 @ link register save eliminated. +1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t sta_reg; + 2335 .loc 1 1327 1 is_stmt 0 view .LVU702 + 2336 0000 0146 mov r1, r0 +1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* 8 is the number of required instructions cycles for the below loop statement. + 2337 .loc 1 1328 3 is_stmt 1 view .LVU703 +1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2338 .loc 1 1331 3 view .LVU704 +1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2339 .loc 1 1331 61 is_stmt 0 view .LVU705 + 2340 0002 144B ldr r3, .L105 + 2341 0004 1B68 ldr r3, [r3] + 2342 0006 144A ldr r2, .L105+4 + 2343 0008 A2FB0323 umull r2, r3, r2, r3 + 2344 000c 5B0A lsrs r3, r3, #9 +1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2345 .loc 1 1331 12 view .LVU706 + 2346 000e 41F28832 movw r2, #5000 + 2347 0012 02FB03F3 mul r3, r2, r3 + 2348 .LVL141: + 2349 .L99: +1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2350 .loc 1 1333 3 is_stmt 1 view .LVU707 +1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2351 .loc 1 1335 5 view .LVU708 + 2352 0016 1A46 mov r2, r3 +1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2353 .loc 1 1335 14 is_stmt 0 view .LVU709 + 2354 0018 013B subs r3, r3, #1 + 2355 .LVL142: +1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2356 .loc 1 1335 8 view .LVU710 + 2357 001a BAB1 cbz r2, .L102 +1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + 2358 .loc 1 1339 5 is_stmt 1 view .LVU711 +1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + 2359 .loc 1 1339 13 is_stmt 0 view .LVU712 + 2360 001c 4A6B ldr r2, [r1, #52] + 2361 .LVL143: +1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + 2362 .loc 1 1340 95 is_stmt 1 view .LVU713 + 2363 001e 12F0450F tst r2, #69 + 2364 0022 F8D0 beq .L99 +1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + 2365 .loc 1 1340 95 is_stmt 0 discriminator 1 view .LVU714 + 2366 0024 12F4006F tst r2, #2048 + 2367 0028 F5D1 bne .L99 +1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2368 .loc 1 1343 3 is_stmt 1 view .LVU715 +1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2369 .loc 1 1343 7 is_stmt 0 view .LVU716 + 2370 002a 4B6B ldr r3, [r1, #52] + 2371 .LVL144: + ARM GAS /tmp/ccPSMkLq.s page 81 + + +1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2372 .loc 1 1343 6 view .LVU717 + 2373 002c 13F0040F tst r3, #4 + 2374 0030 06D1 bne .L103 +1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2375 .loc 1 1349 8 is_stmt 1 view .LVU718 +1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2376 .loc 1 1349 12 is_stmt 0 view .LVU719 + 2377 0032 486B ldr r0, [r1, #52] + 2378 .LVL145: +1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2379 .loc 1 1349 11 view .LVU720 + 2380 0034 10F00100 ands r0, r0, #1 + 2381 0038 05D1 bne .L104 +1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2382 .loc 1 1359 5 is_stmt 1 view .LVU721 + 2383 003a C523 movs r3, #197 + 2384 003c 8B63 str r3, [r1, #56] +1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2385 .loc 1 1362 3 view .LVU722 +1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2386 .loc 1 1362 10 is_stmt 0 view .LVU723 + 2387 003e 7047 bx lr + 2388 .LVL146: + 2389 .L103: +1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2390 .loc 1 1345 5 is_stmt 1 view .LVU724 + 2391 0040 0420 movs r0, #4 + 2392 .LVL147: +1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2393 .loc 1 1345 5 is_stmt 0 view .LVU725 + 2394 0042 8863 str r0, [r1, #56] +1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2395 .loc 1 1347 5 is_stmt 1 view .LVU726 +1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2396 .loc 1 1347 12 is_stmt 0 view .LVU727 + 2397 0044 7047 bx lr + 2398 .L104: +1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2399 .loc 1 1351 5 is_stmt 1 view .LVU728 + 2400 0046 0120 movs r0, #1 + 2401 0048 8863 str r0, [r1, #56] +1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2402 .loc 1 1353 5 view .LVU729 +1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2403 .loc 1 1353 12 is_stmt 0 view .LVU730 + 2404 004a 7047 bx lr + 2405 .LVL148: + 2406 .L102: +1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2407 .loc 1 1337 14 view .LVU731 + 2408 004c 4FF00040 mov r0, #-2147483648 + 2409 .LVL149: +1363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2410 .loc 1 1363 1 view .LVU732 + 2411 0050 7047 bx lr + 2412 .L106: + ARM GAS /tmp/ccPSMkLq.s page 82 + + + 2413 0052 00BF .align 2 + 2414 .L105: + 2415 0054 00000000 .word SystemCoreClock + 2416 0058 D34D6210 .word 274877907 + 2417 .cfi_endproc + 2418 .LFE182: + 2420 .section .text.SDMMC_CmdSendCID,"ax",%progbits + 2421 .align 1 + 2422 .global SDMMC_CmdSendCID + 2423 .syntax unified + 2424 .thumb + 2425 .thumb_func + 2427 SDMMC_CmdSendCID: + 2428 .LVL150: + 2429 .LFB172: + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 2430 .loc 1 952 1 is_stmt 1 view -0 + 2431 .cfi_startproc + 2432 @ args = 0, pretend = 0, frame = 24 + 2433 @ frame_needed = 0, uses_anonymous_args = 0 + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 2434 .loc 1 952 1 is_stmt 0 view .LVU734 + 2435 0000 10B5 push {r4, lr} + 2436 .LCFI66: + 2437 .cfi_def_cfa_offset 8 + 2438 .cfi_offset 4, -8 + 2439 .cfi_offset 14, -4 + 2440 0002 86B0 sub sp, sp, #24 + 2441 .LCFI67: + 2442 .cfi_def_cfa_offset 32 + 2443 0004 0446 mov r4, r0 + 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 2444 .loc 1 953 3 is_stmt 1 view .LVU735 + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2445 .loc 1 954 3 view .LVU736 + 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID; + 2446 .loc 1 957 3 view .LVU737 + 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID; + 2447 .loc 1 957 34 is_stmt 0 view .LVU738 + 2448 0006 0023 movs r3, #0 + 2449 0008 0193 str r3, [sp, #4] + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; + 2450 .loc 1 958 3 is_stmt 1 view .LVU739 + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; + 2451 .loc 1 958 34 is_stmt 0 view .LVU740 + 2452 000a 0222 movs r2, #2 + 2453 000c 0292 str r2, [sp, #8] + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 2454 .loc 1 959 3 is_stmt 1 view .LVU741 + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 2455 .loc 1 959 34 is_stmt 0 view .LVU742 + 2456 000e C022 movs r2, #192 + 2457 0010 0392 str r2, [sp, #12] + 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 2458 .loc 1 960 3 is_stmt 1 view .LVU743 + 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 2459 .loc 1 960 34 is_stmt 0 view .LVU744 + ARM GAS /tmp/ccPSMkLq.s page 83 + + + 2460 0012 0493 str r3, [sp, #16] + 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 2461 .loc 1 961 3 is_stmt 1 view .LVU745 + 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 2462 .loc 1 961 34 is_stmt 0 view .LVU746 + 2463 0014 4FF48063 mov r3, #1024 + 2464 0018 0593 str r3, [sp, #20] + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2465 .loc 1 962 3 is_stmt 1 view .LVU747 + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2466 .loc 1 962 9 is_stmt 0 view .LVU748 + 2467 001a 01A9 add r1, sp, #4 + 2468 001c FFF7FEFF bl SDMMC_SendCommand + 2469 .LVL151: + 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2470 .loc 1 965 3 is_stmt 1 view .LVU749 + 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2471 .loc 1 965 16 is_stmt 0 view .LVU750 + 2472 0020 2046 mov r0, r4 + 2473 0022 FFF7FEFF bl SDMMC_GetCmdResp2 + 2474 .LVL152: + 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2475 .loc 1 967 3 is_stmt 1 view .LVU751 + 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2476 .loc 1 968 1 is_stmt 0 view .LVU752 + 2477 0026 06B0 add sp, sp, #24 + 2478 .LCFI68: + 2479 .cfi_def_cfa_offset 8 + 2480 @ sp needed + 2481 0028 10BD pop {r4, pc} + 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2482 .loc 1 968 1 view .LVU753 + 2483 .cfi_endproc + 2484 .LFE172: + 2486 .section .text.SDMMC_CmdSendCSD,"ax",%progbits + 2487 .align 1 + 2488 .global SDMMC_CmdSendCSD + 2489 .syntax unified + 2490 .thumb + 2491 .thumb_func + 2493 SDMMC_CmdSendCSD: + 2494 .LVL153: + 2495 .LFB173: + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 2496 .loc 1 977 1 is_stmt 1 view -0 + 2497 .cfi_startproc + 2498 @ args = 0, pretend = 0, frame = 24 + 2499 @ frame_needed = 0, uses_anonymous_args = 0 + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 2500 .loc 1 977 1 is_stmt 0 view .LVU755 + 2501 0000 10B5 push {r4, lr} + 2502 .LCFI69: + 2503 .cfi_def_cfa_offset 8 + 2504 .cfi_offset 4, -8 + 2505 .cfi_offset 14, -4 + 2506 0002 86B0 sub sp, sp, #24 + 2507 .LCFI70: + ARM GAS /tmp/ccPSMkLq.s page 84 + + + 2508 .cfi_def_cfa_offset 32 + 2509 0004 0446 mov r4, r0 + 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 2510 .loc 1 978 3 is_stmt 1 view .LVU756 + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2511 .loc 1 979 3 view .LVU757 + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD; + 2512 .loc 1 982 3 view .LVU758 + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD; + 2513 .loc 1 982 34 is_stmt 0 view .LVU759 + 2514 0006 0191 str r1, [sp, #4] + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; + 2515 .loc 1 983 3 is_stmt 1 view .LVU760 + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; + 2516 .loc 1 983 34 is_stmt 0 view .LVU761 + 2517 0008 0923 movs r3, #9 + 2518 000a 0293 str r3, [sp, #8] + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 2519 .loc 1 984 3 is_stmt 1 view .LVU762 + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 2520 .loc 1 984 34 is_stmt 0 view .LVU763 + 2521 000c C023 movs r3, #192 + 2522 000e 0393 str r3, [sp, #12] + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 2523 .loc 1 985 3 is_stmt 1 view .LVU764 + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 2524 .loc 1 985 34 is_stmt 0 view .LVU765 + 2525 0010 0023 movs r3, #0 + 2526 0012 0493 str r3, [sp, #16] + 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 2527 .loc 1 986 3 is_stmt 1 view .LVU766 + 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 2528 .loc 1 986 34 is_stmt 0 view .LVU767 + 2529 0014 4FF48063 mov r3, #1024 + 2530 0018 0593 str r3, [sp, #20] + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2531 .loc 1 987 3 is_stmt 1 view .LVU768 + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2532 .loc 1 987 9 is_stmt 0 view .LVU769 + 2533 001a 01A9 add r1, sp, #4 + 2534 .LVL154: + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2535 .loc 1 987 9 view .LVU770 + 2536 001c FFF7FEFF bl SDMMC_SendCommand + 2537 .LVL155: + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2538 .loc 1 990 3 is_stmt 1 view .LVU771 + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2539 .loc 1 990 16 is_stmt 0 view .LVU772 + 2540 0020 2046 mov r0, r4 + 2541 0022 FFF7FEFF bl SDMMC_GetCmdResp2 + 2542 .LVL156: + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2543 .loc 1 992 3 is_stmt 1 view .LVU773 + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2544 .loc 1 993 1 is_stmt 0 view .LVU774 + 2545 0026 06B0 add sp, sp, #24 + ARM GAS /tmp/ccPSMkLq.s page 85 + + + 2546 .LCFI71: + 2547 .cfi_def_cfa_offset 8 + 2548 @ sp needed + 2549 0028 10BD pop {r4, pc} + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2550 .loc 1 993 1 view .LVU775 + 2551 .cfi_endproc + 2552 .LFE173: + 2554 .section .text.SDMMC_GetCmdResp3,"ax",%progbits + 2555 .align 1 + 2556 .global SDMMC_GetCmdResp3 + 2557 .syntax unified + 2558 .thumb + 2559 .thumb_func + 2561 SDMMC_GetCmdResp3: + 2562 .LVL157: + 2563 .LFB183: +1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t sta_reg; + 2564 .loc 1 1371 1 is_stmt 1 view -0 + 2565 .cfi_startproc + 2566 @ args = 0, pretend = 0, frame = 0 + 2567 @ frame_needed = 0, uses_anonymous_args = 0 + 2568 @ link register save eliminated. +1371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t sta_reg; + 2569 .loc 1 1371 1 is_stmt 0 view .LVU777 + 2570 0000 0146 mov r1, r0 +1372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* 8 is the number of required instructions cycles for the below loop statement. + 2571 .loc 1 1372 3 is_stmt 1 view .LVU778 +1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2572 .loc 1 1375 3 view .LVU779 +1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2573 .loc 1 1375 61 is_stmt 0 view .LVU780 + 2574 0002 104B ldr r3, .L117 + 2575 0004 1B68 ldr r3, [r3] + 2576 0006 104A ldr r2, .L117+4 + 2577 0008 A2FB0323 umull r2, r3, r2, r3 + 2578 000c 5B0A lsrs r3, r3, #9 +1375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2579 .loc 1 1375 12 view .LVU781 + 2580 000e 41F28832 movw r2, #5000 + 2581 0012 02FB03F3 mul r3, r2, r3 + 2582 .LVL158: + 2583 .L113: +1377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2584 .loc 1 1377 3 is_stmt 1 view .LVU782 +1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2585 .loc 1 1379 5 view .LVU783 + 2586 0016 1A46 mov r2, r3 +1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2587 .loc 1 1379 14 is_stmt 0 view .LVU784 + 2588 0018 013B subs r3, r3, #1 + 2589 .LVL159: +1379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2590 .loc 1 1379 8 view .LVU785 + 2591 001a 82B1 cbz r2, .L115 +1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + 2592 .loc 1 1383 5 is_stmt 1 view .LVU786 + ARM GAS /tmp/ccPSMkLq.s page 86 + + +1383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + 2593 .loc 1 1383 13 is_stmt 0 view .LVU787 + 2594 001c 4A6B ldr r2, [r1, #52] + 2595 .LVL160: +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + 2596 .loc 1 1384 95 is_stmt 1 view .LVU788 + 2597 001e 12F0450F tst r2, #69 + 2598 0022 F8D0 beq .L113 +1384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + 2599 .loc 1 1384 95 is_stmt 0 discriminator 1 view .LVU789 + 2600 0024 12F4006F tst r2, #2048 + 2601 0028 F5D1 bne .L113 +1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2602 .loc 1 1387 3 is_stmt 1 view .LVU790 +1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2603 .loc 1 1387 6 is_stmt 0 view .LVU791 + 2604 002a 486B ldr r0, [r1, #52] + 2605 .LVL161: +1387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2606 .loc 1 1387 5 view .LVU792 + 2607 002c 10F00400 ands r0, r0, #4 + 2608 0030 02D1 bne .L116 +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2609 .loc 1 1396 5 is_stmt 1 view .LVU793 + 2610 0032 C523 movs r3, #197 + 2611 .LVL162: +1396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2612 .loc 1 1396 5 is_stmt 0 view .LVU794 + 2613 0034 8B63 str r3, [r1, #56] +1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2614 .loc 1 1399 3 is_stmt 1 view .LVU795 +1399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2615 .loc 1 1399 10 is_stmt 0 view .LVU796 + 2616 0036 7047 bx lr + 2617 .LVL163: + 2618 .L116: +1389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2619 .loc 1 1389 5 is_stmt 1 view .LVU797 + 2620 0038 0420 movs r0, #4 + 2621 003a 8863 str r0, [r1, #56] +1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2622 .loc 1 1391 5 view .LVU798 +1391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2623 .loc 1 1391 12 is_stmt 0 view .LVU799 + 2624 003c 7047 bx lr + 2625 .LVL164: + 2626 .L115: +1381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2627 .loc 1 1381 14 view .LVU800 + 2628 003e 4FF00040 mov r0, #-2147483648 + 2629 .LVL165: +1400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2630 .loc 1 1400 1 view .LVU801 + 2631 0042 7047 bx lr + 2632 .L118: + 2633 .align 2 + 2634 .L117: + ARM GAS /tmp/ccPSMkLq.s page 87 + + + 2635 0044 00000000 .word SystemCoreClock + 2636 0048 D34D6210 .word 274877907 + 2637 .cfi_endproc + 2638 .LFE183: + 2640 .section .text.SDMMC_CmdAppOperCommand,"ax",%progbits + 2641 .align 1 + 2642 .global SDMMC_CmdAppOperCommand + 2643 .syntax unified + 2644 .thumb + 2645 .thumb_func + 2647 SDMMC_CmdAppOperCommand: + 2648 .LVL166: + 2649 .LFB169: + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 2650 .loc 1 881 1 is_stmt 1 view -0 + 2651 .cfi_startproc + 2652 @ args = 0, pretend = 0, frame = 24 + 2653 @ frame_needed = 0, uses_anonymous_args = 0 + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 2654 .loc 1 881 1 is_stmt 0 view .LVU803 + 2655 0000 10B5 push {r4, lr} + 2656 .LCFI72: + 2657 .cfi_def_cfa_offset 8 + 2658 .cfi_offset 4, -8 + 2659 .cfi_offset 14, -4 + 2660 0002 86B0 sub sp, sp, #24 + 2661 .LCFI73: + 2662 .cfi_def_cfa_offset 32 + 2663 0004 0446 mov r4, r0 + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 2664 .loc 1 882 3 is_stmt 1 view .LVU804 + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2665 .loc 1 883 3 view .LVU805 + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; + 2666 .loc 1 885 3 view .LVU806 + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; + 2667 .loc 1 885 60 is_stmt 0 view .LVU807 + 2668 0006 0A4B ldr r3, .L121 + 2669 0008 0B43 orrs r3, r3, r1 + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; + 2670 .loc 1 885 34 view .LVU808 + 2671 000a 0193 str r3, [sp, #4] + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 2672 .loc 1 886 3 is_stmt 1 view .LVU809 + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 2673 .loc 1 886 34 is_stmt 0 view .LVU810 + 2674 000c 2923 movs r3, #41 + 2675 000e 0293 str r3, [sp, #8] + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 2676 .loc 1 887 3 is_stmt 1 view .LVU811 + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 2677 .loc 1 887 34 is_stmt 0 view .LVU812 + 2678 0010 4023 movs r3, #64 + 2679 0012 0393 str r3, [sp, #12] + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 2680 .loc 1 888 3 is_stmt 1 view .LVU813 + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + ARM GAS /tmp/ccPSMkLq.s page 88 + + + 2681 .loc 1 888 34 is_stmt 0 view .LVU814 + 2682 0014 0023 movs r3, #0 + 2683 0016 0493 str r3, [sp, #16] + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 2684 .loc 1 889 3 is_stmt 1 view .LVU815 + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 2685 .loc 1 889 34 is_stmt 0 view .LVU816 + 2686 0018 4FF48063 mov r3, #1024 + 2687 001c 0593 str r3, [sp, #20] + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2688 .loc 1 890 3 is_stmt 1 view .LVU817 + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2689 .loc 1 890 9 is_stmt 0 view .LVU818 + 2690 001e 01A9 add r1, sp, #4 + 2691 .LVL167: + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2692 .loc 1 890 9 view .LVU819 + 2693 0020 FFF7FEFF bl SDMMC_SendCommand + 2694 .LVL168: + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2695 .loc 1 893 3 is_stmt 1 view .LVU820 + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2696 .loc 1 893 16 is_stmt 0 view .LVU821 + 2697 0024 2046 mov r0, r4 + 2698 0026 FFF7FEFF bl SDMMC_GetCmdResp3 + 2699 .LVL169: + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2700 .loc 1 895 3 is_stmt 1 view .LVU822 + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2701 .loc 1 896 1 is_stmt 0 view .LVU823 + 2702 002a 06B0 add sp, sp, #24 + 2703 .LCFI74: + 2704 .cfi_def_cfa_offset 8 + 2705 @ sp needed + 2706 002c 10BD pop {r4, pc} + 2707 .LVL170: + 2708 .L122: + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2709 .loc 1 896 1 view .LVU824 + 2710 002e 00BF .align 2 + 2711 .L121: + 2712 0030 00001080 .word -2146435072 + 2713 .cfi_endproc + 2714 .LFE169: + 2716 .section .text.SDMMC_CmdOpCondition,"ax",%progbits + 2717 .align 1 + 2718 .global SDMMC_CmdOpCondition + 2719 .syntax unified + 2720 .thumb + 2721 .thumb_func + 2723 SDMMC_CmdOpCondition: + 2724 .LVL171: + 2725 .LFB178: +1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 2726 .loc 1 1100 1 is_stmt 1 view -0 + 2727 .cfi_startproc + 2728 @ args = 0, pretend = 0, frame = 24 + ARM GAS /tmp/ccPSMkLq.s page 89 + + + 2729 @ frame_needed = 0, uses_anonymous_args = 0 +1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 2730 .loc 1 1100 1 is_stmt 0 view .LVU826 + 2731 0000 10B5 push {r4, lr} + 2732 .LCFI75: + 2733 .cfi_def_cfa_offset 8 + 2734 .cfi_offset 4, -8 + 2735 .cfi_offset 14, -4 + 2736 0002 86B0 sub sp, sp, #24 + 2737 .LCFI76: + 2738 .cfi_def_cfa_offset 32 + 2739 0004 0446 mov r4, r0 +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 2740 .loc 1 1101 3 is_stmt 1 view .LVU827 +1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2741 .loc 1 1102 3 view .LVU828 +1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND; + 2742 .loc 1 1104 3 view .LVU829 +1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND; + 2743 .loc 1 1104 34 is_stmt 0 view .LVU830 + 2744 0006 0191 str r1, [sp, #4] +1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 2745 .loc 1 1105 3 is_stmt 1 view .LVU831 +1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 2746 .loc 1 1105 34 is_stmt 0 view .LVU832 + 2747 0008 0123 movs r3, #1 + 2748 000a 0293 str r3, [sp, #8] +1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 2749 .loc 1 1106 3 is_stmt 1 view .LVU833 +1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 2750 .loc 1 1106 34 is_stmt 0 view .LVU834 + 2751 000c 4023 movs r3, #64 + 2752 000e 0393 str r3, [sp, #12] +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 2753 .loc 1 1107 3 is_stmt 1 view .LVU835 +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 2754 .loc 1 1107 34 is_stmt 0 view .LVU836 + 2755 0010 0023 movs r3, #0 + 2756 0012 0493 str r3, [sp, #16] +1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 2757 .loc 1 1108 3 is_stmt 1 view .LVU837 +1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 2758 .loc 1 1108 34 is_stmt 0 view .LVU838 + 2759 0014 4FF48063 mov r3, #1024 + 2760 0018 0593 str r3, [sp, #20] +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2761 .loc 1 1109 3 is_stmt 1 view .LVU839 +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2762 .loc 1 1109 9 is_stmt 0 view .LVU840 + 2763 001a 01A9 add r1, sp, #4 + 2764 .LVL172: +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2765 .loc 1 1109 9 view .LVU841 + 2766 001c FFF7FEFF bl SDMMC_SendCommand + 2767 .LVL173: +1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2768 .loc 1 1112 3 is_stmt 1 view .LVU842 + ARM GAS /tmp/ccPSMkLq.s page 90 + + +1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2769 .loc 1 1112 16 is_stmt 0 view .LVU843 + 2770 0020 2046 mov r0, r4 + 2771 0022 FFF7FEFF bl SDMMC_GetCmdResp3 + 2772 .LVL174: +1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2773 .loc 1 1114 3 is_stmt 1 view .LVU844 +1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2774 .loc 1 1115 1 is_stmt 0 view .LVU845 + 2775 0026 06B0 add sp, sp, #24 + 2776 .LCFI77: + 2777 .cfi_def_cfa_offset 8 + 2778 @ sp needed + 2779 0028 10BD pop {r4, pc} +1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2780 .loc 1 1115 1 view .LVU846 + 2781 .cfi_endproc + 2782 .LFE178: + 2784 .section .text.SDMMC_GetCmdResp6,"ax",%progbits + 2785 .align 1 + 2786 .global SDMMC_GetCmdResp6 + 2787 .syntax unified + 2788 .thumb + 2789 .thumb_func + 2791 SDMMC_GetCmdResp6: + 2792 .LVL175: + 2793 .LFB184: +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t response_r1; + 2794 .loc 1 1411 1 is_stmt 1 view -0 + 2795 .cfi_startproc + 2796 @ args = 0, pretend = 0, frame = 0 + 2797 @ frame_needed = 0, uses_anonymous_args = 0 +1411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t response_r1; + 2798 .loc 1 1411 1 is_stmt 0 view .LVU848 + 2799 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 2800 .LCFI78: + 2801 .cfi_def_cfa_offset 24 + 2802 .cfi_offset 3, -24 + 2803 .cfi_offset 4, -20 + 2804 .cfi_offset 5, -16 + 2805 .cfi_offset 6, -12 + 2806 .cfi_offset 7, -8 + 2807 .cfi_offset 14, -4 + 2808 0002 0546 mov r5, r0 + 2809 0004 0E46 mov r6, r1 + 2810 0006 1746 mov r7, r2 +1412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t sta_reg; + 2811 .loc 1 1412 3 is_stmt 1 view .LVU849 +1413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2812 .loc 1 1413 3 view .LVU850 +1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2813 .loc 1 1417 3 view .LVU851 +1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2814 .loc 1 1417 61 is_stmt 0 view .LVU852 + 2815 0008 234B ldr r3, .L139 + 2816 000a 1B68 ldr r3, [r3] + 2817 000c 234A ldr r2, .L139+4 + ARM GAS /tmp/ccPSMkLq.s page 91 + + + 2818 .LVL176: +1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2819 .loc 1 1417 61 view .LVU853 + 2820 000e A2FB0323 umull r2, r3, r2, r3 + 2821 0012 5B0A lsrs r3, r3, #9 +1417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2822 .loc 1 1417 12 view .LVU854 + 2823 0014 41F28832 movw r2, #5000 + 2824 0018 02FB03F3 mul r3, r2, r3 + 2825 .LVL177: + 2826 .L127: +1419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2827 .loc 1 1419 3 is_stmt 1 view .LVU855 +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2828 .loc 1 1421 5 view .LVU856 + 2829 001c 1A46 mov r2, r3 +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2830 .loc 1 1421 14 is_stmt 0 view .LVU857 + 2831 001e 013B subs r3, r3, #1 + 2832 .LVL178: +1421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2833 .loc 1 1421 8 view .LVU858 + 2834 0020 8AB3 cbz r2, .L131 +1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + 2835 .loc 1 1425 5 is_stmt 1 view .LVU859 +1425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + 2836 .loc 1 1425 13 is_stmt 0 view .LVU860 + 2837 0022 6C6B ldr r4, [r5, #52] + 2838 .LVL179: +1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + 2839 .loc 1 1426 95 is_stmt 1 view .LVU861 + 2840 0024 14F0450F tst r4, #69 + 2841 0028 F8D0 beq .L127 +1426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + 2842 .loc 1 1426 95 is_stmt 0 discriminator 1 view .LVU862 + 2843 002a 14F4006F tst r4, #2048 + 2844 002e F5D1 bne .L127 +1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2845 .loc 1 1429 3 is_stmt 1 view .LVU863 +1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2846 .loc 1 1429 6 is_stmt 0 view .LVU864 + 2847 0030 6B6B ldr r3, [r5, #52] + 2848 .LVL180: +1429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2849 .loc 1 1429 5 view .LVU865 + 2850 0032 13F0040F tst r3, #4 + 2851 0036 06D1 bne .L136 +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2852 .loc 1 1435 8 is_stmt 1 view .LVU866 +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2853 .loc 1 1435 11 is_stmt 0 view .LVU867 + 2854 0038 6B6B ldr r3, [r5, #52] +1435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2855 .loc 1 1435 10 view .LVU868 + 2856 003a 13F0010F tst r3, #1 + 2857 003e 05D0 beq .L129 +1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + ARM GAS /tmp/ccPSMkLq.s page 92 + + + 2858 .loc 1 1437 5 is_stmt 1 view .LVU869 + 2859 0040 0120 movs r0, #1 + 2860 .LVL181: +1437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2861 .loc 1 1437 5 is_stmt 0 view .LVU870 + 2862 0042 A863 str r0, [r5, #56] +1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2863 .loc 1 1439 5 is_stmt 1 view .LVU871 +1439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2864 .loc 1 1439 12 is_stmt 0 view .LVU872 + 2865 0044 21E0 b .L125 + 2866 .LVL182: + 2867 .L136: +1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2868 .loc 1 1431 5 is_stmt 1 view .LVU873 + 2869 0046 0420 movs r0, #4 + 2870 .LVL183: +1431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2871 .loc 1 1431 5 is_stmt 0 view .LVU874 + 2872 0048 A863 str r0, [r5, #56] +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2873 .loc 1 1433 5 is_stmt 1 view .LVU875 +1433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2874 .loc 1 1433 12 is_stmt 0 view .LVU876 + 2875 004a 1EE0 b .L125 + 2876 .LVL184: + 2877 .L129: +1444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2878 .loc 1 1444 3 is_stmt 1 view .LVU877 +1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2879 .loc 1 1447 3 view .LVU878 +1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2880 .loc 1 1447 6 is_stmt 0 view .LVU879 + 2881 004c 2846 mov r0, r5 + 2882 .LVL185: +1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2883 .loc 1 1447 6 view .LVU880 + 2884 004e FFF7FEFF bl SDMMC_GetCommandResponse + 2885 .LVL186: +1447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2886 .loc 1 1447 5 discriminator 1 view .LVU881 + 2887 0052 B042 cmp r0, r6 + 2888 0054 01D0 beq .L137 +1449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2889 .loc 1 1449 12 view .LVU882 + 2890 0056 0120 movs r0, #1 + 2891 0058 17E0 b .L125 + 2892 .L137: +1453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2893 .loc 1 1453 3 is_stmt 1 view .LVU883 + 2894 005a C523 movs r3, #197 + 2895 005c AB63 str r3, [r5, #56] +1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2896 .loc 1 1456 3 view .LVU884 +1456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2897 .loc 1 1456 17 is_stmt 0 view .LVU885 + 2898 005e 0021 movs r1, #0 + ARM GAS /tmp/ccPSMkLq.s page 93 + + + 2899 0060 2846 mov r0, r5 + 2900 0062 FFF7FEFF bl SDMMC_GetResponse + 2901 .LVL187: + 2902 0066 0346 mov r3, r0 + 2903 .LVL188: +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2904 .loc 1 1458 3 is_stmt 1 view .LVU886 +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2905 .loc 1 1458 5 is_stmt 0 view .LVU887 + 2906 0068 10F46040 ands r0, r0, #57344 + 2907 .LVL189: +1458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2908 .loc 1 1458 5 view .LVU888 + 2909 006c 08D0 beq .L138 +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2910 .loc 1 1464 8 is_stmt 1 view .LVU889 +1464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2911 .loc 1 1464 10 is_stmt 0 view .LVU890 + 2912 006e 13F4804F tst r3, #16384 + 2913 0072 0BD1 bne .L133 +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2914 .loc 1 1468 8 is_stmt 1 view .LVU891 +1468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 2915 .loc 1 1468 10 is_stmt 0 view .LVU892 + 2916 0074 13F4004F tst r3, #32768 + 2917 0078 0BD0 beq .L134 +1470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2918 .loc 1 1470 12 view .LVU893 + 2919 007a 4FF48050 mov r0, #4096 + 2920 007e 04E0 b .L125 + 2921 .L138: +1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2922 .loc 1 1460 5 is_stmt 1 view .LVU894 +1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2923 .loc 1 1460 13 is_stmt 0 view .LVU895 + 2924 0080 1B0C lsrs r3, r3, #16 + 2925 .LVL190: +1460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2926 .loc 1 1460 11 view .LVU896 + 2927 0082 3B80 strh r3, [r7] @ movhi +1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2928 .loc 1 1462 5 is_stmt 1 view .LVU897 +1462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2929 .loc 1 1462 12 is_stmt 0 view .LVU898 + 2930 0084 01E0 b .L125 + 2931 .LVL191: + 2932 .L131: +1423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2933 .loc 1 1423 14 view .LVU899 + 2934 0086 4FF00040 mov r0, #-2147483648 + 2935 .LVL192: + 2936 .L125: +1476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2937 .loc 1 1476 1 view .LVU900 + 2938 008a F8BD pop {r3, r4, r5, r6, r7, pc} + 2939 .LVL193: + 2940 .L133: + ARM GAS /tmp/ccPSMkLq.s page 94 + + +1466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2941 .loc 1 1466 12 view .LVU901 + 2942 008c 4FF40050 mov r0, #8192 + 2943 0090 FBE7 b .L125 + 2944 .L134: +1474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 2945 .loc 1 1474 12 view .LVU902 + 2946 0092 4FF48030 mov r0, #65536 + 2947 0096 F8E7 b .L125 + 2948 .L140: + 2949 .align 2 + 2950 .L139: + 2951 0098 00000000 .word SystemCoreClock + 2952 009c D34D6210 .word 274877907 + 2953 .cfi_endproc + 2954 .LFE184: + 2956 .section .text.SDMMC_CmdSetRelAdd,"ax",%progbits + 2957 .align 1 + 2958 .global SDMMC_CmdSetRelAdd + 2959 .syntax unified + 2960 .thumb + 2961 .thumb_func + 2963 SDMMC_CmdSetRelAdd: + 2964 .LVL194: + 2965 .LFB174: +1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 2966 .loc 1 1002 1 is_stmt 1 view -0 + 2967 .cfi_startproc + 2968 @ args = 0, pretend = 0, frame = 24 + 2969 @ frame_needed = 0, uses_anonymous_args = 0 +1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 2970 .loc 1 1002 1 is_stmt 0 view .LVU904 + 2971 0000 70B5 push {r4, r5, r6, lr} + 2972 .LCFI79: + 2973 .cfi_def_cfa_offset 16 + 2974 .cfi_offset 4, -16 + 2975 .cfi_offset 5, -12 + 2976 .cfi_offset 6, -8 + 2977 .cfi_offset 14, -4 + 2978 0002 86B0 sub sp, sp, #24 + 2979 .LCFI80: + 2980 .cfi_def_cfa_offset 40 + 2981 0004 0446 mov r4, r0 + 2982 0006 0D46 mov r5, r1 +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 2983 .loc 1 1003 3 is_stmt 1 view .LVU905 +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 2984 .loc 1 1004 3 view .LVU906 +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; + 2985 .loc 1 1007 3 view .LVU907 +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; + 2986 .loc 1 1007 34 is_stmt 0 view .LVU908 + 2987 0008 0023 movs r3, #0 + 2988 000a 0193 str r3, [sp, #4] +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 2989 .loc 1 1008 3 is_stmt 1 view .LVU909 +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + ARM GAS /tmp/ccPSMkLq.s page 95 + + + 2990 .loc 1 1008 34 is_stmt 0 view .LVU910 + 2991 000c 0326 movs r6, #3 + 2992 000e 0296 str r6, [sp, #8] +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 2993 .loc 1 1009 3 is_stmt 1 view .LVU911 +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 2994 .loc 1 1009 34 is_stmt 0 view .LVU912 + 2995 0010 4022 movs r2, #64 + 2996 0012 0392 str r2, [sp, #12] +1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 2997 .loc 1 1010 3 is_stmt 1 view .LVU913 +1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 2998 .loc 1 1010 34 is_stmt 0 view .LVU914 + 2999 0014 0493 str r3, [sp, #16] +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 3000 .loc 1 1011 3 is_stmt 1 view .LVU915 +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 3001 .loc 1 1011 34 is_stmt 0 view .LVU916 + 3002 0016 4FF48063 mov r3, #1024 + 3003 001a 0593 str r3, [sp, #20] +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3004 .loc 1 1012 3 is_stmt 1 view .LVU917 +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3005 .loc 1 1012 9 is_stmt 0 view .LVU918 + 3006 001c 01A9 add r1, sp, #4 + 3007 .LVL195: +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3008 .loc 1 1012 9 view .LVU919 + 3009 001e FFF7FEFF bl SDMMC_SendCommand + 3010 .LVL196: +1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3011 .loc 1 1015 3 is_stmt 1 view .LVU920 +1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3012 .loc 1 1015 16 is_stmt 0 view .LVU921 + 3013 0022 2A46 mov r2, r5 + 3014 0024 3146 mov r1, r6 + 3015 0026 2046 mov r0, r4 + 3016 0028 FFF7FEFF bl SDMMC_GetCmdResp6 + 3017 .LVL197: +1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 3018 .loc 1 1017 3 is_stmt 1 view .LVU922 +1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3019 .loc 1 1018 1 is_stmt 0 view .LVU923 + 3020 002c 06B0 add sp, sp, #24 + 3021 .LCFI81: + 3022 .cfi_def_cfa_offset 16 + 3023 @ sp needed + 3024 002e 70BD pop {r4, r5, r6, pc} +1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3025 .loc 1 1018 1 view .LVU924 + 3026 .cfi_endproc + 3027 .LFE174: + 3029 .section .text.SDMMC_GetCmdResp7,"ax",%progbits + 3030 .align 1 + 3031 .global SDMMC_GetCmdResp7 + 3032 .syntax unified + 3033 .thumb + ARM GAS /tmp/ccPSMkLq.s page 96 + + + 3034 .thumb_func + 3036 SDMMC_GetCmdResp7: + 3037 .LVL198: + 3038 .LFB185: +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t sta_reg; + 3039 .loc 1 1484 1 is_stmt 1 view -0 + 3040 .cfi_startproc + 3041 @ args = 0, pretend = 0, frame = 0 + 3042 @ frame_needed = 0, uses_anonymous_args = 0 + 3043 @ link register save eliminated. +1484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t sta_reg; + 3044 .loc 1 1484 1 is_stmt 0 view .LVU926 + 3045 0000 0146 mov r1, r0 +1485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** /* 8 is the number of required instructions cycles for the below loop statement. + 3046 .loc 1 1485 3 is_stmt 1 view .LVU927 +1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3047 .loc 1 1488 3 view .LVU928 +1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3048 .loc 1 1488 61 is_stmt 0 view .LVU929 + 3049 0002 164B ldr r3, .L151 + 3050 0004 1B68 ldr r3, [r3] + 3051 0006 164A ldr r2, .L151+4 + 3052 0008 A2FB0323 umull r2, r3, r2, r3 + 3053 000c 5B0A lsrs r3, r3, #9 +1488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3054 .loc 1 1488 12 view .LVU930 + 3055 000e 41F28832 movw r2, #5000 + 3056 0012 02FB03F3 mul r3, r2, r3 + 3057 .LVL199: + 3058 .L145: +1490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 3059 .loc 1 1490 3 is_stmt 1 view .LVU931 +1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 3060 .loc 1 1492 5 view .LVU932 + 3061 0016 1A46 mov r2, r3 +1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 3062 .loc 1 1492 14 is_stmt 0 view .LVU933 + 3063 0018 013B subs r3, r3, #1 + 3064 .LVL200: +1492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 3065 .loc 1 1492 8 view .LVU934 + 3066 001a E2B1 cbz r2, .L148 +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + 3067 .loc 1 1496 5 is_stmt 1 view .LVU935 +1496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + 3068 .loc 1 1496 13 is_stmt 0 view .LVU936 + 3069 001c 4A6B ldr r2, [r1, #52] + 3070 .LVL201: +1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + 3071 .loc 1 1497 95 is_stmt 1 view .LVU937 + 3072 001e 12F0450F tst r2, #69 + 3073 0022 F8D0 beq .L145 +1497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + 3074 .loc 1 1497 95 is_stmt 0 discriminator 1 view .LVU938 + 3075 0024 12F4006F tst r2, #2048 + 3076 0028 F5D1 bne .L145 +1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + ARM GAS /tmp/ccPSMkLq.s page 97 + + + 3077 .loc 1 1500 3 is_stmt 1 view .LVU939 +1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 3078 .loc 1 1500 6 is_stmt 0 view .LVU940 + 3079 002a 4B6B ldr r3, [r1, #52] + 3080 .LVL202: +1500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 3081 .loc 1 1500 5 view .LVU941 + 3082 002c 13F0040F tst r3, #4 + 3083 0030 0BD1 bne .L149 +1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 3084 .loc 1 1507 8 is_stmt 1 view .LVU942 +1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 3085 .loc 1 1507 11 is_stmt 0 view .LVU943 + 3086 0032 4B6B ldr r3, [r1, #52] +1507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 3087 .loc 1 1507 10 view .LVU944 + 3088 0034 13F00103 ands r3, r3, #1 + 3089 0038 0AD1 bne .L150 +1517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3090 .loc 1 1517 3 is_stmt 1 view .LVU945 +1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 3091 .loc 1 1519 3 view .LVU946 +1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 3092 .loc 1 1519 6 is_stmt 0 view .LVU947 + 3093 003a 486B ldr r0, [r1, #52] + 3094 .LVL203: +1519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** { + 3095 .loc 1 1519 5 view .LVU948 + 3096 003c 10F04000 ands r0, r0, #64 + 3097 0040 0BD0 beq .L143 +1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 3098 .loc 1 1522 5 is_stmt 1 view .LVU949 + 3099 0042 4022 movs r2, #64 + 3100 .LVL204: +1522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 3101 .loc 1 1522 5 is_stmt 0 view .LVU950 + 3102 0044 8A63 str r2, [r1, #56] +1525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3103 .loc 1 1525 10 view .LVU951 + 3104 0046 1846 mov r0, r3 + 3105 0048 7047 bx lr + 3106 .LVL205: + 3107 .L149: +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3108 .loc 1 1503 5 is_stmt 1 view .LVU952 + 3109 004a 0420 movs r0, #4 + 3110 .LVL206: +1503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3111 .loc 1 1503 5 is_stmt 0 view .LVU953 + 3112 004c 8863 str r0, [r1, #56] +1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 3113 .loc 1 1505 5 is_stmt 1 view .LVU954 +1505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 3114 .loc 1 1505 12 is_stmt 0 view .LVU955 + 3115 004e 7047 bx lr + 3116 .LVL207: + 3117 .L150: + ARM GAS /tmp/ccPSMkLq.s page 98 + + +1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3118 .loc 1 1510 5 is_stmt 1 view .LVU956 + 3119 0050 0120 movs r0, #1 + 3120 .LVL208: +1510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3121 .loc 1 1510 5 is_stmt 0 view .LVU957 + 3122 0052 8863 str r0, [r1, #56] +1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 3123 .loc 1 1512 5 is_stmt 1 view .LVU958 +1512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 3124 .loc 1 1512 12 is_stmt 0 view .LVU959 + 3125 0054 7047 bx lr + 3126 .LVL209: + 3127 .L148: +1494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 3128 .loc 1 1494 14 view .LVU960 + 3129 0056 4FF00040 mov r0, #-2147483648 + 3130 .LVL210: + 3131 .L143: +1527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3132 .loc 1 1527 1 view .LVU961 + 3133 005a 7047 bx lr + 3134 .L152: + 3135 .align 2 + 3136 .L151: + 3137 005c 00000000 .word SystemCoreClock + 3138 0060 D34D6210 .word 274877907 + 3139 .cfi_endproc + 3140 .LFE185: + 3142 .section .text.SDMMC_CmdOperCond,"ax",%progbits + 3143 .align 1 + 3144 .global SDMMC_CmdOperCond + 3145 .syntax unified + 3146 .thumb + 3147 .thumb_func + 3149 SDMMC_CmdOperCond: + 3150 .LVL211: + 3151 .LFB167: + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 3152 .loc 1 822 1 is_stmt 1 view -0 + 3153 .cfi_startproc + 3154 @ args = 0, pretend = 0, frame = 24 + 3155 @ frame_needed = 0, uses_anonymous_args = 0 + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** SDMMC_CmdInitTypeDef sdmmc_cmdinit; + 3156 .loc 1 822 1 is_stmt 0 view .LVU963 + 3157 0000 10B5 push {r4, lr} + 3158 .LCFI82: + 3159 .cfi_def_cfa_offset 8 + 3160 .cfi_offset 4, -8 + 3161 .cfi_offset 14, -4 + 3162 0002 86B0 sub sp, sp, #24 + 3163 .LCFI83: + 3164 .cfi_def_cfa_offset 32 + 3165 0004 0446 mov r4, r0 + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** uint32_t errorstate; + 3166 .loc 1 823 3 is_stmt 1 view .LVU964 + 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + ARM GAS /tmp/ccPSMkLq.s page 99 + + + 3167 .loc 1 824 3 view .LVU965 + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; + 3168 .loc 1 831 3 view .LVU966 + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; + 3169 .loc 1 831 34 is_stmt 0 view .LVU967 + 3170 0006 4FF4D573 mov r3, #426 + 3171 000a 0193 str r3, [sp, #4] + 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 3172 .loc 1 832 3 is_stmt 1 view .LVU968 + 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + 3173 .loc 1 832 34 is_stmt 0 view .LVU969 + 3174 000c 0823 movs r3, #8 + 3175 000e 0293 str r3, [sp, #8] + 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 3176 .loc 1 833 3 is_stmt 1 view .LVU970 + 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + 3177 .loc 1 833 34 is_stmt 0 view .LVU971 + 3178 0010 4023 movs r3, #64 + 3179 0012 0393 str r3, [sp, #12] + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 3180 .loc 1 834 3 is_stmt 1 view .LVU972 + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + 3181 .loc 1 834 34 is_stmt 0 view .LVU973 + 3182 0014 0023 movs r3, #0 + 3183 0016 0493 str r3, [sp, #16] + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 3184 .loc 1 835 3 is_stmt 1 view .LVU974 + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + 3185 .loc 1 835 34 is_stmt 0 view .LVU975 + 3186 0018 4FF48063 mov r3, #1024 + 3187 001c 0593 str r3, [sp, #20] + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3188 .loc 1 836 3 is_stmt 1 view .LVU976 + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3189 .loc 1 836 9 is_stmt 0 view .LVU977 + 3190 001e 01A9 add r1, sp, #4 + 3191 0020 FFF7FEFF bl SDMMC_SendCommand + 3192 .LVL212: + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3193 .loc 1 839 3 is_stmt 1 view .LVU978 + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3194 .loc 1 839 16 is_stmt 0 view .LVU979 + 3195 0024 2046 mov r0, r4 + 3196 0026 FFF7FEFF bl SDMMC_GetCmdResp7 + 3197 .LVL213: + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** } + 3198 .loc 1 841 3 is_stmt 1 view .LVU980 + 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3199 .loc 1 842 1 is_stmt 0 view .LVU981 + 3200 002a 06B0 add sp, sp, #24 + 3201 .LCFI84: + 3202 .cfi_def_cfa_offset 8 + 3203 @ sp needed + 3204 002c 10BD pop {r4, pc} + 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c **** + 3205 .loc 1 842 1 view .LVU982 + 3206 .cfi_endproc + ARM GAS /tmp/ccPSMkLq.s page 100 + + + 3207 .LFE167: + 3209 .text + 3210 .Letext0: + 3211 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 3212 .file 3 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 3213 .file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h" + 3214 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h" + 3215 .file 6 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h" + ARM GAS /tmp/ccPSMkLq.s page 101 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_ll_sdmmc.c + /tmp/ccPSMkLq.s:20 .text.SDMMC_GetCmdError:00000000 $t + /tmp/ccPSMkLq.s:25 .text.SDMMC_GetCmdError:00000000 SDMMC_GetCmdError + /tmp/ccPSMkLq.s:80 .text.SDMMC_GetCmdError:00000030 $d + /tmp/ccPSMkLq.s:86 .text.SDMMC_Init:00000000 $t + /tmp/ccPSMkLq.s:92 .text.SDMMC_Init:00000000 SDMMC_Init + /tmp/ccPSMkLq.s:156 .text.SDMMC_Init:00000030 $d + /tmp/ccPSMkLq.s:161 .text.SDMMC_ReadFIFO:00000000 $t + /tmp/ccPSMkLq.s:167 .text.SDMMC_ReadFIFO:00000000 SDMMC_ReadFIFO + /tmp/ccPSMkLq.s:185 .text.SDMMC_WriteFIFO:00000000 $t + /tmp/ccPSMkLq.s:191 .text.SDMMC_WriteFIFO:00000000 SDMMC_WriteFIFO + /tmp/ccPSMkLq.s:214 .text.SDMMC_PowerState_ON:00000000 $t + /tmp/ccPSMkLq.s:220 .text.SDMMC_PowerState_ON:00000000 SDMMC_PowerState_ON + /tmp/ccPSMkLq.s:242 .text.SDMMC_PowerState_OFF:00000000 $t + /tmp/ccPSMkLq.s:248 .text.SDMMC_PowerState_OFF:00000000 SDMMC_PowerState_OFF + /tmp/ccPSMkLq.s:271 .text.SDMMC_GetPowerState:00000000 $t + /tmp/ccPSMkLq.s:277 .text.SDMMC_GetPowerState:00000000 SDMMC_GetPowerState + /tmp/ccPSMkLq.s:296 .text.SDMMC_SendCommand:00000000 $t + /tmp/ccPSMkLq.s:302 .text.SDMMC_SendCommand:00000000 SDMMC_SendCommand + /tmp/ccPSMkLq.s:354 .text.SDMMC_GetCommandResponse:00000000 $t + /tmp/ccPSMkLq.s:360 .text.SDMMC_GetCommandResponse:00000000 SDMMC_GetCommandResponse + /tmp/ccPSMkLq.s:379 .text.SDMMC_GetResponse:00000000 $t + /tmp/ccPSMkLq.s:385 .text.SDMMC_GetResponse:00000000 SDMMC_GetResponse + /tmp/ccPSMkLq.s:409 .text.SDMMC_ConfigData:00000000 $t + /tmp/ccPSMkLq.s:415 .text.SDMMC_ConfigData:00000000 SDMMC_ConfigData + /tmp/ccPSMkLq.s:473 .text.SDMMC_GetDataCounter:00000000 $t + /tmp/ccPSMkLq.s:479 .text.SDMMC_GetDataCounter:00000000 SDMMC_GetDataCounter + /tmp/ccPSMkLq.s:497 .text.SDMMC_GetFIFOCount:00000000 $t + /tmp/ccPSMkLq.s:503 .text.SDMMC_GetFIFOCount:00000000 SDMMC_GetFIFOCount + /tmp/ccPSMkLq.s:521 .text.SDMMC_SetSDMMCReadWaitMode:00000000 $t + /tmp/ccPSMkLq.s:527 .text.SDMMC_SetSDMMCReadWaitMode:00000000 SDMMC_SetSDMMCReadWaitMode + /tmp/ccPSMkLq.s:551 .text.SDMMC_CmdGoIdleState:00000000 $t + /tmp/ccPSMkLq.s:557 .text.SDMMC_CmdGoIdleState:00000000 SDMMC_CmdGoIdleState + /tmp/ccPSMkLq.s:615 .text.SDMMC_GetCmdResp1:00000000 $t + /tmp/ccPSMkLq.s:621 .text.SDMMC_GetCmdResp1:00000000 SDMMC_GetCmdResp1 + /tmp/ccPSMkLq.s:898 .text.SDMMC_GetCmdResp1:00000148 $d + /tmp/ccPSMkLq.s:905 .text.SDMMC_CmdBlockLength:00000000 $t + /tmp/ccPSMkLq.s:911 .text.SDMMC_CmdBlockLength:00000000 SDMMC_CmdBlockLength + /tmp/ccPSMkLq.s:976 .text.SDMMC_CmdReadSingleBlock:00000000 $t + /tmp/ccPSMkLq.s:982 .text.SDMMC_CmdReadSingleBlock:00000000 SDMMC_CmdReadSingleBlock + /tmp/ccPSMkLq.s:1047 .text.SDMMC_CmdReadMultiBlock:00000000 $t + /tmp/ccPSMkLq.s:1053 .text.SDMMC_CmdReadMultiBlock:00000000 SDMMC_CmdReadMultiBlock + /tmp/ccPSMkLq.s:1118 .text.SDMMC_CmdWriteSingleBlock:00000000 $t + /tmp/ccPSMkLq.s:1124 .text.SDMMC_CmdWriteSingleBlock:00000000 SDMMC_CmdWriteSingleBlock + /tmp/ccPSMkLq.s:1189 .text.SDMMC_CmdWriteMultiBlock:00000000 $t + /tmp/ccPSMkLq.s:1195 .text.SDMMC_CmdWriteMultiBlock:00000000 SDMMC_CmdWriteMultiBlock + /tmp/ccPSMkLq.s:1260 .text.SDMMC_CmdSDEraseStartAdd:00000000 $t + /tmp/ccPSMkLq.s:1266 .text.SDMMC_CmdSDEraseStartAdd:00000000 SDMMC_CmdSDEraseStartAdd + /tmp/ccPSMkLq.s:1331 .text.SDMMC_CmdSDEraseEndAdd:00000000 $t + /tmp/ccPSMkLq.s:1337 .text.SDMMC_CmdSDEraseEndAdd:00000000 SDMMC_CmdSDEraseEndAdd + /tmp/ccPSMkLq.s:1402 .text.SDMMC_CmdEraseStartAdd:00000000 $t + /tmp/ccPSMkLq.s:1408 .text.SDMMC_CmdEraseStartAdd:00000000 SDMMC_CmdEraseStartAdd + /tmp/ccPSMkLq.s:1473 .text.SDMMC_CmdEraseEndAdd:00000000 $t + /tmp/ccPSMkLq.s:1479 .text.SDMMC_CmdEraseEndAdd:00000000 SDMMC_CmdEraseEndAdd + /tmp/ccPSMkLq.s:1544 .text.SDMMC_CmdErase:00000000 $t + /tmp/ccPSMkLq.s:1550 .text.SDMMC_CmdErase:00000000 SDMMC_CmdErase + ARM GAS /tmp/ccPSMkLq.s page 102 + + + /tmp/ccPSMkLq.s:1613 .text.SDMMC_CmdStopTransfer:00000000 $t + /tmp/ccPSMkLq.s:1619 .text.SDMMC_CmdStopTransfer:00000000 SDMMC_CmdStopTransfer + /tmp/ccPSMkLq.s:1682 .text.SDMMC_CmdStopTransfer:00000030 $d + /tmp/ccPSMkLq.s:1687 .text.SDMMC_CmdSelDesel:00000000 $t + /tmp/ccPSMkLq.s:1693 .text.SDMMC_CmdSelDesel:00000000 SDMMC_CmdSelDesel + /tmp/ccPSMkLq.s:1756 .text.SDMMC_CmdAppCommand:00000000 $t + /tmp/ccPSMkLq.s:1762 .text.SDMMC_CmdAppCommand:00000000 SDMMC_CmdAppCommand + /tmp/ccPSMkLq.s:1827 .text.SDMMC_CmdBusWidth:00000000 $t + /tmp/ccPSMkLq.s:1833 .text.SDMMC_CmdBusWidth:00000000 SDMMC_CmdBusWidth + /tmp/ccPSMkLq.s:1898 .text.SDMMC_CmdSendSCR:00000000 $t + /tmp/ccPSMkLq.s:1904 .text.SDMMC_CmdSendSCR:00000000 SDMMC_CmdSendSCR + /tmp/ccPSMkLq.s:1967 .text.SDMMC_CmdSetRelAddMmc:00000000 $t + /tmp/ccPSMkLq.s:1973 .text.SDMMC_CmdSetRelAddMmc:00000000 SDMMC_CmdSetRelAddMmc + /tmp/ccPSMkLq.s:2039 .text.SDMMC_CmdSendStatus:00000000 $t + /tmp/ccPSMkLq.s:2045 .text.SDMMC_CmdSendStatus:00000000 SDMMC_CmdSendStatus + /tmp/ccPSMkLq.s:2110 .text.SDMMC_CmdStatusRegister:00000000 $t + /tmp/ccPSMkLq.s:2116 .text.SDMMC_CmdStatusRegister:00000000 SDMMC_CmdStatusRegister + /tmp/ccPSMkLq.s:2179 .text.SDMMC_CmdSwitch:00000000 $t + /tmp/ccPSMkLq.s:2185 .text.SDMMC_CmdSwitch:00000000 SDMMC_CmdSwitch + /tmp/ccPSMkLq.s:2250 .text.SDMMC_CmdSendEXTCSD:00000000 $t + /tmp/ccPSMkLq.s:2256 .text.SDMMC_CmdSendEXTCSD:00000000 SDMMC_CmdSendEXTCSD + /tmp/ccPSMkLq.s:2321 .text.SDMMC_GetCmdResp2:00000000 $t + /tmp/ccPSMkLq.s:2327 .text.SDMMC_GetCmdResp2:00000000 SDMMC_GetCmdResp2 + /tmp/ccPSMkLq.s:2415 .text.SDMMC_GetCmdResp2:00000054 $d + /tmp/ccPSMkLq.s:2421 .text.SDMMC_CmdSendCID:00000000 $t + /tmp/ccPSMkLq.s:2427 .text.SDMMC_CmdSendCID:00000000 SDMMC_CmdSendCID + /tmp/ccPSMkLq.s:2487 .text.SDMMC_CmdSendCSD:00000000 $t + /tmp/ccPSMkLq.s:2493 .text.SDMMC_CmdSendCSD:00000000 SDMMC_CmdSendCSD + /tmp/ccPSMkLq.s:2555 .text.SDMMC_GetCmdResp3:00000000 $t + /tmp/ccPSMkLq.s:2561 .text.SDMMC_GetCmdResp3:00000000 SDMMC_GetCmdResp3 + /tmp/ccPSMkLq.s:2635 .text.SDMMC_GetCmdResp3:00000044 $d + /tmp/ccPSMkLq.s:2641 .text.SDMMC_CmdAppOperCommand:00000000 $t + /tmp/ccPSMkLq.s:2647 .text.SDMMC_CmdAppOperCommand:00000000 SDMMC_CmdAppOperCommand + /tmp/ccPSMkLq.s:2712 .text.SDMMC_CmdAppOperCommand:00000030 $d + /tmp/ccPSMkLq.s:2717 .text.SDMMC_CmdOpCondition:00000000 $t + /tmp/ccPSMkLq.s:2723 .text.SDMMC_CmdOpCondition:00000000 SDMMC_CmdOpCondition + /tmp/ccPSMkLq.s:2785 .text.SDMMC_GetCmdResp6:00000000 $t + /tmp/ccPSMkLq.s:2791 .text.SDMMC_GetCmdResp6:00000000 SDMMC_GetCmdResp6 + /tmp/ccPSMkLq.s:2951 .text.SDMMC_GetCmdResp6:00000098 $d + /tmp/ccPSMkLq.s:2957 .text.SDMMC_CmdSetRelAdd:00000000 $t + /tmp/ccPSMkLq.s:2963 .text.SDMMC_CmdSetRelAdd:00000000 SDMMC_CmdSetRelAdd + /tmp/ccPSMkLq.s:3030 .text.SDMMC_GetCmdResp7:00000000 $t + /tmp/ccPSMkLq.s:3036 .text.SDMMC_GetCmdResp7:00000000 SDMMC_GetCmdResp7 + /tmp/ccPSMkLq.s:3137 .text.SDMMC_GetCmdResp7:0000005c $d + /tmp/ccPSMkLq.s:3143 .text.SDMMC_CmdOperCond:00000000 $t + /tmp/ccPSMkLq.s:3149 .text.SDMMC_CmdOperCond:00000000 SDMMC_CmdOperCond + +UNDEFINED SYMBOLS +SystemCoreClock diff --git a/build/stm32f7xx_ll_sdmmc.o b/build/stm32f7xx_ll_sdmmc.o new file mode 100644 index 0000000000000000000000000000000000000000..f354821531f54a54df0cac13b0cd57fd4dc6ff9b GIT binary patch literal 47424 zcmeI53t$!1wfASv$vK21K%N)`i{#utu@YXb7K}R+3X%y26U3>_)C1TIU@+xaX5iR@?0KhDSfy zR78*Af-us-ax0d<0#*&yzOb=4f5p6pZ4Ei4Phm}K%qe}Wq4lHmP)_ON#@=dt^q#ia zxkV*Q>8*6-yoU2vUfkf?o=E#MhV1*8_ABY%TGKY$Df{s=3ifZRO_x6Nz6*D!lv@S% zj?j+qj+7mXkQUitf9K%Ge>)f}=Vx?x<|CFh>AsZmUgZ^NsfxKb9SG-~mKHt``eRPH zJ=r?$^gXp}a`w&Y^YNaX{Z{M#=P0H0i5l8{B75xEuG$5AQ}B7>-X{vaRqOb@eWs0+ z8GEh4jvOwZJSV^8C*QY@oAheVzD3eH?xuZy zH|_g%(>~Ts`@!9`FX*QI&~DjtUpa<3hJ>$7?5{@-GswT(eIm{vvv3B<#*y()&&|`3an72|eYO>O?umknYuje0#J1wo zHlK@}Gt3X&xjoX>Wf^Ue`C6Wvj34R&XwD+O#O0 zXO>0jI6G{rNZH#zZiv8P&Wo1mn_0sqrMw9RnO6_qQ6rq$JC9n_Ksl!u%P>&xNDf&02g(5w| zG>PnnlTd18AC%$0MX_C&KatxQ_Eu<2ziHh5KK0}JU54$H4fu#$fDgFe0*B!x+@9EP z1Q1P$G`4hDJ!tbF*3=?=*jCR4u!|m_MYV0GZ3(Xr_soGR{rd8Q90WRZ*=9VR`?uO&Paa&4#QsyXKe#R1)1sjl+ShL-1MU;Z*t}Q^r4i` zbL9c)$5P(x%CYoo(5m6{UH?PV3mMNAS00}JGs+jZ^2qcj(MI75-TXxvRn;@B@I|gX zE@N(Kr4`=l+D}R!&Gz~ySDupoUGz(MTR4lCx}k!S^fT%IVmJSs^gmPH9?oK8g$m}U zUxLmKU*hBs7i_YfmM%c5Y3U5B*Ed^w=OHD{B@i7CA#= zO4d5ouSsHR)|2$uDlsGL*A&-E%*=X&(X5k*3VogOhR_K>b_zQs=P!uB?h(zh*?wFm zVGW&Q*?)yiZWca}T6_nXYLYE0FCY2r^r-P#3FSg2^tHdn{(3r+=6R}vnx0NUg5&Aw z$Z_b~}=tj(#u+RTTV zjdh_{nNyw0+ynpLWx*zzWlq8GLh)NFO*G3LjZoinUZ4_hTL9b||)DMPE#y`){YjyP7TjU8LFH!_MLK#kW&TU%vwFQ&^q8 z_;!lvixT9Yj5T){!iA&x9DM7bXvgaG#dlK7sQ4BX-=xyi{=1IySty>N(u8-HqkJ2R z*RgtiaScLY+jpQZR>HsA7ah==zBt0(z>v@J)q^L4Fq+7&#y;rO-ru5?hB6P*FygOL0O-^9f!r*GG`7z{(^s}r9@a+VKKwxbh zIT9)CnYgwS+m+$8tvPJ&8A3K`~Q&|Zwy33Fb`bcV@O zILD6@<^ng&I;S-kI$^#GgWqEH!rTJi@pikS&N}iK_!@>bQ0JooUu0y(zR1|m2jImX z*3*rwIAshYn+VgfSe+ooxk0E)$2&os41*(2L{4C$_euz3_io^g}J-CVdkSn?2s?aVl-SfTHNkT za~m#{GMWvy5ZV*54yY`h!8|2A(6vF)gw+W%B@kxB3G*8;xCU$f5ai$vax#1;wq_wx zK4%BH7yG^aUO0X{V*lO=mv;YjH_Z3KBN^tq(7uJ$ISsrQo@P!1XqPBfC(QT5iTm*f zVRI-t76!wydSU*pOPJh`dA5rOzYg1#JRM*Z^3ZPY@kPn~V=6q__jyt72_MTSH$dBo z)#>v+;S)B%^qWvzgVl-hc{fV!A1^pjJ`aOESiL^K1-|3)xcdiVakPwVEW7#sKxA*j zi#<8RZNK}S$Ofa*1FO>Pj{NpE(7*bRfbuzEq!-t8IEW6DYCg-Eqz@^=* zw;N_#*c{!y1MRo4I^(J>Jd!a{gr*sY)oZKa zaN~l5X4|7h)ZFx9c%so z_+f{AuS*a--rk)M#5^7dqP`&5VK>2xU7zW;MAT`CUqSmzthp8gkA|mQ4by{A9Kh;C zmg+{P4(sVeHUj-K46D~+v*FvjNT zh&~J@9@_VX%%S}*7~F}~i|ChKBI4jqat4ZIaH5s{_aQGQUh>6Mgd9JDQ~Tm9x9MIA z4d>DQGid*U)rslf12Mhq#554y)gP-DQ#0Ir!B)!uGb4JHt@KDBq9VAoi?iK`9toKd z)dXz=*4*bN1ZUAfWhNfy)bj(`wNEYT;1Nmz333D$LuV8h;yetsrV&yG5atRe%z7BqV)eq@ z-Q6(1!A_qQ2y;DL+MRiBYt9Od<=DIz+TB>4FlU9z*qSdx@jO;1%-Ml3=Qv^ZLLaAN z^};+EzPr_$%h;Nu0%6AB(jL&)4Rch;TmdYDb}81}O$ZNp%oPAf@Yz_MFh>W%EONrU z4+h`I>V^5Y?uL0fuZ{8oVg3Xz?Z>?^^PEmkK~Le-qA>HEP9F}%5Ufs^M+Cymcfvd! z2B%^5!n_r}yVaUSY?;sO_}PVuHn_CUIKpks&unwtyc62nvF2`d@|ff19w?r|>V$dF zPCVsUPM8riUKpzv=6v|>MwopOA0m3i&M|YQDBi*u#Y`dHG^oZHs70OBY!DYWO|gD9`j{_SCc6pvt7=C@G+-( z+L58f$@DCv-RX;Vs4|`DW!h<*9qF6M@C~d3vw0}nX;;$1UYxg`9&WPD3HvFe|Co-m zQ#fVX*S?D}ZS%$CR)n*1PE6ZubEV!B!y$}yAZKck#ayY|i;wDPZnNy|j{6x%pNbWZ zSL4&(VE43Zu))Q3%u6cA@dn%MS?iFY-O1F!XioE0HinFx-TR7{=`?#ByXGcj_$JnY zncO!{vny%gR`zr!nrD&z6FSaL;rvox`$}xv3w@Qv_gUlq8=m`xwz;ZKM>qDsicAml zP&U;Ulbh*TFVj?eB4e6>48=~S)7eHvNiv0TqsOUzkv)N#mLfy7lPRC0EYp_>--}Fm zv%O52wmAcxj|}Hx9r%KirHmFBnAzqQPG9>47N6p)sN49PJx?jNxuoKl|1OIkWdDu6 zejeW~#zFfMlI)n7&HlM*mwSPXFcM?KZbPO?r>^U>Wijh1LE7G&^o&D#IU;FlRAuD<(`Fm3KE||Gziqh16H2>cCL%o2 zO~Bzbp-iL=Kww_WD2Rax!NTY$bONUl)i;u`-`z6E5S;Ht@d+w#;cIf3rIH0NPHp&g7?)? zeZtq~^BpZdwQvkLrd>LohhCJ=f$C&SS|t5AmK8(^RuoHgEtYPaFy({j!&oCc(~xttfy%ekVS5!;bU5JzSG5O^!|oTfi)U7gQPQT4=0PH2NIS+kPsU|lcY_=agHV;Xcw~1 zG^D-TMm)?y)WUJ#c&l(#prtPa71! zGvOg&@kPc8B#G=Oqh3rn7QS=t7w^*lE+hR*iSr*j7B7==J@ubGew$w4;KGg-BYAm& z?Jmbf+^Rzgb}hm=%T*J!H~WyT)gdMraoM=m~I^E6cHo2VH`|NI4s8h*HMKxe>jVDX*mztDjGe>_SVJX_;`&Q9?q4jW8mn5Ow(eNp?5 z_T)kCf8UpxfAstRf_~@8iYF}`{)ygLKkqt=UqfI@L=R)i%PN=>H2*xWyd;1r!K;d7 zrgY;hoahKyMLS97yG#`k!HK=hIsaUAbIo0Lke=c6z41KaLwgZrNXVs=eI#N0%9AGN16&%5jUQTUB7jbd6n&7IO)yBjn{3bf3&;PE`N`9 zpPR{>90lA9>;t`f;YmL8>kW|Yvi8Px_3dj%S5+?VEv+r}qv~r`HjW-Mwy?Nx%;?6J+NRFBddqcHx}a)q)#$SN zb&a+4@EdnMdTzinX`wK}Q#KvVV~bZYoTjGbYwMbuYYS_!&qH5_#}o@2xI4>c0<542 zdkSP~sA*bWSHB8s?2bu%IraOXu}E6<=tw#e(qc%M9*sqZKxM}wy~FEc5j)(oFcd*E$9?_WwqYHPo|2bi zmb}O?$k|1aVS^&sLxP{-=+V&=;nI%g!~%}Cgy1GOl7-y%XgmYvFXVD3EgNZ>jH}3T zkZ80!?%)s>kA$39hp-g-F@XfidX{c-oHz!D!U=J_YSLKKyhuKR=|d+4kwH;BlU6(^ zGH6KrGaMZnuW4eSe{o7Uk~JM13MG`VEzHvM@*=rNWq|ApSS5Pc=~%JBoj|gkK>EVi zG*Cfg0Am_CC^BG3{4*X?ZY<#OG2_v#bz*7H_|k$s^9s{)^G;3HAvZ>y=AN398yRA% zGg=&c2u_XkG@%pE~i`PrgfnR=a z-THU&`pDnK>q}j{y5llPcN_bBR&joi@AaPFFS7~m>EhK5DM+^pUm(;sJ*R!Y#Dn%{o>#ZG+>nByy0SO2K4%Qv zmF9HU;6q%=MsRBGdL7UM9m^|STnF&PpN^c1?dj2E_!EttV+oHDm_R`ko=9-o| zt8!LV#TfHhY(B@D&vBM#KeMT|cFp|ymem~%R#{C)jW*}DG_*Oq*-0}{KvkxOeqo$+YYHDp+9Wx)D zEo&QBx763g`1?j)FjXC`ZPo2HEo)cRx0^uu14UlytoE9<^|M+`IdM;PAYZi&HSIF5 zs_!uQ7}v=)jU5YGF&E-^V%4fQwAGi@ukvO`lFoTxqGhx<58SF=+rR-wGL zeQrxfeS3Rno6|L8CZKB^=j@T@x>@b*t?gDDf78G%r?#~d?K87;?a7UG=;7+d=K9vo z4r{@Ts(GeYtLHA5wP;DTmDnF<4yLrVz1~#H4X3$|ty$IBvbw3>^s^Z-@gDEmu^cyx z<|)71=BPny`&u&|);6@Zcf=CPHYLv7&{nf{ZM@v7`j$G5pw6`>XlK*)*RC)1O$|h%7R#`>W0;_cXywXbSZ0=q+t7=x|NwdnvSg4pg^pgzvliM3R>Wvq# zt$q87GkEB9j0%lwio0mWcF|1eqM0ZS#^mhQxphtT?6G>QlvThH$;4a~x53Wp^o`~2 z{AG<8$0lks{9U!#i;bH56-U>s%F0ER^2A1V4l#ADohzH%_D5w*XPG_0+ZVlE!VI{w z#&z*reuQSRko%XZPT-`%~y^F+uU4V}#^ z!Bx<&YFjscRNa^f6q{OWI!0ldcq$H+bx_o_*EUSW1oFCx^`n}PTh&%r*A^SK8vi*c zSB)x;jame0RUM)lwYI*tqY+1Y$g4VA%(kbqX0)&FY_7+##d}=ob&ahR4XqumEseFyt2$S%t#4mdQ(M2hy{4|F zee~@5miqRZj@I_&6{Rx+#?UNZ+q$ZQyRtbp_&U#t9J@f^bYNods&-D_ICp!&bMNU~ zTUo!l5p(11mNmPybaHI?nDLX%IB2hL8Z)YRL~u~>#szOzAH;$uk~a3nvsjefg|~ci zT><2+pBcR~m+;n@-!2-Ec}vKj&RcQakz)b-p#PxETX=r|yp`vdgZ7M{H+kLV7;Mbw zow_A-sXe22tfDvL^*^%1TYsqc`6*k%7r-VVFK?U8=$+xD%;-IQN$-q*q`M6Z9i=Tx$J?&{{ypixKz#nO&D)OtvCP}L@v&TK#`59P{r=_${5k#O?iwEJ*yD_e!d6ZoJtv-st+16BNY69Cah4Iu`qW?jG^udAj!GZLGKsx_;KE8ylqXX$j#}ly? zwuS}LxmU-Rur(r(J|dootuR_QG5+HM`w#cN_!7281?)$~6R{PxMhDVI2hzs`(s@9N zFJWtJAbo5+5nEwvd?0;%AbnyWePST}_(1ycf%Fps=_drzrv}oe2GXYo(x;pDtoE#? zdt2NHTQdUoGXm+Qf%MWq`m8|uEK^>YXEn>);zrn-9k8Dr=?6i8|Rn%B|H9mS$h)X-qstEhZ_4n)<=?g z=FP_WAr-;Io5x>0hSNnd2`mdxwTY(5sAbgFk~vKiK)_->wbiqyVbJa&oA`; zX+?-;Mosq^95Z8+IIWzJ&}G668M@3Rc{vU_cUN_&Sr{b*=bH{OIb+mGZT-_VzPlJ+ zWP#aa)WUZ=z_aqEB|Qy0n{$6Yg>NR?r}d`Dx%v5 zy3^#k)#Ofc2J^Tx#7-6cccZ)r{L^v4?Cx~33Cx`s4jTDpn7#Qj=UB<#FV4q4orV(( z|1LcZUzHY;=UC>fm-aRM+yxFav>PD1;pCS8x-!p6Uq*bUJ8?1trpIvV4EI@KsvA1X*XG%A6&~)#j#?!IA5$3mx{~94)J{P zO7SLfxA;Tx=i*!9M}6knnS?I9mD>Bu^L1q~}9mw67LVlfHqh z!EY#uZAw2|=@&}gCSE4}^^*B?75&~K{cg$pX?f}&l>Q0HKNa~d3fAKl$$S9|?cbFC zL&+bBpOA<%18qubH$@~1v&-ype3JX88}B%dd4mHz8wC4N~^ zyiNLhNcjJO_>lBZN`6}0BmHZV_loaGzn{cG=o9f%rAMPqyxAnm=_~e^ewgIr#3JdZ zNG=g)NxxX~67f{&S4loYY?c12lFt>lkjLOSDE>2v_TuSov2 z_@?yy*=O2)Bz_`&D$bGgn@b`+UmQrH9KL6QJc)!|Es2BmYHJipmLVk}r8+`2$F#50^Yr93%Zy$uq=q z=}!_@O20~6L&EPl-A1M7X$^RxkE&Z$FJJP=|?jzwZ4b!sZ z2omK?AWy`8CQc(!&K#vzOI|9TE`6iqX0cuR&ElofUn%lM4J_wwk?&++`M)CP;8isu z-?G5+KUDew$p^*EG$%b*>_@`S2ywjh$BWZQ_+KiXMZ$gyS%=?u7Ww)FmV33*Za!ynFYRPNFHt9Es+oiu;{5lDL|13UBqMTRBGQ7M&e3L{uzf<~O zB!4D`dO7*0>ANJ~B7R5u z`y@Xo{;TxQimyojYw=AI<$Nag>FxL*K+eSVjyRNT#`seDWXaRSQt1~-t`e6@-yrf` z0raz8JcmR%*N8tLQNPE@M$39qe40eQmz4gx z$26d^OA&jL@Yhc~TKW-UA&GM4h^tB1caWGuUoUPXQT~NWzf$tm;`P$sA>J?jL*k<( z{P8FE$pa+HNzDQ=m7gJIk|^g$@=RQhN3j<>82#C;_E{Z;8v-0q{C zCiWqbufOC$;!x?wi6zpPiTt%Yd`J5C#eL*h)Fap72onA$kYjM2AxBsj>dI{_%@01KUDew$p^)hJSSf!3APj zQJ;d(>dPQvfiO21k1ZQ>o$-!J(g@lombh_6Y%SA3g9IS0j~a1)5-A4eW%S);|V zB+BQ{x-)&QI6Xt`m1kzgv8SjN#2S z;4dKIuOt;fH^WLiQk0zg!Z1mMYyJNBUop zI0wEi{$BdOlCb}q7(rXIe%U0hRr-nr(vK!#KUSP1{UUK0iEGXkVzcxcNaQ<5+#>zu zWKYyjyjJNqD*Zc>zbD=!{g1?Fq~9arYoD2~LI{R9JR4$o8V(b&%Nn^@oFG<;Cy8cW z5_1`tsxkJP$W=JLi5H8PiC2r)i8qP2ig${;#rwsF#K**c6MrT?C%z@VD}E?`B$_wo zB0jzygmGqxc_QDK%Xz2aVv#sby|rY5%79AL8#tzTubYy~RASpU9W}GM)E+$>YVT zVwpHcZ=XXbIiRg%vT&lSzQF4DJ2zEr$Myk5MAJO%R{;v?dZ#Gi=Ih%bo$F7i#l z%>RLSPz-b475X%>x5#_KoCh2wjuR(|)5TKpL~)_GL_9@YA@bfa{qohpB<~%Qd}}ai z=9j^1BwsJ`t-+j+yG#6m_%9;gAI$V$i)Nk~@_Ul^iTlL^;z2Q*;^a>gv&1}cfEW{p ziN}d0qM3h2x$`715>FCO75Nrp#%t!C!Sf_vAbv~yws@C#k7(wZk?#@7W_}s+^OD~d z-xK$Vd|Nup<=cxnuh>KEBj$+x#X;gQ@i>w1Ic9#opo=_FTqxFxtHl@7tOpg^p8t^QvA92g7}X3zW7J+&m!M-O#gjEGv5sPNXbLQW5g1% zOyv8DIX`)_xLm9i*NA3*8Fpt$HuKDoFO$4OyiUAP{Jwa<_^;w);!~oTcZNT{@0js? zARZv+<9b)@!TDRr>0*w^moZa6NGuS|yfgGCNS-N{i+r^)^PML0oy45SY!TOqXN#M~ z3&l%CzK4$aZWF&N-YwoIJ|#XYz9jxqd|iB7JSc{7qNjf|PmTG`zLdeE#3ACbVxc%e zoGdOBE5%d9(?!0)n0`CNuZri2e0ed`zbTq|>pHv&jxzXw_^|k6@h9RQ@kNpECuY76 z#E-;}MKhm`^xn8;qFtWYPvl#QsV@}yeqqjs&JgE{3&bVjDPoOSFY-;q%zuu!McgWW zQ@lyMUA$AgSA0O^`-$oA7owT}UV`H}W$+K;pTy5ZoAb#??WBus8GT;AH8iiG1BK<5?#1J;9t`Z57WFzbc+DUL;;7?hyG# zVdnpyc(3??_(Sn=kuMvj{hQ){h`$&4o?)hEi2cc#IF5T1NiwDJUFUL=s zXy)l*&vyyae}Tw10(1U$f;df_DV``U6wSOn>`#^4BDRYg#B;<;#Vf^|$P(O75x*zi zEt+|Jq(3703Gt^QUlYvyuZ!=BABcQoFw^-SHPX!QgE^A!%6my1`4d^Irb?-74QV!rnY@n_<5;xENtiDv#E_U}pN zyMLMA?&C03%nku45pNgyE??$yDBbo2(W&Rc7YH^LYN!%h{ESmct$Y<_* zfY(dUxA@ZEgCbwQ8#>Oio)KRZUl#X@Z;2m>=Dr8=@kPDNpDOkdbHw4|NO7zJ= zPfwBW*5y2VOdKX2C-S|yp%~^3#7glbk*~<*{P{ZZ9PvDnZ^Pw$`Ay>O;+-Pjgv<12 z#b1c8h_8$0J_+pj`diMI?A4AZ@J)A`SibxnuBGFzYB-(Wj ziMFmFk$EYJ{$D|2{4|gluWe)u_v=ZF|4k&WGq;k*V7`wWp}#lA{=ADajyt!LI6m$s zaU6eu9EA5%-W7 zKQD?elO;H>i+f3or?Y87w9-zQ0CdTt7)>=)McaacT&1CjK6d#JF8V z=33So665r4G9Q0uMB;d2{(gM`&MRTa7>6}v%(BiQhv4s&$)T3@dlKVp2Fm96x`xEK z`W=b!R2l^_j=n)+{FuMT#kiTpc|wer>q(50Kadz7vr|EgiyKIc2Q$A`g8c<`V*lSr zqTlzE<(4&<^DyY=n@IHU$0YjG{GB5D@#b{M=)X@$^xH*Pz{gB@WMEkdptMGSjWTTD~?K*y=u4oD?1bH}#*rrHE=%ybKl1WD>=6Hgl zjJ$$Gzcfj1Bhfz_C2u0pPunG5PNKhVki3gTzuhT$H;MjxSn{Lf0PSapZx3bk=W9ye zOUASxA$=cZ^zWx6WQ*enl{5PRWs>A6B*u+-euL#x#`syU^o=CO(Y2Cq zAWKlbtHUbf4`f+|EAgXsh4?+D zLMjXW =&F9yfXGQ%A?}<^rGXC7CUmJfSls`pxs1!Uy>Q731lGLB#f1cE@Px4f0 zAlZAi)UWqFVd_`IoBuh}KvMiC+WZMgpE(V-Fdh{2|H@o2IsP!?m@b`zto|obgISTx zUh)5G*&$4PPpKxc=<>Ykp=>_iP4F4kBwiAqW=&#{_+0Cu4D^KSp^}reW5REDCdueM z|C%Jt_atnRRPUMCBx&x`u}PDB&&eiD_nw$dmYVqNY%&YyDcWQy@#krSsqw*BoU{>< zlRrfn%!YyJK5ZLJihCTJEL-6BV1v2g*#9hUFgfmgLNe#^A8tH!#)-)?de7{de0B9J zJ6A7nY+2Qc1F6}rS-G;kew~xk(csrr{bCJ%C3bbaj<$|PS4~r6OTFt6hij{_7SG7@ zHwt~Fu4=DohS7}51%)*o9qo-PJ3HXE8%uxK;`CA|G$7}jz_2o0<{`zk5`5Wx>$GprQ#6& zE(-X|_4&hBcF*5!f%rDTUoq0%1>I_vn*;ua`uyQ5zvu7Y0{-|+e6spJ7VtOD=MPf` zp1-#O{@yr*zr6u}Wj=q$`~2~5SpDOV&(bH0F9bXP_^bB$!<2;=Uo7Bn<{|tI2>7e> z`NNcl=WklTUkChQ%D`KYY?jFZe;x40^I0v{=~!t;nSV>`ukRlCI~IC(ar>8ld+V?7 zMqhk0VC?$q4EX!&A^e>g@VDLPuhi%7@_@ggm|Mh@jJL2{E<8^7x+sRfUtkW^UDy^}P7U}= zX~liATqnLNq`UE*5%8Bf6!!<+pkU|v+ZeE$c8q1MWrt{S?bZj%z4v?=;DV0rauQaz z+=~PL?w*GGeXbMOxtkXS{axqG*V5lopT8Re{*Etk>|kOR*WYyke0{!Yc} z#{+Eqm8@b^<4p5H@??l7j|yN8V|31CGkASGP#hx v;bCQB{+53qTL*n7R{CQzu}t{$mXbz1hvQSY{;~pg%f5yCD~QEiT)Y1R8pS?u literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_ll_spi.d b/build/stm32f7xx_ll_spi.d new file mode 100644 index 0000000..0883518 --- /dev/null +++ b/build/stm32f7xx_ll_spi.d @@ -0,0 +1,74 @@ +build/stm32f7xx_ll_spi.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h: diff --git a/build/stm32f7xx_ll_spi.lst b/build/stm32f7xx_ll_spi.lst new file mode 100644 index 0000000..a37ad88 --- /dev/null +++ b/build/stm32f7xx_ll_spi.lst @@ -0,0 +1,5233 @@ +ARM GAS /tmp/cczBZbME.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_ll_spi.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c" + 19 .section .text.LL_SPI_DeInit,"ax",%progbits + 20 .align 1 + 21 .global LL_SPI_DeInit + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 LL_SPI_DeInit: + 27 .LVL0: + 28 .LFB451: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @file stm32f7xx_ll_spi.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @brief SPI LL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * This software is licensed under terms that can be found in the LICENSE file + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * in the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #if defined(USE_FULL_LL_DRIVER) + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Includes ------------------------------------------------------------------*/ + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #include "stm32f7xx_ll_spi.h" + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #include "stm32f7xx_ll_bus.h" + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #include "stm32f7xx_ll_rcc.h" + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #ifdef USE_FULL_ASSERT + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #include "stm32_assert.h" + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #else + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define assert_param(expr) ((void)0U) + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #endif /* USE_FULL_ASSERT */ + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + ARM GAS /tmp/cczBZbME.s page 2 + + + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @addtogroup STM32F7xx_LL_Driver + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @{ + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defin + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @addtogroup SPI_LL + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @{ + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private types -------------------------------------------------------------*/ + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private variables ---------------------------------------------------------*/ + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private constants ---------------------------------------------------------*/ + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @defgroup SPI_LL_Private_Constants SPI Private Constants + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @{ + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* SPI registers Masks */ + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \ + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \ + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \ + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \ + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_CR1_BIDIMODE) + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @} + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private macros ------------------------------------------------------------*/ + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @defgroup SPI_LL_Private_Macros SPI Private Macros + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @{ + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \ + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \ + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \ + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \ + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_MODE_SLAVE)) + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \ + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \ + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \ + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \ + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \ + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \ + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \ + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \ + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \ + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \ + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \ + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \ + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)) + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \ + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_POLARITY_HIGH)) + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \ + ARM GAS /tmp/cczBZbME.s page 3 + + + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_PHASE_2EDGE)) + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \ + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \ + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \ + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \ + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \ + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \ + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \ + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \ + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \ + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \ + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_MSB_FIRST)) + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \ + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE)) + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U) + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @} + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private function prototypes -----------------------------------------------*/ + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Exported functions --------------------------------------------------------*/ + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @addtogroup SPI_LL_Exported_Functions + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @{ + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @addtogroup SPI_LL_EF_Init + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @{ + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @brief De-initialize the SPI registers to their default reset values. + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @param SPIx SPI Instance + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @retval An ErrorStatus enumeration value: + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - SUCCESS: SPI registers are de-initialized + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - ERROR: SPI registers are not de-initialized + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 29 .loc 1 134 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 34 .loc 1 134 1 is_stmt 0 view .LVU1 + 35 0000 0346 mov r3, r0 + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** ErrorStatus status = ERROR; + 36 .loc 1 135 3 is_stmt 1 view .LVU2 + 37 .LVL1: + ARM GAS /tmp/cczBZbME.s page 4 + + + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Check the parameters */ + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_SPI_ALL_INSTANCE(SPIx)); + 38 .loc 1 138 3 view .LVU3 + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #if defined(SPI1) + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** if (SPIx == SPI1) + 39 .loc 1 141 3 view .LVU4 + 40 .loc 1 141 6 is_stmt 0 view .LVU5 + 41 0002 2D4A ldr r2, .L15 + 42 0004 9042 cmp r0, r2 + 43 0006 10D0 beq .L9 + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 44 .loc 1 135 15 view .LVU6 + 45 0008 0120 movs r0, #1 + 46 .LVL2: + 47 .L2: + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Force reset of SPI clock */ + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1); + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Release reset of SPI clock */ + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1); + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** status = SUCCESS; + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #endif /* SPI1 */ + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #if defined(SPI2) + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** if (SPIx == SPI2) + 48 .loc 1 153 3 is_stmt 1 view .LVU7 + 49 .loc 1 153 6 is_stmt 0 view .LVU8 + 50 000a 2C4A ldr r2, .L15+4 + 51 000c 9342 cmp r3, r2 + 52 000e 18D0 beq .L10 + 53 .LVL3: + 54 .L3: + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Force reset of SPI clock */ + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2); + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Release reset of SPI clock */ + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2); + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** status = SUCCESS; + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #endif /* SPI2 */ + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #if defined(SPI3) + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** if (SPIx == SPI3) + 55 .loc 1 165 3 is_stmt 1 view .LVU9 + 56 .loc 1 165 6 is_stmt 0 view .LVU10 + 57 0010 2B4A ldr r2, .L15+8 + 58 0012 9342 cmp r3, r2 + 59 0014 21D0 beq .L11 + 60 .LVL4: + 61 .L4: + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Force reset of SPI clock */ + ARM GAS /tmp/cczBZbME.s page 5 + + + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3); + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Release reset of SPI clock */ + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3); + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** status = SUCCESS; + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #endif /* SPI3 */ + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #if defined(SPI4) + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** if (SPIx == SPI4) + 62 .loc 1 177 3 is_stmt 1 view .LVU11 + 63 .loc 1 177 6 is_stmt 0 view .LVU12 + 64 0016 2B4A ldr r2, .L15+12 + 65 0018 9342 cmp r3, r2 + 66 001a 2AD0 beq .L12 + 67 .LVL5: + 68 .L5: + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Force reset of SPI clock */ + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4); + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Release reset of SPI clock */ + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4); + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** status = SUCCESS; + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #endif /* SPI4 */ + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #if defined(SPI5) + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** if (SPIx == SPI5) + 69 .loc 1 189 3 is_stmt 1 view .LVU13 + 70 .loc 1 189 6 is_stmt 0 view .LVU14 + 71 001c 2A4A ldr r2, .L15+16 + 72 001e 9342 cmp r3, r2 + 73 0020 33D0 beq .L13 + 74 .LVL6: + 75 .L6: + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Force reset of SPI clock */ + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5); + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Release reset of SPI clock */ + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5); + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** status = SUCCESS; + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #endif /* SPI5 */ + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #if defined(SPI6) + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** if (SPIx == SPI6) + 76 .loc 1 201 3 is_stmt 1 view .LVU15 + 77 .loc 1 201 6 is_stmt 0 view .LVU16 + 78 0022 2A4A ldr r2, .L15+20 + 79 0024 9342 cmp r3, r2 + 80 0026 3CD0 beq .L14 + 81 .LVL7: + 82 .L7: + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Force reset of SPI clock */ + ARM GAS /tmp/cczBZbME.s page 6 + + + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI6); + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Release reset of SPI clock */ + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI6); + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** status = SUCCESS; + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #endif /* SPI6 */ + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** return status; + 83 .loc 1 213 3 is_stmt 1 view .LVU17 + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 84 .loc 1 214 1 is_stmt 0 view .LVU18 + 85 0028 7047 bx lr + 86 .LVL8: + 87 .L9: + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 88 .loc 1 144 5 is_stmt 1 view .LVU19 + 89 .LBB34: + 90 .LBI34: + 91 .file 2 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @file stm32f7xx_ll_bus.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @verbatim + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @attention + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * Copyright (c) 2017 STMicroelectronics. + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * All rights reserved. + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * This software is licensed under terms that can be found in the LICENSE file in + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * the root directory of this software component. + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifndef __STM32F7xx_LL_BUS_H + ARM GAS /tmp/cczBZbME.s page 7 + + + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define __STM32F7xx_LL_BUS_H + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifdef __cplusplus + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** extern "C" { + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #include "stm32f7xx.h" + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @addtogroup STM32F7xx_LL_Driver + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC) + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOJ) + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOJ */ + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOK) + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOK */ + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DTCMRAM RCC_AHB1ENR_DTCMRAMEN + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DMA2D) + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DMA2D */ + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(ETH) + ARM GAS /tmp/cczBZbME.s page 8 + + + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* ETH */ + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_AXI RCC_AHB1LPENR_AXILPEN + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DCMI) + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DCMI */ + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(JPEG) + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_JPEG RCC_AHB2ENR_JPEGEN + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* JPEG */ + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CRYP) + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CRYP */ + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(AES) + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* AES */ + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(HASH) + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* HASH */ + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN + ARM GAS /tmp/cczBZbME.s page 9 + + + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPDIFRX) + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPDIFRX */ + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(I2C4) + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C4 RCC_APB1ENR_I2C4EN + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* I2C4 */ + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN2) + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN2 */ + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN3) + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN3 */ + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CEC) + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CEC */ + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC_APB1ENR_RTCEN) + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCEN + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* RCC_APB1ENR_RTCEN */ + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SDMMC2) + ARM GAS /tmp/cczBZbME.s page 10 + + + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC2 RCC_APB2ENR_SDMMC2EN + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SDMMC2 */ + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPI6) + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPI6 */ + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(LTDC) + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* LTDC */ + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DSI) + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DSI */ + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DFSDM1_Channel0) + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DFSDM1_Channel0 */ + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(MDIOS) + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_MDIO RCC_APB2ENR_MDIOEN + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* MDIOS */ + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(USB_HS_PHYC) + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_OTGPHYC RCC_APB2ENR_OTGPHYCEN + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* USB_HS_PHYC */ + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n + ARM GAS /tmp/cczBZbME.s page 11 + + + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_EnableClock\n + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n + ARM GAS /tmp/cczBZbME.s page 12 + + + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_IsEnabledClock\n + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_IsEnabledClock + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n + ARM GAS /tmp/cczBZbME.s page 13 + + + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_DisableClock\n + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_DisableClock + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1ENR, Periphs); + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + ARM GAS /tmp/cczBZbME.s page 14 + + + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1RSTR, Periphs); + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n + ARM GAS /tmp/cczBZbME.s page 15 + + + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1RSTR, Periphs); + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB1 peripheral clocks in low-power mode + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR AXILPEN LL_AHB1_GRP1_EnableClockLowPower\n + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n + ARM GAS /tmp/cczBZbME.s page 16 + + + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_AXI + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1LPENR, Periphs); + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB1 peripheral clocks in low-power mode + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n + ARM GAS /tmp/cczBZbME.s page 17 + + + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR AXILPEN LL_AHB1_GRP1_DisableClockLowPower\n + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_AXI + 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF + 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 + 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) + 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1LPENR, Periphs); + 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + ARM GAS /tmp/cczBZbME.s page 18 + + + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB2 AHB2 + 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB2 peripherals clock. + 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n + 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_EnableClock\n + 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n + 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n + 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n + 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n + 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock + 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) + 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2ENR, Periphs); + 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB2 peripheral clock is enabled or not + 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n + 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_IsEnabledClock\n + 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n + 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n + 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n + 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n + 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock + 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + ARM GAS /tmp/cczBZbME.s page 19 + + + 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) + 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); + 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB2 peripherals clock. + 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n + 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_DisableClock\n + 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n + 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n + 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n + 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n + 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock + 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) + 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2ENR, Periphs); + 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB2 peripherals reset. + 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n + 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR JPEGRST LL_AHB2_GRP1_ForceReset\n + 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n + 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n + 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n + 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n + 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset + 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) + 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + ARM GAS /tmp/cczBZbME.s page 20 + + + 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2RSTR, Periphs); + 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB2 peripherals reset. + 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n + 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR JPEGRST LL_AHB2_GRP1_ReleaseReset\n + 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n + 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n + 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n + 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n + 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset + 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) + 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2RSTR, Periphs); + 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB2 peripheral clocks in low-power mode + 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n + 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower + 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) + 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2LPENR, Periphs); + 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); + ARM GAS /tmp/cczBZbME.s page 21 + + + 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB2 peripheral clocks in low-power mode + 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n + 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_DisableClockLowPower\n + 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n + 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n + 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n + 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n + 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower + 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) + 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2LPENR, Periphs); + 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB3 AHB3 + 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB3 peripherals clock. + 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n + 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) + 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3ENR, Periphs); + 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); + 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + ARM GAS /tmp/cczBZbME.s page 22 + + + 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB3 peripheral clock is enabled or not + 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n + 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock + 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) + 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); + 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB3 peripherals clock. + 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n + 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock + 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) + 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3ENR, Periphs); + 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB3 peripherals reset. + 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n + 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset + 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) + 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3RSTR, Periphs); + 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB3 peripherals reset. + 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n + 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset + 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + ARM GAS /tmp/cczBZbME.s page 23 + + + 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) + 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3RSTR, Periphs); + 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB3 peripheral clocks in low-power mode + 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n + 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower + 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) + 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3LPENR, Periphs); + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); + 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB3 peripheral clocks in low-power mode + 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n + 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower + 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) + 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3LPENR, Periphs); + 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1 + 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ +1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB1 peripherals clock. +1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n +1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + ARM GAS /tmp/cczBZbME.s page 24 + + +1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n +1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n +1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n +1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n +1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n +1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n +1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n +1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n +1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n +1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n +1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n +1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n +1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n +1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n +1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n +1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n +1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n +1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n +1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n +1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_EnableClock\n +1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n +1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n +1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n +1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n +1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n +1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n +1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n +1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_EnableClock +1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR + ARM GAS /tmp/cczBZbME.s page 25 + + +1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; +1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); +1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; +1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not +1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n +1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n +1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n +1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n +1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n +1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n +1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n +1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n +1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n +1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n +1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n +1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n +1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n +1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n +1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n +1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n +1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n +1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n +1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n +1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n +1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n +1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_IsEnabledClock\n +1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n +1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n +1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n +1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n +1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n +1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n +1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n +1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n +1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_IsEnabledClock +1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + ARM GAS /tmp/cczBZbME.s page 26 + + +1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). +1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); +1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable APB1 peripherals clock. +1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n +1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n +1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n +1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n +1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n +1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n +1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n +1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n +1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n +1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n +1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n +1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n +1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n +1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n +1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n +1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n +1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n +1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n +1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n +1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n +1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n + ARM GAS /tmp/cczBZbME.s page 27 + + +1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_DisableClock\n +1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n +1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n +1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n +1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n +1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n +1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n +1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n +1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n +1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_DisableClock +1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); +1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force APB1 peripherals reset. +1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n +1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n +1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n +1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n + ARM GAS /tmp/cczBZbME.s page 28 + + +1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n +1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n +1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n +1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n +1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n +1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n +1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n +1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n +1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n +1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n +1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n +1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n +1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n +1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n +1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n +1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n +1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n +1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C4RST LL_APB1_GRP1_ForceReset\n +1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n +1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n +1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n +1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n +1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n +1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n +1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n +1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset +1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + ARM GAS /tmp/cczBZbME.s page 29 + + +1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); +1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release APB1 peripherals reset. +1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n +1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n +1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n +1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n +1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n +1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n +1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n +1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n +1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n +1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n +1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n +1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n +1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n +1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n +1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n +1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n +1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n +1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n +1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n +1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n +1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C4RST LL_APB1_GRP1_ReleaseReset\n +1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n +1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n +1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n +1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n +1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n +1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n +1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n +1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset +1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + ARM GAS /tmp/cczBZbME.s page 30 + + +1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB1 peripheral clocks in low-power mode +1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n +1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n +1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n +1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n +1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n +1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n +1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n +1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n +1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n +1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n +1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n +1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n +1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n +1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C4LPEN LL_APB1_GRP1_EnableClockLowPower\n +1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n +1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n +1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n +1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n +1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n +1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n +1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR RTCLPEN LL_APB1_GRP1_EnableClockLowPower + ARM GAS /tmp/cczBZbME.s page 31 + + +1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) +1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; +1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1LPENR, Periphs); +1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ +1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); +1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; +1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable APB1 peripheral clocks in low-power mode +1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n +1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n +1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n +1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n +1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n +1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n +1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n +1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n + ARM GAS /tmp/cczBZbME.s page 32 + + +1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n +1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n +1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n +1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n +1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n +1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C4LPEN LL_APB1_GRP1_DisableClockLowPower\n +1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n +1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n +1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n +1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n +1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n +1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n +1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR RTCLPEN LL_APB1_GRP1_DisableClockLowPower +1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + ARM GAS /tmp/cczBZbME.s page 33 + + +1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) +1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1LPENR, Periphs); +1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} +1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB2 APB2 +1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ +1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB2 peripherals clock. +1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n +1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n +1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n +1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n +1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n +1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n +1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n +1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n +1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC2EN LL_APB2_GRP1_EnableClock\n +1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n +1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n +1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n +1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n +1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n +1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n +1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n +1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n +1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n +1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n +1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n +1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n +1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n +1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR MDIOEN LL_APB2_GRP1_EnableClock\n +1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR OTGPHYCEN LL_APB2_GRP1_EnableClock +1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 +1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 +1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 +1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 +1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 +1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 +1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 +1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 +1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) +1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 +1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 +1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG +1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 +1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 +1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 +1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 +1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + ARM GAS /tmp/cczBZbME.s page 34 + + +1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 +1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 +1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) +1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) +1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) +1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) +1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) +1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; +1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); +1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB2ENR, Periphs); +1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; +1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if APB2 peripheral clock is enabled or not +1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n +1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n +1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n +1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n +1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n +1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n +1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n +1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n +1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC2EN LL_APB2_GRP1_IsEnabledClock\n +1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n +1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n +1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n +1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n +1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n +1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n +1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n +1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n +1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n +1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n +1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n +1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n +1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n +1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR MDIOEN LL_APB2_GRP1_IsEnabledClock\n +1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR OTGPHYCEN LL_APB2_GRP1_IsEnabledClock +1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 +1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 +1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 +1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 +1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 +1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 +1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 +1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 +1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) +1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + ARM GAS /tmp/cczBZbME.s page 35 + + +1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 +1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG +1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 +1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 +1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 +1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 +1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) +1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 +1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 +1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) +1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) +1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) +1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) +1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) +1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). +1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); +1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable APB2 peripherals clock. +1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n +1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n +1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n +1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n +1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n +1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n +1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n +1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n +1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC2EN LL_APB2_GRP1_DisableClock\n +1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n +1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n +1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n +1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n +1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n +1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n +1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n +1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n +1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n +1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n +1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n +1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n +1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n +1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR MDIOEN LL_APB2_GRP1_DisableClock\n +1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR OTGPHYCEN LL_APB2_GRP1_DisableClock +1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 +1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 +1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 +1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 +1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 +1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 +1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 + ARM GAS /tmp/cczBZbME.s page 36 + + +1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 +1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) +1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 +1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 +1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG +1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 +1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 +1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 +1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 +1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) +1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 +1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 +1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) +1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) +1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) +1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) +1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) +1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB2ENR, Periphs); +1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force APB2 peripherals reset. +1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n +1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n +1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n +1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n +1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n +1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n +1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SDMMC2RST LL_APB2_GRP1_ForceReset\n +1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n +1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n +1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n +1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n +1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n +1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n +1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n +1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n +1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n +1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n +1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n +1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n +1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n +1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR MDIORST LL_APB2_GRP1_ForceReset\n +1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ForceReset +1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ALL +1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 +1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 +1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 +1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 +1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC + ARM GAS /tmp/cczBZbME.s page 37 + + +1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 +1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) +1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 +1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 +1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG +1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 +1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 +1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 +1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 +1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) +1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 +1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 +1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) +1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) +1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) +1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) +1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) +1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) + 92 .loc 2 1768 22 view .LVU20 + 93 .LBB35: +1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2RSTR, Periphs); + 94 .loc 2 1770 3 view .LVU21 + 95 002a 02F58432 add r2, r2, #67584 + 96 002e 516A ldr r1, [r2, #36] + 97 0030 41F48051 orr r1, r1, #4096 + 98 0034 5162 str r1, [r2, #36] + 99 .LVL9: + 100 .loc 2 1770 3 is_stmt 0 view .LVU22 + 101 .LBE35: + 102 .LBE34: + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 103 .loc 1 147 5 is_stmt 1 view .LVU23 + 104 .LBB36: + 105 .LBI36: +1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release APB2 peripherals reset. +1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n +1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n +1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n +1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n +1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n +1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n +1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SDMMC2RST LL_APB2_GRP1_ReleaseReset\n +1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n +1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n +1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n +1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n +1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n +1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n +1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n + ARM GAS /tmp/cczBZbME.s page 38 + + +1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n +1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n +1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n +1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n +1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n +1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n +1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR MDIORST LL_APB2_GRP1_ReleaseReset\n +1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ReleaseReset +1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ALL +1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 +1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 +1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 +1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 +1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC +1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 +1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) +1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 +1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 +1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG +1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 +1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 +1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 +1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 +1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) +1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 +1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 +1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) +1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) +1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) +1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) +1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) +1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) + 106 .loc 2 1825 22 view .LVU24 + 107 .LBB37: +1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB2RSTR, Periphs); + 108 .loc 2 1827 3 view .LVU25 + 109 0036 516A ldr r1, [r2, #36] + 110 0038 21F48051 bic r1, r1, #4096 + 111 003c 5162 str r1, [r2, #36] + 112 .LVL10: + 113 .loc 2 1827 3 is_stmt 0 view .LVU26 + 114 .LBE37: + 115 .LBE36: + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 116 .loc 1 149 5 is_stmt 1 view .LVU27 + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 117 .loc 1 149 12 is_stmt 0 view .LVU28 + 118 003e 0020 movs r0, #0 + 119 .LVL11: + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 120 .loc 1 149 12 view .LVU29 + ARM GAS /tmp/cczBZbME.s page 39 + + + 121 0040 E3E7 b .L2 + 122 .LVL12: + 123 .L10: + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 124 .loc 1 156 5 is_stmt 1 view .LVU30 + 125 .LBB38: + 126 .LBI38: +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 127 .loc 2 1295 22 view .LVU31 + 128 .LBB39: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 129 .loc 2 1297 3 view .LVU32 + 130 0042 02F50032 add r2, r2, #131072 + 131 0046 116A ldr r1, [r2, #32] + 132 0048 41F48041 orr r1, r1, #16384 + 133 004c 1162 str r1, [r2, #32] + 134 .LVL13: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 135 .loc 2 1297 3 is_stmt 0 view .LVU33 + 136 .LBE39: + 137 .LBE38: + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 138 .loc 1 159 5 is_stmt 1 view .LVU34 + 139 .LBB40: + 140 .LBI40: +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 141 .loc 2 1367 22 view .LVU35 + 142 .LBB41: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 143 .loc 2 1369 3 view .LVU36 + 144 004e 116A ldr r1, [r2, #32] + 145 0050 21F48041 bic r1, r1, #16384 + 146 0054 1162 str r1, [r2, #32] + 147 .LVL14: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 148 .loc 2 1369 3 is_stmt 0 view .LVU37 + 149 .LBE41: + 150 .LBE40: + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 151 .loc 1 161 5 is_stmt 1 view .LVU38 + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 152 .loc 1 161 12 is_stmt 0 view .LVU39 + 153 0056 0020 movs r0, #0 + 154 0058 DAE7 b .L3 + 155 .LVL15: + 156 .L11: + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 157 .loc 1 168 5 is_stmt 1 view .LVU40 + 158 .LBB42: + 159 .LBI42: +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 160 .loc 2 1295 22 view .LVU41 + 161 .LBB43: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 162 .loc 2 1297 3 view .LVU42 + 163 005a 02F5FE32 add r2, r2, #130048 + 164 005e 116A ldr r1, [r2, #32] + ARM GAS /tmp/cczBZbME.s page 40 + + + 165 0060 41F40041 orr r1, r1, #32768 + 166 0064 1162 str r1, [r2, #32] + 167 .LVL16: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 168 .loc 2 1297 3 is_stmt 0 view .LVU43 + 169 .LBE43: + 170 .LBE42: + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 171 .loc 1 171 5 is_stmt 1 view .LVU44 + 172 .LBB44: + 173 .LBI44: +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 174 .loc 2 1367 22 view .LVU45 + 175 .LBB45: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 176 .loc 2 1369 3 view .LVU46 + 177 0066 116A ldr r1, [r2, #32] + 178 0068 21F40041 bic r1, r1, #32768 + 179 006c 1162 str r1, [r2, #32] + 180 .LVL17: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 181 .loc 2 1369 3 is_stmt 0 view .LVU47 + 182 .LBE45: + 183 .LBE44: + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 184 .loc 1 173 5 is_stmt 1 view .LVU48 + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 185 .loc 1 173 12 is_stmt 0 view .LVU49 + 186 006e 0020 movs r0, #0 + 187 0070 D1E7 b .L4 + 188 .LVL18: + 189 .L12: + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 190 .loc 1 180 5 is_stmt 1 view .LVU50 + 191 .LBB46: + 192 .LBI46: +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 193 .loc 2 1768 22 view .LVU51 + 194 .LBB47: +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 195 .loc 2 1770 3 view .LVU52 + 196 0072 02F58232 add r2, r2, #66560 + 197 0076 516A ldr r1, [r2, #36] + 198 0078 41F40051 orr r1, r1, #8192 + 199 007c 5162 str r1, [r2, #36] + 200 .LVL19: +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 201 .loc 2 1770 3 is_stmt 0 view .LVU53 + 202 .LBE47: + 203 .LBE46: + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 204 .loc 1 183 5 is_stmt 1 view .LVU54 + 205 .LBB48: + 206 .LBI48: +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 207 .loc 2 1825 22 view .LVU55 + 208 .LBB49: + ARM GAS /tmp/cczBZbME.s page 41 + + + 209 .loc 2 1827 3 view .LVU56 + 210 007e 516A ldr r1, [r2, #36] + 211 0080 21F40051 bic r1, r1, #8192 + 212 0084 5162 str r1, [r2, #36] + 213 .LVL20: + 214 .loc 2 1827 3 is_stmt 0 view .LVU57 + 215 .LBE49: + 216 .LBE48: + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 217 .loc 1 185 5 is_stmt 1 view .LVU58 + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 218 .loc 1 185 12 is_stmt 0 view .LVU59 + 219 0086 0020 movs r0, #0 + 220 0088 C8E7 b .L5 + 221 .LVL21: + 222 .L13: + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 223 .loc 1 192 5 is_stmt 1 view .LVU60 + 224 .LBB50: + 225 .LBI50: +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 226 .loc 2 1768 22 view .LVU61 + 227 .LBB51: +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 228 .loc 2 1770 3 view .LVU62 + 229 008a 02F56842 add r2, r2, #59392 + 230 008e 516A ldr r1, [r2, #36] + 231 0090 41F48011 orr r1, r1, #1048576 + 232 0094 5162 str r1, [r2, #36] + 233 .LVL22: +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 234 .loc 2 1770 3 is_stmt 0 view .LVU63 + 235 .LBE51: + 236 .LBE50: + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 237 .loc 1 195 5 is_stmt 1 view .LVU64 + 238 .LBB52: + 239 .LBI52: +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 240 .loc 2 1825 22 view .LVU65 + 241 .LBB53: + 242 .loc 2 1827 3 view .LVU66 + 243 0096 516A ldr r1, [r2, #36] + 244 0098 21F48011 bic r1, r1, #1048576 + 245 009c 5162 str r1, [r2, #36] + 246 .LVL23: + 247 .loc 2 1827 3 is_stmt 0 view .LVU67 + 248 .LBE53: + 249 .LBE52: + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 250 .loc 1 197 5 is_stmt 1 view .LVU68 + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 251 .loc 1 197 12 is_stmt 0 view .LVU69 + 252 009e 0020 movs r0, #0 + 253 00a0 BFE7 b .L6 + 254 .LVL24: + 255 .L14: + ARM GAS /tmp/cczBZbME.s page 42 + + + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 256 .loc 1 204 5 is_stmt 1 view .LVU70 + 257 .LBB54: + 258 .LBI54: +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 259 .loc 2 1768 22 view .LVU71 + 260 .LBB55: +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 261 .loc 2 1770 3 view .LVU72 + 262 00a2 0B4B ldr r3, .L15+24 + 263 .LVL25: +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 264 .loc 2 1770 3 is_stmt 0 view .LVU73 + 265 00a4 5A6A ldr r2, [r3, #36] + 266 00a6 42F40012 orr r2, r2, #2097152 + 267 00aa 5A62 str r2, [r3, #36] + 268 .LVL26: +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 269 .loc 2 1770 3 view .LVU74 + 270 .LBE55: + 271 .LBE54: + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 272 .loc 1 207 5 is_stmt 1 view .LVU75 + 273 .LBB56: + 274 .LBI56: +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 275 .loc 2 1825 22 view .LVU76 + 276 .LBB57: + 277 .loc 2 1827 3 view .LVU77 + 278 00ac 5A6A ldr r2, [r3, #36] + 279 00ae 22F40012 bic r2, r2, #2097152 + 280 00b2 5A62 str r2, [r3, #36] + 281 .LVL27: + 282 .loc 2 1827 3 is_stmt 0 view .LVU78 + 283 .LBE57: + 284 .LBE56: + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 285 .loc 1 209 5 is_stmt 1 view .LVU79 + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 286 .loc 1 209 12 is_stmt 0 view .LVU80 + 287 00b4 0020 movs r0, #0 + 288 00b6 B7E7 b .L7 + 289 .L16: + 290 .align 2 + 291 .L15: + 292 00b8 00300140 .word 1073819648 + 293 00bc 00380040 .word 1073756160 + 294 00c0 003C0040 .word 1073757184 + 295 00c4 00340140 .word 1073820672 + 296 00c8 00500140 .word 1073827840 + 297 00cc 00540140 .word 1073828864 + 298 00d0 00380240 .word 1073887232 + 299 .cfi_endproc + 300 .LFE451: + 302 .section .text.LL_SPI_Init,"ax",%progbits + 303 .align 1 + 304 .global LL_SPI_Init + ARM GAS /tmp/cczBZbME.s page 43 + + + 305 .syntax unified + 306 .thumb + 307 .thumb_func + 309 LL_SPI_Init: + 310 .LVL28: + 311 .LFB452: + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @note As some bits in SPI configuration registers can only be written when the SPI is disable + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERRO + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @param SPIx SPI Instance + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 312 .loc 1 225 1 is_stmt 1 view -0 + 313 .cfi_startproc + 314 @ args = 0, pretend = 0, frame = 0 + 315 @ frame_needed = 0, uses_anonymous_args = 0 + 316 @ link register save eliminated. + 317 .loc 1 225 1 is_stmt 0 view .LVU82 + 318 0000 0346 mov r3, r0 + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** ErrorStatus status = ERROR; + 319 .loc 1 226 3 is_stmt 1 view .LVU83 + 320 .LVL29: + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Check the SPI Instance SPIx*/ + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_SPI_ALL_INSTANCE(SPIx)); + 321 .loc 1 229 3 view .LVU84 + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Check the SPI parameters from SPI_InitStruct*/ + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection)); + 322 .loc 1 232 3 view .LVU85 + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode)); + 323 .loc 1 233 3 view .LVU86 + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth)); + 324 .loc 1 234 3 view .LVU87 + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity)); + 325 .loc 1 235 3 view .LVU88 + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase)); + 326 .loc 1 236 3 view .LVU89 + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS)); + 327 .loc 1 237 3 view .LVU90 + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate)); + 328 .loc 1 238 3 view .LVU91 + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder)); + 329 .loc 1 239 3 view .LVU92 + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation)); + 330 .loc 1 240 3 view .LVU93 + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** if (LL_SPI_IsEnabled(SPIx) == 0x00000000U) + 331 .loc 1 242 3 view .LVU94 + 332 .LBB58: + 333 .LBI58: + 334 .file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h" + ARM GAS /tmp/cczBZbME.s page 44 + + + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @file stm32f7xx_ll_spi.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Header file of SPI LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * This software is licensed under terms that can be found in the LICENSE file + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * in the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #ifndef STM32F7xx_LL_SPI_H + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define STM32F7xx_LL_SPI_H + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #ifdef __cplusplus + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** extern "C" { + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Includes ------------------------------------------------------------------*/ + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #include "stm32f7xx.h" + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @addtogroup STM32F7xx_LL_Driver + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defin + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL SPI + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private types -------------------------------------------------------------*/ + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private variables ---------------------------------------------------------*/ + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private macros ------------------------------------------------------------*/ + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported types ------------------------------------------------------------*/ + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief SPI Init structures definition + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** typedef struct + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mod + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_TRANSFER_M + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + ARM GAS /tmp/cczBZbME.s page 45 + + + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_MODE. + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t DataWidth; /*!< Specifies the SPI data width. + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_POLARITY. + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_PHASE. + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (N + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPR + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** @note The communication clock is derived from the master c + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref SPI_LL_EC_CRC_CALCUL + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter must be a number between Min_Data = 0x00 an + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } LL_SPI_InitTypeDef; + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */ + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported constants --------------------------------------------------------*/ + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants + ARM GAS /tmp/cczBZbME.s page 46 + + + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Flags defines which can be used with LL_SPI_ReadReg function + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format erro + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_IT IT Defines + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty inter + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_MODE Operation Mode + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuratio + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as de + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_PHASE Clock Phase + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition i + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_POLARITY Clock Polarity + ARM GAS /tmp/cczBZbME.s page 47 + + + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< Baud + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< Baud + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< Baud + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< Baud + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< Baud + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< Baud + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< Baud + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< Baud + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/recei + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/recei + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mo + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mod + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed inter + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in I + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in O + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) + ARM GAS /tmp/cczBZbME.s page 48 + + + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */ + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */ + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */ + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated i + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated i + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception em + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/ + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/ + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception fu + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level + ARM GAS /tmp/cczBZbME.s page 49 + + + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */ + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */ + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported macro ------------------------------------------------------------*/ + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Write a value in SPI register + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __INSTANCE__ SPI Instance + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __REG__ Register to be written + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __VALUE__ Value to be written in the register + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Read a value in SPI register + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __INSTANCE__ SPI Instance + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __REG__ Register to be read + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Register value + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + ARM GAS /tmp/cczBZbME.s page 50 + + + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported functions --------------------------------------------------------*/ + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_Configuration Configuration + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable SPI peripheral + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_Enable + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_SPE); + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable SPI peripheral + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note When disabling the SPI, follow the procedure described in the Reference Manual. + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_Disable + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if SPI peripheral is enabled + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SPE LL_SPI_IsEnabled + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) + 335 .loc 3 381 26 view .LVU95 + 336 .LBB59: + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); + 337 .loc 3 383 3 view .LVU96 + 338 .loc 3 383 12 is_stmt 0 view .LVU97 + 339 0002 0268 ldr r2, [r0] + 340 .loc 3 383 69 view .LVU98 + 341 0004 12F0400F tst r2, #64 + 342 0008 36D1 bne .L20 + 343 .LBE59: + 344 .LBE58: + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** ErrorStatus status = ERROR; + 345 .loc 1 225 1 view .LVU99 + 346 000a 10B4 push {r4} + 347 .LCFI0: + 348 .cfi_def_cfa_offset 4 + 349 .cfi_offset 4, -4 + ARM GAS /tmp/cczBZbME.s page 51 + + + 350 .LVL30: + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /*---------------------------- SPIx CR1 Configuration ------------------------ + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * Configure SPIx CR1 with parameters: + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - Master/Slave Mode: SPI_CR1_MSTR bit + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - ClockPolarity: SPI_CR1_CPOL bit + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - ClockPhase: SPI_CR1_CPHA bit + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - NSS management: SPI_CR1_SSM bit + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - BaudRate prescaler: SPI_CR1_BR[2:0] bits + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - BitOrder: SPI_CR1_LSBFIRST bit + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - CRCCalculation: SPI_CR1_CRCEN bit + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** MODIFY_REG(SPIx->CR1, + 351 .loc 1 255 5 is_stmt 1 view .LVU100 + 352 000c 0268 ldr r2, [r0] + 353 000e 1D48 ldr r0, .L27 + 354 .LVL31: + 355 .loc 1 255 5 is_stmt 0 view .LVU101 + 356 0010 1040 ands r0, r0, r2 + 357 0012 0A68 ldr r2, [r1] + 358 0014 4C68 ldr r4, [r1, #4] + 359 0016 2243 orrs r2, r2, r4 + 360 0018 CC68 ldr r4, [r1, #12] + 361 001a 2243 orrs r2, r2, r4 + 362 001c 0C69 ldr r4, [r1, #16] + 363 001e 2243 orrs r2, r2, r4 + 364 0020 4C69 ldr r4, [r1, #20] + 365 0022 2243 orrs r2, r2, r4 + 366 0024 8C69 ldr r4, [r1, #24] + 367 0026 2243 orrs r2, r2, r4 + 368 0028 CC69 ldr r4, [r1, #28] + 369 002a 2243 orrs r2, r2, r4 + 370 002c 0C6A ldr r4, [r1, #32] + 371 002e 2243 orrs r2, r2, r4 + 372 0030 1043 orrs r0, r0, r2 + 373 0032 1860 str r0, [r3] + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_CR1_CLEAR_MASK, + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase | + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_InitStruct->NSS | SPI_InitStruct->BaudRate | + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation); + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /*---------------------------- SPIx CR2 Configuration ------------------------ + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * Configure SPIx CR2 with parameters: + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - DataWidth: DS[3:0] bits + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - NSS management: SSOE bit + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** MODIFY_REG(SPIx->CR2, + 374 .loc 1 267 5 is_stmt 1 view .LVU102 + 375 0034 5868 ldr r0, [r3, #4] + 376 0036 144A ldr r2, .L27+4 + 377 0038 0240 ands r2, r2, r0 + 378 003a 8868 ldr r0, [r1, #8] + 379 003c B1F816C0 ldrh ip, [r1, #22] + 380 0040 40EA0C00 orr r0, r0, ip + 381 0044 0243 orrs r2, r2, r0 + ARM GAS /tmp/cczBZbME.s page 52 + + + 382 0046 5A60 str r2, [r3, #4] + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_CR2_DS | SPI_CR2_SSOE, + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U)); + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */ + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT) + 383 .loc 1 272 5 view .LVU103 + 384 .loc 1 272 23 is_stmt 0 view .LVU104 + 385 0048 8A68 ldr r2, [r1, #8] + 386 .loc 1 272 8 view .LVU105 + 387 004a B2F5006F cmp r2, #2048 + 388 004e 03D2 bcs .L19 + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER); + 389 .loc 1 274 7 is_stmt 1 view .LVU106 + 390 .LVL32: + 391 .LBB60: + 392 .LBI60: + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set SPI operation mode to Master or Slave + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 MSTR LL_SPI_SetMode\n + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 SSI LL_SPI_SetMode + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Mode This parameter can be one of the following values: + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_MASTER + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_SLAVE + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get SPI operation mode (Master or Slave) + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 MSTR LL_SPI_GetMode\n + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 SSI LL_SPI_GetMode + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_MASTER + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MODE_SLAVE + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set serial protocol used + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRF LL_SPI_SetStandard + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Standard This parameter can be one of the following values: + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + ARM GAS /tmp/cczBZbME.s page 53 + + + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_TI + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get serial protocol used + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRF LL_SPI_GetStandard + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PROTOCOL_TI + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set clock phase + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * This bit is not used in SPI TI mode. + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPHA LL_SPI_SetClockPhase + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param ClockPhase This parameter can be one of the following values: + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_1EDGE + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_2EDGE + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get clock phase + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPHA LL_SPI_GetClockPhase + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_1EDGE + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_PHASE_2EDGE + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set clock polarity + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * This bit is not used in SPI TI mode. + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param ClockPolarity This parameter can be one of the following values: + ARM GAS /tmp/cczBZbME.s page 54 + + + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_LOW + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_HIGH + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get clock polarity + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_LOW + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_POLARITY_HIGH + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set baud rate prescaler + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Pr + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param BaudRate This parameter can be one of the following values: + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get baud rate prescaler + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + ARM GAS /tmp/cczBZbME.s page 55 + + + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set transfer bit order + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param BitOrder This parameter can be one of the following values: + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_LSB_FIRST + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MSB_FIRST + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get transfer bit order + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_LSB_FIRST + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_MSB_FIRST + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set transfer direction mode + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note For Half-Duplex mode, Rx Direction is set by default. + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-D + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIMODE LL_SPI_SetTransferDirection\n + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIOE LL_SPI_SetTransferDirection + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param TransferDirection This parameter can be one of the following values: + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_FULL_DUPLEX + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_SIMPLEX_RX + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_RX + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_TX + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get transfer direction mode + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIMODE LL_SPI_GetTransferDirection\n + ARM GAS /tmp/cczBZbME.s page 56 + + + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * CR1 BIDIOE LL_SPI_GetTransferDirection + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_FULL_DUPLEX + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_SIMPLEX_RX + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_RX + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_HALF_DUPLEX_TX + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set frame data width + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 DS LL_SPI_SetDataWidth + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param DataWidth This parameter can be one of the following values: + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_4BIT + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_5BIT + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_6BIT + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_7BIT + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_8BIT + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_9BIT + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_10BIT + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_11BIT + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_12BIT + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_13BIT + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_14BIT + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_15BIT + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_16BIT + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth); + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get frame data width + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 DS LL_SPI_GetDataWidth + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_4BIT + 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_5BIT + 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_6BIT + 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_7BIT + 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_8BIT + 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_9BIT + 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_10BIT + 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_11BIT + 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_12BIT + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_13BIT + 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_14BIT + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_15BIT + 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DATAWIDTH_16BIT + 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + ARM GAS /tmp/cczBZbME.s page 57 + + + 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) + 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); + 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set threshold of RXFIFO that triggers an RXNE event + 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold + 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Threshold This parameter can be one of the following values: + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_HALF + 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) + 393 .loc 3 665 22 view .LVU107 + 394 .LBB61: + 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold); + 395 .loc 3 667 3 view .LVU108 + 396 0050 5A68 ldr r2, [r3, #4] + 397 0052 42F48052 orr r2, r2, #4096 + 398 0056 5A60 str r2, [r3, #4] + 399 .LVL33: + 400 .L19: + 401 .loc 3 667 3 is_stmt 0 view .LVU109 + 402 .LBE61: + 403 .LBE60: + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /*---------------------------- SPIx CRCPR Configuration ---------------------- + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * Configure SPIx CRCPR with parameters: + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - CRCPoly: CRCPOLY[15:0] bits + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE) + 404 .loc 1 281 5 is_stmt 1 view .LVU110 + 405 .loc 1 281 23 is_stmt 0 view .LVU111 + 406 0058 0A6A ldr r2, [r1, #32] + 407 .loc 1 281 8 view .LVU112 + 408 005a B2F5005F cmp r2, #8192 + 409 005e 07D0 beq .L26 + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly)); + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly); + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** status = SUCCESS; + 410 .loc 1 286 12 view .LVU113 + 411 0060 0020 movs r0, #0 + 412 .L18: + 413 .LVL34: + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); + 414 .loc 1 290 3 is_stmt 1 view .LVU114 + 415 0062 DA69 ldr r2, [r3, #28] + 416 0064 22F40062 bic r2, r2, #2048 + ARM GAS /tmp/cczBZbME.s page 58 + + + 417 0068 DA61 str r2, [r3, #28] + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** return status; + 418 .loc 1 291 3 view .LVU115 + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 419 .loc 1 292 1 is_stmt 0 view .LVU116 + 420 006a 5DF8044B ldr r4, [sp], #4 + 421 .LCFI1: + 422 .cfi_remember_state + 423 .cfi_restore 4 + 424 .cfi_def_cfa_offset 0 + 425 006e 7047 bx lr + 426 .LVL35: + 427 .L26: + 428 .LCFI2: + 429 .cfi_restore_state + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly); + 430 .loc 1 283 7 is_stmt 1 view .LVU117 + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 431 .loc 1 284 7 view .LVU118 + 432 .LBB62: + 433 .LBI62: + 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get threshold of RXFIFO that triggers an RXNE event + 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold + 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_HALF + 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER + 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) + 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); + 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_CRC_Management CRC Management + 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable CRC + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_EnableCRC + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) + 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); + 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + ARM GAS /tmp/cczBZbME.s page 59 + + + 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable CRC + 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_DisableCRC + 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) + 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); + 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if CRC is enabled + 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC + 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) + 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); + 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set CRC Length + 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth + 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param CRCLength This parameter can be one of the following values: + 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_8BIT + 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_16BIT + 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) + 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength); + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get CRC Length + 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth + 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_8BIT + 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_CRC_16BIT + 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) + 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); + 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set CRCNext to transfer CRC on the line + 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. + 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext + 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + ARM GAS /tmp/cczBZbME.s page 60 + + + 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) + 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); + 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set polynomial for CRC calculation + 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial + 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF + 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) + 434 .loc 3 774 22 view .LVU119 + 435 .LBB63: + 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly); + 436 .loc 3 776 3 view .LVU120 + 437 0070 8A8C ldrh r2, [r1, #36] + 438 0072 1A61 str r2, [r3, #16] + 439 .LVL36: + 440 .loc 3 776 3 is_stmt 0 view .LVU121 + 441 .LBE63: + 442 .LBE62: + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 443 .loc 1 286 12 view .LVU122 + 444 0074 0020 movs r0, #0 + 445 .LBB65: + 446 .LBB64: + 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 447 .loc 3 777 1 view .LVU123 + 448 0076 F4E7 b .L18 + 449 .LVL37: + 450 .L20: + 451 .LCFI3: + 452 .cfi_def_cfa_offset 0 + 453 .cfi_restore 4 + 454 .loc 3 777 1 view .LVU124 + 455 .LBE64: + 456 .LBE65: + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 457 .loc 1 226 15 view .LVU125 + 458 0078 0120 movs r0, #1 + 459 .LVL38: + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** return status; + 460 .loc 1 290 3 is_stmt 1 view .LVU126 + 461 007a DA69 ldr r2, [r3, #28] + 462 007c 22F40062 bic r2, r2, #2048 + 463 0080 DA61 str r2, [r3, #28] + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 464 .loc 1 291 3 view .LVU127 + 465 .loc 1 292 1 is_stmt 0 view .LVU128 + 466 0082 7047 bx lr + 467 .L28: + 468 .align 2 + 469 .L27: + ARM GAS /tmp/cczBZbME.s page 61 + + + 470 0084 4000FFFF .word -65472 + 471 0088 FBF0FFFF .word -3845 + 472 .cfi_endproc + 473 .LFE452: + 475 .section .text.LL_SPI_StructInit,"ax",%progbits + 476 .align 1 + 477 .global LL_SPI_StructInit + 478 .syntax unified + 479 .thumb + 480 .thumb_func + 482 LL_SPI_StructInit: + 483 .LVL39: + 484 .LFB453: + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @brief Set each @ref LL_SPI_InitTypeDef field to default value. + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * whose fields will be set to default values. + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @retval None + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 485 .loc 1 301 1 is_stmt 1 view -0 + 486 .cfi_startproc + 487 @ args = 0, pretend = 0, frame = 0 + 488 @ frame_needed = 0, uses_anonymous_args = 0 + 489 @ link register save eliminated. + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Set SPI_InitStruct fields to default values */ + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX; + 490 .loc 1 303 3 view .LVU130 + 491 .loc 1 303 37 is_stmt 0 view .LVU131 + 492 0000 0023 movs r3, #0 + 493 0002 0360 str r3, [r0] + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE; + 494 .loc 1 304 3 is_stmt 1 view .LVU132 + 495 .loc 1 304 37 is_stmt 0 view .LVU133 + 496 0004 4360 str r3, [r0, #4] + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT; + 497 .loc 1 305 3 is_stmt 1 view .LVU134 + 498 .loc 1 305 37 is_stmt 0 view .LVU135 + 499 0006 4FF4E062 mov r2, #1792 + 500 000a 8260 str r2, [r0, #8] + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW; + 501 .loc 1 306 3 is_stmt 1 view .LVU136 + 502 .loc 1 306 37 is_stmt 0 view .LVU137 + 503 000c C360 str r3, [r0, #12] + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE; + 504 .loc 1 307 3 is_stmt 1 view .LVU138 + 505 .loc 1 307 37 is_stmt 0 view .LVU139 + 506 000e 0361 str r3, [r0, #16] + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT; + 507 .loc 1 308 3 is_stmt 1 view .LVU140 + 508 .loc 1 308 37 is_stmt 0 view .LVU141 + 509 0010 4361 str r3, [r0, #20] + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2; + 510 .loc 1 309 3 is_stmt 1 view .LVU142 + 511 .loc 1 309 37 is_stmt 0 view .LVU143 + ARM GAS /tmp/cczBZbME.s page 62 + + + 512 0012 8361 str r3, [r0, #24] + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST; + 513 .loc 1 310 3 is_stmt 1 view .LVU144 + 514 .loc 1 310 37 is_stmt 0 view .LVU145 + 515 0014 C361 str r3, [r0, #28] + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; + 516 .loc 1 311 3 is_stmt 1 view .LVU146 + 517 .loc 1 311 37 is_stmt 0 view .LVU147 + 518 0016 0362 str r3, [r0, #32] + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_InitStruct->CRCPoly = 7U; + 519 .loc 1 312 3 is_stmt 1 view .LVU148 + 520 .loc 1 312 37 is_stmt 0 view .LVU149 + 521 0018 0723 movs r3, #7 + 522 001a 4362 str r3, [r0, #36] + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 523 .loc 1 313 1 view .LVU150 + 524 001c 7047 bx lr + 525 .cfi_endproc + 526 .LFE453: + 528 .section .text.LL_I2S_DeInit,"ax",%progbits + 529 .align 1 + 530 .global LL_I2S_DeInit + 531 .syntax unified + 532 .thumb + 533 .thumb_func + 535 LL_I2S_DeInit: + 536 .LVL40: + 537 .LFB454: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @} + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @} + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @} + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @addtogroup I2S_LL + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @{ + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private types -------------------------------------------------------------*/ + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private variables ---------------------------------------------------------*/ + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private constants ---------------------------------------------------------*/ + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @defgroup I2S_LL_Private_Constants I2S Private Constants + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @{ + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* I2S registers Masks */ + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD ) + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define I2S_I2SPR_CLEAR_MASK 0x0002U + ARM GAS /tmp/cczBZbME.s page 63 + + + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @} + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private macros ------------------------------------------------------------*/ + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @defgroup I2S_LL_Private_Macros I2S Private Macros + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @{ + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \ + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \ + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \ + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \ + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_POLARITY_HIGH)) + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \ + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_STANDARD_MSB) \ + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_STANDARD_LSB) \ + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \ + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \ + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \ + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \ + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_MODE_MASTER_RX)) + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \ + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \ + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \ + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U) + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \ + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @} + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Private function prototypes -----------------------------------------------*/ + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Exported functions --------------------------------------------------------*/ + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @addtogroup I2S_LL_Exported_Functions + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @{ + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** @addtogroup I2S_LL_EF_Init + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @{ + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @brief De-initialize the SPI/I2S registers to their default reset values. + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @param SPIx SPI Instance + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @retval An ErrorStatus enumeration value: + ARM GAS /tmp/cczBZbME.s page 64 + + + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - SUCCESS: SPI registers are de-initialized + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - ERROR: SPI registers are not de-initialized + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 538 .loc 1 404 1 is_stmt 1 view -0 + 539 .cfi_startproc + 540 @ args = 0, pretend = 0, frame = 0 + 541 @ frame_needed = 0, uses_anonymous_args = 0 + 542 .loc 1 404 1 is_stmt 0 view .LVU152 + 543 0000 08B5 push {r3, lr} + 544 .LCFI4: + 545 .cfi_def_cfa_offset 8 + 546 .cfi_offset 3, -8 + 547 .cfi_offset 14, -4 + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** return LL_SPI_DeInit(SPIx); + 548 .loc 1 405 3 is_stmt 1 view .LVU153 + 549 .loc 1 405 10 is_stmt 0 view .LVU154 + 550 0002 FFF7FEFF bl LL_SPI_DeInit + 551 .LVL41: + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 552 .loc 1 406 1 view .LVU155 + 553 0006 08BD pop {r3, pc} + 554 .cfi_endproc + 555 .LFE454: + 557 .section .text.LL_I2S_Init,"ax",%progbits + 558 .align 1 + 559 .global LL_I2S_Init + 560 .syntax unified + 561 .thumb + 562 .thumb_func + 564 LL_I2S_Init: + 565 .LVL42: + 566 .LFB455: + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStru + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @note As some bits in SPI configuration registers can only be written when the SPI is disable + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERRO + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @param SPIx SPI Instance + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @retval An ErrorStatus enumeration value: + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - SUCCESS: SPI registers are Initialized + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - ERROR: SPI registers are not Initialized + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 567 .loc 1 419 1 is_stmt 1 view -0 + 568 .cfi_startproc + 569 @ args = 0, pretend = 0, frame = 0 + 570 @ frame_needed = 0, uses_anonymous_args = 0 + 571 .loc 1 419 1 is_stmt 0 view .LVU157 + 572 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 573 .LCFI5: + 574 .cfi_def_cfa_offset 24 + 575 .cfi_offset 3, -24 + 576 .cfi_offset 4, -20 + ARM GAS /tmp/cczBZbME.s page 65 + + + 577 .cfi_offset 5, -16 + 578 .cfi_offset 6, -12 + 579 .cfi_offset 7, -8 + 580 .cfi_offset 14, -4 + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** uint32_t i2sdiv = 2U; + 581 .loc 1 420 3 is_stmt 1 view .LVU158 + 582 .LVL43: + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** uint32_t i2sodd = 0U; + 583 .loc 1 421 3 view .LVU159 + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** uint32_t packetlength = 1U; + 584 .loc 1 422 3 view .LVU160 + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** uint32_t tmp; + 585 .loc 1 423 3 view .LVU161 + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** uint32_t sourceclock; + 586 .loc 1 424 3 view .LVU162 + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** ErrorStatus status = ERROR; + 587 .loc 1 425 3 view .LVU163 + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Check the I2S parameters */ + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_I2S_ALL_INSTANCE(SPIx)); + 588 .loc 1 428 3 view .LVU164 + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); + 589 .loc 1 429 3 view .LVU165 + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); + 590 .loc 1 430 3 view .LVU166 + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); + 591 .loc 1 431 3 view .LVU167 + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput)); + 592 .loc 1 432 3 view .LVU168 + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq)); + 593 .loc 1 433 3 view .LVU169 + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity)); + 594 .loc 1 434 3 view .LVU170 + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** if (LL_I2S_IsEnabled(SPIx) == 0x00000000U) + 595 .loc 1 436 3 view .LVU171 + 596 .LBB66: + 597 .LBI66: + 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get polynomial for CRC calculation + 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial + 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) + 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->CRCPR)); + 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get Rx CRC + 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC + 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) + ARM GAS /tmp/cczBZbME.s page 66 + + + 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->RXCRCR)); + 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get Tx CRC + 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC + 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) + 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_REG(SPIx->TXCRCR)); + 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management + 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set NSS mode + 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. + 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n + 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 SSOE LL_SPI_SetNSSMode + 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param NSS This parameter can be one of the following values: + 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_SOFT + 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_INPUT + 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_OUTPUT + 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) + 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); + 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); + 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get NSS mode + 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n + 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 SSOE LL_SPI_GetNSSMode + 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_SOFT + 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_INPUT + 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_NSS_HARD_OUTPUT + 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) + 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); + 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); + 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (Ssm | Ssoe); + 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + ARM GAS /tmp/cczBZbME.s page 67 + + + 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable NSS pulse management + 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S + 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt + 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) + 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_NSSP); + 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable NSS pulse management + 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S + 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt + 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None + 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) + 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP); + 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if NSS pulse is enabled + 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit should not be changed when communication is ongoing. This bit is not used in S + 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse + 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) + 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); + 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} + 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management + 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ + 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Rx buffer is not empty + 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE + 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) + 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); + 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + ARM GAS /tmp/cczBZbME.s page 68 + + + 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Tx buffer is empty + 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE + 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) + 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); + 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get CRC error flag + 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR + 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) + 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); + 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get mode fault error flag + 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF + 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) + 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); + 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get overrun error flag + 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR + 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) + 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); + 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get busy flag + 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note The BSY flag is cleared under any one of the following conditions: + 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -When the SPI is correctly disabled + 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -When a fault is detected in Master mode (MODF bit set to 1) + 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -In Master mode, when it finishes a data transmission and no new data is ready to be + 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * sent + 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between + 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * each data transfer. + 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY + 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) + ARM GAS /tmp/cczBZbME.s page 69 + + + 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); + 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get frame format error flag + 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE + 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). + 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) + 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); + 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get FIFO reception Level + 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel + 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance + 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: + 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_EMPTY + 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL + 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_HALF_FULL + 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_RX_FIFO_FULL + 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) + 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); + 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get FIFO Transmission Level +1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel +1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: +1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_EMPTY +1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL +1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_HALF_FULL +1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_TX_FIFO_FULL +1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) +1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); +1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear CRC error flag +1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR +1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) +1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); +1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + ARM GAS /tmp/cczBZbME.s page 70 + + +1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear mode fault error flag +1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note Clearing this flag is done by a read access to the SPIx_SR +1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * register followed by a write access to the SPIx_CR1 register +1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR MODF LL_SPI_ClearFlag_MODF +1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) +1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint32_t tmpreg_sr; +1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg_sr = SPIx->SR; +1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg_sr; +1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear overrun error flag +1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note Clearing this flag is done by a read access to the SPIx_DR +1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * register followed by a read access to the SPIx_SR register +1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR OVR LL_SPI_ClearFlag_OVR +1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint32_t tmpreg; +1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg = SPIx->DR; +1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg; +1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg = SPIx->SR; +1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg; +1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Clear frame format error flag +1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note Clearing this flag is done by reading SPIx_SR register +1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll SR FRE LL_SPI_ClearFlag_FRE +1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) +1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint32_t tmpreg; +1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** tmpreg = SPIx->SR; +1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** (void) tmpreg; +1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_IT_Management Interrupt Management +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable error interrupt +1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR + ARM GAS /tmp/cczBZbME.s page 71 + + +1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR +1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) +1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); +1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable Rx buffer not empty interrupt +1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE +1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) +1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable Tx buffer empty interrupt +1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE +1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) +1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); +1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable error interrupt +1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR +1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR +1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) +1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); +1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable Rx buffer not empty interrupt +1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE +1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) +1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable Tx buffer empty interrupt +1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE + ARM GAS /tmp/cczBZbME.s page 72 + + +1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) +1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); +1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if error interrupt is enabled +1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR +1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). +1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); +1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Rx buffer not empty interrupt is enabled +1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE +1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). +1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); +1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if Tx buffer empty interrupt +1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE +1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). +1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); +1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_DMA_Management DMA Management +1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable DMA Rx +1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX +1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) +1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { + ARM GAS /tmp/cczBZbME.s page 73 + + +1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable DMA Rx +1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX +1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) +1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if DMA Rx is enabled +1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX +1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). +1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); +1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Enable DMA Tx +1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX +1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) +1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable DMA Tx +1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX +1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) +1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if DMA Tx is enabled +1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX +1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). +1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); +1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } + ARM GAS /tmp/cczBZbME.s page 74 + + +1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set parity of Last DMA reception +1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX +1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Parity This parameter can be one of the following values: +1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD +1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN +1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) +1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos)); +1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get parity configuration for Last DMA reception +1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX +1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: +1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD +1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN +1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) +1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); +1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Set parity of Last DMA transmission +1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX +1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param Parity This parameter can be one of the following values: +1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD +1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN +1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) +1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos)); +1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get parity configuration for Last DMA transmission +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX +1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Returned value can be one of the following values: +1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_ODD +1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @arg @ref LL_SPI_DMA_PARITY_EVEN +1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) +1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); +1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Get the data register address used for DMA transfer + ARM GAS /tmp/cczBZbME.s page 75 + + +1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_DMA_GetRegAddr +1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Address of data register +1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint32_t) &(SPIx->DR); +1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_DATA_Management DATA Management +1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Read 8-Bits in the data register +1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_ReceiveData8 +1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF +1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) +1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (*((__IO uint8_t *)&SPIx->DR)); +1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Read 16-Bits in the data register +1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_ReceiveData16 +1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF +1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) +1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return (uint16_t)(READ_REG(SPIx->DR)); +1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Write 8-Bits in the data register +1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_TransmitData8 +1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF +1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) +1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (__GNUC__) +1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR); +1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; +1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #else +1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *((__IO uint8_t *)&SPIx->DR) = TxData; +1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* __GNUC__ */ +1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + ARM GAS /tmp/cczBZbME.s page 76 + + +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Write 16-Bits in the data register +1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll DR DR LL_SPI_TransmitData16 +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF +1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined (__GNUC__) +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR); +1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** *spidr = TxData; +1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #else +1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SPIx->DR = TxData; +1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* __GNUC__ */ +1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) +1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions +1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); +1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); +1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */ +1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL I2S +1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private variables ---------------------------------------------------------*/ +1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private constants ---------------------------------------------------------*/ +1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Private macros ------------------------------------------------------------*/ +1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported types ------------------------------------------------------------*/ +1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) +1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure +1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief I2S Init structure definition +1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ + ARM GAS /tmp/cczBZbME.s page 77 + + +1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** typedef struct +1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Mode; /*!< Specifies the I2S operating mode. +1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref I2S_LL_EC_MODE +1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func +1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t Standard; /*!< Specifies the standard used for the I2S communication. +1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref I2S_LL_EC_STANDARD +1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func +1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. +1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref I2S_LL_EC_DATA_FORMA +1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func +1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. +1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPU +1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func +1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication +1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ +1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** Audio Frequency can be modified afterwards using Reference +1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** and unitary functions @ref LL_I2S_SetPrescalerLinear() and +1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock. +1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This parameter can be a value of @ref I2S_LL_EC_POLARITY +1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** This feature can be modified afterwards using unitary func +1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } LL_I2S_InitTypeDef; +1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /*USE_FULL_LL_DRIVER*/ +1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported constants --------------------------------------------------------*/ +1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants +1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines +1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Flags defines which can be used with LL_I2S_ReadReg function +1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag +1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag +1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag + ARM GAS /tmp/cczBZbME.s page 78 + + +1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag +1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag +1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format erro +1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup SPI_LL_EC_IT IT Defines +1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions +1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty inter +1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt +1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable +1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EC_DATA_FORMAT Data format +1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data +1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data +1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data +1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EC_POLARITY Clock Polarity +1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low +1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is hig +1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EC_STANDARD I2s Standard +1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_STANDARD_PHILIPS 0x00000000U +1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) +1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) +1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) +1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCF +1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EC_MODE Operation Mode +1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave +1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave +1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Maste +1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Maste + ARM GAS /tmp/cczBZbME.s page 79 + + +1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor +1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider +1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider +1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #if defined(USE_FULL_LL_DRIVER) +1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output +1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is di +1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is en +1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency +1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 +1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 +1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 +1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 +1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 +1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 +1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 +1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 +1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 +1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2 +1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #endif /* USE_FULL_LL_DRIVER */ +1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported macro ------------------------------------------------------------*/ +1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros +1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros +1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** + ARM GAS /tmp/cczBZbME.s page 80 + + +1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Write a value in I2S register +1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __INSTANCE__ I2S Instance +1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __REG__ Register to be written +1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __VALUE__ Value to be written in the register +1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE +1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Read a value in I2S register +1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __INSTANCE__ I2S Instance +1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param __REG__ Register to be read +1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval Register value +1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @} +1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /* Exported functions --------------------------------------------------------*/ +1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions +1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** @defgroup I2S_LL_EF_Configuration Configuration +1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @{ +1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Select I2S mode and Enable I2S peripheral +1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n +1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * I2SCFGR I2SE LL_I2S_Enable +1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx) +1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** +1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Disable I2S peripheral +1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll I2SCFGR I2SE LL_I2S_Disable +1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval None +1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) +1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** } +1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** + ARM GAS /tmp/cczBZbME.s page 81 + + +1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** /** +1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @brief Check if I2S peripheral is enabled +1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled +1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @param SPIx SPI Instance +1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** * @retval State of bit (1 or 0). +1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** */ +1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx) + 598 .loc 3 1658 26 view .LVU172 + 599 .LBB67: +1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** { +1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h **** return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL); + 600 .loc 3 1660 3 view .LVU173 + 601 .loc 3 1660 12 is_stmt 0 view .LVU174 + 602 0002 C669 ldr r6, [r0, #28] + 603 .loc 3 1660 83 view .LVU175 + 604 0004 16F48066 ands r6, r6, #1024 + 605 0008 49D1 bne .L39 + 606 000a 0446 mov r4, r0 + 607 000c 0D46 mov r5, r1 + 608 .LVL44: + 609 .loc 3 1660 83 view .LVU176 + 610 .LBE67: + 611 .LBE66: + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /*---------------------------- SPIx I2SCFGR Configuration -------------------- + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * Configure SPIx I2SCFGR with parameters: + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - ClockPolarity: SPI_I2SCFGR_CKPOL bit + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Write to SPIx I2SCFGR */ + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** MODIFY_REG(SPIx->I2SCFGR, + 612 .loc 1 447 5 is_stmt 1 view .LVU177 + 613 000e C269 ldr r2, [r0, #28] + 614 0010 244B ldr r3, .L45 + 615 0012 1340 ands r3, r3, r2 + 616 0014 0A68 ldr r2, [r1] + 617 0016 4968 ldr r1, [r1, #4] + 618 .LVL45: + 619 .loc 1 447 5 is_stmt 0 view .LVU178 + 620 0018 0A43 orrs r2, r2, r1 + 621 001a A968 ldr r1, [r5, #8] + 622 001c 0A43 orrs r2, r2, r1 + 623 001e 6969 ldr r1, [r5, #20] + 624 0020 0A43 orrs r2, r2, r1 + 625 0022 1343 orrs r3, r3, r2 + 626 0024 43F40063 orr r3, r3, #2048 + 627 0028 C361 str r3, [r0, #28] + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** I2S_I2SCFGR_CLEAR_MASK, + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** I2S_InitStruct->Mode | I2S_InitStruct->Standard | + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** SPI_I2SCFGR_I2SMOD); + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /*---------------------------- SPIx I2SPR Configuration ---------------------- + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * Configure SPIx I2SPR with parameters: + ARM GAS /tmp/cczBZbME.s page 82 + + + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - MCLKOutput: SPI_I2SPR_MCKOE bit + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv) + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * else, default values are used: i2sodd = 0U, i2sdiv = 2U. + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT) + 628 .loc 1 462 5 is_stmt 1 view .LVU179 + 629 .loc 1 462 23 is_stmt 0 view .LVU180 + 630 002a 2B69 ldr r3, [r5, #16] + 631 .loc 1 462 8 view .LVU181 + 632 002c 022B cmp r3, #2 + 633 002e 32D0 beq .L40 + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Check the frame length (For the Prescaler computing) + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U). + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B) + 634 .loc 1 467 7 is_stmt 1 view .LVU182 + 635 .loc 1 467 25 is_stmt 0 view .LVU183 + 636 0030 AB68 ldr r3, [r5, #8] + 637 .loc 1 467 10 view .LVU184 + 638 0032 2BBB cbnz r3, .L41 + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** uint32_t tmp; + 639 .loc 1 422 12 view .LVU185 + 640 0034 0127 movs r7, #1 + 641 .L35: + 642 .LVL46: + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Packet length is 32 bits */ + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** packetlength = 2U; + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* If an external I2S clock has to be used, the specific define should be set + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** in the project configuration or in the stm32f7xx_ll_rcc.h file */ + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Get the I2S source clock value */ + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE); + 643 .loc 1 476 7 is_stmt 1 view .LVU186 + 644 .loc 1 476 21 is_stmt 0 view .LVU187 + 645 0036 4FF40000 mov r0, #8388608 + 646 .LVL47: + 647 .loc 1 476 21 view .LVU188 + 648 003a FFF7FEFF bl LL_RCC_GetI2SClockFreq + 649 .LVL48: + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Compute the Real divider depending on the MCLK output state with a floating point */ + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE) + 650 .loc 1 479 7 is_stmt 1 view .LVU189 + 651 .loc 1 479 25 is_stmt 0 view .LVU190 + 652 003e EB68 ldr r3, [r5, #12] + 653 .loc 1 479 10 view .LVU191 + 654 0040 B3F5007F cmp r3, #512 + 655 0044 1ED0 beq .L44 + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* MCLK output is enabled */ + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); + ARM GAS /tmp/cczBZbME.s page 83 + + + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** else + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* MCLK output is disabled */ + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); + 656 .loc 1 487 9 is_stmt 1 view .LVU192 + 657 .loc 1 487 39 is_stmt 0 view .LVU193 + 658 0046 7F01 lsls r7, r7, #5 + 659 .LVL49: + 660 .loc 1 487 32 view .LVU194 + 661 0048 B0FBF7F0 udiv r0, r0, r7 + 662 .LVL50: + 663 .loc 1 487 56 view .LVU195 + 664 004c 00EB8000 add r0, r0, r0, lsl #2 + 665 0050 4300 lsls r3, r0, #1 + 666 .loc 1 487 79 view .LVU196 + 667 0052 2A69 ldr r2, [r5, #16] + 668 .loc 1 487 63 view .LVU197 + 669 0054 B3FBF2F3 udiv r3, r3, r2 + 670 .loc 1 487 13 view .LVU198 + 671 0058 0533 adds r3, r3, #5 + 672 .LVL51: + 673 .L37: + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Remove the floating point */ + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** tmp = tmp / 10U; + 674 .loc 1 491 7 is_stmt 1 view .LVU199 + 675 .loc 1 491 11 is_stmt 0 view .LVU200 + 676 005a 134A ldr r2, .L45+4 + 677 005c A2FB0323 umull r2, r3, r2, r3 + 678 .LVL52: + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Check the parity of the divider */ + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** i2sodd = (tmp & (uint16_t)0x0001U); + 679 .loc 1 494 7 is_stmt 1 view .LVU201 + 680 .loc 1 494 14 is_stmt 0 view .LVU202 + 681 0060 C3F3C002 ubfx r2, r3, #3, #1 + 682 .LVL53: + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Compute the i2sdiv prescaler */ + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** i2sdiv = ((tmp - i2sodd) / 2U); + 683 .loc 1 497 7 is_stmt 1 view .LVU203 + 684 .loc 1 497 22 is_stmt 0 view .LVU204 + 685 0064 C2EBD303 rsb r3, r2, r3, lsr #3 + 686 .LVL54: + 687 .loc 1 497 14 view .LVU205 + 688 0068 5B08 lsrs r3, r3, #1 + 689 .LVL55: + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** i2sodd = (i2sodd << 8U); + 690 .loc 1 500 7 is_stmt 1 view .LVU206 + 691 .loc 1 500 14 is_stmt 0 view .LVU207 + 692 006a 1202 lsls r2, r2, #8 + 693 .LVL56: + 694 .L34: + ARM GAS /tmp/cczBZbME.s page 84 + + + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Test if the divider is 1 or 0 or greater than 0xFF */ + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) + 695 .loc 1 504 5 is_stmt 1 view .LVU208 + 696 .loc 1 504 23 is_stmt 0 view .LVU209 + 697 006c 991E subs r1, r3, #2 + 698 .loc 1 504 8 view .LVU210 + 699 006e FD29 cmp r1, #253 + 700 0070 13D8 bhi .L42 + 701 0072 1646 mov r6, r2 + 702 .LVL57: + 703 .L38: + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Set the default values */ + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** i2sdiv = 2U; + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** i2sodd = 0U; + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Write to SPIx I2SPR register the computed value */ + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput); + 704 .loc 1 512 5 is_stmt 1 view .LVU211 + 705 0074 3343 orrs r3, r3, r6 + 706 .LVL58: + 707 .loc 1 512 5 is_stmt 0 view .LVU212 + 708 0076 EA68 ldr r2, [r5, #12] + 709 0078 1343 orrs r3, r3, r2 + 710 007a 2362 str r3, [r4, #32] + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** status = SUCCESS; + 711 .loc 1 514 5 is_stmt 1 view .LVU213 + 712 .LVL59: + 713 .loc 1 514 12 is_stmt 0 view .LVU214 + 714 007c 0020 movs r0, #0 + 715 .LVL60: + 716 .L33: + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** return status; + 717 .loc 1 516 3 is_stmt 1 view .LVU215 + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 718 .loc 1 517 1 is_stmt 0 view .LVU216 + 719 007e F8BD pop {r3, r4, r5, r6, r7, pc} + 720 .LVL61: + 721 .L41: + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 722 .loc 1 470 22 view .LVU217 + 723 0080 0227 movs r7, #2 + 724 0082 D8E7 b .L35 + 725 .LVL62: + 726 .L44: + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 727 .loc 1 482 9 is_stmt 1 view .LVU218 + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 728 .loc 1 482 32 is_stmt 0 view .LVU219 + 729 0084 000A lsrs r0, r0, #8 + 730 .LVL63: + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + ARM GAS /tmp/cczBZbME.s page 85 + + + 731 .loc 1 482 40 view .LVU220 + 732 0086 00EB8000 add r0, r0, r0, lsl #2 + 733 008a 4300 lsls r3, r0, #1 + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 734 .loc 1 482 63 view .LVU221 + 735 008c 2A69 ldr r2, [r5, #16] + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 736 .loc 1 482 47 view .LVU222 + 737 008e B3FBF2F3 udiv r3, r3, r2 + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 738 .loc 1 482 13 view .LVU223 + 739 0092 0533 adds r3, r3, #5 + 740 .LVL64: + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 741 .loc 1 482 13 view .LVU224 + 742 0094 E1E7 b .L37 + 743 .LVL65: + 744 .L40: + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** uint32_t packetlength = 1U; + 745 .loc 1 421 12 view .LVU225 + 746 0096 3246 mov r2, r6 + 747 0098 E8E7 b .L34 + 748 .LVL66: + 749 .L42: + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** i2sodd = 0U; + 750 .loc 1 507 14 view .LVU226 + 751 009a 0223 movs r3, #2 + 752 .LVL67: + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** i2sodd = 0U; + 753 .loc 1 507 14 view .LVU227 + 754 009c EAE7 b .L38 + 755 .LVL68: + 756 .L39: + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 757 .loc 1 425 15 view .LVU228 + 758 009e 0120 movs r0, #1 + 759 .LVL69: + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 760 .loc 1 425 15 view .LVU229 + 761 00a0 EDE7 b .L33 + 762 .L46: + 763 00a2 00BF .align 2 + 764 .L45: + 765 00a4 C0F4FFFF .word -2880 + 766 00a8 CDCCCCCC .word -858993459 + 767 .cfi_endproc + 768 .LFE455: + 770 .section .text.LL_I2S_StructInit,"ax",%progbits + 771 .align 1 + 772 .global LL_I2S_StructInit + 773 .syntax unified + 774 .thumb + 775 .thumb_func + 777 LL_I2S_StructInit: + 778 .LVL70: + 779 .LFB456: + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + ARM GAS /tmp/cczBZbME.s page 86 + + + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @brief Set each @ref LL_I2S_InitTypeDef field to default value. + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * whose fields will be set to default values. + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @retval None + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 780 .loc 1 526 1 is_stmt 1 view -0 + 781 .cfi_startproc + 782 @ args = 0, pretend = 0, frame = 0 + 783 @ frame_needed = 0, uses_anonymous_args = 0 + 784 @ link register save eliminated. + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /*--------------- Reset I2S init structure parameters values -----------------*/ + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX; + 785 .loc 1 528 3 view .LVU231 + 786 .loc 1 528 37 is_stmt 0 view .LVU232 + 787 0000 0023 movs r3, #0 + 788 0002 0360 str r3, [r0] + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS; + 789 .loc 1 529 3 is_stmt 1 view .LVU233 + 790 .loc 1 529 37 is_stmt 0 view .LVU234 + 791 0004 4360 str r3, [r0, #4] + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B; + 792 .loc 1 530 3 is_stmt 1 view .LVU235 + 793 .loc 1 530 37 is_stmt 0 view .LVU236 + 794 0006 8360 str r3, [r0, #8] + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE; + 795 .loc 1 531 3 is_stmt 1 view .LVU237 + 796 .loc 1 531 37 is_stmt 0 view .LVU238 + 797 0008 C360 str r3, [r0, #12] + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT; + 798 .loc 1 532 3 is_stmt 1 view .LVU239 + 799 .loc 1 532 37 is_stmt 0 view .LVU240 + 800 000a 0222 movs r2, #2 + 801 000c 0261 str r2, [r0, #16] + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW; + 802 .loc 1 533 3 is_stmt 1 view .LVU241 + 803 .loc 1 533 37 is_stmt 0 view .LVU242 + 804 000e 4361 str r3, [r0, #20] + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 805 .loc 1 534 1 view .LVU243 + 806 0010 7047 bx lr + 807 .cfi_endproc + 808 .LFE456: + 810 .section .text.LL_I2S_ConfigPrescaler,"ax",%progbits + 811 .align 1 + 812 .global LL_I2S_ConfigPrescaler + 813 .syntax unified + 814 .thumb + 815 .thumb_func + 817 LL_I2S_ConfigPrescaler: + 818 .LVL71: + 819 .LFB457: + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /** + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @brief Set linear and parity prescaler. + ARM GAS /tmp/cczBZbME.s page 87 + + + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @param SPIx SPI Instance + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF. + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @param PrescalerParity This parameter can be one of the following values: + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** * @retval None + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** */ + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity) + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** { + 820 .loc 1 548 1 is_stmt 1 view -0 + 821 .cfi_startproc + 822 @ args = 0, pretend = 0, frame = 0 + 823 @ frame_needed = 0, uses_anonymous_args = 0 + 824 @ link register save eliminated. + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Check the I2S parameters */ + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_I2S_ALL_INSTANCE(SPIx)); + 825 .loc 1 550 3 view .LVU245 + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear)); + 826 .loc 1 551 3 view .LVU246 + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity)); + 827 .loc 1 552 3 view .LVU247 + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** /* Write to SPIx I2SPR */ + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8 + 828 .loc 1 555 3 view .LVU248 + 829 0000 036A ldr r3, [r0, #32] + 830 0002 6FF30803 bfc r3, #0, #9 + 831 0006 41EA0221 orr r1, r1, r2, lsl #8 + 832 .LVL72: + 833 .loc 1 555 3 is_stmt 0 view .LVU249 + 834 000a 0B43 orrs r3, r3, r1 + 835 000c 0362 str r3, [r0, #32] + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c **** } + 836 .loc 1 556 1 view .LVU250 + 837 000e 7047 bx lr + 838 .cfi_endproc + 839 .LFE457: + 841 .text + 842 .Letext0: + 843 .file 4 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 844 .file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 845 .file 6 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + 846 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h" + ARM GAS /tmp/cczBZbME.s page 88 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_ll_spi.c + /tmp/cczBZbME.s:20 .text.LL_SPI_DeInit:00000000 $t + /tmp/cczBZbME.s:26 .text.LL_SPI_DeInit:00000000 LL_SPI_DeInit + /tmp/cczBZbME.s:292 .text.LL_SPI_DeInit:000000b8 $d + /tmp/cczBZbME.s:303 .text.LL_SPI_Init:00000000 $t + /tmp/cczBZbME.s:309 .text.LL_SPI_Init:00000000 LL_SPI_Init + /tmp/cczBZbME.s:470 .text.LL_SPI_Init:00000084 $d + /tmp/cczBZbME.s:476 .text.LL_SPI_StructInit:00000000 $t + /tmp/cczBZbME.s:482 .text.LL_SPI_StructInit:00000000 LL_SPI_StructInit + /tmp/cczBZbME.s:529 .text.LL_I2S_DeInit:00000000 $t + /tmp/cczBZbME.s:535 .text.LL_I2S_DeInit:00000000 LL_I2S_DeInit + /tmp/cczBZbME.s:558 .text.LL_I2S_Init:00000000 $t + /tmp/cczBZbME.s:564 .text.LL_I2S_Init:00000000 LL_I2S_Init + /tmp/cczBZbME.s:765 .text.LL_I2S_Init:000000a4 $d + /tmp/cczBZbME.s:771 .text.LL_I2S_StructInit:00000000 $t + /tmp/cczBZbME.s:777 .text.LL_I2S_StructInit:00000000 LL_I2S_StructInit + /tmp/cczBZbME.s:811 .text.LL_I2S_ConfigPrescaler:00000000 $t + /tmp/cczBZbME.s:817 .text.LL_I2S_ConfigPrescaler:00000000 LL_I2S_ConfigPrescaler + +UNDEFINED SYMBOLS +LL_RCC_GetI2SClockFreq diff --git a/build/stm32f7xx_ll_spi.o b/build/stm32f7xx_ll_spi.o new file mode 100644 index 0000000000000000000000000000000000000000..a2eb649a4004cfe90d626826d06c42878d2f56e8 GIT binary patch literal 15748 zcmbuG34B!5y~oeJckX1F?18WdI6#oitgKShBoh)MAR!4t@zrFKOqhXeOeQSWB_b}R zRI%WK8y0N^ORZb$(x+Il)=xiBp|#KDJzv$@;?hM0#a1it_dEB0Co|FK>*w>%hjYK@ zznuSB?z!jQ+__x7U~!FM7|KnCnxY0JrMAq~7JH_~6y;Z^E32mHyzNyvM-2a&=k2H( zd1N|{ML_wbEyZF z|5fNe*Lo#-Qu&WUzgfpo5{Fd&=b;Z*>G-)4A5{JW$9#)ct*JVp@>aF3S~EdY`5!%| zN{tFNS5>I_$TLx{M{c6dtgvd#aNheB*|U%4JYt5&F3hP&4=)Z+2pmGrh)f79M&5>e z2svZTgg{PUWXsC%u=C7{Yr_wIQt))eyBW$1tZLaBe&{3BWBq1Txa!0}!>X3_HISQA zj$m{V^rZFG;5R<;Eb6V@x@~k&`A-}(;`-j&3U%t#r|+LSr6yV}ftIBwUT@vpa(*ygE zBa!q#ejso{wH*vjkC@ZTkNhw^{b$DHr6-hPg!jS^f21xScjR*8flp7quihI_0W~f1 z@TVUhw`b&^x93x9;=$ujo6o%WTkFEqJagB$e@@MRxu9l7;N5V3U?OJulPAr|FCSCs z$u-|NR$lY=F>~U(7};NrsRK`+ICbjqp+kq9Fb$oUNB}@RW_(K$V#?$%5)}s%DP59xD4X>OCpj5W?%RBi%8TLe-Cu zQ%i9$RN7AaFJ{^y)JYFCDEn__?pD^BsC;7)%zodMJ-%Nsc#JHf9lFJedn|OXRbWg_c-hS(`|3Q?*saO?%FGS-(-JJxpKAd zApMmk?JdMfg=|bZDB8tZDO2`Mjw2QetbeB~`&Gsz zRP45_S8xt9Q;c@h_wF-pg*K}Qbye2CV;F|AVt{wQbvX=Xs;3U#*;A}pX-nXf^K~4o zIT_A!R5`OK&KJ>>^8}(;l_I9*TtaJ&h#5KeBa*d9#GKso8yl5XFXFJAjjX#|#F063 z(Yke^h+}eEDYl5{&$*JJLLwF_YauJIv3>-vw2{^gcG|OO+NXQB!xlH?dxN!Zab=J1 zJqEqgl~aA|DBt7C8NQDx-{;CXK0TfXU3r+wC}gugwJpv{N;3p*VtUW8l;Bz<|uTmp)SN0fZuq)qyb`kOj9cqtJ!BB5O@hbA@b_Tk~(6c`m;u@zuOpup>*`hLjILgRS)7MF`j7P7>nPVj!R>u?C1dV0 zvbmCZtGFI{%oVt7L6xNstoDeJat%f>b|)+^Li=l4#+`%1NeujSqu#0r6mkY`qxX)4 z8Aye~%SQebpMf356wbgjXwN_%2ZQ=JMTbc{ZhfSto-92H)o|kl#5T?}oRc~ZD$ai{ zJPU@SJ}hTa(DTm=%x_!)ALI4G>E8x<85?K#@p}4S*Ry{Il-yn?=s>Sm=s3$J>e+Zx zPsS^-9z`zvSSBNbL*{;Fe3-HW;l|q7u=CMuHnJLX2&Q^kd05Fpo{{oA{oaOU27Jnp z$NndTMJUv<(xg3*dQo6#WsEUW#y$m23v3tB`9TQlQQ+=`xiV5gY!DC9sJ8(Is-D)AxYVvRa-FDkA)9nHn3@m_C z@o1}P<)MRxz4j?L+9)m{u9ZSYqt)c0n{Gd}&q$MKWpF9cZX9WpRvz@F{fNDUZX9VH zTxzu&M@p;7!`1YE)Q-`OBMri(S-UaXR$6(uiG`=_+uUfI;IcuxF&eEV4|me-p#6*+ z?FP79ACI<&Rvx%Z7>De4+-UpYaxdK`Ga9WX50B981zY#)=P)0ji<+_!tJEByQear@ z;?(az2T^ZuYRYmG(%W7bIcbjZZSNcoRZTe;>%m-M!^qR<7+2U*^BHU;W;Tu74jf~) z?bMvM6*aAky`%L;Y;hS+<<$k%TwdC0$`2@cE!5_P;TXNv*JzxoZ$Mt_Jf{;g(T=st zgeR{w$8(o?w)T7$pUfw+aE+(s8$KUu+GqKw zPtR0Vsw39r&qbGgP%tv=jv_;v(h58-c#Ly=KG>Yr86#^7s*FMGY>ACtQJ*8BbSD`* zR~m~e@@6Isg9|jj*f=-CZGUn`UH<$GMjB@8felZ#=3-N-NWZyCyAsVfiHCno*hip1kPlGN#QKB0&)+ozwFdnP&vHD8i*Xn>V^z;0A{C^ z7yz7BN_8uY2#>+QrSZVn$K#2CXCs@cY&W?O*-$G608Tp9gOk6) zoqVbXBbUV^qXyC{uTcad^9t;n1~l5Han z!CF)g)~<&}C#UC1_Z;2{O}QS>qPP;-gYoCYm&2ewp);m#mMhm(>k8cvgW3dF*XYvO zkm`vk$nYelAt%l{NsBd59$p) z{+qPEqM|UtpE^#2M{eR-F##UmfA}mVN_%th1;kN)TP-LSz8d)ET_LVd?EtyeXGiT$* z=7p7un;mUQW3)|ur9)kJn=0w=i;T}9nJ-JzmTur*RrHlw(_xU3}7 z-PYOP9*TzwENQH3EU6BykF*WkY9_H=v7}W0TGqm=)Oszf7(S8^; z>ADS0rN`0|D?PtnS3;dxy3VnrI=4!l{YiCR98%|zq|P0d&b{ks zrE@p+CAYITsm?1>=f9Kc>={z$cE{?Mkbjg)ze%cezf;M~!2%vUH?I$#n|w*bJeED$ z`Zm0*VVpO6fgkf|SZ`i7pL0CU?=8j|OZDGvkAN}NZ>MaKTd#Z*(Y)5v%C9S$c2d9ho4R|G z^uj8!9gY{CJw$f(UrnRLG?LobVad9+)6vWq%zIq3p10x7>^YP7oL&}s@*4dsomF^n zz2RNywX(Onvy$SSVUI%KbU%jQ$Z51@`|aUgqZq|9*Ocb1wkN~O@3-d`+e_!$=lbnT zdKB6|s8hV>+F6=qb^(}0(?qSZ;UZ_q_EvlS-g9(^Ebjz;A_}Z!emf0kve@>c;uODq z?tHt1!P%dHAFuEKL!q2)-G8~?Z+era<~tY@R>zl5|Ilf6PLDBu$n@T=W8~)#_pWp& zw{l@s+2Z;I=QpV8z@k7+Eq)8Atgk9-Xl!awu$9xYcyV)Gd1G^3cO=%dsW(&|>Y%Ez zzOK2hZ$WpkwKLQnS0wmURpVEv`o)V;mw{Dpux)K9)*0$v9Sf_fV1Ii1LH8uv|FU?km*sy9^8E8PfzHm=8=I5_p)xlVBMWh|En!?c#^quWWw}WoaaE8Z40$^_Oz|lqvN3JQKv1~8Hz5Bbccdbt#@ikyN$7Ee_Kqq?T+42xm|7y z#Tqu&)YU8o^WOaPB zswCXg6)NcnwFgU<)YUhYGz8ltJ@w(9SWkDPt+}zkwJ#Ly2)2cqqrvuIw4^rF9f}5H zJ<;a+K-CauXqx+aI$|4w(U3E`_MU#M1~$!3exXb8v9*Pr8Q04T=e544bCZ&BYun%i z#_MqA0z8HF;b31#@!ZZR$H`4{;F8sILvz_|m@&`Y7)ZMca;mW$8!PLo>n>=}Gt$Jx z%XRK7`1mZ<2cwbLCN5sRqMSvS)KFCmnrLX99=lxQ?2cS)7!7BuHWcH<%SqSHjmrap z1^7K|Ne`Zm;J#7Lv@E`)VK+sC-F+RQXmunSYSSa<#i7rQyCFDdv!~OUY`N?Pw-o1G z=@S4OdxtAd7E5^LXelFD;)@R$6+Nzo@INxBu)mY)GMvMO||s$HM(xtzZZA9lh&k6}6Ymrr6mN zj1}Pt^K7j9b|`|;w(!|__FO+FRMa)Sqqn%d*I%?6|JrdabrhBRi;)aOiJ zALNeyZatN89bT*l0`vS+%4W^eor{J#%ZkdU4(%zQ2{VvSA>l3GC0QAnTBe?f&+21z z$vNyGA5&F&sk8kM0qn)mZX{Ksd=7Z#&BbVHPRS`x6@;c zamEDxWiTWqsyyn0Q;BAa59SHUlD~*tmBk0}goK|+lg7%wokqa^SlnmuZz-xQyy;1t z8@~CW|CYEv-;)d`OL>R*dk2juSt@0S9lvxXBuk|Yv8U=3zctKsRwT8<1I_>opJa_briW z%i{|El0Bp_rV8VaMT6U_yR~rV)LYu%P9+=Qps)MbLEkUij-^7vgNkT|-t+lKVY=UW z>zqCbzY;?>u_$?FO>fqceSunc(L$u z;dh0<6uu-pDNMnnGtLO%WZ@iPt#E~KwQz&*8sW{tdxeh*e<^%PcuaUwn1YGZ?F%Oh z=LlB~aceyiK@I_^9wX;qQcR z36BeNv1KuiUsxhMM|i%lUC3X>>Ayv|Q+SW?5#cX{$Ao_u=3~oa{W0V)v@0wU{e0m< zawOh_3zvyLEL=z8BJ3A#7X2>a4@hiB_X+PO5$`dvKP&R{!o#9}Mda6nZ;Jk}B7Z16 zDS8VR5aXr@Gf0eYq{w50MMC~iPXE~?{P=SpzwiMP?L8s(=S2RM@C6e7Z;Sl{61RnqgeGn|j5|s=iNxkPRaitK{v5Ga ziCiOGB>Jxl+eIH1t|Jj|z3^h;R7p+c&JH^ecoH3fGFgN4QD!mkBouzbp2egm;Pl`@(&~$Ho4n@Ry=LBs?N~ zUF>fO|0??9!jnQP-5GC+FpI=`7%QAEoF`l;TpSxUa!1wVt>VH)8vyGW&FOcIh};EL^wzIH6g#0qdh1L3-$dQ`aY322(J--Td42n z@Z+x)jH5sA1-~cqUg3V>!@@^}PYIt9z9oEH_&4Ek;Xj0*3$u9NMtga}QNpo8e&0v? zd||b4p>V0NQFx)SS=b?5BkU7y5b{$&#=lv(TX?tdKH>esp9mip{#^JA;UVD>A-_6g z{P%^Q2tN~Ae6E09KevF{BIgT73&#o15Ka?T2&;vQgiD31gck|7j_`fq3E^i#{0XG%@taB3A0ZqkoFL@4lC;ke@^eYbONA{${Tv8AzmTN;Vj;hN z9;pDP?C#5YV@&;OA@`xIfRaHdc{ zSE5`Ya;V!nfUXae+N^KM*+P){3Py4Q%GEIr6jJ?xg?(7D@fdzn7E#Bx;0VM%n<5$ zh>KgSj_((Jp-{(1J7-b`bvtNpCS_2!hj!;v1}jLkUoBinq92Qe`o4hn^nQcRZ0Gfa zxcd4+JbgVOPBwfPN3S2$=TOYCGJe=}{~+uBA&zbjvThIYn#6x4iMX92_mYUeP2}w) z+PPiiyGS-x+_$MK7HkD$QHNo-gm;lKRm?Yss<^eUPZd*9j28oZ+aT{2l63kvg(OYF z3x#65QHlTG@Jm8Mt&V803r>{{ONxWBSTxewA4AxG zHR1J$emBHxfoZ0L_z|}zoyOyc+ce&9IccaLZA_Dqv1I;FKdyP!No@B;$ZqmTp#n_w zONGGoi8Q*{y@3x)Vk|&$!98{S6AYOxqRc z+)M7sPO!a)a$>u4OYl`2{MatXxRtr_CJu?mo5@=2rEYTLojxSq#@Wt3&v<;3 z?8YmRc%>3xEgTLEiN~1phWJgJ=v;$RO^=a&wc_XMo8Y(C6+pJj6o6micppIjdZB0k z@aiGnzb5!$FQ7@M&k(QN6+pJhL?$c`Ra&Uj02I77{m5)L2bpamUOYW;hEjLMrNMZ7 S*PH0)pM&pe-Ns;Zi~j@bmgN}$ literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_ll_tim.d b/build/stm32f7xx_ll_tim.d new file mode 100644 index 0000000..1f86406 --- /dev/null +++ b/build/stm32f7xx_ll_tim.d @@ -0,0 +1,72 @@ +build/stm32f7xx_ll_tim.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h: diff --git a/build/stm32f7xx_ll_tim.lst b/build/stm32f7xx_ll_tim.lst new file mode 100644 index 0000000..909c510 --- /dev/null +++ b/build/stm32f7xx_ll_tim.lst @@ -0,0 +1,11811 @@ +ARM GAS /tmp/ccqfGNRw.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_ll_tim.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c" + 19 .section .text.OC1Config,"ax",%progbits + 20 .align 1 + 21 .syntax unified + 22 .thumb + 23 .thumb_func + 25 OC1Config: + 26 .LVL0: + 27 .LFB391: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @file stm32f7xx_ll_tim.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief TIM LL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * This software is licensed under terms that can be found in the LICENSE file + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * in the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(USE_FULL_LL_DRIVER) + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Includes ------------------------------------------------------------------*/ + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #include "stm32f7xx_ll_tim.h" + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #include "stm32f7xx_ll_bus.h" + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #ifdef USE_FULL_ASSERT + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #include "stm32_assert.h" + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #else + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define assert_param(expr) ((void)0U) + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* USE_FULL_ASSERT */ + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** @addtogroup STM32F7xx_LL_Driver + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @{ + ARM GAS /tmp/ccqfGNRw.s page 2 + + + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defi + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** @addtogroup TIM_LL + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @{ + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Private types -------------------------------------------------------------*/ + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Private variables ---------------------------------------------------------*/ + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Private constants ---------------------------------------------------------*/ + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Private macros ------------------------------------------------------------*/ + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** @addtogroup TIM_LL_Private_Macros + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @{ + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \ + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \ + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \ + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2)) + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \ + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) + ARM GAS /tmp/ccqfGNRw.s page 3 + + + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \ + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \ + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \ + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \ + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \ + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \ + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \ + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \ + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \ + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \ + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \ + ARM GAS /tmp/ccqfGNRw.s page 4 + + + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \ + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \ + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \ + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \ + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8)) + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \ + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \ + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \ + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENAB + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @} + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Private function prototypes -----------------------------------------------*/ + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** @defgroup TIM_LL_Private_Functions TIM Private Functions + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @{ + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @} + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Exported functions --------------------------------------------------------*/ + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** @addtogroup TIM_LL_Exported_Functions + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @{ + ARM GAS /tmp/ccqfGNRw.s page 5 + + + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** @addtogroup TIM_LL_EF_Init + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @{ + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Set TIMx registers to their reset values. + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIMx Timer instance + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - ERROR: invalid TIMx instance + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx) + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus result = SUCCESS; + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Check the parameters */ + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_TIM_INSTANCE(TIMx)); + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** if (TIMx == TIM1) + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1); + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1); + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** else if (TIMx == TIM2) + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM3) + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** else if (TIMx == TIM3) + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM3 */ + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM4) + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** else if (TIMx == TIM4) + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM4 */ + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM5) + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** else if (TIMx == TIM5) + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM5 */ + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM6) + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** else if (TIMx == TIM6) + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + ARM GAS /tmp/ccqfGNRw.s page 6 + + + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM6 */ + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined (TIM7) + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** else if (TIMx == TIM7) + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM7 */ + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM8) + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** else if (TIMx == TIM8) + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8); + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8); + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM8 */ + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM9) + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** else if (TIMx == TIM9) + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9); + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9); + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM9 */ + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM10) + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** else if (TIMx == TIM10) + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10); + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10); + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM10 */ + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM11) + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** else if (TIMx == TIM11) + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11); + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11); + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM11 */ + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM12) + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** else if (TIMx == TIM12) + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12); + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12); + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM12 */ + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM13) + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** else if (TIMx == TIM13) + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13); + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13); + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM13 */ + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #if defined(TIM14) + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** else if (TIMx == TIM14) + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14); + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14); + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** #endif /* TIM14 */ + ARM GAS /tmp/ccqfGNRw.s page 7 + + + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** else + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** result = ERROR; + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** return result; + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Set the fields of the time base unit configuration data structure + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * to their default values. + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configura + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval None + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the default configuration */ + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_InitStruct->Prescaler = (uint16_t)0x0000; + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_InitStruct->Autoreload = 0xFFFFFFFFU; + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_InitStruct->RepetitionCounter = 0x00000000U; + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Configure the TIMx time base unit. + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIMx Timer Instance + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * (TIMx time base unit configuration data structure) + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - ERROR: not applicable + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct) + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpcr1; + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Check the parameters */ + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_TIM_INSTANCE(TIMx)); + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Select the Counter Mode */ + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the clock division */ + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CR1 */ + ARM GAS /tmp/ccqfGNRw.s page 8 + + + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CR1, tmpcr1); + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Autoreload value */ + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Prescaler value */ + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Repetition Counter value */ + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter); + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Generate an update event to reload the Prescaler + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** and the repetition counter value (if applicable) immediately */ + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_GenerateEvent_UPDATE(TIMx); + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** return SUCCESS; + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Set the fields of the TIMx output channel configuration data + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * structure to their default values. + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * (the output channel configuration data structure) + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval None + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the default configuration */ + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->CompareValue = 0x00000000U; + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Configure the TIMx output channel. + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIMx Timer Instance + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param Channel This parameter can be one of the following values: + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @arg @ref LL_TIM_CHANNEL_CH1 + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @arg @ref LL_TIM_CHANNEL_CH2 + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @arg @ref LL_TIM_CHANNEL_CH3 + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @arg @ref LL_TIM_CHANNEL_CH4 + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @arg @ref LL_TIM_CHANNEL_CH5 + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @arg @ref LL_TIM_CHANNEL_CH6 + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channe + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * data structure) + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - SUCCESS: TIMx output channel is initialized + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - ERROR: TIMx output channel is not initialized + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + ARM GAS /tmp/ccqfGNRw.s page 9 + + + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus result = ERROR; + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** switch (Channel) + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** case LL_TIM_CHANNEL_CH1: + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** result = OC1Config(TIMx, TIM_OC_InitStruct); + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** case LL_TIM_CHANNEL_CH2: + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** result = OC2Config(TIMx, TIM_OC_InitStruct); + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** case LL_TIM_CHANNEL_CH3: + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** result = OC3Config(TIMx, TIM_OC_InitStruct); + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** case LL_TIM_CHANNEL_CH4: + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** result = OC4Config(TIMx, TIM_OC_InitStruct); + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** case LL_TIM_CHANNEL_CH5: + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** result = OC5Config(TIMx, TIM_OC_InitStruct); + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** case LL_TIM_CHANNEL_CH6: + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** result = OC6Config(TIMx, TIM_OC_InitStruct); + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** default: + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** return result; + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Set the fields of the TIMx input channel configuration data + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * structure to their default values. + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel c + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * data structure) + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval None + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the default configuration */ + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING; + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Configure the TIMx input channel. + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIMx Timer Instance + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param Channel This parameter can be one of the following values: + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @arg @ref LL_TIM_CHANNEL_CH1 + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @arg @ref LL_TIM_CHANNEL_CH2 + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @arg @ref LL_TIM_CHANNEL_CH3 + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @arg @ref LL_TIM_CHANNEL_CH4 + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * structure) + ARM GAS /tmp/ccqfGNRw.s page 10 + + + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - SUCCESS: TIMx output channel is initialized + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - ERROR: TIMx output channel is not initialized + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus result = ERROR; + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** switch (Channel) + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** case LL_TIM_CHANNEL_CH1: + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** result = IC1Config(TIMx, TIM_IC_InitStruct); + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** case LL_TIM_CHANNEL_CH2: + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** result = IC2Config(TIMx, TIM_IC_InitStruct); + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** case LL_TIM_CHANNEL_CH3: + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** result = IC3Config(TIMx, TIM_IC_InitStruct); + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** case LL_TIM_CHANNEL_CH4: + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** result = IC4Config(TIMx, TIM_IC_InitStruct); + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** default: + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** return result; + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Fills each TIM_EncoderInitStruct field with its default value + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder i + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * configuration data structure) + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval None + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the default configuration */ + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1; + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Configure the encoder interface of the timer instance. + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIMx Timer Instance + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx enco + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * configuration data structure) + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - ERROR: not applicable + ARM GAS /tmp/ccqfGNRw.s page 11 + + + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderIni + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccmr1; + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccer; + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Check the parameters */ + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CCMR1 register value */ + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CCER register value */ + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer = LL_TIM_ReadReg(TIMx, CCER); + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Configure TI1 */ + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Configure TI2 */ + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set encoder mode */ + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode); + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CCMR1 */ + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CCER */ + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCER, tmpccer); + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** return SUCCESS; + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + ARM GAS /tmp/ccqfGNRw.s page 12 + + + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Set the fields of the TIMx Hall sensor interface configuration data + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * structure to their default values. + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HAL + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * configuration data structure) + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval None + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the default configuration */ + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_HallSensorInitStruct->CommutationDelay = 0U; + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Configure the Hall sensor interface of the timer instance. + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * to the TI1 input channel + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @note TIMx slave mode controller is configured in reset mode. + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** Selected internal trigger is TI1F_ED. + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @note Channel 1 is configured as input, IC1 is mapped on TRC. + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * between 2 changes on the inputs. It gives information about motor speed. + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @note Channel 2 is configured in output PWM 2 mode. + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @note OC2REF is selected as trigger output on TRGO. + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * when TIMx operates in Hall sensor interface mode. + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIMx Timer Instance + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIM + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * interface configuration data structure) + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - ERROR: not applicable + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_Hall + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpcr2; + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccmr1; + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccer; + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpsmcr; + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Check the parameters */ + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx)); + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity)); + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler)); + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter)); + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CR2 register value */ + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CCMR1 register value */ + ARM GAS /tmp/ccqfGNRw.s page 13 + + + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CCER register value */ + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer = LL_TIM_ReadReg(TIMx, CCER); + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx SMCR register value */ + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR); + 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */ + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpcr2 |= TIM_CR2_TI1S; + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* OC2REF signal is used as trigger output (TRGO) */ + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpcr2 |= LL_TIM_TRGO_OC2REF; + 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Configure the slave mode controller */ + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS); + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpsmcr |= LL_TIM_TS_TI1F_ED; + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpsmcr |= LL_TIM_SLAVEMODE_RESET; + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Configure input channel 1 */ + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U); + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U); + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Configure input channel 2 */ + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE); + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U); + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CR2 */ + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx SMCR */ + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr); + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CCMR1 */ + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CCER */ + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCER, tmpccer); + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CCR2 */ + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay); + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** return SUCCESS; + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Set the fields of the Break and Dead Time configuration data structure + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * to their default values. + 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * data structure) + ARM GAS /tmp/ccqfGNRw.s page 14 + + + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval None + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the default configuration */ + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; + 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00; + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1; + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE; + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW; + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1; + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Configure the Break and Dead Time feature of the timer instance. + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * and DTG[7:0] can be write-locked depending on the LOCK configuration, it + 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * can be necessary to configure all of them during the first write access to + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * the TIMx_BDTR register. + 740:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + 741:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * a timer instance provides a break input. + 742:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + 743:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * a timer instance provides a second break input. + 744:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIMx Timer Instance + 745:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead + 746:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * data structure) + 747:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 748:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - SUCCESS: Break and Dead Time is initialized + 749:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - ERROR: not applicable + 750:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 751:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpbdtr = 0; + 754:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 755:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Check the parameters */ + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_TIM_BREAK_INSTANCE(TIMx)); + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState)); + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel)); + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); + 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + 764:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 765:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + 766:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** the OSSI State, the dead time value and the Automatic Output Enable Bit */ + 767:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 768:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the BDTR bits */ + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); + ARM GAS /tmp/ccqfGNRw.s page 15 + + + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); + 777:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** if (IS_TIM_BKIN2_INSTANCE(TIMx)) + 779:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State)); + 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity)); + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter)); + 783:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 784:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the BREAK2 input related BDTR bit-fields */ + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter)); + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State); + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity); + 788:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 789:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 790:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set TIMx_BDTR */ + 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); + 792:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** return SUCCESS; + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 795:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 796:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @} + 797:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 798:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 799:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 800:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @} + 801:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 802:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 803:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** @addtogroup TIM_LL_Private_Functions TIM Private Functions + 804:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Private functions + 805:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @{ + 806:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 807:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 808:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Configure the TIMx output channel 1. + 809:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIMx Timer Instance + 810:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure + 811:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 812:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized + 813:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - ERROR: not applicable + 814:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 815:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) + 816:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 28 .loc 1 816 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .loc 1 816 1 is_stmt 0 view .LVU1 + 34 0000 70B4 push {r4, r5, r6} + 35 .LCFI0: + 36 .cfi_def_cfa_offset 12 + 37 .cfi_offset 4, -12 + 38 .cfi_offset 5, -8 + 39 .cfi_offset 6, -4 + 817:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccmr1; + ARM GAS /tmp/ccqfGNRw.s page 16 + + + 40 .loc 1 817 3 is_stmt 1 view .LVU2 + 818:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccer; + 41 .loc 1 818 3 view .LVU3 + 819:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpcr2; + 42 .loc 1 819 3 view .LVU4 + 820:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 821:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Check the parameters */ + 822:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + 43 .loc 1 822 3 view .LVU5 + 823:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + 44 .loc 1 823 3 view .LVU6 + 824:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + 45 .loc 1 824 3 view .LVU7 + 825:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + 46 .loc 1 825 3 view .LVU8 + 826:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 827:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Disable the Channel 1: Reset the CC1E Bit */ + 828:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); + 47 .loc 1 828 3 view .LVU9 + 48 0002 036A ldr r3, [r0, #32] + 49 0004 23F00103 bic r3, r3, #1 + 50 0008 0362 str r3, [r0, #32] + 829:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 830:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CCER register value */ + 831:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer = LL_TIM_ReadReg(TIMx, CCER); + 51 .loc 1 831 3 view .LVU10 + 52 .loc 1 831 11 is_stmt 0 view .LVU11 + 53 000a 036A ldr r3, [r0, #32] + 54 .LVL1: + 832:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 833:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CR2 register value */ + 834:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + 55 .loc 1 834 3 is_stmt 1 view .LVU12 + 56 .loc 1 834 10 is_stmt 0 view .LVU13 + 57 000c 4268 ldr r2, [r0, #4] + 58 .LVL2: + 835:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 836:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CCMR1 register value */ + 837:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + 59 .loc 1 837 3 is_stmt 1 view .LVU14 + 60 .loc 1 837 12 is_stmt 0 view .LVU15 + 61 000e 8569 ldr r5, [r0, #24] + 62 .LVL3: + 838:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 839:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Reset Capture/Compare selection Bits */ + 840:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); + 63 .loc 1 840 3 is_stmt 1 view .LVU16 + 841:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 842:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Output Compare Mode */ + 843:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); + 64 .loc 1 843 3 view .LVU17 + 65 0010 164C ldr r4, .L4 + 66 0012 2C40 ands r4, r4, r5 + 67 0014 0D68 ldr r5, [r1] + 68 .LVL4: + 69 .loc 1 843 3 is_stmt 0 view .LVU18 + 70 0016 2C43 orrs r4, r4, r5 + ARM GAS /tmp/ccqfGNRw.s page 17 + + + 71 .LVL5: + 844:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 845:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Output Compare Polarity */ + 846:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); + 72 .loc 1 846 3 is_stmt 1 view .LVU19 + 73 0018 23F00203 bic r3, r3, #2 + 74 .LVL6: + 75 .loc 1 846 3 is_stmt 0 view .LVU20 + 76 001c 0D69 ldr r5, [r1, #16] + 77 001e 2B43 orrs r3, r3, r5 + 78 .LVL7: + 847:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 848:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Output State */ + 849:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); + 79 .loc 1 849 3 is_stmt 1 view .LVU21 + 80 0020 23F00103 bic r3, r3, #1 + 81 .LVL8: + 82 .loc 1 849 3 is_stmt 0 view .LVU22 + 83 0024 4D68 ldr r5, [r1, #4] + 84 0026 2B43 orrs r3, r3, r5 + 85 .LVL9: + 850:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 851:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** if (IS_TIM_BREAK_INSTANCE(TIMx)) + 86 .loc 1 851 3 is_stmt 1 view .LVU23 + 87 .loc 1 851 6 is_stmt 0 view .LVU24 + 88 0028 114E ldr r6, .L4+4 + 89 002a 124D ldr r5, .L4+8 + 90 002c A842 cmp r0, r5 + 91 002e 18BF it ne + 92 0030 B042 cmpne r0, r6 + 93 0032 12D1 bne .L2 + 852:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 853:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + 94 .loc 1 853 5 is_stmt 1 view .LVU25 + 854:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + 95 .loc 1 854 5 view .LVU26 + 855:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + 96 .loc 1 855 5 view .LVU27 + 856:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + 97 .loc 1 856 5 view .LVU28 + 857:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 858:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the complementary output Polarity */ + 859:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); + 98 .loc 1 859 5 view .LVU29 + 99 0034 23F00803 bic r3, r3, #8 + 100 .LVL10: + 101 .loc 1 859 5 is_stmt 0 view .LVU30 + 102 0038 4D69 ldr r5, [r1, #20] + 103 003a 43EA8503 orr r3, r3, r5, lsl #2 + 104 .LVL11: + 860:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 861:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the complementary output State */ + 862:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); + 105 .loc 1 862 5 is_stmt 1 view .LVU31 + 106 003e 23F00403 bic r3, r3, #4 + 107 .LVL12: + 108 .loc 1 862 5 is_stmt 0 view .LVU32 + ARM GAS /tmp/ccqfGNRw.s page 18 + + + 109 0042 8D68 ldr r5, [r1, #8] + 110 .loc 1 862 5 view .LVU33 + 111 0044 43EA8503 orr r3, r3, r5, lsl #2 + 112 .LVL13: + 863:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 864:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Output Idle state */ + 865:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); + 113 .loc 1 865 5 is_stmt 1 view .LVU34 + 114 0048 22F48072 bic r2, r2, #256 + 115 .LVL14: + 116 .loc 1 865 5 is_stmt 0 view .LVU35 + 117 004c 8D69 ldr r5, [r1, #24] + 118 004e 2A43 orrs r2, r2, r5 + 119 .LVL15: + 866:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 867:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the complementary output Idle state */ + 868:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); + 120 .loc 1 868 5 is_stmt 1 view .LVU36 + 121 0050 22F40072 bic r2, r2, #512 + 122 .LVL16: + 123 .loc 1 868 5 is_stmt 0 view .LVU37 + 124 0054 CD69 ldr r5, [r1, #28] + 125 0056 42EA4502 orr r2, r2, r5, lsl #1 + 126 .LVL17: + 127 .L2: + 869:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 870:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 871:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CR2 */ + 872:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + 128 .loc 1 872 3 is_stmt 1 view .LVU38 + 129 005a 4260 str r2, [r0, #4] + 873:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 874:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CCMR1 */ + 875:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + 130 .loc 1 875 3 view .LVU39 + 131 005c 8461 str r4, [r0, #24] + 876:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 877:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Capture Compare Register value */ + 878:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue); + 132 .loc 1 878 3 view .LVU40 + 133 .loc 1 878 49 is_stmt 0 view .LVU41 + 134 005e CA68 ldr r2, [r1, #12] + 135 .LVL18: + 136 .LBB82: + 137 .LBI82: + 138 .file 2 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @file stm32f7xx_ll_tim.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Header file of TIM LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * + ARM GAS /tmp/ccqfGNRw.s page 19 + + + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * This software is licensed under terms that can be found in the LICENSE file + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifndef __STM32F7xx_LL_TIM_H + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __STM32F7xx_LL_TIM_H + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #ifdef __cplusplus + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** extern "C" { + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Includes ------------------------------------------------------------------*/ + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #include "stm32f7xx.h" + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @addtogroup STM32F7xx_LL_Driver + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defi + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL TIM + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private types -------------------------------------------------------------*/ + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private variables ---------------------------------------------------------*/ + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Variables TIM Private Variables + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t OFFSET_TAB_CCMRx[] = + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 0: TIMx_CH1 */ + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 1: TIMx_CH1N */ + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 2: TIMx_CH2 */ + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x00U, /* 3: TIMx_CH2N */ + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 4: TIMx_CH3 */ + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 5: TIMx_CH3N */ + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x04U, /* 6: TIMx_CH4 */ + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x3CU, /* 7: TIMx_CH5 */ + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0x3CU /* 8: TIMx_CH6 */ + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OCxx[] = + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: OC1M, OC1FE, OC1PE */ + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 1: - NA */ + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 2: OC2M, OC2FE, OC2PE */ + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 3: - NA */ + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 4: OC3M, OC3FE, OC3PE */ + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 5: - NA */ + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 6: OC4M, OC4FE, OC4PE */ + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 7: OC5M, OC5FE, OC5PE */ + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U /* 8: OC6M, OC6FE, OC6PE */ + ARM GAS /tmp/ccqfGNRw.s page 20 + + + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_ICxx[] = + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: CC1S, IC1PSC, IC1F */ + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 1: - NA */ + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 2: CC2S, IC2PSC, IC2F */ + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 3: - NA */ + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 4: CC3S, IC3PSC, IC3F */ + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 5: - NA */ + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 6: CC4S, IC4PSC, IC4F */ + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 7: - NA */ + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U /* 8: - NA */ + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_CCxP[] = + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: CC1P */ + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2U, /* 1: CC1NP */ + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4U, /* 2: CC2P */ + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 6U, /* 3: CC2NP */ + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 4: CC3P */ + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 10U, /* 5: CC3NP */ + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 12U, /* 6: CC4P */ + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 16U, /* 7: CC5P */ + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 20U /* 8: CC6P */ + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** static const uint8_t SHIFT_TAB_OISx[] = + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U, /* 0: OIS1 */ + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 1U, /* 1: OIS1N */ + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 2U, /* 2: OIS2 */ + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 3U, /* 3: OIS2N */ + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 4U, /* 4: OIS3 */ + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 5U, /* 5: OIS3N */ + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 6U, /* 6: OIS4 */ + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 8U, /* 7: OIS5 */ + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 10U /* 8: OIS6 */ + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** }; + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private constants ---------------------------------------------------------*/ + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Constants TIM Private Constants + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(TIM_BREAK_INPUT_SUPPORT) + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Defines used for the bit position in the register and perform offsets */ + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Generic bit definitions for TIMx_AF1 register */ + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */ + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + ARM GAS /tmp/ccqfGNRw.s page 21 + + + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Remap mask definitions */ + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_SHIFT 16U + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIMx_OR_RMP_MASK 0x0000FFFFU + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT) + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM5_OR_RMP_MASK (TIM5_OR_TI4_RMP << TIMx_OR_RMP_SHIFT) + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM11_OR_RMP_MASK (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_1 ((uint8_t)0x7F) + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_2 ((uint8_t)0x3F) + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_3 ((uint8_t)0x1F) + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_DELAY_4 ((uint8_t)0x1F) + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_1 ((uint8_t)0x00) + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_2 ((uint8_t)0x80) + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_3 ((uint8_t)0xC0) + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define DT_RANGE_4 ((uint8_t)0xE0) + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Private macros ------------------------------------------------------------*/ + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Private_Macros TIM Private Macros + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief Convert channel id into channel index. + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CHANNEL__ This parameter can be one of the following values: + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval none + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @brief Calculate the deadtime sampling period(in ps). + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz). + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CKD__ This parameter can be one of the following values: + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + ARM GAS /tmp/ccqfGNRw.s page 22 + + + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval none + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported types ------------------------------------------------------------*/ + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Time Base configuration structure definition. + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data=0x0000 and Max_D + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetPrescaler().*/ + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CounterMode; /*!< Specifies the counter mode. + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetCounterMode().*/ + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Auto-Reload Register at the next update event. + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter must be a number between Min_Data=0x0000 and Max_ + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Some timer instances may support 32 bits counters. In that case + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** be a number between 0x0000 and 0xFFFFFFFF. + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetAutoReload().*/ + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ClockDivision; /*!< Specifies the clock division. + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetClockDivision().*/ + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downc + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** reaches zero, an update event is generated and counting restarts + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** from the RCR value (N). + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This means in PWM mode that (N+1) corresponds to: + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** - the number of PWM periods in edge-aligned mode + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** - the number of half PWM period in center-aligned mode + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** GP timers: this parameter must be a number between Min_Data = 0x + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Max_Data = 0xFF. + ARM GAS /tmp/ccqfGNRw.s page 23 + + + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Advanced timers: this parameter must be a number between Min_Dat + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Max_Data = 0xFFFF. + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetRepetitionCounter().*/ + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_InitTypeDef; + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Output Compare configuration structure definition. + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCMode; /*!< Specifies the output mode. + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCMODE. + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetMode().*/ + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCState; /*!< Specifies the TIM Output Compare state. + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functions + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functions + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Re + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data=0x0000 and Max_Data= + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** LL_TIM_OC_SetCompareCHx (x=1..6).*/ + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCPolarity; /*!< Specifies the output polarity. + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetPolarity().*/ + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetPolarity().*/ + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetIdleState().*/ + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + ARM GAS /tmp/ccqfGNRw.s page 24 + + + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetIdleState().*/ + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_OC_InitTypeDef; + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Input Capture configuration structure definition. + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICActiveInput; /*!< Specifies the input. + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ICFilter; /*!< Specifies the input capture filter. + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_IC_InitTypeDef; + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Encoder interface configuration structure definition. + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetEncoderMode().*/ + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + ARM GAS /tmp/ccqfGNRw.s page 25 + + + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetActiveInput().*/ + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC2Filter; /*!< Specifies the TI2 input filter. + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_ENCODER_InitTypeDef; + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief TIM Hall sensor interface configuration structure definition. + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPolarity().*/ + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** Prescaler must be set to get a maximum counter period longer th + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** time interval between 2 consecutive changes on the Hall inputs. + ARM GAS /tmp/ccqfGNRw.s page 26 + + + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_ICPSC. + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetPrescaler().*/ + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref TIM_LL_EC_IC_FILTER. + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_IC_SetFilter().*/ + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compa + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** A positive pulse (TRGO event) is generated with a programmable + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** a change occurs on the Hall inputs. + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data = 0x0000 and Ma + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary function + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetCompareCH2().*/ + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_HALLSENSOR_InitTypeDef; + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief BDTR (Break and Dead Time) structure definition + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** typedef struct + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OSSR + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetOffStates() + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field cannot be modified as long as LOCK level + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_OSSI + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_SetOffStates() + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field cannot be modified as long as LOCK level + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t LockLevel; /*!< Specifies the LOCK level parameters. + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note The LOCK bits can be written only once after the reset. + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** register has been written, their content is frozen until the + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** switching-on of the outputs. + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a number between Min_Data = 0x00 and Ma + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_OC_SetDeadTime() + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + ARM GAS /tmp/ccqfGNRw.s page 27 + + + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARIT + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK() + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK() + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARI + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK2() + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_ConfigBRK2() + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + ARM GAS /tmp/ccqfGNRw.s page 28 + + + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTP + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** This feature can be modified afterwards using unitary functio + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAut + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @note This bit-field can not be modified as long as LOCK leve + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** programmed. */ + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } LL_TIM_BDTR_InitTypeDef; + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported constants --------------------------------------------------------*/ + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Flags defines which can be used with LL_TIM_ReadReg function. + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrup + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrup + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrup + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrup + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrup + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrup + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt fla + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapt + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapt + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapt + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapt + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt fla + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + ARM GAS /tmp/ccqfGNRw.s page 29 + + + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by softw + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_IT IT Defines + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrup + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrup + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrup + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrup + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable * + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/unde + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounte + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and + 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and + ARM GAS /tmp/ccqfGNRw.s page 30 + + + 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and + 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division + 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ + 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ + 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction + 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ + 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down + 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bi + 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bi + 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request + 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when + 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when + 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level + 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write + 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ + 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ + 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ + 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_CHANNEL Channel + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 + ARM GAS /tmp/ccqfGNRw.s page 31 + + + 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output ch + 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 + 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output ch + 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 + 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output ch + 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 + 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ + 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ + 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(USE_FULL_LL_DRIVER) + 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State + 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ + 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on + 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* USE_FULL_LL_DRIVER */ + 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** Legacy definitions for compatibility purpose + 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @cond 0 + 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1 + 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2 + 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** @endcond + 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode + 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FROZEN 0x00000000U + 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 + 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 + 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) + 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 + 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) + 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) + 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1 + 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) + 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) + 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1 + 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1 + 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) + 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity + 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ + ARM GAS /tmp/ccqfGNRw.s page 32 + + + 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ + 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} + 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State + 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ + 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!__REG__, (__VAL +1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Read a value in TIM register. +1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __INSTANCE__ TIM Instance +1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __REG__ Register to be read +1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Register value +1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro retrieving the UIFCPY flag from the counter value. +1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); +1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied +1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * to TIMx_CNT register bit 31) +1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CNT__ Counter value +1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval UIF status bit +1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ +1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) +1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + ARM GAS /tmp/ccqfGNRw.s page 40 + + +1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested de +1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); +1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) +1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CKD__ This parameter can be one of the following values: +1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 +1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 +1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 +1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DT__ deadtime duration (in ns) +1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval DTG[0:7] +1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ +1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? +1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : +1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__C +1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMC +1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) +1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__C +1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC +1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) +1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__ +1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMC +1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) +1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** 0U) +1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the prescaler value to achieve the required counter clock freq +1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); +1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) +1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __CNTCLK__ counter clock frequency (in Hz) +1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) +1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ +1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U +1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal fr +1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); +1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) +1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler +1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __FREQ__ output signal frequency (in Hz) +1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) +1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ +1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) +1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the compare value required to achieve the required timer outpu +1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * active/inactive delay. +1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); +1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) +1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler +1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DELAY__ timer output compare active/inactive delay (in us) +1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Compare value (between Min_Data=0 and Max_Data=65535) +1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ +1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ +1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + ARM GAS /tmp/ccqfGNRw.s page 41 + + +1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration +1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (when the timer operates in one pulse mode). +1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); +1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __TIMCLK__ timer input clock frequency (in Hz) +1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PSC__ prescaler +1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __DELAY__ timer output compare active/inactive delay (in us) +1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __PULSE__ pulse duration (in us) +1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) +1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ +1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ +1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) +1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief HELPER macro retrieving the ratio of the input capture prescaler +1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); +1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param __ICPSC__ This parameter can be one of the following values: +1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 +1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 +1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 +1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 +1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Input capture prescaler ratio (1, 2, 4 or 8) +1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ +1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) +1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /* Exported functions --------------------------------------------------------*/ +1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions +1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Time_Base Time Base configuration +1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable timer counter. +1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_EnableCounter +1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) +1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_CEN); +1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable timer counter. +1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_DisableCounter +1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None + ARM GAS /tmp/ccqfGNRw.s page 42 + + +1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) +1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); +1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the timer counter is enabled. +1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter +1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) +1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); +1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable update event generation. +1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent +1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) +1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); +1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable update event generation. +1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent +1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) +1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_UDIS); +1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether update event generation is enabled. +1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent +1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Inverted state of bit (0 or 1). +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); +1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set update event source +1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * generate an update interrupt or DMA request if enabled: +1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Counter overflow/underflow +1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Setting the UG bit +1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * - Update generation through the slave mode controller + ARM GAS /tmp/ccqfGNRw.s page 43 + + +1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter +1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * overflow/underflow generates an update interrupt or DMA request if enabled. +1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 URS LL_TIM_SetUpdateSource +1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param UpdateSource This parameter can be one of the following values: +1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_REGULAR +1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_COUNTER +1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) +1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); +1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual event update source +1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 URS LL_TIM_GetUpdateSource +1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_REGULAR +1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_UPDATESOURCE_COUNTER +1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) +1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); +1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set one pulse mode (one shot v.s. repetitive). +1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode +1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OnePulseMode This parameter can be one of the following values: +1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE +1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE +1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) +1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); +1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual one pulse mode. +1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode +1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE +1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE +1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) +1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); +1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the timer counter counting mode. +1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + ARM GAS /tmp/ccqfGNRw.s page 44 + + +1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * check whether or not the counter mode selection feature is supported +1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * by a timer instance. +1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) +1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * requires a timer reset to avoid unexpected direction +1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * due to DIR bit readonly in center aligned mode. +1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n +1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR1 CMS LL_TIM_SetCounterMode +1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CounterMode This parameter can be one of the following values: +1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_UP +1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_DOWN +1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP +1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN +1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN +1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) +1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); +1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual counter mode. +1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to +1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * check whether or not the counter mode selection feature is supported +1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * by a timer instance. +1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n +1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR1 CMS LL_TIM_GetCounterMode +1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_UP +1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_DOWN +1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP +1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN +1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN +1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) +1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t counter_mode; +1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); +1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** if (counter_mode == 0U) +1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return counter_mode; +1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable auto-reload (ARR) preload. +1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload +1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) + ARM GAS /tmp/ccqfGNRw.s page 45 + + +1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_ARPE); +1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable auto-reload (ARR) preload. +1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload +1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) +1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); +1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether auto-reload (ARR) preload is enabled. +1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload +1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) +1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); +1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the division ratio between the timer clock and the sampling clock used by the dead +1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (when supported) and the digital filters. +1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check +1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not the clock division feature is supported by the timer +1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * instance. +1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CKD LL_TIM_SetClockDivision +1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ClockDivision This parameter can be one of the following values: +1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 +1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 +1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 +1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) +1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); +1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the actual division ratio between the timer clock and the sampling clock used by t +1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * generators (when supported) and the digital filters. +1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check +1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not the clock division feature is supported by the timer +1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * instance. +1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 CKD LL_TIM_GetClockDivision +1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 +1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 +1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + ARM GAS /tmp/ccqfGNRw.s page 46 + + +1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) +1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); +1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the counter value. +1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CNT CNT LL_TIM_SetCounter +1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) +1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CNT, Counter); +1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the counter value. +1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CNT CNT LL_TIM_GetCounter +1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) +1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) +1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CNT)); +1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current direction of the counter +1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 DIR LL_TIM_GetDirection +1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERDIRECTION_UP +1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN +1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) +1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the prescaler value. +1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). +1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The prescaler can be changed on the fly as this control register is buffered. The new +1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * prescaler ratio is taken into account at the next update event. +1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter +1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll PSC PSC LL_TIM_SetPrescaler +1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Prescaler between Min_Data=0 and Max_Data=65535 +1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + ARM GAS /tmp/ccqfGNRw.s page 47 + + +1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) +1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->PSC, Prescaler); +1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the prescaler value. +1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll PSC PSC LL_TIM_GetPrescaler +1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Prescaler value between Min_Data=0 and Max_Data=65535 +1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) +1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->PSC)); +1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the auto-reload value. +1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The counter is blocked while the auto-reload value is null. +1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter +1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll ARR ARR LL_TIM_SetAutoReload +1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param AutoReload between Min_Data=0 and Max_Data=65535 +1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) +1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->ARR, AutoReload); +1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the auto-reload value. +1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll ARR ARR LL_TIM_GetAutoReload +1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Auto-reload value +1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) +1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->ARR)); +1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the repetition counter value. +1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note For advanced timer instances RepetitionCounter can be up to 65535. +1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check +1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a repetition counter. +1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll RCR REP LL_TIM_SetRepetitionCounter +1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. +1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) +1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + ARM GAS /tmp/ccqfGNRw.s page 48 + + +1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->RCR, RepetitionCounter); +1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the repetition counter value. +1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check +1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a repetition counter. +1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll RCR REP LL_TIM_GetRepetitionCounter +1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Repetition counter value +1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) +1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->RCR)); +1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter regis +1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This allows both the counter value and a potential roll-over condition signalled by the U +1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in an atomic way. +1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap +1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) +1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable update interrupt flag (UIF) remapping. +1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap +1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) +1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether update interrupt flag (UIF) copy is set. +1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Counter Counter value +1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) +1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); +1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration +1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + ARM GAS /tmp/ccqfGNRw.s page 49 + + +1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. +1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, +1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * they are updated only when a commutation event (COM) occurs. +1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Only on channels that have a complementary output. +1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check +1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. +1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload +1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) +1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR2, TIM_CR2_CCPC); +1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. +1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check +1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. +1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload +1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) +1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); +1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is en +1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload +1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). +1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check +1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance is able to generate a commutation event. +1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate +1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CCUpdateSource This parameter can be one of the following values: +1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI +1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) +1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); +1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + ARM GAS /tmp/ccqfGNRw.s page 50 + + +1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger of the capture/compare DMA request. +1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger +1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMAReqTrigger This parameter can be one of the following values: +1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_CC +1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE +1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) +1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); +1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get actual trigger of the capture/compare DMA request. +1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger +1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_CC +1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE +1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) +1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); +1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the lock level to freeze the +1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * configuration of several capture/compare parameters. +1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the lock mechanism is supported by a timer instance. +1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel +1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param LockLevel This parameter can be one of the following values: +1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_OFF +1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_1 +1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_2 +1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_LOCKLEVEL_3 +1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) +1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); +1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable capture/compare channels. +1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_EnableChannel\n +1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_EnableChannel\n +1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_EnableChannel\n +1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_EnableChannel\n +1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_EnableChannel\n +1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_EnableChannel\n +1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_EnableChannel\n +1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_EnableChannel +1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance + ARM GAS /tmp/ccqfGNRw.s page 51 + + +1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: +1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CCER, Channels); +1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable capture/compare channels. +1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n +1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_DisableChannel\n +1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_DisableChannel\n +1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_DisableChannel\n +1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_DisableChannel\n +1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_DisableChannel\n +1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_DisableChannel\n +1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_DisableChannel\n +1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_DisableChannel +1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: +1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CCER, Channels); +1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether channel(s) is(are) enabled. +1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n +1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n +1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2E LL_TIM_CC_IsEnabledChannel\n +1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n +1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3E LL_TIM_CC_IsEnabledChannel\n +1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n +1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4E LL_TIM_CC_IsEnabledChannel\n +1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5E LL_TIM_CC_IsEnabledChannel\n +1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6E LL_TIM_CC_IsEnabledChannel + ARM GAS /tmp/ccqfGNRw.s page 52 + + +1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channels This parameter can be a combination of the following values: +1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) +1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); +1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration +1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure an output channel. +1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n +1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n +1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n +1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n +1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n +1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n +1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1P LL_TIM_OC_ConfigOutput\n +1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_ConfigOutput\n +1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_ConfigOutput\n +1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_ConfigOutput\n +1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_ConfigOutput\n +1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_ConfigOutput\n +1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS1 LL_TIM_OC_ConfigOutput\n +1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_ConfigOutput\n +1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_ConfigOutput\n +1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_ConfigOutput\n +1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_ConfigOutput\n +1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_ConfigOutput +1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Configuration This parameter must be a combination of all the following values: +1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW +1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH +1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None + ARM GAS /tmp/ccqfGNRw.s page 53 + + +1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configura +1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); +1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), +1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); +1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), +1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); +1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Define the behavior of the output reference signal OCxREF from which +1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * OCx and OCxN (when relevant) are derived. +1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n +1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2M LL_TIM_OC_SetMode\n +1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3M LL_TIM_OC_SetMode\n +1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4M LL_TIM_OC_SetMode\n +1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5M LL_TIM_OC_SetMode\n +1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6M LL_TIM_OC_SetMode +1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Mode This parameter can be one of the following values: +1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FROZEN +1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ACTIVE +1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_INACTIVE +1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_TOGGLE +1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE +1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE +1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM1 +1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM2 +1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 +1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 +1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 +1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 +1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 +1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 +1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) +1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT +2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the output compare mode of an output channel. +2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n +2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2M LL_TIM_OC_GetMode\n + ARM GAS /tmp/ccqfGNRw.s page 54 + + +2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3M LL_TIM_OC_GetMode\n +2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4M LL_TIM_OC_GetMode\n +2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5M LL_TIM_OC_GetMode\n +2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6M LL_TIM_OC_GetMode +2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FROZEN +2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ACTIVE +2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_INACTIVE +2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_TOGGLE +2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE +2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE +2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM1 +2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_PWM2 +2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 +2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 +2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 +2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 +2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) +2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT +2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the polarity of an output channel. +2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n +2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_OC_SetPolarity\n +2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_SetPolarity\n +2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_OC_SetPolarity\n +2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_SetPolarity\n +2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_OC_SetPolarity\n +2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_SetPolarity\n +2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_SetPolarity\n +2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_SetPolarity +2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 + ARM GAS /tmp/ccqfGNRw.s page 55 + + +2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Polarity This parameter can be one of the following values: +2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH +2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_LOW +2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) +2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[i +2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the polarity of an output channel. +2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n +2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_OC_GetPolarity\n +2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_OC_GetPolarity\n +2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_OC_GetPolarity\n +2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_OC_GetPolarity\n +2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_OC_GetPolarity\n +2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_OC_GetPolarity\n +2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC5P LL_TIM_OC_GetPolarity\n +2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC6P LL_TIM_OC_GetPolarity +2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_HIGH +2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCPOLARITY_LOW +2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChan +2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the IDLE state of an output channel +2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function is significant only for the timer instances +2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) +2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * can be used to check whether or not a timer instance provides +2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a break input. +2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n +2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_SetIdleState\n +2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_SetIdleState\n +2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_SetIdleState\n +2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_SetIdleState\n +2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3N LL_TIM_OC_SetIdleState\n +2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_SetIdleState\n +2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_SetIdleState\n + ARM GAS /tmp/ccqfGNRw.s page 56 + + +2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_SetIdleState +2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param IdleState This parameter can be one of the following values: +2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW +2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_HIGH +2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState +2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iC +2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the IDLE state of an output channel +2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n +2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_GetIdleState\n +2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2 LL_TIM_OC_GetIdleState\n +2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS2N LL_TIM_OC_GetIdleState\n +2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3 LL_TIM_OC_GetIdleState\n +2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS3N LL_TIM_OC_GetIdleState\n +2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS4 LL_TIM_OC_GetIdleState\n +2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS5 LL_TIM_OC_GetIdleState\n +2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CR2 OIS6 LL_TIM_OC_GetIdleState +2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1N +2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2N +2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3N +2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_LOW +2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OCIDLESTATE_HIGH +2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) +2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChanne +2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable fast mode for the output channel. + ARM GAS /tmp/ccqfGNRw.s page 57 + + +2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Acts only if the channel is configured in PWM1 or PWM2 mode. +2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n +2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_EnableFast\n +2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_EnableFast\n +2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_EnableFast\n +2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_EnableFast\n +2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_EnableFast +2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) +2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); +2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable fast mode for the output channel. +2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n +2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_DisableFast\n +2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_DisableFast\n +2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_DisableFast\n +2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_DisableFast\n +2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_DisableFast +2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) +2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); +2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether fast mode is enabled for the output channel. +2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n +2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n +2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n +2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n + ARM GAS /tmp/ccqfGNRw.s page 58 + + +2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n +2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast +2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) +2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; +2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable compare register (TIMx_CCRx) preload for the output channel. +2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n +2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n +2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n +2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n +2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n +2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_EnablePreload +2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable compare register (TIMx_CCRx) preload for the output channel. +2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n +2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n +2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n +2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n +2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n +2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_DisablePreload +2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 + ARM GAS /tmp/ccqfGNRw.s page 59 + + +2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channe +2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n +2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n +2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n +2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n +2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n +2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload +2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) +2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; +2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable clearing the output channel on an external event. +2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function can only be used in Output compare and PWM modes. It does not work in Force +2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether +2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. +2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n +2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_EnableClear\n +2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_EnableClear\n +2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_EnableClear\n +2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_EnableClear\n +2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_EnableClear +2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 + ARM GAS /tmp/ccqfGNRw.s page 60 + + +2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) +2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable clearing the output channel on an external event. +2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether +2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. +2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n +2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_DisableClear\n +2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_DisableClear\n +2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_DisableClear\n +2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_DisableClear\n +2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_DisableClear +2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 +2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) +2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates clearing the output channel on an external event is enabled for the output ch +2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function enables clearing the output channel on an external event. +2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note This function can only be used in Output compare and PWM modes. It does not work in Force +2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether +2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance can clear the OCxREF signal on an external event. +2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n +2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n +2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n +2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n +2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n +2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear +2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH5 +2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH6 + ARM GAS /tmp/ccqfGNRw.s page 61 + + +2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) +2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; +2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal an +2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the Ocx and OCxN signals). +2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * dead-time insertion feature is supported by a timer instance. +2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter +2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime +2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DeadTime between Min_Data=0 and Max_Data=255 +2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) +2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); +2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 1 (TIMx_CCR1). +2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. +2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not +2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 1 is supported by a timer instance. +2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 +2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) + 139 .loc 2 2444 22 is_stmt 1 view .LVU42 + 140 .LBB83: +2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR1, CompareValue); + 141 .loc 2 2446 3 view .LVU43 + 142 0060 4263 str r2, [r0, #52] + 143 .LVL19: + 144 .loc 2 2446 3 is_stmt 0 view .LVU44 + 145 .LBE83: + 146 .LBE82: + 879:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 880:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CCER */ + 881:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCER, tmpccer); + 147 .loc 1 881 3 is_stmt 1 view .LVU45 + 148 0062 0362 str r3, [r0, #32] + 882:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 883:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** return SUCCESS; + 149 .loc 1 883 3 view .LVU46 + ARM GAS /tmp/ccqfGNRw.s page 62 + + + 884:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 150 .loc 1 884 1 is_stmt 0 view .LVU47 + 151 0064 0020 movs r0, #0 + 152 .LVL20: + 153 .loc 1 884 1 view .LVU48 + 154 0066 70BC pop {r4, r5, r6} + 155 .LCFI1: + 156 .cfi_restore 6 + 157 .cfi_restore 5 + 158 .cfi_restore 4 + 159 .cfi_def_cfa_offset 0 + 160 .LVL21: + 161 .loc 1 884 1 view .LVU49 + 162 0068 7047 bx lr + 163 .L5: + 164 006a 00BF .align 2 + 165 .L4: + 166 006c 8CFFFEFF .word -65652 + 167 0070 00000140 .word 1073807360 + 168 0074 00040140 .word 1073808384 + 169 .cfi_endproc + 170 .LFE391: + 172 .section .text.OC2Config,"ax",%progbits + 173 .align 1 + 174 .syntax unified + 175 .thumb + 176 .thumb_func + 178 OC2Config: + 179 .LVL22: + 180 .LFB392: + 885:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 886:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 887:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Configure the TIMx output channel 2. + 888:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIMx Timer Instance + 889:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure + 890:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 891:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized + 892:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - ERROR: not applicable + 893:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 894:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) + 895:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 181 .loc 1 895 1 is_stmt 1 view -0 + 182 .cfi_startproc + 183 @ args = 0, pretend = 0, frame = 0 + 184 @ frame_needed = 0, uses_anonymous_args = 0 + 185 @ link register save eliminated. + 186 .loc 1 895 1 is_stmt 0 view .LVU51 + 187 0000 70B4 push {r4, r5, r6} + 188 .LCFI2: + 189 .cfi_def_cfa_offset 12 + 190 .cfi_offset 4, -12 + 191 .cfi_offset 5, -8 + 192 .cfi_offset 6, -4 + 896:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccmr1; + 193 .loc 1 896 3 is_stmt 1 view .LVU52 + 897:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccer; + 194 .loc 1 897 3 view .LVU53 + ARM GAS /tmp/ccqfGNRw.s page 63 + + + 898:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpcr2; + 195 .loc 1 898 3 view .LVU54 + 899:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 900:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Check the parameters */ + 901:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(TIMx)); + 196 .loc 1 901 3 view .LVU55 + 902:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + 197 .loc 1 902 3 view .LVU56 + 903:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + 198 .loc 1 903 3 view .LVU57 + 904:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + 199 .loc 1 904 3 view .LVU58 + 905:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 906:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Disable the Channel 2: Reset the CC2E Bit */ + 907:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); + 200 .loc 1 907 3 view .LVU59 + 201 0002 036A ldr r3, [r0, #32] + 202 0004 23F01003 bic r3, r3, #16 + 203 0008 0362 str r3, [r0, #32] + 908:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 909:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CCER register value */ + 910:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer = LL_TIM_ReadReg(TIMx, CCER); + 204 .loc 1 910 3 view .LVU60 + 205 .loc 1 910 11 is_stmt 0 view .LVU61 + 206 000a 036A ldr r3, [r0, #32] + 207 .LVL23: + 911:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 912:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CR2 register value */ + 913:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + 208 .loc 1 913 3 is_stmt 1 view .LVU62 + 209 .loc 1 913 10 is_stmt 0 view .LVU63 + 210 000c 4268 ldr r2, [r0, #4] + 211 .LVL24: + 914:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 915:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CCMR1 register value */ + 916:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + 212 .loc 1 916 3 is_stmt 1 view .LVU64 + 213 .loc 1 916 12 is_stmt 0 view .LVU65 + 214 000e 8569 ldr r5, [r0, #24] + 215 .LVL25: + 917:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 918:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Reset Capture/Compare selection Bits */ + 919:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); + 216 .loc 1 919 3 is_stmt 1 view .LVU66 + 920:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 921:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Select the Output Compare Mode */ + 922:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); + 217 .loc 1 922 3 view .LVU67 + 218 0010 184C ldr r4, .L9 + 219 0012 2C40 ands r4, r4, r5 + 220 0014 0D68 ldr r5, [r1] + 221 .LVL26: + 222 .loc 1 922 3 is_stmt 0 view .LVU68 + 223 0016 44EA0524 orr r4, r4, r5, lsl #8 + 224 .LVL27: + 923:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 924:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Output Compare Polarity */ + ARM GAS /tmp/ccqfGNRw.s page 64 + + + 925:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); + 225 .loc 1 925 3 is_stmt 1 view .LVU69 + 226 001a 23F02003 bic r3, r3, #32 + 227 .LVL28: + 228 .loc 1 925 3 is_stmt 0 view .LVU70 + 229 001e 0D69 ldr r5, [r1, #16] + 230 0020 43EA0513 orr r3, r3, r5, lsl #4 + 231 .LVL29: + 926:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 927:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Output State */ + 928:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); + 232 .loc 1 928 3 is_stmt 1 view .LVU71 + 233 0024 23F01003 bic r3, r3, #16 + 234 .LVL30: + 235 .loc 1 928 3 is_stmt 0 view .LVU72 + 236 0028 4D68 ldr r5, [r1, #4] + 237 .loc 1 928 3 view .LVU73 + 238 002a 43EA0513 orr r3, r3, r5, lsl #4 + 239 .LVL31: + 929:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 930:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** if (IS_TIM_BREAK_INSTANCE(TIMx)) + 240 .loc 1 930 3 is_stmt 1 view .LVU74 + 241 .loc 1 930 6 is_stmt 0 view .LVU75 + 242 002e 124E ldr r6, .L9+4 + 243 0030 124D ldr r5, .L9+8 + 244 0032 A842 cmp r0, r5 + 245 0034 18BF it ne + 246 0036 B042 cmpne r0, r6 + 247 0038 13D1 bne .L7 + 931:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 932:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + 248 .loc 1 932 5 is_stmt 1 view .LVU76 + 933:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + 249 .loc 1 933 5 view .LVU77 + 934:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + 250 .loc 1 934 5 view .LVU78 + 935:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + 251 .loc 1 935 5 view .LVU79 + 936:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 937:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the complementary output Polarity */ + 938:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); + 252 .loc 1 938 5 view .LVU80 + 253 003a 23F08003 bic r3, r3, #128 + 254 .LVL32: + 255 .loc 1 938 5 is_stmt 0 view .LVU81 + 256 003e 4D69 ldr r5, [r1, #20] + 257 0040 43EA8513 orr r3, r3, r5, lsl #6 + 258 .LVL33: + 939:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 940:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the complementary output State */ + 941:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); + 259 .loc 1 941 5 is_stmt 1 view .LVU82 + 260 0044 23F04003 bic r3, r3, #64 + 261 .LVL34: + 262 .loc 1 941 5 is_stmt 0 view .LVU83 + 263 0048 8D68 ldr r5, [r1, #8] + 264 .loc 1 941 5 view .LVU84 + ARM GAS /tmp/ccqfGNRw.s page 65 + + + 265 004a 43EA8513 orr r3, r3, r5, lsl #6 + 266 .LVL35: + 942:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 943:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Output Idle state */ + 944:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); + 267 .loc 1 944 5 is_stmt 1 view .LVU85 + 268 004e 22F48062 bic r2, r2, #1024 + 269 .LVL36: + 270 .loc 1 944 5 is_stmt 0 view .LVU86 + 271 0052 8D69 ldr r5, [r1, #24] + 272 0054 42EA8502 orr r2, r2, r5, lsl #2 + 273 .LVL37: + 945:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 946:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the complementary output Idle state */ + 947:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); + 274 .loc 1 947 5 is_stmt 1 view .LVU87 + 275 0058 22F40062 bic r2, r2, #2048 + 276 .LVL38: + 277 .loc 1 947 5 is_stmt 0 view .LVU88 + 278 005c CD69 ldr r5, [r1, #28] + 279 .loc 1 947 5 view .LVU89 + 280 005e 42EAC502 orr r2, r2, r5, lsl #3 + 281 .LVL39: + 282 .L7: + 948:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 949:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 950:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CR2 */ + 951:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + 283 .loc 1 951 3 is_stmt 1 view .LVU90 + 284 0062 4260 str r2, [r0, #4] + 952:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 953:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CCMR1 */ + 954:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + 285 .loc 1 954 3 view .LVU91 + 286 0064 8461 str r4, [r0, #24] + 955:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 956:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Capture Compare Register value */ + 957:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue); + 287 .loc 1 957 3 view .LVU92 + 288 .loc 1 957 49 is_stmt 0 view .LVU93 + 289 0066 CA68 ldr r2, [r1, #12] + 290 .LVL40: + 291 .LBB84: + 292 .LBI84: +2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 2 (TIMx_CCR2). +2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. +2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not +2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 2 is supported by a timer instance. +2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 +2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None + ARM GAS /tmp/ccqfGNRw.s page 66 + + +2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) + 293 .loc 2 2461 22 is_stmt 1 view .LVU94 + 294 .LBB85: +2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR2, CompareValue); + 295 .loc 2 2463 3 view .LVU95 + 296 0068 8263 str r2, [r0, #56] + 297 .LVL41: + 298 .loc 2 2463 3 is_stmt 0 view .LVU96 + 299 .LBE85: + 300 .LBE84: + 958:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 959:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CCER */ + 960:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCER, tmpccer); + 301 .loc 1 960 3 is_stmt 1 view .LVU97 + 302 006a 0362 str r3, [r0, #32] + 961:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 962:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** return SUCCESS; + 303 .loc 1 962 3 view .LVU98 + 963:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 304 .loc 1 963 1 is_stmt 0 view .LVU99 + 305 006c 0020 movs r0, #0 + 306 .LVL42: + 307 .loc 1 963 1 view .LVU100 + 308 006e 70BC pop {r4, r5, r6} + 309 .LCFI3: + 310 .cfi_restore 6 + 311 .cfi_restore 5 + 312 .cfi_restore 4 + 313 .cfi_def_cfa_offset 0 + 314 .LVL43: + 315 .loc 1 963 1 view .LVU101 + 316 0070 7047 bx lr + 317 .L10: + 318 0072 00BF .align 2 + 319 .L9: + 320 0074 FF8CFFFE .word -16806657 + 321 0078 00000140 .word 1073807360 + 322 007c 00040140 .word 1073808384 + 323 .cfi_endproc + 324 .LFE392: + 326 .section .text.OC3Config,"ax",%progbits + 327 .align 1 + 328 .syntax unified + 329 .thumb + 330 .thumb_func + 332 OC3Config: + 333 .LVL44: + 334 .LFB393: + 964:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 965:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 966:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Configure the TIMx output channel 3. + 967:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIMx Timer Instance + 968:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure + 969:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: + 970:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized + ARM GAS /tmp/ccqfGNRw.s page 67 + + + 971:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - ERROR: not applicable + 972:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + 973:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) + 974:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 335 .loc 1 974 1 is_stmt 1 view -0 + 336 .cfi_startproc + 337 @ args = 0, pretend = 0, frame = 0 + 338 @ frame_needed = 0, uses_anonymous_args = 0 + 339 @ link register save eliminated. + 340 .loc 1 974 1 is_stmt 0 view .LVU103 + 341 0000 70B4 push {r4, r5, r6} + 342 .LCFI4: + 343 .cfi_def_cfa_offset 12 + 344 .cfi_offset 4, -12 + 345 .cfi_offset 5, -8 + 346 .cfi_offset 6, -4 + 975:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccmr2; + 347 .loc 1 975 3 is_stmt 1 view .LVU104 + 976:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccer; + 348 .loc 1 976 3 view .LVU105 + 977:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpcr2; + 349 .loc 1 977 3 view .LVU106 + 978:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 979:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Check the parameters */ + 980:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_TIM_CC3_INSTANCE(TIMx)); + 350 .loc 1 980 3 view .LVU107 + 981:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + 351 .loc 1 981 3 view .LVU108 + 982:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + 352 .loc 1 982 3 view .LVU109 + 983:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + 353 .loc 1 983 3 view .LVU110 + 984:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 985:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Disable the Channel 3: Reset the CC3E Bit */ + 986:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); + 354 .loc 1 986 3 view .LVU111 + 355 0002 036A ldr r3, [r0, #32] + 356 0004 23F48073 bic r3, r3, #256 + 357 0008 0362 str r3, [r0, #32] + 987:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 988:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CCER register value */ + 989:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer = LL_TIM_ReadReg(TIMx, CCER); + 358 .loc 1 989 3 view .LVU112 + 359 .loc 1 989 11 is_stmt 0 view .LVU113 + 360 000a 036A ldr r3, [r0, #32] + 361 .LVL45: + 990:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 991:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CR2 register value */ + 992:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + 362 .loc 1 992 3 is_stmt 1 view .LVU114 + 363 .loc 1 992 10 is_stmt 0 view .LVU115 + 364 000c 4268 ldr r2, [r0, #4] + 365 .LVL46: + 993:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 994:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CCMR2 register value */ + 995:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); + 366 .loc 1 995 3 is_stmt 1 view .LVU116 + ARM GAS /tmp/ccqfGNRw.s page 68 + + + 367 .loc 1 995 12 is_stmt 0 view .LVU117 + 368 000e C569 ldr r5, [r0, #28] + 369 .LVL47: + 996:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 997:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Reset Capture/Compare selection Bits */ + 998:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); + 370 .loc 1 998 3 is_stmt 1 view .LVU118 + 999:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1000:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Select the Output Compare Mode */ +1001:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); + 371 .loc 1 1001 3 view .LVU119 + 372 0010 174C ldr r4, .L14 + 373 0012 2C40 ands r4, r4, r5 + 374 0014 0D68 ldr r5, [r1] + 375 .LVL48: + 376 .loc 1 1001 3 is_stmt 0 view .LVU120 + 377 0016 2C43 orrs r4, r4, r5 + 378 .LVL49: +1002:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1003:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Output Compare Polarity */ +1004:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); + 379 .loc 1 1004 3 is_stmt 1 view .LVU121 + 380 0018 23F40073 bic r3, r3, #512 + 381 .LVL50: + 382 .loc 1 1004 3 is_stmt 0 view .LVU122 + 383 001c 0D69 ldr r5, [r1, #16] + 384 001e 43EA0523 orr r3, r3, r5, lsl #8 + 385 .LVL51: +1005:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1006:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Output State */ +1007:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); + 386 .loc 1 1007 3 is_stmt 1 view .LVU123 + 387 0022 23F48073 bic r3, r3, #256 + 388 .LVL52: + 389 .loc 1 1007 3 is_stmt 0 view .LVU124 + 390 0026 4D68 ldr r5, [r1, #4] + 391 .loc 1 1007 3 view .LVU125 + 392 0028 43EA0523 orr r3, r3, r5, lsl #8 + 393 .LVL53: +1008:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1009:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** if (IS_TIM_BREAK_INSTANCE(TIMx)) + 394 .loc 1 1009 3 is_stmt 1 view .LVU126 + 395 .loc 1 1009 6 is_stmt 0 view .LVU127 + 396 002c 114E ldr r6, .L14+4 + 397 002e 124D ldr r5, .L14+8 + 398 0030 A842 cmp r0, r5 + 399 0032 18BF it ne + 400 0034 B042 cmpne r0, r6 + 401 0036 13D1 bne .L12 +1010:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { +1011:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + 402 .loc 1 1011 5 is_stmt 1 view .LVU128 +1012:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + 403 .loc 1 1012 5 view .LVU129 +1013:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + 404 .loc 1 1013 5 view .LVU130 +1014:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + ARM GAS /tmp/ccqfGNRw.s page 69 + + + 405 .loc 1 1014 5 view .LVU131 +1015:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1016:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the complementary output Polarity */ +1017:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); + 406 .loc 1 1017 5 view .LVU132 + 407 0038 23F40063 bic r3, r3, #2048 + 408 .LVL54: + 409 .loc 1 1017 5 is_stmt 0 view .LVU133 + 410 003c 4D69 ldr r5, [r1, #20] + 411 003e 43EA8523 orr r3, r3, r5, lsl #10 + 412 .LVL55: +1018:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1019:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the complementary output State */ +1020:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); + 413 .loc 1 1020 5 is_stmt 1 view .LVU134 + 414 0042 23F48063 bic r3, r3, #1024 + 415 .LVL56: + 416 .loc 1 1020 5 is_stmt 0 view .LVU135 + 417 0046 8D68 ldr r5, [r1, #8] + 418 .loc 1 1020 5 view .LVU136 + 419 0048 43EA8523 orr r3, r3, r5, lsl #10 + 420 .LVL57: +1021:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1022:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Output Idle state */ +1023:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); + 421 .loc 1 1023 5 is_stmt 1 view .LVU137 + 422 004c 22F48052 bic r2, r2, #4096 + 423 .LVL58: + 424 .loc 1 1023 5 is_stmt 0 view .LVU138 + 425 0050 8D69 ldr r5, [r1, #24] + 426 0052 42EA0512 orr r2, r2, r5, lsl #4 + 427 .LVL59: +1024:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1025:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the complementary output Idle state */ +1026:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); + 428 .loc 1 1026 5 is_stmt 1 view .LVU139 + 429 0056 22F40052 bic r2, r2, #8192 + 430 .LVL60: + 431 .loc 1 1026 5 is_stmt 0 view .LVU140 + 432 005a CD69 ldr r5, [r1, #28] + 433 .loc 1 1026 5 view .LVU141 + 434 005c 42EA4512 orr r2, r2, r5, lsl #5 + 435 .LVL61: + 436 .L12: +1027:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } +1028:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1029:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CR2 */ +1030:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + 437 .loc 1 1030 3 is_stmt 1 view .LVU142 + 438 0060 4260 str r2, [r0, #4] +1031:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1032:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CCMR2 */ +1033:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); + 439 .loc 1 1033 3 view .LVU143 + 440 0062 C461 str r4, [r0, #28] +1034:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1035:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Capture Compare Register value */ + ARM GAS /tmp/ccqfGNRw.s page 70 + + +1036:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue); + 441 .loc 1 1036 3 view .LVU144 + 442 .loc 1 1036 49 is_stmt 0 view .LVU145 + 443 0064 CA68 ldr r2, [r1, #12] + 444 .LVL62: + 445 .LBB86: + 446 .LBI86: +2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 3 (TIMx_CCR3). +2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. +2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not +2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel is supported by a timer instance. +2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 +2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) + 447 .loc 2 2478 22 is_stmt 1 view .LVU146 + 448 .LBB87: +2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR3, CompareValue); + 449 .loc 2 2480 3 view .LVU147 + 450 0066 C263 str r2, [r0, #60] + 451 .LVL63: + 452 .loc 2 2480 3 is_stmt 0 view .LVU148 + 453 .LBE87: + 454 .LBE86: +1037:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1038:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CCER */ +1039:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCER, tmpccer); + 455 .loc 1 1039 3 is_stmt 1 view .LVU149 + 456 0068 0362 str r3, [r0, #32] +1040:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1041:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** return SUCCESS; + 457 .loc 1 1041 3 view .LVU150 +1042:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 458 .loc 1 1042 1 is_stmt 0 view .LVU151 + 459 006a 0020 movs r0, #0 + 460 .LVL64: + 461 .loc 1 1042 1 view .LVU152 + 462 006c 70BC pop {r4, r5, r6} + 463 .LCFI5: + 464 .cfi_restore 6 + 465 .cfi_restore 5 + 466 .cfi_restore 4 + 467 .cfi_def_cfa_offset 0 + 468 .LVL65: + 469 .loc 1 1042 1 view .LVU153 + 470 006e 7047 bx lr + 471 .L15: + 472 .align 2 + 473 .L14: + ARM GAS /tmp/ccqfGNRw.s page 71 + + + 474 0070 8CFFFEFF .word -65652 + 475 0074 00000140 .word 1073807360 + 476 0078 00040140 .word 1073808384 + 477 .cfi_endproc + 478 .LFE393: + 480 .section .text.OC4Config,"ax",%progbits + 481 .align 1 + 482 .syntax unified + 483 .thumb + 484 .thumb_func + 486 OC4Config: + 487 .LVL66: + 488 .LFB394: +1043:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1044:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** +1045:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Configure the TIMx output channel 4. +1046:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIMx Timer Instance +1047:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure +1048:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: +1049:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized +1050:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - ERROR: not applicable +1051:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ +1052:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +1053:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 489 .loc 1 1053 1 is_stmt 1 view -0 + 490 .cfi_startproc + 491 @ args = 0, pretend = 0, frame = 0 + 492 @ frame_needed = 0, uses_anonymous_args = 0 + 493 @ link register save eliminated. + 494 .loc 1 1053 1 is_stmt 0 view .LVU155 + 495 0000 70B4 push {r4, r5, r6} + 496 .LCFI6: + 497 .cfi_def_cfa_offset 12 + 498 .cfi_offset 4, -12 + 499 .cfi_offset 5, -8 + 500 .cfi_offset 6, -4 +1054:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccmr2; + 501 .loc 1 1054 3 is_stmt 1 view .LVU156 +1055:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccer; + 502 .loc 1 1055 3 view .LVU157 +1056:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpcr2; + 503 .loc 1 1056 3 view .LVU158 +1057:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1058:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Check the parameters */ +1059:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_TIM_CC4_INSTANCE(TIMx)); + 504 .loc 1 1059 3 view .LVU159 +1060:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + 505 .loc 1 1060 3 view .LVU160 +1061:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + 506 .loc 1 1061 3 view .LVU161 +1062:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + 507 .loc 1 1062 3 view .LVU162 +1063:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1064:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Disable the Channel 4: Reset the CC4E Bit */ +1065:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); + 508 .loc 1 1065 3 view .LVU163 + 509 0002 036A ldr r3, [r0, #32] + ARM GAS /tmp/ccqfGNRw.s page 72 + + + 510 0004 23F48053 bic r3, r3, #4096 + 511 0008 0362 str r3, [r0, #32] +1066:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1067:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CCER register value */ +1068:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer = LL_TIM_ReadReg(TIMx, CCER); + 512 .loc 1 1068 3 view .LVU164 + 513 .loc 1 1068 11 is_stmt 0 view .LVU165 + 514 000a 036A ldr r3, [r0, #32] + 515 .LVL67: +1069:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1070:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CR2 register value */ +1071:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + 516 .loc 1 1071 3 is_stmt 1 view .LVU166 + 517 .loc 1 1071 10 is_stmt 0 view .LVU167 + 518 000c 4468 ldr r4, [r0, #4] + 519 .LVL68: +1072:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1073:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CCMR2 register value */ +1074:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); + 520 .loc 1 1074 3 is_stmt 1 view .LVU168 + 521 .loc 1 1074 12 is_stmt 0 view .LVU169 + 522 000e C569 ldr r5, [r0, #28] + 523 .LVL69: +1075:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1076:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Reset Capture/Compare selection Bits */ +1077:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); + 524 .loc 1 1077 3 is_stmt 1 view .LVU170 +1078:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1079:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Select the Output Compare Mode */ +1080:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); + 525 .loc 1 1080 3 view .LVU171 + 526 0010 104A ldr r2, .L19 + 527 0012 2A40 ands r2, r2, r5 + 528 0014 0D68 ldr r5, [r1] + 529 .LVL70: + 530 .loc 1 1080 3 is_stmt 0 view .LVU172 + 531 0016 42EA0522 orr r2, r2, r5, lsl #8 + 532 .LVL71: +1081:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1082:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Output Compare Polarity */ +1083:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); + 533 .loc 1 1083 3 is_stmt 1 view .LVU173 + 534 001a 23F40053 bic r3, r3, #8192 + 535 .LVL72: + 536 .loc 1 1083 3 is_stmt 0 view .LVU174 + 537 001e 0D69 ldr r5, [r1, #16] + 538 0020 43EA0533 orr r3, r3, r5, lsl #12 + 539 .LVL73: +1084:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1085:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Output State */ +1086:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); + 540 .loc 1 1086 3 is_stmt 1 view .LVU175 + 541 0024 23F48053 bic r3, r3, #4096 + 542 .LVL74: + 543 .loc 1 1086 3 is_stmt 0 view .LVU176 + 544 0028 4D68 ldr r5, [r1, #4] + 545 .loc 1 1086 3 view .LVU177 + ARM GAS /tmp/ccqfGNRw.s page 73 + + + 546 002a 43EA0533 orr r3, r3, r5, lsl #12 + 547 .LVL75: +1087:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1088:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** if (IS_TIM_BREAK_INSTANCE(TIMx)) + 548 .loc 1 1088 3 is_stmt 1 view .LVU178 + 549 .loc 1 1088 6 is_stmt 0 view .LVU179 + 550 002e 0A4E ldr r6, .L19+4 + 551 0030 0A4D ldr r5, .L19+8 + 552 0032 A842 cmp r0, r5 + 553 0034 18BF it ne + 554 0036 B042 cmpne r0, r6 + 555 0038 04D1 bne .L17 +1089:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { +1090:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + 556 .loc 1 1090 5 is_stmt 1 view .LVU180 +1091:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1092:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Output Idle state */ +1093:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); + 557 .loc 1 1093 5 view .LVU181 + 558 003a 24F48044 bic r4, r4, #16384 + 559 .LVL76: + 560 .loc 1 1093 5 is_stmt 0 view .LVU182 + 561 003e 8D69 ldr r5, [r1, #24] + 562 0040 44EA8514 orr r4, r4, r5, lsl #6 + 563 .LVL77: + 564 .L17: +1094:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } +1095:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1096:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CR2 */ +1097:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + 565 .loc 1 1097 3 is_stmt 1 view .LVU183 + 566 0044 4460 str r4, [r0, #4] +1098:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1099:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CCMR2 */ +1100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); + 567 .loc 1 1100 3 view .LVU184 + 568 0046 C261 str r2, [r0, #28] +1101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Capture Compare Register value */ +1103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue); + 569 .loc 1 1103 3 view .LVU185 + 570 .loc 1 1103 49 is_stmt 0 view .LVU186 + 571 0048 CA68 ldr r2, [r1, #12] + 572 .LVL78: + 573 .LBB88: + 574 .LBI88: +2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 4 (TIMx_CCR4). +2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. +2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not +2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 4 is supported by a timer instance. +2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 +2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance + ARM GAS /tmp/ccqfGNRw.s page 74 + + +2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) + 575 .loc 2 2495 22 is_stmt 1 view .LVU187 + 576 .LBB89: +2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR4, CompareValue); + 577 .loc 2 2497 3 view .LVU188 + 578 004a 0264 str r2, [r0, #64] + 579 .LVL79: + 580 .loc 2 2497 3 is_stmt 0 view .LVU189 + 581 .LBE89: + 582 .LBE88: +1104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CCER */ +1106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCER, tmpccer); + 583 .loc 1 1106 3 is_stmt 1 view .LVU190 + 584 004c 0362 str r3, [r0, #32] +1107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** return SUCCESS; + 585 .loc 1 1108 3 view .LVU191 +1109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 586 .loc 1 1109 1 is_stmt 0 view .LVU192 + 587 004e 0020 movs r0, #0 + 588 .LVL80: + 589 .loc 1 1109 1 view .LVU193 + 590 0050 70BC pop {r4, r5, r6} + 591 .LCFI7: + 592 .cfi_restore 6 + 593 .cfi_restore 5 + 594 .cfi_restore 4 + 595 .cfi_def_cfa_offset 0 + 596 .LVL81: + 597 .loc 1 1109 1 view .LVU194 + 598 0052 7047 bx lr + 599 .L20: + 600 .align 2 + 601 .L19: + 602 0054 FF8CFFFE .word -16806657 + 603 0058 00000140 .word 1073807360 + 604 005c 00040140 .word 1073808384 + 605 .cfi_endproc + 606 .LFE394: + 608 .section .text.OC5Config,"ax",%progbits + 609 .align 1 + 610 .syntax unified + 611 .thumb + 612 .thumb_func + 614 OC5Config: + 615 .LVL82: + 616 .LFB395: +1110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** +1112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Configure the TIMx output channel 5. +1113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIMx Timer Instance +1114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure + ARM GAS /tmp/ccqfGNRw.s page 75 + + +1115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: +1116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized +1117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - ERROR: not applicable +1118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ +1119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +1120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 617 .loc 1 1120 1 is_stmt 1 view -0 + 618 .cfi_startproc + 619 @ args = 0, pretend = 0, frame = 0 + 620 @ frame_needed = 0, uses_anonymous_args = 0 + 621 @ link register save eliminated. + 622 .loc 1 1120 1 is_stmt 0 view .LVU196 + 623 0000 30B4 push {r4, r5} + 624 .LCFI8: + 625 .cfi_def_cfa_offset 8 + 626 .cfi_offset 4, -8 + 627 .cfi_offset 5, -4 +1121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccmr3; + 628 .loc 1 1121 3 is_stmt 1 view .LVU197 +1122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccer; + 629 .loc 1 1122 3 view .LVU198 +1123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Check the parameters */ +1125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_TIM_CC5_INSTANCE(TIMx)); + 630 .loc 1 1125 3 view .LVU199 +1126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + 631 .loc 1 1126 3 view .LVU200 +1127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + 632 .loc 1 1127 3 view .LVU201 +1128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + 633 .loc 1 1128 3 view .LVU202 +1129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + 634 .loc 1 1129 3 view .LVU203 +1130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + 635 .loc 1 1130 3 view .LVU204 +1131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Disable the Channel 5: Reset the CC5E Bit */ +1133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E); + 636 .loc 1 1133 3 view .LVU205 + 637 0002 036A ldr r3, [r0, #32] + 638 0004 23F48033 bic r3, r3, #65536 + 639 0008 0362 str r3, [r0, #32] +1134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CCER register value */ +1136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer = LL_TIM_ReadReg(TIMx, CCER); + 640 .loc 1 1136 3 view .LVU206 + 641 .loc 1 1136 11 is_stmt 0 view .LVU207 + 642 000a 036A ldr r3, [r0, #32] + 643 .LVL83: +1137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CCMR3 register value */ +1139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); + 644 .loc 1 1139 3 is_stmt 1 view .LVU208 + 645 .loc 1 1139 12 is_stmt 0 view .LVU209 + 646 000c 446D ldr r4, [r0, #84] + 647 .LVL84: +1140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + ARM GAS /tmp/ccqfGNRw.s page 76 + + +1141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Select the Output Compare Mode */ +1142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode); + 648 .loc 1 1142 3 is_stmt 1 view .LVU210 + 649 000e 114A ldr r2, .L24 + 650 0010 2240 ands r2, r2, r4 + 651 0012 0C68 ldr r4, [r1] + 652 .LVL85: + 653 .loc 1 1142 3 is_stmt 0 view .LVU211 + 654 0014 2243 orrs r2, r2, r4 + 655 .LVL86: +1143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Output Compare Polarity */ +1145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U); + 656 .loc 1 1145 3 is_stmt 1 view .LVU212 + 657 0016 23F40033 bic r3, r3, #131072 + 658 .LVL87: + 659 .loc 1 1145 3 is_stmt 0 view .LVU213 + 660 001a 0C69 ldr r4, [r1, #16] + 661 001c 43EA0443 orr r3, r3, r4, lsl #16 + 662 .LVL88: +1146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Output State */ +1148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U); + 663 .loc 1 1148 3 is_stmt 1 view .LVU214 + 664 0020 23F48033 bic r3, r3, #65536 + 665 .LVL89: + 666 .loc 1 1148 3 is_stmt 0 view .LVU215 + 667 0024 4C68 ldr r4, [r1, #4] + 668 .loc 1 1148 3 view .LVU216 + 669 0026 43EA0443 orr r3, r3, r4, lsl #16 + 670 .LVL90: +1149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** if (IS_TIM_BREAK_INSTANCE(TIMx)) + 671 .loc 1 1150 3 is_stmt 1 view .LVU217 + 672 .loc 1 1150 6 is_stmt 0 view .LVU218 + 673 002a 0B4D ldr r5, .L24+4 + 674 002c 0B4C ldr r4, .L24+8 + 675 002e A042 cmp r0, r4 + 676 0030 18BF it ne + 677 0032 A842 cmpne r0, r5 + 678 0034 06D1 bne .L22 +1151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { +1152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + 679 .loc 1 1152 5 is_stmt 1 view .LVU219 +1153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + 680 .loc 1 1153 5 view .LVU220 +1154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Output Idle state */ +1156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U); + 681 .loc 1 1156 5 view .LVU221 + 682 0036 4468 ldr r4, [r0, #4] + 683 0038 24F48034 bic r4, r4, #65536 + 684 003c 8D69 ldr r5, [r1, #24] + 685 003e 44EA0524 orr r4, r4, r5, lsl #8 + 686 0042 4460 str r4, [r0, #4] + 687 .L22: +1157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + ARM GAS /tmp/ccqfGNRw.s page 77 + + +1158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } +1159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CCMR3 */ +1161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); + 688 .loc 1 1161 3 view .LVU222 + 689 0044 4265 str r2, [r0, #84] +1162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Capture Compare Register value */ +1164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue); + 690 .loc 1 1164 3 view .LVU223 + 691 .loc 1 1164 49 is_stmt 0 view .LVU224 + 692 0046 CA68 ldr r2, [r1, #12] + 693 .LVL91: + 694 .LBB90: + 695 .LBI90: +2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 5 (TIMx_CCR5). +2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not +2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 5 is supported by a timer instance. +2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 +2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) + 696 .loc 2 2509 22 is_stmt 1 view .LVU225 + 697 .LBB91: +2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); + 698 .loc 2 2511 3 view .LVU226 + 699 0048 816D ldr r1, [r0, #88] + 700 .LVL92: + 701 .loc 2 2511 3 is_stmt 0 view .LVU227 + 702 004a 8265 str r2, [r0, #88] + 703 .LVL93: + 704 .loc 2 2511 3 view .LVU228 + 705 .LBE91: + 706 .LBE90: +1165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CCER */ +1167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCER, tmpccer); + 707 .loc 1 1167 3 is_stmt 1 view .LVU229 + 708 004c 0362 str r3, [r0, #32] +1168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** return SUCCESS; + 709 .loc 1 1169 3 view .LVU230 +1170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 710 .loc 1 1170 1 is_stmt 0 view .LVU231 + 711 004e 0020 movs r0, #0 + 712 .LVL94: + 713 .loc 1 1170 1 view .LVU232 + 714 0050 30BC pop {r4, r5} + 715 .LCFI9: + 716 .cfi_restore 5 + 717 .cfi_restore 4 + ARM GAS /tmp/ccqfGNRw.s page 78 + + + 718 .cfi_def_cfa_offset 0 + 719 0052 7047 bx lr + 720 .L25: + 721 .align 2 + 722 .L24: + 723 0054 8FFFFEFF .word -65649 + 724 0058 00000140 .word 1073807360 + 725 005c 00040140 .word 1073808384 + 726 .cfi_endproc + 727 .LFE395: + 729 .section .text.OC6Config,"ax",%progbits + 730 .align 1 + 731 .syntax unified + 732 .thumb + 733 .thumb_func + 735 OC6Config: + 736 .LVL95: + 737 .LFB396: +1171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** +1173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Configure the TIMx output channel 6. +1174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIMx Timer Instance +1175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure +1176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: +1177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized +1178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - ERROR: not applicable +1179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ +1180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +1181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 738 .loc 1 1181 1 is_stmt 1 view -0 + 739 .cfi_startproc + 740 @ args = 0, pretend = 0, frame = 0 + 741 @ frame_needed = 0, uses_anonymous_args = 0 + 742 @ link register save eliminated. + 743 .loc 1 1181 1 is_stmt 0 view .LVU234 + 744 0000 30B4 push {r4, r5} + 745 .LCFI10: + 746 .cfi_def_cfa_offset 8 + 747 .cfi_offset 4, -8 + 748 .cfi_offset 5, -4 +1182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccmr3; + 749 .loc 1 1182 3 is_stmt 1 view .LVU235 +1183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccer; + 750 .loc 1 1183 3 view .LVU236 +1184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Check the parameters */ +1186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_TIM_CC6_INSTANCE(TIMx)); + 751 .loc 1 1186 3 view .LVU237 +1187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + 752 .loc 1 1187 3 view .LVU238 +1188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + 753 .loc 1 1188 3 view .LVU239 +1189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + 754 .loc 1 1189 3 view .LVU240 +1190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + 755 .loc 1 1190 3 view .LVU241 +1191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + ARM GAS /tmp/ccqfGNRw.s page 79 + + + 756 .loc 1 1191 3 view .LVU242 +1192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Disable the Channel 5: Reset the CC6E Bit */ +1194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E); + 757 .loc 1 1194 3 view .LVU243 + 758 0002 036A ldr r3, [r0, #32] + 759 0004 23F48013 bic r3, r3, #1048576 + 760 0008 0362 str r3, [r0, #32] +1195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CCER register value */ +1197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer = LL_TIM_ReadReg(TIMx, CCER); + 761 .loc 1 1197 3 view .LVU244 + 762 .loc 1 1197 11 is_stmt 0 view .LVU245 + 763 000a 036A ldr r3, [r0, #32] + 764 .LVL96: +1198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Get the TIMx CCMR3 register value */ +1200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); + 765 .loc 1 1200 3 is_stmt 1 view .LVU246 + 766 .loc 1 1200 12 is_stmt 0 view .LVU247 + 767 000c 446D ldr r4, [r0, #84] + 768 .LVL97: +1201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Select the Output Compare Mode */ +1203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U); + 769 .loc 1 1203 3 is_stmt 1 view .LVU248 + 770 000e 114A ldr r2, .L29 + 771 0010 2240 ands r2, r2, r4 + 772 0012 0C68 ldr r4, [r1] + 773 .LVL98: + 774 .loc 1 1203 3 is_stmt 0 view .LVU249 + 775 0014 42EA0422 orr r2, r2, r4, lsl #8 + 776 .LVL99: +1204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Output Compare Polarity */ +1206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U); + 777 .loc 1 1206 3 is_stmt 1 view .LVU250 + 778 0018 23F40013 bic r3, r3, #2097152 + 779 .LVL100: + 780 .loc 1 1206 3 is_stmt 0 view .LVU251 + 781 001c 0C69 ldr r4, [r1, #16] + 782 001e 43EA0453 orr r3, r3, r4, lsl #20 + 783 .LVL101: +1207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Output State */ +1209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U); + 784 .loc 1 1209 3 is_stmt 1 view .LVU252 + 785 0022 23F48013 bic r3, r3, #1048576 + 786 .LVL102: + 787 .loc 1 1209 3 is_stmt 0 view .LVU253 + 788 0026 4C68 ldr r4, [r1, #4] + 789 .loc 1 1209 3 view .LVU254 + 790 0028 43EA0453 orr r3, r3, r4, lsl #20 + 791 .LVL103: +1210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** if (IS_TIM_BREAK_INSTANCE(TIMx)) + 792 .loc 1 1211 3 is_stmt 1 view .LVU255 + ARM GAS /tmp/ccqfGNRw.s page 80 + + + 793 .loc 1 1211 6 is_stmt 0 view .LVU256 + 794 002c 0A4D ldr r5, .L29+4 + 795 002e 0B4C ldr r4, .L29+8 + 796 0030 A042 cmp r0, r4 + 797 0032 18BF it ne + 798 0034 A842 cmpne r0, r5 + 799 0036 06D1 bne .L27 +1212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { +1213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + 800 .loc 1 1213 5 is_stmt 1 view .LVU257 +1214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + 801 .loc 1 1214 5 view .LVU258 +1215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Output Idle state */ +1217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U); + 802 .loc 1 1217 5 view .LVU259 + 803 0038 4468 ldr r4, [r0, #4] + 804 003a 24F48024 bic r4, r4, #262144 + 805 003e 8D69 ldr r5, [r1, #24] + 806 0040 44EA8524 orr r4, r4, r5, lsl #10 + 807 0044 4460 str r4, [r0, #4] + 808 .L27: +1218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } +1219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CCMR3 */ +1221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); + 809 .loc 1 1221 3 view .LVU260 + 810 0046 4265 str r2, [r0, #84] +1222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the Capture Compare Register value */ +1224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue); + 811 .loc 1 1224 3 view .LVU261 + 812 .loc 1 1224 49 is_stmt 0 view .LVU262 + 813 0048 CA68 ldr r2, [r1, #12] + 814 .LVL104: + 815 .LBB92: + 816 .LBI92: +2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set compare value for output channel 6 (TIMx_CCR6). +2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not +2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 6 is supported by a timer instance. +2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 +2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param CompareValue between Min_Data=0 and Max_Data=65535 +2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) + 817 .loc 2 2523 22 is_stmt 1 view .LVU263 + 818 .LBB93: +2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->CCR6, CompareValue); + 819 .loc 2 2525 3 view .LVU264 + 820 004a C265 str r2, [r0, #92] + 821 .LVL105: + 822 .loc 2 2525 3 is_stmt 0 view .LVU265 + ARM GAS /tmp/ccqfGNRw.s page 81 + + + 823 .LBE93: + 824 .LBE92: +1225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Write to TIMx CCER */ +1227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_TIM_WriteReg(TIMx, CCER, tmpccer); + 825 .loc 1 1227 3 is_stmt 1 view .LVU266 + 826 004c 0362 str r3, [r0, #32] +1228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** return SUCCESS; + 827 .loc 1 1229 3 view .LVU267 +1230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 828 .loc 1 1230 1 is_stmt 0 view .LVU268 + 829 004e 0020 movs r0, #0 + 830 .LVL106: + 831 .loc 1 1230 1 view .LVU269 + 832 0050 30BC pop {r4, r5} + 833 .LCFI11: + 834 .cfi_restore 5 + 835 .cfi_restore 4 + 836 .cfi_def_cfa_offset 0 + 837 0052 7047 bx lr + 838 .L30: + 839 .align 2 + 840 .L29: + 841 0054 FF8FFFFE .word -16805889 + 842 0058 00000140 .word 1073807360 + 843 005c 00040140 .word 1073808384 + 844 .cfi_endproc + 845 .LFE396: + 847 .section .text.IC1Config,"ax",%progbits + 848 .align 1 + 849 .syntax unified + 850 .thumb + 851 .thumb_func + 853 IC1Config: + 854 .LVL107: + 855 .LFB397: +1231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** +1233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Configure the TIMx input channel 1. +1234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIMx Timer Instance +1235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure +1236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: +1237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized +1238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - ERROR: not applicable +1239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ +1240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +1241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 856 .loc 1 1241 1 is_stmt 1 view -0 + 857 .cfi_startproc + 858 @ args = 0, pretend = 0, frame = 0 + 859 @ frame_needed = 0, uses_anonymous_args = 0 + 860 @ link register save eliminated. + 861 .loc 1 1241 1 is_stmt 0 view .LVU271 + 862 0000 10B4 push {r4} + 863 .LCFI12: + 864 .cfi_def_cfa_offset 4 + ARM GAS /tmp/ccqfGNRw.s page 82 + + + 865 .cfi_offset 4, -4 +1242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Check the parameters */ +1243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + 866 .loc 1 1243 3 is_stmt 1 view .LVU272 +1244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + 867 .loc 1 1244 3 view .LVU273 +1245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + 868 .loc 1 1245 3 view .LVU274 +1246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + 869 .loc 1 1246 3 view .LVU275 +1247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + 870 .loc 1 1247 3 view .LVU276 +1248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Disable the Channel 1: Reset the CC1E Bit */ +1250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; + 871 .loc 1 1250 3 view .LVU277 + 872 .loc 1 1250 7 is_stmt 0 view .LVU278 + 873 0002 036A ldr r3, [r0, #32] + 874 .loc 1 1250 14 view .LVU279 + 875 0004 23F00103 bic r3, r3, #1 + 876 0008 0362 str r3, [r0, #32] +1251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Select the Input and set the filter and the prescaler value */ +1253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(TIMx->CCMR1, + 877 .loc 1 1253 3 is_stmt 1 view .LVU280 + 878 000a 8369 ldr r3, [r0, #24] + 879 000c 23F0FF03 bic r3, r3, #255 + 880 0010 4A68 ldr r2, [r1, #4] + 881 0012 CC68 ldr r4, [r1, #12] + 882 0014 2243 orrs r2, r2, r4 + 883 0016 8C68 ldr r4, [r1, #8] + 884 0018 2243 orrs r2, r2, r4 + 885 001a 43EA1243 orr r3, r3, r2, lsr #16 + 886 001e 8361 str r3, [r0, #24] +1254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), +1255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPr +1256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Select the Polarity and set the CC1E Bit */ +1258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(TIMx->CCER, + 887 .loc 1 1258 3 view .LVU281 + 888 0020 036A ldr r3, [r0, #32] + 889 0022 23F00A03 bic r3, r3, #10 + 890 0026 0A68 ldr r2, [r1] + 891 0028 1343 orrs r3, r3, r2 + 892 002a 43F00103 orr r3, r3, #1 + 893 002e 0362 str r3, [r0, #32] +1259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** (TIM_CCER_CC1P | TIM_CCER_CC1NP), +1260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E)); +1261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** return SUCCESS; + 894 .loc 1 1262 3 view .LVU282 +1263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 895 .loc 1 1263 1 is_stmt 0 view .LVU283 + 896 0030 0020 movs r0, #0 + 897 .LVL108: + 898 .loc 1 1263 1 view .LVU284 + 899 0032 5DF8044B ldr r4, [sp], #4 + ARM GAS /tmp/ccqfGNRw.s page 83 + + + 900 .LCFI13: + 901 .cfi_restore 4 + 902 .cfi_def_cfa_offset 0 + 903 0036 7047 bx lr + 904 .cfi_endproc + 905 .LFE397: + 907 .section .text.IC2Config,"ax",%progbits + 908 .align 1 + 909 .syntax unified + 910 .thumb + 911 .thumb_func + 913 IC2Config: + 914 .LVL109: + 915 .LFB398: +1264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** +1266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Configure the TIMx input channel 2. +1267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIMx Timer Instance +1268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure +1269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: +1270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized +1271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - ERROR: not applicable +1272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ +1273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +1274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 916 .loc 1 1274 1 is_stmt 1 view -0 + 917 .cfi_startproc + 918 @ args = 0, pretend = 0, frame = 0 + 919 @ frame_needed = 0, uses_anonymous_args = 0 + 920 @ link register save eliminated. + 921 .loc 1 1274 1 is_stmt 0 view .LVU286 + 922 0000 10B4 push {r4} + 923 .LCFI14: + 924 .cfi_def_cfa_offset 4 + 925 .cfi_offset 4, -4 +1275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Check the parameters */ +1276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(TIMx)); + 926 .loc 1 1276 3 is_stmt 1 view .LVU287 +1277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + 927 .loc 1 1277 3 view .LVU288 +1278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + 928 .loc 1 1278 3 view .LVU289 +1279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + 929 .loc 1 1279 3 view .LVU290 +1280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + 930 .loc 1 1280 3 view .LVU291 +1281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Disable the Channel 2: Reset the CC2E Bit */ +1283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; + 931 .loc 1 1283 3 view .LVU292 + 932 .loc 1 1283 7 is_stmt 0 view .LVU293 + 933 0002 036A ldr r3, [r0, #32] + 934 .loc 1 1283 14 view .LVU294 + 935 0004 23F01003 bic r3, r3, #16 + 936 0008 0362 str r3, [r0, #32] +1284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Select the Input and set the filter and the prescaler value */ + ARM GAS /tmp/ccqfGNRw.s page 84 + + +1286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(TIMx->CCMR1, + 937 .loc 1 1286 3 is_stmt 1 view .LVU295 + 938 000a 8369 ldr r3, [r0, #24] + 939 000c 23F47F43 bic r3, r3, #65280 + 940 0010 4A68 ldr r2, [r1, #4] + 941 0012 CC68 ldr r4, [r1, #12] + 942 0014 2243 orrs r2, r2, r4 + 943 0016 8C68 ldr r4, [r1, #8] + 944 0018 2243 orrs r2, r2, r4 + 945 001a 43EA1223 orr r3, r3, r2, lsr #8 + 946 001e 8361 str r3, [r0, #24] +1287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), +1288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPr +1289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Select the Polarity and set the CC2E Bit */ +1291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(TIMx->CCER, + 947 .loc 1 1291 3 view .LVU296 + 948 0020 036A ldr r3, [r0, #32] + 949 0022 23F0A003 bic r3, r3, #160 + 950 0026 0A68 ldr r2, [r1] + 951 0028 43EA0213 orr r3, r3, r2, lsl #4 + 952 002c 43F01003 orr r3, r3, #16 + 953 0030 0362 str r3, [r0, #32] +1292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** (TIM_CCER_CC2P | TIM_CCER_CC2NP), +1293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E)); +1294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** return SUCCESS; + 954 .loc 1 1295 3 view .LVU297 +1296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 955 .loc 1 1296 1 is_stmt 0 view .LVU298 + 956 0032 0020 movs r0, #0 + 957 .LVL110: + 958 .loc 1 1296 1 view .LVU299 + 959 0034 5DF8044B ldr r4, [sp], #4 + 960 .LCFI15: + 961 .cfi_restore 4 + 962 .cfi_def_cfa_offset 0 + 963 0038 7047 bx lr + 964 .cfi_endproc + 965 .LFE398: + 967 .section .text.IC3Config,"ax",%progbits + 968 .align 1 + 969 .syntax unified + 970 .thumb + 971 .thumb_func + 973 IC3Config: + 974 .LVL111: + 975 .LFB399: +1297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** +1299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Configure the TIMx input channel 3. +1300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIMx Timer Instance +1301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure +1302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: +1303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized +1304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - ERROR: not applicable +1305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ + ARM GAS /tmp/ccqfGNRw.s page 85 + + +1306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +1307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 976 .loc 1 1307 1 is_stmt 1 view -0 + 977 .cfi_startproc + 978 @ args = 0, pretend = 0, frame = 0 + 979 @ frame_needed = 0, uses_anonymous_args = 0 + 980 @ link register save eliminated. + 981 .loc 1 1307 1 is_stmt 0 view .LVU301 + 982 0000 10B4 push {r4} + 983 .LCFI16: + 984 .cfi_def_cfa_offset 4 + 985 .cfi_offset 4, -4 +1308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Check the parameters */ +1309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_TIM_CC3_INSTANCE(TIMx)); + 986 .loc 1 1309 3 is_stmt 1 view .LVU302 +1310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + 987 .loc 1 1310 3 view .LVU303 +1311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + 988 .loc 1 1311 3 view .LVU304 +1312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + 989 .loc 1 1312 3 view .LVU305 +1313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + 990 .loc 1 1313 3 view .LVU306 +1314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Disable the Channel 3: Reset the CC3E Bit */ +1316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; + 991 .loc 1 1316 3 view .LVU307 + 992 .loc 1 1316 7 is_stmt 0 view .LVU308 + 993 0002 036A ldr r3, [r0, #32] + 994 .loc 1 1316 14 view .LVU309 + 995 0004 23F48073 bic r3, r3, #256 + 996 0008 0362 str r3, [r0, #32] +1317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Select the Input and set the filter and the prescaler value */ +1319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(TIMx->CCMR2, + 997 .loc 1 1319 3 is_stmt 1 view .LVU310 + 998 000a C369 ldr r3, [r0, #28] + 999 000c 23F0FF03 bic r3, r3, #255 + 1000 0010 4A68 ldr r2, [r1, #4] + 1001 0012 CC68 ldr r4, [r1, #12] + 1002 0014 2243 orrs r2, r2, r4 + 1003 0016 8C68 ldr r4, [r1, #8] + 1004 0018 2243 orrs r2, r2, r4 + 1005 001a 43EA1243 orr r3, r3, r2, lsr #16 + 1006 001e C361 str r3, [r0, #28] +1320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), +1321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPr +1322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Select the Polarity and set the CC3E Bit */ +1324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(TIMx->CCER, + 1007 .loc 1 1324 3 view .LVU311 + 1008 0020 036A ldr r3, [r0, #32] + 1009 0022 23F42063 bic r3, r3, #2560 + 1010 0026 0A68 ldr r2, [r1] + 1011 0028 43EA0223 orr r3, r3, r2, lsl #8 + 1012 002c 43F48073 orr r3, r3, #256 + 1013 0030 0362 str r3, [r0, #32] + ARM GAS /tmp/ccqfGNRw.s page 86 + + +1325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** (TIM_CCER_CC3P | TIM_CCER_CC3NP), +1326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E)); +1327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** return SUCCESS; + 1014 .loc 1 1328 3 view .LVU312 +1329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1015 .loc 1 1329 1 is_stmt 0 view .LVU313 + 1016 0032 0020 movs r0, #0 + 1017 .LVL112: + 1018 .loc 1 1329 1 view .LVU314 + 1019 0034 5DF8044B ldr r4, [sp], #4 + 1020 .LCFI17: + 1021 .cfi_restore 4 + 1022 .cfi_def_cfa_offset 0 + 1023 0038 7047 bx lr + 1024 .cfi_endproc + 1025 .LFE399: + 1027 .section .text.IC4Config,"ax",%progbits + 1028 .align 1 + 1029 .syntax unified + 1030 .thumb + 1031 .thumb_func + 1033 IC4Config: + 1034 .LVL113: + 1035 .LFB400: +1330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** +1332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @brief Configure the TIMx input channel 4. +1333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIMx Timer Instance +1334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure +1335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * @retval An ErrorStatus enumeration value: +1336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - SUCCESS: TIMx registers are de-initialized +1337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** * - ERROR: not applicable +1338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** */ +1339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +1340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1036 .loc 1 1340 1 is_stmt 1 view -0 + 1037 .cfi_startproc + 1038 @ args = 0, pretend = 0, frame = 0 + 1039 @ frame_needed = 0, uses_anonymous_args = 0 + 1040 @ link register save eliminated. + 1041 .loc 1 1340 1 is_stmt 0 view .LVU316 + 1042 0000 10B4 push {r4} + 1043 .LCFI18: + 1044 .cfi_def_cfa_offset 4 + 1045 .cfi_offset 4, -4 +1341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Check the parameters */ +1342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_TIM_CC4_INSTANCE(TIMx)); + 1046 .loc 1 1342 3 is_stmt 1 view .LVU317 +1343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + 1047 .loc 1 1343 3 view .LVU318 +1344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + 1048 .loc 1 1344 3 view .LVU319 +1345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + 1049 .loc 1 1345 3 view .LVU320 +1346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + 1050 .loc 1 1346 3 view .LVU321 + ARM GAS /tmp/ccqfGNRw.s page 87 + + +1347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Disable the Channel 4: Reset the CC4E Bit */ +1349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; + 1051 .loc 1 1349 3 view .LVU322 + 1052 .loc 1 1349 7 is_stmt 0 view .LVU323 + 1053 0002 036A ldr r3, [r0, #32] + 1054 .loc 1 1349 14 view .LVU324 + 1055 0004 23F48053 bic r3, r3, #4096 + 1056 0008 0362 str r3, [r0, #32] +1350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Select the Input and set the filter and the prescaler value */ +1352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(TIMx->CCMR2, + 1057 .loc 1 1352 3 is_stmt 1 view .LVU325 + 1058 000a C369 ldr r3, [r0, #28] + 1059 000c 23F47F43 bic r3, r3, #65280 + 1060 0010 4A68 ldr r2, [r1, #4] + 1061 0012 CC68 ldr r4, [r1, #12] + 1062 0014 2243 orrs r2, r2, r4 + 1063 0016 8C68 ldr r4, [r1, #8] + 1064 0018 2243 orrs r2, r2, r4 + 1065 001a 43EA1223 orr r3, r3, r2, lsr #8 + 1066 001e C361 str r3, [r0, #28] +1353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), +1354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPr +1355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Select the Polarity and set the CC4E Bit */ +1357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(TIMx->CCER, + 1067 .loc 1 1357 3 view .LVU326 + 1068 0020 036A ldr r3, [r0, #32] + 1069 0022 23F42043 bic r3, r3, #40960 + 1070 0026 0A68 ldr r2, [r1] + 1071 0028 43EA0233 orr r3, r3, r2, lsl #12 + 1072 002c 43F48053 orr r3, r3, #4096 + 1073 0030 0362 str r3, [r0, #32] +1358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** (TIM_CCER_CC4P | TIM_CCER_CC4NP), +1359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); +1360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** +1361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** return SUCCESS; + 1074 .loc 1 1361 3 view .LVU327 +1362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1075 .loc 1 1362 1 is_stmt 0 view .LVU328 + 1076 0032 0020 movs r0, #0 + 1077 .LVL114: + 1078 .loc 1 1362 1 view .LVU329 + 1079 0034 5DF8044B ldr r4, [sp], #4 + 1080 .LCFI19: + 1081 .cfi_restore 4 + 1082 .cfi_def_cfa_offset 0 + 1083 0038 7047 bx lr + 1084 .cfi_endproc + 1085 .LFE400: + 1087 .section .text.LL_TIM_DeInit,"ax",%progbits + 1088 .align 1 + 1089 .global LL_TIM_DeInit + 1090 .syntax unified + 1091 .thumb + 1092 .thumb_func + ARM GAS /tmp/ccqfGNRw.s page 88 + + + 1094 LL_TIM_DeInit: + 1095 .LVL115: + 1096 .LFB378: + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus result = SUCCESS; + 1097 .loc 1 217 1 is_stmt 1 view -0 + 1098 .cfi_startproc + 1099 @ args = 0, pretend = 0, frame = 0 + 1100 @ frame_needed = 0, uses_anonymous_args = 0 + 1101 @ link register save eliminated. + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1102 .loc 1 218 3 view .LVU331 + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1103 .loc 1 221 3 view .LVU332 + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1104 .loc 1 223 3 view .LVU333 + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1105 .loc 1 223 6 is_stmt 0 view .LVU334 + 1106 0000 6B4B ldr r3, .L69 + 1107 0002 9842 cmp r0, r3 + 1108 0004 2CD0 beq .L55 + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1109 .loc 1 228 8 is_stmt 1 view .LVU335 + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1110 .loc 1 228 11 is_stmt 0 view .LVU336 + 1111 0006 B0F1804F cmp r0, #1073741824 + 1112 000a 35D0 beq .L56 + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1113 .loc 1 234 8 is_stmt 1 view .LVU337 + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1114 .loc 1 234 11 is_stmt 0 view .LVU338 + 1115 000c 694B ldr r3, .L69+4 + 1116 000e 9842 cmp r0, r3 + 1117 0010 3DD0 beq .L57 + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1118 .loc 1 241 8 is_stmt 1 view .LVU339 + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1119 .loc 1 241 11 is_stmt 0 view .LVU340 + 1120 0012 694B ldr r3, .L69+8 + 1121 0014 9842 cmp r0, r3 + 1122 0016 46D0 beq .L58 + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1123 .loc 1 248 8 is_stmt 1 view .LVU341 + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1124 .loc 1 248 11 is_stmt 0 view .LVU342 + 1125 0018 684B ldr r3, .L69+12 + 1126 001a 9842 cmp r0, r3 + 1127 001c 4FD0 beq .L59 + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1128 .loc 1 255 8 is_stmt 1 view .LVU343 + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1129 .loc 1 255 11 is_stmt 0 view .LVU344 + 1130 001e 684B ldr r3, .L69+16 + 1131 0020 9842 cmp r0, r3 + 1132 0022 58D0 beq .L60 + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1133 .loc 1 262 8 is_stmt 1 view .LVU345 + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + ARM GAS /tmp/ccqfGNRw.s page 89 + + + 1134 .loc 1 262 11 is_stmt 0 view .LVU346 + 1135 0024 674B ldr r3, .L69+20 + 1136 0026 9842 cmp r0, r3 + 1137 0028 61D0 beq .L61 + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1138 .loc 1 269 8 is_stmt 1 view .LVU347 + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1139 .loc 1 269 11 is_stmt 0 view .LVU348 + 1140 002a 674B ldr r3, .L69+24 + 1141 002c 9842 cmp r0, r3 + 1142 002e 6AD0 beq .L62 + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1143 .loc 1 276 8 is_stmt 1 view .LVU349 + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1144 .loc 1 276 11 is_stmt 0 view .LVU350 + 1145 0030 664B ldr r3, .L69+28 + 1146 0032 9842 cmp r0, r3 + 1147 0034 73D0 beq .L63 + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1148 .loc 1 283 8 is_stmt 1 view .LVU351 + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1149 .loc 1 283 11 is_stmt 0 view .LVU352 + 1150 0036 664B ldr r3, .L69+32 + 1151 0038 9842 cmp r0, r3 + 1152 003a 7CD0 beq .L64 + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1153 .loc 1 290 8 is_stmt 1 view .LVU353 + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1154 .loc 1 290 11 is_stmt 0 view .LVU354 + 1155 003c 654B ldr r3, .L69+36 + 1156 003e 9842 cmp r0, r3 + 1157 0040 00F08580 beq .L65 + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1158 .loc 1 297 8 is_stmt 1 view .LVU355 + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1159 .loc 1 297 11 is_stmt 0 view .LVU356 + 1160 0044 644B ldr r3, .L69+40 + 1161 0046 9842 cmp r0, r3 + 1162 0048 00F08D80 beq .L66 + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1163 .loc 1 304 8 is_stmt 1 view .LVU357 + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1164 .loc 1 304 11 is_stmt 0 view .LVU358 + 1165 004c 634B ldr r3, .L69+44 + 1166 004e 9842 cmp r0, r3 + 1167 0050 00F09580 beq .L67 + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1168 .loc 1 311 8 is_stmt 1 view .LVU359 + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1169 .loc 1 311 11 is_stmt 0 view .LVU360 + 1170 0054 624B ldr r3, .L69+48 + 1171 0056 9842 cmp r0, r3 + 1172 0058 00F09D80 beq .L68 + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1173 .loc 1 319 12 view .LVU361 + 1174 005c 0120 movs r0, #1 + 1175 .LVL116: + ARM GAS /tmp/ccqfGNRw.s page 90 + + + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1176 .loc 1 322 3 is_stmt 1 view .LVU362 + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1177 .loc 1 323 1 is_stmt 0 view .LVU363 + 1178 005e 7047 bx lr + 1179 .LVL117: + 1180 .L55: + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1); + 1181 .loc 1 225 5 is_stmt 1 view .LVU364 + 1182 .LBB94: + 1183 .LBI94: + 1184 .file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @file stm32f7xx_ll_bus.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @verbatim + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @attention + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * Copyright (c) 2017 STMicroelectronics. + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * All rights reserved. + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * This software is licensed under terms that can be found in the LICENSE file in + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * the root directory of this software component. + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifndef __STM32F7xx_LL_BUS_H + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define __STM32F7xx_LL_BUS_H + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifdef __cplusplus + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** extern "C" { + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #include "stm32f7xx.h" + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + ARM GAS /tmp/ccqfGNRw.s page 91 + + + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @addtogroup STM32F7xx_LL_Driver + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC) + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOJ) + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOJ */ + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOK) + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOK */ + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DTCMRAM RCC_AHB1ENR_DTCMRAMEN + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DMA2D) + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DMA2D */ + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(ETH) + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* ETH */ + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_AXI RCC_AHB1LPENR_AXILPEN + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN + ARM GAS /tmp/ccqfGNRw.s page 92 + + + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DCMI) + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DCMI */ + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(JPEG) + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_JPEG RCC_AHB2ENR_JPEGEN + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* JPEG */ + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CRYP) + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CRYP */ + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(AES) + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* AES */ + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(HASH) + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* HASH */ + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN + ARM GAS /tmp/ccqfGNRw.s page 93 + + + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPDIFRX) + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPDIFRX */ + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(I2C4) + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C4 RCC_APB1ENR_I2C4EN + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* I2C4 */ + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN2) + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN2 */ + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN3) + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN3 */ + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CEC) + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CEC */ + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC_APB1ENR_RTCEN) + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCEN + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* RCC_APB1ENR_RTCEN */ + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SDMMC2) + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC2 RCC_APB2ENR_SDMMC2EN + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SDMMC2 */ + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN + ARM GAS /tmp/ccqfGNRw.s page 94 + + + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPI6) + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPI6 */ + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(LTDC) + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* LTDC */ + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DSI) + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DSI */ + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DFSDM1_Channel0) + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DFSDM1_Channel0 */ + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(MDIOS) + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_MDIO RCC_APB2ENR_MDIOEN + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* MDIOS */ + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(USB_HS_PHYC) + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_OTGPHYC RCC_APB2ENR_OTGPHYCEN + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* USB_HS_PHYC */ + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_EnableClock\n + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n + ARM GAS /tmp/ccqfGNRw.s page 95 + + + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n + ARM GAS /tmp/ccqfGNRw.s page 96 + + + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_IsEnabledClock\n + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_IsEnabledClock + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n + ARM GAS /tmp/ccqfGNRw.s page 97 + + + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_DisableClock\n + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_DisableClock + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1ENR, Periphs); + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n + ARM GAS /tmp/ccqfGNRw.s page 98 + + + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1RSTR, Periphs); + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + ARM GAS /tmp/ccqfGNRw.s page 99 + + + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1RSTR, Periphs); + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB1 peripheral clocks in low-power mode + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR AXILPEN LL_AHB1_GRP1_EnableClockLowPower\n + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + ARM GAS /tmp/ccqfGNRw.s page 100 + + + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_AXI + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1LPENR, Periphs); + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB1 peripheral clocks in low-power mode + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR AXILPEN LL_AHB1_GRP1_DisableClockLowPower\n + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n + ARM GAS /tmp/ccqfGNRw.s page 101 + + + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_AXI + 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF + 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 + 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) + 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1LPENR, Periphs); + 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB2 AHB2 + 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + ARM GAS /tmp/ccqfGNRw.s page 102 + + + 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB2 peripherals clock. + 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n + 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_EnableClock\n + 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n + 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n + 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n + 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n + 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock + 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) + 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2ENR, Periphs); + 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB2 peripheral clock is enabled or not + 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n + 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_IsEnabledClock\n + 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n + 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n + 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n + 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n + 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock + 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) + 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); + 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB2 peripherals clock. + ARM GAS /tmp/ccqfGNRw.s page 103 + + + 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n + 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_DisableClock\n + 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n + 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n + 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n + 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n + 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock + 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) + 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2ENR, Periphs); + 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB2 peripherals reset. + 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n + 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR JPEGRST LL_AHB2_GRP1_ForceReset\n + 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n + 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n + 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n + 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n + 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset + 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) + 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2RSTR, Periphs); + 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB2 peripherals reset. + 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n + 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR JPEGRST LL_AHB2_GRP1_ReleaseReset\n + 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n + 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n + ARM GAS /tmp/ccqfGNRw.s page 104 + + + 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n + 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n + 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset + 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) + 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2RSTR, Periphs); + 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB2 peripheral clocks in low-power mode + 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n + 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower + 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) + 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2LPENR, Periphs); + 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); + 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB2 peripheral clocks in low-power mode + 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n + 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_DisableClockLowPower\n + 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n + 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n + ARM GAS /tmp/ccqfGNRw.s page 105 + + + 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n + 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n + 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower + 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) + 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2LPENR, Periphs); + 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB3 AHB3 + 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB3 peripherals clock. + 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n + 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) + 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3ENR, Periphs); + 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); + 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB3 peripheral clock is enabled or not + 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n + 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock + 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + ARM GAS /tmp/ccqfGNRw.s page 106 + + + 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) + 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); + 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB3 peripherals clock. + 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n + 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock + 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) + 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3ENR, Periphs); + 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB3 peripherals reset. + 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n + 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset + 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) + 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3RSTR, Periphs); + 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB3 peripherals reset. + 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n + 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset + 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) + 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3RSTR, Periphs); + 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + ARM GAS /tmp/ccqfGNRw.s page 107 + + + 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB3 peripheral clocks in low-power mode + 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n + 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower + 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) + 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3LPENR, Periphs); + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); + 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB3 peripheral clocks in low-power mode + 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n + 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower + 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) + 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3LPENR, Periphs); + 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1 + 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ +1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB1 peripherals clock. +1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n +1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n +1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n +1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n +1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n +1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n +1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n +1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n +1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n +1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n +1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + ARM GAS /tmp/ccqfGNRw.s page 108 + + +1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n +1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n +1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n +1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n +1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n +1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n +1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n +1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n +1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n +1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n +1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_EnableClock\n +1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n +1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n +1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n +1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n +1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n +1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n +1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n +1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_EnableClock +1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) + ARM GAS /tmp/ccqfGNRw.s page 109 + + +1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; +1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); +1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; +1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not +1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n +1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n +1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n +1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n +1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n +1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n +1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n +1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n +1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n +1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n +1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n +1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n +1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n +1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n +1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n +1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n +1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n +1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n +1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n +1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n +1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n +1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_IsEnabledClock\n +1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n +1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n +1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n +1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n +1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n +1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n +1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n +1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n +1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_IsEnabledClock +1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + ARM GAS /tmp/ccqfGNRw.s page 110 + + +1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). +1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); +1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable APB1 peripherals clock. +1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n +1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n +1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n +1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n +1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n +1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n +1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n +1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n +1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n +1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n +1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n +1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n +1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n +1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n +1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n +1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n +1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n +1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n +1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n +1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n +1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n +1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_DisableClock\n +1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n +1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n +1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n +1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n +1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n +1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n +1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n +1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n + ARM GAS /tmp/ccqfGNRw.s page 111 + + +1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_DisableClock +1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); +1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force APB1 peripherals reset. +1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n +1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n +1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n +1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n +1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n +1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n +1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n +1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n +1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n +1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n +1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n +1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n +1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n + ARM GAS /tmp/ccqfGNRw.s page 112 + + +1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n +1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n +1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n +1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n +1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n +1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n +1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n +1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n +1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C4RST LL_APB1_GRP1_ForceReset\n +1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n +1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n +1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n +1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n +1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n +1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n +1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n +1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset +1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); +1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + ARM GAS /tmp/ccqfGNRw.s page 113 + + +1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release APB1 peripherals reset. +1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n +1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n +1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n +1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n +1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n +1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n +1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n +1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n +1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n +1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n +1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n +1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n +1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n +1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n +1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n +1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n +1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n +1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n +1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n +1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n +1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C4RST LL_APB1_GRP1_ReleaseReset\n +1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n +1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n +1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n +1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n +1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n +1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n +1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n +1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset +1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + ARM GAS /tmp/ccqfGNRw.s page 114 + + +1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB1 peripheral clocks in low-power mode +1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n +1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n +1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n +1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n +1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n +1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n +1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n +1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n +1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n +1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n +1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n +1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n +1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n +1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C4LPEN LL_APB1_GRP1_EnableClockLowPower\n +1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n +1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n +1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n +1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n +1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n +1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n +1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR RTCLPEN LL_APB1_GRP1_EnableClockLowPower +1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + ARM GAS /tmp/ccqfGNRw.s page 115 + + +1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) +1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; +1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1LPENR, Periphs); +1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ +1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); +1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; +1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable APB1 peripheral clocks in low-power mode +1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n +1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n +1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n +1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n +1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n +1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n +1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n +1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n +1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n +1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n +1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n +1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n +1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n + ARM GAS /tmp/ccqfGNRw.s page 116 + + +1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C4LPEN LL_APB1_GRP1_DisableClockLowPower\n +1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n +1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n +1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n +1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n +1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n +1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n +1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR RTCLPEN LL_APB1_GRP1_DisableClockLowPower +1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) +1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1LPENR, Periphs); +1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} +1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + ARM GAS /tmp/ccqfGNRw.s page 117 + + +1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB2 APB2 +1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ +1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB2 peripherals clock. +1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n +1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n +1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n +1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n +1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n +1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n +1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n +1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n +1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC2EN LL_APB2_GRP1_EnableClock\n +1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n +1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n +1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n +1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n +1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n +1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n +1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n +1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n +1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n +1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n +1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n +1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n +1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n +1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR MDIOEN LL_APB2_GRP1_EnableClock\n +1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR OTGPHYCEN LL_APB2_GRP1_EnableClock +1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 +1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 +1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 +1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 +1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 +1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 +1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 +1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 +1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) +1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 +1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 +1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG +1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 +1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 +1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 +1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 +1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) +1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 +1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 +1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) +1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) +1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) +1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) +1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) +1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + ARM GAS /tmp/ccqfGNRw.s page 118 + + +1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; +1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); +1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB2ENR, Periphs); +1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; +1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if APB2 peripheral clock is enabled or not +1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n +1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n +1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n +1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n +1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n +1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n +1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n +1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n +1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC2EN LL_APB2_GRP1_IsEnabledClock\n +1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n +1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n +1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n +1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n +1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n +1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n +1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n +1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n +1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n +1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n +1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n +1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n +1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n +1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR MDIOEN LL_APB2_GRP1_IsEnabledClock\n +1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR OTGPHYCEN LL_APB2_GRP1_IsEnabledClock +1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 +1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 +1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 +1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 +1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 +1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 +1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 +1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 +1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) +1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 +1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 +1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG +1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 +1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 +1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 +1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 +1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) +1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 +1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + ARM GAS /tmp/ccqfGNRw.s page 119 + + +1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) +1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) +1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) +1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) +1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) +1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). +1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); +1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable APB2 peripherals clock. +1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n +1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n +1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n +1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n +1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n +1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n +1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n +1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n +1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC2EN LL_APB2_GRP1_DisableClock\n +1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n +1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n +1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n +1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n +1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n +1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n +1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n +1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n +1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n +1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n +1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n +1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n +1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n +1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR MDIOEN LL_APB2_GRP1_DisableClock\n +1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR OTGPHYCEN LL_APB2_GRP1_DisableClock +1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 +1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 +1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 +1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 +1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 +1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 +1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 +1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 +1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) +1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 +1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 +1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG +1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 +1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 +1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 +1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + ARM GAS /tmp/ccqfGNRw.s page 120 + + +1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) +1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 +1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 +1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) +1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) +1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) +1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) +1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) +1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB2ENR, Periphs); +1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force APB2 peripherals reset. +1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n +1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n +1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n +1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n +1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n +1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n +1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SDMMC2RST LL_APB2_GRP1_ForceReset\n +1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n +1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n +1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n +1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n +1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n +1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n +1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n +1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n +1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n +1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n +1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n +1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n +1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n +1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR MDIORST LL_APB2_GRP1_ForceReset\n +1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ForceReset +1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ALL +1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 +1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 +1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 +1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 +1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC +1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 +1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) +1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 +1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 +1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG +1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 +1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 +1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 +1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + ARM GAS /tmp/ccqfGNRw.s page 121 + + +1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) +1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 +1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 +1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) +1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) +1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) +1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) +1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) +1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) + 1185 .loc 3 1768 22 view .LVU365 + 1186 .LBB95: +1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2RSTR, Periphs); + 1187 .loc 3 1770 3 view .LVU366 + 1188 0060 03F59C33 add r3, r3, #79872 + 1189 0064 5A6A ldr r2, [r3, #36] + 1190 0066 42F00102 orr r2, r2, #1 + 1191 006a 5A62 str r2, [r3, #36] + 1192 .LVL118: + 1193 .loc 3 1770 3 is_stmt 0 view .LVU367 + 1194 .LBE95: + 1195 .LBE94: + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1196 .loc 1 226 5 is_stmt 1 view .LVU368 + 1197 .LBB96: + 1198 .LBI96: +1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release APB2 peripherals reset. +1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n +1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n +1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n +1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n +1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n +1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n +1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SDMMC2RST LL_APB2_GRP1_ReleaseReset\n +1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n +1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n +1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n +1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n +1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n +1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n +1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n +1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n +1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n +1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n +1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n +1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n +1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n +1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR MDIORST LL_APB2_GRP1_ReleaseReset\n +1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ReleaseReset +1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + ARM GAS /tmp/ccqfGNRw.s page 122 + + +1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ALL +1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 +1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 +1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 +1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 +1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC +1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 +1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) +1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 +1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 +1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG +1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 +1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 +1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 +1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 +1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) +1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 +1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 +1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) +1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) +1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) +1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) +1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) +1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) + 1199 .loc 3 1825 22 view .LVU369 + 1200 .LBB97: +1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB2RSTR, Periphs); + 1201 .loc 3 1827 3 view .LVU370 + 1202 006c 5A6A ldr r2, [r3, #36] + 1203 006e 22F00102 bic r2, r2, #1 + 1204 0072 5A62 str r2, [r3, #36] + 1205 .LVL119: + 1206 .loc 3 1827 3 is_stmt 0 view .LVU371 + 1207 .LBE97: + 1208 .LBE96: + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1209 .loc 1 218 15 view .LVU372 + 1210 0074 0020 movs r0, #0 + 1211 .LVL120: + 1212 .LBB99: + 1213 .LBB98: +1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1214 .loc 3 1828 1 view .LVU373 + 1215 0076 7047 bx lr + 1216 .LVL121: + 1217 .L56: + 1218 .loc 3 1828 1 view .LVU374 + 1219 .LBE98: + 1220 .LBE99: + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); + 1221 .loc 1 230 5 is_stmt 1 view .LVU375 + 1222 .LBB100: + ARM GAS /tmp/ccqfGNRw.s page 123 + + + 1223 .LBI100: +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1224 .loc 3 1295 22 view .LVU376 + 1225 .LBB101: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1226 .loc 3 1297 3 view .LVU377 + 1227 0078 5A4B ldr r3, .L69+52 + 1228 007a 1A6A ldr r2, [r3, #32] + 1229 007c 42F00102 orr r2, r2, #1 + 1230 0080 1A62 str r2, [r3, #32] + 1231 .LVL122: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1232 .loc 3 1297 3 is_stmt 0 view .LVU378 + 1233 .LBE101: + 1234 .LBE100: + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1235 .loc 1 231 5 is_stmt 1 view .LVU379 + 1236 .LBB102: + 1237 .LBI102: +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1238 .loc 3 1367 22 view .LVU380 + 1239 .LBB103: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1240 .loc 3 1369 3 view .LVU381 + 1241 0082 1A6A ldr r2, [r3, #32] + 1242 0084 22F00102 bic r2, r2, #1 + 1243 0088 1A62 str r2, [r3, #32] + 1244 .LVL123: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1245 .loc 3 1369 3 is_stmt 0 view .LVU382 + 1246 .LBE103: + 1247 .LBE102: + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1248 .loc 1 218 15 view .LVU383 + 1249 008a 0020 movs r0, #0 + 1250 .LVL124: + 1251 .LBB105: + 1252 .LBB104: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 1253 .loc 3 1370 1 view .LVU384 + 1254 008c 7047 bx lr + 1255 .LVL125: + 1256 .L57: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 1257 .loc 3 1370 1 view .LVU385 + 1258 .LBE104: + 1259 .LBE105: + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); + 1260 .loc 1 236 5 is_stmt 1 view .LVU386 + 1261 .LBB106: + 1262 .LBI106: +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1263 .loc 3 1295 22 view .LVU387 + 1264 .LBB107: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1265 .loc 3 1297 3 view .LVU388 + 1266 008e 03F50D33 add r3, r3, #144384 + ARM GAS /tmp/ccqfGNRw.s page 124 + + + 1267 0092 1A6A ldr r2, [r3, #32] + 1268 0094 42F00202 orr r2, r2, #2 + 1269 0098 1A62 str r2, [r3, #32] + 1270 .LVL126: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1271 .loc 3 1297 3 is_stmt 0 view .LVU389 + 1272 .LBE107: + 1273 .LBE106: + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1274 .loc 1 237 5 is_stmt 1 view .LVU390 + 1275 .LBB108: + 1276 .LBI108: +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1277 .loc 3 1367 22 view .LVU391 + 1278 .LBB109: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1279 .loc 3 1369 3 view .LVU392 + 1280 009a 1A6A ldr r2, [r3, #32] + 1281 009c 22F00202 bic r2, r2, #2 + 1282 00a0 1A62 str r2, [r3, #32] + 1283 .LVL127: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1284 .loc 3 1369 3 is_stmt 0 view .LVU393 + 1285 .LBE109: + 1286 .LBE108: + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1287 .loc 1 218 15 view .LVU394 + 1288 00a2 0020 movs r0, #0 + 1289 .LVL128: + 1290 .LBB111: + 1291 .LBB110: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 1292 .loc 3 1370 1 view .LVU395 + 1293 00a4 7047 bx lr + 1294 .LVL129: + 1295 .L58: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 1296 .loc 3 1370 1 view .LVU396 + 1297 .LBE110: + 1298 .LBE111: + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); + 1299 .loc 1 243 5 is_stmt 1 view .LVU397 + 1300 .LBB112: + 1301 .LBI112: +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1302 .loc 3 1295 22 view .LVU398 + 1303 .LBB113: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1304 .loc 3 1297 3 view .LVU399 + 1305 00a6 03F50C33 add r3, r3, #143360 + 1306 00aa 1A6A ldr r2, [r3, #32] + 1307 00ac 42F00402 orr r2, r2, #4 + 1308 00b0 1A62 str r2, [r3, #32] + 1309 .LVL130: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1310 .loc 3 1297 3 is_stmt 0 view .LVU400 + 1311 .LBE113: + ARM GAS /tmp/ccqfGNRw.s page 125 + + + 1312 .LBE112: + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1313 .loc 1 244 5 is_stmt 1 view .LVU401 + 1314 .LBB114: + 1315 .LBI114: +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1316 .loc 3 1367 22 view .LVU402 + 1317 .LBB115: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1318 .loc 3 1369 3 view .LVU403 + 1319 00b2 1A6A ldr r2, [r3, #32] + 1320 00b4 22F00402 bic r2, r2, #4 + 1321 00b8 1A62 str r2, [r3, #32] + 1322 .LVL131: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1323 .loc 3 1369 3 is_stmt 0 view .LVU404 + 1324 .LBE115: + 1325 .LBE114: + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1326 .loc 1 218 15 view .LVU405 + 1327 00ba 0020 movs r0, #0 + 1328 .LVL132: + 1329 .LBB117: + 1330 .LBB116: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 1331 .loc 3 1370 1 view .LVU406 + 1332 00bc 7047 bx lr + 1333 .LVL133: + 1334 .L59: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 1335 .loc 3 1370 1 view .LVU407 + 1336 .LBE116: + 1337 .LBE117: + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); + 1338 .loc 1 250 5 is_stmt 1 view .LVU408 + 1339 .LBB118: + 1340 .LBI118: +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1341 .loc 3 1295 22 view .LVU409 + 1342 .LBB119: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1343 .loc 3 1297 3 view .LVU410 + 1344 00be 03F50B33 add r3, r3, #142336 + 1345 00c2 1A6A ldr r2, [r3, #32] + 1346 00c4 42F00802 orr r2, r2, #8 + 1347 00c8 1A62 str r2, [r3, #32] + 1348 .LVL134: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1349 .loc 3 1297 3 is_stmt 0 view .LVU411 + 1350 .LBE119: + 1351 .LBE118: + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1352 .loc 1 251 5 is_stmt 1 view .LVU412 + 1353 .LBB120: + 1354 .LBI120: +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1355 .loc 3 1367 22 view .LVU413 + ARM GAS /tmp/ccqfGNRw.s page 126 + + + 1356 .LBB121: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1357 .loc 3 1369 3 view .LVU414 + 1358 00ca 1A6A ldr r2, [r3, #32] + 1359 00cc 22F00802 bic r2, r2, #8 + 1360 00d0 1A62 str r2, [r3, #32] + 1361 .LVL135: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1362 .loc 3 1369 3 is_stmt 0 view .LVU415 + 1363 .LBE121: + 1364 .LBE120: + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1365 .loc 1 218 15 view .LVU416 + 1366 00d2 0020 movs r0, #0 + 1367 .LVL136: + 1368 .LBB123: + 1369 .LBB122: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 1370 .loc 3 1370 1 view .LVU417 + 1371 00d4 7047 bx lr + 1372 .LVL137: + 1373 .L60: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 1374 .loc 3 1370 1 view .LVU418 + 1375 .LBE122: + 1376 .LBE123: + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); + 1377 .loc 1 257 5 is_stmt 1 view .LVU419 + 1378 .LBB124: + 1379 .LBI124: +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1380 .loc 3 1295 22 view .LVU420 + 1381 .LBB125: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1382 .loc 3 1297 3 view .LVU421 + 1383 00d6 03F50A33 add r3, r3, #141312 + 1384 00da 1A6A ldr r2, [r3, #32] + 1385 00dc 42F01002 orr r2, r2, #16 + 1386 00e0 1A62 str r2, [r3, #32] + 1387 .LVL138: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1388 .loc 3 1297 3 is_stmt 0 view .LVU422 + 1389 .LBE125: + 1390 .LBE124: + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1391 .loc 1 258 5 is_stmt 1 view .LVU423 + 1392 .LBB126: + 1393 .LBI126: +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1394 .loc 3 1367 22 view .LVU424 + 1395 .LBB127: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1396 .loc 3 1369 3 view .LVU425 + 1397 00e2 1A6A ldr r2, [r3, #32] + 1398 00e4 22F01002 bic r2, r2, #16 + 1399 00e8 1A62 str r2, [r3, #32] + 1400 .LVL139: + ARM GAS /tmp/ccqfGNRw.s page 127 + + +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1401 .loc 3 1369 3 is_stmt 0 view .LVU426 + 1402 .LBE127: + 1403 .LBE126: + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1404 .loc 1 218 15 view .LVU427 + 1405 00ea 0020 movs r0, #0 + 1406 .LVL140: + 1407 .LBB129: + 1408 .LBB128: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 1409 .loc 3 1370 1 view .LVU428 + 1410 00ec 7047 bx lr + 1411 .LVL141: + 1412 .L61: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 1413 .loc 3 1370 1 view .LVU429 + 1414 .LBE128: + 1415 .LBE129: + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); + 1416 .loc 1 264 5 is_stmt 1 view .LVU430 + 1417 .LBB130: + 1418 .LBI130: +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1419 .loc 3 1295 22 view .LVU431 + 1420 .LBB131: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1421 .loc 3 1297 3 view .LVU432 + 1422 00ee 03F50933 add r3, r3, #140288 + 1423 00f2 1A6A ldr r2, [r3, #32] + 1424 00f4 42F02002 orr r2, r2, #32 + 1425 00f8 1A62 str r2, [r3, #32] + 1426 .LVL142: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1427 .loc 3 1297 3 is_stmt 0 view .LVU433 + 1428 .LBE131: + 1429 .LBE130: + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1430 .loc 1 265 5 is_stmt 1 view .LVU434 + 1431 .LBB132: + 1432 .LBI132: +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1433 .loc 3 1367 22 view .LVU435 + 1434 .LBB133: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1435 .loc 3 1369 3 view .LVU436 + 1436 00fa 1A6A ldr r2, [r3, #32] + 1437 00fc 22F02002 bic r2, r2, #32 + 1438 0100 1A62 str r2, [r3, #32] + 1439 .LVL143: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1440 .loc 3 1369 3 is_stmt 0 view .LVU437 + 1441 .LBE133: + 1442 .LBE132: + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1443 .loc 1 218 15 view .LVU438 + 1444 0102 0020 movs r0, #0 + ARM GAS /tmp/ccqfGNRw.s page 128 + + + 1445 .LVL144: + 1446 .LBB135: + 1447 .LBB134: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 1448 .loc 3 1370 1 view .LVU439 + 1449 0104 7047 bx lr + 1450 .LVL145: + 1451 .L62: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 1452 .loc 3 1370 1 view .LVU440 + 1453 .LBE134: + 1454 .LBE135: + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8); + 1455 .loc 1 271 5 is_stmt 1 view .LVU441 + 1456 .LBB136: + 1457 .LBI136: +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1458 .loc 3 1768 22 view .LVU442 + 1459 .LBB137: +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1460 .loc 3 1770 3 view .LVU443 + 1461 0106 03F59A33 add r3, r3, #78848 + 1462 010a 5A6A ldr r2, [r3, #36] + 1463 010c 42F00202 orr r2, r2, #2 + 1464 0110 5A62 str r2, [r3, #36] + 1465 .LVL146: +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1466 .loc 3 1770 3 is_stmt 0 view .LVU444 + 1467 .LBE137: + 1468 .LBE136: + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1469 .loc 1 272 5 is_stmt 1 view .LVU445 + 1470 .LBB138: + 1471 .LBI138: +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1472 .loc 3 1825 22 view .LVU446 + 1473 .LBB139: +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1474 .loc 3 1827 3 view .LVU447 + 1475 0112 5A6A ldr r2, [r3, #36] + 1476 0114 22F00202 bic r2, r2, #2 + 1477 0118 5A62 str r2, [r3, #36] + 1478 .LVL147: +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1479 .loc 3 1827 3 is_stmt 0 view .LVU448 + 1480 .LBE139: + 1481 .LBE138: + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1482 .loc 1 218 15 view .LVU449 + 1483 011a 0020 movs r0, #0 + 1484 .LVL148: + 1485 .LBB141: + 1486 .LBB140: + 1487 .loc 3 1828 1 view .LVU450 + 1488 011c 7047 bx lr + 1489 .LVL149: + 1490 .L63: + ARM GAS /tmp/ccqfGNRw.s page 129 + + + 1491 .loc 3 1828 1 view .LVU451 + 1492 .LBE140: + 1493 .LBE141: + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9); + 1494 .loc 1 278 5 is_stmt 1 view .LVU452 + 1495 .LBB142: + 1496 .LBI142: +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1497 .loc 3 1768 22 view .LVU453 + 1498 .LBB143: +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1499 .loc 3 1770 3 view .LVU454 + 1500 011e 03F57843 add r3, r3, #63488 + 1501 0122 5A6A ldr r2, [r3, #36] + 1502 0124 42F48032 orr r2, r2, #65536 + 1503 0128 5A62 str r2, [r3, #36] + 1504 .LVL150: +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1505 .loc 3 1770 3 is_stmt 0 view .LVU455 + 1506 .LBE143: + 1507 .LBE142: + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1508 .loc 1 279 5 is_stmt 1 view .LVU456 + 1509 .LBB144: + 1510 .LBI144: +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1511 .loc 3 1825 22 view .LVU457 + 1512 .LBB145: +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1513 .loc 3 1827 3 view .LVU458 + 1514 012a 5A6A ldr r2, [r3, #36] + 1515 012c 22F48032 bic r2, r2, #65536 + 1516 0130 5A62 str r2, [r3, #36] + 1517 .LVL151: +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1518 .loc 3 1827 3 is_stmt 0 view .LVU459 + 1519 .LBE145: + 1520 .LBE144: + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1521 .loc 1 218 15 view .LVU460 + 1522 0132 0020 movs r0, #0 + 1523 .LVL152: + 1524 .LBB147: + 1525 .LBB146: + 1526 .loc 3 1828 1 view .LVU461 + 1527 0134 7047 bx lr + 1528 .LVL153: + 1529 .L64: + 1530 .loc 3 1828 1 view .LVU462 + 1531 .LBE146: + 1532 .LBE147: + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10); + 1533 .loc 1 285 5 is_stmt 1 view .LVU463 + 1534 .LBB148: + 1535 .LBI148: +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1536 .loc 3 1768 22 view .LVU464 + ARM GAS /tmp/ccqfGNRw.s page 130 + + + 1537 .LBB149: +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1538 .loc 3 1770 3 view .LVU465 + 1539 0136 03F57443 add r3, r3, #62464 + 1540 013a 5A6A ldr r2, [r3, #36] + 1541 013c 42F40032 orr r2, r2, #131072 + 1542 0140 5A62 str r2, [r3, #36] + 1543 .LVL154: +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1544 .loc 3 1770 3 is_stmt 0 view .LVU466 + 1545 .LBE149: + 1546 .LBE148: + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1547 .loc 1 286 5 is_stmt 1 view .LVU467 + 1548 .LBB150: + 1549 .LBI150: +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1550 .loc 3 1825 22 view .LVU468 + 1551 .LBB151: +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1552 .loc 3 1827 3 view .LVU469 + 1553 0142 5A6A ldr r2, [r3, #36] + 1554 0144 22F40032 bic r2, r2, #131072 + 1555 0148 5A62 str r2, [r3, #36] + 1556 .LVL155: +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1557 .loc 3 1827 3 is_stmt 0 view .LVU470 + 1558 .LBE151: + 1559 .LBE150: + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1560 .loc 1 218 15 view .LVU471 + 1561 014a 0020 movs r0, #0 + 1562 .LVL156: + 1563 .LBB153: + 1564 .LBB152: + 1565 .loc 3 1828 1 view .LVU472 + 1566 014c 7047 bx lr + 1567 .LVL157: + 1568 .L65: + 1569 .loc 3 1828 1 view .LVU473 + 1570 .LBE152: + 1571 .LBE153: + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11); + 1572 .loc 1 292 5 is_stmt 1 view .LVU474 + 1573 .LBB154: + 1574 .LBI154: +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1575 .loc 3 1768 22 view .LVU475 + 1576 .LBB155: +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1577 .loc 3 1770 3 view .LVU476 + 1578 014e 03F57043 add r3, r3, #61440 + 1579 0152 5A6A ldr r2, [r3, #36] + 1580 0154 42F48022 orr r2, r2, #262144 + 1581 0158 5A62 str r2, [r3, #36] + 1582 .LVL158: +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + ARM GAS /tmp/ccqfGNRw.s page 131 + + + 1583 .loc 3 1770 3 is_stmt 0 view .LVU477 + 1584 .LBE155: + 1585 .LBE154: + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1586 .loc 1 293 5 is_stmt 1 view .LVU478 + 1587 .LBB156: + 1588 .LBI156: +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1589 .loc 3 1825 22 view .LVU479 + 1590 .LBB157: +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1591 .loc 3 1827 3 view .LVU480 + 1592 015a 5A6A ldr r2, [r3, #36] + 1593 015c 22F48022 bic r2, r2, #262144 + 1594 0160 5A62 str r2, [r3, #36] + 1595 .LVL159: +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1596 .loc 3 1827 3 is_stmt 0 view .LVU481 + 1597 .LBE157: + 1598 .LBE156: + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1599 .loc 1 218 15 view .LVU482 + 1600 0162 0020 movs r0, #0 + 1601 .LVL160: + 1602 .LBB159: + 1603 .LBB158: + 1604 .loc 3 1828 1 view .LVU483 + 1605 0164 7047 bx lr + 1606 .LVL161: + 1607 .L66: + 1608 .loc 3 1828 1 view .LVU484 + 1609 .LBE158: + 1610 .LBE159: + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12); + 1611 .loc 1 299 5 is_stmt 1 view .LVU485 + 1612 .LBB160: + 1613 .LBI160: +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1614 .loc 3 1295 22 view .LVU486 + 1615 .LBB161: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1616 .loc 3 1297 3 view .LVU487 + 1617 0166 03F50833 add r3, r3, #139264 + 1618 016a 1A6A ldr r2, [r3, #32] + 1619 016c 42F04002 orr r2, r2, #64 + 1620 0170 1A62 str r2, [r3, #32] + 1621 .LVL162: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1622 .loc 3 1297 3 is_stmt 0 view .LVU488 + 1623 .LBE161: + 1624 .LBE160: + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1625 .loc 1 300 5 is_stmt 1 view .LVU489 + 1626 .LBB162: + 1627 .LBI162: +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1628 .loc 3 1367 22 view .LVU490 + ARM GAS /tmp/ccqfGNRw.s page 132 + + + 1629 .LBB163: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1630 .loc 3 1369 3 view .LVU491 + 1631 0172 1A6A ldr r2, [r3, #32] + 1632 0174 22F04002 bic r2, r2, #64 + 1633 0178 1A62 str r2, [r3, #32] + 1634 .LVL163: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1635 .loc 3 1369 3 is_stmt 0 view .LVU492 + 1636 .LBE163: + 1637 .LBE162: + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1638 .loc 1 218 15 view .LVU493 + 1639 017a 0020 movs r0, #0 + 1640 .LVL164: + 1641 .LBB165: + 1642 .LBB164: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 1643 .loc 3 1370 1 view .LVU494 + 1644 017c 7047 bx lr + 1645 .LVL165: + 1646 .L67: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 1647 .loc 3 1370 1 view .LVU495 + 1648 .LBE164: + 1649 .LBE165: + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13); + 1650 .loc 1 306 5 is_stmt 1 view .LVU496 + 1651 .LBB166: + 1652 .LBI166: +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1653 .loc 3 1295 22 view .LVU497 + 1654 .LBB167: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1655 .loc 3 1297 3 view .LVU498 + 1656 017e 03F50733 add r3, r3, #138240 + 1657 0182 1A6A ldr r2, [r3, #32] + 1658 0184 42F08002 orr r2, r2, #128 + 1659 0188 1A62 str r2, [r3, #32] + 1660 .LVL166: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1661 .loc 3 1297 3 is_stmt 0 view .LVU499 + 1662 .LBE167: + 1663 .LBE166: + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1664 .loc 1 307 5 is_stmt 1 view .LVU500 + 1665 .LBB168: + 1666 .LBI168: +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1667 .loc 3 1367 22 view .LVU501 + 1668 .LBB169: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1669 .loc 3 1369 3 view .LVU502 + 1670 018a 1A6A ldr r2, [r3, #32] + 1671 018c 22F08002 bic r2, r2, #128 + 1672 0190 1A62 str r2, [r3, #32] + 1673 .LVL167: + ARM GAS /tmp/ccqfGNRw.s page 133 + + +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1674 .loc 3 1369 3 is_stmt 0 view .LVU503 + 1675 .LBE169: + 1676 .LBE168: + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1677 .loc 1 218 15 view .LVU504 + 1678 0192 0020 movs r0, #0 + 1679 .LVL168: + 1680 .LBB171: + 1681 .LBB170: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 1682 .loc 3 1370 1 view .LVU505 + 1683 0194 7047 bx lr + 1684 .LVL169: + 1685 .L68: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 1686 .loc 3 1370 1 view .LVU506 + 1687 .LBE170: + 1688 .LBE171: + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14); + 1689 .loc 1 313 5 is_stmt 1 view .LVU507 + 1690 .LBB172: + 1691 .LBI172: +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1692 .loc 3 1295 22 view .LVU508 + 1693 .LBB173: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1694 .loc 3 1297 3 view .LVU509 + 1695 0196 03F50633 add r3, r3, #137216 + 1696 019a 1A6A ldr r2, [r3, #32] + 1697 019c 42F48072 orr r2, r2, #256 + 1698 01a0 1A62 str r2, [r3, #32] + 1699 .LVL170: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1700 .loc 3 1297 3 is_stmt 0 view .LVU510 + 1701 .LBE173: + 1702 .LBE172: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1703 .loc 1 314 5 is_stmt 1 view .LVU511 + 1704 .LBB174: + 1705 .LBI174: +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 1706 .loc 3 1367 22 view .LVU512 + 1707 .LBB175: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1708 .loc 3 1369 3 view .LVU513 + 1709 01a2 1A6A ldr r2, [r3, #32] + 1710 01a4 22F48072 bic r2, r2, #256 + 1711 01a8 1A62 str r2, [r3, #32] + 1712 .LVL171: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 1713 .loc 3 1369 3 is_stmt 0 view .LVU514 + 1714 .LBE175: + 1715 .LBE174: + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1716 .loc 1 218 15 view .LVU515 + 1717 01aa 0020 movs r0, #0 + ARM GAS /tmp/ccqfGNRw.s page 134 + + + 1718 .LVL172: + 1719 .LBB177: + 1720 .LBB176: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 1721 .loc 3 1370 1 view .LVU516 + 1722 01ac 7047 bx lr + 1723 .L70: + 1724 01ae 00BF .align 2 + 1725 .L69: + 1726 01b0 00000140 .word 1073807360 + 1727 01b4 00040040 .word 1073742848 + 1728 01b8 00080040 .word 1073743872 + 1729 01bc 000C0040 .word 1073744896 + 1730 01c0 00100040 .word 1073745920 + 1731 01c4 00140040 .word 1073746944 + 1732 01c8 00040140 .word 1073808384 + 1733 01cc 00400140 .word 1073823744 + 1734 01d0 00440140 .word 1073824768 + 1735 01d4 00480140 .word 1073825792 + 1736 01d8 00180040 .word 1073747968 + 1737 01dc 001C0040 .word 1073748992 + 1738 01e0 00200040 .word 1073750016 + 1739 01e4 00380240 .word 1073887232 + 1740 .LBE176: + 1741 .LBE177: + 1742 .cfi_endproc + 1743 .LFE378: + 1745 .section .text.LL_TIM_StructInit,"ax",%progbits + 1746 .align 1 + 1747 .global LL_TIM_StructInit + 1748 .syntax unified + 1749 .thumb + 1750 .thumb_func + 1752 LL_TIM_StructInit: + 1753 .LVL173: + 1754 .LFB379: + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the default configuration */ + 1755 .loc 1 332 1 is_stmt 1 view -0 + 1756 .cfi_startproc + 1757 @ args = 0, pretend = 0, frame = 0 + 1758 @ frame_needed = 0, uses_anonymous_args = 0 + 1759 @ link register save eliminated. + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; + 1760 .loc 1 334 3 view .LVU518 + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; + 1761 .loc 1 334 37 is_stmt 0 view .LVU519 + 1762 0000 0023 movs r3, #0 + 1763 0002 0380 strh r3, [r0] @ movhi + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_InitStruct->Autoreload = 0xFFFFFFFFU; + 1764 .loc 1 335 3 is_stmt 1 view .LVU520 + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_InitStruct->Autoreload = 0xFFFFFFFFU; + 1765 .loc 1 335 37 is_stmt 0 view .LVU521 + 1766 0004 4360 str r3, [r0, #4] + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + 1767 .loc 1 336 3 is_stmt 1 view .LVU522 + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + 1768 .loc 1 336 37 is_stmt 0 view .LVU523 + ARM GAS /tmp/ccqfGNRw.s page 135 + + + 1769 0006 4FF0FF32 mov r2, #-1 + 1770 000a 8260 str r2, [r0, #8] + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_InitStruct->RepetitionCounter = 0x00000000U; + 1771 .loc 1 337 3 is_stmt 1 view .LVU524 + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_InitStruct->RepetitionCounter = 0x00000000U; + 1772 .loc 1 337 37 is_stmt 0 view .LVU525 + 1773 000c C360 str r3, [r0, #12] + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1774 .loc 1 338 3 is_stmt 1 view .LVU526 + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1775 .loc 1 338 37 is_stmt 0 view .LVU527 + 1776 000e 0361 str r3, [r0, #16] + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1777 .loc 1 339 1 view .LVU528 + 1778 0010 7047 bx lr + 1779 .cfi_endproc + 1780 .LFE379: + 1782 .section .text.LL_TIM_Init,"ax",%progbits + 1783 .align 1 + 1784 .global LL_TIM_Init + 1785 .syntax unified + 1786 .thumb + 1787 .thumb_func + 1789 LL_TIM_Init: + 1790 .LVL174: + 1791 .LFB380: + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpcr1; + 1792 .loc 1 351 1 is_stmt 1 view -0 + 1793 .cfi_startproc + 1794 @ args = 0, pretend = 0, frame = 0 + 1795 @ frame_needed = 0, uses_anonymous_args = 0 + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpcr1; + 1796 .loc 1 351 1 is_stmt 0 view .LVU530 + 1797 0000 30B5 push {r4, r5, lr} + 1798 .LCFI20: + 1799 .cfi_def_cfa_offset 12 + 1800 .cfi_offset 4, -12 + 1801 .cfi_offset 5, -8 + 1802 .cfi_offset 14, -4 + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1803 .loc 1 352 3 is_stmt 1 view .LVU531 + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); + 1804 .loc 1 355 3 view .LVU532 + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); + 1805 .loc 1 356 3 view .LVU533 + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1806 .loc 1 357 3 view .LVU534 + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1807 .loc 1 359 3 view .LVU535 + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1808 .loc 1 359 10 is_stmt 0 view .LVU536 + 1809 0002 0368 ldr r3, [r0] + 1810 .LVL175: + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1811 .loc 1 361 3 is_stmt 1 view .LVU537 + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1812 .loc 1 361 7 is_stmt 0 view .LVU538 + ARM GAS /tmp/ccqfGNRw.s page 136 + + + 1813 0004 3B4A ldr r2, .L81 + 1814 0006 9042 cmp r0, r2 + 1815 0008 14BF ite ne + 1816 000a 4FF0000E movne lr, #0 + 1817 000e 4FF0010E moveq lr, #1 + 1818 0012 B0F1804F cmp r0, #1073741824 + 1819 0016 14BF ite ne + 1820 0018 7246 movne r2, lr + 1821 001a 4EF00102 orreq r2, lr, #1 + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1822 .loc 1 361 6 view .LVU539 + 1823 001e AAB9 cbnz r2, .L73 + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1824 .loc 1 361 7 discriminator 1 view .LVU540 + 1825 0020 354C ldr r4, .L81+4 + 1826 0022 A042 cmp r0, r4 + 1827 0024 14BF ite ne + 1828 0026 0024 movne r4, #0 + 1829 0028 0124 moveq r4, #1 + 1830 002a 344D ldr r5, .L81+8 + 1831 002c A842 cmp r0, r5 + 1832 002e 0DD0 beq .L73 + 1833 0030 64B9 cbnz r4, .L73 + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1834 .loc 1 361 7 discriminator 2 view .LVU541 + 1835 0032 04F18044 add r4, r4, #1073741824 + 1836 0036 04F58234 add r4, r4, #66560 + 1837 003a A042 cmp r0, r4 + 1838 003c 14BF ite ne + 1839 003e 0024 movne r4, #0 + 1840 0040 0124 moveq r4, #1 + 1841 0042 05F50065 add r5, r5, #2048 + 1842 0046 A842 cmp r0, r5 + 1843 0048 00D0 beq .L73 + 1844 004a 1CB1 cbz r4, .L74 + 1845 .L73: + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1846 .loc 1 364 5 is_stmt 1 view .LVU542 + 1847 004c 23F07003 bic r3, r3, #112 + 1848 .LVL176: + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1849 .loc 1 364 5 is_stmt 0 view .LVU543 + 1850 0050 4C68 ldr r4, [r1, #4] + 1851 0052 2343 orrs r3, r3, r4 + 1852 .LVL177: + 1853 .L74: + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1854 .loc 1 367 3 is_stmt 1 view .LVU544 + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1855 .loc 1 367 6 is_stmt 0 view .LVU545 + 1856 0054 002A cmp r2, #0 + 1857 0056 33D1 bne .L76 + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1858 .loc 1 367 7 discriminator 1 view .LVU546 + 1859 0058 274A ldr r2, .L81+4 + 1860 005a 9042 cmp r0, r2 + 1861 005c 14BF ite ne + ARM GAS /tmp/ccqfGNRw.s page 137 + + + 1862 005e 0022 movne r2, #0 + 1863 0060 0122 moveq r2, #1 + 1864 0062 264C ldr r4, .L81+8 + 1865 0064 A042 cmp r0, r4 + 1866 0066 2BD0 beq .L76 + 1867 0068 52BB cbnz r2, .L76 + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1868 .loc 1 367 7 discriminator 2 view .LVU547 + 1869 006a 02F18042 add r2, r2, #1073741824 + 1870 006e 02F58232 add r2, r2, #66560 + 1871 0072 9042 cmp r0, r2 + 1872 0074 14BF ite ne + 1873 0076 0022 movne r2, #0 + 1874 0078 0122 moveq r2, #1 + 1875 007a 04F50064 add r4, r4, #2048 + 1876 007e A042 cmp r0, r4 + 1877 0080 1ED0 beq .L76 + 1878 0082 EAB9 cbnz r2, .L76 + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1879 .loc 1 367 7 discriminator 3 view .LVU548 + 1880 0084 1E4A ldr r2, .L81+12 + 1881 0086 9042 cmp r0, r2 + 1882 0088 14BF ite ne + 1883 008a 0022 movne r2, #0 + 1884 008c 0122 moveq r2, #1 + 1885 008e 04F59A34 add r4, r4, #78848 + 1886 0092 A042 cmp r0, r4 + 1887 0094 14D0 beq .L76 + 1888 0096 9AB9 cbnz r2, .L76 + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1889 .loc 1 367 7 discriminator 4 view .LVU549 + 1890 0098 1A4A ldr r2, .L81+16 + 1891 009a 9042 cmp r0, r2 + 1892 009c 14BF ite ne + 1893 009e 0022 movne r2, #0 + 1894 00a0 0122 moveq r2, #1 + 1895 00a2 04F50064 add r4, r4, #2048 + 1896 00a6 A042 cmp r0, r4 + 1897 00a8 0AD0 beq .L76 + 1898 00aa 4AB9 cbnz r2, .L76 + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1899 .loc 1 367 7 discriminator 5 view .LVU550 + 1900 00ac 164A ldr r2, .L81+20 + 1901 00ae 9042 cmp r0, r2 + 1902 00b0 14BF ite ne + 1903 00b2 0022 movne r2, #0 + 1904 00b4 0122 moveq r2, #1 + 1905 00b6 A4F59634 sub r4, r4, #76800 + 1906 00ba A042 cmp r0, r4 + 1907 00bc 00D0 beq .L76 + 1908 00be 22B1 cbz r2, .L77 + 1909 .L76: + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1910 .loc 1 370 5 is_stmt 1 view .LVU551 + 1911 00c0 23F4407C bic ip, r3, #768 + 1912 00c4 CB68 ldr r3, [r1, #12] + 1913 .LVL178: + ARM GAS /tmp/ccqfGNRw.s page 138 + + + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1914 .loc 1 370 5 is_stmt 0 view .LVU552 + 1915 00c6 4CEA0303 orr r3, ip, r3 + 1916 .LVL179: + 1917 .L77: + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1918 .loc 1 374 3 is_stmt 1 view .LVU553 + 1919 00ca 0360 str r3, [r0] + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1920 .loc 1 377 3 view .LVU554 + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1921 .loc 1 377 44 is_stmt 0 view .LVU555 + 1922 00cc 8A68 ldr r2, [r1, #8] + 1923 .LVL180: + 1924 .LBB178: + 1925 .LBI178: +1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 1926 .loc 2 1635 22 is_stmt 1 view .LVU556 + 1927 .LBB179: +1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 1928 .loc 2 1637 3 view .LVU557 + 1929 00ce C262 str r2, [r0, #44] + 1930 .LVL181: +1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 1931 .loc 2 1637 3 is_stmt 0 view .LVU558 + 1932 .LBE179: + 1933 .LBE178: + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1934 .loc 1 380 3 is_stmt 1 view .LVU559 + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1935 .loc 1 380 43 is_stmt 0 view .LVU560 + 1936 00d0 0A88 ldrh r2, [r1] + 1937 .LVL182: + 1938 .LBB180: + 1939 .LBI180: +1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 1940 .loc 2 1608 22 is_stmt 1 view .LVU561 + 1941 .LBB181: +1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 1942 .loc 2 1610 3 view .LVU562 + 1943 00d2 8262 str r2, [r0, #40] + 1944 .LVL183: +1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 1945 .loc 2 1610 3 is_stmt 0 view .LVU563 + 1946 .LBE181: + 1947 .LBE180: + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1948 .loc 1 382 3 is_stmt 1 view .LVU564 + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 1949 .loc 1 382 7 is_stmt 0 view .LVU565 + 1950 00d4 0D4A ldr r2, .L81+24 + 1951 00d6 9042 cmp r0, r2 + 1952 00d8 14BF ite ne + 1953 00da 7346 movne r3, lr + 1954 00dc 4EF00103 orreq r3, lr, #1 + 1955 .LVL184: + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + ARM GAS /tmp/ccqfGNRw.s page 139 + + + 1956 .loc 1 382 6 view .LVU566 + 1957 00e0 0BB1 cbz r3, .L79 + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1958 .loc 1 385 5 is_stmt 1 view .LVU567 + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1959 .loc 1 385 53 is_stmt 0 view .LVU568 + 1960 00e2 0B69 ldr r3, [r1, #16] + 1961 .LVL185: + 1962 .LBB182: + 1963 .LBI182: +1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 1964 .loc 2 1663 22 is_stmt 1 view .LVU569 + 1965 .LBB183: +1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 1966 .loc 2 1665 3 view .LVU570 + 1967 00e4 0363 str r3, [r0, #48] + 1968 .LVL186: + 1969 .L79: +1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 1970 .loc 2 1665 3 is_stmt 0 view .LVU571 + 1971 .LBE183: + 1972 .LBE182: + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1973 .loc 1 390 3 is_stmt 1 view .LVU572 + 1974 .LBB184: + 1975 .LBI184: +2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR1) set for output channel 1. +2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF +2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not +2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 1 is supported by a timer instance. +2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 +2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) +2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR1)); +2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR2) set for output channel 2. +2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF +2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not +2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 2 is supported by a timer instance. +2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 +2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) +2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + ARM GAS /tmp/ccqfGNRw.s page 140 + + +2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR2)); +2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR3) set for output channel 3. +2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF +2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not +2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 3 is supported by a timer instance. +2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 +2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) +2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR3)); +2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR4) set for output channel 4. +2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFF +2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not +2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 4 is supported by a timer instance. +2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 +2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) +2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR4)); +2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR5) set for output channel 5. +2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not +2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 5 is supported by a timer instance. +2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 +2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) +2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); +2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get compare value (TIMx_CCR6) set for output channel 6. +2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not +2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * output channel 6 is supported by a timer instance. +2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 +2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CompareValue (between Min_Data=0 and Max_Data=65535) +2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) + ARM GAS /tmp/ccqfGNRw.s page 141 + + +2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR6)); +2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Select on which reference signal the OC5REF is combined to. +2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check +2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports the combined 3-phase PWM mode. +2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n +2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n +2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels +2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param GroupCH5 This parameter can be a combination of the following values: +2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_NONE +2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC1REFC +2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC2REFC +2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_GROUPCH5_OC3REFC +2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) +2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); +2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration +2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure input channel. +2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n +2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC1PSC LL_TIM_IC_Config\n +2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC1F LL_TIM_IC_Config\n +2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_Config\n +2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_Config\n +2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_Config\n +2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_Config\n +2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_Config\n +2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_Config\n +2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_Config\n +2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_Config\n +2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_Config\n +2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1P LL_TIM_IC_Config\n +2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_Config\n +2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_Config\n +2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_Config\n +2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_Config\n +2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_Config\n +2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_Config\n +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_Config +2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 + ARM GAS /tmp/ccqfGNRw.s page 142 + + +2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Configuration This parameter must be a combination of all the following values: +2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_ +2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 +2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 +2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_I +2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChanne +2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) +2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** << SHIFT_TAB_ICxx[iChannel]); +2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), +2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); +2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the active input. +2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n +2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n +2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n +2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_SetActiveInput +2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICActiveInput This parameter can be one of the following values: +2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI +2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI +2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_TRC +2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiv +2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT +2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current active input. +2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n +2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n +2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n +2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 CC4S LL_TIM_IC_GetActiveInput +2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 + ARM GAS /tmp/ccqfGNRw.s page 143 + + +2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI +2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI +2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ACTIVEINPUT_TRC +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) +2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann +2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the prescaler of input channel. +2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n +2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n +2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n +2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler +2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICPrescaler This parameter can be one of the following values: +2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 +2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 +2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 +2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 +2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescal +2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT +2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current prescaler value acting on an input channel. +2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n +2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n +2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n +2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler +2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV1 +2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV2 +2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV4 +2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ICPSC_DIV8 +2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) + ARM GAS /tmp/ccqfGNRw.s page 144 + + +2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iCha +2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the input filter duration. +2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n +2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_SetFilter\n +2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_SetFilter\n +2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_SetFilter +2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICFilter This parameter can be one of the following values: +2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 +2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 +2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 +2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 +2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 +2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 +2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 +2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 +2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 +2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 +2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 +2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 +2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 +2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 +2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 +2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 +2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) +2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iC +2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ +2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the input filter duration. +2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n +2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR1 IC2F LL_TIM_IC_GetFilter\n +2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC3F LL_TIM_IC_GetFilter\n +2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCMR2 IC4F LL_TIM_IC_GetFilter +2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: + ARM GAS /tmp/ccqfGNRw.s page 145 + + +2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1 +2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 +2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 +2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 +2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 +2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 +2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 +2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 +2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 +2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 +2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 +2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 +2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 +2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 +2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 +2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 +2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) +2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CC +2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChann +2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the input channel polarity. +2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n +2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_SetPolarity\n +2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_SetPolarity\n +2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_SetPolarity\n +2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_SetPolarity\n +2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_SetPolarity\n +2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_SetPolarity\n +2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_SetPolarity +2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ICPolarity This parameter can be one of the following values: +2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING +2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_FALLING +2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE +2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity +2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), +2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** ICPolarity << SHIFT_TAB_CCxP[iChannel]); +2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get the current input channel polarity. +2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n +2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC1NP LL_TIM_IC_GetPolarity\n + ARM GAS /tmp/ccqfGNRw.s page 146 + + +2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2P LL_TIM_IC_GetPolarity\n +2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC2NP LL_TIM_IC_GetPolarity\n +2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3P LL_TIM_IC_GetPolarity\n +2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC3NP LL_TIM_IC_GetPolarity\n +2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4P LL_TIM_IC_GetPolarity\n +2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * CCER CC4NP LL_TIM_IC_GetPolarity +2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Channel This parameter can be one of the following values: +2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH1 +2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH2 +2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH3 +2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CHANNEL_CH4 +2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval Returned value can be one of the following values: +2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_RISING +2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_FALLING +2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE +2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); +2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> +2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SHIFT_TAB_CCxP[iChannel]); +2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). +2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not +2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. +2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination +2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) +2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->CR2, TIM_CR2_TI1S); +2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. +2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not +2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. +2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination +2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) +2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); +2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. +2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not +2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an XOR input. +2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination +2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). + ARM GAS /tmp/ccqfGNRw.s page 147 + + +2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) +2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); +2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 1. +2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF +2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not +2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 1 is supported by a timer instance. +2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 +2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) +2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) +2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR1)); +2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 2. +2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF +2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not +2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 2 is supported by a timer instance. +2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 +2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) +2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) +2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR2)); +2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 3. +2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF +2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not +3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 3 is supported by a timer instance. +3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 +3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) +3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) +3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR3)); +3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Get captured value for input channel 4. +3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xF + ARM GAS /tmp/ccqfGNRw.s page 148 + + +3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check +3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports a 32 bits counter. +3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not +3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * input channel 4 is supported by a timer instance. +3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 +3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) +3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) +3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return (uint32_t)(READ_REG(TIMx->CCR4)); +3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection +3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable external clock mode 2. +3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ET +3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check +3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. +3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_EnableExternalClock +3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) +3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); +3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable external clock mode 2. +3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check +3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. +3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_DisableExternalClock +3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) +3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); +3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether external clock mode 2 is enabled. +3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check +3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. +3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock +3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) +3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + ARM GAS /tmp/ccqfGNRw.s page 149 + + +3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); +3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the clock source of the counter clock. +3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note when selected clock source is external clock mode 1, the timer input +3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() +3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * function. This timer input must be configured by calling +3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * the @ref LL_TIM_IC_Config() function. +3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check +3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode1. +3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check +3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports external clock mode2. +3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetClockSource\n +3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ECE LL_TIM_SetClockSource +3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ClockSource This parameter can be one of the following values: +3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL +3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 +3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 +3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) +3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); +3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the encoder interface mode. +3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check +3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance supports the encoder mode. +3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetEncoderMode +3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param EncoderMode This parameter can be one of the following values: +3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 +3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 +3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 +3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) +3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); +3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration +3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger output (TRGO) used for timer synchronization . +3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check +3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance can operate as a master timer. +3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput +3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance + ARM GAS /tmp/ccqfGNRw.s page 150 + + +3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TimerSynchronization This parameter can be one of the following values: +3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_RESET +3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_ENABLE +3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_UPDATE +3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_CC1IF +3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC1REF +3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC2REF +3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC3REF +3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO_OC4REF +3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) +3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); +3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . +3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check +3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * whether or not a timer instance can be used for ADC synchronization. +3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 +3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer Instance +3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ADCSynchronization This parameter can be one of the following values: +3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_RESET +3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_ENABLE +3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_UPDATE +3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_CC1F +3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC1 +3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC2 +3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC3 +3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4 +3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5 +3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC6 +3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING +3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING +3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING +3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING +3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING +3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING +3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) +3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); +3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the synchronization mode of a slave timer. +3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. +3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR SMS LL_TIM_SetSlaveMode +3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param SlaveMode This parameter can be one of the following values: +3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_DISABLED +3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_RESET +3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_GATED +3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_TRIGGER + ARM GAS /tmp/ccqfGNRw.s page 151 + + +3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER +3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) +3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); +3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the selects the trigger input to be used to synchronize the counter. +3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. +3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR TS LL_TIM_SetTriggerInput +3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TriggerInput This parameter can be one of the following values: +3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR0 +3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR1 +3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR2 +3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ITR3 +3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI1F_ED +3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI1FP1 +3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_TI2FP2 +3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TS_ETRF +3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) +3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); +3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the Master/Slave mode. +3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. +3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode +3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) +3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); +3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the Master/Slave mode. +3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. +3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode +3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) +3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); +3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + ARM GAS /tmp/ccqfGNRw.s page 152 + + +3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the Master/Slave mode is enabled. +3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not +3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance can operate as a slave timer. +3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode +3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) +3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); +3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the external trigger (ETR) input. +3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not +3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides an external trigger input. +3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SMCR ETP LL_TIM_ConfigETR\n +3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ETPS LL_TIM_ConfigETR\n +3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * SMCR ETF LL_TIM_ConfigETR +3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRPolarity This parameter can be one of the following values: +3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED +3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_POLARITY_INVERTED +3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRPrescaler This parameter can be one of the following values: +3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 +3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 +3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 +3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 +3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param ETRFilter This parameter can be one of the following values: +3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1 +3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 +3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 +3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 +3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 +3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 +3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 +3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 +3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 +3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 +3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 +3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 +3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 +3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 +3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 +3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 +3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescale +3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t ETRFilter) +3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | +3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + ARM GAS /tmp/ccqfGNRw.s page 153 + + +3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Break_Function Break function configuration +3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the break function. +3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKE LL_TIM_EnableBRK +3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) +3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); +3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the break function. +3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKE LL_TIM_DisableBRK +3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) +3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); +3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the break input. +3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n +3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR BKF LL_TIM_ConfigBRK +3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakPolarity This parameter can be one of the following values: +3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_POLARITY_LOW +3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_POLARITY_HIGH +3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakFilter This parameter can be one of the following values: +3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 +3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 +3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 +3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 +3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 +3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 +3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 +3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 +3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 +3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 +3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 +3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 +3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 +3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 +3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 +3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 +3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None + ARM GAS /tmp/ccqfGNRw.s page 154 + + +3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, +3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t BreakFilter) +3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); +3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the break 2 function. +3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not +3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. +3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 +3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) +3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the break 2 function. +3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not +3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. +3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 +3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) +3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configure the break 2 input. +3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not +3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a second break input. +3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n +3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR BK2F LL_TIM_ConfigBRK2 +3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Break2Polarity This parameter can be one of the following values: +3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_POLARITY_LOW +3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH +3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Break2Filter This parameter can be one of the following values: +3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 +3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 +3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 +3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 +3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 +3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 +3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 +3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 +3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 +3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 +3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 +3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 +3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 + ARM GAS /tmp/ccqfGNRw.s page 155 + + +3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 +3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 +3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 +3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2F +3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); +3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. +3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n +3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * BDTR OSSR LL_TIM_SetOffStates +3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OffStateIdle This parameter can be one of the following values: +3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSI_DISABLE +3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSI_ENABLE +3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param OffStateRun This parameter can be one of the following values: +3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSR_DISABLE +3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_OSSR_ENABLE +3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStat +3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); +3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable automatic output (MOE can be set by software or automatically when a break input +3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput +3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) +3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); +3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable automatic output (MOE can be set only by software). +3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput +3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) +3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); +3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + ARM GAS /tmp/ccqfGNRw.s page 156 + + +3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether automatic output is enabled. +3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput +3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) +3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); +3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). +3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by +3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * software and is reset in case of break or break2 event +3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs +3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) +3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); +3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). +3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by +3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * software and is reset in case of break or break2 event. +3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs +3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) +3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); +3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether outputs are enabled. +3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not +3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a timer instance provides a break input. +3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs +3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) +3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); +3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #if defined(TIM_BREAK_INPUT_SUPPORT) +3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + ARM GAS /tmp/ccqfGNRw.s page 157 + + +3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable the signals connected to the designated timer break input. +3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether +3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. +3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n +3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKE LL_TIM_EnableBreakInputSource\n +3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INE LL_TIM_EnableBreakInputSource\n +3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKE LL_TIM_EnableBreakInputSource +3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: +3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN +3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 +3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: +3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN +3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK +3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t +3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); +3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(*pReg, Source); +3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable the signals connected to the designated timer break input. +3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether +3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. +3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n +3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKE LL_TIM_DisableBreakInputSource\n +3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INE LL_TIM_DisableBreakInputSource\n +3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKE LL_TIM_DisableBreakInputSource +3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: +3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN +3559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 +3560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: +3561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN +3562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK +3563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_ +3566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); +3568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(*pReg, Source); +3569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Set the polarity of the break signal for the timer break input. +3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether +3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * or not a timer instance allows for break input selection. +3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n +3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF1 BKDFBKP LL_TIM_SetBreakInputSourcePolarity\n +3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n +3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * AF2 BK2DFBKP LL_TIM_SetBreakInputSourcePolarity +3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param BreakInput This parameter can be one of the following values: +3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN +3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + ARM GAS /tmp/ccqfGNRw.s page 158 + + +3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Source This parameter can be one of the following values: +3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_BKIN +3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK +3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Polarity This parameter can be one of the following values: +3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_POLARITY_LOW +3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_BKIN_POLARITY_HIGH +3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uin +3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** uint32_t Polarity) +3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); +3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOUR +3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** #endif /* TIM_BREAK_INPUT_SUPPORT */ +3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Configures the timer DMA burst feature. +3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or +3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * not a timer instance supports the DMA burst mode. +3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n +3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * DCR DBA LL_TIM_ConfigDMABurst +3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMABurstBaseAddress This parameter can be one of the following values: +3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 +3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 +3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR +3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER +3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_SR +3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR +3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 +3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 +3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER +3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT +3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC +3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR +3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR +3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 +3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 +3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 +3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 +3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR +3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_OR +3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 +3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 +3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 +3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 (*) +3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 (*) +3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (*) value not defined in all devices +3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param DMABurstLength This parameter can be one of the following values: +3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER + ARM GAS /tmp/ccqfGNRw.s page 159 + + +3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS +3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS +3642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS +3643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS +3644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS +3645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS +3646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS +3647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS +3648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS +3649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS +3650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS +3651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS +3652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS +3653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS +3654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS +3655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS +3656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS +3657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_ +3660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); +3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping +3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Remap TIM inputs (input channel, internal/external triggers). +3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not +3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * a some timer inputs can be remapped. +3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n +3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM5_OR TI4_RMP LL_TIM_SetRemap\n +3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM11_OR TI1_RMP LL_TIM_SetRemap +3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param Remap Remap param depends on the TIMx. Description available only +3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * in CHM version of the User Manual (not in .pdf). +3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Otherwise see Reference Manual description of OR registers. +3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * Below description summarizes "Timer Instance" and "Remap" param combinations: +3684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM2: one of the following values +3686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * ITR1_RMP can be one of the following values +3688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO +3689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP +3690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF +3691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF +3692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM5: one of the following values +3694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO +3696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI + ARM GAS /tmp/ccqfGNRw.s page 160 + + +3697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE +3698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC +3699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * TIM11: one of the following values +3701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO +3703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX +3704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE +3705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @arg @ref LL_TIM_TIM11_TI1_RMP_MCO1 +3706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * +3707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) +3710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); +3712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +3716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management +3719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +3720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the update interrupt flag (UIF). +3723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE +3724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) +3728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); +3730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). +3734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE +3735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) +3739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); +3741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). +3745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 +3746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) +3750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); +3752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** + ARM GAS /tmp/ccqfGNRw.s page 161 + + +3754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 inte +3756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 +3757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) +3761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); +3763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). +3767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 +3768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) +3772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); +3774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 inte +3778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 +3779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) +3783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); +3785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). +3789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 +3790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) +3794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); +3796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 inte +3800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 +3801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) +3805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); +3807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). + ARM GAS /tmp/ccqfGNRw.s page 162 + + +3811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 +3812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) +3816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); +3818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 inte +3822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 +3823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) +3827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); +3829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). +3833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 +3834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) +3838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); +3840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 inte +3844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 +3845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) +3849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); +3851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). +3855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 +3856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) +3860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); +3862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 inte +3866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 +3867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance + ARM GAS /tmp/ccqfGNRw.s page 163 + + +3868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) +3871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); +3873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the commutation interrupt flag (COMIF). +3877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR COMIF LL_TIM_ClearFlag_COM +3878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) +3882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); +3884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pe +3888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM +3889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) +3893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); +3895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the trigger interrupt flag (TIF). +3899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG +3900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) +3904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); +3906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). +3910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG +3911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) +3915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); +3917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the break interrupt flag (BIF). +3921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR BIF LL_TIM_ClearFlag_BRK +3922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + ARM GAS /tmp/ccqfGNRw.s page 164 + + +3925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) +3926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); +3928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). +3932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK +3933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) +3937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); +3939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the break 2 interrupt flag (B2IF). +3943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 +3944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) +3948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); +3950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). +3954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 +3955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) +3959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); +3961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). +3965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR +3966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) +3970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); +3972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set +3976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 1 interrupt is pending). +3977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR +3978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +3980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) + ARM GAS /tmp/ccqfGNRw.s page 165 + + +3982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); +3984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). +3988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR +3989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +3990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +3991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +3992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) +3993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +3994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); +3995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +3996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +3997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +3998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set +3999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 2 over-capture interrupt is pending). +4000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR +4001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) +4005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); +4007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). +4011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR +4012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) +4016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); +4018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set +4022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 3 over-capture interrupt is pending). +4023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR +4024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) +4028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); +4030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). +4034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR +4035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) + ARM GAS /tmp/ccqfGNRw.s page 166 + + +4039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); +4041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set +4045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * (Capture/Compare 4 over-capture interrupt is pending). +4046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR +4047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) +4051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); +4053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Clear the system break interrupt flag (SBIF). +4057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK +4058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) +4062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); +4064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is p +4068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK +4069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) +4073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); +4075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +4079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_IT_Management IT-Management +4082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +4083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable update interrupt (UIE). +4086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE +4087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) +4091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_UIE); +4093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** + ARM GAS /tmp/ccqfGNRw.s page 167 + + +4096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable update interrupt (UIE). +4097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE +4098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) +4102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); +4104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the update interrupt (UIE) is enabled. +4108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE +4109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) +4113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); +4115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable capture/compare 1 interrupt (CC1IE). +4119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 +4120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) +4124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); +4126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable capture/compare 1 interrupt (CC1IE). +4130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 +4131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) +4135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); +4137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. +4141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 +4142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) +4146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); +4148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable capture/compare 2 interrupt (CC2IE). +4152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 + ARM GAS /tmp/ccqfGNRw.s page 168 + + +4153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) +4157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); +4159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable capture/compare 2 interrupt (CC2IE). +4163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 +4164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) +4168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); +4170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. +4174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 +4175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) +4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable capture/compare 3 interrupt (CC3IE). +4185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 +4186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) +4190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); +4192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable capture/compare 3 interrupt (CC3IE). +4196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 +4197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) +4201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); +4203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. +4207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 +4208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). + ARM GAS /tmp/ccqfGNRw.s page 169 + + +4210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) +4212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); +4214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable capture/compare 4 interrupt (CC4IE). +4218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 +4219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) +4223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); +4225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable capture/compare 4 interrupt (CC4IE). +4229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 +4230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) +4234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); +4236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. +4240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 +4241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) +4245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); +4247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable commutation interrupt (COMIE). +4251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER COMIE LL_TIM_EnableIT_COM +4252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) +4256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_COMIE); +4258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable commutation interrupt (COMIE). +4262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER COMIE LL_TIM_DisableIT_COM +4263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) + ARM GAS /tmp/ccqfGNRw.s page 170 + + +4267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); +4269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the commutation interrupt (COMIE) is enabled. +4273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM +4274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) +4278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); +4280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable trigger interrupt (TIE). +4284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG +4285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) +4289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_TIE); +4291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable trigger interrupt (TIE). +4295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG +4296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) +4300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); +4302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the trigger interrupt (TIE) is enabled. +4306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG +4307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) +4311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); +4313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable break interrupt (BIE). +4317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER BIE LL_TIM_EnableIT_BRK +4318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) +4322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_BIE); + ARM GAS /tmp/ccqfGNRw.s page 171 + + +4324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable break interrupt (BIE). +4328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER BIE LL_TIM_DisableIT_BRK +4329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) +4333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); +4335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the break interrupt (BIE) is enabled. +4339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK +4340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) +4344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); +4346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +4350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_DMA_Management DMA Management +4353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +4354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable update DMA request (UDE). +4357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE +4358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) +4362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_UDE); +4364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable update DMA request (UDE). +4368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE +4369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) +4373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); +4375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the update DMA request (UDE) is enabled. +4379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE +4380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance + ARM GAS /tmp/ccqfGNRw.s page 172 + + +4381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) +4384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); +4386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable capture/compare 1 DMA request (CC1DE). +4390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 +4391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) +4395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); +4397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable capture/compare 1 DMA request (CC1DE). +4401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 +4402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) +4406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); +4408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. +4412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 +4413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) +4417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); +4419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable capture/compare 2 DMA request (CC2DE). +4423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 +4424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) +4428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); +4430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable capture/compare 2 DMA request (CC2DE). +4434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 +4435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ + ARM GAS /tmp/ccqfGNRw.s page 173 + + +4438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) +4439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); +4441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. +4445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 +4446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) +4450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); +4452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable capture/compare 3 DMA request (CC3DE). +4456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 +4457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) +4461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); +4463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable capture/compare 3 DMA request (CC3DE). +4467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 +4468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) +4472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); +4474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. +4478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 +4479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) +4483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); +4485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable capture/compare 4 DMA request (CC4DE). +4489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 +4490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) +4494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + ARM GAS /tmp/ccqfGNRw.s page 174 + + +4495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); +4496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable capture/compare 4 DMA request (CC4DE). +4500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 +4501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) +4505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); +4507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. +4511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 +4512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) +4516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); +4518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable commutation DMA request (COMDE). +4522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM +4523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) +4527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_COMDE); +4529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable commutation DMA request (COMDE). +4533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM +4534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) +4538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); +4540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the commutation DMA request (COMDE) is enabled. +4544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM +4545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) +4549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); +4551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + ARM GAS /tmp/ccqfGNRw.s page 175 + + +4552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Enable trigger interrupt (TDE). +4555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG +4556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) +4560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->DIER, TIM_DIER_TDE); +4562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Disable trigger interrupt (TDE). +4566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG +4567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) +4571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); +4573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Indicates whether the trigger interrupt (TDE) is enabled. +4577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG +4578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval State of bit (1 or 0). +4580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) +4582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); +4584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } +4585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @} +4588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** +4590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management +4591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @{ +4592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** /** +4594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @brief Generate an update event. +4595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE +4596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @param TIMx Timer instance +4597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** * @retval None +4598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** */ +4599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) + 1976 .loc 2 4599 22 view .LVU573 + 1977 .LBB185: +4600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { +4601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** SET_BIT(TIMx->EGR, TIM_EGR_UG); + 1978 .loc 2 4601 3 view .LVU574 + 1979 00e6 4369 ldr r3, [r0, #20] + 1980 00e8 43F00103 orr r3, r3, #1 + 1981 00ec 4361 str r3, [r0, #20] + 1982 .LVL187: + ARM GAS /tmp/ccqfGNRw.s page 176 + + + 1983 .loc 2 4601 3 is_stmt 0 view .LVU575 + 1984 .LBE185: + 1985 .LBE184: + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 1986 .loc 1 392 3 is_stmt 1 view .LVU576 + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1987 .loc 1 393 1 is_stmt 0 view .LVU577 + 1988 00ee 0020 movs r0, #0 + 1989 .LVL188: + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 1990 .loc 1 393 1 view .LVU578 + 1991 00f0 30BD pop {r4, r5, pc} + 1992 .L82: + 1993 00f2 00BF .align 2 + 1994 .L81: + 1995 00f4 00000140 .word 1073807360 + 1996 00f8 00080040 .word 1073743872 + 1997 00fc 00040040 .word 1073742848 + 1998 0100 00440140 .word 1073824768 + 1999 0104 00180040 .word 1073747968 + 2000 0108 00200040 .word 1073750016 + 2001 010c 00040140 .word 1073808384 + 2002 .cfi_endproc + 2003 .LFE380: + 2005 .section .text.LL_TIM_OC_StructInit,"ax",%progbits + 2006 .align 1 + 2007 .global LL_TIM_OC_StructInit + 2008 .syntax unified + 2009 .thumb + 2010 .thumb_func + 2012 LL_TIM_OC_StructInit: + 2013 .LVL189: + 2014 .LFB381: + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the default configuration */ + 2015 .loc 1 403 1 is_stmt 1 view -0 + 2016 .cfi_startproc + 2017 @ args = 0, pretend = 0, frame = 0 + 2018 @ frame_needed = 0, uses_anonymous_args = 0 + 2019 @ link register save eliminated. + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; + 2020 .loc 1 405 3 view .LVU580 + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; + 2021 .loc 1 405 35 is_stmt 0 view .LVU581 + 2022 0000 0023 movs r3, #0 + 2023 0002 0360 str r3, [r0] + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; + 2024 .loc 1 406 3 is_stmt 1 view .LVU582 + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; + 2025 .loc 1 406 35 is_stmt 0 view .LVU583 + 2026 0004 4360 str r3, [r0, #4] + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->CompareValue = 0x00000000U; + 2027 .loc 1 407 3 is_stmt 1 view .LVU584 + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->CompareValue = 0x00000000U; + 2028 .loc 1 407 35 is_stmt 0 view .LVU585 + 2029 0006 8360 str r3, [r0, #8] + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; + 2030 .loc 1 408 3 is_stmt 1 view .LVU586 + ARM GAS /tmp/ccqfGNRw.s page 177 + + + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; + 2031 .loc 1 408 35 is_stmt 0 view .LVU587 + 2032 0008 C360 str r3, [r0, #12] + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; + 2033 .loc 1 409 3 is_stmt 1 view .LVU588 + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; + 2034 .loc 1 409 35 is_stmt 0 view .LVU589 + 2035 000a 0361 str r3, [r0, #16] + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; + 2036 .loc 1 410 3 is_stmt 1 view .LVU590 + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; + 2037 .loc 1 410 35 is_stmt 0 view .LVU591 + 2038 000c 4361 str r3, [r0, #20] + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; + 2039 .loc 1 411 3 is_stmt 1 view .LVU592 + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; + 2040 .loc 1 411 35 is_stmt 0 view .LVU593 + 2041 000e 8361 str r3, [r0, #24] + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 2042 .loc 1 412 3 is_stmt 1 view .LVU594 + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 2043 .loc 1 412 35 is_stmt 0 view .LVU595 + 2044 0010 C361 str r3, [r0, #28] + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2045 .loc 1 413 1 view .LVU596 + 2046 0012 7047 bx lr + 2047 .cfi_endproc + 2048 .LFE381: + 2050 .section .text.LL_TIM_OC_Init,"ax",%progbits + 2051 .align 1 + 2052 .global LL_TIM_OC_Init + 2053 .syntax unified + 2054 .thumb + 2055 .thumb_func + 2057 LL_TIM_OC_Init: + 2058 .LVL190: + 2059 .LFB382: + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus result = ERROR; + 2060 .loc 1 432 1 is_stmt 1 view -0 + 2061 .cfi_startproc + 2062 @ args = 0, pretend = 0, frame = 0 + 2063 @ frame_needed = 0, uses_anonymous_args = 0 + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus result = ERROR; + 2064 .loc 1 432 1 is_stmt 0 view .LVU598 + 2065 0000 08B5 push {r3, lr} + 2066 .LCFI21: + 2067 .cfi_def_cfa_offset 8 + 2068 .cfi_offset 3, -8 + 2069 .cfi_offset 14, -4 + 2070 0002 0B46 mov r3, r1 + 2071 0004 1146 mov r1, r2 + 2072 .LVL191: + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2073 .loc 1 433 3 is_stmt 1 view .LVU599 + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 2074 .loc 1 435 3 view .LVU600 + 2075 0006 B3F5805F cmp r3, #4096 + ARM GAS /tmp/ccqfGNRw.s page 178 + + + 2076 000a 1DD0 beq .L85 + 2077 000c 0BD8 bhi .L86 + 2078 000e 102B cmp r3, #16 + 2079 0010 14D0 beq .L87 + 2080 0012 B3F5807F cmp r3, #256 + 2081 0016 14D0 beq .L88 + 2082 0018 012B cmp r3, #1 + 2083 001a 02D1 bne .L94 + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2084 .loc 1 438 7 view .LVU601 + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2085 .loc 1 438 16 is_stmt 0 view .LVU602 + 2086 001c FFF7FEFF bl OC1Config + 2087 .LVL192: + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** case LL_TIM_CHANNEL_CH2: + 2088 .loc 1 439 7 is_stmt 1 view .LVU603 + 2089 .L90: + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 2090 .loc 1 459 3 view .LVU604 + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2091 .loc 1 460 1 is_stmt 0 view .LVU605 + 2092 0020 08BD pop {r3, pc} + 2093 .LVL193: + 2094 .L94: + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 2095 .loc 1 435 3 view .LVU606 + 2096 0022 0120 movs r0, #1 + 2097 .LVL194: + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 2098 .loc 1 435 3 view .LVU607 + 2099 0024 FCE7 b .L90 + 2100 .LVL195: + 2101 .L86: + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 2102 .loc 1 435 3 view .LVU608 + 2103 0026 B3F5803F cmp r3, #65536 + 2104 002a 10D0 beq .L91 + 2105 002c B3F5801F cmp r3, #1048576 + 2106 0030 02D1 bne .L95 + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2107 .loc 1 453 7 is_stmt 1 view .LVU609 + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2108 .loc 1 453 16 is_stmt 0 view .LVU610 + 2109 0032 FFF7FEFF bl OC6Config + 2110 .LVL196: + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** default: + 2111 .loc 1 454 7 is_stmt 1 view .LVU611 + 2112 0036 F3E7 b .L90 + 2113 .LVL197: + 2114 .L95: + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 2115 .loc 1 435 3 is_stmt 0 view .LVU612 + 2116 0038 0120 movs r0, #1 + 2117 .LVL198: + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 2118 .loc 1 435 3 view .LVU613 + 2119 003a F1E7 b .L90 + ARM GAS /tmp/ccqfGNRw.s page 179 + + + 2120 .LVL199: + 2121 .L87: + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2122 .loc 1 441 7 is_stmt 1 view .LVU614 + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2123 .loc 1 441 16 is_stmt 0 view .LVU615 + 2124 003c FFF7FEFF bl OC2Config + 2125 .LVL200: + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** case LL_TIM_CHANNEL_CH3: + 2126 .loc 1 442 7 is_stmt 1 view .LVU616 + 2127 0040 EEE7 b .L90 + 2128 .LVL201: + 2129 .L88: + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2130 .loc 1 444 7 view .LVU617 + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2131 .loc 1 444 16 is_stmt 0 view .LVU618 + 2132 0042 FFF7FEFF bl OC3Config + 2133 .LVL202: + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** case LL_TIM_CHANNEL_CH4: + 2134 .loc 1 445 7 is_stmt 1 view .LVU619 + 2135 0046 EBE7 b .L90 + 2136 .LVL203: + 2137 .L85: + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2138 .loc 1 447 7 view .LVU620 + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2139 .loc 1 447 16 is_stmt 0 view .LVU621 + 2140 0048 FFF7FEFF bl OC4Config + 2141 .LVL204: + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** case LL_TIM_CHANNEL_CH5: + 2142 .loc 1 448 7 is_stmt 1 view .LVU622 + 2143 004c E8E7 b .L90 + 2144 .LVL205: + 2145 .L91: + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2146 .loc 1 450 7 view .LVU623 + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2147 .loc 1 450 16 is_stmt 0 view .LVU624 + 2148 004e FFF7FEFF bl OC5Config + 2149 .LVL206: + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** case LL_TIM_CHANNEL_CH6: + 2150 .loc 1 451 7 is_stmt 1 view .LVU625 + 2151 0052 E5E7 b .L90 + 2152 .cfi_endproc + 2153 .LFE382: + 2155 .section .text.LL_TIM_IC_StructInit,"ax",%progbits + 2156 .align 1 + 2157 .global LL_TIM_IC_StructInit + 2158 .syntax unified + 2159 .thumb + 2160 .thumb_func + 2162 LL_TIM_IC_StructInit: + 2163 .LVL207: + 2164 .LFB383: + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the default configuration */ + 2165 .loc 1 470 1 view -0 + ARM GAS /tmp/ccqfGNRw.s page 180 + + + 2166 .cfi_startproc + 2167 @ args = 0, pretend = 0, frame = 0 + 2168 @ frame_needed = 0, uses_anonymous_args = 0 + 2169 @ link register save eliminated. + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + 2170 .loc 1 472 3 view .LVU627 + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + 2171 .loc 1 472 35 is_stmt 0 view .LVU628 + 2172 0000 0023 movs r3, #0 + 2173 0002 0360 str r3, [r0] + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; + 2174 .loc 1 473 3 is_stmt 1 view .LVU629 + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; + 2175 .loc 1 473 35 is_stmt 0 view .LVU630 + 2176 0004 4FF48032 mov r2, #65536 + 2177 0008 4260 str r2, [r0, #4] + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; + 2178 .loc 1 474 3 is_stmt 1 view .LVU631 + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; + 2179 .loc 1 474 35 is_stmt 0 view .LVU632 + 2180 000a 8360 str r3, [r0, #8] + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 2181 .loc 1 475 3 is_stmt 1 view .LVU633 + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 2182 .loc 1 475 35 is_stmt 0 view .LVU634 + 2183 000c C360 str r3, [r0, #12] + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2184 .loc 1 476 1 view .LVU635 + 2185 000e 7047 bx lr + 2186 .cfi_endproc + 2187 .LFE383: + 2189 .section .text.LL_TIM_IC_Init,"ax",%progbits + 2190 .align 1 + 2191 .global LL_TIM_IC_Init + 2192 .syntax unified + 2193 .thumb + 2194 .thumb_func + 2196 LL_TIM_IC_Init: + 2197 .LVL208: + 2198 .LFB384: + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus result = ERROR; + 2199 .loc 1 493 1 is_stmt 1 view -0 + 2200 .cfi_startproc + 2201 @ args = 0, pretend = 0, frame = 0 + 2202 @ frame_needed = 0, uses_anonymous_args = 0 + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** ErrorStatus result = ERROR; + 2203 .loc 1 493 1 is_stmt 0 view .LVU637 + 2204 0000 08B5 push {r3, lr} + 2205 .LCFI22: + 2206 .cfi_def_cfa_offset 8 + 2207 .cfi_offset 3, -8 + 2208 .cfi_offset 14, -4 + 2209 0002 0B46 mov r3, r1 + 2210 0004 1146 mov r1, r2 + 2211 .LVL209: + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2212 .loc 1 494 3 is_stmt 1 view .LVU638 + ARM GAS /tmp/ccqfGNRw.s page 181 + + + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 2213 .loc 1 496 3 view .LVU639 + 2214 0006 B3F5807F cmp r3, #256 + 2215 000a 14D0 beq .L98 + 2216 000c 08D8 bhi .L99 + 2217 000e 012B cmp r3, #1 + 2218 0010 0ED0 beq .L100 + 2219 0012 102B cmp r3, #16 + 2220 0014 02D1 bne .L105 + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2221 .loc 1 502 7 view .LVU640 + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2222 .loc 1 502 16 is_stmt 0 view .LVU641 + 2223 0016 FFF7FEFF bl IC2Config + 2224 .LVL210: + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** case LL_TIM_CHANNEL_CH3: + 2225 .loc 1 503 7 is_stmt 1 view .LVU642 + 2226 001a 0BE0 b .L102 + 2227 .LVL211: + 2228 .L105: + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 2229 .loc 1 496 3 is_stmt 0 view .LVU643 + 2230 001c 0120 movs r0, #1 + 2231 .LVL212: + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 2232 .loc 1 496 3 view .LVU644 + 2233 001e 09E0 b .L102 + 2234 .LVL213: + 2235 .L99: + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 2236 .loc 1 496 3 view .LVU645 + 2237 0020 B3F5805F cmp r3, #4096 + 2238 0024 02D1 bne .L106 + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2239 .loc 1 508 7 is_stmt 1 view .LVU646 + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2240 .loc 1 508 16 is_stmt 0 view .LVU647 + 2241 0026 FFF7FEFF bl IC4Config + 2242 .LVL214: + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** default: + 2243 .loc 1 509 7 is_stmt 1 view .LVU648 + 2244 002a 03E0 b .L102 + 2245 .LVL215: + 2246 .L106: + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 2247 .loc 1 496 3 is_stmt 0 view .LVU649 + 2248 002c 0120 movs r0, #1 + 2249 .LVL216: + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 2250 .loc 1 496 3 view .LVU650 + 2251 002e 01E0 b .L102 + 2252 .LVL217: + 2253 .L100: + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2254 .loc 1 499 7 is_stmt 1 view .LVU651 + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2255 .loc 1 499 16 is_stmt 0 view .LVU652 + ARM GAS /tmp/ccqfGNRw.s page 182 + + + 2256 0030 FFF7FEFF bl IC1Config + 2257 .LVL218: + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** case LL_TIM_CHANNEL_CH2: + 2258 .loc 1 500 7 is_stmt 1 view .LVU653 + 2259 .L102: + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 2260 .loc 1 514 3 view .LVU654 + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2261 .loc 1 515 1 is_stmt 0 view .LVU655 + 2262 0034 08BD pop {r3, pc} + 2263 .LVL219: + 2264 .L98: + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2265 .loc 1 505 7 is_stmt 1 view .LVU656 + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** break; + 2266 .loc 1 505 16 is_stmt 0 view .LVU657 + 2267 0036 FFF7FEFF bl IC3Config + 2268 .LVL220: + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** case LL_TIM_CHANNEL_CH4: + 2269 .loc 1 506 7 is_stmt 1 view .LVU658 + 2270 003a FBE7 b .L102 + 2271 .cfi_endproc + 2272 .LFE384: + 2274 .section .text.LL_TIM_ENCODER_StructInit,"ax",%progbits + 2275 .align 1 + 2276 .global LL_TIM_ENCODER_StructInit + 2277 .syntax unified + 2278 .thumb + 2279 .thumb_func + 2281 LL_TIM_ENCODER_StructInit: + 2282 .LVL221: + 2283 .LFB385: + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the default configuration */ + 2284 .loc 1 524 1 view -0 + 2285 .cfi_startproc + 2286 @ args = 0, pretend = 0, frame = 0 + 2287 @ frame_needed = 0, uses_anonymous_args = 0 + 2288 @ link register save eliminated. + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + 2289 .loc 1 526 3 view .LVU660 + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + 2290 .loc 1 526 41 is_stmt 0 view .LVU661 + 2291 0000 0123 movs r3, #1 + 2292 0002 0360 str r3, [r0] + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + 2293 .loc 1 527 3 is_stmt 1 view .LVU662 + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + 2294 .loc 1 527 41 is_stmt 0 view .LVU663 + 2295 0004 0023 movs r3, #0 + 2296 0006 4360 str r3, [r0, #4] + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + 2297 .loc 1 528 3 is_stmt 1 view .LVU664 + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + 2298 .loc 1 528 41 is_stmt 0 view .LVU665 + 2299 0008 4FF48032 mov r2, #65536 + 2300 000c 8260 str r2, [r0, #8] + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + ARM GAS /tmp/ccqfGNRw.s page 183 + + + 2301 .loc 1 529 3 is_stmt 1 view .LVU666 + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + 2302 .loc 1 529 41 is_stmt 0 view .LVU667 + 2303 000e C360 str r3, [r0, #12] + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; + 2304 .loc 1 530 3 is_stmt 1 view .LVU668 + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; + 2305 .loc 1 530 41 is_stmt 0 view .LVU669 + 2306 0010 0361 str r3, [r0, #16] + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + 2307 .loc 1 531 3 is_stmt 1 view .LVU670 + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + 2308 .loc 1 531 41 is_stmt 0 view .LVU671 + 2309 0012 4361 str r3, [r0, #20] + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; + 2310 .loc 1 532 3 is_stmt 1 view .LVU672 + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; + 2311 .loc 1 532 41 is_stmt 0 view .LVU673 + 2312 0014 8261 str r2, [r0, #24] + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; + 2313 .loc 1 533 3 is_stmt 1 view .LVU674 + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; + 2314 .loc 1 533 41 is_stmt 0 view .LVU675 + 2315 0016 C361 str r3, [r0, #28] + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 2316 .loc 1 534 3 is_stmt 1 view .LVU676 + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 2317 .loc 1 534 41 is_stmt 0 view .LVU677 + 2318 0018 0362 str r3, [r0, #32] + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2319 .loc 1 535 1 view .LVU678 + 2320 001a 7047 bx lr + 2321 .cfi_endproc + 2322 .LFE385: + 2324 .section .text.LL_TIM_ENCODER_Init,"ax",%progbits + 2325 .align 1 + 2326 .global LL_TIM_ENCODER_Init + 2327 .syntax unified + 2328 .thumb + 2329 .thumb_func + 2331 LL_TIM_ENCODER_Init: + 2332 .LVL222: + 2333 .LFB386: + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccmr1; + 2334 .loc 1 547 1 is_stmt 1 view -0 + 2335 .cfi_startproc + 2336 @ args = 0, pretend = 0, frame = 0 + 2337 @ frame_needed = 0, uses_anonymous_args = 0 + 2338 @ link register save eliminated. + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccmr1; + 2339 .loc 1 547 1 is_stmt 0 view .LVU680 + 2340 0000 30B4 push {r4, r5} + 2341 .LCFI23: + 2342 .cfi_def_cfa_offset 8 + 2343 .cfi_offset 4, -8 + 2344 .cfi_offset 5, -4 + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccer; + ARM GAS /tmp/ccqfGNRw.s page 184 + + + 2345 .loc 1 548 3 is_stmt 1 view .LVU681 + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2346 .loc 1 549 3 view .LVU682 + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); + 2347 .loc 1 552 3 view .LVU683 + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); + 2348 .loc 1 553 3 view .LVU684 + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); + 2349 .loc 1 554 3 view .LVU685 + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); + 2350 .loc 1 555 3 view .LVU686 + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); + 2351 .loc 1 556 3 view .LVU687 + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); + 2352 .loc 1 557 3 view .LVU688 + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); + 2353 .loc 1 558 3 view .LVU689 + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); + 2354 .loc 1 559 3 view .LVU690 + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); + 2355 .loc 1 560 3 view .LVU691 + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2356 .loc 1 561 3 view .LVU692 + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2357 .loc 1 564 3 view .LVU693 + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2358 .loc 1 564 7 is_stmt 0 view .LVU694 + 2359 0002 036A ldr r3, [r0, #32] + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2360 .loc 1 564 14 view .LVU695 + 2361 0004 23F01103 bic r3, r3, #17 + 2362 0008 0362 str r3, [r0, #32] + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2363 .loc 1 567 3 is_stmt 1 view .LVU696 + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2364 .loc 1 567 12 is_stmt 0 view .LVU697 + 2365 000a 8269 ldr r2, [r0, #24] + 2366 .LVL223: + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2367 .loc 1 570 3 is_stmt 1 view .LVU698 + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2368 .loc 1 570 11 is_stmt 0 view .LVU699 + 2369 000c 046A ldr r4, [r0, #32] + 2370 .LVL224: + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); + 2371 .loc 1 573 3 is_stmt 1 view .LVU700 + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); + 2372 .loc 1 573 12 is_stmt 0 view .LVU701 + 2373 000e 22F0FF02 bic r2, r2, #255 + 2374 .LVL225: + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); + 2375 .loc 1 574 3 is_stmt 1 view .LVU702 + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); + 2376 .loc 1 574 64 is_stmt 0 view .LVU703 + 2377 0012 4B89 ldrh r3, [r1, #10] + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); + 2378 .loc 1 574 12 view .LVU704 + ARM GAS /tmp/ccqfGNRw.s page 185 + + + 2379 0014 1343 orrs r3, r3, r2 + 2380 .LVL226: + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); + 2381 .loc 1 575 3 is_stmt 1 view .LVU705 + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); + 2382 .loc 1 575 59 is_stmt 0 view .LVU706 + 2383 0016 4A8A ldrh r2, [r1, #18] + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); + 2384 .loc 1 575 12 view .LVU707 + 2385 0018 1A43 orrs r2, r2, r3 + 2386 .LVL227: + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2387 .loc 1 576 3 is_stmt 1 view .LVU708 + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2388 .loc 1 576 62 is_stmt 0 view .LVU709 + 2389 001a CB89 ldrh r3, [r1, #14] + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2390 .loc 1 576 12 view .LVU710 + 2391 001c 1343 orrs r3, r3, r2 + 2392 .LVL228: + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); + 2393 .loc 1 579 3 is_stmt 1 view .LVU711 + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); + 2394 .loc 1 579 12 is_stmt 0 view .LVU712 + 2395 001e 23F47F43 bic r3, r3, #65280 + 2396 .LVL229: + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); + 2397 .loc 1 580 3 is_stmt 1 view .LVU713 + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); + 2398 .loc 1 580 47 is_stmt 0 view .LVU714 + 2399 0022 8A69 ldr r2, [r1, #24] + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); + 2400 .loc 1 580 12 view .LVU715 + 2401 0024 43EA1223 orr r3, r3, r2, lsr #8 + 2402 .LVL230: + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); + 2403 .loc 1 581 3 is_stmt 1 view .LVU716 + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); + 2404 .loc 1 581 47 is_stmt 0 view .LVU717 + 2405 0028 0A6A ldr r2, [r1, #32] + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); + 2406 .loc 1 581 12 view .LVU718 + 2407 002a 43EA1223 orr r3, r3, r2, lsr #8 + 2408 .LVL231: + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2409 .loc 1 582 3 is_stmt 1 view .LVU719 + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2410 .loc 1 582 47 is_stmt 0 view .LVU720 + 2411 002e CA69 ldr r2, [r1, #28] + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2412 .loc 1 582 12 view .LVU721 + 2413 0030 43EA1223 orr r3, r3, r2, lsr #8 + 2414 .LVL232: + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); + 2415 .loc 1 585 3 is_stmt 1 view .LVU722 + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); + 2416 .loc 1 585 11 is_stmt 0 view .LVU723 + ARM GAS /tmp/ccqfGNRw.s page 186 + + + 2417 0034 24F0AA04 bic r4, r4, #170 + 2418 .LVL233: + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); + 2419 .loc 1 586 3 is_stmt 1 view .LVU724 + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); + 2420 .loc 1 586 46 is_stmt 0 view .LVU725 + 2421 0038 4A68 ldr r2, [r1, #4] + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); + 2422 .loc 1 586 11 view .LVU726 + 2423 003a 2243 orrs r2, r2, r4 + 2424 .LVL234: + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + 2425 .loc 1 587 3 is_stmt 1 view .LVU727 + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + 2426 .loc 1 587 46 is_stmt 0 view .LVU728 + 2427 003c 4C69 ldr r4, [r1, #20] + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + 2428 .loc 1 587 11 view .LVU729 + 2429 003e 42EA0412 orr r2, r2, r4, lsl #4 + 2430 .LVL235: + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2431 .loc 1 588 3 is_stmt 1 view .LVU730 + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2432 .loc 1 588 11 is_stmt 0 view .LVU731 + 2433 0042 42F01102 orr r2, r2, #17 + 2434 .LVL236: + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2435 .loc 1 591 3 is_stmt 1 view .LVU732 + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2436 .loc 1 591 52 is_stmt 0 view .LVU733 + 2437 0046 0968 ldr r1, [r1] + 2438 .LVL237: + 2439 .LBB186: + 2440 .LBI186: +3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 2441 .loc 2 3109 22 is_stmt 1 view .LVU734 + 2442 .LBB187: +3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 2443 .loc 2 3111 3 view .LVU735 + 2444 0048 8568 ldr r5, [r0, #8] + 2445 004a 044C ldr r4, .L110 + 2446 004c 2C40 ands r4, r4, r5 + 2447 004e 2143 orrs r1, r1, r4 + 2448 .LVL238: +3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 2449 .loc 2 3111 3 is_stmt 0 view .LVU736 + 2450 0050 8160 str r1, [r0, #8] + 2451 .LVL239: +3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 2452 .loc 2 3111 3 view .LVU737 + 2453 .LBE187: + 2454 .LBE186: + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2455 .loc 1 594 3 is_stmt 1 view .LVU738 + 2456 0052 8361 str r3, [r0, #24] + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2457 .loc 1 597 3 view .LVU739 + ARM GAS /tmp/ccqfGNRw.s page 187 + + + 2458 0054 0262 str r2, [r0, #32] + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 2459 .loc 1 599 3 view .LVU740 + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2460 .loc 1 600 1 is_stmt 0 view .LVU741 + 2461 0056 0020 movs r0, #0 + 2462 .LVL240: + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2463 .loc 1 600 1 view .LVU742 + 2464 0058 30BC pop {r4, r5} + 2465 .LCFI24: + 2466 .cfi_restore 5 + 2467 .cfi_restore 4 + 2468 .cfi_def_cfa_offset 0 + 2469 005a 7047 bx lr + 2470 .L111: + 2471 .align 2 + 2472 .L110: + 2473 005c F8FFFEFF .word -65544 + 2474 .cfi_endproc + 2475 .LFE386: + 2477 .section .text.LL_TIM_HALLSENSOR_StructInit,"ax",%progbits + 2478 .align 1 + 2479 .global LL_TIM_HALLSENSOR_StructInit + 2480 .syntax unified + 2481 .thumb + 2482 .thumb_func + 2484 LL_TIM_HALLSENSOR_StructInit: + 2485 .LVL241: + 2486 .LFB387: + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the default configuration */ + 2487 .loc 1 610 1 is_stmt 1 view -0 + 2488 .cfi_startproc + 2489 @ args = 0, pretend = 0, frame = 0 + 2490 @ frame_needed = 0, uses_anonymous_args = 0 + 2491 @ link register save eliminated. + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + 2492 .loc 1 612 3 view .LVU744 + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + 2493 .loc 1 612 47 is_stmt 0 view .LVU745 + 2494 0000 0023 movs r3, #0 + 2495 0002 0360 str r3, [r0] + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + 2496 .loc 1 613 3 is_stmt 1 view .LVU746 + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + 2497 .loc 1 613 47 is_stmt 0 view .LVU747 + 2498 0004 4360 str r3, [r0, #4] + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_HallSensorInitStruct->CommutationDelay = 0U; + 2499 .loc 1 614 3 is_stmt 1 view .LVU748 + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_HallSensorInitStruct->CommutationDelay = 0U; + 2500 .loc 1 614 47 is_stmt 0 view .LVU749 + 2501 0006 8360 str r3, [r0, #8] + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 2502 .loc 1 615 3 is_stmt 1 view .LVU750 + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 2503 .loc 1 615 47 is_stmt 0 view .LVU751 + 2504 0008 C360 str r3, [r0, #12] + ARM GAS /tmp/ccqfGNRw.s page 188 + + + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2505 .loc 1 616 1 view .LVU752 + 2506 000a 7047 bx lr + 2507 .cfi_endproc + 2508 .LFE387: + 2510 .section .text.LL_TIM_HALLSENSOR_Init,"ax",%progbits + 2511 .align 1 + 2512 .global LL_TIM_HALLSENSOR_Init + 2513 .syntax unified + 2514 .thumb + 2515 .thumb_func + 2517 LL_TIM_HALLSENSOR_Init: + 2518 .LVL242: + 2519 .LFB388: + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpcr2; + 2520 .loc 1 640 1 is_stmt 1 view -0 + 2521 .cfi_startproc + 2522 @ args = 0, pretend = 0, frame = 0 + 2523 @ frame_needed = 0, uses_anonymous_args = 0 + 2524 @ link register save eliminated. + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpcr2; + 2525 .loc 1 640 1 is_stmt 0 view .LVU754 + 2526 0000 70B4 push {r4, r5, r6} + 2527 .LCFI25: + 2528 .cfi_def_cfa_offset 12 + 2529 .cfi_offset 4, -12 + 2530 .cfi_offset 5, -8 + 2531 .cfi_offset 6, -4 + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccmr1; + 2532 .loc 1 641 3 is_stmt 1 view .LVU755 + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpccer; + 2533 .loc 1 642 3 view .LVU756 + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpsmcr; + 2534 .loc 1 643 3 view .LVU757 + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2535 .loc 1 644 3 view .LVU758 + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity)); + 2536 .loc 1 647 3 view .LVU759 + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler)); + 2537 .loc 1 648 3 view .LVU760 + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter)); + 2538 .loc 1 649 3 view .LVU761 + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2539 .loc 1 650 3 view .LVU762 + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2540 .loc 1 653 3 view .LVU763 + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2541 .loc 1 653 7 is_stmt 0 view .LVU764 + 2542 0002 036A ldr r3, [r0, #32] + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2543 .loc 1 653 14 view .LVU765 + 2544 0004 23F01103 bic r3, r3, #17 + 2545 0008 0362 str r3, [r0, #32] + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2546 .loc 1 656 3 is_stmt 1 view .LVU766 + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2547 .loc 1 656 10 is_stmt 0 view .LVU767 + ARM GAS /tmp/ccqfGNRw.s page 189 + + + 2548 000a 4568 ldr r5, [r0, #4] + 2549 .LVL243: + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2550 .loc 1 659 3 is_stmt 1 view .LVU768 + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2551 .loc 1 659 12 is_stmt 0 view .LVU769 + 2552 000c 8369 ldr r3, [r0, #24] + 2553 .LVL244: + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2554 .loc 1 662 3 is_stmt 1 view .LVU770 + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2555 .loc 1 662 11 is_stmt 0 view .LVU771 + 2556 000e 066A ldr r6, [r0, #32] + 2557 .LVL245: + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2558 .loc 1 665 3 is_stmt 1 view .LVU772 + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2559 .loc 1 665 11 is_stmt 0 view .LVU773 + 2560 0010 8268 ldr r2, [r0, #8] + 2561 .LVL246: + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2562 .loc 1 668 3 is_stmt 1 view .LVU774 + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2563 .loc 1 671 3 view .LVU775 + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2564 .loc 1 671 10 is_stmt 0 view .LVU776 + 2565 0012 45F0D005 orr r5, r5, #208 + 2566 .LVL247: + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpsmcr |= LL_TIM_TS_TI1F_ED; + 2567 .loc 1 674 3 is_stmt 1 view .LVU777 + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpsmcr |= LL_TIM_TS_TI1F_ED; + 2568 .loc 1 674 11 is_stmt 0 view .LVU778 + 2569 0016 104C ldr r4, .L115 + 2570 0018 1440 ands r4, r4, r2 + 2571 .LVL248: + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpsmcr |= LL_TIM_SLAVEMODE_RESET; + 2572 .loc 1 675 3 is_stmt 1 view .LVU779 + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2573 .loc 1 676 3 view .LVU780 + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2574 .loc 1 676 11 is_stmt 0 view .LVU781 + 2575 001a 44F04404 orr r4, r4, #68 + 2576 .LVL249: + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U); + 2577 .loc 1 679 3 is_stmt 1 view .LVU782 + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U); + 2578 .loc 1 679 12 is_stmt 0 view .LVU783 + 2579 001e 23F0FF03 bic r3, r3, #255 + 2580 .LVL250: + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U); + 2581 .loc 1 680 3 is_stmt 1 view .LVU784 + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U); + 2582 .loc 1 680 12 is_stmt 0 view .LVU785 + 2583 0022 43F00303 orr r3, r3, #3 + 2584 .LVL251: + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); + 2585 .loc 1 681 3 is_stmt 1 view .LVU786 + ARM GAS /tmp/ccqfGNRw.s page 190 + + + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); + 2586 .loc 1 681 62 is_stmt 0 view .LVU787 + 2587 0026 4A89 ldrh r2, [r1, #10] + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); + 2588 .loc 1 681 12 view .LVU788 + 2589 0028 1343 orrs r3, r3, r2 + 2590 .LVL252: + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2591 .loc 1 682 3 is_stmt 1 view .LVU789 + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2592 .loc 1 682 65 is_stmt 0 view .LVU790 + 2593 002a CA88 ldrh r2, [r1, #6] + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2594 .loc 1 682 12 view .LVU791 + 2595 002c 1A43 orrs r2, r2, r3 + 2596 .LVL253: + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U); + 2597 .loc 1 685 3 is_stmt 1 view .LVU792 + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U); + 2598 .loc 1 685 12 is_stmt 0 view .LVU793 + 2599 002e 0B4B ldr r3, .L115+4 + 2600 0030 1340 ands r3, r3, r2 + 2601 .LVL254: + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2602 .loc 1 686 3 is_stmt 1 view .LVU794 + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2603 .loc 1 686 12 is_stmt 0 view .LVU795 + 2604 0032 43F4E042 orr r2, r3, #28672 + 2605 .LVL255: + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); + 2606 .loc 1 689 3 is_stmt 1 view .LVU796 + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); + 2607 .loc 1 689 11 is_stmt 0 view .LVU797 + 2608 0036 26F0AA0C bic ip, r6, #170 + 2609 .LVL256: + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + 2610 .loc 1 690 3 is_stmt 1 view .LVU798 + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + 2611 .loc 1 690 49 is_stmt 0 view .LVU799 + 2612 003a 0B68 ldr r3, [r1] + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + 2613 .loc 1 690 11 view .LVU800 + 2614 003c 43EA0C03 orr r3, r3, ip + 2615 .LVL257: + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2616 .loc 1 691 3 is_stmt 1 view .LVU801 + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2617 .loc 1 691 11 is_stmt 0 view .LVU802 + 2618 0040 43F01103 orr r3, r3, #17 + 2619 .LVL258: + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2620 .loc 1 694 3 is_stmt 1 view .LVU803 + 2621 0044 4560 str r5, [r0, #4] + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2622 .loc 1 697 3 view .LVU804 + 2623 0046 8460 str r4, [r0, #8] + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + ARM GAS /tmp/ccqfGNRw.s page 191 + + + 2624 .loc 1 700 3 view .LVU805 + 2625 0048 8261 str r2, [r0, #24] + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2626 .loc 1 703 3 view .LVU806 + 2627 004a 0362 str r3, [r0, #32] + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2628 .loc 1 706 3 view .LVU807 + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2629 .loc 1 706 57 is_stmt 0 view .LVU808 + 2630 004c CB68 ldr r3, [r1, #12] + 2631 .LVL259: + 2632 .LBB188: + 2633 .LBI188: +2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** { + 2634 .loc 2 2461 22 is_stmt 1 view .LVU809 + 2635 .LBB189: +2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 2636 .loc 2 2463 3 view .LVU810 + 2637 004e 8363 str r3, [r0, #56] + 2638 .LVL260: +2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h **** } + 2639 .loc 2 2463 3 is_stmt 0 view .LVU811 + 2640 .LBE189: + 2641 .LBE188: + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 2642 .loc 1 708 3 is_stmt 1 view .LVU812 + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2643 .loc 1 709 1 is_stmt 0 view .LVU813 + 2644 0050 0020 movs r0, #0 + 2645 .LVL261: + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2646 .loc 1 709 1 view .LVU814 + 2647 0052 70BC pop {r4, r5, r6} + 2648 .LCFI26: + 2649 .cfi_restore 6 + 2650 .cfi_restore 5 + 2651 .cfi_restore 4 + 2652 .cfi_def_cfa_offset 0 + 2653 .LVL262: + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2654 .loc 1 709 1 view .LVU815 + 2655 0054 7047 bx lr + 2656 .L116: + 2657 0056 00BF .align 2 + 2658 .L115: + 2659 0058 88FFFEFF .word -65656 + 2660 005c FF03FFFE .word -16841729 + 2661 .cfi_endproc + 2662 .LFE388: + 2664 .section .text.LL_TIM_BDTR_StructInit,"ax",%progbits + 2665 .align 1 + 2666 .global LL_TIM_BDTR_StructInit + 2667 .syntax unified + 2668 .thumb + 2669 .thumb_func + 2671 LL_TIM_BDTR_StructInit: + 2672 .LVL263: + ARM GAS /tmp/ccqfGNRw.s page 192 + + + 2673 .LFB389: + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /* Set the default configuration */ + 2674 .loc 1 719 1 is_stmt 1 view -0 + 2675 .cfi_startproc + 2676 @ args = 0, pretend = 0, frame = 0 + 2677 @ frame_needed = 0, uses_anonymous_args = 0 + 2678 @ link register save eliminated. + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; + 2679 .loc 1 721 3 view .LVU817 + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; + 2680 .loc 1 721 39 is_stmt 0 view .LVU818 + 2681 0000 0023 movs r3, #0 + 2682 0002 0360 str r3, [r0] + 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; + 2683 .loc 1 722 3 is_stmt 1 view .LVU819 + 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; + 2684 .loc 1 722 39 is_stmt 0 view .LVU820 + 2685 0004 4360 str r3, [r0, #4] + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00; + 2686 .loc 1 723 3 is_stmt 1 view .LVU821 + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00; + 2687 .loc 1 723 39 is_stmt 0 view .LVU822 + 2688 0006 8360 str r3, [r0, #8] + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; + 2689 .loc 1 724 3 is_stmt 1 view .LVU823 + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; + 2690 .loc 1 724 39 is_stmt 0 view .LVU824 + 2691 0008 0373 strb r3, [r0, #12] + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; + 2692 .loc 1 725 3 is_stmt 1 view .LVU825 + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; + 2693 .loc 1 725 39 is_stmt 0 view .LVU826 + 2694 000a C381 strh r3, [r0, #14] @ movhi + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1; + 2695 .loc 1 726 3 is_stmt 1 view .LVU827 + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1; + 2696 .loc 1 726 39 is_stmt 0 view .LVU828 + 2697 000c 0361 str r3, [r0, #16] + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE; + 2698 .loc 1 727 3 is_stmt 1 view .LVU829 + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE; + 2699 .loc 1 727 39 is_stmt 0 view .LVU830 + 2700 000e 4361 str r3, [r0, #20] + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW; + 2701 .loc 1 728 3 is_stmt 1 view .LVU831 + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW; + 2702 .loc 1 728 39 is_stmt 0 view .LVU832 + 2703 0010 8361 str r3, [r0, #24] + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1; + 2704 .loc 1 729 3 is_stmt 1 view .LVU833 + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1; + 2705 .loc 1 729 39 is_stmt 0 view .LVU834 + 2706 0012 C361 str r3, [r0, #28] + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; + 2707 .loc 1 730 3 is_stmt 1 view .LVU835 + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; + 2708 .loc 1 730 39 is_stmt 0 view .LVU836 + ARM GAS /tmp/ccqfGNRw.s page 193 + + + 2709 0014 0362 str r3, [r0, #32] + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 2710 .loc 1 731 3 is_stmt 1 view .LVU837 + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 2711 .loc 1 731 39 is_stmt 0 view .LVU838 + 2712 0016 4362 str r3, [r0, #36] + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2713 .loc 1 732 1 view .LVU839 + 2714 0018 7047 bx lr + 2715 .cfi_endproc + 2716 .LFE389: + 2718 .section .text.LL_TIM_BDTR_Init,"ax",%progbits + 2719 .align 1 + 2720 .global LL_TIM_BDTR_Init + 2721 .syntax unified + 2722 .thumb + 2723 .thumb_func + 2725 LL_TIM_BDTR_Init: + 2726 .LVL264: + 2727 .LFB390: + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpbdtr = 0; + 2728 .loc 1 752 1 is_stmt 1 view -0 + 2729 .cfi_startproc + 2730 @ args = 0, pretend = 0, frame = 0 + 2731 @ frame_needed = 0, uses_anonymous_args = 0 + 2732 @ link register save eliminated. + 752:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** uint32_t tmpbdtr = 0; + 2733 .loc 1 752 1 is_stmt 0 view .LVU841 + 2734 0000 10B4 push {r4} + 2735 .LCFI27: + 2736 .cfi_def_cfa_offset 4 + 2737 .cfi_offset 4, -4 + 753:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2738 .loc 1 753 3 is_stmt 1 view .LVU842 + 2739 .LVL265: + 756:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); + 2740 .loc 1 756 3 view .LVU843 + 757:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState)); + 2741 .loc 1 757 3 view .LVU844 + 758:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel)); + 2742 .loc 1 758 3 view .LVU845 + 759:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); + 2743 .loc 1 759 3 view .LVU846 + 760:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); + 2744 .loc 1 760 3 view .LVU847 + 761:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + 2745 .loc 1 761 3 view .LVU848 + 762:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + 2746 .loc 1 762 3 view .LVU849 + 763:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2747 .loc 1 763 3 view .LVU850 + 769:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); + 2748 .loc 1 769 3 view .LVU851 + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); + 2749 .loc 1 770 3 view .LVU852 + 2750 0002 0B7B ldrb r3, [r1, #12] @ zero_extendqisi2 + 2751 .LVL266: + ARM GAS /tmp/ccqfGNRw.s page 194 + + + 770:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); + 2752 .loc 1 770 3 is_stmt 0 view .LVU853 + 2753 0004 8A68 ldr r2, [r1, #8] + 2754 0006 1343 orrs r3, r3, r2 + 2755 .LVL267: + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); + 2756 .loc 1 771 3 is_stmt 1 view .LVU854 + 2757 0008 23F48063 bic r3, r3, #1024 + 2758 .LVL268: + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); + 2759 .loc 1 771 3 is_stmt 0 view .LVU855 + 2760 000c 4A68 ldr r2, [r1, #4] + 2761 .LVL269: + 771:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); + 2762 .loc 1 771 3 view .LVU856 + 2763 000e 1343 orrs r3, r3, r2 + 2764 .LVL270: + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); + 2765 .loc 1 772 3 is_stmt 1 view .LVU857 + 2766 0010 23F40063 bic r3, r3, #2048 + 2767 .LVL271: + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); + 2768 .loc 1 772 3 is_stmt 0 view .LVU858 + 2769 0014 0A68 ldr r2, [r1] + 2770 .LVL272: + 772:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); + 2771 .loc 1 772 3 view .LVU859 + 2772 0016 1343 orrs r3, r3, r2 + 2773 .LVL273: + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); + 2774 .loc 1 773 3 is_stmt 1 view .LVU860 + 2775 0018 23F48053 bic r3, r3, #4096 + 2776 .LVL274: + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); + 2777 .loc 1 773 3 is_stmt 0 view .LVU861 + 2778 001c CA89 ldrh r2, [r1, #14] + 2779 .LVL275: + 773:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); + 2780 .loc 1 773 3 view .LVU862 + 2781 001e 1343 orrs r3, r3, r2 + 2782 .LVL276: + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); + 2783 .loc 1 774 3 is_stmt 1 view .LVU863 + 2784 0020 23F40053 bic r3, r3, #8192 + 2785 .LVL277: + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); + 2786 .loc 1 774 3 is_stmt 0 view .LVU864 + 2787 0024 0A69 ldr r2, [r1, #16] + 2788 .LVL278: + 774:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); + 2789 .loc 1 774 3 view .LVU865 + 2790 0026 1343 orrs r3, r3, r2 + 2791 .LVL279: + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); + 2792 .loc 1 775 3 is_stmt 1 view .LVU866 + 2793 0028 23F48043 bic r3, r3, #16384 + 2794 .LVL280: + ARM GAS /tmp/ccqfGNRw.s page 195 + + + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); + 2795 .loc 1 775 3 is_stmt 0 view .LVU867 + 2796 002c 4A6A ldr r2, [r1, #36] + 2797 .LVL281: + 775:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); + 2798 .loc 1 775 3 view .LVU868 + 2799 002e 1343 orrs r3, r3, r2 + 2800 .LVL282: + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2801 .loc 1 776 3 is_stmt 1 view .LVU869 + 2802 0030 23F47023 bic r3, r3, #983040 + 2803 .LVL283: + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2804 .loc 1 776 3 is_stmt 0 view .LVU870 + 2805 0034 4A69 ldr r2, [r1, #20] + 2806 .LVL284: + 776:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2807 .loc 1 776 3 view .LVU871 + 2808 0036 1343 orrs r3, r3, r2 + 2809 .LVL285: + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 2810 .loc 1 778 3 is_stmt 1 view .LVU872 + 778:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** { + 2811 .loc 1 778 6 is_stmt 0 view .LVU873 + 2812 0038 0B4C ldr r4, .L121 + 2813 003a 0C4A ldr r2, .L121+4 + 2814 003c 9042 cmp r0, r2 + 2815 003e 18BF it ne + 2816 0040 A042 cmpne r0, r4 + 2817 0042 0BD1 bne .L119 + 780:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity)); + 2818 .loc 1 780 5 is_stmt 1 view .LVU874 + 781:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter)); + 2819 .loc 1 781 5 view .LVU875 + 782:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2820 .loc 1 782 5 view .LVU876 + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State); + 2821 .loc 1 785 5 view .LVU877 + 2822 0044 23F47003 bic r3, r3, #15728640 + 2823 .LVL286: + 785:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State); + 2824 .loc 1 785 5 is_stmt 0 view .LVU878 + 2825 0048 0A6A ldr r2, [r1, #32] + 2826 004a 1343 orrs r3, r3, r2 + 2827 .LVL287: + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity); + 2828 .loc 1 786 5 is_stmt 1 view .LVU879 + 2829 004c 23F08073 bic r3, r3, #16777216 + 2830 .LVL288: + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity); + 2831 .loc 1 786 5 is_stmt 0 view .LVU880 + 2832 0050 8A69 ldr r2, [r1, #24] + 2833 .LVL289: + 786:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity); + 2834 .loc 1 786 5 view .LVU881 + 2835 0052 1343 orrs r3, r3, r2 + 2836 .LVL290: + ARM GAS /tmp/ccqfGNRw.s page 196 + + + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 2837 .loc 1 787 5 is_stmt 1 view .LVU882 + 2838 0054 23F00073 bic r3, r3, #33554432 + 2839 .LVL291: + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 2840 .loc 1 787 5 is_stmt 0 view .LVU883 + 2841 0058 CA69 ldr r2, [r1, #28] + 2842 .LVL292: + 787:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 2843 .loc 1 787 5 view .LVU884 + 2844 005a 1343 orrs r3, r3, r2 + 2845 .LVL293: + 2846 .L119: + 791:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** + 2847 .loc 1 791 3 is_stmt 1 view .LVU885 + 2848 005c 4364 str r3, [r0, #68] + 793:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** } + 2849 .loc 1 793 3 view .LVU886 + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 2850 .loc 1 794 1 is_stmt 0 view .LVU887 + 2851 005e 0020 movs r0, #0 + 2852 .LVL294: + 794:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c **** /** + 2853 .loc 1 794 1 view .LVU888 + 2854 0060 5DF8044B ldr r4, [sp], #4 + 2855 .LCFI28: + 2856 .cfi_restore 4 + 2857 .cfi_def_cfa_offset 0 + 2858 0064 7047 bx lr + 2859 .L122: + 2860 0066 00BF .align 2 + 2861 .L121: + 2862 0068 00000140 .word 1073807360 + 2863 006c 00040140 .word 1073808384 + 2864 .cfi_endproc + 2865 .LFE390: + 2867 .text + 2868 .Letext0: + 2869 .file 4 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 2870 .file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 2871 .file 6 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + ARM GAS /tmp/ccqfGNRw.s page 197 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_ll_tim.c + /tmp/ccqfGNRw.s:20 .text.OC1Config:00000000 $t + /tmp/ccqfGNRw.s:25 .text.OC1Config:00000000 OC1Config + /tmp/ccqfGNRw.s:166 .text.OC1Config:0000006c $d + /tmp/ccqfGNRw.s:173 .text.OC2Config:00000000 $t + /tmp/ccqfGNRw.s:178 .text.OC2Config:00000000 OC2Config + /tmp/ccqfGNRw.s:320 .text.OC2Config:00000074 $d + /tmp/ccqfGNRw.s:327 .text.OC3Config:00000000 $t + /tmp/ccqfGNRw.s:332 .text.OC3Config:00000000 OC3Config + /tmp/ccqfGNRw.s:474 .text.OC3Config:00000070 $d + /tmp/ccqfGNRw.s:481 .text.OC4Config:00000000 $t + /tmp/ccqfGNRw.s:486 .text.OC4Config:00000000 OC4Config + /tmp/ccqfGNRw.s:602 .text.OC4Config:00000054 $d + /tmp/ccqfGNRw.s:609 .text.OC5Config:00000000 $t + /tmp/ccqfGNRw.s:614 .text.OC5Config:00000000 OC5Config + /tmp/ccqfGNRw.s:723 .text.OC5Config:00000054 $d + /tmp/ccqfGNRw.s:730 .text.OC6Config:00000000 $t + /tmp/ccqfGNRw.s:735 .text.OC6Config:00000000 OC6Config + /tmp/ccqfGNRw.s:841 .text.OC6Config:00000054 $d + /tmp/ccqfGNRw.s:848 .text.IC1Config:00000000 $t + /tmp/ccqfGNRw.s:853 .text.IC1Config:00000000 IC1Config + /tmp/ccqfGNRw.s:908 .text.IC2Config:00000000 $t + /tmp/ccqfGNRw.s:913 .text.IC2Config:00000000 IC2Config + /tmp/ccqfGNRw.s:968 .text.IC3Config:00000000 $t + /tmp/ccqfGNRw.s:973 .text.IC3Config:00000000 IC3Config + /tmp/ccqfGNRw.s:1028 .text.IC4Config:00000000 $t + /tmp/ccqfGNRw.s:1033 .text.IC4Config:00000000 IC4Config + /tmp/ccqfGNRw.s:1088 .text.LL_TIM_DeInit:00000000 $t + /tmp/ccqfGNRw.s:1094 .text.LL_TIM_DeInit:00000000 LL_TIM_DeInit + /tmp/ccqfGNRw.s:1726 .text.LL_TIM_DeInit:000001b0 $d + /tmp/ccqfGNRw.s:1746 .text.LL_TIM_StructInit:00000000 $t + /tmp/ccqfGNRw.s:1752 .text.LL_TIM_StructInit:00000000 LL_TIM_StructInit + /tmp/ccqfGNRw.s:1783 .text.LL_TIM_Init:00000000 $t + /tmp/ccqfGNRw.s:1789 .text.LL_TIM_Init:00000000 LL_TIM_Init + /tmp/ccqfGNRw.s:1995 .text.LL_TIM_Init:000000f4 $d + /tmp/ccqfGNRw.s:2006 .text.LL_TIM_OC_StructInit:00000000 $t + /tmp/ccqfGNRw.s:2012 .text.LL_TIM_OC_StructInit:00000000 LL_TIM_OC_StructInit + /tmp/ccqfGNRw.s:2051 .text.LL_TIM_OC_Init:00000000 $t + /tmp/ccqfGNRw.s:2057 .text.LL_TIM_OC_Init:00000000 LL_TIM_OC_Init + /tmp/ccqfGNRw.s:2156 .text.LL_TIM_IC_StructInit:00000000 $t + /tmp/ccqfGNRw.s:2162 .text.LL_TIM_IC_StructInit:00000000 LL_TIM_IC_StructInit + /tmp/ccqfGNRw.s:2190 .text.LL_TIM_IC_Init:00000000 $t + /tmp/ccqfGNRw.s:2196 .text.LL_TIM_IC_Init:00000000 LL_TIM_IC_Init + /tmp/ccqfGNRw.s:2275 .text.LL_TIM_ENCODER_StructInit:00000000 $t + /tmp/ccqfGNRw.s:2281 .text.LL_TIM_ENCODER_StructInit:00000000 LL_TIM_ENCODER_StructInit + /tmp/ccqfGNRw.s:2325 .text.LL_TIM_ENCODER_Init:00000000 $t + /tmp/ccqfGNRw.s:2331 .text.LL_TIM_ENCODER_Init:00000000 LL_TIM_ENCODER_Init + /tmp/ccqfGNRw.s:2473 .text.LL_TIM_ENCODER_Init:0000005c $d + /tmp/ccqfGNRw.s:2478 .text.LL_TIM_HALLSENSOR_StructInit:00000000 $t + /tmp/ccqfGNRw.s:2484 .text.LL_TIM_HALLSENSOR_StructInit:00000000 LL_TIM_HALLSENSOR_StructInit + /tmp/ccqfGNRw.s:2511 .text.LL_TIM_HALLSENSOR_Init:00000000 $t + /tmp/ccqfGNRw.s:2517 .text.LL_TIM_HALLSENSOR_Init:00000000 LL_TIM_HALLSENSOR_Init + /tmp/ccqfGNRw.s:2659 .text.LL_TIM_HALLSENSOR_Init:00000058 $d + /tmp/ccqfGNRw.s:2665 .text.LL_TIM_BDTR_StructInit:00000000 $t + /tmp/ccqfGNRw.s:2671 .text.LL_TIM_BDTR_StructInit:00000000 LL_TIM_BDTR_StructInit + /tmp/ccqfGNRw.s:2719 .text.LL_TIM_BDTR_Init:00000000 $t + ARM GAS /tmp/ccqfGNRw.s page 198 + + + /tmp/ccqfGNRw.s:2725 .text.LL_TIM_BDTR_Init:00000000 LL_TIM_BDTR_Init + /tmp/ccqfGNRw.s:2862 .text.LL_TIM_BDTR_Init:00000068 $d + +NO UNDEFINED SYMBOLS diff --git a/build/stm32f7xx_ll_tim.o b/build/stm32f7xx_ll_tim.o new file mode 100644 index 0000000000000000000000000000000000000000..d209220ec49baef8581d73bb9382bb4656d64c75 GIT binary patch literal 41128 zcmdU&d3+Vs-T!Cq5|Z42Aqfy8>V*VFWlKOr1r53E1PBSPRY^z!39^JFAX?OjTCK&k z?i*^YTdhmgr&<@RTNO97sI*#Z)w=MwpyF=j_xYUjIrq-J0iXIj{pUBY%)IBjobOrY z%$d0-bMKryv3ip4`<`2TZ?Kn=Ja6!2#u6Q6FxVU64fopa4lgX-;)lcY!V9ZfPH*j7 zJ*2W{%aBCrmQc87>pq|#p3$;TqW8>#88=lGue+nF;DypH+2I+jiOr{nOSeSAXSZ-~ z;MT78vs?F04BYCqKigWhd19!l{*EO;l?HWnM zX2hzm!BM@bD(i&_Er>pf(W7M(>Z_X9x16$gbu;6Sz|lK5aO@PnFc`mTbA+WYG&$5E zheDG>U2bL$Wv2Yf;gMwgZOFhKoBU*-JhioS%eL^emS<4@HCPjy3lgU`u*c?xb6W}% z3Da}E_|acQrngPD>DZ@`ZtKa3v~;C5-8D#;*c>WMpl`8mft026caw*>J}vU9t5nhekGYBap4Yo6g%U4Fc6a`^KrM;^JbYKtE_a^8^( z2O8pBoP6Z;5~D4dS7Nj!JVW8#b0qblkkyk`pJ((D=}D`P8GW|&q}AsdeZKUh)#n&} zTzb;#FE^zOsg$JEuS}ryTe~Vu=?$&E)95|vNvm(O{sZL?T79<3w^I3%R^P+uyQC+r zK8t#cXQmwtsrS~|{^?bE*;w?#^|Q8Y zt5{wCXnnW=vAhxYgj)`rc3xG{x>;MiUbD9Nz1RC*AdV*W6t<#5U#cQ?vp5Cl_t-_X)kQ z?aS}CWk2Z0zk3(DgY#+G-D*F3*N=blF6|$g?SGr?duIF3cbU&D^rb43S0E3>&EDki z(`!S%qQ~Cw<2i3IcN;eh*?+_4%k8)C`iSL~;>aSNJ+g_0)hKy*UfX0dMsDeiF=lmZ z1ZUZ{(Da`dCZ?TLl6V^ANO2a%;)2rLh1{+;`(;~hiA=*NSB+~)q@Zd`?@&(5=`9gl znFb_IsXw(Lg#O8~_$!XZ$@XfS+-Am0<~6b9)Yhzpt6L^+*$~aIE~=ccWkQ4_Xktq^ zJPrA-KeHqen_gI%*!o7*9$Rk7i(xFxgSB^fV*P3Lt5Nc&TTX36Z#UQLGm+1>Fvex& z74CTSlyHMRI^lT<)Y9|v?~eWSER4h$@f)WZdKf2-T({oT)T_&FHF9FwLb9!N8su1Y z9(qghx@)RpxTdy+b7|Ys)o~Vmw|E`v!9-JXtkk*ZSAMXw=Y>2j5r1V5&&wNy&6C-l zR};L`fjN}jx%Ik_wrr~lWX-dCCO4UX-_@_gg$ zBVsLR<>n z`_#m)WqCtRo)h~m{liW^Ja!P}NLckdDz+2K9gRABee4UiPnMILVpHhf!{yf!TZ2O$ z&35*-+(aGPJIBeLv9IZ$>-<;7=F&fA?cvfcKXx*DLp0ARPV-}1SmK^eai$-e%_{YB ziZy=hNGf)6it~IgZv=zjyk(ckX^H+JoUBUM}nMuoLrhCr*a^M<*A>_F*|5adL62obsbi?jPI6@Q*n;o|~9C$BRDh zf!pVbk$JZkMpPW1-x0ZeVNhgnp-NE8L<>XPZ4z}fbCy$A(r2Mp#$Hq>i z{EU+;V+AbVvre9nJAv_^bMlnfdo1tsPOi?K1@i_c*2G$v{R>W>6I;#jFFN_~*cp`n z?Bt_z$4^4*Z*+1!oDy4 zUif%8W!)OS5K<^RayX=&Oqw2Z;j{@_GgM@IkteaAe-5e|8rqk7oPY=)iHseaAHm5K zI>2ceJ=@F9e+Qi>G&x=C<&T3kG)LM{Br7{NFTW^%cO(imNb85fkthtki$YK5T!W5Y zus1V!Ht$%bE%geXVB|mN*|8&1P(k%yBxV<|aG^IP<`w*g;(HSFz3}f5F!XtNIuK#- z-to{kIS1en72L$ieJ4*Z*2YXjzT`;kdM3xY1VOH=j_FPiRKR-=;TQ3 z0;V1BD9?9tUTi%ZZjqDoW9yiCyOWDzg>1={PA-o1Wcrhw+&}g)Tjn$;$GyC7*)(VQ z;hR}l77;CRuAg%)3u_8@fphk3VJ>xY#1`fnCuhg<5F>P>lhG1$S-RW&@S%tnVaS}p zp}YK?C8%@^7jG|gk8}27_t5ttCr4tVS+GAjIXm_^gFoxX%vHHGFV@MLz2d8<_KG#L zCEsxV`LXq^>HAJDie<6oK6P?&Y%J4%>*W5iYngu}q&^sroke?3CzpA7H}kmn35D-s zWmtv651{c6j24-59o6v;;0BBT7|caW5dr3X9zjib6EFm8pFt3yoJkLVHb#K!QLn;A z6wWWnh;$eu^+K_1q!JtH3}{bHMk+~0DqM;R`(H=WOLH4z)Fxwm9WkYO9ooMpV|*QP zr77&ka%>937z3{;l@}*tY_c)-g_f5KTcb^>81Jx#R|aC#BgRpTv2U)c%au098fedC zjOlEuDDos)6StV~jwqWh|E0kjji@=R3>KYVv9kc^b``xh?{|>@v?2N*SLO#wy z_RlEfRM`9rW3DCp+d>`>?Q*QPCHp5^@@I(S?`BJK6YSSuwZ+@rD&L3VEh^(EqaU}* zzR0)$Yrkhvp!DXQg)+a-V!}KMYw>FkrekL+R+QOP?AdUt7p{W#7})$Nd9KXQhD|R# z2imi++A=>Ic1Pco`T4Lp`uD?r4^~^|4OaOX6z@}M%KU;=jzRaYz}oLi6lgxn!c7ZS zKM!Rt#CX#Pa|71mEC?&HvjQv1%!2qQ1Sze|?+BwObDq2*=GmieS)nNLIt zzsr{7J=ovGYRi0zRSw8P(XiSwueQqhP}I{f00m-E&1NBEJs1ubkAwDnn9s#pJOaWE z*x`7AGMCb6c%aNHp|}q=|Bjxnorl{pzYpy{vDz{ZPcL)1ElFPtYWY}gnJcVvCKS9R z*fNi_%3nfpHr9UAQJ{KcYBuvge+kOG0NRIOegJFnkr4ijofoir-p>BaYX{rc z+n|02MnAWgEA+=9(>eOWwE%0MU0J7(LpAik(6A9_z5j_FmXCvd99EpvKLtwsJ=uq! z3vsB2h&6N~23sVwQJxEprr_5g0SEA%{o{D#PYx8Q9*Lg8LHGGF!j8KqhsrsEvnzas zwa@KHi8SVe1`1^Q;3>91d!gw|vGz6HVYOAxh2k(O&8TpyRbBzbFR9#>B{`|3i=nsxtF3XFt;gd~ zJV>Rf@gS@G7ZhJ(?KcbO=M)y2n_8^?EL84TXm>}zU9c7(17R|DCSqmfW}C_##G@Ni z<@&?Gqq}oHDrZU*3yq~Cv%iGFKk!rCZ7dW=BBuWe9PQElz~76Ny8zk~uof-A ziHkI2c*i>*UUTSqs10-sFWS-Gp7%MFeQ#saedO=N8~w|m{5jTL*y(u5z8@a_{hFN5 z!k>G4eL3Pw2(u}KjNt9MH~hK~ZCCyShS%p^dGD|u8XU!8fd7(jyDlMMuMr_YS*OVuzQ2T_<6O*RNfxvBRtF zuIvN{Vh2?(XQN)Asv{p$b=IVhDcS{og{c%v-(u>$Jn~hAg$`3!mME`(gCVZ-yXd{G1>@=7}%OSnZMBKc? zM5p-CZ<*+PSXRPk1rwbH;cV>uf{FT7;0&Q}h?|d?=x2Vocs#V%!F~;W&_uVQW+ncI zXefWW+7xk3o6bhvZ9`1=hfpxx=^7;1-9MlGZ&T{Dc@Is>bM4-Ko)#sig}<6JVFQY=9_zqY;ZTpvd~OzT=O59>kWcYu82$y1Z?Sr%4?&_8=Qdp4jJ`{k zXQAW;yEj&EU>`WHqzgBz>Gn>v7y3qV84P>DWly@5euYG|hM@KQccbNW=>g$jn0YC+ zk9QN! z>1Dcb^CsPVKe`|N*ie6g&nxsRV?)tw+S3pD(Vw_jAH)7(G8Vg4h?{S)`q_T;R2M5+ zg85IZHWtmH^XQY~M{jho`omsApWWCK%%?AIID_Nw|MHj9r1|&`pe$ z??-ten!Yd<_Q}auyU~Z6y&0>oAKe9g(8QVxpQDqpXbwHhSpEFy!SrFjIu7>b$ylT5 z!%Y=q?dnGtxLD`H=j>!GnnRlyYd1g2Q_#e^5%ymvW6h)wH=Nz`%lznFF4j8uJeZ6{ zb7%`=4f3O}xLB{i{*sBs<2au_+_W>+K7Mo?{dgQdhR=s47LOy%m??qJ5Ifg&G|AYZ;CCzO(=Tk)f{;8L!I?}HRnL% zY38b4&6#FB&!gwF^yEh=>-lWZ^I7M)lAi16$qz8rb6wDLo%7@;hR|*F$S6H|y5(s-Wjp&T|Ak*U*!fBkQ>)=()yuMndpBnMa0~Nb7lWmTAI0%>>}d zSu<_jYjH6NHPVyUMeEs^HO9130+$%rCL7PeFY-7{p{MnllC_`lGLw;0vL+cX&+qLI z>QxvE_u8e`Az8isT0ftKF7slsgP_Dw@9Two9S}P(wts9Yt|E~=JR-WUL6-cGZx7#} zTIj=+JpiWRxE0AM^kXrkjP4(!KDVbA&bH#z!ZElpi9x~0uv4Z%YZH*R|dTN|@W z=^hwQxZqsDdZOVNyB{GBkRC`|MnUqu8iFplUh?z9+MwV6zhOtC8fcIRsRjvF%H=lgFDOtGW5=f&Hg}J@a_a{5eLfb?%qJX-Njami;~tBDdqpv7J2{IgRRFS^HChGzIO=0 zYWDD!d$Dcbm8@k=*hna%J8~hfjmJ8$@bK@36;)<+2ix6YK)v0?Ho35K9fTE~YXZPJ zU>930E}OJQNhx>OC`*tYXFwjg%I+&-3X8CdGk~DWcFzFQDBEe0EHp_DT7+i=^GGW+ zWV5g(wtpgwg$3rZrYdxx>b4 zLmD;~*=6^!O3H3eWPw%fJX@6bZ5El)e_vWL~%U2L_~gKWjLu9Z^mu(6tu28|UV zdE~K=ZTeCV5$7R6m+du{pPLKI|7HmxkzGfuB_mj~y=8e9`q|q`)>7hGil!mhdt%Pm z?hRN=MLyO%r(BkuHDE0@_KH|XaEL4nI>fepTf)>d6dPaV$J8_~iy#UuI)ntf{w|qO z=os7frHMv|IM)6L2TQ{CORG2efIjFoR{^wFqFG(Tgia6 zbRU8hSrNmqj`+7z$F}|5u9~VZA+9aD?(Vtsj*=Rj&9Tc?_m*t-AYq)2AqSn`aczP zSsbNi#KW4>FXUfme9On=H&xc=DjG8cZ8&=c=+vH*g75iC+mE|RY zthf8vrZ4uYR72Eb-QFmN8A@34uohs&4H&^egqMWuE<2zw516n`TR2kjTtX>{3bTu+ zEjxI<)nc2rBTyEL-aI+T&++vE$GL~S)m4UFka|jMt zSzf1?T{&Pa_if3!)xziuo7S=^B~8gC*xW}#i{{QI>+L?a>5J`qHAFqu?KZbk*mHI^ zk#ybe-M>9HJRqnnVJlnbDhn;^$slP}vKN-IMm>kH9<|s@F3jDw#cYDM9Ddxj1xdQ4 z{!3`QlloxuFb6hI()a^An2ADJYl!|>gUv*l)q$CaV-1=q?}Zg+f>(f`nKC;f%*2Qc zGv$%iOt5nXQ&ZmGnhDk@XomO$OBQUtH=D54Gyld&R!@hPvMqmITKQ#W`E3E~(h4YZ zs(^KA1(X?ycevOx)e^}v+5dyCO_gbOTA5@{m1%ZbnPg6tX?9wfWOfDO7!zFBPVB)U zuiSjVV+n)Z|#J#x}VGyC?^Nf47Ue0J~!cIS~V~2KxhL zd(%_nZhC@d-rMYp6{(3aSc7KDEHlim=s`29a&$`h@b;CUQ0Q=V?k1V^`^ zneuFFCfF`PGsJ&m33PbdNOftAq&~?;vaL{;)(SGS6>K%@(yA$Qs+x6a)s#6^&APN| z%ABfZU0O9|{x|CA*_zd+)l5A*RkPV?HIq42v)O4ilQ~th*=aSCIaRaSX*H8MRkPV? zHIv!ZEc2vudLFtsR-Sw$tAc(=@RXvOWEG$$DzQ>cvgl9~ldw`vvdB;q)l!ozD%1oo zFZ3qa=b*+mxrDHX(-SK`{-EgC&r2G$vjs#lf-XDmwGntQIxdOK>Iu8M9(cpahkJ ziSi1p$c1#+r$9GR%~(w`Sso3^U~iteJQy!%W$>UJdbbhMDpQSWz^BZ4xXR z

Tr%mn|99W+z!Z_Nb%GaWQj9%ao0|JfWgQ?9mVg8x4bnkhF~Gr@le2hEgMSu?@^ z@&?V6FSKTY|F{jBDc@?%1fTN=no(`D@T{;4k88*qvDO`5v`9Tv<^d6?trHuH+C^A- z&N*$!Xga%TdE{4j(^7L*H!Zut(g5LThKJ*^|r@5MHo$)RbTirD@r%_=H2m zs~lSv2u)qZcJ%CLRaQSP=uh3W?daWu42XYF(4S8)%(MP!diF#VocS_S5UIM$kR|fID@!bkjd$jsiAj?u)de4cWyFmQ@y}pK`Z8L*|8t z%K;YM$R5w7z`|S+xLYK7j?;_0r{dDzBAH)ahFl`KO(b|8@vL#9CUsog8L|fZJTKgG zId*t9xN*|yUC(y|q|>`zz7Y!cZMV1{{Q(s0$8K?**NufvUw}4YKXrqk)9(#k1y(ou zIlb$7ZrF2r*TdX+=k%^Cxq;52>NOad=`kAd zpokqKJf6x;+bzJx0S>0}2cK6k?qb#rJ?9mqv5NJj*^=W3x)LhGmsw9TClf zGMd%G6p#9U>J;sPzT1oaHyjj}U zemL=sayut2@h8&0^uvj7liL|-iNBKexgSn^kKFze3)cCDPTSh&|L~#uREO%tw8Xzv z;mH4V1Bo6JCHrhOm$IHV-(Lv@aJ6s$fj!TpM0UZ?bafW9ChPz?lz?wB5F-oKRI-l*tANiTE%ie^vAGUYuz5Utu?MF+T-?UK0^1%8jjz|C^99$ z&VqP64qdole#)8^UTlltkWjxd6gyRuDUS-Q08`O4~ zvX!P(;a;{fsKtu7Q)iUx7Z`)l`EB|#krlv=lyGe5sfh%_EiW}8^ zgt_eS8e`?*(MlxaonqF2=z*!-gWPV)akx_rk8W?bT#<)IhryBeT8Nn39WHBmbd>9$ zFBh8LJEp%@kY=?}y>tuWA?z@l9 z=45pWlO=a8=9p}w0nzcUZBor;y^>*gUv66^*%YN%qWin%c(rHhWdC)$JvZZ_thB~> zE^0c^o@xxs0nz^iyEWp+7#&Q9vUiDvg~f$g@vPzez%gJ)n}Mm1C;W7hbjG18)6wO} zk2zCk%$>TVwX?3XeR*T2H@>E-yt-!M%vx_&U0rQmXG3SRH!D$|Sh{3>>jH1W)QPp; z_~o5T+nX0HZD_*t98)LFnLB5E)!am4Weprh%F#qk1Oq1$GipbA)zxzYCa-gGTVvzm z_HwsV;dYEC%2F|Ra&1ld+(}E@8=GsJJDNMa1b^x#J55Qd@@tvKf_1hYm%a)Vip%xt)zTuc@=$TaJX~qvv)8N}HB>O>=u| zTT6#4L|t=dZF5_5XKQEc(j|$d%aHl=>%|(ROpRS}MD#iHelK7FOR0oFKJ{#9SB8_L^j;vxg+$+tISL zy)&LxF!-$WOgh`yYO1TJR@AY>nDc6JLuYH_tmU0;%ad)3nVIUki8JeFr8O^#J-)FM zvp7?i&{s#x^>LO2M>AEI)QLJZv2rDvb!M{EYO2Z2OPbqpwohEqyrgsPAvF`m&zZ=M z)Umj+-5kKFi9pS&mo^?--MpfC5kpOFTGZ@Dihb3<6KiYnqe^L~TW#~A=7tWP#>zEN zIYvjc3U`EX+L?~d4r32h_s)sdGfg)ucwlX^#3B@NLhFjw4s>S39j&-XQa668Nu@Hl z&dUP0BU?MMZes1B6DN%D++KNduOhiOGPyS@xwo%7C(!;JDN$>Vl!=yxB}>p;=wT{I zvRjx@V^$*7itN!C6K(IY=l)FFzG#b)wk=flV3|#?(g?u*%|VF{n-mW@0T=7`Kn*h4va<{|M!`F?RbTNf?rd4Ucpf+(`uS}u_8r<(KAIx>Rp(GlxQ=USXm5g|p}nzX z9HwGd?AJVW@jmn0hBdXthc3Wh({T;$^M_W%ht7gDzp0_KVQ5D)29KpnIv~$qzQpV& zb*O)Na&!nZ&D6S;?&wU#(NDEupqr~(CI@M+t}cP0&2-IVOkBb%cpV?f%_wg63 z#ouXDhzS_kFd*;}HU?d@?hqWQx;oP%r!*{DRM)(uV`+P!Uk-0sy104x{N|>H;WMVz z%o$$W(A2uLre$g8(j~2pbL*DR>u7GD-_Y1Rx4ogMp?$c9yQS@OYZ6r%&d|*5SUSHG z&Bm*dJEbrnu^Xs-?1-r**wJ|6yfel*H_Rv&&ZOW?%G5-#``L?(3V{pb@oAvY z?#<9wlkMtFP9zS94=&&L0Mn^(k5)dkVz0~|W}c(OL!#U8wYycl@_Hu!*Tk7{{=Z{< zue{U3r-y##cRcavvg{ldlm&VGsCAK!@| z$i~Q6f~tu3$+n;wbJ9T(|JE`8uu1B|{6|k<3FH4f!8YUncJak<6J;eBf;<3RluU#F z3k8<27tKf?)dO_4?}uP#`p#sUXmXD`VLaHIo`05}_O$;y48hLyssGz%Wu)(sk-mqX zaq`Unfg&x~5M?{C*jBo;|50jL{%HeX*&}QAwBJXu3m7Pr7gfN-bf06)4@`{8U8JA&k*2-QM5CYe{+pM?aQt*QA9z zVe>d;N)`6vDZ$tWX2@k3@*WxT;0$^144Ka}r3HHVb?P&X^#K31ka z$KfVbAEa;#l-zR@EvZlX>9>>ahAVaFCXKn-)PDM{T}m1BNxuVjK{Sga(S5KC+$UyO zf)N9^h}{zejKMTJn2t%^e)E{-;u29o;#A==&&7~hMPjJpqp-P!di)xvdSA-u;_St_ z=(;1w-Ss_$LHybZ#^kB?ekL>%zfD0I<(4q#}UXG_ThNy`B*+_#&mGJWadx( zERlVd@&a*@c!GGcc!BsQ@fGn)u?PAf%>O!F7Z+E&mw=y zljZwNEW~XPWT*&mVog!r`de-+=6 zezW+o^xsO}CT8c_e0qw##ofqho;Oh3M;tDWCDBe(Ner$t#M!d{MD_)ej}_abUnRLq zJYD+pC0`_7F8vLXZxQbzk?+0Y1L9M%KP$d0{#E=3iE@8L;^OeB_=W7eou@sIoQ8W6 zv5)j+;t1(SiTg`GQSwxAru0WjK1N(XBL78Vn|Pw^r-)~X=ZF`PDBpD?J{sI0-Xi605|iB;p-P zq7NP^9wU2;?46QViu@W2)2$INmHtZcTIqi)`A+e_q<=*66XNqE^4}a0A-*I1=c3;W>CqpeVgZS`yO0U| z43;=V`h-|RR$_iYJe)+Fd9p8&+%6s`{m;Y;r04JTGTjx@-zfPv;vLdIAo*dDKk3VI zz99J}@pTgAdP{s)+$#H5qK|u0Q*W`5oQdlNc@WMAaj5hY#M$J5_$s}41c~xD%Dz-` zhqzMu(co%C}hH;OINcS>F< zo=76!UyHYizZV}CpAt8cDDU6Ma?ksR_>uHceE6olfEkaf9a=) zbEH39Y#4}A^Y9pgW?~>r%9ySAZ`@@Df|24r{WhP ze#gb6i;6j7UlR2%5eJhq@v9}|5PYvztdjl+v6nb=88om>bRRy;%t`wBk?QQ|0VjE_+UK?NYuZt7?*w!i8!OBKR}!y`&4m; zc#Q1x#6{9CBN1n{^gk2Nll>y`GVvDKZxip8{y`FPo|FDX@ip21A^ubRLiTUONI#@U zeRD{}DIrns-NeDN4;9PBD%mHAHPRnKBF=p27mA&-A1|ILo+JAO;+4{0OCru~(*I6e zM`B!gPJB)LZ}Dp}8`ID9>njctM~YQqjW}0aB%UDtT)bGkUc5_uSbR?Wo48s0O6-Bp zm@H3`I8ZDX4-%`zpNK8u3h{LD0`VI0cJTpmz4(&&rs!ee=Y34e80Lw%TpJn1HROCD z{YHqRMBL&S{lVg4BtHNDL~Ilnh)cx|@eJ`7;sxTx;%#JH-@^s}AerB{rTz(Vz4*HL zrue@2p~!a;aeg32>@D^YcNGVSd`l7i_ZKV03F1*C+Ol435f_P_;!1Iic%EqH5t051 z$$VQ8<2@)oCO#=XFaBBFEPf<@E`BZIA7v(9MC4nI7=LGxFE*k)Oynz!`1yXkI8~e> z9wHtg^5sVKUnZ^;SBZSj5$#uszY=d09~aGwHQ~2G@<#Dh@$VwvhQxT^h<@10Q87=< z7x`)=`VSKMb|lINhKsw4VeAYLY3CGvesw67DN5Z8+@i+>gQDkl1WDSj{VGdA@(Vowpj zTW$3C!D++Y#Zr-Pabmi$VnUoO&J@jWi^GqvbfW(Pk#BXPyh`L-oH$=`u6T)fh4?G+ zM$ybi!+)LRCqy$p4L#rO#CRWwpNU_Jkt}P^7WvvI`VSI^i01d!q2Eukna76A-|?pZ zByonwA9tdDzPM0aCN39OiCrRJAH{SRi8qM1hPy4{;vlhH+*jl)rs!WQ9w8nrHi>-cEd7>>9pVY%Nh04)MZZhLt3@*p z5B<%Oe=9yDJ|gmMRZRbi$d^-bzGt)esrZFx=Ivp}*FTLPUt2~05^;byNaQQ4Xy^N? z$WukWd6e=+;$@nXd=O zOFvOuARa54d3gA(ki1s>mH49gviLXgA7Z~;oBu9it$3(-wAdi76@MkZDZV3qD1IWE z`DB!D9Oq%d3E~v-GVv<$WAQWb8}WPb2;5LH&e7t1;)5dJ6&9+*bx$<&p^#sb{I>X> z$X6!OACIpX_7L%g0VDGbVxdaU8!Ck z1od+nUs6W@rQ!H;S){e;3~o zH;a7B8S^*uonSWS|G+$vuQ;PzD()=~6DNz)MZT?!^L59F^TmZC-&;oe#iE(lgnX^! zJH>m%2ShWk3BL`JH;S){e-}R%KNG(ZzZZLPUJ!8#M81KI@~+}gv0NM@juq#NW*!si zmPuYNt`fV%^F%j~d4**DL^1QdUA#;DgZPl><~d)KZ00+W?r)O$b~nb!5%a|&u}mB+ z4i`s?330M$<~b3sR`NV?zPMOiCh|pc%>OFU%yUA%S@Ip?-QokHnfHX>pCmsm{#krQ zd|iA~+$@^;P^9PE)i}TEbAAxa5qpY!eH``UMKk{ixmxm3V!gOPJXSRGpYS*HpWx4= zKTEt^yjuLVc(Zt)Xy!kW{xQiVJBQ@^{u95yc@fz`Z(ad*_L_d~n<~t!jDtWzV<~^Y|^PZrY z_XOXU{X_9zqR)9i*t5kvajaM=P8O$&KN07O^TmbY3F1kjncqY{W_}Yi^P8ZV-vqCh z-%aAZqM7G}{ZYw(5?>Kt72g!!5&1qs)~iGuDDEK+70bo_#c|>Uaf(MSNBKS~T;W zNFU)mAeb%gBo>N%aUt!4MZUX`@;H(2D5T6^`z86BLXxjVBl$W)a+Sz85>h^2yiUA9 zANjfXoydo`sm~XS#9hSQ#o^*e@c{84ai&-+9w8nrE*6)GE5%jf8u2`luQOx0 zt`L7C-Y))^_y=*lXyz}G?j^~85#JX-6t{|es~Ph#^O|5D=M}+1v7fl7xR1zpn$d5x zI7yr)&K3_5o5fbKP3#m;6Zw*C#ywa3rT8oHM)5ZBcj5+dqsX^GGtL|0yW)R~eDNdg zKIW`QzU7hZC-QZUl!uCZcO&J5$d@!yK0@Rh87VInPZ7<$D)fBMBJEd*e4!%cJ4L=d zk@BBJz9o_J-$cF=&5-hbBHvs{d4|Y06jE*!`8GnzKNb1b zLCU`r`G!HtzY+N+LCTMcd}|=(S4F-Zkn(3D-vmgR&xn$I;~zOdp{hS?%MmKnKNH1p-~i%TvOO}(HWC3%d<=WiKzidZe0dO|-(a=q9jwupY!^s@H4?(Oa(GQzM zGoO$CXy)_5HtNwY&AdM7=JolTg6yYVB>L%T;+bR|_idt?_ea0IkTQ5FiT-<~cnyhi zUN7E64za(oO5Q;k{rYb4UK0KL0r6oH{roZUNfQ128F2%Ne!o%NM56z{CcZ)9Ja}7t zkHq=#fw+aN#JrvO6^ZlXJJI~V0q2SNe*?G&^=Ri?Nwo7Q&fBAXA0W}5Bf}utaV?4V z%Z-5ie+!9rYavT94wGmnGoOt1xiK3u+T$$}?eQRDvmMNHl&JqHoXU9c<`W(r5g#_Z0D0h(u&eHgV@{f`{hD2U-Bp*&9O{e6QB7G9Gn<{D9 zroOLYs?pRuZ~20`txM)FMRzd!4fE!;H?QylR{Xj{P;6*#ShAoQeTGeE({$G?YF*Oo zBBIlI!y55>2l%y%V5<4;4fq*>VdHCO3~T7@Y;T>nyc1#n?PV8u;?yzUlVPG!+yoY! z24)$6E&ak)?B+)smp!p!==&f2Fcfslmt&M$FszzoEVjY&-3qzOSnS66RYMH=4S}#~ zJAOxH_}v7*`tA5F%JAcOu{}TL5zMz`2YzcZ{GNp080g&M+WAT-g7Mgp2RJ9t`LP{> ze*C}j_WT~m@ax=x-!mD0cfjvGW}wBj^Ba(Z`Cf`^5T=}xi!0w(8Gg6IFMm7na-j>x zdmzhR<6J-&Z?6o$4e*=eoIvL{2!6N>dX=)h(QNP8heBpKSr7KlgEHdrdocOXyT!#j zI>V3OlNsxrK<9TvM!xy;JuePB^TlO0nJ<6q8Gp(1tqt+|Lw1XccR_~V8u-;aC(s>_ zTQmGVfL~s~&&A{O8NqzN+CjVzGW-rlW8ouLa&hr;uoH~e3BR_aSE_uxzS7SvZ^Lg3 z?lautY;pJnkJ|{e-@S#l{cszSY`+m1@iq>`oFa5?aq+4${7xO@dB=0G)8hONf?qJ- z_l`$BFqgyQ7RT!P%j}GJ-&Nv&46wV!#pClR!FY$CXFsDc-axD_UQ@^_M@A8cDZG~SobZ%iixLgcfu>HJ?>}MO6Z*Q!wzI;vx&5-PJ zmB-lcj4}on*M4Lm8?O_7TQC;k*3-N@h4J#SGEc-yE=^6iez+jex?S8tr}?#AjAv*9 I892ZH2MSTe{r~^~ literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_ll_usart.d b/build/stm32f7xx_ll_usart.d new file mode 100644 index 0000000..2777464 --- /dev/null +++ b/build/stm32f7xx_ll_usart.d @@ -0,0 +1,74 @@ +build/stm32f7xx_ll_usart.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h: diff --git a/build/stm32f7xx_ll_usart.lst b/build/stm32f7xx_ll_usart.lst new file mode 100644 index 0000000..2c4fb51 --- /dev/null +++ b/build/stm32f7xx_ll_usart.lst @@ -0,0 +1,5295 @@ +ARM GAS /tmp/ccci4zB8.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_ll_usart.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c" + 19 .section .text.LL_USART_SetBaudRate,"ax",%progbits + 20 .align 1 + 21 .syntax unified + 22 .thumb + 23 .thumb_func + 25 LL_USART_SetBaudRate: + 26 .LVL0: + 27 .LFB215: + 28 .file 2 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @file stm32f7xx_ll_usart.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Header file of USART LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * This software is licensed under terms that can be found in the LICENSE file + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * in the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifndef STM32F7xx_LL_USART_H + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define STM32F7xx_LL_USART_H + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #ifdef __cplusplus + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** extern "C" { + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Includes ------------------------------------------------------------------*/ + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #include "stm32f7xx.h" + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @addtogroup STM32F7xx_LL_Driver + ARM GAS /tmp/ccci4zB8.s page 2 + + + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \ + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL USART + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private types -------------------------------------------------------------*/ + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private variables ---------------------------------------------------------*/ + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private constants ---------------------------------------------------------*/ + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Constants USART Private Constants + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Private macros ------------------------------------------------------------*/ + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Private_Macros USART Private Macros + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/ + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported types ------------------------------------------------------------*/ + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_ES_INIT USART Exported Init structures + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief LL USART Init Structure definition + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t BaudRate; /*!< This field defines expected Usart communication baud rat + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetBaudRate().*/ + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or receive + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_DATAWI + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetDataWidth().*/ + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_STOPBI + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + ARM GAS /tmp/ccci4zB8.s page 3 + + + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetStopBitsLength().*/ + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t Parity; /*!< Specifies the parity mode. + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_PARITY + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetParity().*/ + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is en + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_DIRECT + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetTransferDirection().*/ + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enab + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_HWCONT + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetHWFlowCtrl().*/ + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_OVERSA + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This feature can be modified afterwards using unitary + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** function @ref LL_USART_SetOverSampling().*/ + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_InitTypeDef; + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief LL USART Clock Init Structure definition + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** typedef struct + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_CLOCK. + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_Disabl + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_POLARI + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetClockPolarity(). + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_PHASE. + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetClockPhase(). + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the l + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** data bit (MSB) has to be output on the SCLK pin in synch + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** This parameter can be a value of @ref USART_LL_EC_LASTCL + ARM GAS /tmp/ccci4zB8.s page 4 + + + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USART HW configuration can be modified afterwards using + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** functions @ref LL_USART_SetLastClkPulseOutput(). + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** For more details, refer to description of this function. + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } LL_USART_ClockInitTypeDef; + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USE_FULL_LL_DRIVER */ + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported constants --------------------------------------------------------*/ + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Constants USART Exported Constants + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Flags defines which can be used with LL_USART_WriteReg function + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error cle + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error cl + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error dete + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error cl + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detect + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission com + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission com + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detect + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag * + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block cle + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Flags defines which can be used with LL_USART_ReadReg function + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error fla + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error fl + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected f + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error fl + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detect + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data regist + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission com + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data re + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detect + ARM GAS /tmp/ccci4zB8.s page 5 + + + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt fl + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block fla + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate e + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate f + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_ISR_REACK) + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable a + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_ISR_REACK */ + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission com + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IT IT Defines + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt e + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data regist + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission com + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data re + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block int + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detect + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt en + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUFIE) + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUFIE */ + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_TCBGT_SUPPORT) + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission com + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_TCBGT_SUPPORT */ + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DIRECTION Communication Direction + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter + ARM GAS /tmp/ccci4zB8.s page 6 + + + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PARITY Parity Control + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_NONE 0x00000000U /*!< Parity co + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity co + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity co + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP Wakeup + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DATAWIDTH Datawidth + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : S + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : S + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : S + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USE_FULL_LL_DRIVER) + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_CLOCK Clock Signal + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provid + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided * + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /*USE_FULL_LL_DRIVER*/ + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ARM GAS /tmp/ccci4zB8.s page 7 + + + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the l + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the l + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_PHASE Clock Phase + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transiti + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transit + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_POLARITY Clock Polarity + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCL + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_STOPBITS Stop Bits + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1 0x00000000U /*!< 1 s + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 s + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXRX TX RX Pins Swap + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as d + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works usin + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + ARM GAS /tmp/ccci4zB8.s page 8 + + + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works usin + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the da + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the da + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_BITORDER Bit Order + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/rece + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/rece + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Me + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Fa + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_HWCONTROL Hardware Control + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and R + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS outpu + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and R + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ARM GAS /tmp/ccci4zB8.s page 9 + + + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS) + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake u + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake u + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake u + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */ + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode * + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection m + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection m + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data regis + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data regis + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported macro ------------------------------------------------------------*/ + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Macros USART Exported Macros + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + ARM GAS /tmp/ccci4zB8.s page 10 + + + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Write a value in USART register + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __INSTANCE__ USART Instance + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __REG__ Register to be written + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __VALUE__ Value to be written in the register + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VAL + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Read a value in USART register + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __INSTANCE__ USART Instance + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __REG__ Register to be read + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Register value + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Compute USARTDIV value according to Peripheral Clock and + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __BAUDRATE__ Baud rate value to achieve + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\ + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ((__BAUDRATE__)/2U))/(__BAUDRATE_ + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Compute USARTDIV value according to Peripheral Clock and + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param __BAUDRATE__ Baud rate value to achieve + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/ + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @} + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ARM GAS /tmp/ccci4zB8.s page 11 + + + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /* Exported functions --------------------------------------------------------*/ + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_Exported_Functions USART Exported Functions + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** @defgroup USART_LL_EF_Configuration Configuration functions + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @{ + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Enable + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_Enable + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR1, USART_CR1_UE); + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Disable (all USART prescalers and outputs are disabled) + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When USART is disabled, USART prescalers and outputs are stopped immediately, + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * and current operations are discarded. The configuration of the USART is kept, but all t + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * flags, in the USARTx_ISR are set to their default values. + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_Disable + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR1, USART_CR1_UE); + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART is enabled + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UE LL_USART_IsEnabled + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART enabled in STOP Mode. + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provide + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * USART clock selection is HSI or LSE in RCC. + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_EnableInStopMode + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + ARM GAS /tmp/ccci4zB8.s page 12 + + + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART disabled in STOP Mode. + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_DisableInStopMode + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_UCESM) + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART Clock enabled in STOP Mode + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is called, USART Clock is enabled while in STOP mode + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_EnableClockInStopMode + 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx) + 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_UCESM); + 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief USART clock disabled in STOP Mode + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note When this function is called, USART Clock is disabled while in STOP mode + 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_DisableClockInStopMode + 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx) + 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM); + 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ARM GAS /tmp/ccci4zB8.s page 13 + + + 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if USART clock is enabled in STOP Mode + 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 UCESM LL_USART_IsClockEnabledInStopMode + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(const USART_TypeDef *USARTx) + 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)); + 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_UCESM */ + 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM*/ + 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_EnableDirectionRx + 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) + 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); + 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Receiver Disable + 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_DisableDirectionRx + 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) + 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); + 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Transmitter Enable + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TE LL_USART_EnableDirectionTx + 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) + 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); + 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Transmitter Disable + 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 TE LL_USART_DisableDirectionTx + 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) + 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); + 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ARM GAS /tmp/ccci4zB8.s page 14 + + + 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure simultaneously enabled/disabled states + 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * of Transmitter and Receiver + 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_SetTransferDirection\n + 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 TE LL_USART_SetTransferDirection + 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param TransferDirection This parameter can be one of the following values: + 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_NONE + 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_RX + 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX + 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX_RX + 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirectio + 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); + 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return enabled/disabled states of Transmitter and Receiver + 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 RE LL_USART_GetTransferDirection\n + 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 TE LL_USART_GetTransferDirection + 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_NONE + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_RX + 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX + 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DIRECTION_TX_RX + 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) + 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); + 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Parity (enabled/disabled and parity mode if enabled). + 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This function selects if hardware parity control (generation and detection) is enabled + 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * When the parity control is enabled (Odd or Even), computed parity bit is inserted at th + 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (9th or 8th bit depending on data width) and parity is checked on the received data. + 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_SetParity\n + 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_SetParity + 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Parity This parameter can be one of the following values: + 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE + 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN + 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD + 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) + 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); + 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_GetParity\n + 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_GetParity + ARM GAS /tmp/ccci4zB8.s page 15 + + + 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE + 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN + 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD + 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) + 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); + 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Receiver Wake Up method from Mute mode. + 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod + 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Method This parameter can be one of the following values: + 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_IDLELINE + 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) + 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); + 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Receiver Wake Up method from Mute mode + 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod + 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_IDLELINE + 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) + 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); + 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) + 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 M0 LL_USART_SetDataWidth\n + 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_SetDataWidth + 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataWidth This parameter can be one of the following values: + 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B + 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B + 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B + 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) + 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); + 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 M0 LL_USART_GetDataWidth\n + ARM GAS /tmp/ccci4zB8.s page 16 + + + 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_GetDataWidth + 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B + 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B + 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B + 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) + 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); + 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Allow switch between Mute Mode and Active mode + 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_EnableMuteMode + 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) + 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); + 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_DisableMuteMode + 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) + 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); + 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if switch between Mute Mode and Active mode is allowed + 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode + 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). + 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) + 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); + 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Oversampling to 8-bit or 16-bit mode + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 OVER8 LL_USART_SetOverSampling + 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: + 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 + 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 + 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) + 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); + ARM GAS /tmp/ccci4zB8.s page 17 + + + 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Oversampling mode + 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 OVER8 LL_USART_GetOverSampling + 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 + 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 + 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) + 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); + 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not + 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput + 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LastBitClockPulse This parameter can be one of the following values: + 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPul + 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); + 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve Clock pulse of the last data bit output configuration + 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (Last bit Clock pulse output to the SCLK pin or not) + 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput + 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) + 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); + 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select the phase of the clock output on the SCLK pin in synchronous mode + 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_SetClockPhase + 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param ClockPhase This parameter can be one of the following values: + 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE + 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE + 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + ARM GAS /tmp/ccci4zB8.s page 18 + + + 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) + 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); + 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return phase of the clock output on the SCLK pin in synchronous mode + 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_GetClockPhase + 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE + 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE + 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) + 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); + 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode + 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPOL LL_USART_SetClockPolarity + 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param ClockPolarity This parameter can be one of the following values: + 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW + 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) + 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); + 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return polarity of the clock output on the SCLK pin in synchronous mode + 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPOL LL_USART_GetClockPolarity + 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: + 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW + 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH + 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) + 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); + 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** + 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock + 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. + 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : + ARM GAS /tmp/ccci4zB8.s page 19 + + +1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function +1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function +1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutpu +1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CPHA LL_USART_ConfigClock\n +1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 CPOL LL_USART_ConfigClock\n +1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 LBCL LL_USART_ConfigClock +1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Phase This parameter can be one of the following values: +1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_1EDGE +1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PHASE_2EDGE +1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Polarity This parameter can be one of the following values: +1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_LOW +1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_POLARITY_HIGH +1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param LBCPOutput This parameter can be one of the following values: +1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT +1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT +1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, +1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCP +1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Clock output on SCLK pin +1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not +1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. +1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput +1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) +1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Clock output on SCLK pin +1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not +1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. +1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput +1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) +1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); +1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Clock output on SCLK pin is enabled +1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not +1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Synchronous mode is supported by the USARTx instance. +1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput +1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ + ARM GAS /tmp/ccci4zB8.s page 20 + + +1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) +1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); +1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set the length of the stop bits +1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 STOP LL_USART_SetStopBitsLength +1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param StopBits This parameter can be one of the following values: +1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 +1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 +1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 +1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 +1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) +1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve the length of the stop bits +1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 STOP LL_USART_GetStopBitsLength +1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 +1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 +1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 +1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 +1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) +1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); +1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) +1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Call of this function is equivalent to following function call sequence : +1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Data Width configuration using @ref LL_USART_SetDataWidth() function +1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Parity Control and mode configuration using @ref LL_USART_SetParity() function +1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function +1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR1 PS LL_USART_ConfigCharacter\n +1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 PCE LL_USART_ConfigCharacter\n +1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M0 LL_USART_ConfigCharacter\n +1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR1 M1 LL_USART_ConfigCharacter\n +1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 STOP LL_USART_ConfigCharacter +1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataWidth This parameter can be one of the following values: +1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_7B +1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_8B +1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_DATAWIDTH_9B +1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Parity This parameter can be one of the following values: +1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_NONE +1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_EVEN +1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_PARITY_ODD +1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param StopBits This parameter can be one of the following values: + ARM GAS /tmp/ccci4zB8.s page 21 + + +1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_0_5 +1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1 +1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_1_5 +1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_STOPBITS_2 +1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t P +1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t StopBits) +1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); +1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure TX/RX pins swapping setting. +1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap +1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param SwapConfig This parameter can be one of the following values: +1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_STANDARD +1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_SWAPPED +1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) +1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); +1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve TX/RX pins swapping configuration. +1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap +1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_STANDARD +1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXRX_SWAPPED +1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) +1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); +1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure RX pin active level logic +1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel +1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PinInvMethod This parameter can be one of the following values: +1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD +1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED +1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); +1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve RX pin active level logic configuration +1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel + ARM GAS /tmp/ccci4zB8.s page 22 + + +1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD +1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED +1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) +1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); +1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure TX pin active level logic +1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel +1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PinInvMethod This parameter can be one of the following values: +1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD +1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED +1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); +1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve TX pin active level logic configuration +1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel +1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD +1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED +1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) +1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); +1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure Binary data logic. +1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Allow to define how Logical data from the data register are send/received : +1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) +1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic +1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param DataLogic This parameter can be one of the following values: +1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE +1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE +1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) +1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); +1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Retrieve Binary data configuration +1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic +1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance + ARM GAS /tmp/ccci4zB8.s page 23 + + +1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE +1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE +1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) +1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); +1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure transfer bit order (either Less or Most Significant Bit First) +1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note MSB First means data is transmitted/received with the MSB first, following the start bi +1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LSB First means data is transmitted/received with data bit 0 first, following the start +1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder +1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BitOrder This parameter can be one of the following values: +1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_LSBFIRST +1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_MSBFIRST +1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) +1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return transfer bit order (either Less or Most Significant Bit First) +1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note MSB First means data is transmitted/received with the MSB first, following the start bi +1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * LSB First means data is transmitted/received with data bit 0 first, following the start +1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder +1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_LSBFIRST +1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_BITORDER_MSBFIRST +1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) +1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); +1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Auto Baud-Rate Detection +1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or +1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate +1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) +1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_ABREN); +1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Auto Baud-Rate Detection +1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or +1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. + ARM GAS /tmp/ccci4zB8.s page 24 + + +1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate +1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) +1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); +1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled +1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud +1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) +1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); +1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Auto Baud-Rate mode bits +1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or +1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode +1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AutoBaudRateMode This parameter can be one of the following values: +1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE +1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME +1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME +1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) +1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); +1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Auto Baud-Rate mode +1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or +1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Auto Baud Rate detection feature is supported by the USARTx instance. +1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode +1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT +1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE +1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME +1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME +1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) +1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); +1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + ARM GAS /tmp/ccci4zB8.s page 25 + + +1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Receiver Timeout +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout +1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) +1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR2, USART_CR2_RTOEN); +1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Receiver Timeout +1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout +1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) +1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); +1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Receiver Timeout feature is enabled +1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) +1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Set Address of the USART node. +1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note This is used in multiprocessor communication during Mute mode or Stop mode, +1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * for wake up with address mark detection. +1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. +1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (b7-b4 should be set to 0) +1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. +1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (This is used in multiprocessor communication during Mute mode or Stop mode, +1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * for wake up with 7-bit address mark detection. +1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * The MSB of the character sent by the transmitter should be equal to 1. +1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * It may also be used for character detection during normal reception, +1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Mute mode inactive (for example, end of block detection in ModBus protocol). +1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * In this case, the whole received character (8-bit) is compared to the ADD[7:0] +1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * value and CMF flag is set on match) +1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n +1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR2 ADDM7 LL_USART_ConfigNodeAddress +1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param AddressLen This parameter can be one of the following values: +1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_4B +1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_7B +1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param NodeAddress 4 or 7 bit Address of the USART node. +1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_ + ARM GAS /tmp/ccci4zB8.s page 26 + + +1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, +1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); +1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. +1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note If 4-bit Address Detection is selected in ADDM7, +1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) +1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * If 7-bit Address Detection is selected in ADDM7, +1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) +1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADD LL_USART_GetNodeAddress +1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) +1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) +1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) +1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen +1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_4B +1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_ADDRESS_DETECT_7B +1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) +1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); +1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable RTS HW Flow Control +1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl +1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) +1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_RTSE); +1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable RTS HW Flow Control +1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl +1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) +1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); + ARM GAS /tmp/ccci4zB8.s page 27 + + +1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable CTS HW Flow Control +1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl +1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) +1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_CTSE); +1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable CTS HW Flow Control +1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl +1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) +1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); +1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure HW Flow Control mode (both CTS and RTS) +1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n +1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 CTSE LL_USART_SetHWFlowCtrl +1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param HardwareFlowControl This parameter can be one of the following values: +1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_NONE +1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS +1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_CTS +1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS_CTS +1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) +1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return HW Flow Control configuration (both CTS and RTS) +1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Hardware Flow control feature is supported by the USARTx instance. +1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n +1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * CR3 CTSE LL_USART_GetHWFlowCtrl +1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_NONE +1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS + ARM GAS /tmp/ccci4zB8.s page 28 + + +1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_CTS +1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_HWCONTROL_RTS_CTS +1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) +1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable One bit sampling method +1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp +1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) +1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); +1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable One bit sampling method +1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp +1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) +1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); +1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if One bit sampling method is enabled +1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp +1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) +1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); +1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Enable Overrun detection +1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect +1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) +1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); +1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Disable Overrun detection +1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect +1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None + ARM GAS /tmp/ccci4zB8.s page 29 + + +1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) +1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); +1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Indicate if Overrun detection is enabled +1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect +1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval State of bit (1 or 0). +1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) +1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR1_UESM) +1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #if defined(USART_CR3_WUS) +1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) +1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. +1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUS LL_USART_SetWKUPType +1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param Type This parameter can be one of the following values: +1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_ADDRESS +1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_STARTBIT +1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_RXNE +1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) +1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type); +1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) +1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not +1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * Wake-up from Stop mode feature is supported by the USARTx instance. +1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll CR3 WUS LL_USART_GetWKUPType +1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval Returned value can be one of the following values: +1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_ADDRESS +1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_STARTBIT +1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_WAKEUP_ON_RXNE +1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx) +1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); +1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR3_WUS */ +1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** #endif /* USART_CR1_UESM */ +1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** /** +1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @brief Configure USART BRR register for achieving expected Baud Rate value. +1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Compute and set USARTDIV value in BRR Register (full BRR content) + ARM GAS /tmp/ccci4zB8.s page 30 + + +1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values +1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note Peripheral clock and Baud rate values provided as function parameters should be valid +1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * (Baud rate value != 0) +1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. +1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @rmtoll BRR BRR LL_USART_SetBaudRate +1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param USARTx USART Instance +1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param PeriphClk Peripheral Clock +1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param OverSampling This parameter can be one of the following values: +1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_16 +1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @arg @ref LL_USART_OVERSAMPLING_8 +1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @param BaudRate Baud Rate +1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** * @retval None +1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** */ +1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverS +1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t BaudRate) +1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 29 .loc 2 1642 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. +1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t usartdiv; + 34 .loc 2 1643 3 view .LVU1 +1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** uint32_t brrtemp; + 35 .loc 2 1644 3 view .LVU2 +1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** +1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** if (OverSampling == LL_USART_OVERSAMPLING_8) + 36 .loc 2 1646 3 view .LVU3 + 37 .loc 2 1646 6 is_stmt 0 view .LVU4 + 38 0000 B2F5004F cmp r2, #32768 + 39 0004 06D0 beq .L4 +1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); +1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrtemp = usartdiv & 0xFFF0U; +1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); +1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->BRR = brrtemp; +1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** else +1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { +1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); + 40 .loc 2 1655 5 is_stmt 1 view .LVU5 + 41 .loc 2 1655 30 is_stmt 0 view .LVU6 + 42 0006 01EB5301 add r1, r1, r3, lsr #1 + 43 .LVL1: + 44 .loc 2 1655 30 view .LVU7 + 45 000a B1FBF3F1 udiv r1, r1, r3 + 46 000e 89B2 uxth r1, r1 + 47 .loc 2 1655 17 view .LVU8 + 48 0010 C160 str r1, [r0, #12] +1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } +1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 49 .loc 2 1657 1 view .LVU9 + 50 0012 7047 bx lr + 51 .LVL2: + 52 .L4: +1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrtemp = usartdiv & 0xFFF0U; + 53 .loc 2 1648 5 is_stmt 1 view .LVU10 + ARM GAS /tmp/ccci4zB8.s page 31 + + +1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrtemp = usartdiv & 0xFFF0U; + 54 .loc 2 1648 27 is_stmt 0 view .LVU11 + 55 0014 5A08 lsrs r2, r3, #1 + 56 .LVL3: +1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrtemp = usartdiv & 0xFFF0U; + 57 .loc 2 1648 27 view .LVU12 + 58 0016 02EB4102 add r2, r2, r1, lsl #1 + 59 001a B2FBF3F3 udiv r3, r2, r3 + 60 .LVL4: +1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + 61 .loc 2 1649 5 is_stmt 1 view .LVU13 +1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + 62 .loc 2 1649 13 is_stmt 0 view .LVU14 + 63 001e 4FF6F072 movw r2, #65520 + 64 0022 1A40 ands r2, r2, r3 + 65 .LVL5: +1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->BRR = brrtemp; + 66 .loc 2 1650 5 is_stmt 1 view .LVU15 +1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->BRR = brrtemp; + 67 .loc 2 1650 16 is_stmt 0 view .LVU16 + 68 0024 C3F34203 ubfx r3, r3, #1, #3 + 69 .LVL6: +1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** USARTx->BRR = brrtemp; + 70 .loc 2 1650 13 view .LVU17 + 71 0028 1343 orrs r3, r3, r2 + 72 .LVL7: +1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 73 .loc 2 1651 5 is_stmt 1 view .LVU18 +1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 74 .loc 2 1651 17 is_stmt 0 view .LVU19 + 75 002a C360 str r3, [r0, #12] + 76 002c 7047 bx lr + 77 .cfi_endproc + 78 .LFE215: + 80 .section .text.LL_USART_DeInit,"ax",%progbits + 81 .align 1 + 82 .global LL_USART_DeInit + 83 .syntax unified + 84 .thumb + 85 .thumb_func + 87 LL_USART_DeInit: + 88 .LVL8: + 89 .LFB542: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @file stm32f7xx_ll_usart.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @brief USART LL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * This software is licensed under terms that can be found in the LICENSE file + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * in the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + ARM GAS /tmp/ccci4zB8.s page 32 + + + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #if defined(USE_FULL_LL_DRIVER) + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Includes ------------------------------------------------------------------*/ + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #include "stm32f7xx_ll_usart.h" + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #include "stm32f7xx_ll_rcc.h" + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #include "stm32f7xx_ll_bus.h" + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #ifdef USE_FULL_ASSERT + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #include "stm32_assert.h" + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #else + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define assert_param(expr) ((void)0U) + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #endif /* USE_FULL_ASSERT */ + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** @addtogroup STM32F7xx_LL_Driver + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @{ + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \ + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** @addtogroup USART_LL + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @{ + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Private types -------------------------------------------------------------*/ + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Private variables ---------------------------------------------------------*/ + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Private constants ---------------------------------------------------------*/ + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** @addtogroup USART_LL_Private_Constants + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @{ + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Definition of default baudrate value used for USART initialisation */ + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define USART_DEFAULT_BAUDRATE (9600U) + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @} + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Private macros ------------------------------------------------------------*/ + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** @addtogroup USART_LL_Private_Macros + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @{ + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * divided by the smallest oversampling used on the USART (i.e. 8) */ + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 27000000U) + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** || ((__VALUE__) == LL_USART_DIRECTION_RX) \ + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** || ((__VALUE__) == LL_USART_DIRECTION_TX) \ + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + ARM GAS /tmp/ccci4zB8.s page 33 + + + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** || ((__VALUE__) == LL_USART_PARITY_EVEN) \ + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** || ((__VALUE__) == LL_USART_PARITY_ODD)) + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \ + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \ + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** || ((__VALUE__) == LL_USART_PHASE_2EDGE)) + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** || ((__VALUE__) == LL_USART_POLARITY_HIGH)) + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \ + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** || ((__VALUE__) == LL_USART_STOPBITS_1) \ + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** || ((__VALUE__) == LL_USART_STOPBITS_2)) + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @} + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Private function prototypes -----------------------------------------------*/ + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Exported functions --------------------------------------------------------*/ + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** @addtogroup USART_LL_Exported_Functions + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @{ + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** @addtogroup USART_LL_EF_Init + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @{ + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @brief De-initialize USART registers (Registers restored to their default values). + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @param USARTx USART Instance + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @retval An ErrorStatus enumeration value: + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * - SUCCESS: USART registers are de-initialized + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * - ERROR: USART registers are not de-initialized + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx) + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + ARM GAS /tmp/ccci4zB8.s page 34 + + + 90 .loc 1 128 1 is_stmt 1 view -0 + 91 .cfi_startproc + 92 @ args = 0, pretend = 0, frame = 0 + 93 @ frame_needed = 0, uses_anonymous_args = 0 + 94 @ link register save eliminated. + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** ErrorStatus status = SUCCESS; + 95 .loc 1 129 3 view .LVU21 + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Check the parameters */ + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** assert_param(IS_UART_INSTANCE(USARTx)); + 96 .loc 1 132 3 view .LVU22 + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** if (USARTx == USART1) + 97 .loc 1 134 3 view .LVU23 + 98 .loc 1 134 6 is_stmt 0 view .LVU24 + 99 0000 3C4B ldr r3, .L23 + 100 0002 9842 cmp r0, r3 + 101 0004 16D0 beq .L15 + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Force reset of USART clock */ + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1); + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Release reset of USART clock */ + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1); + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** else if (USARTx == USART2) + 102 .loc 1 142 8 is_stmt 1 view .LVU25 + 103 .loc 1 142 11 is_stmt 0 view .LVU26 + 104 0006 3C4B ldr r3, .L23+4 + 105 0008 9842 cmp r0, r3 + 106 000a 1FD0 beq .L16 + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Force reset of USART clock */ + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2); + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Release reset of USART clock */ + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2); + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** else if (USARTx == USART3) + 107 .loc 1 150 8 is_stmt 1 view .LVU27 + 108 .loc 1 150 11 is_stmt 0 view .LVU28 + 109 000c 3B4B ldr r3, .L23+8 + 110 000e 9842 cmp r0, r3 + 111 0010 28D0 beq .L17 + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Force reset of USART clock */ + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3); + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Release reset of USART clock */ + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3); + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** else if (USARTx == UART4) + 112 .loc 1 158 8 is_stmt 1 view .LVU29 + 113 .loc 1 158 11 is_stmt 0 view .LVU30 + 114 0012 3B4B ldr r3, .L23+12 + 115 0014 9842 cmp r0, r3 + 116 0016 31D0 beq .L18 + ARM GAS /tmp/ccci4zB8.s page 35 + + + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Force reset of UART clock */ + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4); + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Release reset of UART clock */ + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4); + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** else if (USARTx == UART5) + 117 .loc 1 166 8 is_stmt 1 view .LVU31 + 118 .loc 1 166 11 is_stmt 0 view .LVU32 + 119 0018 3A4B ldr r3, .L23+16 + 120 001a 9842 cmp r0, r3 + 121 001c 3AD0 beq .L19 + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Force reset of UART clock */ + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5); + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Release reset of UART clock */ + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5); + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** else if (USARTx == USART6) + 122 .loc 1 174 8 is_stmt 1 view .LVU33 + 123 .loc 1 174 11 is_stmt 0 view .LVU34 + 124 001e 3A4B ldr r3, .L23+20 + 125 0020 9842 cmp r0, r3 + 126 0022 43D0 beq .L20 + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Force reset of USART clock */ + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6); + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Release reset of USART clock */ + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6); + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** else if (USARTx == UART7) + 127 .loc 1 182 8 is_stmt 1 view .LVU35 + 128 .loc 1 182 11 is_stmt 0 view .LVU36 + 129 0024 394B ldr r3, .L23+24 + 130 0026 9842 cmp r0, r3 + 131 0028 4CD0 beq .L21 + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Force reset of UART clock */ + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7); + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Release reset of UART clock */ + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7); + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** else if (USARTx == UART8) + 132 .loc 1 190 8 is_stmt 1 view .LVU37 + 133 .loc 1 190 11 is_stmt 0 view .LVU38 + 134 002a 394B ldr r3, .L23+28 + 135 002c 9842 cmp r0, r3 + 136 002e 55D0 beq .L22 + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Force reset of UART clock */ + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8); + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Release reset of UART clock */ + ARM GAS /tmp/ccci4zB8.s page 36 + + + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8); + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** else + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** status = ERROR; + 137 .loc 1 200 12 view .LVU39 + 138 0030 0120 movs r0, #1 + 139 .LVL9: + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** return (status); + 140 .loc 1 203 3 is_stmt 1 view .LVU40 + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 141 .loc 1 204 1 is_stmt 0 view .LVU41 + 142 0032 7047 bx lr + 143 .LVL10: + 144 .L15: + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 145 .loc 1 137 5 is_stmt 1 view .LVU42 + 146 .LBB44: + 147 .LBI44: + 148 .file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @file stm32f7xx_ll_bus.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Header file of BUS LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @verbatim + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ##### RCC Limitations ##### + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ============================================================================== + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** A delay between an RCC peripheral clock enable and the effective peripheral + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** enabling should be taken into account in order to manage the peripheral read/write + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** from/to registers. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (+) This delay depends on the peripheral mapping. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (++) AHB & APB peripherals, 1 dummy read is necessary + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** [..] + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** Workarounds: + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** @endverbatim + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @attention + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * Copyright (c) 2017 STMicroelectronics. + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * All rights reserved. + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * This software is licensed under terms that can be found in the LICENSE file in + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * the root directory of this software component. + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** ****************************************************************************** + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + ARM GAS /tmp/ccci4zB8.s page 37 + + + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifndef __STM32F7xx_LL_BUS_H + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define __STM32F7xx_LL_BUS_H + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #ifdef __cplusplus + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** extern "C" { + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Includes ------------------------------------------------------------------*/ + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #include "stm32f7xx.h" + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @addtogroup STM32F7xx_LL_Driver + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC) + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL BUS + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private types -------------------------------------------------------------*/ + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private variables ---------------------------------------------------------*/ + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private constants ---------------------------------------------------------*/ + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Private macros ------------------------------------------------------------*/ + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported types ------------------------------------------------------------*/ + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported constants --------------------------------------------------------*/ + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOJ) + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOJ */ + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(GPIOK) + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* GPIOK */ + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DTCMRAM RCC_AHB1ENR_DTCMRAMEN + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DMA2D) + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DMA2D */ + ARM GAS /tmp/ccci4zB8.s page 38 + + + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(ETH) + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* ETH */ + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_AXI RCC_AHB1LPENR_AXILPEN + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DCMI) + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DCMI */ + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(JPEG) + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_JPEG RCC_AHB2ENR_JPEGEN + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* JPEG */ + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CRYP) + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CRYP */ + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(AES) + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* AES */ + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(HASH) + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* HASH */ + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN + ARM GAS /tmp/ccci4zB8.s page 39 + + + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPDIFRX) + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPDIFRX */ + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(I2C4) + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_I2C4 RCC_APB1ENR_I2C4EN + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* I2C4 */ + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN2) + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN2 */ + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CAN3) + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CAN3 */ + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(CEC) + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* CEC */ + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(RCC_APB1ENR_RTCEN) + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCEN + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* RCC_APB1ENR_RTCEN */ + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN + ARM GAS /tmp/ccci4zB8.s page 40 + + + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SDMMC2) + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SDMMC2 RCC_APB2ENR_SDMMC2EN + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SDMMC2 */ + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(SPI6) + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* SPI6 */ + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(LTDC) + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* LTDC */ + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DSI) + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DSI */ + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(DFSDM1_Channel0) + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* DFSDM1_Channel0 */ + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(MDIOS) + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_MDIO RCC_APB2ENR_MDIOEN + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* MDIOS */ + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #if defined(USB_HS_PHYC) + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_OTGPHYC RCC_APB2ENR_OTGPHYCEN + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #endif /* USB_HS_PHYC */ + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported macro ------------------------------------------------------------*/ + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Exported functions --------------------------------------------------------*/ + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB1 AHB1 + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB1 peripherals clock. + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n + ARM GAS /tmp/ccci4zB8.s page 41 + + + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_EnableClock\n + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1ENR, Periphs); + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB1 peripheral clock is enabled or not + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n + ARM GAS /tmp/ccci4zB8.s page 42 + + + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_IsEnabledClock\n + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_IsEnabledClock + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB1 peripherals clock. + ARM GAS /tmp/ccci4zB8.s page 43 + + + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_DisableClock\n + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_DisableClock + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1ENR, Periphs); + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + ARM GAS /tmp/ccci4zB8.s page 44 + + + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB1 peripherals reset. + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1RSTR, Periphs); + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB1 peripherals reset. + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n + ARM GAS /tmp/ccci4zB8.s page 45 + + + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1RSTR, Periphs); + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB1 peripheral clocks in low-power mode + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR AXILPEN LL_AHB1_GRP1_EnableClockLowPower\n + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n + ARM GAS /tmp/ccci4zB8.s page 46 + + + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_AXI + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB1LPENR, Periphs); + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB1 peripheral clocks in low-power mode + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n + ARM GAS /tmp/ccci4zB8.s page 47 + + + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR AXILPEN LL_AHB1_GRP1_DisableClockLowPower\n + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_AXI + 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF + 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 + 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) + 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB1LPENR, Periphs); + 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + ARM GAS /tmp/ccci4zB8.s page 48 + + + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB2 AHB2 + 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB2 peripherals clock. + 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n + 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_EnableClock\n + 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n + 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n + 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n + 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n + 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock + 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) + 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2ENR, Periphs); + 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB2 peripheral clock is enabled or not + 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n + 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_IsEnabledClock\n + 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n + 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n + 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n + 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n + 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock + 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + ARM GAS /tmp/ccci4zB8.s page 49 + + + 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) + 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); + 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB2 peripherals clock. + 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n + 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR JPEGEN LL_AHB2_GRP1_DisableClock\n + 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n + 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n + 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n + 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n + 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock + 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) + 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2ENR, Periphs); + 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB2 peripherals reset. + 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n + 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR JPEGRST LL_AHB2_GRP1_ForceReset\n + 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n + 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n + 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n + 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n + 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset + 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) + ARM GAS /tmp/ccci4zB8.s page 50 + + + 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2RSTR, Periphs); + 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB2 peripherals reset. + 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n + 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR JPEGRST LL_AHB2_GRP1_ReleaseReset\n + 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n + 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n + 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n + 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n + 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset + 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) + 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2RSTR, Periphs); + 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB2 peripheral clocks in low-power mode + 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n + 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n + 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower + 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) + 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB2LPENR, Periphs); + 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + ARM GAS /tmp/ccci4zB8.s page 51 + + + 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); + 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB2 peripheral clocks in low-power mode + 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n + 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_DisableClockLowPower\n + 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n + 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n + 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n + 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n + 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower + 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) + 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB2LPENR, Periphs); + 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_AHB3 AHB3 + 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ + 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB3 peripherals clock. + 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n + 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) + 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3ENR, Periphs); + 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); + 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + ARM GAS /tmp/ccci4zB8.s page 52 + + + 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if AHB3 peripheral clock is enabled or not + 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n + 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock + 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). + 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) + 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); + 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB3 peripherals clock. + 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n + 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock + 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) + 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3ENR, Periphs); + 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force AHB3 peripherals reset. + 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n + 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset + 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) + 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3RSTR, Periphs); + 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release AHB3 peripherals reset. + 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n + 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset + 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + ARM GAS /tmp/ccci4zB8.s page 53 + + + 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) + 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3RSTR, Periphs); + 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable AHB3 peripheral clocks in low-power mode + 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n + 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower + 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) + 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; + 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->AHB3LPENR, Periphs); + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ + 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); + 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; + 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable AHB3 peripheral clocks in low-power mode + 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n + 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower + 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: + 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * + 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. + 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) + 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->AHB3LPENR, Periphs); + 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** + 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} + 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ + 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB1 APB1 + 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ +1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB1 peripherals clock. +1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + ARM GAS /tmp/ccci4zB8.s page 54 + + +1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n +1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n +1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n +1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n +1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n +1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n +1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n +1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n +1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n +1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n +1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n +1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n +1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n +1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n +1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n +1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n +1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n +1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n +1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n +1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n +1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_EnableClock\n +1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n +1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n +1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n +1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n +1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n +1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n +1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n +1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_EnableClock +1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + ARM GAS /tmp/ccci4zB8.s page 55 + + +1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; +1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1ENR, Periphs); +1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1ENR, Periphs); +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; +1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if APB1 peripheral clock is enabled or not +1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n +1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n +1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n +1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n +1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n +1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n +1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n +1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n +1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n +1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n +1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n +1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n +1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n +1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n +1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n +1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n +1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n +1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n +1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n +1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n +1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n +1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_IsEnabledClock\n +1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n +1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n +1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n +1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n +1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n +1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n +1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n +1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n +1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_IsEnabledClock +1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + ARM GAS /tmp/ccci4zB8.s page 56 + + +1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). +1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); +1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable APB1 peripherals clock. +1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n +1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n +1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n +1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n +1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n +1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n +1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n +1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n +1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n +1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n +1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n +1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n +1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n +1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n +1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n +1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n +1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n +1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n +1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n +1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + ARM GAS /tmp/ccci4zB8.s page 57 + + +1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n +1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR I2C4EN LL_APB1_GRP1_DisableClock\n +1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n +1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n +1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n +1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n +1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n +1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n +1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n +1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n +1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1ENR RTCEN LL_APB1_GRP1_DisableClock +1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1ENR, Periphs); +1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force APB1 peripherals reset. +1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n +1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n +1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n + ARM GAS /tmp/ccci4zB8.s page 58 + + +1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n +1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n +1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n +1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n +1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n +1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n +1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n +1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n +1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n +1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n +1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n +1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n +1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n +1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n +1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n +1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n +1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n +1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n +1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C4RST LL_APB1_GRP1_ForceReset\n +1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n +1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n +1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n +1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n +1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n +1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n +1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n +1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset +1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + ARM GAS /tmp/ccci4zB8.s page 59 + + +1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1RSTR, Periphs); +1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release APB1 peripherals reset. +1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n +1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n +1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n +1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n +1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n +1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n +1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n +1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n +1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n +1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n +1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n +1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n +1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n +1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n +1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n +1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n +1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n +1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n +1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n +1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n +1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR I2C4RST LL_APB1_GRP1_ReleaseReset\n +1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n +1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n +1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n +1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n +1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n +1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n +1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n +1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset +1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + ARM GAS /tmp/ccci4zB8.s page 60 + + +1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1RSTR, Periphs); +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB1 peripheral clocks in low-power mode +1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n +1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n +1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n +1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n +1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n +1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n +1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n +1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n +1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n +1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n +1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n +1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n +1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n +1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C4LPEN LL_APB1_GRP1_EnableClockLowPower\n +1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n +1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n +1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n +1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n +1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n +1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n +1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n +1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n + ARM GAS /tmp/ccci4zB8.s page 61 + + +1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR RTCLPEN LL_APB1_GRP1_EnableClockLowPower +1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) +1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; +1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB1LPENR, Periphs); +1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ +1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); +1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; +1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable APB1 peripheral clocks in low-power mode +1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n +1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n +1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n +1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n +1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n +1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n +1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n + ARM GAS /tmp/ccci4zB8.s page 62 + + +1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n +1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n +1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n +1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n +1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n +1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n +1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR I2C4LPEN LL_APB1_GRP1_DisableClockLowPower\n +1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n +1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n +1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n +1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n +1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n +1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n +1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n +1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n +1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB1LPENR RTCLPEN LL_APB1_GRP1_DisableClockLowPower +1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 +1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 +1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 +1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 +1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 +1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 +1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 +1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 +1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 +1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 +1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_WWDG +1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 +1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 +1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) +1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART2 +1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_USART3 +1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART4 +1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART5 +1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 +1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 +1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 +1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 +1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) +1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) +1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) +1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_PWR +1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 +1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART7 +1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_UART8 +1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) +1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None + ARM GAS /tmp/ccci4zB8.s page 63 + + +1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) +1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB1LPENR, Periphs); +1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @} +1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** @defgroup BUS_LL_EF_APB2 APB2 +1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @{ +1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Enable APB2 peripherals clock. +1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n +1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n +1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n +1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n +1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n +1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n +1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n +1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n +1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC2EN LL_APB2_GRP1_EnableClock\n +1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n +1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n +1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n +1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n +1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n +1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n +1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n +1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n +1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n +1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n +1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n +1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n +1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n +1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR MDIOEN LL_APB2_GRP1_EnableClock\n +1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR OTGPHYCEN LL_APB2_GRP1_EnableClock +1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 +1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 +1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 +1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 +1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 +1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 +1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 +1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 +1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) +1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 +1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 +1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG +1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 +1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 +1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 +1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + ARM GAS /tmp/ccci4zB8.s page 64 + + +1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) +1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 +1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 +1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) +1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) +1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) +1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) +1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) +1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __IO uint32_t tmpreg; +1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2ENR, Periphs); +1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /* Delay after an RCC peripheral clock enabling */ +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** tmpreg = READ_BIT(RCC->APB2ENR, Periphs); +1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** (void)tmpreg; +1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Check if APB2 peripheral clock is enabled or not +1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n +1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n +1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n +1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n +1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n +1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n +1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n +1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n +1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC2EN LL_APB2_GRP1_IsEnabledClock\n +1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n +1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n +1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n +1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n +1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n +1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n +1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n +1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n +1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n +1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n +1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n +1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n +1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n +1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR MDIOEN LL_APB2_GRP1_IsEnabledClock\n +1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR OTGPHYCEN LL_APB2_GRP1_IsEnabledClock +1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 +1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 +1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 +1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 +1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 +1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 +1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 +1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 +1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) + ARM GAS /tmp/ccci4zB8.s page 65 + + +1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 +1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 +1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG +1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 +1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 +1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 +1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 +1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) +1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 +1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 +1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) +1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) +1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) +1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) +1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) +1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval State of Periphs (1 or 0). +1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); +1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Disable APB2 peripherals clock. +1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n +1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n +1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n +1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n +1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n +1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n +1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n +1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n +1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SDMMC2EN LL_APB2_GRP1_DisableClock\n +1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n +1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n +1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n +1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n +1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n +1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n +1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n +1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n +1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n +1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n +1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n +1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n +1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n +1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR MDIOEN LL_APB2_GRP1_DisableClock\n +1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2ENR OTGPHYCEN LL_APB2_GRP1_DisableClock +1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 +1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 +1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 +1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 +1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 +1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 + ARM GAS /tmp/ccci4zB8.s page 66 + + +1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 +1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 +1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) +1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 +1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 +1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG +1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 +1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 +1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 +1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 +1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) +1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 +1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 +1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) +1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) +1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) +1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) +1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) +1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB2ENR, Periphs); +1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Force APB2 peripherals reset. +1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n +1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n +1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n +1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n +1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n +1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n +1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SDMMC2RST LL_APB2_GRP1_ForceReset\n +1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n +1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n +1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n +1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n +1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n +1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n +1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n +1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n +1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n +1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n +1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n +1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n +1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n +1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR MDIORST LL_APB2_GRP1_ForceReset\n +1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ForceReset +1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ALL +1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 +1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 +1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 +1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + ARM GAS /tmp/ccci4zB8.s page 67 + + +1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC +1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 +1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) +1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 +1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 +1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG +1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 +1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 +1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 +1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 +1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) +1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 +1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 +1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) +1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) +1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) +1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) +1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) +1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) + 149 .loc 3 1768 22 view .LVU43 + 150 .LBB45: +1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** SET_BIT(RCC->APB2RSTR, Periphs); + 151 .loc 3 1770 3 view .LVU44 + 152 0034 03F59433 add r3, r3, #75776 + 153 0038 5A6A ldr r2, [r3, #36] + 154 003a 42F01002 orr r2, r2, #16 + 155 003e 5A62 str r2, [r3, #36] + 156 .LVL11: + 157 .loc 3 1770 3 is_stmt 0 view .LVU45 + 158 .LBE45: + 159 .LBE44: + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 160 .loc 1 140 5 is_stmt 1 view .LVU46 + 161 .LBB46: + 162 .LBI46: +1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } +1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** +1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** /** +1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @brief Release APB2 peripherals reset. +1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n +1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n +1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n +1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n +1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n +1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n +1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SDMMC2RST LL_APB2_GRP1_ReleaseReset\n +1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n +1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n +1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n +1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n +1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n +1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n + ARM GAS /tmp/ccci4zB8.s page 68 + + +1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n +1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n +1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n +1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n +1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n +1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n +1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n +1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR MDIORST LL_APB2_GRP1_ReleaseReset\n +1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ReleaseReset +1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @param Periphs This parameter can be a combination of the following values: +1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ALL +1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 +1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 +1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART1 +1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_USART6 +1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_ADC +1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 +1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) +1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 +1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 +1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG +1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 +1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 +1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 +1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 +1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) +1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 +1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 +1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) +1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) +1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) +1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) +1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) +1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * +1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * (*) value not defined in all devices. +1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** * @retval None +1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** */ +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) + 163 .loc 3 1825 22 view .LVU47 + 164 .LBB47: +1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** CLEAR_BIT(RCC->APB2RSTR, Periphs); + 165 .loc 3 1827 3 view .LVU48 + 166 0040 5A6A ldr r2, [r3, #36] + 167 0042 22F01002 bic r2, r2, #16 + 168 0046 5A62 str r2, [r3, #36] + 169 .LVL12: + 170 .loc 3 1827 3 is_stmt 0 view .LVU49 + 171 .LBE47: + 172 .LBE46: + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 173 .loc 1 129 15 view .LVU50 + 174 0048 0020 movs r0, #0 + 175 .LVL13: + 176 .LBB49: + 177 .LBB48: +1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + ARM GAS /tmp/ccci4zB8.s page 69 + + + 178 .loc 3 1828 1 view .LVU51 + 179 004a 7047 bx lr + 180 .LVL14: + 181 .L16: + 182 .loc 3 1828 1 view .LVU52 + 183 .LBE48: + 184 .LBE49: + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 185 .loc 1 145 5 is_stmt 1 view .LVU53 + 186 .LBB50: + 187 .LBI50: +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 188 .loc 3 1295 22 view .LVU54 + 189 .LBB51: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 190 .loc 3 1297 3 view .LVU55 + 191 004c 03F5FA33 add r3, r3, #128000 + 192 0050 1A6A ldr r2, [r3, #32] + 193 0052 42F40032 orr r2, r2, #131072 + 194 0056 1A62 str r2, [r3, #32] + 195 .LVL15: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 196 .loc 3 1297 3 is_stmt 0 view .LVU56 + 197 .LBE51: + 198 .LBE50: + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 199 .loc 1 148 5 is_stmt 1 view .LVU57 + 200 .LBB52: + 201 .LBI52: +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 202 .loc 3 1367 22 view .LVU58 + 203 .LBB53: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 204 .loc 3 1369 3 view .LVU59 + 205 0058 1A6A ldr r2, [r3, #32] + 206 005a 22F40032 bic r2, r2, #131072 + 207 005e 1A62 str r2, [r3, #32] + 208 .LVL16: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 209 .loc 3 1369 3 is_stmt 0 view .LVU60 + 210 .LBE53: + 211 .LBE52: + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 212 .loc 1 129 15 view .LVU61 + 213 0060 0020 movs r0, #0 + 214 .LVL17: + 215 .LBB55: + 216 .LBB54: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 217 .loc 3 1370 1 view .LVU62 + 218 0062 7047 bx lr + 219 .LVL18: + 220 .L17: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 221 .loc 3 1370 1 view .LVU63 + 222 .LBE54: + 223 .LBE55: + ARM GAS /tmp/ccci4zB8.s page 70 + + + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 224 .loc 1 153 5 is_stmt 1 view .LVU64 + 225 .LBB56: + 226 .LBI56: +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 227 .loc 3 1295 22 view .LVU65 + 228 .LBB57: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 229 .loc 3 1297 3 view .LVU66 + 230 0064 03F5F833 add r3, r3, #126976 + 231 0068 1A6A ldr r2, [r3, #32] + 232 006a 42F48022 orr r2, r2, #262144 + 233 006e 1A62 str r2, [r3, #32] + 234 .LVL19: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 235 .loc 3 1297 3 is_stmt 0 view .LVU67 + 236 .LBE57: + 237 .LBE56: + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 238 .loc 1 156 5 is_stmt 1 view .LVU68 + 239 .LBB58: + 240 .LBI58: +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 241 .loc 3 1367 22 view .LVU69 + 242 .LBB59: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 243 .loc 3 1369 3 view .LVU70 + 244 0070 1A6A ldr r2, [r3, #32] + 245 0072 22F48022 bic r2, r2, #262144 + 246 0076 1A62 str r2, [r3, #32] + 247 .LVL20: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 248 .loc 3 1369 3 is_stmt 0 view .LVU71 + 249 .LBE59: + 250 .LBE58: + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 251 .loc 1 129 15 view .LVU72 + 252 0078 0020 movs r0, #0 + 253 .LVL21: + 254 .LBB61: + 255 .LBB60: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 256 .loc 3 1370 1 view .LVU73 + 257 007a 7047 bx lr + 258 .LVL22: + 259 .L18: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 260 .loc 3 1370 1 view .LVU74 + 261 .LBE60: + 262 .LBE61: + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 263 .loc 1 161 5 is_stmt 1 view .LVU75 + 264 .LBB62: + 265 .LBI62: +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 266 .loc 3 1295 22 view .LVU76 + 267 .LBB63: + ARM GAS /tmp/ccci4zB8.s page 71 + + +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 268 .loc 3 1297 3 view .LVU77 + 269 007c 03F5F633 add r3, r3, #125952 + 270 0080 1A6A ldr r2, [r3, #32] + 271 0082 42F40022 orr r2, r2, #524288 + 272 0086 1A62 str r2, [r3, #32] + 273 .LVL23: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 274 .loc 3 1297 3 is_stmt 0 view .LVU78 + 275 .LBE63: + 276 .LBE62: + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 277 .loc 1 164 5 is_stmt 1 view .LVU79 + 278 .LBB64: + 279 .LBI64: +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 280 .loc 3 1367 22 view .LVU80 + 281 .LBB65: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 282 .loc 3 1369 3 view .LVU81 + 283 0088 1A6A ldr r2, [r3, #32] + 284 008a 22F40022 bic r2, r2, #524288 + 285 008e 1A62 str r2, [r3, #32] + 286 .LVL24: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 287 .loc 3 1369 3 is_stmt 0 view .LVU82 + 288 .LBE65: + 289 .LBE64: + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 290 .loc 1 129 15 view .LVU83 + 291 0090 0020 movs r0, #0 + 292 .LVL25: + 293 .LBB67: + 294 .LBB66: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 295 .loc 3 1370 1 view .LVU84 + 296 0092 7047 bx lr + 297 .LVL26: + 298 .L19: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 299 .loc 3 1370 1 view .LVU85 + 300 .LBE66: + 301 .LBE67: + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 302 .loc 1 169 5 is_stmt 1 view .LVU86 + 303 .LBB68: + 304 .LBI68: +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 305 .loc 3 1295 22 view .LVU87 + 306 .LBB69: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 307 .loc 3 1297 3 view .LVU88 + 308 0094 03F5F433 add r3, r3, #124928 + 309 0098 1A6A ldr r2, [r3, #32] + 310 009a 42F48012 orr r2, r2, #1048576 + 311 009e 1A62 str r2, [r3, #32] + 312 .LVL27: + ARM GAS /tmp/ccci4zB8.s page 72 + + +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 313 .loc 3 1297 3 is_stmt 0 view .LVU89 + 314 .LBE69: + 315 .LBE68: + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 316 .loc 1 172 5 is_stmt 1 view .LVU90 + 317 .LBB70: + 318 .LBI70: +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 319 .loc 3 1367 22 view .LVU91 + 320 .LBB71: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 321 .loc 3 1369 3 view .LVU92 + 322 00a0 1A6A ldr r2, [r3, #32] + 323 00a2 22F48012 bic r2, r2, #1048576 + 324 00a6 1A62 str r2, [r3, #32] + 325 .LVL28: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 326 .loc 3 1369 3 is_stmt 0 view .LVU93 + 327 .LBE71: + 328 .LBE70: + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 329 .loc 1 129 15 view .LVU94 + 330 00a8 0020 movs r0, #0 + 331 .LVL29: + 332 .LBB73: + 333 .LBB72: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 334 .loc 3 1370 1 view .LVU95 + 335 00aa 7047 bx lr + 336 .LVL30: + 337 .L20: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 338 .loc 3 1370 1 view .LVU96 + 339 .LBE72: + 340 .LBE73: + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 341 .loc 1 177 5 is_stmt 1 view .LVU97 + 342 .LBB74: + 343 .LBI74: +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 344 .loc 3 1768 22 view .LVU98 + 345 .LBB75: +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 346 .loc 3 1770 3 view .LVU99 + 347 00ac 03F59233 add r3, r3, #74752 + 348 00b0 5A6A ldr r2, [r3, #36] + 349 00b2 42F02002 orr r2, r2, #32 + 350 00b6 5A62 str r2, [r3, #36] + 351 .LVL31: +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 352 .loc 3 1770 3 is_stmt 0 view .LVU100 + 353 .LBE75: + 354 .LBE74: + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 355 .loc 1 180 5 is_stmt 1 view .LVU101 + 356 .LBB76: + ARM GAS /tmp/ccci4zB8.s page 73 + + + 357 .LBI76: +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 358 .loc 3 1825 22 view .LVU102 + 359 .LBB77: +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 360 .loc 3 1827 3 view .LVU103 + 361 00b8 5A6A ldr r2, [r3, #36] + 362 00ba 22F02002 bic r2, r2, #32 + 363 00be 5A62 str r2, [r3, #36] + 364 .LVL32: +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 365 .loc 3 1827 3 is_stmt 0 view .LVU104 + 366 .LBE77: + 367 .LBE76: + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 368 .loc 1 129 15 view .LVU105 + 369 00c0 0020 movs r0, #0 + 370 .LVL33: + 371 .LBB79: + 372 .LBB78: + 373 .loc 3 1828 1 view .LVU106 + 374 00c2 7047 bx lr + 375 .LVL34: + 376 .L21: + 377 .loc 3 1828 1 view .LVU107 + 378 .LBE78: + 379 .LBE79: + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 380 .loc 1 185 5 is_stmt 1 view .LVU108 + 381 .LBB80: + 382 .LBI80: +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 383 .loc 3 1295 22 view .LVU109 + 384 .LBB81: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 385 .loc 3 1297 3 view .LVU110 + 386 00c4 03F5E033 add r3, r3, #114688 + 387 00c8 1A6A ldr r2, [r3, #32] + 388 00ca 42F08042 orr r2, r2, #1073741824 + 389 00ce 1A62 str r2, [r3, #32] + 390 .LVL35: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 391 .loc 3 1297 3 is_stmt 0 view .LVU111 + 392 .LBE81: + 393 .LBE80: + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 394 .loc 1 188 5 is_stmt 1 view .LVU112 + 395 .LBB82: + 396 .LBI82: +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 397 .loc 3 1367 22 view .LVU113 + 398 .LBB83: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 399 .loc 3 1369 3 view .LVU114 + 400 00d0 1A6A ldr r2, [r3, #32] + 401 00d2 22F08042 bic r2, r2, #1073741824 + 402 00d6 1A62 str r2, [r3, #32] + ARM GAS /tmp/ccci4zB8.s page 74 + + + 403 .LVL36: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 404 .loc 3 1369 3 is_stmt 0 view .LVU115 + 405 .LBE83: + 406 .LBE82: + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 407 .loc 1 129 15 view .LVU116 + 408 00d8 0020 movs r0, #0 + 409 .LVL37: + 410 .LBB85: + 411 .LBB84: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 412 .loc 3 1370 1 view .LVU117 + 413 00da 7047 bx lr + 414 .LVL38: + 415 .L22: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 416 .loc 3 1370 1 view .LVU118 + 417 .LBE84: + 418 .LBE85: + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 419 .loc 1 193 5 is_stmt 1 view .LVU119 + 420 .LBB86: + 421 .LBI86: +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 422 .loc 3 1295 22 view .LVU120 + 423 .LBB87: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 424 .loc 3 1297 3 view .LVU121 + 425 00dc 03F5DE33 add r3, r3, #113664 + 426 00e0 1A6A ldr r2, [r3, #32] + 427 00e2 42F00042 orr r2, r2, #-2147483648 + 428 00e6 1A62 str r2, [r3, #32] + 429 .LVL39: +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 430 .loc 3 1297 3 is_stmt 0 view .LVU122 + 431 .LBE87: + 432 .LBE86: + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 433 .loc 1 196 5 is_stmt 1 view .LVU123 + 434 .LBB88: + 435 .LBI88: +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** { + 436 .loc 3 1367 22 view .LVU124 + 437 .LBB89: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 438 .loc 3 1369 3 view .LVU125 + 439 00e8 1A6A ldr r2, [r3, #32] + 440 00ea 22F00042 bic r2, r2, #-2147483648 + 441 00ee 1A62 str r2, [r3, #32] + 442 .LVL40: +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** } + 443 .loc 3 1369 3 is_stmt 0 view .LVU126 + 444 .LBE89: + 445 .LBE88: + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 446 .loc 1 129 15 view .LVU127 + ARM GAS /tmp/ccci4zB8.s page 75 + + + 447 00f0 0020 movs r0, #0 + 448 .LVL41: + 449 .LBB91: + 450 .LBB90: +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h **** + 451 .loc 3 1370 1 view .LVU128 + 452 00f2 7047 bx lr + 453 .L24: + 454 .align 2 + 455 .L23: + 456 00f4 00100140 .word 1073811456 + 457 00f8 00440040 .word 1073759232 + 458 00fc 00480040 .word 1073760256 + 459 0100 004C0040 .word 1073761280 + 460 0104 00500040 .word 1073762304 + 461 0108 00140140 .word 1073812480 + 462 010c 00780040 .word 1073772544 + 463 0110 007C0040 .word 1073773568 + 464 .LBE90: + 465 .LBE91: + 466 .cfi_endproc + 467 .LFE542: + 469 .section .text.LL_USART_Init,"ax",%progbits + 470 .align 1 + 471 .global LL_USART_Init + 472 .syntax unified + 473 .thumb + 474 .thumb_func + 476 LL_USART_Init: + 477 .LVL42: + 478 .LFB543: + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @brief Initialize USART registers according to the specified + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * parameters in USART_InitStruct. + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @note As some bits in USART configuration registers can only be written when + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled sta + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * this function. Otherwise, ERROR result will be returned. + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different f + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @param USARTx USART Instance + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * that contains the configuration information for the specified USART peripheral. + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @retval An ErrorStatus enumeration value: + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * - SUCCESS: USART registers are initialized according to USART_InitStruct content + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * - ERROR: Problem occurred during USART Registers initialization + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct) + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 479 .loc 1 221 1 is_stmt 1 view -0 + 480 .cfi_startproc + 481 @ args = 0, pretend = 0, frame = 0 + 482 @ frame_needed = 0, uses_anonymous_args = 0 + 483 .loc 1 221 1 is_stmt 0 view .LVU130 + 484 0000 38B5 push {r3, r4, r5, lr} + 485 .LCFI0: + 486 .cfi_def_cfa_offset 16 + 487 .cfi_offset 3, -16 + ARM GAS /tmp/ccci4zB8.s page 76 + + + 488 .cfi_offset 4, -12 + 489 .cfi_offset 5, -8 + 490 .cfi_offset 14, -4 + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** ErrorStatus status = ERROR; + 491 .loc 1 222 3 is_stmt 1 view .LVU131 + 492 .LVL43: + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + 493 .loc 1 223 3 view .LVU132 + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Check the parameters */ + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** assert_param(IS_UART_INSTANCE(USARTx)); + 494 .loc 1 226 3 view .LVU133 + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate)); + 495 .loc 1 227 3 view .LVU134 + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth)); + 496 .loc 1 228 3 view .LVU135 + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits)); + 497 .loc 1 229 3 view .LVU136 + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity)); + 498 .loc 1 230 3 view .LVU137 + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection)); + 499 .loc 1 231 3 view .LVU138 + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl)); + 500 .loc 1 232 3 view .LVU139 + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling)); + 501 .loc 1 233 3 view .LVU140 + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* USART needs to be in disabled state, in order to be able to configure some bits in + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** CRx registers */ + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** if (LL_USART_IsEnabled(USARTx) == 0U) + 502 .loc 1 237 3 view .LVU141 + 503 .LBB92: + 504 .LBI92: + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 505 .loc 2 585 26 view .LVU142 + 506 .LBB93: + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 507 .loc 2 587 3 view .LVU143 + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 508 .loc 2 587 12 is_stmt 0 view .LVU144 + 509 0002 0368 ldr r3, [r0] + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 510 .loc 2 587 73 view .LVU145 + 511 0004 13F0010F tst r3, #1 + 512 0008 62D1 bne .L35 + 513 000a 0446 mov r4, r0 + 514 000c 0D46 mov r5, r1 + 515 .LVL44: + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 516 .loc 2 587 73 view .LVU146 + 517 .LBE93: + 518 .LBE92: + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /*---------------------------- USART CR1 Configuration --------------------- + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity + ARM GAS /tmp/ccci4zB8.s page 77 + + + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->Transfe + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value. + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** MODIFY_REG(USARTx->CR1, + 519 .loc 1 246 5 is_stmt 1 view .LVU147 + 520 000e 0368 ldr r3, [r0] + 521 0010 314A ldr r2, .L49 + 522 0012 1A40 ands r2, r2, r3 + 523 0014 4B68 ldr r3, [r1, #4] + 524 0016 C968 ldr r1, [r1, #12] + 525 .LVL45: + 526 .loc 1 246 5 is_stmt 0 view .LVU148 + 527 0018 0B43 orrs r3, r3, r1 + 528 001a 2969 ldr r1, [r5, #16] + 529 001c 0B43 orrs r3, r3, r1 + 530 001e A969 ldr r1, [r5, #24] + 531 0020 0B43 orrs r3, r3, r1 + 532 0022 1A43 orrs r2, r2, r3 + 533 0024 0260 str r2, [r0] + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** (USART_InitStruct->DataWidth | USART_InitStruct->Parity | + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling)); + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /*---------------------------- USART CR2 Configuration --------------------- + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * Configure USARTx CR2 (Stop bits) with parameters: + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value. + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit(). + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits); + 534 .loc 1 257 5 is_stmt 1 view .LVU149 + 535 .loc 1 257 56 is_stmt 0 view .LVU150 + 536 0026 AB68 ldr r3, [r5, #8] + 537 .LVL46: + 538 .LBB94: + 539 .LBI94: +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 540 .loc 2 1073 22 is_stmt 1 view .LVU151 + 541 .LBB95: +1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 542 .loc 2 1075 3 view .LVU152 + 543 0028 4268 ldr r2, [r0, #4] + 544 002a 22F44052 bic r2, r2, #12288 + 545 002e 1343 orrs r3, r3, r2 + 546 .LVL47: +1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 547 .loc 2 1075 3 is_stmt 0 view .LVU153 + 548 0030 4360 str r3, [r0, #4] + 549 .LVL48: +1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 550 .loc 2 1075 3 view .LVU154 + 551 .LBE95: + 552 .LBE94: + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /*---------------------------- USART CR3 Configuration --------------------- + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * Configure USARTx CR3 (Hardware Flow Control) with parameters: + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to + ARM GAS /tmp/ccci4zB8.s page 78 + + + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * USART_InitStruct->HardwareFlowControl value. + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl); + 553 .loc 1 264 5 is_stmt 1 view .LVU155 + 554 .loc 1 264 52 is_stmt 0 view .LVU156 + 555 0032 6B69 ldr r3, [r5, #20] + 556 .LVL49: + 557 .LBB96: + 558 .LBI96: +1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 559 .loc 2 1498 22 is_stmt 1 view .LVU157 + 560 .LBB97: +1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 561 .loc 2 1500 3 view .LVU158 + 562 0034 8268 ldr r2, [r0, #8] + 563 0036 22F44072 bic r2, r2, #768 + 564 003a 1343 orrs r3, r3, r2 + 565 .LVL50: +1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 566 .loc 2 1500 3 is_stmt 0 view .LVU159 + 567 003c 8360 str r3, [r0, #8] + 568 .LVL51: +1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 569 .loc 2 1500 3 view .LVU160 + 570 .LBE97: + 571 .LBE96: + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /*---------------------------- USART BRR Configuration --------------------- + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * Retrieve Clock frequency used for USART Peripheral + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** if (USARTx == USART1) + 572 .loc 1 269 5 is_stmt 1 view .LVU161 + 573 .loc 1 269 8 is_stmt 0 view .LVU162 + 574 003e 274B ldr r3, .L49+4 + 575 0040 9842 cmp r0, r3 + 576 0042 16D0 beq .L40 + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE); + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** else if (USARTx == USART2) + 577 .loc 1 273 10 is_stmt 1 view .LVU163 + 578 .loc 1 273 13 is_stmt 0 view .LVU164 + 579 0044 264B ldr r3, .L49+8 + 580 0046 9842 cmp r0, r3 + 581 0048 1BD0 beq .L41 + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE); + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** else if (USARTx == USART3) + 582 .loc 1 277 10 is_stmt 1 view .LVU165 + 583 .loc 1 277 13 is_stmt 0 view .LVU166 + 584 004a 264B ldr r3, .L49+12 + 585 004c 9842 cmp r0, r3 + 586 004e 1CD0 beq .L42 + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE); + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + ARM GAS /tmp/ccci4zB8.s page 79 + + + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** else if (USARTx == UART4) + 587 .loc 1 281 10 is_stmt 1 view .LVU167 + 588 .loc 1 281 13 is_stmt 0 view .LVU168 + 589 0050 254B ldr r3, .L49+16 + 590 0052 9842 cmp r0, r3 + 591 0054 1DD0 beq .L43 + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE); + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** else if (USARTx == UART5) + 592 .loc 1 285 10 is_stmt 1 view .LVU169 + 593 .loc 1 285 13 is_stmt 0 view .LVU170 + 594 0056 254B ldr r3, .L49+20 + 595 0058 9842 cmp r0, r3 + 596 005a 1ED0 beq .L44 + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE); + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** else if (USARTx == USART6) + 597 .loc 1 289 10 is_stmt 1 view .LVU171 + 598 .loc 1 289 13 is_stmt 0 view .LVU172 + 599 005c 244B ldr r3, .L49+24 + 600 005e 9842 cmp r0, r3 + 601 0060 20D0 beq .L45 + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART6_CLKSOURCE); + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** else if (USARTx == UART7) + 602 .loc 1 293 10 is_stmt 1 view .LVU173 + 603 .loc 1 293 13 is_stmt 0 view .LVU174 + 604 0062 244B ldr r3, .L49+28 + 605 0064 9842 cmp r0, r3 + 606 0066 22D0 beq .L46 + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART7_CLKSOURCE); + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** else if (USARTx == UART8) + 607 .loc 1 297 10 is_stmt 1 view .LVU175 + 608 .loc 1 297 13 is_stmt 0 view .LVU176 + 609 0068 234B ldr r3, .L49+32 + 610 006a 9842 cmp r0, r3 + 611 006c 24D0 beq .L47 + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + 612 .loc 1 222 15 view .LVU177 + 613 006e 0120 movs r0, #1 + 614 .LVL52: + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + 615 .loc 1 222 15 view .LVU178 + 616 0070 2FE0 b .L26 + 617 .LVL53: + 618 .L40: + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 619 .loc 1 271 7 is_stmt 1 view .LVU179 + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 620 .loc 1 271 19 is_stmt 0 view .LVU180 + 621 0072 0320 movs r0, #3 + 622 .LVL54: + ARM GAS /tmp/ccci4zB8.s page 80 + + + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 623 .loc 1 271 19 view .LVU181 + 624 0074 FFF7FEFF bl LL_RCC_GetUSARTClockFreq + 625 .LVL55: + 626 .L28: + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART8_CLKSOURCE); + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** else + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Nothing to do, as error code is already assigned to ERROR value */ + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 627 .loc 1 304 5 is_stmt 1 view .LVU182 + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Configure the USART Baud Rate : + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** - valid baud rate value (different from 0) is required + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** - Peripheral clock as returned by RCC service, should be valid (different from 0). + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO) + 628 .loc 1 310 5 view .LVU183 + 629 .loc 1 310 8 is_stmt 0 view .LVU184 + 630 0078 60B3 cbz r0, .L37 + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** && (USART_InitStruct->BaudRate != 0U)) + 631 .loc 1 311 29 view .LVU185 + 632 007a 2B68 ldr r3, [r5] + 633 .loc 1 311 9 view .LVU186 + 634 007c 0BBB cbnz r3, .L48 + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + 635 .loc 1 222 15 view .LVU187 + 636 007e 0120 movs r0, #1 + 637 .LVL56: + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + 638 .loc 1 222 15 view .LVU188 + 639 0080 27E0 b .L26 + 640 .LVL57: + 641 .L41: + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 642 .loc 1 275 7 is_stmt 1 view .LVU189 + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 643 .loc 1 275 19 is_stmt 0 view .LVU190 + 644 0082 0C20 movs r0, #12 + 645 .LVL58: + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 646 .loc 1 275 19 view .LVU191 + 647 0084 FFF7FEFF bl LL_RCC_GetUSARTClockFreq + 648 .LVL59: + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 649 .loc 1 275 19 view .LVU192 + 650 0088 F6E7 b .L28 + 651 .LVL60: + 652 .L42: + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 653 .loc 1 279 7 is_stmt 1 view .LVU193 + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 654 .loc 1 279 19 is_stmt 0 view .LVU194 + 655 008a 3020 movs r0, #48 + 656 .LVL61: + ARM GAS /tmp/ccci4zB8.s page 81 + + + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 657 .loc 1 279 19 view .LVU195 + 658 008c FFF7FEFF bl LL_RCC_GetUSARTClockFreq + 659 .LVL62: + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 660 .loc 1 279 19 view .LVU196 + 661 0090 F2E7 b .L28 + 662 .LVL63: + 663 .L43: + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 664 .loc 1 283 7 is_stmt 1 view .LVU197 + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 665 .loc 1 283 19 is_stmt 0 view .LVU198 + 666 0092 C020 movs r0, #192 + 667 .LVL64: + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 668 .loc 1 283 19 view .LVU199 + 669 0094 FFF7FEFF bl LL_RCC_GetUARTClockFreq + 670 .LVL65: + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 671 .loc 1 283 19 view .LVU200 + 672 0098 EEE7 b .L28 + 673 .LVL66: + 674 .L44: + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 675 .loc 1 287 7 is_stmt 1 view .LVU201 + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 676 .loc 1 287 19 is_stmt 0 view .LVU202 + 677 009a 4FF44070 mov r0, #768 + 678 .LVL67: + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 679 .loc 1 287 19 view .LVU203 + 680 009e FFF7FEFF bl LL_RCC_GetUARTClockFreq + 681 .LVL68: + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 682 .loc 1 287 19 view .LVU204 + 683 00a2 E9E7 b .L28 + 684 .LVL69: + 685 .L45: + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 686 .loc 1 291 7 is_stmt 1 view .LVU205 + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 687 .loc 1 291 19 is_stmt 0 view .LVU206 + 688 00a4 4FF44060 mov r0, #3072 + 689 .LVL70: + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 690 .loc 1 291 19 view .LVU207 + 691 00a8 FFF7FEFF bl LL_RCC_GetUSARTClockFreq + 692 .LVL71: + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 693 .loc 1 291 19 view .LVU208 + 694 00ac E4E7 b .L28 + 695 .LVL72: + 696 .L46: + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 697 .loc 1 295 7 is_stmt 1 view .LVU209 + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + ARM GAS /tmp/ccci4zB8.s page 82 + + + 698 .loc 1 295 19 is_stmt 0 view .LVU210 + 699 00ae 4FF44050 mov r0, #12288 + 700 .LVL73: + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 701 .loc 1 295 19 view .LVU211 + 702 00b2 FFF7FEFF bl LL_RCC_GetUARTClockFreq + 703 .LVL74: + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 704 .loc 1 295 19 view .LVU212 + 705 00b6 DFE7 b .L28 + 706 .LVL75: + 707 .L47: + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 708 .loc 1 299 7 is_stmt 1 view .LVU213 + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 709 .loc 1 299 19 is_stmt 0 view .LVU214 + 710 00b8 4FF44040 mov r0, #49152 + 711 .LVL76: + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 712 .loc 1 299 19 view .LVU215 + 713 00bc FFF7FEFF bl LL_RCC_GetUARTClockFreq + 714 .LVL77: + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 715 .loc 1 299 19 view .LVU216 + 716 00c0 DAE7 b .L28 + 717 .L48: + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** status = SUCCESS; + 718 .loc 1 313 7 is_stmt 1 view .LVU217 + 719 .LVL78: + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_USART_SetBaudRate(USARTx, + 720 .loc 1 314 7 view .LVU218 + 721 00c2 AA69 ldr r2, [r5, #24] + 722 00c4 0146 mov r1, r0 + 723 00c6 2046 mov r0, r4 + 724 .LVL79: + 725 .loc 1 314 7 is_stmt 0 view .LVU219 + 726 00c8 FFF7FEFF bl LL_USART_SetBaudRate + 727 .LVL80: + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_USART_SetBaudRate(USARTx, + 728 .loc 1 313 14 view .LVU220 + 729 00cc 0020 movs r0, #0 + 730 00ce 00E0 b .L26 + 731 .LVL81: + 732 .L35: + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + 733 .loc 1 222 15 view .LVU221 + 734 00d0 0120 movs r0, #1 + 735 .LVL82: + 736 .L26: + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** periphclk, + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** USART_InitStruct->OverSampling, + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** USART_InitStruct->BaudRate); + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Check BRR is greater than or equal to 16d */ + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); + 737 .loc 1 320 7 is_stmt 1 view .LVU222 + ARM GAS /tmp/ccci4zB8.s page 83 + + + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Endif (=> USART not in Disabled state => return ERROR) */ + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** return (status); + 738 .loc 1 325 3 view .LVU223 + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 739 .loc 1 326 1 is_stmt 0 view .LVU224 + 740 00d2 38BD pop {r3, r4, r5, pc} + 741 .LVL83: + 742 .L37: + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + 743 .loc 1 222 15 view .LVU225 + 744 00d4 0120 movs r0, #1 + 745 .LVL84: + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + 746 .loc 1 222 15 view .LVU226 + 747 00d6 FCE7 b .L26 + 748 .L50: + 749 .align 2 + 750 .L49: + 751 00d8 F369FFEF .word -268473869 + 752 00dc 00100140 .word 1073811456 + 753 00e0 00440040 .word 1073759232 + 754 00e4 00480040 .word 1073760256 + 755 00e8 004C0040 .word 1073761280 + 756 00ec 00500040 .word 1073762304 + 757 00f0 00140140 .word 1073812480 + 758 00f4 00780040 .word 1073772544 + 759 00f8 007C0040 .word 1073773568 + 760 .cfi_endproc + 761 .LFE543: + 763 .section .text.LL_USART_StructInit,"ax",%progbits + 764 .align 1 + 765 .global LL_USART_StructInit + 766 .syntax unified + 767 .thumb + 768 .thumb_func + 770 LL_USART_StructInit: + 771 .LVL85: + 772 .LFB544: + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @brief Set each @ref LL_USART_InitTypeDef field to default value. + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * whose fields will be set to default values. + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @retval None + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 773 .loc 1 336 1 is_stmt 1 view -0 + 774 .cfi_startproc + 775 @ args = 0, pretend = 0, frame = 0 + 776 @ frame_needed = 0, uses_anonymous_args = 0 + 777 @ link register save eliminated. + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Set USART_InitStruct fields to default values */ + ARM GAS /tmp/ccci4zB8.s page 84 + + + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** USART_InitStruct->BaudRate = USART_DEFAULT_BAUDRATE; + 778 .loc 1 338 3 view .LVU228 + 779 .loc 1 338 41 is_stmt 0 view .LVU229 + 780 0000 4FF41653 mov r3, #9600 + 781 0004 0360 str r3, [r0] + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; + 782 .loc 1 339 3 is_stmt 1 view .LVU230 + 783 .loc 1 339 41 is_stmt 0 view .LVU231 + 784 0006 0023 movs r3, #0 + 785 0008 4360 str r3, [r0, #4] + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** USART_InitStruct->StopBits = LL_USART_STOPBITS_1; + 786 .loc 1 340 3 is_stmt 1 view .LVU232 + 787 .loc 1 340 41 is_stmt 0 view .LVU233 + 788 000a 8360 str r3, [r0, #8] + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** USART_InitStruct->Parity = LL_USART_PARITY_NONE ; + 789 .loc 1 341 3 is_stmt 1 view .LVU234 + 790 .loc 1 341 41 is_stmt 0 view .LVU235 + 791 000c C360 str r3, [r0, #12] + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX; + 792 .loc 1 342 3 is_stmt 1 view .LVU236 + 793 .loc 1 342 41 is_stmt 0 view .LVU237 + 794 000e 0C22 movs r2, #12 + 795 0010 0261 str r2, [r0, #16] + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE; + 796 .loc 1 343 3 is_stmt 1 view .LVU238 + 797 .loc 1 343 41 is_stmt 0 view .LVU239 + 798 0012 4361 str r3, [r0, #20] + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16; + 799 .loc 1 344 3 is_stmt 1 view .LVU240 + 800 .loc 1 344 41 is_stmt 0 view .LVU241 + 801 0014 8361 str r3, [r0, #24] + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 802 .loc 1 345 1 view .LVU242 + 803 0016 7047 bx lr + 804 .cfi_endproc + 805 .LFE544: + 807 .section .text.LL_USART_ClockInit,"ax",%progbits + 808 .align 1 + 809 .global LL_USART_ClockInit + 810 .syntax unified + 811 .thumb + 812 .thumb_func + 814 LL_USART_ClockInit: + 815 .LVL86: + 816 .LFB545: + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @brief Initialize USART Clock related settings according to the + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * specified parameters in the USART_ClockInitStruct. + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @note As some bits in USART configuration registers can only be written when + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled sta + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * this function. Otherwise, ERROR result will be returned. + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @param USARTx USART Instance + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * that contains the Clock configuration information for the specified USART peripheral. + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @retval An ErrorStatus enumeration value: + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * - SUCCESS: USART registers related to Clock settings are initialized according + ARM GAS /tmp/ccci4zB8.s page 85 + + + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * to USART_ClockInitStruct content + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * - ERROR: Problem occurred during USART Registers initialization + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockI + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 817 .loc 1 362 1 is_stmt 1 view -0 + 818 .cfi_startproc + 819 @ args = 0, pretend = 0, frame = 0 + 820 @ frame_needed = 0, uses_anonymous_args = 0 + 821 @ link register save eliminated. + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** ErrorStatus status = SUCCESS; + 822 .loc 1 363 3 view .LVU244 + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Check USART Instance and Clock signal output parameters */ + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** assert_param(IS_UART_INSTANCE(USARTx)); + 823 .loc 1 366 3 view .LVU245 + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput)); + 824 .loc 1 367 3 view .LVU246 + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* USART needs to be in disabled state, in order to be able to configure some bits in + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** CRx registers */ + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** if (LL_USART_IsEnabled(USARTx) == 0U) + 825 .loc 1 371 3 view .LVU247 + 826 .LBB98: + 827 .LBI98: + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 828 .loc 2 585 26 view .LVU248 + 829 .LBB99: + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 830 .loc 2 587 3 view .LVU249 + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 831 .loc 2 587 12 is_stmt 0 view .LVU250 + 832 0000 0368 ldr r3, [r0] + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 833 .loc 2 587 73 view .LVU251 + 834 0002 13F0010F tst r3, #1 + 835 0006 18D1 bne .L55 + 836 .LVL87: + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 837 .loc 2 587 73 view .LVU252 + 838 .LBE99: + 839 .LBE98: + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* If USART Clock signal is disabled */ + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE) + 840 .loc 1 374 5 is_stmt 1 view .LVU253 + 841 .loc 1 374 30 is_stmt 0 view .LVU254 + 842 0008 0B68 ldr r3, [r1] + 843 .loc 1 374 8 view .LVU255 + 844 000a 2BB9 cbnz r3, .L54 + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Deactivate Clock signal delivery : + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * - Disable Clock Output: USART_CR2_CLKEN cleared + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_USART_DisableSCLKOutput(USARTx); + 845 .loc 1 379 7 is_stmt 1 view .LVU256 + 846 .LVL88: + ARM GAS /tmp/ccci4zB8.s page 86 + + + 847 .LBB100: + 848 .LBI100: +1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** { + 849 .loc 2 1044 22 view .LVU257 + 850 .LBB101: +1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 851 .loc 2 1046 3 view .LVU258 + 852 000c 4368 ldr r3, [r0, #4] + 853 000e 23F40063 bic r3, r3, #2048 + 854 0012 4360 str r3, [r0, #4] + 855 .LVL89: +1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** } + 856 .loc 2 1046 3 is_stmt 0 view .LVU259 + 857 .LBE101: + 858 .LBE100: + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 859 .loc 1 363 15 view .LVU260 + 860 0014 0020 movs r0, #0 + 861 .LVL90: + 862 .LBB103: + 863 .LBB102: +1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 864 .loc 2 1047 1 view .LVU261 + 865 0016 7047 bx lr + 866 .LVL91: + 867 .L54: +1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h **** + 868 .loc 2 1047 1 view .LVU262 + 869 .LBE102: + 870 .LBE103: + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** ErrorStatus status = SUCCESS; + 871 .loc 1 362 1 view .LVU263 + 872 0018 10B4 push {r4} + 873 .LCFI1: + 874 .cfi_def_cfa_offset 4 + 875 .cfi_offset 4, -4 + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** else + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Ensure USART instance is USART capable */ + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** assert_param(IS_USART_INSTANCE(USARTx)); + 876 .loc 1 384 7 is_stmt 1 view .LVU264 + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Check clock related parameters */ + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); + 877 .loc 1 387 7 view .LVU265 + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); + 878 .loc 1 388 7 view .LVU266 + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); + 879 .loc 1 389 7 view .LVU267 + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /*---------------------------- USART CR2 Configuration ----------------------- + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * Configure USARTx CR2 (Clock signal related bits) with parameters: + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * - Enable Clock Output: USART_CR2_CLKEN set + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->Cloc + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->Cloc + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->Last + ARM GAS /tmp/ccci4zB8.s page 87 + + + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** MODIFY_REG(USARTx->CR2, + 880 .loc 1 398 7 view .LVU268 + 881 001a 4368 ldr r3, [r0, #4] + 882 001c 23F47063 bic r3, r3, #3840 + 883 0020 4A68 ldr r2, [r1, #4] + 884 0022 8C68 ldr r4, [r1, #8] + 885 0024 2243 orrs r2, r2, r4 + 886 0026 C968 ldr r1, [r1, #12] + 887 .LVL92: + 888 .loc 1 398 7 is_stmt 0 view .LVU269 + 889 0028 0A43 orrs r2, r2, r1 + 890 002a 1343 orrs r3, r3, r2 + 891 002c 43F40063 orr r3, r3, #2048 + 892 0030 4360 str r3, [r0, #4] + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 893 .loc 1 363 15 view .LVU270 + 894 0032 0020 movs r0, #0 + 895 .LVL93: + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity | + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Else (USART not in Disabled state => return ERROR */ + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** else + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** status = ERROR; + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** return (status); + 896 .loc 1 410 3 is_stmt 1 view .LVU271 + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 897 .loc 1 411 1 is_stmt 0 view .LVU272 + 898 0034 5DF8044B ldr r4, [sp], #4 + 899 .LCFI2: + 900 .cfi_restore 4 + 901 .cfi_def_cfa_offset 0 + 902 0038 7047 bx lr + 903 .LVL94: + 904 .L55: + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 905 .loc 1 407 12 view .LVU273 + 906 003a 0120 movs r0, #1 + 907 .LVL95: + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 908 .loc 1 410 3 is_stmt 1 view .LVU274 + 909 .loc 1 411 1 is_stmt 0 view .LVU275 + 910 003c 7047 bx lr + 911 .cfi_endproc + 912 .LFE545: + 914 .section .text.LL_USART_ClockStructInit,"ax",%progbits + 915 .align 1 + 916 .global LL_USART_ClockStructInit + 917 .syntax unified + 918 .thumb + 919 .thumb_func + ARM GAS /tmp/ccci4zB8.s page 88 + + + 921 LL_USART_ClockStructInit: + 922 .LVL96: + 923 .LFB546: + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /** + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value. + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * whose fields will be set to default values. + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** * @retval None + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** */ + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** { + 924 .loc 1 420 1 is_stmt 1 view -0 + 925 .cfi_startproc + 926 @ args = 0, pretend = 0, frame = 0 + 927 @ frame_needed = 0, uses_anonymous_args = 0 + 928 @ link register save eliminated. + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** /* Set LL_USART_ClockInitStruct fields with default values */ + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE; + 929 .loc 1 422 3 view .LVU277 + 930 .loc 1 422 44 is_stmt 0 view .LVU278 + 931 0000 0023 movs r3, #0 + 932 0002 0360 str r3, [r0] + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when + 933 .loc 1 423 3 is_stmt 1 view .LVU279 + 934 .loc 1 423 44 is_stmt 0 view .LVU280 + 935 0004 4360 str r3, [r0, #4] + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_USART_CLOCK_DI + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when + 936 .loc 1 425 3 is_stmt 1 view .LVU281 + 937 .loc 1 425 44 is_stmt 0 view .LVU282 + 938 0006 8360 str r3, [r0, #8] + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_USART_CLOCK_DI + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when + 939 .loc 1 427 3 is_stmt 1 view .LVU283 + 940 .loc 1 427 44 is_stmt 0 view .LVU284 + 941 0008 C360 str r3, [r0, #12] + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** LL_USART_CLOCK_DI + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c **** } + 942 .loc 1 429 1 view .LVU285 + 943 000a 7047 bx lr + 944 .cfi_endproc + 945 .LFE546: + 947 .text + 948 .Letext0: + 949 .file 4 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 950 .file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 951 .file 6 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + 952 .file 7 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h" + ARM GAS /tmp/ccci4zB8.s page 89 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_ll_usart.c + /tmp/ccci4zB8.s:20 .text.LL_USART_SetBaudRate:00000000 $t + /tmp/ccci4zB8.s:25 .text.LL_USART_SetBaudRate:00000000 LL_USART_SetBaudRate + /tmp/ccci4zB8.s:81 .text.LL_USART_DeInit:00000000 $t + /tmp/ccci4zB8.s:87 .text.LL_USART_DeInit:00000000 LL_USART_DeInit + /tmp/ccci4zB8.s:456 .text.LL_USART_DeInit:000000f4 $d + /tmp/ccci4zB8.s:470 .text.LL_USART_Init:00000000 $t + /tmp/ccci4zB8.s:476 .text.LL_USART_Init:00000000 LL_USART_Init + /tmp/ccci4zB8.s:751 .text.LL_USART_Init:000000d8 $d + /tmp/ccci4zB8.s:764 .text.LL_USART_StructInit:00000000 $t + /tmp/ccci4zB8.s:770 .text.LL_USART_StructInit:00000000 LL_USART_StructInit + /tmp/ccci4zB8.s:808 .text.LL_USART_ClockInit:00000000 $t + /tmp/ccci4zB8.s:814 .text.LL_USART_ClockInit:00000000 LL_USART_ClockInit + /tmp/ccci4zB8.s:915 .text.LL_USART_ClockStructInit:00000000 $t + /tmp/ccci4zB8.s:921 .text.LL_USART_ClockStructInit:00000000 LL_USART_ClockStructInit + +UNDEFINED SYMBOLS +LL_RCC_GetUSARTClockFreq +LL_RCC_GetUARTClockFreq diff --git a/build/stm32f7xx_ll_usart.o b/build/stm32f7xx_ll_usart.o new file mode 100644 index 0000000000000000000000000000000000000000..6d6703cf23f0a44b34431a4b3d2fd411a23d7a41 GIT binary patch literal 17516 zcmb8034B!5*~ZVEJ9n~7RuV%9h!Y4B#H^q!1`U}&2m}b3P$-|8Op*zSWOFiMv0A9O z;PO?fP~5d*UC}CP)oLp)t+v`4Teni&S}oX0MM1zy<$IoU-#eK^w4djfd;jNM&U@Co z&du6cHM0%FP);&bz8a8}dh!fyu_kNetI_Iswf!@-(9>`HGhjUU#r{t&+x~Q8Pt~$` z*FR^vwtumI|H6a&!a3#7?yoR2{LjLoRN1_1E3*2zKcW9L?DO@$q<=c{)AiopKMnaB zyO*!X`(X{o4wSL_gTTj~h zgSNluRaAe#_8%txpzVLPuGc5^lD7U``tMs;q5U;&{o7ivL{Cz$(u{Idsmj$HY&FPkqE}%h+e6HofAWojluYE18>9KCkV!ZC?L`cCY_#Y&m{cM)7?8X|FwJJf$|=De#l%SbMG@(%iKH6l{2?<_dV^# zY~O6=l~28E_@@5S@EzH`zy0XP|E=!}4`c<*Mm5&oxW4h(#-uT>pg*`ih&k6IlKqOe zZQ|qpwy_6Pv%isJnf5THp60o2SGJAu|F$jBkMR)eS%=;8daAf$)L668j)+J}O1bok zbsJ+XrIOAzm2yM#rdAH@T<*9x-0+Q$y9rj8;VCo#mo*+e_b~LK6fEdL*;zA~>x`T42?8teE z^^`w%N07gT(cAA!!!L3c)O~T?6s@X->0}hM0a{7#d;Cr)0Z&LG7*!~w;+J4QN*lM_GMQ5u#>dFV8IC0tCqCP9oUwwgTMZA|i?bm%*9FR$4u`Bqpn_#O1)~5b>Rk$-_^3T&s)j@CYa z)*fdBu{Rb<_p)JN_eOZoy;|E+OhI>#6L`GwHoLcLpm#@5W-dY+e~eRVwC>%mli0aU zP@aQrv<|du0qs9V;VZG7p!@c=?%E#640=K$A{p=KSzd(l6S4W&UD%YDyA(R?je7(Q z(!HI622H}Ia&CiLJ~Db&N;ku>{z1QA!SY@BEXFqSK?vs|vsxEg4N2deamPtA;tlHr zv~uJoSbhYb|7D>|A#6v6GWvbk5Qg};LnWS=mE}q+>N`%}Y%BQ2s9ct`LP=0{1MC)7; zn=YHI?R5DClxtzWAR4KKF5LCd?KB8Lxy8Xl&n;>m^9xlI*Mxxajp0-F7r`w5)M62sAx;$s;C^y4&Bh6TtKfxhBeg<}CZd{gOa&hH94hzI-`ouiG8!O1% z$3 z$l?hMmgzi$8MWCTp?-+-Sm6_B^&{A_^;NFT(?I1XQ0%4h4n}GBOr~;FJQUbQj9|1C z9(_)$g2GSbbRKvew(=S%xa!q-p1NH-*oiv$aQ0>am7emuFR=X-zV6@QnbYomf zhSy9PnX=fEZqylRSg)=;<@KHpB}O(&nJLq~r+KG&t21zYJy8+XDHJ07f5%=st?w&_0Fs>t{HM)l`TbFaZQIb(-JXYal z@ulAHT1#|SMp~*QLwrU>eHMFc4_u(5wWG7_$e`LsOYM3fB+3b~V<9?UG_ut0wQJA4 z>_P)eqeM^Xn9DCTlq>N^73lO>$ABx%FV8# zNZmr27eknd=|jwv%WN~jiegJc9Fp=O8)^{|jb+$XQDy*`vDZmoU?tD$U8?vNrx|FG zQ#;j8^-xOz`z8_sPe3u=F&=n`f-TdwV;@bdm?KFZvGZwBW;$~Y*+-_@$yKF6SzpW*<+gjo=TT47?Yl(ha zOZ?H+60c&5ony)zB16?ggGVbh>HgzE*cb37Q#Tp#ZI_^H<6r?XRx_c$t@&f zasHi{)H^{j?oKSK;i(ft{P#q!)z}!ET!#$-F9bGVqnflQs+QO&YVvAq@FuPmHEB;( zEpeNuNqeqp3El@WHfc{*Ex{XPs>#Q&AvUoC8`b0s*q|m})Y(M?V^Vwz2jX?x1ACo# z+F&nJu%V#ijjT4yE*~t`9s!~hn@jb@1Cr=K?T~Vlp(@kr0Kp?0QfN3T7!g807-7jceug%dLv*R~ zs1|u>=6prV@mq?`t;%QQ#duTKcnm!Uw8z$;9_vrt>SO3R!W(S;8L|G8R zFOT)7?yh6#IR`v&Ocn2oX+BjuzN+Sw^kYMB=f*~-?#*N9IY)c2S*mSODG!3KR-|% zD5?ytY;O*s;(@x05Knum-bm-9(pEO7qobj(HyDl-HnY9Q(6@2P4AM9C^%jb@1wW!7 zk4H-JI2AFW!1{_786vXAaC5UA0q;@q!-J(4rTJl!VVM~jnU=?6SokdsSR>}|b<)^1ML+PToCns0}xG|a8ZKA-KjS8KA& zFY#t@pz!)tcHw6eVhZ22(k}ex1gG#*T9aiS98~xUDg4AY7k*v}|7%d;Yozc)-(2`* zDg5_Ag>R6;_kMHXH>B{Rg9hw(GGKdc?bi+1W^sFcP|f#B%{P2=&AX-MKMX4TkQBb= zYYN8?T0^@GyvxS?=Vlz2VW%uC+8lG2i*scq!C38EYR~Sy7Z{$U9@87Krg{u`WqHg8 zJU&kJT$%sZ))>}g$M(mBLAD21a&a0~qNiLh?{CXg^O3b>J}b^+miVj;`#>>s3$u05 z<8v+4mTKO))~8)gv0Vz`o~NCUkt>YqzBXs3_%b|YR!RXv|8y<=&A%%2YPddHQq5~o zohxI|fWB-G+yp(UGc21$!rUPotT%F9#-LaqG8QJro|4yb>_?}hOs3@f2G1f^JbOKk zb7Ed+(amG8xYy3(L>cBbi$|IHr}GTNi&{A5@Y?2VvOT}f?UM{h{g*3?v&2K=+D>QqIruca;+ z39-sjyScTxxxLD6o71FdV`JM{8H@y%w6{ds*w9IKaUHe~O`X~h(H&v?*&*8;jS~n( z<}A^@h=e;-Z~OADP>Zj*Ef`i!;cz6>*`qqTyO#S}y8D_s&^*LvAg$9o4n{OHD;(|) z2O_~pU$3h3`x~5AYlprriOwRG{&{R+snX-IurJcnr<+--$9u?p*h8si)zvN3)5UHy zRMpj%G|cV}H;3v%y`jj!=%Yu@1lNSRmSa?k+PXVKMXjNhVA1^Q+WMlpU`u;z|88(>hILmhC{v0^+B0Idrj*bk(TzAT!wnF=s{nt>gqAbz4jaq>P=m!BZMZ| zqg@*ew@21Q?}EPWj;knoV-kDs!%mf)icZb^6pvRFB}l4!0pnwu2OO^)VHiRMm~k?!uWd&6@Dr)6MNduMfV)LNYN zS|W!dhg()<)H&vW4=nckX9WVX8f2{w8o&B*u&cK<6s~L!hngep-Cg?78a$_1$kFpc zw3f<{p6WqkW>2)9#F&BOIc;F%1_HGAvP%Jf%{)2msunEv`Aeqw>^odvX>sYKlH%fN zzJku?p1v8)IOT;_7j#a69BJ$8Yyw-MZ|zxmNsT4c9gOLKG2gT#~;s`tp%mNf`yP;TX5bg=(YRb3%RwgOOHiVr&N{SKi!vK za>{hwxNxYWq@Z-d(3bKMf{z(Tk?>CY{FJ2RL61;;%%I&#eB6kA6yamo%#^hC?u*Qe zT|cy6nmWGpi}mFr+WZvvMaIJCQs@&Km-(3`*ai8-pp5azT2p2f%vYY|xcLdL#Q0(E zOyf9XxS4H?FmjAh#%N;BX2cyrwi!}!h=nd@#C#&03$B(|o_5kSi8u(3SX;V_KfCXu-ohhe<#6q)O9 z7{&*u?_)f1<_*3^Mo%qyEdwV!IlDwp7W!QCP3M$jo~5J3V@`=t-Jok_%!NM2H-dg7 z`t08e$SXx=zY}xqUjazIwxE5x=${n6K;lxLmkOxIuWG@E+k4!ru$?a7tqQ z$->RTM}$uZpAq&8-xux|x^SvuoOGd2SR_1MxIow@TqV3jxLNp9;funzgolLb`~e>I z<&Zcn;P+R}iK4F%E+lcF282sUoTP$c?-co5;Y!h8DDox3D@4CV5hmh5p*~kwK;kr7B0Pmef6fs5T#*+D1EN1$ zf zp_hbzmdH86u_U&9;mN`>66MQ|xGx9IN^ zJ}UMng*$}(Vt-Zmw&?#xBF=u%9}*h4)U#h6VWKdHM88H0^F?1kBF+ra&lJuRd#$iu z*dq2eVOaF5NW{5R^j8Qsi~V}x&BFV|zFqjF=$|GL=M~YvCVWTi?+f<`4~zYX(1S}i z`|l+YXC#S!^V>>tg4hd%r9ytfLHlfBt>_n%h!YfjNEjxuu6`iAN_ewyoA3$YZ-s9P z|1SKP#5rWYkhflpn<^Yhvi-t5(HDz6SvXDfvqY{IE)e}PkfaN7DBLSNAUrJOO(y-_!r{V^LO!d| zexh)S@H8PmB zox=Bo9|%7Z?i1?!AC&(>Wc;9^<9US1!gOJ_aFlSYP~R^hPNB%9!fC=8!b;&B;X+|R zxJ-DqFeGdjt`S}!EC`n*D8bfzUxL$qmas*r?{lH&$MLj(U&xQ(DeL=P@J5ku73%M3q5rwa z{C1qzpS{8Z!ox!SK`QJ?yl(_Egu{j7h5G&&_EM2g70wpU6)qAk7KViF!X9Bnc#&{} z@G9Xo!mYwPh4%}$3-x_6+VvZee=pSc%h10k@(03?g!;Z2c78|Ceh(Ao2uBOY2`32o zMLqrXeKW|<=P551>ic8JD@0x^TrcF;@ASVx$WPrVKP2Qg?UY{>z9ambkYB3P{)LdA zrBluj^80hj6NUWPoN|SbUzJnl|3Q$Q!gGcER-F3Fg#0+1@@+zXa?SgLr-Z)|{!Xax zhhcwPWPXiJ|IdU+gm~ql_53iKcAs#(aH5dkXwyDVxKwzike_SQzD0Pm@HQca2_Ia` z^&Nit`VO0qdK@SDB%Yg!Nn8i@^&ZcKOzbxf6HR0__5A__Cyu^Pfb0`{o>0ewezM3q zE@XWl0nQP9jj&dz-#@_KC~}LiO{m{Tz`k1K^M&h#7YR2CHwmv5-YC3FxJ~$g@L}N& zGEM$H0enH^mxOPU7|&h8cS*GCec>Jwq*3G6j_fq;_7il z`E}HDJrwq?>5K%Mz)09;o0G%4^oT0tn{QRv)Z42HsVI!T9gBVEKg1;O<_hr=e27KA zr5mD)d7U=IGVlWKSccegtf?i`)VI8$y{okwt=9QqQ&Tv!Qt5Ws8vJe=D+ck~#_|xl zHcXJ-gMe#Mk(4F@~nG_!7gVK5R2w>R}g5cdC{FeO|n`aK{^ zab9B+ZfkVP#h!jxHaZRUqm5}iHY|_->UT1HhSpmMos*n;tDuPW<9gydVkfyJ69i-Z zRzu*i;3UWIEGY0OsmjH0<3#)1!ExZZjecx@AGX+d5i}?pIwv{py9$a}KmPBZ^NAXL z9lyJV`27xsBsxfP{9c62cusm9hPW6<$M!rNV*Bwv`caOCvmZDdqy6A}RHqEG>Mb0b ze{w2|vGKVl*6#tl2!4ELxCXIagpStB^N~{qSrx=H?;K_%Ikp3k zW8-C(+1CulqI23UK zNOEi=kco}=(hU3B#(0_7oOlx?Ua^$lldBZpJvxc;xJ@47cLxp_{6&-FH&gr^LqD80 zI0DFenP$K*wtYv?zDDTTKCV}%eSF@;vD*WcPD}IcFSZ?-^)it$%R^lWzgj3pK|dNB l<8fYCr*keqR_!`TsU6Hna^ms#gjl~bad4dN7-4g={|B=J8nXZZ literal 0 HcmV?d00001 diff --git a/build/stm32f7xx_ll_utils.d b/build/stm32f7xx_ll_utils.d new file mode 100644 index 0000000..7a7e6b3 --- /dev/null +++ b/build/stm32f7xx_ll_utils.d @@ -0,0 +1,76 @@ +build/stm32f7xx_ll_utils.o: \ + Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h: diff --git a/build/stm32f7xx_ll_utils.lst b/build/stm32f7xx_ll_utils.lst new file mode 100644 index 0000000..56b8018 --- /dev/null +++ b/build/stm32f7xx_ll_utils.lst @@ -0,0 +1,8356 @@ +ARM GAS /tmp/ccTd4L28.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "stm32f7xx_ll_utils.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c" + 19 .section .text.UTILS_GetPLLOutputFrequency,"ax",%progbits + 20 .align 1 + 21 .syntax unified + 22 .thumb + 23 .thumb_func + 25 UTILS_GetPLLOutputFrequency: + 26 .LVL0: + 27 .LFB411: + 1:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @file stm32f7xx_ll_utils.c + 4:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @brief UTILS LL module driver. + 6:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * + 9:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * + 12:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * This software is licensed under terms that can be found in the LICENSE file + 13:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * in the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * + 16:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 18:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Includes ------------------------------------------------------------------*/ + 19:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #include "stm32f7xx_ll_utils.h" + 20:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #include "stm32f7xx_ll_rcc.h" + 21:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #include "stm32f7xx_ll_system.h" + 22:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #include "stm32f7xx_ll_pwr.h" + 23:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #ifdef USE_FULL_ASSERT + 24:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #include "stm32_assert.h" + 25:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #else + 26:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define assert_param(expr) ((void)0U) + 27:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #endif /* USE_FULL_ASSERT */ + 28:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 29:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** @addtogroup STM32F7xx_LL_Driver + 30:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @{ + 31:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + ARM GAS /tmp/ccTd4L28.s page 2 + + + 32:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 33:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** @addtogroup UTILS_LL + 34:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @{ + 35:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 36:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 37:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Private types -------------------------------------------------------------*/ + 38:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Private variables ---------------------------------------------------------*/ + 39:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Private constants ---------------------------------------------------------*/ + 40:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** @addtogroup UTILS_LL_Private_Constants + 41:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @{ + 42:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 43:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_MAX_FREQUENCY_SCALE1 216000000U /*!< Maximum frequency for system clock at power sca + 44:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_MAX_FREQUENCY_SCALE2 180000000U /*!< Maximum frequency for system clock at pow + 45:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_MAX_FREQUENCY_SCALE3 144000000U /*!< Maximum frequency for system clock at pow + 46:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 47:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Defines used for PLL range */ + 48:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz * + 49:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz * + 50:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz * + 51:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz * + 52:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 53:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Defines used for HSE range */ + 54:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz + 55:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz + 56:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 57:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Defines used for FLASH latency according to HCLK Frequency */ + 58:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in p + 59:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in p + 60:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in p + 61:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in p + 62:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in p + 63:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE1_LATENCY6_FREQ 180000000U /*!< HCLK frequency to set FLASH latency 6 in p + 64:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE1_LATENCY7_FREQ 210000000U /*!< HCLK frequency to set FLASH latency 7 in p + 65:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in p + 66:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in p + 67:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in p + 68:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE2_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in p + 69:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in p + 70:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in p + 71:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in p + 72:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in p + 73:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define UTILS_SCALE3_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in p + 74:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** + 75:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @} + 76:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 77:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 78:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Private macros ------------------------------------------------------------*/ + 79:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** @addtogroup UTILS_LL_Private_Macros + 80:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @{ + 81:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 82:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ + 83:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ + 84:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ + 85:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ + 86:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ + 87:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ + 88:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ + ARM GAS /tmp/ccTd4L28.s page 3 + + + 89:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ + 90:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) + 91:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 92:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ + 93:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ + 94:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ + 95:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ + 96:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB1_DIV_16)) + 97:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 98:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ + 99:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ + 100:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ + 101:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ + 102:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_APB2_DIV_16)) + 103:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 104:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \ + 105:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \ + 106:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \ + 107:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \ + 108:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \ + 109:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \ + 110:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \ + 111:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \ + 112:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \ + 113:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \ + 114:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \ + 115:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \ + 116:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \ + 117:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \ + 118:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \ + 119:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \ + 120:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \ + 121:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \ + 122:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \ + 123:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \ + 124:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \ + 125:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \ + 126:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \ + 127:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \ + 128:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \ + 129:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \ + 130:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \ + 131:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \ + 132:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \ + 133:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \ + 134:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \ + 135:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \ + 136:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \ + 137:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \ + 138:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \ + 139:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \ + 140:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \ + 141:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \ + 142:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \ + 143:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \ + 144:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \ + 145:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \ + ARM GAS /tmp/ccTd4L28.s page 4 + + + 146:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \ + 147:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \ + 148:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \ + 149:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \ + 150:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \ + 151:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \ + 152:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \ + 153:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \ + 154:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \ + 155:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \ + 156:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \ + 157:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \ + 158:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \ + 159:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \ + 160:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \ + 161:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \ + 162:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \ + 163:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \ + 164:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \ + 165:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLM_DIV_63)) + 166:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 167:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((50 <= (__VALUE__)) && ((__VALUE__) <= 432)) + 168:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 169:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \ + 170:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \ + 171:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \ + 172:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__VALUE__) == LL_RCC_PLLP_DIV_8)) + 173:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 174:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE_ + 175:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 176:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE + 177:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 178:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTA + 179:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTA + 180:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3)) + 181:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 182:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ + 183:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) + 184:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 185:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ( + 186:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** + 187:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @} + 188:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 189:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Private function prototypes -----------------------------------------------*/ + 190:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** @defgroup UTILS_LL_Private_Functions UTILS Private functions + 191:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @{ + 192:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 193:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, + 194:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); + 195:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDe + 196:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** static ErrorStatus UTILS_PLL_IsBusy(void); + 197:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** + 198:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @} + 199:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 200:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 201:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Exported functions --------------------------------------------------------*/ + 202:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** @addtogroup UTILS_LL_Exported_Functions + ARM GAS /tmp/ccTd4L28.s page 5 + + + 203:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @{ + 204:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 205:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 206:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** @addtogroup UTILS_LL_EF_DELAY + 207:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @{ + 208:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 209:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 210:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** + 211:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @brief This function configures the Cortex-M SysTick source to have 1ms time base. + 212:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @note When a RTOS is used, it is recommended to avoid changing the Systick + 213:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * configuration by calling this function, for a delay use rather osDelay RTOS service. + 214:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @param HCLKFrequency HCLK frequency in Hz + 215:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_Get + 216:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @retval None + 217:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 218:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** void LL_Init1msTick(uint32_t HCLKFrequency) + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 220:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Use frequency provided in argument */ + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** LL_InitTick(HCLKFrequency, 1000U); + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 223:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 224:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** + 225:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @brief This function provides accurate delay (in milliseconds) based + 226:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * on SysTick counter flag + 227:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @note When a RTOS is used, it is recommended to avoid using blocking delay + 228:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * and use rather osDelay service. + 229:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which + 230:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * will configure Systick to 1ms + 231:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @param Delay specifies the delay time length, in milliseconds. + 232:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @retval None + 233:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 234:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** void LL_mDelay(uint32_t Delay) + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + 237:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Add this code to indicate that local variable is not used */ + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ((void)tmp); + 239:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 240:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Add a period to guaranty minimum wait */ + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(Delay < LL_MAX_DELAY) + 242:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** Delay++; + 244:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 245:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** while (Delay) + 247:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) + 249:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** Delay--; + 251:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 252:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 254:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 255:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** + 256:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @} + 257:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 258:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 259:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** @addtogroup UTILS_EF_SYSTEM + ARM GAS /tmp/ccTd4L28.s page 6 + + + 260:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @brief System Configuration functions + 261:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * + 262:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** @verbatim + 263:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** =============================================================================== + 264:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ##### System Configuration functions ##### + 265:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** =============================================================================== + 266:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** [..] + 267:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** System, AHB and APB buses clocks configuration + 268:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 269:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 216000000 Hz. + 270:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** @endverbatim + 271:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** @internal + 272:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** Depending on the device voltage range, the maximum frequency should be + 273:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** adapted accordingly: + 274:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) +-------------------------------------------------------------------------------- + 275:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) | Wait states | HCLK clock frequency (MHz) + 276:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) | |--------------------------------------------------------------- + 277:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) | (Latency) | voltage range | voltage range | voltage range | + 278:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) | | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.7V | + 279:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |----------------|-------------------|-------------------|-------------------|--- + 280:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |0WS(1CPU cycle) | 0 < HCLK <= 30 | 0 < HCLK <= 24 | 0 < HCLK <= 22 | + 281:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |----------------|-------------------|-------------------|-------------------|--- + 282:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |1WS(2CPU cycle) | 30 < HCLK <= 60 | 24 < HCLK <= 48 | 22 < HCLK <= 44 | 2 + 283:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |----------------|-------------------|-------------------|-------------------|--- + 284:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |2WS(3CPU cycle) | 60 < HCLK <= 90 | 48 < HCLK <= 72 | 44 < HCLK <= 66 | 4 + 285:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |----------------|-------------------|-------------------|-------------------|--- + 286:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |3WS(4CPU cycle) | 90 < HCLK <= 120 | 72 < HCLK <= 96 | 66 < HCLK <= 88 | 6 + 287:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |----------------|-------------------|-------------------|-------------------|--- + 288:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |4WS(5CPU cycle) | 120 < HCLK <= 150 | 96 < HCLK <= 120 | 88 < HCLK <= 110 | 8 + 289:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |----------------|-------------------|-------------------|-------------------|--- + 290:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |5WS(6CPU cycle) | 150 < HCLK <= 180 | 120 < HCLK <= 144 | 110 < HCLK <= 132 | 10 + 291:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |----------------|-------------------|-------------------|-------------------|--- + 292:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |6WS(7CPU cycle) | 180 < HCLK <= 210 | 144 < HCLK <= 168 | 132 < HCLK <= 154 | 12 + 293:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |----------------|-------------------|-------------------|-------------------|--- + 294:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |7WS(8CPU cycle) | 210 < HCLK <= 216 | 168 < HCLK <= 192 | 154 < HCLK <= 176 | 14 + 295:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |----------------|-------------------|-------------------|-------------------|--- + 296:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |8WS(9CPU cycle) | -- | 192 < HCLK <= 216 | 176 < HCLK <= 198 | 16 + 297:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |----------------|-------------------|-------------------|-------------------|--- + 298:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) |9WS(10CPU cycle)| -- | -- | 198 < HCLK <= 216 | + 299:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** (++) +-------------------------------------------------------------------------------- + 300:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 301:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** @endinternal + 302:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @{ + 303:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 304:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 305:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** + 306:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @brief This function sets directly SystemCoreClock CMSIS variable. + 307:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @note Variable can be calculated also through SystemCoreClockUpdate function. + 308:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + 309:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @retval None + 310:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 311:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** void LL_SetSystemCoreClock(uint32_t HCLKFrequency) + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 313:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* HCLK clock frequency */ + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** SystemCoreClock = HCLKFrequency; + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 316:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + ARM GAS /tmp/ccTd4L28.s page 7 + + + 317:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** + 318:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @brief Update number of Flash wait states in line with new frequency and current + 319:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** voltage range. + 320:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and + 321:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @param HCLK_Frequency HCLK frequency + 322:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @retval An ErrorStatus enumeration value: + 323:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * - SUCCESS: Latency has been modified + 324:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * - ERROR: Latency cannot be modified + 325:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 326:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** uint32_t timeout; + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** uint32_t getlatency; + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 332:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 333:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Frequency cannot be equal to 0 */ + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(HCLK_Frequency == 0U) + 335:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** status = ERROR; + 337:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 338:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** else + 339:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) + 341:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(LL_PWR_IsEnabledOverDriveMode() != 0U) + 343:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(HCLK_Frequency > UTILS_SCALE1_LATENCY7_FREQ) + 345:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 346:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* 210 < HCLK <= 216 => 7WS (8 CPU cycles) */ + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** latency = LL_FLASH_LATENCY_7; + 348:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 349:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** else /* (HCLK_Frequency > UTILS_SCALE1_LATENCY6_FREQ) */ + 350:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 351:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* 180 < HCLK <= 210 => 6WS (7 CPU cycles) */ + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** latency = LL_FLASH_LATENCY_6; + 353:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 354:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ) && (latency == LL_FLASH_LATENCY_0)) + 356:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 357:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* 150 < HCLK <= 180 => 5WS (6 CPU cycles) */ + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** latency = LL_FLASH_LATENCY_5; + 359:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** else if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (latency == LL_FLASH_LATENCY_0)) + 361:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 362:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */ + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** latency = LL_FLASH_LATENCY_4; + 364:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (latency == LL_FLASH_LATENCY_0)) + 366:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 367:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */ + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** latency = LL_FLASH_LATENCY_3; + 369:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (latency == LL_FLASH_LATENCY_0)) + 371:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 372:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */ + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** latency = LL_FLASH_LATENCY_2; + ARM GAS /tmp/ccTd4L28.s page 8 + + + 374:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 375:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** else + 376:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (latency == LL_FLASH_LATENCY_0)) + 378:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 379:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */ + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** latency = LL_FLASH_LATENCY_1; + 381:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 382:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* else HCLK_Frequency < 30MHz default LL_FLASH_LATENCY_0 0WS */ + 383:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 384:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) + 386:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ) + 388:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 389:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* 150 < HCLK <= 168 OR 150 < HCLK <= 180 (when OverDrive mode is enable) => 5WS (6 CPU cyc + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** latency = LL_FLASH_LATENCY_5; + 391:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** else if(HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ) + 393:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 394:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */ + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** latency = LL_FLASH_LATENCY_4; + 396:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** else if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) + 398:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 399:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */ + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** latency = LL_FLASH_LATENCY_3; + 401:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** else if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) + 403:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 404:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */ + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** latency = LL_FLASH_LATENCY_2; + 406:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 407:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** else + 408:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) + 410:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 411:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */ + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** latency = LL_FLASH_LATENCY_1; + 413:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 414:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* else HCLK_Frequency < 24MHz default LL_FLASH_LATENCY_0 0WS */ + 415:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 416:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 417:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** else /* Scale 3 */ + 418:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(HCLK_Frequency > UTILS_SCALE3_LATENCY4_FREQ) + 420:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 421:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* 120 < HCLK <= 144 => 4WS (5 CPU cycles) */ + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** latency = LL_FLASH_LATENCY_4; + 423:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** else if(HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ) + 425:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 426:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */ + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** latency = LL_FLASH_LATENCY_3; + 428:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** else if(HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) + 430:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + ARM GAS /tmp/ccTd4L28.s page 9 + + + 431:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */ + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** latency = LL_FLASH_LATENCY_2; + 433:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 434:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** else + 435:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) + 437:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 438:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */ + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** latency = LL_FLASH_LATENCY_1; + 440:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 441:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* else HCLK_Frequency < 22MHz default LL_FLASH_LATENCY_0 0WS */ + 442:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 443:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 444:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if (status != ERROR) + 446:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** LL_FLASH_SetLatency(latency); + 448:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 449:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Check that the new number of wait states is taken into account to access the Flash + 450:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** memory by reading the FLASH_ACR register */ + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** timeout = 2; + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** do + 453:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 454:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Wait for Flash latency to be updated */ + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** getlatency = LL_FLASH_GetLatency(); + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** timeout--; + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } while ((getlatency != latency) && (timeout > 0)); + 458:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(getlatency != latency) + 460:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** status = ERROR; + 462:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 463:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** else + 464:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** status = SUCCESS; + 466:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 467:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 468:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** return status; + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 471:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 472:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** + 473:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @brief This function configures system clock at maximum frequency with HSI as clock source of + 474:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @note The application need to ensure that PLL is disabled. + 475:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @note Function is based on the following formula: + 476:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP) + 477:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz (PLLVCO_input = + 478:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output + 479:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * - PLLP: ensure that max frequency at 216000000 Hz is reach (PLLVCO_output / PLLP) + 480:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + 481:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * the configuration information for the PLL. + 482:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + 483:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * the configuration information for the BUS prescalers. + 484:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @retval An ErrorStatus enumeration value: + 485:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * - SUCCESS: Max frequency configuration done + 486:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * - ERROR: Max frequency configuration not done + 487:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + ARM GAS /tmp/ccTd4L28.s page 10 + + + 488:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + 489:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** uint32_t pllfreq = 0U; + 493:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 494:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Check if one of the PLL is enabled */ + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(UTILS_PLL_IsBusy() == SUCCESS) + 496:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 497:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Calculate the new PLL output frequency */ + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); + 499:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 500:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Enable HSI if not enabled */ + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(LL_RCC_HSI_IsReady() != 1U) + 502:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** LL_RCC_HSI_Enable(); + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** while (LL_RCC_HSI_IsReady() != 1U) + 505:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 506:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Wait for HSI ready */ + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 508:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 509:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 510:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Configure PLL */ + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruc + 512:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** UTILS_PLLInitStruct->PLLP); + 513:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 514:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Enable PLL and switch system clock to PLL */ + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + 516:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 517:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** else + 518:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 519:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Current PLL configuration cannot be modified */ + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** status = ERROR; + 521:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 522:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** return status; + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 525:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 526:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** + 527:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @brief This function configures system clock with HSE as clock source of the PLL + 528:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @note The application need to ensure that PLL is disabled. + 529:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @note Function is based on the following formula: + 530:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP) + 531:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input + 532:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output + 533:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * - PLLP: ensure that max frequency at 216000000 Hz is reached (PLLVCO_output / PLLP) + 534:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000 + 535:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @param HSEBypass This parameter can be one of the following values: + 536:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @arg @ref LL_UTILS_HSEBYPASS_ON + 537:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @arg @ref LL_UTILS_HSEBYPASS_OFF + 538:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + 539:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * the configuration information for the PLL. + 540:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + 541:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * the configuration information for the BUS prescalers. + 542:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @retval An ErrorStatus enumeration value: + 543:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * - SUCCESS: Max frequency configuration done + 544:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * - ERROR: Max frequency configuration not done + ARM GAS /tmp/ccTd4L28.s page 11 + + + 545:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 546:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + 547:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_Clk + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** uint32_t pllfreq = 0U; + 551:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 552:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Check the parameters */ + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); + 555:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 556:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Check if one of the PLL is enabled */ + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(UTILS_PLL_IsBusy() == SUCCESS) + 558:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 559:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Calculate the new PLL output frequency */ + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); + 561:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 562:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Enable HSE if not enabled */ + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(LL_RCC_HSE_IsReady() != 1U) + 564:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 565:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Check if need to enable HSE bypass feature or not */ + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(HSEBypass == LL_UTILS_HSEBYPASS_ON) + 567:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** LL_RCC_HSE_EnableBypass(); + 569:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 570:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** else + 571:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** LL_RCC_HSE_DisableBypass(); + 573:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 574:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 575:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Enable HSE */ + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** LL_RCC_HSE_Enable(); + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** while (LL_RCC_HSE_IsReady() != 1U) + 578:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 579:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Wait for HSE ready */ + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 581:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 582:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 583:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Configure PLL */ + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruc + 585:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** UTILS_PLLInitStruct->PLLP); + 586:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 587:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Enable PLL and switch system clock to PLL */ + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + 589:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 590:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** else + 591:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 592:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Current PLL configuration cannot be modified */ + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** status = ERROR; + 594:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 595:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** return status; + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 598:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 599:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** + 600:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @} + 601:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + ARM GAS /tmp/ccTd4L28.s page 12 + + + 602:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 603:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** + 604:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @} + 605:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 606:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 607:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** @addtogroup UTILS_LL_Private_Functions + 608:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @{ + 609:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 610:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** + 611:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @brief Function to check that PLL can be modified + 612:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @param PLL_InputFrequency PLL input frequency (in Hz) + 613:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + 614:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * the configuration information for the PLL. + 615:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @retval PLL output frequency (in Hz) + 616:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 617:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *U + 618:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 28 .loc 1 618 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 619:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** uint32_t pllfreq = 0U; + 33 .loc 1 619 3 view .LVU1 + 620:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 621:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Check the parameters */ + 622:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); + 34 .loc 1 622 3 view .LVU2 + 623:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN)); + 35 .loc 1 623 3 view .LVU3 + 624:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP)); + 36 .loc 1 624 3 view .LVU4 + 625:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 626:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Check different PLL parameters according to RM */ + 627:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz. */ + 628:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM + 37 .loc 1 628 3 view .LVU5 + 38 .loc 1 628 54 is_stmt 0 view .LVU6 + 39 0000 0B68 ldr r3, [r1] + 40 .loc 1 628 61 view .LVU7 + 41 0002 03F03F03 and r3, r3, #63 + 42 .loc 1 628 11 view .LVU8 + 43 0006 B0FBF3F0 udiv r0, r0, r3 + 44 .LVL1: + 629:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq)); + 45 .loc 1 629 3 is_stmt 1 view .LVU9 + 630:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 631:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz.*/ + 632:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos)); + 46 .loc 1 632 3 view .LVU10 + 47 .loc 1 632 43 is_stmt 0 view .LVU11 + 48 000a 4B68 ldr r3, [r1, #4] + 49 .loc 1 632 50 view .LVU12 + 50 000c C3F30803 ubfx r3, r3, #0, #9 + 51 .loc 1 632 11 view .LVU13 + 52 0010 03FB00F0 mul r0, r3, r0 + 53 .LVL2: + ARM GAS /tmp/ccTd4L28.s page 13 + + + 633:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq)); + 54 .loc 1 633 3 is_stmt 1 view .LVU14 + 634:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 635:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* - PLLP: ensure that max frequency at 216000000 Hz is reached */ + 636:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2); + 55 .loc 1 636 3 view .LVU15 + 56 .loc 1 636 52 is_stmt 0 view .LVU16 + 57 0014 4B89 ldrh r3, [r1, #10] + 58 .loc 1 636 77 view .LVU17 + 59 0016 0133 adds r3, r3, #1 + 60 .loc 1 636 82 view .LVU18 + 61 0018 5B00 lsls r3, r3, #1 + 62 .LVL3: + 637:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); + 63 .loc 1 637 3 is_stmt 1 view .LVU19 + 638:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 639:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** return pllfreq; + 64 .loc 1 639 3 view .LVU20 + 640:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 65 .loc 1 640 1 is_stmt 0 view .LVU21 + 66 001a B0FBF3F0 udiv r0, r0, r3 + 67 .LVL4: + 68 .loc 1 640 1 view .LVU22 + 69 001e 7047 bx lr + 70 .cfi_endproc + 71 .LFE411: + 73 .section .text.UTILS_PLL_IsBusy,"ax",%progbits + 74 .align 1 + 75 .syntax unified + 76 .thumb + 77 .thumb_func + 79 UTILS_PLL_IsBusy: + 80 .LFB412: + 641:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 642:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** + 643:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @brief Function to check that PLL can be modified + 644:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @retval An ErrorStatus enumeration value: + 645:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * - SUCCESS: PLL modification can be done + 646:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * - ERROR: PLL is busy + 647:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 648:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** static ErrorStatus UTILS_PLL_IsBusy(void) + 649:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 81 .loc 1 649 1 is_stmt 1 view -0 + 82 .cfi_startproc + 83 @ args = 0, pretend = 0, frame = 0 + 84 @ frame_needed = 0, uses_anonymous_args = 0 + 85 @ link register save eliminated. + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 86 .loc 1 650 3 view .LVU24 + 87 .LVL5: + 651:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 652:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Check if PLL is busy*/ + 653:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(LL_RCC_PLL_IsReady() != 0U) + 88 .loc 1 653 3 view .LVU25 + 89 .LBB54: + 90 .LBI54: + 91 .file 2 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h" + ARM GAS /tmp/ccTd4L28.s page 14 + + + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @file stm32f7xx_ll_rcc.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Header file of RCC LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * This software is licensed under terms that can be found in the LICENSE file in + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** ****************************************************************************** + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #ifndef __STM32F7xx_LL_RCC_H + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __STM32F7xx_LL_RCC_H + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #ifdef __cplusplus + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** extern "C" { + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Includes ------------------------------------------------------------------*/ + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #include "stm32f7xx.h" + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @addtogroup STM32F7xx_LL_Driver + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC) + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL RCC + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Private types -------------------------------------------------------------*/ + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Private variables ---------------------------------------------------------*/ + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Variables RCC Private Variables + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_DCKCFGR1_PLLSAIDIVR) + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16}; + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_DCKCFGR1_PLLSAIDIVR */ + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Private constants ---------------------------------------------------------*/ + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Private macros ------------------------------------------------------------*/ + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Macros RCC Private Macros + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + ARM GAS /tmp/ccTd4L28.s page 15 + + + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /*USE_FULL_LL_DRIVER*/ + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Exported types ------------------------------------------------------------*/ + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Types RCC Exported Types + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief RCC Clocks Frequency Structure + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** typedef struct + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } LL_RCC_ClocksTypeDef; + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */ + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Exported constants --------------------------------------------------------*/ + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Defines used to adapt values of different oscillators + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note These values could be modified in the user environment according to + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * HW set-up. + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined (HSE_VALUE) + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */ + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* HSE_VALUE */ + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined (HSI_VALUE) + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* HSI_VALUE */ + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined (LSE_VALUE) + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* LSE_VALUE */ + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + ARM GAS /tmp/ccTd4L28.s page 16 + + + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined (LSI_VALUE) + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* LSI_VALUE */ + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined (EXTERNAL_CLOCK_VALUE) + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* EXTERNAL_CLOCK_VALUE */ + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined (EXTERNAL_SAI1_CLOCK_VALUE) + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if !defined (EXTERNAL_SAI2_CLOCK_VALUE) + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* EXTERNAL_SAI2_CLOCK_VALUE */ + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Flags defines which can be used with LL_RCC_WriteReg function + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */ + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */ + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Flags defines which can be used with LL_RCC_ReadReg function + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */ + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */ + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + ARM GAS /tmp/ccTd4L28.s page 17 + + + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_IT IT Defines + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving cap + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high drivi + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low drivin + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving ca + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ + ARM GAS /tmp/ccTd4L28.s page 18 + + + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1 + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2 + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFG + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFG + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFG + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFG + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) + ARM GAS /tmp/ccTd4L28.s page 19 + + + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */ + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */ + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE cl + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */ + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE cl + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE cl + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */ + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE cl + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE cl + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE cl + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1| + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */ + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE cl + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE cl + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE cl + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1| + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE cl + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1| + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2| + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2| + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2| + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for th + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be pro + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */ + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | 0x00000000U + ARM GAS /tmp/ccTd4L28.s page 20 + + + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | 0x00000000U + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | 0x00000000U + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | 0x00000000U + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_UARTx_CLKSOURCE Peripheral UART clock source selection + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | 0x00000000U) + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_ + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_ + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_ + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | 0x00000000U) + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_ + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_ + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_ + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | 0x00000000U) + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_ + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_ + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_ + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | 0x00000000U) + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_ + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_ + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_ + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C1SEL|0x00000000U) /*!< PCLK1 + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_0 + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_1 + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C2SEL|0x00000000U) /*!< PCLK1 + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_0 + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_1 + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C3SEL|0x00000000U) /*!< PCLK1 + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_0 + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_1 + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(I2C4) + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C4_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C4SEL|0x00000000U) /*!< PCLK1 + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C4_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_0 + ARM GAS /tmp/ccTd4L28.s page 21 + + + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C4_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_1 + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* I2C4 */ + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LP + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock u + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock u + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTI + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI1SEL | 0x00000000U) + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_ + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_ + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_SAI1SEL_PLLSRC_SUPPORT) + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */ + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI2SEL | 0x00000000U) + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_ + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_ + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_SAI2SEL_PLLSRC_SUPPORT) + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */ + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SDMMCx_CLKSOURCE Peripheral SDMMC clock source selection + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | 0x00000000U) + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | (RCC_DCKCFGR2_SD + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SDMMC2) + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | 0x00000000U) + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | (RCC_DCKCFGR2_SD + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SDMMC2 */ + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as RNG clock s + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI clock used as RNG cloc + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + ARM GAS /tmp/ccTd4L28.s page 22 + + + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as USB clock s + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI1 clock used as USB clo + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI) + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR2_DSISEL /*!< PLL clock used as DSI byte lan + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */ + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(CEC) + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE_LSE 0x00000000U /*!< LSE oscillator clock + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 RCC_DCKCFGR2_CECSEL /*!< HSI oscillator clock + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* CEC */ + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock u + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator cl + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DFSDM1_Channel0) + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /*!< SAI1 clock used as D + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL /*!< SAI2 clock used as D + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + ARM GAS /tmp/ccTd4L28.s page 23 + + + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL /*!< System clock used as + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DFSDM1_Channel0 */ + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE RCC_DCKCFGR2_USART1SEL /*!< USART1 Clock source selectio + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE RCC_DCKCFGR2_USART2SEL /*!< USART2 Clock source selectio + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE RCC_DCKCFGR2_USART3SEL /*!< USART3 Clock source selectio + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USART6_CLKSOURCE RCC_DCKCFGR2_USART6SEL /*!< USART6 Clock source selectio + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_UARTx Peripheral UART get clock source + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART4_CLKSOURCE RCC_DCKCFGR2_UART4SEL /*!< UART4 Clock source selection + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART5_CLKSOURCE RCC_DCKCFGR2_UART5SEL /*!< UART5 Clock source selection + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART7_CLKSOURCE RCC_DCKCFGR2_UART7SEL /*!< UART7 Clock source selection + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_UART8_CLKSOURCE RCC_DCKCFGR2_UART8SEL /*!< UART8 Clock source selection + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2Cx Peripheral I2C get clock source + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE RCC_DCKCFGR2_I2C1SEL /*!< I2C1 Clock source selection * + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE RCC_DCKCFGR2_I2C2SEL /*!< I2C2 Clock source selection * + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C3_CLKSOURCE RCC_DCKCFGR2_I2C3SEL /*!< I2C3 Clock source selection * + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(I2C4) + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2C4_CLKSOURCE RCC_DCKCFGR2_I2C4SEL /*!< I2C4 Clock source selection * + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* I2C4 */ + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selectio + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source + ARM GAS /tmp/ccTd4L28.s page 24 + + + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR1_SAI1SEL /*!< SAI1 Clock source selection */ + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR1_SAI2SEL /*!< SAI2 Clock source selection */ + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SDMMCx Peripheral SDMMC get clock source + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC1_CLKSOURCE RCC_DCKCFGR2_SDMMC1SEL /*!< SDMMC1 Clock source selectio + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SDMMC2) + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SDMMC2_CLKSOURCE RCC_DCKCFGR2_SDMMC2SEL /*!< SDMMC2 Clock source selectio + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SDMMC2 */ + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source sel + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< RNG Clock source selection */ + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< USB Clock source selection */ + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(CEC) + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */ + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* CEC */ + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S Clock source selection */ + ARM GAS /tmp/ccTd4L28.s page 25 + + + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DFSDM1_Channel0) + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR1_ADFSDM1SEL /*!< DFSDM Audio Clock source se + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source + 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR1_DFSDM1SEL /*!< DFSDM Clock source selection + 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DFSDM1_Channel0 */ + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI) + 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source + 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR2_DSISEL /*!< DSI Clock source selection */ + 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */ + 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(LTDC) + 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR1_PLLSAIDIVR /*!< LTDC Clock source selection + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* LTDC */ + 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SPDIFRX) + 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source + 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SPDIFRX1_CLKSOURCE RCC_PLLI2SCFGR_PLLI2SP /*!< SPDIFRX Clock source select + 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SPDIFRX */ + 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock + 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used a + 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used a + ARM GAS /tmp/ccTd4L28.s page 26 + + + 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divide + 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection + 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice + 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR1_TIMPRE /*!< Timers clock to four + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source + 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL + 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL e + 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor + 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI divisio + 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI + 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI divisio + 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI + 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI + 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_P + 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI divisio + 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI + 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI + 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_P + 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI + 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P + 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P + 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P + 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI divisio + 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI + 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI + 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_P + 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI + 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P + 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P + 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P + 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI + 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI divisio + ARM GAS /tmp/ccTd4L28.s page 27 + + + 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI + 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI + 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_P + 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI + 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P + 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P + 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_P + 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI + 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_P + 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI + 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_P + 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLCFGR_PLLR) + 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR) + 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL d + 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL d + 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL d + 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL d + 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL d + 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL d + 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLCFGR_PLLR */ + 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) + 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for + 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for + 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for + 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PL + ARM GAS /tmp/ccTd4L28.s page 28 + + + 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) + 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL di + 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL di + 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL di + 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL di + 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL di + 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_ + 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL di + 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL di + 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL di + 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_ + 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL di + 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_ + 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_ + 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_ + 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection + 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spe + 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spect + 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ) + 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division fact + 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) + 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division fact + 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) + 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) + 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RC + 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division fact + 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) + 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) + 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RC + 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) + 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RC + 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RC + 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RC + 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ) + 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + ARM GAS /tmp/ccTd4L28.s page 29 + + + 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division f + 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR1_PLLI2SDIVQ_0 /*!< PLLI2S division f + 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR1_PLLI2SDIVQ_1 /*!< PLLI2S division f + 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) + 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR1_PLLI2SDIVQ_2 /*!< PLLI2S division f + 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) + 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) + 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | + 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR1_PLLI2SDIVQ_3 /*!< PLLI2S division f + 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_0) + 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1) + 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | + 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2) + 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | + 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | + 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | + 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR1_PLLI2SDIVQ_4 /*!< PLLI2S division f + 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_0) + 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1) + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | + 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2) + 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | + 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | + 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | + 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3) + 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | + 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | + 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | + 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | + 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | + 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | + 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | + 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR) + 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 + 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) + 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 + 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) + 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) + 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RC + 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLI2SCFGR_PLLI2SP) + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP) + 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PL + 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division fact + 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division fact + ARM GAS /tmp/ccTd4L28.s page 30 + + + 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) + 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLI2SCFGR_PLLI2SP */ + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ) + 920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division fact + 923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) + 924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division fact + 925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) + 926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) + 927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RC + 928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division fact + 929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) + 930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) + 931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RC + 932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) + 933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RC + 934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RC + 935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RC + 936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ) + 941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for + 944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR1_PLLSAIDIVQ_0 /*!< PLLSAI division f + 945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR1_PLLSAIDIVQ_1 /*!< PLLSAI division f + 946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) + 947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR1_PLLSAIDIVQ_2 /*!< PLLSAI division f + 948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) + 949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) + 950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | + 951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR1_PLLSAIDIVQ_3 /*!< PLLSAI division f + 952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_0) + 953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1) + 954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | + 955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2) + 956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | + 957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | + 958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | + 959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR1_PLLSAIDIVQ_4 /*!< PLLSAI division fa + 960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_0) + 961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1) + 962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | + 963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2) + 964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | + 965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | + 966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | + 967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3) + 968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | + 969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | + ARM GAS /tmp/ccTd4L28.s page 31 + + + 970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | + 971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | + 972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | + 973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | + 974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | + 975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLSAICFGR_PLLSAIR) + 980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR) + 981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 + 984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) + 985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 + 986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) + 987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) + 988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RC + 989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + 990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + 991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLSAICFGR_PLLSAIR */ + 993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_DCKCFGR1_PLLSAIDIVR) + 995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR) + 996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ + 997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ + 998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for P + 999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR1_PLLSAIDIVR_0 /*!< PLLSAI division fac +1000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR1_PLLSAIDIVR_1 /*!< PLLSAI division fac +1001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVR_1 | RCC_DCKCFGR1_PLLSAIDIVR_0) +1002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +1004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_DCKCFGR1_PLLSAIDIVR */ +1006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP) +1008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +1009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for +1011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division fact +1012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division fact +1013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) +1014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +1016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +1020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Exported macro ------------------------------------------------------------*/ +1023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros +1024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +1025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + ARM GAS /tmp/ccTd4L28.s page 32 + + +1027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros +1028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +1029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Write a value in RCC register +1033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __REG__ Register to be written +1034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __VALUE__ Value to be written in the register +1035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +1036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) +1038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Read a value in RCC register +1041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __REG__ Register to be read +1042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Register value +1043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +1045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +1047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies +1050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +1051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLCLK frequency on system domain +1055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); +1057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +1067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +1068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +1069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +1070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +1071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +1072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +1073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +1074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +1075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +1076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +1077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +1078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +1079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +1080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +1081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +1082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +1083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 + ARM GAS /tmp/ccTd4L28.s page 33 + + +1084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +1085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +1086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +1087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +1088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +1089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +1090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +1091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +1092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +1093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +1094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +1095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +1096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +1097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +1098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +1099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +1100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +1101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +1102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +1103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +1104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +1105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +1106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +1107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +1108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +1109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +1110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +1111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +1112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +1113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +1114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +1115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +1116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +1117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +1118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +1119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +1120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +1121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLN__ Between 50 and 432 +1122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLP__ This parameter can be one of the following values: +1123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_2 +1124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_4 +1125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_6 +1126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_8 +1127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) +1128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ( +1130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U)) +1131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain +1134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); +1136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 + ARM GAS /tmp/ccTd4L28.s page 34 + + +1141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +1146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +1147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +1148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +1149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +1150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +1151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +1152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +1153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +1154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +1155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +1156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +1157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +1158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +1159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +1160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +1161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +1162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +1163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +1164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +1165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +1166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +1167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +1168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +1169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +1170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +1171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +1172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +1173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +1174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +1175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +1176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +1177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +1178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +1179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +1180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +1181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +1182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +1183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +1184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +1185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +1186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +1187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +1188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +1189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +1190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +1191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +1192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +1193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +1194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +1195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +1196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +1197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 + ARM GAS /tmp/ccTd4L28.s page 35 + + +1198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +1199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +1200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLN__ Between 50 and 432 +1201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLQ__ This parameter can be one of the following values: +1202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_2 +1203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_3 +1204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_4 +1205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_5 +1206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_6 +1207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_7 +1208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_8 +1209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_9 +1210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_10 +1211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_11 +1212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_12 +1213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_13 +1214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_14 +1215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_15 +1216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) +1217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) +1219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos )) +1220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI) +1222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLCLK frequency used on DSI +1224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), +1225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); +1226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +1236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +1237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +1238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +1239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +1240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +1241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +1242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +1243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +1244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +1245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +1246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +1247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +1248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +1249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +1250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +1251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +1252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +1253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +1254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 + ARM GAS /tmp/ccTd4L28.s page 36 + + +1255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +1256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +1257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +1258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +1259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +1260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +1261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +1262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +1263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +1264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +1265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +1266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +1267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +1268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +1269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +1270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +1271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +1272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +1273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +1274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +1275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +1276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +1277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +1278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +1279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +1280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +1281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +1282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +1283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +1284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +1285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +1286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +1287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +1288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +1289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +1290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLN__ Between 50 and 432 +1291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLR__ This parameter can be one of the following values: +1292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_2 +1293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_3 +1294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_4 +1295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_5 +1296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_6 +1297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_7 +1298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) +1299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) +1301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) +1302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */ +1303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLSAI frequency used for SAI1 and SAI2 domains +1306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ +1308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 + ARM GAS /tmp/ccTd4L28.s page 37 + + +1312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +1318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +1319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +1320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +1321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +1322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +1323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +1324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +1325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +1326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +1327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +1328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +1329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +1330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +1331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +1332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +1333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +1334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +1335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +1336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +1337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +1338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +1339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +1340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +1341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +1342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +1343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +1344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +1345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +1346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +1347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +1348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +1349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +1350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +1351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +1352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +1353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +1354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +1355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +1356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +1357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +1358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +1359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +1360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +1361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +1362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +1363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +1364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +1365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +1366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +1367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +1368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 + ARM GAS /tmp/ccTd4L28.s page 38 + + +1369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +1370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +1371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +1372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLSAIN__ Between 50 and 432 +1373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLSAIQ__ This parameter can be one of the following values: +1374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_2 +1375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_3 +1376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_4 +1377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_5 +1378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_6 +1379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_7 +1380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_8 +1381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_9 +1382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_10 +1383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_11 +1384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_12 +1385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_13 +1386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_14 +1387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIQ_DIV_15 +1388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLSAIDIVQ__ This parameter can be one of the following values: +1389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 +1390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 +1391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 +1392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 +1393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 +1394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 +1395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 +1396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 +1397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 +1398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 +1399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 +1400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 +1401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 +1402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 +1403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 +1404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 +1405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 +1406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 +1407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 +1408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 +1409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 +1410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 +1411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 +1412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 +1413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 +1414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 +1415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 +1416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 +1417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 +1418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 +1419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 +1420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 +1421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PLLSAI clock frequency (in Hz) +1422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDI +1424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCF +1425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + ARM GAS /tmp/ccTd4L28.s page 39 + + +1426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain +1428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ()); +1430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +1440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +1441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +1442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +1443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +1444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +1445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +1446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +1447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +1448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +1449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +1450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +1451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +1452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +1453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +1454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +1455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +1456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +1457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +1458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +1459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +1460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +1461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +1462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +1463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +1464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +1465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +1466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +1467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +1468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +1469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +1470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +1471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +1472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +1473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +1474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +1475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +1476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +1477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +1478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +1479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +1480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +1481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +1482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 + ARM GAS /tmp/ccTd4L28.s page 40 + + +1483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +1484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +1485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +1486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +1487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +1488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +1489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +1490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +1491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +1492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +1493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +1494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLSAIN__ Between 50 and 432 +1495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLSAIP__ This parameter can be one of the following values: +1496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIP_DIV_2 +1497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIP_DIV_4 +1498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIP_DIV_6 +1499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIP_DIV_8 +1500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PLLSAI clock frequency (in Hz) +1501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUT +1503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U ) * 2U)) +1504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(LTDC) +1506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain +1508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR +1510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +1520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +1521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +1522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +1523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +1524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +1525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +1526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +1527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +1528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +1529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +1530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +1531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +1532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +1533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +1534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +1535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +1536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +1537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +1538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +1539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 + ARM GAS /tmp/ccTd4L28.s page 41 + + +1540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +1541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +1542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +1543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +1544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +1545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +1546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +1547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +1548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +1549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +1550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +1551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +1552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +1553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +1554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +1555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +1556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +1557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +1558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +1559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +1560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +1561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +1562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +1563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +1564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +1565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +1566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +1567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +1568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +1569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +1570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +1571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +1572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +1573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +1574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLSAIN__ Between 50 and 432 +1575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLSAIR__ This parameter can be one of the following values: +1576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_2 +1577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_3 +1578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_4 +1579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_5 +1580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_6 +1581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIR_DIV_7 +1582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLSAIDIVR__ This parameter can be one of the following values: +1583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 +1584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 +1585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 +1586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 +1587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PLLSAI clock frequency (in Hz) +1588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAID +1590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__P +1591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* LTDC */ +1592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLI2S frequency used for SAI1 and SAI2 domains +1595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ + ARM GAS /tmp/ccTd4L28.s page 42 + + +1597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +1607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +1608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +1609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +1610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +1611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +1612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +1613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +1614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +1615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +1616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +1617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +1618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +1619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +1620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +1621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +1622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +1623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +1624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +1625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +1626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +1627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +1628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +1629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +1630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +1631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +1632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +1633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +1634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +1635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +1636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +1637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +1638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +1639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +1640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +1641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +1642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +1643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +1644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +1645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +1646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +1647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +1648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +1649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +1650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +1651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +1652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +1653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 + ARM GAS /tmp/ccTd4L28.s page 43 + + +1654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +1655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +1656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +1657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +1658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +1659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +1660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +1661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLI2SN__ Between 50 and 432 +1662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLI2SQ__ This parameter can be one of the following values: +1663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_2 +1664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_3 +1665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_4 +1666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_5 +1667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_6 +1668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_7 +1669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_8 +1670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_9 +1671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_10 +1672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_11 +1673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_12 +1674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_13 +1675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_14 +1676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_15 +1677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLI2SDIVQ__ This parameter can be one of the following values: +1678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 +1679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 +1680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 +1681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 +1682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 +1683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 +1684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 +1685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 +1686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 +1687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 +1688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 +1689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 +1690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 +1691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 +1692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 +1693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 +1694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 +1695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 +1696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 +1697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 +1698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 +1699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 +1700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 +1701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 +1702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 +1703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 +1704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 +1705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 +1706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 +1707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 +1708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 +1709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 +1710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PLLI2S clock frequency (in Hz) + ARM GAS /tmp/ccTd4L28.s page 44 + + +1711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SDI +1713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** (((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ__) >> RCC_DCKCF +1714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SPDIFRX) +1716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain +1718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ()); +1720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +1730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +1731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +1732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +1733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +1734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +1735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +1736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +1737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +1738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +1739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +1740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +1741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +1742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +1743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +1744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +1745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +1746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +1747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +1748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +1749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +1750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +1751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +1752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +1753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +1754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +1755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +1756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +1757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +1758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +1759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +1760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +1761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +1762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +1763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +1764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +1765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +1766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +1767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 + ARM GAS /tmp/ccTd4L28.s page 45 + + +1768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +1769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +1770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +1771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +1772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +1773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +1774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +1775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +1776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +1777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +1778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +1779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +1780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +1781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +1782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +1783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +1784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLI2SN__ Between 50 and 432 +1785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLI2SP__ This parameter can be one of the following values: +1786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_2 +1787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_4 +1788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_6 +1789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_8 +1790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PLLI2S clock frequency (in Hz) +1791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__I +1793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U)) +1794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SPDIFRX */ +1795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain +1798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ()); +1800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +1810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +1811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +1812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +1813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +1814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +1815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +1816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +1817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +1818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +1819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +1820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +1821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +1822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +1823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +1824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 + ARM GAS /tmp/ccTd4L28.s page 46 + + +1825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +1826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +1827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +1828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +1829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +1830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +1831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +1832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +1833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +1834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +1835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +1836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +1837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +1838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +1839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +1840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +1841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +1842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +1843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +1844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +1845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +1846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +1847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +1848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +1849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +1850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +1851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +1852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +1853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +1854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +1855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +1856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +1857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +1858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +1859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +1860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +1861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +1862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +1863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +1864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLI2SN__ Between 50 and 432 +1865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __PLLI2SR__ This parameter can be one of the following values: +1866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_2 +1867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_3 +1868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_4 +1869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_5 +1870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_6 +1871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_7 +1872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PLLI2S clock frequency (in Hz) +1873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUT +1875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos)) +1876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the HCLK frequency +1879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) +1880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __AHBPRESCALER__ This parameter can be one of the following values: +1881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 + ARM GAS /tmp/ccTd4L28.s page 47 + + +1882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 +1883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 +1884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 +1885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 +1886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 +1887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 +1888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 +1889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 +1890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval HCLK clock frequency (in Hz) +1891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTabl +1893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PCLK1 frequency (ABP1) +1896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __HCLKFREQ__ HCLK frequency +1897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __APB1PRESCALER__ This parameter can be one of the following values: +1898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 +1899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 +1900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 +1901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 +1902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 +1903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PCLK1 clock frequency (in Hz) +1904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[ +1906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Helper macro to calculate the PCLK2 frequency (ABP2) +1909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __HCLKFREQ__ HCLK frequency +1910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param __APB2PRESCALER__ This parameter can be one of the following values: +1911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_1 +1912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_2 +1913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_4 +1914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_8 +1915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_16 +1916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval PCLK2 clock frequency (in Hz) +1917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[ +1919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +1922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +1926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /* Exported functions --------------------------------------------------------*/ +1929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions +1930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +1931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSE HSE +1934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +1935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable the Clock Security System. + ARM GAS /tmp/ccTd4L28.s page 48 + + +1939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS +1940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +1941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +1943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +1944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_CSSON); +1945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +1946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable HSE external oscillator (HSE Bypass) +1949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass +1950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +1951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +1953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSEBYP); +1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +1956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable HSE external oscillator (HSE Bypass) +1959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass +1960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +1961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +1963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +1965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +1966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable HSE crystal oscillator (HSE ON) +1969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSEON LL_RCC_HSE_Enable +1970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +1971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Enable(void) +1973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSEON); +1975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +1976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable HSE crystal oscillator (HSE ON) +1979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSEON LL_RCC_HSE_Disable +1980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +1981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Disable(void) +1983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +1984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +1985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +1986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Check if HSE oscillator Ready +1989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSERDY LL_RCC_HSE_IsReady +1990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +1993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); +1995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + ARM GAS /tmp/ccTd4L28.s page 49 + + +1996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +1997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +1998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +1999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI HSI +2002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +2003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable HSI oscillator +2007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSION LL_RCC_HSI_Enable +2008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Enable(void) +2011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSION); +2013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable HSI oscillator +2017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSION LL_RCC_HSI_Disable +2018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Disable(void) +2021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSION); +2023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Check if HSI clock is ready +2027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady +2028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval State of bit (1 or 0). +2029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +2031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); +2033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get HSI Calibration value +2037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note When HSITRIM is written, HSICAL is updated with the sum of +2038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * HSITRIM and the factory trim value +2039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration +2040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0xFF +2041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +2043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); +2045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Set HSI Calibration trimming +2049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note user-programmable trimming value that is added to the HSICAL +2050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note Default value is 16, which, when added to the HSICAL value, +2051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * should trim the HSI to 16 MHz +/- 1 % +2052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming + ARM GAS /tmp/ccTd4L28.s page 50 + + +2053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Value Between Min_Data = 0 and Max_Data = 31 +2054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +2057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); +2059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get HSI Calibration trimming +2063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming +2064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Between Min_Data = 0 and Max_Data = 31 +2065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +2067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); +2069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +2073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSE LSE +2076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +2077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable Low Speed External (LSE) crystal. +2081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR LSEON LL_RCC_LSE_Enable +2082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Enable(void) +2085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +2087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable Low Speed External (LSE) crystal. +2091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR LSEON LL_RCC_LSE_Disable +2092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Disable(void) +2095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +2097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable external clock source (LSE bypass). +2101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass +2102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +2105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +2107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + ARM GAS /tmp/ccTd4L28.s page 51 + + +2110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable external clock source (LSE bypass). +2111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass +2112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +2115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +2117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Set LSE oscillator drive capability +2121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note The oscillator is in Xtal mode when it is not in bypass mode. +2122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability +2123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param LSEDrive This parameter can be one of the following values: +2124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_LOW +2125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH +2126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW +2127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_HIGH +2128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +2131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +2133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get LSE oscillator drive capability +2137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability +2138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_LOW +2140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH +2141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW +2142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_HIGH +2143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +2145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +2147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Check if LSE oscillator Ready +2151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady +2152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval State of bit (1 or 0). +2153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +2155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); +2157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +2161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSI LSI +2164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +2165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + ARM GAS /tmp/ccTd4L28.s page 52 + + +2167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable LSI Oscillator +2169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CSR LSION LL_RCC_LSI_Enable +2170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Enable(void) +2173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_LSION); +2175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable LSI Oscillator +2179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CSR LSION LL_RCC_LSI_Disable +2180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Disable(void) +2183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +2185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Check if LSI is Ready +2189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady +2190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval State of bit (1 or 0). +2191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +2193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); +2195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +2199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_System System +2202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +2203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure the system clock source +2207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR SW LL_RCC_SetSysClkSource +2208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +2209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI +2210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE +2211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL +2212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +2215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +2217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get the system clock source +2221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR SWS LL_RCC_GetSysClkSource +2222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + ARM GAS /tmp/ccTd4L28.s page 53 + + +2224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE +2225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL +2226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +2228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +2230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Set AHB prescaler +2234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler +2235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +2236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 +2237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 +2238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 +2239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 +2240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 +2241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 +2242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 +2243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 +2244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 +2245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +2248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +2250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Set APB1 prescaler +2254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler +2255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +2256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 +2257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 +2258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 +2259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 +2260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 +2261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +2264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); +2266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Set APB2 prescaler +2270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler +2271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +2272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_1 +2273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_2 +2274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_4 +2275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_8 +2276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_16 +2277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +2280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + ARM GAS /tmp/ccTd4L28.s page 54 + + +2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); +2282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get AHB prescaler +2286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler +2287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 +2289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 +2290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 +2291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 +2292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 +2293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 +2294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 +2295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 +2296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 +2297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +2299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +2301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get APB1 prescaler +2305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler +2306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 +2308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 +2309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 +2310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 +2311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 +2312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +2314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); +2316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get APB2 prescaler +2320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler +2321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_1 +2323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_2 +2324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_4 +2325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_8 +2326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_APB2_DIV_16 +2327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +2329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); +2331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +2335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_MCO MCO + ARM GAS /tmp/ccTd4L28.s page 55 + + +2338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +2339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure MCOx +2343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n +2344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * CFGR MCO1PRE LL_RCC_ConfigMCO\n +2345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * CFGR MCO2 LL_RCC_ConfigMCO\n +2346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * CFGR MCO2PRE LL_RCC_ConfigMCO +2347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param MCOxSource This parameter can be one of the following values: +2348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSI +2349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_LSE +2350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_HSE +2351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK +2352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK +2353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S +2354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO2SOURCE_HSE +2355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK +2356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param MCOxPrescaler This parameter can be one of the following values: +2357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_1 +2358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_2 +2359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_3 +2360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_4 +2361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO1_DIV_5 +2362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO2_DIV_1 +2363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO2_DIV_2 +2364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO2_DIV_3 +2365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO2_DIV_4 +2366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_MCO2_DIV_5 +2367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +2370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << +2372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +2376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source +2379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +2380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure USARTx clock source +2384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 USART1SEL LL_RCC_SetUSARTClockSource\n +2385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 USART2SEL LL_RCC_SetUSARTClockSource\n +2386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 USART3SEL LL_RCC_SetUSARTClockSource\n +2387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 USART6SEL LL_RCC_SetUSARTClockSource +2388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param USARTxSource This parameter can be one of the following values: +2389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 +2390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK +2391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI +2392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE +2393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 +2394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK + ARM GAS /tmp/ccTd4L28.s page 56 + + +2395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI +2396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE +2397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 +2398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK +2399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI +2400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE +2401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2 +2402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK +2403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI +2404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE +2405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +2408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU)); +2410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure UARTx clock source +2414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 UART4SEL LL_RCC_SetUARTClockSource\n +2415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 UART5SEL LL_RCC_SetUARTClockSource\n +2416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 UART7SEL LL_RCC_SetUARTClockSource\n +2417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 UART8SEL LL_RCC_SetUARTClockSource +2418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param UARTxSource This parameter can be one of the following values: +2419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 +2420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK +2421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI +2422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE +2423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 +2424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK +2425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI +2426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE +2427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 +2428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK +2429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI +2430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE +2431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 +2432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK +2433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI +2434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE +2435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) +2438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU)); +2440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure I2Cx clock source +2444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 I2C1SEL LL_RCC_SetI2CClockSource\n +2445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 I2C2SEL LL_RCC_SetI2CClockSource\n +2446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 I2C3SEL LL_RCC_SetI2CClockSource\n +2447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 I2C4SEL LL_RCC_SetI2CClockSource +2448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param I2CxSource This parameter can be one of the following values: +2449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 +2450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK +2451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + ARM GAS /tmp/ccTd4L28.s page 57 + + +2452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 +2453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK +2454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI +2455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 +2456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK +2457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI +2458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*) +2459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*) +2460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) +2461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * +2462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * (*) value not defined in all devices. +2463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +2466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, (I2CxSource & 0xFFFF0000U), (I2CxSource << 16U)); +2468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure LPTIMx clock source +2472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource +2473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param LPTIMxSource This parameter can be one of the following values: +2474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 +2475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI +2476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI +2477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE +2478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) +2481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource); +2483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure SAIx clock source +2487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 SAI1SEL LL_RCC_SetSAIClockSource\n +2488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR1 SAI2SEL LL_RCC_SetSAIClockSource +2489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param SAIxSource This parameter can be one of the following values: +2490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI +2491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S +2492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN +2493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*) +2494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI +2495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S +2496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN +2497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) +2498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * +2499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * (*) value not defined in all devices. +2500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) +2503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR1, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U)); +2505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure SDMMC clock source + ARM GAS /tmp/ccTd4L28.s page 58 + + +2509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_SetSDMMCClockSource\n +2510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 SDMMC2SEL LL_RCC_SetSDMMCClockSource +2511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param SDMMCxSource This parameter can be one of the following values: +2512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK +2513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK +2514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*) +2515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*) +2516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * +2517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * (*) value not defined in all devices. +2518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource) +2521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, (SDMMCxSource & 0xFFFF0000U), (SDMMCxSource << 16U)); +2523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure 48Mhz domain clock source +2527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource +2528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param CK48MxSource This parameter can be one of the following values: +2529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL +2530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI +2531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource) +2534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource); +2536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure RNG clock source +2540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource +2541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param RNGxSource This parameter can be one of the following values: +2542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL +2543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI +2544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) +2547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource); +2549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure USB clock source +2553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource +2554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param USBxSource This parameter can be one of the following values: +2555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLL +2556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI +2557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +2560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource); +2562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(CEC) +2565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** + ARM GAS /tmp/ccTd4L28.s page 59 + + +2566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure CEC clock source +2567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource +2568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +2569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE +2570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 +2571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source) +2574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source); +2576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* CEC */ +2578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure I2S clock source +2581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource +2582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +2583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S +2584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN +2585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source) +2588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source); +2590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI) +2593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure DSI clock source +2595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 DSISEL LL_RCC_SetDSIClockSource +2596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +2597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY +2598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL +2599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) +2602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, Source); +2604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */ +2606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DFSDM1_Channel0) +2608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure DFSDM Audio clock source +2610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource +2611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +2612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 +2613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 +2614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source) +2617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, Source); +2619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure DFSDM Kernel clock source + ARM GAS /tmp/ccTd4L28.s page 60 + + +2623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_SetDFSDMClockSource +2624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +2625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 +2626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK +2627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source) +2630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, Source); +2632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DFSDM1_Channel0 */ +2634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get USARTx clock source +2637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 USART1SEL LL_RCC_GetUSARTClockSource\n +2638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 USART2SEL LL_RCC_GetUSARTClockSource\n +2639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 USART3SEL LL_RCC_GetUSARTClockSource\n +2640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 USART6SEL LL_RCC_GetUSARTClockSource +2641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param USARTx This parameter can be one of the following values: +2642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE +2643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE +2644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE +2645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART6_CLKSOURCE +2646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 +2648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK +2649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI +2650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE +2651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 +2652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK +2653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI +2654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE +2655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 +2656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK +2657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI +2658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE +2659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2 +2660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK +2661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI +2662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE +2663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +2665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USARTx) | (USARTx << 16U)); +2667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get UARTx clock source +2671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 UART4SEL LL_RCC_GetUARTClockSource\n +2672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 UART5SEL LL_RCC_GetUARTClockSource\n +2673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 UART7SEL LL_RCC_GetUARTClockSource\n +2674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 UART8SEL LL_RCC_GetUARTClockSource +2675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param UARTx This parameter can be one of the following values: +2676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART4_CLKSOURCE +2677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART5_CLKSOURCE +2678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART7_CLKSOURCE +2679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART8_CLKSOURCE + ARM GAS /tmp/ccTd4L28.s page 61 + + +2680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 +2682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK +2683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI +2684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE +2685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 +2686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK +2687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI +2688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE +2689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 +2690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK +2691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI +2692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE +2693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 +2694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK +2695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI +2696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE +2697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) +2699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR2, UARTx) | (UARTx << 16U)); +2701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get I2Cx clock source +2705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 I2C1SEL LL_RCC_GetI2CClockSource\n +2706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 I2C2SEL LL_RCC_GetI2CClockSource\n +2707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 I2C3SEL LL_RCC_GetI2CClockSource\n +2708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 I2C4SEL LL_RCC_GetI2CClockSource +2709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param I2Cx This parameter can be one of the following values: +2710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE +2711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C2_CLKSOURCE +2712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE +2713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C4_CLKSOURCE (*) +2714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 +2716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK +2717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI +2718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 +2719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK +2720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI +2721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 +2722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK +2723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI +2724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*) +2725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*) +2726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) +2727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * +2728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * (*) value not defined in all devices. +2729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +2731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)((READ_BIT(RCC->DCKCFGR2, I2Cx) >> 16U) | I2Cx); +2733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get LPTIMx clock source + ARM GAS /tmp/ccTd4L28.s page 62 + + +2737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource +2738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param LPTIMx This parameter can be one of the following values: +2739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE +2740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 +2742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI +2743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI +2744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE +2745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) +2747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)); +2749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get SAIx clock source +2753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 SAI1SEL LL_RCC_GetSAIClockSource\n +2754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR1 SAI2SEL LL_RCC_GetSAIClockSource +2755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param SAIx This parameter can be one of the following values: +2756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI1_CLKSOURCE +2757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI2_CLKSOURCE +2758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI +2760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S +2761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN +2762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*) +2763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI +2764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S +2765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN +2766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) +2767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * +2768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * (*) value not defined in all devices. +2769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) +2771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR1, SAIx) >> 16U | SAIx); +2773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get SDMMCx clock source +2777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_GetSDMMCClockSource\n +2778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR2 SDMMC2SEL LL_RCC_GetSDMMCClockSource +2779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param SDMMCx This parameter can be one of the following values: +2780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC1_CLKSOURCE +2781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC1_CLKSOURCE (*) +2782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK +2784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK +2785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*) +2786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*) +2787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * +2788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * (*) value not defined in all devices. +2789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx) +2791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDMMCx) >> 16U | SDMMCx); +2793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + ARM GAS /tmp/ccTd4L28.s page 63 + + +2794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get 48Mhz domain clock source +2797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource +2798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param CK48Mx This parameter can be one of the following values: +2799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CK48M_CLKSOURCE +2800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL +2802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI +2803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx) +2805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx)); +2807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get RNGx clock source +2811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource +2812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param RNGx This parameter can be one of the following values: +2813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE +2814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL +2816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI +2817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) +2819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx)); +2821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get USBx clock source +2825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource +2826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param USBx This parameter can be one of the following values: +2827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE +2828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLL +2830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI +2831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +2833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx)); +2835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(CEC) +2838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get CEC Clock Source +2840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource +2841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param CECx This parameter can be one of the following values: +2842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE +2843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE +2845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 +2846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) +2848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx)); +2850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + ARM GAS /tmp/ccTd4L28.s page 64 + + +2851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* CEC */ +2852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get I2S Clock Source +2855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource +2856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param I2Sx This parameter can be one of the following values: +2857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S1_CLKSOURCE +2858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S +2860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN +2861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) +2863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx)); +2865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DFSDM1_Channel0) +2868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get DFSDM Audio Clock Source +2870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource +2871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param DFSDMx This parameter can be one of the following values: +2872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE +2873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 +2875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 +2876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx) +2878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx)); +2880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get DFSDM Audio Clock Source +2884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_GetDFSDMClockSource +2885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param DFSDMx This parameter can be one of the following values: +2886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_CLKSOURCE +2887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 +2889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK +2890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx) +2892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx)); +2894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DFSDM1_Channel0 */ +2896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI) +2898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get DSI Clock Source +2900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR2 DSISEL LL_RCC_GetDSIClockSource +2901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param DSIx This parameter can be one of the following values: +2902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DSI_CLKSOURCE +2903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY +2905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL +2906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) + ARM GAS /tmp/ccTd4L28.s page 65 + + +2908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR2, DSIx)); +2910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */ +2912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +2915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_RTC RTC +2918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +2919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Set RTC Clock Source +2923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note Once the RTC clock source has been selected, it cannot be changed anymore unless +2924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is +2925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * set). The BDRST bit can be used to reset them. +2926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource +2927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +2928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE +2929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE +2930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI +2931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE +2932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +2935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +2937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get RTC Clock Source +2941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource +2942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +2943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE +2944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE +2945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI +2946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE +2947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +2949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +2951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable RTC +2955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR RTCEN LL_RCC_EnableRTC +2956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_EnableRTC(void) +2959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +2961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable RTC + ARM GAS /tmp/ccTd4L28.s page 66 + + +2965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR RTCEN LL_RCC_DisableRTC +2966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_DisableRTC(void) +2969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +2971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Check if RTC has been enabled or not +2975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC +2976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval State of bit (1 or 0). +2977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +2979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); +2981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Force the Backup domain reset +2985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset +2986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +2989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +2990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +2991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +2992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +2993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +2994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Release the Backup domain reset +2995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset +2996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +2997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +2998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +2999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +3001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Set HSE Prescalers for RTC Clock +3005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler +3006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +3007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_NOCLOCK +3008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_2 +3009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_3 +3010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_4 +3011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_5 +3012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_6 +3013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_7 +3014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_8 +3015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_9 +3016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_10 +3017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_11 +3018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_12 +3019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_13 +3020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_14 +3021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_15 + ARM GAS /tmp/ccTd4L28.s page 67 + + +3022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_16 +3023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_17 +3024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_18 +3025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_19 +3026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_20 +3027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_21 +3028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_22 +3029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_23 +3030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_24 +3031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_25 +3032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_26 +3033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_27 +3034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_28 +3035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_29 +3036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_30 +3037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_31 +3038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler) +3041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler); +3043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get HSE Prescalers for RTC Clock +3047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler +3048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +3049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_NOCLOCK +3050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_2 +3051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_3 +3052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_4 +3053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_5 +3054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_6 +3055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_7 +3056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_8 +3057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_9 +3058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_10 +3059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_11 +3060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_12 +3061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_13 +3062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_14 +3063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_15 +3064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_16 +3065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_17 +3066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_18 +3067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_19 +3068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_20 +3069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_21 +3070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_22 +3071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_23 +3072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_24 +3073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_25 +3074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_26 +3075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_27 +3076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_28 +3077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_29 +3078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_30 + ARM GAS /tmp/ccTd4L28.s page 68 + + +3079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_RTC_HSE_DIV_31 +3080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) +3082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)); +3084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +3088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM +3091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +3092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Set Timers Clock Prescalers +3096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 TIMPRE LL_RCC_SetTIMPrescaler +3097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +3098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_TIM_PRESCALER_TWICE +3099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES +3100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler) +3103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE, Prescaler); +3105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get Timers Clock Prescalers +3109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 TIMPRE LL_RCC_GetTIMPrescaler +3110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +3111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_TIM_PRESCALER_TWICE +3112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES +3113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void) +3115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE)); +3117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +3121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_PLL PLL +3124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +3125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable PLL +3129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR PLLON LL_RCC_PLL_Enable +3130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_Enable(void) +3133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_PLLON); +3135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + ARM GAS /tmp/ccTd4L28.s page 69 + + +3136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable PLL +3139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note Cannot be disabled if the PLL clock is used as the system clock +3140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR PLLON LL_RCC_PLL_Disable +3141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_Disable(void) +3144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +3146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Check if PLL Ready +3150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady +3151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval State of bit (1 or 0). +3152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) + 92 .loc 2 3153 26 view .LVU26 + 93 .LBB55: +3154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); + 94 .loc 2 3155 3 view .LVU27 + 95 .loc 2 3155 11 is_stmt 0 view .LVU28 + 96 0000 0A4B ldr r3, .L9 + 97 0002 1B68 ldr r3, [r3] + 98 .LBE55: + 99 .LBE54: + 100 .loc 1 653 5 discriminator 1 view .LVU29 + 101 0004 13F0007F tst r3, #33554432 + 102 0008 0DD1 bne .L6 + 650:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 103 .loc 1 650 15 view .LVU30 + 104 000a 0020 movs r0, #0 + 105 .L3: + 106 .LVL6: + 654:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 655:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* PLL configuration cannot be modified */ + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** status = ERROR; + 657:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 658:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 659:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Check if PLLSAI is busy*/ + 660:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(LL_RCC_PLLSAI_IsReady() != 0U) + 107 .loc 1 660 3 is_stmt 1 view .LVU31 + 108 .LBB56: + 109 .LBI56: +3156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure PLL used for SYSCLK Domain +3160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLL Source and PLLM Divider can be written only when PLL, +3161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2S and PLLSAI are disabled +3162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLLN/PLLP can be written only when PLL is disabled +3163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n +3164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n +3165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n +3166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS + ARM GAS /tmp/ccTd4L28.s page 70 + + +3167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +3168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +3169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +3170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLM This parameter can be one of the following values: +3171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +3172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +3173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +3174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +3175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +3176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +3177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +3178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +3179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +3180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +3181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +3182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +3183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +3184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +3185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +3186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +3187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +3188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +3189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +3190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +3191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +3192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +3193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +3194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +3195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +3196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +3197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +3198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +3199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +3200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +3201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +3202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +3203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +3204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +3205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +3206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +3207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +3208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +3209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +3210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +3211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +3212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +3213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +3214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +3215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +3216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +3217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +3218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +3219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +3220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +3221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +3222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +3223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 + ARM GAS /tmp/ccTd4L28.s page 71 + + +3224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +3225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +3226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +3227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +3228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +3229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +3230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +3231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +3232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +3233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLN Between 50 and 432 +3234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLP This parameter can be one of the following values: +3235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_2 +3236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_4 +3237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_6 +3238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_8 +3239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uin +3242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_P +3244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); +3245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure PLL used for 48Mhz domain clock +3249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLL Source and PLLM Divider can be written only when PLL, +3250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2S and PLLSAI are disabled +3251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLLN/PLLQ can be written only when PLL is disabled +3252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note This can be selected for USB, RNG, SDMMC1 +3253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n +3254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n +3255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n +3256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M +3257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +3258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +3259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +3260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLM This parameter can be one of the following values: +3261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +3262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +3263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +3264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +3265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +3266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +3267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +3268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +3269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +3270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +3271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +3272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +3273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +3274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +3275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +3276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +3277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +3278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +3279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +3280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 + ARM GAS /tmp/ccTd4L28.s page 72 + + +3281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +3282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +3283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +3284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +3285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +3286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +3287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +3288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +3289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +3290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +3291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +3292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +3293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +3294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +3295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +3296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +3297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +3298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +3299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +3300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +3301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +3302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +3303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +3304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +3305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +3306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +3307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +3308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +3309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +3310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +3311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +3312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +3313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +3314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +3315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +3316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +3317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +3318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +3319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +3320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +3321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +3322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +3323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLN Between 50 and 432 +3324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLQ This parameter can be one of the following values: +3325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_2 +3326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_3 +3327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_4 +3328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_5 +3329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_6 +3330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_7 +3331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_8 +3332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_9 +3333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_10 +3334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_11 +3335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_12 +3336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_13 +3337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_14 + ARM GAS /tmp/ccTd4L28.s page 73 + + +3338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_15 +3339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uin +3342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_P +3344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ); +3345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(DSI) +3348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure PLL used for DSI clock +3350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLL Source and PLLM Divider can be written only when PLL, +3351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2S and PLLSAI are disabled +3352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLLN/PLLR can be written only when PLL is disabled +3353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note This can be selected for DSI +3354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n +3355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n +3356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n +3357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI +3358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +3359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +3360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +3361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLM This parameter can be one of the following values: +3362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +3363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +3364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +3365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +3366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +3367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +3368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +3369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +3370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +3371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +3372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +3373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +3374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +3375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +3376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +3377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +3378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +3379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +3380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +3381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +3382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +3383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +3384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +3385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +3386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +3387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +3388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +3389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +3390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +3391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +3392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +3393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +3394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 + ARM GAS /tmp/ccTd4L28.s page 74 + + +3395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +3396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +3397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +3398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +3399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +3400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +3401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +3402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +3403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +3404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +3405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +3406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +3407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +3408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +3409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +3410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +3411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +3412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +3413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +3414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +3415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +3416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +3417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +3418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +3419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +3420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +3421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +3422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +3423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +3424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLN Between 50 and 432 +3425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLR This parameter can be one of the following values: +3426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_2 +3427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_3 +3428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_4 +3429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_5 +3430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_6 +3431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_7 +3432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uin +3435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_P +3437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); +3438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* DSI */ +3440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure PLL clock source +3443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource +3444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLSource This parameter can be one of the following values: +3445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +3446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +3447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +3450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); + ARM GAS /tmp/ccTd4L28.s page 75 + + +3452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get the oscillator used as PLL clock source. +3456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource +3457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +3458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +3459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +3460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +3462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +3464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get Main PLL multiplication factor for VCO +3468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN +3469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Between 50 and 432 +3470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) +3472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); +3474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get Main PLL division factor for PLLP +3478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP +3479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +3480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_2 +3481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_4 +3482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_6 +3483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_8 +3484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) +3486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); +3488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get Main PLL division factor for PLLQ +3492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note used for PLL48MCLK selected for USB, RNG, SDMMC (48 MHz clock) +3493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ +3494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +3495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_2 +3496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_3 +3497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_4 +3498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_5 +3499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_6 +3500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_7 +3501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_8 +3502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_9 +3503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_10 +3504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_11 +3505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_12 +3506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_13 +3507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_14 +3508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_15 + ARM GAS /tmp/ccTd4L28.s page 76 + + +3509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) +3511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)); +3513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLCFGR_PLLR) +3516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get Main PLL division factor for PLLR +3518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note used for PLLCLK (system clock) +3519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR +3520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +3521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_2 +3522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_3 +3523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_4 +3524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_5 +3525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_6 +3526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_7 +3527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) +3529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); +3531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLCFGR_PLLR */ +3533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get Division factor for the main PLL and other PLL +3536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider +3537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +3538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +3539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +3540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +3541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +3542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +3543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +3544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +3545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +3546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +3547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +3548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +3549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +3550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +3551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +3552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +3553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +3554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +3555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +3556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +3557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +3558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +3559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +3560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +3561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +3562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +3563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +3564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +3565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 + ARM GAS /tmp/ccTd4L28.s page 77 + + +3566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +3567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +3568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +3569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +3570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +3571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +3572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +3573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +3574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +3575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +3576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +3577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +3578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +3579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +3580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +3581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +3582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +3583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +3584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +3585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +3586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +3587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +3588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +3589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +3590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +3591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +3592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +3593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +3594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +3595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +3596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +3597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +3598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +3599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +3600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) +3602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); +3604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure Spread Spectrum used for PLL +3608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note These bits must be written before enabling PLL +3609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n +3610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n +3611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum +3612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Mod Between Min_Data=0 and Max_Data=8191 +3613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Inc Between Min_Data=0 and Max_Data=32767 +3614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Sel This parameter can be one of the following values: +3615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SPREAD_SELECT_CENTER +3616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SPREAD_SELECT_DOWN +3617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel) +3620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << +3622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + ARM GAS /tmp/ccTd4L28.s page 78 + + +3623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get Spread Spectrum Modulation Period for PLL +3626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation +3627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Between Min_Data=0 and Max_Data=8191 +3628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void) +3630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER)); +3632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get Spread Spectrum Incrementation Step for PLL +3636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note Must be written before enabling PLL +3637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation +3638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Between Min_Data=0 and Max_Data=32767 +3639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void) +3641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos); +3643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get Spread Spectrum Selection for PLL +3647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note Must be written before enabling PLL +3648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection +3649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +3650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SPREAD_SELECT_CENTER +3651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_SPREAD_SELECT_DOWN +3652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void) +3654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL)); +3656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable Spread Spectrum for PLL. +3660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable +3661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void) +3664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); +3666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable Spread Spectrum for PLL. +3670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable +3671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void) +3674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); +3676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} + ARM GAS /tmp/ccTd4L28.s page 79 + + +3680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_PLLI2S PLLI2S +3683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +3684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable PLLI2S +3688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable +3689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void) +3692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_PLLI2SON); +3694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable PLLI2S +3698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable +3699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void) +3702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); +3704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Check if PLLI2S Ready +3708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady +3709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval State of bit (1 or 0). +3710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void) +3712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY)); +3714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure PLLI2S used for SAI1 and SAI2 domain clock +3718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLL Source and PLLM Divider can be written only when PLL, +3719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2S and PLLSAI are disabled +3720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLLN/PLLQ can be written only when PLLI2S is disabled +3721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note This can be selected for SAI1 and SAI2 +3722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n +3723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n +3724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n +3725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n +3726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI +3727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +3728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +3729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +3730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLM This parameter can be one of the following values: +3731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +3732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +3733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +3734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +3735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +3736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 + ARM GAS /tmp/ccTd4L28.s page 80 + + +3737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +3738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +3739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +3740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +3741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +3742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +3743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +3744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +3745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +3746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +3747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +3748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +3749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +3750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +3751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +3752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +3753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +3754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +3755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +3756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +3757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +3758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +3759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +3760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +3761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +3762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +3763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +3764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +3765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +3766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +3767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +3768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +3769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +3770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +3771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +3772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +3773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +3774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +3775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +3776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +3777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +3778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +3779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +3780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +3781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +3782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +3783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +3784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +3785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +3786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +3787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +3788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +3789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +3790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +3791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +3792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +3793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLN Between 50 and 432 + ARM GAS /tmp/ccTd4L28.s page 81 + + +3794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLQ This parameter can be one of the following values: +3795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_2 +3796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_3 +3797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_4 +3798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_5 +3799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_6 +3800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_7 +3801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_8 +3802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_9 +3803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_10 +3804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_11 +3805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_12 +3806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_13 +3807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_14 +3808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_15 +3809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLDIVQ This parameter can be one of the following values: +3810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 +3811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 +3812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 +3813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 +3814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 +3815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 +3816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 +3817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 +3818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 +3819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 +3820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 +3821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 +3822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 +3823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 +3824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 +3825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 +3826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 +3827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 +3828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 +3829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 +3830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 +3831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 +3832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 +3833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 +3834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 +3835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 +3836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 +3837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 +3838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 +3839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 +3840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 +3841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 +3842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, +3845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); +3847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCF +3848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, PLLDIVQ); +3849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + ARM GAS /tmp/ccTd4L28.s page 82 + + +3851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(SPDIFRX) +3852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure PLLI2S used for SPDIFRX domain clock +3854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLL Source and PLLM Divider can be written only when PLL, +3855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2S and PLLSAI are disabled +3856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLLN/PLLP can be written only when PLLI2S is disabled +3857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note This can be selected for SPDIFRX +3858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n +3859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n +3860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n +3861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX +3862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +3863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +3864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +3865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLM This parameter can be one of the following values: +3866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +3867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +3868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +3869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +3870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +3871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +3872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +3873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 +3874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +3875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +3876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +3877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +3878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +3879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +3880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +3881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +3882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +3883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +3884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +3885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +3886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +3887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +3888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +3889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +3890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +3891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +3892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +3893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +3894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +3895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +3896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +3897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +3898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +3899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +3900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +3901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +3902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +3903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +3904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +3905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +3906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +3907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 + ARM GAS /tmp/ccTd4L28.s page 83 + + +3908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +3909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +3910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +3911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +3912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +3913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +3914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +3915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +3916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +3917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +3918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +3919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +3920:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +3921:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +3922:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +3923:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +3924:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +3925:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +3926:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +3927:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +3928:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLN Between 50 and 432 +3929:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLP This parameter can be one of the following values: +3930:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_2 +3931:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_4 +3932:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_6 +3933:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_8 +3934:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +3935:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +3936:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PL +3937:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +3938:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); +3939:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCF +3940:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +3941:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* SPDIFRX */ +3942:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +3943:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +3944:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Configure PLLI2S used for I2S1 domain clock +3945:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLL Source and PLLM Divider can be written only when PLL, +3946:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2S and PLLSAI are disabled +3947:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note PLLN/PLLR can be written only when PLLI2S is disabled +3948:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note This can be selected for I2S +3949:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n +3950:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n +3951:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n +3952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S +3953:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +3954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSI +3955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLSOURCE_HSE +3956:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLM This parameter can be one of the following values: +3957:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +3958:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +3959:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +3960:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +3961:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +3962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +3963:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +3964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_9 + ARM GAS /tmp/ccTd4L28.s page 84 + + +3965:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_10 +3966:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_11 +3967:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_12 +3968:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_13 +3969:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_14 +3970:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_15 +3971:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_16 +3972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_17 +3973:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_18 +3974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_19 +3975:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_20 +3976:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_21 +3977:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_22 +3978:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_23 +3979:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_24 +3980:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_25 +3981:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_26 +3982:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_27 +3983:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_28 +3984:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_29 +3985:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_30 +3986:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_31 +3987:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_32 +3988:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_33 +3989:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_34 +3990:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_35 +3991:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_36 +3992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_37 +3993:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_38 +3994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_39 +3995:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_40 +3996:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_41 +3997:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_42 +3998:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_43 +3999:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_44 +4000:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_45 +4001:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_46 +4002:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_47 +4003:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_48 +4004:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_49 +4005:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_50 +4006:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_51 +4007:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_52 +4008:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_53 +4009:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_54 +4010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_55 +4011:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_56 +4012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_57 +4013:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_58 +4014:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_59 +4015:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_60 +4016:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_61 +4017:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_62 +4018:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_63 +4019:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLN Between 50 and 432 +4020:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @param PLLR This parameter can be one of the following values: +4021:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_2 + ARM GAS /tmp/ccTd4L28.s page 85 + + +4022:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_3 +4023:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_4 +4024:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_5 +4025:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_6 +4026:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_7 +4027:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +4028:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4029:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, +4030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4031:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); +4032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCF +4033:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4034:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4035:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4036:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get I2SPLL multiplication factor for VCO +4037:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN +4038:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Between 50 and 432 +4039:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4040:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void) +4041:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4042:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos +4043:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4044:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4045:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4046:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get I2SPLL division factor for PLLI2SQ +4047:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ +4048:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +4049:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_2 +4050:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_3 +4051:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_4 +4052:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_5 +4053:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_6 +4054:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_7 +4055:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_8 +4056:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_9 +4057:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_10 +4058:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_11 +4059:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_12 +4060:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_13 +4061:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_14 +4062:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SQ_DIV_15 +4063:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4064:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void) +4065:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4066:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ)); +4067:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4068:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4069:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4070:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get I2SPLL division factor for PLLI2SR +4071:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note used for PLLI2SCLK (I2S clock) +4072:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR +4073:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +4074:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_2 +4075:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_3 +4076:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_4 +4077:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_5 +4078:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_6 + ARM GAS /tmp/ccTd4L28.s page 86 + + +4079:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SR_DIV_7 +4080:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4081:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void) +4082:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4083:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR)); +4084:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4085:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4086:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #if defined(RCC_PLLI2SCFGR_PLLI2SP) +4087:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4088:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get I2SPLL division factor for PLLI2SP +4089:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note used for PLLSPDIFRXCLK (SPDIFRX clock) +4090:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP +4091:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +4092:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_2 +4093:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_4 +4094:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_6 +4095:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SP_DIV_8 +4096:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4097:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void) +4098:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4099:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP)); +4100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** #endif /* RCC_PLLI2SCFGR_PLLI2SP */ +4102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Get I2SPLL division factor for PLLI2SDIVQ +4105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock) +4106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ +4107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +4108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 +4109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 +4110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 +4111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 +4112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 +4113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 +4114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 +4115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 +4116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 +4117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 +4118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 +4119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 +4120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 +4121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 +4122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 +4123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 +4124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 +4125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 +4126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 +4127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 +4128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 +4129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 +4130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 +4131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 +4132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 +4133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 +4134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 +4135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 + ARM GAS /tmp/ccTd4L28.s page 87 + + +4136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 +4137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 +4138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 +4139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 +4140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void) +4142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ)); +4144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @} +4148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_PLLSAI PLLSAI +4151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @{ +4152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Enable PLLSAI +4156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable +4157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +4158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLSAI_Enable(void) +4160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_PLLSAION); +4162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Disable PLLSAI +4166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable +4167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval None +4168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_PLLSAI_Disable(void) +4170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); +4172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } +4173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** +4174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** /** +4175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @brief Check if PLLSAI Ready +4176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady +4177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** * @retval State of bit (1 or 0). +4178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** */ +4179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void) + 110 .loc 2 4179 26 view .LVU32 + 111 .LBB57: +4180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { +4181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY)); + 112 .loc 2 4181 3 view .LVU33 + 113 .loc 2 4181 11 is_stmt 0 view .LVU34 + 114 000c 074B ldr r3, .L9 + 115 000e 1B68 ldr r3, [r3] + 116 .LBE57: + 117 .LBE56: + 118 .loc 1 660 5 discriminator 1 view .LVU35 + 119 0010 13F0005F tst r3, #536870912 + 120 0014 00D0 beq .L4 + ARM GAS /tmp/ccTd4L28.s page 88 + + + 661:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 662:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* PLLSAI1 configuration cannot be modified */ + 663:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** status = ERROR; + 121 .loc 1 663 12 view .LVU36 + 122 0016 0120 movs r0, #1 + 123 .LVL7: + 124 .L4: + 664:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 665:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Check if PLLI2S is busy*/ + 666:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(LL_RCC_PLLI2S_IsReady() != 0U) + 125 .loc 1 666 3 is_stmt 1 view .LVU37 + 126 .LBB58: + 127 .LBI58: +3711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 128 .loc 2 3711 26 view .LVU38 + 129 .LBB59: +3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 130 .loc 2 3713 3 view .LVU39 +3713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 131 .loc 2 3713 11 is_stmt 0 view .LVU40 + 132 0018 044B ldr r3, .L9 + 133 001a 1B68 ldr r3, [r3] + 134 .LBE59: + 135 .LBE58: + 136 .loc 1 666 5 discriminator 1 view .LVU41 + 137 001c 13F0006F tst r3, #134217728 + 138 0020 00D0 beq .L5 + 667:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 668:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* PLLI2S configuration cannot be modified */ + 669:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** status = ERROR; + 139 .loc 1 669 12 view .LVU42 + 140 0022 0120 movs r0, #1 + 141 .LVL8: + 142 .L5: + 670:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 671:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** return status; + 143 .loc 1 671 3 is_stmt 1 view .LVU43 + 672:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 144 .loc 1 672 1 is_stmt 0 view .LVU44 + 145 0024 7047 bx lr + 146 .LVL9: + 147 .L6: + 656:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 148 .loc 1 656 12 view .LVU45 + 149 0026 0120 movs r0, #1 + 150 0028 F0E7 b .L3 + 151 .L10: + 152 002a 00BF .align 2 + 153 .L9: + 154 002c 00380240 .word 1073887232 + 155 .cfi_endproc + 156 .LFE412: + 158 .section .text.LL_Init1msTick,"ax",%progbits + 159 .align 1 + 160 .global LL_Init1msTick + 161 .syntax unified + 162 .thumb + ARM GAS /tmp/ccTd4L28.s page 89 + + + 163 .thumb_func + 165 LL_Init1msTick: + 166 .LVL10: + 167 .LFB405: + 219:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Use frequency provided in argument */ + 168 .loc 1 219 1 is_stmt 1 view -0 + 169 .cfi_startproc + 170 @ args = 0, pretend = 0, frame = 0 + 171 @ frame_needed = 0, uses_anonymous_args = 0 + 172 @ link register save eliminated. + 221:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 173 .loc 1 221 3 view .LVU47 + 174 .LBB60: + 175 .LBI60: + 176 .file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @file stm32f7xx_ll_utils.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @brief Header file of UTILS LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** @verbatim + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** ============================================================================== + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** ##### How to use this driver ##### + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** ============================================================================== + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** [..] + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** The LL UTILS driver contains a set of generic APIs that can be + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** used by user: + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** (+) Device electronic signature + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** (+) Timing functions + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** (+) PLL configuration functions + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** @endverbatim + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** ****************************************************************************** + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @attention + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * Copyright (c) 2017 STMicroelectronics. + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * All rights reserved. + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * This software is licensed under terms that can be found in the LICENSE file + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * in the root directory of this software component. + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** ****************************************************************************** + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #ifndef __STM32F7xx_LL_UTILS_H + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define __STM32F7xx_LL_UTILS_H + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #ifdef __cplusplus + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** extern "C" { + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #endif + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Includes ------------------------------------------------------------------*/ + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #include "stm32f7xx.h" + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @addtogroup STM32F7xx_LL_Driver + ARM GAS /tmp/ccTd4L28.s page 90 + + + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @{ + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_LL UTILS + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @{ + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Private types -------------------------------------------------------------*/ + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Private variables ---------------------------------------------------------*/ + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Private constants ---------------------------------------------------------*/ + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @{ + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Max delay can be used in LL_mDelay */ + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_MAX_DELAY 0xFFFFFFFFU + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @brief Unique device ID register base address + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define UID_BASE_ADDRESS UID_BASE + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @brief Flash size data register base address + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @brief Package data register base address + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define PACKAGE_BASE_ADDRESS PACKAGE_BASE + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @} + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Private macros ------------------------------------------------------------*/ + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @{ + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @} + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Exported types ------------------------------------------------------------*/ + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @{ + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @brief UTILS PLL structure definition + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** typedef struct + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** { + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** uint32_t PLLM; /*!< Division factor for PLL VCO input clock. + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** This feature can be modified afterwards using unitary function + ARM GAS /tmp/ccTd4L28.s page 91 + + + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** This parameter must be a number between Min_Data = 50 and Max_Data = 432 + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** This feature can be modified afterwards using unitary function + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** uint32_t PLLP; /*!< Division for the main system clock. + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** This feature can be modified afterwards using unitary function + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** } LL_UTILS_PLLInitTypeDef; + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @brief UTILS System, AHB and APB buses clock configuration structure definition + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** typedef struct + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** { + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** This feature can be modified afterwards using unitary functi + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** @ref LL_RCC_SetAHBPrescaler(). */ + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from t + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** This feature can be modified afterwards using unitary functi + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** @ref LL_RCC_SetAPB1Prescaler(). */ + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from t + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** This feature can be modified afterwards using unitary functi + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** @ref LL_RCC_SetAPB2Prescaler(). */ + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** } LL_UTILS_ClkInitTypeDef; + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @} + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Exported constants --------------------------------------------------------*/ + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @{ + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @{ + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @} + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + ARM GAS /tmp/ccTd4L28.s page 92 + + + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @{ + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_UTILS_PACKAGETYPE_LQFP100 0x00000100U /*!< LQFP100 package type + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_UTILS_PACKAGETYPE_LQFP144_WLCSP143 0x00000200U /*!< LQFP144 or WLCSP143 packag + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_UTILS_PACKAGETYPE_WLCSP180_LQFP176_UFBGA176 0x00000300U /*!< WLCSP180, LQFP176 or UFBGA + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_UTILS_PACKAGETYPE_LQFP176_LQFP208_TFBGA216 0x00000400U /*!< LQFP176, LQFP208 or TFBGA2 + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_UTILS_PACKAGETYPE_TFBGA216_LQFP176_LQFP208 0x00000500U /*!< LQFP176, LQFP208 or TFBGA2 + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_UTILS_PACKAGETYPE_LQFP176_TFBGA216_LQFP208 0x00000600U /*!< LQFP176, LQFP208 or TFBGA2 + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** #define LL_UTILS_PACKAGETYPE_LQFP208_LQFP176_TFBGA216 0x00000700U /*!< LQFP176, LQFP208 or TFBGA2 + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @} + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @} + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Exported macro ------------------------------------------------------------*/ + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Exported functions --------------------------------------------------------*/ + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @{ + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @{ + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @retval UID[31:0] + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** __STATIC_INLINE uint32_t LL_GetUID_Word0(void) + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** { + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** } + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @retval UID[63:32] + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** __STATIC_INLINE uint32_t LL_GetUID_Word1(void) + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** { + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** } + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @retval UID[95:64] + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** __STATIC_INLINE uint32_t LL_GetUID_Word2(void) + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** { + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** } + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + ARM GAS /tmp/ccTd4L28.s page 93 + + + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @brief Get Flash memory size + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @note This bitfield indicates the size of the device Flash memory expressed in + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @retval FLASH_SIZE[15:0]: Flash memory size + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** __STATIC_INLINE uint32_t LL_GetFlashSize(void) + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** { + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU); + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** } + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @brief Get Package type + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @retval Returned value can be one of the following values: + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100 + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_WLCSP143 (*) + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP180_LQFP176_UFBGA176 (*) + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_LQFP208_TFBGA216 (*) + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * (*) value not defined in all devices. + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** __STATIC_INLINE uint32_t LL_GetPackageType(void) + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** { + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U); + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** } + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @} + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** @defgroup UTILS_LL_EF_DELAY DELAY + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @{ + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /** + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @brief This function configures the Cortex-M SysTick source of the time base. + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @note When a RTOS is used, it is recommended to avoid changing the SysTick + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * configuration by calling this function, for a delay use rather osDelay RTOS service. + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @param Ticks Frequency of Ticks (Hz) + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** * @retval None + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** */ + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) + 177 .loc 3 256 22 view .LVU48 + 178 .LBB61: + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** { + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** /* Configure the SysTick to have interrupt in 1ms time base */ + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + 179 .loc 3 259 3 view .LVU49 + 180 .loc 3 259 46 is_stmt 0 view .LVU50 + 181 0000 064B ldr r3, .L12 + 182 0002 A3FB0023 umull r2, r3, r3, r0 + 183 0006 9B09 lsrs r3, r3, #6 + 184 .loc 3 259 20 view .LVU51 + 185 0008 013B subs r3, r3, #1 + 186 .loc 3 259 18 view .LVU52 + 187 000a 4FF0E022 mov r2, #-536813568 + ARM GAS /tmp/ccTd4L28.s page 94 + + + 188 000e 5361 str r3, [r2, #20] + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 189 .loc 3 260 3 is_stmt 1 view .LVU53 + 190 .loc 3 260 18 is_stmt 0 view .LVU54 + 191 0010 0023 movs r3, #0 + 192 0012 9361 str r3, [r2, #24] + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h **** SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 193 .loc 3 261 3 is_stmt 1 view .LVU55 + 194 .loc 3 261 18 is_stmt 0 view .LVU56 + 195 0014 0523 movs r3, #5 + 196 0016 1361 str r3, [r2, #16] + 197 .LVL11: + 198 .loc 3 261 18 view .LVU57 + 199 .LBE61: + 200 .LBE60: + 222:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 201 .loc 1 222 1 view .LVU58 + 202 0018 7047 bx lr + 203 .L13: + 204 001a 00BF .align 2 + 205 .L12: + 206 001c D34D6210 .word 274877907 + 207 .cfi_endproc + 208 .LFE405: + 210 .section .text.LL_mDelay,"ax",%progbits + 211 .align 1 + 212 .global LL_mDelay + 213 .syntax unified + 214 .thumb + 215 .thumb_func + 217 LL_mDelay: + 218 .LVL12: + 219 .LFB406: + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + 220 .loc 1 235 1 is_stmt 1 view -0 + 221 .cfi_startproc + 222 @ args = 0, pretend = 0, frame = 8 + 223 @ frame_needed = 0, uses_anonymous_args = 0 + 224 @ link register save eliminated. + 235:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + 225 .loc 1 235 1 is_stmt 0 view .LVU60 + 226 0000 82B0 sub sp, sp, #8 + 227 .LCFI0: + 228 .cfi_def_cfa_offset 8 + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Add this code to indicate that local variable is not used */ + 229 .loc 1 236 3 is_stmt 1 view .LVU61 + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Add this code to indicate that local variable is not used */ + 230 .loc 1 236 31 is_stmt 0 view .LVU62 + 231 0002 4FF0E023 mov r3, #-536813568 + 232 0006 1B69 ldr r3, [r3, #16] + 236:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Add this code to indicate that local variable is not used */ + 233 .loc 1 236 18 view .LVU63 + 234 0008 0193 str r3, [sp, #4] + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 235 .loc 1 238 3 is_stmt 1 view .LVU64 + 238:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 236 .loc 1 238 4 is_stmt 0 view .LVU65 + ARM GAS /tmp/ccTd4L28.s page 95 + + + 237 000a 019B ldr r3, [sp, #4] + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 238 .loc 1 241 3 is_stmt 1 view .LVU66 + 241:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 239 .loc 1 241 5 is_stmt 0 view .LVU67 + 240 000c B0F1FF3F cmp r0, #-1 + 241 0010 00D0 beq .L17 + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 242 .loc 1 243 5 is_stmt 1 view .LVU68 + 243:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 243 .loc 1 243 10 is_stmt 0 view .LVU69 + 244 0012 0130 adds r0, r0, #1 + 245 .LVL13: + 246 .L17: + 246:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 247 .loc 1 246 10 is_stmt 1 view .LVU70 + 248 0014 38B1 cbz r0, .L20 + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 249 .loc 1 248 5 view .LVU71 + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 250 .loc 1 248 16 is_stmt 0 view .LVU72 + 251 0016 4FF0E023 mov r3, #-536813568 + 252 001a 1B69 ldr r3, [r3, #16] + 248:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 253 .loc 1 248 7 view .LVU73 + 254 001c 13F4803F tst r3, #65536 + 255 0020 F8D0 beq .L17 + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 256 .loc 1 250 7 is_stmt 1 view .LVU74 + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 257 .loc 1 250 12 is_stmt 0 view .LVU75 + 258 0022 0138 subs r0, r0, #1 + 259 .LVL14: + 250:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 260 .loc 1 250 12 view .LVU76 + 261 0024 F6E7 b .L17 + 262 .L20: + 253:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 263 .loc 1 253 1 view .LVU77 + 264 0026 02B0 add sp, sp, #8 + 265 .LCFI1: + 266 .cfi_def_cfa_offset 0 + 267 @ sp needed + 268 0028 7047 bx lr + 269 .cfi_endproc + 270 .LFE406: + 272 .section .text.LL_SetSystemCoreClock,"ax",%progbits + 273 .align 1 + 274 .global LL_SetSystemCoreClock + 275 .syntax unified + 276 .thumb + 277 .thumb_func + 279 LL_SetSystemCoreClock: + 280 .LVL15: + 281 .LFB407: + 312:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* HCLK clock frequency */ + 282 .loc 1 312 1 is_stmt 1 view -0 + ARM GAS /tmp/ccTd4L28.s page 96 + + + 283 .cfi_startproc + 284 @ args = 0, pretend = 0, frame = 0 + 285 @ frame_needed = 0, uses_anonymous_args = 0 + 286 @ link register save eliminated. + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 287 .loc 1 314 3 view .LVU79 + 314:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 288 .loc 1 314 19 is_stmt 0 view .LVU80 + 289 0000 014B ldr r3, .L22 + 290 0002 1860 str r0, [r3] + 315:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 291 .loc 1 315 1 view .LVU81 + 292 0004 7047 bx lr + 293 .L23: + 294 0006 00BF .align 2 + 295 .L22: + 296 0008 00000000 .word SystemCoreClock + 297 .cfi_endproc + 298 .LFE407: + 300 .section .text.LL_SetFlashLatency,"ax",%progbits + 301 .align 1 + 302 .global LL_SetFlashLatency + 303 .syntax unified + 304 .thumb + 305 .thumb_func + 307 LL_SetFlashLatency: + 308 .LVL16: + 309 .LFB408: + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** uint32_t timeout; + 310 .loc 1 327 1 is_stmt 1 view -0 + 311 .cfi_startproc + 312 @ args = 0, pretend = 0, frame = 0 + 313 @ frame_needed = 0, uses_anonymous_args = 0 + 314 @ link register save eliminated. + 328:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** uint32_t getlatency; + 315 .loc 1 328 3 view .LVU83 + 329:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ + 316 .loc 1 329 3 view .LVU84 + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 317 .loc 1 330 3 view .LVU85 + 331:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 318 .loc 1 331 3 view .LVU86 + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 319 .loc 1 334 3 view .LVU87 + 334:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 320 .loc 1 334 5 is_stmt 0 view .LVU88 + 321 0000 0028 cmp r0, #0 + 322 0002 00F09880 beq .L32 + 327:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** uint32_t timeout; + 323 .loc 1 327 1 view .LVU89 + 324 0006 10B4 push {r4} + 325 .LCFI2: + 326 .cfi_def_cfa_offset 4 + 327 .cfi_offset 4, -4 + 328 0008 0246 mov r2, r0 + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 329 .loc 1 340 5 is_stmt 1 view .LVU90 + ARM GAS /tmp/ccTd4L28.s page 97 + + + 330 .LBB62: + 331 .LBI62: + 332 .file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @file stm32f7xx_ll_pwr.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @brief Header file of PWR LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * This software is licensed under terms that can be found in the LICENSE file + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * in the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #ifndef __STM32F7xx_LL_PWR_H + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define __STM32F7xx_LL_PWR_H + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #ifdef __cplusplus + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** extern "C" { + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #endif + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Includes ------------------------------------------------------------------*/ + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #include "stm32f7xx.h" + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @addtogroup STM32F7xx_LL_Driver + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @{ + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #if defined(PWR) + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL PWR + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @{ + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Private types -------------------------------------------------------------*/ + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Private variables ---------------------------------------------------------*/ + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Private constants ---------------------------------------------------------*/ + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Private macros ------------------------------------------------------------*/ + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Exported types ------------------------------------------------------------*/ + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Exported constants --------------------------------------------------------*/ + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @{ + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @brief Flags defines which can be used with LL_PWR_WriteReg function + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @{ + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CR1_CSBF PWR_CR1_CSBF /*!< Clear standby flag */ + ARM GAS /tmp/ccTd4L28.s page 98 + + + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CR2_CWUF6 PWR_CR2_CWUF6 /*!< Clear WKUP pin 6 */ + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CR2_CWUF5 PWR_CR2_CWUF5 /*!< Clear WKUP pin 5 */ + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CR2_CWUF4 PWR_CR2_CWUF4 /*!< Clear WKUP pin 4 */ + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CR2_CWUF3 PWR_CR2_CWUF3 /*!< Clear WKUP pin 3 */ + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CR2_CWUF2 PWR_CR2_CWUF2 /*!< Clear WKUP pin 2 */ + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CR2_CWUF1 PWR_CR2_CWUF1 /*!< Clear WKUP pin 1 */ + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @} + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @brief Flags defines which can be used with LL_PWR_ReadReg function + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @{ + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR1_WUIF PWR_CSR1_WUIF /*!< Wakeup flag */ + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR1_SBF PWR_CSR1_SBF /*!< Standby flag */ + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR1_PVDO PWR_CSR1_PVDO /*!< Power voltage detector outp + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR1_BRR PWR_CSR1_BRR /*!< Backup Regulator ready flag + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR1_VOSRDY PWR_CSR1_VOSRDY /*!< Voltage scaling select flag + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR1_ODRDY PWR_CSR1_ODRDY /*!< Over-drive mode ready */ + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR1_ODSWRDY PWR_CSR1_ODSWRDY /*!< Over-drive mode switching r + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR1_UDRDY PWR_CSR1_UDRDY /*!< Under-drive ready flag */ + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR2_EWUP1 PWR_CSR2_EWUP1 /*!< Enable WKUP pin 1 */ + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR2_EWUP2 PWR_CSR2_EWUP2 /*!< Enable WKUP pin 2 */ + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR2_EWUP3 PWR_CSR2_EWUP3 /*!< Enable WKUP pin 3 */ + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR2_EWUP4 PWR_CSR2_EWUP4 /*!< Enable WKUP pin 4 */ + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR2_EWUP5 PWR_CSR2_EWUP5 /*!< Enable WKUP pin 5 */ + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_CSR2_EWUP6 PWR_CSR2_EWUP6 /*!< Enable WKUP pin 6 */ + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @} + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_MODE_PWR Mode Power + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @{ + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (PWR_CR1_MRUDS | PWR_CR1_FPDS) + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_MODE_STOP_LPREGU PWR_CR1_LPDS + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_FPDS) + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_MODE_STANDBY PWR_CR1_PDDS + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @} + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @{ + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_CR1_VOS_0 + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_CR1_VOS_1 + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0 | PWR_CR1_VOS_1) + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @} + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode + ARM GAS /tmp/ccTd4L28.s page 99 + + + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @{ + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in mai + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_REGU_DSMODE_LOW_POWER PWR_CR1_LPDS /*!< Voltage Regulator in low + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @} + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @{ + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Voltage threshold detected by + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Voltage threshold detected by + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Voltage threshold detected by + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Voltage threshold detected by + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Voltage threshold detected by + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Voltage threshold detected by + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Voltage threshold detected by + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< Voltage threshold detected by + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @} + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @{ + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1 /*!< WKUP pin 1 : PA0 */ + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2 /*!< WKUP pin 2 : PA2 */ + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3 /*!< WKUP pin 3 : PC1 */ + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4 /*!< WKUP pin 4 : PC13 */ + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5 /*!< WKUP pin 5 : PI8 */ + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6 /*!< WKUP pin 6 : PI11 */ + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @} + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @} + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Exported macro ------------------------------------------------------------*/ + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @{ + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @{ + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @brief Write a value in PWR register + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @param __REG__ Register to be written + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @param __VALUE__ Value to be written in the register + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @retval None + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + ARM GAS /tmp/ccTd4L28.s page 100 + + + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @brief Read a value in PWR register + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @param __REG__ Register to be read + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @retval Register value + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @} + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @} + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /* Exported functions --------------------------------------------------------*/ + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @{ + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** @defgroup PWR_LL_EF_Configuration Configuration + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @{ + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @brief Enable Under Drive Mode + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @rmtoll CR1 UDEN LL_PWR_EnableUnderDriveMode + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @note This mode is enabled only with STOP low power mode. + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * mode is only available when the main Regulator or the low power Regulator + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * is in low voltage mode. + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @note If the Under-drive mode was enabled, it is automatically disabled after + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * exiting Stop mode. + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * When the voltage Regulator operates in Under-drive mode, an additional + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * startup delay is induced when waking up from Stop mode. + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @retval None + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void) + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** { + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** SET_BIT(PWR->CR1, PWR_CR1_UDEN); + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** } + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @brief Disable Under Drive Mode + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @rmtoll CR1 UDEN LL_PWR_DisableUnderDriveMode + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @retval None + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void) + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** { + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** CLEAR_BIT(PWR->CR1, PWR_CR1_UDEN); + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** } + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @brief Check if Under Drive Mode is enabled + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @rmtoll CR1 UDEN LL_PWR_IsEnabledUnderDriveMode + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @retval State of bit (1 or 0). + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void) + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** { + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** return (READ_BIT(PWR->CR1, PWR_CR1_UDEN) == (PWR_CR1_UDEN)); + ARM GAS /tmp/ccTd4L28.s page 101 + + + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** } + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @brief Enable Over drive switching + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @rmtoll CR1 ODSWEN LL_PWR_EnableOverDriveSwitching + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @retval None + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void) + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** { + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** SET_BIT(PWR->CR1, PWR_CR1_ODSWEN); + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** } + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @brief Disable Over drive switching + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @rmtoll CR1 ODSWEN LL_PWR_DisableOverDriveSwitching + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @retval None + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void) + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** { + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** CLEAR_BIT(PWR->CR1, PWR_CR1_ODSWEN); + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** } + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @brief Check if Over drive switching is enabled + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @rmtoll CR1 ODSWEN LL_PWR_IsEnabledOverDriveSwitching + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @retval State of bit (1 or 0). + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void) + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** { + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** return (READ_BIT(PWR->CR1, PWR_CR1_ODSWEN) == (PWR_CR1_ODSWEN)); + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** } + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @brief Enable Over drive Mode + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @rmtoll CR1 ODEN LL_PWR_EnableOverDriveMode + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @retval None + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE void LL_PWR_EnableOverDriveMode(void) + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** { + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** SET_BIT(PWR->CR1, PWR_CR1_ODEN); + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** } + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @brief Disable Over drive Mode + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @rmtoll CR1 ODEN LL_PWR_DisableOverDriveMode + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @retval None + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE void LL_PWR_DisableOverDriveMode(void) + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** { + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** CLEAR_BIT(PWR->CR1, PWR_CR1_ODEN); + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** } + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @brief Check if Over drive switching is enabled + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @rmtoll CR1 ODEN LL_PWR_IsEnabledOverDriveMode + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @retval State of bit (1 or 0). + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + ARM GAS /tmp/ccTd4L28.s page 102 + + + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void) + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** { + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** return (READ_BIT(PWR->CR1, PWR_CR1_ODEN) == (PWR_CR1_ODEN)); + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** } + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @brief Set the main internal Regulator output voltage + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @param VoltageScaling This parameter can be one of the following values: + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @retval None + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** { + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** } + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** /** + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @brief Get the main internal Regulator output voltage + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @retval Returned value can be one of the following values: + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** */ + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) + 333 .loc 4 310 26 view .LVU91 + 334 .LBB63: + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** { + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); + 335 .loc 4 312 3 view .LVU92 + 336 .loc 4 312 21 is_stmt 0 view .LVU93 + 337 000a 4D4B ldr r3, .L56 + 338 000c 1B68 ldr r3, [r3] + 339 .loc 4 312 10 view .LVU94 + 340 000e 03F44043 and r3, r3, #49152 + 341 .LBE63: + 342 .LBE62: + 340:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 343 .loc 1 340 7 discriminator 1 view .LVU95 + 344 0012 B3F5404F cmp r3, #49152 + 345 0016 14D0 beq .L54 + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 346 .loc 1 385 10 is_stmt 1 view .LVU96 + 347 .LBB64: + 348 .LBI64: + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** { + 349 .loc 4 310 26 view .LVU97 + 350 .LBB65: + 351 .loc 4 312 3 view .LVU98 + 352 .loc 4 312 21 is_stmt 0 view .LVU99 + 353 0018 494B ldr r3, .L56 + 354 001a 1B68 ldr r3, [r3] + 355 .loc 4 312 10 view .LVU100 + 356 001c 03F44043 and r3, r3, #49152 + ARM GAS /tmp/ccTd4L28.s page 103 + + + 357 .LBE65: + 358 .LBE64: + 385:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 359 .loc 1 385 12 discriminator 1 view .LVU101 + 360 0020 B3F5004F cmp r3, #32768 + 361 0024 41D0 beq .L55 + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 362 .loc 1 419 7 is_stmt 1 view .LVU102 + 419:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 363 .loc 1 419 9 is_stmt 0 view .LVU103 + 364 0026 474B ldr r3, .L56+4 + 365 0028 9842 cmp r0, r3 + 366 002a 64D8 bhi .L44 + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 367 .loc 1 424 12 is_stmt 1 view .LVU104 + 424:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 368 .loc 1 424 14 is_stmt 0 view .LVU105 + 369 002c 464B ldr r3, .L56+8 + 370 002e 9842 cmp r0, r3 + 371 0030 7BD8 bhi .L45 + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 372 .loc 1 429 12 is_stmt 1 view .LVU106 + 429:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 373 .loc 1 429 14 is_stmt 0 view .LVU107 + 374 0032 464B ldr r3, .L56+12 + 375 0034 9842 cmp r0, r3 + 376 0036 7AD8 bhi .L46 + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 377 .loc 1 436 9 is_stmt 1 view .LVU108 + 436:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 378 .loc 1 436 11 is_stmt 0 view .LVU109 + 379 0038 454B ldr r3, .L56+16 + 380 003a 9842 cmp r0, r3 + 381 003c 79D8 bhi .L47 + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 382 .loc 1 330 12 view .LVU110 + 383 003e 0020 movs r0, #0 + 384 .LVL17: + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 385 .loc 1 330 12 view .LVU111 + 386 0040 5AE0 b .L28 + 387 .LVL18: + 388 .L54: + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 389 .loc 1 342 7 is_stmt 1 view .LVU112 + 390 .LBB66: + 391 .LBI66: + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** { + 392 .loc 4 283 26 view .LVU113 + 393 .LBB67: + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** } + 394 .loc 4 285 3 view .LVU114 + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** } + 395 .loc 4 285 11 is_stmt 0 view .LVU115 + 396 0042 3F4B ldr r3, .L56 + 397 0044 1868 ldr r0, [r3] + 398 .LVL19: + ARM GAS /tmp/ccTd4L28.s page 104 + + + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h **** } + 399 .loc 4 285 11 view .LVU116 + 400 .LBE67: + 401 .LBE66: + 342:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 402 .loc 1 342 9 discriminator 1 view .LVU117 + 403 0046 10F48030 ands r0, r0, #65536 + 404 004a 03D0 beq .L27 + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 405 .loc 1 344 11 is_stmt 1 view .LVU118 + 344:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 406 .loc 1 344 13 is_stmt 0 view .LVU119 + 407 004c 414B ldr r3, .L56+20 + 408 004e 9A42 cmp r2, r3 + 409 0050 29D9 bls .L33 + 347:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 410 .loc 1 347 21 view .LVU120 + 411 0052 0720 movs r0, #7 + 412 .L27: + 413 .LVL20: + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 414 .loc 1 355 7 is_stmt 1 view .LVU121 + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 415 .loc 1 355 68 is_stmt 0 view .LVU122 + 416 0054 B0FA80F3 clz r3, r0 + 417 0058 5B09 lsrs r3, r3, #5 + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 418 .loc 1 355 56 view .LVU123 + 419 005a 3F4C ldr r4, .L56+24 + 420 005c A242 cmp r2, r4 + 421 005e 94BF ite ls + 422 0060 0021 movls r1, #0 + 423 0062 03F00101 andhi r1, r3, #1 + 355:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 424 .loc 1 355 9 view .LVU124 + 425 0066 0029 cmp r1, #0 + 426 0068 33D1 bne .L34 + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 427 .loc 1 360 12 is_stmt 1 view .LVU125 + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 428 .loc 1 360 61 is_stmt 0 view .LVU126 + 429 006a 364C ldr r4, .L56+4 + 430 006c A242 cmp r2, r4 + 431 006e 94BF ite ls + 432 0070 0021 movls r1, #0 + 433 0072 03F00101 andhi r1, r3, #1 + 360:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 434 .loc 1 360 14 view .LVU127 + 435 0076 71BB cbnz r1, .L35 + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 436 .loc 1 365 12 is_stmt 1 view .LVU128 + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 437 .loc 1 365 61 is_stmt 0 view .LVU129 + 438 0078 334C ldr r4, .L56+8 + 439 007a A242 cmp r2, r4 + 440 007c 94BF ite ls + 441 007e 0021 movls r1, #0 + ARM GAS /tmp/ccTd4L28.s page 105 + + + 442 0080 03F00101 andhi r1, r3, #1 + 365:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 443 .loc 1 365 14 view .LVU130 + 444 0084 49BB cbnz r1, .L36 + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 445 .loc 1 370 12 is_stmt 1 view .LVU131 + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 446 .loc 1 370 61 is_stmt 0 view .LVU132 + 447 0086 314C ldr r4, .L56+12 + 448 0088 A242 cmp r2, r4 + 449 008a 94BF ite ls + 450 008c 0021 movls r1, #0 + 451 008e 03F00101 andhi r1, r3, #1 + 370:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 452 .loc 1 370 14 view .LVU133 + 453 0092 21BB cbnz r1, .L37 + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 454 .loc 1 377 9 is_stmt 1 view .LVU134 + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 455 .loc 1 377 58 is_stmt 0 view .LVU135 + 456 0094 2E49 ldr r1, .L56+16 + 457 0096 8A42 cmp r2, r1 + 458 0098 94BF ite ls + 459 009a 0023 movls r3, #0 + 460 009c 03F00103 andhi r3, r3, #1 + 377:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 461 .loc 1 377 11 view .LVU136 + 462 00a0 53B3 cbz r3, .L28 + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 463 .loc 1 380 19 view .LVU137 + 464 00a2 0120 movs r0, #1 + 465 .LVL21: + 380:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 466 .loc 1 380 19 view .LVU138 + 467 00a4 28E0 b .L28 + 468 .LVL22: + 469 .L33: + 352:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 470 .loc 1 352 21 view .LVU139 + 471 00a6 0620 movs r0, #6 + 472 00a8 D4E7 b .L27 + 473 .LVL23: + 474 .L55: + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 475 .loc 1 387 7 is_stmt 1 view .LVU140 + 387:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 476 .loc 1 387 9 is_stmt 0 view .LVU141 + 477 00aa 03F10F63 add r3, r3, #149946368 + 478 00ae 03F5A343 add r3, r3, #20864 + 479 00b2 9842 cmp r0, r3 + 480 00b4 15D8 bhi .L39 + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 481 .loc 1 392 12 is_stmt 1 view .LVU142 + 392:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 482 .loc 1 392 14 is_stmt 0 view .LVU143 + 483 00b6 234B ldr r3, .L56+4 + 484 00b8 9842 cmp r0, r3 + ARM GAS /tmp/ccTd4L28.s page 106 + + + 485 00ba 14D8 bhi .L40 + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 486 .loc 1 397 12 is_stmt 1 view .LVU144 + 397:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 487 .loc 1 397 14 is_stmt 0 view .LVU145 + 488 00bc 224B ldr r3, .L56+8 + 489 00be 9842 cmp r0, r3 + 490 00c0 13D8 bhi .L41 + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 491 .loc 1 402 12 is_stmt 1 view .LVU146 + 402:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 492 .loc 1 402 14 is_stmt 0 view .LVU147 + 493 00c2 224B ldr r3, .L56+12 + 494 00c4 9842 cmp r0, r3 + 495 00c6 12D8 bhi .L42 + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 496 .loc 1 409 9 is_stmt 1 view .LVU148 + 409:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 497 .loc 1 409 11 is_stmt 0 view .LVU149 + 498 00c8 214B ldr r3, .L56+16 + 499 00ca 9842 cmp r0, r3 + 500 00cc 11D8 bhi .L43 + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 501 .loc 1 330 12 view .LVU150 + 502 00ce 0020 movs r0, #0 + 503 .LVL24: + 330:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 504 .loc 1 330 12 view .LVU151 + 505 00d0 12E0 b .L28 + 506 .LVL25: + 507 .L34: + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 508 .loc 1 358 17 view .LVU152 + 509 00d2 0520 movs r0, #5 + 510 .LVL26: + 358:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 511 .loc 1 358 17 view .LVU153 + 512 00d4 10E0 b .L28 + 513 .LVL27: + 514 .L35: + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 515 .loc 1 363 17 view .LVU154 + 516 00d6 0420 movs r0, #4 + 517 .LVL28: + 363:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 518 .loc 1 363 17 view .LVU155 + 519 00d8 0EE0 b .L28 + 520 .LVL29: + 521 .L36: + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 522 .loc 1 368 17 view .LVU156 + 523 00da 0320 movs r0, #3 + 524 .LVL30: + 368:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 525 .loc 1 368 17 view .LVU157 + 526 00dc 0CE0 b .L28 + 527 .LVL31: + ARM GAS /tmp/ccTd4L28.s page 107 + + + 528 .L37: + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 529 .loc 1 373 17 view .LVU158 + 530 00de 0220 movs r0, #2 + 531 .LVL32: + 373:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 532 .loc 1 373 17 view .LVU159 + 533 00e0 0AE0 b .L28 + 534 .LVL33: + 535 .L39: + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 536 .loc 1 390 17 view .LVU160 + 537 00e2 0520 movs r0, #5 + 538 .LVL34: + 390:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 539 .loc 1 390 17 view .LVU161 + 540 00e4 08E0 b .L28 + 541 .LVL35: + 542 .L40: + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 543 .loc 1 395 17 view .LVU162 + 544 00e6 0420 movs r0, #4 + 545 .LVL36: + 395:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 546 .loc 1 395 17 view .LVU163 + 547 00e8 06E0 b .L28 + 548 .LVL37: + 549 .L41: + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 550 .loc 1 400 17 view .LVU164 + 551 00ea 0320 movs r0, #3 + 552 .LVL38: + 400:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 553 .loc 1 400 17 view .LVU165 + 554 00ec 04E0 b .L28 + 555 .LVL39: + 556 .L42: + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 557 .loc 1 405 17 view .LVU166 + 558 00ee 0220 movs r0, #2 + 559 .LVL40: + 405:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 560 .loc 1 405 17 view .LVU167 + 561 00f0 02E0 b .L28 + 562 .LVL41: + 563 .L43: + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 564 .loc 1 412 19 view .LVU168 + 565 00f2 0120 movs r0, #1 + 566 .LVL42: + 412:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 567 .loc 1 412 19 view .LVU169 + 568 00f4 00E0 b .L28 + 569 .LVL43: + 570 .L44: + 422:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 571 .loc 1 422 17 view .LVU170 + ARM GAS /tmp/ccTd4L28.s page 108 + + + 572 00f6 0420 movs r0, #4 + 573 .LVL44: + 574 .L28: + 445:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 575 .loc 1 445 5 is_stmt 1 view .LVU171 + 447:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 576 .loc 1 447 7 view .LVU172 + 577 .LBB68: + 578 .LBI68: + 579 .file 5 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h" + 1:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 2:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** ****************************************************************************** + 3:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @file stm32f7xx_ll_system.h + 4:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @author MCD Application Team + 5:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Header file of SYSTEM LL module. + 6:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** ****************************************************************************** + 7:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @attention + 8:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * + 9:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * Copyright (c) 2017 STMicroelectronics. + 10:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * All rights reserved. + 11:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * + 12:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * This software is licensed under terms that can be found in the LICENSE file + 13:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * in the root directory of this software component. + 14:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * + 16:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** ****************************************************************************** + 17:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** @verbatim + 18:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** ============================================================================== + 19:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** ##### How to use this driver ##### + 20:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** ============================================================================== + 21:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** [..] + 22:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** The LL SYSTEM driver contains a set of generic APIs that can be + 23:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** used by user: + 24:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** (+) Some of the FLASH features need to be handled in the SYSTEM file. + 25:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** (+) Access to DBGCMU registers + 26:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** (+) Access to SYSCFG registers + 27:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 28:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** @endverbatim + 29:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** ****************************************************************************** + 30:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 31:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 32:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 33:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #ifndef __STM32F7xx_LL_SYSTEM_H + 34:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define __STM32F7xx_LL_SYSTEM_H + 35:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 36:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #ifdef __cplusplus + 37:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** extern "C" { + 38:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif + 39:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 40:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Includes ------------------------------------------------------------------*/ + 41:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #include "stm32f7xx.h" + 42:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 43:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @addtogroup STM32F7xx_LL_Driver + 44:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 45:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 46:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 47:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) + ARM GAS /tmp/ccTd4L28.s page 109 + + + 48:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 49:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL SYSTEM + 50:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 51:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 52:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 53:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Private types -------------------------------------------------------------*/ + 54:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Private variables ---------------------------------------------------------*/ + 55:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 56:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Private constants ---------------------------------------------------------*/ + 57:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + 58:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 59:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 60:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 61:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 62:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @} + 63:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 64:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 65:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Private macros ------------------------------------------------------------*/ + 66:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 67:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Exported types ------------------------------------------------------------*/ + 68:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Exported constants --------------------------------------------------------*/ + 69:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + 70:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 71:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 72:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 73:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP + 74:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 75:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 76:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_REMAP_BOOT0 0x00000000U /*! + 77:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_REMAP_BOOT1 SYSCFG_MEMRMP_MEM_BOOT /*! + 78:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 79:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @} + 80:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 81:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 82:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 83:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_MEMRMP_SWP_FB) + 84:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE + 85:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 86:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 87:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank 1 base address m + 88:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** and Flash Bank 2 base address + 89:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 90:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_SWP_FB /*!< Flash Bank 2 base address m + 91:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** and Flash Bank 1 base address + 92:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 93:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @} + 94:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 95:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_MEMRMP_SWP_FB */ + 96:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 97:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_PMC_MII_RMII_SEL) + 98:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC + 99:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 100:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 101:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_PMC_ETHMII 0x00000000U /*!< + 102:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /*!< + 103:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 104:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + ARM GAS /tmp/ccTd4L28.s page 110 + + + 105:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @} + 106:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 107:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_PMC_MII_RMII_SEL */ + 108:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 109:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + 110:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 111:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 112:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_PMC_I2C1_FMP) + 113:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP /*!< Enable Fast Mode Plus + 114:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP /*!< Enable Fast Mode Plus + 115:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP /*!< Enable Fast Mode Plus + 116:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_PMC_I2C1_FMP */ + 117:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_PMC_I2C4_FMP) + 118:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP /*!< Enable Fast Mode Plus + 119:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_PMC_I2C4_FMP */ + 120:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_PMC_I2C_PB6_FMP) + 121:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP /*!< Enable Fast Mode Plus + 122:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP /*!< Enable Fast Mode Plus + 123:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP /*!< Enable Fast Mode Plus + 124:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP /*!< Enable Fast Mode Plus + 125:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_PMC_I2C_PB6_FMP */ + 126:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 127:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @} + 128:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 129:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 130:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT + 131:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 133:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A + 134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B + 135:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C + 136:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D + 137:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E + 138:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(GPIOF) + 139:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F + 140:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* GPIOF */ + 141:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(GPIOG) + 142:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G + 143:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* GPIOG */ + 144:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H + 145:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(GPIOI) + 146:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I + 147:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* GPIOI */ + 148:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(GPIOJ) + 149:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTJ 9U /*!< EXTI PORT J + 150:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* GPIOJ */ + 151:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(GPIOK) + 152:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_PORTK 10U /*!< EXTI PORT k + 153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* GPIOK */ + 154:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @} + 156:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 157:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 158:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE + 159:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 160:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 161:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE0 (0x000FU << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] + ARM GAS /tmp/ccTd4L28.s page 111 + + + 162:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE1 (0x00F0U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] + 163:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE2 (0x0F00U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] + 164:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE3 (0xF000U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] + 165:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE4 (0x000FU << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] + 166:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE5 (0x00F0U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] + 167:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE6 (0x0F00U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] + 168:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE7 (0xF000U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] + 169:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE8 (0x000FU << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] + 170:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE9 (0x00F0U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] + 171:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE10 (0x0F00U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] + 172:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE11 (0xF000U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] + 173:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE12 (0x000FU << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] + 174:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE13 (0x00F0U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] + 175:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE14 (0x0F00U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] + 176:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_EXTI_LINE15 (0xF000U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] + 177:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 178:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @} + 179:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 180:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 181:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + 182:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 183:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 184:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_CBR_CLL) + 185:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CBR_CLL /*!< Enables and locks the Lockup out + 186:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** lockup state) of Cortex-M7 with + 187:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CBR_PVDL /*!< Enables and locks the PVD connec + 188:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** It also locks (write protect) th + 189:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** of the power controller */ + 190:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_CBR_CLL */ + 191:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 192:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @} + 193:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 194:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_CMP_PD SYSCFG CMP PD + 195:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 196:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 197:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_DISABLE_CMP_PD 0x00000000U /*!< I/O compensation cell power- + 198:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_SYSCFG_ENABLE_CMP_PD SYSCFG_CMPCR_CMP_PD /*!< I/O compensation cell enable + 199:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 200:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @} + 201:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 202:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 203:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment + 204:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 205:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 206:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRA + 207:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRA + 208:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRA + 209:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRA + 210:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRA + 211:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 212:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @} + 213:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 215:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + 216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 217:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 218:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter + ARM GAS /tmp/ccTd4L28.s page 112 + + + 219:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter + 220:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter + 221:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter + 222:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter + 223:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter + 224:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter + 225:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter + 226:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter + 227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP /*!< LPTIIM1 count + 228:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter s + 229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window + 230:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Indepen + 231:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS ti + 232:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS ti + 233:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS ti + 234:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT) + 235:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_I2C4_STOP DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS ti + 236:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */ + 237:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< CAN1 debug st + 238:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP) + 239:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /*!< CAN2 debug st + 240:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */ + 241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP) + 242:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB1_GRP1_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP /*!< CAN3 debug st + 243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /*DBGMCU_APB1_FZ_DBG_CAN3_STOP*/ + 244:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 245:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @} + 246:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 248:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP + 249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 250:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 251:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopp + 252:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopp + 253:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopp + 254:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stop + 255:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stop + 256:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 257:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @} + 258:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 259:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 260:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + 261:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 262:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ + 264:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ + 265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ + 266:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ + 267:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ + 268:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */ + 269:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ + 270:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */ + 271:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */ + 272:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */ + 273:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */ + 274:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states * + 275:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states * + ARM GAS /tmp/ccTd4L28.s page 113 + + + 276:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states + 277:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states + 278:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states + 279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 280:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @} + 281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 282:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 283:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 284:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @} + 285:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 286:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 287:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Exported macro ------------------------------------------------------------*/ + 288:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 289:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /* Exported functions --------------------------------------------------------*/ + 290:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + 291:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 292:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 293:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 294:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + 295:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 296:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 297:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 298:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 299:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Enables the FMC Memory Mapping Swapping + 300:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping + 301:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @note SDRAM is accessible at 0x60000000 and NOR/RAM + 302:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * is accessible at 0xC0000000 + 303:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 304:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 305:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void) + 306:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 307:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0); + 308:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 309:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 310:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 311:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Disables the FMC Memory Mapping Swapping + 312:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping + 313:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @note SDRAM is accessible at 0xC0000000 (default mapping) + 314:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * and NOR/RAM is accessible at 0x60000000 (default mapping) + 315:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 316:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 317:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void) + 318:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 319:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC); + 320:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 321:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 322:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 323:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Enables the Compensation Cell + 324:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell + 325:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @note The I/O compensation cell can be used only when the device supply + 326:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * voltage ranges from 2.4 to 3.6 V + 327:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 328:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 329:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void) + 330:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 331:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD); + 332:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + ARM GAS /tmp/ccTd4L28.s page 114 + + + 333:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 334:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 335:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Disables the Compensation Cell + 336:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell + 337:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @note The I/O compensation cell can be used only when the device supply + 338:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * voltage ranges from 2.4 to 3.6 V + 339:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 340:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 341:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void) + 342:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 343:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD); + 344:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 345:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 346:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 347:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Get Compensation Cell ready Flag + 348:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR + 349:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval State of bit (1 or 0). + 350:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 351:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void) + 352:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 353:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY)); + 354:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 355:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 356:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 357:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 358:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Get the memory boot mapping as configured by user + 359:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll SYSCFG_MEMRMP MEM_BOOT LL_SYSCFG_GetRemapMemoryBoot + 360:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval Returned value can be one of the following values: + 361:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_BOOT0 + 362:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_REMAP_BOOT1 + 363:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * + 364:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * (*) value not defined in all devices + 365:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 366:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemoryBoot(void) + 367:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 368:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT)); + 369:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 370:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 371:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_PMC_MII_RMII_SEL) + 372:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 373:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Select Ethernet PHY interface + 374:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface + 375:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @param Interface This parameter can be one of the following values: + 376:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_PMC_ETHMII + 377:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_PMC_ETHRMII + 378:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 379:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 380:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface) + 381:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 382:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface); + 383:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 384:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 385:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 386:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Get Ethernet PHY interface + 387:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface + 388:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval Returned value can be one of the following values: + 389:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_PMC_ETHMII + ARM GAS /tmp/ccTd4L28.s page 115 + + + 390:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_PMC_ETHRMII + 391:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 392:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 393:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void) + 394:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 395:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL)); + 396:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 397:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_PMC_MII_RMII_SEL */ + 398:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 399:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 400:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_MEMRMP_SWP_FB) + 401:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 402:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Select Flash bank mode (Bank flashed at 0x08000000) + 403:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode + 404:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @param Bank This parameter can be one of the following values: + 405:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_BANKMODE_BANK1 + 406:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_BANKMODE_BANK2 + 407:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 408:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 409:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank) + 410:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 411:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB, Bank); + 412:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 413:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 414:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 415:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Get Flash bank mode (Bank flashed at 0x08000000) + 416:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode + 417:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval Returned value can be one of the following values: + 418:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_BANKMODE_BANK1 + 419:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_BANKMODE_BANK2 + 420:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 421:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void) + 422:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 423:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB)); + 424:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 425:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 426:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_MEMRMP_SWP_FB */ + 427:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 428:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_PMC_I2C1_FMP) + 429:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 430:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Enable the I2C fast mode plus driving capability. + 431:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll SYSCFG_PMC I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n + 432:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * SYSCFG_PMC I2Cx_FMP LL_SYSCFG_EnableFastModePlus + 433:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @param ConfigFastModePlus This parameter can be a combination of the following values: + 434:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + 435:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + 436:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) + 437:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) + 438:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + 439:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + 440:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 + 441:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*) + 442:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * + 443:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * (*) value not defined in all devices + 444:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 445:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 446:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) + ARM GAS /tmp/ccTd4L28.s page 116 + + + 447:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 448:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** SET_BIT(SYSCFG->PMC, ConfigFastModePlus); + 449:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 450:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 451:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 452:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Disable the I2C fast mode plus driving capability. + 453:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll SYSCFG_PMC I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n + 454:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * SYSCFG_PMC I2Cx_FMP LL_SYSCFG_DisableFastModePlus + 455:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @param ConfigFastModePlus This parameter can be a combination of the following values: + 456:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + 457:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + 458:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) + 459:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) + 460:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + 461:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + 462:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 + 463:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 + 464:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * (*) value not defined in all devices + 465:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 466:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 467:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) + 468:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 469:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** CLEAR_BIT(SYSCFG->PMC, ConfigFastModePlus); + 470:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 471:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_PMC_I2C1_FMP */ + 472:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 473:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 474:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 475:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Configure source input for the EXTI external interrupt. + 476:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n + 477:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n + 478:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n + 479:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource + 480:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @param Port This parameter can be one of the following values: + 481:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTA + 482:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTB + 483:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTC + 484:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTD + 485:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTE + 486:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTF + 487:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTG + 488:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTH + 489:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTI + 490:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTJ + 491:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTK + 492:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * + 493:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * (*) value not defined in all devices + 494:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @param Line This parameter can be one of the following values: + 495:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE0 + 496:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE1 + 497:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE2 + 498:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE3 + 499:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE4 + 500:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE5 + 501:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE6 + 502:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE7 + 503:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE8 + ARM GAS /tmp/ccTd4L28.s page 117 + + + 504:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE9 + 505:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE10 + 506:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE11 + 507:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE12 + 508:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE13 + 509:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE14 + 510:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE15 + 511:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 512:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 513:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) + 514:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 515:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U))); + 516:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 517:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 518:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 519:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Get the configured defined for specific EXTI Line + 520:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n + 521:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n + 522:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n + 523:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource + 524:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @param Line This parameter can be one of the following values: + 525:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE0 + 526:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE1 + 527:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE2 + 528:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE3 + 529:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE4 + 530:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE5 + 531:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE6 + 532:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE7 + 533:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE8 + 534:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE9 + 535:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE10 + 536:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE11 + 537:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE12 + 538:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE13 + 539:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE14 + 540:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_LINE15 + 541:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval Returned value can be one of the following values: + 542:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTA + 543:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTB + 544:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTC + 545:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTD + 546:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTE + 547:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTF + 548:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTG + 549:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTH + 550:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTI + 551:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTJ + 552:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_EXTI_PORTK + 553:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * (*) value not defined in all devices + 554:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 555:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) + 556:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 557:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 1 + 558:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 559:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 560:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #if defined(SYSCFG_CBR_CLL) + ARM GAS /tmp/ccTd4L28.s page 118 + + + 561:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 562:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Set connections to TIM1/8/15/16/17 Break inputs + 563:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * SYSCFG_CBR CLL LL_SYSCFG_SetTIMBreakInputs\n + 564:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * SYSCFG_CBR PVDL LL_SYSCFG_SetTIMBreakInputs + 565:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @param Break This parameter can be a combination of the following values: + 566:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + 567:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIMBREAK_PVD + 568:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 569:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 570:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) + 571:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 572:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** MODIFY_REG(SYSCFG->CBR, SYSCFG_CBR_CLL | SYSCFG_CBR_PVDL, Break); + 573:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 574:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 575:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 576:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Get connections to TIM1/8/15/16/17 Break inputs + 577:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * SYSCFG_CBR CLL LL_SYSCFG_GetTIMBreakInputs\n + 578:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * SYSCFG_CBR PVDL LL_SYSCFG_GetTIMBreakInputs + 579:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval Returned value can be can be a combination of the following values: + 580:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + 581:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_SYSCFG_TIMBREAK_PVD + 582:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 583:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) + 584:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 585:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** return (uint32_t)(READ_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL | SYSCFG_CBR_PVDL)); + 586:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 587:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** #endif /* SYSCFG_CBR_CLL */ + 588:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 589:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 590:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @} + 591:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 592:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 593:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + 594:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 595:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 596:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 597:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 598:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Return the device identifier + 599:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @note For STM32F75xxx and STM32F74xxx devices, the device ID is 0x449 + 600:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @note For STM32F77xxx and STM32F76xxx devices, the device ID is 0x451 + 601:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @note For STM32F72xxx and STM32F73xxx devices, the device ID is 0x452 + 602:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + 603:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval Values between Min_Data=0x00 and Max_Data=0xFFF + 604:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 605:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) + 606:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 607:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); + 608:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 609:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 610:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 611:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Return the device revision identifier + 612:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @note This field indicates the revision of the device. + 613:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 + 614:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + 615:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + 616:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 617:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) + ARM GAS /tmp/ccTd4L28.s page 119 + + + 618:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 619:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); + 620:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 621:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 622:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 623:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Enable the Debug Module during SLEEP mode + 624:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode + 625:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 626:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 627:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) + 628:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 629:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); + 630:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 631:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 632:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 633:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Disable the Debug Module during SLEEP mode + 634:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode + 635:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 636:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 637:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) + 638:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 639:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); + 640:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 641:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 642:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 643:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Enable the Debug Module during STOP mode + 644:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + 645:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 646:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 647:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) + 648:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 649:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); + 650:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 651:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 652:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 653:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Disable the Debug Module during STOP mode + 654:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + 655:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 656:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 657:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) + 658:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 659:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); + 660:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 661:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 662:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 663:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Enable the Debug Module during STANDBY mode + 664:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + 665:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 666:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 667:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) + 668:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 669:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); + 670:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 671:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 672:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 673:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Disable the Debug Module during STANDBY mode + 674:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + ARM GAS /tmp/ccTd4L28.s page 120 + + + 675:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 676:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 677:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) + 678:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 679:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); + 680:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 681:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 682:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 683:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Set Trace pin assignment control + 684:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n + 685:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment + 686:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @param PinAssignment This parameter can be one of the following values: + 687:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_NONE + 688:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_ASYNCH + 689:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + 690:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + 691:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + 692:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 693:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 694:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) + 695:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 696:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); + 697:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 698:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 699:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 700:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Get Trace pin assignment control + 701:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n + 702:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment + 703:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval Returned value can be one of the following values: + 704:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_NONE + 705:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_ASYNCH + 706:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + 707:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + 708:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + 709:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 710:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) + 711:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 712:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); + 713:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 714:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 715:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 716:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Freeze APB1 peripherals (group1 peripherals) + 717:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 718:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 719:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 720:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 721:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 722:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 723:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 724:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 725:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 726:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 727:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 728:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 729:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 730:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 731:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + ARM GAS /tmp/ccTd4L28.s page 121 + + + 732:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 733:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 734:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 735:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + 736:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + 737:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values: + 738:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + 739:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + 740:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + 741:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + 742:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + 743:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + 744:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + 745:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + 746:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + 747:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + 748:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + 749:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + 750:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + 751:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + 752:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + 753:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + 754:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*) + 755:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP + 756:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) + 757:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*) + 758:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * + 759:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * (*) value not defined in all devices. + 760:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 761:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 762:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) + 763:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 764:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** SET_BIT(DBGMCU->APB1FZ, Periphs); + 765:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 766:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 767:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 768:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Unfreeze APB1 peripherals (group1 peripherals) + 769:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 770:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 771:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 772:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 773:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 774:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 775:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 776:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 777:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 778:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 779:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 780:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 781:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 782:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 783:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 784:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 785:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 786:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 787:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + 788:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + ARM GAS /tmp/ccTd4L28.s page 122 + + + 789:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values: + 790:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + 791:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + 792:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + 793:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + 794:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + 795:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + 796:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + 797:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + 798:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + 799:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + 800:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + 801:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + 802:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + 803:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + 804:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + 805:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + 806:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*) + 807:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP + 808:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) + 809:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*) + 810:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * (*) value not defined in all devices. + 811:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 812:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 813:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) + 814:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 815:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** CLEAR_BIT(DBGMCU->APB1FZ, Periphs); + 816:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 817:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 818:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 819:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Freeze APB2 peripherals + 820:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + 821:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + 822:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + 823:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + 824:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + 825:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values: + 826:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + 827:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP + 828:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP + 829:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP + 830:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP + 831:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * + 832:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * (*) value not defined in all devices. + 833:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 834:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 835:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) + 836:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 837:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** SET_BIT(DBGMCU->APB2FZ, Periphs); + 838:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 839:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 840:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 841:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Unfreeze APB2 peripherals + 842:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + 843:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + 844:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + 845:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + ARM GAS /tmp/ccTd4L28.s page 123 + + + 846:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph + 847:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @param Periphs This parameter can be a combination of the following values: + 848:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + 849:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP + 850:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP + 851:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP + 852:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP + 853:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * + 854:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * (*) value not defined in all devices. + 855:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 856:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 857:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) + 858:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 859:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** CLEAR_BIT(DBGMCU->APB2FZ, Periphs); + 860:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 861:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 862:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @} + 863:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 864:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 865:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** @defgroup SYSTEM_LL_EF_FLASH FLASH + 866:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @{ + 867:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 868:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 869:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 870:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Set FLASH Latency + 871:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + 872:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @param Latency This parameter can be one of the following values: + 873:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_0 + 874:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_1 + 875:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_2 + 876:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_3 + 877:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_4 + 878:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_5 + 879:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_6 + 880:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_7 + 881:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_8 + 882:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_9 + 883:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_10 + 884:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_11 + 885:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_12 + 886:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_13 + 887:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_14 + 888:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_15 + 889:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval None + 890:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 891:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) + 580 .loc 5 891 22 view .LVU173 + 581 .LBB69: + 892:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 893:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); + 582 .loc 5 893 3 view .LVU174 + 583 00f8 184A ldr r2, .L56+28 + 584 .LVL45: + 585 .loc 5 893 3 is_stmt 0 view .LVU175 + 586 00fa 1368 ldr r3, [r2] + 587 00fc 23F00F03 bic r3, r3, #15 + 588 0100 0343 orrs r3, r3, r0 + ARM GAS /tmp/ccTd4L28.s page 124 + + + 589 0102 1360 str r3, [r2] + 590 .LVL46: + 591 .loc 5 893 3 view .LVU176 + 592 .LBE69: + 593 .LBE68: + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** do + 594 .loc 1 451 7 is_stmt 1 view .LVU177 + 451:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** do + 595 .loc 1 451 15 is_stmt 0 view .LVU178 + 596 0104 0222 movs r2, #2 + 597 .LVL47: + 598 .L30: + 452:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 599 .loc 1 452 7 is_stmt 1 view .LVU179 + 455:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** timeout--; + 600 .loc 1 455 7 view .LVU180 + 601 .LBB70: + 602 .LBI70: + 894:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** } + 895:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** + 896:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** /** + 897:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @brief Get FLASH Latency + 898:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + 899:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @retval Returned value can be one of the following values: + 900:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_0 + 901:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_1 + 902:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_2 + 903:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_3 + 904:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_4 + 905:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_5 + 906:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_6 + 907:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_7 + 908:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_8 + 909:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_9 + 910:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_10 + 911:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_11 + 912:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_12 + 913:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_13 + 914:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_14 + 915:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** * @arg @ref LL_FLASH_LATENCY_15 + 916:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** */ + 917:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) + 603 .loc 5 917 26 view .LVU181 + 604 .LBB71: + 918:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** { + 919:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h **** return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); + 605 .loc 5 919 3 view .LVU182 + 606 .loc 5 919 21 is_stmt 0 view .LVU183 + 607 0106 154B ldr r3, .L56+28 + 608 0108 1B68 ldr r3, [r3] + 609 .loc 5 919 10 view .LVU184 + 610 010a 03F00F03 and r3, r3, #15 + 611 .LVL48: + 612 .loc 5 919 10 view .LVU185 + 613 .LBE71: + 614 .LBE70: + 456:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } while ((getlatency != latency) && (timeout > 0)); + ARM GAS /tmp/ccTd4L28.s page 125 + + + 615 .loc 1 456 7 is_stmt 1 view .LVU186 + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 616 .loc 1 457 40 discriminator 1 view .LVU187 + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 617 .loc 1 457 52 is_stmt 0 discriminator 1 view .LVU188 + 618 010e 013A subs r2, r2, #1 + 619 .LVL49: + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 620 .loc 1 457 52 discriminator 1 view .LVU189 + 621 0110 14BF ite ne + 622 0112 0121 movne r1, #1 + 623 0114 0021 moveq r1, #0 + 457:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 624 .loc 1 457 40 discriminator 1 view .LVU190 + 625 0116 9842 cmp r0, r3 + 626 0118 01D0 beq .L49 + 627 011a 0029 cmp r1, #0 + 628 011c F3D1 bne .L30 + 629 .L49: + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 630 .loc 1 459 7 is_stmt 1 view .LVU191 + 459:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 631 .loc 1 459 9 is_stmt 0 view .LVU192 + 632 011e 9842 cmp r0, r3 + 633 0120 0BD0 beq .L48 + 461:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 634 .loc 1 461 16 view .LVU193 + 635 0122 0120 movs r0, #1 + 636 .LVL50: + 637 .L25: + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 638 .loc 1 469 3 is_stmt 1 view .LVU194 + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 639 .loc 1 470 1 is_stmt 0 view .LVU195 + 640 0124 5DF8044B ldr r4, [sp], #4 + 641 .LCFI3: + 642 .cfi_remember_state + 643 .cfi_restore 4 + 644 .cfi_def_cfa_offset 0 + 645 0128 7047 bx lr + 646 .LVL51: + 647 .L45: + 648 .LCFI4: + 649 .cfi_restore_state + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 650 .loc 1 427 17 view .LVU196 + 651 012a 0320 movs r0, #3 + 652 .LVL52: + 427:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 653 .loc 1 427 17 view .LVU197 + 654 012c E4E7 b .L28 + 655 .LVL53: + 656 .L46: + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 657 .loc 1 432 17 view .LVU198 + 658 012e 0220 movs r0, #2 + 659 .LVL54: + ARM GAS /tmp/ccTd4L28.s page 126 + + + 432:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 660 .loc 1 432 17 view .LVU199 + 661 0130 E2E7 b .L28 + 662 .LVL55: + 663 .L47: + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 664 .loc 1 439 19 view .LVU200 + 665 0132 0120 movs r0, #1 + 666 .LVL56: + 439:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 667 .loc 1 439 19 view .LVU201 + 668 0134 E0E7 b .L28 + 669 .LVL57: + 670 .L32: + 671 .LCFI5: + 672 .cfi_def_cfa_offset 0 + 673 .cfi_restore 4 + 336:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 674 .loc 1 336 12 view .LVU202 + 675 0136 0120 movs r0, #1 + 676 .LVL58: + 469:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 677 .loc 1 469 3 is_stmt 1 view .LVU203 + 470:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 678 .loc 1 470 1 is_stmt 0 view .LVU204 + 679 0138 7047 bx lr + 680 .LVL59: + 681 .L48: + 682 .LCFI6: + 683 .cfi_def_cfa_offset 4 + 684 .cfi_offset 4, -4 + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 685 .loc 1 465 16 view .LVU205 + 686 013a 0020 movs r0, #0 + 687 .LVL60: + 465:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 688 .loc 1 465 16 view .LVU206 + 689 013c F2E7 b .L25 + 690 .L57: + 691 013e 00BF .align 2 + 692 .L56: + 693 0140 00700040 .word 1073770496 + 694 0144 000E2707 .word 120000000 + 695 0148 804A5D05 .word 90000000 + 696 014c 00879303 .word 60000000 + 697 0150 80C3C901 .word 30000000 + 698 0154 8058840C .word 210000000 + 699 0158 80D1F008 .word 150000000 + 700 015c 003C0240 .word 1073888256 + 701 .cfi_endproc + 702 .LFE408: + 704 .section .text.UTILS_EnablePLLAndSwitchSystem,"ax",%progbits + 705 .align 1 + 706 .syntax unified + 707 .thumb + 708 .thumb_func + 710 UTILS_EnablePLLAndSwitchSystem: + ARM GAS /tmp/ccTd4L28.s page 127 + + + 711 .LVL61: + 712 .LFB413: + 673:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 674:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /** + 675:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @brief Function to enable PLL and switch system clock to PLL + 676:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @param SYSCLK_Frequency SYSCLK frequency + 677:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + 678:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * the configuration information for the BUS prescalers. + 679:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * @retval An ErrorStatus enumeration value: + 680:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * - SUCCESS: No problem to switch system to PLL + 681:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** * - ERROR: Problem to switch system to PLL + 682:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** */ + 683:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDe + 684:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 713 .loc 1 684 1 is_stmt 1 view -0 + 714 .cfi_startproc + 715 @ args = 0, pretend = 0, frame = 0 + 716 @ frame_needed = 0, uses_anonymous_args = 0 + 717 .loc 1 684 1 is_stmt 0 view .LVU208 + 718 0000 70B5 push {r4, r5, r6, lr} + 719 .LCFI7: + 720 .cfi_def_cfa_offset 16 + 721 .cfi_offset 4, -16 + 722 .cfi_offset 5, -12 + 723 .cfi_offset 6, -8 + 724 .cfi_offset 14, -4 + 725 0002 0C46 mov r4, r1 + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 726 .loc 1 685 3 is_stmt 1 view .LVU209 + 727 .LVL62: + 686:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** uint32_t hclk_frequency = 0U; + 728 .loc 1 686 3 view .LVU210 + 687:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 688:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); + 729 .loc 1 688 3 view .LVU211 + 689:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); + 730 .loc 1 689 3 view .LVU212 + 690:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider)); + 731 .loc 1 690 3 view .LVU213 + 691:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 692:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Calculate HCLK frequency */ + 693:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider); + 732 .loc 1 693 3 view .LVU214 + 733 .loc 1 693 20 is_stmt 0 view .LVU215 + 734 0004 0B68 ldr r3, [r1] + 735 0006 C3F30313 ubfx r3, r3, #4, #4 + 736 000a 254A ldr r2, .L70 + 737 000c D35C ldrb r3, [r2, r3] @ zero_extendqisi2 + 738 .loc 1 693 18 view .LVU216 + 739 000e 20FA03F5 lsr r5, r0, r3 + 740 .LVL63: + 694:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 695:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Increasing the number of wait states because of higher CPU frequency */ + 696:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(SystemCoreClock < hclk_frequency) + 741 .loc 1 696 3 is_stmt 1 view .LVU217 + 742 .loc 1 696 22 is_stmt 0 view .LVU218 + 743 0012 244B ldr r3, .L70+4 + ARM GAS /tmp/ccTd4L28.s page 128 + + + 744 0014 1B68 ldr r3, [r3] + 745 .loc 1 696 5 view .LVU219 + 746 0016 AB42 cmp r3, r5 + 747 0018 31D3 bcc .L67 + 685:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** uint32_t hclk_frequency = 0U; + 748 .loc 1 685 15 view .LVU220 + 749 001a 0026 movs r6, #0 + 750 .LVL64: + 751 .L59: + 697:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 698:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Set FLASH latency to highest latency */ + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** status = LL_SetFlashLatency(hclk_frequency); + 700:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 701:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 702:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Update system clock configuration */ + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(status == SUCCESS) + 704:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 705:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Enable PLL */ + 706:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** LL_RCC_PLL_Enable(); + 752 .loc 1 706 5 is_stmt 1 view .LVU221 + 753 .LBB72: + 754 .LBI72: +3132:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 755 .loc 2 3132 22 view .LVU222 + 756 .LBB73: +3134:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 757 .loc 2 3134 3 view .LVU223 + 758 001c 224A ldr r2, .L70+8 + 759 001e 1368 ldr r3, [r2] + 760 0020 43F08073 orr r3, r3, #16777216 + 761 0024 1360 str r3, [r2] + 762 .LBE73: + 763 .LBE72: + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** while (LL_RCC_PLL_IsReady() != 1U) + 764 .loc 1 707 5 view .LVU224 + 765 .L61: + 708:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 709:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Wait for PLL ready */ + 710:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 766 .loc 1 710 5 view .LVU225 + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** while (LL_RCC_PLL_IsReady() != 1U) + 767 .loc 1 707 33 discriminator 1 view .LVU226 + 768 .LBB74: + 769 .LBI74: +3153:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 770 .loc 2 3153 26 view .LVU227 + 771 .LBB75: +3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 772 .loc 2 3155 3 view .LVU228 +3155:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 773 .loc 2 3155 11 is_stmt 0 view .LVU229 + 774 0026 204B ldr r3, .L70+8 + 775 0028 1B68 ldr r3, [r3] + 776 .LBE75: + 777 .LBE74: + 707:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 778 .loc 1 707 33 discriminator 1 view .LVU230 + ARM GAS /tmp/ccTd4L28.s page 129 + + + 779 002a 13F0007F tst r3, #33554432 + 780 002e FAD0 beq .L61 + 711:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 712:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Sysclk activation on the main PLL */ + 713:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + 781 .loc 1 713 5 is_stmt 1 view .LVU231 + 782 0030 2368 ldr r3, [r4] + 783 .LVL65: + 784 .LBB76: + 785 .LBI76: +2247:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 786 .loc 2 2247 22 view .LVU232 + 787 .LBB77: +2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 788 .loc 2 2249 3 view .LVU233 + 789 0032 1D4A ldr r2, .L70+8 + 790 0034 9168 ldr r1, [r2, #8] + 791 0036 21F0F001 bic r1, r1, #240 + 792 003a 0B43 orrs r3, r3, r1 + 793 .LVL66: +2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 794 .loc 2 2249 3 is_stmt 0 view .LVU234 + 795 003c 9360 str r3, [r2, #8] + 796 .LVL67: +2249:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 797 .loc 2 2249 3 view .LVU235 + 798 .LBE77: + 799 .LBE76: + 714:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + 800 .loc 1 714 5 is_stmt 1 view .LVU236 + 801 .LBB78: + 802 .LBI78: +2214:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 803 .loc 2 2214 22 view .LVU237 + 804 .LBB79: +2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 805 .loc 2 2216 3 view .LVU238 + 806 003e 9368 ldr r3, [r2, #8] + 807 0040 23F00303 bic r3, r3, #3 + 808 0044 43F00203 orr r3, r3, #2 + 809 0048 9360 str r3, [r2, #8] + 810 .LVL68: +2216:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 811 .loc 2 2216 3 is_stmt 0 view .LVU239 + 812 .LBE79: + 813 .LBE78: + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) + 814 .loc 1 715 5 is_stmt 1 view .LVU240 + 815 .L62: + 716:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 717:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Wait for system clock switch to PLL */ + 718:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 816 .loc 1 718 5 view .LVU241 + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) + 817 .loc 1 715 37 discriminator 1 view .LVU242 + 818 .LBB80: + 819 .LBI80: + ARM GAS /tmp/ccTd4L28.s page 130 + + +2227:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 820 .loc 2 2227 26 view .LVU243 + 821 .LBB81: +2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 822 .loc 2 2229 3 view .LVU244 +2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 823 .loc 2 2229 21 is_stmt 0 view .LVU245 + 824 004a 174B ldr r3, .L70+8 + 825 004c 9B68 ldr r3, [r3, #8] +2229:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 826 .loc 2 2229 10 view .LVU246 + 827 004e 03F00C03 and r3, r3, #12 + 828 .LBE81: + 829 .LBE80: + 715:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 830 .loc 1 715 37 discriminator 1 view .LVU247 + 831 0052 082B cmp r3, #8 + 832 0054 F9D1 bne .L62 + 719:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 720:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Set APB1 & APB2 prescaler*/ + 721:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); + 833 .loc 1 721 5 is_stmt 1 view .LVU248 + 834 0056 6268 ldr r2, [r4, #4] + 835 .LVL69: + 836 .LBB82: + 837 .LBI82: +2263:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 838 .loc 2 2263 22 view .LVU249 + 839 .LBB83: +2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 840 .loc 2 2265 3 view .LVU250 + 841 0058 134B ldr r3, .L70+8 + 842 005a 9968 ldr r1, [r3, #8] + 843 005c 21F4E051 bic r1, r1, #7168 + 844 0060 0A43 orrs r2, r2, r1 + 845 .LVL70: +2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 846 .loc 2 2265 3 is_stmt 0 view .LVU251 + 847 0062 9A60 str r2, [r3, #8] + 848 .LVL71: +2265:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 849 .loc 2 2265 3 view .LVU252 + 850 .LBE83: + 851 .LBE82: + 722:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); + 852 .loc 1 722 5 is_stmt 1 view .LVU253 + 853 0064 A268 ldr r2, [r4, #8] + 854 .LVL72: + 855 .LBB84: + 856 .LBI84: +2279:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 857 .loc 2 2279 22 view .LVU254 + 858 .LBB85: +2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 859 .loc 2 2281 3 view .LVU255 + 860 0066 9968 ldr r1, [r3, #8] + 861 0068 21F46041 bic r1, r1, #57344 + ARM GAS /tmp/ccTd4L28.s page 131 + + + 862 006c 0A43 orrs r2, r2, r1 + 863 .LVL73: +2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 864 .loc 2 2281 3 is_stmt 0 view .LVU256 + 865 006e 9A60 str r2, [r3, #8] + 866 .LVL74: + 867 .L60: +2281:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 868 .loc 2 2281 3 view .LVU257 + 869 .LBE85: + 870 .LBE84: + 723:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 724:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 725:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Decreasing the number of wait states because of lower CPU frequency */ + 726:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(SystemCoreClock > hclk_frequency) + 871 .loc 1 726 3 is_stmt 1 view .LVU258 + 872 .loc 1 726 22 is_stmt 0 view .LVU259 + 873 0070 0C4B ldr r3, .L70+4 + 874 0072 1B68 ldr r3, [r3] + 875 .loc 1 726 5 view .LVU260 + 876 0074 AB42 cmp r3, r5 + 877 0076 09D8 bhi .L68 + 878 .L63: + 879 .LVL75: + 727:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 728:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Set FLASH latency to lowest latency */ + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** status = LL_SetFlashLatency(hclk_frequency); + 730:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 731:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 732:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** /* Update SystemCoreClock variable */ + 733:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** if(status == SUCCESS) + 880 .loc 1 733 3 is_stmt 1 view .LVU261 + 881 .loc 1 733 5 is_stmt 0 view .LVU262 + 882 0078 6EB1 cbz r6, .L69 + 883 .L64: + 734:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** LL_SetSystemCoreClock(hclk_frequency); + 736:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 737:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 738:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** return status; + 884 .loc 1 738 3 is_stmt 1 view .LVU263 + 739:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 885 .loc 1 739 1 is_stmt 0 view .LVU264 + 886 007a 3046 mov r0, r6 + 887 007c 70BD pop {r4, r5, r6, pc} + 888 .LVL76: + 889 .L67: + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 890 .loc 1 699 5 is_stmt 1 view .LVU265 + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 891 .loc 1 699 14 is_stmt 0 view .LVU266 + 892 007e 2846 mov r0, r5 + 893 .LVL77: + 699:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 894 .loc 1 699 14 view .LVU267 + 895 0080 FFF7FEFF bl LL_SetFlashLatency + 896 .LVL78: + ARM GAS /tmp/ccTd4L28.s page 132 + + + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 897 .loc 1 703 3 is_stmt 1 view .LVU268 + 703:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 898 .loc 1 703 5 is_stmt 0 view .LVU269 + 899 0084 0646 mov r6, r0 + 900 0086 0028 cmp r0, #0 + 901 0088 F2D1 bne .L60 + 902 008a C7E7 b .L59 + 903 .LVL79: + 904 .L68: + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 905 .loc 1 729 5 is_stmt 1 view .LVU270 + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 906 .loc 1 729 14 is_stmt 0 view .LVU271 + 907 008c 2846 mov r0, r5 + 908 008e FFF7FEFF bl LL_SetFlashLatency + 909 .LVL80: + 910 0092 0646 mov r6, r0 + 911 .LVL81: + 729:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 912 .loc 1 729 14 view .LVU272 + 913 0094 F0E7 b .L63 + 914 .L69: + 735:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 915 .loc 1 735 5 is_stmt 1 view .LVU273 + 916 0096 2846 mov r0, r5 + 917 0098 FFF7FEFF bl LL_SetSystemCoreClock + 918 .LVL82: + 919 009c EDE7 b .L64 + 920 .L71: + 921 009e 00BF .align 2 + 922 .L70: + 923 00a0 00000000 .word AHBPrescTable + 924 00a4 00000000 .word SystemCoreClock + 925 00a8 00380240 .word 1073887232 + 926 .cfi_endproc + 927 .LFE413: + 929 .section .text.LL_PLL_ConfigSystemClock_HSI,"ax",%progbits + 930 .align 1 + 931 .global LL_PLL_ConfigSystemClock_HSI + 932 .syntax unified + 933 .thumb + 934 .thumb_func + 936 LL_PLL_ConfigSystemClock_HSI: + 937 .LVL83: + 938 .LFB409: + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 939 .loc 1 490 1 view -0 + 940 .cfi_startproc + 941 @ args = 0, pretend = 0, frame = 0 + 942 @ frame_needed = 0, uses_anonymous_args = 0 + 490:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 943 .loc 1 490 1 is_stmt 0 view .LVU275 + 944 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 945 .LCFI8: + 946 .cfi_def_cfa_offset 24 + 947 .cfi_offset 3, -24 + ARM GAS /tmp/ccTd4L28.s page 133 + + + 948 .cfi_offset 4, -20 + 949 .cfi_offset 5, -16 + 950 .cfi_offset 6, -12 + 951 .cfi_offset 7, -8 + 952 .cfi_offset 14, -4 + 953 0002 0446 mov r4, r0 + 954 0004 0D46 mov r5, r1 + 491:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** uint32_t pllfreq = 0U; + 955 .loc 1 491 3 is_stmt 1 view .LVU276 + 956 .LVL84: + 492:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 957 .loc 1 492 3 view .LVU277 + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 958 .loc 1 495 3 view .LVU278 + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 959 .loc 1 495 6 is_stmt 0 view .LVU279 + 960 0006 FFF7FEFF bl UTILS_PLL_IsBusy + 961 .LVL85: + 495:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 962 .loc 1 495 5 discriminator 1 view .LVU280 + 963 000a 10BB cbnz r0, .L76 + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 964 .loc 1 498 5 is_stmt 1 view .LVU281 + 498:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 965 .loc 1 498 15 is_stmt 0 view .LVU282 + 966 000c 2146 mov r1, r4 + 967 000e 1248 ldr r0, .L78 + 968 0010 FFF7FEFF bl UTILS_GetPLLOutputFrequency + 969 .LVL86: + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 970 .loc 1 501 5 is_stmt 1 view .LVU283 + 971 .LBB86: + 972 .LBI86: +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 973 .loc 2 2030 26 view .LVU284 + 974 .LBB87: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 975 .loc 2 2032 3 view .LVU285 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 976 .loc 2 2032 11 is_stmt 0 view .LVU286 + 977 0014 114B ldr r3, .L78+4 + 978 0016 1B68 ldr r3, [r3] + 979 .LBE87: + 980 .LBE86: + 501:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 981 .loc 1 501 7 discriminator 1 view .LVU287 + 982 0018 13F0020F tst r3, #2 + 983 001c 09D1 bne .L74 + 503:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** while (LL_RCC_HSI_IsReady() != 1U) + 984 .loc 1 503 7 is_stmt 1 view .LVU288 + 985 .LBB88: + 986 .LBI88: +2010:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 987 .loc 2 2010 22 view .LVU289 + 988 .LBB89: +2012:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 989 .loc 2 2012 3 view .LVU290 + ARM GAS /tmp/ccTd4L28.s page 134 + + + 990 001e 0F4A ldr r2, .L78+4 + 991 0020 1368 ldr r3, [r2] + 992 0022 43F00103 orr r3, r3, #1 + 993 0026 1360 str r3, [r2] + 994 .LBE89: + 995 .LBE88: + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 996 .loc 1 504 7 view .LVU291 + 997 .L75: + 507:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 998 .loc 1 507 7 view .LVU292 + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 999 .loc 1 504 35 discriminator 1 view .LVU293 + 1000 .LBB90: + 1001 .LBI90: +2030:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1002 .loc 2 2030 26 view .LVU294 + 1003 .LBB91: +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1004 .loc 2 2032 3 view .LVU295 +2032:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1005 .loc 2 2032 11 is_stmt 0 view .LVU296 + 1006 0028 0C4B ldr r3, .L78+4 + 1007 002a 1B68 ldr r3, [r3] + 1008 .LBE91: + 1009 .LBE90: + 504:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 1010 .loc 1 504 35 discriminator 1 view .LVU297 + 1011 002c 13F0020F tst r3, #2 + 1012 0030 FAD0 beq .L75 + 1013 .L74: + 511:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** UTILS_PLLInitStruct->PLLP); + 1014 .loc 1 511 5 is_stmt 1 view .LVU298 + 1015 0032 2168 ldr r1, [r4] + 1016 0034 6668 ldr r6, [r4, #4] + 1017 0036 A268 ldr r2, [r4, #8] + 1018 .LVL87: + 1019 .LBB92: + 1020 .LBI92: +3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1021 .loc 2 3241 22 view .LVU299 + 1022 .LBB93: +3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); + 1023 .loc 2 3243 3 view .LVU300 + 1024 0038 084C ldr r4, .L78+4 + 1025 .LVL88: +3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); + 1026 .loc 2 3243 3 is_stmt 0 view .LVU301 + 1027 003a 6768 ldr r7, [r4, #4] + 1028 003c 084B ldr r3, .L78+8 + 1029 003e 3B40 ands r3, r3, r7 + 1030 0040 41EA8611 orr r1, r1, r6, lsl #6 + 1031 .LVL89: +3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); + 1032 .loc 2 3243 3 view .LVU302 + 1033 0044 0A43 orrs r2, r2, r1 + 1034 .LVL90: + ARM GAS /tmp/ccTd4L28.s page 135 + + +3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); + 1035 .loc 2 3243 3 view .LVU303 + 1036 0046 1343 orrs r3, r3, r2 + 1037 0048 6360 str r3, [r4, #4] + 1038 .LVL91: +3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); + 1039 .loc 2 3243 3 view .LVU304 + 1040 .LBE93: + 1041 .LBE92: + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 1042 .loc 1 515 5 is_stmt 1 view .LVU305 + 515:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 1043 .loc 1 515 14 is_stmt 0 view .LVU306 + 1044 004a 2946 mov r1, r5 + 1045 004c FFF7FEFF bl UTILS_EnablePLLAndSwitchSystem + 1046 .LVL92: + 1047 .L73: + 523:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 1048 .loc 1 523 3 is_stmt 1 view .LVU307 + 524:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 1049 .loc 1 524 1 is_stmt 0 view .LVU308 + 1050 0050 F8BD pop {r3, r4, r5, r6, r7, pc} + 1051 .LVL93: + 1052 .L76: + 520:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 1053 .loc 1 520 12 view .LVU309 + 1054 0052 0120 movs r0, #1 + 1055 0054 FCE7 b .L73 + 1056 .L79: + 1057 0056 00BF .align 2 + 1058 .L78: + 1059 0058 0024F400 .word 16000000 + 1060 005c 00380240 .word 1073887232 + 1061 0060 0080BCFF .word -4423680 + 1062 .cfi_endproc + 1063 .LFE409: + 1065 .section .text.LL_PLL_ConfigSystemClock_HSE,"ax",%progbits + 1066 .align 1 + 1067 .global LL_PLL_ConfigSystemClock_HSE + 1068 .syntax unified + 1069 .thumb + 1070 .thumb_func + 1072 LL_PLL_ConfigSystemClock_HSE: + 1073 .LVL94: + 1074 .LFB410: + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 1075 .loc 1 548 1 is_stmt 1 view -0 + 1076 .cfi_startproc + 1077 @ args = 0, pretend = 0, frame = 0 + 1078 @ frame_needed = 0, uses_anonymous_args = 0 + 548:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** ErrorStatus status = SUCCESS; + 1079 .loc 1 548 1 is_stmt 0 view .LVU311 + 1080 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 1081 .LCFI9: + 1082 .cfi_def_cfa_offset 24 + 1083 .cfi_offset 3, -24 + 1084 .cfi_offset 4, -20 + ARM GAS /tmp/ccTd4L28.s page 136 + + + 1085 .cfi_offset 5, -16 + 1086 .cfi_offset 6, -12 + 1087 .cfi_offset 7, -8 + 1088 .cfi_offset 14, -4 + 1089 0002 0646 mov r6, r0 + 1090 0004 0F46 mov r7, r1 + 1091 0006 1446 mov r4, r2 + 1092 0008 1D46 mov r5, r3 + 549:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** uint32_t pllfreq = 0U; + 1093 .loc 1 549 3 is_stmt 1 view .LVU312 + 1094 .LVL95: + 550:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 1095 .loc 1 550 3 view .LVU313 + 553:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); + 1096 .loc 1 553 3 view .LVU314 + 554:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 1097 .loc 1 554 3 view .LVU315 + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 1098 .loc 1 557 3 view .LVU316 + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 1099 .loc 1 557 6 is_stmt 0 view .LVU317 + 1100 000a FFF7FEFF bl UTILS_PLL_IsBusy + 1101 .LVL96: + 557:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 1102 .loc 1 557 5 discriminator 1 view .LVU318 + 1103 000e 0028 cmp r0, #0 + 1104 0010 31D1 bne .L86 + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 1105 .loc 1 560 5 is_stmt 1 view .LVU319 + 560:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 1106 .loc 1 560 15 is_stmt 0 view .LVU320 + 1107 0012 2146 mov r1, r4 + 1108 0014 3046 mov r0, r6 + 1109 0016 FFF7FEFF bl UTILS_GetPLLOutputFrequency + 1110 .LVL97: + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 1111 .loc 1 563 5 is_stmt 1 view .LVU321 + 1112 .LBB94: + 1113 .LBI94: +1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1114 .loc 2 1992 26 view .LVU322 + 1115 .LBB95: +1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1116 .loc 2 1994 3 view .LVU323 +1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1117 .loc 2 1994 11 is_stmt 0 view .LVU324 + 1118 001a 184B ldr r3, .L89 + 1119 001c 1B68 ldr r3, [r3] + 1120 .LBE95: + 1121 .LBE94: + 563:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 1122 .loc 1 563 7 discriminator 1 view .LVU325 + 1123 001e 13F4003F tst r3, #131072 + 1124 0022 10D1 bne .L82 + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 1125 .loc 1 566 7 is_stmt 1 view .LVU326 + 566:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + ARM GAS /tmp/ccTd4L28.s page 137 + + + 1126 .loc 1 566 9 is_stmt 0 view .LVU327 + 1127 0024 012F cmp r7, #1 + 1128 0026 20D0 beq .L88 + 572:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 1129 .loc 1 572 9 is_stmt 1 view .LVU328 + 1130 .LBB96: + 1131 .LBI96: +1962:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1132 .loc 2 1962 22 view .LVU329 + 1133 .LBB97: +1964:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1134 .loc 2 1964 3 view .LVU330 + 1135 0028 144A ldr r2, .L89 + 1136 002a 1368 ldr r3, [r2] + 1137 002c 23F48023 bic r3, r3, #262144 + 1138 0030 1360 str r3, [r2] + 1139 .L84: + 1140 .LBE97: + 1141 .LBE96: + 576:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** while (LL_RCC_HSE_IsReady() != 1U) + 1142 .loc 1 576 7 view .LVU331 + 1143 .LBB98: + 1144 .LBI98: +1972:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1145 .loc 2 1972 22 view .LVU332 + 1146 .LBB99: +1974:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1147 .loc 2 1974 3 view .LVU333 + 1148 0032 124A ldr r2, .L89 + 1149 0034 1368 ldr r3, [r2] + 1150 0036 43F48033 orr r3, r3, #65536 + 1151 003a 1360 str r3, [r2] + 1152 .LBE99: + 1153 .LBE98: + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 1154 .loc 1 577 7 view .LVU334 + 1155 .L85: + 580:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 1156 .loc 1 580 7 view .LVU335 + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 1157 .loc 1 577 35 discriminator 1 view .LVU336 + 1158 .LBB100: + 1159 .LBI100: +1992:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1160 .loc 2 1992 26 view .LVU337 + 1161 .LBB101: +1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1162 .loc 2 1994 3 view .LVU338 +1994:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1163 .loc 2 1994 11 is_stmt 0 view .LVU339 + 1164 003c 0F4A ldr r2, .L89 + 1165 003e 1268 ldr r2, [r2] + 1166 .LBE101: + 1167 .LBE100: + 577:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** { + 1168 .loc 1 577 35 discriminator 1 view .LVU340 + 1169 0040 12F4003F tst r2, #131072 + ARM GAS /tmp/ccTd4L28.s page 138 + + + 1170 0044 FAD0 beq .L85 + 1171 .L82: + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** UTILS_PLLInitStruct->PLLP); + 1172 .loc 1 584 5 is_stmt 1 view .LVU341 + 1173 0046 2268 ldr r2, [r4] + 1174 0048 6668 ldr r6, [r4, #4] + 1175 .LVL98: + 584:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** UTILS_PLLInitStruct->PLLP); + 1176 .loc 1 584 5 is_stmt 0 view .LVU342 + 1177 004a A168 ldr r1, [r4, #8] + 1178 .LVL99: + 1179 .LBB102: + 1180 .LBI102: +3241:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1181 .loc 2 3241 22 is_stmt 1 view .LVU343 + 1182 .LBB103: +3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); + 1183 .loc 2 3243 3 view .LVU344 + 1184 004c 0B4C ldr r4, .L89 + 1185 .LVL100: +3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); + 1186 .loc 2 3243 3 is_stmt 0 view .LVU345 + 1187 004e 6768 ldr r7, [r4, #4] + 1188 .LVL101: +3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); + 1189 .loc 2 3243 3 view .LVU346 + 1190 0050 0B4B ldr r3, .L89+4 + 1191 0052 3B40 ands r3, r3, r7 + 1192 0054 42F48002 orr r2, r2, #4194304 + 1193 .LVL102: +3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); + 1194 .loc 2 3243 3 view .LVU347 + 1195 0058 42EA8612 orr r2, r2, r6, lsl #6 + 1196 005c 0A43 orrs r2, r2, r1 + 1197 005e 1343 orrs r3, r3, r2 + 1198 0060 6360 str r3, [r4, #4] + 1199 .LVL103: +3243:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); + 1200 .loc 2 3243 3 view .LVU348 + 1201 .LBE103: + 1202 .LBE102: + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 1203 .loc 1 588 5 is_stmt 1 view .LVU349 + 588:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 1204 .loc 1 588 14 is_stmt 0 view .LVU350 + 1205 0062 2946 mov r1, r5 + 1206 0064 FFF7FEFF bl UTILS_EnablePLLAndSwitchSystem + 1207 .LVL104: + 1208 .L81: + 596:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 1209 .loc 1 596 3 is_stmt 1 view .LVU351 + 597:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** + 1210 .loc 1 597 1 is_stmt 0 view .LVU352 + 1211 0068 F8BD pop {r3, r4, r5, r6, r7, pc} + 1212 .LVL105: + 1213 .L88: + 568:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + ARM GAS /tmp/ccTd4L28.s page 139 + + + 1214 .loc 1 568 9 is_stmt 1 view .LVU353 + 1215 .LBB104: + 1216 .LBI104: +1952:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** { + 1217 .loc 2 1952 22 view .LVU354 + 1218 .LBB105: +1954:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** } + 1219 .loc 2 1954 3 view .LVU355 + 1220 006a 044A ldr r2, .L89 + 1221 006c 1368 ldr r3, [r2] + 1222 006e 43F48023 orr r3, r3, #262144 + 1223 0072 1360 str r3, [r2] +1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 1224 .loc 2 1955 1 is_stmt 0 view .LVU356 + 1225 0074 DDE7 b .L84 + 1226 .LVL106: + 1227 .L86: +1955:Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h **** + 1228 .loc 2 1955 1 view .LVU357 + 1229 .LBE105: + 1230 .LBE104: + 593:Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c **** } + 1231 .loc 1 593 12 view .LVU358 + 1232 0076 0120 movs r0, #1 + 1233 0078 F6E7 b .L81 + 1234 .L90: + 1235 007a 00BF .align 2 + 1236 .L89: + 1237 007c 00380240 .word 1073887232 + 1238 0080 0080BCFF .word -4423680 + 1239 .cfi_endproc + 1240 .LFE410: + 1242 .text + 1243 .Letext0: + 1244 .file 6 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 1245 .file 7 "Drivers/CMSIS/Include/core_cm7.h" + 1246 .file 8 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h" + 1247 .file 9 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + 1248 .file 10 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + ARM GAS /tmp/ccTd4L28.s page 140 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f7xx_ll_utils.c + /tmp/ccTd4L28.s:20 .text.UTILS_GetPLLOutputFrequency:00000000 $t + /tmp/ccTd4L28.s:25 .text.UTILS_GetPLLOutputFrequency:00000000 UTILS_GetPLLOutputFrequency + /tmp/ccTd4L28.s:74 .text.UTILS_PLL_IsBusy:00000000 $t + /tmp/ccTd4L28.s:79 .text.UTILS_PLL_IsBusy:00000000 UTILS_PLL_IsBusy + /tmp/ccTd4L28.s:154 .text.UTILS_PLL_IsBusy:0000002c $d + /tmp/ccTd4L28.s:159 .text.LL_Init1msTick:00000000 $t + /tmp/ccTd4L28.s:165 .text.LL_Init1msTick:00000000 LL_Init1msTick + /tmp/ccTd4L28.s:206 .text.LL_Init1msTick:0000001c $d + /tmp/ccTd4L28.s:211 .text.LL_mDelay:00000000 $t + /tmp/ccTd4L28.s:217 .text.LL_mDelay:00000000 LL_mDelay + /tmp/ccTd4L28.s:273 .text.LL_SetSystemCoreClock:00000000 $t + /tmp/ccTd4L28.s:279 .text.LL_SetSystemCoreClock:00000000 LL_SetSystemCoreClock + /tmp/ccTd4L28.s:296 .text.LL_SetSystemCoreClock:00000008 $d + /tmp/ccTd4L28.s:301 .text.LL_SetFlashLatency:00000000 $t + /tmp/ccTd4L28.s:307 .text.LL_SetFlashLatency:00000000 LL_SetFlashLatency + /tmp/ccTd4L28.s:693 .text.LL_SetFlashLatency:00000140 $d + /tmp/ccTd4L28.s:705 .text.UTILS_EnablePLLAndSwitchSystem:00000000 $t + /tmp/ccTd4L28.s:710 .text.UTILS_EnablePLLAndSwitchSystem:00000000 UTILS_EnablePLLAndSwitchSystem + /tmp/ccTd4L28.s:923 .text.UTILS_EnablePLLAndSwitchSystem:000000a0 $d + /tmp/ccTd4L28.s:930 .text.LL_PLL_ConfigSystemClock_HSI:00000000 $t + /tmp/ccTd4L28.s:936 .text.LL_PLL_ConfigSystemClock_HSI:00000000 LL_PLL_ConfigSystemClock_HSI + /tmp/ccTd4L28.s:1059 .text.LL_PLL_ConfigSystemClock_HSI:00000058 $d + /tmp/ccTd4L28.s:1066 .text.LL_PLL_ConfigSystemClock_HSE:00000000 $t + /tmp/ccTd4L28.s:1072 .text.LL_PLL_ConfigSystemClock_HSE:00000000 LL_PLL_ConfigSystemClock_HSE + /tmp/ccTd4L28.s:1237 .text.LL_PLL_ConfigSystemClock_HSE:0000007c $d + +UNDEFINED SYMBOLS +SystemCoreClock +AHBPrescTable diff --git a/build/stm32f7xx_ll_utils.o b/build/stm32f7xx_ll_utils.o new file mode 100644 index 0000000000000000000000000000000000000000..ce9c3dccf8ee0b19fd7e2edec8708be2b5e01abc GIT binary patch literal 20452 zcmb`P34B%6wg2}y=T1p(=7A`KHwi{KWt2t(gXUR`K zS2?%E7-ugVI+$JGta5H_cITuv_bpOS|9K5*=_4m zk8E6UY@adb(?jONuvf;C%qEtTaEEqmOnStuT#A~lBPHcOKU%UZZC`a*Qp-yBEn2dp zto1-8j+g7>Wd{}_z3zYteCyzXC7B&bM>ZB%`%0JGS~mHQ-oV2rHhyw`%z~P`%eFtQ zvaBI=-Q*ejXGO@DJTW6es(zv{Ldtp~uljnH%t1-3{^v#@_n;^6$|38c#1`x5Ps(?c zr60&a?P&+HaZJ_6lml5vCnKJegYH1mL02H*pcU{RGy}1aeULqnU69R#MnFN%T%6jG zGn8mq<*7|(b~;-N$v7+RX(LNz?I<($smY)0-%%Eaak%i9Yf0ZCEAaLqGw{|SBXAHq z`Y-S?$EHt}sDw%0jf*dIt7~txHa_<&W8=zA{*C*Ge5%+i>3h^)8HX8QrA}D<`wIdm ztfS*m*8^pRzgH8p5kvXV#(~tP0Cb!UC-&uZj9t8~BWq~Lh%3Lb=|;qe5Qj|b#->qA zZbOWI%QyA-{?#3+OK$1NI&yG%Z27HCcXu$|RLZnpdyhHLv%8?O@2T9%uRr_hYfq)h z{doW0Lyj~gsSg;xvtf=Md(>4KuS+C7kyV*e#j?pdGBYt|f1-}ouu^p$sY7PsiG5ie zZ5?-a_-fiad`r$QDShvn1~hG6T>uJ-t&-U z`n&~L@227TC-O|w{R2ua_j}m%Fnkq`XPqXRR1I^R0z5?{ij)Hp)@H0hIRcab#D_xurGA`@AFj ze4oIJ_XR8EYC6sFtJqIbr+2Sq{Sb;c*7p^5|708t72gVL-`r%X4I{1*7z1;io2XoV zq~pshn4CR|dc*LJi77N=?n64Jw7gEm%rKLkz&gE9&U9p#?-m-J>BzpAdYI30M1KrR z&vwKl-*!|TGsltBe2-9`>&TfZHk^BM|L5< zNX5ME$Ua{y^WSk~bk8dK{kv&BO26AM*CRDeywi@?c?lxD`%tOJI=}C zcNCipUmQ!sJBlra&%-WGa1=KfzPA`tqNCVqsMs!gO}4CfI7{#vt!PB-{YC>kB|eWV zmAD;63}sD3e(ZzRTx6ISYDh_b>)SCuf}DIk?5rj~SDcxnl7B$4O+;7n%M`mr^eO8X z7#Hgjs~sibVol7ObkT-dthHemlUU};u#2rMvT4{w5bd(Aw|1eVUf^FMp%=KNTpu8v zaw|j0%b?z6x_n8gzhEmKFw=C)kf|Qz0h@6bTA7x?)B|QQn~;k=fIV%zU8bEDYoO@C zp1vD`@l!LAJ;VjQi^^TJe8|)R9*5#6_Ke?RLX1Je;9(*Y|7p52o`#l!#lsY8pELcV zQgO;If}jucsr{AdejTmO%tj8+Q<>P+s0EOiZSug|GUL~#+eAp2=OAYuY|f@#Mgb&d zyLhOh-AkzDQ`Ef@f2ci2n(QO^pjlLba+PJWd8sp-ak9`(uV@t%C6hL9FSH@VZe7mEs zw>$a{RChCW-Fq-n=x;O*yYW5KlW`%U!vD(PA&H6Y&~`z}q`-q7h+EN9V?&s_MyHu< zaIConu(Q@d)SC7qgpJ%;%=|CZ_#*akH=!mdTWDb{Pyd{weX%{-pCkVh>}V60!WqV0 z5R7ayK0MJjA@gk385;xtTj(m=oI(FB(4LPy?N&O>HWyQQ9~3{PQdgQ|mb20ipm>K$ zJtcF@OE@L-P-+TxyQe1DJyi!q4V5~`iFS~ip;(VSV-1G+bW~#SFph~CrY~bFw4C$? z4@FEAn=u)iq16Hp#nhIVUhRQ`#X||TrDnpY%hA;}5cFX+wN-|ZI1U@b!_f-$Bn|>6uHDIp4c*Dhpk0LB?&Noka(41o zC~m-Rck(|Bd)-6v5S6-<-#7HSe+P=cV$Zk$(Wjvng9kkUj~c#=i=ov$&I3Ez_{{KX zTM8Br)2KaW*xfk?g5qH@wOP^J;M8vZ(&dW92Q2kt=t90PAV<*m9f}X{soE`snloJC3Y`&`>;f?XQZMvY=gl= z3KI?JP-=DW@(`f*DkDB48`?4oJXA7qt`R$`1lnT|OdedE5>Ff6xoAY@GUV(=CI60H zWfVfRq@O*JO%8wh%?wD;%U?&*0D%ZWa!%S;p!5tY_smP#hf=4>DV^0&JVp# zaEmxwUiZQ_H<8H~!#UTm#z&YlbtcQ~(#a5g|Cq^XY^$XVB&Tq2k({bK;|W_|u3M#y zWMe`?YMhlYI$?z;*{Cy;=y$w|i<=K6ie)G(;jFl`0!J|=Yh%!ry7_=_w0nt1$7gl3no+JSvQ0kK<03A02NQrbe28z@?L$?e8O!8N!CL1Y6iRb1r zKTG2r=;T$Wnx4nX&?)KSKnEs2Z%+E90Z<25^+hYpWG-o_Ihr?^@5XFR3IB=X#jB)_uNh3Qfj@_7> z7ajyQBLLOp$c_l;fu0iCex;^H7GjZU(M7l_u<^uZs`Z)=+G*a{owVuuI#o+ti9J?* zVjWclpH2Qu-AQ>Pc0<(?^b(m3@ubc6w%qY%s0KQ@8oQyE6LbPCj(XGA1D(Q&N#A3d zs^HGGNVA-w&LuWsr<%M$t82FdwySfI(i!e zk4(#k!lCIHoCoHO=(VH_8EW&PQ9@&mv zis(CXRZH0YJ6t;A2|z7JzHBw%YV0FAk!sFMOgLwH#&7}K4Mv7+PH~qiDH|V-l$nuZ z-KynNk2PyMrQ>@Lm#x(K< zJPkWqM&#*a9l`hV&=N(qmY8X433fG>4>8Bq5>416D?pukGcj)1vGE~@PZ_*SkosXq z)e%Y9E!Dr_P9_){{5zwFq%JN8n%frj!xr_9h095t#0F?M!N_~Cqlr6#mqks!Vyj;T z4%o@pfj`^HzW@jAB*&E9OLydW9dIq9vZr9don*1ChJoI2za6o$49k;tb98z3B-JE+ zAWEl|R67n#T|YY%29AMbBF5IQpJ;pVrYCk~SjirgyPBy?Fmi~Hm~l?FPxEAlvkMF+0)WB*cuGGDqmV(U7wG#r_fde*L1c75zcT#VM{d- z>Yh>5#vr@88V5t2T?2V77{q9Oe@jbV2Z!er)+g)xF6}>s^}xD;P_Wy{XvL3fNaMM( zrMExW*wQ^45|*BA)flb^TFiP8XCcfeg(E7rq1<}*Sns+Fx0RZnnwsIBgPj;9__fKeRG!=Gv9gQZF(~Wzl)4il7~?7D zn4sH!xS=>eLw`U!Tc~{@iE%Z;Ia(qaodftBnmkM+V8c$bR$y`HReR)FGg)1>w^KqX^!PN6GhqL3A#rR$;v#AH2bNDSsv^3#Z)YYFwu;Q>aBMz zySL_{t32! z_0|^M&~jaJS2~tCr%!-$192a?2(w!^r9wBwKL)?sM=tH3aK4~ft8ns+inlN--kT!p zwc~vk@h;%Zl1~0GRz}@xZ692z!#Ogn`tD$KL#~ZSy@RGq`Ps=);1x-cgn$Ff>ze1_n^XeKG1w(bg_Q9@md%Hr-?ZNt%=C013 zb|<%bU|~=5>aJkxGF5RqE6Ge6P4Rvauqqjd4pbDL^WZ|kh z-I*v~-rLjG*jE-D}40XWAvcXW_U}$)v z>Hdu>{f+m8xM|D}-x5XMsG%X4VU=CY106Lo$f3^eVDDf^m6z63m$7#czwRJRmKnPD zrS&Kn)%vKhs}J=Lw%8+PuN9Pzn45OJGEU(Z!zOz5aBg#w*^{MgU0?G6dR78mSXZ~K zP9a*B_?@QSp9vdg0_r9G|nmv)9)I_#>s0E+DRWNsJfHLRN{gWA{C zMR&?s1n`2jrh5dfu%|t`!ilPGVg16oa~D<=C?{1IP8EeyGs3Bv;nbPo)GW@PZo56< zLDq{AtsR~O;Wf?0A{{PcgCJ!sRP=T?clI>mROL)b`;<~Nd`jWK+MN(?5N4gzATBzd z>}W+s)F5k^lX^I+K`hG|MU4@QePLro=KxPh&H&n{Hpb|jJ;Z5Mef6+vS!o3;W8(_D z^+MFcrN@RrMNAc*A{kp$n{?E05Y1=mjRo((zFG1$EtY=ge7Z_Sz0TMK7V?CNa}O~(_}Je(w3p=j=J>6nLStu?cQ z)4Qj(_2sqp1*W&-|JF;J``e}$1*R{9)YjS@YMwq2YzcMt_6$I78|=~PuugH(J7JbL z)Ya&-bmYPtUJ@B)wK=zb^q28X(md5(Q)dRu)w&s>#V}EmNbASG#U{A2WIn>+V zSX*8;!Wf#yf!?+dS{~Hlb8ws`Gkn1ck2U@XtWe=lr1Z&LEh;ZRE09}w=2?1p`h#7C z(~BmL94kDG^8x;AY`9OoBEcUYexT=bdH}ogfKQnZ?U8Z-GG9748(#{PCivE0Y50A6 zj4{sOpIMIFB2_N+(btjr7N6Q9HcMWoI4X+|+YuZ7=uBlq$b3t48f1D2U^n?V9Ldyb8X{7P^dc6*C{U1cfHi1Hq7KgKafe&l8;?+AOmaf#S0ywr`3$EW@I z!ZyPxsw}))jJA)}_9fwNiw&2w?c+w+$Ej*$(42F_#H(z!_s7`n4L=J;Y!-eXiLNhR z+pi4U@Q07#%~FXY>=U*96=9RaaEb{_C6AEt<7>obMXe6nM@M7nH*muREd9etq&z$_ z)LQxvfg2~e6GI~^zR=;=6Xv(|2Z#;qTgnX4}IgkSor#a)0w`t9^WeV|MIqD#AOYl zTys21Z{29T^g>&(YI5>SA4mvlDpq(UPJ#?=0dcav)s&6Y9kn%uhjR2JILww z{4}vZ?}1D^uCiE6b@pd0mQ)Rih0obfJ!c8^>|^R_Z)V%)RC5yk1cEY{F624GoPeL^ z$%*#*XZ{Sy=TBCYONCWJ{&YlrgRouLBODNZS9q6jw{XAkEg?^a^vClixmfru;TGWz z;r+sW!Xcr7_lPV%NjO`mzd3-uUF1uJ*9vbI-Ya}exL5d^@R0B`p%g^viI z6TU2bOUOTfr+@xIAelvu!u%0VCUY=_(RqUVPYtZ$p}J`(-^D2bEEFN80M{$&#Ny(;{xlap}16ggcu zjzpaN^_!d|oGF|uoF`l?Tqdj+HVK2mPT?Bi<-!fZtt8^wF1$l{mvEQxA>m`fCxp+F zi1*jR-wIz79u%Gs`ter>Z2xKGXv}M27Ku2fO8#t-&lZ-5zD8vJ`2+1&h`w3mpztEm zuMzn&;ngJS-6Fg}c#H5y!n=k4E__7zxbS)5uZ6!A{*^>re-pkh91|_=fO3;Xj3+2yuI??cKr{VTN$D@C;!AiT2GD&KG^TaFMW%ME{&m z;%1~#*d_Y)!p$UZ39l1=kA(l5CI4=bcM6{r{T>oGs4oitAo@chzb_mTenG-7A3Dhx zVZ1PnM7;O{P_sx_Dy$WLTi7kULikX|d|HT}(bpYZ{_X3XkoTXw9_0$B3H5y=^s_}?BwQlo zpK`F=xxzKV%Y;`6Hw$kNZWZ1vyiNFskk1zM`;2gp@Fn5zgs%zzBz#Nwcj0m2mqPrW zto_Ca`B@a}2?!?%rwaKw6!S}k{J@DaKaV8&Y(%yS*9xx?UM;*<$ghxiz2+xAq`vP3 ze=71L!pDXDeu&p)eP0Z|CNe*~q@Ldnk$7pN>E(Sa)78D8DM?*G!Z@5bBQ~ARiN%A2=~TT{wxvb!)0{hH$o!A0#oqUidBHw}nAr zr*NHcy^!B7vHW)7Z9@Hg0lj{{03R3qGr~Q>mxR9)z9W2B_>u6a@CzYcU+H@Fa|!(8 z&+4^&h7fDq)kbRk&Vwm2ex0>*!6wJB0eV1N!?#{;BX$AwNK6 zxo3sX3x6Zj&mqX?M@_UFE!58uko9u}I9>FG!a2fXVYzUTP(N3oT%E|Pgck~1h5XWz z_4Wz}gqI1g6mAw?C*&uWEVo^FoA6HIPT?*gKenR1er^Gu6!{t9Ug1kZ{Tu^3{Tu_n zA^JCk9|`qy4D!Da8Lz8!Jzk-Ho^!JePQQus6NS@-g+l#&13&ut2CNW$m9SRWAnX=iB3vh2FWe;DBGk`0@T;G5z}rNB zr;y*xu|1Cp_mH?xd{MYh_=@n)Lj8OLyCWhW6MikUc%P4ae#^%D$4ucgVSy0SOPN{r z`!`-UGbzJIfJC`m5`OT?PT$|oArWs0iR*q9iStb@iSsfy`oU>T6RxyBxYE@3SrFjD zj*EnUzTG7QB<`cf3w8Z4o<My1YmXL^}LU^Ox7yN}pFhO27QU6X7 z_37&>>Wk;~1^$P4{)OLhTzByIUnKk?OPL5p_Yc~q-r&Au^j5T zK*~3fsIN=pJ`&Eii@bwG{SS-$2#GlMiTn!5e$E?M*BxqJ4Tkz{b~q{g*ceiI{Ap0- zt;SE>c~s=tFP2aJ2LO>4_7AE0)w8X}8{f!ZO~Xog$()BD)WW(`yl#%ni+briT+j~f zU%uZSHvEQ{&(-Sx$!wu*)*4(r*xuOL)7FcQ(&^^atNVj%B6IP|J5p@!Z|-RiqBq%I zyUfWN{3%Y*@rdD2c`d!&-9h|iNkpl({^o8NmDVlIYYv6_J68{e;P(Gx!*o!X&iY+A zi_PRAV#CzdTNaMA!_?N>NIT|nn}i)x`2T9hH8`@~0Cdjg)O!vTk#-G`xo({eOH6M; z93$;EK@R8~`{3B|St`=*9>`N7?3{Y}TSKHB*9?|ocys(+4-HO#szh>pc*tY>v#^u2 zBX?ns^!I1TO;pI{_}dFP(ykZ*J?I#Lj@@%eN7kE!dUK&;y?AU7*E@uCq`$-P*9x7p zIsV>I>O%u_~U()vpN257~yXR{8hn-{!Yj4_`6;F6^MiB z6Y;I$2!Hf>?+ClwrrYNTDW>~{c6?SRoox^7I47OWnO6_PC~`awMzoigGAF)gVTY;I z=ahdKzYi8U0_fC5MobU&HtY&eFdO=**y%3`JL`lxyrsd}$6;yMALnAET^~Aczf&3V HoaFxjo-&E4 literal 0 HcmV?d00001 diff --git a/build/syscall.d b/build/syscall.d new file mode 100644 index 0000000..80daec2 --- /dev/null +++ b/build/syscall.d @@ -0,0 +1,100 @@ +build/syscall.o: Middlewares/Third_Party/FatFs/src/option/syscall.c \ + Middlewares/Third_Party/FatFs/src/option/../ff.h \ + Middlewares/Third_Party/FatFs/src/option/../integer.h Inc/ffconf.h \ + Inc/main.h Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h Inc/bsp_driver_sd.h \ + Inc/fatfs_platform.h +Middlewares/Third_Party/FatFs/src/option/../ff.h: +Middlewares/Third_Party/FatFs/src/option/../integer.h: +Inc/ffconf.h: +Inc/main.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h: +Inc/bsp_driver_sd.h: +Inc/fatfs_platform.h: diff --git a/build/syscall.lst b/build/syscall.lst new file mode 100644 index 0000000..be05997 --- /dev/null +++ b/build/syscall.lst @@ -0,0 +1,33 @@ +ARM GAS /tmp/ccLTnVRs.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "syscall.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Middlewares/Third_Party/FatFs/src/option/syscall.c" + 19 .Letext0: + 20 .file 2 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h" + 21 .file 3 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h" + 22 .file 4 "Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h" + 23 .file 5 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + ARM GAS /tmp/ccLTnVRs.s page 2 + + +DEFINED SYMBOLS + *ABS*:00000000 syscall.c + +NO UNDEFINED SYMBOLS diff --git a/build/syscall.o b/build/syscall.o new file mode 100644 index 0000000000000000000000000000000000000000..147e0312c03048000d4a9777df350de16ba4b3b9 GIT binary patch literal 2620 zcmb7GL2nyH6rT02<89rBl(cC}E963fpw_#w(==^ps-|w78pVwp8&o99YP`FSSF(4l z-F0vehzmj-K%zH}T;LxdA;Ffy4m`A^6^UCSF%az*Bae@++(cguhF&4Q(mOw+V$*Ysy8 z@S0?G@H*4=Z-MI8G|TjLVq1dEXfyiZBXh^~A89{auu29ygdthN6xGWh;9>m0tn#=TnNet)!65bmpWO<*eK(BEW~;tjuC9(o*6odL zYs{K8-)8183eBF^Hur4Xh_gedMW zmpe3JuV*=ZZggo6Q*7+@|A7r{Te1$S61s{_^#XsdkTg`Oe791u8r$2=joPi+tGf+s z({Ay0&t*eD^7ee!DUjO`%@r$V&D*tV%W7@hv?`TRV?5WC<7D$@S3gV1VJZa(G=#)^VYOr_jq?ZI%}4#L;a&4-;2>s5`PxJ#WbyhpI=7>dIET%AZD&l~X z#3cvk1VcLdNfLJ`iOCYhc-k}Ds#Mkri=~ydWY?kFD;3KxKAr-$Q9`wGs&A&e05!Y1 zS*){}qq+K_%whdW?YMG6IjNpfPAg9-XO*XwXXwgJOPbNxuYaYj>eNe3_ji1=rH`6a zyX=vD`p&Bi4@^o_ysK$Z$8Y2Tr80U!CZaMtF)2~mk@Uq)X3ro5SeC(adraU7fu{-a zuu*ErZU|fvcuinM;L8H<3cM%K66gqgU*JQ5UkLnK;P(Rm6gZD0Q~c`!?+Uypkg}Aa zpCu!D(2sc=7>8r*N)1IGGlNQ!8SN-y25Q1^-1czK^88K!Q=;>BJ9PKcRvvPH&&7bT zL(lVFsbg+t*g?PVqU4N?-MYc!IP}`X82G^ad>?d$iq|F0CI_;a}H~8I@$wi-R z^x^%O^1F=MqMS;Res6(5jt7#z55KbP0LhPpFcpS<2){?*=syj*dz8O9e6&}2W>8rJ Xc~0M8IUn8AwBJP};{zHXMEd;=XjhGm literal 0 HcmV?d00001 diff --git a/build/syscalls.d b/build/syscalls.d new file mode 100644 index 0000000..d61fce2 --- /dev/null +++ b/build/syscalls.d @@ -0,0 +1 @@ +build/syscalls.o: Src/syscalls.c diff --git a/build/syscalls.lst b/build/syscalls.lst new file mode 100644 index 0000000..4dc1f54 --- /dev/null +++ b/build/syscalls.lst @@ -0,0 +1,871 @@ +ARM GAS /tmp/ccEcvKCS.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "syscalls.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Src/syscalls.c" + 19 .section .text.initialise_monitor_handles,"ax",%progbits + 20 .align 1 + 21 .global initialise_monitor_handles + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 initialise_monitor_handles: + 27 .LFB25: + 1:Src/syscalls.c **** /** + 2:Src/syscalls.c **** ****************************************************************************** + 3:Src/syscalls.c **** * @file syscalls.c + 4:Src/syscalls.c **** * @author Auto-generated by STM32CubeMX + 5:Src/syscalls.c **** * @brief Minimal System calls file + 6:Src/syscalls.c **** * + 7:Src/syscalls.c **** * For more information about which c-functions + 8:Src/syscalls.c **** * need which of these lowlevel functions + 9:Src/syscalls.c **** * please consult the Newlib libc-manual + 10:Src/syscalls.c **** ****************************************************************************** + 11:Src/syscalls.c **** * @attention + 12:Src/syscalls.c **** * + 13:Src/syscalls.c **** * Copyright (c) 2020-2024 STMicroelectronics. + 14:Src/syscalls.c **** * All rights reserved. + 15:Src/syscalls.c **** * + 16:Src/syscalls.c **** * This software is licensed under terms that can be found in the LICENSE file + 17:Src/syscalls.c **** * in the root directory of this software component. + 18:Src/syscalls.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 19:Src/syscalls.c **** * + 20:Src/syscalls.c **** ****************************************************************************** + 21:Src/syscalls.c **** */ + 22:Src/syscalls.c **** + 23:Src/syscalls.c **** /* Includes */ + 24:Src/syscalls.c **** #include + 25:Src/syscalls.c **** #include + 26:Src/syscalls.c **** #include + 27:Src/syscalls.c **** #include + 28:Src/syscalls.c **** #include + 29:Src/syscalls.c **** #include + 30:Src/syscalls.c **** #include + 31:Src/syscalls.c **** #include + ARM GAS /tmp/ccEcvKCS.s page 2 + + + 32:Src/syscalls.c **** + 33:Src/syscalls.c **** + 34:Src/syscalls.c **** /* Variables */ + 35:Src/syscalls.c **** extern int __io_putchar(int ch) __attribute__((weak)); + 36:Src/syscalls.c **** extern int __io_getchar(void) __attribute__((weak)); + 37:Src/syscalls.c **** + 38:Src/syscalls.c **** + 39:Src/syscalls.c **** char *__env[1] = { 0 }; + 40:Src/syscalls.c **** char **environ = __env; + 41:Src/syscalls.c **** + 42:Src/syscalls.c **** + 43:Src/syscalls.c **** /* Functions */ + 44:Src/syscalls.c **** void initialise_monitor_handles() + 45:Src/syscalls.c **** { + 28 .loc 1 45 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 46:Src/syscalls.c **** } + 33 .loc 1 46 1 view .LVU1 + 34 0000 7047 bx lr + 35 .cfi_endproc + 36 .LFE25: + 38 .section .text._getpid,"ax",%progbits + 39 .align 1 + 40 .global _getpid + 41 .syntax unified + 42 .thumb + 43 .thumb_func + 45 _getpid: + 46 .LFB26: + 47:Src/syscalls.c **** + 48:Src/syscalls.c **** int _getpid(void) + 49:Src/syscalls.c **** { + 47 .loc 1 49 1 view -0 + 48 .cfi_startproc + 49 @ args = 0, pretend = 0, frame = 0 + 50 @ frame_needed = 0, uses_anonymous_args = 0 + 51 @ link register save eliminated. + 50:Src/syscalls.c **** return 1; + 52 .loc 1 50 3 view .LVU3 + 51:Src/syscalls.c **** } + 53 .loc 1 51 1 is_stmt 0 view .LVU4 + 54 0000 0120 movs r0, #1 + 55 0002 7047 bx lr + 56 .cfi_endproc + 57 .LFE26: + 59 .section .text._kill,"ax",%progbits + 60 .align 1 + 61 .global _kill + 62 .syntax unified + 63 .thumb + 64 .thumb_func + 66 _kill: + 67 .LVL0: + 68 .LFB27: + ARM GAS /tmp/ccEcvKCS.s page 3 + + + 52:Src/syscalls.c **** + 53:Src/syscalls.c **** int _kill(int pid, int sig) + 54:Src/syscalls.c **** { + 69 .loc 1 54 1 is_stmt 1 view -0 + 70 .cfi_startproc + 71 @ args = 0, pretend = 0, frame = 0 + 72 @ frame_needed = 0, uses_anonymous_args = 0 + 73 .loc 1 54 1 is_stmt 0 view .LVU6 + 74 0000 08B5 push {r3, lr} + 75 .LCFI0: + 76 .cfi_def_cfa_offset 8 + 77 .cfi_offset 3, -8 + 78 .cfi_offset 14, -4 + 55:Src/syscalls.c **** (void)pid; + 79 .loc 1 55 3 is_stmt 1 view .LVU7 + 56:Src/syscalls.c **** (void)sig; + 80 .loc 1 56 3 view .LVU8 + 57:Src/syscalls.c **** errno = EINVAL; + 81 .loc 1 57 3 view .LVU9 + 82 0002 FFF7FEFF bl __errno + 83 .LVL1: + 84 .loc 1 57 9 is_stmt 0 discriminator 1 view .LVU10 + 85 0006 1623 movs r3, #22 + 86 0008 0360 str r3, [r0] + 58:Src/syscalls.c **** return -1; + 87 .loc 1 58 3 is_stmt 1 view .LVU11 + 59:Src/syscalls.c **** } + 88 .loc 1 59 1 is_stmt 0 view .LVU12 + 89 000a 4FF0FF30 mov r0, #-1 + 90 000e 08BD pop {r3, pc} + 91 .cfi_endproc + 92 .LFE27: + 94 .section .text._exit,"ax",%progbits + 95 .align 1 + 96 .global _exit + 97 .syntax unified + 98 .thumb + 99 .thumb_func + 101 _exit: + 102 .LVL2: + 103 .LFB28: + 60:Src/syscalls.c **** + 61:Src/syscalls.c **** void _exit (int status) + 62:Src/syscalls.c **** { + 104 .loc 1 62 1 is_stmt 1 view -0 + 105 .cfi_startproc + 106 @ Volatile: function does not return. + 107 @ args = 0, pretend = 0, frame = 0 + 108 @ frame_needed = 0, uses_anonymous_args = 0 + 109 .loc 1 62 1 is_stmt 0 view .LVU14 + 110 0000 08B5 push {r3, lr} + 111 .LCFI1: + 112 .cfi_def_cfa_offset 8 + 113 .cfi_offset 3, -8 + 114 .cfi_offset 14, -4 + 63:Src/syscalls.c **** _kill(status, -1); + 115 .loc 1 63 3 is_stmt 1 view .LVU15 + ARM GAS /tmp/ccEcvKCS.s page 4 + + + 116 0002 4FF0FF31 mov r1, #-1 + 117 0006 FFF7FEFF bl _kill + 118 .LVL3: + 119 .L6: + 64:Src/syscalls.c **** while (1) {} /* Make sure we hang here */ + 120 .loc 1 64 3 view .LVU16 + 121 .loc 1 64 14 view .LVU17 + 122 .loc 1 64 9 view .LVU18 + 123 000a FEE7 b .L6 + 124 .cfi_endproc + 125 .LFE28: + 127 .section .text._read,"ax",%progbits + 128 .align 1 + 129 .weak _read + 130 .syntax unified + 131 .thumb + 132 .thumb_func + 134 _read: + 135 .LVL4: + 136 .LFB29: + 65:Src/syscalls.c **** } + 66:Src/syscalls.c **** + 67:Src/syscalls.c **** __attribute__((weak)) int _read(int file, char *ptr, int len) + 68:Src/syscalls.c **** { + 137 .loc 1 68 1 view -0 + 138 .cfi_startproc + 139 @ args = 0, pretend = 0, frame = 0 + 140 @ frame_needed = 0, uses_anonymous_args = 0 + 141 .loc 1 68 1 is_stmt 0 view .LVU20 + 142 0000 70B5 push {r4, r5, r6, lr} + 143 .LCFI2: + 144 .cfi_def_cfa_offset 16 + 145 .cfi_offset 4, -16 + 146 .cfi_offset 5, -12 + 147 .cfi_offset 6, -8 + 148 .cfi_offset 14, -4 + 149 0002 0C46 mov r4, r1 + 150 0004 1646 mov r6, r2 + 69:Src/syscalls.c **** (void)file; + 151 .loc 1 69 3 is_stmt 1 view .LVU21 + 70:Src/syscalls.c **** int DataIdx; + 152 .loc 1 70 3 view .LVU22 + 71:Src/syscalls.c **** + 72:Src/syscalls.c **** for (DataIdx = 0; DataIdx < len; DataIdx++) + 153 .loc 1 72 3 view .LVU23 + 154 .LVL5: + 155 .loc 1 72 16 is_stmt 0 view .LVU24 + 156 0006 0025 movs r5, #0 + 157 .loc 1 72 3 view .LVU25 + 158 0008 06E0 b .L9 + 159 .LVL6: + 160 .L10: + 73:Src/syscalls.c **** { + 74:Src/syscalls.c **** *ptr++ = __io_getchar(); + 161 .loc 1 74 5 is_stmt 1 view .LVU26 + 162 .loc 1 74 14 is_stmt 0 view .LVU27 + 163 000a FFF7FEFF bl __io_getchar + ARM GAS /tmp/ccEcvKCS.s page 5 + + + 164 .LVL7: + 165 .loc 1 74 9 discriminator 1 view .LVU28 + 166 000e 2146 mov r1, r4 + 167 .LVL8: + 168 .loc 1 74 12 discriminator 1 view .LVU29 + 169 0010 01F8010B strb r0, [r1], #1 + 170 .LVL9: + 72:Src/syscalls.c **** { + 171 .loc 1 72 43 is_stmt 1 discriminator 3 view .LVU30 + 172 0014 0135 adds r5, r5, #1 + 173 .LVL10: + 174 .loc 1 74 9 is_stmt 0 discriminator 1 view .LVU31 + 175 0016 0C46 mov r4, r1 + 176 .LVL11: + 177 .L9: + 72:Src/syscalls.c **** { + 178 .loc 1 72 29 is_stmt 1 discriminator 1 view .LVU32 + 179 0018 B542 cmp r5, r6 + 180 001a F6DB blt .L10 + 75:Src/syscalls.c **** } + 76:Src/syscalls.c **** + 77:Src/syscalls.c **** return len; + 181 .loc 1 77 3 view .LVU33 + 78:Src/syscalls.c **** } + 182 .loc 1 78 1 is_stmt 0 view .LVU34 + 183 001c 3046 mov r0, r6 + 184 001e 70BD pop {r4, r5, r6, pc} + 185 .loc 1 78 1 view .LVU35 + 186 .cfi_endproc + 187 .LFE29: + 189 .section .text._write,"ax",%progbits + 190 .align 1 + 191 .weak _write + 192 .syntax unified + 193 .thumb + 194 .thumb_func + 196 _write: + 197 .LVL12: + 198 .LFB30: + 79:Src/syscalls.c **** + 80:Src/syscalls.c **** __attribute__((weak)) int _write(int file, char *ptr, int len) + 81:Src/syscalls.c **** { + 199 .loc 1 81 1 is_stmt 1 view -0 + 200 .cfi_startproc + 201 @ args = 0, pretend = 0, frame = 0 + 202 @ frame_needed = 0, uses_anonymous_args = 0 + 203 .loc 1 81 1 is_stmt 0 view .LVU37 + 204 0000 70B5 push {r4, r5, r6, lr} + 205 .LCFI3: + 206 .cfi_def_cfa_offset 16 + 207 .cfi_offset 4, -16 + 208 .cfi_offset 5, -12 + 209 .cfi_offset 6, -8 + 210 .cfi_offset 14, -4 + 211 0002 0C46 mov r4, r1 + 212 0004 1646 mov r6, r2 + 82:Src/syscalls.c **** (void)file; + ARM GAS /tmp/ccEcvKCS.s page 6 + + + 213 .loc 1 82 3 is_stmt 1 view .LVU38 + 83:Src/syscalls.c **** int DataIdx; + 214 .loc 1 83 3 view .LVU39 + 84:Src/syscalls.c **** + 85:Src/syscalls.c **** for (DataIdx = 0; DataIdx < len; DataIdx++) + 215 .loc 1 85 3 view .LVU40 + 216 .LVL13: + 217 .loc 1 85 16 is_stmt 0 view .LVU41 + 218 0006 0025 movs r5, #0 + 219 .loc 1 85 3 view .LVU42 + 220 0008 04E0 b .L13 + 221 .LVL14: + 222 .L14: + 86:Src/syscalls.c **** { + 87:Src/syscalls.c **** __io_putchar(*ptr++); + 223 .loc 1 87 5 is_stmt 1 view .LVU43 + 224 .loc 1 87 5 is_stmt 0 view .LVU44 + 225 000a 14F8010B ldrb r0, [r4], #1 @ zero_extendqisi2 + 226 .LVL15: + 227 .loc 1 87 5 view .LVU45 + 228 000e FFF7FEFF bl __io_putchar + 229 .LVL16: + 85:Src/syscalls.c **** { + 230 .loc 1 85 43 is_stmt 1 discriminator 3 view .LVU46 + 231 0012 0135 adds r5, r5, #1 + 232 .LVL17: + 233 .L13: + 85:Src/syscalls.c **** { + 234 .loc 1 85 29 discriminator 1 view .LVU47 + 235 0014 B542 cmp r5, r6 + 236 0016 F8DB blt .L14 + 88:Src/syscalls.c **** } + 89:Src/syscalls.c **** return len; + 237 .loc 1 89 3 view .LVU48 + 90:Src/syscalls.c **** } + 238 .loc 1 90 1 is_stmt 0 view .LVU49 + 239 0018 3046 mov r0, r6 + 240 001a 70BD pop {r4, r5, r6, pc} + 241 .loc 1 90 1 view .LVU50 + 242 .cfi_endproc + 243 .LFE30: + 245 .section .text._close,"ax",%progbits + 246 .align 1 + 247 .global _close + 248 .syntax unified + 249 .thumb + 250 .thumb_func + 252 _close: + 253 .LVL18: + 254 .LFB31: + 91:Src/syscalls.c **** + 92:Src/syscalls.c **** int _close(int file) + 93:Src/syscalls.c **** { + 255 .loc 1 93 1 is_stmt 1 view -0 + 256 .cfi_startproc + 257 @ args = 0, pretend = 0, frame = 0 + 258 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccEcvKCS.s page 7 + + + 259 @ link register save eliminated. + 94:Src/syscalls.c **** (void)file; + 260 .loc 1 94 3 view .LVU52 + 95:Src/syscalls.c **** return -1; + 261 .loc 1 95 3 view .LVU53 + 96:Src/syscalls.c **** } + 262 .loc 1 96 1 is_stmt 0 view .LVU54 + 263 0000 4FF0FF30 mov r0, #-1 + 264 .LVL19: + 265 .loc 1 96 1 view .LVU55 + 266 0004 7047 bx lr + 267 .cfi_endproc + 268 .LFE31: + 270 .section .text._fstat,"ax",%progbits + 271 .align 1 + 272 .global _fstat + 273 .syntax unified + 274 .thumb + 275 .thumb_func + 277 _fstat: + 278 .LVL20: + 279 .LFB32: + 97:Src/syscalls.c **** + 98:Src/syscalls.c **** + 99:Src/syscalls.c **** int _fstat(int file, struct stat *st) + 100:Src/syscalls.c **** { + 280 .loc 1 100 1 is_stmt 1 view -0 + 281 .cfi_startproc + 282 @ args = 0, pretend = 0, frame = 0 + 283 @ frame_needed = 0, uses_anonymous_args = 0 + 284 @ link register save eliminated. + 101:Src/syscalls.c **** (void)file; + 285 .loc 1 101 3 view .LVU57 + 102:Src/syscalls.c **** st->st_mode = S_IFCHR; + 286 .loc 1 102 3 view .LVU58 + 287 .loc 1 102 15 is_stmt 0 view .LVU59 + 288 0000 4FF40053 mov r3, #8192 + 289 0004 4B60 str r3, [r1, #4] + 103:Src/syscalls.c **** return 0; + 290 .loc 1 103 3 is_stmt 1 view .LVU60 + 104:Src/syscalls.c **** } + 291 .loc 1 104 1 is_stmt 0 view .LVU61 + 292 0006 0020 movs r0, #0 + 293 .LVL21: + 294 .loc 1 104 1 view .LVU62 + 295 0008 7047 bx lr + 296 .cfi_endproc + 297 .LFE32: + 299 .section .text._isatty,"ax",%progbits + 300 .align 1 + 301 .global _isatty + 302 .syntax unified + 303 .thumb + 304 .thumb_func + 306 _isatty: + 307 .LVL22: + 308 .LFB33: + ARM GAS /tmp/ccEcvKCS.s page 8 + + + 105:Src/syscalls.c **** + 106:Src/syscalls.c **** int _isatty(int file) + 107:Src/syscalls.c **** { + 309 .loc 1 107 1 is_stmt 1 view -0 + 310 .cfi_startproc + 311 @ args = 0, pretend = 0, frame = 0 + 312 @ frame_needed = 0, uses_anonymous_args = 0 + 313 @ link register save eliminated. + 108:Src/syscalls.c **** (void)file; + 314 .loc 1 108 3 view .LVU64 + 109:Src/syscalls.c **** return 1; + 315 .loc 1 109 3 view .LVU65 + 110:Src/syscalls.c **** } + 316 .loc 1 110 1 is_stmt 0 view .LVU66 + 317 0000 0120 movs r0, #1 + 318 .LVL23: + 319 .loc 1 110 1 view .LVU67 + 320 0002 7047 bx lr + 321 .cfi_endproc + 322 .LFE33: + 324 .section .text._lseek,"ax",%progbits + 325 .align 1 + 326 .global _lseek + 327 .syntax unified + 328 .thumb + 329 .thumb_func + 331 _lseek: + 332 .LVL24: + 333 .LFB34: + 111:Src/syscalls.c **** + 112:Src/syscalls.c **** int _lseek(int file, int ptr, int dir) + 113:Src/syscalls.c **** { + 334 .loc 1 113 1 is_stmt 1 view -0 + 335 .cfi_startproc + 336 @ args = 0, pretend = 0, frame = 0 + 337 @ frame_needed = 0, uses_anonymous_args = 0 + 338 @ link register save eliminated. + 114:Src/syscalls.c **** (void)file; + 339 .loc 1 114 3 view .LVU69 + 115:Src/syscalls.c **** (void)ptr; + 340 .loc 1 115 3 view .LVU70 + 116:Src/syscalls.c **** (void)dir; + 341 .loc 1 116 3 view .LVU71 + 117:Src/syscalls.c **** return 0; + 342 .loc 1 117 3 view .LVU72 + 118:Src/syscalls.c **** } + 343 .loc 1 118 1 is_stmt 0 view .LVU73 + 344 0000 0020 movs r0, #0 + 345 .LVL25: + 346 .loc 1 118 1 view .LVU74 + 347 0002 7047 bx lr + 348 .cfi_endproc + 349 .LFE34: + 351 .section .text._open,"ax",%progbits + 352 .align 1 + 353 .global _open + 354 .syntax unified + ARM GAS /tmp/ccEcvKCS.s page 9 + + + 355 .thumb + 356 .thumb_func + 358 _open: + 359 .LVL26: + 360 .LFB35: + 119:Src/syscalls.c **** + 120:Src/syscalls.c **** int _open(char *path, int flags, ...) + 121:Src/syscalls.c **** { + 361 .loc 1 121 1 is_stmt 1 view -0 + 362 .cfi_startproc + 363 @ args = 4, pretend = 12, frame = 0 + 364 @ frame_needed = 0, uses_anonymous_args = 1 + 365 @ link register save eliminated. + 366 .loc 1 121 1 is_stmt 0 view .LVU76 + 367 0000 0EB4 push {r1, r2, r3} + 368 .LCFI4: + 369 .cfi_def_cfa_offset 12 + 370 .cfi_offset 1, -12 + 371 .cfi_offset 2, -8 + 372 .cfi_offset 3, -4 + 122:Src/syscalls.c **** (void)path; + 373 .loc 1 122 3 is_stmt 1 view .LVU77 + 123:Src/syscalls.c **** (void)flags; + 374 .loc 1 123 3 view .LVU78 + 124:Src/syscalls.c **** /* Pretend like we always fail */ + 125:Src/syscalls.c **** return -1; + 375 .loc 1 125 3 view .LVU79 + 126:Src/syscalls.c **** } + 376 .loc 1 126 1 is_stmt 0 view .LVU80 + 377 0002 4FF0FF30 mov r0, #-1 + 378 .LVL27: + 379 .loc 1 126 1 view .LVU81 + 380 0006 03B0 add sp, sp, #12 + 381 .LCFI5: + 382 .cfi_restore 3 + 383 .cfi_restore 2 + 384 .cfi_restore 1 + 385 .cfi_def_cfa_offset 0 + 386 0008 7047 bx lr + 387 .cfi_endproc + 388 .LFE35: + 390 .section .text._wait,"ax",%progbits + 391 .align 1 + 392 .global _wait + 393 .syntax unified + 394 .thumb + 395 .thumb_func + 397 _wait: + 398 .LVL28: + 399 .LFB36: + 127:Src/syscalls.c **** + 128:Src/syscalls.c **** int _wait(int *status) + 129:Src/syscalls.c **** { + 400 .loc 1 129 1 is_stmt 1 view -0 + 401 .cfi_startproc + 402 @ args = 0, pretend = 0, frame = 0 + 403 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccEcvKCS.s page 10 + + + 404 .loc 1 129 1 is_stmt 0 view .LVU83 + 405 0000 08B5 push {r3, lr} + 406 .LCFI6: + 407 .cfi_def_cfa_offset 8 + 408 .cfi_offset 3, -8 + 409 .cfi_offset 14, -4 + 130:Src/syscalls.c **** (void)status; + 410 .loc 1 130 3 is_stmt 1 view .LVU84 + 131:Src/syscalls.c **** errno = ECHILD; + 411 .loc 1 131 3 view .LVU85 + 412 0002 FFF7FEFF bl __errno + 413 .LVL29: + 414 .loc 1 131 9 is_stmt 0 discriminator 1 view .LVU86 + 415 0006 0A23 movs r3, #10 + 416 0008 0360 str r3, [r0] + 132:Src/syscalls.c **** return -1; + 417 .loc 1 132 3 is_stmt 1 view .LVU87 + 133:Src/syscalls.c **** } + 418 .loc 1 133 1 is_stmt 0 view .LVU88 + 419 000a 4FF0FF30 mov r0, #-1 + 420 000e 08BD pop {r3, pc} + 421 .cfi_endproc + 422 .LFE36: + 424 .section .text._unlink,"ax",%progbits + 425 .align 1 + 426 .global _unlink + 427 .syntax unified + 428 .thumb + 429 .thumb_func + 431 _unlink: + 432 .LVL30: + 433 .LFB37: + 134:Src/syscalls.c **** + 135:Src/syscalls.c **** int _unlink(char *name) + 136:Src/syscalls.c **** { + 434 .loc 1 136 1 is_stmt 1 view -0 + 435 .cfi_startproc + 436 @ args = 0, pretend = 0, frame = 0 + 437 @ frame_needed = 0, uses_anonymous_args = 0 + 438 .loc 1 136 1 is_stmt 0 view .LVU90 + 439 0000 08B5 push {r3, lr} + 440 .LCFI7: + 441 .cfi_def_cfa_offset 8 + 442 .cfi_offset 3, -8 + 443 .cfi_offset 14, -4 + 137:Src/syscalls.c **** (void)name; + 444 .loc 1 137 3 is_stmt 1 view .LVU91 + 138:Src/syscalls.c **** errno = ENOENT; + 445 .loc 1 138 3 view .LVU92 + 446 0002 FFF7FEFF bl __errno + 447 .LVL31: + 448 .loc 1 138 9 is_stmt 0 discriminator 1 view .LVU93 + 449 0006 0223 movs r3, #2 + 450 0008 0360 str r3, [r0] + 139:Src/syscalls.c **** return -1; + 451 .loc 1 139 3 is_stmt 1 view .LVU94 + 140:Src/syscalls.c **** } + ARM GAS /tmp/ccEcvKCS.s page 11 + + + 452 .loc 1 140 1 is_stmt 0 view .LVU95 + 453 000a 4FF0FF30 mov r0, #-1 + 454 000e 08BD pop {r3, pc} + 455 .cfi_endproc + 456 .LFE37: + 458 .section .text._times,"ax",%progbits + 459 .align 1 + 460 .global _times + 461 .syntax unified + 462 .thumb + 463 .thumb_func + 465 _times: + 466 .LVL32: + 467 .LFB38: + 141:Src/syscalls.c **** + 142:Src/syscalls.c **** int _times(struct tms *buf) + 143:Src/syscalls.c **** { + 468 .loc 1 143 1 is_stmt 1 view -0 + 469 .cfi_startproc + 470 @ args = 0, pretend = 0, frame = 0 + 471 @ frame_needed = 0, uses_anonymous_args = 0 + 472 @ link register save eliminated. + 144:Src/syscalls.c **** (void)buf; + 473 .loc 1 144 3 view .LVU97 + 145:Src/syscalls.c **** return -1; + 474 .loc 1 145 3 view .LVU98 + 146:Src/syscalls.c **** } + 475 .loc 1 146 1 is_stmt 0 view .LVU99 + 476 0000 4FF0FF30 mov r0, #-1 + 477 .LVL33: + 478 .loc 1 146 1 view .LVU100 + 479 0004 7047 bx lr + 480 .cfi_endproc + 481 .LFE38: + 483 .section .text._stat,"ax",%progbits + 484 .align 1 + 485 .global _stat + 486 .syntax unified + 487 .thumb + 488 .thumb_func + 490 _stat: + 491 .LVL34: + 492 .LFB39: + 147:Src/syscalls.c **** + 148:Src/syscalls.c **** int _stat(char *file, struct stat *st) + 149:Src/syscalls.c **** { + 493 .loc 1 149 1 is_stmt 1 view -0 + 494 .cfi_startproc + 495 @ args = 0, pretend = 0, frame = 0 + 496 @ frame_needed = 0, uses_anonymous_args = 0 + 497 @ link register save eliminated. + 150:Src/syscalls.c **** (void)file; + 498 .loc 1 150 3 view .LVU102 + 151:Src/syscalls.c **** st->st_mode = S_IFCHR; + 499 .loc 1 151 3 view .LVU103 + 500 .loc 1 151 15 is_stmt 0 view .LVU104 + 501 0000 4FF40053 mov r3, #8192 + ARM GAS /tmp/ccEcvKCS.s page 12 + + + 502 0004 4B60 str r3, [r1, #4] + 152:Src/syscalls.c **** return 0; + 503 .loc 1 152 3 is_stmt 1 view .LVU105 + 153:Src/syscalls.c **** } + 504 .loc 1 153 1 is_stmt 0 view .LVU106 + 505 0006 0020 movs r0, #0 + 506 .LVL35: + 507 .loc 1 153 1 view .LVU107 + 508 0008 7047 bx lr + 509 .cfi_endproc + 510 .LFE39: + 512 .section .text._link,"ax",%progbits + 513 .align 1 + 514 .global _link + 515 .syntax unified + 516 .thumb + 517 .thumb_func + 519 _link: + 520 .LVL36: + 521 .LFB40: + 154:Src/syscalls.c **** + 155:Src/syscalls.c **** int _link(char *old, char *new) + 156:Src/syscalls.c **** { + 522 .loc 1 156 1 is_stmt 1 view -0 + 523 .cfi_startproc + 524 @ args = 0, pretend = 0, frame = 0 + 525 @ frame_needed = 0, uses_anonymous_args = 0 + 526 .loc 1 156 1 is_stmt 0 view .LVU109 + 527 0000 08B5 push {r3, lr} + 528 .LCFI8: + 529 .cfi_def_cfa_offset 8 + 530 .cfi_offset 3, -8 + 531 .cfi_offset 14, -4 + 157:Src/syscalls.c **** (void)old; + 532 .loc 1 157 3 is_stmt 1 view .LVU110 + 158:Src/syscalls.c **** (void)new; + 533 .loc 1 158 3 view .LVU111 + 159:Src/syscalls.c **** errno = EMLINK; + 534 .loc 1 159 3 view .LVU112 + 535 0002 FFF7FEFF bl __errno + 536 .LVL37: + 537 .loc 1 159 9 is_stmt 0 discriminator 1 view .LVU113 + 538 0006 1F23 movs r3, #31 + 539 0008 0360 str r3, [r0] + 160:Src/syscalls.c **** return -1; + 540 .loc 1 160 3 is_stmt 1 view .LVU114 + 161:Src/syscalls.c **** } + 541 .loc 1 161 1 is_stmt 0 view .LVU115 + 542 000a 4FF0FF30 mov r0, #-1 + 543 000e 08BD pop {r3, pc} + 544 .cfi_endproc + 545 .LFE40: + 547 .section .text._fork,"ax",%progbits + 548 .align 1 + 549 .global _fork + 550 .syntax unified + 551 .thumb + ARM GAS /tmp/ccEcvKCS.s page 13 + + + 552 .thumb_func + 554 _fork: + 555 .LFB41: + 162:Src/syscalls.c **** + 163:Src/syscalls.c **** int _fork(void) + 164:Src/syscalls.c **** { + 556 .loc 1 164 1 is_stmt 1 view -0 + 557 .cfi_startproc + 558 @ args = 0, pretend = 0, frame = 0 + 559 @ frame_needed = 0, uses_anonymous_args = 0 + 560 0000 08B5 push {r3, lr} + 561 .LCFI9: + 562 .cfi_def_cfa_offset 8 + 563 .cfi_offset 3, -8 + 564 .cfi_offset 14, -4 + 165:Src/syscalls.c **** errno = EAGAIN; + 565 .loc 1 165 3 view .LVU117 + 566 0002 FFF7FEFF bl __errno + 567 .LVL38: + 568 .loc 1 165 9 is_stmt 0 discriminator 1 view .LVU118 + 569 0006 0B23 movs r3, #11 + 570 0008 0360 str r3, [r0] + 166:Src/syscalls.c **** return -1; + 571 .loc 1 166 3 is_stmt 1 view .LVU119 + 167:Src/syscalls.c **** } + 572 .loc 1 167 1 is_stmt 0 view .LVU120 + 573 000a 4FF0FF30 mov r0, #-1 + 574 000e 08BD pop {r3, pc} + 575 .cfi_endproc + 576 .LFE41: + 578 .section .text._execve,"ax",%progbits + 579 .align 1 + 580 .global _execve + 581 .syntax unified + 582 .thumb + 583 .thumb_func + 585 _execve: + 586 .LVL39: + 587 .LFB42: + 168:Src/syscalls.c **** + 169:Src/syscalls.c **** int _execve(char *name, char **argv, char **env) + 170:Src/syscalls.c **** { + 588 .loc 1 170 1 is_stmt 1 view -0 + 589 .cfi_startproc + 590 @ args = 0, pretend = 0, frame = 0 + 591 @ frame_needed = 0, uses_anonymous_args = 0 + 592 .loc 1 170 1 is_stmt 0 view .LVU122 + 593 0000 08B5 push {r3, lr} + 594 .LCFI10: + 595 .cfi_def_cfa_offset 8 + 596 .cfi_offset 3, -8 + 597 .cfi_offset 14, -4 + 171:Src/syscalls.c **** (void)name; + 598 .loc 1 171 3 is_stmt 1 view .LVU123 + 172:Src/syscalls.c **** (void)argv; + 599 .loc 1 172 3 view .LVU124 + 173:Src/syscalls.c **** (void)env; + ARM GAS /tmp/ccEcvKCS.s page 14 + + + 600 .loc 1 173 3 view .LVU125 + 174:Src/syscalls.c **** errno = ENOMEM; + 601 .loc 1 174 3 view .LVU126 + 602 0002 FFF7FEFF bl __errno + 603 .LVL40: + 604 .loc 1 174 9 is_stmt 0 discriminator 1 view .LVU127 + 605 0006 0C23 movs r3, #12 + 606 0008 0360 str r3, [r0] + 175:Src/syscalls.c **** return -1; + 607 .loc 1 175 3 is_stmt 1 view .LVU128 + 176:Src/syscalls.c **** } + 608 .loc 1 176 1 is_stmt 0 view .LVU129 + 609 000a 4FF0FF30 mov r0, #-1 + 610 000e 08BD pop {r3, pc} + 611 .cfi_endproc + 612 .LFE42: + 614 .global environ + 615 .section .data.environ,"aw" + 616 .align 2 + 619 environ: + 620 0000 00000000 .word __env + 621 .global __env + 622 .section .bss.__env,"aw",%nobits + 623 .align 2 + 626 __env: + 627 0000 00000000 .space 4 + 628 .weak __io_putchar + 629 .weak __io_getchar + 630 .text + 631 .Letext0: + 632 .file 2 "/usr/include/newlib/machine/_default_types.h" + 633 .file 3 "/usr/include/newlib/sys/_types.h" + 634 .file 4 "/usr/include/newlib/sys/_timeval.h" + 635 .file 5 "/usr/include/newlib/sys/_timespec.h" + 636 .file 6 "/usr/include/newlib/sys/types.h" + 637 .file 7 "/usr/include/newlib/sys/stat.h" + 638 .file 8 "/usr/include/newlib/sys/times.h" + 639 .file 9 "/usr/include/newlib/sys/errno.h" + ARM GAS /tmp/ccEcvKCS.s page 15 + + +DEFINED SYMBOLS + *ABS*:00000000 syscalls.c + /tmp/ccEcvKCS.s:20 .text.initialise_monitor_handles:00000000 $t + /tmp/ccEcvKCS.s:26 .text.initialise_monitor_handles:00000000 initialise_monitor_handles + /tmp/ccEcvKCS.s:39 .text._getpid:00000000 $t + /tmp/ccEcvKCS.s:45 .text._getpid:00000000 _getpid + /tmp/ccEcvKCS.s:60 .text._kill:00000000 $t + /tmp/ccEcvKCS.s:66 .text._kill:00000000 _kill + /tmp/ccEcvKCS.s:95 .text._exit:00000000 $t + /tmp/ccEcvKCS.s:101 .text._exit:00000000 _exit + /tmp/ccEcvKCS.s:128 .text._read:00000000 $t + /tmp/ccEcvKCS.s:134 .text._read:00000000 _read + /tmp/ccEcvKCS.s:190 .text._write:00000000 $t + /tmp/ccEcvKCS.s:196 .text._write:00000000 _write + /tmp/ccEcvKCS.s:246 .text._close:00000000 $t + /tmp/ccEcvKCS.s:252 .text._close:00000000 _close + /tmp/ccEcvKCS.s:271 .text._fstat:00000000 $t + /tmp/ccEcvKCS.s:277 .text._fstat:00000000 _fstat + /tmp/ccEcvKCS.s:300 .text._isatty:00000000 $t + /tmp/ccEcvKCS.s:306 .text._isatty:00000000 _isatty + /tmp/ccEcvKCS.s:325 .text._lseek:00000000 $t + /tmp/ccEcvKCS.s:331 .text._lseek:00000000 _lseek + /tmp/ccEcvKCS.s:352 .text._open:00000000 $t + /tmp/ccEcvKCS.s:358 .text._open:00000000 _open + /tmp/ccEcvKCS.s:391 .text._wait:00000000 $t + /tmp/ccEcvKCS.s:397 .text._wait:00000000 _wait + /tmp/ccEcvKCS.s:425 .text._unlink:00000000 $t + /tmp/ccEcvKCS.s:431 .text._unlink:00000000 _unlink + /tmp/ccEcvKCS.s:459 .text._times:00000000 $t + /tmp/ccEcvKCS.s:465 .text._times:00000000 _times + /tmp/ccEcvKCS.s:484 .text._stat:00000000 $t + /tmp/ccEcvKCS.s:490 .text._stat:00000000 _stat + /tmp/ccEcvKCS.s:513 .text._link:00000000 $t + /tmp/ccEcvKCS.s:519 .text._link:00000000 _link + /tmp/ccEcvKCS.s:548 .text._fork:00000000 $t + /tmp/ccEcvKCS.s:554 .text._fork:00000000 _fork + /tmp/ccEcvKCS.s:579 .text._execve:00000000 $t + /tmp/ccEcvKCS.s:585 .text._execve:00000000 _execve + /tmp/ccEcvKCS.s:619 .data.environ:00000000 environ + /tmp/ccEcvKCS.s:616 .data.environ:00000000 $d + /tmp/ccEcvKCS.s:626 .bss.__env:00000000 __env + /tmp/ccEcvKCS.s:623 .bss.__env:00000000 $d + +UNDEFINED SYMBOLS +__errno +__io_getchar +__io_putchar diff --git a/build/syscalls.o b/build/syscalls.o new file mode 100644 index 0000000000000000000000000000000000000000..f6f1e5ff99089f4c3cf75939dd9a2f039ca59cbf GIT binary patch literal 14908 zcmd5@33OZ4nZ8f5me`6H$w{1DjvW$6EZbQ~$U+u}gph^XFl4^(zW+&251Y_) z=s9!ar|=vIT%6Gh!XexR?p?Oo@v2Vpq&;>PbU`S zCSBp60|lC)F7qqp(lM7AF}G3yAE*|4X0#AWe%~*^c9r?wCK%p_HTY`?F3$~6bGdx$ z(b`q!SqX5z#QNINNlMCm_mJ{?4uNvtM%FJT^a9GtJgIaZlCmpd$h{mcxF=L@pw>tl znPk={lMylNN6DXCbsAX{slT9ZHS2%F`XaNwn>wq^`r8zqTYD}6|CBpf{ax05?C?dc z<0%W6(JW)Ts~{~qDVPU%N1{Qsr`f*>a^E6wJT1dQ)NN3{9{@eAK051a@GG|;y53mr zwV>V0**H1kA6Q3kpFn-&!~H+px;ftvHtzw`7Qv*H@wlP=$MsQMscELZyOq;g~VMOs?zn?&-Y z&_qqv`7R+jO~|Rfv)OjKkaKaxoHU9sl-Yi7q50=MuTjjeBJby^YGT(Hx@Yf3I_kBcigpdK{_oCHs z7|@oLsyL4wO!3jM;Q=44YO<#KXMz%zr;N=4#?#bl2p9v@SP%Jd)>Ngj4`QQH1eL}* zb`TnFWVDGgDpeVC@M|3K=*FljcEe))4qDaBqH!R^ej33HLBcqXHhH`!!=X(#(2G0MtH6;Gn#ZKaA&Q1L7%*7WssLRv#_-U9P= z95w00cJRiLSB-@5|(F#MOm4ByK9sNlN>sU`huLB1fa-LKfry_o1cd;R}dku}%c&zO1*4cdk z%=>T@eXlZ3qT)blS#=!v7^|Sfj6+px7fIbe(lhaZvb;G zjuB7l7GnpX=(-_45@An3)yNcWAVMAX>olR0m#L=u*U|h!9JQHz77fObXRNF3Op$8P z)OwiP4i)44&zq}7I!$xu*HHNY^zOoeCOhzJ#EVU=;oDef64xHQ0QKi_=;4bu$nb@X zh2R;Ri|ws}+g)hCS+_q1y-#pp$j)b%?PHArAj>!$Coo+K3ynTvm~$)s=!&#oE(vlYxH95uOA7kG8#Z3evwNAWZmYrN02wG<7)2R#eN z84sgoOy`*Dtpm?UoLR=?%20*7a%|;U-Wp@QQ4P7PQB_o&3MMXCBbB>yUd8;1Qz}-5 zaCsF8eDhR6i9Bz}a937Tm`Vm1zTvhua}mGaFjj^r8CI`WhMFssDn}c?y-md|Tbo4z z7g_}(#-f1L`INxQ(1HMMAUW){GNPPPq|@1?#t0gVy??({x2*Qq`fzz4S&C4xu(+`ByOyJaz4jxZV4^6MW>HwH0q=kSH_`$4xG)Kl+7$Jf+106b8HlvqNB``NbwM05U4Ul zEQLE(Q+=H|bJ%httGt@HRo>Xk3eA9z-;!dsTu(4HxEI%jmmw?dF4eNPsB)HQXt2+X zFgVAFhAKlu1BqFN0}Qo}z{J37LM;xry1>}WN*D)J@LN)B(S#u|)E7o$stg$oFS>|^ z6QHCF1BJ06P-UoS?1`cOgPHnj*OKq(Uht#mKastfg=YkdHPh%hOIZJ!gU>2QoQ0WW zvD#T^@hv+RI@?)%Cz@9OfBKcely|Eq;G)a;q;j~z6CrHkFxJ>0X5*^4KbLJzrQ<#Q zorz}L;q;_BntNmM?o>K4s4TZLrxbqTv7Vk>Bu+cg&O|cS-;S4P)G04 ze5yCGE!G2xMddPyxJg=VAj#!pd10af4S|`+X48FURe22M(L?W^ZiHOefEh(j3+_}y z9>W{LJ)@mJ+wel-tq+Af!|+VT@J2v2Yejd7;zChe<*770!wiS{r<5sP7^?MD(_+}; z@lNtoqN>eCJONq{d!_;0-s#fWB+q!==>(5^Ci{$(bouCHn(a(%Q}Ld@_||A%;bBE8+m}}TsZLPQ zo?IfaRYm)fNl=-HY}U6^1Co)b7RqH*Y{Xp|2> zpqzqadp4C%P{jVCNv)Vn^}yKHR8NnhT^Pu9_hs{8K5mRg@f+<)#B%wQXHk-mNVRo?d?OoFB|QSr8|2PIn~pb?h5N4+CZBw+*L)P)=BHBbRT|oAUQJ-{^p>N z?n$MYfc`XYxzdTwaJ)N~Rp}Ulg})F)x5p4gb9Y~FqB)u9j5V)W*}k!PeXKLp*WTTi zha2(ehW?IRBAblG6VYs}GnQ>$kw_=9G5Xiuw$z~vPBhn-%x{ln6Q9_wt=z&?2j>~`oyx`X`JFW0tBo^a zSmel<0|N=>AQd>X%>0xXr6hyY%`#Jz={HlfES8V0?A!rnKN2u=2Hi~dWw$DG4l|X! z&yI2yQYLd7Gb@hSmRFfrzFW^luK3ytBeiBV^QoPb)1Y56$$XjZG39vyKua@6E6zMC z+}1iL+&VKdBhnh4(K2IZYfH;1;ilerrhj1^lRdGcsdo-Ki9|GE zvgA{J=^W@}e_GcIJUkd_YnvCI+B$olb}pOfX>FQuqSI4cdbvwEhJstuiz@@eH4T<7 zyu4Yv7&5p+;nvV9+<7di^k3$>)+ph#jm77EvsJ>VEUB!%yzC11H`&H6#r>+K?{Ubv<1Q9A_PeF+t$nPi<5qr$y!39sjeT-yduxAe zwGTMtrP^-Xqm^=at5z&-RppRZ6@{p|v7aw(Z|%2DHMgp9$ZH(!gAO?#eHM#bg&cA` zDzX)~8sU(Suu19PD2IHMLtf{Q+s`_-AMKEjcC;VskdJl9$2;WX9rB6Du)R#Q6X?I* zA+LAHCpqXw2R+$A^Qq&%pypQ79CVX|Zg$WS2i>YTf;@}3J_d1q&;n_$LqR;f znk_VEN)YpZKF})Uwc(&X=T#8%f2Gi2;3Uja~p-ulo>edo^gxV*x+21I2Pf7ba^@9@q z(dwZRdaU|s2|Zpt37Uoe)u@T;IZat~eaS6eV_r3Oe$gheunW*T&%!0!+^2qi+a+69 zy%n?e8M610eXO;gDQuXzvod##QEQJNJ59Zni0aLhxiPW!($?17+%$9El+TlAKc|>a z0?HSfPm{_Qne&QrOK&J-np|s4J1$I9&L`JQ=Fmj06r_1ZyKr6Mnc|wE)O6uPq~+*J z;}XHs1vwAdo{xBlUlU9Ta^8{OFL;&Ub%Odc1IX_d`a!{e7W`Mi{}end_@3Y=f>oH@ z?59>REZ8KtKybC-Cc#d@jNrwB{L+E;_->wfr{MPme=PX4;32`+1m6?%rq1P-pQ?N~tFa0QAO+>qMh_DkU)+^N|m>2#fMCe~8c!%&05OF!W zPw?j=e^&6qCr_j3uFBSexf_D#pi+rEZcM0B0g#NQ4 zf02lX=PwDqLPYyN3jRsZi>)^K<$_g2v>QW&pC=HZdy?QR;m;>xZY&bSGOf>hoCX^8 zb!dwDB%JF(qwuE+qD!rZE;Ozc+#q3ZZtaJk?af=MFQnezoN5bPJ^ zmoZ!~ZVD_lR^ZWGG|^>q>a6G&HK-U`kTJXw%muuy)c;8}wFfRTKD%|hHIsIQlx_4N{X zo$zlIyj}24L4Ntd_KyhuOz=rTeg#AMOMB|Z*9)F4__u;F!Se;vg8YDn_OB4UTJUH zTurh*fyX;yu5)1`^z}LgzgkEm4|9nauf;^nuhWT`kL^Uv<4r`&_bo)67u`ghUwVIx z^L7Vmoc{yFddwqYgHqQMCo6Re5$hTY*HxrJqn`-B^m+=cCJq1i?1)%LgrB@GB!-Fb zw^48^5q|6aKCp!}{GTN_mxwqP2recfo@Iik6A>4-lp5QKh;O6dCL-eG{V8z^5%G2k zb`ueIk6?y~`1680h{(gmf&)b4<8r|(iO9>p*5znJS zKTbqk|0cA~6XJVW=+}sd^HZS}^MQEv^$h*jkw)CpiJ{Nh6HGSWgm|w21jQ!4xJs`n&L^CE16p>UylBBa63jHYwiE z*vVKnmhQp}GMmQdIdCvxS;W|>NW8DNH-XnrwpPh3U!_HstX~tso1bi|qdyO`U%p@} za!TswS8RnTRZ?*J=~9nh>f!X$#i>Ub3#XnR$MN*0L&w>#)fYti`3rFk4!hpTpvx$b zVzr5aw(Ie^O0}f~wDi7)I+g>q7zazB-t-rbW^@i{oBsFVu-iKWbO47{EPGqQu-mJ( z*`poH-X*Bp?eV!z7>89Xdl!LWw>QpakIxh>d)J|Ex3>-SI2=~7?EM`Wc6*IBdyL1j zcRT8Kd*1@hYqeD@dk4U<>)isHep$uRdl(G6-amq7Uskd7o(99N_g&C~=^b+D-3xlK zeqVR!Jp_8NdGHGO_Pk85FU|uj?}fa4;IK!32ebDFhrL-gd$>Fl>>YF1dja%dc@7{c z_$$bMi~3;kj&ta}3BAGm<8{U!?}GYbytq6S{Nr^9e}#UJ3}J7o!`?ERJ+3JnL(YF* z$L#jXKn&*JT=4Dwt*$Tnhs$HZ-kH$DUtxXWb<{pztUB-i?DjU+7wzHlTClendiM2- zd9rLktx(?zKK=@YdZ)9Y6ie2HioM^>^-2w3fVsX*!eQlQJM^qJG_eJZ4%--3b&o@@ z4SSc%u-~zYrFR7?_I_W+LVQ0uW53uQ6#BizVec6X#yyrXpk + 25:Src/sysmem.c **** #include + 26:Src/sysmem.c **** + 27:Src/sysmem.c **** /** + 28:Src/sysmem.c **** * Pointer to the current high watermark of the heap usage + 29:Src/sysmem.c **** */ + 30:Src/sysmem.c **** static uint8_t *__sbrk_heap_end = NULL; + ARM GAS /tmp/ccTZCPY8.s page 2 + + + 31:Src/sysmem.c **** + 32:Src/sysmem.c **** /** + 33:Src/sysmem.c **** * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + 34:Src/sysmem.c **** * and others from the C library + 35:Src/sysmem.c **** * + 36:Src/sysmem.c **** * @verbatim + 37:Src/sysmem.c **** * ############################################################################ + 38:Src/sysmem.c **** * # .data # .bss # newlib heap # MSP stack # + 39:Src/sysmem.c **** * # # # # Reserved by _Min_Stack_Size # + 40:Src/sysmem.c **** * ############################################################################ + 41:Src/sysmem.c **** * ^-- RAM start ^-- _end _estack, RAM end --^ + 42:Src/sysmem.c **** * @endverbatim + 43:Src/sysmem.c **** * + 44:Src/sysmem.c **** * This implementation starts allocating at the '_end' linker symbol + 45:Src/sysmem.c **** * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + 46:Src/sysmem.c **** * The implementation considers '_estack' linker symbol to be RAM end + 47:Src/sysmem.c **** * NOTE: If the MSP stack, at any point during execution, grows larger than the + 48:Src/sysmem.c **** * reserved size, please increase the '_Min_Stack_Size'. + 49:Src/sysmem.c **** * + 50:Src/sysmem.c **** * @param incr Memory size + 51:Src/sysmem.c **** * @return Pointer to allocated memory + 52:Src/sysmem.c **** */ + 53:Src/sysmem.c **** void *_sbrk(ptrdiff_t incr) + 54:Src/sysmem.c **** { + 29 .loc 1 54 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 .loc 1 54 1 is_stmt 0 view .LVU1 + 34 0000 10B5 push {r4, lr} + 35 .LCFI0: + 36 .cfi_def_cfa_offset 8 + 37 .cfi_offset 4, -8 + 38 .cfi_offset 14, -4 + 39 0002 0346 mov r3, r0 + 55:Src/sysmem.c **** extern uint8_t _end; /* Symbol defined in the linker script */ + 40 .loc 1 55 3 is_stmt 1 view .LVU2 + 56:Src/sysmem.c **** extern uint8_t _estack; /* Symbol defined in the linker script */ + 41 .loc 1 56 3 view .LVU3 + 57:Src/sysmem.c **** extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + 42 .loc 1 57 3 view .LVU4 + 58:Src/sysmem.c **** const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + 43 .loc 1 58 3 view .LVU5 + 44 .LVL1: + 59:Src/sysmem.c **** const uint8_t *max_heap = (uint8_t *)stack_limit; + 45 .loc 1 59 3 view .LVU6 + 58:Src/sysmem.c **** const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + 46 .loc 1 58 51 is_stmt 0 view .LVU7 + 47 0004 0C4A ldr r2, .L8 + 48 0006 0D49 ldr r1, .L8+4 + 49 .LVL2: + 60:Src/sysmem.c **** uint8_t *prev_heap_end; + 50 .loc 1 60 3 is_stmt 1 view .LVU8 + 61:Src/sysmem.c **** + 62:Src/sysmem.c **** /* Initialize heap end at first call */ + 63:Src/sysmem.c **** if (NULL == __sbrk_heap_end) + 51 .loc 1 63 3 view .LVU9 + ARM GAS /tmp/ccTZCPY8.s page 3 + + + 52 .loc 1 63 12 is_stmt 0 view .LVU10 + 53 0008 0D48 ldr r0, .L8+8 + 54 .LVL3: + 55 .loc 1 63 12 view .LVU11 + 56 000a 0068 ldr r0, [r0] + 57 .loc 1 63 6 view .LVU12 + 58 000c 40B1 cbz r0, .L6 + 59 .L2: + 64:Src/sysmem.c **** { + 65:Src/sysmem.c **** __sbrk_heap_end = &_end; + 66:Src/sysmem.c **** } + 67:Src/sysmem.c **** + 68:Src/sysmem.c **** /* Protect heap from growing into the reserved MSP stack */ + 69:Src/sysmem.c **** if (__sbrk_heap_end + incr > max_heap) + 60 .loc 1 69 3 is_stmt 1 view .LVU13 + 61 .loc 1 69 23 is_stmt 0 view .LVU14 + 62 000e 0C48 ldr r0, .L8+8 + 63 0010 0068 ldr r0, [r0] + 64 0012 0344 add r3, r3, r0 + 65 .LVL4: + 66 .loc 1 69 6 view .LVU15 + 67 0014 521A subs r2, r2, r1 + 68 0016 9342 cmp r3, r2 + 69 0018 06D8 bhi .L7 + 70:Src/sysmem.c **** { + 71:Src/sysmem.c **** errno = ENOMEM; + 72:Src/sysmem.c **** return (void *)-1; + 73:Src/sysmem.c **** } + 74:Src/sysmem.c **** + 75:Src/sysmem.c **** prev_heap_end = __sbrk_heap_end; + 70 .loc 1 75 3 is_stmt 1 view .LVU16 + 71 .LVL5: + 76:Src/sysmem.c **** __sbrk_heap_end += incr; + 72 .loc 1 76 3 view .LVU17 + 73 .loc 1 76 19 is_stmt 0 view .LVU18 + 74 001a 094A ldr r2, .L8+8 + 75 001c 1360 str r3, [r2] + 77:Src/sysmem.c **** + 78:Src/sysmem.c **** return (void *)prev_heap_end; + 76 .loc 1 78 3 is_stmt 1 view .LVU19 + 77 .LVL6: + 78 .L1: + 79:Src/sysmem.c **** } + 79 .loc 1 79 1 is_stmt 0 view .LVU20 + 80 001e 10BD pop {r4, pc} + 81 .LVL7: + 82 .L6: + 65:Src/sysmem.c **** } + 83 .loc 1 65 5 is_stmt 1 view .LVU21 + 65:Src/sysmem.c **** } + 84 .loc 1 65 21 is_stmt 0 view .LVU22 + 85 0020 0748 ldr r0, .L8+8 + 86 0022 084C ldr r4, .L8+12 + 87 0024 0460 str r4, [r0] + 88 0026 F2E7 b .L2 + 89 .LVL8: + 90 .L7: + ARM GAS /tmp/ccTZCPY8.s page 4 + + + 71:Src/sysmem.c **** return (void *)-1; + 91 .loc 1 71 5 is_stmt 1 view .LVU23 + 92 0028 FFF7FEFF bl __errno + 93 .LVL9: + 71:Src/sysmem.c **** return (void *)-1; + 94 .loc 1 71 11 is_stmt 0 discriminator 1 view .LVU24 + 95 002c 0C23 movs r3, #12 + 96 002e 0360 str r3, [r0] + 72:Src/sysmem.c **** } + 97 .loc 1 72 5 is_stmt 1 view .LVU25 + 72:Src/sysmem.c **** } + 98 .loc 1 72 12 is_stmt 0 view .LVU26 + 99 0030 4FF0FF30 mov r0, #-1 + 100 0034 F3E7 b .L1 + 101 .L9: + 102 0036 00BF .align 2 + 103 .L8: + 104 0038 00000000 .word _estack + 105 003c 00000000 .word _Min_Stack_Size + 106 0040 00000000 .word __sbrk_heap_end + 107 0044 00000000 .word _end + 108 .cfi_endproc + 109 .LFE0: + 111 .section .bss.__sbrk_heap_end,"aw",%nobits + 112 .align 2 + 115 __sbrk_heap_end: + 116 0000 00000000 .space 4 + 117 .text + 118 .Letext0: + 119 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stddef.h" + 120 .file 3 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 121 .file 4 "/usr/include/newlib/sys/errno.h" + ARM GAS /tmp/ccTZCPY8.s page 5 + + +DEFINED SYMBOLS + *ABS*:00000000 sysmem.c + /tmp/ccTZCPY8.s:20 .text._sbrk:00000000 $t + /tmp/ccTZCPY8.s:26 .text._sbrk:00000000 _sbrk + /tmp/ccTZCPY8.s:104 .text._sbrk:00000038 $d + /tmp/ccTZCPY8.s:115 .bss.__sbrk_heap_end:00000000 __sbrk_heap_end + /tmp/ccTZCPY8.s:112 .bss.__sbrk_heap_end:00000000 $d + +UNDEFINED SYMBOLS +__errno +_estack +_Min_Stack_Size +_end diff --git a/build/sysmem.o b/build/sysmem.o new file mode 100644 index 0000000000000000000000000000000000000000..d7e21ef65bb4909cebdd72ac26165a3f1df09ecb GIT binary patch literal 4132 zcma)8TZ|i589rymGxqMXbjdaXsSlH}JziT` zUo;*kEfgpb5}+c~s;Y_vRgsVi5)uL-!~^2;f+{W#sN$g#h$p00f`>qhQUPN5zTrig3MQGw48sD zS?N4k%K4>&^v3~C%95GyKuNuTm+kHM0q*lO{G5gp2R=o^*YQe!4=;IWoTG4TyhJ9& zz!CW?WKR`x@^@e|lVX2HS*8GXto3!Kd|NiJ!^ zc$3r`wA%HhJ5r3xStM1$?PXy$h+G2b7}*C2hJcN~N|;pY8li}1RJ?2dT^zkPb5FcR zK8;6;H3Cy6-JnXOoB|%ggOmf45C@^KADCJ7=8FlElH~8fVT&)~ZOMP;b69zGPPzDN zQB{=ty{Np=td!TQ)p8KEO6^WNEQLX(S)QHu=DgW*vt8Zj*TO-hCgpZ`n~i$U^n}2x z6}G%8dMSEwtrph32D=CyCv2dHQPl20<(7A(aMTFw1?fu1cFP5bGw+T=pV{MNU0HP8 zBFGVE9|GJZsLKVXpn_){=@uNvwWFf52NuU&b;fWYrRza2v$d7QC^tIo^`d(5nD-i; zC@%Kfz2>vcaCD&vkO+l6+R z{gr0hUt5^ZFMsrU@xtt4aj@vcxtY27*_oMB#Zs%_em*oggk@-<-j?YA^&*wQ&YJ>egadYJH^M^=jQ>X&t{Bs@6+$#nKaC^;!@IrCwN# zo1JzKyxwmseaj|%U+o^D*KROdoUFlO)H?mjMu^?UsorR|nr5{*XV~K0q=Wq_E?>BC zx;Q<%a9WKr3O8m;b4Q1V%!9E5gmCS4OPS%tUHZ?veZK{qlgEk_Y7>`5_#UVM&@&;;)-Yzs)n15L+L8W3ttO zGK>d3g_|TPDUky`xn)X;-CF1MAqDQpgxKJW-q*x5)5uA6)RGdk1rG?Gs`N`K|pzoFih|_@8SXz+WK|8;*O<8W#dT zg?lt2L|D6ocz}ow9@qAHjb}Bg4;eImQuC)YRx~y>b~WDC_!*5~(D-GIuWJ0R#vc>W z?>996gT{A=_;C7*#=AspqJL;Vu6xBtH0Fuu=RuA9Vj(}N@uJ36jZYDg&(~NZst>gR zavzhc`2%td$&YE|`jancJf-oRMzs#`t9b){Lfd_fRgL@@VxG@wRO^OM8B-5tY)13}S}s z@(wY=b)@jT@s>M>hcXE=4aAXFpJ0q*J)ZAm-DkBQpv2_64rcmF2jk*|!KfdDJy~}N zglB|xc?+Am0d&&_s^EA1pQ&guKCXz->H0k;_5~e7Fuo4-WZf87`g5?cE^l{J_YQQ^ z2CBG;2`^I7Vtl+`lKI|45}q064hb7Sq4Cpks(#fRgu-Z_W^)sYOh5TO7w``UZ@= jpZK4{d>l7xBHxz$29t7Wi*4t_)x9I`IQsX_2gLmc{09BR literal 0 HcmV?d00001 diff --git a/build/system_stm32f7xx.d b/build/system_stm32f7xx.d new file mode 100644 index 0000000..edacd03 --- /dev/null +++ b/build/system_stm32f7xx.d @@ -0,0 +1,67 @@ +build/system_stm32f7xx.o: Src/system_stm32f7xx.c \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h \ + Drivers/CMSIS/Include/core_cm7.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h \ + Inc/stm32f7xx_hal_conf.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h \ + Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h: +Drivers/CMSIS/Include/core_cm7.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h: +Inc/stm32f7xx_hal_conf.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h: +Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h: +Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h: diff --git a/build/system_stm32f7xx.lst b/build/system_stm32f7xx.lst new file mode 100644 index 0000000..5931984 --- /dev/null +++ b/build/system_stm32f7xx.lst @@ -0,0 +1,569 @@ +ARM GAS /tmp/ccZPj2qA.s page 1 + + + 1 .cpu cortex-m7 + 2 .arch armv7e-m + 3 .fpu fpv5-d16 + 4 .eabi_attribute 28, 1 + 5 .eabi_attribute 20, 1 + 6 .eabi_attribute 21, 1 + 7 .eabi_attribute 23, 3 + 8 .eabi_attribute 24, 1 + 9 .eabi_attribute 25, 1 + 10 .eabi_attribute 26, 1 + 11 .eabi_attribute 30, 1 + 12 .eabi_attribute 34, 1 + 13 .eabi_attribute 18, 4 + 14 .file "system_stm32f7xx.c" + 15 .text + 16 .Ltext0: + 17 .cfi_sections .debug_frame + 18 .file 1 "Src/system_stm32f7xx.c" + 19 .section .text.SystemInit,"ax",%progbits + 20 .align 1 + 21 .global SystemInit + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 SystemInit: + 27 .LFB141: + 1:Src/system_stm32f7xx.c **** /** + 2:Src/system_stm32f7xx.c **** ****************************************************************************** + 3:Src/system_stm32f7xx.c **** * @file system_stm32f7xx.c + 4:Src/system_stm32f7xx.c **** * @author MCD Application Team + 5:Src/system_stm32f7xx.c **** * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. + 6:Src/system_stm32f7xx.c **** * + 7:Src/system_stm32f7xx.c **** * This file provides two functions and one global variable to be called from + 8:Src/system_stm32f7xx.c **** * user application: + 9:Src/system_stm32f7xx.c **** * - SystemInit(): This function is called at startup just after reset and + 10:Src/system_stm32f7xx.c **** * before branch to main program. This call is made inside + 11:Src/system_stm32f7xx.c **** * the "startup_stm32f7xx.s" file. + 12:Src/system_stm32f7xx.c **** * + 13:Src/system_stm32f7xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + 14:Src/system_stm32f7xx.c **** * by the user application to setup the SysTick + 15:Src/system_stm32f7xx.c **** * timer or configure other parameters. + 16:Src/system_stm32f7xx.c **** * + 17:Src/system_stm32f7xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + 18:Src/system_stm32f7xx.c **** * be called whenever the core clock is changed + 19:Src/system_stm32f7xx.c **** * during program execution. + 20:Src/system_stm32f7xx.c **** * + 21:Src/system_stm32f7xx.c **** * + 22:Src/system_stm32f7xx.c **** ****************************************************************************** + 23:Src/system_stm32f7xx.c **** * @attention + 24:Src/system_stm32f7xx.c **** * + 25:Src/system_stm32f7xx.c **** * Copyright (c) 2016 STMicroelectronics. + 26:Src/system_stm32f7xx.c **** * All rights reserved. + 27:Src/system_stm32f7xx.c **** * + 28:Src/system_stm32f7xx.c **** * This software is licensed under terms that can be found in the LICENSE file + 29:Src/system_stm32f7xx.c **** * in the root directory of this software component. + 30:Src/system_stm32f7xx.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 31:Src/system_stm32f7xx.c **** * + ARM GAS /tmp/ccZPj2qA.s page 2 + + + 32:Src/system_stm32f7xx.c **** ****************************************************************************** + 33:Src/system_stm32f7xx.c **** */ + 34:Src/system_stm32f7xx.c **** + 35:Src/system_stm32f7xx.c **** /** @addtogroup CMSIS + 36:Src/system_stm32f7xx.c **** * @{ + 37:Src/system_stm32f7xx.c **** */ + 38:Src/system_stm32f7xx.c **** + 39:Src/system_stm32f7xx.c **** /** @addtogroup stm32f7xx_system + 40:Src/system_stm32f7xx.c **** * @{ + 41:Src/system_stm32f7xx.c **** */ + 42:Src/system_stm32f7xx.c **** + 43:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_Includes + 44:Src/system_stm32f7xx.c **** * @{ + 45:Src/system_stm32f7xx.c **** */ + 46:Src/system_stm32f7xx.c **** + 47:Src/system_stm32f7xx.c **** #include "stm32f7xx.h" + 48:Src/system_stm32f7xx.c **** + 49:Src/system_stm32f7xx.c **** #if !defined (HSE_VALUE) + 50:Src/system_stm32f7xx.c **** #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ + 51:Src/system_stm32f7xx.c **** #endif /* HSE_VALUE */ + 52:Src/system_stm32f7xx.c **** + 53:Src/system_stm32f7xx.c **** #if !defined (HSI_VALUE) + 54:Src/system_stm32f7xx.c **** #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ + 55:Src/system_stm32f7xx.c **** #endif /* HSI_VALUE */ + 56:Src/system_stm32f7xx.c **** + 57:Src/system_stm32f7xx.c **** /** + 58:Src/system_stm32f7xx.c **** * @} + 59:Src/system_stm32f7xx.c **** */ + 60:Src/system_stm32f7xx.c **** + 61:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_TypesDefinitions + 62:Src/system_stm32f7xx.c **** * @{ + 63:Src/system_stm32f7xx.c **** */ + 64:Src/system_stm32f7xx.c **** + 65:Src/system_stm32f7xx.c **** /** + 66:Src/system_stm32f7xx.c **** * @} + 67:Src/system_stm32f7xx.c **** */ + 68:Src/system_stm32f7xx.c **** + 69:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_Defines + 70:Src/system_stm32f7xx.c **** * @{ + 71:Src/system_stm32f7xx.c **** */ + 72:Src/system_stm32f7xx.c **** + 73:Src/system_stm32f7xx.c **** /************************* Miscellaneous Configuration ************************/ + 74:Src/system_stm32f7xx.c **** + 75:Src/system_stm32f7xx.c **** /* Note: Following vector table addresses must be defined in line with linker + 76:Src/system_stm32f7xx.c **** configuration. */ + 77:Src/system_stm32f7xx.c **** /*!< Uncomment the following line if you need to relocate the vector table + 78:Src/system_stm32f7xx.c **** anywhere in Flash or Sram, else the vector table is kept at the automatic + 79:Src/system_stm32f7xx.c **** remap of boot address selected */ + 80:Src/system_stm32f7xx.c **** /* #define USER_VECT_TAB_ADDRESS */ + 81:Src/system_stm32f7xx.c **** + 82:Src/system_stm32f7xx.c **** #if defined(USER_VECT_TAB_ADDRESS) + 83:Src/system_stm32f7xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table + 84:Src/system_stm32f7xx.c **** in Sram else user remap will be done in Flash. */ + 85:Src/system_stm32f7xx.c **** /* #define VECT_TAB_SRAM */ + 86:Src/system_stm32f7xx.c **** #if defined(VECT_TAB_SRAM) + 87:Src/system_stm32f7xx.c **** #define VECT_TAB_BASE_ADDRESS RAMDTCM_BASE /*!< Vector Table base address field. + 88:Src/system_stm32f7xx.c **** This value must be a multiple of 0x200. */ + ARM GAS /tmp/ccZPj2qA.s page 3 + + + 89:Src/system_stm32f7xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + 90:Src/system_stm32f7xx.c **** This value must be a multiple of 0x200. */ + 91:Src/system_stm32f7xx.c **** #else + 92:Src/system_stm32f7xx.c **** #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + 93:Src/system_stm32f7xx.c **** This value must be a multiple of 0x200. */ + 94:Src/system_stm32f7xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + 95:Src/system_stm32f7xx.c **** This value must be a multiple of 0x200. */ + 96:Src/system_stm32f7xx.c **** #endif /* VECT_TAB_SRAM */ + 97:Src/system_stm32f7xx.c **** #endif /* USER_VECT_TAB_ADDRESS */ + 98:Src/system_stm32f7xx.c **** /******************************************************************************/ + 99:Src/system_stm32f7xx.c **** + 100:Src/system_stm32f7xx.c **** /** + 101:Src/system_stm32f7xx.c **** * @} + 102:Src/system_stm32f7xx.c **** */ + 103:Src/system_stm32f7xx.c **** + 104:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_Macros + 105:Src/system_stm32f7xx.c **** * @{ + 106:Src/system_stm32f7xx.c **** */ + 107:Src/system_stm32f7xx.c **** + 108:Src/system_stm32f7xx.c **** /** + 109:Src/system_stm32f7xx.c **** * @} + 110:Src/system_stm32f7xx.c **** */ + 111:Src/system_stm32f7xx.c **** + 112:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_Variables + 113:Src/system_stm32f7xx.c **** * @{ + 114:Src/system_stm32f7xx.c **** */ + 115:Src/system_stm32f7xx.c **** + 116:Src/system_stm32f7xx.c **** /* This variable is updated in three ways: + 117:Src/system_stm32f7xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate() + 118:Src/system_stm32f7xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 119:Src/system_stm32f7xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + 120:Src/system_stm32f7xx.c **** Note: If you use this function to configure the system clock; then there + 121:Src/system_stm32f7xx.c **** is no need to call the 2 first functions listed above, since SystemCoreClock + 122:Src/system_stm32f7xx.c **** variable is updated automatically. + 123:Src/system_stm32f7xx.c **** */ + 124:Src/system_stm32f7xx.c **** uint32_t SystemCoreClock = 16000000; + 125:Src/system_stm32f7xx.c **** const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + 126:Src/system_stm32f7xx.c **** const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + 127:Src/system_stm32f7xx.c **** + 128:Src/system_stm32f7xx.c **** /** + 129:Src/system_stm32f7xx.c **** * @} + 130:Src/system_stm32f7xx.c **** */ + 131:Src/system_stm32f7xx.c **** + 132:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_FunctionPrototypes + 133:Src/system_stm32f7xx.c **** * @{ + 134:Src/system_stm32f7xx.c **** */ + 135:Src/system_stm32f7xx.c **** + 136:Src/system_stm32f7xx.c **** /** + 137:Src/system_stm32f7xx.c **** * @} + 138:Src/system_stm32f7xx.c **** */ + 139:Src/system_stm32f7xx.c **** + 140:Src/system_stm32f7xx.c **** /** @addtogroup STM32F7xx_System_Private_Functions + 141:Src/system_stm32f7xx.c **** * @{ + 142:Src/system_stm32f7xx.c **** */ + 143:Src/system_stm32f7xx.c **** + 144:Src/system_stm32f7xx.c **** /** + 145:Src/system_stm32f7xx.c **** * @brief Setup the microcontroller system + ARM GAS /tmp/ccZPj2qA.s page 4 + + + 146:Src/system_stm32f7xx.c **** * Initialize the Embedded Flash Interface, the PLL and update the + 147:Src/system_stm32f7xx.c **** * SystemFrequency variable. + 148:Src/system_stm32f7xx.c **** * @param None + 149:Src/system_stm32f7xx.c **** * @retval None + 150:Src/system_stm32f7xx.c **** */ + 151:Src/system_stm32f7xx.c **** void SystemInit(void) + 152:Src/system_stm32f7xx.c **** { + 28 .loc 1 152 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 153:Src/system_stm32f7xx.c **** /* FPU settings ------------------------------------------------------------*/ + 154:Src/system_stm32f7xx.c **** #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + 155:Src/system_stm32f7xx.c **** SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + 33 .loc 1 155 3 view .LVU1 + 34 .loc 1 155 6 is_stmt 0 view .LVU2 + 35 0000 034A ldr r2, .L2 + 36 0002 D2F88830 ldr r3, [r2, #136] + 37 .loc 1 155 14 view .LVU3 + 38 0006 43F47003 orr r3, r3, #15728640 + 39 000a C2F88830 str r3, [r2, #136] + 156:Src/system_stm32f7xx.c **** #endif + 157:Src/system_stm32f7xx.c **** + 158:Src/system_stm32f7xx.c **** /* Configure the Vector Table location -------------------------------------*/ + 159:Src/system_stm32f7xx.c **** #if defined(USER_VECT_TAB_ADDRESS) + 160:Src/system_stm32f7xx.c **** SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM + 161:Src/system_stm32f7xx.c **** #endif /* USER_VECT_TAB_ADDRESS */ + 162:Src/system_stm32f7xx.c **** } + 40 .loc 1 162 1 view .LVU4 + 41 000e 7047 bx lr + 42 .L3: + 43 .align 2 + 44 .L2: + 45 0010 00ED00E0 .word -536810240 + 46 .cfi_endproc + 47 .LFE141: + 49 .section .text.SystemCoreClockUpdate,"ax",%progbits + 50 .align 1 + 51 .global SystemCoreClockUpdate + 52 .syntax unified + 53 .thumb + 54 .thumb_func + 56 SystemCoreClockUpdate: + 57 .LFB142: + 163:Src/system_stm32f7xx.c **** + 164:Src/system_stm32f7xx.c **** /** + 165:Src/system_stm32f7xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values. + 166:Src/system_stm32f7xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can + 167:Src/system_stm32f7xx.c **** * be used by the user application to setup the SysTick timer or configure + 168:Src/system_stm32f7xx.c **** * other parameters. + 169:Src/system_stm32f7xx.c **** * + 170:Src/system_stm32f7xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called + 171:Src/system_stm32f7xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration + 172:Src/system_stm32f7xx.c **** * based on this variable will be incorrect. + 173:Src/system_stm32f7xx.c **** * + 174:Src/system_stm32f7xx.c **** * @note - The system frequency computed by this function is not the real + ARM GAS /tmp/ccZPj2qA.s page 5 + + + 175:Src/system_stm32f7xx.c **** * frequency in the chip. It is calculated based on the predefined + 176:Src/system_stm32f7xx.c **** * constant and the selected clock source: + 177:Src/system_stm32f7xx.c **** * + 178:Src/system_stm32f7xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + 179:Src/system_stm32f7xx.c **** * + 180:Src/system_stm32f7xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + 181:Src/system_stm32f7xx.c **** * + 182:Src/system_stm32f7xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + 183:Src/system_stm32f7xx.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors. + 184:Src/system_stm32f7xx.c **** * + 185:Src/system_stm32f7xx.c **** * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + 186:Src/system_stm32f7xx.c **** * 16 MHz) but the real value may vary depending on the variations + 187:Src/system_stm32f7xx.c **** * in voltage and temperature. + 188:Src/system_stm32f7xx.c **** * + 189:Src/system_stm32f7xx.c **** * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + 190:Src/system_stm32f7xx.c **** * 25 MHz), user has to ensure that HSE_VALUE is same as the real + 191:Src/system_stm32f7xx.c **** * frequency of the crystal used. Otherwise, this function may + 192:Src/system_stm32f7xx.c **** * have wrong result. + 193:Src/system_stm32f7xx.c **** * + 194:Src/system_stm32f7xx.c **** * - The result of this function could be not correct when using fractional + 195:Src/system_stm32f7xx.c **** * value for HSE crystal. + 196:Src/system_stm32f7xx.c **** * + 197:Src/system_stm32f7xx.c **** * @param None + 198:Src/system_stm32f7xx.c **** * @retval None + 199:Src/system_stm32f7xx.c **** */ + 200:Src/system_stm32f7xx.c **** void SystemCoreClockUpdate(void) + 201:Src/system_stm32f7xx.c **** { + 58 .loc 1 201 1 is_stmt 1 view -0 + 59 .cfi_startproc + 60 @ args = 0, pretend = 0, frame = 0 + 61 @ frame_needed = 0, uses_anonymous_args = 0 + 62 @ link register save eliminated. + 202:Src/system_stm32f7xx.c **** uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + 63 .loc 1 202 3 view .LVU6 + 64 .LVL0: + 203:Src/system_stm32f7xx.c **** + 204:Src/system_stm32f7xx.c **** /* Get SYSCLK source -------------------------------------------------------*/ + 205:Src/system_stm32f7xx.c **** tmp = RCC->CFGR & RCC_CFGR_SWS; + 65 .loc 1 205 3 view .LVU7 + 66 .loc 1 205 12 is_stmt 0 view .LVU8 + 67 0000 224B ldr r3, .L11 + 68 0002 9B68 ldr r3, [r3, #8] + 69 .loc 1 205 7 view .LVU9 + 70 0004 03F00C03 and r3, r3, #12 + 71 .LVL1: + 206:Src/system_stm32f7xx.c **** + 207:Src/system_stm32f7xx.c **** switch (tmp) + 72 .loc 1 207 3 is_stmt 1 view .LVU10 + 73 0008 042B cmp r3, #4 + 74 000a 11D0 beq .L5 + 75 000c 082B cmp r3, #8 + 76 000e 13D0 beq .L6 + 77 0010 002B cmp r3, #0 + 78 0012 37D1 bne .L7 + 208:Src/system_stm32f7xx.c **** { + 209:Src/system_stm32f7xx.c **** case 0x00: /* HSI used as system clock source */ + 210:Src/system_stm32f7xx.c **** SystemCoreClock = HSI_VALUE; + ARM GAS /tmp/ccZPj2qA.s page 6 + + + 79 .loc 1 210 7 view .LVU11 + 80 .loc 1 210 23 is_stmt 0 view .LVU12 + 81 0014 1E4B ldr r3, .L11+4 + 82 .LVL2: + 83 .loc 1 210 23 view .LVU13 + 84 0016 1F4A ldr r2, .L11+8 + 85 0018 1A60 str r2, [r3] + 211:Src/system_stm32f7xx.c **** break; + 86 .loc 1 211 7 is_stmt 1 view .LVU14 + 87 .LVL3: + 88 .L8: + 212:Src/system_stm32f7xx.c **** case 0x04: /* HSE used as system clock source */ + 213:Src/system_stm32f7xx.c **** SystemCoreClock = HSE_VALUE; + 214:Src/system_stm32f7xx.c **** break; + 215:Src/system_stm32f7xx.c **** case 0x08: /* PLL used as system clock source */ + 216:Src/system_stm32f7xx.c **** + 217:Src/system_stm32f7xx.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + 218:Src/system_stm32f7xx.c **** SYSCLK = PLL_VCO / PLL_P + 219:Src/system_stm32f7xx.c **** */ + 220:Src/system_stm32f7xx.c **** pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + 221:Src/system_stm32f7xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + 222:Src/system_stm32f7xx.c **** + 223:Src/system_stm32f7xx.c **** if (pllsource != 0) + 224:Src/system_stm32f7xx.c **** { + 225:Src/system_stm32f7xx.c **** /* HSE used as PLL clock source */ + 226:Src/system_stm32f7xx.c **** pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + 227:Src/system_stm32f7xx.c **** } + 228:Src/system_stm32f7xx.c **** else + 229:Src/system_stm32f7xx.c **** { + 230:Src/system_stm32f7xx.c **** /* HSI used as PLL clock source */ + 231:Src/system_stm32f7xx.c **** pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + 232:Src/system_stm32f7xx.c **** } + 233:Src/system_stm32f7xx.c **** + 234:Src/system_stm32f7xx.c **** pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + 235:Src/system_stm32f7xx.c **** SystemCoreClock = pllvco/pllp; + 236:Src/system_stm32f7xx.c **** break; + 237:Src/system_stm32f7xx.c **** default: + 238:Src/system_stm32f7xx.c **** SystemCoreClock = HSI_VALUE; + 239:Src/system_stm32f7xx.c **** break; + 240:Src/system_stm32f7xx.c **** } + 241:Src/system_stm32f7xx.c **** /* Compute HCLK frequency --------------------------------------------------*/ + 242:Src/system_stm32f7xx.c **** /* Get HCLK prescaler */ + 243:Src/system_stm32f7xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + 89 .loc 1 243 3 view .LVU15 + 90 .loc 1 243 28 is_stmt 0 view .LVU16 + 91 001a 1C4B ldr r3, .L11 + 92 001c 9B68 ldr r3, [r3, #8] + 93 .loc 1 243 52 view .LVU17 + 94 001e C3F30313 ubfx r3, r3, #4, #4 + 95 .loc 1 243 22 view .LVU18 + 96 0022 1D4A ldr r2, .L11+12 + 97 0024 D15C ldrb r1, [r2, r3] @ zero_extendqisi2 + 98 .LVL4: + 244:Src/system_stm32f7xx.c **** /* HCLK frequency */ + 245:Src/system_stm32f7xx.c **** SystemCoreClock >>= tmp; + 99 .loc 1 245 3 is_stmt 1 view .LVU19 + 100 .loc 1 245 19 is_stmt 0 view .LVU20 + ARM GAS /tmp/ccZPj2qA.s page 7 + + + 101 0026 1A4A ldr r2, .L11+4 + 102 0028 1368 ldr r3, [r2] + 103 002a CB40 lsrs r3, r3, r1 + 104 002c 1360 str r3, [r2] + 246:Src/system_stm32f7xx.c **** } + 105 .loc 1 246 1 view .LVU21 + 106 002e 7047 bx lr + 107 .LVL5: + 108 .L5: + 213:Src/system_stm32f7xx.c **** break; + 109 .loc 1 213 7 is_stmt 1 view .LVU22 + 213:Src/system_stm32f7xx.c **** break; + 110 .loc 1 213 23 is_stmt 0 view .LVU23 + 111 0030 174B ldr r3, .L11+4 + 112 .LVL6: + 213:Src/system_stm32f7xx.c **** break; + 113 .loc 1 213 23 view .LVU24 + 114 0032 1A4A ldr r2, .L11+16 + 115 0034 1A60 str r2, [r3] + 214:Src/system_stm32f7xx.c **** case 0x08: /* PLL used as system clock source */ + 116 .loc 1 214 7 is_stmt 1 view .LVU25 + 117 0036 F0E7 b .L8 + 118 .LVL7: + 119 .L6: + 220:Src/system_stm32f7xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + 120 .loc 1 220 7 view .LVU26 + 220:Src/system_stm32f7xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + 121 .loc 1 220 23 is_stmt 0 view .LVU27 + 122 0038 144B ldr r3, .L11 + 123 .LVL8: + 220:Src/system_stm32f7xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + 124 .loc 1 220 23 view .LVU28 + 125 003a 5968 ldr r1, [r3, #4] + 126 .LVL9: + 221:Src/system_stm32f7xx.c **** + 127 .loc 1 221 7 is_stmt 1 view .LVU29 + 221:Src/system_stm32f7xx.c **** + 128 .loc 1 221 17 is_stmt 0 view .LVU30 + 129 003c 5A68 ldr r2, [r3, #4] + 221:Src/system_stm32f7xx.c **** + 130 .loc 1 221 12 view .LVU31 + 131 003e 02F03F02 and r2, r2, #63 + 132 .LVL10: + 223:Src/system_stm32f7xx.c **** { + 133 .loc 1 223 7 is_stmt 1 view .LVU32 + 223:Src/system_stm32f7xx.c **** { + 134 .loc 1 223 10 is_stmt 0 view .LVU33 + 135 0042 11F4800F tst r1, #4194304 + 136 0046 13D0 beq .L9 + 226:Src/system_stm32f7xx.c **** } + 137 .loc 1 226 9 is_stmt 1 view .LVU34 + 226:Src/system_stm32f7xx.c **** } + 138 .loc 1 226 29 is_stmt 0 view .LVU35 + 139 0048 144B ldr r3, .L11+16 + 140 004a B3FBF2F3 udiv r3, r3, r2 + 226:Src/system_stm32f7xx.c **** } + 141 .loc 1 226 44 view .LVU36 + ARM GAS /tmp/ccZPj2qA.s page 8 + + + 142 004e 0F4A ldr r2, .L11 + 143 .LVL11: + 226:Src/system_stm32f7xx.c **** } + 144 .loc 1 226 44 view .LVU37 + 145 0050 5268 ldr r2, [r2, #4] + 226:Src/system_stm32f7xx.c **** } + 146 .loc 1 226 74 view .LVU38 + 147 0052 C2F38812 ubfx r2, r2, #6, #9 + 226:Src/system_stm32f7xx.c **** } + 148 .loc 1 226 16 view .LVU39 + 149 0056 02FB03F3 mul r3, r2, r3 + 150 .LVL12: + 151 .L10: + 234:Src/system_stm32f7xx.c **** SystemCoreClock = pllvco/pllp; + 152 .loc 1 234 7 is_stmt 1 view .LVU40 + 234:Src/system_stm32f7xx.c **** SystemCoreClock = pllvco/pllp; + 153 .loc 1 234 20 is_stmt 0 view .LVU41 + 154 005a 0C4A ldr r2, .L11 + 155 005c 5268 ldr r2, [r2, #4] + 234:Src/system_stm32f7xx.c **** SystemCoreClock = pllvco/pllp; + 156 .loc 1 234 50 view .LVU42 + 157 005e C2F30142 ubfx r2, r2, #16, #2 + 234:Src/system_stm32f7xx.c **** SystemCoreClock = pllvco/pllp; + 158 .loc 1 234 56 view .LVU43 + 159 0062 0132 adds r2, r2, #1 + 234:Src/system_stm32f7xx.c **** SystemCoreClock = pllvco/pllp; + 160 .loc 1 234 12 view .LVU44 + 161 0064 5200 lsls r2, r2, #1 + 162 .LVL13: + 235:Src/system_stm32f7xx.c **** break; + 163 .loc 1 235 7 is_stmt 1 view .LVU45 + 235:Src/system_stm32f7xx.c **** break; + 164 .loc 1 235 31 is_stmt 0 view .LVU46 + 165 0066 B3FBF2F3 udiv r3, r3, r2 + 166 .LVL14: + 235:Src/system_stm32f7xx.c **** break; + 167 .loc 1 235 23 view .LVU47 + 168 006a 094A ldr r2, .L11+4 + 169 .LVL15: + 235:Src/system_stm32f7xx.c **** break; + 170 .loc 1 235 23 view .LVU48 + 171 006c 1360 str r3, [r2] + 236:Src/system_stm32f7xx.c **** default: + 172 .loc 1 236 7 is_stmt 1 view .LVU49 + 173 006e D4E7 b .L8 + 174 .LVL16: + 175 .L9: + 231:Src/system_stm32f7xx.c **** } + 176 .loc 1 231 9 view .LVU50 + 231:Src/system_stm32f7xx.c **** } + 177 .loc 1 231 29 is_stmt 0 view .LVU51 + 178 0070 084B ldr r3, .L11+8 + 179 0072 B3FBF2F3 udiv r3, r3, r2 + 231:Src/system_stm32f7xx.c **** } + 180 .loc 1 231 44 view .LVU52 + 181 0076 054A ldr r2, .L11 + 182 .LVL17: + ARM GAS /tmp/ccZPj2qA.s page 9 + + + 231:Src/system_stm32f7xx.c **** } + 183 .loc 1 231 44 view .LVU53 + 184 0078 5268 ldr r2, [r2, #4] + 231:Src/system_stm32f7xx.c **** } + 185 .loc 1 231 74 view .LVU54 + 186 007a C2F38812 ubfx r2, r2, #6, #9 + 231:Src/system_stm32f7xx.c **** } + 187 .loc 1 231 16 view .LVU55 + 188 007e 02FB03F3 mul r3, r2, r3 + 189 .LVL18: + 231:Src/system_stm32f7xx.c **** } + 190 .loc 1 231 16 view .LVU56 + 191 0082 EAE7 b .L10 + 192 .LVL19: + 193 .L7: + 238:Src/system_stm32f7xx.c **** break; + 194 .loc 1 238 7 is_stmt 1 view .LVU57 + 238:Src/system_stm32f7xx.c **** break; + 195 .loc 1 238 23 is_stmt 0 view .LVU58 + 196 0084 024B ldr r3, .L11+4 + 197 .LVL20: + 238:Src/system_stm32f7xx.c **** break; + 198 .loc 1 238 23 view .LVU59 + 199 0086 034A ldr r2, .L11+8 + 200 0088 1A60 str r2, [r3] + 239:Src/system_stm32f7xx.c **** } + 201 .loc 1 239 7 is_stmt 1 view .LVU60 + 202 008a C6E7 b .L8 + 203 .L12: + 204 .align 2 + 205 .L11: + 206 008c 00380240 .word 1073887232 + 207 0090 00000000 .word SystemCoreClock + 208 0094 0024F400 .word 16000000 + 209 0098 00000000 .word AHBPrescTable + 210 009c 40787D01 .word 25000000 + 211 .cfi_endproc + 212 .LFE142: + 214 .global APBPrescTable + 215 .section .rodata.APBPrescTable,"a" + 216 .align 2 + 219 APBPrescTable: + 220 0000 00000000 .ascii "\000\000\000\000\001\002\003\004" + 220 01020304 + 221 .global AHBPrescTable + 222 .section .rodata.AHBPrescTable,"a" + 223 .align 2 + 226 AHBPrescTable: + 227 0000 00000000 .ascii "\000\000\000\000\000\000\000\000\001\002\003\004\006" + 227 00000000 + 227 01020304 + 227 06 + 228 000d 070809 .ascii "\007\010\011" + 229 .global SystemCoreClock + 230 .section .data.SystemCoreClock,"aw" + 231 .align 2 + 234 SystemCoreClock: + ARM GAS /tmp/ccZPj2qA.s page 10 + + + 235 0000 0024F400 .word 16000000 + 236 .text + 237 .Letext0: + 238 .file 2 "/usr/lib/gcc/arm-none-eabi/13.2.1/include/stdint.h" + 239 .file 3 "Drivers/CMSIS/Include/core_cm7.h" + 240 .file 4 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h" + 241 .file 5 "Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h" + ARM GAS /tmp/ccZPj2qA.s page 11 + + +DEFINED SYMBOLS + *ABS*:00000000 system_stm32f7xx.c + /tmp/ccZPj2qA.s:20 .text.SystemInit:00000000 $t + /tmp/ccZPj2qA.s:26 .text.SystemInit:00000000 SystemInit + /tmp/ccZPj2qA.s:45 .text.SystemInit:00000010 $d + /tmp/ccZPj2qA.s:50 .text.SystemCoreClockUpdate:00000000 $t + /tmp/ccZPj2qA.s:56 .text.SystemCoreClockUpdate:00000000 SystemCoreClockUpdate + /tmp/ccZPj2qA.s:206 .text.SystemCoreClockUpdate:0000008c $d + /tmp/ccZPj2qA.s:234 .data.SystemCoreClock:00000000 SystemCoreClock + /tmp/ccZPj2qA.s:226 .rodata.AHBPrescTable:00000000 AHBPrescTable + /tmp/ccZPj2qA.s:219 .rodata.APBPrescTable:00000000 APBPrescTable + /tmp/ccZPj2qA.s:216 .rodata.APBPrescTable:00000000 $d + /tmp/ccZPj2qA.s:223 .rodata.AHBPrescTable:00000000 $d + /tmp/ccZPj2qA.s:231 .data.SystemCoreClock:00000000 $d + +NO UNDEFINED SYMBOLS diff --git a/build/system_stm32f7xx.o b/build/system_stm32f7xx.o new file mode 100644 index 0000000000000000000000000000000000000000..1a544bce35f6261cdc5212807b07660594bb9e31 GIT binary patch literal 8312 zcma)A4RDmldEWhgbbHcCaFRfPu`O9LkYJsplR$t);dDaikYo#;z)egdPN&mPD(S@O zMC8=?C-vBF$KyDOTikIvC{0?olTI2YnK4Hw*NWA`-u2?; z2kWDkChg;dlRL#b;*A?RA0M&j0=Bb0cv7t|J1N#TpSrH|`dzE`uO`jET(rxs-F0f; zs$FFx&uuT;Ke@A_a~0|4&Xsq5V&sz}*4#ELcEXWWgDtEz7MY#&X;<0Oh_wU{9kST5&spvx9Cf zZkANfX%Al?Wv~Y+u+_BkZrF^%MmssaYEoLt_b!=XAJS6 zRPV#$r?PY}rLe0XlIk1C@uso3$58?N6mIW{4j+>NtpV zhIqzNg^2N1t|NB!^Ny;;llZyGa?(-dusCllUUt;2u=pQiaoSNEK)h{;*B$jFvbIqo9XNX5#wE-6I8{#ony#(R|Lwvx-p zWAQhxDBMj9CU()IR4Eb;R#YKYlA@MrQVRDnkq!v0xxr{`;g(X}0iiW5M&k(gCTKtu zVnJgf=x8kCv1@r>PLFZWa!F3U-^i{A93p@FinJdm)WN=Hlu{IbhX%pf97GN&3-=Nn zGukD>JxcZBhlzAMPJ+H1bkaLuuSgMlM%sWQ|BaD1skh<( zzb0Rcx*zucXY||EYq0;&$ZdLAyTayt9g56_D{UU19`!8ZSw`+t`=Pgu{QG**yN=EM z+oy(M?;8Dn^`~fmfsqIG0(X5T--xP3JZ1Eg{%D-W+i&EoUhZz8v7b@5z`iJ_*E?4j zM8FWVbB!Zou_3T?!J@Lhks@#&OwhJJz^E(dJ2Xg3FeT-k0hhv&^dm@z zf-L+;470wF4?)8izFGS z;+z|av9e9Hdi+GFoIXbsN*ODIX;Br$sw<+db1LmaOS8$7d0U``My7<46wN1D(j<14 z<=SRZilrgBEnphEHV~Aha(m(7)&Pcq8YchIP~-(pn;X1UN>Q6upQ#OBZMYU9NV|HL8WQNCQM#pEw}e zZ){j~KGuALYP1L4goB$dn8zry`aXaADE^;lq-}AU zj4XMjq?q=5eaa_R#xqG#H$9c98yg*{8%`$c5}EPZiS$IOHkB9{t!roug+mQ>qZ7%o z>A{p}%ZwgOWv1$)-SJqwF7}aZTk7CwGF2DvqhEJpxV?F1CT}UG?wHD^#`~wT?EcT*^5TIF6(L`4X0 zRj&VvM{7e@&yHJqMNd~(w0&oN_>d%UJ zw6(wQj>(kHiBx3WlSxe_`w|0V#8TUIOQKz|wq6nMqZ2`_tv}MleMLW$h{K{X)qP??`aL^av=^$3)_*?#iFrDSJxh7 z*WH~Q8=Fc`XOg<9jpzVbkY4B+KW+;(N^=A@;iA>$j)I=(i$fh&>J<--h#>DhbrH8VgO=MEJUJjdMoX4+0;z! zcr(e_k?HXP!Xe^^CJ%0?9cl!v}(T&Tb#u{qF zA6wkg+-dAXDpFW?mIR9Pr!(xac*U608su5JA`Ns);GH4lTB^FuJ8HW{L9wsfZxyOi zr(761&nJcjqiw zv#u55G2nIdSq(`4GckuP>NZ9Sh!Fv<1d@RMS#-d?iTOsxEsPPycE(RLrWkQ>MZC{5 z{xRcW#wQq`WPF8ltcjJp{Vj0YI+W&9%JR~e5o z9%DSkc!u!;qofIm_5>NL7#kQPjJp{Vj0YI+W&9%JQO0A8FEYN#c!|-aC5XHgjB6O1 zfV5s(fwW$FfY;LpE!KY;NQ-!Y@pC}hUhZQ2BOt|nnB^}q9%lY8S^jIrZ!rH|mj99Q zpP4_w@(YZwF#ls9jo}$ay`HIE*yGW@6^yGHs~Oiah8Xd0751AM@v#$f8)FA!l5vGseGQ{3;{9Y#{IV8Gp$5EaNH0R~TPse1q{a<8K%ptY?ac zPiVlUjOC0~j5jjkiwW$ajGc`5fDHaN#@iVO7>5|g84obhG!qtWuKIb+=a|O_8|20N#v*6!PjPBkUdMhSGR)3!a41;6=Y6?4?udbc4^`fNyhZ&uO~KI*oEi}i?frYY zj1N`CFNplOhcMM+i|kfVkb8~Nqr<-B&HEHBNcuRe^WrpW@}BhgP*waned1h)3KtXl zd6K>HdZ+_f`XDbpAg}VH$s6bi9_ z$329pULc(}-h&j#%olpy<>TRF8hq;MLV279BZg#Lpu-hdWOtStg|%Rcv0KS@h7ZtL z)x-v8LN6mbZ~Gqe^p{@0`Sz_LJDMJoCSD80!#mFu_A}s<3e8aA2}&r bzD&~m8_rAfV~a8O+I^4Ox6vdcovHpm`mtHG literal 0 HcmV?d00001